\n implicit val sourceInfo: SourceInfo = c.info\n c.cloneProto.map { cp =>\n // If the child is a clone, then recursively set cloneProto of its children as well\n def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {\n require(bases.size == clones.size)\n (bases.zip(clones)).map { case (l, r) =>\n require(l.getClass == r.getClass, s\"Cloned children class mismatch ${l.name} != ${r.name}\")\n l.cloneProto = Some(r)\n assignCloneProtos(l.children, r.children)\n }\n }\n assignCloneProtos(c.children, cp.children)\n // Clone the child module as a record, and get its [[AutoBundle]]\n val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)\n val clonedAuto = clone(\"auto\").asInstanceOf[AutoBundle]\n // Get the empty [[Dangle]]'s of the cloned child\n val rawDangles = c.cloneDangles()\n require(rawDangles.size == clonedAuto.elements.size)\n // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s\n val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }\n dangles\n }.getOrElse {\n // For non-clones, instantiate the child module\n val mod = try {\n Module(c.module)\n } catch {\n case e: ChiselException => {\n println(s\"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}\")\n throw e\n }\n }\n mod.dangles\n }\n }\n\n // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].\n // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.\n val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())\n // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]\n val allDangles = nodeDangles ++ childDangles\n // Group [[allDangles]] by their [[source]].\n val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)\n // For each [[source]] set of [[Dangle]]s of size 2, ensure that these\n // can be connected as a source-sink pair (have opposite flipped value).\n // Make the connection and mark them as [[done]].\n val done = Set() ++ pairing.values.filter(_.size == 2).map {\n case Seq(a, b) =>\n require(a.flipped != b.flipped)\n // @todo <> in chisel3 makes directionless connection.\n if (a.flipped) {\n a.data <> b.data\n } else {\n b.data <> a.data\n }\n a.source\n case _ => None\n }\n // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.\n val forward = allDangles.filter(d => !done(d.source))\n // Generate [[AutoBundle]] IO from [[forward]].\n val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))\n // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]\n val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>\n if (d.flipped) {\n d.data <> io\n } else {\n io <> d.data\n }\n d.copy(dataOpt = Some(io), name = wrapper.suggestedName + \"_\" + d.name)\n }\n // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].\n wrapper.inModuleBody.reverse.foreach {\n _()\n }\n\n if (wrapper.shouldBeInlined) {\n chisel3.experimental.annotate(new ChiselAnnotation {\n def toFirrtl = InlineAnnotation(toNamed)\n })\n }\n\n // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].\n (auto, dangles)\n }\n}\n\n/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].\n *\n * @param wrapper\n * the [[LazyModule]] from which the `.module` call is being made.\n */\nclass LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {\n\n /** Instantiate hardware of this `Module`. */\n val (auto, dangles) = instantiate()\n}\n\n/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].\n *\n * @param wrapper\n * the [[LazyModule]] from which the `.module` call is being made.\n */\nclass LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {\n // These wires are the default clock+reset for all LazyModule children.\n // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the\n // [[LazyRawModuleImp]] children.\n // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.\n /** drive clock explicitly. */\n val childClock: Clock = Wire(Clock())\n\n /** drive reset explicitly. */\n val childReset: Reset = Wire(Reset())\n // the default is that these are disabled\n childClock := false.B.asClock\n childReset := chisel3.DontCare\n\n def provideImplicitClockToLazyChildren: Boolean = false\n val (auto, dangles) =\n if (provideImplicitClockToLazyChildren) {\n withClockAndReset(childClock, childReset) { instantiate() }\n } else {\n instantiate()\n }\n}\nFile Debug.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.devices.debug\n\n\nimport chisel3._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config._\nimport org.chipsalliance.diplomacy.lazymodule._\n\nimport freechips.rocketchip.amba.apb.{APBFanout, APBToTL}\nimport freechips.rocketchip.devices.debug.systembusaccess.{SBToTL, SystemBusAccessModule}\nimport freechips.rocketchip.devices.tilelink.{DevNullParams, TLBusBypass, TLError}\nimport freechips.rocketchip.diplomacy.{AddressSet, BufferParams}\nimport freechips.rocketchip.resources.{Description, Device, Resource, ResourceBindings, ResourceString, SimpleDevice}\nimport freechips.rocketchip.interrupts.{IntNexusNode, IntSinkParameters, IntSinkPortParameters, IntSourceParameters, IntSourcePortParameters, IntSyncCrossingSource, IntSyncIdentityNode}\nimport freechips.rocketchip.regmapper.{RegField, RegFieldAccessType, RegFieldDesc, RegFieldGroup, RegFieldWrType, RegReadFn, RegWriteFn}\nimport freechips.rocketchip.rocket.{CSRs, Instructions}\nimport freechips.rocketchip.tile.MaxHartIdBits\nimport freechips.rocketchip.tilelink.{TLAsyncCrossingSink, TLAsyncCrossingSource, TLBuffer, TLRegisterNode, TLXbar}\nimport freechips.rocketchip.util.{Annotated, AsyncBundle, AsyncQueueParams, AsyncResetSynchronizerShiftReg, FromAsyncBundle, ParameterizedBundle, ResetSynchronizerShiftReg, ToAsyncBundle}\n\nimport freechips.rocketchip.util.SeqBoolBitwiseOps\nimport freechips.rocketchip.util.SeqToAugmentedSeq\nimport freechips.rocketchip.util.BooleanToAugmentedBoolean\n\nobject DsbBusConsts {\n def sbAddrWidth = 12\n def sbIdWidth = 10\n}\n\nobject DsbRegAddrs{\n\n // These are used by the ROM.\n def HALTED = 0x100\n def GOING = 0x104\n def RESUMING = 0x108\n def EXCEPTION = 0x10C\n\n def WHERETO = 0x300\n // This needs to be aligned for up to lq/sq\n\n \n // This shows up in HartInfo, and needs to be aligned\n // to enable up to LQ/SQ instructions.\n def DATA = 0x380\n\n // We want DATA to immediately follow PROGBUF so that we can\n // use them interchangeably. Leave another slot if there is an\n // implicit ebreak.\n def PROGBUF(cfg:DebugModuleParams) = {\n val tmp = DATA - (cfg.nProgramBufferWords * 4)\n if (cfg.hasImplicitEbreak) (tmp - 4) else tmp\n }\n // This is unused if hasImpEbreak is false, and just points to the end of the PROGBUF.\n def IMPEBREAK(cfg: DebugModuleParams) = { DATA - 4 }\n\n // We want abstract to be immediately before PROGBUF\n // because we auto-generate 2 (or 5) instructions.\n def ABSTRACT(cfg:DebugModuleParams) = PROGBUF(cfg) - (cfg.nAbstractInstructions * 4)\n\n def FLAGS = 0x400\n def ROMBASE = 0x800\n \n}\n\n/** Enumerations used both in the hardware\n * and in the configuration specification.\n */\n\nobject DebugModuleAccessType extends scala.Enumeration {\n type DebugModuleAccessType = Value\n val Access8Bit, Access16Bit, Access32Bit, Access64Bit, Access128Bit = Value\n}\n\nobject DebugAbstractCommandError extends scala.Enumeration {\n type DebugAbstractCommandError = Value\n val Success, ErrBusy, ErrNotSupported, ErrException, ErrHaltResume = Value\n}\n\nobject DebugAbstractCommandType extends scala.Enumeration {\n type DebugAbstractCommandType = Value\n val AccessRegister, QuickAccess = Value\n}\n\n/** Parameters exposed to the top-level design, set based on\n * external requirements, etc.\n *\n * This object checks that the parameters conform to the \n * full specification. The implementation which receives this\n * object can perform more checks on what that implementation\n * actually supports.\n * @param nComponents Number of components to support debugging.\n * @param baseAddress Base offest for debugEntry and debugException\n * @param nDMIAddrSize Size of the Debug Bus Address\n * @param nAbstractDataWords Number of 32-bit words for Abstract Commands\n * @param nProgamBufferWords Number of 32-bit words for Program Buffer\n * @param hasBusMaster Whether or not a bus master should be included\n * @param clockGate Whether or not to use dmactive as the clockgate for debug module\n * @param maxSupportedSBAccess Maximum transaction size supported by System Bus Access logic.\n * @param supportQuickAccess Whether or not to support the quick access command.\n * @param supportHartArray Whether or not to implement the hart array register (if >1 hart).\n * @param nHaltGroups Number of halt groups\n * @param nExtTriggers Number of external triggers\n * @param hasHartResets Feature to reset all the currently selected harts\n * @param hasImplicitEbreak There is an additional RO program buffer word containing an ebreak\n * @param crossingHasSafeReset Include \"safe\" logic in Async Crossings so that only one side needs to be reset.\n */\n\ncase class DebugModuleParams (\n baseAddress : BigInt = BigInt(0),\n nDMIAddrSize : Int = 7,\n nProgramBufferWords: Int = 16,\n nAbstractDataWords : Int = 4,\n nScratch : Int = 1,\n hasBusMaster : Boolean = false,\n clockGate : Boolean = true,\n maxSupportedSBAccess : Int = 32,\n supportQuickAccess : Boolean = false,\n supportHartArray : Boolean = true,\n nHaltGroups : Int = 1,\n nExtTriggers : Int = 0,\n hasHartResets : Boolean = false,\n hasImplicitEbreak : Boolean = false,\n hasAuthentication : Boolean = false,\n crossingHasSafeReset : Boolean = true\n) {\n\n require ((nDMIAddrSize >= 7) && (nDMIAddrSize <= 32), s\"Legal DMIAddrSize is 7-32, not ${nDMIAddrSize}\")\n\n require ((nAbstractDataWords > 0) && (nAbstractDataWords <= 16), s\"Legal nAbstractDataWords is 0-16, not ${nAbstractDataWords}\")\n require ((nProgramBufferWords >= 0) && (nProgramBufferWords <= 16), s\"Legal nProgramBufferWords is 0-16, not ${nProgramBufferWords}\")\n\n require (nHaltGroups < 32, s\"Legal nHaltGroups is 0-31, not ${nHaltGroups}\")\n require (nExtTriggers <= 16, s\"Legal nExtTriggers is 0-16, not ${nExtTriggers}\")\n\n if (supportQuickAccess) {\n // TODO: Check that quick access requirements are met.\n }\n\n def address = AddressSet(baseAddress, 0xFFF)\n /** the base address of DM */\n def atzero = (baseAddress == 0)\n /** The number of generated instructions\n *\n * When the base address is not zero, we need more instruction also,\n * more dscratch registers) to load/store memory mapped data register\n * because they may no longer be directly addressible with x0 + 12-bit imm\n */\n def nAbstractInstructions = if (atzero) 2 else 5\n def debugEntry: BigInt = baseAddress + 0x800\n def debugException: BigInt = baseAddress + 0x808\n def nDscratch: Int = if (atzero) 1 else 2\n}\n\nobject DefaultDebugModuleParams {\n\n def apply(xlen:Int /*TODO , val configStringAddr: Int*/): DebugModuleParams = {\n new DebugModuleParams().copy(\n nAbstractDataWords = (if (xlen == 32) 1 else if (xlen == 64) 2 else 4),\n maxSupportedSBAccess = xlen\n )\n }\n}\n\ncase object DebugModuleKey extends Field[Option[DebugModuleParams]](Some(DebugModuleParams()))\n\n/** Functional parameters exposed to the design configuration.\n *\n * hartIdToHartSel: For systems where hart ids are not 1:1 with hartsel, provide the mapping.\n * hartSelToHartId: Provide inverse mapping of the above\n */\ncase class DebugModuleHartSelFuncs (\n hartIdToHartSel : (UInt) => UInt = (x:UInt) => x,\n hartSelToHartId : (UInt) => UInt = (x:UInt) => x\n)\n\ncase object DebugModuleHartSelKey extends Field(DebugModuleHartSelFuncs())\n\nclass DebugExtTriggerOut (val nExtTriggers: Int) extends Bundle {\n val req = Output(UInt(nExtTriggers.W))\n val ack = Input(UInt(nExtTriggers.W))\n}\n\nclass DebugExtTriggerIn (val nExtTriggers: Int) extends Bundle {\n val req = Input(UInt(nExtTriggers.W))\n val ack = Output(UInt(nExtTriggers.W))\n}\n\nclass DebugExtTriggerIO () (implicit val p: Parameters) extends ParameterizedBundle()(p) {\n val out = new DebugExtTriggerOut(p(DebugModuleKey).get.nExtTriggers)\n val in = new DebugExtTriggerIn (p(DebugModuleKey).get.nExtTriggers)\n}\n\nclass DebugAuthenticationIO () (implicit val p: Parameters) extends ParameterizedBundle()(p) {\n val dmactive = Output(Bool())\n val dmAuthWrite = Output(Bool())\n val dmAuthRead = Output(Bool())\n val dmAuthWdata = Output(UInt(32.W))\n val dmAuthBusy = Input(Bool())\n val dmAuthRdata = Input(UInt(32.W))\n val dmAuthenticated = Input(Bool())\n}\n\n// *****************************************\n// Module Interfaces\n// \n// *****************************************\n\n/** Control signals for Inner, generated in Outer\n * {{{\n * run control: resumreq, ackhavereset, halt-on-reset mask\n * hart select: hasel, hartsel and the hart array mask\n * }}}\n */\nclass DebugInternalBundle (val nComponents: Int)(implicit val p: Parameters) extends ParameterizedBundle()(p) {\n /** resume request */\n val resumereq = Bool()\n /** hart select */\n val hartsel = UInt(10.W)\n /** reset acknowledge */\n val ackhavereset = Bool()\n /** hart array enable */\n val hasel = Bool()\n /** hart array mask */\n val hamask = Vec(nComponents, Bool())\n /** halt-on-reset mask */\n val hrmask = Vec(nComponents, Bool())\n}\n\n/** structure for top-level Debug Module signals which aren't the bus interfaces. */\nclass DebugCtrlBundle (nComponents: Int)(implicit val p: Parameters) extends ParameterizedBundle()(p) {\n /** debug availability status for all harts */\n val debugUnavail = Input(Vec(nComponents, Bool()))\n /** reset signal\n *\n * for every part of the hardware platform,\n * including every hart, except for the DM and any\n * logic required to access the DM\n */\n val ndreset = Output(Bool())\n /** reset signal for the DM itself */\n val dmactive = Output(Bool())\n /** dmactive acknowlege */\n val dmactiveAck = Input(Bool())\n}\n\n// *****************************************\n// Debug Module \n// \n// *****************************************\n\n/** Parameterized version of the Debug Module defined in the\n * RISC-V Debug Specification \n * \n * DebugModule is a slave to two asynchronous masters:\n * The Debug Bus (DMI) -- This is driven by an external debugger\n * \n * The System Bus -- This services requests from the cores. Generally\n * this interface should only be active at the request\n * of the debugger, but the Debug Module may also \n * provide the default MTVEC since it is mapped\n * to address 0x0.\n * \n * DebugModule is responsible for control registers and RAM, and\n * Debug ROM. It runs partially off of the dmiClk (e.g. TCK) and\n * the TL clock. Therefore, it is divided into \"Outer\" portion (running\n * off dmiClock and dmiReset) and \"Inner\" (running off tl_clock and tl_reset).\n * This allows DMCONTROL.haltreq, hartsel, hasel, hawindowsel, hawindow, dmactive,\n * and ndreset to be modified even while the Core is in reset or not being clocked.\n * Not all reads from the Debugger to the Debug Module will actually complete\n * in these scenarios either, they will just block until tl_clock and tl_reset\n * allow them to complete. This is not strictly necessary for \n * proper debugger functionality.\n */\n\n// Local reg mapper function : Notify when written, but give the value as well. \nobject WNotifyWire {\n def apply(n: Int, value: UInt, set: Bool, name: String, desc: String) : RegField = {\n RegField(n, 0.U, RegWriteFn((valid, data) => {\n set := valid\n value := data\n true.B\n }), Some(RegFieldDesc(name = name, desc = desc,\n access = RegFieldAccessType.W)))\n }\n}\n\n// Local reg mapper function : Notify when accessed either as read or write.\nobject RWNotify {\n def apply (n: Int, rVal: UInt, wVal: UInt, rNotify: Bool, wNotify: Bool, desc: Option[RegFieldDesc] = None): RegField = {\n RegField(n,\n RegReadFn ((ready) => {rNotify := ready ; (true.B, rVal)}),\n RegWriteFn((valid, data) => {\n wNotify := valid\n when (valid) {wVal := data}\n true.B\n }\n ), desc)\n }\n}\n\n// Local reg mapper function : Notify with value when written, take read input as presented.\n// This allows checking or correcting the write value before storing it in the register field.\nobject WNotifyVal {\n def apply(n: Int, rVal: UInt, wVal: UInt, wNotify: Bool, desc: RegFieldDesc): RegField = {\n RegField(n, rVal, RegWriteFn((valid, data) => {\n wNotify := valid\n wVal := data\n true.B\n }\n ), desc)\n }\n}\n\nclass TLDebugModuleOuter(device: Device)(implicit p: Parameters) extends LazyModule {\n\n // For Shorter Register Names\n import DMI_RegAddrs._\n\n val cfg = p(DebugModuleKey).get\n\n val intnode = IntNexusNode(\n sourceFn = { _ => IntSourcePortParameters(Seq(IntSourceParameters(1, Seq(Resource(device, \"int\"))))) },\n sinkFn = { _ => IntSinkPortParameters(Seq(IntSinkParameters())) },\n outputRequiresInput = false)\n\n val dmiNode = TLRegisterNode (\n address = AddressSet.misaligned(DMI_DMCONTROL << 2, 4) ++\n AddressSet.misaligned(DMI_HARTINFO << 2, 4) ++\n AddressSet.misaligned(DMI_HAWINDOWSEL << 2, 4) ++\n AddressSet.misaligned(DMI_HAWINDOW << 2, 4),\n device = device,\n beatBytes = 4,\n executable = false\n )\n\n lazy val module = new Impl\n class Impl extends LazyModuleImp(this) {\n require (intnode.edges.in.size == 0, \"Debug Module does not accept interrupts\")\n\n val nComponents = intnode.out.size\n def getNComponents = () => nComponents\n\n val supportHartArray = cfg.supportHartArray && (nComponents > 1) // no hart array if only one hart\n\n val io = IO(new Bundle {\n /** structure for top-level Debug Module signals which aren't the bus interfaces. */\n val ctrl = (new DebugCtrlBundle(nComponents))\n /** control signals for Inner, generated in Outer */\n val innerCtrl = new DecoupledIO(new DebugInternalBundle(nComponents))\n /** debug interruption from Inner to Outer\n *\n * contains 2 type of debug interruption causes:\n * - halt group\n * - halt-on-reset\n */\n val hgDebugInt = Input(Vec(nComponents, Bool()))\n /** hart reset request to core */\n val hartResetReq = cfg.hasHartResets.option(Output(Vec(nComponents, Bool())))\n /** authentication support */\n val dmAuthenticated = cfg.hasAuthentication.option(Input(Bool()))\n })\n\n val omRegMap = withReset(reset.asAsyncReset) {\n // FIXME: Instead of casting reset to ensure it is Async, assert/require reset.Type == AsyncReset (when this feature is available)\n\n val dmAuthenticated = io.dmAuthenticated.map( dma =>\n ResetSynchronizerShiftReg(in=dma, sync=3, name=Some(\"dmAuthenticated_sync\"))).getOrElse(true.B)\n\n //----DMCONTROL (The whole point of 'Outer' is to maintain this register on dmiClock (e.g. TCK) domain, so that it\n // can be written even if 'Inner' is not being clocked or is in reset. This allows halting\n // harts while the rest of the system is in reset. It doesn't really allow any other\n // register accesses, which will keep returning 'busy' to the debugger interface.\n\n val DMCONTROLReset = WireInit(0.U.asTypeOf(new DMCONTROLFields()))\n val DMCONTROLNxt = WireInit(0.U.asTypeOf(new DMCONTROLFields()))\n val DMCONTROLReg = RegNext(next=DMCONTROLNxt, init=0.U.asTypeOf(DMCONTROLNxt)).suggestName(\"DMCONTROLReg\")\n\n val hartsel_mask = if (nComponents > 1) ((1 << p(MaxHartIdBits)) - 1).U else 0.U\n val DMCONTROLWrData = WireInit(0.U.asTypeOf(new DMCONTROLFields()))\n\n val dmactiveWrEn = WireInit(false.B)\n val ndmresetWrEn = WireInit(false.B)\n val clrresethaltreqWrEn = WireInit(false.B)\n val setresethaltreqWrEn = WireInit(false.B)\n val hartselloWrEn = WireInit(false.B)\n val haselWrEn = WireInit(false.B)\n val ackhaveresetWrEn = WireInit(false.B)\n val hartresetWrEn = WireInit(false.B)\n val resumereqWrEn = WireInit(false.B)\n val haltreqWrEn = WireInit(false.B)\n\n val dmactive = DMCONTROLReg.dmactive\n\n DMCONTROLNxt := DMCONTROLReg\n when (~dmactive) {\n DMCONTROLNxt := DMCONTROLReset\n } .otherwise {\n when (dmAuthenticated && ndmresetWrEn) { DMCONTROLNxt.ndmreset := DMCONTROLWrData.ndmreset }\n when (dmAuthenticated && hartselloWrEn) { DMCONTROLNxt.hartsello := DMCONTROLWrData.hartsello & hartsel_mask}\n when (dmAuthenticated && haselWrEn) { DMCONTROLNxt.hasel := DMCONTROLWrData.hasel }\n when (dmAuthenticated && hartresetWrEn) { DMCONTROLNxt.hartreset := DMCONTROLWrData.hartreset }\n when (dmAuthenticated && haltreqWrEn) { DMCONTROLNxt.haltreq := DMCONTROLWrData.haltreq }\n }\n\n // Put this last to override its own effects.\n when (dmactiveWrEn) {\n DMCONTROLNxt.dmactive := DMCONTROLWrData.dmactive\n }\n\n //----HARTINFO\n // DATA registers are mapped to memory. The dataaddr field of HARTINFO has only\n // 12 bits and assumes the DM base is 0. If not at 0, then HARTINFO reads as 0\n // (implying nonexistence according to the Debug Spec).\n\n val HARTINFORdData = WireInit(0.U.asTypeOf(new HARTINFOFields()))\n if (cfg.atzero) when (dmAuthenticated) {\n HARTINFORdData.dataaccess := true.B\n HARTINFORdData.datasize := cfg.nAbstractDataWords.U\n HARTINFORdData.dataaddr := DsbRegAddrs.DATA.U\n HARTINFORdData.nscratch := cfg.nScratch.U\n }\n\n //--------------------------------------------------------------\n // Hart array mask and window\n // hamask is hart array mask(1 bit per component), which doesn't include the hart selected by dmcontrol.hartsello\n // HAWINDOWSEL selects a 32-bit slice of HAMASK to be visible for read/write in HAWINDOW\n //--------------------------------------------------------------\n\n val hamask = WireInit(VecInit(Seq.fill(nComponents) {false.B} ))\n def haWindowSize = 32\n\n // The following need to be declared even if supportHartArray is false due to reference\n // at compile time by dmiNode.regmap\n val HAWINDOWSELWrData = WireInit(0.U.asTypeOf(new HAWINDOWSELFields()))\n val HAWINDOWSELWrEn = WireInit(false.B)\n\n val HAWINDOWRdData = WireInit(0.U.asTypeOf(new HAWINDOWFields()))\n val HAWINDOWWrData = WireInit(0.U.asTypeOf(new HAWINDOWFields()))\n val HAWINDOWWrEn = WireInit(false.B)\n\n /** whether the hart is selected */\n def hartSelected(hart: Int): Bool = {\n ((io.innerCtrl.bits.hartsel === hart.U) ||\n (if (supportHartArray) io.innerCtrl.bits.hasel && io.innerCtrl.bits.hamask(hart) else false.B))\n }\n\n val HAWINDOWSELNxt = WireInit(0.U.asTypeOf(new HAWINDOWSELFields()))\n val HAWINDOWSELReg = RegNext(next=HAWINDOWSELNxt, init=0.U.asTypeOf(HAWINDOWSELNxt))\n\n if (supportHartArray) {\n val HAWINDOWSELReset = WireInit(0.U.asTypeOf(new HAWINDOWSELFields()))\n\n HAWINDOWSELNxt := HAWINDOWSELReg\n when (~dmactive || ~dmAuthenticated) {\n HAWINDOWSELNxt := HAWINDOWSELReset\n } .otherwise {\n when (HAWINDOWSELWrEn) {\n // Unneeded upper bits of HAWINDOWSEL are tied to 0. Entire register is 0 if all harts fit in one window\n if (nComponents > haWindowSize) {\n HAWINDOWSELNxt.hawindowsel := HAWINDOWSELWrData.hawindowsel & ((1 << (log2Up(nComponents) - 5)) - 1).U\n } else {\n HAWINDOWSELNxt.hawindowsel := 0.U\n }\n }\n }\n val numHAMASKSlices = ((nComponents - 1)/haWindowSize)+1\n HAWINDOWRdData.maskdata := 0.U // default, overridden below\n // for each slice,use a hamaskReg to store the selection info\n for (ii <- 0 until numHAMASKSlices) {\n val sliceMask = if (nComponents > ((ii*haWindowSize) + haWindowSize-1)) (BigInt(1) << haWindowSize) - 1 // All harts in this slice exist\n else (BigInt(1)<<(nComponents - (ii*haWindowSize))) - 1 // Partial last slice\n val HAMASKRst = WireInit(0.U.asTypeOf(new HAWINDOWFields()))\n val HAMASKNxt = WireInit(0.U.asTypeOf(new HAWINDOWFields()))\n val HAMASKReg = RegNext(next=HAMASKNxt, init=0.U.asTypeOf(HAMASKNxt))\n\n when (ii.U === HAWINDOWSELReg.hawindowsel) {\n HAWINDOWRdData.maskdata := HAMASKReg.asUInt & sliceMask.U\n }\n\n HAMASKNxt.maskdata := HAMASKReg.asUInt\n when (~dmactive || ~dmAuthenticated) {\n HAMASKNxt := HAMASKRst\n }.otherwise {\n when (HAWINDOWWrEn && (ii.U === HAWINDOWSELReg.hawindowsel)) {\n HAMASKNxt.maskdata := HAWINDOWWrData.maskdata\n }\n }\n \n // drive each slice of hamask with stored HAMASKReg or with new value being written\n for (jj <- 0 until haWindowSize) {\n if (((ii*haWindowSize) + jj) < nComponents) {\n val tempWrData = HAWINDOWWrData.maskdata.asBools\n val tempMaskReg = HAMASKReg.asUInt.asBools\n when (HAWINDOWWrEn && (ii.U === HAWINDOWSELReg.hawindowsel)) {\n hamask(ii*haWindowSize + jj) := tempWrData(jj)\n }.otherwise {\n hamask(ii*haWindowSize + jj) := tempMaskReg(jj)\n }\n }\n }\n }\n }\n\n //--------------------------------------------------------------\n // Halt-on-reset\n // hrmaskReg is current set of harts that should halt-on-reset\n // Reset state (dmactive=0) is all zeroes\n // Bits are set by writing 1 to DMCONTROL.setresethaltreq\n // Bits are cleared by writing 1 to DMCONTROL.clrresethaltreq\n // Spec says if both are 1, then clrresethaltreq is executed\n // hrmask is the halt-on-reset mask which will be sent to inner\n //--------------------------------------------------------------\n\n val hrmask = Wire(Vec(nComponents, Bool()))\n val hrmaskNxt = Wire(Vec(nComponents, Bool()))\n val hrmaskReg = RegNext(next=hrmaskNxt, init=0.U.asTypeOf(hrmaskNxt)).suggestName(\"hrmaskReg\")\n\n hrmaskNxt := hrmaskReg\n for (component <- 0 until nComponents) {\n when (~dmactive || ~dmAuthenticated) {\n hrmaskNxt(component) := false.B\n }.elsewhen (clrresethaltreqWrEn && DMCONTROLWrData.clrresethaltreq && hartSelected(component)) {\n hrmaskNxt(component) := false.B\n }.elsewhen (setresethaltreqWrEn && DMCONTROLWrData.setresethaltreq && hartSelected(component)) {\n hrmaskNxt(component) := true.B\n }\n }\n hrmask := hrmaskNxt\n\n val dmControlRegFields = RegFieldGroup(\"dmcontrol\", Some(\"debug module control register\"), Seq(\n WNotifyVal(1, DMCONTROLReg.dmactive & io.ctrl.dmactiveAck, DMCONTROLWrData.dmactive, dmactiveWrEn,\n RegFieldDesc(\"dmactive\", \"debug module active\", reset=Some(0))),\n WNotifyVal(1, DMCONTROLReg.ndmreset, DMCONTROLWrData.ndmreset, ndmresetWrEn,\n RegFieldDesc(\"ndmreset\", \"debug module reset output\", reset=Some(0))),\n WNotifyVal(1, 0.U, DMCONTROLWrData.clrresethaltreq, clrresethaltreqWrEn,\n RegFieldDesc(\"clrresethaltreq\", \"clear reset halt request\", reset=Some(0), access=RegFieldAccessType.W)),\n WNotifyVal(1, 0.U, DMCONTROLWrData.setresethaltreq, setresethaltreqWrEn,\n RegFieldDesc(\"setresethaltreq\", \"set reset halt request\", reset=Some(0), access=RegFieldAccessType.W)),\n RegField(12),\n if (nComponents > 1) WNotifyVal(p(MaxHartIdBits),\n DMCONTROLReg.hartsello, DMCONTROLWrData.hartsello, hartselloWrEn,\n RegFieldDesc(\"hartsello\", \"hart select low\", reset=Some(0)))\n else RegField(1),\n if (nComponents > 1) RegField(10-p(MaxHartIdBits))\n else RegField(9),\n if (supportHartArray)\n WNotifyVal(1, DMCONTROLReg.hasel, DMCONTROLWrData.hasel, haselWrEn,\n RegFieldDesc(\"hasel\", \"hart array select\", reset=Some(0)))\n else RegField(1),\n RegField(1),\n WNotifyVal(1, 0.U, DMCONTROLWrData.ackhavereset, ackhaveresetWrEn,\n RegFieldDesc(\"ackhavereset\", \"acknowledge reset\", reset=Some(0), access=RegFieldAccessType.W)),\n if (cfg.hasHartResets)\n WNotifyVal(1, DMCONTROLReg.hartreset, DMCONTROLWrData.hartreset, hartresetWrEn,\n RegFieldDesc(\"hartreset\", \"hart reset request\", reset=Some(0)))\n else RegField(1),\n WNotifyVal(1, 0.U, DMCONTROLWrData.resumereq, resumereqWrEn,\n RegFieldDesc(\"resumereq\", \"resume request\", reset=Some(0), access=RegFieldAccessType.W)),\n WNotifyVal(1, DMCONTROLReg.haltreq, DMCONTROLWrData.haltreq, haltreqWrEn, // Spec says W, but maintaining previous behavior\n RegFieldDesc(\"haltreq\", \"halt request\", reset=Some(0)))\n ))\n\n val hartinfoRegFields = RegFieldGroup(\"dmi_hartinfo\", Some(\"hart information\"), Seq(\n RegField.r(12, HARTINFORdData.dataaddr, RegFieldDesc(\"dataaddr\", \"data address\", reset=Some(if (cfg.atzero) DsbRegAddrs.DATA else 0))),\n RegField.r(4, HARTINFORdData.datasize, RegFieldDesc(\"datasize\", \"number of DATA registers\", reset=Some(if (cfg.atzero) cfg.nAbstractDataWords else 0))),\n RegField.r(1, HARTINFORdData.dataaccess, RegFieldDesc(\"dataaccess\", \"data access type\", reset=Some(if (cfg.atzero) 1 else 0))),\n RegField(3),\n RegField.r(4, HARTINFORdData.nscratch, RegFieldDesc(\"nscratch\", \"number of scratch registers\", reset=Some(if (cfg.atzero) cfg.nScratch else 0)))\n ))\n\n //--------------------------------------------------------------\n // DMI register decoder for Outer\n //--------------------------------------------------------------\n\n // regmap addresses are byte offsets from lowest address\n def DMI_DMCONTROL_OFFSET = 0\n def DMI_HARTINFO_OFFSET = ((DMI_HARTINFO - DMI_DMCONTROL) << 2)\n def DMI_HAWINDOWSEL_OFFSET = ((DMI_HAWINDOWSEL - DMI_DMCONTROL) << 2)\n def DMI_HAWINDOW_OFFSET = ((DMI_HAWINDOW - DMI_DMCONTROL) << 2)\n\n val omRegMap = dmiNode.regmap(\n DMI_DMCONTROL_OFFSET -> dmControlRegFields,\n DMI_HARTINFO_OFFSET -> hartinfoRegFields,\n DMI_HAWINDOWSEL_OFFSET -> (if (supportHartArray && (nComponents > 32)) Seq(\n WNotifyVal(log2Up(nComponents)-5, HAWINDOWSELReg.hawindowsel, HAWINDOWSELWrData.hawindowsel, HAWINDOWSELWrEn,\n RegFieldDesc(\"hawindowsel\", \"hart array window select\", reset=Some(0)))) else Nil),\n DMI_HAWINDOW_OFFSET -> (if (supportHartArray) Seq(\n WNotifyVal(if (nComponents > 31) 32 else nComponents, HAWINDOWRdData.maskdata, HAWINDOWWrData.maskdata, HAWINDOWWrEn,\n RegFieldDesc(\"hawindow\", \"hart array window\", reset=Some(0), volatile=(nComponents > 32)))) else Nil)\n )\n\n //--------------------------------------------------------------\n // Interrupt Registers\n //--------------------------------------------------------------\n\n val debugIntNxt = WireInit(VecInit(Seq.fill(nComponents) {false.B} ))\n val debugIntRegs = RegNext(next=debugIntNxt, init=0.U.asTypeOf(debugIntNxt)).suggestName(\"debugIntRegs\")\n\n debugIntNxt := debugIntRegs\n val (intnode_out, _) = intnode.out.unzip\n for (component <- 0 until nComponents) {\n intnode_out(component)(0) := debugIntRegs(component) | io.hgDebugInt(component)\n }\n\n // sends debug interruption to Core when dmcs.haltreq is set,\n for (component <- 0 until nComponents) {\n when (~dmactive || ~dmAuthenticated) {\n debugIntNxt(component) := false.B\n }. otherwise {\n when (haltreqWrEn && ((DMCONTROLWrData.hartsello === component.U)\n || (if (supportHartArray) DMCONTROLWrData.hasel && hamask(component) else false.B))) {\n debugIntNxt(component) := DMCONTROLWrData.haltreq\n }\n }\n }\n // Halt request registers are set & cleared by writes to DMCONTROL.haltreq\n // resumereq also causes the core to execute a 'dret',\n // so resumereq is passed through to Inner.\n // hartsel/hasel/hamask must also be used by the DebugModule state machine,\n // so it is passed to Inner.\n\n // These registers ensure that requests to dmInner are not lost if inner clock isn't running or requests occur too close together.\n // If the innerCtrl async queue is not ready, the notification will be posted and held until ready is received.\n // Additional notifications that occur while one is already waiting update the pending data so that the last value written is sent.\n // Volatile events resumereq and ackhavereset are registered when they occur and remain pending until ready is received.\n val innerCtrlValid = Wire(Bool())\n val innerCtrlValidReg = RegInit(false.B).suggestName(\"innerCtrlValidReg\")\n val innerCtrlResumeReqReg = RegInit(false.B).suggestName(\"innerCtrlResumeReqReg\")\n val innerCtrlAckHaveResetReg = RegInit(false.B).suggestName(\"innerCtrlAckHaveResetReg\")\n\n innerCtrlValid := hartselloWrEn | resumereqWrEn | ackhaveresetWrEn | setresethaltreqWrEn | clrresethaltreqWrEn | haselWrEn |\n (HAWINDOWWrEn & supportHartArray.B)\n\n innerCtrlValidReg := io.innerCtrl.valid & ~io.innerCtrl.ready // Hold innerctrl request until the async queue accepts it\n innerCtrlResumeReqReg := io.innerCtrl.bits.resumereq & ~io.innerCtrl.ready // Hold resumereq until accepted\n innerCtrlAckHaveResetReg := io.innerCtrl.bits.ackhavereset & ~io.innerCtrl.ready // Hold ackhavereset until accepted\n\n io.innerCtrl.valid := innerCtrlValid | innerCtrlValidReg\n io.innerCtrl.bits.hartsel := Mux(hartselloWrEn, DMCONTROLWrData.hartsello, DMCONTROLReg.hartsello)\n io.innerCtrl.bits.resumereq := (resumereqWrEn & DMCONTROLWrData.resumereq) | innerCtrlResumeReqReg\n io.innerCtrl.bits.ackhavereset := (ackhaveresetWrEn & DMCONTROLWrData.ackhavereset) | innerCtrlAckHaveResetReg\n io.innerCtrl.bits.hrmask := hrmask\n if (supportHartArray) {\n io.innerCtrl.bits.hasel := Mux(haselWrEn, DMCONTROLWrData.hasel, DMCONTROLReg.hasel)\n io.innerCtrl.bits.hamask := hamask\n } else {\n io.innerCtrl.bits.hasel := DontCare\n io.innerCtrl.bits.hamask := DontCare\n }\n\n io.ctrl.ndreset := DMCONTROLReg.ndmreset\n io.ctrl.dmactive := DMCONTROLReg.dmactive\n\n // hart reset mechanism implementation\n if (cfg.hasHartResets) {\n val hartResetNxt = Wire(Vec(nComponents, Bool()))\n val hartResetReg = RegNext(next=hartResetNxt, init=0.U.asTypeOf(hartResetNxt))\n\n for (component <- 0 until nComponents) {\n hartResetNxt(component) := DMCONTROLReg.hartreset & hartSelected(component)\n io.hartResetReq.get(component) := hartResetReg(component)\n }\n }\n omRegMap // FIXME: Remove this when withReset is removed\n }}\n}\n// wrap a Outer with a DMIToTL, derived by dmi clock & reset\nclass TLDebugModuleOuterAsync(device: Device)(implicit p: Parameters) extends LazyModule {\n\n val cfg = p(DebugModuleKey).get\n\n val dmiXbar = LazyModule (new TLXbar(nameSuffix = Some(\"dmixbar\")))\n\n val dmi2tlOpt = (!p(ExportDebug).apb).option({\n val dmi2tl = LazyModule(new DMIToTL())\n dmiXbar.node := dmi2tl.node\n dmi2tl\n })\n\n val apbNodeOpt = p(ExportDebug).apb.option({\n val apb2tl = LazyModule(new APBToTL())\n val apb2tlBuffer = LazyModule(new TLBuffer(BufferParams.pipe))\n val dmTopAddr = (1 << cfg.nDMIAddrSize) << 2\n val tlErrorParams = DevNullParams(AddressSet.misaligned(dmTopAddr, APBDebugConsts.apbDebugRegBase-dmTopAddr), maxAtomic=0, maxTransfer=4)\n val tlError = LazyModule(new TLError(tlErrorParams, buffer=false))\n val apbXbar = LazyModule(new APBFanout())\n val apbRegs = LazyModule(new APBDebugRegisters())\n\n apbRegs.node := apbXbar.node\n apb2tl.node := apbXbar.node\n apb2tlBuffer.node := apb2tl.node\n dmiXbar.node := apb2tlBuffer.node\n tlError.node := dmiXbar.node\n apbXbar.node\n })\n\n val dmOuter = LazyModule( new TLDebugModuleOuter(device))\n val intnode = IntSyncIdentityNode()\n intnode :*= IntSyncCrossingSource(alreadyRegistered = true) :*= dmOuter.intnode\n\n val dmiBypass = LazyModule(new TLBusBypass(beatBytes=4, bufferError=false, maxAtomic=0, maxTransfer=4))\n val dmiInnerNode = TLAsyncCrossingSource() := dmiBypass.node := dmiXbar.node\n dmOuter.dmiNode := dmiXbar.node\n \n lazy val module = new Impl\n class Impl extends LazyRawModuleImp(this) {\n\n val nComponents = dmOuter.intnode.edges.out.size\n\n val io = IO(new Bundle {\n val dmi_clock = Input(Clock())\n val dmi_reset = Input(Reset())\n /** Debug Module Interface bewteen DM and DTM\n *\n * The DTM provides access to one or more Debug Modules (DMs) using DMI\n */\n val dmi = (!p(ExportDebug).apb).option(Flipped(new DMIIO()(p)))\n // Optional APB Interface is fully diplomatic so is not listed here.\n val ctrl = new DebugCtrlBundle(nComponents)\n /** conrol signals for Inner, generated in Outer */\n val innerCtrl = new AsyncBundle(new DebugInternalBundle(nComponents), AsyncQueueParams.singleton(safe=cfg.crossingHasSafeReset))\n /** debug interruption generated in Inner */\n val hgDebugInt = Input(Vec(nComponents, Bool()))\n /** hart reset request to core */\n val hartResetReq = p(DebugModuleKey).get.hasHartResets.option(Output(Vec(nComponents, Bool())))\n /** Authentication signal from core */\n val dmAuthenticated = p(DebugModuleKey).get.hasAuthentication.option(Input(Bool()))\n })\n val rf_reset = IO(Input(Reset())) // RF transform\n\n childClock := io.dmi_clock\n childReset := io.dmi_reset\n override def provideImplicitClockToLazyChildren = true\n\n withClockAndReset(childClock, childReset) {\n dmi2tlOpt.foreach { _.module.io.dmi <> io.dmi.get }\n\n val dmactiveAck = AsyncResetSynchronizerShiftReg(in=io.ctrl.dmactiveAck, sync=3, name=Some(\"dmactiveAckSync\"))\n dmiBypass.module.io.bypass := ~io.ctrl.dmactive | ~dmactiveAck\n\n io.ctrl <> dmOuter.module.io.ctrl\n dmOuter.module.io.ctrl.dmactiveAck := dmactiveAck // send synced version down to dmOuter\n io.innerCtrl <> ToAsyncBundle(dmOuter.module.io.innerCtrl, AsyncQueueParams.singleton(safe=cfg.crossingHasSafeReset))\n dmOuter.module.io.hgDebugInt := io.hgDebugInt\n io.hartResetReq.foreach { x => dmOuter.module.io.hartResetReq.foreach {y => x := y}}\n io.dmAuthenticated.foreach { x => dmOuter.module.io.dmAuthenticated.foreach { y => y := x}}\n }\n }\n}\n\nclass TLDebugModuleInner(device: Device, getNComponents: () => Int, beatBytes: Int)(implicit p: Parameters) extends LazyModule\n{\n\n // For Shorter Register Names\n import DMI_RegAddrs._\n\n val cfg = p(DebugModuleKey).get\n def getCfg = () => cfg\n val dmTopAddr = (1 << cfg.nDMIAddrSize) << 2\n /** dmiNode address set */\n val dmiNode = TLRegisterNode(\n // Address is range 0 to 0x1FF except DMCONTROL, HARTINFO, HAWINDOWSEL, HAWINDOW which are handled by Outer\n address = AddressSet.misaligned(0, DMI_DMCONTROL << 2) ++\n AddressSet.misaligned((DMI_DMCONTROL + 1) << 2, ((DMI_HARTINFO << 2) - ((DMI_DMCONTROL + 1) << 2))) ++\n AddressSet.misaligned((DMI_HARTINFO + 1) << 2, ((DMI_HAWINDOWSEL << 2) - ((DMI_HARTINFO + 1) << 2))) ++\n AddressSet.misaligned((DMI_HAWINDOW + 1) << 2, (dmTopAddr - ((DMI_HAWINDOW + 1) << 2))),\n device = device,\n beatBytes = 4,\n executable = false\n )\n\n val tlNode = TLRegisterNode(\n address=Seq(cfg.address),\n device=device,\n beatBytes=beatBytes,\n executable=true\n )\n\n val sb2tlOpt = cfg.hasBusMaster.option(LazyModule(new SBToTL()))\n\n // If we want to support custom registers read through Abstract Commands,\n // provide a place to bring them into the debug module. What this connects\n // to is up to the implementation.\n val customNode = new DebugCustomSink()\n\n lazy val module = new Impl\n class Impl extends LazyModuleImp(this){\n val nComponents = getNComponents()\n Annotated.params(this, cfg)\n val supportHartArray = cfg.supportHartArray & (nComponents > 1)\n val nExtTriggers = cfg.nExtTriggers\n val nHaltGroups = if ((nComponents > 1) | (nExtTriggers > 0)) cfg.nHaltGroups\n else 0 // no halt groups possible if single hart with no external triggers\n\n val hartSelFuncs = if (getNComponents() > 1) p(DebugModuleHartSelKey) else DebugModuleHartSelFuncs(\n hartIdToHartSel = (x) => 0.U,\n hartSelToHartId = (x) => x\n )\n\n val io = IO(new Bundle {\n /** dm reset signal passed in from Outer */\n val dmactive = Input(Bool())\n /** conrol signals for Inner\n *\n * it's generated by Outer and comes in\n */\n val innerCtrl = Flipped(new DecoupledIO(new DebugInternalBundle(nComponents)))\n /** debug unavail signal passed in from Outer*/\n val debugUnavail = Input(Vec(nComponents, Bool()))\n /** debug interruption from Inner to Outer\n *\n * contain 2 type of debug interruption causes:\n * - halt group\n * - halt-on-reset\n */\n val hgDebugInt = Output(Vec(nComponents, Bool()))\n /** interface for trigger */\n val extTrigger = (nExtTriggers > 0).option(new DebugExtTriggerIO())\n /** vector to indicate which hart is in reset\n *\n * dm receives it from core and sends it to Inner\n */\n val hartIsInReset = Input(Vec(nComponents, Bool()))\n val tl_clock = Input(Clock())\n val tl_reset = Input(Reset())\n /** Debug Authentication signals from core */\n val auth = cfg.hasAuthentication.option(new DebugAuthenticationIO())\n })\n\n sb2tlOpt.map { sb =>\n sb.module.clock := io.tl_clock\n sb.module.reset := io.tl_reset\n sb.module.rf_reset := io.tl_reset\n }\n\n //--------------------------------------------------------------\n // Import constants for shorter variable names\n //--------------------------------------------------------------\n\n import DMI_RegAddrs._\n import DsbRegAddrs._\n import DsbBusConsts._\n\n //--------------------------------------------------------------\n // Sanity Check Configuration For this implementation.\n //--------------------------------------------------------------\n\n require (cfg.supportQuickAccess == false, \"No Quick Access support yet\")\n require ((nHaltGroups > 0) || (nExtTriggers == 0), \"External triggers require at least 1 halt group\")\n\n //--------------------------------------------------------------\n // Register & Wire Declarations (which need to be pre-declared)\n //--------------------------------------------------------------\n\n // run control regs: tracking all the harts\n // implements: see implementation-specific bits part\n /** all harts halted status */\n val haltedBitRegs = Reg(UInt(nComponents.W))\n /** all harts resume request status */\n val resumeReqRegs = Reg(UInt(nComponents.W))\n /** all harts have reset status */\n val haveResetBitRegs = Reg(UInt(nComponents.W))\n\n // default is 1,after resume, resumeAcks get 0\n /** all harts resume ack status */\n val resumeAcks = Wire(UInt(nComponents.W))\n\n // --- regmapper outputs\n\n // hart state Id and En\n // in Hart Bus Access ROM\n val hartHaltedWrEn = Wire(Bool())\n val hartHaltedId = Wire(UInt(sbIdWidth.W))\n val hartGoingWrEn = Wire(Bool())\n val hartGoingId = Wire(UInt(sbIdWidth.W))\n val hartResumingWrEn = Wire(Bool())\n val hartResumingId = Wire(UInt(sbIdWidth.W))\n val hartExceptionWrEn = Wire(Bool())\n val hartExceptionId = Wire(UInt(sbIdWidth.W))\n\n // progbuf and abstract data: byte-addressable control logic\n // AccessLegal is set only when state = waiting\n // RdEn and WrEnMaybe : contrl signal drived by DMI bus\n val dmiProgramBufferRdEn = WireInit(VecInit(Seq.fill(cfg.nProgramBufferWords * 4) {false.B} ))\n val dmiProgramBufferAccessLegal = WireInit(false.B)\n val dmiProgramBufferWrEnMaybe = WireInit(VecInit(Seq.fill(cfg.nProgramBufferWords * 4) {false.B} ))\n\n val dmiAbstractDataRdEn = WireInit(VecInit(Seq.fill(cfg.nAbstractDataWords * 4) {false.B} ))\n val dmiAbstractDataAccessLegal = WireInit(false.B)\n val dmiAbstractDataWrEnMaybe = WireInit(VecInit(Seq.fill(cfg.nAbstractDataWords * 4) {false.B} ))\n\n //--------------------------------------------------------------\n // Registers coming from 'CONTROL' in Outer\n //--------------------------------------------------------------\n\n val dmAuthenticated = io.auth.map(a => a.dmAuthenticated).getOrElse(true.B)\n\n val selectedHartReg = Reg(UInt(p(MaxHartIdBits).W))\n // hamaskFull is a vector of all selected harts including hartsel, whether or not supportHartArray is true\n val hamaskFull = WireInit(VecInit(Seq.fill(nComponents) {false.B} ))\n\n if (nComponents > 1) {\n when (~io.dmactive) {\n selectedHartReg := 0.U\n }.elsewhen (io.innerCtrl.fire){\n selectedHartReg := io.innerCtrl.bits.hartsel\n }\n }\n\n if (supportHartArray) {\n val hamaskZero = WireInit(VecInit(Seq.fill(nComponents) {false.B} ))\n val hamaskReg = Reg(Vec(nComponents, Bool()))\n when (~io.dmactive || ~dmAuthenticated) {\n hamaskReg := hamaskZero\n }.elsewhen (io.innerCtrl.fire){\n hamaskReg := Mux(io.innerCtrl.bits.hasel, io.innerCtrl.bits.hamask, hamaskZero)\n }\n hamaskFull := hamaskReg\n }\n // Outer.hamask doesn't consider the hart selected by dmcontrol.hartsello,\n // so append it here\n when (selectedHartReg < nComponents.U) {\n hamaskFull(if (nComponents == 1) 0.U(0.W) else selectedHartReg) := true.B\n }\n\n io.innerCtrl.ready := true.B\n\n // Construct a Vec from io.innerCtrl fields indicating whether each hart is being selected in this write\n // A hart may be selected by hartsel field or by hart array\n val hamaskWrSel = WireInit(VecInit(Seq.fill(nComponents) {false.B} ))\n for (component <- 0 until nComponents ) {\n hamaskWrSel(component) := ((io.innerCtrl.bits.hartsel === component.U) ||\n (if (supportHartArray) io.innerCtrl.bits.hasel && io.innerCtrl.bits.hamask(component) else false.B))\n }\n\n //-------------------------------------\n // Halt-on-reset logic\n // hrmask is set in dmOuter and passed in\n // Debug interrupt is generated when a reset occurs whose corresponding hrmask bit is set\n // Debug interrupt is maintained until the hart enters halted state\n //-------------------------------------\n val hrReset = WireInit(VecInit(Seq.fill(nComponents) { false.B } ))\n val hrDebugInt = Wire(Vec(nComponents, Bool()))\n val hrmaskReg = RegInit(hrReset)\n val hartIsInResetSync = Wire(Vec(nComponents, Bool()))\n\n for (component <- 0 until nComponents) {\n hartIsInResetSync(component) := AsyncResetSynchronizerShiftReg(io.hartIsInReset(component), 3, Some(s\"debug_hartReset_$component\"))\n }\n\n when (~io.dmactive || ~dmAuthenticated) {\n hrmaskReg := hrReset\n }.elsewhen (io.innerCtrl.fire){\n hrmaskReg := io.innerCtrl.bits.hrmask\n }\n\n withReset(reset.asAsyncReset) { // ensure interrupt requests are negated at first clock edge\n val hrDebugIntReg = RegInit(VecInit(Seq.fill(nComponents) { false.B } ))\n when (~io.dmactive || ~dmAuthenticated) {\n hrDebugIntReg := hrReset\n }.otherwise {\n hrDebugIntReg := hrmaskReg &\n (hartIsInResetSync | // set debugInt during reset\n (hrDebugIntReg & ~(haltedBitRegs.asBools))) // maintain until core halts\n }\n hrDebugInt := hrDebugIntReg\n }\n\n //--------------------------------------------------------------\n // DMI Registers\n //--------------------------------------------------------------\n\n //----DMSTATUS\n\n val DMSTATUSRdData = WireInit(0.U.asTypeOf(new DMSTATUSFields()))\n DMSTATUSRdData.authenticated := dmAuthenticated\n DMSTATUSRdData.version := 2.U // Version 0.13\n io.auth.map(a => DMSTATUSRdData.authbusy := a.dmAuthBusy)\n\n val resumereq = io.innerCtrl.fire && io.innerCtrl.bits.resumereq\n\n when (dmAuthenticated) {\n DMSTATUSRdData.hasresethaltreq := true.B\n\n DMSTATUSRdData.anynonexistent := (selectedHartReg >= nComponents.U) // only hartsel can be nonexistent\n\n // all harts nonexistent if hartsel is out of range and there are no harts selected in the hart array\n DMSTATUSRdData.allnonexistent := (selectedHartReg >= nComponents.U) & (~hamaskFull.reduce(_ | _))\n\n when (~DMSTATUSRdData.allnonexistent) { // if no existent harts selected, all other status is false\n DMSTATUSRdData.anyunavail := (io.debugUnavail & hamaskFull).reduce(_ | _)\n DMSTATUSRdData.anyhalted := ((~io.debugUnavail & (haltedBitRegs.asBools)) & hamaskFull).reduce(_ | _)\n DMSTATUSRdData.anyrunning := ((~io.debugUnavail & ~(haltedBitRegs.asBools)) & hamaskFull).reduce(_ | _)\n DMSTATUSRdData.anyhavereset := (haveResetBitRegs.asBools & hamaskFull).reduce(_ | _)\n DMSTATUSRdData.anyresumeack := (resumeAcks.asBools & hamaskFull).reduce(_ | _)\n when (~DMSTATUSRdData.anynonexistent) { // if one hart is nonexistent, no 'all' status is set\n DMSTATUSRdData.allunavail := (io.debugUnavail | ~hamaskFull).reduce(_ & _)\n DMSTATUSRdData.allhalted := ((~io.debugUnavail & (haltedBitRegs.asBools)) | ~hamaskFull).reduce(_ & _)\n DMSTATUSRdData.allrunning := ((~io.debugUnavail & ~(haltedBitRegs.asBools)) | ~hamaskFull).reduce(_ & _)\n DMSTATUSRdData.allhavereset := (haveResetBitRegs.asBools | ~hamaskFull).reduce(_ & _)\n DMSTATUSRdData.allresumeack := (resumeAcks.asBools | ~hamaskFull).reduce(_ & _)\n }\n }\n\n //TODO\n DMSTATUSRdData.confstrptrvalid := false.B\n DMSTATUSRdData.impebreak := (cfg.hasImplicitEbreak).B\n }\n\n when(~io.dmactive || ~dmAuthenticated) {\n haveResetBitRegs := 0.U\n }.otherwise {\n when (io.innerCtrl.fire && io.innerCtrl.bits.ackhavereset) {\n haveResetBitRegs := (haveResetBitRegs & (~(hamaskWrSel.asUInt))) | hartIsInResetSync.asUInt \n }.otherwise {\n haveResetBitRegs := haveResetBitRegs | hartIsInResetSync.asUInt \n }\n }\n\n //----DMCS2 (Halt Groups)\n\n val DMCS2RdData = WireInit(0.U.asTypeOf(new DMCS2Fields()))\n val DMCS2WrData = WireInit(0.U.asTypeOf(new DMCS2Fields()))\n val hgselectWrEn = WireInit(false.B)\n val hgwriteWrEn = WireInit(false.B)\n val haltgroupWrEn = WireInit(false.B)\n val exttriggerWrEn = WireInit(false.B)\n val hgDebugInt = WireInit(VecInit(Seq.fill(nComponents) {false.B} ))\n\n if (nHaltGroups > 0) withReset (reset.asAsyncReset) { // async reset ensures triggers don't falsely fire during startup\n val hgBits = log2Up(nHaltGroups)\n // hgParticipate: Each entry indicates which hg that entity belongs to (1 to nHartGroups). 0 means no hg assigned.\n val hgParticipateHart = RegInit(VecInit(Seq.fill(nComponents)(0.U(hgBits.W))))\n val hgParticipateTrig = if (nExtTriggers > 0) RegInit(VecInit(Seq.fill(nExtTriggers)(0.U(hgBits.W)))) else Nil\n\n // assign group index to current seledcted harts\n for (component <- 0 until nComponents) {\n when (~io.dmactive || ~dmAuthenticated) {\n hgParticipateHart(component) := 0.U\n }.otherwise {\n when (haltgroupWrEn & DMCS2WrData.hgwrite & ~DMCS2WrData.hgselect &\n hamaskFull(component) & (DMCS2WrData.haltgroup <= nHaltGroups.U)) {\n hgParticipateHart(component) := DMCS2WrData.haltgroup\n }\n }\n }\n DMCS2RdData.haltgroup := hgParticipateHart(if (nComponents == 1) 0.U(0.W) else selectedHartReg)\n\n if (nExtTriggers > 0) {\n val hgSelect = Reg(Bool())\n\n when (~io.dmactive || ~dmAuthenticated) {\n hgSelect := false.B\n }.otherwise {\n when (hgselectWrEn) {\n hgSelect := DMCS2WrData.hgselect\n }\n }\n\n // assign group index to trigger\n for (trigger <- 0 until nExtTriggers) {\n when (~io.dmactive || ~dmAuthenticated) {\n hgParticipateTrig(trigger) := 0.U\n }.otherwise {\n when (haltgroupWrEn & DMCS2WrData.hgwrite & DMCS2WrData.hgselect &\n (DMCS2WrData.exttrigger === trigger.U) & (DMCS2WrData.haltgroup <= nHaltGroups.U)) {\n hgParticipateTrig(trigger) := DMCS2WrData.haltgroup\n }\n }\n }\n\n DMCS2RdData.hgselect := hgSelect\n when (hgSelect) {\n DMCS2RdData.haltgroup := hgParticipateTrig(0)\n }\n\n // If there is only 1 ext trigger, then the exttrigger field is fixed at 0\n // Otherwise, instantiate a register with only the number of bits required\n\n if (nExtTriggers > 1) {\n val trigBits = log2Up(nExtTriggers-1)\n val hgExtTrigger = Reg(UInt(trigBits.W))\n when (~io.dmactive || ~dmAuthenticated) {\n hgExtTrigger := 0.U\n }.otherwise {\n when (exttriggerWrEn & (DMCS2WrData.exttrigger < nExtTriggers.U)) {\n hgExtTrigger := DMCS2WrData.exttrigger\n }\n }\n\n DMCS2RdData.exttrigger := hgExtTrigger\n when (hgSelect) {\n DMCS2RdData.haltgroup := hgParticipateTrig(hgExtTrigger)\n }\n }\n }\n\n // Halt group state machine\n // IDLE: Go to FIRED when any hart in this hg writes to HALTED while its HaltedBitRegs=0\n // or when any trigin assigned to this hg occurs\n // FIRED: Back to IDLE when all harts in this hg have set their haltedBitRegs\n // and all trig out in this hg have been acknowledged\n\n val hgFired = RegInit (VecInit(Seq.fill(nHaltGroups+1) {false.B} ))\n val hgHartFiring = WireInit(VecInit(Seq.fill(nHaltGroups+1) {false.B} )) // which hg's are firing due to hart halting\n val hgTrigFiring = WireInit(VecInit(Seq.fill(nHaltGroups+1) {false.B} )) // which hg's are firing due to trig in\n val hgHartsAllHalted = WireInit(VecInit(Seq.fill(nHaltGroups+1) {false.B} )) // in which hg's have all harts halted\n val hgTrigsAllAcked = WireInit(VecInit(Seq.fill(nHaltGroups+1) { true.B} )) // in which hg's have all trigouts been acked\n\n io.extTrigger.foreach {extTrigger =>\n val extTriggerInReq = Wire(Vec(nExtTriggers, Bool()))\n val extTriggerOutAck = Wire(Vec(nExtTriggers, Bool()))\n extTriggerInReq := extTrigger.in.req.asBools\n extTriggerOutAck := extTrigger.out.ack.asBools\n val trigInReq = ResetSynchronizerShiftReg(in=extTriggerInReq, sync=3, name=Some(\"dm_extTriggerInReqSync\"))\n val trigOutAck = ResetSynchronizerShiftReg(in=extTriggerOutAck, sync=3, name=Some(\"dm_extTriggerOutAckSync\"))\n for (hg <- 1 to nHaltGroups) {\n hgTrigFiring(hg) := (trigInReq & ~RegNext(trigInReq) & hgParticipateTrig.map(_ === hg.U)).reduce(_ | _)\n hgTrigsAllAcked(hg) := (trigOutAck | hgParticipateTrig.map(_ =/= hg.U)).reduce(_ & _)\n }\n extTrigger.in.ack := trigInReq.asUInt\n }\n\n for (hg <- 1 to nHaltGroups) {\n hgHartFiring(hg) := hartHaltedWrEn & ~haltedBitRegs(hartHaltedId) & (hgParticipateHart(hartSelFuncs.hartIdToHartSel(hartHaltedId)) === hg.U)\n hgHartsAllHalted(hg) := (haltedBitRegs.asBools | hgParticipateHart.map(_ =/= hg.U)).reduce(_ & _)\n\n when (~io.dmactive || ~dmAuthenticated) {\n hgFired(hg) := false.B\n }.elsewhen (~hgFired(hg) & (hgHartFiring(hg) | hgTrigFiring(hg))) {\n hgFired(hg) := true.B\n }.elsewhen ( hgFired(hg) & hgHartsAllHalted(hg) & hgTrigsAllAcked(hg)) {\n hgFired(hg) := false.B\n }\n }\n\n // For each hg that has fired, assert debug interrupt to each hart in that hg\n for (component <- 0 until nComponents) {\n hgDebugInt(component) := hgFired(hgParticipateHart(component))\n }\n\n // For each hg that has fired, assert trigger out for all external triggers in that hg\n io.extTrigger.foreach {extTrigger =>\n val extTriggerOutReq = RegInit(VecInit(Seq.fill(cfg.nExtTriggers) {false.B} ))\n for (trig <- 0 until nExtTriggers) {\n extTriggerOutReq(trig) := hgFired(hgParticipateTrig(trig))\n }\n extTrigger.out.req := extTriggerOutReq.asUInt\n }\n }\n io.hgDebugInt := hgDebugInt | hrDebugInt\n\n\n //----HALTSUM*\n val numHaltedStatus = ((nComponents - 1) / 32) + 1\n val haltedStatus = Wire(Vec(numHaltedStatus, Bits(32.W)))\n\n for (ii <- 0 until numHaltedStatus) {\n when (dmAuthenticated) {\n haltedStatus(ii) := haltedBitRegs >> (ii*32)\n }.otherwise {\n haltedStatus(ii) := 0.U\n }\n }\n\n val haltedSummary = Cat(haltedStatus.map(_.orR).reverse)\n val HALTSUM1RdData = haltedSummary.asTypeOf(new HALTSUM1Fields())\n\n val selectedHaltedStatus = Mux((selectedHartReg >> 5) > numHaltedStatus.U, 0.U, haltedStatus(selectedHartReg >> 5))\n val HALTSUM0RdData = selectedHaltedStatus.asTypeOf(new HALTSUM0Fields())\n\n // Since we only support 1024 harts, we don't implement HALTSUM2 or HALTSUM3\n\n //----ABSTRACTCS\n\n val ABSTRACTCSReset = WireInit(0.U.asTypeOf(new ABSTRACTCSFields()))\n ABSTRACTCSReset.datacount := cfg.nAbstractDataWords.U\n ABSTRACTCSReset.progbufsize := cfg.nProgramBufferWords.U\n\n val ABSTRACTCSReg = Reg(new ABSTRACTCSFields())\n val ABSTRACTCSWrData = WireInit(0.U.asTypeOf(new ABSTRACTCSFields()))\n val ABSTRACTCSRdData = WireInit(ABSTRACTCSReg)\n\n val ABSTRACTCSRdEn = WireInit(false.B)\n val ABSTRACTCSWrEnMaybe = WireInit(false.B)\n\n val ABSTRACTCSWrEnLegal = WireInit(false.B)\n val ABSTRACTCSWrEn = ABSTRACTCSWrEnMaybe && ABSTRACTCSWrEnLegal\n \n // multiple error types\n // find implement in the state machine part\n val errorBusy = WireInit(false.B)\n val errorException = WireInit(false.B)\n val errorUnsupported = WireInit(false.B)\n val errorHaltResume = WireInit(false.B)\n\n when (~io.dmactive || ~dmAuthenticated) {\n ABSTRACTCSReg := ABSTRACTCSReset\n }.otherwise {\n when (errorBusy){\n ABSTRACTCSReg.cmderr := DebugAbstractCommandError.ErrBusy.id.U\n }.elsewhen (errorException) {\n ABSTRACTCSReg.cmderr := DebugAbstractCommandError.ErrException.id.U\n }.elsewhen (errorUnsupported) {\n ABSTRACTCSReg.cmderr := DebugAbstractCommandError.ErrNotSupported.id.U\n }.elsewhen (errorHaltResume) {\n ABSTRACTCSReg.cmderr := DebugAbstractCommandError.ErrHaltResume.id.U\n }.otherwise {\n //W1C\n when (ABSTRACTCSWrEn){\n ABSTRACTCSReg.cmderr := ABSTRACTCSReg.cmderr & ~(ABSTRACTCSWrData.cmderr);\n }\n }\n }\n\n // For busy, see below state machine.\n val abstractCommandBusy = WireInit(true.B)\n ABSTRACTCSRdData.busy := abstractCommandBusy\n when (~dmAuthenticated) { // read value must be 0 when not authenticated\n ABSTRACTCSRdData.datacount := 0.U\n ABSTRACTCSRdData.progbufsize := 0.U\n }\n\n //---- ABSTRACTAUTO\n // It is a mask indicating whether datai/probufi have the autoexcution permisson\n // this part aims to produce 3 wires : autoexecData,autoexecProg,autoexec\n // first two specify which reg supports autoexec\n // autoexec is a control signal, meaning there is at least one enabled autoexec reg\n // when autoexec is set, generate instructions using COMMAND register\n\n val ABSTRACTAUTOReset = WireInit(0.U.asTypeOf(new ABSTRACTAUTOFields()))\n val ABSTRACTAUTOReg = Reg(new ABSTRACTAUTOFields())\n val ABSTRACTAUTOWrData = WireInit(0.U.asTypeOf(new ABSTRACTAUTOFields()))\n val ABSTRACTAUTORdData = WireInit(ABSTRACTAUTOReg)\n\n val ABSTRACTAUTORdEn = WireInit(false.B)\n val autoexecdataWrEnMaybe = WireInit(false.B)\n val autoexecprogbufWrEnMaybe = WireInit(false.B)\n\n val ABSTRACTAUTOWrEnLegal = WireInit(false.B)\n\n when (~io.dmactive || ~dmAuthenticated) {\n ABSTRACTAUTOReg := ABSTRACTAUTOReset\n }.otherwise {\n when (autoexecprogbufWrEnMaybe && ABSTRACTAUTOWrEnLegal) {\n ABSTRACTAUTOReg.autoexecprogbuf := ABSTRACTAUTOWrData.autoexecprogbuf & ( (1 << cfg.nProgramBufferWords) - 1).U\n }\n when (autoexecdataWrEnMaybe && ABSTRACTAUTOWrEnLegal) {\n ABSTRACTAUTOReg.autoexecdata := ABSTRACTAUTOWrData.autoexecdata & ( (1 << cfg.nAbstractDataWords) - 1).U\n }\n }\n\n // Abstract Data access vector(byte-addressable)\n val dmiAbstractDataAccessVec = WireInit(VecInit(Seq.fill(cfg.nAbstractDataWords * 4) {false.B} ))\n dmiAbstractDataAccessVec := (dmiAbstractDataWrEnMaybe zip dmiAbstractDataRdEn).map{ case (r,w) => r | w}\n // Program Buffer access vector(byte-addressable)\n val dmiProgramBufferAccessVec = WireInit(VecInit(Seq.fill(cfg.nProgramBufferWords * 4) {false.B} ))\n dmiProgramBufferAccessVec := (dmiProgramBufferWrEnMaybe zip dmiProgramBufferRdEn).map{ case (r,w) => r | w}\n // at least one word access\n val dmiAbstractDataAccess = dmiAbstractDataAccessVec.reduce(_ || _ )\n val dmiProgramBufferAccess = dmiProgramBufferAccessVec.reduce(_ || _)\n\n // This will take the shorter of the lists, which is what we want.\n val autoexecData = WireInit(VecInit(Seq.fill(cfg.nAbstractDataWords) {false.B} ))\n val autoexecProg = WireInit(VecInit(Seq.fill(cfg.nProgramBufferWords) {false.B} ))\n (autoexecData zip ABSTRACTAUTOReg.autoexecdata.asBools).zipWithIndex.foreach {case (t, i) => t._1 := dmiAbstractDataAccessVec(i * 4) && t._2 }\n (autoexecProg zip ABSTRACTAUTOReg.autoexecprogbuf.asBools).zipWithIndex.foreach {case (t, i) => t._1 := dmiProgramBufferAccessVec(i * 4) && t._2}\n\n val autoexec = autoexecData.reduce(_ || _) || autoexecProg.reduce(_ || _)\n\n //---- COMMAND\n\n val COMMANDReset = WireInit(0.U.asTypeOf(new COMMANDFields()))\n val COMMANDReg = Reg(new COMMANDFields())\n\n val COMMANDWrDataVal = WireInit(0.U(32.W))\n val COMMANDWrData = WireInit(COMMANDWrDataVal.asTypeOf(new COMMANDFields()))\n val COMMANDWrEnMaybe = WireInit(false.B)\n val COMMANDWrEnLegal = WireInit(false.B)\n val COMMANDRdEn = WireInit(false.B)\n\n val COMMANDWrEn = COMMANDWrEnMaybe && COMMANDWrEnLegal\n val COMMANDRdData = COMMANDReg\n\n when (~io.dmactive || ~dmAuthenticated) {\n COMMANDReg := COMMANDReset\n }.otherwise {\n when (COMMANDWrEn) {\n COMMANDReg := COMMANDWrData\n }\n }\n\n // --- Abstract Data\n\n // These are byte addressible, s.t. the Processor can use\n // byte-addressible instructions to store to them.\n val abstractDataMem = Reg(Vec(cfg.nAbstractDataWords*4, UInt(8.W)))\n val abstractDataNxt = WireInit(abstractDataMem)\n\n // --- Program Buffer\n\n // byte-addressible mem\n val programBufferMem = Reg(Vec(cfg.nProgramBufferWords*4, UInt(8.W)))\n val programBufferNxt = WireInit(programBufferMem)\n\n //--------------------------------------------------------------\n // These bits are implementation-specific bits set\n // by harts executing code.\n //--------------------------------------------------------------\n\n // Run control logic\n when (~io.dmactive || ~dmAuthenticated) {\n haltedBitRegs := 0.U\n resumeReqRegs := 0.U\n }.otherwise {\n //remove those harts in reset\n resumeReqRegs := resumeReqRegs & ~(hartIsInResetSync.asUInt)\n\n val hartHaltedIdIndex = UIntToOH(hartSelFuncs.hartIdToHartSel(hartHaltedId))\n val hartResumingIdIndex = UIntToOH(hartSelFuncs.hartIdToHartSel(hartResumingId))\n val hartselIndex = UIntToOH(io.innerCtrl.bits.hartsel)\n when (hartHaltedWrEn) {\n // add those harts halting and remove those in reset\n haltedBitRegs := (haltedBitRegs | hartHaltedIdIndex) & ~(hartIsInResetSync.asUInt)\n }.elsewhen (hartResumingWrEn) {\n // remove those harts in reset and those in resume\n haltedBitRegs := (haltedBitRegs & ~(hartResumingIdIndex)) & ~(hartIsInResetSync.asUInt)\n }.otherwise {\n // remove those harts in reset\n haltedBitRegs := haltedBitRegs & ~(hartIsInResetSync.asUInt)\n }\n\n when (hartResumingWrEn) {\n // remove those harts in resume and those in reset\n resumeReqRegs := (resumeReqRegs & ~(hartResumingIdIndex)) & ~(hartIsInResetSync.asUInt)\n }\n when (resumereq) {\n // set all sleceted harts to resumeReq, remove those in reset\n resumeReqRegs := (resumeReqRegs | hamaskWrSel.asUInt) & ~(hartIsInResetSync.asUInt)\n }\n\n }\n\n when (resumereq) {\n // next cycle resumeAcls will be the negation of next cycle resumeReqRegs\n resumeAcks := (~resumeReqRegs & ~(hamaskWrSel.asUInt))\n }.otherwise {\n resumeAcks := ~resumeReqRegs\n }\n\n\n //---- AUTHDATA\n val authRdEnMaybe = WireInit(false.B)\n val authWrEnMaybe = WireInit(false.B)\n io.auth.map { a =>\n a.dmactive := io.dmactive\n a.dmAuthRead := authRdEnMaybe & ~a.dmAuthBusy\n a.dmAuthWrite := authWrEnMaybe & ~a.dmAuthBusy\n }\n\n val dmstatusRegFields = RegFieldGroup(\"dmi_dmstatus\", Some(\"debug module status register\"), Seq(\n RegField.r(4, DMSTATUSRdData.version, RegFieldDesc(\"version\", \"version\", reset=Some(2))),\n RegField.r(1, DMSTATUSRdData.confstrptrvalid, RegFieldDesc(\"confstrptrvalid\", \"confstrptrvalid\", reset=Some(0))),\n RegField.r(1, DMSTATUSRdData.hasresethaltreq, RegFieldDesc(\"hasresethaltreq\", \"hasresethaltreq\", reset=Some(1))),\n RegField.r(1, DMSTATUSRdData.authbusy, RegFieldDesc(\"authbusy\", \"authbusy\", reset=Some(0))),\n RegField.r(1, DMSTATUSRdData.authenticated, RegFieldDesc(\"authenticated\", \"authenticated\", reset=Some(1))),\n RegField.r(1, DMSTATUSRdData.anyhalted, RegFieldDesc(\"anyhalted\", \"anyhalted\", reset=Some(0))),\n RegField.r(1, DMSTATUSRdData.allhalted, RegFieldDesc(\"allhalted\", \"allhalted\", reset=Some(0))),\n RegField.r(1, DMSTATUSRdData.anyrunning, RegFieldDesc(\"anyrunning\", \"anyrunning\", reset=Some(1))),\n RegField.r(1, DMSTATUSRdData.allrunning, RegFieldDesc(\"allrunning\", \"allrunning\", reset=Some(1))),\n RegField.r(1, DMSTATUSRdData.anyunavail, RegFieldDesc(\"anyunavail\", \"anyunavail\", reset=Some(0))),\n RegField.r(1, DMSTATUSRdData.allunavail, RegFieldDesc(\"allunavail\", \"allunavail\", reset=Some(0))),\n RegField.r(1, DMSTATUSRdData.anynonexistent, RegFieldDesc(\"anynonexistent\", \"anynonexistent\", reset=Some(0))),\n RegField.r(1, DMSTATUSRdData.allnonexistent, RegFieldDesc(\"allnonexistent\", \"allnonexistent\", reset=Some(0))),\n RegField.r(1, DMSTATUSRdData.anyresumeack, RegFieldDesc(\"anyresumeack\", \"anyresumeack\", reset=Some(1))),\n RegField.r(1, DMSTATUSRdData.allresumeack, RegFieldDesc(\"allresumeack\", \"allresumeack\", reset=Some(1))),\n RegField.r(1, DMSTATUSRdData.anyhavereset, RegFieldDesc(\"anyhavereset\", \"anyhavereset\", reset=Some(0))),\n RegField.r(1, DMSTATUSRdData.allhavereset, RegFieldDesc(\"allhavereset\", \"allhavereset\", reset=Some(0))),\n RegField(2),\n RegField.r(1, DMSTATUSRdData.impebreak, RegFieldDesc(\"impebreak\", \"impebreak\", reset=Some(if (cfg.hasImplicitEbreak) 1 else 0)))\n ))\n\n val dmcs2RegFields = RegFieldGroup(\"dmi_dmcs2\", Some(\"debug module control/status register 2\"), Seq(\n WNotifyVal(1, DMCS2RdData.hgselect, DMCS2WrData.hgselect, hgselectWrEn,\n RegFieldDesc(\"hgselect\", \"select halt groups or external triggers\", reset=Some(0), volatile=true)),\n WNotifyVal(1, 0.U, DMCS2WrData.hgwrite, hgwriteWrEn,\n RegFieldDesc(\"hgwrite\", \"write 1 to change halt groups\", reset=None, access=RegFieldAccessType.W)),\n WNotifyVal(5, DMCS2RdData.haltgroup, DMCS2WrData.haltgroup, haltgroupWrEn,\n RegFieldDesc(\"haltgroup\", \"halt group\", reset=Some(0), volatile=true)),\n if (nExtTriggers > 1)\n WNotifyVal(4, DMCS2RdData.exttrigger, DMCS2WrData.exttrigger, exttriggerWrEn,\n RegFieldDesc(\"exttrigger\", \"external trigger select\", reset=Some(0), volatile=true))\n else RegField(4)\n ))\n\n val abstractcsRegFields = RegFieldGroup(\"dmi_abstractcs\", Some(\"abstract command control/status\"), Seq(\n RegField.r(4, ABSTRACTCSRdData.datacount, RegFieldDesc(\"datacount\", \"number of DATA registers\", reset=Some(cfg.nAbstractDataWords))),\n RegField(4),\n WNotifyVal(3, ABSTRACTCSRdData.cmderr, ABSTRACTCSWrData.cmderr, ABSTRACTCSWrEnMaybe,\n RegFieldDesc(\"cmderr\", \"command error\", reset=Some(0), wrType=Some(RegFieldWrType.ONE_TO_CLEAR))),\n RegField(1),\n RegField.r(1, ABSTRACTCSRdData.busy, RegFieldDesc(\"busy\", \"busy\", reset=Some(0))),\n RegField(11),\n RegField.r(5, ABSTRACTCSRdData.progbufsize, RegFieldDesc(\"progbufsize\", \"number of PROGBUF registers\", reset=Some(cfg.nProgramBufferWords)))\n ))\n\n val (sbcsFields, sbAddrFields, sbDataFields):\n (Seq[RegField], Seq[Seq[RegField]], Seq[Seq[RegField]]) = sb2tlOpt.map{ sb2tl =>\n SystemBusAccessModule(sb2tl, io.dmactive, dmAuthenticated)(p)\n }.getOrElse((Seq.empty[RegField], Seq.fill[Seq[RegField]](4)(Seq.empty[RegField]), Seq.fill[Seq[RegField]](4)(Seq.empty[RegField])))\n\n //--------------------------------------------------------------\n // Program Buffer Access (DMI ... System Bus can override)\n //--------------------------------------------------------------\n\n val omRegMap = dmiNode.regmap(\n (DMI_DMSTATUS << 2) -> dmstatusRegFields,\n //TODO (DMI_CFGSTRADDR0 << 2) -> cfgStrAddrFields,\n (DMI_DMCS2 << 2) -> (if (nHaltGroups > 0) dmcs2RegFields else Nil),\n (DMI_HALTSUM0 << 2) -> RegFieldGroup(\"dmi_haltsum0\", Some(\"Halt Summary 0\"),\n Seq(RegField.r(32, HALTSUM0RdData.asUInt, RegFieldDesc(\"dmi_haltsum0\", \"halt summary 0\")))),\n (DMI_HALTSUM1 << 2) -> RegFieldGroup(\"dmi_haltsum1\", Some(\"Halt Summary 1\"),\n Seq(RegField.r(32, HALTSUM1RdData.asUInt, RegFieldDesc(\"dmi_haltsum1\", \"halt summary 1\")))),\n (DMI_ABSTRACTCS << 2) -> abstractcsRegFields,\n (DMI_ABSTRACTAUTO<< 2) -> RegFieldGroup(\"dmi_abstractauto\", Some(\"abstract command autoexec\"), Seq(\n WNotifyVal(cfg.nAbstractDataWords, ABSTRACTAUTORdData.autoexecdata, ABSTRACTAUTOWrData.autoexecdata, autoexecdataWrEnMaybe,\n RegFieldDesc(\"autoexecdata\", \"abstract command data autoexec\", reset=Some(0))),\n RegField(16-cfg.nAbstractDataWords),\n WNotifyVal(cfg.nProgramBufferWords, ABSTRACTAUTORdData.autoexecprogbuf, ABSTRACTAUTOWrData.autoexecprogbuf, autoexecprogbufWrEnMaybe,\n RegFieldDesc(\"autoexecprogbuf\", \"abstract command progbuf autoexec\", reset=Some(0))))),\n (DMI_COMMAND << 2) -> RegFieldGroup(\"dmi_command\", Some(\"Abstract Command Register\"),\n Seq(RWNotify(32, COMMANDRdData.asUInt, COMMANDWrDataVal, COMMANDRdEn, COMMANDWrEnMaybe,\n Some(RegFieldDesc(\"dmi_command\", \"abstract command register\", reset=Some(0), volatile=true))))),\n (DMI_DATA0 << 2) -> RegFieldGroup(\"dmi_data\", Some(\"abstract command data registers\"), abstractDataMem.zipWithIndex.map{case (x, i) =>\n RWNotify(8, Mux(dmAuthenticated, x, 0.U), abstractDataNxt(i),\n dmiAbstractDataRdEn(i),\n dmiAbstractDataWrEnMaybe(i),\n Some(RegFieldDesc(s\"dmi_data_$i\", s\"abstract command data register $i\", reset = Some(0), volatile=true)))}, false),\n (DMI_PROGBUF0 << 2) -> RegFieldGroup(\"dmi_progbuf\", Some(\"abstract command progbuf registers\"), programBufferMem.zipWithIndex.map{case (x, i) =>\n RWNotify(8, Mux(dmAuthenticated, x, 0.U), programBufferNxt(i),\n dmiProgramBufferRdEn(i),\n dmiProgramBufferWrEnMaybe(i),\n Some(RegFieldDesc(s\"dmi_progbuf_$i\", s\"abstract command progbuf register $i\", reset = Some(0))))}, false),\n (DMI_AUTHDATA << 2) -> (if (cfg.hasAuthentication) RegFieldGroup(\"dmi_authdata\", Some(\"authentication data exchange register\"),\n Seq(RWNotify(32, io.auth.get.dmAuthRdata, io.auth.get.dmAuthWdata, authRdEnMaybe, authWrEnMaybe,\n Some(RegFieldDesc(\"authdata\", \"authentication data exchange\", volatile=true))))) else Nil),\n (DMI_SBCS << 2) -> sbcsFields,\n (DMI_SBDATA0 << 2) -> sbDataFields(0),\n (DMI_SBDATA1 << 2) -> sbDataFields(1),\n (DMI_SBDATA2 << 2) -> sbDataFields(2),\n (DMI_SBDATA3 << 2) -> sbDataFields(3),\n (DMI_SBADDRESS0 << 2) -> sbAddrFields(0),\n (DMI_SBADDRESS1 << 2) -> sbAddrFields(1),\n (DMI_SBADDRESS2 << 2) -> sbAddrFields(2),\n (DMI_SBADDRESS3 << 2) -> sbAddrFields(3) \n )\n\n // Abstract data mem is written by both the tile link interface and DMI...\n abstractDataMem.zipWithIndex.foreach { case (x, i) =>\n when (dmAuthenticated && dmiAbstractDataWrEnMaybe(i) && dmiAbstractDataAccessLegal) {\n x := abstractDataNxt(i)\n }\n }\n // ... and also by custom register read (if implemented)\n val (customs, customParams) = customNode.in.unzip\n val needCustom = (customs.size > 0) && (customParams.head.addrs.size > 0)\n def getNeedCustom = () => needCustom\n\n if (needCustom) {\n val (custom, customP) = customNode.in.head\n require(customP.width % 8 == 0, s\"Debug Custom width must be divisible by 8, not ${customP.width}\")\n val custom_data = custom.data.asBools\n val custom_bytes = Seq.tabulate(customP.width/8){i => custom_data.slice(i*8, (i+1)*8).asUInt}\n when (custom.ready && custom.valid) {\n (abstractDataMem zip custom_bytes).zipWithIndex.foreach {case ((a, b), i) =>\n a := b\n }\n }\n }\n\n programBufferMem.zipWithIndex.foreach { case (x, i) =>\n when (dmAuthenticated && dmiProgramBufferWrEnMaybe(i) && dmiProgramBufferAccessLegal) {\n x := programBufferNxt(i)\n }\n }\n\n //--------------------------------------------------------------\n // \"Variable\" ROM Generation\n //--------------------------------------------------------------\n\n val goReg = Reg(Bool())\n val goAbstract = WireInit(false.B)\n val goCustom = WireInit(false.B)\n val jalAbstract = WireInit(Instructions.JAL.value.U.asTypeOf(new GeneratedUJ()))\n jalAbstract.setImm(ABSTRACT(cfg) - WHERETO)\n\n when (~io.dmactive){\n goReg := false.B\n }.otherwise {\n when (goAbstract) {\n goReg := true.B\n }.elsewhen (hartGoingWrEn){\n assert(hartGoingId === 0.U, \"Unexpected 'GOING' hart.\")//Chisel3 #540 %x, expected %x\", hartGoingId, 0.U)\n goReg := false.B\n }\n }\n\n class flagBundle extends Bundle {\n val reserved = UInt(6.W)\n val resume = Bool()\n val go = Bool()\n }\n\n val flags = WireInit(VecInit(Seq.fill(1 << selectedHartReg.getWidth) {0.U.asTypeOf(new flagBundle())} ))\n assert ((hartSelFuncs.hartSelToHartId(selectedHartReg) < flags.size.U),\n s\"HartSel to HartId Mapping is illegal for this Debug Implementation, because HartID must be < ${flags.size} for it to work.\")\n flags(hartSelFuncs.hartSelToHartId(selectedHartReg)).go := goReg\n\n for (component <- 0 until nComponents) {\n val componentSel = WireInit(component.U)\n flags(hartSelFuncs.hartSelToHartId(componentSel)).resume := resumeReqRegs(component)\n }\n\n //----------------------------\n // Abstract Command Decoding & Generation\n //----------------------------\n\n val accessRegisterCommandWr = WireInit(COMMANDWrData.asUInt.asTypeOf(new ACCESS_REGISTERFields()))\n /** real COMMAND*/\n val accessRegisterCommandReg = WireInit(COMMANDReg.asUInt.asTypeOf(new ACCESS_REGISTERFields()))\n\n // TODO: Quick Access\n\n class GeneratedI extends Bundle {\n val imm = UInt(12.W)\n val rs1 = UInt(5.W)\n val funct3 = UInt(3.W)\n val rd = UInt(5.W)\n val opcode = UInt(7.W)\n }\n\n class GeneratedS extends Bundle {\n val immhi = UInt(7.W)\n val rs2 = UInt(5.W)\n val rs1 = UInt(5.W)\n val funct3 = UInt(3.W)\n val immlo = UInt(5.W)\n val opcode = UInt(7.W)\n }\n\n class GeneratedCSR extends Bundle {\n val imm = UInt(12.W)\n val rs1 = UInt(5.W)\n val funct3 = UInt(3.W)\n val rd = UInt(5.W)\n val opcode = UInt(7.W)\n }\n\n class GeneratedUJ extends Bundle {\n val imm3 = UInt(1.W)\n val imm0 = UInt(10.W)\n val imm1 = UInt(1.W)\n val imm2 = UInt(8.W)\n val rd = UInt(5.W)\n val opcode = UInt(7.W)\n\n def setImm(imm: Int) : Unit = {\n // TODO: Check bounds of imm.\n\n require(imm % 2 == 0, \"Immediate must be even for UJ encoding.\")\n val immWire = WireInit(imm.S(21.W))\n val immBits = WireInit(VecInit(immWire.asBools))\n\n imm0 := immBits.slice(1, 1 + 10).asUInt\n imm1 := immBits.slice(11, 11 + 11).asUInt\n imm2 := immBits.slice(12, 12 + 8).asUInt\n imm3 := immBits.slice(20, 20 + 1).asUInt\n }\n }\n\n require((cfg.atzero && cfg.nAbstractInstructions == 2) || (!cfg.atzero && cfg.nAbstractInstructions == 5),\n \"Mismatch between DebugModuleParams atzero and nAbstractInstructions\")\n val abstractGeneratedMem = Reg(Vec(cfg.nAbstractInstructions, (UInt(32.W))))\n\n def abstractGeneratedI(cfg: DebugModuleParams): UInt = {\n val inst = Wire(new GeneratedI())\n val offset = if (cfg.atzero) DATA else (DATA-0x800) & 0xFFF\n val base = if (cfg.atzero) 0.U else Mux(accessRegisterCommandReg.regno(0), 8.U, 9.U)\n inst.opcode := (Instructions.LW.value.U.asTypeOf(new GeneratedI())).opcode\n inst.rd := (accessRegisterCommandReg.regno & 0x1F.U)\n inst.funct3 := accessRegisterCommandReg.size\n inst.rs1 := base\n inst.imm := offset.U\n inst.asUInt\n }\n\n def abstractGeneratedS(cfg: DebugModuleParams): UInt = {\n val inst = Wire(new GeneratedS())\n val offset = if (cfg.atzero) DATA else (DATA-0x800) & 0xFFF\n val base = if (cfg.atzero) 0.U else Mux(accessRegisterCommandReg.regno(0), 8.U, 9.U)\n inst.opcode := (Instructions.SW.value.U.asTypeOf(new GeneratedS())).opcode\n inst.immlo := (offset & 0x1F).U\n inst.funct3 := accessRegisterCommandReg.size\n inst.rs1 := base\n inst.rs2 := (accessRegisterCommandReg.regno & 0x1F.U)\n inst.immhi := (offset >> 5).U\n inst.asUInt\n }\n\n def abstractGeneratedCSR: UInt = {\n val inst = Wire(new GeneratedCSR())\n val base = Mux(accessRegisterCommandReg.regno(0), 8.U, 9.U) // use s0 as base for odd regs, s1 as base for even regs\n inst := (Instructions.CSRRW.value.U.asTypeOf(new GeneratedCSR()))\n inst.imm := CSRs.dscratch1.U\n inst.rs1 := base\n inst.rd := base\n inst.asUInt\n }\n\n val nop = Wire(new GeneratedI())\n nop := Instructions.ADDI.value.U.asTypeOf(new GeneratedI())\n nop.rd := 0.U\n nop.rs1 := 0.U\n nop.imm := 0.U\n\n val isa = Wire(new GeneratedI())\n isa := Instructions.ADDIW.value.U.asTypeOf(new GeneratedI())\n isa.rd := 0.U\n isa.rs1 := 0.U\n isa.imm := 0.U\n\n\n when (goAbstract) {\n if (cfg.nAbstractInstructions == 2) {\n // ABSTRACT(0): Transfer: LW or SW, else NOP\n // ABSTRACT(1): Postexec: NOP else EBREAK\n abstractGeneratedMem(0) := Mux(accessRegisterCommandReg.transfer,\n Mux(accessRegisterCommandReg.write, abstractGeneratedI(cfg), abstractGeneratedS(cfg)),\n nop.asUInt\n )\n abstractGeneratedMem(1) := Mux(accessRegisterCommandReg.postexec,\n nop.asUInt,\n Instructions.EBREAK.value.U)\n } else {\n // Entry: All regs in GPRs, dscratch1=offset 0x800 in DM\n // ABSTRACT(0): CheckISA: ADDW or NOP (exception here if size=3 and not RV64)\n // ABSTRACT(1): CSRRW s1,dscratch1,s1 or CSRRW s0,dscratch1,s0\n // ABSTRACT(2): Transfer: LW, SW, LD, SD else NOP\n // ABSTRACT(3): CSRRW s1,dscratch1,s1 or CSRRW s0,dscratch1,s0\n // ABSTRACT(4): Postexec: NOP else EBREAK\n abstractGeneratedMem(0) := Mux(accessRegisterCommandReg.transfer && accessRegisterCommandReg.size =/= 2.U, isa.asUInt, nop.asUInt)\n abstractGeneratedMem(1) := abstractGeneratedCSR\n abstractGeneratedMem(2) := Mux(accessRegisterCommandReg.transfer,\n Mux(accessRegisterCommandReg.write, abstractGeneratedI(cfg), abstractGeneratedS(cfg)),\n nop.asUInt\n )\n abstractGeneratedMem(3) := abstractGeneratedCSR\n abstractGeneratedMem(4) := Mux(accessRegisterCommandReg.postexec,\n nop.asUInt,\n Instructions.EBREAK.value.U)\n }\n }\n\n //--------------------------------------------------------------\n // Drive Custom Access\n //--------------------------------------------------------------\n if (needCustom) {\n val (custom, customP) = customNode.in.head\n custom.addr := accessRegisterCommandReg.regno\n custom.valid := goCustom\n }\n //--------------------------------------------------------------\n // Hart Bus Access\n //--------------------------------------------------------------\n\n tlNode.regmap(\n // This memory is writable.\n HALTED -> Seq(WNotifyWire(sbIdWidth, hartHaltedId, hartHaltedWrEn,\n \"debug_hart_halted\", \"Debug ROM Causes hart to write its hartID here when it is in Debug Mode.\")),\n GOING -> Seq(WNotifyWire(sbIdWidth, hartGoingId, hartGoingWrEn,\n \"debug_hart_going\", \"Debug ROM causes hart to write 0 here when it begins executing Debug Mode instructions.\")),\n RESUMING -> Seq(WNotifyWire(sbIdWidth, hartResumingId, hartResumingWrEn,\n \"debug_hart_resuming\", \"Debug ROM causes hart to write its hartID here when it leaves Debug Mode.\")),\n EXCEPTION -> Seq(WNotifyWire(sbIdWidth, hartExceptionId, hartExceptionWrEn,\n \"debug_hart_exception\", \"Debug ROM causes hart to write 0 here if it gets an exception in Debug Mode.\")),\n DATA -> RegFieldGroup(\"debug_data\", Some(\"Data used to communicate with Debug Module\"),\n abstractDataMem.zipWithIndex.map {case (x, i) => RegField(8, x, RegFieldDesc(s\"debug_data_$i\", \"\"))}),\n PROGBUF(cfg)-> RegFieldGroup(\"debug_progbuf\", Some(\"Program buffer used to communicate with Debug Module\"),\n programBufferMem.zipWithIndex.map {case (x, i) => RegField(8, x, RegFieldDesc(s\"debug_progbuf_$i\", \"\"))}),\n\n // These sections are read-only.\n IMPEBREAK(cfg)-> {if (cfg.hasImplicitEbreak) Seq(RegField.r(32, Instructions.EBREAK.value.U,\n RegFieldDesc(\"debug_impebreak\", \"Debug Implicit EBREAK\", reset=Some(Instructions.EBREAK.value)))) else Nil},\n WHERETO -> Seq(RegField.r(32, jalAbstract.asUInt, RegFieldDesc(\"debug_whereto\", \"Instruction filled in by Debug Module to control hart in Debug Mode\", volatile = true))),\n ABSTRACT(cfg) -> RegFieldGroup(\"debug_abstract\", Some(\"Instructions generated by Debug Module\"),\n abstractGeneratedMem.zipWithIndex.map{ case (x,i) => RegField.r(32, x, RegFieldDesc(s\"debug_abstract_$i\", \"\", volatile=true))}),\n FLAGS -> RegFieldGroup(\"debug_flags\", Some(\"Memory region used to control hart going/resuming in Debug Mode\"),\n if (nComponents == 1) {\n Seq.tabulate(1024) { i => RegField.r(8, flags(0).asUInt, RegFieldDesc(s\"debug_flags_$i\", \"\", volatile=true)) }\n } else {\n flags.zipWithIndex.map{case(x, i) => RegField.r(8, x.asUInt, RegFieldDesc(s\"debug_flags_$i\", \"\", volatile=true))}\n }),\n ROMBASE -> RegFieldGroup(\"debug_rom\", Some(\"Debug ROM\"),\n (if (cfg.atzero) DebugRomContents() else DebugRomNonzeroContents()).zipWithIndex.map{case (x, i) =>\n RegField.r(8, (x & 0xFF).U(8.W), RegFieldDesc(s\"debug_rom_$i\", \"\", reset=Some(x)))})\n )\n\n // Override System Bus accesses with dmactive reset.\n when (~io.dmactive){\n abstractDataMem.foreach {x => x := 0.U}\n programBufferMem.foreach {x => x := 0.U}\n }\n\n //--------------------------------------------------------------\n // Abstract Command State Machine\n //--------------------------------------------------------------\n\n object CtrlState extends scala.Enumeration {\n type CtrlState = Value\n val Waiting, CheckGenerate, Exec, Custom = Value\n\n def apply( t : Value) : UInt = {\n t.id.U(log2Up(values.size).W)\n }\n }\n import CtrlState._\n\n // This is not an initialization!\n val ctrlStateReg = Reg(chiselTypeOf(CtrlState(Waiting)))\n\n val hartHalted = haltedBitRegs(if (nComponents == 1) 0.U(0.W) else selectedHartReg)\n val ctrlStateNxt = WireInit(ctrlStateReg)\n\n //------------------------\n // DMI Register Control and Status\n\n abstractCommandBusy := (ctrlStateReg =/= CtrlState(Waiting))\n\n ABSTRACTCSWrEnLegal := (ctrlStateReg === CtrlState(Waiting))\n COMMANDWrEnLegal := (ctrlStateReg === CtrlState(Waiting))\n ABSTRACTAUTOWrEnLegal := (ctrlStateReg === CtrlState(Waiting))\n dmiAbstractDataAccessLegal := (ctrlStateReg === CtrlState(Waiting))\n dmiProgramBufferAccessLegal := (ctrlStateReg === CtrlState(Waiting))\n\n errorBusy := (ABSTRACTCSWrEnMaybe && ~ABSTRACTCSWrEnLegal) ||\n (autoexecdataWrEnMaybe && ~ABSTRACTAUTOWrEnLegal) ||\n (autoexecprogbufWrEnMaybe && ~ABSTRACTAUTOWrEnLegal) ||\n (COMMANDWrEnMaybe && ~COMMANDWrEnLegal) ||\n (dmiAbstractDataAccess && ~dmiAbstractDataAccessLegal) ||\n (dmiProgramBufferAccess && ~dmiProgramBufferAccessLegal)\n\n // TODO: Maybe Quick Access\n val commandWrIsAccessRegister = (COMMANDWrData.cmdtype === DebugAbstractCommandType.AccessRegister.id.U)\n val commandRegIsAccessRegister = (COMMANDReg.cmdtype === DebugAbstractCommandType.AccessRegister.id.U)\n\n val commandWrIsUnsupported = COMMANDWrEn && !commandWrIsAccessRegister\n\n val commandRegIsUnsupported = WireInit(true.B)\n val commandRegBadHaltResume = WireInit(false.B)\n\n // We only support abstract commands for GPRs and any custom registers, if specified.\n val accessRegIsLegalSize = (accessRegisterCommandReg.size === 2.U) || (accessRegisterCommandReg.size === 3.U)\n val accessRegIsGPR = (accessRegisterCommandReg.regno >= 0x1000.U && accessRegisterCommandReg.regno <= 0x101F.U) && accessRegIsLegalSize\n val accessRegIsCustom = if (needCustom) {\n val (custom, customP) = customNode.in.head\n customP.addrs.foldLeft(false.B){\n (result, current) => result || (current.U === accessRegisterCommandReg.regno)}\n } else false.B\n\n when (commandRegIsAccessRegister) {\n when (accessRegIsCustom && accessRegisterCommandReg.transfer && accessRegisterCommandReg.write === false.B) {\n commandRegIsUnsupported := false.B\n }.elsewhen (!accessRegisterCommandReg.transfer || accessRegIsGPR) {\n commandRegIsUnsupported := false.B\n commandRegBadHaltResume := ~hartHalted\n }\n }\n\n val wrAccessRegisterCommand = COMMANDWrEn && commandWrIsAccessRegister && (ABSTRACTCSReg.cmderr === 0.U)\n val regAccessRegisterCommand = autoexec && commandRegIsAccessRegister && (ABSTRACTCSReg.cmderr === 0.U)\n\n //------------------------\n // Variable ROM STATE MACHINE\n // -----------------------\n\n when (ctrlStateReg === CtrlState(Waiting)){\n when (wrAccessRegisterCommand || regAccessRegisterCommand) {\n ctrlStateNxt := CtrlState(CheckGenerate)\n }.elsewhen (commandWrIsUnsupported) { // These checks are really on the command type.\n errorUnsupported := true.B\n }.elsewhen (autoexec && commandRegIsUnsupported) {\n errorUnsupported := true.B\n }\n }.elsewhen (ctrlStateReg === CtrlState(CheckGenerate)){\n\n // We use this state to ensure that the COMMAND has been\n // registered by the time that we need to use it, to avoid\n // generating it directly from the COMMANDWrData.\n // This 'commandRegIsUnsupported' is really just checking the\n // AccessRegisterCommand parameters (regno)\n when (commandRegIsUnsupported) {\n errorUnsupported := true.B\n ctrlStateNxt := CtrlState(Waiting)\n }.elsewhen (commandRegBadHaltResume){\n errorHaltResume := true.B\n ctrlStateNxt := CtrlState(Waiting)\n }.otherwise {\n when(accessRegIsCustom) {\n ctrlStateNxt := CtrlState(Custom)\n }.otherwise {\n ctrlStateNxt := CtrlState(Exec)\n goAbstract := true.B\n }\n }\n }.elsewhen (ctrlStateReg === CtrlState(Exec)) {\n\n // We can't just look at 'hartHalted' here, because\n // hartHaltedWrEn is overloaded to mean 'got an ebreak'\n // which may have happened when we were already halted.\n when(goReg === false.B && hartHaltedWrEn && (hartSelFuncs.hartIdToHartSel(hartHaltedId) === selectedHartReg)){\n ctrlStateNxt := CtrlState(Waiting)\n }\n when(hartExceptionWrEn) {\n assert(hartExceptionId === 0.U, \"Unexpected 'EXCEPTION' hart\")//Chisel3 #540, %x, expected %x\", hartExceptionId, 0.U)\n ctrlStateNxt := CtrlState(Waiting)\n errorException := true.B\n }\n }.elsewhen (ctrlStateReg === CtrlState(Custom)) {\n assert(needCustom.B, \"Should not be in custom state unless we need it.\")\n goCustom := true.B\n val (custom, customP) = customNode.in.head\n when (custom.ready && custom.valid) {\n ctrlStateNxt := CtrlState(Waiting)\n }\n }\n\n when (~io.dmactive || ~dmAuthenticated) {\n ctrlStateReg := CtrlState(Waiting)\n }.otherwise {\n ctrlStateReg := ctrlStateNxt\n }\n assert ((!io.dmactive || !hartExceptionWrEn || ctrlStateReg === CtrlState(Exec)),\n \"Unexpected EXCEPTION write: should only get it in Debug Module EXEC state\")\n }\n}\n\n// Wrapper around TL Debug Module Inner and an Async DMI Sink interface.\n// Handles the synchronization of dmactive, which is used as a synchronous reset\n// inside the Inner block.\n// Also is the Sink side of hartsel & resumereq fields of DMCONTROL.\nclass TLDebugModuleInnerAsync(device: Device, getNComponents: () => Int, beatBytes: Int)(implicit p: Parameters) extends LazyModule{\n\n val cfg = p(DebugModuleKey).get\n val dmInner = LazyModule(new TLDebugModuleInner(device, getNComponents, beatBytes))\n val dmiXing = LazyModule(new TLAsyncCrossingSink(AsyncQueueParams.singleton(safe=cfg.crossingHasSafeReset)))\n val dmiNode = dmiXing.node\n val tlNode = dmInner.tlNode\n\n dmInner.dmiNode := dmiXing.node\n\n // Require that there are no registers in TL interface, so that spurious\n // processor accesses to the DM don't need to enable the clock. We don't\n // require this property of the SBA, because the debugger is responsible for\n // raising dmactive (hence enabling the clock) during these transactions.\n require(dmInner.tlNode.concurrency == 0)\n\n lazy val module = new Impl\n class Impl extends LazyRawModuleImp(this) {\n\n // Clock/reset domains:\n // debug_clock / debug_reset = Debug inner domain\n // tl_clock / tl_reset = tilelink domain (External: clock / reset)\n //\n val io = IO(new Bundle {\n val debug_clock = Input(Clock())\n val debug_reset = Input(Reset())\n val tl_clock = Input(Clock())\n val tl_reset = Input(Reset())\n // These are all asynchronous and come from Outer\n /** reset signal for DM */\n val dmactive = Input(Bool())\n /** conrol signals for Inner\n *\n * generated in Outer\n */\n val innerCtrl = Flipped(new AsyncBundle(new DebugInternalBundle(getNComponents()), AsyncQueueParams.singleton(safe=cfg.crossingHasSafeReset)))\n // This comes from tlClk domain.\n /** debug available status */\n val debugUnavail = Input(Vec(getNComponents(), Bool()))\n /** debug interruption*/\n val hgDebugInt = Output(Vec(getNComponents(), Bool()))\n val extTrigger = (p(DebugModuleKey).get.nExtTriggers > 0).option(new DebugExtTriggerIO())\n /** vector to indicate which hart is in reset\n *\n * dm receives it from core and sends it to Inner\n */\n val hartIsInReset = Input(Vec(getNComponents(), Bool()))\n /** Debug Authentication signals from core */\n val auth = p(DebugModuleKey).get.hasAuthentication.option(new DebugAuthenticationIO())\n })\n val rf_reset = IO(Input(Reset())) // RF transform\n\n childClock := io.debug_clock\n childReset := io.debug_reset\n override def provideImplicitClockToLazyChildren = true\n\n val dmactive_synced = withClockAndReset(childClock, childReset) {\n val dmactive_synced = AsyncResetSynchronizerShiftReg(in=io.dmactive, sync=3, name=Some(\"dmactiveSync\"))\n dmInner.module.clock := io.debug_clock\n dmInner.module.reset := io.debug_reset\n dmInner.module.io.tl_clock := io.tl_clock\n dmInner.module.io.tl_reset := io.tl_reset\n dmInner.module.io.dmactive := dmactive_synced\n dmInner.module.io.innerCtrl <> FromAsyncBundle(io.innerCtrl)\n dmInner.module.io.debugUnavail := io.debugUnavail\n io.hgDebugInt := dmInner.module.io.hgDebugInt\n io.extTrigger.foreach { x => dmInner.module.io.extTrigger.foreach {y => x <> y}}\n dmInner.module.io.hartIsInReset := io.hartIsInReset\n io.auth.foreach { x => dmInner.module.io.auth.foreach {y => x <> y}}\n dmactive_synced\n }\n }\n}\n\n/** Create a version of the TLDebugModule which includes a synchronization interface\n * internally for the DMI. This is no longer optional outside of this module\n * because the Clock must run when tl_clock isn't running or tl_reset is asserted.\n */\n\nclass TLDebugModule(beatBytes: Int)(implicit p: Parameters) extends LazyModule {\n\n val device = new SimpleDevice(\"debug-controller\", Seq(\"sifive,debug-013\",\"riscv,debug-013\")){\n override val alwaysExtended = true\n override def describe(resources: ResourceBindings): Description = {\n val Description(name, mapping) = super.describe(resources)\n val attach = Map(\n \"debug-attach\" -> (\n (if (p(ExportDebug).apb) Seq(ResourceString(\"apb\")) else Seq()) ++\n (if (p(ExportDebug).jtag) Seq(ResourceString(\"jtag\")) else Seq()) ++\n (if (p(ExportDebug).cjtag) Seq(ResourceString(\"cjtag\")) else Seq()) ++\n (if (p(ExportDebug).dmi) Seq(ResourceString(\"dmi\")) else Seq())))\n Description(name, mapping ++ attach)\n }\n }\n\n val dmOuter : TLDebugModuleOuterAsync = LazyModule(new TLDebugModuleOuterAsync(device)(p))\n val dmInner : TLDebugModuleInnerAsync = LazyModule(new TLDebugModuleInnerAsync(device, () => {dmOuter.dmOuter.intnode.edges.out.size}, beatBytes)(p))\n\n val node = dmInner.tlNode\n val intnode = dmOuter.intnode\n val apbNodeOpt = dmOuter.apbNodeOpt\n\n dmInner.dmiNode := dmOuter.dmiInnerNode\n\n lazy val module = new Impl\n class Impl extends LazyRawModuleImp(this) {\n val nComponents = dmOuter.dmOuter.intnode.edges.out.size\n\n // Clock/reset domains:\n // tl_clock / tl_reset = tilelink domain\n // debug_clock / debug_reset = Inner debug (synchronous to tl_clock)\n // apb_clock / apb_reset = Outer debug with APB\n // dmiClock / dmiReset = Outer debug without APB\n //\n val io = IO(new Bundle {\n val debug_clock = Input(Clock())\n val debug_reset = Input(Reset())\n val tl_clock = Input(Clock())\n val tl_reset = Input(Reset())\n\n /** Debug control signals generated in Outer */\n val ctrl = new DebugCtrlBundle(nComponents)\n /** Debug Module Interface bewteen DM and DTM\n *\n * The DTM provides access to one or more Debug Modules (DMs) using DMI\n */\n val dmi = (!p(ExportDebug).apb).option(Flipped(new ClockedDMIIO()))\n val apb_clock = p(ExportDebug).apb.option(Input(Clock()))\n val apb_reset = p(ExportDebug).apb.option(Input(Reset()))\n val extTrigger = (p(DebugModuleKey).get.nExtTriggers > 0).option(new DebugExtTriggerIO())\n /** vector to indicate which hart is in reset\n *\n * dm receives it from core and sends it to Inner\n */\n val hartIsInReset = Input(Vec(nComponents, Bool()))\n /** hart reset request generated by hartreset-logic in Outer */\n val hartResetReq = p(DebugModuleKey).get.hasHartResets.option(Output(Vec(nComponents, Bool())))\n /** Debug Authentication signals from core */\n val auth = p(DebugModuleKey).get.hasAuthentication.option(new DebugAuthenticationIO())\n })\n\n childClock := io.tl_clock\n childReset := io.tl_reset\n override def provideImplicitClockToLazyChildren = true\n\n dmOuter.module.io.dmi.foreach { dmOuterDMI =>\n dmOuterDMI <> io.dmi.get.dmi\n dmOuter.module.io.dmi_reset := io.dmi.get.dmiReset\n dmOuter.module.io.dmi_clock := io.dmi.get.dmiClock\n dmOuter.module.rf_reset := io.dmi.get.dmiReset\n }\n\n (io.apb_clock zip io.apb_reset) foreach { case (c, r) =>\n dmOuter.module.io.dmi_reset := r\n dmOuter.module.io.dmi_clock := c\n dmOuter.module.rf_reset := r\n }\n\n dmInner.module.rf_reset := io.debug_reset\n dmInner.module.io.debug_clock := io.debug_clock\n dmInner.module.io.debug_reset := io.debug_reset\n dmInner.module.io.tl_clock := io.tl_clock\n dmInner.module.io.tl_reset := io.tl_reset\n dmInner.module.io.innerCtrl <> dmOuter.module.io.innerCtrl\n dmInner.module.io.dmactive := dmOuter.module.io.ctrl.dmactive\n dmInner.module.io.debugUnavail := io.ctrl.debugUnavail\n dmOuter.module.io.hgDebugInt := dmInner.module.io.hgDebugInt\n\n io.ctrl <> dmOuter.module.io.ctrl\n io.extTrigger.foreach { x => dmInner.module.io.extTrigger.foreach {y => x <> y}}\n dmInner.module.io.hartIsInReset := io.hartIsInReset\n io.hartResetReq.foreach { x => dmOuter.module.io.hartResetReq.foreach {y => x := y}}\n io.auth.foreach { x => dmOuter.module.io.dmAuthenticated.get := x.dmAuthenticated }\n io.auth.foreach { x => dmInner.module.io.auth.foreach {y => x <> y}}\n }\n}\n"},"response":{"kind":"string","value":"module TLDebugModule(\t// @[Debug.scala:1959:9]\n input auto_dmInner_dmInner_sb2tlOpt_out_a_ready,\t// @[LazyModuleImp.scala:107:25]\n output auto_dmInner_dmInner_sb2tlOpt_out_a_valid,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_dmInner_dmInner_sb2tlOpt_out_a_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n output [3:0] auto_dmInner_dmInner_sb2tlOpt_out_a_bits_size,\t// @[LazyModuleImp.scala:107:25]\n output [31:0] auto_dmInner_dmInner_sb2tlOpt_out_a_bits_address,\t// @[LazyModuleImp.scala:107:25]\n output [7:0] auto_dmInner_dmInner_sb2tlOpt_out_a_bits_data,\t// @[LazyModuleImp.scala:107:25]\n output auto_dmInner_dmInner_sb2tlOpt_out_d_ready,\t// @[LazyModuleImp.scala:107:25]\n input auto_dmInner_dmInner_sb2tlOpt_out_d_valid,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_dmInner_dmInner_sb2tlOpt_out_d_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_dmInner_dmInner_sb2tlOpt_out_d_bits_param,\t// @[LazyModuleImp.scala:107:25]\n input [3:0] auto_dmInner_dmInner_sb2tlOpt_out_d_bits_size,\t// @[LazyModuleImp.scala:107:25]\n input [4:0] auto_dmInner_dmInner_sb2tlOpt_out_d_bits_sink,\t// @[LazyModuleImp.scala:107:25]\n input auto_dmInner_dmInner_sb2tlOpt_out_d_bits_denied,\t// @[LazyModuleImp.scala:107:25]\n input [7:0] auto_dmInner_dmInner_sb2tlOpt_out_d_bits_data,\t// @[LazyModuleImp.scala:107:25]\n input auto_dmInner_dmInner_sb2tlOpt_out_d_bits_corrupt,\t// @[LazyModuleImp.scala:107:25]\n output auto_dmInner_dmInner_tl_in_a_ready,\t// @[LazyModuleImp.scala:107:25]\n input auto_dmInner_dmInner_tl_in_a_valid,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_dmInner_dmInner_tl_in_a_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_dmInner_dmInner_tl_in_a_bits_param,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_dmInner_dmInner_tl_in_a_bits_size,\t// @[LazyModuleImp.scala:107:25]\n input [12:0] auto_dmInner_dmInner_tl_in_a_bits_source,\t// @[LazyModuleImp.scala:107:25]\n input [11:0] auto_dmInner_dmInner_tl_in_a_bits_address,\t// @[LazyModuleImp.scala:107:25]\n input [7:0] auto_dmInner_dmInner_tl_in_a_bits_mask,\t// @[LazyModuleImp.scala:107:25]\n input [63:0] auto_dmInner_dmInner_tl_in_a_bits_data,\t// @[LazyModuleImp.scala:107:25]\n input auto_dmInner_dmInner_tl_in_a_bits_corrupt,\t// @[LazyModuleImp.scala:107:25]\n input auto_dmInner_dmInner_tl_in_d_ready,\t// @[LazyModuleImp.scala:107:25]\n output auto_dmInner_dmInner_tl_in_d_valid,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_dmInner_dmInner_tl_in_d_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n output [1:0] auto_dmInner_dmInner_tl_in_d_bits_size,\t// @[LazyModuleImp.scala:107:25]\n output [12:0] auto_dmInner_dmInner_tl_in_d_bits_source,\t// @[LazyModuleImp.scala:107:25]\n output [63:0] auto_dmInner_dmInner_tl_in_d_bits_data,\t// @[LazyModuleImp.scala:107:25]\n output auto_dmOuter_int_out_sync_0,\t// @[LazyModuleImp.scala:107:25]\n input io_debug_clock,\t// @[Debug.scala:1968:16]\n input io_debug_reset,\t// @[Debug.scala:1968:16]\n input io_tl_clock,\t// @[Debug.scala:1968:16]\n input io_tl_reset,\t// @[Debug.scala:1968:16]\n output io_ctrl_ndreset,\t// @[Debug.scala:1968:16]\n output io_ctrl_dmactive,\t// @[Debug.scala:1968:16]\n input io_ctrl_dmactiveAck,\t// @[Debug.scala:1968:16]\n output io_dmi_dmi_req_ready,\t// @[Debug.scala:1968:16]\n input io_dmi_dmi_req_valid,\t// @[Debug.scala:1968:16]\n input [6:0] io_dmi_dmi_req_bits_addr,\t// @[Debug.scala:1968:16]\n input [31:0] io_dmi_dmi_req_bits_data,\t// @[Debug.scala:1968:16]\n input [1:0] io_dmi_dmi_req_bits_op,\t// @[Debug.scala:1968:16]\n input io_dmi_dmi_resp_ready,\t// @[Debug.scala:1968:16]\n output io_dmi_dmi_resp_valid,\t// @[Debug.scala:1968:16]\n output [31:0] io_dmi_dmi_resp_bits_data,\t// @[Debug.scala:1968:16]\n output [1:0] io_dmi_dmi_resp_bits_resp,\t// @[Debug.scala:1968:16]\n input io_dmi_dmiClock,\t// @[Debug.scala:1968:16]\n input io_dmi_dmiReset,\t// @[Debug.scala:1968:16]\n input io_hartIsInReset_0\t// @[Debug.scala:1968:16]\n);\n\n wire _dmInner_auto_dmiXing_in_a_ridx;\t// @[Debug.scala:1950:53]\n wire _dmInner_auto_dmiXing_in_a_safe_ridx_valid;\t// @[Debug.scala:1950:53]\n wire _dmInner_auto_dmiXing_in_a_safe_sink_reset_n;\t// @[Debug.scala:1950:53]\n wire [2:0] _dmInner_auto_dmiXing_in_d_mem_0_opcode;\t// @[Debug.scala:1950:53]\n wire [1:0] _dmInner_auto_dmiXing_in_d_mem_0_size;\t// @[Debug.scala:1950:53]\n wire _dmInner_auto_dmiXing_in_d_mem_0_source;\t// @[Debug.scala:1950:53]\n wire [31:0] _dmInner_auto_dmiXing_in_d_mem_0_data;\t// @[Debug.scala:1950:53]\n wire _dmInner_auto_dmiXing_in_d_widx;\t// @[Debug.scala:1950:53]\n wire _dmInner_auto_dmiXing_in_d_safe_widx_valid;\t// @[Debug.scala:1950:53]\n wire _dmInner_auto_dmiXing_in_d_safe_source_reset_n;\t// @[Debug.scala:1950:53]\n wire _dmInner_io_innerCtrl_ridx;\t// @[Debug.scala:1950:53]\n wire _dmInner_io_innerCtrl_safe_ridx_valid;\t// @[Debug.scala:1950:53]\n wire _dmInner_io_innerCtrl_safe_sink_reset_n;\t// @[Debug.scala:1950:53]\n wire _dmInner_io_hgDebugInt_0;\t// @[Debug.scala:1950:53]\n wire [2:0] _dmOuter_auto_asource_out_a_mem_0_opcode;\t// @[Debug.scala:1949:53]\n wire [8:0] _dmOuter_auto_asource_out_a_mem_0_address;\t// @[Debug.scala:1949:53]\n wire [31:0] _dmOuter_auto_asource_out_a_mem_0_data;\t// @[Debug.scala:1949:53]\n wire _dmOuter_auto_asource_out_a_widx;\t// @[Debug.scala:1949:53]\n wire _dmOuter_auto_asource_out_a_safe_widx_valid;\t// @[Debug.scala:1949:53]\n wire _dmOuter_auto_asource_out_a_safe_source_reset_n;\t// @[Debug.scala:1949:53]\n wire _dmOuter_auto_asource_out_d_ridx;\t// @[Debug.scala:1949:53]\n wire _dmOuter_auto_asource_out_d_safe_ridx_valid;\t// @[Debug.scala:1949:53]\n wire _dmOuter_auto_asource_out_d_safe_sink_reset_n;\t// @[Debug.scala:1949:53]\n wire _dmOuter_io_ctrl_dmactive;\t// @[Debug.scala:1949:53]\n wire _dmOuter_io_innerCtrl_mem_0_resumereq;\t// @[Debug.scala:1949:53]\n wire [9:0] _dmOuter_io_innerCtrl_mem_0_hartsel;\t// @[Debug.scala:1949:53]\n wire _dmOuter_io_innerCtrl_mem_0_ackhavereset;\t// @[Debug.scala:1949:53]\n wire _dmOuter_io_innerCtrl_mem_0_hrmask_0;\t// @[Debug.scala:1949:53]\n wire _dmOuter_io_innerCtrl_widx;\t// @[Debug.scala:1949:53]\n wire _dmOuter_io_innerCtrl_safe_widx_valid;\t// @[Debug.scala:1949:53]\n wire _dmOuter_io_innerCtrl_safe_source_reset_n;\t// @[Debug.scala:1949:53]\n wire auto_dmInner_dmInner_sb2tlOpt_out_a_ready_0 = auto_dmInner_dmInner_sb2tlOpt_out_a_ready;\t// @[Debug.scala:1959:9]\n wire auto_dmInner_dmInner_sb2tlOpt_out_d_valid_0 = auto_dmInner_dmInner_sb2tlOpt_out_d_valid;\t// @[Debug.scala:1959:9]\n wire [2:0] auto_dmInner_dmInner_sb2tlOpt_out_d_bits_opcode_0 = auto_dmInner_dmInner_sb2tlOpt_out_d_bits_opcode;\t// @[Debug.scala:1959:9]\n wire [1:0] auto_dmInner_dmInner_sb2tlOpt_out_d_bits_param_0 = auto_dmInner_dmInner_sb2tlOpt_out_d_bits_param;\t// @[Debug.scala:1959:9]\n wire [3:0] auto_dmInner_dmInner_sb2tlOpt_out_d_bits_size_0 = auto_dmInner_dmInner_sb2tlOpt_out_d_bits_size;\t// @[Debug.scala:1959:9]\n wire [4:0] auto_dmInner_dmInner_sb2tlOpt_out_d_bits_sink_0 = auto_dmInner_dmInner_sb2tlOpt_out_d_bits_sink;\t// @[Debug.scala:1959:9]\n wire auto_dmInner_dmInner_sb2tlOpt_out_d_bits_denied_0 = auto_dmInner_dmInner_sb2tlOpt_out_d_bits_denied;\t// @[Debug.scala:1959:9]\n wire [7:0] auto_dmInner_dmInner_sb2tlOpt_out_d_bits_data_0 = auto_dmInner_dmInner_sb2tlOpt_out_d_bits_data;\t// @[Debug.scala:1959:9]\n wire auto_dmInner_dmInner_sb2tlOpt_out_d_bits_corrupt_0 = auto_dmInner_dmInner_sb2tlOpt_out_d_bits_corrupt;\t// @[Debug.scala:1959:9]\n wire auto_dmInner_dmInner_tl_in_a_valid_0 = auto_dmInner_dmInner_tl_in_a_valid;\t// @[Debug.scala:1959:9]\n wire [2:0] auto_dmInner_dmInner_tl_in_a_bits_opcode_0 = auto_dmInner_dmInner_tl_in_a_bits_opcode;\t// @[Debug.scala:1959:9]\n wire [2:0] auto_dmInner_dmInner_tl_in_a_bits_param_0 = auto_dmInner_dmInner_tl_in_a_bits_param;\t// @[Debug.scala:1959:9]\n wire [1:0] auto_dmInner_dmInner_tl_in_a_bits_size_0 = auto_dmInner_dmInner_tl_in_a_bits_size;\t// @[Debug.scala:1959:9]\n wire [12:0] auto_dmInner_dmInner_tl_in_a_bits_source_0 = auto_dmInner_dmInner_tl_in_a_bits_source;\t// @[Debug.scala:1959:9]\n wire [11:0] auto_dmInner_dmInner_tl_in_a_bits_address_0 = auto_dmInner_dmInner_tl_in_a_bits_address;\t// @[Debug.scala:1959:9]\n wire [7:0] auto_dmInner_dmInner_tl_in_a_bits_mask_0 = auto_dmInner_dmInner_tl_in_a_bits_mask;\t// @[Debug.scala:1959:9]\n wire [63:0] auto_dmInner_dmInner_tl_in_a_bits_data_0 = auto_dmInner_dmInner_tl_in_a_bits_data;\t// @[Debug.scala:1959:9]\n wire auto_dmInner_dmInner_tl_in_a_bits_corrupt_0 = auto_dmInner_dmInner_tl_in_a_bits_corrupt;\t// @[Debug.scala:1959:9]\n wire auto_dmInner_dmInner_tl_in_d_ready_0 = auto_dmInner_dmInner_tl_in_d_ready;\t// @[Debug.scala:1959:9]\n wire io_debug_clock_0 = io_debug_clock;\t// @[Debug.scala:1959:9]\n wire io_debug_reset_0 = io_debug_reset;\t// @[Debug.scala:1959:9]\n wire io_tl_clock_0 = io_tl_clock;\t// @[Debug.scala:1959:9]\n wire io_tl_reset_0 = io_tl_reset;\t// @[Debug.scala:1959:9]\n wire io_ctrl_dmactiveAck_0 = io_ctrl_dmactiveAck;\t// @[Debug.scala:1959:9]\n wire io_dmi_dmi_req_valid_0 = io_dmi_dmi_req_valid;\t// @[Debug.scala:1959:9]\n wire [6:0] io_dmi_dmi_req_bits_addr_0 = io_dmi_dmi_req_bits_addr;\t// @[Debug.scala:1959:9]\n wire [31:0] io_dmi_dmi_req_bits_data_0 = io_dmi_dmi_req_bits_data;\t// @[Debug.scala:1959:9]\n wire [1:0] io_dmi_dmi_req_bits_op_0 = io_dmi_dmi_req_bits_op;\t// @[Debug.scala:1959:9]\n wire io_dmi_dmi_resp_ready_0 = io_dmi_dmi_resp_ready;\t// @[Debug.scala:1959:9]\n wire io_dmi_dmiClock_0 = io_dmi_dmiClock;\t// @[Debug.scala:1959:9]\n wire io_dmi_dmiReset_0 = io_dmi_dmiReset;\t// @[Debug.scala:1959:9]\n wire io_hartIsInReset_0_0 = io_hartIsInReset_0;\t// @[Debug.scala:1959:9]\n wire auto_dmInner_dmInner_sb2tlOpt_out_a_bits_source = 1'h0;\t// @[Debug.scala:1959:9]\n wire auto_dmInner_dmInner_sb2tlOpt_out_a_bits_corrupt = 1'h0;\t// @[Debug.scala:1959:9]\n wire auto_dmInner_dmInner_sb2tlOpt_out_d_bits_source = 1'h0;\t// @[Debug.scala:1959:9]\n wire auto_dmInner_dmInner_custom_in_addr = 1'h0;\t// @[Debug.scala:1959:9]\n wire auto_dmInner_dmInner_custom_in_ready = 1'h0;\t// @[Debug.scala:1959:9]\n wire auto_dmInner_dmInner_custom_in_valid = 1'h0;\t// @[Debug.scala:1959:9]\n wire auto_dmInner_dmInner_tl_in_d_bits_sink = 1'h0;\t// @[Debug.scala:1959:9]\n wire auto_dmInner_dmInner_tl_in_d_bits_denied = 1'h0;\t// @[Debug.scala:1959:9]\n wire auto_dmInner_dmInner_tl_in_d_bits_corrupt = 1'h0;\t// @[Debug.scala:1959:9]\n wire io_ctrl_debugUnavail_0 = 1'h0;\t// @[Debug.scala:1959:9]\n wire _childClock_T = 1'h0;\t// @[LazyModuleImp.scala:160:25]\n wire [1:0] auto_dmInner_dmInner_tl_in_d_bits_param = 2'h0;\t// @[Debug.scala:1949:53, :1950:53, :1959:9]\n wire auto_dmInner_dmInner_sb2tlOpt_out_a_bits_mask = 1'h1;\t// @[Debug.scala:1950:53, :1959:9]\n wire [2:0] auto_dmInner_dmInner_sb2tlOpt_out_a_bits_param = 3'h0;\t// @[Debug.scala:1949:53, :1950:53, :1959:9]\n wire childClock = io_tl_clock_0;\t// @[Debug.scala:1959:9]\n wire childReset = io_tl_reset_0;\t// @[Debug.scala:1959:9]\n wire [2:0] auto_dmInner_dmInner_sb2tlOpt_out_a_bits_opcode_0;\t// @[Debug.scala:1959:9]\n wire [3:0] auto_dmInner_dmInner_sb2tlOpt_out_a_bits_size_0;\t// @[Debug.scala:1959:9]\n wire [31:0] auto_dmInner_dmInner_sb2tlOpt_out_a_bits_address_0;\t// @[Debug.scala:1959:9]\n wire [7:0] auto_dmInner_dmInner_sb2tlOpt_out_a_bits_data_0;\t// @[Debug.scala:1959:9]\n wire auto_dmInner_dmInner_sb2tlOpt_out_a_valid_0;\t// @[Debug.scala:1959:9]\n wire auto_dmInner_dmInner_sb2tlOpt_out_d_ready_0;\t// @[Debug.scala:1959:9]\n wire auto_dmInner_dmInner_tl_in_a_ready_0;\t// @[Debug.scala:1959:9]\n wire [2:0] auto_dmInner_dmInner_tl_in_d_bits_opcode_0;\t// @[Debug.scala:1959:9]\n wire [1:0] auto_dmInner_dmInner_tl_in_d_bits_size_0;\t// @[Debug.scala:1959:9]\n wire [12:0] auto_dmInner_dmInner_tl_in_d_bits_source_0;\t// @[Debug.scala:1959:9]\n wire [63:0] auto_dmInner_dmInner_tl_in_d_bits_data_0;\t// @[Debug.scala:1959:9]\n wire auto_dmInner_dmInner_tl_in_d_valid_0;\t// @[Debug.scala:1959:9]\n wire auto_dmOuter_int_out_sync_0_0;\t// @[Debug.scala:1959:9]\n wire io_ctrl_ndreset_0;\t// @[Debug.scala:1959:9]\n wire io_ctrl_dmactive_0;\t// @[Debug.scala:1959:9]\n wire io_dmi_dmi_req_ready_0;\t// @[Debug.scala:1959:9]\n wire [31:0] io_dmi_dmi_resp_bits_data_0;\t// @[Debug.scala:1959:9]\n wire [1:0] io_dmi_dmi_resp_bits_resp_0;\t// @[Debug.scala:1959:9]\n wire io_dmi_dmi_resp_valid_0;\t// @[Debug.scala:1959:9]\n TLDebugModuleOuterAsync dmOuter (\t// @[Debug.scala:1949:53]\n .auto_asource_out_a_mem_0_opcode (_dmOuter_auto_asource_out_a_mem_0_opcode),\n .auto_asource_out_a_mem_0_address (_dmOuter_auto_asource_out_a_mem_0_address),\n .auto_asource_out_a_mem_0_data (_dmOuter_auto_asource_out_a_mem_0_data),\n .auto_asource_out_a_ridx (_dmInner_auto_dmiXing_in_a_ridx),\t// @[Debug.scala:1950:53]\n .auto_asource_out_a_widx (_dmOuter_auto_asource_out_a_widx),\n .auto_asource_out_a_safe_ridx_valid (_dmInner_auto_dmiXing_in_a_safe_ridx_valid),\t// @[Debug.scala:1950:53]\n .auto_asource_out_a_safe_widx_valid (_dmOuter_auto_asource_out_a_safe_widx_valid),\n .auto_asource_out_a_safe_source_reset_n (_dmOuter_auto_asource_out_a_safe_source_reset_n),\n .auto_asource_out_a_safe_sink_reset_n (_dmInner_auto_dmiXing_in_a_safe_sink_reset_n),\t// @[Debug.scala:1950:53]\n .auto_asource_out_d_mem_0_opcode (_dmInner_auto_dmiXing_in_d_mem_0_opcode),\t// @[Debug.scala:1950:53]\n .auto_asource_out_d_mem_0_size (_dmInner_auto_dmiXing_in_d_mem_0_size),\t// @[Debug.scala:1950:53]\n .auto_asource_out_d_mem_0_source (_dmInner_auto_dmiXing_in_d_mem_0_source),\t// @[Debug.scala:1950:53]\n .auto_asource_out_d_mem_0_data (_dmInner_auto_dmiXing_in_d_mem_0_data),\t// @[Debug.scala:1950:53]\n .auto_asource_out_d_ridx (_dmOuter_auto_asource_out_d_ridx),\n .auto_asource_out_d_widx (_dmInner_auto_dmiXing_in_d_widx),\t// @[Debug.scala:1950:53]\n .auto_asource_out_d_safe_ridx_valid (_dmOuter_auto_asource_out_d_safe_ridx_valid),\n .auto_asource_out_d_safe_widx_valid (_dmInner_auto_dmiXing_in_d_safe_widx_valid),\t// @[Debug.scala:1950:53]\n .auto_asource_out_d_safe_source_reset_n (_dmInner_auto_dmiXing_in_d_safe_source_reset_n),\t// @[Debug.scala:1950:53]\n .auto_asource_out_d_safe_sink_reset_n (_dmOuter_auto_asource_out_d_safe_sink_reset_n),\n .auto_int_out_sync_0 (auto_dmOuter_int_out_sync_0_0),\n .io_dmi_clock (io_dmi_dmiClock_0),\t// @[Debug.scala:1959:9]\n .io_dmi_reset (io_dmi_dmiReset_0),\t// @[Debug.scala:1959:9]\n .io_dmi_req_ready (io_dmi_dmi_req_ready_0),\n .io_dmi_req_valid (io_dmi_dmi_req_valid_0),\t// @[Debug.scala:1959:9]\n .io_dmi_req_bits_addr (io_dmi_dmi_req_bits_addr_0),\t// @[Debug.scala:1959:9]\n .io_dmi_req_bits_data (io_dmi_dmi_req_bits_data_0),\t// @[Debug.scala:1959:9]\n .io_dmi_req_bits_op (io_dmi_dmi_req_bits_op_0),\t// @[Debug.scala:1959:9]\n .io_dmi_resp_ready (io_dmi_dmi_resp_ready_0),\t// @[Debug.scala:1959:9]\n .io_dmi_resp_valid (io_dmi_dmi_resp_valid_0),\n .io_dmi_resp_bits_data (io_dmi_dmi_resp_bits_data_0),\n .io_dmi_resp_bits_resp (io_dmi_dmi_resp_bits_resp_0),\n .io_ctrl_ndreset (io_ctrl_ndreset_0),\n .io_ctrl_dmactive (_dmOuter_io_ctrl_dmactive),\n .io_ctrl_dmactiveAck (io_ctrl_dmactiveAck_0),\t// @[Debug.scala:1959:9]\n .io_innerCtrl_mem_0_resumereq (_dmOuter_io_innerCtrl_mem_0_resumereq),\n .io_innerCtrl_mem_0_hartsel (_dmOuter_io_innerCtrl_mem_0_hartsel),\n .io_innerCtrl_mem_0_ackhavereset (_dmOuter_io_innerCtrl_mem_0_ackhavereset),\n .io_innerCtrl_mem_0_hrmask_0 (_dmOuter_io_innerCtrl_mem_0_hrmask_0),\n .io_innerCtrl_ridx (_dmInner_io_innerCtrl_ridx),\t// @[Debug.scala:1950:53]\n .io_innerCtrl_widx (_dmOuter_io_innerCtrl_widx),\n .io_innerCtrl_safe_ridx_valid (_dmInner_io_innerCtrl_safe_ridx_valid),\t// @[Debug.scala:1950:53]\n .io_innerCtrl_safe_widx_valid (_dmOuter_io_innerCtrl_safe_widx_valid),\n .io_innerCtrl_safe_source_reset_n (_dmOuter_io_innerCtrl_safe_source_reset_n),\n .io_innerCtrl_safe_sink_reset_n (_dmInner_io_innerCtrl_safe_sink_reset_n),\t// @[Debug.scala:1950:53]\n .io_hgDebugInt_0 (_dmInner_io_hgDebugInt_0),\t// @[Debug.scala:1950:53]\n .rf_reset (io_dmi_dmiReset_0)\t// @[Debug.scala:1959:9]\n );\t// @[Debug.scala:1949:53]\n assign io_ctrl_dmactive_0 = _dmOuter_io_ctrl_dmactive;\t// @[Debug.scala:1949:53, :1959:9]\n TLDebugModuleInnerAsync dmInner (\t// @[Debug.scala:1950:53]\n .auto_dmiXing_in_a_mem_0_opcode (_dmOuter_auto_asource_out_a_mem_0_opcode),\t// @[Debug.scala:1949:53]\n .auto_dmiXing_in_a_mem_0_address (_dmOuter_auto_asource_out_a_mem_0_address),\t// @[Debug.scala:1949:53]\n .auto_dmiXing_in_a_mem_0_data (_dmOuter_auto_asource_out_a_mem_0_data),\t// @[Debug.scala:1949:53]\n .auto_dmiXing_in_a_ridx (_dmInner_auto_dmiXing_in_a_ridx),\n .auto_dmiXing_in_a_widx (_dmOuter_auto_asource_out_a_widx),\t// @[Debug.scala:1949:53]\n .auto_dmiXing_in_a_safe_ridx_valid (_dmInner_auto_dmiXing_in_a_safe_ridx_valid),\n .auto_dmiXing_in_a_safe_widx_valid (_dmOuter_auto_asource_out_a_safe_widx_valid),\t// @[Debug.scala:1949:53]\n .auto_dmiXing_in_a_safe_source_reset_n (_dmOuter_auto_asource_out_a_safe_source_reset_n),\t// @[Debug.scala:1949:53]\n .auto_dmiXing_in_a_safe_sink_reset_n (_dmInner_auto_dmiXing_in_a_safe_sink_reset_n),\n .auto_dmiXing_in_d_mem_0_opcode (_dmInner_auto_dmiXing_in_d_mem_0_opcode),\n .auto_dmiXing_in_d_mem_0_size (_dmInner_auto_dmiXing_in_d_mem_0_size),\n .auto_dmiXing_in_d_mem_0_source (_dmInner_auto_dmiXing_in_d_mem_0_source),\n .auto_dmiXing_in_d_mem_0_data (_dmInner_auto_dmiXing_in_d_mem_0_data),\n .auto_dmiXing_in_d_ridx (_dmOuter_auto_asource_out_d_ridx),\t// @[Debug.scala:1949:53]\n .auto_dmiXing_in_d_widx (_dmInner_auto_dmiXing_in_d_widx),\n .auto_dmiXing_in_d_safe_ridx_valid (_dmOuter_auto_asource_out_d_safe_ridx_valid),\t// @[Debug.scala:1949:53]\n .auto_dmiXing_in_d_safe_widx_valid (_dmInner_auto_dmiXing_in_d_safe_widx_valid),\n .auto_dmiXing_in_d_safe_source_reset_n (_dmInner_auto_dmiXing_in_d_safe_source_reset_n),\n .auto_dmiXing_in_d_safe_sink_reset_n (_dmOuter_auto_asource_out_d_safe_sink_reset_n),\t// @[Debug.scala:1949:53]\n .auto_dmInner_sb2tlOpt_out_a_ready (auto_dmInner_dmInner_sb2tlOpt_out_a_ready_0),\t// @[Debug.scala:1959:9]\n .auto_dmInner_sb2tlOpt_out_a_valid (auto_dmInner_dmInner_sb2tlOpt_out_a_valid_0),\n .auto_dmInner_sb2tlOpt_out_a_bits_opcode (auto_dmInner_dmInner_sb2tlOpt_out_a_bits_opcode_0),\n .auto_dmInner_sb2tlOpt_out_a_bits_size (auto_dmInner_dmInner_sb2tlOpt_out_a_bits_size_0),\n .auto_dmInner_sb2tlOpt_out_a_bits_address (auto_dmInner_dmInner_sb2tlOpt_out_a_bits_address_0),\n .auto_dmInner_sb2tlOpt_out_a_bits_data (auto_dmInner_dmInner_sb2tlOpt_out_a_bits_data_0),\n .auto_dmInner_sb2tlOpt_out_d_ready (auto_dmInner_dmInner_sb2tlOpt_out_d_ready_0),\n .auto_dmInner_sb2tlOpt_out_d_valid (auto_dmInner_dmInner_sb2tlOpt_out_d_valid_0),\t// @[Debug.scala:1959:9]\n .auto_dmInner_sb2tlOpt_out_d_bits_opcode (auto_dmInner_dmInner_sb2tlOpt_out_d_bits_opcode_0),\t// @[Debug.scala:1959:9]\n .auto_dmInner_sb2tlOpt_out_d_bits_param (auto_dmInner_dmInner_sb2tlOpt_out_d_bits_param_0),\t// @[Debug.scala:1959:9]\n .auto_dmInner_sb2tlOpt_out_d_bits_size (auto_dmInner_dmInner_sb2tlOpt_out_d_bits_size_0),\t// @[Debug.scala:1959:9]\n .auto_dmInner_sb2tlOpt_out_d_bits_sink (auto_dmInner_dmInner_sb2tlOpt_out_d_bits_sink_0),\t// @[Debug.scala:1959:9]\n .auto_dmInner_sb2tlOpt_out_d_bits_denied (auto_dmInner_dmInner_sb2tlOpt_out_d_bits_denied_0),\t// @[Debug.scala:1959:9]\n .auto_dmInner_sb2tlOpt_out_d_bits_data (auto_dmInner_dmInner_sb2tlOpt_out_d_bits_data_0),\t// @[Debug.scala:1959:9]\n .auto_dmInner_sb2tlOpt_out_d_bits_corrupt (auto_dmInner_dmInner_sb2tlOpt_out_d_bits_corrupt_0),\t// @[Debug.scala:1959:9]\n .auto_dmInner_tl_in_a_ready (auto_dmInner_dmInner_tl_in_a_ready_0),\n .auto_dmInner_tl_in_a_valid (auto_dmInner_dmInner_tl_in_a_valid_0),\t// @[Debug.scala:1959:9]\n .auto_dmInner_tl_in_a_bits_opcode (auto_dmInner_dmInner_tl_in_a_bits_opcode_0),\t// @[Debug.scala:1959:9]\n .auto_dmInner_tl_in_a_bits_param (auto_dmInner_dmInner_tl_in_a_bits_param_0),\t// @[Debug.scala:1959:9]\n .auto_dmInner_tl_in_a_bits_size (auto_dmInner_dmInner_tl_in_a_bits_size_0),\t// @[Debug.scala:1959:9]\n .auto_dmInner_tl_in_a_bits_source (auto_dmInner_dmInner_tl_in_a_bits_source_0),\t// @[Debug.scala:1959:9]\n .auto_dmInner_tl_in_a_bits_address (auto_dmInner_dmInner_tl_in_a_bits_address_0),\t// @[Debug.scala:1959:9]\n .auto_dmInner_tl_in_a_bits_mask (auto_dmInner_dmInner_tl_in_a_bits_mask_0),\t// @[Debug.scala:1959:9]\n .auto_dmInner_tl_in_a_bits_data (auto_dmInner_dmInner_tl_in_a_bits_data_0),\t// @[Debug.scala:1959:9]\n .auto_dmInner_tl_in_a_bits_corrupt (auto_dmInner_dmInner_tl_in_a_bits_corrupt_0),\t// @[Debug.scala:1959:9]\n .auto_dmInner_tl_in_d_ready (auto_dmInner_dmInner_tl_in_d_ready_0),\t// @[Debug.scala:1959:9]\n .auto_dmInner_tl_in_d_valid (auto_dmInner_dmInner_tl_in_d_valid_0),\n .auto_dmInner_tl_in_d_bits_opcode (auto_dmInner_dmInner_tl_in_d_bits_opcode_0),\n .auto_dmInner_tl_in_d_bits_size (auto_dmInner_dmInner_tl_in_d_bits_size_0),\n .auto_dmInner_tl_in_d_bits_source (auto_dmInner_dmInner_tl_in_d_bits_source_0),\n .auto_dmInner_tl_in_d_bits_data (auto_dmInner_dmInner_tl_in_d_bits_data_0),\n .io_debug_clock (io_debug_clock_0),\t// @[Debug.scala:1959:9]\n .io_debug_reset (io_debug_reset_0),\t// @[Debug.scala:1959:9]\n .io_tl_clock (io_tl_clock_0),\t// @[Debug.scala:1959:9]\n .io_tl_reset (io_tl_reset_0),\t// @[Debug.scala:1959:9]\n .io_dmactive (_dmOuter_io_ctrl_dmactive),\t// @[Debug.scala:1949:53]\n .io_innerCtrl_mem_0_resumereq (_dmOuter_io_innerCtrl_mem_0_resumereq),\t// @[Debug.scala:1949:53]\n .io_innerCtrl_mem_0_hartsel (_dmOuter_io_innerCtrl_mem_0_hartsel),\t// @[Debug.scala:1949:53]\n .io_innerCtrl_mem_0_ackhavereset (_dmOuter_io_innerCtrl_mem_0_ackhavereset),\t// @[Debug.scala:1949:53]\n .io_innerCtrl_mem_0_hrmask_0 (_dmOuter_io_innerCtrl_mem_0_hrmask_0),\t// @[Debug.scala:1949:53]\n .io_innerCtrl_ridx (_dmInner_io_innerCtrl_ridx),\n .io_innerCtrl_widx (_dmOuter_io_innerCtrl_widx),\t// @[Debug.scala:1949:53]\n .io_innerCtrl_safe_ridx_valid (_dmInner_io_innerCtrl_safe_ridx_valid),\n .io_innerCtrl_safe_widx_valid (_dmOuter_io_innerCtrl_safe_widx_valid),\t// @[Debug.scala:1949:53]\n .io_innerCtrl_safe_source_reset_n (_dmOuter_io_innerCtrl_safe_source_reset_n),\t// @[Debug.scala:1949:53]\n .io_innerCtrl_safe_sink_reset_n (_dmInner_io_innerCtrl_safe_sink_reset_n),\n .io_hgDebugInt_0 (_dmInner_io_hgDebugInt_0),\n .io_hartIsInReset_0 (io_hartIsInReset_0_0),\t// @[Debug.scala:1959:9]\n .rf_reset (io_debug_reset_0)\t// @[Debug.scala:1959:9]\n );\t// @[Debug.scala:1950:53]\n assign auto_dmInner_dmInner_sb2tlOpt_out_a_valid = auto_dmInner_dmInner_sb2tlOpt_out_a_valid_0;\t// @[Debug.scala:1959:9]\n assign auto_dmInner_dmInner_sb2tlOpt_out_a_bits_opcode = auto_dmInner_dmInner_sb2tlOpt_out_a_bits_opcode_0;\t// @[Debug.scala:1959:9]\n assign auto_dmInner_dmInner_sb2tlOpt_out_a_bits_size = auto_dmInner_dmInner_sb2tlOpt_out_a_bits_size_0;\t// @[Debug.scala:1959:9]\n assign auto_dmInner_dmInner_sb2tlOpt_out_a_bits_address = auto_dmInner_dmInner_sb2tlOpt_out_a_bits_address_0;\t// @[Debug.scala:1959:9]\n assign auto_dmInner_dmInner_sb2tlOpt_out_a_bits_data = auto_dmInner_dmInner_sb2tlOpt_out_a_bits_data_0;\t// @[Debug.scala:1959:9]\n assign auto_dmInner_dmInner_sb2tlOpt_out_d_ready = auto_dmInner_dmInner_sb2tlOpt_out_d_ready_0;\t// @[Debug.scala:1959:9]\n assign auto_dmInner_dmInner_tl_in_a_ready = auto_dmInner_dmInner_tl_in_a_ready_0;\t// @[Debug.scala:1959:9]\n assign auto_dmInner_dmInner_tl_in_d_valid = auto_dmInner_dmInner_tl_in_d_valid_0;\t// @[Debug.scala:1959:9]\n assign auto_dmInner_dmInner_tl_in_d_bits_opcode = auto_dmInner_dmInner_tl_in_d_bits_opcode_0;\t// @[Debug.scala:1959:9]\n assign auto_dmInner_dmInner_tl_in_d_bits_size = auto_dmInner_dmInner_tl_in_d_bits_size_0;\t// @[Debug.scala:1959:9]\n assign auto_dmInner_dmInner_tl_in_d_bits_source = auto_dmInner_dmInner_tl_in_d_bits_source_0;\t// @[Debug.scala:1959:9]\n assign auto_dmInner_dmInner_tl_in_d_bits_data = auto_dmInner_dmInner_tl_in_d_bits_data_0;\t// @[Debug.scala:1959:9]\n assign auto_dmOuter_int_out_sync_0 = auto_dmOuter_int_out_sync_0_0;\t// @[Debug.scala:1959:9]\n assign io_ctrl_ndreset = io_ctrl_ndreset_0;\t// @[Debug.scala:1959:9]\n assign io_ctrl_dmactive = io_ctrl_dmactive_0;\t// @[Debug.scala:1959:9]\n assign io_dmi_dmi_req_ready = io_dmi_dmi_req_ready_0;\t// @[Debug.scala:1959:9]\n assign io_dmi_dmi_resp_valid = io_dmi_dmi_resp_valid_0;\t// @[Debug.scala:1959:9]\n assign io_dmi_dmi_resp_bits_data = io_dmi_dmi_resp_bits_data_0;\t// @[Debug.scala:1959:9]\n assign io_dmi_dmi_resp_bits_resp = io_dmi_dmi_resp_bits_resp_0;\t// @[Debug.scala:1959:9]\nendmodule"}}},{"rowIdx":567,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to the following Chisel files.\nFile Monitor.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.tilelink\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.experimental.SourceLine\n\nimport org.chipsalliance.cde.config._\nimport org.chipsalliance.diplomacy._\n\nimport freechips.rocketchip.diplomacy.EnableMonitors\nimport freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}\nimport freechips.rocketchip.util.PlusArg\n\ncase class TLMonitorArgs(edge: TLEdge)\n\nabstract class TLMonitorBase(args: TLMonitorArgs) extends Module\n{\n val io = IO(new Bundle {\n val in = Input(new TLBundle(args.edge.bundle))\n })\n\n def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit\n legalize(io.in, args.edge, reset)\n}\n\nobject TLMonitor {\n def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {\n if (enable) {\n EnableMonitors { implicit p => node := TLEphemeralNode()(ValName(\"monitor\")) }\n } else { node }\n }\n}\n\nclass TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)\n{\n require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))\n\n val cover_prop_class = PropertyClass.Default\n\n //Like assert but can flip to being an assumption for formal verification\n def monAssert(cond: Bool, message: String): Unit =\n if (monitorDir == MonitorDirection.Monitor) {\n assert(cond, message)\n } else {\n Property(monitorDir, cond, message, PropertyClass.Default)\n }\n\n def assume(cond: Bool, message: String): Unit =\n if (monitorDir == MonitorDirection.Monitor) {\n assert(cond, message)\n } else {\n Property(monitorDir.flip, cond, message, PropertyClass.Default)\n }\n\n def extra = {\n args.edge.sourceInfo match {\n case SourceLine(filename, line, col) => s\" (connected at $filename:$line:$col)\"\n case _ => \"\"\n }\n }\n\n def visible(address: UInt, source: UInt, edge: TLEdge) =\n edge.client.clients.map { c =>\n !c.sourceId.contains(source) ||\n c.visibility.map(_.contains(address)).reduce(_ || _)\n }.reduce(_ && _)\n\n def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {\n //switch this flag to turn on diplomacy in error messages\n def diplomacyInfo = if (true) \"\" else \"\\nThe diplomacy information for the edge is as follows:\\n\" + edge.formatEdge + \"\\n\"\n monAssert (TLMessages.isA(bundle.opcode), \"'A' channel has invalid opcode\" + extra)\n\n // Reuse these subexpressions to save some firrtl lines\n val source_ok = edge.client.contains(bundle.source)\n val is_aligned = edge.isAligned(bundle.address, bundle.size)\n val mask = edge.full_mask(bundle)\n\n monAssert (visible(edge.address(bundle), bundle.source, edge), \"'A' channel carries an address illegal for the specified bank visibility\")\n\n //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B\n //TODO: check for acquireT?\n when (bundle.opcode === TLMessages.AcquireBlock) {\n monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters\" + diplomacyInfo + extra)\n monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock from a client which does not support Probe\" + diplomacyInfo + extra)\n monAssert (source_ok, \"'A' channel AcquireBlock carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'A' channel AcquireBlock smaller than a beat\" + extra)\n monAssert (is_aligned, \"'A' channel AcquireBlock address not aligned to size\" + extra)\n monAssert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquireBlock carries invalid grow param\" + extra)\n monAssert (~bundle.mask === 0.U, \"'A' channel AcquireBlock contains invalid mask\" + extra)\n monAssert (!bundle.corrupt, \"'A' channel AcquireBlock is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.AcquirePerm) {\n monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters\" + diplomacyInfo + extra)\n monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm from a client which does not support Probe\" + diplomacyInfo + extra)\n monAssert (source_ok, \"'A' channel AcquirePerm carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'A' channel AcquirePerm smaller than a beat\" + extra)\n monAssert (is_aligned, \"'A' channel AcquirePerm address not aligned to size\" + extra)\n monAssert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquirePerm carries invalid grow param\" + extra)\n monAssert (bundle.param =/= TLPermissions.NtoB, \"'A' channel AcquirePerm requests NtoB\" + extra)\n monAssert (~bundle.mask === 0.U, \"'A' channel AcquirePerm contains invalid mask\" + extra)\n monAssert (!bundle.corrupt, \"'A' channel AcquirePerm is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.Get) {\n monAssert (edge.master.emitsGet(bundle.source, bundle.size), \"'A' channel carries Get type which master claims it can't emit\" + diplomacyInfo + extra)\n monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), \"'A' channel carries Get type which slave claims it can't support\" + diplomacyInfo + extra)\n monAssert (source_ok, \"'A' channel Get carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'A' channel Get carries invalid param\" + extra)\n monAssert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n monAssert (!bundle.corrupt, \"'A' channel Get is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.PutFullData) {\n monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type which is unexpected using diplomatic parameters\" + diplomacyInfo + extra)\n monAssert (source_ok, \"'A' channel PutFull carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'A' channel PutFull carries invalid param\" + extra)\n monAssert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.PutPartialData) {\n monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type which is unexpected using diplomatic parameters\" + extra)\n monAssert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'A' channel PutPartial carries invalid param\" + extra)\n monAssert ((bundle.mask & ~mask) === 0.U, \"'A' channel PutPartial contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.ArithmeticData) {\n monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type which is unexpected using diplomatic parameters\" + extra)\n monAssert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n monAssert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n monAssert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.LogicalData) {\n monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type which is unexpected using diplomatic parameters\" + extra)\n monAssert (source_ok, \"'A' channel Logical carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n monAssert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n monAssert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.Hint) {\n monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type which is unexpected using diplomatic parameters\" + extra)\n monAssert (source_ok, \"'A' channel Hint carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n monAssert (TLHints.isHints(bundle.param), \"'A' channel Hint carries invalid opcode param\" + extra)\n monAssert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n monAssert (!bundle.corrupt, \"'A' channel Hint is corrupt\" + extra)\n }\n }\n\n def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {\n monAssert (TLMessages.isB(bundle.opcode), \"'B' channel has invalid opcode\" + extra)\n\n monAssert (visible(edge.address(bundle), bundle.source, edge), \"'B' channel carries an address illegal for the specified bank visibility\")\n\n // Reuse these subexpressions to save some firrtl lines\n val address_ok = edge.manager.containsSafe(edge.address(bundle))\n val is_aligned = edge.isAligned(bundle.address, bundle.size)\n val mask = edge.full_mask(bundle)\n val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source\n\n when (bundle.opcode === TLMessages.Probe) {\n assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), \"'B' channel carries Probe type which is unexpected using diplomatic parameters\" + extra)\n assume (address_ok, \"'B' channel Probe carries unmanaged address\" + extra)\n assume (legal_source, \"'B' channel Probe carries source that is not first source\" + extra)\n assume (is_aligned, \"'B' channel Probe address not aligned to size\" + extra)\n assume (TLPermissions.isCap(bundle.param), \"'B' channel Probe carries invalid cap param\" + extra)\n assume (bundle.mask === mask, \"'B' channel Probe contains invalid mask\" + extra)\n assume (!bundle.corrupt, \"'B' channel Probe is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.Get) {\n monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), \"'B' channel carries Get type which is unexpected using diplomatic parameters\" + extra)\n monAssert (address_ok, \"'B' channel Get carries unmanaged address\" + extra)\n monAssert (legal_source, \"'B' channel Get carries source that is not first source\" + extra)\n monAssert (is_aligned, \"'B' channel Get address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'B' channel Get carries invalid param\" + extra)\n monAssert (bundle.mask === mask, \"'B' channel Get contains invalid mask\" + extra)\n monAssert (!bundle.corrupt, \"'B' channel Get is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.PutFullData) {\n monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), \"'B' channel carries PutFull type which is unexpected using diplomatic parameters\" + extra)\n monAssert (address_ok, \"'B' channel PutFull carries unmanaged address\" + extra)\n monAssert (legal_source, \"'B' channel PutFull carries source that is not first source\" + extra)\n monAssert (is_aligned, \"'B' channel PutFull address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'B' channel PutFull carries invalid param\" + extra)\n monAssert (bundle.mask === mask, \"'B' channel PutFull contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.PutPartialData) {\n monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), \"'B' channel carries PutPartial type which is unexpected using diplomatic parameters\" + extra)\n monAssert (address_ok, \"'B' channel PutPartial carries unmanaged address\" + extra)\n monAssert (legal_source, \"'B' channel PutPartial carries source that is not first source\" + extra)\n monAssert (is_aligned, \"'B' channel PutPartial address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'B' channel PutPartial carries invalid param\" + extra)\n monAssert ((bundle.mask & ~mask) === 0.U, \"'B' channel PutPartial contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.ArithmeticData) {\n monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), \"'B' channel carries Arithmetic type unsupported by master\" + extra)\n monAssert (address_ok, \"'B' channel Arithmetic carries unmanaged address\" + extra)\n monAssert (legal_source, \"'B' channel Arithmetic carries source that is not first source\" + extra)\n monAssert (is_aligned, \"'B' channel Arithmetic address not aligned to size\" + extra)\n monAssert (TLAtomics.isArithmetic(bundle.param), \"'B' channel Arithmetic carries invalid opcode param\" + extra)\n monAssert (bundle.mask === mask, \"'B' channel Arithmetic contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.LogicalData) {\n monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), \"'B' channel carries Logical type unsupported by client\" + extra)\n monAssert (address_ok, \"'B' channel Logical carries unmanaged address\" + extra)\n monAssert (legal_source, \"'B' channel Logical carries source that is not first source\" + extra)\n monAssert (is_aligned, \"'B' channel Logical address not aligned to size\" + extra)\n monAssert (TLAtomics.isLogical(bundle.param), \"'B' channel Logical carries invalid opcode param\" + extra)\n monAssert (bundle.mask === mask, \"'B' channel Logical contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.Hint) {\n monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), \"'B' channel carries Hint type unsupported by client\" + extra)\n monAssert (address_ok, \"'B' channel Hint carries unmanaged address\" + extra)\n monAssert (legal_source, \"'B' channel Hint carries source that is not first source\" + extra)\n monAssert (is_aligned, \"'B' channel Hint address not aligned to size\" + extra)\n monAssert (bundle.mask === mask, \"'B' channel Hint contains invalid mask\" + extra)\n monAssert (!bundle.corrupt, \"'B' channel Hint is corrupt\" + extra)\n }\n }\n\n def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {\n monAssert (TLMessages.isC(bundle.opcode), \"'C' channel has invalid opcode\" + extra)\n\n val source_ok = edge.client.contains(bundle.source)\n val is_aligned = edge.isAligned(bundle.address, bundle.size)\n val address_ok = edge.manager.containsSafe(edge.address(bundle))\n\n monAssert (visible(edge.address(bundle), bundle.source, edge), \"'C' channel carries an address illegal for the specified bank visibility\")\n\n when (bundle.opcode === TLMessages.ProbeAck) {\n monAssert (address_ok, \"'C' channel ProbeAck carries unmanaged address\" + extra)\n monAssert (source_ok, \"'C' channel ProbeAck carries invalid source ID\" + extra)\n monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'C' channel ProbeAck smaller than a beat\" + extra)\n monAssert (is_aligned, \"'C' channel ProbeAck address not aligned to size\" + extra)\n monAssert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAck carries invalid report param\" + extra)\n monAssert (!bundle.corrupt, \"'C' channel ProbeAck is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.ProbeAckData) {\n monAssert (address_ok, \"'C' channel ProbeAckData carries unmanaged address\" + extra)\n monAssert (source_ok, \"'C' channel ProbeAckData carries invalid source ID\" + extra)\n monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'C' channel ProbeAckData smaller than a beat\" + extra)\n monAssert (is_aligned, \"'C' channel ProbeAckData address not aligned to size\" + extra)\n monAssert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAckData carries invalid report param\" + extra)\n }\n\n when (bundle.opcode === TLMessages.Release) {\n monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries Release type unsupported by manager\" + extra)\n monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), \"'C' channel carries Release from a client which does not support Probe\" + extra)\n monAssert (source_ok, \"'C' channel Release carries invalid source ID\" + extra)\n monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'C' channel Release smaller than a beat\" + extra)\n monAssert (is_aligned, \"'C' channel Release address not aligned to size\" + extra)\n monAssert (TLPermissions.isReport(bundle.param), \"'C' channel Release carries invalid report param\" + extra)\n monAssert (!bundle.corrupt, \"'C' channel Release is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.ReleaseData) {\n monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries ReleaseData type unsupported by manager\" + extra)\n monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), \"'C' channel carries Release from a client which does not support Probe\" + extra)\n monAssert (source_ok, \"'C' channel ReleaseData carries invalid source ID\" + extra)\n monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'C' channel ReleaseData smaller than a beat\" + extra)\n monAssert (is_aligned, \"'C' channel ReleaseData address not aligned to size\" + extra)\n monAssert (TLPermissions.isReport(bundle.param), \"'C' channel ReleaseData carries invalid report param\" + extra)\n }\n\n when (bundle.opcode === TLMessages.AccessAck) {\n monAssert (address_ok, \"'C' channel AccessAck carries unmanaged address\" + extra)\n monAssert (source_ok, \"'C' channel AccessAck carries invalid source ID\" + extra)\n monAssert (is_aligned, \"'C' channel AccessAck address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'C' channel AccessAck carries invalid param\" + extra)\n monAssert (!bundle.corrupt, \"'C' channel AccessAck is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.AccessAckData) {\n monAssert (address_ok, \"'C' channel AccessAckData carries unmanaged address\" + extra)\n monAssert (source_ok, \"'C' channel AccessAckData carries invalid source ID\" + extra)\n monAssert (is_aligned, \"'C' channel AccessAckData address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'C' channel AccessAckData carries invalid param\" + extra)\n }\n\n when (bundle.opcode === TLMessages.HintAck) {\n monAssert (address_ok, \"'C' channel HintAck carries unmanaged address\" + extra)\n monAssert (source_ok, \"'C' channel HintAck carries invalid source ID\" + extra)\n monAssert (is_aligned, \"'C' channel HintAck address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'C' channel HintAck carries invalid param\" + extra)\n monAssert (!bundle.corrupt, \"'C' channel HintAck is corrupt\" + extra)\n }\n }\n\n def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {\n assume (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n\n val source_ok = edge.client.contains(bundle.source)\n val sink_ok = bundle.sink < edge.manager.endSinkId.U\n val deny_put_ok = edge.manager.mayDenyPut.B\n val deny_get_ok = edge.manager.mayDenyGet.B\n\n when (bundle.opcode === TLMessages.ReleaseAck) {\n assume (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'D' channel ReleaseAck smaller than a beat\" + extra)\n assume (bundle.param === 0.U, \"'D' channel ReleaseeAck carries invalid param\" + extra)\n assume (!bundle.corrupt, \"'D' channel ReleaseAck is corrupt\" + extra)\n assume (!bundle.denied, \"'D' channel ReleaseAck is denied\" + extra)\n }\n\n when (bundle.opcode === TLMessages.Grant) {\n assume (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n assume (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'D' channel Grant smaller than a beat\" + extra)\n assume (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n assume (bundle.param =/= TLPermissions.toN, \"'D' channel Grant carries toN param\" + extra)\n assume (!bundle.corrupt, \"'D' channel Grant is corrupt\" + extra)\n assume (deny_put_ok || !bundle.denied, \"'D' channel Grant is denied\" + extra)\n }\n\n when (bundle.opcode === TLMessages.GrantData) {\n assume (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n assume (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'D' channel GrantData smaller than a beat\" + extra)\n assume (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n assume (bundle.param =/= TLPermissions.toN, \"'D' channel GrantData carries toN param\" + extra)\n assume (!bundle.denied || bundle.corrupt, \"'D' channel GrantData is denied but not corrupt\" + extra)\n assume (deny_get_ok || !bundle.denied, \"'D' channel GrantData is denied\" + extra)\n }\n\n when (bundle.opcode === TLMessages.AccessAck) {\n assume (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n // size is ignored\n assume (bundle.param === 0.U, \"'D' channel AccessAck carries invalid param\" + extra)\n assume (!bundle.corrupt, \"'D' channel AccessAck is corrupt\" + extra)\n assume (deny_put_ok || !bundle.denied, \"'D' channel AccessAck is denied\" + extra)\n }\n\n when (bundle.opcode === TLMessages.AccessAckData) {\n assume (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n // size is ignored\n assume (bundle.param === 0.U, \"'D' channel AccessAckData carries invalid param\" + extra)\n assume (!bundle.denied || bundle.corrupt, \"'D' channel AccessAckData is denied but not corrupt\" + extra)\n assume (deny_get_ok || !bundle.denied, \"'D' channel AccessAckData is denied\" + extra)\n }\n\n when (bundle.opcode === TLMessages.HintAck) {\n assume (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n // size is ignored\n assume (bundle.param === 0.U, \"'D' channel HintAck carries invalid param\" + extra)\n assume (!bundle.corrupt, \"'D' channel HintAck is corrupt\" + extra)\n assume (deny_put_ok || !bundle.denied, \"'D' channel HintAck is denied\" + extra)\n }\n }\n\n def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {\n val sink_ok = bundle.sink < edge.manager.endSinkId.U\n monAssert (sink_ok, \"'E' channels carries invalid sink ID\" + extra)\n }\n\n def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {\n when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }\n when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }\n if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {\n when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }\n when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }\n when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }\n } else {\n monAssert (!bundle.b.valid, \"'B' channel valid and not TL-C\" + extra)\n monAssert (!bundle.c.valid, \"'C' channel valid and not TL-C\" + extra)\n monAssert (!bundle.e.valid, \"'E' channel valid and not TL-C\" + extra)\n }\n }\n\n def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {\n val a_first = edge.first(a.bits, a.fire)\n val opcode = Reg(UInt())\n val param = Reg(UInt())\n val size = Reg(UInt())\n val source = Reg(UInt())\n val address = Reg(UInt())\n when (a.valid && !a_first) {\n monAssert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n monAssert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n monAssert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n monAssert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n monAssert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n }\n when (a.fire && a_first) {\n opcode := a.bits.opcode\n param := a.bits.param\n size := a.bits.size\n source := a.bits.source\n address := a.bits.address\n }\n }\n\n def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {\n val b_first = edge.first(b.bits, b.fire)\n val opcode = Reg(UInt())\n val param = Reg(UInt())\n val size = Reg(UInt())\n val source = Reg(UInt())\n val address = Reg(UInt())\n when (b.valid && !b_first) {\n monAssert (b.bits.opcode === opcode, \"'B' channel opcode changed within multibeat operation\" + extra)\n monAssert (b.bits.param === param, \"'B' channel param changed within multibeat operation\" + extra)\n monAssert (b.bits.size === size, \"'B' channel size changed within multibeat operation\" + extra)\n monAssert (b.bits.source === source, \"'B' channel source changed within multibeat operation\" + extra)\n monAssert (b.bits.address=== address,\"'B' channel addresss changed with multibeat operation\" + extra)\n }\n when (b.fire && b_first) {\n opcode := b.bits.opcode\n param := b.bits.param\n size := b.bits.size\n source := b.bits.source\n address := b.bits.address\n }\n }\n\n def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {\n // Symbolic variable\n val sym_source = Wire(UInt(edge.client.endSourceId.W))\n // TODO: Connect sym_source to a fixed value for simulation and to a\n // free wire in formal\n sym_source := 0.U\n\n // Type casting Int to UInt\n val maxSourceId = Wire(UInt(edge.client.endSourceId.W))\n maxSourceId := edge.client.endSourceId.U\n\n // Delayed verison of sym_source\n val sym_source_d = Reg(UInt(edge.client.endSourceId.W))\n sym_source_d := sym_source\n\n // These will be constraints for FV setup\n Property(\n MonitorDirection.Monitor,\n (sym_source === sym_source_d),\n \"sym_source should remain stable\",\n PropertyClass.Default)\n Property(\n MonitorDirection.Monitor,\n (sym_source <= maxSourceId),\n \"sym_source should take legal value\",\n PropertyClass.Default)\n\n val my_resp_pend = RegInit(false.B)\n val my_opcode = Reg(UInt())\n val my_size = Reg(UInt())\n\n val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)\n val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)\n\n val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)\n val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)\n\n val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)\n val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)\n when (my_set_resp_pend) {\n my_resp_pend := true.B\n } .elsewhen (my_clr_resp_pend) {\n my_resp_pend := false.B\n }\n\n when (my_a_first_beat) {\n my_opcode := bundle.a.bits.opcode\n my_size := bundle.a.bits.size\n }\n\n val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)\n val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)\n\n val my_resp_opcode_legal = Wire(Bool())\n when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||\n (my_resp_opcode === TLMessages.LogicalData)) {\n my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)\n } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {\n my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)\n } .otherwise {\n my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)\n }\n\n monAssert (IfThen(my_resp_pend, !my_a_first_beat),\n \"Request message should not be sent with a source ID, for which a response message\" +\n \"is already pending (not received until current cycle) for a prior request message\" +\n \"with the same source ID\" + extra)\n\n assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),\n \"Response message should be accepted with a source ID only if a request message with the\" +\n \"same source ID has been accepted or is being accepted in the current cycle\" + extra)\n assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),\n \"Response message should be sent with a source ID only if a request message with the\" +\n \"same source ID has been accepted or is being sent in the current cycle\" + extra)\n assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),\n \"If d_valid is 1, then d_size should be same as a_size of the corresponding request\" +\n \"message\" + extra)\n assume (IfThen(my_d_first_beat, my_resp_opcode_legal),\n \"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding\" +\n \"request message\" + extra)\n }\n\n def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {\n val c_first = edge.first(c.bits, c.fire)\n val opcode = Reg(UInt())\n val param = Reg(UInt())\n val size = Reg(UInt())\n val source = Reg(UInt())\n val address = Reg(UInt())\n when (c.valid && !c_first) {\n monAssert (c.bits.opcode === opcode, \"'C' channel opcode changed within multibeat operation\" + extra)\n monAssert (c.bits.param === param, \"'C' channel param changed within multibeat operation\" + extra)\n monAssert (c.bits.size === size, \"'C' channel size changed within multibeat operation\" + extra)\n monAssert (c.bits.source === source, \"'C' channel source changed within multibeat operation\" + extra)\n monAssert (c.bits.address=== address,\"'C' channel address changed with multibeat operation\" + extra)\n }\n when (c.fire && c_first) {\n opcode := c.bits.opcode\n param := c.bits.param\n size := c.bits.size\n source := c.bits.source\n address := c.bits.address\n }\n }\n\n def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {\n val d_first = edge.first(d.bits, d.fire)\n val opcode = Reg(UInt())\n val param = Reg(UInt())\n val size = Reg(UInt())\n val source = Reg(UInt())\n val sink = Reg(UInt())\n val denied = Reg(Bool())\n when (d.valid && !d_first) {\n assume (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n assume (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n assume (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n assume (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n assume (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n assume (d.bits.denied === denied, \"'D' channel denied changed with multibeat operation\" + extra)\n }\n when (d.fire && d_first) {\n opcode := d.bits.opcode\n param := d.bits.param\n size := d.bits.size\n source := d.bits.source\n sink := d.bits.sink\n denied := d.bits.denied\n }\n }\n\n def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {\n legalizeMultibeatA(bundle.a, edge)\n legalizeMultibeatD(bundle.d, edge)\n if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {\n legalizeMultibeatB(bundle.b, edge)\n legalizeMultibeatC(bundle.c, edge)\n }\n }\n\n //This is left in for almond which doesn't adhere to the tilelink protocol\n @deprecated(\"Use legalizeADSource instead if possible\",\"\")\n def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {\n val inflight = RegInit(0.U(edge.client.endSourceId.W))\n\n val a_first = edge.first(bundle.a.bits, bundle.a.fire)\n val d_first = edge.first(bundle.d.bits, bundle.d.fire)\n\n val a_set = WireInit(0.U(edge.client.endSourceId.W))\n when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {\n a_set := UIntToOH(bundle.a.bits.source)\n assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n }\n\n val d_clr = WireInit(0.U(edge.client.endSourceId.W))\n val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck\n when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {\n d_clr := UIntToOH(bundle.d.bits.source)\n assume((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n }\n\n if (edge.manager.minLatency > 0) {\n assume(a_set =/= d_clr || !a_set.orR, s\"'A' and 'D' concurrent, despite minlatency > 0\" + extra)\n }\n\n inflight := (inflight | a_set) & ~d_clr\n\n val watchdog = RegInit(0.U(32.W))\n val limit = PlusArg(\"tilelink_timeout\",\n docstring=\"Kill emulation after INT waiting TileLink cycles. Off if 0.\")\n assert (!inflight.orR || limit === 0.U || watchdog < limit, \"TileLink timeout expired\" + extra)\n\n watchdog := watchdog + 1.U\n when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }\n }\n\n def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {\n val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)\n val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything\n val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)\n val log_a_size_bus_size = log2Ceil(a_size_bus_size)\n def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits\n\n val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error\n inflight.suggestName(\"inflight\")\n val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))\n inflight_opcodes.suggestName(\"inflight_opcodes\")\n val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))\n inflight_sizes.suggestName(\"inflight_sizes\")\n\n val a_first = edge.first(bundle.a.bits, bundle.a.fire)\n a_first.suggestName(\"a_first\")\n val d_first = edge.first(bundle.d.bits, bundle.d.fire)\n d_first.suggestName(\"d_first\")\n\n val a_set = WireInit(0.U(edge.client.endSourceId.W))\n val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))\n a_set.suggestName(\"a_set\")\n a_set_wo_ready.suggestName(\"a_set_wo_ready\")\n val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))\n a_opcodes_set.suggestName(\"a_opcodes_set\")\n val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))\n a_sizes_set.suggestName(\"a_sizes_set\")\n\n val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))\n a_opcode_lookup.suggestName(\"a_opcode_lookup\")\n a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U\n\n val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))\n a_size_lookup.suggestName(\"a_size_lookup\")\n a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U\n\n val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))\n val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))\n\n val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))\n a_opcodes_set_interm.suggestName(\"a_opcodes_set_interm\")\n val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))\n a_sizes_set_interm.suggestName(\"a_sizes_set_interm\")\n\n when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {\n a_set_wo_ready := UIntToOH(bundle.a.bits.source)\n }\n\n when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {\n a_set := UIntToOH(bundle.a.bits.source)\n a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U\n a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U\n a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)\n a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)\n monAssert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n }\n\n val d_clr = WireInit(0.U(edge.client.endSourceId.W))\n val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))\n d_clr.suggestName(\"d_clr\")\n d_clr_wo_ready.suggestName(\"d_clr_wo_ready\")\n val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))\n d_opcodes_clr.suggestName(\"d_opcodes_clr\")\n val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))\n d_sizes_clr.suggestName(\"d_sizes_clr\")\n\n val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck\n when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {\n d_clr_wo_ready := UIntToOH(bundle.d.bits.source)\n }\n\n when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {\n d_clr := UIntToOH(bundle.d.bits.source)\n d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)\n d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)\n }\n when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {\n val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)\n assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, \"'D' channel acknowledged for nothing inflight\" + extra)\n\n when (same_cycle_resp) {\n assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||\n (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), \"'D' channel contains improper opcode response\" + extra)\n assume((bundle.a.bits.size === bundle.d.bits.size), \"'D' channel contains improper response size\" + extra)\n } .otherwise {\n assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||\n (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), \"'D' channel contains improper opcode response\" + extra)\n assume((bundle.d.bits.size === a_size_lookup), \"'D' channel contains improper response size\" + extra)\n }\n }\n when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {\n assume((!bundle.d.ready) || bundle.a.ready, \"ready check\")\n }\n\n if (edge.manager.minLatency > 0) {\n assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s\"'A' and 'D' concurrent, despite minlatency > 0\" + extra)\n }\n\n inflight := (inflight | a_set) & ~d_clr\n inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr\n inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr\n\n val watchdog = RegInit(0.U(32.W))\n val limit = PlusArg(\"tilelink_timeout\",\n docstring=\"Kill emulation after INT waiting TileLink cycles. Off if 0.\")\n monAssert (!inflight.orR || limit === 0.U || watchdog < limit, \"TileLink timeout expired\" + extra)\n\n watchdog := watchdog + 1.U\n when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }\n }\n\n def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {\n val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)\n val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything\n\n val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)\n val log_c_size_bus_size = log2Ceil(c_size_bus_size)\n def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits\n\n val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))\n val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))\n val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))\n inflight.suggestName(\"inflight\")\n inflight_opcodes.suggestName(\"inflight_opcodes\")\n inflight_sizes.suggestName(\"inflight_sizes\")\n\n val c_first = edge.first(bundle.c.bits, bundle.c.fire)\n val d_first = edge.first(bundle.d.bits, bundle.d.fire)\n c_first.suggestName(\"c_first\")\n d_first.suggestName(\"d_first\")\n\n val c_set = WireInit(0.U(edge.client.endSourceId.W))\n val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))\n val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))\n val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))\n c_set.suggestName(\"c_set\")\n c_set_wo_ready.suggestName(\"c_set_wo_ready\")\n c_opcodes_set.suggestName(\"c_opcodes_set\")\n c_sizes_set.suggestName(\"c_sizes_set\")\n\n val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))\n val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))\n c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U\n c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U\n c_opcode_lookup.suggestName(\"c_opcode_lookup\")\n c_size_lookup.suggestName(\"c_size_lookup\")\n\n val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))\n val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))\n c_opcodes_set_interm.suggestName(\"c_opcodes_set_interm\")\n c_sizes_set_interm.suggestName(\"c_sizes_set_interm\")\n\n when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {\n c_set_wo_ready := UIntToOH(bundle.c.bits.source)\n }\n\n when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {\n c_set := UIntToOH(bundle.c.bits.source)\n c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U\n c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U\n c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)\n c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)\n monAssert(!inflight(bundle.c.bits.source), \"'C' channel re-used a source ID\" + extra)\n }\n\n val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData\n\n val d_clr = WireInit(0.U(edge.client.endSourceId.W))\n val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))\n val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))\n val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))\n d_clr.suggestName(\"d_clr\")\n d_clr_wo_ready.suggestName(\"d_clr_wo_ready\")\n d_opcodes_clr.suggestName(\"d_opcodes_clr\")\n d_sizes_clr.suggestName(\"d_sizes_clr\")\n\n val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck\n when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {\n d_clr_wo_ready := UIntToOH(bundle.d.bits.source)\n }\n\n when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {\n d_clr := UIntToOH(bundle.d.bits.source)\n d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)\n d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)\n }\n\n when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {\n val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)\n assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, \"'D' channel acknowledged for nothing inflight\" + extra)\n when (same_cycle_resp) {\n assume((bundle.d.bits.size === bundle.c.bits.size), \"'D' channel contains improper response size\" + extra)\n } .otherwise {\n assume((bundle.d.bits.size === c_size_lookup), \"'D' channel contains improper response size\" + extra)\n }\n }\n\n when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {\n assume((!bundle.d.ready) || bundle.c.ready, \"ready check\")\n }\n\n if (edge.manager.minLatency > 0) {\n when (c_set_wo_ready.orR) {\n assume(c_set_wo_ready =/= d_clr_wo_ready, s\"'C' and 'D' concurrent, despite minlatency > 0\" + extra)\n }\n }\n\n inflight := (inflight | c_set) & ~d_clr\n inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr\n inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr\n\n val watchdog = RegInit(0.U(32.W))\n val limit = PlusArg(\"tilelink_timeout\",\n docstring=\"Kill emulation after INT waiting TileLink cycles. Off if 0.\")\n monAssert (!inflight.orR || limit === 0.U || watchdog < limit, \"TileLink timeout expired\" + extra)\n\n watchdog := watchdog + 1.U\n when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }\n }\n\n def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {\n val inflight = RegInit(0.U(edge.manager.endSinkId.W))\n\n val d_first = edge.first(bundle.d.bits, bundle.d.fire)\n val e_first = true.B\n\n val d_set = WireInit(0.U(edge.manager.endSinkId.W))\n when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {\n d_set := UIntToOH(bundle.d.bits.sink)\n assume(!inflight(bundle.d.bits.sink), \"'D' channel re-used a sink ID\" + extra)\n }\n\n val e_clr = WireInit(0.U(edge.manager.endSinkId.W))\n when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {\n e_clr := UIntToOH(bundle.e.bits.sink)\n monAssert((d_set | inflight)(bundle.e.bits.sink), \"'E' channel acknowledged for nothing inflight\" + extra)\n }\n\n // edge.client.minLatency applies to BC, not DE\n\n inflight := (inflight | d_set) & ~e_clr\n }\n\n def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {\n val sourceBits = log2Ceil(edge.client.endSourceId)\n val tooBig = 14 // >16kB worth of flight information gets to be too much\n if (sourceBits > tooBig) {\n println(s\"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked\")\n } else {\n if (args.edge.params(TestplanTestType).simulation) {\n if (args.edge.params(TLMonitorStrictMode)) {\n legalizeADSource(bundle, edge)\n legalizeCDSource(bundle, edge)\n } else {\n legalizeADSourceOld(bundle, edge)\n }\n }\n if (args.edge.params(TestplanTestType).formal) {\n legalizeADSourceFormal(bundle, edge)\n }\n }\n if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {\n // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...\n val sinkBits = log2Ceil(edge.manager.endSinkId)\n if (sinkBits > tooBig) {\n println(s\"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked\")\n } else {\n legalizeDESink(bundle, edge)\n }\n }\n }\n\n def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {\n legalizeFormat (bundle, edge)\n legalizeMultibeat (bundle, edge)\n legalizeUnique (bundle, edge)\n }\n}\nFile Misc.scala:\n// See LICENSE.Berkeley for license details.\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.util.random.LFSR\nimport org.chipsalliance.cde.config.Parameters\nimport scala.math._\n\nclass ParameterizedBundle(implicit p: Parameters) extends Bundle\n\ntrait Clocked extends Bundle {\n val clock = Clock()\n val reset = Bool() \n}\n\nobject DecoupledHelper {\n def apply(rvs: Bool*) = new DecoupledHelper(rvs)\n}\n\nclass DecoupledHelper(val rvs: Seq[Bool]) {\n def fire(exclude: Bool, includes: Bool*) = {\n require(rvs.contains(exclude), \"Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!\")\n (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)\n }\n def fire() = {\n rvs.reduce(_ && _)\n }\n}\n\nobject MuxT {\n def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =\n (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))\n\n def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =\n (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))\n\n def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =\n (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))\n}\n\n/** Creates a cascade of n MuxTs to search for a key value. */\nobject MuxTLookup {\n def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {\n var res = default\n for ((k, v) <- mapping.reverse)\n res = MuxT(k === key, v, res)\n res\n }\n\n def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {\n var res = default\n for ((k, v) <- mapping.reverse)\n res = MuxT(k === key, v, res)\n res\n }\n}\n\nobject ValidMux {\n def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {\n apply(v1 +: v2.toSeq)\n }\n def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {\n val out = Wire(Valid(valids.head.bits.cloneType))\n out.valid := valids.map(_.valid).reduce(_ || _)\n out.bits := MuxCase(valids.head.bits,\n valids.map(v => (v.valid -> v.bits)))\n out\n }\n}\n\nobject Str\n{\n def apply(s: String): UInt = {\n var i = BigInt(0)\n require(s.forall(validChar _))\n for (c <- s)\n i = (i << 8) | c\n i.U((s.length*8).W)\n }\n def apply(x: Char): UInt = {\n require(validChar(x))\n x.U(8.W)\n }\n def apply(x: UInt): UInt = apply(x, 10)\n def apply(x: UInt, radix: Int): UInt = {\n val rad = radix.U\n val w = x.getWidth\n require(w > 0)\n\n var q = x\n var s = digit(q % rad)\n for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {\n q = q / rad\n s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)\n }\n s\n }\n def apply(x: SInt): UInt = apply(x, 10)\n def apply(x: SInt, radix: Int): UInt = {\n val neg = x < 0.S\n val abs = x.abs.asUInt\n if (radix != 10) {\n Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))\n } else {\n val rad = radix.U\n val w = abs.getWidth\n require(w > 0)\n\n var q = abs\n var s = digit(q % rad)\n var needSign = neg\n for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {\n q = q / rad\n val placeSpace = q === 0.U\n val space = Mux(needSign, Str('-'), Str(' '))\n needSign = needSign && !placeSpace\n s = Cat(Mux(placeSpace, space, digit(q % rad)), s)\n }\n Cat(Mux(needSign, Str('-'), Str(' ')), s)\n }\n }\n\n private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)\n private def validChar(x: Char) = x == (x & 0xFF)\n}\n\nobject Split\n{\n def apply(x: UInt, n0: Int) = {\n val w = x.getWidth\n (x.extract(w-1,n0), x.extract(n0-1,0))\n }\n def apply(x: UInt, n1: Int, n0: Int) = {\n val w = x.getWidth\n (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))\n }\n def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {\n val w = x.getWidth\n (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))\n }\n}\n\nobject Random\n{\n def apply(mod: Int, random: UInt): UInt = {\n if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)\n else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))\n }\n def apply(mod: Int): UInt = apply(mod, randomizer)\n def oneHot(mod: Int, random: UInt): UInt = {\n if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))\n else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt\n }\n def oneHot(mod: Int): UInt = oneHot(mod, randomizer)\n\n private def randomizer = LFSR(16)\n private def partition(value: UInt, slices: Int) =\n Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)\n}\n\nobject Majority {\n def apply(in: Set[Bool]): Bool = {\n val n = (in.size >> 1) + 1\n val clauses = in.subsets(n).map(_.reduce(_ && _))\n clauses.reduce(_ || _)\n }\n\n def apply(in: Seq[Bool]): Bool = apply(in.toSet)\n\n def apply(in: UInt): Bool = apply(in.asBools.toSet)\n}\n\nobject PopCountAtLeast {\n private def two(x: UInt): (Bool, Bool) = x.getWidth match {\n case 1 => (x.asBool, false.B)\n case n =>\n val half = x.getWidth / 2\n val (leftOne, leftTwo) = two(x(half - 1, 0))\n val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))\n (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))\n }\n def apply(x: UInt, n: Int): Bool = n match {\n case 0 => true.B\n case 1 => x.orR\n case 2 => two(x)._2\n case 3 => PopCount(x) >= n.U\n }\n}\n\n// This gets used everywhere, so make the smallest circuit possible ...\n// Given an address and size, create a mask of beatBytes size\n// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111\n// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01\nobject MaskGen {\n def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {\n require (groupBy >= 1 && beatBytes >= groupBy)\n require (isPow2(beatBytes) && isPow2(groupBy))\n val lgBytes = log2Ceil(beatBytes)\n val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U\n\n def helper(i: Int): Seq[(Bool, Bool)] = {\n if (i == 0) {\n Seq((lgSize >= lgBytes.asUInt, true.B))\n } else {\n val sub = helper(i-1)\n val size = sizeOH(lgBytes - i)\n val bit = addr_lo(lgBytes - i)\n val nbit = !bit\n Seq.tabulate (1 << i) { j =>\n val (sub_acc, sub_eq) = sub(j/2)\n val eq = sub_eq && (if (j % 2 == 1) bit else nbit)\n val acc = sub_acc || (size && eq)\n (acc, eq)\n }\n }\n }\n\n if (groupBy == beatBytes) 1.U else\n Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)\n }\n}\nFile PlusArg.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3._\nimport chisel3.experimental._\nimport chisel3.util.HasBlackBoxResource\n\n@deprecated(\"This will be removed in Rocket Chip 2020.08\", \"Rocket Chip 2020.05\")\ncase class PlusArgInfo(default: BigInt, docstring: String)\n\n/** Case class for PlusArg information\n *\n * @tparam A scala type of the PlusArg value\n * @param default optional default value\n * @param docstring text to include in the help\n * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)\n */\nprivate case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)\n\n/** Typeclass for converting a type to a doctype string\n * @tparam A some type\n */\ntrait Doctypeable[A] {\n\n /** Return the doctype string for some option */\n def toDoctype(a: Option[A]): String\n\n}\n\n/** Object containing implementations of the Doctypeable typeclass */\nobject Doctypes {\n\n /** Converts an Int => \"INT\" */\n implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = \"INT\" }\n\n /** Converts a BigInt => \"INT\" */\n implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = \"INT\" }\n\n /** Converts a String => \"STRING\" */\n implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = \"STRING\" }\n\n}\n\nclass plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(\n \"FORMAT\" -> StringParam(format),\n \"DEFAULT\" -> IntParam(default),\n \"WIDTH\" -> IntParam(width)\n )) with HasBlackBoxResource {\n val io = IO(new Bundle {\n val out = Output(UInt(width.W))\n })\n\n addResource(\"/vsrc/plusarg_reader.v\")\n}\n\n/* This wrapper class has no outputs, making it clear it is a simulation-only construct */\nclass PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {\n val io = IO(new Bundle {\n val count = Input(UInt(width.W))\n })\n val max = Module(new plusarg_reader(format, default, docstring, width)).io.out\n when (max > 0.U) {\n assert (io.count < max, s\"Timeout exceeded: $docstring\")\n }\n}\n\nimport Doctypes._\n\nobject PlusArg\n{\n /** PlusArg(\"foo\") will return 42.U if the simulation is run with +foo=42\n * Do not use this as an initial register value. The value is set in an\n * initial block and thus accessing it from another initial is racey.\n * Add a docstring to document the arg, which can be dumped in an elaboration\n * pass.\n */\n def apply(name: String, default: BigInt = 0, docstring: String = \"\", width: Int = 32): UInt = {\n PlusArgArtefacts.append(name, Some(default), docstring)\n Module(new plusarg_reader(name + \"=%d\", default, docstring, width)).io.out\n }\n\n /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert\n * to kill the simulation when count exceeds the specified integer argument.\n * Default 0 will never assert.\n */\n def timeout(name: String, default: BigInt = 0, docstring: String = \"\", width: Int = 32)(count: UInt): Unit = {\n PlusArgArtefacts.append(name, Some(default), docstring)\n Module(new PlusArgTimeout(name + \"=%d\", default, docstring, width)).io.count := count\n }\n}\n\nobject PlusArgArtefacts {\n private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty\n\n /* Add a new PlusArg */\n @deprecated(\n \"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08\",\n \"Rocket Chip 2020.05\"\n )\n def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)\n\n /** Add a new PlusArg\n *\n * @tparam A scala type of the PlusArg value\n * @param name name for the PlusArg\n * @param default optional default value\n * @param docstring text to include in the help\n */\n def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =\n artefacts = artefacts ++\n Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))\n\n /* From plus args, generate help text */\n private def serializeHelp_cHeader(tab: String = \"\"): String = artefacts\n .map{ case(arg, info) =>\n s\"\"\"|$tab+$arg=${info.doctype}\\\\n\\\\\n |$tab${\" \"*20}${info.docstring}\\\\n\\\\\n |\"\"\".stripMargin ++ info.default.map{ case default =>\n s\"$tab${\" \"*22}(default=${default})\\\\n\\\\\\n\"}.getOrElse(\"\")\n }.toSeq.mkString(\"\\\\n\\\\\\n\") ++ \"\\\"\"\n\n /* From plus args, generate a char array of their names */\n private def serializeArray_cHeader(tab: String = \"\"): String = {\n val prettyTab = tab + \" \" * 44 // Length of 'static const ...'\n s\"${tab}static const char * verilog_plusargs [] = {\\\\\\n\" ++\n artefacts\n .map{ case(arg, _) => s\"\"\"$prettyTab\"$arg\",\\\\\\n\"\"\" }\n .mkString(\"\")++\n s\"${prettyTab}0};\"\n }\n\n /* Generate C code to be included in emulator.cc that helps with\n * argument parsing based on available Verilog PlusArgs */\n def serialize_cHeader(): String =\n s\"\"\"|#define PLUSARG_USAGE_OPTIONS \\\"EMULATOR VERILOG PLUSARGS\\\\n\\\\\n |${serializeHelp_cHeader(\" \"*7)}\n |${serializeArray_cHeader()}\n |\"\"\".stripMargin\n}\nFile package.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip\n\nimport chisel3._\nimport chisel3.util._\nimport scala.math.min\nimport scala.collection.{immutable, mutable}\n\npackage object util {\n implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {\n def unzip = (x.map(_._1), x.map(_._2))\n }\n\n implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {\n def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR\n \n def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)\n }\n\n implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {\n\n /** Like Vec.apply(idx), but tolerates indices of mismatched width */\n def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))\n }\n\n implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {\n def apply(idx: UInt): T = {\n if (x.size <= 1) {\n x.head\n } else if (!isPow2(x.size)) {\n // For non-power-of-2 seqs, reflect elements to simplify decoder\n (x ++ x.takeRight(x.size & -x.size)).toSeq(idx)\n } else {\n // Ignore MSBs of idx\n val truncIdx =\n if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx\n else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)\n x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }\n }\n }\n\n def extract(idx: UInt): T = VecInit(x).extract(idx)\n\n def asUInt: UInt = Cat(x.map(_.asUInt).reverse)\n\n def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)\n\n def rotate(n: UInt): Seq[T] = {\n if (x.size <= 1) {\n x\n } else {\n require(isPow2(x.size))\n val amt = n.padTo(log2Ceil(x.size))\n (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })\n }\n }\n\n def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)\n\n def rotateRight(n: UInt): Seq[T] = {\n if (x.size <= 1) {\n x\n } else {\n require(isPow2(x.size))\n val amt = n.padTo(log2Ceil(x.size))\n (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })\n }\n }\n }\n\n // allow bitwise ops on Seq[Bool] just like UInt\n implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {\n def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }\n def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }\n def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }\n def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x\n def >> (n: Int): Seq[Bool] = x drop n\n def unary_~ : Seq[Bool] = x.map(!_)\n def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)\n def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)\n def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)\n\n private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)\n }\n\n implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {\n def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))\n\n def getElements: Seq[Element] = x match {\n case e: Element => Seq(e)\n case a: Aggregate => a.getElements.flatMap(_.getElements)\n }\n }\n\n /** Any Data subtype that has a Bool member named valid. */\n type DataCanBeValid = Data { val valid: Bool }\n\n implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {\n def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)\n }\n\n implicit class StringToAugmentedString(private val x: String) extends AnyVal {\n /** converts from camel case to to underscores, also removing all spaces */\n def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + \"\") getOrElse \"\") {\n case (acc, c) if c.isUpper => acc + \"_\" + c.toLower\n case (acc, c) if c == ' ' => acc\n case (acc, c) => acc + c\n }\n\n /** converts spaces or underscores to hyphens, also lowering case */\n def kebab: String = x.toLowerCase map {\n case ' ' => '-'\n case '_' => '-'\n case c => c\n }\n\n def named(name: Option[String]): String = {\n x + name.map(\"_named_\" + _ ).getOrElse(\"_with_no_name\")\n }\n\n def named(name: String): String = named(Some(name))\n }\n\n implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)\n implicit def wcToUInt(c: WideCounter): UInt = c.value\n\n implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {\n def sextTo(n: Int): UInt = {\n require(x.getWidth <= n)\n if (x.getWidth == n) x\n else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)\n }\n\n def padTo(n: Int): UInt = {\n require(x.getWidth <= n)\n if (x.getWidth == n) x\n else Cat(0.U((n - x.getWidth).W), x)\n }\n\n // shifts left by n if n >= 0, or right by -n if n < 0\n def << (n: SInt): UInt = {\n val w = n.getWidth - 1\n require(w <= 30)\n\n val shifted = x << n(w-1, 0)\n Mux(n(w), shifted >> (1 << w), shifted)\n }\n\n // shifts right by n if n >= 0, or left by -n if n < 0\n def >> (n: SInt): UInt = {\n val w = n.getWidth - 1\n require(w <= 30)\n\n val shifted = x << (1 << w) >> n(w-1, 0)\n Mux(n(w), shifted, shifted >> (1 << w))\n }\n\n // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts\n def extract(hi: Int, lo: Int): UInt = {\n require(hi >= lo-1)\n if (hi == lo-1) 0.U\n else x(hi, lo)\n }\n\n // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts\n def extractOption(hi: Int, lo: Int): Option[UInt] = {\n require(hi >= lo-1)\n if (hi == lo-1) None\n else Some(x(hi, lo))\n }\n\n // like x & ~y, but first truncate or zero-extend y to x's width\n def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))\n\n def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)\n\n def rotateRight(n: UInt): UInt = {\n if (x.getWidth <= 1) {\n x\n } else {\n val amt = n.padTo(log2Ceil(x.getWidth))\n (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))\n }\n }\n\n def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))\n\n def rotateLeft(n: UInt): UInt = {\n if (x.getWidth <= 1) {\n x\n } else {\n val amt = n.padTo(log2Ceil(x.getWidth))\n (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))\n }\n }\n\n // compute (this + y) % n, given (this < n) and (y < n)\n def addWrap(y: UInt, n: Int): UInt = {\n val z = x +& y\n if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)\n }\n\n // compute (this - y) % n, given (this < n) and (y < n)\n def subWrap(y: UInt, n: Int): UInt = {\n val z = x -& y\n if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)\n }\n\n def grouped(width: Int): Seq[UInt] =\n (0 until x.getWidth by width).map(base => x(base + width - 1, base))\n\n def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds\n\n def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)\n\n // Like >=, but prevents x-prop for ('x >= 0)\n def >== (y: UInt): Bool = x >= y || y === 0.U\n }\n\n implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {\n def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)\n def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)\n }\n\n implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {\n def toInt: Int = if (x) 1 else 0\n\n // this one's snagged from scalaz\n def option[T](z: => T): Option[T] = if (x) Some(z) else None\n }\n\n implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {\n // exact log2\n def log2: Int = {\n require(isPow2(x))\n log2Ceil(x)\n }\n }\n\n def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)\n def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))\n def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)\n def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)\n\n def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None\n\n // Fill 1s from low bits to high bits\n def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)\n def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {\n val stop = min(width, cap)\n def helper(s: Int, x: UInt): UInt =\n if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))\n helper(1, x)(width-1, 0)\n }\n\n // Fill 1s form high bits to low bits\n def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)\n def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {\n val stop = min(width, cap)\n def helper(s: Int, x: UInt): UInt =\n if (s >= stop) x else helper(s+s, x | (x >> s))\n helper(1, x)(width-1, 0)\n }\n\n def OptimizationBarrier[T <: Data](in: T): T = {\n val barrier = Module(new Module {\n val io = IO(new Bundle {\n val x = Input(chiselTypeOf(in))\n val y = Output(chiselTypeOf(in))\n })\n io.y := io.x\n override def desiredName = s\"OptimizationBarrier_${in.typeName}\"\n })\n barrier.io.x := in\n barrier.io.y\n }\n\n /** Similar to Seq.groupBy except this returns a Seq instead of a Map\n * Useful for deterministic code generation\n */\n def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {\n val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]\n for (x <- xs) {\n val key = f(x)\n val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])\n l += x\n }\n map.view.map({ case (k, vs) => k -> vs.toList }).toList\n }\n\n def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {\n case 1 => List.fill(n)(in.head)\n case x if x == n => in\n case _ => throw new Exception(s\"must provide exactly 1 or $n of some field, but got:\\n$in\")\n }\n\n // HeterogeneousBag moved to standalond diplomacy\n @deprecated(\"HeterogeneousBag has been absorbed into standalone diplomacy library\", \"rocketchip 2.0.0\")\n def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)\n @deprecated(\"HeterogeneousBag has been absorbed into standalone diplomacy library\", \"rocketchip 2.0.0\")\n val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag\n}\nFile Edges.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.tilelink\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.experimental.SourceInfo\nimport org.chipsalliance.cde.config.Parameters\nimport freechips.rocketchip.util._\n\nclass TLEdge(\n client: TLClientPortParameters,\n manager: TLManagerPortParameters,\n params: Parameters,\n sourceInfo: SourceInfo)\n extends TLEdgeParameters(client, manager, params, sourceInfo)\n{\n def isAligned(address: UInt, lgSize: UInt): Bool = {\n if (maxLgSize == 0) true.B else {\n val mask = UIntToOH1(lgSize, maxLgSize)\n (address & mask) === 0.U\n }\n }\n\n def mask(address: UInt, lgSize: UInt): UInt =\n MaskGen(address, lgSize, manager.beatBytes)\n\n def staticHasData(bundle: TLChannel): Option[Boolean] = {\n bundle match {\n case _:TLBundleA => {\n // Do there exist A messages with Data?\n val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial\n // Do there exist A messages without Data?\n val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint\n // Statically optimize the case where hasData is a constant\n if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None\n }\n case _:TLBundleB => {\n // Do there exist B messages with Data?\n val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial\n // Do there exist B messages without Data?\n val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint\n // Statically optimize the case where hasData is a constant\n if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None\n }\n case _:TLBundleC => {\n // Do there eixst C messages with Data?\n val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe\n // Do there exist C messages without Data?\n val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe\n if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None\n }\n case _:TLBundleD => {\n // Do there eixst D messages with Data?\n val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB\n // Do there exist D messages without Data?\n val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT\n if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None\n }\n case _:TLBundleE => Some(false)\n }\n }\n\n def isRequest(x: TLChannel): Bool = {\n x match {\n case a: TLBundleA => true.B\n case b: TLBundleB => true.B\n case c: TLBundleC => c.opcode(2) && c.opcode(1)\n // opcode === TLMessages.Release ||\n // opcode === TLMessages.ReleaseData\n case d: TLBundleD => d.opcode(2) && !d.opcode(1)\n // opcode === TLMessages.Grant ||\n // opcode === TLMessages.GrantData\n case e: TLBundleE => false.B\n }\n }\n\n def isResponse(x: TLChannel): Bool = {\n x match {\n case a: TLBundleA => false.B\n case b: TLBundleB => false.B\n case c: TLBundleC => !c.opcode(2) || !c.opcode(1)\n // opcode =/= TLMessages.Release &&\n // opcode =/= TLMessages.ReleaseData\n case d: TLBundleD => true.B // Grant isResponse + isRequest\n case e: TLBundleE => true.B\n }\n }\n\n def hasData(x: TLChannel): Bool = {\n val opdata = x match {\n case a: TLBundleA => !a.opcode(2)\n // opcode === TLMessages.PutFullData ||\n // opcode === TLMessages.PutPartialData ||\n // opcode === TLMessages.ArithmeticData ||\n // opcode === TLMessages.LogicalData\n case b: TLBundleB => !b.opcode(2)\n // opcode === TLMessages.PutFullData ||\n // opcode === TLMessages.PutPartialData ||\n // opcode === TLMessages.ArithmeticData ||\n // opcode === TLMessages.LogicalData\n case c: TLBundleC => c.opcode(0)\n // opcode === TLMessages.AccessAckData ||\n // opcode === TLMessages.ProbeAckData ||\n // opcode === TLMessages.ReleaseData\n case d: TLBundleD => d.opcode(0)\n // opcode === TLMessages.AccessAckData ||\n // opcode === TLMessages.GrantData\n case e: TLBundleE => false.B\n }\n staticHasData(x).map(_.B).getOrElse(opdata)\n }\n\n def opcode(x: TLDataChannel): UInt = {\n x match {\n case a: TLBundleA => a.opcode\n case b: TLBundleB => b.opcode\n case c: TLBundleC => c.opcode\n case d: TLBundleD => d.opcode\n }\n }\n\n def param(x: TLDataChannel): UInt = {\n x match {\n case a: TLBundleA => a.param\n case b: TLBundleB => b.param\n case c: TLBundleC => c.param\n case d: TLBundleD => d.param\n }\n }\n\n def size(x: TLDataChannel): UInt = {\n x match {\n case a: TLBundleA => a.size\n case b: TLBundleB => b.size\n case c: TLBundleC => c.size\n case d: TLBundleD => d.size\n }\n }\n\n def data(x: TLDataChannel): UInt = {\n x match {\n case a: TLBundleA => a.data\n case b: TLBundleB => b.data\n case c: TLBundleC => c.data\n case d: TLBundleD => d.data\n }\n }\n\n def corrupt(x: TLDataChannel): Bool = {\n x match {\n case a: TLBundleA => a.corrupt\n case b: TLBundleB => b.corrupt\n case c: TLBundleC => c.corrupt\n case d: TLBundleD => d.corrupt\n }\n }\n\n def mask(x: TLAddrChannel): UInt = {\n x match {\n case a: TLBundleA => a.mask\n case b: TLBundleB => b.mask\n case c: TLBundleC => mask(c.address, c.size)\n }\n }\n\n def full_mask(x: TLAddrChannel): UInt = {\n x match {\n case a: TLBundleA => mask(a.address, a.size)\n case b: TLBundleB => mask(b.address, b.size)\n case c: TLBundleC => mask(c.address, c.size)\n }\n }\n\n def address(x: TLAddrChannel): UInt = {\n x match {\n case a: TLBundleA => a.address\n case b: TLBundleB => b.address\n case c: TLBundleC => c.address\n }\n }\n\n def source(x: TLDataChannel): UInt = {\n x match {\n case a: TLBundleA => a.source\n case b: TLBundleB => b.source\n case c: TLBundleC => c.source\n case d: TLBundleD => d.source\n }\n }\n\n def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)\n def addr_lo(x: UInt): UInt =\n if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)\n\n def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))\n def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))\n\n def numBeats(x: TLChannel): UInt = {\n x match {\n case _: TLBundleE => 1.U\n case bundle: TLDataChannel => {\n val hasData = this.hasData(bundle)\n val size = this.size(bundle)\n val cutoff = log2Ceil(manager.beatBytes)\n val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U\n val decode = UIntToOH(size, maxLgSize+1) >> cutoff\n Mux(hasData, decode | small.asUInt, 1.U)\n }\n }\n }\n\n def numBeats1(x: TLChannel): UInt = {\n x match {\n case _: TLBundleE => 0.U\n case bundle: TLDataChannel => {\n if (maxLgSize == 0) {\n 0.U\n } else {\n val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)\n Mux(hasData(bundle), decode, 0.U)\n }\n }\n }\n }\n\n def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {\n val beats1 = numBeats1(bits)\n val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))\n val counter1 = counter - 1.U\n val first = counter === 0.U\n val last = counter === 1.U || beats1 === 0.U\n val done = last && fire\n val count = (beats1 & ~counter1)\n when (fire) {\n counter := Mux(first, beats1, counter1)\n }\n (first, last, done, count)\n }\n\n def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1\n def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)\n def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)\n\n def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2\n def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)\n def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)\n\n def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3\n def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)\n def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)\n\n def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {\n val r = firstlastHelper(bits, fire)\n (r._1, r._2, r._3)\n }\n def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)\n def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)\n\n def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {\n val r = firstlastHelper(bits, fire)\n (r._1, r._2, r._3, r._4)\n }\n def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)\n def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)\n\n def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {\n val r = firstlastHelper(bits, fire)\n (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))\n }\n def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)\n def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)\n\n // Does the request need T permissions to be executed?\n def needT(a: TLBundleA): Bool = {\n val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(\n TLPermissions.NtoB -> false.B,\n TLPermissions.NtoT -> true.B,\n TLPermissions.BtoT -> true.B))\n MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(\n TLMessages.PutFullData -> true.B,\n TLMessages.PutPartialData -> true.B,\n TLMessages.ArithmeticData -> true.B,\n TLMessages.LogicalData -> true.B,\n TLMessages.Get -> false.B,\n TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(\n TLHints.PREFETCH_READ -> false.B,\n TLHints.PREFETCH_WRITE -> true.B)),\n TLMessages.AcquireBlock -> acq_needT,\n TLMessages.AcquirePerm -> acq_needT))\n }\n\n // This is a very expensive circuit; use only if you really mean it!\n def inFlight(x: TLBundle): (UInt, UInt) = {\n val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))\n val bce = manager.anySupportAcquireB && client.anySupportProbe\n\n val (a_first, a_last, _) = firstlast(x.a)\n val (b_first, b_last, _) = firstlast(x.b)\n val (c_first, c_last, _) = firstlast(x.c)\n val (d_first, d_last, _) = firstlast(x.d)\n val (e_first, e_last, _) = firstlast(x.e)\n\n val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))\n val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))\n val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))\n val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))\n val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))\n\n val a_inc = x.a.fire && a_first && a_request\n val b_inc = x.b.fire && b_first && b_request\n val c_inc = x.c.fire && c_first && c_request\n val d_inc = x.d.fire && d_first && d_request\n val e_inc = x.e.fire && e_first && e_request\n val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))\n\n val a_dec = x.a.fire && a_last && a_response\n val b_dec = x.b.fire && b_last && b_response\n val c_dec = x.c.fire && c_last && c_response\n val d_dec = x.d.fire && d_last && d_response\n val e_dec = x.e.fire && e_last && e_response\n val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))\n\n val next_flight = flight + PopCount(inc) - PopCount(dec)\n flight := next_flight\n\n (flight, next_flight)\n }\n\n def prettySourceMapping(context: String): String = {\n s\"TL-Source mapping for $context:\\n${(new TLSourceIdMap(client)).pretty}\\n\"\n }\n}\n\nclass TLEdgeOut(\n client: TLClientPortParameters,\n manager: TLManagerPortParameters,\n params: Parameters,\n sourceInfo: SourceInfo)\n extends TLEdge(client, manager, params, sourceInfo)\n{\n // Transfers\n def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {\n require (manager.anySupportAcquireB, s\"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsAcquireBFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.AcquireBlock\n a.param := growPermissions\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := DontCare\n a.corrupt := false.B\n (legal, a)\n }\n\n def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {\n require (manager.anySupportAcquireB, s\"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsAcquireBFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.AcquirePerm\n a.param := growPermissions\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := DontCare\n a.corrupt := false.B\n (legal, a)\n }\n\n def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {\n require (manager.anySupportAcquireB, s\"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsAcquireBFast(toAddress, lgSize)\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.Release\n c.param := shrinkPermissions\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := DontCare\n c.corrupt := false.B\n (legal, c)\n }\n\n def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {\n require (manager.anySupportAcquireB, s\"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsAcquireBFast(toAddress, lgSize)\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.ReleaseData\n c.param := shrinkPermissions\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := data\n c.corrupt := corrupt\n (legal, c)\n }\n\n def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =\n Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)\n\n def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =\n ProbeAck(b.source, b.address, b.size, reportPermissions)\n\n def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.ProbeAck\n c.param := reportPermissions\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := DontCare\n c.corrupt := false.B\n c\n }\n\n def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =\n ProbeAck(b.source, b.address, b.size, reportPermissions, data)\n\n def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.ProbeAckData\n c.param := reportPermissions\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := data\n c.corrupt := corrupt\n c\n }\n\n def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =\n ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)\n\n def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)\n def GrantAck(toSink: UInt): TLBundleE = {\n val e = Wire(new TLBundleE(bundle))\n e.sink := toSink\n e\n }\n\n // Accesses\n def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {\n require (manager.anySupportGet, s\"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsGetFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.Get\n a.param := 0.U\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := DontCare\n a.corrupt := false.B\n (legal, a)\n }\n\n def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =\n Put(fromSource, toAddress, lgSize, data, false.B)\n\n def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {\n require (manager.anySupportPutFull, s\"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsPutFullFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.PutFullData\n a.param := 0.U\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := data\n a.corrupt := corrupt\n (legal, a)\n }\n\n def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =\n Put(fromSource, toAddress, lgSize, data, mask, false.B)\n\n def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {\n require (manager.anySupportPutPartial, s\"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsPutPartialFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.PutPartialData\n a.param := 0.U\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask\n a.data := data\n a.corrupt := corrupt\n (legal, a)\n }\n\n def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {\n require (manager.anySupportArithmetic, s\"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsArithmeticFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.ArithmeticData\n a.param := atomic\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := data\n a.corrupt := corrupt\n (legal, a)\n }\n\n def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {\n require (manager.anySupportLogical, s\"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsLogicalFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.LogicalData\n a.param := atomic\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := data\n a.corrupt := corrupt\n (legal, a)\n }\n\n def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {\n require (manager.anySupportHint, s\"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsHintFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.Hint\n a.param := param\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := DontCare\n a.corrupt := false.B\n (legal, a)\n }\n\n def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)\n def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.AccessAck\n c.param := 0.U\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := DontCare\n c.corrupt := false.B\n c\n }\n\n def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)\n def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)\n def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)\n def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.AccessAckData\n c.param := 0.U\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := data\n c.corrupt := corrupt\n c\n }\n\n def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)\n def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.HintAck\n c.param := 0.U\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := DontCare\n c.corrupt := false.B\n c\n }\n}\n\nclass TLEdgeIn(\n client: TLClientPortParameters,\n manager: TLManagerPortParameters,\n params: Parameters,\n sourceInfo: SourceInfo)\n extends TLEdge(client, manager, params, sourceInfo)\n{\n private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {\n val todo = x.filter(!_.isEmpty)\n val heads = todo.map(_.head)\n val tails = todo.map(_.tail)\n if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }\n }\n\n // Transfers\n def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {\n require (client.anySupportProbe, s\"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}\")\n val legal = client.supportsProbe(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.Probe\n b.param := capPermissions\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask(fromAddress, lgSize)\n b.data := DontCare\n b.corrupt := false.B\n (legal, b)\n }\n\n def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)\n def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {\n val d = Wire(new TLBundleD(bundle))\n d.opcode := TLMessages.Grant\n d.param := capPermissions\n d.size := lgSize\n d.source := toSource\n d.sink := fromSink\n d.denied := denied\n d.user := DontCare\n d.echo := DontCare\n d.data := DontCare\n d.corrupt := false.B\n d\n }\n\n def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)\n def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {\n val d = Wire(new TLBundleD(bundle))\n d.opcode := TLMessages.GrantData\n d.param := capPermissions\n d.size := lgSize\n d.source := toSource\n d.sink := fromSink\n d.denied := denied\n d.user := DontCare\n d.echo := DontCare\n d.data := data\n d.corrupt := corrupt\n d\n }\n\n def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)\n def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {\n val d = Wire(new TLBundleD(bundle))\n d.opcode := TLMessages.ReleaseAck\n d.param := 0.U\n d.size := lgSize\n d.source := toSource\n d.sink := 0.U\n d.denied := denied\n d.user := DontCare\n d.echo := DontCare\n d.data := DontCare\n d.corrupt := false.B\n d\n }\n\n // Accesses\n def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {\n require (client.anySupportGet, s\"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}\")\n val legal = client.supportsGet(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.Get\n b.param := 0.U\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask(fromAddress, lgSize)\n b.data := DontCare\n b.corrupt := false.B\n (legal, b)\n }\n\n def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =\n Put(fromAddress, toSource, lgSize, data, false.B)\n\n def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {\n require (client.anySupportPutFull, s\"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}\")\n val legal = client.supportsPutFull(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.PutFullData\n b.param := 0.U\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask(fromAddress, lgSize)\n b.data := data\n b.corrupt := corrupt\n (legal, b)\n }\n\n def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =\n Put(fromAddress, toSource, lgSize, data, mask, false.B)\n\n def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {\n require (client.anySupportPutPartial, s\"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}\")\n val legal = client.supportsPutPartial(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.PutPartialData\n b.param := 0.U\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask\n b.data := data\n b.corrupt := corrupt\n (legal, b)\n }\n\n def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {\n require (client.anySupportArithmetic, s\"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}\")\n val legal = client.supportsArithmetic(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.ArithmeticData\n b.param := atomic\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask(fromAddress, lgSize)\n b.data := data\n b.corrupt := corrupt\n (legal, b)\n }\n\n def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {\n require (client.anySupportLogical, s\"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}\")\n val legal = client.supportsLogical(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.LogicalData\n b.param := atomic\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask(fromAddress, lgSize)\n b.data := data\n b.corrupt := corrupt\n (legal, b)\n }\n\n def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {\n require (client.anySupportHint, s\"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}\")\n val legal = client.supportsHint(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.Hint\n b.param := param\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask(fromAddress, lgSize)\n b.data := DontCare\n b.corrupt := false.B\n (legal, b)\n }\n\n def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)\n def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)\n def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)\n def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {\n val d = Wire(new TLBundleD(bundle))\n d.opcode := TLMessages.AccessAck\n d.param := 0.U\n d.size := lgSize\n d.source := toSource\n d.sink := 0.U\n d.denied := denied\n d.user := DontCare\n d.echo := DontCare\n d.data := DontCare\n d.corrupt := false.B\n d\n }\n\n def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)\n def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)\n def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)\n def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {\n val d = Wire(new TLBundleD(bundle))\n d.opcode := TLMessages.AccessAckData\n d.param := 0.U\n d.size := lgSize\n d.source := toSource\n d.sink := 0.U\n d.denied := denied\n d.user := DontCare\n d.echo := DontCare\n d.data := data\n d.corrupt := corrupt\n d\n }\n\n def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)\n def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)\n def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)\n def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {\n val d = Wire(new TLBundleD(bundle))\n d.opcode := TLMessages.HintAck\n d.param := 0.U\n d.size := lgSize\n d.source := toSource\n d.sink := 0.U\n d.denied := denied\n d.user := DontCare\n d.echo := DontCare\n d.data := DontCare\n d.corrupt := false.B\n d\n }\n}\n"},"response":{"kind":"string","value":"module TLMonitor_52(\t// @[Monitor.scala:36:7]\n input clock,\t// @[Monitor.scala:36:7]\n input reset,\t// @[Monitor.scala:36:7]\n input io_in_a_ready,\t// @[Monitor.scala:20:14]\n input io_in_a_valid,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_a_bits_opcode,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_a_bits_param,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_a_bits_size,\t// @[Monitor.scala:20:14]\n input [3:0] io_in_a_bits_source,\t// @[Monitor.scala:20:14]\n input [31:0] io_in_a_bits_address,\t// @[Monitor.scala:20:14]\n input [7:0] io_in_a_bits_mask,\t// @[Monitor.scala:20:14]\n input io_in_a_bits_corrupt,\t// @[Monitor.scala:20:14]\n input io_in_d_ready,\t// @[Monitor.scala:20:14]\n input io_in_d_valid,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_d_bits_opcode,\t// @[Monitor.scala:20:14]\n input [1:0] io_in_d_bits_param,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_d_bits_size,\t// @[Monitor.scala:20:14]\n input [3:0] io_in_d_bits_source,\t// @[Monitor.scala:20:14]\n input io_in_d_bits_sink,\t// @[Monitor.scala:20:14]\n input io_in_d_bits_denied,\t// @[Monitor.scala:20:14]\n input io_in_d_bits_corrupt\t// @[Monitor.scala:20:14]\n);\n\n wire [31:0] _plusarg_reader_1_out;\t// @[PlusArg.scala:80:11]\n wire [31:0] _plusarg_reader_out;\t// @[PlusArg.scala:80:11]\n wire [12:0] _GEN = {10'h0, io_in_a_bits_size};\t// @[package.scala:243:71]\n wire _a_first_T_1 = io_in_a_ready & io_in_a_valid;\t// @[Decoupled.scala:51:35]\n reg [2:0] a_first_counter;\t// @[Edges.scala:229:27]\n reg [2:0] opcode;\t// @[Monitor.scala:387:22]\n reg [2:0] param;\t// @[Monitor.scala:388:22]\n reg [2:0] size;\t// @[Monitor.scala:389:22]\n reg [3:0] source;\t// @[Monitor.scala:390:22]\n reg [31:0] address;\t// @[Monitor.scala:391:22]\n reg [2:0] d_first_counter;\t// @[Edges.scala:229:27]\n reg [2:0] opcode_1;\t// @[Monitor.scala:538:22]\n reg [1:0] param_1;\t// @[Monitor.scala:539:22]\n reg [2:0] size_1;\t// @[Monitor.scala:540:22]\n reg [3:0] source_1;\t// @[Monitor.scala:541:22]\n reg sink;\t// @[Monitor.scala:542:22]\n reg denied;\t// @[Monitor.scala:543:22]\n reg [9:0] inflight;\t// @[Monitor.scala:614:27]\n reg [39:0] inflight_opcodes;\t// @[Monitor.scala:616:35]\n reg [39:0] inflight_sizes;\t// @[Monitor.scala:618:33]\n reg [2:0] a_first_counter_1;\t// @[Edges.scala:229:27]\n wire a_first_1 = a_first_counter_1 == 3'h0;\t// @[Edges.scala:229:27, :231:25]\n reg [2:0] d_first_counter_1;\t// @[Edges.scala:229:27]\n wire d_first_1 = d_first_counter_1 == 3'h0;\t// @[Edges.scala:229:27, :231:25]\n wire [15:0] _GEN_0 = {12'h0, io_in_a_bits_source};\t// @[OneHot.scala:58:35]\n wire _GEN_1 = _a_first_T_1 & a_first_1;\t// @[Decoupled.scala:51:35]\n wire d_release_ack = io_in_d_bits_opcode == 3'h6;\t// @[Monitor.scala:673:46]\n wire _GEN_2 = io_in_d_bits_opcode != 3'h6;\t// @[Monitor.scala:673:46, :674:74]\n wire [15:0] _GEN_3 = {12'h0, io_in_d_bits_source};\t// @[OneHot.scala:58:35]\n reg [31:0] watchdog;\t// @[Monitor.scala:709:27]\n reg [9:0] inflight_1;\t// @[Monitor.scala:726:35]\n reg [39:0] inflight_sizes_1;\t// @[Monitor.scala:728:35]\n reg [2:0] d_first_counter_2;\t// @[Edges.scala:229:27]\n wire d_first_2 = d_first_counter_2 == 3'h0;\t// @[Edges.scala:229:27, :231:25]\n reg [31:0] watchdog_1;\t// @[Monitor.scala:818:27]"}}},{"rowIdx":568,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to the following Chisel files.\nFile ShiftReg.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3._\n\n// Similar to the Chisel ShiftRegister but allows the user to suggest a\n// name to the registers that get instantiated, and\n// to provide a reset value.\nobject ShiftRegInit {\n def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =\n\n (0 until n).foldRight(in) {\n case (i, next) => {\n val r = RegNext(next, init)\n name.foreach { na => r.suggestName(s\"${na}_${i}\") }\n r\n }\n }\n}\n\n/** These wrap behavioral\n * shift registers into specific modules to allow for\n * backend flows to replace or constrain\n * them properly when used for CDC synchronization,\n * rather than buffering.\n * \n * The different types vary in their reset behavior:\n * AsyncResetShiftReg -- Asynchronously reset register array\n * A W(width) x D(depth) sized array is constructed from D instantiations of a\n * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,\n * but only used for timing applications\n */\n\nabstract class AbstractPipelineReg(w: Int = 1) extends Module {\n val io = IO(new Bundle {\n val d = Input(UInt(w.W))\n val q = Output(UInt(w.W))\n }\n )\n}\n\nobject AbstractPipelineReg {\n def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {\n val chain = Module(gen)\n name.foreach{ chain.suggestName(_) }\n chain.io.d := in.asUInt\n chain.io.q.asTypeOf(in)\n }\n}\n\nclass AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = \"pipe\") extends AbstractPipelineReg(w) {\n require(depth > 0, \"Depth must be greater than 0.\")\n\n override def desiredName = s\"AsyncResetShiftReg_w${w}_d${depth}_i${init}\"\n\n val chain = List.tabulate(depth) { i =>\n Module (new AsyncResetRegVec(w, init)).suggestName(s\"${name}_${i}\")\n }\n\n chain.last.io.d := io.d\n chain.last.io.en := true.B\n\n (chain.init zip chain.tail).foreach { case (sink, source) =>\n sink.io.d := source.io.q\n sink.io.en := true.B\n }\n io.q := chain.head.io.q\n}\n\nobject AsyncResetShiftReg {\n def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =\n AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)\n\n def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =\n apply(in, depth, 0, name)\n\n def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =\n apply(in, depth, init.litValue.toInt, name)\n\n def apply [T <: Data](in: T, depth: Int, init: T): T =\n apply (in, depth, init.litValue.toInt, None)\n}\nFile SynchronizerReg.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3._\nimport chisel3.util.{RegEnable, Cat}\n\n/** These wrap behavioral\n * shift and next registers into specific modules to allow for\n * backend flows to replace or constrain\n * them properly when used for CDC synchronization,\n * rather than buffering.\n * \n * \n * These are built up of *ResetSynchronizerPrimitiveShiftReg,\n * intended to be replaced by the integrator's metastable flops chains or replaced\n * at this level if they have a multi-bit wide synchronizer primitive.\n * The different types vary in their reset behavior:\n * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin\n * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep\n * 1-bit-wide shift registers.\n * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg\n * \n * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.\n * \n * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross\n * Clock Domains.\n*/\n\nobject SynchronizerResetType extends Enumeration {\n val NonSync, Inferred, Sync, Async = Value\n}\n\n\n// Note: this should not be used directly.\n// Use the companion object to generate this with the correct reset type mixin.\nprivate class SynchronizerPrimitiveShiftReg(\n sync: Int,\n init: Boolean,\n resetType: SynchronizerResetType.Value)\n extends AbstractPipelineReg(1) {\n\n val initInt = if (init) 1 else 0\n val initPostfix = resetType match {\n case SynchronizerResetType.NonSync => \"\"\n case _ => s\"_i${initInt}\"\n }\n override def desiredName = s\"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}\"\n\n val chain = List.tabulate(sync) { i =>\n val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)\n reg.suggestName(s\"sync_$i\")\n }\n chain.last := io.d.asBool\n\n (chain.init zip chain.tail).foreach { case (sink, source) =>\n sink := source\n }\n io.q := chain.head.asUInt\n}\n\nprivate object SynchronizerPrimitiveShiftReg {\n def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {\n val gen: () => SynchronizerPrimitiveShiftReg = resetType match {\n case SynchronizerResetType.NonSync =>\n () => new SynchronizerPrimitiveShiftReg(sync, init, resetType)\n case SynchronizerResetType.Async =>\n () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset\n case SynchronizerResetType.Sync =>\n () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset\n case SynchronizerResetType.Inferred =>\n () => new SynchronizerPrimitiveShiftReg(sync, init, resetType)\n }\n AbstractPipelineReg(gen(), in)\n }\n}\n\n// Note: This module may end up with a non-AsyncReset type reset.\n// But the Primitives within will always have AsyncReset type.\nclass AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)\n extends AbstractPipelineReg(w) {\n require(sync > 1, s\"Sync must be greater than 1, not ${sync}.\")\n override def desiredName = s\"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}\"\n val output = Seq.tabulate(w) { i =>\n val initBit = ((init >> i) & 1) > 0\n withReset(reset.asAsyncReset){\n SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)\n }\n }\n io.q := Cat(output.reverse)\n}\n\nobject AsyncResetSynchronizerShiftReg {\n def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =\n AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)\n\n def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =\n apply (in, sync, 0, name)\n\n def apply [T <: Data](in: T, sync: Int): T =\n apply (in, sync, 0, None)\n\n def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =\n apply(in, sync, init.litValue.toInt, name)\n\n def apply [T <: Data](in: T, sync: Int, init: T): T =\n apply (in, sync, init.litValue.toInt, None)\n}\n\n// Note: This module may end up with a non-Bool type reset.\n// But the Primitives within will always have Bool reset type.\n@deprecated(\"SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.\", \"rocket-chip 1.2\")\nclass SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {\n require(sync > 1, s\"Sync must be greater than 1, not ${sync}.\")\n override def desiredName = s\"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}\"\n val output = Seq.tabulate(w) { i =>\n val initBit = ((init >> i) & 1) > 0\n withReset(reset.asBool){\n SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)\n }\n }\n io.q := Cat(output.reverse)\n}\n\nobject SyncResetSynchronizerShiftReg {\n def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =\n if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)\n\n def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =\n apply (in, sync, 0, name)\n\n def apply [T <: Data](in: T, sync: Int): T =\n apply (in, sync, 0, None)\n\n def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =\n apply(in, sync, init.litValue.toInt, name)\n\n def apply [T <: Data](in: T, sync: Int, init: T): T =\n apply (in, sync, init.litValue.toInt, None)\n}\n\nclass ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {\n require(sync > 1, s\"Sync must be greater than 1, not ${sync}.\")\n override def desiredName = s\"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}\"\n val output = Seq.tabulate(w) { i =>\n val initBit = ((init >> i) & 1) > 0\n SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)\n }\n io.q := Cat(output.reverse)\n}\n\nobject ResetSynchronizerShiftReg {\n def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =\n AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)\n\n def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =\n apply (in, sync, 0, name)\n\n def apply [T <: Data](in: T, sync: Int): T =\n apply (in, sync, 0, None)\n\n def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =\n apply(in, sync, init.litValue.toInt, name)\n\n def apply [T <: Data](in: T, sync: Int, init: T): T =\n apply (in, sync, init.litValue.toInt, None)\n}\n\nclass SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {\n require(sync > 1, s\"Sync must be greater than 1, not ${sync}.\")\n override def desiredName = s\"SynchronizerShiftReg_w${w}_d${sync}\"\n val output = Seq.tabulate(w) { i =>\n SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)\n }\n io.q := Cat(output.reverse)\n}\n\nobject SynchronizerShiftReg {\n def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =\n if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)\n\n def apply [T <: Data](in: T, sync: Int): T =\n apply (in, sync, None)\n\n def apply [T <: Data](in: T): T =\n apply (in, 3, None)\n\n\n}\n\nclass ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {\n\n override def desiredName = s\"ClockCrossingReg_w${w}\"\n\n val io = IO(new Bundle{\n val d = Input(UInt(w.W))\n val q = Output(UInt(w.W))\n val en = Input(Bool())\n })\n\n val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)\n io.q := cdc_reg\n}\n\nobject ClockCrossingReg {\n def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {\n val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))\n name.foreach{ cdc_reg.suggestName(_) }\n cdc_reg.io.d := in.asUInt\n cdc_reg.io.en := en\n cdc_reg.io.q.asTypeOf(in)\n }\n}\n"},"response":{"kind":"string","value":"module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_289(\t// @[SynchronizerReg.scala:68:19]\n input clock,\t// @[SynchronizerReg.scala:68:19]\n input reset,\t// @[SynchronizerReg.scala:68:19]\n input io_d,\t// @[ShiftReg.scala:36:14]\n output io_q\t// @[ShiftReg.scala:36:14]\n);\n\n wire io_d_0 = io_d;\t// @[SynchronizerReg.scala:68:19]\n wire _sync_2_T = io_d_0;\t// @[SynchronizerReg.scala:54:22, :68:19]\n wire io_q_0;\t// @[SynchronizerReg.scala:68:19]\n reg sync_0;\t// @[SynchronizerReg.scala:51:87]\n assign io_q_0 = sync_0;\t// @[SynchronizerReg.scala:51:87, :68:19]\n reg sync_1;\t// @[SynchronizerReg.scala:51:87]\n reg sync_2;\t// @[SynchronizerReg.scala:51:87]\n always @(posedge clock or posedge reset) begin\t// @[SynchronizerReg.scala:68:19]\n if (reset) begin\t// @[SynchronizerReg.scala:68:19]\n sync_0 <= 1'h0;\t// @[SynchronizerReg.scala:51:87]\n sync_1 <= 1'h0;\t// @[SynchronizerReg.scala:51:87]\n sync_2 <= 1'h0;\t// @[SynchronizerReg.scala:51:87]\n end\n else begin\t// @[SynchronizerReg.scala:68:19]\n sync_0 <= sync_1;\t// @[SynchronizerReg.scala:51:87]\n sync_1 <= sync_2;\t// @[SynchronizerReg.scala:51:87]\n sync_2 <= _sync_2_T;\t// @[SynchronizerReg.scala:51:87, :54:22]\n end\n always @(posedge, posedge)"}}},{"rowIdx":569,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to the following Chisel files.\nFile PlusArg.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3._\nimport chisel3.experimental._\nimport chisel3.util.HasBlackBoxResource\n\n@deprecated(\"This will be removed in Rocket Chip 2020.08\", \"Rocket Chip 2020.05\")\ncase class PlusArgInfo(default: BigInt, docstring: String)\n\n/** Case class for PlusArg information\n *\n * @tparam A scala type of the PlusArg value\n * @param default optional default value\n * @param docstring text to include in the help\n * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)\n */\nprivate case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)\n\n/** Typeclass for converting a type to a doctype string\n * @tparam A some type\n */\ntrait Doctypeable[A] {\n\n /** Return the doctype string for some option */\n def toDoctype(a: Option[A]): String\n\n}\n\n/** Object containing implementations of the Doctypeable typeclass */\nobject Doctypes {\n\n /** Converts an Int => \"INT\" */\n implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = \"INT\" }\n\n /** Converts a BigInt => \"INT\" */\n implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = \"INT\" }\n\n /** Converts a String => \"STRING\" */\n implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = \"STRING\" }\n\n}\n\nclass plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(\n \"FORMAT\" -> StringParam(format),\n \"DEFAULT\" -> IntParam(default),\n \"WIDTH\" -> IntParam(width)\n )) with HasBlackBoxResource {\n val io = IO(new Bundle {\n val out = Output(UInt(width.W))\n })\n\n addResource(\"/vsrc/plusarg_reader.v\")\n}\n\n/* This wrapper class has no outputs, making it clear it is a simulation-only construct */\nclass PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {\n val io = IO(new Bundle {\n val count = Input(UInt(width.W))\n })\n val max = Module(new plusarg_reader(format, default, docstring, width)).io.out\n when (max > 0.U) {\n assert (io.count < max, s\"Timeout exceeded: $docstring\")\n }\n}\n\nimport Doctypes._\n\nobject PlusArg\n{\n /** PlusArg(\"foo\") will return 42.U if the simulation is run with +foo=42\n * Do not use this as an initial register value. The value is set in an\n * initial block and thus accessing it from another initial is racey.\n * Add a docstring to document the arg, which can be dumped in an elaboration\n * pass.\n */\n def apply(name: String, default: BigInt = 0, docstring: String = \"\", width: Int = 32): UInt = {\n PlusArgArtefacts.append(name, Some(default), docstring)\n Module(new plusarg_reader(name + \"=%d\", default, docstring, width)).io.out\n }\n\n /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert\n * to kill the simulation when count exceeds the specified integer argument.\n * Default 0 will never assert.\n */\n def timeout(name: String, default: BigInt = 0, docstring: String = \"\", width: Int = 32)(count: UInt): Unit = {\n PlusArgArtefacts.append(name, Some(default), docstring)\n Module(new PlusArgTimeout(name + \"=%d\", default, docstring, width)).io.count := count\n }\n}\n\nobject PlusArgArtefacts {\n private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty\n\n /* Add a new PlusArg */\n @deprecated(\n \"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08\",\n \"Rocket Chip 2020.05\"\n )\n def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)\n\n /** Add a new PlusArg\n *\n * @tparam A scala type of the PlusArg value\n * @param name name for the PlusArg\n * @param default optional default value\n * @param docstring text to include in the help\n */\n def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =\n artefacts = artefacts ++\n Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))\n\n /* From plus args, generate help text */\n private def serializeHelp_cHeader(tab: String = \"\"): String = artefacts\n .map{ case(arg, info) =>\n s\"\"\"|$tab+$arg=${info.doctype}\\\\n\\\\\n |$tab${\" \"*20}${info.docstring}\\\\n\\\\\n |\"\"\".stripMargin ++ info.default.map{ case default =>\n s\"$tab${\" \"*22}(default=${default})\\\\n\\\\\\n\"}.getOrElse(\"\")\n }.toSeq.mkString(\"\\\\n\\\\\\n\") ++ \"\\\"\"\n\n /* From plus args, generate a char array of their names */\n private def serializeArray_cHeader(tab: String = \"\"): String = {\n val prettyTab = tab + \" \" * 44 // Length of 'static const ...'\n s\"${tab}static const char * verilog_plusargs [] = {\\\\\\n\" ++\n artefacts\n .map{ case(arg, _) => s\"\"\"$prettyTab\"$arg\",\\\\\\n\"\"\" }\n .mkString(\"\")++\n s\"${prettyTab}0};\"\n }\n\n /* Generate C code to be included in emulator.cc that helps with\n * argument parsing based on available Verilog PlusArgs */\n def serialize_cHeader(): String =\n s\"\"\"|#define PLUSARG_USAGE_OPTIONS \\\"EMULATOR VERILOG PLUSARGS\\\\n\\\\\n |${serializeHelp_cHeader(\" \"*7)}\n |${serializeArray_cHeader()}\n |\"\"\".stripMargin\n}\nFile Nodes.scala:\npackage constellation.channel\n\nimport chisel3._\nimport chisel3.experimental.SourceInfo\nimport org.chipsalliance.cde.config.{Parameters, Field}\nimport freechips.rocketchip.diplomacy._\n\ncase class EmptyParams()\n\ncase class ChannelEdgeParams(cp: ChannelParams, p: Parameters)\n\nobject ChannelImp extends SimpleNodeImp[EmptyParams, ChannelParams, ChannelEdgeParams, Channel] {\n def edge(pd: EmptyParams, pu: ChannelParams, p: Parameters, sourceInfo: SourceInfo) = {\n ChannelEdgeParams(pu, p)\n }\n def bundle(e: ChannelEdgeParams) = new Channel(e.cp)(e.p)\n def render(e: ChannelEdgeParams) = if (e.cp.possibleFlows.size == 0) {\n RenderedEdge(colour = \"ffffff\", label = \"X\")\n } else {\n RenderedEdge(colour = \"#0000ff\", label = e.cp.payloadBits.toString)\n }\n\n override def monitor(bundle: Channel, edge: ChannelEdgeParams): Unit = {\n val monitor = Module(new NoCMonitor(edge.cp)(edge.p))\n monitor.io.in := bundle\n }\n // TODO: Add nodepath stuff? override def mixO, override def mixI\n}\n\ncase class ChannelSourceNode(val destId: Int)(implicit valName: ValName) extends SourceNode(ChannelImp)(Seq(EmptyParams()))\ncase class ChannelDestNode(val destParams: ChannelParams)(implicit valName: ValName) extends SinkNode(ChannelImp)(Seq(destParams))\ncase class ChannelAdapterNode(\n slaveFn: ChannelParams => ChannelParams = { d => d })(\n implicit valName: ValName) extends AdapterNode(ChannelImp)((e: EmptyParams) => e, slaveFn)\ncase class ChannelIdentityNode()(implicit valName: ValName) extends IdentityNode(ChannelImp)()\ncase class ChannelEphemeralNode()(implicit valName: ValName) extends EphemeralNode(ChannelImp)()\n\ncase class IngressChannelEdgeParams(cp: IngressChannelParams, p: Parameters)\ncase class EgressChannelEdgeParams(cp: EgressChannelParams, p: Parameters)\n\nobject IngressChannelImp extends SimpleNodeImp[EmptyParams, IngressChannelParams, IngressChannelEdgeParams, IngressChannel] {\n def edge(pd: EmptyParams, pu: IngressChannelParams, p: Parameters, sourceInfo: SourceInfo) = {\n IngressChannelEdgeParams(pu, p)\n }\n def bundle(e: IngressChannelEdgeParams) = new IngressChannel(e.cp)(e.p)\n def render(e: IngressChannelEdgeParams) = if (e.cp.possibleFlows.size == 0) {\n RenderedEdge(colour = \"ffffff\", label = \"X\")\n } else {\n RenderedEdge(colour = \"#00ff00\", label = e.cp.payloadBits.toString)\n }\n}\n\nobject EgressChannelImp extends SimpleNodeImp[EmptyParams, EgressChannelParams, EgressChannelEdgeParams, EgressChannel] {\n def edge(pd: EmptyParams, pu: EgressChannelParams, p: Parameters, sourceInfo: SourceInfo) = {\n EgressChannelEdgeParams(pu, p)\n }\n def bundle(e: EgressChannelEdgeParams) = new EgressChannel(e.cp)(e.p)\n def render(e: EgressChannelEdgeParams) = if (e.cp.possibleFlows.size == 0) {\n RenderedEdge(colour = \"ffffff\", label = \"X\")\n } else {\n RenderedEdge(colour = \"#ff0000\", label = e.cp.payloadBits.toString)\n }\n}\n\ncase class IngressChannelSourceNode(val destId: Int)(implicit valName: ValName) extends SourceNode(IngressChannelImp)(Seq(EmptyParams()))\ncase class IngressChannelDestNode(val destParams: IngressChannelParams)(implicit valName: ValName) extends SinkNode(IngressChannelImp)(Seq(destParams))\ncase class EgressChannelSourceNode(val egressId: Int)(implicit valName: ValName) extends SourceNode(EgressChannelImp)(Seq(EmptyParams()))\ncase class EgressChannelDestNode(val destParams: EgressChannelParams)(implicit valName: ValName) extends SinkNode(EgressChannelImp)(Seq(destParams))\n\n\ncase class IngressChannelAdapterNode(\n slaveFn: IngressChannelParams => IngressChannelParams = { d => d })(\n implicit valName: ValName) extends AdapterNode(IngressChannelImp)(m => m, slaveFn)\n\ncase class EgressChannelAdapterNode(\n slaveFn: EgressChannelParams => EgressChannelParams = { d => d })(\n implicit valName: ValName) extends AdapterNode(EgressChannelImp)(m => m, slaveFn)\n\ncase class IngressChannelIdentityNode()(implicit valName: ValName) extends IdentityNode(IngressChannelImp)()\ncase class EgressChannelIdentityNode()(implicit valName: ValName) extends IdentityNode(EgressChannelImp)()\n\ncase class IngressChannelEphemeralNode()(implicit valName: ValName) extends EphemeralNode(IngressChannelImp)()\ncase class EgressChannelEphemeralNode()(implicit valName: ValName) extends EphemeralNode(EgressChannelImp)()\nFile Router.scala:\npackage constellation.router\n\nimport chisel3._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config.{Field, Parameters}\nimport freechips.rocketchip.diplomacy._\nimport freechips.rocketchip.util._\n\nimport constellation.channel._\nimport constellation.routing.{RoutingRelation}\nimport constellation.noc.{HasNoCParams}\n\ncase class UserRouterParams(\n // Payload width. Must match payload width on all channels attached to this routing node\n payloadBits: Int = 64,\n // Combines SA and ST stages (removes pipeline register)\n combineSAST: Boolean = false,\n // Combines RC and VA stages (removes pipeline register)\n combineRCVA: Boolean = false,\n // Adds combinational path from SA to VA\n coupleSAVA: Boolean = false,\n vcAllocator: VCAllocatorParams => Parameters => VCAllocator = (vP) => (p) => new RotatingSingleVCAllocator(vP)(p)\n)\n\ncase class RouterParams(\n nodeId: Int,\n nIngress: Int,\n nEgress: Int,\n user: UserRouterParams\n)\n\ntrait HasRouterOutputParams {\n def outParams: Seq[ChannelParams]\n def egressParams: Seq[EgressChannelParams]\n\n def allOutParams = outParams ++ egressParams\n\n def nOutputs = outParams.size\n def nEgress = egressParams.size\n def nAllOutputs = allOutParams.size\n}\n\ntrait HasRouterInputParams {\n def inParams: Seq[ChannelParams]\n def ingressParams: Seq[IngressChannelParams]\n\n def allInParams = inParams ++ ingressParams\n\n def nInputs = inParams.size\n def nIngress = ingressParams.size\n def nAllInputs = allInParams.size\n}\n\ntrait HasRouterParams\n{\n def routerParams: RouterParams\n def nodeId = routerParams.nodeId\n def payloadBits = routerParams.user.payloadBits\n}\n\nclass DebugBundle(val nIn: Int) extends Bundle {\n val va_stall = Vec(nIn, UInt())\n val sa_stall = Vec(nIn, UInt())\n}\n\nclass Router(\n val routerParams: RouterParams,\n preDiplomaticInParams: Seq[ChannelParams],\n preDiplomaticIngressParams: Seq[IngressChannelParams],\n outDests: Seq[Int],\n egressIds: Seq[Int]\n)(implicit p: Parameters) extends LazyModule with HasNoCParams with HasRouterParams {\n val allPreDiplomaticInParams = preDiplomaticInParams ++ preDiplomaticIngressParams\n\n val destNodes = preDiplomaticInParams.map(u => ChannelDestNode(u))\n val sourceNodes = outDests.map(u => ChannelSourceNode(u))\n val ingressNodes = preDiplomaticIngressParams.map(u => IngressChannelDestNode(u))\n val egressNodes = egressIds.map(u => EgressChannelSourceNode(u))\n\n val debugNode = BundleBridgeSource(() => new DebugBundle(allPreDiplomaticInParams.size))\n val ctrlNode = if (hasCtrl) Some(BundleBridgeSource(() => new RouterCtrlBundle)) else None\n\n def inParams = module.inParams\n def outParams = module.outParams\n def ingressParams = module.ingressParams\n def egressParams = module.egressParams\n\n lazy val module = new LazyModuleImp(this) with HasRouterInputParams with HasRouterOutputParams {\n\n val (io_in, edgesIn) = destNodes.map(_.in(0)).unzip\n val (io_out, edgesOut) = sourceNodes.map(_.out(0)).unzip\n val (io_ingress, edgesIngress) = ingressNodes.map(_.in(0)).unzip\n val (io_egress, edgesEgress) = egressNodes.map(_.out(0)).unzip\n val io_debug = debugNode.out(0)._1\n\n val inParams = edgesIn.map(_.cp)\n val outParams = edgesOut.map(_.cp)\n val ingressParams = edgesIngress.map(_.cp)\n val egressParams = edgesEgress.map(_.cp)\n\n allOutParams.foreach(u => require(u.srcId == nodeId && u.payloadBits == routerParams.user.payloadBits))\n allInParams.foreach(u => require(u.destId == nodeId && u.payloadBits == routerParams.user.payloadBits))\n\n require(nIngress == routerParams.nIngress)\n require(nEgress == routerParams.nEgress)\n require(nAllInputs >= 1)\n require(nAllOutputs >= 1)\n require(nodeId < (1 << nodeIdBits))\n\n val input_units = inParams.zipWithIndex.map { case (u,i) =>\n Module(new InputUnit(u, outParams, egressParams,\n routerParams.user.combineRCVA, routerParams.user.combineSAST))\n .suggestName(s\"input_unit_${i}_from_${u.srcId}\") }\n val ingress_units = ingressParams.zipWithIndex.map { case (u,i) =>\n Module(new IngressUnit(i, u, outParams, egressParams,\n routerParams.user.combineRCVA, routerParams.user.combineSAST))\n .suggestName(s\"ingress_unit_${i+nInputs}_from_${u.ingressId}\") }\n val all_input_units = input_units ++ ingress_units\n\n val output_units = outParams.zipWithIndex.map { case (u,i) =>\n Module(new OutputUnit(inParams, ingressParams, u))\n .suggestName(s\"output_unit_${i}_to_${u.destId}\")}\n val egress_units = egressParams.zipWithIndex.map { case (u,i) =>\n Module(new EgressUnit(routerParams.user.coupleSAVA && all_input_units.size == 1,\n routerParams.user.combineSAST,\n inParams, ingressParams, u))\n .suggestName(s\"egress_unit_${i+nOutputs}_to_${u.egressId}\")}\n val all_output_units = output_units ++ egress_units\n\n val switch = Module(new Switch(routerParams, inParams, outParams, ingressParams, egressParams))\n val switch_allocator = Module(new SwitchAllocator(routerParams, inParams, outParams, ingressParams, egressParams))\n val vc_allocator = Module(routerParams.user.vcAllocator(\n VCAllocatorParams(routerParams, inParams, outParams, ingressParams, egressParams)\n )(p))\n val route_computer = Module(new RouteComputer(routerParams, inParams, outParams, ingressParams, egressParams))\n\n\n val fires_count = WireInit(PopCount(vc_allocator.io.req.map(_.fire)))\n dontTouch(fires_count)\n\n\n (io_in zip input_units ).foreach { case (i,u) => u.io.in <> i }\n (io_ingress zip ingress_units).foreach { case (i,u) => u.io.in <> i.flit }\n (output_units zip io_out ).foreach { case (u,o) => o <> u.io.out }\n (egress_units zip io_egress).foreach { case (u,o) => o.flit <> u.io.out }\n (route_computer.io.req zip all_input_units).foreach {\n case (i,u) => i <> u.io.router_req }\n (all_input_units zip route_computer.io.resp).foreach {\n case (u,o) => u.io.router_resp <> o }\n\n (vc_allocator.io.req zip all_input_units).foreach {\n case (i,u) => i <> u.io.vcalloc_req }\n (all_input_units zip vc_allocator.io.resp).foreach {\n case (u,o) => u.io.vcalloc_resp <> o }\n\n\n (all_output_units zip vc_allocator.io.out_allocs).foreach {\n case (u,a) => u.io.allocs <> a }\n (vc_allocator.io.channel_status zip all_output_units).foreach {\n case (a,u) => a := u.io.channel_status }\n\n all_input_units.foreach(in => all_output_units.zipWithIndex.foreach { case (out,outIdx) =>\n in.io.out_credit_available(outIdx) := out.io.credit_available\n })\n (all_input_units zip switch_allocator.io.req).foreach {\n case (u,r) => r <> u.io.salloc_req }\n (all_output_units zip switch_allocator.io.credit_alloc).foreach {\n case (u,a) => u.io.credit_alloc := a }\n\n (switch.io.in zip all_input_units).foreach {\n case (i,u) => i <> u.io.out }\n (all_output_units zip switch.io.out).foreach {\n case (u,o) => u.io.in <> o }\n switch.io.sel := (if (routerParams.user.combineSAST) {\n switch_allocator.io.switch_sel\n } else {\n RegNext(switch_allocator.io.switch_sel)\n })\n\n if (hasCtrl) {\n val io_ctrl = ctrlNode.get.out(0)._1\n val ctrl = Module(new RouterControlUnit(routerParams, inParams, outParams, ingressParams, egressParams))\n io_ctrl <> ctrl.io.ctrl\n (all_input_units zip ctrl.io.in_block ).foreach { case (l,r) => l.io.block := r }\n (all_input_units zip ctrl.io.in_fire ).foreach { case (l,r) => r := l.io.out.map(_.valid) }\n } else {\n input_units.foreach(_.io.block := false.B)\n ingress_units.foreach(_.io.block := false.B)\n }\n\n (io_debug.va_stall zip all_input_units.map(_.io.debug.va_stall)).map { case (l,r) => l := r }\n (io_debug.sa_stall zip all_input_units.map(_.io.debug.sa_stall)).map { case (l,r) => l := r }\n\n val debug_tsc = RegInit(0.U(64.W))\n debug_tsc := debug_tsc + 1.U\n val debug_sample = RegInit(0.U(64.W))\n debug_sample := debug_sample + 1.U\n val sample_rate = PlusArg(\"noc_util_sample_rate\", width=20)\n when (debug_sample === sample_rate - 1.U) { debug_sample := 0.U }\n\n def sample(fire: Bool, s: String) = {\n val util_ctr = RegInit(0.U(64.W))\n val fired = RegInit(false.B)\n util_ctr := util_ctr + fire\n fired := fired || fire\n when (sample_rate =/= 0.U && debug_sample === sample_rate - 1.U && fired) {\n val fmtStr = s\"nocsample %d $s %d\\n\"\n printf(fmtStr, debug_tsc, util_ctr);\n fired := fire\n }\n }\n\n destNodes.map(_.in(0)).foreach { case (in, edge) => in.flit.map { f =>\n sample(f.fire, s\"${edge.cp.srcId} $nodeId\")\n } }\n ingressNodes.map(_.in(0)).foreach { case (in, edge) =>\n sample(in.flit.fire, s\"i${edge.cp.asInstanceOf[IngressChannelParams].ingressId} $nodeId\")\n }\n egressNodes.map(_.out(0)).foreach { case (out, edge) =>\n sample(out.flit.fire, s\"$nodeId e${edge.cp.asInstanceOf[EgressChannelParams].egressId}\")\n }\n\n }\n}\nFile LazyModuleImp.scala:\npackage org.chipsalliance.diplomacy.lazymodule\n\nimport chisel3.{withClockAndReset, Module, RawModule, Reset, _}\nimport chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}\nimport firrtl.passes.InlineAnnotation\nimport org.chipsalliance.cde.config.Parameters\nimport org.chipsalliance.diplomacy.nodes.Dangle\n\nimport scala.collection.immutable.SortedMap\n\n/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].\n *\n * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.\n */\nsealed trait LazyModuleImpLike extends RawModule {\n\n /** [[LazyModule]] that contains this instance. */\n val wrapper: LazyModule\n\n /** IOs that will be automatically \"punched\" for this instance. */\n val auto: AutoBundle\n\n /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */\n protected[diplomacy] val dangles: Seq[Dangle]\n\n // [[wrapper.module]] had better not be accessed while LazyModules are still being built!\n require(\n LazyModule.scope.isEmpty,\n s\"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}\"\n )\n\n /** Set module name. Defaults to the containing LazyModule's desiredName. */\n override def desiredName: String = wrapper.desiredName\n\n suggestName(wrapper.suggestedName)\n\n /** [[Parameters]] for chisel [[Module]]s. */\n implicit val p: Parameters = wrapper.p\n\n /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and\n * submodules.\n */\n protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {\n // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],\n // 2. return [[Dangle]]s from each module.\n val childDangles = wrapper.children.reverse.flatMap { c =>\n implicit val sourceInfo: SourceInfo = c.info\n c.cloneProto.map { cp =>\n // If the child is a clone, then recursively set cloneProto of its children as well\n def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {\n require(bases.size == clones.size)\n (bases.zip(clones)).map { case (l, r) =>\n require(l.getClass == r.getClass, s\"Cloned children class mismatch ${l.name} != ${r.name}\")\n l.cloneProto = Some(r)\n assignCloneProtos(l.children, r.children)\n }\n }\n assignCloneProtos(c.children, cp.children)\n // Clone the child module as a record, and get its [[AutoBundle]]\n val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)\n val clonedAuto = clone(\"auto\").asInstanceOf[AutoBundle]\n // Get the empty [[Dangle]]'s of the cloned child\n val rawDangles = c.cloneDangles()\n require(rawDangles.size == clonedAuto.elements.size)\n // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s\n val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }\n dangles\n }.getOrElse {\n // For non-clones, instantiate the child module\n val mod = try {\n Module(c.module)\n } catch {\n case e: ChiselException => {\n println(s\"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}\")\n throw e\n }\n }\n mod.dangles\n }\n }\n\n // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].\n // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.\n val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())\n // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]\n val allDangles = nodeDangles ++ childDangles\n // Group [[allDangles]] by their [[source]].\n val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)\n // For each [[source]] set of [[Dangle]]s of size 2, ensure that these\n // can be connected as a source-sink pair (have opposite flipped value).\n // Make the connection and mark them as [[done]].\n val done = Set() ++ pairing.values.filter(_.size == 2).map {\n case Seq(a, b) =>\n require(a.flipped != b.flipped)\n // @todo <> in chisel3 makes directionless connection.\n if (a.flipped) {\n a.data <> b.data\n } else {\n b.data <> a.data\n }\n a.source\n case _ => None\n }\n // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.\n val forward = allDangles.filter(d => !done(d.source))\n // Generate [[AutoBundle]] IO from [[forward]].\n val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))\n // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]\n val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>\n if (d.flipped) {\n d.data <> io\n } else {\n io <> d.data\n }\n d.copy(dataOpt = Some(io), name = wrapper.suggestedName + \"_\" + d.name)\n }\n // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].\n wrapper.inModuleBody.reverse.foreach {\n _()\n }\n\n if (wrapper.shouldBeInlined) {\n chisel3.experimental.annotate(new ChiselAnnotation {\n def toFirrtl = InlineAnnotation(toNamed)\n })\n }\n\n // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].\n (auto, dangles)\n }\n}\n\n/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].\n *\n * @param wrapper\n * the [[LazyModule]] from which the `.module` call is being made.\n */\nclass LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {\n\n /** Instantiate hardware of this `Module`. */\n val (auto, dangles) = instantiate()\n}\n\n/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].\n *\n * @param wrapper\n * the [[LazyModule]] from which the `.module` call is being made.\n */\nclass LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {\n // These wires are the default clock+reset for all LazyModule children.\n // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the\n // [[LazyRawModuleImp]] children.\n // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.\n /** drive clock explicitly. */\n val childClock: Clock = Wire(Clock())\n\n /** drive reset explicitly. */\n val childReset: Reset = Wire(Reset())\n // the default is that these are disabled\n childClock := false.B.asClock\n childReset := chisel3.DontCare\n\n def provideImplicitClockToLazyChildren: Boolean = false\n val (auto, dangles) =\n if (provideImplicitClockToLazyChildren) {\n withClockAndReset(childClock, childReset) { instantiate() }\n } else {\n instantiate()\n }\n}\n"},"response":{"kind":"string","value":"module Router_29(\t// @[Router.scala:89:25]\n input clock,\t// @[Router.scala:89:25]\n input reset,\t// @[Router.scala:89:25]\n output [4:0] auto_debug_out_va_stall_0,\t// @[LazyModuleImp.scala:107:25]\n output [4:0] auto_debug_out_va_stall_1,\t// @[LazyModuleImp.scala:107:25]\n output [4:0] auto_debug_out_sa_stall_0,\t// @[LazyModuleImp.scala:107:25]\n output [4:0] auto_debug_out_sa_stall_1,\t// @[LazyModuleImp.scala:107:25]\n output auto_source_nodes_out_1_flit_0_valid,\t// @[LazyModuleImp.scala:107:25]\n output auto_source_nodes_out_1_flit_0_bits_head,\t// @[LazyModuleImp.scala:107:25]\n output auto_source_nodes_out_1_flit_0_bits_tail,\t// @[LazyModuleImp.scala:107:25]\n output [72:0] auto_source_nodes_out_1_flit_0_bits_payload,\t// @[LazyModuleImp.scala:107:25]\n output [3:0] auto_source_nodes_out_1_flit_0_bits_flow_vnet_id,\t// @[LazyModuleImp.scala:107:25]\n output [5:0] auto_source_nodes_out_1_flit_0_bits_flow_ingress_node,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_source_nodes_out_1_flit_0_bits_flow_ingress_node_id,\t// @[LazyModuleImp.scala:107:25]\n output [5:0] auto_source_nodes_out_1_flit_0_bits_flow_egress_node,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_source_nodes_out_1_flit_0_bits_flow_egress_node_id,\t// @[LazyModuleImp.scala:107:25]\n output [4:0] auto_source_nodes_out_1_flit_0_bits_virt_channel_id,\t// @[LazyModuleImp.scala:107:25]\n input [21:0] auto_source_nodes_out_1_credit_return,\t// @[LazyModuleImp.scala:107:25]\n input [21:0] auto_source_nodes_out_1_vc_free,\t// @[LazyModuleImp.scala:107:25]\n output auto_source_nodes_out_0_flit_0_valid,\t// @[LazyModuleImp.scala:107:25]\n output auto_source_nodes_out_0_flit_0_bits_head,\t// @[LazyModuleImp.scala:107:25]\n output auto_source_nodes_out_0_flit_0_bits_tail,\t// @[LazyModuleImp.scala:107:25]\n output [72:0] auto_source_nodes_out_0_flit_0_bits_payload,\t// @[LazyModuleImp.scala:107:25]\n output [3:0] auto_source_nodes_out_0_flit_0_bits_flow_vnet_id,\t// @[LazyModuleImp.scala:107:25]\n output [5:0] auto_source_nodes_out_0_flit_0_bits_flow_ingress_node,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_source_nodes_out_0_flit_0_bits_flow_ingress_node_id,\t// @[LazyModuleImp.scala:107:25]\n output [5:0] auto_source_nodes_out_0_flit_0_bits_flow_egress_node,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_source_nodes_out_0_flit_0_bits_flow_egress_node_id,\t// @[LazyModuleImp.scala:107:25]\n output [4:0] auto_source_nodes_out_0_flit_0_bits_virt_channel_id,\t// @[LazyModuleImp.scala:107:25]\n input [21:0] auto_source_nodes_out_0_credit_return,\t// @[LazyModuleImp.scala:107:25]\n input [21:0] auto_source_nodes_out_0_vc_free,\t// @[LazyModuleImp.scala:107:25]\n input auto_dest_nodes_in_1_flit_0_valid,\t// @[LazyModuleImp.scala:107:25]\n input auto_dest_nodes_in_1_flit_0_bits_head,\t// @[LazyModuleImp.scala:107:25]\n input auto_dest_nodes_in_1_flit_0_bits_tail,\t// @[LazyModuleImp.scala:107:25]\n input [72:0] auto_dest_nodes_in_1_flit_0_bits_payload,\t// @[LazyModuleImp.scala:107:25]\n input [3:0] auto_dest_nodes_in_1_flit_0_bits_flow_vnet_id,\t// @[LazyModuleImp.scala:107:25]\n input [5:0] auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id,\t// @[LazyModuleImp.scala:107:25]\n input [5:0] auto_dest_nodes_in_1_flit_0_bits_flow_egress_node,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_dest_nodes_in_1_flit_0_bits_flow_egress_node_id,\t// @[LazyModuleImp.scala:107:25]\n input [4:0] auto_dest_nodes_in_1_flit_0_bits_virt_channel_id,\t// @[LazyModuleImp.scala:107:25]\n output [21:0] auto_dest_nodes_in_1_credit_return,\t// @[LazyModuleImp.scala:107:25]\n output [21:0] auto_dest_nodes_in_1_vc_free,\t// @[LazyModuleImp.scala:107:25]\n input auto_dest_nodes_in_0_flit_0_valid,\t// @[LazyModuleImp.scala:107:25]\n input auto_dest_nodes_in_0_flit_0_bits_head,\t// @[LazyModuleImp.scala:107:25]\n input auto_dest_nodes_in_0_flit_0_bits_tail,\t// @[LazyModuleImp.scala:107:25]\n input [72:0] auto_dest_nodes_in_0_flit_0_bits_payload,\t// @[LazyModuleImp.scala:107:25]\n input [3:0] auto_dest_nodes_in_0_flit_0_bits_flow_vnet_id,\t// @[LazyModuleImp.scala:107:25]\n input [5:0] auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id,\t// @[LazyModuleImp.scala:107:25]\n input [5:0] auto_dest_nodes_in_0_flit_0_bits_flow_egress_node,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_dest_nodes_in_0_flit_0_bits_flow_egress_node_id,\t// @[LazyModuleImp.scala:107:25]\n input [4:0] auto_dest_nodes_in_0_flit_0_bits_virt_channel_id,\t// @[LazyModuleImp.scala:107:25]\n output [21:0] auto_dest_nodes_in_0_credit_return,\t// @[LazyModuleImp.scala:107:25]\n output [21:0] auto_dest_nodes_in_0_vc_free\t// @[LazyModuleImp.scala:107:25]\n);\n\n wire [19:0] _plusarg_reader_out;\t// @[PlusArg.scala:80:11]\n wire _route_computer_io_resp_1_vc_sel_0_12;\t// @[Router.scala:136:32]\n wire _route_computer_io_resp_1_vc_sel_0_13;\t// @[Router.scala:136:32]\n wire _route_computer_io_resp_1_vc_sel_0_16;\t// @[Router.scala:136:32]\n wire _route_computer_io_resp_1_vc_sel_0_17;\t// @[Router.scala:136:32]\n wire _route_computer_io_resp_1_vc_sel_0_20;\t// @[Router.scala:136:32]\n wire _route_computer_io_resp_1_vc_sel_0_21;\t// @[Router.scala:136:32]\n wire _route_computer_io_resp_0_vc_sel_1_10;\t// @[Router.scala:136:32]\n wire _route_computer_io_resp_0_vc_sel_1_11;\t// @[Router.scala:136:32]\n wire _route_computer_io_resp_0_vc_sel_1_14;\t// @[Router.scala:136:32]\n wire _route_computer_io_resp_0_vc_sel_1_15;\t// @[Router.scala:136:32]\n wire _route_computer_io_resp_0_vc_sel_1_18;\t// @[Router.scala:136:32]\n wire _route_computer_io_resp_0_vc_sel_1_19;\t// @[Router.scala:136:32]\n wire _route_computer_io_resp_0_vc_sel_1_20;\t// @[Router.scala:136:32]\n wire _route_computer_io_resp_0_vc_sel_1_21;\t// @[Router.scala:136:32]\n wire _vc_allocator_io_req_1_ready;\t// @[Router.scala:133:30]\n wire _vc_allocator_io_req_0_ready;\t// @[Router.scala:133:30]\n wire _vc_allocator_io_resp_1_vc_sel_0_12;\t// @[Router.scala:133:30]\n wire _vc_allocator_io_resp_1_vc_sel_0_13;\t// @[Router.scala:133:30]\n wire _vc_allocator_io_resp_1_vc_sel_0_16;\t// @[Router.scala:133:30]\n wire _vc_allocator_io_resp_1_vc_sel_0_17;\t// @[Router.scala:133:30]\n wire _vc_allocator_io_resp_1_vc_sel_0_20;\t// @[Router.scala:133:30]\n wire _vc_allocator_io_resp_1_vc_sel_0_21;\t// @[Router.scala:133:30]\n wire _vc_allocator_io_resp_0_vc_sel_1_10;\t// @[Router.scala:133:30]\n wire _vc_allocator_io_resp_0_vc_sel_1_11;\t// @[Router.scala:133:30]\n wire _vc_allocator_io_resp_0_vc_sel_1_14;\t// @[Router.scala:133:30]\n wire _vc_allocator_io_resp_0_vc_sel_1_15;\t// @[Router.scala:133:30]\n wire _vc_allocator_io_resp_0_vc_sel_1_18;\t// @[Router.scala:133:30]\n wire _vc_allocator_io_resp_0_vc_sel_1_19;\t// @[Router.scala:133:30]\n wire _vc_allocator_io_resp_0_vc_sel_1_20;\t// @[Router.scala:133:30]\n wire _vc_allocator_io_resp_0_vc_sel_1_21;\t// @[Router.scala:133:30]\n wire _vc_allocator_io_out_allocs_1_10_alloc;\t// @[Router.scala:133:30]\n wire _vc_allocator_io_out_allocs_1_11_alloc;\t// @[Router.scala:133:30]\n wire _vc_allocator_io_out_allocs_1_14_alloc;\t// @[Router.scala:133:30]\n wire _vc_allocator_io_out_allocs_1_15_alloc;\t// @[Router.scala:133:30]\n wire _vc_allocator_io_out_allocs_1_18_alloc;\t// @[Router.scala:133:30]\n wire _vc_allocator_io_out_allocs_1_19_alloc;\t// @[Router.scala:133:30]\n wire _vc_allocator_io_out_allocs_1_20_alloc;\t// @[Router.scala:133:30]\n wire _vc_allocator_io_out_allocs_1_21_alloc;\t// @[Router.scala:133:30]\n wire _vc_allocator_io_out_allocs_0_12_alloc;\t// @[Router.scala:133:30]\n wire _vc_allocator_io_out_allocs_0_13_alloc;\t// @[Router.scala:133:30]\n wire _vc_allocator_io_out_allocs_0_16_alloc;\t// @[Router.scala:133:30]\n wire _vc_allocator_io_out_allocs_0_17_alloc;\t// @[Router.scala:133:30]\n wire _vc_allocator_io_out_allocs_0_20_alloc;\t// @[Router.scala:133:30]\n wire _vc_allocator_io_out_allocs_0_21_alloc;\t// @[Router.scala:133:30]\n wire _switch_allocator_io_req_1_0_ready;\t// @[Router.scala:132:34]\n wire _switch_allocator_io_req_0_0_ready;\t// @[Router.scala:132:34]\n wire _switch_allocator_io_credit_alloc_1_10_alloc;\t// @[Router.scala:132:34]\n wire _switch_allocator_io_credit_alloc_1_11_alloc;\t// @[Router.scala:132:34]\n wire _switch_allocator_io_credit_alloc_1_14_alloc;\t// @[Router.scala:132:34]\n wire _switch_allocator_io_credit_alloc_1_15_alloc;\t// @[Router.scala:132:34]\n wire _switch_allocator_io_credit_alloc_1_18_alloc;\t// @[Router.scala:132:34]\n wire _switch_allocator_io_credit_alloc_1_19_alloc;\t// @[Router.scala:132:34]\n wire _switch_allocator_io_credit_alloc_1_20_alloc;\t// @[Router.scala:132:34]\n wire _switch_allocator_io_credit_alloc_1_21_alloc;\t// @[Router.scala:132:34]\n wire _switch_allocator_io_credit_alloc_0_12_alloc;\t// @[Router.scala:132:34]\n wire _switch_allocator_io_credit_alloc_0_13_alloc;\t// @[Router.scala:132:34]\n wire _switch_allocator_io_credit_alloc_0_16_alloc;\t// @[Router.scala:132:34]\n wire _switch_allocator_io_credit_alloc_0_17_alloc;\t// @[Router.scala:132:34]\n wire _switch_allocator_io_credit_alloc_0_20_alloc;\t// @[Router.scala:132:34]\n wire _switch_allocator_io_credit_alloc_0_21_alloc;\t// @[Router.scala:132:34]\n wire _switch_allocator_io_switch_sel_1_0_1_0;\t// @[Router.scala:132:34]\n wire _switch_allocator_io_switch_sel_1_0_0_0;\t// @[Router.scala:132:34]\n wire _switch_allocator_io_switch_sel_0_0_1_0;\t// @[Router.scala:132:34]\n wire _switch_allocator_io_switch_sel_0_0_0_0;\t// @[Router.scala:132:34]\n wire _switch_io_out_1_0_valid;\t// @[Router.scala:131:24]\n wire _switch_io_out_1_0_bits_head;\t// @[Router.scala:131:24]\n wire _switch_io_out_1_0_bits_tail;\t// @[Router.scala:131:24]\n wire [72:0] _switch_io_out_1_0_bits_payload;\t// @[Router.scala:131:24]\n wire [3:0] _switch_io_out_1_0_bits_flow_vnet_id;\t// @[Router.scala:131:24]\n wire [5:0] _switch_io_out_1_0_bits_flow_ingress_node;\t// @[Router.scala:131:24]\n wire [2:0] _switch_io_out_1_0_bits_flow_ingress_node_id;\t// @[Router.scala:131:24]\n wire [5:0] _switch_io_out_1_0_bits_flow_egress_node;\t// @[Router.scala:131:24]\n wire [2:0] _switch_io_out_1_0_bits_flow_egress_node_id;\t// @[Router.scala:131:24]\n wire [4:0] _switch_io_out_1_0_bits_virt_channel_id;\t// @[Router.scala:131:24]\n wire _switch_io_out_0_0_valid;\t// @[Router.scala:131:24]\n wire _switch_io_out_0_0_bits_head;\t// @[Router.scala:131:24]\n wire _switch_io_out_0_0_bits_tail;\t// @[Router.scala:131:24]\n wire [72:0] _switch_io_out_0_0_bits_payload;\t// @[Router.scala:131:24]\n wire [3:0] _switch_io_out_0_0_bits_flow_vnet_id;\t// @[Router.scala:131:24]\n wire [5:0] _switch_io_out_0_0_bits_flow_ingress_node;\t// @[Router.scala:131:24]\n wire [2:0] _switch_io_out_0_0_bits_flow_ingress_node_id;\t// @[Router.scala:131:24]\n wire [5:0] _switch_io_out_0_0_bits_flow_egress_node;\t// @[Router.scala:131:24]\n wire [2:0] _switch_io_out_0_0_bits_flow_egress_node_id;\t// @[Router.scala:131:24]\n wire [4:0] _switch_io_out_0_0_bits_virt_channel_id;\t// @[Router.scala:131:24]\n wire _output_unit_1_to_33_io_credit_available_10;\t// @[Router.scala:122:13]\n wire _output_unit_1_to_33_io_credit_available_11;\t// @[Router.scala:122:13]\n wire _output_unit_1_to_33_io_credit_available_14;\t// @[Router.scala:122:13]\n wire _output_unit_1_to_33_io_credit_available_15;\t// @[Router.scala:122:13]\n wire _output_unit_1_to_33_io_credit_available_18;\t// @[Router.scala:122:13]\n wire _output_unit_1_to_33_io_credit_available_19;\t// @[Router.scala:122:13]\n wire _output_unit_1_to_33_io_credit_available_20;\t// @[Router.scala:122:13]\n wire _output_unit_1_to_33_io_credit_available_21;\t// @[Router.scala:122:13]\n wire _output_unit_1_to_33_io_channel_status_10_occupied;\t// @[Router.scala:122:13]\n wire _output_unit_1_to_33_io_channel_status_11_occupied;\t// @[Router.scala:122:13]\n wire _output_unit_1_to_33_io_channel_status_14_occupied;\t// @[Router.scala:122:13]\n wire _output_unit_1_to_33_io_channel_status_15_occupied;\t// @[Router.scala:122:13]\n wire _output_unit_1_to_33_io_channel_status_18_occupied;\t// @[Router.scala:122:13]\n wire _output_unit_1_to_33_io_channel_status_19_occupied;\t// @[Router.scala:122:13]\n wire _output_unit_1_to_33_io_channel_status_20_occupied;\t// @[Router.scala:122:13]\n wire _output_unit_1_to_33_io_channel_status_21_occupied;\t// @[Router.scala:122:13]\n wire _output_unit_0_to_14_io_credit_available_12;\t// @[Router.scala:122:13]\n wire _output_unit_0_to_14_io_credit_available_13;\t// @[Router.scala:122:13]\n wire _output_unit_0_to_14_io_credit_available_16;\t// @[Router.scala:122:13]\n wire _output_unit_0_to_14_io_credit_available_17;\t// @[Router.scala:122:13]\n wire _output_unit_0_to_14_io_credit_available_20;\t// @[Router.scala:122:13]\n wire _output_unit_0_to_14_io_credit_available_21;\t// @[Router.scala:122:13]\n wire _output_unit_0_to_14_io_channel_status_12_occupied;\t// @[Router.scala:122:13]\n wire _output_unit_0_to_14_io_channel_status_13_occupied;\t// @[Router.scala:122:13]\n wire _output_unit_0_to_14_io_channel_status_16_occupied;\t// @[Router.scala:122:13]\n wire _output_unit_0_to_14_io_channel_status_17_occupied;\t// @[Router.scala:122:13]\n wire _output_unit_0_to_14_io_channel_status_20_occupied;\t// @[Router.scala:122:13]\n wire _output_unit_0_to_14_io_channel_status_21_occupied;\t// @[Router.scala:122:13]\n wire [4:0] _input_unit_1_from_33_io_router_req_bits_src_virt_id;\t// @[Router.scala:112:13]\n wire [3:0] _input_unit_1_from_33_io_router_req_bits_flow_vnet_id;\t// @[Router.scala:112:13]\n wire [5:0] _input_unit_1_from_33_io_router_req_bits_flow_ingress_node;\t// @[Router.scala:112:13]\n wire [2:0] _input_unit_1_from_33_io_router_req_bits_flow_ingress_node_id;\t// @[Router.scala:112:13]\n wire [5:0] _input_unit_1_from_33_io_router_req_bits_flow_egress_node;\t// @[Router.scala:112:13]\n wire [2:0] _input_unit_1_from_33_io_router_req_bits_flow_egress_node_id;\t// @[Router.scala:112:13]\n wire _input_unit_1_from_33_io_vcalloc_req_valid;\t// @[Router.scala:112:13]\n wire _input_unit_1_from_33_io_vcalloc_req_bits_vc_sel_0_12;\t// @[Router.scala:112:13]\n wire _input_unit_1_from_33_io_vcalloc_req_bits_vc_sel_0_13;\t// @[Router.scala:112:13]\n wire _input_unit_1_from_33_io_vcalloc_req_bits_vc_sel_0_16;\t// @[Router.scala:112:13]\n wire _input_unit_1_from_33_io_vcalloc_req_bits_vc_sel_0_17;\t// @[Router.scala:112:13]\n wire _input_unit_1_from_33_io_vcalloc_req_bits_vc_sel_0_20;\t// @[Router.scala:112:13]\n wire _input_unit_1_from_33_io_vcalloc_req_bits_vc_sel_0_21;\t// @[Router.scala:112:13]\n wire _input_unit_1_from_33_io_salloc_req_0_valid;\t// @[Router.scala:112:13]\n wire _input_unit_1_from_33_io_salloc_req_0_bits_vc_sel_1_2;\t// @[Router.scala:112:13]\n wire _input_unit_1_from_33_io_salloc_req_0_bits_vc_sel_1_3;\t// @[Router.scala:112:13]\n wire _input_unit_1_from_33_io_salloc_req_0_bits_vc_sel_1_8;\t// @[Router.scala:112:13]\n wire _input_unit_1_from_33_io_salloc_req_0_bits_vc_sel_1_9;\t// @[Router.scala:112:13]\n wire _input_unit_1_from_33_io_salloc_req_0_bits_vc_sel_1_10;\t// @[Router.scala:112:13]\n wire _input_unit_1_from_33_io_salloc_req_0_bits_vc_sel_1_11;\t// @[Router.scala:112:13]\n wire _input_unit_1_from_33_io_salloc_req_0_bits_vc_sel_1_12;\t// @[Router.scala:112:13]\n wire _input_unit_1_from_33_io_salloc_req_0_bits_vc_sel_1_13;\t// @[Router.scala:112:13]\n wire _input_unit_1_from_33_io_salloc_req_0_bits_vc_sel_1_14;\t// @[Router.scala:112:13]\n wire _input_unit_1_from_33_io_salloc_req_0_bits_vc_sel_1_15;\t// @[Router.scala:112:13]\n wire _input_unit_1_from_33_io_salloc_req_0_bits_vc_sel_1_16;\t// @[Router.scala:112:13]\n wire _input_unit_1_from_33_io_salloc_req_0_bits_vc_sel_1_17;\t// @[Router.scala:112:13]\n wire _input_unit_1_from_33_io_salloc_req_0_bits_vc_sel_1_18;\t// @[Router.scala:112:13]\n wire _input_unit_1_from_33_io_salloc_req_0_bits_vc_sel_1_19;\t// @[Router.scala:112:13]\n wire _input_unit_1_from_33_io_salloc_req_0_bits_vc_sel_1_20;\t// @[Router.scala:112:13]\n wire _input_unit_1_from_33_io_salloc_req_0_bits_vc_sel_1_21;\t// @[Router.scala:112:13]\n wire _input_unit_1_from_33_io_salloc_req_0_bits_vc_sel_0_2;\t// @[Router.scala:112:13]\n wire _input_unit_1_from_33_io_salloc_req_0_bits_vc_sel_0_3;\t// @[Router.scala:112:13]\n wire _input_unit_1_from_33_io_salloc_req_0_bits_vc_sel_0_8;\t// @[Router.scala:112:13]\n wire _input_unit_1_from_33_io_salloc_req_0_bits_vc_sel_0_9;\t// @[Router.scala:112:13]\n wire _input_unit_1_from_33_io_salloc_req_0_bits_vc_sel_0_10;\t// @[Router.scala:112:13]\n wire _input_unit_1_from_33_io_salloc_req_0_bits_vc_sel_0_11;\t// @[Router.scala:112:13]\n wire _input_unit_1_from_33_io_salloc_req_0_bits_vc_sel_0_12;\t// @[Router.scala:112:13]\n wire _input_unit_1_from_33_io_salloc_req_0_bits_vc_sel_0_13;\t// @[Router.scala:112:13]\n wire _input_unit_1_from_33_io_salloc_req_0_bits_vc_sel_0_14;\t// @[Router.scala:112:13]\n wire _input_unit_1_from_33_io_salloc_req_0_bits_vc_sel_0_15;\t// @[Router.scala:112:13]\n wire _input_unit_1_from_33_io_salloc_req_0_bits_vc_sel_0_16;\t// @[Router.scala:112:13]\n wire _input_unit_1_from_33_io_salloc_req_0_bits_vc_sel_0_17;\t// @[Router.scala:112:13]\n wire _input_unit_1_from_33_io_salloc_req_0_bits_vc_sel_0_18;\t// @[Router.scala:112:13]\n wire _input_unit_1_from_33_io_salloc_req_0_bits_vc_sel_0_19;\t// @[Router.scala:112:13]\n wire _input_unit_1_from_33_io_salloc_req_0_bits_vc_sel_0_20;\t// @[Router.scala:112:13]\n wire _input_unit_1_from_33_io_salloc_req_0_bits_vc_sel_0_21;\t// @[Router.scala:112:13]\n wire _input_unit_1_from_33_io_salloc_req_0_bits_tail;\t// @[Router.scala:112:13]\n wire _input_unit_1_from_33_io_out_0_valid;\t// @[Router.scala:112:13]\n wire _input_unit_1_from_33_io_out_0_bits_flit_head;\t// @[Router.scala:112:13]\n wire _input_unit_1_from_33_io_out_0_bits_flit_tail;\t// @[Router.scala:112:13]\n wire [72:0] _input_unit_1_from_33_io_out_0_bits_flit_payload;\t// @[Router.scala:112:13]\n wire [3:0] _input_unit_1_from_33_io_out_0_bits_flit_flow_vnet_id;\t// @[Router.scala:112:13]\n wire [5:0] _input_unit_1_from_33_io_out_0_bits_flit_flow_ingress_node;\t// @[Router.scala:112:13]\n wire [2:0] _input_unit_1_from_33_io_out_0_bits_flit_flow_ingress_node_id;\t// @[Router.scala:112:13]\n wire [5:0] _input_unit_1_from_33_io_out_0_bits_flit_flow_egress_node;\t// @[Router.scala:112:13]\n wire [2:0] _input_unit_1_from_33_io_out_0_bits_flit_flow_egress_node_id;\t// @[Router.scala:112:13]\n wire [4:0] _input_unit_1_from_33_io_out_0_bits_out_virt_channel;\t// @[Router.scala:112:13]\n wire [4:0] _input_unit_0_from_14_io_router_req_bits_src_virt_id;\t// @[Router.scala:112:13]\n wire [3:0] _input_unit_0_from_14_io_router_req_bits_flow_vnet_id;\t// @[Router.scala:112:13]\n wire [5:0] _input_unit_0_from_14_io_router_req_bits_flow_ingress_node;\t// @[Router.scala:112:13]\n wire [2:0] _input_unit_0_from_14_io_router_req_bits_flow_ingress_node_id;\t// @[Router.scala:112:13]\n wire [5:0] _input_unit_0_from_14_io_router_req_bits_flow_egress_node;\t// @[Router.scala:112:13]\n wire [2:0] _input_unit_0_from_14_io_router_req_bits_flow_egress_node_id;\t// @[Router.scala:112:13]\n wire _input_unit_0_from_14_io_vcalloc_req_valid;\t// @[Router.scala:112:13]\n wire _input_unit_0_from_14_io_vcalloc_req_bits_vc_sel_1_10;\t// @[Router.scala:112:13]\n wire _input_unit_0_from_14_io_vcalloc_req_bits_vc_sel_1_11;\t// @[Router.scala:112:13]\n wire _input_unit_0_from_14_io_vcalloc_req_bits_vc_sel_1_14;\t// @[Router.scala:112:13]\n wire _input_unit_0_from_14_io_vcalloc_req_bits_vc_sel_1_15;\t// @[Router.scala:112:13]\n wire _input_unit_0_from_14_io_vcalloc_req_bits_vc_sel_1_18;\t// @[Router.scala:112:13]\n wire _input_unit_0_from_14_io_vcalloc_req_bits_vc_sel_1_19;\t// @[Router.scala:112:13]\n wire _input_unit_0_from_14_io_vcalloc_req_bits_vc_sel_1_20;\t// @[Router.scala:112:13]\n wire _input_unit_0_from_14_io_vcalloc_req_bits_vc_sel_1_21;\t// @[Router.scala:112:13]\n wire _input_unit_0_from_14_io_salloc_req_0_valid;\t// @[Router.scala:112:13]\n wire _input_unit_0_from_14_io_salloc_req_0_bits_vc_sel_1_2;\t// @[Router.scala:112:13]\n wire _input_unit_0_from_14_io_salloc_req_0_bits_vc_sel_1_3;\t// @[Router.scala:112:13]\n wire _input_unit_0_from_14_io_salloc_req_0_bits_vc_sel_1_8;\t// @[Router.scala:112:13]\n wire _input_unit_0_from_14_io_salloc_req_0_bits_vc_sel_1_9;\t// @[Router.scala:112:13]\n wire _input_unit_0_from_14_io_salloc_req_0_bits_vc_sel_1_10;\t// @[Router.scala:112:13]\n wire _input_unit_0_from_14_io_salloc_req_0_bits_vc_sel_1_11;\t// @[Router.scala:112:13]\n wire _input_unit_0_from_14_io_salloc_req_0_bits_vc_sel_1_12;\t// @[Router.scala:112:13]\n wire _input_unit_0_from_14_io_salloc_req_0_bits_vc_sel_1_13;\t// @[Router.scala:112:13]\n wire _input_unit_0_from_14_io_salloc_req_0_bits_vc_sel_1_14;\t// @[Router.scala:112:13]\n wire _input_unit_0_from_14_io_salloc_req_0_bits_vc_sel_1_15;\t// @[Router.scala:112:13]\n wire _input_unit_0_from_14_io_salloc_req_0_bits_vc_sel_1_16;\t// @[Router.scala:112:13]\n wire _input_unit_0_from_14_io_salloc_req_0_bits_vc_sel_1_17;\t// @[Router.scala:112:13]\n wire _input_unit_0_from_14_io_salloc_req_0_bits_vc_sel_1_18;\t// @[Router.scala:112:13]\n wire _input_unit_0_from_14_io_salloc_req_0_bits_vc_sel_1_19;\t// @[Router.scala:112:13]\n wire _input_unit_0_from_14_io_salloc_req_0_bits_vc_sel_1_20;\t// @[Router.scala:112:13]\n wire _input_unit_0_from_14_io_salloc_req_0_bits_vc_sel_1_21;\t// @[Router.scala:112:13]\n wire _input_unit_0_from_14_io_salloc_req_0_bits_vc_sel_0_2;\t// @[Router.scala:112:13]\n wire _input_unit_0_from_14_io_salloc_req_0_bits_vc_sel_0_3;\t// @[Router.scala:112:13]\n wire _input_unit_0_from_14_io_salloc_req_0_bits_vc_sel_0_8;\t// @[Router.scala:112:13]\n wire _input_unit_0_from_14_io_salloc_req_0_bits_vc_sel_0_9;\t// @[Router.scala:112:13]\n wire _input_unit_0_from_14_io_salloc_req_0_bits_vc_sel_0_10;\t// @[Router.scala:112:13]\n wire _input_unit_0_from_14_io_salloc_req_0_bits_vc_sel_0_11;\t// @[Router.scala:112:13]\n wire _input_unit_0_from_14_io_salloc_req_0_bits_vc_sel_0_12;\t// @[Router.scala:112:13]\n wire _input_unit_0_from_14_io_salloc_req_0_bits_vc_sel_0_13;\t// @[Router.scala:112:13]\n wire _input_unit_0_from_14_io_salloc_req_0_bits_vc_sel_0_14;\t// @[Router.scala:112:13]\n wire _input_unit_0_from_14_io_salloc_req_0_bits_vc_sel_0_15;\t// @[Router.scala:112:13]\n wire _input_unit_0_from_14_io_salloc_req_0_bits_vc_sel_0_16;\t// @[Router.scala:112:13]\n wire _input_unit_0_from_14_io_salloc_req_0_bits_vc_sel_0_17;\t// @[Router.scala:112:13]\n wire _input_unit_0_from_14_io_salloc_req_0_bits_vc_sel_0_18;\t// @[Router.scala:112:13]\n wire _input_unit_0_from_14_io_salloc_req_0_bits_vc_sel_0_19;\t// @[Router.scala:112:13]\n wire _input_unit_0_from_14_io_salloc_req_0_bits_vc_sel_0_20;\t// @[Router.scala:112:13]\n wire _input_unit_0_from_14_io_salloc_req_0_bits_vc_sel_0_21;\t// @[Router.scala:112:13]\n wire _input_unit_0_from_14_io_salloc_req_0_bits_tail;\t// @[Router.scala:112:13]\n wire _input_unit_0_from_14_io_out_0_valid;\t// @[Router.scala:112:13]\n wire _input_unit_0_from_14_io_out_0_bits_flit_head;\t// @[Router.scala:112:13]\n wire _input_unit_0_from_14_io_out_0_bits_flit_tail;\t// @[Router.scala:112:13]\n wire [72:0] _input_unit_0_from_14_io_out_0_bits_flit_payload;\t// @[Router.scala:112:13]\n wire [3:0] _input_unit_0_from_14_io_out_0_bits_flit_flow_vnet_id;\t// @[Router.scala:112:13]\n wire [5:0] _input_unit_0_from_14_io_out_0_bits_flit_flow_ingress_node;\t// @[Router.scala:112:13]\n wire [2:0] _input_unit_0_from_14_io_out_0_bits_flit_flow_ingress_node_id;\t// @[Router.scala:112:13]\n wire [5:0] _input_unit_0_from_14_io_out_0_bits_flit_flow_egress_node;\t// @[Router.scala:112:13]\n wire [2:0] _input_unit_0_from_14_io_out_0_bits_flit_flow_egress_node_id;\t// @[Router.scala:112:13]\n wire [4:0] _input_unit_0_from_14_io_out_0_bits_out_virt_channel;\t// @[Router.scala:112:13]\n wire [1:0] fires_count = {1'h0, _vc_allocator_io_req_0_ready & _input_unit_0_from_14_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_1_ready & _input_unit_1_from_33_io_vcalloc_req_valid};\t// @[Decoupled.scala:51:35]\n reg REG_1_0_1_0;\t// @[Router.scala:178:14]\n reg REG_1_0_0_0;\t// @[Router.scala:178:14]\n reg REG_0_0_1_0;\t// @[Router.scala:178:14]\n reg REG_0_0_0_0;\t// @[Router.scala:178:14]\n reg [63:0] debug_tsc;\t// @[Router.scala:195:28]\n reg [63:0] debug_sample;\t// @[Router.scala:197:31]\n wire _GEN = debug_sample == {44'h0, _plusarg_reader_out - 20'h1};\t// @[PlusArg.scala:80:11]\n reg [63:0] util_ctr;\t// @[Router.scala:203:29]\n reg fired;\t// @[Router.scala:204:26]\n wire _GEN_0 = (|_plusarg_reader_out) & _GEN;\t// @[PlusArg.scala:80:11]\n wire _GEN_1 = _GEN_0 & fired;\t// @[Router.scala:204:26, :207:{33,71}]\n reg [63:0] util_ctr_1;\t// @[Router.scala:203:29]\n reg fired_1;\t// @[Router.scala:204:26]\n wire _GEN_2 = _GEN_0 & fired_1;\t// @[Router.scala:204:26, :207:{33,71}]"}}},{"rowIdx":570,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to the following Chisel files.\nFile PE.scala:\n// See README.md for license details.\npackage gemmini\n\nimport chisel3._\nimport chisel3.util._\n\nclass PEControl[T <: Data : Arithmetic](accType: T) extends Bundle {\n val dataflow = UInt(1.W) // TODO make this an Enum\n val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)?\n val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats\n\n}\n\nclass MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module {\n import ev._\n val io = IO(new Bundle {\n val in_a = Input(inputType)\n val in_b = Input(inputType)\n val in_c = Input(cType)\n val out_d = Output(dType)\n })\n\n io.out_d := io.in_c.mac(io.in_a, io.in_b)\n}\n\n// TODO update documentation\n/**\n * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh.\n * @param width Data width of operands\n */\nclass PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int)\n (implicit ev: Arithmetic[T]) extends Module { // Debugging variables\n import ev._\n\n val io = IO(new Bundle {\n val in_a = Input(inputType)\n val in_b = Input(outputType)\n val in_d = Input(outputType)\n val out_a = Output(inputType)\n val out_b = Output(outputType)\n val out_c = Output(outputType)\n\n val in_control = Input(new PEControl(accType))\n val out_control = Output(new PEControl(accType))\n\n val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W))\n val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W))\n\n val in_last = Input(Bool())\n val out_last = Output(Bool())\n\n val in_valid = Input(Bool())\n val out_valid = Output(Bool())\n\n val bad_dataflow = Output(Bool())\n })\n\n val cType = if (df == Dataflow.WS) inputType else accType\n\n // When creating PEs that support multiple dataflows, the\n // elaboration/synthesis tools often fail to consolidate and de-duplicate\n // MAC units. To force mac circuitry to be re-used, we create a \"mac_unit\"\n // module here which just performs a single MAC operation\n val mac_unit = Module(new MacUnit(inputType,\n if (df == Dataflow.WS) outputType else accType, outputType))\n\n val a = io.in_a\n val b = io.in_b\n val d = io.in_d\n val c1 = Reg(cType)\n val c2 = Reg(cType)\n val dataflow = io.in_control.dataflow\n val prop = io.in_control.propagate\n val shift = io.in_control.shift\n val id = io.in_id\n val last = io.in_last\n val valid = io.in_valid\n\n io.out_a := a\n io.out_control.dataflow := dataflow\n io.out_control.propagate := prop\n io.out_control.shift := shift\n io.out_id := id\n io.out_last := last\n io.out_valid := valid\n\n mac_unit.io.in_a := a\n\n val last_s = RegEnable(prop, valid)\n val flip = last_s =/= prop\n val shift_offset = Mux(flip, shift, 0.U)\n\n // Which dataflow are we using?\n val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W)\n val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W)\n\n // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)?\n val COMPUTE = 0.U(1.W)\n val PROPAGATE = 1.U(1.W)\n\n io.bad_dataflow := false.B\n when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) {\n when(prop === PROPAGATE) {\n io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType)\n io.out_b := b\n mac_unit.io.in_b := b.asTypeOf(inputType)\n mac_unit.io.in_c := c2\n c2 := mac_unit.io.out_d\n c1 := d.withWidthOf(cType)\n }.otherwise {\n io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType)\n io.out_b := b\n mac_unit.io.in_b := b.asTypeOf(inputType)\n mac_unit.io.in_c := c1\n c1 := mac_unit.io.out_d\n c2 := d.withWidthOf(cType)\n }\n }.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) {\n when(prop === PROPAGATE) {\n io.out_c := c1\n mac_unit.io.in_b := c2.asTypeOf(inputType)\n mac_unit.io.in_c := b\n io.out_b := mac_unit.io.out_d\n c1 := d\n }.otherwise {\n io.out_c := c2\n mac_unit.io.in_b := c1.asTypeOf(inputType)\n mac_unit.io.in_c := b\n io.out_b := mac_unit.io.out_d\n c2 := d\n }\n }.otherwise {\n io.bad_dataflow := true.B\n //assert(false.B, \"unknown dataflow\")\n io.out_c := DontCare\n io.out_b := DontCare\n mac_unit.io.in_b := b.asTypeOf(inputType)\n mac_unit.io.in_c := c2\n }\n\n when (!valid) {\n c1 := c1\n c2 := c2\n mac_unit.io.in_b := DontCare\n mac_unit.io.in_c := DontCare\n }\n}\nFile Arithmetic.scala:\n// A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own:\n// implicit MyTypeArithmetic extends Arithmetic[MyType] { ... }\n\npackage gemmini\n\nimport chisel3._\nimport chisel3.util._\nimport hardfloat._\n\n// Bundles that represent the raw bits of custom datatypes\ncase class Float(expWidth: Int, sigWidth: Int) extends Bundle {\n val bits = UInt((expWidth + sigWidth).W)\n\n val bias: Int = (1 << (expWidth-1)) - 1\n}\n\ncase class DummySInt(w: Int) extends Bundle {\n val bits = UInt(w.W)\n def dontCare: DummySInt = {\n val o = Wire(new DummySInt(w))\n o.bits := 0.U\n o\n }\n}\n\n// The Arithmetic typeclass which implements various arithmetic operations on custom datatypes\nabstract class Arithmetic[T <: Data] {\n implicit def cast(t: T): ArithmeticOps[T]\n}\n\nabstract class ArithmeticOps[T <: Data](self: T) {\n def *(t: T): T\n def mac(m1: T, m2: T): T // Returns (m1 * m2 + self)\n def +(t: T): T\n def -(t: T): T\n def >>(u: UInt): T // This is a rounding shift! Rounds away from 0\n def >(t: T): Bool\n def identity: T\n def withWidthOf(t: T): T\n def clippedToWidthOf(t: T): T // Like \"withWidthOf\", except that it saturates\n def relu: T\n def zero: T\n def minimum: T\n\n // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers\n def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None\n def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None\n def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None\n def mult_with_reciprocal[U <: Data](reciprocal: U) = self\n}\n\nobject Arithmetic {\n implicit object UIntArithmetic extends Arithmetic[UInt] {\n override implicit def cast(self: UInt) = new ArithmeticOps(self) {\n override def *(t: UInt) = self * t\n override def mac(m1: UInt, m2: UInt) = m1 * m2 + self\n override def +(t: UInt) = self + t\n override def -(t: UInt) = self - t\n\n override def >>(u: UInt) = {\n // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm\n\n // TODO Do we need to explicitly handle the cases where \"u\" is a small number (like 0)? What is the default behavior here?\n val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))\n val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U\n val ones_digit = self(u)\n\n val r = point_five & (zeros | ones_digit)\n\n (self >> u).asUInt + r\n }\n\n override def >(t: UInt): Bool = self > t\n\n override def withWidthOf(t: UInt) = self.asTypeOf(t)\n\n override def clippedToWidthOf(t: UInt) = {\n val sat = ((1 << (t.getWidth-1))-1).U\n Mux(self > sat, sat, self)(t.getWidth-1, 0)\n }\n\n override def relu: UInt = self\n\n override def zero: UInt = 0.U\n override def identity: UInt = 1.U\n override def minimum: UInt = 0.U\n }\n }\n\n implicit object SIntArithmetic extends Arithmetic[SInt] {\n override implicit def cast(self: SInt) = new ArithmeticOps(self) {\n override def *(t: SInt) = self * t\n override def mac(m1: SInt, m2: SInt) = m1 * m2 + self\n override def +(t: SInt) = self + t\n override def -(t: SInt) = self - t\n\n override def >>(u: UInt) = {\n // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm\n\n // TODO Do we need to explicitly handle the cases where \"u\" is a small number (like 0)? What is the default behavior here?\n val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))\n val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U\n val ones_digit = self(u)\n\n val r = (point_five & (zeros | ones_digit)).asBool\n\n (self >> u).asSInt + Mux(r, 1.S, 0.S)\n }\n\n override def >(t: SInt): Bool = self > t\n\n override def withWidthOf(t: SInt) = {\n if (self.getWidth >= t.getWidth)\n self(t.getWidth-1, 0).asSInt\n else {\n val sign_bits = t.getWidth - self.getWidth\n val sign = self(self.getWidth-1)\n Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t)\n }\n }\n\n override def clippedToWidthOf(t: SInt): SInt = {\n val maxsat = ((1 << (t.getWidth-1))-1).S\n val minsat = (-(1 << (t.getWidth-1))).S\n MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt\n }\n\n override def relu: SInt = Mux(self >= 0.S, self, 0.S)\n\n override def zero: SInt = 0.S\n override def identity: SInt = 1.S\n override def minimum: SInt = (-(1 << (self.getWidth-1))).S\n\n override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {\n // TODO this uses a floating point divider, but we should use an integer divider instead\n\n val input = Wire(Decoupled(denom_t.cloneType))\n val output = Wire(Decoupled(self.cloneType))\n\n // We translate our integer to floating-point form so that we can use the hardfloat divider\n val expWidth = log2Up(self.getWidth) + 1\n val sigWidth = self.getWidth\n\n def sin_to_float(x: SInt) = {\n val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))\n in_to_rec_fn.io.signedIn := true.B\n in_to_rec_fn.io.in := x.asUInt\n in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag\n in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding\n\n in_to_rec_fn.io.out\n }\n\n def uin_to_float(x: UInt) = {\n val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))\n in_to_rec_fn.io.signedIn := false.B\n in_to_rec_fn.io.in := x\n in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag\n in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding\n\n in_to_rec_fn.io.out\n }\n\n def float_to_in(x: UInt) = {\n val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))\n rec_fn_to_in.io.signedOut := true.B\n rec_fn_to_in.io.in := x\n rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag\n\n rec_fn_to_in.io.out.asSInt\n }\n\n val self_rec = sin_to_float(self)\n val denom_rec = uin_to_float(input.bits)\n\n // Instantiate the hardloat divider\n val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))\n\n input.ready := divider.io.inReady\n divider.io.inValid := input.valid\n divider.io.sqrtOp := false.B\n divider.io.a := self_rec\n divider.io.b := denom_rec\n divider.io.roundingMode := consts.round_minMag\n divider.io.detectTininess := consts.tininess_afterRounding\n\n output.valid := divider.io.outValid_div\n output.bits := float_to_in(divider.io.out)\n\n assert(!output.valid || output.ready)\n\n Some((input, output))\n }\n\n override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {\n // TODO this uses a floating point divider, but we should use an integer divider instead\n\n val input = Wire(Decoupled(UInt(0.W)))\n val output = Wire(Decoupled(self.cloneType))\n\n input.bits := DontCare\n\n // We translate our integer to floating-point form so that we can use the hardfloat divider\n val expWidth = log2Up(self.getWidth) + 1\n val sigWidth = self.getWidth\n\n def in_to_float(x: SInt) = {\n val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))\n in_to_rec_fn.io.signedIn := true.B\n in_to_rec_fn.io.in := x.asUInt\n in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag\n in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding\n\n in_to_rec_fn.io.out\n }\n\n def float_to_in(x: UInt) = {\n val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))\n rec_fn_to_in.io.signedOut := true.B\n rec_fn_to_in.io.in := x\n rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag\n\n rec_fn_to_in.io.out.asSInt\n }\n\n val self_rec = in_to_float(self)\n\n // Instantiate the hardloat sqrt\n val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0))\n\n input.ready := sqrter.io.inReady\n sqrter.io.inValid := input.valid\n sqrter.io.sqrtOp := true.B\n sqrter.io.a := self_rec\n sqrter.io.b := DontCare\n sqrter.io.roundingMode := consts.round_minMag\n sqrter.io.detectTininess := consts.tininess_afterRounding\n\n output.valid := sqrter.io.outValid_sqrt\n output.bits := float_to_in(sqrter.io.out)\n\n assert(!output.valid || output.ready)\n\n Some((input, output))\n }\n\n override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match {\n case Float(expWidth, sigWidth) =>\n val input = Wire(Decoupled(UInt(0.W)))\n val output = Wire(Decoupled(u.cloneType))\n\n input.bits := DontCare\n\n // We translate our integer to floating-point form so that we can use the hardfloat divider\n def in_to_float(x: SInt) = {\n val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))\n in_to_rec_fn.io.signedIn := true.B\n in_to_rec_fn.io.in := x.asUInt\n in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag\n in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding\n\n in_to_rec_fn.io.out\n }\n\n val self_rec = in_to_float(self)\n val one_rec = in_to_float(1.S)\n\n // Instantiate the hardloat divider\n val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))\n\n input.ready := divider.io.inReady\n divider.io.inValid := input.valid\n divider.io.sqrtOp := false.B\n divider.io.a := one_rec\n divider.io.b := self_rec\n divider.io.roundingMode := consts.round_near_even\n divider.io.detectTininess := consts.tininess_afterRounding\n\n output.valid := divider.io.outValid_div\n output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u)\n\n assert(!output.valid || output.ready)\n\n Some((input, output))\n\n case _ => None\n }\n\n override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match {\n case recip @ Float(expWidth, sigWidth) =>\n def in_to_float(x: SInt) = {\n val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))\n in_to_rec_fn.io.signedIn := true.B\n in_to_rec_fn.io.in := x.asUInt\n in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag\n in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding\n\n in_to_rec_fn.io.out\n }\n\n def float_to_in(x: UInt) = {\n val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))\n rec_fn_to_in.io.signedOut := true.B\n rec_fn_to_in.io.in := x\n rec_fn_to_in.io.roundingMode := consts.round_minMag\n\n rec_fn_to_in.io.out.asSInt\n }\n\n val self_rec = in_to_float(self)\n val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits)\n\n // Instantiate the hardloat divider\n val muladder = Module(new MulRecFN(expWidth, sigWidth))\n muladder.io.roundingMode := consts.round_near_even\n muladder.io.detectTininess := consts.tininess_afterRounding\n\n muladder.io.a := self_rec\n muladder.io.b := reciprocal_rec\n\n float_to_in(muladder.io.out)\n\n case _ => self\n }\n }\n }\n\n implicit object FloatArithmetic extends Arithmetic[Float] {\n // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array\n\n override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) {\n override def *(t: Float): Float = {\n val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)\n val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)\n\n val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))\n t_resizer.io.in := t_rec\n t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag\n t_resizer.io.detectTininess := consts.tininess_afterRounding\n val t_rec_resized = t_resizer.io.out\n\n val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))\n\n muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag\n muladder.io.detectTininess := consts.tininess_afterRounding\n\n muladder.io.a := self_rec\n muladder.io.b := t_rec_resized\n\n val out = Wire(Float(self.expWidth, self.sigWidth))\n out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)\n out\n }\n\n override def mac(m1: Float, m2: Float): Float = {\n // Recode all operands\n val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits)\n val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits)\n val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)\n\n // Resize m1 to self's width\n val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth))\n m1_resizer.io.in := m1_rec\n m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag\n m1_resizer.io.detectTininess := consts.tininess_afterRounding\n val m1_rec_resized = m1_resizer.io.out\n \n // Resize m2 to self's width\n val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth))\n m2_resizer.io.in := m2_rec\n m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag\n m2_resizer.io.detectTininess := consts.tininess_afterRounding\n val m2_rec_resized = m2_resizer.io.out\n\n // Perform multiply-add\n val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))\n\n muladder.io.op := 0.U\n muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag\n muladder.io.detectTininess := consts.tininess_afterRounding\n\n muladder.io.a := m1_rec_resized\n muladder.io.b := m2_rec_resized\n muladder.io.c := self_rec\n\n // Convert result to standard format // TODO remove these intermediate recodings\n val out = Wire(Float(self.expWidth, self.sigWidth))\n out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)\n out\n }\n\n override def +(t: Float): Float = {\n require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code\n\n // Recode all operands\n val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)\n val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)\n\n // Generate 1 as a float\n val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth))\n in_to_rec_fn.io.signedIn := false.B\n in_to_rec_fn.io.in := 1.U\n in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag\n in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding\n\n val one_rec = in_to_rec_fn.io.out\n\n // Resize t\n val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))\n t_resizer.io.in := t_rec\n t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag\n t_resizer.io.detectTininess := consts.tininess_afterRounding\n val t_rec_resized = t_resizer.io.out\n\n // Perform addition\n val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))\n\n muladder.io.op := 0.U\n muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag\n muladder.io.detectTininess := consts.tininess_afterRounding\n\n muladder.io.a := t_rec_resized\n muladder.io.b := one_rec\n muladder.io.c := self_rec\n\n val result = Wire(Float(self.expWidth, self.sigWidth))\n result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)\n result\n }\n\n override def -(t: Float): Float = {\n val t_sgn = t.bits(t.getWidth-1)\n val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t)\n self + neg_t\n }\n\n override def >>(u: UInt): Float = {\n // Recode self\n val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)\n\n // Get 2^(-u) as a recoded float\n val shift_exp = Wire(UInt(self.expWidth.W))\n shift_exp := self.bias.U - u\n val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W))\n val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn)\n\n assert(shift_exp =/= 0.U, \"scaling by denormalized numbers is not currently supported\")\n\n // Multiply self and 2^(-u)\n val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))\n\n muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag\n muladder.io.detectTininess := consts.tininess_afterRounding\n\n muladder.io.a := self_rec\n muladder.io.b := shift_rec\n\n val result = Wire(Float(self.expWidth, self.sigWidth))\n result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)\n result\n }\n\n override def >(t: Float): Bool = {\n // Recode all operands\n val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)\n val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)\n\n // Resize t to self's width\n val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))\n t_resizer.io.in := t_rec\n t_resizer.io.roundingMode := consts.round_near_even\n t_resizer.io.detectTininess := consts.tininess_afterRounding\n val t_rec_resized = t_resizer.io.out\n\n val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth))\n comparator.io.a := self_rec\n comparator.io.b := t_rec_resized\n comparator.io.signaling := false.B\n\n comparator.io.gt\n }\n\n override def withWidthOf(t: Float): Float = {\n val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)\n\n val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))\n resizer.io.in := self_rec\n resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag\n resizer.io.detectTininess := consts.tininess_afterRounding\n\n val result = Wire(Float(t.expWidth, t.sigWidth))\n result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)\n result\n }\n\n override def clippedToWidthOf(t: Float): Float = {\n // TODO check for overflow. Right now, we just assume that overflow doesn't happen\n val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)\n\n val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))\n resizer.io.in := self_rec\n resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag\n resizer.io.detectTininess := consts.tininess_afterRounding\n\n val result = Wire(Float(t.expWidth, t.sigWidth))\n result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)\n result\n }\n\n override def relu: Float = {\n val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits)\n\n val result = Wire(Float(self.expWidth, self.sigWidth))\n result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits)\n result\n }\n\n override def zero: Float = 0.U.asTypeOf(self)\n override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)\n override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)\n }\n }\n\n implicit object DummySIntArithmetic extends Arithmetic[DummySInt] {\n override implicit def cast(self: DummySInt) = new ArithmeticOps(self) {\n override def *(t: DummySInt) = self.dontCare\n override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare\n override def +(t: DummySInt) = self.dontCare\n override def -(t: DummySInt) = self.dontCare\n override def >>(t: UInt) = self.dontCare\n override def >(t: DummySInt): Bool = false.B\n override def identity = self.dontCare\n override def withWidthOf(t: DummySInt) = self.dontCare\n override def clippedToWidthOf(t: DummySInt) = self.dontCare\n override def relu = self.dontCare\n override def zero = self.dontCare\n override def minimum: DummySInt = self.dontCare\n }\n }\n}\n"},"response":{"kind":"string","value":"module PE_496(\t// @[PE.scala:31:7]\n input clock,\t// @[PE.scala:31:7]\n input reset,\t// @[PE.scala:31:7]\n input [7:0] io_in_a,\t// @[PE.scala:35:14]\n input [19:0] io_in_b,\t// @[PE.scala:35:14]\n input [19:0] io_in_d,\t// @[PE.scala:35:14]\n output [7:0] io_out_a,\t// @[PE.scala:35:14]\n output [19:0] io_out_b,\t// @[PE.scala:35:14]\n output [19:0] io_out_c,\t// @[PE.scala:35:14]\n input io_in_control_dataflow,\t// @[PE.scala:35:14]\n input io_in_control_propagate,\t// @[PE.scala:35:14]\n input [4:0] io_in_control_shift,\t// @[PE.scala:35:14]\n output io_out_control_dataflow,\t// @[PE.scala:35:14]\n output io_out_control_propagate,\t// @[PE.scala:35:14]\n output [4:0] io_out_control_shift,\t// @[PE.scala:35:14]\n input [2:0] io_in_id,\t// @[PE.scala:35:14]\n output [2:0] io_out_id,\t// @[PE.scala:35:14]\n input io_in_last,\t// @[PE.scala:35:14]\n output io_out_last,\t// @[PE.scala:35:14]\n input io_in_valid,\t// @[PE.scala:35:14]\n output io_out_valid\t// @[PE.scala:35:14]\n);\n\n wire [7:0] io_in_a_0 = io_in_a;\t// @[PE.scala:31:7]\n wire [19:0] io_in_b_0 = io_in_b;\t// @[PE.scala:31:7]\n wire [19:0] io_in_d_0 = io_in_d;\t// @[PE.scala:31:7]\n wire io_in_control_dataflow_0 = io_in_control_dataflow;\t// @[PE.scala:31:7]\n wire io_in_control_propagate_0 = io_in_control_propagate;\t// @[PE.scala:31:7]\n wire [4:0] io_in_control_shift_0 = io_in_control_shift;\t// @[PE.scala:31:7]\n wire [2:0] io_in_id_0 = io_in_id;\t// @[PE.scala:31:7]\n wire io_in_last_0 = io_in_last;\t// @[PE.scala:31:7]\n wire io_in_valid_0 = io_in_valid;\t// @[PE.scala:31:7]\n wire io_bad_dataflow = 1'h0;\t// @[PE.scala:31:7]\n wire _io_out_c_T_5 = 1'h0;\t// @[Arithmetic.scala:125:33]\n wire _io_out_c_T_6 = 1'h0;\t// @[Arithmetic.scala:125:60]\n wire _io_out_c_T_16 = 1'h0;\t// @[Arithmetic.scala:125:33]\n wire _io_out_c_T_17 = 1'h0;\t// @[Arithmetic.scala:125:60]\n wire [7:0] io_out_a_0 = io_in_a_0;\t// @[PE.scala:31:7]\n wire [19:0] _mac_unit_io_in_b_T = io_in_b_0;\t// @[PE.scala:31:7, :106:37]\n wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0;\t// @[PE.scala:31:7, :113:37]\n wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0;\t// @[PE.scala:31:7, :137:35]\n wire io_out_control_dataflow_0 = io_in_control_dataflow_0;\t// @[PE.scala:31:7]\n wire io_out_control_propagate_0 = io_in_control_propagate_0;\t// @[PE.scala:31:7]\n wire [4:0] io_out_control_shift_0 = io_in_control_shift_0;\t// @[PE.scala:31:7]\n wire [2:0] io_out_id_0 = io_in_id_0;\t// @[PE.scala:31:7]\n wire io_out_last_0 = io_in_last_0;\t// @[PE.scala:31:7]\n wire io_out_valid_0 = io_in_valid_0;\t// @[PE.scala:31:7]\n wire [19:0] io_out_b_0;\t// @[PE.scala:31:7]\n wire [19:0] io_out_c_0;\t// @[PE.scala:31:7]\n reg [7:0] c1;\t// @[PE.scala:70:15]\n wire [7:0] _io_out_c_zeros_T_1 = c1;\t// @[PE.scala:70:15]\n wire [7:0] _mac_unit_io_in_b_T_6 = c1;\t// @[PE.scala:70:15, :127:38]\n reg [7:0] c2;\t// @[PE.scala:71:15]\n wire [7:0] _io_out_c_zeros_T_10 = c2;\t// @[PE.scala:71:15]\n wire [7:0] _mac_unit_io_in_b_T_4 = c2;\t// @[PE.scala:71:15, :121:38]\n reg last_s;\t// @[PE.scala:89:25]\n wire flip = last_s != io_in_control_propagate_0;\t// @[PE.scala:31:7, :89:25, :90:21]\n wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0;\t// @[PE.scala:31:7, :90:21, :91:25]\n wire _GEN = shift_offset == 5'h0;\t// @[PE.scala:91:25]\n wire _io_out_c_point_five_T;\t// @[Arithmetic.scala:101:32]\n assign _io_out_c_point_five_T = _GEN;\t// @[Arithmetic.scala:101:32]\n wire _io_out_c_point_five_T_5;\t// @[Arithmetic.scala:101:32]\n assign _io_out_c_point_five_T_5 = _GEN;\t// @[Arithmetic.scala:101:32]\n wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1;\t// @[PE.scala:91:25]\n wire [5:0] _io_out_c_point_five_T_1;\t// @[Arithmetic.scala:101:53]\n assign _io_out_c_point_five_T_1 = _GEN_0;\t// @[Arithmetic.scala:101:53]\n wire [5:0] _io_out_c_zeros_T_2;\t// @[Arithmetic.scala:102:66]\n assign _io_out_c_zeros_T_2 = _GEN_0;\t// @[Arithmetic.scala:101:53, :102:66]\n wire [5:0] _io_out_c_point_five_T_6;\t// @[Arithmetic.scala:101:53]\n assign _io_out_c_point_five_T_6 = _GEN_0;\t// @[Arithmetic.scala:101:53]\n wire [5:0] _io_out_c_zeros_T_11;\t// @[Arithmetic.scala:102:66]\n assign _io_out_c_zeros_T_11 = _GEN_0;\t// @[Arithmetic.scala:101:53, :102:66]\n wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0];\t// @[Arithmetic.scala:101:53]\n wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2);\t// @[PE.scala:70:15]\n wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0];\t// @[Arithmetic.scala:101:50]\n wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4;\t// @[Arithmetic.scala:101:{29,32,50}]\n wire _GEN_1 = shift_offset < 5'h2;\t// @[PE.scala:91:25]\n wire _io_out_c_zeros_T;\t// @[Arithmetic.scala:102:27]\n assign _io_out_c_zeros_T = _GEN_1;\t// @[Arithmetic.scala:102:27]\n wire _io_out_c_zeros_T_9;\t// @[Arithmetic.scala:102:27]\n assign _io_out_c_zeros_T_9 = _GEN_1;\t// @[Arithmetic.scala:102:27]\n wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0];\t// @[Arithmetic.scala:102:66]\n wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3;\t// @[Arithmetic.scala:102:{60,66}]\n wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1;\t// @[Arithmetic.scala:102:{60,81}]\n wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0];\t// @[Arithmetic.scala:102:81]\n wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1};\t// @[Arithmetic.scala:102:{45,52,81}]\n wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7;\t// @[Arithmetic.scala:102:{24,27,52}]\n wire io_out_c_zeros = |_io_out_c_zeros_T_8;\t// @[Arithmetic.scala:102:{24,89}]\n wire [7:0] _GEN_2 = {3'h0, shift_offset};\t// @[PE.scala:91:25]\n wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2);\t// @[PE.scala:70:15]\n wire [7:0] _io_out_c_ones_digit_T;\t// @[Arithmetic.scala:103:30]\n assign _io_out_c_ones_digit_T = _GEN_3;\t// @[Arithmetic.scala:103:30]\n wire [7:0] _io_out_c_T;\t// @[Arithmetic.scala:107:15]\n assign _io_out_c_T = _GEN_3;\t// @[Arithmetic.scala:103:30, :107:15]\n wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0];\t// @[Arithmetic.scala:103:30]\n wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit;\t// @[Arithmetic.scala:102:89, :103:30, :105:38]\n wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T;\t// @[Arithmetic.scala:101:29, :105:{29,38}]\n wire io_out_c_r = _io_out_c_r_T_1;\t// @[Arithmetic.scala:105:{29,53}]\n wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r};\t// @[Arithmetic.scala:105:53, :107:33]\n wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1};\t// @[Arithmetic.scala:107:{15,28,33}]\n wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0];\t// @[Arithmetic.scala:107:28]\n wire [7:0] _io_out_c_T_4 = _io_out_c_T_3;\t// @[Arithmetic.scala:107:28]\n wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4};\t// @[Mux.scala:126:16]\n wire [19:0] _io_out_c_T_8 = _io_out_c_T_7;\t// @[Mux.scala:126:16]\n wire [19:0] _io_out_c_T_9 = _io_out_c_T_8;\t// @[Mux.scala:126:16]\n wire [19:0] _io_out_c_T_10 = _io_out_c_T_9;\t// @[Arithmetic.scala:125:{81,99}]\n wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T;\t// @[PE.scala:106:37]\n wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0];\t// @[PE.scala:106:37]\n wire [7:0] _c1_T = io_in_d_0[7:0];\t// @[PE.scala:31:7]\n wire [7:0] _c2_T = io_in_d_0[7:0];\t// @[PE.scala:31:7]\n wire [7:0] _c1_T_1 = _c1_T;\t// @[Arithmetic.scala:114:{15,33}]\n wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0];\t// @[Arithmetic.scala:101:53]\n wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7);\t// @[PE.scala:71:15]\n wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0];\t// @[Arithmetic.scala:101:50]\n wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9;\t// @[Arithmetic.scala:101:{29,32,50}]\n wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0];\t// @[Arithmetic.scala:102:66]\n wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12;\t// @[Arithmetic.scala:102:{60,66}]\n wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1;\t// @[Arithmetic.scala:102:{60,81}]\n wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0];\t// @[Arithmetic.scala:102:81]\n wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10};\t// @[Arithmetic.scala:102:{45,52,81}]\n wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16;\t// @[Arithmetic.scala:102:{24,27,52}]\n wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17;\t// @[Arithmetic.scala:102:{24,89}]\n wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2);\t// @[PE.scala:71:15]\n wire [7:0] _io_out_c_ones_digit_T_1;\t// @[Arithmetic.scala:103:30]\n assign _io_out_c_ones_digit_T_1 = _GEN_4;\t// @[Arithmetic.scala:103:30]\n wire [7:0] _io_out_c_T_11;\t// @[Arithmetic.scala:107:15]\n assign _io_out_c_T_11 = _GEN_4;\t// @[Arithmetic.scala:103:30, :107:15]\n wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0];\t// @[Arithmetic.scala:103:30]\n wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1;\t// @[Arithmetic.scala:102:89, :103:30, :105:38]\n wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2;\t// @[Arithmetic.scala:101:29, :105:{29,38}]\n wire io_out_c_r_1 = _io_out_c_r_T_3;\t// @[Arithmetic.scala:105:{29,53}]\n wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1};\t// @[Arithmetic.scala:105:53, :107:33]\n wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12};\t// @[Arithmetic.scala:107:{15,28,33}]\n wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0];\t// @[Arithmetic.scala:107:28]\n wire [7:0] _io_out_c_T_15 = _io_out_c_T_14;\t// @[Arithmetic.scala:107:28]\n wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15};\t// @[Mux.scala:126:16]\n wire [19:0] _io_out_c_T_19 = _io_out_c_T_18;\t// @[Mux.scala:126:16]\n wire [19:0] _io_out_c_T_20 = _io_out_c_T_19;\t// @[Mux.scala:126:16]\n wire [19:0] _io_out_c_T_21 = _io_out_c_T_20;\t// @[Arithmetic.scala:125:{81,99}]\n wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2;\t// @[PE.scala:113:37]\n wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0];\t// @[PE.scala:113:37]\n wire [7:0] _c2_T_1 = _c2_T;\t// @[Arithmetic.scala:114:{15,33}]\n wire [7:0] _mac_unit_io_in_b_T_5;\t// @[PE.scala:121:38]\n assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4;\t// @[PE.scala:121:38]\n wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5;\t// @[PE.scala:121:38]\n assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2};\t// @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16]\n wire [7:0] _mac_unit_io_in_b_T_7;\t// @[PE.scala:127:38]\n assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6;\t// @[PE.scala:127:38]\n wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7;\t// @[PE.scala:127:38]\n wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8;\t// @[PE.scala:137:35]\n wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0];\t// @[PE.scala:137:35]\n always @(posedge clock) begin\t// @[PE.scala:31:7]\n if (io_in_valid_0 & io_in_control_propagate_0)\t// @[PE.scala:31:7, :102:95, :141:17, :142:8]\n c1 <= io_in_d_0[7:0];\t// @[PE.scala:31:7, :70:15]\n if (~(~io_in_valid_0 | io_in_control_propagate_0))\t// @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8]\n c2 <= io_in_d_0[7:0];\t// @[PE.scala:31:7, :71:15]\n if (io_in_valid_0)\t// @[PE.scala:31:7]\n last_s <= io_in_control_propagate_0;\t// @[PE.scala:31:7, :89:25]\n always @(posedge)\n MacUnit_240 mac_unit (\t// @[PE.scala:64:24]\n .clock (clock),\n .reset (reset),\n .io_in_a (io_in_a_0),\t// @[PE.scala:31:7]\n .io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3),\t// @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}]\n .io_in_c (io_in_b_0),\t// @[PE.scala:31:7]\n .io_out_d (io_out_b_0)\n );\t// @[PE.scala:64:24]\n assign io_out_a = io_out_a_0;\t// @[PE.scala:31:7]\n assign io_out_b = io_out_b_0;\t// @[PE.scala:31:7]\n assign io_out_c = io_out_c_0;\t// @[PE.scala:31:7]\n assign io_out_control_dataflow = io_out_control_dataflow_0;\t// @[PE.scala:31:7]\n assign io_out_control_propagate = io_out_control_propagate_0;\t// @[PE.scala:31:7]\n assign io_out_control_shift = io_out_control_shift_0;\t// @[PE.scala:31:7]\n assign io_out_id = io_out_id_0;\t// @[PE.scala:31:7]\n assign io_out_last = io_out_last_0;\t// @[PE.scala:31:7]\n assign io_out_valid = io_out_valid_0;\t// @[PE.scala:31:7]\nendmodule"}}},{"rowIdx":571,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to the following Chisel files.\nFile Monitor.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.tilelink\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.experimental.SourceLine\n\nimport org.chipsalliance.cde.config._\nimport org.chipsalliance.diplomacy._\n\nimport freechips.rocketchip.diplomacy.EnableMonitors\nimport freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}\nimport freechips.rocketchip.util.PlusArg\n\ncase class TLMonitorArgs(edge: TLEdge)\n\nabstract class TLMonitorBase(args: TLMonitorArgs) extends Module\n{\n val io = IO(new Bundle {\n val in = Input(new TLBundle(args.edge.bundle))\n })\n\n def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit\n legalize(io.in, args.edge, reset)\n}\n\nobject TLMonitor {\n def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {\n if (enable) {\n EnableMonitors { implicit p => node := TLEphemeralNode()(ValName(\"monitor\")) }\n } else { node }\n }\n}\n\nclass TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)\n{\n require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))\n\n val cover_prop_class = PropertyClass.Default\n\n //Like assert but can flip to being an assumption for formal verification\n def monAssert(cond: Bool, message: String): Unit =\n if (monitorDir == MonitorDirection.Monitor) {\n assert(cond, message)\n } else {\n Property(monitorDir, cond, message, PropertyClass.Default)\n }\n\n def assume(cond: Bool, message: String): Unit =\n if (monitorDir == MonitorDirection.Monitor) {\n assert(cond, message)\n } else {\n Property(monitorDir.flip, cond, message, PropertyClass.Default)\n }\n\n def extra = {\n args.edge.sourceInfo match {\n case SourceLine(filename, line, col) => s\" (connected at $filename:$line:$col)\"\n case _ => \"\"\n }\n }\n\n def visible(address: UInt, source: UInt, edge: TLEdge) =\n edge.client.clients.map { c =>\n !c.sourceId.contains(source) ||\n c.visibility.map(_.contains(address)).reduce(_ || _)\n }.reduce(_ && _)\n\n def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {\n //switch this flag to turn on diplomacy in error messages\n def diplomacyInfo = if (true) \"\" else \"\\nThe diplomacy information for the edge is as follows:\\n\" + edge.formatEdge + \"\\n\"\n monAssert (TLMessages.isA(bundle.opcode), \"'A' channel has invalid opcode\" + extra)\n\n // Reuse these subexpressions to save some firrtl lines\n val source_ok = edge.client.contains(bundle.source)\n val is_aligned = edge.isAligned(bundle.address, bundle.size)\n val mask = edge.full_mask(bundle)\n\n monAssert (visible(edge.address(bundle), bundle.source, edge), \"'A' channel carries an address illegal for the specified bank visibility\")\n\n //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B\n //TODO: check for acquireT?\n when (bundle.opcode === TLMessages.AcquireBlock) {\n monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters\" + diplomacyInfo + extra)\n monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock from a client which does not support Probe\" + diplomacyInfo + extra)\n monAssert (source_ok, \"'A' channel AcquireBlock carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'A' channel AcquireBlock smaller than a beat\" + extra)\n monAssert (is_aligned, \"'A' channel AcquireBlock address not aligned to size\" + extra)\n monAssert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquireBlock carries invalid grow param\" + extra)\n monAssert (~bundle.mask === 0.U, \"'A' channel AcquireBlock contains invalid mask\" + extra)\n monAssert (!bundle.corrupt, \"'A' channel AcquireBlock is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.AcquirePerm) {\n monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters\" + diplomacyInfo + extra)\n monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm from a client which does not support Probe\" + diplomacyInfo + extra)\n monAssert (source_ok, \"'A' channel AcquirePerm carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'A' channel AcquirePerm smaller than a beat\" + extra)\n monAssert (is_aligned, \"'A' channel AcquirePerm address not aligned to size\" + extra)\n monAssert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquirePerm carries invalid grow param\" + extra)\n monAssert (bundle.param =/= TLPermissions.NtoB, \"'A' channel AcquirePerm requests NtoB\" + extra)\n monAssert (~bundle.mask === 0.U, \"'A' channel AcquirePerm contains invalid mask\" + extra)\n monAssert (!bundle.corrupt, \"'A' channel AcquirePerm is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.Get) {\n monAssert (edge.master.emitsGet(bundle.source, bundle.size), \"'A' channel carries Get type which master claims it can't emit\" + diplomacyInfo + extra)\n monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), \"'A' channel carries Get type which slave claims it can't support\" + diplomacyInfo + extra)\n monAssert (source_ok, \"'A' channel Get carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'A' channel Get carries invalid param\" + extra)\n monAssert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n monAssert (!bundle.corrupt, \"'A' channel Get is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.PutFullData) {\n monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type which is unexpected using diplomatic parameters\" + diplomacyInfo + extra)\n monAssert (source_ok, \"'A' channel PutFull carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'A' channel PutFull carries invalid param\" + extra)\n monAssert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.PutPartialData) {\n monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type which is unexpected using diplomatic parameters\" + extra)\n monAssert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'A' channel PutPartial carries invalid param\" + extra)\n monAssert ((bundle.mask & ~mask) === 0.U, \"'A' channel PutPartial contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.ArithmeticData) {\n monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type which is unexpected using diplomatic parameters\" + extra)\n monAssert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n monAssert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n monAssert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.LogicalData) {\n monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type which is unexpected using diplomatic parameters\" + extra)\n monAssert (source_ok, \"'A' channel Logical carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n monAssert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n monAssert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.Hint) {\n monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type which is unexpected using diplomatic parameters\" + extra)\n monAssert (source_ok, \"'A' channel Hint carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n monAssert (TLHints.isHints(bundle.param), \"'A' channel Hint carries invalid opcode param\" + extra)\n monAssert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n monAssert (!bundle.corrupt, \"'A' channel Hint is corrupt\" + extra)\n }\n }\n\n def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {\n monAssert (TLMessages.isB(bundle.opcode), \"'B' channel has invalid opcode\" + extra)\n\n monAssert (visible(edge.address(bundle), bundle.source, edge), \"'B' channel carries an address illegal for the specified bank visibility\")\n\n // Reuse these subexpressions to save some firrtl lines\n val address_ok = edge.manager.containsSafe(edge.address(bundle))\n val is_aligned = edge.isAligned(bundle.address, bundle.size)\n val mask = edge.full_mask(bundle)\n val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source\n\n when (bundle.opcode === TLMessages.Probe) {\n assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), \"'B' channel carries Probe type which is unexpected using diplomatic parameters\" + extra)\n assume (address_ok, \"'B' channel Probe carries unmanaged address\" + extra)\n assume (legal_source, \"'B' channel Probe carries source that is not first source\" + extra)\n assume (is_aligned, \"'B' channel Probe address not aligned to size\" + extra)\n assume (TLPermissions.isCap(bundle.param), \"'B' channel Probe carries invalid cap param\" + extra)\n assume (bundle.mask === mask, \"'B' channel Probe contains invalid mask\" + extra)\n assume (!bundle.corrupt, \"'B' channel Probe is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.Get) {\n monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), \"'B' channel carries Get type which is unexpected using diplomatic parameters\" + extra)\n monAssert (address_ok, \"'B' channel Get carries unmanaged address\" + extra)\n monAssert (legal_source, \"'B' channel Get carries source that is not first source\" + extra)\n monAssert (is_aligned, \"'B' channel Get address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'B' channel Get carries invalid param\" + extra)\n monAssert (bundle.mask === mask, \"'B' channel Get contains invalid mask\" + extra)\n monAssert (!bundle.corrupt, \"'B' channel Get is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.PutFullData) {\n monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), \"'B' channel carries PutFull type which is unexpected using diplomatic parameters\" + extra)\n monAssert (address_ok, \"'B' channel PutFull carries unmanaged address\" + extra)\n monAssert (legal_source, \"'B' channel PutFull carries source that is not first source\" + extra)\n monAssert (is_aligned, \"'B' channel PutFull address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'B' channel PutFull carries invalid param\" + extra)\n monAssert (bundle.mask === mask, \"'B' channel PutFull contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.PutPartialData) {\n monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), \"'B' channel carries PutPartial type which is unexpected using diplomatic parameters\" + extra)\n monAssert (address_ok, \"'B' channel PutPartial carries unmanaged address\" + extra)\n monAssert (legal_source, \"'B' channel PutPartial carries source that is not first source\" + extra)\n monAssert (is_aligned, \"'B' channel PutPartial address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'B' channel PutPartial carries invalid param\" + extra)\n monAssert ((bundle.mask & ~mask) === 0.U, \"'B' channel PutPartial contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.ArithmeticData) {\n monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), \"'B' channel carries Arithmetic type unsupported by master\" + extra)\n monAssert (address_ok, \"'B' channel Arithmetic carries unmanaged address\" + extra)\n monAssert (legal_source, \"'B' channel Arithmetic carries source that is not first source\" + extra)\n monAssert (is_aligned, \"'B' channel Arithmetic address not aligned to size\" + extra)\n monAssert (TLAtomics.isArithmetic(bundle.param), \"'B' channel Arithmetic carries invalid opcode param\" + extra)\n monAssert (bundle.mask === mask, \"'B' channel Arithmetic contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.LogicalData) {\n monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), \"'B' channel carries Logical type unsupported by client\" + extra)\n monAssert (address_ok, \"'B' channel Logical carries unmanaged address\" + extra)\n monAssert (legal_source, \"'B' channel Logical carries source that is not first source\" + extra)\n monAssert (is_aligned, \"'B' channel Logical address not aligned to size\" + extra)\n monAssert (TLAtomics.isLogical(bundle.param), \"'B' channel Logical carries invalid opcode param\" + extra)\n monAssert (bundle.mask === mask, \"'B' channel Logical contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.Hint) {\n monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), \"'B' channel carries Hint type unsupported by client\" + extra)\n monAssert (address_ok, \"'B' channel Hint carries unmanaged address\" + extra)\n monAssert (legal_source, \"'B' channel Hint carries source that is not first source\" + extra)\n monAssert (is_aligned, \"'B' channel Hint address not aligned to size\" + extra)\n monAssert (bundle.mask === mask, \"'B' channel Hint contains invalid mask\" + extra)\n monAssert (!bundle.corrupt, \"'B' channel Hint is corrupt\" + extra)\n }\n }\n\n def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {\n monAssert (TLMessages.isC(bundle.opcode), \"'C' channel has invalid opcode\" + extra)\n\n val source_ok = edge.client.contains(bundle.source)\n val is_aligned = edge.isAligned(bundle.address, bundle.size)\n val address_ok = edge.manager.containsSafe(edge.address(bundle))\n\n monAssert (visible(edge.address(bundle), bundle.source, edge), \"'C' channel carries an address illegal for the specified bank visibility\")\n\n when (bundle.opcode === TLMessages.ProbeAck) {\n monAssert (address_ok, \"'C' channel ProbeAck carries unmanaged address\" + extra)\n monAssert (source_ok, \"'C' channel ProbeAck carries invalid source ID\" + extra)\n monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'C' channel ProbeAck smaller than a beat\" + extra)\n monAssert (is_aligned, \"'C' channel ProbeAck address not aligned to size\" + extra)\n monAssert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAck carries invalid report param\" + extra)\n monAssert (!bundle.corrupt, \"'C' channel ProbeAck is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.ProbeAckData) {\n monAssert (address_ok, \"'C' channel ProbeAckData carries unmanaged address\" + extra)\n monAssert (source_ok, \"'C' channel ProbeAckData carries invalid source ID\" + extra)\n monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'C' channel ProbeAckData smaller than a beat\" + extra)\n monAssert (is_aligned, \"'C' channel ProbeAckData address not aligned to size\" + extra)\n monAssert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAckData carries invalid report param\" + extra)\n }\n\n when (bundle.opcode === TLMessages.Release) {\n monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries Release type unsupported by manager\" + extra)\n monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), \"'C' channel carries Release from a client which does not support Probe\" + extra)\n monAssert (source_ok, \"'C' channel Release carries invalid source ID\" + extra)\n monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'C' channel Release smaller than a beat\" + extra)\n monAssert (is_aligned, \"'C' channel Release address not aligned to size\" + extra)\n monAssert (TLPermissions.isReport(bundle.param), \"'C' channel Release carries invalid report param\" + extra)\n monAssert (!bundle.corrupt, \"'C' channel Release is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.ReleaseData) {\n monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries ReleaseData type unsupported by manager\" + extra)\n monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), \"'C' channel carries Release from a client which does not support Probe\" + extra)\n monAssert (source_ok, \"'C' channel ReleaseData carries invalid source ID\" + extra)\n monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'C' channel ReleaseData smaller than a beat\" + extra)\n monAssert (is_aligned, \"'C' channel ReleaseData address not aligned to size\" + extra)\n monAssert (TLPermissions.isReport(bundle.param), \"'C' channel ReleaseData carries invalid report param\" + extra)\n }\n\n when (bundle.opcode === TLMessages.AccessAck) {\n monAssert (address_ok, \"'C' channel AccessAck carries unmanaged address\" + extra)\n monAssert (source_ok, \"'C' channel AccessAck carries invalid source ID\" + extra)\n monAssert (is_aligned, \"'C' channel AccessAck address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'C' channel AccessAck carries invalid param\" + extra)\n monAssert (!bundle.corrupt, \"'C' channel AccessAck is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.AccessAckData) {\n monAssert (address_ok, \"'C' channel AccessAckData carries unmanaged address\" + extra)\n monAssert (source_ok, \"'C' channel AccessAckData carries invalid source ID\" + extra)\n monAssert (is_aligned, \"'C' channel AccessAckData address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'C' channel AccessAckData carries invalid param\" + extra)\n }\n\n when (bundle.opcode === TLMessages.HintAck) {\n monAssert (address_ok, \"'C' channel HintAck carries unmanaged address\" + extra)\n monAssert (source_ok, \"'C' channel HintAck carries invalid source ID\" + extra)\n monAssert (is_aligned, \"'C' channel HintAck address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'C' channel HintAck carries invalid param\" + extra)\n monAssert (!bundle.corrupt, \"'C' channel HintAck is corrupt\" + extra)\n }\n }\n\n def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {\n assume (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n\n val source_ok = edge.client.contains(bundle.source)\n val sink_ok = bundle.sink < edge.manager.endSinkId.U\n val deny_put_ok = edge.manager.mayDenyPut.B\n val deny_get_ok = edge.manager.mayDenyGet.B\n\n when (bundle.opcode === TLMessages.ReleaseAck) {\n assume (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'D' channel ReleaseAck smaller than a beat\" + extra)\n assume (bundle.param === 0.U, \"'D' channel ReleaseeAck carries invalid param\" + extra)\n assume (!bundle.corrupt, \"'D' channel ReleaseAck is corrupt\" + extra)\n assume (!bundle.denied, \"'D' channel ReleaseAck is denied\" + extra)\n }\n\n when (bundle.opcode === TLMessages.Grant) {\n assume (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n assume (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'D' channel Grant smaller than a beat\" + extra)\n assume (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n assume (bundle.param =/= TLPermissions.toN, \"'D' channel Grant carries toN param\" + extra)\n assume (!bundle.corrupt, \"'D' channel Grant is corrupt\" + extra)\n assume (deny_put_ok || !bundle.denied, \"'D' channel Grant is denied\" + extra)\n }\n\n when (bundle.opcode === TLMessages.GrantData) {\n assume (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n assume (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'D' channel GrantData smaller than a beat\" + extra)\n assume (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n assume (bundle.param =/= TLPermissions.toN, \"'D' channel GrantData carries toN param\" + extra)\n assume (!bundle.denied || bundle.corrupt, \"'D' channel GrantData is denied but not corrupt\" + extra)\n assume (deny_get_ok || !bundle.denied, \"'D' channel GrantData is denied\" + extra)\n }\n\n when (bundle.opcode === TLMessages.AccessAck) {\n assume (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n // size is ignored\n assume (bundle.param === 0.U, \"'D' channel AccessAck carries invalid param\" + extra)\n assume (!bundle.corrupt, \"'D' channel AccessAck is corrupt\" + extra)\n assume (deny_put_ok || !bundle.denied, \"'D' channel AccessAck is denied\" + extra)\n }\n\n when (bundle.opcode === TLMessages.AccessAckData) {\n assume (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n // size is ignored\n assume (bundle.param === 0.U, \"'D' channel AccessAckData carries invalid param\" + extra)\n assume (!bundle.denied || bundle.corrupt, \"'D' channel AccessAckData is denied but not corrupt\" + extra)\n assume (deny_get_ok || !bundle.denied, \"'D' channel AccessAckData is denied\" + extra)\n }\n\n when (bundle.opcode === TLMessages.HintAck) {\n assume (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n // size is ignored\n assume (bundle.param === 0.U, \"'D' channel HintAck carries invalid param\" + extra)\n assume (!bundle.corrupt, \"'D' channel HintAck is corrupt\" + extra)\n assume (deny_put_ok || !bundle.denied, \"'D' channel HintAck is denied\" + extra)\n }\n }\n\n def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {\n val sink_ok = bundle.sink < edge.manager.endSinkId.U\n monAssert (sink_ok, \"'E' channels carries invalid sink ID\" + extra)\n }\n\n def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {\n when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }\n when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }\n if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {\n when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }\n when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }\n when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }\n } else {\n monAssert (!bundle.b.valid, \"'B' channel valid and not TL-C\" + extra)\n monAssert (!bundle.c.valid, \"'C' channel valid and not TL-C\" + extra)\n monAssert (!bundle.e.valid, \"'E' channel valid and not TL-C\" + extra)\n }\n }\n\n def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {\n val a_first = edge.first(a.bits, a.fire)\n val opcode = Reg(UInt())\n val param = Reg(UInt())\n val size = Reg(UInt())\n val source = Reg(UInt())\n val address = Reg(UInt())\n when (a.valid && !a_first) {\n monAssert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n monAssert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n monAssert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n monAssert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n monAssert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n }\n when (a.fire && a_first) {\n opcode := a.bits.opcode\n param := a.bits.param\n size := a.bits.size\n source := a.bits.source\n address := a.bits.address\n }\n }\n\n def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {\n val b_first = edge.first(b.bits, b.fire)\n val opcode = Reg(UInt())\n val param = Reg(UInt())\n val size = Reg(UInt())\n val source = Reg(UInt())\n val address = Reg(UInt())\n when (b.valid && !b_first) {\n monAssert (b.bits.opcode === opcode, \"'B' channel opcode changed within multibeat operation\" + extra)\n monAssert (b.bits.param === param, \"'B' channel param changed within multibeat operation\" + extra)\n monAssert (b.bits.size === size, \"'B' channel size changed within multibeat operation\" + extra)\n monAssert (b.bits.source === source, \"'B' channel source changed within multibeat operation\" + extra)\n monAssert (b.bits.address=== address,\"'B' channel addresss changed with multibeat operation\" + extra)\n }\n when (b.fire && b_first) {\n opcode := b.bits.opcode\n param := b.bits.param\n size := b.bits.size\n source := b.bits.source\n address := b.bits.address\n }\n }\n\n def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {\n // Symbolic variable\n val sym_source = Wire(UInt(edge.client.endSourceId.W))\n // TODO: Connect sym_source to a fixed value for simulation and to a\n // free wire in formal\n sym_source := 0.U\n\n // Type casting Int to UInt\n val maxSourceId = Wire(UInt(edge.client.endSourceId.W))\n maxSourceId := edge.client.endSourceId.U\n\n // Delayed verison of sym_source\n val sym_source_d = Reg(UInt(edge.client.endSourceId.W))\n sym_source_d := sym_source\n\n // These will be constraints for FV setup\n Property(\n MonitorDirection.Monitor,\n (sym_source === sym_source_d),\n \"sym_source should remain stable\",\n PropertyClass.Default)\n Property(\n MonitorDirection.Monitor,\n (sym_source <= maxSourceId),\n \"sym_source should take legal value\",\n PropertyClass.Default)\n\n val my_resp_pend = RegInit(false.B)\n val my_opcode = Reg(UInt())\n val my_size = Reg(UInt())\n\n val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)\n val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)\n\n val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)\n val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)\n\n val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)\n val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)\n when (my_set_resp_pend) {\n my_resp_pend := true.B\n } .elsewhen (my_clr_resp_pend) {\n my_resp_pend := false.B\n }\n\n when (my_a_first_beat) {\n my_opcode := bundle.a.bits.opcode\n my_size := bundle.a.bits.size\n }\n\n val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)\n val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)\n\n val my_resp_opcode_legal = Wire(Bool())\n when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||\n (my_resp_opcode === TLMessages.LogicalData)) {\n my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)\n } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {\n my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)\n } .otherwise {\n my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)\n }\n\n monAssert (IfThen(my_resp_pend, !my_a_first_beat),\n \"Request message should not be sent with a source ID, for which a response message\" +\n \"is already pending (not received until current cycle) for a prior request message\" +\n \"with the same source ID\" + extra)\n\n assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),\n \"Response message should be accepted with a source ID only if a request message with the\" +\n \"same source ID has been accepted or is being accepted in the current cycle\" + extra)\n assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),\n \"Response message should be sent with a source ID only if a request message with the\" +\n \"same source ID has been accepted or is being sent in the current cycle\" + extra)\n assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),\n \"If d_valid is 1, then d_size should be same as a_size of the corresponding request\" +\n \"message\" + extra)\n assume (IfThen(my_d_first_beat, my_resp_opcode_legal),\n \"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding\" +\n \"request message\" + extra)\n }\n\n def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {\n val c_first = edge.first(c.bits, c.fire)\n val opcode = Reg(UInt())\n val param = Reg(UInt())\n val size = Reg(UInt())\n val source = Reg(UInt())\n val address = Reg(UInt())\n when (c.valid && !c_first) {\n monAssert (c.bits.opcode === opcode, \"'C' channel opcode changed within multibeat operation\" + extra)\n monAssert (c.bits.param === param, \"'C' channel param changed within multibeat operation\" + extra)\n monAssert (c.bits.size === size, \"'C' channel size changed within multibeat operation\" + extra)\n monAssert (c.bits.source === source, \"'C' channel source changed within multibeat operation\" + extra)\n monAssert (c.bits.address=== address,\"'C' channel address changed with multibeat operation\" + extra)\n }\n when (c.fire && c_first) {\n opcode := c.bits.opcode\n param := c.bits.param\n size := c.bits.size\n source := c.bits.source\n address := c.bits.address\n }\n }\n\n def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {\n val d_first = edge.first(d.bits, d.fire)\n val opcode = Reg(UInt())\n val param = Reg(UInt())\n val size = Reg(UInt())\n val source = Reg(UInt())\n val sink = Reg(UInt())\n val denied = Reg(Bool())\n when (d.valid && !d_first) {\n assume (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n assume (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n assume (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n assume (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n assume (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n assume (d.bits.denied === denied, \"'D' channel denied changed with multibeat operation\" + extra)\n }\n when (d.fire && d_first) {\n opcode := d.bits.opcode\n param := d.bits.param\n size := d.bits.size\n source := d.bits.source\n sink := d.bits.sink\n denied := d.bits.denied\n }\n }\n\n def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {\n legalizeMultibeatA(bundle.a, edge)\n legalizeMultibeatD(bundle.d, edge)\n if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {\n legalizeMultibeatB(bundle.b, edge)\n legalizeMultibeatC(bundle.c, edge)\n }\n }\n\n //This is left in for almond which doesn't adhere to the tilelink protocol\n @deprecated(\"Use legalizeADSource instead if possible\",\"\")\n def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {\n val inflight = RegInit(0.U(edge.client.endSourceId.W))\n\n val a_first = edge.first(bundle.a.bits, bundle.a.fire)\n val d_first = edge.first(bundle.d.bits, bundle.d.fire)\n\n val a_set = WireInit(0.U(edge.client.endSourceId.W))\n when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {\n a_set := UIntToOH(bundle.a.bits.source)\n assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n }\n\n val d_clr = WireInit(0.U(edge.client.endSourceId.W))\n val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck\n when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {\n d_clr := UIntToOH(bundle.d.bits.source)\n assume((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n }\n\n if (edge.manager.minLatency > 0) {\n assume(a_set =/= d_clr || !a_set.orR, s\"'A' and 'D' concurrent, despite minlatency > 0\" + extra)\n }\n\n inflight := (inflight | a_set) & ~d_clr\n\n val watchdog = RegInit(0.U(32.W))\n val limit = PlusArg(\"tilelink_timeout\",\n docstring=\"Kill emulation after INT waiting TileLink cycles. Off if 0.\")\n assert (!inflight.orR || limit === 0.U || watchdog < limit, \"TileLink timeout expired\" + extra)\n\n watchdog := watchdog + 1.U\n when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }\n }\n\n def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {\n val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)\n val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything\n val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)\n val log_a_size_bus_size = log2Ceil(a_size_bus_size)\n def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits\n\n val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error\n inflight.suggestName(\"inflight\")\n val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))\n inflight_opcodes.suggestName(\"inflight_opcodes\")\n val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))\n inflight_sizes.suggestName(\"inflight_sizes\")\n\n val a_first = edge.first(bundle.a.bits, bundle.a.fire)\n a_first.suggestName(\"a_first\")\n val d_first = edge.first(bundle.d.bits, bundle.d.fire)\n d_first.suggestName(\"d_first\")\n\n val a_set = WireInit(0.U(edge.client.endSourceId.W))\n val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))\n a_set.suggestName(\"a_set\")\n a_set_wo_ready.suggestName(\"a_set_wo_ready\")\n val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))\n a_opcodes_set.suggestName(\"a_opcodes_set\")\n val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))\n a_sizes_set.suggestName(\"a_sizes_set\")\n\n val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))\n a_opcode_lookup.suggestName(\"a_opcode_lookup\")\n a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U\n\n val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))\n a_size_lookup.suggestName(\"a_size_lookup\")\n a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U\n\n val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))\n val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))\n\n val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))\n a_opcodes_set_interm.suggestName(\"a_opcodes_set_interm\")\n val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))\n a_sizes_set_interm.suggestName(\"a_sizes_set_interm\")\n\n when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {\n a_set_wo_ready := UIntToOH(bundle.a.bits.source)\n }\n\n when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {\n a_set := UIntToOH(bundle.a.bits.source)\n a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U\n a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U\n a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)\n a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)\n monAssert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n }\n\n val d_clr = WireInit(0.U(edge.client.endSourceId.W))\n val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))\n d_clr.suggestName(\"d_clr\")\n d_clr_wo_ready.suggestName(\"d_clr_wo_ready\")\n val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))\n d_opcodes_clr.suggestName(\"d_opcodes_clr\")\n val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))\n d_sizes_clr.suggestName(\"d_sizes_clr\")\n\n val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck\n when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {\n d_clr_wo_ready := UIntToOH(bundle.d.bits.source)\n }\n\n when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {\n d_clr := UIntToOH(bundle.d.bits.source)\n d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)\n d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)\n }\n when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {\n val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)\n assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, \"'D' channel acknowledged for nothing inflight\" + extra)\n\n when (same_cycle_resp) {\n assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||\n (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), \"'D' channel contains improper opcode response\" + extra)\n assume((bundle.a.bits.size === bundle.d.bits.size), \"'D' channel contains improper response size\" + extra)\n } .otherwise {\n assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||\n (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), \"'D' channel contains improper opcode response\" + extra)\n assume((bundle.d.bits.size === a_size_lookup), \"'D' channel contains improper response size\" + extra)\n }\n }\n when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {\n assume((!bundle.d.ready) || bundle.a.ready, \"ready check\")\n }\n\n if (edge.manager.minLatency > 0) {\n assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s\"'A' and 'D' concurrent, despite minlatency > 0\" + extra)\n }\n\n inflight := (inflight | a_set) & ~d_clr\n inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr\n inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr\n\n val watchdog = RegInit(0.U(32.W))\n val limit = PlusArg(\"tilelink_timeout\",\n docstring=\"Kill emulation after INT waiting TileLink cycles. Off if 0.\")\n monAssert (!inflight.orR || limit === 0.U || watchdog < limit, \"TileLink timeout expired\" + extra)\n\n watchdog := watchdog + 1.U\n when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }\n }\n\n def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {\n val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)\n val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything\n\n val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)\n val log_c_size_bus_size = log2Ceil(c_size_bus_size)\n def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits\n\n val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))\n val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))\n val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))\n inflight.suggestName(\"inflight\")\n inflight_opcodes.suggestName(\"inflight_opcodes\")\n inflight_sizes.suggestName(\"inflight_sizes\")\n\n val c_first = edge.first(bundle.c.bits, bundle.c.fire)\n val d_first = edge.first(bundle.d.bits, bundle.d.fire)\n c_first.suggestName(\"c_first\")\n d_first.suggestName(\"d_first\")\n\n val c_set = WireInit(0.U(edge.client.endSourceId.W))\n val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))\n val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))\n val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))\n c_set.suggestName(\"c_set\")\n c_set_wo_ready.suggestName(\"c_set_wo_ready\")\n c_opcodes_set.suggestName(\"c_opcodes_set\")\n c_sizes_set.suggestName(\"c_sizes_set\")\n\n val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))\n val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))\n c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U\n c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U\n c_opcode_lookup.suggestName(\"c_opcode_lookup\")\n c_size_lookup.suggestName(\"c_size_lookup\")\n\n val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))\n val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))\n c_opcodes_set_interm.suggestName(\"c_opcodes_set_interm\")\n c_sizes_set_interm.suggestName(\"c_sizes_set_interm\")\n\n when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {\n c_set_wo_ready := UIntToOH(bundle.c.bits.source)\n }\n\n when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {\n c_set := UIntToOH(bundle.c.bits.source)\n c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U\n c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U\n c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)\n c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)\n monAssert(!inflight(bundle.c.bits.source), \"'C' channel re-used a source ID\" + extra)\n }\n\n val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData\n\n val d_clr = WireInit(0.U(edge.client.endSourceId.W))\n val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))\n val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))\n val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))\n d_clr.suggestName(\"d_clr\")\n d_clr_wo_ready.suggestName(\"d_clr_wo_ready\")\n d_opcodes_clr.suggestName(\"d_opcodes_clr\")\n d_sizes_clr.suggestName(\"d_sizes_clr\")\n\n val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck\n when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {\n d_clr_wo_ready := UIntToOH(bundle.d.bits.source)\n }\n\n when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {\n d_clr := UIntToOH(bundle.d.bits.source)\n d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)\n d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)\n }\n\n when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {\n val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)\n assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, \"'D' channel acknowledged for nothing inflight\" + extra)\n when (same_cycle_resp) {\n assume((bundle.d.bits.size === bundle.c.bits.size), \"'D' channel contains improper response size\" + extra)\n } .otherwise {\n assume((bundle.d.bits.size === c_size_lookup), \"'D' channel contains improper response size\" + extra)\n }\n }\n\n when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {\n assume((!bundle.d.ready) || bundle.c.ready, \"ready check\")\n }\n\n if (edge.manager.minLatency > 0) {\n when (c_set_wo_ready.orR) {\n assume(c_set_wo_ready =/= d_clr_wo_ready, s\"'C' and 'D' concurrent, despite minlatency > 0\" + extra)\n }\n }\n\n inflight := (inflight | c_set) & ~d_clr\n inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr\n inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr\n\n val watchdog = RegInit(0.U(32.W))\n val limit = PlusArg(\"tilelink_timeout\",\n docstring=\"Kill emulation after INT waiting TileLink cycles. Off if 0.\")\n monAssert (!inflight.orR || limit === 0.U || watchdog < limit, \"TileLink timeout expired\" + extra)\n\n watchdog := watchdog + 1.U\n when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }\n }\n\n def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {\n val inflight = RegInit(0.U(edge.manager.endSinkId.W))\n\n val d_first = edge.first(bundle.d.bits, bundle.d.fire)\n val e_first = true.B\n\n val d_set = WireInit(0.U(edge.manager.endSinkId.W))\n when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {\n d_set := UIntToOH(bundle.d.bits.sink)\n assume(!inflight(bundle.d.bits.sink), \"'D' channel re-used a sink ID\" + extra)\n }\n\n val e_clr = WireInit(0.U(edge.manager.endSinkId.W))\n when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {\n e_clr := UIntToOH(bundle.e.bits.sink)\n monAssert((d_set | inflight)(bundle.e.bits.sink), \"'E' channel acknowledged for nothing inflight\" + extra)\n }\n\n // edge.client.minLatency applies to BC, not DE\n\n inflight := (inflight | d_set) & ~e_clr\n }\n\n def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {\n val sourceBits = log2Ceil(edge.client.endSourceId)\n val tooBig = 14 // >16kB worth of flight information gets to be too much\n if (sourceBits > tooBig) {\n println(s\"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked\")\n } else {\n if (args.edge.params(TestplanTestType).simulation) {\n if (args.edge.params(TLMonitorStrictMode)) {\n legalizeADSource(bundle, edge)\n legalizeCDSource(bundle, edge)\n } else {\n legalizeADSourceOld(bundle, edge)\n }\n }\n if (args.edge.params(TestplanTestType).formal) {\n legalizeADSourceFormal(bundle, edge)\n }\n }\n if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {\n // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...\n val sinkBits = log2Ceil(edge.manager.endSinkId)\n if (sinkBits > tooBig) {\n println(s\"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked\")\n } else {\n legalizeDESink(bundle, edge)\n }\n }\n }\n\n def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {\n legalizeFormat (bundle, edge)\n legalizeMultibeat (bundle, edge)\n legalizeUnique (bundle, edge)\n }\n}\nFile Misc.scala:\n// See LICENSE.Berkeley for license details.\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.util.random.LFSR\nimport org.chipsalliance.cde.config.Parameters\nimport scala.math._\n\nclass ParameterizedBundle(implicit p: Parameters) extends Bundle\n\ntrait Clocked extends Bundle {\n val clock = Clock()\n val reset = Bool() \n}\n\nobject DecoupledHelper {\n def apply(rvs: Bool*) = new DecoupledHelper(rvs)\n}\n\nclass DecoupledHelper(val rvs: Seq[Bool]) {\n def fire(exclude: Bool, includes: Bool*) = {\n require(rvs.contains(exclude), \"Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!\")\n (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)\n }\n def fire() = {\n rvs.reduce(_ && _)\n }\n}\n\nobject MuxT {\n def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =\n (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))\n\n def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =\n (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))\n\n def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =\n (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))\n}\n\n/** Creates a cascade of n MuxTs to search for a key value. */\nobject MuxTLookup {\n def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {\n var res = default\n for ((k, v) <- mapping.reverse)\n res = MuxT(k === key, v, res)\n res\n }\n\n def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {\n var res = default\n for ((k, v) <- mapping.reverse)\n res = MuxT(k === key, v, res)\n res\n }\n}\n\nobject ValidMux {\n def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {\n apply(v1 +: v2.toSeq)\n }\n def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {\n val out = Wire(Valid(valids.head.bits.cloneType))\n out.valid := valids.map(_.valid).reduce(_ || _)\n out.bits := MuxCase(valids.head.bits,\n valids.map(v => (v.valid -> v.bits)))\n out\n }\n}\n\nobject Str\n{\n def apply(s: String): UInt = {\n var i = BigInt(0)\n require(s.forall(validChar _))\n for (c <- s)\n i = (i << 8) | c\n i.U((s.length*8).W)\n }\n def apply(x: Char): UInt = {\n require(validChar(x))\n x.U(8.W)\n }\n def apply(x: UInt): UInt = apply(x, 10)\n def apply(x: UInt, radix: Int): UInt = {\n val rad = radix.U\n val w = x.getWidth\n require(w > 0)\n\n var q = x\n var s = digit(q % rad)\n for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {\n q = q / rad\n s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)\n }\n s\n }\n def apply(x: SInt): UInt = apply(x, 10)\n def apply(x: SInt, radix: Int): UInt = {\n val neg = x < 0.S\n val abs = x.abs.asUInt\n if (radix != 10) {\n Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))\n } else {\n val rad = radix.U\n val w = abs.getWidth\n require(w > 0)\n\n var q = abs\n var s = digit(q % rad)\n var needSign = neg\n for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {\n q = q / rad\n val placeSpace = q === 0.U\n val space = Mux(needSign, Str('-'), Str(' '))\n needSign = needSign && !placeSpace\n s = Cat(Mux(placeSpace, space, digit(q % rad)), s)\n }\n Cat(Mux(needSign, Str('-'), Str(' ')), s)\n }\n }\n\n private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)\n private def validChar(x: Char) = x == (x & 0xFF)\n}\n\nobject Split\n{\n def apply(x: UInt, n0: Int) = {\n val w = x.getWidth\n (x.extract(w-1,n0), x.extract(n0-1,0))\n }\n def apply(x: UInt, n1: Int, n0: Int) = {\n val w = x.getWidth\n (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))\n }\n def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {\n val w = x.getWidth\n (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))\n }\n}\n\nobject Random\n{\n def apply(mod: Int, random: UInt): UInt = {\n if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)\n else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))\n }\n def apply(mod: Int): UInt = apply(mod, randomizer)\n def oneHot(mod: Int, random: UInt): UInt = {\n if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))\n else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt\n }\n def oneHot(mod: Int): UInt = oneHot(mod, randomizer)\n\n private def randomizer = LFSR(16)\n private def partition(value: UInt, slices: Int) =\n Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)\n}\n\nobject Majority {\n def apply(in: Set[Bool]): Bool = {\n val n = (in.size >> 1) + 1\n val clauses = in.subsets(n).map(_.reduce(_ && _))\n clauses.reduce(_ || _)\n }\n\n def apply(in: Seq[Bool]): Bool = apply(in.toSet)\n\n def apply(in: UInt): Bool = apply(in.asBools.toSet)\n}\n\nobject PopCountAtLeast {\n private def two(x: UInt): (Bool, Bool) = x.getWidth match {\n case 1 => (x.asBool, false.B)\n case n =>\n val half = x.getWidth / 2\n val (leftOne, leftTwo) = two(x(half - 1, 0))\n val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))\n (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))\n }\n def apply(x: UInt, n: Int): Bool = n match {\n case 0 => true.B\n case 1 => x.orR\n case 2 => two(x)._2\n case 3 => PopCount(x) >= n.U\n }\n}\n\n// This gets used everywhere, so make the smallest circuit possible ...\n// Given an address and size, create a mask of beatBytes size\n// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111\n// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01\nobject MaskGen {\n def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {\n require (groupBy >= 1 && beatBytes >= groupBy)\n require (isPow2(beatBytes) && isPow2(groupBy))\n val lgBytes = log2Ceil(beatBytes)\n val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U\n\n def helper(i: Int): Seq[(Bool, Bool)] = {\n if (i == 0) {\n Seq((lgSize >= lgBytes.asUInt, true.B))\n } else {\n val sub = helper(i-1)\n val size = sizeOH(lgBytes - i)\n val bit = addr_lo(lgBytes - i)\n val nbit = !bit\n Seq.tabulate (1 << i) { j =>\n val (sub_acc, sub_eq) = sub(j/2)\n val eq = sub_eq && (if (j % 2 == 1) bit else nbit)\n val acc = sub_acc || (size && eq)\n (acc, eq)\n }\n }\n }\n\n if (groupBy == beatBytes) 1.U else\n Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)\n }\n}\nFile PlusArg.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3._\nimport chisel3.experimental._\nimport chisel3.util.HasBlackBoxResource\n\n@deprecated(\"This will be removed in Rocket Chip 2020.08\", \"Rocket Chip 2020.05\")\ncase class PlusArgInfo(default: BigInt, docstring: String)\n\n/** Case class for PlusArg information\n *\n * @tparam A scala type of the PlusArg value\n * @param default optional default value\n * @param docstring text to include in the help\n * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)\n */\nprivate case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)\n\n/** Typeclass for converting a type to a doctype string\n * @tparam A some type\n */\ntrait Doctypeable[A] {\n\n /** Return the doctype string for some option */\n def toDoctype(a: Option[A]): String\n\n}\n\n/** Object containing implementations of the Doctypeable typeclass */\nobject Doctypes {\n\n /** Converts an Int => \"INT\" */\n implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = \"INT\" }\n\n /** Converts a BigInt => \"INT\" */\n implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = \"INT\" }\n\n /** Converts a String => \"STRING\" */\n implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = \"STRING\" }\n\n}\n\nclass plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(\n \"FORMAT\" -> StringParam(format),\n \"DEFAULT\" -> IntParam(default),\n \"WIDTH\" -> IntParam(width)\n )) with HasBlackBoxResource {\n val io = IO(new Bundle {\n val out = Output(UInt(width.W))\n })\n\n addResource(\"/vsrc/plusarg_reader.v\")\n}\n\n/* This wrapper class has no outputs, making it clear it is a simulation-only construct */\nclass PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {\n val io = IO(new Bundle {\n val count = Input(UInt(width.W))\n })\n val max = Module(new plusarg_reader(format, default, docstring, width)).io.out\n when (max > 0.U) {\n assert (io.count < max, s\"Timeout exceeded: $docstring\")\n }\n}\n\nimport Doctypes._\n\nobject PlusArg\n{\n /** PlusArg(\"foo\") will return 42.U if the simulation is run with +foo=42\n * Do not use this as an initial register value. The value is set in an\n * initial block and thus accessing it from another initial is racey.\n * Add a docstring to document the arg, which can be dumped in an elaboration\n * pass.\n */\n def apply(name: String, default: BigInt = 0, docstring: String = \"\", width: Int = 32): UInt = {\n PlusArgArtefacts.append(name, Some(default), docstring)\n Module(new plusarg_reader(name + \"=%d\", default, docstring, width)).io.out\n }\n\n /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert\n * to kill the simulation when count exceeds the specified integer argument.\n * Default 0 will never assert.\n */\n def timeout(name: String, default: BigInt = 0, docstring: String = \"\", width: Int = 32)(count: UInt): Unit = {\n PlusArgArtefacts.append(name, Some(default), docstring)\n Module(new PlusArgTimeout(name + \"=%d\", default, docstring, width)).io.count := count\n }\n}\n\nobject PlusArgArtefacts {\n private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty\n\n /* Add a new PlusArg */\n @deprecated(\n \"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08\",\n \"Rocket Chip 2020.05\"\n )\n def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)\n\n /** Add a new PlusArg\n *\n * @tparam A scala type of the PlusArg value\n * @param name name for the PlusArg\n * @param default optional default value\n * @param docstring text to include in the help\n */\n def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =\n artefacts = artefacts ++\n Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))\n\n /* From plus args, generate help text */\n private def serializeHelp_cHeader(tab: String = \"\"): String = artefacts\n .map{ case(arg, info) =>\n s\"\"\"|$tab+$arg=${info.doctype}\\\\n\\\\\n |$tab${\" \"*20}${info.docstring}\\\\n\\\\\n |\"\"\".stripMargin ++ info.default.map{ case default =>\n s\"$tab${\" \"*22}(default=${default})\\\\n\\\\\\n\"}.getOrElse(\"\")\n }.toSeq.mkString(\"\\\\n\\\\\\n\") ++ \"\\\"\"\n\n /* From plus args, generate a char array of their names */\n private def serializeArray_cHeader(tab: String = \"\"): String = {\n val prettyTab = tab + \" \" * 44 // Length of 'static const ...'\n s\"${tab}static const char * verilog_plusargs [] = {\\\\\\n\" ++\n artefacts\n .map{ case(arg, _) => s\"\"\"$prettyTab\"$arg\",\\\\\\n\"\"\" }\n .mkString(\"\")++\n s\"${prettyTab}0};\"\n }\n\n /* Generate C code to be included in emulator.cc that helps with\n * argument parsing based on available Verilog PlusArgs */\n def serialize_cHeader(): String =\n s\"\"\"|#define PLUSARG_USAGE_OPTIONS \\\"EMULATOR VERILOG PLUSARGS\\\\n\\\\\n |${serializeHelp_cHeader(\" \"*7)}\n |${serializeArray_cHeader()}\n |\"\"\".stripMargin\n}\nFile package.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip\n\nimport chisel3._\nimport chisel3.util._\nimport scala.math.min\nimport scala.collection.{immutable, mutable}\n\npackage object util {\n implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {\n def unzip = (x.map(_._1), x.map(_._2))\n }\n\n implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {\n def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR\n \n def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)\n }\n\n implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {\n\n /** Like Vec.apply(idx), but tolerates indices of mismatched width */\n def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))\n }\n\n implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {\n def apply(idx: UInt): T = {\n if (x.size <= 1) {\n x.head\n } else if (!isPow2(x.size)) {\n // For non-power-of-2 seqs, reflect elements to simplify decoder\n (x ++ x.takeRight(x.size & -x.size)).toSeq(idx)\n } else {\n // Ignore MSBs of idx\n val truncIdx =\n if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx\n else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)\n x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }\n }\n }\n\n def extract(idx: UInt): T = VecInit(x).extract(idx)\n\n def asUInt: UInt = Cat(x.map(_.asUInt).reverse)\n\n def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)\n\n def rotate(n: UInt): Seq[T] = {\n if (x.size <= 1) {\n x\n } else {\n require(isPow2(x.size))\n val amt = n.padTo(log2Ceil(x.size))\n (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })\n }\n }\n\n def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)\n\n def rotateRight(n: UInt): Seq[T] = {\n if (x.size <= 1) {\n x\n } else {\n require(isPow2(x.size))\n val amt = n.padTo(log2Ceil(x.size))\n (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })\n }\n }\n }\n\n // allow bitwise ops on Seq[Bool] just like UInt\n implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {\n def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }\n def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }\n def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }\n def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x\n def >> (n: Int): Seq[Bool] = x drop n\n def unary_~ : Seq[Bool] = x.map(!_)\n def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)\n def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)\n def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)\n\n private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)\n }\n\n implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {\n def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))\n\n def getElements: Seq[Element] = x match {\n case e: Element => Seq(e)\n case a: Aggregate => a.getElements.flatMap(_.getElements)\n }\n }\n\n /** Any Data subtype that has a Bool member named valid. */\n type DataCanBeValid = Data { val valid: Bool }\n\n implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {\n def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)\n }\n\n implicit class StringToAugmentedString(private val x: String) extends AnyVal {\n /** converts from camel case to to underscores, also removing all spaces */\n def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + \"\") getOrElse \"\") {\n case (acc, c) if c.isUpper => acc + \"_\" + c.toLower\n case (acc, c) if c == ' ' => acc\n case (acc, c) => acc + c\n }\n\n /** converts spaces or underscores to hyphens, also lowering case */\n def kebab: String = x.toLowerCase map {\n case ' ' => '-'\n case '_' => '-'\n case c => c\n }\n\n def named(name: Option[String]): String = {\n x + name.map(\"_named_\" + _ ).getOrElse(\"_with_no_name\")\n }\n\n def named(name: String): String = named(Some(name))\n }\n\n implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)\n implicit def wcToUInt(c: WideCounter): UInt = c.value\n\n implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {\n def sextTo(n: Int): UInt = {\n require(x.getWidth <= n)\n if (x.getWidth == n) x\n else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)\n }\n\n def padTo(n: Int): UInt = {\n require(x.getWidth <= n)\n if (x.getWidth == n) x\n else Cat(0.U((n - x.getWidth).W), x)\n }\n\n // shifts left by n if n >= 0, or right by -n if n < 0\n def << (n: SInt): UInt = {\n val w = n.getWidth - 1\n require(w <= 30)\n\n val shifted = x << n(w-1, 0)\n Mux(n(w), shifted >> (1 << w), shifted)\n }\n\n // shifts right by n if n >= 0, or left by -n if n < 0\n def >> (n: SInt): UInt = {\n val w = n.getWidth - 1\n require(w <= 30)\n\n val shifted = x << (1 << w) >> n(w-1, 0)\n Mux(n(w), shifted, shifted >> (1 << w))\n }\n\n // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts\n def extract(hi: Int, lo: Int): UInt = {\n require(hi >= lo-1)\n if (hi == lo-1) 0.U\n else x(hi, lo)\n }\n\n // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts\n def extractOption(hi: Int, lo: Int): Option[UInt] = {\n require(hi >= lo-1)\n if (hi == lo-1) None\n else Some(x(hi, lo))\n }\n\n // like x & ~y, but first truncate or zero-extend y to x's width\n def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))\n\n def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)\n\n def rotateRight(n: UInt): UInt = {\n if (x.getWidth <= 1) {\n x\n } else {\n val amt = n.padTo(log2Ceil(x.getWidth))\n (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))\n }\n }\n\n def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))\n\n def rotateLeft(n: UInt): UInt = {\n if (x.getWidth <= 1) {\n x\n } else {\n val amt = n.padTo(log2Ceil(x.getWidth))\n (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))\n }\n }\n\n // compute (this + y) % n, given (this < n) and (y < n)\n def addWrap(y: UInt, n: Int): UInt = {\n val z = x +& y\n if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)\n }\n\n // compute (this - y) % n, given (this < n) and (y < n)\n def subWrap(y: UInt, n: Int): UInt = {\n val z = x -& y\n if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)\n }\n\n def grouped(width: Int): Seq[UInt] =\n (0 until x.getWidth by width).map(base => x(base + width - 1, base))\n\n def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds\n\n def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)\n\n // Like >=, but prevents x-prop for ('x >= 0)\n def >== (y: UInt): Bool = x >= y || y === 0.U\n }\n\n implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {\n def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)\n def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)\n }\n\n implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {\n def toInt: Int = if (x) 1 else 0\n\n // this one's snagged from scalaz\n def option[T](z: => T): Option[T] = if (x) Some(z) else None\n }\n\n implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {\n // exact log2\n def log2: Int = {\n require(isPow2(x))\n log2Ceil(x)\n }\n }\n\n def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)\n def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))\n def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)\n def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)\n\n def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None\n\n // Fill 1s from low bits to high bits\n def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)\n def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {\n val stop = min(width, cap)\n def helper(s: Int, x: UInt): UInt =\n if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))\n helper(1, x)(width-1, 0)\n }\n\n // Fill 1s form high bits to low bits\n def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)\n def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {\n val stop = min(width, cap)\n def helper(s: Int, x: UInt): UInt =\n if (s >= stop) x else helper(s+s, x | (x >> s))\n helper(1, x)(width-1, 0)\n }\n\n def OptimizationBarrier[T <: Data](in: T): T = {\n val barrier = Module(new Module {\n val io = IO(new Bundle {\n val x = Input(chiselTypeOf(in))\n val y = Output(chiselTypeOf(in))\n })\n io.y := io.x\n override def desiredName = s\"OptimizationBarrier_${in.typeName}\"\n })\n barrier.io.x := in\n barrier.io.y\n }\n\n /** Similar to Seq.groupBy except this returns a Seq instead of a Map\n * Useful for deterministic code generation\n */\n def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {\n val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]\n for (x <- xs) {\n val key = f(x)\n val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])\n l += x\n }\n map.view.map({ case (k, vs) => k -> vs.toList }).toList\n }\n\n def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {\n case 1 => List.fill(n)(in.head)\n case x if x == n => in\n case _ => throw new Exception(s\"must provide exactly 1 or $n of some field, but got:\\n$in\")\n }\n\n // HeterogeneousBag moved to standalond diplomacy\n @deprecated(\"HeterogeneousBag has been absorbed into standalone diplomacy library\", \"rocketchip 2.0.0\")\n def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)\n @deprecated(\"HeterogeneousBag has been absorbed into standalone diplomacy library\", \"rocketchip 2.0.0\")\n val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag\n}\nFile Parameters.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.diplomacy\n\nimport chisel3._\nimport chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}\nimport freechips.rocketchip.util.ShiftQueue\n\n/** Options for describing the attributes of memory regions */\nobject RegionType {\n // Define the 'more relaxed than' ordering\n val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)\n sealed trait T extends Ordered[T] {\n def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)\n }\n\n case object CACHED extends T // an intermediate agent may have cached a copy of the region for you\n case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided\n case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible\n case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached\n case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects\n case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed\n case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively\n}\n\n// A non-empty half-open range; [start, end)\ncase class IdRange(start: Int, end: Int) extends Ordered[IdRange]\n{\n require (start >= 0, s\"Ids cannot be negative, but got: $start.\")\n require (start <= end, \"Id ranges cannot be negative.\")\n\n def compare(x: IdRange) = {\n val primary = (this.start - x.start).signum\n val secondary = (x.end - this.end).signum\n if (primary != 0) primary else secondary\n }\n\n def overlaps(x: IdRange) = start < x.end && x.start < end\n def contains(x: IdRange) = start <= x.start && x.end <= end\n\n def contains(x: Int) = start <= x && x < end\n def contains(x: UInt) =\n if (size == 0) {\n false.B\n } else if (size == 1) { // simple comparison\n x === start.U\n } else {\n // find index of largest different bit\n val largestDeltaBit = log2Floor(start ^ (end-1))\n val smallestCommonBit = largestDeltaBit + 1 // may not exist in x\n val uncommonMask = (1 << smallestCommonBit) - 1\n val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)\n // the prefix must match exactly (note: may shift ALL bits away)\n (x >> smallestCommonBit) === (start >> smallestCommonBit).U &&\n // firrtl constant prop range analysis can eliminate these two:\n (start & uncommonMask).U <= uncommonBits &&\n uncommonBits <= ((end-1) & uncommonMask).U\n }\n\n def shift(x: Int) = IdRange(start+x, end+x)\n def size = end - start\n def isEmpty = end == start\n\n def range = start until end\n}\n\nobject IdRange\n{\n def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {\n val ranges = s.sorted\n (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }\n }\n}\n\n// An potentially empty inclusive range of 2-powers [min, max] (in bytes)\ncase class TransferSizes(min: Int, max: Int)\n{\n def this(x: Int) = this(x, x)\n\n require (min <= max, s\"Min transfer $min > max transfer $max\")\n require (min >= 0 && max >= 0, s\"TransferSizes must be positive, got: ($min, $max)\")\n require (max == 0 || isPow2(max), s\"TransferSizes must be a power of 2, got: $max\")\n require (min == 0 || isPow2(min), s\"TransferSizes must be a power of 2, got: $min\")\n require (max == 0 || min != 0, s\"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)\")\n\n def none = min == 0\n def contains(x: Int) = isPow2(x) && min <= x && x <= max\n def containsLg(x: Int) = contains(1 << x)\n def containsLg(x: UInt) =\n if (none) false.B\n else if (min == max) { log2Ceil(min).U === x }\n else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }\n\n def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)\n\n def intersect(x: TransferSizes) =\n if (x.max < min || max < x.min) TransferSizes.none\n else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))\n\n // Not a union, because the result may contain sizes contained by neither term\n // NOT TO BE CONFUSED WITH COVERPOINTS\n def mincover(x: TransferSizes) = {\n if (none) {\n x\n } else if (x.none) {\n this\n } else {\n TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))\n }\n }\n\n override def toString() = \"TransferSizes[%d, %d]\".format(min, max)\n}\n\nobject TransferSizes {\n def apply(x: Int) = new TransferSizes(x)\n val none = new TransferSizes(0)\n\n def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)\n def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)\n\n implicit def asBool(x: TransferSizes) = !x.none\n}\n\n// AddressSets specify the address space managed by the manager\n// Base is the base address, and mask are the bits consumed by the manager\n// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff\n// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...\ncase class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]\n{\n // Forbid misaligned base address (and empty sets)\n require ((base & mask) == 0, s\"Mis-aligned AddressSets are forbidden, got: ${this.toString}\")\n require (base >= 0, s\"AddressSet negative base is ambiguous: $base\") // TL2 address widths are not fixed => negative is ambiguous\n // We do allow negative mask (=> ignore all high bits)\n\n def contains(x: BigInt) = ((x ^ base) & ~mask) == 0\n def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S\n\n // turn x into an address contained in this set\n def legalize(x: UInt): UInt = base.U | (mask.U & x)\n\n // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)\n def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0\n // contains iff bitwise: x.mask => mask && contains(x.base)\n def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0\n\n // The number of bytes to which the manager must be aligned\n def alignment = ((mask + 1) & ~mask)\n // Is this a contiguous memory range\n def contiguous = alignment == mask+1\n\n def finite = mask >= 0\n def max = { require (finite, \"Max cannot be calculated on infinite mask\"); base | mask }\n\n // Widen the match function to ignore all bits in imask\n def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)\n\n // Return an AddressSet that only contains the addresses both sets contain\n def intersect(x: AddressSet): Option[AddressSet] = {\n if (!overlaps(x)) {\n None\n } else {\n val r_mask = mask & x.mask\n val r_base = base | x.base\n Some(AddressSet(r_base, r_mask))\n }\n }\n\n def subtract(x: AddressSet): Seq[AddressSet] = {\n intersect(x) match {\n case None => Seq(this)\n case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>\n val nmask = (mask & (bit-1)) | remove.mask\n val nbase = (remove.base ^ bit) & ~nmask\n AddressSet(nbase, nmask)\n }\n }\n }\n\n // AddressSets have one natural Ordering (the containment order, if contiguous)\n def compare(x: AddressSet) = {\n val primary = (this.base - x.base).signum // smallest address first\n val secondary = (x.mask - this.mask).signum // largest mask first\n if (primary != 0) primary else secondary\n }\n\n // We always want to see things in hex\n override def toString() = {\n if (mask >= 0) {\n \"AddressSet(0x%x, 0x%x)\".format(base, mask)\n } else {\n \"AddressSet(0x%x, ~0x%x)\".format(base, ~mask)\n }\n }\n\n def toRanges = {\n require (finite, \"Ranges cannot be calculated on infinite mask\")\n val size = alignment\n val fragments = mask & ~(size-1)\n val bits = bitIndexes(fragments)\n (BigInt(0) until (BigInt(1) << bits.size)).map { i =>\n val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }\n AddressRange(off, size)\n }\n }\n}\n\nobject AddressSet\n{\n val everything = AddressSet(0, -1)\n def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {\n if (size == 0) tail.reverse else {\n val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)\n val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size\n val step =\n if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)\n maxSizeAlignment else maxBaseAlignment\n misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)\n }\n }\n\n def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {\n // Pair terms up by ignoring 'bit'\n seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>\n if (seq.size == 1) {\n seq.head // singleton -> unaffected\n } else {\n key.copy(mask = key.mask | bit) // pair - widen mask by bit\n }\n }.toList\n }\n\n def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {\n val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)\n AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted\n }\n\n def enumerateMask(mask: BigInt): Seq[BigInt] = {\n def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =\n if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)\n helper(0, Nil)\n }\n\n def enumerateBits(mask: BigInt): Seq[BigInt] = {\n def helper(x: BigInt): Seq[BigInt] = {\n if (x == 0) {\n Nil\n } else {\n val bit = x & (-x)\n bit +: helper(x & ~bit)\n }\n }\n helper(mask)\n }\n}\n\ncase class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)\n{\n require (depth >= 0, \"Buffer depth must be >= 0\")\n def isDefined = depth > 0\n def latency = if (isDefined && !flow) 1 else 0\n\n def apply[T <: Data](x: DecoupledIO[T]) =\n if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)\n else x\n\n def irrevocable[T <: Data](x: ReadyValidIO[T]) =\n if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)\n else x\n\n def sq[T <: Data](x: DecoupledIO[T]) =\n if (!isDefined) x else {\n val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))\n sq.io.enq <> x\n sq.io.deq\n }\n\n override def toString() = \"BufferParams:%d%s%s\".format(depth, if (flow) \"F\" else \"\", if (pipe) \"P\" else \"\")\n\n}\n\nobject BufferParams\n{\n implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)\n\n val default = BufferParams(2)\n val none = BufferParams(0)\n val flow = BufferParams(1, true, false)\n val pipe = BufferParams(1, false, true)\n}\n\ncase class TriStateValue(value: Boolean, set: Boolean)\n{\n def update(orig: Boolean) = if (set) value else orig\n}\n\nobject TriStateValue\n{\n implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)\n def unset = TriStateValue(false, false)\n}\n\ntrait DirectedBuffers[T] {\n def copyIn(x: BufferParams): T\n def copyOut(x: BufferParams): T\n def copyInOut(x: BufferParams): T\n}\n\ntrait IdMapEntry {\n def name: String\n def from: IdRange\n def to: IdRange\n def isCache: Boolean\n def requestFifo: Boolean\n def maxTransactionsInFlight: Option[Int]\n def pretty(fmt: String) =\n if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5\n fmt.format(to.start, to.end, from.start, from.end, s\"\"\"\"$name\"\"\"\", if (isCache) \" [CACHE]\" else \"\", if (requestFifo) \" [FIFO]\" else \"\")\n } else {\n fmt.format(from.start, from.end, s\"\"\"\"$name\"\"\"\", if (isCache) \" [CACHE]\" else \"\", if (requestFifo) \" [FIFO]\" else \"\")\n }\n}\n\nabstract class IdMap[T <: IdMapEntry] {\n protected val fmt: String\n val mapping: Seq[T]\n def pretty: String = mapping.map(_.pretty(fmt)).mkString(\",\\n\")\n}\nFile Edges.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.tilelink\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.experimental.SourceInfo\nimport org.chipsalliance.cde.config.Parameters\nimport freechips.rocketchip.util._\n\nclass TLEdge(\n client: TLClientPortParameters,\n manager: TLManagerPortParameters,\n params: Parameters,\n sourceInfo: SourceInfo)\n extends TLEdgeParameters(client, manager, params, sourceInfo)\n{\n def isAligned(address: UInt, lgSize: UInt): Bool = {\n if (maxLgSize == 0) true.B else {\n val mask = UIntToOH1(lgSize, maxLgSize)\n (address & mask) === 0.U\n }\n }\n\n def mask(address: UInt, lgSize: UInt): UInt =\n MaskGen(address, lgSize, manager.beatBytes)\n\n def staticHasData(bundle: TLChannel): Option[Boolean] = {\n bundle match {\n case _:TLBundleA => {\n // Do there exist A messages with Data?\n val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial\n // Do there exist A messages without Data?\n val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint\n // Statically optimize the case where hasData is a constant\n if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None\n }\n case _:TLBundleB => {\n // Do there exist B messages with Data?\n val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial\n // Do there exist B messages without Data?\n val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint\n // Statically optimize the case where hasData is a constant\n if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None\n }\n case _:TLBundleC => {\n // Do there eixst C messages with Data?\n val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe\n // Do there exist C messages without Data?\n val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe\n if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None\n }\n case _:TLBundleD => {\n // Do there eixst D messages with Data?\n val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB\n // Do there exist D messages without Data?\n val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT\n if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None\n }\n case _:TLBundleE => Some(false)\n }\n }\n\n def isRequest(x: TLChannel): Bool = {\n x match {\n case a: TLBundleA => true.B\n case b: TLBundleB => true.B\n case c: TLBundleC => c.opcode(2) && c.opcode(1)\n // opcode === TLMessages.Release ||\n // opcode === TLMessages.ReleaseData\n case d: TLBundleD => d.opcode(2) && !d.opcode(1)\n // opcode === TLMessages.Grant ||\n // opcode === TLMessages.GrantData\n case e: TLBundleE => false.B\n }\n }\n\n def isResponse(x: TLChannel): Bool = {\n x match {\n case a: TLBundleA => false.B\n case b: TLBundleB => false.B\n case c: TLBundleC => !c.opcode(2) || !c.opcode(1)\n // opcode =/= TLMessages.Release &&\n // opcode =/= TLMessages.ReleaseData\n case d: TLBundleD => true.B // Grant isResponse + isRequest\n case e: TLBundleE => true.B\n }\n }\n\n def hasData(x: TLChannel): Bool = {\n val opdata = x match {\n case a: TLBundleA => !a.opcode(2)\n // opcode === TLMessages.PutFullData ||\n // opcode === TLMessages.PutPartialData ||\n // opcode === TLMessages.ArithmeticData ||\n // opcode === TLMessages.LogicalData\n case b: TLBundleB => !b.opcode(2)\n // opcode === TLMessages.PutFullData ||\n // opcode === TLMessages.PutPartialData ||\n // opcode === TLMessages.ArithmeticData ||\n // opcode === TLMessages.LogicalData\n case c: TLBundleC => c.opcode(0)\n // opcode === TLMessages.AccessAckData ||\n // opcode === TLMessages.ProbeAckData ||\n // opcode === TLMessages.ReleaseData\n case d: TLBundleD => d.opcode(0)\n // opcode === TLMessages.AccessAckData ||\n // opcode === TLMessages.GrantData\n case e: TLBundleE => false.B\n }\n staticHasData(x).map(_.B).getOrElse(opdata)\n }\n\n def opcode(x: TLDataChannel): UInt = {\n x match {\n case a: TLBundleA => a.opcode\n case b: TLBundleB => b.opcode\n case c: TLBundleC => c.opcode\n case d: TLBundleD => d.opcode\n }\n }\n\n def param(x: TLDataChannel): UInt = {\n x match {\n case a: TLBundleA => a.param\n case b: TLBundleB => b.param\n case c: TLBundleC => c.param\n case d: TLBundleD => d.param\n }\n }\n\n def size(x: TLDataChannel): UInt = {\n x match {\n case a: TLBundleA => a.size\n case b: TLBundleB => b.size\n case c: TLBundleC => c.size\n case d: TLBundleD => d.size\n }\n }\n\n def data(x: TLDataChannel): UInt = {\n x match {\n case a: TLBundleA => a.data\n case b: TLBundleB => b.data\n case c: TLBundleC => c.data\n case d: TLBundleD => d.data\n }\n }\n\n def corrupt(x: TLDataChannel): Bool = {\n x match {\n case a: TLBundleA => a.corrupt\n case b: TLBundleB => b.corrupt\n case c: TLBundleC => c.corrupt\n case d: TLBundleD => d.corrupt\n }\n }\n\n def mask(x: TLAddrChannel): UInt = {\n x match {\n case a: TLBundleA => a.mask\n case b: TLBundleB => b.mask\n case c: TLBundleC => mask(c.address, c.size)\n }\n }\n\n def full_mask(x: TLAddrChannel): UInt = {\n x match {\n case a: TLBundleA => mask(a.address, a.size)\n case b: TLBundleB => mask(b.address, b.size)\n case c: TLBundleC => mask(c.address, c.size)\n }\n }\n\n def address(x: TLAddrChannel): UInt = {\n x match {\n case a: TLBundleA => a.address\n case b: TLBundleB => b.address\n case c: TLBundleC => c.address\n }\n }\n\n def source(x: TLDataChannel): UInt = {\n x match {\n case a: TLBundleA => a.source\n case b: TLBundleB => b.source\n case c: TLBundleC => c.source\n case d: TLBundleD => d.source\n }\n }\n\n def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)\n def addr_lo(x: UInt): UInt =\n if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)\n\n def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))\n def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))\n\n def numBeats(x: TLChannel): UInt = {\n x match {\n case _: TLBundleE => 1.U\n case bundle: TLDataChannel => {\n val hasData = this.hasData(bundle)\n val size = this.size(bundle)\n val cutoff = log2Ceil(manager.beatBytes)\n val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U\n val decode = UIntToOH(size, maxLgSize+1) >> cutoff\n Mux(hasData, decode | small.asUInt, 1.U)\n }\n }\n }\n\n def numBeats1(x: TLChannel): UInt = {\n x match {\n case _: TLBundleE => 0.U\n case bundle: TLDataChannel => {\n if (maxLgSize == 0) {\n 0.U\n } else {\n val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)\n Mux(hasData(bundle), decode, 0.U)\n }\n }\n }\n }\n\n def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {\n val beats1 = numBeats1(bits)\n val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))\n val counter1 = counter - 1.U\n val first = counter === 0.U\n val last = counter === 1.U || beats1 === 0.U\n val done = last && fire\n val count = (beats1 & ~counter1)\n when (fire) {\n counter := Mux(first, beats1, counter1)\n }\n (first, last, done, count)\n }\n\n def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1\n def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)\n def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)\n\n def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2\n def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)\n def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)\n\n def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3\n def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)\n def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)\n\n def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {\n val r = firstlastHelper(bits, fire)\n (r._1, r._2, r._3)\n }\n def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)\n def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)\n\n def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {\n val r = firstlastHelper(bits, fire)\n (r._1, r._2, r._3, r._4)\n }\n def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)\n def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)\n\n def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {\n val r = firstlastHelper(bits, fire)\n (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))\n }\n def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)\n def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)\n\n // Does the request need T permissions to be executed?\n def needT(a: TLBundleA): Bool = {\n val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(\n TLPermissions.NtoB -> false.B,\n TLPermissions.NtoT -> true.B,\n TLPermissions.BtoT -> true.B))\n MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(\n TLMessages.PutFullData -> true.B,\n TLMessages.PutPartialData -> true.B,\n TLMessages.ArithmeticData -> true.B,\n TLMessages.LogicalData -> true.B,\n TLMessages.Get -> false.B,\n TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(\n TLHints.PREFETCH_READ -> false.B,\n TLHints.PREFETCH_WRITE -> true.B)),\n TLMessages.AcquireBlock -> acq_needT,\n TLMessages.AcquirePerm -> acq_needT))\n }\n\n // This is a very expensive circuit; use only if you really mean it!\n def inFlight(x: TLBundle): (UInt, UInt) = {\n val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))\n val bce = manager.anySupportAcquireB && client.anySupportProbe\n\n val (a_first, a_last, _) = firstlast(x.a)\n val (b_first, b_last, _) = firstlast(x.b)\n val (c_first, c_last, _) = firstlast(x.c)\n val (d_first, d_last, _) = firstlast(x.d)\n val (e_first, e_last, _) = firstlast(x.e)\n\n val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))\n val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))\n val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))\n val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))\n val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))\n\n val a_inc = x.a.fire && a_first && a_request\n val b_inc = x.b.fire && b_first && b_request\n val c_inc = x.c.fire && c_first && c_request\n val d_inc = x.d.fire && d_first && d_request\n val e_inc = x.e.fire && e_first && e_request\n val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))\n\n val a_dec = x.a.fire && a_last && a_response\n val b_dec = x.b.fire && b_last && b_response\n val c_dec = x.c.fire && c_last && c_response\n val d_dec = x.d.fire && d_last && d_response\n val e_dec = x.e.fire && e_last && e_response\n val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))\n\n val next_flight = flight + PopCount(inc) - PopCount(dec)\n flight := next_flight\n\n (flight, next_flight)\n }\n\n def prettySourceMapping(context: String): String = {\n s\"TL-Source mapping for $context:\\n${(new TLSourceIdMap(client)).pretty}\\n\"\n }\n}\n\nclass TLEdgeOut(\n client: TLClientPortParameters,\n manager: TLManagerPortParameters,\n params: Parameters,\n sourceInfo: SourceInfo)\n extends TLEdge(client, manager, params, sourceInfo)\n{\n // Transfers\n def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {\n require (manager.anySupportAcquireB, s\"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsAcquireBFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.AcquireBlock\n a.param := growPermissions\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := DontCare\n a.corrupt := false.B\n (legal, a)\n }\n\n def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {\n require (manager.anySupportAcquireB, s\"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsAcquireBFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.AcquirePerm\n a.param := growPermissions\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := DontCare\n a.corrupt := false.B\n (legal, a)\n }\n\n def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {\n require (manager.anySupportAcquireB, s\"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsAcquireBFast(toAddress, lgSize)\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.Release\n c.param := shrinkPermissions\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := DontCare\n c.corrupt := false.B\n (legal, c)\n }\n\n def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {\n require (manager.anySupportAcquireB, s\"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsAcquireBFast(toAddress, lgSize)\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.ReleaseData\n c.param := shrinkPermissions\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := data\n c.corrupt := corrupt\n (legal, c)\n }\n\n def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =\n Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)\n\n def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =\n ProbeAck(b.source, b.address, b.size, reportPermissions)\n\n def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.ProbeAck\n c.param := reportPermissions\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := DontCare\n c.corrupt := false.B\n c\n }\n\n def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =\n ProbeAck(b.source, b.address, b.size, reportPermissions, data)\n\n def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.ProbeAckData\n c.param := reportPermissions\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := data\n c.corrupt := corrupt\n c\n }\n\n def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =\n ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)\n\n def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)\n def GrantAck(toSink: UInt): TLBundleE = {\n val e = Wire(new TLBundleE(bundle))\n e.sink := toSink\n e\n }\n\n // Accesses\n def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {\n require (manager.anySupportGet, s\"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsGetFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.Get\n a.param := 0.U\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := DontCare\n a.corrupt := false.B\n (legal, a)\n }\n\n def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =\n Put(fromSource, toAddress, lgSize, data, false.B)\n\n def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {\n require (manager.anySupportPutFull, s\"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsPutFullFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.PutFullData\n a.param := 0.U\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := data\n a.corrupt := corrupt\n (legal, a)\n }\n\n def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =\n Put(fromSource, toAddress, lgSize, data, mask, false.B)\n\n def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {\n require (manager.anySupportPutPartial, s\"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsPutPartialFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.PutPartialData\n a.param := 0.U\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask\n a.data := data\n a.corrupt := corrupt\n (legal, a)\n }\n\n def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {\n require (manager.anySupportArithmetic, s\"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsArithmeticFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.ArithmeticData\n a.param := atomic\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := data\n a.corrupt := corrupt\n (legal, a)\n }\n\n def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {\n require (manager.anySupportLogical, s\"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsLogicalFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.LogicalData\n a.param := atomic\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := data\n a.corrupt := corrupt\n (legal, a)\n }\n\n def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {\n require (manager.anySupportHint, s\"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsHintFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.Hint\n a.param := param\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := DontCare\n a.corrupt := false.B\n (legal, a)\n }\n\n def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)\n def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.AccessAck\n c.param := 0.U\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := DontCare\n c.corrupt := false.B\n c\n }\n\n def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)\n def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)\n def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)\n def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.AccessAckData\n c.param := 0.U\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := data\n c.corrupt := corrupt\n c\n }\n\n def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)\n def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.HintAck\n c.param := 0.U\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := DontCare\n c.corrupt := false.B\n c\n }\n}\n\nclass TLEdgeIn(\n client: TLClientPortParameters,\n manager: TLManagerPortParameters,\n params: Parameters,\n sourceInfo: SourceInfo)\n extends TLEdge(client, manager, params, sourceInfo)\n{\n private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {\n val todo = x.filter(!_.isEmpty)\n val heads = todo.map(_.head)\n val tails = todo.map(_.tail)\n if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }\n }\n\n // Transfers\n def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {\n require (client.anySupportProbe, s\"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}\")\n val legal = client.supportsProbe(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.Probe\n b.param := capPermissions\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask(fromAddress, lgSize)\n b.data := DontCare\n b.corrupt := false.B\n (legal, b)\n }\n\n def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)\n def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {\n val d = Wire(new TLBundleD(bundle))\n d.opcode := TLMessages.Grant\n d.param := capPermissions\n d.size := lgSize\n d.source := toSource\n d.sink := fromSink\n d.denied := denied\n d.user := DontCare\n d.echo := DontCare\n d.data := DontCare\n d.corrupt := false.B\n d\n }\n\n def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)\n def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {\n val d = Wire(new TLBundleD(bundle))\n d.opcode := TLMessages.GrantData\n d.param := capPermissions\n d.size := lgSize\n d.source := toSource\n d.sink := fromSink\n d.denied := denied\n d.user := DontCare\n d.echo := DontCare\n d.data := data\n d.corrupt := corrupt\n d\n }\n\n def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)\n def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {\n val d = Wire(new TLBundleD(bundle))\n d.opcode := TLMessages.ReleaseAck\n d.param := 0.U\n d.size := lgSize\n d.source := toSource\n d.sink := 0.U\n d.denied := denied\n d.user := DontCare\n d.echo := DontCare\n d.data := DontCare\n d.corrupt := false.B\n d\n }\n\n // Accesses\n def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {\n require (client.anySupportGet, s\"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}\")\n val legal = client.supportsGet(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.Get\n b.param := 0.U\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask(fromAddress, lgSize)\n b.data := DontCare\n b.corrupt := false.B\n (legal, b)\n }\n\n def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =\n Put(fromAddress, toSource, lgSize, data, false.B)\n\n def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {\n require (client.anySupportPutFull, s\"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}\")\n val legal = client.supportsPutFull(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.PutFullData\n b.param := 0.U\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask(fromAddress, lgSize)\n b.data := data\n b.corrupt := corrupt\n (legal, b)\n }\n\n def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =\n Put(fromAddress, toSource, lgSize, data, mask, false.B)\n\n def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {\n require (client.anySupportPutPartial, s\"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}\")\n val legal = client.supportsPutPartial(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.PutPartialData\n b.param := 0.U\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask\n b.data := data\n b.corrupt := corrupt\n (legal, b)\n }\n\n def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {\n require (client.anySupportArithmetic, s\"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}\")\n val legal = client.supportsArithmetic(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.ArithmeticData\n b.param := atomic\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask(fromAddress, lgSize)\n b.data := data\n b.corrupt := corrupt\n (legal, b)\n }\n\n def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {\n require (client.anySupportLogical, s\"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}\")\n val legal = client.supportsLogical(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.LogicalData\n b.param := atomic\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask(fromAddress, lgSize)\n b.data := data\n b.corrupt := corrupt\n (legal, b)\n }\n\n def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {\n require (client.anySupportHint, s\"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}\")\n val legal = client.supportsHint(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.Hint\n b.param := param\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask(fromAddress, lgSize)\n b.data := DontCare\n b.corrupt := false.B\n (legal, b)\n }\n\n def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)\n def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)\n def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)\n def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {\n val d = Wire(new TLBundleD(bundle))\n d.opcode := TLMessages.AccessAck\n d.param := 0.U\n d.size := lgSize\n d.source := toSource\n d.sink := 0.U\n d.denied := denied\n d.user := DontCare\n d.echo := DontCare\n d.data := DontCare\n d.corrupt := false.B\n d\n }\n\n def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)\n def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)\n def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)\n def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {\n val d = Wire(new TLBundleD(bundle))\n d.opcode := TLMessages.AccessAckData\n d.param := 0.U\n d.size := lgSize\n d.source := toSource\n d.sink := 0.U\n d.denied := denied\n d.user := DontCare\n d.echo := DontCare\n d.data := data\n d.corrupt := corrupt\n d\n }\n\n def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)\n def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)\n def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)\n def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {\n val d = Wire(new TLBundleD(bundle))\n d.opcode := TLMessages.HintAck\n d.param := 0.U\n d.size := lgSize\n d.source := toSource\n d.sink := 0.U\n d.denied := denied\n d.user := DontCare\n d.echo := DontCare\n d.data := DontCare\n d.corrupt := false.B\n d\n }\n}\n"},"response":{"kind":"string","value":"module TLMonitor_9(\t// @[Monitor.scala:36:7]\n input clock,\t// @[Monitor.scala:36:7]\n input reset,\t// @[Monitor.scala:36:7]\n input io_in_a_ready,\t// @[Monitor.scala:20:14]\n input io_in_a_valid,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_a_bits_opcode,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_a_bits_param,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_a_bits_size,\t// @[Monitor.scala:20:14]\n input [7:0] io_in_a_bits_source,\t// @[Monitor.scala:20:14]\n input [28:0] io_in_a_bits_address,\t// @[Monitor.scala:20:14]\n input [7:0] io_in_a_bits_mask,\t// @[Monitor.scala:20:14]\n input io_in_a_bits_corrupt,\t// @[Monitor.scala:20:14]\n input io_in_d_ready,\t// @[Monitor.scala:20:14]\n input io_in_d_valid,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_d_bits_opcode,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_d_bits_size,\t// @[Monitor.scala:20:14]\n input [7:0] io_in_d_bits_source\t// @[Monitor.scala:20:14]\n);\n\n wire [31:0] _plusarg_reader_1_out;\t// @[PlusArg.scala:80:11]\n wire [31:0] _plusarg_reader_out;\t// @[PlusArg.scala:80:11]\n wire [12:0] _GEN = {10'h0, io_in_a_bits_size};\t// @[package.scala:243:71]\n wire _a_first_T_1 = io_in_a_ready & io_in_a_valid;\t// @[Decoupled.scala:51:35]\n reg [2:0] a_first_counter;\t// @[Edges.scala:229:27]\n reg [2:0] opcode;\t// @[Monitor.scala:387:22]\n reg [2:0] param;\t// @[Monitor.scala:388:22]\n reg [2:0] size;\t// @[Monitor.scala:389:22]\n reg [7:0] source;\t// @[Monitor.scala:390:22]\n reg [28:0] address;\t// @[Monitor.scala:391:22]\n reg [2:0] d_first_counter;\t// @[Edges.scala:229:27]\n reg [2:0] opcode_1;\t// @[Monitor.scala:538:22]\n reg [2:0] size_1;\t// @[Monitor.scala:540:22]\n reg [7:0] source_1;\t// @[Monitor.scala:541:22]\n reg [128:0] inflight;\t// @[Monitor.scala:614:27]\n reg [515:0] inflight_opcodes;\t// @[Monitor.scala:616:35]\n reg [515:0] inflight_sizes;\t// @[Monitor.scala:618:33]\n reg [2:0] a_first_counter_1;\t// @[Edges.scala:229:27]\n wire a_first_1 = a_first_counter_1 == 3'h0;\t// @[Edges.scala:229:27, :231:25]\n reg [2:0] d_first_counter_1;\t// @[Edges.scala:229:27]\n wire d_first_1 = d_first_counter_1 == 3'h0;\t// @[Edges.scala:229:27, :231:25]\n wire _GEN_0 = _a_first_T_1 & a_first_1;\t// @[Decoupled.scala:51:35]\n wire d_release_ack = io_in_d_bits_opcode == 3'h6;\t// @[Monitor.scala:673:46]\n wire _GEN_1 = io_in_d_bits_opcode != 3'h6;\t// @[Monitor.scala:673:46, :674:74]\n reg [31:0] watchdog;\t// @[Monitor.scala:709:27]\n reg [128:0] inflight_1;\t// @[Monitor.scala:726:35]\n reg [515:0] inflight_sizes_1;\t// @[Monitor.scala:728:35]\n reg [2:0] d_first_counter_2;\t// @[Edges.scala:229:27]\n wire d_first_2 = d_first_counter_2 == 3'h0;\t// @[Edges.scala:229:27, :231:25]\n reg [31:0] watchdog_1;\t// @[Monitor.scala:818:27]"}}},{"rowIdx":572,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to the following Chisel files.\nFile PE.scala:\n// See README.md for license details.\npackage gemmini\n\nimport chisel3._\nimport chisel3.util._\n\nclass PEControl[T <: Data : Arithmetic](accType: T) extends Bundle {\n val dataflow = UInt(1.W) // TODO make this an Enum\n val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)?\n val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats\n\n}\n\nclass MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module {\n import ev._\n val io = IO(new Bundle {\n val in_a = Input(inputType)\n val in_b = Input(inputType)\n val in_c = Input(cType)\n val out_d = Output(dType)\n })\n\n io.out_d := io.in_c.mac(io.in_a, io.in_b)\n}\n\n// TODO update documentation\n/**\n * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh.\n * @param width Data width of operands\n */\nclass PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int)\n (implicit ev: Arithmetic[T]) extends Module { // Debugging variables\n import ev._\n\n val io = IO(new Bundle {\n val in_a = Input(inputType)\n val in_b = Input(outputType)\n val in_d = Input(outputType)\n val out_a = Output(inputType)\n val out_b = Output(outputType)\n val out_c = Output(outputType)\n\n val in_control = Input(new PEControl(accType))\n val out_control = Output(new PEControl(accType))\n\n val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W))\n val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W))\n\n val in_last = Input(Bool())\n val out_last = Output(Bool())\n\n val in_valid = Input(Bool())\n val out_valid = Output(Bool())\n\n val bad_dataflow = Output(Bool())\n })\n\n val cType = if (df == Dataflow.WS) inputType else accType\n\n // When creating PEs that support multiple dataflows, the\n // elaboration/synthesis tools often fail to consolidate and de-duplicate\n // MAC units. To force mac circuitry to be re-used, we create a \"mac_unit\"\n // module here which just performs a single MAC operation\n val mac_unit = Module(new MacUnit(inputType,\n if (df == Dataflow.WS) outputType else accType, outputType))\n\n val a = io.in_a\n val b = io.in_b\n val d = io.in_d\n val c1 = Reg(cType)\n val c2 = Reg(cType)\n val dataflow = io.in_control.dataflow\n val prop = io.in_control.propagate\n val shift = io.in_control.shift\n val id = io.in_id\n val last = io.in_last\n val valid = io.in_valid\n\n io.out_a := a\n io.out_control.dataflow := dataflow\n io.out_control.propagate := prop\n io.out_control.shift := shift\n io.out_id := id\n io.out_last := last\n io.out_valid := valid\n\n mac_unit.io.in_a := a\n\n val last_s = RegEnable(prop, valid)\n val flip = last_s =/= prop\n val shift_offset = Mux(flip, shift, 0.U)\n\n // Which dataflow are we using?\n val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W)\n val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W)\n\n // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)?\n val COMPUTE = 0.U(1.W)\n val PROPAGATE = 1.U(1.W)\n\n io.bad_dataflow := false.B\n when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) {\n when(prop === PROPAGATE) {\n io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType)\n io.out_b := b\n mac_unit.io.in_b := b.asTypeOf(inputType)\n mac_unit.io.in_c := c2\n c2 := mac_unit.io.out_d\n c1 := d.withWidthOf(cType)\n }.otherwise {\n io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType)\n io.out_b := b\n mac_unit.io.in_b := b.asTypeOf(inputType)\n mac_unit.io.in_c := c1\n c1 := mac_unit.io.out_d\n c2 := d.withWidthOf(cType)\n }\n }.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) {\n when(prop === PROPAGATE) {\n io.out_c := c1\n mac_unit.io.in_b := c2.asTypeOf(inputType)\n mac_unit.io.in_c := b\n io.out_b := mac_unit.io.out_d\n c1 := d\n }.otherwise {\n io.out_c := c2\n mac_unit.io.in_b := c1.asTypeOf(inputType)\n mac_unit.io.in_c := b\n io.out_b := mac_unit.io.out_d\n c2 := d\n }\n }.otherwise {\n io.bad_dataflow := true.B\n //assert(false.B, \"unknown dataflow\")\n io.out_c := DontCare\n io.out_b := DontCare\n mac_unit.io.in_b := b.asTypeOf(inputType)\n mac_unit.io.in_c := c2\n }\n\n when (!valid) {\n c1 := c1\n c2 := c2\n mac_unit.io.in_b := DontCare\n mac_unit.io.in_c := DontCare\n }\n}\nFile Arithmetic.scala:\n// A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own:\n// implicit MyTypeArithmetic extends Arithmetic[MyType] { ... }\n\npackage gemmini\n\nimport chisel3._\nimport chisel3.util._\nimport hardfloat._\n\n// Bundles that represent the raw bits of custom datatypes\ncase class Float(expWidth: Int, sigWidth: Int) extends Bundle {\n val bits = UInt((expWidth + sigWidth).W)\n\n val bias: Int = (1 << (expWidth-1)) - 1\n}\n\ncase class DummySInt(w: Int) extends Bundle {\n val bits = UInt(w.W)\n def dontCare: DummySInt = {\n val o = Wire(new DummySInt(w))\n o.bits := 0.U\n o\n }\n}\n\n// The Arithmetic typeclass which implements various arithmetic operations on custom datatypes\nabstract class Arithmetic[T <: Data] {\n implicit def cast(t: T): ArithmeticOps[T]\n}\n\nabstract class ArithmeticOps[T <: Data](self: T) {\n def *(t: T): T\n def mac(m1: T, m2: T): T // Returns (m1 * m2 + self)\n def +(t: T): T\n def -(t: T): T\n def >>(u: UInt): T // This is a rounding shift! Rounds away from 0\n def >(t: T): Bool\n def identity: T\n def withWidthOf(t: T): T\n def clippedToWidthOf(t: T): T // Like \"withWidthOf\", except that it saturates\n def relu: T\n def zero: T\n def minimum: T\n\n // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers\n def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None\n def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None\n def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None\n def mult_with_reciprocal[U <: Data](reciprocal: U) = self\n}\n\nobject Arithmetic {\n implicit object UIntArithmetic extends Arithmetic[UInt] {\n override implicit def cast(self: UInt) = new ArithmeticOps(self) {\n override def *(t: UInt) = self * t\n override def mac(m1: UInt, m2: UInt) = m1 * m2 + self\n override def +(t: UInt) = self + t\n override def -(t: UInt) = self - t\n\n override def >>(u: UInt) = {\n // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm\n\n // TODO Do we need to explicitly handle the cases where \"u\" is a small number (like 0)? What is the default behavior here?\n val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))\n val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U\n val ones_digit = self(u)\n\n val r = point_five & (zeros | ones_digit)\n\n (self >> u).asUInt + r\n }\n\n override def >(t: UInt): Bool = self > t\n\n override def withWidthOf(t: UInt) = self.asTypeOf(t)\n\n override def clippedToWidthOf(t: UInt) = {\n val sat = ((1 << (t.getWidth-1))-1).U\n Mux(self > sat, sat, self)(t.getWidth-1, 0)\n }\n\n override def relu: UInt = self\n\n override def zero: UInt = 0.U\n override def identity: UInt = 1.U\n override def minimum: UInt = 0.U\n }\n }\n\n implicit object SIntArithmetic extends Arithmetic[SInt] {\n override implicit def cast(self: SInt) = new ArithmeticOps(self) {\n override def *(t: SInt) = self * t\n override def mac(m1: SInt, m2: SInt) = m1 * m2 + self\n override def +(t: SInt) = self + t\n override def -(t: SInt) = self - t\n\n override def >>(u: UInt) = {\n // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm\n\n // TODO Do we need to explicitly handle the cases where \"u\" is a small number (like 0)? What is the default behavior here?\n val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))\n val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U\n val ones_digit = self(u)\n\n val r = (point_five & (zeros | ones_digit)).asBool\n\n (self >> u).asSInt + Mux(r, 1.S, 0.S)\n }\n\n override def >(t: SInt): Bool = self > t\n\n override def withWidthOf(t: SInt) = {\n if (self.getWidth >= t.getWidth)\n self(t.getWidth-1, 0).asSInt\n else {\n val sign_bits = t.getWidth - self.getWidth\n val sign = self(self.getWidth-1)\n Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t)\n }\n }\n\n override def clippedToWidthOf(t: SInt): SInt = {\n val maxsat = ((1 << (t.getWidth-1))-1).S\n val minsat = (-(1 << (t.getWidth-1))).S\n MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt\n }\n\n override def relu: SInt = Mux(self >= 0.S, self, 0.S)\n\n override def zero: SInt = 0.S\n override def identity: SInt = 1.S\n override def minimum: SInt = (-(1 << (self.getWidth-1))).S\n\n override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {\n // TODO this uses a floating point divider, but we should use an integer divider instead\n\n val input = Wire(Decoupled(denom_t.cloneType))\n val output = Wire(Decoupled(self.cloneType))\n\n // We translate our integer to floating-point form so that we can use the hardfloat divider\n val expWidth = log2Up(self.getWidth) + 1\n val sigWidth = self.getWidth\n\n def sin_to_float(x: SInt) = {\n val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))\n in_to_rec_fn.io.signedIn := true.B\n in_to_rec_fn.io.in := x.asUInt\n in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag\n in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding\n\n in_to_rec_fn.io.out\n }\n\n def uin_to_float(x: UInt) = {\n val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))\n in_to_rec_fn.io.signedIn := false.B\n in_to_rec_fn.io.in := x\n in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag\n in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding\n\n in_to_rec_fn.io.out\n }\n\n def float_to_in(x: UInt) = {\n val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))\n rec_fn_to_in.io.signedOut := true.B\n rec_fn_to_in.io.in := x\n rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag\n\n rec_fn_to_in.io.out.asSInt\n }\n\n val self_rec = sin_to_float(self)\n val denom_rec = uin_to_float(input.bits)\n\n // Instantiate the hardloat divider\n val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))\n\n input.ready := divider.io.inReady\n divider.io.inValid := input.valid\n divider.io.sqrtOp := false.B\n divider.io.a := self_rec\n divider.io.b := denom_rec\n divider.io.roundingMode := consts.round_minMag\n divider.io.detectTininess := consts.tininess_afterRounding\n\n output.valid := divider.io.outValid_div\n output.bits := float_to_in(divider.io.out)\n\n assert(!output.valid || output.ready)\n\n Some((input, output))\n }\n\n override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {\n // TODO this uses a floating point divider, but we should use an integer divider instead\n\n val input = Wire(Decoupled(UInt(0.W)))\n val output = Wire(Decoupled(self.cloneType))\n\n input.bits := DontCare\n\n // We translate our integer to floating-point form so that we can use the hardfloat divider\n val expWidth = log2Up(self.getWidth) + 1\n val sigWidth = self.getWidth\n\n def in_to_float(x: SInt) = {\n val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))\n in_to_rec_fn.io.signedIn := true.B\n in_to_rec_fn.io.in := x.asUInt\n in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag\n in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding\n\n in_to_rec_fn.io.out\n }\n\n def float_to_in(x: UInt) = {\n val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))\n rec_fn_to_in.io.signedOut := true.B\n rec_fn_to_in.io.in := x\n rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag\n\n rec_fn_to_in.io.out.asSInt\n }\n\n val self_rec = in_to_float(self)\n\n // Instantiate the hardloat sqrt\n val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0))\n\n input.ready := sqrter.io.inReady\n sqrter.io.inValid := input.valid\n sqrter.io.sqrtOp := true.B\n sqrter.io.a := self_rec\n sqrter.io.b := DontCare\n sqrter.io.roundingMode := consts.round_minMag\n sqrter.io.detectTininess := consts.tininess_afterRounding\n\n output.valid := sqrter.io.outValid_sqrt\n output.bits := float_to_in(sqrter.io.out)\n\n assert(!output.valid || output.ready)\n\n Some((input, output))\n }\n\n override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match {\n case Float(expWidth, sigWidth) =>\n val input = Wire(Decoupled(UInt(0.W)))\n val output = Wire(Decoupled(u.cloneType))\n\n input.bits := DontCare\n\n // We translate our integer to floating-point form so that we can use the hardfloat divider\n def in_to_float(x: SInt) = {\n val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))\n in_to_rec_fn.io.signedIn := true.B\n in_to_rec_fn.io.in := x.asUInt\n in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag\n in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding\n\n in_to_rec_fn.io.out\n }\n\n val self_rec = in_to_float(self)\n val one_rec = in_to_float(1.S)\n\n // Instantiate the hardloat divider\n val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))\n\n input.ready := divider.io.inReady\n divider.io.inValid := input.valid\n divider.io.sqrtOp := false.B\n divider.io.a := one_rec\n divider.io.b := self_rec\n divider.io.roundingMode := consts.round_near_even\n divider.io.detectTininess := consts.tininess_afterRounding\n\n output.valid := divider.io.outValid_div\n output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u)\n\n assert(!output.valid || output.ready)\n\n Some((input, output))\n\n case _ => None\n }\n\n override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match {\n case recip @ Float(expWidth, sigWidth) =>\n def in_to_float(x: SInt) = {\n val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))\n in_to_rec_fn.io.signedIn := true.B\n in_to_rec_fn.io.in := x.asUInt\n in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag\n in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding\n\n in_to_rec_fn.io.out\n }\n\n def float_to_in(x: UInt) = {\n val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))\n rec_fn_to_in.io.signedOut := true.B\n rec_fn_to_in.io.in := x\n rec_fn_to_in.io.roundingMode := consts.round_minMag\n\n rec_fn_to_in.io.out.asSInt\n }\n\n val self_rec = in_to_float(self)\n val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits)\n\n // Instantiate the hardloat divider\n val muladder = Module(new MulRecFN(expWidth, sigWidth))\n muladder.io.roundingMode := consts.round_near_even\n muladder.io.detectTininess := consts.tininess_afterRounding\n\n muladder.io.a := self_rec\n muladder.io.b := reciprocal_rec\n\n float_to_in(muladder.io.out)\n\n case _ => self\n }\n }\n }\n\n implicit object FloatArithmetic extends Arithmetic[Float] {\n // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array\n\n override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) {\n override def *(t: Float): Float = {\n val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)\n val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)\n\n val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))\n t_resizer.io.in := t_rec\n t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag\n t_resizer.io.detectTininess := consts.tininess_afterRounding\n val t_rec_resized = t_resizer.io.out\n\n val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))\n\n muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag\n muladder.io.detectTininess := consts.tininess_afterRounding\n\n muladder.io.a := self_rec\n muladder.io.b := t_rec_resized\n\n val out = Wire(Float(self.expWidth, self.sigWidth))\n out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)\n out\n }\n\n override def mac(m1: Float, m2: Float): Float = {\n // Recode all operands\n val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits)\n val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits)\n val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)\n\n // Resize m1 to self's width\n val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth))\n m1_resizer.io.in := m1_rec\n m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag\n m1_resizer.io.detectTininess := consts.tininess_afterRounding\n val m1_rec_resized = m1_resizer.io.out\n \n // Resize m2 to self's width\n val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth))\n m2_resizer.io.in := m2_rec\n m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag\n m2_resizer.io.detectTininess := consts.tininess_afterRounding\n val m2_rec_resized = m2_resizer.io.out\n\n // Perform multiply-add\n val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))\n\n muladder.io.op := 0.U\n muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag\n muladder.io.detectTininess := consts.tininess_afterRounding\n\n muladder.io.a := m1_rec_resized\n muladder.io.b := m2_rec_resized\n muladder.io.c := self_rec\n\n // Convert result to standard format // TODO remove these intermediate recodings\n val out = Wire(Float(self.expWidth, self.sigWidth))\n out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)\n out\n }\n\n override def +(t: Float): Float = {\n require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code\n\n // Recode all operands\n val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)\n val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)\n\n // Generate 1 as a float\n val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth))\n in_to_rec_fn.io.signedIn := false.B\n in_to_rec_fn.io.in := 1.U\n in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag\n in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding\n\n val one_rec = in_to_rec_fn.io.out\n\n // Resize t\n val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))\n t_resizer.io.in := t_rec\n t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag\n t_resizer.io.detectTininess := consts.tininess_afterRounding\n val t_rec_resized = t_resizer.io.out\n\n // Perform addition\n val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))\n\n muladder.io.op := 0.U\n muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag\n muladder.io.detectTininess := consts.tininess_afterRounding\n\n muladder.io.a := t_rec_resized\n muladder.io.b := one_rec\n muladder.io.c := self_rec\n\n val result = Wire(Float(self.expWidth, self.sigWidth))\n result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)\n result\n }\n\n override def -(t: Float): Float = {\n val t_sgn = t.bits(t.getWidth-1)\n val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t)\n self + neg_t\n }\n\n override def >>(u: UInt): Float = {\n // Recode self\n val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)\n\n // Get 2^(-u) as a recoded float\n val shift_exp = Wire(UInt(self.expWidth.W))\n shift_exp := self.bias.U - u\n val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W))\n val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn)\n\n assert(shift_exp =/= 0.U, \"scaling by denormalized numbers is not currently supported\")\n\n // Multiply self and 2^(-u)\n val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))\n\n muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag\n muladder.io.detectTininess := consts.tininess_afterRounding\n\n muladder.io.a := self_rec\n muladder.io.b := shift_rec\n\n val result = Wire(Float(self.expWidth, self.sigWidth))\n result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)\n result\n }\n\n override def >(t: Float): Bool = {\n // Recode all operands\n val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)\n val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)\n\n // Resize t to self's width\n val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))\n t_resizer.io.in := t_rec\n t_resizer.io.roundingMode := consts.round_near_even\n t_resizer.io.detectTininess := consts.tininess_afterRounding\n val t_rec_resized = t_resizer.io.out\n\n val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth))\n comparator.io.a := self_rec\n comparator.io.b := t_rec_resized\n comparator.io.signaling := false.B\n\n comparator.io.gt\n }\n\n override def withWidthOf(t: Float): Float = {\n val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)\n\n val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))\n resizer.io.in := self_rec\n resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag\n resizer.io.detectTininess := consts.tininess_afterRounding\n\n val result = Wire(Float(t.expWidth, t.sigWidth))\n result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)\n result\n }\n\n override def clippedToWidthOf(t: Float): Float = {\n // TODO check for overflow. Right now, we just assume that overflow doesn't happen\n val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)\n\n val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))\n resizer.io.in := self_rec\n resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag\n resizer.io.detectTininess := consts.tininess_afterRounding\n\n val result = Wire(Float(t.expWidth, t.sigWidth))\n result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)\n result\n }\n\n override def relu: Float = {\n val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits)\n\n val result = Wire(Float(self.expWidth, self.sigWidth))\n result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits)\n result\n }\n\n override def zero: Float = 0.U.asTypeOf(self)\n override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)\n override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)\n }\n }\n\n implicit object DummySIntArithmetic extends Arithmetic[DummySInt] {\n override implicit def cast(self: DummySInt) = new ArithmeticOps(self) {\n override def *(t: DummySInt) = self.dontCare\n override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare\n override def +(t: DummySInt) = self.dontCare\n override def -(t: DummySInt) = self.dontCare\n override def >>(t: UInt) = self.dontCare\n override def >(t: DummySInt): Bool = false.B\n override def identity = self.dontCare\n override def withWidthOf(t: DummySInt) = self.dontCare\n override def clippedToWidthOf(t: DummySInt) = self.dontCare\n override def relu = self.dontCare\n override def zero = self.dontCare\n override def minimum: DummySInt = self.dontCare\n }\n }\n}\n"},"response":{"kind":"string","value":"module PE_498(\t// @[PE.scala:31:7]\n input clock,\t// @[PE.scala:31:7]\n input reset,\t// @[PE.scala:31:7]\n input [7:0] io_in_a,\t// @[PE.scala:35:14]\n input [19:0] io_in_b,\t// @[PE.scala:35:14]\n input [19:0] io_in_d,\t// @[PE.scala:35:14]\n output [7:0] io_out_a,\t// @[PE.scala:35:14]\n output [19:0] io_out_b,\t// @[PE.scala:35:14]\n output [19:0] io_out_c,\t// @[PE.scala:35:14]\n input io_in_control_dataflow,\t// @[PE.scala:35:14]\n input io_in_control_propagate,\t// @[PE.scala:35:14]\n input [4:0] io_in_control_shift,\t// @[PE.scala:35:14]\n output io_out_control_dataflow,\t// @[PE.scala:35:14]\n output io_out_control_propagate,\t// @[PE.scala:35:14]\n output [4:0] io_out_control_shift,\t// @[PE.scala:35:14]\n input [2:0] io_in_id,\t// @[PE.scala:35:14]\n output [2:0] io_out_id,\t// @[PE.scala:35:14]\n input io_in_last,\t// @[PE.scala:35:14]\n output io_out_last,\t// @[PE.scala:35:14]\n input io_in_valid,\t// @[PE.scala:35:14]\n output io_out_valid\t// @[PE.scala:35:14]\n);\n\n wire [7:0] io_in_a_0 = io_in_a;\t// @[PE.scala:31:7]\n wire [19:0] io_in_b_0 = io_in_b;\t// @[PE.scala:31:7]\n wire [19:0] io_in_d_0 = io_in_d;\t// @[PE.scala:31:7]\n wire io_in_control_dataflow_0 = io_in_control_dataflow;\t// @[PE.scala:31:7]\n wire io_in_control_propagate_0 = io_in_control_propagate;\t// @[PE.scala:31:7]\n wire [4:0] io_in_control_shift_0 = io_in_control_shift;\t// @[PE.scala:31:7]\n wire [2:0] io_in_id_0 = io_in_id;\t// @[PE.scala:31:7]\n wire io_in_last_0 = io_in_last;\t// @[PE.scala:31:7]\n wire io_in_valid_0 = io_in_valid;\t// @[PE.scala:31:7]\n wire io_bad_dataflow = 1'h0;\t// @[PE.scala:31:7]\n wire _io_out_c_T_5 = 1'h0;\t// @[Arithmetic.scala:125:33]\n wire _io_out_c_T_6 = 1'h0;\t// @[Arithmetic.scala:125:60]\n wire _io_out_c_T_16 = 1'h0;\t// @[Arithmetic.scala:125:33]\n wire _io_out_c_T_17 = 1'h0;\t// @[Arithmetic.scala:125:60]\n wire [7:0] io_out_a_0 = io_in_a_0;\t// @[PE.scala:31:7]\n wire [19:0] _mac_unit_io_in_b_T = io_in_b_0;\t// @[PE.scala:31:7, :106:37]\n wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0;\t// @[PE.scala:31:7, :113:37]\n wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0;\t// @[PE.scala:31:7, :137:35]\n wire io_out_control_dataflow_0 = io_in_control_dataflow_0;\t// @[PE.scala:31:7]\n wire io_out_control_propagate_0 = io_in_control_propagate_0;\t// @[PE.scala:31:7]\n wire [4:0] io_out_control_shift_0 = io_in_control_shift_0;\t// @[PE.scala:31:7]\n wire [2:0] io_out_id_0 = io_in_id_0;\t// @[PE.scala:31:7]\n wire io_out_last_0 = io_in_last_0;\t// @[PE.scala:31:7]\n wire io_out_valid_0 = io_in_valid_0;\t// @[PE.scala:31:7]\n wire [19:0] io_out_b_0;\t// @[PE.scala:31:7]\n wire [19:0] io_out_c_0;\t// @[PE.scala:31:7]\n reg [7:0] c1;\t// @[PE.scala:70:15]\n wire [7:0] _io_out_c_zeros_T_1 = c1;\t// @[PE.scala:70:15]\n wire [7:0] _mac_unit_io_in_b_T_6 = c1;\t// @[PE.scala:70:15, :127:38]\n reg [7:0] c2;\t// @[PE.scala:71:15]\n wire [7:0] _io_out_c_zeros_T_10 = c2;\t// @[PE.scala:71:15]\n wire [7:0] _mac_unit_io_in_b_T_4 = c2;\t// @[PE.scala:71:15, :121:38]\n reg last_s;\t// @[PE.scala:89:25]\n wire flip = last_s != io_in_control_propagate_0;\t// @[PE.scala:31:7, :89:25, :90:21]\n wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0;\t// @[PE.scala:31:7, :90:21, :91:25]\n wire _GEN = shift_offset == 5'h0;\t// @[PE.scala:91:25]\n wire _io_out_c_point_five_T;\t// @[Arithmetic.scala:101:32]\n assign _io_out_c_point_five_T = _GEN;\t// @[Arithmetic.scala:101:32]\n wire _io_out_c_point_five_T_5;\t// @[Arithmetic.scala:101:32]\n assign _io_out_c_point_five_T_5 = _GEN;\t// @[Arithmetic.scala:101:32]\n wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1;\t// @[PE.scala:91:25]\n wire [5:0] _io_out_c_point_five_T_1;\t// @[Arithmetic.scala:101:53]\n assign _io_out_c_point_five_T_1 = _GEN_0;\t// @[Arithmetic.scala:101:53]\n wire [5:0] _io_out_c_zeros_T_2;\t// @[Arithmetic.scala:102:66]\n assign _io_out_c_zeros_T_2 = _GEN_0;\t// @[Arithmetic.scala:101:53, :102:66]\n wire [5:0] _io_out_c_point_five_T_6;\t// @[Arithmetic.scala:101:53]\n assign _io_out_c_point_five_T_6 = _GEN_0;\t// @[Arithmetic.scala:101:53]\n wire [5:0] _io_out_c_zeros_T_11;\t// @[Arithmetic.scala:102:66]\n assign _io_out_c_zeros_T_11 = _GEN_0;\t// @[Arithmetic.scala:101:53, :102:66]\n wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0];\t// @[Arithmetic.scala:101:53]\n wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2);\t// @[PE.scala:70:15]\n wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0];\t// @[Arithmetic.scala:101:50]\n wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4;\t// @[Arithmetic.scala:101:{29,32,50}]\n wire _GEN_1 = shift_offset < 5'h2;\t// @[PE.scala:91:25]\n wire _io_out_c_zeros_T;\t// @[Arithmetic.scala:102:27]\n assign _io_out_c_zeros_T = _GEN_1;\t// @[Arithmetic.scala:102:27]\n wire _io_out_c_zeros_T_9;\t// @[Arithmetic.scala:102:27]\n assign _io_out_c_zeros_T_9 = _GEN_1;\t// @[Arithmetic.scala:102:27]\n wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0];\t// @[Arithmetic.scala:102:66]\n wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3;\t// @[Arithmetic.scala:102:{60,66}]\n wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1;\t// @[Arithmetic.scala:102:{60,81}]\n wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0];\t// @[Arithmetic.scala:102:81]\n wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1};\t// @[Arithmetic.scala:102:{45,52,81}]\n wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7;\t// @[Arithmetic.scala:102:{24,27,52}]\n wire io_out_c_zeros = |_io_out_c_zeros_T_8;\t// @[Arithmetic.scala:102:{24,89}]\n wire [7:0] _GEN_2 = {3'h0, shift_offset};\t// @[PE.scala:91:25]\n wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2);\t// @[PE.scala:70:15]\n wire [7:0] _io_out_c_ones_digit_T;\t// @[Arithmetic.scala:103:30]\n assign _io_out_c_ones_digit_T = _GEN_3;\t// @[Arithmetic.scala:103:30]\n wire [7:0] _io_out_c_T;\t// @[Arithmetic.scala:107:15]\n assign _io_out_c_T = _GEN_3;\t// @[Arithmetic.scala:103:30, :107:15]\n wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0];\t// @[Arithmetic.scala:103:30]\n wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit;\t// @[Arithmetic.scala:102:89, :103:30, :105:38]\n wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T;\t// @[Arithmetic.scala:101:29, :105:{29,38}]\n wire io_out_c_r = _io_out_c_r_T_1;\t// @[Arithmetic.scala:105:{29,53}]\n wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r};\t// @[Arithmetic.scala:105:53, :107:33]\n wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1};\t// @[Arithmetic.scala:107:{15,28,33}]\n wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0];\t// @[Arithmetic.scala:107:28]\n wire [7:0] _io_out_c_T_4 = _io_out_c_T_3;\t// @[Arithmetic.scala:107:28]\n wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4};\t// @[Mux.scala:126:16]\n wire [19:0] _io_out_c_T_8 = _io_out_c_T_7;\t// @[Mux.scala:126:16]\n wire [19:0] _io_out_c_T_9 = _io_out_c_T_8;\t// @[Mux.scala:126:16]\n wire [19:0] _io_out_c_T_10 = _io_out_c_T_9;\t// @[Arithmetic.scala:125:{81,99}]\n wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T;\t// @[PE.scala:106:37]\n wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0];\t// @[PE.scala:106:37]\n wire [7:0] _c1_T = io_in_d_0[7:0];\t// @[PE.scala:31:7]\n wire [7:0] _c2_T = io_in_d_0[7:0];\t// @[PE.scala:31:7]\n wire [7:0] _c1_T_1 = _c1_T;\t// @[Arithmetic.scala:114:{15,33}]\n wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0];\t// @[Arithmetic.scala:101:53]\n wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7);\t// @[PE.scala:71:15]\n wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0];\t// @[Arithmetic.scala:101:50]\n wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9;\t// @[Arithmetic.scala:101:{29,32,50}]\n wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0];\t// @[Arithmetic.scala:102:66]\n wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12;\t// @[Arithmetic.scala:102:{60,66}]\n wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1;\t// @[Arithmetic.scala:102:{60,81}]\n wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0];\t// @[Arithmetic.scala:102:81]\n wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10};\t// @[Arithmetic.scala:102:{45,52,81}]\n wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16;\t// @[Arithmetic.scala:102:{24,27,52}]\n wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17;\t// @[Arithmetic.scala:102:{24,89}]\n wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2);\t// @[PE.scala:71:15]\n wire [7:0] _io_out_c_ones_digit_T_1;\t// @[Arithmetic.scala:103:30]\n assign _io_out_c_ones_digit_T_1 = _GEN_4;\t// @[Arithmetic.scala:103:30]\n wire [7:0] _io_out_c_T_11;\t// @[Arithmetic.scala:107:15]\n assign _io_out_c_T_11 = _GEN_4;\t// @[Arithmetic.scala:103:30, :107:15]\n wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0];\t// @[Arithmetic.scala:103:30]\n wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1;\t// @[Arithmetic.scala:102:89, :103:30, :105:38]\n wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2;\t// @[Arithmetic.scala:101:29, :105:{29,38}]\n wire io_out_c_r_1 = _io_out_c_r_T_3;\t// @[Arithmetic.scala:105:{29,53}]\n wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1};\t// @[Arithmetic.scala:105:53, :107:33]\n wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12};\t// @[Arithmetic.scala:107:{15,28,33}]\n wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0];\t// @[Arithmetic.scala:107:28]\n wire [7:0] _io_out_c_T_15 = _io_out_c_T_14;\t// @[Arithmetic.scala:107:28]\n wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15};\t// @[Mux.scala:126:16]\n wire [19:0] _io_out_c_T_19 = _io_out_c_T_18;\t// @[Mux.scala:126:16]\n wire [19:0] _io_out_c_T_20 = _io_out_c_T_19;\t// @[Mux.scala:126:16]\n wire [19:0] _io_out_c_T_21 = _io_out_c_T_20;\t// @[Arithmetic.scala:125:{81,99}]\n wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2;\t// @[PE.scala:113:37]\n wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0];\t// @[PE.scala:113:37]\n wire [7:0] _c2_T_1 = _c2_T;\t// @[Arithmetic.scala:114:{15,33}]\n wire [7:0] _mac_unit_io_in_b_T_5;\t// @[PE.scala:121:38]\n assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4;\t// @[PE.scala:121:38]\n wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5;\t// @[PE.scala:121:38]\n assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2};\t// @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16]\n wire [7:0] _mac_unit_io_in_b_T_7;\t// @[PE.scala:127:38]\n assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6;\t// @[PE.scala:127:38]\n wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7;\t// @[PE.scala:127:38]\n wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8;\t// @[PE.scala:137:35]\n wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0];\t// @[PE.scala:137:35]\n always @(posedge clock) begin\t// @[PE.scala:31:7]\n if (io_in_valid_0 & io_in_control_propagate_0)\t// @[PE.scala:31:7, :102:95, :141:17, :142:8]\n c1 <= io_in_d_0[7:0];\t// @[PE.scala:31:7, :70:15]\n if (~(~io_in_valid_0 | io_in_control_propagate_0))\t// @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8]\n c2 <= io_in_d_0[7:0];\t// @[PE.scala:31:7, :71:15]\n if (io_in_valid_0)\t// @[PE.scala:31:7]\n last_s <= io_in_control_propagate_0;\t// @[PE.scala:31:7, :89:25]\n always @(posedge)\n MacUnit_242 mac_unit (\t// @[PE.scala:64:24]\n .clock (clock),\n .reset (reset),\n .io_in_a (io_in_a_0),\t// @[PE.scala:31:7]\n .io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3),\t// @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}]\n .io_in_c (io_in_b_0),\t// @[PE.scala:31:7]\n .io_out_d (io_out_b_0)\n );\t// @[PE.scala:64:24]\n assign io_out_a = io_out_a_0;\t// @[PE.scala:31:7]\n assign io_out_b = io_out_b_0;\t// @[PE.scala:31:7]\n assign io_out_c = io_out_c_0;\t// @[PE.scala:31:7]\n assign io_out_control_dataflow = io_out_control_dataflow_0;\t// @[PE.scala:31:7]\n assign io_out_control_propagate = io_out_control_propagate_0;\t// @[PE.scala:31:7]\n assign io_out_control_shift = io_out_control_shift_0;\t// @[PE.scala:31:7]\n assign io_out_id = io_out_id_0;\t// @[PE.scala:31:7]\n assign io_out_last = io_out_last_0;\t// @[PE.scala:31:7]\n assign io_out_valid = io_out_valid_0;\t// @[PE.scala:31:7]\nendmodule"}}},{"rowIdx":573,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to the following Chisel files.\nFile Monitor.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.tilelink\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.experimental.SourceLine\n\nimport org.chipsalliance.cde.config._\nimport org.chipsalliance.diplomacy._\n\nimport freechips.rocketchip.diplomacy.EnableMonitors\nimport freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}\nimport freechips.rocketchip.util.PlusArg\n\ncase class TLMonitorArgs(edge: TLEdge)\n\nabstract class TLMonitorBase(args: TLMonitorArgs) extends Module\n{\n val io = IO(new Bundle {\n val in = Input(new TLBundle(args.edge.bundle))\n })\n\n def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit\n legalize(io.in, args.edge, reset)\n}\n\nobject TLMonitor {\n def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {\n if (enable) {\n EnableMonitors { implicit p => node := TLEphemeralNode()(ValName(\"monitor\")) }\n } else { node }\n }\n}\n\nclass TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)\n{\n require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))\n\n val cover_prop_class = PropertyClass.Default\n\n //Like assert but can flip to being an assumption for formal verification\n def monAssert(cond: Bool, message: String): Unit =\n if (monitorDir == MonitorDirection.Monitor) {\n assert(cond, message)\n } else {\n Property(monitorDir, cond, message, PropertyClass.Default)\n }\n\n def assume(cond: Bool, message: String): Unit =\n if (monitorDir == MonitorDirection.Monitor) {\n assert(cond, message)\n } else {\n Property(monitorDir.flip, cond, message, PropertyClass.Default)\n }\n\n def extra = {\n args.edge.sourceInfo match {\n case SourceLine(filename, line, col) => s\" (connected at $filename:$line:$col)\"\n case _ => \"\"\n }\n }\n\n def visible(address: UInt, source: UInt, edge: TLEdge) =\n edge.client.clients.map { c =>\n !c.sourceId.contains(source) ||\n c.visibility.map(_.contains(address)).reduce(_ || _)\n }.reduce(_ && _)\n\n def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {\n //switch this flag to turn on diplomacy in error messages\n def diplomacyInfo = if (true) \"\" else \"\\nThe diplomacy information for the edge is as follows:\\n\" + edge.formatEdge + \"\\n\"\n monAssert (TLMessages.isA(bundle.opcode), \"'A' channel has invalid opcode\" + extra)\n\n // Reuse these subexpressions to save some firrtl lines\n val source_ok = edge.client.contains(bundle.source)\n val is_aligned = edge.isAligned(bundle.address, bundle.size)\n val mask = edge.full_mask(bundle)\n\n monAssert (visible(edge.address(bundle), bundle.source, edge), \"'A' channel carries an address illegal for the specified bank visibility\")\n\n //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B\n //TODO: check for acquireT?\n when (bundle.opcode === TLMessages.AcquireBlock) {\n monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters\" + diplomacyInfo + extra)\n monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock from a client which does not support Probe\" + diplomacyInfo + extra)\n monAssert (source_ok, \"'A' channel AcquireBlock carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'A' channel AcquireBlock smaller than a beat\" + extra)\n monAssert (is_aligned, \"'A' channel AcquireBlock address not aligned to size\" + extra)\n monAssert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquireBlock carries invalid grow param\" + extra)\n monAssert (~bundle.mask === 0.U, \"'A' channel AcquireBlock contains invalid mask\" + extra)\n monAssert (!bundle.corrupt, \"'A' channel AcquireBlock is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.AcquirePerm) {\n monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters\" + diplomacyInfo + extra)\n monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm from a client which does not support Probe\" + diplomacyInfo + extra)\n monAssert (source_ok, \"'A' channel AcquirePerm carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'A' channel AcquirePerm smaller than a beat\" + extra)\n monAssert (is_aligned, \"'A' channel AcquirePerm address not aligned to size\" + extra)\n monAssert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquirePerm carries invalid grow param\" + extra)\n monAssert (bundle.param =/= TLPermissions.NtoB, \"'A' channel AcquirePerm requests NtoB\" + extra)\n monAssert (~bundle.mask === 0.U, \"'A' channel AcquirePerm contains invalid mask\" + extra)\n monAssert (!bundle.corrupt, \"'A' channel AcquirePerm is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.Get) {\n monAssert (edge.master.emitsGet(bundle.source, bundle.size), \"'A' channel carries Get type which master claims it can't emit\" + diplomacyInfo + extra)\n monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), \"'A' channel carries Get type which slave claims it can't support\" + diplomacyInfo + extra)\n monAssert (source_ok, \"'A' channel Get carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'A' channel Get carries invalid param\" + extra)\n monAssert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n monAssert (!bundle.corrupt, \"'A' channel Get is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.PutFullData) {\n monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type which is unexpected using diplomatic parameters\" + diplomacyInfo + extra)\n monAssert (source_ok, \"'A' channel PutFull carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'A' channel PutFull carries invalid param\" + extra)\n monAssert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.PutPartialData) {\n monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type which is unexpected using diplomatic parameters\" + extra)\n monAssert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'A' channel PutPartial carries invalid param\" + extra)\n monAssert ((bundle.mask & ~mask) === 0.U, \"'A' channel PutPartial contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.ArithmeticData) {\n monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type which is unexpected using diplomatic parameters\" + extra)\n monAssert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n monAssert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n monAssert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.LogicalData) {\n monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type which is unexpected using diplomatic parameters\" + extra)\n monAssert (source_ok, \"'A' channel Logical carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n monAssert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n monAssert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.Hint) {\n monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type which is unexpected using diplomatic parameters\" + extra)\n monAssert (source_ok, \"'A' channel Hint carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n monAssert (TLHints.isHints(bundle.param), \"'A' channel Hint carries invalid opcode param\" + extra)\n monAssert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n monAssert (!bundle.corrupt, \"'A' channel Hint is corrupt\" + extra)\n }\n }\n\n def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {\n monAssert (TLMessages.isB(bundle.opcode), \"'B' channel has invalid opcode\" + extra)\n\n monAssert (visible(edge.address(bundle), bundle.source, edge), \"'B' channel carries an address illegal for the specified bank visibility\")\n\n // Reuse these subexpressions to save some firrtl lines\n val address_ok = edge.manager.containsSafe(edge.address(bundle))\n val is_aligned = edge.isAligned(bundle.address, bundle.size)\n val mask = edge.full_mask(bundle)\n val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source\n\n when (bundle.opcode === TLMessages.Probe) {\n assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), \"'B' channel carries Probe type which is unexpected using diplomatic parameters\" + extra)\n assume (address_ok, \"'B' channel Probe carries unmanaged address\" + extra)\n assume (legal_source, \"'B' channel Probe carries source that is not first source\" + extra)\n assume (is_aligned, \"'B' channel Probe address not aligned to size\" + extra)\n assume (TLPermissions.isCap(bundle.param), \"'B' channel Probe carries invalid cap param\" + extra)\n assume (bundle.mask === mask, \"'B' channel Probe contains invalid mask\" + extra)\n assume (!bundle.corrupt, \"'B' channel Probe is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.Get) {\n monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), \"'B' channel carries Get type which is unexpected using diplomatic parameters\" + extra)\n monAssert (address_ok, \"'B' channel Get carries unmanaged address\" + extra)\n monAssert (legal_source, \"'B' channel Get carries source that is not first source\" + extra)\n monAssert (is_aligned, \"'B' channel Get address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'B' channel Get carries invalid param\" + extra)\n monAssert (bundle.mask === mask, \"'B' channel Get contains invalid mask\" + extra)\n monAssert (!bundle.corrupt, \"'B' channel Get is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.PutFullData) {\n monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), \"'B' channel carries PutFull type which is unexpected using diplomatic parameters\" + extra)\n monAssert (address_ok, \"'B' channel PutFull carries unmanaged address\" + extra)\n monAssert (legal_source, \"'B' channel PutFull carries source that is not first source\" + extra)\n monAssert (is_aligned, \"'B' channel PutFull address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'B' channel PutFull carries invalid param\" + extra)\n monAssert (bundle.mask === mask, \"'B' channel PutFull contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.PutPartialData) {\n monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), \"'B' channel carries PutPartial type which is unexpected using diplomatic parameters\" + extra)\n monAssert (address_ok, \"'B' channel PutPartial carries unmanaged address\" + extra)\n monAssert (legal_source, \"'B' channel PutPartial carries source that is not first source\" + extra)\n monAssert (is_aligned, \"'B' channel PutPartial address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'B' channel PutPartial carries invalid param\" + extra)\n monAssert ((bundle.mask & ~mask) === 0.U, \"'B' channel PutPartial contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.ArithmeticData) {\n monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), \"'B' channel carries Arithmetic type unsupported by master\" + extra)\n monAssert (address_ok, \"'B' channel Arithmetic carries unmanaged address\" + extra)\n monAssert (legal_source, \"'B' channel Arithmetic carries source that is not first source\" + extra)\n monAssert (is_aligned, \"'B' channel Arithmetic address not aligned to size\" + extra)\n monAssert (TLAtomics.isArithmetic(bundle.param), \"'B' channel Arithmetic carries invalid opcode param\" + extra)\n monAssert (bundle.mask === mask, \"'B' channel Arithmetic contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.LogicalData) {\n monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), \"'B' channel carries Logical type unsupported by client\" + extra)\n monAssert (address_ok, \"'B' channel Logical carries unmanaged address\" + extra)\n monAssert (legal_source, \"'B' channel Logical carries source that is not first source\" + extra)\n monAssert (is_aligned, \"'B' channel Logical address not aligned to size\" + extra)\n monAssert (TLAtomics.isLogical(bundle.param), \"'B' channel Logical carries invalid opcode param\" + extra)\n monAssert (bundle.mask === mask, \"'B' channel Logical contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.Hint) {\n monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), \"'B' channel carries Hint type unsupported by client\" + extra)\n monAssert (address_ok, \"'B' channel Hint carries unmanaged address\" + extra)\n monAssert (legal_source, \"'B' channel Hint carries source that is not first source\" + extra)\n monAssert (is_aligned, \"'B' channel Hint address not aligned to size\" + extra)\n monAssert (bundle.mask === mask, \"'B' channel Hint contains invalid mask\" + extra)\n monAssert (!bundle.corrupt, \"'B' channel Hint is corrupt\" + extra)\n }\n }\n\n def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {\n monAssert (TLMessages.isC(bundle.opcode), \"'C' channel has invalid opcode\" + extra)\n\n val source_ok = edge.client.contains(bundle.source)\n val is_aligned = edge.isAligned(bundle.address, bundle.size)\n val address_ok = edge.manager.containsSafe(edge.address(bundle))\n\n monAssert (visible(edge.address(bundle), bundle.source, edge), \"'C' channel carries an address illegal for the specified bank visibility\")\n\n when (bundle.opcode === TLMessages.ProbeAck) {\n monAssert (address_ok, \"'C' channel ProbeAck carries unmanaged address\" + extra)\n monAssert (source_ok, \"'C' channel ProbeAck carries invalid source ID\" + extra)\n monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'C' channel ProbeAck smaller than a beat\" + extra)\n monAssert (is_aligned, \"'C' channel ProbeAck address not aligned to size\" + extra)\n monAssert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAck carries invalid report param\" + extra)\n monAssert (!bundle.corrupt, \"'C' channel ProbeAck is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.ProbeAckData) {\n monAssert (address_ok, \"'C' channel ProbeAckData carries unmanaged address\" + extra)\n monAssert (source_ok, \"'C' channel ProbeAckData carries invalid source ID\" + extra)\n monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'C' channel ProbeAckData smaller than a beat\" + extra)\n monAssert (is_aligned, \"'C' channel ProbeAckData address not aligned to size\" + extra)\n monAssert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAckData carries invalid report param\" + extra)\n }\n\n when (bundle.opcode === TLMessages.Release) {\n monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries Release type unsupported by manager\" + extra)\n monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), \"'C' channel carries Release from a client which does not support Probe\" + extra)\n monAssert (source_ok, \"'C' channel Release carries invalid source ID\" + extra)\n monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'C' channel Release smaller than a beat\" + extra)\n monAssert (is_aligned, \"'C' channel Release address not aligned to size\" + extra)\n monAssert (TLPermissions.isReport(bundle.param), \"'C' channel Release carries invalid report param\" + extra)\n monAssert (!bundle.corrupt, \"'C' channel Release is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.ReleaseData) {\n monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries ReleaseData type unsupported by manager\" + extra)\n monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), \"'C' channel carries Release from a client which does not support Probe\" + extra)\n monAssert (source_ok, \"'C' channel ReleaseData carries invalid source ID\" + extra)\n monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'C' channel ReleaseData smaller than a beat\" + extra)\n monAssert (is_aligned, \"'C' channel ReleaseData address not aligned to size\" + extra)\n monAssert (TLPermissions.isReport(bundle.param), \"'C' channel ReleaseData carries invalid report param\" + extra)\n }\n\n when (bundle.opcode === TLMessages.AccessAck) {\n monAssert (address_ok, \"'C' channel AccessAck carries unmanaged address\" + extra)\n monAssert (source_ok, \"'C' channel AccessAck carries invalid source ID\" + extra)\n monAssert (is_aligned, \"'C' channel AccessAck address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'C' channel AccessAck carries invalid param\" + extra)\n monAssert (!bundle.corrupt, \"'C' channel AccessAck is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.AccessAckData) {\n monAssert (address_ok, \"'C' channel AccessAckData carries unmanaged address\" + extra)\n monAssert (source_ok, \"'C' channel AccessAckData carries invalid source ID\" + extra)\n monAssert (is_aligned, \"'C' channel AccessAckData address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'C' channel AccessAckData carries invalid param\" + extra)\n }\n\n when (bundle.opcode === TLMessages.HintAck) {\n monAssert (address_ok, \"'C' channel HintAck carries unmanaged address\" + extra)\n monAssert (source_ok, \"'C' channel HintAck carries invalid source ID\" + extra)\n monAssert (is_aligned, \"'C' channel HintAck address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'C' channel HintAck carries invalid param\" + extra)\n monAssert (!bundle.corrupt, \"'C' channel HintAck is corrupt\" + extra)\n }\n }\n\n def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {\n assume (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n\n val source_ok = edge.client.contains(bundle.source)\n val sink_ok = bundle.sink < edge.manager.endSinkId.U\n val deny_put_ok = edge.manager.mayDenyPut.B\n val deny_get_ok = edge.manager.mayDenyGet.B\n\n when (bundle.opcode === TLMessages.ReleaseAck) {\n assume (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'D' channel ReleaseAck smaller than a beat\" + extra)\n assume (bundle.param === 0.U, \"'D' channel ReleaseeAck carries invalid param\" + extra)\n assume (!bundle.corrupt, \"'D' channel ReleaseAck is corrupt\" + extra)\n assume (!bundle.denied, \"'D' channel ReleaseAck is denied\" + extra)\n }\n\n when (bundle.opcode === TLMessages.Grant) {\n assume (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n assume (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'D' channel Grant smaller than a beat\" + extra)\n assume (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n assume (bundle.param =/= TLPermissions.toN, \"'D' channel Grant carries toN param\" + extra)\n assume (!bundle.corrupt, \"'D' channel Grant is corrupt\" + extra)\n assume (deny_put_ok || !bundle.denied, \"'D' channel Grant is denied\" + extra)\n }\n\n when (bundle.opcode === TLMessages.GrantData) {\n assume (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n assume (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'D' channel GrantData smaller than a beat\" + extra)\n assume (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n assume (bundle.param =/= TLPermissions.toN, \"'D' channel GrantData carries toN param\" + extra)\n assume (!bundle.denied || bundle.corrupt, \"'D' channel GrantData is denied but not corrupt\" + extra)\n assume (deny_get_ok || !bundle.denied, \"'D' channel GrantData is denied\" + extra)\n }\n\n when (bundle.opcode === TLMessages.AccessAck) {\n assume (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n // size is ignored\n assume (bundle.param === 0.U, \"'D' channel AccessAck carries invalid param\" + extra)\n assume (!bundle.corrupt, \"'D' channel AccessAck is corrupt\" + extra)\n assume (deny_put_ok || !bundle.denied, \"'D' channel AccessAck is denied\" + extra)\n }\n\n when (bundle.opcode === TLMessages.AccessAckData) {\n assume (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n // size is ignored\n assume (bundle.param === 0.U, \"'D' channel AccessAckData carries invalid param\" + extra)\n assume (!bundle.denied || bundle.corrupt, \"'D' channel AccessAckData is denied but not corrupt\" + extra)\n assume (deny_get_ok || !bundle.denied, \"'D' channel AccessAckData is denied\" + extra)\n }\n\n when (bundle.opcode === TLMessages.HintAck) {\n assume (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n // size is ignored\n assume (bundle.param === 0.U, \"'D' channel HintAck carries invalid param\" + extra)\n assume (!bundle.corrupt, \"'D' channel HintAck is corrupt\" + extra)\n assume (deny_put_ok || !bundle.denied, \"'D' channel HintAck is denied\" + extra)\n }\n }\n\n def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {\n val sink_ok = bundle.sink < edge.manager.endSinkId.U\n monAssert (sink_ok, \"'E' channels carries invalid sink ID\" + extra)\n }\n\n def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {\n when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }\n when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }\n if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {\n when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }\n when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }\n when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }\n } else {\n monAssert (!bundle.b.valid, \"'B' channel valid and not TL-C\" + extra)\n monAssert (!bundle.c.valid, \"'C' channel valid and not TL-C\" + extra)\n monAssert (!bundle.e.valid, \"'E' channel valid and not TL-C\" + extra)\n }\n }\n\n def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {\n val a_first = edge.first(a.bits, a.fire)\n val opcode = Reg(UInt())\n val param = Reg(UInt())\n val size = Reg(UInt())\n val source = Reg(UInt())\n val address = Reg(UInt())\n when (a.valid && !a_first) {\n monAssert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n monAssert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n monAssert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n monAssert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n monAssert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n }\n when (a.fire && a_first) {\n opcode := a.bits.opcode\n param := a.bits.param\n size := a.bits.size\n source := a.bits.source\n address := a.bits.address\n }\n }\n\n def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {\n val b_first = edge.first(b.bits, b.fire)\n val opcode = Reg(UInt())\n val param = Reg(UInt())\n val size = Reg(UInt())\n val source = Reg(UInt())\n val address = Reg(UInt())\n when (b.valid && !b_first) {\n monAssert (b.bits.opcode === opcode, \"'B' channel opcode changed within multibeat operation\" + extra)\n monAssert (b.bits.param === param, \"'B' channel param changed within multibeat operation\" + extra)\n monAssert (b.bits.size === size, \"'B' channel size changed within multibeat operation\" + extra)\n monAssert (b.bits.source === source, \"'B' channel source changed within multibeat operation\" + extra)\n monAssert (b.bits.address=== address,\"'B' channel addresss changed with multibeat operation\" + extra)\n }\n when (b.fire && b_first) {\n opcode := b.bits.opcode\n param := b.bits.param\n size := b.bits.size\n source := b.bits.source\n address := b.bits.address\n }\n }\n\n def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {\n // Symbolic variable\n val sym_source = Wire(UInt(edge.client.endSourceId.W))\n // TODO: Connect sym_source to a fixed value for simulation and to a\n // free wire in formal\n sym_source := 0.U\n\n // Type casting Int to UInt\n val maxSourceId = Wire(UInt(edge.client.endSourceId.W))\n maxSourceId := edge.client.endSourceId.U\n\n // Delayed verison of sym_source\n val sym_source_d = Reg(UInt(edge.client.endSourceId.W))\n sym_source_d := sym_source\n\n // These will be constraints for FV setup\n Property(\n MonitorDirection.Monitor,\n (sym_source === sym_source_d),\n \"sym_source should remain stable\",\n PropertyClass.Default)\n Property(\n MonitorDirection.Monitor,\n (sym_source <= maxSourceId),\n \"sym_source should take legal value\",\n PropertyClass.Default)\n\n val my_resp_pend = RegInit(false.B)\n val my_opcode = Reg(UInt())\n val my_size = Reg(UInt())\n\n val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)\n val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)\n\n val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)\n val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)\n\n val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)\n val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)\n when (my_set_resp_pend) {\n my_resp_pend := true.B\n } .elsewhen (my_clr_resp_pend) {\n my_resp_pend := false.B\n }\n\n when (my_a_first_beat) {\n my_opcode := bundle.a.bits.opcode\n my_size := bundle.a.bits.size\n }\n\n val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)\n val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)\n\n val my_resp_opcode_legal = Wire(Bool())\n when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||\n (my_resp_opcode === TLMessages.LogicalData)) {\n my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)\n } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {\n my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)\n } .otherwise {\n my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)\n }\n\n monAssert (IfThen(my_resp_pend, !my_a_first_beat),\n \"Request message should not be sent with a source ID, for which a response message\" +\n \"is already pending (not received until current cycle) for a prior request message\" +\n \"with the same source ID\" + extra)\n\n assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),\n \"Response message should be accepted with a source ID only if a request message with the\" +\n \"same source ID has been accepted or is being accepted in the current cycle\" + extra)\n assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),\n \"Response message should be sent with a source ID only if a request message with the\" +\n \"same source ID has been accepted or is being sent in the current cycle\" + extra)\n assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),\n \"If d_valid is 1, then d_size should be same as a_size of the corresponding request\" +\n \"message\" + extra)\n assume (IfThen(my_d_first_beat, my_resp_opcode_legal),\n \"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding\" +\n \"request message\" + extra)\n }\n\n def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {\n val c_first = edge.first(c.bits, c.fire)\n val opcode = Reg(UInt())\n val param = Reg(UInt())\n val size = Reg(UInt())\n val source = Reg(UInt())\n val address = Reg(UInt())\n when (c.valid && !c_first) {\n monAssert (c.bits.opcode === opcode, \"'C' channel opcode changed within multibeat operation\" + extra)\n monAssert (c.bits.param === param, \"'C' channel param changed within multibeat operation\" + extra)\n monAssert (c.bits.size === size, \"'C' channel size changed within multibeat operation\" + extra)\n monAssert (c.bits.source === source, \"'C' channel source changed within multibeat operation\" + extra)\n monAssert (c.bits.address=== address,\"'C' channel address changed with multibeat operation\" + extra)\n }\n when (c.fire && c_first) {\n opcode := c.bits.opcode\n param := c.bits.param\n size := c.bits.size\n source := c.bits.source\n address := c.bits.address\n }\n }\n\n def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {\n val d_first = edge.first(d.bits, d.fire)\n val opcode = Reg(UInt())\n val param = Reg(UInt())\n val size = Reg(UInt())\n val source = Reg(UInt())\n val sink = Reg(UInt())\n val denied = Reg(Bool())\n when (d.valid && !d_first) {\n assume (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n assume (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n assume (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n assume (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n assume (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n assume (d.bits.denied === denied, \"'D' channel denied changed with multibeat operation\" + extra)\n }\n when (d.fire && d_first) {\n opcode := d.bits.opcode\n param := d.bits.param\n size := d.bits.size\n source := d.bits.source\n sink := d.bits.sink\n denied := d.bits.denied\n }\n }\n\n def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {\n legalizeMultibeatA(bundle.a, edge)\n legalizeMultibeatD(bundle.d, edge)\n if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {\n legalizeMultibeatB(bundle.b, edge)\n legalizeMultibeatC(bundle.c, edge)\n }\n }\n\n //This is left in for almond which doesn't adhere to the tilelink protocol\n @deprecated(\"Use legalizeADSource instead if possible\",\"\")\n def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {\n val inflight = RegInit(0.U(edge.client.endSourceId.W))\n\n val a_first = edge.first(bundle.a.bits, bundle.a.fire)\n val d_first = edge.first(bundle.d.bits, bundle.d.fire)\n\n val a_set = WireInit(0.U(edge.client.endSourceId.W))\n when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {\n a_set := UIntToOH(bundle.a.bits.source)\n assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n }\n\n val d_clr = WireInit(0.U(edge.client.endSourceId.W))\n val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck\n when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {\n d_clr := UIntToOH(bundle.d.bits.source)\n assume((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n }\n\n if (edge.manager.minLatency > 0) {\n assume(a_set =/= d_clr || !a_set.orR, s\"'A' and 'D' concurrent, despite minlatency > 0\" + extra)\n }\n\n inflight := (inflight | a_set) & ~d_clr\n\n val watchdog = RegInit(0.U(32.W))\n val limit = PlusArg(\"tilelink_timeout\",\n docstring=\"Kill emulation after INT waiting TileLink cycles. Off if 0.\")\n assert (!inflight.orR || limit === 0.U || watchdog < limit, \"TileLink timeout expired\" + extra)\n\n watchdog := watchdog + 1.U\n when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }\n }\n\n def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {\n val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)\n val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything\n val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)\n val log_a_size_bus_size = log2Ceil(a_size_bus_size)\n def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits\n\n val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error\n inflight.suggestName(\"inflight\")\n val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))\n inflight_opcodes.suggestName(\"inflight_opcodes\")\n val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))\n inflight_sizes.suggestName(\"inflight_sizes\")\n\n val a_first = edge.first(bundle.a.bits, bundle.a.fire)\n a_first.suggestName(\"a_first\")\n val d_first = edge.first(bundle.d.bits, bundle.d.fire)\n d_first.suggestName(\"d_first\")\n\n val a_set = WireInit(0.U(edge.client.endSourceId.W))\n val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))\n a_set.suggestName(\"a_set\")\n a_set_wo_ready.suggestName(\"a_set_wo_ready\")\n val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))\n a_opcodes_set.suggestName(\"a_opcodes_set\")\n val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))\n a_sizes_set.suggestName(\"a_sizes_set\")\n\n val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))\n a_opcode_lookup.suggestName(\"a_opcode_lookup\")\n a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U\n\n val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))\n a_size_lookup.suggestName(\"a_size_lookup\")\n a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U\n\n val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))\n val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))\n\n val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))\n a_opcodes_set_interm.suggestName(\"a_opcodes_set_interm\")\n val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))\n a_sizes_set_interm.suggestName(\"a_sizes_set_interm\")\n\n when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {\n a_set_wo_ready := UIntToOH(bundle.a.bits.source)\n }\n\n when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {\n a_set := UIntToOH(bundle.a.bits.source)\n a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U\n a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U\n a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)\n a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)\n monAssert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n }\n\n val d_clr = WireInit(0.U(edge.client.endSourceId.W))\n val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))\n d_clr.suggestName(\"d_clr\")\n d_clr_wo_ready.suggestName(\"d_clr_wo_ready\")\n val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))\n d_opcodes_clr.suggestName(\"d_opcodes_clr\")\n val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))\n d_sizes_clr.suggestName(\"d_sizes_clr\")\n\n val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck\n when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {\n d_clr_wo_ready := UIntToOH(bundle.d.bits.source)\n }\n\n when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {\n d_clr := UIntToOH(bundle.d.bits.source)\n d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)\n d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)\n }\n when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {\n val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)\n assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, \"'D' channel acknowledged for nothing inflight\" + extra)\n\n when (same_cycle_resp) {\n assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||\n (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), \"'D' channel contains improper opcode response\" + extra)\n assume((bundle.a.bits.size === bundle.d.bits.size), \"'D' channel contains improper response size\" + extra)\n } .otherwise {\n assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||\n (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), \"'D' channel contains improper opcode response\" + extra)\n assume((bundle.d.bits.size === a_size_lookup), \"'D' channel contains improper response size\" + extra)\n }\n }\n when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {\n assume((!bundle.d.ready) || bundle.a.ready, \"ready check\")\n }\n\n if (edge.manager.minLatency > 0) {\n assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s\"'A' and 'D' concurrent, despite minlatency > 0\" + extra)\n }\n\n inflight := (inflight | a_set) & ~d_clr\n inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr\n inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr\n\n val watchdog = RegInit(0.U(32.W))\n val limit = PlusArg(\"tilelink_timeout\",\n docstring=\"Kill emulation after INT waiting TileLink cycles. Off if 0.\")\n monAssert (!inflight.orR || limit === 0.U || watchdog < limit, \"TileLink timeout expired\" + extra)\n\n watchdog := watchdog + 1.U\n when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }\n }\n\n def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {\n val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)\n val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything\n\n val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)\n val log_c_size_bus_size = log2Ceil(c_size_bus_size)\n def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits\n\n val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))\n val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))\n val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))\n inflight.suggestName(\"inflight\")\n inflight_opcodes.suggestName(\"inflight_opcodes\")\n inflight_sizes.suggestName(\"inflight_sizes\")\n\n val c_first = edge.first(bundle.c.bits, bundle.c.fire)\n val d_first = edge.first(bundle.d.bits, bundle.d.fire)\n c_first.suggestName(\"c_first\")\n d_first.suggestName(\"d_first\")\n\n val c_set = WireInit(0.U(edge.client.endSourceId.W))\n val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))\n val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))\n val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))\n c_set.suggestName(\"c_set\")\n c_set_wo_ready.suggestName(\"c_set_wo_ready\")\n c_opcodes_set.suggestName(\"c_opcodes_set\")\n c_sizes_set.suggestName(\"c_sizes_set\")\n\n val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))\n val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))\n c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U\n c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U\n c_opcode_lookup.suggestName(\"c_opcode_lookup\")\n c_size_lookup.suggestName(\"c_size_lookup\")\n\n val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))\n val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))\n c_opcodes_set_interm.suggestName(\"c_opcodes_set_interm\")\n c_sizes_set_interm.suggestName(\"c_sizes_set_interm\")\n\n when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {\n c_set_wo_ready := UIntToOH(bundle.c.bits.source)\n }\n\n when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {\n c_set := UIntToOH(bundle.c.bits.source)\n c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U\n c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U\n c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)\n c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)\n monAssert(!inflight(bundle.c.bits.source), \"'C' channel re-used a source ID\" + extra)\n }\n\n val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData\n\n val d_clr = WireInit(0.U(edge.client.endSourceId.W))\n val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))\n val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))\n val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))\n d_clr.suggestName(\"d_clr\")\n d_clr_wo_ready.suggestName(\"d_clr_wo_ready\")\n d_opcodes_clr.suggestName(\"d_opcodes_clr\")\n d_sizes_clr.suggestName(\"d_sizes_clr\")\n\n val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck\n when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {\n d_clr_wo_ready := UIntToOH(bundle.d.bits.source)\n }\n\n when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {\n d_clr := UIntToOH(bundle.d.bits.source)\n d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)\n d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)\n }\n\n when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {\n val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)\n assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, \"'D' channel acknowledged for nothing inflight\" + extra)\n when (same_cycle_resp) {\n assume((bundle.d.bits.size === bundle.c.bits.size), \"'D' channel contains improper response size\" + extra)\n } .otherwise {\n assume((bundle.d.bits.size === c_size_lookup), \"'D' channel contains improper response size\" + extra)\n }\n }\n\n when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {\n assume((!bundle.d.ready) || bundle.c.ready, \"ready check\")\n }\n\n if (edge.manager.minLatency > 0) {\n when (c_set_wo_ready.orR) {\n assume(c_set_wo_ready =/= d_clr_wo_ready, s\"'C' and 'D' concurrent, despite minlatency > 0\" + extra)\n }\n }\n\n inflight := (inflight | c_set) & ~d_clr\n inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr\n inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr\n\n val watchdog = RegInit(0.U(32.W))\n val limit = PlusArg(\"tilelink_timeout\",\n docstring=\"Kill emulation after INT waiting TileLink cycles. Off if 0.\")\n monAssert (!inflight.orR || limit === 0.U || watchdog < limit, \"TileLink timeout expired\" + extra)\n\n watchdog := watchdog + 1.U\n when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }\n }\n\n def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {\n val inflight = RegInit(0.U(edge.manager.endSinkId.W))\n\n val d_first = edge.first(bundle.d.bits, bundle.d.fire)\n val e_first = true.B\n\n val d_set = WireInit(0.U(edge.manager.endSinkId.W))\n when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {\n d_set := UIntToOH(bundle.d.bits.sink)\n assume(!inflight(bundle.d.bits.sink), \"'D' channel re-used a sink ID\" + extra)\n }\n\n val e_clr = WireInit(0.U(edge.manager.endSinkId.W))\n when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {\n e_clr := UIntToOH(bundle.e.bits.sink)\n monAssert((d_set | inflight)(bundle.e.bits.sink), \"'E' channel acknowledged for nothing inflight\" + extra)\n }\n\n // edge.client.minLatency applies to BC, not DE\n\n inflight := (inflight | d_set) & ~e_clr\n }\n\n def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {\n val sourceBits = log2Ceil(edge.client.endSourceId)\n val tooBig = 14 // >16kB worth of flight information gets to be too much\n if (sourceBits > tooBig) {\n println(s\"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked\")\n } else {\n if (args.edge.params(TestplanTestType).simulation) {\n if (args.edge.params(TLMonitorStrictMode)) {\n legalizeADSource(bundle, edge)\n legalizeCDSource(bundle, edge)\n } else {\n legalizeADSourceOld(bundle, edge)\n }\n }\n if (args.edge.params(TestplanTestType).formal) {\n legalizeADSourceFormal(bundle, edge)\n }\n }\n if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {\n // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...\n val sinkBits = log2Ceil(edge.manager.endSinkId)\n if (sinkBits > tooBig) {\n println(s\"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked\")\n } else {\n legalizeDESink(bundle, edge)\n }\n }\n }\n\n def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {\n legalizeFormat (bundle, edge)\n legalizeMultibeat (bundle, edge)\n legalizeUnique (bundle, edge)\n }\n}\nFile Misc.scala:\n// See LICENSE.Berkeley for license details.\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.util.random.LFSR\nimport org.chipsalliance.cde.config.Parameters\nimport scala.math._\n\nclass ParameterizedBundle(implicit p: Parameters) extends Bundle\n\ntrait Clocked extends Bundle {\n val clock = Clock()\n val reset = Bool() \n}\n\nobject DecoupledHelper {\n def apply(rvs: Bool*) = new DecoupledHelper(rvs)\n}\n\nclass DecoupledHelper(val rvs: Seq[Bool]) {\n def fire(exclude: Bool, includes: Bool*) = {\n require(rvs.contains(exclude), \"Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!\")\n (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)\n }\n def fire() = {\n rvs.reduce(_ && _)\n }\n}\n\nobject MuxT {\n def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =\n (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))\n\n def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =\n (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))\n\n def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =\n (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))\n}\n\n/** Creates a cascade of n MuxTs to search for a key value. */\nobject MuxTLookup {\n def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {\n var res = default\n for ((k, v) <- mapping.reverse)\n res = MuxT(k === key, v, res)\n res\n }\n\n def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {\n var res = default\n for ((k, v) <- mapping.reverse)\n res = MuxT(k === key, v, res)\n res\n }\n}\n\nobject ValidMux {\n def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {\n apply(v1 +: v2.toSeq)\n }\n def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {\n val out = Wire(Valid(valids.head.bits.cloneType))\n out.valid := valids.map(_.valid).reduce(_ || _)\n out.bits := MuxCase(valids.head.bits,\n valids.map(v => (v.valid -> v.bits)))\n out\n }\n}\n\nobject Str\n{\n def apply(s: String): UInt = {\n var i = BigInt(0)\n require(s.forall(validChar _))\n for (c <- s)\n i = (i << 8) | c\n i.U((s.length*8).W)\n }\n def apply(x: Char): UInt = {\n require(validChar(x))\n x.U(8.W)\n }\n def apply(x: UInt): UInt = apply(x, 10)\n def apply(x: UInt, radix: Int): UInt = {\n val rad = radix.U\n val w = x.getWidth\n require(w > 0)\n\n var q = x\n var s = digit(q % rad)\n for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {\n q = q / rad\n s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)\n }\n s\n }\n def apply(x: SInt): UInt = apply(x, 10)\n def apply(x: SInt, radix: Int): UInt = {\n val neg = x < 0.S\n val abs = x.abs.asUInt\n if (radix != 10) {\n Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))\n } else {\n val rad = radix.U\n val w = abs.getWidth\n require(w > 0)\n\n var q = abs\n var s = digit(q % rad)\n var needSign = neg\n for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {\n q = q / rad\n val placeSpace = q === 0.U\n val space = Mux(needSign, Str('-'), Str(' '))\n needSign = needSign && !placeSpace\n s = Cat(Mux(placeSpace, space, digit(q % rad)), s)\n }\n Cat(Mux(needSign, Str('-'), Str(' ')), s)\n }\n }\n\n private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)\n private def validChar(x: Char) = x == (x & 0xFF)\n}\n\nobject Split\n{\n def apply(x: UInt, n0: Int) = {\n val w = x.getWidth\n (x.extract(w-1,n0), x.extract(n0-1,0))\n }\n def apply(x: UInt, n1: Int, n0: Int) = {\n val w = x.getWidth\n (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))\n }\n def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {\n val w = x.getWidth\n (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))\n }\n}\n\nobject Random\n{\n def apply(mod: Int, random: UInt): UInt = {\n if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)\n else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))\n }\n def apply(mod: Int): UInt = apply(mod, randomizer)\n def oneHot(mod: Int, random: UInt): UInt = {\n if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))\n else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt\n }\n def oneHot(mod: Int): UInt = oneHot(mod, randomizer)\n\n private def randomizer = LFSR(16)\n private def partition(value: UInt, slices: Int) =\n Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)\n}\n\nobject Majority {\n def apply(in: Set[Bool]): Bool = {\n val n = (in.size >> 1) + 1\n val clauses = in.subsets(n).map(_.reduce(_ && _))\n clauses.reduce(_ || _)\n }\n\n def apply(in: Seq[Bool]): Bool = apply(in.toSet)\n\n def apply(in: UInt): Bool = apply(in.asBools.toSet)\n}\n\nobject PopCountAtLeast {\n private def two(x: UInt): (Bool, Bool) = x.getWidth match {\n case 1 => (x.asBool, false.B)\n case n =>\n val half = x.getWidth / 2\n val (leftOne, leftTwo) = two(x(half - 1, 0))\n val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))\n (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))\n }\n def apply(x: UInt, n: Int): Bool = n match {\n case 0 => true.B\n case 1 => x.orR\n case 2 => two(x)._2\n case 3 => PopCount(x) >= n.U\n }\n}\n\n// This gets used everywhere, so make the smallest circuit possible ...\n// Given an address and size, create a mask of beatBytes size\n// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111\n// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01\nobject MaskGen {\n def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {\n require (groupBy >= 1 && beatBytes >= groupBy)\n require (isPow2(beatBytes) && isPow2(groupBy))\n val lgBytes = log2Ceil(beatBytes)\n val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U\n\n def helper(i: Int): Seq[(Bool, Bool)] = {\n if (i == 0) {\n Seq((lgSize >= lgBytes.asUInt, true.B))\n } else {\n val sub = helper(i-1)\n val size = sizeOH(lgBytes - i)\n val bit = addr_lo(lgBytes - i)\n val nbit = !bit\n Seq.tabulate (1 << i) { j =>\n val (sub_acc, sub_eq) = sub(j/2)\n val eq = sub_eq && (if (j % 2 == 1) bit else nbit)\n val acc = sub_acc || (size && eq)\n (acc, eq)\n }\n }\n }\n\n if (groupBy == beatBytes) 1.U else\n Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)\n }\n}\nFile PlusArg.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3._\nimport chisel3.experimental._\nimport chisel3.util.HasBlackBoxResource\n\n@deprecated(\"This will be removed in Rocket Chip 2020.08\", \"Rocket Chip 2020.05\")\ncase class PlusArgInfo(default: BigInt, docstring: String)\n\n/** Case class for PlusArg information\n *\n * @tparam A scala type of the PlusArg value\n * @param default optional default value\n * @param docstring text to include in the help\n * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)\n */\nprivate case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)\n\n/** Typeclass for converting a type to a doctype string\n * @tparam A some type\n */\ntrait Doctypeable[A] {\n\n /** Return the doctype string for some option */\n def toDoctype(a: Option[A]): String\n\n}\n\n/** Object containing implementations of the Doctypeable typeclass */\nobject Doctypes {\n\n /** Converts an Int => \"INT\" */\n implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = \"INT\" }\n\n /** Converts a BigInt => \"INT\" */\n implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = \"INT\" }\n\n /** Converts a String => \"STRING\" */\n implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = \"STRING\" }\n\n}\n\nclass plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(\n \"FORMAT\" -> StringParam(format),\n \"DEFAULT\" -> IntParam(default),\n \"WIDTH\" -> IntParam(width)\n )) with HasBlackBoxResource {\n val io = IO(new Bundle {\n val out = Output(UInt(width.W))\n })\n\n addResource(\"/vsrc/plusarg_reader.v\")\n}\n\n/* This wrapper class has no outputs, making it clear it is a simulation-only construct */\nclass PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {\n val io = IO(new Bundle {\n val count = Input(UInt(width.W))\n })\n val max = Module(new plusarg_reader(format, default, docstring, width)).io.out\n when (max > 0.U) {\n assert (io.count < max, s\"Timeout exceeded: $docstring\")\n }\n}\n\nimport Doctypes._\n\nobject PlusArg\n{\n /** PlusArg(\"foo\") will return 42.U if the simulation is run with +foo=42\n * Do not use this as an initial register value. The value is set in an\n * initial block and thus accessing it from another initial is racey.\n * Add a docstring to document the arg, which can be dumped in an elaboration\n * pass.\n */\n def apply(name: String, default: BigInt = 0, docstring: String = \"\", width: Int = 32): UInt = {\n PlusArgArtefacts.append(name, Some(default), docstring)\n Module(new plusarg_reader(name + \"=%d\", default, docstring, width)).io.out\n }\n\n /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert\n * to kill the simulation when count exceeds the specified integer argument.\n * Default 0 will never assert.\n */\n def timeout(name: String, default: BigInt = 0, docstring: String = \"\", width: Int = 32)(count: UInt): Unit = {\n PlusArgArtefacts.append(name, Some(default), docstring)\n Module(new PlusArgTimeout(name + \"=%d\", default, docstring, width)).io.count := count\n }\n}\n\nobject PlusArgArtefacts {\n private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty\n\n /* Add a new PlusArg */\n @deprecated(\n \"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08\",\n \"Rocket Chip 2020.05\"\n )\n def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)\n\n /** Add a new PlusArg\n *\n * @tparam A scala type of the PlusArg value\n * @param name name for the PlusArg\n * @param default optional default value\n * @param docstring text to include in the help\n */\n def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =\n artefacts = artefacts ++\n Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))\n\n /* From plus args, generate help text */\n private def serializeHelp_cHeader(tab: String = \"\"): String = artefacts\n .map{ case(arg, info) =>\n s\"\"\"|$tab+$arg=${info.doctype}\\\\n\\\\\n |$tab${\" \"*20}${info.docstring}\\\\n\\\\\n |\"\"\".stripMargin ++ info.default.map{ case default =>\n s\"$tab${\" \"*22}(default=${default})\\\\n\\\\\\n\"}.getOrElse(\"\")\n }.toSeq.mkString(\"\\\\n\\\\\\n\") ++ \"\\\"\"\n\n /* From plus args, generate a char array of their names */\n private def serializeArray_cHeader(tab: String = \"\"): String = {\n val prettyTab = tab + \" \" * 44 // Length of 'static const ...'\n s\"${tab}static const char * verilog_plusargs [] = {\\\\\\n\" ++\n artefacts\n .map{ case(arg, _) => s\"\"\"$prettyTab\"$arg\",\\\\\\n\"\"\" }\n .mkString(\"\")++\n s\"${prettyTab}0};\"\n }\n\n /* Generate C code to be included in emulator.cc that helps with\n * argument parsing based on available Verilog PlusArgs */\n def serialize_cHeader(): String =\n s\"\"\"|#define PLUSARG_USAGE_OPTIONS \\\"EMULATOR VERILOG PLUSARGS\\\\n\\\\\n |${serializeHelp_cHeader(\" \"*7)}\n |${serializeArray_cHeader()}\n |\"\"\".stripMargin\n}\nFile package.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip\n\nimport chisel3._\nimport chisel3.util._\nimport scala.math.min\nimport scala.collection.{immutable, mutable}\n\npackage object util {\n implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {\n def unzip = (x.map(_._1), x.map(_._2))\n }\n\n implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {\n def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR\n \n def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)\n }\n\n implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {\n\n /** Like Vec.apply(idx), but tolerates indices of mismatched width */\n def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))\n }\n\n implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {\n def apply(idx: UInt): T = {\n if (x.size <= 1) {\n x.head\n } else if (!isPow2(x.size)) {\n // For non-power-of-2 seqs, reflect elements to simplify decoder\n (x ++ x.takeRight(x.size & -x.size)).toSeq(idx)\n } else {\n // Ignore MSBs of idx\n val truncIdx =\n if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx\n else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)\n x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }\n }\n }\n\n def extract(idx: UInt): T = VecInit(x).extract(idx)\n\n def asUInt: UInt = Cat(x.map(_.asUInt).reverse)\n\n def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)\n\n def rotate(n: UInt): Seq[T] = {\n if (x.size <= 1) {\n x\n } else {\n require(isPow2(x.size))\n val amt = n.padTo(log2Ceil(x.size))\n (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })\n }\n }\n\n def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)\n\n def rotateRight(n: UInt): Seq[T] = {\n if (x.size <= 1) {\n x\n } else {\n require(isPow2(x.size))\n val amt = n.padTo(log2Ceil(x.size))\n (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })\n }\n }\n }\n\n // allow bitwise ops on Seq[Bool] just like UInt\n implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {\n def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }\n def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }\n def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }\n def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x\n def >> (n: Int): Seq[Bool] = x drop n\n def unary_~ : Seq[Bool] = x.map(!_)\n def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)\n def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)\n def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)\n\n private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)\n }\n\n implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {\n def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))\n\n def getElements: Seq[Element] = x match {\n case e: Element => Seq(e)\n case a: Aggregate => a.getElements.flatMap(_.getElements)\n }\n }\n\n /** Any Data subtype that has a Bool member named valid. */\n type DataCanBeValid = Data { val valid: Bool }\n\n implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {\n def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)\n }\n\n implicit class StringToAugmentedString(private val x: String) extends AnyVal {\n /** converts from camel case to to underscores, also removing all spaces */\n def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + \"\") getOrElse \"\") {\n case (acc, c) if c.isUpper => acc + \"_\" + c.toLower\n case (acc, c) if c == ' ' => acc\n case (acc, c) => acc + c\n }\n\n /** converts spaces or underscores to hyphens, also lowering case */\n def kebab: String = x.toLowerCase map {\n case ' ' => '-'\n case '_' => '-'\n case c => c\n }\n\n def named(name: Option[String]): String = {\n x + name.map(\"_named_\" + _ ).getOrElse(\"_with_no_name\")\n }\n\n def named(name: String): String = named(Some(name))\n }\n\n implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)\n implicit def wcToUInt(c: WideCounter): UInt = c.value\n\n implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {\n def sextTo(n: Int): UInt = {\n require(x.getWidth <= n)\n if (x.getWidth == n) x\n else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)\n }\n\n def padTo(n: Int): UInt = {\n require(x.getWidth <= n)\n if (x.getWidth == n) x\n else Cat(0.U((n - x.getWidth).W), x)\n }\n\n // shifts left by n if n >= 0, or right by -n if n < 0\n def << (n: SInt): UInt = {\n val w = n.getWidth - 1\n require(w <= 30)\n\n val shifted = x << n(w-1, 0)\n Mux(n(w), shifted >> (1 << w), shifted)\n }\n\n // shifts right by n if n >= 0, or left by -n if n < 0\n def >> (n: SInt): UInt = {\n val w = n.getWidth - 1\n require(w <= 30)\n\n val shifted = x << (1 << w) >> n(w-1, 0)\n Mux(n(w), shifted, shifted >> (1 << w))\n }\n\n // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts\n def extract(hi: Int, lo: Int): UInt = {\n require(hi >= lo-1)\n if (hi == lo-1) 0.U\n else x(hi, lo)\n }\n\n // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts\n def extractOption(hi: Int, lo: Int): Option[UInt] = {\n require(hi >= lo-1)\n if (hi == lo-1) None\n else Some(x(hi, lo))\n }\n\n // like x & ~y, but first truncate or zero-extend y to x's width\n def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))\n\n def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)\n\n def rotateRight(n: UInt): UInt = {\n if (x.getWidth <= 1) {\n x\n } else {\n val amt = n.padTo(log2Ceil(x.getWidth))\n (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))\n }\n }\n\n def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))\n\n def rotateLeft(n: UInt): UInt = {\n if (x.getWidth <= 1) {\n x\n } else {\n val amt = n.padTo(log2Ceil(x.getWidth))\n (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))\n }\n }\n\n // compute (this + y) % n, given (this < n) and (y < n)\n def addWrap(y: UInt, n: Int): UInt = {\n val z = x +& y\n if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)\n }\n\n // compute (this - y) % n, given (this < n) and (y < n)\n def subWrap(y: UInt, n: Int): UInt = {\n val z = x -& y\n if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)\n }\n\n def grouped(width: Int): Seq[UInt] =\n (0 until x.getWidth by width).map(base => x(base + width - 1, base))\n\n def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds\n\n def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)\n\n // Like >=, but prevents x-prop for ('x >= 0)\n def >== (y: UInt): Bool = x >= y || y === 0.U\n }\n\n implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {\n def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)\n def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)\n }\n\n implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {\n def toInt: Int = if (x) 1 else 0\n\n // this one's snagged from scalaz\n def option[T](z: => T): Option[T] = if (x) Some(z) else None\n }\n\n implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {\n // exact log2\n def log2: Int = {\n require(isPow2(x))\n log2Ceil(x)\n }\n }\n\n def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)\n def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))\n def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)\n def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)\n\n def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None\n\n // Fill 1s from low bits to high bits\n def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)\n def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {\n val stop = min(width, cap)\n def helper(s: Int, x: UInt): UInt =\n if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))\n helper(1, x)(width-1, 0)\n }\n\n // Fill 1s form high bits to low bits\n def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)\n def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {\n val stop = min(width, cap)\n def helper(s: Int, x: UInt): UInt =\n if (s >= stop) x else helper(s+s, x | (x >> s))\n helper(1, x)(width-1, 0)\n }\n\n def OptimizationBarrier[T <: Data](in: T): T = {\n val barrier = Module(new Module {\n val io = IO(new Bundle {\n val x = Input(chiselTypeOf(in))\n val y = Output(chiselTypeOf(in))\n })\n io.y := io.x\n override def desiredName = s\"OptimizationBarrier_${in.typeName}\"\n })\n barrier.io.x := in\n barrier.io.y\n }\n\n /** Similar to Seq.groupBy except this returns a Seq instead of a Map\n * Useful for deterministic code generation\n */\n def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {\n val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]\n for (x <- xs) {\n val key = f(x)\n val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])\n l += x\n }\n map.view.map({ case (k, vs) => k -> vs.toList }).toList\n }\n\n def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {\n case 1 => List.fill(n)(in.head)\n case x if x == n => in\n case _ => throw new Exception(s\"must provide exactly 1 or $n of some field, but got:\\n$in\")\n }\n\n // HeterogeneousBag moved to standalond diplomacy\n @deprecated(\"HeterogeneousBag has been absorbed into standalone diplomacy library\", \"rocketchip 2.0.0\")\n def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)\n @deprecated(\"HeterogeneousBag has been absorbed into standalone diplomacy library\", \"rocketchip 2.0.0\")\n val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag\n}\nFile Bundles.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.tilelink\n\nimport chisel3._\nimport freechips.rocketchip.util._\nimport scala.collection.immutable.ListMap\nimport chisel3.util.Decoupled\nimport chisel3.util.DecoupledIO\nimport chisel3.reflect.DataMirror\n\nabstract class TLBundleBase(val params: TLBundleParameters) extends Bundle\n\n// common combos in lazy policy:\n// Put + Acquire\n// Release + AccessAck\n\nobject TLMessages\n{\n // A B C D E\n def PutFullData = 0.U // . . => AccessAck\n def PutPartialData = 1.U // . . => AccessAck\n def ArithmeticData = 2.U // . . => AccessAckData\n def LogicalData = 3.U // . . => AccessAckData\n def Get = 4.U // . . => AccessAckData\n def Hint = 5.U // . . => HintAck\n def AcquireBlock = 6.U // . => Grant[Data]\n def AcquirePerm = 7.U // . => Grant[Data]\n def Probe = 6.U // . => ProbeAck[Data]\n def AccessAck = 0.U // . .\n def AccessAckData = 1.U // . .\n def HintAck = 2.U // . .\n def ProbeAck = 4.U // .\n def ProbeAckData = 5.U // .\n def Release = 6.U // . => ReleaseAck\n def ReleaseData = 7.U // . => ReleaseAck\n def Grant = 4.U // . => GrantAck\n def GrantData = 5.U // . => GrantAck\n def ReleaseAck = 6.U // .\n def GrantAck = 0.U // .\n\n def isA(x: UInt) = x <= AcquirePerm\n def isB(x: UInt) = x <= Probe\n def isC(x: UInt) = x <= ReleaseData\n def isD(x: UInt) = x <= ReleaseAck\n\n def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant)\n def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck)\n\n def a = Seq( (\"PutFullData\",TLPermissions.PermMsgReserved),\n (\"PutPartialData\",TLPermissions.PermMsgReserved),\n (\"ArithmeticData\",TLAtomics.ArithMsg),\n (\"LogicalData\",TLAtomics.LogicMsg),\n (\"Get\",TLPermissions.PermMsgReserved),\n (\"Hint\",TLHints.HintsMsg),\n (\"AcquireBlock\",TLPermissions.PermMsgGrow),\n (\"AcquirePerm\",TLPermissions.PermMsgGrow))\n\n def b = Seq( (\"PutFullData\",TLPermissions.PermMsgReserved),\n (\"PutPartialData\",TLPermissions.PermMsgReserved),\n (\"ArithmeticData\",TLAtomics.ArithMsg),\n (\"LogicalData\",TLAtomics.LogicMsg),\n (\"Get\",TLPermissions.PermMsgReserved),\n (\"Hint\",TLHints.HintsMsg),\n (\"Probe\",TLPermissions.PermMsgCap))\n\n def c = Seq( (\"AccessAck\",TLPermissions.PermMsgReserved),\n (\"AccessAckData\",TLPermissions.PermMsgReserved),\n (\"HintAck\",TLPermissions.PermMsgReserved),\n (\"Invalid Opcode\",TLPermissions.PermMsgReserved),\n (\"ProbeAck\",TLPermissions.PermMsgReport),\n (\"ProbeAckData\",TLPermissions.PermMsgReport),\n (\"Release\",TLPermissions.PermMsgReport),\n (\"ReleaseData\",TLPermissions.PermMsgReport))\n\n def d = Seq( (\"AccessAck\",TLPermissions.PermMsgReserved),\n (\"AccessAckData\",TLPermissions.PermMsgReserved),\n (\"HintAck\",TLPermissions.PermMsgReserved),\n (\"Invalid Opcode\",TLPermissions.PermMsgReserved),\n (\"Grant\",TLPermissions.PermMsgCap),\n (\"GrantData\",TLPermissions.PermMsgCap),\n (\"ReleaseAck\",TLPermissions.PermMsgReserved))\n\n}\n\n/**\n * The three primary TileLink permissions are:\n * (T)runk: the agent is (or is on inwards path to) the global point of serialization.\n * (B)ranch: the agent is on an outwards path to\n * (N)one:\n * These permissions are permuted by transfer operations in various ways.\n * Operations can cap permissions, request for them to be grown or shrunk,\n * or for a report on their current status.\n */\nobject TLPermissions\n{\n val aWidth = 2\n val bdWidth = 2\n val cWidth = 3\n\n // Cap types (Grant = new permissions, Probe = permisions <= target)\n def toT = 0.U(bdWidth.W)\n def toB = 1.U(bdWidth.W)\n def toN = 2.U(bdWidth.W)\n def isCap(x: UInt) = x <= toN\n\n // Grow types (Acquire = permissions >= target)\n def NtoB = 0.U(aWidth.W)\n def NtoT = 1.U(aWidth.W)\n def BtoT = 2.U(aWidth.W)\n def isGrow(x: UInt) = x <= BtoT\n\n // Shrink types (ProbeAck, Release)\n def TtoB = 0.U(cWidth.W)\n def TtoN = 1.U(cWidth.W)\n def BtoN = 2.U(cWidth.W)\n def isShrink(x: UInt) = x <= BtoN\n\n // Report types (ProbeAck, Release)\n def TtoT = 3.U(cWidth.W)\n def BtoB = 4.U(cWidth.W)\n def NtoN = 5.U(cWidth.W)\n def isReport(x: UInt) = x <= NtoN\n\n def PermMsgGrow:Seq[String] = Seq(\"Grow NtoB\", \"Grow NtoT\", \"Grow BtoT\")\n def PermMsgCap:Seq[String] = Seq(\"Cap toT\", \"Cap toB\", \"Cap toN\")\n def PermMsgReport:Seq[String] = Seq(\"Shrink TtoB\", \"Shrink TtoN\", \"Shrink BtoN\", \"Report TotT\", \"Report BtoB\", \"Report NtoN\")\n def PermMsgReserved:Seq[String] = Seq(\"Reserved\")\n}\n\nobject TLAtomics\n{\n val width = 3\n\n // Arithmetic types\n def MIN = 0.U(width.W)\n def MAX = 1.U(width.W)\n def MINU = 2.U(width.W)\n def MAXU = 3.U(width.W)\n def ADD = 4.U(width.W)\n def isArithmetic(x: UInt) = x <= ADD\n\n // Logical types\n def XOR = 0.U(width.W)\n def OR = 1.U(width.W)\n def AND = 2.U(width.W)\n def SWAP = 3.U(width.W)\n def isLogical(x: UInt) = x <= SWAP\n\n def ArithMsg:Seq[String] = Seq(\"MIN\", \"MAX\", \"MINU\", \"MAXU\", \"ADD\")\n def LogicMsg:Seq[String] = Seq(\"XOR\", \"OR\", \"AND\", \"SWAP\")\n}\n\n\nobject TLHints\n{\n val width = 1\n\n def PREFETCH_READ = 0.U(width.W)\n def PREFETCH_WRITE = 1.U(width.W)\n def isHints(x: UInt) = x <= PREFETCH_WRITE\n\n def HintsMsg:Seq[String] = Seq(\"PrefetchRead\", \"PrefetchWrite\")\n}\n\nsealed trait TLChannel extends TLBundleBase {\n val channelName: String\n}\n\nsealed trait TLDataChannel extends TLChannel\nsealed trait TLAddrChannel extends TLDataChannel\n\nfinal class TLBundleA(params: TLBundleParameters)\n extends TLBundleBase(params) with TLAddrChannel\n{\n override def typeName = s\"TLBundleA_${params.shortName}\"\n val channelName = \"'A' channel\"\n // fixed fields during multibeat:\n val opcode = UInt(3.W)\n val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint\n val size = UInt(params.sizeBits.W)\n val source = UInt(params.sourceBits.W) // from\n val address = UInt(params.addressBits.W) // to\n val user = BundleMap(params.requestFields)\n val echo = BundleMap(params.echoFields)\n // variable fields during multibeat:\n val mask = UInt((params.dataBits/8).W)\n val data = UInt(params.dataBits.W)\n val corrupt = Bool() // only applies to *Data messages\n}\nfinal class TLBundleB(params: TLBundleParameters)\n extends TLBundleBase(params) with TLAddrChannel\n{\n override def typeName = s\"TLBundleB_${params.shortName}\"\n val channelName = \"'B' channel\"\n // fixed fields during multibeat:\n val opcode = UInt(3.W)\n val param = UInt(TLPermissions.bdWidth.W) // cap perms\n val size = UInt(params.sizeBits.W)\n val source = UInt(params.sourceBits.W) // to\n val address = UInt(params.addressBits.W) // from\n // variable fields during multibeat:\n val mask = UInt((params.dataBits/8).W)\n val data = UInt(params.dataBits.W)\n val corrupt = Bool() // only applies to *Data messages\n}\n\nfinal class TLBundleC(params: TLBundleParameters)\n extends TLBundleBase(params) with TLAddrChannel\n{\n override def typeName = s\"TLBundleC_${params.shortName}\"\n val channelName = \"'C' channel\"\n // fixed fields during multibeat:\n val opcode = UInt(3.W)\n val param = UInt(TLPermissions.cWidth.W) // shrink or report perms\n val size = UInt(params.sizeBits.W)\n val source = UInt(params.sourceBits.W) // from\n val address = UInt(params.addressBits.W) // to\n val user = BundleMap(params.requestFields)\n val echo = BundleMap(params.echoFields)\n // variable fields during multibeat:\n val data = UInt(params.dataBits.W)\n val corrupt = Bool() // only applies to *Data messages\n}\n\nfinal class TLBundleD(params: TLBundleParameters)\n extends TLBundleBase(params) with TLDataChannel\n{\n override def typeName = s\"TLBundleD_${params.shortName}\"\n val channelName = \"'D' channel\"\n // fixed fields during multibeat:\n val opcode = UInt(3.W)\n val param = UInt(TLPermissions.bdWidth.W) // cap perms\n val size = UInt(params.sizeBits.W)\n val source = UInt(params.sourceBits.W) // to\n val sink = UInt(params.sinkBits.W) // from\n val denied = Bool() // implies corrupt iff *Data\n val user = BundleMap(params.responseFields)\n val echo = BundleMap(params.echoFields)\n // variable fields during multibeat:\n val data = UInt(params.dataBits.W)\n val corrupt = Bool() // only applies to *Data messages\n}\n\nfinal class TLBundleE(params: TLBundleParameters)\n extends TLBundleBase(params) with TLChannel\n{\n override def typeName = s\"TLBundleE_${params.shortName}\"\n val channelName = \"'E' channel\"\n val sink = UInt(params.sinkBits.W) // to\n}\n\nclass TLBundle(val params: TLBundleParameters) extends Record\n{\n // Emulate a Bundle with elements abcde or ad depending on params.hasBCE\n\n private val optA = Some (Decoupled(new TLBundleA(params)))\n private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params))))\n private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params)))\n private val optD = Some (Flipped(Decoupled(new TLBundleD(params))))\n private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params)))\n\n def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params)))))\n def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params)))))\n def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params)))))\n def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params)))))\n def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params)))))\n\n val elements =\n if (params.hasBCE) ListMap(\"e\" -> e, \"d\" -> d, \"c\" -> c, \"b\" -> b, \"a\" -> a)\n else ListMap(\"d\" -> d, \"a\" -> a)\n\n def tieoff(): Unit = {\n DataMirror.specifiedDirectionOf(a.ready) match {\n case SpecifiedDirection.Input =>\n a.ready := false.B\n c.ready := false.B\n e.ready := false.B\n b.valid := false.B\n d.valid := false.B\n case SpecifiedDirection.Output =>\n a.valid := false.B\n c.valid := false.B\n e.valid := false.B\n b.ready := false.B\n d.ready := false.B\n case _ =>\n }\n }\n}\n\nobject TLBundle\n{\n def apply(params: TLBundleParameters) = new TLBundle(params)\n}\n\nclass TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle\n\nclass TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params)\n{\n val a = new AsyncBundle(new TLBundleA(params.base), params.async)\n val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async))\n val c = new AsyncBundle(new TLBundleC(params.base), params.async)\n val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async))\n val e = new AsyncBundle(new TLBundleE(params.base), params.async)\n}\n\nclass TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params)\n{\n val a = RationalIO(new TLBundleA(params))\n val b = Flipped(RationalIO(new TLBundleB(params)))\n val c = RationalIO(new TLBundleC(params))\n val d = Flipped(RationalIO(new TLBundleD(params)))\n val e = RationalIO(new TLBundleE(params))\n}\n\nclass TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params)\n{\n val a = CreditedIO(new TLBundleA(params))\n val b = Flipped(CreditedIO(new TLBundleB(params)))\n val c = CreditedIO(new TLBundleC(params))\n val d = Flipped(CreditedIO(new TLBundleD(params)))\n val e = CreditedIO(new TLBundleE(params))\n}\nFile Parameters.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.diplomacy\n\nimport chisel3._\nimport chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}\nimport freechips.rocketchip.util.ShiftQueue\n\n/** Options for describing the attributes of memory regions */\nobject RegionType {\n // Define the 'more relaxed than' ordering\n val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)\n sealed trait T extends Ordered[T] {\n def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)\n }\n\n case object CACHED extends T // an intermediate agent may have cached a copy of the region for you\n case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided\n case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible\n case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached\n case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects\n case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed\n case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively\n}\n\n// A non-empty half-open range; [start, end)\ncase class IdRange(start: Int, end: Int) extends Ordered[IdRange]\n{\n require (start >= 0, s\"Ids cannot be negative, but got: $start.\")\n require (start <= end, \"Id ranges cannot be negative.\")\n\n def compare(x: IdRange) = {\n val primary = (this.start - x.start).signum\n val secondary = (x.end - this.end).signum\n if (primary != 0) primary else secondary\n }\n\n def overlaps(x: IdRange) = start < x.end && x.start < end\n def contains(x: IdRange) = start <= x.start && x.end <= end\n\n def contains(x: Int) = start <= x && x < end\n def contains(x: UInt) =\n if (size == 0) {\n false.B\n } else if (size == 1) { // simple comparison\n x === start.U\n } else {\n // find index of largest different bit\n val largestDeltaBit = log2Floor(start ^ (end-1))\n val smallestCommonBit = largestDeltaBit + 1 // may not exist in x\n val uncommonMask = (1 << smallestCommonBit) - 1\n val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)\n // the prefix must match exactly (note: may shift ALL bits away)\n (x >> smallestCommonBit) === (start >> smallestCommonBit).U &&\n // firrtl constant prop range analysis can eliminate these two:\n (start & uncommonMask).U <= uncommonBits &&\n uncommonBits <= ((end-1) & uncommonMask).U\n }\n\n def shift(x: Int) = IdRange(start+x, end+x)\n def size = end - start\n def isEmpty = end == start\n\n def range = start until end\n}\n\nobject IdRange\n{\n def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {\n val ranges = s.sorted\n (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }\n }\n}\n\n// An potentially empty inclusive range of 2-powers [min, max] (in bytes)\ncase class TransferSizes(min: Int, max: Int)\n{\n def this(x: Int) = this(x, x)\n\n require (min <= max, s\"Min transfer $min > max transfer $max\")\n require (min >= 0 && max >= 0, s\"TransferSizes must be positive, got: ($min, $max)\")\n require (max == 0 || isPow2(max), s\"TransferSizes must be a power of 2, got: $max\")\n require (min == 0 || isPow2(min), s\"TransferSizes must be a power of 2, got: $min\")\n require (max == 0 || min != 0, s\"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)\")\n\n def none = min == 0\n def contains(x: Int) = isPow2(x) && min <= x && x <= max\n def containsLg(x: Int) = contains(1 << x)\n def containsLg(x: UInt) =\n if (none) false.B\n else if (min == max) { log2Ceil(min).U === x }\n else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }\n\n def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)\n\n def intersect(x: TransferSizes) =\n if (x.max < min || max < x.min) TransferSizes.none\n else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))\n\n // Not a union, because the result may contain sizes contained by neither term\n // NOT TO BE CONFUSED WITH COVERPOINTS\n def mincover(x: TransferSizes) = {\n if (none) {\n x\n } else if (x.none) {\n this\n } else {\n TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))\n }\n }\n\n override def toString() = \"TransferSizes[%d, %d]\".format(min, max)\n}\n\nobject TransferSizes {\n def apply(x: Int) = new TransferSizes(x)\n val none = new TransferSizes(0)\n\n def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)\n def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)\n\n implicit def asBool(x: TransferSizes) = !x.none\n}\n\n// AddressSets specify the address space managed by the manager\n// Base is the base address, and mask are the bits consumed by the manager\n// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff\n// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...\ncase class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]\n{\n // Forbid misaligned base address (and empty sets)\n require ((base & mask) == 0, s\"Mis-aligned AddressSets are forbidden, got: ${this.toString}\")\n require (base >= 0, s\"AddressSet negative base is ambiguous: $base\") // TL2 address widths are not fixed => negative is ambiguous\n // We do allow negative mask (=> ignore all high bits)\n\n def contains(x: BigInt) = ((x ^ base) & ~mask) == 0\n def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S\n\n // turn x into an address contained in this set\n def legalize(x: UInt): UInt = base.U | (mask.U & x)\n\n // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)\n def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0\n // contains iff bitwise: x.mask => mask && contains(x.base)\n def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0\n\n // The number of bytes to which the manager must be aligned\n def alignment = ((mask + 1) & ~mask)\n // Is this a contiguous memory range\n def contiguous = alignment == mask+1\n\n def finite = mask >= 0\n def max = { require (finite, \"Max cannot be calculated on infinite mask\"); base | mask }\n\n // Widen the match function to ignore all bits in imask\n def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)\n\n // Return an AddressSet that only contains the addresses both sets contain\n def intersect(x: AddressSet): Option[AddressSet] = {\n if (!overlaps(x)) {\n None\n } else {\n val r_mask = mask & x.mask\n val r_base = base | x.base\n Some(AddressSet(r_base, r_mask))\n }\n }\n\n def subtract(x: AddressSet): Seq[AddressSet] = {\n intersect(x) match {\n case None => Seq(this)\n case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>\n val nmask = (mask & (bit-1)) | remove.mask\n val nbase = (remove.base ^ bit) & ~nmask\n AddressSet(nbase, nmask)\n }\n }\n }\n\n // AddressSets have one natural Ordering (the containment order, if contiguous)\n def compare(x: AddressSet) = {\n val primary = (this.base - x.base).signum // smallest address first\n val secondary = (x.mask - this.mask).signum // largest mask first\n if (primary != 0) primary else secondary\n }\n\n // We always want to see things in hex\n override def toString() = {\n if (mask >= 0) {\n \"AddressSet(0x%x, 0x%x)\".format(base, mask)\n } else {\n \"AddressSet(0x%x, ~0x%x)\".format(base, ~mask)\n }\n }\n\n def toRanges = {\n require (finite, \"Ranges cannot be calculated on infinite mask\")\n val size = alignment\n val fragments = mask & ~(size-1)\n val bits = bitIndexes(fragments)\n (BigInt(0) until (BigInt(1) << bits.size)).map { i =>\n val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }\n AddressRange(off, size)\n }\n }\n}\n\nobject AddressSet\n{\n val everything = AddressSet(0, -1)\n def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {\n if (size == 0) tail.reverse else {\n val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)\n val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size\n val step =\n if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)\n maxSizeAlignment else maxBaseAlignment\n misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)\n }\n }\n\n def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {\n // Pair terms up by ignoring 'bit'\n seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>\n if (seq.size == 1) {\n seq.head // singleton -> unaffected\n } else {\n key.copy(mask = key.mask | bit) // pair - widen mask by bit\n }\n }.toList\n }\n\n def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {\n val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)\n AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted\n }\n\n def enumerateMask(mask: BigInt): Seq[BigInt] = {\n def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =\n if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)\n helper(0, Nil)\n }\n\n def enumerateBits(mask: BigInt): Seq[BigInt] = {\n def helper(x: BigInt): Seq[BigInt] = {\n if (x == 0) {\n Nil\n } else {\n val bit = x & (-x)\n bit +: helper(x & ~bit)\n }\n }\n helper(mask)\n }\n}\n\ncase class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)\n{\n require (depth >= 0, \"Buffer depth must be >= 0\")\n def isDefined = depth > 0\n def latency = if (isDefined && !flow) 1 else 0\n\n def apply[T <: Data](x: DecoupledIO[T]) =\n if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)\n else x\n\n def irrevocable[T <: Data](x: ReadyValidIO[T]) =\n if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)\n else x\n\n def sq[T <: Data](x: DecoupledIO[T]) =\n if (!isDefined) x else {\n val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))\n sq.io.enq <> x\n sq.io.deq\n }\n\n override def toString() = \"BufferParams:%d%s%s\".format(depth, if (flow) \"F\" else \"\", if (pipe) \"P\" else \"\")\n\n}\n\nobject BufferParams\n{\n implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)\n\n val default = BufferParams(2)\n val none = BufferParams(0)\n val flow = BufferParams(1, true, false)\n val pipe = BufferParams(1, false, true)\n}\n\ncase class TriStateValue(value: Boolean, set: Boolean)\n{\n def update(orig: Boolean) = if (set) value else orig\n}\n\nobject TriStateValue\n{\n implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)\n def unset = TriStateValue(false, false)\n}\n\ntrait DirectedBuffers[T] {\n def copyIn(x: BufferParams): T\n def copyOut(x: BufferParams): T\n def copyInOut(x: BufferParams): T\n}\n\ntrait IdMapEntry {\n def name: String\n def from: IdRange\n def to: IdRange\n def isCache: Boolean\n def requestFifo: Boolean\n def maxTransactionsInFlight: Option[Int]\n def pretty(fmt: String) =\n if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5\n fmt.format(to.start, to.end, from.start, from.end, s\"\"\"\"$name\"\"\"\", if (isCache) \" [CACHE]\" else \"\", if (requestFifo) \" [FIFO]\" else \"\")\n } else {\n fmt.format(from.start, from.end, s\"\"\"\"$name\"\"\"\", if (isCache) \" [CACHE]\" else \"\", if (requestFifo) \" [FIFO]\" else \"\")\n }\n}\n\nabstract class IdMap[T <: IdMapEntry] {\n protected val fmt: String\n val mapping: Seq[T]\n def pretty: String = mapping.map(_.pretty(fmt)).mkString(\",\\n\")\n}\nFile Edges.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.tilelink\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.experimental.SourceInfo\nimport org.chipsalliance.cde.config.Parameters\nimport freechips.rocketchip.util._\n\nclass TLEdge(\n client: TLClientPortParameters,\n manager: TLManagerPortParameters,\n params: Parameters,\n sourceInfo: SourceInfo)\n extends TLEdgeParameters(client, manager, params, sourceInfo)\n{\n def isAligned(address: UInt, lgSize: UInt): Bool = {\n if (maxLgSize == 0) true.B else {\n val mask = UIntToOH1(lgSize, maxLgSize)\n (address & mask) === 0.U\n }\n }\n\n def mask(address: UInt, lgSize: UInt): UInt =\n MaskGen(address, lgSize, manager.beatBytes)\n\n def staticHasData(bundle: TLChannel): Option[Boolean] = {\n bundle match {\n case _:TLBundleA => {\n // Do there exist A messages with Data?\n val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial\n // Do there exist A messages without Data?\n val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint\n // Statically optimize the case where hasData is a constant\n if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None\n }\n case _:TLBundleB => {\n // Do there exist B messages with Data?\n val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial\n // Do there exist B messages without Data?\n val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint\n // Statically optimize the case where hasData is a constant\n if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None\n }\n case _:TLBundleC => {\n // Do there eixst C messages with Data?\n val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe\n // Do there exist C messages without Data?\n val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe\n if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None\n }\n case _:TLBundleD => {\n // Do there eixst D messages with Data?\n val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB\n // Do there exist D messages without Data?\n val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT\n if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None\n }\n case _:TLBundleE => Some(false)\n }\n }\n\n def isRequest(x: TLChannel): Bool = {\n x match {\n case a: TLBundleA => true.B\n case b: TLBundleB => true.B\n case c: TLBundleC => c.opcode(2) && c.opcode(1)\n // opcode === TLMessages.Release ||\n // opcode === TLMessages.ReleaseData\n case d: TLBundleD => d.opcode(2) && !d.opcode(1)\n // opcode === TLMessages.Grant ||\n // opcode === TLMessages.GrantData\n case e: TLBundleE => false.B\n }\n }\n\n def isResponse(x: TLChannel): Bool = {\n x match {\n case a: TLBundleA => false.B\n case b: TLBundleB => false.B\n case c: TLBundleC => !c.opcode(2) || !c.opcode(1)\n // opcode =/= TLMessages.Release &&\n // opcode =/= TLMessages.ReleaseData\n case d: TLBundleD => true.B // Grant isResponse + isRequest\n case e: TLBundleE => true.B\n }\n }\n\n def hasData(x: TLChannel): Bool = {\n val opdata = x match {\n case a: TLBundleA => !a.opcode(2)\n // opcode === TLMessages.PutFullData ||\n // opcode === TLMessages.PutPartialData ||\n // opcode === TLMessages.ArithmeticData ||\n // opcode === TLMessages.LogicalData\n case b: TLBundleB => !b.opcode(2)\n // opcode === TLMessages.PutFullData ||\n // opcode === TLMessages.PutPartialData ||\n // opcode === TLMessages.ArithmeticData ||\n // opcode === TLMessages.LogicalData\n case c: TLBundleC => c.opcode(0)\n // opcode === TLMessages.AccessAckData ||\n // opcode === TLMessages.ProbeAckData ||\n // opcode === TLMessages.ReleaseData\n case d: TLBundleD => d.opcode(0)\n // opcode === TLMessages.AccessAckData ||\n // opcode === TLMessages.GrantData\n case e: TLBundleE => false.B\n }\n staticHasData(x).map(_.B).getOrElse(opdata)\n }\n\n def opcode(x: TLDataChannel): UInt = {\n x match {\n case a: TLBundleA => a.opcode\n case b: TLBundleB => b.opcode\n case c: TLBundleC => c.opcode\n case d: TLBundleD => d.opcode\n }\n }\n\n def param(x: TLDataChannel): UInt = {\n x match {\n case a: TLBundleA => a.param\n case b: TLBundleB => b.param\n case c: TLBundleC => c.param\n case d: TLBundleD => d.param\n }\n }\n\n def size(x: TLDataChannel): UInt = {\n x match {\n case a: TLBundleA => a.size\n case b: TLBundleB => b.size\n case c: TLBundleC => c.size\n case d: TLBundleD => d.size\n }\n }\n\n def data(x: TLDataChannel): UInt = {\n x match {\n case a: TLBundleA => a.data\n case b: TLBundleB => b.data\n case c: TLBundleC => c.data\n case d: TLBundleD => d.data\n }\n }\n\n def corrupt(x: TLDataChannel): Bool = {\n x match {\n case a: TLBundleA => a.corrupt\n case b: TLBundleB => b.corrupt\n case c: TLBundleC => c.corrupt\n case d: TLBundleD => d.corrupt\n }\n }\n\n def mask(x: TLAddrChannel): UInt = {\n x match {\n case a: TLBundleA => a.mask\n case b: TLBundleB => b.mask\n case c: TLBundleC => mask(c.address, c.size)\n }\n }\n\n def full_mask(x: TLAddrChannel): UInt = {\n x match {\n case a: TLBundleA => mask(a.address, a.size)\n case b: TLBundleB => mask(b.address, b.size)\n case c: TLBundleC => mask(c.address, c.size)\n }\n }\n\n def address(x: TLAddrChannel): UInt = {\n x match {\n case a: TLBundleA => a.address\n case b: TLBundleB => b.address\n case c: TLBundleC => c.address\n }\n }\n\n def source(x: TLDataChannel): UInt = {\n x match {\n case a: TLBundleA => a.source\n case b: TLBundleB => b.source\n case c: TLBundleC => c.source\n case d: TLBundleD => d.source\n }\n }\n\n def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)\n def addr_lo(x: UInt): UInt =\n if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)\n\n def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))\n def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))\n\n def numBeats(x: TLChannel): UInt = {\n x match {\n case _: TLBundleE => 1.U\n case bundle: TLDataChannel => {\n val hasData = this.hasData(bundle)\n val size = this.size(bundle)\n val cutoff = log2Ceil(manager.beatBytes)\n val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U\n val decode = UIntToOH(size, maxLgSize+1) >> cutoff\n Mux(hasData, decode | small.asUInt, 1.U)\n }\n }\n }\n\n def numBeats1(x: TLChannel): UInt = {\n x match {\n case _: TLBundleE => 0.U\n case bundle: TLDataChannel => {\n if (maxLgSize == 0) {\n 0.U\n } else {\n val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)\n Mux(hasData(bundle), decode, 0.U)\n }\n }\n }\n }\n\n def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {\n val beats1 = numBeats1(bits)\n val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))\n val counter1 = counter - 1.U\n val first = counter === 0.U\n val last = counter === 1.U || beats1 === 0.U\n val done = last && fire\n val count = (beats1 & ~counter1)\n when (fire) {\n counter := Mux(first, beats1, counter1)\n }\n (first, last, done, count)\n }\n\n def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1\n def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)\n def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)\n\n def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2\n def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)\n def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)\n\n def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3\n def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)\n def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)\n\n def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {\n val r = firstlastHelper(bits, fire)\n (r._1, r._2, r._3)\n }\n def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)\n def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)\n\n def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {\n val r = firstlastHelper(bits, fire)\n (r._1, r._2, r._3, r._4)\n }\n def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)\n def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)\n\n def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {\n val r = firstlastHelper(bits, fire)\n (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))\n }\n def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)\n def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)\n\n // Does the request need T permissions to be executed?\n def needT(a: TLBundleA): Bool = {\n val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(\n TLPermissions.NtoB -> false.B,\n TLPermissions.NtoT -> true.B,\n TLPermissions.BtoT -> true.B))\n MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(\n TLMessages.PutFullData -> true.B,\n TLMessages.PutPartialData -> true.B,\n TLMessages.ArithmeticData -> true.B,\n TLMessages.LogicalData -> true.B,\n TLMessages.Get -> false.B,\n TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(\n TLHints.PREFETCH_READ -> false.B,\n TLHints.PREFETCH_WRITE -> true.B)),\n TLMessages.AcquireBlock -> acq_needT,\n TLMessages.AcquirePerm -> acq_needT))\n }\n\n // This is a very expensive circuit; use only if you really mean it!\n def inFlight(x: TLBundle): (UInt, UInt) = {\n val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))\n val bce = manager.anySupportAcquireB && client.anySupportProbe\n\n val (a_first, a_last, _) = firstlast(x.a)\n val (b_first, b_last, _) = firstlast(x.b)\n val (c_first, c_last, _) = firstlast(x.c)\n val (d_first, d_last, _) = firstlast(x.d)\n val (e_first, e_last, _) = firstlast(x.e)\n\n val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))\n val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))\n val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))\n val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))\n val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))\n\n val a_inc = x.a.fire && a_first && a_request\n val b_inc = x.b.fire && b_first && b_request\n val c_inc = x.c.fire && c_first && c_request\n val d_inc = x.d.fire && d_first && d_request\n val e_inc = x.e.fire && e_first && e_request\n val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))\n\n val a_dec = x.a.fire && a_last && a_response\n val b_dec = x.b.fire && b_last && b_response\n val c_dec = x.c.fire && c_last && c_response\n val d_dec = x.d.fire && d_last && d_response\n val e_dec = x.e.fire && e_last && e_response\n val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))\n\n val next_flight = flight + PopCount(inc) - PopCount(dec)\n flight := next_flight\n\n (flight, next_flight)\n }\n\n def prettySourceMapping(context: String): String = {\n s\"TL-Source mapping for $context:\\n${(new TLSourceIdMap(client)).pretty}\\n\"\n }\n}\n\nclass TLEdgeOut(\n client: TLClientPortParameters,\n manager: TLManagerPortParameters,\n params: Parameters,\n sourceInfo: SourceInfo)\n extends TLEdge(client, manager, params, sourceInfo)\n{\n // Transfers\n def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {\n require (manager.anySupportAcquireB, s\"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsAcquireBFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.AcquireBlock\n a.param := growPermissions\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := DontCare\n a.corrupt := false.B\n (legal, a)\n }\n\n def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {\n require (manager.anySupportAcquireB, s\"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsAcquireBFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.AcquirePerm\n a.param := growPermissions\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := DontCare\n a.corrupt := false.B\n (legal, a)\n }\n\n def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {\n require (manager.anySupportAcquireB, s\"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsAcquireBFast(toAddress, lgSize)\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.Release\n c.param := shrinkPermissions\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := DontCare\n c.corrupt := false.B\n (legal, c)\n }\n\n def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {\n require (manager.anySupportAcquireB, s\"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsAcquireBFast(toAddress, lgSize)\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.ReleaseData\n c.param := shrinkPermissions\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := data\n c.corrupt := corrupt\n (legal, c)\n }\n\n def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =\n Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)\n\n def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =\n ProbeAck(b.source, b.address, b.size, reportPermissions)\n\n def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.ProbeAck\n c.param := reportPermissions\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := DontCare\n c.corrupt := false.B\n c\n }\n\n def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =\n ProbeAck(b.source, b.address, b.size, reportPermissions, data)\n\n def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.ProbeAckData\n c.param := reportPermissions\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := data\n c.corrupt := corrupt\n c\n }\n\n def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =\n ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)\n\n def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)\n def GrantAck(toSink: UInt): TLBundleE = {\n val e = Wire(new TLBundleE(bundle))\n e.sink := toSink\n e\n }\n\n // Accesses\n def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {\n require (manager.anySupportGet, s\"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsGetFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.Get\n a.param := 0.U\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := DontCare\n a.corrupt := false.B\n (legal, a)\n }\n\n def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =\n Put(fromSource, toAddress, lgSize, data, false.B)\n\n def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {\n require (manager.anySupportPutFull, s\"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsPutFullFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.PutFullData\n a.param := 0.U\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := data\n a.corrupt := corrupt\n (legal, a)\n }\n\n def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =\n Put(fromSource, toAddress, lgSize, data, mask, false.B)\n\n def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {\n require (manager.anySupportPutPartial, s\"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsPutPartialFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.PutPartialData\n a.param := 0.U\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask\n a.data := data\n a.corrupt := corrupt\n (legal, a)\n }\n\n def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {\n require (manager.anySupportArithmetic, s\"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsArithmeticFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.ArithmeticData\n a.param := atomic\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := data\n a.corrupt := corrupt\n (legal, a)\n }\n\n def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {\n require (manager.anySupportLogical, s\"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsLogicalFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.LogicalData\n a.param := atomic\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := data\n a.corrupt := corrupt\n (legal, a)\n }\n\n def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {\n require (manager.anySupportHint, s\"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsHintFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.Hint\n a.param := param\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := DontCare\n a.corrupt := false.B\n (legal, a)\n }\n\n def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)\n def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.AccessAck\n c.param := 0.U\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := DontCare\n c.corrupt := false.B\n c\n }\n\n def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)\n def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)\n def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)\n def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.AccessAckData\n c.param := 0.U\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := data\n c.corrupt := corrupt\n c\n }\n\n def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)\n def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.HintAck\n c.param := 0.U\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := DontCare\n c.corrupt := false.B\n c\n }\n}\n\nclass TLEdgeIn(\n client: TLClientPortParameters,\n manager: TLManagerPortParameters,\n params: Parameters,\n sourceInfo: SourceInfo)\n extends TLEdge(client, manager, params, sourceInfo)\n{\n private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {\n val todo = x.filter(!_.isEmpty)\n val heads = todo.map(_.head)\n val tails = todo.map(_.tail)\n if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }\n }\n\n // Transfers\n def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {\n require (client.anySupportProbe, s\"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}\")\n val legal = client.supportsProbe(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.Probe\n b.param := capPermissions\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask(fromAddress, lgSize)\n b.data := DontCare\n b.corrupt := false.B\n (legal, b)\n }\n\n def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)\n def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {\n val d = Wire(new TLBundleD(bundle))\n d.opcode := TLMessages.Grant\n d.param := capPermissions\n d.size := lgSize\n d.source := toSource\n d.sink := fromSink\n d.denied := denied\n d.user := DontCare\n d.echo := DontCare\n d.data := DontCare\n d.corrupt := false.B\n d\n }\n\n def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)\n def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {\n val d = Wire(new TLBundleD(bundle))\n d.opcode := TLMessages.GrantData\n d.param := capPermissions\n d.size := lgSize\n d.source := toSource\n d.sink := fromSink\n d.denied := denied\n d.user := DontCare\n d.echo := DontCare\n d.data := data\n d.corrupt := corrupt\n d\n }\n\n def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)\n def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {\n val d = Wire(new TLBundleD(bundle))\n d.opcode := TLMessages.ReleaseAck\n d.param := 0.U\n d.size := lgSize\n d.source := toSource\n d.sink := 0.U\n d.denied := denied\n d.user := DontCare\n d.echo := DontCare\n d.data := DontCare\n d.corrupt := false.B\n d\n }\n\n // Accesses\n def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {\n require (client.anySupportGet, s\"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}\")\n val legal = client.supportsGet(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.Get\n b.param := 0.U\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask(fromAddress, lgSize)\n b.data := DontCare\n b.corrupt := false.B\n (legal, b)\n }\n\n def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =\n Put(fromAddress, toSource, lgSize, data, false.B)\n\n def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {\n require (client.anySupportPutFull, s\"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}\")\n val legal = client.supportsPutFull(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.PutFullData\n b.param := 0.U\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask(fromAddress, lgSize)\n b.data := data\n b.corrupt := corrupt\n (legal, b)\n }\n\n def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =\n Put(fromAddress, toSource, lgSize, data, mask, false.B)\n\n def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {\n require (client.anySupportPutPartial, s\"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}\")\n val legal = client.supportsPutPartial(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.PutPartialData\n b.param := 0.U\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask\n b.data := data\n b.corrupt := corrupt\n (legal, b)\n }\n\n def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {\n require (client.anySupportArithmetic, s\"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}\")\n val legal = client.supportsArithmetic(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.ArithmeticData\n b.param := atomic\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask(fromAddress, lgSize)\n b.data := data\n b.corrupt := corrupt\n (legal, b)\n }\n\n def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {\n require (client.anySupportLogical, s\"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}\")\n val legal = client.supportsLogical(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.LogicalData\n b.param := atomic\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask(fromAddress, lgSize)\n b.data := data\n b.corrupt := corrupt\n (legal, b)\n }\n\n def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {\n require (client.anySupportHint, s\"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}\")\n val legal = client.supportsHint(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.Hint\n b.param := param\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask(fromAddress, lgSize)\n b.data := DontCare\n b.corrupt := false.B\n (legal, b)\n }\n\n def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)\n def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)\n def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)\n def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {\n val d = Wire(new TLBundleD(bundle))\n d.opcode := TLMessages.AccessAck\n d.param := 0.U\n d.size := lgSize\n d.source := toSource\n d.sink := 0.U\n d.denied := denied\n d.user := DontCare\n d.echo := DontCare\n d.data := DontCare\n d.corrupt := false.B\n d\n }\n\n def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)\n def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)\n def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)\n def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {\n val d = Wire(new TLBundleD(bundle))\n d.opcode := TLMessages.AccessAckData\n d.param := 0.U\n d.size := lgSize\n d.source := toSource\n d.sink := 0.U\n d.denied := denied\n d.user := DontCare\n d.echo := DontCare\n d.data := data\n d.corrupt := corrupt\n d\n }\n\n def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)\n def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)\n def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)\n def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {\n val d = Wire(new TLBundleD(bundle))\n d.opcode := TLMessages.HintAck\n d.param := 0.U\n d.size := lgSize\n d.source := toSource\n d.sink := 0.U\n d.denied := denied\n d.user := DontCare\n d.echo := DontCare\n d.data := DontCare\n d.corrupt := false.B\n d\n }\n}\n"},"response":{"kind":"string","value":"module TLMonitor_55(\t// @[Monitor.scala:36:7]\n input clock,\t// @[Monitor.scala:36:7]\n input reset,\t// @[Monitor.scala:36:7]\n input io_in_a_ready,\t// @[Monitor.scala:20:14]\n input io_in_a_valid,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_a_bits_opcode,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_a_bits_param,\t// @[Monitor.scala:20:14]\n input [1:0] io_in_a_bits_size,\t// @[Monitor.scala:20:14]\n input [7:0] io_in_a_bits_source,\t// @[Monitor.scala:20:14]\n input [27:0] io_in_a_bits_address,\t// @[Monitor.scala:20:14]\n input [7:0] io_in_a_bits_mask,\t// @[Monitor.scala:20:14]\n input [63:0] io_in_a_bits_data,\t// @[Monitor.scala:20:14]\n input io_in_a_bits_corrupt,\t// @[Monitor.scala:20:14]\n input io_in_d_ready,\t// @[Monitor.scala:20:14]\n input io_in_d_valid,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_d_bits_opcode,\t// @[Monitor.scala:20:14]\n input [1:0] io_in_d_bits_size,\t// @[Monitor.scala:20:14]\n input [7:0] io_in_d_bits_source,\t// @[Monitor.scala:20:14]\n input [63:0] io_in_d_bits_data\t// @[Monitor.scala:20:14]\n);\n\n wire [31:0] _plusarg_reader_1_out;\t// @[PlusArg.scala:80:11]\n wire [31:0] _plusarg_reader_out;\t// @[PlusArg.scala:80:11]\n wire io_in_a_ready_0 = io_in_a_ready;\t// @[Monitor.scala:36:7]\n wire io_in_a_valid_0 = io_in_a_valid;\t// @[Monitor.scala:36:7]\n wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode;\t// @[Monitor.scala:36:7]\n wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param;\t// @[Monitor.scala:36:7]\n wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size;\t// @[Monitor.scala:36:7]\n wire [7:0] io_in_a_bits_source_0 = io_in_a_bits_source;\t// @[Monitor.scala:36:7]\n wire [27:0] io_in_a_bits_address_0 = io_in_a_bits_address;\t// @[Monitor.scala:36:7]\n wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask;\t// @[Monitor.scala:36:7]\n wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data;\t// @[Monitor.scala:36:7]\n wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt;\t// @[Monitor.scala:36:7]\n wire io_in_d_ready_0 = io_in_d_ready;\t// @[Monitor.scala:36:7]\n wire io_in_d_valid_0 = io_in_d_valid;\t// @[Monitor.scala:36:7]\n wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode;\t// @[Monitor.scala:36:7]\n wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size;\t// @[Monitor.scala:36:7]\n wire [7:0] io_in_d_bits_source_0 = io_in_d_bits_source;\t// @[Monitor.scala:36:7]\n wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data;\t// @[Monitor.scala:36:7]\n wire io_in_d_bits_sink = 1'h0;\t// @[Monitor.scala:36:7]\n wire io_in_d_bits_denied = 1'h0;\t// @[Monitor.scala:36:7]\n wire io_in_d_bits_corrupt = 1'h0;\t// @[Monitor.scala:36:7]\n wire _source_ok_T = 1'h0;\t// @[Parameters.scala:54:10]\n wire _source_ok_T_6 = 1'h0;\t// @[Parameters.scala:54:10]\n wire sink_ok = 1'h0;\t// @[Monitor.scala:309:31]\n wire a_first_beats1_decode = 1'h0;\t// @[Edges.scala:220:59]\n wire a_first_beats1 = 1'h0;\t// @[Edges.scala:221:14]\n wire a_first_count = 1'h0;\t// @[Edges.scala:234:25]\n wire d_first_beats1_decode = 1'h0;\t// @[Edges.scala:220:59]\n wire d_first_beats1 = 1'h0;\t// @[Edges.scala:221:14]\n wire d_first_count = 1'h0;\t// @[Edges.scala:234:25]\n wire a_first_beats1_decode_1 = 1'h0;\t// @[Edges.scala:220:59]\n wire a_first_beats1_1 = 1'h0;\t// @[Edges.scala:221:14]\n wire a_first_count_1 = 1'h0;\t// @[Edges.scala:234:25]\n wire d_first_beats1_decode_1 = 1'h0;\t// @[Edges.scala:220:59]\n wire d_first_beats1_1 = 1'h0;\t// @[Edges.scala:221:14]\n wire d_first_count_1 = 1'h0;\t// @[Edges.scala:234:25]\n wire _c_first_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_2_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_2_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_2_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_3_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_3_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_3_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_T = 1'h0;\t// @[Decoupled.scala:51:35]\n wire c_first_beats1_decode = 1'h0;\t// @[Edges.scala:220:59]\n wire c_first_beats1_opdata = 1'h0;\t// @[Edges.scala:102:36]\n wire c_first_beats1 = 1'h0;\t// @[Edges.scala:221:14]\n wire _c_first_last_T = 1'h0;\t// @[Edges.scala:232:25]\n wire c_first_done = 1'h0;\t// @[Edges.scala:233:22]\n wire _c_first_count_T = 1'h0;\t// @[Edges.scala:234:27]\n wire c_first_count = 1'h0;\t// @[Edges.scala:234:25]\n wire _c_first_counter_T = 1'h0;\t// @[Edges.scala:236:21]\n wire d_first_beats1_decode_2 = 1'h0;\t// @[Edges.scala:220:59]\n wire d_first_beats1_2 = 1'h0;\t// @[Edges.scala:221:14]\n wire d_first_count_2 = 1'h0;\t// @[Edges.scala:234:25]\n wire _c_set_wo_ready_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_wo_ready_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_wo_ready_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_wo_ready_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_interm_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_interm_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_interm_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_interm_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_interm_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_interm_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_T = 1'h0;\t// @[Monitor.scala:772:47]\n wire _c_probe_ack_WIRE_2_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_2_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_3_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_3_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_T_1 = 1'h0;\t// @[Monitor.scala:772:95]\n wire c_probe_ack = 1'h0;\t// @[Monitor.scala:772:71]\n wire _same_cycle_resp_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_T_3 = 1'h0;\t// @[Monitor.scala:795:44]\n wire _same_cycle_resp_WIRE_2_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_2_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_3_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_3_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_T_4 = 1'h0;\t// @[Edges.scala:68:36]\n wire _same_cycle_resp_T_5 = 1'h0;\t// @[Edges.scala:68:51]\n wire _same_cycle_resp_T_6 = 1'h0;\t// @[Edges.scala:68:40]\n wire _same_cycle_resp_T_7 = 1'h0;\t// @[Monitor.scala:795:55]\n wire _same_cycle_resp_WIRE_4_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_4_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_5_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_5_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire same_cycle_resp_1 = 1'h0;\t// @[Monitor.scala:795:88]\n wire _source_ok_T_1 = 1'h1;\t// @[Parameters.scala:54:32]\n wire _source_ok_T_2 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _source_ok_T_3 = 1'h1;\t// @[Parameters.scala:54:67]\n wire _source_ok_T_7 = 1'h1;\t// @[Parameters.scala:54:32]\n wire _source_ok_T_8 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _source_ok_T_9 = 1'h1;\t// @[Parameters.scala:54:67]\n wire _a_first_last_T_1 = 1'h1;\t// @[Edges.scala:232:43]\n wire a_first_last = 1'h1;\t// @[Edges.scala:232:33]\n wire _d_first_last_T_1 = 1'h1;\t// @[Edges.scala:232:43]\n wire d_first_last = 1'h1;\t// @[Edges.scala:232:33]\n wire _a_first_last_T_3 = 1'h1;\t// @[Edges.scala:232:43]\n wire a_first_last_1 = 1'h1;\t// @[Edges.scala:232:33]\n wire _d_first_last_T_3 = 1'h1;\t// @[Edges.scala:232:43]\n wire d_first_last_1 = 1'h1;\t// @[Edges.scala:232:33]\n wire c_first_counter1 = 1'h1;\t// @[Edges.scala:230:28]\n wire c_first = 1'h1;\t// @[Edges.scala:231:25]\n wire _c_first_last_T_1 = 1'h1;\t// @[Edges.scala:232:43]\n wire c_first_last = 1'h1;\t// @[Edges.scala:232:33]\n wire _d_first_last_T_5 = 1'h1;\t// @[Edges.scala:232:43]\n wire d_first_last_2 = 1'h1;\t// @[Edges.scala:232:33]\n wire [1:0] _c_first_counter1_T = 2'h3;\t// @[Edges.scala:230:28]\n wire [1:0] io_in_d_bits_param = 2'h0;\t// @[Monitor.scala:36:7]\n wire [1:0] _c_first_WIRE_bits_size = 2'h0;\t// @[Bundles.scala:265:74]\n wire [1:0] _c_first_WIRE_1_bits_size = 2'h0;\t// @[Bundles.scala:265:61]\n wire [1:0] _c_first_WIRE_2_bits_size = 2'h0;\t// @[Bundles.scala:265:74]\n wire [1:0] _c_first_WIRE_3_bits_size = 2'h0;\t// @[Bundles.scala:265:61]\n wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0;\t// @[Bundles.scala:265:74]\n wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0;\t// @[Bundles.scala:265:61]\n wire [1:0] _c_set_WIRE_bits_size = 2'h0;\t// @[Bundles.scala:265:74]\n wire [1:0] _c_set_WIRE_1_bits_size = 2'h0;\t// @[Bundles.scala:265:61]\n wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0;\t// @[Bundles.scala:265:74]\n wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0;\t// @[Bundles.scala:265:61]\n wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0;\t// @[Bundles.scala:265:74]\n wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0;\t// @[Bundles.scala:265:61]\n wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0;\t// @[Bundles.scala:265:74]\n wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0;\t// @[Bundles.scala:265:61]\n wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0;\t// @[Bundles.scala:265:74]\n wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0;\t// @[Bundles.scala:265:61]\n wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0;\t// @[Bundles.scala:265:74]\n wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0;\t// @[Bundles.scala:265:61]\n wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0;\t// @[Bundles.scala:265:74]\n wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0;\t// @[Bundles.scala:265:61]\n wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0;\t// @[Bundles.scala:265:74]\n wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0;\t// @[Bundles.scala:265:61]\n wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0;\t// @[Bundles.scala:265:74]\n wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0;\t// @[Bundles.scala:265:61]\n wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0;\t// @[Bundles.scala:265:74]\n wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_first_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_first_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_first_WIRE_2_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_first_WIRE_3_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_set_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_set_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [27:0] _c_first_WIRE_bits_address = 28'h0;\t// @[Bundles.scala:265:74]\n wire [27:0] _c_first_WIRE_1_bits_address = 28'h0;\t// @[Bundles.scala:265:61]\n wire [27:0] _c_first_WIRE_2_bits_address = 28'h0;\t// @[Bundles.scala:265:74]\n wire [27:0] _c_first_WIRE_3_bits_address = 28'h0;\t// @[Bundles.scala:265:61]\n wire [27:0] _c_set_wo_ready_WIRE_bits_address = 28'h0;\t// @[Bundles.scala:265:74]\n wire [27:0] _c_set_wo_ready_WIRE_1_bits_address = 28'h0;\t// @[Bundles.scala:265:61]\n wire [27:0] _c_set_WIRE_bits_address = 28'h0;\t// @[Bundles.scala:265:74]\n wire [27:0] _c_set_WIRE_1_bits_address = 28'h0;\t// @[Bundles.scala:265:61]\n wire [27:0] _c_opcodes_set_interm_WIRE_bits_address = 28'h0;\t// @[Bundles.scala:265:74]\n wire [27:0] _c_opcodes_set_interm_WIRE_1_bits_address = 28'h0;\t// @[Bundles.scala:265:61]\n wire [27:0] _c_sizes_set_interm_WIRE_bits_address = 28'h0;\t// @[Bundles.scala:265:74]\n wire [27:0] _c_sizes_set_interm_WIRE_1_bits_address = 28'h0;\t// @[Bundles.scala:265:61]\n wire [27:0] _c_opcodes_set_WIRE_bits_address = 28'h0;\t// @[Bundles.scala:265:74]\n wire [27:0] _c_opcodes_set_WIRE_1_bits_address = 28'h0;\t// @[Bundles.scala:265:61]\n wire [27:0] _c_sizes_set_WIRE_bits_address = 28'h0;\t// @[Bundles.scala:265:74]\n wire [27:0] _c_sizes_set_WIRE_1_bits_address = 28'h0;\t// @[Bundles.scala:265:61]\n wire [27:0] _c_probe_ack_WIRE_bits_address = 28'h0;\t// @[Bundles.scala:265:74]\n wire [27:0] _c_probe_ack_WIRE_1_bits_address = 28'h0;\t// @[Bundles.scala:265:61]\n wire [27:0] _c_probe_ack_WIRE_2_bits_address = 28'h0;\t// @[Bundles.scala:265:74]\n wire [27:0] _c_probe_ack_WIRE_3_bits_address = 28'h0;\t// @[Bundles.scala:265:61]\n wire [27:0] _same_cycle_resp_WIRE_bits_address = 28'h0;\t// @[Bundles.scala:265:74]\n wire [27:0] _same_cycle_resp_WIRE_1_bits_address = 28'h0;\t// @[Bundles.scala:265:61]\n wire [27:0] _same_cycle_resp_WIRE_2_bits_address = 28'h0;\t// @[Bundles.scala:265:74]\n wire [27:0] _same_cycle_resp_WIRE_3_bits_address = 28'h0;\t// @[Bundles.scala:265:61]\n wire [27:0] _same_cycle_resp_WIRE_4_bits_address = 28'h0;\t// @[Bundles.scala:265:74]\n wire [27:0] _same_cycle_resp_WIRE_5_bits_address = 28'h0;\t// @[Bundles.scala:265:61]\n wire [7:0] _c_first_WIRE_bits_source = 8'h0;\t// @[Bundles.scala:265:74]\n wire [7:0] _c_first_WIRE_1_bits_source = 8'h0;\t// @[Bundles.scala:265:61]\n wire [7:0] _c_first_WIRE_2_bits_source = 8'h0;\t// @[Bundles.scala:265:74]\n wire [7:0] _c_first_WIRE_3_bits_source = 8'h0;\t// @[Bundles.scala:265:61]\n wire [7:0] _c_set_wo_ready_WIRE_bits_source = 8'h0;\t// @[Bundles.scala:265:74]\n wire [7:0] _c_set_wo_ready_WIRE_1_bits_source = 8'h0;\t// @[Bundles.scala:265:61]\n wire [7:0] _c_set_WIRE_bits_source = 8'h0;\t// @[Bundles.scala:265:74]\n wire [7:0] _c_set_WIRE_1_bits_source = 8'h0;\t// @[Bundles.scala:265:61]\n wire [7:0] _c_opcodes_set_interm_WIRE_bits_source = 8'h0;\t// @[Bundles.scala:265:74]\n wire [7:0] _c_opcodes_set_interm_WIRE_1_bits_source = 8'h0;\t// @[Bundles.scala:265:61]\n wire [7:0] _c_sizes_set_interm_WIRE_bits_source = 8'h0;\t// @[Bundles.scala:265:74]\n wire [7:0] _c_sizes_set_interm_WIRE_1_bits_source = 8'h0;\t// @[Bundles.scala:265:61]\n wire [7:0] _c_opcodes_set_WIRE_bits_source = 8'h0;\t// @[Bundles.scala:265:74]\n wire [7:0] _c_opcodes_set_WIRE_1_bits_source = 8'h0;\t// @[Bundles.scala:265:61]\n wire [7:0] _c_sizes_set_WIRE_bits_source = 8'h0;\t// @[Bundles.scala:265:74]\n wire [7:0] _c_sizes_set_WIRE_1_bits_source = 8'h0;\t// @[Bundles.scala:265:61]\n wire [7:0] _c_probe_ack_WIRE_bits_source = 8'h0;\t// @[Bundles.scala:265:74]\n wire [7:0] _c_probe_ack_WIRE_1_bits_source = 8'h0;\t// @[Bundles.scala:265:61]\n wire [7:0] _c_probe_ack_WIRE_2_bits_source = 8'h0;\t// @[Bundles.scala:265:74]\n wire [7:0] _c_probe_ack_WIRE_3_bits_source = 8'h0;\t// @[Bundles.scala:265:61]\n wire [7:0] _same_cycle_resp_WIRE_bits_source = 8'h0;\t// @[Bundles.scala:265:74]\n wire [7:0] _same_cycle_resp_WIRE_1_bits_source = 8'h0;\t// @[Bundles.scala:265:61]\n wire [7:0] _same_cycle_resp_WIRE_2_bits_source = 8'h0;\t// @[Bundles.scala:265:74]\n wire [7:0] _same_cycle_resp_WIRE_3_bits_source = 8'h0;\t// @[Bundles.scala:265:61]\n wire [7:0] _same_cycle_resp_WIRE_4_bits_source = 8'h0;\t// @[Bundles.scala:265:74]\n wire [7:0] _same_cycle_resp_WIRE_5_bits_source = 8'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] responseMap_0 = 3'h0;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMap_1 = 3'h0;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMapSecondOption_0 = 3'h0;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMapSecondOption_1 = 3'h0;\t// @[Monitor.scala:644:42]\n wire [2:0] _c_first_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_first_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_first_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_first_WIRE_2_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_first_WIRE_3_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_first_beats1_decode_T_2 = 3'h0;\t// @[package.scala:243:46]\n wire [2:0] c_sizes_set_interm = 3'h0;\t// @[Monitor.scala:755:40]\n wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_set_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_set_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_set_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_interm_T = 3'h0;\t// @[Monitor.scala:766:51]\n wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [15:0] _a_opcode_lookup_T_5 = 16'hF;\t// @[Monitor.scala:612:57]\n wire [15:0] _a_size_lookup_T_5 = 16'hF;\t// @[Monitor.scala:612:57]\n wire [15:0] _d_opcodes_clr_T_3 = 16'hF;\t// @[Monitor.scala:612:57]\n wire [15:0] _d_sizes_clr_T_3 = 16'hF;\t// @[Monitor.scala:612:57]\n wire [15:0] _c_opcode_lookup_T_5 = 16'hF;\t// @[Monitor.scala:724:57]\n wire [15:0] _c_size_lookup_T_5 = 16'hF;\t// @[Monitor.scala:724:57]\n wire [15:0] _d_opcodes_clr_T_9 = 16'hF;\t// @[Monitor.scala:724:57]\n wire [15:0] _d_sizes_clr_T_9 = 16'hF;\t// @[Monitor.scala:724:57]\n wire [16:0] _a_opcode_lookup_T_4 = 17'hF;\t// @[Monitor.scala:612:57]\n wire [16:0] _a_size_lookup_T_4 = 17'hF;\t// @[Monitor.scala:612:57]\n wire [16:0] _d_opcodes_clr_T_2 = 17'hF;\t// @[Monitor.scala:612:57]\n wire [16:0] _d_sizes_clr_T_2 = 17'hF;\t// @[Monitor.scala:612:57]\n wire [16:0] _c_opcode_lookup_T_4 = 17'hF;\t// @[Monitor.scala:724:57]\n wire [16:0] _c_size_lookup_T_4 = 17'hF;\t// @[Monitor.scala:724:57]\n wire [16:0] _d_opcodes_clr_T_8 = 17'hF;\t// @[Monitor.scala:724:57]\n wire [16:0] _d_sizes_clr_T_8 = 17'hF;\t// @[Monitor.scala:724:57]\n wire [15:0] _a_opcode_lookup_T_3 = 16'h10;\t// @[Monitor.scala:612:51]\n wire [15:0] _a_size_lookup_T_3 = 16'h10;\t// @[Monitor.scala:612:51]\n wire [15:0] _d_opcodes_clr_T_1 = 16'h10;\t// @[Monitor.scala:612:51]\n wire [15:0] _d_sizes_clr_T_1 = 16'h10;\t// @[Monitor.scala:612:51]\n wire [15:0] _c_opcode_lookup_T_3 = 16'h10;\t// @[Monitor.scala:724:51]\n wire [15:0] _c_size_lookup_T_3 = 16'h10;\t// @[Monitor.scala:724:51]\n wire [15:0] _d_opcodes_clr_T_7 = 16'h10;\t// @[Monitor.scala:724:51]\n wire [15:0] _d_sizes_clr_T_7 = 16'h10;\t// @[Monitor.scala:724:51]\n wire [2049:0] _c_sizes_set_T_1 = 2050'h0;\t// @[Monitor.scala:768:52]\n wire [10:0] _c_opcodes_set_T = 11'h0;\t// @[Monitor.scala:767:79]\n wire [10:0] _c_sizes_set_T = 11'h0;\t// @[Monitor.scala:768:77]\n wire [2050:0] _c_opcodes_set_T_1 = 2051'h0;\t// @[Monitor.scala:767:54]\n wire [2:0] responseMap_2 = 3'h1;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMap_3 = 3'h1;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMap_4 = 3'h1;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMapSecondOption_2 = 3'h1;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMapSecondOption_3 = 3'h1;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMapSecondOption_4 = 3'h1;\t// @[Monitor.scala:644:42]\n wire [2:0] _c_sizes_set_interm_T_1 = 3'h1;\t// @[Monitor.scala:766:59]\n wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1;\t// @[Monitor.scala:765:61]\n wire [3:0] c_opcodes_set_interm = 4'h0;\t// @[Monitor.scala:754:40]\n wire [3:0] _c_opcodes_set_interm_T = 4'h0;\t// @[Monitor.scala:765:53]\n wire [255:0] _c_set_wo_ready_T = 256'h1;\t// @[OneHot.scala:58:35]\n wire [255:0] _c_set_T = 256'h1;\t// @[OneHot.scala:58:35]\n wire [639:0] c_opcodes_set = 640'h0;\t// @[Monitor.scala:740:34]\n wire [639:0] c_sizes_set = 640'h0;\t// @[Monitor.scala:741:34]\n wire [159:0] c_set = 160'h0;\t// @[Monitor.scala:738:34]\n wire [159:0] c_set_wo_ready = 160'h0;\t// @[Monitor.scala:739:34]\n wire [2:0] _c_first_beats1_decode_T_1 = 3'h7;\t// @[package.scala:243:76]\n wire [5:0] _c_first_beats1_decode_T = 6'h7;\t// @[package.scala:243:71]\n wire [2:0] responseMap_6 = 3'h4;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMap_7 = 3'h4;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMapSecondOption_7 = 3'h4;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMapSecondOption_6 = 3'h5;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMap_5 = 3'h2;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMapSecondOption_5 = 3'h2;\t// @[Monitor.scala:644:42]\n wire [3:0] _a_opcode_lookup_T_2 = 4'h4;\t// @[Monitor.scala:637:123]\n wire [3:0] _a_size_lookup_T_2 = 4'h4;\t// @[Monitor.scala:641:117]\n wire [3:0] _d_opcodes_clr_T = 4'h4;\t// @[Monitor.scala:680:48]\n wire [3:0] _d_sizes_clr_T = 4'h4;\t// @[Monitor.scala:681:48]\n wire [3:0] _c_opcode_lookup_T_2 = 4'h4;\t// @[Monitor.scala:749:123]\n wire [3:0] _c_size_lookup_T_2 = 4'h4;\t// @[Monitor.scala:750:119]\n wire [3:0] _d_opcodes_clr_T_6 = 4'h4;\t// @[Monitor.scala:790:48]\n wire [3:0] _d_sizes_clr_T_6 = 4'h4;\t// @[Monitor.scala:791:48]\n wire [7:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_1 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_2 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_3 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_4 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_5 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_6 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_7 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_8 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] source_ok_uncommonBits = _source_ok_uncommonBits_T;\t// @[Parameters.scala:52:{29,56}]\n wire _source_ok_T_4 = source_ok_uncommonBits < 8'hA0;\t// @[Parameters.scala:52:56, :57:20]\n wire _source_ok_T_5 = _source_ok_T_4;\t// @[Parameters.scala:56:48, :57:20]\n wire _source_ok_WIRE_0 = _source_ok_T_5;\t// @[Parameters.scala:1138:31]\n wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0;\t// @[package.scala:243:71]\n wire [5:0] _is_aligned_mask_T;\t// @[package.scala:243:71]\n assign _is_aligned_mask_T = _GEN;\t// @[package.scala:243:71]\n wire [5:0] _a_first_beats1_decode_T;\t// @[package.scala:243:71]\n assign _a_first_beats1_decode_T = _GEN;\t// @[package.scala:243:71]\n wire [5:0] _a_first_beats1_decode_T_3;\t// @[package.scala:243:71]\n assign _a_first_beats1_decode_T_3 = _GEN;\t// @[package.scala:243:71]\n wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0];\t// @[package.scala:243:{71,76}]\n wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1;\t// @[package.scala:243:{46,76}]\n wire [27:0] _is_aligned_T = {25'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask};\t// @[package.scala:243:46]\n wire is_aligned = _is_aligned_T == 28'h0;\t// @[Edges.scala:21:{16,24}]\n wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0};\t// @[Misc.scala:202:34]\n wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0];\t// @[OneHot.scala:64:49]\n wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount;\t// @[OneHot.scala:64:49, :65:12]\n wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0];\t// @[OneHot.scala:65:{12,27}]\n wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1};\t// @[OneHot.scala:65:27]\n wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0;\t// @[Misc.scala:206:21]\n wire mask_sub_sub_size = mask_sizeOH[2];\t// @[Misc.scala:202:81, :209:26]\n wire mask_sub_sub_bit = io_in_a_bits_address_0[2];\t// @[Misc.scala:210:26]\n wire mask_sub_sub_1_2 = mask_sub_sub_bit;\t// @[Misc.scala:210:26, :214:27]\n wire mask_sub_sub_nbit = ~mask_sub_sub_bit;\t// @[Misc.scala:210:26, :211:20]\n wire mask_sub_sub_0_2 = mask_sub_sub_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T;\t// @[Misc.scala:206:21, :215:{29,38}]\n wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1;\t// @[Misc.scala:206:21, :215:{29,38}]\n wire mask_sub_size = mask_sizeOH[1];\t// @[Misc.scala:202:81, :209:26]\n wire mask_sub_bit = io_in_a_bits_address_0[1];\t// @[Misc.scala:210:26]\n wire mask_sub_nbit = ~mask_sub_bit;\t// @[Misc.scala:210:26, :211:20]\n wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T;\t// @[Misc.scala:215:{29,38}]\n wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1;\t// @[Misc.scala:215:{29,38}]\n wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2;\t// @[Misc.scala:215:{29,38}]\n wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3;\t// @[Misc.scala:215:{29,38}]\n wire mask_size = mask_sizeOH[0];\t// @[Misc.scala:202:81, :209:26]\n wire mask_bit = io_in_a_bits_address_0[0];\t// @[Misc.scala:210:26]\n wire mask_nbit = ~mask_bit;\t// @[Misc.scala:210:26, :211:20]\n wire mask_eq = mask_sub_0_2 & mask_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_acc_T = mask_size & mask_eq;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc = mask_sub_0_1 | _mask_acc_T;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_1 = mask_sub_0_2 & mask_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_acc_T_1 = mask_size & mask_eq_1;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_2 = mask_sub_1_2 & mask_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_acc_T_2 = mask_size & mask_eq_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_3 = mask_sub_1_2 & mask_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_acc_T_3 = mask_size & mask_eq_3;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_4 = mask_sub_2_2 & mask_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_acc_T_4 = mask_size & mask_eq_4;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_5 = mask_sub_2_2 & mask_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_acc_T_5 = mask_size & mask_eq_5;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_6 = mask_sub_3_2 & mask_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_acc_T_6 = mask_size & mask_eq_6;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_7 = mask_sub_3_2 & mask_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_acc_T_7 = mask_size & mask_eq_7;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7;\t// @[Misc.scala:215:{29,38}]\n wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc};\t// @[Misc.scala:215:29, :222:10]\n wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2};\t// @[Misc.scala:215:29, :222:10]\n wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo};\t// @[Misc.scala:222:10]\n wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4};\t// @[Misc.scala:215:29, :222:10]\n wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6};\t// @[Misc.scala:215:29, :222:10]\n wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo};\t// @[Misc.scala:222:10]\n wire [7:0] mask = {mask_hi, mask_lo};\t// @[Misc.scala:222:10]\n wire [7:0] uncommonBits = _uncommonBits_T;\t// @[Parameters.scala:52:{29,56}]\n wire [7:0] uncommonBits_1 = _uncommonBits_T_1;\t// @[Parameters.scala:52:{29,56}]\n wire [7:0] uncommonBits_2 = _uncommonBits_T_2;\t// @[Parameters.scala:52:{29,56}]\n wire [7:0] uncommonBits_3 = _uncommonBits_T_3;\t// @[Parameters.scala:52:{29,56}]\n wire [7:0] uncommonBits_4 = _uncommonBits_T_4;\t// @[Parameters.scala:52:{29,56}]\n wire [7:0] uncommonBits_5 = _uncommonBits_T_5;\t// @[Parameters.scala:52:{29,56}]\n wire [7:0] uncommonBits_6 = _uncommonBits_T_6;\t// @[Parameters.scala:52:{29,56}]\n wire [7:0] uncommonBits_7 = _uncommonBits_T_7;\t// @[Parameters.scala:52:{29,56}]\n wire [7:0] uncommonBits_8 = _uncommonBits_T_8;\t// @[Parameters.scala:52:{29,56}]\n wire [7:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1;\t// @[Parameters.scala:52:{29,56}]\n wire _source_ok_T_10 = source_ok_uncommonBits_1 < 8'hA0;\t// @[Parameters.scala:52:56, :57:20]\n wire _source_ok_T_11 = _source_ok_T_10;\t// @[Parameters.scala:56:48, :57:20]\n wire _source_ok_WIRE_1_0 = _source_ok_T_11;\t// @[Parameters.scala:1138:31]\n wire _T_672 = io_in_a_ready_0 & io_in_a_valid_0;\t// @[Decoupled.scala:51:35]\n wire _a_first_T;\t// @[Decoupled.scala:51:35]\n assign _a_first_T = _T_672;\t// @[Decoupled.scala:51:35]\n wire _a_first_T_1;\t// @[Decoupled.scala:51:35]\n assign _a_first_T_1 = _T_672;\t// @[Decoupled.scala:51:35]\n wire a_first_done = _a_first_T;\t// @[Decoupled.scala:51:35]\n wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0];\t// @[package.scala:243:{71,76}]\n wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1;\t// @[package.scala:243:{46,76}]\n wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2];\t// @[Monitor.scala:36:7]\n wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2];\t// @[Monitor.scala:36:7]\n wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T;\t// @[Edges.scala:92:{28,37}]\n reg a_first_counter;\t// @[Edges.scala:229:27]\n wire _a_first_last_T = a_first_counter;\t// @[Edges.scala:229:27, :232:25]\n wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1;\t// @[Edges.scala:229:27, :230:28]\n wire a_first_counter1 = _a_first_counter1_T[0];\t// @[Edges.scala:230:28]\n wire a_first = ~a_first_counter;\t// @[Edges.scala:229:27, :231:25]\n wire _a_first_count_T = ~a_first_counter1;\t// @[Edges.scala:230:28, :234:27]\n wire _a_first_counter_T = ~a_first & a_first_counter1;\t// @[Edges.scala:230:28, :231:25, :236:21]\n reg [2:0] opcode;\t// @[Monitor.scala:387:22]\n reg [2:0] param;\t// @[Monitor.scala:388:22]\n reg [1:0] size;\t// @[Monitor.scala:389:22]\n reg [7:0] source;\t// @[Monitor.scala:390:22]\n reg [27:0] address;\t// @[Monitor.scala:391:22]\n wire _T_745 = io_in_d_ready_0 & io_in_d_valid_0;\t// @[Decoupled.scala:51:35]\n wire _d_first_T;\t// @[Decoupled.scala:51:35]\n assign _d_first_T = _T_745;\t// @[Decoupled.scala:51:35]\n wire _d_first_T_1;\t// @[Decoupled.scala:51:35]\n assign _d_first_T_1 = _T_745;\t// @[Decoupled.scala:51:35]\n wire _d_first_T_2;\t// @[Decoupled.scala:51:35]\n assign _d_first_T_2 = _T_745;\t// @[Decoupled.scala:51:35]\n wire d_first_done = _d_first_T;\t// @[Decoupled.scala:51:35]\n wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0;\t// @[package.scala:243:71]\n wire [5:0] _d_first_beats1_decode_T;\t// @[package.scala:243:71]\n assign _d_first_beats1_decode_T = _GEN_0;\t// @[package.scala:243:71]\n wire [5:0] _d_first_beats1_decode_T_3;\t// @[package.scala:243:71]\n assign _d_first_beats1_decode_T_3 = _GEN_0;\t// @[package.scala:243:71]\n wire [5:0] _d_first_beats1_decode_T_6;\t// @[package.scala:243:71]\n assign _d_first_beats1_decode_T_6 = _GEN_0;\t// @[package.scala:243:71]\n wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0];\t// @[package.scala:243:{71,76}]\n wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1;\t// @[package.scala:243:{46,76}]\n wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0];\t// @[Monitor.scala:36:7]\n wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0];\t// @[Monitor.scala:36:7]\n wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0];\t// @[Monitor.scala:36:7]\n reg d_first_counter;\t// @[Edges.scala:229:27]\n wire _d_first_last_T = d_first_counter;\t// @[Edges.scala:229:27, :232:25]\n wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1;\t// @[Edges.scala:229:27, :230:28]\n wire d_first_counter1 = _d_first_counter1_T[0];\t// @[Edges.scala:230:28]\n wire d_first = ~d_first_counter;\t// @[Edges.scala:229:27, :231:25]\n wire _d_first_count_T = ~d_first_counter1;\t// @[Edges.scala:230:28, :234:27]\n wire _d_first_counter_T = ~d_first & d_first_counter1;\t// @[Edges.scala:230:28, :231:25, :236:21]\n reg [2:0] opcode_1;\t// @[Monitor.scala:538:22]\n reg [1:0] size_1;\t// @[Monitor.scala:540:22]\n reg [7:0] source_1;\t// @[Monitor.scala:541:22]\n reg [159:0] inflight;\t// @[Monitor.scala:614:27]\n reg [639:0] inflight_opcodes;\t// @[Monitor.scala:616:35]\n reg [639:0] inflight_sizes;\t// @[Monitor.scala:618:33]\n wire a_first_done_1 = _a_first_T_1;\t// @[Decoupled.scala:51:35]\n wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0];\t// @[package.scala:243:{71,76}]\n wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4;\t// @[package.scala:243:{46,76}]\n wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1;\t// @[Edges.scala:92:{28,37}]\n reg a_first_counter_1;\t// @[Edges.scala:229:27]\n wire _a_first_last_T_2 = a_first_counter_1;\t// @[Edges.scala:229:27, :232:25]\n wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1;\t// @[Edges.scala:229:27, :230:28]\n wire a_first_counter1_1 = _a_first_counter1_T_1[0];\t// @[Edges.scala:230:28]\n wire a_first_1 = ~a_first_counter_1;\t// @[Edges.scala:229:27, :231:25]\n wire _a_first_count_T_1 = ~a_first_counter1_1;\t// @[Edges.scala:230:28, :234:27]\n wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1;\t// @[Edges.scala:230:28, :231:25, :236:21]\n wire d_first_done_1 = _d_first_T_1;\t// @[Decoupled.scala:51:35]\n wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0];\t// @[package.scala:243:{71,76}]\n wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4;\t// @[package.scala:243:{46,76}]\n reg d_first_counter_1;\t// @[Edges.scala:229:27]\n wire _d_first_last_T_2 = d_first_counter_1;\t// @[Edges.scala:229:27, :232:25]\n wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1;\t// @[Edges.scala:229:27, :230:28]\n wire d_first_counter1_1 = _d_first_counter1_T_1[0];\t// @[Edges.scala:230:28]\n wire d_first_1 = ~d_first_counter_1;\t// @[Edges.scala:229:27, :231:25]\n wire _d_first_count_T_1 = ~d_first_counter1_1;\t// @[Edges.scala:230:28, :234:27]\n wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1;\t// @[Edges.scala:230:28, :231:25, :236:21]\n wire [159:0] a_set;\t// @[Monitor.scala:626:34]\n wire [159:0] a_set_wo_ready;\t// @[Monitor.scala:627:34]\n wire [639:0] a_opcodes_set;\t// @[Monitor.scala:630:33]\n wire [639:0] a_sizes_set;\t// @[Monitor.scala:632:31]\n wire [2:0] a_opcode_lookup;\t// @[Monitor.scala:635:35]\n wire [10:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0};\t// @[Monitor.scala:36:7, :637:69]\n wire [10:0] _a_opcode_lookup_T;\t// @[Monitor.scala:637:69]\n assign _a_opcode_lookup_T = _GEN_1;\t// @[Monitor.scala:637:69]\n wire [10:0] _a_size_lookup_T;\t// @[Monitor.scala:641:65]\n assign _a_size_lookup_T = _GEN_1;\t// @[Monitor.scala:637:69, :641:65]\n wire [10:0] _d_opcodes_clr_T_4;\t// @[Monitor.scala:680:101]\n assign _d_opcodes_clr_T_4 = _GEN_1;\t// @[Monitor.scala:637:69, :680:101]\n wire [10:0] _d_sizes_clr_T_4;\t// @[Monitor.scala:681:99]\n assign _d_sizes_clr_T_4 = _GEN_1;\t// @[Monitor.scala:637:69, :681:99]\n wire [10:0] _c_opcode_lookup_T;\t// @[Monitor.scala:749:69]\n assign _c_opcode_lookup_T = _GEN_1;\t// @[Monitor.scala:637:69, :749:69]\n wire [10:0] _c_size_lookup_T;\t// @[Monitor.scala:750:67]\n assign _c_size_lookup_T = _GEN_1;\t// @[Monitor.scala:637:69, :750:67]\n wire [10:0] _d_opcodes_clr_T_10;\t// @[Monitor.scala:790:101]\n assign _d_opcodes_clr_T_10 = _GEN_1;\t// @[Monitor.scala:637:69, :790:101]\n wire [10:0] _d_sizes_clr_T_10;\t// @[Monitor.scala:791:99]\n assign _d_sizes_clr_T_10 = _GEN_1;\t// @[Monitor.scala:637:69, :791:99]\n wire [639:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T;\t// @[Monitor.scala:616:35, :637:{44,69}]\n wire [639:0] _a_opcode_lookup_T_6 = {636'h0, _a_opcode_lookup_T_1[3:0]};\t// @[Monitor.scala:637:{44,97}]\n wire [639:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[639:1]};\t// @[Monitor.scala:637:{97,152}]\n assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0];\t// @[Monitor.scala:635:35, :637:{21,152}]\n wire [3:0] a_size_lookup;\t// @[Monitor.scala:639:33]\n wire [639:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T;\t// @[Monitor.scala:618:33, :641:{40,65}]\n wire [639:0] _a_size_lookup_T_6 = {636'h0, _a_size_lookup_T_1[3:0]};\t// @[Monitor.scala:641:{40,91}]\n wire [639:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[639:1]};\t// @[Monitor.scala:641:{91,144}]\n assign a_size_lookup = _a_size_lookup_T_7[3:0];\t// @[Monitor.scala:639:33, :641:{19,144}]\n wire [3:0] a_opcodes_set_interm;\t// @[Monitor.scala:646:40]\n wire [2:0] a_sizes_set_interm;\t// @[Monitor.scala:648:38]\n wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1;\t// @[Monitor.scala:36:7, :651:26, :684:44]\n wire [255:0] _GEN_2 = 256'h1 << io_in_a_bits_source_0;\t// @[OneHot.scala:58:35]\n wire [255:0] _a_set_wo_ready_T;\t// @[OneHot.scala:58:35]\n assign _a_set_wo_ready_T = _GEN_2;\t// @[OneHot.scala:58:35]\n wire [255:0] _a_set_T;\t// @[OneHot.scala:58:35]\n assign _a_set_T = _GEN_2;\t// @[OneHot.scala:58:35]\n assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[159:0] : 160'h0;\t// @[OneHot.scala:58:35]\n wire _T_598 = _T_672 & a_first_1;\t// @[Decoupled.scala:51:35]\n assign a_set = _T_598 ? _a_set_T[159:0] : 160'h0;\t// @[OneHot.scala:58:35]\n wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0};\t// @[Monitor.scala:36:7, :657:53]\n wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1};\t// @[Monitor.scala:657:{53,61}]\n assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0;\t// @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]\n wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0};\t// @[Monitor.scala:36:7, :658:51]\n wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1};\t// @[Monitor.scala:658:{51,59}]\n assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0;\t// @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]\n wire [10:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0};\t// @[Monitor.scala:36:7, :659:79]\n wire [10:0] _a_opcodes_set_T;\t// @[Monitor.scala:659:79]\n assign _a_opcodes_set_T = _GEN_3;\t// @[Monitor.scala:659:79]\n wire [10:0] _a_sizes_set_T;\t// @[Monitor.scala:660:77]\n assign _a_sizes_set_T = _GEN_3;\t// @[Monitor.scala:659:79, :660:77]\n wire [2050:0] _a_opcodes_set_T_1 = {2047'h0, a_opcodes_set_interm} << _a_opcodes_set_T;\t// @[Monitor.scala:646:40, :659:{54,79}]\n assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[639:0] : 640'h0;\t// @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]\n wire [2049:0] _a_sizes_set_T_1 = {2047'h0, a_sizes_set_interm} << _a_sizes_set_T;\t// @[Monitor.scala:648:38, :659:54, :660:{52,77}]\n assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[639:0] : 640'h0;\t// @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]\n wire [159:0] d_clr;\t// @[Monitor.scala:664:34]\n wire [159:0] d_clr_wo_ready;\t// @[Monitor.scala:665:34]\n wire [639:0] d_opcodes_clr;\t// @[Monitor.scala:668:33]\n wire [639:0] d_sizes_clr;\t// @[Monitor.scala:670:31]\n wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6;\t// @[Monitor.scala:36:7, :673:46]\n wire d_release_ack;\t// @[Monitor.scala:673:46]\n assign d_release_ack = _GEN_4;\t// @[Monitor.scala:673:46]\n wire d_release_ack_1;\t// @[Monitor.scala:783:46]\n assign d_release_ack_1 = _GEN_4;\t// @[Monitor.scala:673:46, :783:46]\n wire _T_644 = io_in_d_valid_0 & d_first_1;\t// @[Monitor.scala:36:7, :674:26]\n wire [255:0] _GEN_5 = 256'h1 << io_in_d_bits_source_0;\t// @[OneHot.scala:58:35]\n wire [255:0] _d_clr_wo_ready_T;\t// @[OneHot.scala:58:35]\n assign _d_clr_wo_ready_T = _GEN_5;\t// @[OneHot.scala:58:35]\n wire [255:0] _d_clr_T;\t// @[OneHot.scala:58:35]\n assign _d_clr_T = _GEN_5;\t// @[OneHot.scala:58:35]\n wire [255:0] _d_clr_wo_ready_T_1;\t// @[OneHot.scala:58:35]\n assign _d_clr_wo_ready_T_1 = _GEN_5;\t// @[OneHot.scala:58:35]\n wire [255:0] _d_clr_T_1;\t// @[OneHot.scala:58:35]\n assign _d_clr_T_1 = _GEN_5;\t// @[OneHot.scala:58:35]\n assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[159:0] : 160'h0;\t// @[OneHot.scala:58:35]\n wire _T_613 = _T_745 & d_first_1 & ~d_release_ack;\t// @[Decoupled.scala:51:35]\n assign d_clr = _T_613 ? _d_clr_T[159:0] : 160'h0;\t// @[OneHot.scala:58:35]\n wire [2062:0] _d_opcodes_clr_T_5 = 2063'hF << _d_opcodes_clr_T_4;\t// @[Monitor.scala:680:{76,101}]\n assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[639:0] : 640'h0;\t// @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]\n wire [2062:0] _d_sizes_clr_T_5 = 2063'hF << _d_sizes_clr_T_4;\t// @[Monitor.scala:681:{74,99}]\n assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[639:0] : 640'h0;\t// @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]\n wire _same_cycle_resp_T_1 = _same_cycle_resp_T;\t// @[Monitor.scala:684:{44,55}]\n wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0;\t// @[Monitor.scala:36:7, :684:113]\n wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2;\t// @[Monitor.scala:684:{55,88,113}]\n wire [159:0] _inflight_T = inflight | a_set;\t// @[Monitor.scala:614:27, :626:34, :705:27]\n wire [159:0] _inflight_T_1 = ~d_clr;\t// @[Monitor.scala:664:34, :705:38]\n wire [159:0] _inflight_T_2 = _inflight_T & _inflight_T_1;\t// @[Monitor.scala:705:{27,36,38}]\n wire [639:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set;\t// @[Monitor.scala:616:35, :630:33, :706:43]\n wire [639:0] _inflight_opcodes_T_1 = ~d_opcodes_clr;\t// @[Monitor.scala:668:33, :706:62]\n wire [639:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1;\t// @[Monitor.scala:706:{43,60,62}]\n wire [639:0] _inflight_sizes_T = inflight_sizes | a_sizes_set;\t// @[Monitor.scala:618:33, :632:31, :707:39]\n wire [639:0] _inflight_sizes_T_1 = ~d_sizes_clr;\t// @[Monitor.scala:670:31, :707:56]\n wire [639:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1;\t// @[Monitor.scala:707:{39,54,56}]\n reg [31:0] watchdog;\t// @[Monitor.scala:709:27]\n wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1;\t// @[Monitor.scala:709:27, :714:26]\n wire [31:0] _watchdog_T_1 = _watchdog_T[31:0];\t// @[Monitor.scala:714:26]\n reg [159:0] inflight_1;\t// @[Monitor.scala:726:35]\n wire [159:0] _inflight_T_3 = inflight_1;\t// @[Monitor.scala:726:35, :814:35]\n reg [639:0] inflight_opcodes_1;\t// @[Monitor.scala:727:35]\n wire [639:0] _inflight_opcodes_T_3 = inflight_opcodes_1;\t// @[Monitor.scala:727:35, :815:43]\n reg [639:0] inflight_sizes_1;\t// @[Monitor.scala:728:35]\n wire [639:0] _inflight_sizes_T_3 = inflight_sizes_1;\t// @[Monitor.scala:728:35, :816:41]\n wire d_first_done_2 = _d_first_T_2;\t// @[Decoupled.scala:51:35]\n wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0];\t// @[package.scala:243:{71,76}]\n wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7;\t// @[package.scala:243:{46,76}]\n reg d_first_counter_2;\t// @[Edges.scala:229:27]\n wire _d_first_last_T_4 = d_first_counter_2;\t// @[Edges.scala:229:27, :232:25]\n wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1;\t// @[Edges.scala:229:27, :230:28]\n wire d_first_counter1_2 = _d_first_counter1_T_2[0];\t// @[Edges.scala:230:28]\n wire d_first_2 = ~d_first_counter_2;\t// @[Edges.scala:229:27, :231:25]\n wire _d_first_count_T_2 = ~d_first_counter1_2;\t// @[Edges.scala:230:28, :234:27]\n wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2;\t// @[Edges.scala:230:28, :231:25, :236:21]\n wire [3:0] c_opcode_lookup;\t// @[Monitor.scala:747:35]\n wire [3:0] c_size_lookup;\t// @[Monitor.scala:748:35]\n wire [639:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T;\t// @[Monitor.scala:727:35, :749:{44,69}]\n wire [639:0] _c_opcode_lookup_T_6 = {636'h0, _c_opcode_lookup_T_1[3:0]};\t// @[Monitor.scala:749:{44,97}]\n wire [639:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[639:1]};\t// @[Monitor.scala:749:{97,152}]\n assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0];\t// @[Monitor.scala:747:35, :749:{21,152}]\n wire [639:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T;\t// @[Monitor.scala:728:35, :750:{42,67}]\n wire [639:0] _c_size_lookup_T_6 = {636'h0, _c_size_lookup_T_1[3:0]};\t// @[Monitor.scala:750:{42,93}]\n wire [639:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[639:1]};\t// @[Monitor.scala:750:{93,146}]\n assign c_size_lookup = _c_size_lookup_T_7[3:0];\t// @[Monitor.scala:748:35, :750:{21,146}]\n wire [159:0] d_clr_1;\t// @[Monitor.scala:774:34]\n wire [159:0] d_clr_wo_ready_1;\t// @[Monitor.scala:775:34]\n wire [639:0] d_opcodes_clr_1;\t// @[Monitor.scala:776:34]\n wire [639:0] d_sizes_clr_1;\t// @[Monitor.scala:777:34]\n wire _T_716 = io_in_d_valid_0 & d_first_2;\t// @[Monitor.scala:36:7, :784:26]\n assign d_clr_wo_ready_1 = _T_716 & d_release_ack_1 ? _d_clr_wo_ready_T_1[159:0] : 160'h0;\t// @[OneHot.scala:58:35]\n wire _T_698 = _T_745 & d_first_2 & d_release_ack_1;\t// @[Decoupled.scala:51:35]\n assign d_clr_1 = _T_698 ? _d_clr_T_1[159:0] : 160'h0;\t// @[OneHot.scala:58:35]\n wire [2062:0] _d_opcodes_clr_T_11 = 2063'hF << _d_opcodes_clr_T_10;\t// @[Monitor.scala:790:{76,101}]\n assign d_opcodes_clr_1 = _T_698 ? _d_opcodes_clr_T_11[639:0] : 640'h0;\t// @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]\n wire [2062:0] _d_sizes_clr_T_11 = 2063'hF << _d_sizes_clr_T_10;\t// @[Monitor.scala:791:{74,99}]\n assign d_sizes_clr_1 = _T_698 ? _d_sizes_clr_T_11[639:0] : 640'h0;\t// @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]\n wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 8'h0;\t// @[Monitor.scala:36:7, :795:113]\n wire [159:0] _inflight_T_4 = ~d_clr_1;\t// @[Monitor.scala:774:34, :814:46]\n wire [159:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4;\t// @[Monitor.scala:814:{35,44,46}]\n wire [639:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1;\t// @[Monitor.scala:776:34, :815:62]\n wire [639:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4;\t// @[Monitor.scala:815:{43,60,62}]\n wire [639:0] _inflight_sizes_T_4 = ~d_sizes_clr_1;\t// @[Monitor.scala:777:34, :816:58]\n wire [639:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4;\t// @[Monitor.scala:816:{41,56,58}]\n reg [31:0] watchdog_1;\t// @[Monitor.scala:818:27]"}}},{"rowIdx":574,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to the following Chisel files.\nFile FPU.scala:\n// See LICENSE.Berkeley for license details.\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.tile\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.{DontCare, WireInit, withClock, withReset}\nimport chisel3.experimental.SourceInfo\nimport chisel3.experimental.dataview._\nimport org.chipsalliance.cde.config.Parameters\nimport freechips.rocketchip.rocket._\nimport freechips.rocketchip.rocket.Instructions._\nimport freechips.rocketchip.util._\nimport freechips.rocketchip.util.property\n\ncase class FPUParams(\n minFLen: Int = 32,\n fLen: Int = 64,\n divSqrt: Boolean = true,\n sfmaLatency: Int = 3,\n dfmaLatency: Int = 4,\n fpmuLatency: Int = 2,\n ifpuLatency: Int = 2\n)\n\nobject FPConstants\n{\n val RM_SZ = 3\n val FLAGS_SZ = 5\n}\n\ntrait HasFPUCtrlSigs {\n val ldst = Bool()\n val wen = Bool()\n val ren1 = Bool()\n val ren2 = Bool()\n val ren3 = Bool()\n val swap12 = Bool()\n val swap23 = Bool()\n val typeTagIn = UInt(2.W)\n val typeTagOut = UInt(2.W)\n val fromint = Bool()\n val toint = Bool()\n val fastpipe = Bool()\n val fma = Bool()\n val div = Bool()\n val sqrt = Bool()\n val wflags = Bool()\n val vec = Bool()\n}\n\nclass FPUCtrlSigs extends Bundle with HasFPUCtrlSigs\n\nclass FPUDecoder(implicit p: Parameters) extends FPUModule()(p) {\n val io = IO(new Bundle {\n val inst = Input(Bits(32.W))\n val sigs = Output(new FPUCtrlSigs())\n })\n\n private val X2 = BitPat.dontCare(2)\n\n val default = List(X,X,X,X,X,X,X,X2,X2,X,X,X,X,X,X,X,N)\n val h: Array[(BitPat, List[BitPat])] =\n Array(FLH -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),\n FSH -> List(Y,N,N,Y,N,Y,X, I, H,N,Y,N,N,N,N,N,N),\n FMV_H_X -> List(N,Y,N,N,N,X,X, H, I,Y,N,N,N,N,N,N,N),\n FCVT_H_W -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),\n FCVT_H_WU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),\n FCVT_H_L -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),\n FCVT_H_LU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),\n FMV_X_H -> List(N,N,Y,N,N,N,X, I, H,N,Y,N,N,N,N,N,N),\n FCLASS_H -> List(N,N,Y,N,N,N,X, H, H,N,Y,N,N,N,N,N,N),\n FCVT_W_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),\n FCVT_WU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),\n FCVT_L_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),\n FCVT_LU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),\n FCVT_S_H -> List(N,Y,Y,N,N,N,X, H, S,N,N,Y,N,N,N,Y,N),\n FCVT_H_S -> List(N,Y,Y,N,N,N,X, S, H,N,N,Y,N,N,N,Y,N),\n FEQ_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),\n FLT_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),\n FLE_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),\n FSGNJ_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),\n FSGNJN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),\n FSGNJX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),\n FMIN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N),\n FMAX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N),\n FADD_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N),\n FSUB_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N),\n FMUL_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,Y,N,N,Y,N),\n FMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),\n FMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),\n FNMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),\n FNMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),\n FDIV_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,N,Y,N,Y,N),\n FSQRT_H -> List(N,Y,Y,N,N,N,X, H, H,N,N,N,N,N,Y,Y,N))\n val f: Array[(BitPat, List[BitPat])] =\n Array(FLW -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),\n FSW -> List(Y,N,N,Y,N,Y,X, I, S,N,Y,N,N,N,N,N,N),\n FMV_W_X -> List(N,Y,N,N,N,X,X, S, I,Y,N,N,N,N,N,N,N),\n FCVT_S_W -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),\n FCVT_S_WU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),\n FCVT_S_L -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),\n FCVT_S_LU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),\n FMV_X_W -> List(N,N,Y,N,N,N,X, I, S,N,Y,N,N,N,N,N,N),\n FCLASS_S -> List(N,N,Y,N,N,N,X, S, S,N,Y,N,N,N,N,N,N),\n FCVT_W_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),\n FCVT_WU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),\n FCVT_L_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),\n FCVT_LU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),\n FEQ_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),\n FLT_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),\n FLE_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),\n FSGNJ_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),\n FSGNJN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),\n FSGNJX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),\n FMIN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N),\n FMAX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N),\n FADD_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N),\n FSUB_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N),\n FMUL_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,Y,N,N,Y,N),\n FMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),\n FMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),\n FNMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),\n FNMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),\n FDIV_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,N,Y,N,Y,N),\n FSQRT_S -> List(N,Y,Y,N,N,N,X, S, S,N,N,N,N,N,Y,Y,N))\n val d: Array[(BitPat, List[BitPat])] =\n Array(FLD -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),\n FSD -> List(Y,N,N,Y,N,Y,X, I, D,N,Y,N,N,N,N,N,N),\n FMV_D_X -> List(N,Y,N,N,N,X,X, D, I,Y,N,N,N,N,N,N,N),\n FCVT_D_W -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),\n FCVT_D_WU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),\n FCVT_D_L -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),\n FCVT_D_LU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),\n FMV_X_D -> List(N,N,Y,N,N,N,X, I, D,N,Y,N,N,N,N,N,N),\n FCLASS_D -> List(N,N,Y,N,N,N,X, D, D,N,Y,N,N,N,N,N,N),\n FCVT_W_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),\n FCVT_WU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),\n FCVT_L_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),\n FCVT_LU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),\n FCVT_S_D -> List(N,Y,Y,N,N,N,X, D, S,N,N,Y,N,N,N,Y,N),\n FCVT_D_S -> List(N,Y,Y,N,N,N,X, S, D,N,N,Y,N,N,N,Y,N),\n FEQ_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),\n FLT_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),\n FLE_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),\n FSGNJ_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),\n FSGNJN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),\n FSGNJX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),\n FMIN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N),\n FMAX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N),\n FADD_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N),\n FSUB_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N),\n FMUL_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,Y,N,N,Y,N),\n FMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),\n FMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),\n FNMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),\n FNMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),\n FDIV_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,N,Y,N,Y,N),\n FSQRT_D -> List(N,Y,Y,N,N,N,X, D, D,N,N,N,N,N,Y,Y,N))\n val fcvt_hd: Array[(BitPat, List[BitPat])] =\n Array(FCVT_H_D -> List(N,Y,Y,N,N,N,X, D, H,N,N,Y,N,N,N,Y,N),\n FCVT_D_H -> List(N,Y,Y,N,N,N,X, H, D,N,N,Y,N,N,N,Y,N))\n val vfmv_f_s: Array[(BitPat, List[BitPat])] =\n Array(VFMV_F_S -> List(N,Y,N,N,N,N,X,X2,X2,N,N,N,N,N,N,N,Y))\n\n val insns = ((minFLen, fLen) match {\n case (32, 32) => f\n case (16, 32) => h ++ f\n case (32, 64) => f ++ d\n case (16, 64) => h ++ f ++ d ++ fcvt_hd\n case other => throw new Exception(s\"minFLen = ${minFLen} & fLen = ${fLen} is an unsupported configuration\")\n }) ++ (if (usingVector) vfmv_f_s else Array[(BitPat, List[BitPat])]())\n val decoder = DecodeLogic(io.inst, default, insns)\n val s = io.sigs\n val sigs = Seq(s.ldst, s.wen, s.ren1, s.ren2, s.ren3, s.swap12,\n s.swap23, s.typeTagIn, s.typeTagOut, s.fromint, s.toint,\n s.fastpipe, s.fma, s.div, s.sqrt, s.wflags, s.vec)\n sigs zip decoder map {case(s,d) => s := d}\n}\n\nclass FPUCoreIO(implicit p: Parameters) extends CoreBundle()(p) {\n val hartid = Input(UInt(hartIdLen.W))\n val time = Input(UInt(xLen.W))\n\n val inst = Input(Bits(32.W))\n val fromint_data = Input(Bits(xLen.W))\n\n val fcsr_rm = Input(Bits(FPConstants.RM_SZ.W))\n val fcsr_flags = Valid(Bits(FPConstants.FLAGS_SZ.W))\n\n val v_sew = Input(UInt(3.W))\n\n val store_data = Output(Bits(fLen.W))\n val toint_data = Output(Bits(xLen.W))\n\n val ll_resp_val = Input(Bool())\n val ll_resp_type = Input(Bits(3.W))\n val ll_resp_tag = Input(UInt(5.W))\n val ll_resp_data = Input(Bits(fLen.W))\n\n val valid = Input(Bool())\n val fcsr_rdy = Output(Bool())\n val nack_mem = Output(Bool())\n val illegal_rm = Output(Bool())\n val killx = Input(Bool())\n val killm = Input(Bool())\n val dec = Output(new FPUCtrlSigs())\n val sboard_set = Output(Bool())\n val sboard_clr = Output(Bool())\n val sboard_clra = Output(UInt(5.W))\n\n val keep_clock_enabled = Input(Bool())\n}\n\nclass FPUIO(implicit p: Parameters) extends FPUCoreIO ()(p) {\n val cp_req = Flipped(Decoupled(new FPInput())) //cp doesn't pay attn to kill sigs\n val cp_resp = Decoupled(new FPResult())\n}\n\nclass FPResult(implicit p: Parameters) extends CoreBundle()(p) {\n val data = Bits((fLen+1).W)\n val exc = Bits(FPConstants.FLAGS_SZ.W)\n}\n\nclass IntToFPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs {\n val rm = Bits(FPConstants.RM_SZ.W)\n val typ = Bits(2.W)\n val in1 = Bits(xLen.W)\n}\n\nclass FPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs {\n val rm = Bits(FPConstants.RM_SZ.W)\n val fmaCmd = Bits(2.W)\n val typ = Bits(2.W)\n val fmt = Bits(2.W)\n val in1 = Bits((fLen+1).W)\n val in2 = Bits((fLen+1).W)\n val in3 = Bits((fLen+1).W)\n\n}\n\ncase class FType(exp: Int, sig: Int) {\n def ieeeWidth = exp + sig\n def recodedWidth = ieeeWidth + 1\n\n def ieeeQNaN = ((BigInt(1) << (ieeeWidth - 1)) - (BigInt(1) << (sig - 2))).U(ieeeWidth.W)\n def qNaN = ((BigInt(7) << (exp + sig - 3)) + (BigInt(1) << (sig - 2))).U(recodedWidth.W)\n def isNaN(x: UInt) = x(sig + exp - 1, sig + exp - 3).andR\n def isSNaN(x: UInt) = isNaN(x) && !x(sig - 2)\n\n def classify(x: UInt) = {\n val sign = x(sig + exp)\n val code = x(exp + sig - 1, exp + sig - 3)\n val codeHi = code(2, 1)\n val isSpecial = codeHi === 3.U\n\n val isHighSubnormalIn = x(exp + sig - 3, sig - 1) < 2.U\n val isSubnormal = code === 1.U || codeHi === 1.U && isHighSubnormalIn\n val isNormal = codeHi === 1.U && !isHighSubnormalIn || codeHi === 2.U\n val isZero = code === 0.U\n val isInf = isSpecial && !code(0)\n val isNaN = code.andR\n val isSNaN = isNaN && !x(sig-2)\n val isQNaN = isNaN && x(sig-2)\n\n Cat(isQNaN, isSNaN, isInf && !sign, isNormal && !sign,\n isSubnormal && !sign, isZero && !sign, isZero && sign,\n isSubnormal && sign, isNormal && sign, isInf && sign)\n }\n\n // convert between formats, ignoring rounding, range, NaN\n def unsafeConvert(x: UInt, to: FType) = if (this == to) x else {\n val sign = x(sig + exp)\n val fractIn = x(sig - 2, 0)\n val expIn = x(sig + exp - 1, sig - 1)\n val fractOut = fractIn << to.sig >> sig\n val expOut = {\n val expCode = expIn(exp, exp - 2)\n val commonCase = (expIn + (1 << to.exp).U) - (1 << exp).U\n Mux(expCode === 0.U || expCode >= 6.U, Cat(expCode, commonCase(to.exp - 3, 0)), commonCase(to.exp, 0))\n }\n Cat(sign, expOut, fractOut)\n }\n\n private def ieeeBundle = {\n val expWidth = exp\n class IEEEBundle extends Bundle {\n val sign = Bool()\n val exp = UInt(expWidth.W)\n val sig = UInt((ieeeWidth-expWidth-1).W)\n }\n new IEEEBundle\n }\n\n def unpackIEEE(x: UInt) = x.asTypeOf(ieeeBundle)\n\n def recode(x: UInt) = hardfloat.recFNFromFN(exp, sig, x)\n def ieee(x: UInt) = hardfloat.fNFromRecFN(exp, sig, x)\n}\n\nobject FType {\n val H = new FType(5, 11)\n val S = new FType(8, 24)\n val D = new FType(11, 53)\n\n val all = List(H, S, D)\n}\n\ntrait HasFPUParameters {\n require(fLen == 0 || FType.all.exists(_.ieeeWidth == fLen))\n val minFLen: Int\n val fLen: Int\n def xLen: Int\n val minXLen = 32\n val nIntTypes = log2Ceil(xLen/minXLen) + 1\n def floatTypes = FType.all.filter(t => minFLen <= t.ieeeWidth && t.ieeeWidth <= fLen)\n def minType = floatTypes.head\n def maxType = floatTypes.last\n def prevType(t: FType) = floatTypes(typeTag(t) - 1)\n def maxExpWidth = maxType.exp\n def maxSigWidth = maxType.sig\n def typeTag(t: FType) = floatTypes.indexOf(t)\n def typeTagWbOffset = (FType.all.indexOf(minType) + 1).U\n def typeTagGroup(t: FType) = (if (floatTypes.contains(t)) typeTag(t) else typeTag(maxType)).U\n // typeTag\n def H = typeTagGroup(FType.H)\n def S = typeTagGroup(FType.S)\n def D = typeTagGroup(FType.D)\n def I = typeTag(maxType).U\n\n private def isBox(x: UInt, t: FType): Bool = x(t.sig + t.exp, t.sig + t.exp - 4).andR\n\n private def box(x: UInt, xt: FType, y: UInt, yt: FType): UInt = {\n require(xt.ieeeWidth == 2 * yt.ieeeWidth)\n val swizzledNaN = Cat(\n x(xt.sig + xt.exp, xt.sig + xt.exp - 3),\n x(xt.sig - 2, yt.recodedWidth - 1).andR,\n x(xt.sig + xt.exp - 5, xt.sig),\n y(yt.recodedWidth - 2),\n x(xt.sig - 2, yt.recodedWidth - 1),\n y(yt.recodedWidth - 1),\n y(yt.recodedWidth - 3, 0))\n Mux(xt.isNaN(x), swizzledNaN, x)\n }\n\n // implement NaN unboxing for FU inputs\n def unbox(x: UInt, tag: UInt, exactType: Option[FType]): UInt = {\n val outType = exactType.getOrElse(maxType)\n def helper(x: UInt, t: FType): Seq[(Bool, UInt)] = {\n val prev =\n if (t == minType) {\n Seq()\n } else {\n val prevT = prevType(t)\n val unswizzled = Cat(\n x(prevT.sig + prevT.exp - 1),\n x(t.sig - 1),\n x(prevT.sig + prevT.exp - 2, 0))\n val prev = helper(unswizzled, prevT)\n val isbox = isBox(x, t)\n prev.map(p => (isbox && p._1, p._2))\n }\n prev :+ (true.B, t.unsafeConvert(x, outType))\n }\n\n val (oks, floats) = helper(x, maxType).unzip\n if (exactType.isEmpty || floatTypes.size == 1) {\n Mux(oks(tag), floats(tag), maxType.qNaN)\n } else {\n val t = exactType.get\n floats(typeTag(t)) | Mux(oks(typeTag(t)), 0.U, t.qNaN)\n }\n }\n\n // make sure that the redundant bits in the NaN-boxed encoding are consistent\n def consistent(x: UInt): Bool = {\n def helper(x: UInt, t: FType): Bool = if (typeTag(t) == 0) true.B else {\n val prevT = prevType(t)\n val unswizzled = Cat(\n x(prevT.sig + prevT.exp - 1),\n x(t.sig - 1),\n x(prevT.sig + prevT.exp - 2, 0))\n val prevOK = !isBox(x, t) || helper(unswizzled, prevT)\n val curOK = !t.isNaN(x) || x(t.sig + t.exp - 4) === x(t.sig - 2, prevT.recodedWidth - 1).andR\n prevOK && curOK\n }\n helper(x, maxType)\n }\n\n // generate a NaN box from an FU result\n def box(x: UInt, t: FType): UInt = {\n if (t == maxType) {\n x\n } else {\n val nt = floatTypes(typeTag(t) + 1)\n val bigger = box(((BigInt(1) << nt.recodedWidth)-1).U, nt, x, t)\n bigger | ((BigInt(1) << maxType.recodedWidth) - (BigInt(1) << nt.recodedWidth)).U\n }\n }\n\n // generate a NaN box from an FU result\n def box(x: UInt, tag: UInt): UInt = {\n val opts = floatTypes.map(t => box(x, t))\n opts(tag)\n }\n\n // zap bits that hardfloat thinks are don't-cares, but we do care about\n def sanitizeNaN(x: UInt, t: FType): UInt = {\n if (typeTag(t) == 0) {\n x\n } else {\n val maskedNaN = x & ~((BigInt(1) << (t.sig-1)) | (BigInt(1) << (t.sig+t.exp-4))).U(t.recodedWidth.W)\n Mux(t.isNaN(x), maskedNaN, x)\n }\n }\n\n // implement NaN boxing and recoding for FL*/fmv.*.x\n def recode(x: UInt, tag: UInt): UInt = {\n def helper(x: UInt, t: FType): UInt = {\n if (typeTag(t) == 0) {\n t.recode(x)\n } else {\n val prevT = prevType(t)\n box(t.recode(x), t, helper(x, prevT), prevT)\n }\n }\n\n // fill MSBs of subword loads to emulate a wider load of a NaN-boxed value\n val boxes = floatTypes.map(t => ((BigInt(1) << maxType.ieeeWidth) - (BigInt(1) << t.ieeeWidth)).U)\n helper(boxes(tag) | x, maxType)\n }\n\n // implement NaN unboxing and un-recoding for FS*/fmv.x.*\n def ieee(x: UInt, t: FType = maxType): UInt = {\n if (typeTag(t) == 0) {\n t.ieee(x)\n } else {\n val unrecoded = t.ieee(x)\n val prevT = prevType(t)\n val prevRecoded = Cat(\n x(prevT.recodedWidth-2),\n x(t.sig-1),\n x(prevT.recodedWidth-3, 0))\n val prevUnrecoded = ieee(prevRecoded, prevT)\n Cat(unrecoded >> prevT.ieeeWidth, Mux(t.isNaN(x), prevUnrecoded, unrecoded(prevT.ieeeWidth-1, 0)))\n }\n }\n}\n\nabstract class FPUModule(implicit val p: Parameters) extends Module with HasCoreParameters with HasFPUParameters\n\nclass FPToInt(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {\n class Output extends Bundle {\n val in = new FPInput\n val lt = Bool()\n val store = Bits(fLen.W)\n val toint = Bits(xLen.W)\n val exc = Bits(FPConstants.FLAGS_SZ.W)\n }\n val io = IO(new Bundle {\n val in = Flipped(Valid(new FPInput))\n val out = Valid(new Output)\n })\n\n val in = RegEnable(io.in.bits, io.in.valid)\n val valid = RegNext(io.in.valid)\n\n val dcmp = Module(new hardfloat.CompareRecFN(maxExpWidth, maxSigWidth))\n dcmp.io.a := in.in1\n dcmp.io.b := in.in2\n dcmp.io.signaling := !in.rm(1)\n\n val tag = in.typeTagOut\n val toint_ieee = (floatTypes.map(t => if (t == FType.H) Fill(maxType.ieeeWidth / minXLen, ieee(in.in1)(15, 0).sextTo(minXLen))\n else Fill(maxType.ieeeWidth / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag)\n\n val toint = WireDefault(toint_ieee)\n val intType = WireDefault(in.fmt(0))\n io.out.bits.store := (floatTypes.map(t => Fill(fLen / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag)\n io.out.bits.toint := ((0 until nIntTypes).map(i => toint((minXLen << i) - 1, 0).sextTo(xLen)): Seq[UInt])(intType)\n io.out.bits.exc := 0.U\n\n when (in.rm(0)) {\n val classify_out = (floatTypes.map(t => t.classify(maxType.unsafeConvert(in.in1, t))): Seq[UInt])(tag)\n toint := classify_out | (toint_ieee >> minXLen << minXLen)\n intType := false.B\n }\n\n when (in.wflags) { // feq/flt/fle, fcvt\n toint := (~in.rm & Cat(dcmp.io.lt, dcmp.io.eq)).orR | (toint_ieee >> minXLen << minXLen)\n io.out.bits.exc := dcmp.io.exceptionFlags\n intType := false.B\n\n when (!in.ren2) { // fcvt\n val cvtType = in.typ.extract(log2Ceil(nIntTypes), 1)\n intType := cvtType\n val conv = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, xLen))\n conv.io.in := in.in1\n conv.io.roundingMode := in.rm\n conv.io.signedOut := ~in.typ(0)\n toint := conv.io.out\n io.out.bits.exc := Cat(conv.io.intExceptionFlags(2, 1).orR, 0.U(3.W), conv.io.intExceptionFlags(0))\n\n for (i <- 0 until nIntTypes-1) {\n val w = minXLen << i\n when (cvtType === i.U) {\n val narrow = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, w))\n narrow.io.in := in.in1\n narrow.io.roundingMode := in.rm\n narrow.io.signedOut := ~in.typ(0)\n\n val excSign = in.in1(maxExpWidth + maxSigWidth) && !maxType.isNaN(in.in1)\n val excOut = Cat(conv.io.signedOut === excSign, Fill(w-1, !excSign))\n val invalid = conv.io.intExceptionFlags(2) || narrow.io.intExceptionFlags(1)\n when (invalid) { toint := Cat(conv.io.out >> w, excOut) }\n io.out.bits.exc := Cat(invalid, 0.U(3.W), !invalid && conv.io.intExceptionFlags(0))\n }\n }\n }\n }\n\n io.out.valid := valid\n io.out.bits.lt := dcmp.io.lt || (dcmp.io.a.asSInt < 0.S && dcmp.io.b.asSInt >= 0.S)\n io.out.bits.in := in\n}\n\nclass IntToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {\n val io = IO(new Bundle {\n val in = Flipped(Valid(new IntToFPInput))\n val out = Valid(new FPResult)\n })\n\n val in = Pipe(io.in)\n val tag = in.bits.typeTagIn\n\n val mux = Wire(new FPResult)\n mux.exc := 0.U\n mux.data := recode(in.bits.in1, tag)\n\n val intValue = {\n val res = WireDefault(in.bits.in1.asSInt)\n for (i <- 0 until nIntTypes-1) {\n val smallInt = in.bits.in1((minXLen << i) - 1, 0)\n when (in.bits.typ.extract(log2Ceil(nIntTypes), 1) === i.U) {\n res := Mux(in.bits.typ(0), smallInt.zext, smallInt.asSInt)\n }\n }\n res.asUInt\n }\n\n when (in.bits.wflags) { // fcvt\n // could be improved for RVD/RVQ with a single variable-position rounding\n // unit, rather than N fixed-position ones\n val i2fResults = for (t <- floatTypes) yield {\n val i2f = Module(new hardfloat.INToRecFN(xLen, t.exp, t.sig))\n i2f.io.signedIn := ~in.bits.typ(0)\n i2f.io.in := intValue\n i2f.io.roundingMode := in.bits.rm\n i2f.io.detectTininess := hardfloat.consts.tininess_afterRounding\n (sanitizeNaN(i2f.io.out, t), i2f.io.exceptionFlags)\n }\n\n val (data, exc) = i2fResults.unzip\n val dataPadded = data.init.map(d => Cat(data.last >> d.getWidth, d)) :+ data.last\n mux.data := dataPadded(tag)\n mux.exc := exc(tag)\n }\n\n io.out <> Pipe(in.valid, mux, latency-1)\n}\n\nclass FPToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {\n val io = IO(new Bundle {\n val in = Flipped(Valid(new FPInput))\n val out = Valid(new FPResult)\n val lt = Input(Bool()) // from FPToInt\n })\n\n val in = Pipe(io.in)\n\n val signNum = Mux(in.bits.rm(1), in.bits.in1 ^ in.bits.in2, Mux(in.bits.rm(0), ~in.bits.in2, in.bits.in2))\n val fsgnj = Cat(signNum(fLen), in.bits.in1(fLen-1, 0))\n\n val fsgnjMux = Wire(new FPResult)\n fsgnjMux.exc := 0.U\n fsgnjMux.data := fsgnj\n\n when (in.bits.wflags) { // fmin/fmax\n val isnan1 = maxType.isNaN(in.bits.in1)\n val isnan2 = maxType.isNaN(in.bits.in2)\n val isInvalid = maxType.isSNaN(in.bits.in1) || maxType.isSNaN(in.bits.in2)\n val isNaNOut = isnan1 && isnan2\n val isLHS = isnan2 || in.bits.rm(0) =/= io.lt && !isnan1\n fsgnjMux.exc := isInvalid << 4\n fsgnjMux.data := Mux(isNaNOut, maxType.qNaN, Mux(isLHS, in.bits.in1, in.bits.in2))\n }\n\n val inTag = in.bits.typeTagIn\n val outTag = in.bits.typeTagOut\n val mux = WireDefault(fsgnjMux)\n for (t <- floatTypes.init) {\n when (outTag === typeTag(t).U) {\n mux.data := Cat(fsgnjMux.data >> t.recodedWidth, maxType.unsafeConvert(fsgnjMux.data, t))\n }\n }\n\n when (in.bits.wflags && !in.bits.ren2) { // fcvt\n if (floatTypes.size > 1) {\n // widening conversions simply canonicalize NaN operands\n val widened = Mux(maxType.isNaN(in.bits.in1), maxType.qNaN, in.bits.in1)\n fsgnjMux.data := widened\n fsgnjMux.exc := maxType.isSNaN(in.bits.in1) << 4\n\n // narrowing conversions require rounding (for RVQ, this could be\n // optimized to use a single variable-position rounding unit, rather\n // than two fixed-position ones)\n for (outType <- floatTypes.init) when (outTag === typeTag(outType).U && ((typeTag(outType) == 0).B || outTag < inTag)) {\n val narrower = Module(new hardfloat.RecFNToRecFN(maxType.exp, maxType.sig, outType.exp, outType.sig))\n narrower.io.in := in.bits.in1\n narrower.io.roundingMode := in.bits.rm\n narrower.io.detectTininess := hardfloat.consts.tininess_afterRounding\n val narrowed = sanitizeNaN(narrower.io.out, outType)\n mux.data := Cat(fsgnjMux.data >> narrowed.getWidth, narrowed)\n mux.exc := narrower.io.exceptionFlags\n }\n }\n }\n\n io.out <> Pipe(in.valid, mux, latency-1)\n}\n\nclass MulAddRecFNPipe(latency: Int, expWidth: Int, sigWidth: Int) extends Module\n{\n override def desiredName = s\"MulAddRecFNPipe_l${latency}_e${expWidth}_s${sigWidth}\"\n require(latency<=2)\n\n val io = IO(new Bundle {\n val validin = Input(Bool())\n val op = Input(Bits(2.W))\n val a = Input(Bits((expWidth + sigWidth + 1).W))\n val b = Input(Bits((expWidth + sigWidth + 1).W))\n val c = Input(Bits((expWidth + sigWidth + 1).W))\n val roundingMode = Input(UInt(3.W))\n val detectTininess = Input(UInt(1.W))\n val out = Output(Bits((expWidth + sigWidth + 1).W))\n val exceptionFlags = Output(Bits(5.W))\n val validout = Output(Bool())\n })\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n\n val mulAddRecFNToRaw_preMul = Module(new hardfloat.MulAddRecFNToRaw_preMul(expWidth, sigWidth))\n val mulAddRecFNToRaw_postMul = Module(new hardfloat.MulAddRecFNToRaw_postMul(expWidth, sigWidth))\n\n mulAddRecFNToRaw_preMul.io.op := io.op\n mulAddRecFNToRaw_preMul.io.a := io.a\n mulAddRecFNToRaw_preMul.io.b := io.b\n mulAddRecFNToRaw_preMul.io.c := io.c\n\n val mulAddResult =\n (mulAddRecFNToRaw_preMul.io.mulAddA *\n mulAddRecFNToRaw_preMul.io.mulAddB) +&\n mulAddRecFNToRaw_preMul.io.mulAddC\n\n val valid_stage0 = Wire(Bool())\n val roundingMode_stage0 = Wire(UInt(3.W))\n val detectTininess_stage0 = Wire(UInt(1.W))\n\n val postmul_regs = if(latency>0) 1 else 0\n mulAddRecFNToRaw_postMul.io.fromPreMul := Pipe(io.validin, mulAddRecFNToRaw_preMul.io.toPostMul, postmul_regs).bits\n mulAddRecFNToRaw_postMul.io.mulAddResult := Pipe(io.validin, mulAddResult, postmul_regs).bits\n mulAddRecFNToRaw_postMul.io.roundingMode := Pipe(io.validin, io.roundingMode, postmul_regs).bits\n roundingMode_stage0 := Pipe(io.validin, io.roundingMode, postmul_regs).bits\n detectTininess_stage0 := Pipe(io.validin, io.detectTininess, postmul_regs).bits\n valid_stage0 := Pipe(io.validin, false.B, postmul_regs).valid\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n\n val roundRawFNToRecFN = Module(new hardfloat.RoundRawFNToRecFN(expWidth, sigWidth, 0))\n\n val round_regs = if(latency==2) 1 else 0\n roundRawFNToRecFN.io.invalidExc := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.invalidExc, round_regs).bits\n roundRawFNToRecFN.io.in := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.rawOut, round_regs).bits\n roundRawFNToRecFN.io.roundingMode := Pipe(valid_stage0, roundingMode_stage0, round_regs).bits\n roundRawFNToRecFN.io.detectTininess := Pipe(valid_stage0, detectTininess_stage0, round_regs).bits\n io.validout := Pipe(valid_stage0, false.B, round_regs).valid\n\n roundRawFNToRecFN.io.infiniteExc := false.B\n\n io.out := roundRawFNToRecFN.io.out\n io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags\n}\n\nclass FPUFMAPipe(val latency: Int, val t: FType)\n (implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {\n override def desiredName = s\"FPUFMAPipe_l${latency}_f${t.ieeeWidth}\"\n require(latency>0)\n\n val io = IO(new Bundle {\n val in = Flipped(Valid(new FPInput))\n val out = Valid(new FPResult)\n })\n\n val valid = RegNext(io.in.valid)\n val in = Reg(new FPInput)\n when (io.in.valid) {\n val one = 1.U << (t.sig + t.exp - 1)\n val zero = (io.in.bits.in1 ^ io.in.bits.in2) & (1.U << (t.sig + t.exp))\n val cmd_fma = io.in.bits.ren3\n val cmd_addsub = io.in.bits.swap23\n in := io.in.bits\n when (cmd_addsub) { in.in2 := one }\n when (!(cmd_fma || cmd_addsub)) { in.in3 := zero }\n }\n\n val fma = Module(new MulAddRecFNPipe((latency-1) min 2, t.exp, t.sig))\n fma.io.validin := valid\n fma.io.op := in.fmaCmd\n fma.io.roundingMode := in.rm\n fma.io.detectTininess := hardfloat.consts.tininess_afterRounding\n fma.io.a := in.in1\n fma.io.b := in.in2\n fma.io.c := in.in3\n\n val res = Wire(new FPResult)\n res.data := sanitizeNaN(fma.io.out, t)\n res.exc := fma.io.exceptionFlags\n\n io.out := Pipe(fma.io.validout, res, (latency-3) max 0)\n}\n\nclass FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) {\n val io = IO(new FPUIO)\n\n val (useClockGating, useDebugROB) = coreParams match {\n case r: RocketCoreParams =>\n val sz = if (r.debugROB.isDefined) r.debugROB.get.size else 1\n (r.clockGate, sz < 1)\n case _ => (false, false)\n }\n val clock_en_reg = Reg(Bool())\n val clock_en = clock_en_reg || io.cp_req.valid\n val gated_clock =\n if (!useClockGating) clock\n else ClockGate(clock, clock_en, \"fpu_clock_gate\")\n\n val fp_decoder = Module(new FPUDecoder)\n fp_decoder.io.inst := io.inst\n val id_ctrl = WireInit(fp_decoder.io.sigs)\n coreParams match { case r: RocketCoreParams => r.vector.map(v => {\n val v_decode = v.decoder(p) // Only need to get ren1\n v_decode.io.inst := io.inst\n v_decode.io.vconfig := DontCare // core deals with this\n when (v_decode.io.legal && v_decode.io.read_frs1) {\n id_ctrl.ren1 := true.B\n id_ctrl.swap12 := false.B\n id_ctrl.toint := true.B\n id_ctrl.typeTagIn := I\n id_ctrl.typeTagOut := Mux(io.v_sew === 3.U, D, S)\n }\n when (v_decode.io.write_frd) { id_ctrl.wen := true.B }\n })}\n\n val ex_reg_valid = RegNext(io.valid, false.B)\n val ex_reg_inst = RegEnable(io.inst, io.valid)\n val ex_reg_ctrl = RegEnable(id_ctrl, io.valid)\n val ex_ra = List.fill(3)(Reg(UInt()))\n\n // load/vector response\n val load_wb = RegNext(io.ll_resp_val)\n val load_wb_typeTag = RegEnable(io.ll_resp_type(1,0) - typeTagWbOffset, io.ll_resp_val)\n val load_wb_data = RegEnable(io.ll_resp_data, io.ll_resp_val)\n val load_wb_tag = RegEnable(io.ll_resp_tag, io.ll_resp_val)\n\n class FPUImpl { // entering gated-clock domain\n\n val req_valid = ex_reg_valid || io.cp_req.valid\n val ex_cp_valid = io.cp_req.fire\n val mem_cp_valid = RegNext(ex_cp_valid, false.B)\n val wb_cp_valid = RegNext(mem_cp_valid, false.B)\n val mem_reg_valid = RegInit(false.B)\n val killm = (io.killm || io.nack_mem) && !mem_cp_valid\n // Kill X-stage instruction if M-stage is killed. This prevents it from\n // speculatively being sent to the div-sqrt unit, which can cause priority\n // inversion for two back-to-back divides, the first of which is killed.\n val killx = io.killx || mem_reg_valid && killm\n mem_reg_valid := ex_reg_valid && !killx || ex_cp_valid\n val mem_reg_inst = RegEnable(ex_reg_inst, ex_reg_valid)\n val wb_reg_valid = RegNext(mem_reg_valid && (!killm || mem_cp_valid), false.B)\n\n val cp_ctrl = Wire(new FPUCtrlSigs)\n cp_ctrl :<>= io.cp_req.bits.viewAsSupertype(new FPUCtrlSigs)\n io.cp_resp.valid := false.B\n io.cp_resp.bits.data := 0.U\n io.cp_resp.bits.exc := DontCare\n\n val ex_ctrl = Mux(ex_cp_valid, cp_ctrl, ex_reg_ctrl)\n val mem_ctrl = RegEnable(ex_ctrl, req_valid)\n val wb_ctrl = RegEnable(mem_ctrl, mem_reg_valid)\n\n // CoreMonitorBundle to monitor fp register file writes\n val frfWriteBundle = Seq.fill(2)(WireInit(new CoreMonitorBundle(xLen, fLen), DontCare))\n frfWriteBundle.foreach { i =>\n i.clock := clock\n i.reset := reset\n i.hartid := io.hartid\n i.timer := io.time(31,0)\n i.valid := false.B\n i.wrenx := false.B\n i.wrenf := false.B\n i.excpt := false.B\n }\n\n // regfile\n val regfile = Mem(32, Bits((fLen+1).W))\n when (load_wb) {\n val wdata = recode(load_wb_data, load_wb_typeTag)\n regfile(load_wb_tag) := wdata\n assert(consistent(wdata))\n if (enableCommitLog)\n printf(\"f%d p%d 0x%x\\n\", load_wb_tag, load_wb_tag + 32.U, ieee(wdata))\n if (useDebugROB)\n DebugROB.pushWb(clock, reset, io.hartid, load_wb, load_wb_tag + 32.U, ieee(wdata))\n frfWriteBundle(0).wrdst := load_wb_tag\n frfWriteBundle(0).wrenf := true.B\n frfWriteBundle(0).wrdata := ieee(wdata)\n }\n\n val ex_rs = ex_ra.map(a => regfile(a))\n when (io.valid) {\n when (id_ctrl.ren1) {\n when (!id_ctrl.swap12) { ex_ra(0) := io.inst(19,15) }\n when (id_ctrl.swap12) { ex_ra(1) := io.inst(19,15) }\n }\n when (id_ctrl.ren2) {\n when (id_ctrl.swap12) { ex_ra(0) := io.inst(24,20) }\n when (id_ctrl.swap23) { ex_ra(2) := io.inst(24,20) }\n when (!id_ctrl.swap12 && !id_ctrl.swap23) { ex_ra(1) := io.inst(24,20) }\n }\n when (id_ctrl.ren3) { ex_ra(2) := io.inst(31,27) }\n }\n val ex_rm = Mux(ex_reg_inst(14,12) === 7.U, io.fcsr_rm, ex_reg_inst(14,12))\n\n def fuInput(minT: Option[FType]): FPInput = {\n val req = Wire(new FPInput)\n val tag = ex_ctrl.typeTagIn\n req.viewAsSupertype(new Bundle with HasFPUCtrlSigs) :#= ex_ctrl.viewAsSupertype(new Bundle with HasFPUCtrlSigs)\n req.rm := ex_rm\n req.in1 := unbox(ex_rs(0), tag, minT)\n req.in2 := unbox(ex_rs(1), tag, minT)\n req.in3 := unbox(ex_rs(2), tag, minT)\n req.typ := ex_reg_inst(21,20)\n req.fmt := ex_reg_inst(26,25)\n req.fmaCmd := ex_reg_inst(3,2) | (!ex_ctrl.ren3 && ex_reg_inst(27))\n when (ex_cp_valid) {\n req := io.cp_req.bits\n when (io.cp_req.bits.swap12) {\n req.in1 := io.cp_req.bits.in2\n req.in2 := io.cp_req.bits.in1\n }\n when (io.cp_req.bits.swap23) {\n req.in2 := io.cp_req.bits.in3\n req.in3 := io.cp_req.bits.in2\n }\n }\n req\n }\n\n val sfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.S))\n sfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === S\n sfma.io.in.bits := fuInput(Some(sfma.t))\n\n val fpiu = Module(new FPToInt)\n fpiu.io.in.valid := req_valid && (ex_ctrl.toint || ex_ctrl.div || ex_ctrl.sqrt || (ex_ctrl.fastpipe && ex_ctrl.wflags))\n fpiu.io.in.bits := fuInput(None)\n io.store_data := fpiu.io.out.bits.store\n io.toint_data := fpiu.io.out.bits.toint\n when(fpiu.io.out.valid && mem_cp_valid && mem_ctrl.toint){\n io.cp_resp.bits.data := fpiu.io.out.bits.toint\n io.cp_resp.valid := true.B\n }\n\n val ifpu = Module(new IntToFP(cfg.ifpuLatency))\n ifpu.io.in.valid := req_valid && ex_ctrl.fromint\n ifpu.io.in.bits := fpiu.io.in.bits\n ifpu.io.in.bits.in1 := Mux(ex_cp_valid, io.cp_req.bits.in1, io.fromint_data)\n\n val fpmu = Module(new FPToFP(cfg.fpmuLatency))\n fpmu.io.in.valid := req_valid && ex_ctrl.fastpipe\n fpmu.io.in.bits := fpiu.io.in.bits\n fpmu.io.lt := fpiu.io.out.bits.lt\n\n val divSqrt_wen = WireDefault(false.B)\n val divSqrt_inFlight = WireDefault(false.B)\n val divSqrt_waddr = Reg(UInt(5.W))\n val divSqrt_cp = Reg(Bool())\n val divSqrt_typeTag = Wire(UInt(log2Up(floatTypes.size).W))\n val divSqrt_wdata = Wire(UInt((fLen+1).W))\n val divSqrt_flags = Wire(UInt(FPConstants.FLAGS_SZ.W))\n divSqrt_typeTag := DontCare\n divSqrt_wdata := DontCare\n divSqrt_flags := DontCare\n // writeback arbitration\n case class Pipe(p: Module, lat: Int, cond: (FPUCtrlSigs) => Bool, res: FPResult)\n val pipes = List(\n Pipe(fpmu, fpmu.latency, (c: FPUCtrlSigs) => c.fastpipe, fpmu.io.out.bits),\n Pipe(ifpu, ifpu.latency, (c: FPUCtrlSigs) => c.fromint, ifpu.io.out.bits),\n Pipe(sfma, sfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === S, sfma.io.out.bits)) ++\n (fLen > 32).option({\n val dfma = Module(new FPUFMAPipe(cfg.dfmaLatency, FType.D))\n dfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === D\n dfma.io.in.bits := fuInput(Some(dfma.t))\n Pipe(dfma, dfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === D, dfma.io.out.bits)\n }) ++\n (minFLen == 16).option({\n val hfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.H))\n hfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === H\n hfma.io.in.bits := fuInput(Some(hfma.t))\n Pipe(hfma, hfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === H, hfma.io.out.bits)\n })\n def latencyMask(c: FPUCtrlSigs, offset: Int) = {\n require(pipes.forall(_.lat >= offset))\n pipes.map(p => Mux(p.cond(c), (1 << p.lat-offset).U, 0.U)).reduce(_|_)\n }\n def pipeid(c: FPUCtrlSigs) = pipes.zipWithIndex.map(p => Mux(p._1.cond(c), p._2.U, 0.U)).reduce(_|_)\n val maxLatency = pipes.map(_.lat).max\n val memLatencyMask = latencyMask(mem_ctrl, 2)\n\n class WBInfo extends Bundle {\n val rd = UInt(5.W)\n val typeTag = UInt(log2Up(floatTypes.size).W)\n val cp = Bool()\n val pipeid = UInt(log2Ceil(pipes.size).W)\n }\n\n val wen = RegInit(0.U((maxLatency-1).W))\n val wbInfo = Reg(Vec(maxLatency-1, new WBInfo))\n val mem_wen = mem_reg_valid && (mem_ctrl.fma || mem_ctrl.fastpipe || mem_ctrl.fromint)\n val write_port_busy = RegEnable(mem_wen && (memLatencyMask & latencyMask(ex_ctrl, 1)).orR || (wen & latencyMask(ex_ctrl, 0)).orR, req_valid)\n ccover(mem_reg_valid && write_port_busy, \"WB_STRUCTURAL\", \"structural hazard on writeback\")\n\n for (i <- 0 until maxLatency-2) {\n when (wen(i+1)) { wbInfo(i) := wbInfo(i+1) }\n }\n wen := wen >> 1\n when (mem_wen) {\n when (!killm) {\n wen := wen >> 1 | memLatencyMask\n }\n for (i <- 0 until maxLatency-1) {\n when (!write_port_busy && memLatencyMask(i)) {\n wbInfo(i).cp := mem_cp_valid\n wbInfo(i).typeTag := mem_ctrl.typeTagOut\n wbInfo(i).pipeid := pipeid(mem_ctrl)\n wbInfo(i).rd := mem_reg_inst(11,7)\n }\n }\n }\n\n val waddr = Mux(divSqrt_wen, divSqrt_waddr, wbInfo(0).rd)\n val wb_cp = Mux(divSqrt_wen, divSqrt_cp, wbInfo(0).cp)\n val wtypeTag = Mux(divSqrt_wen, divSqrt_typeTag, wbInfo(0).typeTag)\n val wdata = box(Mux(divSqrt_wen, divSqrt_wdata, (pipes.map(_.res.data): Seq[UInt])(wbInfo(0).pipeid)), wtypeTag)\n val wexc = (pipes.map(_.res.exc): Seq[UInt])(wbInfo(0).pipeid)\n when ((!wbInfo(0).cp && wen(0)) || divSqrt_wen) {\n assert(consistent(wdata))\n regfile(waddr) := wdata\n if (enableCommitLog) {\n printf(\"f%d p%d 0x%x\\n\", waddr, waddr + 32.U, ieee(wdata))\n }\n frfWriteBundle(1).wrdst := waddr\n frfWriteBundle(1).wrenf := true.B\n frfWriteBundle(1).wrdata := ieee(wdata)\n }\n if (useDebugROB) {\n DebugROB.pushWb(clock, reset, io.hartid, (!wbInfo(0).cp && wen(0)) || divSqrt_wen, waddr + 32.U, ieee(wdata))\n }\n\n when (wb_cp && (wen(0) || divSqrt_wen)) {\n io.cp_resp.bits.data := wdata\n io.cp_resp.valid := true.B\n }\n\n assert(!io.cp_req.valid || pipes.forall(_.lat == pipes.head.lat).B,\n s\"FPU only supports coprocessor if FMA pipes have uniform latency ${pipes.map(_.lat)}\")\n // Avoid structural hazards and nacking of external requests\n // toint responds in the MEM stage, so an incoming toint can induce a structural hazard against inflight FMAs\n io.cp_req.ready := !ex_reg_valid && !(cp_ctrl.toint && wen =/= 0.U) && !divSqrt_inFlight\n\n val wb_toint_valid = wb_reg_valid && wb_ctrl.toint\n val wb_toint_exc = RegEnable(fpiu.io.out.bits.exc, mem_ctrl.toint)\n io.fcsr_flags.valid := wb_toint_valid || divSqrt_wen || wen(0)\n io.fcsr_flags.bits :=\n Mux(wb_toint_valid, wb_toint_exc, 0.U) |\n Mux(divSqrt_wen, divSqrt_flags, 0.U) |\n Mux(wen(0), wexc, 0.U)\n\n val divSqrt_write_port_busy = (mem_ctrl.div || mem_ctrl.sqrt) && wen.orR\n io.fcsr_rdy := !(ex_reg_valid && ex_ctrl.wflags || mem_reg_valid && mem_ctrl.wflags || wb_reg_valid && wb_ctrl.toint || wen.orR || divSqrt_inFlight)\n io.nack_mem := (write_port_busy || divSqrt_write_port_busy || divSqrt_inFlight) && !mem_cp_valid\n io.dec <> id_ctrl\n def useScoreboard(f: ((Pipe, Int)) => Bool) = pipes.zipWithIndex.filter(_._1.lat > 3).map(x => f(x)).fold(false.B)(_||_)\n io.sboard_set := wb_reg_valid && !wb_cp_valid && RegNext(useScoreboard(_._1.cond(mem_ctrl)) || mem_ctrl.div || mem_ctrl.sqrt || mem_ctrl.vec)\n io.sboard_clr := !wb_cp_valid && (divSqrt_wen || (wen(0) && useScoreboard(x => wbInfo(0).pipeid === x._2.U)))\n io.sboard_clra := waddr\n ccover(io.sboard_clr && load_wb, \"DUAL_WRITEBACK\", \"load and FMA writeback on same cycle\")\n // we don't currently support round-max-magnitude (rm=4)\n io.illegal_rm := io.inst(14,12).isOneOf(5.U, 6.U) || io.inst(14,12) === 7.U && io.fcsr_rm >= 5.U\n\n if (cfg.divSqrt) {\n val divSqrt_inValid = mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt) && !divSqrt_inFlight\n val divSqrt_killed = RegNext(divSqrt_inValid && killm, true.B)\n when (divSqrt_inValid) {\n divSqrt_waddr := mem_reg_inst(11,7)\n divSqrt_cp := mem_cp_valid\n }\n\n ccover(divSqrt_inFlight && divSqrt_killed, \"DIV_KILLED\", \"divide killed after issued to divider\")\n ccover(divSqrt_inFlight && mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt), \"DIV_BUSY\", \"divider structural hazard\")\n ccover(mem_reg_valid && divSqrt_write_port_busy, \"DIV_WB_STRUCTURAL\", \"structural hazard on division writeback\")\n\n for (t <- floatTypes) {\n val tag = mem_ctrl.typeTagOut\n val divSqrt = withReset(divSqrt_killed) { Module(new hardfloat.DivSqrtRecFN_small(t.exp, t.sig, 0)) }\n divSqrt.io.inValid := divSqrt_inValid && tag === typeTag(t).U\n divSqrt.io.sqrtOp := mem_ctrl.sqrt\n divSqrt.io.a := maxType.unsafeConvert(fpiu.io.out.bits.in.in1, t)\n divSqrt.io.b := maxType.unsafeConvert(fpiu.io.out.bits.in.in2, t)\n divSqrt.io.roundingMode := fpiu.io.out.bits.in.rm\n divSqrt.io.detectTininess := hardfloat.consts.tininess_afterRounding\n\n when (!divSqrt.io.inReady) { divSqrt_inFlight := true.B } // only 1 in flight\n\n when (divSqrt.io.outValid_div || divSqrt.io.outValid_sqrt) {\n divSqrt_wen := !divSqrt_killed\n divSqrt_wdata := sanitizeNaN(divSqrt.io.out, t)\n divSqrt_flags := divSqrt.io.exceptionFlags\n divSqrt_typeTag := typeTag(t).U\n }\n }\n\n when (divSqrt_killed) { divSqrt_inFlight := false.B }\n } else {\n when (id_ctrl.div || id_ctrl.sqrt) { io.illegal_rm := true.B }\n }\n\n // gate the clock\n clock_en_reg := !useClockGating.B ||\n io.keep_clock_enabled || // chicken bit\n io.valid || // ID stage\n req_valid || // EX stage\n mem_reg_valid || mem_cp_valid || // MEM stage\n wb_reg_valid || wb_cp_valid || // WB stage\n wen.orR || divSqrt_inFlight || // post-WB stage\n io.ll_resp_val // load writeback\n\n } // leaving gated-clock domain\n val fpuImpl = withClock (gated_clock) { new FPUImpl }\n\n def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) =\n property.cover(cond, s\"FPU_$label\", \"Core;;\" + desc)\n}\n"},"response":{"kind":"string","value":"module MulAddRecFNPipe_l2_e8_s24_1(\t// @[FPU.scala:633:7]\n input clock,\t// @[FPU.scala:633:7]\n input reset,\t// @[FPU.scala:633:7]\n input io_validin,\t// @[FPU.scala:638:16]\n input [1:0] io_op,\t// @[FPU.scala:638:16]\n input [32:0] io_a,\t// @[FPU.scala:638:16]\n input [32:0] io_b,\t// @[FPU.scala:638:16]\n input [32:0] io_c,\t// @[FPU.scala:638:16]\n input [2:0] io_roundingMode,\t// @[FPU.scala:638:16]\n output [32:0] io_out,\t// @[FPU.scala:638:16]\n output [4:0] io_exceptionFlags,\t// @[FPU.scala:638:16]\n output io_validout\t// @[FPU.scala:638:16]\n);\n\n wire _mulAddRecFNToRaw_postMul_io_invalidExc;\t// @[FPU.scala:655:42]\n wire _mulAddRecFNToRaw_postMul_io_rawOut_isNaN;\t// @[FPU.scala:655:42]\n wire _mulAddRecFNToRaw_postMul_io_rawOut_isInf;\t// @[FPU.scala:655:42]\n wire _mulAddRecFNToRaw_postMul_io_rawOut_isZero;\t// @[FPU.scala:655:42]\n wire _mulAddRecFNToRaw_postMul_io_rawOut_sign;\t// @[FPU.scala:655:42]\n wire [9:0] _mulAddRecFNToRaw_postMul_io_rawOut_sExp;\t// @[FPU.scala:655:42]\n wire [26:0] _mulAddRecFNToRaw_postMul_io_rawOut_sig;\t// @[FPU.scala:655:42]\n wire [23:0] _mulAddRecFNToRaw_preMul_io_mulAddA;\t// @[FPU.scala:654:41]\n wire [23:0] _mulAddRecFNToRaw_preMul_io_mulAddB;\t// @[FPU.scala:654:41]\n wire [47:0] _mulAddRecFNToRaw_preMul_io_mulAddC;\t// @[FPU.scala:654:41]\n wire _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny;\t// @[FPU.scala:654:41]\n wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB;\t// @[FPU.scala:654:41]\n wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfA;\t// @[FPU.scala:654:41]\n wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA;\t// @[FPU.scala:654:41]\n wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfB;\t// @[FPU.scala:654:41]\n wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB;\t// @[FPU.scala:654:41]\n wire _mulAddRecFNToRaw_preMul_io_toPostMul_signProd;\t// @[FPU.scala:654:41]\n wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC;\t// @[FPU.scala:654:41]\n wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfC;\t// @[FPU.scala:654:41]\n wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC;\t// @[FPU.scala:654:41]\n wire [9:0] _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum;\t// @[FPU.scala:654:41]\n wire _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags;\t// @[FPU.scala:654:41]\n wire _mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant;\t// @[FPU.scala:654:41]\n wire [4:0] _mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist;\t// @[FPU.scala:654:41]\n wire [25:0] _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC;\t// @[FPU.scala:654:41]\n wire _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC;\t// @[FPU.scala:654:41]\n wire io_validin_0 = io_validin;\t// @[FPU.scala:633:7]\n wire [1:0] io_op_0 = io_op;\t// @[FPU.scala:633:7]\n wire [32:0] io_a_0 = io_a;\t// @[FPU.scala:633:7]\n wire [32:0] io_b_0 = io_b;\t// @[FPU.scala:633:7]\n wire [32:0] io_c_0 = io_c;\t// @[FPU.scala:633:7]\n wire [2:0] io_roundingMode_0 = io_roundingMode;\t// @[FPU.scala:633:7]\n wire io_detectTininess = 1'h1;\t// @[FPU.scala:633:7]\n wire detectTininess_stage0 = 1'h1;\t// @[FPU.scala:669:37]\n wire detectTininess_stage0_pipe_out_bits = 1'h1;\t// @[Valid.scala:135:21]\n wire valid_stage0_pipe_out_bits = 1'h0;\t// @[Valid.scala:135:21]\n wire io_validout_pipe_out_bits = 1'h0;\t// @[Valid.scala:135:21]\n wire io_validout_pipe_out_valid;\t// @[Valid.scala:135:21]\n wire [32:0] io_out_0;\t// @[FPU.scala:633:7]\n wire [4:0] io_exceptionFlags_0;\t// @[FPU.scala:633:7]\n wire io_validout_0;\t// @[FPU.scala:633:7]\n wire [47:0] _mulAddResult_T = {24'h0, _mulAddRecFNToRaw_preMul_io_mulAddA} * {24'h0, _mulAddRecFNToRaw_preMul_io_mulAddB};\t// @[FPU.scala:654:41, :663:45]\n wire [48:0] mulAddResult = {1'h0, _mulAddResult_T} + {1'h0, _mulAddRecFNToRaw_preMul_io_mulAddC};\t// @[FPU.scala:654:41, :663:45, :664:50]\n wire valid_stage0_pipe_out_valid;\t// @[Valid.scala:135:21]\n wire valid_stage0;\t// @[FPU.scala:667:28]\n wire [2:0] roundingMode_stage0_pipe_out_bits;\t// @[Valid.scala:135:21]\n wire [2:0] roundingMode_stage0;\t// @[FPU.scala:668:35]\n reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v;\t// @[Valid.scala:141:24]\n wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_valid = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v;\t// @[Valid.scala:135:21, :141:24]\n reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isSigNaNAny;\t// @[Valid.scala:142:26]\n wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isSigNaNAny = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isSigNaNAny;\t// @[Valid.scala:135:21, :142:26]\n reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNAOrB;\t// @[Valid.scala:142:26]\n wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isNaNAOrB = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNAOrB;\t// @[Valid.scala:135:21, :142:26]\n reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfA;\t// @[Valid.scala:142:26]\n wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfA = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfA;\t// @[Valid.scala:135:21, :142:26]\n reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroA;\t// @[Valid.scala:142:26]\n wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroA = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroA;\t// @[Valid.scala:135:21, :142:26]\n reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfB;\t// @[Valid.scala:142:26]\n wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfB = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfB;\t// @[Valid.scala:135:21, :142:26]\n reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroB;\t// @[Valid.scala:142:26]\n wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroB = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroB;\t// @[Valid.scala:135:21, :142:26]\n reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_signProd;\t// @[Valid.scala:142:26]\n wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_signProd = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_signProd;\t// @[Valid.scala:135:21, :142:26]\n reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNC;\t// @[Valid.scala:142:26]\n wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isNaNC = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNC;\t// @[Valid.scala:135:21, :142:26]\n reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfC;\t// @[Valid.scala:142:26]\n wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfC = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfC;\t// @[Valid.scala:135:21, :142:26]\n reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroC;\t// @[Valid.scala:142:26]\n wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroC = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroC;\t// @[Valid.scala:135:21, :142:26]\n reg [9:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_sExpSum;\t// @[Valid.scala:142:26]\n wire [9:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_sExpSum = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_sExpSum;\t// @[Valid.scala:135:21, :142:26]\n reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_doSubMags;\t// @[Valid.scala:142:26]\n wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_doSubMags = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_doSubMags;\t// @[Valid.scala:135:21, :142:26]\n reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CIsDominant;\t// @[Valid.scala:142:26]\n wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_CIsDominant = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CIsDominant;\t// @[Valid.scala:135:21, :142:26]\n reg [4:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CDom_CAlignDist;\t// @[Valid.scala:142:26]\n wire [4:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_CDom_CAlignDist = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CDom_CAlignDist;\t// @[Valid.scala:135:21, :142:26]\n reg [25:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_highAlignedSigC;\t// @[Valid.scala:142:26]\n wire [25:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_highAlignedSigC = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_highAlignedSigC;\t// @[Valid.scala:135:21, :142:26]\n reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_bit0AlignedSigC;\t// @[Valid.scala:142:26]\n wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_bit0AlignedSigC = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_bit0AlignedSigC;\t// @[Valid.scala:135:21, :142:26]\n reg mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v;\t// @[Valid.scala:141:24]\n wire mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out_valid = mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v;\t// @[Valid.scala:135:21, :141:24]\n reg [48:0] mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b;\t// @[Valid.scala:142:26]\n wire [48:0] mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out_bits = mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b;\t// @[Valid.scala:135:21, :142:26]\n reg mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v;\t// @[Valid.scala:141:24]\n wire mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out_valid = mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v;\t// @[Valid.scala:135:21, :141:24]\n reg [2:0] mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b;\t// @[Valid.scala:142:26]\n wire [2:0] mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out_bits = mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b;\t// @[Valid.scala:135:21, :142:26]\n reg roundingMode_stage0_pipe_v;\t// @[Valid.scala:141:24]\n wire roundingMode_stage0_pipe_out_valid = roundingMode_stage0_pipe_v;\t// @[Valid.scala:135:21, :141:24]\n reg [2:0] roundingMode_stage0_pipe_b;\t// @[Valid.scala:142:26]\n assign roundingMode_stage0_pipe_out_bits = roundingMode_stage0_pipe_b;\t// @[Valid.scala:135:21, :142:26]\n assign roundingMode_stage0 = roundingMode_stage0_pipe_out_bits;\t// @[Valid.scala:135:21]\n reg detectTininess_stage0_pipe_v;\t// @[Valid.scala:141:24]\n wire detectTininess_stage0_pipe_out_valid = detectTininess_stage0_pipe_v;\t// @[Valid.scala:135:21, :141:24]\n reg valid_stage0_pipe_v;\t// @[Valid.scala:141:24]\n assign valid_stage0_pipe_out_valid = valid_stage0_pipe_v;\t// @[Valid.scala:135:21, :141:24]\n assign valid_stage0 = valid_stage0_pipe_out_valid;\t// @[Valid.scala:135:21]\n reg roundRawFNToRecFN_io_invalidExc_pipe_v;\t// @[Valid.scala:141:24]\n wire roundRawFNToRecFN_io_invalidExc_pipe_out_valid = roundRawFNToRecFN_io_invalidExc_pipe_v;\t// @[Valid.scala:135:21, :141:24]\n reg roundRawFNToRecFN_io_invalidExc_pipe_b;\t// @[Valid.scala:142:26]\n wire roundRawFNToRecFN_io_invalidExc_pipe_out_bits = roundRawFNToRecFN_io_invalidExc_pipe_b;\t// @[Valid.scala:135:21, :142:26]\n reg roundRawFNToRecFN_io_in_pipe_v;\t// @[Valid.scala:141:24]\n wire roundRawFNToRecFN_io_in_pipe_out_valid = roundRawFNToRecFN_io_in_pipe_v;\t// @[Valid.scala:135:21, :141:24]\n reg roundRawFNToRecFN_io_in_pipe_b_isNaN;\t// @[Valid.scala:142:26]\n wire roundRawFNToRecFN_io_in_pipe_out_bits_isNaN = roundRawFNToRecFN_io_in_pipe_b_isNaN;\t// @[Valid.scala:135:21, :142:26]\n reg roundRawFNToRecFN_io_in_pipe_b_isInf;\t// @[Valid.scala:142:26]\n wire roundRawFNToRecFN_io_in_pipe_out_bits_isInf = roundRawFNToRecFN_io_in_pipe_b_isInf;\t// @[Valid.scala:135:21, :142:26]\n reg roundRawFNToRecFN_io_in_pipe_b_isZero;\t// @[Valid.scala:142:26]\n wire roundRawFNToRecFN_io_in_pipe_out_bits_isZero = roundRawFNToRecFN_io_in_pipe_b_isZero;\t// @[Valid.scala:135:21, :142:26]\n reg roundRawFNToRecFN_io_in_pipe_b_sign;\t// @[Valid.scala:142:26]\n wire roundRawFNToRecFN_io_in_pipe_out_bits_sign = roundRawFNToRecFN_io_in_pipe_b_sign;\t// @[Valid.scala:135:21, :142:26]\n reg [9:0] roundRawFNToRecFN_io_in_pipe_b_sExp;\t// @[Valid.scala:142:26]\n wire [9:0] roundRawFNToRecFN_io_in_pipe_out_bits_sExp = roundRawFNToRecFN_io_in_pipe_b_sExp;\t// @[Valid.scala:135:21, :142:26]\n reg [26:0] roundRawFNToRecFN_io_in_pipe_b_sig;\t// @[Valid.scala:142:26]\n wire [26:0] roundRawFNToRecFN_io_in_pipe_out_bits_sig = roundRawFNToRecFN_io_in_pipe_b_sig;\t// @[Valid.scala:135:21, :142:26]\n reg roundRawFNToRecFN_io_roundingMode_pipe_v;\t// @[Valid.scala:141:24]\n wire roundRawFNToRecFN_io_roundingMode_pipe_out_valid = roundRawFNToRecFN_io_roundingMode_pipe_v;\t// @[Valid.scala:135:21, :141:24]\n reg [2:0] roundRawFNToRecFN_io_roundingMode_pipe_b;\t// @[Valid.scala:142:26]\n wire [2:0] roundRawFNToRecFN_io_roundingMode_pipe_out_bits = roundRawFNToRecFN_io_roundingMode_pipe_b;\t// @[Valid.scala:135:21, :142:26]\n reg roundRawFNToRecFN_io_detectTininess_pipe_v;\t// @[Valid.scala:141:24]\n wire roundRawFNToRecFN_io_detectTininess_pipe_out_valid = roundRawFNToRecFN_io_detectTininess_pipe_v;\t// @[Valid.scala:135:21, :141:24]\n reg roundRawFNToRecFN_io_detectTininess_pipe_b;\t// @[Valid.scala:142:26]\n wire roundRawFNToRecFN_io_detectTininess_pipe_out_bits = roundRawFNToRecFN_io_detectTininess_pipe_b;\t// @[Valid.scala:135:21, :142:26]\n reg io_validout_pipe_v;\t// @[Valid.scala:141:24]\n assign io_validout_pipe_out_valid = io_validout_pipe_v;\t// @[Valid.scala:135:21, :141:24]\n assign io_validout_0 = io_validout_pipe_out_valid;\t// @[Valid.scala:135:21]\n always @(posedge clock) begin\t// @[FPU.scala:633:7]\n if (reset) begin\t// @[FPU.scala:633:7]\n mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v <= 1'h0;\t// @[Valid.scala:141:24]\n mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v <= 1'h0;\t// @[Valid.scala:141:24]\n mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v <= 1'h0;\t// @[Valid.scala:141:24]\n roundingMode_stage0_pipe_v <= 1'h0;\t// @[Valid.scala:141:24]\n detectTininess_stage0_pipe_v <= 1'h0;\t// @[Valid.scala:141:24]\n valid_stage0_pipe_v <= 1'h0;\t// @[Valid.scala:141:24]\n roundRawFNToRecFN_io_invalidExc_pipe_v <= 1'h0;\t// @[Valid.scala:141:24]\n roundRawFNToRecFN_io_in_pipe_v <= 1'h0;\t// @[Valid.scala:141:24]\n roundRawFNToRecFN_io_roundingMode_pipe_v <= 1'h0;\t// @[Valid.scala:141:24]\n roundRawFNToRecFN_io_detectTininess_pipe_v <= 1'h0;\t// @[Valid.scala:141:24]\n io_validout_pipe_v <= 1'h0;\t// @[Valid.scala:141:24]\n end\n else begin\t// @[FPU.scala:633:7]\n mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v <= io_validin_0;\t// @[Valid.scala:141:24]\n mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v <= io_validin_0;\t// @[Valid.scala:141:24]\n mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v <= io_validin_0;\t// @[Valid.scala:141:24]\n roundingMode_stage0_pipe_v <= io_validin_0;\t// @[Valid.scala:141:24]\n detectTininess_stage0_pipe_v <= io_validin_0;\t// @[Valid.scala:141:24]\n valid_stage0_pipe_v <= io_validin_0;\t// @[Valid.scala:141:24]\n roundRawFNToRecFN_io_invalidExc_pipe_v <= valid_stage0;\t// @[Valid.scala:141:24]\n roundRawFNToRecFN_io_in_pipe_v <= valid_stage0;\t// @[Valid.scala:141:24]\n roundRawFNToRecFN_io_roundingMode_pipe_v <= valid_stage0;\t// @[Valid.scala:141:24]\n roundRawFNToRecFN_io_detectTininess_pipe_v <= valid_stage0;\t// @[Valid.scala:141:24]\n io_validout_pipe_v <= valid_stage0;\t// @[Valid.scala:141:24]\n end\n if (io_validin_0) begin\t// @[FPU.scala:633:7]\n mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isSigNaNAny <= _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny;\t// @[Valid.scala:142:26]\n mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNAOrB <= _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB;\t// @[Valid.scala:142:26]\n mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfA <= _mulAddRecFNToRaw_preMul_io_toPostMul_isInfA;\t// @[Valid.scala:142:26]\n mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroA <= _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA;\t// @[Valid.scala:142:26]\n mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfB <= _mulAddRecFNToRaw_preMul_io_toPostMul_isInfB;\t// @[Valid.scala:142:26]\n mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroB <= _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB;\t// @[Valid.scala:142:26]\n mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_signProd <= _mulAddRecFNToRaw_preMul_io_toPostMul_signProd;\t// @[Valid.scala:142:26]\n mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNC <= _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC;\t// @[Valid.scala:142:26]\n mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfC <= _mulAddRecFNToRaw_preMul_io_toPostMul_isInfC;\t// @[Valid.scala:142:26]\n mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroC <= _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC;\t// @[Valid.scala:142:26]\n mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_sExpSum <= _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum;\t// @[Valid.scala:142:26]\n mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_doSubMags <= _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags;\t// @[Valid.scala:142:26]\n mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CIsDominant <= _mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant;\t// @[Valid.scala:142:26]\n mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CDom_CAlignDist <= _mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist;\t// @[Valid.scala:142:26]\n mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_highAlignedSigC <= _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC;\t// @[Valid.scala:142:26]\n mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_bit0AlignedSigC <= _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC;\t// @[Valid.scala:142:26]\n mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b <= mulAddResult;\t// @[Valid.scala:142:26]\n mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b <= io_roundingMode_0;\t// @[Valid.scala:142:26]\n roundingMode_stage0_pipe_b <= io_roundingMode_0;\t// @[Valid.scala:142:26]\n end\n if (valid_stage0) begin\t// @[FPU.scala:667:28]\n roundRawFNToRecFN_io_invalidExc_pipe_b <= _mulAddRecFNToRaw_postMul_io_invalidExc;\t// @[Valid.scala:142:26]\n roundRawFNToRecFN_io_in_pipe_b_isNaN <= _mulAddRecFNToRaw_postMul_io_rawOut_isNaN;\t// @[Valid.scala:142:26]\n roundRawFNToRecFN_io_in_pipe_b_isInf <= _mulAddRecFNToRaw_postMul_io_rawOut_isInf;\t// @[Valid.scala:142:26]\n roundRawFNToRecFN_io_in_pipe_b_isZero <= _mulAddRecFNToRaw_postMul_io_rawOut_isZero;\t// @[Valid.scala:142:26]\n roundRawFNToRecFN_io_in_pipe_b_sign <= _mulAddRecFNToRaw_postMul_io_rawOut_sign;\t// @[Valid.scala:142:26]\n roundRawFNToRecFN_io_in_pipe_b_sExp <= _mulAddRecFNToRaw_postMul_io_rawOut_sExp;\t// @[Valid.scala:142:26]\n roundRawFNToRecFN_io_in_pipe_b_sig <= _mulAddRecFNToRaw_postMul_io_rawOut_sig;\t// @[Valid.scala:142:26]\n roundRawFNToRecFN_io_roundingMode_pipe_b <= roundingMode_stage0;\t// @[Valid.scala:142:26]\n end\n roundRawFNToRecFN_io_detectTininess_pipe_b <= valid_stage0 | roundRawFNToRecFN_io_detectTininess_pipe_b;\t// @[Valid.scala:142:26]\n always @(posedge)\n MulAddRecFNToRaw_preMul_e8_s24_1 mulAddRecFNToRaw_preMul (\t// @[FPU.scala:654:41]\n .io_op (io_op_0),\t// @[FPU.scala:633:7]\n .io_a (io_a_0),\t// @[FPU.scala:633:7]\n .io_b (io_b_0),\t// @[FPU.scala:633:7]\n .io_c (io_c_0),\t// @[FPU.scala:633:7]\n .io_mulAddA (_mulAddRecFNToRaw_preMul_io_mulAddA),\n .io_mulAddB (_mulAddRecFNToRaw_preMul_io_mulAddB),\n .io_mulAddC (_mulAddRecFNToRaw_preMul_io_mulAddC),\n .io_toPostMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny),\n .io_toPostMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB),\n .io_toPostMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA),\n .io_toPostMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA),\n .io_toPostMul_isInfB (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfB),\n .io_toPostMul_isZeroB (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB),\n .io_toPostMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd),\n .io_toPostMul_isNaNC (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC),\n .io_toPostMul_isInfC (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfC),\n .io_toPostMul_isZeroC (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC),\n .io_toPostMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum),\n .io_toPostMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags),\n .io_toPostMul_CIsDominant (_mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant),\n .io_toPostMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist),\n .io_toPostMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC),\n .io_toPostMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC)\n );\t// @[FPU.scala:654:41]\n MulAddRecFNToRaw_postMul_e8_s24_1 mulAddRecFNToRaw_postMul (\t// @[FPU.scala:655:42]\n .io_fromPreMul_isSigNaNAny (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isSigNaNAny),\t// @[Valid.scala:135:21]\n .io_fromPreMul_isNaNAOrB (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isNaNAOrB),\t// @[Valid.scala:135:21]\n .io_fromPreMul_isInfA (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfA),\t// @[Valid.scala:135:21]\n .io_fromPreMul_isZeroA (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroA),\t// @[Valid.scala:135:21]\n .io_fromPreMul_isInfB (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfB),\t// @[Valid.scala:135:21]\n .io_fromPreMul_isZeroB (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroB),\t// @[Valid.scala:135:21]\n .io_fromPreMul_signProd (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_signProd),\t// @[Valid.scala:135:21]\n .io_fromPreMul_isNaNC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isNaNC),\t// @[Valid.scala:135:21]\n .io_fromPreMul_isInfC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfC),\t// @[Valid.scala:135:21]\n .io_fromPreMul_isZeroC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroC),\t// @[Valid.scala:135:21]\n .io_fromPreMul_sExpSum (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_sExpSum),\t// @[Valid.scala:135:21]\n .io_fromPreMul_doSubMags (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_doSubMags),\t// @[Valid.scala:135:21]\n .io_fromPreMul_CIsDominant (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_CIsDominant),\t// @[Valid.scala:135:21]\n .io_fromPreMul_CDom_CAlignDist (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_CDom_CAlignDist),\t// @[Valid.scala:135:21]\n .io_fromPreMul_highAlignedSigC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_highAlignedSigC),\t// @[Valid.scala:135:21]\n .io_fromPreMul_bit0AlignedSigC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_bit0AlignedSigC),\t// @[Valid.scala:135:21]\n .io_mulAddResult (mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out_bits),\t// @[Valid.scala:135:21]\n .io_roundingMode (mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out_bits),\t// @[Valid.scala:135:21]\n .io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc),\n .io_rawOut_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN),\n .io_rawOut_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf),\n .io_rawOut_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero),\n .io_rawOut_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign),\n .io_rawOut_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp),\n .io_rawOut_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig)\n );\t// @[FPU.scala:655:42]\n RoundRawFNToRecFN_e8_s24_1 roundRawFNToRecFN (\t// @[FPU.scala:682:35]\n .io_invalidExc (roundRawFNToRecFN_io_invalidExc_pipe_out_bits),\t// @[Valid.scala:135:21]\n .io_in_isNaN (roundRawFNToRecFN_io_in_pipe_out_bits_isNaN),\t// @[Valid.scala:135:21]\n .io_in_isInf (roundRawFNToRecFN_io_in_pipe_out_bits_isInf),\t// @[Valid.scala:135:21]\n .io_in_isZero (roundRawFNToRecFN_io_in_pipe_out_bits_isZero),\t// @[Valid.scala:135:21]\n .io_in_sign (roundRawFNToRecFN_io_in_pipe_out_bits_sign),\t// @[Valid.scala:135:21]\n .io_in_sExp (roundRawFNToRecFN_io_in_pipe_out_bits_sExp),\t// @[Valid.scala:135:21]\n .io_in_sig (roundRawFNToRecFN_io_in_pipe_out_bits_sig),\t// @[Valid.scala:135:21]\n .io_roundingMode (roundRawFNToRecFN_io_roundingMode_pipe_out_bits),\t// @[Valid.scala:135:21]\n .io_detectTininess (roundRawFNToRecFN_io_detectTininess_pipe_out_bits),\t// @[Valid.scala:135:21]\n .io_out (io_out_0),\n .io_exceptionFlags (io_exceptionFlags_0)\n );\t// @[FPU.scala:682:35]\n assign io_out = io_out_0;\t// @[FPU.scala:633:7]\n assign io_exceptionFlags = io_exceptionFlags_0;\t// @[FPU.scala:633:7]\n assign io_validout = io_validout_0;\t// @[FPU.scala:633:7]\nendmodule"}}},{"rowIdx":575,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to the following Chisel files.\nFile MSHR.scala:\n/*\n * Copyright 2019 SiFive, Inc.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You should have received a copy of LICENSE.Apache2 along with\n * this software. If not, you may obtain a copy at\n *\n * https://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\npackage sifive.blocks.inclusivecache\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.experimental.SourceInfo\nimport freechips.rocketchip.tilelink._\nimport TLPermissions._\nimport TLMessages._\nimport MetaData._\nimport chisel3.PrintableHelper\nimport chisel3.experimental.dataview._\n\nclass ScheduleRequest(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params)\n{\n val a = Valid(new SourceARequest(params))\n val b = Valid(new SourceBRequest(params))\n val c = Valid(new SourceCRequest(params))\n val d = Valid(new SourceDRequest(params))\n val e = Valid(new SourceERequest(params))\n val x = Valid(new SourceXRequest(params))\n val dir = Valid(new DirectoryWrite(params))\n val reload = Bool() // get next request via allocate (if any)\n}\n\nclass MSHRStatus(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params)\n{\n val set = UInt(params.setBits.W)\n val tag = UInt(params.tagBits.W)\n val way = UInt(params.wayBits.W)\n val blockB = Bool()\n val nestB = Bool()\n val blockC = Bool()\n val nestC = Bool()\n}\n\nclass NestedWriteback(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params)\n{\n val set = UInt(params.setBits.W)\n val tag = UInt(params.tagBits.W)\n val b_toN = Bool() // nested Probes may unhit us\n val b_toB = Bool() // nested Probes may demote us\n val b_clr_dirty = Bool() // nested Probes clear dirty\n val c_set_dirty = Bool() // nested Releases MAY set dirty\n}\n\nsealed trait CacheState\n{\n val code = CacheState.index.U\n CacheState.index = CacheState.index + 1\n}\n\nobject CacheState\n{\n var index = 0\n}\n\ncase object S_INVALID extends CacheState\ncase object S_BRANCH extends CacheState\ncase object S_BRANCH_C extends CacheState\ncase object S_TIP extends CacheState\ncase object S_TIP_C extends CacheState\ncase object S_TIP_CD extends CacheState\ncase object S_TIP_D extends CacheState\ncase object S_TRUNK_C extends CacheState\ncase object S_TRUNK_CD extends CacheState\n\nclass MSHR(params: InclusiveCacheParameters) extends Module\n{\n val io = IO(new Bundle {\n val allocate = Flipped(Valid(new AllocateRequest(params))) // refills MSHR for next cycle\n val directory = Flipped(Valid(new DirectoryResult(params))) // triggers schedule setup\n val status = Valid(new MSHRStatus(params))\n val schedule = Decoupled(new ScheduleRequest(params))\n val sinkc = Flipped(Valid(new SinkCResponse(params)))\n val sinkd = Flipped(Valid(new SinkDResponse(params)))\n val sinke = Flipped(Valid(new SinkEResponse(params)))\n val nestedwb = Flipped(new NestedWriteback(params))\n })\n\n val request_valid = RegInit(false.B)\n val request = Reg(new FullRequest(params))\n val meta_valid = RegInit(false.B)\n val meta = Reg(new DirectoryResult(params))\n\n // Define which states are valid\n when (meta_valid) {\n when (meta.state === INVALID) {\n assert (!meta.clients.orR)\n assert (!meta.dirty)\n }\n when (meta.state === BRANCH) {\n assert (!meta.dirty)\n }\n when (meta.state === TRUNK) {\n assert (meta.clients.orR)\n assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one\n }\n when (meta.state === TIP) {\n // noop\n }\n }\n\n // Completed transitions (s_ = scheduled), (w_ = waiting)\n val s_rprobe = RegInit(true.B) // B\n val w_rprobeackfirst = RegInit(true.B)\n val w_rprobeacklast = RegInit(true.B)\n val s_release = RegInit(true.B) // CW w_rprobeackfirst\n val w_releaseack = RegInit(true.B)\n val s_pprobe = RegInit(true.B) // B\n val s_acquire = RegInit(true.B) // A s_release, s_pprobe [1]\n val s_flush = RegInit(true.B) // X w_releaseack\n val w_grantfirst = RegInit(true.B)\n val w_grantlast = RegInit(true.B)\n val w_grant = RegInit(true.B) // first | last depending on wormhole\n val w_pprobeackfirst = RegInit(true.B)\n val w_pprobeacklast = RegInit(true.B)\n val w_pprobeack = RegInit(true.B) // first | last depending on wormhole\n val s_probeack = RegInit(true.B) // C w_pprobeackfirst (mutually exclusive with next two s_*)\n val s_grantack = RegInit(true.B) // E w_grantfirst ... CAN require both outE&inD to service outD\n val s_execute = RegInit(true.B) // D w_pprobeack, w_grant\n val w_grantack = RegInit(true.B)\n val s_writeback = RegInit(true.B) // W w_*\n\n // [1]: We cannot issue outer Acquire while holding blockB (=> outA can stall)\n // However, inB and outC are higher priority than outB, so s_release and s_pprobe\n // may be safely issued while blockB. Thus we must NOT try to schedule the\n // potentially stuck s_acquire with either of them (scheduler is all or none).\n\n // Meta-data that we discover underway\n val sink = Reg(UInt(params.outer.bundle.sinkBits.W))\n val gotT = Reg(Bool())\n val bad_grant = Reg(Bool())\n val probes_done = Reg(UInt(params.clientBits.W))\n val probes_toN = Reg(UInt(params.clientBits.W))\n val probes_noT = Reg(Bool())\n\n // When a nested transaction completes, update our meta data\n when (meta_valid && meta.state =/= INVALID &&\n io.nestedwb.set === request.set && io.nestedwb.tag === meta.tag) {\n when (io.nestedwb.b_clr_dirty) { meta.dirty := false.B }\n when (io.nestedwb.c_set_dirty) { meta.dirty := true.B }\n when (io.nestedwb.b_toB) { meta.state := BRANCH }\n when (io.nestedwb.b_toN) { meta.hit := false.B }\n }\n\n // Scheduler status\n io.status.valid := request_valid\n io.status.bits.set := request.set\n io.status.bits.tag := request.tag\n io.status.bits.way := meta.way\n io.status.bits.blockB := !meta_valid || ((!w_releaseack || !w_rprobeacklast || !w_pprobeacklast) && !w_grantfirst)\n io.status.bits.nestB := meta_valid && w_releaseack && w_rprobeacklast && w_pprobeacklast && !w_grantfirst\n // The above rules ensure we will block and not nest an outer probe while still doing our\n // own inner probes. Thus every probe wakes exactly one MSHR.\n io.status.bits.blockC := !meta_valid\n io.status.bits.nestC := meta_valid && (!w_rprobeackfirst || !w_pprobeackfirst || !w_grantfirst)\n // The w_grantfirst in nestC is necessary to deal with:\n // acquire waiting for grant, inner release gets queued, outer probe -> inner probe -> deadlock\n // ... this is possible because the release+probe can be for same set, but different tag\n\n // We can only demand: block, nest, or queue\n assert (!io.status.bits.nestB || !io.status.bits.blockB)\n assert (!io.status.bits.nestC || !io.status.bits.blockC)\n\n // Scheduler requests\n val no_wait = w_rprobeacklast && w_releaseack && w_grantlast && w_pprobeacklast && w_grantack\n io.schedule.bits.a.valid := !s_acquire && s_release && s_pprobe\n io.schedule.bits.b.valid := !s_rprobe || !s_pprobe\n io.schedule.bits.c.valid := (!s_release && w_rprobeackfirst) || (!s_probeack && w_pprobeackfirst)\n io.schedule.bits.d.valid := !s_execute && w_pprobeack && w_grant\n io.schedule.bits.e.valid := !s_grantack && w_grantfirst\n io.schedule.bits.x.valid := !s_flush && w_releaseack\n io.schedule.bits.dir.valid := (!s_release && w_rprobeackfirst) || (!s_writeback && no_wait)\n io.schedule.bits.reload := no_wait\n io.schedule.valid := io.schedule.bits.a.valid || io.schedule.bits.b.valid || io.schedule.bits.c.valid ||\n io.schedule.bits.d.valid || io.schedule.bits.e.valid || io.schedule.bits.x.valid ||\n io.schedule.bits.dir.valid\n\n // Schedule completions\n when (io.schedule.ready) {\n s_rprobe := true.B\n when (w_rprobeackfirst) { s_release := true.B }\n s_pprobe := true.B\n when (s_release && s_pprobe) { s_acquire := true.B }\n when (w_releaseack) { s_flush := true.B }\n when (w_pprobeackfirst) { s_probeack := true.B }\n when (w_grantfirst) { s_grantack := true.B }\n when (w_pprobeack && w_grant) { s_execute := true.B }\n when (no_wait) { s_writeback := true.B }\n // Await the next operation\n when (no_wait) {\n request_valid := false.B\n meta_valid := false.B\n }\n }\n\n // Resulting meta-data\n val final_meta_writeback = WireInit(meta)\n\n val req_clientBit = params.clientBit(request.source)\n val req_needT = needT(request.opcode, request.param)\n val req_acquire = request.opcode === AcquireBlock || request.opcode === AcquirePerm\n val meta_no_clients = !meta.clients.orR\n val req_promoteT = req_acquire && Mux(meta.hit, meta_no_clients && meta.state === TIP, gotT)\n\n when (request.prio(2) && (!params.firstLevel).B) { // always a hit\n final_meta_writeback.dirty := meta.dirty || request.opcode(0)\n final_meta_writeback.state := Mux(request.param =/= TtoT && meta.state === TRUNK, TIP, meta.state)\n final_meta_writeback.clients := meta.clients & ~Mux(isToN(request.param), req_clientBit, 0.U)\n final_meta_writeback.hit := true.B // chained requests are hits\n } .elsewhen (request.control && params.control.B) { // request.prio(0)\n when (meta.hit) {\n final_meta_writeback.dirty := false.B\n final_meta_writeback.state := INVALID\n final_meta_writeback.clients := meta.clients & ~probes_toN\n }\n final_meta_writeback.hit := false.B\n } .otherwise {\n final_meta_writeback.dirty := (meta.hit && meta.dirty) || !request.opcode(2)\n final_meta_writeback.state := Mux(req_needT,\n Mux(req_acquire, TRUNK, TIP),\n Mux(!meta.hit, Mux(gotT, Mux(req_acquire, TRUNK, TIP), BRANCH),\n MuxLookup(meta.state, 0.U(2.W))(Seq(\n INVALID -> BRANCH,\n BRANCH -> BRANCH,\n TRUNK -> TIP,\n TIP -> Mux(meta_no_clients && req_acquire, TRUNK, TIP)))))\n final_meta_writeback.clients := Mux(meta.hit, meta.clients & ~probes_toN, 0.U) |\n Mux(req_acquire, req_clientBit, 0.U)\n final_meta_writeback.tag := request.tag\n final_meta_writeback.hit := true.B\n }\n\n when (bad_grant) {\n when (meta.hit) {\n // upgrade failed (B -> T)\n assert (!meta_valid || meta.state === BRANCH)\n final_meta_writeback.hit := true.B\n final_meta_writeback.dirty := false.B\n final_meta_writeback.state := BRANCH\n final_meta_writeback.clients := meta.clients & ~probes_toN\n } .otherwise {\n // failed N -> (T or B)\n final_meta_writeback.hit := false.B\n final_meta_writeback.dirty := false.B\n final_meta_writeback.state := INVALID\n final_meta_writeback.clients := 0.U\n }\n }\n\n val invalid = Wire(new DirectoryEntry(params))\n invalid.dirty := false.B\n invalid.state := INVALID\n invalid.clients := 0.U\n invalid.tag := 0.U\n\n // Just because a client says BtoT, by the time we process the request he may be N.\n // Therefore, we must consult our own meta-data state to confirm he owns the line still.\n val honour_BtoT = meta.hit && (meta.clients & req_clientBit).orR\n\n // The client asking us to act is proof they don't have permissions.\n val excluded_client = Mux(meta.hit && request.prio(0) && skipProbeN(request.opcode, params.cache.hintsSkipProbe), req_clientBit, 0.U)\n io.schedule.bits.a.bits.tag := request.tag\n io.schedule.bits.a.bits.set := request.set\n io.schedule.bits.a.bits.param := Mux(req_needT, Mux(meta.hit, BtoT, NtoT), NtoB)\n io.schedule.bits.a.bits.block := request.size =/= log2Ceil(params.cache.blockBytes).U ||\n !(request.opcode === PutFullData || request.opcode === AcquirePerm)\n io.schedule.bits.a.bits.source := 0.U\n io.schedule.bits.b.bits.param := Mux(!s_rprobe, toN, Mux(request.prio(1), request.param, Mux(req_needT, toN, toB)))\n io.schedule.bits.b.bits.tag := Mux(!s_rprobe, meta.tag, request.tag)\n io.schedule.bits.b.bits.set := request.set\n io.schedule.bits.b.bits.clients := meta.clients & ~excluded_client\n io.schedule.bits.c.bits.opcode := Mux(meta.dirty, ReleaseData, Release)\n io.schedule.bits.c.bits.param := Mux(meta.state === BRANCH, BtoN, TtoN)\n io.schedule.bits.c.bits.source := 0.U\n io.schedule.bits.c.bits.tag := meta.tag\n io.schedule.bits.c.bits.set := request.set\n io.schedule.bits.c.bits.way := meta.way\n io.schedule.bits.c.bits.dirty := meta.dirty\n io.schedule.bits.d.bits.viewAsSupertype(chiselTypeOf(request)) := request\n io.schedule.bits.d.bits.param := Mux(!req_acquire, request.param,\n MuxLookup(request.param, request.param)(Seq(\n NtoB -> Mux(req_promoteT, NtoT, NtoB),\n BtoT -> Mux(honour_BtoT, BtoT, NtoT),\n NtoT -> NtoT)))\n io.schedule.bits.d.bits.sink := 0.U\n io.schedule.bits.d.bits.way := meta.way\n io.schedule.bits.d.bits.bad := bad_grant\n io.schedule.bits.e.bits.sink := sink\n io.schedule.bits.x.bits.fail := false.B\n io.schedule.bits.dir.bits.set := request.set\n io.schedule.bits.dir.bits.way := meta.way\n io.schedule.bits.dir.bits.data := Mux(!s_release, invalid, WireInit(new DirectoryEntry(params), init = final_meta_writeback))\n\n // Coverage of state transitions\n def cacheState(entry: DirectoryEntry, hit: Bool) = {\n val out = WireDefault(0.U)\n val c = entry.clients.orR\n val d = entry.dirty\n switch (entry.state) {\n is (BRANCH) { out := Mux(c, S_BRANCH_C.code, S_BRANCH.code) }\n is (TRUNK) { out := Mux(d, S_TRUNK_CD.code, S_TRUNK_C.code) }\n is (TIP) { out := Mux(c, Mux(d, S_TIP_CD.code, S_TIP_C.code), Mux(d, S_TIP_D.code, S_TIP.code)) }\n is (INVALID) { out := S_INVALID.code }\n }\n when (!hit) { out := S_INVALID.code }\n out\n }\n\n val p = !params.lastLevel // can be probed\n val c = !params.firstLevel // can be acquired\n val m = params.inner.client.clients.exists(!_.supports.probe) // can be written (or read)\n val r = params.outer.manager.managers.exists(!_.alwaysGrantsT) // read-only devices exist\n val f = params.control // flush control register exists\n val cfg = (p, c, m, r, f)\n val b = r || p // can reach branch state (via probe downgrade or read-only device)\n\n // The cache must be used for something or we would not be here\n require(c || m)\n\n val evict = cacheState(meta, !meta.hit)\n val before = cacheState(meta, meta.hit)\n val after = cacheState(final_meta_writeback, true.B)\n\n def eviction(from: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) {\n if (cover) {\n params.ccover(evict === from.code, s\"MSHR_${from}_EVICT\", s\"State transition from ${from} to evicted ${cfg}\")\n } else {\n assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n }\n if (cover && f) {\n params.ccover(before === from.code, s\"MSHR_${from}_FLUSH\", s\"State transition from ${from} to flushed ${cfg}\")\n } else {\n assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n }\n }\n\n def transition(from: CacheState, to: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) {\n if (cover) {\n params.ccover(before === from.code && after === to.code, s\"MSHR_${from}_${to}\", s\"State transition from ${from} to ${to} ${cfg}\")\n } else {\n assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n }\n }\n\n when ((!s_release && w_rprobeackfirst) && io.schedule.ready) {\n eviction(S_BRANCH, b) // MMIO read to read-only device\n eviction(S_BRANCH_C, b && c) // you need children to become C\n eviction(S_TIP, true) // MMIO read || clean release can lead to this state\n eviction(S_TIP_C, c) // needs two clients || client + mmio || downgrading client\n eviction(S_TIP_CD, c) // needs two clients || client + mmio || downgrading client\n eviction(S_TIP_D, true) // MMIO write || dirty release lead here\n eviction(S_TRUNK_C, c) // acquire for write\n eviction(S_TRUNK_CD, c) // dirty release then reacquire\n }\n\n when ((!s_writeback && no_wait) && io.schedule.ready) {\n transition(S_INVALID, S_BRANCH, b && m) // only MMIO can bring us to BRANCH state\n transition(S_INVALID, S_BRANCH_C, b && c) // C state is only possible if there are inner caches\n transition(S_INVALID, S_TIP, m) // MMIO read\n transition(S_INVALID, S_TIP_C, false) // we would go S_TRUNK_C instead\n transition(S_INVALID, S_TIP_CD, false) // acquire does not cause dirty immediately\n transition(S_INVALID, S_TIP_D, m) // MMIO write\n transition(S_INVALID, S_TRUNK_C, c) // acquire\n transition(S_INVALID, S_TRUNK_CD, false) // acquire does not cause dirty immediately\n\n transition(S_BRANCH, S_INVALID, b && p) // probe can do this (flushes run as evictions)\n transition(S_BRANCH, S_BRANCH_C, b && c) // acquire\n transition(S_BRANCH, S_TIP, b && m) // prefetch write\n transition(S_BRANCH, S_TIP_C, false) // we would go S_TRUNK_C instead\n transition(S_BRANCH, S_TIP_CD, false) // acquire does not cause dirty immediately\n transition(S_BRANCH, S_TIP_D, b && m) // MMIO write\n transition(S_BRANCH, S_TRUNK_C, b && c) // acquire\n transition(S_BRANCH, S_TRUNK_CD, false) // acquire does not cause dirty immediately\n\n transition(S_BRANCH_C, S_INVALID, b && c && p)\n transition(S_BRANCH_C, S_BRANCH, b && c) // clean release (optional)\n transition(S_BRANCH_C, S_TIP, b && c && m) // prefetch write\n transition(S_BRANCH_C, S_TIP_C, false) // we would go S_TRUNK_C instead\n transition(S_BRANCH_C, S_TIP_D, b && c && m) // MMIO write\n transition(S_BRANCH_C, S_TIP_CD, false) // going dirty means we must shoot down clients\n transition(S_BRANCH_C, S_TRUNK_C, b && c) // acquire\n transition(S_BRANCH_C, S_TRUNK_CD, false) // acquire does not cause dirty immediately\n\n transition(S_TIP, S_INVALID, p)\n transition(S_TIP, S_BRANCH, p) // losing TIP only possible via probe\n transition(S_TIP, S_BRANCH_C, false) // we would go S_TRUNK_C instead\n transition(S_TIP, S_TIP_C, false) // we would go S_TRUNK_C instead\n transition(S_TIP, S_TIP_D, m) // direct dirty only via MMIO write\n transition(S_TIP, S_TIP_CD, false) // acquire does not make us dirty immediately\n transition(S_TIP, S_TRUNK_C, c) // acquire\n transition(S_TIP, S_TRUNK_CD, false) // acquire does not make us dirty immediately\n\n transition(S_TIP_C, S_INVALID, c && p)\n transition(S_TIP_C, S_BRANCH, c && p) // losing TIP only possible via probe\n transition(S_TIP_C, S_BRANCH_C, c && p) // losing TIP only possible via probe\n transition(S_TIP_C, S_TIP, c) // probed while MMIO read || clean release (optional)\n transition(S_TIP_C, S_TIP_D, c && m) // direct dirty only via MMIO write\n transition(S_TIP_C, S_TIP_CD, false) // going dirty means we must shoot down clients\n transition(S_TIP_C, S_TRUNK_C, c) // acquire\n transition(S_TIP_C, S_TRUNK_CD, false) // acquire does not make us immediately dirty\n\n transition(S_TIP_D, S_INVALID, p)\n transition(S_TIP_D, S_BRANCH, p) // losing D is only possible via probe\n transition(S_TIP_D, S_BRANCH_C, p && c) // probed while acquire shared\n transition(S_TIP_D, S_TIP, p) // probed while MMIO read || outer probe.toT (optional)\n transition(S_TIP_D, S_TIP_C, false) // we would go S_TRUNK_C instead\n transition(S_TIP_D, S_TIP_CD, false) // we would go S_TRUNK_CD instead\n transition(S_TIP_D, S_TRUNK_C, p && c) // probed while acquired\n transition(S_TIP_D, S_TRUNK_CD, c) // acquire\n\n transition(S_TIP_CD, S_INVALID, c && p)\n transition(S_TIP_CD, S_BRANCH, c && p) // losing D is only possible via probe\n transition(S_TIP_CD, S_BRANCH_C, c && p) // losing D is only possible via probe\n transition(S_TIP_CD, S_TIP, c && p) // probed while MMIO read || outer probe.toT (optional)\n transition(S_TIP_CD, S_TIP_C, false) // we would go S_TRUNK_C instead\n transition(S_TIP_CD, S_TIP_D, c) // MMIO write || clean release (optional)\n transition(S_TIP_CD, S_TRUNK_C, c && p) // probed while acquire\n transition(S_TIP_CD, S_TRUNK_CD, c) // acquire\n\n transition(S_TRUNK_C, S_INVALID, c && p)\n transition(S_TRUNK_C, S_BRANCH, c && p) // losing TIP only possible via probe\n transition(S_TRUNK_C, S_BRANCH_C, c && p) // losing TIP only possible via probe\n transition(S_TRUNK_C, S_TIP, c) // MMIO read || clean release (optional)\n transition(S_TRUNK_C, S_TIP_C, c) // bounce shared\n transition(S_TRUNK_C, S_TIP_D, c) // dirty release\n transition(S_TRUNK_C, S_TIP_CD, c) // dirty bounce shared\n transition(S_TRUNK_C, S_TRUNK_CD, c) // dirty bounce\n\n transition(S_TRUNK_CD, S_INVALID, c && p)\n transition(S_TRUNK_CD, S_BRANCH, c && p) // losing D only possible via probe\n transition(S_TRUNK_CD, S_BRANCH_C, c && p) // losing D only possible via probe\n transition(S_TRUNK_CD, S_TIP, c && p) // probed while MMIO read || outer probe.toT (optional)\n transition(S_TRUNK_CD, S_TIP_C, false) // we would go S_TRUNK_C instead\n transition(S_TRUNK_CD, S_TIP_D, c) // dirty release\n transition(S_TRUNK_CD, S_TIP_CD, c) // bounce shared\n transition(S_TRUNK_CD, S_TRUNK_C, c && p) // probed while acquire\n }\n\n // Handle response messages\n val probe_bit = params.clientBit(io.sinkc.bits.source)\n val last_probe = (probes_done | probe_bit) === (meta.clients & ~excluded_client)\n val probe_toN = isToN(io.sinkc.bits.param)\n if (!params.firstLevel) when (io.sinkc.valid) {\n params.ccover( probe_toN && io.schedule.bits.b.bits.param === toB, \"MSHR_PROBE_FULL\", \"Client downgraded to N when asked only to do B\")\n params.ccover(!probe_toN && io.schedule.bits.b.bits.param === toB, \"MSHR_PROBE_HALF\", \"Client downgraded to B when asked only to do B\")\n // Caution: the probe matches us only in set.\n // We would never allow an outer probe to nest until both w_[rp]probeack complete, so\n // it is safe to just unguardedly update the probe FSM.\n probes_done := probes_done | probe_bit\n probes_toN := probes_toN | Mux(probe_toN, probe_bit, 0.U)\n probes_noT := probes_noT || io.sinkc.bits.param =/= TtoT\n w_rprobeackfirst := w_rprobeackfirst || last_probe\n w_rprobeacklast := w_rprobeacklast || (last_probe && io.sinkc.bits.last)\n w_pprobeackfirst := w_pprobeackfirst || last_probe\n w_pprobeacklast := w_pprobeacklast || (last_probe && io.sinkc.bits.last)\n // Allow wormhole routing from sinkC if the first request beat has offset 0\n val set_pprobeack = last_probe && (io.sinkc.bits.last || request.offset === 0.U)\n w_pprobeack := w_pprobeack || set_pprobeack\n params.ccover(!set_pprobeack && w_rprobeackfirst, \"MSHR_PROBE_SERIAL\", \"Sequential routing of probe response data\")\n params.ccover( set_pprobeack && w_rprobeackfirst, \"MSHR_PROBE_WORMHOLE\", \"Wormhole routing of probe response data\")\n // However, meta-data updates need to be done more cautiously\n when (meta.state =/= INVALID && io.sinkc.bits.tag === meta.tag && io.sinkc.bits.data) { meta.dirty := true.B } // !!!\n }\n when (io.sinkd.valid) {\n when (io.sinkd.bits.opcode === Grant || io.sinkd.bits.opcode === GrantData) {\n sink := io.sinkd.bits.sink\n w_grantfirst := true.B\n w_grantlast := io.sinkd.bits.last\n // Record if we need to prevent taking ownership\n bad_grant := io.sinkd.bits.denied\n // Allow wormhole routing for requests whose first beat has offset 0\n w_grant := request.offset === 0.U || io.sinkd.bits.last\n params.ccover(io.sinkd.bits.opcode === GrantData && request.offset === 0.U, \"MSHR_GRANT_WORMHOLE\", \"Wormhole routing of grant response data\")\n params.ccover(io.sinkd.bits.opcode === GrantData && request.offset =/= 0.U, \"MSHR_GRANT_SERIAL\", \"Sequential routing of grant response data\")\n gotT := io.sinkd.bits.param === toT\n }\n .elsewhen (io.sinkd.bits.opcode === ReleaseAck) {\n w_releaseack := true.B\n }\n }\n when (io.sinke.valid) {\n w_grantack := true.B\n }\n\n // Bootstrap new requests\n val allocate_as_full = WireInit(new FullRequest(params), init = io.allocate.bits)\n val new_meta = Mux(io.allocate.valid && io.allocate.bits.repeat, final_meta_writeback, io.directory.bits)\n val new_request = Mux(io.allocate.valid, allocate_as_full, request)\n val new_needT = needT(new_request.opcode, new_request.param)\n val new_clientBit = params.clientBit(new_request.source)\n val new_skipProbe = Mux(skipProbeN(new_request.opcode, params.cache.hintsSkipProbe), new_clientBit, 0.U)\n\n val prior = cacheState(final_meta_writeback, true.B)\n def bypass(from: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) {\n if (cover) {\n params.ccover(prior === from.code, s\"MSHR_${from}_BYPASS\", s\"State bypass transition from ${from} ${cfg}\")\n } else {\n assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n }\n }\n\n when (io.allocate.valid && io.allocate.bits.repeat) {\n bypass(S_INVALID, f || p) // Can lose permissions (probe/flush)\n bypass(S_BRANCH, b) // MMIO read to read-only device\n bypass(S_BRANCH_C, b && c) // you need children to become C\n bypass(S_TIP, true) // MMIO read || clean release can lead to this state\n bypass(S_TIP_C, c) // needs two clients || client + mmio || downgrading client\n bypass(S_TIP_CD, c) // needs two clients || client + mmio || downgrading client\n bypass(S_TIP_D, true) // MMIO write || dirty release lead here\n bypass(S_TRUNK_C, c) // acquire for write\n bypass(S_TRUNK_CD, c) // dirty release then reacquire\n }\n\n when (io.allocate.valid) {\n assert (!request_valid || (no_wait && io.schedule.fire))\n request_valid := true.B\n request := io.allocate.bits\n }\n\n // Create execution plan\n when (io.directory.valid || (io.allocate.valid && io.allocate.bits.repeat)) {\n meta_valid := true.B\n meta := new_meta\n probes_done := 0.U\n probes_toN := 0.U\n probes_noT := false.B\n gotT := false.B\n bad_grant := false.B\n\n // These should already be either true or turning true\n // We clear them here explicitly to simplify the mux tree\n s_rprobe := true.B\n w_rprobeackfirst := true.B\n w_rprobeacklast := true.B\n s_release := true.B\n w_releaseack := true.B\n s_pprobe := true.B\n s_acquire := true.B\n s_flush := true.B\n w_grantfirst := true.B\n w_grantlast := true.B\n w_grant := true.B\n w_pprobeackfirst := true.B\n w_pprobeacklast := true.B\n w_pprobeack := true.B\n s_probeack := true.B\n s_grantack := true.B\n s_execute := true.B\n w_grantack := true.B\n s_writeback := true.B\n\n // For C channel requests (ie: Release[Data])\n when (new_request.prio(2) && (!params.firstLevel).B) {\n s_execute := false.B\n // Do we need to go dirty?\n when (new_request.opcode(0) && !new_meta.dirty) {\n s_writeback := false.B\n }\n // Does our state change?\n when (isToB(new_request.param) && new_meta.state === TRUNK) {\n s_writeback := false.B\n }\n // Do our clients change?\n when (isToN(new_request.param) && (new_meta.clients & new_clientBit) =/= 0.U) {\n s_writeback := false.B\n }\n assert (new_meta.hit)\n }\n // For X channel requests (ie: flush)\n .elsewhen (new_request.control && params.control.B) { // new_request.prio(0)\n s_flush := false.B\n // Do we need to actually do something?\n when (new_meta.hit) {\n s_release := false.B\n w_releaseack := false.B\n // Do we need to shoot-down inner caches?\n when ((!params.firstLevel).B && (new_meta.clients =/= 0.U)) {\n s_rprobe := false.B\n w_rprobeackfirst := false.B\n w_rprobeacklast := false.B\n }\n }\n }\n // For A channel requests\n .otherwise { // new_request.prio(0) && !new_request.control\n s_execute := false.B\n // Do we need an eviction?\n when (!new_meta.hit && new_meta.state =/= INVALID) {\n s_release := false.B\n w_releaseack := false.B\n // Do we need to shoot-down inner caches?\n when ((!params.firstLevel).B & (new_meta.clients =/= 0.U)) {\n s_rprobe := false.B\n w_rprobeackfirst := false.B\n w_rprobeacklast := false.B\n }\n }\n // Do we need an acquire?\n when (!new_meta.hit || (new_meta.state === BRANCH && new_needT)) {\n s_acquire := false.B\n w_grantfirst := false.B\n w_grantlast := false.B\n w_grant := false.B\n s_grantack := false.B\n s_writeback := false.B\n }\n // Do we need a probe?\n when ((!params.firstLevel).B && (new_meta.hit &&\n (new_needT || new_meta.state === TRUNK) &&\n (new_meta.clients & ~new_skipProbe) =/= 0.U)) {\n s_pprobe := false.B\n w_pprobeackfirst := false.B\n w_pprobeacklast := false.B\n w_pprobeack := false.B\n s_writeback := false.B\n }\n // Do we need a grantack?\n when (new_request.opcode === AcquireBlock || new_request.opcode === AcquirePerm) {\n w_grantack := false.B\n s_writeback := false.B\n }\n // Becomes dirty?\n when (!new_request.opcode(2) && new_meta.hit && !new_meta.dirty) {\n s_writeback := false.B\n }\n }\n }\n}\nFile Parameters.scala:\n/*\n * Copyright 2019 SiFive, Inc.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You should have received a copy of LICENSE.Apache2 along with\n * this software. If not, you may obtain a copy at\n *\n * https://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\npackage sifive.blocks.inclusivecache\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.experimental.SourceInfo\nimport org.chipsalliance.cde.config._\nimport freechips.rocketchip.diplomacy._\nimport freechips.rocketchip.tilelink._\nimport freechips.rocketchip.util._\nimport freechips.rocketchip.util.property.cover\nimport scala.math.{min,max}\n\ncase class CacheParameters(\n level: Int,\n ways: Int,\n sets: Int,\n blockBytes: Int,\n beatBytes: Int, // inner\n hintsSkipProbe: Boolean)\n{\n require (ways > 0)\n require (sets > 0)\n require (blockBytes > 0 && isPow2(blockBytes))\n require (beatBytes > 0 && isPow2(beatBytes))\n require (blockBytes >= beatBytes)\n\n val blocks = ways * sets\n val sizeBytes = blocks * blockBytes\n val blockBeats = blockBytes/beatBytes\n}\n\ncase class InclusiveCachePortParameters(\n a: BufferParams,\n b: BufferParams,\n c: BufferParams,\n d: BufferParams,\n e: BufferParams)\n{\n def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new TLBuffer(a, b, c, d, e))\n}\n\nobject InclusiveCachePortParameters\n{\n val none = InclusiveCachePortParameters(\n a = BufferParams.none,\n b = BufferParams.none,\n c = BufferParams.none,\n d = BufferParams.none,\n e = BufferParams.none)\n\n val full = InclusiveCachePortParameters(\n a = BufferParams.default,\n b = BufferParams.default,\n c = BufferParams.default,\n d = BufferParams.default,\n e = BufferParams.default)\n\n // This removes feed-through paths from C=>A and A=>C\n val fullC = InclusiveCachePortParameters(\n a = BufferParams.none,\n b = BufferParams.none,\n c = BufferParams.default,\n d = BufferParams.none,\n e = BufferParams.none)\n\n val flowAD = InclusiveCachePortParameters(\n a = BufferParams.flow,\n b = BufferParams.none,\n c = BufferParams.none,\n d = BufferParams.flow,\n e = BufferParams.none)\n\n val flowAE = InclusiveCachePortParameters(\n a = BufferParams.flow,\n b = BufferParams.none,\n c = BufferParams.none,\n d = BufferParams.none,\n e = BufferParams.flow)\n\n // For innerBuf:\n // SinkA: no restrictions, flows into scheduler+putbuffer\n // SourceB: no restrictions, flows out of scheduler\n // sinkC: no restrictions, flows into scheduler+putbuffer & buffered to bankedStore\n // SourceD: no restrictions, flows out of bankedStore/regout\n // SinkE: no restrictions, flows into scheduler\n //\n // ... so while none is possible, you probably want at least flowAC to cut ready\n // from the scheduler delay and flowD to ease SourceD back-pressure\n\n // For outerBufer:\n // SourceA: must not be pipe, flows out of scheduler\n // SinkB: no restrictions, flows into scheduler\n // SourceC: pipe is useless, flows out of bankedStore/regout, parameter depth ignored\n // SinkD: no restrictions, flows into scheduler & bankedStore\n // SourceE: must not be pipe, flows out of scheduler\n //\n // ... AE take the channel ready into the scheduler, so you need at least flowAE\n}\n\ncase class InclusiveCacheMicroParameters(\n writeBytes: Int, // backing store update granularity\n memCycles: Int = 40, // # of L2 clock cycles for a memory round-trip (50ns @ 800MHz)\n portFactor: Int = 4, // numSubBanks = (widest TL port * portFactor) / writeBytes\n dirReg: Boolean = false,\n innerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.fullC, // or none\n outerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.full) // or flowAE\n{\n require (writeBytes > 0 && isPow2(writeBytes))\n require (memCycles > 0)\n require (portFactor >= 2) // for inner RMW and concurrent outer Relase + Grant\n}\n\ncase class InclusiveCacheControlParameters(\n address: BigInt,\n beatBytes: Int,\n bankedControl: Boolean)\n\ncase class InclusiveCacheParameters(\n cache: CacheParameters,\n micro: InclusiveCacheMicroParameters,\n control: Boolean,\n inner: TLEdgeIn,\n outer: TLEdgeOut)(implicit val p: Parameters)\n{\n require (cache.ways > 1)\n require (cache.sets > 1 && isPow2(cache.sets))\n require (micro.writeBytes <= inner.manager.beatBytes)\n require (micro.writeBytes <= outer.manager.beatBytes)\n require (inner.manager.beatBytes <= cache.blockBytes)\n require (outer.manager.beatBytes <= cache.blockBytes)\n\n // Require that all cached address ranges have contiguous blocks\n outer.manager.managers.flatMap(_.address).foreach { a =>\n require (a.alignment >= cache.blockBytes)\n }\n\n // If we are the first level cache, we do not need to support inner-BCE\n val firstLevel = !inner.client.clients.exists(_.supports.probe)\n // If we are the last level cache, we do not need to support outer-B\n val lastLevel = !outer.manager.managers.exists(_.regionType > RegionType.UNCACHED)\n require (lastLevel)\n\n // Provision enough resources to achieve full throughput with missing single-beat accesses\n val mshrs = InclusiveCacheParameters.all_mshrs(cache, micro)\n val secondary = max(mshrs, micro.memCycles - mshrs)\n val putLists = micro.memCycles // allow every request to be single beat\n val putBeats = max(2*cache.blockBeats, micro.memCycles)\n val relLists = 2\n val relBeats = relLists*cache.blockBeats\n\n val flatAddresses = AddressSet.unify(outer.manager.managers.flatMap(_.address))\n val pickMask = AddressDecoder(flatAddresses.map(Seq(_)), flatAddresses.map(_.mask).reduce(_|_))\n\n def bitOffsets(x: BigInt, offset: Int = 0, tail: List[Int] = List.empty[Int]): List[Int] =\n if (x == 0) tail.reverse else bitOffsets(x >> 1, offset + 1, if ((x & 1) == 1) offset :: tail else tail)\n val addressMapping = bitOffsets(pickMask)\n val addressBits = addressMapping.size\n\n // println(s\"addresses: ${flatAddresses} => ${pickMask} => ${addressBits}\")\n\n val allClients = inner.client.clients.size\n val clientBitsRaw = inner.client.clients.filter(_.supports.probe).size\n val clientBits = max(1, clientBitsRaw)\n val stateBits = 2\n\n val wayBits = log2Ceil(cache.ways)\n val setBits = log2Ceil(cache.sets)\n val offsetBits = log2Ceil(cache.blockBytes)\n val tagBits = addressBits - setBits - offsetBits\n val putBits = log2Ceil(max(putLists, relLists))\n\n require (tagBits > 0)\n require (offsetBits > 0)\n\n val innerBeatBits = (offsetBits - log2Ceil(inner.manager.beatBytes)) max 1\n val outerBeatBits = (offsetBits - log2Ceil(outer.manager.beatBytes)) max 1\n val innerMaskBits = inner.manager.beatBytes / micro.writeBytes\n val outerMaskBits = outer.manager.beatBytes / micro.writeBytes\n\n def clientBit(source: UInt): UInt = {\n if (clientBitsRaw == 0) {\n 0.U\n } else {\n Cat(inner.client.clients.filter(_.supports.probe).map(_.sourceId.contains(source)).reverse)\n }\n }\n\n def clientSource(bit: UInt): UInt = {\n if (clientBitsRaw == 0) {\n 0.U\n } else {\n Mux1H(bit, inner.client.clients.filter(_.supports.probe).map(c => c.sourceId.start.U))\n }\n }\n\n def parseAddress(x: UInt): (UInt, UInt, UInt) = {\n val offset = Cat(addressMapping.map(o => x(o,o)).reverse)\n val set = offset >> offsetBits\n val tag = set >> setBits\n (tag(tagBits-1, 0), set(setBits-1, 0), offset(offsetBits-1, 0))\n }\n\n def widen(x: UInt, width: Int): UInt = {\n val y = x | 0.U(width.W)\n assert (y >> width === 0.U)\n y(width-1, 0)\n }\n\n def expandAddress(tag: UInt, set: UInt, offset: UInt): UInt = {\n val base = Cat(widen(tag, tagBits), widen(set, setBits), widen(offset, offsetBits))\n val bits = Array.fill(outer.bundle.addressBits) { 0.U(1.W) }\n addressMapping.zipWithIndex.foreach { case (a, i) => bits(a) = base(i,i) }\n Cat(bits.reverse)\n }\n\n def restoreAddress(expanded: UInt): UInt = {\n val missingBits = flatAddresses\n .map { a => (a.widen(pickMask).base, a.widen(~pickMask)) } // key is the bits to restore on match\n .groupBy(_._1)\n .view\n .mapValues(_.map(_._2))\n val muxMask = AddressDecoder(missingBits.values.toList)\n val mux = missingBits.toList.map { case (bits, addrs) =>\n val widen = addrs.map(_.widen(~muxMask))\n val matches = AddressSet\n .unify(widen.distinct)\n .map(_.contains(expanded))\n .reduce(_ || _)\n (matches, bits.U)\n }\n expanded | Mux1H(mux)\n }\n\n def dirReg[T <: Data](x: T, en: Bool = true.B): T = {\n if (micro.dirReg) RegEnable(x, en) else x\n }\n\n def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) =\n cover(cond, \"CCACHE_L\" + cache.level + \"_\" + label, \"MemorySystem;;\" + desc)\n}\n\nobject MetaData\n{\n val stateBits = 2\n def INVALID: UInt = 0.U(stateBits.W) // way is empty\n def BRANCH: UInt = 1.U(stateBits.W) // outer slave cache is trunk\n def TRUNK: UInt = 2.U(stateBits.W) // unique inner master cache is trunk\n def TIP: UInt = 3.U(stateBits.W) // we are trunk, inner masters are branch\n\n // Does a request need trunk?\n def needT(opcode: UInt, param: UInt): Bool = {\n !opcode(2) ||\n (opcode === TLMessages.Hint && param === TLHints.PREFETCH_WRITE) ||\n ((opcode === TLMessages.AcquireBlock || opcode === TLMessages.AcquirePerm) && param =/= TLPermissions.NtoB)\n }\n // Does a request prove the client need not be probed?\n def skipProbeN(opcode: UInt, hintsSkipProbe: Boolean): Bool = {\n // Acquire(toB) and Get => is N, so no probe\n // Acquire(*toT) => is N or B, but need T, so no probe\n // Hint => could be anything, so probe IS needed, if hintsSkipProbe is enabled, skip probe the same client\n // Put* => is N or B, so probe IS needed\n opcode === TLMessages.AcquireBlock || opcode === TLMessages.AcquirePerm || opcode === TLMessages.Get || (opcode === TLMessages.Hint && hintsSkipProbe.B)\n }\n def isToN(param: UInt): Bool = {\n param === TLPermissions.TtoN || param === TLPermissions.BtoN || param === TLPermissions.NtoN\n }\n def isToB(param: UInt): Bool = {\n param === TLPermissions.TtoB || param === TLPermissions.BtoB\n }\n}\n\nobject InclusiveCacheParameters\n{\n val lfsrBits = 10\n val L2ControlAddress = 0x2010000\n val L2ControlSize = 0x1000\n def out_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = {\n // We need 2-3 normal MSHRs to cover the Directory latency\n // To fully exploit memory bandwidth-delay-product, we need memCyles/blockBeats MSHRs\n max(if (micro.dirReg) 3 else 2, (micro.memCycles + cache.blockBeats - 1) / cache.blockBeats)\n }\n def all_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int =\n // We need a dedicated MSHR for B+C each\n 2 + out_mshrs(cache, micro)\n}\n\nclass InclusiveCacheBundle(params: InclusiveCacheParameters) extends Bundle\n"},"response":{"kind":"string","value":"module MSHR_32(\t// @[MSHR.scala:84:7]\n input clock,\t// @[MSHR.scala:84:7]\n input reset,\t// @[MSHR.scala:84:7]\n input io_allocate_valid,\t// @[MSHR.scala:86:14]\n input io_allocate_bits_prio_0,\t// @[MSHR.scala:86:14]\n input io_allocate_bits_prio_1,\t// @[MSHR.scala:86:14]\n input io_allocate_bits_prio_2,\t// @[MSHR.scala:86:14]\n input io_allocate_bits_control,\t// @[MSHR.scala:86:14]\n input [2:0] io_allocate_bits_opcode,\t// @[MSHR.scala:86:14]\n input [2:0] io_allocate_bits_param,\t// @[MSHR.scala:86:14]\n input [2:0] io_allocate_bits_size,\t// @[MSHR.scala:86:14]\n input [5:0] io_allocate_bits_source,\t// @[MSHR.scala:86:14]\n input [8:0] io_allocate_bits_tag,\t// @[MSHR.scala:86:14]\n input [5:0] io_allocate_bits_offset,\t// @[MSHR.scala:86:14]\n input [5:0] io_allocate_bits_put,\t// @[MSHR.scala:86:14]\n input [10:0] io_allocate_bits_set,\t// @[MSHR.scala:86:14]\n input io_allocate_bits_repeat,\t// @[MSHR.scala:86:14]\n input io_directory_valid,\t// @[MSHR.scala:86:14]\n input io_directory_bits_dirty,\t// @[MSHR.scala:86:14]\n input [1:0] io_directory_bits_state,\t// @[MSHR.scala:86:14]\n input io_directory_bits_clients,\t// @[MSHR.scala:86:14]\n input [8:0] io_directory_bits_tag,\t// @[MSHR.scala:86:14]\n input io_directory_bits_hit,\t// @[MSHR.scala:86:14]\n input [3:0] io_directory_bits_way,\t// @[MSHR.scala:86:14]\n output io_status_valid,\t// @[MSHR.scala:86:14]\n output [10:0] io_status_bits_set,\t// @[MSHR.scala:86:14]\n output [8:0] io_status_bits_tag,\t// @[MSHR.scala:86:14]\n output [3:0] io_status_bits_way,\t// @[MSHR.scala:86:14]\n output io_status_bits_blockB,\t// @[MSHR.scala:86:14]\n output io_status_bits_nestB,\t// @[MSHR.scala:86:14]\n output io_status_bits_blockC,\t// @[MSHR.scala:86:14]\n output io_status_bits_nestC,\t// @[MSHR.scala:86:14]\n input io_schedule_ready,\t// @[MSHR.scala:86:14]\n output io_schedule_valid,\t// @[MSHR.scala:86:14]\n output io_schedule_bits_a_valid,\t// @[MSHR.scala:86:14]\n output [8:0] io_schedule_bits_a_bits_tag,\t// @[MSHR.scala:86:14]\n output [10:0] io_schedule_bits_a_bits_set,\t// @[MSHR.scala:86:14]\n output [2:0] io_schedule_bits_a_bits_param,\t// @[MSHR.scala:86:14]\n output io_schedule_bits_a_bits_block,\t// @[MSHR.scala:86:14]\n output io_schedule_bits_b_valid,\t// @[MSHR.scala:86:14]\n output [2:0] io_schedule_bits_b_bits_param,\t// @[MSHR.scala:86:14]\n output [8:0] io_schedule_bits_b_bits_tag,\t// @[MSHR.scala:86:14]\n output [10:0] io_schedule_bits_b_bits_set,\t// @[MSHR.scala:86:14]\n output io_schedule_bits_b_bits_clients,\t// @[MSHR.scala:86:14]\n output io_schedule_bits_c_valid,\t// @[MSHR.scala:86:14]\n output [2:0] io_schedule_bits_c_bits_opcode,\t// @[MSHR.scala:86:14]\n output [2:0] io_schedule_bits_c_bits_param,\t// @[MSHR.scala:86:14]\n output [8:0] io_schedule_bits_c_bits_tag,\t// @[MSHR.scala:86:14]\n output [10:0] io_schedule_bits_c_bits_set,\t// @[MSHR.scala:86:14]\n output [3:0] io_schedule_bits_c_bits_way,\t// @[MSHR.scala:86:14]\n output io_schedule_bits_c_bits_dirty,\t// @[MSHR.scala:86:14]\n output io_schedule_bits_d_valid,\t// @[MSHR.scala:86:14]\n output io_schedule_bits_d_bits_prio_0,\t// @[MSHR.scala:86:14]\n output io_schedule_bits_d_bits_prio_1,\t// @[MSHR.scala:86:14]\n output io_schedule_bits_d_bits_prio_2,\t// @[MSHR.scala:86:14]\n output io_schedule_bits_d_bits_control,\t// @[MSHR.scala:86:14]\n output [2:0] io_schedule_bits_d_bits_opcode,\t// @[MSHR.scala:86:14]\n output [2:0] io_schedule_bits_d_bits_param,\t// @[MSHR.scala:86:14]\n output [2:0] io_schedule_bits_d_bits_size,\t// @[MSHR.scala:86:14]\n output [5:0] io_schedule_bits_d_bits_source,\t// @[MSHR.scala:86:14]\n output [8:0] io_schedule_bits_d_bits_tag,\t// @[MSHR.scala:86:14]\n output [5:0] io_schedule_bits_d_bits_offset,\t// @[MSHR.scala:86:14]\n output [5:0] io_schedule_bits_d_bits_put,\t// @[MSHR.scala:86:14]\n output [10:0] io_schedule_bits_d_bits_set,\t// @[MSHR.scala:86:14]\n output [3:0] io_schedule_bits_d_bits_way,\t// @[MSHR.scala:86:14]\n output io_schedule_bits_d_bits_bad,\t// @[MSHR.scala:86:14]\n output io_schedule_bits_e_valid,\t// @[MSHR.scala:86:14]\n output [2:0] io_schedule_bits_e_bits_sink,\t// @[MSHR.scala:86:14]\n output io_schedule_bits_x_valid,\t// @[MSHR.scala:86:14]\n output io_schedule_bits_dir_valid,\t// @[MSHR.scala:86:14]\n output [10:0] io_schedule_bits_dir_bits_set,\t// @[MSHR.scala:86:14]\n output [3:0] io_schedule_bits_dir_bits_way,\t// @[MSHR.scala:86:14]\n output io_schedule_bits_dir_bits_data_dirty,\t// @[MSHR.scala:86:14]\n output [1:0] io_schedule_bits_dir_bits_data_state,\t// @[MSHR.scala:86:14]\n output io_schedule_bits_dir_bits_data_clients,\t// @[MSHR.scala:86:14]\n output [8:0] io_schedule_bits_dir_bits_data_tag,\t// @[MSHR.scala:86:14]\n output io_schedule_bits_reload,\t// @[MSHR.scala:86:14]\n input io_sinkc_valid,\t// @[MSHR.scala:86:14]\n input io_sinkc_bits_last,\t// @[MSHR.scala:86:14]\n input [10:0] io_sinkc_bits_set,\t// @[MSHR.scala:86:14]\n input [8:0] io_sinkc_bits_tag,\t// @[MSHR.scala:86:14]\n input [5:0] io_sinkc_bits_source,\t// @[MSHR.scala:86:14]\n input [2:0] io_sinkc_bits_param,\t// @[MSHR.scala:86:14]\n input io_sinkc_bits_data,\t// @[MSHR.scala:86:14]\n input io_sinkd_valid,\t// @[MSHR.scala:86:14]\n input io_sinkd_bits_last,\t// @[MSHR.scala:86:14]\n input [2:0] io_sinkd_bits_opcode,\t// @[MSHR.scala:86:14]\n input [2:0] io_sinkd_bits_param,\t// @[MSHR.scala:86:14]\n input [3:0] io_sinkd_bits_source,\t// @[MSHR.scala:86:14]\n input [2:0] io_sinkd_bits_sink,\t// @[MSHR.scala:86:14]\n input io_sinkd_bits_denied,\t// @[MSHR.scala:86:14]\n input io_sinke_valid,\t// @[MSHR.scala:86:14]\n input [3:0] io_sinke_bits_sink,\t// @[MSHR.scala:86:14]\n input [10:0] io_nestedwb_set,\t// @[MSHR.scala:86:14]\n input [8:0] io_nestedwb_tag,\t// @[MSHR.scala:86:14]\n input io_nestedwb_b_toN,\t// @[MSHR.scala:86:14]\n input io_nestedwb_b_toB,\t// @[MSHR.scala:86:14]\n input io_nestedwb_b_clr_dirty,\t// @[MSHR.scala:86:14]\n input io_nestedwb_c_set_dirty\t// @[MSHR.scala:86:14]\n);\n\n wire [8:0] final_meta_writeback_tag;\t// @[MSHR.scala:215:38]\n wire final_meta_writeback_clients;\t// @[MSHR.scala:215:38]\n wire [1:0] final_meta_writeback_state;\t// @[MSHR.scala:215:38]\n wire final_meta_writeback_dirty;\t// @[MSHR.scala:215:38]\n wire io_allocate_valid_0 = io_allocate_valid;\t// @[MSHR.scala:84:7]\n wire io_allocate_bits_prio_0_0 = io_allocate_bits_prio_0;\t// @[MSHR.scala:84:7]\n wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1;\t// @[MSHR.scala:84:7]\n wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2;\t// @[MSHR.scala:84:7]\n wire io_allocate_bits_control_0 = io_allocate_bits_control;\t// @[MSHR.scala:84:7]\n wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode;\t// @[MSHR.scala:84:7]\n wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param;\t// @[MSHR.scala:84:7]\n wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size;\t// @[MSHR.scala:84:7]\n wire [5:0] io_allocate_bits_source_0 = io_allocate_bits_source;\t// @[MSHR.scala:84:7]\n wire [8:0] io_allocate_bits_tag_0 = io_allocate_bits_tag;\t// @[MSHR.scala:84:7]\n wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset;\t// @[MSHR.scala:84:7]\n wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put;\t// @[MSHR.scala:84:7]\n wire [10:0] io_allocate_bits_set_0 = io_allocate_bits_set;\t// @[MSHR.scala:84:7]\n wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat;\t// @[MSHR.scala:84:7]\n wire io_directory_valid_0 = io_directory_valid;\t// @[MSHR.scala:84:7]\n wire io_directory_bits_dirty_0 = io_directory_bits_dirty;\t// @[MSHR.scala:84:7]\n wire [1:0] io_directory_bits_state_0 = io_directory_bits_state;\t// @[MSHR.scala:84:7]\n wire io_directory_bits_clients_0 = io_directory_bits_clients;\t// @[MSHR.scala:84:7]\n wire [8:0] io_directory_bits_tag_0 = io_directory_bits_tag;\t// @[MSHR.scala:84:7]\n wire io_directory_bits_hit_0 = io_directory_bits_hit;\t// @[MSHR.scala:84:7]\n wire [3:0] io_directory_bits_way_0 = io_directory_bits_way;\t// @[MSHR.scala:84:7]\n wire io_schedule_ready_0 = io_schedule_ready;\t// @[MSHR.scala:84:7]\n wire io_sinkc_valid_0 = io_sinkc_valid;\t// @[MSHR.scala:84:7]\n wire io_sinkc_bits_last_0 = io_sinkc_bits_last;\t// @[MSHR.scala:84:7]\n wire [10:0] io_sinkc_bits_set_0 = io_sinkc_bits_set;\t// @[MSHR.scala:84:7]\n wire [8:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag;\t// @[MSHR.scala:84:7]\n wire [5:0] io_sinkc_bits_source_0 = io_sinkc_bits_source;\t// @[MSHR.scala:84:7]\n wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param;\t// @[MSHR.scala:84:7]\n wire io_sinkc_bits_data_0 = io_sinkc_bits_data;\t// @[MSHR.scala:84:7]\n wire io_sinkd_valid_0 = io_sinkd_valid;\t// @[MSHR.scala:84:7]\n wire io_sinkd_bits_last_0 = io_sinkd_bits_last;\t// @[MSHR.scala:84:7]\n wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode;\t// @[MSHR.scala:84:7]\n wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param;\t// @[MSHR.scala:84:7]\n wire [3:0] io_sinkd_bits_source_0 = io_sinkd_bits_source;\t// @[MSHR.scala:84:7]\n wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink;\t// @[MSHR.scala:84:7]\n wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied;\t// @[MSHR.scala:84:7]\n wire io_sinke_valid_0 = io_sinke_valid;\t// @[MSHR.scala:84:7]\n wire [3:0] io_sinke_bits_sink_0 = io_sinke_bits_sink;\t// @[MSHR.scala:84:7]\n wire [10:0] io_nestedwb_set_0 = io_nestedwb_set;\t// @[MSHR.scala:84:7]\n wire [8:0] io_nestedwb_tag_0 = io_nestedwb_tag;\t// @[MSHR.scala:84:7]\n wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN;\t// @[MSHR.scala:84:7]\n wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB;\t// @[MSHR.scala:84:7]\n wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty;\t// @[MSHR.scala:84:7]\n wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty;\t// @[MSHR.scala:84:7]\n wire [3:0] io_schedule_bits_a_bits_source = 4'h0;\t// @[MSHR.scala:84:7]\n wire [3:0] io_schedule_bits_c_bits_source = 4'h0;\t// @[MSHR.scala:84:7]\n wire [3:0] io_schedule_bits_d_bits_sink = 4'h0;\t// @[MSHR.scala:84:7]\n wire io_schedule_bits_x_bits_fail = 1'h0;\t// @[MSHR.scala:84:7]\n wire _io_schedule_bits_c_valid_T_2 = 1'h0;\t// @[MSHR.scala:186:68]\n wire _io_schedule_bits_c_valid_T_3 = 1'h0;\t// @[MSHR.scala:186:80]\n wire invalid_dirty = 1'h0;\t// @[MSHR.scala:268:21]\n wire invalid_clients = 1'h0;\t// @[MSHR.scala:268:21]\n wire _excluded_client_T_7 = 1'h0;\t// @[Parameters.scala:279:137]\n wire _after_T_4 = 1'h0;\t// @[MSHR.scala:323:11]\n wire _new_skipProbe_T_6 = 1'h0;\t// @[Parameters.scala:279:137]\n wire _prior_T_4 = 1'h0;\t// @[MSHR.scala:323:11]\n wire [8:0] invalid_tag = 9'h0;\t// @[MSHR.scala:268:21]\n wire [1:0] invalid_state = 2'h0;\t// @[MSHR.scala:268:21]\n wire [1:0] _final_meta_writeback_state_T_11 = 2'h1;\t// @[MSHR.scala:240:70]\n wire allocate_as_full_prio_0 = io_allocate_bits_prio_0_0;\t// @[MSHR.scala:84:7, :504:34]\n wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0;\t// @[MSHR.scala:84:7, :504:34]\n wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0;\t// @[MSHR.scala:84:7, :504:34]\n wire allocate_as_full_control = io_allocate_bits_control_0;\t// @[MSHR.scala:84:7, :504:34]\n wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0;\t// @[MSHR.scala:84:7, :504:34]\n wire [2:0] allocate_as_full_param = io_allocate_bits_param_0;\t// @[MSHR.scala:84:7, :504:34]\n wire [2:0] allocate_as_full_size = io_allocate_bits_size_0;\t// @[MSHR.scala:84:7, :504:34]\n wire [5:0] allocate_as_full_source = io_allocate_bits_source_0;\t// @[MSHR.scala:84:7, :504:34]\n wire [8:0] allocate_as_full_tag = io_allocate_bits_tag_0;\t// @[MSHR.scala:84:7, :504:34]\n wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0;\t// @[MSHR.scala:84:7, :504:34]\n wire [5:0] allocate_as_full_put = io_allocate_bits_put_0;\t// @[MSHR.scala:84:7, :504:34]\n wire [10:0] allocate_as_full_set = io_allocate_bits_set_0;\t// @[MSHR.scala:84:7, :504:34]\n wire _io_status_bits_blockB_T_8;\t// @[MSHR.scala:168:40]\n wire _io_status_bits_nestB_T_4;\t// @[MSHR.scala:169:93]\n wire _io_status_bits_blockC_T;\t// @[MSHR.scala:172:28]\n wire _io_status_bits_nestC_T_5;\t// @[MSHR.scala:173:39]\n wire _io_schedule_valid_T_5;\t// @[MSHR.scala:193:105]\n wire _io_schedule_bits_a_valid_T_2;\t// @[MSHR.scala:184:55]\n wire _io_schedule_bits_a_bits_block_T_5;\t// @[MSHR.scala:283:91]\n wire _io_schedule_bits_b_valid_T_2;\t// @[MSHR.scala:185:41]\n wire [2:0] _io_schedule_bits_b_bits_param_T_3;\t// @[MSHR.scala:286:41]\n wire [8:0] _io_schedule_bits_b_bits_tag_T_1;\t// @[MSHR.scala:287:41]\n wire _io_schedule_bits_b_bits_clients_T_1;\t// @[MSHR.scala:289:51]\n wire _io_schedule_bits_c_valid_T_4;\t// @[MSHR.scala:186:64]\n wire [2:0] _io_schedule_bits_c_bits_opcode_T;\t// @[MSHR.scala:290:41]\n wire [2:0] _io_schedule_bits_c_bits_param_T_1;\t// @[MSHR.scala:291:41]\n wire _io_schedule_bits_d_valid_T_2;\t// @[MSHR.scala:187:57]\n wire [2:0] _io_schedule_bits_d_bits_param_T_9;\t// @[MSHR.scala:298:41]\n wire _io_schedule_bits_e_valid_T_1;\t// @[MSHR.scala:188:43]\n wire _io_schedule_bits_x_valid_T_1;\t// @[MSHR.scala:189:40]\n wire _io_schedule_bits_dir_valid_T_4;\t// @[MSHR.scala:190:66]\n wire _io_schedule_bits_dir_bits_data_T_1_dirty;\t// @[MSHR.scala:310:41]\n wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state;\t// @[MSHR.scala:310:41]\n wire _io_schedule_bits_dir_bits_data_T_1_clients;\t// @[MSHR.scala:310:41]\n wire [8:0] _io_schedule_bits_dir_bits_data_T_1_tag;\t// @[MSHR.scala:310:41]\n wire no_wait;\t// @[MSHR.scala:183:83]\n wire [10:0] io_status_bits_set_0;\t// @[MSHR.scala:84:7]\n wire [8:0] io_status_bits_tag_0;\t// @[MSHR.scala:84:7]\n wire [3:0] io_status_bits_way_0;\t// @[MSHR.scala:84:7]\n wire io_status_bits_blockB_0;\t// @[MSHR.scala:84:7]\n wire io_status_bits_nestB_0;\t// @[MSHR.scala:84:7]\n wire io_status_bits_blockC_0;\t// @[MSHR.scala:84:7]\n wire io_status_bits_nestC_0;\t// @[MSHR.scala:84:7]\n wire io_status_valid_0;\t// @[MSHR.scala:84:7]\n wire [8:0] io_schedule_bits_a_bits_tag_0;\t// @[MSHR.scala:84:7]\n wire [10:0] io_schedule_bits_a_bits_set_0;\t// @[MSHR.scala:84:7]\n wire [2:0] io_schedule_bits_a_bits_param_0;\t// @[MSHR.scala:84:7]\n wire io_schedule_bits_a_bits_block_0;\t// @[MSHR.scala:84:7]\n wire io_schedule_bits_a_valid_0;\t// @[MSHR.scala:84:7]\n wire [2:0] io_schedule_bits_b_bits_param_0;\t// @[MSHR.scala:84:7]\n wire [8:0] io_schedule_bits_b_bits_tag_0;\t// @[MSHR.scala:84:7]\n wire [10:0] io_schedule_bits_b_bits_set_0;\t// @[MSHR.scala:84:7]\n wire io_schedule_bits_b_bits_clients_0;\t// @[MSHR.scala:84:7]\n wire io_schedule_bits_b_valid_0;\t// @[MSHR.scala:84:7]\n wire [2:0] io_schedule_bits_c_bits_opcode_0;\t// @[MSHR.scala:84:7]\n wire [2:0] io_schedule_bits_c_bits_param_0;\t// @[MSHR.scala:84:7]\n wire [8:0] io_schedule_bits_c_bits_tag_0;\t// @[MSHR.scala:84:7]\n wire [10:0] io_schedule_bits_c_bits_set_0;\t// @[MSHR.scala:84:7]\n wire [3:0] io_schedule_bits_c_bits_way_0;\t// @[MSHR.scala:84:7]\n wire io_schedule_bits_c_bits_dirty_0;\t// @[MSHR.scala:84:7]\n wire io_schedule_bits_c_valid_0;\t// @[MSHR.scala:84:7]\n wire io_schedule_bits_d_bits_prio_0_0;\t// @[MSHR.scala:84:7]\n wire io_schedule_bits_d_bits_prio_1_0;\t// @[MSHR.scala:84:7]\n wire io_schedule_bits_d_bits_prio_2_0;\t// @[MSHR.scala:84:7]\n wire io_schedule_bits_d_bits_control_0;\t// @[MSHR.scala:84:7]\n wire [2:0] io_schedule_bits_d_bits_opcode_0;\t// @[MSHR.scala:84:7]\n wire [2:0] io_schedule_bits_d_bits_param_0;\t// @[MSHR.scala:84:7]\n wire [2:0] io_schedule_bits_d_bits_size_0;\t// @[MSHR.scala:84:7]\n wire [5:0] io_schedule_bits_d_bits_source_0;\t// @[MSHR.scala:84:7]\n wire [8:0] io_schedule_bits_d_bits_tag_0;\t// @[MSHR.scala:84:7]\n wire [5:0] io_schedule_bits_d_bits_offset_0;\t// @[MSHR.scala:84:7]\n wire [5:0] io_schedule_bits_d_bits_put_0;\t// @[MSHR.scala:84:7]\n wire [10:0] io_schedule_bits_d_bits_set_0;\t// @[MSHR.scala:84:7]\n wire [3:0] io_schedule_bits_d_bits_way_0;\t// @[MSHR.scala:84:7]\n wire io_schedule_bits_d_bits_bad_0;\t// @[MSHR.scala:84:7]\n wire io_schedule_bits_d_valid_0;\t// @[MSHR.scala:84:7]\n wire [2:0] io_schedule_bits_e_bits_sink_0;\t// @[MSHR.scala:84:7]\n wire io_schedule_bits_e_valid_0;\t// @[MSHR.scala:84:7]\n wire io_schedule_bits_x_valid_0;\t// @[MSHR.scala:84:7]\n wire io_schedule_bits_dir_bits_data_dirty_0;\t// @[MSHR.scala:84:7]\n wire [1:0] io_schedule_bits_dir_bits_data_state_0;\t// @[MSHR.scala:84:7]\n wire io_schedule_bits_dir_bits_data_clients_0;\t// @[MSHR.scala:84:7]\n wire [8:0] io_schedule_bits_dir_bits_data_tag_0;\t// @[MSHR.scala:84:7]\n wire [10:0] io_schedule_bits_dir_bits_set_0;\t// @[MSHR.scala:84:7]\n wire [3:0] io_schedule_bits_dir_bits_way_0;\t// @[MSHR.scala:84:7]\n wire io_schedule_bits_dir_valid_0;\t// @[MSHR.scala:84:7]\n wire io_schedule_bits_reload_0;\t// @[MSHR.scala:84:7]\n wire io_schedule_valid_0;\t// @[MSHR.scala:84:7]\n reg request_valid;\t// @[MSHR.scala:97:30]\n assign io_status_valid_0 = request_valid;\t// @[MSHR.scala:84:7, :97:30]\n reg request_prio_0;\t// @[MSHR.scala:98:20]\n assign io_schedule_bits_d_bits_prio_0_0 = request_prio_0;\t// @[MSHR.scala:84:7, :98:20]\n reg request_prio_1;\t// @[MSHR.scala:98:20]\n assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1;\t// @[MSHR.scala:84:7, :98:20]\n reg request_prio_2;\t// @[MSHR.scala:98:20]\n assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2;\t// @[MSHR.scala:84:7, :98:20]\n reg request_control;\t// @[MSHR.scala:98:20]\n assign io_schedule_bits_d_bits_control_0 = request_control;\t// @[MSHR.scala:84:7, :98:20]\n reg [2:0] request_opcode;\t// @[MSHR.scala:98:20]\n assign io_schedule_bits_d_bits_opcode_0 = request_opcode;\t// @[MSHR.scala:84:7, :98:20]\n reg [2:0] request_param;\t// @[MSHR.scala:98:20]\n reg [2:0] request_size;\t// @[MSHR.scala:98:20]\n assign io_schedule_bits_d_bits_size_0 = request_size;\t// @[MSHR.scala:84:7, :98:20]\n reg [5:0] request_source;\t// @[MSHR.scala:98:20]\n assign io_schedule_bits_d_bits_source_0 = request_source;\t// @[MSHR.scala:84:7, :98:20]\n reg [8:0] request_tag;\t// @[MSHR.scala:98:20]\n assign io_status_bits_tag_0 = request_tag;\t// @[MSHR.scala:84:7, :98:20]\n assign io_schedule_bits_a_bits_tag_0 = request_tag;\t// @[MSHR.scala:84:7, :98:20]\n assign io_schedule_bits_d_bits_tag_0 = request_tag;\t// @[MSHR.scala:84:7, :98:20]\n reg [5:0] request_offset;\t// @[MSHR.scala:98:20]\n assign io_schedule_bits_d_bits_offset_0 = request_offset;\t// @[MSHR.scala:84:7, :98:20]\n reg [5:0] request_put;\t// @[MSHR.scala:98:20]\n assign io_schedule_bits_d_bits_put_0 = request_put;\t// @[MSHR.scala:84:7, :98:20]\n reg [10:0] request_set;\t// @[MSHR.scala:98:20]\n assign io_status_bits_set_0 = request_set;\t// @[MSHR.scala:84:7, :98:20]\n assign io_schedule_bits_a_bits_set_0 = request_set;\t// @[MSHR.scala:84:7, :98:20]\n assign io_schedule_bits_b_bits_set_0 = request_set;\t// @[MSHR.scala:84:7, :98:20]\n assign io_schedule_bits_c_bits_set_0 = request_set;\t// @[MSHR.scala:84:7, :98:20]\n assign io_schedule_bits_d_bits_set_0 = request_set;\t// @[MSHR.scala:84:7, :98:20]\n assign io_schedule_bits_dir_bits_set_0 = request_set;\t// @[MSHR.scala:84:7, :98:20]\n reg meta_valid;\t// @[MSHR.scala:99:27]\n reg meta_dirty;\t// @[MSHR.scala:100:17]\n assign io_schedule_bits_c_bits_dirty_0 = meta_dirty;\t// @[MSHR.scala:84:7, :100:17]\n reg [1:0] meta_state;\t// @[MSHR.scala:100:17]\n reg meta_clients;\t// @[MSHR.scala:100:17]\n wire _meta_no_clients_T = meta_clients;\t// @[MSHR.scala:100:17, :220:39]\n wire evict_c = meta_clients;\t// @[MSHR.scala:100:17, :315:27]\n wire before_c = meta_clients;\t// @[MSHR.scala:100:17, :315:27]\n reg [8:0] meta_tag;\t// @[MSHR.scala:100:17]\n assign io_schedule_bits_c_bits_tag_0 = meta_tag;\t// @[MSHR.scala:84:7, :100:17]\n reg meta_hit;\t// @[MSHR.scala:100:17]\n reg [3:0] meta_way;\t// @[MSHR.scala:100:17]\n assign io_status_bits_way_0 = meta_way;\t// @[MSHR.scala:84:7, :100:17]\n assign io_schedule_bits_c_bits_way_0 = meta_way;\t// @[MSHR.scala:84:7, :100:17]\n assign io_schedule_bits_d_bits_way_0 = meta_way;\t// @[MSHR.scala:84:7, :100:17]\n assign io_schedule_bits_dir_bits_way_0 = meta_way;\t// @[MSHR.scala:84:7, :100:17]\n wire [3:0] final_meta_writeback_way = meta_way;\t// @[MSHR.scala:100:17, :215:38]\n reg s_rprobe;\t// @[MSHR.scala:121:33]\n reg w_rprobeackfirst;\t// @[MSHR.scala:122:33]\n reg w_rprobeacklast;\t// @[MSHR.scala:123:33]\n reg s_release;\t// @[MSHR.scala:124:33]\n reg w_releaseack;\t// @[MSHR.scala:125:33]\n reg s_pprobe;\t// @[MSHR.scala:126:33]\n reg s_acquire;\t// @[MSHR.scala:127:33]\n reg s_flush;\t// @[MSHR.scala:128:33]\n reg w_grantfirst;\t// @[MSHR.scala:129:33]\n reg w_grantlast;\t// @[MSHR.scala:130:33]\n reg w_grant;\t// @[MSHR.scala:131:33]\n reg w_pprobeackfirst;\t// @[MSHR.scala:132:33]\n reg w_pprobeacklast;\t// @[MSHR.scala:133:33]\n reg w_pprobeack;\t// @[MSHR.scala:134:33]\n reg s_grantack;\t// @[MSHR.scala:136:33]\n reg s_execute;\t// @[MSHR.scala:137:33]\n reg w_grantack;\t// @[MSHR.scala:138:33]\n reg s_writeback;\t// @[MSHR.scala:139:33]\n reg [2:0] sink;\t// @[MSHR.scala:147:17]\n assign io_schedule_bits_e_bits_sink_0 = sink;\t// @[MSHR.scala:84:7, :147:17]\n reg gotT;\t// @[MSHR.scala:148:17]\n reg bad_grant;\t// @[MSHR.scala:149:22]\n assign io_schedule_bits_d_bits_bad_0 = bad_grant;\t// @[MSHR.scala:84:7, :149:22]\n reg probes_done;\t// @[MSHR.scala:150:24]\n reg probes_toN;\t// @[MSHR.scala:151:23]\n reg probes_noT;\t// @[MSHR.scala:152:23]\n wire _io_status_bits_blockB_T = ~meta_valid;\t// @[MSHR.scala:99:27, :168:28]\n wire _io_status_bits_blockB_T_1 = ~w_releaseack;\t// @[MSHR.scala:125:33, :168:45]\n wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast;\t// @[MSHR.scala:123:33, :168:62]\n wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 | _io_status_bits_blockB_T_2;\t// @[MSHR.scala:168:{45,59,62}]\n wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast;\t// @[MSHR.scala:133:33, :168:82]\n wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 | _io_status_bits_blockB_T_4;\t// @[MSHR.scala:168:{59,79,82}]\n wire _io_status_bits_blockB_T_6 = ~w_grantfirst;\t// @[MSHR.scala:129:33, :168:103]\n wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6;\t// @[MSHR.scala:168:{79,100,103}]\n assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T | _io_status_bits_blockB_T_7;\t// @[MSHR.scala:168:{28,40,100}]\n assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8;\t// @[MSHR.scala:84:7, :168:40]\n wire _io_status_bits_nestB_T = meta_valid & w_releaseack;\t// @[MSHR.scala:99:27, :125:33, :169:39]\n wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast;\t// @[MSHR.scala:123:33, :169:{39,55}]\n wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast;\t// @[MSHR.scala:133:33, :169:{55,74}]\n wire _io_status_bits_nestB_T_3 = ~w_grantfirst;\t// @[MSHR.scala:129:33, :168:103, :169:96]\n assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3;\t// @[MSHR.scala:169:{74,93,96}]\n assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4;\t// @[MSHR.scala:84:7, :169:93]\n assign _io_status_bits_blockC_T = ~meta_valid;\t// @[MSHR.scala:99:27, :168:28, :172:28]\n assign io_status_bits_blockC_0 = _io_status_bits_blockC_T;\t// @[MSHR.scala:84:7, :172:28]\n wire _io_status_bits_nestC_T = ~w_rprobeackfirst;\t// @[MSHR.scala:122:33, :173:43]\n wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst;\t// @[MSHR.scala:132:33, :173:64]\n wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T | _io_status_bits_nestC_T_1;\t// @[MSHR.scala:173:{43,61,64}]\n wire _io_status_bits_nestC_T_3 = ~w_grantfirst;\t// @[MSHR.scala:129:33, :168:103, :173:85]\n wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 | _io_status_bits_nestC_T_3;\t// @[MSHR.scala:173:{61,82,85}]\n assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4;\t// @[MSHR.scala:99:27, :173:{39,82}]\n assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5;\t// @[MSHR.scala:84:7, :173:39]\n wire _no_wait_T = w_rprobeacklast & w_releaseack;\t// @[MSHR.scala:123:33, :125:33, :183:33]\n wire _no_wait_T_1 = _no_wait_T & w_grantlast;\t// @[MSHR.scala:130:33, :183:{33,49}]\n wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast;\t// @[MSHR.scala:133:33, :183:{49,64}]\n assign no_wait = _no_wait_T_2 & w_grantack;\t// @[MSHR.scala:138:33, :183:{64,83}]\n assign io_schedule_bits_reload_0 = no_wait;\t// @[MSHR.scala:84:7, :183:83]\n wire _io_schedule_bits_a_valid_T = ~s_acquire;\t// @[MSHR.scala:127:33, :184:31]\n wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release;\t// @[MSHR.scala:124:33, :184:{31,42}]\n assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe;\t// @[MSHR.scala:126:33, :184:{42,55}]\n assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2;\t// @[MSHR.scala:84:7, :184:55]\n wire _io_schedule_bits_b_valid_T = ~s_rprobe;\t// @[MSHR.scala:121:33, :185:31]\n wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe;\t// @[MSHR.scala:126:33, :185:44]\n assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T | _io_schedule_bits_b_valid_T_1;\t// @[MSHR.scala:185:{31,41,44}]\n assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2;\t// @[MSHR.scala:84:7, :185:41]\n wire _io_schedule_bits_c_valid_T = ~s_release;\t// @[MSHR.scala:124:33, :186:32]\n wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst;\t// @[MSHR.scala:122:33, :186:{32,43}]\n assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1;\t// @[MSHR.scala:186:{43,64}]\n assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4;\t// @[MSHR.scala:84:7, :186:64]\n wire _io_schedule_bits_d_valid_T = ~s_execute;\t// @[MSHR.scala:137:33, :187:31]\n wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack;\t// @[MSHR.scala:134:33, :187:{31,42}]\n assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant;\t// @[MSHR.scala:131:33, :187:{42,57}]\n assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2;\t// @[MSHR.scala:84:7, :187:57]\n wire _io_schedule_bits_e_valid_T = ~s_grantack;\t// @[MSHR.scala:136:33, :188:31]\n assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst;\t// @[MSHR.scala:129:33, :188:{31,43}]\n assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1;\t// @[MSHR.scala:84:7, :188:43]\n wire _io_schedule_bits_x_valid_T = ~s_flush;\t// @[MSHR.scala:128:33, :189:31]\n assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack;\t// @[MSHR.scala:125:33, :189:{31,40}]\n assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1;\t// @[MSHR.scala:84:7, :189:40]\n wire _io_schedule_bits_dir_valid_T = ~s_release;\t// @[MSHR.scala:124:33, :186:32, :190:34]\n wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst;\t// @[MSHR.scala:122:33, :190:{34,45}]\n wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback;\t// @[MSHR.scala:139:33, :190:70]\n wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait;\t// @[MSHR.scala:183:83, :190:{70,83}]\n assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 | _io_schedule_bits_dir_valid_T_3;\t// @[MSHR.scala:190:{45,66,83}]\n assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4;\t// @[MSHR.scala:84:7, :190:66]\n wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 | io_schedule_bits_b_valid_0;\t// @[MSHR.scala:84:7, :192:49]\n wire _io_schedule_valid_T_1 = _io_schedule_valid_T | io_schedule_bits_c_valid_0;\t// @[MSHR.scala:84:7, :192:{49,77}]\n wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 | io_schedule_bits_d_valid_0;\t// @[MSHR.scala:84:7, :192:{77,105}]\n wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 | io_schedule_bits_e_valid_0;\t// @[MSHR.scala:84:7, :192:105, :193:49]\n wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 | io_schedule_bits_x_valid_0;\t// @[MSHR.scala:84:7, :193:{49,77}]\n assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 | io_schedule_bits_dir_valid_0;\t// @[MSHR.scala:84:7, :193:{77,105}]\n assign io_schedule_valid_0 = _io_schedule_valid_T_5;\t// @[MSHR.scala:84:7, :193:105]\n wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty;\t// @[MSHR.scala:215:38, :310:71]\n wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state;\t// @[MSHR.scala:215:38, :310:71]\n wire _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients;\t// @[MSHR.scala:215:38, :310:71]\n wire after_c = final_meta_writeback_clients;\t// @[MSHR.scala:215:38, :315:27]\n wire prior_c = final_meta_writeback_clients;\t// @[MSHR.scala:215:38, :315:27]\n wire [8:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag;\t// @[MSHR.scala:215:38, :310:71]\n wire final_meta_writeback_hit;\t// @[MSHR.scala:215:38]\n wire req_clientBit = request_source == 6'h28;\t// @[Parameters.scala:46:9]\n wire _req_needT_T = request_opcode[2];\t// @[Parameters.scala:269:12]\n wire _final_meta_writeback_dirty_T_3 = request_opcode[2];\t// @[Parameters.scala:269:12]\n wire _req_needT_T_1 = ~_req_needT_T;\t// @[Parameters.scala:269:{5,12}]\n wire _GEN = request_opcode == 3'h5;\t// @[Parameters.scala:270:13]\n wire _req_needT_T_2;\t// @[Parameters.scala:270:13]\n assign _req_needT_T_2 = _GEN;\t// @[Parameters.scala:270:13]\n wire _excluded_client_T_6;\t// @[Parameters.scala:279:117]\n assign _excluded_client_T_6 = _GEN;\t// @[Parameters.scala:270:13, :279:117]\n wire _GEN_0 = request_param == 3'h1;\t// @[Parameters.scala:270:42]\n wire _req_needT_T_3;\t// @[Parameters.scala:270:42]\n assign _req_needT_T_3 = _GEN_0;\t// @[Parameters.scala:270:42]\n wire _final_meta_writeback_clients_T;\t// @[Parameters.scala:282:11]\n assign _final_meta_writeback_clients_T = _GEN_0;\t// @[Parameters.scala:270:42, :282:11]\n wire _io_schedule_bits_d_bits_param_T_7;\t// @[MSHR.scala:299:79]\n assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0;\t// @[Parameters.scala:270:42]\n wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3;\t// @[Parameters.scala:270:{13,33,42}]\n wire _req_needT_T_5 = _req_needT_T_1 | _req_needT_T_4;\t// @[Parameters.scala:269:{5,16}, :270:33]\n wire _GEN_1 = request_opcode == 3'h6;\t// @[Parameters.scala:271:14]\n wire _req_needT_T_6;\t// @[Parameters.scala:271:14]\n assign _req_needT_T_6 = _GEN_1;\t// @[Parameters.scala:271:14]\n wire _req_acquire_T;\t// @[MSHR.scala:219:36]\n assign _req_acquire_T = _GEN_1;\t// @[Parameters.scala:271:14]\n wire _excluded_client_T_1;\t// @[Parameters.scala:279:12]\n assign _excluded_client_T_1 = _GEN_1;\t// @[Parameters.scala:271:14, :279:12]\n wire _req_needT_T_7 = &request_opcode;\t// @[Parameters.scala:271:52]\n wire _req_needT_T_8 = _req_needT_T_6 | _req_needT_T_7;\t// @[Parameters.scala:271:{14,42,52}]\n wire _req_needT_T_9 = |request_param;\t// @[Parameters.scala:271:89]\n wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9;\t// @[Parameters.scala:271:{42,80,89}]\n wire req_needT = _req_needT_T_5 | _req_needT_T_10;\t// @[Parameters.scala:269:16, :270:70, :271:80]\n wire _req_acquire_T_1 = &request_opcode;\t// @[Parameters.scala:271:52]\n wire req_acquire = _req_acquire_T | _req_acquire_T_1;\t// @[MSHR.scala:219:{36,53,71}]\n wire meta_no_clients = ~_meta_no_clients_T;\t// @[MSHR.scala:220:{25,39}]\n wire _req_promoteT_T = &meta_state;\t// @[MSHR.scala:100:17, :221:81]\n wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T;\t// @[MSHR.scala:220:25, :221:{67,81}]\n wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT;\t// @[MSHR.scala:100:17, :148:17, :221:{40,67}]\n wire req_promoteT = req_acquire & _req_promoteT_T_2;\t// @[MSHR.scala:219:53, :221:{34,40}]\n wire _final_meta_writeback_dirty_T = request_opcode[0];\t// @[MSHR.scala:98:20, :224:65]\n wire _final_meta_writeback_dirty_T_1 = meta_dirty | _final_meta_writeback_dirty_T;\t// @[MSHR.scala:100:17, :224:{48,65}]\n wire _final_meta_writeback_state_T = request_param != 3'h3;\t// @[MSHR.scala:98:20, :225:55]\n wire _GEN_2 = meta_state == 2'h2;\t// @[MSHR.scala:100:17, :225:78]\n wire _final_meta_writeback_state_T_1;\t// @[MSHR.scala:225:78]\n assign _final_meta_writeback_state_T_1 = _GEN_2;\t// @[MSHR.scala:225:78]\n wire _final_meta_writeback_state_T_12;\t// @[MSHR.scala:240:70]\n assign _final_meta_writeback_state_T_12 = _GEN_2;\t// @[MSHR.scala:225:78, :240:70]\n wire _evict_T_2;\t// @[MSHR.scala:317:26]\n assign _evict_T_2 = _GEN_2;\t// @[MSHR.scala:225:78, :317:26]\n wire _before_T_1;\t// @[MSHR.scala:317:26]\n assign _before_T_1 = _GEN_2;\t// @[MSHR.scala:225:78, :317:26]\n wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1;\t// @[MSHR.scala:225:{55,64,78}]\n wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state;\t// @[MSHR.scala:100:17, :225:{40,64}]\n wire _GEN_3 = request_param == 3'h2;\t// @[Parameters.scala:282:43]\n wire _final_meta_writeback_clients_T_1;\t// @[Parameters.scala:282:43]\n assign _final_meta_writeback_clients_T_1 = _GEN_3;\t// @[Parameters.scala:282:43]\n wire _io_schedule_bits_d_bits_param_T_5;\t// @[MSHR.scala:299:79]\n assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3;\t// @[Parameters.scala:282:43]\n wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T | _final_meta_writeback_clients_T_1;\t// @[Parameters.scala:282:{11,34,43}]\n wire _final_meta_writeback_clients_T_3 = request_param == 3'h5;\t// @[Parameters.scala:282:75]\n wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 | _final_meta_writeback_clients_T_3;\t// @[Parameters.scala:282:{34,66,75}]\n wire _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 & req_clientBit;\t// @[Parameters.scala:46:9]\n wire _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5;\t// @[MSHR.scala:226:{52,56}]\n wire _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6;\t// @[MSHR.scala:100:17, :226:{50,52}]\n wire _final_meta_writeback_clients_T_8 = ~probes_toN;\t// @[MSHR.scala:151:23, :232:54]\n wire _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8;\t// @[MSHR.scala:100:17, :232:{52,54}]\n wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty;\t// @[MSHR.scala:100:17, :236:45]\n wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3;\t// @[MSHR.scala:236:{63,78}]\n wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 | _final_meta_writeback_dirty_T_4;\t// @[MSHR.scala:236:{45,60,63}]\n wire [1:0] _GEN_4 = {1'h1, ~req_acquire};\t// @[MSHR.scala:219:53, :238:40]\n wire [1:0] _final_meta_writeback_state_T_4;\t// @[MSHR.scala:238:40]\n assign _final_meta_writeback_state_T_4 = _GEN_4;\t// @[MSHR.scala:238:40]\n wire [1:0] _final_meta_writeback_state_T_6;\t// @[MSHR.scala:239:65]\n assign _final_meta_writeback_state_T_6 = _GEN_4;\t// @[MSHR.scala:238:40, :239:65]\n wire _final_meta_writeback_state_T_5 = ~meta_hit;\t// @[MSHR.scala:100:17, :239:41]\n wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1;\t// @[MSHR.scala:148:17, :239:{55,65}]\n wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire;\t// @[MSHR.scala:219:53, :220:25, :244:72]\n wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8};\t// @[MSHR.scala:244:{55,72}]\n wire _GEN_5 = meta_state == 2'h1;\t// @[MSHR.scala:100:17, :240:70]\n wire _final_meta_writeback_state_T_10;\t// @[MSHR.scala:240:70]\n assign _final_meta_writeback_state_T_10 = _GEN_5;\t// @[MSHR.scala:240:70]\n wire _io_schedule_bits_c_bits_param_T;\t// @[MSHR.scala:291:53]\n assign _io_schedule_bits_c_bits_param_T = _GEN_5;\t// @[MSHR.scala:240:70, :291:53]\n wire _evict_T_1;\t// @[MSHR.scala:317:26]\n assign _evict_T_1 = _GEN_5;\t// @[MSHR.scala:240:70, :317:26]\n wire _before_T;\t// @[MSHR.scala:317:26]\n assign _before_T = _GEN_5;\t// @[MSHR.scala:240:70, :317:26]\n wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1};\t// @[MSHR.scala:240:70]\n wire _final_meta_writeback_state_T_14 = &meta_state;\t// @[MSHR.scala:100:17, :221:81, :240:70]\n wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13;\t// @[MSHR.scala:240:70, :244:55]\n wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15;\t// @[MSHR.scala:239:{40,41,55}, :240:70]\n wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16;\t// @[Parameters.scala:270:70]\n wire _final_meta_writeback_clients_T_10 = ~probes_toN;\t// @[MSHR.scala:151:23, :232:54, :245:66]\n wire _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10;\t// @[MSHR.scala:100:17, :245:{64,66}]\n wire _final_meta_writeback_clients_T_12 = meta_hit & _final_meta_writeback_clients_T_11;\t// @[MSHR.scala:100:17, :245:{40,64}]\n wire _final_meta_writeback_clients_T_13 = req_acquire & req_clientBit;\t// @[Parameters.scala:46:9]\n wire _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 | _final_meta_writeback_clients_T_13;\t// @[MSHR.scala:245:{40,84}, :246:40]\n assign final_meta_writeback_tag = request_prio_2 | request_control ? meta_tag : request_tag;\t// @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30]\n wire _final_meta_writeback_clients_T_15 = ~probes_toN;\t// @[MSHR.scala:151:23, :232:54, :258:54]\n wire _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15;\t// @[MSHR.scala:100:17, :258:{52,54}]\n assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 | ~request_control;\t// @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21]\n assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5);\t// @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21]\n assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17;\t// @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36]\n assign final_meta_writeback_clients = bad_grant ? meta_hit & _final_meta_writeback_clients_T_16 : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14;\t// @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36]\n wire _honour_BtoT_T = meta_clients & req_clientBit;\t// @[Parameters.scala:46:9]\n wire _honour_BtoT_T_1 = _honour_BtoT_T;\t// @[MSHR.scala:276:{47,64}]\n wire honour_BtoT = meta_hit & _honour_BtoT_T_1;\t// @[MSHR.scala:100:17, :276:{30,64}]\n wire _excluded_client_T = meta_hit & request_prio_0;\t// @[MSHR.scala:98:20, :100:17, :279:38]\n wire _excluded_client_T_2 = &request_opcode;\t// @[Parameters.scala:271:52, :279:50]\n wire _excluded_client_T_3 = _excluded_client_T_1 | _excluded_client_T_2;\t// @[Parameters.scala:279:{12,40,50}]\n wire _excluded_client_T_4 = request_opcode == 3'h4;\t// @[Parameters.scala:279:87]\n wire _excluded_client_T_5 = _excluded_client_T_3 | _excluded_client_T_4;\t// @[Parameters.scala:279:{40,77,87}]\n wire _excluded_client_T_8 = _excluded_client_T_5;\t// @[Parameters.scala:279:{77,106}]\n wire _excluded_client_T_9 = _excluded_client_T & _excluded_client_T_8;\t// @[Parameters.scala:279:106]\n wire excluded_client = _excluded_client_T_9 & req_clientBit;\t// @[Parameters.scala:46:9]\n wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1;\t// @[MSHR.scala:100:17, :282:56]\n wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0;\t// @[Parameters.scala:270:70]\n assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1};\t// @[MSHR.scala:84:7, :282:{35,41}]\n wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6;\t// @[MSHR.scala:98:20, :283:51]\n wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0;\t// @[MSHR.scala:98:20, :284:55]\n wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode;\t// @[Parameters.scala:271:52]\n wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 | _io_schedule_bits_a_bits_block_T_2;\t// @[MSHR.scala:284:{55,71,89}]\n wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3;\t// @[MSHR.scala:284:{38,71}]\n assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T | _io_schedule_bits_a_bits_block_T_4;\t// @[MSHR.scala:283:{51,91}, :284:38]\n assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5;\t// @[MSHR.scala:84:7, :283:91]\n wire _io_schedule_bits_b_bits_param_T = ~s_rprobe;\t// @[MSHR.scala:121:33, :185:31, :286:42]\n wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1;\t// @[Parameters.scala:270:70]\n wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1};\t// @[MSHR.scala:98:20, :286:{61,97}]\n assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2;\t// @[MSHR.scala:286:{41,42,61}]\n assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3;\t// @[MSHR.scala:84:7, :286:41]\n wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe;\t// @[MSHR.scala:121:33, :185:31, :287:42]\n assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag;\t// @[MSHR.scala:98:20, :100:17, :287:{41,42}]\n assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1;\t// @[MSHR.scala:84:7, :287:41]\n wire _io_schedule_bits_b_bits_clients_T = ~excluded_client;\t// @[MSHR.scala:279:28, :289:53]\n assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients & _io_schedule_bits_b_bits_clients_T;\t// @[MSHR.scala:100:17, :289:{51,53}]\n assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1;\t// @[MSHR.scala:84:7, :289:51]\n assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty};\t// @[MSHR.scala:100:17, :290:41]\n assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T;\t// @[MSHR.scala:84:7, :290:41]\n assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1;\t// @[MSHR.scala:291:{41,53}]\n assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1;\t// @[MSHR.scala:84:7, :291:41]\n wire _io_schedule_bits_d_bits_param_T = ~req_acquire;\t// @[MSHR.scala:219:53, :298:42]\n wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT};\t// @[MSHR.scala:221:34, :300:53]\n wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1;\t// @[MSHR.scala:276:30, :301:53]\n wire _io_schedule_bits_d_bits_param_T_3 = ~(|request_param);\t// @[Parameters.scala:271:89]\n wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param;\t// @[MSHR.scala:98:20, :299:79, :300:53]\n wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4;\t// @[MSHR.scala:299:79, :301:53]\n wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6;\t// @[MSHR.scala:299:79]\n assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8;\t// @[MSHR.scala:98:20, :298:{41,42}, :299:79]\n assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9;\t// @[MSHR.scala:84:7, :298:41]\n wire _io_schedule_bits_dir_bits_data_T = ~s_release;\t// @[MSHR.scala:124:33, :186:32, :310:42]\n assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty;\t// @[MSHR.scala:310:{41,42,71}]\n assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state;\t// @[MSHR.scala:310:{41,42,71}]\n assign _io_schedule_bits_dir_bits_data_T_1_clients = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_clients;\t// @[MSHR.scala:310:{41,42,71}]\n assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 9'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag;\t// @[MSHR.scala:310:{41,42,71}]\n assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty;\t// @[MSHR.scala:84:7, :310:41]\n assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state;\t// @[MSHR.scala:84:7, :310:41]\n assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients;\t// @[MSHR.scala:84:7, :310:41]\n assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag;\t// @[MSHR.scala:84:7, :310:41]\n wire _evict_T = ~meta_hit;\t// @[MSHR.scala:100:17, :239:41, :338:32]\n wire [3:0] evict;\t// @[MSHR.scala:314:26]\n wire _evict_out_T = ~evict_c;\t// @[MSHR.scala:315:27, :318:32]\n wire [1:0] _GEN_6 = {1'h1, ~meta_dirty};\t// @[MSHR.scala:100:17, :319:32]\n wire [1:0] _evict_out_T_1;\t// @[MSHR.scala:319:32]\n assign _evict_out_T_1 = _GEN_6;\t// @[MSHR.scala:319:32]\n wire [1:0] _before_out_T_1;\t// @[MSHR.scala:319:32]\n assign _before_out_T_1 = _GEN_6;\t// @[MSHR.scala:319:32]\n wire _evict_T_3 = &meta_state;\t// @[MSHR.scala:100:17, :221:81, :317:26]\n wire [2:0] _GEN_7 = {2'h2, ~meta_dirty};\t// @[MSHR.scala:100:17, :319:32, :320:39]\n wire [2:0] _evict_out_T_2;\t// @[MSHR.scala:320:39]\n assign _evict_out_T_2 = _GEN_7;\t// @[MSHR.scala:320:39]\n wire [2:0] _before_out_T_2;\t// @[MSHR.scala:320:39]\n assign _before_out_T_2 = _GEN_7;\t// @[MSHR.scala:320:39]\n wire [2:0] _GEN_8 = {2'h3, ~meta_dirty};\t// @[MSHR.scala:100:17, :319:32, :320:76]\n wire [2:0] _evict_out_T_3;\t// @[MSHR.scala:320:76]\n assign _evict_out_T_3 = _GEN_8;\t// @[MSHR.scala:320:76]\n wire [2:0] _before_out_T_3;\t// @[MSHR.scala:320:76]\n assign _before_out_T_3 = _GEN_8;\t// @[MSHR.scala:320:76]\n wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3;\t// @[MSHR.scala:315:27, :320:{32,39,76}]\n wire _evict_T_4 = ~(|meta_state);\t// @[MSHR.scala:100:17, :104:22, :317:26]\n wire _evict_T_5 = ~_evict_T;\t// @[MSHR.scala:323:11, :338:32]\n assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0};\t// @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}]\n wire [3:0] before_0;\t// @[MSHR.scala:314:26]\n wire _before_out_T = ~before_c;\t// @[MSHR.scala:315:27, :318:32]\n wire _before_T_2 = &meta_state;\t// @[MSHR.scala:100:17, :221:81, :317:26]\n wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3;\t// @[MSHR.scala:315:27, :320:{32,39,76}]\n wire _before_T_3 = ~(|meta_state);\t// @[MSHR.scala:100:17, :104:22, :317:26]\n wire _before_T_4 = ~meta_hit;\t// @[MSHR.scala:100:17, :239:41, :323:11]\n assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0};\t// @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}]\n wire [3:0] after;\t// @[MSHR.scala:314:26]\n wire _GEN_9 = final_meta_writeback_state == 2'h1;\t// @[MSHR.scala:215:38, :317:26]\n wire _after_T;\t// @[MSHR.scala:317:26]\n assign _after_T = _GEN_9;\t// @[MSHR.scala:317:26]\n wire _prior_T;\t// @[MSHR.scala:317:26]\n assign _prior_T = _GEN_9;\t// @[MSHR.scala:317:26]\n wire _after_out_T = ~after_c;\t// @[MSHR.scala:315:27, :318:32]\n wire _GEN_10 = final_meta_writeback_state == 2'h2;\t// @[MSHR.scala:215:38, :317:26]\n wire _after_T_1;\t// @[MSHR.scala:317:26]\n assign _after_T_1 = _GEN_10;\t// @[MSHR.scala:317:26]\n wire _prior_T_1;\t// @[MSHR.scala:317:26]\n assign _prior_T_1 = _GEN_10;\t// @[MSHR.scala:317:26]\n wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty};\t// @[MSHR.scala:215:38, :319:32]\n wire [1:0] _after_out_T_1;\t// @[MSHR.scala:319:32]\n assign _after_out_T_1 = _GEN_11;\t// @[MSHR.scala:319:32]\n wire [1:0] _prior_out_T_1;\t// @[MSHR.scala:319:32]\n assign _prior_out_T_1 = _GEN_11;\t// @[MSHR.scala:319:32]\n wire _after_T_2 = &final_meta_writeback_state;\t// @[MSHR.scala:215:38, :317:26]\n wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty};\t// @[MSHR.scala:215:38, :319:32, :320:39]\n wire [2:0] _after_out_T_2;\t// @[MSHR.scala:320:39]\n assign _after_out_T_2 = _GEN_12;\t// @[MSHR.scala:320:39]\n wire [2:0] _prior_out_T_2;\t// @[MSHR.scala:320:39]\n assign _prior_out_T_2 = _GEN_12;\t// @[MSHR.scala:320:39]\n wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty};\t// @[MSHR.scala:215:38, :319:32, :320:76]\n wire [2:0] _after_out_T_3;\t// @[MSHR.scala:320:76]\n assign _after_out_T_3 = _GEN_13;\t// @[MSHR.scala:320:76]\n wire [2:0] _prior_out_T_3;\t// @[MSHR.scala:320:76]\n assign _prior_out_T_3 = _GEN_13;\t// @[MSHR.scala:320:76]\n wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3;\t// @[MSHR.scala:315:27, :320:{32,39,76}]\n wire _GEN_14 = final_meta_writeback_state == 2'h0;\t// @[MSHR.scala:215:38, :317:26]\n wire _after_T_3;\t// @[MSHR.scala:317:26]\n assign _after_T_3 = _GEN_14;\t// @[MSHR.scala:317:26]\n wire _prior_T_3;\t// @[MSHR.scala:317:26]\n assign _prior_T_3 = _GEN_14;\t// @[MSHR.scala:317:26]\n assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0};\t// @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26]\n wire probe_bit = io_sinkc_bits_source_0 == 6'h28;\t// @[Parameters.scala:46:9]\n wire _GEN_15 = probes_done | probe_bit;\t// @[Parameters.scala:46:9]\n wire _last_probe_T;\t// @[MSHR.scala:459:33]\n assign _last_probe_T = _GEN_15;\t// @[MSHR.scala:459:33]\n wire _probes_done_T;\t// @[MSHR.scala:467:32]\n assign _probes_done_T = _GEN_15;\t// @[MSHR.scala:459:33, :467:32]\n wire _last_probe_T_1 = ~excluded_client;\t// @[MSHR.scala:279:28, :289:53, :459:66]\n wire _last_probe_T_2 = meta_clients & _last_probe_T_1;\t// @[MSHR.scala:100:17, :459:{64,66}]\n wire last_probe = _last_probe_T == _last_probe_T_2;\t// @[MSHR.scala:459:{33,46,64}]\n wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1;\t// @[Parameters.scala:282:11]\n wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2;\t// @[Parameters.scala:282:43]\n wire _probe_toN_T_2 = _probe_toN_T | _probe_toN_T_1;\t// @[Parameters.scala:282:{11,34,43}]\n wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5;\t// @[Parameters.scala:282:75]\n wire probe_toN = _probe_toN_T_2 | _probe_toN_T_3;\t// @[Parameters.scala:282:{34,66,75}]\n wire _probes_toN_T = probe_toN & probe_bit;\t// @[Parameters.scala:46:9]\n wire _probes_toN_T_1 = probes_toN | _probes_toN_T;\t// @[MSHR.scala:151:23, :468:{30,35}]\n wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3;\t// @[MSHR.scala:84:7, :469:53]\n wire _probes_noT_T_1 = probes_noT | _probes_noT_T;\t// @[MSHR.scala:152:23, :469:{30,53}]\n wire _w_rprobeackfirst_T = w_rprobeackfirst | last_probe;\t// @[MSHR.scala:122:33, :459:46, :470:42]\n wire _GEN_16 = last_probe & io_sinkc_bits_last_0;\t// @[MSHR.scala:84:7, :459:46, :471:55]\n wire _w_rprobeacklast_T;\t// @[MSHR.scala:471:55]\n assign _w_rprobeacklast_T = _GEN_16;\t// @[MSHR.scala:471:55]\n wire _w_pprobeacklast_T;\t// @[MSHR.scala:473:55]\n assign _w_pprobeacklast_T = _GEN_16;\t// @[MSHR.scala:471:55, :473:55]\n wire _w_rprobeacklast_T_1 = w_rprobeacklast | _w_rprobeacklast_T;\t// @[MSHR.scala:123:33, :471:{40,55}]\n wire _w_pprobeackfirst_T = w_pprobeackfirst | last_probe;\t// @[MSHR.scala:132:33, :459:46, :472:42]\n wire _w_pprobeacklast_T_1 = w_pprobeacklast | _w_pprobeacklast_T;\t// @[MSHR.scala:133:33, :473:{40,55}]\n wire _set_pprobeack_T = ~(|request_offset);\t// @[MSHR.scala:98:20, :475:77]\n wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 | _set_pprobeack_T;\t// @[MSHR.scala:84:7, :475:{59,77}]\n wire set_pprobeack = last_probe & _set_pprobeack_T_1;\t// @[MSHR.scala:459:46, :475:{36,59}]\n wire _w_pprobeack_T = w_pprobeack | set_pprobeack;\t// @[MSHR.scala:134:33, :475:36, :476:32]\n wire _w_grant_T = ~(|request_offset);\t// @[MSHR.scala:98:20, :475:77, :490:33]\n wire _w_grant_T_1 = _w_grant_T | io_sinkd_bits_last_0;\t// @[MSHR.scala:84:7, :490:{33,41}]\n wire _gotT_T = io_sinkd_bits_param_0 == 3'h0;\t// @[MSHR.scala:84:7, :493:35]\n wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0;\t// @[MSHR.scala:84:7, :505:40]\n wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0;\t// @[MSHR.scala:84:7, :215:38, :505:{21,40}]\n wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0;\t// @[MSHR.scala:84:7, :215:38, :505:{21,40}]\n wire new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0;\t// @[MSHR.scala:84:7, :215:38, :505:{21,40}]\n wire [8:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0;\t// @[MSHR.scala:84:7, :215:38, :505:{21,40}]\n wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0;\t// @[MSHR.scala:84:7, :215:38, :505:{21,40}]\n wire [3:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0;\t// @[MSHR.scala:84:7, :215:38, :505:{21,40}]\n wire new_request_prio_0 = io_allocate_valid_0 ? allocate_as_full_prio_0 : request_prio_0;\t// @[MSHR.scala:84:7, :98:20, :504:34, :506:24]\n wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1;\t// @[MSHR.scala:84:7, :98:20, :504:34, :506:24]\n wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2;\t// @[MSHR.scala:84:7, :98:20, :504:34, :506:24]\n wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control;\t// @[MSHR.scala:84:7, :98:20, :504:34, :506:24]\n wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode;\t// @[MSHR.scala:84:7, :98:20, :504:34, :506:24]\n wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param;\t// @[MSHR.scala:84:7, :98:20, :504:34, :506:24]\n wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size;\t// @[MSHR.scala:84:7, :98:20, :504:34, :506:24]\n wire [5:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source;\t// @[MSHR.scala:84:7, :98:20, :504:34, :506:24]\n wire [8:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag;\t// @[MSHR.scala:84:7, :98:20, :504:34, :506:24]\n wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset;\t// @[MSHR.scala:84:7, :98:20, :504:34, :506:24]\n wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put;\t// @[MSHR.scala:84:7, :98:20, :504:34, :506:24]\n wire [10:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set;\t// @[MSHR.scala:84:7, :98:20, :504:34, :506:24]\n wire _new_needT_T = new_request_opcode[2];\t// @[Parameters.scala:269:12]\n wire _new_needT_T_1 = ~_new_needT_T;\t// @[Parameters.scala:269:{5,12}]\n wire _GEN_17 = new_request_opcode == 3'h5;\t// @[Parameters.scala:270:13]\n wire _new_needT_T_2;\t// @[Parameters.scala:270:13]\n assign _new_needT_T_2 = _GEN_17;\t// @[Parameters.scala:270:13]\n wire _new_skipProbe_T_5;\t// @[Parameters.scala:279:117]\n assign _new_skipProbe_T_5 = _GEN_17;\t// @[Parameters.scala:270:13, :279:117]\n wire _new_needT_T_3 = new_request_param == 3'h1;\t// @[Parameters.scala:270:42]\n wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3;\t// @[Parameters.scala:270:{13,33,42}]\n wire _new_needT_T_5 = _new_needT_T_1 | _new_needT_T_4;\t// @[Parameters.scala:269:{5,16}, :270:33]\n wire _T_615 = new_request_opcode == 3'h6;\t// @[Parameters.scala:271:14]\n wire _new_needT_T_6;\t// @[Parameters.scala:271:14]\n assign _new_needT_T_6 = _T_615;\t// @[Parameters.scala:271:14]\n wire _new_skipProbe_T;\t// @[Parameters.scala:279:12]\n assign _new_skipProbe_T = _T_615;\t// @[Parameters.scala:271:14, :279:12]\n wire _new_needT_T_7 = &new_request_opcode;\t// @[Parameters.scala:271:52]\n wire _new_needT_T_8 = _new_needT_T_6 | _new_needT_T_7;\t// @[Parameters.scala:271:{14,42,52}]\n wire _new_needT_T_9 = |new_request_param;\t// @[Parameters.scala:271:89]\n wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9;\t// @[Parameters.scala:271:{42,80,89}]\n wire new_needT = _new_needT_T_5 | _new_needT_T_10;\t// @[Parameters.scala:269:16, :270:70, :271:80]\n wire new_clientBit = new_request_source == 6'h28;\t// @[Parameters.scala:46:9]\n wire _new_skipProbe_T_1 = &new_request_opcode;\t// @[Parameters.scala:271:52, :279:50]\n wire _new_skipProbe_T_2 = _new_skipProbe_T | _new_skipProbe_T_1;\t// @[Parameters.scala:279:{12,40,50}]\n wire _new_skipProbe_T_3 = new_request_opcode == 3'h4;\t// @[Parameters.scala:279:87]\n wire _new_skipProbe_T_4 = _new_skipProbe_T_2 | _new_skipProbe_T_3;\t// @[Parameters.scala:279:{40,77,87}]\n wire _new_skipProbe_T_7 = _new_skipProbe_T_4;\t// @[Parameters.scala:279:{77,106}]\n wire new_skipProbe = _new_skipProbe_T_7 & new_clientBit;\t// @[Parameters.scala:46:9]\n wire [3:0] prior;\t// @[MSHR.scala:314:26]\n wire _prior_out_T = ~prior_c;\t// @[MSHR.scala:315:27, :318:32]\n wire _prior_T_2 = &final_meta_writeback_state;\t// @[MSHR.scala:215:38, :317:26]\n wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3;\t// @[MSHR.scala:315:27, :320:{32,39,76}]\n assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0};\t// @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26]\n wire _T_574 = io_directory_valid_0 | _new_meta_T;\t// @[MSHR.scala:84:7, :505:40, :539:28]"}}},{"rowIdx":576,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to the following Chisel files.\nFile Monitor.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.tilelink\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.experimental.SourceLine\n\nimport org.chipsalliance.cde.config._\nimport org.chipsalliance.diplomacy._\n\nimport freechips.rocketchip.diplomacy.EnableMonitors\nimport freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}\nimport freechips.rocketchip.util.PlusArg\n\ncase class TLMonitorArgs(edge: TLEdge)\n\nabstract class TLMonitorBase(args: TLMonitorArgs) extends Module\n{\n val io = IO(new Bundle {\n val in = Input(new TLBundle(args.edge.bundle))\n })\n\n def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit\n legalize(io.in, args.edge, reset)\n}\n\nobject TLMonitor {\n def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {\n if (enable) {\n EnableMonitors { implicit p => node := TLEphemeralNode()(ValName(\"monitor\")) }\n } else { node }\n }\n}\n\nclass TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)\n{\n require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))\n\n val cover_prop_class = PropertyClass.Default\n\n //Like assert but can flip to being an assumption for formal verification\n def monAssert(cond: Bool, message: String): Unit =\n if (monitorDir == MonitorDirection.Monitor) {\n assert(cond, message)\n } else {\n Property(monitorDir, cond, message, PropertyClass.Default)\n }\n\n def assume(cond: Bool, message: String): Unit =\n if (monitorDir == MonitorDirection.Monitor) {\n assert(cond, message)\n } else {\n Property(monitorDir.flip, cond, message, PropertyClass.Default)\n }\n\n def extra = {\n args.edge.sourceInfo match {\n case SourceLine(filename, line, col) => s\" (connected at $filename:$line:$col)\"\n case _ => \"\"\n }\n }\n\n def visible(address: UInt, source: UInt, edge: TLEdge) =\n edge.client.clients.map { c =>\n !c.sourceId.contains(source) ||\n c.visibility.map(_.contains(address)).reduce(_ || _)\n }.reduce(_ && _)\n\n def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {\n //switch this flag to turn on diplomacy in error messages\n def diplomacyInfo = if (true) \"\" else \"\\nThe diplomacy information for the edge is as follows:\\n\" + edge.formatEdge + \"\\n\"\n monAssert (TLMessages.isA(bundle.opcode), \"'A' channel has invalid opcode\" + extra)\n\n // Reuse these subexpressions to save some firrtl lines\n val source_ok = edge.client.contains(bundle.source)\n val is_aligned = edge.isAligned(bundle.address, bundle.size)\n val mask = edge.full_mask(bundle)\n\n monAssert (visible(edge.address(bundle), bundle.source, edge), \"'A' channel carries an address illegal for the specified bank visibility\")\n\n //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B\n //TODO: check for acquireT?\n when (bundle.opcode === TLMessages.AcquireBlock) {\n monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters\" + diplomacyInfo + extra)\n monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock from a client which does not support Probe\" + diplomacyInfo + extra)\n monAssert (source_ok, \"'A' channel AcquireBlock carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'A' channel AcquireBlock smaller than a beat\" + extra)\n monAssert (is_aligned, \"'A' channel AcquireBlock address not aligned to size\" + extra)\n monAssert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquireBlock carries invalid grow param\" + extra)\n monAssert (~bundle.mask === 0.U, \"'A' channel AcquireBlock contains invalid mask\" + extra)\n monAssert (!bundle.corrupt, \"'A' channel AcquireBlock is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.AcquirePerm) {\n monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters\" + diplomacyInfo + extra)\n monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm from a client which does not support Probe\" + diplomacyInfo + extra)\n monAssert (source_ok, \"'A' channel AcquirePerm carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'A' channel AcquirePerm smaller than a beat\" + extra)\n monAssert (is_aligned, \"'A' channel AcquirePerm address not aligned to size\" + extra)\n monAssert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquirePerm carries invalid grow param\" + extra)\n monAssert (bundle.param =/= TLPermissions.NtoB, \"'A' channel AcquirePerm requests NtoB\" + extra)\n monAssert (~bundle.mask === 0.U, \"'A' channel AcquirePerm contains invalid mask\" + extra)\n monAssert (!bundle.corrupt, \"'A' channel AcquirePerm is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.Get) {\n monAssert (edge.master.emitsGet(bundle.source, bundle.size), \"'A' channel carries Get type which master claims it can't emit\" + diplomacyInfo + extra)\n monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), \"'A' channel carries Get type which slave claims it can't support\" + diplomacyInfo + extra)\n monAssert (source_ok, \"'A' channel Get carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'A' channel Get carries invalid param\" + extra)\n monAssert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n monAssert (!bundle.corrupt, \"'A' channel Get is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.PutFullData) {\n monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type which is unexpected using diplomatic parameters\" + diplomacyInfo + extra)\n monAssert (source_ok, \"'A' channel PutFull carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'A' channel PutFull carries invalid param\" + extra)\n monAssert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.PutPartialData) {\n monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type which is unexpected using diplomatic parameters\" + extra)\n monAssert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'A' channel PutPartial carries invalid param\" + extra)\n monAssert ((bundle.mask & ~mask) === 0.U, \"'A' channel PutPartial contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.ArithmeticData) {\n monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type which is unexpected using diplomatic parameters\" + extra)\n monAssert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n monAssert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n monAssert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.LogicalData) {\n monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type which is unexpected using diplomatic parameters\" + extra)\n monAssert (source_ok, \"'A' channel Logical carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n monAssert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n monAssert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.Hint) {\n monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type which is unexpected using diplomatic parameters\" + extra)\n monAssert (source_ok, \"'A' channel Hint carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n monAssert (TLHints.isHints(bundle.param), \"'A' channel Hint carries invalid opcode param\" + extra)\n monAssert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n monAssert (!bundle.corrupt, \"'A' channel Hint is corrupt\" + extra)\n }\n }\n\n def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {\n monAssert (TLMessages.isB(bundle.opcode), \"'B' channel has invalid opcode\" + extra)\n\n monAssert (visible(edge.address(bundle), bundle.source, edge), \"'B' channel carries an address illegal for the specified bank visibility\")\n\n // Reuse these subexpressions to save some firrtl lines\n val address_ok = edge.manager.containsSafe(edge.address(bundle))\n val is_aligned = edge.isAligned(bundle.address, bundle.size)\n val mask = edge.full_mask(bundle)\n val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source\n\n when (bundle.opcode === TLMessages.Probe) {\n assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), \"'B' channel carries Probe type which is unexpected using diplomatic parameters\" + extra)\n assume (address_ok, \"'B' channel Probe carries unmanaged address\" + extra)\n assume (legal_source, \"'B' channel Probe carries source that is not first source\" + extra)\n assume (is_aligned, \"'B' channel Probe address not aligned to size\" + extra)\n assume (TLPermissions.isCap(bundle.param), \"'B' channel Probe carries invalid cap param\" + extra)\n assume (bundle.mask === mask, \"'B' channel Probe contains invalid mask\" + extra)\n assume (!bundle.corrupt, \"'B' channel Probe is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.Get) {\n monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), \"'B' channel carries Get type which is unexpected using diplomatic parameters\" + extra)\n monAssert (address_ok, \"'B' channel Get carries unmanaged address\" + extra)\n monAssert (legal_source, \"'B' channel Get carries source that is not first source\" + extra)\n monAssert (is_aligned, \"'B' channel Get address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'B' channel Get carries invalid param\" + extra)\n monAssert (bundle.mask === mask, \"'B' channel Get contains invalid mask\" + extra)\n monAssert (!bundle.corrupt, \"'B' channel Get is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.PutFullData) {\n monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), \"'B' channel carries PutFull type which is unexpected using diplomatic parameters\" + extra)\n monAssert (address_ok, \"'B' channel PutFull carries unmanaged address\" + extra)\n monAssert (legal_source, \"'B' channel PutFull carries source that is not first source\" + extra)\n monAssert (is_aligned, \"'B' channel PutFull address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'B' channel PutFull carries invalid param\" + extra)\n monAssert (bundle.mask === mask, \"'B' channel PutFull contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.PutPartialData) {\n monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), \"'B' channel carries PutPartial type which is unexpected using diplomatic parameters\" + extra)\n monAssert (address_ok, \"'B' channel PutPartial carries unmanaged address\" + extra)\n monAssert (legal_source, \"'B' channel PutPartial carries source that is not first source\" + extra)\n monAssert (is_aligned, \"'B' channel PutPartial address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'B' channel PutPartial carries invalid param\" + extra)\n monAssert ((bundle.mask & ~mask) === 0.U, \"'B' channel PutPartial contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.ArithmeticData) {\n monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), \"'B' channel carries Arithmetic type unsupported by master\" + extra)\n monAssert (address_ok, \"'B' channel Arithmetic carries unmanaged address\" + extra)\n monAssert (legal_source, \"'B' channel Arithmetic carries source that is not first source\" + extra)\n monAssert (is_aligned, \"'B' channel Arithmetic address not aligned to size\" + extra)\n monAssert (TLAtomics.isArithmetic(bundle.param), \"'B' channel Arithmetic carries invalid opcode param\" + extra)\n monAssert (bundle.mask === mask, \"'B' channel Arithmetic contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.LogicalData) {\n monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), \"'B' channel carries Logical type unsupported by client\" + extra)\n monAssert (address_ok, \"'B' channel Logical carries unmanaged address\" + extra)\n monAssert (legal_source, \"'B' channel Logical carries source that is not first source\" + extra)\n monAssert (is_aligned, \"'B' channel Logical address not aligned to size\" + extra)\n monAssert (TLAtomics.isLogical(bundle.param), \"'B' channel Logical carries invalid opcode param\" + extra)\n monAssert (bundle.mask === mask, \"'B' channel Logical contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.Hint) {\n monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), \"'B' channel carries Hint type unsupported by client\" + extra)\n monAssert (address_ok, \"'B' channel Hint carries unmanaged address\" + extra)\n monAssert (legal_source, \"'B' channel Hint carries source that is not first source\" + extra)\n monAssert (is_aligned, \"'B' channel Hint address not aligned to size\" + extra)\n monAssert (bundle.mask === mask, \"'B' channel Hint contains invalid mask\" + extra)\n monAssert (!bundle.corrupt, \"'B' channel Hint is corrupt\" + extra)\n }\n }\n\n def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {\n monAssert (TLMessages.isC(bundle.opcode), \"'C' channel has invalid opcode\" + extra)\n\n val source_ok = edge.client.contains(bundle.source)\n val is_aligned = edge.isAligned(bundle.address, bundle.size)\n val address_ok = edge.manager.containsSafe(edge.address(bundle))\n\n monAssert (visible(edge.address(bundle), bundle.source, edge), \"'C' channel carries an address illegal for the specified bank visibility\")\n\n when (bundle.opcode === TLMessages.ProbeAck) {\n monAssert (address_ok, \"'C' channel ProbeAck carries unmanaged address\" + extra)\n monAssert (source_ok, \"'C' channel ProbeAck carries invalid source ID\" + extra)\n monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'C' channel ProbeAck smaller than a beat\" + extra)\n monAssert (is_aligned, \"'C' channel ProbeAck address not aligned to size\" + extra)\n monAssert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAck carries invalid report param\" + extra)\n monAssert (!bundle.corrupt, \"'C' channel ProbeAck is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.ProbeAckData) {\n monAssert (address_ok, \"'C' channel ProbeAckData carries unmanaged address\" + extra)\n monAssert (source_ok, \"'C' channel ProbeAckData carries invalid source ID\" + extra)\n monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'C' channel ProbeAckData smaller than a beat\" + extra)\n monAssert (is_aligned, \"'C' channel ProbeAckData address not aligned to size\" + extra)\n monAssert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAckData carries invalid report param\" + extra)\n }\n\n when (bundle.opcode === TLMessages.Release) {\n monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries Release type unsupported by manager\" + extra)\n monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), \"'C' channel carries Release from a client which does not support Probe\" + extra)\n monAssert (source_ok, \"'C' channel Release carries invalid source ID\" + extra)\n monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'C' channel Release smaller than a beat\" + extra)\n monAssert (is_aligned, \"'C' channel Release address not aligned to size\" + extra)\n monAssert (TLPermissions.isReport(bundle.param), \"'C' channel Release carries invalid report param\" + extra)\n monAssert (!bundle.corrupt, \"'C' channel Release is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.ReleaseData) {\n monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries ReleaseData type unsupported by manager\" + extra)\n monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), \"'C' channel carries Release from a client which does not support Probe\" + extra)\n monAssert (source_ok, \"'C' channel ReleaseData carries invalid source ID\" + extra)\n monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'C' channel ReleaseData smaller than a beat\" + extra)\n monAssert (is_aligned, \"'C' channel ReleaseData address not aligned to size\" + extra)\n monAssert (TLPermissions.isReport(bundle.param), \"'C' channel ReleaseData carries invalid report param\" + extra)\n }\n\n when (bundle.opcode === TLMessages.AccessAck) {\n monAssert (address_ok, \"'C' channel AccessAck carries unmanaged address\" + extra)\n monAssert (source_ok, \"'C' channel AccessAck carries invalid source ID\" + extra)\n monAssert (is_aligned, \"'C' channel AccessAck address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'C' channel AccessAck carries invalid param\" + extra)\n monAssert (!bundle.corrupt, \"'C' channel AccessAck is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.AccessAckData) {\n monAssert (address_ok, \"'C' channel AccessAckData carries unmanaged address\" + extra)\n monAssert (source_ok, \"'C' channel AccessAckData carries invalid source ID\" + extra)\n monAssert (is_aligned, \"'C' channel AccessAckData address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'C' channel AccessAckData carries invalid param\" + extra)\n }\n\n when (bundle.opcode === TLMessages.HintAck) {\n monAssert (address_ok, \"'C' channel HintAck carries unmanaged address\" + extra)\n monAssert (source_ok, \"'C' channel HintAck carries invalid source ID\" + extra)\n monAssert (is_aligned, \"'C' channel HintAck address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'C' channel HintAck carries invalid param\" + extra)\n monAssert (!bundle.corrupt, \"'C' channel HintAck is corrupt\" + extra)\n }\n }\n\n def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {\n assume (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n\n val source_ok = edge.client.contains(bundle.source)\n val sink_ok = bundle.sink < edge.manager.endSinkId.U\n val deny_put_ok = edge.manager.mayDenyPut.B\n val deny_get_ok = edge.manager.mayDenyGet.B\n\n when (bundle.opcode === TLMessages.ReleaseAck) {\n assume (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'D' channel ReleaseAck smaller than a beat\" + extra)\n assume (bundle.param === 0.U, \"'D' channel ReleaseeAck carries invalid param\" + extra)\n assume (!bundle.corrupt, \"'D' channel ReleaseAck is corrupt\" + extra)\n assume (!bundle.denied, \"'D' channel ReleaseAck is denied\" + extra)\n }\n\n when (bundle.opcode === TLMessages.Grant) {\n assume (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n assume (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'D' channel Grant smaller than a beat\" + extra)\n assume (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n assume (bundle.param =/= TLPermissions.toN, \"'D' channel Grant carries toN param\" + extra)\n assume (!bundle.corrupt, \"'D' channel Grant is corrupt\" + extra)\n assume (deny_put_ok || !bundle.denied, \"'D' channel Grant is denied\" + extra)\n }\n\n when (bundle.opcode === TLMessages.GrantData) {\n assume (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n assume (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'D' channel GrantData smaller than a beat\" + extra)\n assume (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n assume (bundle.param =/= TLPermissions.toN, \"'D' channel GrantData carries toN param\" + extra)\n assume (!bundle.denied || bundle.corrupt, \"'D' channel GrantData is denied but not corrupt\" + extra)\n assume (deny_get_ok || !bundle.denied, \"'D' channel GrantData is denied\" + extra)\n }\n\n when (bundle.opcode === TLMessages.AccessAck) {\n assume (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n // size is ignored\n assume (bundle.param === 0.U, \"'D' channel AccessAck carries invalid param\" + extra)\n assume (!bundle.corrupt, \"'D' channel AccessAck is corrupt\" + extra)\n assume (deny_put_ok || !bundle.denied, \"'D' channel AccessAck is denied\" + extra)\n }\n\n when (bundle.opcode === TLMessages.AccessAckData) {\n assume (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n // size is ignored\n assume (bundle.param === 0.U, \"'D' channel AccessAckData carries invalid param\" + extra)\n assume (!bundle.denied || bundle.corrupt, \"'D' channel AccessAckData is denied but not corrupt\" + extra)\n assume (deny_get_ok || !bundle.denied, \"'D' channel AccessAckData is denied\" + extra)\n }\n\n when (bundle.opcode === TLMessages.HintAck) {\n assume (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n // size is ignored\n assume (bundle.param === 0.U, \"'D' channel HintAck carries invalid param\" + extra)\n assume (!bundle.corrupt, \"'D' channel HintAck is corrupt\" + extra)\n assume (deny_put_ok || !bundle.denied, \"'D' channel HintAck is denied\" + extra)\n }\n }\n\n def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {\n val sink_ok = bundle.sink < edge.manager.endSinkId.U\n monAssert (sink_ok, \"'E' channels carries invalid sink ID\" + extra)\n }\n\n def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {\n when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }\n when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }\n if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {\n when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }\n when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }\n when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }\n } else {\n monAssert (!bundle.b.valid, \"'B' channel valid and not TL-C\" + extra)\n monAssert (!bundle.c.valid, \"'C' channel valid and not TL-C\" + extra)\n monAssert (!bundle.e.valid, \"'E' channel valid and not TL-C\" + extra)\n }\n }\n\n def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {\n val a_first = edge.first(a.bits, a.fire)\n val opcode = Reg(UInt())\n val param = Reg(UInt())\n val size = Reg(UInt())\n val source = Reg(UInt())\n val address = Reg(UInt())\n when (a.valid && !a_first) {\n monAssert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n monAssert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n monAssert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n monAssert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n monAssert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n }\n when (a.fire && a_first) {\n opcode := a.bits.opcode\n param := a.bits.param\n size := a.bits.size\n source := a.bits.source\n address := a.bits.address\n }\n }\n\n def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {\n val b_first = edge.first(b.bits, b.fire)\n val opcode = Reg(UInt())\n val param = Reg(UInt())\n val size = Reg(UInt())\n val source = Reg(UInt())\n val address = Reg(UInt())\n when (b.valid && !b_first) {\n monAssert (b.bits.opcode === opcode, \"'B' channel opcode changed within multibeat operation\" + extra)\n monAssert (b.bits.param === param, \"'B' channel param changed within multibeat operation\" + extra)\n monAssert (b.bits.size === size, \"'B' channel size changed within multibeat operation\" + extra)\n monAssert (b.bits.source === source, \"'B' channel source changed within multibeat operation\" + extra)\n monAssert (b.bits.address=== address,\"'B' channel addresss changed with multibeat operation\" + extra)\n }\n when (b.fire && b_first) {\n opcode := b.bits.opcode\n param := b.bits.param\n size := b.bits.size\n source := b.bits.source\n address := b.bits.address\n }\n }\n\n def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {\n // Symbolic variable\n val sym_source = Wire(UInt(edge.client.endSourceId.W))\n // TODO: Connect sym_source to a fixed value for simulation and to a\n // free wire in formal\n sym_source := 0.U\n\n // Type casting Int to UInt\n val maxSourceId = Wire(UInt(edge.client.endSourceId.W))\n maxSourceId := edge.client.endSourceId.U\n\n // Delayed verison of sym_source\n val sym_source_d = Reg(UInt(edge.client.endSourceId.W))\n sym_source_d := sym_source\n\n // These will be constraints for FV setup\n Property(\n MonitorDirection.Monitor,\n (sym_source === sym_source_d),\n \"sym_source should remain stable\",\n PropertyClass.Default)\n Property(\n MonitorDirection.Monitor,\n (sym_source <= maxSourceId),\n \"sym_source should take legal value\",\n PropertyClass.Default)\n\n val my_resp_pend = RegInit(false.B)\n val my_opcode = Reg(UInt())\n val my_size = Reg(UInt())\n\n val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)\n val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)\n\n val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)\n val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)\n\n val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)\n val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)\n when (my_set_resp_pend) {\n my_resp_pend := true.B\n } .elsewhen (my_clr_resp_pend) {\n my_resp_pend := false.B\n }\n\n when (my_a_first_beat) {\n my_opcode := bundle.a.bits.opcode\n my_size := bundle.a.bits.size\n }\n\n val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)\n val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)\n\n val my_resp_opcode_legal = Wire(Bool())\n when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||\n (my_resp_opcode === TLMessages.LogicalData)) {\n my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)\n } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {\n my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)\n } .otherwise {\n my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)\n }\n\n monAssert (IfThen(my_resp_pend, !my_a_first_beat),\n \"Request message should not be sent with a source ID, for which a response message\" +\n \"is already pending (not received until current cycle) for a prior request message\" +\n \"with the same source ID\" + extra)\n\n assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),\n \"Response message should be accepted with a source ID only if a request message with the\" +\n \"same source ID has been accepted or is being accepted in the current cycle\" + extra)\n assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),\n \"Response message should be sent with a source ID only if a request message with the\" +\n \"same source ID has been accepted or is being sent in the current cycle\" + extra)\n assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),\n \"If d_valid is 1, then d_size should be same as a_size of the corresponding request\" +\n \"message\" + extra)\n assume (IfThen(my_d_first_beat, my_resp_opcode_legal),\n \"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding\" +\n \"request message\" + extra)\n }\n\n def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {\n val c_first = edge.first(c.bits, c.fire)\n val opcode = Reg(UInt())\n val param = Reg(UInt())\n val size = Reg(UInt())\n val source = Reg(UInt())\n val address = Reg(UInt())\n when (c.valid && !c_first) {\n monAssert (c.bits.opcode === opcode, \"'C' channel opcode changed within multibeat operation\" + extra)\n monAssert (c.bits.param === param, \"'C' channel param changed within multibeat operation\" + extra)\n monAssert (c.bits.size === size, \"'C' channel size changed within multibeat operation\" + extra)\n monAssert (c.bits.source === source, \"'C' channel source changed within multibeat operation\" + extra)\n monAssert (c.bits.address=== address,\"'C' channel address changed with multibeat operation\" + extra)\n }\n when (c.fire && c_first) {\n opcode := c.bits.opcode\n param := c.bits.param\n size := c.bits.size\n source := c.bits.source\n address := c.bits.address\n }\n }\n\n def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {\n val d_first = edge.first(d.bits, d.fire)\n val opcode = Reg(UInt())\n val param = Reg(UInt())\n val size = Reg(UInt())\n val source = Reg(UInt())\n val sink = Reg(UInt())\n val denied = Reg(Bool())\n when (d.valid && !d_first) {\n assume (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n assume (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n assume (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n assume (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n assume (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n assume (d.bits.denied === denied, \"'D' channel denied changed with multibeat operation\" + extra)\n }\n when (d.fire && d_first) {\n opcode := d.bits.opcode\n param := d.bits.param\n size := d.bits.size\n source := d.bits.source\n sink := d.bits.sink\n denied := d.bits.denied\n }\n }\n\n def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {\n legalizeMultibeatA(bundle.a, edge)\n legalizeMultibeatD(bundle.d, edge)\n if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {\n legalizeMultibeatB(bundle.b, edge)\n legalizeMultibeatC(bundle.c, edge)\n }\n }\n\n //This is left in for almond which doesn't adhere to the tilelink protocol\n @deprecated(\"Use legalizeADSource instead if possible\",\"\")\n def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {\n val inflight = RegInit(0.U(edge.client.endSourceId.W))\n\n val a_first = edge.first(bundle.a.bits, bundle.a.fire)\n val d_first = edge.first(bundle.d.bits, bundle.d.fire)\n\n val a_set = WireInit(0.U(edge.client.endSourceId.W))\n when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {\n a_set := UIntToOH(bundle.a.bits.source)\n assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n }\n\n val d_clr = WireInit(0.U(edge.client.endSourceId.W))\n val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck\n when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {\n d_clr := UIntToOH(bundle.d.bits.source)\n assume((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n }\n\n if (edge.manager.minLatency > 0) {\n assume(a_set =/= d_clr || !a_set.orR, s\"'A' and 'D' concurrent, despite minlatency > 0\" + extra)\n }\n\n inflight := (inflight | a_set) & ~d_clr\n\n val watchdog = RegInit(0.U(32.W))\n val limit = PlusArg(\"tilelink_timeout\",\n docstring=\"Kill emulation after INT waiting TileLink cycles. Off if 0.\")\n assert (!inflight.orR || limit === 0.U || watchdog < limit, \"TileLink timeout expired\" + extra)\n\n watchdog := watchdog + 1.U\n when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }\n }\n\n def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {\n val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)\n val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything\n val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)\n val log_a_size_bus_size = log2Ceil(a_size_bus_size)\n def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits\n\n val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error\n inflight.suggestName(\"inflight\")\n val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))\n inflight_opcodes.suggestName(\"inflight_opcodes\")\n val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))\n inflight_sizes.suggestName(\"inflight_sizes\")\n\n val a_first = edge.first(bundle.a.bits, bundle.a.fire)\n a_first.suggestName(\"a_first\")\n val d_first = edge.first(bundle.d.bits, bundle.d.fire)\n d_first.suggestName(\"d_first\")\n\n val a_set = WireInit(0.U(edge.client.endSourceId.W))\n val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))\n a_set.suggestName(\"a_set\")\n a_set_wo_ready.suggestName(\"a_set_wo_ready\")\n val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))\n a_opcodes_set.suggestName(\"a_opcodes_set\")\n val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))\n a_sizes_set.suggestName(\"a_sizes_set\")\n\n val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))\n a_opcode_lookup.suggestName(\"a_opcode_lookup\")\n a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U\n\n val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))\n a_size_lookup.suggestName(\"a_size_lookup\")\n a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U\n\n val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))\n val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))\n\n val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))\n a_opcodes_set_interm.suggestName(\"a_opcodes_set_interm\")\n val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))\n a_sizes_set_interm.suggestName(\"a_sizes_set_interm\")\n\n when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {\n a_set_wo_ready := UIntToOH(bundle.a.bits.source)\n }\n\n when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {\n a_set := UIntToOH(bundle.a.bits.source)\n a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U\n a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U\n a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)\n a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)\n monAssert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n }\n\n val d_clr = WireInit(0.U(edge.client.endSourceId.W))\n val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))\n d_clr.suggestName(\"d_clr\")\n d_clr_wo_ready.suggestName(\"d_clr_wo_ready\")\n val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))\n d_opcodes_clr.suggestName(\"d_opcodes_clr\")\n val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))\n d_sizes_clr.suggestName(\"d_sizes_clr\")\n\n val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck\n when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {\n d_clr_wo_ready := UIntToOH(bundle.d.bits.source)\n }\n\n when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {\n d_clr := UIntToOH(bundle.d.bits.source)\n d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)\n d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)\n }\n when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {\n val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)\n assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, \"'D' channel acknowledged for nothing inflight\" + extra)\n\n when (same_cycle_resp) {\n assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||\n (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), \"'D' channel contains improper opcode response\" + extra)\n assume((bundle.a.bits.size === bundle.d.bits.size), \"'D' channel contains improper response size\" + extra)\n } .otherwise {\n assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||\n (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), \"'D' channel contains improper opcode response\" + extra)\n assume((bundle.d.bits.size === a_size_lookup), \"'D' channel contains improper response size\" + extra)\n }\n }\n when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {\n assume((!bundle.d.ready) || bundle.a.ready, \"ready check\")\n }\n\n if (edge.manager.minLatency > 0) {\n assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s\"'A' and 'D' concurrent, despite minlatency > 0\" + extra)\n }\n\n inflight := (inflight | a_set) & ~d_clr\n inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr\n inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr\n\n val watchdog = RegInit(0.U(32.W))\n val limit = PlusArg(\"tilelink_timeout\",\n docstring=\"Kill emulation after INT waiting TileLink cycles. Off if 0.\")\n monAssert (!inflight.orR || limit === 0.U || watchdog < limit, \"TileLink timeout expired\" + extra)\n\n watchdog := watchdog + 1.U\n when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }\n }\n\n def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {\n val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)\n val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything\n\n val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)\n val log_c_size_bus_size = log2Ceil(c_size_bus_size)\n def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits\n\n val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))\n val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))\n val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))\n inflight.suggestName(\"inflight\")\n inflight_opcodes.suggestName(\"inflight_opcodes\")\n inflight_sizes.suggestName(\"inflight_sizes\")\n\n val c_first = edge.first(bundle.c.bits, bundle.c.fire)\n val d_first = edge.first(bundle.d.bits, bundle.d.fire)\n c_first.suggestName(\"c_first\")\n d_first.suggestName(\"d_first\")\n\n val c_set = WireInit(0.U(edge.client.endSourceId.W))\n val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))\n val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))\n val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))\n c_set.suggestName(\"c_set\")\n c_set_wo_ready.suggestName(\"c_set_wo_ready\")\n c_opcodes_set.suggestName(\"c_opcodes_set\")\n c_sizes_set.suggestName(\"c_sizes_set\")\n\n val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))\n val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))\n c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U\n c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U\n c_opcode_lookup.suggestName(\"c_opcode_lookup\")\n c_size_lookup.suggestName(\"c_size_lookup\")\n\n val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))\n val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))\n c_opcodes_set_interm.suggestName(\"c_opcodes_set_interm\")\n c_sizes_set_interm.suggestName(\"c_sizes_set_interm\")\n\n when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {\n c_set_wo_ready := UIntToOH(bundle.c.bits.source)\n }\n\n when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {\n c_set := UIntToOH(bundle.c.bits.source)\n c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U\n c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U\n c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)\n c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)\n monAssert(!inflight(bundle.c.bits.source), \"'C' channel re-used a source ID\" + extra)\n }\n\n val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData\n\n val d_clr = WireInit(0.U(edge.client.endSourceId.W))\n val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))\n val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))\n val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))\n d_clr.suggestName(\"d_clr\")\n d_clr_wo_ready.suggestName(\"d_clr_wo_ready\")\n d_opcodes_clr.suggestName(\"d_opcodes_clr\")\n d_sizes_clr.suggestName(\"d_sizes_clr\")\n\n val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck\n when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {\n d_clr_wo_ready := UIntToOH(bundle.d.bits.source)\n }\n\n when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {\n d_clr := UIntToOH(bundle.d.bits.source)\n d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)\n d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)\n }\n\n when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {\n val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)\n assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, \"'D' channel acknowledged for nothing inflight\" + extra)\n when (same_cycle_resp) {\n assume((bundle.d.bits.size === bundle.c.bits.size), \"'D' channel contains improper response size\" + extra)\n } .otherwise {\n assume((bundle.d.bits.size === c_size_lookup), \"'D' channel contains improper response size\" + extra)\n }\n }\n\n when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {\n assume((!bundle.d.ready) || bundle.c.ready, \"ready check\")\n }\n\n if (edge.manager.minLatency > 0) {\n when (c_set_wo_ready.orR) {\n assume(c_set_wo_ready =/= d_clr_wo_ready, s\"'C' and 'D' concurrent, despite minlatency > 0\" + extra)\n }\n }\n\n inflight := (inflight | c_set) & ~d_clr\n inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr\n inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr\n\n val watchdog = RegInit(0.U(32.W))\n val limit = PlusArg(\"tilelink_timeout\",\n docstring=\"Kill emulation after INT waiting TileLink cycles. Off if 0.\")\n monAssert (!inflight.orR || limit === 0.U || watchdog < limit, \"TileLink timeout expired\" + extra)\n\n watchdog := watchdog + 1.U\n when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }\n }\n\n def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {\n val inflight = RegInit(0.U(edge.manager.endSinkId.W))\n\n val d_first = edge.first(bundle.d.bits, bundle.d.fire)\n val e_first = true.B\n\n val d_set = WireInit(0.U(edge.manager.endSinkId.W))\n when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {\n d_set := UIntToOH(bundle.d.bits.sink)\n assume(!inflight(bundle.d.bits.sink), \"'D' channel re-used a sink ID\" + extra)\n }\n\n val e_clr = WireInit(0.U(edge.manager.endSinkId.W))\n when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {\n e_clr := UIntToOH(bundle.e.bits.sink)\n monAssert((d_set | inflight)(bundle.e.bits.sink), \"'E' channel acknowledged for nothing inflight\" + extra)\n }\n\n // edge.client.minLatency applies to BC, not DE\n\n inflight := (inflight | d_set) & ~e_clr\n }\n\n def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {\n val sourceBits = log2Ceil(edge.client.endSourceId)\n val tooBig = 14 // >16kB worth of flight information gets to be too much\n if (sourceBits > tooBig) {\n println(s\"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked\")\n } else {\n if (args.edge.params(TestplanTestType).simulation) {\n if (args.edge.params(TLMonitorStrictMode)) {\n legalizeADSource(bundle, edge)\n legalizeCDSource(bundle, edge)\n } else {\n legalizeADSourceOld(bundle, edge)\n }\n }\n if (args.edge.params(TestplanTestType).formal) {\n legalizeADSourceFormal(bundle, edge)\n }\n }\n if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {\n // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...\n val sinkBits = log2Ceil(edge.manager.endSinkId)\n if (sinkBits > tooBig) {\n println(s\"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked\")\n } else {\n legalizeDESink(bundle, edge)\n }\n }\n }\n\n def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {\n legalizeFormat (bundle, edge)\n legalizeMultibeat (bundle, edge)\n legalizeUnique (bundle, edge)\n }\n}\nFile PlusArg.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3._\nimport chisel3.experimental._\nimport chisel3.util.HasBlackBoxResource\n\n@deprecated(\"This will be removed in Rocket Chip 2020.08\", \"Rocket Chip 2020.05\")\ncase class PlusArgInfo(default: BigInt, docstring: String)\n\n/** Case class for PlusArg information\n *\n * @tparam A scala type of the PlusArg value\n * @param default optional default value\n * @param docstring text to include in the help\n * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)\n */\nprivate case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)\n\n/** Typeclass for converting a type to a doctype string\n * @tparam A some type\n */\ntrait Doctypeable[A] {\n\n /** Return the doctype string for some option */\n def toDoctype(a: Option[A]): String\n\n}\n\n/** Object containing implementations of the Doctypeable typeclass */\nobject Doctypes {\n\n /** Converts an Int => \"INT\" */\n implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = \"INT\" }\n\n /** Converts a BigInt => \"INT\" */\n implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = \"INT\" }\n\n /** Converts a String => \"STRING\" */\n implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = \"STRING\" }\n\n}\n\nclass plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(\n \"FORMAT\" -> StringParam(format),\n \"DEFAULT\" -> IntParam(default),\n \"WIDTH\" -> IntParam(width)\n )) with HasBlackBoxResource {\n val io = IO(new Bundle {\n val out = Output(UInt(width.W))\n })\n\n addResource(\"/vsrc/plusarg_reader.v\")\n}\n\n/* This wrapper class has no outputs, making it clear it is a simulation-only construct */\nclass PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {\n val io = IO(new Bundle {\n val count = Input(UInt(width.W))\n })\n val max = Module(new plusarg_reader(format, default, docstring, width)).io.out\n when (max > 0.U) {\n assert (io.count < max, s\"Timeout exceeded: $docstring\")\n }\n}\n\nimport Doctypes._\n\nobject PlusArg\n{\n /** PlusArg(\"foo\") will return 42.U if the simulation is run with +foo=42\n * Do not use this as an initial register value. The value is set in an\n * initial block and thus accessing it from another initial is racey.\n * Add a docstring to document the arg, which can be dumped in an elaboration\n * pass.\n */\n def apply(name: String, default: BigInt = 0, docstring: String = \"\", width: Int = 32): UInt = {\n PlusArgArtefacts.append(name, Some(default), docstring)\n Module(new plusarg_reader(name + \"=%d\", default, docstring, width)).io.out\n }\n\n /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert\n * to kill the simulation when count exceeds the specified integer argument.\n * Default 0 will never assert.\n */\n def timeout(name: String, default: BigInt = 0, docstring: String = \"\", width: Int = 32)(count: UInt): Unit = {\n PlusArgArtefacts.append(name, Some(default), docstring)\n Module(new PlusArgTimeout(name + \"=%d\", default, docstring, width)).io.count := count\n }\n}\n\nobject PlusArgArtefacts {\n private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty\n\n /* Add a new PlusArg */\n @deprecated(\n \"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08\",\n \"Rocket Chip 2020.05\"\n )\n def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)\n\n /** Add a new PlusArg\n *\n * @tparam A scala type of the PlusArg value\n * @param name name for the PlusArg\n * @param default optional default value\n * @param docstring text to include in the help\n */\n def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =\n artefacts = artefacts ++\n Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))\n\n /* From plus args, generate help text */\n private def serializeHelp_cHeader(tab: String = \"\"): String = artefacts\n .map{ case(arg, info) =>\n s\"\"\"|$tab+$arg=${info.doctype}\\\\n\\\\\n |$tab${\" \"*20}${info.docstring}\\\\n\\\\\n |\"\"\".stripMargin ++ info.default.map{ case default =>\n s\"$tab${\" \"*22}(default=${default})\\\\n\\\\\\n\"}.getOrElse(\"\")\n }.toSeq.mkString(\"\\\\n\\\\\\n\") ++ \"\\\"\"\n\n /* From plus args, generate a char array of their names */\n private def serializeArray_cHeader(tab: String = \"\"): String = {\n val prettyTab = tab + \" \" * 44 // Length of 'static const ...'\n s\"${tab}static const char * verilog_plusargs [] = {\\\\\\n\" ++\n artefacts\n .map{ case(arg, _) => s\"\"\"$prettyTab\"$arg\",\\\\\\n\"\"\" }\n .mkString(\"\")++\n s\"${prettyTab}0};\"\n }\n\n /* Generate C code to be included in emulator.cc that helps with\n * argument parsing based on available Verilog PlusArgs */\n def serialize_cHeader(): String =\n s\"\"\"|#define PLUSARG_USAGE_OPTIONS \\\"EMULATOR VERILOG PLUSARGS\\\\n\\\\\n |${serializeHelp_cHeader(\" \"*7)}\n |${serializeArray_cHeader()}\n |\"\"\".stripMargin\n}\nFile package.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip\n\nimport chisel3._\nimport chisel3.util._\nimport scala.math.min\nimport scala.collection.{immutable, mutable}\n\npackage object util {\n implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {\n def unzip = (x.map(_._1), x.map(_._2))\n }\n\n implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {\n def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR\n \n def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)\n }\n\n implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {\n\n /** Like Vec.apply(idx), but tolerates indices of mismatched width */\n def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))\n }\n\n implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {\n def apply(idx: UInt): T = {\n if (x.size <= 1) {\n x.head\n } else if (!isPow2(x.size)) {\n // For non-power-of-2 seqs, reflect elements to simplify decoder\n (x ++ x.takeRight(x.size & -x.size)).toSeq(idx)\n } else {\n // Ignore MSBs of idx\n val truncIdx =\n if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx\n else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)\n x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }\n }\n }\n\n def extract(idx: UInt): T = VecInit(x).extract(idx)\n\n def asUInt: UInt = Cat(x.map(_.asUInt).reverse)\n\n def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)\n\n def rotate(n: UInt): Seq[T] = {\n if (x.size <= 1) {\n x\n } else {\n require(isPow2(x.size))\n val amt = n.padTo(log2Ceil(x.size))\n (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })\n }\n }\n\n def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)\n\n def rotateRight(n: UInt): Seq[T] = {\n if (x.size <= 1) {\n x\n } else {\n require(isPow2(x.size))\n val amt = n.padTo(log2Ceil(x.size))\n (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })\n }\n }\n }\n\n // allow bitwise ops on Seq[Bool] just like UInt\n implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {\n def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }\n def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }\n def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }\n def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x\n def >> (n: Int): Seq[Bool] = x drop n\n def unary_~ : Seq[Bool] = x.map(!_)\n def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)\n def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)\n def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)\n\n private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)\n }\n\n implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {\n def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))\n\n def getElements: Seq[Element] = x match {\n case e: Element => Seq(e)\n case a: Aggregate => a.getElements.flatMap(_.getElements)\n }\n }\n\n /** Any Data subtype that has a Bool member named valid. */\n type DataCanBeValid = Data { val valid: Bool }\n\n implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {\n def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)\n }\n\n implicit class StringToAugmentedString(private val x: String) extends AnyVal {\n /** converts from camel case to to underscores, also removing all spaces */\n def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + \"\") getOrElse \"\") {\n case (acc, c) if c.isUpper => acc + \"_\" + c.toLower\n case (acc, c) if c == ' ' => acc\n case (acc, c) => acc + c\n }\n\n /** converts spaces or underscores to hyphens, also lowering case */\n def kebab: String = x.toLowerCase map {\n case ' ' => '-'\n case '_' => '-'\n case c => c\n }\n\n def named(name: Option[String]): String = {\n x + name.map(\"_named_\" + _ ).getOrElse(\"_with_no_name\")\n }\n\n def named(name: String): String = named(Some(name))\n }\n\n implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)\n implicit def wcToUInt(c: WideCounter): UInt = c.value\n\n implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {\n def sextTo(n: Int): UInt = {\n require(x.getWidth <= n)\n if (x.getWidth == n) x\n else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)\n }\n\n def padTo(n: Int): UInt = {\n require(x.getWidth <= n)\n if (x.getWidth == n) x\n else Cat(0.U((n - x.getWidth).W), x)\n }\n\n // shifts left by n if n >= 0, or right by -n if n < 0\n def << (n: SInt): UInt = {\n val w = n.getWidth - 1\n require(w <= 30)\n\n val shifted = x << n(w-1, 0)\n Mux(n(w), shifted >> (1 << w), shifted)\n }\n\n // shifts right by n if n >= 0, or left by -n if n < 0\n def >> (n: SInt): UInt = {\n val w = n.getWidth - 1\n require(w <= 30)\n\n val shifted = x << (1 << w) >> n(w-1, 0)\n Mux(n(w), shifted, shifted >> (1 << w))\n }\n\n // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts\n def extract(hi: Int, lo: Int): UInt = {\n require(hi >= lo-1)\n if (hi == lo-1) 0.U\n else x(hi, lo)\n }\n\n // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts\n def extractOption(hi: Int, lo: Int): Option[UInt] = {\n require(hi >= lo-1)\n if (hi == lo-1) None\n else Some(x(hi, lo))\n }\n\n // like x & ~y, but first truncate or zero-extend y to x's width\n def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))\n\n def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)\n\n def rotateRight(n: UInt): UInt = {\n if (x.getWidth <= 1) {\n x\n } else {\n val amt = n.padTo(log2Ceil(x.getWidth))\n (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))\n }\n }\n\n def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))\n\n def rotateLeft(n: UInt): UInt = {\n if (x.getWidth <= 1) {\n x\n } else {\n val amt = n.padTo(log2Ceil(x.getWidth))\n (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))\n }\n }\n\n // compute (this + y) % n, given (this < n) and (y < n)\n def addWrap(y: UInt, n: Int): UInt = {\n val z = x +& y\n if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)\n }\n\n // compute (this - y) % n, given (this < n) and (y < n)\n def subWrap(y: UInt, n: Int): UInt = {\n val z = x -& y\n if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)\n }\n\n def grouped(width: Int): Seq[UInt] =\n (0 until x.getWidth by width).map(base => x(base + width - 1, base))\n\n def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds\n\n def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)\n\n // Like >=, but prevents x-prop for ('x >= 0)\n def >== (y: UInt): Bool = x >= y || y === 0.U\n }\n\n implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {\n def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)\n def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)\n }\n\n implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {\n def toInt: Int = if (x) 1 else 0\n\n // this one's snagged from scalaz\n def option[T](z: => T): Option[T] = if (x) Some(z) else None\n }\n\n implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {\n // exact log2\n def log2: Int = {\n require(isPow2(x))\n log2Ceil(x)\n }\n }\n\n def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)\n def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))\n def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)\n def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)\n\n def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None\n\n // Fill 1s from low bits to high bits\n def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)\n def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {\n val stop = min(width, cap)\n def helper(s: Int, x: UInt): UInt =\n if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))\n helper(1, x)(width-1, 0)\n }\n\n // Fill 1s form high bits to low bits\n def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)\n def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {\n val stop = min(width, cap)\n def helper(s: Int, x: UInt): UInt =\n if (s >= stop) x else helper(s+s, x | (x >> s))\n helper(1, x)(width-1, 0)\n }\n\n def OptimizationBarrier[T <: Data](in: T): T = {\n val barrier = Module(new Module {\n val io = IO(new Bundle {\n val x = Input(chiselTypeOf(in))\n val y = Output(chiselTypeOf(in))\n })\n io.y := io.x\n override def desiredName = s\"OptimizationBarrier_${in.typeName}\"\n })\n barrier.io.x := in\n barrier.io.y\n }\n\n /** Similar to Seq.groupBy except this returns a Seq instead of a Map\n * Useful for deterministic code generation\n */\n def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {\n val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]\n for (x <- xs) {\n val key = f(x)\n val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])\n l += x\n }\n map.view.map({ case (k, vs) => k -> vs.toList }).toList\n }\n\n def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {\n case 1 => List.fill(n)(in.head)\n case x if x == n => in\n case _ => throw new Exception(s\"must provide exactly 1 or $n of some field, but got:\\n$in\")\n }\n\n // HeterogeneousBag moved to standalond diplomacy\n @deprecated(\"HeterogeneousBag has been absorbed into standalone diplomacy library\", \"rocketchip 2.0.0\")\n def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)\n @deprecated(\"HeterogeneousBag has been absorbed into standalone diplomacy library\", \"rocketchip 2.0.0\")\n val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag\n}\nFile Parameters.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.diplomacy\n\nimport chisel3._\nimport chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}\nimport freechips.rocketchip.util.ShiftQueue\n\n/** Options for describing the attributes of memory regions */\nobject RegionType {\n // Define the 'more relaxed than' ordering\n val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)\n sealed trait T extends Ordered[T] {\n def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)\n }\n\n case object CACHED extends T // an intermediate agent may have cached a copy of the region for you\n case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided\n case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible\n case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached\n case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects\n case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed\n case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively\n}\n\n// A non-empty half-open range; [start, end)\ncase class IdRange(start: Int, end: Int) extends Ordered[IdRange]\n{\n require (start >= 0, s\"Ids cannot be negative, but got: $start.\")\n require (start <= end, \"Id ranges cannot be negative.\")\n\n def compare(x: IdRange) = {\n val primary = (this.start - x.start).signum\n val secondary = (x.end - this.end).signum\n if (primary != 0) primary else secondary\n }\n\n def overlaps(x: IdRange) = start < x.end && x.start < end\n def contains(x: IdRange) = start <= x.start && x.end <= end\n\n def contains(x: Int) = start <= x && x < end\n def contains(x: UInt) =\n if (size == 0) {\n false.B\n } else if (size == 1) { // simple comparison\n x === start.U\n } else {\n // find index of largest different bit\n val largestDeltaBit = log2Floor(start ^ (end-1))\n val smallestCommonBit = largestDeltaBit + 1 // may not exist in x\n val uncommonMask = (1 << smallestCommonBit) - 1\n val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)\n // the prefix must match exactly (note: may shift ALL bits away)\n (x >> smallestCommonBit) === (start >> smallestCommonBit).U &&\n // firrtl constant prop range analysis can eliminate these two:\n (start & uncommonMask).U <= uncommonBits &&\n uncommonBits <= ((end-1) & uncommonMask).U\n }\n\n def shift(x: Int) = IdRange(start+x, end+x)\n def size = end - start\n def isEmpty = end == start\n\n def range = start until end\n}\n\nobject IdRange\n{\n def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {\n val ranges = s.sorted\n (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }\n }\n}\n\n// An potentially empty inclusive range of 2-powers [min, max] (in bytes)\ncase class TransferSizes(min: Int, max: Int)\n{\n def this(x: Int) = this(x, x)\n\n require (min <= max, s\"Min transfer $min > max transfer $max\")\n require (min >= 0 && max >= 0, s\"TransferSizes must be positive, got: ($min, $max)\")\n require (max == 0 || isPow2(max), s\"TransferSizes must be a power of 2, got: $max\")\n require (min == 0 || isPow2(min), s\"TransferSizes must be a power of 2, got: $min\")\n require (max == 0 || min != 0, s\"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)\")\n\n def none = min == 0\n def contains(x: Int) = isPow2(x) && min <= x && x <= max\n def containsLg(x: Int) = contains(1 << x)\n def containsLg(x: UInt) =\n if (none) false.B\n else if (min == max) { log2Ceil(min).U === x }\n else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }\n\n def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)\n\n def intersect(x: TransferSizes) =\n if (x.max < min || max < x.min) TransferSizes.none\n else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))\n\n // Not a union, because the result may contain sizes contained by neither term\n // NOT TO BE CONFUSED WITH COVERPOINTS\n def mincover(x: TransferSizes) = {\n if (none) {\n x\n } else if (x.none) {\n this\n } else {\n TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))\n }\n }\n\n override def toString() = \"TransferSizes[%d, %d]\".format(min, max)\n}\n\nobject TransferSizes {\n def apply(x: Int) = new TransferSizes(x)\n val none = new TransferSizes(0)\n\n def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)\n def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)\n\n implicit def asBool(x: TransferSizes) = !x.none\n}\n\n// AddressSets specify the address space managed by the manager\n// Base is the base address, and mask are the bits consumed by the manager\n// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff\n// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...\ncase class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]\n{\n // Forbid misaligned base address (and empty sets)\n require ((base & mask) == 0, s\"Mis-aligned AddressSets are forbidden, got: ${this.toString}\")\n require (base >= 0, s\"AddressSet negative base is ambiguous: $base\") // TL2 address widths are not fixed => negative is ambiguous\n // We do allow negative mask (=> ignore all high bits)\n\n def contains(x: BigInt) = ((x ^ base) & ~mask) == 0\n def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S\n\n // turn x into an address contained in this set\n def legalize(x: UInt): UInt = base.U | (mask.U & x)\n\n // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)\n def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0\n // contains iff bitwise: x.mask => mask && contains(x.base)\n def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0\n\n // The number of bytes to which the manager must be aligned\n def alignment = ((mask + 1) & ~mask)\n // Is this a contiguous memory range\n def contiguous = alignment == mask+1\n\n def finite = mask >= 0\n def max = { require (finite, \"Max cannot be calculated on infinite mask\"); base | mask }\n\n // Widen the match function to ignore all bits in imask\n def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)\n\n // Return an AddressSet that only contains the addresses both sets contain\n def intersect(x: AddressSet): Option[AddressSet] = {\n if (!overlaps(x)) {\n None\n } else {\n val r_mask = mask & x.mask\n val r_base = base | x.base\n Some(AddressSet(r_base, r_mask))\n }\n }\n\n def subtract(x: AddressSet): Seq[AddressSet] = {\n intersect(x) match {\n case None => Seq(this)\n case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>\n val nmask = (mask & (bit-1)) | remove.mask\n val nbase = (remove.base ^ bit) & ~nmask\n AddressSet(nbase, nmask)\n }\n }\n }\n\n // AddressSets have one natural Ordering (the containment order, if contiguous)\n def compare(x: AddressSet) = {\n val primary = (this.base - x.base).signum // smallest address first\n val secondary = (x.mask - this.mask).signum // largest mask first\n if (primary != 0) primary else secondary\n }\n\n // We always want to see things in hex\n override def toString() = {\n if (mask >= 0) {\n \"AddressSet(0x%x, 0x%x)\".format(base, mask)\n } else {\n \"AddressSet(0x%x, ~0x%x)\".format(base, ~mask)\n }\n }\n\n def toRanges = {\n require (finite, \"Ranges cannot be calculated on infinite mask\")\n val size = alignment\n val fragments = mask & ~(size-1)\n val bits = bitIndexes(fragments)\n (BigInt(0) until (BigInt(1) << bits.size)).map { i =>\n val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }\n AddressRange(off, size)\n }\n }\n}\n\nobject AddressSet\n{\n val everything = AddressSet(0, -1)\n def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {\n if (size == 0) tail.reverse else {\n val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)\n val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size\n val step =\n if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)\n maxSizeAlignment else maxBaseAlignment\n misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)\n }\n }\n\n def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {\n // Pair terms up by ignoring 'bit'\n seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>\n if (seq.size == 1) {\n seq.head // singleton -> unaffected\n } else {\n key.copy(mask = key.mask | bit) // pair - widen mask by bit\n }\n }.toList\n }\n\n def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {\n val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)\n AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted\n }\n\n def enumerateMask(mask: BigInt): Seq[BigInt] = {\n def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =\n if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)\n helper(0, Nil)\n }\n\n def enumerateBits(mask: BigInt): Seq[BigInt] = {\n def helper(x: BigInt): Seq[BigInt] = {\n if (x == 0) {\n Nil\n } else {\n val bit = x & (-x)\n bit +: helper(x & ~bit)\n }\n }\n helper(mask)\n }\n}\n\ncase class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)\n{\n require (depth >= 0, \"Buffer depth must be >= 0\")\n def isDefined = depth > 0\n def latency = if (isDefined && !flow) 1 else 0\n\n def apply[T <: Data](x: DecoupledIO[T]) =\n if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)\n else x\n\n def irrevocable[T <: Data](x: ReadyValidIO[T]) =\n if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)\n else x\n\n def sq[T <: Data](x: DecoupledIO[T]) =\n if (!isDefined) x else {\n val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))\n sq.io.enq <> x\n sq.io.deq\n }\n\n override def toString() = \"BufferParams:%d%s%s\".format(depth, if (flow) \"F\" else \"\", if (pipe) \"P\" else \"\")\n\n}\n\nobject BufferParams\n{\n implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)\n\n val default = BufferParams(2)\n val none = BufferParams(0)\n val flow = BufferParams(1, true, false)\n val pipe = BufferParams(1, false, true)\n}\n\ncase class TriStateValue(value: Boolean, set: Boolean)\n{\n def update(orig: Boolean) = if (set) value else orig\n}\n\nobject TriStateValue\n{\n implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)\n def unset = TriStateValue(false, false)\n}\n\ntrait DirectedBuffers[T] {\n def copyIn(x: BufferParams): T\n def copyOut(x: BufferParams): T\n def copyInOut(x: BufferParams): T\n}\n\ntrait IdMapEntry {\n def name: String\n def from: IdRange\n def to: IdRange\n def isCache: Boolean\n def requestFifo: Boolean\n def maxTransactionsInFlight: Option[Int]\n def pretty(fmt: String) =\n if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5\n fmt.format(to.start, to.end, from.start, from.end, s\"\"\"\"$name\"\"\"\", if (isCache) \" [CACHE]\" else \"\", if (requestFifo) \" [FIFO]\" else \"\")\n } else {\n fmt.format(from.start, from.end, s\"\"\"\"$name\"\"\"\", if (isCache) \" [CACHE]\" else \"\", if (requestFifo) \" [FIFO]\" else \"\")\n }\n}\n\nabstract class IdMap[T <: IdMapEntry] {\n protected val fmt: String\n val mapping: Seq[T]\n def pretty: String = mapping.map(_.pretty(fmt)).mkString(\",\\n\")\n}\nFile Edges.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.tilelink\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.experimental.SourceInfo\nimport org.chipsalliance.cde.config.Parameters\nimport freechips.rocketchip.util._\n\nclass TLEdge(\n client: TLClientPortParameters,\n manager: TLManagerPortParameters,\n params: Parameters,\n sourceInfo: SourceInfo)\n extends TLEdgeParameters(client, manager, params, sourceInfo)\n{\n def isAligned(address: UInt, lgSize: UInt): Bool = {\n if (maxLgSize == 0) true.B else {\n val mask = UIntToOH1(lgSize, maxLgSize)\n (address & mask) === 0.U\n }\n }\n\n def mask(address: UInt, lgSize: UInt): UInt =\n MaskGen(address, lgSize, manager.beatBytes)\n\n def staticHasData(bundle: TLChannel): Option[Boolean] = {\n bundle match {\n case _:TLBundleA => {\n // Do there exist A messages with Data?\n val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial\n // Do there exist A messages without Data?\n val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint\n // Statically optimize the case where hasData is a constant\n if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None\n }\n case _:TLBundleB => {\n // Do there exist B messages with Data?\n val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial\n // Do there exist B messages without Data?\n val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint\n // Statically optimize the case where hasData is a constant\n if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None\n }\n case _:TLBundleC => {\n // Do there eixst C messages with Data?\n val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe\n // Do there exist C messages without Data?\n val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe\n if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None\n }\n case _:TLBundleD => {\n // Do there eixst D messages with Data?\n val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB\n // Do there exist D messages without Data?\n val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT\n if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None\n }\n case _:TLBundleE => Some(false)\n }\n }\n\n def isRequest(x: TLChannel): Bool = {\n x match {\n case a: TLBundleA => true.B\n case b: TLBundleB => true.B\n case c: TLBundleC => c.opcode(2) && c.opcode(1)\n // opcode === TLMessages.Release ||\n // opcode === TLMessages.ReleaseData\n case d: TLBundleD => d.opcode(2) && !d.opcode(1)\n // opcode === TLMessages.Grant ||\n // opcode === TLMessages.GrantData\n case e: TLBundleE => false.B\n }\n }\n\n def isResponse(x: TLChannel): Bool = {\n x match {\n case a: TLBundleA => false.B\n case b: TLBundleB => false.B\n case c: TLBundleC => !c.opcode(2) || !c.opcode(1)\n // opcode =/= TLMessages.Release &&\n // opcode =/= TLMessages.ReleaseData\n case d: TLBundleD => true.B // Grant isResponse + isRequest\n case e: TLBundleE => true.B\n }\n }\n\n def hasData(x: TLChannel): Bool = {\n val opdata = x match {\n case a: TLBundleA => !a.opcode(2)\n // opcode === TLMessages.PutFullData ||\n // opcode === TLMessages.PutPartialData ||\n // opcode === TLMessages.ArithmeticData ||\n // opcode === TLMessages.LogicalData\n case b: TLBundleB => !b.opcode(2)\n // opcode === TLMessages.PutFullData ||\n // opcode === TLMessages.PutPartialData ||\n // opcode === TLMessages.ArithmeticData ||\n // opcode === TLMessages.LogicalData\n case c: TLBundleC => c.opcode(0)\n // opcode === TLMessages.AccessAckData ||\n // opcode === TLMessages.ProbeAckData ||\n // opcode === TLMessages.ReleaseData\n case d: TLBundleD => d.opcode(0)\n // opcode === TLMessages.AccessAckData ||\n // opcode === TLMessages.GrantData\n case e: TLBundleE => false.B\n }\n staticHasData(x).map(_.B).getOrElse(opdata)\n }\n\n def opcode(x: TLDataChannel): UInt = {\n x match {\n case a: TLBundleA => a.opcode\n case b: TLBundleB => b.opcode\n case c: TLBundleC => c.opcode\n case d: TLBundleD => d.opcode\n }\n }\n\n def param(x: TLDataChannel): UInt = {\n x match {\n case a: TLBundleA => a.param\n case b: TLBundleB => b.param\n case c: TLBundleC => c.param\n case d: TLBundleD => d.param\n }\n }\n\n def size(x: TLDataChannel): UInt = {\n x match {\n case a: TLBundleA => a.size\n case b: TLBundleB => b.size\n case c: TLBundleC => c.size\n case d: TLBundleD => d.size\n }\n }\n\n def data(x: TLDataChannel): UInt = {\n x match {\n case a: TLBundleA => a.data\n case b: TLBundleB => b.data\n case c: TLBundleC => c.data\n case d: TLBundleD => d.data\n }\n }\n\n def corrupt(x: TLDataChannel): Bool = {\n x match {\n case a: TLBundleA => a.corrupt\n case b: TLBundleB => b.corrupt\n case c: TLBundleC => c.corrupt\n case d: TLBundleD => d.corrupt\n }\n }\n\n def mask(x: TLAddrChannel): UInt = {\n x match {\n case a: TLBundleA => a.mask\n case b: TLBundleB => b.mask\n case c: TLBundleC => mask(c.address, c.size)\n }\n }\n\n def full_mask(x: TLAddrChannel): UInt = {\n x match {\n case a: TLBundleA => mask(a.address, a.size)\n case b: TLBundleB => mask(b.address, b.size)\n case c: TLBundleC => mask(c.address, c.size)\n }\n }\n\n def address(x: TLAddrChannel): UInt = {\n x match {\n case a: TLBundleA => a.address\n case b: TLBundleB => b.address\n case c: TLBundleC => c.address\n }\n }\n\n def source(x: TLDataChannel): UInt = {\n x match {\n case a: TLBundleA => a.source\n case b: TLBundleB => b.source\n case c: TLBundleC => c.source\n case d: TLBundleD => d.source\n }\n }\n\n def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)\n def addr_lo(x: UInt): UInt =\n if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)\n\n def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))\n def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))\n\n def numBeats(x: TLChannel): UInt = {\n x match {\n case _: TLBundleE => 1.U\n case bundle: TLDataChannel => {\n val hasData = this.hasData(bundle)\n val size = this.size(bundle)\n val cutoff = log2Ceil(manager.beatBytes)\n val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U\n val decode = UIntToOH(size, maxLgSize+1) >> cutoff\n Mux(hasData, decode | small.asUInt, 1.U)\n }\n }\n }\n\n def numBeats1(x: TLChannel): UInt = {\n x match {\n case _: TLBundleE => 0.U\n case bundle: TLDataChannel => {\n if (maxLgSize == 0) {\n 0.U\n } else {\n val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)\n Mux(hasData(bundle), decode, 0.U)\n }\n }\n }\n }\n\n def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {\n val beats1 = numBeats1(bits)\n val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))\n val counter1 = counter - 1.U\n val first = counter === 0.U\n val last = counter === 1.U || beats1 === 0.U\n val done = last && fire\n val count = (beats1 & ~counter1)\n when (fire) {\n counter := Mux(first, beats1, counter1)\n }\n (first, last, done, count)\n }\n\n def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1\n def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)\n def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)\n\n def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2\n def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)\n def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)\n\n def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3\n def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)\n def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)\n\n def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {\n val r = firstlastHelper(bits, fire)\n (r._1, r._2, r._3)\n }\n def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)\n def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)\n\n def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {\n val r = firstlastHelper(bits, fire)\n (r._1, r._2, r._3, r._4)\n }\n def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)\n def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)\n\n def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {\n val r = firstlastHelper(bits, fire)\n (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))\n }\n def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)\n def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)\n\n // Does the request need T permissions to be executed?\n def needT(a: TLBundleA): Bool = {\n val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(\n TLPermissions.NtoB -> false.B,\n TLPermissions.NtoT -> true.B,\n TLPermissions.BtoT -> true.B))\n MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(\n TLMessages.PutFullData -> true.B,\n TLMessages.PutPartialData -> true.B,\n TLMessages.ArithmeticData -> true.B,\n TLMessages.LogicalData -> true.B,\n TLMessages.Get -> false.B,\n TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(\n TLHints.PREFETCH_READ -> false.B,\n TLHints.PREFETCH_WRITE -> true.B)),\n TLMessages.AcquireBlock -> acq_needT,\n TLMessages.AcquirePerm -> acq_needT))\n }\n\n // This is a very expensive circuit; use only if you really mean it!\n def inFlight(x: TLBundle): (UInt, UInt) = {\n val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))\n val bce = manager.anySupportAcquireB && client.anySupportProbe\n\n val (a_first, a_last, _) = firstlast(x.a)\n val (b_first, b_last, _) = firstlast(x.b)\n val (c_first, c_last, _) = firstlast(x.c)\n val (d_first, d_last, _) = firstlast(x.d)\n val (e_first, e_last, _) = firstlast(x.e)\n\n val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))\n val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))\n val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))\n val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))\n val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))\n\n val a_inc = x.a.fire && a_first && a_request\n val b_inc = x.b.fire && b_first && b_request\n val c_inc = x.c.fire && c_first && c_request\n val d_inc = x.d.fire && d_first && d_request\n val e_inc = x.e.fire && e_first && e_request\n val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))\n\n val a_dec = x.a.fire && a_last && a_response\n val b_dec = x.b.fire && b_last && b_response\n val c_dec = x.c.fire && c_last && c_response\n val d_dec = x.d.fire && d_last && d_response\n val e_dec = x.e.fire && e_last && e_response\n val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))\n\n val next_flight = flight + PopCount(inc) - PopCount(dec)\n flight := next_flight\n\n (flight, next_flight)\n }\n\n def prettySourceMapping(context: String): String = {\n s\"TL-Source mapping for $context:\\n${(new TLSourceIdMap(client)).pretty}\\n\"\n }\n}\n\nclass TLEdgeOut(\n client: TLClientPortParameters,\n manager: TLManagerPortParameters,\n params: Parameters,\n sourceInfo: SourceInfo)\n extends TLEdge(client, manager, params, sourceInfo)\n{\n // Transfers\n def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {\n require (manager.anySupportAcquireB, s\"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsAcquireBFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.AcquireBlock\n a.param := growPermissions\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := DontCare\n a.corrupt := false.B\n (legal, a)\n }\n\n def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {\n require (manager.anySupportAcquireB, s\"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsAcquireBFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.AcquirePerm\n a.param := growPermissions\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := DontCare\n a.corrupt := false.B\n (legal, a)\n }\n\n def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {\n require (manager.anySupportAcquireB, s\"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsAcquireBFast(toAddress, lgSize)\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.Release\n c.param := shrinkPermissions\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := DontCare\n c.corrupt := false.B\n (legal, c)\n }\n\n def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {\n require (manager.anySupportAcquireB, s\"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsAcquireBFast(toAddress, lgSize)\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.ReleaseData\n c.param := shrinkPermissions\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := data\n c.corrupt := corrupt\n (legal, c)\n }\n\n def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =\n Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)\n\n def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =\n ProbeAck(b.source, b.address, b.size, reportPermissions)\n\n def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.ProbeAck\n c.param := reportPermissions\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := DontCare\n c.corrupt := false.B\n c\n }\n\n def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =\n ProbeAck(b.source, b.address, b.size, reportPermissions, data)\n\n def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.ProbeAckData\n c.param := reportPermissions\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := data\n c.corrupt := corrupt\n c\n }\n\n def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =\n ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)\n\n def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)\n def GrantAck(toSink: UInt): TLBundleE = {\n val e = Wire(new TLBundleE(bundle))\n e.sink := toSink\n e\n }\n\n // Accesses\n def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {\n require (manager.anySupportGet, s\"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsGetFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.Get\n a.param := 0.U\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := DontCare\n a.corrupt := false.B\n (legal, a)\n }\n\n def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =\n Put(fromSource, toAddress, lgSize, data, false.B)\n\n def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {\n require (manager.anySupportPutFull, s\"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsPutFullFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.PutFullData\n a.param := 0.U\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := data\n a.corrupt := corrupt\n (legal, a)\n }\n\n def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =\n Put(fromSource, toAddress, lgSize, data, mask, false.B)\n\n def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {\n require (manager.anySupportPutPartial, s\"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsPutPartialFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.PutPartialData\n a.param := 0.U\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask\n a.data := data\n a.corrupt := corrupt\n (legal, a)\n }\n\n def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {\n require (manager.anySupportArithmetic, s\"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsArithmeticFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.ArithmeticData\n a.param := atomic\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := data\n a.corrupt := corrupt\n (legal, a)\n }\n\n def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {\n require (manager.anySupportLogical, s\"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsLogicalFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.LogicalData\n a.param := atomic\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := data\n a.corrupt := corrupt\n (legal, a)\n }\n\n def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {\n require (manager.anySupportHint, s\"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsHintFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.Hint\n a.param := param\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := DontCare\n a.corrupt := false.B\n (legal, a)\n }\n\n def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)\n def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.AccessAck\n c.param := 0.U\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := DontCare\n c.corrupt := false.B\n c\n }\n\n def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)\n def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)\n def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)\n def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.AccessAckData\n c.param := 0.U\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := data\n c.corrupt := corrupt\n c\n }\n\n def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)\n def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.HintAck\n c.param := 0.U\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := DontCare\n c.corrupt := false.B\n c\n }\n}\n\nclass TLEdgeIn(\n client: TLClientPortParameters,\n manager: TLManagerPortParameters,\n params: Parameters,\n sourceInfo: SourceInfo)\n extends TLEdge(client, manager, params, sourceInfo)\n{\n private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {\n val todo = x.filter(!_.isEmpty)\n val heads = todo.map(_.head)\n val tails = todo.map(_.tail)\n if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }\n }\n\n // Transfers\n def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {\n require (client.anySupportProbe, s\"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}\")\n val legal = client.supportsProbe(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.Probe\n b.param := capPermissions\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask(fromAddress, lgSize)\n b.data := DontCare\n b.corrupt := false.B\n (legal, b)\n }\n\n def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)\n def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {\n val d = Wire(new TLBundleD(bundle))\n d.opcode := TLMessages.Grant\n d.param := capPermissions\n d.size := lgSize\n d.source := toSource\n d.sink := fromSink\n d.denied := denied\n d.user := DontCare\n d.echo := DontCare\n d.data := DontCare\n d.corrupt := false.B\n d\n }\n\n def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)\n def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {\n val d = Wire(new TLBundleD(bundle))\n d.opcode := TLMessages.GrantData\n d.param := capPermissions\n d.size := lgSize\n d.source := toSource\n d.sink := fromSink\n d.denied := denied\n d.user := DontCare\n d.echo := DontCare\n d.data := data\n d.corrupt := corrupt\n d\n }\n\n def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)\n def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {\n val d = Wire(new TLBundleD(bundle))\n d.opcode := TLMessages.ReleaseAck\n d.param := 0.U\n d.size := lgSize\n d.source := toSource\n d.sink := 0.U\n d.denied := denied\n d.user := DontCare\n d.echo := DontCare\n d.data := DontCare\n d.corrupt := false.B\n d\n }\n\n // Accesses\n def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {\n require (client.anySupportGet, s\"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}\")\n val legal = client.supportsGet(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.Get\n b.param := 0.U\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask(fromAddress, lgSize)\n b.data := DontCare\n b.corrupt := false.B\n (legal, b)\n }\n\n def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =\n Put(fromAddress, toSource, lgSize, data, false.B)\n\n def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {\n require (client.anySupportPutFull, s\"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}\")\n val legal = client.supportsPutFull(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.PutFullData\n b.param := 0.U\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask(fromAddress, lgSize)\n b.data := data\n b.corrupt := corrupt\n (legal, b)\n }\n\n def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =\n Put(fromAddress, toSource, lgSize, data, mask, false.B)\n\n def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {\n require (client.anySupportPutPartial, s\"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}\")\n val legal = client.supportsPutPartial(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.PutPartialData\n b.param := 0.U\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask\n b.data := data\n b.corrupt := corrupt\n (legal, b)\n }\n\n def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {\n require (client.anySupportArithmetic, s\"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}\")\n val legal = client.supportsArithmetic(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.ArithmeticData\n b.param := atomic\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask(fromAddress, lgSize)\n b.data := data\n b.corrupt := corrupt\n (legal, b)\n }\n\n def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {\n require (client.anySupportLogical, s\"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}\")\n val legal = client.supportsLogical(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.LogicalData\n b.param := atomic\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask(fromAddress, lgSize)\n b.data := data\n b.corrupt := corrupt\n (legal, b)\n }\n\n def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {\n require (client.anySupportHint, s\"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}\")\n val legal = client.supportsHint(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.Hint\n b.param := param\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask(fromAddress, lgSize)\n b.data := DontCare\n b.corrupt := false.B\n (legal, b)\n }\n\n def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)\n def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)\n def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)\n def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {\n val d = Wire(new TLBundleD(bundle))\n d.opcode := TLMessages.AccessAck\n d.param := 0.U\n d.size := lgSize\n d.source := toSource\n d.sink := 0.U\n d.denied := denied\n d.user := DontCare\n d.echo := DontCare\n d.data := DontCare\n d.corrupt := false.B\n d\n }\n\n def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)\n def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)\n def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)\n def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {\n val d = Wire(new TLBundleD(bundle))\n d.opcode := TLMessages.AccessAckData\n d.param := 0.U\n d.size := lgSize\n d.source := toSource\n d.sink := 0.U\n d.denied := denied\n d.user := DontCare\n d.echo := DontCare\n d.data := data\n d.corrupt := corrupt\n d\n }\n\n def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)\n def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)\n def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)\n def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {\n val d = Wire(new TLBundleD(bundle))\n d.opcode := TLMessages.HintAck\n d.param := 0.U\n d.size := lgSize\n d.source := toSource\n d.sink := 0.U\n d.denied := denied\n d.user := DontCare\n d.echo := DontCare\n d.data := DontCare\n d.corrupt := false.B\n d\n }\n}\n"},"response":{"kind":"string","value":"module TLMonitor_42(\t// @[Monitor.scala:36:7]\n input clock,\t// @[Monitor.scala:36:7]\n input reset,\t// @[Monitor.scala:36:7]\n input io_in_a_ready,\t// @[Monitor.scala:20:14]\n input io_in_a_valid,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_a_bits_opcode,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_a_bits_param,\t// @[Monitor.scala:20:14]\n input [3:0] io_in_a_bits_size,\t// @[Monitor.scala:20:14]\n input [1:0] io_in_a_bits_source,\t// @[Monitor.scala:20:14]\n input [31:0] io_in_a_bits_address,\t// @[Monitor.scala:20:14]\n input [7:0] io_in_a_bits_mask,\t// @[Monitor.scala:20:14]\n input io_in_b_ready,\t// @[Monitor.scala:20:14]\n input io_in_b_valid,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_b_bits_opcode,\t// @[Monitor.scala:20:14]\n input [1:0] io_in_b_bits_param,\t// @[Monitor.scala:20:14]\n input [3:0] io_in_b_bits_size,\t// @[Monitor.scala:20:14]\n input [1:0] io_in_b_bits_source,\t// @[Monitor.scala:20:14]\n input [31:0] io_in_b_bits_address,\t// @[Monitor.scala:20:14]\n input [7:0] io_in_b_bits_mask,\t// @[Monitor.scala:20:14]\n input io_in_b_bits_corrupt,\t// @[Monitor.scala:20:14]\n input io_in_c_ready,\t// @[Monitor.scala:20:14]\n input io_in_c_valid,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_c_bits_opcode,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_c_bits_param,\t// @[Monitor.scala:20:14]\n input [3:0] io_in_c_bits_size,\t// @[Monitor.scala:20:14]\n input [1:0] io_in_c_bits_source,\t// @[Monitor.scala:20:14]\n input [31:0] io_in_c_bits_address,\t// @[Monitor.scala:20:14]\n input io_in_d_ready,\t// @[Monitor.scala:20:14]\n input io_in_d_valid,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_d_bits_opcode,\t// @[Monitor.scala:20:14]\n input [1:0] io_in_d_bits_param,\t// @[Monitor.scala:20:14]\n input [3:0] io_in_d_bits_size,\t// @[Monitor.scala:20:14]\n input [1:0] io_in_d_bits_source,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_d_bits_sink,\t// @[Monitor.scala:20:14]\n input io_in_d_bits_denied,\t// @[Monitor.scala:20:14]\n input io_in_d_bits_corrupt,\t// @[Monitor.scala:20:14]\n input io_in_e_ready,\t// @[Monitor.scala:20:14]\n input io_in_e_valid,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_e_bits_sink\t// @[Monitor.scala:20:14]\n);\n\n wire [31:0] _plusarg_reader_1_out;\t// @[PlusArg.scala:80:11]\n wire [31:0] _plusarg_reader_out;\t// @[PlusArg.scala:80:11]\n wire [26:0] _GEN = {23'h0, io_in_a_bits_size};\t// @[package.scala:243:71]\n wire [26:0] _GEN_0 = {23'h0, io_in_c_bits_size};\t// @[package.scala:243:71]\n wire _a_first_T_1 = io_in_a_ready & io_in_a_valid;\t// @[Decoupled.scala:51:35]\n reg [8:0] a_first_counter;\t// @[Edges.scala:229:27]\n reg [2:0] opcode;\t// @[Monitor.scala:387:22]\n reg [2:0] param;\t// @[Monitor.scala:388:22]\n reg [3:0] size;\t// @[Monitor.scala:389:22]\n reg [1:0] source;\t// @[Monitor.scala:390:22]\n reg [31:0] address;\t// @[Monitor.scala:391:22]\n wire _d_first_T_3 = io_in_d_ready & io_in_d_valid;\t// @[Decoupled.scala:51:35]\n reg [8:0] d_first_counter;\t// @[Edges.scala:229:27]\n reg [2:0] opcode_1;\t// @[Monitor.scala:538:22]\n reg [1:0] param_1;\t// @[Monitor.scala:539:22]\n reg [3:0] size_1;\t// @[Monitor.scala:540:22]\n reg [1:0] source_1;\t// @[Monitor.scala:541:22]\n reg [2:0] sink;\t// @[Monitor.scala:542:22]\n reg denied;\t// @[Monitor.scala:543:22]\n reg [8:0] b_first_counter;\t// @[Edges.scala:229:27]\n reg [2:0] opcode_2;\t// @[Monitor.scala:410:22]\n reg [1:0] param_2;\t// @[Monitor.scala:411:22]\n reg [3:0] size_2;\t// @[Monitor.scala:412:22]\n reg [1:0] source_2;\t// @[Monitor.scala:413:22]\n reg [31:0] address_1;\t// @[Monitor.scala:414:22]\n wire _c_first_T_1 = io_in_c_ready & io_in_c_valid;\t// @[Decoupled.scala:51:35]\n reg [8:0] c_first_counter;\t// @[Edges.scala:229:27]\n reg [2:0] opcode_3;\t// @[Monitor.scala:515:22]\n reg [2:0] param_3;\t// @[Monitor.scala:516:22]\n reg [3:0] size_3;\t// @[Monitor.scala:517:22]\n reg [1:0] source_3;\t// @[Monitor.scala:518:22]\n reg [31:0] address_2;\t// @[Monitor.scala:519:22]\n reg [2:0] inflight;\t// @[Monitor.scala:614:27]\n reg [11:0] inflight_opcodes;\t// @[Monitor.scala:616:35]\n reg [23:0] inflight_sizes;\t// @[Monitor.scala:618:33]\n reg [8:0] a_first_counter_1;\t// @[Edges.scala:229:27]\n wire a_first_1 = a_first_counter_1 == 9'h0;\t// @[Edges.scala:229:27, :231:25]\n reg [8:0] d_first_counter_1;\t// @[Edges.scala:229:27]\n wire d_first_1 = d_first_counter_1 == 9'h0;\t// @[Edges.scala:229:27, :231:25]\n wire [3:0] _GEN_1 = {2'h0, io_in_a_bits_source};\t// @[OneHot.scala:58:35]\n wire _GEN_2 = _a_first_T_1 & a_first_1;\t// @[Decoupled.scala:51:35]\n wire d_release_ack = io_in_d_bits_opcode == 3'h6;\t// @[Monitor.scala:673:46]\n wire _GEN_3 = io_in_d_bits_opcode != 3'h6;\t// @[Monitor.scala:673:46, :674:74]\n wire [3:0] _GEN_4 = {2'h0, io_in_d_bits_source};\t// @[OneHot.scala:58:35]\n reg [31:0] watchdog;\t// @[Monitor.scala:709:27]\n reg [2:0] inflight_1;\t// @[Monitor.scala:726:35]\n reg [23:0] inflight_sizes_1;\t// @[Monitor.scala:728:35]\n reg [8:0] c_first_counter_1;\t// @[Edges.scala:229:27]\n wire c_first_1 = c_first_counter_1 == 9'h0;\t// @[Edges.scala:229:27, :231:25]\n reg [8:0] d_first_counter_2;\t// @[Edges.scala:229:27]\n wire d_first_2 = d_first_counter_2 == 9'h0;\t// @[Edges.scala:229:27, :231:25]\n wire _GEN_5 = io_in_c_bits_opcode[2] & io_in_c_bits_opcode[1];\t// @[Edges.scala:68:{36,40,51}]\n wire [3:0] _GEN_6 = {2'h0, io_in_c_bits_source};\t// @[OneHot.scala:58:35]\n wire _GEN_7 = _c_first_T_1 & c_first_1 & _GEN_5;\t// @[Decoupled.scala:51:35]\n reg [31:0] watchdog_1;\t// @[Monitor.scala:818:27]\n reg [7:0] inflight_2;\t// @[Monitor.scala:828:27]\n reg [8:0] d_first_counter_3;\t// @[Edges.scala:229:27]\n wire d_first_3 = d_first_counter_3 == 9'h0;\t// @[Edges.scala:229:27, :231:25]\n wire _GEN_8 = _d_first_T_3 & d_first_3 & io_in_d_bits_opcode[2] & ~(io_in_d_bits_opcode[1]);\t// @[Decoupled.scala:51:35]\n wire [7:0] _GEN_9 = {5'h0, io_in_d_bits_sink};\t// @[OneHot.scala:58:35]\n wire [7:0] d_set = _GEN_8 ? 8'h1 << _GEN_9 : 8'h0;\t// @[OneHot.scala:58:35]\n wire _GEN_10 = io_in_e_ready & io_in_e_valid;\t// @[Decoupled.scala:51:35]\n wire [7:0] _GEN_11 = {5'h0, io_in_e_bits_sink};\t// @[OneHot.scala:58:35]"}}},{"rowIdx":577,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to the following Chisel files.\nFile Nodes.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.tilelink\n\nimport chisel3._\nimport chisel3.experimental.SourceInfo\n\nimport org.chipsalliance.cde.config._\nimport org.chipsalliance.diplomacy._\nimport org.chipsalliance.diplomacy.nodes._\n\nimport freechips.rocketchip.util.{AsyncQueueParams,RationalDirection}\n\ncase object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args))\n\nobject TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle]\n{\n def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo)\n def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo)\n\n def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle)\n def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle)\n\n def render(ei: TLEdgeIn) = RenderedEdge(colour = \"#000000\" /* black */, label = (ei.manager.beatBytes * 8).toString)\n\n override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = {\n val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge)))\n monitor.io.in := bundle\n }\n\n override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters =\n pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })\n override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters =\n pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })\n}\n\n\ntrait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut]\n\ncase class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode\ncase class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode\n\ncase class TLAdapterNode(\n clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s },\n managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })(\n implicit valName: ValName)\n extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode\n\ncase class TLJunctionNode(\n clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters],\n managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])(\n implicit valName: ValName)\n extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode\n\ncase class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode\n\nobject TLNameNode {\n def apply(name: ValName) = TLIdentityNode()(name)\n def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse(\"with_no_name\")))\n def apply(name: String): TLIdentityNode = apply(Some(name))\n}\n\ncase class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)()\n\nobject TLTempNode {\n def apply(): TLEphemeralNode = TLEphemeralNode()(ValName(\"temp\"))\n}\n\ncase class TLNexusNode(\n clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters,\n managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)(\n implicit valName: ValName)\n extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode\n\nabstract class TLCustomNode(implicit valName: ValName)\n extends CustomNode(TLImp) with TLFormatNode\n\n// Asynchronous crossings\n\ntrait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters]\n\nobject TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle]\n{\n def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo)\n def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle)\n def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = \"#ff0000\" /* red */, label = e.manager.async.depth.toString)\n\n override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters =\n pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))\n override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters =\n pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))\n}\n\ncase class TLAsyncAdapterNode(\n clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s },\n managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })(\n implicit valName: ValName)\n extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode\n\ncase class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode\n\nobject TLAsyncNameNode {\n def apply(name: ValName) = TLAsyncIdentityNode()(name)\n def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse(\"with_no_name\")))\n def apply(name: String): TLAsyncIdentityNode = apply(Some(name))\n}\n\ncase class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName)\n extends MixedAdapterNode(TLImp, TLAsyncImp)(\n dFn = { p => TLAsyncClientPortParameters(p) },\n uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain\ncase class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName)\n extends MixedAdapterNode(TLAsyncImp, TLImp)(\n dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) },\n uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut]\n\n// Rationally related crossings\n\ntrait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters]\n\nobject TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle]\n{\n def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo)\n def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle)\n def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = \"#00ff00\" /* green */)\n\n override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters =\n pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))\n override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters =\n pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))\n}\n\ncase class TLRationalAdapterNode(\n clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s },\n managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })(\n implicit valName: ValName)\n extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode\n\ncase class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode\n\nobject TLRationalNameNode {\n def apply(name: ValName) = TLRationalIdentityNode()(name)\n def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse(\"with_no_name\")))\n def apply(name: String): TLRationalIdentityNode = apply(Some(name))\n}\n\ncase class TLRationalSourceNode()(implicit valName: ValName)\n extends MixedAdapterNode(TLImp, TLRationalImp)(\n dFn = { p => TLRationalClientPortParameters(p) },\n uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain\ncase class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName)\n extends MixedAdapterNode(TLRationalImp, TLImp)(\n dFn = { p => p.base.v1copy(minLatency = 1) },\n uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut]\n\n// Credited version of TileLink channels\n\ntrait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters]\n\nobject TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle]\n{\n def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo)\n def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle)\n def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = \"#ffff00\" /* yellow */, e.delay.toString)\n\n override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters =\n pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))\n override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters =\n pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))\n}\n\ncase class TLCreditedAdapterNode(\n clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s },\n managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })(\n implicit valName: ValName)\n extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode\n\ncase class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode\n\nobject TLCreditedNameNode {\n def apply(name: ValName) = TLCreditedIdentityNode()(name)\n def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse(\"with_no_name\")))\n def apply(name: String): TLCreditedIdentityNode = apply(Some(name))\n}\n\ncase class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName)\n extends MixedAdapterNode(TLImp, TLCreditedImp)(\n dFn = { p => TLCreditedClientPortParameters(delay, p) },\n uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain\n\ncase class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName)\n extends MixedAdapterNode(TLCreditedImp, TLImp)(\n dFn = { p => p.base.v1copy(minLatency = 1) },\n uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut]\nFile AsyncQueue.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3._\nimport chisel3.util._\n\ncase class AsyncQueueParams(\n depth: Int = 8,\n sync: Int = 3,\n safe: Boolean = true,\n// If safe is true, then effort is made to resynchronize the crossing indices when either side is reset.\n// This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty.\n narrow: Boolean = false)\n// If narrow is true then the read mux is moved to the source side of the crossing.\n// This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing,\n// at the expense of a combinational path from the sink to the source and back to the sink.\n{\n require (depth > 0 && isPow2(depth))\n require (sync >= 2)\n\n val bits = log2Ceil(depth)\n val wires = if (narrow) 1 else depth\n}\n\nobject AsyncQueueParams {\n // When there is only one entry, we don't need narrow.\n def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false)\n}\n\nclass AsyncBundleSafety extends Bundle {\n val ridx_valid = Input (Bool())\n val widx_valid = Output(Bool())\n val source_reset_n = Output(Bool())\n val sink_reset_n = Input (Bool())\n}\n\nclass AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle {\n // Data-path synchronization\n val mem = Output(Vec(params.wires, gen))\n val ridx = Input (UInt((params.bits+1).W))\n val widx = Output(UInt((params.bits+1).W))\n val index = params.narrow.option(Input(UInt(params.bits.W)))\n\n // Signals used to self-stabilize a safe AsyncQueue\n val safe = params.safe.option(new AsyncBundleSafety)\n}\n\nobject GrayCounter {\n def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = \"binary\"): UInt = {\n val incremented = Wire(UInt(bits.W))\n val binary = RegNext(next=incremented, init=0.U).suggestName(name)\n incremented := Mux(clear, 0.U, binary + increment.asUInt)\n incremented ^ (incremented >> 1)\n }\n}\n\nclass AsyncValidSync(sync: Int, desc: String) extends RawModule {\n val io = IO(new Bundle {\n val in = Input(Bool())\n val out = Output(Bool())\n })\n val clock = IO(Input(Clock()))\n val reset = IO(Input(AsyncReset()))\n withClockAndReset(clock, reset){\n io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc))\n }\n}\n\nclass AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {\n override def desiredName = s\"AsyncQueueSource_${gen.typeName}\"\n\n val io = IO(new Bundle {\n // These come from the source domain\n val enq = Flipped(Decoupled(gen))\n // These cross to the sink clock domain\n val async = new AsyncBundle(gen, params)\n })\n\n val bits = params.bits\n val sink_ready = WireInit(true.B)\n val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all.\n val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, \"widx_bin\"))\n val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some(\"ridx_gray\"))\n val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U)\n\n val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1))\n when (io.enq.fire) { mem(index) := io.enq.bits }\n\n val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName(\"ready_reg\"))\n io.enq.ready := ready_reg && sink_ready\n\n val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName(\"widx_gray\"))\n io.async.widx := widx_reg\n\n io.async.index match {\n case Some(index) => io.async.mem(0) := mem(index)\n case None => io.async.mem := mem\n }\n\n io.async.safe.foreach { sio =>\n val source_valid_0 = Module(new AsyncValidSync(params.sync, \"source_valid_0\"))\n val source_valid_1 = Module(new AsyncValidSync(params.sync, \"source_valid_1\"))\n\n val sink_extend = Module(new AsyncValidSync(params.sync, \"sink_extend\"))\n val sink_valid = Module(new AsyncValidSync(params.sync, \"sink_valid\"))\n source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset\n source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset\n sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset\n sink_valid .reset := reset.asAsyncReset\n\n source_valid_0.clock := clock\n source_valid_1.clock := clock\n sink_extend .clock := clock\n sink_valid .clock := clock\n\n source_valid_0.io.in := true.B\n source_valid_1.io.in := source_valid_0.io.out\n sio.widx_valid := source_valid_1.io.out\n sink_extend.io.in := sio.ridx_valid\n sink_valid.io.in := sink_extend.io.out\n sink_ready := sink_valid.io.out\n sio.source_reset_n := !reset.asBool\n\n // Assert that if there is stuff in the queue, then reset cannot happen\n // Impossible to write because dequeue can occur on the receiving side,\n // then reset allowed to happen, but write side cannot know that dequeue\n // occurred.\n // TODO: write some sort of sanity check assertion for users\n // that denote don't reset when there is activity\n // assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, \"Enqueue while sink is reset and AsyncQueueSource is unprotected\")\n // assert (!reset_rise || prev_idx_match.asBool, \"Sink reset while AsyncQueueSource not empty\")\n }\n}\n\nclass AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {\n override def desiredName = s\"AsyncQueueSink_${gen.typeName}\"\n\n val io = IO(new Bundle {\n // These come from the sink domain\n val deq = Decoupled(gen)\n // These cross to the source clock domain\n val async = Flipped(new AsyncBundle(gen, params))\n })\n\n val bits = params.bits\n val source_ready = WireInit(true.B)\n val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, \"ridx_bin\"))\n val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some(\"widx_gray\"))\n val valid = source_ready && ridx =/= widx\n\n // The mux is safe because timing analysis ensures ridx has reached the register\n // On an ASIC, changes to the unread location cannot affect the selected value\n // On an FPGA, only one input changes at a time => mem updates don't cause glitches\n // The register only latches when the selected valued is not being written\n val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1))\n io.async.index.foreach { _ := index }\n // This register does not NEED to be reset, as its contents will not\n // be considered unless the asynchronously reset deq valid register is set.\n // It is possible that bits latches when the source domain is reset / has power cut\n // This is safe, because isolation gates brought mem low before the zeroed widx reached us\n val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index)\n io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some(\"deq_bits_reg\"))\n\n val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName(\"valid_reg\"))\n io.deq.valid := valid_reg && source_ready\n\n val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName(\"ridx_gray\"))\n io.async.ridx := ridx_reg\n\n io.async.safe.foreach { sio =>\n val sink_valid_0 = Module(new AsyncValidSync(params.sync, \"sink_valid_0\"))\n val sink_valid_1 = Module(new AsyncValidSync(params.sync, \"sink_valid_1\"))\n\n val source_extend = Module(new AsyncValidSync(params.sync, \"source_extend\"))\n val source_valid = Module(new AsyncValidSync(params.sync, \"source_valid\"))\n sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset\n sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset\n source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset\n source_valid .reset := reset.asAsyncReset\n\n sink_valid_0 .clock := clock\n sink_valid_1 .clock := clock\n source_extend.clock := clock\n source_valid .clock := clock\n\n sink_valid_0.io.in := true.B\n sink_valid_1.io.in := sink_valid_0.io.out\n sio.ridx_valid := sink_valid_1.io.out\n source_extend.io.in := sio.widx_valid\n source_valid.io.in := source_extend.io.out\n source_ready := source_valid.io.out\n sio.sink_reset_n := !reset.asBool\n\n // TODO: write some sort of sanity check assertion for users\n // that denote don't reset when there is activity\n // \n // val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool\n // val reset_and_extend_prev = RegNext(reset_and_extend, true.B)\n // val reset_rise = !reset_and_extend_prev && reset_and_extend\n // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0)\n // assert (!reset_rise || prev_idx_match.asBool, \"Source reset while AsyncQueueSink not empty\")\n }\n}\n\nobject FromAsyncBundle\n{\n // Sometimes it makes sense for the sink to have different sync than the source\n def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync)\n def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = {\n val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync)))\n sink.io.async <> x\n sink.io.deq\n }\n}\n\nobject ToAsyncBundle\n{\n def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = {\n val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params))\n source.io.enq <> x\n source.io.async\n }\n}\n\nclass AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] {\n val io = IO(new CrossingIO(gen))\n val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) }\n val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) }\n\n source.io.enq <> io.enq\n io.deq <> sink.io.deq\n sink.io.async <> source.io.async\n}\nFile AsyncCrossing.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.tilelink\n\nimport chisel3._\n\nimport org.chipsalliance.cde.config._\nimport org.chipsalliance.diplomacy.lazymodule._\n\nimport freechips.rocketchip.diplomacy.{AddressSet, NodeHandle}\nimport freechips.rocketchip.prci.{AsynchronousCrossing}\nimport freechips.rocketchip.subsystem.CrossingWrapper\nimport freechips.rocketchip.util.{AsyncQueueParams, ToAsyncBundle, FromAsyncBundle, Pow2ClockDivider, property}\n\nclass TLAsyncCrossingSource(sync: Option[Int])(implicit p: Parameters) extends LazyModule\n{\n def this(x: Int)(implicit p: Parameters) = this(Some(x))\n def this()(implicit p: Parameters) = this(None)\n\n val node = TLAsyncSourceNode(sync)\n\n lazy val module = new Impl\n class Impl extends LazyModuleImp(this) {\n override def desiredName = (Seq(\"TLAsyncCrossingSource\") ++ node.in.headOption.map(_._2.bundle.shortName)).mkString(\"_\")\n (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>\n val bce = edgeIn.manager.anySupportAcquireB && edgeIn.client.anySupportProbe\n val psync = sync.getOrElse(edgeOut.manager.async.sync)\n val params = edgeOut.manager.async.copy(sync = psync)\n\n out.a <> ToAsyncBundle(in.a, params)\n in.d <> FromAsyncBundle(out.d, psync)\n property.cover(in.a, \"TL_ASYNC_CROSSING_SOURCE_A\", \"MemorySystem;;TLAsyncCrossingSource Channel A\")\n property.cover(in.d, \"TL_ASYNC_CROSSING_SOURCE_D\", \"MemorySystem;;TLAsyncCrossingSource Channel D\")\n\n if (bce) {\n in.b <> FromAsyncBundle(out.b, psync)\n out.c <> ToAsyncBundle(in.c, params)\n out.e <> ToAsyncBundle(in.e, params)\n property.cover(in.b, \"TL_ASYNC_CROSSING_SOURCE_B\", \"MemorySystem;;TLAsyncCrossingSource Channel B\")\n property.cover(in.c, \"TL_ASYNC_CROSSING_SOURCE_C\", \"MemorySystem;;TLAsyncCrossingSource Channel C\")\n property.cover(in.e, \"TL_ASYNC_CROSSING_SOURCE_E\", \"MemorySystem;;TLAsyncCrossingSource Channel E\")\n } else {\n in.b.valid := false.B\n in.c.ready := true.B\n in.e.ready := true.B\n out.b.ridx := 0.U\n out.c.widx := 0.U\n out.e.widx := 0.U\n }\n }\n }\n}\n\nclass TLAsyncCrossingSink(params: AsyncQueueParams = AsyncQueueParams())(implicit p: Parameters) extends LazyModule\n{\n val node = TLAsyncSinkNode(params)\n\n lazy val module = new Impl\n class Impl extends LazyModuleImp(this) {\n override def desiredName = (Seq(\"TLAsyncCrossingSink\") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString(\"_\")\n (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>\n val bce = edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe\n\n out.a <> FromAsyncBundle(in.a, params.sync)\n in.d <> ToAsyncBundle(out.d, params)\n property.cover(out.a, \"TL_ASYNC_CROSSING_SINK_A\", \"MemorySystem;;TLAsyncCrossingSink Channel A\")\n property.cover(out.d, \"TL_ASYNC_CROSSING_SINK_D\", \"MemorySystem;;TLAsyncCrossingSink Channel D\")\n\n if (bce) {\n in.b <> ToAsyncBundle(out.b, params)\n out.c <> FromAsyncBundle(in.c, params.sync)\n out.e <> FromAsyncBundle(in.e, params.sync)\n property.cover(out.b, \"TL_ASYNC_CROSSING_SINK_B\", \"MemorySystem;;TLAsyncCrossingSinkChannel B\")\n property.cover(out.c, \"TL_ASYNC_CROSSING_SINK_C\", \"MemorySystem;;TLAsyncCrossingSink Channel C\")\n property.cover(out.e, \"TL_ASYNC_CROSSING_SINK_E\", \"MemorySystem;;TLAsyncCrossingSink Channel E\")\n } else {\n in.b.widx := 0.U\n in.c.ridx := 0.U\n in.e.ridx := 0.U\n out.b.ready := true.B\n out.c.valid := false.B\n out.e.valid := false.B\n }\n }\n }\n}\n\nobject TLAsyncCrossingSource\n{\n def apply()(implicit p: Parameters): TLAsyncSourceNode = apply(None)\n def apply(sync: Int)(implicit p: Parameters): TLAsyncSourceNode = apply(Some(sync))\n def apply(sync: Option[Int])(implicit p: Parameters): TLAsyncSourceNode =\n {\n val asource = LazyModule(new TLAsyncCrossingSource(sync))\n asource.node\n }\n}\n\nobject TLAsyncCrossingSink\n{\n def apply(params: AsyncQueueParams = AsyncQueueParams())(implicit p: Parameters) =\n {\n val asink = LazyModule(new TLAsyncCrossingSink(params))\n asink.node\n }\n}\n\n@deprecated(\"TLAsyncCrossing is fragile. Use TLAsyncCrossingSource and TLAsyncCrossingSink\", \"rocket-chip 1.2\")\nclass TLAsyncCrossing(params: AsyncQueueParams = AsyncQueueParams())(implicit p: Parameters) extends LazyModule\n{\n val source = LazyModule(new TLAsyncCrossingSource())\n val sink = LazyModule(new TLAsyncCrossingSink(params))\n val node = NodeHandle(source.node, sink.node)\n\n sink.node := source.node\n\n lazy val module = new Impl\n class Impl extends LazyModuleImp(this) {\n val io = IO(new Bundle {\n val in_clock = Input(Clock())\n val in_reset = Input(Bool())\n val out_clock = Input(Clock())\n val out_reset = Input(Bool())\n })\n\n source.module.clock := io.in_clock\n source.module.reset := io.in_reset\n sink.module.clock := io.out_clock\n sink.module.reset := io.out_reset\n }\n}\n\n// Synthesizable unit tests\nimport freechips.rocketchip.unittest._\n\nclass TLRAMAsyncCrossing(txns: Int, params: AsynchronousCrossing = AsynchronousCrossing())(implicit p: Parameters) extends LazyModule {\n val model = LazyModule(new TLRAMModel(\"AsyncCrossing\"))\n val fuzz = LazyModule(new TLFuzzer(txns))\n val island = LazyModule(new CrossingWrapper(params))\n val ram = island { LazyModule(new TLRAM(AddressSet(0x0, 0x3ff))) }\n\n island.crossTLIn(ram.node) := TLFragmenter(4, 256) := TLDelayer(0.1) := model.node := fuzz.node\n\n lazy val module = new Impl\n class Impl extends LazyModuleImp(this) with UnitTestModule {\n io.finished := fuzz.module.io.finished\n\n // Shove the RAM into another clock domain\n val clocks = Module(new Pow2ClockDivider(2))\n island.module.clock := clocks.io.clock_out\n }\n}\n\nclass TLRAMAsyncCrossingTest(txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {\n val dut_wide = Module(LazyModule(new TLRAMAsyncCrossing(txns)).module)\n val dut_narrow = Module(LazyModule(new TLRAMAsyncCrossing(txns, AsynchronousCrossing(safe = false, narrow = true))).module)\n io.finished := dut_wide.io.finished && dut_narrow.io.finished\n dut_wide.io.start := io.start\n dut_narrow.io.start := io.start\n}\nFile LazyModuleImp.scala:\npackage org.chipsalliance.diplomacy.lazymodule\n\nimport chisel3.{withClockAndReset, Module, RawModule, Reset, _}\nimport chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}\nimport firrtl.passes.InlineAnnotation\nimport org.chipsalliance.cde.config.Parameters\nimport org.chipsalliance.diplomacy.nodes.Dangle\n\nimport scala.collection.immutable.SortedMap\n\n/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].\n *\n * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.\n */\nsealed trait LazyModuleImpLike extends RawModule {\n\n /** [[LazyModule]] that contains this instance. */\n val wrapper: LazyModule\n\n /** IOs that will be automatically \"punched\" for this instance. */\n val auto: AutoBundle\n\n /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */\n protected[diplomacy] val dangles: Seq[Dangle]\n\n // [[wrapper.module]] had better not be accessed while LazyModules are still being built!\n require(\n LazyModule.scope.isEmpty,\n s\"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}\"\n )\n\n /** Set module name. Defaults to the containing LazyModule's desiredName. */\n override def desiredName: String = wrapper.desiredName\n\n suggestName(wrapper.suggestedName)\n\n /** [[Parameters]] for chisel [[Module]]s. */\n implicit val p: Parameters = wrapper.p\n\n /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and\n * submodules.\n */\n protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {\n // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],\n // 2. return [[Dangle]]s from each module.\n val childDangles = wrapper.children.reverse.flatMap { c =>\n implicit val sourceInfo: SourceInfo = c.info\n c.cloneProto.map { cp =>\n // If the child is a clone, then recursively set cloneProto of its children as well\n def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {\n require(bases.size == clones.size)\n (bases.zip(clones)).map { case (l, r) =>\n require(l.getClass == r.getClass, s\"Cloned children class mismatch ${l.name} != ${r.name}\")\n l.cloneProto = Some(r)\n assignCloneProtos(l.children, r.children)\n }\n }\n assignCloneProtos(c.children, cp.children)\n // Clone the child module as a record, and get its [[AutoBundle]]\n val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)\n val clonedAuto = clone(\"auto\").asInstanceOf[AutoBundle]\n // Get the empty [[Dangle]]'s of the cloned child\n val rawDangles = c.cloneDangles()\n require(rawDangles.size == clonedAuto.elements.size)\n // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s\n val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }\n dangles\n }.getOrElse {\n // For non-clones, instantiate the child module\n val mod = try {\n Module(c.module)\n } catch {\n case e: ChiselException => {\n println(s\"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}\")\n throw e\n }\n }\n mod.dangles\n }\n }\n\n // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].\n // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.\n val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())\n // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]\n val allDangles = nodeDangles ++ childDangles\n // Group [[allDangles]] by their [[source]].\n val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)\n // For each [[source]] set of [[Dangle]]s of size 2, ensure that these\n // can be connected as a source-sink pair (have opposite flipped value).\n // Make the connection and mark them as [[done]].\n val done = Set() ++ pairing.values.filter(_.size == 2).map {\n case Seq(a, b) =>\n require(a.flipped != b.flipped)\n // @todo <> in chisel3 makes directionless connection.\n if (a.flipped) {\n a.data <> b.data\n } else {\n b.data <> a.data\n }\n a.source\n case _ => None\n }\n // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.\n val forward = allDangles.filter(d => !done(d.source))\n // Generate [[AutoBundle]] IO from [[forward]].\n val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))\n // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]\n val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>\n if (d.flipped) {\n d.data <> io\n } else {\n io <> d.data\n }\n d.copy(dataOpt = Some(io), name = wrapper.suggestedName + \"_\" + d.name)\n }\n // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].\n wrapper.inModuleBody.reverse.foreach {\n _()\n }\n\n if (wrapper.shouldBeInlined) {\n chisel3.experimental.annotate(new ChiselAnnotation {\n def toFirrtl = InlineAnnotation(toNamed)\n })\n }\n\n // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].\n (auto, dangles)\n }\n}\n\n/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].\n *\n * @param wrapper\n * the [[LazyModule]] from which the `.module` call is being made.\n */\nclass LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {\n\n /** Instantiate hardware of this `Module`. */\n val (auto, dangles) = instantiate()\n}\n\n/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].\n *\n * @param wrapper\n * the [[LazyModule]] from which the `.module` call is being made.\n */\nclass LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {\n // These wires are the default clock+reset for all LazyModule children.\n // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the\n // [[LazyRawModuleImp]] children.\n // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.\n /** drive clock explicitly. */\n val childClock: Clock = Wire(Clock())\n\n /** drive reset explicitly. */\n val childReset: Reset = Wire(Reset())\n // the default is that these are disabled\n childClock := false.B.asClock\n childReset := chisel3.DontCare\n\n def provideImplicitClockToLazyChildren: Boolean = false\n val (auto, dangles) =\n if (provideImplicitClockToLazyChildren) {\n withClockAndReset(childClock, childReset) { instantiate() }\n } else {\n instantiate()\n }\n}\nFile MixedNode.scala:\npackage org.chipsalliance.diplomacy.nodes\n\nimport chisel3.{Data, DontCare, Wire}\nimport chisel3.experimental.SourceInfo\nimport org.chipsalliance.cde.config.{Field, Parameters}\n\nimport org.chipsalliance.diplomacy.ValName\nimport org.chipsalliance.diplomacy.sourceLine\n\n/** One side metadata of a [[Dangle]].\n *\n * Describes one side of an edge going into or out of a [[BaseNode]].\n *\n * @param serial\n * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.\n * @param index\n * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.\n */\ncase class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {\n\n import scala.math.Ordered.orderingToOrdered\n\n def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))\n}\n\n/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]\n * connects.\n *\n * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,\n * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].\n *\n * @param source\n * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within\n * that [[BaseNode]].\n * @param sink\n * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that\n * [[BaseNode]].\n * @param flipped\n * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to\n * `danglesIn`.\n * @param dataOpt\n * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module\n */\ncase class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {\n def data = dataOpt.get\n}\n\n/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often\n * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually\n * implement the protocol.\n */\ncase class Edges[EI, EO](in: Seq[EI], out: Seq[EO])\n\n/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */\ncase object MonitorsEnabled extends Field[Boolean](true)\n\n/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.\n *\n * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but\n * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink\n * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the\n * [[LazyModule]].\n */\ncase object RenderFlipped extends Field[Boolean](false)\n\n/** The sealed node class in the package, all node are derived from it.\n *\n * @param inner\n * Sink interface implementation.\n * @param outer\n * Source interface implementation.\n * @param valName\n * val name of this node.\n * @tparam DI\n * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters\n * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected\n * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port\n * parameters.\n * @tparam UI\n * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing\n * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.\n * @tparam EI\n * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers\n * specified for a sink according to protocol.\n * @tparam BI\n * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.\n * It should extends from [[chisel3.Data]], which represents the real hardware.\n * @tparam DO\n * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters\n * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.\n * @tparam UO\n * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing\n * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].\n * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.\n * @tparam EO\n * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers\n * specified for a source according to protocol.\n * @tparam BO\n * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source\n * interface. It should extends from [[chisel3.Data]], which represents the real hardware.\n *\n * @note\n * Call Graph of [[MixedNode]]\n * - line `─`: source is process by a function and generate pass to others\n * - Arrow `→`: target of arrow is generated by source\n *\n * {{{\n * (from the other node)\n * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐\n * ↓ │\n * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │\n * [[InwardNode.accPI]] │ │ │\n * │ │ (based on protocol) │\n * │ │ [[MixedNode.inner.edgeI]] │\n * │ │ ↓ │\n * ↓ │ │ │\n * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │\n * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │\n * │ │ ↑ │ │ │\n * │ │ │ [[OutwardNode.doParams]] │ │\n * │ │ │ (from the other node) │ │\n * │ │ │ │ │ │\n * │ │ │ │ │ │\n * │ │ │ └────────┬──────────────┤ │\n * │ │ │ │ │ │\n * │ │ │ │ (based on protocol) │\n * │ │ │ │ [[MixedNode.inner.edgeI]] │\n * │ │ │ │ │ │\n * │ │ (from the other node) │ ↓ │\n * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │\n * │ ↑ ↑ │ │ ↓ │\n * │ │ │ │ │ [[MixedNode.in]] │\n * │ │ │ │ ↓ ↑ │\n * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │\n * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │\n * │ │ │ [[MixedNode.bundleOut]]─┐ │ │\n * │ │ │ ↑ ↓ │ │\n * │ │ │ │ [[MixedNode.out]] │ │\n * │ ↓ ↓ │ ↑ │ │\n * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │\n * │ │ (from the other node) ↑ │ │\n * │ │ │ │ │ │\n * │ │ │ [[MixedNode.outer.edgeO]] │ │\n * │ │ │ (based on protocol) │ │\n * │ │ │ │ │ │\n * │ │ │ ┌────────────────────────────────────────┤ │ │\n * │ │ │ │ │ │ │\n * │ │ │ │ │ │ │\n * │ │ │ │ │ │ │\n * (immobilize after elaboration)│ ↓ │ │ │ │\n * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │\n * ↑ (inward port from [[OutwardNode]]) │ │ │ │\n * │ ┌─────────────────────────────────────────┤ │ │ │\n * │ │ │ │ │ │\n * │ │ │ │ │ │\n * [[OutwardNode.accPO]] │ ↓ │ │ │\n * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │\n * │ ↑ │ │\n * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │\n * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘\n * }}}\n */\nabstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](\n val inner: InwardNodeImp[DI, UI, EI, BI],\n val outer: OutwardNodeImp[DO, UO, EO, BO]\n)(\n implicit valName: ValName)\n extends BaseNode\n with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]\n with InwardNode[DI, UI, BI]\n with OutwardNode[DO, UO, BO] {\n // Generate a [[NodeHandle]] with inward and outward node are both this node.\n val inward = this\n val outward = this\n\n /** Debug info of nodes binding. */\n def bindingInfo: String = s\"\"\"$iBindingInfo\n |$oBindingInfo\n |\"\"\".stripMargin\n\n /** Debug info of ports connecting. */\n def connectedPortsInfo: String = s\"\"\"${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(\",\")}]\n |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(\",\")}]\n |\"\"\".stripMargin\n\n /** Debug info of parameters propagations. */\n def parametersInfo: String = s\"\"\"${doParams.size} downstream outward parameters: [${doParams.mkString(\",\")}]\n |${uoParams.size} upstream outward parameters: [${uoParams.mkString(\",\")}]\n |${diParams.size} downstream inward parameters: [${diParams.mkString(\",\")}]\n |${uiParams.size} upstream inward parameters: [${uiParams.mkString(\",\")}]\n |\"\"\".stripMargin\n\n /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and\n * [[MixedNode.iPortMapping]].\n *\n * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward\n * stars and outward stars.\n *\n * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type\n * of node.\n *\n * @param iKnown\n * Number of known-size ([[BIND_ONCE]]) input bindings.\n * @param oKnown\n * Number of known-size ([[BIND_ONCE]]) output bindings.\n * @param iStar\n * Number of unknown size ([[BIND_STAR]]) input bindings.\n * @param oStar\n * Number of unknown size ([[BIND_STAR]]) output bindings.\n * @return\n * A Tuple of the resolved number of input and output connections.\n */\n protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)\n\n /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output\n * ports.\n *\n * @param n\n * The size of the output sequence to generate.\n * @param p\n * Sequence of downward-flowing input parameters of this node.\n * @return\n * A `n`-sized sequence of downward-flowing output edge parameters.\n */\n protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]\n\n /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].\n *\n * @param n\n * Size of the output sequence.\n * @param p\n * Upward-flowing output edge parameters.\n * @return\n * A n-sized sequence of upward-flowing input edge parameters.\n */\n protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]\n\n /** @return\n * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with\n * [[BIND_STAR]].\n */\n protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)\n\n /** @return\n * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of\n * output bindings bound with [[BIND_STAR]].\n */\n protected[diplomacy] lazy val sourceCard: Int =\n iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)\n\n /** @return list of nodes involved in flex bindings with this node. */\n protected[diplomacy] lazy val flexes: Seq[BaseNode] =\n oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)\n\n /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin\n * greedily taking up the remaining connections.\n *\n * @return\n * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return\n * value is not relevant.\n */\n protected[diplomacy] lazy val flexOffset: Int = {\n\n /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex\n * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a\n * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of\n * each node in the current set and decide whether they should be added to the set or not.\n *\n * @return\n * the mapping of [[BaseNode]] indexed by their serial numbers.\n */\n def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {\n if (visited.contains(v.serial) || !v.flexibleArityDirection) {\n visited\n } else {\n v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))\n }\n }\n\n /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.\n *\n * @example\n * {{{\n * a :*=* b :*=* c\n * d :*=* b\n * e :*=* f\n * }}}\n *\n * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`\n */\n val flexSet = DFS(this, Map()).values\n\n /** The total number of :*= operators where we're on the left. */\n val allSink = flexSet.map(_.sinkCard).sum\n\n /** The total number of :=* operators used when we're on the right. */\n val allSource = flexSet.map(_.sourceCard).sum\n\n require(\n allSink == 0 || allSource == 0,\n s\"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction.\"\n )\n allSink - allSource\n }\n\n /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */\n protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {\n if (flexibleArityDirection) flexOffset\n else if (n.flexibleArityDirection) n.flexOffset\n else 0\n }\n\n /** For a node which is connected between two nodes, select the one that will influence the direction of the flex\n * resolution.\n */\n protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {\n val dir = edgeArityDirection(n)\n if (dir < 0) l\n else if (dir > 0) r\n else 1\n }\n\n /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */\n private var starCycleGuard = false\n\n /** Resolve all the star operators into concrete indicies. As connections are being made, some may be \"star\"\n * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also\n * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct\n * edge parameters and later build up correct bundle connections.\n *\n * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding\n * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort\n * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=\n * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`\n */\n protected[diplomacy] lazy val (\n oPortMapping: Seq[(Int, Int)],\n iPortMapping: Seq[(Int, Int)],\n oStar: Int,\n iStar: Int\n ) = {\n try {\n if (starCycleGuard) throw StarCycleException()\n starCycleGuard = true\n // For a given node N...\n // Number of foo :=* N\n // + Number of bar :=* foo :*=* N\n val oStars = oBindings.count { case (_, n, b, _, _) =>\n b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)\n }\n // Number of N :*= foo\n // + Number of N :*=* foo :*= bar\n val iStars = iBindings.count { case (_, n, b, _, _) =>\n b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)\n }\n // 1 for foo := N\n // + bar.iStar for bar :*= foo :*=* N\n // + foo.iStar for foo :*= N\n // + 0 for foo :=* N\n val oKnown = oBindings.map { case (_, n, b, _, _) =>\n b match {\n case BIND_ONCE => 1\n case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)\n case BIND_QUERY => n.iStar\n case BIND_STAR => 0\n }\n }.sum\n // 1 for N := foo\n // + bar.oStar for N :*=* foo :=* bar\n // + foo.oStar for N :=* foo\n // + 0 for N :*= foo\n val iKnown = iBindings.map { case (_, n, b, _, _) =>\n b match {\n case BIND_ONCE => 1\n case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)\n case BIND_QUERY => n.oStar\n case BIND_STAR => 0\n }\n }.sum\n // Resolve star depends on the node subclass to implement the algorithm for this.\n val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)\n // Cumulative list of resolved outward binding range starting points\n val oSum = oBindings.map { case (_, n, b, _, _) =>\n b match {\n case BIND_ONCE => 1\n case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)\n case BIND_QUERY => n.iStar\n case BIND_STAR => oStar\n }\n }.scanLeft(0)(_ + _)\n // Cumulative list of resolved inward binding range starting points\n val iSum = iBindings.map { case (_, n, b, _, _) =>\n b match {\n case BIND_ONCE => 1\n case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)\n case BIND_QUERY => n.oStar\n case BIND_STAR => iStar\n }\n }.scanLeft(0)(_ + _)\n // Create ranges for each binding based on the running sums and return\n // those along with resolved values for the star operations.\n (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)\n } catch {\n case c: StarCycleException => throw c.copy(loop = context +: c.loop)\n }\n }\n\n /** Sequence of inward ports.\n *\n * This should be called after all star bindings are resolved.\n *\n * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.\n * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this\n * connection was made in the source code.\n */\n protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =\n oBindings.flatMap { case (i, n, _, p, s) =>\n // for each binding operator in this node, look at what it connects to\n val (start, end) = n.iPortMapping(i)\n (start until end).map { j => (j, n, p, s) }\n }\n\n /** Sequence of outward ports.\n *\n * This should be called after all star bindings are resolved.\n *\n * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of\n * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection\n * was made in the source code.\n */\n protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =\n iBindings.flatMap { case (i, n, _, p, s) =>\n // query this port index range of this node in the other side of node.\n val (start, end) = n.oPortMapping(i)\n (start until end).map { j => (j, n, p, s) }\n }\n\n // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree\n // Thus, there must exist an Eulerian path and the below algorithms terminate\n @scala.annotation.tailrec\n private def oTrace(\n tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)\n ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {\n case (i, n, p, s) => n.iForward(i) match {\n case None => (i, n, p, s)\n case Some((j, m)) => oTrace((j, m, p, s))\n }\n }\n\n @scala.annotation.tailrec\n private def iTrace(\n tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)\n ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {\n case (i, n, p, s) => n.oForward(i) match {\n case None => (i, n, p, s)\n case Some((j, m)) => iTrace((j, m, p, s))\n }\n }\n\n /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.\n *\n * Each Port is a tuple of:\n * - Numeric index of this binding in the [[InwardNode]] on the other end.\n * - [[InwardNode]] on the other end of this binding.\n * - A view of [[Parameters]] where the binding occurred.\n * - [[SourceInfo]] for source-level error reporting.\n */\n lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)\n\n /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.\n *\n * Each Port is a tuple of:\n * - numeric index of this binding in [[OutwardNode]] on the other end.\n * - [[OutwardNode]] on the other end of this binding.\n * - a view of [[Parameters]] where the binding occurred.\n * - [[SourceInfo]] for source-level error reporting.\n */\n lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)\n\n private var oParamsCycleGuard = false\n protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }\n protected[diplomacy] lazy val doParams: Seq[DO] = {\n try {\n if (oParamsCycleGuard) throw DownwardCycleException()\n oParamsCycleGuard = true\n val o = mapParamsD(oPorts.size, diParams)\n require(\n o.size == oPorts.size,\n s\"\"\"Diplomacy has detected a problem with your graph:\n |At the following node, the number of outward ports should equal the number of produced outward parameters.\n |$context\n |$connectedPortsInfo\n |Downstreamed inward parameters: [${diParams.mkString(\",\")}]\n |Produced outward parameters: [${o.mkString(\",\")}]\n |\"\"\".stripMargin\n )\n o.map(outer.mixO(_, this))\n } catch {\n case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)\n }\n }\n\n private var iParamsCycleGuard = false\n protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }\n protected[diplomacy] lazy val uiParams: Seq[UI] = {\n try {\n if (iParamsCycleGuard) throw UpwardCycleException()\n iParamsCycleGuard = true\n val i = mapParamsU(iPorts.size, uoParams)\n require(\n i.size == iPorts.size,\n s\"\"\"Diplomacy has detected a problem with your graph:\n |At the following node, the number of inward ports should equal the number of produced inward parameters.\n |$context\n |$connectedPortsInfo\n |Upstreamed outward parameters: [${uoParams.mkString(\",\")}]\n |Produced inward parameters: [${i.mkString(\",\")}]\n |\"\"\".stripMargin\n )\n i.map(inner.mixI(_, this))\n } catch {\n case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)\n }\n }\n\n /** Outward edge parameters. */\n protected[diplomacy] lazy val edgesOut: Seq[EO] =\n (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }\n\n /** Inward edge parameters. */\n protected[diplomacy] lazy val edgesIn: Seq[EI] =\n (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }\n\n /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.\n *\n * If you need to access to the edges of a foreign Node, use this method (in/out create bundles).\n */\n lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)\n\n /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */\n protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>\n val x = Wire(outer.bundleO(e)).suggestName(s\"${valName.value}Out\")\n // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,\n // In the future, we should add an option to decide whether allowing unconnected in the LazyModule\n x := DontCare\n x\n }\n\n /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */\n protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>\n val x = Wire(inner.bundleI(e)).suggestName(s\"${valName.value}In\")\n // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,\n // In the future, we should add an option to decide whether allowing unconnected in the LazyModule\n x := DontCare\n x\n }\n\n private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>\n Dangle(\n source = HalfEdge(serial, i),\n sink = HalfEdge(n.serial, j),\n flipped = false,\n name = wirePrefix + \"out\",\n dataOpt = None\n )\n }\n private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>\n Dangle(\n source = HalfEdge(n.serial, j),\n sink = HalfEdge(serial, i),\n flipped = true,\n name = wirePrefix + \"in\",\n dataOpt = None\n )\n }\n\n /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */\n protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>\n d.copy(dataOpt = Some(bundleOut(i)))\n }\n\n /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */\n protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>\n d.copy(dataOpt = Some(bundleIn(i)))\n }\n\n private[diplomacy] var instantiated = false\n\n /** Gather Bundle and edge parameters of outward ports.\n *\n * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within\n * [[LazyModuleImp]] code or after its instantiation has completed.\n */\n def out: Seq[(BO, EO)] = {\n require(\n instantiated,\n s\"$name.out should not be called until after instantiation of its parent LazyModule.module has begun\"\n )\n bundleOut.zip(edgesOut)\n }\n\n /** Gather Bundle and edge parameters of inward ports.\n *\n * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within\n * [[LazyModuleImp]] code or after its instantiation has completed.\n */\n def in: Seq[(BI, EI)] = {\n require(\n instantiated,\n s\"$name.in should not be called until after instantiation of its parent LazyModule.module has begun\"\n )\n bundleIn.zip(edgesIn)\n }\n\n /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,\n * instantiate monitors on all input ports if appropriate, and return all the dangles of this node.\n */\n protected[diplomacy] def instantiate(): Seq[Dangle] = {\n instantiated = true\n if (!circuitIdentity) {\n (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }\n }\n danglesOut ++ danglesIn\n }\n\n protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn\n\n /** Connects the outward part of a node with the inward part of this node. */\n protected[diplomacy] def bind(\n h: OutwardNode[DI, UI, BI],\n binding: NodeBinding\n )(\n implicit p: Parameters,\n sourceInfo: SourceInfo\n ): Unit = {\n val x = this // x := y\n val y = h\n sourceLine(sourceInfo, \" at \", \"\")\n val i = x.iPushed\n val o = y.oPushed\n y.oPush(\n i,\n x,\n binding match {\n case BIND_ONCE => BIND_ONCE\n case BIND_FLEX => BIND_FLEX\n case BIND_STAR => BIND_QUERY\n case BIND_QUERY => BIND_STAR\n }\n )\n x.iPush(o, y, binding)\n }\n\n /* Metadata for printing the node graph. */\n def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>\n val re = inner.render(e)\n (n, re.copy(flipped = re.flipped != p(RenderFlipped)))\n }\n\n /** Metadata for printing the node graph */\n def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }\n}\n"},"response":{"kind":"string","value":"module TLAsyncCrossingSource_a32d64s2k3z4c(\t// @[AsyncCrossing.scala:23:9]\n input clock,\t// @[AsyncCrossing.scala:23:9]\n input reset,\t// @[AsyncCrossing.scala:23:9]\n output auto_in_a_ready,\t// @[LazyModuleImp.scala:107:25]\n input auto_in_a_valid,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_in_a_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_in_a_bits_param,\t// @[LazyModuleImp.scala:107:25]\n input [3:0] auto_in_a_bits_size,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_in_a_bits_source,\t// @[LazyModuleImp.scala:107:25]\n input [31:0] auto_in_a_bits_address,\t// @[LazyModuleImp.scala:107:25]\n input [7:0] auto_in_a_bits_mask,\t// @[LazyModuleImp.scala:107:25]\n input [63:0] auto_in_a_bits_data,\t// @[LazyModuleImp.scala:107:25]\n input auto_in_b_ready,\t// @[LazyModuleImp.scala:107:25]\n output auto_in_b_valid,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_in_b_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n output [1:0] auto_in_b_bits_param,\t// @[LazyModuleImp.scala:107:25]\n output [3:0] auto_in_b_bits_size,\t// @[LazyModuleImp.scala:107:25]\n output [1:0] auto_in_b_bits_source,\t// @[LazyModuleImp.scala:107:25]\n output [31:0] auto_in_b_bits_address,\t// @[LazyModuleImp.scala:107:25]\n output [7:0] auto_in_b_bits_mask,\t// @[LazyModuleImp.scala:107:25]\n output [63:0] auto_in_b_bits_data,\t// @[LazyModuleImp.scala:107:25]\n output auto_in_b_bits_corrupt,\t// @[LazyModuleImp.scala:107:25]\n output auto_in_c_ready,\t// @[LazyModuleImp.scala:107:25]\n input auto_in_c_valid,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_in_c_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_in_c_bits_param,\t// @[LazyModuleImp.scala:107:25]\n input [3:0] auto_in_c_bits_size,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_in_c_bits_source,\t// @[LazyModuleImp.scala:107:25]\n input [31:0] auto_in_c_bits_address,\t// @[LazyModuleImp.scala:107:25]\n input [63:0] auto_in_c_bits_data,\t// @[LazyModuleImp.scala:107:25]\n input auto_in_d_ready,\t// @[LazyModuleImp.scala:107:25]\n output auto_in_d_valid,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_in_d_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n output [1:0] auto_in_d_bits_param,\t// @[LazyModuleImp.scala:107:25]\n output [3:0] auto_in_d_bits_size,\t// @[LazyModuleImp.scala:107:25]\n output [1:0] auto_in_d_bits_source,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_in_d_bits_sink,\t// @[LazyModuleImp.scala:107:25]\n output auto_in_d_bits_denied,\t// @[LazyModuleImp.scala:107:25]\n output [63:0] auto_in_d_bits_data,\t// @[LazyModuleImp.scala:107:25]\n output auto_in_d_bits_corrupt,\t// @[LazyModuleImp.scala:107:25]\n output auto_in_e_ready,\t// @[LazyModuleImp.scala:107:25]\n input auto_in_e_valid,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_in_e_bits_sink,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_out_a_mem_0_opcode,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_out_a_mem_0_param,\t// @[LazyModuleImp.scala:107:25]\n output [3:0] auto_out_a_mem_0_size,\t// @[LazyModuleImp.scala:107:25]\n output [1:0] auto_out_a_mem_0_source,\t// @[LazyModuleImp.scala:107:25]\n output [31:0] auto_out_a_mem_0_address,\t// @[LazyModuleImp.scala:107:25]\n output [7:0] auto_out_a_mem_0_mask,\t// @[LazyModuleImp.scala:107:25]\n output [63:0] auto_out_a_mem_0_data,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_out_a_mem_1_opcode,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_out_a_mem_1_param,\t// @[LazyModuleImp.scala:107:25]\n output [3:0] auto_out_a_mem_1_size,\t// @[LazyModuleImp.scala:107:25]\n output [1:0] auto_out_a_mem_1_source,\t// @[LazyModuleImp.scala:107:25]\n output [31:0] auto_out_a_mem_1_address,\t// @[LazyModuleImp.scala:107:25]\n output [7:0] auto_out_a_mem_1_mask,\t// @[LazyModuleImp.scala:107:25]\n output [63:0] auto_out_a_mem_1_data,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_out_a_mem_2_opcode,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_out_a_mem_2_param,\t// @[LazyModuleImp.scala:107:25]\n output [3:0] auto_out_a_mem_2_size,\t// @[LazyModuleImp.scala:107:25]\n output [1:0] auto_out_a_mem_2_source,\t// @[LazyModuleImp.scala:107:25]\n output [31:0] auto_out_a_mem_2_address,\t// @[LazyModuleImp.scala:107:25]\n output [7:0] auto_out_a_mem_2_mask,\t// @[LazyModuleImp.scala:107:25]\n output [63:0] auto_out_a_mem_2_data,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_out_a_mem_3_opcode,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_out_a_mem_3_param,\t// @[LazyModuleImp.scala:107:25]\n output [3:0] auto_out_a_mem_3_size,\t// @[LazyModuleImp.scala:107:25]\n output [1:0] auto_out_a_mem_3_source,\t// @[LazyModuleImp.scala:107:25]\n output [31:0] auto_out_a_mem_3_address,\t// @[LazyModuleImp.scala:107:25]\n output [7:0] auto_out_a_mem_3_mask,\t// @[LazyModuleImp.scala:107:25]\n output [63:0] auto_out_a_mem_3_data,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_out_a_mem_4_opcode,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_out_a_mem_4_param,\t// @[LazyModuleImp.scala:107:25]\n output [3:0] auto_out_a_mem_4_size,\t// @[LazyModuleImp.scala:107:25]\n output [1:0] auto_out_a_mem_4_source,\t// @[LazyModuleImp.scala:107:25]\n output [31:0] auto_out_a_mem_4_address,\t// @[LazyModuleImp.scala:107:25]\n output [7:0] auto_out_a_mem_4_mask,\t// @[LazyModuleImp.scala:107:25]\n output [63:0] auto_out_a_mem_4_data,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_out_a_mem_5_opcode,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_out_a_mem_5_param,\t// @[LazyModuleImp.scala:107:25]\n output [3:0] auto_out_a_mem_5_size,\t// @[LazyModuleImp.scala:107:25]\n output [1:0] auto_out_a_mem_5_source,\t// @[LazyModuleImp.scala:107:25]\n output [31:0] auto_out_a_mem_5_address,\t// @[LazyModuleImp.scala:107:25]\n output [7:0] auto_out_a_mem_5_mask,\t// @[LazyModuleImp.scala:107:25]\n output [63:0] auto_out_a_mem_5_data,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_out_a_mem_6_opcode,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_out_a_mem_6_param,\t// @[LazyModuleImp.scala:107:25]\n output [3:0] auto_out_a_mem_6_size,\t// @[LazyModuleImp.scala:107:25]\n output [1:0] auto_out_a_mem_6_source,\t// @[LazyModuleImp.scala:107:25]\n output [31:0] auto_out_a_mem_6_address,\t// @[LazyModuleImp.scala:107:25]\n output [7:0] auto_out_a_mem_6_mask,\t// @[LazyModuleImp.scala:107:25]\n output [63:0] auto_out_a_mem_6_data,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_out_a_mem_7_opcode,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_out_a_mem_7_param,\t// @[LazyModuleImp.scala:107:25]\n output [3:0] auto_out_a_mem_7_size,\t// @[LazyModuleImp.scala:107:25]\n output [1:0] auto_out_a_mem_7_source,\t// @[LazyModuleImp.scala:107:25]\n output [31:0] auto_out_a_mem_7_address,\t// @[LazyModuleImp.scala:107:25]\n output [7:0] auto_out_a_mem_7_mask,\t// @[LazyModuleImp.scala:107:25]\n output [63:0] auto_out_a_mem_7_data,\t// @[LazyModuleImp.scala:107:25]\n input [3:0] auto_out_a_ridx,\t// @[LazyModuleImp.scala:107:25]\n output [3:0] auto_out_a_widx,\t// @[LazyModuleImp.scala:107:25]\n input auto_out_a_safe_ridx_valid,\t// @[LazyModuleImp.scala:107:25]\n output auto_out_a_safe_widx_valid,\t// @[LazyModuleImp.scala:107:25]\n output auto_out_a_safe_source_reset_n,\t// @[LazyModuleImp.scala:107:25]\n input auto_out_a_safe_sink_reset_n,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_out_b_mem_0_param,\t// @[LazyModuleImp.scala:107:25]\n input [31:0] auto_out_b_mem_0_address,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_out_b_mem_1_param,\t// @[LazyModuleImp.scala:107:25]\n input [31:0] auto_out_b_mem_1_address,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_out_b_mem_2_param,\t// @[LazyModuleImp.scala:107:25]\n input [31:0] auto_out_b_mem_2_address,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_out_b_mem_3_param,\t// @[LazyModuleImp.scala:107:25]\n input [31:0] auto_out_b_mem_3_address,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_out_b_mem_4_param,\t// @[LazyModuleImp.scala:107:25]\n input [31:0] auto_out_b_mem_4_address,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_out_b_mem_5_param,\t// @[LazyModuleImp.scala:107:25]\n input [31:0] auto_out_b_mem_5_address,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_out_b_mem_6_param,\t// @[LazyModuleImp.scala:107:25]\n input [31:0] auto_out_b_mem_6_address,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_out_b_mem_7_param,\t// @[LazyModuleImp.scala:107:25]\n input [31:0] auto_out_b_mem_7_address,\t// @[LazyModuleImp.scala:107:25]\n output [3:0] auto_out_b_ridx,\t// @[LazyModuleImp.scala:107:25]\n input [3:0] auto_out_b_widx,\t// @[LazyModuleImp.scala:107:25]\n output auto_out_b_safe_ridx_valid,\t// @[LazyModuleImp.scala:107:25]\n input auto_out_b_safe_widx_valid,\t// @[LazyModuleImp.scala:107:25]\n input auto_out_b_safe_source_reset_n,\t// @[LazyModuleImp.scala:107:25]\n output auto_out_b_safe_sink_reset_n,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_out_c_mem_0_opcode,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_out_c_mem_0_param,\t// @[LazyModuleImp.scala:107:25]\n output [3:0] auto_out_c_mem_0_size,\t// @[LazyModuleImp.scala:107:25]\n output [1:0] auto_out_c_mem_0_source,\t// @[LazyModuleImp.scala:107:25]\n output [31:0] auto_out_c_mem_0_address,\t// @[LazyModuleImp.scala:107:25]\n output [63:0] auto_out_c_mem_0_data,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_out_c_mem_1_opcode,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_out_c_mem_1_param,\t// @[LazyModuleImp.scala:107:25]\n output [3:0] auto_out_c_mem_1_size,\t// @[LazyModuleImp.scala:107:25]\n output [1:0] auto_out_c_mem_1_source,\t// @[LazyModuleImp.scala:107:25]\n output [31:0] auto_out_c_mem_1_address,\t// @[LazyModuleImp.scala:107:25]\n output [63:0] auto_out_c_mem_1_data,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_out_c_mem_2_opcode,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_out_c_mem_2_param,\t// @[LazyModuleImp.scala:107:25]\n output [3:0] auto_out_c_mem_2_size,\t// @[LazyModuleImp.scala:107:25]\n output [1:0] auto_out_c_mem_2_source,\t// @[LazyModuleImp.scala:107:25]\n output [31:0] auto_out_c_mem_2_address,\t// @[LazyModuleImp.scala:107:25]\n output [63:0] auto_out_c_mem_2_data,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_out_c_mem_3_opcode,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_out_c_mem_3_param,\t// @[LazyModuleImp.scala:107:25]\n output [3:0] auto_out_c_mem_3_size,\t// @[LazyModuleImp.scala:107:25]\n output [1:0] auto_out_c_mem_3_source,\t// @[LazyModuleImp.scala:107:25]\n output [31:0] auto_out_c_mem_3_address,\t// @[LazyModuleImp.scala:107:25]\n output [63:0] auto_out_c_mem_3_data,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_out_c_mem_4_opcode,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_out_c_mem_4_param,\t// @[LazyModuleImp.scala:107:25]\n output [3:0] auto_out_c_mem_4_size,\t// @[LazyModuleImp.scala:107:25]\n output [1:0] auto_out_c_mem_4_source,\t// @[LazyModuleImp.scala:107:25]\n output [31:0] auto_out_c_mem_4_address,\t// @[LazyModuleImp.scala:107:25]\n output [63:0] auto_out_c_mem_4_data,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_out_c_mem_5_opcode,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_out_c_mem_5_param,\t// @[LazyModuleImp.scala:107:25]\n output [3:0] auto_out_c_mem_5_size,\t// @[LazyModuleImp.scala:107:25]\n output [1:0] auto_out_c_mem_5_source,\t// @[LazyModuleImp.scala:107:25]\n output [31:0] auto_out_c_mem_5_address,\t// @[LazyModuleImp.scala:107:25]\n output [63:0] auto_out_c_mem_5_data,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_out_c_mem_6_opcode,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_out_c_mem_6_param,\t// @[LazyModuleImp.scala:107:25]\n output [3:0] auto_out_c_mem_6_size,\t// @[LazyModuleImp.scala:107:25]\n output [1:0] auto_out_c_mem_6_source,\t// @[LazyModuleImp.scala:107:25]\n output [31:0] auto_out_c_mem_6_address,\t// @[LazyModuleImp.scala:107:25]\n output [63:0] auto_out_c_mem_6_data,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_out_c_mem_7_opcode,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_out_c_mem_7_param,\t// @[LazyModuleImp.scala:107:25]\n output [3:0] auto_out_c_mem_7_size,\t// @[LazyModuleImp.scala:107:25]\n output [1:0] auto_out_c_mem_7_source,\t// @[LazyModuleImp.scala:107:25]\n output [31:0] auto_out_c_mem_7_address,\t// @[LazyModuleImp.scala:107:25]\n output [63:0] auto_out_c_mem_7_data,\t// @[LazyModuleImp.scala:107:25]\n input [3:0] auto_out_c_ridx,\t// @[LazyModuleImp.scala:107:25]\n output [3:0] auto_out_c_widx,\t// @[LazyModuleImp.scala:107:25]\n input auto_out_c_safe_ridx_valid,\t// @[LazyModuleImp.scala:107:25]\n output auto_out_c_safe_widx_valid,\t// @[LazyModuleImp.scala:107:25]\n output auto_out_c_safe_source_reset_n,\t// @[LazyModuleImp.scala:107:25]\n input auto_out_c_safe_sink_reset_n,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_out_d_mem_0_opcode,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_out_d_mem_0_param,\t// @[LazyModuleImp.scala:107:25]\n input [3:0] auto_out_d_mem_0_size,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_out_d_mem_0_source,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_out_d_mem_0_sink,\t// @[LazyModuleImp.scala:107:25]\n input auto_out_d_mem_0_denied,\t// @[LazyModuleImp.scala:107:25]\n input [63:0] auto_out_d_mem_0_data,\t// @[LazyModuleImp.scala:107:25]\n input auto_out_d_mem_0_corrupt,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_out_d_mem_1_opcode,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_out_d_mem_1_param,\t// @[LazyModuleImp.scala:107:25]\n input [3:0] auto_out_d_mem_1_size,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_out_d_mem_1_source,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_out_d_mem_1_sink,\t// @[LazyModuleImp.scala:107:25]\n input auto_out_d_mem_1_denied,\t// @[LazyModuleImp.scala:107:25]\n input [63:0] auto_out_d_mem_1_data,\t// @[LazyModuleImp.scala:107:25]\n input auto_out_d_mem_1_corrupt,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_out_d_mem_2_opcode,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_out_d_mem_2_param,\t// @[LazyModuleImp.scala:107:25]\n input [3:0] auto_out_d_mem_2_size,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_out_d_mem_2_source,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_out_d_mem_2_sink,\t// @[LazyModuleImp.scala:107:25]\n input auto_out_d_mem_2_denied,\t// @[LazyModuleImp.scala:107:25]\n input [63:0] auto_out_d_mem_2_data,\t// @[LazyModuleImp.scala:107:25]\n input auto_out_d_mem_2_corrupt,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_out_d_mem_3_opcode,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_out_d_mem_3_param,\t// @[LazyModuleImp.scala:107:25]\n input [3:0] auto_out_d_mem_3_size,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_out_d_mem_3_source,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_out_d_mem_3_sink,\t// @[LazyModuleImp.scala:107:25]\n input auto_out_d_mem_3_denied,\t// @[LazyModuleImp.scala:107:25]\n input [63:0] auto_out_d_mem_3_data,\t// @[LazyModuleImp.scala:107:25]\n input auto_out_d_mem_3_corrupt,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_out_d_mem_4_opcode,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_out_d_mem_4_param,\t// @[LazyModuleImp.scala:107:25]\n input [3:0] auto_out_d_mem_4_size,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_out_d_mem_4_source,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_out_d_mem_4_sink,\t// @[LazyModuleImp.scala:107:25]\n input auto_out_d_mem_4_denied,\t// @[LazyModuleImp.scala:107:25]\n input [63:0] auto_out_d_mem_4_data,\t// @[LazyModuleImp.scala:107:25]\n input auto_out_d_mem_4_corrupt,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_out_d_mem_5_opcode,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_out_d_mem_5_param,\t// @[LazyModuleImp.scala:107:25]\n input [3:0] auto_out_d_mem_5_size,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_out_d_mem_5_source,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_out_d_mem_5_sink,\t// @[LazyModuleImp.scala:107:25]\n input auto_out_d_mem_5_denied,\t// @[LazyModuleImp.scala:107:25]\n input [63:0] auto_out_d_mem_5_data,\t// @[LazyModuleImp.scala:107:25]\n input auto_out_d_mem_5_corrupt,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_out_d_mem_6_opcode,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_out_d_mem_6_param,\t// @[LazyModuleImp.scala:107:25]\n input [3:0] auto_out_d_mem_6_size,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_out_d_mem_6_source,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_out_d_mem_6_sink,\t// @[LazyModuleImp.scala:107:25]\n input auto_out_d_mem_6_denied,\t// @[LazyModuleImp.scala:107:25]\n input [63:0] auto_out_d_mem_6_data,\t// @[LazyModuleImp.scala:107:25]\n input auto_out_d_mem_6_corrupt,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_out_d_mem_7_opcode,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_out_d_mem_7_param,\t// @[LazyModuleImp.scala:107:25]\n input [3:0] auto_out_d_mem_7_size,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_out_d_mem_7_source,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_out_d_mem_7_sink,\t// @[LazyModuleImp.scala:107:25]\n input auto_out_d_mem_7_denied,\t// @[LazyModuleImp.scala:107:25]\n input [63:0] auto_out_d_mem_7_data,\t// @[LazyModuleImp.scala:107:25]\n input auto_out_d_mem_7_corrupt,\t// @[LazyModuleImp.scala:107:25]\n output [3:0] auto_out_d_ridx,\t// @[LazyModuleImp.scala:107:25]\n input [3:0] auto_out_d_widx,\t// @[LazyModuleImp.scala:107:25]\n output auto_out_d_safe_ridx_valid,\t// @[LazyModuleImp.scala:107:25]\n input auto_out_d_safe_widx_valid,\t// @[LazyModuleImp.scala:107:25]\n input auto_out_d_safe_source_reset_n,\t// @[LazyModuleImp.scala:107:25]\n output auto_out_d_safe_sink_reset_n,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_out_e_mem_0_sink,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_out_e_mem_1_sink,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_out_e_mem_2_sink,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_out_e_mem_3_sink,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_out_e_mem_4_sink,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_out_e_mem_5_sink,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_out_e_mem_6_sink,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_out_e_mem_7_sink,\t// @[LazyModuleImp.scala:107:25]\n input [3:0] auto_out_e_ridx,\t// @[LazyModuleImp.scala:107:25]\n output [3:0] auto_out_e_widx,\t// @[LazyModuleImp.scala:107:25]\n input auto_out_e_safe_ridx_valid,\t// @[LazyModuleImp.scala:107:25]\n output auto_out_e_safe_widx_valid,\t// @[LazyModuleImp.scala:107:25]\n output auto_out_e_safe_source_reset_n,\t// @[LazyModuleImp.scala:107:25]\n input auto_out_e_safe_sink_reset_n\t// @[LazyModuleImp.scala:107:25]\n);\n\n wire auto_in_a_valid_0 = auto_in_a_valid;\t// @[AsyncCrossing.scala:23:9]\n wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode;\t// @[AsyncCrossing.scala:23:9]\n wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param;\t// @[AsyncCrossing.scala:23:9]\n wire [3:0] auto_in_a_bits_size_0 = auto_in_a_bits_size;\t// @[AsyncCrossing.scala:23:9]\n wire [1:0] auto_in_a_bits_source_0 = auto_in_a_bits_source;\t// @[AsyncCrossing.scala:23:9]\n wire [31:0] auto_in_a_bits_address_0 = auto_in_a_bits_address;\t// @[AsyncCrossing.scala:23:9]\n wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask;\t// @[AsyncCrossing.scala:23:9]\n wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data;\t// @[AsyncCrossing.scala:23:9]\n wire auto_in_b_ready_0 = auto_in_b_ready;\t// @[AsyncCrossing.scala:23:9]\n wire auto_in_c_valid_0 = auto_in_c_valid;\t// @[AsyncCrossing.scala:23:9]\n wire [2:0] auto_in_c_bits_opcode_0 = auto_in_c_bits_opcode;\t// @[AsyncCrossing.scala:23:9]\n wire [2:0] auto_in_c_bits_param_0 = auto_in_c_bits_param;\t// @[AsyncCrossing.scala:23:9]\n wire [3:0] auto_in_c_bits_size_0 = auto_in_c_bits_size;\t// @[AsyncCrossing.scala:23:9]\n wire [1:0] auto_in_c_bits_source_0 = auto_in_c_bits_source;\t// @[AsyncCrossing.scala:23:9]\n wire [31:0] auto_in_c_bits_address_0 = auto_in_c_bits_address;\t// @[AsyncCrossing.scala:23:9]\n wire [63:0] auto_in_c_bits_data_0 = auto_in_c_bits_data;\t// @[AsyncCrossing.scala:23:9]\n wire auto_in_d_ready_0 = auto_in_d_ready;\t// @[AsyncCrossing.scala:23:9]\n wire auto_in_e_valid_0 = auto_in_e_valid;\t// @[AsyncCrossing.scala:23:9]\n wire [2:0] auto_in_e_bits_sink_0 = auto_in_e_bits_sink;\t// @[AsyncCrossing.scala:23:9]\n wire [3:0] auto_out_a_ridx_0 = auto_out_a_ridx;\t// @[AsyncCrossing.scala:23:9]\n wire auto_out_a_safe_ridx_valid_0 = auto_out_a_safe_ridx_valid;\t// @[AsyncCrossing.scala:23:9]\n wire auto_out_a_safe_sink_reset_n_0 = auto_out_a_safe_sink_reset_n;\t// @[AsyncCrossing.scala:23:9]\n wire [1:0] auto_out_b_mem_0_param_0 = auto_out_b_mem_0_param;\t// @[AsyncCrossing.scala:23:9]\n wire [31:0] auto_out_b_mem_0_address_0 = auto_out_b_mem_0_address;\t// @[AsyncCrossing.scala:23:9]\n wire [1:0] auto_out_b_mem_1_param_0 = auto_out_b_mem_1_param;\t// @[AsyncCrossing.scala:23:9]\n wire [31:0] auto_out_b_mem_1_address_0 = auto_out_b_mem_1_address;\t// @[AsyncCrossing.scala:23:9]\n wire [1:0] auto_out_b_mem_2_param_0 = auto_out_b_mem_2_param;\t// @[AsyncCrossing.scala:23:9]\n wire [31:0] auto_out_b_mem_2_address_0 = auto_out_b_mem_2_address;\t// @[AsyncCrossing.scala:23:9]\n wire [1:0] auto_out_b_mem_3_param_0 = auto_out_b_mem_3_param;\t// @[AsyncCrossing.scala:23:9]\n wire [31:0] auto_out_b_mem_3_address_0 = auto_out_b_mem_3_address;\t// @[AsyncCrossing.scala:23:9]\n wire [1:0] auto_out_b_mem_4_param_0 = auto_out_b_mem_4_param;\t// @[AsyncCrossing.scala:23:9]\n wire [31:0] auto_out_b_mem_4_address_0 = auto_out_b_mem_4_address;\t// @[AsyncCrossing.scala:23:9]\n wire [1:0] auto_out_b_mem_5_param_0 = auto_out_b_mem_5_param;\t// @[AsyncCrossing.scala:23:9]\n wire [31:0] auto_out_b_mem_5_address_0 = auto_out_b_mem_5_address;\t// @[AsyncCrossing.scala:23:9]\n wire [1:0] auto_out_b_mem_6_param_0 = auto_out_b_mem_6_param;\t// @[AsyncCrossing.scala:23:9]\n wire [31:0] auto_out_b_mem_6_address_0 = auto_out_b_mem_6_address;\t// @[AsyncCrossing.scala:23:9]\n wire [1:0] auto_out_b_mem_7_param_0 = auto_out_b_mem_7_param;\t// @[AsyncCrossing.scala:23:9]\n wire [31:0] auto_out_b_mem_7_address_0 = auto_out_b_mem_7_address;\t// @[AsyncCrossing.scala:23:9]\n wire [3:0] auto_out_b_widx_0 = auto_out_b_widx;\t// @[AsyncCrossing.scala:23:9]\n wire auto_out_b_safe_widx_valid_0 = auto_out_b_safe_widx_valid;\t// @[AsyncCrossing.scala:23:9]\n wire auto_out_b_safe_source_reset_n_0 = auto_out_b_safe_source_reset_n;\t// @[AsyncCrossing.scala:23:9]\n wire [3:0] auto_out_c_ridx_0 = auto_out_c_ridx;\t// @[AsyncCrossing.scala:23:9]\n wire auto_out_c_safe_ridx_valid_0 = auto_out_c_safe_ridx_valid;\t// @[AsyncCrossing.scala:23:9]\n wire auto_out_c_safe_sink_reset_n_0 = auto_out_c_safe_sink_reset_n;\t// @[AsyncCrossing.scala:23:9]\n wire [2:0] auto_out_d_mem_0_opcode_0 = auto_out_d_mem_0_opcode;\t// @[AsyncCrossing.scala:23:9]\n wire [1:0] auto_out_d_mem_0_param_0 = auto_out_d_mem_0_param;\t// @[AsyncCrossing.scala:23:9]\n wire [3:0] auto_out_d_mem_0_size_0 = auto_out_d_mem_0_size;\t// @[AsyncCrossing.scala:23:9]\n wire [1:0] auto_out_d_mem_0_source_0 = auto_out_d_mem_0_source;\t// @[AsyncCrossing.scala:23:9]\n wire [2:0] auto_out_d_mem_0_sink_0 = auto_out_d_mem_0_sink;\t// @[AsyncCrossing.scala:23:9]\n wire auto_out_d_mem_0_denied_0 = auto_out_d_mem_0_denied;\t// @[AsyncCrossing.scala:23:9]\n wire [63:0] auto_out_d_mem_0_data_0 = auto_out_d_mem_0_data;\t// @[AsyncCrossing.scala:23:9]\n wire auto_out_d_mem_0_corrupt_0 = auto_out_d_mem_0_corrupt;\t// @[AsyncCrossing.scala:23:9]\n wire [2:0] auto_out_d_mem_1_opcode_0 = auto_out_d_mem_1_opcode;\t// @[AsyncCrossing.scala:23:9]\n wire [1:0] auto_out_d_mem_1_param_0 = auto_out_d_mem_1_param;\t// @[AsyncCrossing.scala:23:9]\n wire [3:0] auto_out_d_mem_1_size_0 = auto_out_d_mem_1_size;\t// @[AsyncCrossing.scala:23:9]\n wire [1:0] auto_out_d_mem_1_source_0 = auto_out_d_mem_1_source;\t// @[AsyncCrossing.scala:23:9]\n wire [2:0] auto_out_d_mem_1_sink_0 = auto_out_d_mem_1_sink;\t// @[AsyncCrossing.scala:23:9]\n wire auto_out_d_mem_1_denied_0 = auto_out_d_mem_1_denied;\t// @[AsyncCrossing.scala:23:9]\n wire [63:0] auto_out_d_mem_1_data_0 = auto_out_d_mem_1_data;\t// @[AsyncCrossing.scala:23:9]\n wire auto_out_d_mem_1_corrupt_0 = auto_out_d_mem_1_corrupt;\t// @[AsyncCrossing.scala:23:9]\n wire [2:0] auto_out_d_mem_2_opcode_0 = auto_out_d_mem_2_opcode;\t// @[AsyncCrossing.scala:23:9]\n wire [1:0] auto_out_d_mem_2_param_0 = auto_out_d_mem_2_param;\t// @[AsyncCrossing.scala:23:9]\n wire [3:0] auto_out_d_mem_2_size_0 = auto_out_d_mem_2_size;\t// @[AsyncCrossing.scala:23:9]\n wire [1:0] auto_out_d_mem_2_source_0 = auto_out_d_mem_2_source;\t// @[AsyncCrossing.scala:23:9]\n wire [2:0] auto_out_d_mem_2_sink_0 = auto_out_d_mem_2_sink;\t// @[AsyncCrossing.scala:23:9]\n wire auto_out_d_mem_2_denied_0 = auto_out_d_mem_2_denied;\t// @[AsyncCrossing.scala:23:9]\n wire [63:0] auto_out_d_mem_2_data_0 = auto_out_d_mem_2_data;\t// @[AsyncCrossing.scala:23:9]\n wire auto_out_d_mem_2_corrupt_0 = auto_out_d_mem_2_corrupt;\t// @[AsyncCrossing.scala:23:9]\n wire [2:0] auto_out_d_mem_3_opcode_0 = auto_out_d_mem_3_opcode;\t// @[AsyncCrossing.scala:23:9]\n wire [1:0] auto_out_d_mem_3_param_0 = auto_out_d_mem_3_param;\t// @[AsyncCrossing.scala:23:9]\n wire [3:0] auto_out_d_mem_3_size_0 = auto_out_d_mem_3_size;\t// @[AsyncCrossing.scala:23:9]\n wire [1:0] auto_out_d_mem_3_source_0 = auto_out_d_mem_3_source;\t// @[AsyncCrossing.scala:23:9]\n wire [2:0] auto_out_d_mem_3_sink_0 = auto_out_d_mem_3_sink;\t// @[AsyncCrossing.scala:23:9]\n wire auto_out_d_mem_3_denied_0 = auto_out_d_mem_3_denied;\t// @[AsyncCrossing.scala:23:9]\n wire [63:0] auto_out_d_mem_3_data_0 = auto_out_d_mem_3_data;\t// @[AsyncCrossing.scala:23:9]\n wire auto_out_d_mem_3_corrupt_0 = auto_out_d_mem_3_corrupt;\t// @[AsyncCrossing.scala:23:9]\n wire [2:0] auto_out_d_mem_4_opcode_0 = auto_out_d_mem_4_opcode;\t// @[AsyncCrossing.scala:23:9]\n wire [1:0] auto_out_d_mem_4_param_0 = auto_out_d_mem_4_param;\t// @[AsyncCrossing.scala:23:9]\n wire [3:0] auto_out_d_mem_4_size_0 = auto_out_d_mem_4_size;\t// @[AsyncCrossing.scala:23:9]\n wire [1:0] auto_out_d_mem_4_source_0 = auto_out_d_mem_4_source;\t// @[AsyncCrossing.scala:23:9]\n wire [2:0] auto_out_d_mem_4_sink_0 = auto_out_d_mem_4_sink;\t// @[AsyncCrossing.scala:23:9]\n wire auto_out_d_mem_4_denied_0 = auto_out_d_mem_4_denied;\t// @[AsyncCrossing.scala:23:9]\n wire [63:0] auto_out_d_mem_4_data_0 = auto_out_d_mem_4_data;\t// @[AsyncCrossing.scala:23:9]\n wire auto_out_d_mem_4_corrupt_0 = auto_out_d_mem_4_corrupt;\t// @[AsyncCrossing.scala:23:9]\n wire [2:0] auto_out_d_mem_5_opcode_0 = auto_out_d_mem_5_opcode;\t// @[AsyncCrossing.scala:23:9]\n wire [1:0] auto_out_d_mem_5_param_0 = auto_out_d_mem_5_param;\t// @[AsyncCrossing.scala:23:9]\n wire [3:0] auto_out_d_mem_5_size_0 = auto_out_d_mem_5_size;\t// @[AsyncCrossing.scala:23:9]\n wire [1:0] auto_out_d_mem_5_source_0 = auto_out_d_mem_5_source;\t// @[AsyncCrossing.scala:23:9]\n wire [2:0] auto_out_d_mem_5_sink_0 = auto_out_d_mem_5_sink;\t// @[AsyncCrossing.scala:23:9]\n wire auto_out_d_mem_5_denied_0 = auto_out_d_mem_5_denied;\t// @[AsyncCrossing.scala:23:9]\n wire [63:0] auto_out_d_mem_5_data_0 = auto_out_d_mem_5_data;\t// @[AsyncCrossing.scala:23:9]\n wire auto_out_d_mem_5_corrupt_0 = auto_out_d_mem_5_corrupt;\t// @[AsyncCrossing.scala:23:9]\n wire [2:0] auto_out_d_mem_6_opcode_0 = auto_out_d_mem_6_opcode;\t// @[AsyncCrossing.scala:23:9]\n wire [1:0] auto_out_d_mem_6_param_0 = auto_out_d_mem_6_param;\t// @[AsyncCrossing.scala:23:9]\n wire [3:0] auto_out_d_mem_6_size_0 = auto_out_d_mem_6_size;\t// @[AsyncCrossing.scala:23:9]\n wire [1:0] auto_out_d_mem_6_source_0 = auto_out_d_mem_6_source;\t// @[AsyncCrossing.scala:23:9]\n wire [2:0] auto_out_d_mem_6_sink_0 = auto_out_d_mem_6_sink;\t// @[AsyncCrossing.scala:23:9]\n wire auto_out_d_mem_6_denied_0 = auto_out_d_mem_6_denied;\t// @[AsyncCrossing.scala:23:9]\n wire [63:0] auto_out_d_mem_6_data_0 = auto_out_d_mem_6_data;\t// @[AsyncCrossing.scala:23:9]\n wire auto_out_d_mem_6_corrupt_0 = auto_out_d_mem_6_corrupt;\t// @[AsyncCrossing.scala:23:9]\n wire [2:0] auto_out_d_mem_7_opcode_0 = auto_out_d_mem_7_opcode;\t// @[AsyncCrossing.scala:23:9]\n wire [1:0] auto_out_d_mem_7_param_0 = auto_out_d_mem_7_param;\t// @[AsyncCrossing.scala:23:9]\n wire [3:0] auto_out_d_mem_7_size_0 = auto_out_d_mem_7_size;\t// @[AsyncCrossing.scala:23:9]\n wire [1:0] auto_out_d_mem_7_source_0 = auto_out_d_mem_7_source;\t// @[AsyncCrossing.scala:23:9]\n wire [2:0] auto_out_d_mem_7_sink_0 = auto_out_d_mem_7_sink;\t// @[AsyncCrossing.scala:23:9]\n wire auto_out_d_mem_7_denied_0 = auto_out_d_mem_7_denied;\t// @[AsyncCrossing.scala:23:9]\n wire [63:0] auto_out_d_mem_7_data_0 = auto_out_d_mem_7_data;\t// @[AsyncCrossing.scala:23:9]\n wire auto_out_d_mem_7_corrupt_0 = auto_out_d_mem_7_corrupt;\t// @[AsyncCrossing.scala:23:9]\n wire [3:0] auto_out_d_widx_0 = auto_out_d_widx;\t// @[AsyncCrossing.scala:23:9]\n wire auto_out_d_safe_widx_valid_0 = auto_out_d_safe_widx_valid;\t// @[AsyncCrossing.scala:23:9]\n wire auto_out_d_safe_source_reset_n_0 = auto_out_d_safe_source_reset_n;\t// @[AsyncCrossing.scala:23:9]\n wire [3:0] auto_out_e_ridx_0 = auto_out_e_ridx;\t// @[AsyncCrossing.scala:23:9]\n wire auto_out_e_safe_ridx_valid_0 = auto_out_e_safe_ridx_valid;\t// @[AsyncCrossing.scala:23:9]\n wire auto_out_e_safe_sink_reset_n_0 = auto_out_e_safe_sink_reset_n;\t// @[AsyncCrossing.scala:23:9]\n wire [63:0] auto_out_b_mem_0_data = 64'h0;\t// @[AsyncQueue.scala:211:22]\n wire [63:0] auto_out_b_mem_1_data = 64'h0;\t// @[AsyncQueue.scala:211:22]\n wire [63:0] auto_out_b_mem_2_data = 64'h0;\t// @[AsyncQueue.scala:211:22]\n wire [63:0] auto_out_b_mem_3_data = 64'h0;\t// @[AsyncQueue.scala:211:22]\n wire [63:0] auto_out_b_mem_4_data = 64'h0;\t// @[AsyncQueue.scala:211:22]\n wire [63:0] auto_out_b_mem_5_data = 64'h0;\t// @[AsyncQueue.scala:211:22]\n wire [63:0] auto_out_b_mem_6_data = 64'h0;\t// @[AsyncQueue.scala:211:22]\n wire [63:0] auto_out_b_mem_7_data = 64'h0;\t// @[AsyncQueue.scala:211:22]\n wire [63:0] nodeOut_b_mem_0_data = 64'h0;\t// @[AsyncQueue.scala:211:22]\n wire [63:0] nodeOut_b_mem_1_data = 64'h0;\t// @[AsyncQueue.scala:211:22]\n wire [63:0] nodeOut_b_mem_2_data = 64'h0;\t// @[AsyncQueue.scala:211:22]\n wire [63:0] nodeOut_b_mem_3_data = 64'h0;\t// @[AsyncQueue.scala:211:22]\n wire [63:0] nodeOut_b_mem_4_data = 64'h0;\t// @[AsyncQueue.scala:211:22]\n wire [63:0] nodeOut_b_mem_5_data = 64'h0;\t// @[AsyncQueue.scala:211:22]\n wire [63:0] nodeOut_b_mem_6_data = 64'h0;\t// @[AsyncQueue.scala:211:22]\n wire [63:0] nodeOut_b_mem_7_data = 64'h0;\t// @[AsyncQueue.scala:211:22]\n wire [7:0] auto_out_b_mem_0_mask = 8'hFF;\t// @[AsyncQueue.scala:211:22]\n wire [7:0] auto_out_b_mem_1_mask = 8'hFF;\t// @[AsyncQueue.scala:211:22]\n wire [7:0] auto_out_b_mem_2_mask = 8'hFF;\t// @[AsyncQueue.scala:211:22]\n wire [7:0] auto_out_b_mem_3_mask = 8'hFF;\t// @[AsyncQueue.scala:211:22]\n wire [7:0] auto_out_b_mem_4_mask = 8'hFF;\t// @[AsyncQueue.scala:211:22]\n wire [7:0] auto_out_b_mem_5_mask = 8'hFF;\t// @[AsyncQueue.scala:211:22]\n wire [7:0] auto_out_b_mem_6_mask = 8'hFF;\t// @[AsyncQueue.scala:211:22]\n wire [7:0] auto_out_b_mem_7_mask = 8'hFF;\t// @[AsyncQueue.scala:211:22]\n wire [7:0] nodeOut_b_mem_0_mask = 8'hFF;\t// @[AsyncQueue.scala:211:22]\n wire [7:0] nodeOut_b_mem_1_mask = 8'hFF;\t// @[AsyncQueue.scala:211:22]\n wire [7:0] nodeOut_b_mem_2_mask = 8'hFF;\t// @[AsyncQueue.scala:211:22]\n wire [7:0] nodeOut_b_mem_3_mask = 8'hFF;\t// @[AsyncQueue.scala:211:22]\n wire [7:0] nodeOut_b_mem_4_mask = 8'hFF;\t// @[AsyncQueue.scala:211:22]\n wire [7:0] nodeOut_b_mem_5_mask = 8'hFF;\t// @[AsyncQueue.scala:211:22]\n wire [7:0] nodeOut_b_mem_6_mask = 8'hFF;\t// @[AsyncQueue.scala:211:22]\n wire [7:0] nodeOut_b_mem_7_mask = 8'hFF;\t// @[AsyncQueue.scala:211:22]\n wire [1:0] auto_out_b_mem_0_source = 2'h0;\t// @[AsyncQueue.scala:211:22]\n wire [1:0] auto_out_b_mem_1_source = 2'h0;\t// @[AsyncQueue.scala:211:22]\n wire [1:0] auto_out_b_mem_2_source = 2'h0;\t// @[AsyncQueue.scala:211:22]\n wire [1:0] auto_out_b_mem_3_source = 2'h0;\t// @[AsyncQueue.scala:211:22]\n wire [1:0] auto_out_b_mem_4_source = 2'h0;\t// @[AsyncQueue.scala:211:22]\n wire [1:0] auto_out_b_mem_5_source = 2'h0;\t// @[AsyncQueue.scala:211:22]\n wire [1:0] auto_out_b_mem_6_source = 2'h0;\t// @[AsyncQueue.scala:211:22]\n wire [1:0] auto_out_b_mem_7_source = 2'h0;\t// @[AsyncQueue.scala:211:22]\n wire [1:0] nodeOut_b_mem_0_source = 2'h0;\t// @[AsyncQueue.scala:211:22]\n wire [1:0] nodeOut_b_mem_1_source = 2'h0;\t// @[AsyncQueue.scala:211:22]\n wire [1:0] nodeOut_b_mem_2_source = 2'h0;\t// @[AsyncQueue.scala:211:22]\n wire [1:0] nodeOut_b_mem_3_source = 2'h0;\t// @[AsyncQueue.scala:211:22]\n wire [1:0] nodeOut_b_mem_4_source = 2'h0;\t// @[AsyncQueue.scala:211:22]\n wire [1:0] nodeOut_b_mem_5_source = 2'h0;\t// @[AsyncQueue.scala:211:22]\n wire [1:0] nodeOut_b_mem_6_source = 2'h0;\t// @[AsyncQueue.scala:211:22]\n wire [1:0] nodeOut_b_mem_7_source = 2'h0;\t// @[AsyncQueue.scala:211:22]\n wire [3:0] auto_out_b_mem_0_size = 4'h6;\t// @[AsyncQueue.scala:211:22]\n wire [3:0] auto_out_b_mem_1_size = 4'h6;\t// @[AsyncQueue.scala:211:22]\n wire [3:0] auto_out_b_mem_2_size = 4'h6;\t// @[AsyncQueue.scala:211:22]\n wire [3:0] auto_out_b_mem_3_size = 4'h6;\t// @[AsyncQueue.scala:211:22]\n wire [3:0] auto_out_b_mem_4_size = 4'h6;\t// @[AsyncQueue.scala:211:22]\n wire [3:0] auto_out_b_mem_5_size = 4'h6;\t// @[AsyncQueue.scala:211:22]\n wire [3:0] auto_out_b_mem_6_size = 4'h6;\t// @[AsyncQueue.scala:211:22]\n wire [3:0] auto_out_b_mem_7_size = 4'h6;\t// @[AsyncQueue.scala:211:22]\n wire [3:0] nodeOut_b_mem_0_size = 4'h6;\t// @[AsyncQueue.scala:211:22]\n wire [3:0] nodeOut_b_mem_1_size = 4'h6;\t// @[AsyncQueue.scala:211:22]\n wire [3:0] nodeOut_b_mem_2_size = 4'h6;\t// @[AsyncQueue.scala:211:22]\n wire [3:0] nodeOut_b_mem_3_size = 4'h6;\t// @[AsyncQueue.scala:211:22]\n wire [3:0] nodeOut_b_mem_4_size = 4'h6;\t// @[AsyncQueue.scala:211:22]\n wire [3:0] nodeOut_b_mem_5_size = 4'h6;\t// @[AsyncQueue.scala:211:22]\n wire [3:0] nodeOut_b_mem_6_size = 4'h6;\t// @[AsyncQueue.scala:211:22]\n wire [3:0] nodeOut_b_mem_7_size = 4'h6;\t// @[AsyncQueue.scala:211:22]\n wire [2:0] auto_out_b_mem_0_opcode = 3'h6;\t// @[AsyncQueue.scala:211:22]\n wire [2:0] auto_out_b_mem_1_opcode = 3'h6;\t// @[AsyncQueue.scala:211:22]\n wire [2:0] auto_out_b_mem_2_opcode = 3'h6;\t// @[AsyncQueue.scala:211:22]\n wire [2:0] auto_out_b_mem_3_opcode = 3'h6;\t// @[AsyncQueue.scala:211:22]\n wire [2:0] auto_out_b_mem_4_opcode = 3'h6;\t// @[AsyncQueue.scala:211:22]\n wire [2:0] auto_out_b_mem_5_opcode = 3'h6;\t// @[AsyncQueue.scala:211:22]\n wire [2:0] auto_out_b_mem_6_opcode = 3'h6;\t// @[AsyncQueue.scala:211:22]\n wire [2:0] auto_out_b_mem_7_opcode = 3'h6;\t// @[AsyncQueue.scala:211:22]\n wire [2:0] nodeOut_b_mem_0_opcode = 3'h6;\t// @[AsyncQueue.scala:211:22]\n wire [2:0] nodeOut_b_mem_1_opcode = 3'h6;\t// @[AsyncQueue.scala:211:22]\n wire [2:0] nodeOut_b_mem_2_opcode = 3'h6;\t// @[AsyncQueue.scala:211:22]\n wire [2:0] nodeOut_b_mem_3_opcode = 3'h6;\t// @[AsyncQueue.scala:211:22]\n wire [2:0] nodeOut_b_mem_4_opcode = 3'h6;\t// @[AsyncQueue.scala:211:22]\n wire [2:0] nodeOut_b_mem_5_opcode = 3'h6;\t// @[AsyncQueue.scala:211:22]\n wire [2:0] nodeOut_b_mem_6_opcode = 3'h6;\t// @[AsyncQueue.scala:211:22]\n wire [2:0] nodeOut_b_mem_7_opcode = 3'h6;\t// @[AsyncQueue.scala:211:22]\n wire auto_in_a_bits_corrupt = 1'h0;\t// @[AsyncCrossing.scala:23:9]\n wire auto_in_c_bits_corrupt = 1'h0;\t// @[AsyncCrossing.scala:23:9]\n wire auto_out_a_mem_0_corrupt = 1'h0;\t// @[AsyncCrossing.scala:23:9]\n wire auto_out_a_mem_1_corrupt = 1'h0;\t// @[AsyncCrossing.scala:23:9]\n wire auto_out_a_mem_2_corrupt = 1'h0;\t// @[AsyncCrossing.scala:23:9]\n wire auto_out_a_mem_3_corrupt = 1'h0;\t// @[AsyncCrossing.scala:23:9]\n wire auto_out_a_mem_4_corrupt = 1'h0;\t// @[AsyncCrossing.scala:23:9]\n wire auto_out_a_mem_5_corrupt = 1'h0;\t// @[AsyncCrossing.scala:23:9]\n wire auto_out_a_mem_6_corrupt = 1'h0;\t// @[AsyncCrossing.scala:23:9]\n wire auto_out_a_mem_7_corrupt = 1'h0;\t// @[AsyncCrossing.scala:23:9]\n wire auto_out_b_mem_0_corrupt = 1'h0;\t// @[AsyncCrossing.scala:23:9]\n wire auto_out_b_mem_1_corrupt = 1'h0;\t// @[AsyncCrossing.scala:23:9]\n wire auto_out_b_mem_2_corrupt = 1'h0;\t// @[AsyncCrossing.scala:23:9]\n wire auto_out_b_mem_3_corrupt = 1'h0;\t// @[AsyncCrossing.scala:23:9]\n wire auto_out_b_mem_4_corrupt = 1'h0;\t// @[AsyncCrossing.scala:23:9]\n wire auto_out_b_mem_5_corrupt = 1'h0;\t// @[AsyncCrossing.scala:23:9]\n wire auto_out_b_mem_6_corrupt = 1'h0;\t// @[AsyncCrossing.scala:23:9]\n wire auto_out_b_mem_7_corrupt = 1'h0;\t// @[AsyncCrossing.scala:23:9]\n wire auto_out_c_mem_0_corrupt = 1'h0;\t// @[AsyncCrossing.scala:23:9]\n wire auto_out_c_mem_1_corrupt = 1'h0;\t// @[AsyncCrossing.scala:23:9]\n wire auto_out_c_mem_2_corrupt = 1'h0;\t// @[AsyncCrossing.scala:23:9]\n wire auto_out_c_mem_3_corrupt = 1'h0;\t// @[AsyncCrossing.scala:23:9]\n wire auto_out_c_mem_4_corrupt = 1'h0;\t// @[AsyncCrossing.scala:23:9]\n wire auto_out_c_mem_5_corrupt = 1'h0;\t// @[AsyncCrossing.scala:23:9]\n wire auto_out_c_mem_6_corrupt = 1'h0;\t// @[AsyncCrossing.scala:23:9]\n wire auto_out_c_mem_7_corrupt = 1'h0;\t// @[AsyncCrossing.scala:23:9]\n wire nodeIn_a_ready;\t// @[MixedNode.scala:551:17]\n wire nodeIn_a_bits_corrupt = 1'h0;\t// @[MixedNode.scala:551:17]\n wire nodeIn_c_bits_corrupt = 1'h0;\t// @[MixedNode.scala:551:17]\n wire nodeOut_a_mem_0_corrupt = 1'h0;\t// @[MixedNode.scala:542:17]\n wire nodeOut_a_mem_1_corrupt = 1'h0;\t// @[MixedNode.scala:542:17]\n wire nodeOut_a_mem_2_corrupt = 1'h0;\t// @[MixedNode.scala:542:17]\n wire nodeOut_a_mem_3_corrupt = 1'h0;\t// @[MixedNode.scala:542:17]\n wire nodeOut_a_mem_4_corrupt = 1'h0;\t// @[MixedNode.scala:542:17]\n wire nodeOut_a_mem_5_corrupt = 1'h0;\t// @[MixedNode.scala:542:17]\n wire nodeOut_a_mem_6_corrupt = 1'h0;\t// @[MixedNode.scala:542:17]\n wire nodeOut_a_mem_7_corrupt = 1'h0;\t// @[MixedNode.scala:542:17]\n wire nodeOut_b_mem_0_corrupt = 1'h0;\t// @[MixedNode.scala:542:17]\n wire nodeOut_b_mem_1_corrupt = 1'h0;\t// @[MixedNode.scala:542:17]\n wire nodeOut_b_mem_2_corrupt = 1'h0;\t// @[MixedNode.scala:542:17]\n wire nodeOut_b_mem_3_corrupt = 1'h0;\t// @[MixedNode.scala:542:17]\n wire nodeOut_b_mem_4_corrupt = 1'h0;\t// @[MixedNode.scala:542:17]\n wire nodeOut_b_mem_5_corrupt = 1'h0;\t// @[MixedNode.scala:542:17]\n wire nodeOut_b_mem_6_corrupt = 1'h0;\t// @[MixedNode.scala:542:17]\n wire nodeOut_b_mem_7_corrupt = 1'h0;\t// @[MixedNode.scala:542:17]\n wire nodeOut_c_mem_0_corrupt = 1'h0;\t// @[MixedNode.scala:542:17]\n wire nodeOut_c_mem_1_corrupt = 1'h0;\t// @[MixedNode.scala:542:17]\n wire nodeOut_c_mem_2_corrupt = 1'h0;\t// @[MixedNode.scala:542:17]\n wire nodeOut_c_mem_3_corrupt = 1'h0;\t// @[MixedNode.scala:542:17]\n wire nodeOut_c_mem_4_corrupt = 1'h0;\t// @[MixedNode.scala:542:17]\n wire nodeOut_c_mem_5_corrupt = 1'h0;\t// @[MixedNode.scala:542:17]\n wire nodeOut_c_mem_6_corrupt = 1'h0;\t// @[MixedNode.scala:542:17]\n wire nodeOut_c_mem_7_corrupt = 1'h0;\t// @[MixedNode.scala:542:17]\n wire nodeIn_a_valid = auto_in_a_valid_0;\t// @[AsyncCrossing.scala:23:9]\n wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0;\t// @[AsyncCrossing.scala:23:9]\n wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0;\t// @[AsyncCrossing.scala:23:9]\n wire [3:0] nodeIn_a_bits_size = auto_in_a_bits_size_0;\t// @[AsyncCrossing.scala:23:9]\n wire [1:0] nodeIn_a_bits_source = auto_in_a_bits_source_0;\t// @[AsyncCrossing.scala:23:9]\n wire [31:0] nodeIn_a_bits_address = auto_in_a_bits_address_0;\t// @[AsyncCrossing.scala:23:9]\n wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0;\t// @[AsyncCrossing.scala:23:9]\n wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0;\t// @[AsyncCrossing.scala:23:9]\n wire nodeIn_b_ready = auto_in_b_ready_0;\t// @[AsyncCrossing.scala:23:9]\n wire nodeIn_b_valid;\t// @[MixedNode.scala:551:17]\n wire [2:0] nodeIn_b_bits_opcode;\t// @[MixedNode.scala:551:17]\n wire [1:0] nodeIn_b_bits_param;\t// @[MixedNode.scala:551:17]\n wire [3:0] nodeIn_b_bits_size;\t// @[MixedNode.scala:551:17]\n wire [1:0] nodeIn_b_bits_source;\t// @[MixedNode.scala:551:17]\n wire [31:0] nodeIn_b_bits_address;\t// @[MixedNode.scala:551:17]\n wire [7:0] nodeIn_b_bits_mask;\t// @[MixedNode.scala:551:17]\n wire [63:0] nodeIn_b_bits_data;\t// @[MixedNode.scala:551:17]\n wire nodeIn_b_bits_corrupt;\t// @[MixedNode.scala:551:17]\n wire nodeIn_c_ready;\t// @[MixedNode.scala:551:17]\n wire nodeIn_c_valid = auto_in_c_valid_0;\t// @[AsyncCrossing.scala:23:9]\n wire [2:0] nodeIn_c_bits_opcode = auto_in_c_bits_opcode_0;\t// @[AsyncCrossing.scala:23:9]\n wire [2:0] nodeIn_c_bits_param = auto_in_c_bits_param_0;\t// @[AsyncCrossing.scala:23:9]\n wire [3:0] nodeIn_c_bits_size = auto_in_c_bits_size_0;\t// @[AsyncCrossing.scala:23:9]\n wire [1:0] nodeIn_c_bits_source = auto_in_c_bits_source_0;\t// @[AsyncCrossing.scala:23:9]\n wire [31:0] nodeIn_c_bits_address = auto_in_c_bits_address_0;\t// @[AsyncCrossing.scala:23:9]\n wire [63:0] nodeIn_c_bits_data = auto_in_c_bits_data_0;\t// @[AsyncCrossing.scala:23:9]\n wire nodeIn_d_ready = auto_in_d_ready_0;\t// @[AsyncCrossing.scala:23:9]\n wire nodeIn_d_valid;\t// @[MixedNode.scala:551:17]\n wire [2:0] nodeIn_d_bits_opcode;\t// @[MixedNode.scala:551:17]\n wire [1:0] nodeIn_d_bits_param;\t// @[MixedNode.scala:551:17]\n wire [3:0] nodeIn_d_bits_size;\t// @[MixedNode.scala:551:17]\n wire [1:0] nodeIn_d_bits_source;\t// @[MixedNode.scala:551:17]\n wire [2:0] nodeIn_d_bits_sink;\t// @[MixedNode.scala:551:17]\n wire nodeIn_d_bits_denied;\t// @[MixedNode.scala:551:17]\n wire [63:0] nodeIn_d_bits_data;\t// @[MixedNode.scala:551:17]\n wire nodeIn_d_bits_corrupt;\t// @[MixedNode.scala:551:17]\n wire nodeIn_e_ready;\t// @[MixedNode.scala:551:17]\n wire nodeIn_e_valid = auto_in_e_valid_0;\t// @[AsyncCrossing.scala:23:9]\n wire [2:0] nodeIn_e_bits_sink = auto_in_e_bits_sink_0;\t// @[AsyncCrossing.scala:23:9]\n wire [2:0] nodeOut_a_mem_0_opcode;\t// @[MixedNode.scala:542:17]\n wire [2:0] nodeOut_a_mem_0_param;\t// @[MixedNode.scala:542:17]\n wire [3:0] nodeOut_a_mem_0_size;\t// @[MixedNode.scala:542:17]\n wire [1:0] nodeOut_a_mem_0_source;\t// @[MixedNode.scala:542:17]\n wire [31:0] nodeOut_a_mem_0_address;\t// @[MixedNode.scala:542:17]\n wire [7:0] nodeOut_a_mem_0_mask;\t// @[MixedNode.scala:542:17]\n wire [63:0] nodeOut_a_mem_0_data;\t// @[MixedNode.scala:542:17]\n wire [2:0] nodeOut_a_mem_1_opcode;\t// @[MixedNode.scala:542:17]\n wire [2:0] nodeOut_a_mem_1_param;\t// @[MixedNode.scala:542:17]\n wire [3:0] nodeOut_a_mem_1_size;\t// @[MixedNode.scala:542:17]\n wire [1:0] nodeOut_a_mem_1_source;\t// @[MixedNode.scala:542:17]\n wire [31:0] nodeOut_a_mem_1_address;\t// @[MixedNode.scala:542:17]\n wire [7:0] nodeOut_a_mem_1_mask;\t// @[MixedNode.scala:542:17]\n wire [63:0] nodeOut_a_mem_1_data;\t// @[MixedNode.scala:542:17]\n wire [2:0] nodeOut_a_mem_2_opcode;\t// @[MixedNode.scala:542:17]\n wire [2:0] nodeOut_a_mem_2_param;\t// @[MixedNode.scala:542:17]\n wire [3:0] nodeOut_a_mem_2_size;\t// @[MixedNode.scala:542:17]\n wire [1:0] nodeOut_a_mem_2_source;\t// @[MixedNode.scala:542:17]\n wire [31:0] nodeOut_a_mem_2_address;\t// @[MixedNode.scala:542:17]\n wire [7:0] nodeOut_a_mem_2_mask;\t// @[MixedNode.scala:542:17]\n wire [63:0] nodeOut_a_mem_2_data;\t// @[MixedNode.scala:542:17]\n wire [2:0] nodeOut_a_mem_3_opcode;\t// @[MixedNode.scala:542:17]\n wire [2:0] nodeOut_a_mem_3_param;\t// @[MixedNode.scala:542:17]\n wire [3:0] nodeOut_a_mem_3_size;\t// @[MixedNode.scala:542:17]\n wire [1:0] nodeOut_a_mem_3_source;\t// @[MixedNode.scala:542:17]\n wire [31:0] nodeOut_a_mem_3_address;\t// @[MixedNode.scala:542:17]\n wire [7:0] nodeOut_a_mem_3_mask;\t// @[MixedNode.scala:542:17]\n wire [63:0] nodeOut_a_mem_3_data;\t// @[MixedNode.scala:542:17]\n wire [2:0] nodeOut_a_mem_4_opcode;\t// @[MixedNode.scala:542:17]\n wire [2:0] nodeOut_a_mem_4_param;\t// @[MixedNode.scala:542:17]\n wire [3:0] nodeOut_a_mem_4_size;\t// @[MixedNode.scala:542:17]\n wire [1:0] nodeOut_a_mem_4_source;\t// @[MixedNode.scala:542:17]\n wire [31:0] nodeOut_a_mem_4_address;\t// @[MixedNode.scala:542:17]\n wire [7:0] nodeOut_a_mem_4_mask;\t// @[MixedNode.scala:542:17]\n wire [63:0] nodeOut_a_mem_4_data;\t// @[MixedNode.scala:542:17]\n wire [2:0] nodeOut_a_mem_5_opcode;\t// @[MixedNode.scala:542:17]\n wire [2:0] nodeOut_a_mem_5_param;\t// @[MixedNode.scala:542:17]\n wire [3:0] nodeOut_a_mem_5_size;\t// @[MixedNode.scala:542:17]\n wire [1:0] nodeOut_a_mem_5_source;\t// @[MixedNode.scala:542:17]\n wire [31:0] nodeOut_a_mem_5_address;\t// @[MixedNode.scala:542:17]\n wire [7:0] nodeOut_a_mem_5_mask;\t// @[MixedNode.scala:542:17]\n wire [63:0] nodeOut_a_mem_5_data;\t// @[MixedNode.scala:542:17]\n wire [2:0] nodeOut_a_mem_6_opcode;\t// @[MixedNode.scala:542:17]\n wire [2:0] nodeOut_a_mem_6_param;\t// @[MixedNode.scala:542:17]\n wire [3:0] nodeOut_a_mem_6_size;\t// @[MixedNode.scala:542:17]\n wire [1:0] nodeOut_a_mem_6_source;\t// @[MixedNode.scala:542:17]\n wire [31:0] nodeOut_a_mem_6_address;\t// @[MixedNode.scala:542:17]\n wire [7:0] nodeOut_a_mem_6_mask;\t// @[MixedNode.scala:542:17]\n wire [63:0] nodeOut_a_mem_6_data;\t// @[MixedNode.scala:542:17]\n wire [2:0] nodeOut_a_mem_7_opcode;\t// @[MixedNode.scala:542:17]\n wire [2:0] nodeOut_a_mem_7_param;\t// @[MixedNode.scala:542:17]\n wire [3:0] nodeOut_a_mem_7_size;\t// @[MixedNode.scala:542:17]\n wire [1:0] nodeOut_a_mem_7_source;\t// @[MixedNode.scala:542:17]\n wire [31:0] nodeOut_a_mem_7_address;\t// @[MixedNode.scala:542:17]\n wire [7:0] nodeOut_a_mem_7_mask;\t// @[MixedNode.scala:542:17]\n wire [63:0] nodeOut_a_mem_7_data;\t// @[MixedNode.scala:542:17]\n wire [3:0] nodeOut_a_ridx = auto_out_a_ridx_0;\t// @[AsyncCrossing.scala:23:9]\n wire [3:0] nodeOut_a_widx;\t// @[MixedNode.scala:542:17]\n wire nodeOut_a_safe_ridx_valid = auto_out_a_safe_ridx_valid_0;\t// @[AsyncCrossing.scala:23:9]\n wire nodeOut_a_safe_widx_valid;\t// @[MixedNode.scala:542:17]\n wire nodeOut_a_safe_source_reset_n;\t// @[MixedNode.scala:542:17]\n wire nodeOut_a_safe_sink_reset_n = auto_out_a_safe_sink_reset_n_0;\t// @[AsyncCrossing.scala:23:9]\n wire [1:0] nodeOut_b_mem_0_param = auto_out_b_mem_0_param_0;\t// @[AsyncCrossing.scala:23:9]\n wire [31:0] nodeOut_b_mem_0_address = auto_out_b_mem_0_address_0;\t// @[AsyncCrossing.scala:23:9]\n wire [1:0] nodeOut_b_mem_1_param = auto_out_b_mem_1_param_0;\t// @[AsyncCrossing.scala:23:9]\n wire [31:0] nodeOut_b_mem_1_address = auto_out_b_mem_1_address_0;\t// @[AsyncCrossing.scala:23:9]\n wire [1:0] nodeOut_b_mem_2_param = auto_out_b_mem_2_param_0;\t// @[AsyncCrossing.scala:23:9]\n wire [31:0] nodeOut_b_mem_2_address = auto_out_b_mem_2_address_0;\t// @[AsyncCrossing.scala:23:9]\n wire [1:0] nodeOut_b_mem_3_param = auto_out_b_mem_3_param_0;\t// @[AsyncCrossing.scala:23:9]\n wire [31:0] nodeOut_b_mem_3_address = auto_out_b_mem_3_address_0;\t// @[AsyncCrossing.scala:23:9]\n wire [1:0] nodeOut_b_mem_4_param = auto_out_b_mem_4_param_0;\t// @[AsyncCrossing.scala:23:9]\n wire [31:0] nodeOut_b_mem_4_address = auto_out_b_mem_4_address_0;\t// @[AsyncCrossing.scala:23:9]\n wire [1:0] nodeOut_b_mem_5_param = auto_out_b_mem_5_param_0;\t// @[AsyncCrossing.scala:23:9]\n wire [31:0] nodeOut_b_mem_5_address = auto_out_b_mem_5_address_0;\t// @[AsyncCrossing.scala:23:9]\n wire [1:0] nodeOut_b_mem_6_param = auto_out_b_mem_6_param_0;\t// @[AsyncCrossing.scala:23:9]\n wire [31:0] nodeOut_b_mem_6_address = auto_out_b_mem_6_address_0;\t// @[AsyncCrossing.scala:23:9]\n wire [1:0] nodeOut_b_mem_7_param = auto_out_b_mem_7_param_0;\t// @[AsyncCrossing.scala:23:9]\n wire [31:0] nodeOut_b_mem_7_address = auto_out_b_mem_7_address_0;\t// @[AsyncCrossing.scala:23:9]\n wire [3:0] nodeOut_b_ridx;\t// @[MixedNode.scala:542:17]\n wire [3:0] nodeOut_b_widx = auto_out_b_widx_0;\t// @[AsyncCrossing.scala:23:9]\n wire nodeOut_b_safe_ridx_valid;\t// @[MixedNode.scala:542:17]\n wire nodeOut_b_safe_widx_valid = auto_out_b_safe_widx_valid_0;\t// @[AsyncCrossing.scala:23:9]\n wire nodeOut_b_safe_source_reset_n = auto_out_b_safe_source_reset_n_0;\t// @[AsyncCrossing.scala:23:9]\n wire nodeOut_b_safe_sink_reset_n;\t// @[MixedNode.scala:542:17]\n wire [2:0] nodeOut_c_mem_0_opcode;\t// @[MixedNode.scala:542:17]\n wire [2:0] nodeOut_c_mem_0_param;\t// @[MixedNode.scala:542:17]\n wire [3:0] nodeOut_c_mem_0_size;\t// @[MixedNode.scala:542:17]\n wire [1:0] nodeOut_c_mem_0_source;\t// @[MixedNode.scala:542:17]\n wire [31:0] nodeOut_c_mem_0_address;\t// @[MixedNode.scala:542:17]\n wire [63:0] nodeOut_c_mem_0_data;\t// @[MixedNode.scala:542:17]\n wire [2:0] nodeOut_c_mem_1_opcode;\t// @[MixedNode.scala:542:17]\n wire [2:0] nodeOut_c_mem_1_param;\t// @[MixedNode.scala:542:17]\n wire [3:0] nodeOut_c_mem_1_size;\t// @[MixedNode.scala:542:17]\n wire [1:0] nodeOut_c_mem_1_source;\t// @[MixedNode.scala:542:17]\n wire [31:0] nodeOut_c_mem_1_address;\t// @[MixedNode.scala:542:17]\n wire [63:0] nodeOut_c_mem_1_data;\t// @[MixedNode.scala:542:17]\n wire [2:0] nodeOut_c_mem_2_opcode;\t// @[MixedNode.scala:542:17]\n wire [2:0] nodeOut_c_mem_2_param;\t// @[MixedNode.scala:542:17]\n wire [3:0] nodeOut_c_mem_2_size;\t// @[MixedNode.scala:542:17]\n wire [1:0] nodeOut_c_mem_2_source;\t// @[MixedNode.scala:542:17]\n wire [31:0] nodeOut_c_mem_2_address;\t// @[MixedNode.scala:542:17]\n wire [63:0] nodeOut_c_mem_2_data;\t// @[MixedNode.scala:542:17]\n wire [2:0] nodeOut_c_mem_3_opcode;\t// @[MixedNode.scala:542:17]\n wire [2:0] nodeOut_c_mem_3_param;\t// @[MixedNode.scala:542:17]\n wire [3:0] nodeOut_c_mem_3_size;\t// @[MixedNode.scala:542:17]\n wire [1:0] nodeOut_c_mem_3_source;\t// @[MixedNode.scala:542:17]\n wire [31:0] nodeOut_c_mem_3_address;\t// @[MixedNode.scala:542:17]\n wire [63:0] nodeOut_c_mem_3_data;\t// @[MixedNode.scala:542:17]\n wire [2:0] nodeOut_c_mem_4_opcode;\t// @[MixedNode.scala:542:17]\n wire [2:0] nodeOut_c_mem_4_param;\t// @[MixedNode.scala:542:17]\n wire [3:0] nodeOut_c_mem_4_size;\t// @[MixedNode.scala:542:17]\n wire [1:0] nodeOut_c_mem_4_source;\t// @[MixedNode.scala:542:17]\n wire [31:0] nodeOut_c_mem_4_address;\t// @[MixedNode.scala:542:17]\n wire [63:0] nodeOut_c_mem_4_data;\t// @[MixedNode.scala:542:17]\n wire [2:0] nodeOut_c_mem_5_opcode;\t// @[MixedNode.scala:542:17]\n wire [2:0] nodeOut_c_mem_5_param;\t// @[MixedNode.scala:542:17]\n wire [3:0] nodeOut_c_mem_5_size;\t// @[MixedNode.scala:542:17]\n wire [1:0] nodeOut_c_mem_5_source;\t// @[MixedNode.scala:542:17]\n wire [31:0] nodeOut_c_mem_5_address;\t// @[MixedNode.scala:542:17]\n wire [63:0] nodeOut_c_mem_5_data;\t// @[MixedNode.scala:542:17]\n wire [2:0] nodeOut_c_mem_6_opcode;\t// @[MixedNode.scala:542:17]\n wire [2:0] nodeOut_c_mem_6_param;\t// @[MixedNode.scala:542:17]\n wire [3:0] nodeOut_c_mem_6_size;\t// @[MixedNode.scala:542:17]\n wire [1:0] nodeOut_c_mem_6_source;\t// @[MixedNode.scala:542:17]\n wire [31:0] nodeOut_c_mem_6_address;\t// @[MixedNode.scala:542:17]\n wire [63:0] nodeOut_c_mem_6_data;\t// @[MixedNode.scala:542:17]\n wire [2:0] nodeOut_c_mem_7_opcode;\t// @[MixedNode.scala:542:17]\n wire [2:0] nodeOut_c_mem_7_param;\t// @[MixedNode.scala:542:17]\n wire [3:0] nodeOut_c_mem_7_size;\t// @[MixedNode.scala:542:17]\n wire [1:0] nodeOut_c_mem_7_source;\t// @[MixedNode.scala:542:17]\n wire [31:0] nodeOut_c_mem_7_address;\t// @[MixedNode.scala:542:17]\n wire [63:0] nodeOut_c_mem_7_data;\t// @[MixedNode.scala:542:17]\n wire [3:0] nodeOut_c_ridx = auto_out_c_ridx_0;\t// @[AsyncCrossing.scala:23:9]\n wire [3:0] nodeOut_c_widx;\t// @[MixedNode.scala:542:17]\n wire nodeOut_c_safe_ridx_valid = auto_out_c_safe_ridx_valid_0;\t// @[AsyncCrossing.scala:23:9]\n wire nodeOut_c_safe_widx_valid;\t// @[MixedNode.scala:542:17]\n wire nodeOut_c_safe_source_reset_n;\t// @[MixedNode.scala:542:17]\n wire nodeOut_c_safe_sink_reset_n = auto_out_c_safe_sink_reset_n_0;\t// @[AsyncCrossing.scala:23:9]\n wire [2:0] nodeOut_d_mem_0_opcode = auto_out_d_mem_0_opcode_0;\t// @[AsyncCrossing.scala:23:9]\n wire [1:0] nodeOut_d_mem_0_param = auto_out_d_mem_0_param_0;\t// @[AsyncCrossing.scala:23:9]\n wire [3:0] nodeOut_d_mem_0_size = auto_out_d_mem_0_size_0;\t// @[AsyncCrossing.scala:23:9]\n wire [1:0] nodeOut_d_mem_0_source = auto_out_d_mem_0_source_0;\t// @[AsyncCrossing.scala:23:9]\n wire [2:0] nodeOut_d_mem_0_sink = auto_out_d_mem_0_sink_0;\t// @[AsyncCrossing.scala:23:9]\n wire nodeOut_d_mem_0_denied = auto_out_d_mem_0_denied_0;\t// @[AsyncCrossing.scala:23:9]\n wire [63:0] nodeOut_d_mem_0_data = auto_out_d_mem_0_data_0;\t// @[AsyncCrossing.scala:23:9]\n wire nodeOut_d_mem_0_corrupt = auto_out_d_mem_0_corrupt_0;\t// @[AsyncCrossing.scala:23:9]\n wire [2:0] nodeOut_d_mem_1_opcode = auto_out_d_mem_1_opcode_0;\t// @[AsyncCrossing.scala:23:9]\n wire [1:0] nodeOut_d_mem_1_param = auto_out_d_mem_1_param_0;\t// @[AsyncCrossing.scala:23:9]\n wire [3:0] nodeOut_d_mem_1_size = auto_out_d_mem_1_size_0;\t// @[AsyncCrossing.scala:23:9]\n wire [1:0] nodeOut_d_mem_1_source = auto_out_d_mem_1_source_0;\t// @[AsyncCrossing.scala:23:9]\n wire [2:0] nodeOut_d_mem_1_sink = auto_out_d_mem_1_sink_0;\t// @[AsyncCrossing.scala:23:9]\n wire nodeOut_d_mem_1_denied = auto_out_d_mem_1_denied_0;\t// @[AsyncCrossing.scala:23:9]\n wire [63:0] nodeOut_d_mem_1_data = auto_out_d_mem_1_data_0;\t// @[AsyncCrossing.scala:23:9]\n wire nodeOut_d_mem_1_corrupt = auto_out_d_mem_1_corrupt_0;\t// @[AsyncCrossing.scala:23:9]\n wire [2:0] nodeOut_d_mem_2_opcode = auto_out_d_mem_2_opcode_0;\t// @[AsyncCrossing.scala:23:9]\n wire [1:0] nodeOut_d_mem_2_param = auto_out_d_mem_2_param_0;\t// @[AsyncCrossing.scala:23:9]\n wire [3:0] nodeOut_d_mem_2_size = auto_out_d_mem_2_size_0;\t// @[AsyncCrossing.scala:23:9]\n wire [1:0] nodeOut_d_mem_2_source = auto_out_d_mem_2_source_0;\t// @[AsyncCrossing.scala:23:9]\n wire [2:0] nodeOut_d_mem_2_sink = auto_out_d_mem_2_sink_0;\t// @[AsyncCrossing.scala:23:9]\n wire nodeOut_d_mem_2_denied = auto_out_d_mem_2_denied_0;\t// @[AsyncCrossing.scala:23:9]\n wire [63:0] nodeOut_d_mem_2_data = auto_out_d_mem_2_data_0;\t// @[AsyncCrossing.scala:23:9]\n wire nodeOut_d_mem_2_corrupt = auto_out_d_mem_2_corrupt_0;\t// @[AsyncCrossing.scala:23:9]\n wire [2:0] nodeOut_d_mem_3_opcode = auto_out_d_mem_3_opcode_0;\t// @[AsyncCrossing.scala:23:9]\n wire [1:0] nodeOut_d_mem_3_param = auto_out_d_mem_3_param_0;\t// @[AsyncCrossing.scala:23:9]\n wire [3:0] nodeOut_d_mem_3_size = auto_out_d_mem_3_size_0;\t// @[AsyncCrossing.scala:23:9]\n wire [1:0] nodeOut_d_mem_3_source = auto_out_d_mem_3_source_0;\t// @[AsyncCrossing.scala:23:9]\n wire [2:0] nodeOut_d_mem_3_sink = auto_out_d_mem_3_sink_0;\t// @[AsyncCrossing.scala:23:9]\n wire nodeOut_d_mem_3_denied = auto_out_d_mem_3_denied_0;\t// @[AsyncCrossing.scala:23:9]\n wire [63:0] nodeOut_d_mem_3_data = auto_out_d_mem_3_data_0;\t// @[AsyncCrossing.scala:23:9]\n wire nodeOut_d_mem_3_corrupt = auto_out_d_mem_3_corrupt_0;\t// @[AsyncCrossing.scala:23:9]\n wire [2:0] nodeOut_d_mem_4_opcode = auto_out_d_mem_4_opcode_0;\t// @[AsyncCrossing.scala:23:9]\n wire [1:0] nodeOut_d_mem_4_param = auto_out_d_mem_4_param_0;\t// @[AsyncCrossing.scala:23:9]\n wire [3:0] nodeOut_d_mem_4_size = auto_out_d_mem_4_size_0;\t// @[AsyncCrossing.scala:23:9]\n wire [1:0] nodeOut_d_mem_4_source = auto_out_d_mem_4_source_0;\t// @[AsyncCrossing.scala:23:9]\n wire [2:0] nodeOut_d_mem_4_sink = auto_out_d_mem_4_sink_0;\t// @[AsyncCrossing.scala:23:9]\n wire nodeOut_d_mem_4_denied = auto_out_d_mem_4_denied_0;\t// @[AsyncCrossing.scala:23:9]\n wire [63:0] nodeOut_d_mem_4_data = auto_out_d_mem_4_data_0;\t// @[AsyncCrossing.scala:23:9]\n wire nodeOut_d_mem_4_corrupt = auto_out_d_mem_4_corrupt_0;\t// @[AsyncCrossing.scala:23:9]\n wire [2:0] nodeOut_d_mem_5_opcode = auto_out_d_mem_5_opcode_0;\t// @[AsyncCrossing.scala:23:9]\n wire [1:0] nodeOut_d_mem_5_param = auto_out_d_mem_5_param_0;\t// @[AsyncCrossing.scala:23:9]\n wire [3:0] nodeOut_d_mem_5_size = auto_out_d_mem_5_size_0;\t// @[AsyncCrossing.scala:23:9]\n wire [1:0] nodeOut_d_mem_5_source = auto_out_d_mem_5_source_0;\t// @[AsyncCrossing.scala:23:9]\n wire [2:0] nodeOut_d_mem_5_sink = auto_out_d_mem_5_sink_0;\t// @[AsyncCrossing.scala:23:9]\n wire nodeOut_d_mem_5_denied = auto_out_d_mem_5_denied_0;\t// @[AsyncCrossing.scala:23:9]\n wire [63:0] nodeOut_d_mem_5_data = auto_out_d_mem_5_data_0;\t// @[AsyncCrossing.scala:23:9]\n wire nodeOut_d_mem_5_corrupt = auto_out_d_mem_5_corrupt_0;\t// @[AsyncCrossing.scala:23:9]\n wire [2:0] nodeOut_d_mem_6_opcode = auto_out_d_mem_6_opcode_0;\t// @[AsyncCrossing.scala:23:9]\n wire [1:0] nodeOut_d_mem_6_param = auto_out_d_mem_6_param_0;\t// @[AsyncCrossing.scala:23:9]\n wire [3:0] nodeOut_d_mem_6_size = auto_out_d_mem_6_size_0;\t// @[AsyncCrossing.scala:23:9]\n wire [1:0] nodeOut_d_mem_6_source = auto_out_d_mem_6_source_0;\t// @[AsyncCrossing.scala:23:9]\n wire [2:0] nodeOut_d_mem_6_sink = auto_out_d_mem_6_sink_0;\t// @[AsyncCrossing.scala:23:9]\n wire nodeOut_d_mem_6_denied = auto_out_d_mem_6_denied_0;\t// @[AsyncCrossing.scala:23:9]\n wire [63:0] nodeOut_d_mem_6_data = auto_out_d_mem_6_data_0;\t// @[AsyncCrossing.scala:23:9]\n wire nodeOut_d_mem_6_corrupt = auto_out_d_mem_6_corrupt_0;\t// @[AsyncCrossing.scala:23:9]\n wire [2:0] nodeOut_d_mem_7_opcode = auto_out_d_mem_7_opcode_0;\t// @[AsyncCrossing.scala:23:9]\n wire [1:0] nodeOut_d_mem_7_param = auto_out_d_mem_7_param_0;\t// @[AsyncCrossing.scala:23:9]\n wire [3:0] nodeOut_d_mem_7_size = auto_out_d_mem_7_size_0;\t// @[AsyncCrossing.scala:23:9]\n wire [1:0] nodeOut_d_mem_7_source = auto_out_d_mem_7_source_0;\t// @[AsyncCrossing.scala:23:9]\n wire [2:0] nodeOut_d_mem_7_sink = auto_out_d_mem_7_sink_0;\t// @[AsyncCrossing.scala:23:9]\n wire nodeOut_d_mem_7_denied = auto_out_d_mem_7_denied_0;\t// @[AsyncCrossing.scala:23:9]\n wire [63:0] nodeOut_d_mem_7_data = auto_out_d_mem_7_data_0;\t// @[AsyncCrossing.scala:23:9]\n wire nodeOut_d_mem_7_corrupt = auto_out_d_mem_7_corrupt_0;\t// @[AsyncCrossing.scala:23:9]\n wire [3:0] nodeOut_d_ridx;\t// @[MixedNode.scala:542:17]\n wire [3:0] nodeOut_d_widx = auto_out_d_widx_0;\t// @[AsyncCrossing.scala:23:9]\n wire nodeOut_d_safe_ridx_valid;\t// @[MixedNode.scala:542:17]\n wire nodeOut_d_safe_widx_valid = auto_out_d_safe_widx_valid_0;\t// @[AsyncCrossing.scala:23:9]\n wire nodeOut_d_safe_source_reset_n = auto_out_d_safe_source_reset_n_0;\t// @[AsyncCrossing.scala:23:9]\n wire nodeOut_d_safe_sink_reset_n;\t// @[MixedNode.scala:542:17]\n wire [2:0] nodeOut_e_mem_0_sink;\t// @[MixedNode.scala:542:17]\n wire [2:0] nodeOut_e_mem_1_sink;\t// @[MixedNode.scala:542:17]\n wire [2:0] nodeOut_e_mem_2_sink;\t// @[MixedNode.scala:542:17]\n wire [2:0] nodeOut_e_mem_3_sink;\t// @[MixedNode.scala:542:17]\n wire [2:0] nodeOut_e_mem_4_sink;\t// @[MixedNode.scala:542:17]\n wire [2:0] nodeOut_e_mem_5_sink;\t// @[MixedNode.scala:542:17]\n wire [2:0] nodeOut_e_mem_6_sink;\t// @[MixedNode.scala:542:17]\n wire [2:0] nodeOut_e_mem_7_sink;\t// @[MixedNode.scala:542:17]\n wire [3:0] nodeOut_e_ridx = auto_out_e_ridx_0;\t// @[AsyncCrossing.scala:23:9]\n wire [3:0] nodeOut_e_widx;\t// @[MixedNode.scala:542:17]\n wire nodeOut_e_safe_ridx_valid = auto_out_e_safe_ridx_valid_0;\t// @[AsyncCrossing.scala:23:9]\n wire nodeOut_e_safe_widx_valid;\t// @[MixedNode.scala:542:17]\n wire nodeOut_e_safe_source_reset_n;\t// @[MixedNode.scala:542:17]\n wire nodeOut_e_safe_sink_reset_n = auto_out_e_safe_sink_reset_n_0;\t// @[AsyncCrossing.scala:23:9]\n wire auto_in_a_ready_0;\t// @[AsyncCrossing.scala:23:9]\n wire [2:0] auto_in_b_bits_opcode_0;\t// @[AsyncCrossing.scala:23:9]\n wire [1:0] auto_in_b_bits_param_0;\t// @[AsyncCrossing.scala:23:9]\n wire [3:0] auto_in_b_bits_size_0;\t// @[AsyncCrossing.scala:23:9]\n wire [1:0] auto_in_b_bits_source_0;\t// @[AsyncCrossing.scala:23:9]\n wire [31:0] auto_in_b_bits_address_0;\t// @[AsyncCrossing.scala:23:9]\n wire [7:0] auto_in_b_bits_mask_0;\t// @[AsyncCrossing.scala:23:9]\n wire [63:0] auto_in_b_bits_data_0;\t// @[AsyncCrossing.scala:23:9]\n wire auto_in_b_bits_corrupt_0;\t// @[AsyncCrossing.scala:23:9]\n wire auto_in_b_valid_0;\t// @[AsyncCrossing.scala:23:9]\n wire auto_in_c_ready_0;\t// @[AsyncCrossing.scala:23:9]\n wire [2:0] auto_in_d_bits_opcode_0;\t// @[AsyncCrossing.scala:23:9]\n wire [1:0] auto_in_d_bits_param_0;\t// @[AsyncCrossing.scala:23:9]\n wire [3:0] auto_in_d_bits_size_0;\t// @[AsyncCrossing.scala:23:9]\n wire [1:0] auto_in_d_bits_source_0;\t// @[AsyncCrossing.scala:23:9]\n wire [2:0] auto_in_d_bits_sink_0;\t// @[AsyncCrossing.scala:23:9]\n wire auto_in_d_bits_denied_0;\t// @[AsyncCrossing.scala:23:9]\n wire [63:0] auto_in_d_bits_data_0;\t// @[AsyncCrossing.scala:23:9]\n wire auto_in_d_bits_corrupt_0;\t// @[AsyncCrossing.scala:23:9]\n wire auto_in_d_valid_0;\t// @[AsyncCrossing.scala:23:9]\n wire auto_in_e_ready_0;\t// @[AsyncCrossing.scala:23:9]\n wire [2:0] auto_out_a_mem_0_opcode_0;\t// @[AsyncCrossing.scala:23:9]\n wire [2:0] auto_out_a_mem_0_param_0;\t// @[AsyncCrossing.scala:23:9]\n wire [3:0] auto_out_a_mem_0_size_0;\t// @[AsyncCrossing.scala:23:9]\n wire [1:0] auto_out_a_mem_0_source_0;\t// @[AsyncCrossing.scala:23:9]\n wire [31:0] auto_out_a_mem_0_address_0;\t// @[AsyncCrossing.scala:23:9]\n wire [7:0] auto_out_a_mem_0_mask_0;\t// @[AsyncCrossing.scala:23:9]\n wire [63:0] auto_out_a_mem_0_data_0;\t// @[AsyncCrossing.scala:23:9]\n wire [2:0] auto_out_a_mem_1_opcode_0;\t// @[AsyncCrossing.scala:23:9]\n wire [2:0] auto_out_a_mem_1_param_0;\t// @[AsyncCrossing.scala:23:9]\n wire [3:0] auto_out_a_mem_1_size_0;\t// @[AsyncCrossing.scala:23:9]\n wire [1:0] auto_out_a_mem_1_source_0;\t// @[AsyncCrossing.scala:23:9]\n wire [31:0] auto_out_a_mem_1_address_0;\t// @[AsyncCrossing.scala:23:9]\n wire [7:0] auto_out_a_mem_1_mask_0;\t// @[AsyncCrossing.scala:23:9]\n wire [63:0] auto_out_a_mem_1_data_0;\t// @[AsyncCrossing.scala:23:9]\n wire [2:0] auto_out_a_mem_2_opcode_0;\t// @[AsyncCrossing.scala:23:9]\n wire [2:0] auto_out_a_mem_2_param_0;\t// @[AsyncCrossing.scala:23:9]\n wire [3:0] auto_out_a_mem_2_size_0;\t// @[AsyncCrossing.scala:23:9]\n wire [1:0] auto_out_a_mem_2_source_0;\t// @[AsyncCrossing.scala:23:9]\n wire [31:0] auto_out_a_mem_2_address_0;\t// @[AsyncCrossing.scala:23:9]\n wire [7:0] auto_out_a_mem_2_mask_0;\t// @[AsyncCrossing.scala:23:9]\n wire [63:0] auto_out_a_mem_2_data_0;\t// @[AsyncCrossing.scala:23:9]\n wire [2:0] auto_out_a_mem_3_opcode_0;\t// @[AsyncCrossing.scala:23:9]\n wire [2:0] auto_out_a_mem_3_param_0;\t// @[AsyncCrossing.scala:23:9]\n wire [3:0] auto_out_a_mem_3_size_0;\t// @[AsyncCrossing.scala:23:9]\n wire [1:0] auto_out_a_mem_3_source_0;\t// @[AsyncCrossing.scala:23:9]\n wire [31:0] auto_out_a_mem_3_address_0;\t// @[AsyncCrossing.scala:23:9]\n wire [7:0] auto_out_a_mem_3_mask_0;\t// @[AsyncCrossing.scala:23:9]\n wire [63:0] auto_out_a_mem_3_data_0;\t// @[AsyncCrossing.scala:23:9]\n wire [2:0] auto_out_a_mem_4_opcode_0;\t// @[AsyncCrossing.scala:23:9]\n wire [2:0] auto_out_a_mem_4_param_0;\t// @[AsyncCrossing.scala:23:9]\n wire [3:0] auto_out_a_mem_4_size_0;\t// @[AsyncCrossing.scala:23:9]\n wire [1:0] auto_out_a_mem_4_source_0;\t// @[AsyncCrossing.scala:23:9]\n wire [31:0] auto_out_a_mem_4_address_0;\t// @[AsyncCrossing.scala:23:9]\n wire [7:0] auto_out_a_mem_4_mask_0;\t// @[AsyncCrossing.scala:23:9]\n wire [63:0] auto_out_a_mem_4_data_0;\t// @[AsyncCrossing.scala:23:9]\n wire [2:0] auto_out_a_mem_5_opcode_0;\t// @[AsyncCrossing.scala:23:9]\n wire [2:0] auto_out_a_mem_5_param_0;\t// @[AsyncCrossing.scala:23:9]\n wire [3:0] auto_out_a_mem_5_size_0;\t// @[AsyncCrossing.scala:23:9]\n wire [1:0] auto_out_a_mem_5_source_0;\t// @[AsyncCrossing.scala:23:9]\n wire [31:0] auto_out_a_mem_5_address_0;\t// @[AsyncCrossing.scala:23:9]\n wire [7:0] auto_out_a_mem_5_mask_0;\t// @[AsyncCrossing.scala:23:9]\n wire [63:0] auto_out_a_mem_5_data_0;\t// @[AsyncCrossing.scala:23:9]\n wire [2:0] auto_out_a_mem_6_opcode_0;\t// @[AsyncCrossing.scala:23:9]\n wire [2:0] auto_out_a_mem_6_param_0;\t// @[AsyncCrossing.scala:23:9]\n wire [3:0] auto_out_a_mem_6_size_0;\t// @[AsyncCrossing.scala:23:9]\n wire [1:0] auto_out_a_mem_6_source_0;\t// @[AsyncCrossing.scala:23:9]\n wire [31:0] auto_out_a_mem_6_address_0;\t// @[AsyncCrossing.scala:23:9]\n wire [7:0] auto_out_a_mem_6_mask_0;\t// @[AsyncCrossing.scala:23:9]\n wire [63:0] auto_out_a_mem_6_data_0;\t// @[AsyncCrossing.scala:23:9]\n wire [2:0] auto_out_a_mem_7_opcode_0;\t// @[AsyncCrossing.scala:23:9]\n wire [2:0] auto_out_a_mem_7_param_0;\t// @[AsyncCrossing.scala:23:9]\n wire [3:0] auto_out_a_mem_7_size_0;\t// @[AsyncCrossing.scala:23:9]\n wire [1:0] auto_out_a_mem_7_source_0;\t// @[AsyncCrossing.scala:23:9]\n wire [31:0] auto_out_a_mem_7_address_0;\t// @[AsyncCrossing.scala:23:9]\n wire [7:0] auto_out_a_mem_7_mask_0;\t// @[AsyncCrossing.scala:23:9]\n wire [63:0] auto_out_a_mem_7_data_0;\t// @[AsyncCrossing.scala:23:9]\n wire auto_out_a_safe_widx_valid_0;\t// @[AsyncCrossing.scala:23:9]\n wire auto_out_a_safe_source_reset_n_0;\t// @[AsyncCrossing.scala:23:9]\n wire [3:0] auto_out_a_widx_0;\t// @[AsyncCrossing.scala:23:9]\n wire auto_out_b_safe_ridx_valid_0;\t// @[AsyncCrossing.scala:23:9]\n wire auto_out_b_safe_sink_reset_n_0;\t// @[AsyncCrossing.scala:23:9]\n wire [3:0] auto_out_b_ridx_0;\t// @[AsyncCrossing.scala:23:9]\n wire [2:0] auto_out_c_mem_0_opcode_0;\t// @[AsyncCrossing.scala:23:9]\n wire [2:0] auto_out_c_mem_0_param_0;\t// @[AsyncCrossing.scala:23:9]\n wire [3:0] auto_out_c_mem_0_size_0;\t// @[AsyncCrossing.scala:23:9]\n wire [1:0] auto_out_c_mem_0_source_0;\t// @[AsyncCrossing.scala:23:9]\n wire [31:0] auto_out_c_mem_0_address_0;\t// @[AsyncCrossing.scala:23:9]\n wire [63:0] auto_out_c_mem_0_data_0;\t// @[AsyncCrossing.scala:23:9]\n wire [2:0] auto_out_c_mem_1_opcode_0;\t// @[AsyncCrossing.scala:23:9]\n wire [2:0] auto_out_c_mem_1_param_0;\t// @[AsyncCrossing.scala:23:9]\n wire [3:0] auto_out_c_mem_1_size_0;\t// @[AsyncCrossing.scala:23:9]\n wire [1:0] auto_out_c_mem_1_source_0;\t// @[AsyncCrossing.scala:23:9]\n wire [31:0] auto_out_c_mem_1_address_0;\t// @[AsyncCrossing.scala:23:9]\n wire [63:0] auto_out_c_mem_1_data_0;\t// @[AsyncCrossing.scala:23:9]\n wire [2:0] auto_out_c_mem_2_opcode_0;\t// @[AsyncCrossing.scala:23:9]\n wire [2:0] auto_out_c_mem_2_param_0;\t// @[AsyncCrossing.scala:23:9]\n wire [3:0] auto_out_c_mem_2_size_0;\t// @[AsyncCrossing.scala:23:9]\n wire [1:0] auto_out_c_mem_2_source_0;\t// @[AsyncCrossing.scala:23:9]\n wire [31:0] auto_out_c_mem_2_address_0;\t// @[AsyncCrossing.scala:23:9]\n wire [63:0] auto_out_c_mem_2_data_0;\t// @[AsyncCrossing.scala:23:9]\n wire [2:0] auto_out_c_mem_3_opcode_0;\t// @[AsyncCrossing.scala:23:9]\n wire [2:0] auto_out_c_mem_3_param_0;\t// @[AsyncCrossing.scala:23:9]\n wire [3:0] auto_out_c_mem_3_size_0;\t// @[AsyncCrossing.scala:23:9]\n wire [1:0] auto_out_c_mem_3_source_0;\t// @[AsyncCrossing.scala:23:9]\n wire [31:0] auto_out_c_mem_3_address_0;\t// @[AsyncCrossing.scala:23:9]\n wire [63:0] auto_out_c_mem_3_data_0;\t// @[AsyncCrossing.scala:23:9]\n wire [2:0] auto_out_c_mem_4_opcode_0;\t// @[AsyncCrossing.scala:23:9]\n wire [2:0] auto_out_c_mem_4_param_0;\t// @[AsyncCrossing.scala:23:9]\n wire [3:0] auto_out_c_mem_4_size_0;\t// @[AsyncCrossing.scala:23:9]\n wire [1:0] auto_out_c_mem_4_source_0;\t// @[AsyncCrossing.scala:23:9]\n wire [31:0] auto_out_c_mem_4_address_0;\t// @[AsyncCrossing.scala:23:9]\n wire [63:0] auto_out_c_mem_4_data_0;\t// @[AsyncCrossing.scala:23:9]\n wire [2:0] auto_out_c_mem_5_opcode_0;\t// @[AsyncCrossing.scala:23:9]\n wire [2:0] auto_out_c_mem_5_param_0;\t// @[AsyncCrossing.scala:23:9]\n wire [3:0] auto_out_c_mem_5_size_0;\t// @[AsyncCrossing.scala:23:9]\n wire [1:0] auto_out_c_mem_5_source_0;\t// @[AsyncCrossing.scala:23:9]\n wire [31:0] auto_out_c_mem_5_address_0;\t// @[AsyncCrossing.scala:23:9]\n wire [63:0] auto_out_c_mem_5_data_0;\t// @[AsyncCrossing.scala:23:9]\n wire [2:0] auto_out_c_mem_6_opcode_0;\t// @[AsyncCrossing.scala:23:9]\n wire [2:0] auto_out_c_mem_6_param_0;\t// @[AsyncCrossing.scala:23:9]\n wire [3:0] auto_out_c_mem_6_size_0;\t// @[AsyncCrossing.scala:23:9]\n wire [1:0] auto_out_c_mem_6_source_0;\t// @[AsyncCrossing.scala:23:9]\n wire [31:0] auto_out_c_mem_6_address_0;\t// @[AsyncCrossing.scala:23:9]\n wire [63:0] auto_out_c_mem_6_data_0;\t// @[AsyncCrossing.scala:23:9]\n wire [2:0] auto_out_c_mem_7_opcode_0;\t// @[AsyncCrossing.scala:23:9]\n wire [2:0] auto_out_c_mem_7_param_0;\t// @[AsyncCrossing.scala:23:9]\n wire [3:0] auto_out_c_mem_7_size_0;\t// @[AsyncCrossing.scala:23:9]\n wire [1:0] auto_out_c_mem_7_source_0;\t// @[AsyncCrossing.scala:23:9]\n wire [31:0] auto_out_c_mem_7_address_0;\t// @[AsyncCrossing.scala:23:9]\n wire [63:0] auto_out_c_mem_7_data_0;\t// @[AsyncCrossing.scala:23:9]\n wire auto_out_c_safe_widx_valid_0;\t// @[AsyncCrossing.scala:23:9]\n wire auto_out_c_safe_source_reset_n_0;\t// @[AsyncCrossing.scala:23:9]\n wire [3:0] auto_out_c_widx_0;\t// @[AsyncCrossing.scala:23:9]\n wire auto_out_d_safe_ridx_valid_0;\t// @[AsyncCrossing.scala:23:9]\n wire auto_out_d_safe_sink_reset_n_0;\t// @[AsyncCrossing.scala:23:9]\n wire [3:0] auto_out_d_ridx_0;\t// @[AsyncCrossing.scala:23:9]\n wire [2:0] auto_out_e_mem_0_sink_0;\t// @[AsyncCrossing.scala:23:9]\n wire [2:0] auto_out_e_mem_1_sink_0;\t// @[AsyncCrossing.scala:23:9]\n wire [2:0] auto_out_e_mem_2_sink_0;\t// @[AsyncCrossing.scala:23:9]\n wire [2:0] auto_out_e_mem_3_sink_0;\t// @[AsyncCrossing.scala:23:9]\n wire [2:0] auto_out_e_mem_4_sink_0;\t// @[AsyncCrossing.scala:23:9]\n wire [2:0] auto_out_e_mem_5_sink_0;\t// @[AsyncCrossing.scala:23:9]\n wire [2:0] auto_out_e_mem_6_sink_0;\t// @[AsyncCrossing.scala:23:9]\n wire [2:0] auto_out_e_mem_7_sink_0;\t// @[AsyncCrossing.scala:23:9]\n wire auto_out_e_safe_widx_valid_0;\t// @[AsyncCrossing.scala:23:9]\n wire auto_out_e_safe_source_reset_n_0;\t// @[AsyncCrossing.scala:23:9]\n wire [3:0] auto_out_e_widx_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_in_a_ready_0 = nodeIn_a_ready;\t// @[AsyncCrossing.scala:23:9]\n assign auto_in_b_valid_0 = nodeIn_b_valid;\t// @[AsyncCrossing.scala:23:9]\n assign auto_in_b_bits_opcode_0 = nodeIn_b_bits_opcode;\t// @[AsyncCrossing.scala:23:9]\n assign auto_in_b_bits_param_0 = nodeIn_b_bits_param;\t// @[AsyncCrossing.scala:23:9]\n assign auto_in_b_bits_size_0 = nodeIn_b_bits_size;\t// @[AsyncCrossing.scala:23:9]\n assign auto_in_b_bits_source_0 = nodeIn_b_bits_source;\t// @[AsyncCrossing.scala:23:9]\n assign auto_in_b_bits_address_0 = nodeIn_b_bits_address;\t// @[AsyncCrossing.scala:23:9]\n assign auto_in_b_bits_mask_0 = nodeIn_b_bits_mask;\t// @[AsyncCrossing.scala:23:9]\n assign auto_in_b_bits_data_0 = nodeIn_b_bits_data;\t// @[AsyncCrossing.scala:23:9]\n assign auto_in_b_bits_corrupt_0 = nodeIn_b_bits_corrupt;\t// @[AsyncCrossing.scala:23:9]\n assign auto_in_c_ready_0 = nodeIn_c_ready;\t// @[AsyncCrossing.scala:23:9]\n assign auto_in_d_valid_0 = nodeIn_d_valid;\t// @[AsyncCrossing.scala:23:9]\n assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode;\t// @[AsyncCrossing.scala:23:9]\n assign auto_in_d_bits_param_0 = nodeIn_d_bits_param;\t// @[AsyncCrossing.scala:23:9]\n assign auto_in_d_bits_size_0 = nodeIn_d_bits_size;\t// @[AsyncCrossing.scala:23:9]\n assign auto_in_d_bits_source_0 = nodeIn_d_bits_source;\t// @[AsyncCrossing.scala:23:9]\n assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink;\t// @[AsyncCrossing.scala:23:9]\n assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied;\t// @[AsyncCrossing.scala:23:9]\n assign auto_in_d_bits_data_0 = nodeIn_d_bits_data;\t// @[AsyncCrossing.scala:23:9]\n assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt;\t// @[AsyncCrossing.scala:23:9]\n assign auto_in_e_ready_0 = nodeIn_e_ready;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_0_opcode_0 = nodeOut_a_mem_0_opcode;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_0_param_0 = nodeOut_a_mem_0_param;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_0_size_0 = nodeOut_a_mem_0_size;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_0_source_0 = nodeOut_a_mem_0_source;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_0_address_0 = nodeOut_a_mem_0_address;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_0_mask_0 = nodeOut_a_mem_0_mask;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_0_data_0 = nodeOut_a_mem_0_data;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_1_opcode_0 = nodeOut_a_mem_1_opcode;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_1_param_0 = nodeOut_a_mem_1_param;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_1_size_0 = nodeOut_a_mem_1_size;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_1_source_0 = nodeOut_a_mem_1_source;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_1_address_0 = nodeOut_a_mem_1_address;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_1_mask_0 = nodeOut_a_mem_1_mask;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_1_data_0 = nodeOut_a_mem_1_data;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_2_opcode_0 = nodeOut_a_mem_2_opcode;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_2_param_0 = nodeOut_a_mem_2_param;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_2_size_0 = nodeOut_a_mem_2_size;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_2_source_0 = nodeOut_a_mem_2_source;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_2_address_0 = nodeOut_a_mem_2_address;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_2_mask_0 = nodeOut_a_mem_2_mask;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_2_data_0 = nodeOut_a_mem_2_data;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_3_opcode_0 = nodeOut_a_mem_3_opcode;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_3_param_0 = nodeOut_a_mem_3_param;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_3_size_0 = nodeOut_a_mem_3_size;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_3_source_0 = nodeOut_a_mem_3_source;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_3_address_0 = nodeOut_a_mem_3_address;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_3_mask_0 = nodeOut_a_mem_3_mask;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_3_data_0 = nodeOut_a_mem_3_data;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_4_opcode_0 = nodeOut_a_mem_4_opcode;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_4_param_0 = nodeOut_a_mem_4_param;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_4_size_0 = nodeOut_a_mem_4_size;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_4_source_0 = nodeOut_a_mem_4_source;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_4_address_0 = nodeOut_a_mem_4_address;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_4_mask_0 = nodeOut_a_mem_4_mask;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_4_data_0 = nodeOut_a_mem_4_data;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_5_opcode_0 = nodeOut_a_mem_5_opcode;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_5_param_0 = nodeOut_a_mem_5_param;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_5_size_0 = nodeOut_a_mem_5_size;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_5_source_0 = nodeOut_a_mem_5_source;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_5_address_0 = nodeOut_a_mem_5_address;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_5_mask_0 = nodeOut_a_mem_5_mask;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_5_data_0 = nodeOut_a_mem_5_data;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_6_opcode_0 = nodeOut_a_mem_6_opcode;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_6_param_0 = nodeOut_a_mem_6_param;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_6_size_0 = nodeOut_a_mem_6_size;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_6_source_0 = nodeOut_a_mem_6_source;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_6_address_0 = nodeOut_a_mem_6_address;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_6_mask_0 = nodeOut_a_mem_6_mask;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_6_data_0 = nodeOut_a_mem_6_data;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_7_opcode_0 = nodeOut_a_mem_7_opcode;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_7_param_0 = nodeOut_a_mem_7_param;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_7_size_0 = nodeOut_a_mem_7_size;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_7_source_0 = nodeOut_a_mem_7_source;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_7_address_0 = nodeOut_a_mem_7_address;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_7_mask_0 = nodeOut_a_mem_7_mask;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_7_data_0 = nodeOut_a_mem_7_data;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_widx_0 = nodeOut_a_widx;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_safe_widx_valid_0 = nodeOut_a_safe_widx_valid;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_safe_source_reset_n_0 = nodeOut_a_safe_source_reset_n;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_b_ridx_0 = nodeOut_b_ridx;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_b_safe_ridx_valid_0 = nodeOut_b_safe_ridx_valid;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_b_safe_sink_reset_n_0 = nodeOut_b_safe_sink_reset_n;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_0_opcode_0 = nodeOut_c_mem_0_opcode;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_0_param_0 = nodeOut_c_mem_0_param;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_0_size_0 = nodeOut_c_mem_0_size;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_0_source_0 = nodeOut_c_mem_0_source;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_0_address_0 = nodeOut_c_mem_0_address;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_0_data_0 = nodeOut_c_mem_0_data;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_1_opcode_0 = nodeOut_c_mem_1_opcode;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_1_param_0 = nodeOut_c_mem_1_param;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_1_size_0 = nodeOut_c_mem_1_size;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_1_source_0 = nodeOut_c_mem_1_source;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_1_address_0 = nodeOut_c_mem_1_address;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_1_data_0 = nodeOut_c_mem_1_data;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_2_opcode_0 = nodeOut_c_mem_2_opcode;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_2_param_0 = nodeOut_c_mem_2_param;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_2_size_0 = nodeOut_c_mem_2_size;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_2_source_0 = nodeOut_c_mem_2_source;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_2_address_0 = nodeOut_c_mem_2_address;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_2_data_0 = nodeOut_c_mem_2_data;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_3_opcode_0 = nodeOut_c_mem_3_opcode;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_3_param_0 = nodeOut_c_mem_3_param;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_3_size_0 = nodeOut_c_mem_3_size;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_3_source_0 = nodeOut_c_mem_3_source;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_3_address_0 = nodeOut_c_mem_3_address;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_3_data_0 = nodeOut_c_mem_3_data;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_4_opcode_0 = nodeOut_c_mem_4_opcode;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_4_param_0 = nodeOut_c_mem_4_param;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_4_size_0 = nodeOut_c_mem_4_size;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_4_source_0 = nodeOut_c_mem_4_source;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_4_address_0 = nodeOut_c_mem_4_address;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_4_data_0 = nodeOut_c_mem_4_data;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_5_opcode_0 = nodeOut_c_mem_5_opcode;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_5_param_0 = nodeOut_c_mem_5_param;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_5_size_0 = nodeOut_c_mem_5_size;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_5_source_0 = nodeOut_c_mem_5_source;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_5_address_0 = nodeOut_c_mem_5_address;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_5_data_0 = nodeOut_c_mem_5_data;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_6_opcode_0 = nodeOut_c_mem_6_opcode;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_6_param_0 = nodeOut_c_mem_6_param;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_6_size_0 = nodeOut_c_mem_6_size;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_6_source_0 = nodeOut_c_mem_6_source;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_6_address_0 = nodeOut_c_mem_6_address;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_6_data_0 = nodeOut_c_mem_6_data;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_7_opcode_0 = nodeOut_c_mem_7_opcode;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_7_param_0 = nodeOut_c_mem_7_param;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_7_size_0 = nodeOut_c_mem_7_size;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_7_source_0 = nodeOut_c_mem_7_source;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_7_address_0 = nodeOut_c_mem_7_address;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_7_data_0 = nodeOut_c_mem_7_data;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_widx_0 = nodeOut_c_widx;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_safe_widx_valid_0 = nodeOut_c_safe_widx_valid;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_safe_source_reset_n_0 = nodeOut_c_safe_source_reset_n;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_d_ridx_0 = nodeOut_d_ridx;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_d_safe_ridx_valid_0 = nodeOut_d_safe_ridx_valid;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_d_safe_sink_reset_n_0 = nodeOut_d_safe_sink_reset_n;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_e_mem_0_sink_0 = nodeOut_e_mem_0_sink;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_e_mem_1_sink_0 = nodeOut_e_mem_1_sink;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_e_mem_2_sink_0 = nodeOut_e_mem_2_sink;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_e_mem_3_sink_0 = nodeOut_e_mem_3_sink;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_e_mem_4_sink_0 = nodeOut_e_mem_4_sink;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_e_mem_5_sink_0 = nodeOut_e_mem_5_sink;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_e_mem_6_sink_0 = nodeOut_e_mem_6_sink;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_e_mem_7_sink_0 = nodeOut_e_mem_7_sink;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_e_widx_0 = nodeOut_e_widx;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_e_safe_widx_valid_0 = nodeOut_e_safe_widx_valid;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_e_safe_source_reset_n_0 = nodeOut_e_safe_source_reset_n;\t// @[AsyncCrossing.scala:23:9]\n TLMonitor_41 monitor (\t// @[Nodes.scala:27:25]\n .clock (clock),\n .reset (reset),\n .io_in_a_ready (nodeIn_a_ready),\t// @[MixedNode.scala:551:17]\n .io_in_a_valid (nodeIn_a_valid),\t// @[MixedNode.scala:551:17]\n .io_in_a_bits_opcode (nodeIn_a_bits_opcode),\t// @[MixedNode.scala:551:17]\n .io_in_a_bits_param (nodeIn_a_bits_param),\t// @[MixedNode.scala:551:17]\n .io_in_a_bits_size (nodeIn_a_bits_size),\t// @[MixedNode.scala:551:17]\n .io_in_a_bits_source (nodeIn_a_bits_source),\t// @[MixedNode.scala:551:17]\n .io_in_a_bits_address (nodeIn_a_bits_address),\t// @[MixedNode.scala:551:17]\n .io_in_a_bits_mask (nodeIn_a_bits_mask),\t// @[MixedNode.scala:551:17]\n .io_in_a_bits_data (nodeIn_a_bits_data),\t// @[MixedNode.scala:551:17]\n .io_in_b_ready (nodeIn_b_ready),\t// @[MixedNode.scala:551:17]\n .io_in_b_valid (nodeIn_b_valid),\t// @[MixedNode.scala:551:17]\n .io_in_b_bits_opcode (nodeIn_b_bits_opcode),\t// @[MixedNode.scala:551:17]\n .io_in_b_bits_param (nodeIn_b_bits_param),\t// @[MixedNode.scala:551:17]\n .io_in_b_bits_size (nodeIn_b_bits_size),\t// @[MixedNode.scala:551:17]\n .io_in_b_bits_source (nodeIn_b_bits_source),\t// @[MixedNode.scala:551:17]\n .io_in_b_bits_address (nodeIn_b_bits_address),\t// @[MixedNode.scala:551:17]\n .io_in_b_bits_mask (nodeIn_b_bits_mask),\t// @[MixedNode.scala:551:17]\n .io_in_b_bits_data (nodeIn_b_bits_data),\t// @[MixedNode.scala:551:17]\n .io_in_b_bits_corrupt (nodeIn_b_bits_corrupt),\t// @[MixedNode.scala:551:17]\n .io_in_c_ready (nodeIn_c_ready),\t// @[MixedNode.scala:551:17]\n .io_in_c_valid (nodeIn_c_valid),\t// @[MixedNode.scala:551:17]\n .io_in_c_bits_opcode (nodeIn_c_bits_opcode),\t// @[MixedNode.scala:551:17]\n .io_in_c_bits_param (nodeIn_c_bits_param),\t// @[MixedNode.scala:551:17]\n .io_in_c_bits_size (nodeIn_c_bits_size),\t// @[MixedNode.scala:551:17]\n .io_in_c_bits_source (nodeIn_c_bits_source),\t// @[MixedNode.scala:551:17]\n .io_in_c_bits_address (nodeIn_c_bits_address),\t// @[MixedNode.scala:551:17]\n .io_in_c_bits_data (nodeIn_c_bits_data),\t// @[MixedNode.scala:551:17]\n .io_in_d_ready (nodeIn_d_ready),\t// @[MixedNode.scala:551:17]\n .io_in_d_valid (nodeIn_d_valid),\t// @[MixedNode.scala:551:17]\n .io_in_d_bits_opcode (nodeIn_d_bits_opcode),\t// @[MixedNode.scala:551:17]\n .io_in_d_bits_param (nodeIn_d_bits_param),\t// @[MixedNode.scala:551:17]\n .io_in_d_bits_size (nodeIn_d_bits_size),\t// @[MixedNode.scala:551:17]\n .io_in_d_bits_source (nodeIn_d_bits_source),\t// @[MixedNode.scala:551:17]\n .io_in_d_bits_sink (nodeIn_d_bits_sink),\t// @[MixedNode.scala:551:17]\n .io_in_d_bits_denied (nodeIn_d_bits_denied),\t// @[MixedNode.scala:551:17]\n .io_in_d_bits_data (nodeIn_d_bits_data),\t// @[MixedNode.scala:551:17]\n .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt),\t// @[MixedNode.scala:551:17]\n .io_in_e_ready (nodeIn_e_ready),\t// @[MixedNode.scala:551:17]\n .io_in_e_valid (nodeIn_e_valid),\t// @[MixedNode.scala:551:17]\n .io_in_e_bits_sink (nodeIn_e_bits_sink)\t// @[MixedNode.scala:551:17]\n );\t// @[Nodes.scala:27:25]\n AsyncQueueSource_TLBundleA_a32d64s2k3z4c nodeOut_a_source (\t// @[AsyncQueue.scala:220:24]\n .clock (clock),\n .reset (reset),\n .io_enq_ready (nodeIn_a_ready),\n .io_enq_valid (nodeIn_a_valid),\t// @[MixedNode.scala:551:17]\n .io_enq_bits_opcode (nodeIn_a_bits_opcode),\t// @[MixedNode.scala:551:17]\n .io_enq_bits_param (nodeIn_a_bits_param),\t// @[MixedNode.scala:551:17]\n .io_enq_bits_size (nodeIn_a_bits_size),\t// @[MixedNode.scala:551:17]\n .io_enq_bits_source (nodeIn_a_bits_source),\t// @[MixedNode.scala:551:17]\n .io_enq_bits_address (nodeIn_a_bits_address),\t// @[MixedNode.scala:551:17]\n .io_enq_bits_mask (nodeIn_a_bits_mask),\t// @[MixedNode.scala:551:17]\n .io_enq_bits_data (nodeIn_a_bits_data),\t// @[MixedNode.scala:551:17]\n .io_async_mem_0_opcode (nodeOut_a_mem_0_opcode),\n .io_async_mem_0_param (nodeOut_a_mem_0_param),\n .io_async_mem_0_size (nodeOut_a_mem_0_size),\n .io_async_mem_0_source (nodeOut_a_mem_0_source),\n .io_async_mem_0_address (nodeOut_a_mem_0_address),\n .io_async_mem_0_mask (nodeOut_a_mem_0_mask),\n .io_async_mem_0_data (nodeOut_a_mem_0_data),\n .io_async_mem_1_opcode (nodeOut_a_mem_1_opcode),\n .io_async_mem_1_param (nodeOut_a_mem_1_param),\n .io_async_mem_1_size (nodeOut_a_mem_1_size),\n .io_async_mem_1_source (nodeOut_a_mem_1_source),\n .io_async_mem_1_address (nodeOut_a_mem_1_address),\n .io_async_mem_1_mask (nodeOut_a_mem_1_mask),\n .io_async_mem_1_data (nodeOut_a_mem_1_data),\n .io_async_mem_2_opcode (nodeOut_a_mem_2_opcode),\n .io_async_mem_2_param (nodeOut_a_mem_2_param),\n .io_async_mem_2_size (nodeOut_a_mem_2_size),\n .io_async_mem_2_source (nodeOut_a_mem_2_source),\n .io_async_mem_2_address (nodeOut_a_mem_2_address),\n .io_async_mem_2_mask (nodeOut_a_mem_2_mask),\n .io_async_mem_2_data (nodeOut_a_mem_2_data),\n .io_async_mem_3_opcode (nodeOut_a_mem_3_opcode),\n .io_async_mem_3_param (nodeOut_a_mem_3_param),\n .io_async_mem_3_size (nodeOut_a_mem_3_size),\n .io_async_mem_3_source (nodeOut_a_mem_3_source),\n .io_async_mem_3_address (nodeOut_a_mem_3_address),\n .io_async_mem_3_mask (nodeOut_a_mem_3_mask),\n .io_async_mem_3_data (nodeOut_a_mem_3_data),\n .io_async_mem_4_opcode (nodeOut_a_mem_4_opcode),\n .io_async_mem_4_param (nodeOut_a_mem_4_param),\n .io_async_mem_4_size (nodeOut_a_mem_4_size),\n .io_async_mem_4_source (nodeOut_a_mem_4_source),\n .io_async_mem_4_address (nodeOut_a_mem_4_address),\n .io_async_mem_4_mask (nodeOut_a_mem_4_mask),\n .io_async_mem_4_data (nodeOut_a_mem_4_data),\n .io_async_mem_5_opcode (nodeOut_a_mem_5_opcode),\n .io_async_mem_5_param (nodeOut_a_mem_5_param),\n .io_async_mem_5_size (nodeOut_a_mem_5_size),\n .io_async_mem_5_source (nodeOut_a_mem_5_source),\n .io_async_mem_5_address (nodeOut_a_mem_5_address),\n .io_async_mem_5_mask (nodeOut_a_mem_5_mask),\n .io_async_mem_5_data (nodeOut_a_mem_5_data),\n .io_async_mem_6_opcode (nodeOut_a_mem_6_opcode),\n .io_async_mem_6_param (nodeOut_a_mem_6_param),\n .io_async_mem_6_size (nodeOut_a_mem_6_size),\n .io_async_mem_6_source (nodeOut_a_mem_6_source),\n .io_async_mem_6_address (nodeOut_a_mem_6_address),\n .io_async_mem_6_mask (nodeOut_a_mem_6_mask),\n .io_async_mem_6_data (nodeOut_a_mem_6_data),\n .io_async_mem_7_opcode (nodeOut_a_mem_7_opcode),\n .io_async_mem_7_param (nodeOut_a_mem_7_param),\n .io_async_mem_7_size (nodeOut_a_mem_7_size),\n .io_async_mem_7_source (nodeOut_a_mem_7_source),\n .io_async_mem_7_address (nodeOut_a_mem_7_address),\n .io_async_mem_7_mask (nodeOut_a_mem_7_mask),\n .io_async_mem_7_data (nodeOut_a_mem_7_data),\n .io_async_ridx (nodeOut_a_ridx),\t// @[MixedNode.scala:542:17]\n .io_async_widx (nodeOut_a_widx),\n .io_async_safe_ridx_valid (nodeOut_a_safe_ridx_valid),\t// @[MixedNode.scala:542:17]\n .io_async_safe_widx_valid (nodeOut_a_safe_widx_valid),\n .io_async_safe_source_reset_n (nodeOut_a_safe_source_reset_n),\n .io_async_safe_sink_reset_n (nodeOut_a_safe_sink_reset_n)\t// @[MixedNode.scala:542:17]\n );\t// @[AsyncQueue.scala:220:24]\n AsyncQueueSink_TLBundleD_a32d64s2k3z4c nodeIn_d_sink (\t// @[AsyncQueue.scala:211:22]\n .clock (clock),\n .reset (reset),\n .io_deq_ready (nodeIn_d_ready),\t// @[MixedNode.scala:551:17]\n .io_deq_valid (nodeIn_d_valid),\n .io_deq_bits_opcode (nodeIn_d_bits_opcode),\n .io_deq_bits_param (nodeIn_d_bits_param),\n .io_deq_bits_size (nodeIn_d_bits_size),\n .io_deq_bits_source (nodeIn_d_bits_source),\n .io_deq_bits_sink (nodeIn_d_bits_sink),\n .io_deq_bits_denied (nodeIn_d_bits_denied),\n .io_deq_bits_data (nodeIn_d_bits_data),\n .io_deq_bits_corrupt (nodeIn_d_bits_corrupt),\n .io_async_mem_0_opcode (nodeOut_d_mem_0_opcode),\t// @[MixedNode.scala:542:17]\n .io_async_mem_0_param (nodeOut_d_mem_0_param),\t// @[MixedNode.scala:542:17]\n .io_async_mem_0_size (nodeOut_d_mem_0_size),\t// @[MixedNode.scala:542:17]\n .io_async_mem_0_source (nodeOut_d_mem_0_source),\t// @[MixedNode.scala:542:17]\n .io_async_mem_0_sink (nodeOut_d_mem_0_sink),\t// @[MixedNode.scala:542:17]\n .io_async_mem_0_denied (nodeOut_d_mem_0_denied),\t// @[MixedNode.scala:542:17]\n .io_async_mem_0_data (nodeOut_d_mem_0_data),\t// @[MixedNode.scala:542:17]\n .io_async_mem_0_corrupt (nodeOut_d_mem_0_corrupt),\t// @[MixedNode.scala:542:17]\n .io_async_mem_1_opcode (nodeOut_d_mem_1_opcode),\t// @[MixedNode.scala:542:17]\n .io_async_mem_1_param (nodeOut_d_mem_1_param),\t// @[MixedNode.scala:542:17]\n .io_async_mem_1_size (nodeOut_d_mem_1_size),\t// @[MixedNode.scala:542:17]\n .io_async_mem_1_source (nodeOut_d_mem_1_source),\t// @[MixedNode.scala:542:17]\n .io_async_mem_1_sink (nodeOut_d_mem_1_sink),\t// @[MixedNode.scala:542:17]\n .io_async_mem_1_denied (nodeOut_d_mem_1_denied),\t// @[MixedNode.scala:542:17]\n .io_async_mem_1_data (nodeOut_d_mem_1_data),\t// @[MixedNode.scala:542:17]\n .io_async_mem_1_corrupt (nodeOut_d_mem_1_corrupt),\t// @[MixedNode.scala:542:17]\n .io_async_mem_2_opcode (nodeOut_d_mem_2_opcode),\t// @[MixedNode.scala:542:17]\n .io_async_mem_2_param (nodeOut_d_mem_2_param),\t// @[MixedNode.scala:542:17]\n .io_async_mem_2_size (nodeOut_d_mem_2_size),\t// @[MixedNode.scala:542:17]\n .io_async_mem_2_source (nodeOut_d_mem_2_source),\t// @[MixedNode.scala:542:17]\n .io_async_mem_2_sink (nodeOut_d_mem_2_sink),\t// @[MixedNode.scala:542:17]\n .io_async_mem_2_denied (nodeOut_d_mem_2_denied),\t// @[MixedNode.scala:542:17]\n .io_async_mem_2_data (nodeOut_d_mem_2_data),\t// @[MixedNode.scala:542:17]\n .io_async_mem_2_corrupt (nodeOut_d_mem_2_corrupt),\t// @[MixedNode.scala:542:17]\n .io_async_mem_3_opcode (nodeOut_d_mem_3_opcode),\t// @[MixedNode.scala:542:17]\n .io_async_mem_3_param (nodeOut_d_mem_3_param),\t// @[MixedNode.scala:542:17]\n .io_async_mem_3_size (nodeOut_d_mem_3_size),\t// @[MixedNode.scala:542:17]\n .io_async_mem_3_source (nodeOut_d_mem_3_source),\t// @[MixedNode.scala:542:17]\n .io_async_mem_3_sink (nodeOut_d_mem_3_sink),\t// @[MixedNode.scala:542:17]\n .io_async_mem_3_denied (nodeOut_d_mem_3_denied),\t// @[MixedNode.scala:542:17]\n .io_async_mem_3_data (nodeOut_d_mem_3_data),\t// @[MixedNode.scala:542:17]\n .io_async_mem_3_corrupt (nodeOut_d_mem_3_corrupt),\t// @[MixedNode.scala:542:17]\n .io_async_mem_4_opcode (nodeOut_d_mem_4_opcode),\t// @[MixedNode.scala:542:17]\n .io_async_mem_4_param (nodeOut_d_mem_4_param),\t// @[MixedNode.scala:542:17]\n .io_async_mem_4_size (nodeOut_d_mem_4_size),\t// @[MixedNode.scala:542:17]\n .io_async_mem_4_source (nodeOut_d_mem_4_source),\t// @[MixedNode.scala:542:17]\n .io_async_mem_4_sink (nodeOut_d_mem_4_sink),\t// @[MixedNode.scala:542:17]\n .io_async_mem_4_denied (nodeOut_d_mem_4_denied),\t// @[MixedNode.scala:542:17]\n .io_async_mem_4_data (nodeOut_d_mem_4_data),\t// @[MixedNode.scala:542:17]\n .io_async_mem_4_corrupt (nodeOut_d_mem_4_corrupt),\t// @[MixedNode.scala:542:17]\n .io_async_mem_5_opcode (nodeOut_d_mem_5_opcode),\t// @[MixedNode.scala:542:17]\n .io_async_mem_5_param (nodeOut_d_mem_5_param),\t// @[MixedNode.scala:542:17]\n .io_async_mem_5_size (nodeOut_d_mem_5_size),\t// @[MixedNode.scala:542:17]\n .io_async_mem_5_source (nodeOut_d_mem_5_source),\t// @[MixedNode.scala:542:17]\n .io_async_mem_5_sink (nodeOut_d_mem_5_sink),\t// @[MixedNode.scala:542:17]\n .io_async_mem_5_denied (nodeOut_d_mem_5_denied),\t// @[MixedNode.scala:542:17]\n .io_async_mem_5_data (nodeOut_d_mem_5_data),\t// @[MixedNode.scala:542:17]\n .io_async_mem_5_corrupt (nodeOut_d_mem_5_corrupt),\t// @[MixedNode.scala:542:17]\n .io_async_mem_6_opcode (nodeOut_d_mem_6_opcode),\t// @[MixedNode.scala:542:17]\n .io_async_mem_6_param (nodeOut_d_mem_6_param),\t// @[MixedNode.scala:542:17]\n .io_async_mem_6_size (nodeOut_d_mem_6_size),\t// @[MixedNode.scala:542:17]\n .io_async_mem_6_source (nodeOut_d_mem_6_source),\t// @[MixedNode.scala:542:17]\n .io_async_mem_6_sink (nodeOut_d_mem_6_sink),\t// @[MixedNode.scala:542:17]\n .io_async_mem_6_denied (nodeOut_d_mem_6_denied),\t// @[MixedNode.scala:542:17]\n .io_async_mem_6_data (nodeOut_d_mem_6_data),\t// @[MixedNode.scala:542:17]\n .io_async_mem_6_corrupt (nodeOut_d_mem_6_corrupt),\t// @[MixedNode.scala:542:17]\n .io_async_mem_7_opcode (nodeOut_d_mem_7_opcode),\t// @[MixedNode.scala:542:17]\n .io_async_mem_7_param (nodeOut_d_mem_7_param),\t// @[MixedNode.scala:542:17]\n .io_async_mem_7_size (nodeOut_d_mem_7_size),\t// @[MixedNode.scala:542:17]\n .io_async_mem_7_source (nodeOut_d_mem_7_source),\t// @[MixedNode.scala:542:17]\n .io_async_mem_7_sink (nodeOut_d_mem_7_sink),\t// @[MixedNode.scala:542:17]\n .io_async_mem_7_denied (nodeOut_d_mem_7_denied),\t// @[MixedNode.scala:542:17]\n .io_async_mem_7_data (nodeOut_d_mem_7_data),\t// @[MixedNode.scala:542:17]\n .io_async_mem_7_corrupt (nodeOut_d_mem_7_corrupt),\t// @[MixedNode.scala:542:17]\n .io_async_ridx (nodeOut_d_ridx),\n .io_async_widx (nodeOut_d_widx),\t// @[MixedNode.scala:542:17]\n .io_async_safe_ridx_valid (nodeOut_d_safe_ridx_valid),\n .io_async_safe_widx_valid (nodeOut_d_safe_widx_valid),\t// @[MixedNode.scala:542:17]\n .io_async_safe_source_reset_n (nodeOut_d_safe_source_reset_n),\t// @[MixedNode.scala:542:17]\n .io_async_safe_sink_reset_n (nodeOut_d_safe_sink_reset_n)\n );\t// @[AsyncQueue.scala:211:22]\n AsyncQueueSink_TLBundleB_a32d64s2k3z4c nodeIn_b_sink (\t// @[AsyncQueue.scala:211:22]\n .clock (clock),\n .reset (reset),\n .io_deq_ready (nodeIn_b_ready),\t// @[MixedNode.scala:551:17]\n .io_deq_valid (nodeIn_b_valid),\n .io_deq_bits_opcode (nodeIn_b_bits_opcode),\n .io_deq_bits_param (nodeIn_b_bits_param),\n .io_deq_bits_size (nodeIn_b_bits_size),\n .io_deq_bits_source (nodeIn_b_bits_source),\n .io_deq_bits_address (nodeIn_b_bits_address),\n .io_deq_bits_mask (nodeIn_b_bits_mask),\n .io_deq_bits_data (nodeIn_b_bits_data),\n .io_deq_bits_corrupt (nodeIn_b_bits_corrupt),\n .io_async_mem_0_param (nodeOut_b_mem_0_param),\t// @[MixedNode.scala:542:17]\n .io_async_mem_0_address (nodeOut_b_mem_0_address),\t// @[MixedNode.scala:542:17]\n .io_async_mem_1_param (nodeOut_b_mem_1_param),\t// @[MixedNode.scala:542:17]\n .io_async_mem_1_address (nodeOut_b_mem_1_address),\t// @[MixedNode.scala:542:17]\n .io_async_mem_2_param (nodeOut_b_mem_2_param),\t// @[MixedNode.scala:542:17]\n .io_async_mem_2_address (nodeOut_b_mem_2_address),\t// @[MixedNode.scala:542:17]\n .io_async_mem_3_param (nodeOut_b_mem_3_param),\t// @[MixedNode.scala:542:17]\n .io_async_mem_3_address (nodeOut_b_mem_3_address),\t// @[MixedNode.scala:542:17]\n .io_async_mem_4_param (nodeOut_b_mem_4_param),\t// @[MixedNode.scala:542:17]\n .io_async_mem_4_address (nodeOut_b_mem_4_address),\t// @[MixedNode.scala:542:17]\n .io_async_mem_5_param (nodeOut_b_mem_5_param),\t// @[MixedNode.scala:542:17]\n .io_async_mem_5_address (nodeOut_b_mem_5_address),\t// @[MixedNode.scala:542:17]\n .io_async_mem_6_param (nodeOut_b_mem_6_param),\t// @[MixedNode.scala:542:17]\n .io_async_mem_6_address (nodeOut_b_mem_6_address),\t// @[MixedNode.scala:542:17]\n .io_async_mem_7_param (nodeOut_b_mem_7_param),\t// @[MixedNode.scala:542:17]\n .io_async_mem_7_address (nodeOut_b_mem_7_address),\t// @[MixedNode.scala:542:17]\n .io_async_ridx (nodeOut_b_ridx),\n .io_async_widx (nodeOut_b_widx),\t// @[MixedNode.scala:542:17]\n .io_async_safe_ridx_valid (nodeOut_b_safe_ridx_valid),\n .io_async_safe_widx_valid (nodeOut_b_safe_widx_valid),\t// @[MixedNode.scala:542:17]\n .io_async_safe_source_reset_n (nodeOut_b_safe_source_reset_n),\t// @[MixedNode.scala:542:17]\n .io_async_safe_sink_reset_n (nodeOut_b_safe_sink_reset_n)\n );\t// @[AsyncQueue.scala:211:22]\n AsyncQueueSource_TLBundleC_a32d64s2k3z4c nodeOut_c_source (\t// @[AsyncQueue.scala:220:24]\n .clock (clock),\n .reset (reset),\n .io_enq_ready (nodeIn_c_ready),\n .io_enq_valid (nodeIn_c_valid),\t// @[MixedNode.scala:551:17]\n .io_enq_bits_opcode (nodeIn_c_bits_opcode),\t// @[MixedNode.scala:551:17]\n .io_enq_bits_param (nodeIn_c_bits_param),\t// @[MixedNode.scala:551:17]\n .io_enq_bits_size (nodeIn_c_bits_size),\t// @[MixedNode.scala:551:17]\n .io_enq_bits_source (nodeIn_c_bits_source),\t// @[MixedNode.scala:551:17]\n .io_enq_bits_address (nodeIn_c_bits_address),\t// @[MixedNode.scala:551:17]\n .io_enq_bits_data (nodeIn_c_bits_data),\t// @[MixedNode.scala:551:17]\n .io_async_mem_0_opcode (nodeOut_c_mem_0_opcode),\n .io_async_mem_0_param (nodeOut_c_mem_0_param),\n .io_async_mem_0_size (nodeOut_c_mem_0_size),\n .io_async_mem_0_source (nodeOut_c_mem_0_source),\n .io_async_mem_0_address (nodeOut_c_mem_0_address),\n .io_async_mem_0_data (nodeOut_c_mem_0_data),\n .io_async_mem_1_opcode (nodeOut_c_mem_1_opcode),\n .io_async_mem_1_param (nodeOut_c_mem_1_param),\n .io_async_mem_1_size (nodeOut_c_mem_1_size),\n .io_async_mem_1_source (nodeOut_c_mem_1_source),\n .io_async_mem_1_address (nodeOut_c_mem_1_address),\n .io_async_mem_1_data (nodeOut_c_mem_1_data),\n .io_async_mem_2_opcode (nodeOut_c_mem_2_opcode),\n .io_async_mem_2_param (nodeOut_c_mem_2_param),\n .io_async_mem_2_size (nodeOut_c_mem_2_size),\n .io_async_mem_2_source (nodeOut_c_mem_2_source),\n .io_async_mem_2_address (nodeOut_c_mem_2_address),\n .io_async_mem_2_data (nodeOut_c_mem_2_data),\n .io_async_mem_3_opcode (nodeOut_c_mem_3_opcode),\n .io_async_mem_3_param (nodeOut_c_mem_3_param),\n .io_async_mem_3_size (nodeOut_c_mem_3_size),\n .io_async_mem_3_source (nodeOut_c_mem_3_source),\n .io_async_mem_3_address (nodeOut_c_mem_3_address),\n .io_async_mem_3_data (nodeOut_c_mem_3_data),\n .io_async_mem_4_opcode (nodeOut_c_mem_4_opcode),\n .io_async_mem_4_param (nodeOut_c_mem_4_param),\n .io_async_mem_4_size (nodeOut_c_mem_4_size),\n .io_async_mem_4_source (nodeOut_c_mem_4_source),\n .io_async_mem_4_address (nodeOut_c_mem_4_address),\n .io_async_mem_4_data (nodeOut_c_mem_4_data),\n .io_async_mem_5_opcode (nodeOut_c_mem_5_opcode),\n .io_async_mem_5_param (nodeOut_c_mem_5_param),\n .io_async_mem_5_size (nodeOut_c_mem_5_size),\n .io_async_mem_5_source (nodeOut_c_mem_5_source),\n .io_async_mem_5_address (nodeOut_c_mem_5_address),\n .io_async_mem_5_data (nodeOut_c_mem_5_data),\n .io_async_mem_6_opcode (nodeOut_c_mem_6_opcode),\n .io_async_mem_6_param (nodeOut_c_mem_6_param),\n .io_async_mem_6_size (nodeOut_c_mem_6_size),\n .io_async_mem_6_source (nodeOut_c_mem_6_source),\n .io_async_mem_6_address (nodeOut_c_mem_6_address),\n .io_async_mem_6_data (nodeOut_c_mem_6_data),\n .io_async_mem_7_opcode (nodeOut_c_mem_7_opcode),\n .io_async_mem_7_param (nodeOut_c_mem_7_param),\n .io_async_mem_7_size (nodeOut_c_mem_7_size),\n .io_async_mem_7_source (nodeOut_c_mem_7_source),\n .io_async_mem_7_address (nodeOut_c_mem_7_address),\n .io_async_mem_7_data (nodeOut_c_mem_7_data),\n .io_async_ridx (nodeOut_c_ridx),\t// @[MixedNode.scala:542:17]\n .io_async_widx (nodeOut_c_widx),\n .io_async_safe_ridx_valid (nodeOut_c_safe_ridx_valid),\t// @[MixedNode.scala:542:17]\n .io_async_safe_widx_valid (nodeOut_c_safe_widx_valid),\n .io_async_safe_source_reset_n (nodeOut_c_safe_source_reset_n),\n .io_async_safe_sink_reset_n (nodeOut_c_safe_sink_reset_n)\t// @[MixedNode.scala:542:17]\n );\t// @[AsyncQueue.scala:220:24]\n AsyncQueueSource_TLBundleE_a32d64s2k3z4c nodeOut_e_source (\t// @[AsyncQueue.scala:220:24]\n .clock (clock),\n .reset (reset),\n .io_enq_ready (nodeIn_e_ready),\n .io_enq_valid (nodeIn_e_valid),\t// @[MixedNode.scala:551:17]\n .io_enq_bits_sink (nodeIn_e_bits_sink),\t// @[MixedNode.scala:551:17]\n .io_async_mem_0_sink (nodeOut_e_mem_0_sink),\n .io_async_mem_1_sink (nodeOut_e_mem_1_sink),\n .io_async_mem_2_sink (nodeOut_e_mem_2_sink),\n .io_async_mem_3_sink (nodeOut_e_mem_3_sink),\n .io_async_mem_4_sink (nodeOut_e_mem_4_sink),\n .io_async_mem_5_sink (nodeOut_e_mem_5_sink),\n .io_async_mem_6_sink (nodeOut_e_mem_6_sink),\n .io_async_mem_7_sink (nodeOut_e_mem_7_sink),\n .io_async_ridx (nodeOut_e_ridx),\t// @[MixedNode.scala:542:17]\n .io_async_widx (nodeOut_e_widx),\n .io_async_safe_ridx_valid (nodeOut_e_safe_ridx_valid),\t// @[MixedNode.scala:542:17]\n .io_async_safe_widx_valid (nodeOut_e_safe_widx_valid),\n .io_async_safe_source_reset_n (nodeOut_e_safe_source_reset_n),\n .io_async_safe_sink_reset_n (nodeOut_e_safe_sink_reset_n)\t// @[MixedNode.scala:542:17]\n );\t// @[AsyncQueue.scala:220:24]\n assign auto_in_a_ready = auto_in_a_ready_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_in_b_valid = auto_in_b_valid_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_in_b_bits_opcode = auto_in_b_bits_opcode_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_in_b_bits_param = auto_in_b_bits_param_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_in_b_bits_size = auto_in_b_bits_size_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_in_b_bits_source = auto_in_b_bits_source_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_in_b_bits_address = auto_in_b_bits_address_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_in_b_bits_mask = auto_in_b_bits_mask_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_in_b_bits_data = auto_in_b_bits_data_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_in_b_bits_corrupt = auto_in_b_bits_corrupt_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_in_c_ready = auto_in_c_ready_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_in_d_valid = auto_in_d_valid_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_in_d_bits_param = auto_in_d_bits_param_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_in_d_bits_size = auto_in_d_bits_size_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_in_d_bits_source = auto_in_d_bits_source_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_in_d_bits_sink = auto_in_d_bits_sink_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_in_d_bits_denied = auto_in_d_bits_denied_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_in_d_bits_data = auto_in_d_bits_data_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_in_e_ready = auto_in_e_ready_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_0_opcode = auto_out_a_mem_0_opcode_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_0_param = auto_out_a_mem_0_param_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_0_size = auto_out_a_mem_0_size_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_0_source = auto_out_a_mem_0_source_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_0_address = auto_out_a_mem_0_address_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_0_mask = auto_out_a_mem_0_mask_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_0_data = auto_out_a_mem_0_data_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_1_opcode = auto_out_a_mem_1_opcode_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_1_param = auto_out_a_mem_1_param_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_1_size = auto_out_a_mem_1_size_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_1_source = auto_out_a_mem_1_source_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_1_address = auto_out_a_mem_1_address_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_1_mask = auto_out_a_mem_1_mask_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_1_data = auto_out_a_mem_1_data_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_2_opcode = auto_out_a_mem_2_opcode_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_2_param = auto_out_a_mem_2_param_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_2_size = auto_out_a_mem_2_size_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_2_source = auto_out_a_mem_2_source_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_2_address = auto_out_a_mem_2_address_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_2_mask = auto_out_a_mem_2_mask_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_2_data = auto_out_a_mem_2_data_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_3_opcode = auto_out_a_mem_3_opcode_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_3_param = auto_out_a_mem_3_param_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_3_size = auto_out_a_mem_3_size_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_3_source = auto_out_a_mem_3_source_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_3_address = auto_out_a_mem_3_address_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_3_mask = auto_out_a_mem_3_mask_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_3_data = auto_out_a_mem_3_data_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_4_opcode = auto_out_a_mem_4_opcode_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_4_param = auto_out_a_mem_4_param_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_4_size = auto_out_a_mem_4_size_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_4_source = auto_out_a_mem_4_source_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_4_address = auto_out_a_mem_4_address_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_4_mask = auto_out_a_mem_4_mask_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_4_data = auto_out_a_mem_4_data_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_5_opcode = auto_out_a_mem_5_opcode_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_5_param = auto_out_a_mem_5_param_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_5_size = auto_out_a_mem_5_size_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_5_source = auto_out_a_mem_5_source_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_5_address = auto_out_a_mem_5_address_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_5_mask = auto_out_a_mem_5_mask_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_5_data = auto_out_a_mem_5_data_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_6_opcode = auto_out_a_mem_6_opcode_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_6_param = auto_out_a_mem_6_param_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_6_size = auto_out_a_mem_6_size_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_6_source = auto_out_a_mem_6_source_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_6_address = auto_out_a_mem_6_address_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_6_mask = auto_out_a_mem_6_mask_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_6_data = auto_out_a_mem_6_data_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_7_opcode = auto_out_a_mem_7_opcode_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_7_param = auto_out_a_mem_7_param_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_7_size = auto_out_a_mem_7_size_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_7_source = auto_out_a_mem_7_source_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_7_address = auto_out_a_mem_7_address_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_7_mask = auto_out_a_mem_7_mask_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_mem_7_data = auto_out_a_mem_7_data_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_widx = auto_out_a_widx_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_safe_widx_valid = auto_out_a_safe_widx_valid_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_a_safe_source_reset_n = auto_out_a_safe_source_reset_n_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_b_ridx = auto_out_b_ridx_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_b_safe_ridx_valid = auto_out_b_safe_ridx_valid_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_b_safe_sink_reset_n = auto_out_b_safe_sink_reset_n_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_0_opcode = auto_out_c_mem_0_opcode_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_0_param = auto_out_c_mem_0_param_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_0_size = auto_out_c_mem_0_size_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_0_source = auto_out_c_mem_0_source_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_0_address = auto_out_c_mem_0_address_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_0_data = auto_out_c_mem_0_data_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_1_opcode = auto_out_c_mem_1_opcode_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_1_param = auto_out_c_mem_1_param_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_1_size = auto_out_c_mem_1_size_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_1_source = auto_out_c_mem_1_source_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_1_address = auto_out_c_mem_1_address_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_1_data = auto_out_c_mem_1_data_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_2_opcode = auto_out_c_mem_2_opcode_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_2_param = auto_out_c_mem_2_param_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_2_size = auto_out_c_mem_2_size_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_2_source = auto_out_c_mem_2_source_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_2_address = auto_out_c_mem_2_address_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_2_data = auto_out_c_mem_2_data_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_3_opcode = auto_out_c_mem_3_opcode_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_3_param = auto_out_c_mem_3_param_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_3_size = auto_out_c_mem_3_size_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_3_source = auto_out_c_mem_3_source_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_3_address = auto_out_c_mem_3_address_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_3_data = auto_out_c_mem_3_data_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_4_opcode = auto_out_c_mem_4_opcode_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_4_param = auto_out_c_mem_4_param_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_4_size = auto_out_c_mem_4_size_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_4_source = auto_out_c_mem_4_source_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_4_address = auto_out_c_mem_4_address_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_4_data = auto_out_c_mem_4_data_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_5_opcode = auto_out_c_mem_5_opcode_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_5_param = auto_out_c_mem_5_param_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_5_size = auto_out_c_mem_5_size_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_5_source = auto_out_c_mem_5_source_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_5_address = auto_out_c_mem_5_address_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_5_data = auto_out_c_mem_5_data_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_6_opcode = auto_out_c_mem_6_opcode_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_6_param = auto_out_c_mem_6_param_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_6_size = auto_out_c_mem_6_size_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_6_source = auto_out_c_mem_6_source_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_6_address = auto_out_c_mem_6_address_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_6_data = auto_out_c_mem_6_data_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_7_opcode = auto_out_c_mem_7_opcode_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_7_param = auto_out_c_mem_7_param_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_7_size = auto_out_c_mem_7_size_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_7_source = auto_out_c_mem_7_source_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_7_address = auto_out_c_mem_7_address_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_mem_7_data = auto_out_c_mem_7_data_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_widx = auto_out_c_widx_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_safe_widx_valid = auto_out_c_safe_widx_valid_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_c_safe_source_reset_n = auto_out_c_safe_source_reset_n_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_d_ridx = auto_out_d_ridx_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_d_safe_ridx_valid = auto_out_d_safe_ridx_valid_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_d_safe_sink_reset_n = auto_out_d_safe_sink_reset_n_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_e_mem_0_sink = auto_out_e_mem_0_sink_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_e_mem_1_sink = auto_out_e_mem_1_sink_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_e_mem_2_sink = auto_out_e_mem_2_sink_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_e_mem_3_sink = auto_out_e_mem_3_sink_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_e_mem_4_sink = auto_out_e_mem_4_sink_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_e_mem_5_sink = auto_out_e_mem_5_sink_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_e_mem_6_sink = auto_out_e_mem_6_sink_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_e_mem_7_sink = auto_out_e_mem_7_sink_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_e_widx = auto_out_e_widx_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_e_safe_widx_valid = auto_out_e_safe_widx_valid_0;\t// @[AsyncCrossing.scala:23:9]\n assign auto_out_e_safe_source_reset_n = auto_out_e_safe_source_reset_n_0;\t// @[AsyncCrossing.scala:23:9]\nendmodule"}}},{"rowIdx":578,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to the following Chisel files.\nFile ShiftReg.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3._\n\n// Similar to the Chisel ShiftRegister but allows the user to suggest a\n// name to the registers that get instantiated, and\n// to provide a reset value.\nobject ShiftRegInit {\n def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =\n\n (0 until n).foldRight(in) {\n case (i, next) => {\n val r = RegNext(next, init)\n name.foreach { na => r.suggestName(s\"${na}_${i}\") }\n r\n }\n }\n}\n\n/** These wrap behavioral\n * shift registers into specific modules to allow for\n * backend flows to replace or constrain\n * them properly when used for CDC synchronization,\n * rather than buffering.\n * \n * The different types vary in their reset behavior:\n * AsyncResetShiftReg -- Asynchronously reset register array\n * A W(width) x D(depth) sized array is constructed from D instantiations of a\n * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,\n * but only used for timing applications\n */\n\nabstract class AbstractPipelineReg(w: Int = 1) extends Module {\n val io = IO(new Bundle {\n val d = Input(UInt(w.W))\n val q = Output(UInt(w.W))\n }\n )\n}\n\nobject AbstractPipelineReg {\n def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {\n val chain = Module(gen)\n name.foreach{ chain.suggestName(_) }\n chain.io.d := in.asUInt\n chain.io.q.asTypeOf(in)\n }\n}\n\nclass AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = \"pipe\") extends AbstractPipelineReg(w) {\n require(depth > 0, \"Depth must be greater than 0.\")\n\n override def desiredName = s\"AsyncResetShiftReg_w${w}_d${depth}_i${init}\"\n\n val chain = List.tabulate(depth) { i =>\n Module (new AsyncResetRegVec(w, init)).suggestName(s\"${name}_${i}\")\n }\n\n chain.last.io.d := io.d\n chain.last.io.en := true.B\n\n (chain.init zip chain.tail).foreach { case (sink, source) =>\n sink.io.d := source.io.q\n sink.io.en := true.B\n }\n io.q := chain.head.io.q\n}\n\nobject AsyncResetShiftReg {\n def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =\n AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)\n\n def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =\n apply(in, depth, 0, name)\n\n def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =\n apply(in, depth, init.litValue.toInt, name)\n\n def apply [T <: Data](in: T, depth: Int, init: T): T =\n apply (in, depth, init.litValue.toInt, None)\n}\nFile AsyncQueue.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3._\nimport chisel3.util._\n\ncase class AsyncQueueParams(\n depth: Int = 8,\n sync: Int = 3,\n safe: Boolean = true,\n// If safe is true, then effort is made to resynchronize the crossing indices when either side is reset.\n// This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty.\n narrow: Boolean = false)\n// If narrow is true then the read mux is moved to the source side of the crossing.\n// This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing,\n// at the expense of a combinational path from the sink to the source and back to the sink.\n{\n require (depth > 0 && isPow2(depth))\n require (sync >= 2)\n\n val bits = log2Ceil(depth)\n val wires = if (narrow) 1 else depth\n}\n\nobject AsyncQueueParams {\n // When there is only one entry, we don't need narrow.\n def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false)\n}\n\nclass AsyncBundleSafety extends Bundle {\n val ridx_valid = Input (Bool())\n val widx_valid = Output(Bool())\n val source_reset_n = Output(Bool())\n val sink_reset_n = Input (Bool())\n}\n\nclass AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle {\n // Data-path synchronization\n val mem = Output(Vec(params.wires, gen))\n val ridx = Input (UInt((params.bits+1).W))\n val widx = Output(UInt((params.bits+1).W))\n val index = params.narrow.option(Input(UInt(params.bits.W)))\n\n // Signals used to self-stabilize a safe AsyncQueue\n val safe = params.safe.option(new AsyncBundleSafety)\n}\n\nobject GrayCounter {\n def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = \"binary\"): UInt = {\n val incremented = Wire(UInt(bits.W))\n val binary = RegNext(next=incremented, init=0.U).suggestName(name)\n incremented := Mux(clear, 0.U, binary + increment.asUInt)\n incremented ^ (incremented >> 1)\n }\n}\n\nclass AsyncValidSync(sync: Int, desc: String) extends RawModule {\n val io = IO(new Bundle {\n val in = Input(Bool())\n val out = Output(Bool())\n })\n val clock = IO(Input(Clock()))\n val reset = IO(Input(AsyncReset()))\n withClockAndReset(clock, reset){\n io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc))\n }\n}\n\nclass AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {\n override def desiredName = s\"AsyncQueueSource_${gen.typeName}\"\n\n val io = IO(new Bundle {\n // These come from the source domain\n val enq = Flipped(Decoupled(gen))\n // These cross to the sink clock domain\n val async = new AsyncBundle(gen, params)\n })\n\n val bits = params.bits\n val sink_ready = WireInit(true.B)\n val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all.\n val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, \"widx_bin\"))\n val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some(\"ridx_gray\"))\n val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U)\n\n val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1))\n when (io.enq.fire) { mem(index) := io.enq.bits }\n\n val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName(\"ready_reg\"))\n io.enq.ready := ready_reg && sink_ready\n\n val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName(\"widx_gray\"))\n io.async.widx := widx_reg\n\n io.async.index match {\n case Some(index) => io.async.mem(0) := mem(index)\n case None => io.async.mem := mem\n }\n\n io.async.safe.foreach { sio =>\n val source_valid_0 = Module(new AsyncValidSync(params.sync, \"source_valid_0\"))\n val source_valid_1 = Module(new AsyncValidSync(params.sync, \"source_valid_1\"))\n\n val sink_extend = Module(new AsyncValidSync(params.sync, \"sink_extend\"))\n val sink_valid = Module(new AsyncValidSync(params.sync, \"sink_valid\"))\n source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset\n source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset\n sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset\n sink_valid .reset := reset.asAsyncReset\n\n source_valid_0.clock := clock\n source_valid_1.clock := clock\n sink_extend .clock := clock\n sink_valid .clock := clock\n\n source_valid_0.io.in := true.B\n source_valid_1.io.in := source_valid_0.io.out\n sio.widx_valid := source_valid_1.io.out\n sink_extend.io.in := sio.ridx_valid\n sink_valid.io.in := sink_extend.io.out\n sink_ready := sink_valid.io.out\n sio.source_reset_n := !reset.asBool\n\n // Assert that if there is stuff in the queue, then reset cannot happen\n // Impossible to write because dequeue can occur on the receiving side,\n // then reset allowed to happen, but write side cannot know that dequeue\n // occurred.\n // TODO: write some sort of sanity check assertion for users\n // that denote don't reset when there is activity\n // assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, \"Enqueue while sink is reset and AsyncQueueSource is unprotected\")\n // assert (!reset_rise || prev_idx_match.asBool, \"Sink reset while AsyncQueueSource not empty\")\n }\n}\n\nclass AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {\n override def desiredName = s\"AsyncQueueSink_${gen.typeName}\"\n\n val io = IO(new Bundle {\n // These come from the sink domain\n val deq = Decoupled(gen)\n // These cross to the source clock domain\n val async = Flipped(new AsyncBundle(gen, params))\n })\n\n val bits = params.bits\n val source_ready = WireInit(true.B)\n val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, \"ridx_bin\"))\n val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some(\"widx_gray\"))\n val valid = source_ready && ridx =/= widx\n\n // The mux is safe because timing analysis ensures ridx has reached the register\n // On an ASIC, changes to the unread location cannot affect the selected value\n // On an FPGA, only one input changes at a time => mem updates don't cause glitches\n // The register only latches when the selected valued is not being written\n val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1))\n io.async.index.foreach { _ := index }\n // This register does not NEED to be reset, as its contents will not\n // be considered unless the asynchronously reset deq valid register is set.\n // It is possible that bits latches when the source domain is reset / has power cut\n // This is safe, because isolation gates brought mem low before the zeroed widx reached us\n val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index)\n io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some(\"deq_bits_reg\"))\n\n val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName(\"valid_reg\"))\n io.deq.valid := valid_reg && source_ready\n\n val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName(\"ridx_gray\"))\n io.async.ridx := ridx_reg\n\n io.async.safe.foreach { sio =>\n val sink_valid_0 = Module(new AsyncValidSync(params.sync, \"sink_valid_0\"))\n val sink_valid_1 = Module(new AsyncValidSync(params.sync, \"sink_valid_1\"))\n\n val source_extend = Module(new AsyncValidSync(params.sync, \"source_extend\"))\n val source_valid = Module(new AsyncValidSync(params.sync, \"source_valid\"))\n sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset\n sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset\n source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset\n source_valid .reset := reset.asAsyncReset\n\n sink_valid_0 .clock := clock\n sink_valid_1 .clock := clock\n source_extend.clock := clock\n source_valid .clock := clock\n\n sink_valid_0.io.in := true.B\n sink_valid_1.io.in := sink_valid_0.io.out\n sio.ridx_valid := sink_valid_1.io.out\n source_extend.io.in := sio.widx_valid\n source_valid.io.in := source_extend.io.out\n source_ready := source_valid.io.out\n sio.sink_reset_n := !reset.asBool\n\n // TODO: write some sort of sanity check assertion for users\n // that denote don't reset when there is activity\n // \n // val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool\n // val reset_and_extend_prev = RegNext(reset_and_extend, true.B)\n // val reset_rise = !reset_and_extend_prev && reset_and_extend\n // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0)\n // assert (!reset_rise || prev_idx_match.asBool, \"Source reset while AsyncQueueSink not empty\")\n }\n}\n\nobject FromAsyncBundle\n{\n // Sometimes it makes sense for the sink to have different sync than the source\n def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync)\n def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = {\n val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync)))\n sink.io.async <> x\n sink.io.deq\n }\n}\n\nobject ToAsyncBundle\n{\n def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = {\n val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params))\n source.io.enq <> x\n source.io.async\n }\n}\n\nclass AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] {\n val io = IO(new CrossingIO(gen))\n val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) }\n val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) }\n\n source.io.enq <> io.enq\n io.deq <> sink.io.deq\n sink.io.async <> source.io.async\n}\n"},"response":{"kind":"string","value":"module AsyncValidSync_58(\t// @[AsyncQueue.scala:58:7]\n input io_in,\t// @[AsyncQueue.scala:59:14]\n output io_out,\t// @[AsyncQueue.scala:59:14]\n input clock,\t// @[AsyncQueue.scala:63:17]\n input reset\t// @[AsyncQueue.scala:64:17]\n);\n\n wire io_in_0 = io_in;\t// @[AsyncQueue.scala:58:7]\n wire _io_out_WIRE;\t// @[ShiftReg.scala:48:24]\n wire io_out_0;\t// @[AsyncQueue.scala:58:7]\n assign io_out_0 = _io_out_WIRE;\t// @[ShiftReg.scala:48:24]\n AsyncResetSynchronizerShiftReg_w1_d3_i0_68 io_out_sink_extend (\t// @[ShiftReg.scala:45:23]\n .clock (clock),\n .reset (reset),\n .io_d (io_in_0),\t// @[AsyncQueue.scala:58:7]\n .io_q (_io_out_WIRE)\n );\t// @[ShiftReg.scala:45:23]\n assign io_out = io_out_0;\t// @[AsyncQueue.scala:58:7]\nendmodule"}}},{"rowIdx":579,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to the following Chisel files.\nFile ShiftReg.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3._\n\n// Similar to the Chisel ShiftRegister but allows the user to suggest a\n// name to the registers that get instantiated, and\n// to provide a reset value.\nobject ShiftRegInit {\n def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =\n\n (0 until n).foldRight(in) {\n case (i, next) => {\n val r = RegNext(next, init)\n name.foreach { na => r.suggestName(s\"${na}_${i}\") }\n r\n }\n }\n}\n\n/** These wrap behavioral\n * shift registers into specific modules to allow for\n * backend flows to replace or constrain\n * them properly when used for CDC synchronization,\n * rather than buffering.\n * \n * The different types vary in their reset behavior:\n * AsyncResetShiftReg -- Asynchronously reset register array\n * A W(width) x D(depth) sized array is constructed from D instantiations of a\n * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,\n * but only used for timing applications\n */\n\nabstract class AbstractPipelineReg(w: Int = 1) extends Module {\n val io = IO(new Bundle {\n val d = Input(UInt(w.W))\n val q = Output(UInt(w.W))\n }\n )\n}\n\nobject AbstractPipelineReg {\n def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {\n val chain = Module(gen)\n name.foreach{ chain.suggestName(_) }\n chain.io.d := in.asUInt\n chain.io.q.asTypeOf(in)\n }\n}\n\nclass AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = \"pipe\") extends AbstractPipelineReg(w) {\n require(depth > 0, \"Depth must be greater than 0.\")\n\n override def desiredName = s\"AsyncResetShiftReg_w${w}_d${depth}_i${init}\"\n\n val chain = List.tabulate(depth) { i =>\n Module (new AsyncResetRegVec(w, init)).suggestName(s\"${name}_${i}\")\n }\n\n chain.last.io.d := io.d\n chain.last.io.en := true.B\n\n (chain.init zip chain.tail).foreach { case (sink, source) =>\n sink.io.d := source.io.q\n sink.io.en := true.B\n }\n io.q := chain.head.io.q\n}\n\nobject AsyncResetShiftReg {\n def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =\n AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)\n\n def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =\n apply(in, depth, 0, name)\n\n def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =\n apply(in, depth, init.litValue.toInt, name)\n\n def apply [T <: Data](in: T, depth: Int, init: T): T =\n apply (in, depth, init.litValue.toInt, None)\n}\nFile SynchronizerReg.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3._\nimport chisel3.util.{RegEnable, Cat}\n\n/** These wrap behavioral\n * shift and next registers into specific modules to allow for\n * backend flows to replace or constrain\n * them properly when used for CDC synchronization,\n * rather than buffering.\n * \n * \n * These are built up of *ResetSynchronizerPrimitiveShiftReg,\n * intended to be replaced by the integrator's metastable flops chains or replaced\n * at this level if they have a multi-bit wide synchronizer primitive.\n * The different types vary in their reset behavior:\n * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin\n * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep\n * 1-bit-wide shift registers.\n * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg\n * \n * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.\n * \n * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross\n * Clock Domains.\n*/\n\nobject SynchronizerResetType extends Enumeration {\n val NonSync, Inferred, Sync, Async = Value\n}\n\n\n// Note: this should not be used directly.\n// Use the companion object to generate this with the correct reset type mixin.\nprivate class SynchronizerPrimitiveShiftReg(\n sync: Int,\n init: Boolean,\n resetType: SynchronizerResetType.Value)\n extends AbstractPipelineReg(1) {\n\n val initInt = if (init) 1 else 0\n val initPostfix = resetType match {\n case SynchronizerResetType.NonSync => \"\"\n case _ => s\"_i${initInt}\"\n }\n override def desiredName = s\"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}\"\n\n val chain = List.tabulate(sync) { i =>\n val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)\n reg.suggestName(s\"sync_$i\")\n }\n chain.last := io.d.asBool\n\n (chain.init zip chain.tail).foreach { case (sink, source) =>\n sink := source\n }\n io.q := chain.head.asUInt\n}\n\nprivate object SynchronizerPrimitiveShiftReg {\n def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {\n val gen: () => SynchronizerPrimitiveShiftReg = resetType match {\n case SynchronizerResetType.NonSync =>\n () => new SynchronizerPrimitiveShiftReg(sync, init, resetType)\n case SynchronizerResetType.Async =>\n () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset\n case SynchronizerResetType.Sync =>\n () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset\n case SynchronizerResetType.Inferred =>\n () => new SynchronizerPrimitiveShiftReg(sync, init, resetType)\n }\n AbstractPipelineReg(gen(), in)\n }\n}\n\n// Note: This module may end up with a non-AsyncReset type reset.\n// But the Primitives within will always have AsyncReset type.\nclass AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)\n extends AbstractPipelineReg(w) {\n require(sync > 1, s\"Sync must be greater than 1, not ${sync}.\")\n override def desiredName = s\"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}\"\n val output = Seq.tabulate(w) { i =>\n val initBit = ((init >> i) & 1) > 0\n withReset(reset.asAsyncReset){\n SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)\n }\n }\n io.q := Cat(output.reverse)\n}\n\nobject AsyncResetSynchronizerShiftReg {\n def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =\n AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)\n\n def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =\n apply (in, sync, 0, name)\n\n def apply [T <: Data](in: T, sync: Int): T =\n apply (in, sync, 0, None)\n\n def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =\n apply(in, sync, init.litValue.toInt, name)\n\n def apply [T <: Data](in: T, sync: Int, init: T): T =\n apply (in, sync, init.litValue.toInt, None)\n}\n\n// Note: This module may end up with a non-Bool type reset.\n// But the Primitives within will always have Bool reset type.\n@deprecated(\"SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.\", \"rocket-chip 1.2\")\nclass SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {\n require(sync > 1, s\"Sync must be greater than 1, not ${sync}.\")\n override def desiredName = s\"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}\"\n val output = Seq.tabulate(w) { i =>\n val initBit = ((init >> i) & 1) > 0\n withReset(reset.asBool){\n SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)\n }\n }\n io.q := Cat(output.reverse)\n}\n\nobject SyncResetSynchronizerShiftReg {\n def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =\n if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)\n\n def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =\n apply (in, sync, 0, name)\n\n def apply [T <: Data](in: T, sync: Int): T =\n apply (in, sync, 0, None)\n\n def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =\n apply(in, sync, init.litValue.toInt, name)\n\n def apply [T <: Data](in: T, sync: Int, init: T): T =\n apply (in, sync, init.litValue.toInt, None)\n}\n\nclass ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {\n require(sync > 1, s\"Sync must be greater than 1, not ${sync}.\")\n override def desiredName = s\"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}\"\n val output = Seq.tabulate(w) { i =>\n val initBit = ((init >> i) & 1) > 0\n SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)\n }\n io.q := Cat(output.reverse)\n}\n\nobject ResetSynchronizerShiftReg {\n def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =\n AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)\n\n def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =\n apply (in, sync, 0, name)\n\n def apply [T <: Data](in: T, sync: Int): T =\n apply (in, sync, 0, None)\n\n def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =\n apply(in, sync, init.litValue.toInt, name)\n\n def apply [T <: Data](in: T, sync: Int, init: T): T =\n apply (in, sync, init.litValue.toInt, None)\n}\n\nclass SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {\n require(sync > 1, s\"Sync must be greater than 1, not ${sync}.\")\n override def desiredName = s\"SynchronizerShiftReg_w${w}_d${sync}\"\n val output = Seq.tabulate(w) { i =>\n SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)\n }\n io.q := Cat(output.reverse)\n}\n\nobject SynchronizerShiftReg {\n def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =\n if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)\n\n def apply [T <: Data](in: T, sync: Int): T =\n apply (in, sync, None)\n\n def apply [T <: Data](in: T): T =\n apply (in, 3, None)\n\n\n}\n\nclass ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {\n\n override def desiredName = s\"ClockCrossingReg_w${w}\"\n\n val io = IO(new Bundle{\n val d = Input(UInt(w.W))\n val q = Output(UInt(w.W))\n val en = Input(Bool())\n })\n\n val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)\n io.q := cdc_reg\n}\n\nobject ClockCrossingReg {\n def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {\n val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))\n name.foreach{ cdc_reg.suggestName(_) }\n cdc_reg.io.d := in.asUInt\n cdc_reg.io.en := en\n cdc_reg.io.q.asTypeOf(in)\n }\n}\n"},"response":{"kind":"string","value":"module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_160(\t// @[SynchronizerReg.scala:68:19]\n input clock,\t// @[SynchronizerReg.scala:68:19]\n input reset,\t// @[SynchronizerReg.scala:68:19]\n input io_d,\t// @[ShiftReg.scala:36:14]\n output io_q\t// @[ShiftReg.scala:36:14]\n);\n\n wire io_d_0 = io_d;\t// @[SynchronizerReg.scala:68:19]\n wire _sync_2_T = io_d_0;\t// @[SynchronizerReg.scala:54:22, :68:19]\n wire io_q_0;\t// @[SynchronizerReg.scala:68:19]\n reg sync_0;\t// @[SynchronizerReg.scala:51:87]\n assign io_q_0 = sync_0;\t// @[SynchronizerReg.scala:51:87, :68:19]\n reg sync_1;\t// @[SynchronizerReg.scala:51:87]\n reg sync_2;\t// @[SynchronizerReg.scala:51:87]\n always @(posedge clock or posedge reset) begin\t// @[SynchronizerReg.scala:68:19]\n if (reset) begin\t// @[SynchronizerReg.scala:68:19]\n sync_0 <= 1'h0;\t// @[SynchronizerReg.scala:51:87]\n sync_1 <= 1'h0;\t// @[SynchronizerReg.scala:51:87]\n sync_2 <= 1'h0;\t// @[SynchronizerReg.scala:51:87]\n end\n else begin\t// @[SynchronizerReg.scala:68:19]\n sync_0 <= sync_1;\t// @[SynchronizerReg.scala:51:87]\n sync_1 <= sync_2;\t// @[SynchronizerReg.scala:51:87]\n sync_2 <= _sync_2_T;\t// @[SynchronizerReg.scala:51:87, :54:22]\n end\n always @(posedge, posedge)"}}},{"rowIdx":580,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to the following Chisel files.\nFile Directory.scala:\n/*\n * Copyright 2019 SiFive, Inc.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You should have received a copy of LICENSE.Apache2 along with\n * this software. If not, you may obtain a copy at\n *\n * https://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\npackage sifive.blocks.inclusivecache\n\nimport chisel3._\nimport chisel3.util._\nimport org.chipsalliance.cde.config._\nimport freechips.rocketchip.diplomacy._\nimport freechips.rocketchip.tilelink._\nimport MetaData._\nimport chisel3.experimental.dataview._\nimport freechips.rocketchip.util.DescribedSRAM\n\nclass DirectoryEntry(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params)\n{\n val dirty = Bool() // true => TRUNK or TIP\n val state = UInt(params.stateBits.W)\n val clients = UInt(params.clientBits.W)\n val tag = UInt(params.tagBits.W)\n}\n\nclass DirectoryWrite(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params)\n{\n val set = UInt(params.setBits.W)\n val way = UInt(params.wayBits.W)\n val data = new DirectoryEntry(params)\n}\n\nclass DirectoryRead(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params)\n{\n val set = UInt(params.setBits.W)\n val tag = UInt(params.tagBits.W)\n}\n\nclass DirectoryResult(params: InclusiveCacheParameters) extends DirectoryEntry(params)\n{\n val hit = Bool()\n val way = UInt(params.wayBits.W)\n}\n\nclass Directory(params: InclusiveCacheParameters) extends Module\n{\n val io = IO(new Bundle {\n val write = Flipped(Decoupled(new DirectoryWrite(params)))\n val read = Flipped(Valid(new DirectoryRead(params))) // sees same-cycle write\n val result = Valid(new DirectoryResult(params))\n val ready = Bool() // reset complete; can enable access\n })\n\n val codeBits = new DirectoryEntry(params).getWidth\n\n val cc_dir = DescribedSRAM(\n name = \"cc_dir\",\n desc = \"Directory RAM\",\n size = params.cache.sets,\n data = Vec(params.cache.ways, UInt(codeBits.W))\n )\n\n val write = Queue(io.write, 1) // must inspect contents => max size 1\n // a flow Q creates a WaR hazard... this MIGHT not cause a problem\n // a pipe Q causes combinational loop through the scheduler\n\n // Wiping the Directory with 0s on reset has ultimate priority\n val wipeCount = RegInit(0.U((params.setBits + 1).W))\n val wipeOff = RegNext(false.B, true.B) // don't wipe tags during reset\n val wipeDone = wipeCount(params.setBits)\n val wipeSet = wipeCount(params.setBits - 1,0)\n\n io.ready := wipeDone\n when (!wipeDone && !wipeOff) { wipeCount := wipeCount + 1.U }\n assert (wipeDone || !io.read.valid)\n\n // Be explicit for dumb 1-port inference\n val ren = io.read.valid\n val wen = (!wipeDone && !wipeOff) || write.valid\n assert (!io.read.valid || wipeDone)\n\n require (codeBits <= 256)\n\n write.ready := !io.read.valid\n when (!ren && wen) {\n cc_dir.write(\n Mux(wipeDone, write.bits.set, wipeSet),\n VecInit.fill(params.cache.ways) { Mux(wipeDone, write.bits.data.asUInt, 0.U) },\n UIntToOH(write.bits.way, params.cache.ways).asBools.map(_ || !wipeDone))\n }\n\n val ren1 = RegInit(false.B)\n val ren2 = if (params.micro.dirReg) RegInit(false.B) else ren1\n ren2 := ren1\n ren1 := ren\n\n val bypass_valid = params.dirReg(write.valid)\n val bypass = params.dirReg(write.bits, ren1 && write.valid)\n val regout = params.dirReg(cc_dir.read(io.read.bits.set, ren), ren1)\n val tag = params.dirReg(RegEnable(io.read.bits.tag, ren), ren1)\n val set = params.dirReg(RegEnable(io.read.bits.set, ren), ren1)\n\n // Compute the victim way in case of an evicition\n val victimLFSR = random.LFSR(width = 16, params.dirReg(ren))(InclusiveCacheParameters.lfsrBits-1, 0)\n val victimSums = Seq.tabulate(params.cache.ways) { i => ((1 << InclusiveCacheParameters.lfsrBits)*i / params.cache.ways).U }\n val victimLTE = Cat(victimSums.map { _ <= victimLFSR }.reverse)\n val victimSimp = Cat(0.U(1.W), victimLTE(params.cache.ways-1, 1), 1.U(1.W))\n val victimWayOH = victimSimp(params.cache.ways-1,0) & ~(victimSimp >> 1)\n val victimWay = OHToUInt(victimWayOH)\n assert (!ren2 || victimLTE(0) === 1.U)\n assert (!ren2 || ((victimSimp >> 1) & ~victimSimp) === 0.U) // monotone\n assert (!ren2 || PopCount(victimWayOH) === 1.U)\n\n val setQuash = bypass_valid && bypass.set === set\n val tagMatch = bypass.data.tag === tag\n val wayMatch = bypass.way === victimWay\n\n val ways = regout.map(d => d.asTypeOf(new DirectoryEntry(params)))\n val hits = Cat(ways.zipWithIndex.map { case (w, i) =>\n w.tag === tag && w.state =/= INVALID && (!setQuash || i.U =/= bypass.way)\n }.reverse)\n val hit = hits.orR\n\n io.result.valid := ren2\n io.result.bits.viewAsSupertype(chiselTypeOf(bypass.data)) := Mux(hit, Mux1H(hits, ways), Mux(setQuash && (tagMatch || wayMatch), bypass.data, Mux1H(victimWayOH, ways)))\n io.result.bits.hit := hit || (setQuash && tagMatch && bypass.data.state =/= INVALID)\n io.result.bits.way := Mux(hit, OHToUInt(hits), Mux(setQuash && tagMatch, bypass.way, victimWay))\n\n params.ccover(ren2 && setQuash && tagMatch, \"DIRECTORY_HIT_BYPASS\", \"Bypassing write to a directory hit\")\n params.ccover(ren2 && setQuash && !tagMatch && wayMatch, \"DIRECTORY_EVICT_BYPASS\", \"Bypassing a write to a directory eviction\")\n\n def json: String = s\"\"\"{\"clients\":${params.clientBits},\"mem\":\"${cc_dir.pathName}\",\"clean\":\"${wipeDone.pathName}\"}\"\"\"\n}\nFile DescribedSRAM.scala:\n// See LICENSE.Berkeley for license details.\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3.{Data, SyncReadMem, Vec}\nimport chisel3.util.log2Ceil\n\nobject DescribedSRAM {\n def apply[T <: Data](\n name: String,\n desc: String,\n size: BigInt, // depth\n data: T\n ): SyncReadMem[T] = {\n\n val mem = SyncReadMem(size, data)\n\n mem.suggestName(name)\n\n val granWidth = data match {\n case v: Vec[_] => v.head.getWidth\n case d => d.getWidth\n }\n\n val uid = 0\n\n Annotated.srams(\n component = mem,\n name = name,\n address_width = log2Ceil(size),\n data_width = data.getWidth,\n depth = size,\n description = desc,\n write_mask_granularity = granWidth\n )\n\n mem\n }\n}\n"},"response":{"kind":"string","value":"module Directory(\t// @[Directory.scala:56:7]\n input clock,\t// @[Directory.scala:56:7]\n input reset,\t// @[Directory.scala:56:7]\n output io_write_ready,\t// @[Directory.scala:58:14]\n input io_write_valid,\t// @[Directory.scala:58:14]\n input [9:0] io_write_bits_set,\t// @[Directory.scala:58:14]\n input [2:0] io_write_bits_way,\t// @[Directory.scala:58:14]\n input io_write_bits_data_dirty,\t// @[Directory.scala:58:14]\n input [1:0] io_write_bits_data_state,\t// @[Directory.scala:58:14]\n input [7:0] io_write_bits_data_clients,\t// @[Directory.scala:58:14]\n input [10:0] io_write_bits_data_tag,\t// @[Directory.scala:58:14]\n input io_read_valid,\t// @[Directory.scala:58:14]\n input [9:0] io_read_bits_set,\t// @[Directory.scala:58:14]\n input [10:0] io_read_bits_tag,\t// @[Directory.scala:58:14]\n output io_result_bits_dirty,\t// @[Directory.scala:58:14]\n output [1:0] io_result_bits_state,\t// @[Directory.scala:58:14]\n output [7:0] io_result_bits_clients,\t// @[Directory.scala:58:14]\n output [10:0] io_result_bits_tag,\t// @[Directory.scala:58:14]\n output io_result_bits_hit,\t// @[Directory.scala:58:14]\n output [2:0] io_result_bits_way,\t// @[Directory.scala:58:14]\n output io_ready\t// @[Directory.scala:58:14]\n);\n\n wire cc_dir_MPORT_mask_7;\t// @[Directory.scala:100:65]\n wire cc_dir_MPORT_mask_6;\t// @[Directory.scala:100:65]\n wire cc_dir_MPORT_mask_5;\t// @[Directory.scala:100:65]\n wire cc_dir_MPORT_mask_4;\t// @[Directory.scala:100:65]\n wire cc_dir_MPORT_mask_3;\t// @[Directory.scala:100:65]\n wire cc_dir_MPORT_mask_2;\t// @[Directory.scala:100:65]\n wire cc_dir_MPORT_mask_1;\t// @[Directory.scala:100:65]\n wire cc_dir_MPORT_mask_0;\t// @[Directory.scala:100:65]\n wire [21:0] cc_dir_MPORT_data_7;\t// @[Directory.scala:99:44]\n wire [9:0] cc_dir_MPORT_addr;\t// @[Directory.scala:98:10]\n wire cc_dir_MPORT_en;\t// @[Directory.scala:96:14]\n wire _victimLFSR_prng_io_out_0;\t// @[PRNG.scala:91:22]\n wire _victimLFSR_prng_io_out_1;\t// @[PRNG.scala:91:22]\n wire _victimLFSR_prng_io_out_2;\t// @[PRNG.scala:91:22]\n wire _victimLFSR_prng_io_out_3;\t// @[PRNG.scala:91:22]\n wire _victimLFSR_prng_io_out_4;\t// @[PRNG.scala:91:22]\n wire _victimLFSR_prng_io_out_5;\t// @[PRNG.scala:91:22]\n wire _victimLFSR_prng_io_out_6;\t// @[PRNG.scala:91:22]\n wire _victimLFSR_prng_io_out_7;\t// @[PRNG.scala:91:22]\n wire _victimLFSR_prng_io_out_8;\t// @[PRNG.scala:91:22]\n wire _victimLFSR_prng_io_out_9;\t// @[PRNG.scala:91:22]\n wire _write_q_io_deq_valid;\t// @[Decoupled.scala:362:21]\n wire [9:0] _write_q_io_deq_bits_set;\t// @[Decoupled.scala:362:21]\n wire [2:0] _write_q_io_deq_bits_way;\t// @[Decoupled.scala:362:21]\n wire _write_q_io_deq_bits_data_dirty;\t// @[Decoupled.scala:362:21]\n wire [1:0] _write_q_io_deq_bits_data_state;\t// @[Decoupled.scala:362:21]\n wire [7:0] _write_q_io_deq_bits_data_clients;\t// @[Decoupled.scala:362:21]\n wire [10:0] _write_q_io_deq_bits_data_tag;\t// @[Decoupled.scala:362:21]\n wire [175:0] _cc_dir_RW0_rdata;\t// @[DescribedSRAM.scala:17:26]\n reg [10:0] wipeCount;\t// @[Directory.scala:79:26]\n reg wipeOff;\t// @[Directory.scala:80:24]\n assign cc_dir_MPORT_en = ~io_read_valid & (~(wipeCount[10]) & ~wipeOff | _write_q_io_deq_valid);\t// @[Decoupled.scala:362:21]\n assign cc_dir_MPORT_addr = wipeCount[10] ? _write_q_io_deq_bits_set : wipeCount[9:0];\t// @[Decoupled.scala:362:21]\n assign cc_dir_MPORT_data_7 = wipeCount[10] ? {_write_q_io_deq_bits_data_dirty, _write_q_io_deq_bits_data_state, _write_q_io_deq_bits_data_clients, _write_q_io_deq_bits_data_tag} : 22'h0;\t// @[Decoupled.scala:362:21]\n assign cc_dir_MPORT_mask_0 = _write_q_io_deq_bits_way == 3'h0 | ~(wipeCount[10]);\t// @[Decoupled.scala:362:21]\n assign cc_dir_MPORT_mask_1 = _write_q_io_deq_bits_way == 3'h1 | ~(wipeCount[10]);\t// @[Decoupled.scala:362:21]\n assign cc_dir_MPORT_mask_2 = _write_q_io_deq_bits_way == 3'h2 | ~(wipeCount[10]);\t// @[Decoupled.scala:362:21]\n assign cc_dir_MPORT_mask_3 = _write_q_io_deq_bits_way == 3'h3 | ~(wipeCount[10]);\t// @[Decoupled.scala:362:21]\n assign cc_dir_MPORT_mask_4 = _write_q_io_deq_bits_way == 3'h4 | ~(wipeCount[10]);\t// @[Decoupled.scala:362:21]\n assign cc_dir_MPORT_mask_5 = _write_q_io_deq_bits_way == 3'h5 | ~(wipeCount[10]);\t// @[Decoupled.scala:362:21]\n assign cc_dir_MPORT_mask_6 = _write_q_io_deq_bits_way == 3'h6 | ~(wipeCount[10]);\t// @[Decoupled.scala:362:21]\n assign cc_dir_MPORT_mask_7 = (&_write_q_io_deq_bits_way) | ~(wipeCount[10]);\t// @[Decoupled.scala:362:21]\n reg ren1;\t// @[Directory.scala:103:21]\n reg [10:0] tag;\t// @[Directory.scala:111:36]\n reg [9:0] set;\t// @[Directory.scala:112:36]\n wire [9:0] victimLFSR = {_victimLFSR_prng_io_out_9, _victimLFSR_prng_io_out_8, _victimLFSR_prng_io_out_7, _victimLFSR_prng_io_out_6, _victimLFSR_prng_io_out_5, _victimLFSR_prng_io_out_4, _victimLFSR_prng_io_out_3, _victimLFSR_prng_io_out_2, _victimLFSR_prng_io_out_1, _victimLFSR_prng_io_out_0};\t// @[PRNG.scala:91:22]\n wire [2:0] _GEN = {_victimLFSR_prng_io_out_9, _victimLFSR_prng_io_out_8, _victimLFSR_prng_io_out_7};\t// @[PRNG.scala:91:22]\n wire [1:0] _GEN_0 = {_victimLFSR_prng_io_out_9, _victimLFSR_prng_io_out_8};\t// @[PRNG.scala:91:22]\n wire _victimLTE_T_3 = victimLFSR > 10'h17F;\t// @[Directory.scala:115:63, :117:43]\n wire _victimLTE_T_5 = victimLFSR > 10'h27F;\t// @[Directory.scala:115:63, :117:43]\n wire _victimLTE_T_6 = victimLFSR > 10'h2FF;\t// @[Directory.scala:115:63, :117:43]\n wire _victimLTE_T_7 = victimLFSR > 10'h37F;\t// @[Directory.scala:115:63, :117:43]\n wire [3:0] victimWay_hi = {_victimLTE_T_7, _victimLTE_T_6, _victimLTE_T_5, _victimLFSR_prng_io_out_9} & {1'h1, ~_victimLTE_T_7, ~_victimLTE_T_6, ~_victimLTE_T_5};\t// @[PRNG.scala:91:22]\n wire [2:0] _victimWay_T_1 = victimWay_hi[3:1] | {_victimLTE_T_3, |_GEN_0, |_GEN} & {~_victimLFSR_prng_io_out_9, ~_victimLTE_T_3, ~(|_GEN_0)};\t// @[PRNG.scala:91:22]\n wire [2:0] victimWay = {|victimWay_hi, |(_victimWay_T_1[2:1]), _victimWay_T_1[2] | _victimWay_T_1[0]};\t// @[OneHot.scala:30:18, :31:18, :32:{10,14,28}]\n wire _view__T_71 = (|_GEN) & ~(|_GEN_0);\t// @[Directory.scala:117:43, :119:{55,57}, :123:28]\n wire _view__T_72 = (|_GEN_0) & ~_victimLTE_T_3;\t// @[Directory.scala:117:43, :119:{55,57}, :123:28]\n wire _view__T_73 = _victimLTE_T_3 & ~_victimLFSR_prng_io_out_9;\t// @[PRNG.scala:91:22]\n wire _view__T_74 = _victimLFSR_prng_io_out_9 & ~_victimLTE_T_5;\t// @[PRNG.scala:91:22]\n wire _view__T_75 = _victimLTE_T_5 & ~_victimLTE_T_6;\t// @[Directory.scala:117:43, :119:{55,57}, :123:28]\n wire _view__T_76 = _victimLTE_T_6 & ~_victimLTE_T_7;\t// @[Directory.scala:117:43, :119:{55,57}, :123:28]"}}},{"rowIdx":581,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to the following Chisel files.\nFile Monitor.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.tilelink\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.experimental.SourceLine\n\nimport org.chipsalliance.cde.config._\nimport org.chipsalliance.diplomacy._\n\nimport freechips.rocketchip.diplomacy.EnableMonitors\nimport freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}\nimport freechips.rocketchip.util.PlusArg\n\ncase class TLMonitorArgs(edge: TLEdge)\n\nabstract class TLMonitorBase(args: TLMonitorArgs) extends Module\n{\n val io = IO(new Bundle {\n val in = Input(new TLBundle(args.edge.bundle))\n })\n\n def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit\n legalize(io.in, args.edge, reset)\n}\n\nobject TLMonitor {\n def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {\n if (enable) {\n EnableMonitors { implicit p => node := TLEphemeralNode()(ValName(\"monitor\")) }\n } else { node }\n }\n}\n\nclass TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)\n{\n require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))\n\n val cover_prop_class = PropertyClass.Default\n\n //Like assert but can flip to being an assumption for formal verification\n def monAssert(cond: Bool, message: String): Unit =\n if (monitorDir == MonitorDirection.Monitor) {\n assert(cond, message)\n } else {\n Property(monitorDir, cond, message, PropertyClass.Default)\n }\n\n def assume(cond: Bool, message: String): Unit =\n if (monitorDir == MonitorDirection.Monitor) {\n assert(cond, message)\n } else {\n Property(monitorDir.flip, cond, message, PropertyClass.Default)\n }\n\n def extra = {\n args.edge.sourceInfo match {\n case SourceLine(filename, line, col) => s\" (connected at $filename:$line:$col)\"\n case _ => \"\"\n }\n }\n\n def visible(address: UInt, source: UInt, edge: TLEdge) =\n edge.client.clients.map { c =>\n !c.sourceId.contains(source) ||\n c.visibility.map(_.contains(address)).reduce(_ || _)\n }.reduce(_ && _)\n\n def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {\n //switch this flag to turn on diplomacy in error messages\n def diplomacyInfo = if (true) \"\" else \"\\nThe diplomacy information for the edge is as follows:\\n\" + edge.formatEdge + \"\\n\"\n monAssert (TLMessages.isA(bundle.opcode), \"'A' channel has invalid opcode\" + extra)\n\n // Reuse these subexpressions to save some firrtl lines\n val source_ok = edge.client.contains(bundle.source)\n val is_aligned = edge.isAligned(bundle.address, bundle.size)\n val mask = edge.full_mask(bundle)\n\n monAssert (visible(edge.address(bundle), bundle.source, edge), \"'A' channel carries an address illegal for the specified bank visibility\")\n\n //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B\n //TODO: check for acquireT?\n when (bundle.opcode === TLMessages.AcquireBlock) {\n monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters\" + diplomacyInfo + extra)\n monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock from a client which does not support Probe\" + diplomacyInfo + extra)\n monAssert (source_ok, \"'A' channel AcquireBlock carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'A' channel AcquireBlock smaller than a beat\" + extra)\n monAssert (is_aligned, \"'A' channel AcquireBlock address not aligned to size\" + extra)\n monAssert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquireBlock carries invalid grow param\" + extra)\n monAssert (~bundle.mask === 0.U, \"'A' channel AcquireBlock contains invalid mask\" + extra)\n monAssert (!bundle.corrupt, \"'A' channel AcquireBlock is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.AcquirePerm) {\n monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters\" + diplomacyInfo + extra)\n monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm from a client which does not support Probe\" + diplomacyInfo + extra)\n monAssert (source_ok, \"'A' channel AcquirePerm carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'A' channel AcquirePerm smaller than a beat\" + extra)\n monAssert (is_aligned, \"'A' channel AcquirePerm address not aligned to size\" + extra)\n monAssert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquirePerm carries invalid grow param\" + extra)\n monAssert (bundle.param =/= TLPermissions.NtoB, \"'A' channel AcquirePerm requests NtoB\" + extra)\n monAssert (~bundle.mask === 0.U, \"'A' channel AcquirePerm contains invalid mask\" + extra)\n monAssert (!bundle.corrupt, \"'A' channel AcquirePerm is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.Get) {\n monAssert (edge.master.emitsGet(bundle.source, bundle.size), \"'A' channel carries Get type which master claims it can't emit\" + diplomacyInfo + extra)\n monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), \"'A' channel carries Get type which slave claims it can't support\" + diplomacyInfo + extra)\n monAssert (source_ok, \"'A' channel Get carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'A' channel Get carries invalid param\" + extra)\n monAssert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n monAssert (!bundle.corrupt, \"'A' channel Get is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.PutFullData) {\n monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type which is unexpected using diplomatic parameters\" + diplomacyInfo + extra)\n monAssert (source_ok, \"'A' channel PutFull carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'A' channel PutFull carries invalid param\" + extra)\n monAssert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.PutPartialData) {\n monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type which is unexpected using diplomatic parameters\" + extra)\n monAssert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'A' channel PutPartial carries invalid param\" + extra)\n monAssert ((bundle.mask & ~mask) === 0.U, \"'A' channel PutPartial contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.ArithmeticData) {\n monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type which is unexpected using diplomatic parameters\" + extra)\n monAssert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n monAssert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n monAssert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.LogicalData) {\n monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type which is unexpected using diplomatic parameters\" + extra)\n monAssert (source_ok, \"'A' channel Logical carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n monAssert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n monAssert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.Hint) {\n monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type which is unexpected using diplomatic parameters\" + extra)\n monAssert (source_ok, \"'A' channel Hint carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n monAssert (TLHints.isHints(bundle.param), \"'A' channel Hint carries invalid opcode param\" + extra)\n monAssert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n monAssert (!bundle.corrupt, \"'A' channel Hint is corrupt\" + extra)\n }\n }\n\n def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {\n monAssert (TLMessages.isB(bundle.opcode), \"'B' channel has invalid opcode\" + extra)\n\n monAssert (visible(edge.address(bundle), bundle.source, edge), \"'B' channel carries an address illegal for the specified bank visibility\")\n\n // Reuse these subexpressions to save some firrtl lines\n val address_ok = edge.manager.containsSafe(edge.address(bundle))\n val is_aligned = edge.isAligned(bundle.address, bundle.size)\n val mask = edge.full_mask(bundle)\n val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source\n\n when (bundle.opcode === TLMessages.Probe) {\n assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), \"'B' channel carries Probe type which is unexpected using diplomatic parameters\" + extra)\n assume (address_ok, \"'B' channel Probe carries unmanaged address\" + extra)\n assume (legal_source, \"'B' channel Probe carries source that is not first source\" + extra)\n assume (is_aligned, \"'B' channel Probe address not aligned to size\" + extra)\n assume (TLPermissions.isCap(bundle.param), \"'B' channel Probe carries invalid cap param\" + extra)\n assume (bundle.mask === mask, \"'B' channel Probe contains invalid mask\" + extra)\n assume (!bundle.corrupt, \"'B' channel Probe is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.Get) {\n monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), \"'B' channel carries Get type which is unexpected using diplomatic parameters\" + extra)\n monAssert (address_ok, \"'B' channel Get carries unmanaged address\" + extra)\n monAssert (legal_source, \"'B' channel Get carries source that is not first source\" + extra)\n monAssert (is_aligned, \"'B' channel Get address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'B' channel Get carries invalid param\" + extra)\n monAssert (bundle.mask === mask, \"'B' channel Get contains invalid mask\" + extra)\n monAssert (!bundle.corrupt, \"'B' channel Get is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.PutFullData) {\n monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), \"'B' channel carries PutFull type which is unexpected using diplomatic parameters\" + extra)\n monAssert (address_ok, \"'B' channel PutFull carries unmanaged address\" + extra)\n monAssert (legal_source, \"'B' channel PutFull carries source that is not first source\" + extra)\n monAssert (is_aligned, \"'B' channel PutFull address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'B' channel PutFull carries invalid param\" + extra)\n monAssert (bundle.mask === mask, \"'B' channel PutFull contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.PutPartialData) {\n monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), \"'B' channel carries PutPartial type which is unexpected using diplomatic parameters\" + extra)\n monAssert (address_ok, \"'B' channel PutPartial carries unmanaged address\" + extra)\n monAssert (legal_source, \"'B' channel PutPartial carries source that is not first source\" + extra)\n monAssert (is_aligned, \"'B' channel PutPartial address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'B' channel PutPartial carries invalid param\" + extra)\n monAssert ((bundle.mask & ~mask) === 0.U, \"'B' channel PutPartial contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.ArithmeticData) {\n monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), \"'B' channel carries Arithmetic type unsupported by master\" + extra)\n monAssert (address_ok, \"'B' channel Arithmetic carries unmanaged address\" + extra)\n monAssert (legal_source, \"'B' channel Arithmetic carries source that is not first source\" + extra)\n monAssert (is_aligned, \"'B' channel Arithmetic address not aligned to size\" + extra)\n monAssert (TLAtomics.isArithmetic(bundle.param), \"'B' channel Arithmetic carries invalid opcode param\" + extra)\n monAssert (bundle.mask === mask, \"'B' channel Arithmetic contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.LogicalData) {\n monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), \"'B' channel carries Logical type unsupported by client\" + extra)\n monAssert (address_ok, \"'B' channel Logical carries unmanaged address\" + extra)\n monAssert (legal_source, \"'B' channel Logical carries source that is not first source\" + extra)\n monAssert (is_aligned, \"'B' channel Logical address not aligned to size\" + extra)\n monAssert (TLAtomics.isLogical(bundle.param), \"'B' channel Logical carries invalid opcode param\" + extra)\n monAssert (bundle.mask === mask, \"'B' channel Logical contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.Hint) {\n monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), \"'B' channel carries Hint type unsupported by client\" + extra)\n monAssert (address_ok, \"'B' channel Hint carries unmanaged address\" + extra)\n monAssert (legal_source, \"'B' channel Hint carries source that is not first source\" + extra)\n monAssert (is_aligned, \"'B' channel Hint address not aligned to size\" + extra)\n monAssert (bundle.mask === mask, \"'B' channel Hint contains invalid mask\" + extra)\n monAssert (!bundle.corrupt, \"'B' channel Hint is corrupt\" + extra)\n }\n }\n\n def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {\n monAssert (TLMessages.isC(bundle.opcode), \"'C' channel has invalid opcode\" + extra)\n\n val source_ok = edge.client.contains(bundle.source)\n val is_aligned = edge.isAligned(bundle.address, bundle.size)\n val address_ok = edge.manager.containsSafe(edge.address(bundle))\n\n monAssert (visible(edge.address(bundle), bundle.source, edge), \"'C' channel carries an address illegal for the specified bank visibility\")\n\n when (bundle.opcode === TLMessages.ProbeAck) {\n monAssert (address_ok, \"'C' channel ProbeAck carries unmanaged address\" + extra)\n monAssert (source_ok, \"'C' channel ProbeAck carries invalid source ID\" + extra)\n monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'C' channel ProbeAck smaller than a beat\" + extra)\n monAssert (is_aligned, \"'C' channel ProbeAck address not aligned to size\" + extra)\n monAssert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAck carries invalid report param\" + extra)\n monAssert (!bundle.corrupt, \"'C' channel ProbeAck is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.ProbeAckData) {\n monAssert (address_ok, \"'C' channel ProbeAckData carries unmanaged address\" + extra)\n monAssert (source_ok, \"'C' channel ProbeAckData carries invalid source ID\" + extra)\n monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'C' channel ProbeAckData smaller than a beat\" + extra)\n monAssert (is_aligned, \"'C' channel ProbeAckData address not aligned to size\" + extra)\n monAssert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAckData carries invalid report param\" + extra)\n }\n\n when (bundle.opcode === TLMessages.Release) {\n monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries Release type unsupported by manager\" + extra)\n monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), \"'C' channel carries Release from a client which does not support Probe\" + extra)\n monAssert (source_ok, \"'C' channel Release carries invalid source ID\" + extra)\n monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'C' channel Release smaller than a beat\" + extra)\n monAssert (is_aligned, \"'C' channel Release address not aligned to size\" + extra)\n monAssert (TLPermissions.isReport(bundle.param), \"'C' channel Release carries invalid report param\" + extra)\n monAssert (!bundle.corrupt, \"'C' channel Release is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.ReleaseData) {\n monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries ReleaseData type unsupported by manager\" + extra)\n monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), \"'C' channel carries Release from a client which does not support Probe\" + extra)\n monAssert (source_ok, \"'C' channel ReleaseData carries invalid source ID\" + extra)\n monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'C' channel ReleaseData smaller than a beat\" + extra)\n monAssert (is_aligned, \"'C' channel ReleaseData address not aligned to size\" + extra)\n monAssert (TLPermissions.isReport(bundle.param), \"'C' channel ReleaseData carries invalid report param\" + extra)\n }\n\n when (bundle.opcode === TLMessages.AccessAck) {\n monAssert (address_ok, \"'C' channel AccessAck carries unmanaged address\" + extra)\n monAssert (source_ok, \"'C' channel AccessAck carries invalid source ID\" + extra)\n monAssert (is_aligned, \"'C' channel AccessAck address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'C' channel AccessAck carries invalid param\" + extra)\n monAssert (!bundle.corrupt, \"'C' channel AccessAck is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.AccessAckData) {\n monAssert (address_ok, \"'C' channel AccessAckData carries unmanaged address\" + extra)\n monAssert (source_ok, \"'C' channel AccessAckData carries invalid source ID\" + extra)\n monAssert (is_aligned, \"'C' channel AccessAckData address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'C' channel AccessAckData carries invalid param\" + extra)\n }\n\n when (bundle.opcode === TLMessages.HintAck) {\n monAssert (address_ok, \"'C' channel HintAck carries unmanaged address\" + extra)\n monAssert (source_ok, \"'C' channel HintAck carries invalid source ID\" + extra)\n monAssert (is_aligned, \"'C' channel HintAck address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'C' channel HintAck carries invalid param\" + extra)\n monAssert (!bundle.corrupt, \"'C' channel HintAck is corrupt\" + extra)\n }\n }\n\n def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {\n assume (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n\n val source_ok = edge.client.contains(bundle.source)\n val sink_ok = bundle.sink < edge.manager.endSinkId.U\n val deny_put_ok = edge.manager.mayDenyPut.B\n val deny_get_ok = edge.manager.mayDenyGet.B\n\n when (bundle.opcode === TLMessages.ReleaseAck) {\n assume (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'D' channel ReleaseAck smaller than a beat\" + extra)\n assume (bundle.param === 0.U, \"'D' channel ReleaseeAck carries invalid param\" + extra)\n assume (!bundle.corrupt, \"'D' channel ReleaseAck is corrupt\" + extra)\n assume (!bundle.denied, \"'D' channel ReleaseAck is denied\" + extra)\n }\n\n when (bundle.opcode === TLMessages.Grant) {\n assume (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n assume (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'D' channel Grant smaller than a beat\" + extra)\n assume (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n assume (bundle.param =/= TLPermissions.toN, \"'D' channel Grant carries toN param\" + extra)\n assume (!bundle.corrupt, \"'D' channel Grant is corrupt\" + extra)\n assume (deny_put_ok || !bundle.denied, \"'D' channel Grant is denied\" + extra)\n }\n\n when (bundle.opcode === TLMessages.GrantData) {\n assume (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n assume (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'D' channel GrantData smaller than a beat\" + extra)\n assume (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n assume (bundle.param =/= TLPermissions.toN, \"'D' channel GrantData carries toN param\" + extra)\n assume (!bundle.denied || bundle.corrupt, \"'D' channel GrantData is denied but not corrupt\" + extra)\n assume (deny_get_ok || !bundle.denied, \"'D' channel GrantData is denied\" + extra)\n }\n\n when (bundle.opcode === TLMessages.AccessAck) {\n assume (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n // size is ignored\n assume (bundle.param === 0.U, \"'D' channel AccessAck carries invalid param\" + extra)\n assume (!bundle.corrupt, \"'D' channel AccessAck is corrupt\" + extra)\n assume (deny_put_ok || !bundle.denied, \"'D' channel AccessAck is denied\" + extra)\n }\n\n when (bundle.opcode === TLMessages.AccessAckData) {\n assume (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n // size is ignored\n assume (bundle.param === 0.U, \"'D' channel AccessAckData carries invalid param\" + extra)\n assume (!bundle.denied || bundle.corrupt, \"'D' channel AccessAckData is denied but not corrupt\" + extra)\n assume (deny_get_ok || !bundle.denied, \"'D' channel AccessAckData is denied\" + extra)\n }\n\n when (bundle.opcode === TLMessages.HintAck) {\n assume (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n // size is ignored\n assume (bundle.param === 0.U, \"'D' channel HintAck carries invalid param\" + extra)\n assume (!bundle.corrupt, \"'D' channel HintAck is corrupt\" + extra)\n assume (deny_put_ok || !bundle.denied, \"'D' channel HintAck is denied\" + extra)\n }\n }\n\n def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {\n val sink_ok = bundle.sink < edge.manager.endSinkId.U\n monAssert (sink_ok, \"'E' channels carries invalid sink ID\" + extra)\n }\n\n def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {\n when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }\n when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }\n if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {\n when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }\n when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }\n when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }\n } else {\n monAssert (!bundle.b.valid, \"'B' channel valid and not TL-C\" + extra)\n monAssert (!bundle.c.valid, \"'C' channel valid and not TL-C\" + extra)\n monAssert (!bundle.e.valid, \"'E' channel valid and not TL-C\" + extra)\n }\n }\n\n def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {\n val a_first = edge.first(a.bits, a.fire)\n val opcode = Reg(UInt())\n val param = Reg(UInt())\n val size = Reg(UInt())\n val source = Reg(UInt())\n val address = Reg(UInt())\n when (a.valid && !a_first) {\n monAssert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n monAssert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n monAssert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n monAssert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n monAssert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n }\n when (a.fire && a_first) {\n opcode := a.bits.opcode\n param := a.bits.param\n size := a.bits.size\n source := a.bits.source\n address := a.bits.address\n }\n }\n\n def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {\n val b_first = edge.first(b.bits, b.fire)\n val opcode = Reg(UInt())\n val param = Reg(UInt())\n val size = Reg(UInt())\n val source = Reg(UInt())\n val address = Reg(UInt())\n when (b.valid && !b_first) {\n monAssert (b.bits.opcode === opcode, \"'B' channel opcode changed within multibeat operation\" + extra)\n monAssert (b.bits.param === param, \"'B' channel param changed within multibeat operation\" + extra)\n monAssert (b.bits.size === size, \"'B' channel size changed within multibeat operation\" + extra)\n monAssert (b.bits.source === source, \"'B' channel source changed within multibeat operation\" + extra)\n monAssert (b.bits.address=== address,\"'B' channel addresss changed with multibeat operation\" + extra)\n }\n when (b.fire && b_first) {\n opcode := b.bits.opcode\n param := b.bits.param\n size := b.bits.size\n source := b.bits.source\n address := b.bits.address\n }\n }\n\n def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {\n // Symbolic variable\n val sym_source = Wire(UInt(edge.client.endSourceId.W))\n // TODO: Connect sym_source to a fixed value for simulation and to a\n // free wire in formal\n sym_source := 0.U\n\n // Type casting Int to UInt\n val maxSourceId = Wire(UInt(edge.client.endSourceId.W))\n maxSourceId := edge.client.endSourceId.U\n\n // Delayed verison of sym_source\n val sym_source_d = Reg(UInt(edge.client.endSourceId.W))\n sym_source_d := sym_source\n\n // These will be constraints for FV setup\n Property(\n MonitorDirection.Monitor,\n (sym_source === sym_source_d),\n \"sym_source should remain stable\",\n PropertyClass.Default)\n Property(\n MonitorDirection.Monitor,\n (sym_source <= maxSourceId),\n \"sym_source should take legal value\",\n PropertyClass.Default)\n\n val my_resp_pend = RegInit(false.B)\n val my_opcode = Reg(UInt())\n val my_size = Reg(UInt())\n\n val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)\n val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)\n\n val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)\n val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)\n\n val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)\n val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)\n when (my_set_resp_pend) {\n my_resp_pend := true.B\n } .elsewhen (my_clr_resp_pend) {\n my_resp_pend := false.B\n }\n\n when (my_a_first_beat) {\n my_opcode := bundle.a.bits.opcode\n my_size := bundle.a.bits.size\n }\n\n val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)\n val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)\n\n val my_resp_opcode_legal = Wire(Bool())\n when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||\n (my_resp_opcode === TLMessages.LogicalData)) {\n my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)\n } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {\n my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)\n } .otherwise {\n my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)\n }\n\n monAssert (IfThen(my_resp_pend, !my_a_first_beat),\n \"Request message should not be sent with a source ID, for which a response message\" +\n \"is already pending (not received until current cycle) for a prior request message\" +\n \"with the same source ID\" + extra)\n\n assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),\n \"Response message should be accepted with a source ID only if a request message with the\" +\n \"same source ID has been accepted or is being accepted in the current cycle\" + extra)\n assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),\n \"Response message should be sent with a source ID only if a request message with the\" +\n \"same source ID has been accepted or is being sent in the current cycle\" + extra)\n assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),\n \"If d_valid is 1, then d_size should be same as a_size of the corresponding request\" +\n \"message\" + extra)\n assume (IfThen(my_d_first_beat, my_resp_opcode_legal),\n \"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding\" +\n \"request message\" + extra)\n }\n\n def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {\n val c_first = edge.first(c.bits, c.fire)\n val opcode = Reg(UInt())\n val param = Reg(UInt())\n val size = Reg(UInt())\n val source = Reg(UInt())\n val address = Reg(UInt())\n when (c.valid && !c_first) {\n monAssert (c.bits.opcode === opcode, \"'C' channel opcode changed within multibeat operation\" + extra)\n monAssert (c.bits.param === param, \"'C' channel param changed within multibeat operation\" + extra)\n monAssert (c.bits.size === size, \"'C' channel size changed within multibeat operation\" + extra)\n monAssert (c.bits.source === source, \"'C' channel source changed within multibeat operation\" + extra)\n monAssert (c.bits.address=== address,\"'C' channel address changed with multibeat operation\" + extra)\n }\n when (c.fire && c_first) {\n opcode := c.bits.opcode\n param := c.bits.param\n size := c.bits.size\n source := c.bits.source\n address := c.bits.address\n }\n }\n\n def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {\n val d_first = edge.first(d.bits, d.fire)\n val opcode = Reg(UInt())\n val param = Reg(UInt())\n val size = Reg(UInt())\n val source = Reg(UInt())\n val sink = Reg(UInt())\n val denied = Reg(Bool())\n when (d.valid && !d_first) {\n assume (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n assume (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n assume (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n assume (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n assume (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n assume (d.bits.denied === denied, \"'D' channel denied changed with multibeat operation\" + extra)\n }\n when (d.fire && d_first) {\n opcode := d.bits.opcode\n param := d.bits.param\n size := d.bits.size\n source := d.bits.source\n sink := d.bits.sink\n denied := d.bits.denied\n }\n }\n\n def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {\n legalizeMultibeatA(bundle.a, edge)\n legalizeMultibeatD(bundle.d, edge)\n if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {\n legalizeMultibeatB(bundle.b, edge)\n legalizeMultibeatC(bundle.c, edge)\n }\n }\n\n //This is left in for almond which doesn't adhere to the tilelink protocol\n @deprecated(\"Use legalizeADSource instead if possible\",\"\")\n def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {\n val inflight = RegInit(0.U(edge.client.endSourceId.W))\n\n val a_first = edge.first(bundle.a.bits, bundle.a.fire)\n val d_first = edge.first(bundle.d.bits, bundle.d.fire)\n\n val a_set = WireInit(0.U(edge.client.endSourceId.W))\n when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {\n a_set := UIntToOH(bundle.a.bits.source)\n assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n }\n\n val d_clr = WireInit(0.U(edge.client.endSourceId.W))\n val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck\n when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {\n d_clr := UIntToOH(bundle.d.bits.source)\n assume((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n }\n\n if (edge.manager.minLatency > 0) {\n assume(a_set =/= d_clr || !a_set.orR, s\"'A' and 'D' concurrent, despite minlatency > 0\" + extra)\n }\n\n inflight := (inflight | a_set) & ~d_clr\n\n val watchdog = RegInit(0.U(32.W))\n val limit = PlusArg(\"tilelink_timeout\",\n docstring=\"Kill emulation after INT waiting TileLink cycles. Off if 0.\")\n assert (!inflight.orR || limit === 0.U || watchdog < limit, \"TileLink timeout expired\" + extra)\n\n watchdog := watchdog + 1.U\n when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }\n }\n\n def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {\n val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)\n val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything\n val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)\n val log_a_size_bus_size = log2Ceil(a_size_bus_size)\n def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits\n\n val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error\n inflight.suggestName(\"inflight\")\n val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))\n inflight_opcodes.suggestName(\"inflight_opcodes\")\n val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))\n inflight_sizes.suggestName(\"inflight_sizes\")\n\n val a_first = edge.first(bundle.a.bits, bundle.a.fire)\n a_first.suggestName(\"a_first\")\n val d_first = edge.first(bundle.d.bits, bundle.d.fire)\n d_first.suggestName(\"d_first\")\n\n val a_set = WireInit(0.U(edge.client.endSourceId.W))\n val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))\n a_set.suggestName(\"a_set\")\n a_set_wo_ready.suggestName(\"a_set_wo_ready\")\n val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))\n a_opcodes_set.suggestName(\"a_opcodes_set\")\n val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))\n a_sizes_set.suggestName(\"a_sizes_set\")\n\n val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))\n a_opcode_lookup.suggestName(\"a_opcode_lookup\")\n a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U\n\n val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))\n a_size_lookup.suggestName(\"a_size_lookup\")\n a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U\n\n val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))\n val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))\n\n val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))\n a_opcodes_set_interm.suggestName(\"a_opcodes_set_interm\")\n val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))\n a_sizes_set_interm.suggestName(\"a_sizes_set_interm\")\n\n when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {\n a_set_wo_ready := UIntToOH(bundle.a.bits.source)\n }\n\n when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {\n a_set := UIntToOH(bundle.a.bits.source)\n a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U\n a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U\n a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)\n a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)\n monAssert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n }\n\n val d_clr = WireInit(0.U(edge.client.endSourceId.W))\n val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))\n d_clr.suggestName(\"d_clr\")\n d_clr_wo_ready.suggestName(\"d_clr_wo_ready\")\n val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))\n d_opcodes_clr.suggestName(\"d_opcodes_clr\")\n val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))\n d_sizes_clr.suggestName(\"d_sizes_clr\")\n\n val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck\n when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {\n d_clr_wo_ready := UIntToOH(bundle.d.bits.source)\n }\n\n when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {\n d_clr := UIntToOH(bundle.d.bits.source)\n d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)\n d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)\n }\n when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {\n val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)\n assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, \"'D' channel acknowledged for nothing inflight\" + extra)\n\n when (same_cycle_resp) {\n assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||\n (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), \"'D' channel contains improper opcode response\" + extra)\n assume((bundle.a.bits.size === bundle.d.bits.size), \"'D' channel contains improper response size\" + extra)\n } .otherwise {\n assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||\n (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), \"'D' channel contains improper opcode response\" + extra)\n assume((bundle.d.bits.size === a_size_lookup), \"'D' channel contains improper response size\" + extra)\n }\n }\n when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {\n assume((!bundle.d.ready) || bundle.a.ready, \"ready check\")\n }\n\n if (edge.manager.minLatency > 0) {\n assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s\"'A' and 'D' concurrent, despite minlatency > 0\" + extra)\n }\n\n inflight := (inflight | a_set) & ~d_clr\n inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr\n inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr\n\n val watchdog = RegInit(0.U(32.W))\n val limit = PlusArg(\"tilelink_timeout\",\n docstring=\"Kill emulation after INT waiting TileLink cycles. Off if 0.\")\n monAssert (!inflight.orR || limit === 0.U || watchdog < limit, \"TileLink timeout expired\" + extra)\n\n watchdog := watchdog + 1.U\n when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }\n }\n\n def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {\n val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)\n val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything\n\n val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)\n val log_c_size_bus_size = log2Ceil(c_size_bus_size)\n def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits\n\n val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))\n val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))\n val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))\n inflight.suggestName(\"inflight\")\n inflight_opcodes.suggestName(\"inflight_opcodes\")\n inflight_sizes.suggestName(\"inflight_sizes\")\n\n val c_first = edge.first(bundle.c.bits, bundle.c.fire)\n val d_first = edge.first(bundle.d.bits, bundle.d.fire)\n c_first.suggestName(\"c_first\")\n d_first.suggestName(\"d_first\")\n\n val c_set = WireInit(0.U(edge.client.endSourceId.W))\n val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))\n val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))\n val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))\n c_set.suggestName(\"c_set\")\n c_set_wo_ready.suggestName(\"c_set_wo_ready\")\n c_opcodes_set.suggestName(\"c_opcodes_set\")\n c_sizes_set.suggestName(\"c_sizes_set\")\n\n val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))\n val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))\n c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U\n c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U\n c_opcode_lookup.suggestName(\"c_opcode_lookup\")\n c_size_lookup.suggestName(\"c_size_lookup\")\n\n val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))\n val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))\n c_opcodes_set_interm.suggestName(\"c_opcodes_set_interm\")\n c_sizes_set_interm.suggestName(\"c_sizes_set_interm\")\n\n when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {\n c_set_wo_ready := UIntToOH(bundle.c.bits.source)\n }\n\n when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {\n c_set := UIntToOH(bundle.c.bits.source)\n c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U\n c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U\n c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)\n c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)\n monAssert(!inflight(bundle.c.bits.source), \"'C' channel re-used a source ID\" + extra)\n }\n\n val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData\n\n val d_clr = WireInit(0.U(edge.client.endSourceId.W))\n val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))\n val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))\n val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))\n d_clr.suggestName(\"d_clr\")\n d_clr_wo_ready.suggestName(\"d_clr_wo_ready\")\n d_opcodes_clr.suggestName(\"d_opcodes_clr\")\n d_sizes_clr.suggestName(\"d_sizes_clr\")\n\n val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck\n when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {\n d_clr_wo_ready := UIntToOH(bundle.d.bits.source)\n }\n\n when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {\n d_clr := UIntToOH(bundle.d.bits.source)\n d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)\n d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)\n }\n\n when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {\n val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)\n assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, \"'D' channel acknowledged for nothing inflight\" + extra)\n when (same_cycle_resp) {\n assume((bundle.d.bits.size === bundle.c.bits.size), \"'D' channel contains improper response size\" + extra)\n } .otherwise {\n assume((bundle.d.bits.size === c_size_lookup), \"'D' channel contains improper response size\" + extra)\n }\n }\n\n when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {\n assume((!bundle.d.ready) || bundle.c.ready, \"ready check\")\n }\n\n if (edge.manager.minLatency > 0) {\n when (c_set_wo_ready.orR) {\n assume(c_set_wo_ready =/= d_clr_wo_ready, s\"'C' and 'D' concurrent, despite minlatency > 0\" + extra)\n }\n }\n\n inflight := (inflight | c_set) & ~d_clr\n inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr\n inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr\n\n val watchdog = RegInit(0.U(32.W))\n val limit = PlusArg(\"tilelink_timeout\",\n docstring=\"Kill emulation after INT waiting TileLink cycles. Off if 0.\")\n monAssert (!inflight.orR || limit === 0.U || watchdog < limit, \"TileLink timeout expired\" + extra)\n\n watchdog := watchdog + 1.U\n when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }\n }\n\n def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {\n val inflight = RegInit(0.U(edge.manager.endSinkId.W))\n\n val d_first = edge.first(bundle.d.bits, bundle.d.fire)\n val e_first = true.B\n\n val d_set = WireInit(0.U(edge.manager.endSinkId.W))\n when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {\n d_set := UIntToOH(bundle.d.bits.sink)\n assume(!inflight(bundle.d.bits.sink), \"'D' channel re-used a sink ID\" + extra)\n }\n\n val e_clr = WireInit(0.U(edge.manager.endSinkId.W))\n when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {\n e_clr := UIntToOH(bundle.e.bits.sink)\n monAssert((d_set | inflight)(bundle.e.bits.sink), \"'E' channel acknowledged for nothing inflight\" + extra)\n }\n\n // edge.client.minLatency applies to BC, not DE\n\n inflight := (inflight | d_set) & ~e_clr\n }\n\n def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {\n val sourceBits = log2Ceil(edge.client.endSourceId)\n val tooBig = 14 // >16kB worth of flight information gets to be too much\n if (sourceBits > tooBig) {\n println(s\"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked\")\n } else {\n if (args.edge.params(TestplanTestType).simulation) {\n if (args.edge.params(TLMonitorStrictMode)) {\n legalizeADSource(bundle, edge)\n legalizeCDSource(bundle, edge)\n } else {\n legalizeADSourceOld(bundle, edge)\n }\n }\n if (args.edge.params(TestplanTestType).formal) {\n legalizeADSourceFormal(bundle, edge)\n }\n }\n if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {\n // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...\n val sinkBits = log2Ceil(edge.manager.endSinkId)\n if (sinkBits > tooBig) {\n println(s\"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked\")\n } else {\n legalizeDESink(bundle, edge)\n }\n }\n }\n\n def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {\n legalizeFormat (bundle, edge)\n legalizeMultibeat (bundle, edge)\n legalizeUnique (bundle, edge)\n }\n}\nFile Misc.scala:\n// See LICENSE.Berkeley for license details.\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.util.random.LFSR\nimport org.chipsalliance.cde.config.Parameters\nimport scala.math._\n\nclass ParameterizedBundle(implicit p: Parameters) extends Bundle\n\ntrait Clocked extends Bundle {\n val clock = Clock()\n val reset = Bool() \n}\n\nobject DecoupledHelper {\n def apply(rvs: Bool*) = new DecoupledHelper(rvs)\n}\n\nclass DecoupledHelper(val rvs: Seq[Bool]) {\n def fire(exclude: Bool, includes: Bool*) = {\n require(rvs.contains(exclude), \"Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!\")\n (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)\n }\n def fire() = {\n rvs.reduce(_ && _)\n }\n}\n\nobject MuxT {\n def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =\n (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))\n\n def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =\n (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))\n\n def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =\n (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))\n}\n\n/** Creates a cascade of n MuxTs to search for a key value. */\nobject MuxTLookup {\n def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {\n var res = default\n for ((k, v) <- mapping.reverse)\n res = MuxT(k === key, v, res)\n res\n }\n\n def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {\n var res = default\n for ((k, v) <- mapping.reverse)\n res = MuxT(k === key, v, res)\n res\n }\n}\n\nobject ValidMux {\n def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {\n apply(v1 +: v2.toSeq)\n }\n def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {\n val out = Wire(Valid(valids.head.bits.cloneType))\n out.valid := valids.map(_.valid).reduce(_ || _)\n out.bits := MuxCase(valids.head.bits,\n valids.map(v => (v.valid -> v.bits)))\n out\n }\n}\n\nobject Str\n{\n def apply(s: String): UInt = {\n var i = BigInt(0)\n require(s.forall(validChar _))\n for (c <- s)\n i = (i << 8) | c\n i.U((s.length*8).W)\n }\n def apply(x: Char): UInt = {\n require(validChar(x))\n x.U(8.W)\n }\n def apply(x: UInt): UInt = apply(x, 10)\n def apply(x: UInt, radix: Int): UInt = {\n val rad = radix.U\n val w = x.getWidth\n require(w > 0)\n\n var q = x\n var s = digit(q % rad)\n for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {\n q = q / rad\n s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)\n }\n s\n }\n def apply(x: SInt): UInt = apply(x, 10)\n def apply(x: SInt, radix: Int): UInt = {\n val neg = x < 0.S\n val abs = x.abs.asUInt\n if (radix != 10) {\n Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))\n } else {\n val rad = radix.U\n val w = abs.getWidth\n require(w > 0)\n\n var q = abs\n var s = digit(q % rad)\n var needSign = neg\n for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {\n q = q / rad\n val placeSpace = q === 0.U\n val space = Mux(needSign, Str('-'), Str(' '))\n needSign = needSign && !placeSpace\n s = Cat(Mux(placeSpace, space, digit(q % rad)), s)\n }\n Cat(Mux(needSign, Str('-'), Str(' ')), s)\n }\n }\n\n private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)\n private def validChar(x: Char) = x == (x & 0xFF)\n}\n\nobject Split\n{\n def apply(x: UInt, n0: Int) = {\n val w = x.getWidth\n (x.extract(w-1,n0), x.extract(n0-1,0))\n }\n def apply(x: UInt, n1: Int, n0: Int) = {\n val w = x.getWidth\n (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))\n }\n def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {\n val w = x.getWidth\n (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))\n }\n}\n\nobject Random\n{\n def apply(mod: Int, random: UInt): UInt = {\n if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)\n else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))\n }\n def apply(mod: Int): UInt = apply(mod, randomizer)\n def oneHot(mod: Int, random: UInt): UInt = {\n if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))\n else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt\n }\n def oneHot(mod: Int): UInt = oneHot(mod, randomizer)\n\n private def randomizer = LFSR(16)\n private def partition(value: UInt, slices: Int) =\n Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)\n}\n\nobject Majority {\n def apply(in: Set[Bool]): Bool = {\n val n = (in.size >> 1) + 1\n val clauses = in.subsets(n).map(_.reduce(_ && _))\n clauses.reduce(_ || _)\n }\n\n def apply(in: Seq[Bool]): Bool = apply(in.toSet)\n\n def apply(in: UInt): Bool = apply(in.asBools.toSet)\n}\n\nobject PopCountAtLeast {\n private def two(x: UInt): (Bool, Bool) = x.getWidth match {\n case 1 => (x.asBool, false.B)\n case n =>\n val half = x.getWidth / 2\n val (leftOne, leftTwo) = two(x(half - 1, 0))\n val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))\n (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))\n }\n def apply(x: UInt, n: Int): Bool = n match {\n case 0 => true.B\n case 1 => x.orR\n case 2 => two(x)._2\n case 3 => PopCount(x) >= n.U\n }\n}\n\n// This gets used everywhere, so make the smallest circuit possible ...\n// Given an address and size, create a mask of beatBytes size\n// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111\n// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01\nobject MaskGen {\n def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {\n require (groupBy >= 1 && beatBytes >= groupBy)\n require (isPow2(beatBytes) && isPow2(groupBy))\n val lgBytes = log2Ceil(beatBytes)\n val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U\n\n def helper(i: Int): Seq[(Bool, Bool)] = {\n if (i == 0) {\n Seq((lgSize >= lgBytes.asUInt, true.B))\n } else {\n val sub = helper(i-1)\n val size = sizeOH(lgBytes - i)\n val bit = addr_lo(lgBytes - i)\n val nbit = !bit\n Seq.tabulate (1 << i) { j =>\n val (sub_acc, sub_eq) = sub(j/2)\n val eq = sub_eq && (if (j % 2 == 1) bit else nbit)\n val acc = sub_acc || (size && eq)\n (acc, eq)\n }\n }\n }\n\n if (groupBy == beatBytes) 1.U else\n Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)\n }\n}\nFile PlusArg.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3._\nimport chisel3.experimental._\nimport chisel3.util.HasBlackBoxResource\n\n@deprecated(\"This will be removed in Rocket Chip 2020.08\", \"Rocket Chip 2020.05\")\ncase class PlusArgInfo(default: BigInt, docstring: String)\n\n/** Case class for PlusArg information\n *\n * @tparam A scala type of the PlusArg value\n * @param default optional default value\n * @param docstring text to include in the help\n * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)\n */\nprivate case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)\n\n/** Typeclass for converting a type to a doctype string\n * @tparam A some type\n */\ntrait Doctypeable[A] {\n\n /** Return the doctype string for some option */\n def toDoctype(a: Option[A]): String\n\n}\n\n/** Object containing implementations of the Doctypeable typeclass */\nobject Doctypes {\n\n /** Converts an Int => \"INT\" */\n implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = \"INT\" }\n\n /** Converts a BigInt => \"INT\" */\n implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = \"INT\" }\n\n /** Converts a String => \"STRING\" */\n implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = \"STRING\" }\n\n}\n\nclass plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(\n \"FORMAT\" -> StringParam(format),\n \"DEFAULT\" -> IntParam(default),\n \"WIDTH\" -> IntParam(width)\n )) with HasBlackBoxResource {\n val io = IO(new Bundle {\n val out = Output(UInt(width.W))\n })\n\n addResource(\"/vsrc/plusarg_reader.v\")\n}\n\n/* This wrapper class has no outputs, making it clear it is a simulation-only construct */\nclass PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {\n val io = IO(new Bundle {\n val count = Input(UInt(width.W))\n })\n val max = Module(new plusarg_reader(format, default, docstring, width)).io.out\n when (max > 0.U) {\n assert (io.count < max, s\"Timeout exceeded: $docstring\")\n }\n}\n\nimport Doctypes._\n\nobject PlusArg\n{\n /** PlusArg(\"foo\") will return 42.U if the simulation is run with +foo=42\n * Do not use this as an initial register value. The value is set in an\n * initial block and thus accessing it from another initial is racey.\n * Add a docstring to document the arg, which can be dumped in an elaboration\n * pass.\n */\n def apply(name: String, default: BigInt = 0, docstring: String = \"\", width: Int = 32): UInt = {\n PlusArgArtefacts.append(name, Some(default), docstring)\n Module(new plusarg_reader(name + \"=%d\", default, docstring, width)).io.out\n }\n\n /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert\n * to kill the simulation when count exceeds the specified integer argument.\n * Default 0 will never assert.\n */\n def timeout(name: String, default: BigInt = 0, docstring: String = \"\", width: Int = 32)(count: UInt): Unit = {\n PlusArgArtefacts.append(name, Some(default), docstring)\n Module(new PlusArgTimeout(name + \"=%d\", default, docstring, width)).io.count := count\n }\n}\n\nobject PlusArgArtefacts {\n private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty\n\n /* Add a new PlusArg */\n @deprecated(\n \"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08\",\n \"Rocket Chip 2020.05\"\n )\n def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)\n\n /** Add a new PlusArg\n *\n * @tparam A scala type of the PlusArg value\n * @param name name for the PlusArg\n * @param default optional default value\n * @param docstring text to include in the help\n */\n def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =\n artefacts = artefacts ++\n Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))\n\n /* From plus args, generate help text */\n private def serializeHelp_cHeader(tab: String = \"\"): String = artefacts\n .map{ case(arg, info) =>\n s\"\"\"|$tab+$arg=${info.doctype}\\\\n\\\\\n |$tab${\" \"*20}${info.docstring}\\\\n\\\\\n |\"\"\".stripMargin ++ info.default.map{ case default =>\n s\"$tab${\" \"*22}(default=${default})\\\\n\\\\\\n\"}.getOrElse(\"\")\n }.toSeq.mkString(\"\\\\n\\\\\\n\") ++ \"\\\"\"\n\n /* From plus args, generate a char array of their names */\n private def serializeArray_cHeader(tab: String = \"\"): String = {\n val prettyTab = tab + \" \" * 44 // Length of 'static const ...'\n s\"${tab}static const char * verilog_plusargs [] = {\\\\\\n\" ++\n artefacts\n .map{ case(arg, _) => s\"\"\"$prettyTab\"$arg\",\\\\\\n\"\"\" }\n .mkString(\"\")++\n s\"${prettyTab}0};\"\n }\n\n /* Generate C code to be included in emulator.cc that helps with\n * argument parsing based on available Verilog PlusArgs */\n def serialize_cHeader(): String =\n s\"\"\"|#define PLUSARG_USAGE_OPTIONS \\\"EMULATOR VERILOG PLUSARGS\\\\n\\\\\n |${serializeHelp_cHeader(\" \"*7)}\n |${serializeArray_cHeader()}\n |\"\"\".stripMargin\n}\nFile package.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip\n\nimport chisel3._\nimport chisel3.util._\nimport scala.math.min\nimport scala.collection.{immutable, mutable}\n\npackage object util {\n implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {\n def unzip = (x.map(_._1), x.map(_._2))\n }\n\n implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {\n def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR\n \n def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)\n }\n\n implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {\n\n /** Like Vec.apply(idx), but tolerates indices of mismatched width */\n def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))\n }\n\n implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {\n def apply(idx: UInt): T = {\n if (x.size <= 1) {\n x.head\n } else if (!isPow2(x.size)) {\n // For non-power-of-2 seqs, reflect elements to simplify decoder\n (x ++ x.takeRight(x.size & -x.size)).toSeq(idx)\n } else {\n // Ignore MSBs of idx\n val truncIdx =\n if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx\n else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)\n x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }\n }\n }\n\n def extract(idx: UInt): T = VecInit(x).extract(idx)\n\n def asUInt: UInt = Cat(x.map(_.asUInt).reverse)\n\n def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)\n\n def rotate(n: UInt): Seq[T] = {\n if (x.size <= 1) {\n x\n } else {\n require(isPow2(x.size))\n val amt = n.padTo(log2Ceil(x.size))\n (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })\n }\n }\n\n def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)\n\n def rotateRight(n: UInt): Seq[T] = {\n if (x.size <= 1) {\n x\n } else {\n require(isPow2(x.size))\n val amt = n.padTo(log2Ceil(x.size))\n (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })\n }\n }\n }\n\n // allow bitwise ops on Seq[Bool] just like UInt\n implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {\n def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }\n def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }\n def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }\n def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x\n def >> (n: Int): Seq[Bool] = x drop n\n def unary_~ : Seq[Bool] = x.map(!_)\n def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)\n def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)\n def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)\n\n private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)\n }\n\n implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {\n def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))\n\n def getElements: Seq[Element] = x match {\n case e: Element => Seq(e)\n case a: Aggregate => a.getElements.flatMap(_.getElements)\n }\n }\n\n /** Any Data subtype that has a Bool member named valid. */\n type DataCanBeValid = Data { val valid: Bool }\n\n implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {\n def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)\n }\n\n implicit class StringToAugmentedString(private val x: String) extends AnyVal {\n /** converts from camel case to to underscores, also removing all spaces */\n def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + \"\") getOrElse \"\") {\n case (acc, c) if c.isUpper => acc + \"_\" + c.toLower\n case (acc, c) if c == ' ' => acc\n case (acc, c) => acc + c\n }\n\n /** converts spaces or underscores to hyphens, also lowering case */\n def kebab: String = x.toLowerCase map {\n case ' ' => '-'\n case '_' => '-'\n case c => c\n }\n\n def named(name: Option[String]): String = {\n x + name.map(\"_named_\" + _ ).getOrElse(\"_with_no_name\")\n }\n\n def named(name: String): String = named(Some(name))\n }\n\n implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)\n implicit def wcToUInt(c: WideCounter): UInt = c.value\n\n implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {\n def sextTo(n: Int): UInt = {\n require(x.getWidth <= n)\n if (x.getWidth == n) x\n else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)\n }\n\n def padTo(n: Int): UInt = {\n require(x.getWidth <= n)\n if (x.getWidth == n) x\n else Cat(0.U((n - x.getWidth).W), x)\n }\n\n // shifts left by n if n >= 0, or right by -n if n < 0\n def << (n: SInt): UInt = {\n val w = n.getWidth - 1\n require(w <= 30)\n\n val shifted = x << n(w-1, 0)\n Mux(n(w), shifted >> (1 << w), shifted)\n }\n\n // shifts right by n if n >= 0, or left by -n if n < 0\n def >> (n: SInt): UInt = {\n val w = n.getWidth - 1\n require(w <= 30)\n\n val shifted = x << (1 << w) >> n(w-1, 0)\n Mux(n(w), shifted, shifted >> (1 << w))\n }\n\n // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts\n def extract(hi: Int, lo: Int): UInt = {\n require(hi >= lo-1)\n if (hi == lo-1) 0.U\n else x(hi, lo)\n }\n\n // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts\n def extractOption(hi: Int, lo: Int): Option[UInt] = {\n require(hi >= lo-1)\n if (hi == lo-1) None\n else Some(x(hi, lo))\n }\n\n // like x & ~y, but first truncate or zero-extend y to x's width\n def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))\n\n def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)\n\n def rotateRight(n: UInt): UInt = {\n if (x.getWidth <= 1) {\n x\n } else {\n val amt = n.padTo(log2Ceil(x.getWidth))\n (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))\n }\n }\n\n def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))\n\n def rotateLeft(n: UInt): UInt = {\n if (x.getWidth <= 1) {\n x\n } else {\n val amt = n.padTo(log2Ceil(x.getWidth))\n (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))\n }\n }\n\n // compute (this + y) % n, given (this < n) and (y < n)\n def addWrap(y: UInt, n: Int): UInt = {\n val z = x +& y\n if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)\n }\n\n // compute (this - y) % n, given (this < n) and (y < n)\n def subWrap(y: UInt, n: Int): UInt = {\n val z = x -& y\n if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)\n }\n\n def grouped(width: Int): Seq[UInt] =\n (0 until x.getWidth by width).map(base => x(base + width - 1, base))\n\n def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds\n\n def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)\n\n // Like >=, but prevents x-prop for ('x >= 0)\n def >== (y: UInt): Bool = x >= y || y === 0.U\n }\n\n implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {\n def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)\n def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)\n }\n\n implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {\n def toInt: Int = if (x) 1 else 0\n\n // this one's snagged from scalaz\n def option[T](z: => T): Option[T] = if (x) Some(z) else None\n }\n\n implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {\n // exact log2\n def log2: Int = {\n require(isPow2(x))\n log2Ceil(x)\n }\n }\n\n def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)\n def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))\n def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)\n def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)\n\n def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None\n\n // Fill 1s from low bits to high bits\n def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)\n def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {\n val stop = min(width, cap)\n def helper(s: Int, x: UInt): UInt =\n if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))\n helper(1, x)(width-1, 0)\n }\n\n // Fill 1s form high bits to low bits\n def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)\n def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {\n val stop = min(width, cap)\n def helper(s: Int, x: UInt): UInt =\n if (s >= stop) x else helper(s+s, x | (x >> s))\n helper(1, x)(width-1, 0)\n }\n\n def OptimizationBarrier[T <: Data](in: T): T = {\n val barrier = Module(new Module {\n val io = IO(new Bundle {\n val x = Input(chiselTypeOf(in))\n val y = Output(chiselTypeOf(in))\n })\n io.y := io.x\n override def desiredName = s\"OptimizationBarrier_${in.typeName}\"\n })\n barrier.io.x := in\n barrier.io.y\n }\n\n /** Similar to Seq.groupBy except this returns a Seq instead of a Map\n * Useful for deterministic code generation\n */\n def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {\n val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]\n for (x <- xs) {\n val key = f(x)\n val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])\n l += x\n }\n map.view.map({ case (k, vs) => k -> vs.toList }).toList\n }\n\n def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {\n case 1 => List.fill(n)(in.head)\n case x if x == n => in\n case _ => throw new Exception(s\"must provide exactly 1 or $n of some field, but got:\\n$in\")\n }\n\n // HeterogeneousBag moved to standalond diplomacy\n @deprecated(\"HeterogeneousBag has been absorbed into standalone diplomacy library\", \"rocketchip 2.0.0\")\n def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)\n @deprecated(\"HeterogeneousBag has been absorbed into standalone diplomacy library\", \"rocketchip 2.0.0\")\n val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag\n}\nFile Bundles.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.tilelink\n\nimport chisel3._\nimport freechips.rocketchip.util._\nimport scala.collection.immutable.ListMap\nimport chisel3.util.Decoupled\nimport chisel3.util.DecoupledIO\nimport chisel3.reflect.DataMirror\n\nabstract class TLBundleBase(val params: TLBundleParameters) extends Bundle\n\n// common combos in lazy policy:\n// Put + Acquire\n// Release + AccessAck\n\nobject TLMessages\n{\n // A B C D E\n def PutFullData = 0.U // . . => AccessAck\n def PutPartialData = 1.U // . . => AccessAck\n def ArithmeticData = 2.U // . . => AccessAckData\n def LogicalData = 3.U // . . => AccessAckData\n def Get = 4.U // . . => AccessAckData\n def Hint = 5.U // . . => HintAck\n def AcquireBlock = 6.U // . => Grant[Data]\n def AcquirePerm = 7.U // . => Grant[Data]\n def Probe = 6.U // . => ProbeAck[Data]\n def AccessAck = 0.U // . .\n def AccessAckData = 1.U // . .\n def HintAck = 2.U // . .\n def ProbeAck = 4.U // .\n def ProbeAckData = 5.U // .\n def Release = 6.U // . => ReleaseAck\n def ReleaseData = 7.U // . => ReleaseAck\n def Grant = 4.U // . => GrantAck\n def GrantData = 5.U // . => GrantAck\n def ReleaseAck = 6.U // .\n def GrantAck = 0.U // .\n\n def isA(x: UInt) = x <= AcquirePerm\n def isB(x: UInt) = x <= Probe\n def isC(x: UInt) = x <= ReleaseData\n def isD(x: UInt) = x <= ReleaseAck\n\n def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant)\n def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck)\n\n def a = Seq( (\"PutFullData\",TLPermissions.PermMsgReserved),\n (\"PutPartialData\",TLPermissions.PermMsgReserved),\n (\"ArithmeticData\",TLAtomics.ArithMsg),\n (\"LogicalData\",TLAtomics.LogicMsg),\n (\"Get\",TLPermissions.PermMsgReserved),\n (\"Hint\",TLHints.HintsMsg),\n (\"AcquireBlock\",TLPermissions.PermMsgGrow),\n (\"AcquirePerm\",TLPermissions.PermMsgGrow))\n\n def b = Seq( (\"PutFullData\",TLPermissions.PermMsgReserved),\n (\"PutPartialData\",TLPermissions.PermMsgReserved),\n (\"ArithmeticData\",TLAtomics.ArithMsg),\n (\"LogicalData\",TLAtomics.LogicMsg),\n (\"Get\",TLPermissions.PermMsgReserved),\n (\"Hint\",TLHints.HintsMsg),\n (\"Probe\",TLPermissions.PermMsgCap))\n\n def c = Seq( (\"AccessAck\",TLPermissions.PermMsgReserved),\n (\"AccessAckData\",TLPermissions.PermMsgReserved),\n (\"HintAck\",TLPermissions.PermMsgReserved),\n (\"Invalid Opcode\",TLPermissions.PermMsgReserved),\n (\"ProbeAck\",TLPermissions.PermMsgReport),\n (\"ProbeAckData\",TLPermissions.PermMsgReport),\n (\"Release\",TLPermissions.PermMsgReport),\n (\"ReleaseData\",TLPermissions.PermMsgReport))\n\n def d = Seq( (\"AccessAck\",TLPermissions.PermMsgReserved),\n (\"AccessAckData\",TLPermissions.PermMsgReserved),\n (\"HintAck\",TLPermissions.PermMsgReserved),\n (\"Invalid Opcode\",TLPermissions.PermMsgReserved),\n (\"Grant\",TLPermissions.PermMsgCap),\n (\"GrantData\",TLPermissions.PermMsgCap),\n (\"ReleaseAck\",TLPermissions.PermMsgReserved))\n\n}\n\n/**\n * The three primary TileLink permissions are:\n * (T)runk: the agent is (or is on inwards path to) the global point of serialization.\n * (B)ranch: the agent is on an outwards path to\n * (N)one:\n * These permissions are permuted by transfer operations in various ways.\n * Operations can cap permissions, request for them to be grown or shrunk,\n * or for a report on their current status.\n */\nobject TLPermissions\n{\n val aWidth = 2\n val bdWidth = 2\n val cWidth = 3\n\n // Cap types (Grant = new permissions, Probe = permisions <= target)\n def toT = 0.U(bdWidth.W)\n def toB = 1.U(bdWidth.W)\n def toN = 2.U(bdWidth.W)\n def isCap(x: UInt) = x <= toN\n\n // Grow types (Acquire = permissions >= target)\n def NtoB = 0.U(aWidth.W)\n def NtoT = 1.U(aWidth.W)\n def BtoT = 2.U(aWidth.W)\n def isGrow(x: UInt) = x <= BtoT\n\n // Shrink types (ProbeAck, Release)\n def TtoB = 0.U(cWidth.W)\n def TtoN = 1.U(cWidth.W)\n def BtoN = 2.U(cWidth.W)\n def isShrink(x: UInt) = x <= BtoN\n\n // Report types (ProbeAck, Release)\n def TtoT = 3.U(cWidth.W)\n def BtoB = 4.U(cWidth.W)\n def NtoN = 5.U(cWidth.W)\n def isReport(x: UInt) = x <= NtoN\n\n def PermMsgGrow:Seq[String] = Seq(\"Grow NtoB\", \"Grow NtoT\", \"Grow BtoT\")\n def PermMsgCap:Seq[String] = Seq(\"Cap toT\", \"Cap toB\", \"Cap toN\")\n def PermMsgReport:Seq[String] = Seq(\"Shrink TtoB\", \"Shrink TtoN\", \"Shrink BtoN\", \"Report TotT\", \"Report BtoB\", \"Report NtoN\")\n def PermMsgReserved:Seq[String] = Seq(\"Reserved\")\n}\n\nobject TLAtomics\n{\n val width = 3\n\n // Arithmetic types\n def MIN = 0.U(width.W)\n def MAX = 1.U(width.W)\n def MINU = 2.U(width.W)\n def MAXU = 3.U(width.W)\n def ADD = 4.U(width.W)\n def isArithmetic(x: UInt) = x <= ADD\n\n // Logical types\n def XOR = 0.U(width.W)\n def OR = 1.U(width.W)\n def AND = 2.U(width.W)\n def SWAP = 3.U(width.W)\n def isLogical(x: UInt) = x <= SWAP\n\n def ArithMsg:Seq[String] = Seq(\"MIN\", \"MAX\", \"MINU\", \"MAXU\", \"ADD\")\n def LogicMsg:Seq[String] = Seq(\"XOR\", \"OR\", \"AND\", \"SWAP\")\n}\n\n\nobject TLHints\n{\n val width = 1\n\n def PREFETCH_READ = 0.U(width.W)\n def PREFETCH_WRITE = 1.U(width.W)\n def isHints(x: UInt) = x <= PREFETCH_WRITE\n\n def HintsMsg:Seq[String] = Seq(\"PrefetchRead\", \"PrefetchWrite\")\n}\n\nsealed trait TLChannel extends TLBundleBase {\n val channelName: String\n}\n\nsealed trait TLDataChannel extends TLChannel\nsealed trait TLAddrChannel extends TLDataChannel\n\nfinal class TLBundleA(params: TLBundleParameters)\n extends TLBundleBase(params) with TLAddrChannel\n{\n override def typeName = s\"TLBundleA_${params.shortName}\"\n val channelName = \"'A' channel\"\n // fixed fields during multibeat:\n val opcode = UInt(3.W)\n val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint\n val size = UInt(params.sizeBits.W)\n val source = UInt(params.sourceBits.W) // from\n val address = UInt(params.addressBits.W) // to\n val user = BundleMap(params.requestFields)\n val echo = BundleMap(params.echoFields)\n // variable fields during multibeat:\n val mask = UInt((params.dataBits/8).W)\n val data = UInt(params.dataBits.W)\n val corrupt = Bool() // only applies to *Data messages\n}\nfinal class TLBundleB(params: TLBundleParameters)\n extends TLBundleBase(params) with TLAddrChannel\n{\n override def typeName = s\"TLBundleB_${params.shortName}\"\n val channelName = \"'B' channel\"\n // fixed fields during multibeat:\n val opcode = UInt(3.W)\n val param = UInt(TLPermissions.bdWidth.W) // cap perms\n val size = UInt(params.sizeBits.W)\n val source = UInt(params.sourceBits.W) // to\n val address = UInt(params.addressBits.W) // from\n // variable fields during multibeat:\n val mask = UInt((params.dataBits/8).W)\n val data = UInt(params.dataBits.W)\n val corrupt = Bool() // only applies to *Data messages\n}\n\nfinal class TLBundleC(params: TLBundleParameters)\n extends TLBundleBase(params) with TLAddrChannel\n{\n override def typeName = s\"TLBundleC_${params.shortName}\"\n val channelName = \"'C' channel\"\n // fixed fields during multibeat:\n val opcode = UInt(3.W)\n val param = UInt(TLPermissions.cWidth.W) // shrink or report perms\n val size = UInt(params.sizeBits.W)\n val source = UInt(params.sourceBits.W) // from\n val address = UInt(params.addressBits.W) // to\n val user = BundleMap(params.requestFields)\n val echo = BundleMap(params.echoFields)\n // variable fields during multibeat:\n val data = UInt(params.dataBits.W)\n val corrupt = Bool() // only applies to *Data messages\n}\n\nfinal class TLBundleD(params: TLBundleParameters)\n extends TLBundleBase(params) with TLDataChannel\n{\n override def typeName = s\"TLBundleD_${params.shortName}\"\n val channelName = \"'D' channel\"\n // fixed fields during multibeat:\n val opcode = UInt(3.W)\n val param = UInt(TLPermissions.bdWidth.W) // cap perms\n val size = UInt(params.sizeBits.W)\n val source = UInt(params.sourceBits.W) // to\n val sink = UInt(params.sinkBits.W) // from\n val denied = Bool() // implies corrupt iff *Data\n val user = BundleMap(params.responseFields)\n val echo = BundleMap(params.echoFields)\n // variable fields during multibeat:\n val data = UInt(params.dataBits.W)\n val corrupt = Bool() // only applies to *Data messages\n}\n\nfinal class TLBundleE(params: TLBundleParameters)\n extends TLBundleBase(params) with TLChannel\n{\n override def typeName = s\"TLBundleE_${params.shortName}\"\n val channelName = \"'E' channel\"\n val sink = UInt(params.sinkBits.W) // to\n}\n\nclass TLBundle(val params: TLBundleParameters) extends Record\n{\n // Emulate a Bundle with elements abcde or ad depending on params.hasBCE\n\n private val optA = Some (Decoupled(new TLBundleA(params)))\n private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params))))\n private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params)))\n private val optD = Some (Flipped(Decoupled(new TLBundleD(params))))\n private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params)))\n\n def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params)))))\n def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params)))))\n def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params)))))\n def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params)))))\n def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params)))))\n\n val elements =\n if (params.hasBCE) ListMap(\"e\" -> e, \"d\" -> d, \"c\" -> c, \"b\" -> b, \"a\" -> a)\n else ListMap(\"d\" -> d, \"a\" -> a)\n\n def tieoff(): Unit = {\n DataMirror.specifiedDirectionOf(a.ready) match {\n case SpecifiedDirection.Input =>\n a.ready := false.B\n c.ready := false.B\n e.ready := false.B\n b.valid := false.B\n d.valid := false.B\n case SpecifiedDirection.Output =>\n a.valid := false.B\n c.valid := false.B\n e.valid := false.B\n b.ready := false.B\n d.ready := false.B\n case _ =>\n }\n }\n}\n\nobject TLBundle\n{\n def apply(params: TLBundleParameters) = new TLBundle(params)\n}\n\nclass TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle\n\nclass TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params)\n{\n val a = new AsyncBundle(new TLBundleA(params.base), params.async)\n val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async))\n val c = new AsyncBundle(new TLBundleC(params.base), params.async)\n val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async))\n val e = new AsyncBundle(new TLBundleE(params.base), params.async)\n}\n\nclass TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params)\n{\n val a = RationalIO(new TLBundleA(params))\n val b = Flipped(RationalIO(new TLBundleB(params)))\n val c = RationalIO(new TLBundleC(params))\n val d = Flipped(RationalIO(new TLBundleD(params)))\n val e = RationalIO(new TLBundleE(params))\n}\n\nclass TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params)\n{\n val a = CreditedIO(new TLBundleA(params))\n val b = Flipped(CreditedIO(new TLBundleB(params)))\n val c = CreditedIO(new TLBundleC(params))\n val d = Flipped(CreditedIO(new TLBundleD(params)))\n val e = CreditedIO(new TLBundleE(params))\n}\nFile Parameters.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.diplomacy\n\nimport chisel3._\nimport chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}\nimport freechips.rocketchip.util.ShiftQueue\n\n/** Options for describing the attributes of memory regions */\nobject RegionType {\n // Define the 'more relaxed than' ordering\n val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)\n sealed trait T extends Ordered[T] {\n def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)\n }\n\n case object CACHED extends T // an intermediate agent may have cached a copy of the region for you\n case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided\n case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible\n case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached\n case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects\n case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed\n case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively\n}\n\n// A non-empty half-open range; [start, end)\ncase class IdRange(start: Int, end: Int) extends Ordered[IdRange]\n{\n require (start >= 0, s\"Ids cannot be negative, but got: $start.\")\n require (start <= end, \"Id ranges cannot be negative.\")\n\n def compare(x: IdRange) = {\n val primary = (this.start - x.start).signum\n val secondary = (x.end - this.end).signum\n if (primary != 0) primary else secondary\n }\n\n def overlaps(x: IdRange) = start < x.end && x.start < end\n def contains(x: IdRange) = start <= x.start && x.end <= end\n\n def contains(x: Int) = start <= x && x < end\n def contains(x: UInt) =\n if (size == 0) {\n false.B\n } else if (size == 1) { // simple comparison\n x === start.U\n } else {\n // find index of largest different bit\n val largestDeltaBit = log2Floor(start ^ (end-1))\n val smallestCommonBit = largestDeltaBit + 1 // may not exist in x\n val uncommonMask = (1 << smallestCommonBit) - 1\n val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)\n // the prefix must match exactly (note: may shift ALL bits away)\n (x >> smallestCommonBit) === (start >> smallestCommonBit).U &&\n // firrtl constant prop range analysis can eliminate these two:\n (start & uncommonMask).U <= uncommonBits &&\n uncommonBits <= ((end-1) & uncommonMask).U\n }\n\n def shift(x: Int) = IdRange(start+x, end+x)\n def size = end - start\n def isEmpty = end == start\n\n def range = start until end\n}\n\nobject IdRange\n{\n def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {\n val ranges = s.sorted\n (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }\n }\n}\n\n// An potentially empty inclusive range of 2-powers [min, max] (in bytes)\ncase class TransferSizes(min: Int, max: Int)\n{\n def this(x: Int) = this(x, x)\n\n require (min <= max, s\"Min transfer $min > max transfer $max\")\n require (min >= 0 && max >= 0, s\"TransferSizes must be positive, got: ($min, $max)\")\n require (max == 0 || isPow2(max), s\"TransferSizes must be a power of 2, got: $max\")\n require (min == 0 || isPow2(min), s\"TransferSizes must be a power of 2, got: $min\")\n require (max == 0 || min != 0, s\"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)\")\n\n def none = min == 0\n def contains(x: Int) = isPow2(x) && min <= x && x <= max\n def containsLg(x: Int) = contains(1 << x)\n def containsLg(x: UInt) =\n if (none) false.B\n else if (min == max) { log2Ceil(min).U === x }\n else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }\n\n def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)\n\n def intersect(x: TransferSizes) =\n if (x.max < min || max < x.min) TransferSizes.none\n else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))\n\n // Not a union, because the result may contain sizes contained by neither term\n // NOT TO BE CONFUSED WITH COVERPOINTS\n def mincover(x: TransferSizes) = {\n if (none) {\n x\n } else if (x.none) {\n this\n } else {\n TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))\n }\n }\n\n override def toString() = \"TransferSizes[%d, %d]\".format(min, max)\n}\n\nobject TransferSizes {\n def apply(x: Int) = new TransferSizes(x)\n val none = new TransferSizes(0)\n\n def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)\n def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)\n\n implicit def asBool(x: TransferSizes) = !x.none\n}\n\n// AddressSets specify the address space managed by the manager\n// Base is the base address, and mask are the bits consumed by the manager\n// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff\n// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...\ncase class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]\n{\n // Forbid misaligned base address (and empty sets)\n require ((base & mask) == 0, s\"Mis-aligned AddressSets are forbidden, got: ${this.toString}\")\n require (base >= 0, s\"AddressSet negative base is ambiguous: $base\") // TL2 address widths are not fixed => negative is ambiguous\n // We do allow negative mask (=> ignore all high bits)\n\n def contains(x: BigInt) = ((x ^ base) & ~mask) == 0\n def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S\n\n // turn x into an address contained in this set\n def legalize(x: UInt): UInt = base.U | (mask.U & x)\n\n // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)\n def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0\n // contains iff bitwise: x.mask => mask && contains(x.base)\n def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0\n\n // The number of bytes to which the manager must be aligned\n def alignment = ((mask + 1) & ~mask)\n // Is this a contiguous memory range\n def contiguous = alignment == mask+1\n\n def finite = mask >= 0\n def max = { require (finite, \"Max cannot be calculated on infinite mask\"); base | mask }\n\n // Widen the match function to ignore all bits in imask\n def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)\n\n // Return an AddressSet that only contains the addresses both sets contain\n def intersect(x: AddressSet): Option[AddressSet] = {\n if (!overlaps(x)) {\n None\n } else {\n val r_mask = mask & x.mask\n val r_base = base | x.base\n Some(AddressSet(r_base, r_mask))\n }\n }\n\n def subtract(x: AddressSet): Seq[AddressSet] = {\n intersect(x) match {\n case None => Seq(this)\n case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>\n val nmask = (mask & (bit-1)) | remove.mask\n val nbase = (remove.base ^ bit) & ~nmask\n AddressSet(nbase, nmask)\n }\n }\n }\n\n // AddressSets have one natural Ordering (the containment order, if contiguous)\n def compare(x: AddressSet) = {\n val primary = (this.base - x.base).signum // smallest address first\n val secondary = (x.mask - this.mask).signum // largest mask first\n if (primary != 0) primary else secondary\n }\n\n // We always want to see things in hex\n override def toString() = {\n if (mask >= 0) {\n \"AddressSet(0x%x, 0x%x)\".format(base, mask)\n } else {\n \"AddressSet(0x%x, ~0x%x)\".format(base, ~mask)\n }\n }\n\n def toRanges = {\n require (finite, \"Ranges cannot be calculated on infinite mask\")\n val size = alignment\n val fragments = mask & ~(size-1)\n val bits = bitIndexes(fragments)\n (BigInt(0) until (BigInt(1) << bits.size)).map { i =>\n val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }\n AddressRange(off, size)\n }\n }\n}\n\nobject AddressSet\n{\n val everything = AddressSet(0, -1)\n def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {\n if (size == 0) tail.reverse else {\n val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)\n val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size\n val step =\n if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)\n maxSizeAlignment else maxBaseAlignment\n misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)\n }\n }\n\n def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {\n // Pair terms up by ignoring 'bit'\n seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>\n if (seq.size == 1) {\n seq.head // singleton -> unaffected\n } else {\n key.copy(mask = key.mask | bit) // pair - widen mask by bit\n }\n }.toList\n }\n\n def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {\n val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)\n AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted\n }\n\n def enumerateMask(mask: BigInt): Seq[BigInt] = {\n def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =\n if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)\n helper(0, Nil)\n }\n\n def enumerateBits(mask: BigInt): Seq[BigInt] = {\n def helper(x: BigInt): Seq[BigInt] = {\n if (x == 0) {\n Nil\n } else {\n val bit = x & (-x)\n bit +: helper(x & ~bit)\n }\n }\n helper(mask)\n }\n}\n\ncase class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)\n{\n require (depth >= 0, \"Buffer depth must be >= 0\")\n def isDefined = depth > 0\n def latency = if (isDefined && !flow) 1 else 0\n\n def apply[T <: Data](x: DecoupledIO[T]) =\n if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)\n else x\n\n def irrevocable[T <: Data](x: ReadyValidIO[T]) =\n if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)\n else x\n\n def sq[T <: Data](x: DecoupledIO[T]) =\n if (!isDefined) x else {\n val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))\n sq.io.enq <> x\n sq.io.deq\n }\n\n override def toString() = \"BufferParams:%d%s%s\".format(depth, if (flow) \"F\" else \"\", if (pipe) \"P\" else \"\")\n\n}\n\nobject BufferParams\n{\n implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)\n\n val default = BufferParams(2)\n val none = BufferParams(0)\n val flow = BufferParams(1, true, false)\n val pipe = BufferParams(1, false, true)\n}\n\ncase class TriStateValue(value: Boolean, set: Boolean)\n{\n def update(orig: Boolean) = if (set) value else orig\n}\n\nobject TriStateValue\n{\n implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)\n def unset = TriStateValue(false, false)\n}\n\ntrait DirectedBuffers[T] {\n def copyIn(x: BufferParams): T\n def copyOut(x: BufferParams): T\n def copyInOut(x: BufferParams): T\n}\n\ntrait IdMapEntry {\n def name: String\n def from: IdRange\n def to: IdRange\n def isCache: Boolean\n def requestFifo: Boolean\n def maxTransactionsInFlight: Option[Int]\n def pretty(fmt: String) =\n if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5\n fmt.format(to.start, to.end, from.start, from.end, s\"\"\"\"$name\"\"\"\", if (isCache) \" [CACHE]\" else \"\", if (requestFifo) \" [FIFO]\" else \"\")\n } else {\n fmt.format(from.start, from.end, s\"\"\"\"$name\"\"\"\", if (isCache) \" [CACHE]\" else \"\", if (requestFifo) \" [FIFO]\" else \"\")\n }\n}\n\nabstract class IdMap[T <: IdMapEntry] {\n protected val fmt: String\n val mapping: Seq[T]\n def pretty: String = mapping.map(_.pretty(fmt)).mkString(\",\\n\")\n}\nFile Edges.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.tilelink\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.experimental.SourceInfo\nimport org.chipsalliance.cde.config.Parameters\nimport freechips.rocketchip.util._\n\nclass TLEdge(\n client: TLClientPortParameters,\n manager: TLManagerPortParameters,\n params: Parameters,\n sourceInfo: SourceInfo)\n extends TLEdgeParameters(client, manager, params, sourceInfo)\n{\n def isAligned(address: UInt, lgSize: UInt): Bool = {\n if (maxLgSize == 0) true.B else {\n val mask = UIntToOH1(lgSize, maxLgSize)\n (address & mask) === 0.U\n }\n }\n\n def mask(address: UInt, lgSize: UInt): UInt =\n MaskGen(address, lgSize, manager.beatBytes)\n\n def staticHasData(bundle: TLChannel): Option[Boolean] = {\n bundle match {\n case _:TLBundleA => {\n // Do there exist A messages with Data?\n val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial\n // Do there exist A messages without Data?\n val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint\n // Statically optimize the case where hasData is a constant\n if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None\n }\n case _:TLBundleB => {\n // Do there exist B messages with Data?\n val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial\n // Do there exist B messages without Data?\n val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint\n // Statically optimize the case where hasData is a constant\n if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None\n }\n case _:TLBundleC => {\n // Do there eixst C messages with Data?\n val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe\n // Do there exist C messages without Data?\n val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe\n if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None\n }\n case _:TLBundleD => {\n // Do there eixst D messages with Data?\n val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB\n // Do there exist D messages without Data?\n val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT\n if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None\n }\n case _:TLBundleE => Some(false)\n }\n }\n\n def isRequest(x: TLChannel): Bool = {\n x match {\n case a: TLBundleA => true.B\n case b: TLBundleB => true.B\n case c: TLBundleC => c.opcode(2) && c.opcode(1)\n // opcode === TLMessages.Release ||\n // opcode === TLMessages.ReleaseData\n case d: TLBundleD => d.opcode(2) && !d.opcode(1)\n // opcode === TLMessages.Grant ||\n // opcode === TLMessages.GrantData\n case e: TLBundleE => false.B\n }\n }\n\n def isResponse(x: TLChannel): Bool = {\n x match {\n case a: TLBundleA => false.B\n case b: TLBundleB => false.B\n case c: TLBundleC => !c.opcode(2) || !c.opcode(1)\n // opcode =/= TLMessages.Release &&\n // opcode =/= TLMessages.ReleaseData\n case d: TLBundleD => true.B // Grant isResponse + isRequest\n case e: TLBundleE => true.B\n }\n }\n\n def hasData(x: TLChannel): Bool = {\n val opdata = x match {\n case a: TLBundleA => !a.opcode(2)\n // opcode === TLMessages.PutFullData ||\n // opcode === TLMessages.PutPartialData ||\n // opcode === TLMessages.ArithmeticData ||\n // opcode === TLMessages.LogicalData\n case b: TLBundleB => !b.opcode(2)\n // opcode === TLMessages.PutFullData ||\n // opcode === TLMessages.PutPartialData ||\n // opcode === TLMessages.ArithmeticData ||\n // opcode === TLMessages.LogicalData\n case c: TLBundleC => c.opcode(0)\n // opcode === TLMessages.AccessAckData ||\n // opcode === TLMessages.ProbeAckData ||\n // opcode === TLMessages.ReleaseData\n case d: TLBundleD => d.opcode(0)\n // opcode === TLMessages.AccessAckData ||\n // opcode === TLMessages.GrantData\n case e: TLBundleE => false.B\n }\n staticHasData(x).map(_.B).getOrElse(opdata)\n }\n\n def opcode(x: TLDataChannel): UInt = {\n x match {\n case a: TLBundleA => a.opcode\n case b: TLBundleB => b.opcode\n case c: TLBundleC => c.opcode\n case d: TLBundleD => d.opcode\n }\n }\n\n def param(x: TLDataChannel): UInt = {\n x match {\n case a: TLBundleA => a.param\n case b: TLBundleB => b.param\n case c: TLBundleC => c.param\n case d: TLBundleD => d.param\n }\n }\n\n def size(x: TLDataChannel): UInt = {\n x match {\n case a: TLBundleA => a.size\n case b: TLBundleB => b.size\n case c: TLBundleC => c.size\n case d: TLBundleD => d.size\n }\n }\n\n def data(x: TLDataChannel): UInt = {\n x match {\n case a: TLBundleA => a.data\n case b: TLBundleB => b.data\n case c: TLBundleC => c.data\n case d: TLBundleD => d.data\n }\n }\n\n def corrupt(x: TLDataChannel): Bool = {\n x match {\n case a: TLBundleA => a.corrupt\n case b: TLBundleB => b.corrupt\n case c: TLBundleC => c.corrupt\n case d: TLBundleD => d.corrupt\n }\n }\n\n def mask(x: TLAddrChannel): UInt = {\n x match {\n case a: TLBundleA => a.mask\n case b: TLBundleB => b.mask\n case c: TLBundleC => mask(c.address, c.size)\n }\n }\n\n def full_mask(x: TLAddrChannel): UInt = {\n x match {\n case a: TLBundleA => mask(a.address, a.size)\n case b: TLBundleB => mask(b.address, b.size)\n case c: TLBundleC => mask(c.address, c.size)\n }\n }\n\n def address(x: TLAddrChannel): UInt = {\n x match {\n case a: TLBundleA => a.address\n case b: TLBundleB => b.address\n case c: TLBundleC => c.address\n }\n }\n\n def source(x: TLDataChannel): UInt = {\n x match {\n case a: TLBundleA => a.source\n case b: TLBundleB => b.source\n case c: TLBundleC => c.source\n case d: TLBundleD => d.source\n }\n }\n\n def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)\n def addr_lo(x: UInt): UInt =\n if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)\n\n def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))\n def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))\n\n def numBeats(x: TLChannel): UInt = {\n x match {\n case _: TLBundleE => 1.U\n case bundle: TLDataChannel => {\n val hasData = this.hasData(bundle)\n val size = this.size(bundle)\n val cutoff = log2Ceil(manager.beatBytes)\n val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U\n val decode = UIntToOH(size, maxLgSize+1) >> cutoff\n Mux(hasData, decode | small.asUInt, 1.U)\n }\n }\n }\n\n def numBeats1(x: TLChannel): UInt = {\n x match {\n case _: TLBundleE => 0.U\n case bundle: TLDataChannel => {\n if (maxLgSize == 0) {\n 0.U\n } else {\n val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)\n Mux(hasData(bundle), decode, 0.U)\n }\n }\n }\n }\n\n def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {\n val beats1 = numBeats1(bits)\n val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))\n val counter1 = counter - 1.U\n val first = counter === 0.U\n val last = counter === 1.U || beats1 === 0.U\n val done = last && fire\n val count = (beats1 & ~counter1)\n when (fire) {\n counter := Mux(first, beats1, counter1)\n }\n (first, last, done, count)\n }\n\n def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1\n def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)\n def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)\n\n def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2\n def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)\n def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)\n\n def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3\n def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)\n def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)\n\n def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {\n val r = firstlastHelper(bits, fire)\n (r._1, r._2, r._3)\n }\n def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)\n def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)\n\n def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {\n val r = firstlastHelper(bits, fire)\n (r._1, r._2, r._3, r._4)\n }\n def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)\n def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)\n\n def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {\n val r = firstlastHelper(bits, fire)\n (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))\n }\n def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)\n def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)\n\n // Does the request need T permissions to be executed?\n def needT(a: TLBundleA): Bool = {\n val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(\n TLPermissions.NtoB -> false.B,\n TLPermissions.NtoT -> true.B,\n TLPermissions.BtoT -> true.B))\n MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(\n TLMessages.PutFullData -> true.B,\n TLMessages.PutPartialData -> true.B,\n TLMessages.ArithmeticData -> true.B,\n TLMessages.LogicalData -> true.B,\n TLMessages.Get -> false.B,\n TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(\n TLHints.PREFETCH_READ -> false.B,\n TLHints.PREFETCH_WRITE -> true.B)),\n TLMessages.AcquireBlock -> acq_needT,\n TLMessages.AcquirePerm -> acq_needT))\n }\n\n // This is a very expensive circuit; use only if you really mean it!\n def inFlight(x: TLBundle): (UInt, UInt) = {\n val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))\n val bce = manager.anySupportAcquireB && client.anySupportProbe\n\n val (a_first, a_last, _) = firstlast(x.a)\n val (b_first, b_last, _) = firstlast(x.b)\n val (c_first, c_last, _) = firstlast(x.c)\n val (d_first, d_last, _) = firstlast(x.d)\n val (e_first, e_last, _) = firstlast(x.e)\n\n val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))\n val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))\n val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))\n val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))\n val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))\n\n val a_inc = x.a.fire && a_first && a_request\n val b_inc = x.b.fire && b_first && b_request\n val c_inc = x.c.fire && c_first && c_request\n val d_inc = x.d.fire && d_first && d_request\n val e_inc = x.e.fire && e_first && e_request\n val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))\n\n val a_dec = x.a.fire && a_last && a_response\n val b_dec = x.b.fire && b_last && b_response\n val c_dec = x.c.fire && c_last && c_response\n val d_dec = x.d.fire && d_last && d_response\n val e_dec = x.e.fire && e_last && e_response\n val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))\n\n val next_flight = flight + PopCount(inc) - PopCount(dec)\n flight := next_flight\n\n (flight, next_flight)\n }\n\n def prettySourceMapping(context: String): String = {\n s\"TL-Source mapping for $context:\\n${(new TLSourceIdMap(client)).pretty}\\n\"\n }\n}\n\nclass TLEdgeOut(\n client: TLClientPortParameters,\n manager: TLManagerPortParameters,\n params: Parameters,\n sourceInfo: SourceInfo)\n extends TLEdge(client, manager, params, sourceInfo)\n{\n // Transfers\n def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {\n require (manager.anySupportAcquireB, s\"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsAcquireBFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.AcquireBlock\n a.param := growPermissions\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := DontCare\n a.corrupt := false.B\n (legal, a)\n }\n\n def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {\n require (manager.anySupportAcquireB, s\"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsAcquireBFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.AcquirePerm\n a.param := growPermissions\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := DontCare\n a.corrupt := false.B\n (legal, a)\n }\n\n def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {\n require (manager.anySupportAcquireB, s\"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsAcquireBFast(toAddress, lgSize)\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.Release\n c.param := shrinkPermissions\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := DontCare\n c.corrupt := false.B\n (legal, c)\n }\n\n def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {\n require (manager.anySupportAcquireB, s\"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsAcquireBFast(toAddress, lgSize)\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.ReleaseData\n c.param := shrinkPermissions\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := data\n c.corrupt := corrupt\n (legal, c)\n }\n\n def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =\n Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)\n\n def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =\n ProbeAck(b.source, b.address, b.size, reportPermissions)\n\n def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.ProbeAck\n c.param := reportPermissions\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := DontCare\n c.corrupt := false.B\n c\n }\n\n def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =\n ProbeAck(b.source, b.address, b.size, reportPermissions, data)\n\n def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.ProbeAckData\n c.param := reportPermissions\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := data\n c.corrupt := corrupt\n c\n }\n\n def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =\n ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)\n\n def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)\n def GrantAck(toSink: UInt): TLBundleE = {\n val e = Wire(new TLBundleE(bundle))\n e.sink := toSink\n e\n }\n\n // Accesses\n def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {\n require (manager.anySupportGet, s\"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsGetFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.Get\n a.param := 0.U\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := DontCare\n a.corrupt := false.B\n (legal, a)\n }\n\n def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =\n Put(fromSource, toAddress, lgSize, data, false.B)\n\n def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {\n require (manager.anySupportPutFull, s\"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsPutFullFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.PutFullData\n a.param := 0.U\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := data\n a.corrupt := corrupt\n (legal, a)\n }\n\n def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =\n Put(fromSource, toAddress, lgSize, data, mask, false.B)\n\n def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {\n require (manager.anySupportPutPartial, s\"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsPutPartialFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.PutPartialData\n a.param := 0.U\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask\n a.data := data\n a.corrupt := corrupt\n (legal, a)\n }\n\n def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {\n require (manager.anySupportArithmetic, s\"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsArithmeticFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.ArithmeticData\n a.param := atomic\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := data\n a.corrupt := corrupt\n (legal, a)\n }\n\n def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {\n require (manager.anySupportLogical, s\"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsLogicalFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.LogicalData\n a.param := atomic\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := data\n a.corrupt := corrupt\n (legal, a)\n }\n\n def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {\n require (manager.anySupportHint, s\"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsHintFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.Hint\n a.param := param\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := DontCare\n a.corrupt := false.B\n (legal, a)\n }\n\n def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)\n def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.AccessAck\n c.param := 0.U\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := DontCare\n c.corrupt := false.B\n c\n }\n\n def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)\n def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)\n def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)\n def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.AccessAckData\n c.param := 0.U\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := data\n c.corrupt := corrupt\n c\n }\n\n def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)\n def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.HintAck\n c.param := 0.U\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := DontCare\n c.corrupt := false.B\n c\n }\n}\n\nclass TLEdgeIn(\n client: TLClientPortParameters,\n manager: TLManagerPortParameters,\n params: Parameters,\n sourceInfo: SourceInfo)\n extends TLEdge(client, manager, params, sourceInfo)\n{\n private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {\n val todo = x.filter(!_.isEmpty)\n val heads = todo.map(_.head)\n val tails = todo.map(_.tail)\n if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }\n }\n\n // Transfers\n def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {\n require (client.anySupportProbe, s\"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}\")\n val legal = client.supportsProbe(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.Probe\n b.param := capPermissions\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask(fromAddress, lgSize)\n b.data := DontCare\n b.corrupt := false.B\n (legal, b)\n }\n\n def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)\n def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {\n val d = Wire(new TLBundleD(bundle))\n d.opcode := TLMessages.Grant\n d.param := capPermissions\n d.size := lgSize\n d.source := toSource\n d.sink := fromSink\n d.denied := denied\n d.user := DontCare\n d.echo := DontCare\n d.data := DontCare\n d.corrupt := false.B\n d\n }\n\n def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)\n def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {\n val d = Wire(new TLBundleD(bundle))\n d.opcode := TLMessages.GrantData\n d.param := capPermissions\n d.size := lgSize\n d.source := toSource\n d.sink := fromSink\n d.denied := denied\n d.user := DontCare\n d.echo := DontCare\n d.data := data\n d.corrupt := corrupt\n d\n }\n\n def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)\n def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {\n val d = Wire(new TLBundleD(bundle))\n d.opcode := TLMessages.ReleaseAck\n d.param := 0.U\n d.size := lgSize\n d.source := toSource\n d.sink := 0.U\n d.denied := denied\n d.user := DontCare\n d.echo := DontCare\n d.data := DontCare\n d.corrupt := false.B\n d\n }\n\n // Accesses\n def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {\n require (client.anySupportGet, s\"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}\")\n val legal = client.supportsGet(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.Get\n b.param := 0.U\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask(fromAddress, lgSize)\n b.data := DontCare\n b.corrupt := false.B\n (legal, b)\n }\n\n def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =\n Put(fromAddress, toSource, lgSize, data, false.B)\n\n def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {\n require (client.anySupportPutFull, s\"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}\")\n val legal = client.supportsPutFull(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.PutFullData\n b.param := 0.U\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask(fromAddress, lgSize)\n b.data := data\n b.corrupt := corrupt\n (legal, b)\n }\n\n def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =\n Put(fromAddress, toSource, lgSize, data, mask, false.B)\n\n def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {\n require (client.anySupportPutPartial, s\"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}\")\n val legal = client.supportsPutPartial(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.PutPartialData\n b.param := 0.U\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask\n b.data := data\n b.corrupt := corrupt\n (legal, b)\n }\n\n def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {\n require (client.anySupportArithmetic, s\"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}\")\n val legal = client.supportsArithmetic(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.ArithmeticData\n b.param := atomic\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask(fromAddress, lgSize)\n b.data := data\n b.corrupt := corrupt\n (legal, b)\n }\n\n def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {\n require (client.anySupportLogical, s\"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}\")\n val legal = client.supportsLogical(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.LogicalData\n b.param := atomic\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask(fromAddress, lgSize)\n b.data := data\n b.corrupt := corrupt\n (legal, b)\n }\n\n def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {\n require (client.anySupportHint, s\"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}\")\n val legal = client.supportsHint(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.Hint\n b.param := param\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask(fromAddress, lgSize)\n b.data := DontCare\n b.corrupt := false.B\n (legal, b)\n }\n\n def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)\n def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)\n def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)\n def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {\n val d = Wire(new TLBundleD(bundle))\n d.opcode := TLMessages.AccessAck\n d.param := 0.U\n d.size := lgSize\n d.source := toSource\n d.sink := 0.U\n d.denied := denied\n d.user := DontCare\n d.echo := DontCare\n d.data := DontCare\n d.corrupt := false.B\n d\n }\n\n def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)\n def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)\n def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)\n def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {\n val d = Wire(new TLBundleD(bundle))\n d.opcode := TLMessages.AccessAckData\n d.param := 0.U\n d.size := lgSize\n d.source := toSource\n d.sink := 0.U\n d.denied := denied\n d.user := DontCare\n d.echo := DontCare\n d.data := data\n d.corrupt := corrupt\n d\n }\n\n def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)\n def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)\n def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)\n def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {\n val d = Wire(new TLBundleD(bundle))\n d.opcode := TLMessages.HintAck\n d.param := 0.U\n d.size := lgSize\n d.source := toSource\n d.sink := 0.U\n d.denied := denied\n d.user := DontCare\n d.echo := DontCare\n d.data := DontCare\n d.corrupt := false.B\n d\n }\n}\n"},"response":{"kind":"string","value":"module TLMonitor_22(\t// @[Monitor.scala:36:7]\n input clock,\t// @[Monitor.scala:36:7]\n input reset,\t// @[Monitor.scala:36:7]\n input io_in_a_ready,\t// @[Monitor.scala:20:14]\n input io_in_a_valid,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_a_bits_opcode,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_a_bits_param,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_a_bits_size,\t// @[Monitor.scala:20:14]\n input [6:0] io_in_a_bits_source,\t// @[Monitor.scala:20:14]\n input [25:0] io_in_a_bits_address,\t// @[Monitor.scala:20:14]\n input [7:0] io_in_a_bits_mask,\t// @[Monitor.scala:20:14]\n input [63:0] io_in_a_bits_data,\t// @[Monitor.scala:20:14]\n input io_in_a_bits_corrupt,\t// @[Monitor.scala:20:14]\n input io_in_d_ready,\t// @[Monitor.scala:20:14]\n input io_in_d_valid,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_d_bits_opcode,\t// @[Monitor.scala:20:14]\n input [1:0] io_in_d_bits_param,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_d_bits_size,\t// @[Monitor.scala:20:14]\n input [6:0] io_in_d_bits_source,\t// @[Monitor.scala:20:14]\n input io_in_d_bits_sink,\t// @[Monitor.scala:20:14]\n input io_in_d_bits_denied,\t// @[Monitor.scala:20:14]\n input [63:0] io_in_d_bits_data,\t// @[Monitor.scala:20:14]\n input io_in_d_bits_corrupt\t// @[Monitor.scala:20:14]\n);\n\n wire [31:0] _plusarg_reader_1_out;\t// @[PlusArg.scala:80:11]\n wire [31:0] _plusarg_reader_out;\t// @[PlusArg.scala:80:11]\n wire io_in_a_ready_0 = io_in_a_ready;\t// @[Monitor.scala:36:7]\n wire io_in_a_valid_0 = io_in_a_valid;\t// @[Monitor.scala:36:7]\n wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode;\t// @[Monitor.scala:36:7]\n wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param;\t// @[Monitor.scala:36:7]\n wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size;\t// @[Monitor.scala:36:7]\n wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source;\t// @[Monitor.scala:36:7]\n wire [25:0] io_in_a_bits_address_0 = io_in_a_bits_address;\t// @[Monitor.scala:36:7]\n wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask;\t// @[Monitor.scala:36:7]\n wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data;\t// @[Monitor.scala:36:7]\n wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt;\t// @[Monitor.scala:36:7]\n wire io_in_d_ready_0 = io_in_d_ready;\t// @[Monitor.scala:36:7]\n wire io_in_d_valid_0 = io_in_d_valid;\t// @[Monitor.scala:36:7]\n wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode;\t// @[Monitor.scala:36:7]\n wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param;\t// @[Monitor.scala:36:7]\n wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size;\t// @[Monitor.scala:36:7]\n wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source;\t// @[Monitor.scala:36:7]\n wire io_in_d_bits_sink_0 = io_in_d_bits_sink;\t// @[Monitor.scala:36:7]\n wire io_in_d_bits_denied_0 = io_in_d_bits_denied;\t// @[Monitor.scala:36:7]\n wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data;\t// @[Monitor.scala:36:7]\n wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt;\t// @[Monitor.scala:36:7]\n wire sink_ok = 1'h0;\t// @[Monitor.scala:309:31]\n wire _c_first_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_2_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_2_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_2_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_3_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_3_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_3_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_T = 1'h0;\t// @[Decoupled.scala:51:35]\n wire c_first_beats1_opdata = 1'h0;\t// @[Edges.scala:102:36]\n wire _c_first_last_T = 1'h0;\t// @[Edges.scala:232:25]\n wire c_first_done = 1'h0;\t// @[Edges.scala:233:22]\n wire _c_set_wo_ready_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_wo_ready_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_wo_ready_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_wo_ready_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_interm_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_interm_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_interm_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_interm_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_interm_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_interm_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_T = 1'h0;\t// @[Monitor.scala:772:47]\n wire _c_probe_ack_WIRE_2_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_2_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_3_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_3_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_T_1 = 1'h0;\t// @[Monitor.scala:772:95]\n wire c_probe_ack = 1'h0;\t// @[Monitor.scala:772:71]\n wire _same_cycle_resp_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_T_3 = 1'h0;\t// @[Monitor.scala:795:44]\n wire _same_cycle_resp_WIRE_2_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_2_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_3_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_3_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_T_4 = 1'h0;\t// @[Edges.scala:68:36]\n wire _same_cycle_resp_T_5 = 1'h0;\t// @[Edges.scala:68:51]\n wire _same_cycle_resp_T_6 = 1'h0;\t// @[Edges.scala:68:40]\n wire _same_cycle_resp_T_7 = 1'h0;\t// @[Monitor.scala:795:55]\n wire _same_cycle_resp_WIRE_4_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_4_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_5_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_5_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire same_cycle_resp_1 = 1'h0;\t// @[Monitor.scala:795:88]\n wire [2:0] responseMap_0 = 3'h0;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMap_1 = 3'h0;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMapSecondOption_0 = 3'h0;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMapSecondOption_1 = 3'h0;\t// @[Monitor.scala:644:42]\n wire [2:0] _c_first_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_first_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_first_WIRE_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_first_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_first_WIRE_1_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_first_WIRE_2_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_first_WIRE_2_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_first_WIRE_3_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_first_WIRE_3_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] c_first_beats1_decode = 3'h0;\t// @[Edges.scala:220:59]\n wire [2:0] c_first_beats1 = 3'h0;\t// @[Edges.scala:221:14]\n wire [2:0] _c_first_count_T = 3'h0;\t// @[Edges.scala:234:27]\n wire [2:0] c_first_count = 3'h0;\t// @[Edges.scala:234:25]\n wire [2:0] _c_first_counter_T = 3'h0;\t// @[Edges.scala:236:21]\n wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_set_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_set_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_set_WIRE_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_set_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_set_WIRE_1_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire _source_ok_T_3 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _source_ok_T_5 = 1'h1;\t// @[Parameters.scala:57:20]\n wire _source_ok_T_9 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _source_ok_T_11 = 1'h1;\t// @[Parameters.scala:57:20]\n wire _source_ok_T_15 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _source_ok_T_17 = 1'h1;\t// @[Parameters.scala:57:20]\n wire _source_ok_T_21 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _source_ok_T_23 = 1'h1;\t// @[Parameters.scala:57:20]\n wire _source_ok_T_39 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _source_ok_T_41 = 1'h1;\t// @[Parameters.scala:57:20]\n wire _source_ok_T_45 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _source_ok_T_47 = 1'h1;\t// @[Parameters.scala:57:20]\n wire _source_ok_T_51 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _source_ok_T_53 = 1'h1;\t// @[Parameters.scala:57:20]\n wire _source_ok_T_57 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _source_ok_T_59 = 1'h1;\t// @[Parameters.scala:57:20]\n wire c_first = 1'h1;\t// @[Edges.scala:231:25]\n wire _c_first_last_T_1 = 1'h1;\t// @[Edges.scala:232:43]\n wire c_first_last = 1'h1;\t// @[Edges.scala:232:33]\n wire [2:0] c_first_counter1 = 3'h7;\t// @[Edges.scala:230:28]\n wire [3:0] _c_first_counter1_T = 4'hF;\t// @[Edges.scala:230:28]\n wire [63:0] _c_first_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_first_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_first_WIRE_2_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_first_WIRE_3_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_set_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_set_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [25:0] _c_first_WIRE_bits_address = 26'h0;\t// @[Bundles.scala:265:74]\n wire [25:0] _c_first_WIRE_1_bits_address = 26'h0;\t// @[Bundles.scala:265:61]\n wire [25:0] _c_first_WIRE_2_bits_address = 26'h0;\t// @[Bundles.scala:265:74]\n wire [25:0] _c_first_WIRE_3_bits_address = 26'h0;\t// @[Bundles.scala:265:61]\n wire [25:0] _c_set_wo_ready_WIRE_bits_address = 26'h0;\t// @[Bundles.scala:265:74]\n wire [25:0] _c_set_wo_ready_WIRE_1_bits_address = 26'h0;\t// @[Bundles.scala:265:61]\n wire [25:0] _c_set_WIRE_bits_address = 26'h0;\t// @[Bundles.scala:265:74]\n wire [25:0] _c_set_WIRE_1_bits_address = 26'h0;\t// @[Bundles.scala:265:61]\n wire [25:0] _c_opcodes_set_interm_WIRE_bits_address = 26'h0;\t// @[Bundles.scala:265:74]\n wire [25:0] _c_opcodes_set_interm_WIRE_1_bits_address = 26'h0;\t// @[Bundles.scala:265:61]\n wire [25:0] _c_sizes_set_interm_WIRE_bits_address = 26'h0;\t// @[Bundles.scala:265:74]\n wire [25:0] _c_sizes_set_interm_WIRE_1_bits_address = 26'h0;\t// @[Bundles.scala:265:61]\n wire [25:0] _c_opcodes_set_WIRE_bits_address = 26'h0;\t// @[Bundles.scala:265:74]\n wire [25:0] _c_opcodes_set_WIRE_1_bits_address = 26'h0;\t// @[Bundles.scala:265:61]\n wire [25:0] _c_sizes_set_WIRE_bits_address = 26'h0;\t// @[Bundles.scala:265:74]\n wire [25:0] _c_sizes_set_WIRE_1_bits_address = 26'h0;\t// @[Bundles.scala:265:61]\n wire [25:0] _c_probe_ack_WIRE_bits_address = 26'h0;\t// @[Bundles.scala:265:74]\n wire [25:0] _c_probe_ack_WIRE_1_bits_address = 26'h0;\t// @[Bundles.scala:265:61]\n wire [25:0] _c_probe_ack_WIRE_2_bits_address = 26'h0;\t// @[Bundles.scala:265:74]\n wire [25:0] _c_probe_ack_WIRE_3_bits_address = 26'h0;\t// @[Bundles.scala:265:61]\n wire [25:0] _same_cycle_resp_WIRE_bits_address = 26'h0;\t// @[Bundles.scala:265:74]\n wire [25:0] _same_cycle_resp_WIRE_1_bits_address = 26'h0;\t// @[Bundles.scala:265:61]\n wire [25:0] _same_cycle_resp_WIRE_2_bits_address = 26'h0;\t// @[Bundles.scala:265:74]\n wire [25:0] _same_cycle_resp_WIRE_3_bits_address = 26'h0;\t// @[Bundles.scala:265:61]\n wire [25:0] _same_cycle_resp_WIRE_4_bits_address = 26'h0;\t// @[Bundles.scala:265:74]\n wire [25:0] _same_cycle_resp_WIRE_5_bits_address = 26'h0;\t// @[Bundles.scala:265:61]\n wire [6:0] _c_first_WIRE_bits_source = 7'h0;\t// @[Bundles.scala:265:74]\n wire [6:0] _c_first_WIRE_1_bits_source = 7'h0;\t// @[Bundles.scala:265:61]\n wire [6:0] _c_first_WIRE_2_bits_source = 7'h0;\t// @[Bundles.scala:265:74]\n wire [6:0] _c_first_WIRE_3_bits_source = 7'h0;\t// @[Bundles.scala:265:61]\n wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0;\t// @[Bundles.scala:265:74]\n wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0;\t// @[Bundles.scala:265:61]\n wire [6:0] _c_set_WIRE_bits_source = 7'h0;\t// @[Bundles.scala:265:74]\n wire [6:0] _c_set_WIRE_1_bits_source = 7'h0;\t// @[Bundles.scala:265:61]\n wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0;\t// @[Bundles.scala:265:74]\n wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0;\t// @[Bundles.scala:265:61]\n wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0;\t// @[Bundles.scala:265:74]\n wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0;\t// @[Bundles.scala:265:61]\n wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0;\t// @[Bundles.scala:265:74]\n wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0;\t// @[Bundles.scala:265:61]\n wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0;\t// @[Bundles.scala:265:74]\n wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0;\t// @[Bundles.scala:265:61]\n wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0;\t// @[Bundles.scala:265:74]\n wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0;\t// @[Bundles.scala:265:61]\n wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0;\t// @[Bundles.scala:265:74]\n wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0;\t// @[Bundles.scala:265:61]\n wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0;\t// @[Bundles.scala:265:74]\n wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0;\t// @[Bundles.scala:265:61]\n wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0;\t// @[Bundles.scala:265:74]\n wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0;\t// @[Bundles.scala:265:61]\n wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0;\t// @[Bundles.scala:265:74]\n wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0;\t// @[Bundles.scala:265:61]\n wire [15:0] _a_opcode_lookup_T_5 = 16'hF;\t// @[Monitor.scala:612:57]\n wire [15:0] _a_size_lookup_T_5 = 16'hF;\t// @[Monitor.scala:612:57]\n wire [15:0] _d_opcodes_clr_T_3 = 16'hF;\t// @[Monitor.scala:612:57]\n wire [15:0] _d_sizes_clr_T_3 = 16'hF;\t// @[Monitor.scala:612:57]\n wire [15:0] _c_opcode_lookup_T_5 = 16'hF;\t// @[Monitor.scala:724:57]\n wire [15:0] _c_size_lookup_T_5 = 16'hF;\t// @[Monitor.scala:724:57]\n wire [15:0] _d_opcodes_clr_T_9 = 16'hF;\t// @[Monitor.scala:724:57]\n wire [15:0] _d_sizes_clr_T_9 = 16'hF;\t// @[Monitor.scala:724:57]\n wire [16:0] _a_opcode_lookup_T_4 = 17'hF;\t// @[Monitor.scala:612:57]\n wire [16:0] _a_size_lookup_T_4 = 17'hF;\t// @[Monitor.scala:612:57]\n wire [16:0] _d_opcodes_clr_T_2 = 17'hF;\t// @[Monitor.scala:612:57]\n wire [16:0] _d_sizes_clr_T_2 = 17'hF;\t// @[Monitor.scala:612:57]\n wire [16:0] _c_opcode_lookup_T_4 = 17'hF;\t// @[Monitor.scala:724:57]\n wire [16:0] _c_size_lookup_T_4 = 17'hF;\t// @[Monitor.scala:724:57]\n wire [16:0] _d_opcodes_clr_T_8 = 17'hF;\t// @[Monitor.scala:724:57]\n wire [16:0] _d_sizes_clr_T_8 = 17'hF;\t// @[Monitor.scala:724:57]\n wire [15:0] _a_opcode_lookup_T_3 = 16'h10;\t// @[Monitor.scala:612:51]\n wire [15:0] _a_size_lookup_T_3 = 16'h10;\t// @[Monitor.scala:612:51]\n wire [15:0] _d_opcodes_clr_T_1 = 16'h10;\t// @[Monitor.scala:612:51]\n wire [15:0] _d_sizes_clr_T_1 = 16'h10;\t// @[Monitor.scala:612:51]\n wire [15:0] _c_opcode_lookup_T_3 = 16'h10;\t// @[Monitor.scala:724:51]\n wire [15:0] _c_size_lookup_T_3 = 16'h10;\t// @[Monitor.scala:724:51]\n wire [15:0] _d_opcodes_clr_T_7 = 16'h10;\t// @[Monitor.scala:724:51]\n wire [15:0] _d_sizes_clr_T_7 = 16'h10;\t// @[Monitor.scala:724:51]\n wire [1026:0] _c_opcodes_set_T_1 = 1027'h0;\t// @[Monitor.scala:767:54]\n wire [1026:0] _c_sizes_set_T_1 = 1027'h0;\t// @[Monitor.scala:768:52]\n wire [9:0] _c_opcodes_set_T = 10'h0;\t// @[Monitor.scala:767:79]\n wire [9:0] _c_sizes_set_T = 10'h0;\t// @[Monitor.scala:768:77]\n wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1;\t// @[Monitor.scala:765:61]\n wire [3:0] _c_sizes_set_interm_T_1 = 4'h1;\t// @[Monitor.scala:766:59]\n wire [3:0] c_opcodes_set_interm = 4'h0;\t// @[Monitor.scala:754:40]\n wire [3:0] c_sizes_set_interm = 4'h0;\t// @[Monitor.scala:755:40]\n wire [3:0] _c_opcodes_set_interm_T = 4'h0;\t// @[Monitor.scala:765:53]\n wire [3:0] _c_sizes_set_interm_T = 4'h0;\t// @[Monitor.scala:766:51]\n wire [127:0] _c_set_wo_ready_T = 128'h1;\t// @[OneHot.scala:58:35]\n wire [127:0] _c_set_T = 128'h1;\t// @[OneHot.scala:58:35]\n wire [259:0] c_opcodes_set = 260'h0;\t// @[Monitor.scala:740:34]\n wire [259:0] c_sizes_set = 260'h0;\t// @[Monitor.scala:741:34]\n wire [64:0] c_set = 65'h0;\t// @[Monitor.scala:738:34]\n wire [64:0] c_set_wo_ready = 65'h0;\t// @[Monitor.scala:739:34]\n wire [5:0] _c_first_beats1_decode_T_2 = 6'h0;\t// @[package.scala:243:46]\n wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F;\t// @[package.scala:243:76]\n wire [12:0] _c_first_beats1_decode_T = 13'h3F;\t// @[package.scala:243:71]\n wire [2:0] responseMap_6 = 3'h4;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMap_7 = 3'h4;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMapSecondOption_7 = 3'h4;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMapSecondOption_6 = 3'h5;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMap_5 = 3'h2;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMapSecondOption_5 = 3'h2;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMap_2 = 3'h1;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMap_3 = 3'h1;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMap_4 = 3'h1;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMapSecondOption_2 = 3'h1;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMapSecondOption_3 = 3'h1;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMapSecondOption_4 = 3'h1;\t// @[Monitor.scala:644:42]\n wire [3:0] _a_opcode_lookup_T_2 = 4'h4;\t// @[Monitor.scala:637:123]\n wire [3:0] _a_size_lookup_T_2 = 4'h4;\t// @[Monitor.scala:641:117]\n wire [3:0] _d_opcodes_clr_T = 4'h4;\t// @[Monitor.scala:680:48]\n wire [3:0] _d_sizes_clr_T = 4'h4;\t// @[Monitor.scala:681:48]\n wire [3:0] _c_opcode_lookup_T_2 = 4'h4;\t// @[Monitor.scala:749:123]\n wire [3:0] _c_size_lookup_T_2 = 4'h4;\t// @[Monitor.scala:750:119]\n wire [3:0] _d_opcodes_clr_T_6 = 4'h4;\t// @[Monitor.scala:790:48]\n wire [3:0] _d_sizes_clr_T_6 = 4'h4;\t// @[Monitor.scala:791:48]\n wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0;\t// @[Misc.scala:202:34]\n wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [6:0] _uncommonBits_T = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [6:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0;\t// @[Monitor.scala:36:7]\n wire _source_ok_T = io_in_a_bits_source_0 == 7'h10;\t// @[Monitor.scala:36:7]\n wire _source_ok_WIRE_0 = _source_ok_T;\t// @[Parameters.scala:1138:31]\n wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2];\t// @[Monitor.scala:36:7]\n wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2];\t// @[Monitor.scala:36:7]\n wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2];\t// @[Monitor.scala:36:7]\n wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2];\t// @[Monitor.scala:36:7]\n wire _source_ok_T_2 = _source_ok_T_1 == 5'h0;\t// @[Parameters.scala:54:{10,32}]\n wire _source_ok_T_4 = _source_ok_T_2;\t// @[Parameters.scala:54:{32,67}]\n wire _source_ok_T_6 = _source_ok_T_4;\t// @[Parameters.scala:54:67, :56:48]\n wire _source_ok_WIRE_1 = _source_ok_T_6;\t// @[Parameters.scala:1138:31]\n wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire _source_ok_T_8 = _source_ok_T_7 == 5'h1;\t// @[Parameters.scala:54:{10,32}]\n wire _source_ok_T_10 = _source_ok_T_8;\t// @[Parameters.scala:54:{32,67}]\n wire _source_ok_T_12 = _source_ok_T_10;\t// @[Parameters.scala:54:67, :56:48]\n wire _source_ok_WIRE_2 = _source_ok_T_12;\t// @[Parameters.scala:1138:31]\n wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire _source_ok_T_14 = _source_ok_T_13 == 5'h2;\t// @[Parameters.scala:54:{10,32}]\n wire _source_ok_T_16 = _source_ok_T_14;\t// @[Parameters.scala:54:{32,67}]\n wire _source_ok_T_18 = _source_ok_T_16;\t// @[Parameters.scala:54:67, :56:48]\n wire _source_ok_WIRE_3 = _source_ok_T_18;\t// @[Parameters.scala:1138:31]\n wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire _source_ok_T_20 = _source_ok_T_19 == 5'h3;\t// @[Parameters.scala:54:{10,32}]\n wire _source_ok_T_22 = _source_ok_T_20;\t// @[Parameters.scala:54:{32,67}]\n wire _source_ok_T_24 = _source_ok_T_22;\t// @[Parameters.scala:54:67, :56:48]\n wire _source_ok_WIRE_4 = _source_ok_T_24;\t// @[Parameters.scala:1138:31]\n wire _source_ok_T_25 = io_in_a_bits_source_0 == 7'h20;\t// @[Monitor.scala:36:7]\n wire _source_ok_WIRE_5 = _source_ok_T_25;\t// @[Parameters.scala:1138:31]\n wire _source_ok_T_26 = io_in_a_bits_source_0 == 7'h21;\t// @[Monitor.scala:36:7]\n wire _source_ok_WIRE_6 = _source_ok_T_26;\t// @[Parameters.scala:1138:31]\n wire _source_ok_T_27 = io_in_a_bits_source_0 == 7'h22;\t// @[Monitor.scala:36:7]\n wire _source_ok_WIRE_7 = _source_ok_T_27;\t// @[Parameters.scala:1138:31]\n wire _source_ok_T_28 = io_in_a_bits_source_0 == 7'h40;\t// @[Monitor.scala:36:7]\n wire _source_ok_WIRE_8 = _source_ok_T_28;\t// @[Parameters.scala:1138:31]\n wire _source_ok_T_29 = _source_ok_WIRE_0 | _source_ok_WIRE_1;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _source_ok_T_30 = _source_ok_T_29 | _source_ok_WIRE_2;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _source_ok_T_31 = _source_ok_T_30 | _source_ok_WIRE_3;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _source_ok_T_32 = _source_ok_T_31 | _source_ok_WIRE_4;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _source_ok_T_33 = _source_ok_T_32 | _source_ok_WIRE_5;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _source_ok_T_34 = _source_ok_T_33 | _source_ok_WIRE_6;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _source_ok_T_35 = _source_ok_T_34 | _source_ok_WIRE_7;\t// @[Parameters.scala:1138:31, :1139:46]\n wire source_ok = _source_ok_T_35 | _source_ok_WIRE_8;\t// @[Parameters.scala:1138:31, :1139:46]\n wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0;\t// @[package.scala:243:71]\n wire [12:0] _is_aligned_mask_T;\t// @[package.scala:243:71]\n assign _is_aligned_mask_T = _GEN;\t// @[package.scala:243:71]\n wire [12:0] _a_first_beats1_decode_T;\t// @[package.scala:243:71]\n assign _a_first_beats1_decode_T = _GEN;\t// @[package.scala:243:71]\n wire [12:0] _a_first_beats1_decode_T_3;\t// @[package.scala:243:71]\n assign _a_first_beats1_decode_T_3 = _GEN;\t// @[package.scala:243:71]\n wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0];\t// @[package.scala:243:{71,76}]\n wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1;\t// @[package.scala:243:{46,76}]\n wire [25:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask};\t// @[package.scala:243:46]\n wire is_aligned = _is_aligned_T == 26'h0;\t// @[Edges.scala:21:{16,24}]\n wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0];\t// @[OneHot.scala:64:49]\n wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount;\t// @[OneHot.scala:64:49, :65:12]\n wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0];\t// @[OneHot.scala:65:{12,27}]\n wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1};\t// @[OneHot.scala:65:27]\n wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2;\t// @[Misc.scala:206:21]\n wire mask_sub_sub_size = mask_sizeOH[2];\t// @[Misc.scala:202:81, :209:26]\n wire mask_sub_sub_bit = io_in_a_bits_address_0[2];\t// @[Misc.scala:210:26]\n wire mask_sub_sub_1_2 = mask_sub_sub_bit;\t// @[Misc.scala:210:26, :214:27]\n wire mask_sub_sub_nbit = ~mask_sub_sub_bit;\t// @[Misc.scala:210:26, :211:20]\n wire mask_sub_sub_0_2 = mask_sub_sub_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T;\t// @[Misc.scala:206:21, :215:{29,38}]\n wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1;\t// @[Misc.scala:206:21, :215:{29,38}]\n wire mask_sub_size = mask_sizeOH[1];\t// @[Misc.scala:202:81, :209:26]\n wire mask_sub_bit = io_in_a_bits_address_0[1];\t// @[Misc.scala:210:26]\n wire mask_sub_nbit = ~mask_sub_bit;\t// @[Misc.scala:210:26, :211:20]\n wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T;\t// @[Misc.scala:215:{29,38}]\n wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1;\t// @[Misc.scala:215:{29,38}]\n wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2;\t// @[Misc.scala:215:{29,38}]\n wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3;\t// @[Misc.scala:215:{29,38}]\n wire mask_size = mask_sizeOH[0];\t// @[Misc.scala:202:81, :209:26]\n wire mask_bit = io_in_a_bits_address_0[0];\t// @[Misc.scala:210:26]\n wire mask_nbit = ~mask_bit;\t// @[Misc.scala:210:26, :211:20]\n wire mask_eq = mask_sub_0_2 & mask_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_acc_T = mask_size & mask_eq;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc = mask_sub_0_1 | _mask_acc_T;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_1 = mask_sub_0_2 & mask_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_acc_T_1 = mask_size & mask_eq_1;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_2 = mask_sub_1_2 & mask_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_acc_T_2 = mask_size & mask_eq_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_3 = mask_sub_1_2 & mask_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_acc_T_3 = mask_size & mask_eq_3;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_4 = mask_sub_2_2 & mask_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_acc_T_4 = mask_size & mask_eq_4;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_5 = mask_sub_2_2 & mask_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_acc_T_5 = mask_size & mask_eq_5;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_6 = mask_sub_3_2 & mask_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_acc_T_6 = mask_size & mask_eq_6;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_7 = mask_sub_3_2 & mask_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_acc_T_7 = mask_size & mask_eq_7;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7;\t// @[Misc.scala:215:{29,38}]\n wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc};\t// @[Misc.scala:215:29, :222:10]\n wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2};\t// @[Misc.scala:215:29, :222:10]\n wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo};\t// @[Misc.scala:222:10]\n wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4};\t// @[Misc.scala:215:29, :222:10]\n wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6};\t// @[Misc.scala:215:29, :222:10]\n wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo};\t// @[Misc.scala:222:10]\n wire [7:0] mask = {mask_hi, mask_lo};\t// @[Misc.scala:222:10]\n wire [1:0] uncommonBits = _uncommonBits_T[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire _source_ok_T_36 = io_in_d_bits_source_0 == 7'h10;\t// @[Monitor.scala:36:7]\n wire _source_ok_WIRE_1_0 = _source_ok_T_36;\t// @[Parameters.scala:1138:31]\n wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] _source_ok_T_37 = io_in_d_bits_source_0[6:2];\t// @[Monitor.scala:36:7]\n wire [4:0] _source_ok_T_43 = io_in_d_bits_source_0[6:2];\t// @[Monitor.scala:36:7]\n wire [4:0] _source_ok_T_49 = io_in_d_bits_source_0[6:2];\t// @[Monitor.scala:36:7]\n wire [4:0] _source_ok_T_55 = io_in_d_bits_source_0[6:2];\t// @[Monitor.scala:36:7]\n wire _source_ok_T_38 = _source_ok_T_37 == 5'h0;\t// @[Parameters.scala:54:{10,32}]\n wire _source_ok_T_40 = _source_ok_T_38;\t// @[Parameters.scala:54:{32,67}]\n wire _source_ok_T_42 = _source_ok_T_40;\t// @[Parameters.scala:54:67, :56:48]\n wire _source_ok_WIRE_1_1 = _source_ok_T_42;\t// @[Parameters.scala:1138:31]\n wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire _source_ok_T_44 = _source_ok_T_43 == 5'h1;\t// @[Parameters.scala:54:{10,32}]\n wire _source_ok_T_46 = _source_ok_T_44;\t// @[Parameters.scala:54:{32,67}]\n wire _source_ok_T_48 = _source_ok_T_46;\t// @[Parameters.scala:54:67, :56:48]\n wire _source_ok_WIRE_1_2 = _source_ok_T_48;\t// @[Parameters.scala:1138:31]\n wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire _source_ok_T_50 = _source_ok_T_49 == 5'h2;\t// @[Parameters.scala:54:{10,32}]\n wire _source_ok_T_52 = _source_ok_T_50;\t// @[Parameters.scala:54:{32,67}]\n wire _source_ok_T_54 = _source_ok_T_52;\t// @[Parameters.scala:54:67, :56:48]\n wire _source_ok_WIRE_1_3 = _source_ok_T_54;\t// @[Parameters.scala:1138:31]\n wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire _source_ok_T_56 = _source_ok_T_55 == 5'h3;\t// @[Parameters.scala:54:{10,32}]\n wire _source_ok_T_58 = _source_ok_T_56;\t// @[Parameters.scala:54:{32,67}]\n wire _source_ok_T_60 = _source_ok_T_58;\t// @[Parameters.scala:54:67, :56:48]\n wire _source_ok_WIRE_1_4 = _source_ok_T_60;\t// @[Parameters.scala:1138:31]\n wire _source_ok_T_61 = io_in_d_bits_source_0 == 7'h20;\t// @[Monitor.scala:36:7]\n wire _source_ok_WIRE_1_5 = _source_ok_T_61;\t// @[Parameters.scala:1138:31]\n wire _source_ok_T_62 = io_in_d_bits_source_0 == 7'h21;\t// @[Monitor.scala:36:7]\n wire _source_ok_WIRE_1_6 = _source_ok_T_62;\t// @[Parameters.scala:1138:31]\n wire _source_ok_T_63 = io_in_d_bits_source_0 == 7'h22;\t// @[Monitor.scala:36:7]\n wire _source_ok_WIRE_1_7 = _source_ok_T_63;\t// @[Parameters.scala:1138:31]\n wire _source_ok_T_64 = io_in_d_bits_source_0 == 7'h40;\t// @[Monitor.scala:36:7]\n wire _source_ok_WIRE_1_8 = _source_ok_T_64;\t// @[Parameters.scala:1138:31]\n wire _source_ok_T_65 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _source_ok_T_66 = _source_ok_T_65 | _source_ok_WIRE_1_2;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _source_ok_T_67 = _source_ok_T_66 | _source_ok_WIRE_1_3;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _source_ok_T_68 = _source_ok_T_67 | _source_ok_WIRE_1_4;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _source_ok_T_69 = _source_ok_T_68 | _source_ok_WIRE_1_5;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _source_ok_T_70 = _source_ok_T_69 | _source_ok_WIRE_1_6;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _source_ok_T_71 = _source_ok_T_70 | _source_ok_WIRE_1_7;\t// @[Parameters.scala:1138:31, :1139:46]\n wire source_ok_1 = _source_ok_T_71 | _source_ok_WIRE_1_8;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _T_1101 = io_in_a_ready_0 & io_in_a_valid_0;\t// @[Decoupled.scala:51:35]\n wire _a_first_T;\t// @[Decoupled.scala:51:35]\n assign _a_first_T = _T_1101;\t// @[Decoupled.scala:51:35]\n wire _a_first_T_1;\t// @[Decoupled.scala:51:35]\n assign _a_first_T_1 = _T_1101;\t// @[Decoupled.scala:51:35]\n wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0];\t// @[package.scala:243:{71,76}]\n wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1;\t// @[package.scala:243:{46,76}]\n wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3];\t// @[package.scala:243:46]\n wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2];\t// @[Monitor.scala:36:7]\n wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2];\t// @[Monitor.scala:36:7]\n wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T;\t// @[Edges.scala:92:{28,37}]\n wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0;\t// @[Edges.scala:92:28, :220:59, :221:14]\n reg [2:0] a_first_counter;\t// @[Edges.scala:229:27]\n wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1;\t// @[Edges.scala:229:27, :230:28]\n wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0];\t// @[Edges.scala:230:28]\n wire a_first = a_first_counter == 3'h0;\t// @[Edges.scala:229:27, :231:25]\n wire _a_first_last_T = a_first_counter == 3'h1;\t// @[Edges.scala:229:27, :232:25]\n wire _a_first_last_T_1 = a_first_beats1 == 3'h0;\t// @[Edges.scala:221:14, :232:43]\n wire a_first_last = _a_first_last_T | _a_first_last_T_1;\t// @[Edges.scala:232:{25,33,43}]\n wire a_first_done = a_first_last & _a_first_T;\t// @[Decoupled.scala:51:35]\n wire [2:0] _a_first_count_T = ~a_first_counter1;\t// @[Edges.scala:230:28, :234:27]\n wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T;\t// @[Edges.scala:221:14, :234:{25,27}]\n wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1;\t// @[Edges.scala:221:14, :230:28, :231:25, :236:21]\n reg [2:0] opcode;\t// @[Monitor.scala:387:22]\n reg [2:0] param;\t// @[Monitor.scala:388:22]\n reg [2:0] size;\t// @[Monitor.scala:389:22]\n reg [6:0] source;\t// @[Monitor.scala:390:22]\n reg [25:0] address;\t// @[Monitor.scala:391:22]\n wire _T_1174 = io_in_d_ready_0 & io_in_d_valid_0;\t// @[Decoupled.scala:51:35]\n wire _d_first_T;\t// @[Decoupled.scala:51:35]\n assign _d_first_T = _T_1174;\t// @[Decoupled.scala:51:35]\n wire _d_first_T_1;\t// @[Decoupled.scala:51:35]\n assign _d_first_T_1 = _T_1174;\t// @[Decoupled.scala:51:35]\n wire _d_first_T_2;\t// @[Decoupled.scala:51:35]\n assign _d_first_T_2 = _T_1174;\t// @[Decoupled.scala:51:35]\n wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0;\t// @[package.scala:243:71]\n wire [12:0] _d_first_beats1_decode_T;\t// @[package.scala:243:71]\n assign _d_first_beats1_decode_T = _GEN_0;\t// @[package.scala:243:71]\n wire [12:0] _d_first_beats1_decode_T_3;\t// @[package.scala:243:71]\n assign _d_first_beats1_decode_T_3 = _GEN_0;\t// @[package.scala:243:71]\n wire [12:0] _d_first_beats1_decode_T_6;\t// @[package.scala:243:71]\n assign _d_first_beats1_decode_T_6 = _GEN_0;\t// @[package.scala:243:71]\n wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0];\t// @[package.scala:243:{71,76}]\n wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1;\t// @[package.scala:243:{46,76}]\n wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3];\t// @[package.scala:243:46]\n wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0];\t// @[Monitor.scala:36:7]\n wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0];\t// @[Monitor.scala:36:7]\n wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0];\t// @[Monitor.scala:36:7]\n wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0;\t// @[Edges.scala:106:36, :220:59, :221:14]\n reg [2:0] d_first_counter;\t// @[Edges.scala:229:27]\n wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1;\t// @[Edges.scala:229:27, :230:28]\n wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0];\t// @[Edges.scala:230:28]\n wire d_first = d_first_counter == 3'h0;\t// @[Edges.scala:229:27, :231:25]\n wire _d_first_last_T = d_first_counter == 3'h1;\t// @[Edges.scala:229:27, :232:25]\n wire _d_first_last_T_1 = d_first_beats1 == 3'h0;\t// @[Edges.scala:221:14, :232:43]\n wire d_first_last = _d_first_last_T | _d_first_last_T_1;\t// @[Edges.scala:232:{25,33,43}]\n wire d_first_done = d_first_last & _d_first_T;\t// @[Decoupled.scala:51:35]\n wire [2:0] _d_first_count_T = ~d_first_counter1;\t// @[Edges.scala:230:28, :234:27]\n wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T;\t// @[Edges.scala:221:14, :234:{25,27}]\n wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1;\t// @[Edges.scala:221:14, :230:28, :231:25, :236:21]\n reg [2:0] opcode_1;\t// @[Monitor.scala:538:22]\n reg [1:0] param_1;\t// @[Monitor.scala:539:22]\n reg [2:0] size_1;\t// @[Monitor.scala:540:22]\n reg [6:0] source_1;\t// @[Monitor.scala:541:22]\n reg sink;\t// @[Monitor.scala:542:22]\n reg denied;\t// @[Monitor.scala:543:22]\n reg [64:0] inflight;\t// @[Monitor.scala:614:27]\n reg [259:0] inflight_opcodes;\t// @[Monitor.scala:616:35]\n reg [259:0] inflight_sizes;\t// @[Monitor.scala:618:33]\n wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0];\t// @[package.scala:243:{71,76}]\n wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4;\t// @[package.scala:243:{46,76}]\n wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3];\t// @[package.scala:243:46]\n wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1;\t// @[Edges.scala:92:{28,37}]\n wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0;\t// @[Edges.scala:92:28, :220:59, :221:14]\n reg [2:0] a_first_counter_1;\t// @[Edges.scala:229:27]\n wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1;\t// @[Edges.scala:229:27, :230:28]\n wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0];\t// @[Edges.scala:230:28]\n wire a_first_1 = a_first_counter_1 == 3'h0;\t// @[Edges.scala:229:27, :231:25]\n wire _a_first_last_T_2 = a_first_counter_1 == 3'h1;\t// @[Edges.scala:229:27, :232:25]\n wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0;\t// @[Edges.scala:221:14, :232:43]\n wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3;\t// @[Edges.scala:232:{25,33,43}]\n wire a_first_done_1 = a_first_last_1 & _a_first_T_1;\t// @[Decoupled.scala:51:35]\n wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1;\t// @[Edges.scala:230:28, :234:27]\n wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1;\t// @[Edges.scala:221:14, :234:{25,27}]\n wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1;\t// @[Edges.scala:221:14, :230:28, :231:25, :236:21]\n wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0];\t// @[package.scala:243:{71,76}]\n wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4;\t// @[package.scala:243:{46,76}]\n wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3];\t// @[package.scala:243:46]\n wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0;\t// @[Edges.scala:106:36, :220:59, :221:14]\n reg [2:0] d_first_counter_1;\t// @[Edges.scala:229:27]\n wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1;\t// @[Edges.scala:229:27, :230:28]\n wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0];\t// @[Edges.scala:230:28]\n wire d_first_1 = d_first_counter_1 == 3'h0;\t// @[Edges.scala:229:27, :231:25]\n wire _d_first_last_T_2 = d_first_counter_1 == 3'h1;\t// @[Edges.scala:229:27, :232:25]\n wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0;\t// @[Edges.scala:221:14, :232:43]\n wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3;\t// @[Edges.scala:232:{25,33,43}]\n wire d_first_done_1 = d_first_last_1 & _d_first_T_1;\t// @[Decoupled.scala:51:35]\n wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1;\t// @[Edges.scala:230:28, :234:27]\n wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1;\t// @[Edges.scala:221:14, :234:{25,27}]\n wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1;\t// @[Edges.scala:221:14, :230:28, :231:25, :236:21]\n wire [64:0] a_set;\t// @[Monitor.scala:626:34]\n wire [64:0] a_set_wo_ready;\t// @[Monitor.scala:627:34]\n wire [259:0] a_opcodes_set;\t// @[Monitor.scala:630:33]\n wire [259:0] a_sizes_set;\t// @[Monitor.scala:632:31]\n wire [2:0] a_opcode_lookup;\t// @[Monitor.scala:635:35]\n wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0};\t// @[Monitor.scala:36:7, :637:69]\n wire [9:0] _a_opcode_lookup_T;\t// @[Monitor.scala:637:69]\n assign _a_opcode_lookup_T = _GEN_1;\t// @[Monitor.scala:637:69]\n wire [9:0] _a_size_lookup_T;\t// @[Monitor.scala:641:65]\n assign _a_size_lookup_T = _GEN_1;\t// @[Monitor.scala:637:69, :641:65]\n wire [9:0] _d_opcodes_clr_T_4;\t// @[Monitor.scala:680:101]\n assign _d_opcodes_clr_T_4 = _GEN_1;\t// @[Monitor.scala:637:69, :680:101]\n wire [9:0] _d_sizes_clr_T_4;\t// @[Monitor.scala:681:99]\n assign _d_sizes_clr_T_4 = _GEN_1;\t// @[Monitor.scala:637:69, :681:99]\n wire [9:0] _c_opcode_lookup_T;\t// @[Monitor.scala:749:69]\n assign _c_opcode_lookup_T = _GEN_1;\t// @[Monitor.scala:637:69, :749:69]\n wire [9:0] _c_size_lookup_T;\t// @[Monitor.scala:750:67]\n assign _c_size_lookup_T = _GEN_1;\t// @[Monitor.scala:637:69, :750:67]\n wire [9:0] _d_opcodes_clr_T_10;\t// @[Monitor.scala:790:101]\n assign _d_opcodes_clr_T_10 = _GEN_1;\t// @[Monitor.scala:637:69, :790:101]\n wire [9:0] _d_sizes_clr_T_10;\t// @[Monitor.scala:791:99]\n assign _d_sizes_clr_T_10 = _GEN_1;\t// @[Monitor.scala:637:69, :791:99]\n wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T;\t// @[Monitor.scala:616:35, :637:{44,69}]\n wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]};\t// @[Monitor.scala:637:{44,97}]\n wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]};\t// @[Monitor.scala:637:{97,152}]\n assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0];\t// @[Monitor.scala:635:35, :637:{21,152}]\n wire [3:0] a_size_lookup;\t// @[Monitor.scala:639:33]\n wire [259:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T;\t// @[Monitor.scala:618:33, :641:{40,65}]\n wire [259:0] _a_size_lookup_T_6 = {256'h0, _a_size_lookup_T_1[3:0]};\t// @[Monitor.scala:641:{40,91}]\n wire [259:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[259:1]};\t// @[Monitor.scala:641:{91,144}]\n assign a_size_lookup = _a_size_lookup_T_7[3:0];\t// @[Monitor.scala:639:33, :641:{19,144}]\n wire [3:0] a_opcodes_set_interm;\t// @[Monitor.scala:646:40]\n wire [3:0] a_sizes_set_interm;\t// @[Monitor.scala:648:38]\n wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1;\t// @[Monitor.scala:36:7, :651:26, :684:44]\n wire [127:0] _GEN_2 = 128'h1 << io_in_a_bits_source_0;\t// @[OneHot.scala:58:35]\n wire [127:0] _a_set_wo_ready_T;\t// @[OneHot.scala:58:35]\n assign _a_set_wo_ready_T = _GEN_2;\t// @[OneHot.scala:58:35]\n wire [127:0] _a_set_T;\t// @[OneHot.scala:58:35]\n assign _a_set_T = _GEN_2;\t// @[OneHot.scala:58:35]\n assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0;\t// @[OneHot.scala:58:35]\n wire _T_1027 = _T_1101 & a_first_1;\t// @[Decoupled.scala:51:35]\n assign a_set = _T_1027 ? _a_set_T[64:0] : 65'h0;\t// @[OneHot.scala:58:35]\n wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0};\t// @[Monitor.scala:36:7, :657:53]\n wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1};\t// @[Monitor.scala:657:{53,61}]\n assign a_opcodes_set_interm = _T_1027 ? _a_opcodes_set_interm_T_1 : 4'h0;\t// @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]\n wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0};\t// @[Monitor.scala:36:7, :658:51]\n wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1};\t// @[Monitor.scala:658:{51,59}]\n assign a_sizes_set_interm = _T_1027 ? _a_sizes_set_interm_T_1 : 4'h0;\t// @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]\n wire [9:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0};\t// @[Monitor.scala:36:7, :659:79]\n wire [9:0] _a_opcodes_set_T;\t// @[Monitor.scala:659:79]\n assign _a_opcodes_set_T = _GEN_3;\t// @[Monitor.scala:659:79]\n wire [9:0] _a_sizes_set_T;\t// @[Monitor.scala:660:77]\n assign _a_sizes_set_T = _GEN_3;\t// @[Monitor.scala:659:79, :660:77]\n wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T;\t// @[Monitor.scala:646:40, :659:{54,79}]\n assign a_opcodes_set = _T_1027 ? _a_opcodes_set_T_1[259:0] : 260'h0;\t// @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]\n wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T;\t// @[Monitor.scala:648:38, :659:54, :660:{52,77}]\n assign a_sizes_set = _T_1027 ? _a_sizes_set_T_1[259:0] : 260'h0;\t// @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]\n wire [64:0] d_clr;\t// @[Monitor.scala:664:34]\n wire [64:0] d_clr_wo_ready;\t// @[Monitor.scala:665:34]\n wire [259:0] d_opcodes_clr;\t// @[Monitor.scala:668:33]\n wire [259:0] d_sizes_clr;\t// @[Monitor.scala:670:31]\n wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6;\t// @[Monitor.scala:36:7, :673:46]\n wire d_release_ack;\t// @[Monitor.scala:673:46]\n assign d_release_ack = _GEN_4;\t// @[Monitor.scala:673:46]\n wire d_release_ack_1;\t// @[Monitor.scala:783:46]\n assign d_release_ack_1 = _GEN_4;\t// @[Monitor.scala:673:46, :783:46]\n wire _T_1073 = io_in_d_valid_0 & d_first_1;\t// @[Monitor.scala:36:7, :674:26]\n wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0;\t// @[OneHot.scala:58:35]\n wire [127:0] _d_clr_wo_ready_T;\t// @[OneHot.scala:58:35]\n assign _d_clr_wo_ready_T = _GEN_5;\t// @[OneHot.scala:58:35]\n wire [127:0] _d_clr_T;\t// @[OneHot.scala:58:35]\n assign _d_clr_T = _GEN_5;\t// @[OneHot.scala:58:35]\n wire [127:0] _d_clr_wo_ready_T_1;\t// @[OneHot.scala:58:35]\n assign _d_clr_wo_ready_T_1 = _GEN_5;\t// @[OneHot.scala:58:35]\n wire [127:0] _d_clr_T_1;\t// @[OneHot.scala:58:35]\n assign _d_clr_T_1 = _GEN_5;\t// @[OneHot.scala:58:35]\n assign d_clr_wo_ready = _T_1073 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0;\t// @[OneHot.scala:58:35]\n wire _T_1042 = _T_1174 & d_first_1 & ~d_release_ack;\t// @[Decoupled.scala:51:35]\n assign d_clr = _T_1042 ? _d_clr_T[64:0] : 65'h0;\t// @[OneHot.scala:58:35]\n wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4;\t// @[Monitor.scala:680:{76,101}]\n assign d_opcodes_clr = _T_1042 ? _d_opcodes_clr_T_5[259:0] : 260'h0;\t// @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]\n wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4;\t// @[Monitor.scala:681:{74,99}]\n assign d_sizes_clr = _T_1042 ? _d_sizes_clr_T_5[259:0] : 260'h0;\t// @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]\n wire _same_cycle_resp_T_1 = _same_cycle_resp_T;\t// @[Monitor.scala:684:{44,55}]\n wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0;\t// @[Monitor.scala:36:7, :684:113]\n wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2;\t// @[Monitor.scala:684:{55,88,113}]\n wire [64:0] _inflight_T = inflight | a_set;\t// @[Monitor.scala:614:27, :626:34, :705:27]\n wire [64:0] _inflight_T_1 = ~d_clr;\t// @[Monitor.scala:664:34, :705:38]\n wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1;\t// @[Monitor.scala:705:{27,36,38}]\n wire [259:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set;\t// @[Monitor.scala:616:35, :630:33, :706:43]\n wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr;\t// @[Monitor.scala:668:33, :706:62]\n wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1;\t// @[Monitor.scala:706:{43,60,62}]\n wire [259:0] _inflight_sizes_T = inflight_sizes | a_sizes_set;\t// @[Monitor.scala:618:33, :632:31, :707:39]\n wire [259:0] _inflight_sizes_T_1 = ~d_sizes_clr;\t// @[Monitor.scala:670:31, :707:56]\n wire [259:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1;\t// @[Monitor.scala:707:{39,54,56}]\n reg [31:0] watchdog;\t// @[Monitor.scala:709:27]\n wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1;\t// @[Monitor.scala:709:27, :714:26]\n wire [31:0] _watchdog_T_1 = _watchdog_T[31:0];\t// @[Monitor.scala:714:26]\n reg [64:0] inflight_1;\t// @[Monitor.scala:726:35]\n wire [64:0] _inflight_T_3 = inflight_1;\t// @[Monitor.scala:726:35, :814:35]\n reg [259:0] inflight_opcodes_1;\t// @[Monitor.scala:727:35]\n wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1;\t// @[Monitor.scala:727:35, :815:43]\n reg [259:0] inflight_sizes_1;\t// @[Monitor.scala:728:35]\n wire [259:0] _inflight_sizes_T_3 = inflight_sizes_1;\t// @[Monitor.scala:728:35, :816:41]\n wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0];\t// @[package.scala:243:{71,76}]\n wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7;\t// @[package.scala:243:{46,76}]\n wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3];\t// @[package.scala:243:46]\n wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0;\t// @[Edges.scala:106:36, :220:59, :221:14]\n reg [2:0] d_first_counter_2;\t// @[Edges.scala:229:27]\n wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1;\t// @[Edges.scala:229:27, :230:28]\n wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0];\t// @[Edges.scala:230:28]\n wire d_first_2 = d_first_counter_2 == 3'h0;\t// @[Edges.scala:229:27, :231:25]\n wire _d_first_last_T_4 = d_first_counter_2 == 3'h1;\t// @[Edges.scala:229:27, :232:25]\n wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0;\t// @[Edges.scala:221:14, :232:43]\n wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5;\t// @[Edges.scala:232:{25,33,43}]\n wire d_first_done_2 = d_first_last_2 & _d_first_T_2;\t// @[Decoupled.scala:51:35]\n wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2;\t// @[Edges.scala:230:28, :234:27]\n wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2;\t// @[Edges.scala:221:14, :234:{25,27}]\n wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2;\t// @[Edges.scala:221:14, :230:28, :231:25, :236:21]\n wire [3:0] c_opcode_lookup;\t// @[Monitor.scala:747:35]\n wire [3:0] c_size_lookup;\t// @[Monitor.scala:748:35]\n wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T;\t// @[Monitor.scala:727:35, :749:{44,69}]\n wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]};\t// @[Monitor.scala:749:{44,97}]\n wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]};\t// @[Monitor.scala:749:{97,152}]\n assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0];\t// @[Monitor.scala:747:35, :749:{21,152}]\n wire [259:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T;\t// @[Monitor.scala:728:35, :750:{42,67}]\n wire [259:0] _c_size_lookup_T_6 = {256'h0, _c_size_lookup_T_1[3:0]};\t// @[Monitor.scala:750:{42,93}]\n wire [259:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[259:1]};\t// @[Monitor.scala:750:{93,146}]\n assign c_size_lookup = _c_size_lookup_T_7[3:0];\t// @[Monitor.scala:748:35, :750:{21,146}]\n wire [64:0] d_clr_1;\t// @[Monitor.scala:774:34]\n wire [64:0] d_clr_wo_ready_1;\t// @[Monitor.scala:775:34]\n wire [259:0] d_opcodes_clr_1;\t// @[Monitor.scala:776:34]\n wire [259:0] d_sizes_clr_1;\t// @[Monitor.scala:777:34]\n wire _T_1145 = io_in_d_valid_0 & d_first_2;\t// @[Monitor.scala:36:7, :784:26]\n assign d_clr_wo_ready_1 = _T_1145 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0;\t// @[OneHot.scala:58:35]\n wire _T_1127 = _T_1174 & d_first_2 & d_release_ack_1;\t// @[Decoupled.scala:51:35]\n assign d_clr_1 = _T_1127 ? _d_clr_T_1[64:0] : 65'h0;\t// @[OneHot.scala:58:35]\n wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10;\t// @[Monitor.scala:790:{76,101}]\n assign d_opcodes_clr_1 = _T_1127 ? _d_opcodes_clr_T_11[259:0] : 260'h0;\t// @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]\n wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10;\t// @[Monitor.scala:791:{74,99}]\n assign d_sizes_clr_1 = _T_1127 ? _d_sizes_clr_T_11[259:0] : 260'h0;\t// @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]\n wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0;\t// @[Monitor.scala:36:7, :795:113]\n wire [64:0] _inflight_T_4 = ~d_clr_1;\t// @[Monitor.scala:774:34, :814:46]\n wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4;\t// @[Monitor.scala:814:{35,44,46}]\n wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1;\t// @[Monitor.scala:776:34, :815:62]\n wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4;\t// @[Monitor.scala:815:{43,60,62}]\n wire [259:0] _inflight_sizes_T_4 = ~d_sizes_clr_1;\t// @[Monitor.scala:777:34, :816:58]\n wire [259:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4;\t// @[Monitor.scala:816:{41,56,58}]\n reg [31:0] watchdog_1;\t// @[Monitor.scala:818:27]"}}},{"rowIdx":582,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to the following Chisel files.\nFile EarlyTrapCheck.scala:\npackage saturn.frontend\n\nimport chisel3._\nimport chisel3.util._\nimport org.chipsalliance.cde.config._\nimport freechips.rocketchip.rocket._\nimport freechips.rocketchip.util._\nimport freechips.rocketchip.tile._\nimport freechips.rocketchip.tilelink._\nimport freechips.rocketchip.diplomacy._\n\nimport saturn.common._\nimport saturn.backend.{VectorBackend}\n\nclass EarlyTrapCheck(edge: TLEdge, sgSize: Option[BigInt])(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams {\n\n val unified_addresses = AddressSet.unify(edge.manager.managers.map(_.address).flatten)\n require(unified_addresses.forall(_.alignment >= (1 << pgIdxBits)),\n \"Memory devices on this system must be at least page-aligned\")\n\n val io = IO(new Bundle {\n val sg_base = Input(UInt(coreMaxAddrBits.W))\n\n val busy = Output(Bool())\n val s0 = new Bundle {\n val in = Input(Valid(new Bundle {\n val inst = UInt(32.W)\n val pc = UInt(vaddrBitsExtended.W)\n val status = new MStatus\n val vconfig = new VConfig\n val vstart = UInt(log2Ceil(maxVLMax).W)\n val rs1 = UInt(xLen.W)\n val rs2 = UInt(xLen.W)\n val phys = Bool()\n }))\n val tlb_req = Valid(new TLBReq(3))\n }\n\n val s1 = new Bundle {\n val inst = Output(new VectorIssueInst)\n val rs1 = Input(Valid(UInt(xLen.W)))\n val kill = Input(Bool())\n val tlb_req = Valid(new TLBReq(3))\n val tlb_resp = Input(new TLBResp)\n }\n\n val s2 = new Bundle {\n val scalar_store_pending = Input(Bool())\n val inst = Valid(new VectorIssueInst)\n val replay = Output(Bool())\n val vstart = Valid(UInt(log2Ceil(maxVLMax).W))\n val retire = Output(Bool())\n val xcpt = Valid(new Bundle {\n val cause = UInt(xLen.W)\n val tval = UInt(coreMaxAddrBits.W)\n })\n val pc = Output(UInt(vaddrBitsExtended.W))\n val internal_replay = Valid(new VectorIssueInst)\n val issue = Decoupled(new VectorIssueInst)\n val vxrm = Input(UInt(2.W))\n val frm = Input(UInt(3.W))\n }\n })\n\n val s1_valid = RegInit(false.B)\n val s2_valid = RegInit(false.B)\n io.busy := s1_valid || s2_valid\n\n val s0_inst = Wire(new VectorIssueInst)\n s0_inst.pc := io.s0.in.bits.pc\n s0_inst.bits := io.s0.in.bits.inst\n s0_inst.vconfig := io.s0.in.bits.vconfig\n s0_inst.vstart := Mux(s1_valid || s2_valid, 0.U, io.s0.in.bits.vstart)\n s0_inst.segstart := 0.U\n s0_inst.segend := s0_inst.seg_nf\n s0_inst.rs1_data := io.s0.in.bits.rs1\n s0_inst.rs2_data := io.s0.in.bits.rs2\n s0_inst.emul := Mux(io.s0.in.bits.vconfig.vtype.vlmul_sign, 0.U, io.s0.in.bits.vconfig.vtype.vlmul_mag)\n s0_inst.page := DontCare\n s0_inst.vat := DontCare\n s0_inst.debug_id := DontCare\n s0_inst.rm := DontCare\n s0_inst.fast_sg := false.B\n s0_inst.mop := s0_inst.orig_mop\n when (s0_inst.vmu && s0_inst.mop === mopUnit) {\n val mask_vl = (io.s0.in.bits.vconfig.vl >> 3) + Mux(io.s0.in.bits.vconfig.vl(2,0) === 0.U, 0.U, 1.U)\n val whole_vl = (vLen.U >> (s0_inst.mem_elem_size +& 3.U)) * (s0_inst.nf +& 1.U)\n s0_inst.vconfig.vl := MuxLookup(s0_inst.umop, io.s0.in.bits.vconfig.vl)(Seq(\n (lumopWhole -> whole_vl), (lumopMask -> mask_vl)\n ))\n when (s0_inst.umop === lumopWhole) {\n s0_inst.emul := VecInit.tabulate(8)(nf => log2Ceil(nf+1).U)(s0_inst.nf)\n }\n }\n when (!s0_inst.vmu && s0_inst.funct3 === OPIVI && s0_inst.funct6 === OPIFunct6.mvnrr.litValue.U) {\n s0_inst.emul := log2_up(s0_inst.imm5, 8)\n }\n\n val s0_unit = s0_inst.mop === mopUnit || (s0_inst.mop === mopStrided && io.s0.in.bits.rs2 === ((s0_inst.nf +& 1.U) << s0_inst.mem_elem_size))\n val s0_indexed = s0_inst.mop.isOneOf(mopOrdered, mopUnordered)\n val s0_base = io.s0.in.bits.rs1 + (((s0_inst.seg_nf +& 1.U) * s0_inst.vstart ) << s0_inst.mem_elem_size)\n val s0_bound = io.s0.in.bits.rs1 + (((s0_inst.seg_nf +& 1.U) * s0_inst.vconfig.vl) << s0_inst.mem_elem_size) - 1.U\n val s0_single_page = (s0_base >> pgIdxBits) === (s0_bound >> pgIdxBits)\n val s0_replay_next_page = s0_inst.vmu && s0_unit && s0_inst.nf === 0.U && !s0_single_page\n val s0_iterative = (!s0_single_page || !s0_unit || s0_inst.umop === lumopFF) && !s0_replay_next_page\n val s0_fast_sg = s0_iterative && io.s0.in.bits.phys && s0_inst.mop === mopUnordered && s0_inst.seg_nf === 0.U && sgSize.map { size =>\n s0_base >= io.sg_base && s0_base < (io.sg_base + size.U)\n }.getOrElse(false.B)\n\n val s0_tlb_valid = !s0_iterative && s0_inst.vmu && s0_inst.vstart < s0_inst.vconfig.vl\n\n io.s0.tlb_req.valid := s0_tlb_valid && io.s0.in.valid\n io.s0.tlb_req.bits.vaddr := s0_base\n io.s0.tlb_req.bits.passthrough := false.B\n io.s0.tlb_req.bits.size := s0_inst.mem_elem_size\n io.s0.tlb_req.bits.cmd := Mux(s0_inst.opcode(5), M_XWR, M_XRD)\n io.s0.tlb_req.bits.prv := io.s0.in.bits.status.prv\n io.s0.tlb_req.bits.v := io.s0.in.bits.status.v\n\n // s1_stage\n s1_valid := io.s0.in.fire\n val s1_inst = RegEnable(s0_inst , io.s0.in.valid)\n val s1_iterative = RegEnable(s0_iterative , io.s0.in.valid)\n val s1_replay_next_page = RegEnable(s0_replay_next_page, io.s0.in.valid)\n val s1_base = RegEnable(s0_base , io.s0.in.valid)\n val s1_tlb_valid = RegEnable(s0_tlb_valid , io.s0.in.valid)\n val s1_fast_sg = RegEnable(s0_fast_sg , io.s0.in.valid)\n val s1_tlb_resp = WireInit(io.s1.tlb_resp)\n\n when (!s1_tlb_valid) {\n s1_tlb_resp := 0.U.asTypeOf(new TLBResp)\n when (s1_fast_sg) {\n s1_tlb_resp.paddr := s1_base\n }\n }\n\n io.s1.inst := s1_inst\n io.s1.tlb_req.valid := RegNext(io.s0.tlb_req.valid, false.B)\n io.s1.tlb_req.bits := RegEnable(io.s0.tlb_req.bits, s0_tlb_valid)\n\n // s2 stage\n s2_valid := s1_valid && !io.s1.kill\n val s2_inst = Reg(new VectorIssueInst)\n val s2_base = RegEnable(s1_base, s1_valid)\n val s2_iterative = RegEnable(s1_iterative , s1_valid)\n val s2_fast_sg = RegEnable(s1_fast_sg , s1_valid)\n val s2_replay_next_page = RegEnable(s1_replay_next_page, s1_valid)\n when (s1_valid) {\n s2_inst := s1_inst\n when (io.s1.rs1.valid) { s2_inst.rs1_data := io.s1.rs1.bits }\n }\n val s2_tlb_resp = RegEnable(s1_tlb_resp, s1_valid)\n\n val s2_xcpts = Seq(\n (s2_tlb_resp.pf.st, Causes.store_page_fault.U),\n (s2_tlb_resp.pf.ld, Causes.load_page_fault.U),\n (s2_tlb_resp.gf.st, Causes.store_guest_page_fault.U),\n (s2_tlb_resp.gf.ld, Causes.load_guest_page_fault.U),\n (s2_tlb_resp.ae.st, Causes.store_access.U),\n (s2_tlb_resp.ae.ld, Causes.load_access.U),\n (s2_tlb_resp.ma.st, Causes.misaligned_store.U),\n (s2_tlb_resp.ma.ld, Causes.misaligned_load.U)\n )\n val s2_xcpt = s2_xcpts.map(_._1).orR\n val s2_cause = PriorityMux(s2_xcpts)\n val s2_go_to_itc = WireInit(s2_inst.vmu && s2_iterative)\n val s2_generate_xcpt = WireInit(s2_xcpt)\n\n // masked checks, even in the fast case, need to\n // to to ITC to get the precise element+address of the trap\n when (s2_inst.vmu && s2_xcpt && !s2_inst.vm) {\n s2_go_to_itc := true.B\n s2_generate_xcpt := false.B\n }\n\n io.s2.inst.valid := s2_valid\n io.s2.inst.bits := s2_inst\n io.s2.replay := false.B\n io.s2.vstart.valid := false.B\n io.s2.vstart.bits := 0.U\n io.s2.retire := false.B\n io.s2.internal_replay.valid := false.B\n io.s2.internal_replay.bits := s2_inst\n io.s2.internal_replay.bits.rm := Mux(s2_inst.isOpf, io.s2.frm, io.s2.vxrm)\n io.s2.xcpt.valid := false.B\n io.s2.xcpt.bits.cause := s2_cause\n io.s2.xcpt.bits.tval := s2_base\n io.s2.pc := s2_inst.pc\n io.s2.issue.valid := false.B\n io.s2.issue.bits := s2_inst\n io.s2.issue.bits.segstart := 0.U\n io.s2.issue.bits.segend := s2_inst.seg_nf\n io.s2.issue.bits.rm := Mux(s2_inst.isOpf, io.s2.frm, io.s2.vxrm)\n io.s2.issue.bits.page := s2_tlb_resp.paddr >> pgIdxBits\n\n val consumed = ((1 << pgIdxBits).U - s2_tlb_resp.paddr(pgIdxBits-1,0)) >> s2_inst.mem_elem_size\n when (s2_inst.vmu && s2_replay_next_page) {\n io.s2.issue.bits.vconfig.vl := s2_inst.vstart +& consumed\n }\n\n when (s2_valid) {\n when (!io.s2.issue.ready || (io.s2.scalar_store_pending && s2_inst.vmu)) {\n io.s2.replay := true.B\n } .elsewhen (s2_inst.vstart =/= 0.U && !s2_inst.vmu) {\n io.s2.xcpt.valid := true.B\n io.s2.xcpt.bits.cause := Causes.illegal_instruction.U\n io.s2.xcpt.bits.tval := s2_inst.pc\n } .elsewhen (s2_inst.vstart >= s2_inst.vconfig.vl) {\n io.s2.retire := true.B\n io.s2.issue.valid := true.B\n io.s2.vstart.valid := true.B\n } .elsewhen (s2_tlb_resp.miss) {\n io.s2.replay := true.B\n } .elsewhen (s2_generate_xcpt) {\n io.s2.xcpt.valid := true.B\n } .elsewhen (s2_inst.vmu && s2_fast_sg) {\n io.s2.retire := true.B\n io.s2.issue.valid := true.B\n io.s2.issue.bits.fast_sg := true.B\n io.s2.vstart.valid := true.B\n } .elsewhen (s2_go_to_itc) {\n io.s2.internal_replay.valid := true.B\n } .elsewhen (s2_replay_next_page) {\n io.s2.replay := true.B\n io.s2.issue.valid := true.B\n io.s2.vstart.valid := true.B\n io.s2.vstart.bits := s2_inst.vstart +& consumed\n } .otherwise {\n io.s2.retire := true.B\n io.s2.vstart.valid := true.B\n io.s2.issue.valid := true.B\n }\n }\n\n}\n"},"response":{"kind":"string","value":"module EarlyTrapCheck(\t// @[EarlyTrapCheck.scala:15:7]\n input clock,\t// @[EarlyTrapCheck.scala:15:7]\n input reset,\t// @[EarlyTrapCheck.scala:15:7]\n output io_busy,\t// @[EarlyTrapCheck.scala:21:14]\n input io_s0_in_valid,\t// @[EarlyTrapCheck.scala:21:14]\n input [31:0] io_s0_in_bits_inst,\t// @[EarlyTrapCheck.scala:21:14]\n input [39:0] io_s0_in_bits_pc,\t// @[EarlyTrapCheck.scala:21:14]\n input [1:0] io_s0_in_bits_status_prv,\t// @[EarlyTrapCheck.scala:21:14]\n input [8:0] io_s0_in_bits_vconfig_vl,\t// @[EarlyTrapCheck.scala:21:14]\n input io_s0_in_bits_vconfig_vtype_vill,\t// @[EarlyTrapCheck.scala:21:14]\n input [54:0] io_s0_in_bits_vconfig_vtype_reserved,\t// @[EarlyTrapCheck.scala:21:14]\n input io_s0_in_bits_vconfig_vtype_vma,\t// @[EarlyTrapCheck.scala:21:14]\n input io_s0_in_bits_vconfig_vtype_vta,\t// @[EarlyTrapCheck.scala:21:14]\n input [2:0] io_s0_in_bits_vconfig_vtype_vsew,\t// @[EarlyTrapCheck.scala:21:14]\n input io_s0_in_bits_vconfig_vtype_vlmul_sign,\t// @[EarlyTrapCheck.scala:21:14]\n input [1:0] io_s0_in_bits_vconfig_vtype_vlmul_mag,\t// @[EarlyTrapCheck.scala:21:14]\n input [7:0] io_s0_in_bits_vstart,\t// @[EarlyTrapCheck.scala:21:14]\n input [63:0] io_s0_in_bits_rs1,\t// @[EarlyTrapCheck.scala:21:14]\n input [63:0] io_s0_in_bits_rs2,\t// @[EarlyTrapCheck.scala:21:14]\n output [31:0] io_s1_inst_bits,\t// @[EarlyTrapCheck.scala:21:14]\n input io_s1_rs1_valid,\t// @[EarlyTrapCheck.scala:21:14]\n input [63:0] io_s1_rs1_bits,\t// @[EarlyTrapCheck.scala:21:14]\n input io_s1_kill,\t// @[EarlyTrapCheck.scala:21:14]\n output io_s1_tlb_req_valid,\t// @[EarlyTrapCheck.scala:21:14]\n output [39:0] io_s1_tlb_req_bits_vaddr,\t// @[EarlyTrapCheck.scala:21:14]\n output [1:0] io_s1_tlb_req_bits_size,\t// @[EarlyTrapCheck.scala:21:14]\n output [4:0] io_s1_tlb_req_bits_cmd,\t// @[EarlyTrapCheck.scala:21:14]\n output [1:0] io_s1_tlb_req_bits_prv,\t// @[EarlyTrapCheck.scala:21:14]\n input io_s1_tlb_resp_miss,\t// @[EarlyTrapCheck.scala:21:14]\n input [31:0] io_s1_tlb_resp_paddr,\t// @[EarlyTrapCheck.scala:21:14]\n input io_s1_tlb_resp_pf_ld,\t// @[EarlyTrapCheck.scala:21:14]\n input io_s1_tlb_resp_pf_st,\t// @[EarlyTrapCheck.scala:21:14]\n input io_s1_tlb_resp_ae_ld,\t// @[EarlyTrapCheck.scala:21:14]\n input io_s1_tlb_resp_ae_st,\t// @[EarlyTrapCheck.scala:21:14]\n input io_s1_tlb_resp_ma_ld,\t// @[EarlyTrapCheck.scala:21:14]\n input io_s1_tlb_resp_ma_st,\t// @[EarlyTrapCheck.scala:21:14]\n input io_s2_scalar_store_pending,\t// @[EarlyTrapCheck.scala:21:14]\n output io_s2_inst_valid,\t// @[EarlyTrapCheck.scala:21:14]\n output [31:0] io_s2_inst_bits_bits,\t// @[EarlyTrapCheck.scala:21:14]\n output io_s2_vstart_valid,\t// @[EarlyTrapCheck.scala:21:14]\n output [7:0] io_s2_vstart_bits,\t// @[EarlyTrapCheck.scala:21:14]\n output io_s2_retire,\t// @[EarlyTrapCheck.scala:21:14]\n output io_s2_xcpt_valid,\t// @[EarlyTrapCheck.scala:21:14]\n output [63:0] io_s2_xcpt_bits_cause,\t// @[EarlyTrapCheck.scala:21:14]\n output [39:0] io_s2_xcpt_bits_tval,\t// @[EarlyTrapCheck.scala:21:14]\n output [39:0] io_s2_pc,\t// @[EarlyTrapCheck.scala:21:14]\n output io_s2_internal_replay_valid,\t// @[EarlyTrapCheck.scala:21:14]\n output [39:0] io_s2_internal_replay_bits_pc,\t// @[EarlyTrapCheck.scala:21:14]\n output [31:0] io_s2_internal_replay_bits_bits,\t// @[EarlyTrapCheck.scala:21:14]\n output [8:0] io_s2_internal_replay_bits_vconfig_vl,\t// @[EarlyTrapCheck.scala:21:14]\n output io_s2_internal_replay_bits_vconfig_vtype_vill,\t// @[EarlyTrapCheck.scala:21:14]\n output [54:0] io_s2_internal_replay_bits_vconfig_vtype_reserved,\t// @[EarlyTrapCheck.scala:21:14]\n output io_s2_internal_replay_bits_vconfig_vtype_vma,\t// @[EarlyTrapCheck.scala:21:14]\n output io_s2_internal_replay_bits_vconfig_vtype_vta,\t// @[EarlyTrapCheck.scala:21:14]\n output [2:0] io_s2_internal_replay_bits_vconfig_vtype_vsew,\t// @[EarlyTrapCheck.scala:21:14]\n output io_s2_internal_replay_bits_vconfig_vtype_vlmul_sign,\t// @[EarlyTrapCheck.scala:21:14]\n output [1:0] io_s2_internal_replay_bits_vconfig_vtype_vlmul_mag,\t// @[EarlyTrapCheck.scala:21:14]\n output [7:0] io_s2_internal_replay_bits_vstart,\t// @[EarlyTrapCheck.scala:21:14]\n output [63:0] io_s2_internal_replay_bits_rs1_data,\t// @[EarlyTrapCheck.scala:21:14]\n output [63:0] io_s2_internal_replay_bits_rs2_data,\t// @[EarlyTrapCheck.scala:21:14]\n output [2:0] io_s2_internal_replay_bits_rm,\t// @[EarlyTrapCheck.scala:21:14]\n output [1:0] io_s2_internal_replay_bits_emul,\t// @[EarlyTrapCheck.scala:21:14]\n output [1:0] io_s2_internal_replay_bits_mop,\t// @[EarlyTrapCheck.scala:21:14]\n input io_s2_issue_ready,\t// @[EarlyTrapCheck.scala:21:14]\n output io_s2_issue_valid,\t// @[EarlyTrapCheck.scala:21:14]\n output [31:0] io_s2_issue_bits_bits,\t// @[EarlyTrapCheck.scala:21:14]\n output [8:0] io_s2_issue_bits_vconfig_vl,\t// @[EarlyTrapCheck.scala:21:14]\n output [2:0] io_s2_issue_bits_vconfig_vtype_vsew,\t// @[EarlyTrapCheck.scala:21:14]\n output io_s2_issue_bits_vconfig_vtype_vlmul_sign,\t// @[EarlyTrapCheck.scala:21:14]\n output [1:0] io_s2_issue_bits_vconfig_vtype_vlmul_mag,\t// @[EarlyTrapCheck.scala:21:14]\n output [7:0] io_s2_issue_bits_vstart,\t// @[EarlyTrapCheck.scala:21:14]\n output [2:0] io_s2_issue_bits_segend,\t// @[EarlyTrapCheck.scala:21:14]\n output [63:0] io_s2_issue_bits_rs1_data,\t// @[EarlyTrapCheck.scala:21:14]\n output [63:0] io_s2_issue_bits_rs2_data,\t// @[EarlyTrapCheck.scala:21:14]\n output [19:0] io_s2_issue_bits_page,\t// @[EarlyTrapCheck.scala:21:14]\n output [2:0] io_s2_issue_bits_rm,\t// @[EarlyTrapCheck.scala:21:14]\n output [1:0] io_s2_issue_bits_emul,\t// @[EarlyTrapCheck.scala:21:14]\n output [1:0] io_s2_issue_bits_mop,\t// @[EarlyTrapCheck.scala:21:14]\n input [1:0] io_s2_vxrm,\t// @[EarlyTrapCheck.scala:21:14]\n input [2:0] io_s2_frm\t// @[EarlyTrapCheck.scala:21:14]\n);\n\n reg s1_valid;\t// @[EarlyTrapCheck.scala:65:25]\n reg s2_valid;\t// @[EarlyTrapCheck.scala:66:25]\n wire io_busy_0 = s1_valid | s2_valid;\t// @[EarlyTrapCheck.scala:65:25, :66:25, :67:23]\n reg [39:0] s1_inst_pc;\t// @[EarlyTrapCheck.scala:122:38]\n reg [31:0] s1_inst_bits;\t// @[EarlyTrapCheck.scala:122:38]\n reg [8:0] s1_inst_vconfig_vl;\t// @[EarlyTrapCheck.scala:122:38]\n reg s1_inst_vconfig_vtype_vill;\t// @[EarlyTrapCheck.scala:122:38]\n reg [54:0] s1_inst_vconfig_vtype_reserved;\t// @[EarlyTrapCheck.scala:122:38]\n reg s1_inst_vconfig_vtype_vma;\t// @[EarlyTrapCheck.scala:122:38]\n reg s1_inst_vconfig_vtype_vta;\t// @[EarlyTrapCheck.scala:122:38]\n reg [2:0] s1_inst_vconfig_vtype_vsew;\t// @[EarlyTrapCheck.scala:122:38]\n reg s1_inst_vconfig_vtype_vlmul_sign;\t// @[EarlyTrapCheck.scala:122:38]\n reg [1:0] s1_inst_vconfig_vtype_vlmul_mag;\t// @[EarlyTrapCheck.scala:122:38]\n reg [7:0] s1_inst_vstart;\t// @[EarlyTrapCheck.scala:122:38]\n reg [63:0] s1_inst_rs1_data;\t// @[EarlyTrapCheck.scala:122:38]\n reg [63:0] s1_inst_rs2_data;\t// @[EarlyTrapCheck.scala:122:38]\n reg [1:0] s1_inst_emul;\t// @[EarlyTrapCheck.scala:122:38]\n reg [1:0] s1_inst_mop;\t// @[EarlyTrapCheck.scala:122:38]\n reg s1_iterative;\t// @[EarlyTrapCheck.scala:123:38]\n reg s1_replay_next_page;\t// @[EarlyTrapCheck.scala:124:38]\n reg [63:0] s1_base;\t// @[EarlyTrapCheck.scala:125:38]\n reg s1_tlb_valid;\t// @[EarlyTrapCheck.scala:126:38]\n reg io_s1_tlb_req_valid_REG;\t// @[EarlyTrapCheck.scala:138:33]\n reg [39:0] io_s1_tlb_req_bits_r_vaddr;\t// @[EarlyTrapCheck.scala:139:35]\n reg [1:0] io_s1_tlb_req_bits_r_size;\t// @[EarlyTrapCheck.scala:139:35]\n reg [4:0] io_s1_tlb_req_bits_r_cmd;\t// @[EarlyTrapCheck.scala:139:35]\n reg [1:0] io_s1_tlb_req_bits_r_prv;\t// @[EarlyTrapCheck.scala:139:35]\n reg [39:0] s2_inst_pc;\t// @[EarlyTrapCheck.scala:143:20]\n reg [31:0] s2_inst_bits;\t// @[EarlyTrapCheck.scala:143:20]\n reg [8:0] s2_inst_vconfig_vl;\t// @[EarlyTrapCheck.scala:143:20]\n reg s2_inst_vconfig_vtype_vill;\t// @[EarlyTrapCheck.scala:143:20]\n reg [54:0] s2_inst_vconfig_vtype_reserved;\t// @[EarlyTrapCheck.scala:143:20]\n reg s2_inst_vconfig_vtype_vma;\t// @[EarlyTrapCheck.scala:143:20]\n reg s2_inst_vconfig_vtype_vta;\t// @[EarlyTrapCheck.scala:143:20]\n reg [2:0] s2_inst_vconfig_vtype_vsew;\t// @[EarlyTrapCheck.scala:143:20]\n reg s2_inst_vconfig_vtype_vlmul_sign;\t// @[EarlyTrapCheck.scala:143:20]\n reg [1:0] s2_inst_vconfig_vtype_vlmul_mag;\t// @[EarlyTrapCheck.scala:143:20]\n reg [7:0] s2_inst_vstart;\t// @[EarlyTrapCheck.scala:143:20]\n reg [63:0] s2_inst_rs1_data;\t// @[EarlyTrapCheck.scala:143:20]\n reg [63:0] s2_inst_rs2_data;\t// @[EarlyTrapCheck.scala:143:20]\n reg [1:0] s2_inst_emul;\t// @[EarlyTrapCheck.scala:143:20]\n reg [1:0] s2_inst_mop;\t// @[EarlyTrapCheck.scala:143:20]\n reg [63:0] s2_base;\t// @[EarlyTrapCheck.scala:144:26]\n reg s2_iterative;\t// @[EarlyTrapCheck.scala:145:38]\n reg s2_replay_next_page;\t// @[EarlyTrapCheck.scala:147:38]\n reg s2_tlb_resp_miss;\t// @[EarlyTrapCheck.scala:152:30]\n reg [31:0] s2_tlb_resp_paddr;\t// @[EarlyTrapCheck.scala:152:30]\n reg s2_tlb_resp_pf_ld;\t// @[EarlyTrapCheck.scala:152:30]\n reg s2_tlb_resp_pf_st;\t// @[EarlyTrapCheck.scala:152:30]\n reg s2_tlb_resp_ae_ld;\t// @[EarlyTrapCheck.scala:152:30]\n reg s2_tlb_resp_ae_st;\t// @[EarlyTrapCheck.scala:152:30]\n reg s2_tlb_resp_ma_ld;\t// @[EarlyTrapCheck.scala:152:30]\n reg s2_tlb_resp_ma_st;\t// @[EarlyTrapCheck.scala:152:30]\n wire s2_xcpt = s2_tlb_resp_pf_st | s2_tlb_resp_pf_ld | s2_tlb_resp_ae_st | s2_tlb_resp_ae_ld | s2_tlb_resp_ma_st | s2_tlb_resp_ma_ld;\t// @[EarlyTrapCheck.scala:152:30]\n wire _GEN = s2_inst_bits[6:0] == 7'h7 | s2_inst_bits[6:0] == 7'h27;\t// @[EarlyTrapCheck.scala:143:20]\n wire _GEN_0 = _GEN & s2_xcpt & ~(s2_inst_bits[25]);\t// @[EarlyTrapCheck.scala:143:20, :171:{21,32,35}]\n wire s2_go_to_itc = _GEN_0 | (s2_inst_bits[6:0] == 7'h7 | s2_inst_bits[6:0] == 7'h27) & s2_iterative;\t// @[EarlyTrapCheck.scala:143:20, :145:38, :166:{30,43}, :171:{21,32,48}, :172:18]\n wire s2_generate_xcpt = ~_GEN_0 & s2_xcpt;\t// @[EarlyTrapCheck.scala:167:34, :171:{21,32,48}, :173:22]\n wire [2:0] _GEN_1 = {1'h0, io_s2_vxrm};\t// @[EarlyTrapCheck.scala:184:39]\n wire [12:0] consumed = 13'h1000 - {1'h0, s2_tlb_resp_paddr[11:0]} >> (s2_inst_mop[0] ? s2_inst_vconfig_vtype_vsew : {1'h0, s2_inst_bits[13:12]});\t// @[EarlyTrapCheck.scala:143:20, :152:30, :196:{38,57,74}]\n wire [8:0] _GEN_2 = {1'h0, s2_inst_vstart};\t// @[EarlyTrapCheck.scala:143:20, :198:51]\n wire _GEN_3 = ~io_s2_issue_ready | io_s2_scalar_store_pending & _GEN;\t// @[EarlyTrapCheck.scala:202:{11,30,61}]\n wire _GEN_4 = (|s2_inst_vstart) & ~_GEN;\t// @[EarlyTrapCheck.scala:143:20, :204:{33,41,44}]\n wire _GEN_5 = ~s2_valid | _GEN_3 | ~_GEN_4;\t// @[EarlyTrapCheck.scala:66:25, :186:29, :201:19, :202:{30,78}, :204:{41,58}]\n wire _GEN_6 = _GEN_2 >= s2_inst_vconfig_vl;\t// @[EarlyTrapCheck.scala:143:20, :198:51, :208:33]\n wire _GEN_7 = s2_tlb_resp_miss | s2_generate_xcpt;\t// @[EarlyTrapCheck.scala:152:30, :167:34, :171:48, :173:22, :182:33, :212:36, :214:36, :216:45, :221:32]\n wire _GEN_8 = _GEN_3 | _GEN_4;\t// @[EarlyTrapCheck.scala:181:22, :202:{30,78}, :204:{41,58}, :208:56]\n wire io_s2_issue_valid_0 = s2_valid & ~_GEN_8 & (_GEN_6 | ~_GEN_7 & ~s2_go_to_itc);\t// @[EarlyTrapCheck.scala:66:25, :166:30, :171:48, :172:18, :179:22, :181:22, :182:33, :201:19, :202:78, :204:58, :208:{33,56}, :211:26, :212:36, :214:36, :216:45, :221:32, :223:39]\n wire [7:0][1:0] _GEN_9 = '{2'h3, 2'h3, 2'h3, 2'h3, 2'h2, 2'h2, 2'h1, 2'h0};\n wire [7:0] s0_inst_vstart = io_busy_0 ? 8'h0 : io_s0_in_bits_vstart;\t// @[EarlyTrapCheck.scala:67:23, :73:26]\n wire _GEN_10 = io_s0_in_bits_inst[6:0] == 7'h7 | io_s0_in_bits_inst[6:0] == 7'h27;\t// @[Bundles.scala:56:20]\n wire _s0_unit_T = io_s0_in_bits_inst[27:26] == 2'h0;\t// @[EarlyTrapCheck.scala:85:36]\n wire _GEN_11 = _GEN_10 & _s0_unit_T;\t// @[EarlyTrapCheck.scala:85:{21,36}]\n wire [3:0] _GEN_12 = {1'h0, io_s0_in_bits_inst[31:29]};\t// @[EarlyTrapCheck.scala:87:77]\n wire [8:0] s0_inst_vconfig_vl = _GEN_11 ? (io_s0_in_bits_inst[24:20] == 5'hB ? {3'h0, io_s0_in_bits_vconfig_vl[8:3] + {5'h0, |(io_s0_in_bits_vconfig_vl[2:0])}} : io_s0_in_bits_inst[24:20] == 5'h8 ? (9'h100 >> {1'h0, io_s0_in_bits_inst[26] ? io_s0_in_bits_vconfig_vtype_vsew : {1'h0, io_s0_in_bits_inst[13:12]}} + 4'h3) * {5'h0, _GEN_12 + 4'h1} : io_s0_in_bits_vconfig_vl) : io_s0_in_bits_vconfig_vl;\t// @[EarlyTrapCheck.scala:15:7, :72:19, :85:{21,49}, :86:{45,51,81,87}, :87:{28,54,63,77}, :88:{24,76}]\n wire [2:0] _GEN_13 = {1'h0, io_s0_in_bits_inst[13:12]};\t// @[Bundles.scala:59:{26,59}]\n wire s0_unit = _s0_unit_T | io_s0_in_bits_inst[27:26] == 2'h2 & io_s0_in_bits_rs2 == {53'h0, {7'h0, _GEN_12 + 4'h1} << (io_s0_in_bits_inst[26] ? io_s0_in_bits_vconfig_vtype_vsew : _GEN_13)};\t// @[EarlyTrapCheck.scala:85:36, :87:77, :88:76, :99:{41,57,72,93,110,118}]\n wire [63:0] _s0_base_T_13 = io_s0_in_bits_rs1 + {45'h0, {7'h0, {8'h0, {1'h0, ~(|(io_s0_in_bits_inst[27:26])) & io_s0_in_bits_inst[24:20] == 5'h8 ? 3'h0 : io_s0_in_bits_inst[31:29]} + 4'h1} * {4'h0, s0_inst_vstart}} << (io_s0_in_bits_inst[26] ? io_s0_in_bits_vconfig_vtype_vsew : _GEN_13)};\t// @[EarlyTrapCheck.scala:15:7, :73:26, :88:76, :101:{36,56,64,86}]\n wire [63:0] _s0_bound_T_15 = io_s0_in_bits_rs1 + {44'h0, {7'h0, {9'h0, {1'h0, ~(|(io_s0_in_bits_inst[27:26])) & io_s0_in_bits_inst[24:20] == 5'h8 ? 3'h0 : io_s0_in_bits_inst[31:29]} + 4'h1} * {4'h0, s0_inst_vconfig_vl}} << (io_s0_in_bits_inst[26] ? io_s0_in_bits_vconfig_vtype_vsew : _GEN_13)} - 64'h1;\t// @[EarlyTrapCheck.scala:15:7, :72:19, :85:49, :87:63, :88:{24,76}, :102:{36,56,64,86,112}]\n wire _s0_iterative_T = _s0_base_T_13[63:12] != _s0_bound_T_15[63:12];\t// @[EarlyTrapCheck.scala:101:36, :102:{36,112}, :103:{33,47,61}, :104:77]\n wire s0_replay_next_page = (io_s0_in_bits_inst[6:0] == 7'h7 | io_s0_in_bits_inst[6:0] == 7'h27) & s0_unit & io_s0_in_bits_inst[31:29] == 3'h0 & _s0_iterative_T;\t// @[EarlyTrapCheck.scala:99:41, :103:47, :104:{41,52,66,74,77}]\n wire s0_iterative = (_s0_iterative_T | ~s0_unit | io_s0_in_bits_inst[24:20] == 5'h10) & ~s0_replay_next_page;\t// @[EarlyTrapCheck.scala:15:7, :99:41, :103:47, :104:{41,52,74,77}, :105:{39,42,51,67,80,83}]\n wire s0_tlb_valid = ~s0_iterative & (io_s0_in_bits_inst[6:0] == 7'h7 | io_s0_in_bits_inst[6:0] == 7'h27) & {1'h0, s0_inst_vstart} < s0_inst_vconfig_vl;\t// @[EarlyTrapCheck.scala:72:19, :73:26, :85:49, :88:24, :105:80, :110:{22,36,51,69}]\n always @(posedge clock) begin\t// @[EarlyTrapCheck.scala:15:7]\n if (reset) begin\t// @[EarlyTrapCheck.scala:15:7]\n s1_valid <= 1'h0;\t// @[EarlyTrapCheck.scala:65:25]\n s2_valid <= 1'h0;\t// @[EarlyTrapCheck.scala:66:25]\n io_s1_tlb_req_valid_REG <= 1'h0;\t// @[EarlyTrapCheck.scala:138:33]\n end\n else begin\t// @[EarlyTrapCheck.scala:15:7]\n s1_valid <= io_s0_in_valid;\t// @[EarlyTrapCheck.scala:65:25]\n s2_valid <= s1_valid & ~io_s1_kill;\t// @[EarlyTrapCheck.scala:65:25, :66:25, :142:{24,27}]\n io_s1_tlb_req_valid_REG <= s0_tlb_valid & io_s0_in_valid;\t// @[EarlyTrapCheck.scala:110:{36,51}, :112:50, :138:33]\n end\n if (io_s0_in_valid) begin\t// @[EarlyTrapCheck.scala:21:14]\n s1_inst_pc <= io_s0_in_bits_pc;\t// @[EarlyTrapCheck.scala:122:38]\n s1_inst_bits <= io_s0_in_bits_inst;\t// @[EarlyTrapCheck.scala:122:38]\n s1_inst_vconfig_vl <= s0_inst_vconfig_vl;\t// @[EarlyTrapCheck.scala:72:19, :85:49, :88:24, :122:38]\n s1_inst_vconfig_vtype_vill <= io_s0_in_bits_vconfig_vtype_vill;\t// @[EarlyTrapCheck.scala:122:38]\n s1_inst_vconfig_vtype_reserved <= io_s0_in_bits_vconfig_vtype_reserved;\t// @[EarlyTrapCheck.scala:122:38]\n s1_inst_vconfig_vtype_vma <= io_s0_in_bits_vconfig_vtype_vma;\t// @[EarlyTrapCheck.scala:122:38]\n s1_inst_vconfig_vtype_vta <= io_s0_in_bits_vconfig_vtype_vta;\t// @[EarlyTrapCheck.scala:122:38]\n s1_inst_vconfig_vtype_vsew <= io_s0_in_bits_vconfig_vtype_vsew;\t// @[EarlyTrapCheck.scala:122:38]\n s1_inst_vconfig_vtype_vlmul_sign <= io_s0_in_bits_vconfig_vtype_vlmul_sign;\t// @[EarlyTrapCheck.scala:122:38]\n s1_inst_vconfig_vtype_vlmul_mag <= io_s0_in_bits_vconfig_vtype_vlmul_mag;\t// @[EarlyTrapCheck.scala:122:38]\n s1_inst_vstart <= s0_inst_vstart;\t// @[EarlyTrapCheck.scala:73:26, :122:38]\n s1_inst_rs1_data <= io_s0_in_bits_rs1;\t// @[EarlyTrapCheck.scala:122:38]\n s1_inst_rs2_data <= io_s0_in_bits_rs2;\t// @[EarlyTrapCheck.scala:122:38]\n s1_inst_emul <= ~_GEN_10 & io_s0_in_bits_inst[14:12] == 3'h3 & io_s0_in_bits_inst[31:26] == 6'h27 ? _GEN_9[io_s0_in_bits_inst[17:15]] : _GEN_11 & io_s0_in_bits_inst[24:20] == 5'h8 ? _GEN_9[io_s0_in_bits_inst[31:29]] : io_s0_in_bits_vconfig_vtype_vlmul_sign ? 2'h0 : io_s0_in_bits_vconfig_vtype_vlmul_mag;\t// @[EarlyTrapCheck.scala:15:7, :78:{20,26}, :85:{21,49}, :91:{24,40}, :92:20, :95:{9,22,40,50,68,100}, :96:18, :122:38]\n s1_inst_mop <= io_s0_in_bits_inst[27:26];\t// @[EarlyTrapCheck.scala:122:38]\n s1_iterative <= s0_iterative;\t// @[EarlyTrapCheck.scala:105:80, :123:38]\n s1_replay_next_page <= s0_replay_next_page;\t// @[EarlyTrapCheck.scala:104:{41,52,74}, :124:38]\n s1_base <= _s0_base_T_13;\t// @[EarlyTrapCheck.scala:101:36, :125:38]\n s1_tlb_valid <= s0_tlb_valid;\t// @[EarlyTrapCheck.scala:110:{36,51}, :126:38]\n end\n if (s0_tlb_valid) begin\t// @[EarlyTrapCheck.scala:110:{36,51}]\n io_s1_tlb_req_bits_r_vaddr <= _s0_base_T_13[39:0];\t// @[EarlyTrapCheck.scala:101:36, :113:34, :139:35]\n io_s1_tlb_req_bits_r_size <= io_s0_in_bits_inst[26] ? io_s0_in_bits_vconfig_vtype_vsew[1:0] : io_s0_in_bits_inst[13:12];\t// @[EarlyTrapCheck.scala:21:14, :139:35]\n io_s1_tlb_req_bits_r_cmd <= {4'h0, io_s0_in_bits_inst[5]};\t// @[EarlyTrapCheck.scala:116:{34,55}, :139:35]\n io_s1_tlb_req_bits_r_prv <= io_s0_in_bits_status_prv;\t// @[EarlyTrapCheck.scala:139:35]\n end\n if (s1_valid) begin\t// @[EarlyTrapCheck.scala:65:25]\n s2_inst_pc <= s1_inst_pc;\t// @[EarlyTrapCheck.scala:122:38, :143:20]\n s2_inst_bits <= s1_inst_bits;\t// @[EarlyTrapCheck.scala:122:38, :143:20]\n s2_inst_vconfig_vl <= s1_inst_vconfig_vl;\t// @[EarlyTrapCheck.scala:122:38, :143:20]\n s2_inst_vconfig_vtype_vill <= s1_inst_vconfig_vtype_vill;\t// @[EarlyTrapCheck.scala:122:38, :143:20]\n s2_inst_vconfig_vtype_reserved <= s1_inst_vconfig_vtype_reserved;\t// @[EarlyTrapCheck.scala:122:38, :143:20]\n s2_inst_vconfig_vtype_vma <= s1_inst_vconfig_vtype_vma;\t// @[EarlyTrapCheck.scala:122:38, :143:20]\n s2_inst_vconfig_vtype_vta <= s1_inst_vconfig_vtype_vta;\t// @[EarlyTrapCheck.scala:122:38, :143:20]\n s2_inst_vconfig_vtype_vsew <= s1_inst_vconfig_vtype_vsew;\t// @[EarlyTrapCheck.scala:122:38, :143:20]\n s2_inst_vconfig_vtype_vlmul_sign <= s1_inst_vconfig_vtype_vlmul_sign;\t// @[EarlyTrapCheck.scala:122:38, :143:20]\n s2_inst_vconfig_vtype_vlmul_mag <= s1_inst_vconfig_vtype_vlmul_mag;\t// @[EarlyTrapCheck.scala:122:38, :143:20]\n s2_inst_vstart <= s1_inst_vstart;\t// @[EarlyTrapCheck.scala:122:38, :143:20]\n s2_inst_rs1_data <= io_s1_rs1_valid ? io_s1_rs1_bits : s1_inst_rs1_data;\t// @[EarlyTrapCheck.scala:122:38, :143:20, :149:13, :150:{28,47}]\n s2_inst_rs2_data <= s1_inst_rs2_data;\t// @[EarlyTrapCheck.scala:122:38, :143:20]\n s2_inst_emul <= s1_inst_emul;\t// @[EarlyTrapCheck.scala:122:38, :143:20]\n s2_inst_mop <= s1_inst_mop;\t// @[EarlyTrapCheck.scala:122:38, :143:20]\n s2_base <= s1_base;\t// @[EarlyTrapCheck.scala:125:38, :144:26]\n s2_iterative <= s1_iterative;\t// @[EarlyTrapCheck.scala:123:38, :145:38]\n s2_replay_next_page <= s1_replay_next_page;\t// @[EarlyTrapCheck.scala:124:38, :147:38]\n s2_tlb_resp_miss <= s1_tlb_valid & io_s1_tlb_resp_miss;\t// @[EarlyTrapCheck.scala:126:38, :128:37, :130:24, :131:17, :152:30]\n s2_tlb_resp_paddr <= s1_tlb_valid ? io_s1_tlb_resp_paddr : 32'h0;\t// @[EarlyTrapCheck.scala:126:38, :128:37, :130:24, :132:23, :152:30]\n s2_tlb_resp_pf_ld <= s1_tlb_valid & io_s1_tlb_resp_pf_ld;\t// @[EarlyTrapCheck.scala:126:38, :128:37, :130:24, :131:17, :152:30]\n s2_tlb_resp_pf_st <= s1_tlb_valid & io_s1_tlb_resp_pf_st;\t// @[EarlyTrapCheck.scala:126:38, :128:37, :130:24, :131:17, :152:30]\n s2_tlb_resp_ae_ld <= s1_tlb_valid & io_s1_tlb_resp_ae_ld;\t// @[EarlyTrapCheck.scala:126:38, :128:37, :130:24, :131:17, :152:30]\n s2_tlb_resp_ae_st <= s1_tlb_valid & io_s1_tlb_resp_ae_st;\t// @[EarlyTrapCheck.scala:126:38, :128:37, :130:24, :131:17, :152:30]\n s2_tlb_resp_ma_ld <= s1_tlb_valid & io_s1_tlb_resp_ma_ld;\t// @[EarlyTrapCheck.scala:126:38, :128:37, :130:24, :131:17, :152:30]\n s2_tlb_resp_ma_st <= s1_tlb_valid & io_s1_tlb_resp_ma_st;\t// @[EarlyTrapCheck.scala:126:38, :128:37, :130:24, :131:17, :152:30]\n end\n always @(posedge)"}}},{"rowIdx":583,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to the following Chisel files.\nFile ShiftReg.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3._\n\n// Similar to the Chisel ShiftRegister but allows the user to suggest a\n// name to the registers that get instantiated, and\n// to provide a reset value.\nobject ShiftRegInit {\n def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =\n\n (0 until n).foldRight(in) {\n case (i, next) => {\n val r = RegNext(next, init)\n name.foreach { na => r.suggestName(s\"${na}_${i}\") }\n r\n }\n }\n}\n\n/** These wrap behavioral\n * shift registers into specific modules to allow for\n * backend flows to replace or constrain\n * them properly when used for CDC synchronization,\n * rather than buffering.\n * \n * The different types vary in their reset behavior:\n * AsyncResetShiftReg -- Asynchronously reset register array\n * A W(width) x D(depth) sized array is constructed from D instantiations of a\n * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,\n * but only used for timing applications\n */\n\nabstract class AbstractPipelineReg(w: Int = 1) extends Module {\n val io = IO(new Bundle {\n val d = Input(UInt(w.W))\n val q = Output(UInt(w.W))\n }\n )\n}\n\nobject AbstractPipelineReg {\n def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {\n val chain = Module(gen)\n name.foreach{ chain.suggestName(_) }\n chain.io.d := in.asUInt\n chain.io.q.asTypeOf(in)\n }\n}\n\nclass AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = \"pipe\") extends AbstractPipelineReg(w) {\n require(depth > 0, \"Depth must be greater than 0.\")\n\n override def desiredName = s\"AsyncResetShiftReg_w${w}_d${depth}_i${init}\"\n\n val chain = List.tabulate(depth) { i =>\n Module (new AsyncResetRegVec(w, init)).suggestName(s\"${name}_${i}\")\n }\n\n chain.last.io.d := io.d\n chain.last.io.en := true.B\n\n (chain.init zip chain.tail).foreach { case (sink, source) =>\n sink.io.d := source.io.q\n sink.io.en := true.B\n }\n io.q := chain.head.io.q\n}\n\nobject AsyncResetShiftReg {\n def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =\n AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)\n\n def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =\n apply(in, depth, 0, name)\n\n def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =\n apply(in, depth, init.litValue.toInt, name)\n\n def apply [T <: Data](in: T, depth: Int, init: T): T =\n apply (in, depth, init.litValue.toInt, None)\n}\nFile AsyncQueue.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3._\nimport chisel3.util._\n\ncase class AsyncQueueParams(\n depth: Int = 8,\n sync: Int = 3,\n safe: Boolean = true,\n// If safe is true, then effort is made to resynchronize the crossing indices when either side is reset.\n// This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty.\n narrow: Boolean = false)\n// If narrow is true then the read mux is moved to the source side of the crossing.\n// This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing,\n// at the expense of a combinational path from the sink to the source and back to the sink.\n{\n require (depth > 0 && isPow2(depth))\n require (sync >= 2)\n\n val bits = log2Ceil(depth)\n val wires = if (narrow) 1 else depth\n}\n\nobject AsyncQueueParams {\n // When there is only one entry, we don't need narrow.\n def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false)\n}\n\nclass AsyncBundleSafety extends Bundle {\n val ridx_valid = Input (Bool())\n val widx_valid = Output(Bool())\n val source_reset_n = Output(Bool())\n val sink_reset_n = Input (Bool())\n}\n\nclass AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle {\n // Data-path synchronization\n val mem = Output(Vec(params.wires, gen))\n val ridx = Input (UInt((params.bits+1).W))\n val widx = Output(UInt((params.bits+1).W))\n val index = params.narrow.option(Input(UInt(params.bits.W)))\n\n // Signals used to self-stabilize a safe AsyncQueue\n val safe = params.safe.option(new AsyncBundleSafety)\n}\n\nobject GrayCounter {\n def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = \"binary\"): UInt = {\n val incremented = Wire(UInt(bits.W))\n val binary = RegNext(next=incremented, init=0.U).suggestName(name)\n incremented := Mux(clear, 0.U, binary + increment.asUInt)\n incremented ^ (incremented >> 1)\n }\n}\n\nclass AsyncValidSync(sync: Int, desc: String) extends RawModule {\n val io = IO(new Bundle {\n val in = Input(Bool())\n val out = Output(Bool())\n })\n val clock = IO(Input(Clock()))\n val reset = IO(Input(AsyncReset()))\n withClockAndReset(clock, reset){\n io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc))\n }\n}\n\nclass AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {\n override def desiredName = s\"AsyncQueueSource_${gen.typeName}\"\n\n val io = IO(new Bundle {\n // These come from the source domain\n val enq = Flipped(Decoupled(gen))\n // These cross to the sink clock domain\n val async = new AsyncBundle(gen, params)\n })\n\n val bits = params.bits\n val sink_ready = WireInit(true.B)\n val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all.\n val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, \"widx_bin\"))\n val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some(\"ridx_gray\"))\n val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U)\n\n val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1))\n when (io.enq.fire) { mem(index) := io.enq.bits }\n\n val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName(\"ready_reg\"))\n io.enq.ready := ready_reg && sink_ready\n\n val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName(\"widx_gray\"))\n io.async.widx := widx_reg\n\n io.async.index match {\n case Some(index) => io.async.mem(0) := mem(index)\n case None => io.async.mem := mem\n }\n\n io.async.safe.foreach { sio =>\n val source_valid_0 = Module(new AsyncValidSync(params.sync, \"source_valid_0\"))\n val source_valid_1 = Module(new AsyncValidSync(params.sync, \"source_valid_1\"))\n\n val sink_extend = Module(new AsyncValidSync(params.sync, \"sink_extend\"))\n val sink_valid = Module(new AsyncValidSync(params.sync, \"sink_valid\"))\n source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset\n source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset\n sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset\n sink_valid .reset := reset.asAsyncReset\n\n source_valid_0.clock := clock\n source_valid_1.clock := clock\n sink_extend .clock := clock\n sink_valid .clock := clock\n\n source_valid_0.io.in := true.B\n source_valid_1.io.in := source_valid_0.io.out\n sio.widx_valid := source_valid_1.io.out\n sink_extend.io.in := sio.ridx_valid\n sink_valid.io.in := sink_extend.io.out\n sink_ready := sink_valid.io.out\n sio.source_reset_n := !reset.asBool\n\n // Assert that if there is stuff in the queue, then reset cannot happen\n // Impossible to write because dequeue can occur on the receiving side,\n // then reset allowed to happen, but write side cannot know that dequeue\n // occurred.\n // TODO: write some sort of sanity check assertion for users\n // that denote don't reset when there is activity\n // assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, \"Enqueue while sink is reset and AsyncQueueSource is unprotected\")\n // assert (!reset_rise || prev_idx_match.asBool, \"Sink reset while AsyncQueueSource not empty\")\n }\n}\n\nclass AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {\n override def desiredName = s\"AsyncQueueSink_${gen.typeName}\"\n\n val io = IO(new Bundle {\n // These come from the sink domain\n val deq = Decoupled(gen)\n // These cross to the source clock domain\n val async = Flipped(new AsyncBundle(gen, params))\n })\n\n val bits = params.bits\n val source_ready = WireInit(true.B)\n val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, \"ridx_bin\"))\n val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some(\"widx_gray\"))\n val valid = source_ready && ridx =/= widx\n\n // The mux is safe because timing analysis ensures ridx has reached the register\n // On an ASIC, changes to the unread location cannot affect the selected value\n // On an FPGA, only one input changes at a time => mem updates don't cause glitches\n // The register only latches when the selected valued is not being written\n val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1))\n io.async.index.foreach { _ := index }\n // This register does not NEED to be reset, as its contents will not\n // be considered unless the asynchronously reset deq valid register is set.\n // It is possible that bits latches when the source domain is reset / has power cut\n // This is safe, because isolation gates brought mem low before the zeroed widx reached us\n val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index)\n io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some(\"deq_bits_reg\"))\n\n val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName(\"valid_reg\"))\n io.deq.valid := valid_reg && source_ready\n\n val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName(\"ridx_gray\"))\n io.async.ridx := ridx_reg\n\n io.async.safe.foreach { sio =>\n val sink_valid_0 = Module(new AsyncValidSync(params.sync, \"sink_valid_0\"))\n val sink_valid_1 = Module(new AsyncValidSync(params.sync, \"sink_valid_1\"))\n\n val source_extend = Module(new AsyncValidSync(params.sync, \"source_extend\"))\n val source_valid = Module(new AsyncValidSync(params.sync, \"source_valid\"))\n sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset\n sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset\n source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset\n source_valid .reset := reset.asAsyncReset\n\n sink_valid_0 .clock := clock\n sink_valid_1 .clock := clock\n source_extend.clock := clock\n source_valid .clock := clock\n\n sink_valid_0.io.in := true.B\n sink_valid_1.io.in := sink_valid_0.io.out\n sio.ridx_valid := sink_valid_1.io.out\n source_extend.io.in := sio.widx_valid\n source_valid.io.in := source_extend.io.out\n source_ready := source_valid.io.out\n sio.sink_reset_n := !reset.asBool\n\n // TODO: write some sort of sanity check assertion for users\n // that denote don't reset when there is activity\n // \n // val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool\n // val reset_and_extend_prev = RegNext(reset_and_extend, true.B)\n // val reset_rise = !reset_and_extend_prev && reset_and_extend\n // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0)\n // assert (!reset_rise || prev_idx_match.asBool, \"Source reset while AsyncQueueSink not empty\")\n }\n}\n\nobject FromAsyncBundle\n{\n // Sometimes it makes sense for the sink to have different sync than the source\n def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync)\n def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = {\n val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync)))\n sink.io.async <> x\n sink.io.deq\n }\n}\n\nobject ToAsyncBundle\n{\n def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = {\n val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params))\n source.io.enq <> x\n source.io.async\n }\n}\n\nclass AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] {\n val io = IO(new CrossingIO(gen))\n val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) }\n val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) }\n\n source.io.enq <> io.enq\n io.deq <> sink.io.deq\n sink.io.async <> source.io.async\n}\n"},"response":{"kind":"string","value":"module AsyncValidSync_161(\t// @[AsyncQueue.scala:58:7]\n input io_in,\t// @[AsyncQueue.scala:59:14]\n output io_out,\t// @[AsyncQueue.scala:59:14]\n input clock,\t// @[AsyncQueue.scala:63:17]\n input reset\t// @[AsyncQueue.scala:64:17]\n);\n\n wire io_in_0 = io_in;\t// @[AsyncQueue.scala:58:7]\n wire _io_out_WIRE;\t// @[ShiftReg.scala:48:24]\n wire io_out_0;\t// @[AsyncQueue.scala:58:7]\n assign io_out_0 = _io_out_WIRE;\t// @[ShiftReg.scala:48:24]\n AsyncResetSynchronizerShiftReg_w1_d3_i0_178 io_out_source_valid_1 (\t// @[ShiftReg.scala:45:23]\n .clock (clock),\n .reset (reset),\n .io_d (io_in_0),\t// @[AsyncQueue.scala:58:7]\n .io_q (_io_out_WIRE)\n );\t// @[ShiftReg.scala:45:23]\n assign io_out = io_out_0;\t// @[AsyncQueue.scala:58:7]\nendmodule"}}},{"rowIdx":584,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to the following Chisel files.\nFile DivSqrtRecFN_small.scala:\n/*============================================================================\n\nThis Chisel source file is part of a pre-release version of the HardFloat IEEE\nFloating-Point Arithmetic Package, by John R. Hauser (with some contributions\nfrom Yunsup Lee and Andrew Waterman, mainly concerning testing).\n\nCopyright 2017 SiFive, Inc. All rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions, and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright notice,\n this list of conditions, and the following disclaimer in the documentation\n and/or other materials provided with the distribution.\n\n 3. Neither the name of SiFive nor the names of its contributors may\n be used to endorse or promote products derived from this software without\n specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY SIFIVE AND CONTRIBUTORS \"AS IS\", AND ANY\nEXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\nWARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE\nDISCLAIMED. IN NO EVENT SHALL SIFIVE OR CONTRIBUTORS BE LIABLE FOR ANY\nDIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\nLOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\nON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\nSOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n=============================================================================*/\n\n\n\n\n/*\n\ns = sigWidth\nc_i = newBit\n\nDivision:\nwidth of a is (s+2)\n\nNormal\n------\n\n(qi + ci * 2^(-i))*b <= a\nq0 = 0\nr0 = a\n\nq(i+1) = qi + ci*2^(-i)\nri = a - qi*b\nr(i+1) = a - q(i+1)*b\n = a - qi*b - ci*2^(-i)*b\nr(i+1) = ri - ci*2^(-i)*b\nci = ri >= 2^(-i)*b\nsummary_i = ri != 0\n\ni = 0 to s+1\n\n(s+1)th bit plus summary_(i+1) gives enough information for rounding\nIf (a < b), then we need to calculate (s+2)th bit and summary_(i+1)\nbecause we need s bits ignoring the leading zero. (This is skipCycle2\npart of Hauser's code.)\n\nHauser\n------\nsig_i = qi\nrem_i = 2^(i-2)*ri\ncycle_i = s+3-i\n\nsig_0 = 0\nrem_0 = a/4\ncycle_0 = s+3\nbit_0 = 2^0 (= 2^(s+1), since we represent a, b and q with (s+2) bits)\n\nsig(i+1) = sig(i) + ci*bit_i\nrem(i+1) = 2rem_i - ci*b/2\nci = 2rem_i >= b/2\nbit_i = 2^-i (=2^(cycle_i-2), since we represent a, b and q with (s+2) bits)\ncycle(i+1) = cycle_i-1\nsummary_1 = a <> b\nsummary(i+1) = if ci then 2rem_i-b/2 <> 0 else summary_i, i <> 0\n\nProof:\n2^i*r(i+1) = 2^i*ri - ci*b. Qed\n\nci = 2^i*ri >= b. Qed\n\nsummary(i+1) = if ci then rem(i+1) else summary_i, i <> 0\nNow, note that all of ck's cannot be 0, since that means\na is 0. So when you traverse through a chain of 0 ck's,\nfrom the end,\neventually, you reach a non-zero cj. That is exactly the\nvalue of ri as the reminder remains the same. When all ck's\nare 0 except c0 (which must be 1) then summary_1 is set\ncorrectly according\nto r1 = a-b != 0. So summary(i+1) is always set correctly\naccording to r(i+1)\n\n\n\nSquare root:\nwidth of a is (s+1)\n\nNormal\n------\n(xi + ci*2^(-i))^2 <= a\nxi^2 + ci*2^(-i)*(2xi+ci*2^(-i)) <= a\n\nx0 = 0\nx(i+1) = xi + ci*2^(-i)\nri = a - xi^2\nr(i+1) = a - x(i+1)^2\n = a - (xi^2 + ci*2^(-i)*(2xi+ci*2^(-i)))\n = ri - ci*2^(-i)*(2xi+ci*2^(-i))\n = ri - ci*2^(-i)*(2xi+2^(-i)) // ci is always 0 or 1\nci = ri >= 2^(-i)*(2xi + 2^(-i))\nsummary_i = ri != 0\n\n\ni = 0 to s+1\n\nFor odd expression, do 2 steps initially.\n\n(s+1)th bit plus summary_(i+1) gives enough information for rounding.\n\nHauser\n------\n\nsig_i = xi\nrem_i = ri*2^(i-1)\ncycle_i = s+2-i\nbit_i = 2^(-i) (= 2^(s-i) = 2^(cycle_i-2) in terms of bit representation)\n\nsig_0 = 0\nrem_0 = a/2\ncycle_0 = s+2\nbit_0 = 1 (= 2^s in terms of bit representation)\n\nsig(i+1) = sig_i + ci * bit_i\nrem(i+1) = 2rem_i - ci*(2sig_i + bit_i)\nci = 2*sig_i + bit_i <= 2*rem_i\nbit_i = 2^(cycle_i-2) (in terms of bit representation)\ncycle(i+1) = cycle_i-1\nsummary_1 = a - (2^s) (in terms of bit representation) \nsummary(i+1) = if ci then rem(i+1) <> 0 else summary_i, i <> 0\n\n\nProof:\nci = 2*sig_i + bit_i <= 2*rem_i\nci = 2xi + 2^(-i) <= ri*2^i. Qed\n\nsig(i+1) = sig_i + ci * bit_i\nx(i+1) = xi + ci*2^(-i). Qed\n\nrem(i+1) = 2rem_i - ci*(2sig_i + bit_i)\nr(i+1)*2^i = ri*2^i - ci*(2xi + 2^(-i))\nr(i+1) = ri - ci*2^(-i)*(2xi + 2^(-i)). Qed\n\nSame argument as before for summary.\n\n\n------------------------------\nNote that all registers are updated normally until cycle == 2.\nAt cycle == 2, rem is not updated, but all other registers are updated normally.\nBut, cycle == 1 does not read rem to calculate anything (note that final summary\nis calculated using the values at cycle = 2).\n\n*/\n\n\n\n\n\n\n\n\n\n\n\npackage hardfloat\n\nimport chisel3._\nimport chisel3.util._\nimport consts._\n\n/*----------------------------------------------------------------------------\n| Computes a division or square root for floating-point in recoded form.\n| Multiple clock cycles are needed for each division or square-root operation,\n| except possibly in special cases.\n*----------------------------------------------------------------------------*/\n\nclass\n DivSqrtRawFN_small(expWidth: Int, sigWidth: Int, options: Int)\n extends Module\n{\n override def desiredName = s\"DivSqrtRawFN_small_e${expWidth}_s${sigWidth}\"\n val io = IO(new Bundle {\n /*--------------------------------------------------------------------\n *--------------------------------------------------------------------*/\n val inReady = Output(Bool())\n val inValid = Input(Bool())\n val sqrtOp = Input(Bool())\n val a = Input(new RawFloat(expWidth, sigWidth))\n val b = Input(new RawFloat(expWidth, sigWidth))\n val roundingMode = Input(UInt(3.W))\n /*--------------------------------------------------------------------\n *--------------------------------------------------------------------*/\n val rawOutValid_div = Output(Bool())\n val rawOutValid_sqrt = Output(Bool())\n val roundingModeOut = Output(UInt(3.W))\n val invalidExc = Output(Bool())\n val infiniteExc = Output(Bool())\n val rawOut = Output(new RawFloat(expWidth, sigWidth + 2))\n })\n\n /*------------------------------------------------------------------------\n *------------------------------------------------------------------------*/\n val cycleNum = RegInit(0.U(log2Ceil(sigWidth + 3).W))\n val inReady = RegInit(true.B) // <-> (cycleNum <= 1)\n val rawOutValid = RegInit(false.B) // <-> (cycleNum === 1)\n\n val sqrtOp_Z = Reg(Bool())\n val majorExc_Z = Reg(Bool())\n//*** REDUCE 3 BITS TO 2-BIT CODE:\n val isNaN_Z = Reg(Bool())\n val isInf_Z = Reg(Bool())\n val isZero_Z = Reg(Bool())\n val sign_Z = Reg(Bool())\n val sExp_Z = Reg(SInt((expWidth + 2).W))\n val fractB_Z = Reg(UInt(sigWidth.W))\n val roundingMode_Z = Reg(UInt(3.W))\n\n /*------------------------------------------------------------------------\n | (The most-significant and least-significant bits of 'rem_Z' are needed\n | only for square roots.)\n *------------------------------------------------------------------------*/\n val rem_Z = Reg(UInt((sigWidth + 2).W))\n val notZeroRem_Z = Reg(Bool())\n val sigX_Z = Reg(UInt((sigWidth + 2).W))\n\n /*------------------------------------------------------------------------\n *------------------------------------------------------------------------*/\n val rawA_S = io.a\n val rawB_S = io.b\n\n//*** IMPROVE THESE:\n val notSigNaNIn_invalidExc_S_div =\n (rawA_S.isZero && rawB_S.isZero) || (rawA_S.isInf && rawB_S.isInf)\n val notSigNaNIn_invalidExc_S_sqrt =\n ! rawA_S.isNaN && ! rawA_S.isZero && rawA_S.sign\n val majorExc_S =\n Mux(io.sqrtOp,\n isSigNaNRawFloat(rawA_S) || notSigNaNIn_invalidExc_S_sqrt,\n isSigNaNRawFloat(rawA_S) || isSigNaNRawFloat(rawB_S) ||\n notSigNaNIn_invalidExc_S_div ||\n (! rawA_S.isNaN && ! rawA_S.isInf && rawB_S.isZero)\n )\n val isNaN_S =\n Mux(io.sqrtOp,\n rawA_S.isNaN || notSigNaNIn_invalidExc_S_sqrt,\n rawA_S.isNaN || rawB_S.isNaN || notSigNaNIn_invalidExc_S_div\n )\n val isInf_S = Mux(io.sqrtOp, rawA_S.isInf, rawA_S.isInf || rawB_S.isZero)\n val isZero_S = Mux(io.sqrtOp, rawA_S.isZero, rawA_S.isZero || rawB_S.isInf)\n val sign_S = rawA_S.sign ^ (! io.sqrtOp && rawB_S.sign)\n\n val specialCaseA_S = rawA_S.isNaN || rawA_S.isInf || rawA_S.isZero\n val specialCaseB_S = rawB_S.isNaN || rawB_S.isInf || rawB_S.isZero\n val normalCase_S_div = ! specialCaseA_S && ! specialCaseB_S\n val normalCase_S_sqrt = ! specialCaseA_S && ! rawA_S.sign\n val normalCase_S = Mux(io.sqrtOp, normalCase_S_sqrt, normalCase_S_div)\n\n val sExpQuot_S_div =\n rawA_S.sExp +&\n Cat(rawB_S.sExp(expWidth), ~rawB_S.sExp(expWidth - 1, 0)).asSInt\n//*** IS THIS OPTIMAL?:\n val sSatExpQuot_S_div =\n Cat(Mux(((BigInt(7)<<(expWidth - 2)).S <= sExpQuot_S_div),\n 6.U,\n sExpQuot_S_div(expWidth + 1, expWidth - 2)\n ),\n sExpQuot_S_div(expWidth - 3, 0)\n ).asSInt\n\n val evenSqrt_S = io.sqrtOp && ! rawA_S.sExp(0)\n val oddSqrt_S = io.sqrtOp && rawA_S.sExp(0)\n\n /*------------------------------------------------------------------------\n *------------------------------------------------------------------------*/\n val idle = cycleNum === 0.U\n val entering = inReady && io.inValid\n val entering_normalCase = entering && normalCase_S\n\n val processTwoBits = cycleNum >= 3.U && ((options & divSqrtOpt_twoBitsPerCycle) != 0).B\n val skipCycle2 = cycleNum === 3.U && sigX_Z(sigWidth + 1) && ((options & divSqrtOpt_twoBitsPerCycle) == 0).B\n\n when (! idle || entering) {\n def computeCycleNum(f: UInt => UInt): UInt = {\n Mux(entering & ! normalCase_S, f(1.U), 0.U) |\n Mux(entering_normalCase,\n Mux(io.sqrtOp,\n Mux(rawA_S.sExp(0), f(sigWidth.U), f((sigWidth + 1).U)),\n f((sigWidth + 2).U)\n ),\n 0.U\n ) |\n Mux(! entering && ! skipCycle2, f(cycleNum - Mux(processTwoBits, 2.U, 1.U)), 0.U) |\n Mux(skipCycle2, f(1.U), 0.U)\n }\n\n inReady := computeCycleNum(_ <= 1.U).asBool\n rawOutValid := computeCycleNum(_ === 1.U).asBool\n cycleNum := computeCycleNum(x => x)\n }\n\n io.inReady := inReady\n\n /*------------------------------------------------------------------------\n *------------------------------------------------------------------------*/\n when (entering) {\n sqrtOp_Z := io.sqrtOp\n majorExc_Z := majorExc_S\n isNaN_Z := isNaN_S\n isInf_Z := isInf_S\n isZero_Z := isZero_S\n sign_Z := sign_S\n sExp_Z :=\n Mux(io.sqrtOp,\n (rawA_S.sExp>>1) +& (BigInt(1)<<(expWidth - 1)).S,\n sSatExpQuot_S_div\n )\n roundingMode_Z := io.roundingMode\n }\n when (entering || ! inReady && sqrtOp_Z) {\n fractB_Z :=\n Mux(inReady && ! io.sqrtOp, rawB_S.sig(sigWidth - 2, 0)<<1, 0.U) |\n Mux(inReady && io.sqrtOp && rawA_S.sExp(0), (BigInt(1)<<(sigWidth - 2)).U, 0.U) |\n Mux(inReady && io.sqrtOp && ! rawA_S.sExp(0), (BigInt(1)<<(sigWidth - 1)).U, 0.U) |\n Mux(! inReady /* sqrtOp_Z */ && processTwoBits, fractB_Z>>2, 0.U) |\n Mux(! inReady /* sqrtOp_Z */ && ! processTwoBits, fractB_Z>>1, 0.U)\n }\n\n /*------------------------------------------------------------------------\n *------------------------------------------------------------------------*/\n val rem =\n Mux(inReady && ! oddSqrt_S, rawA_S.sig<<1, 0.U) |\n Mux(inReady && oddSqrt_S,\n Cat(rawA_S.sig(sigWidth - 1, sigWidth - 2) - 1.U,\n rawA_S.sig(sigWidth - 3, 0)<<3\n ),\n 0.U\n ) |\n Mux(! inReady, rem_Z<<1, 0.U)\n val bitMask = (1.U<>2\n val trialTerm =\n Mux(inReady && ! io.sqrtOp, rawB_S.sig<<1, 0.U) |\n Mux(inReady && evenSqrt_S, (BigInt(1)<>1 | sigX_Z<<1, fractB_Z | (1.U << sigWidth))\n val trialTerm2_newBit1 = trialTerm2_newBit0 | Mux(sqrtOp_Z, fractB_Z<<1, 0.U)\n val trialRem2 =\n Mux(newBit,\n (trialRem<<1) - trialTerm2_newBit1.zext,\n (rem_Z<<2)(sigWidth+2, 0).zext - trialTerm2_newBit0.zext)\n val newBit2 = (0.S <= trialRem2)\n val nextNotZeroRem_Z = Mux(inReady || newBit, trialRem =/= 0.S, notZeroRem_Z)\n val nextNotZeroRem_Z_2 = // <-> Mux(newBit2, trialRem2 =/= 0.S, nextNotZeroRem_Z)\n processTwoBits && newBit && (0.S < (trialRem<<1) - trialTerm2_newBit1.zext) ||\n processTwoBits && !newBit && (0.S < (rem_Z<<2)(sigWidth+2, 0).zext - trialTerm2_newBit0.zext) ||\n !(processTwoBits && newBit2) && nextNotZeroRem_Z\n val nextRem_Z_2 =\n Mux(processTwoBits && newBit2, trialRem2.asUInt(sigWidth + 1, 0), 0.U) |\n Mux(processTwoBits && !newBit2, rem2(sigWidth + 1, 0), 0.U) |\n Mux(!processTwoBits, nextRem_Z, 0.U)\n\n when (entering || ! inReady) {\n notZeroRem_Z := nextNotZeroRem_Z_2\n rem_Z := nextRem_Z_2\n sigX_Z :=\n Mux(inReady && ! io.sqrtOp, newBit<<(sigWidth + 1), 0.U) |\n Mux(inReady && io.sqrtOp, (BigInt(1)<>1, 0.U)\n }\n\n /*------------------------------------------------------------------------\n *------------------------------------------------------------------------*/\n io.rawOutValid_div := rawOutValid && ! sqrtOp_Z\n io.rawOutValid_sqrt := rawOutValid && sqrtOp_Z\n io.roundingModeOut := roundingMode_Z\n io.invalidExc := majorExc_Z && isNaN_Z\n io.infiniteExc := majorExc_Z && ! isNaN_Z\n io.rawOut.isNaN := isNaN_Z\n io.rawOut.isInf := isInf_Z\n io.rawOut.isZero := isZero_Z\n io.rawOut.sign := sign_Z\n io.rawOut.sExp := sExp_Z\n io.rawOut.sig := sigX_Z<<1 | notZeroRem_Z\n\n}\n\n/*----------------------------------------------------------------------------\n*----------------------------------------------------------------------------*/\n\nclass\n DivSqrtRecFNToRaw_small(expWidth: Int, sigWidth: Int, options: Int)\n extends Module\n{\n override def desiredName = s\"DivSqrtRecFMToRaw_small_e${expWidth}_s${sigWidth}\"\n val io = IO(new Bundle {\n /*--------------------------------------------------------------------\n *--------------------------------------------------------------------*/\n val inReady = Output(Bool())\n val inValid = Input(Bool())\n val sqrtOp = Input(Bool())\n val a = Input(UInt((expWidth + sigWidth + 1).W))\n val b = Input(UInt((expWidth + sigWidth + 1).W))\n val roundingMode = Input(UInt(3.W))\n /*--------------------------------------------------------------------\n *--------------------------------------------------------------------*/\n val rawOutValid_div = Output(Bool())\n val rawOutValid_sqrt = Output(Bool())\n val roundingModeOut = Output(UInt(3.W))\n val invalidExc = Output(Bool())\n val infiniteExc = Output(Bool())\n val rawOut = Output(new RawFloat(expWidth, sigWidth + 2))\n })\n\n val divSqrtRawFN =\n Module(new DivSqrtRawFN_small(expWidth, sigWidth, options))\n\n io.inReady := divSqrtRawFN.io.inReady\n divSqrtRawFN.io.inValid := io.inValid\n divSqrtRawFN.io.sqrtOp := io.sqrtOp\n divSqrtRawFN.io.a := rawFloatFromRecFN(expWidth, sigWidth, io.a)\n divSqrtRawFN.io.b := rawFloatFromRecFN(expWidth, sigWidth, io.b)\n divSqrtRawFN.io.roundingMode := io.roundingMode\n\n io.rawOutValid_div := divSqrtRawFN.io.rawOutValid_div\n io.rawOutValid_sqrt := divSqrtRawFN.io.rawOutValid_sqrt\n io.roundingModeOut := divSqrtRawFN.io.roundingModeOut\n io.invalidExc := divSqrtRawFN.io.invalidExc\n io.infiniteExc := divSqrtRawFN.io.infiniteExc\n io.rawOut := divSqrtRawFN.io.rawOut\n\n}\n\n/*----------------------------------------------------------------------------\n*----------------------------------------------------------------------------*/\n\nclass\n DivSqrtRecFN_small(expWidth: Int, sigWidth: Int, options: Int)\n extends Module\n{\n override def desiredName = s\"DivSqrtRecFM_small_e${expWidth}_s${sigWidth}\"\n val io = IO(new Bundle {\n /*--------------------------------------------------------------------\n *--------------------------------------------------------------------*/\n val inReady = Output(Bool())\n val inValid = Input(Bool())\n val sqrtOp = Input(Bool())\n val a = Input(UInt((expWidth + sigWidth + 1).W))\n val b = Input(UInt((expWidth + sigWidth + 1).W))\n val roundingMode = Input(UInt(3.W))\n val detectTininess = Input(UInt(1.W))\n /*--------------------------------------------------------------------\n *--------------------------------------------------------------------*/\n val outValid_div = Output(Bool())\n val outValid_sqrt = Output(Bool())\n val out = Output(UInt((expWidth + sigWidth + 1).W))\n val exceptionFlags = Output(UInt(5.W))\n })\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val divSqrtRecFNToRaw =\n Module(new DivSqrtRecFNToRaw_small(expWidth, sigWidth, options))\n\n io.inReady := divSqrtRecFNToRaw.io.inReady\n divSqrtRecFNToRaw.io.inValid := io.inValid\n divSqrtRecFNToRaw.io.sqrtOp := io.sqrtOp\n divSqrtRecFNToRaw.io.a := io.a\n divSqrtRecFNToRaw.io.b := io.b\n divSqrtRecFNToRaw.io.roundingMode := io.roundingMode\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n io.outValid_div := divSqrtRecFNToRaw.io.rawOutValid_div\n io.outValid_sqrt := divSqrtRecFNToRaw.io.rawOutValid_sqrt\n\n val roundRawFNToRecFN =\n Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0))\n roundRawFNToRecFN.io.invalidExc := divSqrtRecFNToRaw.io.invalidExc\n roundRawFNToRecFN.io.infiniteExc := divSqrtRecFNToRaw.io.infiniteExc\n roundRawFNToRecFN.io.in := divSqrtRecFNToRaw.io.rawOut\n roundRawFNToRecFN.io.roundingMode := divSqrtRecFNToRaw.io.roundingModeOut\n roundRawFNToRecFN.io.detectTininess := io.detectTininess\n io.out := roundRawFNToRecFN.io.out\n io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags\n\n}\n"},"response":{"kind":"string","value":"module DivSqrtRecFM_small_e5_s11_2(\t// @[DivSqrtRecFN_small.scala:468:5]\n input clock,\t// @[DivSqrtRecFN_small.scala:468:5]\n input reset,\t// @[DivSqrtRecFN_small.scala:468:5]\n output io_inReady,\t// @[DivSqrtRecFN_small.scala:472:16]\n input io_inValid,\t// @[DivSqrtRecFN_small.scala:472:16]\n input io_sqrtOp,\t// @[DivSqrtRecFN_small.scala:472:16]\n input [16:0] io_a,\t// @[DivSqrtRecFN_small.scala:472:16]\n input [16:0] io_b,\t// @[DivSqrtRecFN_small.scala:472:16]\n input [2:0] io_roundingMode,\t// @[DivSqrtRecFN_small.scala:472:16]\n output io_outValid_div,\t// @[DivSqrtRecFN_small.scala:472:16]\n output io_outValid_sqrt,\t// @[DivSqrtRecFN_small.scala:472:16]\n output [16:0] io_out,\t// @[DivSqrtRecFN_small.scala:472:16]\n output [4:0] io_exceptionFlags\t// @[DivSqrtRecFN_small.scala:472:16]\n);\n\n wire [2:0] _divSqrtRecFNToRaw_io_roundingModeOut;\t// @[DivSqrtRecFN_small.scala:493:15]\n wire _divSqrtRecFNToRaw_io_invalidExc;\t// @[DivSqrtRecFN_small.scala:493:15]\n wire _divSqrtRecFNToRaw_io_infiniteExc;\t// @[DivSqrtRecFN_small.scala:493:15]\n wire _divSqrtRecFNToRaw_io_rawOut_isNaN;\t// @[DivSqrtRecFN_small.scala:493:15]\n wire _divSqrtRecFNToRaw_io_rawOut_isInf;\t// @[DivSqrtRecFN_small.scala:493:15]\n wire _divSqrtRecFNToRaw_io_rawOut_isZero;\t// @[DivSqrtRecFN_small.scala:493:15]\n wire _divSqrtRecFNToRaw_io_rawOut_sign;\t// @[DivSqrtRecFN_small.scala:493:15]\n wire [6:0] _divSqrtRecFNToRaw_io_rawOut_sExp;\t// @[DivSqrtRecFN_small.scala:493:15]\n wire [13:0] _divSqrtRecFNToRaw_io_rawOut_sig;\t// @[DivSqrtRecFN_small.scala:493:15]\n wire io_inValid_0 = io_inValid;\t// @[DivSqrtRecFN_small.scala:468:5]\n wire io_sqrtOp_0 = io_sqrtOp;\t// @[DivSqrtRecFN_small.scala:468:5]\n wire [16:0] io_a_0 = io_a;\t// @[DivSqrtRecFN_small.scala:468:5]\n wire [16:0] io_b_0 = io_b;\t// @[DivSqrtRecFN_small.scala:468:5]\n wire [2:0] io_roundingMode_0 = io_roundingMode;\t// @[DivSqrtRecFN_small.scala:468:5]\n wire io_detectTininess = 1'h1;\t// @[DivSqrtRecFN_small.scala:468:5, :472:16, :508:15]\n wire io_inReady_0;\t// @[DivSqrtRecFN_small.scala:468:5]\n wire io_outValid_div_0;\t// @[DivSqrtRecFN_small.scala:468:5]\n wire io_outValid_sqrt_0;\t// @[DivSqrtRecFN_small.scala:468:5]\n wire [16:0] io_out_0;\t// @[DivSqrtRecFN_small.scala:468:5]\n wire [4:0] io_exceptionFlags_0;\t// @[DivSqrtRecFN_small.scala:468:5]\n DivSqrtRecFMToRaw_small_e5_s11_2 divSqrtRecFNToRaw (\t// @[DivSqrtRecFN_small.scala:493:15]\n .clock (clock),\n .reset (reset),\n .io_inReady (io_inReady_0),\n .io_inValid (io_inValid_0),\t// @[DivSqrtRecFN_small.scala:468:5]\n .io_sqrtOp (io_sqrtOp_0),\t// @[DivSqrtRecFN_small.scala:468:5]\n .io_a (io_a_0),\t// @[DivSqrtRecFN_small.scala:468:5]\n .io_b (io_b_0),\t// @[DivSqrtRecFN_small.scala:468:5]\n .io_roundingMode (io_roundingMode_0),\t// @[DivSqrtRecFN_small.scala:468:5]\n .io_rawOutValid_div (io_outValid_div_0),\n .io_rawOutValid_sqrt (io_outValid_sqrt_0),\n .io_roundingModeOut (_divSqrtRecFNToRaw_io_roundingModeOut),\n .io_invalidExc (_divSqrtRecFNToRaw_io_invalidExc),\n .io_infiniteExc (_divSqrtRecFNToRaw_io_infiniteExc),\n .io_rawOut_isNaN (_divSqrtRecFNToRaw_io_rawOut_isNaN),\n .io_rawOut_isInf (_divSqrtRecFNToRaw_io_rawOut_isInf),\n .io_rawOut_isZero (_divSqrtRecFNToRaw_io_rawOut_isZero),\n .io_rawOut_sign (_divSqrtRecFNToRaw_io_rawOut_sign),\n .io_rawOut_sExp (_divSqrtRecFNToRaw_io_rawOut_sExp),\n .io_rawOut_sig (_divSqrtRecFNToRaw_io_rawOut_sig)\n );\t// @[DivSqrtRecFN_small.scala:493:15]\n RoundRawFNToRecFN_e5_s11_5 roundRawFNToRecFN (\t// @[DivSqrtRecFN_small.scala:508:15]\n .io_invalidExc (_divSqrtRecFNToRaw_io_invalidExc),\t// @[DivSqrtRecFN_small.scala:493:15]\n .io_infiniteExc (_divSqrtRecFNToRaw_io_infiniteExc),\t// @[DivSqrtRecFN_small.scala:493:15]\n .io_in_isNaN (_divSqrtRecFNToRaw_io_rawOut_isNaN),\t// @[DivSqrtRecFN_small.scala:493:15]\n .io_in_isInf (_divSqrtRecFNToRaw_io_rawOut_isInf),\t// @[DivSqrtRecFN_small.scala:493:15]\n .io_in_isZero (_divSqrtRecFNToRaw_io_rawOut_isZero),\t// @[DivSqrtRecFN_small.scala:493:15]\n .io_in_sign (_divSqrtRecFNToRaw_io_rawOut_sign),\t// @[DivSqrtRecFN_small.scala:493:15]\n .io_in_sExp (_divSqrtRecFNToRaw_io_rawOut_sExp),\t// @[DivSqrtRecFN_small.scala:493:15]\n .io_in_sig (_divSqrtRecFNToRaw_io_rawOut_sig),\t// @[DivSqrtRecFN_small.scala:493:15]\n .io_roundingMode (_divSqrtRecFNToRaw_io_roundingModeOut),\t// @[DivSqrtRecFN_small.scala:493:15]\n .io_out (io_out_0),\n .io_exceptionFlags (io_exceptionFlags_0)\n );\t// @[DivSqrtRecFN_small.scala:508:15]\n assign io_inReady = io_inReady_0;\t// @[DivSqrtRecFN_small.scala:468:5]\n assign io_outValid_div = io_outValid_div_0;\t// @[DivSqrtRecFN_small.scala:468:5]\n assign io_outValid_sqrt = io_outValid_sqrt_0;\t// @[DivSqrtRecFN_small.scala:468:5]\n assign io_out = io_out_0;\t// @[DivSqrtRecFN_small.scala:468:5]\n assign io_exceptionFlags = io_exceptionFlags_0;\t// @[DivSqrtRecFN_small.scala:468:5]\nendmodule"}}},{"rowIdx":585,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to the following Chisel files.\nFile Multiplier.scala:\n// See LICENSE.Berkeley for license details.\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.rocket\n\nimport chisel3._\nimport chisel3.util.{Cat, log2Up, log2Ceil, log2Floor, Log2, Decoupled, Enum, Fill, Valid, Pipe}\nimport freechips.rocketchip.util._\n\nimport ALU._\n\nclass MultiplierReq(dataBits: Int, tagBits: Int) extends Bundle {\n val fn = Bits(SZ_ALU_FN.W)\n val dw = Bits(SZ_DW.W)\n val in1 = Bits(dataBits.W)\n val in2 = Bits(dataBits.W)\n val tag = UInt(tagBits.W)\n}\n\nclass MultiplierResp(dataBits: Int, tagBits: Int) extends Bundle {\n val data = Bits(dataBits.W)\n val full_data = Bits((2*dataBits).W)\n val tag = UInt(tagBits.W)\n}\n\nclass MultiplierIO(val dataBits: Int, val tagBits: Int) extends Bundle {\n val req = Flipped(Decoupled(new MultiplierReq(dataBits, tagBits)))\n val kill = Input(Bool())\n val resp = Decoupled(new MultiplierResp(dataBits, tagBits))\n}\n\ncase class MulDivParams(\n mulUnroll: Int = 1,\n divUnroll: Int = 1,\n mulEarlyOut: Boolean = false,\n divEarlyOut: Boolean = false,\n divEarlyOutGranularity: Int = 1\n)\n\nclass MulDiv(cfg: MulDivParams, width: Int, nXpr: Int = 32) extends Module {\n private def minDivLatency = (cfg.divUnroll > 0).option(if (cfg.divEarlyOut) 3 else 1 + w/cfg.divUnroll)\n private def minMulLatency = (cfg.mulUnroll > 0).option(if (cfg.mulEarlyOut) 2 else w/cfg.mulUnroll)\n def minLatency: Int = (minDivLatency ++ minMulLatency).min\n\n val io = IO(new MultiplierIO(width, log2Up(nXpr)))\n val w = io.req.bits.in1.getWidth\n val mulw = if (cfg.mulUnroll == 0) w else (w + cfg.mulUnroll - 1) / cfg.mulUnroll * cfg.mulUnroll\n val fastMulW = if (cfg.mulUnroll == 0) false else w/2 > cfg.mulUnroll && w % (2*cfg.mulUnroll) == 0\n \n val s_ready :: s_neg_inputs :: s_mul :: s_div :: s_dummy :: s_neg_output :: s_done_mul :: s_done_div :: Nil = Enum(8)\n val state = RegInit(s_ready)\n \n val req = Reg(chiselTypeOf(io.req.bits))\n val count = Reg(UInt(log2Ceil(\n ((cfg.divUnroll != 0).option(w/cfg.divUnroll + 1).toSeq ++\n (cfg.mulUnroll != 0).option(mulw/cfg.mulUnroll)).reduce(_ max _)).W))\n val neg_out = Reg(Bool())\n val isHi = Reg(Bool())\n val resHi = Reg(Bool())\n val divisor = Reg(Bits((w+1).W)) // div only needs w bits\n val remainder = Reg(Bits((2*mulw+2).W)) // div only needs 2*w+1 bits\n\n val mulDecode = List(\n FN_MUL -> List(Y, N, X, X),\n FN_MULH -> List(Y, Y, Y, Y),\n FN_MULHU -> List(Y, Y, N, N),\n FN_MULHSU -> List(Y, Y, Y, N))\n val divDecode = List(\n FN_DIV -> List(N, N, Y, Y),\n FN_REM -> List(N, Y, Y, Y),\n FN_DIVU -> List(N, N, N, N),\n FN_REMU -> List(N, Y, N, N))\n val cmdMul :: cmdHi :: lhsSigned :: rhsSigned :: Nil =\n DecodeLogic(io.req.bits.fn, List(X, X, X, X),\n (if (cfg.divUnroll != 0) divDecode else Nil) ++ (if (cfg.mulUnroll != 0) mulDecode else Nil)).map(_.asBool)\n\n require(w == 32 || w == 64)\n def halfWidth(req: MultiplierReq) = (w > 32).B && req.dw === DW_32\n\n def sext(x: Bits, halfW: Bool, signed: Bool) = {\n val sign = signed && Mux(halfW, x(w/2-1), x(w-1))\n val hi = Mux(halfW, Fill(w/2, sign), x(w-1,w/2))\n (Cat(hi, x(w/2-1,0)), sign)\n }\n val (lhs_in, lhs_sign) = sext(io.req.bits.in1, halfWidth(io.req.bits), lhsSigned)\n val (rhs_in, rhs_sign) = sext(io.req.bits.in2, halfWidth(io.req.bits), rhsSigned)\n \n val subtractor = remainder(2*w,w) - divisor\n val result = Mux(resHi, remainder(2*w, w+1), remainder(w-1, 0))\n val negated_remainder = -result\n\n if (cfg.divUnroll != 0) when (state === s_neg_inputs) {\n when (remainder(w-1)) {\n remainder := negated_remainder\n }\n when (divisor(w-1)) {\n divisor := subtractor\n }\n state := s_div\n }\n if (cfg.divUnroll != 0) when (state === s_neg_output) {\n remainder := negated_remainder\n state := s_done_div\n resHi := false.B\n }\n if (cfg.mulUnroll != 0) when (state === s_mul) {\n val mulReg = Cat(remainder(2*mulw+1,w+1),remainder(w-1,0))\n val mplierSign = remainder(w)\n val mplier = mulReg(mulw-1,0)\n val accum = mulReg(2*mulw,mulw).asSInt\n val mpcand = divisor.asSInt\n val prod = Cat(mplierSign, mplier(cfg.mulUnroll-1, 0)).asSInt * mpcand + accum\n val nextMulReg = Cat(prod, mplier(mulw-1, cfg.mulUnroll))\n val nextMplierSign = count === (mulw/cfg.mulUnroll-2).U && neg_out\n\n val eOutMask = ((BigInt(-1) << mulw).S >> (count * cfg.mulUnroll.U)(log2Up(mulw)-1,0))(mulw-1,0)\n val eOut = (cfg.mulEarlyOut).B && count =/= (mulw/cfg.mulUnroll-1).U && count =/= 0.U &&\n !isHi && (mplier & ~eOutMask) === 0.U\n val eOutRes = (mulReg >> (mulw.U - count * cfg.mulUnroll.U)(log2Up(mulw)-1,0))\n val nextMulReg1 = Cat(nextMulReg(2*mulw,mulw), Mux(eOut, eOutRes, nextMulReg)(mulw-1,0))\n remainder := Cat(nextMulReg1 >> w, nextMplierSign, nextMulReg1(w-1,0))\n\n count := count + 1.U\n when (eOut || count === (mulw/cfg.mulUnroll-1).U) {\n state := s_done_mul\n resHi := isHi\n }\n }\n if (cfg.divUnroll != 0) when (state === s_div) {\n val unrolls = ((0 until cfg.divUnroll) scanLeft remainder) { case (rem, i) =>\n // the special case for iteration 0 is to save HW, not for correctness\n val difference = if (i == 0) subtractor else rem(2*w,w) - divisor(w-1,0)\n val less = difference(w)\n Cat(Mux(less, rem(2*w-1,w), difference(w-1,0)), rem(w-1,0), !less)\n }.tail\n\n remainder := unrolls.last\n when (count === (w/cfg.divUnroll).U) {\n state := Mux(neg_out, s_neg_output, s_done_div)\n resHi := isHi\n if (w % cfg.divUnroll < cfg.divUnroll - 1)\n remainder := unrolls(w % cfg.divUnroll)\n }\n count := count + 1.U\n\n val divby0 = count === 0.U && !subtractor(w)\n if (cfg.divEarlyOut) {\n val align = 1 << log2Floor(cfg.divUnroll max cfg.divEarlyOutGranularity)\n val alignMask = ~((align-1).U(log2Ceil(w).W))\n val divisorMSB = Log2(divisor(w-1,0), w) & alignMask\n val dividendMSB = Log2(remainder(w-1,0), w) | ~alignMask\n val eOutPos = ~(dividendMSB - divisorMSB)\n val eOut = count === 0.U && !divby0 && eOutPos >= align.U\n when (eOut) {\n remainder := remainder(w-1,0) << eOutPos\n count := eOutPos >> log2Floor(cfg.divUnroll)\n }\n }\n when (divby0 && !isHi) { neg_out := false.B }\n }\n when (io.resp.fire || io.kill) {\n state := s_ready\n }\n when (io.req.fire) {\n state := Mux(cmdMul, s_mul, Mux(lhs_sign || rhs_sign, s_neg_inputs, s_div))\n isHi := cmdHi\n resHi := false.B\n count := (if (fastMulW) Mux[UInt](cmdMul && halfWidth(io.req.bits), (w/cfg.mulUnroll/2).U, 0.U) else 0.U)\n neg_out := Mux(cmdHi, lhs_sign, lhs_sign =/= rhs_sign)\n divisor := Cat(rhs_sign, rhs_in)\n remainder := lhs_in\n req := io.req.bits\n }\n\n val outMul = (state & (s_done_mul ^ s_done_div)) === (s_done_mul & ~s_done_div)\n val loOut = Mux(fastMulW.B && halfWidth(req) && outMul, result(w-1,w/2), result(w/2-1,0))\n val hiOut = Mux(halfWidth(req), Fill(w/2, loOut(w/2-1)), result(w-1,w/2))\n io.resp.bits.tag := req.tag\n\n io.resp.bits.data := Cat(hiOut, loOut)\n io.resp.bits.full_data := Cat(remainder(2*w, w+1), remainder(w-1, 0))\n io.resp.valid := (state === s_done_mul || state === s_done_div)\n io.req.ready := state === s_ready\n}\n\nclass PipelinedMultiplier(width: Int, latency: Int, nXpr: Int = 32) extends Module with ShouldBeRetimed {\n val io = IO(new Bundle {\n val req = Flipped(Valid(new MultiplierReq(width, log2Ceil(nXpr))))\n val resp = Valid(new MultiplierResp(width, log2Ceil(nXpr)))\n })\n\n val in = Pipe(io.req)\n\n val decode = List(\n FN_MUL -> List(N, X, X),\n FN_MULH -> List(Y, Y, Y),\n FN_MULHU -> List(Y, N, N),\n FN_MULHSU -> List(Y, Y, N))\n val cmdHi :: lhsSigned :: rhsSigned :: Nil =\n DecodeLogic(in.bits.fn, List(X, X, X), decode).map(_.asBool)\n val cmdHalf = (width > 32).B && in.bits.dw === DW_32\n\n val lhs = Cat(lhsSigned && in.bits.in1(width-1), in.bits.in1).asSInt\n val rhs = Cat(rhsSigned && in.bits.in2(width-1), in.bits.in2).asSInt\n val prod = lhs * rhs\n val muxed = Mux(cmdHi, prod(2*width-1, width), Mux(cmdHalf, prod(width/2-1, 0).sextTo(width), prod(width-1, 0)))\n\n val resp = Pipe(in, latency-1)\n io.resp.valid := resp.valid\n io.resp.bits.tag := resp.bits.tag\n io.resp.bits.data := Pipe(in.valid, muxed, latency-1).bits\n io.resp.bits.full_data := Pipe(in.valid, prod, latency-1).bits.asUInt\n}\n"},"response":{"kind":"string","value":"module MulDiv(\t// @[Multiplier.scala:40:7]\n input clock,\t// @[Multiplier.scala:40:7]\n input reset,\t// @[Multiplier.scala:40:7]\n output io_req_ready,\t// @[Multiplier.scala:45:14]\n input io_req_valid,\t// @[Multiplier.scala:45:14]\n input [4:0] io_req_bits_fn,\t// @[Multiplier.scala:45:14]\n input io_req_bits_dw,\t// @[Multiplier.scala:45:14]\n input [63:0] io_req_bits_in1,\t// @[Multiplier.scala:45:14]\n input [63:0] io_req_bits_in2,\t// @[Multiplier.scala:45:14]\n input io_kill,\t// @[Multiplier.scala:45:14]\n input io_resp_ready,\t// @[Multiplier.scala:45:14]\n output io_resp_valid,\t// @[Multiplier.scala:45:14]\n output [63:0] io_resp_bits_data\t// @[Multiplier.scala:45:14]\n);\n\n wire io_req_valid_0 = io_req_valid;\t// @[Multiplier.scala:40:7]\n wire [4:0] io_req_bits_fn_0 = io_req_bits_fn;\t// @[Multiplier.scala:40:7]\n wire io_req_bits_dw_0 = io_req_bits_dw;\t// @[Multiplier.scala:40:7]\n wire [63:0] io_req_bits_in1_0 = io_req_bits_in1;\t// @[Multiplier.scala:40:7]\n wire [63:0] io_req_bits_in2_0 = io_req_bits_in2;\t// @[Multiplier.scala:40:7]\n wire io_kill_0 = io_kill;\t// @[Multiplier.scala:40:7]\n wire io_resp_ready_0 = io_resp_ready;\t// @[Multiplier.scala:40:7]\n wire _eOut_T_1 = 1'h0;\t// @[Multiplier.scala:117:36]\n wire _eOut_T_3 = 1'h0;\t// @[Multiplier.scala:117:74]\n wire _eOut_T_5 = 1'h0;\t// @[Multiplier.scala:117:91]\n wire eOut = 1'h0;\t// @[Multiplier.scala:118:13]\n wire [5:0] alignMask = 6'h3F;\t// @[Multiplier.scala:149:23]\n wire [5:0] _dividendMSB_T_111 = 6'h0;\t// @[Multiplier.scala:151:53]\n wire [2:0] _outMul_T = 3'h1;\t// @[Multiplier.scala:175:37]\n wire [2:0] _outMul_T_2 = 3'h0;\t// @[Multiplier.scala:175:70]\n wire [2:0] _outMul_T_3 = 3'h0;\t// @[Multiplier.scala:175:68]\n wire [4:0] io_req_bits_tag = 5'h0;\t// @[Multiplier.scala:40:7]\n wire [4:0] io_resp_bits_tag = 5'h0;\t// @[Multiplier.scala:40:7]\n wire _io_req_ready_T;\t// @[Multiplier.scala:183:25]\n wire _io_resp_valid_T_2;\t// @[Multiplier.scala:182:42]\n wire [63:0] _io_resp_bits_data_T;\t// @[Multiplier.scala:180:27]\n wire [127:0] _io_resp_bits_full_data_T_2;\t// @[Multiplier.scala:181:32]\n wire io_req_ready_0;\t// @[Multiplier.scala:40:7]\n wire [63:0] io_resp_bits_data_0;\t// @[Multiplier.scala:40:7]\n wire [127:0] io_resp_bits_full_data;\t// @[Multiplier.scala:40:7]\n wire io_resp_valid_0;\t// @[Multiplier.scala:40:7]\n reg [2:0] state;\t// @[Multiplier.scala:51:22]\n reg [4:0] req_fn;\t// @[Multiplier.scala:53:16]\n reg req_dw;\t// @[Multiplier.scala:53:16]\n reg [63:0] req_in1;\t// @[Multiplier.scala:53:16]\n reg [63:0] req_in2;\t// @[Multiplier.scala:53:16]\n reg [6:0] count;\t// @[Multiplier.scala:54:18]\n reg neg_out;\t// @[Multiplier.scala:57:20]\n reg isHi;\t// @[Multiplier.scala:58:17]\n reg resHi;\t// @[Multiplier.scala:59:18]\n reg [64:0] divisor;\t// @[Multiplier.scala:60:20]\n wire [64:0] mpcand = divisor;\t// @[Multiplier.scala:60:20, :111:26]\n reg [129:0] remainder;\t// @[Multiplier.scala:61:22]\n wire [2:0] decoded_plaInput;\t// @[pla.scala:77:22]\n wire [2:0] decoded_invInputs = ~decoded_plaInput;\t// @[pla.scala:77:22, :78:21]\n wire [3:0] decoded_invMatrixOutputs;\t// @[pla.scala:120:37]\n wire [3:0] decoded;\t// @[pla.scala:81:23]\n wire decoded_andMatrixOutputs_andMatrixInput_0 = decoded_invInputs[0];\t// @[pla.scala:78:21, :91:29]\n wire decoded_andMatrixOutputs_andMatrixInput_0_5 = decoded_invInputs[0];\t// @[pla.scala:78:21, :91:29]\n wire decoded_andMatrixOutputs_3_2 = decoded_andMatrixOutputs_andMatrixInput_0;\t// @[pla.scala:91:29, :98:70]\n wire decoded_andMatrixOutputs_andMatrixInput_0_1 = decoded_invInputs[2];\t// @[pla.scala:78:21, :91:29]\n wire decoded_andMatrixOutputs_andMatrixInput_1 = decoded_invInputs[2];\t// @[pla.scala:78:21, :91:29]\n wire decoded_andMatrixOutputs_andMatrixInput_1_1 = decoded_invInputs[2];\t// @[pla.scala:78:21, :91:29]\n wire decoded_andMatrixOutputs_4_2 = decoded_andMatrixOutputs_andMatrixInput_0_1;\t// @[pla.scala:91:29, :98:70]\n wire _decoded_orMatrixOutputs_T_6 = decoded_andMatrixOutputs_4_2;\t// @[pla.scala:98:70, :114:36]\n wire decoded_andMatrixOutputs_andMatrixInput_0_2 = decoded_invInputs[1];\t// @[pla.scala:78:21, :91:29]\n wire [1:0] _decoded_andMatrixOutputs_T = {decoded_andMatrixOutputs_andMatrixInput_0_2, decoded_andMatrixOutputs_andMatrixInput_1};\t// @[pla.scala:91:29, :98:53]\n wire decoded_andMatrixOutputs_2_2 = &_decoded_andMatrixOutputs_T;\t// @[pla.scala:98:{53,70}]\n wire decoded_andMatrixOutputs_andMatrixInput_0_3 = decoded_plaInput[0];\t// @[pla.scala:77:22, :90:45]\n wire [1:0] _decoded_andMatrixOutputs_T_1 = {decoded_andMatrixOutputs_andMatrixInput_0_3, decoded_andMatrixOutputs_andMatrixInput_1_1};\t// @[pla.scala:90:45, :91:29, :98:53]\n wire decoded_andMatrixOutputs_0_2 = &_decoded_andMatrixOutputs_T_1;\t// @[pla.scala:98:{53,70}]\n wire decoded_andMatrixOutputs_andMatrixInput_0_4 = decoded_plaInput[1];\t// @[pla.scala:77:22, :90:45]\n wire decoded_andMatrixOutputs_1_2 = decoded_andMatrixOutputs_andMatrixInput_0_4;\t// @[pla.scala:90:45, :98:70]\n wire decoded_andMatrixOutputs_andMatrixInput_1_2 = decoded_plaInput[2];\t// @[pla.scala:77:22, :90:45]\n wire [1:0] _decoded_andMatrixOutputs_T_2 = {decoded_andMatrixOutputs_andMatrixInput_0_5, decoded_andMatrixOutputs_andMatrixInput_1_2};\t// @[pla.scala:90:45, :91:29, :98:53]\n wire decoded_andMatrixOutputs_5_2 = &_decoded_andMatrixOutputs_T_2;\t// @[pla.scala:98:{53,70}]\n wire [1:0] _decoded_orMatrixOutputs_T = {decoded_andMatrixOutputs_2_2, decoded_andMatrixOutputs_5_2};\t// @[pla.scala:98:70, :114:19]\n wire _decoded_orMatrixOutputs_T_1 = |_decoded_orMatrixOutputs_T;\t// @[pla.scala:114:{19,36}]\n wire [1:0] _decoded_orMatrixOutputs_T_2 = {decoded_andMatrixOutputs_3_2, decoded_andMatrixOutputs_2_2};\t// @[pla.scala:98:70, :114:19]\n wire _decoded_orMatrixOutputs_T_3 = |_decoded_orMatrixOutputs_T_2;\t// @[pla.scala:114:{19,36}]\n wire [1:0] _decoded_orMatrixOutputs_T_4 = {decoded_andMatrixOutputs_0_2, decoded_andMatrixOutputs_1_2};\t// @[pla.scala:98:70, :114:19]\n wire _decoded_orMatrixOutputs_T_5 = |_decoded_orMatrixOutputs_T_4;\t// @[pla.scala:114:{19,36}]\n wire [1:0] decoded_orMatrixOutputs_lo = {_decoded_orMatrixOutputs_T_3, _decoded_orMatrixOutputs_T_1};\t// @[pla.scala:102:36, :114:36]\n wire [1:0] decoded_orMatrixOutputs_hi = {_decoded_orMatrixOutputs_T_6, _decoded_orMatrixOutputs_T_5};\t// @[pla.scala:102:36, :114:36]\n wire [3:0] decoded_orMatrixOutputs = {decoded_orMatrixOutputs_hi, decoded_orMatrixOutputs_lo};\t// @[pla.scala:102:36]\n wire _decoded_invMatrixOutputs_T = decoded_orMatrixOutputs[0];\t// @[pla.scala:102:36, :124:31]\n wire _decoded_invMatrixOutputs_T_1 = decoded_orMatrixOutputs[1];\t// @[pla.scala:102:36, :124:31]\n wire _decoded_invMatrixOutputs_T_2 = decoded_orMatrixOutputs[2];\t// @[pla.scala:102:36, :124:31]\n wire _decoded_invMatrixOutputs_T_3 = decoded_orMatrixOutputs[3];\t// @[pla.scala:102:36, :124:31]\n wire [1:0] decoded_invMatrixOutputs_lo = {_decoded_invMatrixOutputs_T_1, _decoded_invMatrixOutputs_T};\t// @[pla.scala:120:37, :124:31]\n wire [1:0] decoded_invMatrixOutputs_hi = {_decoded_invMatrixOutputs_T_3, _decoded_invMatrixOutputs_T_2};\t// @[pla.scala:120:37, :124:31]\n assign decoded_invMatrixOutputs = {decoded_invMatrixOutputs_hi, decoded_invMatrixOutputs_lo};\t// @[pla.scala:120:37]\n assign decoded = decoded_invMatrixOutputs;\t// @[pla.scala:81:23, :120:37]\n assign decoded_plaInput = io_req_bits_fn_0[2:0];\t// @[pla.scala:77:22]\n wire cmdMul = decoded[3];\t// @[pla.scala:81:23]\n wire cmdHi = decoded[2];\t// @[pla.scala:81:23]\n wire lhsSigned = decoded[1];\t// @[pla.scala:81:23]\n wire rhsSigned = decoded[0];\t// @[pla.scala:81:23]\n wire _count_T_5 = ~io_req_bits_dw_0;\t// @[Multiplier.scala:40:7, :78:60]\n wire _sign_T = io_req_bits_in1_0[31];\t// @[Multiplier.scala:40:7, :81:38]\n wire _sign_T_1 = io_req_bits_in1_0[63];\t// @[Multiplier.scala:40:7, :81:48]\n wire _sign_T_2 = io_req_bits_dw_0 ? _sign_T_1 : _sign_T;\t// @[Multiplier.scala:40:7, :81:{29,38,48}]\n wire lhs_sign = lhsSigned & _sign_T_2;\t// @[Multiplier.scala:75:107, :81:{23,29}]\n wire [31:0] _hi_T = {32{lhs_sign}};\t// @[Multiplier.scala:81:23, :82:29]\n wire [31:0] _hi_T_1 = io_req_bits_in1_0[63:32];\t// @[Multiplier.scala:40:7, :82:43]\n wire [31:0] hi = io_req_bits_dw_0 ? _hi_T_1 : _hi_T;\t// @[Multiplier.scala:40:7, :82:{17,29,43}]\n wire [63:0] lhs_in = {hi, io_req_bits_in1_0[31:0]};\t// @[Multiplier.scala:40:7, :82:17, :83:{9,15}]\n wire _sign_T_3 = io_req_bits_in2_0[31];\t// @[Multiplier.scala:40:7, :81:38]\n wire _sign_T_4 = io_req_bits_in2_0[63];\t// @[Multiplier.scala:40:7, :81:48]\n wire _sign_T_5 = io_req_bits_dw_0 ? _sign_T_4 : _sign_T_3;\t// @[Multiplier.scala:40:7, :81:{29,38,48}]\n wire rhs_sign = rhsSigned & _sign_T_5;\t// @[Multiplier.scala:75:107, :81:{23,29}]\n wire [31:0] _hi_T_2 = {32{rhs_sign}};\t// @[Multiplier.scala:81:23, :82:29]\n wire [31:0] _hi_T_3 = io_req_bits_in2_0[63:32];\t// @[Multiplier.scala:40:7, :82:43]\n wire [31:0] hi_1 = io_req_bits_dw_0 ? _hi_T_3 : _hi_T_2;\t// @[Multiplier.scala:40:7, :82:{17,29,43}]\n wire [63:0] rhs_in = {hi_1, io_req_bits_in2_0[31:0]};\t// @[Multiplier.scala:40:7, :82:17, :83:{9,15}]\n wire [64:0] _subtractor_T = remainder[128:64];\t// @[Multiplier.scala:61:22, :88:29]\n wire [65:0] _subtractor_T_1 = {1'h0, _subtractor_T} - {1'h0, divisor};\t// @[Multiplier.scala:60:20, :88:{29,37}]\n wire [64:0] subtractor = _subtractor_T_1[64:0];\t// @[Multiplier.scala:88:37]\n wire [63:0] _result_T = remainder[128:65];\t// @[Multiplier.scala:61:22, :89:36]\n wire [63:0] _io_resp_bits_full_data_T = remainder[128:65];\t// @[Multiplier.scala:61:22, :89:36, :181:42]\n wire [63:0] _result_T_1 = remainder[63:0];\t// @[Multiplier.scala:61:22, :89:57]\n wire [63:0] _mulReg_T_1 = remainder[63:0];\t// @[Multiplier.scala:61:22, :89:57, :107:55]\n wire [63:0] _unrolls_T_3 = remainder[63:0];\t// @[Multiplier.scala:61:22, :89:57, :134:58]\n wire [63:0] _dividendMSB_T = remainder[63:0];\t// @[Multiplier.scala:61:22, :89:57, :151:39]\n wire [63:0] _remainder_T_3 = remainder[63:0];\t// @[Multiplier.scala:61:22, :89:57, :155:31]\n wire [63:0] _io_resp_bits_full_data_T_1 = remainder[63:0];\t// @[Multiplier.scala:61:22, :89:57, :181:63]\n wire [63:0] result = resHi ? _result_T : _result_T_1;\t// @[Multiplier.scala:59:18, :89:{19,36,57}]\n wire [64:0] _negated_remainder_T = 65'h0 - {1'h0, result};\t// @[Multiplier.scala:89:19, :90:27]\n wire [63:0] negated_remainder = _negated_remainder_T[63:0];\t// @[Multiplier.scala:90:27]\n wire [64:0] _mulReg_T = remainder[129:65];\t// @[Multiplier.scala:61:22, :107:31]\n wire [128:0] mulReg = {_mulReg_T, _mulReg_T_1};\t// @[Multiplier.scala:107:{21,31,55}]\n wire mplierSign = remainder[64];\t// @[Multiplier.scala:61:22, :108:31]\n wire [63:0] mplier = mulReg[63:0];\t// @[Multiplier.scala:107:21, :109:24]\n wire [64:0] _accum_T = mulReg[128:64];\t// @[Multiplier.scala:107:21, :110:23]\n wire [64:0] accum = _accum_T;\t// @[Multiplier.scala:110:{23,37}]\n wire _prod_T = mplier[0];\t// @[Multiplier.scala:109:24, :112:38]\n wire [1:0] _prod_T_1 = {mplierSign, _prod_T};\t// @[Multiplier.scala:108:31, :112:{19,38}]\n wire [1:0] _prod_T_2 = _prod_T_1;\t// @[Multiplier.scala:112:{19,60}]\n wire [66:0] _prod_T_3 = {{65{_prod_T_2[1]}}, _prod_T_2} * {{2{mpcand[64]}}, mpcand};\t// @[Multiplier.scala:111:26, :112:{60,67}]\n wire [67:0] _prod_T_4 = {_prod_T_3[66], _prod_T_3} + {{3{accum[64]}}, accum};\t// @[Multiplier.scala:110:37, :112:{67,76}]\n wire [66:0] _prod_T_5 = _prod_T_4[66:0];\t// @[Multiplier.scala:112:76]\n wire [66:0] prod = _prod_T_5;\t// @[Multiplier.scala:112:76]\n wire [66:0] nextMulReg_hi = prod;\t// @[Multiplier.scala:112:76, :113:25]\n wire [62:0] _nextMulReg_T = mplier[63:1];\t// @[Multiplier.scala:109:24, :113:38]\n wire [129:0] nextMulReg = {nextMulReg_hi, _nextMulReg_T};\t// @[Multiplier.scala:113:{25,38}]\n wire [129:0] _nextMulReg1_T_1 = nextMulReg;\t// @[Multiplier.scala:113:25, :120:55]\n wire _nextMplierSign_T = count == 7'h3E;\t// @[Multiplier.scala:54:18, :114:32]\n wire nextMplierSign = _nextMplierSign_T & neg_out;\t// @[Multiplier.scala:57:20, :114:{32,61}]\n wire [7:0] _GEN = {1'h0, count};\t// @[Multiplier.scala:54:18, :116:54]\n wire [7:0] _eOutMask_T;\t// @[Multiplier.scala:116:54]\n assign _eOutMask_T = _GEN;\t// @[Multiplier.scala:116:54]\n wire [7:0] _eOutRes_T;\t// @[Multiplier.scala:119:46]\n assign _eOutRes_T = _GEN;\t// @[Multiplier.scala:116:54, :119:46]\n wire [5:0] _eOutMask_T_1 = _eOutMask_T[5:0];\t// @[Multiplier.scala:116:{54,72}]\n wire [64:0] _eOutMask_T_2 = $signed(65'sh10000000000000000 >>> _eOutMask_T_1);\t// @[Multiplier.scala:116:{44,72}]\n wire [63:0] eOutMask = _eOutMask_T_2[63:0];\t// @[Multiplier.scala:116:{44,91}]\n wire _eOut_T = count != 7'h3F;\t// @[Multiplier.scala:54:18, :117:45]\n wire _eOut_T_2 = |count;\t// @[Multiplier.scala:54:18, :117:83]\n wire _eOut_T_4 = ~isHi;\t// @[Multiplier.scala:58:17, :118:7]\n wire [63:0] _eOut_T_6 = ~eOutMask;\t// @[Multiplier.scala:116:91, :118:26]\n wire [63:0] _eOut_T_7 = mplier & _eOut_T_6;\t// @[Multiplier.scala:109:24, :118:{24,26}]\n wire _eOut_T_8 = _eOut_T_7 == 64'h0;\t// @[Multiplier.scala:118:{24,37}]\n wire [8:0] _eOutRes_T_1 = 9'h40 - {1'h0, _eOutRes_T};\t// @[Multiplier.scala:119:{38,46}]\n wire [7:0] _eOutRes_T_2 = _eOutRes_T_1[7:0];\t// @[Multiplier.scala:119:38]\n wire [5:0] _eOutRes_T_3 = _eOutRes_T_2[5:0];\t// @[Multiplier.scala:119:{38,64}]\n wire [128:0] eOutRes = mulReg >> _eOutRes_T_3;\t// @[Multiplier.scala:107:21, :119:{27,64}]\n wire [64:0] _nextMulReg1_T = nextMulReg[128:64];\t// @[Multiplier.scala:113:25, :120:37]\n wire [63:0] _nextMulReg1_T_2 = _nextMulReg1_T_1[63:0];\t// @[Multiplier.scala:120:{55,82}]\n wire [128:0] nextMulReg1 = {_nextMulReg1_T, _nextMulReg1_T_2};\t// @[Multiplier.scala:120:{26,37,82}]\n wire [64:0] _remainder_T = nextMulReg1[128:64];\t// @[Multiplier.scala:120:26, :121:34]\n wire [63:0] _remainder_T_1 = nextMulReg1[63:0];\t// @[Multiplier.scala:120:26, :121:67]\n wire [65:0] remainder_hi = {_remainder_T, nextMplierSign};\t// @[Multiplier.scala:114:61, :121:{21,34}]\n wire [129:0] _remainder_T_2 = {remainder_hi, _remainder_T_1};\t// @[Multiplier.scala:121:{21,67}]\n wire [7:0] _GEN_0 = _GEN + 8'h1;\t// @[Multiplier.scala:116:54, :123:20]\n wire [7:0] _count_T;\t// @[Multiplier.scala:123:20]\n assign _count_T = _GEN_0;\t// @[Multiplier.scala:123:20]\n wire [7:0] _count_T_2;\t// @[Multiplier.scala:144:20]\n assign _count_T_2 = _GEN_0;\t// @[Multiplier.scala:123:20, :144:20]\n wire [6:0] _count_T_1 = _count_T[6:0];\t// @[Multiplier.scala:123:20]\n wire unrolls_less = subtractor[64];\t// @[Multiplier.scala:88:37, :133:28]\n wire _divby0_T_1 = subtractor[64];\t// @[Multiplier.scala:88:37, :133:28, :146:46]\n wire [63:0] _unrolls_T = remainder[127:64];\t// @[Multiplier.scala:61:22, :134:24]\n wire [63:0] _unrolls_T_1 = subtractor[63:0];\t// @[Multiplier.scala:88:37, :134:45]\n wire [63:0] _unrolls_T_2 = unrolls_less ? _unrolls_T : _unrolls_T_1;\t// @[Multiplier.scala:133:28, :134:{14,24,45}]\n wire _unrolls_T_4 = ~unrolls_less;\t// @[Multiplier.scala:133:28, :134:67]\n wire [127:0] unrolls_hi = {_unrolls_T_2, _unrolls_T_3};\t// @[Multiplier.scala:134:{10,14,58}]\n wire [128:0] unrolls_0 = {unrolls_hi, _unrolls_T_4};\t// @[Multiplier.scala:134:{10,67}]\n wire [2:0] _state_T = {1'h1, ~neg_out, 1'h1};\t// @[Multiplier.scala:57:20, :139:19]\n wire [6:0] _count_T_3 = _count_T_2[6:0];\t// @[Multiplier.scala:144:20]\n wire _divby0_T = ~(|count);\t// @[Multiplier.scala:54:18, :117:83, :146:24]\n wire _divby0_T_2 = ~_divby0_T_1;\t// @[Multiplier.scala:146:{35,46}]\n wire divby0 = _divby0_T & _divby0_T_2;\t// @[Multiplier.scala:146:{24,32,35}]\n wire [63:0] _divisorMSB_T = divisor[63:0];\t// @[Multiplier.scala:60:20, :150:36]\n wire [31:0] divisorMSB_hi = _divisorMSB_T[63:32];\t// @[CircuitMath.scala:33:17]\n wire [31:0] divisorMSB_lo = _divisorMSB_T[31:0];\t// @[CircuitMath.scala:34:17]\n wire divisorMSB_useHi = |divisorMSB_hi;\t// @[CircuitMath.scala:33:17, :35:22]\n wire [15:0] divisorMSB_hi_1 = divisorMSB_hi[31:16];\t// @[CircuitMath.scala:33:17]\n wire [15:0] divisorMSB_lo_1 = divisorMSB_hi[15:0];\t// @[CircuitMath.scala:33:17, :34:17]\n wire divisorMSB_useHi_1 = |divisorMSB_hi_1;\t// @[CircuitMath.scala:33:17, :35:22]\n wire [7:0] divisorMSB_hi_2 = divisorMSB_hi_1[15:8];\t// @[CircuitMath.scala:33:17]\n wire [7:0] divisorMSB_lo_2 = divisorMSB_hi_1[7:0];\t// @[CircuitMath.scala:33:17, :34:17]\n wire divisorMSB_useHi_2 = |divisorMSB_hi_2;\t// @[CircuitMath.scala:33:17, :35:22]\n wire [3:0] divisorMSB_hi_3 = divisorMSB_hi_2[7:4];\t// @[CircuitMath.scala:33:17]\n wire [3:0] divisorMSB_lo_3 = divisorMSB_hi_2[3:0];\t// @[CircuitMath.scala:33:17, :34:17]\n wire divisorMSB_useHi_3 = |divisorMSB_hi_3;\t// @[CircuitMath.scala:33:17, :35:22]\n wire _divisorMSB_T_1 = divisorMSB_hi_3[3];\t// @[CircuitMath.scala:30:12, :33:17]\n wire _divisorMSB_T_2 = divisorMSB_hi_3[2];\t// @[CircuitMath.scala:30:12, :33:17]\n wire _divisorMSB_T_3 = divisorMSB_hi_3[1];\t// @[CircuitMath.scala:28:8, :33:17]\n wire [1:0] _divisorMSB_T_4 = _divisorMSB_T_2 ? 2'h2 : {1'h0, _divisorMSB_T_3};\t// @[CircuitMath.scala:28:8, :30:{10,12}]\n wire [1:0] _divisorMSB_T_5 = _divisorMSB_T_1 ? 2'h3 : _divisorMSB_T_4;\t// @[CircuitMath.scala:30:{10,12}]\n wire _divisorMSB_T_6 = divisorMSB_lo_3[3];\t// @[CircuitMath.scala:30:12, :34:17]\n wire _divisorMSB_T_7 = divisorMSB_lo_3[2];\t// @[CircuitMath.scala:30:12, :34:17]\n wire _divisorMSB_T_8 = divisorMSB_lo_3[1];\t// @[CircuitMath.scala:28:8, :34:17]\n wire [1:0] _divisorMSB_T_9 = _divisorMSB_T_7 ? 2'h2 : {1'h0, _divisorMSB_T_8};\t// @[CircuitMath.scala:28:8, :30:{10,12}]\n wire [1:0] _divisorMSB_T_10 = _divisorMSB_T_6 ? 2'h3 : _divisorMSB_T_9;\t// @[CircuitMath.scala:30:{10,12}]\n wire [1:0] _divisorMSB_T_11 = divisorMSB_useHi_3 ? _divisorMSB_T_5 : _divisorMSB_T_10;\t// @[CircuitMath.scala:30:10, :35:22, :36:21]\n wire [2:0] _divisorMSB_T_12 = {divisorMSB_useHi_3, _divisorMSB_T_11};\t// @[CircuitMath.scala:35:22, :36:{10,21}]\n wire [3:0] divisorMSB_hi_4 = divisorMSB_lo_2[7:4];\t// @[CircuitMath.scala:33:17, :34:17]\n wire [3:0] divisorMSB_lo_4 = divisorMSB_lo_2[3:0];\t// @[CircuitMath.scala:34:17]\n wire divisorMSB_useHi_4 = |divisorMSB_hi_4;\t// @[CircuitMath.scala:33:17, :35:22]\n wire _divisorMSB_T_13 = divisorMSB_hi_4[3];\t// @[CircuitMath.scala:30:12, :33:17]\n wire _divisorMSB_T_14 = divisorMSB_hi_4[2];\t// @[CircuitMath.scala:30:12, :33:17]\n wire _divisorMSB_T_15 = divisorMSB_hi_4[1];\t// @[CircuitMath.scala:28:8, :33:17]\n wire [1:0] _divisorMSB_T_16 = _divisorMSB_T_14 ? 2'h2 : {1'h0, _divisorMSB_T_15};\t// @[CircuitMath.scala:28:8, :30:{10,12}]\n wire [1:0] _divisorMSB_T_17 = _divisorMSB_T_13 ? 2'h3 : _divisorMSB_T_16;\t// @[CircuitMath.scala:30:{10,12}]\n wire _divisorMSB_T_18 = divisorMSB_lo_4[3];\t// @[CircuitMath.scala:30:12, :34:17]\n wire _divisorMSB_T_19 = divisorMSB_lo_4[2];\t// @[CircuitMath.scala:30:12, :34:17]\n wire _divisorMSB_T_20 = divisorMSB_lo_4[1];\t// @[CircuitMath.scala:28:8, :34:17]\n wire [1:0] _divisorMSB_T_21 = _divisorMSB_T_19 ? 2'h2 : {1'h0, _divisorMSB_T_20};\t// @[CircuitMath.scala:28:8, :30:{10,12}]\n wire [1:0] _divisorMSB_T_22 = _divisorMSB_T_18 ? 2'h3 : _divisorMSB_T_21;\t// @[CircuitMath.scala:30:{10,12}]\n wire [1:0] _divisorMSB_T_23 = divisorMSB_useHi_4 ? _divisorMSB_T_17 : _divisorMSB_T_22;\t// @[CircuitMath.scala:30:10, :35:22, :36:21]\n wire [2:0] _divisorMSB_T_24 = {divisorMSB_useHi_4, _divisorMSB_T_23};\t// @[CircuitMath.scala:35:22, :36:{10,21}]\n wire [2:0] _divisorMSB_T_25 = divisorMSB_useHi_2 ? _divisorMSB_T_12 : _divisorMSB_T_24;\t// @[CircuitMath.scala:35:22, :36:{10,21}]\n wire [3:0] _divisorMSB_T_26 = {divisorMSB_useHi_2, _divisorMSB_T_25};\t// @[CircuitMath.scala:35:22, :36:{10,21}]\n wire [7:0] divisorMSB_hi_5 = divisorMSB_lo_1[15:8];\t// @[CircuitMath.scala:33:17, :34:17]\n wire [7:0] divisorMSB_lo_5 = divisorMSB_lo_1[7:0];\t// @[CircuitMath.scala:34:17]\n wire divisorMSB_useHi_5 = |divisorMSB_hi_5;\t// @[CircuitMath.scala:33:17, :35:22]\n wire [3:0] divisorMSB_hi_6 = divisorMSB_hi_5[7:4];\t// @[CircuitMath.scala:33:17]\n wire [3:0] divisorMSB_lo_6 = divisorMSB_hi_5[3:0];\t// @[CircuitMath.scala:33:17, :34:17]\n wire divisorMSB_useHi_6 = |divisorMSB_hi_6;\t// @[CircuitMath.scala:33:17, :35:22]\n wire _divisorMSB_T_27 = divisorMSB_hi_6[3];\t// @[CircuitMath.scala:30:12, :33:17]\n wire _divisorMSB_T_28 = divisorMSB_hi_6[2];\t// @[CircuitMath.scala:30:12, :33:17]\n wire _divisorMSB_T_29 = divisorMSB_hi_6[1];\t// @[CircuitMath.scala:28:8, :33:17]\n wire [1:0] _divisorMSB_T_30 = _divisorMSB_T_28 ? 2'h2 : {1'h0, _divisorMSB_T_29};\t// @[CircuitMath.scala:28:8, :30:{10,12}]\n wire [1:0] _divisorMSB_T_31 = _divisorMSB_T_27 ? 2'h3 : _divisorMSB_T_30;\t// @[CircuitMath.scala:30:{10,12}]\n wire _divisorMSB_T_32 = divisorMSB_lo_6[3];\t// @[CircuitMath.scala:30:12, :34:17]\n wire _divisorMSB_T_33 = divisorMSB_lo_6[2];\t// @[CircuitMath.scala:30:12, :34:17]\n wire _divisorMSB_T_34 = divisorMSB_lo_6[1];\t// @[CircuitMath.scala:28:8, :34:17]\n wire [1:0] _divisorMSB_T_35 = _divisorMSB_T_33 ? 2'h2 : {1'h0, _divisorMSB_T_34};\t// @[CircuitMath.scala:28:8, :30:{10,12}]\n wire [1:0] _divisorMSB_T_36 = _divisorMSB_T_32 ? 2'h3 : _divisorMSB_T_35;\t// @[CircuitMath.scala:30:{10,12}]\n wire [1:0] _divisorMSB_T_37 = divisorMSB_useHi_6 ? _divisorMSB_T_31 : _divisorMSB_T_36;\t// @[CircuitMath.scala:30:10, :35:22, :36:21]\n wire [2:0] _divisorMSB_T_38 = {divisorMSB_useHi_6, _divisorMSB_T_37};\t// @[CircuitMath.scala:35:22, :36:{10,21}]\n wire [3:0] divisorMSB_hi_7 = divisorMSB_lo_5[7:4];\t// @[CircuitMath.scala:33:17, :34:17]\n wire [3:0] divisorMSB_lo_7 = divisorMSB_lo_5[3:0];\t// @[CircuitMath.scala:34:17]\n wire divisorMSB_useHi_7 = |divisorMSB_hi_7;\t// @[CircuitMath.scala:33:17, :35:22]\n wire _divisorMSB_T_39 = divisorMSB_hi_7[3];\t// @[CircuitMath.scala:30:12, :33:17]\n wire _divisorMSB_T_40 = divisorMSB_hi_7[2];\t// @[CircuitMath.scala:30:12, :33:17]\n wire _divisorMSB_T_41 = divisorMSB_hi_7[1];\t// @[CircuitMath.scala:28:8, :33:17]\n wire [1:0] _divisorMSB_T_42 = _divisorMSB_T_40 ? 2'h2 : {1'h0, _divisorMSB_T_41};\t// @[CircuitMath.scala:28:8, :30:{10,12}]\n wire [1:0] _divisorMSB_T_43 = _divisorMSB_T_39 ? 2'h3 : _divisorMSB_T_42;\t// @[CircuitMath.scala:30:{10,12}]\n wire _divisorMSB_T_44 = divisorMSB_lo_7[3];\t// @[CircuitMath.scala:30:12, :34:17]\n wire _divisorMSB_T_45 = divisorMSB_lo_7[2];\t// @[CircuitMath.scala:30:12, :34:17]\n wire _divisorMSB_T_46 = divisorMSB_lo_7[1];\t// @[CircuitMath.scala:28:8, :34:17]\n wire [1:0] _divisorMSB_T_47 = _divisorMSB_T_45 ? 2'h2 : {1'h0, _divisorMSB_T_46};\t// @[CircuitMath.scala:28:8, :30:{10,12}]\n wire [1:0] _divisorMSB_T_48 = _divisorMSB_T_44 ? 2'h3 : _divisorMSB_T_47;\t// @[CircuitMath.scala:30:{10,12}]\n wire [1:0] _divisorMSB_T_49 = divisorMSB_useHi_7 ? _divisorMSB_T_43 : _divisorMSB_T_48;\t// @[CircuitMath.scala:30:10, :35:22, :36:21]\n wire [2:0] _divisorMSB_T_50 = {divisorMSB_useHi_7, _divisorMSB_T_49};\t// @[CircuitMath.scala:35:22, :36:{10,21}]\n wire [2:0] _divisorMSB_T_51 = divisorMSB_useHi_5 ? _divisorMSB_T_38 : _divisorMSB_T_50;\t// @[CircuitMath.scala:35:22, :36:{10,21}]\n wire [3:0] _divisorMSB_T_52 = {divisorMSB_useHi_5, _divisorMSB_T_51};\t// @[CircuitMath.scala:35:22, :36:{10,21}]\n wire [3:0] _divisorMSB_T_53 = divisorMSB_useHi_1 ? _divisorMSB_T_26 : _divisorMSB_T_52;\t// @[CircuitMath.scala:35:22, :36:{10,21}]\n wire [4:0] _divisorMSB_T_54 = {divisorMSB_useHi_1, _divisorMSB_T_53};\t// @[CircuitMath.scala:35:22, :36:{10,21}]\n wire [15:0] divisorMSB_hi_8 = divisorMSB_lo[31:16];\t// @[CircuitMath.scala:33:17, :34:17]\n wire [15:0] divisorMSB_lo_8 = divisorMSB_lo[15:0];\t// @[CircuitMath.scala:34:17]\n wire divisorMSB_useHi_8 = |divisorMSB_hi_8;\t// @[CircuitMath.scala:33:17, :35:22]\n wire [7:0] divisorMSB_hi_9 = divisorMSB_hi_8[15:8];\t// @[CircuitMath.scala:33:17]\n wire [7:0] divisorMSB_lo_9 = divisorMSB_hi_8[7:0];\t// @[CircuitMath.scala:33:17, :34:17]\n wire divisorMSB_useHi_9 = |divisorMSB_hi_9;\t// @[CircuitMath.scala:33:17, :35:22]\n wire [3:0] divisorMSB_hi_10 = divisorMSB_hi_9[7:4];\t// @[CircuitMath.scala:33:17]\n wire [3:0] divisorMSB_lo_10 = divisorMSB_hi_9[3:0];\t// @[CircuitMath.scala:33:17, :34:17]\n wire divisorMSB_useHi_10 = |divisorMSB_hi_10;\t// @[CircuitMath.scala:33:17, :35:22]\n wire _divisorMSB_T_55 = divisorMSB_hi_10[3];\t// @[CircuitMath.scala:30:12, :33:17]\n wire _divisorMSB_T_56 = divisorMSB_hi_10[2];\t// @[CircuitMath.scala:30:12, :33:17]\n wire _divisorMSB_T_57 = divisorMSB_hi_10[1];\t// @[CircuitMath.scala:28:8, :33:17]\n wire [1:0] _divisorMSB_T_58 = _divisorMSB_T_56 ? 2'h2 : {1'h0, _divisorMSB_T_57};\t// @[CircuitMath.scala:28:8, :30:{10,12}]\n wire [1:0] _divisorMSB_T_59 = _divisorMSB_T_55 ? 2'h3 : _divisorMSB_T_58;\t// @[CircuitMath.scala:30:{10,12}]\n wire _divisorMSB_T_60 = divisorMSB_lo_10[3];\t// @[CircuitMath.scala:30:12, :34:17]\n wire _divisorMSB_T_61 = divisorMSB_lo_10[2];\t// @[CircuitMath.scala:30:12, :34:17]\n wire _divisorMSB_T_62 = divisorMSB_lo_10[1];\t// @[CircuitMath.scala:28:8, :34:17]\n wire [1:0] _divisorMSB_T_63 = _divisorMSB_T_61 ? 2'h2 : {1'h0, _divisorMSB_T_62};\t// @[CircuitMath.scala:28:8, :30:{10,12}]\n wire [1:0] _divisorMSB_T_64 = _divisorMSB_T_60 ? 2'h3 : _divisorMSB_T_63;\t// @[CircuitMath.scala:30:{10,12}]\n wire [1:0] _divisorMSB_T_65 = divisorMSB_useHi_10 ? _divisorMSB_T_59 : _divisorMSB_T_64;\t// @[CircuitMath.scala:30:10, :35:22, :36:21]\n wire [2:0] _divisorMSB_T_66 = {divisorMSB_useHi_10, _divisorMSB_T_65};\t// @[CircuitMath.scala:35:22, :36:{10,21}]\n wire [3:0] divisorMSB_hi_11 = divisorMSB_lo_9[7:4];\t// @[CircuitMath.scala:33:17, :34:17]\n wire [3:0] divisorMSB_lo_11 = divisorMSB_lo_9[3:0];\t// @[CircuitMath.scala:34:17]\n wire divisorMSB_useHi_11 = |divisorMSB_hi_11;\t// @[CircuitMath.scala:33:17, :35:22]\n wire _divisorMSB_T_67 = divisorMSB_hi_11[3];\t// @[CircuitMath.scala:30:12, :33:17]\n wire _divisorMSB_T_68 = divisorMSB_hi_11[2];\t// @[CircuitMath.scala:30:12, :33:17]\n wire _divisorMSB_T_69 = divisorMSB_hi_11[1];\t// @[CircuitMath.scala:28:8, :33:17]\n wire [1:0] _divisorMSB_T_70 = _divisorMSB_T_68 ? 2'h2 : {1'h0, _divisorMSB_T_69};\t// @[CircuitMath.scala:28:8, :30:{10,12}]\n wire [1:0] _divisorMSB_T_71 = _divisorMSB_T_67 ? 2'h3 : _divisorMSB_T_70;\t// @[CircuitMath.scala:30:{10,12}]\n wire _divisorMSB_T_72 = divisorMSB_lo_11[3];\t// @[CircuitMath.scala:30:12, :34:17]\n wire _divisorMSB_T_73 = divisorMSB_lo_11[2];\t// @[CircuitMath.scala:30:12, :34:17]\n wire _divisorMSB_T_74 = divisorMSB_lo_11[1];\t// @[CircuitMath.scala:28:8, :34:17]\n wire [1:0] _divisorMSB_T_75 = _divisorMSB_T_73 ? 2'h2 : {1'h0, _divisorMSB_T_74};\t// @[CircuitMath.scala:28:8, :30:{10,12}]\n wire [1:0] _divisorMSB_T_76 = _divisorMSB_T_72 ? 2'h3 : _divisorMSB_T_75;\t// @[CircuitMath.scala:30:{10,12}]\n wire [1:0] _divisorMSB_T_77 = divisorMSB_useHi_11 ? _divisorMSB_T_71 : _divisorMSB_T_76;\t// @[CircuitMath.scala:30:10, :35:22, :36:21]\n wire [2:0] _divisorMSB_T_78 = {divisorMSB_useHi_11, _divisorMSB_T_77};\t// @[CircuitMath.scala:35:22, :36:{10,21}]\n wire [2:0] _divisorMSB_T_79 = divisorMSB_useHi_9 ? _divisorMSB_T_66 : _divisorMSB_T_78;\t// @[CircuitMath.scala:35:22, :36:{10,21}]\n wire [3:0] _divisorMSB_T_80 = {divisorMSB_useHi_9, _divisorMSB_T_79};\t// @[CircuitMath.scala:35:22, :36:{10,21}]\n wire [7:0] divisorMSB_hi_12 = divisorMSB_lo_8[15:8];\t// @[CircuitMath.scala:33:17, :34:17]\n wire [7:0] divisorMSB_lo_12 = divisorMSB_lo_8[7:0];\t// @[CircuitMath.scala:34:17]\n wire divisorMSB_useHi_12 = |divisorMSB_hi_12;\t// @[CircuitMath.scala:33:17, :35:22]\n wire [3:0] divisorMSB_hi_13 = divisorMSB_hi_12[7:4];\t// @[CircuitMath.scala:33:17]\n wire [3:0] divisorMSB_lo_13 = divisorMSB_hi_12[3:0];\t// @[CircuitMath.scala:33:17, :34:17]\n wire divisorMSB_useHi_13 = |divisorMSB_hi_13;\t// @[CircuitMath.scala:33:17, :35:22]\n wire _divisorMSB_T_81 = divisorMSB_hi_13[3];\t// @[CircuitMath.scala:30:12, :33:17]\n wire _divisorMSB_T_82 = divisorMSB_hi_13[2];\t// @[CircuitMath.scala:30:12, :33:17]\n wire _divisorMSB_T_83 = divisorMSB_hi_13[1];\t// @[CircuitMath.scala:28:8, :33:17]\n wire [1:0] _divisorMSB_T_84 = _divisorMSB_T_82 ? 2'h2 : {1'h0, _divisorMSB_T_83};\t// @[CircuitMath.scala:28:8, :30:{10,12}]\n wire [1:0] _divisorMSB_T_85 = _divisorMSB_T_81 ? 2'h3 : _divisorMSB_T_84;\t// @[CircuitMath.scala:30:{10,12}]\n wire _divisorMSB_T_86 = divisorMSB_lo_13[3];\t// @[CircuitMath.scala:30:12, :34:17]\n wire _divisorMSB_T_87 = divisorMSB_lo_13[2];\t// @[CircuitMath.scala:30:12, :34:17]\n wire _divisorMSB_T_88 = divisorMSB_lo_13[1];\t// @[CircuitMath.scala:28:8, :34:17]\n wire [1:0] _divisorMSB_T_89 = _divisorMSB_T_87 ? 2'h2 : {1'h0, _divisorMSB_T_88};\t// @[CircuitMath.scala:28:8, :30:{10,12}]\n wire [1:0] _divisorMSB_T_90 = _divisorMSB_T_86 ? 2'h3 : _divisorMSB_T_89;\t// @[CircuitMath.scala:30:{10,12}]\n wire [1:0] _divisorMSB_T_91 = divisorMSB_useHi_13 ? _divisorMSB_T_85 : _divisorMSB_T_90;\t// @[CircuitMath.scala:30:10, :35:22, :36:21]\n wire [2:0] _divisorMSB_T_92 = {divisorMSB_useHi_13, _divisorMSB_T_91};\t// @[CircuitMath.scala:35:22, :36:{10,21}]\n wire [3:0] divisorMSB_hi_14 = divisorMSB_lo_12[7:4];\t// @[CircuitMath.scala:33:17, :34:17]\n wire [3:0] divisorMSB_lo_14 = divisorMSB_lo_12[3:0];\t// @[CircuitMath.scala:34:17]\n wire divisorMSB_useHi_14 = |divisorMSB_hi_14;\t// @[CircuitMath.scala:33:17, :35:22]\n wire _divisorMSB_T_93 = divisorMSB_hi_14[3];\t// @[CircuitMath.scala:30:12, :33:17]\n wire _divisorMSB_T_94 = divisorMSB_hi_14[2];\t// @[CircuitMath.scala:30:12, :33:17]\n wire _divisorMSB_T_95 = divisorMSB_hi_14[1];\t// @[CircuitMath.scala:28:8, :33:17]\n wire [1:0] _divisorMSB_T_96 = _divisorMSB_T_94 ? 2'h2 : {1'h0, _divisorMSB_T_95};\t// @[CircuitMath.scala:28:8, :30:{10,12}]\n wire [1:0] _divisorMSB_T_97 = _divisorMSB_T_93 ? 2'h3 : _divisorMSB_T_96;\t// @[CircuitMath.scala:30:{10,12}]\n wire _divisorMSB_T_98 = divisorMSB_lo_14[3];\t// @[CircuitMath.scala:30:12, :34:17]\n wire _divisorMSB_T_99 = divisorMSB_lo_14[2];\t// @[CircuitMath.scala:30:12, :34:17]\n wire _divisorMSB_T_100 = divisorMSB_lo_14[1];\t// @[CircuitMath.scala:28:8, :34:17]\n wire [1:0] _divisorMSB_T_101 = _divisorMSB_T_99 ? 2'h2 : {1'h0, _divisorMSB_T_100};\t// @[CircuitMath.scala:28:8, :30:{10,12}]\n wire [1:0] _divisorMSB_T_102 = _divisorMSB_T_98 ? 2'h3 : _divisorMSB_T_101;\t// @[CircuitMath.scala:30:{10,12}]\n wire [1:0] _divisorMSB_T_103 = divisorMSB_useHi_14 ? _divisorMSB_T_97 : _divisorMSB_T_102;\t// @[CircuitMath.scala:30:10, :35:22, :36:21]\n wire [2:0] _divisorMSB_T_104 = {divisorMSB_useHi_14, _divisorMSB_T_103};\t// @[CircuitMath.scala:35:22, :36:{10,21}]\n wire [2:0] _divisorMSB_T_105 = divisorMSB_useHi_12 ? _divisorMSB_T_92 : _divisorMSB_T_104;\t// @[CircuitMath.scala:35:22, :36:{10,21}]\n wire [3:0] _divisorMSB_T_106 = {divisorMSB_useHi_12, _divisorMSB_T_105};\t// @[CircuitMath.scala:35:22, :36:{10,21}]\n wire [3:0] _divisorMSB_T_107 = divisorMSB_useHi_8 ? _divisorMSB_T_80 : _divisorMSB_T_106;\t// @[CircuitMath.scala:35:22, :36:{10,21}]\n wire [4:0] _divisorMSB_T_108 = {divisorMSB_useHi_8, _divisorMSB_T_107};\t// @[CircuitMath.scala:35:22, :36:{10,21}]\n wire [4:0] _divisorMSB_T_109 = divisorMSB_useHi ? _divisorMSB_T_54 : _divisorMSB_T_108;\t// @[CircuitMath.scala:35:22, :36:{10,21}]\n wire [5:0] _divisorMSB_T_110 = {divisorMSB_useHi, _divisorMSB_T_109};\t// @[CircuitMath.scala:35:22, :36:{10,21}]\n wire [5:0] divisorMSB = _divisorMSB_T_110;\t// @[CircuitMath.scala:36:10]\n wire [31:0] dividendMSB_hi = _dividendMSB_T[63:32];\t// @[CircuitMath.scala:33:17]\n wire [31:0] dividendMSB_lo = _dividendMSB_T[31:0];\t// @[CircuitMath.scala:34:17]\n wire dividendMSB_useHi = |dividendMSB_hi;\t// @[CircuitMath.scala:33:17, :35:22]\n wire [15:0] dividendMSB_hi_1 = dividendMSB_hi[31:16];\t// @[CircuitMath.scala:33:17]\n wire [15:0] dividendMSB_lo_1 = dividendMSB_hi[15:0];\t// @[CircuitMath.scala:33:17, :34:17]\n wire dividendMSB_useHi_1 = |dividendMSB_hi_1;\t// @[CircuitMath.scala:33:17, :35:22]\n wire [7:0] dividendMSB_hi_2 = dividendMSB_hi_1[15:8];\t// @[CircuitMath.scala:33:17]\n wire [7:0] dividendMSB_lo_2 = dividendMSB_hi_1[7:0];\t// @[CircuitMath.scala:33:17, :34:17]\n wire dividendMSB_useHi_2 = |dividendMSB_hi_2;\t// @[CircuitMath.scala:33:17, :35:22]\n wire [3:0] dividendMSB_hi_3 = dividendMSB_hi_2[7:4];\t// @[CircuitMath.scala:33:17]\n wire [3:0] dividendMSB_lo_3 = dividendMSB_hi_2[3:0];\t// @[CircuitMath.scala:33:17, :34:17]\n wire dividendMSB_useHi_3 = |dividendMSB_hi_3;\t// @[CircuitMath.scala:33:17, :35:22]\n wire _dividendMSB_T_1 = dividendMSB_hi_3[3];\t// @[CircuitMath.scala:30:12, :33:17]\n wire _dividendMSB_T_2 = dividendMSB_hi_3[2];\t// @[CircuitMath.scala:30:12, :33:17]\n wire _dividendMSB_T_3 = dividendMSB_hi_3[1];\t// @[CircuitMath.scala:28:8, :33:17]\n wire [1:0] _dividendMSB_T_4 = _dividendMSB_T_2 ? 2'h2 : {1'h0, _dividendMSB_T_3};\t// @[CircuitMath.scala:28:8, :30:{10,12}]\n wire [1:0] _dividendMSB_T_5 = _dividendMSB_T_1 ? 2'h3 : _dividendMSB_T_4;\t// @[CircuitMath.scala:30:{10,12}]\n wire _dividendMSB_T_6 = dividendMSB_lo_3[3];\t// @[CircuitMath.scala:30:12, :34:17]\n wire _dividendMSB_T_7 = dividendMSB_lo_3[2];\t// @[CircuitMath.scala:30:12, :34:17]\n wire _dividendMSB_T_8 = dividendMSB_lo_3[1];\t// @[CircuitMath.scala:28:8, :34:17]\n wire [1:0] _dividendMSB_T_9 = _dividendMSB_T_7 ? 2'h2 : {1'h0, _dividendMSB_T_8};\t// @[CircuitMath.scala:28:8, :30:{10,12}]\n wire [1:0] _dividendMSB_T_10 = _dividendMSB_T_6 ? 2'h3 : _dividendMSB_T_9;\t// @[CircuitMath.scala:30:{10,12}]\n wire [1:0] _dividendMSB_T_11 = dividendMSB_useHi_3 ? _dividendMSB_T_5 : _dividendMSB_T_10;\t// @[CircuitMath.scala:30:10, :35:22, :36:21]\n wire [2:0] _dividendMSB_T_12 = {dividendMSB_useHi_3, _dividendMSB_T_11};\t// @[CircuitMath.scala:35:22, :36:{10,21}]\n wire [3:0] dividendMSB_hi_4 = dividendMSB_lo_2[7:4];\t// @[CircuitMath.scala:33:17, :34:17]\n wire [3:0] dividendMSB_lo_4 = dividendMSB_lo_2[3:0];\t// @[CircuitMath.scala:34:17]\n wire dividendMSB_useHi_4 = |dividendMSB_hi_4;\t// @[CircuitMath.scala:33:17, :35:22]\n wire _dividendMSB_T_13 = dividendMSB_hi_4[3];\t// @[CircuitMath.scala:30:12, :33:17]\n wire _dividendMSB_T_14 = dividendMSB_hi_4[2];\t// @[CircuitMath.scala:30:12, :33:17]\n wire _dividendMSB_T_15 = dividendMSB_hi_4[1];\t// @[CircuitMath.scala:28:8, :33:17]\n wire [1:0] _dividendMSB_T_16 = _dividendMSB_T_14 ? 2'h2 : {1'h0, _dividendMSB_T_15};\t// @[CircuitMath.scala:28:8, :30:{10,12}]\n wire [1:0] _dividendMSB_T_17 = _dividendMSB_T_13 ? 2'h3 : _dividendMSB_T_16;\t// @[CircuitMath.scala:30:{10,12}]\n wire _dividendMSB_T_18 = dividendMSB_lo_4[3];\t// @[CircuitMath.scala:30:12, :34:17]\n wire _dividendMSB_T_19 = dividendMSB_lo_4[2];\t// @[CircuitMath.scala:30:12, :34:17]\n wire _dividendMSB_T_20 = dividendMSB_lo_4[1];\t// @[CircuitMath.scala:28:8, :34:17]\n wire [1:0] _dividendMSB_T_21 = _dividendMSB_T_19 ? 2'h2 : {1'h0, _dividendMSB_T_20};\t// @[CircuitMath.scala:28:8, :30:{10,12}]\n wire [1:0] _dividendMSB_T_22 = _dividendMSB_T_18 ? 2'h3 : _dividendMSB_T_21;\t// @[CircuitMath.scala:30:{10,12}]\n wire [1:0] _dividendMSB_T_23 = dividendMSB_useHi_4 ? _dividendMSB_T_17 : _dividendMSB_T_22;\t// @[CircuitMath.scala:30:10, :35:22, :36:21]\n wire [2:0] _dividendMSB_T_24 = {dividendMSB_useHi_4, _dividendMSB_T_23};\t// @[CircuitMath.scala:35:22, :36:{10,21}]\n wire [2:0] _dividendMSB_T_25 = dividendMSB_useHi_2 ? _dividendMSB_T_12 : _dividendMSB_T_24;\t// @[CircuitMath.scala:35:22, :36:{10,21}]\n wire [3:0] _dividendMSB_T_26 = {dividendMSB_useHi_2, _dividendMSB_T_25};\t// @[CircuitMath.scala:35:22, :36:{10,21}]\n wire [7:0] dividendMSB_hi_5 = dividendMSB_lo_1[15:8];\t// @[CircuitMath.scala:33:17, :34:17]\n wire [7:0] dividendMSB_lo_5 = dividendMSB_lo_1[7:0];\t// @[CircuitMath.scala:34:17]\n wire dividendMSB_useHi_5 = |dividendMSB_hi_5;\t// @[CircuitMath.scala:33:17, :35:22]\n wire [3:0] dividendMSB_hi_6 = dividendMSB_hi_5[7:4];\t// @[CircuitMath.scala:33:17]\n wire [3:0] dividendMSB_lo_6 = dividendMSB_hi_5[3:0];\t// @[CircuitMath.scala:33:17, :34:17]\n wire dividendMSB_useHi_6 = |dividendMSB_hi_6;\t// @[CircuitMath.scala:33:17, :35:22]\n wire _dividendMSB_T_27 = dividendMSB_hi_6[3];\t// @[CircuitMath.scala:30:12, :33:17]\n wire _dividendMSB_T_28 = dividendMSB_hi_6[2];\t// @[CircuitMath.scala:30:12, :33:17]\n wire _dividendMSB_T_29 = dividendMSB_hi_6[1];\t// @[CircuitMath.scala:28:8, :33:17]\n wire [1:0] _dividendMSB_T_30 = _dividendMSB_T_28 ? 2'h2 : {1'h0, _dividendMSB_T_29};\t// @[CircuitMath.scala:28:8, :30:{10,12}]\n wire [1:0] _dividendMSB_T_31 = _dividendMSB_T_27 ? 2'h3 : _dividendMSB_T_30;\t// @[CircuitMath.scala:30:{10,12}]\n wire _dividendMSB_T_32 = dividendMSB_lo_6[3];\t// @[CircuitMath.scala:30:12, :34:17]\n wire _dividendMSB_T_33 = dividendMSB_lo_6[2];\t// @[CircuitMath.scala:30:12, :34:17]\n wire _dividendMSB_T_34 = dividendMSB_lo_6[1];\t// @[CircuitMath.scala:28:8, :34:17]\n wire [1:0] _dividendMSB_T_35 = _dividendMSB_T_33 ? 2'h2 : {1'h0, _dividendMSB_T_34};\t// @[CircuitMath.scala:28:8, :30:{10,12}]\n wire [1:0] _dividendMSB_T_36 = _dividendMSB_T_32 ? 2'h3 : _dividendMSB_T_35;\t// @[CircuitMath.scala:30:{10,12}]\n wire [1:0] _dividendMSB_T_37 = dividendMSB_useHi_6 ? _dividendMSB_T_31 : _dividendMSB_T_36;\t// @[CircuitMath.scala:30:10, :35:22, :36:21]\n wire [2:0] _dividendMSB_T_38 = {dividendMSB_useHi_6, _dividendMSB_T_37};\t// @[CircuitMath.scala:35:22, :36:{10,21}]\n wire [3:0] dividendMSB_hi_7 = dividendMSB_lo_5[7:4];\t// @[CircuitMath.scala:33:17, :34:17]\n wire [3:0] dividendMSB_lo_7 = dividendMSB_lo_5[3:0];\t// @[CircuitMath.scala:34:17]\n wire dividendMSB_useHi_7 = |dividendMSB_hi_7;\t// @[CircuitMath.scala:33:17, :35:22]\n wire _dividendMSB_T_39 = dividendMSB_hi_7[3];\t// @[CircuitMath.scala:30:12, :33:17]\n wire _dividendMSB_T_40 = dividendMSB_hi_7[2];\t// @[CircuitMath.scala:30:12, :33:17]\n wire _dividendMSB_T_41 = dividendMSB_hi_7[1];\t// @[CircuitMath.scala:28:8, :33:17]\n wire [1:0] _dividendMSB_T_42 = _dividendMSB_T_40 ? 2'h2 : {1'h0, _dividendMSB_T_41};\t// @[CircuitMath.scala:28:8, :30:{10,12}]\n wire [1:0] _dividendMSB_T_43 = _dividendMSB_T_39 ? 2'h3 : _dividendMSB_T_42;\t// @[CircuitMath.scala:30:{10,12}]\n wire _dividendMSB_T_44 = dividendMSB_lo_7[3];\t// @[CircuitMath.scala:30:12, :34:17]\n wire _dividendMSB_T_45 = dividendMSB_lo_7[2];\t// @[CircuitMath.scala:30:12, :34:17]\n wire _dividendMSB_T_46 = dividendMSB_lo_7[1];\t// @[CircuitMath.scala:28:8, :34:17]\n wire [1:0] _dividendMSB_T_47 = _dividendMSB_T_45 ? 2'h2 : {1'h0, _dividendMSB_T_46};\t// @[CircuitMath.scala:28:8, :30:{10,12}]\n wire [1:0] _dividendMSB_T_48 = _dividendMSB_T_44 ? 2'h3 : _dividendMSB_T_47;\t// @[CircuitMath.scala:30:{10,12}]\n wire [1:0] _dividendMSB_T_49 = dividendMSB_useHi_7 ? _dividendMSB_T_43 : _dividendMSB_T_48;\t// @[CircuitMath.scala:30:10, :35:22, :36:21]\n wire [2:0] _dividendMSB_T_50 = {dividendMSB_useHi_7, _dividendMSB_T_49};\t// @[CircuitMath.scala:35:22, :36:{10,21}]\n wire [2:0] _dividendMSB_T_51 = dividendMSB_useHi_5 ? _dividendMSB_T_38 : _dividendMSB_T_50;\t// @[CircuitMath.scala:35:22, :36:{10,21}]\n wire [3:0] _dividendMSB_T_52 = {dividendMSB_useHi_5, _dividendMSB_T_51};\t// @[CircuitMath.scala:35:22, :36:{10,21}]\n wire [3:0] _dividendMSB_T_53 = dividendMSB_useHi_1 ? _dividendMSB_T_26 : _dividendMSB_T_52;\t// @[CircuitMath.scala:35:22, :36:{10,21}]\n wire [4:0] _dividendMSB_T_54 = {dividendMSB_useHi_1, _dividendMSB_T_53};\t// @[CircuitMath.scala:35:22, :36:{10,21}]\n wire [15:0] dividendMSB_hi_8 = dividendMSB_lo[31:16];\t// @[CircuitMath.scala:33:17, :34:17]\n wire [15:0] dividendMSB_lo_8 = dividendMSB_lo[15:0];\t// @[CircuitMath.scala:34:17]\n wire dividendMSB_useHi_8 = |dividendMSB_hi_8;\t// @[CircuitMath.scala:33:17, :35:22]\n wire [7:0] dividendMSB_hi_9 = dividendMSB_hi_8[15:8];\t// @[CircuitMath.scala:33:17]\n wire [7:0] dividendMSB_lo_9 = dividendMSB_hi_8[7:0];\t// @[CircuitMath.scala:33:17, :34:17]\n wire dividendMSB_useHi_9 = |dividendMSB_hi_9;\t// @[CircuitMath.scala:33:17, :35:22]\n wire [3:0] dividendMSB_hi_10 = dividendMSB_hi_9[7:4];\t// @[CircuitMath.scala:33:17]\n wire [3:0] dividendMSB_lo_10 = dividendMSB_hi_9[3:0];\t// @[CircuitMath.scala:33:17, :34:17]\n wire dividendMSB_useHi_10 = |dividendMSB_hi_10;\t// @[CircuitMath.scala:33:17, :35:22]\n wire _dividendMSB_T_55 = dividendMSB_hi_10[3];\t// @[CircuitMath.scala:30:12, :33:17]\n wire _dividendMSB_T_56 = dividendMSB_hi_10[2];\t// @[CircuitMath.scala:30:12, :33:17]\n wire _dividendMSB_T_57 = dividendMSB_hi_10[1];\t// @[CircuitMath.scala:28:8, :33:17]\n wire [1:0] _dividendMSB_T_58 = _dividendMSB_T_56 ? 2'h2 : {1'h0, _dividendMSB_T_57};\t// @[CircuitMath.scala:28:8, :30:{10,12}]\n wire [1:0] _dividendMSB_T_59 = _dividendMSB_T_55 ? 2'h3 : _dividendMSB_T_58;\t// @[CircuitMath.scala:30:{10,12}]\n wire _dividendMSB_T_60 = dividendMSB_lo_10[3];\t// @[CircuitMath.scala:30:12, :34:17]\n wire _dividendMSB_T_61 = dividendMSB_lo_10[2];\t// @[CircuitMath.scala:30:12, :34:17]\n wire _dividendMSB_T_62 = dividendMSB_lo_10[1];\t// @[CircuitMath.scala:28:8, :34:17]\n wire [1:0] _dividendMSB_T_63 = _dividendMSB_T_61 ? 2'h2 : {1'h0, _dividendMSB_T_62};\t// @[CircuitMath.scala:28:8, :30:{10,12}]\n wire [1:0] _dividendMSB_T_64 = _dividendMSB_T_60 ? 2'h3 : _dividendMSB_T_63;\t// @[CircuitMath.scala:30:{10,12}]\n wire [1:0] _dividendMSB_T_65 = dividendMSB_useHi_10 ? _dividendMSB_T_59 : _dividendMSB_T_64;\t// @[CircuitMath.scala:30:10, :35:22, :36:21]\n wire [2:0] _dividendMSB_T_66 = {dividendMSB_useHi_10, _dividendMSB_T_65};\t// @[CircuitMath.scala:35:22, :36:{10,21}]\n wire [3:0] dividendMSB_hi_11 = dividendMSB_lo_9[7:4];\t// @[CircuitMath.scala:33:17, :34:17]\n wire [3:0] dividendMSB_lo_11 = dividendMSB_lo_9[3:0];\t// @[CircuitMath.scala:34:17]\n wire dividendMSB_useHi_11 = |dividendMSB_hi_11;\t// @[CircuitMath.scala:33:17, :35:22]\n wire _dividendMSB_T_67 = dividendMSB_hi_11[3];\t// @[CircuitMath.scala:30:12, :33:17]\n wire _dividendMSB_T_68 = dividendMSB_hi_11[2];\t// @[CircuitMath.scala:30:12, :33:17]\n wire _dividendMSB_T_69 = dividendMSB_hi_11[1];\t// @[CircuitMath.scala:28:8, :33:17]\n wire [1:0] _dividendMSB_T_70 = _dividendMSB_T_68 ? 2'h2 : {1'h0, _dividendMSB_T_69};\t// @[CircuitMath.scala:28:8, :30:{10,12}]\n wire [1:0] _dividendMSB_T_71 = _dividendMSB_T_67 ? 2'h3 : _dividendMSB_T_70;\t// @[CircuitMath.scala:30:{10,12}]\n wire _dividendMSB_T_72 = dividendMSB_lo_11[3];\t// @[CircuitMath.scala:30:12, :34:17]\n wire _dividendMSB_T_73 = dividendMSB_lo_11[2];\t// @[CircuitMath.scala:30:12, :34:17]\n wire _dividendMSB_T_74 = dividendMSB_lo_11[1];\t// @[CircuitMath.scala:28:8, :34:17]\n wire [1:0] _dividendMSB_T_75 = _dividendMSB_T_73 ? 2'h2 : {1'h0, _dividendMSB_T_74};\t// @[CircuitMath.scala:28:8, :30:{10,12}]\n wire [1:0] _dividendMSB_T_76 = _dividendMSB_T_72 ? 2'h3 : _dividendMSB_T_75;\t// @[CircuitMath.scala:30:{10,12}]\n wire [1:0] _dividendMSB_T_77 = dividendMSB_useHi_11 ? _dividendMSB_T_71 : _dividendMSB_T_76;\t// @[CircuitMath.scala:30:10, :35:22, :36:21]\n wire [2:0] _dividendMSB_T_78 = {dividendMSB_useHi_11, _dividendMSB_T_77};\t// @[CircuitMath.scala:35:22, :36:{10,21}]\n wire [2:0] _dividendMSB_T_79 = dividendMSB_useHi_9 ? _dividendMSB_T_66 : _dividendMSB_T_78;\t// @[CircuitMath.scala:35:22, :36:{10,21}]\n wire [3:0] _dividendMSB_T_80 = {dividendMSB_useHi_9, _dividendMSB_T_79};\t// @[CircuitMath.scala:35:22, :36:{10,21}]\n wire [7:0] dividendMSB_hi_12 = dividendMSB_lo_8[15:8];\t// @[CircuitMath.scala:33:17, :34:17]\n wire [7:0] dividendMSB_lo_12 = dividendMSB_lo_8[7:0];\t// @[CircuitMath.scala:34:17]\n wire dividendMSB_useHi_12 = |dividendMSB_hi_12;\t// @[CircuitMath.scala:33:17, :35:22]\n wire [3:0] dividendMSB_hi_13 = dividendMSB_hi_12[7:4];\t// @[CircuitMath.scala:33:17]\n wire [3:0] dividendMSB_lo_13 = dividendMSB_hi_12[3:0];\t// @[CircuitMath.scala:33:17, :34:17]\n wire dividendMSB_useHi_13 = |dividendMSB_hi_13;\t// @[CircuitMath.scala:33:17, :35:22]\n wire _dividendMSB_T_81 = dividendMSB_hi_13[3];\t// @[CircuitMath.scala:30:12, :33:17]\n wire _dividendMSB_T_82 = dividendMSB_hi_13[2];\t// @[CircuitMath.scala:30:12, :33:17]\n wire _dividendMSB_T_83 = dividendMSB_hi_13[1];\t// @[CircuitMath.scala:28:8, :33:17]\n wire [1:0] _dividendMSB_T_84 = _dividendMSB_T_82 ? 2'h2 : {1'h0, _dividendMSB_T_83};\t// @[CircuitMath.scala:28:8, :30:{10,12}]\n wire [1:0] _dividendMSB_T_85 = _dividendMSB_T_81 ? 2'h3 : _dividendMSB_T_84;\t// @[CircuitMath.scala:30:{10,12}]\n wire _dividendMSB_T_86 = dividendMSB_lo_13[3];\t// @[CircuitMath.scala:30:12, :34:17]\n wire _dividendMSB_T_87 = dividendMSB_lo_13[2];\t// @[CircuitMath.scala:30:12, :34:17]\n wire _dividendMSB_T_88 = dividendMSB_lo_13[1];\t// @[CircuitMath.scala:28:8, :34:17]\n wire [1:0] _dividendMSB_T_89 = _dividendMSB_T_87 ? 2'h2 : {1'h0, _dividendMSB_T_88};\t// @[CircuitMath.scala:28:8, :30:{10,12}]\n wire [1:0] _dividendMSB_T_90 = _dividendMSB_T_86 ? 2'h3 : _dividendMSB_T_89;\t// @[CircuitMath.scala:30:{10,12}]\n wire [1:0] _dividendMSB_T_91 = dividendMSB_useHi_13 ? _dividendMSB_T_85 : _dividendMSB_T_90;\t// @[CircuitMath.scala:30:10, :35:22, :36:21]\n wire [2:0] _dividendMSB_T_92 = {dividendMSB_useHi_13, _dividendMSB_T_91};\t// @[CircuitMath.scala:35:22, :36:{10,21}]\n wire [3:0] dividendMSB_hi_14 = dividendMSB_lo_12[7:4];\t// @[CircuitMath.scala:33:17, :34:17]\n wire [3:0] dividendMSB_lo_14 = dividendMSB_lo_12[3:0];\t// @[CircuitMath.scala:34:17]\n wire dividendMSB_useHi_14 = |dividendMSB_hi_14;\t// @[CircuitMath.scala:33:17, :35:22]\n wire _dividendMSB_T_93 = dividendMSB_hi_14[3];\t// @[CircuitMath.scala:30:12, :33:17]\n wire _dividendMSB_T_94 = dividendMSB_hi_14[2];\t// @[CircuitMath.scala:30:12, :33:17]\n wire _dividendMSB_T_95 = dividendMSB_hi_14[1];\t// @[CircuitMath.scala:28:8, :33:17]\n wire [1:0] _dividendMSB_T_96 = _dividendMSB_T_94 ? 2'h2 : {1'h0, _dividendMSB_T_95};\t// @[CircuitMath.scala:28:8, :30:{10,12}]\n wire [1:0] _dividendMSB_T_97 = _dividendMSB_T_93 ? 2'h3 : _dividendMSB_T_96;\t// @[CircuitMath.scala:30:{10,12}]\n wire _dividendMSB_T_98 = dividendMSB_lo_14[3];\t// @[CircuitMath.scala:30:12, :34:17]\n wire _dividendMSB_T_99 = dividendMSB_lo_14[2];\t// @[CircuitMath.scala:30:12, :34:17]\n wire _dividendMSB_T_100 = dividendMSB_lo_14[1];\t// @[CircuitMath.scala:28:8, :34:17]\n wire [1:0] _dividendMSB_T_101 = _dividendMSB_T_99 ? 2'h2 : {1'h0, _dividendMSB_T_100};\t// @[CircuitMath.scala:28:8, :30:{10,12}]\n wire [1:0] _dividendMSB_T_102 = _dividendMSB_T_98 ? 2'h3 : _dividendMSB_T_101;\t// @[CircuitMath.scala:30:{10,12}]\n wire [1:0] _dividendMSB_T_103 = dividendMSB_useHi_14 ? _dividendMSB_T_97 : _dividendMSB_T_102;\t// @[CircuitMath.scala:30:10, :35:22, :36:21]\n wire [2:0] _dividendMSB_T_104 = {dividendMSB_useHi_14, _dividendMSB_T_103};\t// @[CircuitMath.scala:35:22, :36:{10,21}]\n wire [2:0] _dividendMSB_T_105 = dividendMSB_useHi_12 ? _dividendMSB_T_92 : _dividendMSB_T_104;\t// @[CircuitMath.scala:35:22, :36:{10,21}]\n wire [3:0] _dividendMSB_T_106 = {dividendMSB_useHi_12, _dividendMSB_T_105};\t// @[CircuitMath.scala:35:22, :36:{10,21}]\n wire [3:0] _dividendMSB_T_107 = dividendMSB_useHi_8 ? _dividendMSB_T_80 : _dividendMSB_T_106;\t// @[CircuitMath.scala:35:22, :36:{10,21}]\n wire [4:0] _dividendMSB_T_108 = {dividendMSB_useHi_8, _dividendMSB_T_107};\t// @[CircuitMath.scala:35:22, :36:{10,21}]\n wire [4:0] _dividendMSB_T_109 = dividendMSB_useHi ? _dividendMSB_T_54 : _dividendMSB_T_108;\t// @[CircuitMath.scala:35:22, :36:{10,21}]\n wire [5:0] _dividendMSB_T_110 = {dividendMSB_useHi, _dividendMSB_T_109};\t// @[CircuitMath.scala:35:22, :36:{10,21}]\n wire [5:0] dividendMSB = _dividendMSB_T_110;\t// @[CircuitMath.scala:36:10]\n wire [6:0] _eOutPos_T = {1'h0, dividendMSB} - {1'h0, divisorMSB};\t// @[Multiplier.scala:150:48, :151:51, :152:35]\n wire [5:0] _eOutPos_T_1 = _eOutPos_T[5:0];\t// @[Multiplier.scala:152:35]\n wire [5:0] eOutPos = ~_eOutPos_T_1;\t// @[Multiplier.scala:152:{21,35}]\n wire [5:0] _count_T_4 = eOutPos;\t// @[Multiplier.scala:152:21, :156:26]\n wire _eOut_T_9 = ~(|count);\t// @[Multiplier.scala:54:18, :117:83, :146:24, :153:24]\n wire _eOut_T_10 = ~divby0;\t// @[Multiplier.scala:146:32, :153:35]\n wire _eOut_T_11 = _eOut_T_9 & _eOut_T_10;\t// @[Multiplier.scala:153:{24,32,35}]\n wire _eOut_T_12 = |eOutPos;\t// @[Multiplier.scala:152:21, :153:54]\n wire eOut_1 = _eOut_T_11 & _eOut_T_12;\t// @[Multiplier.scala:153:{32,43,54}]\n wire [126:0] _remainder_T_4 = {63'h0, _remainder_T_3} << eOutPos;\t// @[Multiplier.scala:152:21, :155:{31,39}]\n wire _state_T_1 = lhs_sign | rhs_sign;\t// @[Multiplier.scala:81:23, :165:46]\n wire [2:0] _state_T_2 = {1'h0, ~_state_T_1, 1'h1};\t// @[Multiplier.scala:165:{36,46}]\n wire [2:0] _state_T_3 = cmdMul ? 3'h2 : _state_T_2;\t// @[Multiplier.scala:75:107, :165:{17,36}]\n wire _count_T_6 = _count_T_5;\t// @[Multiplier.scala:78:{50,60}]\n wire _count_T_7 = cmdMul & _count_T_6;\t// @[Multiplier.scala:75:107, :78:50, :168:46]\n wire [5:0] _count_T_8 = {_count_T_7, 5'h0};\t// @[Multiplier.scala:168:{38,46}]\n wire _neg_out_T = lhs_sign != rhs_sign;\t// @[Multiplier.scala:81:23, :169:46]\n wire _neg_out_T_1 = cmdHi ? lhs_sign : _neg_out_T;\t// @[Multiplier.scala:75:107, :81:23, :169:{19,46}]\n wire [64:0] _divisor_T = {rhs_sign, rhs_in};\t// @[Multiplier.scala:81:23, :83:9, :170:19]\n wire [2:0] _outMul_T_1 = state & 3'h1;\t// @[Multiplier.scala:51:22, :175:23]\n wire outMul = _outMul_T_1 == 3'h0;\t// @[Multiplier.scala:175:{23,52}]\n wire _loOut_T = ~req_dw;\t// @[Multiplier.scala:53:16, :78:60]\n wire _loOut_T_1 = _loOut_T;\t// @[Multiplier.scala:78:{50,60}]\n wire _loOut_T_2 = _loOut_T_1;\t// @[Multiplier.scala:78:50, :176:30]\n wire _loOut_T_3 = _loOut_T_2 & outMul;\t// @[Multiplier.scala:175:52, :176:{30,48}]\n wire [31:0] _loOut_T_4 = result[63:32];\t// @[Multiplier.scala:89:19, :176:65]\n wire [31:0] _hiOut_T_4 = result[63:32];\t// @[Multiplier.scala:89:19, :176:65, :177:66]\n wire [31:0] _loOut_T_5 = result[31:0];\t// @[Multiplier.scala:89:19, :176:82]\n wire [31:0] loOut = _loOut_T_3 ? _loOut_T_4 : _loOut_T_5;\t// @[Multiplier.scala:176:{18,48,65,82}]\n wire _hiOut_T = ~req_dw;\t// @[Multiplier.scala:53:16, :78:60]\n wire _hiOut_T_1 = _hiOut_T;\t// @[Multiplier.scala:78:{50,60}]\n wire _hiOut_T_2 = loOut[31];\t// @[Multiplier.scala:176:18, :177:50]\n wire [31:0] _hiOut_T_3 = {32{_hiOut_T_2}};\t// @[Multiplier.scala:177:{39,50}]\n wire [31:0] hiOut = _hiOut_T_1 ? _hiOut_T_3 : _hiOut_T_4;\t// @[Multiplier.scala:78:50, :177:{18,39,66}]\n assign _io_resp_bits_data_T = {hiOut, loOut};\t// @[Multiplier.scala:176:18, :177:18, :180:27]\n assign io_resp_bits_data_0 = _io_resp_bits_data_T;\t// @[Multiplier.scala:40:7, :180:27]\n assign _io_resp_bits_full_data_T_2 = {_io_resp_bits_full_data_T, _io_resp_bits_full_data_T_1};\t// @[Multiplier.scala:181:{32,42,63}]\n assign io_resp_bits_full_data = _io_resp_bits_full_data_T_2;\t// @[Multiplier.scala:40:7, :181:32]\n wire _io_resp_valid_T = state == 3'h6;\t// @[Multiplier.scala:51:22, :182:27]\n wire _io_resp_valid_T_1 = &state;\t// @[Multiplier.scala:51:22, :182:51]\n assign _io_resp_valid_T_2 = _io_resp_valid_T | _io_resp_valid_T_1;\t// @[Multiplier.scala:182:{27,42,51}]\n assign io_resp_valid_0 = _io_resp_valid_T_2;\t// @[Multiplier.scala:40:7, :182:42]\n assign _io_req_ready_T = state == 3'h0;\t// @[Multiplier.scala:51:22, :183:25]\n assign io_req_ready_0 = _io_req_ready_T;\t// @[Multiplier.scala:40:7, :183:25]\n wire _T_10 = state == 3'h1;\t// @[Multiplier.scala:51:22, :92:39]\n wire _T_13 = state == 3'h5;\t// @[Multiplier.scala:51:22, :101:39]\n wire _T_14 = state == 3'h2;\t// @[Multiplier.scala:51:22, :106:39]\n wire _GEN_1 = _T_14 & count == 7'h3F;\t// @[Multiplier.scala:54:18, :101:57, :106:{39,50}, :124:{25,55}, :125:13]\n wire _T_17 = state == 3'h3;\t// @[Multiplier.scala:51:22, :129:39]\n wire _T_18 = count == 7'h40;\t// @[Multiplier.scala:54:18, :138:17]\n wire _T_23 = io_req_ready_0 & io_req_valid_0;\t// @[Decoupled.scala:51:35]\n always @(posedge clock) begin\t// @[Multiplier.scala:40:7]\n if (reset)\t// @[Multiplier.scala:40:7]\n state <= 3'h0;\t// @[Multiplier.scala:51:22]\n else if (_T_23)\t// @[Decoupled.scala:51:35]\n state <= _state_T_3;\t// @[Multiplier.scala:51:22, :165:17]\n else if (io_resp_ready_0 & io_resp_valid_0 | io_kill_0)\t// @[Decoupled.scala:51:35]\n state <= 3'h0;\t// @[Multiplier.scala:51:22]\n else if (_T_17 & _T_18)\t// @[Multiplier.scala:106:50, :129:{39,50}, :138:{17,42}, :139:13]\n state <= _state_T;\t// @[Multiplier.scala:51:22, :139:19]\n else if (_GEN_1)\t// @[Multiplier.scala:101:57, :106:50, :124:55, :125:13]\n state <= 3'h6;\t// @[Multiplier.scala:51:22]\n else if (_T_13)\t// @[Multiplier.scala:101:39]\n state <= 3'h7;\t// @[Multiplier.scala:51:22]\n else if (_T_10)\t// @[Multiplier.scala:92:39]\n state <= 3'h3;\t// @[Multiplier.scala:51:22]\n if (_T_23) begin\t// @[Decoupled.scala:51:35]\n req_fn <= io_req_bits_fn_0;\t// @[Multiplier.scala:40:7, :53:16]\n req_dw <= io_req_bits_dw_0;\t// @[Multiplier.scala:40:7, :53:16]\n req_in1 <= io_req_bits_in1_0;\t// @[Multiplier.scala:40:7, :53:16]\n req_in2 <= io_req_bits_in2_0;\t// @[Multiplier.scala:40:7, :53:16]\n count <= {1'h0, _count_T_8};\t// @[Multiplier.scala:54:18, :168:{11,38}]\n isHi <= cmdHi;\t// @[Multiplier.scala:58:17, :75:107]\n divisor <= _divisor_T;\t// @[Multiplier.scala:60:20, :170:19]\n remainder <= {66'h0, lhs_in};\t// @[Multiplier.scala:61:22, :83:9, :94:17, :171:15]\n end\n else begin\t// @[Decoupled.scala:51:35]\n if (_T_17) begin\t// @[Multiplier.scala:129:39]\n count <= eOut_1 ? {1'h0, _count_T_4} : _count_T_3;\t// @[Multiplier.scala:54:18, :144:{11,20}, :153:43, :154:19, :156:{15,26}]\n remainder <= eOut_1 ? {3'h0, _remainder_T_4} : {1'h0, unrolls_0};\t// @[Multiplier.scala:61:22, :134:10, :137:15, :153:43, :154:19, :155:{19,39}]\n end\n else if (_T_14) begin\t// @[Multiplier.scala:106:39]\n count <= _count_T_1;\t// @[Multiplier.scala:54:18, :123:20]\n remainder <= _remainder_T_2;\t// @[Multiplier.scala:61:22, :121:21]\n end\n else if (_T_13 | _T_10 & remainder[63])\t// @[Multiplier.scala:61:22, :92:{39,57}, :93:{20,27}, :94:17, :101:{39,57}, :102:15]\n remainder <= {66'h0, negated_remainder};\t// @[Multiplier.scala:61:22, :90:27, :94:17]\n if (_T_10 & divisor[63])\t// @[Multiplier.scala:60:20, :92:{39,57}, :96:{18,25}, :97:15]\n divisor <= subtractor;\t// @[Multiplier.scala:60:20, :88:37]\n end\n neg_out <= _T_23 ? _neg_out_T_1 : ~(_T_17 & divby0 & ~isHi) & neg_out;\t// @[Decoupled.scala:51:35]\n resHi <= ~_T_23 & (_T_17 & _T_18 | _GEN_1 ? isHi : ~_T_13 & resHi);\t// @[Decoupled.scala:51:35]\n always @(posedge)\n assign io_req_ready = io_req_ready_0;\t// @[Multiplier.scala:40:7]\n assign io_resp_valid = io_resp_valid_0;\t// @[Multiplier.scala:40:7]\n assign io_resp_bits_data = io_resp_bits_data_0;\t// @[Multiplier.scala:40:7]\nendmodule"}}},{"rowIdx":586,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to the following Chisel files.\nFile util.scala:\n//******************************************************************************\n// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).\n// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.\n//------------------------------------------------------------------------------\n\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n// Utility Functions\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n\npackage boom.v4.util\n\nimport chisel3._\nimport chisel3.util._\n\nimport freechips.rocketchip.rocket.Instructions._\nimport freechips.rocketchip.rocket._\nimport freechips.rocketchip.util.{Str}\nimport org.chipsalliance.cde.config.{Parameters}\nimport freechips.rocketchip.tile.{TileKey}\n\nimport boom.v4.common.{MicroOp}\nimport boom.v4.exu.{BrUpdateInfo}\n\n/**\n * Object to XOR fold a input register of fullLength into a compressedLength.\n */\nobject Fold\n{\n def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = {\n val clen = compressedLength\n val hlen = fullLength\n if (hlen <= clen) {\n input\n } else {\n var res = 0.U(clen.W)\n var remaining = input.asUInt\n for (i <- 0 to hlen-1 by clen) {\n val len = if (i + clen > hlen ) (hlen - i) else clen\n require(len > 0)\n res = res(clen-1,0) ^ remaining(len-1,0)\n remaining = remaining >> len.U\n }\n res\n }\n }\n}\n\n/**\n * Object to check if MicroOp was killed due to a branch mispredict.\n * Uses \"Fast\" branch masks\n */\nobject IsKilledByBranch\n{\n def apply(brupdate: BrUpdateInfo, flush: Bool, uop: MicroOp): Bool = {\n return apply(brupdate, flush, uop.br_mask)\n }\n\n def apply(brupdate: BrUpdateInfo, flush: Bool, uop_mask: UInt): Bool = {\n return maskMatch(brupdate.b1.mispredict_mask, uop_mask) || flush\n }\n\n def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: T): Bool = {\n return apply(brupdate, flush, bundle.uop)\n }\n\n def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Bool = {\n return apply(brupdate, flush, bundle.bits)\n }\n}\n\n/**\n * Object to return new MicroOp with a new BR mask given a MicroOp mask\n * and old BR mask.\n */\nobject GetNewUopAndBrMask\n{\n def apply(uop: MicroOp, brupdate: BrUpdateInfo)\n (implicit p: Parameters): MicroOp = {\n val newuop = WireInit(uop)\n newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask\n newuop\n }\n}\n\n/**\n * Object to return a BR mask given a MicroOp mask and old BR mask.\n */\nobject GetNewBrMask\n{\n def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = {\n return uop.br_mask & ~brupdate.b1.resolve_mask\n }\n\n def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = {\n return br_mask & ~brupdate.b1.resolve_mask\n }\n}\n\nobject UpdateBrMask\n{\n def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = {\n val out = WireInit(uop)\n out.br_mask := GetNewBrMask(brupdate, uop)\n out\n }\n def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = {\n val out = WireInit(bundle)\n out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask)\n out\n }\n def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Valid[T] = {\n val out = WireInit(bundle)\n out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask)\n out.valid := bundle.valid && !IsKilledByBranch(brupdate, flush, bundle.bits.uop.br_mask)\n out\n }\n}\n\n/**\n * Object to check if at least 1 bit matches in two masks\n */\nobject maskMatch\n{\n def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U\n}\n\n/**\n * Object to clear one bit in a mask given an index\n */\nobject clearMaskBit\n{\n def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0)\n}\n\n/**\n * Object to shift a register over by one bit and concat a new one\n */\nobject PerformShiftRegister\n{\n def apply(reg_val: UInt, new_bit: Bool): UInt = {\n reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt\n reg_val\n }\n}\n\n/**\n * Object to shift a register over by one bit, wrapping the top bit around to the bottom\n * (XOR'ed with a new-bit), and evicting a bit at index HLEN.\n * This is used to simulate a longer HLEN-width shift register that is folded\n * down to a compressed CLEN.\n */\nobject PerformCircularShiftRegister\n{\n def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = {\n val carry = csr(clen-1)\n val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U)\n newval\n }\n}\n\n/**\n * Object to increment an input value, wrapping it if\n * necessary.\n */\nobject WrapAdd\n{\n // \"n\" is the number of increments, so we wrap at n-1.\n def apply(value: UInt, amt: UInt, n: Int): UInt = {\n if (isPow2(n)) {\n (value + amt)(log2Ceil(n)-1,0)\n } else {\n val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt)\n Mux(sum >= n.U,\n sum - n.U,\n sum)\n }\n }\n}\n\n/**\n * Object to decrement an input value, wrapping it if\n * necessary.\n */\nobject WrapSub\n{\n // \"n\" is the number of increments, so we wrap to n-1.\n def apply(value: UInt, amt: Int, n: Int): UInt = {\n if (isPow2(n)) {\n (value - amt.U)(log2Ceil(n)-1,0)\n } else {\n val v = Cat(0.U(1.W), value)\n val b = Cat(0.U(1.W), amt.U)\n Mux(value >= amt.U,\n value - amt.U,\n n.U - amt.U + value)\n }\n }\n}\n\n/**\n * Object to increment an input value, wrapping it if\n * necessary.\n */\nobject WrapInc\n{\n // \"n\" is the number of increments, so we wrap at n-1.\n def apply(value: UInt, n: Int): UInt = {\n if (isPow2(n)) {\n (value + 1.U)(log2Ceil(n)-1,0)\n } else {\n val wrap = (value === (n-1).U)\n Mux(wrap, 0.U, value + 1.U)\n }\n }\n}\n\n/**\n * Object to decrement an input value, wrapping it if\n * necessary.\n */\nobject WrapDec\n{\n // \"n\" is the number of increments, so we wrap at n-1.\n def apply(value: UInt, n: Int): UInt = {\n if (isPow2(n)) {\n (value - 1.U)(log2Ceil(n)-1,0)\n } else {\n val wrap = (value === 0.U)\n Mux(wrap, (n-1).U, value - 1.U)\n }\n }\n}\n\n/**\n * Object to mask off lower bits of a PC to align to a \"b\"\n * Byte boundary.\n */\nobject AlignPCToBoundary\n{\n def apply(pc: UInt, b: Int): UInt = {\n // Invert for scenario where pc longer than b\n // (which would clear all bits above size(b)).\n ~(~pc | (b-1).U)\n }\n}\n\n/**\n * Object to rotate a signal left by one\n */\nobject RotateL1\n{\n def apply(signal: UInt): UInt = {\n val w = signal.getWidth\n val out = Cat(signal(w-2,0), signal(w-1))\n\n return out\n }\n}\n\n/**\n * Object to sext a value to a particular length.\n */\nobject Sext\n{\n def apply(x: UInt, length: Int): UInt = {\n if (x.getWidth == length) return x\n else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x)\n }\n}\n\n\n/**\n * Object to translate from BOOM's special \"packed immediate\" to a 32b signed immediate\n * Asking for U-type gives it shifted up 12 bits.\n */\nobject ImmGen\n{\n import boom.v4.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U, IS_N}\n def apply(i: UInt, isel: UInt): UInt = {\n val ip = Mux(isel === IS_N, 0.U(LONGEST_IMM_SZ.W), i)\n\n val sign = ip(LONGEST_IMM_SZ-1).asSInt\n val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign)\n val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign)\n val i11 = Mux(isel === IS_U, 0.S,\n Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign))\n val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt)\n val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt)\n val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S)\n\n\n return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0)\n }\n}\n\n/**\n * Object to see if an instruction is a JALR.\n */\nobject DebugIsJALR\n{\n def apply(inst: UInt): Bool = {\n // TODO Chisel not sure why this won't compile\n// val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)),\n// Array(\n// JALR -> Bool(true)))\n inst(6,0) === \"b1100111\".U\n }\n}\n\n/**\n * Object to take an instruction and output its branch or jal target. Only used\n * for a debug assert (no where else would we jump straight from instruction\n * bits to a target).\n */\nobject DebugGetBJImm\n{\n def apply(inst: UInt): UInt = {\n // TODO Chisel not sure why this won't compile\n //val csignals =\n //rocket.DecodeLogic(inst,\n // List(Bool(false), Bool(false)),\n // Array(\n // BEQ -> List(Bool(true ), Bool(false)),\n // BNE -> List(Bool(true ), Bool(false)),\n // BGE -> List(Bool(true ), Bool(false)),\n // BGEU -> List(Bool(true ), Bool(false)),\n // BLT -> List(Bool(true ), Bool(false)),\n // BLTU -> List(Bool(true ), Bool(false))\n // ))\n //val is_br :: nothing :: Nil = csignals\n\n val is_br = (inst(6,0) === \"b1100011\".U)\n\n val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W))\n val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W))\n\n Mux(is_br, br_targ, jal_targ)\n }\n}\n\n/**\n * Object to return the lowest bit position after the head.\n */\nobject AgePriorityEncoder\n{\n def apply(in: Seq[Bool], head: UInt): UInt = {\n val n = in.size\n val width = log2Ceil(in.size)\n val n_padded = 1 << width\n val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in\n val idx = PriorityEncoder(temp_vec)\n idx(width-1, 0) //discard msb\n }\n}\n\n/**\n * Object to determine whether queue\n * index i0 is older than index i1.\n */\nobject IsOlder\n{\n def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head))\n}\n\nobject IsYoungerMask\n{\n def apply(i: UInt, head: UInt, n: Integer): UInt = {\n val hi_mask = ~MaskLower(UIntToOH(i)(n-1,0))\n val lo_mask = ~MaskUpper(UIntToOH(head)(n-1,0))\n Mux(i < head, hi_mask & lo_mask, hi_mask | lo_mask)(n-1,0)\n }\n}\n\n/**\n * Set all bits at or below the highest order '1'.\n */\nobject MaskLower\n{\n def apply(in: UInt) = {\n val n = in.getWidth\n (0 until n).map(i => in >> i.U).reduce(_|_)\n }\n}\n\n/**\n * Set all bits at or above the lowest order '1'.\n */\nobject MaskUpper\n{\n def apply(in: UInt) = {\n val n = in.getWidth\n (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_)\n }\n}\n\n/**\n * Transpose a matrix of Chisel Vecs.\n */\nobject Transpose\n{\n def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = {\n val n = in(0).size\n VecInit((0 until n).map(i => VecInit(in.map(row => row(i)))))\n }\n}\n\n/**\n * N-wide one-hot priority encoder.\n */\nobject SelectFirstN\n{\n def apply(in: UInt, n: Int) = {\n val sels = Wire(Vec(n, UInt(in.getWidth.W)))\n var mask = in\n\n for (i <- 0 until n) {\n sels(i) := PriorityEncoderOH(mask)\n mask = mask & ~sels(i)\n }\n\n sels\n }\n}\n\n/**\n * Connect the first k of n valid input interfaces to k output interfaces.\n */\nclass Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module\n{\n require(n >= k)\n\n val io = IO(new Bundle {\n val in = Vec(n, Flipped(DecoupledIO(gen)))\n val out = Vec(k, DecoupledIO(gen))\n })\n\n if (n == k) {\n io.out <> io.in\n } else {\n val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c))\n val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col =>\n (col zip io.in.map(_.valid)) map {case (c,v) => c && v})\n val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_))\n val out_valids = sels map (col => col.reduce(_||_))\n val out_data = sels map (s => Mux1H(s, io.in.map(_.bits)))\n\n in_readys zip io.in foreach {case (r,i) => i.ready := r}\n out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d}\n }\n}\n\n/**\n * Create a queue that can be killed with a branch kill signal.\n * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq).\n */\nclass BranchKillableQueue[T <: boom.v4.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v4.common.MicroOp => Bool = u => true.B, fastDeq: Boolean = false)\n (implicit p: org.chipsalliance.cde.config.Parameters)\n extends boom.v4.common.BoomModule()(p)\n with boom.v4.common.HasBoomCoreParameters\n{\n val io = IO(new Bundle {\n val enq = Flipped(Decoupled(gen))\n val deq = Decoupled(gen)\n\n val brupdate = Input(new BrUpdateInfo())\n val flush = Input(Bool())\n\n val empty = Output(Bool())\n val count = Output(UInt(log2Ceil(entries).W))\n })\n\n if (fastDeq && entries > 1) {\n // Pipeline dequeue selection so the mux gets an entire cycle\n val main = Module(new BranchKillableQueue(gen, entries-1, flush_fn, false))\n val out_reg = Reg(gen)\n val out_valid = RegInit(false.B)\n val out_uop = Reg(new MicroOp)\n\n main.io.enq <> io.enq\n main.io.brupdate := io.brupdate\n main.io.flush := io.flush\n io.empty := main.io.empty && !out_valid\n io.count := main.io.count + out_valid\n\n io.deq.valid := out_valid\n io.deq.bits := out_reg\n io.deq.bits.uop := out_uop\n\n out_uop := UpdateBrMask(io.brupdate, out_uop)\n out_valid := out_valid && !IsKilledByBranch(io.brupdate, false.B, out_uop) && !(io.flush && flush_fn(out_uop))\n\n main.io.deq.ready := false.B\n when (io.deq.fire || !out_valid) {\n out_valid := main.io.deq.valid && !IsKilledByBranch(io.brupdate, false.B, main.io.deq.bits.uop) && !(io.flush && flush_fn(main.io.deq.bits.uop))\n out_reg := main.io.deq.bits\n out_uop := UpdateBrMask(io.brupdate, main.io.deq.bits.uop)\n main.io.deq.ready := true.B\n }\n\n } else {\n val ram = Mem(entries, gen)\n val valids = RegInit(VecInit(Seq.fill(entries) {false.B}))\n val uops = Reg(Vec(entries, new MicroOp))\n\n val enq_ptr = Counter(entries)\n val deq_ptr = Counter(entries)\n val maybe_full = RegInit(false.B)\n\n val ptr_match = enq_ptr.value === deq_ptr.value\n io.empty := ptr_match && !maybe_full\n val full = ptr_match && maybe_full\n val do_enq = WireInit(io.enq.fire && !IsKilledByBranch(io.brupdate, false.B, io.enq.bits.uop) && !(io.flush && flush_fn(io.enq.bits.uop)))\n val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty)\n\n for (i <- 0 until entries) {\n val mask = uops(i).br_mask\n val uop = uops(i)\n valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, false.B, mask) && !(io.flush && flush_fn(uop))\n when (valids(i)) {\n uops(i).br_mask := GetNewBrMask(io.brupdate, mask)\n }\n }\n\n when (do_enq) {\n ram(enq_ptr.value) := io.enq.bits\n valids(enq_ptr.value) := true.B\n uops(enq_ptr.value) := io.enq.bits.uop\n uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)\n enq_ptr.inc()\n }\n\n when (do_deq) {\n valids(deq_ptr.value) := false.B\n deq_ptr.inc()\n }\n\n when (do_enq =/= do_deq) {\n maybe_full := do_enq\n }\n\n io.enq.ready := !full\n\n val out = Wire(gen)\n out := ram(deq_ptr.value)\n out.uop := uops(deq_ptr.value)\n io.deq.valid := !io.empty && valids(deq_ptr.value)\n io.deq.bits := out\n\n val ptr_diff = enq_ptr.value - deq_ptr.value\n if (isPow2(entries)) {\n io.count := Cat(maybe_full && ptr_match, ptr_diff)\n }\n else {\n io.count := Mux(ptr_match,\n Mux(maybe_full,\n entries.asUInt, 0.U),\n Mux(deq_ptr.value > enq_ptr.value,\n entries.asUInt + ptr_diff, ptr_diff))\n }\n }\n}\n\n// ------------------------------------------\n// Printf helper functions\n// ------------------------------------------\n\nobject BoolToChar\n{\n /**\n * Take in a Chisel Bool and convert it into a Str\n * based on the Chars given\n *\n * @param c_bool Chisel Bool\n * @param trueChar Scala Char if bool is true\n * @param falseChar Scala Char if bool is false\n * @return UInt ASCII Char for \"trueChar\" or \"falseChar\"\n */\n def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = {\n Mux(c_bool, Str(trueChar), Str(falseChar))\n }\n}\n\nobject CfiTypeToChars\n{\n /**\n * Get a Vec of Strs that can be used for printing\n *\n * @param cfi_type specific cfi type\n * @return Vec of Strs (must be indexed to get specific char)\n */\n def apply(cfi_type: UInt) = {\n val strings = Seq(\"----\", \"BR \", \"JAL \", \"JALR\")\n val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })\n multiVec(cfi_type)\n }\n}\n\nobject BpdTypeToChars\n{\n /**\n * Get a Vec of Strs that can be used for printing\n *\n * @param bpd_type specific bpd type\n * @return Vec of Strs (must be indexed to get specific char)\n */\n def apply(bpd_type: UInt) = {\n val strings = Seq(\"BR \", \"JUMP\", \"----\", \"RET \", \"----\", \"CALL\", \"----\", \"----\")\n val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })\n multiVec(bpd_type)\n }\n}\n\nobject RobTypeToChars\n{\n /**\n * Get a Vec of Strs that can be used for printing\n *\n * @param rob_type specific rob type\n * @return Vec of Strs (must be indexed to get specific char)\n */\n def apply(rob_type: UInt) = {\n val strings = Seq(\"RST\", \"NML\", \"RBK\", \" WT\")\n val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })\n multiVec(rob_type)\n }\n}\n\nobject XRegToChars\n{\n /**\n * Get a Vec of Strs that can be used for printing\n *\n * @param xreg specific register number\n * @return Vec of Strs (must be indexed to get specific char)\n */\n def apply(xreg: UInt) = {\n val strings = Seq(\" x0\", \" ra\", \" sp\", \" gp\",\n \" tp\", \" t0\", \" t1\", \" t2\",\n \" s0\", \" s1\", \" a0\", \" a1\",\n \" a2\", \" a3\", \" a4\", \" a5\",\n \" a6\", \" a7\", \" s2\", \" s3\",\n \" s4\", \" s5\", \" s6\", \" s7\",\n \" s8\", \" s9\", \"s10\", \"s11\",\n \" t3\", \" t4\", \" t5\", \" t6\")\n val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })\n multiVec(xreg)\n }\n}\n\nobject FPRegToChars\n{\n /**\n * Get a Vec of Strs that can be used for printing\n *\n * @param fpreg specific register number\n * @return Vec of Strs (must be indexed to get specific char)\n */\n def apply(fpreg: UInt) = {\n val strings = Seq(\" ft0\", \" ft1\", \" ft2\", \" ft3\",\n \" ft4\", \" ft5\", \" ft6\", \" ft7\",\n \" fs0\", \" fs1\", \" fa0\", \" fa1\",\n \" fa2\", \" fa3\", \" fa4\", \" fa5\",\n \" fa6\", \" fa7\", \" fs2\", \" fs3\",\n \" fs4\", \" fs5\", \" fs6\", \" fs7\",\n \" fs8\", \" fs9\", \"fs10\", \"fs11\",\n \" ft8\", \" ft9\", \"ft10\", \"ft11\")\n val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })\n multiVec(fpreg)\n }\n}\n\nobject BoomCoreStringPrefix\n{\n /**\n * Add prefix to BOOM strings (currently only adds the hartId)\n *\n * @param strs list of strings\n * @return String combining the list with the prefix per line\n */\n def apply(strs: String*)(implicit p: Parameters) = {\n val prefix = \"[C\" + s\"${p(TileKey).tileId}\" + \"] \"\n strs.map(str => prefix + str + \"\\n\").mkString(\"\")\n }\n}\n\nclass BranchKillablePipeline[T <: boom.v4.common.HasBoomUOP](gen: T, stages: Int)\n (implicit p: org.chipsalliance.cde.config.Parameters)\n extends boom.v4.common.BoomModule()(p)\n with boom.v4.common.HasBoomCoreParameters\n{\n val io = IO(new Bundle {\n val req = Input(Valid(gen))\n val flush = Input(Bool())\n val brupdate = Input(new BrUpdateInfo)\n val resp = Output(Vec(stages, Valid(gen)))\n })\n require(stages > 0)\n val uops = Reg(Vec(stages, Valid(gen)))\n uops(0).valid := io.req.valid && !IsKilledByBranch(io.brupdate, io.flush, io.req.bits)\n uops(0).bits := UpdateBrMask(io.brupdate, io.req.bits)\n for (i <- 1 until stages) {\n uops(i).valid := uops(i-1).valid && !IsKilledByBranch(io.brupdate, io.flush, uops(i-1).bits)\n uops(i).bits := UpdateBrMask(io.brupdate, uops(i-1).bits)\n }\n\n for (i <- 0 until stages) { when (reset.asBool) { uops(i).valid := false.B } }\n\n io.resp := uops\n\n}\nFile issue-slot.scala:\n//******************************************************************************\n// Copyright (c) 2015 - 2018, The Regents of the University of California (Regents).\n// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.\n//------------------------------------------------------------------------------\n\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n// RISCV Processor Issue Slot Logic\n//--------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n//\n// Note: stores (and AMOs) are \"broken down\" into 2 uops, but stored within a single issue-slot.\n// TODO XXX make a separate issueSlot for MemoryIssueSlots, and only they break apart stores.\n// TODO Disable ldspec for FP queue.\n\npackage boom.v4.exu\n\nimport chisel3._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config.Parameters\n\nimport boom.v4.common._\nimport boom.v4.util._\n\nclass IssueSlotIO(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomBundle\n{\n val valid = Output(Bool())\n val will_be_valid = Output(Bool()) // TODO code review, do we need this signal so explicitely?\n val request = Output(Bool())\n val grant = Input(Bool())\n val iss_uop = Output(new MicroOp())\n\n val in_uop = Input(Valid(new MicroOp())) // if valid, this WILL overwrite an entry!\n val out_uop = Output(new MicroOp())\n\n\n val brupdate = Input(new BrUpdateInfo())\n val kill = Input(Bool()) // pipeline flush\n val clear = Input(Bool()) // entry being moved elsewhere (not mutually exclusive with grant)\n\n val squash_grant = Input(Bool())\n\n val wakeup_ports = Flipped(Vec(numWakeupPorts, Valid(new Wakeup)))\n val pred_wakeup_port = Flipped(Valid(UInt(log2Ceil(ftqSz).W)))\n val child_rebusys = Input(UInt(aluWidth.W))\n}\n\nclass IssueSlot(val numWakeupPorts: Int, val isMem: Boolean, val isFp: Boolean)(implicit p: Parameters)\n extends BoomModule\n{\n val io = IO(new IssueSlotIO(numWakeupPorts))\n\n\n val slot_valid = RegInit(false.B)\n val slot_uop = Reg(new MicroOp())\n\n val next_valid = WireInit(slot_valid)\n val next_uop = WireInit(UpdateBrMask(io.brupdate, slot_uop))\n\n val killed = IsKilledByBranch(io.brupdate, io.kill, slot_uop)\n\n io.valid := slot_valid\n io.out_uop := next_uop\n io.will_be_valid := next_valid && !killed\n\n when (io.kill) {\n slot_valid := false.B\n } .elsewhen (io.in_uop.valid) {\n slot_valid := true.B\n } .elsewhen (io.clear) {\n slot_valid := false.B\n } .otherwise {\n slot_valid := next_valid && !killed\n }\n\n when (io.in_uop.valid) {\n slot_uop := io.in_uop.bits\n assert (!slot_valid || io.clear || io.kill)\n } .otherwise {\n slot_uop := next_uop\n }\n\n\n // Wakeups\n next_uop.iw_p1_bypass_hint := false.B\n next_uop.iw_p2_bypass_hint := false.B\n next_uop.iw_p3_bypass_hint := false.B\n next_uop.iw_p1_speculative_child := 0.U\n next_uop.iw_p2_speculative_child := 0.U\n\n val rebusied_prs1 = WireInit(false.B)\n val rebusied_prs2 = WireInit(false.B)\n val rebusied = rebusied_prs1 || rebusied_prs2\n\n val prs1_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs1 }\n val prs2_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs2 }\n val prs3_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs3 }\n val prs1_wakeups = (io.wakeup_ports zip prs1_matches).map { case (w,m) => w.valid && m }\n val prs2_wakeups = (io.wakeup_ports zip prs2_matches).map { case (w,m) => w.valid && m }\n val prs3_wakeups = (io.wakeup_ports zip prs3_matches).map { case (w,m) => w.valid && m }\n val prs1_rebusys = (io.wakeup_ports zip prs1_matches).map { case (w,m) => w.bits.rebusy && m }\n val prs2_rebusys = (io.wakeup_ports zip prs2_matches).map { case (w,m) => w.bits.rebusy && m }\n val bypassables = io.wakeup_ports.map { w => w.bits.bypassable }\n val speculative_masks = io.wakeup_ports.map { w => w.bits.speculative_mask }\n\n when (prs1_wakeups.reduce(_||_)) {\n next_uop.prs1_busy := false.B\n next_uop.iw_p1_speculative_child := Mux1H(prs1_wakeups, speculative_masks)\n next_uop.iw_p1_bypass_hint := Mux1H(prs1_wakeups, bypassables)\n }\n when ((prs1_rebusys.reduce(_||_) || ((io.child_rebusys & slot_uop.iw_p1_speculative_child) =/= 0.U)) &&\n slot_uop.lrs1_rtype === RT_FIX) {\n next_uop.prs1_busy := true.B\n rebusied_prs1 := true.B\n }\n when (prs2_wakeups.reduce(_||_)) {\n next_uop.prs2_busy := false.B\n next_uop.iw_p2_speculative_child := Mux1H(prs2_wakeups, speculative_masks)\n next_uop.iw_p2_bypass_hint := Mux1H(prs2_wakeups, bypassables)\n }\n when ((prs2_rebusys.reduce(_||_) || ((io.child_rebusys & slot_uop.iw_p2_speculative_child) =/= 0.U)) &&\n slot_uop.lrs2_rtype === RT_FIX) {\n next_uop.prs2_busy := true.B\n rebusied_prs2 := true.B\n }\n\n when (prs3_wakeups.reduce(_||_)) {\n next_uop.prs3_busy := false.B\n next_uop.iw_p3_bypass_hint := Mux1H(prs3_wakeups, bypassables)\n }\n when (io.pred_wakeup_port.valid && io.pred_wakeup_port.bits === slot_uop.ppred) {\n next_uop.ppred_busy := false.B\n }\n\n val iss_ready = !slot_uop.prs1_busy && !slot_uop.prs2_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && !(slot_uop.prs3_busy && isFp.B)\n val agen_ready = (slot_uop.fu_code(FC_AGEN) && !slot_uop.prs1_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && isMem.B)\n val dgen_ready = (slot_uop.fu_code(FC_DGEN) && !slot_uop.prs2_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && isMem.B)\n\n io.request := slot_valid && !slot_uop.iw_issued && (\n iss_ready || agen_ready || dgen_ready\n )\n\n io.iss_uop := slot_uop\n\n // Update state for current micro-op based on grant\n\n\n next_uop.iw_issued := false.B\n next_uop.iw_issued_partial_agen := false.B\n next_uop.iw_issued_partial_dgen := false.B\n when (io.grant && !io.squash_grant) {\n next_uop.iw_issued := true.B\n }\n\n if (isMem) {\n when (slot_uop.fu_code(FC_AGEN) && slot_uop.fu_code(FC_DGEN)) {\n when (agen_ready) {\n // Issue the AGEN, next slot entry is a DGEN\n when (io.grant && !io.squash_grant) {\n next_uop.iw_issued_partial_agen := true.B\n }\n io.iss_uop.fu_code(FC_AGEN) := true.B\n io.iss_uop.fu_code(FC_DGEN) := false.B\n } .otherwise {\n // Issue the DGEN, next slot entry is the AGEN\n when (io.grant && !io.squash_grant) {\n next_uop.iw_issued_partial_dgen := true.B\n }\n io.iss_uop.fu_code(FC_AGEN) := false.B\n io.iss_uop.fu_code(FC_DGEN) := true.B\n io.iss_uop.imm_sel := IS_N\n io.iss_uop.prs1 := slot_uop.prs2\n io.iss_uop.lrs1_rtype := slot_uop.lrs2_rtype\n io.iss_uop.iw_p1_bypass_hint := slot_uop.iw_p2_bypass_hint\n }\n } .elsewhen (slot_uop.fu_code(FC_DGEN)) {\n io.iss_uop.imm_sel := IS_N\n io.iss_uop.prs1 := slot_uop.prs2\n io.iss_uop.lrs1_rtype := slot_uop.lrs2_rtype\n io.iss_uop.iw_p1_bypass_hint := slot_uop.iw_p2_bypass_hint\n }\n io.iss_uop.lrs2_rtype := RT_X\n io.iss_uop.prs2 := io.iss_uop.prs1 // helps with DCE\n }\n\n when (slot_valid && slot_uop.iw_issued) {\n next_valid := rebusied\n if (isMem) {\n when (slot_uop.iw_issued_partial_agen) {\n next_valid := true.B\n when (!rebusied_prs1) {\n next_uop.fu_code(FC_AGEN) := false.B\n next_uop.fu_code(FC_DGEN) := true.B\n }\n } .elsewhen (slot_uop.iw_issued_partial_dgen) {\n next_valid := true.B\n when (!rebusied_prs2) {\n next_uop.fu_code(FC_AGEN) := true.B\n next_uop.fu_code(FC_DGEN) := false.B\n }\n }\n\n }\n }\n\n\n\n\n}\n"},"response":{"kind":"string","value":"module IssueSlot_76(\t// @[issue-slot.scala:49:7]\n input clock,\t// @[issue-slot.scala:49:7]\n input reset,\t// @[issue-slot.scala:49:7]\n output io_valid,\t// @[issue-slot.scala:52:14]\n output io_will_be_valid,\t// @[issue-slot.scala:52:14]\n output io_request,\t// @[issue-slot.scala:52:14]\n input io_grant,\t// @[issue-slot.scala:52:14]\n output [31:0] io_iss_uop_inst,\t// @[issue-slot.scala:52:14]\n output [31:0] io_iss_uop_debug_inst,\t// @[issue-slot.scala:52:14]\n output io_iss_uop_is_rvc,\t// @[issue-slot.scala:52:14]\n output [39:0] io_iss_uop_debug_pc,\t// @[issue-slot.scala:52:14]\n output io_iss_uop_iq_type_0,\t// @[issue-slot.scala:52:14]\n output io_iss_uop_iq_type_1,\t// @[issue-slot.scala:52:14]\n output io_iss_uop_iq_type_2,\t// @[issue-slot.scala:52:14]\n output io_iss_uop_iq_type_3,\t// @[issue-slot.scala:52:14]\n output io_iss_uop_fu_code_0,\t// @[issue-slot.scala:52:14]\n output io_iss_uop_fu_code_1,\t// @[issue-slot.scala:52:14]\n output io_iss_uop_fu_code_2,\t// @[issue-slot.scala:52:14]\n output io_iss_uop_fu_code_3,\t// @[issue-slot.scala:52:14]\n output io_iss_uop_fu_code_4,\t// @[issue-slot.scala:52:14]\n output io_iss_uop_fu_code_5,\t// @[issue-slot.scala:52:14]\n output io_iss_uop_fu_code_6,\t// @[issue-slot.scala:52:14]\n output io_iss_uop_fu_code_7,\t// @[issue-slot.scala:52:14]\n output io_iss_uop_fu_code_8,\t// @[issue-slot.scala:52:14]\n output io_iss_uop_fu_code_9,\t// @[issue-slot.scala:52:14]\n output io_iss_uop_iw_issued,\t// @[issue-slot.scala:52:14]\n output [2:0] io_iss_uop_iw_p1_speculative_child,\t// @[issue-slot.scala:52:14]\n output [2:0] io_iss_uop_iw_p2_speculative_child,\t// @[issue-slot.scala:52:14]\n output io_iss_uop_iw_p1_bypass_hint,\t// @[issue-slot.scala:52:14]\n output io_iss_uop_iw_p2_bypass_hint,\t// @[issue-slot.scala:52:14]\n output io_iss_uop_iw_p3_bypass_hint,\t// @[issue-slot.scala:52:14]\n output [2:0] io_iss_uop_dis_col_sel,\t// @[issue-slot.scala:52:14]\n output [15:0] io_iss_uop_br_mask,\t// @[issue-slot.scala:52:14]\n output [3:0] io_iss_uop_br_tag,\t// @[issue-slot.scala:52:14]\n output [3:0] io_iss_uop_br_type,\t// @[issue-slot.scala:52:14]\n output io_iss_uop_is_sfb,\t// @[issue-slot.scala:52:14]\n output io_iss_uop_is_fence,\t// @[issue-slot.scala:52:14]\n output io_iss_uop_is_fencei,\t// @[issue-slot.scala:52:14]\n output io_iss_uop_is_sfence,\t// @[issue-slot.scala:52:14]\n output io_iss_uop_is_amo,\t// @[issue-slot.scala:52:14]\n output io_iss_uop_is_eret,\t// @[issue-slot.scala:52:14]\n output io_iss_uop_is_sys_pc2epc,\t// @[issue-slot.scala:52:14]\n output io_iss_uop_is_rocc,\t// @[issue-slot.scala:52:14]\n output io_iss_uop_is_mov,\t// @[issue-slot.scala:52:14]\n output [4:0] io_iss_uop_ftq_idx,\t// @[issue-slot.scala:52:14]\n output io_iss_uop_edge_inst,\t// @[issue-slot.scala:52:14]\n output [5:0] io_iss_uop_pc_lob,\t// @[issue-slot.scala:52:14]\n output io_iss_uop_taken,\t// @[issue-slot.scala:52:14]\n output io_iss_uop_imm_rename,\t// @[issue-slot.scala:52:14]\n output [2:0] io_iss_uop_imm_sel,\t// @[issue-slot.scala:52:14]\n output [4:0] io_iss_uop_pimm,\t// @[issue-slot.scala:52:14]\n output [19:0] io_iss_uop_imm_packed,\t// @[issue-slot.scala:52:14]\n output [1:0] io_iss_uop_op1_sel,\t// @[issue-slot.scala:52:14]\n output [2:0] io_iss_uop_op2_sel,\t// @[issue-slot.scala:52:14]\n output io_iss_uop_fp_ctrl_ldst,\t// @[issue-slot.scala:52:14]\n output io_iss_uop_fp_ctrl_wen,\t// @[issue-slot.scala:52:14]\n output io_iss_uop_fp_ctrl_ren1,\t// @[issue-slot.scala:52:14]\n output io_iss_uop_fp_ctrl_ren2,\t// @[issue-slot.scala:52:14]\n output io_iss_uop_fp_ctrl_ren3,\t// @[issue-slot.scala:52:14]\n output io_iss_uop_fp_ctrl_swap12,\t// @[issue-slot.scala:52:14]\n output io_iss_uop_fp_ctrl_swap23,\t// @[issue-slot.scala:52:14]\n output [1:0] io_iss_uop_fp_ctrl_typeTagIn,\t// @[issue-slot.scala:52:14]\n output [1:0] io_iss_uop_fp_ctrl_typeTagOut,\t// @[issue-slot.scala:52:14]\n output io_iss_uop_fp_ctrl_fromint,\t// @[issue-slot.scala:52:14]\n output io_iss_uop_fp_ctrl_toint,\t// @[issue-slot.scala:52:14]\n output io_iss_uop_fp_ctrl_fastpipe,\t// @[issue-slot.scala:52:14]\n output io_iss_uop_fp_ctrl_fma,\t// @[issue-slot.scala:52:14]\n output io_iss_uop_fp_ctrl_div,\t// @[issue-slot.scala:52:14]\n output io_iss_uop_fp_ctrl_sqrt,\t// @[issue-slot.scala:52:14]\n output io_iss_uop_fp_ctrl_wflags,\t// @[issue-slot.scala:52:14]\n output io_iss_uop_fp_ctrl_vec,\t// @[issue-slot.scala:52:14]\n output [6:0] io_iss_uop_rob_idx,\t// @[issue-slot.scala:52:14]\n output [4:0] io_iss_uop_ldq_idx,\t// @[issue-slot.scala:52:14]\n output [4:0] io_iss_uop_stq_idx,\t// @[issue-slot.scala:52:14]\n output [1:0] io_iss_uop_rxq_idx,\t// @[issue-slot.scala:52:14]\n output [6:0] io_iss_uop_pdst,\t// @[issue-slot.scala:52:14]\n output [6:0] io_iss_uop_prs1,\t// @[issue-slot.scala:52:14]\n output [6:0] io_iss_uop_prs2,\t// @[issue-slot.scala:52:14]\n output [6:0] io_iss_uop_prs3,\t// @[issue-slot.scala:52:14]\n output [4:0] io_iss_uop_ppred,\t// @[issue-slot.scala:52:14]\n output io_iss_uop_prs1_busy,\t// @[issue-slot.scala:52:14]\n output io_iss_uop_prs2_busy,\t// @[issue-slot.scala:52:14]\n output io_iss_uop_prs3_busy,\t// @[issue-slot.scala:52:14]\n output io_iss_uop_ppred_busy,\t// @[issue-slot.scala:52:14]\n output [6:0] io_iss_uop_stale_pdst,\t// @[issue-slot.scala:52:14]\n output io_iss_uop_exception,\t// @[issue-slot.scala:52:14]\n output [63:0] io_iss_uop_exc_cause,\t// @[issue-slot.scala:52:14]\n output [4:0] io_iss_uop_mem_cmd,\t// @[issue-slot.scala:52:14]\n output [1:0] io_iss_uop_mem_size,\t// @[issue-slot.scala:52:14]\n output io_iss_uop_mem_signed,\t// @[issue-slot.scala:52:14]\n output io_iss_uop_uses_ldq,\t// @[issue-slot.scala:52:14]\n output io_iss_uop_uses_stq,\t// @[issue-slot.scala:52:14]\n output io_iss_uop_is_unique,\t// @[issue-slot.scala:52:14]\n output io_iss_uop_flush_on_commit,\t// @[issue-slot.scala:52:14]\n output [2:0] io_iss_uop_csr_cmd,\t// @[issue-slot.scala:52:14]\n output io_iss_uop_ldst_is_rs1,\t// @[issue-slot.scala:52:14]\n output [5:0] io_iss_uop_ldst,\t// @[issue-slot.scala:52:14]\n output [5:0] io_iss_uop_lrs1,\t// @[issue-slot.scala:52:14]\n output [5:0] io_iss_uop_lrs2,\t// @[issue-slot.scala:52:14]\n output [5:0] io_iss_uop_lrs3,\t// @[issue-slot.scala:52:14]\n output [1:0] io_iss_uop_dst_rtype,\t// @[issue-slot.scala:52:14]\n output [1:0] io_iss_uop_lrs1_rtype,\t// @[issue-slot.scala:52:14]\n output [1:0] io_iss_uop_lrs2_rtype,\t// @[issue-slot.scala:52:14]\n output io_iss_uop_frs3_en,\t// @[issue-slot.scala:52:14]\n output io_iss_uop_fcn_dw,\t// @[issue-slot.scala:52:14]\n output [4:0] io_iss_uop_fcn_op,\t// @[issue-slot.scala:52:14]\n output io_iss_uop_fp_val,\t// @[issue-slot.scala:52:14]\n output [2:0] io_iss_uop_fp_rm,\t// @[issue-slot.scala:52:14]\n output [1:0] io_iss_uop_fp_typ,\t// @[issue-slot.scala:52:14]\n output io_iss_uop_xcpt_pf_if,\t// @[issue-slot.scala:52:14]\n output io_iss_uop_xcpt_ae_if,\t// @[issue-slot.scala:52:14]\n output io_iss_uop_xcpt_ma_if,\t// @[issue-slot.scala:52:14]\n output io_iss_uop_bp_debug_if,\t// @[issue-slot.scala:52:14]\n output io_iss_uop_bp_xcpt_if,\t// @[issue-slot.scala:52:14]\n output [2:0] io_iss_uop_debug_fsrc,\t// @[issue-slot.scala:52:14]\n output [2:0] io_iss_uop_debug_tsrc,\t// @[issue-slot.scala:52:14]\n input io_in_uop_valid,\t// @[issue-slot.scala:52:14]\n input [31:0] io_in_uop_bits_inst,\t// @[issue-slot.scala:52:14]\n input [31:0] io_in_uop_bits_debug_inst,\t// @[issue-slot.scala:52:14]\n input io_in_uop_bits_is_rvc,\t// @[issue-slot.scala:52:14]\n input [39:0] io_in_uop_bits_debug_pc,\t// @[issue-slot.scala:52:14]\n input io_in_uop_bits_iq_type_0,\t// @[issue-slot.scala:52:14]\n input io_in_uop_bits_iq_type_1,\t// @[issue-slot.scala:52:14]\n input io_in_uop_bits_iq_type_2,\t// @[issue-slot.scala:52:14]\n input io_in_uop_bits_iq_type_3,\t// @[issue-slot.scala:52:14]\n input io_in_uop_bits_fu_code_0,\t// @[issue-slot.scala:52:14]\n input io_in_uop_bits_fu_code_1,\t// @[issue-slot.scala:52:14]\n input io_in_uop_bits_fu_code_2,\t// @[issue-slot.scala:52:14]\n input io_in_uop_bits_fu_code_3,\t// @[issue-slot.scala:52:14]\n input io_in_uop_bits_fu_code_4,\t// @[issue-slot.scala:52:14]\n input io_in_uop_bits_fu_code_5,\t// @[issue-slot.scala:52:14]\n input io_in_uop_bits_fu_code_6,\t// @[issue-slot.scala:52:14]\n input io_in_uop_bits_fu_code_7,\t// @[issue-slot.scala:52:14]\n input io_in_uop_bits_fu_code_8,\t// @[issue-slot.scala:52:14]\n input io_in_uop_bits_fu_code_9,\t// @[issue-slot.scala:52:14]\n input io_in_uop_bits_iw_issued,\t// @[issue-slot.scala:52:14]\n input [2:0] io_in_uop_bits_iw_p1_speculative_child,\t// @[issue-slot.scala:52:14]\n input [2:0] io_in_uop_bits_iw_p2_speculative_child,\t// @[issue-slot.scala:52:14]\n input io_in_uop_bits_iw_p1_bypass_hint,\t// @[issue-slot.scala:52:14]\n input io_in_uop_bits_iw_p2_bypass_hint,\t// @[issue-slot.scala:52:14]\n input io_in_uop_bits_iw_p3_bypass_hint,\t// @[issue-slot.scala:52:14]\n input [2:0] io_in_uop_bits_dis_col_sel,\t// @[issue-slot.scala:52:14]\n input [15:0] io_in_uop_bits_br_mask,\t// @[issue-slot.scala:52:14]\n input [3:0] io_in_uop_bits_br_tag,\t// @[issue-slot.scala:52:14]\n input [3:0] io_in_uop_bits_br_type,\t// @[issue-slot.scala:52:14]\n input io_in_uop_bits_is_sfb,\t// @[issue-slot.scala:52:14]\n input io_in_uop_bits_is_fence,\t// @[issue-slot.scala:52:14]\n input io_in_uop_bits_is_fencei,\t// @[issue-slot.scala:52:14]\n input io_in_uop_bits_is_sfence,\t// @[issue-slot.scala:52:14]\n input io_in_uop_bits_is_amo,\t// @[issue-slot.scala:52:14]\n input io_in_uop_bits_is_eret,\t// @[issue-slot.scala:52:14]\n input io_in_uop_bits_is_sys_pc2epc,\t// @[issue-slot.scala:52:14]\n input io_in_uop_bits_is_rocc,\t// @[issue-slot.scala:52:14]\n input io_in_uop_bits_is_mov,\t// @[issue-slot.scala:52:14]\n input [4:0] io_in_uop_bits_ftq_idx,\t// @[issue-slot.scala:52:14]\n input io_in_uop_bits_edge_inst,\t// @[issue-slot.scala:52:14]\n input [5:0] io_in_uop_bits_pc_lob,\t// @[issue-slot.scala:52:14]\n input io_in_uop_bits_taken,\t// @[issue-slot.scala:52:14]\n input io_in_uop_bits_imm_rename,\t// @[issue-slot.scala:52:14]\n input [2:0] io_in_uop_bits_imm_sel,\t// @[issue-slot.scala:52:14]\n input [4:0] io_in_uop_bits_pimm,\t// @[issue-slot.scala:52:14]\n input [19:0] io_in_uop_bits_imm_packed,\t// @[issue-slot.scala:52:14]\n input [1:0] io_in_uop_bits_op1_sel,\t// @[issue-slot.scala:52:14]\n input [2:0] io_in_uop_bits_op2_sel,\t// @[issue-slot.scala:52:14]\n input io_in_uop_bits_fp_ctrl_ldst,\t// @[issue-slot.scala:52:14]\n input io_in_uop_bits_fp_ctrl_wen,\t// @[issue-slot.scala:52:14]\n input io_in_uop_bits_fp_ctrl_ren1,\t// @[issue-slot.scala:52:14]\n input io_in_uop_bits_fp_ctrl_ren2,\t// @[issue-slot.scala:52:14]\n input io_in_uop_bits_fp_ctrl_ren3,\t// @[issue-slot.scala:52:14]\n input io_in_uop_bits_fp_ctrl_swap12,\t// @[issue-slot.scala:52:14]\n input io_in_uop_bits_fp_ctrl_swap23,\t// @[issue-slot.scala:52:14]\n input [1:0] io_in_uop_bits_fp_ctrl_typeTagIn,\t// @[issue-slot.scala:52:14]\n input [1:0] io_in_uop_bits_fp_ctrl_typeTagOut,\t// @[issue-slot.scala:52:14]\n input io_in_uop_bits_fp_ctrl_fromint,\t// @[issue-slot.scala:52:14]\n input io_in_uop_bits_fp_ctrl_toint,\t// @[issue-slot.scala:52:14]\n input io_in_uop_bits_fp_ctrl_fastpipe,\t// @[issue-slot.scala:52:14]\n input io_in_uop_bits_fp_ctrl_fma,\t// @[issue-slot.scala:52:14]\n input io_in_uop_bits_fp_ctrl_div,\t// @[issue-slot.scala:52:14]\n input io_in_uop_bits_fp_ctrl_sqrt,\t// @[issue-slot.scala:52:14]\n input io_in_uop_bits_fp_ctrl_wflags,\t// @[issue-slot.scala:52:14]\n input io_in_uop_bits_fp_ctrl_vec,\t// @[issue-slot.scala:52:14]\n input [6:0] io_in_uop_bits_rob_idx,\t// @[issue-slot.scala:52:14]\n input [4:0] io_in_uop_bits_ldq_idx,\t// @[issue-slot.scala:52:14]\n input [4:0] io_in_uop_bits_stq_idx,\t// @[issue-slot.scala:52:14]\n input [1:0] io_in_uop_bits_rxq_idx,\t// @[issue-slot.scala:52:14]\n input [6:0] io_in_uop_bits_pdst,\t// @[issue-slot.scala:52:14]\n input [6:0] io_in_uop_bits_prs1,\t// @[issue-slot.scala:52:14]\n input [6:0] io_in_uop_bits_prs2,\t// @[issue-slot.scala:52:14]\n input [6:0] io_in_uop_bits_prs3,\t// @[issue-slot.scala:52:14]\n input [4:0] io_in_uop_bits_ppred,\t// @[issue-slot.scala:52:14]\n input io_in_uop_bits_prs1_busy,\t// @[issue-slot.scala:52:14]\n input io_in_uop_bits_prs2_busy,\t// @[issue-slot.scala:52:14]\n input io_in_uop_bits_prs3_busy,\t// @[issue-slot.scala:52:14]\n input io_in_uop_bits_ppred_busy,\t// @[issue-slot.scala:52:14]\n input [6:0] io_in_uop_bits_stale_pdst,\t// @[issue-slot.scala:52:14]\n input io_in_uop_bits_exception,\t// @[issue-slot.scala:52:14]\n input [63:0] io_in_uop_bits_exc_cause,\t// @[issue-slot.scala:52:14]\n input [4:0] io_in_uop_bits_mem_cmd,\t// @[issue-slot.scala:52:14]\n input [1:0] io_in_uop_bits_mem_size,\t// @[issue-slot.scala:52:14]\n input io_in_uop_bits_mem_signed,\t// @[issue-slot.scala:52:14]\n input io_in_uop_bits_uses_ldq,\t// @[issue-slot.scala:52:14]\n input io_in_uop_bits_uses_stq,\t// @[issue-slot.scala:52:14]\n input io_in_uop_bits_is_unique,\t// @[issue-slot.scala:52:14]\n input io_in_uop_bits_flush_on_commit,\t// @[issue-slot.scala:52:14]\n input [2:0] io_in_uop_bits_csr_cmd,\t// @[issue-slot.scala:52:14]\n input io_in_uop_bits_ldst_is_rs1,\t// @[issue-slot.scala:52:14]\n input [5:0] io_in_uop_bits_ldst,\t// @[issue-slot.scala:52:14]\n input [5:0] io_in_uop_bits_lrs1,\t// @[issue-slot.scala:52:14]\n input [5:0] io_in_uop_bits_lrs2,\t// @[issue-slot.scala:52:14]\n input [5:0] io_in_uop_bits_lrs3,\t// @[issue-slot.scala:52:14]\n input [1:0] io_in_uop_bits_dst_rtype,\t// @[issue-slot.scala:52:14]\n input [1:0] io_in_uop_bits_lrs1_rtype,\t// @[issue-slot.scala:52:14]\n input [1:0] io_in_uop_bits_lrs2_rtype,\t// @[issue-slot.scala:52:14]\n input io_in_uop_bits_frs3_en,\t// @[issue-slot.scala:52:14]\n input io_in_uop_bits_fcn_dw,\t// @[issue-slot.scala:52:14]\n input [4:0] io_in_uop_bits_fcn_op,\t// @[issue-slot.scala:52:14]\n input io_in_uop_bits_fp_val,\t// @[issue-slot.scala:52:14]\n input [2:0] io_in_uop_bits_fp_rm,\t// @[issue-slot.scala:52:14]\n input [1:0] io_in_uop_bits_fp_typ,\t// @[issue-slot.scala:52:14]\n input io_in_uop_bits_xcpt_pf_if,\t// @[issue-slot.scala:52:14]\n input io_in_uop_bits_xcpt_ae_if,\t// @[issue-slot.scala:52:14]\n input io_in_uop_bits_xcpt_ma_if,\t// @[issue-slot.scala:52:14]\n input io_in_uop_bits_bp_debug_if,\t// @[issue-slot.scala:52:14]\n input io_in_uop_bits_bp_xcpt_if,\t// @[issue-slot.scala:52:14]\n input [2:0] io_in_uop_bits_debug_fsrc,\t// @[issue-slot.scala:52:14]\n input [2:0] io_in_uop_bits_debug_tsrc,\t// @[issue-slot.scala:52:14]\n output [31:0] io_out_uop_inst,\t// @[issue-slot.scala:52:14]\n output [31:0] io_out_uop_debug_inst,\t// @[issue-slot.scala:52:14]\n output io_out_uop_is_rvc,\t// @[issue-slot.scala:52:14]\n output [39:0] io_out_uop_debug_pc,\t// @[issue-slot.scala:52:14]\n output io_out_uop_iq_type_0,\t// @[issue-slot.scala:52:14]\n output io_out_uop_iq_type_1,\t// @[issue-slot.scala:52:14]\n output io_out_uop_iq_type_2,\t// @[issue-slot.scala:52:14]\n output io_out_uop_iq_type_3,\t// @[issue-slot.scala:52:14]\n output io_out_uop_fu_code_0,\t// @[issue-slot.scala:52:14]\n output io_out_uop_fu_code_1,\t// @[issue-slot.scala:52:14]\n output io_out_uop_fu_code_2,\t// @[issue-slot.scala:52:14]\n output io_out_uop_fu_code_3,\t// @[issue-slot.scala:52:14]\n output io_out_uop_fu_code_4,\t// @[issue-slot.scala:52:14]\n output io_out_uop_fu_code_5,\t// @[issue-slot.scala:52:14]\n output io_out_uop_fu_code_6,\t// @[issue-slot.scala:52:14]\n output io_out_uop_fu_code_7,\t// @[issue-slot.scala:52:14]\n output io_out_uop_fu_code_8,\t// @[issue-slot.scala:52:14]\n output io_out_uop_fu_code_9,\t// @[issue-slot.scala:52:14]\n output io_out_uop_iw_issued,\t// @[issue-slot.scala:52:14]\n output [2:0] io_out_uop_iw_p1_speculative_child,\t// @[issue-slot.scala:52:14]\n output [2:0] io_out_uop_iw_p2_speculative_child,\t// @[issue-slot.scala:52:14]\n output io_out_uop_iw_p1_bypass_hint,\t// @[issue-slot.scala:52:14]\n output io_out_uop_iw_p2_bypass_hint,\t// @[issue-slot.scala:52:14]\n output io_out_uop_iw_p3_bypass_hint,\t// @[issue-slot.scala:52:14]\n output [2:0] io_out_uop_dis_col_sel,\t// @[issue-slot.scala:52:14]\n output [15:0] io_out_uop_br_mask,\t// @[issue-slot.scala:52:14]\n output [3:0] io_out_uop_br_tag,\t// @[issue-slot.scala:52:14]\n output [3:0] io_out_uop_br_type,\t// @[issue-slot.scala:52:14]\n output io_out_uop_is_sfb,\t// @[issue-slot.scala:52:14]\n output io_out_uop_is_fence,\t// @[issue-slot.scala:52:14]\n output io_out_uop_is_fencei,\t// @[issue-slot.scala:52:14]\n output io_out_uop_is_sfence,\t// @[issue-slot.scala:52:14]\n output io_out_uop_is_amo,\t// @[issue-slot.scala:52:14]\n output io_out_uop_is_eret,\t// @[issue-slot.scala:52:14]\n output io_out_uop_is_sys_pc2epc,\t// @[issue-slot.scala:52:14]\n output io_out_uop_is_rocc,\t// @[issue-slot.scala:52:14]\n output io_out_uop_is_mov,\t// @[issue-slot.scala:52:14]\n output [4:0] io_out_uop_ftq_idx,\t// @[issue-slot.scala:52:14]\n output io_out_uop_edge_inst,\t// @[issue-slot.scala:52:14]\n output [5:0] io_out_uop_pc_lob,\t// @[issue-slot.scala:52:14]\n output io_out_uop_taken,\t// @[issue-slot.scala:52:14]\n output io_out_uop_imm_rename,\t// @[issue-slot.scala:52:14]\n output [2:0] io_out_uop_imm_sel,\t// @[issue-slot.scala:52:14]\n output [4:0] io_out_uop_pimm,\t// @[issue-slot.scala:52:14]\n output [19:0] io_out_uop_imm_packed,\t// @[issue-slot.scala:52:14]\n output [1:0] io_out_uop_op1_sel,\t// @[issue-slot.scala:52:14]\n output [2:0] io_out_uop_op2_sel,\t// @[issue-slot.scala:52:14]\n output io_out_uop_fp_ctrl_ldst,\t// @[issue-slot.scala:52:14]\n output io_out_uop_fp_ctrl_wen,\t// @[issue-slot.scala:52:14]\n output io_out_uop_fp_ctrl_ren1,\t// @[issue-slot.scala:52:14]\n output io_out_uop_fp_ctrl_ren2,\t// @[issue-slot.scala:52:14]\n output io_out_uop_fp_ctrl_ren3,\t// @[issue-slot.scala:52:14]\n output io_out_uop_fp_ctrl_swap12,\t// @[issue-slot.scala:52:14]\n output io_out_uop_fp_ctrl_swap23,\t// @[issue-slot.scala:52:14]\n output [1:0] io_out_uop_fp_ctrl_typeTagIn,\t// @[issue-slot.scala:52:14]\n output [1:0] io_out_uop_fp_ctrl_typeTagOut,\t// @[issue-slot.scala:52:14]\n output io_out_uop_fp_ctrl_fromint,\t// @[issue-slot.scala:52:14]\n output io_out_uop_fp_ctrl_toint,\t// @[issue-slot.scala:52:14]\n output io_out_uop_fp_ctrl_fastpipe,\t// @[issue-slot.scala:52:14]\n output io_out_uop_fp_ctrl_fma,\t// @[issue-slot.scala:52:14]\n output io_out_uop_fp_ctrl_div,\t// @[issue-slot.scala:52:14]\n output io_out_uop_fp_ctrl_sqrt,\t// @[issue-slot.scala:52:14]\n output io_out_uop_fp_ctrl_wflags,\t// @[issue-slot.scala:52:14]\n output io_out_uop_fp_ctrl_vec,\t// @[issue-slot.scala:52:14]\n output [6:0] io_out_uop_rob_idx,\t// @[issue-slot.scala:52:14]\n output [4:0] io_out_uop_ldq_idx,\t// @[issue-slot.scala:52:14]\n output [4:0] io_out_uop_stq_idx,\t// @[issue-slot.scala:52:14]\n output [1:0] io_out_uop_rxq_idx,\t// @[issue-slot.scala:52:14]\n output [6:0] io_out_uop_pdst,\t// @[issue-slot.scala:52:14]\n output [6:0] io_out_uop_prs1,\t// @[issue-slot.scala:52:14]\n output [6:0] io_out_uop_prs2,\t// @[issue-slot.scala:52:14]\n output [6:0] io_out_uop_prs3,\t// @[issue-slot.scala:52:14]\n output [4:0] io_out_uop_ppred,\t// @[issue-slot.scala:52:14]\n output io_out_uop_prs1_busy,\t// @[issue-slot.scala:52:14]\n output io_out_uop_prs2_busy,\t// @[issue-slot.scala:52:14]\n output io_out_uop_prs3_busy,\t// @[issue-slot.scala:52:14]\n output io_out_uop_ppred_busy,\t// @[issue-slot.scala:52:14]\n output [6:0] io_out_uop_stale_pdst,\t// @[issue-slot.scala:52:14]\n output io_out_uop_exception,\t// @[issue-slot.scala:52:14]\n output [63:0] io_out_uop_exc_cause,\t// @[issue-slot.scala:52:14]\n output [4:0] io_out_uop_mem_cmd,\t// @[issue-slot.scala:52:14]\n output [1:0] io_out_uop_mem_size,\t// @[issue-slot.scala:52:14]\n output io_out_uop_mem_signed,\t// @[issue-slot.scala:52:14]\n output io_out_uop_uses_ldq,\t// @[issue-slot.scala:52:14]\n output io_out_uop_uses_stq,\t// @[issue-slot.scala:52:14]\n output io_out_uop_is_unique,\t// @[issue-slot.scala:52:14]\n output io_out_uop_flush_on_commit,\t// @[issue-slot.scala:52:14]\n output [2:0] io_out_uop_csr_cmd,\t// @[issue-slot.scala:52:14]\n output io_out_uop_ldst_is_rs1,\t// @[issue-slot.scala:52:14]\n output [5:0] io_out_uop_ldst,\t// @[issue-slot.scala:52:14]\n output [5:0] io_out_uop_lrs1,\t// @[issue-slot.scala:52:14]\n output [5:0] io_out_uop_lrs2,\t// @[issue-slot.scala:52:14]\n output [5:0] io_out_uop_lrs3,\t// @[issue-slot.scala:52:14]\n output [1:0] io_out_uop_dst_rtype,\t// @[issue-slot.scala:52:14]\n output [1:0] io_out_uop_lrs1_rtype,\t// @[issue-slot.scala:52:14]\n output [1:0] io_out_uop_lrs2_rtype,\t// @[issue-slot.scala:52:14]\n output io_out_uop_frs3_en,\t// @[issue-slot.scala:52:14]\n output io_out_uop_fcn_dw,\t// @[issue-slot.scala:52:14]\n output [4:0] io_out_uop_fcn_op,\t// @[issue-slot.scala:52:14]\n output io_out_uop_fp_val,\t// @[issue-slot.scala:52:14]\n output [2:0] io_out_uop_fp_rm,\t// @[issue-slot.scala:52:14]\n output [1:0] io_out_uop_fp_typ,\t// @[issue-slot.scala:52:14]\n output io_out_uop_xcpt_pf_if,\t// @[issue-slot.scala:52:14]\n output io_out_uop_xcpt_ae_if,\t// @[issue-slot.scala:52:14]\n output io_out_uop_xcpt_ma_if,\t// @[issue-slot.scala:52:14]\n output io_out_uop_bp_debug_if,\t// @[issue-slot.scala:52:14]\n output io_out_uop_bp_xcpt_if,\t// @[issue-slot.scala:52:14]\n output [2:0] io_out_uop_debug_fsrc,\t// @[issue-slot.scala:52:14]\n output [2:0] io_out_uop_debug_tsrc,\t// @[issue-slot.scala:52:14]\n input [15:0] io_brupdate_b1_resolve_mask,\t// @[issue-slot.scala:52:14]\n input [15:0] io_brupdate_b1_mispredict_mask,\t// @[issue-slot.scala:52:14]\n input [31:0] io_brupdate_b2_uop_inst,\t// @[issue-slot.scala:52:14]\n input [31:0] io_brupdate_b2_uop_debug_inst,\t// @[issue-slot.scala:52:14]\n input io_brupdate_b2_uop_is_rvc,\t// @[issue-slot.scala:52:14]\n input [39:0] io_brupdate_b2_uop_debug_pc,\t// @[issue-slot.scala:52:14]\n input io_brupdate_b2_uop_iq_type_0,\t// @[issue-slot.scala:52:14]\n input io_brupdate_b2_uop_iq_type_1,\t// @[issue-slot.scala:52:14]\n input io_brupdate_b2_uop_iq_type_2,\t// @[issue-slot.scala:52:14]\n input io_brupdate_b2_uop_iq_type_3,\t// @[issue-slot.scala:52:14]\n input io_brupdate_b2_uop_fu_code_0,\t// @[issue-slot.scala:52:14]\n input io_brupdate_b2_uop_fu_code_1,\t// @[issue-slot.scala:52:14]\n input io_brupdate_b2_uop_fu_code_2,\t// @[issue-slot.scala:52:14]\n input io_brupdate_b2_uop_fu_code_3,\t// @[issue-slot.scala:52:14]\n input io_brupdate_b2_uop_fu_code_4,\t// @[issue-slot.scala:52:14]\n input io_brupdate_b2_uop_fu_code_5,\t// @[issue-slot.scala:52:14]\n input io_brupdate_b2_uop_fu_code_6,\t// @[issue-slot.scala:52:14]\n input io_brupdate_b2_uop_fu_code_7,\t// @[issue-slot.scala:52:14]\n input io_brupdate_b2_uop_fu_code_8,\t// @[issue-slot.scala:52:14]\n input io_brupdate_b2_uop_fu_code_9,\t// @[issue-slot.scala:52:14]\n input io_brupdate_b2_uop_iw_issued,\t// @[issue-slot.scala:52:14]\n input io_brupdate_b2_uop_iw_issued_partial_agen,\t// @[issue-slot.scala:52:14]\n input io_brupdate_b2_uop_iw_issued_partial_dgen,\t// @[issue-slot.scala:52:14]\n input [2:0] io_brupdate_b2_uop_iw_p1_speculative_child,\t// @[issue-slot.scala:52:14]\n input [2:0] io_brupdate_b2_uop_iw_p2_speculative_child,\t// @[issue-slot.scala:52:14]\n input io_brupdate_b2_uop_iw_p1_bypass_hint,\t// @[issue-slot.scala:52:14]\n input io_brupdate_b2_uop_iw_p2_bypass_hint,\t// @[issue-slot.scala:52:14]\n input io_brupdate_b2_uop_iw_p3_bypass_hint,\t// @[issue-slot.scala:52:14]\n input [2:0] io_brupdate_b2_uop_dis_col_sel,\t// @[issue-slot.scala:52:14]\n input [15:0] io_brupdate_b2_uop_br_mask,\t// @[issue-slot.scala:52:14]\n input [3:0] io_brupdate_b2_uop_br_tag,\t// @[issue-slot.scala:52:14]\n input [3:0] io_brupdate_b2_uop_br_type,\t// @[issue-slot.scala:52:14]\n input io_brupdate_b2_uop_is_sfb,\t// @[issue-slot.scala:52:14]\n input io_brupdate_b2_uop_is_fence,\t// @[issue-slot.scala:52:14]\n input io_brupdate_b2_uop_is_fencei,\t// @[issue-slot.scala:52:14]\n input io_brupdate_b2_uop_is_sfence,\t// @[issue-slot.scala:52:14]\n input io_brupdate_b2_uop_is_amo,\t// @[issue-slot.scala:52:14]\n input io_brupdate_b2_uop_is_eret,\t// @[issue-slot.scala:52:14]\n input io_brupdate_b2_uop_is_sys_pc2epc,\t// @[issue-slot.scala:52:14]\n input io_brupdate_b2_uop_is_rocc,\t// @[issue-slot.scala:52:14]\n input io_brupdate_b2_uop_is_mov,\t// @[issue-slot.scala:52:14]\n input [4:0] io_brupdate_b2_uop_ftq_idx,\t// @[issue-slot.scala:52:14]\n input io_brupdate_b2_uop_edge_inst,\t// @[issue-slot.scala:52:14]\n input [5:0] io_brupdate_b2_uop_pc_lob,\t// @[issue-slot.scala:52:14]\n input io_brupdate_b2_uop_taken,\t// @[issue-slot.scala:52:14]\n input io_brupdate_b2_uop_imm_rename,\t// @[issue-slot.scala:52:14]\n input [2:0] io_brupdate_b2_uop_imm_sel,\t// @[issue-slot.scala:52:14]\n input [4:0] io_brupdate_b2_uop_pimm,\t// @[issue-slot.scala:52:14]\n input [19:0] io_brupdate_b2_uop_imm_packed,\t// @[issue-slot.scala:52:14]\n input [1:0] io_brupdate_b2_uop_op1_sel,\t// @[issue-slot.scala:52:14]\n input [2:0] io_brupdate_b2_uop_op2_sel,\t// @[issue-slot.scala:52:14]\n input io_brupdate_b2_uop_fp_ctrl_ldst,\t// @[issue-slot.scala:52:14]\n input io_brupdate_b2_uop_fp_ctrl_wen,\t// @[issue-slot.scala:52:14]\n input io_brupdate_b2_uop_fp_ctrl_ren1,\t// @[issue-slot.scala:52:14]\n input io_brupdate_b2_uop_fp_ctrl_ren2,\t// @[issue-slot.scala:52:14]\n input io_brupdate_b2_uop_fp_ctrl_ren3,\t// @[issue-slot.scala:52:14]\n input io_brupdate_b2_uop_fp_ctrl_swap12,\t// @[issue-slot.scala:52:14]\n input io_brupdate_b2_uop_fp_ctrl_swap23,\t// @[issue-slot.scala:52:14]\n input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn,\t// @[issue-slot.scala:52:14]\n input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut,\t// @[issue-slot.scala:52:14]\n input io_brupdate_b2_uop_fp_ctrl_fromint,\t// @[issue-slot.scala:52:14]\n input io_brupdate_b2_uop_fp_ctrl_toint,\t// @[issue-slot.scala:52:14]\n input io_brupdate_b2_uop_fp_ctrl_fastpipe,\t// @[issue-slot.scala:52:14]\n input io_brupdate_b2_uop_fp_ctrl_fma,\t// @[issue-slot.scala:52:14]\n input io_brupdate_b2_uop_fp_ctrl_div,\t// @[issue-slot.scala:52:14]\n input io_brupdate_b2_uop_fp_ctrl_sqrt,\t// @[issue-slot.scala:52:14]\n input io_brupdate_b2_uop_fp_ctrl_wflags,\t// @[issue-slot.scala:52:14]\n input io_brupdate_b2_uop_fp_ctrl_vec,\t// @[issue-slot.scala:52:14]\n input [6:0] io_brupdate_b2_uop_rob_idx,\t// @[issue-slot.scala:52:14]\n input [4:0] io_brupdate_b2_uop_ldq_idx,\t// @[issue-slot.scala:52:14]\n input [4:0] io_brupdate_b2_uop_stq_idx,\t// @[issue-slot.scala:52:14]\n input [1:0] io_brupdate_b2_uop_rxq_idx,\t// @[issue-slot.scala:52:14]\n input [6:0] io_brupdate_b2_uop_pdst,\t// @[issue-slot.scala:52:14]\n input [6:0] io_brupdate_b2_uop_prs1,\t// @[issue-slot.scala:52:14]\n input [6:0] io_brupdate_b2_uop_prs2,\t// @[issue-slot.scala:52:14]\n input [6:0] io_brupdate_b2_uop_prs3,\t// @[issue-slot.scala:52:14]\n input [4:0] io_brupdate_b2_uop_ppred,\t// @[issue-slot.scala:52:14]\n input io_brupdate_b2_uop_prs1_busy,\t// @[issue-slot.scala:52:14]\n input io_brupdate_b2_uop_prs2_busy,\t// @[issue-slot.scala:52:14]\n input io_brupdate_b2_uop_prs3_busy,\t// @[issue-slot.scala:52:14]\n input io_brupdate_b2_uop_ppred_busy,\t// @[issue-slot.scala:52:14]\n input [6:0] io_brupdate_b2_uop_stale_pdst,\t// @[issue-slot.scala:52:14]\n input io_brupdate_b2_uop_exception,\t// @[issue-slot.scala:52:14]\n input [63:0] io_brupdate_b2_uop_exc_cause,\t// @[issue-slot.scala:52:14]\n input [4:0] io_brupdate_b2_uop_mem_cmd,\t// @[issue-slot.scala:52:14]\n input [1:0] io_brupdate_b2_uop_mem_size,\t// @[issue-slot.scala:52:14]\n input io_brupdate_b2_uop_mem_signed,\t// @[issue-slot.scala:52:14]\n input io_brupdate_b2_uop_uses_ldq,\t// @[issue-slot.scala:52:14]\n input io_brupdate_b2_uop_uses_stq,\t// @[issue-slot.scala:52:14]\n input io_brupdate_b2_uop_is_unique,\t// @[issue-slot.scala:52:14]\n input io_brupdate_b2_uop_flush_on_commit,\t// @[issue-slot.scala:52:14]\n input [2:0] io_brupdate_b2_uop_csr_cmd,\t// @[issue-slot.scala:52:14]\n input io_brupdate_b2_uop_ldst_is_rs1,\t// @[issue-slot.scala:52:14]\n input [5:0] io_brupdate_b2_uop_ldst,\t// @[issue-slot.scala:52:14]\n input [5:0] io_brupdate_b2_uop_lrs1,\t// @[issue-slot.scala:52:14]\n input [5:0] io_brupdate_b2_uop_lrs2,\t// @[issue-slot.scala:52:14]\n input [5:0] io_brupdate_b2_uop_lrs3,\t// @[issue-slot.scala:52:14]\n input [1:0] io_brupdate_b2_uop_dst_rtype,\t// @[issue-slot.scala:52:14]\n input [1:0] io_brupdate_b2_uop_lrs1_rtype,\t// @[issue-slot.scala:52:14]\n input [1:0] io_brupdate_b2_uop_lrs2_rtype,\t// @[issue-slot.scala:52:14]\n input io_brupdate_b2_uop_frs3_en,\t// @[issue-slot.scala:52:14]\n input io_brupdate_b2_uop_fcn_dw,\t// @[issue-slot.scala:52:14]\n input [4:0] io_brupdate_b2_uop_fcn_op,\t// @[issue-slot.scala:52:14]\n input io_brupdate_b2_uop_fp_val,\t// @[issue-slot.scala:52:14]\n input [2:0] io_brupdate_b2_uop_fp_rm,\t// @[issue-slot.scala:52:14]\n input [1:0] io_brupdate_b2_uop_fp_typ,\t// @[issue-slot.scala:52:14]\n input io_brupdate_b2_uop_xcpt_pf_if,\t// @[issue-slot.scala:52:14]\n input io_brupdate_b2_uop_xcpt_ae_if,\t// @[issue-slot.scala:52:14]\n input io_brupdate_b2_uop_xcpt_ma_if,\t// @[issue-slot.scala:52:14]\n input io_brupdate_b2_uop_bp_debug_if,\t// @[issue-slot.scala:52:14]\n input io_brupdate_b2_uop_bp_xcpt_if,\t// @[issue-slot.scala:52:14]\n input [2:0] io_brupdate_b2_uop_debug_fsrc,\t// @[issue-slot.scala:52:14]\n input [2:0] io_brupdate_b2_uop_debug_tsrc,\t// @[issue-slot.scala:52:14]\n input io_brupdate_b2_mispredict,\t// @[issue-slot.scala:52:14]\n input io_brupdate_b2_taken,\t// @[issue-slot.scala:52:14]\n input [2:0] io_brupdate_b2_cfi_type,\t// @[issue-slot.scala:52:14]\n input [1:0] io_brupdate_b2_pc_sel,\t// @[issue-slot.scala:52:14]\n input [39:0] io_brupdate_b2_jalr_target,\t// @[issue-slot.scala:52:14]\n input [20:0] io_brupdate_b2_target_offset,\t// @[issue-slot.scala:52:14]\n input io_kill,\t// @[issue-slot.scala:52:14]\n input io_clear,\t// @[issue-slot.scala:52:14]\n input io_squash_grant,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_0_valid,\t// @[issue-slot.scala:52:14]\n input [31:0] io_wakeup_ports_0_bits_uop_inst,\t// @[issue-slot.scala:52:14]\n input [31:0] io_wakeup_ports_0_bits_uop_debug_inst,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_0_bits_uop_is_rvc,\t// @[issue-slot.scala:52:14]\n input [39:0] io_wakeup_ports_0_bits_uop_debug_pc,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_0_bits_uop_iq_type_0,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_0_bits_uop_iq_type_1,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_0_bits_uop_iq_type_2,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_0_bits_uop_iq_type_3,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_0_bits_uop_fu_code_0,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_0_bits_uop_fu_code_1,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_0_bits_uop_fu_code_2,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_0_bits_uop_fu_code_3,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_0_bits_uop_fu_code_4,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_0_bits_uop_fu_code_5,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_0_bits_uop_fu_code_6,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_0_bits_uop_fu_code_7,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_0_bits_uop_fu_code_8,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_0_bits_uop_fu_code_9,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_0_bits_uop_iw_issued,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_0_bits_uop_iw_issued_partial_agen,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen,\t// @[issue-slot.scala:52:14]\n input [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child,\t// @[issue-slot.scala:52:14]\n input [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint,\t// @[issue-slot.scala:52:14]\n input [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel,\t// @[issue-slot.scala:52:14]\n input [15:0] io_wakeup_ports_0_bits_uop_br_mask,\t// @[issue-slot.scala:52:14]\n input [3:0] io_wakeup_ports_0_bits_uop_br_tag,\t// @[issue-slot.scala:52:14]\n input [3:0] io_wakeup_ports_0_bits_uop_br_type,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_0_bits_uop_is_sfb,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_0_bits_uop_is_fence,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_0_bits_uop_is_fencei,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_0_bits_uop_is_sfence,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_0_bits_uop_is_amo,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_0_bits_uop_is_eret,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_0_bits_uop_is_sys_pc2epc,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_0_bits_uop_is_rocc,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_0_bits_uop_is_mov,\t// @[issue-slot.scala:52:14]\n input [4:0] io_wakeup_ports_0_bits_uop_ftq_idx,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_0_bits_uop_edge_inst,\t// @[issue-slot.scala:52:14]\n input [5:0] io_wakeup_ports_0_bits_uop_pc_lob,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_0_bits_uop_taken,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_0_bits_uop_imm_rename,\t// @[issue-slot.scala:52:14]\n input [2:0] io_wakeup_ports_0_bits_uop_imm_sel,\t// @[issue-slot.scala:52:14]\n input [4:0] io_wakeup_ports_0_bits_uop_pimm,\t// @[issue-slot.scala:52:14]\n input [19:0] io_wakeup_ports_0_bits_uop_imm_packed,\t// @[issue-slot.scala:52:14]\n input [1:0] io_wakeup_ports_0_bits_uop_op1_sel,\t// @[issue-slot.scala:52:14]\n input [2:0] io_wakeup_ports_0_bits_uop_op2_sel,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_0_bits_uop_fp_ctrl_ldst,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_0_bits_uop_fp_ctrl_wen,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_0_bits_uop_fp_ctrl_ren1,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_0_bits_uop_fp_ctrl_ren2,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_0_bits_uop_fp_ctrl_ren3,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_0_bits_uop_fp_ctrl_swap12,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_0_bits_uop_fp_ctrl_swap23,\t// @[issue-slot.scala:52:14]\n input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn,\t// @[issue-slot.scala:52:14]\n input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_0_bits_uop_fp_ctrl_fromint,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_0_bits_uop_fp_ctrl_toint,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_0_bits_uop_fp_ctrl_fma,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_0_bits_uop_fp_ctrl_div,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_0_bits_uop_fp_ctrl_wflags,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_0_bits_uop_fp_ctrl_vec,\t// @[issue-slot.scala:52:14]\n input [6:0] io_wakeup_ports_0_bits_uop_rob_idx,\t// @[issue-slot.scala:52:14]\n input [4:0] io_wakeup_ports_0_bits_uop_ldq_idx,\t// @[issue-slot.scala:52:14]\n input [4:0] io_wakeup_ports_0_bits_uop_stq_idx,\t// @[issue-slot.scala:52:14]\n input [1:0] io_wakeup_ports_0_bits_uop_rxq_idx,\t// @[issue-slot.scala:52:14]\n input [6:0] io_wakeup_ports_0_bits_uop_pdst,\t// @[issue-slot.scala:52:14]\n input [6:0] io_wakeup_ports_0_bits_uop_prs1,\t// @[issue-slot.scala:52:14]\n input [6:0] io_wakeup_ports_0_bits_uop_prs2,\t// @[issue-slot.scala:52:14]\n input [6:0] io_wakeup_ports_0_bits_uop_prs3,\t// @[issue-slot.scala:52:14]\n input [4:0] io_wakeup_ports_0_bits_uop_ppred,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_0_bits_uop_prs1_busy,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_0_bits_uop_prs2_busy,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_0_bits_uop_prs3_busy,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_0_bits_uop_ppred_busy,\t// @[issue-slot.scala:52:14]\n input [6:0] io_wakeup_ports_0_bits_uop_stale_pdst,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_0_bits_uop_exception,\t// @[issue-slot.scala:52:14]\n input [63:0] io_wakeup_ports_0_bits_uop_exc_cause,\t// @[issue-slot.scala:52:14]\n input [4:0] io_wakeup_ports_0_bits_uop_mem_cmd,\t// @[issue-slot.scala:52:14]\n input [1:0] io_wakeup_ports_0_bits_uop_mem_size,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_0_bits_uop_mem_signed,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_0_bits_uop_uses_ldq,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_0_bits_uop_uses_stq,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_0_bits_uop_is_unique,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_0_bits_uop_flush_on_commit,\t// @[issue-slot.scala:52:14]\n input [2:0] io_wakeup_ports_0_bits_uop_csr_cmd,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_0_bits_uop_ldst_is_rs1,\t// @[issue-slot.scala:52:14]\n input [5:0] io_wakeup_ports_0_bits_uop_ldst,\t// @[issue-slot.scala:52:14]\n input [5:0] io_wakeup_ports_0_bits_uop_lrs1,\t// @[issue-slot.scala:52:14]\n input [5:0] io_wakeup_ports_0_bits_uop_lrs2,\t// @[issue-slot.scala:52:14]\n input [5:0] io_wakeup_ports_0_bits_uop_lrs3,\t// @[issue-slot.scala:52:14]\n input [1:0] io_wakeup_ports_0_bits_uop_dst_rtype,\t// @[issue-slot.scala:52:14]\n input [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype,\t// @[issue-slot.scala:52:14]\n input [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_0_bits_uop_frs3_en,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_0_bits_uop_fcn_dw,\t// @[issue-slot.scala:52:14]\n input [4:0] io_wakeup_ports_0_bits_uop_fcn_op,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_0_bits_uop_fp_val,\t// @[issue-slot.scala:52:14]\n input [2:0] io_wakeup_ports_0_bits_uop_fp_rm,\t// @[issue-slot.scala:52:14]\n input [1:0] io_wakeup_ports_0_bits_uop_fp_typ,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_0_bits_uop_xcpt_pf_if,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_0_bits_uop_xcpt_ae_if,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_0_bits_uop_xcpt_ma_if,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_0_bits_uop_bp_debug_if,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_0_bits_uop_bp_xcpt_if,\t// @[issue-slot.scala:52:14]\n input [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc,\t// @[issue-slot.scala:52:14]\n input [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_0_bits_bypassable,\t// @[issue-slot.scala:52:14]\n input [2:0] io_wakeup_ports_0_bits_speculative_mask,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_0_bits_rebusy,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_1_valid,\t// @[issue-slot.scala:52:14]\n input [31:0] io_wakeup_ports_1_bits_uop_inst,\t// @[issue-slot.scala:52:14]\n input [31:0] io_wakeup_ports_1_bits_uop_debug_inst,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_1_bits_uop_is_rvc,\t// @[issue-slot.scala:52:14]\n input [39:0] io_wakeup_ports_1_bits_uop_debug_pc,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_1_bits_uop_iq_type_0,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_1_bits_uop_iq_type_1,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_1_bits_uop_iq_type_2,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_1_bits_uop_iq_type_3,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_1_bits_uop_fu_code_0,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_1_bits_uop_fu_code_1,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_1_bits_uop_fu_code_2,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_1_bits_uop_fu_code_3,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_1_bits_uop_fu_code_4,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_1_bits_uop_fu_code_5,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_1_bits_uop_fu_code_6,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_1_bits_uop_fu_code_7,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_1_bits_uop_fu_code_8,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_1_bits_uop_fu_code_9,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_1_bits_uop_iw_issued,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_1_bits_uop_iw_issued_partial_agen,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen,\t// @[issue-slot.scala:52:14]\n input [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child,\t// @[issue-slot.scala:52:14]\n input [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint,\t// @[issue-slot.scala:52:14]\n input [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel,\t// @[issue-slot.scala:52:14]\n input [15:0] io_wakeup_ports_1_bits_uop_br_mask,\t// @[issue-slot.scala:52:14]\n input [3:0] io_wakeup_ports_1_bits_uop_br_tag,\t// @[issue-slot.scala:52:14]\n input [3:0] io_wakeup_ports_1_bits_uop_br_type,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_1_bits_uop_is_sfb,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_1_bits_uop_is_fence,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_1_bits_uop_is_fencei,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_1_bits_uop_is_sfence,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_1_bits_uop_is_amo,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_1_bits_uop_is_eret,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_1_bits_uop_is_sys_pc2epc,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_1_bits_uop_is_rocc,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_1_bits_uop_is_mov,\t// @[issue-slot.scala:52:14]\n input [4:0] io_wakeup_ports_1_bits_uop_ftq_idx,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_1_bits_uop_edge_inst,\t// @[issue-slot.scala:52:14]\n input [5:0] io_wakeup_ports_1_bits_uop_pc_lob,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_1_bits_uop_taken,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_1_bits_uop_imm_rename,\t// @[issue-slot.scala:52:14]\n input [2:0] io_wakeup_ports_1_bits_uop_imm_sel,\t// @[issue-slot.scala:52:14]\n input [4:0] io_wakeup_ports_1_bits_uop_pimm,\t// @[issue-slot.scala:52:14]\n input [19:0] io_wakeup_ports_1_bits_uop_imm_packed,\t// @[issue-slot.scala:52:14]\n input [1:0] io_wakeup_ports_1_bits_uop_op1_sel,\t// @[issue-slot.scala:52:14]\n input [2:0] io_wakeup_ports_1_bits_uop_op2_sel,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_1_bits_uop_fp_ctrl_ldst,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_1_bits_uop_fp_ctrl_wen,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_1_bits_uop_fp_ctrl_ren1,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_1_bits_uop_fp_ctrl_ren2,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_1_bits_uop_fp_ctrl_ren3,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_1_bits_uop_fp_ctrl_swap12,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_1_bits_uop_fp_ctrl_swap23,\t// @[issue-slot.scala:52:14]\n input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn,\t// @[issue-slot.scala:52:14]\n input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_1_bits_uop_fp_ctrl_fromint,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_1_bits_uop_fp_ctrl_toint,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_1_bits_uop_fp_ctrl_fma,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_1_bits_uop_fp_ctrl_div,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_1_bits_uop_fp_ctrl_wflags,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_1_bits_uop_fp_ctrl_vec,\t// @[issue-slot.scala:52:14]\n input [6:0] io_wakeup_ports_1_bits_uop_rob_idx,\t// @[issue-slot.scala:52:14]\n input [4:0] io_wakeup_ports_1_bits_uop_ldq_idx,\t// @[issue-slot.scala:52:14]\n input [4:0] io_wakeup_ports_1_bits_uop_stq_idx,\t// @[issue-slot.scala:52:14]\n input [1:0] io_wakeup_ports_1_bits_uop_rxq_idx,\t// @[issue-slot.scala:52:14]\n input [6:0] io_wakeup_ports_1_bits_uop_pdst,\t// @[issue-slot.scala:52:14]\n input [6:0] io_wakeup_ports_1_bits_uop_prs1,\t// @[issue-slot.scala:52:14]\n input [6:0] io_wakeup_ports_1_bits_uop_prs2,\t// @[issue-slot.scala:52:14]\n input [6:0] io_wakeup_ports_1_bits_uop_prs3,\t// @[issue-slot.scala:52:14]\n input [4:0] io_wakeup_ports_1_bits_uop_ppred,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_1_bits_uop_prs1_busy,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_1_bits_uop_prs2_busy,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_1_bits_uop_prs3_busy,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_1_bits_uop_ppred_busy,\t// @[issue-slot.scala:52:14]\n input [6:0] io_wakeup_ports_1_bits_uop_stale_pdst,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_1_bits_uop_exception,\t// @[issue-slot.scala:52:14]\n input [63:0] io_wakeup_ports_1_bits_uop_exc_cause,\t// @[issue-slot.scala:52:14]\n input [4:0] io_wakeup_ports_1_bits_uop_mem_cmd,\t// @[issue-slot.scala:52:14]\n input [1:0] io_wakeup_ports_1_bits_uop_mem_size,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_1_bits_uop_mem_signed,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_1_bits_uop_uses_ldq,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_1_bits_uop_uses_stq,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_1_bits_uop_is_unique,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_1_bits_uop_flush_on_commit,\t// @[issue-slot.scala:52:14]\n input [2:0] io_wakeup_ports_1_bits_uop_csr_cmd,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_1_bits_uop_ldst_is_rs1,\t// @[issue-slot.scala:52:14]\n input [5:0] io_wakeup_ports_1_bits_uop_ldst,\t// @[issue-slot.scala:52:14]\n input [5:0] io_wakeup_ports_1_bits_uop_lrs1,\t// @[issue-slot.scala:52:14]\n input [5:0] io_wakeup_ports_1_bits_uop_lrs2,\t// @[issue-slot.scala:52:14]\n input [5:0] io_wakeup_ports_1_bits_uop_lrs3,\t// @[issue-slot.scala:52:14]\n input [1:0] io_wakeup_ports_1_bits_uop_dst_rtype,\t// @[issue-slot.scala:52:14]\n input [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype,\t// @[issue-slot.scala:52:14]\n input [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_1_bits_uop_frs3_en,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_1_bits_uop_fcn_dw,\t// @[issue-slot.scala:52:14]\n input [4:0] io_wakeup_ports_1_bits_uop_fcn_op,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_1_bits_uop_fp_val,\t// @[issue-slot.scala:52:14]\n input [2:0] io_wakeup_ports_1_bits_uop_fp_rm,\t// @[issue-slot.scala:52:14]\n input [1:0] io_wakeup_ports_1_bits_uop_fp_typ,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_1_bits_uop_xcpt_pf_if,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_1_bits_uop_xcpt_ae_if,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_1_bits_uop_xcpt_ma_if,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_1_bits_uop_bp_debug_if,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_1_bits_uop_bp_xcpt_if,\t// @[issue-slot.scala:52:14]\n input [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc,\t// @[issue-slot.scala:52:14]\n input [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_2_valid,\t// @[issue-slot.scala:52:14]\n input [31:0] io_wakeup_ports_2_bits_uop_inst,\t// @[issue-slot.scala:52:14]\n input [31:0] io_wakeup_ports_2_bits_uop_debug_inst,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_2_bits_uop_is_rvc,\t// @[issue-slot.scala:52:14]\n input [39:0] io_wakeup_ports_2_bits_uop_debug_pc,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_2_bits_uop_iq_type_0,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_2_bits_uop_iq_type_1,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_2_bits_uop_iq_type_2,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_2_bits_uop_iq_type_3,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_2_bits_uop_fu_code_0,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_2_bits_uop_fu_code_1,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_2_bits_uop_fu_code_2,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_2_bits_uop_fu_code_3,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_2_bits_uop_fu_code_4,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_2_bits_uop_fu_code_5,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_2_bits_uop_fu_code_6,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_2_bits_uop_fu_code_7,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_2_bits_uop_fu_code_8,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_2_bits_uop_fu_code_9,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_2_bits_uop_iw_issued,\t// @[issue-slot.scala:52:14]\n input [2:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child,\t// @[issue-slot.scala:52:14]\n input [2:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint,\t// @[issue-slot.scala:52:14]\n input [2:0] io_wakeup_ports_2_bits_uop_dis_col_sel,\t// @[issue-slot.scala:52:14]\n input [15:0] io_wakeup_ports_2_bits_uop_br_mask,\t// @[issue-slot.scala:52:14]\n input [3:0] io_wakeup_ports_2_bits_uop_br_tag,\t// @[issue-slot.scala:52:14]\n input [3:0] io_wakeup_ports_2_bits_uop_br_type,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_2_bits_uop_is_sfb,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_2_bits_uop_is_fence,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_2_bits_uop_is_fencei,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_2_bits_uop_is_sfence,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_2_bits_uop_is_amo,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_2_bits_uop_is_eret,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_2_bits_uop_is_sys_pc2epc,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_2_bits_uop_is_rocc,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_2_bits_uop_is_mov,\t// @[issue-slot.scala:52:14]\n input [4:0] io_wakeup_ports_2_bits_uop_ftq_idx,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_2_bits_uop_edge_inst,\t// @[issue-slot.scala:52:14]\n input [5:0] io_wakeup_ports_2_bits_uop_pc_lob,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_2_bits_uop_taken,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_2_bits_uop_imm_rename,\t// @[issue-slot.scala:52:14]\n input [2:0] io_wakeup_ports_2_bits_uop_imm_sel,\t// @[issue-slot.scala:52:14]\n input [4:0] io_wakeup_ports_2_bits_uop_pimm,\t// @[issue-slot.scala:52:14]\n input [19:0] io_wakeup_ports_2_bits_uop_imm_packed,\t// @[issue-slot.scala:52:14]\n input [1:0] io_wakeup_ports_2_bits_uop_op1_sel,\t// @[issue-slot.scala:52:14]\n input [2:0] io_wakeup_ports_2_bits_uop_op2_sel,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_2_bits_uop_fp_ctrl_ldst,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_2_bits_uop_fp_ctrl_wen,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_2_bits_uop_fp_ctrl_ren1,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_2_bits_uop_fp_ctrl_ren2,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_2_bits_uop_fp_ctrl_ren3,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_2_bits_uop_fp_ctrl_swap12,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_2_bits_uop_fp_ctrl_swap23,\t// @[issue-slot.scala:52:14]\n input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn,\t// @[issue-slot.scala:52:14]\n input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_2_bits_uop_fp_ctrl_fromint,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_2_bits_uop_fp_ctrl_toint,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_2_bits_uop_fp_ctrl_fma,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_2_bits_uop_fp_ctrl_div,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_2_bits_uop_fp_ctrl_wflags,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_2_bits_uop_fp_ctrl_vec,\t// @[issue-slot.scala:52:14]\n input [6:0] io_wakeup_ports_2_bits_uop_rob_idx,\t// @[issue-slot.scala:52:14]\n input [4:0] io_wakeup_ports_2_bits_uop_ldq_idx,\t// @[issue-slot.scala:52:14]\n input [4:0] io_wakeup_ports_2_bits_uop_stq_idx,\t// @[issue-slot.scala:52:14]\n input [1:0] io_wakeup_ports_2_bits_uop_rxq_idx,\t// @[issue-slot.scala:52:14]\n input [6:0] io_wakeup_ports_2_bits_uop_pdst,\t// @[issue-slot.scala:52:14]\n input [6:0] io_wakeup_ports_2_bits_uop_prs1,\t// @[issue-slot.scala:52:14]\n input [6:0] io_wakeup_ports_2_bits_uop_prs2,\t// @[issue-slot.scala:52:14]\n input [6:0] io_wakeup_ports_2_bits_uop_prs3,\t// @[issue-slot.scala:52:14]\n input [4:0] io_wakeup_ports_2_bits_uop_ppred,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_2_bits_uop_prs1_busy,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_2_bits_uop_prs2_busy,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_2_bits_uop_prs3_busy,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_2_bits_uop_ppred_busy,\t// @[issue-slot.scala:52:14]\n input [6:0] io_wakeup_ports_2_bits_uop_stale_pdst,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_2_bits_uop_exception,\t// @[issue-slot.scala:52:14]\n input [63:0] io_wakeup_ports_2_bits_uop_exc_cause,\t// @[issue-slot.scala:52:14]\n input [4:0] io_wakeup_ports_2_bits_uop_mem_cmd,\t// @[issue-slot.scala:52:14]\n input [1:0] io_wakeup_ports_2_bits_uop_mem_size,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_2_bits_uop_mem_signed,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_2_bits_uop_uses_ldq,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_2_bits_uop_uses_stq,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_2_bits_uop_is_unique,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_2_bits_uop_flush_on_commit,\t// @[issue-slot.scala:52:14]\n input [2:0] io_wakeup_ports_2_bits_uop_csr_cmd,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_2_bits_uop_ldst_is_rs1,\t// @[issue-slot.scala:52:14]\n input [5:0] io_wakeup_ports_2_bits_uop_ldst,\t// @[issue-slot.scala:52:14]\n input [5:0] io_wakeup_ports_2_bits_uop_lrs1,\t// @[issue-slot.scala:52:14]\n input [5:0] io_wakeup_ports_2_bits_uop_lrs2,\t// @[issue-slot.scala:52:14]\n input [5:0] io_wakeup_ports_2_bits_uop_lrs3,\t// @[issue-slot.scala:52:14]\n input [1:0] io_wakeup_ports_2_bits_uop_dst_rtype,\t// @[issue-slot.scala:52:14]\n input [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype,\t// @[issue-slot.scala:52:14]\n input [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_2_bits_uop_frs3_en,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_2_bits_uop_fcn_dw,\t// @[issue-slot.scala:52:14]\n input [4:0] io_wakeup_ports_2_bits_uop_fcn_op,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_2_bits_uop_fp_val,\t// @[issue-slot.scala:52:14]\n input [2:0] io_wakeup_ports_2_bits_uop_fp_rm,\t// @[issue-slot.scala:52:14]\n input [1:0] io_wakeup_ports_2_bits_uop_fp_typ,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_2_bits_uop_xcpt_pf_if,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_2_bits_uop_xcpt_ae_if,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_2_bits_uop_xcpt_ma_if,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_2_bits_uop_bp_debug_if,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_2_bits_uop_bp_xcpt_if,\t// @[issue-slot.scala:52:14]\n input [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc,\t// @[issue-slot.scala:52:14]\n input [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_3_valid,\t// @[issue-slot.scala:52:14]\n input [31:0] io_wakeup_ports_3_bits_uop_inst,\t// @[issue-slot.scala:52:14]\n input [31:0] io_wakeup_ports_3_bits_uop_debug_inst,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_3_bits_uop_is_rvc,\t// @[issue-slot.scala:52:14]\n input [39:0] io_wakeup_ports_3_bits_uop_debug_pc,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_3_bits_uop_iq_type_0,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_3_bits_uop_iq_type_1,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_3_bits_uop_iq_type_2,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_3_bits_uop_iq_type_3,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_3_bits_uop_fu_code_0,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_3_bits_uop_fu_code_1,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_3_bits_uop_fu_code_2,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_3_bits_uop_fu_code_3,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_3_bits_uop_fu_code_4,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_3_bits_uop_fu_code_5,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_3_bits_uop_fu_code_6,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_3_bits_uop_fu_code_7,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_3_bits_uop_fu_code_8,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_3_bits_uop_fu_code_9,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_3_bits_uop_iw_issued,\t// @[issue-slot.scala:52:14]\n input [2:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child,\t// @[issue-slot.scala:52:14]\n input [2:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint,\t// @[issue-slot.scala:52:14]\n input [2:0] io_wakeup_ports_3_bits_uop_dis_col_sel,\t// @[issue-slot.scala:52:14]\n input [15:0] io_wakeup_ports_3_bits_uop_br_mask,\t// @[issue-slot.scala:52:14]\n input [3:0] io_wakeup_ports_3_bits_uop_br_tag,\t// @[issue-slot.scala:52:14]\n input [3:0] io_wakeup_ports_3_bits_uop_br_type,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_3_bits_uop_is_sfb,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_3_bits_uop_is_fence,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_3_bits_uop_is_fencei,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_3_bits_uop_is_sfence,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_3_bits_uop_is_amo,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_3_bits_uop_is_eret,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_3_bits_uop_is_sys_pc2epc,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_3_bits_uop_is_rocc,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_3_bits_uop_is_mov,\t// @[issue-slot.scala:52:14]\n input [4:0] io_wakeup_ports_3_bits_uop_ftq_idx,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_3_bits_uop_edge_inst,\t// @[issue-slot.scala:52:14]\n input [5:0] io_wakeup_ports_3_bits_uop_pc_lob,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_3_bits_uop_taken,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_3_bits_uop_imm_rename,\t// @[issue-slot.scala:52:14]\n input [2:0] io_wakeup_ports_3_bits_uop_imm_sel,\t// @[issue-slot.scala:52:14]\n input [4:0] io_wakeup_ports_3_bits_uop_pimm,\t// @[issue-slot.scala:52:14]\n input [19:0] io_wakeup_ports_3_bits_uop_imm_packed,\t// @[issue-slot.scala:52:14]\n input [1:0] io_wakeup_ports_3_bits_uop_op1_sel,\t// @[issue-slot.scala:52:14]\n input [2:0] io_wakeup_ports_3_bits_uop_op2_sel,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_3_bits_uop_fp_ctrl_ldst,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_3_bits_uop_fp_ctrl_wen,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_3_bits_uop_fp_ctrl_ren1,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_3_bits_uop_fp_ctrl_ren2,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_3_bits_uop_fp_ctrl_ren3,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_3_bits_uop_fp_ctrl_swap12,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_3_bits_uop_fp_ctrl_swap23,\t// @[issue-slot.scala:52:14]\n input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn,\t// @[issue-slot.scala:52:14]\n input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_3_bits_uop_fp_ctrl_fromint,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_3_bits_uop_fp_ctrl_toint,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_3_bits_uop_fp_ctrl_fma,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_3_bits_uop_fp_ctrl_div,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_3_bits_uop_fp_ctrl_wflags,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_3_bits_uop_fp_ctrl_vec,\t// @[issue-slot.scala:52:14]\n input [6:0] io_wakeup_ports_3_bits_uop_rob_idx,\t// @[issue-slot.scala:52:14]\n input [4:0] io_wakeup_ports_3_bits_uop_ldq_idx,\t// @[issue-slot.scala:52:14]\n input [4:0] io_wakeup_ports_3_bits_uop_stq_idx,\t// @[issue-slot.scala:52:14]\n input [1:0] io_wakeup_ports_3_bits_uop_rxq_idx,\t// @[issue-slot.scala:52:14]\n input [6:0] io_wakeup_ports_3_bits_uop_pdst,\t// @[issue-slot.scala:52:14]\n input [6:0] io_wakeup_ports_3_bits_uop_prs1,\t// @[issue-slot.scala:52:14]\n input [6:0] io_wakeup_ports_3_bits_uop_prs2,\t// @[issue-slot.scala:52:14]\n input [6:0] io_wakeup_ports_3_bits_uop_prs3,\t// @[issue-slot.scala:52:14]\n input [4:0] io_wakeup_ports_3_bits_uop_ppred,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_3_bits_uop_prs1_busy,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_3_bits_uop_prs2_busy,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_3_bits_uop_prs3_busy,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_3_bits_uop_ppred_busy,\t// @[issue-slot.scala:52:14]\n input [6:0] io_wakeup_ports_3_bits_uop_stale_pdst,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_3_bits_uop_exception,\t// @[issue-slot.scala:52:14]\n input [63:0] io_wakeup_ports_3_bits_uop_exc_cause,\t// @[issue-slot.scala:52:14]\n input [4:0] io_wakeup_ports_3_bits_uop_mem_cmd,\t// @[issue-slot.scala:52:14]\n input [1:0] io_wakeup_ports_3_bits_uop_mem_size,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_3_bits_uop_mem_signed,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_3_bits_uop_uses_ldq,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_3_bits_uop_uses_stq,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_3_bits_uop_is_unique,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_3_bits_uop_flush_on_commit,\t// @[issue-slot.scala:52:14]\n input [2:0] io_wakeup_ports_3_bits_uop_csr_cmd,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_3_bits_uop_ldst_is_rs1,\t// @[issue-slot.scala:52:14]\n input [5:0] io_wakeup_ports_3_bits_uop_ldst,\t// @[issue-slot.scala:52:14]\n input [5:0] io_wakeup_ports_3_bits_uop_lrs1,\t// @[issue-slot.scala:52:14]\n input [5:0] io_wakeup_ports_3_bits_uop_lrs2,\t// @[issue-slot.scala:52:14]\n input [5:0] io_wakeup_ports_3_bits_uop_lrs3,\t// @[issue-slot.scala:52:14]\n input [1:0] io_wakeup_ports_3_bits_uop_dst_rtype,\t// @[issue-slot.scala:52:14]\n input [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype,\t// @[issue-slot.scala:52:14]\n input [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_3_bits_uop_frs3_en,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_3_bits_uop_fcn_dw,\t// @[issue-slot.scala:52:14]\n input [4:0] io_wakeup_ports_3_bits_uop_fcn_op,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_3_bits_uop_fp_val,\t// @[issue-slot.scala:52:14]\n input [2:0] io_wakeup_ports_3_bits_uop_fp_rm,\t// @[issue-slot.scala:52:14]\n input [1:0] io_wakeup_ports_3_bits_uop_fp_typ,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_3_bits_uop_xcpt_pf_if,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_3_bits_uop_xcpt_ae_if,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_3_bits_uop_xcpt_ma_if,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_3_bits_uop_bp_debug_if,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_3_bits_uop_bp_xcpt_if,\t// @[issue-slot.scala:52:14]\n input [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc,\t// @[issue-slot.scala:52:14]\n input [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_4_valid,\t// @[issue-slot.scala:52:14]\n input [31:0] io_wakeup_ports_4_bits_uop_inst,\t// @[issue-slot.scala:52:14]\n input [31:0] io_wakeup_ports_4_bits_uop_debug_inst,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_4_bits_uop_is_rvc,\t// @[issue-slot.scala:52:14]\n input [39:0] io_wakeup_ports_4_bits_uop_debug_pc,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_4_bits_uop_iq_type_0,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_4_bits_uop_iq_type_1,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_4_bits_uop_iq_type_2,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_4_bits_uop_iq_type_3,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_4_bits_uop_fu_code_0,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_4_bits_uop_fu_code_1,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_4_bits_uop_fu_code_2,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_4_bits_uop_fu_code_3,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_4_bits_uop_fu_code_4,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_4_bits_uop_fu_code_5,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_4_bits_uop_fu_code_6,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_4_bits_uop_fu_code_7,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_4_bits_uop_fu_code_8,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_4_bits_uop_fu_code_9,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_4_bits_uop_iw_issued,\t// @[issue-slot.scala:52:14]\n input [2:0] io_wakeup_ports_4_bits_uop_iw_p1_speculative_child,\t// @[issue-slot.scala:52:14]\n input [2:0] io_wakeup_ports_4_bits_uop_iw_p2_speculative_child,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint,\t// @[issue-slot.scala:52:14]\n input [2:0] io_wakeup_ports_4_bits_uop_dis_col_sel,\t// @[issue-slot.scala:52:14]\n input [15:0] io_wakeup_ports_4_bits_uop_br_mask,\t// @[issue-slot.scala:52:14]\n input [3:0] io_wakeup_ports_4_bits_uop_br_tag,\t// @[issue-slot.scala:52:14]\n input [3:0] io_wakeup_ports_4_bits_uop_br_type,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_4_bits_uop_is_sfb,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_4_bits_uop_is_fence,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_4_bits_uop_is_fencei,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_4_bits_uop_is_sfence,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_4_bits_uop_is_amo,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_4_bits_uop_is_eret,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_4_bits_uop_is_sys_pc2epc,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_4_bits_uop_is_rocc,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_4_bits_uop_is_mov,\t// @[issue-slot.scala:52:14]\n input [4:0] io_wakeup_ports_4_bits_uop_ftq_idx,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_4_bits_uop_edge_inst,\t// @[issue-slot.scala:52:14]\n input [5:0] io_wakeup_ports_4_bits_uop_pc_lob,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_4_bits_uop_taken,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_4_bits_uop_imm_rename,\t// @[issue-slot.scala:52:14]\n input [2:0] io_wakeup_ports_4_bits_uop_imm_sel,\t// @[issue-slot.scala:52:14]\n input [4:0] io_wakeup_ports_4_bits_uop_pimm,\t// @[issue-slot.scala:52:14]\n input [19:0] io_wakeup_ports_4_bits_uop_imm_packed,\t// @[issue-slot.scala:52:14]\n input [1:0] io_wakeup_ports_4_bits_uop_op1_sel,\t// @[issue-slot.scala:52:14]\n input [2:0] io_wakeup_ports_4_bits_uop_op2_sel,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_4_bits_uop_fp_ctrl_ldst,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_4_bits_uop_fp_ctrl_wen,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_4_bits_uop_fp_ctrl_ren1,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_4_bits_uop_fp_ctrl_ren2,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_4_bits_uop_fp_ctrl_ren3,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_4_bits_uop_fp_ctrl_swap12,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_4_bits_uop_fp_ctrl_swap23,\t// @[issue-slot.scala:52:14]\n input [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn,\t// @[issue-slot.scala:52:14]\n input [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_4_bits_uop_fp_ctrl_fromint,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_4_bits_uop_fp_ctrl_toint,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_4_bits_uop_fp_ctrl_fma,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_4_bits_uop_fp_ctrl_div,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_4_bits_uop_fp_ctrl_wflags,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_4_bits_uop_fp_ctrl_vec,\t// @[issue-slot.scala:52:14]\n input [6:0] io_wakeup_ports_4_bits_uop_rob_idx,\t// @[issue-slot.scala:52:14]\n input [4:0] io_wakeup_ports_4_bits_uop_ldq_idx,\t// @[issue-slot.scala:52:14]\n input [4:0] io_wakeup_ports_4_bits_uop_stq_idx,\t// @[issue-slot.scala:52:14]\n input [1:0] io_wakeup_ports_4_bits_uop_rxq_idx,\t// @[issue-slot.scala:52:14]\n input [6:0] io_wakeup_ports_4_bits_uop_pdst,\t// @[issue-slot.scala:52:14]\n input [6:0] io_wakeup_ports_4_bits_uop_prs1,\t// @[issue-slot.scala:52:14]\n input [6:0] io_wakeup_ports_4_bits_uop_prs2,\t// @[issue-slot.scala:52:14]\n input [6:0] io_wakeup_ports_4_bits_uop_prs3,\t// @[issue-slot.scala:52:14]\n input [4:0] io_wakeup_ports_4_bits_uop_ppred,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_4_bits_uop_prs1_busy,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_4_bits_uop_prs2_busy,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_4_bits_uop_prs3_busy,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_4_bits_uop_ppred_busy,\t// @[issue-slot.scala:52:14]\n input [6:0] io_wakeup_ports_4_bits_uop_stale_pdst,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_4_bits_uop_exception,\t// @[issue-slot.scala:52:14]\n input [63:0] io_wakeup_ports_4_bits_uop_exc_cause,\t// @[issue-slot.scala:52:14]\n input [4:0] io_wakeup_ports_4_bits_uop_mem_cmd,\t// @[issue-slot.scala:52:14]\n input [1:0] io_wakeup_ports_4_bits_uop_mem_size,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_4_bits_uop_mem_signed,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_4_bits_uop_uses_ldq,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_4_bits_uop_uses_stq,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_4_bits_uop_is_unique,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_4_bits_uop_flush_on_commit,\t// @[issue-slot.scala:52:14]\n input [2:0] io_wakeup_ports_4_bits_uop_csr_cmd,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_4_bits_uop_ldst_is_rs1,\t// @[issue-slot.scala:52:14]\n input [5:0] io_wakeup_ports_4_bits_uop_ldst,\t// @[issue-slot.scala:52:14]\n input [5:0] io_wakeup_ports_4_bits_uop_lrs1,\t// @[issue-slot.scala:52:14]\n input [5:0] io_wakeup_ports_4_bits_uop_lrs2,\t// @[issue-slot.scala:52:14]\n input [5:0] io_wakeup_ports_4_bits_uop_lrs3,\t// @[issue-slot.scala:52:14]\n input [1:0] io_wakeup_ports_4_bits_uop_dst_rtype,\t// @[issue-slot.scala:52:14]\n input [1:0] io_wakeup_ports_4_bits_uop_lrs1_rtype,\t// @[issue-slot.scala:52:14]\n input [1:0] io_wakeup_ports_4_bits_uop_lrs2_rtype,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_4_bits_uop_frs3_en,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_4_bits_uop_fcn_dw,\t// @[issue-slot.scala:52:14]\n input [4:0] io_wakeup_ports_4_bits_uop_fcn_op,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_4_bits_uop_fp_val,\t// @[issue-slot.scala:52:14]\n input [2:0] io_wakeup_ports_4_bits_uop_fp_rm,\t// @[issue-slot.scala:52:14]\n input [1:0] io_wakeup_ports_4_bits_uop_fp_typ,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_4_bits_uop_xcpt_pf_if,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_4_bits_uop_xcpt_ae_if,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_4_bits_uop_xcpt_ma_if,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_4_bits_uop_bp_debug_if,\t// @[issue-slot.scala:52:14]\n input io_wakeup_ports_4_bits_uop_bp_xcpt_if,\t// @[issue-slot.scala:52:14]\n input [2:0] io_wakeup_ports_4_bits_uop_debug_fsrc,\t// @[issue-slot.scala:52:14]\n input [2:0] io_wakeup_ports_4_bits_uop_debug_tsrc,\t// @[issue-slot.scala:52:14]\n input io_pred_wakeup_port_valid,\t// @[issue-slot.scala:52:14]\n input [4:0] io_pred_wakeup_port_bits,\t// @[issue-slot.scala:52:14]\n input [2:0] io_child_rebusys\t// @[issue-slot.scala:52:14]\n);\n\n wire [15:0] next_uop_out_br_mask;\t// @[util.scala:104:23]\n wire io_grant_0 = io_grant;\t// @[issue-slot.scala:49:7]\n wire io_in_uop_valid_0 = io_in_uop_valid;\t// @[issue-slot.scala:49:7]\n wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst;\t// @[issue-slot.scala:49:7]\n wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst;\t// @[issue-slot.scala:49:7]\n wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc;\t// @[issue-slot.scala:49:7]\n wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc;\t// @[issue-slot.scala:49:7]\n wire io_in_uop_bits_iq_type_0_0 = io_in_uop_bits_iq_type_0;\t// @[issue-slot.scala:49:7]\n wire io_in_uop_bits_iq_type_1_0 = io_in_uop_bits_iq_type_1;\t// @[issue-slot.scala:49:7]\n wire io_in_uop_bits_iq_type_2_0 = io_in_uop_bits_iq_type_2;\t// @[issue-slot.scala:49:7]\n wire io_in_uop_bits_iq_type_3_0 = io_in_uop_bits_iq_type_3;\t// @[issue-slot.scala:49:7]\n wire io_in_uop_bits_fu_code_0_0 = io_in_uop_bits_fu_code_0;\t// @[issue-slot.scala:49:7]\n wire io_in_uop_bits_fu_code_1_0 = io_in_uop_bits_fu_code_1;\t// @[issue-slot.scala:49:7]\n wire io_in_uop_bits_fu_code_2_0 = io_in_uop_bits_fu_code_2;\t// @[issue-slot.scala:49:7]\n wire io_in_uop_bits_fu_code_3_0 = io_in_uop_bits_fu_code_3;\t// @[issue-slot.scala:49:7]\n wire io_in_uop_bits_fu_code_4_0 = io_in_uop_bits_fu_code_4;\t// @[issue-slot.scala:49:7]\n wire io_in_uop_bits_fu_code_5_0 = io_in_uop_bits_fu_code_5;\t// @[issue-slot.scala:49:7]\n wire io_in_uop_bits_fu_code_6_0 = io_in_uop_bits_fu_code_6;\t// @[issue-slot.scala:49:7]\n wire io_in_uop_bits_fu_code_7_0 = io_in_uop_bits_fu_code_7;\t// @[issue-slot.scala:49:7]\n wire io_in_uop_bits_fu_code_8_0 = io_in_uop_bits_fu_code_8;\t// @[issue-slot.scala:49:7]\n wire io_in_uop_bits_fu_code_9_0 = io_in_uop_bits_fu_code_9;\t// @[issue-slot.scala:49:7]\n wire io_in_uop_bits_iw_issued_0 = io_in_uop_bits_iw_issued;\t// @[issue-slot.scala:49:7]\n wire [2:0] io_in_uop_bits_iw_p1_speculative_child_0 = io_in_uop_bits_iw_p1_speculative_child;\t// @[issue-slot.scala:49:7]\n wire [2:0] io_in_uop_bits_iw_p2_speculative_child_0 = io_in_uop_bits_iw_p2_speculative_child;\t// @[issue-slot.scala:49:7]\n wire io_in_uop_bits_iw_p1_bypass_hint_0 = io_in_uop_bits_iw_p1_bypass_hint;\t// @[issue-slot.scala:49:7]\n wire io_in_uop_bits_iw_p2_bypass_hint_0 = io_in_uop_bits_iw_p2_bypass_hint;\t// @[issue-slot.scala:49:7]\n wire io_in_uop_bits_iw_p3_bypass_hint_0 = io_in_uop_bits_iw_p3_bypass_hint;\t// @[issue-slot.scala:49:7]\n wire [2:0] io_in_uop_bits_dis_col_sel_0 = io_in_uop_bits_dis_col_sel;\t// @[issue-slot.scala:49:7]\n wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask;\t// @[issue-slot.scala:49:7]\n wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag;\t// @[issue-slot.scala:49:7]\n wire [3:0] io_in_uop_bits_br_type_0 = io_in_uop_bits_br_type;\t// @[issue-slot.scala:49:7]\n wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb;\t// @[issue-slot.scala:49:7]\n wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence;\t// @[issue-slot.scala:49:7]\n wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei;\t// @[issue-slot.scala:49:7]\n wire io_in_uop_bits_is_sfence_0 = io_in_uop_bits_is_sfence;\t// @[issue-slot.scala:49:7]\n wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo;\t// @[issue-slot.scala:49:7]\n wire io_in_uop_bits_is_eret_0 = io_in_uop_bits_is_eret;\t// @[issue-slot.scala:49:7]\n wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc;\t// @[issue-slot.scala:49:7]\n wire io_in_uop_bits_is_rocc_0 = io_in_uop_bits_is_rocc;\t// @[issue-slot.scala:49:7]\n wire io_in_uop_bits_is_mov_0 = io_in_uop_bits_is_mov;\t// @[issue-slot.scala:49:7]\n wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx;\t// @[issue-slot.scala:49:7]\n wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst;\t// @[issue-slot.scala:49:7]\n wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob;\t// @[issue-slot.scala:49:7]\n wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken;\t// @[issue-slot.scala:49:7]\n wire io_in_uop_bits_imm_rename_0 = io_in_uop_bits_imm_rename;\t// @[issue-slot.scala:49:7]\n wire [2:0] io_in_uop_bits_imm_sel_0 = io_in_uop_bits_imm_sel;\t// @[issue-slot.scala:49:7]\n wire [4:0] io_in_uop_bits_pimm_0 = io_in_uop_bits_pimm;\t// @[issue-slot.scala:49:7]\n wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed;\t// @[issue-slot.scala:49:7]\n wire [1:0] io_in_uop_bits_op1_sel_0 = io_in_uop_bits_op1_sel;\t// @[issue-slot.scala:49:7]\n wire [2:0] io_in_uop_bits_op2_sel_0 = io_in_uop_bits_op2_sel;\t// @[issue-slot.scala:49:7]\n wire io_in_uop_bits_fp_ctrl_ldst_0 = io_in_uop_bits_fp_ctrl_ldst;\t// @[issue-slot.scala:49:7]\n wire io_in_uop_bits_fp_ctrl_wen_0 = io_in_uop_bits_fp_ctrl_wen;\t// @[issue-slot.scala:49:7]\n wire io_in_uop_bits_fp_ctrl_ren1_0 = io_in_uop_bits_fp_ctrl_ren1;\t// @[issue-slot.scala:49:7]\n wire io_in_uop_bits_fp_ctrl_ren2_0 = io_in_uop_bits_fp_ctrl_ren2;\t// @[issue-slot.scala:49:7]\n wire io_in_uop_bits_fp_ctrl_ren3_0 = io_in_uop_bits_fp_ctrl_ren3;\t// @[issue-slot.scala:49:7]\n wire io_in_uop_bits_fp_ctrl_swap12_0 = io_in_uop_bits_fp_ctrl_swap12;\t// @[issue-slot.scala:49:7]\n wire io_in_uop_bits_fp_ctrl_swap23_0 = io_in_uop_bits_fp_ctrl_swap23;\t// @[issue-slot.scala:49:7]\n wire [1:0] io_in_uop_bits_fp_ctrl_typeTagIn_0 = io_in_uop_bits_fp_ctrl_typeTagIn;\t// @[issue-slot.scala:49:7]\n wire [1:0] io_in_uop_bits_fp_ctrl_typeTagOut_0 = io_in_uop_bits_fp_ctrl_typeTagOut;\t// @[issue-slot.scala:49:7]\n wire io_in_uop_bits_fp_ctrl_fromint_0 = io_in_uop_bits_fp_ctrl_fromint;\t// @[issue-slot.scala:49:7]\n wire io_in_uop_bits_fp_ctrl_toint_0 = io_in_uop_bits_fp_ctrl_toint;\t// @[issue-slot.scala:49:7]\n wire io_in_uop_bits_fp_ctrl_fastpipe_0 = io_in_uop_bits_fp_ctrl_fastpipe;\t// @[issue-slot.scala:49:7]\n wire io_in_uop_bits_fp_ctrl_fma_0 = io_in_uop_bits_fp_ctrl_fma;\t// @[issue-slot.scala:49:7]\n wire io_in_uop_bits_fp_ctrl_div_0 = io_in_uop_bits_fp_ctrl_div;\t// @[issue-slot.scala:49:7]\n wire io_in_uop_bits_fp_ctrl_sqrt_0 = io_in_uop_bits_fp_ctrl_sqrt;\t// @[issue-slot.scala:49:7]\n wire io_in_uop_bits_fp_ctrl_wflags_0 = io_in_uop_bits_fp_ctrl_wflags;\t// @[issue-slot.scala:49:7]\n wire io_in_uop_bits_fp_ctrl_vec_0 = io_in_uop_bits_fp_ctrl_vec;\t// @[issue-slot.scala:49:7]\n wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx;\t// @[issue-slot.scala:49:7]\n wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx;\t// @[issue-slot.scala:49:7]\n wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx;\t// @[issue-slot.scala:49:7]\n wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx;\t// @[issue-slot.scala:49:7]\n wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst;\t// @[issue-slot.scala:49:7]\n wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1;\t// @[issue-slot.scala:49:7]\n wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2;\t// @[issue-slot.scala:49:7]\n wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3;\t// @[issue-slot.scala:49:7]\n wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred;\t// @[issue-slot.scala:49:7]\n wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy;\t// @[issue-slot.scala:49:7]\n wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy;\t// @[issue-slot.scala:49:7]\n wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy;\t// @[issue-slot.scala:49:7]\n wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy;\t// @[issue-slot.scala:49:7]\n wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst;\t// @[issue-slot.scala:49:7]\n wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception;\t// @[issue-slot.scala:49:7]\n wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause;\t// @[issue-slot.scala:49:7]\n wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd;\t// @[issue-slot.scala:49:7]\n wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size;\t// @[issue-slot.scala:49:7]\n wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed;\t// @[issue-slot.scala:49:7]\n wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq;\t// @[issue-slot.scala:49:7]\n wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq;\t// @[issue-slot.scala:49:7]\n wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique;\t// @[issue-slot.scala:49:7]\n wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit;\t// @[issue-slot.scala:49:7]\n wire [2:0] io_in_uop_bits_csr_cmd_0 = io_in_uop_bits_csr_cmd;\t// @[issue-slot.scala:49:7]\n wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1;\t// @[issue-slot.scala:49:7]\n wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst;\t// @[issue-slot.scala:49:7]\n wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1;\t// @[issue-slot.scala:49:7]\n wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2;\t// @[issue-slot.scala:49:7]\n wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3;\t// @[issue-slot.scala:49:7]\n wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype;\t// @[issue-slot.scala:49:7]\n wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype;\t// @[issue-slot.scala:49:7]\n wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype;\t// @[issue-slot.scala:49:7]\n wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en;\t// @[issue-slot.scala:49:7]\n wire io_in_uop_bits_fcn_dw_0 = io_in_uop_bits_fcn_dw;\t// @[issue-slot.scala:49:7]\n wire [4:0] io_in_uop_bits_fcn_op_0 = io_in_uop_bits_fcn_op;\t// @[issue-slot.scala:49:7]\n wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val;\t// @[issue-slot.scala:49:7]\n wire [2:0] io_in_uop_bits_fp_rm_0 = io_in_uop_bits_fp_rm;\t// @[issue-slot.scala:49:7]\n wire [1:0] io_in_uop_bits_fp_typ_0 = io_in_uop_bits_fp_typ;\t// @[issue-slot.scala:49:7]\n wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if;\t// @[issue-slot.scala:49:7]\n wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if;\t// @[issue-slot.scala:49:7]\n wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if;\t// @[issue-slot.scala:49:7]\n wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if;\t// @[issue-slot.scala:49:7]\n wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if;\t// @[issue-slot.scala:49:7]\n wire [2:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc;\t// @[issue-slot.scala:49:7]\n wire [2:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc;\t// @[issue-slot.scala:49:7]\n wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask;\t// @[issue-slot.scala:49:7]\n wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask;\t// @[issue-slot.scala:49:7]\n wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst;\t// @[issue-slot.scala:49:7]\n wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst;\t// @[issue-slot.scala:49:7]\n wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc;\t// @[issue-slot.scala:49:7]\n wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc;\t// @[issue-slot.scala:49:7]\n wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0;\t// @[issue-slot.scala:49:7]\n wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1;\t// @[issue-slot.scala:49:7]\n wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2;\t// @[issue-slot.scala:49:7]\n wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3;\t// @[issue-slot.scala:49:7]\n wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0;\t// @[issue-slot.scala:49:7]\n wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1;\t// @[issue-slot.scala:49:7]\n wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2;\t// @[issue-slot.scala:49:7]\n wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3;\t// @[issue-slot.scala:49:7]\n wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4;\t// @[issue-slot.scala:49:7]\n wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5;\t// @[issue-slot.scala:49:7]\n wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6;\t// @[issue-slot.scala:49:7]\n wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7;\t// @[issue-slot.scala:49:7]\n wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8;\t// @[issue-slot.scala:49:7]\n wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9;\t// @[issue-slot.scala:49:7]\n wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued;\t// @[issue-slot.scala:49:7]\n wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen;\t// @[issue-slot.scala:49:7]\n wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen;\t// @[issue-slot.scala:49:7]\n wire [2:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child;\t// @[issue-slot.scala:49:7]\n wire [2:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child;\t// @[issue-slot.scala:49:7]\n wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint;\t// @[issue-slot.scala:49:7]\n wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint;\t// @[issue-slot.scala:49:7]\n wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint;\t// @[issue-slot.scala:49:7]\n wire [2:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel;\t// @[issue-slot.scala:49:7]\n wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask;\t// @[issue-slot.scala:49:7]\n wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag;\t// @[issue-slot.scala:49:7]\n wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type;\t// @[issue-slot.scala:49:7]\n wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb;\t// @[issue-slot.scala:49:7]\n wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence;\t// @[issue-slot.scala:49:7]\n wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei;\t// @[issue-slot.scala:49:7]\n wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence;\t// @[issue-slot.scala:49:7]\n wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo;\t// @[issue-slot.scala:49:7]\n wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret;\t// @[issue-slot.scala:49:7]\n wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc;\t// @[issue-slot.scala:49:7]\n wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc;\t// @[issue-slot.scala:49:7]\n wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov;\t// @[issue-slot.scala:49:7]\n wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx;\t// @[issue-slot.scala:49:7]\n wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst;\t// @[issue-slot.scala:49:7]\n wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob;\t// @[issue-slot.scala:49:7]\n wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken;\t// @[issue-slot.scala:49:7]\n wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename;\t// @[issue-slot.scala:49:7]\n wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel;\t// @[issue-slot.scala:49:7]\n wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm;\t// @[issue-slot.scala:49:7]\n wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed;\t// @[issue-slot.scala:49:7]\n wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel;\t// @[issue-slot.scala:49:7]\n wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel;\t// @[issue-slot.scala:49:7]\n wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst;\t// @[issue-slot.scala:49:7]\n wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen;\t// @[issue-slot.scala:49:7]\n wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1;\t// @[issue-slot.scala:49:7]\n wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2;\t// @[issue-slot.scala:49:7]\n wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3;\t// @[issue-slot.scala:49:7]\n wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12;\t// @[issue-slot.scala:49:7]\n wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23;\t// @[issue-slot.scala:49:7]\n wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn;\t// @[issue-slot.scala:49:7]\n wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut;\t// @[issue-slot.scala:49:7]\n wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint;\t// @[issue-slot.scala:49:7]\n wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint;\t// @[issue-slot.scala:49:7]\n wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe;\t// @[issue-slot.scala:49:7]\n wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma;\t// @[issue-slot.scala:49:7]\n wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div;\t// @[issue-slot.scala:49:7]\n wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt;\t// @[issue-slot.scala:49:7]\n wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags;\t// @[issue-slot.scala:49:7]\n wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec;\t// @[issue-slot.scala:49:7]\n wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx;\t// @[issue-slot.scala:49:7]\n wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx;\t// @[issue-slot.scala:49:7]\n wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx;\t// @[issue-slot.scala:49:7]\n wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx;\t// @[issue-slot.scala:49:7]\n wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst;\t// @[issue-slot.scala:49:7]\n wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1;\t// @[issue-slot.scala:49:7]\n wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2;\t// @[issue-slot.scala:49:7]\n wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3;\t// @[issue-slot.scala:49:7]\n wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred;\t// @[issue-slot.scala:49:7]\n wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy;\t// @[issue-slot.scala:49:7]\n wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy;\t// @[issue-slot.scala:49:7]\n wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy;\t// @[issue-slot.scala:49:7]\n wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy;\t// @[issue-slot.scala:49:7]\n wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst;\t// @[issue-slot.scala:49:7]\n wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception;\t// @[issue-slot.scala:49:7]\n wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause;\t// @[issue-slot.scala:49:7]\n wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd;\t// @[issue-slot.scala:49:7]\n wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size;\t// @[issue-slot.scala:49:7]\n wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed;\t// @[issue-slot.scala:49:7]\n wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq;\t// @[issue-slot.scala:49:7]\n wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq;\t// @[issue-slot.scala:49:7]\n wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique;\t// @[issue-slot.scala:49:7]\n wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit;\t// @[issue-slot.scala:49:7]\n wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd;\t// @[issue-slot.scala:49:7]\n wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1;\t// @[issue-slot.scala:49:7]\n wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst;\t// @[issue-slot.scala:49:7]\n wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1;\t// @[issue-slot.scala:49:7]\n wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2;\t// @[issue-slot.scala:49:7]\n wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3;\t// @[issue-slot.scala:49:7]\n wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype;\t// @[issue-slot.scala:49:7]\n wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype;\t// @[issue-slot.scala:49:7]\n wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype;\t// @[issue-slot.scala:49:7]\n wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en;\t// @[issue-slot.scala:49:7]\n wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw;\t// @[issue-slot.scala:49:7]\n wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op;\t// @[issue-slot.scala:49:7]\n wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val;\t// @[issue-slot.scala:49:7]\n wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm;\t// @[issue-slot.scala:49:7]\n wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ;\t// @[issue-slot.scala:49:7]\n wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if;\t// @[issue-slot.scala:49:7]\n wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if;\t// @[issue-slot.scala:49:7]\n wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if;\t// @[issue-slot.scala:49:7]\n wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if;\t// @[issue-slot.scala:49:7]\n wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if;\t// @[issue-slot.scala:49:7]\n wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc;\t// @[issue-slot.scala:49:7]\n wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc;\t// @[issue-slot.scala:49:7]\n wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict;\t// @[issue-slot.scala:49:7]\n wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken;\t// @[issue-slot.scala:49:7]\n wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type;\t// @[issue-slot.scala:49:7]\n wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel;\t// @[issue-slot.scala:49:7]\n wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target;\t// @[issue-slot.scala:49:7]\n wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset;\t// @[issue-slot.scala:49:7]\n wire io_kill_0 = io_kill;\t// @[issue-slot.scala:49:7]\n wire io_clear_0 = io_clear;\t// @[issue-slot.scala:49:7]\n wire io_squash_grant_0 = io_squash_grant;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid;\t// @[issue-slot.scala:49:7]\n wire [31:0] io_wakeup_ports_0_bits_uop_inst_0 = io_wakeup_ports_0_bits_uop_inst;\t// @[issue-slot.scala:49:7]\n wire [31:0] io_wakeup_ports_0_bits_uop_debug_inst_0 = io_wakeup_ports_0_bits_uop_debug_inst;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_0_bits_uop_is_rvc_0 = io_wakeup_ports_0_bits_uop_is_rvc;\t// @[issue-slot.scala:49:7]\n wire [39:0] io_wakeup_ports_0_bits_uop_debug_pc_0 = io_wakeup_ports_0_bits_uop_debug_pc;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_0_bits_uop_iq_type_0_0 = io_wakeup_ports_0_bits_uop_iq_type_0;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_0_bits_uop_iq_type_1_0 = io_wakeup_ports_0_bits_uop_iq_type_1;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_0_bits_uop_iq_type_2_0 = io_wakeup_ports_0_bits_uop_iq_type_2;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_0_bits_uop_iq_type_3_0 = io_wakeup_ports_0_bits_uop_iq_type_3;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_0_bits_uop_fu_code_0_0 = io_wakeup_ports_0_bits_uop_fu_code_0;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_0_bits_uop_fu_code_1_0 = io_wakeup_ports_0_bits_uop_fu_code_1;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_0_bits_uop_fu_code_2_0 = io_wakeup_ports_0_bits_uop_fu_code_2;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_0_bits_uop_fu_code_3_0 = io_wakeup_ports_0_bits_uop_fu_code_3;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_0_bits_uop_fu_code_4_0 = io_wakeup_ports_0_bits_uop_fu_code_4;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_0_bits_uop_fu_code_5_0 = io_wakeup_ports_0_bits_uop_fu_code_5;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_0_bits_uop_fu_code_6_0 = io_wakeup_ports_0_bits_uop_fu_code_6;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_0_bits_uop_fu_code_7_0 = io_wakeup_ports_0_bits_uop_fu_code_7;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_0_bits_uop_fu_code_8_0 = io_wakeup_ports_0_bits_uop_fu_code_8;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_0_bits_uop_fu_code_9_0 = io_wakeup_ports_0_bits_uop_fu_code_9;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_0_bits_uop_iw_issued_0 = io_wakeup_ports_0_bits_uop_iw_issued;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen;\t// @[issue-slot.scala:49:7]\n wire [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child;\t// @[issue-slot.scala:49:7]\n wire [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint;\t// @[issue-slot.scala:49:7]\n wire [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel_0 = io_wakeup_ports_0_bits_uop_dis_col_sel;\t// @[issue-slot.scala:49:7]\n wire [15:0] io_wakeup_ports_0_bits_uop_br_mask_0 = io_wakeup_ports_0_bits_uop_br_mask;\t// @[issue-slot.scala:49:7]\n wire [3:0] io_wakeup_ports_0_bits_uop_br_tag_0 = io_wakeup_ports_0_bits_uop_br_tag;\t// @[issue-slot.scala:49:7]\n wire [3:0] io_wakeup_ports_0_bits_uop_br_type_0 = io_wakeup_ports_0_bits_uop_br_type;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_0_bits_uop_is_sfb_0 = io_wakeup_ports_0_bits_uop_is_sfb;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_0_bits_uop_is_fence_0 = io_wakeup_ports_0_bits_uop_is_fence;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_0_bits_uop_is_fencei_0 = io_wakeup_ports_0_bits_uop_is_fencei;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_0_bits_uop_is_sfence_0 = io_wakeup_ports_0_bits_uop_is_sfence;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_0_bits_uop_is_amo_0 = io_wakeup_ports_0_bits_uop_is_amo;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_0_bits_uop_is_eret_0 = io_wakeup_ports_0_bits_uop_is_eret;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_0_bits_uop_is_sys_pc2epc;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_0_bits_uop_is_rocc_0 = io_wakeup_ports_0_bits_uop_is_rocc;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_0_bits_uop_is_mov_0 = io_wakeup_ports_0_bits_uop_is_mov;\t// @[issue-slot.scala:49:7]\n wire [4:0] io_wakeup_ports_0_bits_uop_ftq_idx_0 = io_wakeup_ports_0_bits_uop_ftq_idx;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_0_bits_uop_edge_inst_0 = io_wakeup_ports_0_bits_uop_edge_inst;\t// @[issue-slot.scala:49:7]\n wire [5:0] io_wakeup_ports_0_bits_uop_pc_lob_0 = io_wakeup_ports_0_bits_uop_pc_lob;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_0_bits_uop_taken_0 = io_wakeup_ports_0_bits_uop_taken;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_0_bits_uop_imm_rename_0 = io_wakeup_ports_0_bits_uop_imm_rename;\t// @[issue-slot.scala:49:7]\n wire [2:0] io_wakeup_ports_0_bits_uop_imm_sel_0 = io_wakeup_ports_0_bits_uop_imm_sel;\t// @[issue-slot.scala:49:7]\n wire [4:0] io_wakeup_ports_0_bits_uop_pimm_0 = io_wakeup_ports_0_bits_uop_pimm;\t// @[issue-slot.scala:49:7]\n wire [19:0] io_wakeup_ports_0_bits_uop_imm_packed_0 = io_wakeup_ports_0_bits_uop_imm_packed;\t// @[issue-slot.scala:49:7]\n wire [1:0] io_wakeup_ports_0_bits_uop_op1_sel_0 = io_wakeup_ports_0_bits_uop_op1_sel;\t// @[issue-slot.scala:49:7]\n wire [2:0] io_wakeup_ports_0_bits_uop_op2_sel_0 = io_wakeup_ports_0_bits_uop_op2_sel;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wen;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23;\t// @[issue-slot.scala:49:7]\n wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn;\t// @[issue-slot.scala:49:7]\n wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_toint;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fma;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_0_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_div;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_vec;\t// @[issue-slot.scala:49:7]\n wire [6:0] io_wakeup_ports_0_bits_uop_rob_idx_0 = io_wakeup_ports_0_bits_uop_rob_idx;\t// @[issue-slot.scala:49:7]\n wire [4:0] io_wakeup_ports_0_bits_uop_ldq_idx_0 = io_wakeup_ports_0_bits_uop_ldq_idx;\t// @[issue-slot.scala:49:7]\n wire [4:0] io_wakeup_ports_0_bits_uop_stq_idx_0 = io_wakeup_ports_0_bits_uop_stq_idx;\t// @[issue-slot.scala:49:7]\n wire [1:0] io_wakeup_ports_0_bits_uop_rxq_idx_0 = io_wakeup_ports_0_bits_uop_rxq_idx;\t// @[issue-slot.scala:49:7]\n wire [6:0] io_wakeup_ports_0_bits_uop_pdst_0 = io_wakeup_ports_0_bits_uop_pdst;\t// @[issue-slot.scala:49:7]\n wire [6:0] io_wakeup_ports_0_bits_uop_prs1_0 = io_wakeup_ports_0_bits_uop_prs1;\t// @[issue-slot.scala:49:7]\n wire [6:0] io_wakeup_ports_0_bits_uop_prs2_0 = io_wakeup_ports_0_bits_uop_prs2;\t// @[issue-slot.scala:49:7]\n wire [6:0] io_wakeup_ports_0_bits_uop_prs3_0 = io_wakeup_ports_0_bits_uop_prs3;\t// @[issue-slot.scala:49:7]\n wire [4:0] io_wakeup_ports_0_bits_uop_ppred_0 = io_wakeup_ports_0_bits_uop_ppred;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_0_bits_uop_prs1_busy_0 = io_wakeup_ports_0_bits_uop_prs1_busy;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_0_bits_uop_prs2_busy_0 = io_wakeup_ports_0_bits_uop_prs2_busy;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_0_bits_uop_prs3_busy_0 = io_wakeup_ports_0_bits_uop_prs3_busy;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_0_bits_uop_ppred_busy_0 = io_wakeup_ports_0_bits_uop_ppred_busy;\t// @[issue-slot.scala:49:7]\n wire [6:0] io_wakeup_ports_0_bits_uop_stale_pdst_0 = io_wakeup_ports_0_bits_uop_stale_pdst;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_0_bits_uop_exception_0 = io_wakeup_ports_0_bits_uop_exception;\t// @[issue-slot.scala:49:7]\n wire [63:0] io_wakeup_ports_0_bits_uop_exc_cause_0 = io_wakeup_ports_0_bits_uop_exc_cause;\t// @[issue-slot.scala:49:7]\n wire [4:0] io_wakeup_ports_0_bits_uop_mem_cmd_0 = io_wakeup_ports_0_bits_uop_mem_cmd;\t// @[issue-slot.scala:49:7]\n wire [1:0] io_wakeup_ports_0_bits_uop_mem_size_0 = io_wakeup_ports_0_bits_uop_mem_size;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_0_bits_uop_mem_signed_0 = io_wakeup_ports_0_bits_uop_mem_signed;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_0_bits_uop_uses_ldq_0 = io_wakeup_ports_0_bits_uop_uses_ldq;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_0_bits_uop_uses_stq_0 = io_wakeup_ports_0_bits_uop_uses_stq;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_0_bits_uop_is_unique_0 = io_wakeup_ports_0_bits_uop_is_unique;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_0_bits_uop_flush_on_commit_0 = io_wakeup_ports_0_bits_uop_flush_on_commit;\t// @[issue-slot.scala:49:7]\n wire [2:0] io_wakeup_ports_0_bits_uop_csr_cmd_0 = io_wakeup_ports_0_bits_uop_csr_cmd;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_0_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_0_bits_uop_ldst_is_rs1;\t// @[issue-slot.scala:49:7]\n wire [5:0] io_wakeup_ports_0_bits_uop_ldst_0 = io_wakeup_ports_0_bits_uop_ldst;\t// @[issue-slot.scala:49:7]\n wire [5:0] io_wakeup_ports_0_bits_uop_lrs1_0 = io_wakeup_ports_0_bits_uop_lrs1;\t// @[issue-slot.scala:49:7]\n wire [5:0] io_wakeup_ports_0_bits_uop_lrs2_0 = io_wakeup_ports_0_bits_uop_lrs2;\t// @[issue-slot.scala:49:7]\n wire [5:0] io_wakeup_ports_0_bits_uop_lrs3_0 = io_wakeup_ports_0_bits_uop_lrs3;\t// @[issue-slot.scala:49:7]\n wire [1:0] io_wakeup_ports_0_bits_uop_dst_rtype_0 = io_wakeup_ports_0_bits_uop_dst_rtype;\t// @[issue-slot.scala:49:7]\n wire [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype_0 = io_wakeup_ports_0_bits_uop_lrs1_rtype;\t// @[issue-slot.scala:49:7]\n wire [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype_0 = io_wakeup_ports_0_bits_uop_lrs2_rtype;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_0_bits_uop_frs3_en_0 = io_wakeup_ports_0_bits_uop_frs3_en;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_0_bits_uop_fcn_dw_0 = io_wakeup_ports_0_bits_uop_fcn_dw;\t// @[issue-slot.scala:49:7]\n wire [4:0] io_wakeup_ports_0_bits_uop_fcn_op_0 = io_wakeup_ports_0_bits_uop_fcn_op;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_0_bits_uop_fp_val_0 = io_wakeup_ports_0_bits_uop_fp_val;\t// @[issue-slot.scala:49:7]\n wire [2:0] io_wakeup_ports_0_bits_uop_fp_rm_0 = io_wakeup_ports_0_bits_uop_fp_rm;\t// @[issue-slot.scala:49:7]\n wire [1:0] io_wakeup_ports_0_bits_uop_fp_typ_0 = io_wakeup_ports_0_bits_uop_fp_typ;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_0_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_0_bits_uop_xcpt_pf_if;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_0_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ae_if;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_0_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ma_if;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_0_bits_uop_bp_debug_if_0 = io_wakeup_ports_0_bits_uop_bp_debug_if;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_0_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_0_bits_uop_bp_xcpt_if;\t// @[issue-slot.scala:49:7]\n wire [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc_0 = io_wakeup_ports_0_bits_uop_debug_fsrc;\t// @[issue-slot.scala:49:7]\n wire [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc_0 = io_wakeup_ports_0_bits_uop_debug_tsrc;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_0_bits_bypassable_0 = io_wakeup_ports_0_bits_bypassable;\t// @[issue-slot.scala:49:7]\n wire [2:0] io_wakeup_ports_0_bits_speculative_mask_0 = io_wakeup_ports_0_bits_speculative_mask;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_0_bits_rebusy_0 = io_wakeup_ports_0_bits_rebusy;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid;\t// @[issue-slot.scala:49:7]\n wire [31:0] io_wakeup_ports_1_bits_uop_inst_0 = io_wakeup_ports_1_bits_uop_inst;\t// @[issue-slot.scala:49:7]\n wire [31:0] io_wakeup_ports_1_bits_uop_debug_inst_0 = io_wakeup_ports_1_bits_uop_debug_inst;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_1_bits_uop_is_rvc_0 = io_wakeup_ports_1_bits_uop_is_rvc;\t// @[issue-slot.scala:49:7]\n wire [39:0] io_wakeup_ports_1_bits_uop_debug_pc_0 = io_wakeup_ports_1_bits_uop_debug_pc;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_1_bits_uop_iq_type_0_0 = io_wakeup_ports_1_bits_uop_iq_type_0;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_1_bits_uop_iq_type_1_0 = io_wakeup_ports_1_bits_uop_iq_type_1;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_1_bits_uop_iq_type_2_0 = io_wakeup_ports_1_bits_uop_iq_type_2;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_1_bits_uop_iq_type_3_0 = io_wakeup_ports_1_bits_uop_iq_type_3;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_1_bits_uop_fu_code_0_0 = io_wakeup_ports_1_bits_uop_fu_code_0;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_1_bits_uop_fu_code_1_0 = io_wakeup_ports_1_bits_uop_fu_code_1;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_1_bits_uop_fu_code_2_0 = io_wakeup_ports_1_bits_uop_fu_code_2;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_1_bits_uop_fu_code_3_0 = io_wakeup_ports_1_bits_uop_fu_code_3;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_1_bits_uop_fu_code_4_0 = io_wakeup_ports_1_bits_uop_fu_code_4;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_1_bits_uop_fu_code_5_0 = io_wakeup_ports_1_bits_uop_fu_code_5;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_1_bits_uop_fu_code_6_0 = io_wakeup_ports_1_bits_uop_fu_code_6;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_1_bits_uop_fu_code_7_0 = io_wakeup_ports_1_bits_uop_fu_code_7;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_1_bits_uop_fu_code_8_0 = io_wakeup_ports_1_bits_uop_fu_code_8;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_1_bits_uop_fu_code_9_0 = io_wakeup_ports_1_bits_uop_fu_code_9;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_1_bits_uop_iw_issued_0 = io_wakeup_ports_1_bits_uop_iw_issued;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen;\t// @[issue-slot.scala:49:7]\n wire [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child;\t// @[issue-slot.scala:49:7]\n wire [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint;\t// @[issue-slot.scala:49:7]\n wire [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel_0 = io_wakeup_ports_1_bits_uop_dis_col_sel;\t// @[issue-slot.scala:49:7]\n wire [15:0] io_wakeup_ports_1_bits_uop_br_mask_0 = io_wakeup_ports_1_bits_uop_br_mask;\t// @[issue-slot.scala:49:7]\n wire [3:0] io_wakeup_ports_1_bits_uop_br_tag_0 = io_wakeup_ports_1_bits_uop_br_tag;\t// @[issue-slot.scala:49:7]\n wire [3:0] io_wakeup_ports_1_bits_uop_br_type_0 = io_wakeup_ports_1_bits_uop_br_type;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_1_bits_uop_is_sfb_0 = io_wakeup_ports_1_bits_uop_is_sfb;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_1_bits_uop_is_fence_0 = io_wakeup_ports_1_bits_uop_is_fence;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_1_bits_uop_is_fencei_0 = io_wakeup_ports_1_bits_uop_is_fencei;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_1_bits_uop_is_sfence_0 = io_wakeup_ports_1_bits_uop_is_sfence;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_1_bits_uop_is_amo_0 = io_wakeup_ports_1_bits_uop_is_amo;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_1_bits_uop_is_eret_0 = io_wakeup_ports_1_bits_uop_is_eret;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_1_bits_uop_is_sys_pc2epc;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_1_bits_uop_is_rocc_0 = io_wakeup_ports_1_bits_uop_is_rocc;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_1_bits_uop_is_mov_0 = io_wakeup_ports_1_bits_uop_is_mov;\t// @[issue-slot.scala:49:7]\n wire [4:0] io_wakeup_ports_1_bits_uop_ftq_idx_0 = io_wakeup_ports_1_bits_uop_ftq_idx;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_1_bits_uop_edge_inst_0 = io_wakeup_ports_1_bits_uop_edge_inst;\t// @[issue-slot.scala:49:7]\n wire [5:0] io_wakeup_ports_1_bits_uop_pc_lob_0 = io_wakeup_ports_1_bits_uop_pc_lob;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_1_bits_uop_taken_0 = io_wakeup_ports_1_bits_uop_taken;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_1_bits_uop_imm_rename_0 = io_wakeup_ports_1_bits_uop_imm_rename;\t// @[issue-slot.scala:49:7]\n wire [2:0] io_wakeup_ports_1_bits_uop_imm_sel_0 = io_wakeup_ports_1_bits_uop_imm_sel;\t// @[issue-slot.scala:49:7]\n wire [4:0] io_wakeup_ports_1_bits_uop_pimm_0 = io_wakeup_ports_1_bits_uop_pimm;\t// @[issue-slot.scala:49:7]\n wire [19:0] io_wakeup_ports_1_bits_uop_imm_packed_0 = io_wakeup_ports_1_bits_uop_imm_packed;\t// @[issue-slot.scala:49:7]\n wire [1:0] io_wakeup_ports_1_bits_uop_op1_sel_0 = io_wakeup_ports_1_bits_uop_op1_sel;\t// @[issue-slot.scala:49:7]\n wire [2:0] io_wakeup_ports_1_bits_uop_op2_sel_0 = io_wakeup_ports_1_bits_uop_op2_sel;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wen;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23;\t// @[issue-slot.scala:49:7]\n wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn;\t// @[issue-slot.scala:49:7]\n wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_toint;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fma;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_1_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_div;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_vec;\t// @[issue-slot.scala:49:7]\n wire [6:0] io_wakeup_ports_1_bits_uop_rob_idx_0 = io_wakeup_ports_1_bits_uop_rob_idx;\t// @[issue-slot.scala:49:7]\n wire [4:0] io_wakeup_ports_1_bits_uop_ldq_idx_0 = io_wakeup_ports_1_bits_uop_ldq_idx;\t// @[issue-slot.scala:49:7]\n wire [4:0] io_wakeup_ports_1_bits_uop_stq_idx_0 = io_wakeup_ports_1_bits_uop_stq_idx;\t// @[issue-slot.scala:49:7]\n wire [1:0] io_wakeup_ports_1_bits_uop_rxq_idx_0 = io_wakeup_ports_1_bits_uop_rxq_idx;\t// @[issue-slot.scala:49:7]\n wire [6:0] io_wakeup_ports_1_bits_uop_pdst_0 = io_wakeup_ports_1_bits_uop_pdst;\t// @[issue-slot.scala:49:7]\n wire [6:0] io_wakeup_ports_1_bits_uop_prs1_0 = io_wakeup_ports_1_bits_uop_prs1;\t// @[issue-slot.scala:49:7]\n wire [6:0] io_wakeup_ports_1_bits_uop_prs2_0 = io_wakeup_ports_1_bits_uop_prs2;\t// @[issue-slot.scala:49:7]\n wire [6:0] io_wakeup_ports_1_bits_uop_prs3_0 = io_wakeup_ports_1_bits_uop_prs3;\t// @[issue-slot.scala:49:7]\n wire [4:0] io_wakeup_ports_1_bits_uop_ppred_0 = io_wakeup_ports_1_bits_uop_ppred;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_1_bits_uop_prs1_busy_0 = io_wakeup_ports_1_bits_uop_prs1_busy;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_1_bits_uop_prs2_busy_0 = io_wakeup_ports_1_bits_uop_prs2_busy;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_1_bits_uop_prs3_busy_0 = io_wakeup_ports_1_bits_uop_prs3_busy;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_1_bits_uop_ppred_busy_0 = io_wakeup_ports_1_bits_uop_ppred_busy;\t// @[issue-slot.scala:49:7]\n wire [6:0] io_wakeup_ports_1_bits_uop_stale_pdst_0 = io_wakeup_ports_1_bits_uop_stale_pdst;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_1_bits_uop_exception_0 = io_wakeup_ports_1_bits_uop_exception;\t// @[issue-slot.scala:49:7]\n wire [63:0] io_wakeup_ports_1_bits_uop_exc_cause_0 = io_wakeup_ports_1_bits_uop_exc_cause;\t// @[issue-slot.scala:49:7]\n wire [4:0] io_wakeup_ports_1_bits_uop_mem_cmd_0 = io_wakeup_ports_1_bits_uop_mem_cmd;\t// @[issue-slot.scala:49:7]\n wire [1:0] io_wakeup_ports_1_bits_uop_mem_size_0 = io_wakeup_ports_1_bits_uop_mem_size;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_1_bits_uop_mem_signed_0 = io_wakeup_ports_1_bits_uop_mem_signed;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_1_bits_uop_uses_ldq_0 = io_wakeup_ports_1_bits_uop_uses_ldq;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_1_bits_uop_uses_stq_0 = io_wakeup_ports_1_bits_uop_uses_stq;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_1_bits_uop_is_unique_0 = io_wakeup_ports_1_bits_uop_is_unique;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_1_bits_uop_flush_on_commit_0 = io_wakeup_ports_1_bits_uop_flush_on_commit;\t// @[issue-slot.scala:49:7]\n wire [2:0] io_wakeup_ports_1_bits_uop_csr_cmd_0 = io_wakeup_ports_1_bits_uop_csr_cmd;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_1_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_1_bits_uop_ldst_is_rs1;\t// @[issue-slot.scala:49:7]\n wire [5:0] io_wakeup_ports_1_bits_uop_ldst_0 = io_wakeup_ports_1_bits_uop_ldst;\t// @[issue-slot.scala:49:7]\n wire [5:0] io_wakeup_ports_1_bits_uop_lrs1_0 = io_wakeup_ports_1_bits_uop_lrs1;\t// @[issue-slot.scala:49:7]\n wire [5:0] io_wakeup_ports_1_bits_uop_lrs2_0 = io_wakeup_ports_1_bits_uop_lrs2;\t// @[issue-slot.scala:49:7]\n wire [5:0] io_wakeup_ports_1_bits_uop_lrs3_0 = io_wakeup_ports_1_bits_uop_lrs3;\t// @[issue-slot.scala:49:7]\n wire [1:0] io_wakeup_ports_1_bits_uop_dst_rtype_0 = io_wakeup_ports_1_bits_uop_dst_rtype;\t// @[issue-slot.scala:49:7]\n wire [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype_0 = io_wakeup_ports_1_bits_uop_lrs1_rtype;\t// @[issue-slot.scala:49:7]\n wire [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype_0 = io_wakeup_ports_1_bits_uop_lrs2_rtype;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_1_bits_uop_frs3_en_0 = io_wakeup_ports_1_bits_uop_frs3_en;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_1_bits_uop_fcn_dw_0 = io_wakeup_ports_1_bits_uop_fcn_dw;\t// @[issue-slot.scala:49:7]\n wire [4:0] io_wakeup_ports_1_bits_uop_fcn_op_0 = io_wakeup_ports_1_bits_uop_fcn_op;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_1_bits_uop_fp_val_0 = io_wakeup_ports_1_bits_uop_fp_val;\t// @[issue-slot.scala:49:7]\n wire [2:0] io_wakeup_ports_1_bits_uop_fp_rm_0 = io_wakeup_ports_1_bits_uop_fp_rm;\t// @[issue-slot.scala:49:7]\n wire [1:0] io_wakeup_ports_1_bits_uop_fp_typ_0 = io_wakeup_ports_1_bits_uop_fp_typ;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_1_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_1_bits_uop_xcpt_pf_if;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_1_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ae_if;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_1_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ma_if;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_1_bits_uop_bp_debug_if_0 = io_wakeup_ports_1_bits_uop_bp_debug_if;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_1_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_1_bits_uop_bp_xcpt_if;\t// @[issue-slot.scala:49:7]\n wire [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc_0 = io_wakeup_ports_1_bits_uop_debug_fsrc;\t// @[issue-slot.scala:49:7]\n wire [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc_0 = io_wakeup_ports_1_bits_uop_debug_tsrc;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid;\t// @[issue-slot.scala:49:7]\n wire [31:0] io_wakeup_ports_2_bits_uop_inst_0 = io_wakeup_ports_2_bits_uop_inst;\t// @[issue-slot.scala:49:7]\n wire [31:0] io_wakeup_ports_2_bits_uop_debug_inst_0 = io_wakeup_ports_2_bits_uop_debug_inst;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_2_bits_uop_is_rvc_0 = io_wakeup_ports_2_bits_uop_is_rvc;\t// @[issue-slot.scala:49:7]\n wire [39:0] io_wakeup_ports_2_bits_uop_debug_pc_0 = io_wakeup_ports_2_bits_uop_debug_pc;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_2_bits_uop_iq_type_0_0 = io_wakeup_ports_2_bits_uop_iq_type_0;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_2_bits_uop_iq_type_1_0 = io_wakeup_ports_2_bits_uop_iq_type_1;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_2_bits_uop_iq_type_2_0 = io_wakeup_ports_2_bits_uop_iq_type_2;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_2_bits_uop_iq_type_3_0 = io_wakeup_ports_2_bits_uop_iq_type_3;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_2_bits_uop_fu_code_0_0 = io_wakeup_ports_2_bits_uop_fu_code_0;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_2_bits_uop_fu_code_1_0 = io_wakeup_ports_2_bits_uop_fu_code_1;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_2_bits_uop_fu_code_2_0 = io_wakeup_ports_2_bits_uop_fu_code_2;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_2_bits_uop_fu_code_3_0 = io_wakeup_ports_2_bits_uop_fu_code_3;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_2_bits_uop_fu_code_4_0 = io_wakeup_ports_2_bits_uop_fu_code_4;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_2_bits_uop_fu_code_5_0 = io_wakeup_ports_2_bits_uop_fu_code_5;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_2_bits_uop_fu_code_6_0 = io_wakeup_ports_2_bits_uop_fu_code_6;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_2_bits_uop_fu_code_7_0 = io_wakeup_ports_2_bits_uop_fu_code_7;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_2_bits_uop_fu_code_8_0 = io_wakeup_ports_2_bits_uop_fu_code_8;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_2_bits_uop_fu_code_9_0 = io_wakeup_ports_2_bits_uop_fu_code_9;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_2_bits_uop_iw_issued_0 = io_wakeup_ports_2_bits_uop_iw_issued;\t// @[issue-slot.scala:49:7]\n wire [2:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child;\t// @[issue-slot.scala:49:7]\n wire [2:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint;\t// @[issue-slot.scala:49:7]\n wire [2:0] io_wakeup_ports_2_bits_uop_dis_col_sel_0 = io_wakeup_ports_2_bits_uop_dis_col_sel;\t// @[issue-slot.scala:49:7]\n wire [15:0] io_wakeup_ports_2_bits_uop_br_mask_0 = io_wakeup_ports_2_bits_uop_br_mask;\t// @[issue-slot.scala:49:7]\n wire [3:0] io_wakeup_ports_2_bits_uop_br_tag_0 = io_wakeup_ports_2_bits_uop_br_tag;\t// @[issue-slot.scala:49:7]\n wire [3:0] io_wakeup_ports_2_bits_uop_br_type_0 = io_wakeup_ports_2_bits_uop_br_type;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_2_bits_uop_is_sfb_0 = io_wakeup_ports_2_bits_uop_is_sfb;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_2_bits_uop_is_fence_0 = io_wakeup_ports_2_bits_uop_is_fence;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_2_bits_uop_is_fencei_0 = io_wakeup_ports_2_bits_uop_is_fencei;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_2_bits_uop_is_sfence_0 = io_wakeup_ports_2_bits_uop_is_sfence;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_2_bits_uop_is_amo_0 = io_wakeup_ports_2_bits_uop_is_amo;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_2_bits_uop_is_eret_0 = io_wakeup_ports_2_bits_uop_is_eret;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_2_bits_uop_is_sys_pc2epc;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_2_bits_uop_is_rocc_0 = io_wakeup_ports_2_bits_uop_is_rocc;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_2_bits_uop_is_mov_0 = io_wakeup_ports_2_bits_uop_is_mov;\t// @[issue-slot.scala:49:7]\n wire [4:0] io_wakeup_ports_2_bits_uop_ftq_idx_0 = io_wakeup_ports_2_bits_uop_ftq_idx;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_2_bits_uop_edge_inst_0 = io_wakeup_ports_2_bits_uop_edge_inst;\t// @[issue-slot.scala:49:7]\n wire [5:0] io_wakeup_ports_2_bits_uop_pc_lob_0 = io_wakeup_ports_2_bits_uop_pc_lob;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_2_bits_uop_taken_0 = io_wakeup_ports_2_bits_uop_taken;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_2_bits_uop_imm_rename_0 = io_wakeup_ports_2_bits_uop_imm_rename;\t// @[issue-slot.scala:49:7]\n wire [2:0] io_wakeup_ports_2_bits_uop_imm_sel_0 = io_wakeup_ports_2_bits_uop_imm_sel;\t// @[issue-slot.scala:49:7]\n wire [4:0] io_wakeup_ports_2_bits_uop_pimm_0 = io_wakeup_ports_2_bits_uop_pimm;\t// @[issue-slot.scala:49:7]\n wire [19:0] io_wakeup_ports_2_bits_uop_imm_packed_0 = io_wakeup_ports_2_bits_uop_imm_packed;\t// @[issue-slot.scala:49:7]\n wire [1:0] io_wakeup_ports_2_bits_uop_op1_sel_0 = io_wakeup_ports_2_bits_uop_op1_sel;\t// @[issue-slot.scala:49:7]\n wire [2:0] io_wakeup_ports_2_bits_uop_op2_sel_0 = io_wakeup_ports_2_bits_uop_op2_sel;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wen;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23;\t// @[issue-slot.scala:49:7]\n wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn;\t// @[issue-slot.scala:49:7]\n wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_toint;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fma;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_2_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_div;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_vec;\t// @[issue-slot.scala:49:7]\n wire [6:0] io_wakeup_ports_2_bits_uop_rob_idx_0 = io_wakeup_ports_2_bits_uop_rob_idx;\t// @[issue-slot.scala:49:7]\n wire [4:0] io_wakeup_ports_2_bits_uop_ldq_idx_0 = io_wakeup_ports_2_bits_uop_ldq_idx;\t// @[issue-slot.scala:49:7]\n wire [4:0] io_wakeup_ports_2_bits_uop_stq_idx_0 = io_wakeup_ports_2_bits_uop_stq_idx;\t// @[issue-slot.scala:49:7]\n wire [1:0] io_wakeup_ports_2_bits_uop_rxq_idx_0 = io_wakeup_ports_2_bits_uop_rxq_idx;\t// @[issue-slot.scala:49:7]\n wire [6:0] io_wakeup_ports_2_bits_uop_pdst_0 = io_wakeup_ports_2_bits_uop_pdst;\t// @[issue-slot.scala:49:7]\n wire [6:0] io_wakeup_ports_2_bits_uop_prs1_0 = io_wakeup_ports_2_bits_uop_prs1;\t// @[issue-slot.scala:49:7]\n wire [6:0] io_wakeup_ports_2_bits_uop_prs2_0 = io_wakeup_ports_2_bits_uop_prs2;\t// @[issue-slot.scala:49:7]\n wire [6:0] io_wakeup_ports_2_bits_uop_prs3_0 = io_wakeup_ports_2_bits_uop_prs3;\t// @[issue-slot.scala:49:7]\n wire [4:0] io_wakeup_ports_2_bits_uop_ppred_0 = io_wakeup_ports_2_bits_uop_ppred;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_2_bits_uop_prs1_busy_0 = io_wakeup_ports_2_bits_uop_prs1_busy;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_2_bits_uop_prs2_busy_0 = io_wakeup_ports_2_bits_uop_prs2_busy;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_2_bits_uop_prs3_busy_0 = io_wakeup_ports_2_bits_uop_prs3_busy;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_2_bits_uop_ppred_busy_0 = io_wakeup_ports_2_bits_uop_ppred_busy;\t// @[issue-slot.scala:49:7]\n wire [6:0] io_wakeup_ports_2_bits_uop_stale_pdst_0 = io_wakeup_ports_2_bits_uop_stale_pdst;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_2_bits_uop_exception_0 = io_wakeup_ports_2_bits_uop_exception;\t// @[issue-slot.scala:49:7]\n wire [63:0] io_wakeup_ports_2_bits_uop_exc_cause_0 = io_wakeup_ports_2_bits_uop_exc_cause;\t// @[issue-slot.scala:49:7]\n wire [4:0] io_wakeup_ports_2_bits_uop_mem_cmd_0 = io_wakeup_ports_2_bits_uop_mem_cmd;\t// @[issue-slot.scala:49:7]\n wire [1:0] io_wakeup_ports_2_bits_uop_mem_size_0 = io_wakeup_ports_2_bits_uop_mem_size;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_2_bits_uop_mem_signed_0 = io_wakeup_ports_2_bits_uop_mem_signed;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_2_bits_uop_uses_ldq_0 = io_wakeup_ports_2_bits_uop_uses_ldq;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_2_bits_uop_uses_stq_0 = io_wakeup_ports_2_bits_uop_uses_stq;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_2_bits_uop_is_unique_0 = io_wakeup_ports_2_bits_uop_is_unique;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_2_bits_uop_flush_on_commit_0 = io_wakeup_ports_2_bits_uop_flush_on_commit;\t// @[issue-slot.scala:49:7]\n wire [2:0] io_wakeup_ports_2_bits_uop_csr_cmd_0 = io_wakeup_ports_2_bits_uop_csr_cmd;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_2_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_2_bits_uop_ldst_is_rs1;\t// @[issue-slot.scala:49:7]\n wire [5:0] io_wakeup_ports_2_bits_uop_ldst_0 = io_wakeup_ports_2_bits_uop_ldst;\t// @[issue-slot.scala:49:7]\n wire [5:0] io_wakeup_ports_2_bits_uop_lrs1_0 = io_wakeup_ports_2_bits_uop_lrs1;\t// @[issue-slot.scala:49:7]\n wire [5:0] io_wakeup_ports_2_bits_uop_lrs2_0 = io_wakeup_ports_2_bits_uop_lrs2;\t// @[issue-slot.scala:49:7]\n wire [5:0] io_wakeup_ports_2_bits_uop_lrs3_0 = io_wakeup_ports_2_bits_uop_lrs3;\t// @[issue-slot.scala:49:7]\n wire [1:0] io_wakeup_ports_2_bits_uop_dst_rtype_0 = io_wakeup_ports_2_bits_uop_dst_rtype;\t// @[issue-slot.scala:49:7]\n wire [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype_0 = io_wakeup_ports_2_bits_uop_lrs1_rtype;\t// @[issue-slot.scala:49:7]\n wire [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype_0 = io_wakeup_ports_2_bits_uop_lrs2_rtype;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_2_bits_uop_frs3_en_0 = io_wakeup_ports_2_bits_uop_frs3_en;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_2_bits_uop_fcn_dw_0 = io_wakeup_ports_2_bits_uop_fcn_dw;\t// @[issue-slot.scala:49:7]\n wire [4:0] io_wakeup_ports_2_bits_uop_fcn_op_0 = io_wakeup_ports_2_bits_uop_fcn_op;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_2_bits_uop_fp_val_0 = io_wakeup_ports_2_bits_uop_fp_val;\t// @[issue-slot.scala:49:7]\n wire [2:0] io_wakeup_ports_2_bits_uop_fp_rm_0 = io_wakeup_ports_2_bits_uop_fp_rm;\t// @[issue-slot.scala:49:7]\n wire [1:0] io_wakeup_ports_2_bits_uop_fp_typ_0 = io_wakeup_ports_2_bits_uop_fp_typ;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_2_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_2_bits_uop_xcpt_pf_if;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_2_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ae_if;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_2_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ma_if;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_2_bits_uop_bp_debug_if_0 = io_wakeup_ports_2_bits_uop_bp_debug_if;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_2_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_2_bits_uop_bp_xcpt_if;\t// @[issue-slot.scala:49:7]\n wire [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc_0 = io_wakeup_ports_2_bits_uop_debug_fsrc;\t// @[issue-slot.scala:49:7]\n wire [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc_0 = io_wakeup_ports_2_bits_uop_debug_tsrc;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid;\t// @[issue-slot.scala:49:7]\n wire [31:0] io_wakeup_ports_3_bits_uop_inst_0 = io_wakeup_ports_3_bits_uop_inst;\t// @[issue-slot.scala:49:7]\n wire [31:0] io_wakeup_ports_3_bits_uop_debug_inst_0 = io_wakeup_ports_3_bits_uop_debug_inst;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_3_bits_uop_is_rvc_0 = io_wakeup_ports_3_bits_uop_is_rvc;\t// @[issue-slot.scala:49:7]\n wire [39:0] io_wakeup_ports_3_bits_uop_debug_pc_0 = io_wakeup_ports_3_bits_uop_debug_pc;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_3_bits_uop_iq_type_0_0 = io_wakeup_ports_3_bits_uop_iq_type_0;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_3_bits_uop_iq_type_1_0 = io_wakeup_ports_3_bits_uop_iq_type_1;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_3_bits_uop_iq_type_2_0 = io_wakeup_ports_3_bits_uop_iq_type_2;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_3_bits_uop_iq_type_3_0 = io_wakeup_ports_3_bits_uop_iq_type_3;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_3_bits_uop_fu_code_0_0 = io_wakeup_ports_3_bits_uop_fu_code_0;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_3_bits_uop_fu_code_1_0 = io_wakeup_ports_3_bits_uop_fu_code_1;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_3_bits_uop_fu_code_2_0 = io_wakeup_ports_3_bits_uop_fu_code_2;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_3_bits_uop_fu_code_3_0 = io_wakeup_ports_3_bits_uop_fu_code_3;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_3_bits_uop_fu_code_4_0 = io_wakeup_ports_3_bits_uop_fu_code_4;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_3_bits_uop_fu_code_5_0 = io_wakeup_ports_3_bits_uop_fu_code_5;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_3_bits_uop_fu_code_6_0 = io_wakeup_ports_3_bits_uop_fu_code_6;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_3_bits_uop_fu_code_7_0 = io_wakeup_ports_3_bits_uop_fu_code_7;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_3_bits_uop_fu_code_8_0 = io_wakeup_ports_3_bits_uop_fu_code_8;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_3_bits_uop_fu_code_9_0 = io_wakeup_ports_3_bits_uop_fu_code_9;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_3_bits_uop_iw_issued_0 = io_wakeup_ports_3_bits_uop_iw_issued;\t// @[issue-slot.scala:49:7]\n wire [2:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child;\t// @[issue-slot.scala:49:7]\n wire [2:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint;\t// @[issue-slot.scala:49:7]\n wire [2:0] io_wakeup_ports_3_bits_uop_dis_col_sel_0 = io_wakeup_ports_3_bits_uop_dis_col_sel;\t// @[issue-slot.scala:49:7]\n wire [15:0] io_wakeup_ports_3_bits_uop_br_mask_0 = io_wakeup_ports_3_bits_uop_br_mask;\t// @[issue-slot.scala:49:7]\n wire [3:0] io_wakeup_ports_3_bits_uop_br_tag_0 = io_wakeup_ports_3_bits_uop_br_tag;\t// @[issue-slot.scala:49:7]\n wire [3:0] io_wakeup_ports_3_bits_uop_br_type_0 = io_wakeup_ports_3_bits_uop_br_type;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_3_bits_uop_is_sfb_0 = io_wakeup_ports_3_bits_uop_is_sfb;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_3_bits_uop_is_fence_0 = io_wakeup_ports_3_bits_uop_is_fence;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_3_bits_uop_is_fencei_0 = io_wakeup_ports_3_bits_uop_is_fencei;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_3_bits_uop_is_sfence_0 = io_wakeup_ports_3_bits_uop_is_sfence;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_3_bits_uop_is_amo_0 = io_wakeup_ports_3_bits_uop_is_amo;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_3_bits_uop_is_eret_0 = io_wakeup_ports_3_bits_uop_is_eret;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_3_bits_uop_is_sys_pc2epc;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_3_bits_uop_is_rocc_0 = io_wakeup_ports_3_bits_uop_is_rocc;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_3_bits_uop_is_mov_0 = io_wakeup_ports_3_bits_uop_is_mov;\t// @[issue-slot.scala:49:7]\n wire [4:0] io_wakeup_ports_3_bits_uop_ftq_idx_0 = io_wakeup_ports_3_bits_uop_ftq_idx;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_3_bits_uop_edge_inst_0 = io_wakeup_ports_3_bits_uop_edge_inst;\t// @[issue-slot.scala:49:7]\n wire [5:0] io_wakeup_ports_3_bits_uop_pc_lob_0 = io_wakeup_ports_3_bits_uop_pc_lob;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_3_bits_uop_taken_0 = io_wakeup_ports_3_bits_uop_taken;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_3_bits_uop_imm_rename_0 = io_wakeup_ports_3_bits_uop_imm_rename;\t// @[issue-slot.scala:49:7]\n wire [2:0] io_wakeup_ports_3_bits_uop_imm_sel_0 = io_wakeup_ports_3_bits_uop_imm_sel;\t// @[issue-slot.scala:49:7]\n wire [4:0] io_wakeup_ports_3_bits_uop_pimm_0 = io_wakeup_ports_3_bits_uop_pimm;\t// @[issue-slot.scala:49:7]\n wire [19:0] io_wakeup_ports_3_bits_uop_imm_packed_0 = io_wakeup_ports_3_bits_uop_imm_packed;\t// @[issue-slot.scala:49:7]\n wire [1:0] io_wakeup_ports_3_bits_uop_op1_sel_0 = io_wakeup_ports_3_bits_uop_op1_sel;\t// @[issue-slot.scala:49:7]\n wire [2:0] io_wakeup_ports_3_bits_uop_op2_sel_0 = io_wakeup_ports_3_bits_uop_op2_sel;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wen;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23;\t// @[issue-slot.scala:49:7]\n wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn;\t// @[issue-slot.scala:49:7]\n wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_toint;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fma;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_3_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_div;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_vec;\t// @[issue-slot.scala:49:7]\n wire [6:0] io_wakeup_ports_3_bits_uop_rob_idx_0 = io_wakeup_ports_3_bits_uop_rob_idx;\t// @[issue-slot.scala:49:7]\n wire [4:0] io_wakeup_ports_3_bits_uop_ldq_idx_0 = io_wakeup_ports_3_bits_uop_ldq_idx;\t// @[issue-slot.scala:49:7]\n wire [4:0] io_wakeup_ports_3_bits_uop_stq_idx_0 = io_wakeup_ports_3_bits_uop_stq_idx;\t// @[issue-slot.scala:49:7]\n wire [1:0] io_wakeup_ports_3_bits_uop_rxq_idx_0 = io_wakeup_ports_3_bits_uop_rxq_idx;\t// @[issue-slot.scala:49:7]\n wire [6:0] io_wakeup_ports_3_bits_uop_pdst_0 = io_wakeup_ports_3_bits_uop_pdst;\t// @[issue-slot.scala:49:7]\n wire [6:0] io_wakeup_ports_3_bits_uop_prs1_0 = io_wakeup_ports_3_bits_uop_prs1;\t// @[issue-slot.scala:49:7]\n wire [6:0] io_wakeup_ports_3_bits_uop_prs2_0 = io_wakeup_ports_3_bits_uop_prs2;\t// @[issue-slot.scala:49:7]\n wire [6:0] io_wakeup_ports_3_bits_uop_prs3_0 = io_wakeup_ports_3_bits_uop_prs3;\t// @[issue-slot.scala:49:7]\n wire [4:0] io_wakeup_ports_3_bits_uop_ppred_0 = io_wakeup_ports_3_bits_uop_ppred;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_3_bits_uop_prs1_busy_0 = io_wakeup_ports_3_bits_uop_prs1_busy;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_3_bits_uop_prs2_busy_0 = io_wakeup_ports_3_bits_uop_prs2_busy;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_3_bits_uop_prs3_busy_0 = io_wakeup_ports_3_bits_uop_prs3_busy;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_3_bits_uop_ppred_busy_0 = io_wakeup_ports_3_bits_uop_ppred_busy;\t// @[issue-slot.scala:49:7]\n wire [6:0] io_wakeup_ports_3_bits_uop_stale_pdst_0 = io_wakeup_ports_3_bits_uop_stale_pdst;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_3_bits_uop_exception_0 = io_wakeup_ports_3_bits_uop_exception;\t// @[issue-slot.scala:49:7]\n wire [63:0] io_wakeup_ports_3_bits_uop_exc_cause_0 = io_wakeup_ports_3_bits_uop_exc_cause;\t// @[issue-slot.scala:49:7]\n wire [4:0] io_wakeup_ports_3_bits_uop_mem_cmd_0 = io_wakeup_ports_3_bits_uop_mem_cmd;\t// @[issue-slot.scala:49:7]\n wire [1:0] io_wakeup_ports_3_bits_uop_mem_size_0 = io_wakeup_ports_3_bits_uop_mem_size;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_3_bits_uop_mem_signed_0 = io_wakeup_ports_3_bits_uop_mem_signed;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_3_bits_uop_uses_ldq_0 = io_wakeup_ports_3_bits_uop_uses_ldq;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_3_bits_uop_uses_stq_0 = io_wakeup_ports_3_bits_uop_uses_stq;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_3_bits_uop_is_unique_0 = io_wakeup_ports_3_bits_uop_is_unique;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_3_bits_uop_flush_on_commit_0 = io_wakeup_ports_3_bits_uop_flush_on_commit;\t// @[issue-slot.scala:49:7]\n wire [2:0] io_wakeup_ports_3_bits_uop_csr_cmd_0 = io_wakeup_ports_3_bits_uop_csr_cmd;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_3_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_3_bits_uop_ldst_is_rs1;\t// @[issue-slot.scala:49:7]\n wire [5:0] io_wakeup_ports_3_bits_uop_ldst_0 = io_wakeup_ports_3_bits_uop_ldst;\t// @[issue-slot.scala:49:7]\n wire [5:0] io_wakeup_ports_3_bits_uop_lrs1_0 = io_wakeup_ports_3_bits_uop_lrs1;\t// @[issue-slot.scala:49:7]\n wire [5:0] io_wakeup_ports_3_bits_uop_lrs2_0 = io_wakeup_ports_3_bits_uop_lrs2;\t// @[issue-slot.scala:49:7]\n wire [5:0] io_wakeup_ports_3_bits_uop_lrs3_0 = io_wakeup_ports_3_bits_uop_lrs3;\t// @[issue-slot.scala:49:7]\n wire [1:0] io_wakeup_ports_3_bits_uop_dst_rtype_0 = io_wakeup_ports_3_bits_uop_dst_rtype;\t// @[issue-slot.scala:49:7]\n wire [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype_0 = io_wakeup_ports_3_bits_uop_lrs1_rtype;\t// @[issue-slot.scala:49:7]\n wire [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype_0 = io_wakeup_ports_3_bits_uop_lrs2_rtype;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_3_bits_uop_frs3_en_0 = io_wakeup_ports_3_bits_uop_frs3_en;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_3_bits_uop_fcn_dw_0 = io_wakeup_ports_3_bits_uop_fcn_dw;\t// @[issue-slot.scala:49:7]\n wire [4:0] io_wakeup_ports_3_bits_uop_fcn_op_0 = io_wakeup_ports_3_bits_uop_fcn_op;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_3_bits_uop_fp_val_0 = io_wakeup_ports_3_bits_uop_fp_val;\t// @[issue-slot.scala:49:7]\n wire [2:0] io_wakeup_ports_3_bits_uop_fp_rm_0 = io_wakeup_ports_3_bits_uop_fp_rm;\t// @[issue-slot.scala:49:7]\n wire [1:0] io_wakeup_ports_3_bits_uop_fp_typ_0 = io_wakeup_ports_3_bits_uop_fp_typ;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_3_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_3_bits_uop_xcpt_pf_if;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_3_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ae_if;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_3_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ma_if;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_3_bits_uop_bp_debug_if_0 = io_wakeup_ports_3_bits_uop_bp_debug_if;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_3_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_3_bits_uop_bp_xcpt_if;\t// @[issue-slot.scala:49:7]\n wire [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc_0 = io_wakeup_ports_3_bits_uop_debug_fsrc;\t// @[issue-slot.scala:49:7]\n wire [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc_0 = io_wakeup_ports_3_bits_uop_debug_tsrc;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_4_valid_0 = io_wakeup_ports_4_valid;\t// @[issue-slot.scala:49:7]\n wire [31:0] io_wakeup_ports_4_bits_uop_inst_0 = io_wakeup_ports_4_bits_uop_inst;\t// @[issue-slot.scala:49:7]\n wire [31:0] io_wakeup_ports_4_bits_uop_debug_inst_0 = io_wakeup_ports_4_bits_uop_debug_inst;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_4_bits_uop_is_rvc_0 = io_wakeup_ports_4_bits_uop_is_rvc;\t// @[issue-slot.scala:49:7]\n wire [39:0] io_wakeup_ports_4_bits_uop_debug_pc_0 = io_wakeup_ports_4_bits_uop_debug_pc;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_4_bits_uop_iq_type_0_0 = io_wakeup_ports_4_bits_uop_iq_type_0;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_4_bits_uop_iq_type_1_0 = io_wakeup_ports_4_bits_uop_iq_type_1;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_4_bits_uop_iq_type_2_0 = io_wakeup_ports_4_bits_uop_iq_type_2;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_4_bits_uop_iq_type_3_0 = io_wakeup_ports_4_bits_uop_iq_type_3;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_4_bits_uop_fu_code_0_0 = io_wakeup_ports_4_bits_uop_fu_code_0;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_4_bits_uop_fu_code_1_0 = io_wakeup_ports_4_bits_uop_fu_code_1;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_4_bits_uop_fu_code_2_0 = io_wakeup_ports_4_bits_uop_fu_code_2;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_4_bits_uop_fu_code_3_0 = io_wakeup_ports_4_bits_uop_fu_code_3;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_4_bits_uop_fu_code_4_0 = io_wakeup_ports_4_bits_uop_fu_code_4;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_4_bits_uop_fu_code_5_0 = io_wakeup_ports_4_bits_uop_fu_code_5;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_4_bits_uop_fu_code_6_0 = io_wakeup_ports_4_bits_uop_fu_code_6;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_4_bits_uop_fu_code_7_0 = io_wakeup_ports_4_bits_uop_fu_code_7;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_4_bits_uop_fu_code_8_0 = io_wakeup_ports_4_bits_uop_fu_code_8;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_4_bits_uop_fu_code_9_0 = io_wakeup_ports_4_bits_uop_fu_code_9;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_4_bits_uop_iw_issued_0 = io_wakeup_ports_4_bits_uop_iw_issued;\t// @[issue-slot.scala:49:7]\n wire [2:0] io_wakeup_ports_4_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_4_bits_uop_iw_p1_speculative_child;\t// @[issue-slot.scala:49:7]\n wire [2:0] io_wakeup_ports_4_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_4_bits_uop_iw_p2_speculative_child;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint;\t// @[issue-slot.scala:49:7]\n wire [2:0] io_wakeup_ports_4_bits_uop_dis_col_sel_0 = io_wakeup_ports_4_bits_uop_dis_col_sel;\t// @[issue-slot.scala:49:7]\n wire [15:0] io_wakeup_ports_4_bits_uop_br_mask_0 = io_wakeup_ports_4_bits_uop_br_mask;\t// @[issue-slot.scala:49:7]\n wire [3:0] io_wakeup_ports_4_bits_uop_br_tag_0 = io_wakeup_ports_4_bits_uop_br_tag;\t// @[issue-slot.scala:49:7]\n wire [3:0] io_wakeup_ports_4_bits_uop_br_type_0 = io_wakeup_ports_4_bits_uop_br_type;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_4_bits_uop_is_sfb_0 = io_wakeup_ports_4_bits_uop_is_sfb;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_4_bits_uop_is_fence_0 = io_wakeup_ports_4_bits_uop_is_fence;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_4_bits_uop_is_fencei_0 = io_wakeup_ports_4_bits_uop_is_fencei;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_4_bits_uop_is_sfence_0 = io_wakeup_ports_4_bits_uop_is_sfence;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_4_bits_uop_is_amo_0 = io_wakeup_ports_4_bits_uop_is_amo;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_4_bits_uop_is_eret_0 = io_wakeup_ports_4_bits_uop_is_eret;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_4_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_4_bits_uop_is_sys_pc2epc;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_4_bits_uop_is_rocc_0 = io_wakeup_ports_4_bits_uop_is_rocc;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_4_bits_uop_is_mov_0 = io_wakeup_ports_4_bits_uop_is_mov;\t// @[issue-slot.scala:49:7]\n wire [4:0] io_wakeup_ports_4_bits_uop_ftq_idx_0 = io_wakeup_ports_4_bits_uop_ftq_idx;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_4_bits_uop_edge_inst_0 = io_wakeup_ports_4_bits_uop_edge_inst;\t// @[issue-slot.scala:49:7]\n wire [5:0] io_wakeup_ports_4_bits_uop_pc_lob_0 = io_wakeup_ports_4_bits_uop_pc_lob;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_4_bits_uop_taken_0 = io_wakeup_ports_4_bits_uop_taken;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_4_bits_uop_imm_rename_0 = io_wakeup_ports_4_bits_uop_imm_rename;\t// @[issue-slot.scala:49:7]\n wire [2:0] io_wakeup_ports_4_bits_uop_imm_sel_0 = io_wakeup_ports_4_bits_uop_imm_sel;\t// @[issue-slot.scala:49:7]\n wire [4:0] io_wakeup_ports_4_bits_uop_pimm_0 = io_wakeup_ports_4_bits_uop_pimm;\t// @[issue-slot.scala:49:7]\n wire [19:0] io_wakeup_ports_4_bits_uop_imm_packed_0 = io_wakeup_ports_4_bits_uop_imm_packed;\t// @[issue-slot.scala:49:7]\n wire [1:0] io_wakeup_ports_4_bits_uop_op1_sel_0 = io_wakeup_ports_4_bits_uop_op1_sel;\t// @[issue-slot.scala:49:7]\n wire [2:0] io_wakeup_ports_4_bits_uop_op2_sel_0 = io_wakeup_ports_4_bits_uop_op2_sel;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_4_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ldst;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_4_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_wen;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren1;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren2;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren3;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_4_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap12;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_4_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap23;\t// @[issue-slot.scala:49:7]\n wire [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn;\t// @[issue-slot.scala:49:7]\n wire [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_4_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fromint;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_4_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_toint;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_4_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fma;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_4_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_div;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_4_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_wflags;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_4_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_vec;\t// @[issue-slot.scala:49:7]\n wire [6:0] io_wakeup_ports_4_bits_uop_rob_idx_0 = io_wakeup_ports_4_bits_uop_rob_idx;\t// @[issue-slot.scala:49:7]\n wire [4:0] io_wakeup_ports_4_bits_uop_ldq_idx_0 = io_wakeup_ports_4_bits_uop_ldq_idx;\t// @[issue-slot.scala:49:7]\n wire [4:0] io_wakeup_ports_4_bits_uop_stq_idx_0 = io_wakeup_ports_4_bits_uop_stq_idx;\t// @[issue-slot.scala:49:7]\n wire [1:0] io_wakeup_ports_4_bits_uop_rxq_idx_0 = io_wakeup_ports_4_bits_uop_rxq_idx;\t// @[issue-slot.scala:49:7]\n wire [6:0] io_wakeup_ports_4_bits_uop_pdst_0 = io_wakeup_ports_4_bits_uop_pdst;\t// @[issue-slot.scala:49:7]\n wire [6:0] io_wakeup_ports_4_bits_uop_prs1_0 = io_wakeup_ports_4_bits_uop_prs1;\t// @[issue-slot.scala:49:7]\n wire [6:0] io_wakeup_ports_4_bits_uop_prs2_0 = io_wakeup_ports_4_bits_uop_prs2;\t// @[issue-slot.scala:49:7]\n wire [6:0] io_wakeup_ports_4_bits_uop_prs3_0 = io_wakeup_ports_4_bits_uop_prs3;\t// @[issue-slot.scala:49:7]\n wire [4:0] io_wakeup_ports_4_bits_uop_ppred_0 = io_wakeup_ports_4_bits_uop_ppred;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_4_bits_uop_prs1_busy_0 = io_wakeup_ports_4_bits_uop_prs1_busy;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_4_bits_uop_prs2_busy_0 = io_wakeup_ports_4_bits_uop_prs2_busy;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_4_bits_uop_prs3_busy_0 = io_wakeup_ports_4_bits_uop_prs3_busy;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_4_bits_uop_ppred_busy_0 = io_wakeup_ports_4_bits_uop_ppred_busy;\t// @[issue-slot.scala:49:7]\n wire [6:0] io_wakeup_ports_4_bits_uop_stale_pdst_0 = io_wakeup_ports_4_bits_uop_stale_pdst;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_4_bits_uop_exception_0 = io_wakeup_ports_4_bits_uop_exception;\t// @[issue-slot.scala:49:7]\n wire [63:0] io_wakeup_ports_4_bits_uop_exc_cause_0 = io_wakeup_ports_4_bits_uop_exc_cause;\t// @[issue-slot.scala:49:7]\n wire [4:0] io_wakeup_ports_4_bits_uop_mem_cmd_0 = io_wakeup_ports_4_bits_uop_mem_cmd;\t// @[issue-slot.scala:49:7]\n wire [1:0] io_wakeup_ports_4_bits_uop_mem_size_0 = io_wakeup_ports_4_bits_uop_mem_size;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_4_bits_uop_mem_signed_0 = io_wakeup_ports_4_bits_uop_mem_signed;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_4_bits_uop_uses_ldq_0 = io_wakeup_ports_4_bits_uop_uses_ldq;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_4_bits_uop_uses_stq_0 = io_wakeup_ports_4_bits_uop_uses_stq;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_4_bits_uop_is_unique_0 = io_wakeup_ports_4_bits_uop_is_unique;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_4_bits_uop_flush_on_commit_0 = io_wakeup_ports_4_bits_uop_flush_on_commit;\t// @[issue-slot.scala:49:7]\n wire [2:0] io_wakeup_ports_4_bits_uop_csr_cmd_0 = io_wakeup_ports_4_bits_uop_csr_cmd;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_4_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_4_bits_uop_ldst_is_rs1;\t// @[issue-slot.scala:49:7]\n wire [5:0] io_wakeup_ports_4_bits_uop_ldst_0 = io_wakeup_ports_4_bits_uop_ldst;\t// @[issue-slot.scala:49:7]\n wire [5:0] io_wakeup_ports_4_bits_uop_lrs1_0 = io_wakeup_ports_4_bits_uop_lrs1;\t// @[issue-slot.scala:49:7]\n wire [5:0] io_wakeup_ports_4_bits_uop_lrs2_0 = io_wakeup_ports_4_bits_uop_lrs2;\t// @[issue-slot.scala:49:7]\n wire [5:0] io_wakeup_ports_4_bits_uop_lrs3_0 = io_wakeup_ports_4_bits_uop_lrs3;\t// @[issue-slot.scala:49:7]\n wire [1:0] io_wakeup_ports_4_bits_uop_dst_rtype_0 = io_wakeup_ports_4_bits_uop_dst_rtype;\t// @[issue-slot.scala:49:7]\n wire [1:0] io_wakeup_ports_4_bits_uop_lrs1_rtype_0 = io_wakeup_ports_4_bits_uop_lrs1_rtype;\t// @[issue-slot.scala:49:7]\n wire [1:0] io_wakeup_ports_4_bits_uop_lrs2_rtype_0 = io_wakeup_ports_4_bits_uop_lrs2_rtype;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_4_bits_uop_frs3_en_0 = io_wakeup_ports_4_bits_uop_frs3_en;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_4_bits_uop_fcn_dw_0 = io_wakeup_ports_4_bits_uop_fcn_dw;\t// @[issue-slot.scala:49:7]\n wire [4:0] io_wakeup_ports_4_bits_uop_fcn_op_0 = io_wakeup_ports_4_bits_uop_fcn_op;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_4_bits_uop_fp_val_0 = io_wakeup_ports_4_bits_uop_fp_val;\t// @[issue-slot.scala:49:7]\n wire [2:0] io_wakeup_ports_4_bits_uop_fp_rm_0 = io_wakeup_ports_4_bits_uop_fp_rm;\t// @[issue-slot.scala:49:7]\n wire [1:0] io_wakeup_ports_4_bits_uop_fp_typ_0 = io_wakeup_ports_4_bits_uop_fp_typ;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_4_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_4_bits_uop_xcpt_pf_if;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_4_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_4_bits_uop_xcpt_ae_if;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_4_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_4_bits_uop_xcpt_ma_if;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_4_bits_uop_bp_debug_if_0 = io_wakeup_ports_4_bits_uop_bp_debug_if;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_4_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_4_bits_uop_bp_xcpt_if;\t// @[issue-slot.scala:49:7]\n wire [2:0] io_wakeup_ports_4_bits_uop_debug_fsrc_0 = io_wakeup_ports_4_bits_uop_debug_fsrc;\t// @[issue-slot.scala:49:7]\n wire [2:0] io_wakeup_ports_4_bits_uop_debug_tsrc_0 = io_wakeup_ports_4_bits_uop_debug_tsrc;\t// @[issue-slot.scala:49:7]\n wire io_pred_wakeup_port_valid_0 = io_pred_wakeup_port_valid;\t// @[issue-slot.scala:49:7]\n wire [4:0] io_pred_wakeup_port_bits_0 = io_pred_wakeup_port_bits;\t// @[issue-slot.scala:49:7]\n wire [2:0] io_child_rebusys_0 = io_child_rebusys;\t// @[issue-slot.scala:49:7]\n wire io_iss_uop_iw_issued_partial_agen = 1'h0;\t// @[issue-slot.scala:49:7]\n wire io_iss_uop_iw_issued_partial_dgen = 1'h0;\t// @[issue-slot.scala:49:7]\n wire io_in_uop_bits_iw_issued_partial_agen = 1'h0;\t// @[issue-slot.scala:49:7]\n wire io_in_uop_bits_iw_issued_partial_dgen = 1'h0;\t// @[issue-slot.scala:49:7]\n wire io_out_uop_iw_issued_partial_agen = 1'h0;\t// @[issue-slot.scala:49:7]\n wire io_out_uop_iw_issued_partial_dgen = 1'h0;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_1_bits_bypassable = 1'h0;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_1_bits_rebusy = 1'h0;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_2_bits_rebusy = 1'h0;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_3_bits_rebusy = 1'h0;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_4_bits_uop_iw_issued_partial_agen = 1'h0;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_4_bits_uop_iw_issued_partial_dgen = 1'h0;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_4_bits_rebusy = 1'h0;\t// @[issue-slot.scala:49:7]\n wire next_uop_out_iw_issued_partial_agen = 1'h0;\t// @[util.scala:104:23]\n wire next_uop_out_iw_issued_partial_dgen = 1'h0;\t// @[util.scala:104:23]\n wire next_uop_iw_issued_partial_agen = 1'h0;\t// @[issue-slot.scala:59:28]\n wire next_uop_iw_issued_partial_dgen = 1'h0;\t// @[issue-slot.scala:59:28]\n wire prs1_rebusys_1 = 1'h0;\t// @[issue-slot.scala:102:91]\n wire prs1_rebusys_2 = 1'h0;\t// @[issue-slot.scala:102:91]\n wire prs1_rebusys_3 = 1'h0;\t// @[issue-slot.scala:102:91]\n wire prs1_rebusys_4 = 1'h0;\t// @[issue-slot.scala:102:91]\n wire prs2_rebusys_1 = 1'h0;\t// @[issue-slot.scala:103:91]\n wire prs2_rebusys_2 = 1'h0;\t// @[issue-slot.scala:103:91]\n wire prs2_rebusys_3 = 1'h0;\t// @[issue-slot.scala:103:91]\n wire prs2_rebusys_4 = 1'h0;\t// @[issue-slot.scala:103:91]\n wire _next_uop_iw_p1_bypass_hint_T_1 = 1'h0;\t// @[Mux.scala:30:73]\n wire _next_uop_iw_p2_bypass_hint_T_1 = 1'h0;\t// @[Mux.scala:30:73]\n wire _next_uop_iw_p3_bypass_hint_T_1 = 1'h0;\t// @[Mux.scala:30:73]\n wire _iss_ready_T_6 = 1'h0;\t// @[issue-slot.scala:136:131]\n wire agen_ready = 1'h0;\t// @[issue-slot.scala:137:114]\n wire dgen_ready = 1'h0;\t// @[issue-slot.scala:138:114]\n wire [2:0] io_wakeup_ports_1_bits_speculative_mask = 3'h0;\t// @[issue-slot.scala:49:7]\n wire [2:0] _next_uop_iw_p1_speculative_child_T_1 = 3'h0;\t// @[Mux.scala:30:73]\n wire [2:0] _next_uop_iw_p2_speculative_child_T_1 = 3'h0;\t// @[Mux.scala:30:73]\n wire io_wakeup_ports_2_bits_bypassable = 1'h1;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_3_bits_bypassable = 1'h1;\t// @[issue-slot.scala:49:7]\n wire io_wakeup_ports_4_bits_bypassable = 1'h1;\t// @[issue-slot.scala:49:7]\n wire _iss_ready_T_7 = 1'h1;\t// @[issue-slot.scala:136:110]\n wire [2:0] io_wakeup_ports_2_bits_speculative_mask = 3'h1;\t// @[issue-slot.scala:49:7]\n wire [2:0] io_wakeup_ports_3_bits_speculative_mask = 3'h2;\t// @[issue-slot.scala:49:7]\n wire [2:0] io_wakeup_ports_4_bits_speculative_mask = 3'h4;\t// @[issue-slot.scala:49:7]\n wire _io_will_be_valid_T_1;\t// @[issue-slot.scala:65:34]\n wire _io_request_T_4;\t// @[issue-slot.scala:140:51]\n wire [31:0] next_uop_inst;\t// @[issue-slot.scala:59:28]\n wire [31:0] next_uop_debug_inst;\t// @[issue-slot.scala:59:28]\n wire next_uop_is_rvc;\t// @[issue-slot.scala:59:28]\n wire [39:0] next_uop_debug_pc;\t// @[issue-slot.scala:59:28]\n wire next_uop_iq_type_0;\t// @[issue-slot.scala:59:28]\n wire next_uop_iq_type_1;\t// @[issue-slot.scala:59:28]\n wire next_uop_iq_type_2;\t// @[issue-slot.scala:59:28]\n wire next_uop_iq_type_3;\t// @[issue-slot.scala:59:28]\n wire next_uop_fu_code_0;\t// @[issue-slot.scala:59:28]\n wire next_uop_fu_code_1;\t// @[issue-slot.scala:59:28]\n wire next_uop_fu_code_2;\t// @[issue-slot.scala:59:28]\n wire next_uop_fu_code_3;\t// @[issue-slot.scala:59:28]\n wire next_uop_fu_code_4;\t// @[issue-slot.scala:59:28]\n wire next_uop_fu_code_5;\t// @[issue-slot.scala:59:28]\n wire next_uop_fu_code_6;\t// @[issue-slot.scala:59:28]\n wire next_uop_fu_code_7;\t// @[issue-slot.scala:59:28]\n wire next_uop_fu_code_8;\t// @[issue-slot.scala:59:28]\n wire next_uop_fu_code_9;\t// @[issue-slot.scala:59:28]\n wire next_uop_iw_issued;\t// @[issue-slot.scala:59:28]\n wire [2:0] next_uop_iw_p1_speculative_child;\t// @[issue-slot.scala:59:28]\n wire [2:0] next_uop_iw_p2_speculative_child;\t// @[issue-slot.scala:59:28]\n wire next_uop_iw_p1_bypass_hint;\t// @[issue-slot.scala:59:28]\n wire next_uop_iw_p2_bypass_hint;\t// @[issue-slot.scala:59:28]\n wire next_uop_iw_p3_bypass_hint;\t// @[issue-slot.scala:59:28]\n wire [2:0] next_uop_dis_col_sel;\t// @[issue-slot.scala:59:28]\n wire [15:0] next_uop_br_mask;\t// @[issue-slot.scala:59:28]\n wire [3:0] next_uop_br_tag;\t// @[issue-slot.scala:59:28]\n wire [3:0] next_uop_br_type;\t// @[issue-slot.scala:59:28]\n wire next_uop_is_sfb;\t// @[issue-slot.scala:59:28]\n wire next_uop_is_fence;\t// @[issue-slot.scala:59:28]\n wire next_uop_is_fencei;\t// @[issue-slot.scala:59:28]\n wire next_uop_is_sfence;\t// @[issue-slot.scala:59:28]\n wire next_uop_is_amo;\t// @[issue-slot.scala:59:28]\n wire next_uop_is_eret;\t// @[issue-slot.scala:59:28]\n wire next_uop_is_sys_pc2epc;\t// @[issue-slot.scala:59:28]\n wire next_uop_is_rocc;\t// @[issue-slot.scala:59:28]\n wire next_uop_is_mov;\t// @[issue-slot.scala:59:28]\n wire [4:0] next_uop_ftq_idx;\t// @[issue-slot.scala:59:28]\n wire next_uop_edge_inst;\t// @[issue-slot.scala:59:28]\n wire [5:0] next_uop_pc_lob;\t// @[issue-slot.scala:59:28]\n wire next_uop_taken;\t// @[issue-slot.scala:59:28]\n wire next_uop_imm_rename;\t// @[issue-slot.scala:59:28]\n wire [2:0] next_uop_imm_sel;\t// @[issue-slot.scala:59:28]\n wire [4:0] next_uop_pimm;\t// @[issue-slot.scala:59:28]\n wire [19:0] next_uop_imm_packed;\t// @[issue-slot.scala:59:28]\n wire [1:0] next_uop_op1_sel;\t// @[issue-slot.scala:59:28]\n wire [2:0] next_uop_op2_sel;\t// @[issue-slot.scala:59:28]\n wire next_uop_fp_ctrl_ldst;\t// @[issue-slot.scala:59:28]\n wire next_uop_fp_ctrl_wen;\t// @[issue-slot.scala:59:28]\n wire next_uop_fp_ctrl_ren1;\t// @[issue-slot.scala:59:28]\n wire next_uop_fp_ctrl_ren2;\t// @[issue-slot.scala:59:28]\n wire next_uop_fp_ctrl_ren3;\t// @[issue-slot.scala:59:28]\n wire next_uop_fp_ctrl_swap12;\t// @[issue-slot.scala:59:28]\n wire next_uop_fp_ctrl_swap23;\t// @[issue-slot.scala:59:28]\n wire [1:0] next_uop_fp_ctrl_typeTagIn;\t// @[issue-slot.scala:59:28]\n wire [1:0] next_uop_fp_ctrl_typeTagOut;\t// @[issue-slot.scala:59:28]\n wire next_uop_fp_ctrl_fromint;\t// @[issue-slot.scala:59:28]\n wire next_uop_fp_ctrl_toint;\t// @[issue-slot.scala:59:28]\n wire next_uop_fp_ctrl_fastpipe;\t// @[issue-slot.scala:59:28]\n wire next_uop_fp_ctrl_fma;\t// @[issue-slot.scala:59:28]\n wire next_uop_fp_ctrl_div;\t// @[issue-slot.scala:59:28]\n wire next_uop_fp_ctrl_sqrt;\t// @[issue-slot.scala:59:28]\n wire next_uop_fp_ctrl_wflags;\t// @[issue-slot.scala:59:28]\n wire next_uop_fp_ctrl_vec;\t// @[issue-slot.scala:59:28]\n wire [6:0] next_uop_rob_idx;\t// @[issue-slot.scala:59:28]\n wire [4:0] next_uop_ldq_idx;\t// @[issue-slot.scala:59:28]\n wire [4:0] next_uop_stq_idx;\t// @[issue-slot.scala:59:28]\n wire [1:0] next_uop_rxq_idx;\t// @[issue-slot.scala:59:28]\n wire [6:0] next_uop_pdst;\t// @[issue-slot.scala:59:28]\n wire [6:0] next_uop_prs1;\t// @[issue-slot.scala:59:28]\n wire [6:0] next_uop_prs2;\t// @[issue-slot.scala:59:28]\n wire [6:0] next_uop_prs3;\t// @[issue-slot.scala:59:28]\n wire [4:0] next_uop_ppred;\t// @[issue-slot.scala:59:28]\n wire next_uop_prs1_busy;\t// @[issue-slot.scala:59:28]\n wire next_uop_prs2_busy;\t// @[issue-slot.scala:59:28]\n wire next_uop_prs3_busy;\t// @[issue-slot.scala:59:28]\n wire next_uop_ppred_busy;\t// @[issue-slot.scala:59:28]\n wire [6:0] next_uop_stale_pdst;\t// @[issue-slot.scala:59:28]\n wire next_uop_exception;\t// @[issue-slot.scala:59:28]\n wire [63:0] next_uop_exc_cause;\t// @[issue-slot.scala:59:28]\n wire [4:0] next_uop_mem_cmd;\t// @[issue-slot.scala:59:28]\n wire [1:0] next_uop_mem_size;\t// @[issue-slot.scala:59:28]\n wire next_uop_mem_signed;\t// @[issue-slot.scala:59:28]\n wire next_uop_uses_ldq;\t// @[issue-slot.scala:59:28]\n wire next_uop_uses_stq;\t// @[issue-slot.scala:59:28]\n wire next_uop_is_unique;\t// @[issue-slot.scala:59:28]\n wire next_uop_flush_on_commit;\t// @[issue-slot.scala:59:28]\n wire [2:0] next_uop_csr_cmd;\t// @[issue-slot.scala:59:28]\n wire next_uop_ldst_is_rs1;\t// @[issue-slot.scala:59:28]\n wire [5:0] next_uop_ldst;\t// @[issue-slot.scala:59:28]\n wire [5:0] next_uop_lrs1;\t// @[issue-slot.scala:59:28]\n wire [5:0] next_uop_lrs2;\t// @[issue-slot.scala:59:28]\n wire [5:0] next_uop_lrs3;\t// @[issue-slot.scala:59:28]\n wire [1:0] next_uop_dst_rtype;\t// @[issue-slot.scala:59:28]\n wire [1:0] next_uop_lrs1_rtype;\t// @[issue-slot.scala:59:28]\n wire [1:0] next_uop_lrs2_rtype;\t// @[issue-slot.scala:59:28]\n wire next_uop_frs3_en;\t// @[issue-slot.scala:59:28]\n wire next_uop_fcn_dw;\t// @[issue-slot.scala:59:28]\n wire [4:0] next_uop_fcn_op;\t// @[issue-slot.scala:59:28]\n wire next_uop_fp_val;\t// @[issue-slot.scala:59:28]\n wire [2:0] next_uop_fp_rm;\t// @[issue-slot.scala:59:28]\n wire [1:0] next_uop_fp_typ;\t// @[issue-slot.scala:59:28]\n wire next_uop_xcpt_pf_if;\t// @[issue-slot.scala:59:28]\n wire next_uop_xcpt_ae_if;\t// @[issue-slot.scala:59:28]\n wire next_uop_xcpt_ma_if;\t// @[issue-slot.scala:59:28]\n wire next_uop_bp_debug_if;\t// @[issue-slot.scala:59:28]\n wire next_uop_bp_xcpt_if;\t// @[issue-slot.scala:59:28]\n wire [2:0] next_uop_debug_fsrc;\t// @[issue-slot.scala:59:28]\n wire [2:0] next_uop_debug_tsrc;\t// @[issue-slot.scala:59:28]\n wire io_iss_uop_iq_type_0_0;\t// @[issue-slot.scala:49:7]\n wire io_iss_uop_iq_type_1_0;\t// @[issue-slot.scala:49:7]\n wire io_iss_uop_iq_type_2_0;\t// @[issue-slot.scala:49:7]\n wire io_iss_uop_iq_type_3_0;\t// @[issue-slot.scala:49:7]\n wire io_iss_uop_fu_code_0_0;\t// @[issue-slot.scala:49:7]\n wire io_iss_uop_fu_code_1_0;\t// @[issue-slot.scala:49:7]\n wire io_iss_uop_fu_code_2_0;\t// @[issue-slot.scala:49:7]\n wire io_iss_uop_fu_code_3_0;\t// @[issue-slot.scala:49:7]\n wire io_iss_uop_fu_code_4_0;\t// @[issue-slot.scala:49:7]\n wire io_iss_uop_fu_code_5_0;\t// @[issue-slot.scala:49:7]\n wire io_iss_uop_fu_code_6_0;\t// @[issue-slot.scala:49:7]\n wire io_iss_uop_fu_code_7_0;\t// @[issue-slot.scala:49:7]\n wire io_iss_uop_fu_code_8_0;\t// @[issue-slot.scala:49:7]\n wire io_iss_uop_fu_code_9_0;\t// @[issue-slot.scala:49:7]\n wire io_iss_uop_fp_ctrl_ldst_0;\t// @[issue-slot.scala:49:7]\n wire io_iss_uop_fp_ctrl_wen_0;\t// @[issue-slot.scala:49:7]\n wire io_iss_uop_fp_ctrl_ren1_0;\t// @[issue-slot.scala:49:7]\n wire io_iss_uop_fp_ctrl_ren2_0;\t// @[issue-slot.scala:49:7]\n wire io_iss_uop_fp_ctrl_ren3_0;\t// @[issue-slot.scala:49:7]\n wire io_iss_uop_fp_ctrl_swap12_0;\t// @[issue-slot.scala:49:7]\n wire io_iss_uop_fp_ctrl_swap23_0;\t// @[issue-slot.scala:49:7]\n wire [1:0] io_iss_uop_fp_ctrl_typeTagIn_0;\t// @[issue-slot.scala:49:7]\n wire [1:0] io_iss_uop_fp_ctrl_typeTagOut_0;\t// @[issue-slot.scala:49:7]\n wire io_iss_uop_fp_ctrl_fromint_0;\t// @[issue-slot.scala:49:7]\n wire io_iss_uop_fp_ctrl_toint_0;\t// @[issue-slot.scala:49:7]\n wire io_iss_uop_fp_ctrl_fastpipe_0;\t// @[issue-slot.scala:49:7]\n wire io_iss_uop_fp_ctrl_fma_0;\t// @[issue-slot.scala:49:7]\n wire io_iss_uop_fp_ctrl_div_0;\t// @[issue-slot.scala:49:7]\n wire io_iss_uop_fp_ctrl_sqrt_0;\t// @[issue-slot.scala:49:7]\n wire io_iss_uop_fp_ctrl_wflags_0;\t// @[issue-slot.scala:49:7]\n wire io_iss_uop_fp_ctrl_vec_0;\t// @[issue-slot.scala:49:7]\n wire [31:0] io_iss_uop_inst_0;\t// @[issue-slot.scala:49:7]\n wire [31:0] io_iss_uop_debug_inst_0;\t// @[issue-slot.scala:49:7]\n wire io_iss_uop_is_rvc_0;\t// @[issue-slot.scala:49:7]\n wire [39:0] io_iss_uop_debug_pc_0;\t// @[issue-slot.scala:49:7]\n wire io_iss_uop_iw_issued_0;\t// @[issue-slot.scala:49:7]\n wire [2:0] io_iss_uop_iw_p1_speculative_child_0;\t// @[issue-slot.scala:49:7]\n wire [2:0] io_iss_uop_iw_p2_speculative_child_0;\t// @[issue-slot.scala:49:7]\n wire io_iss_uop_iw_p1_bypass_hint_0;\t// @[issue-slot.scala:49:7]\n wire io_iss_uop_iw_p2_bypass_hint_0;\t// @[issue-slot.scala:49:7]\n wire io_iss_uop_iw_p3_bypass_hint_0;\t// @[issue-slot.scala:49:7]\n wire [2:0] io_iss_uop_dis_col_sel_0;\t// @[issue-slot.scala:49:7]\n wire [15:0] io_iss_uop_br_mask_0;\t// @[issue-slot.scala:49:7]\n wire [3:0] io_iss_uop_br_tag_0;\t// @[issue-slot.scala:49:7]\n wire [3:0] io_iss_uop_br_type_0;\t// @[issue-slot.scala:49:7]\n wire io_iss_uop_is_sfb_0;\t// @[issue-slot.scala:49:7]\n wire io_iss_uop_is_fence_0;\t// @[issue-slot.scala:49:7]\n wire io_iss_uop_is_fencei_0;\t// @[issue-slot.scala:49:7]\n wire io_iss_uop_is_sfence_0;\t// @[issue-slot.scala:49:7]\n wire io_iss_uop_is_amo_0;\t// @[issue-slot.scala:49:7]\n wire io_iss_uop_is_eret_0;\t// @[issue-slot.scala:49:7]\n wire io_iss_uop_is_sys_pc2epc_0;\t// @[issue-slot.scala:49:7]\n wire io_iss_uop_is_rocc_0;\t// @[issue-slot.scala:49:7]\n wire io_iss_uop_is_mov_0;\t// @[issue-slot.scala:49:7]\n wire [4:0] io_iss_uop_ftq_idx_0;\t// @[issue-slot.scala:49:7]\n wire io_iss_uop_edge_inst_0;\t// @[issue-slot.scala:49:7]\n wire [5:0] io_iss_uop_pc_lob_0;\t// @[issue-slot.scala:49:7]\n wire io_iss_uop_taken_0;\t// @[issue-slot.scala:49:7]\n wire io_iss_uop_imm_rename_0;\t// @[issue-slot.scala:49:7]\n wire [2:0] io_iss_uop_imm_sel_0;\t// @[issue-slot.scala:49:7]\n wire [4:0] io_iss_uop_pimm_0;\t// @[issue-slot.scala:49:7]\n wire [19:0] io_iss_uop_imm_packed_0;\t// @[issue-slot.scala:49:7]\n wire [1:0] io_iss_uop_op1_sel_0;\t// @[issue-slot.scala:49:7]\n wire [2:0] io_iss_uop_op2_sel_0;\t// @[issue-slot.scala:49:7]\n wire [6:0] io_iss_uop_rob_idx_0;\t// @[issue-slot.scala:49:7]\n wire [4:0] io_iss_uop_ldq_idx_0;\t// @[issue-slot.scala:49:7]\n wire [4:0] io_iss_uop_stq_idx_0;\t// @[issue-slot.scala:49:7]\n wire [1:0] io_iss_uop_rxq_idx_0;\t// @[issue-slot.scala:49:7]\n wire [6:0] io_iss_uop_pdst_0;\t// @[issue-slot.scala:49:7]\n wire [6:0] io_iss_uop_prs1_0;\t// @[issue-slot.scala:49:7]\n wire [6:0] io_iss_uop_prs2_0;\t// @[issue-slot.scala:49:7]\n wire [6:0] io_iss_uop_prs3_0;\t// @[issue-slot.scala:49:7]\n wire [4:0] io_iss_uop_ppred_0;\t// @[issue-slot.scala:49:7]\n wire io_iss_uop_prs1_busy_0;\t// @[issue-slot.scala:49:7]\n wire io_iss_uop_prs2_busy_0;\t// @[issue-slot.scala:49:7]\n wire io_iss_uop_prs3_busy_0;\t// @[issue-slot.scala:49:7]\n wire io_iss_uop_ppred_busy_0;\t// @[issue-slot.scala:49:7]\n wire [6:0] io_iss_uop_stale_pdst_0;\t// @[issue-slot.scala:49:7]\n wire io_iss_uop_exception_0;\t// @[issue-slot.scala:49:7]\n wire [63:0] io_iss_uop_exc_cause_0;\t// @[issue-slot.scala:49:7]\n wire [4:0] io_iss_uop_mem_cmd_0;\t// @[issue-slot.scala:49:7]\n wire [1:0] io_iss_uop_mem_size_0;\t// @[issue-slot.scala:49:7]\n wire io_iss_uop_mem_signed_0;\t// @[issue-slot.scala:49:7]\n wire io_iss_uop_uses_ldq_0;\t// @[issue-slot.scala:49:7]\n wire io_iss_uop_uses_stq_0;\t// @[issue-slot.scala:49:7]\n wire io_iss_uop_is_unique_0;\t// @[issue-slot.scala:49:7]\n wire io_iss_uop_flush_on_commit_0;\t// @[issue-slot.scala:49:7]\n wire [2:0] io_iss_uop_csr_cmd_0;\t// @[issue-slot.scala:49:7]\n wire io_iss_uop_ldst_is_rs1_0;\t// @[issue-slot.scala:49:7]\n wire [5:0] io_iss_uop_ldst_0;\t// @[issue-slot.scala:49:7]\n wire [5:0] io_iss_uop_lrs1_0;\t// @[issue-slot.scala:49:7]\n wire [5:0] io_iss_uop_lrs2_0;\t// @[issue-slot.scala:49:7]\n wire [5:0] io_iss_uop_lrs3_0;\t// @[issue-slot.scala:49:7]\n wire [1:0] io_iss_uop_dst_rtype_0;\t// @[issue-slot.scala:49:7]\n wire [1:0] io_iss_uop_lrs1_rtype_0;\t// @[issue-slot.scala:49:7]\n wire [1:0] io_iss_uop_lrs2_rtype_0;\t// @[issue-slot.scala:49:7]\n wire io_iss_uop_frs3_en_0;\t// @[issue-slot.scala:49:7]\n wire io_iss_uop_fcn_dw_0;\t// @[issue-slot.scala:49:7]\n wire [4:0] io_iss_uop_fcn_op_0;\t// @[issue-slot.scala:49:7]\n wire io_iss_uop_fp_val_0;\t// @[issue-slot.scala:49:7]\n wire [2:0] io_iss_uop_fp_rm_0;\t// @[issue-slot.scala:49:7]\n wire [1:0] io_iss_uop_fp_typ_0;\t// @[issue-slot.scala:49:7]\n wire io_iss_uop_xcpt_pf_if_0;\t// @[issue-slot.scala:49:7]\n wire io_iss_uop_xcpt_ae_if_0;\t// @[issue-slot.scala:49:7]\n wire io_iss_uop_xcpt_ma_if_0;\t// @[issue-slot.scala:49:7]\n wire io_iss_uop_bp_debug_if_0;\t// @[issue-slot.scala:49:7]\n wire io_iss_uop_bp_xcpt_if_0;\t// @[issue-slot.scala:49:7]\n wire [2:0] io_iss_uop_debug_fsrc_0;\t// @[issue-slot.scala:49:7]\n wire [2:0] io_iss_uop_debug_tsrc_0;\t// @[issue-slot.scala:49:7]\n wire io_out_uop_iq_type_0_0;\t// @[issue-slot.scala:49:7]\n wire io_out_uop_iq_type_1_0;\t// @[issue-slot.scala:49:7]\n wire io_out_uop_iq_type_2_0;\t// @[issue-slot.scala:49:7]\n wire io_out_uop_iq_type_3_0;\t// @[issue-slot.scala:49:7]\n wire io_out_uop_fu_code_0_0;\t// @[issue-slot.scala:49:7]\n wire io_out_uop_fu_code_1_0;\t// @[issue-slot.scala:49:7]\n wire io_out_uop_fu_code_2_0;\t// @[issue-slot.scala:49:7]\n wire io_out_uop_fu_code_3_0;\t// @[issue-slot.scala:49:7]\n wire io_out_uop_fu_code_4_0;\t// @[issue-slot.scala:49:7]\n wire io_out_uop_fu_code_5_0;\t// @[issue-slot.scala:49:7]\n wire io_out_uop_fu_code_6_0;\t// @[issue-slot.scala:49:7]\n wire io_out_uop_fu_code_7_0;\t// @[issue-slot.scala:49:7]\n wire io_out_uop_fu_code_8_0;\t// @[issue-slot.scala:49:7]\n wire io_out_uop_fu_code_9_0;\t// @[issue-slot.scala:49:7]\n wire io_out_uop_fp_ctrl_ldst_0;\t// @[issue-slot.scala:49:7]\n wire io_out_uop_fp_ctrl_wen_0;\t// @[issue-slot.scala:49:7]\n wire io_out_uop_fp_ctrl_ren1_0;\t// @[issue-slot.scala:49:7]\n wire io_out_uop_fp_ctrl_ren2_0;\t// @[issue-slot.scala:49:7]\n wire io_out_uop_fp_ctrl_ren3_0;\t// @[issue-slot.scala:49:7]\n wire io_out_uop_fp_ctrl_swap12_0;\t// @[issue-slot.scala:49:7]\n wire io_out_uop_fp_ctrl_swap23_0;\t// @[issue-slot.scala:49:7]\n wire [1:0] io_out_uop_fp_ctrl_typeTagIn_0;\t// @[issue-slot.scala:49:7]\n wire [1:0] io_out_uop_fp_ctrl_typeTagOut_0;\t// @[issue-slot.scala:49:7]\n wire io_out_uop_fp_ctrl_fromint_0;\t// @[issue-slot.scala:49:7]\n wire io_out_uop_fp_ctrl_toint_0;\t// @[issue-slot.scala:49:7]\n wire io_out_uop_fp_ctrl_fastpipe_0;\t// @[issue-slot.scala:49:7]\n wire io_out_uop_fp_ctrl_fma_0;\t// @[issue-slot.scala:49:7]\n wire io_out_uop_fp_ctrl_div_0;\t// @[issue-slot.scala:49:7]\n wire io_out_uop_fp_ctrl_sqrt_0;\t// @[issue-slot.scala:49:7]\n wire io_out_uop_fp_ctrl_wflags_0;\t// @[issue-slot.scala:49:7]\n wire io_out_uop_fp_ctrl_vec_0;\t// @[issue-slot.scala:49:7]\n wire [31:0] io_out_uop_inst_0;\t// @[issue-slot.scala:49:7]\n wire [31:0] io_out_uop_debug_inst_0;\t// @[issue-slot.scala:49:7]\n wire io_out_uop_is_rvc_0;\t// @[issue-slot.scala:49:7]\n wire [39:0] io_out_uop_debug_pc_0;\t// @[issue-slot.scala:49:7]\n wire io_out_uop_iw_issued_0;\t// @[issue-slot.scala:49:7]\n wire [2:0] io_out_uop_iw_p1_speculative_child_0;\t// @[issue-slot.scala:49:7]\n wire [2:0] io_out_uop_iw_p2_speculative_child_0;\t// @[issue-slot.scala:49:7]\n wire io_out_uop_iw_p1_bypass_hint_0;\t// @[issue-slot.scala:49:7]\n wire io_out_uop_iw_p2_bypass_hint_0;\t// @[issue-slot.scala:49:7]\n wire io_out_uop_iw_p3_bypass_hint_0;\t// @[issue-slot.scala:49:7]\n wire [2:0] io_out_uop_dis_col_sel_0;\t// @[issue-slot.scala:49:7]\n wire [15:0] io_out_uop_br_mask_0;\t// @[issue-slot.scala:49:7]\n wire [3:0] io_out_uop_br_tag_0;\t// @[issue-slot.scala:49:7]\n wire [3:0] io_out_uop_br_type_0;\t// @[issue-slot.scala:49:7]\n wire io_out_uop_is_sfb_0;\t// @[issue-slot.scala:49:7]\n wire io_out_uop_is_fence_0;\t// @[issue-slot.scala:49:7]\n wire io_out_uop_is_fencei_0;\t// @[issue-slot.scala:49:7]\n wire io_out_uop_is_sfence_0;\t// @[issue-slot.scala:49:7]\n wire io_out_uop_is_amo_0;\t// @[issue-slot.scala:49:7]\n wire io_out_uop_is_eret_0;\t// @[issue-slot.scala:49:7]\n wire io_out_uop_is_sys_pc2epc_0;\t// @[issue-slot.scala:49:7]\n wire io_out_uop_is_rocc_0;\t// @[issue-slot.scala:49:7]\n wire io_out_uop_is_mov_0;\t// @[issue-slot.scala:49:7]\n wire [4:0] io_out_uop_ftq_idx_0;\t// @[issue-slot.scala:49:7]\n wire io_out_uop_edge_inst_0;\t// @[issue-slot.scala:49:7]\n wire [5:0] io_out_uop_pc_lob_0;\t// @[issue-slot.scala:49:7]\n wire io_out_uop_taken_0;\t// @[issue-slot.scala:49:7]\n wire io_out_uop_imm_rename_0;\t// @[issue-slot.scala:49:7]\n wire [2:0] io_out_uop_imm_sel_0;\t// @[issue-slot.scala:49:7]\n wire [4:0] io_out_uop_pimm_0;\t// @[issue-slot.scala:49:7]\n wire [19:0] io_out_uop_imm_packed_0;\t// @[issue-slot.scala:49:7]\n wire [1:0] io_out_uop_op1_sel_0;\t// @[issue-slot.scala:49:7]\n wire [2:0] io_out_uop_op2_sel_0;\t// @[issue-slot.scala:49:7]\n wire [6:0] io_out_uop_rob_idx_0;\t// @[issue-slot.scala:49:7]\n wire [4:0] io_out_uop_ldq_idx_0;\t// @[issue-slot.scala:49:7]\n wire [4:0] io_out_uop_stq_idx_0;\t// @[issue-slot.scala:49:7]\n wire [1:0] io_out_uop_rxq_idx_0;\t// @[issue-slot.scala:49:7]\n wire [6:0] io_out_uop_pdst_0;\t// @[issue-slot.scala:49:7]\n wire [6:0] io_out_uop_prs1_0;\t// @[issue-slot.scala:49:7]\n wire [6:0] io_out_uop_prs2_0;\t// @[issue-slot.scala:49:7]\n wire [6:0] io_out_uop_prs3_0;\t// @[issue-slot.scala:49:7]\n wire [4:0] io_out_uop_ppred_0;\t// @[issue-slot.scala:49:7]\n wire io_out_uop_prs1_busy_0;\t// @[issue-slot.scala:49:7]\n wire io_out_uop_prs2_busy_0;\t// @[issue-slot.scala:49:7]\n wire io_out_uop_prs3_busy_0;\t// @[issue-slot.scala:49:7]\n wire io_out_uop_ppred_busy_0;\t// @[issue-slot.scala:49:7]\n wire [6:0] io_out_uop_stale_pdst_0;\t// @[issue-slot.scala:49:7]\n wire io_out_uop_exception_0;\t// @[issue-slot.scala:49:7]\n wire [63:0] io_out_uop_exc_cause_0;\t// @[issue-slot.scala:49:7]\n wire [4:0] io_out_uop_mem_cmd_0;\t// @[issue-slot.scala:49:7]\n wire [1:0] io_out_uop_mem_size_0;\t// @[issue-slot.scala:49:7]\n wire io_out_uop_mem_signed_0;\t// @[issue-slot.scala:49:7]\n wire io_out_uop_uses_ldq_0;\t// @[issue-slot.scala:49:7]\n wire io_out_uop_uses_stq_0;\t// @[issue-slot.scala:49:7]\n wire io_out_uop_is_unique_0;\t// @[issue-slot.scala:49:7]\n wire io_out_uop_flush_on_commit_0;\t// @[issue-slot.scala:49:7]\n wire [2:0] io_out_uop_csr_cmd_0;\t// @[issue-slot.scala:49:7]\n wire io_out_uop_ldst_is_rs1_0;\t// @[issue-slot.scala:49:7]\n wire [5:0] io_out_uop_ldst_0;\t// @[issue-slot.scala:49:7]\n wire [5:0] io_out_uop_lrs1_0;\t// @[issue-slot.scala:49:7]\n wire [5:0] io_out_uop_lrs2_0;\t// @[issue-slot.scala:49:7]\n wire [5:0] io_out_uop_lrs3_0;\t// @[issue-slot.scala:49:7]\n wire [1:0] io_out_uop_dst_rtype_0;\t// @[issue-slot.scala:49:7]\n wire [1:0] io_out_uop_lrs1_rtype_0;\t// @[issue-slot.scala:49:7]\n wire [1:0] io_out_uop_lrs2_rtype_0;\t// @[issue-slot.scala:49:7]\n wire io_out_uop_frs3_en_0;\t// @[issue-slot.scala:49:7]\n wire io_out_uop_fcn_dw_0;\t// @[issue-slot.scala:49:7]\n wire [4:0] io_out_uop_fcn_op_0;\t// @[issue-slot.scala:49:7]\n wire io_out_uop_fp_val_0;\t// @[issue-slot.scala:49:7]\n wire [2:0] io_out_uop_fp_rm_0;\t// @[issue-slot.scala:49:7]\n wire [1:0] io_out_uop_fp_typ_0;\t// @[issue-slot.scala:49:7]\n wire io_out_uop_xcpt_pf_if_0;\t// @[issue-slot.scala:49:7]\n wire io_out_uop_xcpt_ae_if_0;\t// @[issue-slot.scala:49:7]\n wire io_out_uop_xcpt_ma_if_0;\t// @[issue-slot.scala:49:7]\n wire io_out_uop_bp_debug_if_0;\t// @[issue-slot.scala:49:7]\n wire io_out_uop_bp_xcpt_if_0;\t// @[issue-slot.scala:49:7]\n wire [2:0] io_out_uop_debug_fsrc_0;\t// @[issue-slot.scala:49:7]\n wire [2:0] io_out_uop_debug_tsrc_0;\t// @[issue-slot.scala:49:7]\n wire io_valid_0;\t// @[issue-slot.scala:49:7]\n wire io_will_be_valid_0;\t// @[issue-slot.scala:49:7]\n wire io_request_0;\t// @[issue-slot.scala:49:7]\n reg slot_valid;\t// @[issue-slot.scala:55:27]\n assign io_valid_0 = slot_valid;\t// @[issue-slot.scala:49:7, :55:27]\n reg [31:0] slot_uop_inst;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_inst_0 = slot_uop_inst;\t// @[issue-slot.scala:49:7, :56:21]\n wire [31:0] next_uop_out_inst = slot_uop_inst;\t// @[util.scala:104:23]\n reg [31:0] slot_uop_debug_inst;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_debug_inst_0 = slot_uop_debug_inst;\t// @[issue-slot.scala:49:7, :56:21]\n wire [31:0] next_uop_out_debug_inst = slot_uop_debug_inst;\t// @[util.scala:104:23]\n reg slot_uop_is_rvc;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_is_rvc_0 = slot_uop_is_rvc;\t// @[issue-slot.scala:49:7, :56:21]\n wire next_uop_out_is_rvc = slot_uop_is_rvc;\t// @[util.scala:104:23]\n reg [39:0] slot_uop_debug_pc;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_debug_pc_0 = slot_uop_debug_pc;\t// @[issue-slot.scala:49:7, :56:21]\n wire [39:0] next_uop_out_debug_pc = slot_uop_debug_pc;\t// @[util.scala:104:23]\n reg slot_uop_iq_type_0;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_iq_type_0_0 = slot_uop_iq_type_0;\t// @[issue-slot.scala:49:7, :56:21]\n wire next_uop_out_iq_type_0 = slot_uop_iq_type_0;\t// @[util.scala:104:23]\n reg slot_uop_iq_type_1;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_iq_type_1_0 = slot_uop_iq_type_1;\t// @[issue-slot.scala:49:7, :56:21]\n wire next_uop_out_iq_type_1 = slot_uop_iq_type_1;\t// @[util.scala:104:23]\n reg slot_uop_iq_type_2;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_iq_type_2_0 = slot_uop_iq_type_2;\t// @[issue-slot.scala:49:7, :56:21]\n wire next_uop_out_iq_type_2 = slot_uop_iq_type_2;\t// @[util.scala:104:23]\n reg slot_uop_iq_type_3;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_iq_type_3_0 = slot_uop_iq_type_3;\t// @[issue-slot.scala:49:7, :56:21]\n wire next_uop_out_iq_type_3 = slot_uop_iq_type_3;\t// @[util.scala:104:23]\n reg slot_uop_fu_code_0;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_fu_code_0_0 = slot_uop_fu_code_0;\t// @[issue-slot.scala:49:7, :56:21]\n wire next_uop_out_fu_code_0 = slot_uop_fu_code_0;\t// @[util.scala:104:23]\n reg slot_uop_fu_code_1;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_fu_code_1_0 = slot_uop_fu_code_1;\t// @[issue-slot.scala:49:7, :56:21]\n wire next_uop_out_fu_code_1 = slot_uop_fu_code_1;\t// @[util.scala:104:23]\n reg slot_uop_fu_code_2;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_fu_code_2_0 = slot_uop_fu_code_2;\t// @[issue-slot.scala:49:7, :56:21]\n wire next_uop_out_fu_code_2 = slot_uop_fu_code_2;\t// @[util.scala:104:23]\n reg slot_uop_fu_code_3;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_fu_code_3_0 = slot_uop_fu_code_3;\t// @[issue-slot.scala:49:7, :56:21]\n wire next_uop_out_fu_code_3 = slot_uop_fu_code_3;\t// @[util.scala:104:23]\n reg slot_uop_fu_code_4;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_fu_code_4_0 = slot_uop_fu_code_4;\t// @[issue-slot.scala:49:7, :56:21]\n wire next_uop_out_fu_code_4 = slot_uop_fu_code_4;\t// @[util.scala:104:23]\n reg slot_uop_fu_code_5;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_fu_code_5_0 = slot_uop_fu_code_5;\t// @[issue-slot.scala:49:7, :56:21]\n wire next_uop_out_fu_code_5 = slot_uop_fu_code_5;\t// @[util.scala:104:23]\n reg slot_uop_fu_code_6;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_fu_code_6_0 = slot_uop_fu_code_6;\t// @[issue-slot.scala:49:7, :56:21]\n wire next_uop_out_fu_code_6 = slot_uop_fu_code_6;\t// @[util.scala:104:23]\n reg slot_uop_fu_code_7;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_fu_code_7_0 = slot_uop_fu_code_7;\t// @[issue-slot.scala:49:7, :56:21]\n wire next_uop_out_fu_code_7 = slot_uop_fu_code_7;\t// @[util.scala:104:23]\n reg slot_uop_fu_code_8;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_fu_code_8_0 = slot_uop_fu_code_8;\t// @[issue-slot.scala:49:7, :56:21]\n wire next_uop_out_fu_code_8 = slot_uop_fu_code_8;\t// @[util.scala:104:23]\n reg slot_uop_fu_code_9;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_fu_code_9_0 = slot_uop_fu_code_9;\t// @[issue-slot.scala:49:7, :56:21]\n wire next_uop_out_fu_code_9 = slot_uop_fu_code_9;\t// @[util.scala:104:23]\n reg slot_uop_iw_issued;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_iw_issued_0 = slot_uop_iw_issued;\t// @[issue-slot.scala:49:7, :56:21]\n wire next_uop_out_iw_issued = slot_uop_iw_issued;\t// @[util.scala:104:23]\n reg [2:0] slot_uop_iw_p1_speculative_child;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_iw_p1_speculative_child_0 = slot_uop_iw_p1_speculative_child;\t// @[issue-slot.scala:49:7, :56:21]\n wire [2:0] next_uop_out_iw_p1_speculative_child = slot_uop_iw_p1_speculative_child;\t// @[util.scala:104:23]\n reg [2:0] slot_uop_iw_p2_speculative_child;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_iw_p2_speculative_child_0 = slot_uop_iw_p2_speculative_child;\t// @[issue-slot.scala:49:7, :56:21]\n wire [2:0] next_uop_out_iw_p2_speculative_child = slot_uop_iw_p2_speculative_child;\t// @[util.scala:104:23]\n reg slot_uop_iw_p1_bypass_hint;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_iw_p1_bypass_hint_0 = slot_uop_iw_p1_bypass_hint;\t// @[issue-slot.scala:49:7, :56:21]\n wire next_uop_out_iw_p1_bypass_hint = slot_uop_iw_p1_bypass_hint;\t// @[util.scala:104:23]\n reg slot_uop_iw_p2_bypass_hint;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_iw_p2_bypass_hint_0 = slot_uop_iw_p2_bypass_hint;\t// @[issue-slot.scala:49:7, :56:21]\n wire next_uop_out_iw_p2_bypass_hint = slot_uop_iw_p2_bypass_hint;\t// @[util.scala:104:23]\n reg slot_uop_iw_p3_bypass_hint;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_iw_p3_bypass_hint_0 = slot_uop_iw_p3_bypass_hint;\t// @[issue-slot.scala:49:7, :56:21]\n wire next_uop_out_iw_p3_bypass_hint = slot_uop_iw_p3_bypass_hint;\t// @[util.scala:104:23]\n reg [2:0] slot_uop_dis_col_sel;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_dis_col_sel_0 = slot_uop_dis_col_sel;\t// @[issue-slot.scala:49:7, :56:21]\n wire [2:0] next_uop_out_dis_col_sel = slot_uop_dis_col_sel;\t// @[util.scala:104:23]\n reg [15:0] slot_uop_br_mask;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_br_mask_0 = slot_uop_br_mask;\t// @[issue-slot.scala:49:7, :56:21]\n reg [3:0] slot_uop_br_tag;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_br_tag_0 = slot_uop_br_tag;\t// @[issue-slot.scala:49:7, :56:21]\n wire [3:0] next_uop_out_br_tag = slot_uop_br_tag;\t// @[util.scala:104:23]\n reg [3:0] slot_uop_br_type;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_br_type_0 = slot_uop_br_type;\t// @[issue-slot.scala:49:7, :56:21]\n wire [3:0] next_uop_out_br_type = slot_uop_br_type;\t// @[util.scala:104:23]\n reg slot_uop_is_sfb;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_is_sfb_0 = slot_uop_is_sfb;\t// @[issue-slot.scala:49:7, :56:21]\n wire next_uop_out_is_sfb = slot_uop_is_sfb;\t// @[util.scala:104:23]\n reg slot_uop_is_fence;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_is_fence_0 = slot_uop_is_fence;\t// @[issue-slot.scala:49:7, :56:21]\n wire next_uop_out_is_fence = slot_uop_is_fence;\t// @[util.scala:104:23]\n reg slot_uop_is_fencei;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_is_fencei_0 = slot_uop_is_fencei;\t// @[issue-slot.scala:49:7, :56:21]\n wire next_uop_out_is_fencei = slot_uop_is_fencei;\t// @[util.scala:104:23]\n reg slot_uop_is_sfence;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_is_sfence_0 = slot_uop_is_sfence;\t// @[issue-slot.scala:49:7, :56:21]\n wire next_uop_out_is_sfence = slot_uop_is_sfence;\t// @[util.scala:104:23]\n reg slot_uop_is_amo;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_is_amo_0 = slot_uop_is_amo;\t// @[issue-slot.scala:49:7, :56:21]\n wire next_uop_out_is_amo = slot_uop_is_amo;\t// @[util.scala:104:23]\n reg slot_uop_is_eret;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_is_eret_0 = slot_uop_is_eret;\t// @[issue-slot.scala:49:7, :56:21]\n wire next_uop_out_is_eret = slot_uop_is_eret;\t// @[util.scala:104:23]\n reg slot_uop_is_sys_pc2epc;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc;\t// @[issue-slot.scala:49:7, :56:21]\n wire next_uop_out_is_sys_pc2epc = slot_uop_is_sys_pc2epc;\t// @[util.scala:104:23]\n reg slot_uop_is_rocc;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_is_rocc_0 = slot_uop_is_rocc;\t// @[issue-slot.scala:49:7, :56:21]\n wire next_uop_out_is_rocc = slot_uop_is_rocc;\t// @[util.scala:104:23]\n reg slot_uop_is_mov;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_is_mov_0 = slot_uop_is_mov;\t// @[issue-slot.scala:49:7, :56:21]\n wire next_uop_out_is_mov = slot_uop_is_mov;\t// @[util.scala:104:23]\n reg [4:0] slot_uop_ftq_idx;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_ftq_idx_0 = slot_uop_ftq_idx;\t// @[issue-slot.scala:49:7, :56:21]\n wire [4:0] next_uop_out_ftq_idx = slot_uop_ftq_idx;\t// @[util.scala:104:23]\n reg slot_uop_edge_inst;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_edge_inst_0 = slot_uop_edge_inst;\t// @[issue-slot.scala:49:7, :56:21]\n wire next_uop_out_edge_inst = slot_uop_edge_inst;\t// @[util.scala:104:23]\n reg [5:0] slot_uop_pc_lob;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_pc_lob_0 = slot_uop_pc_lob;\t// @[issue-slot.scala:49:7, :56:21]\n wire [5:0] next_uop_out_pc_lob = slot_uop_pc_lob;\t// @[util.scala:104:23]\n reg slot_uop_taken;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_taken_0 = slot_uop_taken;\t// @[issue-slot.scala:49:7, :56:21]\n wire next_uop_out_taken = slot_uop_taken;\t// @[util.scala:104:23]\n reg slot_uop_imm_rename;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_imm_rename_0 = slot_uop_imm_rename;\t// @[issue-slot.scala:49:7, :56:21]\n wire next_uop_out_imm_rename = slot_uop_imm_rename;\t// @[util.scala:104:23]\n reg [2:0] slot_uop_imm_sel;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_imm_sel_0 = slot_uop_imm_sel;\t// @[issue-slot.scala:49:7, :56:21]\n wire [2:0] next_uop_out_imm_sel = slot_uop_imm_sel;\t// @[util.scala:104:23]\n reg [4:0] slot_uop_pimm;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_pimm_0 = slot_uop_pimm;\t// @[issue-slot.scala:49:7, :56:21]\n wire [4:0] next_uop_out_pimm = slot_uop_pimm;\t// @[util.scala:104:23]\n reg [19:0] slot_uop_imm_packed;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_imm_packed_0 = slot_uop_imm_packed;\t// @[issue-slot.scala:49:7, :56:21]\n wire [19:0] next_uop_out_imm_packed = slot_uop_imm_packed;\t// @[util.scala:104:23]\n reg [1:0] slot_uop_op1_sel;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_op1_sel_0 = slot_uop_op1_sel;\t// @[issue-slot.scala:49:7, :56:21]\n wire [1:0] next_uop_out_op1_sel = slot_uop_op1_sel;\t// @[util.scala:104:23]\n reg [2:0] slot_uop_op2_sel;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_op2_sel_0 = slot_uop_op2_sel;\t// @[issue-slot.scala:49:7, :56:21]\n wire [2:0] next_uop_out_op2_sel = slot_uop_op2_sel;\t// @[util.scala:104:23]\n reg slot_uop_fp_ctrl_ldst;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_fp_ctrl_ldst_0 = slot_uop_fp_ctrl_ldst;\t// @[issue-slot.scala:49:7, :56:21]\n wire next_uop_out_fp_ctrl_ldst = slot_uop_fp_ctrl_ldst;\t// @[util.scala:104:23]\n reg slot_uop_fp_ctrl_wen;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_fp_ctrl_wen_0 = slot_uop_fp_ctrl_wen;\t// @[issue-slot.scala:49:7, :56:21]\n wire next_uop_out_fp_ctrl_wen = slot_uop_fp_ctrl_wen;\t// @[util.scala:104:23]\n reg slot_uop_fp_ctrl_ren1;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_fp_ctrl_ren1_0 = slot_uop_fp_ctrl_ren1;\t// @[issue-slot.scala:49:7, :56:21]\n wire next_uop_out_fp_ctrl_ren1 = slot_uop_fp_ctrl_ren1;\t// @[util.scala:104:23]\n reg slot_uop_fp_ctrl_ren2;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_fp_ctrl_ren2_0 = slot_uop_fp_ctrl_ren2;\t// @[issue-slot.scala:49:7, :56:21]\n wire next_uop_out_fp_ctrl_ren2 = slot_uop_fp_ctrl_ren2;\t// @[util.scala:104:23]\n reg slot_uop_fp_ctrl_ren3;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_fp_ctrl_ren3_0 = slot_uop_fp_ctrl_ren3;\t// @[issue-slot.scala:49:7, :56:21]\n wire next_uop_out_fp_ctrl_ren3 = slot_uop_fp_ctrl_ren3;\t// @[util.scala:104:23]\n reg slot_uop_fp_ctrl_swap12;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_fp_ctrl_swap12_0 = slot_uop_fp_ctrl_swap12;\t// @[issue-slot.scala:49:7, :56:21]\n wire next_uop_out_fp_ctrl_swap12 = slot_uop_fp_ctrl_swap12;\t// @[util.scala:104:23]\n reg slot_uop_fp_ctrl_swap23;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_fp_ctrl_swap23_0 = slot_uop_fp_ctrl_swap23;\t// @[issue-slot.scala:49:7, :56:21]\n wire next_uop_out_fp_ctrl_swap23 = slot_uop_fp_ctrl_swap23;\t// @[util.scala:104:23]\n reg [1:0] slot_uop_fp_ctrl_typeTagIn;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_fp_ctrl_typeTagIn_0 = slot_uop_fp_ctrl_typeTagIn;\t// @[issue-slot.scala:49:7, :56:21]\n wire [1:0] next_uop_out_fp_ctrl_typeTagIn = slot_uop_fp_ctrl_typeTagIn;\t// @[util.scala:104:23]\n reg [1:0] slot_uop_fp_ctrl_typeTagOut;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_fp_ctrl_typeTagOut_0 = slot_uop_fp_ctrl_typeTagOut;\t// @[issue-slot.scala:49:7, :56:21]\n wire [1:0] next_uop_out_fp_ctrl_typeTagOut = slot_uop_fp_ctrl_typeTagOut;\t// @[util.scala:104:23]\n reg slot_uop_fp_ctrl_fromint;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_fp_ctrl_fromint_0 = slot_uop_fp_ctrl_fromint;\t// @[issue-slot.scala:49:7, :56:21]\n wire next_uop_out_fp_ctrl_fromint = slot_uop_fp_ctrl_fromint;\t// @[util.scala:104:23]\n reg slot_uop_fp_ctrl_toint;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_fp_ctrl_toint_0 = slot_uop_fp_ctrl_toint;\t// @[issue-slot.scala:49:7, :56:21]\n wire next_uop_out_fp_ctrl_toint = slot_uop_fp_ctrl_toint;\t// @[util.scala:104:23]\n reg slot_uop_fp_ctrl_fastpipe;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_fp_ctrl_fastpipe_0 = slot_uop_fp_ctrl_fastpipe;\t// @[issue-slot.scala:49:7, :56:21]\n wire next_uop_out_fp_ctrl_fastpipe = slot_uop_fp_ctrl_fastpipe;\t// @[util.scala:104:23]\n reg slot_uop_fp_ctrl_fma;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_fp_ctrl_fma_0 = slot_uop_fp_ctrl_fma;\t// @[issue-slot.scala:49:7, :56:21]\n wire next_uop_out_fp_ctrl_fma = slot_uop_fp_ctrl_fma;\t// @[util.scala:104:23]\n reg slot_uop_fp_ctrl_div;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_fp_ctrl_div_0 = slot_uop_fp_ctrl_div;\t// @[issue-slot.scala:49:7, :56:21]\n wire next_uop_out_fp_ctrl_div = slot_uop_fp_ctrl_div;\t// @[util.scala:104:23]\n reg slot_uop_fp_ctrl_sqrt;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_fp_ctrl_sqrt_0 = slot_uop_fp_ctrl_sqrt;\t// @[issue-slot.scala:49:7, :56:21]\n wire next_uop_out_fp_ctrl_sqrt = slot_uop_fp_ctrl_sqrt;\t// @[util.scala:104:23]\n reg slot_uop_fp_ctrl_wflags;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_fp_ctrl_wflags_0 = slot_uop_fp_ctrl_wflags;\t// @[issue-slot.scala:49:7, :56:21]\n wire next_uop_out_fp_ctrl_wflags = slot_uop_fp_ctrl_wflags;\t// @[util.scala:104:23]\n reg slot_uop_fp_ctrl_vec;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_fp_ctrl_vec_0 = slot_uop_fp_ctrl_vec;\t// @[issue-slot.scala:49:7, :56:21]\n wire next_uop_out_fp_ctrl_vec = slot_uop_fp_ctrl_vec;\t// @[util.scala:104:23]\n reg [6:0] slot_uop_rob_idx;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_rob_idx_0 = slot_uop_rob_idx;\t// @[issue-slot.scala:49:7, :56:21]\n wire [6:0] next_uop_out_rob_idx = slot_uop_rob_idx;\t// @[util.scala:104:23]\n reg [4:0] slot_uop_ldq_idx;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_ldq_idx_0 = slot_uop_ldq_idx;\t// @[issue-slot.scala:49:7, :56:21]\n wire [4:0] next_uop_out_ldq_idx = slot_uop_ldq_idx;\t// @[util.scala:104:23]\n reg [4:0] slot_uop_stq_idx;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_stq_idx_0 = slot_uop_stq_idx;\t// @[issue-slot.scala:49:7, :56:21]\n wire [4:0] next_uop_out_stq_idx = slot_uop_stq_idx;\t// @[util.scala:104:23]\n reg [1:0] slot_uop_rxq_idx;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_rxq_idx_0 = slot_uop_rxq_idx;\t// @[issue-slot.scala:49:7, :56:21]\n wire [1:0] next_uop_out_rxq_idx = slot_uop_rxq_idx;\t// @[util.scala:104:23]\n reg [6:0] slot_uop_pdst;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_pdst_0 = slot_uop_pdst;\t// @[issue-slot.scala:49:7, :56:21]\n wire [6:0] next_uop_out_pdst = slot_uop_pdst;\t// @[util.scala:104:23]\n reg [6:0] slot_uop_prs1;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_prs1_0 = slot_uop_prs1;\t// @[issue-slot.scala:49:7, :56:21]\n wire [6:0] next_uop_out_prs1 = slot_uop_prs1;\t// @[util.scala:104:23]\n reg [6:0] slot_uop_prs2;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_prs2_0 = slot_uop_prs2;\t// @[issue-slot.scala:49:7, :56:21]\n wire [6:0] next_uop_out_prs2 = slot_uop_prs2;\t// @[util.scala:104:23]\n reg [6:0] slot_uop_prs3;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_prs3_0 = slot_uop_prs3;\t// @[issue-slot.scala:49:7, :56:21]\n wire [6:0] next_uop_out_prs3 = slot_uop_prs3;\t// @[util.scala:104:23]\n reg [4:0] slot_uop_ppred;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_ppred_0 = slot_uop_ppred;\t// @[issue-slot.scala:49:7, :56:21]\n wire [4:0] next_uop_out_ppred = slot_uop_ppred;\t// @[util.scala:104:23]\n reg slot_uop_prs1_busy;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_prs1_busy_0 = slot_uop_prs1_busy;\t// @[issue-slot.scala:49:7, :56:21]\n wire next_uop_out_prs1_busy = slot_uop_prs1_busy;\t// @[util.scala:104:23]\n reg slot_uop_prs2_busy;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_prs2_busy_0 = slot_uop_prs2_busy;\t// @[issue-slot.scala:49:7, :56:21]\n wire next_uop_out_prs2_busy = slot_uop_prs2_busy;\t// @[util.scala:104:23]\n reg slot_uop_prs3_busy;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_prs3_busy_0 = slot_uop_prs3_busy;\t// @[issue-slot.scala:49:7, :56:21]\n wire next_uop_out_prs3_busy = slot_uop_prs3_busy;\t// @[util.scala:104:23]\n reg slot_uop_ppred_busy;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_ppred_busy_0 = slot_uop_ppred_busy;\t// @[issue-slot.scala:49:7, :56:21]\n wire next_uop_out_ppred_busy = slot_uop_ppred_busy;\t// @[util.scala:104:23]\n wire _iss_ready_T_3 = slot_uop_ppred_busy;\t// @[issue-slot.scala:56:21, :136:88]\n wire _agen_ready_T_2 = slot_uop_ppred_busy;\t// @[issue-slot.scala:56:21, :137:95]\n wire _dgen_ready_T_2 = slot_uop_ppred_busy;\t// @[issue-slot.scala:56:21, :138:95]\n reg [6:0] slot_uop_stale_pdst;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_stale_pdst_0 = slot_uop_stale_pdst;\t// @[issue-slot.scala:49:7, :56:21]\n wire [6:0] next_uop_out_stale_pdst = slot_uop_stale_pdst;\t// @[util.scala:104:23]\n reg slot_uop_exception;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_exception_0 = slot_uop_exception;\t// @[issue-slot.scala:49:7, :56:21]\n wire next_uop_out_exception = slot_uop_exception;\t// @[util.scala:104:23]\n reg [63:0] slot_uop_exc_cause;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_exc_cause_0 = slot_uop_exc_cause;\t// @[issue-slot.scala:49:7, :56:21]\n wire [63:0] next_uop_out_exc_cause = slot_uop_exc_cause;\t// @[util.scala:104:23]\n reg [4:0] slot_uop_mem_cmd;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_mem_cmd_0 = slot_uop_mem_cmd;\t// @[issue-slot.scala:49:7, :56:21]\n wire [4:0] next_uop_out_mem_cmd = slot_uop_mem_cmd;\t// @[util.scala:104:23]\n reg [1:0] slot_uop_mem_size;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_mem_size_0 = slot_uop_mem_size;\t// @[issue-slot.scala:49:7, :56:21]\n wire [1:0] next_uop_out_mem_size = slot_uop_mem_size;\t// @[util.scala:104:23]\n reg slot_uop_mem_signed;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_mem_signed_0 = slot_uop_mem_signed;\t// @[issue-slot.scala:49:7, :56:21]\n wire next_uop_out_mem_signed = slot_uop_mem_signed;\t// @[util.scala:104:23]\n reg slot_uop_uses_ldq;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_uses_ldq_0 = slot_uop_uses_ldq;\t// @[issue-slot.scala:49:7, :56:21]\n wire next_uop_out_uses_ldq = slot_uop_uses_ldq;\t// @[util.scala:104:23]\n reg slot_uop_uses_stq;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_uses_stq_0 = slot_uop_uses_stq;\t// @[issue-slot.scala:49:7, :56:21]\n wire next_uop_out_uses_stq = slot_uop_uses_stq;\t// @[util.scala:104:23]\n reg slot_uop_is_unique;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_is_unique_0 = slot_uop_is_unique;\t// @[issue-slot.scala:49:7, :56:21]\n wire next_uop_out_is_unique = slot_uop_is_unique;\t// @[util.scala:104:23]\n reg slot_uop_flush_on_commit;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_flush_on_commit_0 = slot_uop_flush_on_commit;\t// @[issue-slot.scala:49:7, :56:21]\n wire next_uop_out_flush_on_commit = slot_uop_flush_on_commit;\t// @[util.scala:104:23]\n reg [2:0] slot_uop_csr_cmd;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_csr_cmd_0 = slot_uop_csr_cmd;\t// @[issue-slot.scala:49:7, :56:21]\n wire [2:0] next_uop_out_csr_cmd = slot_uop_csr_cmd;\t// @[util.scala:104:23]\n reg slot_uop_ldst_is_rs1;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1;\t// @[issue-slot.scala:49:7, :56:21]\n wire next_uop_out_ldst_is_rs1 = slot_uop_ldst_is_rs1;\t// @[util.scala:104:23]\n reg [5:0] slot_uop_ldst;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_ldst_0 = slot_uop_ldst;\t// @[issue-slot.scala:49:7, :56:21]\n wire [5:0] next_uop_out_ldst = slot_uop_ldst;\t// @[util.scala:104:23]\n reg [5:0] slot_uop_lrs1;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_lrs1_0 = slot_uop_lrs1;\t// @[issue-slot.scala:49:7, :56:21]\n wire [5:0] next_uop_out_lrs1 = slot_uop_lrs1;\t// @[util.scala:104:23]\n reg [5:0] slot_uop_lrs2;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_lrs2_0 = slot_uop_lrs2;\t// @[issue-slot.scala:49:7, :56:21]\n wire [5:0] next_uop_out_lrs2 = slot_uop_lrs2;\t// @[util.scala:104:23]\n reg [5:0] slot_uop_lrs3;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_lrs3_0 = slot_uop_lrs3;\t// @[issue-slot.scala:49:7, :56:21]\n wire [5:0] next_uop_out_lrs3 = slot_uop_lrs3;\t// @[util.scala:104:23]\n reg [1:0] slot_uop_dst_rtype;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_dst_rtype_0 = slot_uop_dst_rtype;\t// @[issue-slot.scala:49:7, :56:21]\n wire [1:0] next_uop_out_dst_rtype = slot_uop_dst_rtype;\t// @[util.scala:104:23]\n reg [1:0] slot_uop_lrs1_rtype;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_lrs1_rtype_0 = slot_uop_lrs1_rtype;\t// @[issue-slot.scala:49:7, :56:21]\n wire [1:0] next_uop_out_lrs1_rtype = slot_uop_lrs1_rtype;\t// @[util.scala:104:23]\n reg [1:0] slot_uop_lrs2_rtype;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_lrs2_rtype_0 = slot_uop_lrs2_rtype;\t// @[issue-slot.scala:49:7, :56:21]\n wire [1:0] next_uop_out_lrs2_rtype = slot_uop_lrs2_rtype;\t// @[util.scala:104:23]\n reg slot_uop_frs3_en;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_frs3_en_0 = slot_uop_frs3_en;\t// @[issue-slot.scala:49:7, :56:21]\n wire next_uop_out_frs3_en = slot_uop_frs3_en;\t// @[util.scala:104:23]\n reg slot_uop_fcn_dw;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_fcn_dw_0 = slot_uop_fcn_dw;\t// @[issue-slot.scala:49:7, :56:21]\n wire next_uop_out_fcn_dw = slot_uop_fcn_dw;\t// @[util.scala:104:23]\n reg [4:0] slot_uop_fcn_op;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_fcn_op_0 = slot_uop_fcn_op;\t// @[issue-slot.scala:49:7, :56:21]\n wire [4:0] next_uop_out_fcn_op = slot_uop_fcn_op;\t// @[util.scala:104:23]\n reg slot_uop_fp_val;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_fp_val_0 = slot_uop_fp_val;\t// @[issue-slot.scala:49:7, :56:21]\n wire next_uop_out_fp_val = slot_uop_fp_val;\t// @[util.scala:104:23]\n reg [2:0] slot_uop_fp_rm;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_fp_rm_0 = slot_uop_fp_rm;\t// @[issue-slot.scala:49:7, :56:21]\n wire [2:0] next_uop_out_fp_rm = slot_uop_fp_rm;\t// @[util.scala:104:23]\n reg [1:0] slot_uop_fp_typ;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_fp_typ_0 = slot_uop_fp_typ;\t// @[issue-slot.scala:49:7, :56:21]\n wire [1:0] next_uop_out_fp_typ = slot_uop_fp_typ;\t// @[util.scala:104:23]\n reg slot_uop_xcpt_pf_if;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if;\t// @[issue-slot.scala:49:7, :56:21]\n wire next_uop_out_xcpt_pf_if = slot_uop_xcpt_pf_if;\t// @[util.scala:104:23]\n reg slot_uop_xcpt_ae_if;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if;\t// @[issue-slot.scala:49:7, :56:21]\n wire next_uop_out_xcpt_ae_if = slot_uop_xcpt_ae_if;\t// @[util.scala:104:23]\n reg slot_uop_xcpt_ma_if;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if;\t// @[issue-slot.scala:49:7, :56:21]\n wire next_uop_out_xcpt_ma_if = slot_uop_xcpt_ma_if;\t// @[util.scala:104:23]\n reg slot_uop_bp_debug_if;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_bp_debug_if_0 = slot_uop_bp_debug_if;\t// @[issue-slot.scala:49:7, :56:21]\n wire next_uop_out_bp_debug_if = slot_uop_bp_debug_if;\t// @[util.scala:104:23]\n reg slot_uop_bp_xcpt_if;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if;\t// @[issue-slot.scala:49:7, :56:21]\n wire next_uop_out_bp_xcpt_if = slot_uop_bp_xcpt_if;\t// @[util.scala:104:23]\n reg [2:0] slot_uop_debug_fsrc;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_debug_fsrc_0 = slot_uop_debug_fsrc;\t// @[issue-slot.scala:49:7, :56:21]\n wire [2:0] next_uop_out_debug_fsrc = slot_uop_debug_fsrc;\t// @[util.scala:104:23]\n reg [2:0] slot_uop_debug_tsrc;\t// @[issue-slot.scala:56:21]\n assign io_iss_uop_debug_tsrc_0 = slot_uop_debug_tsrc;\t// @[issue-slot.scala:49:7, :56:21]\n wire [2:0] next_uop_out_debug_tsrc = slot_uop_debug_tsrc;\t// @[util.scala:104:23]\n wire next_valid;\t// @[issue-slot.scala:58:28]\n assign next_uop_inst = next_uop_out_inst;\t// @[util.scala:104:23]\n assign next_uop_debug_inst = next_uop_out_debug_inst;\t// @[util.scala:104:23]\n assign next_uop_is_rvc = next_uop_out_is_rvc;\t// @[util.scala:104:23]\n assign next_uop_debug_pc = next_uop_out_debug_pc;\t// @[util.scala:104:23]\n assign next_uop_iq_type_0 = next_uop_out_iq_type_0;\t// @[util.scala:104:23]\n assign next_uop_iq_type_1 = next_uop_out_iq_type_1;\t// @[util.scala:104:23]\n assign next_uop_iq_type_2 = next_uop_out_iq_type_2;\t// @[util.scala:104:23]\n assign next_uop_iq_type_3 = next_uop_out_iq_type_3;\t// @[util.scala:104:23]\n assign next_uop_fu_code_0 = next_uop_out_fu_code_0;\t// @[util.scala:104:23]\n assign next_uop_fu_code_1 = next_uop_out_fu_code_1;\t// @[util.scala:104:23]\n assign next_uop_fu_code_2 = next_uop_out_fu_code_2;\t// @[util.scala:104:23]\n assign next_uop_fu_code_3 = next_uop_out_fu_code_3;\t// @[util.scala:104:23]\n assign next_uop_fu_code_4 = next_uop_out_fu_code_4;\t// @[util.scala:104:23]\n assign next_uop_fu_code_5 = next_uop_out_fu_code_5;\t// @[util.scala:104:23]\n assign next_uop_fu_code_6 = next_uop_out_fu_code_6;\t// @[util.scala:104:23]\n assign next_uop_fu_code_7 = next_uop_out_fu_code_7;\t// @[util.scala:104:23]\n assign next_uop_fu_code_8 = next_uop_out_fu_code_8;\t// @[util.scala:104:23]\n assign next_uop_fu_code_9 = next_uop_out_fu_code_9;\t// @[util.scala:104:23]\n wire [15:0] _next_uop_out_br_mask_T_1;\t// @[util.scala:93:25]\n assign next_uop_dis_col_sel = next_uop_out_dis_col_sel;\t// @[util.scala:104:23]\n assign next_uop_br_mask = next_uop_out_br_mask;\t// @[util.scala:104:23]\n assign next_uop_br_tag = next_uop_out_br_tag;\t// @[util.scala:104:23]\n assign next_uop_br_type = next_uop_out_br_type;\t// @[util.scala:104:23]\n assign next_uop_is_sfb = next_uop_out_is_sfb;\t// @[util.scala:104:23]\n assign next_uop_is_fence = next_uop_out_is_fence;\t// @[util.scala:104:23]\n assign next_uop_is_fencei = next_uop_out_is_fencei;\t// @[util.scala:104:23]\n assign next_uop_is_sfence = next_uop_out_is_sfence;\t// @[util.scala:104:23]\n assign next_uop_is_amo = next_uop_out_is_amo;\t// @[util.scala:104:23]\n assign next_uop_is_eret = next_uop_out_is_eret;\t// @[util.scala:104:23]\n assign next_uop_is_sys_pc2epc = next_uop_out_is_sys_pc2epc;\t// @[util.scala:104:23]\n assign next_uop_is_rocc = next_uop_out_is_rocc;\t// @[util.scala:104:23]\n assign next_uop_is_mov = next_uop_out_is_mov;\t// @[util.scala:104:23]\n assign next_uop_ftq_idx = next_uop_out_ftq_idx;\t// @[util.scala:104:23]\n assign next_uop_edge_inst = next_uop_out_edge_inst;\t// @[util.scala:104:23]\n assign next_uop_pc_lob = next_uop_out_pc_lob;\t// @[util.scala:104:23]\n assign next_uop_taken = next_uop_out_taken;\t// @[util.scala:104:23]\n assign next_uop_imm_rename = next_uop_out_imm_rename;\t// @[util.scala:104:23]\n assign next_uop_imm_sel = next_uop_out_imm_sel;\t// @[util.scala:104:23]\n assign next_uop_pimm = next_uop_out_pimm;\t// @[util.scala:104:23]\n assign next_uop_imm_packed = next_uop_out_imm_packed;\t// @[util.scala:104:23]\n assign next_uop_op1_sel = next_uop_out_op1_sel;\t// @[util.scala:104:23]\n assign next_uop_op2_sel = next_uop_out_op2_sel;\t// @[util.scala:104:23]\n assign next_uop_fp_ctrl_ldst = next_uop_out_fp_ctrl_ldst;\t// @[util.scala:104:23]\n assign next_uop_fp_ctrl_wen = next_uop_out_fp_ctrl_wen;\t// @[util.scala:104:23]\n assign next_uop_fp_ctrl_ren1 = next_uop_out_fp_ctrl_ren1;\t// @[util.scala:104:23]\n assign next_uop_fp_ctrl_ren2 = next_uop_out_fp_ctrl_ren2;\t// @[util.scala:104:23]\n assign next_uop_fp_ctrl_ren3 = next_uop_out_fp_ctrl_ren3;\t// @[util.scala:104:23]\n assign next_uop_fp_ctrl_swap12 = next_uop_out_fp_ctrl_swap12;\t// @[util.scala:104:23]\n assign next_uop_fp_ctrl_swap23 = next_uop_out_fp_ctrl_swap23;\t// @[util.scala:104:23]\n assign next_uop_fp_ctrl_typeTagIn = next_uop_out_fp_ctrl_typeTagIn;\t// @[util.scala:104:23]\n assign next_uop_fp_ctrl_typeTagOut = next_uop_out_fp_ctrl_typeTagOut;\t// @[util.scala:104:23]\n assign next_uop_fp_ctrl_fromint = next_uop_out_fp_ctrl_fromint;\t// @[util.scala:104:23]\n assign next_uop_fp_ctrl_toint = next_uop_out_fp_ctrl_toint;\t// @[util.scala:104:23]\n assign next_uop_fp_ctrl_fastpipe = next_uop_out_fp_ctrl_fastpipe;\t// @[util.scala:104:23]\n assign next_uop_fp_ctrl_fma = next_uop_out_fp_ctrl_fma;\t// @[util.scala:104:23]\n assign next_uop_fp_ctrl_div = next_uop_out_fp_ctrl_div;\t// @[util.scala:104:23]\n assign next_uop_fp_ctrl_sqrt = next_uop_out_fp_ctrl_sqrt;\t// @[util.scala:104:23]\n assign next_uop_fp_ctrl_wflags = next_uop_out_fp_ctrl_wflags;\t// @[util.scala:104:23]\n assign next_uop_fp_ctrl_vec = next_uop_out_fp_ctrl_vec;\t// @[util.scala:104:23]\n assign next_uop_rob_idx = next_uop_out_rob_idx;\t// @[util.scala:104:23]\n assign next_uop_ldq_idx = next_uop_out_ldq_idx;\t// @[util.scala:104:23]\n assign next_uop_stq_idx = next_uop_out_stq_idx;\t// @[util.scala:104:23]\n assign next_uop_rxq_idx = next_uop_out_rxq_idx;\t// @[util.scala:104:23]\n assign next_uop_pdst = next_uop_out_pdst;\t// @[util.scala:104:23]\n assign next_uop_prs1 = next_uop_out_prs1;\t// @[util.scala:104:23]\n assign next_uop_prs2 = next_uop_out_prs2;\t// @[util.scala:104:23]\n assign next_uop_prs3 = next_uop_out_prs3;\t// @[util.scala:104:23]\n assign next_uop_ppred = next_uop_out_ppred;\t// @[util.scala:104:23]\n assign next_uop_stale_pdst = next_uop_out_stale_pdst;\t// @[util.scala:104:23]\n assign next_uop_exception = next_uop_out_exception;\t// @[util.scala:104:23]\n assign next_uop_exc_cause = next_uop_out_exc_cause;\t// @[util.scala:104:23]\n assign next_uop_mem_cmd = next_uop_out_mem_cmd;\t// @[util.scala:104:23]\n assign next_uop_mem_size = next_uop_out_mem_size;\t// @[util.scala:104:23]\n assign next_uop_mem_signed = next_uop_out_mem_signed;\t// @[util.scala:104:23]\n assign next_uop_uses_ldq = next_uop_out_uses_ldq;\t// @[util.scala:104:23]\n assign next_uop_uses_stq = next_uop_out_uses_stq;\t// @[util.scala:104:23]\n assign next_uop_is_unique = next_uop_out_is_unique;\t// @[util.scala:104:23]\n assign next_uop_flush_on_commit = next_uop_out_flush_on_commit;\t// @[util.scala:104:23]\n assign next_uop_csr_cmd = next_uop_out_csr_cmd;\t// @[util.scala:104:23]\n assign next_uop_ldst_is_rs1 = next_uop_out_ldst_is_rs1;\t// @[util.scala:104:23]\n assign next_uop_ldst = next_uop_out_ldst;\t// @[util.scala:104:23]\n assign next_uop_lrs1 = next_uop_out_lrs1;\t// @[util.scala:104:23]\n assign next_uop_lrs2 = next_uop_out_lrs2;\t// @[util.scala:104:23]\n assign next_uop_lrs3 = next_uop_out_lrs3;\t// @[util.scala:104:23]\n assign next_uop_dst_rtype = next_uop_out_dst_rtype;\t// @[util.scala:104:23]\n assign next_uop_lrs1_rtype = next_uop_out_lrs1_rtype;\t// @[util.scala:104:23]\n assign next_uop_lrs2_rtype = next_uop_out_lrs2_rtype;\t// @[util.scala:104:23]\n assign next_uop_frs3_en = next_uop_out_frs3_en;\t// @[util.scala:104:23]\n assign next_uop_fcn_dw = next_uop_out_fcn_dw;\t// @[util.scala:104:23]\n assign next_uop_fcn_op = next_uop_out_fcn_op;\t// @[util.scala:104:23]\n assign next_uop_fp_val = next_uop_out_fp_val;\t// @[util.scala:104:23]\n assign next_uop_fp_rm = next_uop_out_fp_rm;\t// @[util.scala:104:23]\n assign next_uop_fp_typ = next_uop_out_fp_typ;\t// @[util.scala:104:23]\n assign next_uop_xcpt_pf_if = next_uop_out_xcpt_pf_if;\t// @[util.scala:104:23]\n assign next_uop_xcpt_ae_if = next_uop_out_xcpt_ae_if;\t// @[util.scala:104:23]\n assign next_uop_xcpt_ma_if = next_uop_out_xcpt_ma_if;\t// @[util.scala:104:23]\n assign next_uop_bp_debug_if = next_uop_out_bp_debug_if;\t// @[util.scala:104:23]\n assign next_uop_bp_xcpt_if = next_uop_out_bp_xcpt_if;\t// @[util.scala:104:23]\n assign next_uop_debug_fsrc = next_uop_out_debug_fsrc;\t// @[util.scala:104:23]\n assign next_uop_debug_tsrc = next_uop_out_debug_tsrc;\t// @[util.scala:104:23]\n wire [15:0] _next_uop_out_br_mask_T = ~io_brupdate_b1_resolve_mask_0;\t// @[util.scala:93:27]\n assign _next_uop_out_br_mask_T_1 = slot_uop_br_mask & _next_uop_out_br_mask_T;\t// @[util.scala:93:{25,27}]\n assign next_uop_out_br_mask = _next_uop_out_br_mask_T_1;\t// @[util.scala:93:25, :104:23]\n assign io_out_uop_inst_0 = next_uop_inst;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_debug_inst_0 = next_uop_debug_inst;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_is_rvc_0 = next_uop_is_rvc;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_debug_pc_0 = next_uop_debug_pc;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_iq_type_0_0 = next_uop_iq_type_0;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_iq_type_1_0 = next_uop_iq_type_1;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_iq_type_2_0 = next_uop_iq_type_2;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_iq_type_3_0 = next_uop_iq_type_3;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_fu_code_0_0 = next_uop_fu_code_0;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_fu_code_1_0 = next_uop_fu_code_1;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_fu_code_2_0 = next_uop_fu_code_2;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_fu_code_3_0 = next_uop_fu_code_3;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_fu_code_4_0 = next_uop_fu_code_4;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_fu_code_5_0 = next_uop_fu_code_5;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_fu_code_6_0 = next_uop_fu_code_6;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_fu_code_7_0 = next_uop_fu_code_7;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_fu_code_8_0 = next_uop_fu_code_8;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_fu_code_9_0 = next_uop_fu_code_9;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_iw_issued_0 = next_uop_iw_issued;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_iw_p1_speculative_child_0 = next_uop_iw_p1_speculative_child;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_iw_p2_speculative_child_0 = next_uop_iw_p2_speculative_child;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_iw_p1_bypass_hint_0 = next_uop_iw_p1_bypass_hint;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_iw_p2_bypass_hint_0 = next_uop_iw_p2_bypass_hint;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_iw_p3_bypass_hint_0 = next_uop_iw_p3_bypass_hint;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_dis_col_sel_0 = next_uop_dis_col_sel;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_br_mask_0 = next_uop_br_mask;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_br_tag_0 = next_uop_br_tag;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_br_type_0 = next_uop_br_type;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_is_sfb_0 = next_uop_is_sfb;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_is_fence_0 = next_uop_is_fence;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_is_fencei_0 = next_uop_is_fencei;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_is_sfence_0 = next_uop_is_sfence;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_is_amo_0 = next_uop_is_amo;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_is_eret_0 = next_uop_is_eret;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_is_sys_pc2epc_0 = next_uop_is_sys_pc2epc;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_is_rocc_0 = next_uop_is_rocc;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_is_mov_0 = next_uop_is_mov;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_ftq_idx_0 = next_uop_ftq_idx;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_edge_inst_0 = next_uop_edge_inst;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_pc_lob_0 = next_uop_pc_lob;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_taken_0 = next_uop_taken;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_imm_rename_0 = next_uop_imm_rename;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_imm_sel_0 = next_uop_imm_sel;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_pimm_0 = next_uop_pimm;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_imm_packed_0 = next_uop_imm_packed;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_op1_sel_0 = next_uop_op1_sel;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_op2_sel_0 = next_uop_op2_sel;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_fp_ctrl_ldst_0 = next_uop_fp_ctrl_ldst;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_fp_ctrl_wen_0 = next_uop_fp_ctrl_wen;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_fp_ctrl_ren1_0 = next_uop_fp_ctrl_ren1;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_fp_ctrl_ren2_0 = next_uop_fp_ctrl_ren2;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_fp_ctrl_ren3_0 = next_uop_fp_ctrl_ren3;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_fp_ctrl_swap12_0 = next_uop_fp_ctrl_swap12;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_fp_ctrl_swap23_0 = next_uop_fp_ctrl_swap23;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_fp_ctrl_typeTagIn_0 = next_uop_fp_ctrl_typeTagIn;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_fp_ctrl_typeTagOut_0 = next_uop_fp_ctrl_typeTagOut;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_fp_ctrl_fromint_0 = next_uop_fp_ctrl_fromint;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_fp_ctrl_toint_0 = next_uop_fp_ctrl_toint;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_fp_ctrl_fastpipe_0 = next_uop_fp_ctrl_fastpipe;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_fp_ctrl_fma_0 = next_uop_fp_ctrl_fma;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_fp_ctrl_div_0 = next_uop_fp_ctrl_div;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_fp_ctrl_sqrt_0 = next_uop_fp_ctrl_sqrt;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_fp_ctrl_wflags_0 = next_uop_fp_ctrl_wflags;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_fp_ctrl_vec_0 = next_uop_fp_ctrl_vec;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_rob_idx_0 = next_uop_rob_idx;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_ldq_idx_0 = next_uop_ldq_idx;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_stq_idx_0 = next_uop_stq_idx;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_rxq_idx_0 = next_uop_rxq_idx;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_pdst_0 = next_uop_pdst;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_prs1_0 = next_uop_prs1;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_prs2_0 = next_uop_prs2;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_prs3_0 = next_uop_prs3;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_ppred_0 = next_uop_ppred;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_prs1_busy_0 = next_uop_prs1_busy;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_prs2_busy_0 = next_uop_prs2_busy;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_prs3_busy_0 = next_uop_prs3_busy;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_ppred_busy_0 = next_uop_ppred_busy;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_stale_pdst_0 = next_uop_stale_pdst;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_exception_0 = next_uop_exception;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_exc_cause_0 = next_uop_exc_cause;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_mem_cmd_0 = next_uop_mem_cmd;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_mem_size_0 = next_uop_mem_size;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_mem_signed_0 = next_uop_mem_signed;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_uses_ldq_0 = next_uop_uses_ldq;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_uses_stq_0 = next_uop_uses_stq;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_is_unique_0 = next_uop_is_unique;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_flush_on_commit_0 = next_uop_flush_on_commit;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_csr_cmd_0 = next_uop_csr_cmd;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_ldst_is_rs1_0 = next_uop_ldst_is_rs1;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_ldst_0 = next_uop_ldst;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_lrs1_0 = next_uop_lrs1;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_lrs2_0 = next_uop_lrs2;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_lrs3_0 = next_uop_lrs3;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_dst_rtype_0 = next_uop_dst_rtype;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_lrs1_rtype_0 = next_uop_lrs1_rtype;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_lrs2_rtype_0 = next_uop_lrs2_rtype;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_frs3_en_0 = next_uop_frs3_en;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_fcn_dw_0 = next_uop_fcn_dw;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_fcn_op_0 = next_uop_fcn_op;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_fp_val_0 = next_uop_fp_val;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_fp_rm_0 = next_uop_fp_rm;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_fp_typ_0 = next_uop_fp_typ;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_xcpt_pf_if_0 = next_uop_xcpt_pf_if;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_xcpt_ae_if_0 = next_uop_xcpt_ae_if;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_xcpt_ma_if_0 = next_uop_xcpt_ma_if;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_bp_debug_if_0 = next_uop_bp_debug_if;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_bp_xcpt_if_0 = next_uop_bp_xcpt_if;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_debug_fsrc_0 = next_uop_debug_fsrc;\t// @[issue-slot.scala:49:7, :59:28]\n assign io_out_uop_debug_tsrc_0 = next_uop_debug_tsrc;\t// @[issue-slot.scala:49:7, :59:28]\n wire [15:0] _killed_T = io_brupdate_b1_mispredict_mask_0 & slot_uop_br_mask;\t// @[util.scala:126:51]\n wire _killed_T_1 = |_killed_T;\t// @[util.scala:126:{51,59}]\n wire killed = _killed_T_1 | io_kill_0;\t// @[util.scala:61:61, :126:59]\n wire _io_will_be_valid_T = ~killed;\t// @[util.scala:61:61]\n assign _io_will_be_valid_T_1 = next_valid & _io_will_be_valid_T;\t// @[issue-slot.scala:58:28, :65:{34,37}]\n assign io_will_be_valid_0 = _io_will_be_valid_T_1;\t// @[issue-slot.scala:49:7, :65:34]\n wire _slot_valid_T = ~killed;\t// @[util.scala:61:61]\n wire _slot_valid_T_1 = next_valid & _slot_valid_T;\t// @[issue-slot.scala:58:28, :74:{30,33}]"}}},{"rowIdx":587,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to the following Chisel files.\nFile Crossing.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.interrupts\n\nimport chisel3._\nimport chisel3.util._\nimport org.chipsalliance.cde.config._\nimport org.chipsalliance.diplomacy.lazymodule._\n\nimport freechips.rocketchip.util.{SynchronizerShiftReg, AsyncResetReg}\n\n@deprecated(\"IntXing does not ensure interrupt source is glitch free. Use IntSyncSource and IntSyncSink\", \"rocket-chip 1.2\")\nclass IntXing(sync: Int = 3)(implicit p: Parameters) extends LazyModule\n{\n val intnode = IntAdapterNode()\n\n lazy val module = new Impl\n class Impl extends LazyModuleImp(this) {\n (intnode.in zip intnode.out) foreach { case ((in, _), (out, _)) =>\n out := SynchronizerShiftReg(in, sync)\n }\n }\n}\n\nobject IntSyncCrossingSource\n{\n def apply(alreadyRegistered: Boolean = false)(implicit p: Parameters) =\n {\n val intsource = LazyModule(new IntSyncCrossingSource(alreadyRegistered))\n intsource.node\n }\n}\n\n\nclass IntSyncCrossingSource(alreadyRegistered: Boolean = false)(implicit p: Parameters) extends LazyModule\n{\n val node = IntSyncSourceNode(alreadyRegistered)\n\n lazy val module = if (alreadyRegistered) (new ImplRegistered) else (new Impl)\n\n class Impl extends LazyModuleImp(this) {\n def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0)\n override def desiredName = s\"IntSyncCrossingSource_n${node.out.size}x${outSize}\"\n (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>\n out.sync := AsyncResetReg(Cat(in.reverse)).asBools\n }\n }\n class ImplRegistered extends LazyRawModuleImp(this) {\n def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0)\n override def desiredName = s\"IntSyncCrossingSource_n${node.out.size}x${outSize}_Registered\"\n (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>\n out.sync := in\n }\n }\n}\n\n\nobject IntSyncCrossingSink\n{\n @deprecated(\"IntSyncCrossingSink which used the `sync` parameter to determine crossing type is deprecated. Use IntSyncAsyncCrossingSink, IntSyncRationalCrossingSink, or IntSyncSyncCrossingSink instead for > 1, 1, and 0 sync values respectively\", \"rocket-chip 1.2\")\n def apply(sync: Int = 3)(implicit p: Parameters) =\n {\n val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync))\n intsink.node\n }\n}\n\n\nclass IntSyncAsyncCrossingSink(sync: Int = 3)(implicit p: Parameters) extends LazyModule\n{\n val node = IntSyncSinkNode(sync)\n\n lazy val module = new Impl\n class Impl extends LazyModuleImp(this) {\n override def desiredName = s\"IntSyncAsyncCrossingSink_n${node.out.size}x${node.out.head._1.size}\"\n (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>\n out := SynchronizerShiftReg(in.sync, sync)\n }\n }\n}\n\nobject IntSyncAsyncCrossingSink\n{\n def apply(sync: Int = 3)(implicit p: Parameters) =\n {\n val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync))\n intsink.node\n }\n}\n\nclass IntSyncSyncCrossingSink()(implicit p: Parameters) extends LazyModule\n{\n val node = IntSyncSinkNode(0)\n\n lazy val module = new Impl\n class Impl extends LazyRawModuleImp(this) {\n def outSize = node.out.headOption.map(_._1.size).getOrElse(0)\n override def desiredName = s\"IntSyncSyncCrossingSink_n${node.out.size}x${outSize}\"\n (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>\n out := in.sync\n }\n }\n}\n\nobject IntSyncSyncCrossingSink\n{\n def apply()(implicit p: Parameters) =\n {\n val intsink = LazyModule(new IntSyncSyncCrossingSink())\n intsink.node\n }\n}\n\nclass IntSyncRationalCrossingSink()(implicit p: Parameters) extends LazyModule\n{\n val node = IntSyncSinkNode(1)\n\n lazy val module = new Impl\n class Impl extends LazyModuleImp(this) {\n def outSize = node.out.headOption.map(_._1.size).getOrElse(0)\n override def desiredName = s\"IntSyncRationalCrossingSink_n${node.out.size}x${outSize}\"\n (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>\n out := RegNext(in.sync)\n }\n }\n}\n\nobject IntSyncRationalCrossingSink\n{\n def apply()(implicit p: Parameters) =\n {\n val intsink = LazyModule(new IntSyncRationalCrossingSink())\n intsink.node\n }\n}\nFile LazyModuleImp.scala:\npackage org.chipsalliance.diplomacy.lazymodule\n\nimport chisel3.{withClockAndReset, Module, RawModule, Reset, _}\nimport chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}\nimport firrtl.passes.InlineAnnotation\nimport org.chipsalliance.cde.config.Parameters\nimport org.chipsalliance.diplomacy.nodes.Dangle\n\nimport scala.collection.immutable.SortedMap\n\n/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].\n *\n * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.\n */\nsealed trait LazyModuleImpLike extends RawModule {\n\n /** [[LazyModule]] that contains this instance. */\n val wrapper: LazyModule\n\n /** IOs that will be automatically \"punched\" for this instance. */\n val auto: AutoBundle\n\n /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */\n protected[diplomacy] val dangles: Seq[Dangle]\n\n // [[wrapper.module]] had better not be accessed while LazyModules are still being built!\n require(\n LazyModule.scope.isEmpty,\n s\"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}\"\n )\n\n /** Set module name. Defaults to the containing LazyModule's desiredName. */\n override def desiredName: String = wrapper.desiredName\n\n suggestName(wrapper.suggestedName)\n\n /** [[Parameters]] for chisel [[Module]]s. */\n implicit val p: Parameters = wrapper.p\n\n /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and\n * submodules.\n */\n protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {\n // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],\n // 2. return [[Dangle]]s from each module.\n val childDangles = wrapper.children.reverse.flatMap { c =>\n implicit val sourceInfo: SourceInfo = c.info\n c.cloneProto.map { cp =>\n // If the child is a clone, then recursively set cloneProto of its children as well\n def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {\n require(bases.size == clones.size)\n (bases.zip(clones)).map { case (l, r) =>\n require(l.getClass == r.getClass, s\"Cloned children class mismatch ${l.name} != ${r.name}\")\n l.cloneProto = Some(r)\n assignCloneProtos(l.children, r.children)\n }\n }\n assignCloneProtos(c.children, cp.children)\n // Clone the child module as a record, and get its [[AutoBundle]]\n val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)\n val clonedAuto = clone(\"auto\").asInstanceOf[AutoBundle]\n // Get the empty [[Dangle]]'s of the cloned child\n val rawDangles = c.cloneDangles()\n require(rawDangles.size == clonedAuto.elements.size)\n // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s\n val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }\n dangles\n }.getOrElse {\n // For non-clones, instantiate the child module\n val mod = try {\n Module(c.module)\n } catch {\n case e: ChiselException => {\n println(s\"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}\")\n throw e\n }\n }\n mod.dangles\n }\n }\n\n // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].\n // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.\n val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())\n // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]\n val allDangles = nodeDangles ++ childDangles\n // Group [[allDangles]] by their [[source]].\n val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)\n // For each [[source]] set of [[Dangle]]s of size 2, ensure that these\n // can be connected as a source-sink pair (have opposite flipped value).\n // Make the connection and mark them as [[done]].\n val done = Set() ++ pairing.values.filter(_.size == 2).map {\n case Seq(a, b) =>\n require(a.flipped != b.flipped)\n // @todo <> in chisel3 makes directionless connection.\n if (a.flipped) {\n a.data <> b.data\n } else {\n b.data <> a.data\n }\n a.source\n case _ => None\n }\n // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.\n val forward = allDangles.filter(d => !done(d.source))\n // Generate [[AutoBundle]] IO from [[forward]].\n val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))\n // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]\n val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>\n if (d.flipped) {\n d.data <> io\n } else {\n io <> d.data\n }\n d.copy(dataOpt = Some(io), name = wrapper.suggestedName + \"_\" + d.name)\n }\n // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].\n wrapper.inModuleBody.reverse.foreach {\n _()\n }\n\n if (wrapper.shouldBeInlined) {\n chisel3.experimental.annotate(new ChiselAnnotation {\n def toFirrtl = InlineAnnotation(toNamed)\n })\n }\n\n // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].\n (auto, dangles)\n }\n}\n\n/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].\n *\n * @param wrapper\n * the [[LazyModule]] from which the `.module` call is being made.\n */\nclass LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {\n\n /** Instantiate hardware of this `Module`. */\n val (auto, dangles) = instantiate()\n}\n\n/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].\n *\n * @param wrapper\n * the [[LazyModule]] from which the `.module` call is being made.\n */\nclass LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {\n // These wires are the default clock+reset for all LazyModule children.\n // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the\n // [[LazyRawModuleImp]] children.\n // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.\n /** drive clock explicitly. */\n val childClock: Clock = Wire(Clock())\n\n /** drive reset explicitly. */\n val childReset: Reset = Wire(Reset())\n // the default is that these are disabled\n childClock := false.B.asClock\n childReset := chisel3.DontCare\n\n def provideImplicitClockToLazyChildren: Boolean = false\n val (auto, dangles) =\n if (provideImplicitClockToLazyChildren) {\n withClockAndReset(childClock, childReset) { instantiate() }\n } else {\n instantiate()\n }\n}\nFile MixedNode.scala:\npackage org.chipsalliance.diplomacy.nodes\n\nimport chisel3.{Data, DontCare, Wire}\nimport chisel3.experimental.SourceInfo\nimport org.chipsalliance.cde.config.{Field, Parameters}\n\nimport org.chipsalliance.diplomacy.ValName\nimport org.chipsalliance.diplomacy.sourceLine\n\n/** One side metadata of a [[Dangle]].\n *\n * Describes one side of an edge going into or out of a [[BaseNode]].\n *\n * @param serial\n * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.\n * @param index\n * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.\n */\ncase class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {\n\n import scala.math.Ordered.orderingToOrdered\n\n def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))\n}\n\n/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]\n * connects.\n *\n * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,\n * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].\n *\n * @param source\n * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within\n * that [[BaseNode]].\n * @param sink\n * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that\n * [[BaseNode]].\n * @param flipped\n * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to\n * `danglesIn`.\n * @param dataOpt\n * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module\n */\ncase class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {\n def data = dataOpt.get\n}\n\n/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often\n * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually\n * implement the protocol.\n */\ncase class Edges[EI, EO](in: Seq[EI], out: Seq[EO])\n\n/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */\ncase object MonitorsEnabled extends Field[Boolean](true)\n\n/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.\n *\n * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but\n * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink\n * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the\n * [[LazyModule]].\n */\ncase object RenderFlipped extends Field[Boolean](false)\n\n/** The sealed node class in the package, all node are derived from it.\n *\n * @param inner\n * Sink interface implementation.\n * @param outer\n * Source interface implementation.\n * @param valName\n * val name of this node.\n * @tparam DI\n * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters\n * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected\n * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port\n * parameters.\n * @tparam UI\n * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing\n * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.\n * @tparam EI\n * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers\n * specified for a sink according to protocol.\n * @tparam BI\n * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.\n * It should extends from [[chisel3.Data]], which represents the real hardware.\n * @tparam DO\n * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters\n * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.\n * @tparam UO\n * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing\n * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].\n * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.\n * @tparam EO\n * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers\n * specified for a source according to protocol.\n * @tparam BO\n * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source\n * interface. It should extends from [[chisel3.Data]], which represents the real hardware.\n *\n * @note\n * Call Graph of [[MixedNode]]\n * - line `─`: source is process by a function and generate pass to others\n * - Arrow `→`: target of arrow is generated by source\n *\n * {{{\n * (from the other node)\n * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐\n * ↓ │\n * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │\n * [[InwardNode.accPI]] │ │ │\n * │ │ (based on protocol) │\n * │ │ [[MixedNode.inner.edgeI]] │\n * │ │ ↓ │\n * ↓ │ │ │\n * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │\n * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │\n * │ │ ↑ │ │ │\n * │ │ │ [[OutwardNode.doParams]] │ │\n * │ │ │ (from the other node) │ │\n * │ │ │ │ │ │\n * │ │ │ │ │ │\n * │ │ │ └────────┬──────────────┤ │\n * │ │ │ │ │ │\n * │ │ │ │ (based on protocol) │\n * │ │ │ │ [[MixedNode.inner.edgeI]] │\n * │ │ │ │ │ │\n * │ │ (from the other node) │ ↓ │\n * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │\n * │ ↑ ↑ │ │ ↓ │\n * │ │ │ │ │ [[MixedNode.in]] │\n * │ │ │ │ ↓ ↑ │\n * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │\n * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │\n * │ │ │ [[MixedNode.bundleOut]]─┐ │ │\n * │ │ │ ↑ ↓ │ │\n * │ │ │ │ [[MixedNode.out]] │ │\n * │ ↓ ↓ │ ↑ │ │\n * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │\n * │ │ (from the other node) ↑ │ │\n * │ │ │ │ │ │\n * │ │ │ [[MixedNode.outer.edgeO]] │ │\n * │ │ │ (based on protocol) │ │\n * │ │ │ │ │ │\n * │ │ │ ┌────────────────────────────────────────┤ │ │\n * │ │ │ │ │ │ │\n * │ │ │ │ │ │ │\n * │ │ │ │ │ │ │\n * (immobilize after elaboration)│ ↓ │ │ │ │\n * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │\n * ↑ (inward port from [[OutwardNode]]) │ │ │ │\n * │ ┌─────────────────────────────────────────┤ │ │ │\n * │ │ │ │ │ │\n * │ │ │ │ │ │\n * [[OutwardNode.accPO]] │ ↓ │ │ │\n * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │\n * │ ↑ │ │\n * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │\n * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘\n * }}}\n */\nabstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](\n val inner: InwardNodeImp[DI, UI, EI, BI],\n val outer: OutwardNodeImp[DO, UO, EO, BO]\n)(\n implicit valName: ValName)\n extends BaseNode\n with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]\n with InwardNode[DI, UI, BI]\n with OutwardNode[DO, UO, BO] {\n // Generate a [[NodeHandle]] with inward and outward node are both this node.\n val inward = this\n val outward = this\n\n /** Debug info of nodes binding. */\n def bindingInfo: String = s\"\"\"$iBindingInfo\n |$oBindingInfo\n |\"\"\".stripMargin\n\n /** Debug info of ports connecting. */\n def connectedPortsInfo: String = s\"\"\"${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(\",\")}]\n |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(\",\")}]\n |\"\"\".stripMargin\n\n /** Debug info of parameters propagations. */\n def parametersInfo: String = s\"\"\"${doParams.size} downstream outward parameters: [${doParams.mkString(\",\")}]\n |${uoParams.size} upstream outward parameters: [${uoParams.mkString(\",\")}]\n |${diParams.size} downstream inward parameters: [${diParams.mkString(\",\")}]\n |${uiParams.size} upstream inward parameters: [${uiParams.mkString(\",\")}]\n |\"\"\".stripMargin\n\n /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and\n * [[MixedNode.iPortMapping]].\n *\n * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward\n * stars and outward stars.\n *\n * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type\n * of node.\n *\n * @param iKnown\n * Number of known-size ([[BIND_ONCE]]) input bindings.\n * @param oKnown\n * Number of known-size ([[BIND_ONCE]]) output bindings.\n * @param iStar\n * Number of unknown size ([[BIND_STAR]]) input bindings.\n * @param oStar\n * Number of unknown size ([[BIND_STAR]]) output bindings.\n * @return\n * A Tuple of the resolved number of input and output connections.\n */\n protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)\n\n /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output\n * ports.\n *\n * @param n\n * The size of the output sequence to generate.\n * @param p\n * Sequence of downward-flowing input parameters of this node.\n * @return\n * A `n`-sized sequence of downward-flowing output edge parameters.\n */\n protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]\n\n /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].\n *\n * @param n\n * Size of the output sequence.\n * @param p\n * Upward-flowing output edge parameters.\n * @return\n * A n-sized sequence of upward-flowing input edge parameters.\n */\n protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]\n\n /** @return\n * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with\n * [[BIND_STAR]].\n */\n protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)\n\n /** @return\n * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of\n * output bindings bound with [[BIND_STAR]].\n */\n protected[diplomacy] lazy val sourceCard: Int =\n iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)\n\n /** @return list of nodes involved in flex bindings with this node. */\n protected[diplomacy] lazy val flexes: Seq[BaseNode] =\n oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)\n\n /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin\n * greedily taking up the remaining connections.\n *\n * @return\n * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return\n * value is not relevant.\n */\n protected[diplomacy] lazy val flexOffset: Int = {\n\n /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex\n * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a\n * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of\n * each node in the current set and decide whether they should be added to the set or not.\n *\n * @return\n * the mapping of [[BaseNode]] indexed by their serial numbers.\n */\n def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {\n if (visited.contains(v.serial) || !v.flexibleArityDirection) {\n visited\n } else {\n v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))\n }\n }\n\n /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.\n *\n * @example\n * {{{\n * a :*=* b :*=* c\n * d :*=* b\n * e :*=* f\n * }}}\n *\n * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`\n */\n val flexSet = DFS(this, Map()).values\n\n /** The total number of :*= operators where we're on the left. */\n val allSink = flexSet.map(_.sinkCard).sum\n\n /** The total number of :=* operators used when we're on the right. */\n val allSource = flexSet.map(_.sourceCard).sum\n\n require(\n allSink == 0 || allSource == 0,\n s\"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction.\"\n )\n allSink - allSource\n }\n\n /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */\n protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {\n if (flexibleArityDirection) flexOffset\n else if (n.flexibleArityDirection) n.flexOffset\n else 0\n }\n\n /** For a node which is connected between two nodes, select the one that will influence the direction of the flex\n * resolution.\n */\n protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {\n val dir = edgeArityDirection(n)\n if (dir < 0) l\n else if (dir > 0) r\n else 1\n }\n\n /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */\n private var starCycleGuard = false\n\n /** Resolve all the star operators into concrete indicies. As connections are being made, some may be \"star\"\n * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also\n * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct\n * edge parameters and later build up correct bundle connections.\n *\n * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding\n * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort\n * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=\n * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`\n */\n protected[diplomacy] lazy val (\n oPortMapping: Seq[(Int, Int)],\n iPortMapping: Seq[(Int, Int)],\n oStar: Int,\n iStar: Int\n ) = {\n try {\n if (starCycleGuard) throw StarCycleException()\n starCycleGuard = true\n // For a given node N...\n // Number of foo :=* N\n // + Number of bar :=* foo :*=* N\n val oStars = oBindings.count { case (_, n, b, _, _) =>\n b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)\n }\n // Number of N :*= foo\n // + Number of N :*=* foo :*= bar\n val iStars = iBindings.count { case (_, n, b, _, _) =>\n b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)\n }\n // 1 for foo := N\n // + bar.iStar for bar :*= foo :*=* N\n // + foo.iStar for foo :*= N\n // + 0 for foo :=* N\n val oKnown = oBindings.map { case (_, n, b, _, _) =>\n b match {\n case BIND_ONCE => 1\n case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)\n case BIND_QUERY => n.iStar\n case BIND_STAR => 0\n }\n }.sum\n // 1 for N := foo\n // + bar.oStar for N :*=* foo :=* bar\n // + foo.oStar for N :=* foo\n // + 0 for N :*= foo\n val iKnown = iBindings.map { case (_, n, b, _, _) =>\n b match {\n case BIND_ONCE => 1\n case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)\n case BIND_QUERY => n.oStar\n case BIND_STAR => 0\n }\n }.sum\n // Resolve star depends on the node subclass to implement the algorithm for this.\n val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)\n // Cumulative list of resolved outward binding range starting points\n val oSum = oBindings.map { case (_, n, b, _, _) =>\n b match {\n case BIND_ONCE => 1\n case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)\n case BIND_QUERY => n.iStar\n case BIND_STAR => oStar\n }\n }.scanLeft(0)(_ + _)\n // Cumulative list of resolved inward binding range starting points\n val iSum = iBindings.map { case (_, n, b, _, _) =>\n b match {\n case BIND_ONCE => 1\n case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)\n case BIND_QUERY => n.oStar\n case BIND_STAR => iStar\n }\n }.scanLeft(0)(_ + _)\n // Create ranges for each binding based on the running sums and return\n // those along with resolved values for the star operations.\n (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)\n } catch {\n case c: StarCycleException => throw c.copy(loop = context +: c.loop)\n }\n }\n\n /** Sequence of inward ports.\n *\n * This should be called after all star bindings are resolved.\n *\n * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.\n * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this\n * connection was made in the source code.\n */\n protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =\n oBindings.flatMap { case (i, n, _, p, s) =>\n // for each binding operator in this node, look at what it connects to\n val (start, end) = n.iPortMapping(i)\n (start until end).map { j => (j, n, p, s) }\n }\n\n /** Sequence of outward ports.\n *\n * This should be called after all star bindings are resolved.\n *\n * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of\n * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection\n * was made in the source code.\n */\n protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =\n iBindings.flatMap { case (i, n, _, p, s) =>\n // query this port index range of this node in the other side of node.\n val (start, end) = n.oPortMapping(i)\n (start until end).map { j => (j, n, p, s) }\n }\n\n // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree\n // Thus, there must exist an Eulerian path and the below algorithms terminate\n @scala.annotation.tailrec\n private def oTrace(\n tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)\n ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {\n case (i, n, p, s) => n.iForward(i) match {\n case None => (i, n, p, s)\n case Some((j, m)) => oTrace((j, m, p, s))\n }\n }\n\n @scala.annotation.tailrec\n private def iTrace(\n tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)\n ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {\n case (i, n, p, s) => n.oForward(i) match {\n case None => (i, n, p, s)\n case Some((j, m)) => iTrace((j, m, p, s))\n }\n }\n\n /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.\n *\n * Each Port is a tuple of:\n * - Numeric index of this binding in the [[InwardNode]] on the other end.\n * - [[InwardNode]] on the other end of this binding.\n * - A view of [[Parameters]] where the binding occurred.\n * - [[SourceInfo]] for source-level error reporting.\n */\n lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)\n\n /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.\n *\n * Each Port is a tuple of:\n * - numeric index of this binding in [[OutwardNode]] on the other end.\n * - [[OutwardNode]] on the other end of this binding.\n * - a view of [[Parameters]] where the binding occurred.\n * - [[SourceInfo]] for source-level error reporting.\n */\n lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)\n\n private var oParamsCycleGuard = false\n protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }\n protected[diplomacy] lazy val doParams: Seq[DO] = {\n try {\n if (oParamsCycleGuard) throw DownwardCycleException()\n oParamsCycleGuard = true\n val o = mapParamsD(oPorts.size, diParams)\n require(\n o.size == oPorts.size,\n s\"\"\"Diplomacy has detected a problem with your graph:\n |At the following node, the number of outward ports should equal the number of produced outward parameters.\n |$context\n |$connectedPortsInfo\n |Downstreamed inward parameters: [${diParams.mkString(\",\")}]\n |Produced outward parameters: [${o.mkString(\",\")}]\n |\"\"\".stripMargin\n )\n o.map(outer.mixO(_, this))\n } catch {\n case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)\n }\n }\n\n private var iParamsCycleGuard = false\n protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }\n protected[diplomacy] lazy val uiParams: Seq[UI] = {\n try {\n if (iParamsCycleGuard) throw UpwardCycleException()\n iParamsCycleGuard = true\n val i = mapParamsU(iPorts.size, uoParams)\n require(\n i.size == iPorts.size,\n s\"\"\"Diplomacy has detected a problem with your graph:\n |At the following node, the number of inward ports should equal the number of produced inward parameters.\n |$context\n |$connectedPortsInfo\n |Upstreamed outward parameters: [${uoParams.mkString(\",\")}]\n |Produced inward parameters: [${i.mkString(\",\")}]\n |\"\"\".stripMargin\n )\n i.map(inner.mixI(_, this))\n } catch {\n case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)\n }\n }\n\n /** Outward edge parameters. */\n protected[diplomacy] lazy val edgesOut: Seq[EO] =\n (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }\n\n /** Inward edge parameters. */\n protected[diplomacy] lazy val edgesIn: Seq[EI] =\n (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }\n\n /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.\n *\n * If you need to access to the edges of a foreign Node, use this method (in/out create bundles).\n */\n lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)\n\n /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */\n protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>\n val x = Wire(outer.bundleO(e)).suggestName(s\"${valName.value}Out\")\n // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,\n // In the future, we should add an option to decide whether allowing unconnected in the LazyModule\n x := DontCare\n x\n }\n\n /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */\n protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>\n val x = Wire(inner.bundleI(e)).suggestName(s\"${valName.value}In\")\n // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,\n // In the future, we should add an option to decide whether allowing unconnected in the LazyModule\n x := DontCare\n x\n }\n\n private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>\n Dangle(\n source = HalfEdge(serial, i),\n sink = HalfEdge(n.serial, j),\n flipped = false,\n name = wirePrefix + \"out\",\n dataOpt = None\n )\n }\n private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>\n Dangle(\n source = HalfEdge(n.serial, j),\n sink = HalfEdge(serial, i),\n flipped = true,\n name = wirePrefix + \"in\",\n dataOpt = None\n )\n }\n\n /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */\n protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>\n d.copy(dataOpt = Some(bundleOut(i)))\n }\n\n /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */\n protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>\n d.copy(dataOpt = Some(bundleIn(i)))\n }\n\n private[diplomacy] var instantiated = false\n\n /** Gather Bundle and edge parameters of outward ports.\n *\n * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within\n * [[LazyModuleImp]] code or after its instantiation has completed.\n */\n def out: Seq[(BO, EO)] = {\n require(\n instantiated,\n s\"$name.out should not be called until after instantiation of its parent LazyModule.module has begun\"\n )\n bundleOut.zip(edgesOut)\n }\n\n /** Gather Bundle and edge parameters of inward ports.\n *\n * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within\n * [[LazyModuleImp]] code or after its instantiation has completed.\n */\n def in: Seq[(BI, EI)] = {\n require(\n instantiated,\n s\"$name.in should not be called until after instantiation of its parent LazyModule.module has begun\"\n )\n bundleIn.zip(edgesIn)\n }\n\n /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,\n * instantiate monitors on all input ports if appropriate, and return all the dangles of this node.\n */\n protected[diplomacy] def instantiate(): Seq[Dangle] = {\n instantiated = true\n if (!circuitIdentity) {\n (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }\n }\n danglesOut ++ danglesIn\n }\n\n protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn\n\n /** Connects the outward part of a node with the inward part of this node. */\n protected[diplomacy] def bind(\n h: OutwardNode[DI, UI, BI],\n binding: NodeBinding\n )(\n implicit p: Parameters,\n sourceInfo: SourceInfo\n ): Unit = {\n val x = this // x := y\n val y = h\n sourceLine(sourceInfo, \" at \", \"\")\n val i = x.iPushed\n val o = y.oPushed\n y.oPush(\n i,\n x,\n binding match {\n case BIND_ONCE => BIND_ONCE\n case BIND_FLEX => BIND_FLEX\n case BIND_STAR => BIND_QUERY\n case BIND_QUERY => BIND_STAR\n }\n )\n x.iPush(o, y, binding)\n }\n\n /* Metadata for printing the node graph. */\n def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>\n val re = inner.render(e)\n (n, re.copy(flipped = re.flipped != p(RenderFlipped)))\n }\n\n /** Metadata for printing the node graph */\n def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }\n}\nFile AsyncResetReg.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3._\n\n/** This black-boxes an Async Reset\n * (or Set)\n * Register.\n * \n * Because Chisel doesn't support\n * parameterized black boxes, \n * we unfortunately have to \n * instantiate a number of these.\n * \n * We also have to hard-code the set/\n * reset behavior.\n * \n * Do not confuse an asynchronous\n * reset signal with an asynchronously\n * reset reg. You should still \n * properly synchronize your reset \n * deassertion.\n * \n * @param d Data input\n * @param q Data Output\n * @param clk Clock Input\n * @param rst Reset Input\n * @param en Write Enable Input\n * \n */\n\nclass AsyncResetReg(resetValue: Int = 0) extends RawModule {\n val io = IO(new Bundle {\n val d = Input(Bool())\n val q = Output(Bool())\n val en = Input(Bool())\n\n val clk = Input(Clock())\n val rst = Input(Reset())\n })\n\n val reg = withClockAndReset(io.clk, io.rst.asAsyncReset)(RegInit(resetValue.U(1.W)))\n when (io.en) {\n reg := io.d\n }\n io.q := reg\n}\n\nclass SimpleRegIO(val w: Int) extends Bundle{\n val d = Input(UInt(w.W))\n val q = Output(UInt(w.W))\n val en = Input(Bool())\n}\n\nclass AsyncResetRegVec(val w: Int, val init: BigInt) extends Module {\n override def desiredName = s\"AsyncResetRegVec_w${w}_i${init}\"\n\n val io = IO(new SimpleRegIO(w))\n\n val reg = withReset(reset.asAsyncReset)(RegInit(init.U(w.W)))\n when (io.en) {\n reg := io.d\n }\n io.q := reg\n}\n\nobject AsyncResetReg {\n // Create Single Registers\n def apply(d: Bool, clk: Clock, rst: Bool, init: Boolean, name: Option[String]): Bool = {\n val reg = Module(new AsyncResetReg(if (init) 1 else 0))\n reg.io.d := d\n reg.io.clk := clk\n reg.io.rst := rst\n reg.io.en := true.B\n name.foreach(reg.suggestName(_))\n reg.io.q\n }\n\n def apply(d: Bool, clk: Clock, rst: Bool): Bool = apply(d, clk, rst, false, None)\n def apply(d: Bool, clk: Clock, rst: Bool, name: String): Bool = apply(d, clk, rst, false, Some(name))\n\n // Create Vectors of Registers\n def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: Option[String] = None): UInt = {\n val w = updateData.getWidth max resetData.bitLength\n val reg = Module(new AsyncResetRegVec(w, resetData))\n name.foreach(reg.suggestName(_))\n reg.io.d := updateData\n reg.io.en := enable\n reg.io.q\n }\n def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: String): UInt = apply(updateData,\n resetData, enable, Some(name))\n\n\n def apply(updateData: UInt, resetData: BigInt): UInt = apply(updateData, resetData, enable = true.B)\n def apply(updateData: UInt, resetData: BigInt, name: String): UInt = apply(updateData, resetData, enable = true.B, Some(name))\n\n def apply(updateData: UInt, enable: Bool): UInt = apply(updateData, resetData=BigInt(0), enable)\n def apply(updateData: UInt, enable: Bool, name: String): UInt = apply(updateData, resetData = BigInt(0), enable, Some(name))\n\n def apply(updateData: UInt): UInt = apply(updateData, resetData = BigInt(0), enable = true.B)\n def apply(updateData: UInt, name:String): UInt = apply(updateData, resetData = BigInt(0), enable = true.B, Some(name))\n}\n"},"response":{"kind":"string","value":"module IntSyncCrossingSource_n1x2_13(\t// @[Crossing.scala:41:9]\n input clock,\t// @[Crossing.scala:41:9]\n input reset,\t// @[Crossing.scala:41:9]\n input auto_in_0,\t// @[LazyModuleImp.scala:107:25]\n input auto_in_1,\t// @[LazyModuleImp.scala:107:25]\n output auto_out_sync_0,\t// @[LazyModuleImp.scala:107:25]\n output auto_out_sync_1\t// @[LazyModuleImp.scala:107:25]\n);\n\n wire [1:0] _reg_io_q;\t// @[AsyncResetReg.scala:86:21]\n wire auto_in_0_0 = auto_in_0;\t// @[Crossing.scala:41:9]\n wire auto_in_1_0 = auto_in_1;\t// @[Crossing.scala:41:9]\n wire nodeIn_0 = auto_in_0_0;\t// @[Crossing.scala:41:9]\n wire nodeIn_1 = auto_in_1_0;\t// @[Crossing.scala:41:9]\n wire nodeOut_sync_0;\t// @[MixedNode.scala:542:17]\n wire nodeOut_sync_1;\t// @[MixedNode.scala:542:17]\n wire auto_out_sync_0_0;\t// @[Crossing.scala:41:9]\n wire auto_out_sync_1_0;\t// @[Crossing.scala:41:9]\n assign auto_out_sync_0_0 = nodeOut_sync_0;\t// @[Crossing.scala:41:9]\n assign auto_out_sync_1_0 = nodeOut_sync_1;\t// @[Crossing.scala:41:9]\n assign nodeOut_sync_0 = _reg_io_q[0];\t// @[AsyncResetReg.scala:86:21]\n assign nodeOut_sync_1 = _reg_io_q[1];\t// @[AsyncResetReg.scala:86:21]\n AsyncResetRegVec_w2_i0_13 reg_0 (\t// @[AsyncResetReg.scala:86:21]\n .clock (clock),\n .reset (reset),\n .io_d ({nodeIn_1, nodeIn_0}),\t// @[Crossing.scala:45:36]\n .io_q (_reg_io_q)\n );\t// @[AsyncResetReg.scala:86:21]\n assign auto_out_sync_0 = auto_out_sync_0_0;\t// @[Crossing.scala:41:9]\n assign auto_out_sync_1 = auto_out_sync_1_0;\t// @[Crossing.scala:41:9]\nendmodule"}}},{"rowIdx":588,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to the following Chisel files.\nFile SynchronizerReg.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3._\nimport chisel3.util.{RegEnable, Cat}\n\n/** These wrap behavioral\n * shift and next registers into specific modules to allow for\n * backend flows to replace or constrain\n * them properly when used for CDC synchronization,\n * rather than buffering.\n * \n * \n * These are built up of *ResetSynchronizerPrimitiveShiftReg,\n * intended to be replaced by the integrator's metastable flops chains or replaced\n * at this level if they have a multi-bit wide synchronizer primitive.\n * The different types vary in their reset behavior:\n * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin\n * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep\n * 1-bit-wide shift registers.\n * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg\n * \n * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.\n * \n * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross\n * Clock Domains.\n*/\n\nobject SynchronizerResetType extends Enumeration {\n val NonSync, Inferred, Sync, Async = Value\n}\n\n\n// Note: this should not be used directly.\n// Use the companion object to generate this with the correct reset type mixin.\nprivate class SynchronizerPrimitiveShiftReg(\n sync: Int,\n init: Boolean,\n resetType: SynchronizerResetType.Value)\n extends AbstractPipelineReg(1) {\n\n val initInt = if (init) 1 else 0\n val initPostfix = resetType match {\n case SynchronizerResetType.NonSync => \"\"\n case _ => s\"_i${initInt}\"\n }\n override def desiredName = s\"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}\"\n\n val chain = List.tabulate(sync) { i =>\n val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)\n reg.suggestName(s\"sync_$i\")\n }\n chain.last := io.d.asBool\n\n (chain.init zip chain.tail).foreach { case (sink, source) =>\n sink := source\n }\n io.q := chain.head.asUInt\n}\n\nprivate object SynchronizerPrimitiveShiftReg {\n def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {\n val gen: () => SynchronizerPrimitiveShiftReg = resetType match {\n case SynchronizerResetType.NonSync =>\n () => new SynchronizerPrimitiveShiftReg(sync, init, resetType)\n case SynchronizerResetType.Async =>\n () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset\n case SynchronizerResetType.Sync =>\n () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset\n case SynchronizerResetType.Inferred =>\n () => new SynchronizerPrimitiveShiftReg(sync, init, resetType)\n }\n AbstractPipelineReg(gen(), in)\n }\n}\n\n// Note: This module may end up with a non-AsyncReset type reset.\n// But the Primitives within will always have AsyncReset type.\nclass AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)\n extends AbstractPipelineReg(w) {\n require(sync > 1, s\"Sync must be greater than 1, not ${sync}.\")\n override def desiredName = s\"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}\"\n val output = Seq.tabulate(w) { i =>\n val initBit = ((init >> i) & 1) > 0\n withReset(reset.asAsyncReset){\n SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)\n }\n }\n io.q := Cat(output.reverse)\n}\n\nobject AsyncResetSynchronizerShiftReg {\n def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =\n AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)\n\n def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =\n apply (in, sync, 0, name)\n\n def apply [T <: Data](in: T, sync: Int): T =\n apply (in, sync, 0, None)\n\n def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =\n apply(in, sync, init.litValue.toInt, name)\n\n def apply [T <: Data](in: T, sync: Int, init: T): T =\n apply (in, sync, init.litValue.toInt, None)\n}\n\n// Note: This module may end up with a non-Bool type reset.\n// But the Primitives within will always have Bool reset type.\n@deprecated(\"SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.\", \"rocket-chip 1.2\")\nclass SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {\n require(sync > 1, s\"Sync must be greater than 1, not ${sync}.\")\n override def desiredName = s\"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}\"\n val output = Seq.tabulate(w) { i =>\n val initBit = ((init >> i) & 1) > 0\n withReset(reset.asBool){\n SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)\n }\n }\n io.q := Cat(output.reverse)\n}\n\nobject SyncResetSynchronizerShiftReg {\n def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =\n if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)\n\n def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =\n apply (in, sync, 0, name)\n\n def apply [T <: Data](in: T, sync: Int): T =\n apply (in, sync, 0, None)\n\n def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =\n apply(in, sync, init.litValue.toInt, name)\n\n def apply [T <: Data](in: T, sync: Int, init: T): T =\n apply (in, sync, init.litValue.toInt, None)\n}\n\nclass ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {\n require(sync > 1, s\"Sync must be greater than 1, not ${sync}.\")\n override def desiredName = s\"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}\"\n val output = Seq.tabulate(w) { i =>\n val initBit = ((init >> i) & 1) > 0\n SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)\n }\n io.q := Cat(output.reverse)\n}\n\nobject ResetSynchronizerShiftReg {\n def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =\n AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)\n\n def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =\n apply (in, sync, 0, name)\n\n def apply [T <: Data](in: T, sync: Int): T =\n apply (in, sync, 0, None)\n\n def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =\n apply(in, sync, init.litValue.toInt, name)\n\n def apply [T <: Data](in: T, sync: Int, init: T): T =\n apply (in, sync, init.litValue.toInt, None)\n}\n\nclass SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {\n require(sync > 1, s\"Sync must be greater than 1, not ${sync}.\")\n override def desiredName = s\"SynchronizerShiftReg_w${w}_d${sync}\"\n val output = Seq.tabulate(w) { i =>\n SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)\n }\n io.q := Cat(output.reverse)\n}\n\nobject SynchronizerShiftReg {\n def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =\n if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)\n\n def apply [T <: Data](in: T, sync: Int): T =\n apply (in, sync, None)\n\n def apply [T <: Data](in: T): T =\n apply (in, 3, None)\n\n\n}\n\nclass ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {\n\n override def desiredName = s\"ClockCrossingReg_w${w}\"\n\n val io = IO(new Bundle{\n val d = Input(UInt(w.W))\n val q = Output(UInt(w.W))\n val en = Input(Bool())\n })\n\n val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)\n io.q := cdc_reg\n}\n\nobject ClockCrossingReg {\n def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {\n val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))\n name.foreach{ cdc_reg.suggestName(_) }\n cdc_reg.io.d := in.asUInt\n cdc_reg.io.en := en\n cdc_reg.io.q.asTypeOf(in)\n }\n}\n"},"response":{"kind":"string","value":"module ClockCrossingReg_w32_TestHarness_UNIQUIFIED(\t// @[SynchronizerReg.scala:191:7]\n input clock,\t// @[SynchronizerReg.scala:191:7]\n input [31:0] io_d,\t// @[SynchronizerReg.scala:195:14]\n output [31:0] io_q,\t// @[SynchronizerReg.scala:195:14]\n input io_en\t// @[SynchronizerReg.scala:195:14]\n);\n\n reg [31:0] cdc_reg;\t// @[SynchronizerReg.scala:201:76]\n always @(posedge clock) begin\t// @[SynchronizerReg.scala:191:7]\n if (io_en)\t// @[SynchronizerReg.scala:195:14]\n cdc_reg <= io_d;\t// @[SynchronizerReg.scala:201:76]\n always @(posedge)"}}},{"rowIdx":589,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to the following Chisel files.\nFile ShiftReg.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3._\n\n// Similar to the Chisel ShiftRegister but allows the user to suggest a\n// name to the registers that get instantiated, and\n// to provide a reset value.\nobject ShiftRegInit {\n def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =\n\n (0 until n).foldRight(in) {\n case (i, next) => {\n val r = RegNext(next, init)\n name.foreach { na => r.suggestName(s\"${na}_${i}\") }\n r\n }\n }\n}\n\n/** These wrap behavioral\n * shift registers into specific modules to allow for\n * backend flows to replace or constrain\n * them properly when used for CDC synchronization,\n * rather than buffering.\n * \n * The different types vary in their reset behavior:\n * AsyncResetShiftReg -- Asynchronously reset register array\n * A W(width) x D(depth) sized array is constructed from D instantiations of a\n * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,\n * but only used for timing applications\n */\n\nabstract class AbstractPipelineReg(w: Int = 1) extends Module {\n val io = IO(new Bundle {\n val d = Input(UInt(w.W))\n val q = Output(UInt(w.W))\n }\n )\n}\n\nobject AbstractPipelineReg {\n def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {\n val chain = Module(gen)\n name.foreach{ chain.suggestName(_) }\n chain.io.d := in.asUInt\n chain.io.q.asTypeOf(in)\n }\n}\n\nclass AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = \"pipe\") extends AbstractPipelineReg(w) {\n require(depth > 0, \"Depth must be greater than 0.\")\n\n override def desiredName = s\"AsyncResetShiftReg_w${w}_d${depth}_i${init}\"\n\n val chain = List.tabulate(depth) { i =>\n Module (new AsyncResetRegVec(w, init)).suggestName(s\"${name}_${i}\")\n }\n\n chain.last.io.d := io.d\n chain.last.io.en := true.B\n\n (chain.init zip chain.tail).foreach { case (sink, source) =>\n sink.io.d := source.io.q\n sink.io.en := true.B\n }\n io.q := chain.head.io.q\n}\n\nobject AsyncResetShiftReg {\n def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =\n AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)\n\n def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =\n apply(in, depth, 0, name)\n\n def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =\n apply(in, depth, init.litValue.toInt, name)\n\n def apply [T <: Data](in: T, depth: Int, init: T): T =\n apply (in, depth, init.litValue.toInt, None)\n}\nFile AsyncQueue.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3._\nimport chisel3.util._\n\ncase class AsyncQueueParams(\n depth: Int = 8,\n sync: Int = 3,\n safe: Boolean = true,\n// If safe is true, then effort is made to resynchronize the crossing indices when either side is reset.\n// This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty.\n narrow: Boolean = false)\n// If narrow is true then the read mux is moved to the source side of the crossing.\n// This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing,\n// at the expense of a combinational path from the sink to the source and back to the sink.\n{\n require (depth > 0 && isPow2(depth))\n require (sync >= 2)\n\n val bits = log2Ceil(depth)\n val wires = if (narrow) 1 else depth\n}\n\nobject AsyncQueueParams {\n // When there is only one entry, we don't need narrow.\n def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false)\n}\n\nclass AsyncBundleSafety extends Bundle {\n val ridx_valid = Input (Bool())\n val widx_valid = Output(Bool())\n val source_reset_n = Output(Bool())\n val sink_reset_n = Input (Bool())\n}\n\nclass AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle {\n // Data-path synchronization\n val mem = Output(Vec(params.wires, gen))\n val ridx = Input (UInt((params.bits+1).W))\n val widx = Output(UInt((params.bits+1).W))\n val index = params.narrow.option(Input(UInt(params.bits.W)))\n\n // Signals used to self-stabilize a safe AsyncQueue\n val safe = params.safe.option(new AsyncBundleSafety)\n}\n\nobject GrayCounter {\n def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = \"binary\"): UInt = {\n val incremented = Wire(UInt(bits.W))\n val binary = RegNext(next=incremented, init=0.U).suggestName(name)\n incremented := Mux(clear, 0.U, binary + increment.asUInt)\n incremented ^ (incremented >> 1)\n }\n}\n\nclass AsyncValidSync(sync: Int, desc: String) extends RawModule {\n val io = IO(new Bundle {\n val in = Input(Bool())\n val out = Output(Bool())\n })\n val clock = IO(Input(Clock()))\n val reset = IO(Input(AsyncReset()))\n withClockAndReset(clock, reset){\n io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc))\n }\n}\n\nclass AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {\n override def desiredName = s\"AsyncQueueSource_${gen.typeName}\"\n\n val io = IO(new Bundle {\n // These come from the source domain\n val enq = Flipped(Decoupled(gen))\n // These cross to the sink clock domain\n val async = new AsyncBundle(gen, params)\n })\n\n val bits = params.bits\n val sink_ready = WireInit(true.B)\n val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all.\n val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, \"widx_bin\"))\n val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some(\"ridx_gray\"))\n val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U)\n\n val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1))\n when (io.enq.fire) { mem(index) := io.enq.bits }\n\n val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName(\"ready_reg\"))\n io.enq.ready := ready_reg && sink_ready\n\n val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName(\"widx_gray\"))\n io.async.widx := widx_reg\n\n io.async.index match {\n case Some(index) => io.async.mem(0) := mem(index)\n case None => io.async.mem := mem\n }\n\n io.async.safe.foreach { sio =>\n val source_valid_0 = Module(new AsyncValidSync(params.sync, \"source_valid_0\"))\n val source_valid_1 = Module(new AsyncValidSync(params.sync, \"source_valid_1\"))\n\n val sink_extend = Module(new AsyncValidSync(params.sync, \"sink_extend\"))\n val sink_valid = Module(new AsyncValidSync(params.sync, \"sink_valid\"))\n source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset\n source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset\n sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset\n sink_valid .reset := reset.asAsyncReset\n\n source_valid_0.clock := clock\n source_valid_1.clock := clock\n sink_extend .clock := clock\n sink_valid .clock := clock\n\n source_valid_0.io.in := true.B\n source_valid_1.io.in := source_valid_0.io.out\n sio.widx_valid := source_valid_1.io.out\n sink_extend.io.in := sio.ridx_valid\n sink_valid.io.in := sink_extend.io.out\n sink_ready := sink_valid.io.out\n sio.source_reset_n := !reset.asBool\n\n // Assert that if there is stuff in the queue, then reset cannot happen\n // Impossible to write because dequeue can occur on the receiving side,\n // then reset allowed to happen, but write side cannot know that dequeue\n // occurred.\n // TODO: write some sort of sanity check assertion for users\n // that denote don't reset when there is activity\n // assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, \"Enqueue while sink is reset and AsyncQueueSource is unprotected\")\n // assert (!reset_rise || prev_idx_match.asBool, \"Sink reset while AsyncQueueSource not empty\")\n }\n}\n\nclass AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {\n override def desiredName = s\"AsyncQueueSink_${gen.typeName}\"\n\n val io = IO(new Bundle {\n // These come from the sink domain\n val deq = Decoupled(gen)\n // These cross to the source clock domain\n val async = Flipped(new AsyncBundle(gen, params))\n })\n\n val bits = params.bits\n val source_ready = WireInit(true.B)\n val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, \"ridx_bin\"))\n val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some(\"widx_gray\"))\n val valid = source_ready && ridx =/= widx\n\n // The mux is safe because timing analysis ensures ridx has reached the register\n // On an ASIC, changes to the unread location cannot affect the selected value\n // On an FPGA, only one input changes at a time => mem updates don't cause glitches\n // The register only latches when the selected valued is not being written\n val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1))\n io.async.index.foreach { _ := index }\n // This register does not NEED to be reset, as its contents will not\n // be considered unless the asynchronously reset deq valid register is set.\n // It is possible that bits latches when the source domain is reset / has power cut\n // This is safe, because isolation gates brought mem low before the zeroed widx reached us\n val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index)\n io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some(\"deq_bits_reg\"))\n\n val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName(\"valid_reg\"))\n io.deq.valid := valid_reg && source_ready\n\n val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName(\"ridx_gray\"))\n io.async.ridx := ridx_reg\n\n io.async.safe.foreach { sio =>\n val sink_valid_0 = Module(new AsyncValidSync(params.sync, \"sink_valid_0\"))\n val sink_valid_1 = Module(new AsyncValidSync(params.sync, \"sink_valid_1\"))\n\n val source_extend = Module(new AsyncValidSync(params.sync, \"source_extend\"))\n val source_valid = Module(new AsyncValidSync(params.sync, \"source_valid\"))\n sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset\n sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset\n source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset\n source_valid .reset := reset.asAsyncReset\n\n sink_valid_0 .clock := clock\n sink_valid_1 .clock := clock\n source_extend.clock := clock\n source_valid .clock := clock\n\n sink_valid_0.io.in := true.B\n sink_valid_1.io.in := sink_valid_0.io.out\n sio.ridx_valid := sink_valid_1.io.out\n source_extend.io.in := sio.widx_valid\n source_valid.io.in := source_extend.io.out\n source_ready := source_valid.io.out\n sio.sink_reset_n := !reset.asBool\n\n // TODO: write some sort of sanity check assertion for users\n // that denote don't reset when there is activity\n // \n // val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool\n // val reset_and_extend_prev = RegNext(reset_and_extend, true.B)\n // val reset_rise = !reset_and_extend_prev && reset_and_extend\n // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0)\n // assert (!reset_rise || prev_idx_match.asBool, \"Source reset while AsyncQueueSink not empty\")\n }\n}\n\nobject FromAsyncBundle\n{\n // Sometimes it makes sense for the sink to have different sync than the source\n def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync)\n def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = {\n val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync)))\n sink.io.async <> x\n sink.io.deq\n }\n}\n\nobject ToAsyncBundle\n{\n def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = {\n val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params))\n source.io.enq <> x\n source.io.async\n }\n}\n\nclass AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] {\n val io = IO(new CrossingIO(gen))\n val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) }\n val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) }\n\n source.io.enq <> io.enq\n io.deq <> sink.io.deq\n sink.io.async <> source.io.async\n}\n"},"response":{"kind":"string","value":"module AsyncValidSync_68(\t// @[AsyncQueue.scala:58:7]\n output io_out,\t// @[AsyncQueue.scala:59:14]\n input clock,\t// @[AsyncQueue.scala:63:17]\n input reset\t// @[AsyncQueue.scala:64:17]\n);\n\n wire io_in = 1'h1;\t// @[ShiftReg.scala:45:23]\n wire _io_out_WIRE;\t// @[ShiftReg.scala:48:24]\n wire io_out_0;\t// @[AsyncQueue.scala:58:7]\n assign io_out_0 = _io_out_WIRE;\t// @[ShiftReg.scala:48:24]\n AsyncResetSynchronizerShiftReg_w1_d3_i0_68 io_out_source_valid_0 (\t// @[ShiftReg.scala:45:23]\n .clock (clock),\n .reset (reset),\n .io_q (_io_out_WIRE)\n );\t// @[ShiftReg.scala:45:23]\n assign io_out = io_out_0;\t// @[AsyncQueue.scala:58:7]\nendmodule"}}},{"rowIdx":590,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to the following Chisel files.\nFile Crossing.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.interrupts\n\nimport chisel3._\nimport chisel3.util._\nimport org.chipsalliance.cde.config._\nimport org.chipsalliance.diplomacy.lazymodule._\n\nimport freechips.rocketchip.util.{SynchronizerShiftReg, AsyncResetReg}\n\n@deprecated(\"IntXing does not ensure interrupt source is glitch free. Use IntSyncSource and IntSyncSink\", \"rocket-chip 1.2\")\nclass IntXing(sync: Int = 3)(implicit p: Parameters) extends LazyModule\n{\n val intnode = IntAdapterNode()\n\n lazy val module = new Impl\n class Impl extends LazyModuleImp(this) {\n (intnode.in zip intnode.out) foreach { case ((in, _), (out, _)) =>\n out := SynchronizerShiftReg(in, sync)\n }\n }\n}\n\nobject IntSyncCrossingSource\n{\n def apply(alreadyRegistered: Boolean = false)(implicit p: Parameters) =\n {\n val intsource = LazyModule(new IntSyncCrossingSource(alreadyRegistered))\n intsource.node\n }\n}\n\n\nclass IntSyncCrossingSource(alreadyRegistered: Boolean = false)(implicit p: Parameters) extends LazyModule\n{\n val node = IntSyncSourceNode(alreadyRegistered)\n\n lazy val module = if (alreadyRegistered) (new ImplRegistered) else (new Impl)\n\n class Impl extends LazyModuleImp(this) {\n def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0)\n override def desiredName = s\"IntSyncCrossingSource_n${node.out.size}x${outSize}\"\n (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>\n out.sync := AsyncResetReg(Cat(in.reverse)).asBools\n }\n }\n class ImplRegistered extends LazyRawModuleImp(this) {\n def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0)\n override def desiredName = s\"IntSyncCrossingSource_n${node.out.size}x${outSize}_Registered\"\n (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>\n out.sync := in\n }\n }\n}\n\n\nobject IntSyncCrossingSink\n{\n @deprecated(\"IntSyncCrossingSink which used the `sync` parameter to determine crossing type is deprecated. Use IntSyncAsyncCrossingSink, IntSyncRationalCrossingSink, or IntSyncSyncCrossingSink instead for > 1, 1, and 0 sync values respectively\", \"rocket-chip 1.2\")\n def apply(sync: Int = 3)(implicit p: Parameters) =\n {\n val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync))\n intsink.node\n }\n}\n\n\nclass IntSyncAsyncCrossingSink(sync: Int = 3)(implicit p: Parameters) extends LazyModule\n{\n val node = IntSyncSinkNode(sync)\n\n lazy val module = new Impl\n class Impl extends LazyModuleImp(this) {\n override def desiredName = s\"IntSyncAsyncCrossingSink_n${node.out.size}x${node.out.head._1.size}\"\n (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>\n out := SynchronizerShiftReg(in.sync, sync)\n }\n }\n}\n\nobject IntSyncAsyncCrossingSink\n{\n def apply(sync: Int = 3)(implicit p: Parameters) =\n {\n val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync))\n intsink.node\n }\n}\n\nclass IntSyncSyncCrossingSink()(implicit p: Parameters) extends LazyModule\n{\n val node = IntSyncSinkNode(0)\n\n lazy val module = new Impl\n class Impl extends LazyRawModuleImp(this) {\n def outSize = node.out.headOption.map(_._1.size).getOrElse(0)\n override def desiredName = s\"IntSyncSyncCrossingSink_n${node.out.size}x${outSize}\"\n (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>\n out := in.sync\n }\n }\n}\n\nobject IntSyncSyncCrossingSink\n{\n def apply()(implicit p: Parameters) =\n {\n val intsink = LazyModule(new IntSyncSyncCrossingSink())\n intsink.node\n }\n}\n\nclass IntSyncRationalCrossingSink()(implicit p: Parameters) extends LazyModule\n{\n val node = IntSyncSinkNode(1)\n\n lazy val module = new Impl\n class Impl extends LazyModuleImp(this) {\n def outSize = node.out.headOption.map(_._1.size).getOrElse(0)\n override def desiredName = s\"IntSyncRationalCrossingSink_n${node.out.size}x${outSize}\"\n (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>\n out := RegNext(in.sync)\n }\n }\n}\n\nobject IntSyncRationalCrossingSink\n{\n def apply()(implicit p: Parameters) =\n {\n val intsink = LazyModule(new IntSyncRationalCrossingSink())\n intsink.node\n }\n}\nFile LazyModuleImp.scala:\npackage org.chipsalliance.diplomacy.lazymodule\n\nimport chisel3.{withClockAndReset, Module, RawModule, Reset, _}\nimport chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}\nimport firrtl.passes.InlineAnnotation\nimport org.chipsalliance.cde.config.Parameters\nimport org.chipsalliance.diplomacy.nodes.Dangle\n\nimport scala.collection.immutable.SortedMap\n\n/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].\n *\n * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.\n */\nsealed trait LazyModuleImpLike extends RawModule {\n\n /** [[LazyModule]] that contains this instance. */\n val wrapper: LazyModule\n\n /** IOs that will be automatically \"punched\" for this instance. */\n val auto: AutoBundle\n\n /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */\n protected[diplomacy] val dangles: Seq[Dangle]\n\n // [[wrapper.module]] had better not be accessed while LazyModules are still being built!\n require(\n LazyModule.scope.isEmpty,\n s\"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}\"\n )\n\n /** Set module name. Defaults to the containing LazyModule's desiredName. */\n override def desiredName: String = wrapper.desiredName\n\n suggestName(wrapper.suggestedName)\n\n /** [[Parameters]] for chisel [[Module]]s. */\n implicit val p: Parameters = wrapper.p\n\n /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and\n * submodules.\n */\n protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {\n // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],\n // 2. return [[Dangle]]s from each module.\n val childDangles = wrapper.children.reverse.flatMap { c =>\n implicit val sourceInfo: SourceInfo = c.info\n c.cloneProto.map { cp =>\n // If the child is a clone, then recursively set cloneProto of its children as well\n def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {\n require(bases.size == clones.size)\n (bases.zip(clones)).map { case (l, r) =>\n require(l.getClass == r.getClass, s\"Cloned children class mismatch ${l.name} != ${r.name}\")\n l.cloneProto = Some(r)\n assignCloneProtos(l.children, r.children)\n }\n }\n assignCloneProtos(c.children, cp.children)\n // Clone the child module as a record, and get its [[AutoBundle]]\n val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)\n val clonedAuto = clone(\"auto\").asInstanceOf[AutoBundle]\n // Get the empty [[Dangle]]'s of the cloned child\n val rawDangles = c.cloneDangles()\n require(rawDangles.size == clonedAuto.elements.size)\n // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s\n val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }\n dangles\n }.getOrElse {\n // For non-clones, instantiate the child module\n val mod = try {\n Module(c.module)\n } catch {\n case e: ChiselException => {\n println(s\"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}\")\n throw e\n }\n }\n mod.dangles\n }\n }\n\n // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].\n // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.\n val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())\n // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]\n val allDangles = nodeDangles ++ childDangles\n // Group [[allDangles]] by their [[source]].\n val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)\n // For each [[source]] set of [[Dangle]]s of size 2, ensure that these\n // can be connected as a source-sink pair (have opposite flipped value).\n // Make the connection and mark them as [[done]].\n val done = Set() ++ pairing.values.filter(_.size == 2).map {\n case Seq(a, b) =>\n require(a.flipped != b.flipped)\n // @todo <> in chisel3 makes directionless connection.\n if (a.flipped) {\n a.data <> b.data\n } else {\n b.data <> a.data\n }\n a.source\n case _ => None\n }\n // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.\n val forward = allDangles.filter(d => !done(d.source))\n // Generate [[AutoBundle]] IO from [[forward]].\n val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))\n // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]\n val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>\n if (d.flipped) {\n d.data <> io\n } else {\n io <> d.data\n }\n d.copy(dataOpt = Some(io), name = wrapper.suggestedName + \"_\" + d.name)\n }\n // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].\n wrapper.inModuleBody.reverse.foreach {\n _()\n }\n\n if (wrapper.shouldBeInlined) {\n chisel3.experimental.annotate(new ChiselAnnotation {\n def toFirrtl = InlineAnnotation(toNamed)\n })\n }\n\n // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].\n (auto, dangles)\n }\n}\n\n/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].\n *\n * @param wrapper\n * the [[LazyModule]] from which the `.module` call is being made.\n */\nclass LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {\n\n /** Instantiate hardware of this `Module`. */\n val (auto, dangles) = instantiate()\n}\n\n/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].\n *\n * @param wrapper\n * the [[LazyModule]] from which the `.module` call is being made.\n */\nclass LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {\n // These wires are the default clock+reset for all LazyModule children.\n // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the\n // [[LazyRawModuleImp]] children.\n // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.\n /** drive clock explicitly. */\n val childClock: Clock = Wire(Clock())\n\n /** drive reset explicitly. */\n val childReset: Reset = Wire(Reset())\n // the default is that these are disabled\n childClock := false.B.asClock\n childReset := chisel3.DontCare\n\n def provideImplicitClockToLazyChildren: Boolean = false\n val (auto, dangles) =\n if (provideImplicitClockToLazyChildren) {\n withClockAndReset(childClock, childReset) { instantiate() }\n } else {\n instantiate()\n }\n}\n"},"response":{"kind":"string","value":"module IntSyncSyncCrossingSink_n0x0_1();\t// @[Crossing.scala:96:9]\n wire childClock = 1'h0;\t// @[LazyModuleImp.scala:155:31]\n wire childReset = 1'h0;\t// @[LazyModuleImp.scala:158:31]\n wire _childClock_T = 1'h0;\t// @[LazyModuleImp.scala:160:25]\nendmodule"}}},{"rowIdx":591,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to the following Chisel files.\nFile ShiftReg.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3._\n\n// Similar to the Chisel ShiftRegister but allows the user to suggest a\n// name to the registers that get instantiated, and\n// to provide a reset value.\nobject ShiftRegInit {\n def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =\n\n (0 until n).foldRight(in) {\n case (i, next) => {\n val r = RegNext(next, init)\n name.foreach { na => r.suggestName(s\"${na}_${i}\") }\n r\n }\n }\n}\n\n/** These wrap behavioral\n * shift registers into specific modules to allow for\n * backend flows to replace or constrain\n * them properly when used for CDC synchronization,\n * rather than buffering.\n * \n * The different types vary in their reset behavior:\n * AsyncResetShiftReg -- Asynchronously reset register array\n * A W(width) x D(depth) sized array is constructed from D instantiations of a\n * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,\n * but only used for timing applications\n */\n\nabstract class AbstractPipelineReg(w: Int = 1) extends Module {\n val io = IO(new Bundle {\n val d = Input(UInt(w.W))\n val q = Output(UInt(w.W))\n }\n )\n}\n\nobject AbstractPipelineReg {\n def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {\n val chain = Module(gen)\n name.foreach{ chain.suggestName(_) }\n chain.io.d := in.asUInt\n chain.io.q.asTypeOf(in)\n }\n}\n\nclass AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = \"pipe\") extends AbstractPipelineReg(w) {\n require(depth > 0, \"Depth must be greater than 0.\")\n\n override def desiredName = s\"AsyncResetShiftReg_w${w}_d${depth}_i${init}\"\n\n val chain = List.tabulate(depth) { i =>\n Module (new AsyncResetRegVec(w, init)).suggestName(s\"${name}_${i}\")\n }\n\n chain.last.io.d := io.d\n chain.last.io.en := true.B\n\n (chain.init zip chain.tail).foreach { case (sink, source) =>\n sink.io.d := source.io.q\n sink.io.en := true.B\n }\n io.q := chain.head.io.q\n}\n\nobject AsyncResetShiftReg {\n def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =\n AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)\n\n def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =\n apply(in, depth, 0, name)\n\n def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =\n apply(in, depth, init.litValue.toInt, name)\n\n def apply [T <: Data](in: T, depth: Int, init: T): T =\n apply (in, depth, init.litValue.toInt, None)\n}\nFile AsyncQueue.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3._\nimport chisel3.util._\n\ncase class AsyncQueueParams(\n depth: Int = 8,\n sync: Int = 3,\n safe: Boolean = true,\n// If safe is true, then effort is made to resynchronize the crossing indices when either side is reset.\n// This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty.\n narrow: Boolean = false)\n// If narrow is true then the read mux is moved to the source side of the crossing.\n// This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing,\n// at the expense of a combinational path from the sink to the source and back to the sink.\n{\n require (depth > 0 && isPow2(depth))\n require (sync >= 2)\n\n val bits = log2Ceil(depth)\n val wires = if (narrow) 1 else depth\n}\n\nobject AsyncQueueParams {\n // When there is only one entry, we don't need narrow.\n def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false)\n}\n\nclass AsyncBundleSafety extends Bundle {\n val ridx_valid = Input (Bool())\n val widx_valid = Output(Bool())\n val source_reset_n = Output(Bool())\n val sink_reset_n = Input (Bool())\n}\n\nclass AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle {\n // Data-path synchronization\n val mem = Output(Vec(params.wires, gen))\n val ridx = Input (UInt((params.bits+1).W))\n val widx = Output(UInt((params.bits+1).W))\n val index = params.narrow.option(Input(UInt(params.bits.W)))\n\n // Signals used to self-stabilize a safe AsyncQueue\n val safe = params.safe.option(new AsyncBundleSafety)\n}\n\nobject GrayCounter {\n def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = \"binary\"): UInt = {\n val incremented = Wire(UInt(bits.W))\n val binary = RegNext(next=incremented, init=0.U).suggestName(name)\n incremented := Mux(clear, 0.U, binary + increment.asUInt)\n incremented ^ (incremented >> 1)\n }\n}\n\nclass AsyncValidSync(sync: Int, desc: String) extends RawModule {\n val io = IO(new Bundle {\n val in = Input(Bool())\n val out = Output(Bool())\n })\n val clock = IO(Input(Clock()))\n val reset = IO(Input(AsyncReset()))\n withClockAndReset(clock, reset){\n io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc))\n }\n}\n\nclass AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {\n override def desiredName = s\"AsyncQueueSource_${gen.typeName}\"\n\n val io = IO(new Bundle {\n // These come from the source domain\n val enq = Flipped(Decoupled(gen))\n // These cross to the sink clock domain\n val async = new AsyncBundle(gen, params)\n })\n\n val bits = params.bits\n val sink_ready = WireInit(true.B)\n val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all.\n val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, \"widx_bin\"))\n val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some(\"ridx_gray\"))\n val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U)\n\n val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1))\n when (io.enq.fire) { mem(index) := io.enq.bits }\n\n val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName(\"ready_reg\"))\n io.enq.ready := ready_reg && sink_ready\n\n val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName(\"widx_gray\"))\n io.async.widx := widx_reg\n\n io.async.index match {\n case Some(index) => io.async.mem(0) := mem(index)\n case None => io.async.mem := mem\n }\n\n io.async.safe.foreach { sio =>\n val source_valid_0 = Module(new AsyncValidSync(params.sync, \"source_valid_0\"))\n val source_valid_1 = Module(new AsyncValidSync(params.sync, \"source_valid_1\"))\n\n val sink_extend = Module(new AsyncValidSync(params.sync, \"sink_extend\"))\n val sink_valid = Module(new AsyncValidSync(params.sync, \"sink_valid\"))\n source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset\n source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset\n sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset\n sink_valid .reset := reset.asAsyncReset\n\n source_valid_0.clock := clock\n source_valid_1.clock := clock\n sink_extend .clock := clock\n sink_valid .clock := clock\n\n source_valid_0.io.in := true.B\n source_valid_1.io.in := source_valid_0.io.out\n sio.widx_valid := source_valid_1.io.out\n sink_extend.io.in := sio.ridx_valid\n sink_valid.io.in := sink_extend.io.out\n sink_ready := sink_valid.io.out\n sio.source_reset_n := !reset.asBool\n\n // Assert that if there is stuff in the queue, then reset cannot happen\n // Impossible to write because dequeue can occur on the receiving side,\n // then reset allowed to happen, but write side cannot know that dequeue\n // occurred.\n // TODO: write some sort of sanity check assertion for users\n // that denote don't reset when there is activity\n // assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, \"Enqueue while sink is reset and AsyncQueueSource is unprotected\")\n // assert (!reset_rise || prev_idx_match.asBool, \"Sink reset while AsyncQueueSource not empty\")\n }\n}\n\nclass AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {\n override def desiredName = s\"AsyncQueueSink_${gen.typeName}\"\n\n val io = IO(new Bundle {\n // These come from the sink domain\n val deq = Decoupled(gen)\n // These cross to the source clock domain\n val async = Flipped(new AsyncBundle(gen, params))\n })\n\n val bits = params.bits\n val source_ready = WireInit(true.B)\n val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, \"ridx_bin\"))\n val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some(\"widx_gray\"))\n val valid = source_ready && ridx =/= widx\n\n // The mux is safe because timing analysis ensures ridx has reached the register\n // On an ASIC, changes to the unread location cannot affect the selected value\n // On an FPGA, only one input changes at a time => mem updates don't cause glitches\n // The register only latches when the selected valued is not being written\n val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1))\n io.async.index.foreach { _ := index }\n // This register does not NEED to be reset, as its contents will not\n // be considered unless the asynchronously reset deq valid register is set.\n // It is possible that bits latches when the source domain is reset / has power cut\n // This is safe, because isolation gates brought mem low before the zeroed widx reached us\n val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index)\n io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some(\"deq_bits_reg\"))\n\n val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName(\"valid_reg\"))\n io.deq.valid := valid_reg && source_ready\n\n val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName(\"ridx_gray\"))\n io.async.ridx := ridx_reg\n\n io.async.safe.foreach { sio =>\n val sink_valid_0 = Module(new AsyncValidSync(params.sync, \"sink_valid_0\"))\n val sink_valid_1 = Module(new AsyncValidSync(params.sync, \"sink_valid_1\"))\n\n val source_extend = Module(new AsyncValidSync(params.sync, \"source_extend\"))\n val source_valid = Module(new AsyncValidSync(params.sync, \"source_valid\"))\n sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset\n sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset\n source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset\n source_valid .reset := reset.asAsyncReset\n\n sink_valid_0 .clock := clock\n sink_valid_1 .clock := clock\n source_extend.clock := clock\n source_valid .clock := clock\n\n sink_valid_0.io.in := true.B\n sink_valid_1.io.in := sink_valid_0.io.out\n sio.ridx_valid := sink_valid_1.io.out\n source_extend.io.in := sio.widx_valid\n source_valid.io.in := source_extend.io.out\n source_ready := source_valid.io.out\n sio.sink_reset_n := !reset.asBool\n\n // TODO: write some sort of sanity check assertion for users\n // that denote don't reset when there is activity\n // \n // val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool\n // val reset_and_extend_prev = RegNext(reset_and_extend, true.B)\n // val reset_rise = !reset_and_extend_prev && reset_and_extend\n // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0)\n // assert (!reset_rise || prev_idx_match.asBool, \"Source reset while AsyncQueueSink not empty\")\n }\n}\n\nobject FromAsyncBundle\n{\n // Sometimes it makes sense for the sink to have different sync than the source\n def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync)\n def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = {\n val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync)))\n sink.io.async <> x\n sink.io.deq\n }\n}\n\nobject ToAsyncBundle\n{\n def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = {\n val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params))\n source.io.enq <> x\n source.io.async\n }\n}\n\nclass AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] {\n val io = IO(new CrossingIO(gen))\n val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) }\n val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) }\n\n source.io.enq <> io.enq\n io.deq <> sink.io.deq\n sink.io.async <> source.io.async\n}\n"},"response":{"kind":"string","value":"module AsyncValidSync_53(\t// @[AsyncQueue.scala:58:7]\n input io_in,\t// @[AsyncQueue.scala:59:14]\n output io_out,\t// @[AsyncQueue.scala:59:14]\n input clock,\t// @[AsyncQueue.scala:63:17]\n input reset\t// @[AsyncQueue.scala:64:17]\n);\n\n wire io_in_0 = io_in;\t// @[AsyncQueue.scala:58:7]\n wire _io_out_WIRE;\t// @[ShiftReg.scala:48:24]\n wire io_out_0;\t// @[AsyncQueue.scala:58:7]\n assign io_out_0 = _io_out_WIRE;\t// @[ShiftReg.scala:48:24]\n AsyncResetSynchronizerShiftReg_w1_d3_i0_63 io_out_sink_valid_1 (\t// @[ShiftReg.scala:45:23]\n .clock (clock),\n .reset (reset),\n .io_d (io_in_0),\t// @[AsyncQueue.scala:58:7]\n .io_q (_io_out_WIRE)\n );\t// @[ShiftReg.scala:45:23]\n assign io_out = io_out_0;\t// @[AsyncQueue.scala:58:7]\nendmodule"}}},{"rowIdx":592,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to the following Chisel files.\nFile ShiftReg.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3._\n\n// Similar to the Chisel ShiftRegister but allows the user to suggest a\n// name to the registers that get instantiated, and\n// to provide a reset value.\nobject ShiftRegInit {\n def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =\n\n (0 until n).foldRight(in) {\n case (i, next) => {\n val r = RegNext(next, init)\n name.foreach { na => r.suggestName(s\"${na}_${i}\") }\n r\n }\n }\n}\n\n/** These wrap behavioral\n * shift registers into specific modules to allow for\n * backend flows to replace or constrain\n * them properly when used for CDC synchronization,\n * rather than buffering.\n * \n * The different types vary in their reset behavior:\n * AsyncResetShiftReg -- Asynchronously reset register array\n * A W(width) x D(depth) sized array is constructed from D instantiations of a\n * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,\n * but only used for timing applications\n */\n\nabstract class AbstractPipelineReg(w: Int = 1) extends Module {\n val io = IO(new Bundle {\n val d = Input(UInt(w.W))\n val q = Output(UInt(w.W))\n }\n )\n}\n\nobject AbstractPipelineReg {\n def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {\n val chain = Module(gen)\n name.foreach{ chain.suggestName(_) }\n chain.io.d := in.asUInt\n chain.io.q.asTypeOf(in)\n }\n}\n\nclass AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = \"pipe\") extends AbstractPipelineReg(w) {\n require(depth > 0, \"Depth must be greater than 0.\")\n\n override def desiredName = s\"AsyncResetShiftReg_w${w}_d${depth}_i${init}\"\n\n val chain = List.tabulate(depth) { i =>\n Module (new AsyncResetRegVec(w, init)).suggestName(s\"${name}_${i}\")\n }\n\n chain.last.io.d := io.d\n chain.last.io.en := true.B\n\n (chain.init zip chain.tail).foreach { case (sink, source) =>\n sink.io.d := source.io.q\n sink.io.en := true.B\n }\n io.q := chain.head.io.q\n}\n\nobject AsyncResetShiftReg {\n def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =\n AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)\n\n def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =\n apply(in, depth, 0, name)\n\n def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =\n apply(in, depth, init.litValue.toInt, name)\n\n def apply [T <: Data](in: T, depth: Int, init: T): T =\n apply (in, depth, init.litValue.toInt, None)\n}\nFile SynchronizerReg.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3._\nimport chisel3.util.{RegEnable, Cat}\n\n/** These wrap behavioral\n * shift and next registers into specific modules to allow for\n * backend flows to replace or constrain\n * them properly when used for CDC synchronization,\n * rather than buffering.\n * \n * \n * These are built up of *ResetSynchronizerPrimitiveShiftReg,\n * intended to be replaced by the integrator's metastable flops chains or replaced\n * at this level if they have a multi-bit wide synchronizer primitive.\n * The different types vary in their reset behavior:\n * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin\n * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep\n * 1-bit-wide shift registers.\n * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg\n * \n * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.\n * \n * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross\n * Clock Domains.\n*/\n\nobject SynchronizerResetType extends Enumeration {\n val NonSync, Inferred, Sync, Async = Value\n}\n\n\n// Note: this should not be used directly.\n// Use the companion object to generate this with the correct reset type mixin.\nprivate class SynchronizerPrimitiveShiftReg(\n sync: Int,\n init: Boolean,\n resetType: SynchronizerResetType.Value)\n extends AbstractPipelineReg(1) {\n\n val initInt = if (init) 1 else 0\n val initPostfix = resetType match {\n case SynchronizerResetType.NonSync => \"\"\n case _ => s\"_i${initInt}\"\n }\n override def desiredName = s\"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}\"\n\n val chain = List.tabulate(sync) { i =>\n val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)\n reg.suggestName(s\"sync_$i\")\n }\n chain.last := io.d.asBool\n\n (chain.init zip chain.tail).foreach { case (sink, source) =>\n sink := source\n }\n io.q := chain.head.asUInt\n}\n\nprivate object SynchronizerPrimitiveShiftReg {\n def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {\n val gen: () => SynchronizerPrimitiveShiftReg = resetType match {\n case SynchronizerResetType.NonSync =>\n () => new SynchronizerPrimitiveShiftReg(sync, init, resetType)\n case SynchronizerResetType.Async =>\n () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset\n case SynchronizerResetType.Sync =>\n () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset\n case SynchronizerResetType.Inferred =>\n () => new SynchronizerPrimitiveShiftReg(sync, init, resetType)\n }\n AbstractPipelineReg(gen(), in)\n }\n}\n\n// Note: This module may end up with a non-AsyncReset type reset.\n// But the Primitives within will always have AsyncReset type.\nclass AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)\n extends AbstractPipelineReg(w) {\n require(sync > 1, s\"Sync must be greater than 1, not ${sync}.\")\n override def desiredName = s\"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}\"\n val output = Seq.tabulate(w) { i =>\n val initBit = ((init >> i) & 1) > 0\n withReset(reset.asAsyncReset){\n SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)\n }\n }\n io.q := Cat(output.reverse)\n}\n\nobject AsyncResetSynchronizerShiftReg {\n def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =\n AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)\n\n def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =\n apply (in, sync, 0, name)\n\n def apply [T <: Data](in: T, sync: Int): T =\n apply (in, sync, 0, None)\n\n def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =\n apply(in, sync, init.litValue.toInt, name)\n\n def apply [T <: Data](in: T, sync: Int, init: T): T =\n apply (in, sync, init.litValue.toInt, None)\n}\n\n// Note: This module may end up with a non-Bool type reset.\n// But the Primitives within will always have Bool reset type.\n@deprecated(\"SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.\", \"rocket-chip 1.2\")\nclass SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {\n require(sync > 1, s\"Sync must be greater than 1, not ${sync}.\")\n override def desiredName = s\"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}\"\n val output = Seq.tabulate(w) { i =>\n val initBit = ((init >> i) & 1) > 0\n withReset(reset.asBool){\n SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)\n }\n }\n io.q := Cat(output.reverse)\n}\n\nobject SyncResetSynchronizerShiftReg {\n def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =\n if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)\n\n def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =\n apply (in, sync, 0, name)\n\n def apply [T <: Data](in: T, sync: Int): T =\n apply (in, sync, 0, None)\n\n def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =\n apply(in, sync, init.litValue.toInt, name)\n\n def apply [T <: Data](in: T, sync: Int, init: T): T =\n apply (in, sync, init.litValue.toInt, None)\n}\n\nclass ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {\n require(sync > 1, s\"Sync must be greater than 1, not ${sync}.\")\n override def desiredName = s\"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}\"\n val output = Seq.tabulate(w) { i =>\n val initBit = ((init >> i) & 1) > 0\n SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)\n }\n io.q := Cat(output.reverse)\n}\n\nobject ResetSynchronizerShiftReg {\n def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =\n AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)\n\n def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =\n apply (in, sync, 0, name)\n\n def apply [T <: Data](in: T, sync: Int): T =\n apply (in, sync, 0, None)\n\n def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =\n apply(in, sync, init.litValue.toInt, name)\n\n def apply [T <: Data](in: T, sync: Int, init: T): T =\n apply (in, sync, init.litValue.toInt, None)\n}\n\nclass SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {\n require(sync > 1, s\"Sync must be greater than 1, not ${sync}.\")\n override def desiredName = s\"SynchronizerShiftReg_w${w}_d${sync}\"\n val output = Seq.tabulate(w) { i =>\n SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)\n }\n io.q := Cat(output.reverse)\n}\n\nobject SynchronizerShiftReg {\n def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =\n if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)\n\n def apply [T <: Data](in: T, sync: Int): T =\n apply (in, sync, None)\n\n def apply [T <: Data](in: T): T =\n apply (in, 3, None)\n\n\n}\n\nclass ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {\n\n override def desiredName = s\"ClockCrossingReg_w${w}\"\n\n val io = IO(new Bundle{\n val d = Input(UInt(w.W))\n val q = Output(UInt(w.W))\n val en = Input(Bool())\n })\n\n val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)\n io.q := cdc_reg\n}\n\nobject ClockCrossingReg {\n def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {\n val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))\n name.foreach{ cdc_reg.suggestName(_) }\n cdc_reg.io.d := in.asUInt\n cdc_reg.io.en := en\n cdc_reg.io.q.asTypeOf(in)\n }\n}\n"},"response":{"kind":"string","value":"module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_215(\t// @[SynchronizerReg.scala:68:19]\n input clock,\t// @[SynchronizerReg.scala:68:19]\n input reset,\t// @[SynchronizerReg.scala:68:19]\n input io_d,\t// @[ShiftReg.scala:36:14]\n output io_q\t// @[ShiftReg.scala:36:14]\n);\n\n wire io_d_0 = io_d;\t// @[SynchronizerReg.scala:68:19]\n wire _sync_2_T = io_d_0;\t// @[SynchronizerReg.scala:54:22, :68:19]\n wire io_q_0;\t// @[SynchronizerReg.scala:68:19]\n reg sync_0;\t// @[SynchronizerReg.scala:51:87]\n assign io_q_0 = sync_0;\t// @[SynchronizerReg.scala:51:87, :68:19]\n reg sync_1;\t// @[SynchronizerReg.scala:51:87]\n reg sync_2;\t// @[SynchronizerReg.scala:51:87]\n always @(posedge clock or posedge reset) begin\t// @[SynchronizerReg.scala:68:19]\n if (reset) begin\t// @[SynchronizerReg.scala:68:19]\n sync_0 <= 1'h0;\t// @[SynchronizerReg.scala:51:87]\n sync_1 <= 1'h0;\t// @[SynchronizerReg.scala:51:87]\n sync_2 <= 1'h0;\t// @[SynchronizerReg.scala:51:87]\n end\n else begin\t// @[SynchronizerReg.scala:68:19]\n sync_0 <= sync_1;\t// @[SynchronizerReg.scala:51:87]\n sync_1 <= sync_2;\t// @[SynchronizerReg.scala:51:87]\n sync_2 <= _sync_2_T;\t// @[SynchronizerReg.scala:51:87, :54:22]\n end\n always @(posedge, posedge)"}}},{"rowIdx":593,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to the following Chisel files.\nFile FIFOFixer.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.tilelink\n\nimport chisel3._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config.Parameters\nimport org.chipsalliance.diplomacy.lazymodule._\nimport org.chipsalliance.diplomacy.nodes._\n\nimport freechips.rocketchip.diplomacy.RegionType\nimport freechips.rocketchip.util.property\n\nclass TLFIFOFixer(policy: TLFIFOFixer.Policy = TLFIFOFixer.all)(implicit p: Parameters) extends LazyModule\n{\n private def fifoMap(seq: Seq[TLSlaveParameters]) = {\n val (flatManagers, keepManagers) = seq.partition(policy)\n // We need to be careful if one flatManager and one keepManager share an existing domain\n // Erring on the side of caution, we will also flatten the keepManager in this case\n val flatDomains = Set(flatManagers.flatMap(_.fifoId):_*) // => ID 0\n val keepDomains = Set(keepManagers.flatMap(_.fifoId):_*) -- flatDomains // => IDs compacted\n // Calculate what the FIFO domains look like after the fixer is applied\n val flatMap = flatDomains.map { x => (x, 0) }.toMap\n val keepMap = keepDomains.scanLeft((-1,0)) { case ((_,s),x) => (x, s+1) }.toMap\n val map = flatMap ++ keepMap\n val fixMap = seq.map { m => m.fifoId match {\n case None => if (policy(m)) Some(0) else None\n case Some(id) => Some(map(id)) // also flattens some who did not ask\n } }\n // Compress the FIFO domain space of those we are combining\n val reMap = flatDomains.scanLeft((-1,-1)) { case ((_,s),x) => (x, s+1) }.toMap\n val splatMap = seq.map { m => m.fifoId match {\n case None => None\n case Some(id) => reMap.lift(id)\n } }\n (fixMap, splatMap)\n }\n\n val node = new AdapterNode(TLImp)(\n { cp => cp },\n { mp =>\n val (fixMap, _) = fifoMap(mp.managers)\n mp.v1copy(managers = (fixMap zip mp.managers) map { case (id, m) => m.v1copy(fifoId = id) })\n }) with TLFormatNode {\n override def circuitIdentity = edges.in.map(_.client.clients.filter(c => c.requestFifo && c.sourceId.size > 1).size).sum == 0\n }\n\n lazy val module = new Impl\n class Impl extends LazyModuleImp(this) {\n (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>\n val (fixMap, splatMap) = fifoMap(edgeOut.manager.managers)\n\n // Do we need to serialize the request to this manager?\n val a_notFIFO = edgeIn.manager.fastProperty(in.a.bits.address, _.fifoId != Some(0), (b:Boolean) => b.B)\n // Compact the IDs of the cases we serialize\n val compacted = ((fixMap zip splatMap) zip edgeOut.manager.managers) flatMap {\n case ((f, s), m) => if (f == Some(0)) Some(m.v1copy(fifoId = s)) else None\n }\n val sinks = if (compacted.exists(_.supportsAcquireB)) edgeOut.manager.endSinkId else 0\n val a_id = if (compacted.isEmpty) 0.U else\n edgeOut.manager.v1copy(managers = compacted, endSinkId = sinks).findFifoIdFast(in.a.bits.address)\n val a_noDomain = a_id === 0.U\n\n if (false) {\n println(s\"FIFOFixer for: ${edgeIn.client.clients.map(_.name).mkString(\", \")}\")\n println(s\"make FIFO: ${edgeIn.manager.managers.filter(_.fifoId==Some(0)).map(_.name).mkString(\", \")}\")\n println(s\"not FIFO: ${edgeIn.manager.managers.filter(_.fifoId!=Some(0)).map(_.name).mkString(\", \")}\")\n println(s\"domains: ${compacted.groupBy(_.name).mapValues(_.map(_.fifoId))}\")\n println(\"\")\n }\n\n // Count beats\n val a_first = edgeIn.first(in.a)\n val d_first = edgeOut.first(out.d) && out.d.bits.opcode =/= TLMessages.ReleaseAck\n\n // Keep one bit for each source recording if there is an outstanding request that must be made FIFO\n // Sources unused in the stall signal calculation should be pruned by DCE\n val flight = RegInit(VecInit(Seq.fill(edgeIn.client.endSourceId) { false.B }))\n when (a_first && in.a.fire) { flight(in.a.bits.source) := !a_notFIFO }\n when (d_first && in.d.fire) { flight(in.d.bits.source) := false.B }\n\n val stalls = edgeIn.client.clients.filter(c => c.requestFifo && c.sourceId.size > 1).map { c =>\n val a_sel = c.sourceId.contains(in.a.bits.source)\n val id = RegEnable(a_id, in.a.fire && a_sel && !a_notFIFO)\n val track = flight.slice(c.sourceId.start, c.sourceId.end)\n\n a_sel && a_first && track.reduce(_ || _) && (a_noDomain || id =/= a_id)\n }\n\n val stall = stalls.foldLeft(false.B)(_||_)\n\n out.a <> in.a\n in.d <> out.d\n out.a.valid := in.a.valid && (a_notFIFO || !stall)\n in.a.ready := out.a.ready && (a_notFIFO || !stall)\n\n if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) {\n in .b <> out.b\n out.c <> in .c\n out.e <> in .e\n } else {\n in.b.valid := false.B\n in.c.ready := true.B\n in.e.ready := true.B\n out.b.ready := true.B\n out.c.valid := false.B\n out.e.valid := false.B\n }\n\n//Functional cover properties\n \n property.cover(in.a.valid && stall, \"COVER FIFOFIXER STALL\", \"Cover: Stall occured for a valid transaction\")\n\n val SourceIdFIFOed = RegInit(0.U(edgeIn.client.endSourceId.W))\n val SourceIdSet = WireDefault(0.U(edgeIn.client.endSourceId.W))\n val SourceIdClear = WireDefault(0.U(edgeIn.client.endSourceId.W))\n\n when (a_first && in.a.fire && !a_notFIFO) {\n SourceIdSet := UIntToOH(in.a.bits.source)\n }\n when (d_first && in.d.fire) {\n SourceIdClear := UIntToOH(in.d.bits.source)\n }\n\n SourceIdFIFOed := SourceIdFIFOed | SourceIdSet\n val allIDs_FIFOed = SourceIdFIFOed===Fill(SourceIdFIFOed.getWidth, 1.U)\n\n property.cover(allIDs_FIFOed, \"COVER all sources\", \"Cover: FIFOFIXER covers all Source IDs\")\n //property.cover(flight.reduce(_ && _), \"COVER full\", \"Cover: FIFO is full with all Source IDs\")\n property.cover(!(flight.reduce(_ || _)), \"COVER empty\", \"Cover: FIFO is empty\")\n property.cover(SourceIdSet > 0.U, \"COVER at least one push\", \"Cover: At least one Source ID is pushed\")\n property.cover(SourceIdClear > 0.U, \"COVER at least one pop\", \"Cover: At least one Source ID is popped\")\n\n }\n }\n}\n\nobject TLFIFOFixer\n{\n // Which slaves should have their FIFOness combined?\n // NOTE: this transformation is still only applied for masters with requestFifo\n type Policy = TLSlaveParameters => Boolean\n import RegionType._\n\n val all: Policy = m => true\n val allFIFO: Policy = m => m.fifoId.isDefined\n val allVolatile: Policy = m => m.regionType <= VOLATILE\n\n def apply(policy: Policy = all)(implicit p: Parameters): TLNode =\n {\n val fixer = LazyModule(new TLFIFOFixer(policy))\n fixer.node\n }\n}\nFile Nodes.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.tilelink\n\nimport chisel3._\nimport chisel3.experimental.SourceInfo\n\nimport org.chipsalliance.cde.config._\nimport org.chipsalliance.diplomacy._\nimport org.chipsalliance.diplomacy.nodes._\n\nimport freechips.rocketchip.util.{AsyncQueueParams,RationalDirection}\n\ncase object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args))\n\nobject TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle]\n{\n def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo)\n def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo)\n\n def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle)\n def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle)\n\n def render(ei: TLEdgeIn) = RenderedEdge(colour = \"#000000\" /* black */, label = (ei.manager.beatBytes * 8).toString)\n\n override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = {\n val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge)))\n monitor.io.in := bundle\n }\n\n override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters =\n pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })\n override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters =\n pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })\n}\n\n\ntrait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut]\n\ncase class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode\ncase class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode\n\ncase class TLAdapterNode(\n clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s },\n managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })(\n implicit valName: ValName)\n extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode\n\ncase class TLJunctionNode(\n clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters],\n managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])(\n implicit valName: ValName)\n extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode\n\ncase class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode\n\nobject TLNameNode {\n def apply(name: ValName) = TLIdentityNode()(name)\n def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse(\"with_no_name\")))\n def apply(name: String): TLIdentityNode = apply(Some(name))\n}\n\ncase class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)()\n\nobject TLTempNode {\n def apply(): TLEphemeralNode = TLEphemeralNode()(ValName(\"temp\"))\n}\n\ncase class TLNexusNode(\n clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters,\n managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)(\n implicit valName: ValName)\n extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode\n\nabstract class TLCustomNode(implicit valName: ValName)\n extends CustomNode(TLImp) with TLFormatNode\n\n// Asynchronous crossings\n\ntrait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters]\n\nobject TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle]\n{\n def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo)\n def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle)\n def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = \"#ff0000\" /* red */, label = e.manager.async.depth.toString)\n\n override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters =\n pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))\n override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters =\n pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))\n}\n\ncase class TLAsyncAdapterNode(\n clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s },\n managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })(\n implicit valName: ValName)\n extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode\n\ncase class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode\n\nobject TLAsyncNameNode {\n def apply(name: ValName) = TLAsyncIdentityNode()(name)\n def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse(\"with_no_name\")))\n def apply(name: String): TLAsyncIdentityNode = apply(Some(name))\n}\n\ncase class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName)\n extends MixedAdapterNode(TLImp, TLAsyncImp)(\n dFn = { p => TLAsyncClientPortParameters(p) },\n uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain\ncase class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName)\n extends MixedAdapterNode(TLAsyncImp, TLImp)(\n dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) },\n uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut]\n\n// Rationally related crossings\n\ntrait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters]\n\nobject TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle]\n{\n def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo)\n def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle)\n def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = \"#00ff00\" /* green */)\n\n override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters =\n pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))\n override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters =\n pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))\n}\n\ncase class TLRationalAdapterNode(\n clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s },\n managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })(\n implicit valName: ValName)\n extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode\n\ncase class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode\n\nobject TLRationalNameNode {\n def apply(name: ValName) = TLRationalIdentityNode()(name)\n def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse(\"with_no_name\")))\n def apply(name: String): TLRationalIdentityNode = apply(Some(name))\n}\n\ncase class TLRationalSourceNode()(implicit valName: ValName)\n extends MixedAdapterNode(TLImp, TLRationalImp)(\n dFn = { p => TLRationalClientPortParameters(p) },\n uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain\ncase class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName)\n extends MixedAdapterNode(TLRationalImp, TLImp)(\n dFn = { p => p.base.v1copy(minLatency = 1) },\n uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut]\n\n// Credited version of TileLink channels\n\ntrait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters]\n\nobject TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle]\n{\n def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo)\n def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle)\n def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = \"#ffff00\" /* yellow */, e.delay.toString)\n\n override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters =\n pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))\n override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters =\n pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))\n}\n\ncase class TLCreditedAdapterNode(\n clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s },\n managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })(\n implicit valName: ValName)\n extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode\n\ncase class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode\n\nobject TLCreditedNameNode {\n def apply(name: ValName) = TLCreditedIdentityNode()(name)\n def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse(\"with_no_name\")))\n def apply(name: String): TLCreditedIdentityNode = apply(Some(name))\n}\n\ncase class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName)\n extends MixedAdapterNode(TLImp, TLCreditedImp)(\n dFn = { p => TLCreditedClientPortParameters(delay, p) },\n uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain\n\ncase class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName)\n extends MixedAdapterNode(TLCreditedImp, TLImp)(\n dFn = { p => p.base.v1copy(minLatency = 1) },\n uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut]\nFile LazyModuleImp.scala:\npackage org.chipsalliance.diplomacy.lazymodule\n\nimport chisel3.{withClockAndReset, Module, RawModule, Reset, _}\nimport chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}\nimport firrtl.passes.InlineAnnotation\nimport org.chipsalliance.cde.config.Parameters\nimport org.chipsalliance.diplomacy.nodes.Dangle\n\nimport scala.collection.immutable.SortedMap\n\n/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].\n *\n * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.\n */\nsealed trait LazyModuleImpLike extends RawModule {\n\n /** [[LazyModule]] that contains this instance. */\n val wrapper: LazyModule\n\n /** IOs that will be automatically \"punched\" for this instance. */\n val auto: AutoBundle\n\n /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */\n protected[diplomacy] val dangles: Seq[Dangle]\n\n // [[wrapper.module]] had better not be accessed while LazyModules are still being built!\n require(\n LazyModule.scope.isEmpty,\n s\"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}\"\n )\n\n /** Set module name. Defaults to the containing LazyModule's desiredName. */\n override def desiredName: String = wrapper.desiredName\n\n suggestName(wrapper.suggestedName)\n\n /** [[Parameters]] for chisel [[Module]]s. */\n implicit val p: Parameters = wrapper.p\n\n /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and\n * submodules.\n */\n protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {\n // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],\n // 2. return [[Dangle]]s from each module.\n val childDangles = wrapper.children.reverse.flatMap { c =>\n implicit val sourceInfo: SourceInfo = c.info\n c.cloneProto.map { cp =>\n // If the child is a clone, then recursively set cloneProto of its children as well\n def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {\n require(bases.size == clones.size)\n (bases.zip(clones)).map { case (l, r) =>\n require(l.getClass == r.getClass, s\"Cloned children class mismatch ${l.name} != ${r.name}\")\n l.cloneProto = Some(r)\n assignCloneProtos(l.children, r.children)\n }\n }\n assignCloneProtos(c.children, cp.children)\n // Clone the child module as a record, and get its [[AutoBundle]]\n val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)\n val clonedAuto = clone(\"auto\").asInstanceOf[AutoBundle]\n // Get the empty [[Dangle]]'s of the cloned child\n val rawDangles = c.cloneDangles()\n require(rawDangles.size == clonedAuto.elements.size)\n // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s\n val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }\n dangles\n }.getOrElse {\n // For non-clones, instantiate the child module\n val mod = try {\n Module(c.module)\n } catch {\n case e: ChiselException => {\n println(s\"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}\")\n throw e\n }\n }\n mod.dangles\n }\n }\n\n // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].\n // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.\n val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())\n // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]\n val allDangles = nodeDangles ++ childDangles\n // Group [[allDangles]] by their [[source]].\n val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)\n // For each [[source]] set of [[Dangle]]s of size 2, ensure that these\n // can be connected as a source-sink pair (have opposite flipped value).\n // Make the connection and mark them as [[done]].\n val done = Set() ++ pairing.values.filter(_.size == 2).map {\n case Seq(a, b) =>\n require(a.flipped != b.flipped)\n // @todo <> in chisel3 makes directionless connection.\n if (a.flipped) {\n a.data <> b.data\n } else {\n b.data <> a.data\n }\n a.source\n case _ => None\n }\n // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.\n val forward = allDangles.filter(d => !done(d.source))\n // Generate [[AutoBundle]] IO from [[forward]].\n val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))\n // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]\n val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>\n if (d.flipped) {\n d.data <> io\n } else {\n io <> d.data\n }\n d.copy(dataOpt = Some(io), name = wrapper.suggestedName + \"_\" + d.name)\n }\n // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].\n wrapper.inModuleBody.reverse.foreach {\n _()\n }\n\n if (wrapper.shouldBeInlined) {\n chisel3.experimental.annotate(new ChiselAnnotation {\n def toFirrtl = InlineAnnotation(toNamed)\n })\n }\n\n // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].\n (auto, dangles)\n }\n}\n\n/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].\n *\n * @param wrapper\n * the [[LazyModule]] from which the `.module` call is being made.\n */\nclass LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {\n\n /** Instantiate hardware of this `Module`. */\n val (auto, dangles) = instantiate()\n}\n\n/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].\n *\n * @param wrapper\n * the [[LazyModule]] from which the `.module` call is being made.\n */\nclass LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {\n // These wires are the default clock+reset for all LazyModule children.\n // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the\n // [[LazyRawModuleImp]] children.\n // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.\n /** drive clock explicitly. */\n val childClock: Clock = Wire(Clock())\n\n /** drive reset explicitly. */\n val childReset: Reset = Wire(Reset())\n // the default is that these are disabled\n childClock := false.B.asClock\n childReset := chisel3.DontCare\n\n def provideImplicitClockToLazyChildren: Boolean = false\n val (auto, dangles) =\n if (provideImplicitClockToLazyChildren) {\n withClockAndReset(childClock, childReset) { instantiate() }\n } else {\n instantiate()\n }\n}\nFile Parameters.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.diplomacy\n\nimport chisel3._\nimport chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}\nimport freechips.rocketchip.util.ShiftQueue\n\n/** Options for describing the attributes of memory regions */\nobject RegionType {\n // Define the 'more relaxed than' ordering\n val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)\n sealed trait T extends Ordered[T] {\n def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)\n }\n\n case object CACHED extends T // an intermediate agent may have cached a copy of the region for you\n case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided\n case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible\n case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached\n case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects\n case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed\n case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively\n}\n\n// A non-empty half-open range; [start, end)\ncase class IdRange(start: Int, end: Int) extends Ordered[IdRange]\n{\n require (start >= 0, s\"Ids cannot be negative, but got: $start.\")\n require (start <= end, \"Id ranges cannot be negative.\")\n\n def compare(x: IdRange) = {\n val primary = (this.start - x.start).signum\n val secondary = (x.end - this.end).signum\n if (primary != 0) primary else secondary\n }\n\n def overlaps(x: IdRange) = start < x.end && x.start < end\n def contains(x: IdRange) = start <= x.start && x.end <= end\n\n def contains(x: Int) = start <= x && x < end\n def contains(x: UInt) =\n if (size == 0) {\n false.B\n } else if (size == 1) { // simple comparison\n x === start.U\n } else {\n // find index of largest different bit\n val largestDeltaBit = log2Floor(start ^ (end-1))\n val smallestCommonBit = largestDeltaBit + 1 // may not exist in x\n val uncommonMask = (1 << smallestCommonBit) - 1\n val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)\n // the prefix must match exactly (note: may shift ALL bits away)\n (x >> smallestCommonBit) === (start >> smallestCommonBit).U &&\n // firrtl constant prop range analysis can eliminate these two:\n (start & uncommonMask).U <= uncommonBits &&\n uncommonBits <= ((end-1) & uncommonMask).U\n }\n\n def shift(x: Int) = IdRange(start+x, end+x)\n def size = end - start\n def isEmpty = end == start\n\n def range = start until end\n}\n\nobject IdRange\n{\n def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {\n val ranges = s.sorted\n (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }\n }\n}\n\n// An potentially empty inclusive range of 2-powers [min, max] (in bytes)\ncase class TransferSizes(min: Int, max: Int)\n{\n def this(x: Int) = this(x, x)\n\n require (min <= max, s\"Min transfer $min > max transfer $max\")\n require (min >= 0 && max >= 0, s\"TransferSizes must be positive, got: ($min, $max)\")\n require (max == 0 || isPow2(max), s\"TransferSizes must be a power of 2, got: $max\")\n require (min == 0 || isPow2(min), s\"TransferSizes must be a power of 2, got: $min\")\n require (max == 0 || min != 0, s\"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)\")\n\n def none = min == 0\n def contains(x: Int) = isPow2(x) && min <= x && x <= max\n def containsLg(x: Int) = contains(1 << x)\n def containsLg(x: UInt) =\n if (none) false.B\n else if (min == max) { log2Ceil(min).U === x }\n else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }\n\n def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)\n\n def intersect(x: TransferSizes) =\n if (x.max < min || max < x.min) TransferSizes.none\n else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))\n\n // Not a union, because the result may contain sizes contained by neither term\n // NOT TO BE CONFUSED WITH COVERPOINTS\n def mincover(x: TransferSizes) = {\n if (none) {\n x\n } else if (x.none) {\n this\n } else {\n TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))\n }\n }\n\n override def toString() = \"TransferSizes[%d, %d]\".format(min, max)\n}\n\nobject TransferSizes {\n def apply(x: Int) = new TransferSizes(x)\n val none = new TransferSizes(0)\n\n def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)\n def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)\n\n implicit def asBool(x: TransferSizes) = !x.none\n}\n\n// AddressSets specify the address space managed by the manager\n// Base is the base address, and mask are the bits consumed by the manager\n// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff\n// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...\ncase class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]\n{\n // Forbid misaligned base address (and empty sets)\n require ((base & mask) == 0, s\"Mis-aligned AddressSets are forbidden, got: ${this.toString}\")\n require (base >= 0, s\"AddressSet negative base is ambiguous: $base\") // TL2 address widths are not fixed => negative is ambiguous\n // We do allow negative mask (=> ignore all high bits)\n\n def contains(x: BigInt) = ((x ^ base) & ~mask) == 0\n def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S\n\n // turn x into an address contained in this set\n def legalize(x: UInt): UInt = base.U | (mask.U & x)\n\n // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)\n def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0\n // contains iff bitwise: x.mask => mask && contains(x.base)\n def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0\n\n // The number of bytes to which the manager must be aligned\n def alignment = ((mask + 1) & ~mask)\n // Is this a contiguous memory range\n def contiguous = alignment == mask+1\n\n def finite = mask >= 0\n def max = { require (finite, \"Max cannot be calculated on infinite mask\"); base | mask }\n\n // Widen the match function to ignore all bits in imask\n def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)\n\n // Return an AddressSet that only contains the addresses both sets contain\n def intersect(x: AddressSet): Option[AddressSet] = {\n if (!overlaps(x)) {\n None\n } else {\n val r_mask = mask & x.mask\n val r_base = base | x.base\n Some(AddressSet(r_base, r_mask))\n }\n }\n\n def subtract(x: AddressSet): Seq[AddressSet] = {\n intersect(x) match {\n case None => Seq(this)\n case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>\n val nmask = (mask & (bit-1)) | remove.mask\n val nbase = (remove.base ^ bit) & ~nmask\n AddressSet(nbase, nmask)\n }\n }\n }\n\n // AddressSets have one natural Ordering (the containment order, if contiguous)\n def compare(x: AddressSet) = {\n val primary = (this.base - x.base).signum // smallest address first\n val secondary = (x.mask - this.mask).signum // largest mask first\n if (primary != 0) primary else secondary\n }\n\n // We always want to see things in hex\n override def toString() = {\n if (mask >= 0) {\n \"AddressSet(0x%x, 0x%x)\".format(base, mask)\n } else {\n \"AddressSet(0x%x, ~0x%x)\".format(base, ~mask)\n }\n }\n\n def toRanges = {\n require (finite, \"Ranges cannot be calculated on infinite mask\")\n val size = alignment\n val fragments = mask & ~(size-1)\n val bits = bitIndexes(fragments)\n (BigInt(0) until (BigInt(1) << bits.size)).map { i =>\n val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }\n AddressRange(off, size)\n }\n }\n}\n\nobject AddressSet\n{\n val everything = AddressSet(0, -1)\n def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {\n if (size == 0) tail.reverse else {\n val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)\n val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size\n val step =\n if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)\n maxSizeAlignment else maxBaseAlignment\n misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)\n }\n }\n\n def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {\n // Pair terms up by ignoring 'bit'\n seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>\n if (seq.size == 1) {\n seq.head // singleton -> unaffected\n } else {\n key.copy(mask = key.mask | bit) // pair - widen mask by bit\n }\n }.toList\n }\n\n def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {\n val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)\n AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted\n }\n\n def enumerateMask(mask: BigInt): Seq[BigInt] = {\n def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =\n if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)\n helper(0, Nil)\n }\n\n def enumerateBits(mask: BigInt): Seq[BigInt] = {\n def helper(x: BigInt): Seq[BigInt] = {\n if (x == 0) {\n Nil\n } else {\n val bit = x & (-x)\n bit +: helper(x & ~bit)\n }\n }\n helper(mask)\n }\n}\n\ncase class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)\n{\n require (depth >= 0, \"Buffer depth must be >= 0\")\n def isDefined = depth > 0\n def latency = if (isDefined && !flow) 1 else 0\n\n def apply[T <: Data](x: DecoupledIO[T]) =\n if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)\n else x\n\n def irrevocable[T <: Data](x: ReadyValidIO[T]) =\n if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)\n else x\n\n def sq[T <: Data](x: DecoupledIO[T]) =\n if (!isDefined) x else {\n val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))\n sq.io.enq <> x\n sq.io.deq\n }\n\n override def toString() = \"BufferParams:%d%s%s\".format(depth, if (flow) \"F\" else \"\", if (pipe) \"P\" else \"\")\n\n}\n\nobject BufferParams\n{\n implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)\n\n val default = BufferParams(2)\n val none = BufferParams(0)\n val flow = BufferParams(1, true, false)\n val pipe = BufferParams(1, false, true)\n}\n\ncase class TriStateValue(value: Boolean, set: Boolean)\n{\n def update(orig: Boolean) = if (set) value else orig\n}\n\nobject TriStateValue\n{\n implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)\n def unset = TriStateValue(false, false)\n}\n\ntrait DirectedBuffers[T] {\n def copyIn(x: BufferParams): T\n def copyOut(x: BufferParams): T\n def copyInOut(x: BufferParams): T\n}\n\ntrait IdMapEntry {\n def name: String\n def from: IdRange\n def to: IdRange\n def isCache: Boolean\n def requestFifo: Boolean\n def maxTransactionsInFlight: Option[Int]\n def pretty(fmt: String) =\n if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5\n fmt.format(to.start, to.end, from.start, from.end, s\"\"\"\"$name\"\"\"\", if (isCache) \" [CACHE]\" else \"\", if (requestFifo) \" [FIFO]\" else \"\")\n } else {\n fmt.format(from.start, from.end, s\"\"\"\"$name\"\"\"\", if (isCache) \" [CACHE]\" else \"\", if (requestFifo) \" [FIFO]\" else \"\")\n }\n}\n\nabstract class IdMap[T <: IdMapEntry] {\n protected val fmt: String\n val mapping: Seq[T]\n def pretty: String = mapping.map(_.pretty(fmt)).mkString(\",\\n\")\n}\nFile MixedNode.scala:\npackage org.chipsalliance.diplomacy.nodes\n\nimport chisel3.{Data, DontCare, Wire}\nimport chisel3.experimental.SourceInfo\nimport org.chipsalliance.cde.config.{Field, Parameters}\n\nimport org.chipsalliance.diplomacy.ValName\nimport org.chipsalliance.diplomacy.sourceLine\n\n/** One side metadata of a [[Dangle]].\n *\n * Describes one side of an edge going into or out of a [[BaseNode]].\n *\n * @param serial\n * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.\n * @param index\n * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.\n */\ncase class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {\n\n import scala.math.Ordered.orderingToOrdered\n\n def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))\n}\n\n/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]\n * connects.\n *\n * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,\n * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].\n *\n * @param source\n * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within\n * that [[BaseNode]].\n * @param sink\n * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that\n * [[BaseNode]].\n * @param flipped\n * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to\n * `danglesIn`.\n * @param dataOpt\n * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module\n */\ncase class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {\n def data = dataOpt.get\n}\n\n/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often\n * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually\n * implement the protocol.\n */\ncase class Edges[EI, EO](in: Seq[EI], out: Seq[EO])\n\n/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */\ncase object MonitorsEnabled extends Field[Boolean](true)\n\n/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.\n *\n * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but\n * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink\n * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the\n * [[LazyModule]].\n */\ncase object RenderFlipped extends Field[Boolean](false)\n\n/** The sealed node class in the package, all node are derived from it.\n *\n * @param inner\n * Sink interface implementation.\n * @param outer\n * Source interface implementation.\n * @param valName\n * val name of this node.\n * @tparam DI\n * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters\n * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected\n * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port\n * parameters.\n * @tparam UI\n * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing\n * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.\n * @tparam EI\n * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers\n * specified for a sink according to protocol.\n * @tparam BI\n * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.\n * It should extends from [[chisel3.Data]], which represents the real hardware.\n * @tparam DO\n * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters\n * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.\n * @tparam UO\n * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing\n * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].\n * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.\n * @tparam EO\n * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers\n * specified for a source according to protocol.\n * @tparam BO\n * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source\n * interface. It should extends from [[chisel3.Data]], which represents the real hardware.\n *\n * @note\n * Call Graph of [[MixedNode]]\n * - line `─`: source is process by a function and generate pass to others\n * - Arrow `→`: target of arrow is generated by source\n *\n * {{{\n * (from the other node)\n * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐\n * ↓ │\n * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │\n * [[InwardNode.accPI]] │ │ │\n * │ │ (based on protocol) │\n * │ │ [[MixedNode.inner.edgeI]] │\n * │ │ ↓ │\n * ↓ │ │ │\n * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │\n * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │\n * │ │ ↑ │ │ │\n * │ │ │ [[OutwardNode.doParams]] │ │\n * │ │ │ (from the other node) │ │\n * │ │ │ │ │ │\n * │ │ │ │ │ │\n * │ │ │ └────────┬──────────────┤ │\n * │ │ │ │ │ │\n * │ │ │ │ (based on protocol) │\n * │ │ │ │ [[MixedNode.inner.edgeI]] │\n * │ │ │ │ │ │\n * │ │ (from the other node) │ ↓ │\n * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │\n * │ ↑ ↑ │ │ ↓ │\n * │ │ │ │ │ [[MixedNode.in]] │\n * │ │ │ │ ↓ ↑ │\n * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │\n * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │\n * │ │ │ [[MixedNode.bundleOut]]─┐ │ │\n * │ │ │ ↑ ↓ │ │\n * │ │ │ │ [[MixedNode.out]] │ │\n * │ ↓ ↓ │ ↑ │ │\n * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │\n * │ │ (from the other node) ↑ │ │\n * │ │ │ │ │ │\n * │ │ │ [[MixedNode.outer.edgeO]] │ │\n * │ │ │ (based on protocol) │ │\n * │ │ │ │ │ │\n * │ │ │ ┌────────────────────────────────────────┤ │ │\n * │ │ │ │ │ │ │\n * │ │ │ │ │ │ │\n * │ │ │ │ │ │ │\n * (immobilize after elaboration)│ ↓ │ │ │ │\n * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │\n * ↑ (inward port from [[OutwardNode]]) │ │ │ │\n * │ ┌─────────────────────────────────────────┤ │ │ │\n * │ │ │ │ │ │\n * │ │ │ │ │ │\n * [[OutwardNode.accPO]] │ ↓ │ │ │\n * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │\n * │ ↑ │ │\n * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │\n * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘\n * }}}\n */\nabstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](\n val inner: InwardNodeImp[DI, UI, EI, BI],\n val outer: OutwardNodeImp[DO, UO, EO, BO]\n)(\n implicit valName: ValName)\n extends BaseNode\n with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]\n with InwardNode[DI, UI, BI]\n with OutwardNode[DO, UO, BO] {\n // Generate a [[NodeHandle]] with inward and outward node are both this node.\n val inward = this\n val outward = this\n\n /** Debug info of nodes binding. */\n def bindingInfo: String = s\"\"\"$iBindingInfo\n |$oBindingInfo\n |\"\"\".stripMargin\n\n /** Debug info of ports connecting. */\n def connectedPortsInfo: String = s\"\"\"${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(\",\")}]\n |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(\",\")}]\n |\"\"\".stripMargin\n\n /** Debug info of parameters propagations. */\n def parametersInfo: String = s\"\"\"${doParams.size} downstream outward parameters: [${doParams.mkString(\",\")}]\n |${uoParams.size} upstream outward parameters: [${uoParams.mkString(\",\")}]\n |${diParams.size} downstream inward parameters: [${diParams.mkString(\",\")}]\n |${uiParams.size} upstream inward parameters: [${uiParams.mkString(\",\")}]\n |\"\"\".stripMargin\n\n /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and\n * [[MixedNode.iPortMapping]].\n *\n * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward\n * stars and outward stars.\n *\n * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type\n * of node.\n *\n * @param iKnown\n * Number of known-size ([[BIND_ONCE]]) input bindings.\n * @param oKnown\n * Number of known-size ([[BIND_ONCE]]) output bindings.\n * @param iStar\n * Number of unknown size ([[BIND_STAR]]) input bindings.\n * @param oStar\n * Number of unknown size ([[BIND_STAR]]) output bindings.\n * @return\n * A Tuple of the resolved number of input and output connections.\n */\n protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)\n\n /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output\n * ports.\n *\n * @param n\n * The size of the output sequence to generate.\n * @param p\n * Sequence of downward-flowing input parameters of this node.\n * @return\n * A `n`-sized sequence of downward-flowing output edge parameters.\n */\n protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]\n\n /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].\n *\n * @param n\n * Size of the output sequence.\n * @param p\n * Upward-flowing output edge parameters.\n * @return\n * A n-sized sequence of upward-flowing input edge parameters.\n */\n protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]\n\n /** @return\n * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with\n * [[BIND_STAR]].\n */\n protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)\n\n /** @return\n * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of\n * output bindings bound with [[BIND_STAR]].\n */\n protected[diplomacy] lazy val sourceCard: Int =\n iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)\n\n /** @return list of nodes involved in flex bindings with this node. */\n protected[diplomacy] lazy val flexes: Seq[BaseNode] =\n oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)\n\n /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin\n * greedily taking up the remaining connections.\n *\n * @return\n * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return\n * value is not relevant.\n */\n protected[diplomacy] lazy val flexOffset: Int = {\n\n /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex\n * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a\n * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of\n * each node in the current set and decide whether they should be added to the set or not.\n *\n * @return\n * the mapping of [[BaseNode]] indexed by their serial numbers.\n */\n def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {\n if (visited.contains(v.serial) || !v.flexibleArityDirection) {\n visited\n } else {\n v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))\n }\n }\n\n /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.\n *\n * @example\n * {{{\n * a :*=* b :*=* c\n * d :*=* b\n * e :*=* f\n * }}}\n *\n * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`\n */\n val flexSet = DFS(this, Map()).values\n\n /** The total number of :*= operators where we're on the left. */\n val allSink = flexSet.map(_.sinkCard).sum\n\n /** The total number of :=* operators used when we're on the right. */\n val allSource = flexSet.map(_.sourceCard).sum\n\n require(\n allSink == 0 || allSource == 0,\n s\"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction.\"\n )\n allSink - allSource\n }\n\n /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */\n protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {\n if (flexibleArityDirection) flexOffset\n else if (n.flexibleArityDirection) n.flexOffset\n else 0\n }\n\n /** For a node which is connected between two nodes, select the one that will influence the direction of the flex\n * resolution.\n */\n protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {\n val dir = edgeArityDirection(n)\n if (dir < 0) l\n else if (dir > 0) r\n else 1\n }\n\n /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */\n private var starCycleGuard = false\n\n /** Resolve all the star operators into concrete indicies. As connections are being made, some may be \"star\"\n * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also\n * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct\n * edge parameters and later build up correct bundle connections.\n *\n * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding\n * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort\n * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=\n * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`\n */\n protected[diplomacy] lazy val (\n oPortMapping: Seq[(Int, Int)],\n iPortMapping: Seq[(Int, Int)],\n oStar: Int,\n iStar: Int\n ) = {\n try {\n if (starCycleGuard) throw StarCycleException()\n starCycleGuard = true\n // For a given node N...\n // Number of foo :=* N\n // + Number of bar :=* foo :*=* N\n val oStars = oBindings.count { case (_, n, b, _, _) =>\n b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)\n }\n // Number of N :*= foo\n // + Number of N :*=* foo :*= bar\n val iStars = iBindings.count { case (_, n, b, _, _) =>\n b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)\n }\n // 1 for foo := N\n // + bar.iStar for bar :*= foo :*=* N\n // + foo.iStar for foo :*= N\n // + 0 for foo :=* N\n val oKnown = oBindings.map { case (_, n, b, _, _) =>\n b match {\n case BIND_ONCE => 1\n case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)\n case BIND_QUERY => n.iStar\n case BIND_STAR => 0\n }\n }.sum\n // 1 for N := foo\n // + bar.oStar for N :*=* foo :=* bar\n // + foo.oStar for N :=* foo\n // + 0 for N :*= foo\n val iKnown = iBindings.map { case (_, n, b, _, _) =>\n b match {\n case BIND_ONCE => 1\n case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)\n case BIND_QUERY => n.oStar\n case BIND_STAR => 0\n }\n }.sum\n // Resolve star depends on the node subclass to implement the algorithm for this.\n val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)\n // Cumulative list of resolved outward binding range starting points\n val oSum = oBindings.map { case (_, n, b, _, _) =>\n b match {\n case BIND_ONCE => 1\n case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)\n case BIND_QUERY => n.iStar\n case BIND_STAR => oStar\n }\n }.scanLeft(0)(_ + _)\n // Cumulative list of resolved inward binding range starting points\n val iSum = iBindings.map { case (_, n, b, _, _) =>\n b match {\n case BIND_ONCE => 1\n case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)\n case BIND_QUERY => n.oStar\n case BIND_STAR => iStar\n }\n }.scanLeft(0)(_ + _)\n // Create ranges for each binding based on the running sums and return\n // those along with resolved values for the star operations.\n (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)\n } catch {\n case c: StarCycleException => throw c.copy(loop = context +: c.loop)\n }\n }\n\n /** Sequence of inward ports.\n *\n * This should be called after all star bindings are resolved.\n *\n * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.\n * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this\n * connection was made in the source code.\n */\n protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =\n oBindings.flatMap { case (i, n, _, p, s) =>\n // for each binding operator in this node, look at what it connects to\n val (start, end) = n.iPortMapping(i)\n (start until end).map { j => (j, n, p, s) }\n }\n\n /** Sequence of outward ports.\n *\n * This should be called after all star bindings are resolved.\n *\n * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of\n * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection\n * was made in the source code.\n */\n protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =\n iBindings.flatMap { case (i, n, _, p, s) =>\n // query this port index range of this node in the other side of node.\n val (start, end) = n.oPortMapping(i)\n (start until end).map { j => (j, n, p, s) }\n }\n\n // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree\n // Thus, there must exist an Eulerian path and the below algorithms terminate\n @scala.annotation.tailrec\n private def oTrace(\n tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)\n ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {\n case (i, n, p, s) => n.iForward(i) match {\n case None => (i, n, p, s)\n case Some((j, m)) => oTrace((j, m, p, s))\n }\n }\n\n @scala.annotation.tailrec\n private def iTrace(\n tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)\n ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {\n case (i, n, p, s) => n.oForward(i) match {\n case None => (i, n, p, s)\n case Some((j, m)) => iTrace((j, m, p, s))\n }\n }\n\n /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.\n *\n * Each Port is a tuple of:\n * - Numeric index of this binding in the [[InwardNode]] on the other end.\n * - [[InwardNode]] on the other end of this binding.\n * - A view of [[Parameters]] where the binding occurred.\n * - [[SourceInfo]] for source-level error reporting.\n */\n lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)\n\n /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.\n *\n * Each Port is a tuple of:\n * - numeric index of this binding in [[OutwardNode]] on the other end.\n * - [[OutwardNode]] on the other end of this binding.\n * - a view of [[Parameters]] where the binding occurred.\n * - [[SourceInfo]] for source-level error reporting.\n */\n lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)\n\n private var oParamsCycleGuard = false\n protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }\n protected[diplomacy] lazy val doParams: Seq[DO] = {\n try {\n if (oParamsCycleGuard) throw DownwardCycleException()\n oParamsCycleGuard = true\n val o = mapParamsD(oPorts.size, diParams)\n require(\n o.size == oPorts.size,\n s\"\"\"Diplomacy has detected a problem with your graph:\n |At the following node, the number of outward ports should equal the number of produced outward parameters.\n |$context\n |$connectedPortsInfo\n |Downstreamed inward parameters: [${diParams.mkString(\",\")}]\n |Produced outward parameters: [${o.mkString(\",\")}]\n |\"\"\".stripMargin\n )\n o.map(outer.mixO(_, this))\n } catch {\n case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)\n }\n }\n\n private var iParamsCycleGuard = false\n protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }\n protected[diplomacy] lazy val uiParams: Seq[UI] = {\n try {\n if (iParamsCycleGuard) throw UpwardCycleException()\n iParamsCycleGuard = true\n val i = mapParamsU(iPorts.size, uoParams)\n require(\n i.size == iPorts.size,\n s\"\"\"Diplomacy has detected a problem with your graph:\n |At the following node, the number of inward ports should equal the number of produced inward parameters.\n |$context\n |$connectedPortsInfo\n |Upstreamed outward parameters: [${uoParams.mkString(\",\")}]\n |Produced inward parameters: [${i.mkString(\",\")}]\n |\"\"\".stripMargin\n )\n i.map(inner.mixI(_, this))\n } catch {\n case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)\n }\n }\n\n /** Outward edge parameters. */\n protected[diplomacy] lazy val edgesOut: Seq[EO] =\n (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }\n\n /** Inward edge parameters. */\n protected[diplomacy] lazy val edgesIn: Seq[EI] =\n (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }\n\n /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.\n *\n * If you need to access to the edges of a foreign Node, use this method (in/out create bundles).\n */\n lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)\n\n /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */\n protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>\n val x = Wire(outer.bundleO(e)).suggestName(s\"${valName.value}Out\")\n // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,\n // In the future, we should add an option to decide whether allowing unconnected in the LazyModule\n x := DontCare\n x\n }\n\n /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */\n protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>\n val x = Wire(inner.bundleI(e)).suggestName(s\"${valName.value}In\")\n // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,\n // In the future, we should add an option to decide whether allowing unconnected in the LazyModule\n x := DontCare\n x\n }\n\n private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>\n Dangle(\n source = HalfEdge(serial, i),\n sink = HalfEdge(n.serial, j),\n flipped = false,\n name = wirePrefix + \"out\",\n dataOpt = None\n )\n }\n private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>\n Dangle(\n source = HalfEdge(n.serial, j),\n sink = HalfEdge(serial, i),\n flipped = true,\n name = wirePrefix + \"in\",\n dataOpt = None\n )\n }\n\n /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */\n protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>\n d.copy(dataOpt = Some(bundleOut(i)))\n }\n\n /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */\n protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>\n d.copy(dataOpt = Some(bundleIn(i)))\n }\n\n private[diplomacy] var instantiated = false\n\n /** Gather Bundle and edge parameters of outward ports.\n *\n * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within\n * [[LazyModuleImp]] code or after its instantiation has completed.\n */\n def out: Seq[(BO, EO)] = {\n require(\n instantiated,\n s\"$name.out should not be called until after instantiation of its parent LazyModule.module has begun\"\n )\n bundleOut.zip(edgesOut)\n }\n\n /** Gather Bundle and edge parameters of inward ports.\n *\n * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within\n * [[LazyModuleImp]] code or after its instantiation has completed.\n */\n def in: Seq[(BI, EI)] = {\n require(\n instantiated,\n s\"$name.in should not be called until after instantiation of its parent LazyModule.module has begun\"\n )\n bundleIn.zip(edgesIn)\n }\n\n /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,\n * instantiate monitors on all input ports if appropriate, and return all the dangles of this node.\n */\n protected[diplomacy] def instantiate(): Seq[Dangle] = {\n instantiated = true\n if (!circuitIdentity) {\n (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }\n }\n danglesOut ++ danglesIn\n }\n\n protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn\n\n /** Connects the outward part of a node with the inward part of this node. */\n protected[diplomacy] def bind(\n h: OutwardNode[DI, UI, BI],\n binding: NodeBinding\n )(\n implicit p: Parameters,\n sourceInfo: SourceInfo\n ): Unit = {\n val x = this // x := y\n val y = h\n sourceLine(sourceInfo, \" at \", \"\")\n val i = x.iPushed\n val o = y.oPushed\n y.oPush(\n i,\n x,\n binding match {\n case BIND_ONCE => BIND_ONCE\n case BIND_FLEX => BIND_FLEX\n case BIND_STAR => BIND_QUERY\n case BIND_QUERY => BIND_STAR\n }\n )\n x.iPush(o, y, binding)\n }\n\n /* Metadata for printing the node graph. */\n def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>\n val re = inner.render(e)\n (n, re.copy(flipped = re.flipped != p(RenderFlipped)))\n }\n\n /** Metadata for printing the node graph */\n def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }\n}\nFile Edges.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.tilelink\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.experimental.SourceInfo\nimport org.chipsalliance.cde.config.Parameters\nimport freechips.rocketchip.util._\n\nclass TLEdge(\n client: TLClientPortParameters,\n manager: TLManagerPortParameters,\n params: Parameters,\n sourceInfo: SourceInfo)\n extends TLEdgeParameters(client, manager, params, sourceInfo)\n{\n def isAligned(address: UInt, lgSize: UInt): Bool = {\n if (maxLgSize == 0) true.B else {\n val mask = UIntToOH1(lgSize, maxLgSize)\n (address & mask) === 0.U\n }\n }\n\n def mask(address: UInt, lgSize: UInt): UInt =\n MaskGen(address, lgSize, manager.beatBytes)\n\n def staticHasData(bundle: TLChannel): Option[Boolean] = {\n bundle match {\n case _:TLBundleA => {\n // Do there exist A messages with Data?\n val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial\n // Do there exist A messages without Data?\n val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint\n // Statically optimize the case where hasData is a constant\n if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None\n }\n case _:TLBundleB => {\n // Do there exist B messages with Data?\n val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial\n // Do there exist B messages without Data?\n val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint\n // Statically optimize the case where hasData is a constant\n if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None\n }\n case _:TLBundleC => {\n // Do there eixst C messages with Data?\n val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe\n // Do there exist C messages without Data?\n val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe\n if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None\n }\n case _:TLBundleD => {\n // Do there eixst D messages with Data?\n val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB\n // Do there exist D messages without Data?\n val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT\n if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None\n }\n case _:TLBundleE => Some(false)\n }\n }\n\n def isRequest(x: TLChannel): Bool = {\n x match {\n case a: TLBundleA => true.B\n case b: TLBundleB => true.B\n case c: TLBundleC => c.opcode(2) && c.opcode(1)\n // opcode === TLMessages.Release ||\n // opcode === TLMessages.ReleaseData\n case d: TLBundleD => d.opcode(2) && !d.opcode(1)\n // opcode === TLMessages.Grant ||\n // opcode === TLMessages.GrantData\n case e: TLBundleE => false.B\n }\n }\n\n def isResponse(x: TLChannel): Bool = {\n x match {\n case a: TLBundleA => false.B\n case b: TLBundleB => false.B\n case c: TLBundleC => !c.opcode(2) || !c.opcode(1)\n // opcode =/= TLMessages.Release &&\n // opcode =/= TLMessages.ReleaseData\n case d: TLBundleD => true.B // Grant isResponse + isRequest\n case e: TLBundleE => true.B\n }\n }\n\n def hasData(x: TLChannel): Bool = {\n val opdata = x match {\n case a: TLBundleA => !a.opcode(2)\n // opcode === TLMessages.PutFullData ||\n // opcode === TLMessages.PutPartialData ||\n // opcode === TLMessages.ArithmeticData ||\n // opcode === TLMessages.LogicalData\n case b: TLBundleB => !b.opcode(2)\n // opcode === TLMessages.PutFullData ||\n // opcode === TLMessages.PutPartialData ||\n // opcode === TLMessages.ArithmeticData ||\n // opcode === TLMessages.LogicalData\n case c: TLBundleC => c.opcode(0)\n // opcode === TLMessages.AccessAckData ||\n // opcode === TLMessages.ProbeAckData ||\n // opcode === TLMessages.ReleaseData\n case d: TLBundleD => d.opcode(0)\n // opcode === TLMessages.AccessAckData ||\n // opcode === TLMessages.GrantData\n case e: TLBundleE => false.B\n }\n staticHasData(x).map(_.B).getOrElse(opdata)\n }\n\n def opcode(x: TLDataChannel): UInt = {\n x match {\n case a: TLBundleA => a.opcode\n case b: TLBundleB => b.opcode\n case c: TLBundleC => c.opcode\n case d: TLBundleD => d.opcode\n }\n }\n\n def param(x: TLDataChannel): UInt = {\n x match {\n case a: TLBundleA => a.param\n case b: TLBundleB => b.param\n case c: TLBundleC => c.param\n case d: TLBundleD => d.param\n }\n }\n\n def size(x: TLDataChannel): UInt = {\n x match {\n case a: TLBundleA => a.size\n case b: TLBundleB => b.size\n case c: TLBundleC => c.size\n case d: TLBundleD => d.size\n }\n }\n\n def data(x: TLDataChannel): UInt = {\n x match {\n case a: TLBundleA => a.data\n case b: TLBundleB => b.data\n case c: TLBundleC => c.data\n case d: TLBundleD => d.data\n }\n }\n\n def corrupt(x: TLDataChannel): Bool = {\n x match {\n case a: TLBundleA => a.corrupt\n case b: TLBundleB => b.corrupt\n case c: TLBundleC => c.corrupt\n case d: TLBundleD => d.corrupt\n }\n }\n\n def mask(x: TLAddrChannel): UInt = {\n x match {\n case a: TLBundleA => a.mask\n case b: TLBundleB => b.mask\n case c: TLBundleC => mask(c.address, c.size)\n }\n }\n\n def full_mask(x: TLAddrChannel): UInt = {\n x match {\n case a: TLBundleA => mask(a.address, a.size)\n case b: TLBundleB => mask(b.address, b.size)\n case c: TLBundleC => mask(c.address, c.size)\n }\n }\n\n def address(x: TLAddrChannel): UInt = {\n x match {\n case a: TLBundleA => a.address\n case b: TLBundleB => b.address\n case c: TLBundleC => c.address\n }\n }\n\n def source(x: TLDataChannel): UInt = {\n x match {\n case a: TLBundleA => a.source\n case b: TLBundleB => b.source\n case c: TLBundleC => c.source\n case d: TLBundleD => d.source\n }\n }\n\n def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)\n def addr_lo(x: UInt): UInt =\n if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)\n\n def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))\n def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))\n\n def numBeats(x: TLChannel): UInt = {\n x match {\n case _: TLBundleE => 1.U\n case bundle: TLDataChannel => {\n val hasData = this.hasData(bundle)\n val size = this.size(bundle)\n val cutoff = log2Ceil(manager.beatBytes)\n val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U\n val decode = UIntToOH(size, maxLgSize+1) >> cutoff\n Mux(hasData, decode | small.asUInt, 1.U)\n }\n }\n }\n\n def numBeats1(x: TLChannel): UInt = {\n x match {\n case _: TLBundleE => 0.U\n case bundle: TLDataChannel => {\n if (maxLgSize == 0) {\n 0.U\n } else {\n val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)\n Mux(hasData(bundle), decode, 0.U)\n }\n }\n }\n }\n\n def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {\n val beats1 = numBeats1(bits)\n val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))\n val counter1 = counter - 1.U\n val first = counter === 0.U\n val last = counter === 1.U || beats1 === 0.U\n val done = last && fire\n val count = (beats1 & ~counter1)\n when (fire) {\n counter := Mux(first, beats1, counter1)\n }\n (first, last, done, count)\n }\n\n def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1\n def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)\n def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)\n\n def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2\n def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)\n def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)\n\n def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3\n def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)\n def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)\n\n def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {\n val r = firstlastHelper(bits, fire)\n (r._1, r._2, r._3)\n }\n def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)\n def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)\n\n def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {\n val r = firstlastHelper(bits, fire)\n (r._1, r._2, r._3, r._4)\n }\n def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)\n def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)\n\n def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {\n val r = firstlastHelper(bits, fire)\n (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))\n }\n def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)\n def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)\n\n // Does the request need T permissions to be executed?\n def needT(a: TLBundleA): Bool = {\n val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(\n TLPermissions.NtoB -> false.B,\n TLPermissions.NtoT -> true.B,\n TLPermissions.BtoT -> true.B))\n MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(\n TLMessages.PutFullData -> true.B,\n TLMessages.PutPartialData -> true.B,\n TLMessages.ArithmeticData -> true.B,\n TLMessages.LogicalData -> true.B,\n TLMessages.Get -> false.B,\n TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(\n TLHints.PREFETCH_READ -> false.B,\n TLHints.PREFETCH_WRITE -> true.B)),\n TLMessages.AcquireBlock -> acq_needT,\n TLMessages.AcquirePerm -> acq_needT))\n }\n\n // This is a very expensive circuit; use only if you really mean it!\n def inFlight(x: TLBundle): (UInt, UInt) = {\n val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))\n val bce = manager.anySupportAcquireB && client.anySupportProbe\n\n val (a_first, a_last, _) = firstlast(x.a)\n val (b_first, b_last, _) = firstlast(x.b)\n val (c_first, c_last, _) = firstlast(x.c)\n val (d_first, d_last, _) = firstlast(x.d)\n val (e_first, e_last, _) = firstlast(x.e)\n\n val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))\n val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))\n val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))\n val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))\n val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))\n\n val a_inc = x.a.fire && a_first && a_request\n val b_inc = x.b.fire && b_first && b_request\n val c_inc = x.c.fire && c_first && c_request\n val d_inc = x.d.fire && d_first && d_request\n val e_inc = x.e.fire && e_first && e_request\n val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))\n\n val a_dec = x.a.fire && a_last && a_response\n val b_dec = x.b.fire && b_last && b_response\n val c_dec = x.c.fire && c_last && c_response\n val d_dec = x.d.fire && d_last && d_response\n val e_dec = x.e.fire && e_last && e_response\n val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))\n\n val next_flight = flight + PopCount(inc) - PopCount(dec)\n flight := next_flight\n\n (flight, next_flight)\n }\n\n def prettySourceMapping(context: String): String = {\n s\"TL-Source mapping for $context:\\n${(new TLSourceIdMap(client)).pretty}\\n\"\n }\n}\n\nclass TLEdgeOut(\n client: TLClientPortParameters,\n manager: TLManagerPortParameters,\n params: Parameters,\n sourceInfo: SourceInfo)\n extends TLEdge(client, manager, params, sourceInfo)\n{\n // Transfers\n def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {\n require (manager.anySupportAcquireB, s\"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsAcquireBFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.AcquireBlock\n a.param := growPermissions\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := DontCare\n a.corrupt := false.B\n (legal, a)\n }\n\n def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {\n require (manager.anySupportAcquireB, s\"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsAcquireBFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.AcquirePerm\n a.param := growPermissions\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := DontCare\n a.corrupt := false.B\n (legal, a)\n }\n\n def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {\n require (manager.anySupportAcquireB, s\"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsAcquireBFast(toAddress, lgSize)\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.Release\n c.param := shrinkPermissions\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := DontCare\n c.corrupt := false.B\n (legal, c)\n }\n\n def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {\n require (manager.anySupportAcquireB, s\"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsAcquireBFast(toAddress, lgSize)\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.ReleaseData\n c.param := shrinkPermissions\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := data\n c.corrupt := corrupt\n (legal, c)\n }\n\n def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =\n Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)\n\n def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =\n ProbeAck(b.source, b.address, b.size, reportPermissions)\n\n def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.ProbeAck\n c.param := reportPermissions\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := DontCare\n c.corrupt := false.B\n c\n }\n\n def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =\n ProbeAck(b.source, b.address, b.size, reportPermissions, data)\n\n def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.ProbeAckData\n c.param := reportPermissions\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := data\n c.corrupt := corrupt\n c\n }\n\n def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =\n ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)\n\n def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)\n def GrantAck(toSink: UInt): TLBundleE = {\n val e = Wire(new TLBundleE(bundle))\n e.sink := toSink\n e\n }\n\n // Accesses\n def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {\n require (manager.anySupportGet, s\"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsGetFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.Get\n a.param := 0.U\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := DontCare\n a.corrupt := false.B\n (legal, a)\n }\n\n def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =\n Put(fromSource, toAddress, lgSize, data, false.B)\n\n def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {\n require (manager.anySupportPutFull, s\"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsPutFullFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.PutFullData\n a.param := 0.U\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := data\n a.corrupt := corrupt\n (legal, a)\n }\n\n def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =\n Put(fromSource, toAddress, lgSize, data, mask, false.B)\n\n def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {\n require (manager.anySupportPutPartial, s\"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsPutPartialFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.PutPartialData\n a.param := 0.U\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask\n a.data := data\n a.corrupt := corrupt\n (legal, a)\n }\n\n def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {\n require (manager.anySupportArithmetic, s\"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsArithmeticFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.ArithmeticData\n a.param := atomic\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := data\n a.corrupt := corrupt\n (legal, a)\n }\n\n def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {\n require (manager.anySupportLogical, s\"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsLogicalFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.LogicalData\n a.param := atomic\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := data\n a.corrupt := corrupt\n (legal, a)\n }\n\n def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {\n require (manager.anySupportHint, s\"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsHintFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.Hint\n a.param := param\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := DontCare\n a.corrupt := false.B\n (legal, a)\n }\n\n def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)\n def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.AccessAck\n c.param := 0.U\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := DontCare\n c.corrupt := false.B\n c\n }\n\n def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)\n def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)\n def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)\n def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.AccessAckData\n c.param := 0.U\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := data\n c.corrupt := corrupt\n c\n }\n\n def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)\n def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.HintAck\n c.param := 0.U\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := DontCare\n c.corrupt := false.B\n c\n }\n}\n\nclass TLEdgeIn(\n client: TLClientPortParameters,\n manager: TLManagerPortParameters,\n params: Parameters,\n sourceInfo: SourceInfo)\n extends TLEdge(client, manager, params, sourceInfo)\n{\n private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {\n val todo = x.filter(!_.isEmpty)\n val heads = todo.map(_.head)\n val tails = todo.map(_.tail)\n if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }\n }\n\n // Transfers\n def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {\n require (client.anySupportProbe, s\"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}\")\n val legal = client.supportsProbe(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.Probe\n b.param := capPermissions\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask(fromAddress, lgSize)\n b.data := DontCare\n b.corrupt := false.B\n (legal, b)\n }\n\n def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)\n def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {\n val d = Wire(new TLBundleD(bundle))\n d.opcode := TLMessages.Grant\n d.param := capPermissions\n d.size := lgSize\n d.source := toSource\n d.sink := fromSink\n d.denied := denied\n d.user := DontCare\n d.echo := DontCare\n d.data := DontCare\n d.corrupt := false.B\n d\n }\n\n def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)\n def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {\n val d = Wire(new TLBundleD(bundle))\n d.opcode := TLMessages.GrantData\n d.param := capPermissions\n d.size := lgSize\n d.source := toSource\n d.sink := fromSink\n d.denied := denied\n d.user := DontCare\n d.echo := DontCare\n d.data := data\n d.corrupt := corrupt\n d\n }\n\n def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)\n def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {\n val d = Wire(new TLBundleD(bundle))\n d.opcode := TLMessages.ReleaseAck\n d.param := 0.U\n d.size := lgSize\n d.source := toSource\n d.sink := 0.U\n d.denied := denied\n d.user := DontCare\n d.echo := DontCare\n d.data := DontCare\n d.corrupt := false.B\n d\n }\n\n // Accesses\n def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {\n require (client.anySupportGet, s\"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}\")\n val legal = client.supportsGet(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.Get\n b.param := 0.U\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask(fromAddress, lgSize)\n b.data := DontCare\n b.corrupt := false.B\n (legal, b)\n }\n\n def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =\n Put(fromAddress, toSource, lgSize, data, false.B)\n\n def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {\n require (client.anySupportPutFull, s\"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}\")\n val legal = client.supportsPutFull(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.PutFullData\n b.param := 0.U\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask(fromAddress, lgSize)\n b.data := data\n b.corrupt := corrupt\n (legal, b)\n }\n\n def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =\n Put(fromAddress, toSource, lgSize, data, mask, false.B)\n\n def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {\n require (client.anySupportPutPartial, s\"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}\")\n val legal = client.supportsPutPartial(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.PutPartialData\n b.param := 0.U\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask\n b.data := data\n b.corrupt := corrupt\n (legal, b)\n }\n\n def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {\n require (client.anySupportArithmetic, s\"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}\")\n val legal = client.supportsArithmetic(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.ArithmeticData\n b.param := atomic\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask(fromAddress, lgSize)\n b.data := data\n b.corrupt := corrupt\n (legal, b)\n }\n\n def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {\n require (client.anySupportLogical, s\"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}\")\n val legal = client.supportsLogical(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.LogicalData\n b.param := atomic\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask(fromAddress, lgSize)\n b.data := data\n b.corrupt := corrupt\n (legal, b)\n }\n\n def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {\n require (client.anySupportHint, s\"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}\")\n val legal = client.supportsHint(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.Hint\n b.param := param\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask(fromAddress, lgSize)\n b.data := DontCare\n b.corrupt := false.B\n (legal, b)\n }\n\n def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)\n def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)\n def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)\n def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {\n val d = Wire(new TLBundleD(bundle))\n d.opcode := TLMessages.AccessAck\n d.param := 0.U\n d.size := lgSize\n d.source := toSource\n d.sink := 0.U\n d.denied := denied\n d.user := DontCare\n d.echo := DontCare\n d.data := DontCare\n d.corrupt := false.B\n d\n }\n\n def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)\n def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)\n def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)\n def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {\n val d = Wire(new TLBundleD(bundle))\n d.opcode := TLMessages.AccessAckData\n d.param := 0.U\n d.size := lgSize\n d.source := toSource\n d.sink := 0.U\n d.denied := denied\n d.user := DontCare\n d.echo := DontCare\n d.data := data\n d.corrupt := corrupt\n d\n }\n\n def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)\n def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)\n def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)\n def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {\n val d = Wire(new TLBundleD(bundle))\n d.opcode := TLMessages.HintAck\n d.param := 0.U\n d.size := lgSize\n d.source := toSource\n d.sink := 0.U\n d.denied := denied\n d.user := DontCare\n d.echo := DontCare\n d.data := DontCare\n d.corrupt := false.B\n d\n }\n}\n"},"response":{"kind":"string","value":"module TLFIFOFixer(\t// @[FIFOFixer.scala:50:9]\n input clock,\t// @[FIFOFixer.scala:50:9]\n input reset,\t// @[FIFOFixer.scala:50:9]\n output auto_anon_in_1_a_ready,\t// @[LazyModuleImp.scala:107:25]\n input auto_anon_in_1_a_valid,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_anon_in_1_a_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_anon_in_1_a_bits_param,\t// @[LazyModuleImp.scala:107:25]\n input [3:0] auto_anon_in_1_a_bits_size,\t// @[LazyModuleImp.scala:107:25]\n input auto_anon_in_1_a_bits_source,\t// @[LazyModuleImp.scala:107:25]\n input [31:0] auto_anon_in_1_a_bits_address,\t// @[LazyModuleImp.scala:107:25]\n input auto_anon_in_1_a_bits_user_amba_prot_bufferable,\t// @[LazyModuleImp.scala:107:25]\n input auto_anon_in_1_a_bits_user_amba_prot_modifiable,\t// @[LazyModuleImp.scala:107:25]\n input auto_anon_in_1_a_bits_user_amba_prot_readalloc,\t// @[LazyModuleImp.scala:107:25]\n input auto_anon_in_1_a_bits_user_amba_prot_writealloc,\t// @[LazyModuleImp.scala:107:25]\n input auto_anon_in_1_a_bits_user_amba_prot_privileged,\t// @[LazyModuleImp.scala:107:25]\n input auto_anon_in_1_a_bits_user_amba_prot_secure,\t// @[LazyModuleImp.scala:107:25]\n input auto_anon_in_1_a_bits_user_amba_prot_fetch,\t// @[LazyModuleImp.scala:107:25]\n input [7:0] auto_anon_in_1_a_bits_mask,\t// @[LazyModuleImp.scala:107:25]\n input [63:0] auto_anon_in_1_a_bits_data,\t// @[LazyModuleImp.scala:107:25]\n input auto_anon_in_1_a_bits_corrupt,\t// @[LazyModuleImp.scala:107:25]\n input auto_anon_in_1_d_ready,\t// @[LazyModuleImp.scala:107:25]\n output auto_anon_in_1_d_valid,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_anon_in_1_d_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n output [1:0] auto_anon_in_1_d_bits_param,\t// @[LazyModuleImp.scala:107:25]\n output [3:0] auto_anon_in_1_d_bits_size,\t// @[LazyModuleImp.scala:107:25]\n output auto_anon_in_1_d_bits_source,\t// @[LazyModuleImp.scala:107:25]\n output auto_anon_in_1_d_bits_sink,\t// @[LazyModuleImp.scala:107:25]\n output auto_anon_in_1_d_bits_denied,\t// @[LazyModuleImp.scala:107:25]\n output [63:0] auto_anon_in_1_d_bits_data,\t// @[LazyModuleImp.scala:107:25]\n output auto_anon_in_1_d_bits_corrupt,\t// @[LazyModuleImp.scala:107:25]\n output auto_anon_in_0_a_ready,\t// @[LazyModuleImp.scala:107:25]\n input auto_anon_in_0_a_valid,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_anon_in_0_a_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_anon_in_0_a_bits_param,\t// @[LazyModuleImp.scala:107:25]\n input [3:0] auto_anon_in_0_a_bits_size,\t// @[LazyModuleImp.scala:107:25]\n input [5:0] auto_anon_in_0_a_bits_source,\t// @[LazyModuleImp.scala:107:25]\n input [31:0] auto_anon_in_0_a_bits_address,\t// @[LazyModuleImp.scala:107:25]\n input auto_anon_in_0_a_bits_user_amba_prot_bufferable,\t// @[LazyModuleImp.scala:107:25]\n input auto_anon_in_0_a_bits_user_amba_prot_modifiable,\t// @[LazyModuleImp.scala:107:25]\n input auto_anon_in_0_a_bits_user_amba_prot_readalloc,\t// @[LazyModuleImp.scala:107:25]\n input auto_anon_in_0_a_bits_user_amba_prot_writealloc,\t// @[LazyModuleImp.scala:107:25]\n input auto_anon_in_0_a_bits_user_amba_prot_privileged,\t// @[LazyModuleImp.scala:107:25]\n input auto_anon_in_0_a_bits_user_amba_prot_secure,\t// @[LazyModuleImp.scala:107:25]\n input auto_anon_in_0_a_bits_user_amba_prot_fetch,\t// @[LazyModuleImp.scala:107:25]\n input [7:0] auto_anon_in_0_a_bits_mask,\t// @[LazyModuleImp.scala:107:25]\n input [63:0] auto_anon_in_0_a_bits_data,\t// @[LazyModuleImp.scala:107:25]\n input auto_anon_in_0_a_bits_corrupt,\t// @[LazyModuleImp.scala:107:25]\n input auto_anon_in_0_d_ready,\t// @[LazyModuleImp.scala:107:25]\n output auto_anon_in_0_d_valid,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_anon_in_0_d_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n output [1:0] auto_anon_in_0_d_bits_param,\t// @[LazyModuleImp.scala:107:25]\n output [3:0] auto_anon_in_0_d_bits_size,\t// @[LazyModuleImp.scala:107:25]\n output [5:0] auto_anon_in_0_d_bits_source,\t// @[LazyModuleImp.scala:107:25]\n output auto_anon_in_0_d_bits_sink,\t// @[LazyModuleImp.scala:107:25]\n output auto_anon_in_0_d_bits_denied,\t// @[LazyModuleImp.scala:107:25]\n output [63:0] auto_anon_in_0_d_bits_data,\t// @[LazyModuleImp.scala:107:25]\n output auto_anon_in_0_d_bits_corrupt,\t// @[LazyModuleImp.scala:107:25]\n input auto_anon_out_1_a_ready,\t// @[LazyModuleImp.scala:107:25]\n output auto_anon_out_1_a_valid,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_anon_out_1_a_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_anon_out_1_a_bits_param,\t// @[LazyModuleImp.scala:107:25]\n output [3:0] auto_anon_out_1_a_bits_size,\t// @[LazyModuleImp.scala:107:25]\n output auto_anon_out_1_a_bits_source,\t// @[LazyModuleImp.scala:107:25]\n output [31:0] auto_anon_out_1_a_bits_address,\t// @[LazyModuleImp.scala:107:25]\n output auto_anon_out_1_a_bits_user_amba_prot_bufferable,\t// @[LazyModuleImp.scala:107:25]\n output auto_anon_out_1_a_bits_user_amba_prot_modifiable,\t// @[LazyModuleImp.scala:107:25]\n output auto_anon_out_1_a_bits_user_amba_prot_readalloc,\t// @[LazyModuleImp.scala:107:25]\n output auto_anon_out_1_a_bits_user_amba_prot_writealloc,\t// @[LazyModuleImp.scala:107:25]\n output auto_anon_out_1_a_bits_user_amba_prot_privileged,\t// @[LazyModuleImp.scala:107:25]\n output auto_anon_out_1_a_bits_user_amba_prot_secure,\t// @[LazyModuleImp.scala:107:25]\n output auto_anon_out_1_a_bits_user_amba_prot_fetch,\t// @[LazyModuleImp.scala:107:25]\n output [7:0] auto_anon_out_1_a_bits_mask,\t// @[LazyModuleImp.scala:107:25]\n output [63:0] auto_anon_out_1_a_bits_data,\t// @[LazyModuleImp.scala:107:25]\n output auto_anon_out_1_a_bits_corrupt,\t// @[LazyModuleImp.scala:107:25]\n output auto_anon_out_1_d_ready,\t// @[LazyModuleImp.scala:107:25]\n input auto_anon_out_1_d_valid,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_anon_out_1_d_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_anon_out_1_d_bits_param,\t// @[LazyModuleImp.scala:107:25]\n input [3:0] auto_anon_out_1_d_bits_size,\t// @[LazyModuleImp.scala:107:25]\n input auto_anon_out_1_d_bits_source,\t// @[LazyModuleImp.scala:107:25]\n input auto_anon_out_1_d_bits_sink,\t// @[LazyModuleImp.scala:107:25]\n input auto_anon_out_1_d_bits_denied,\t// @[LazyModuleImp.scala:107:25]\n input [63:0] auto_anon_out_1_d_bits_data,\t// @[LazyModuleImp.scala:107:25]\n input auto_anon_out_1_d_bits_corrupt,\t// @[LazyModuleImp.scala:107:25]\n input auto_anon_out_0_a_ready,\t// @[LazyModuleImp.scala:107:25]\n output auto_anon_out_0_a_valid,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_anon_out_0_a_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_anon_out_0_a_bits_param,\t// @[LazyModuleImp.scala:107:25]\n output [3:0] auto_anon_out_0_a_bits_size,\t// @[LazyModuleImp.scala:107:25]\n output [5:0] auto_anon_out_0_a_bits_source,\t// @[LazyModuleImp.scala:107:25]\n output [31:0] auto_anon_out_0_a_bits_address,\t// @[LazyModuleImp.scala:107:25]\n output auto_anon_out_0_a_bits_user_amba_prot_bufferable,\t// @[LazyModuleImp.scala:107:25]\n output auto_anon_out_0_a_bits_user_amba_prot_modifiable,\t// @[LazyModuleImp.scala:107:25]\n output auto_anon_out_0_a_bits_user_amba_prot_readalloc,\t// @[LazyModuleImp.scala:107:25]\n output auto_anon_out_0_a_bits_user_amba_prot_writealloc,\t// @[LazyModuleImp.scala:107:25]\n output auto_anon_out_0_a_bits_user_amba_prot_privileged,\t// @[LazyModuleImp.scala:107:25]\n output auto_anon_out_0_a_bits_user_amba_prot_secure,\t// @[LazyModuleImp.scala:107:25]\n output auto_anon_out_0_a_bits_user_amba_prot_fetch,\t// @[LazyModuleImp.scala:107:25]\n output [7:0] auto_anon_out_0_a_bits_mask,\t// @[LazyModuleImp.scala:107:25]\n output [63:0] auto_anon_out_0_a_bits_data,\t// @[LazyModuleImp.scala:107:25]\n output auto_anon_out_0_a_bits_corrupt,\t// @[LazyModuleImp.scala:107:25]\n output auto_anon_out_0_d_ready,\t// @[LazyModuleImp.scala:107:25]\n input auto_anon_out_0_d_valid,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_anon_out_0_d_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_anon_out_0_d_bits_param,\t// @[LazyModuleImp.scala:107:25]\n input [3:0] auto_anon_out_0_d_bits_size,\t// @[LazyModuleImp.scala:107:25]\n input [5:0] auto_anon_out_0_d_bits_source,\t// @[LazyModuleImp.scala:107:25]\n input auto_anon_out_0_d_bits_sink,\t// @[LazyModuleImp.scala:107:25]\n input auto_anon_out_0_d_bits_denied,\t// @[LazyModuleImp.scala:107:25]\n input [63:0] auto_anon_out_0_d_bits_data,\t// @[LazyModuleImp.scala:107:25]\n input auto_anon_out_0_d_bits_corrupt\t// @[LazyModuleImp.scala:107:25]\n);\n\n wire auto_anon_in_1_a_valid_0 = auto_anon_in_1_a_valid;\t// @[FIFOFixer.scala:50:9]\n wire [2:0] auto_anon_in_1_a_bits_opcode_0 = auto_anon_in_1_a_bits_opcode;\t// @[FIFOFixer.scala:50:9]\n wire [2:0] auto_anon_in_1_a_bits_param_0 = auto_anon_in_1_a_bits_param;\t// @[FIFOFixer.scala:50:9]\n wire [3:0] auto_anon_in_1_a_bits_size_0 = auto_anon_in_1_a_bits_size;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_in_1_a_bits_source_0 = auto_anon_in_1_a_bits_source;\t// @[FIFOFixer.scala:50:9]\n wire [31:0] auto_anon_in_1_a_bits_address_0 = auto_anon_in_1_a_bits_address;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_in_1_a_bits_user_amba_prot_bufferable_0 = auto_anon_in_1_a_bits_user_amba_prot_bufferable;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_in_1_a_bits_user_amba_prot_modifiable_0 = auto_anon_in_1_a_bits_user_amba_prot_modifiable;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_in_1_a_bits_user_amba_prot_readalloc_0 = auto_anon_in_1_a_bits_user_amba_prot_readalloc;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_in_1_a_bits_user_amba_prot_writealloc_0 = auto_anon_in_1_a_bits_user_amba_prot_writealloc;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_in_1_a_bits_user_amba_prot_privileged_0 = auto_anon_in_1_a_bits_user_amba_prot_privileged;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_in_1_a_bits_user_amba_prot_secure_0 = auto_anon_in_1_a_bits_user_amba_prot_secure;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_in_1_a_bits_user_amba_prot_fetch_0 = auto_anon_in_1_a_bits_user_amba_prot_fetch;\t// @[FIFOFixer.scala:50:9]\n wire [7:0] auto_anon_in_1_a_bits_mask_0 = auto_anon_in_1_a_bits_mask;\t// @[FIFOFixer.scala:50:9]\n wire [63:0] auto_anon_in_1_a_bits_data_0 = auto_anon_in_1_a_bits_data;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_in_1_a_bits_corrupt_0 = auto_anon_in_1_a_bits_corrupt;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_in_1_d_ready_0 = auto_anon_in_1_d_ready;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_in_0_a_valid_0 = auto_anon_in_0_a_valid;\t// @[FIFOFixer.scala:50:9]\n wire [2:0] auto_anon_in_0_a_bits_opcode_0 = auto_anon_in_0_a_bits_opcode;\t// @[FIFOFixer.scala:50:9]\n wire [2:0] auto_anon_in_0_a_bits_param_0 = auto_anon_in_0_a_bits_param;\t// @[FIFOFixer.scala:50:9]\n wire [3:0] auto_anon_in_0_a_bits_size_0 = auto_anon_in_0_a_bits_size;\t// @[FIFOFixer.scala:50:9]\n wire [5:0] auto_anon_in_0_a_bits_source_0 = auto_anon_in_0_a_bits_source;\t// @[FIFOFixer.scala:50:9]\n wire [31:0] auto_anon_in_0_a_bits_address_0 = auto_anon_in_0_a_bits_address;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_in_0_a_bits_user_amba_prot_bufferable_0 = auto_anon_in_0_a_bits_user_amba_prot_bufferable;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_in_0_a_bits_user_amba_prot_modifiable_0 = auto_anon_in_0_a_bits_user_amba_prot_modifiable;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_in_0_a_bits_user_amba_prot_readalloc_0 = auto_anon_in_0_a_bits_user_amba_prot_readalloc;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_in_0_a_bits_user_amba_prot_writealloc_0 = auto_anon_in_0_a_bits_user_amba_prot_writealloc;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_in_0_a_bits_user_amba_prot_privileged_0 = auto_anon_in_0_a_bits_user_amba_prot_privileged;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_in_0_a_bits_user_amba_prot_secure_0 = auto_anon_in_0_a_bits_user_amba_prot_secure;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_in_0_a_bits_user_amba_prot_fetch_0 = auto_anon_in_0_a_bits_user_amba_prot_fetch;\t// @[FIFOFixer.scala:50:9]\n wire [7:0] auto_anon_in_0_a_bits_mask_0 = auto_anon_in_0_a_bits_mask;\t// @[FIFOFixer.scala:50:9]\n wire [63:0] auto_anon_in_0_a_bits_data_0 = auto_anon_in_0_a_bits_data;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_in_0_a_bits_corrupt_0 = auto_anon_in_0_a_bits_corrupt;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_in_0_d_ready_0 = auto_anon_in_0_d_ready;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_out_1_a_ready_0 = auto_anon_out_1_a_ready;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_out_1_d_valid_0 = auto_anon_out_1_d_valid;\t// @[FIFOFixer.scala:50:9]\n wire [2:0] auto_anon_out_1_d_bits_opcode_0 = auto_anon_out_1_d_bits_opcode;\t// @[FIFOFixer.scala:50:9]\n wire [1:0] auto_anon_out_1_d_bits_param_0 = auto_anon_out_1_d_bits_param;\t// @[FIFOFixer.scala:50:9]\n wire [3:0] auto_anon_out_1_d_bits_size_0 = auto_anon_out_1_d_bits_size;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_out_1_d_bits_source_0 = auto_anon_out_1_d_bits_source;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_out_1_d_bits_sink_0 = auto_anon_out_1_d_bits_sink;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_out_1_d_bits_denied_0 = auto_anon_out_1_d_bits_denied;\t// @[FIFOFixer.scala:50:9]\n wire [63:0] auto_anon_out_1_d_bits_data_0 = auto_anon_out_1_d_bits_data;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_out_1_d_bits_corrupt_0 = auto_anon_out_1_d_bits_corrupt;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_out_0_a_ready_0 = auto_anon_out_0_a_ready;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_out_0_d_valid_0 = auto_anon_out_0_d_valid;\t// @[FIFOFixer.scala:50:9]\n wire [2:0] auto_anon_out_0_d_bits_opcode_0 = auto_anon_out_0_d_bits_opcode;\t// @[FIFOFixer.scala:50:9]\n wire [1:0] auto_anon_out_0_d_bits_param_0 = auto_anon_out_0_d_bits_param;\t// @[FIFOFixer.scala:50:9]\n wire [3:0] auto_anon_out_0_d_bits_size_0 = auto_anon_out_0_d_bits_size;\t// @[FIFOFixer.scala:50:9]\n wire [5:0] auto_anon_out_0_d_bits_source_0 = auto_anon_out_0_d_bits_source;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_out_0_d_bits_sink_0 = auto_anon_out_0_d_bits_sink;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_out_0_d_bits_denied_0 = auto_anon_out_0_d_bits_denied;\t// @[FIFOFixer.scala:50:9]\n wire [63:0] auto_anon_out_0_d_bits_data_0 = auto_anon_out_0_d_bits_data;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_out_0_d_bits_corrupt_0 = auto_anon_out_0_d_bits_corrupt;\t// @[FIFOFixer.scala:50:9]\n wire [32:0] _allIDs_FIFOed_T = 33'h1FFFFFFFF;\t// @[FIFOFixer.scala:127:48]\n wire [32:0] _a_notFIFO_T_2 = 33'h0;\t// @[Parameters.scala:137:46]\n wire [32:0] _a_notFIFO_T_3 = 33'h0;\t// @[Parameters.scala:137:46]\n wire [32:0] _a_notFIFO_T_7 = 33'h0;\t// @[Parameters.scala:137:46]\n wire [32:0] _a_notFIFO_T_8 = 33'h0;\t// @[Parameters.scala:137:46]\n wire _flight_WIRE_0 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_1 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_2 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_3 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_4 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_5 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_6 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_7 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_8 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_9 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_10 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_11 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_12 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_13 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_14 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_15 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_16 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_17 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_18 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_19 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_20 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_21 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_22 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_23 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_24 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_25 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_26 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_27 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_28 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_29 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_30 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_31 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_32 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_1_0 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_1_1 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _a_notFIFO_T_4 = 1'h1;\t// @[Parameters.scala:137:59]\n wire _flight_T = 1'h1;\t// @[FIFOFixer.scala:80:65]\n wire _stalls_a_sel_T_2 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _stalls_a_sel_T_4 = 1'h1;\t// @[Parameters.scala:57:20]\n wire _stalls_id_T_2 = 1'h1;\t// @[FIFOFixer.scala:85:59]\n wire _stalls_a_sel_T_7 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _stalls_a_sel_T_9 = 1'h1;\t// @[Parameters.scala:57:20]\n wire _stalls_id_T_6 = 1'h1;\t// @[FIFOFixer.scala:85:59]\n wire _a_notFIFO_T_9 = 1'h1;\t// @[Parameters.scala:137:59]\n wire _flight_T_1 = 1'h1;\t// @[FIFOFixer.scala:80:65]\n wire _anonOut_a_valid_T_3 = 1'h1;\t// @[FIFOFixer.scala:95:50]\n wire _anonOut_a_valid_T_4 = 1'h1;\t// @[FIFOFixer.scala:95:47]\n wire _anonIn_a_ready_T_3 = 1'h1;\t// @[FIFOFixer.scala:96:50]\n wire _anonIn_a_ready_T_4 = 1'h1;\t// @[FIFOFixer.scala:96:47]\n wire anonIn_1_a_ready;\t// @[MixedNode.scala:551:17]\n wire [1:0] _allIDs_FIFOed_T_1 = 2'h3;\t// @[FIFOFixer.scala:127:48]\n wire anonIn_1_a_valid = auto_anon_in_1_a_valid_0;\t// @[FIFOFixer.scala:50:9]\n wire [2:0] anonIn_1_a_bits_opcode = auto_anon_in_1_a_bits_opcode_0;\t// @[FIFOFixer.scala:50:9]\n wire [2:0] anonIn_1_a_bits_param = auto_anon_in_1_a_bits_param_0;\t// @[FIFOFixer.scala:50:9]\n wire [3:0] anonIn_1_a_bits_size = auto_anon_in_1_a_bits_size_0;\t// @[FIFOFixer.scala:50:9]\n wire anonIn_1_a_bits_source = auto_anon_in_1_a_bits_source_0;\t// @[FIFOFixer.scala:50:9]\n wire [31:0] anonIn_1_a_bits_address = auto_anon_in_1_a_bits_address_0;\t// @[FIFOFixer.scala:50:9]\n wire anonIn_1_a_bits_user_amba_prot_bufferable = auto_anon_in_1_a_bits_user_amba_prot_bufferable_0;\t// @[FIFOFixer.scala:50:9]\n wire anonIn_1_a_bits_user_amba_prot_modifiable = auto_anon_in_1_a_bits_user_amba_prot_modifiable_0;\t// @[FIFOFixer.scala:50:9]\n wire anonIn_1_a_bits_user_amba_prot_readalloc = auto_anon_in_1_a_bits_user_amba_prot_readalloc_0;\t// @[FIFOFixer.scala:50:9]\n wire anonIn_1_a_bits_user_amba_prot_writealloc = auto_anon_in_1_a_bits_user_amba_prot_writealloc_0;\t// @[FIFOFixer.scala:50:9]\n wire anonIn_1_a_bits_user_amba_prot_privileged = auto_anon_in_1_a_bits_user_amba_prot_privileged_0;\t// @[FIFOFixer.scala:50:9]\n wire anonIn_1_a_bits_user_amba_prot_secure = auto_anon_in_1_a_bits_user_amba_prot_secure_0;\t// @[FIFOFixer.scala:50:9]\n wire anonIn_1_a_bits_user_amba_prot_fetch = auto_anon_in_1_a_bits_user_amba_prot_fetch_0;\t// @[FIFOFixer.scala:50:9]\n wire [7:0] anonIn_1_a_bits_mask = auto_anon_in_1_a_bits_mask_0;\t// @[FIFOFixer.scala:50:9]\n wire [63:0] anonIn_1_a_bits_data = auto_anon_in_1_a_bits_data_0;\t// @[FIFOFixer.scala:50:9]\n wire anonIn_1_a_bits_corrupt = auto_anon_in_1_a_bits_corrupt_0;\t// @[FIFOFixer.scala:50:9]\n wire anonIn_1_d_ready = auto_anon_in_1_d_ready_0;\t// @[FIFOFixer.scala:50:9]\n wire anonIn_1_d_valid;\t// @[MixedNode.scala:551:17]\n wire [2:0] anonIn_1_d_bits_opcode;\t// @[MixedNode.scala:551:17]\n wire [1:0] anonIn_1_d_bits_param;\t// @[MixedNode.scala:551:17]\n wire [3:0] anonIn_1_d_bits_size;\t// @[MixedNode.scala:551:17]\n wire anonIn_1_d_bits_source;\t// @[MixedNode.scala:551:17]\n wire anonIn_1_d_bits_sink;\t// @[MixedNode.scala:551:17]\n wire anonIn_1_d_bits_denied;\t// @[MixedNode.scala:551:17]\n wire [63:0] anonIn_1_d_bits_data;\t// @[MixedNode.scala:551:17]\n wire anonIn_1_d_bits_corrupt;\t// @[MixedNode.scala:551:17]\n wire anonIn_a_ready;\t// @[MixedNode.scala:551:17]\n wire anonIn_a_valid = auto_anon_in_0_a_valid_0;\t// @[FIFOFixer.scala:50:9]\n wire [2:0] anonIn_a_bits_opcode = auto_anon_in_0_a_bits_opcode_0;\t// @[FIFOFixer.scala:50:9]\n wire [2:0] anonIn_a_bits_param = auto_anon_in_0_a_bits_param_0;\t// @[FIFOFixer.scala:50:9]\n wire [3:0] anonIn_a_bits_size = auto_anon_in_0_a_bits_size_0;\t// @[FIFOFixer.scala:50:9]\n wire [5:0] anonIn_a_bits_source = auto_anon_in_0_a_bits_source_0;\t// @[FIFOFixer.scala:50:9]\n wire [31:0] anonIn_a_bits_address = auto_anon_in_0_a_bits_address_0;\t// @[FIFOFixer.scala:50:9]\n wire anonIn_a_bits_user_amba_prot_bufferable = auto_anon_in_0_a_bits_user_amba_prot_bufferable_0;\t// @[FIFOFixer.scala:50:9]\n wire anonIn_a_bits_user_amba_prot_modifiable = auto_anon_in_0_a_bits_user_amba_prot_modifiable_0;\t// @[FIFOFixer.scala:50:9]\n wire anonIn_a_bits_user_amba_prot_readalloc = auto_anon_in_0_a_bits_user_amba_prot_readalloc_0;\t// @[FIFOFixer.scala:50:9]\n wire anonIn_a_bits_user_amba_prot_writealloc = auto_anon_in_0_a_bits_user_amba_prot_writealloc_0;\t// @[FIFOFixer.scala:50:9]\n wire anonIn_a_bits_user_amba_prot_privileged = auto_anon_in_0_a_bits_user_amba_prot_privileged_0;\t// @[FIFOFixer.scala:50:9]\n wire anonIn_a_bits_user_amba_prot_secure = auto_anon_in_0_a_bits_user_amba_prot_secure_0;\t// @[FIFOFixer.scala:50:9]\n wire anonIn_a_bits_user_amba_prot_fetch = auto_anon_in_0_a_bits_user_amba_prot_fetch_0;\t// @[FIFOFixer.scala:50:9]\n wire [7:0] anonIn_a_bits_mask = auto_anon_in_0_a_bits_mask_0;\t// @[FIFOFixer.scala:50:9]\n wire [63:0] anonIn_a_bits_data = auto_anon_in_0_a_bits_data_0;\t// @[FIFOFixer.scala:50:9]\n wire anonIn_a_bits_corrupt = auto_anon_in_0_a_bits_corrupt_0;\t// @[FIFOFixer.scala:50:9]\n wire anonIn_d_ready = auto_anon_in_0_d_ready_0;\t// @[FIFOFixer.scala:50:9]\n wire anonIn_d_valid;\t// @[MixedNode.scala:551:17]\n wire [2:0] anonIn_d_bits_opcode;\t// @[MixedNode.scala:551:17]\n wire [1:0] anonIn_d_bits_param;\t// @[MixedNode.scala:551:17]\n wire [3:0] anonIn_d_bits_size;\t// @[MixedNode.scala:551:17]\n wire [5:0] anonIn_d_bits_source;\t// @[MixedNode.scala:551:17]\n wire anonIn_d_bits_sink;\t// @[MixedNode.scala:551:17]\n wire anonIn_d_bits_denied;\t// @[MixedNode.scala:551:17]\n wire [63:0] anonIn_d_bits_data;\t// @[MixedNode.scala:551:17]\n wire anonIn_d_bits_corrupt;\t// @[MixedNode.scala:551:17]\n wire x1_anonOut_a_ready = auto_anon_out_1_a_ready_0;\t// @[FIFOFixer.scala:50:9]\n wire x1_anonOut_a_valid;\t// @[MixedNode.scala:542:17]\n wire [2:0] x1_anonOut_a_bits_opcode;\t// @[MixedNode.scala:542:17]\n wire [2:0] x1_anonOut_a_bits_param;\t// @[MixedNode.scala:542:17]\n wire [3:0] x1_anonOut_a_bits_size;\t// @[MixedNode.scala:542:17]\n wire x1_anonOut_a_bits_source;\t// @[MixedNode.scala:542:17]\n wire [31:0] x1_anonOut_a_bits_address;\t// @[MixedNode.scala:542:17]\n wire x1_anonOut_a_bits_user_amba_prot_bufferable;\t// @[MixedNode.scala:542:17]\n wire x1_anonOut_a_bits_user_amba_prot_modifiable;\t// @[MixedNode.scala:542:17]\n wire x1_anonOut_a_bits_user_amba_prot_readalloc;\t// @[MixedNode.scala:542:17]\n wire x1_anonOut_a_bits_user_amba_prot_writealloc;\t// @[MixedNode.scala:542:17]\n wire x1_anonOut_a_bits_user_amba_prot_privileged;\t// @[MixedNode.scala:542:17]\n wire x1_anonOut_a_bits_user_amba_prot_secure;\t// @[MixedNode.scala:542:17]\n wire x1_anonOut_a_bits_user_amba_prot_fetch;\t// @[MixedNode.scala:542:17]\n wire [7:0] x1_anonOut_a_bits_mask;\t// @[MixedNode.scala:542:17]\n wire [63:0] x1_anonOut_a_bits_data;\t// @[MixedNode.scala:542:17]\n wire x1_anonOut_a_bits_corrupt;\t// @[MixedNode.scala:542:17]\n wire x1_anonOut_d_ready;\t// @[MixedNode.scala:542:17]\n wire x1_anonOut_d_valid = auto_anon_out_1_d_valid_0;\t// @[FIFOFixer.scala:50:9]\n wire [2:0] x1_anonOut_d_bits_opcode = auto_anon_out_1_d_bits_opcode_0;\t// @[FIFOFixer.scala:50:9]\n wire [1:0] x1_anonOut_d_bits_param = auto_anon_out_1_d_bits_param_0;\t// @[FIFOFixer.scala:50:9]\n wire [3:0] x1_anonOut_d_bits_size = auto_anon_out_1_d_bits_size_0;\t// @[FIFOFixer.scala:50:9]\n wire x1_anonOut_d_bits_source = auto_anon_out_1_d_bits_source_0;\t// @[FIFOFixer.scala:50:9]\n wire x1_anonOut_d_bits_sink = auto_anon_out_1_d_bits_sink_0;\t// @[FIFOFixer.scala:50:9]\n wire x1_anonOut_d_bits_denied = auto_anon_out_1_d_bits_denied_0;\t// @[FIFOFixer.scala:50:9]\n wire [63:0] x1_anonOut_d_bits_data = auto_anon_out_1_d_bits_data_0;\t// @[FIFOFixer.scala:50:9]\n wire x1_anonOut_d_bits_corrupt = auto_anon_out_1_d_bits_corrupt_0;\t// @[FIFOFixer.scala:50:9]\n wire anonOut_a_ready = auto_anon_out_0_a_ready_0;\t// @[FIFOFixer.scala:50:9]\n wire anonOut_a_valid;\t// @[MixedNode.scala:542:17]\n wire [2:0] anonOut_a_bits_opcode;\t// @[MixedNode.scala:542:17]\n wire [2:0] anonOut_a_bits_param;\t// @[MixedNode.scala:542:17]\n wire [3:0] anonOut_a_bits_size;\t// @[MixedNode.scala:542:17]\n wire [5:0] anonOut_a_bits_source;\t// @[MixedNode.scala:542:17]\n wire [31:0] anonOut_a_bits_address;\t// @[MixedNode.scala:542:17]\n wire anonOut_a_bits_user_amba_prot_bufferable;\t// @[MixedNode.scala:542:17]\n wire anonOut_a_bits_user_amba_prot_modifiable;\t// @[MixedNode.scala:542:17]\n wire anonOut_a_bits_user_amba_prot_readalloc;\t// @[MixedNode.scala:542:17]\n wire anonOut_a_bits_user_amba_prot_writealloc;\t// @[MixedNode.scala:542:17]\n wire anonOut_a_bits_user_amba_prot_privileged;\t// @[MixedNode.scala:542:17]\n wire anonOut_a_bits_user_amba_prot_secure;\t// @[MixedNode.scala:542:17]\n wire anonOut_a_bits_user_amba_prot_fetch;\t// @[MixedNode.scala:542:17]\n wire [7:0] anonOut_a_bits_mask;\t// @[MixedNode.scala:542:17]\n wire [63:0] anonOut_a_bits_data;\t// @[MixedNode.scala:542:17]\n wire anonOut_a_bits_corrupt;\t// @[MixedNode.scala:542:17]\n wire anonOut_d_ready;\t// @[MixedNode.scala:542:17]\n wire anonOut_d_valid = auto_anon_out_0_d_valid_0;\t// @[FIFOFixer.scala:50:9]\n wire [2:0] anonOut_d_bits_opcode = auto_anon_out_0_d_bits_opcode_0;\t// @[FIFOFixer.scala:50:9]\n wire [1:0] anonOut_d_bits_param = auto_anon_out_0_d_bits_param_0;\t// @[FIFOFixer.scala:50:9]\n wire [3:0] anonOut_d_bits_size = auto_anon_out_0_d_bits_size_0;\t// @[FIFOFixer.scala:50:9]\n wire [5:0] anonOut_d_bits_source = auto_anon_out_0_d_bits_source_0;\t// @[FIFOFixer.scala:50:9]\n wire anonOut_d_bits_sink = auto_anon_out_0_d_bits_sink_0;\t// @[FIFOFixer.scala:50:9]\n wire anonOut_d_bits_denied = auto_anon_out_0_d_bits_denied_0;\t// @[FIFOFixer.scala:50:9]\n wire [63:0] anonOut_d_bits_data = auto_anon_out_0_d_bits_data_0;\t// @[FIFOFixer.scala:50:9]\n wire anonOut_d_bits_corrupt = auto_anon_out_0_d_bits_corrupt_0;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_in_1_a_ready_0;\t// @[FIFOFixer.scala:50:9]\n wire [2:0] auto_anon_in_1_d_bits_opcode_0;\t// @[FIFOFixer.scala:50:9]\n wire [1:0] auto_anon_in_1_d_bits_param_0;\t// @[FIFOFixer.scala:50:9]\n wire [3:0] auto_anon_in_1_d_bits_size_0;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_in_1_d_bits_source_0;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_in_1_d_bits_sink_0;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_in_1_d_bits_denied_0;\t// @[FIFOFixer.scala:50:9]\n wire [63:0] auto_anon_in_1_d_bits_data_0;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_in_1_d_bits_corrupt_0;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_in_1_d_valid_0;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_in_0_a_ready_0;\t// @[FIFOFixer.scala:50:9]\n wire [2:0] auto_anon_in_0_d_bits_opcode_0;\t// @[FIFOFixer.scala:50:9]\n wire [1:0] auto_anon_in_0_d_bits_param_0;\t// @[FIFOFixer.scala:50:9]\n wire [3:0] auto_anon_in_0_d_bits_size_0;\t// @[FIFOFixer.scala:50:9]\n wire [5:0] auto_anon_in_0_d_bits_source_0;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_in_0_d_bits_sink_0;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_in_0_d_bits_denied_0;\t// @[FIFOFixer.scala:50:9]\n wire [63:0] auto_anon_in_0_d_bits_data_0;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_in_0_d_bits_corrupt_0;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_in_0_d_valid_0;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_out_1_a_bits_user_amba_prot_bufferable_0;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_out_1_a_bits_user_amba_prot_modifiable_0;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_out_1_a_bits_user_amba_prot_readalloc_0;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_out_1_a_bits_user_amba_prot_writealloc_0;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_out_1_a_bits_user_amba_prot_privileged_0;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_out_1_a_bits_user_amba_prot_secure_0;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_out_1_a_bits_user_amba_prot_fetch_0;\t// @[FIFOFixer.scala:50:9]\n wire [2:0] auto_anon_out_1_a_bits_opcode_0;\t// @[FIFOFixer.scala:50:9]\n wire [2:0] auto_anon_out_1_a_bits_param_0;\t// @[FIFOFixer.scala:50:9]\n wire [3:0] auto_anon_out_1_a_bits_size_0;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_out_1_a_bits_source_0;\t// @[FIFOFixer.scala:50:9]\n wire [31:0] auto_anon_out_1_a_bits_address_0;\t// @[FIFOFixer.scala:50:9]\n wire [7:0] auto_anon_out_1_a_bits_mask_0;\t// @[FIFOFixer.scala:50:9]\n wire [63:0] auto_anon_out_1_a_bits_data_0;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_out_1_a_bits_corrupt_0;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_out_1_a_valid_0;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_out_1_d_ready_0;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_out_0_a_bits_user_amba_prot_bufferable_0;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_out_0_a_bits_user_amba_prot_modifiable_0;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_out_0_a_bits_user_amba_prot_readalloc_0;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_out_0_a_bits_user_amba_prot_writealloc_0;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_out_0_a_bits_user_amba_prot_privileged_0;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_out_0_a_bits_user_amba_prot_secure_0;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_out_0_a_bits_user_amba_prot_fetch_0;\t// @[FIFOFixer.scala:50:9]\n wire [2:0] auto_anon_out_0_a_bits_opcode_0;\t// @[FIFOFixer.scala:50:9]\n wire [2:0] auto_anon_out_0_a_bits_param_0;\t// @[FIFOFixer.scala:50:9]\n wire [3:0] auto_anon_out_0_a_bits_size_0;\t// @[FIFOFixer.scala:50:9]\n wire [5:0] auto_anon_out_0_a_bits_source_0;\t// @[FIFOFixer.scala:50:9]\n wire [31:0] auto_anon_out_0_a_bits_address_0;\t// @[FIFOFixer.scala:50:9]\n wire [7:0] auto_anon_out_0_a_bits_mask_0;\t// @[FIFOFixer.scala:50:9]\n wire [63:0] auto_anon_out_0_a_bits_data_0;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_out_0_a_bits_corrupt_0;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_out_0_a_valid_0;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_out_0_d_ready_0;\t// @[FIFOFixer.scala:50:9]\n wire _anonIn_a_ready_T_2;\t// @[FIFOFixer.scala:96:33]\n assign auto_anon_in_0_a_ready_0 = anonIn_a_ready;\t// @[FIFOFixer.scala:50:9]\n assign anonOut_a_bits_opcode = anonIn_a_bits_opcode;\t// @[MixedNode.scala:542:17, :551:17]\n assign anonOut_a_bits_param = anonIn_a_bits_param;\t// @[MixedNode.scala:542:17, :551:17]\n assign anonOut_a_bits_size = anonIn_a_bits_size;\t// @[MixedNode.scala:542:17, :551:17]\n assign anonOut_a_bits_source = anonIn_a_bits_source;\t// @[MixedNode.scala:542:17, :551:17]\n wire [5:0] _stalls_a_sel_uncommonBits_T = anonIn_a_bits_source;\t// @[Parameters.scala:52:29]\n wire [5:0] _stalls_a_sel_uncommonBits_T_1 = anonIn_a_bits_source;\t// @[Parameters.scala:52:29]\n assign anonOut_a_bits_address = anonIn_a_bits_address;\t// @[MixedNode.scala:542:17, :551:17]\n wire [31:0] _a_notFIFO_T = anonIn_a_bits_address;\t// @[Parameters.scala:137:31]\n wire [31:0] _a_id_T = anonIn_a_bits_address;\t// @[Parameters.scala:137:31]\n assign anonOut_a_bits_user_amba_prot_bufferable = anonIn_a_bits_user_amba_prot_bufferable;\t// @[MixedNode.scala:542:17, :551:17]\n assign anonOut_a_bits_user_amba_prot_modifiable = anonIn_a_bits_user_amba_prot_modifiable;\t// @[MixedNode.scala:542:17, :551:17]\n assign anonOut_a_bits_user_amba_prot_readalloc = anonIn_a_bits_user_amba_prot_readalloc;\t// @[MixedNode.scala:542:17, :551:17]\n assign anonOut_a_bits_user_amba_prot_writealloc = anonIn_a_bits_user_amba_prot_writealloc;\t// @[MixedNode.scala:542:17, :551:17]\n assign anonOut_a_bits_user_amba_prot_privileged = anonIn_a_bits_user_amba_prot_privileged;\t// @[MixedNode.scala:542:17, :551:17]\n assign anonOut_a_bits_user_amba_prot_secure = anonIn_a_bits_user_amba_prot_secure;\t// @[MixedNode.scala:542:17, :551:17]\n assign anonOut_a_bits_user_amba_prot_fetch = anonIn_a_bits_user_amba_prot_fetch;\t// @[MixedNode.scala:542:17, :551:17]\n assign anonOut_a_bits_mask = anonIn_a_bits_mask;\t// @[MixedNode.scala:542:17, :551:17]\n assign anonOut_a_bits_data = anonIn_a_bits_data;\t// @[MixedNode.scala:542:17, :551:17]\n assign anonOut_a_bits_corrupt = anonIn_a_bits_corrupt;\t// @[MixedNode.scala:542:17, :551:17]\n assign anonOut_d_ready = anonIn_d_ready;\t// @[MixedNode.scala:542:17, :551:17]\n assign auto_anon_in_0_d_valid_0 = anonIn_d_valid;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_in_0_d_bits_opcode_0 = anonIn_d_bits_opcode;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_in_0_d_bits_param_0 = anonIn_d_bits_param;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_in_0_d_bits_size_0 = anonIn_d_bits_size;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_in_0_d_bits_source_0 = anonIn_d_bits_source;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_in_0_d_bits_sink_0 = anonIn_d_bits_sink;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_in_0_d_bits_denied_0 = anonIn_d_bits_denied;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_in_0_d_bits_data_0 = anonIn_d_bits_data;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_in_0_d_bits_corrupt_0 = anonIn_d_bits_corrupt;\t// @[FIFOFixer.scala:50:9]\n wire _anonIn_a_ready_T_5;\t// @[FIFOFixer.scala:96:33]\n assign auto_anon_in_1_a_ready_0 = anonIn_1_a_ready;\t// @[FIFOFixer.scala:50:9]\n wire _anonOut_a_valid_T_5 = anonIn_1_a_valid;\t// @[FIFOFixer.scala:95:33]\n assign x1_anonOut_a_bits_opcode = anonIn_1_a_bits_opcode;\t// @[MixedNode.scala:542:17, :551:17]\n assign x1_anonOut_a_bits_param = anonIn_1_a_bits_param;\t// @[MixedNode.scala:542:17, :551:17]\n assign x1_anonOut_a_bits_size = anonIn_1_a_bits_size;\t// @[MixedNode.scala:542:17, :551:17]\n assign x1_anonOut_a_bits_source = anonIn_1_a_bits_source;\t// @[MixedNode.scala:542:17, :551:17]\n assign x1_anonOut_a_bits_address = anonIn_1_a_bits_address;\t// @[MixedNode.scala:542:17, :551:17]\n wire [31:0] _a_notFIFO_T_5 = anonIn_1_a_bits_address;\t// @[Parameters.scala:137:31]\n wire [31:0] _a_id_T_13 = anonIn_1_a_bits_address;\t// @[Parameters.scala:137:31]\n assign x1_anonOut_a_bits_user_amba_prot_bufferable = anonIn_1_a_bits_user_amba_prot_bufferable;\t// @[MixedNode.scala:542:17, :551:17]\n assign x1_anonOut_a_bits_user_amba_prot_modifiable = anonIn_1_a_bits_user_amba_prot_modifiable;\t// @[MixedNode.scala:542:17, :551:17]\n assign x1_anonOut_a_bits_user_amba_prot_readalloc = anonIn_1_a_bits_user_amba_prot_readalloc;\t// @[MixedNode.scala:542:17, :551:17]\n assign x1_anonOut_a_bits_user_amba_prot_writealloc = anonIn_1_a_bits_user_amba_prot_writealloc;\t// @[MixedNode.scala:542:17, :551:17]\n assign x1_anonOut_a_bits_user_amba_prot_privileged = anonIn_1_a_bits_user_amba_prot_privileged;\t// @[MixedNode.scala:542:17, :551:17]\n assign x1_anonOut_a_bits_user_amba_prot_secure = anonIn_1_a_bits_user_amba_prot_secure;\t// @[MixedNode.scala:542:17, :551:17]\n assign x1_anonOut_a_bits_user_amba_prot_fetch = anonIn_1_a_bits_user_amba_prot_fetch;\t// @[MixedNode.scala:542:17, :551:17]\n assign x1_anonOut_a_bits_mask = anonIn_1_a_bits_mask;\t// @[MixedNode.scala:542:17, :551:17]\n assign x1_anonOut_a_bits_data = anonIn_1_a_bits_data;\t// @[MixedNode.scala:542:17, :551:17]\n assign x1_anonOut_a_bits_corrupt = anonIn_1_a_bits_corrupt;\t// @[MixedNode.scala:542:17, :551:17]\n assign x1_anonOut_d_ready = anonIn_1_d_ready;\t// @[MixedNode.scala:542:17, :551:17]\n assign auto_anon_in_1_d_valid_0 = anonIn_1_d_valid;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_in_1_d_bits_opcode_0 = anonIn_1_d_bits_opcode;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_in_1_d_bits_param_0 = anonIn_1_d_bits_param;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_in_1_d_bits_size_0 = anonIn_1_d_bits_size;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_in_1_d_bits_source_0 = anonIn_1_d_bits_source;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_in_1_d_bits_sink_0 = anonIn_1_d_bits_sink;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_in_1_d_bits_denied_0 = anonIn_1_d_bits_denied;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_in_1_d_bits_data_0 = anonIn_1_d_bits_data;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_in_1_d_bits_corrupt_0 = anonIn_1_d_bits_corrupt;\t// @[FIFOFixer.scala:50:9]\n wire _anonOut_a_valid_T_2;\t// @[FIFOFixer.scala:95:33]\n assign auto_anon_out_0_a_valid_0 = anonOut_a_valid;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_0_a_bits_opcode_0 = anonOut_a_bits_opcode;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_0_a_bits_param_0 = anonOut_a_bits_param;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_0_a_bits_size_0 = anonOut_a_bits_size;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_0_a_bits_source_0 = anonOut_a_bits_source;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_0_a_bits_address_0 = anonOut_a_bits_address;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_0_a_bits_user_amba_prot_bufferable_0 = anonOut_a_bits_user_amba_prot_bufferable;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_0_a_bits_user_amba_prot_modifiable_0 = anonOut_a_bits_user_amba_prot_modifiable;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_0_a_bits_user_amba_prot_readalloc_0 = anonOut_a_bits_user_amba_prot_readalloc;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_0_a_bits_user_amba_prot_writealloc_0 = anonOut_a_bits_user_amba_prot_writealloc;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_0_a_bits_user_amba_prot_privileged_0 = anonOut_a_bits_user_amba_prot_privileged;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_0_a_bits_user_amba_prot_secure_0 = anonOut_a_bits_user_amba_prot_secure;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_0_a_bits_user_amba_prot_fetch_0 = anonOut_a_bits_user_amba_prot_fetch;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_0_a_bits_mask_0 = anonOut_a_bits_mask;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_0_a_bits_data_0 = anonOut_a_bits_data;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_0_a_bits_corrupt_0 = anonOut_a_bits_corrupt;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_0_d_ready_0 = anonOut_d_ready;\t// @[FIFOFixer.scala:50:9]\n assign anonIn_d_valid = anonOut_d_valid;\t// @[MixedNode.scala:542:17, :551:17]\n assign anonIn_d_bits_opcode = anonOut_d_bits_opcode;\t// @[MixedNode.scala:542:17, :551:17]\n assign anonIn_d_bits_param = anonOut_d_bits_param;\t// @[MixedNode.scala:542:17, :551:17]\n assign anonIn_d_bits_size = anonOut_d_bits_size;\t// @[MixedNode.scala:542:17, :551:17]\n assign anonIn_d_bits_source = anonOut_d_bits_source;\t// @[MixedNode.scala:542:17, :551:17]\n assign anonIn_d_bits_sink = anonOut_d_bits_sink;\t// @[MixedNode.scala:542:17, :551:17]\n assign anonIn_d_bits_denied = anonOut_d_bits_denied;\t// @[MixedNode.scala:542:17, :551:17]\n assign anonIn_d_bits_data = anonOut_d_bits_data;\t// @[MixedNode.scala:542:17, :551:17]\n assign anonIn_d_bits_corrupt = anonOut_d_bits_corrupt;\t// @[MixedNode.scala:542:17, :551:17]\n assign _anonIn_a_ready_T_5 = x1_anonOut_a_ready;\t// @[FIFOFixer.scala:96:33]\n assign auto_anon_out_1_a_valid_0 = x1_anonOut_a_valid;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_1_a_bits_opcode_0 = x1_anonOut_a_bits_opcode;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_1_a_bits_param_0 = x1_anonOut_a_bits_param;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_1_a_bits_size_0 = x1_anonOut_a_bits_size;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_1_a_bits_source_0 = x1_anonOut_a_bits_source;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_1_a_bits_address_0 = x1_anonOut_a_bits_address;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_1_a_bits_user_amba_prot_bufferable_0 = x1_anonOut_a_bits_user_amba_prot_bufferable;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_1_a_bits_user_amba_prot_modifiable_0 = x1_anonOut_a_bits_user_amba_prot_modifiable;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_1_a_bits_user_amba_prot_readalloc_0 = x1_anonOut_a_bits_user_amba_prot_readalloc;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_1_a_bits_user_amba_prot_writealloc_0 = x1_anonOut_a_bits_user_amba_prot_writealloc;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_1_a_bits_user_amba_prot_privileged_0 = x1_anonOut_a_bits_user_amba_prot_privileged;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_1_a_bits_user_amba_prot_secure_0 = x1_anonOut_a_bits_user_amba_prot_secure;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_1_a_bits_user_amba_prot_fetch_0 = x1_anonOut_a_bits_user_amba_prot_fetch;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_1_a_bits_mask_0 = x1_anonOut_a_bits_mask;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_1_a_bits_data_0 = x1_anonOut_a_bits_data;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_1_a_bits_corrupt_0 = x1_anonOut_a_bits_corrupt;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_1_d_ready_0 = x1_anonOut_d_ready;\t// @[FIFOFixer.scala:50:9]\n assign anonIn_1_d_valid = x1_anonOut_d_valid;\t// @[MixedNode.scala:542:17, :551:17]\n assign anonIn_1_d_bits_opcode = x1_anonOut_d_bits_opcode;\t// @[MixedNode.scala:542:17, :551:17]\n assign anonIn_1_d_bits_param = x1_anonOut_d_bits_param;\t// @[MixedNode.scala:542:17, :551:17]\n assign anonIn_1_d_bits_size = x1_anonOut_d_bits_size;\t// @[MixedNode.scala:542:17, :551:17]\n assign anonIn_1_d_bits_source = x1_anonOut_d_bits_source;\t// @[MixedNode.scala:542:17, :551:17]\n assign anonIn_1_d_bits_sink = x1_anonOut_d_bits_sink;\t// @[MixedNode.scala:542:17, :551:17]\n assign anonIn_1_d_bits_denied = x1_anonOut_d_bits_denied;\t// @[MixedNode.scala:542:17, :551:17]\n assign anonIn_1_d_bits_data = x1_anonOut_d_bits_data;\t// @[MixedNode.scala:542:17, :551:17]\n assign anonIn_1_d_bits_corrupt = x1_anonOut_d_bits_corrupt;\t// @[MixedNode.scala:542:17, :551:17]\n wire [32:0] _a_notFIFO_T_1 = {1'h0, _a_notFIFO_T};\t// @[Parameters.scala:137:{31,41}]\n wire [32:0] _a_id_T_1 = {1'h0, _a_id_T};\t// @[Parameters.scala:137:{31,41}]\n wire [32:0] _a_id_T_2 = _a_id_T_1 & 33'h40000000;\t// @[Parameters.scala:137:{41,46}]\n wire [32:0] _a_id_T_3 = _a_id_T_2;\t// @[Parameters.scala:137:46]\n wire _a_id_T_4 = _a_id_T_3 == 33'h0;\t// @[Parameters.scala:137:{46,59}]\n wire _a_id_T_10 = _a_id_T_4;\t// @[Mux.scala:30:73]\n wire [31:0] _a_id_T_5 = {anonIn_a_bits_address[31], anonIn_a_bits_address[30:0] ^ 31'h40000000};\t// @[Parameters.scala:137:31]\n wire [32:0] _a_id_T_6 = {1'h0, _a_id_T_5};\t// @[Parameters.scala:137:{31,41}]\n wire [32:0] _a_id_T_7 = _a_id_T_6 & 33'h40000000;\t// @[Parameters.scala:137:{41,46}]\n wire [32:0] _a_id_T_8 = _a_id_T_7;\t// @[Parameters.scala:137:46]\n wire _a_id_T_9 = _a_id_T_8 == 33'h0;\t// @[Parameters.scala:137:{46,59}]\n wire [1:0] _a_id_T_11 = {_a_id_T_9, 1'h0};\t// @[Mux.scala:30:73]\n wire [1:0] _a_id_T_12 = {1'h0, _a_id_T_10} | _a_id_T_11;\t// @[Mux.scala:30:73]\n wire [1:0] a_id = _a_id_T_12;\t// @[Mux.scala:30:73]\n wire a_noDomain = a_id == 2'h0;\t// @[Mux.scala:30:73]\n wire _T_5 = anonIn_a_ready & anonIn_a_valid;\t// @[Decoupled.scala:51:35]\n wire _a_first_T;\t// @[Decoupled.scala:51:35]\n assign _a_first_T = _T_5;\t// @[Decoupled.scala:51:35]\n wire _stalls_id_T;\t// @[Decoupled.scala:51:35]\n assign _stalls_id_T = _T_5;\t// @[Decoupled.scala:51:35]\n wire _stalls_id_T_4;\t// @[Decoupled.scala:51:35]\n assign _stalls_id_T_4 = _T_5;\t// @[Decoupled.scala:51:35]\n wire [26:0] _a_first_beats1_decode_T = 27'hFFF << anonIn_a_bits_size;\t// @[package.scala:243:71]\n wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0];\t// @[package.scala:243:{71,76}]\n wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1;\t// @[package.scala:243:{46,76}]\n wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3];\t// @[package.scala:243:46]\n wire _a_first_beats1_opdata_T = anonIn_a_bits_opcode[2];\t// @[Edges.scala:92:37]\n wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T;\t// @[Edges.scala:92:{28,37}]\n wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0;\t// @[Edges.scala:92:28, :220:59, :221:14]\n reg [8:0] a_first_counter;\t// @[Edges.scala:229:27]\n wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1;\t// @[Edges.scala:229:27, :230:28]\n wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0];\t// @[Edges.scala:230:28]\n wire a_first = a_first_counter == 9'h0;\t// @[Edges.scala:229:27, :231:25]\n wire _a_first_last_T = a_first_counter == 9'h1;\t// @[Edges.scala:229:27, :232:25]\n wire _a_first_last_T_1 = a_first_beats1 == 9'h0;\t// @[Edges.scala:221:14, :232:43]\n wire a_first_last = _a_first_last_T | _a_first_last_T_1;\t// @[Edges.scala:232:{25,33,43}]\n wire a_first_done = a_first_last & _a_first_T;\t// @[Decoupled.scala:51:35]\n wire [8:0] _a_first_count_T = ~a_first_counter1;\t// @[Edges.scala:230:28, :234:27]\n wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T;\t// @[Edges.scala:221:14, :234:{25,27}]\n wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1;\t// @[Edges.scala:221:14, :230:28, :231:25, :236:21]\n wire _d_first_T = anonOut_d_ready & anonOut_d_valid;\t// @[Decoupled.scala:51:35]\n wire [26:0] _d_first_beats1_decode_T = 27'hFFF << anonOut_d_bits_size;\t// @[package.scala:243:71]\n wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0];\t// @[package.scala:243:{71,76}]\n wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1;\t// @[package.scala:243:{46,76}]\n wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3];\t// @[package.scala:243:46]\n wire d_first_beats1_opdata = anonOut_d_bits_opcode[0];\t// @[Edges.scala:106:36]\n wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0;\t// @[Edges.scala:106:36, :220:59, :221:14]\n reg [8:0] d_first_counter;\t// @[Edges.scala:229:27]\n wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1;\t// @[Edges.scala:229:27, :230:28]\n wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0];\t// @[Edges.scala:230:28]\n wire d_first_first = d_first_counter == 9'h0;\t// @[Edges.scala:229:27, :231:25]\n wire _d_first_last_T = d_first_counter == 9'h1;\t// @[Edges.scala:229:27, :232:25]\n wire _d_first_last_T_1 = d_first_beats1 == 9'h0;\t// @[Edges.scala:221:14, :232:43]\n wire d_first_last = _d_first_last_T | _d_first_last_T_1;\t// @[Edges.scala:232:{25,33,43}]\n wire d_first_done = d_first_last & _d_first_T;\t// @[Decoupled.scala:51:35]\n wire [8:0] _d_first_count_T = ~d_first_counter1;\t// @[Edges.scala:230:28, :234:27]\n wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T;\t// @[Edges.scala:221:14, :234:{25,27}]\n wire [8:0] _d_first_counter_T = d_first_first ? d_first_beats1 : d_first_counter1;\t// @[Edges.scala:221:14, :230:28, :231:25, :236:21]\n wire _d_first_T_1 = anonOut_d_bits_opcode != 3'h6;\t// @[FIFOFixer.scala:75:63]\n wire d_first = d_first_first & _d_first_T_1;\t// @[FIFOFixer.scala:75:{42,63}]\n reg flight_0;\t// @[FIFOFixer.scala:79:27]\n reg flight_1;\t// @[FIFOFixer.scala:79:27]\n reg flight_2;\t// @[FIFOFixer.scala:79:27]\n reg flight_3;\t// @[FIFOFixer.scala:79:27]\n reg flight_4;\t// @[FIFOFixer.scala:79:27]\n reg flight_5;\t// @[FIFOFixer.scala:79:27]\n reg flight_6;\t// @[FIFOFixer.scala:79:27]\n reg flight_7;\t// @[FIFOFixer.scala:79:27]\n reg flight_8;\t// @[FIFOFixer.scala:79:27]\n reg flight_9;\t// @[FIFOFixer.scala:79:27]\n reg flight_10;\t// @[FIFOFixer.scala:79:27]\n reg flight_11;\t// @[FIFOFixer.scala:79:27]\n reg flight_12;\t// @[FIFOFixer.scala:79:27]\n reg flight_13;\t// @[FIFOFixer.scala:79:27]\n reg flight_14;\t// @[FIFOFixer.scala:79:27]\n reg flight_15;\t// @[FIFOFixer.scala:79:27]\n reg flight_16;\t// @[FIFOFixer.scala:79:27]\n reg flight_17;\t// @[FIFOFixer.scala:79:27]\n reg flight_18;\t// @[FIFOFixer.scala:79:27]\n reg flight_19;\t// @[FIFOFixer.scala:79:27]\n reg flight_20;\t// @[FIFOFixer.scala:79:27]\n reg flight_21;\t// @[FIFOFixer.scala:79:27]\n reg flight_22;\t// @[FIFOFixer.scala:79:27]\n reg flight_23;\t// @[FIFOFixer.scala:79:27]\n reg flight_24;\t// @[FIFOFixer.scala:79:27]\n reg flight_25;\t// @[FIFOFixer.scala:79:27]\n reg flight_26;\t// @[FIFOFixer.scala:79:27]\n reg flight_27;\t// @[FIFOFixer.scala:79:27]\n reg flight_28;\t// @[FIFOFixer.scala:79:27]\n reg flight_29;\t// @[FIFOFixer.scala:79:27]\n reg flight_30;\t// @[FIFOFixer.scala:79:27]\n reg flight_31;\t// @[FIFOFixer.scala:79:27]\n reg flight_32;\t// @[FIFOFixer.scala:79:27]\n wire _T_9 = anonIn_d_ready & anonIn_d_valid;\t// @[Decoupled.scala:51:35]\n wire [2:0] stalls_a_sel_uncommonBits = _stalls_a_sel_uncommonBits_T[2:0];\t// @[Parameters.scala:52:{29,56}]\n wire [2:0] _stalls_a_sel_T = anonIn_a_bits_source[5:3];\t// @[Parameters.scala:54:10]\n wire [2:0] _stalls_a_sel_T_5 = anonIn_a_bits_source[5:3];\t// @[Parameters.scala:54:10]\n wire _stalls_a_sel_T_1 = _stalls_a_sel_T == 3'h2;\t// @[Parameters.scala:54:{10,32}]\n wire _stalls_a_sel_T_3 = _stalls_a_sel_T_1;\t// @[Parameters.scala:54:{32,67}]\n wire stalls_a_sel = _stalls_a_sel_T_3;\t// @[Parameters.scala:54:67, :56:48]\n wire _stalls_id_T_1 = _stalls_id_T & stalls_a_sel;\t// @[Decoupled.scala:51:35]\n wire _stalls_id_T_3 = _stalls_id_T_1;\t// @[FIFOFixer.scala:85:{47,56}]\n reg [1:0] stalls_id;\t// @[FIFOFixer.scala:85:30]\n wire _stalls_T = stalls_a_sel & a_first;\t// @[FIFOFixer.scala:88:15]\n wire _stalls_T_1 = flight_16 | flight_17;\t// @[FIFOFixer.scala:79:27, :88:44]\n wire _stalls_T_2 = _stalls_T_1 | flight_18;\t// @[FIFOFixer.scala:79:27, :88:44]\n wire _stalls_T_3 = _stalls_T_2 | flight_19;\t// @[FIFOFixer.scala:79:27, :88:44]\n wire _stalls_T_4 = _stalls_T_3 | flight_20;\t// @[FIFOFixer.scala:79:27, :88:44]\n wire _stalls_T_5 = _stalls_T_4 | flight_21;\t// @[FIFOFixer.scala:79:27, :88:44]\n wire _stalls_T_6 = _stalls_T_5 | flight_22;\t// @[FIFOFixer.scala:79:27, :88:44]\n wire _stalls_T_7 = _stalls_T_6 | flight_23;\t// @[FIFOFixer.scala:79:27, :88:44]\n wire _stalls_T_8 = _stalls_T & _stalls_T_7;\t// @[FIFOFixer.scala:88:{15,26,44}]\n wire _stalls_T_9 = stalls_id != a_id;\t// @[Mux.scala:30:73]\n wire _stalls_T_10 = a_noDomain | _stalls_T_9;\t// @[FIFOFixer.scala:63:29, :88:{65,71}]\n wire stalls_0 = _stalls_T_8 & _stalls_T_10;\t// @[FIFOFixer.scala:88:{26,50,65}]\n wire _stall_T = stalls_0;\t// @[FIFOFixer.scala:88:50, :91:45]\n wire [2:0] stalls_a_sel_uncommonBits_1 = _stalls_a_sel_uncommonBits_T_1[2:0];\t// @[Parameters.scala:52:{29,56}]\n wire _stalls_a_sel_T_6 = _stalls_a_sel_T_5 == 3'h3;\t// @[Parameters.scala:54:{10,32}]\n wire _stalls_a_sel_T_8 = _stalls_a_sel_T_6;\t// @[Parameters.scala:54:{32,67}]\n wire stalls_a_sel_1 = _stalls_a_sel_T_8;\t// @[Parameters.scala:54:67, :56:48]\n wire _stalls_id_T_5 = _stalls_id_T_4 & stalls_a_sel_1;\t// @[Decoupled.scala:51:35]\n wire _stalls_id_T_7 = _stalls_id_T_5;\t// @[FIFOFixer.scala:85:{47,56}]\n reg [1:0] stalls_id_1;\t// @[FIFOFixer.scala:85:30]\n wire _stalls_T_11 = stalls_a_sel_1 & a_first;\t// @[FIFOFixer.scala:88:15]\n wire _stalls_T_12 = flight_24 | flight_25;\t// @[FIFOFixer.scala:79:27, :88:44]\n wire _stalls_T_13 = _stalls_T_12 | flight_26;\t// @[FIFOFixer.scala:79:27, :88:44]\n wire _stalls_T_14 = _stalls_T_13 | flight_27;\t// @[FIFOFixer.scala:79:27, :88:44]\n wire _stalls_T_15 = _stalls_T_14 | flight_28;\t// @[FIFOFixer.scala:79:27, :88:44]\n wire _stalls_T_16 = _stalls_T_15 | flight_29;\t// @[FIFOFixer.scala:79:27, :88:44]\n wire _stalls_T_17 = _stalls_T_16 | flight_30;\t// @[FIFOFixer.scala:79:27, :88:44]\n wire _stalls_T_18 = _stalls_T_17 | flight_31;\t// @[FIFOFixer.scala:79:27, :88:44]\n wire _stalls_T_19 = _stalls_T_11 & _stalls_T_18;\t// @[FIFOFixer.scala:88:{15,26,44}]\n wire _stalls_T_20 = stalls_id_1 != a_id;\t// @[Mux.scala:30:73]\n wire _stalls_T_21 = a_noDomain | _stalls_T_20;\t// @[FIFOFixer.scala:63:29, :88:{65,71}]\n wire stalls_1 = _stalls_T_19 & _stalls_T_21;\t// @[FIFOFixer.scala:88:{26,50,65}]\n wire stall = _stall_T | stalls_1;\t// @[FIFOFixer.scala:88:50, :91:45]\n wire _anonOut_a_valid_T = ~stall;\t// @[FIFOFixer.scala:91:45, :95:50]\n wire _anonOut_a_valid_T_1 = _anonOut_a_valid_T;\t// @[FIFOFixer.scala:95:{47,50}]\n assign _anonOut_a_valid_T_2 = anonIn_a_valid & _anonOut_a_valid_T_1;\t// @[FIFOFixer.scala:95:{33,47}]\n assign anonOut_a_valid = _anonOut_a_valid_T_2;\t// @[FIFOFixer.scala:95:33]\n wire _anonIn_a_ready_T = ~stall;\t// @[FIFOFixer.scala:91:45, :95:50, :96:50]\n wire _anonIn_a_ready_T_1 = _anonIn_a_ready_T;\t// @[FIFOFixer.scala:96:{47,50}]\n assign _anonIn_a_ready_T_2 = anonOut_a_ready & _anonIn_a_ready_T_1;\t// @[FIFOFixer.scala:96:{33,47}]\n assign anonIn_a_ready = _anonIn_a_ready_T_2;\t// @[FIFOFixer.scala:96:33]\n reg [32:0] SourceIdFIFOed;\t// @[FIFOFixer.scala:115:35]\n wire [32:0] SourceIdSet;\t// @[FIFOFixer.scala:116:36]\n wire [32:0] SourceIdClear;\t// @[FIFOFixer.scala:117:38]\n wire [63:0] _SourceIdSet_T = 64'h1 << anonIn_a_bits_source;\t// @[OneHot.scala:58:35]\n assign SourceIdSet = a_first & _T_5 ? _SourceIdSet_T[32:0] : 33'h0;\t// @[OneHot.scala:58:35]\n wire [63:0] _SourceIdClear_T = 64'h1 << anonIn_d_bits_source;\t// @[OneHot.scala:58:35]\n assign SourceIdClear = d_first & _T_9 ? _SourceIdClear_T[32:0] : 33'h0;\t// @[OneHot.scala:58:35]\n wire [32:0] _SourceIdFIFOed_T = SourceIdFIFOed | SourceIdSet;\t// @[FIFOFixer.scala:115:35, :116:36, :126:40]\n wire allIDs_FIFOed = &SourceIdFIFOed;\t// @[FIFOFixer.scala:115:35, :127:41]\n wire [32:0] _a_notFIFO_T_6 = {1'h0, _a_notFIFO_T_5};\t// @[Parameters.scala:137:{31,41}]\n wire [32:0] _a_id_T_14 = {1'h0, _a_id_T_13};\t// @[Parameters.scala:137:{31,41}]\n wire [32:0] _a_id_T_15 = _a_id_T_14 & 33'h40000000;\t// @[Parameters.scala:137:{41,46}]\n wire [32:0] _a_id_T_16 = _a_id_T_15;\t// @[Parameters.scala:137:46]\n wire _a_id_T_17 = _a_id_T_16 == 33'h0;\t// @[Parameters.scala:137:{46,59}]\n wire _a_id_T_23 = _a_id_T_17;\t// @[Mux.scala:30:73]\n wire [31:0] _a_id_T_18 = {anonIn_1_a_bits_address[31], anonIn_1_a_bits_address[30:0] ^ 31'h40000000};\t// @[Parameters.scala:137:31]\n wire [32:0] _a_id_T_19 = {1'h0, _a_id_T_18};\t// @[Parameters.scala:137:{31,41}]\n wire [32:0] _a_id_T_20 = _a_id_T_19 & 33'h40000000;\t// @[Parameters.scala:137:{41,46}]\n wire [32:0] _a_id_T_21 = _a_id_T_20;\t// @[Parameters.scala:137:46]\n wire _a_id_T_22 = _a_id_T_21 == 33'h0;\t// @[Parameters.scala:137:{46,59}]\n wire [1:0] _a_id_T_24 = {_a_id_T_22, 1'h0};\t// @[Mux.scala:30:73]\n wire [1:0] _a_id_T_25 = {1'h0, _a_id_T_23} | _a_id_T_24;\t// @[Mux.scala:30:73]\n wire [1:0] a_id_1 = _a_id_T_25;\t// @[Mux.scala:30:73]\n wire a_noDomain_1 = a_id_1 == 2'h0;\t// @[Mux.scala:30:73]\n wire _a_first_T_1 = anonIn_1_a_ready & anonIn_1_a_valid;\t// @[Decoupled.scala:51:35]\n wire [26:0] _a_first_beats1_decode_T_3 = 27'hFFF << anonIn_1_a_bits_size;\t// @[package.scala:243:71]\n wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0];\t// @[package.scala:243:{71,76}]\n wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4;\t// @[package.scala:243:{46,76}]\n wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3];\t// @[package.scala:243:46]\n wire _a_first_beats1_opdata_T_1 = anonIn_1_a_bits_opcode[2];\t// @[Edges.scala:92:37]\n wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1;\t// @[Edges.scala:92:{28,37}]\n wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0;\t// @[Edges.scala:92:28, :220:59, :221:14]\n reg [8:0] a_first_counter_1;\t// @[Edges.scala:229:27]\n wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1;\t// @[Edges.scala:229:27, :230:28]\n wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0];\t// @[Edges.scala:230:28]\n wire a_first_1 = a_first_counter_1 == 9'h0;\t// @[Edges.scala:229:27, :231:25]\n wire _a_first_last_T_2 = a_first_counter_1 == 9'h1;\t// @[Edges.scala:229:27, :232:25]\n wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0;\t// @[Edges.scala:221:14, :232:43]\n wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3;\t// @[Edges.scala:232:{25,33,43}]\n wire a_first_done_1 = a_first_last_1 & _a_first_T_1;\t// @[Decoupled.scala:51:35]\n wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1;\t// @[Edges.scala:230:28, :234:27]\n wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1;\t// @[Edges.scala:221:14, :234:{25,27}]\n wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1;\t// @[Edges.scala:221:14, :230:28, :231:25, :236:21]\n wire _d_first_T_2 = x1_anonOut_d_ready & x1_anonOut_d_valid;\t// @[Decoupled.scala:51:35]\n wire [26:0] _d_first_beats1_decode_T_3 = 27'hFFF << x1_anonOut_d_bits_size;\t// @[package.scala:243:71]\n wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0];\t// @[package.scala:243:{71,76}]\n wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4;\t// @[package.scala:243:{46,76}]\n wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3];\t// @[package.scala:243:46]\n wire d_first_beats1_opdata_1 = x1_anonOut_d_bits_opcode[0];\t// @[Edges.scala:106:36]\n wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0;\t// @[Edges.scala:106:36, :220:59, :221:14]\n reg [8:0] d_first_counter_1;\t// @[Edges.scala:229:27]\n wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1;\t// @[Edges.scala:229:27, :230:28]\n wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0];\t// @[Edges.scala:230:28]\n wire d_first_first_1 = d_first_counter_1 == 9'h0;\t// @[Edges.scala:229:27, :231:25]\n wire _d_first_last_T_2 = d_first_counter_1 == 9'h1;\t// @[Edges.scala:229:27, :232:25]\n wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0;\t// @[Edges.scala:221:14, :232:43]\n wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3;\t// @[Edges.scala:232:{25,33,43}]\n wire d_first_done_1 = d_first_last_1 & _d_first_T_2;\t// @[Decoupled.scala:51:35]\n wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1;\t// @[Edges.scala:230:28, :234:27]\n wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1;\t// @[Edges.scala:221:14, :234:{25,27}]\n wire [8:0] _d_first_counter_T_1 = d_first_first_1 ? d_first_beats1_1 : d_first_counter1_1;\t// @[Edges.scala:221:14, :230:28, :231:25, :236:21]\n wire _d_first_T_3 = x1_anonOut_d_bits_opcode != 3'h6;\t// @[FIFOFixer.scala:75:63]\n wire d_first_1 = d_first_first_1 & _d_first_T_3;\t// @[FIFOFixer.scala:75:{42,63}]\n reg flight_1_0;\t// @[FIFOFixer.scala:79:27]\n reg flight_1_1;\t// @[FIFOFixer.scala:79:27]\n wire _T_55 = anonIn_1_d_ready & anonIn_1_d_valid;\t// @[Decoupled.scala:51:35]\n assign x1_anonOut_a_valid = _anonOut_a_valid_T_5;\t// @[FIFOFixer.scala:95:33]\n assign anonIn_1_a_ready = _anonIn_a_ready_T_5;\t// @[FIFOFixer.scala:96:33]\n reg [1:0] SourceIdFIFOed_1;\t// @[FIFOFixer.scala:115:35]\n wire [1:0] SourceIdSet_1;\t// @[FIFOFixer.scala:116:36]\n wire [1:0] SourceIdClear_1;\t// @[FIFOFixer.scala:117:38]\n wire [1:0] _SourceIdSet_T_1 = 2'h1 << anonIn_1_a_bits_source;\t// @[OneHot.scala:58:35]\n assign SourceIdSet_1 = a_first_1 & _a_first_T_1 ? _SourceIdSet_T_1 : 2'h0;\t// @[OneHot.scala:58:35]\n wire [1:0] _SourceIdClear_T_1 = 2'h1 << anonIn_1_d_bits_source;\t// @[OneHot.scala:58:35]\n assign SourceIdClear_1 = d_first_1 & _T_55 ? _SourceIdClear_T_1 : 2'h0;\t// @[OneHot.scala:58:35]\n wire [1:0] _SourceIdFIFOed_T_1 = SourceIdFIFOed_1 | SourceIdSet_1;\t// @[FIFOFixer.scala:115:35, :116:36, :126:40]\n wire allIDs_FIFOed_1 = &SourceIdFIFOed_1;\t// @[FIFOFixer.scala:115:35, :127:41]\n wire _T_1 = a_first & _T_5;\t// @[Decoupled.scala:51:35]\n wire _T_3 = d_first & _T_9;\t// @[Decoupled.scala:51:35]\n wire _T_47 = a_first_1 & _a_first_T_1;\t// @[Decoupled.scala:51:35]\n wire _T_49 = d_first_1 & _T_55;\t// @[Decoupled.scala:51:35]\n always @(posedge clock) begin\t// @[FIFOFixer.scala:50:9]\n if (reset) begin\t// @[FIFOFixer.scala:50:9]\n a_first_counter <= 9'h0;\t// @[Edges.scala:229:27]\n d_first_counter <= 9'h0;\t// @[Edges.scala:229:27]\n flight_0 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_1 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_2 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_3 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_4 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_5 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_6 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_7 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_8 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_9 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_10 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_11 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_12 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_13 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_14 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_15 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_16 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_17 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_18 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_19 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_20 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_21 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_22 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_23 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_24 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_25 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_26 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_27 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_28 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_29 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_30 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_31 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_32 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n SourceIdFIFOed <= 33'h0;\t// @[FIFOFixer.scala:115:35]\n a_first_counter_1 <= 9'h0;\t// @[Edges.scala:229:27]\n d_first_counter_1 <= 9'h0;\t// @[Edges.scala:229:27]\n flight_1_0 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_1_1 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n SourceIdFIFOed_1 <= 2'h0;\t// @[FIFOFixer.scala:115:35]\n end\n else begin\t// @[FIFOFixer.scala:50:9]\n if (_a_first_T)\t// @[Decoupled.scala:51:35]\n a_first_counter <= _a_first_counter_T;\t// @[Edges.scala:229:27, :236:21]\n if (_d_first_T)\t// @[Decoupled.scala:51:35]\n d_first_counter <= _d_first_counter_T;\t// @[Edges.scala:229:27, :236:21]\n flight_0 <= ~(_T_3 & anonIn_d_bits_source == 6'h0) & (_T_1 & anonIn_a_bits_source == 6'h0 | flight_0);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_1 <= ~(_T_3 & anonIn_d_bits_source == 6'h1) & (_T_1 & anonIn_a_bits_source == 6'h1 | flight_1);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_2 <= ~(_T_3 & anonIn_d_bits_source == 6'h2) & (_T_1 & anonIn_a_bits_source == 6'h2 | flight_2);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_3 <= ~(_T_3 & anonIn_d_bits_source == 6'h3) & (_T_1 & anonIn_a_bits_source == 6'h3 | flight_3);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_4 <= ~(_T_3 & anonIn_d_bits_source == 6'h4) & (_T_1 & anonIn_a_bits_source == 6'h4 | flight_4);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_5 <= ~(_T_3 & anonIn_d_bits_source == 6'h5) & (_T_1 & anonIn_a_bits_source == 6'h5 | flight_5);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_6 <= ~(_T_3 & anonIn_d_bits_source == 6'h6) & (_T_1 & anonIn_a_bits_source == 6'h6 | flight_6);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_7 <= ~(_T_3 & anonIn_d_bits_source == 6'h7) & (_T_1 & anonIn_a_bits_source == 6'h7 | flight_7);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_8 <= ~(_T_3 & anonIn_d_bits_source == 6'h8) & (_T_1 & anonIn_a_bits_source == 6'h8 | flight_8);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_9 <= ~(_T_3 & anonIn_d_bits_source == 6'h9) & (_T_1 & anonIn_a_bits_source == 6'h9 | flight_9);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_10 <= ~(_T_3 & anonIn_d_bits_source == 6'hA) & (_T_1 & anonIn_a_bits_source == 6'hA | flight_10);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_11 <= ~(_T_3 & anonIn_d_bits_source == 6'hB) & (_T_1 & anonIn_a_bits_source == 6'hB | flight_11);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_12 <= ~(_T_3 & anonIn_d_bits_source == 6'hC) & (_T_1 & anonIn_a_bits_source == 6'hC | flight_12);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_13 <= ~(_T_3 & anonIn_d_bits_source == 6'hD) & (_T_1 & anonIn_a_bits_source == 6'hD | flight_13);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_14 <= ~(_T_3 & anonIn_d_bits_source == 6'hE) & (_T_1 & anonIn_a_bits_source == 6'hE | flight_14);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_15 <= ~(_T_3 & anonIn_d_bits_source == 6'hF) & (_T_1 & anonIn_a_bits_source == 6'hF | flight_15);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_16 <= ~(_T_3 & anonIn_d_bits_source == 6'h10) & (_T_1 & anonIn_a_bits_source == 6'h10 | flight_16);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_17 <= ~(_T_3 & anonIn_d_bits_source == 6'h11) & (_T_1 & anonIn_a_bits_source == 6'h11 | flight_17);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_18 <= ~(_T_3 & anonIn_d_bits_source == 6'h12) & (_T_1 & anonIn_a_bits_source == 6'h12 | flight_18);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_19 <= ~(_T_3 & anonIn_d_bits_source == 6'h13) & (_T_1 & anonIn_a_bits_source == 6'h13 | flight_19);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_20 <= ~(_T_3 & anonIn_d_bits_source == 6'h14) & (_T_1 & anonIn_a_bits_source == 6'h14 | flight_20);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_21 <= ~(_T_3 & anonIn_d_bits_source == 6'h15) & (_T_1 & anonIn_a_bits_source == 6'h15 | flight_21);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_22 <= ~(_T_3 & anonIn_d_bits_source == 6'h16) & (_T_1 & anonIn_a_bits_source == 6'h16 | flight_22);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_23 <= ~(_T_3 & anonIn_d_bits_source == 6'h17) & (_T_1 & anonIn_a_bits_source == 6'h17 | flight_23);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_24 <= ~(_T_3 & anonIn_d_bits_source == 6'h18) & (_T_1 & anonIn_a_bits_source == 6'h18 | flight_24);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_25 <= ~(_T_3 & anonIn_d_bits_source == 6'h19) & (_T_1 & anonIn_a_bits_source == 6'h19 | flight_25);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_26 <= ~(_T_3 & anonIn_d_bits_source == 6'h1A) & (_T_1 & anonIn_a_bits_source == 6'h1A | flight_26);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_27 <= ~(_T_3 & anonIn_d_bits_source == 6'h1B) & (_T_1 & anonIn_a_bits_source == 6'h1B | flight_27);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_28 <= ~(_T_3 & anonIn_d_bits_source == 6'h1C) & (_T_1 & anonIn_a_bits_source == 6'h1C | flight_28);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_29 <= ~(_T_3 & anonIn_d_bits_source == 6'h1D) & (_T_1 & anonIn_a_bits_source == 6'h1D | flight_29);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_30 <= ~(_T_3 & anonIn_d_bits_source == 6'h1E) & (_T_1 & anonIn_a_bits_source == 6'h1E | flight_30);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_31 <= ~(_T_3 & anonIn_d_bits_source == 6'h1F) & (_T_1 & anonIn_a_bits_source == 6'h1F | flight_31);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_32 <= ~(_T_3 & anonIn_d_bits_source == 6'h20) & (_T_1 & anonIn_a_bits_source == 6'h20 | flight_32);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n SourceIdFIFOed <= _SourceIdFIFOed_T;\t// @[FIFOFixer.scala:115:35, :126:40]\n if (_a_first_T_1)\t// @[Decoupled.scala:51:35]\n a_first_counter_1 <= _a_first_counter_T_1;\t// @[Edges.scala:229:27, :236:21]\n if (_d_first_T_2)\t// @[Decoupled.scala:51:35]\n d_first_counter_1 <= _d_first_counter_T_1;\t// @[Edges.scala:229:27, :236:21]\n flight_1_0 <= ~(_T_49 & ~anonIn_1_d_bits_source) & (_T_47 & ~anonIn_1_a_bits_source | flight_1_0);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_1_1 <= ~(_T_49 & anonIn_1_d_bits_source) & (_T_47 & anonIn_1_a_bits_source | flight_1_1);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n SourceIdFIFOed_1 <= _SourceIdFIFOed_T_1;\t// @[FIFOFixer.scala:115:35, :126:40]\n end\n if (_stalls_id_T_3)\t// @[FIFOFixer.scala:85:56]\n stalls_id <= a_id;\t// @[Mux.scala:30:73]\n if (_stalls_id_T_7)\t// @[FIFOFixer.scala:85:56]\n stalls_id_1 <= a_id;\t// @[Mux.scala:30:73]\n always @(posedge)\n TLMonitor_2 monitor (\t// @[Nodes.scala:27:25]\n .clock (clock),\n .reset (reset),\n .io_in_a_ready (anonIn_a_ready),\t// @[MixedNode.scala:551:17]\n .io_in_a_valid (anonIn_a_valid),\t// @[MixedNode.scala:551:17]\n .io_in_a_bits_opcode (anonIn_a_bits_opcode),\t// @[MixedNode.scala:551:17]\n .io_in_a_bits_param (anonIn_a_bits_param),\t// @[MixedNode.scala:551:17]\n .io_in_a_bits_size (anonIn_a_bits_size),\t// @[MixedNode.scala:551:17]\n .io_in_a_bits_source (anonIn_a_bits_source),\t// @[MixedNode.scala:551:17]\n .io_in_a_bits_address (anonIn_a_bits_address),\t// @[MixedNode.scala:551:17]\n .io_in_a_bits_user_amba_prot_bufferable (anonIn_a_bits_user_amba_prot_bufferable),\t// @[MixedNode.scala:551:17]\n .io_in_a_bits_user_amba_prot_modifiable (anonIn_a_bits_user_amba_prot_modifiable),\t// @[MixedNode.scala:551:17]\n .io_in_a_bits_user_amba_prot_readalloc (anonIn_a_bits_user_amba_prot_readalloc),\t// @[MixedNode.scala:551:17]\n .io_in_a_bits_user_amba_prot_writealloc (anonIn_a_bits_user_amba_prot_writealloc),\t// @[MixedNode.scala:551:17]\n .io_in_a_bits_user_amba_prot_privileged (anonIn_a_bits_user_amba_prot_privileged),\t// @[MixedNode.scala:551:17]\n .io_in_a_bits_user_amba_prot_secure (anonIn_a_bits_user_amba_prot_secure),\t// @[MixedNode.scala:551:17]\n .io_in_a_bits_user_amba_prot_fetch (anonIn_a_bits_user_amba_prot_fetch),\t// @[MixedNode.scala:551:17]\n .io_in_a_bits_mask (anonIn_a_bits_mask),\t// @[MixedNode.scala:551:17]\n .io_in_a_bits_data (anonIn_a_bits_data),\t// @[MixedNode.scala:551:17]\n .io_in_a_bits_corrupt (anonIn_a_bits_corrupt),\t// @[MixedNode.scala:551:17]\n .io_in_d_ready (anonIn_d_ready),\t// @[MixedNode.scala:551:17]\n .io_in_d_valid (anonIn_d_valid),\t// @[MixedNode.scala:551:17]\n .io_in_d_bits_opcode (anonIn_d_bits_opcode),\t// @[MixedNode.scala:551:17]\n .io_in_d_bits_param (anonIn_d_bits_param),\t// @[MixedNode.scala:551:17]\n .io_in_d_bits_size (anonIn_d_bits_size),\t// @[MixedNode.scala:551:17]\n .io_in_d_bits_source (anonIn_d_bits_source),\t// @[MixedNode.scala:551:17]\n .io_in_d_bits_sink (anonIn_d_bits_sink),\t// @[MixedNode.scala:551:17]\n .io_in_d_bits_denied (anonIn_d_bits_denied),\t// @[MixedNode.scala:551:17]\n .io_in_d_bits_data (anonIn_d_bits_data),\t// @[MixedNode.scala:551:17]\n .io_in_d_bits_corrupt (anonIn_d_bits_corrupt)\t// @[MixedNode.scala:551:17]\n );\t// @[Nodes.scala:27:25]\n TLMonitor_3 monitor_1 (\t// @[Nodes.scala:27:25]\n .clock (clock),\n .reset (reset),\n .io_in_a_ready (anonIn_1_a_ready),\t// @[MixedNode.scala:551:17]\n .io_in_a_valid (anonIn_1_a_valid),\t// @[MixedNode.scala:551:17]\n .io_in_a_bits_opcode (anonIn_1_a_bits_opcode),\t// @[MixedNode.scala:551:17]\n .io_in_a_bits_param (anonIn_1_a_bits_param),\t// @[MixedNode.scala:551:17]\n .io_in_a_bits_size (anonIn_1_a_bits_size),\t// @[MixedNode.scala:551:17]\n .io_in_a_bits_source (anonIn_1_a_bits_source),\t// @[MixedNode.scala:551:17]\n .io_in_a_bits_address (anonIn_1_a_bits_address),\t// @[MixedNode.scala:551:17]\n .io_in_a_bits_user_amba_prot_bufferable (anonIn_1_a_bits_user_amba_prot_bufferable),\t// @[MixedNode.scala:551:17]\n .io_in_a_bits_user_amba_prot_modifiable (anonIn_1_a_bits_user_amba_prot_modifiable),\t// @[MixedNode.scala:551:17]\n .io_in_a_bits_user_amba_prot_readalloc (anonIn_1_a_bits_user_amba_prot_readalloc),\t// @[MixedNode.scala:551:17]\n .io_in_a_bits_user_amba_prot_writealloc (anonIn_1_a_bits_user_amba_prot_writealloc),\t// @[MixedNode.scala:551:17]\n .io_in_a_bits_user_amba_prot_privileged (anonIn_1_a_bits_user_amba_prot_privileged),\t// @[MixedNode.scala:551:17]\n .io_in_a_bits_user_amba_prot_secure (anonIn_1_a_bits_user_amba_prot_secure),\t// @[MixedNode.scala:551:17]\n .io_in_a_bits_user_amba_prot_fetch (anonIn_1_a_bits_user_amba_prot_fetch),\t// @[MixedNode.scala:551:17]\n .io_in_a_bits_mask (anonIn_1_a_bits_mask),\t// @[MixedNode.scala:551:17]\n .io_in_a_bits_data (anonIn_1_a_bits_data),\t// @[MixedNode.scala:551:17]\n .io_in_a_bits_corrupt (anonIn_1_a_bits_corrupt),\t// @[MixedNode.scala:551:17]\n .io_in_d_ready (anonIn_1_d_ready),\t// @[MixedNode.scala:551:17]\n .io_in_d_valid (anonIn_1_d_valid),\t// @[MixedNode.scala:551:17]\n .io_in_d_bits_opcode (anonIn_1_d_bits_opcode),\t// @[MixedNode.scala:551:17]\n .io_in_d_bits_param (anonIn_1_d_bits_param),\t// @[MixedNode.scala:551:17]\n .io_in_d_bits_size (anonIn_1_d_bits_size),\t// @[MixedNode.scala:551:17]\n .io_in_d_bits_source (anonIn_1_d_bits_source),\t// @[MixedNode.scala:551:17]\n .io_in_d_bits_sink (anonIn_1_d_bits_sink),\t// @[MixedNode.scala:551:17]\n .io_in_d_bits_denied (anonIn_1_d_bits_denied),\t// @[MixedNode.scala:551:17]\n .io_in_d_bits_data (anonIn_1_d_bits_data),\t// @[MixedNode.scala:551:17]\n .io_in_d_bits_corrupt (anonIn_1_d_bits_corrupt)\t// @[MixedNode.scala:551:17]\n );\t// @[Nodes.scala:27:25]\n assign auto_anon_in_1_a_ready = auto_anon_in_1_a_ready_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_in_1_d_valid = auto_anon_in_1_d_valid_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_in_1_d_bits_opcode = auto_anon_in_1_d_bits_opcode_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_in_1_d_bits_param = auto_anon_in_1_d_bits_param_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_in_1_d_bits_size = auto_anon_in_1_d_bits_size_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_in_1_d_bits_source = auto_anon_in_1_d_bits_source_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_in_1_d_bits_sink = auto_anon_in_1_d_bits_sink_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_in_1_d_bits_denied = auto_anon_in_1_d_bits_denied_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_in_1_d_bits_data = auto_anon_in_1_d_bits_data_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_in_1_d_bits_corrupt = auto_anon_in_1_d_bits_corrupt_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_in_0_a_ready = auto_anon_in_0_a_ready_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_in_0_d_valid = auto_anon_in_0_d_valid_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_in_0_d_bits_opcode = auto_anon_in_0_d_bits_opcode_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_in_0_d_bits_param = auto_anon_in_0_d_bits_param_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_in_0_d_bits_size = auto_anon_in_0_d_bits_size_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_in_0_d_bits_source = auto_anon_in_0_d_bits_source_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_in_0_d_bits_sink = auto_anon_in_0_d_bits_sink_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_in_0_d_bits_denied = auto_anon_in_0_d_bits_denied_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_in_0_d_bits_data = auto_anon_in_0_d_bits_data_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_in_0_d_bits_corrupt = auto_anon_in_0_d_bits_corrupt_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_1_a_valid = auto_anon_out_1_a_valid_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_1_a_bits_opcode = auto_anon_out_1_a_bits_opcode_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_1_a_bits_param = auto_anon_out_1_a_bits_param_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_1_a_bits_size = auto_anon_out_1_a_bits_size_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_1_a_bits_source = auto_anon_out_1_a_bits_source_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_1_a_bits_address = auto_anon_out_1_a_bits_address_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_1_a_bits_user_amba_prot_bufferable = auto_anon_out_1_a_bits_user_amba_prot_bufferable_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_1_a_bits_user_amba_prot_modifiable = auto_anon_out_1_a_bits_user_amba_prot_modifiable_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_1_a_bits_user_amba_prot_readalloc = auto_anon_out_1_a_bits_user_amba_prot_readalloc_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_1_a_bits_user_amba_prot_writealloc = auto_anon_out_1_a_bits_user_amba_prot_writealloc_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_1_a_bits_user_amba_prot_privileged = auto_anon_out_1_a_bits_user_amba_prot_privileged_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_1_a_bits_user_amba_prot_secure = auto_anon_out_1_a_bits_user_amba_prot_secure_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_1_a_bits_user_amba_prot_fetch = auto_anon_out_1_a_bits_user_amba_prot_fetch_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_1_a_bits_mask = auto_anon_out_1_a_bits_mask_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_1_a_bits_data = auto_anon_out_1_a_bits_data_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_1_a_bits_corrupt = auto_anon_out_1_a_bits_corrupt_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_1_d_ready = auto_anon_out_1_d_ready_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_0_a_valid = auto_anon_out_0_a_valid_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_0_a_bits_opcode = auto_anon_out_0_a_bits_opcode_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_0_a_bits_param = auto_anon_out_0_a_bits_param_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_0_a_bits_size = auto_anon_out_0_a_bits_size_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_0_a_bits_source = auto_anon_out_0_a_bits_source_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_0_a_bits_address = auto_anon_out_0_a_bits_address_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_0_a_bits_user_amba_prot_bufferable = auto_anon_out_0_a_bits_user_amba_prot_bufferable_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_0_a_bits_user_amba_prot_modifiable = auto_anon_out_0_a_bits_user_amba_prot_modifiable_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_0_a_bits_user_amba_prot_readalloc = auto_anon_out_0_a_bits_user_amba_prot_readalloc_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_0_a_bits_user_amba_prot_writealloc = auto_anon_out_0_a_bits_user_amba_prot_writealloc_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_0_a_bits_user_amba_prot_privileged = auto_anon_out_0_a_bits_user_amba_prot_privileged_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_0_a_bits_user_amba_prot_secure = auto_anon_out_0_a_bits_user_amba_prot_secure_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_0_a_bits_user_amba_prot_fetch = auto_anon_out_0_a_bits_user_amba_prot_fetch_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_0_a_bits_mask = auto_anon_out_0_a_bits_mask_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_0_a_bits_data = auto_anon_out_0_a_bits_data_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_0_a_bits_corrupt = auto_anon_out_0_a_bits_corrupt_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_0_d_ready = auto_anon_out_0_d_ready_0;\t// @[FIFOFixer.scala:50:9]\nendmodule"}}},{"rowIdx":594,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to the following Chisel files.\nFile Transposer.scala:\npackage gemmini\n\nimport chisel3._\nimport chisel3.util._\nimport Util._\n\ntrait Transposer[T <: Data] extends Module {\n def dim: Int\n def dataType: T\n val io = IO(new Bundle {\n val inRow = Flipped(Decoupled(Vec(dim, dataType)))\n val outCol = Decoupled(Vec(dim, dataType))\n })\n}\n\nclass PipelinedTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] {\n require(isPow2(dim))\n val regArray = Seq.fill(dim, dim)(Reg(dataType))\n val regArrayT = regArray.transpose\n val sMoveUp :: sMoveLeft :: Nil = Enum(2)\n val state = RegInit(sMoveUp)\n val leftCounter = RegInit(0.U(log2Ceil(dim+1).W)) //(io.inRow.fire && state === sMoveLeft, dim+1)\n val upCounter = RegInit(0.U(log2Ceil(dim+1).W)) //Counter(io.inRow.fire && state === sMoveUp, dim+1)\n\n io.outCol.valid := 0.U\n io.inRow.ready := 0.U\n switch(state) {\n is(sMoveUp) {\n io.inRow.ready := upCounter <= dim.U\n io.outCol.valid := leftCounter > 0.U\n when(io.inRow.fire) {\n upCounter := upCounter + 1.U\n }\n when(upCounter === (dim-1).U) {\n state := sMoveLeft\n leftCounter := 0.U\n }\n when(io.outCol.fire) {\n leftCounter := leftCounter - 1.U\n }\n }\n is(sMoveLeft) {\n io.inRow.ready := leftCounter <= dim.U // TODO: this is naive\n io.outCol.valid := upCounter > 0.U\n when(leftCounter === (dim-1).U) {\n state := sMoveUp\n }\n when(io.inRow.fire) {\n leftCounter := leftCounter + 1.U\n upCounter := 0.U\n }\n when(io.outCol.fire) {\n upCounter := upCounter - 1.U\n }\n }\n }\n\n // Propagate input from bottom row to top row systolically in the move up phase\n // TODO: need to iterate over columns to connect Chisel values of type T\n // Should be able to operate directly on the Vec, but Seq and Vec don't mix (try Array?)\n for (colIdx <- 0 until dim) {\n regArray.foldRight(io.inRow.bits(colIdx)) {\n case (regRow, prevReg) =>\n when (state === sMoveUp) {\n regRow(colIdx) := prevReg\n }\n regRow(colIdx)\n }\n }\n\n // Propagate input from right side to left side systolically in the move left phase\n for (rowIdx <- 0 until dim) {\n regArrayT.foldRight(io.inRow.bits(rowIdx)) {\n case (regCol, prevReg) =>\n when (state === sMoveLeft) {\n regCol(rowIdx) := prevReg\n }\n regCol(rowIdx)\n }\n }\n\n // Pull from the left side or the top side based on the state\n for (idx <- 0 until dim) {\n when (state === sMoveUp) {\n io.outCol.bits(idx) := regArray(0)(idx)\n }.elsewhen(state === sMoveLeft) {\n io.outCol.bits(idx) := regArrayT(0)(idx)\n }.otherwise {\n io.outCol.bits(idx) := DontCare\n }\n }\n}\n\nclass AlwaysOutTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] {\n require(isPow2(dim))\n\n val LEFT_DIR = 0.U(1.W)\n val UP_DIR = 1.U(1.W)\n\n class PE extends Module {\n val io = IO(new Bundle {\n val inR = Input(dataType)\n val inD = Input(dataType)\n val outL = Output(dataType)\n val outU = Output(dataType)\n val dir = Input(UInt(1.W))\n val en = Input(Bool())\n })\n\n val reg = RegEnable(Mux(io.dir === LEFT_DIR, io.inR, io.inD), io.en)\n\n io.outU := reg\n io.outL := reg\n }\n\n val pes = Seq.fill(dim,dim)(Module(new PE))\n val counter = RegInit(0.U((log2Ceil(dim) max 1).W)) // TODO replace this with a standard Chisel counter\n val dir = RegInit(LEFT_DIR)\n\n // Wire up horizontal signals\n for (row <- 0 until dim; col <- 0 until dim) {\n val right_in = if (col == dim-1) io.inRow.bits(row) else pes(row)(col+1).io.outL\n pes(row)(col).io.inR := right_in\n }\n\n // Wire up vertical signals\n for (row <- 0 until dim; col <- 0 until dim) {\n val down_in = if (row == dim-1) io.inRow.bits(col) else pes(row+1)(col).io.outU\n pes(row)(col).io.inD := down_in\n }\n\n // Wire up global signals\n pes.flatten.foreach(_.io.dir := dir)\n pes.flatten.foreach(_.io.en := io.inRow.fire)\n\n io.outCol.valid := true.B\n io.inRow.ready := true.B\n\n val left_out = VecInit(pes.transpose.head.map(_.io.outL))\n val up_out = VecInit(pes.head.map(_.io.outU))\n\n io.outCol.bits := Mux(dir === LEFT_DIR, left_out, up_out)\n\n when (io.inRow.fire) {\n counter := wrappingAdd(counter, 1.U, dim)\n }\n\n when (counter === (dim-1).U && io.inRow.fire) {\n dir := ~dir\n }\n}\n\nclass NaiveTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] {\n val regArray = Seq.fill(dim, dim)(Reg(dataType))\n val regArrayT = regArray.transpose\n // state = 0 => filling regArray row-wise, state = 1 => draining regArray column-wise\n val state = RegInit(0.U(1.W))\n val countInc = io.inRow.fire || io.outCol.fire\n val (countValue, countWrap) = Counter(countInc, dim)\n\n io.inRow.ready := state === 0.U\n io.outCol.valid := state === 1.U\n\n for (i <- 0 until dim) {\n for (j <- 0 until dim) {\n when(countValue === i.U && io.inRow.fire) {\n regArray(i)(j) := io.inRow.bits(j)\n }\n }\n }\n\n for (i <- 0 until dim) {\n io.outCol.bits(i) := 0.U\n for (j <- 0 until dim) {\n when(countValue === j.U) {\n io.outCol.bits(i) := regArrayT(j)(i)\n }\n }\n }\n\n when (io.inRow.fire && countWrap) {\n state := 1.U\n }\n when (io.outCol.fire && countWrap) {\n state := 0.U\n }\n\n assert(!(state === 0.U) || !io.outCol.fire)\n assert(!(state === 1.U) || !io.inRow.fire)\n}\n"},"response":{"kind":"string","value":"module PE_220(\t// @[Transposer.scala:100:9]\n input clock,\t// @[Transposer.scala:100:9]\n input reset,\t// @[Transposer.scala:100:9]\n input [7:0] io_inR,\t// @[Transposer.scala:101:16]\n input [7:0] io_inD,\t// @[Transposer.scala:101:16]\n output [7:0] io_outL,\t// @[Transposer.scala:101:16]\n output [7:0] io_outU,\t// @[Transposer.scala:101:16]\n input io_dir,\t// @[Transposer.scala:101:16]\n input io_en\t// @[Transposer.scala:101:16]\n);\n\n wire [7:0] io_inR_0 = io_inR;\t// @[Transposer.scala:100:9]\n wire [7:0] io_inD_0 = io_inD;\t// @[Transposer.scala:100:9]\n wire io_dir_0 = io_dir;\t// @[Transposer.scala:100:9]\n wire io_en_0 = io_en;\t// @[Transposer.scala:100:9]\n wire [7:0] io_outL_0;\t// @[Transposer.scala:100:9]\n wire [7:0] io_outU_0;\t// @[Transposer.scala:100:9]\n wire _reg_T = ~io_dir_0;\t// @[Transposer.scala:100:9, :110:36]\n wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0;\t// @[Transposer.scala:100:9, :110:{28,36}]\n reg [7:0] reg_0;\t// @[Transposer.scala:110:24]\n assign io_outL_0 = reg_0;\t// @[Transposer.scala:100:9, :110:24]\n assign io_outU_0 = reg_0;\t// @[Transposer.scala:100:9, :110:24]\n always @(posedge clock) begin\t// @[Transposer.scala:100:9]\n if (io_en_0)\t// @[Transposer.scala:100:9]\n reg_0 <= _reg_T_1;\t// @[Transposer.scala:110:{24,28}]\n always @(posedge)\n assign io_outL = io_outL_0;\t// @[Transposer.scala:100:9]\n assign io_outU = io_outU_0;\t// @[Transposer.scala:100:9]\nendmodule"}}},{"rowIdx":595,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to the following Chisel files.\nFile PMP.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.rocket\n\nimport chisel3._\nimport chisel3.util.{Cat, log2Ceil}\nimport org.chipsalliance.cde.config._\nimport freechips.rocketchip.tile._\nimport freechips.rocketchip.util._\n\nclass PMPConfig extends Bundle {\n val l = Bool()\n val res = UInt(2.W)\n val a = UInt(2.W)\n val x = Bool()\n val w = Bool()\n val r = Bool()\n}\n\nobject PMP {\n def lgAlign = 2\n\n def apply(reg: PMPReg): PMP = {\n val pmp = Wire(new PMP()(reg.p))\n pmp.cfg := reg.cfg\n pmp.addr := reg.addr\n pmp.mask := pmp.computeMask\n pmp\n }\n}\n\nclass PMPReg(implicit p: Parameters) extends CoreBundle()(p) {\n val cfg = new PMPConfig\n val addr = UInt((paddrBits - PMP.lgAlign).W)\n\n def reset(): Unit = {\n cfg.a := 0.U\n cfg.l := 0.U\n }\n\n def readAddr = if (pmpGranularity.log2 == PMP.lgAlign) addr else {\n val mask = ((BigInt(1) << (pmpGranularity.log2 - PMP.lgAlign)) - 1).U\n Mux(napot, addr | (mask >> 1), ~(~addr | mask))\n }\n def napot = cfg.a(1)\n def torNotNAPOT = cfg.a(0)\n def tor = !napot && torNotNAPOT\n def cfgLocked = cfg.l\n def addrLocked(next: PMPReg) = cfgLocked || next.cfgLocked && next.tor\n}\n\nclass PMP(implicit p: Parameters) extends PMPReg {\n val mask = UInt(paddrBits.W)\n\n import PMP._\n def computeMask = {\n val base = Cat(addr, cfg.a(0)) | ((pmpGranularity - 1).U >> lgAlign)\n Cat(base & ~(base + 1.U), ((1 << lgAlign) - 1).U)\n }\n private def comparand = ~(~(addr << lgAlign) | (pmpGranularity - 1).U)\n\n private def pow2Match(x: UInt, lgSize: UInt, lgMaxSize: Int) = {\n def eval(a: UInt, b: UInt, m: UInt) = ((a ^ b) & ~m) === 0.U\n if (lgMaxSize <= pmpGranularity.log2) {\n eval(x, comparand, mask)\n } else {\n // break up the circuit; the MSB part will be CSE'd\n val lsbMask = mask | UIntToOH1(lgSize, lgMaxSize)\n val msbMatch = eval(x >> lgMaxSize, comparand >> lgMaxSize, mask >> lgMaxSize)\n val lsbMatch = eval(x(lgMaxSize-1, 0), comparand(lgMaxSize-1, 0), lsbMask(lgMaxSize-1, 0))\n msbMatch && lsbMatch\n }\n }\n\n private def boundMatch(x: UInt, lsbMask: UInt, lgMaxSize: Int) = {\n if (lgMaxSize <= pmpGranularity.log2) {\n x < comparand\n } else {\n // break up the circuit; the MSB part will be CSE'd\n val msbsLess = (x >> lgMaxSize) < (comparand >> lgMaxSize)\n val msbsEqual = ((x >> lgMaxSize) ^ (comparand >> lgMaxSize)) === 0.U\n val lsbsLess = (x(lgMaxSize-1, 0) | lsbMask) < comparand(lgMaxSize-1, 0)\n msbsLess || (msbsEqual && lsbsLess)\n }\n }\n\n private def lowerBoundMatch(x: UInt, lgSize: UInt, lgMaxSize: Int) =\n !boundMatch(x, UIntToOH1(lgSize, lgMaxSize), lgMaxSize)\n\n private def upperBoundMatch(x: UInt, lgMaxSize: Int) =\n boundMatch(x, 0.U, lgMaxSize)\n\n private def rangeMatch(x: UInt, lgSize: UInt, lgMaxSize: Int, prev: PMP) =\n prev.lowerBoundMatch(x, lgSize, lgMaxSize) && upperBoundMatch(x, lgMaxSize)\n\n private def pow2Homogeneous(x: UInt, pgLevel: UInt) = {\n val maskHomogeneous = pgLevelMap { idxBits => if (idxBits > paddrBits) false.B else mask(idxBits - 1) } (pgLevel)\n maskHomogeneous || (pgLevelMap { idxBits => ((x ^ comparand) >> idxBits) =/= 0.U } (pgLevel))\n }\n\n private def pgLevelMap[T](f: Int => T) = (0 until pgLevels).map { i =>\n f(pgIdxBits + (pgLevels - 1 - i) * pgLevelBits)\n }\n\n private def rangeHomogeneous(x: UInt, pgLevel: UInt, prev: PMP) = {\n val beginsAfterLower = !(x < prev.comparand)\n val beginsAfterUpper = !(x < comparand)\n\n val pgMask = pgLevelMap { idxBits => (((BigInt(1) << paddrBits) - (BigInt(1) << idxBits)) max 0).U } (pgLevel)\n val endsBeforeLower = (x & pgMask) < (prev.comparand & pgMask)\n val endsBeforeUpper = (x & pgMask) < (comparand & pgMask)\n\n endsBeforeLower || beginsAfterUpper || (beginsAfterLower && endsBeforeUpper)\n }\n\n // returns whether this PMP completely contains, or contains none of, a page\n def homogeneous(x: UInt, pgLevel: UInt, prev: PMP): Bool =\n Mux(napot, pow2Homogeneous(x, pgLevel), !torNotNAPOT || rangeHomogeneous(x, pgLevel, prev))\n\n // returns whether this matching PMP fully contains the access\n def aligned(x: UInt, lgSize: UInt, lgMaxSize: Int, prev: PMP): Bool = if (lgMaxSize <= pmpGranularity.log2) true.B else {\n val lsbMask = UIntToOH1(lgSize, lgMaxSize)\n val straddlesLowerBound = ((x >> lgMaxSize) ^ (prev.comparand >> lgMaxSize)) === 0.U && (prev.comparand(lgMaxSize-1, 0) & ~x(lgMaxSize-1, 0)) =/= 0.U\n val straddlesUpperBound = ((x >> lgMaxSize) ^ (comparand >> lgMaxSize)) === 0.U && (comparand(lgMaxSize-1, 0) & (x(lgMaxSize-1, 0) | lsbMask)) =/= 0.U\n val rangeAligned = !(straddlesLowerBound || straddlesUpperBound)\n val pow2Aligned = (lsbMask & ~mask(lgMaxSize-1, 0)) === 0.U\n Mux(napot, pow2Aligned, rangeAligned)\n }\n\n // returns whether this PMP matches at least one byte of the access\n def hit(x: UInt, lgSize: UInt, lgMaxSize: Int, prev: PMP): Bool =\n Mux(napot, pow2Match(x, lgSize, lgMaxSize), torNotNAPOT && rangeMatch(x, lgSize, lgMaxSize, prev))\n}\n\nclass PMPHomogeneityChecker(pmps: Seq[PMP])(implicit p: Parameters) {\n def apply(addr: UInt, pgLevel: UInt): Bool = {\n pmps.foldLeft((true.B, 0.U.asTypeOf(new PMP))) { case ((h, prev), pmp) =>\n (h && pmp.homogeneous(addr, pgLevel, prev), pmp)\n }._1\n }\n}\n\nclass PMPChecker(lgMaxSize: Int)(implicit val p: Parameters) extends Module\n with HasCoreParameters {\n override def desiredName = s\"PMPChecker_s${lgMaxSize}\"\n val io = IO(new Bundle {\n val prv = Input(UInt(PRV.SZ.W))\n val pmp = Input(Vec(nPMPs, new PMP))\n val addr = Input(UInt(paddrBits.W))\n val size = Input(UInt(log2Ceil(lgMaxSize + 1).W))\n val r = Output(Bool())\n val w = Output(Bool())\n val x = Output(Bool())\n })\n\n val default = if (io.pmp.isEmpty) true.B else io.prv > PRV.S.U\n val pmp0 = WireInit(0.U.asTypeOf(new PMP))\n pmp0.cfg.r := default\n pmp0.cfg.w := default\n pmp0.cfg.x := default\n\n val res = (io.pmp zip (pmp0 +: io.pmp)).reverse.foldLeft(pmp0) { case (prev, (pmp, prevPMP)) =>\n val hit = pmp.hit(io.addr, io.size, lgMaxSize, prevPMP)\n val ignore = default && !pmp.cfg.l\n val aligned = pmp.aligned(io.addr, io.size, lgMaxSize, prevPMP)\n\n for ((name, idx) <- Seq(\"no\", \"TOR\", if (pmpGranularity <= 4) \"NA4\" else \"\", \"NAPOT\").zipWithIndex; if name.nonEmpty)\n property.cover(pmp.cfg.a === idx.U, s\"The cfg access is set to ${name} access \", \"Cover PMP access mode setting\")\n\n property.cover(pmp.cfg.l === 0x1.U, s\"The cfg lock is set to high \", \"Cover PMP lock mode setting\")\n \n // Not including Write and no Read permission as the combination is reserved\n for ((name, idx) <- Seq(\"no\", \"RO\", \"\", \"RW\", \"X\", \"RX\", \"\", \"RWX\").zipWithIndex; if name.nonEmpty)\n property.cover((Cat(pmp.cfg.x, pmp.cfg.w, pmp.cfg.r) === idx.U), s\"The permission is set to ${name} access \", \"Cover PMP access permission setting\")\n\n for ((name, idx) <- Seq(\"\", \"TOR\", if (pmpGranularity <= 4) \"NA4\" else \"\", \"NAPOT\").zipWithIndex; if name.nonEmpty) {\n property.cover(!ignore && hit && aligned && pmp.cfg.a === idx.U, s\"The access matches ${name} mode \", \"Cover PMP access\")\n property.cover(pmp.cfg.l && hit && aligned && pmp.cfg.a === idx.U, s\"The access matches ${name} mode with lock bit high\", \"Cover PMP access with lock bit\")\n }\n\n val cur = WireInit(pmp)\n cur.cfg.r := aligned && (pmp.cfg.r || ignore)\n cur.cfg.w := aligned && (pmp.cfg.w || ignore)\n cur.cfg.x := aligned && (pmp.cfg.x || ignore)\n Mux(hit, cur, prev)\n }\n\n io.r := res.cfg.r\n io.w := res.cfg.w\n io.x := res.cfg.x\n}\n"},"response":{"kind":"string","value":"module PMPChecker_s2(\t// @[PMP.scala:143:7]\n input [1:0] io_prv,\t// @[PMP.scala:146:14]\n input io_pmp_0_cfg_l,\t// @[PMP.scala:146:14]\n input [1:0] io_pmp_0_cfg_a,\t// @[PMP.scala:146:14]\n input io_pmp_0_cfg_x,\t// @[PMP.scala:146:14]\n input io_pmp_0_cfg_w,\t// @[PMP.scala:146:14]\n input io_pmp_0_cfg_r,\t// @[PMP.scala:146:14]\n input [29:0] io_pmp_0_addr,\t// @[PMP.scala:146:14]\n input [31:0] io_pmp_0_mask,\t// @[PMP.scala:146:14]\n input io_pmp_1_cfg_l,\t// @[PMP.scala:146:14]\n input [1:0] io_pmp_1_cfg_a,\t// @[PMP.scala:146:14]\n input io_pmp_1_cfg_x,\t// @[PMP.scala:146:14]\n input io_pmp_1_cfg_w,\t// @[PMP.scala:146:14]\n input io_pmp_1_cfg_r,\t// @[PMP.scala:146:14]\n input [29:0] io_pmp_1_addr,\t// @[PMP.scala:146:14]\n input [31:0] io_pmp_1_mask,\t// @[PMP.scala:146:14]\n input io_pmp_2_cfg_l,\t// @[PMP.scala:146:14]\n input [1:0] io_pmp_2_cfg_a,\t// @[PMP.scala:146:14]\n input io_pmp_2_cfg_x,\t// @[PMP.scala:146:14]\n input io_pmp_2_cfg_w,\t// @[PMP.scala:146:14]\n input io_pmp_2_cfg_r,\t// @[PMP.scala:146:14]\n input [29:0] io_pmp_2_addr,\t// @[PMP.scala:146:14]\n input [31:0] io_pmp_2_mask,\t// @[PMP.scala:146:14]\n input io_pmp_3_cfg_l,\t// @[PMP.scala:146:14]\n input [1:0] io_pmp_3_cfg_a,\t// @[PMP.scala:146:14]\n input io_pmp_3_cfg_x,\t// @[PMP.scala:146:14]\n input io_pmp_3_cfg_w,\t// @[PMP.scala:146:14]\n input io_pmp_3_cfg_r,\t// @[PMP.scala:146:14]\n input [29:0] io_pmp_3_addr,\t// @[PMP.scala:146:14]\n input [31:0] io_pmp_3_mask,\t// @[PMP.scala:146:14]\n input io_pmp_4_cfg_l,\t// @[PMP.scala:146:14]\n input [1:0] io_pmp_4_cfg_a,\t// @[PMP.scala:146:14]\n input io_pmp_4_cfg_x,\t// @[PMP.scala:146:14]\n input io_pmp_4_cfg_w,\t// @[PMP.scala:146:14]\n input io_pmp_4_cfg_r,\t// @[PMP.scala:146:14]\n input [29:0] io_pmp_4_addr,\t// @[PMP.scala:146:14]\n input [31:0] io_pmp_4_mask,\t// @[PMP.scala:146:14]\n input io_pmp_5_cfg_l,\t// @[PMP.scala:146:14]\n input [1:0] io_pmp_5_cfg_a,\t// @[PMP.scala:146:14]\n input io_pmp_5_cfg_x,\t// @[PMP.scala:146:14]\n input io_pmp_5_cfg_w,\t// @[PMP.scala:146:14]\n input io_pmp_5_cfg_r,\t// @[PMP.scala:146:14]\n input [29:0] io_pmp_5_addr,\t// @[PMP.scala:146:14]\n input [31:0] io_pmp_5_mask,\t// @[PMP.scala:146:14]\n input io_pmp_6_cfg_l,\t// @[PMP.scala:146:14]\n input [1:0] io_pmp_6_cfg_a,\t// @[PMP.scala:146:14]\n input io_pmp_6_cfg_x,\t// @[PMP.scala:146:14]\n input io_pmp_6_cfg_w,\t// @[PMP.scala:146:14]\n input io_pmp_6_cfg_r,\t// @[PMP.scala:146:14]\n input [29:0] io_pmp_6_addr,\t// @[PMP.scala:146:14]\n input [31:0] io_pmp_6_mask,\t// @[PMP.scala:146:14]\n input io_pmp_7_cfg_l,\t// @[PMP.scala:146:14]\n input [1:0] io_pmp_7_cfg_a,\t// @[PMP.scala:146:14]\n input io_pmp_7_cfg_x,\t// @[PMP.scala:146:14]\n input io_pmp_7_cfg_w,\t// @[PMP.scala:146:14]\n input io_pmp_7_cfg_r,\t// @[PMP.scala:146:14]\n input [29:0] io_pmp_7_addr,\t// @[PMP.scala:146:14]\n input [31:0] io_pmp_7_mask,\t// @[PMP.scala:146:14]\n input [31:0] io_addr,\t// @[PMP.scala:146:14]\n output io_r,\t// @[PMP.scala:146:14]\n output io_w,\t// @[PMP.scala:146:14]\n output io_x\t// @[PMP.scala:146:14]\n);\n\n wire res_hit = io_pmp_7_cfg_a[1] ? ((io_addr ^ {io_pmp_7_addr, 2'h0}) & ~io_pmp_7_mask) == 32'h0 : io_pmp_7_cfg_a[0] & io_addr >= {io_pmp_6_addr, 2'h0} & io_addr < {io_pmp_7_addr, 2'h0};\t// @[PMP.scala:45:20, :46:26, :60:48, :63:{47,52,54,58}, :77:9, :88:5, :94:48, :132:{8,61}]\n wire res_ignore = io_prv[1] & ~io_pmp_7_cfg_l;\t// @[PMP.scala:156:56, :164:{26,29}]\n wire res_hit_1 = io_pmp_6_cfg_a[1] ? ((io_addr ^ {io_pmp_6_addr, 2'h0}) & ~io_pmp_6_mask) == 32'h0 : io_pmp_6_cfg_a[0] & io_addr >= {io_pmp_5_addr, 2'h0} & io_addr < {io_pmp_6_addr, 2'h0};\t// @[PMP.scala:45:20, :46:26, :60:48, :63:{47,52,54,58}, :77:9, :88:5, :94:48, :132:{8,61}]\n wire res_ignore_1 = io_prv[1] & ~io_pmp_6_cfg_l;\t// @[PMP.scala:156:56, :164:{26,29}]\n wire res_hit_2 = io_pmp_5_cfg_a[1] ? ((io_addr ^ {io_pmp_5_addr, 2'h0}) & ~io_pmp_5_mask) == 32'h0 : io_pmp_5_cfg_a[0] & io_addr >= {io_pmp_4_addr, 2'h0} & io_addr < {io_pmp_5_addr, 2'h0};\t// @[PMP.scala:45:20, :46:26, :60:48, :63:{47,52,54,58}, :77:9, :88:5, :94:48, :132:{8,61}]\n wire res_ignore_2 = io_prv[1] & ~io_pmp_5_cfg_l;\t// @[PMP.scala:156:56, :164:{26,29}]\n wire res_hit_3 = io_pmp_4_cfg_a[1] ? ((io_addr ^ {io_pmp_4_addr, 2'h0}) & ~io_pmp_4_mask) == 32'h0 : io_pmp_4_cfg_a[0] & io_addr >= {io_pmp_3_addr, 2'h0} & io_addr < {io_pmp_4_addr, 2'h0};\t// @[PMP.scala:45:20, :46:26, :60:48, :63:{47,52,54,58}, :77:9, :88:5, :94:48, :132:{8,61}]\n wire res_ignore_3 = io_prv[1] & ~io_pmp_4_cfg_l;\t// @[PMP.scala:156:56, :164:{26,29}]\n wire res_hit_4 = io_pmp_3_cfg_a[1] ? ((io_addr ^ {io_pmp_3_addr, 2'h0}) & ~io_pmp_3_mask) == 32'h0 : io_pmp_3_cfg_a[0] & io_addr >= {io_pmp_2_addr, 2'h0} & io_addr < {io_pmp_3_addr, 2'h0};\t// @[PMP.scala:45:20, :46:26, :60:48, :63:{47,52,54,58}, :77:9, :88:5, :94:48, :132:{8,61}]\n wire res_ignore_4 = io_prv[1] & ~io_pmp_3_cfg_l;\t// @[PMP.scala:156:56, :164:{26,29}]\n wire res_hit_5 = io_pmp_2_cfg_a[1] ? ((io_addr ^ {io_pmp_2_addr, 2'h0}) & ~io_pmp_2_mask) == 32'h0 : io_pmp_2_cfg_a[0] & io_addr >= {io_pmp_1_addr, 2'h0} & io_addr < {io_pmp_2_addr, 2'h0};\t// @[PMP.scala:45:20, :46:26, :60:48, :63:{47,52,54,58}, :77:9, :88:5, :94:48, :132:{8,61}]\n wire res_ignore_5 = io_prv[1] & ~io_pmp_2_cfg_l;\t// @[PMP.scala:156:56, :164:{26,29}]\n wire res_hit_6 = io_pmp_1_cfg_a[1] ? ((io_addr ^ {io_pmp_1_addr, 2'h0}) & ~io_pmp_1_mask) == 32'h0 : io_pmp_1_cfg_a[0] & io_addr >= {io_pmp_0_addr, 2'h0} & io_addr < {io_pmp_1_addr, 2'h0};\t// @[PMP.scala:45:20, :46:26, :60:48, :63:{47,52,54,58}, :77:9, :88:5, :94:48, :132:{8,61}]\n wire res_ignore_6 = io_prv[1] & ~io_pmp_1_cfg_l;\t// @[PMP.scala:156:56, :164:{26,29}]\n wire res_hit_7 = io_pmp_0_cfg_a[1] ? ((io_addr ^ {io_pmp_0_addr, 2'h0}) & ~io_pmp_0_mask) == 32'h0 : io_pmp_0_cfg_a[0] & io_addr < {io_pmp_0_addr, 2'h0};\t// @[PMP.scala:45:20, :46:26, :60:48, :63:{47,52,54,58}, :77:9, :132:{8,61}]\n wire res_ignore_7 = io_prv[1] & ~io_pmp_0_cfg_l;\t// @[PMP.scala:156:56, :164:{26,29}]\n assign io_r = res_hit_7 ? io_pmp_0_cfg_r | res_ignore_7 : res_hit_6 ? io_pmp_1_cfg_r | res_ignore_6 : res_hit_5 ? io_pmp_2_cfg_r | res_ignore_5 : res_hit_4 ? io_pmp_3_cfg_r | res_ignore_4 : res_hit_3 ? io_pmp_4_cfg_r | res_ignore_3 : res_hit_2 ? io_pmp_5_cfg_r | res_ignore_2 : res_hit_1 ? io_pmp_6_cfg_r | res_ignore_1 : res_hit ? io_pmp_7_cfg_r | res_ignore : io_prv[1];\t// @[PMP.scala:132:8, :143:7, :156:56, :164:26, :182:40, :185:8]\n assign io_w = res_hit_7 ? io_pmp_0_cfg_w | res_ignore_7 : res_hit_6 ? io_pmp_1_cfg_w | res_ignore_6 : res_hit_5 ? io_pmp_2_cfg_w | res_ignore_5 : res_hit_4 ? io_pmp_3_cfg_w | res_ignore_4 : res_hit_3 ? io_pmp_4_cfg_w | res_ignore_3 : res_hit_2 ? io_pmp_5_cfg_w | res_ignore_2 : res_hit_1 ? io_pmp_6_cfg_w | res_ignore_1 : res_hit ? io_pmp_7_cfg_w | res_ignore : io_prv[1];\t// @[PMP.scala:132:8, :143:7, :156:56, :164:26, :183:40, :185:8]\n assign io_x = res_hit_7 ? io_pmp_0_cfg_x | res_ignore_7 : res_hit_6 ? io_pmp_1_cfg_x | res_ignore_6 : res_hit_5 ? io_pmp_2_cfg_x | res_ignore_5 : res_hit_4 ? io_pmp_3_cfg_x | res_ignore_4 : res_hit_3 ? io_pmp_4_cfg_x | res_ignore_3 : res_hit_2 ? io_pmp_5_cfg_x | res_ignore_2 : res_hit_1 ? io_pmp_6_cfg_x | res_ignore_1 : res_hit ? io_pmp_7_cfg_x | res_ignore : io_prv[1];\t// @[PMP.scala:132:8, :143:7, :156:56, :164:26, :184:40, :185:8]\nendmodule"}}},{"rowIdx":596,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to the following Chisel files.\nFile HistoryBufferSRAM.scala:\npackage compressacc\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.{Printable, SyncReadMem}\nimport freechips.rocketchip.tile._\nimport org.chipsalliance.cde.config._\nimport freechips.rocketchip.diplomacy._\nimport freechips.rocketchip.rocket.{TLBConfig}\nimport freechips.rocketchip.util.DecoupledHelper\nimport freechips.rocketchip.rocket.constants.MemoryOpConstants\n\n// there is no offset here, because we always just add on at the current\n// pointer\nclass HBSRAMWrite extends Bundle {\n val data = UInt(256.W)\n val valid_bytes = UInt(6.W)\n}\n\nclass HBSRAMReadReq extends Bundle {\n val offset = UInt(48.W)\n}\n\nclass HBSRAMReadResp extends Bundle {\n val data = UInt(256.W)\n}\n\nclass HBSRAMAdvanceReadPtr extends Bundle {\n val advance_bytes = UInt(6.W)\n}\n\n\n/*\n * This block maintains the history of everything that has been\n * loaded from a buffer to compress. It runs at least one cycle\n * AHEAD of the state machine doing compression, so that handling\n * cases where the offset is less than 32B is easy.\n *\n * The write interface is \"valid\" only, it does not have the ability\n * to backpressure.\n */\nclass HistoryBufferSRAM()(implicit p: Parameters) extends Module with MemoryOpConstants {\n\n val io = IO(new Bundle {\n\n val writes_in = Flipped((Valid(new HBSRAMWrite)))\n\n // these valids are technically not necessary, but useful for debugging/\n // tracking purposes\n val read_req_in = Flipped((Valid(new HBSRAMReadReq)))\n val read_resp_out = (Valid(new HBSRAMReadResp))\n\n val read_advance_ptr = Flipped((Valid(new HBSRAMAdvanceReadPtr)))\n })\n\n println(s\"HIST BUF OVERPROV FACTOR: ${p(LZ77HistBufOverProvisionFactor)}\")\n\n val HIST_BUF_WIDTH = 32\n val HIST_BUF_ELEMS_PER_CHUNK = 4 * 512 * p(LZ77HistBufOverProvisionFactor)\n val HIST_SIZE_BYTES = HIST_BUF_WIDTH * HIST_BUF_ELEMS_PER_CHUNK\n val HIST_BUF_INDEX_WIDTH = log2Up(HIST_SIZE_BYTES)\n val BYTE_SIZE = 8\n println(s\"HIST BUF WIDTH: ${HIST_BUF_WIDTH}\")\n println(s\"HIST BUF ELEMS PER CHUNK: ${HIST_BUF_ELEMS_PER_CHUNK}\")\n println(s\"TOTAL HIST BUF SIZE (B): ${HIST_SIZE_BYTES}\")\n val recent_history_vec = Array.fill(HIST_BUF_WIDTH) {SyncReadMem(HIST_BUF_ELEMS_PER_CHUNK, UInt(BYTE_SIZE.W))}\n val read_indexing_vec = Wire(Vec(HIST_BUF_WIDTH, UInt(HIST_BUF_INDEX_WIDTH.W)))\n val read_ports_vec = Wire(Vec(HIST_BUF_WIDTH, UInt(BYTE_SIZE.W)))\n\n for (i <- 0 until HIST_BUF_WIDTH) {\n read_indexing_vec(i) := DontCare\n }\n\n // shift amount to remove memindex part of addr (low # of bits required to count HIST BUF WIDTH items)\n val MEMINDEX_BITS = log2Up(HIST_BUF_WIDTH)\n // mask to get only memindex part of addr\n val MEMINDEX_MASK = (1 << MEMINDEX_BITS) - 1\n\n\n // HANDLE READS:\n\n val read_addr_ptr = RegInit(0.U(HIST_BUF_INDEX_WIDTH.W))\n when (io.read_advance_ptr.valid) {\n // TODO: should an ongoing read account for advance_bytes?\n read_addr_ptr := read_addr_ptr + io.read_advance_ptr.bits.advance_bytes\n }\n\n val read_result_valid = RegNext(io.read_req_in.valid)\n val read_result_addr_ptr = RegNext(read_addr_ptr)\n val read_result_offset = RegNext(io.read_req_in.bits.offset)\n\n io.read_resp_out.valid := read_result_valid\n\n for (elemno <- 0 until HIST_BUF_WIDTH) {\n read_ports_vec(elemno) := recent_history_vec(elemno)(read_indexing_vec(elemno))\n }\n for (elemno <- 0 until HIST_BUF_WIDTH) {\n val read_memaddr = (read_addr_ptr + 32.U - io.read_req_in.bits.offset - elemno.U - 1.U) >> MEMINDEX_BITS\n val read_memno = (read_addr_ptr + 32.U - io.read_req_in.bits.offset - elemno.U - 1.U) & MEMINDEX_MASK.U\n read_indexing_vec(read_memno) := read_memaddr\n when (io.read_req_in.valid) {\n CompressAccelLogger.logInfo(\"issued hist_read(elemno:%d): from memno:%d,memaddr:%d\\n\", elemno.U, read_memno, read_memaddr)\n }\n }\n\n val read_output_vec = Wire(Vec(HIST_BUF_WIDTH, UInt(BYTE_SIZE.W)))\n\n for (elemno <- 0 until HIST_BUF_WIDTH) {\n // get read data\n val read_memaddr = (read_result_addr_ptr + 32.U - read_result_offset - elemno.U - 1.U) >> MEMINDEX_BITS\n val read_memno = (read_result_addr_ptr + 32.U - read_result_offset - elemno.U - 1.U) & MEMINDEX_MASK.U\n\n read_output_vec(elemno) := read_ports_vec(read_memno)\n val print_read_ports_vec = Wire(UInt(BYTE_SIZE.W))\n print_read_ports_vec := read_ports_vec(read_memno)\n when (read_result_valid) {\n CompressAccelLogger.logInfo(\"got hist_read(elemno:%d): from memno:%d,memaddr:%d = val:0x%x\\n\", elemno.U, read_memno, read_memaddr, print_read_ports_vec)\n }\n }\n\n io.read_resp_out.bits.data := Cat(read_output_vec)\n when (read_result_valid) {\n CompressAccelLogger.logInfo(\"read_resp: 0x%x\\n\", io.read_resp_out.bits.data)\n }\n\n // HANDLE WRITES:\n val write_addr_ptr = RegInit(0.U(HIST_BUF_INDEX_WIDTH.W))\n when (io.writes_in.valid) {\n write_addr_ptr := write_addr_ptr + io.writes_in.bits.valid_bytes\n }\n\n val write_indexing_vec = Wire(Vec(HIST_BUF_WIDTH, UInt(HIST_BUF_INDEX_WIDTH.W)))\n val write_ports_vec = Wire(Vec(HIST_BUF_WIDTH, UInt(BYTE_SIZE.W)))\n val write_ports_write_enable = Wire(Vec(HIST_BUF_WIDTH, Bool()))\n\n for (elemno <- 0 until HIST_BUF_WIDTH) {\n write_ports_write_enable(elemno) := false.B\n write_indexing_vec(elemno) := DontCare\n write_ports_vec(elemno) := DontCare\n }\n\n for (elemno <- 0 until HIST_BUF_WIDTH) {\n when (write_ports_write_enable(elemno)) {\n recent_history_vec(elemno)(write_indexing_vec(elemno)) := write_ports_vec(elemno)\n }\n }\n\n val recent_history_vec_next = Wire(Vec(HIST_BUF_WIDTH, UInt(BYTE_SIZE.W)))\n for (elemno <- 0 until HIST_BUF_WIDTH) {\n recent_history_vec_next(elemno) := DontCare\n }\n for (elemno <- 0 until HIST_BUF_WIDTH) {\n recent_history_vec_next(io.writes_in.bits.valid_bytes - elemno.U - 1.U) := io.writes_in.bits.data(((elemno+1) << 3) - 1, elemno << 3)\n }\n for (elemno <- 0 until HIST_BUF_WIDTH) {\n when (io.writes_in.valid && (elemno.U(MEMINDEX_BITS.W) < io.writes_in.bits.valid_bytes)) {\n val full_address = write_addr_ptr + io.writes_in.bits.valid_bytes - elemno.U - 1.U\n val memno = full_address & (MEMINDEX_MASK).U\n val memaddr = full_address >> MEMINDEX_BITS\n write_indexing_vec(memno) := memaddr\n write_ports_vec(memno) := recent_history_vec_next(elemno)\n write_ports_write_enable(memno) := true.B\n val print_recent_history_vec = Wire(UInt(BYTE_SIZE.W))\n //recent_history_vec_next(elemno))\n print_recent_history_vec := recent_history_vec_next(elemno)\n CompressAccelLogger.logInfo(\"do_write:mem(memno:%d,memaddr:%d): from rhvn(elemno:%d) = val:0x%x\\n\", memno, memaddr, elemno.U, print_recent_history_vec)\n }\n }\n}\n"},"response":{"kind":"string","value":"module MEM_14(\t// @[HistoryBufferSRAM.scala:66:67]\n input [11:0] R0_addr,\n input R0_clk,\n output [7:0] R0_data,\n input [11:0] W0_addr,\n input W0_en,\n input W0_clk,\n input [7:0] W0_data\n);\n\n MEM_ext MEM_ext (\t// @[HistoryBufferSRAM.scala:66:67]\n .R0_addr (R0_addr),\n .R0_en (1'h1),\t// @[HistoryBufferSRAM.scala:66:67]\n .R0_clk (R0_clk),\n .R0_data (R0_data),\n .W0_addr (W0_addr),\n .W0_en (W0_en),\n .W0_clk (W0_clk),\n .W0_data (W0_data)\n );\t// @[HistoryBufferSRAM.scala:66:67]\nendmodule"}}},{"rowIdx":597,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to the following Chisel files.\nFile ShiftRegisterPriorityQueue.scala:\npackage compressacc\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.util._\n\n\n// TODO : support enq & deq at the same cycle\nclass PriorityQueueStageIO(keyWidth: Int, value: ValueInfo) extends Bundle {\n val output_prev = KeyValue(keyWidth, value)\n val output_nxt = KeyValue(keyWidth, value)\n val input_prev = Flipped(KeyValue(keyWidth, value))\n val input_nxt = Flipped(KeyValue(keyWidth, value))\n\n val cmd = Flipped(Valid(UInt(1.W)))\n val insert_here = Input(Bool())\n val cur_input_keyval = Flipped(KeyValue(keyWidth, value))\n val cur_output_keyval = KeyValue(keyWidth, value)\n}\n\nclass PriorityQueueStage(keyWidth: Int, value: ValueInfo) extends Module {\n val io = IO(new PriorityQueueStageIO(keyWidth, value))\n\n dontTouch(io)\n\n val CMD_DEQ = 0.U\n val CMD_ENQ = 1.U\n\n val MAX_VALUE = (1 << keyWidth) - 1\n val key_reg = RegInit(MAX_VALUE.U(keyWidth.W))\n val value_reg = Reg(value)\n\n io.output_prev.key := key_reg\n io.output_prev.value := value_reg\n\n io.output_nxt.key := key_reg\n io.output_nxt.value := value_reg\n\n io.cur_output_keyval.key := key_reg\n io.cur_output_keyval.value := value_reg\n\n when (io.cmd.valid) {\n switch (io.cmd.bits) {\n is (CMD_DEQ) {\n key_reg := io.input_nxt.key\n value_reg := io.input_nxt.value\n }\n is (CMD_ENQ) {\n when (io.insert_here) {\n key_reg := io.cur_input_keyval.key\n value_reg := io.cur_input_keyval.value\n } .elsewhen (key_reg >= io.cur_input_keyval.key) {\n key_reg := io.input_prev.key\n value_reg := io.input_prev.value\n } .otherwise {\n // do nothing\n }\n }\n }\n }\n}\n\nobject PriorityQueueStage {\n def apply(keyWidth: Int, v: ValueInfo): PriorityQueueStage = new PriorityQueueStage(keyWidth, v)\n}\n\n// TODO\n// - This design is not scalable as the enqued_keyval is broadcasted to all the stages\n// - Add pipeline registers later\nclass PriorityQueueIO(queSize: Int, keyWidth: Int, value: ValueInfo) extends Bundle {\n val cnt_bits = log2Ceil(queSize+1)\n val counter = Output(UInt(cnt_bits.W))\n\n val enq = Flipped(Decoupled(KeyValue(keyWidth, value)))\n val deq = Decoupled(KeyValue(keyWidth, value))\n}\n\nclass PriorityQueue(queSize: Int, keyWidth: Int, value: ValueInfo) extends Module {\n val keyWidthInternal = keyWidth + 1\n val CMD_DEQ = 0.U\n val CMD_ENQ = 1.U\n\n val io = IO(new PriorityQueueIO(queSize, keyWidthInternal, value))\n\n dontTouch(io)\n\n val MAX_VALUE = ((1 << keyWidthInternal) - 1).U\n\n val cnt_bits = log2Ceil(queSize+1)\n\n // do not consider cases where we are inserting more entries then the queSize\n val counter = RegInit(0.U(cnt_bits.W))\n io.counter := counter\n\n val full = (counter === queSize.U)\n val empty = (counter === 0.U)\n\n io.deq.valid := !empty\n io.enq.ready := !full\n\n when (io.enq.fire) {\n counter := counter + 1.U\n }\n\n when (io.deq.fire) {\n counter := counter - 1.U\n }\n\n val cmd_valid = io.enq.valid || io.deq.ready\n val cmd = Mux(io.enq.valid, CMD_ENQ, CMD_DEQ)\n\n assert(!(io.enq.valid && io.deq.ready))\n\n val stages = Seq.fill(queSize)(Module(new PriorityQueueStage(keyWidthInternal, value)))\n\n for (i <- 0 until (queSize - 1)) {\n stages(i+1).io.input_prev <> stages(i).io.output_nxt\n stages(i).io.input_nxt <> stages(i+1).io.output_prev\n }\n stages(queSize-1).io.input_nxt.key := MAX_VALUE\n// stages(queSize-1).io.input_nxt.value :=\n stages(queSize-1).io.input_nxt.value.symbol := 0.U\n// stages(queSize-1).io.input_nxt.value.child(0) := 0.U\n// stages(queSize-1).io.input_nxt.value.child(1) := 0.U\n stages(0).io.input_prev.key := io.enq.bits.key\n stages(0).io.input_prev.value <> io.enq.bits.value\n\n for (i <- 0 until queSize) {\n stages(i).io.cmd.valid := cmd_valid\n stages(i).io.cmd.bits := cmd\n stages(i).io.cur_input_keyval <> io.enq.bits\n }\n\n\n val is_large_or_equal = WireInit(VecInit(Seq.fill(queSize)(false.B)))\n for (i <- 0 until queSize) {\n is_large_or_equal(i) := (stages(i).io.cur_output_keyval.key >= io.enq.bits.key)\n }\n\n val is_large_or_equal_cat = Wire(UInt(queSize.W))\n is_large_or_equal_cat := Cat(is_large_or_equal.reverse)\n\n val insert_here_idx = PriorityEncoder(is_large_or_equal_cat)\n\n for (i <- 0 until queSize) {\n when (i.U === insert_here_idx) {\n stages(i).io.insert_here := true.B\n } .otherwise {\n stages(i).io.insert_here := false.B\n }\n }\n\n\n io.deq.bits <> stages(0).io.output_prev\n}\n"},"response":{"kind":"string","value":"module PriorityQueueStage_244(\t// @[ShiftRegisterPriorityQueue.scala:21:7]\n input clock,\t// @[ShiftRegisterPriorityQueue.scala:21:7]\n input reset,\t// @[ShiftRegisterPriorityQueue.scala:21:7]\n output [30:0] io_output_prev_key,\t// @[ShiftRegisterPriorityQueue.scala:22:14]\n output [9:0] io_output_prev_value_symbol,\t// @[ShiftRegisterPriorityQueue.scala:22:14]\n output [30:0] io_output_nxt_key,\t// @[ShiftRegisterPriorityQueue.scala:22:14]\n output [9:0] io_output_nxt_value_symbol,\t// @[ShiftRegisterPriorityQueue.scala:22:14]\n input [30:0] io_input_prev_key,\t// @[ShiftRegisterPriorityQueue.scala:22:14]\n input [9:0] io_input_prev_value_symbol,\t// @[ShiftRegisterPriorityQueue.scala:22:14]\n input [30:0] io_input_nxt_key,\t// @[ShiftRegisterPriorityQueue.scala:22:14]\n input [9:0] io_input_nxt_value_symbol,\t// @[ShiftRegisterPriorityQueue.scala:22:14]\n input io_cmd_valid,\t// @[ShiftRegisterPriorityQueue.scala:22:14]\n input io_cmd_bits,\t// @[ShiftRegisterPriorityQueue.scala:22:14]\n input io_insert_here,\t// @[ShiftRegisterPriorityQueue.scala:22:14]\n input [30:0] io_cur_input_keyval_key,\t// @[ShiftRegisterPriorityQueue.scala:22:14]\n input [9:0] io_cur_input_keyval_value_symbol,\t// @[ShiftRegisterPriorityQueue.scala:22:14]\n output [30:0] io_cur_output_keyval_key,\t// @[ShiftRegisterPriorityQueue.scala:22:14]\n output [9:0] io_cur_output_keyval_value_symbol\t// @[ShiftRegisterPriorityQueue.scala:22:14]\n);\n\n wire [30:0] io_input_prev_key_0 = io_input_prev_key;\t// @[ShiftRegisterPriorityQueue.scala:21:7]\n wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol;\t// @[ShiftRegisterPriorityQueue.scala:21:7]\n wire [30:0] io_input_nxt_key_0 = io_input_nxt_key;\t// @[ShiftRegisterPriorityQueue.scala:21:7]\n wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol;\t// @[ShiftRegisterPriorityQueue.scala:21:7]\n wire io_cmd_valid_0 = io_cmd_valid;\t// @[ShiftRegisterPriorityQueue.scala:21:7]\n wire io_cmd_bits_0 = io_cmd_bits;\t// @[ShiftRegisterPriorityQueue.scala:21:7]\n wire io_insert_here_0 = io_insert_here;\t// @[ShiftRegisterPriorityQueue.scala:21:7]\n wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key;\t// @[ShiftRegisterPriorityQueue.scala:21:7]\n wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol;\t// @[ShiftRegisterPriorityQueue.scala:21:7]\n wire [9:0] io_output_prev_value_symbol_0;\t// @[ShiftRegisterPriorityQueue.scala:21:7]\n wire [30:0] io_output_prev_key_0;\t// @[ShiftRegisterPriorityQueue.scala:21:7]\n wire [9:0] io_output_nxt_value_symbol_0;\t// @[ShiftRegisterPriorityQueue.scala:21:7]\n wire [30:0] io_output_nxt_key_0;\t// @[ShiftRegisterPriorityQueue.scala:21:7]\n wire [9:0] io_cur_output_keyval_value_symbol_0;\t// @[ShiftRegisterPriorityQueue.scala:21:7]\n wire [30:0] io_cur_output_keyval_key_0;\t// @[ShiftRegisterPriorityQueue.scala:21:7]\n reg [30:0] key_reg;\t// @[ShiftRegisterPriorityQueue.scala:30:24]\n assign io_output_prev_key_0 = key_reg;\t// @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]\n assign io_output_nxt_key_0 = key_reg;\t// @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]\n assign io_cur_output_keyval_key_0 = key_reg;\t// @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]\n reg [9:0] value_reg_symbol;\t// @[ShiftRegisterPriorityQueue.scala:31:22]\n assign io_output_prev_value_symbol_0 = value_reg_symbol;\t// @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]\n assign io_output_nxt_value_symbol_0 = value_reg_symbol;\t// @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]\n assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol;\t// @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]\n wire _T_2 = key_reg >= io_cur_input_keyval_key_0;\t// @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30]\n always @(posedge clock) begin\t// @[ShiftRegisterPriorityQueue.scala:21:7]\n if (reset)\t// @[ShiftRegisterPriorityQueue.scala:21:7]\n key_reg <= 31'h7FFFFFFF;\t// @[ShiftRegisterPriorityQueue.scala:30:24]\n else if (io_cmd_valid_0) begin\t// @[ShiftRegisterPriorityQueue.scala:21:7]\n if (io_cmd_bits_0) begin\t// @[ShiftRegisterPriorityQueue.scala:21:7]\n if (io_insert_here_0)\t// @[ShiftRegisterPriorityQueue.scala:21:7]\n key_reg <= io_cur_input_keyval_key_0;\t// @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]\n else if (_T_2)\t// @[ShiftRegisterPriorityQueue.scala:52:30]\n key_reg <= io_input_prev_key_0;\t// @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]\n end\n else\t// @[ShiftRegisterPriorityQueue.scala:21:7]\n key_reg <= io_input_nxt_key_0;\t// @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]\n end\n if (io_cmd_valid_0) begin\t// @[ShiftRegisterPriorityQueue.scala:21:7]\n if (io_cmd_bits_0) begin\t// @[ShiftRegisterPriorityQueue.scala:21:7]\n if (io_insert_here_0)\t// @[ShiftRegisterPriorityQueue.scala:21:7]\n value_reg_symbol <= io_cur_input_keyval_value_symbol_0;\t// @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]\n else if (_T_2)\t// @[ShiftRegisterPriorityQueue.scala:52:30]\n value_reg_symbol <= io_input_prev_value_symbol_0;\t// @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]\n end\n else\t// @[ShiftRegisterPriorityQueue.scala:21:7]\n value_reg_symbol <= io_input_nxt_value_symbol_0;\t// @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]\n end\n always @(posedge)\n assign io_output_prev_key = io_output_prev_key_0;\t// @[ShiftRegisterPriorityQueue.scala:21:7]\n assign io_output_prev_value_symbol = io_output_prev_value_symbol_0;\t// @[ShiftRegisterPriorityQueue.scala:21:7]\n assign io_output_nxt_key = io_output_nxt_key_0;\t// @[ShiftRegisterPriorityQueue.scala:21:7]\n assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0;\t// @[ShiftRegisterPriorityQueue.scala:21:7]\n assign io_cur_output_keyval_key = io_cur_output_keyval_key_0;\t// @[ShiftRegisterPriorityQueue.scala:21:7]\n assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0;\t// @[ShiftRegisterPriorityQueue.scala:21:7]\nendmodule"}}},{"rowIdx":598,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to the following Chisel files.\nFile core.scala:\n//******************************************************************************\n// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).\n// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.\n//------------------------------------------------------------------------------\n\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n// RISC-V Processor Core\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n//\n// BOOM has the following (conceptual) stages:\n// if0 - Instruction Fetch 0 (next-pc select)\n// if1 - Instruction Fetch 1 (I$ access)\n// if2 - Instruction Fetch 2 (instruction return)\n// if3 - Instruction Fetch 3 (enqueue to fetch buffer)\n// if4 - Instruction Fetch 4 (redirect from bpd)\n// dec - Decode\n// ren - Rename1\n// dis - Rename2/Dispatch\n// iss - Issue\n// rrd - Register Read\n// exe - Execute\n// mem - Memory\n// sxt - Sign-extend\n// wb - Writeback\n// com - Commit\n\npackage boom.v3.exu\n\nimport java.nio.file.{Paths}\n\nimport chisel3._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config.Parameters\nimport freechips.rocketchip.rocket.Instructions._\nimport freechips.rocketchip.tile.{TraceBundle}\nimport freechips.rocketchip.rocket.{Causes, PRV, TracedInstruction}\nimport freechips.rocketchip.util.{Str, UIntIsOneOf, CoreMonitorBundle}\nimport freechips.rocketchip.devices.tilelink.{PLICConsts, CLINTConsts}\n\nimport boom.v3.common._\nimport boom.v3.ifu.{GlobalHistory, HasBoomFrontendParameters}\nimport boom.v3.exu.FUConstants._\nimport boom.v3.util._\n\n/**\n * Top level core object that connects the Frontend to the rest of the pipeline.\n */\nclass BoomCore()(implicit p: Parameters) extends BoomModule\n with HasBoomFrontendParameters // TODO: Don't add this trait\n{\n val io = IO(new Bundle {\n val hartid = Input(UInt(hartIdLen.W))\n val interrupts = Input(new freechips.rocketchip.rocket.CoreInterrupts(false))\n val ifu = new boom.v3.ifu.BoomFrontendIO\n val ptw = Flipped(new freechips.rocketchip.rocket.DatapathPTWIO())\n val rocc = Flipped(new freechips.rocketchip.tile.RoCCCoreIO())\n val lsu = Flipped(new boom.v3.lsu.LSUCoreIO)\n val ptw_tlb = new freechips.rocketchip.rocket.TLBPTWIO()\n val trace = Output(new TraceBundle)\n val fcsr_rm = UInt(freechips.rocketchip.tile.FPConstants.RM_SZ.W)\n })\n\n io.ptw_tlb := DontCare\n io.ptw := DontCare\n io.ifu := DontCare\n\n //**********************************\n // construct all of the modules\n\n // Only holds integer-registerfile execution units.\n val exe_units = new boom.v3.exu.ExecutionUnits(fpu=false)\n val jmp_unit_idx = exe_units.jmp_unit_idx\n val jmp_unit = exe_units(jmp_unit_idx)\n\n // Meanwhile, the FP pipeline holds the FP issue window, FP regfile, and FP arithmetic units.\n var fp_pipeline: FpPipeline = null\n if (usingFPU) fp_pipeline = Module(new FpPipeline)\n\n // ********************************************************\n // Clear fp_pipeline before use\n if (usingFPU) {\n fp_pipeline.io.ll_wports := DontCare\n fp_pipeline.io.wb_valids := DontCare\n fp_pipeline.io.wb_pdsts := DontCare\n }\n\n val numIrfWritePorts = exe_units.numIrfWritePorts + memWidth\n val numLlIrfWritePorts = exe_units.numLlIrfWritePorts\n val numIrfReadPorts = exe_units.numIrfReadPorts\n\n val numFastWakeupPorts = exe_units.count(_.bypassable)\n val numAlwaysBypassable = exe_units.count(_.alwaysBypassable)\n\n val numIntIssueWakeupPorts = numIrfWritePorts + numFastWakeupPorts - numAlwaysBypassable // + memWidth for ll_wb\n val numIntRenameWakeupPorts = numIntIssueWakeupPorts\n val numFpWakeupPorts = if (usingFPU) fp_pipeline.io.wakeups.length else 0\n\n val decode_units = for (w <- 0 until decodeWidth) yield { val d = Module(new DecodeUnit); d }\n val dec_brmask_logic = Module(new BranchMaskGenerationLogic(coreWidth))\n val rename_stage = Module(new RenameStage(coreWidth, numIntPhysRegs, numIntRenameWakeupPorts, false))\n val fp_rename_stage = if (usingFPU) Module(new RenameStage(coreWidth, numFpPhysRegs, numFpWakeupPorts, true)) else null\n val pred_rename_stage = Module(new PredRenameStage(coreWidth, ftqSz, 1))\n val rename_stages = if (usingFPU) Seq(rename_stage, fp_rename_stage, pred_rename_stage) else Seq(rename_stage, pred_rename_stage)\n\n val mem_iss_unit = Module(new IssueUnitCollapsing(memIssueParam, numIntIssueWakeupPorts))\n mem_iss_unit.suggestName(\"mem_issue_unit\")\n val int_iss_unit = Module(new IssueUnitCollapsing(intIssueParam, numIntIssueWakeupPorts))\n int_iss_unit.suggestName(\"int_issue_unit\")\n\n val issue_units = Seq(mem_iss_unit, int_iss_unit)\n val dispatcher = Module(new BasicDispatcher)\n\n val iregfile = Module(new RegisterFileSynthesizable(\n numIntPhysRegs,\n numIrfReadPorts,\n numIrfWritePorts,\n xLen,\n Seq.fill(memWidth) {true} ++ exe_units.bypassable_write_port_mask)) // bypassable ll_wb\n val pregfile = Module(new RegisterFileSynthesizable(\n ftqSz,\n exe_units.numIrfReaders,\n 1,\n 1,\n Seq(true))) // The jmp unit is always bypassable\n pregfile.io := DontCare // Only use the IO if enableSFBOpt\n\n // wb arbiter for the 0th ll writeback\n // TODO: should this be a multi-arb?\n val ll_wbarb = Module(new Arbiter(new ExeUnitResp(xLen), 1 +\n (if (usingFPU) 1 else 0) +\n (if (usingRoCC) 1 else 0)))\n val iregister_read = Module(new RegisterRead(\n issue_units.map(_.issueWidth).sum,\n exe_units.withFilter(_.readsIrf).map(_.supportedFuncUnits).toSeq,\n numIrfReadPorts,\n exe_units.withFilter(_.readsIrf).map(x => 2).toSeq,\n exe_units.numTotalBypassPorts,\n jmp_unit.numBypassStages,\n xLen))\n val rob = Module(new Rob(\n numIrfWritePorts + numFpWakeupPorts, // +memWidth for ll writebacks\n numFpWakeupPorts))\n // Used to wakeup registers in rename and issue. ROB needs to listen to something else.\n val int_iss_wakeups = Wire(Vec(numIntIssueWakeupPorts, Valid(new ExeUnitResp(xLen))))\n val int_ren_wakeups = Wire(Vec(numIntRenameWakeupPorts, Valid(new ExeUnitResp(xLen))))\n val pred_wakeup = Wire(Valid(new ExeUnitResp(1)))\n\n require (exe_units.length == issue_units.map(_.issueWidth).sum)\n\n //***********************************\n // Pipeline State Registers and Wires\n\n // Decode/Rename1 Stage\n val dec_valids = Wire(Vec(coreWidth, Bool())) // are the decoded instruction valid? It may be held up though.\n val dec_uops = Wire(Vec(coreWidth, new MicroOp()))\n val dec_fire = Wire(Vec(coreWidth, Bool())) // can the instruction fire beyond decode?\n // (can still be stopped in ren or dis)\n val dec_ready = Wire(Bool())\n val dec_xcpts = Wire(Vec(coreWidth, Bool()))\n val ren_stalls = Wire(Vec(coreWidth, Bool()))\n\n // Rename2/Dispatch stage\n val dis_valids = Wire(Vec(coreWidth, Bool()))\n val dis_uops = Wire(Vec(coreWidth, new MicroOp))\n val dis_fire = Wire(Vec(coreWidth, Bool()))\n val dis_ready = Wire(Bool())\n\n // Issue Stage/Register Read\n val iss_valids = Wire(Vec(exe_units.numIrfReaders, Bool()))\n val iss_uops = Wire(Vec(exe_units.numIrfReaders, new MicroOp()))\n val bypasses = Wire(Vec(exe_units.numTotalBypassPorts, Valid(new ExeUnitResp(xLen))))\n val pred_bypasses = Wire(Vec(jmp_unit.numBypassStages, Valid(new ExeUnitResp(1))))\n require(jmp_unit.bypassable)\n\n // --------------------------------------\n // Dealing with branch resolutions\n\n // The individual branch resolutions from each ALU\n val brinfos = Reg(Vec(coreWidth, new BrResolutionInfo()))\n\n // \"Merged\" branch update info from all ALUs\n // brmask contains masks for rapidly clearing mispredicted instructions\n // brindices contains indices to reset pointers for allocated structures\n // brindices is delayed a cycle\n val brupdate = Wire(new BrUpdateInfo)\n val b1 = Wire(new BrUpdateMasks)\n val b2 = Reg(new BrResolutionInfo)\n\n brupdate.b1 := b1\n brupdate.b2 := b2\n\n for ((b, a) <- brinfos zip exe_units.alu_units) {\n b := a.io.brinfo\n b.valid := a.io.brinfo.valid && !rob.io.flush.valid\n }\n b1.resolve_mask := brinfos.map(x => x.valid << x.uop.br_tag).reduce(_|_)\n b1.mispredict_mask := brinfos.map(x => (x.valid && x.mispredict) << x.uop.br_tag).reduce(_|_)\n\n // Find the oldest mispredict and use it to update indices\n var mispredict_val = false.B\n var oldest_mispredict = brinfos(0)\n for (b <- brinfos) {\n val use_this_mispredict = !mispredict_val ||\n b.valid && b.mispredict && IsOlder(b.uop.rob_idx, oldest_mispredict.uop.rob_idx, rob.io.rob_head_idx)\n\n mispredict_val = mispredict_val || (b.valid && b.mispredict)\n oldest_mispredict = Mux(use_this_mispredict, b, oldest_mispredict)\n }\n\n b2.mispredict := mispredict_val\n b2.cfi_type := oldest_mispredict.cfi_type\n b2.taken := oldest_mispredict.taken\n b2.pc_sel := oldest_mispredict.pc_sel\n b2.uop := UpdateBrMask(brupdate, oldest_mispredict.uop)\n b2.jalr_target := RegNext(jmp_unit.io.brinfo.jalr_target)\n b2.target_offset := oldest_mispredict.target_offset\n\n val oldest_mispredict_ftq_idx = oldest_mispredict.uop.ftq_idx\n\n\n assert (!((brupdate.b1.mispredict_mask =/= 0.U || brupdate.b2.mispredict)\n && rob.io.commit.rollback), \"Can't have a mispredict during rollback.\")\n\n io.ifu.brupdate := brupdate\n\n for (eu <- exe_units) {\n eu.io.brupdate := brupdate\n }\n\n if (usingFPU) {\n fp_pipeline.io.brupdate := brupdate\n }\n\n // Load/Store Unit & ExeUnits\n val mem_units = exe_units.memory_units\n val mem_resps = mem_units.map(_.io.ll_iresp)\n for (i <- 0 until memWidth) {\n mem_units(i).io.lsu_io <> io.lsu.exe(i)\n }\n\n //-------------------------------------------------------------\n // Uarch Hardware Performance Events (HPEs)\n\n val perfEvents = new freechips.rocketchip.rocket.EventSets(Seq(\n new freechips.rocketchip.rocket.EventSet((mask, hits) => (mask & hits).orR, Seq(\n (\"exception\", () => rob.io.com_xcpt.valid),\n (\"nop\", () => false.B),\n (\"nop\", () => false.B),\n (\"nop\", () => false.B))),\n\n new freechips.rocketchip.rocket.EventSet((mask, hits) => (mask & hits).orR, Seq(\n// (\"I$ blocked\", () => icache_blocked),\n (\"nop\", () => false.B),\n (\"branch misprediction\", () => b2.mispredict),\n (\"control-flow target misprediction\", () => b2.mispredict &&\n b2.cfi_type === CFI_JALR),\n (\"flush\", () => rob.io.flush.valid),\n (\"branch resolved\", () => b2.valid)\n )),\n\n new freechips.rocketchip.rocket.EventSet((mask, hits) => (mask & hits).orR, Seq(\n (\"I$ miss\", () => io.ifu.perf.acquire),\n (\"D$ miss\", () => io.lsu.perf.acquire),\n (\"D$ release\", () => io.lsu.perf.release),\n (\"ITLB miss\", () => io.ifu.perf.tlbMiss),\n (\"DTLB miss\", () => io.lsu.perf.tlbMiss),\n (\"L2 TLB miss\", () => io.ptw.perf.l2miss)))))\n val csr = Module(new freechips.rocketchip.rocket.CSRFile(perfEvents, boomParams.customCSRs.decls))\n csr.io.inst foreach { c => c := DontCare }\n csr.io.rocc_interrupt := io.rocc.interrupt\n csr.io.mhtinst_read_pseudo := false.B\n\n val custom_csrs = Wire(new BoomCustomCSRs)\n custom_csrs.csrs.foreach { c => c.stall := false.B; c.set := false.B; c.sdata := DontCare }\n\n (custom_csrs.csrs zip csr.io.customCSRs).map { case (lhs, rhs) => lhs <> rhs }\n\n //val icache_blocked = !(io.ifu.fetchpacket.valid || RegNext(io.ifu.fetchpacket.valid))\n val icache_blocked = false.B\n csr.io.counters foreach { c => c.inc := RegNext(perfEvents.evaluate(c.eventSel)) }\n\n //****************************************\n // Time Stamp Counter & Retired Instruction Counter\n // (only used for printf and vcd dumps - the actual counters are in the CSRFile)\n val debug_tsc_reg = RegInit(0.U(xLen.W))\n val debug_irt_reg = RegInit(0.U(xLen.W))\n val debug_brs = Reg(Vec(4, UInt(xLen.W)))\n val debug_jals = Reg(Vec(4, UInt(xLen.W)))\n val debug_jalrs = Reg(Vec(4, UInt(xLen.W)))\n\n for (j <- 0 until 4) {\n debug_brs(j) := debug_brs(j) + PopCount(VecInit((0 until coreWidth) map {i =>\n rob.io.commit.arch_valids(i) &&\n (rob.io.commit.uops(i).debug_fsrc === j.U) &&\n rob.io.commit.uops(i).is_br\n }))\n debug_jals(j) := debug_jals(j) + PopCount(VecInit((0 until coreWidth) map {i =>\n rob.io.commit.arch_valids(i) &&\n (rob.io.commit.uops(i).debug_fsrc === j.U) &&\n rob.io.commit.uops(i).is_jal\n }))\n debug_jalrs(j) := debug_jalrs(j) + PopCount(VecInit((0 until coreWidth) map {i =>\n rob.io.commit.arch_valids(i) &&\n (rob.io.commit.uops(i).debug_fsrc === j.U) &&\n rob.io.commit.uops(i).is_jalr\n }))\n }\n\n dontTouch(debug_brs)\n dontTouch(debug_jals)\n dontTouch(debug_jalrs)\n\n debug_tsc_reg := debug_tsc_reg + 1.U\n debug_irt_reg := debug_irt_reg + PopCount(rob.io.commit.arch_valids.asUInt)\n dontTouch(debug_tsc_reg)\n dontTouch(debug_irt_reg)\n\n //****************************************\n // Print-out information about the machine\n\n val issStr =\n if (enableAgePriorityIssue) \" (Age-based Priority)\"\n else \" (Unordered Priority)\"\n\n // val btbStr =\n // if (enableBTB) (\"\" + boomParams.btb.nSets * boomParams.btb.nWays + \" entries (\" + boomParams.btb.nSets + \" x \" + boomParams.btb.nWays + \" ways)\")\n // else 0\n val btbStr = \"\"\n\n val fpPipelineStr =\n if (usingFPU) fp_pipeline.toString\n else \"\"\n\n override def toString: String =\n (BoomCoreStringPrefix(\"====Overall Core Params====\") + \"\\n\"\n + exe_units.toString + \"\\n\"\n + fpPipelineStr + \"\\n\"\n + rob.toString + \"\\n\"\n + BoomCoreStringPrefix(\n \"===Other Core Params===\",\n \"Fetch Width : \" + fetchWidth,\n \"Decode Width : \" + coreWidth,\n \"Issue Width : \" + issueParams.map(_.issueWidth).sum,\n \"ROB Size : \" + numRobEntries,\n \"Issue Window Size : \" + issueParams.map(_.numEntries) + issStr,\n \"Load/Store Unit Size : \" + numLdqEntries + \"/\" + numStqEntries,\n \"Num Int Phys Registers: \" + numIntPhysRegs,\n \"Num FP Phys Registers: \" + numFpPhysRegs,\n \"Max Branch Count : \" + maxBrCount)\n + iregfile.toString + \"\\n\"\n + BoomCoreStringPrefix(\n \"Num Slow Wakeup Ports : \" + numIrfWritePorts,\n \"Num Fast Wakeup Ports : \" + exe_units.count(_.bypassable),\n \"Num Bypass Ports : \" + exe_units.numTotalBypassPorts) + \"\\n\"\n + BoomCoreStringPrefix(\n \"DCache Ways : \" + dcacheParams.nWays,\n \"DCache Sets : \" + dcacheParams.nSets,\n \"DCache nMSHRs : \" + dcacheParams.nMSHRs,\n \"ICache Ways : \" + icacheParams.nWays,\n \"ICache Sets : \" + icacheParams.nSets,\n \"D-TLB Ways : \" + dcacheParams.nTLBWays,\n \"I-TLB Ways : \" + icacheParams.nTLBWays,\n \"Paddr Bits : \" + paddrBits,\n \"Vaddr Bits : \" + vaddrBits) + \"\\n\"\n + BoomCoreStringPrefix(\n \"Using FPU Unit? : \" + usingFPU.toString,\n \"Using FDivSqrt? : \" + usingFDivSqrt.toString,\n \"Using VM? : \" + usingVM.toString) + \"\\n\")\n\n //-------------------------------------------------------------\n //-------------------------------------------------------------\n // **** Fetch Stage/Frontend ****\n //-------------------------------------------------------------\n //-------------------------------------------------------------\n io.ifu.redirect_val := false.B\n io.ifu.redirect_flush := false.B\n\n // Breakpoint info\n io.ifu.status := csr.io.status\n io.ifu.bp := csr.io.bp\n io.ifu.mcontext := csr.io.mcontext\n io.ifu.scontext := csr.io.scontext\n\n io.ifu.flush_icache := (0 until coreWidth).map { i =>\n (rob.io.commit.arch_valids(i) && rob.io.commit.uops(i).is_fencei) ||\n (RegNext(dec_valids(i) && dec_uops(i).is_jalr && csr.io.status.debug))\n }.reduce(_||_)\n\n // TODO FIX THIS HACK\n // The below code works because of two quirks with the flush mechanism\n // 1 ) All flush_on_commit instructions are also is_unique,\n // In the future, this constraint will be relaxed.\n // 2 ) We send out flush signals one cycle after the commit signal. We need to\n // mux between one/two cycle delay for the following cases:\n // ERETs are reported to the CSR two cycles before we send the flush\n // Exceptions are reported to the CSR on the cycle we send the flush\n // This discrepency should be resolved elsewhere.\n when (RegNext(rob.io.flush.valid)) {\n io.ifu.redirect_val := true.B\n io.ifu.redirect_flush := true.B\n val flush_typ = RegNext(rob.io.flush.bits.flush_typ)\n // Clear the global history when we flush the ROB (exceptions, AMOs, unique instructions, etc.)\n val new_ghist = WireInit((0.U).asTypeOf(new GlobalHistory))\n new_ghist.current_saw_branch_not_taken := true.B\n new_ghist.ras_idx := io.ifu.get_pc(0).entry.ras_idx\n io.ifu.redirect_ghist := new_ghist\n when (FlushTypes.useCsrEvec(flush_typ)) {\n io.ifu.redirect_pc := Mux(flush_typ === FlushTypes.eret,\n RegNext(RegNext(csr.io.evec)),\n csr.io.evec)\n } .otherwise {\n val flush_pc = (AlignPCToBoundary(io.ifu.get_pc(0).pc, icBlockBytes)\n + RegNext(rob.io.flush.bits.pc_lob)\n - Mux(RegNext(rob.io.flush.bits.edge_inst), 2.U, 0.U))\n val flush_pc_next = flush_pc + Mux(RegNext(rob.io.flush.bits.is_rvc), 2.U, 4.U)\n io.ifu.redirect_pc := Mux(FlushTypes.useSamePC(flush_typ),\n flush_pc, flush_pc_next)\n\n }\n io.ifu.redirect_ftq_idx := RegNext(rob.io.flush.bits.ftq_idx)\n } .elsewhen (brupdate.b2.mispredict && !RegNext(rob.io.flush.valid)) {\n val block_pc = AlignPCToBoundary(io.ifu.get_pc(1).pc, icBlockBytes)\n val uop_maybe_pc = block_pc | brupdate.b2.uop.pc_lob\n val npc = uop_maybe_pc + Mux(brupdate.b2.uop.is_rvc || brupdate.b2.uop.edge_inst, 2.U, 4.U)\n val jal_br_target = Wire(UInt(vaddrBitsExtended.W))\n jal_br_target := (uop_maybe_pc.asSInt + brupdate.b2.target_offset +\n (Fill(vaddrBitsExtended-1, brupdate.b2.uop.edge_inst) << 1).asSInt).asUInt\n val bj_addr = Mux(brupdate.b2.cfi_type === CFI_JALR, brupdate.b2.jalr_target, jal_br_target)\n val mispredict_target = Mux(brupdate.b2.pc_sel === PC_PLUS4, npc, bj_addr)\n io.ifu.redirect_val := true.B\n io.ifu.redirect_pc := mispredict_target\n io.ifu.redirect_flush := true.B\n io.ifu.redirect_ftq_idx := brupdate.b2.uop.ftq_idx\n val use_same_ghist = (brupdate.b2.cfi_type === CFI_BR &&\n !brupdate.b2.taken &&\n bankAlign(block_pc) === bankAlign(npc))\n val ftq_entry = io.ifu.get_pc(1).entry\n val cfi_idx = (brupdate.b2.uop.pc_lob ^\n Mux(ftq_entry.start_bank === 1.U, 1.U << log2Ceil(bankBytes), 0.U))(log2Ceil(fetchWidth), 1)\n val ftq_ghist = io.ifu.get_pc(1).ghist\n val next_ghist = ftq_ghist.update(\n ftq_entry.br_mask.asUInt,\n brupdate.b2.taken,\n brupdate.b2.cfi_type === CFI_BR,\n cfi_idx,\n true.B,\n io.ifu.get_pc(1).pc,\n ftq_entry.cfi_is_call && ftq_entry.cfi_idx.bits === cfi_idx,\n ftq_entry.cfi_is_ret && ftq_entry.cfi_idx.bits === cfi_idx)\n\n\n io.ifu.redirect_ghist := Mux(\n use_same_ghist,\n ftq_ghist,\n next_ghist)\n io.ifu.redirect_ghist.current_saw_branch_not_taken := use_same_ghist\n } .elsewhen (rob.io.flush_frontend || brupdate.b1.mispredict_mask =/= 0.U) {\n io.ifu.redirect_flush := true.B\n }\n\n // Tell the FTQ it can deallocate entries by passing youngest ftq_idx.\n val youngest_com_idx = (coreWidth-1).U - PriorityEncoder(rob.io.commit.valids.reverse)\n io.ifu.commit.valid := rob.io.commit.valids.reduce(_|_) || rob.io.com_xcpt.valid\n io.ifu.commit.bits := Mux(rob.io.com_xcpt.valid,\n rob.io.com_xcpt.bits.ftq_idx,\n rob.io.commit.uops(youngest_com_idx).ftq_idx)\n\n assert(!(rob.io.commit.valids.reduce(_|_) && rob.io.com_xcpt.valid),\n \"ROB can't commit and except in same cycle!\")\n\n for (i <- 0 until memWidth) {\n when (RegNext(io.lsu.exe(i).req.bits.sfence.valid)) {\n io.ifu.sfence := RegNext(io.lsu.exe(i).req.bits.sfence)\n }\n }\n\n //-------------------------------------------------------------\n //-------------------------------------------------------------\n // **** Branch Prediction ****\n //-------------------------------------------------------------\n //-------------------------------------------------------------\n\n //-------------------------------------------------------------\n //-------------------------------------------------------------\n // **** Decode Stage ****\n //-------------------------------------------------------------\n //-------------------------------------------------------------\n\n // track mask of finished instructions in the bundle\n // use this to mask out insts coming from FetchBuffer that have been finished\n // for example, back pressure may cause us to only issue some instructions from FetchBuffer\n // but on the next cycle, we only want to retry a subset\n val dec_finished_mask = RegInit(0.U(coreWidth.W))\n\n //-------------------------------------------------------------\n // Pull out instructions and send to the Decoders\n\n io.ifu.fetchpacket.ready := dec_ready\n val dec_fbundle = io.ifu.fetchpacket.bits\n\n //-------------------------------------------------------------\n // Decoders\n\n for (w <- 0 until coreWidth) {\n dec_valids(w) := io.ifu.fetchpacket.valid && dec_fbundle.uops(w).valid &&\n !dec_finished_mask(w)\n decode_units(w).io.enq.uop := dec_fbundle.uops(w).bits\n decode_units(w).io.status := csr.io.status\n decode_units(w).io.csr_decode <> csr.io.decode(w)\n decode_units(w).io.interrupt := csr.io.interrupt\n decode_units(w).io.interrupt_cause := csr.io.interrupt_cause\n\n dec_uops(w) := decode_units(w).io.deq.uop\n }\n\n //-------------------------------------------------------------\n // FTQ GetPC Port Arbitration\n\n val jmp_pc_req = Wire(Decoupled(UInt(log2Ceil(ftqSz).W)))\n val xcpt_pc_req = Wire(Decoupled(UInt(log2Ceil(ftqSz).W)))\n val flush_pc_req = Wire(Decoupled(UInt(log2Ceil(ftqSz).W)))\n\n val ftq_arb = Module(new Arbiter(UInt(log2Ceil(ftqSz).W), 3))\n\n // Order by the oldest. Flushes come from the oldest instructions in pipe\n // Decoding exceptions come from youngest\n ftq_arb.io.in(0) <> flush_pc_req\n ftq_arb.io.in(1) <> jmp_pc_req\n ftq_arb.io.in(2) <> xcpt_pc_req\n\n // Hookup FTQ\n io.ifu.get_pc(0).ftq_idx := ftq_arb.io.out.bits\n ftq_arb.io.out.ready := true.B\n\n // Branch Unit Requests (for JALs) (Should delay issue of JALs if this not ready)\n jmp_pc_req.valid := RegNext(iss_valids(jmp_unit_idx) && iss_uops(jmp_unit_idx).fu_code === FU_JMP)\n jmp_pc_req.bits := RegNext(iss_uops(jmp_unit_idx).ftq_idx)\n\n jmp_unit.io.get_ftq_pc := DontCare\n jmp_unit.io.get_ftq_pc.pc := io.ifu.get_pc(0).pc\n jmp_unit.io.get_ftq_pc.entry := io.ifu.get_pc(0).entry\n jmp_unit.io.get_ftq_pc.next_val := io.ifu.get_pc(0).next_val\n jmp_unit.io.get_ftq_pc.next_pc := io.ifu.get_pc(0).next_pc\n\n\n // Frontend Exception Requests\n val xcpt_idx = PriorityEncoder(dec_xcpts)\n xcpt_pc_req.valid := dec_xcpts.reduce(_||_)\n xcpt_pc_req.bits := dec_uops(xcpt_idx).ftq_idx\n //rob.io.xcpt_fetch_pc := RegEnable(io.ifu.get_pc.fetch_pc, dis_ready)\n rob.io.xcpt_fetch_pc := io.ifu.get_pc(0).pc\n\n flush_pc_req.valid := rob.io.flush.valid\n flush_pc_req.bits := rob.io.flush.bits.ftq_idx\n\n // Mispredict requests (to get the correct target)\n io.ifu.get_pc(1).ftq_idx := oldest_mispredict_ftq_idx\n\n\n //-------------------------------------------------------------\n // Decode/Rename1 pipeline logic\n\n dec_xcpts := dec_uops zip dec_valids map {case (u,v) => u.exception && v}\n val dec_xcpt_stall = dec_xcpts.reduce(_||_) && !xcpt_pc_req.ready\n // stall fetch/dcode because we ran out of branch tags\n val branch_mask_full = Wire(Vec(coreWidth, Bool()))\n\n val dec_hazards = (0 until coreWidth).map(w =>\n dec_valids(w) &&\n ( !dis_ready\n || rob.io.commit.rollback\n || dec_xcpt_stall\n || branch_mask_full(w)\n || brupdate.b1.mispredict_mask =/= 0.U\n || brupdate.b2.mispredict\n || io.ifu.redirect_flush))\n\n val dec_stalls = dec_hazards.scanLeft(false.B) ((s,h) => s || h).takeRight(coreWidth)\n dec_fire := (0 until coreWidth).map(w => dec_valids(w) && !dec_stalls(w))\n\n // all decoders are empty and ready for new instructions\n dec_ready := dec_fire.last\n\n when (dec_ready || io.ifu.redirect_flush) {\n dec_finished_mask := 0.U\n } .otherwise {\n dec_finished_mask := dec_fire.asUInt | dec_finished_mask\n }\n\n //-------------------------------------------------------------\n // Branch Mask Logic\n\n dec_brmask_logic.io.brupdate := brupdate\n dec_brmask_logic.io.flush_pipeline := RegNext(rob.io.flush.valid)\n\n for (w <- 0 until coreWidth) {\n dec_brmask_logic.io.is_branch(w) := !dec_finished_mask(w) && dec_uops(w).allocate_brtag\n dec_brmask_logic.io.will_fire(w) := dec_fire(w) &&\n dec_uops(w).allocate_brtag // ren, dis can back pressure us\n dec_uops(w).br_tag := dec_brmask_logic.io.br_tag(w)\n dec_uops(w).br_mask := dec_brmask_logic.io.br_mask(w)\n }\n\n branch_mask_full := dec_brmask_logic.io.is_full\n\n //-------------------------------------------------------------\n //-------------------------------------------------------------\n // **** Register Rename Stage ****\n //-------------------------------------------------------------\n //-------------------------------------------------------------\n\n // Inputs\n for (rename <- rename_stages) {\n rename.io.kill := io.ifu.redirect_flush\n rename.io.brupdate := brupdate\n\n rename.io.debug_rob_empty := rob.io.empty\n\n rename.io.dec_fire := dec_fire\n rename.io.dec_uops := dec_uops\n\n rename.io.dis_fire := dis_fire\n rename.io.dis_ready := dis_ready\n\n rename.io.com_valids := rob.io.commit.valids\n rename.io.com_uops := rob.io.commit.uops\n rename.io.rbk_valids := rob.io.commit.rbk_valids\n rename.io.rollback := rob.io.commit.rollback\n }\n\n\n // Outputs\n dis_uops := rename_stage.io.ren2_uops\n dis_valids := rename_stage.io.ren2_mask\n ren_stalls := rename_stage.io.ren_stalls\n\n\n /**\n * TODO This is a bit nasty, but it's currently necessary to\n * split the INT/FP rename pipelines into separate instantiations.\n * Won't have to do this anymore with a properly decoupled FP pipeline.\n */\n for (w <- 0 until coreWidth) {\n val i_uop = rename_stage.io.ren2_uops(w)\n val f_uop = if (usingFPU) fp_rename_stage.io.ren2_uops(w) else NullMicroOp\n val p_uop = if (enableSFBOpt) pred_rename_stage.io.ren2_uops(w) else NullMicroOp\n val f_stall = if (usingFPU) fp_rename_stage.io.ren_stalls(w) else false.B\n val p_stall = if (enableSFBOpt) pred_rename_stage.io.ren_stalls(w) else false.B\n\n // lrs1 can \"pass through\" to prs1. Used solely to index the csr file.\n dis_uops(w).prs1 := Mux(dis_uops(w).lrs1_rtype === RT_FLT, f_uop.prs1,\n Mux(dis_uops(w).lrs1_rtype === RT_FIX, i_uop.prs1, dis_uops(w).lrs1))\n dis_uops(w).prs2 := Mux(dis_uops(w).lrs2_rtype === RT_FLT, f_uop.prs2, i_uop.prs2)\n dis_uops(w).prs3 := f_uop.prs3\n dis_uops(w).ppred := p_uop.ppred\n dis_uops(w).pdst := Mux(dis_uops(w).dst_rtype === RT_FLT, f_uop.pdst,\n Mux(dis_uops(w).dst_rtype === RT_FIX, i_uop.pdst,\n p_uop.pdst))\n dis_uops(w).stale_pdst := Mux(dis_uops(w).dst_rtype === RT_FLT, f_uop.stale_pdst, i_uop.stale_pdst)\n\n dis_uops(w).prs1_busy := i_uop.prs1_busy && (dis_uops(w).lrs1_rtype === RT_FIX) ||\n f_uop.prs1_busy && (dis_uops(w).lrs1_rtype === RT_FLT)\n dis_uops(w).prs2_busy := i_uop.prs2_busy && (dis_uops(w).lrs2_rtype === RT_FIX) ||\n f_uop.prs2_busy && (dis_uops(w).lrs2_rtype === RT_FLT)\n dis_uops(w).prs3_busy := f_uop.prs3_busy && dis_uops(w).frs3_en\n dis_uops(w).ppred_busy := p_uop.ppred_busy && dis_uops(w).is_sfb_shadow\n\n ren_stalls(w) := rename_stage.io.ren_stalls(w) || f_stall || p_stall\n }\n\n //-------------------------------------------------------------\n //-------------------------------------------------------------\n // **** Dispatch Stage ****\n //-------------------------------------------------------------\n //-------------------------------------------------------------\n\n //-------------------------------------------------------------\n // Rename2/Dispatch pipeline logic\n\n val dis_prior_slot_valid = dis_valids.scanLeft(false.B) ((s,v) => s || v)\n val dis_prior_slot_unique = (dis_uops zip dis_valids).scanLeft(false.B) {case (s,(u,v)) => s || v && u.is_unique}\n val wait_for_empty_pipeline = (0 until coreWidth).map(w => (dis_uops(w).is_unique || custom_csrs.disableOOO) &&\n (!rob.io.empty || !io.lsu.fencei_rdy || dis_prior_slot_valid(w)))\n val rocc_shim_busy = if (usingRoCC) !exe_units.rocc_unit.io.rocc.rxq_empty else false.B\n val wait_for_rocc = (0 until coreWidth).map(w =>\n (dis_uops(w).is_fence || dis_uops(w).is_fencei) && (io.rocc.busy || rocc_shim_busy))\n val rxq_full = if (usingRoCC) exe_units.rocc_unit.io.rocc.rxq_full else false.B\n val block_rocc = (dis_uops zip dis_valids).map{case (u,v) => v && u.uopc === uopROCC}.scanLeft(rxq_full)(_||_)\n val dis_rocc_alloc_stall = (dis_uops.map(_.uopc === uopROCC) zip block_rocc) map {case (p,r) =>\n if (usingRoCC) p && r else false.B}\n\n val dis_hazards = (0 until coreWidth).map(w =>\n dis_valids(w) &&\n ( !rob.io.ready\n || ren_stalls(w)\n || io.lsu.ldq_full(w) && dis_uops(w).uses_ldq\n || io.lsu.stq_full(w) && dis_uops(w).uses_stq\n || !dispatcher.io.ren_uops(w).ready\n || wait_for_empty_pipeline(w)\n || wait_for_rocc(w)\n || dis_prior_slot_unique(w)\n || dis_rocc_alloc_stall(w)\n || brupdate.b1.mispredict_mask =/= 0.U\n || brupdate.b2.mispredict\n || io.ifu.redirect_flush))\n\n\n io.lsu.fence_dmem := (dis_valids zip wait_for_empty_pipeline).map {case (v,w) => v && w} .reduce(_||_)\n\n val dis_stalls = dis_hazards.scanLeft(false.B) ((s,h) => s || h).takeRight(coreWidth)\n dis_fire := dis_valids zip dis_stalls map {case (v,s) => v && !s}\n dis_ready := !dis_stalls.last\n\n //-------------------------------------------------------------\n // LDQ/STQ Allocation Logic\n\n for (w <- 0 until coreWidth) {\n // Dispatching instructions request load/store queue entries when they can proceed.\n dis_uops(w).ldq_idx := io.lsu.dis_ldq_idx(w)\n dis_uops(w).stq_idx := io.lsu.dis_stq_idx(w)\n }\n\n //-------------------------------------------------------------\n // Rob Allocation Logic\n\n rob.io.enq_valids := dis_fire\n rob.io.enq_uops := dis_uops\n rob.io.enq_partial_stall := dis_stalls.last // TODO come up with better ROB compacting scheme.\n rob.io.debug_tsc := debug_tsc_reg\n rob.io.csr_stall := csr.io.csr_stall\n\n // Minor hack: ecall and breaks need to increment the FTQ deq ptr earlier than commit, since\n // they write their PC into the CSR the cycle before they commit.\n // Since these are also unique, increment the FTQ ptr when they are dispatched\n when (RegNext(dis_fire.reduce(_||_) && dis_uops(PriorityEncoder(dis_fire)).is_sys_pc2epc)) {\n io.ifu.commit.valid := true.B\n io.ifu.commit.bits := RegNext(dis_uops(PriorityEncoder(dis_valids)).ftq_idx)\n }\n\n for (w <- 0 until coreWidth) {\n // note: this assumes uops haven't been shifted - there's a 1:1 match between PC's LSBs and \"w\" here\n // (thus the LSB of the rob_idx gives part of the PC)\n if (coreWidth == 1) {\n dis_uops(w).rob_idx := rob.io.rob_tail_idx\n } else {\n dis_uops(w).rob_idx := Cat(rob.io.rob_tail_idx >> log2Ceil(coreWidth).U,\n w.U(log2Ceil(coreWidth).W))\n }\n }\n\n //-------------------------------------------------------------\n // RoCC allocation logic\n if (usingRoCC) {\n for (w <- 0 until coreWidth) {\n // We guarantee only decoding 1 RoCC instruction per cycle\n dis_uops(w).rxq_idx := exe_units.rocc_unit.io.rocc.rxq_idx(w)\n }\n }\n\n //-------------------------------------------------------------\n // Dispatch to issue queues\n\n // Get uops from rename2\n for (w <- 0 until coreWidth) {\n dispatcher.io.ren_uops(w).valid := dis_fire(w)\n dispatcher.io.ren_uops(w).bits := dis_uops(w)\n }\n\n var iu_idx = 0\n // Send dispatched uops to correct issue queues\n // Backpressure through dispatcher if necessary\n for (i <- 0 until issueParams.size) {\n if (issueParams(i).iqType == IQT_FP.litValue) {\n fp_pipeline.io.dis_uops <> dispatcher.io.dis_uops(i)\n } else {\n issue_units(iu_idx).io.dis_uops <> dispatcher.io.dis_uops(i)\n iu_idx += 1\n }\n }\n\n //-------------------------------------------------------------\n //-------------------------------------------------------------\n // **** Issue Stage ****\n //-------------------------------------------------------------\n //-------------------------------------------------------------\n\n require (issue_units.map(_.issueWidth).sum == exe_units.length)\n\n var iss_wu_idx = 1\n var ren_wu_idx = 1\n // The 0th wakeup port goes to the ll_wbarb\n int_iss_wakeups(0).valid := ll_wbarb.io.out.fire && ll_wbarb.io.out.bits.uop.dst_rtype === RT_FIX\n int_iss_wakeups(0).bits := ll_wbarb.io.out.bits\n\n int_ren_wakeups(0).valid := ll_wbarb.io.out.fire && ll_wbarb.io.out.bits.uop.dst_rtype === RT_FIX\n int_ren_wakeups(0).bits := ll_wbarb.io.out.bits\n\n for (i <- 1 until memWidth) {\n int_iss_wakeups(i).valid := mem_resps(i).valid && mem_resps(i).bits.uop.dst_rtype === RT_FIX\n int_iss_wakeups(i).bits := mem_resps(i).bits\n\n int_ren_wakeups(i).valid := mem_resps(i).valid && mem_resps(i).bits.uop.dst_rtype === RT_FIX\n int_ren_wakeups(i).bits := mem_resps(i).bits\n iss_wu_idx += 1\n ren_wu_idx += 1\n }\n\n // loop through each issue-port (exe_units are statically connected to an issue-port)\n for (i <- 0 until exe_units.length) {\n if (exe_units(i).writesIrf) {\n val fast_wakeup = Wire(Valid(new ExeUnitResp(xLen)))\n val slow_wakeup = Wire(Valid(new ExeUnitResp(xLen)))\n fast_wakeup := DontCare\n slow_wakeup := DontCare\n\n val resp = exe_units(i).io.iresp\n assert(!(resp.valid && resp.bits.uop.rf_wen && resp.bits.uop.dst_rtype =/= RT_FIX))\n\n // Fast Wakeup (uses just-issued uops that have known latencies)\n fast_wakeup.bits.uop := iss_uops(i)\n fast_wakeup.valid := iss_valids(i) &&\n iss_uops(i).bypassable &&\n iss_uops(i).dst_rtype === RT_FIX &&\n iss_uops(i).ldst_val &&\n !(io.lsu.ld_miss && (iss_uops(i).iw_p1_poisoned || iss_uops(i).iw_p2_poisoned))\n\n // Slow Wakeup (uses write-port to register file)\n slow_wakeup.bits.uop := resp.bits.uop\n slow_wakeup.valid := resp.valid &&\n resp.bits.uop.rf_wen &&\n !resp.bits.uop.bypassable &&\n resp.bits.uop.dst_rtype === RT_FIX\n\n if (exe_units(i).bypassable) {\n int_iss_wakeups(iss_wu_idx) := fast_wakeup\n iss_wu_idx += 1\n }\n if (!exe_units(i).alwaysBypassable) {\n int_iss_wakeups(iss_wu_idx) := slow_wakeup\n iss_wu_idx += 1\n }\n\n if (exe_units(i).bypassable) {\n int_ren_wakeups(ren_wu_idx) := fast_wakeup\n ren_wu_idx += 1\n }\n if (!exe_units(i).alwaysBypassable) {\n int_ren_wakeups(ren_wu_idx) := slow_wakeup\n ren_wu_idx += 1\n }\n }\n }\n require (iss_wu_idx == numIntIssueWakeupPorts)\n require (ren_wu_idx == numIntRenameWakeupPorts)\n require (iss_wu_idx == ren_wu_idx)\n\n // jmp unit performs fast wakeup of the predicate bits\n require (jmp_unit.bypassable)\n pred_wakeup.valid := (iss_valids(jmp_unit_idx) &&\n iss_uops(jmp_unit_idx).is_sfb_br &&\n !(io.lsu.ld_miss && (iss_uops(jmp_unit_idx).iw_p1_poisoned || iss_uops(jmp_unit_idx).iw_p2_poisoned))\n )\n pred_wakeup.bits.uop := iss_uops(jmp_unit_idx)\n pred_wakeup.bits.fflags := DontCare\n pred_wakeup.bits.data := DontCare\n pred_wakeup.bits.predicated := DontCare\n\n // Perform load-hit speculative wakeup through a special port (performs a poison wake-up).\n issue_units map { iu =>\n iu.io.spec_ld_wakeup := io.lsu.spec_ld_wakeup\n }\n\n\n // Connect the predicate wakeup port\n issue_units map { iu =>\n iu.io.pred_wakeup_port.valid := false.B\n iu.io.pred_wakeup_port.bits := DontCare\n }\n if (enableSFBOpt) {\n int_iss_unit.io.pred_wakeup_port.valid := pred_wakeup.valid\n int_iss_unit.io.pred_wakeup_port.bits := pred_wakeup.bits.uop.pdst\n }\n\n\n // ----------------------------------------------------------------\n // Connect the wakeup ports to the busy tables in the rename stages\n\n for ((renport, intport) <- rename_stage.io.wakeups zip int_ren_wakeups) {\n renport <> intport\n }\n if (usingFPU) {\n for ((renport, fpport) <- fp_rename_stage.io.wakeups zip fp_pipeline.io.wakeups) {\n renport <> fpport\n }\n }\n if (enableSFBOpt) {\n pred_rename_stage.io.wakeups(0) := pred_wakeup\n } else {\n pred_rename_stage.io.wakeups := DontCare\n }\n\n // If we issue loads back-to-back endlessly (probably because we are executing some tight loop)\n // the store buffer will never drain, breaking the memory-model forward-progress guarantee\n // If we see a large number of loads saturate the LSU, pause for a cycle to let a store drain\n val loads_saturating = (mem_iss_unit.io.iss_valids(0) && mem_iss_unit.io.iss_uops(0).uses_ldq)\n val saturating_loads_counter = RegInit(0.U(5.W))\n when (loads_saturating) { saturating_loads_counter := saturating_loads_counter + 1.U }\n .otherwise { saturating_loads_counter := 0.U }\n val pause_mem = RegNext(loads_saturating) && saturating_loads_counter === ~(0.U(5.W))\n\n var iss_idx = 0\n var int_iss_cnt = 0\n var mem_iss_cnt = 0\n for (w <- 0 until exe_units.length) {\n var fu_types = exe_units(w).io.fu_types\n val exe_unit = exe_units(w)\n if (exe_unit.readsIrf) {\n if (exe_unit.supportedFuncUnits.muld) {\n // Supress just-issued divides from issuing back-to-back, since it's an iterative divider.\n // But it takes a cycle to get to the Exe stage, so it can't tell us it is busy yet.\n val idiv_issued = iss_valids(iss_idx) && iss_uops(iss_idx).fu_code_is(FU_DIV)\n fu_types = fu_types & RegNext(~Mux(idiv_issued, FU_DIV, 0.U))\n }\n\n if (exe_unit.hasMem) {\n iss_valids(iss_idx) := mem_iss_unit.io.iss_valids(mem_iss_cnt)\n iss_uops(iss_idx) := mem_iss_unit.io.iss_uops(mem_iss_cnt)\n mem_iss_unit.io.fu_types(mem_iss_cnt) := Mux(pause_mem, 0.U, fu_types)\n mem_iss_cnt += 1\n } else {\n iss_valids(iss_idx) := int_iss_unit.io.iss_valids(int_iss_cnt)\n iss_uops(iss_idx) := int_iss_unit.io.iss_uops(int_iss_cnt)\n int_iss_unit.io.fu_types(int_iss_cnt) := fu_types\n int_iss_cnt += 1\n }\n iss_idx += 1\n }\n }\n require(iss_idx == exe_units.numIrfReaders)\n\n issue_units.map(_.io.tsc_reg := debug_tsc_reg)\n issue_units.map(_.io.brupdate := brupdate)\n issue_units.map(_.io.flush_pipeline := RegNext(rob.io.flush.valid))\n\n // Load-hit Misspeculations\n require (mem_iss_unit.issueWidth <= 2)\n issue_units.map(_.io.ld_miss := io.lsu.ld_miss)\n\n mem_units.map(u => u.io.com_exception := RegNext(rob.io.flush.valid))\n\n // Wakeup (Issue & Writeback)\n for {\n iu <- issue_units\n (issport, wakeup) <- iu.io.wakeup_ports zip int_iss_wakeups\n }{\n issport.valid := wakeup.valid\n issport.bits.pdst := wakeup.bits.uop.pdst\n issport.bits.poisoned := wakeup.bits.uop.iw_p1_poisoned || wakeup.bits.uop.iw_p2_poisoned\n\n require (iu.io.wakeup_ports.length == int_iss_wakeups.length)\n }\n\n //-------------------------------------------------------------\n //-------------------------------------------------------------\n // **** Register Read Stage ****\n //-------------------------------------------------------------\n //-------------------------------------------------------------\n\n // Register Read <- Issue (rrd <- iss)\n iregister_read.io.rf_read_ports <> iregfile.io.read_ports\n iregister_read.io.prf_read_ports := DontCare\n if (enableSFBOpt) {\n iregister_read.io.prf_read_ports <> pregfile.io.read_ports\n }\n\n for (w <- 0 until exe_units.numIrfReaders) {\n iregister_read.io.iss_valids(w) :=\n iss_valids(w) && !(io.lsu.ld_miss && (iss_uops(w).iw_p1_poisoned || iss_uops(w).iw_p2_poisoned))\n }\n iregister_read.io.iss_uops := iss_uops\n iregister_read.io.iss_uops map { u => u.iw_p1_poisoned := false.B; u.iw_p2_poisoned := false.B }\n\n iregister_read.io.brupdate := brupdate\n iregister_read.io.kill := RegNext(rob.io.flush.valid)\n\n iregister_read.io.bypass := bypasses\n iregister_read.io.pred_bypass := pred_bypasses\n\n //-------------------------------------------------------------\n // Privileged Co-processor 0 Register File\n // Note: Normally this would be bad in that I'm writing state before\n // committing, so to get this to work I stall the entire pipeline for\n // CSR instructions so I never speculate these instructions.\n\n val csr_exe_unit = exe_units.csr_unit\n\n // for critical path reasons, we aren't zero'ing this out if resp is not valid\n val csr_rw_cmd = csr_exe_unit.io.iresp.bits.uop.ctrl.csr_cmd\n val wb_wdata = csr_exe_unit.io.iresp.bits.data\n\n csr.io.rw.addr := csr_exe_unit.io.iresp.bits.uop.csr_addr\n csr.io.rw.cmd := freechips.rocketchip.rocket.CSR.maskCmd(csr_exe_unit.io.iresp.valid, csr_rw_cmd)\n csr.io.rw.wdata := wb_wdata\n\n rob.io.csr_replay.valid := csr_exe_unit.io.iresp.valid && csr.io.rw_stall\n rob.io.csr_replay.bits.uop := csr_exe_unit.io.iresp.bits.uop\n rob.io.csr_replay.bits.cause := MINI_EXCEPTION_CSR_REPLAY\n rob.io.csr_replay.bits.badvaddr := DontCare\n\n // Extra I/O\n // Delay retire/exception 1 cycle\n csr.io.retire := RegNext(PopCount(rob.io.commit.arch_valids.asUInt))\n csr.io.exception := RegNext(rob.io.com_xcpt.valid)\n // csr.io.pc used for setting EPC during exception or CSR.io.trace.\n\n csr.io.pc := (boom.v3.util.AlignPCToBoundary(io.ifu.get_pc(0).com_pc, icBlockBytes)\n + RegNext(rob.io.com_xcpt.bits.pc_lob)\n - Mux(RegNext(rob.io.com_xcpt.bits.edge_inst), 2.U, 0.U))\n // Cause not valid for for CALL or BREAKPOINTs (CSRFile will override it).\n csr.io.cause := RegNext(rob.io.com_xcpt.bits.cause)\n csr.io.ungated_clock := clock\n\n val tval_valid = csr.io.exception &&\n csr.io.cause.isOneOf(\n //Causes.illegal_instruction.U, we currently only write 0x0 for illegal instructions\n Causes.breakpoint.U,\n Causes.misaligned_load.U,\n Causes.misaligned_store.U,\n Causes.load_access.U,\n Causes.store_access.U,\n Causes.fetch_access.U,\n Causes.load_page_fault.U,\n Causes.store_page_fault.U,\n Causes.fetch_page_fault.U)\n\n csr.io.tval := Mux(tval_valid,\n RegNext(encodeVirtualAddress(rob.io.com_xcpt.bits.badvaddr, rob.io.com_xcpt.bits.badvaddr)), 0.U)\n\n // TODO move this function to some central location (since this is used elsewhere).\n def encodeVirtualAddress(a0: UInt, ea: UInt) =\n if (vaddrBitsExtended == vaddrBits) {\n ea\n } else {\n // Efficient means to compress 64-bit VA into vaddrBits+1 bits.\n // (VA is bad if VA(vaddrBits) != VA(vaddrBits-1)).\n val a = a0.asSInt >> vaddrBits\n val msb = Mux(a === 0.S || a === -1.S, ea(vaddrBits), !ea(vaddrBits-1))\n Cat(msb, ea(vaddrBits-1,0))\n }\n\n // reading requires serializing the entire pipeline\n csr.io.fcsr_flags.valid := rob.io.commit.fflags.valid\n csr.io.fcsr_flags.bits := rob.io.commit.fflags.bits\n csr.io.set_fs_dirty.get := rob.io.commit.fflags.valid\n\n exe_units.withFilter(_.hasFcsr).map(_.io.fcsr_rm := csr.io.fcsr_rm)\n io.fcsr_rm := csr.io.fcsr_rm\n\n if (usingFPU) {\n fp_pipeline.io.fcsr_rm := csr.io.fcsr_rm\n }\n\n csr.io.hartid := io.hartid\n csr.io.interrupts := io.interrupts\n\n // we do not support the H-extension\n csr.io.htval := DontCare\n csr.io.gva := DontCare\n\n// TODO can we add this back in, but handle reset properly and save us\n// the mux above on csr.io.rw.cmd?\n// assert (!(csr_rw_cmd =/= rocket.CSR.N && !exe_units(0).io.resp(0).valid),\n// \"CSRFile is being written to spuriously.\")\n\n //-------------------------------------------------------------\n //-------------------------------------------------------------\n // **** Execute Stage ****\n //-------------------------------------------------------------\n //-------------------------------------------------------------\n\n iss_idx = 0\n var bypass_idx = 0\n for (w <- 0 until exe_units.length) {\n val exe_unit = exe_units(w)\n if (exe_unit.readsIrf) {\n exe_unit.io.req <> iregister_read.io.exe_reqs(iss_idx)\n\n if (exe_unit.bypassable) {\n for (i <- 0 until exe_unit.numBypassStages) {\n bypasses(bypass_idx) := exe_unit.io.bypass(i)\n bypass_idx += 1\n }\n }\n iss_idx += 1\n }\n }\n require (bypass_idx == exe_units.numTotalBypassPorts)\n for (i <- 0 until jmp_unit.numBypassStages) {\n pred_bypasses(i) := jmp_unit.io.bypass(i)\n }\n\n //-------------------------------------------------------------\n //-------------------------------------------------------------\n // **** Load/Store Unit ****\n //-------------------------------------------------------------\n //-------------------------------------------------------------\n\n // enqueue basic load/store info in Decode\n for (w <- 0 until coreWidth) {\n io.lsu.dis_uops(w).valid := dis_fire(w)\n io.lsu.dis_uops(w).bits := dis_uops(w)\n }\n\n // tell LSU about committing loads and stores to clear entries\n io.lsu.commit := rob.io.commit\n\n // tell LSU that it should fire a load that waits for the rob to clear\n io.lsu.commit_load_at_rob_head := rob.io.com_load_is_at_rob_head\n\n //com_xcpt.valid comes too early, will fight against a branch that resolves same cycle as an exception\n io.lsu.exception := RegNext(rob.io.flush.valid)\n\n // Handle Branch Mispeculations\n io.lsu.brupdate := brupdate\n io.lsu.rob_head_idx := rob.io.rob_head_idx\n io.lsu.rob_pnr_idx := rob.io.rob_pnr_idx\n\n io.lsu.tsc_reg := debug_tsc_reg\n\n\n if (usingFPU) {\n io.lsu.fp_stdata <> fp_pipeline.io.to_sdq\n }\n\n //-------------------------------------------------------------\n //-------------------------------------------------------------\n // **** Writeback Stage ****\n //-------------------------------------------------------------\n //-------------------------------------------------------------\n\n var w_cnt = 1\n iregfile.io.write_ports(0) := WritePort(ll_wbarb.io.out, ipregSz, xLen, RT_FIX)\n ll_wbarb.io.in(0) <> mem_resps(0)\n assert (ll_wbarb.io.in(0).ready) // never backpressure the memory unit.\n for (i <- 1 until memWidth) {\n iregfile.io.write_ports(w_cnt) := WritePort(mem_resps(i), ipregSz, xLen, RT_FIX)\n w_cnt += 1\n }\n\n for (i <- 0 until exe_units.length) {\n if (exe_units(i).writesIrf) {\n val wbresp = exe_units(i).io.iresp\n val wbpdst = wbresp.bits.uop.pdst\n val wbdata = wbresp.bits.data\n\n def wbIsValid(rtype: UInt) =\n wbresp.valid && wbresp.bits.uop.rf_wen && wbresp.bits.uop.dst_rtype === rtype\n val wbReadsCSR = wbresp.bits.uop.ctrl.csr_cmd =/= freechips.rocketchip.rocket.CSR.N\n\n iregfile.io.write_ports(w_cnt).valid := wbIsValid(RT_FIX)\n iregfile.io.write_ports(w_cnt).bits.addr := wbpdst\n wbresp.ready := true.B\n if (exe_units(i).hasCSR) {\n iregfile.io.write_ports(w_cnt).bits.data := Mux(wbReadsCSR, csr.io.rw.rdata, wbdata)\n } else {\n iregfile.io.write_ports(w_cnt).bits.data := wbdata\n }\n\n assert (!wbIsValid(RT_FLT), \"[fppipeline] An FP writeback is being attempted to the Int Regfile.\")\n\n assert (!(wbresp.valid &&\n !wbresp.bits.uop.rf_wen &&\n wbresp.bits.uop.dst_rtype === RT_FIX),\n \"[fppipeline] An Int writeback is being attempted with rf_wen disabled.\")\n\n assert (!(wbresp.valid &&\n wbresp.bits.uop.rf_wen &&\n wbresp.bits.uop.dst_rtype =/= RT_FIX),\n \"[fppipeline] writeback being attempted to Int RF with dst != Int type exe_units(\"+i+\").iresp\")\n w_cnt += 1\n }\n }\n require(w_cnt == iregfile.io.write_ports.length)\n\n if (enableSFBOpt) {\n pregfile.io.write_ports(0).valid := jmp_unit.io.iresp.valid && jmp_unit.io.iresp.bits.uop.is_sfb_br\n pregfile.io.write_ports(0).bits.addr := jmp_unit.io.iresp.bits.uop.pdst\n pregfile.io.write_ports(0).bits.data := jmp_unit.io.iresp.bits.data\n }\n\n if (usingFPU) {\n // Connect IFPU\n fp_pipeline.io.from_int <> exe_units.ifpu_unit.io.ll_fresp\n // Connect FPIU\n ll_wbarb.io.in(1) <> fp_pipeline.io.to_int\n // Connect FLDs\n fp_pipeline.io.ll_wports <> exe_units.memory_units.map(_.io.ll_fresp).toSeq\n }\n if (usingRoCC) {\n require(usingFPU)\n ll_wbarb.io.in(2) <> exe_units.rocc_unit.io.ll_iresp\n }\n\n //-------------------------------------------------------------\n //-------------------------------------------------------------\n // **** Commit Stage ****\n //-------------------------------------------------------------\n //-------------------------------------------------------------\n\n // Writeback\n // ---------\n // First connect the ll_wport\n val ll_uop = ll_wbarb.io.out.bits.uop\n rob.io.wb_resps(0).valid := ll_wbarb.io.out.valid && !(ll_uop.uses_stq && !ll_uop.is_amo)\n rob.io.wb_resps(0).bits <> ll_wbarb.io.out.bits\n rob.io.debug_wb_valids(0) := ll_wbarb.io.out.valid && ll_uop.dst_rtype =/= RT_X\n rob.io.debug_wb_wdata(0) := ll_wbarb.io.out.bits.data\n var cnt = 1\n for (i <- 1 until memWidth) {\n val mem_uop = mem_resps(i).bits.uop\n rob.io.wb_resps(cnt).valid := mem_resps(i).valid && !(mem_uop.uses_stq && !mem_uop.is_amo)\n rob.io.wb_resps(cnt).bits := mem_resps(i).bits\n rob.io.debug_wb_valids(cnt) := mem_resps(i).valid && mem_uop.dst_rtype =/= RT_X\n rob.io.debug_wb_wdata(cnt) := mem_resps(i).bits.data\n cnt += 1\n }\n var f_cnt = 0 // rob fflags port index\n for (eu <- exe_units) {\n if (eu.writesIrf)\n {\n val resp = eu.io.iresp\n val wb_uop = resp.bits.uop\n val data = resp.bits.data\n\n rob.io.wb_resps(cnt).valid := resp.valid && !(wb_uop.uses_stq && !wb_uop.is_amo)\n rob.io.wb_resps(cnt).bits <> resp.bits\n rob.io.debug_wb_valids(cnt) := resp.valid && wb_uop.rf_wen && wb_uop.dst_rtype === RT_FIX\n if (eu.hasFFlags) {\n rob.io.fflags(f_cnt) <> resp.bits.fflags\n f_cnt += 1\n }\n if (eu.hasCSR) {\n rob.io.debug_wb_wdata(cnt) := Mux(wb_uop.ctrl.csr_cmd =/= freechips.rocketchip.rocket.CSR.N,\n csr.io.rw.rdata,\n data)\n } else {\n rob.io.debug_wb_wdata(cnt) := data\n }\n cnt += 1\n }\n }\n\n require(cnt == numIrfWritePorts)\n if (usingFPU) {\n for ((wdata, wakeup) <- fp_pipeline.io.debug_wb_wdata zip fp_pipeline.io.wakeups) {\n rob.io.wb_resps(cnt) <> wakeup\n rob.io.fflags(f_cnt) <> wakeup.bits.fflags\n rob.io.debug_wb_valids(cnt) := wakeup.valid\n rob.io.debug_wb_wdata(cnt) := wdata\n cnt += 1\n f_cnt += 1\n\n assert (!(wakeup.valid && wakeup.bits.uop.dst_rtype =/= RT_FLT),\n \"[core] FP wakeup does not write back to a FP register.\")\n\n assert (!(wakeup.valid && !wakeup.bits.uop.fp_val),\n \"[core] FP wakeup does not involve an FP instruction.\")\n }\n }\n\n require (cnt == rob.numWakeupPorts)\n require (f_cnt == rob.numFpuPorts)\n\n // branch resolution\n rob.io.brupdate <> brupdate\n\n exe_units.map(u => u.io.status := csr.io.status)\n if (usingFPU)\n fp_pipeline.io.status := csr.io.status\n\n // Connect breakpoint info to memaddrcalcunit\n for (i <- 0 until memWidth) {\n mem_units(i).io.status := csr.io.status\n mem_units(i).io.bp := csr.io.bp\n mem_units(i).io.mcontext := csr.io.mcontext\n mem_units(i).io.scontext := csr.io.scontext\n }\n\n // LSU <> ROB\n rob.io.lsu_clr_bsy := io.lsu.clr_bsy\n rob.io.lsu_clr_unsafe := io.lsu.clr_unsafe\n rob.io.lxcpt <> io.lsu.lxcpt\n\n assert (!(csr.io.singleStep), \"[core] single-step is unsupported.\")\n\n\n //-------------------------------------------------------------\n // **** Flush Pipeline ****\n //-------------------------------------------------------------\n // flush on exceptions, miniexeptions, and after some special instructions\n\n if (usingFPU) {\n fp_pipeline.io.flush_pipeline := RegNext(rob.io.flush.valid)\n }\n\n for (w <- 0 until exe_units.length) {\n exe_units(w).io.req.bits.kill := RegNext(rob.io.flush.valid)\n }\n\n assert (!(rob.io.com_xcpt.valid && !rob.io.flush.valid),\n \"[core] exception occurred, but pipeline flush signal not set!\")\n\n //-------------------------------------------------------------\n //-------------------------------------------------------------\n // **** Outputs to the External World ****\n //-------------------------------------------------------------\n //-------------------------------------------------------------\n\n // detect pipeline freezes and throw error\n val idle_cycles = freechips.rocketchip.util.WideCounter(32)\n when (rob.io.commit.valids.asUInt.orR ||\n csr.io.csr_stall ||\n io.rocc.busy ||\n reset.asBool) {\n idle_cycles := 0.U\n }\n assert (!(idle_cycles.value(13)), \"Pipeline has hung.\")\n\n if (usingFPU) {\n fp_pipeline.io.debug_tsc_reg := debug_tsc_reg\n }\n\n //-------------------------------------------------------------\n //-------------------------------------------------------------\n // **** Handle Cycle-by-Cycle Printouts ****\n //-------------------------------------------------------------\n //-------------------------------------------------------------\n\n\n if (COMMIT_LOG_PRINTF) {\n var new_commit_cnt = 0.U\n\n for (w <- 0 until coreWidth) {\n val priv = RegNext(csr.io.status.prv) // erets change the privilege. Get the old one\n\n // To allow for diffs against spike :/\n def printf_inst(uop: MicroOp) = {\n when (uop.is_rvc) {\n printf(\"(0x%x)\", uop.debug_inst(15,0))\n } .otherwise {\n printf(\"(0x%x)\", uop.debug_inst)\n }\n }\n\n when (rob.io.commit.arch_valids(w)) {\n printf(\"%d 0x%x \",\n priv,\n Sext(rob.io.commit.uops(w).debug_pc(vaddrBits-1,0), xLen))\n printf_inst(rob.io.commit.uops(w))\n when (rob.io.commit.uops(w).dst_rtype === RT_FIX && rob.io.commit.uops(w).ldst =/= 0.U) {\n printf(\" x%d 0x%x\\n\",\n rob.io.commit.uops(w).ldst,\n rob.io.commit.debug_wdata(w))\n } .elsewhen (rob.io.commit.uops(w).dst_rtype === RT_FLT) {\n printf(\" f%d 0x%x\\n\",\n rob.io.commit.uops(w).ldst,\n rob.io.commit.debug_wdata(w))\n } .otherwise {\n printf(\"\\n\")\n }\n }\n }\n } else if (BRANCH_PRINTF) {\n val debug_ghist = RegInit(0.U(globalHistoryLength.W))\n when (rob.io.flush.valid && FlushTypes.useCsrEvec(rob.io.flush.bits.flush_typ)) {\n debug_ghist := 0.U\n }\n\n var new_ghist = debug_ghist\n\n for (w <- 0 until coreWidth) {\n when (rob.io.commit.arch_valids(w) &&\n (rob.io.commit.uops(w).is_br || rob.io.commit.uops(w).is_jal || rob.io.commit.uops(w).is_jalr)) {\n // for (i <- 0 until globalHistoryLength) {\n // printf(\"%x\", new_ghist(globalHistoryLength-i-1))\n // }\n // printf(\"\\n\")\n printf(\"%x %x %x %x %x %x\\n\",\n rob.io.commit.uops(w).debug_fsrc, rob.io.commit.uops(w).taken,\n rob.io.commit.uops(w).is_br, rob.io.commit.uops(w).is_jal,\n rob.io.commit.uops(w).is_jalr, Sext(rob.io.commit.uops(w).debug_pc(vaddrBits-1,0), xLen))\n\n }\n new_ghist = Mux(rob.io.commit.arch_valids(w) && rob.io.commit.uops(w).is_br,\n Mux(rob.io.commit.uops(w).taken, new_ghist << 1 | 1.U(1.W), new_ghist << 1),\n new_ghist)\n }\n debug_ghist := new_ghist\n }\n\n // TODO: Does anyone want this debugging functionality?\n val coreMonitorBundle = Wire(new CoreMonitorBundle(xLen, fLen))\n coreMonitorBundle := DontCare\n coreMonitorBundle.clock := clock\n coreMonitorBundle.reset := reset\n\n\n //-------------------------------------------------------------\n //-------------------------------------------------------------\n // Page Table Walker\n\n io.ptw.ptbr := csr.io.ptbr\n io.ptw.status := csr.io.status\n io.ptw.pmp := csr.io.pmp\n io.ptw.sfence := io.ifu.sfence\n\n //-------------------------------------------------------------\n //-------------------------------------------------------------\n\n io.rocc := DontCare\n io.rocc.exception := csr.io.exception && csr.io.status.xs.orR\n io.rocc.csrs <> csr.io.roccCSRs\n if (usingRoCC) {\n exe_units.rocc_unit.io.rocc.rocc <> io.rocc\n exe_units.rocc_unit.io.rocc.dis_uops := dis_uops\n exe_units.rocc_unit.io.rocc.rob_head_idx := rob.io.rob_head_idx\n exe_units.rocc_unit.io.rocc.rob_pnr_idx := rob.io.rob_pnr_idx\n exe_units.rocc_unit.io.com_exception := rob.io.flush.valid\n exe_units.rocc_unit.io.status := csr.io.status\n\n for (w <- 0 until coreWidth) {\n exe_units.rocc_unit.io.rocc.dis_rocc_vals(w) := (\n dis_fire(w) &&\n dis_uops(w).uopc === uopROCC &&\n !dis_uops(w).exception\n )\n }\n }\n\n io.trace := DontCare\n io.trace.time := csr.io.time\n io.trace.insns map (t => t.valid := false.B)\n io.trace.custom.get.asInstanceOf[BoomTraceBundle].rob_empty := rob.io.empty\n\n if (trace) {\n for (w <- 0 until coreWidth) {\n // Delay the trace so we have a cycle to pull PCs out of the FTQ\n io.trace.insns(w).valid := RegNext(rob.io.commit.arch_valids(w))\n\n // Recalculate the PC\n io.ifu.debug_ftq_idx(w) := rob.io.commit.uops(w).ftq_idx\n val iaddr = (AlignPCToBoundary(io.ifu.debug_fetch_pc(w), icBlockBytes)\n + RegNext(rob.io.commit.uops(w).pc_lob)\n - Mux(RegNext(rob.io.commit.uops(w).edge_inst), 2.U, 0.U))(vaddrBits-1,0)\n io.trace.insns(w).iaddr := Sext(iaddr, xLen)\n\n def getInst(uop: MicroOp, inst: UInt): UInt = {\n Mux(uop.is_rvc, Cat(0.U(16.W), inst(15,0)), inst)\n }\n\n def getWdata(uop: MicroOp, wdata: UInt): UInt = {\n Mux((uop.dst_rtype === RT_FIX && uop.ldst =/= 0.U) || (uop.dst_rtype === RT_FLT), wdata, 0.U(xLen.W))\n }\n\n // use debug_insts instead of uop.debug_inst to use the rob's debug_inst_mem\n // note: rob.debug_insts comes 1 cycle later\n io.trace.insns(w).insn := getInst(RegNext(rob.io.commit.uops(w)), rob.io.commit.debug_insts(w))\n io.trace.insns(w).wdata.map { _ := RegNext(getWdata(rob.io.commit.uops(w), rob.io.commit.debug_wdata(w))) }\n\n // Comment out this assert because it blows up FPGA synth-asserts\n // This tests correctedness of the debug_inst mem\n // when (RegNext(rob.io.commit.valids(w))) {\n // assert(rob.io.commit.debug_insts(w) === RegNext(rob.io.commit.uops(w).debug_inst))\n // }\n // This tests correctedness of recovering pcs through ftq debug ports\n // when (RegNext(rob.io.commit.valids(w))) {\n // assert(Sext(io.trace.insns(w).iaddr, xLen) ===\n // RegNext(Sext(rob.io.commit.uops(w).debug_pc(vaddrBits-1,0), xLen)))\n // }\n\n // These csr signals do not exactly match up with the ROB commit signals.\n io.trace.insns(w).priv := RegNext(Cat(RegNext(csr.io.status.debug), csr.io.status.prv))\n // Can determine if it is an interrupt or not based on the MSB of the cause\n io.trace.insns(w).exception := RegNext(rob.io.com_xcpt.valid && !rob.io.com_xcpt.bits.cause(xLen - 1)) && (w == 0).B\n io.trace.insns(w).interrupt := RegNext(rob.io.com_xcpt.valid && rob.io.com_xcpt.bits.cause(xLen - 1)) && (w == 0).B\n io.trace.insns(w).cause := RegNext(rob.io.com_xcpt.bits.cause)\n io.trace.insns(w).tval := RegNext(csr.io.tval)\n }\n dontTouch(io.trace)\n } else {\n io.ifu.debug_ftq_idx := DontCare\n }\n}\nFile Counters.scala:\n// See LICENSE.Berkeley for license details.\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3._\nimport chisel3.util._\n\n// Produces 0-width value when counting to 1\nclass ZCounter(val n: Int) {\n val value = RegInit(0.U(log2Ceil(n).W))\n def inc(): Bool = {\n if (n == 1) true.B\n else {\n val wrap = value === (n-1).U\n value := Mux(!isPow2(n).B && wrap, 0.U, value + 1.U)\n wrap\n }\n }\n}\n\nobject ZCounter {\n def apply(n: Int) = new ZCounter(n)\n def apply(cond: Bool, n: Int): (UInt, Bool) = {\n val c = new ZCounter(n)\n var wrap: Bool = null\n when (cond) { wrap = c.inc() }\n (c.value, cond && wrap)\n }\n}\n\nobject TwoWayCounter {\n def apply(up: Bool, down: Bool, max: Int): UInt = {\n val cnt = RegInit(0.U(log2Up(max + 1).W))\n when (up && !down) { cnt := cnt + 1.U }\n when (down && !up) { cnt := cnt - 1.U }\n cnt\n }\n}\n\n// a counter that clock gates most of its MSBs using the LSB carry-out\ncase class WideCounter(width: Int, inc: UInt = 1.U, reset: Boolean = true, inhibit: Bool = false.B) {\n private val isWide = width > (2 * inc.getWidth)\n private val smallWidth = if (isWide) inc.getWidth max log2Up(width) else width\n private val small = if (reset) RegInit(0.U(smallWidth.W)) else Reg(UInt(smallWidth.W))\n private val nextSmall = small +& inc\n when (!inhibit) { small := nextSmall }\n\n private val large = if (isWide) {\n val r = if (reset) RegInit(0.U((width - smallWidth).W)) else Reg(UInt((width - smallWidth).W))\n when (nextSmall(smallWidth) && !inhibit) { r := r + 1.U }\n r\n } else null\n\n val value = if (isWide) Cat(large, small) else small\n lazy val carryOut = {\n val lo = (small ^ nextSmall) >> 1\n if (!isWide)\n lo\n else {\n val hi = Mux(nextSmall(smallWidth), large ^ (large +& 1.U), 0.U) >> 1\n Cat(hi, lo)\n }\n }\n\n def := (x: UInt) = {\n small := x\n if (isWide) large := x >> smallWidth\n }\n}\nFile util.scala:\n//******************************************************************************\n// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).\n// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.\n//------------------------------------------------------------------------------\n\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n// Utility Functions\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n\npackage boom.v3.util\n\nimport chisel3._\nimport chisel3.util._\n\nimport freechips.rocketchip.rocket.Instructions._\nimport freechips.rocketchip.rocket._\nimport freechips.rocketchip.util.{Str}\nimport org.chipsalliance.cde.config.{Parameters}\nimport freechips.rocketchip.tile.{TileKey}\n\nimport boom.v3.common.{MicroOp}\nimport boom.v3.exu.{BrUpdateInfo}\n\n/**\n * Object to XOR fold a input register of fullLength into a compressedLength.\n */\nobject Fold\n{\n def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = {\n val clen = compressedLength\n val hlen = fullLength\n if (hlen <= clen) {\n input\n } else {\n var res = 0.U(clen.W)\n var remaining = input.asUInt\n for (i <- 0 to hlen-1 by clen) {\n val len = if (i + clen > hlen ) (hlen - i) else clen\n require(len > 0)\n res = res(clen-1,0) ^ remaining(len-1,0)\n remaining = remaining >> len.U\n }\n res\n }\n }\n}\n\n/**\n * Object to check if MicroOp was killed due to a branch mispredict.\n * Uses \"Fast\" branch masks\n */\nobject IsKilledByBranch\n{\n def apply(brupdate: BrUpdateInfo, uop: MicroOp): Bool = {\n return maskMatch(brupdate.b1.mispredict_mask, uop.br_mask)\n }\n\n def apply(brupdate: BrUpdateInfo, uop_mask: UInt): Bool = {\n return maskMatch(brupdate.b1.mispredict_mask, uop_mask)\n }\n}\n\n/**\n * Object to return new MicroOp with a new BR mask given a MicroOp mask\n * and old BR mask.\n */\nobject GetNewUopAndBrMask\n{\n def apply(uop: MicroOp, brupdate: BrUpdateInfo)\n (implicit p: Parameters): MicroOp = {\n val newuop = WireInit(uop)\n newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask\n newuop\n }\n}\n\n/**\n * Object to return a BR mask given a MicroOp mask and old BR mask.\n */\nobject GetNewBrMask\n{\n def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = {\n return uop.br_mask & ~brupdate.b1.resolve_mask\n }\n\n def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = {\n return br_mask & ~brupdate.b1.resolve_mask\n }\n}\n\nobject UpdateBrMask\n{\n def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = {\n val out = WireInit(uop)\n out.br_mask := GetNewBrMask(brupdate, uop)\n out\n }\n def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = {\n val out = WireInit(bundle)\n out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask)\n out\n }\n def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: Valid[T]): Valid[T] = {\n val out = WireInit(bundle)\n out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask)\n out.valid := bundle.valid && !IsKilledByBranch(brupdate, bundle.bits.uop.br_mask)\n out\n }\n}\n\n/**\n * Object to check if at least 1 bit matches in two masks\n */\nobject maskMatch\n{\n def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U\n}\n\n/**\n * Object to clear one bit in a mask given an index\n */\nobject clearMaskBit\n{\n def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0)\n}\n\n/**\n * Object to shift a register over by one bit and concat a new one\n */\nobject PerformShiftRegister\n{\n def apply(reg_val: UInt, new_bit: Bool): UInt = {\n reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt\n reg_val\n }\n}\n\n/**\n * Object to shift a register over by one bit, wrapping the top bit around to the bottom\n * (XOR'ed with a new-bit), and evicting a bit at index HLEN.\n * This is used to simulate a longer HLEN-width shift register that is folded\n * down to a compressed CLEN.\n */\nobject PerformCircularShiftRegister\n{\n def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = {\n val carry = csr(clen-1)\n val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U)\n newval\n }\n}\n\n/**\n * Object to increment an input value, wrapping it if\n * necessary.\n */\nobject WrapAdd\n{\n // \"n\" is the number of increments, so we wrap at n-1.\n def apply(value: UInt, amt: UInt, n: Int): UInt = {\n if (isPow2(n)) {\n (value + amt)(log2Ceil(n)-1,0)\n } else {\n val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt)\n Mux(sum >= n.U,\n sum - n.U,\n sum)\n }\n }\n}\n\n/**\n * Object to decrement an input value, wrapping it if\n * necessary.\n */\nobject WrapSub\n{\n // \"n\" is the number of increments, so we wrap to n-1.\n def apply(value: UInt, amt: Int, n: Int): UInt = {\n if (isPow2(n)) {\n (value - amt.U)(log2Ceil(n)-1,0)\n } else {\n val v = Cat(0.U(1.W), value)\n val b = Cat(0.U(1.W), amt.U)\n Mux(value >= amt.U,\n value - amt.U,\n n.U - amt.U + value)\n }\n }\n}\n\n/**\n * Object to increment an input value, wrapping it if\n * necessary.\n */\nobject WrapInc\n{\n // \"n\" is the number of increments, so we wrap at n-1.\n def apply(value: UInt, n: Int): UInt = {\n if (isPow2(n)) {\n (value + 1.U)(log2Ceil(n)-1,0)\n } else {\n val wrap = (value === (n-1).U)\n Mux(wrap, 0.U, value + 1.U)\n }\n }\n}\n\n/**\n * Object to decrement an input value, wrapping it if\n * necessary.\n */\nobject WrapDec\n{\n // \"n\" is the number of increments, so we wrap at n-1.\n def apply(value: UInt, n: Int): UInt = {\n if (isPow2(n)) {\n (value - 1.U)(log2Ceil(n)-1,0)\n } else {\n val wrap = (value === 0.U)\n Mux(wrap, (n-1).U, value - 1.U)\n }\n }\n}\n\n/**\n * Object to mask off lower bits of a PC to align to a \"b\"\n * Byte boundary.\n */\nobject AlignPCToBoundary\n{\n def apply(pc: UInt, b: Int): UInt = {\n // Invert for scenario where pc longer than b\n // (which would clear all bits above size(b)).\n ~(~pc | (b-1).U)\n }\n}\n\n/**\n * Object to rotate a signal left by one\n */\nobject RotateL1\n{\n def apply(signal: UInt): UInt = {\n val w = signal.getWidth\n val out = Cat(signal(w-2,0), signal(w-1))\n\n return out\n }\n}\n\n/**\n * Object to sext a value to a particular length.\n */\nobject Sext\n{\n def apply(x: UInt, length: Int): UInt = {\n if (x.getWidth == length) return x\n else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x)\n }\n}\n\n/**\n * Object to translate from BOOM's special \"packed immediate\" to a 32b signed immediate\n * Asking for U-type gives it shifted up 12 bits.\n */\nobject ImmGen\n{\n import boom.v3.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U}\n def apply(ip: UInt, isel: UInt): SInt = {\n val sign = ip(LONGEST_IMM_SZ-1).asSInt\n val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign)\n val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign)\n val i11 = Mux(isel === IS_U, 0.S,\n Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign))\n val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt)\n val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt)\n val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S)\n\n return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0).asSInt\n }\n}\n\n/**\n * Object to get the FP rounding mode out of a packed immediate.\n */\nobject ImmGenRm { def apply(ip: UInt): UInt = { return ip(2,0) } }\n\n/**\n * Object to get the FP function fype from a packed immediate.\n * Note: only works if !(IS_B or IS_S)\n */\nobject ImmGenTyp { def apply(ip: UInt): UInt = { return ip(9,8) } }\n\n/**\n * Object to see if an instruction is a JALR.\n */\nobject DebugIsJALR\n{\n def apply(inst: UInt): Bool = {\n // TODO Chisel not sure why this won't compile\n// val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)),\n// Array(\n// JALR -> Bool(true)))\n inst(6,0) === \"b1100111\".U\n }\n}\n\n/**\n * Object to take an instruction and output its branch or jal target. Only used\n * for a debug assert (no where else would we jump straight from instruction\n * bits to a target).\n */\nobject DebugGetBJImm\n{\n def apply(inst: UInt): UInt = {\n // TODO Chisel not sure why this won't compile\n //val csignals =\n //rocket.DecodeLogic(inst,\n // List(Bool(false), Bool(false)),\n // Array(\n // BEQ -> List(Bool(true ), Bool(false)),\n // BNE -> List(Bool(true ), Bool(false)),\n // BGE -> List(Bool(true ), Bool(false)),\n // BGEU -> List(Bool(true ), Bool(false)),\n // BLT -> List(Bool(true ), Bool(false)),\n // BLTU -> List(Bool(true ), Bool(false))\n // ))\n //val is_br :: nothing :: Nil = csignals\n\n val is_br = (inst(6,0) === \"b1100011\".U)\n\n val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W))\n val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W))\n\n Mux(is_br, br_targ, jal_targ)\n }\n}\n\n/**\n * Object to return the lowest bit position after the head.\n */\nobject AgePriorityEncoder\n{\n def apply(in: Seq[Bool], head: UInt): UInt = {\n val n = in.size\n val width = log2Ceil(in.size)\n val n_padded = 1 << width\n val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in\n val idx = PriorityEncoder(temp_vec)\n idx(width-1, 0) //discard msb\n }\n}\n\n/**\n * Object to determine whether queue\n * index i0 is older than index i1.\n */\nobject IsOlder\n{\n def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head))\n}\n\n/**\n * Set all bits at or below the highest order '1'.\n */\nobject MaskLower\n{\n def apply(in: UInt) = {\n val n = in.getWidth\n (0 until n).map(i => in >> i.U).reduce(_|_)\n }\n}\n\n/**\n * Set all bits at or above the lowest order '1'.\n */\nobject MaskUpper\n{\n def apply(in: UInt) = {\n val n = in.getWidth\n (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_)\n }\n}\n\n/**\n * Transpose a matrix of Chisel Vecs.\n */\nobject Transpose\n{\n def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = {\n val n = in(0).size\n VecInit((0 until n).map(i => VecInit(in.map(row => row(i)))))\n }\n}\n\n/**\n * N-wide one-hot priority encoder.\n */\nobject SelectFirstN\n{\n def apply(in: UInt, n: Int) = {\n val sels = Wire(Vec(n, UInt(in.getWidth.W)))\n var mask = in\n\n for (i <- 0 until n) {\n sels(i) := PriorityEncoderOH(mask)\n mask = mask & ~sels(i)\n }\n\n sels\n }\n}\n\n/**\n * Connect the first k of n valid input interfaces to k output interfaces.\n */\nclass Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module\n{\n require(n >= k)\n\n val io = IO(new Bundle {\n val in = Vec(n, Flipped(DecoupledIO(gen)))\n val out = Vec(k, DecoupledIO(gen))\n })\n\n if (n == k) {\n io.out <> io.in\n } else {\n val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c))\n val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col =>\n (col zip io.in.map(_.valid)) map {case (c,v) => c && v})\n val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_))\n val out_valids = sels map (col => col.reduce(_||_))\n val out_data = sels map (s => Mux1H(s, io.in.map(_.bits)))\n\n in_readys zip io.in foreach {case (r,i) => i.ready := r}\n out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d}\n }\n}\n\n/**\n * Create a queue that can be killed with a branch kill signal.\n * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq).\n */\nclass BranchKillableQueue[T <: boom.v3.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v3.common.MicroOp => Bool = u => true.B, flow: Boolean = true)\n (implicit p: org.chipsalliance.cde.config.Parameters)\n extends boom.v3.common.BoomModule()(p)\n with boom.v3.common.HasBoomCoreParameters\n{\n val io = IO(new Bundle {\n val enq = Flipped(Decoupled(gen))\n val deq = Decoupled(gen)\n\n val brupdate = Input(new BrUpdateInfo())\n val flush = Input(Bool())\n\n val empty = Output(Bool())\n val count = Output(UInt(log2Ceil(entries).W))\n })\n\n val ram = Mem(entries, gen)\n val valids = RegInit(VecInit(Seq.fill(entries) {false.B}))\n val uops = Reg(Vec(entries, new MicroOp))\n\n val enq_ptr = Counter(entries)\n val deq_ptr = Counter(entries)\n val maybe_full = RegInit(false.B)\n\n val ptr_match = enq_ptr.value === deq_ptr.value\n io.empty := ptr_match && !maybe_full\n val full = ptr_match && maybe_full\n val do_enq = WireInit(io.enq.fire)\n val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty)\n\n for (i <- 0 until entries) {\n val mask = uops(i).br_mask\n val uop = uops(i)\n valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, mask) && !(io.flush && flush_fn(uop))\n when (valids(i)) {\n uops(i).br_mask := GetNewBrMask(io.brupdate, mask)\n }\n }\n\n when (do_enq) {\n ram(enq_ptr.value) := io.enq.bits\n valids(enq_ptr.value) := true.B //!IsKilledByBranch(io.brupdate, io.enq.bits.uop)\n uops(enq_ptr.value) := io.enq.bits.uop\n uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)\n enq_ptr.inc()\n }\n\n when (do_deq) {\n valids(deq_ptr.value) := false.B\n deq_ptr.inc()\n }\n\n when (do_enq =/= do_deq) {\n maybe_full := do_enq\n }\n\n io.enq.ready := !full\n\n val out = Wire(gen)\n out := ram(deq_ptr.value)\n out.uop := uops(deq_ptr.value)\n io.deq.valid := !io.empty && valids(deq_ptr.value) && !IsKilledByBranch(io.brupdate, out.uop) && !(io.flush && flush_fn(out.uop))\n io.deq.bits := out\n io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, out.uop)\n\n // For flow queue behavior.\n if (flow) {\n when (io.empty) {\n io.deq.valid := io.enq.valid //&& !IsKilledByBranch(io.brupdate, io.enq.bits.uop)\n io.deq.bits := io.enq.bits\n io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)\n\n do_deq := false.B\n when (io.deq.ready) { do_enq := false.B }\n }\n }\n private val ptr_diff = enq_ptr.value - deq_ptr.value\n if (isPow2(entries)) {\n io.count := Cat(maybe_full && ptr_match, ptr_diff)\n }\n else {\n io.count := Mux(ptr_match,\n Mux(maybe_full,\n entries.asUInt, 0.U),\n Mux(deq_ptr.value > enq_ptr.value,\n entries.asUInt + ptr_diff, ptr_diff))\n }\n}\n\n// ------------------------------------------\n// Printf helper functions\n// ------------------------------------------\n\nobject BoolToChar\n{\n /**\n * Take in a Chisel Bool and convert it into a Str\n * based on the Chars given\n *\n * @param c_bool Chisel Bool\n * @param trueChar Scala Char if bool is true\n * @param falseChar Scala Char if bool is false\n * @return UInt ASCII Char for \"trueChar\" or \"falseChar\"\n */\n def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = {\n Mux(c_bool, Str(trueChar), Str(falseChar))\n }\n}\n\nobject CfiTypeToChars\n{\n /**\n * Get a Vec of Strs that can be used for printing\n *\n * @param cfi_type specific cfi type\n * @return Vec of Strs (must be indexed to get specific char)\n */\n def apply(cfi_type: UInt) = {\n val strings = Seq(\"----\", \"BR \", \"JAL \", \"JALR\")\n val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })\n multiVec(cfi_type)\n }\n}\n\nobject BpdTypeToChars\n{\n /**\n * Get a Vec of Strs that can be used for printing\n *\n * @param bpd_type specific bpd type\n * @return Vec of Strs (must be indexed to get specific char)\n */\n def apply(bpd_type: UInt) = {\n val strings = Seq(\"BR \", \"JUMP\", \"----\", \"RET \", \"----\", \"CALL\", \"----\", \"----\")\n val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })\n multiVec(bpd_type)\n }\n}\n\nobject RobTypeToChars\n{\n /**\n * Get a Vec of Strs that can be used for printing\n *\n * @param rob_type specific rob type\n * @return Vec of Strs (must be indexed to get specific char)\n */\n def apply(rob_type: UInt) = {\n val strings = Seq(\"RST\", \"NML\", \"RBK\", \" WT\")\n val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })\n multiVec(rob_type)\n }\n}\n\nobject XRegToChars\n{\n /**\n * Get a Vec of Strs that can be used for printing\n *\n * @param xreg specific register number\n * @return Vec of Strs (must be indexed to get specific char)\n */\n def apply(xreg: UInt) = {\n val strings = Seq(\" x0\", \" ra\", \" sp\", \" gp\",\n \" tp\", \" t0\", \" t1\", \" t2\",\n \" s0\", \" s1\", \" a0\", \" a1\",\n \" a2\", \" a3\", \" a4\", \" a5\",\n \" a6\", \" a7\", \" s2\", \" s3\",\n \" s4\", \" s5\", \" s6\", \" s7\",\n \" s8\", \" s9\", \"s10\", \"s11\",\n \" t3\", \" t4\", \" t5\", \" t6\")\n val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })\n multiVec(xreg)\n }\n}\n\nobject FPRegToChars\n{\n /**\n * Get a Vec of Strs that can be used for printing\n *\n * @param fpreg specific register number\n * @return Vec of Strs (must be indexed to get specific char)\n */\n def apply(fpreg: UInt) = {\n val strings = Seq(\" ft0\", \" ft1\", \" ft2\", \" ft3\",\n \" ft4\", \" ft5\", \" ft6\", \" ft7\",\n \" fs0\", \" fs1\", \" fa0\", \" fa1\",\n \" fa2\", \" fa3\", \" fa4\", \" fa5\",\n \" fa6\", \" fa7\", \" fs2\", \" fs3\",\n \" fs4\", \" fs5\", \" fs6\", \" fs7\",\n \" fs8\", \" fs9\", \"fs10\", \"fs11\",\n \" ft8\", \" ft9\", \"ft10\", \"ft11\")\n val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })\n multiVec(fpreg)\n }\n}\n\nobject BoomCoreStringPrefix\n{\n /**\n * Add prefix to BOOM strings (currently only adds the hartId)\n *\n * @param strs list of strings\n * @return String combining the list with the prefix per line\n */\n def apply(strs: String*)(implicit p: Parameters) = {\n val prefix = \"[C\" + s\"${p(TileKey).tileId}\" + \"] \"\n strs.map(str => prefix + str + \"\\n\").mkString(\"\")\n }\n}\nFile Events.scala:\n// See LICENSE.Berkeley for license details.\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.rocket\n\nimport chisel3._\nimport chisel3.util.log2Ceil\nimport freechips.rocketchip.util._\nimport freechips.rocketchip.util.property\n\nclass EventSet(val gate: (UInt, UInt) => Bool, val events: Seq[(String, () => Bool)]) {\n def size = events.size\n val hits = WireDefault(VecInit(Seq.fill(size)(false.B)))\n def check(mask: UInt) = {\n hits := events.map(_._2())\n gate(mask, hits.asUInt)\n }\n def dump(): Unit = {\n for (((name, _), i) <- events.zipWithIndex)\n when (check(1.U << i)) { printf(s\"Event $name\\n\") }\n }\n def withCovers: Unit = {\n events.zipWithIndex.foreach {\n case ((name, func), i) => property.cover(gate((1.U << i), (func() << i)), name)\n }\n }\n}\n\nclass EventSets(val eventSets: Seq[EventSet]) {\n def maskEventSelector(eventSel: UInt): UInt = {\n // allow full associativity between counters and event sets (for now?)\n val setMask = (BigInt(1) << eventSetIdBits) - 1\n val maskMask = ((BigInt(1) << eventSets.map(_.size).max) - 1) << maxEventSetIdBits\n eventSel & (setMask | maskMask).U\n }\n\n private def decode(counter: UInt): (UInt, UInt) = {\n require(eventSets.size <= (1 << maxEventSetIdBits))\n require(eventSetIdBits > 0)\n (counter(eventSetIdBits-1, 0), counter >> maxEventSetIdBits)\n }\n\n def evaluate(eventSel: UInt): Bool = {\n val (set, mask) = decode(eventSel)\n val sets = for (e <- eventSets) yield {\n require(e.hits.getWidth <= mask.getWidth, s\"too many events ${e.hits.getWidth} wider than mask ${mask.getWidth}\")\n e check mask\n }\n sets(set)\n }\n\n def cover() = eventSets.foreach { _.withCovers }\n\n private def eventSetIdBits = log2Ceil(eventSets.size)\n private def maxEventSetIdBits = 8\n\n require(eventSetIdBits <= maxEventSetIdBits)\n}\n\nclass SuperscalarEventSets(val eventSets: Seq[(Seq[EventSet], (UInt, UInt) => UInt)]) {\n def evaluate(eventSel: UInt): UInt = {\n val (set, mask) = decode(eventSel)\n val sets = for ((sets, reducer) <- eventSets) yield {\n sets.map { set =>\n require(set.hits.getWidth <= mask.getWidth, s\"too many events ${set.hits.getWidth} wider than mask ${mask.getWidth}\")\n set.check(mask)\n }.reduce(reducer)\n }\n val zeroPadded = sets.padTo(1 << eventSetIdBits, 0.U)\n zeroPadded(set)\n }\n\n def toScalarEventSets: EventSets = new EventSets(eventSets.map(_._1.head))\n\n def cover(): Unit = { eventSets.foreach(_._1.foreach(_.withCovers)) }\n\n private def decode(counter: UInt): (UInt, UInt) = {\n require(eventSets.size <= (1 << maxEventSetIdBits))\n require(eventSetIdBits > 0)\n (counter(eventSetIdBits-1, 0), counter >> maxEventSetIdBits)\n }\n\n private def eventSetIdBits = log2Ceil(eventSets.size)\n private def maxEventSetIdBits = 8\n\n require(eventSets.forall(s => s._1.forall(_.size == s._1.head.size)))\n require(eventSetIdBits <= maxEventSetIdBits)\n}\nFile consts.scala:\n//******************************************************************************\n// Copyright (c) 2011 - 2018, The Regents of the University of California (Regents).\n// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.\n//------------------------------------------------------------------------------\n\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n// RISCV Processor Constants\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n\npackage boom.v3.common.constants\n\nimport chisel3._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config.Parameters\nimport freechips.rocketchip.util.Str\nimport freechips.rocketchip.rocket.RVCExpander\n\n/**\n * Mixin for issue queue types\n */\ntrait IQType\n{\n val IQT_SZ = 3\n val IQT_INT = 1.U(IQT_SZ.W)\n val IQT_MEM = 2.U(IQT_SZ.W)\n val IQT_FP = 4.U(IQT_SZ.W)\n\n val IQT_MFP = 6.U(IQT_SZ.W)\n}\n\n\n/**\n * Mixin for scalar operation constants\n */\ntrait ScalarOpConstants\n{\n val X = BitPat(\"b?\")\n val Y = BitPat(\"b1\")\n val N = BitPat(\"b0\")\n\n //************************************\n // Extra Constants\n\n // Which branch predictor predicted us\n val BSRC_SZ = 2\n val BSRC_1 = 0.U(BSRC_SZ.W) // 1-cycle branch pred\n val BSRC_2 = 1.U(BSRC_SZ.W) // 2-cycle branch pred\n val BSRC_3 = 2.U(BSRC_SZ.W) // 3-cycle branch pred\n val BSRC_C = 3.U(BSRC_SZ.W) // core branch resolution\n\n //************************************\n // Control Signals\n\n // CFI types\n val CFI_SZ = 3\n val CFI_X = 0.U(CFI_SZ.W) // Not a CFI instruction\n val CFI_BR = 1.U(CFI_SZ.W) // Branch\n val CFI_JAL = 2.U(CFI_SZ.W) // JAL\n val CFI_JALR = 3.U(CFI_SZ.W) // JALR\n\n // PC Select Signal\n val PC_PLUS4 = 0.U(2.W) // PC + 4\n val PC_BRJMP = 1.U(2.W) // brjmp_target\n val PC_JALR = 2.U(2.W) // jump_reg_target\n\n // Branch Type\n val BR_N = 0.U(4.W) // Next\n val BR_NE = 1.U(4.W) // Branch on NotEqual\n val BR_EQ = 2.U(4.W) // Branch on Equal\n val BR_GE = 3.U(4.W) // Branch on Greater/Equal\n val BR_GEU = 4.U(4.W) // Branch on Greater/Equal Unsigned\n val BR_LT = 5.U(4.W) // Branch on Less Than\n val BR_LTU = 6.U(4.W) // Branch on Less Than Unsigned\n val BR_J = 7.U(4.W) // Jump\n val BR_JR = 8.U(4.W) // Jump Register\n\n // RS1 Operand Select Signal\n val OP1_RS1 = 0.U(2.W) // Register Source #1\n val OP1_ZERO= 1.U(2.W)\n val OP1_PC = 2.U(2.W)\n val OP1_X = BitPat(\"b??\")\n\n // RS2 Operand Select Signal\n val OP2_RS2 = 0.U(3.W) // Register Source #2\n val OP2_IMM = 1.U(3.W) // immediate\n val OP2_ZERO= 2.U(3.W) // constant 0\n val OP2_NEXT= 3.U(3.W) // constant 2/4 (for PC+2/4)\n val OP2_IMMC= 4.U(3.W) // for CSR imm found in RS1\n val OP2_X = BitPat(\"b???\")\n\n // Register File Write Enable Signal\n val REN_0 = false.B\n val REN_1 = true.B\n\n // Is 32b Word or 64b Doubldword?\n val SZ_DW = 1\n val DW_X = true.B // Bool(xLen==64)\n val DW_32 = false.B\n val DW_64 = true.B\n val DW_XPR = true.B // Bool(xLen==64)\n\n // Memory Enable Signal\n val MEN_0 = false.B\n val MEN_1 = true.B\n val MEN_X = false.B\n\n // Immediate Extend Select\n val IS_I = 0.U(3.W) // I-Type (LD,ALU)\n val IS_S = 1.U(3.W) // S-Type (ST)\n val IS_B = 2.U(3.W) // SB-Type (BR)\n val IS_U = 3.U(3.W) // U-Type (LUI/AUIPC)\n val IS_J = 4.U(3.W) // UJ-Type (J/JAL)\n val IS_X = BitPat(\"b???\")\n\n // Decode Stage Control Signals\n val RT_FIX = 0.U(2.W)\n val RT_FLT = 1.U(2.W)\n val RT_PAS = 3.U(2.W) // pass-through (prs1 := lrs1, etc)\n val RT_X = 2.U(2.W) // not-a-register (but shouldn't get a busy-bit, etc.)\n // TODO rename RT_NAR\n\n // Micro-op opcodes\n // TODO change micro-op opcodes into using enum\n val UOPC_SZ = 7\n val uopX = BitPat.dontCare(UOPC_SZ)\n val uopNOP = 0.U(UOPC_SZ.W)\n val uopLD = 1.U(UOPC_SZ.W)\n val uopSTA = 2.U(UOPC_SZ.W) // store address generation\n val uopSTD = 3.U(UOPC_SZ.W) // store data generation\n val uopLUI = 4.U(UOPC_SZ.W)\n\n val uopADDI = 5.U(UOPC_SZ.W)\n val uopANDI = 6.U(UOPC_SZ.W)\n val uopORI = 7.U(UOPC_SZ.W)\n val uopXORI = 8.U(UOPC_SZ.W)\n val uopSLTI = 9.U(UOPC_SZ.W)\n val uopSLTIU= 10.U(UOPC_SZ.W)\n val uopSLLI = 11.U(UOPC_SZ.W)\n val uopSRAI = 12.U(UOPC_SZ.W)\n val uopSRLI = 13.U(UOPC_SZ.W)\n\n val uopSLL = 14.U(UOPC_SZ.W)\n val uopADD = 15.U(UOPC_SZ.W)\n val uopSUB = 16.U(UOPC_SZ.W)\n val uopSLT = 17.U(UOPC_SZ.W)\n val uopSLTU = 18.U(UOPC_SZ.W)\n val uopAND = 19.U(UOPC_SZ.W)\n val uopOR = 20.U(UOPC_SZ.W)\n val uopXOR = 21.U(UOPC_SZ.W)\n val uopSRA = 22.U(UOPC_SZ.W)\n val uopSRL = 23.U(UOPC_SZ.W)\n\n val uopBEQ = 24.U(UOPC_SZ.W)\n val uopBNE = 25.U(UOPC_SZ.W)\n val uopBGE = 26.U(UOPC_SZ.W)\n val uopBGEU = 27.U(UOPC_SZ.W)\n val uopBLT = 28.U(UOPC_SZ.W)\n val uopBLTU = 29.U(UOPC_SZ.W)\n val uopCSRRW= 30.U(UOPC_SZ.W)\n val uopCSRRS= 31.U(UOPC_SZ.W)\n val uopCSRRC= 32.U(UOPC_SZ.W)\n val uopCSRRWI=33.U(UOPC_SZ.W)\n val uopCSRRSI=34.U(UOPC_SZ.W)\n val uopCSRRCI=35.U(UOPC_SZ.W)\n\n val uopJ = 36.U(UOPC_SZ.W)\n val uopJAL = 37.U(UOPC_SZ.W)\n val uopJALR = 38.U(UOPC_SZ.W)\n val uopAUIPC= 39.U(UOPC_SZ.W)\n\n//val uopSRET = 40.U(UOPC_SZ.W)\n val uopCFLSH= 41.U(UOPC_SZ.W)\n val uopFENCE= 42.U(UOPC_SZ.W)\n\n val uopADDIW= 43.U(UOPC_SZ.W)\n val uopADDW = 44.U(UOPC_SZ.W)\n val uopSUBW = 45.U(UOPC_SZ.W)\n val uopSLLIW= 46.U(UOPC_SZ.W)\n val uopSLLW = 47.U(UOPC_SZ.W)\n val uopSRAIW= 48.U(UOPC_SZ.W)\n val uopSRAW = 49.U(UOPC_SZ.W)\n val uopSRLIW= 50.U(UOPC_SZ.W)\n val uopSRLW = 51.U(UOPC_SZ.W)\n val uopMUL = 52.U(UOPC_SZ.W)\n val uopMULH = 53.U(UOPC_SZ.W)\n val uopMULHU= 54.U(UOPC_SZ.W)\n val uopMULHSU=55.U(UOPC_SZ.W)\n val uopMULW = 56.U(UOPC_SZ.W)\n val uopDIV = 57.U(UOPC_SZ.W)\n val uopDIVU = 58.U(UOPC_SZ.W)\n val uopREM = 59.U(UOPC_SZ.W)\n val uopREMU = 60.U(UOPC_SZ.W)\n val uopDIVW = 61.U(UOPC_SZ.W)\n val uopDIVUW= 62.U(UOPC_SZ.W)\n val uopREMW = 63.U(UOPC_SZ.W)\n val uopREMUW= 64.U(UOPC_SZ.W)\n\n val uopFENCEI = 65.U(UOPC_SZ.W)\n // = 66.U(UOPC_SZ.W)\n val uopAMO_AG = 67.U(UOPC_SZ.W) // AMO-address gen (use normal STD for datagen)\n\n val uopFMV_W_X = 68.U(UOPC_SZ.W)\n val uopFMV_D_X = 69.U(UOPC_SZ.W)\n val uopFMV_X_W = 70.U(UOPC_SZ.W)\n val uopFMV_X_D = 71.U(UOPC_SZ.W)\n\n val uopFSGNJ_S = 72.U(UOPC_SZ.W)\n val uopFSGNJ_D = 73.U(UOPC_SZ.W)\n\n val uopFCVT_S_D = 74.U(UOPC_SZ.W)\n val uopFCVT_D_S = 75.U(UOPC_SZ.W)\n\n val uopFCVT_S_X = 76.U(UOPC_SZ.W)\n val uopFCVT_D_X = 77.U(UOPC_SZ.W)\n\n val uopFCVT_X_S = 78.U(UOPC_SZ.W)\n val uopFCVT_X_D = 79.U(UOPC_SZ.W)\n\n val uopCMPR_S = 80.U(UOPC_SZ.W)\n val uopCMPR_D = 81.U(UOPC_SZ.W)\n\n val uopFCLASS_S = 82.U(UOPC_SZ.W)\n val uopFCLASS_D = 83.U(UOPC_SZ.W)\n\n val uopFMINMAX_S = 84.U(UOPC_SZ.W)\n val uopFMINMAX_D = 85.U(UOPC_SZ.W)\n\n // = 86.U(UOPC_SZ.W)\n val uopFADD_S = 87.U(UOPC_SZ.W)\n val uopFSUB_S = 88.U(UOPC_SZ.W)\n val uopFMUL_S = 89.U(UOPC_SZ.W)\n val uopFADD_D = 90.U(UOPC_SZ.W)\n val uopFSUB_D = 91.U(UOPC_SZ.W)\n val uopFMUL_D = 92.U(UOPC_SZ.W)\n\n val uopFMADD_S = 93.U(UOPC_SZ.W)\n val uopFMSUB_S = 94.U(UOPC_SZ.W)\n val uopFNMADD_S = 95.U(UOPC_SZ.W)\n val uopFNMSUB_S = 96.U(UOPC_SZ.W)\n val uopFMADD_D = 97.U(UOPC_SZ.W)\n val uopFMSUB_D = 98.U(UOPC_SZ.W)\n val uopFNMADD_D = 99.U(UOPC_SZ.W)\n val uopFNMSUB_D = 100.U(UOPC_SZ.W)\n\n val uopFDIV_S = 101.U(UOPC_SZ.W)\n val uopFDIV_D = 102.U(UOPC_SZ.W)\n val uopFSQRT_S = 103.U(UOPC_SZ.W)\n val uopFSQRT_D = 104.U(UOPC_SZ.W)\n\n val uopWFI = 105.U(UOPC_SZ.W) // pass uop down the CSR pipeline\n val uopERET = 106.U(UOPC_SZ.W) // pass uop down the CSR pipeline, also is ERET\n val uopSFENCE = 107.U(UOPC_SZ.W)\n\n val uopROCC = 108.U(UOPC_SZ.W)\n\n val uopMOV = 109.U(UOPC_SZ.W) // conditional mov decoded from \"add rd, x0, rs2\"\n\n // The Bubble Instruction (Machine generated NOP)\n // Insert (XOR x0,x0,x0) which is different from software compiler\n // generated NOPs which are (ADDI x0, x0, 0).\n // Reasoning for this is to let visualizers and stat-trackers differentiate\n // between software NOPs and machine-generated Bubbles in the pipeline.\n val BUBBLE = (0x4033).U(32.W)\n\n def NullMicroOp()(implicit p: Parameters): boom.v3.common.MicroOp = {\n val uop = Wire(new boom.v3.common.MicroOp)\n uop := DontCare // Overridden in the following lines\n uop.uopc := uopNOP // maybe not required, but helps on asserts that try to catch spurious behavior\n uop.bypassable := false.B\n uop.fp_val := false.B\n uop.uses_stq := false.B\n uop.uses_ldq := false.B\n uop.pdst := 0.U\n uop.dst_rtype := RT_X\n\n val cs = Wire(new boom.v3.common.CtrlSignals())\n cs := DontCare // Overridden in the following lines\n cs.br_type := BR_N\n cs.csr_cmd := freechips.rocketchip.rocket.CSR.N\n cs.is_load := false.B\n cs.is_sta := false.B\n cs.is_std := false.B\n\n uop.ctrl := cs\n uop\n }\n}\n\n/**\n * Mixin for RISCV constants\n */\ntrait RISCVConstants\n{\n // abstract out instruction decode magic numbers\n val RD_MSB = 11\n val RD_LSB = 7\n val RS1_MSB = 19\n val RS1_LSB = 15\n val RS2_MSB = 24\n val RS2_LSB = 20\n val RS3_MSB = 31\n val RS3_LSB = 27\n\n val CSR_ADDR_MSB = 31\n val CSR_ADDR_LSB = 20\n val CSR_ADDR_SZ = 12\n\n // location of the fifth bit in the shamt (for checking for illegal ops for SRAIW,etc.)\n val SHAMT_5_BIT = 25\n val LONGEST_IMM_SZ = 20\n val X0 = 0.U\n val RA = 1.U // return address register\n\n // memory consistency model\n // The C/C++ atomics MCM requires that two loads to the same address maintain program order.\n // The Cortex A9 does NOT enforce load/load ordering (which leads to buggy behavior).\n val MCM_ORDER_DEPENDENT_LOADS = true\n\n val jal_opc = (0x6f).U\n val jalr_opc = (0x67).U\n\n def GetUop(inst: UInt): UInt = inst(6,0)\n def GetRd (inst: UInt): UInt = inst(RD_MSB,RD_LSB)\n def GetRs1(inst: UInt): UInt = inst(RS1_MSB,RS1_LSB)\n\n def ExpandRVC(inst: UInt)(implicit p: Parameters): UInt = {\n val rvc_exp = Module(new RVCExpander)\n rvc_exp.io.in := inst\n Mux(rvc_exp.io.rvc, rvc_exp.io.out.bits, inst)\n }\n\n // Note: Accepts only EXPANDED rvc instructions\n def ComputeBranchTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = {\n val b_imm32 = Cat(Fill(20,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W))\n ((pc.asSInt + b_imm32.asSInt).asSInt & (-2).S).asUInt\n }\n\n // Note: Accepts only EXPANDED rvc instructions\n def ComputeJALTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = {\n val j_imm32 = Cat(Fill(12,inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W))\n ((pc.asSInt + j_imm32.asSInt).asSInt & (-2).S).asUInt\n }\n\n // Note: Accepts only EXPANDED rvc instructions\n def GetCfiType(inst: UInt)(implicit p: Parameters): UInt = {\n val bdecode = Module(new boom.v3.exu.BranchDecode)\n bdecode.io.inst := inst\n bdecode.io.pc := 0.U\n bdecode.io.out.cfi_type\n }\n}\n\n/**\n * Mixin for exception cause constants\n */\ntrait ExcCauseConstants\n{\n // a memory disambigious misspeculation occurred\n val MINI_EXCEPTION_MEM_ORDERING = 16.U\n val MINI_EXCEPTION_CSR_REPLAY = 17.U\n\n require (!freechips.rocketchip.rocket.Causes.all.contains(16))\n require (!freechips.rocketchip.rocket.Causes.all.contains(17))\n}\nFile frontend.scala:\n//******************************************************************************\n// Copyright (c) 2017 - 2019, The Regents of the University of California (Regents).\n// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.\n//------------------------------------------------------------------------------\n\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n// Frontend\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n\npackage boom.v3.ifu\n\nimport chisel3._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config._\nimport freechips.rocketchip.subsystem._\nimport freechips.rocketchip.diplomacy._\nimport freechips.rocketchip.rocket._\nimport freechips.rocketchip.tilelink._\nimport freechips.rocketchip.tile._\nimport freechips.rocketchip.util._\nimport freechips.rocketchip.util.property._\n\nimport boom.v3.common._\nimport boom.v3.exu.{CommitExceptionSignals, BranchDecode, BrUpdateInfo, BranchDecodeSignals}\nimport boom.v3.util._\n\n\nclass FrontendResp(implicit p: Parameters) extends BoomBundle()(p) {\n val pc = UInt(vaddrBitsExtended.W) // ID stage PC\n val data = UInt((fetchWidth * coreInstBits).W)\n val mask = UInt(fetchWidth.W)\n val xcpt = new FrontendExceptions\n val ghist = new GlobalHistory\n\n // fsrc provides the prediction FROM a branch in this packet\n // tsrc provides the prediction TO this packet\n val fsrc = UInt(BSRC_SZ.W)\n val tsrc = UInt(BSRC_SZ.W)\n}\n\nclass GlobalHistory(implicit p: Parameters) extends BoomBundle()(p)\n with HasBoomFrontendParameters\n{\n // For the dual banked case, each bank ignores the contribution of the\n // last bank to the history. Thus we have to track the most recent update to the\n // history in that case\n val old_history = UInt(globalHistoryLength.W)\n\n val current_saw_branch_not_taken = Bool()\n\n val new_saw_branch_not_taken = Bool()\n val new_saw_branch_taken = Bool()\n\n val ras_idx = UInt(log2Ceil(nRasEntries).W)\n\n def histories(bank: Int) = {\n if (nBanks == 1) {\n old_history\n } else {\n require(nBanks == 2)\n if (bank == 0) {\n old_history\n } else {\n Mux(new_saw_branch_taken , old_history << 1 | 1.U,\n Mux(new_saw_branch_not_taken , old_history << 1,\n old_history))\n }\n }\n }\n\n def ===(other: GlobalHistory): Bool = {\n ((old_history === other.old_history) &&\n (new_saw_branch_not_taken === other.new_saw_branch_not_taken) &&\n (new_saw_branch_taken === other.new_saw_branch_taken)\n )\n }\n def =/=(other: GlobalHistory): Bool = !(this === other)\n\n def update(branches: UInt, cfi_taken: Bool, cfi_is_br: Bool, cfi_idx: UInt,\n cfi_valid: Bool, addr: UInt,\n cfi_is_call: Bool, cfi_is_ret: Bool): GlobalHistory = {\n val cfi_idx_fixed = cfi_idx(log2Ceil(fetchWidth)-1,0)\n val cfi_idx_oh = UIntToOH(cfi_idx_fixed)\n val new_history = Wire(new GlobalHistory)\n\n val not_taken_branches = branches & Mux(cfi_valid,\n MaskLower(cfi_idx_oh) & ~Mux(cfi_is_br && cfi_taken, cfi_idx_oh, 0.U(fetchWidth.W)),\n ~(0.U(fetchWidth.W)))\n\n if (nBanks == 1) {\n // In the single bank case every bank sees the history including the previous bank\n new_history := DontCare\n new_history.current_saw_branch_not_taken := false.B\n val saw_not_taken_branch = not_taken_branches =/= 0.U || current_saw_branch_not_taken\n new_history.old_history := Mux(cfi_is_br && cfi_taken && cfi_valid , histories(0) << 1 | 1.U,\n Mux(saw_not_taken_branch , histories(0) << 1,\n histories(0)))\n } else {\n // In the two bank case every bank ignore the history added by the previous bank\n val base = histories(1)\n val cfi_in_bank_0 = cfi_valid && cfi_taken && cfi_idx_fixed < bankWidth.U\n val ignore_second_bank = cfi_in_bank_0 || mayNotBeDualBanked(addr)\n\n val first_bank_saw_not_taken = not_taken_branches(bankWidth-1,0) =/= 0.U || current_saw_branch_not_taken\n new_history.current_saw_branch_not_taken := false.B\n when (ignore_second_bank) {\n new_history.old_history := histories(1)\n new_history.new_saw_branch_not_taken := first_bank_saw_not_taken\n new_history.new_saw_branch_taken := cfi_is_br && cfi_in_bank_0\n } .otherwise {\n new_history.old_history := Mux(cfi_is_br && cfi_in_bank_0 , histories(1) << 1 | 1.U,\n Mux(first_bank_saw_not_taken , histories(1) << 1,\n histories(1)))\n\n new_history.new_saw_branch_not_taken := not_taken_branches(fetchWidth-1,bankWidth) =/= 0.U\n new_history.new_saw_branch_taken := cfi_valid && cfi_taken && cfi_is_br && !cfi_in_bank_0\n\n }\n }\n new_history.ras_idx := Mux(cfi_valid && cfi_is_call, WrapInc(ras_idx, nRasEntries),\n Mux(cfi_valid && cfi_is_ret , WrapDec(ras_idx, nRasEntries), ras_idx))\n new_history\n }\n\n}\n\n/**\n * Parameters to manage a L1 Banked ICache\n */\ntrait HasBoomFrontendParameters extends HasL1ICacheParameters\n{\n // How many banks does the ICache use?\n val nBanks = if (cacheParams.fetchBytes <= 8) 1 else 2\n // How many bytes wide is a bank?\n val bankBytes = fetchBytes/nBanks\n\n val bankWidth = fetchWidth/nBanks\n\n require(nBanks == 1 || nBanks == 2)\n\n\n\n // How many \"chunks\"/interleavings make up a cache line?\n val numChunks = cacheParams.blockBytes / bankBytes\n\n // Which bank is the address pointing to?\n def bank(addr: UInt) = if (nBanks == 2) addr(log2Ceil(bankBytes)) else 0.U\n def isLastBankInBlock(addr: UInt) = {\n (nBanks == 2).B && addr(blockOffBits-1, log2Ceil(bankBytes)) === (numChunks-1).U\n }\n def mayNotBeDualBanked(addr: UInt) = {\n require(nBanks == 2)\n isLastBankInBlock(addr)\n }\n\n def blockAlign(addr: UInt) = ~(~addr | (cacheParams.blockBytes-1).U)\n def bankAlign(addr: UInt) = ~(~addr | (bankBytes-1).U)\n\n def fetchIdx(addr: UInt) = addr >> log2Ceil(fetchBytes)\n\n def nextBank(addr: UInt) = bankAlign(addr) + bankBytes.U\n def nextFetch(addr: UInt) = {\n if (nBanks == 1) {\n bankAlign(addr) + bankBytes.U\n } else {\n require(nBanks == 2)\n bankAlign(addr) + Mux(mayNotBeDualBanked(addr), bankBytes.U, fetchBytes.U)\n }\n }\n\n def fetchMask(addr: UInt) = {\n val idx = addr.extract(log2Ceil(fetchWidth)+log2Ceil(coreInstBytes)-1, log2Ceil(coreInstBytes))\n if (nBanks == 1) {\n ((1 << fetchWidth)-1).U << idx\n } else {\n val shamt = idx.extract(log2Ceil(fetchWidth)-2, 0)\n val end_mask = Mux(mayNotBeDualBanked(addr), Fill(fetchWidth/2, 1.U), Fill(fetchWidth, 1.U))\n ((1 << fetchWidth)-1).U << shamt & end_mask\n }\n }\n\n def bankMask(addr: UInt) = {\n val idx = addr.extract(log2Ceil(fetchWidth)+log2Ceil(coreInstBytes)-1, log2Ceil(coreInstBytes))\n if (nBanks == 1) {\n 1.U(1.W)\n } else {\n Mux(mayNotBeDualBanked(addr), 1.U(2.W), 3.U(2.W))\n }\n }\n}\n\n\n\n/**\n * Bundle passed into the FetchBuffer and used to combine multiple\n * relevant signals together.\n */\nclass FetchBundle(implicit p: Parameters) extends BoomBundle\n with HasBoomFrontendParameters\n{\n val pc = UInt(vaddrBitsExtended.W)\n val next_pc = UInt(vaddrBitsExtended.W)\n val edge_inst = Vec(nBanks, Bool()) // True if 1st instruction in this bundle is pc - 2\n val insts = Vec(fetchWidth, Bits(32.W))\n val exp_insts = Vec(fetchWidth, Bits(32.W))\n\n // Information for sfb folding\n // NOTE: This IS NOT equivalent to uop.pc_lob, that gets calculated in the FB\n val sfbs = Vec(fetchWidth, Bool())\n val sfb_masks = Vec(fetchWidth, UInt((2*fetchWidth).W))\n val sfb_dests = Vec(fetchWidth, UInt((1+log2Ceil(fetchBytes)).W))\n val shadowable_mask = Vec(fetchWidth, Bool())\n val shadowed_mask = Vec(fetchWidth, Bool())\n\n val cfi_idx = Valid(UInt(log2Ceil(fetchWidth).W))\n val cfi_type = UInt(CFI_SZ.W)\n val cfi_is_call = Bool()\n val cfi_is_ret = Bool()\n val cfi_npc_plus4 = Bool()\n\n val ras_top = UInt(vaddrBitsExtended.W)\n\n val ftq_idx = UInt(log2Ceil(ftqSz).W)\n val mask = UInt(fetchWidth.W) // mark which words are valid instructions\n\n val br_mask = UInt(fetchWidth.W)\n\n val ghist = new GlobalHistory\n val lhist = Vec(nBanks, UInt(localHistoryLength.W))\n\n val xcpt_pf_if = Bool() // I-TLB miss (instruction fetch fault).\n val xcpt_ae_if = Bool() // Access exception.\n\n val bp_debug_if_oh= Vec(fetchWidth, Bool())\n val bp_xcpt_if_oh = Vec(fetchWidth, Bool())\n\n val end_half = Valid(UInt(16.W))\n\n\n val bpd_meta = Vec(nBanks, UInt())\n\n // Source of the prediction from this bundle\n val fsrc = UInt(BSRC_SZ.W)\n // Source of the prediction to this bundle\n val tsrc = UInt(BSRC_SZ.W)\n}\n\n\n\n/**\n * IO for the BOOM Frontend to/from the CPU\n */\nclass BoomFrontendIO(implicit p: Parameters) extends BoomBundle\n{\n // Give the backend a packet of instructions.\n val fetchpacket = Flipped(new DecoupledIO(new FetchBufferResp))\n\n // 1 for xcpt/jalr/auipc/flush\n val get_pc = Flipped(Vec(2, new GetPCFromFtqIO()))\n val debug_ftq_idx = Output(Vec(coreWidth, UInt(log2Ceil(ftqSz).W)))\n val debug_fetch_pc = Input(Vec(coreWidth, UInt(vaddrBitsExtended.W)))\n\n // Breakpoint info\n val status = Output(new MStatus)\n val bp = Output(Vec(nBreakpoints, new BP))\n val mcontext = Output(UInt(coreParams.mcontextWidth.W))\n val scontext = Output(UInt(coreParams.scontextWidth.W))\n\n val sfence = Valid(new SFenceReq)\n\n val brupdate = Output(new BrUpdateInfo)\n\n // Redirects change the PC\n val redirect_flush = Output(Bool()) // Flush and hang the frontend?\n val redirect_val = Output(Bool()) // Redirect the frontend?\n val redirect_pc = Output(UInt()) // Where do we redirect to?\n val redirect_ftq_idx = Output(UInt()) // Which ftq entry should we reset to?\n val redirect_ghist = Output(new GlobalHistory) // What are we setting as the global history?\n\n val commit = Valid(UInt(ftqSz.W))\n\n val flush_icache = Output(Bool())\n\n val perf = Input(new FrontendPerfEvents)\n}\n\n/**\n * Top level Frontend class\n *\n * @param icacheParams parameters for the icache\n * @param hartid id for the hardware thread of the core\n */\nclass BoomFrontend(val icacheParams: ICacheParams, staticIdForMetadataUseOnly: Int)(implicit p: Parameters) extends LazyModule\n{\n lazy val module = new BoomFrontendModule(this)\n val icache = LazyModule(new boom.v3.ifu.ICache(icacheParams, staticIdForMetadataUseOnly))\n val masterNode = icache.masterNode\n val resetVectorSinkNode = BundleBridgeSink[UInt](Some(() =>\n UInt(masterNode.edges.out.head.bundle.addressBits.W)))\n}\n\n/**\n * Bundle wrapping the IO for the Frontend as a whole\n *\n * @param outer top level Frontend class\n */\nclass BoomFrontendBundle(val outer: BoomFrontend) extends CoreBundle()(outer.p)\n{\n val cpu = Flipped(new BoomFrontendIO())\n val ptw = new TLBPTWIO()\n}\n\n/**\n * Main Frontend module that connects the icache, TLB, fetch controller,\n * and branch prediction pipeline together.\n *\n * @param outer top level Frontend class\n */\nclass BoomFrontendModule(outer: BoomFrontend) extends LazyModuleImp(outer)\n with HasBoomCoreParameters\n with HasBoomFrontendParameters\n{\n val io = IO(new BoomFrontendBundle(outer))\n val io_reset_vector = outer.resetVectorSinkNode.bundle\n implicit val edge = outer.masterNode.edges.out(0)\n require(fetchWidth*coreInstBytes == outer.icacheParams.fetchBytes)\n\n val bpd = Module(new BranchPredictor)\n bpd.io.f3_fire := false.B\n val ras = Module(new BoomRAS)\n\n val icache = outer.icache.module\n icache.io.invalidate := io.cpu.flush_icache\n val tlb = Module(new TLB(true, log2Ceil(fetchBytes), TLBConfig(nTLBSets, nTLBWays)))\n io.ptw <> tlb.io.ptw\n io.cpu.perf.tlbMiss := io.ptw.req.fire\n io.cpu.perf.acquire := icache.io.perf.acquire\n\n // --------------------------------------------------------\n // **** NextPC Select (F0) ****\n // Send request to ICache\n // --------------------------------------------------------\n\n val s0_vpc = WireInit(0.U(vaddrBitsExtended.W))\n val s0_ghist = WireInit((0.U).asTypeOf(new GlobalHistory))\n val s0_tsrc = WireInit(0.U(BSRC_SZ.W))\n val s0_valid = WireInit(false.B)\n val s0_is_replay = WireInit(false.B)\n val s0_is_sfence = WireInit(false.B)\n val s0_replay_resp = Wire(new TLBResp(log2Ceil(fetchBytes)))\n val s0_replay_bpd_resp = Wire(new BranchPredictionBundle)\n val s0_replay_ppc = Wire(UInt())\n val s0_s1_use_f3_bpd_resp = WireInit(false.B)\n\n\n\n\n when (RegNext(reset.asBool) && !reset.asBool) {\n s0_valid := true.B\n s0_vpc := io_reset_vector\n s0_ghist := (0.U).asTypeOf(new GlobalHistory)\n s0_tsrc := BSRC_C\n }\n\n icache.io.req.valid := s0_valid\n icache.io.req.bits.addr := s0_vpc\n\n bpd.io.f0_req.valid := s0_valid\n bpd.io.f0_req.bits.pc := s0_vpc\n bpd.io.f0_req.bits.ghist := s0_ghist\n\n // --------------------------------------------------------\n // **** ICache Access (F1) ****\n // Translate VPC\n // --------------------------------------------------------\n val s1_vpc = RegNext(s0_vpc)\n val s1_valid = RegNext(s0_valid, false.B)\n val s1_ghist = RegNext(s0_ghist)\n val s1_is_replay = RegNext(s0_is_replay)\n val s1_is_sfence = RegNext(s0_is_sfence)\n val f1_clear = WireInit(false.B)\n val s1_tsrc = RegNext(s0_tsrc)\n tlb.io.req.valid := (s1_valid && !s1_is_replay && !f1_clear) || s1_is_sfence\n tlb.io.req.bits.cmd := DontCare\n tlb.io.req.bits.vaddr := s1_vpc\n tlb.io.req.bits.passthrough := false.B\n tlb.io.req.bits.size := log2Ceil(coreInstBytes * fetchWidth).U\n tlb.io.req.bits.v := io.ptw.status.v\n tlb.io.req.bits.prv := io.ptw.status.prv\n tlb.io.sfence := RegNext(io.cpu.sfence)\n tlb.io.kill := false.B\n\n val s1_tlb_miss = !s1_is_replay && tlb.io.resp.miss\n val s1_tlb_resp = Mux(s1_is_replay, RegNext(s0_replay_resp), tlb.io.resp)\n val s1_ppc = Mux(s1_is_replay, RegNext(s0_replay_ppc), tlb.io.resp.paddr)\n val s1_bpd_resp = bpd.io.resp.f1\n\n icache.io.s1_paddr := s1_ppc\n icache.io.s1_kill := tlb.io.resp.miss || f1_clear\n\n val f1_mask = fetchMask(s1_vpc)\n val f1_redirects = (0 until fetchWidth) map { i =>\n s1_valid && f1_mask(i) && s1_bpd_resp.preds(i).predicted_pc.valid &&\n (s1_bpd_resp.preds(i).is_jal ||\n (s1_bpd_resp.preds(i).is_br && s1_bpd_resp.preds(i).taken))\n }\n val f1_redirect_idx = PriorityEncoder(f1_redirects)\n val f1_do_redirect = f1_redirects.reduce(_||_) && useBPD.B\n val f1_targs = s1_bpd_resp.preds.map(_.predicted_pc.bits)\n val f1_predicted_target = Mux(f1_do_redirect,\n f1_targs(f1_redirect_idx),\n nextFetch(s1_vpc))\n\n val f1_predicted_ghist = s1_ghist.update(\n s1_bpd_resp.preds.map(p => p.is_br && p.predicted_pc.valid).asUInt & f1_mask,\n s1_bpd_resp.preds(f1_redirect_idx).taken && f1_do_redirect,\n s1_bpd_resp.preds(f1_redirect_idx).is_br,\n f1_redirect_idx,\n f1_do_redirect,\n s1_vpc,\n false.B,\n false.B)\n\n when (s1_valid && !s1_tlb_miss) {\n // Stop fetching on fault\n s0_valid := !(s1_tlb_resp.ae.inst || s1_tlb_resp.pf.inst)\n s0_tsrc := BSRC_1\n s0_vpc := f1_predicted_target\n s0_ghist := f1_predicted_ghist\n s0_is_replay := false.B\n }\n\n // --------------------------------------------------------\n // **** ICache Response (F2) ****\n // --------------------------------------------------------\n\n val s2_valid = RegNext(s1_valid && !f1_clear, false.B)\n val s2_vpc = RegNext(s1_vpc)\n val s2_ghist = Reg(new GlobalHistory)\n s2_ghist := s1_ghist\n val s2_ppc = RegNext(s1_ppc)\n val s2_tsrc = RegNext(s1_tsrc) // tsrc provides the predictor component which provided the prediction TO this instruction\n val s2_fsrc = WireInit(BSRC_1) // fsrc provides the predictor component which provided the prediction FROM this instruction\n val f2_clear = WireInit(false.B)\n val s2_tlb_resp = RegNext(s1_tlb_resp)\n val s2_tlb_miss = RegNext(s1_tlb_miss)\n val s2_is_replay = RegNext(s1_is_replay) && s2_valid\n val s2_xcpt = s2_valid && (s2_tlb_resp.ae.inst || s2_tlb_resp.pf.inst) && !s2_is_replay\n val f3_ready = Wire(Bool())\n\n icache.io.s2_kill := s2_xcpt\n\n val f2_bpd_resp = bpd.io.resp.f2\n val f2_mask = fetchMask(s2_vpc)\n val f2_redirects = (0 until fetchWidth) map { i =>\n s2_valid && f2_mask(i) && f2_bpd_resp.preds(i).predicted_pc.valid &&\n (f2_bpd_resp.preds(i).is_jal ||\n (f2_bpd_resp.preds(i).is_br && f2_bpd_resp.preds(i).taken))\n }\n val f2_redirect_idx = PriorityEncoder(f2_redirects)\n val f2_targs = f2_bpd_resp.preds.map(_.predicted_pc.bits)\n val f2_do_redirect = f2_redirects.reduce(_||_) && useBPD.B\n val f2_predicted_target = Mux(f2_do_redirect,\n f2_targs(f2_redirect_idx),\n nextFetch(s2_vpc))\n val f2_predicted_ghist = s2_ghist.update(\n f2_bpd_resp.preds.map(p => p.is_br && p.predicted_pc.valid).asUInt & f2_mask,\n f2_bpd_resp.preds(f2_redirect_idx).taken && f2_do_redirect,\n f2_bpd_resp.preds(f2_redirect_idx).is_br,\n f2_redirect_idx,\n f2_do_redirect,\n s2_vpc,\n false.B,\n false.B)\n\n val f2_correct_f1_ghist = s1_ghist =/= f2_predicted_ghist && enableGHistStallRepair.B\n\n when ((s2_valid && !icache.io.resp.valid) ||\n (s2_valid && icache.io.resp.valid && !f3_ready)) {\n s0_valid := (!s2_tlb_resp.ae.inst && !s2_tlb_resp.pf.inst) || s2_is_replay || s2_tlb_miss\n s0_vpc := s2_vpc\n s0_is_replay := s2_valid && icache.io.resp.valid\n // When this is not a replay (it queried the BPDs, we should use f3 resp in the replaying s1)\n s0_s1_use_f3_bpd_resp := !s2_is_replay\n s0_ghist := s2_ghist\n s0_tsrc := s2_tsrc\n f1_clear := true.B\n } .elsewhen (s2_valid && f3_ready) {\n when (s1_valid && s1_vpc === f2_predicted_target && !f2_correct_f1_ghist) {\n // We trust our prediction of what the global history for the next branch should be\n s2_ghist := f2_predicted_ghist\n }\n when ((s1_valid && (s1_vpc =/= f2_predicted_target || f2_correct_f1_ghist)) || !s1_valid) {\n f1_clear := true.B\n\n s0_valid := !((s2_tlb_resp.ae.inst || s2_tlb_resp.pf.inst) && !s2_is_replay)\n s0_vpc := f2_predicted_target\n s0_is_replay := false.B\n s0_ghist := f2_predicted_ghist\n s2_fsrc := BSRC_2\n s0_tsrc := BSRC_2\n }\n }\n s0_replay_bpd_resp := f2_bpd_resp\n s0_replay_resp := s2_tlb_resp\n s0_replay_ppc := s2_ppc\n\n // --------------------------------------------------------\n // **** F3 ****\n // --------------------------------------------------------\n val f3_clear = WireInit(false.B)\n val f3 = withReset(reset.asBool || f3_clear) {\n Module(new Queue(new FrontendResp, 1, pipe=true, flow=false)) }\n\n // Queue up the bpd resp as well, incase f4 backpressures f3\n // This is \"flow\" because the response (enq) arrives in f3, not f2\n val f3_bpd_resp = withReset(reset.asBool || f3_clear) {\n Module(new Queue(new BranchPredictionBundle, 1, pipe=true, flow=true)) }\n\n\n\n\n val f4_ready = Wire(Bool())\n f3_ready := f3.io.enq.ready\n f3.io.enq.valid := (s2_valid && !f2_clear &&\n (icache.io.resp.valid || ((s2_tlb_resp.ae.inst || s2_tlb_resp.pf.inst) && !s2_tlb_miss))\n )\n f3.io.enq.bits.pc := s2_vpc\n f3.io.enq.bits.data := Mux(s2_xcpt, 0.U, icache.io.resp.bits.data)\n f3.io.enq.bits.ghist := s2_ghist\n f3.io.enq.bits.mask := fetchMask(s2_vpc)\n f3.io.enq.bits.xcpt := s2_tlb_resp\n f3.io.enq.bits.fsrc := s2_fsrc\n f3.io.enq.bits.tsrc := s2_tsrc\n\n // RAS takes a cycle to read\n val ras_read_idx = RegInit(0.U(log2Ceil(nRasEntries).W))\n ras.io.read_idx := ras_read_idx\n when (f3.io.enq.fire) {\n ras_read_idx := f3.io.enq.bits.ghist.ras_idx\n ras.io.read_idx := f3.io.enq.bits.ghist.ras_idx\n }\n\n\n // The BPD resp comes in f3\n f3_bpd_resp.io.enq.valid := f3.io.deq.valid && RegNext(f3.io.enq.ready)\n f3_bpd_resp.io.enq.bits := bpd.io.resp.f3\n when (f3_bpd_resp.io.enq.fire) {\n bpd.io.f3_fire := true.B\n }\n\n f3.io.deq.ready := f4_ready\n f3_bpd_resp.io.deq.ready := f4_ready\n\n\n val f3_imemresp = f3.io.deq.bits\n val f3_bank_mask = bankMask(f3_imemresp.pc)\n val f3_data = f3_imemresp.data\n val f3_aligned_pc = bankAlign(f3_imemresp.pc)\n val f3_is_last_bank_in_block = isLastBankInBlock(f3_aligned_pc)\n val f3_is_rvc = Wire(Vec(fetchWidth, Bool()))\n val f3_redirects = Wire(Vec(fetchWidth, Bool()))\n val f3_targs = Wire(Vec(fetchWidth, UInt(vaddrBitsExtended.W)))\n val f3_cfi_types = Wire(Vec(fetchWidth, UInt(CFI_SZ.W)))\n val f3_shadowed_mask = Wire(Vec(fetchWidth, Bool()))\n val f3_fetch_bundle = Wire(new FetchBundle)\n val f3_mask = Wire(Vec(fetchWidth, Bool()))\n val f3_br_mask = Wire(Vec(fetchWidth, Bool()))\n val f3_call_mask = Wire(Vec(fetchWidth, Bool()))\n val f3_ret_mask = Wire(Vec(fetchWidth, Bool()))\n val f3_npc_plus4_mask = Wire(Vec(fetchWidth, Bool()))\n val f3_btb_mispredicts = Wire(Vec(fetchWidth, Bool()))\n f3_fetch_bundle.mask := f3_mask.asUInt\n f3_fetch_bundle.br_mask := f3_br_mask.asUInt\n f3_fetch_bundle.pc := f3_imemresp.pc\n f3_fetch_bundle.ftq_idx := 0.U // This gets assigned later\n f3_fetch_bundle.xcpt_pf_if := f3_imemresp.xcpt.pf.inst\n f3_fetch_bundle.xcpt_ae_if := f3_imemresp.xcpt.ae.inst\n f3_fetch_bundle.fsrc := f3_imemresp.fsrc\n f3_fetch_bundle.tsrc := f3_imemresp.tsrc\n f3_fetch_bundle.shadowed_mask := f3_shadowed_mask\n\n // Tracks trailing 16b of previous fetch packet\n val f3_prev_half = Reg(UInt(16.W))\n // Tracks if last fetchpacket contained a half-inst\n val f3_prev_is_half = RegInit(false.B)\n\n require(fetchWidth >= 4) // Logic gets kind of annoying with fetchWidth = 2\n def isRVC(inst: UInt) = (inst(1,0) =/= 3.U)\n var redirect_found = false.B\n var bank_prev_is_half = f3_prev_is_half\n var bank_prev_half = f3_prev_half\n var last_inst = 0.U(16.W)\n for (b <- 0 until nBanks) {\n val bank_data = f3_data((b+1)*bankWidth*16-1, b*bankWidth*16)\n val bank_mask = Wire(Vec(bankWidth, Bool()))\n val bank_insts = Wire(Vec(bankWidth, UInt(32.W)))\n\n for (w <- 0 until bankWidth) {\n val i = (b * bankWidth) + w\n\n val valid = Wire(Bool())\n val bpu = Module(new BreakpointUnit(nBreakpoints))\n bpu.io.status := io.cpu.status\n bpu.io.bp := io.cpu.bp\n bpu.io.ea := DontCare\n bpu.io.mcontext := io.cpu.mcontext\n bpu.io.scontext := io.cpu.scontext\n\n val brsigs = Wire(new BranchDecodeSignals)\n if (w == 0) {\n val inst0 = Cat(bank_data(15,0), f3_prev_half)\n val inst1 = bank_data(31,0)\n val exp_inst0 = ExpandRVC(inst0)\n val exp_inst1 = ExpandRVC(inst1)\n val pc0 = (f3_aligned_pc + (i << log2Ceil(coreInstBytes)).U - 2.U)\n val pc1 = (f3_aligned_pc + (i << log2Ceil(coreInstBytes)).U)\n\n val bpd_decoder0 = Module(new BranchDecode)\n bpd_decoder0.io.inst := exp_inst0\n bpd_decoder0.io.pc := pc0\n val bpd_decoder1 = Module(new BranchDecode)\n bpd_decoder1.io.inst := exp_inst1\n bpd_decoder1.io.pc := pc1\n\n when (bank_prev_is_half) {\n bank_insts(w) := inst0\n f3_fetch_bundle.insts(i) := inst0\n f3_fetch_bundle.exp_insts(i) := exp_inst0\n bpu.io.pc := pc0\n brsigs := bpd_decoder0.io.out\n f3_fetch_bundle.edge_inst(b) := true.B\n if (b > 0) {\n val inst0b = Cat(bank_data(15,0), last_inst)\n val exp_inst0b = ExpandRVC(inst0b)\n val bpd_decoder0b = Module(new BranchDecode)\n bpd_decoder0b.io.inst := exp_inst0b\n bpd_decoder0b.io.pc := pc0\n\n when (f3_bank_mask(b-1)) {\n bank_insts(w) := inst0b\n f3_fetch_bundle.insts(i) := inst0b\n f3_fetch_bundle.exp_insts(i) := exp_inst0b\n brsigs := bpd_decoder0b.io.out\n }\n }\n } .otherwise {\n bank_insts(w) := inst1\n f3_fetch_bundle.insts(i) := inst1\n f3_fetch_bundle.exp_insts(i) := exp_inst1\n bpu.io.pc := pc1\n brsigs := bpd_decoder1.io.out\n f3_fetch_bundle.edge_inst(b) := false.B\n }\n valid := true.B\n } else {\n val inst = Wire(UInt(32.W))\n val exp_inst = ExpandRVC(inst)\n val pc = f3_aligned_pc + (i << log2Ceil(coreInstBytes)).U\n val bpd_decoder = Module(new BranchDecode)\n bpd_decoder.io.inst := exp_inst\n bpd_decoder.io.pc := pc\n\n bank_insts(w) := inst\n f3_fetch_bundle.insts(i) := inst\n f3_fetch_bundle.exp_insts(i) := exp_inst\n bpu.io.pc := pc\n brsigs := bpd_decoder.io.out\n if (w == 1) {\n // Need special case since 0th instruction may carry over the wrap around\n inst := bank_data(47,16)\n valid := bank_prev_is_half || !(bank_mask(0) && !isRVC(bank_insts(0)))\n } else if (w == bankWidth - 1) {\n inst := Cat(0.U(16.W), bank_data(bankWidth*16-1,(bankWidth-1)*16))\n valid := !((bank_mask(w-1) && !isRVC(bank_insts(w-1))) ||\n !isRVC(inst))\n } else {\n inst := bank_data(w*16+32-1,w*16)\n valid := !(bank_mask(w-1) && !isRVC(bank_insts(w-1)))\n }\n }\n\n f3_is_rvc(i) := isRVC(bank_insts(w))\n\n\n bank_mask(w) := f3.io.deq.valid && f3_imemresp.mask(i) && valid && !redirect_found\n f3_mask (i) := f3.io.deq.valid && f3_imemresp.mask(i) && valid && !redirect_found\n f3_targs (i) := Mux(brsigs.cfi_type === CFI_JALR,\n f3_bpd_resp.io.deq.bits.preds(i).predicted_pc.bits,\n brsigs.target)\n\n // Flush BTB entries for JALs if we mispredict the target\n f3_btb_mispredicts(i) := (brsigs.cfi_type === CFI_JAL && valid &&\n f3_bpd_resp.io.deq.bits.preds(i).predicted_pc.valid &&\n (f3_bpd_resp.io.deq.bits.preds(i).predicted_pc.bits =/= brsigs.target)\n )\n\n\n f3_npc_plus4_mask(i) := (if (w == 0) {\n !f3_is_rvc(i) && !bank_prev_is_half\n } else {\n !f3_is_rvc(i)\n })\n val offset_from_aligned_pc = (\n (i << 1).U((log2Ceil(icBlockBytes)+1).W) +\n brsigs.sfb_offset.bits -\n Mux(bank_prev_is_half && (w == 0).B, 2.U, 0.U)\n )\n val lower_mask = Wire(UInt((2*fetchWidth).W))\n val upper_mask = Wire(UInt((2*fetchWidth).W))\n lower_mask := UIntToOH(i.U)\n upper_mask := UIntToOH(offset_from_aligned_pc(log2Ceil(fetchBytes)+1,1)) << Mux(f3_is_last_bank_in_block, bankWidth.U, 0.U)\n\n f3_fetch_bundle.sfbs(i) := (\n f3_mask(i) &&\n brsigs.sfb_offset.valid &&\n (offset_from_aligned_pc <= Mux(f3_is_last_bank_in_block, (fetchBytes+bankBytes).U,(2*fetchBytes).U))\n )\n f3_fetch_bundle.sfb_masks(i) := ~MaskLower(lower_mask) & ~MaskUpper(upper_mask)\n f3_fetch_bundle.shadowable_mask(i) := (!(f3_fetch_bundle.xcpt_pf_if || f3_fetch_bundle.xcpt_ae_if || bpu.io.debug_if || bpu.io.xcpt_if) &&\n f3_bank_mask(b) &&\n (brsigs.shadowable || !f3_mask(i)))\n f3_fetch_bundle.sfb_dests(i) := offset_from_aligned_pc\n\n // Redirect if\n // 1) its a JAL/JALR (unconditional)\n // 2) the BPD believes this is a branch and says we should take it\n f3_redirects(i) := f3_mask(i) && (\n brsigs.cfi_type === CFI_JAL || brsigs.cfi_type === CFI_JALR ||\n (brsigs.cfi_type === CFI_BR && f3_bpd_resp.io.deq.bits.preds(i).taken && useBPD.B)\n )\n\n f3_br_mask(i) := f3_mask(i) && brsigs.cfi_type === CFI_BR\n f3_cfi_types(i) := brsigs.cfi_type\n f3_call_mask(i) := brsigs.is_call\n f3_ret_mask(i) := brsigs.is_ret\n\n f3_fetch_bundle.bp_debug_if_oh(i) := bpu.io.debug_if\n f3_fetch_bundle.bp_xcpt_if_oh (i) := bpu.io.xcpt_if\n\n redirect_found = redirect_found || f3_redirects(i)\n }\n last_inst = bank_insts(bankWidth-1)(15,0)\n bank_prev_is_half = Mux(f3_bank_mask(b),\n (!(bank_mask(bankWidth-2) && !isRVC(bank_insts(bankWidth-2))) && !isRVC(last_inst)),\n bank_prev_is_half)\n bank_prev_half = Mux(f3_bank_mask(b),\n last_inst(15,0),\n bank_prev_half)\n }\n\n f3_fetch_bundle.cfi_type := f3_cfi_types(f3_fetch_bundle.cfi_idx.bits)\n f3_fetch_bundle.cfi_is_call := f3_call_mask(f3_fetch_bundle.cfi_idx.bits)\n f3_fetch_bundle.cfi_is_ret := f3_ret_mask (f3_fetch_bundle.cfi_idx.bits)\n f3_fetch_bundle.cfi_npc_plus4 := f3_npc_plus4_mask(f3_fetch_bundle.cfi_idx.bits)\n\n f3_fetch_bundle.ghist := f3.io.deq.bits.ghist\n f3_fetch_bundle.lhist := f3_bpd_resp.io.deq.bits.lhist\n f3_fetch_bundle.bpd_meta := f3_bpd_resp.io.deq.bits.meta\n\n f3_fetch_bundle.end_half.valid := bank_prev_is_half\n f3_fetch_bundle.end_half.bits := bank_prev_half\n\n when (f3.io.deq.fire) {\n f3_prev_is_half := bank_prev_is_half\n f3_prev_half := bank_prev_half\n assert(f3_bpd_resp.io.deq.bits.pc === f3_fetch_bundle.pc)\n }\n\n when (f3_clear) {\n f3_prev_is_half := false.B\n }\n\n f3_fetch_bundle.cfi_idx.valid := f3_redirects.reduce(_||_)\n f3_fetch_bundle.cfi_idx.bits := PriorityEncoder(f3_redirects)\n\n f3_fetch_bundle.ras_top := ras.io.read_addr\n // Redirect earlier stages only if the later stage\n // can consume this packet\n\n val f3_predicted_target = Mux(f3_redirects.reduce(_||_),\n Mux(f3_fetch_bundle.cfi_is_ret && useBPD.B && useRAS.B,\n ras.io.read_addr,\n f3_targs(PriorityEncoder(f3_redirects))\n ),\n nextFetch(f3_fetch_bundle.pc)\n )\n\n f3_fetch_bundle.next_pc := f3_predicted_target\n val f3_predicted_ghist = f3_fetch_bundle.ghist.update(\n f3_fetch_bundle.br_mask,\n f3_fetch_bundle.cfi_idx.valid,\n f3_fetch_bundle.br_mask(f3_fetch_bundle.cfi_idx.bits),\n f3_fetch_bundle.cfi_idx.bits,\n f3_fetch_bundle.cfi_idx.valid,\n f3_fetch_bundle.pc,\n f3_fetch_bundle.cfi_is_call,\n f3_fetch_bundle.cfi_is_ret\n )\n\n\n ras.io.write_valid := false.B\n ras.io.write_addr := f3_aligned_pc + (f3_fetch_bundle.cfi_idx.bits << 1) + Mux(\n f3_fetch_bundle.cfi_npc_plus4, 4.U, 2.U)\n ras.io.write_idx := WrapInc(f3_fetch_bundle.ghist.ras_idx, nRasEntries)\n\n\n val f3_correct_f1_ghist = s1_ghist =/= f3_predicted_ghist && enableGHistStallRepair.B\n val f3_correct_f2_ghist = s2_ghist =/= f3_predicted_ghist && enableGHistStallRepair.B\n\n when (f3.io.deq.valid && f4_ready) {\n when (f3_fetch_bundle.cfi_is_call && f3_fetch_bundle.cfi_idx.valid) {\n ras.io.write_valid := true.B\n }\n when (f3_redirects.reduce(_||_)) {\n f3_prev_is_half := false.B\n }\n when (s2_valid && s2_vpc === f3_predicted_target && !f3_correct_f2_ghist) {\n f3.io.enq.bits.ghist := f3_predicted_ghist\n } .elsewhen (!s2_valid && s1_valid && s1_vpc === f3_predicted_target && !f3_correct_f1_ghist) {\n s2_ghist := f3_predicted_ghist\n } .elsewhen (( s2_valid && (s2_vpc =/= f3_predicted_target || f3_correct_f2_ghist)) ||\n (!s2_valid && s1_valid && (s1_vpc =/= f3_predicted_target || f3_correct_f1_ghist)) ||\n (!s2_valid && !s1_valid)) {\n f2_clear := true.B\n f1_clear := true.B\n\n s0_valid := !(f3_fetch_bundle.xcpt_pf_if || f3_fetch_bundle.xcpt_ae_if)\n s0_vpc := f3_predicted_target\n s0_is_replay := false.B\n s0_ghist := f3_predicted_ghist\n s0_tsrc := BSRC_3\n\n f3_fetch_bundle.fsrc := BSRC_3\n }\n }\n\n // When f3 finds a btb mispredict, queue up a bpd correction update\n val f4_btb_corrections = Module(new Queue(new BranchPredictionUpdate, 2))\n f4_btb_corrections.io.enq.valid := f3.io.deq.fire && f3_btb_mispredicts.reduce(_||_) && enableBTBFastRepair.B\n f4_btb_corrections.io.enq.bits := DontCare\n f4_btb_corrections.io.enq.bits.is_mispredict_update := false.B\n f4_btb_corrections.io.enq.bits.is_repair_update := false.B\n f4_btb_corrections.io.enq.bits.btb_mispredicts := f3_btb_mispredicts.asUInt\n f4_btb_corrections.io.enq.bits.pc := f3_fetch_bundle.pc\n f4_btb_corrections.io.enq.bits.ghist := f3_fetch_bundle.ghist\n f4_btb_corrections.io.enq.bits.lhist := f3_fetch_bundle.lhist\n f4_btb_corrections.io.enq.bits.meta := f3_fetch_bundle.bpd_meta\n\n\n // -------------------------------------------------------\n // **** F4 ****\n // -------------------------------------------------------\n val f4_clear = WireInit(false.B)\n val f4 = withReset(reset.asBool || f4_clear) {\n Module(new Queue(new FetchBundle, 1, pipe=true, flow=false))}\n\n val fb = Module(new FetchBuffer)\n val ftq = Module(new FetchTargetQueue)\n\n // When we mispredict, we need to repair\n\n // Deal with sfbs\n val f4_shadowable_masks = VecInit((0 until fetchWidth) map { i =>\n f4.io.deq.bits.shadowable_mask.asUInt |\n ~f4.io.deq.bits.sfb_masks(i)(fetchWidth-1,0)\n })\n val f3_shadowable_masks = VecInit((0 until fetchWidth) map { i =>\n Mux(f4.io.enq.valid, f4.io.enq.bits.shadowable_mask.asUInt, 0.U) |\n ~f4.io.deq.bits.sfb_masks(i)(2*fetchWidth-1,fetchWidth)\n })\n val f4_sfbs = VecInit((0 until fetchWidth) map { i =>\n enableSFBOpt.B &&\n ((~f4_shadowable_masks(i) === 0.U) &&\n (~f3_shadowable_masks(i) === 0.U) &&\n f4.io.deq.bits.sfbs(i) &&\n !(f4.io.deq.bits.cfi_idx.valid && f4.io.deq.bits.cfi_idx.bits === i.U) &&\n Mux(f4.io.deq.bits.sfb_dests(i) === 0.U,\n !bank_prev_is_half,\n Mux(f4.io.deq.bits.sfb_dests(i) === fetchBytes.U,\n !f4.io.deq.bits.end_half.valid,\n true.B)\n )\n\n )\n })\n val f4_sfb_valid = f4_sfbs.reduce(_||_) && f4.io.deq.valid\n val f4_sfb_idx = PriorityEncoder(f4_sfbs)\n val f4_sfb_mask = f4.io.deq.bits.sfb_masks(f4_sfb_idx)\n // If we have a SFB, wait for next fetch to be available in f3\n val f4_delay = (\n f4.io.deq.bits.sfbs.reduce(_||_) &&\n !f4.io.deq.bits.cfi_idx.valid &&\n !f4.io.enq.valid &&\n !f4.io.deq.bits.xcpt_pf_if &&\n !f4.io.deq.bits.xcpt_ae_if\n )\n when (f4_sfb_valid) {\n f3_shadowed_mask := f4_sfb_mask(2*fetchWidth-1,fetchWidth).asBools\n } .otherwise {\n f3_shadowed_mask := VecInit(0.U(fetchWidth.W).asBools)\n }\n\n f4_ready := f4.io.enq.ready\n f4.io.enq.valid := f3.io.deq.valid && !f3_clear\n f4.io.enq.bits := f3_fetch_bundle\n f4.io.deq.ready := fb.io.enq.ready && ftq.io.enq.ready && !f4_delay\n\n fb.io.enq.valid := f4.io.deq.valid && ftq.io.enq.ready && !f4_delay\n fb.io.enq.bits := f4.io.deq.bits\n fb.io.enq.bits.ftq_idx := ftq.io.enq_idx\n fb.io.enq.bits.sfbs := Mux(f4_sfb_valid, UIntToOH(f4_sfb_idx), 0.U(fetchWidth.W)).asBools\n fb.io.enq.bits.shadowed_mask := (\n Mux(f4_sfb_valid, f4_sfb_mask(fetchWidth-1,0), 0.U(fetchWidth.W)) |\n f4.io.deq.bits.shadowed_mask.asUInt\n ).asBools\n\n\n ftq.io.enq.valid := f4.io.deq.valid && fb.io.enq.ready && !f4_delay\n ftq.io.enq.bits := f4.io.deq.bits\n\n val bpd_update_arbiter = Module(new Arbiter(new BranchPredictionUpdate, 2))\n bpd_update_arbiter.io.in(0).valid := ftq.io.bpdupdate.valid\n bpd_update_arbiter.io.in(0).bits := ftq.io.bpdupdate.bits\n assert(bpd_update_arbiter.io.in(0).ready)\n bpd_update_arbiter.io.in(1) <> f4_btb_corrections.io.deq\n bpd.io.update := bpd_update_arbiter.io.out\n bpd_update_arbiter.io.out.ready := true.B\n\n when (ftq.io.ras_update && enableRasTopRepair.B) {\n ras.io.write_valid := true.B\n ras.io.write_idx := ftq.io.ras_update_idx\n ras.io.write_addr := ftq.io.ras_update_pc\n }\n\n\n // -------------------------------------------------------\n // **** To Core (F5) ****\n // -------------------------------------------------------\n\n io.cpu.fetchpacket <> fb.io.deq\n io.cpu.get_pc <> ftq.io.get_ftq_pc\n ftq.io.deq := io.cpu.commit\n ftq.io.brupdate := io.cpu.brupdate\n\n ftq.io.redirect.valid := io.cpu.redirect_val\n ftq.io.redirect.bits := io.cpu.redirect_ftq_idx\n fb.io.clear := false.B\n\n when (io.cpu.sfence.valid) {\n fb.io.clear := true.B\n f4_clear := true.B\n f3_clear := true.B\n f2_clear := true.B\n f1_clear := true.B\n\n s0_valid := false.B\n s0_vpc := io.cpu.sfence.bits.addr\n s0_is_replay := false.B\n s0_is_sfence := true.B\n\n }.elsewhen (io.cpu.redirect_flush) {\n fb.io.clear := true.B\n f4_clear := true.B\n f3_clear := true.B\n f2_clear := true.B\n f1_clear := true.B\n\n f3_prev_is_half := false.B\n\n s0_valid := io.cpu.redirect_val\n s0_vpc := io.cpu.redirect_pc\n s0_ghist := io.cpu.redirect_ghist\n s0_tsrc := BSRC_C\n s0_is_replay := false.B\n\n ftq.io.redirect.valid := io.cpu.redirect_val\n ftq.io.redirect.bits := io.cpu.redirect_ftq_idx\n }\n\n ftq.io.debug_ftq_idx := io.cpu.debug_ftq_idx\n io.cpu.debug_fetch_pc := ftq.io.debug_fetch_pc\n\n\n override def toString: String =\n (BoomCoreStringPrefix(\"====Overall Frontend Params====\") + \"\\n\"\n + icache.toString + bpd.toString)\n}\nFile regfile.scala:\n//******************************************************************************\n// Copyright (c) 2013 - 2018, The Regents of the University of California (Regents).\n// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.\n//------------------------------------------------------------------------------\n\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n// Register File (Abstract class and Synthesizable RegFile)\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n\npackage boom.v3.exu\n\nimport scala.collection.mutable.ArrayBuffer\n\nimport chisel3._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config.Parameters\n\nimport boom.v3.common._\nimport boom.v3.util.{BoomCoreStringPrefix}\n\n/**\n * IO bundle for a register read port\n *\n * @param addrWidth size of register address in bits\n * @param dataWidth size of register in bits\n */\nclass RegisterFileReadPortIO(val addrWidth: Int, val dataWidth: Int)(implicit p: Parameters) extends BoomBundle\n{\n val addr = Input(UInt(addrWidth.W))\n val data = Output(UInt(dataWidth.W))\n}\n\n/**\n * IO bundle for the register write port\n *\n * @param addrWidth size of register address in bits\n * @param dataWidth size of register in bits\n */\nclass RegisterFileWritePort(val addrWidth: Int, val dataWidth: Int)(implicit p: Parameters) extends BoomBundle\n{\n val addr = UInt(addrWidth.W)\n val data = UInt(dataWidth.W)\n}\n\n/**\n * Utility function to turn ExeUnitResps to match the regfile's WritePort I/Os.\n */\nobject WritePort\n{\n def apply(enq: DecoupledIO[ExeUnitResp], addrWidth: Int, dataWidth: Int, rtype: UInt)\n (implicit p: Parameters): Valid[RegisterFileWritePort] = {\n val wport = Wire(Valid(new RegisterFileWritePort(addrWidth, dataWidth)))\n\n wport.valid := enq.valid && enq.bits.uop.dst_rtype === rtype\n wport.bits.addr := enq.bits.uop.pdst\n wport.bits.data := enq.bits.data\n enq.ready := true.B\n wport\n }\n}\n\n/**\n * Register file abstract class\n *\n * @param numRegisters number of registers\n * @param numReadPorts number of read ports\n * @param numWritePorts number of write ports\n * @param registerWidth size of registers in bits\n * @param bypassableArray list of write ports from func units to the read port of the regfile\n */\nabstract class RegisterFile(\n numRegisters: Int,\n numReadPorts: Int,\n numWritePorts: Int,\n registerWidth: Int,\n bypassableArray: Seq[Boolean]) // which write ports can be bypassed to the read ports?\n (implicit p: Parameters) extends BoomModule\n{\n val io = IO(new BoomBundle {\n val read_ports = Vec(numReadPorts, new RegisterFileReadPortIO(maxPregSz, registerWidth))\n val write_ports = Flipped(Vec(numWritePorts, Valid(new RegisterFileWritePort(maxPregSz, registerWidth))))\n })\n\n private val rf_cost = (numReadPorts + numWritePorts) * (numReadPorts + 2*numWritePorts)\n private val type_str = if (registerWidth == fLen+1) \"Floating Point\" else \"Integer\"\n override def toString: String = BoomCoreStringPrefix(\n \"==\" + type_str + \" Regfile==\",\n \"Num RF Read Ports : \" + numReadPorts,\n \"Num RF Write Ports : \" + numWritePorts,\n \"RF Cost (R+W)*(R+2W) : \" + rf_cost,\n \"Bypassable Units : \" + bypassableArray)\n}\n\n/**\n * A synthesizable model of a Register File. You will likely want to blackbox this for more than modest port counts.\n *\n * @param numRegisters number of registers\n * @param numReadPorts number of read ports\n * @param numWritePorts number of write ports\n * @param registerWidth size of registers in bits\n * @param bypassableArray list of write ports from func units to the read port of the regfile\n */\nclass RegisterFileSynthesizable(\n numRegisters: Int,\n numReadPorts: Int,\n numWritePorts: Int,\n registerWidth: Int,\n bypassableArray: Seq[Boolean])\n (implicit p: Parameters)\n extends RegisterFile(numRegisters, numReadPorts, numWritePorts, registerWidth, bypassableArray)\n{\n // --------------------------------------------------------------\n\n val regfile = Mem(numRegisters, UInt(registerWidth.W))\n\n // --------------------------------------------------------------\n // Read ports.\n\n val read_data = Wire(Vec(numReadPorts, UInt(registerWidth.W)))\n\n // Register the read port addresses to give a full cycle to the RegisterRead Stage (if desired).\n val read_addrs = io.read_ports.map(p => RegNext(p.addr))\n\n for (i <- 0 until numReadPorts) {\n read_data(i) := regfile(read_addrs(i))\n }\n\n // --------------------------------------------------------------\n // Bypass out of the ALU's write ports.\n // We are assuming we cannot bypass a writer to a reader within the regfile memory\n // for a write that occurs at the end of cycle S1 and a read that returns data on cycle S1.\n // But since these bypasses are expensive, and not all write ports need to bypass their data,\n // only perform the w->r bypass on a select number of write ports.\n\n require (bypassableArray.length == io.write_ports.length)\n\n if (bypassableArray.reduce(_||_)) {\n val bypassable_wports = ArrayBuffer[Valid[RegisterFileWritePort]]()\n io.write_ports zip bypassableArray map { case (wport, b) => if (b) { bypassable_wports += wport} }\n\n for (i <- 0 until numReadPorts) {\n val bypass_ens = bypassable_wports.map(x => x.valid &&\n x.bits.addr === read_addrs(i))\n\n val bypass_data = Mux1H(VecInit(bypass_ens.toSeq), VecInit(bypassable_wports.map(_.bits.data).toSeq))\n\n io.read_ports(i).data := Mux(bypass_ens.reduce(_|_), bypass_data, read_data(i))\n }\n } else {\n for (i <- 0 until numReadPorts) {\n io.read_ports(i).data := read_data(i)\n }\n }\n\n // --------------------------------------------------------------\n // Write ports.\n\n for (wport <- io.write_ports) {\n when (wport.valid) {\n regfile(wport.bits.addr) := wport.bits.data\n }\n }\n\n // ensure there is only 1 writer per register (unless to preg0)\n if (numWritePorts > 1) {\n for (i <- 0 until (numWritePorts - 1)) {\n for (j <- (i + 1) until numWritePorts) {\n assert(!io.write_ports(i).valid ||\n !io.write_ports(j).valid ||\n (io.write_ports(i).bits.addr =/= io.write_ports(j).bits.addr) ||\n (io.write_ports(i).bits.addr === 0.U), // note: you only have to check one here\n \"[regfile] too many writers a register\")\n }\n }\n }\n}\nFile execution-units.scala:\n//******************************************************************************\n// Copyright (c) 2015 - 2018, The Regents of the University of California (Regents).\n// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.\n//------------------------------------------------------------------------------\n\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n// RISC-V Constructing the Execution Units\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n\npackage boom.v3.exu\n\nimport scala.collection.mutable.{ArrayBuffer}\n\nimport chisel3._\n\nimport org.chipsalliance.cde.config.{Parameters}\n\nimport boom.v3.common._\nimport boom.v3.util.{BoomCoreStringPrefix}\n\n/**\n * Top level class to wrap all execution units together into a \"collection\"\n *\n * @param fpu using a FPU?\n */\nclass ExecutionUnits(val fpu: Boolean)(implicit val p: Parameters) extends HasBoomCoreParameters\n{\n val totalIssueWidth = issueParams.map(_.issueWidth).sum\n\n //*******************************\n // Instantiate the ExecutionUnits\n\n private val exe_units = ArrayBuffer[ExecutionUnit]()\n\n //*******************************\n // Act like a collection\n\n def length = exe_units.length\n\n def apply(n: Int) = exe_units(n)\n\n def map[T](f: ExecutionUnit => T) = {\n exe_units.map(f)\n }\n\n def withFilter(f: ExecutionUnit => Boolean) = {\n exe_units.withFilter(f)\n }\n\n def foreach[U](f: ExecutionUnit => U) = {\n exe_units.foreach(f)\n }\n\n def zipWithIndex = {\n exe_units.zipWithIndex\n }\n\n def indexWhere(f: ExecutionUnit => Boolean) = {\n exe_units.indexWhere(f)\n }\n\n def count(f: ExecutionUnit => Boolean) = {\n exe_units.count(f)\n }\n\n lazy val memory_units = {\n exe_units.filter(_.hasMem)\n }\n\n lazy val alu_units = {\n exe_units.filter(_.hasAlu)\n }\n\n lazy val csr_unit = {\n require (exe_units.count(_.hasCSR) == 1)\n exe_units.find(_.hasCSR).get\n }\n\n lazy val ifpu_unit = {\n require (usingFPU)\n require (exe_units.count(_.hasIfpu) == 1)\n exe_units.find(_.hasIfpu).get\n }\n\n lazy val fpiu_unit = {\n require (usingFPU)\n require (exe_units.count(_.hasFpiu) == 1)\n exe_units.find(_.hasFpiu).get\n }\n\n\n lazy val jmp_unit_idx = {\n exe_units.indexWhere(_.hasJmpUnit)\n }\n\n lazy val rocc_unit = {\n require (usingRoCC)\n require (exe_units.count(_.hasRocc) == 1)\n exe_units.find(_.hasRocc).get\n }\n\n if (!fpu) {\n val int_width = issueParams.find(_.iqType == IQT_INT.litValue).get.issueWidth\n\n for (w <- 0 until memWidth) {\n val memExeUnit = Module(new ALUExeUnit(\n hasAlu = false,\n hasMem = true))\n\n memExeUnit.io.ll_iresp.ready := DontCare\n\n exe_units += memExeUnit\n }\n\n for (w <- 0 until int_width) {\n def is_nth(n: Int): Boolean = w == ((n) % int_width)\n val alu_exe_unit = Module(new ALUExeUnit(\n hasJmpUnit = is_nth(0),\n hasCSR = is_nth(1),\n hasRocc = is_nth(1) && usingRoCC,\n hasMul = is_nth(2),\n hasDiv = is_nth(3),\n hasIfpu = is_nth(4) && usingFPU))\n exe_units += alu_exe_unit\n }\n } else {\n val fp_width = issueParams.find(_.iqType == IQT_FP.litValue).get.issueWidth\n for (w <- 0 until fp_width) {\n val fpu_exe_unit = Module(new FPUExeUnit(hasFpu = true,\n hasFdiv = usingFDivSqrt && (w==0),\n hasFpiu = (w==0)))\n exe_units += fpu_exe_unit\n }\n }\n\n val exeUnitsStr = new StringBuilder\n for (exe_unit <- exe_units) {\n exeUnitsStr.append(exe_unit.toString)\n }\n\n override def toString: String =\n (BoomCoreStringPrefix(\"===ExecutionUnits===\") + \"\\n\"\n + (if (!fpu) {\n BoomCoreStringPrefix(\n \"==\" + coreWidth + \"-wide Machine==\",\n \"==\" + totalIssueWidth + \" Issue==\")\n } else {\n \"\"\n }) + \"\\n\"\n + exeUnitsStr.toString)\n\n require (exe_units.length != 0)\n if (!fpu) {\n // if this is for FPU units, we don't need a memory unit (or other integer units).\n require (exe_units.map(_.hasMem).reduce(_|_), \"Datapath is missing a memory unit.\")\n require (exe_units.map(_.hasMul).reduce(_|_), \"Datapath is missing a multiplier.\")\n require (exe_units.map(_.hasDiv).reduce(_|_), \"Datapath is missing a divider.\")\n } else {\n require (exe_units.map(_.hasFpu).reduce(_|_),\n \"Datapath is missing a fpu (or has an fpu and shouldnt).\")\n }\n\n val numIrfReaders = exe_units.count(_.readsIrf)\n val numIrfReadPorts = exe_units.count(_.readsIrf) * 2\n val numIrfWritePorts = exe_units.count(_.writesIrf)\n val numLlIrfWritePorts = exe_units.count(_.writesLlIrf)\n val numTotalBypassPorts = exe_units.withFilter(_.bypassable).map(_.numBypassStages).foldLeft(0)(_+_)\n\n val numFrfReaders = exe_units.count(_.readsFrf)\n val numFrfReadPorts = exe_units.count(_.readsFrf) * 3\n val numFrfWritePorts = exe_units.count(_.writesFrf)\n val numLlFrfWritePorts = exe_units.count(_.writesLlFrf)\n\n // The mem-unit will also bypass writes to readers in the RRD stage.\n // NOTE: This does NOT include the ll_wport\n val bypassable_write_port_mask = exe_units.withFilter(x => x.writesIrf).map(u => u.bypassable)\n}\nFile micro-op.scala:\n//******************************************************************************\n// Copyright (c) 2015 - 2018, The Regents of the University of California (Regents).\n// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.\n//------------------------------------------------------------------------------\n\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n// MicroOp\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n\npackage boom.v3.common\n\nimport chisel3._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config.Parameters\n\nimport boom.v3.exu.FUConstants\n\n/**\n * Extension to BoomBundle to add a MicroOp\n */\nabstract trait HasBoomUOP extends BoomBundle\n{\n val uop = new MicroOp()\n}\n\n/**\n * MicroOp passing through the pipeline\n */\nclass MicroOp(implicit p: Parameters) extends BoomBundle\n with freechips.rocketchip.rocket.constants.MemoryOpConstants\n with freechips.rocketchip.rocket.constants.ScalarOpConstants\n{\n val uopc = UInt(UOPC_SZ.W) // micro-op code\n val inst = UInt(32.W)\n val debug_inst = UInt(32.W)\n val is_rvc = Bool()\n val debug_pc = UInt(coreMaxAddrBits.W)\n val iq_type = UInt(IQT_SZ.W) // which issue unit do we use?\n val fu_code = UInt(FUConstants.FUC_SZ.W) // which functional unit do we use?\n val ctrl = new CtrlSignals\n\n // What is the next state of this uop in the issue window? useful\n // for the compacting queue.\n val iw_state = UInt(2.W)\n // Has operand 1 or 2 been waken speculatively by a load?\n // Only integer operands are speculaively woken up,\n // so we can ignore p3.\n val iw_p1_poisoned = Bool()\n val iw_p2_poisoned = Bool()\n\n val is_br = Bool() // is this micro-op a (branch) vs a regular PC+4 inst?\n val is_jalr = Bool() // is this a jump? (jal or jalr)\n val is_jal = Bool() // is this a JAL (doesn't include JR)? used for branch unit\n val is_sfb = Bool() // is this a sfb or in the shadow of a sfb\n\n val br_mask = UInt(maxBrCount.W) // which branches are we being speculated under?\n val br_tag = UInt(brTagSz.W)\n\n // Index into FTQ to figure out our fetch PC.\n val ftq_idx = UInt(log2Ceil(ftqSz).W)\n // This inst straddles two fetch packets\n val edge_inst = Bool()\n // Low-order bits of our own PC. Combine with ftq[ftq_idx] to get PC.\n // Aligned to a cache-line size, as that is the greater fetch granularity.\n // TODO: Shouldn't this be aligned to fetch-width size?\n val pc_lob = UInt(log2Ceil(icBlockBytes).W)\n\n // Was this a branch that was predicted taken?\n val taken = Bool()\n\n val imm_packed = UInt(LONGEST_IMM_SZ.W) // densely pack the imm in decode...\n // then translate and sign-extend in execute\n val csr_addr = UInt(CSR_ADDR_SZ.W) // only used for critical path reasons in Exe\n val rob_idx = UInt(robAddrSz.W)\n val ldq_idx = UInt(ldqAddrSz.W)\n val stq_idx = UInt(stqAddrSz.W)\n val rxq_idx = UInt(log2Ceil(numRxqEntries).W)\n val pdst = UInt(maxPregSz.W)\n val prs1 = UInt(maxPregSz.W)\n val prs2 = UInt(maxPregSz.W)\n val prs3 = UInt(maxPregSz.W)\n val ppred = UInt(log2Ceil(ftqSz).W)\n\n val prs1_busy = Bool()\n val prs2_busy = Bool()\n val prs3_busy = Bool()\n val ppred_busy = Bool()\n val stale_pdst = UInt(maxPregSz.W)\n val exception = Bool()\n val exc_cause = UInt(xLen.W) // TODO compress this down, xlen is insanity\n val bypassable = Bool() // can we bypass ALU results? (doesn't include loads, csr, etc...)\n val mem_cmd = UInt(M_SZ.W) // sync primitives/cache flushes\n val mem_size = UInt(2.W)\n val mem_signed = Bool()\n val is_fence = Bool()\n val is_fencei = Bool()\n val is_amo = Bool()\n val uses_ldq = Bool()\n val uses_stq = Bool()\n val is_sys_pc2epc = Bool() // Is a ECall or Breakpoint -- both set EPC to PC.\n val is_unique = Bool() // only allow this instruction in the pipeline, wait for STQ to\n // drain, clear fetcha fter it (tell ROB to un-ready until empty)\n val flush_on_commit = Bool() // some instructions need to flush the pipeline behind them\n\n // Preditation\n def is_sfb_br = is_br && is_sfb && enableSFBOpt.B // Does this write a predicate\n def is_sfb_shadow = !is_br && is_sfb && enableSFBOpt.B // Is this predicated\n val ldst_is_rs1 = Bool() // If this is set and we are predicated off, copy rs1 to dst,\n // else copy rs2 to dst\n\n // logical specifiers (only used in Decode->Rename), except rollback (ldst)\n val ldst = UInt(lregSz.W)\n val lrs1 = UInt(lregSz.W)\n val lrs2 = UInt(lregSz.W)\n val lrs3 = UInt(lregSz.W)\n\n val ldst_val = Bool() // is there a destination? invalid for stores, rd==x0, etc.\n val dst_rtype = UInt(2.W)\n val lrs1_rtype = UInt(2.W)\n val lrs2_rtype = UInt(2.W)\n val frs3_en = Bool()\n\n // floating point information\n val fp_val = Bool() // is a floating-point instruction (F- or D-extension)?\n // If it's non-ld/st it will write back exception bits to the fcsr.\n val fp_single = Bool() // single-precision floating point instruction (F-extension)\n\n // frontend exception information\n val xcpt_pf_if = Bool() // I-TLB page fault.\n val xcpt_ae_if = Bool() // I$ access exception.\n val xcpt_ma_if = Bool() // Misaligned fetch (jal/brjumping to misaligned addr).\n val bp_debug_if = Bool() // Breakpoint\n val bp_xcpt_if = Bool() // Breakpoint\n\n\n // What prediction structure provides the prediction FROM this op\n val debug_fsrc = UInt(BSRC_SZ.W)\n // What prediction structure provides the prediction TO this op\n val debug_tsrc = UInt(BSRC_SZ.W)\n\n // Do we allocate a branch tag for this?\n // SFB branches don't get a mask, they get a predicate bit\n def allocate_brtag = (is_br && !is_sfb) || is_jalr\n\n // Does this register write-back\n def rf_wen = dst_rtype =/= RT_X\n\n // Is it possible for this uop to misspeculate, preventing the commit of subsequent uops?\n def unsafe = uses_ldq || (uses_stq && !is_fence) || is_br || is_jalr\n\n def fu_code_is(_fu: UInt) = (fu_code & _fu) =/= 0.U\n}\n\n/**\n * Control signals within a MicroOp\n *\n * TODO REFACTOR this, as this should no longer be true, as bypass occurs in stage before branch resolution\n */\nclass CtrlSignals extends Bundle()\n{\n val br_type = UInt(BR_N.getWidth.W)\n val op1_sel = UInt(OP1_X.getWidth.W)\n val op2_sel = UInt(OP2_X.getWidth.W)\n val imm_sel = UInt(IS_X.getWidth.W)\n val op_fcn = UInt(freechips.rocketchip.rocket.ALU.SZ_ALU_FN.W)\n val fcn_dw = Bool()\n val csr_cmd = UInt(freechips.rocketchip.rocket.CSR.SZ.W)\n val is_load = Bool() // will invoke TLB address lookup\n val is_sta = Bool() // will invoke TLB address lookup\n val is_std = Bool()\n}\nFile CSR.scala:\n// See LICENSE.SiFive for license details.\n// See LICENSE.Berkeley for license details.\n\npackage freechips.rocketchip.rocket\n\nimport chisel3._\nimport chisel3.util.{BitPat, Cat, Fill, Mux1H, PopCount, PriorityMux, RegEnable, UIntToOH, Valid, log2Ceil, log2Up}\nimport org.chipsalliance.cde.config.Parameters\nimport freechips.rocketchip.devices.debug.DebugModuleKey\nimport freechips.rocketchip.tile._\nimport freechips.rocketchip.util._\nimport freechips.rocketchip.util.property\n\nimport scala.collection.mutable.LinkedHashMap\nimport Instructions._\nimport CustomInstructions._\n\nclass MStatus extends Bundle {\n // not truly part of mstatus, but convenient\n val debug = Bool()\n val cease = Bool()\n val wfi = Bool()\n val isa = UInt(32.W)\n\n val dprv = UInt(PRV.SZ.W) // effective prv for data accesses\n val dv = Bool() // effective v for data accesses\n val prv = UInt(PRV.SZ.W)\n val v = Bool()\n\n val sd = Bool()\n val zero2 = UInt(23.W)\n val mpv = Bool()\n val gva = Bool()\n val mbe = Bool()\n val sbe = Bool()\n val sxl = UInt(2.W)\n val uxl = UInt(2.W)\n val sd_rv32 = Bool()\n val zero1 = UInt(8.W)\n val tsr = Bool()\n val tw = Bool()\n val tvm = Bool()\n val mxr = Bool()\n val sum = Bool()\n val mprv = Bool()\n val xs = UInt(2.W)\n val fs = UInt(2.W)\n val mpp = UInt(2.W)\n val vs = UInt(2.W)\n val spp = UInt(1.W)\n val mpie = Bool()\n val ube = Bool()\n val spie = Bool()\n val upie = Bool()\n val mie = Bool()\n val hie = Bool()\n val sie = Bool()\n val uie = Bool()\n}\n\nclass MNStatus extends Bundle {\n val mpp = UInt(2.W)\n val zero3 = UInt(3.W)\n val mpv = Bool()\n val zero2 = UInt(3.W)\n val mie = Bool()\n val zero1 = UInt(3.W)\n}\n\nclass HStatus extends Bundle {\n val zero6 = UInt(30.W)\n val vsxl = UInt(2.W)\n val zero5 = UInt(9.W)\n val vtsr = Bool()\n val vtw = Bool()\n val vtvm = Bool()\n val zero3 = UInt(2.W)\n val vgein = UInt(6.W)\n val zero2 = UInt(2.W)\n val hu = Bool()\n val spvp = Bool()\n val spv = Bool()\n val gva = Bool()\n val vsbe = Bool()\n val zero1 = UInt(5.W)\n}\n\nclass DCSR extends Bundle {\n val xdebugver = UInt(2.W)\n val zero4 = UInt(2.W)\n val zero3 = UInt(12.W)\n val ebreakm = Bool()\n val ebreakh = Bool()\n val ebreaks = Bool()\n val ebreaku = Bool()\n val zero2 = Bool()\n val stopcycle = Bool()\n val stoptime = Bool()\n val cause = UInt(3.W)\n val v = Bool()\n val zero1 = UInt(2.W)\n val step = Bool()\n val prv = UInt(PRV.SZ.W)\n}\n\nclass MIP(implicit p: Parameters) extends CoreBundle()(p)\n with HasCoreParameters {\n val lip = Vec(coreParams.nLocalInterrupts, Bool())\n val zero1 = Bool()\n val debug = Bool() // keep in sync with CSR.debugIntCause\n val rocc = Bool()\n val sgeip = Bool()\n val meip = Bool()\n val vseip = Bool()\n val seip = Bool()\n val ueip = Bool()\n val mtip = Bool()\n val vstip = Bool()\n val stip = Bool()\n val utip = Bool()\n val msip = Bool()\n val vssip = Bool()\n val ssip = Bool()\n val usip = Bool()\n}\n\nclass Envcfg extends Bundle {\n val stce = Bool() // only for menvcfg/henvcfg\n val pbmte = Bool() // only for menvcfg/henvcfg\n val zero54 = UInt(54.W)\n val cbze = Bool()\n val cbcfe = Bool()\n val cbie = UInt(2.W)\n val zero3 = UInt(3.W)\n val fiom = Bool()\n def write(wdata: UInt) {\n val new_envcfg = wdata.asTypeOf(new Envcfg)\n fiom := new_envcfg.fiom // only FIOM is writable currently\n }\n}\n\nclass PTBR(implicit p: Parameters) extends CoreBundle()(p) {\n def additionalPgLevels = mode.extract(log2Ceil(pgLevels-minPgLevels+1)-1, 0)\n def pgLevelsToMode(i: Int) = (xLen, i) match {\n case (32, 2) => 1\n case (64, x) if x >= 3 && x <= 6 => x + 5\n }\n val (modeBits, maxASIdBits) = xLen match {\n case 32 => (1, 9)\n case 64 => (4, 16)\n }\n require(modeBits + maxASIdBits + maxPAddrBits - pgIdxBits == xLen)\n\n val mode = UInt(modeBits.W)\n val asid = UInt(maxASIdBits.W)\n val ppn = UInt((maxPAddrBits - pgIdxBits).W)\n}\n\nobject PRV\n{\n val SZ = 2\n val U = 0\n val S = 1\n val H = 2\n val M = 3\n}\n\nobject CSR\n{\n // commands\n val SZ = 3\n def X = BitPat.dontCare(SZ)\n def N = 0.U(SZ.W)\n def R = 2.U(SZ.W)\n def I = 4.U(SZ.W)\n def W = 5.U(SZ.W)\n def S = 6.U(SZ.W)\n def C = 7.U(SZ.W)\n\n // mask a CSR cmd with a valid bit\n def maskCmd(valid: Bool, cmd: UInt): UInt = {\n // all commands less than CSR.I are treated by CSRFile as NOPs\n cmd & ~Mux(valid, 0.U, CSR.I)\n }\n\n val ADDRSZ = 12\n\n def modeLSB: Int = 8\n def mode(addr: Int): Int = (addr >> modeLSB) % (1 << PRV.SZ)\n def mode(addr: UInt): UInt = addr(modeLSB + PRV.SZ - 1, modeLSB)\n\n def busErrorIntCause = 128\n def debugIntCause = 14 // keep in sync with MIP.debug\n def debugTriggerCause = {\n val res = debugIntCause\n require(!(Causes.all contains res))\n res\n }\n def rnmiIntCause = 13 // NMI: Higher numbers = higher priority, must not reuse debugIntCause\n def rnmiBEUCause = 12\n\n val firstCtr = CSRs.cycle\n val firstCtrH = CSRs.cycleh\n val firstHPC = CSRs.hpmcounter3\n val firstHPCH = CSRs.hpmcounter3h\n val firstHPE = CSRs.mhpmevent3\n val firstMHPC = CSRs.mhpmcounter3\n val firstMHPCH = CSRs.mhpmcounter3h\n val firstHPM = 3\n val nCtr = 32\n val nHPM = nCtr - firstHPM\n val hpmWidth = 40\n\n val maxPMPs = 16\n}\n\nclass PerfCounterIO(implicit p: Parameters) extends CoreBundle\n with HasCoreParameters {\n val eventSel = Output(UInt(xLen.W))\n val inc = Input(UInt(log2Ceil(1+retireWidth).W))\n}\n\nclass TracedInstruction(implicit p: Parameters) extends CoreBundle {\n val valid = Bool()\n val iaddr = UInt(coreMaxAddrBits.W)\n val insn = UInt(iLen.W)\n val priv = UInt(3.W)\n val exception = Bool()\n val interrupt = Bool()\n val cause = UInt(xLen.W)\n val tval = UInt((coreMaxAddrBits max iLen).W)\n val wdata = Option.when(traceHasWdata)(UInt((vLen max xLen).W))\n}\n\nclass TraceAux extends Bundle {\n val enable = Bool()\n val stall = Bool()\n}\n\nclass CSRDecodeIO(implicit p: Parameters) extends CoreBundle {\n val inst = Input(UInt(iLen.W))\n\n def csr_addr = (inst >> 20)(CSR.ADDRSZ-1, 0)\n\n val fp_illegal = Output(Bool())\n val vector_illegal = Output(Bool())\n val fp_csr = Output(Bool())\n val vector_csr = Output(Bool())\n val rocc_illegal = Output(Bool())\n val read_illegal = Output(Bool())\n val write_illegal = Output(Bool())\n val write_flush = Output(Bool())\n val system_illegal = Output(Bool())\n val virtual_access_illegal = Output(Bool())\n val virtual_system_illegal = Output(Bool())\n}\n\nclass CSRFileIO(hasBeu: Boolean)(implicit p: Parameters) extends CoreBundle\n with HasCoreParameters {\n val ungated_clock = Input(Clock())\n val interrupts = Input(new CoreInterrupts(hasBeu))\n val hartid = Input(UInt(hartIdLen.W))\n val rw = new Bundle {\n val addr = Input(UInt(CSR.ADDRSZ.W))\n val cmd = Input(Bits(CSR.SZ.W))\n val rdata = Output(Bits(xLen.W))\n val wdata = Input(Bits(xLen.W))\n }\n\n val decode = Vec(decodeWidth, new CSRDecodeIO)\n\n val csr_stall = Output(Bool()) // stall retire for wfi\n val rw_stall = Output(Bool()) // stall rw, rw will have no effect while rw_stall\n val eret = Output(Bool())\n val singleStep = Output(Bool())\n\n val status = Output(new MStatus())\n val hstatus = Output(new HStatus())\n val gstatus = Output(new MStatus())\n val ptbr = Output(new PTBR())\n val hgatp = Output(new PTBR())\n val vsatp = Output(new PTBR())\n val evec = Output(UInt(vaddrBitsExtended.W))\n val exception = Input(Bool())\n val retire = Input(UInt(log2Up(1+retireWidth).W))\n val cause = Input(UInt(xLen.W))\n val pc = Input(UInt(vaddrBitsExtended.W))\n val tval = Input(UInt(vaddrBitsExtended.W))\n val htval = Input(UInt(((maxSVAddrBits + 1) min xLen).W))\n val mhtinst_read_pseudo = Input(Bool())\n val gva = Input(Bool())\n val time = Output(UInt(xLen.W))\n val fcsr_rm = Output(Bits(FPConstants.RM_SZ.W))\n val fcsr_flags = Flipped(Valid(Bits(FPConstants.FLAGS_SZ.W)))\n val set_fs_dirty = coreParams.haveFSDirty.option(Input(Bool()))\n val rocc_interrupt = Input(Bool())\n val interrupt = Output(Bool())\n val interrupt_cause = Output(UInt(xLen.W))\n val bp = Output(Vec(nBreakpoints, new BP))\n val pmp = Output(Vec(nPMPs, new PMP))\n val counters = Vec(nPerfCounters, new PerfCounterIO)\n val csrw_counter = Output(UInt(CSR.nCtr.W))\n val inhibit_cycle = Output(Bool())\n val inst = Input(Vec(retireWidth, UInt(iLen.W)))\n val trace = Output(Vec(retireWidth, new TracedInstruction))\n val mcontext = Output(UInt(coreParams.mcontextWidth.W))\n val scontext = Output(UInt(coreParams.scontextWidth.W))\n val fiom = Output(Bool())\n\n val vector = usingVector.option(new Bundle {\n val vconfig = Output(new VConfig())\n val vstart = Output(UInt(maxVLMax.log2.W))\n val vxrm = Output(UInt(2.W))\n val set_vs_dirty = Input(Bool())\n val set_vconfig = Flipped(Valid(new VConfig))\n val set_vstart = Flipped(Valid(vstart))\n val set_vxsat = Input(Bool())\n })\n}\n\nclass VConfig(implicit p: Parameters) extends CoreBundle {\n val vl = UInt((maxVLMax.log2 + 1).W)\n val vtype = new VType\n}\n\nobject VType {\n def fromUInt(that: UInt, ignore_vill: Boolean = false)(implicit p: Parameters): VType = {\n val res = 0.U.asTypeOf(new VType)\n val in = that.asTypeOf(res)\n val vill = (in.max_vsew.U < in.vsew) || !in.lmul_ok || in.reserved =/= 0.U || in.vill\n when (!vill || ignore_vill.B) {\n res := in\n res.vsew := in.vsew(log2Ceil(1 + in.max_vsew) - 1, 0)\n }\n res.reserved := 0.U\n res.vill := vill\n res\n }\n\n def computeVL(avl: UInt, vtype: UInt, currentVL: UInt, useCurrentVL: Bool, useMax: Bool, useZero: Bool)(implicit p: Parameters): UInt =\n VType.fromUInt(vtype, true).vl(avl, currentVL, useCurrentVL, useMax, useZero)\n}\n\nclass VType(implicit p: Parameters) extends CoreBundle {\n val vill = Bool()\n val reserved = UInt((xLen - 9).W)\n val vma = Bool()\n val vta = Bool()\n val vsew = UInt(3.W)\n val vlmul_sign = Bool()\n val vlmul_mag = UInt(2.W)\n\n def vlmul_signed: SInt = Cat(vlmul_sign, vlmul_mag).asSInt\n\n @deprecated(\"use vlmul_sign, vlmul_mag, or vlmul_signed\", \"RVV 0.9\")\n def vlmul: UInt = vlmul_mag\n\n def max_vsew = log2Ceil(eLen/8)\n def max_vlmul = (1 << vlmul_mag.getWidth) - 1\n\n def lmul_ok: Bool = Mux(this.vlmul_sign, this.vlmul_mag =/= 0.U && ~this.vlmul_mag < max_vsew.U - this.vsew, true.B)\n\n def minVLMax: Int = ((maxVLMax / eLen) >> ((1 << vlmul_mag.getWidth) - 1)) max 1\n\n def vlMax: UInt = (maxVLMax.U >> (this.vsew +& Cat(this.vlmul_sign, ~this.vlmul_mag))).andNot((minVLMax-1).U)\n\n def vl(avl: UInt, currentVL: UInt, useCurrentVL: Bool, useMax: Bool, useZero: Bool): UInt = {\n val atLeastMaxVLMax = useMax || Mux(useCurrentVL, currentVL >= maxVLMax.U, avl >= maxVLMax.U)\n val avl_lsbs = Mux(useCurrentVL, currentVL, avl)(maxVLMax.log2 - 1, 0)\n\n val atLeastVLMax = atLeastMaxVLMax || (avl_lsbs & (-maxVLMax.S >> (this.vsew +& Cat(this.vlmul_sign, ~this.vlmul_mag))).asUInt.andNot((minVLMax-1).U)).orR\n val isZero = vill || useZero\n Mux(!isZero && atLeastVLMax, vlMax, 0.U) | Mux(!isZero && !atLeastVLMax, avl_lsbs, 0.U)\n }\n}\n\nclass CSRFile(\n perfEventSets: EventSets = new EventSets(Seq()),\n customCSRs: Seq[CustomCSR] = Nil,\n roccCSRs: Seq[CustomCSR] = Nil,\n hasBeu: Boolean = false)(implicit p: Parameters)\n extends CoreModule()(p)\n with HasCoreParameters {\n val io = IO(new CSRFileIO(hasBeu) {\n val customCSRs = Vec(CSRFile.this.customCSRs.size, new CustomCSRIO)\n val roccCSRs = Vec(CSRFile.this.roccCSRs.size, new CustomCSRIO)\n })\n\n io.rw_stall := false.B\n\n val reset_mstatus = WireDefault(0.U.asTypeOf(new MStatus()))\n reset_mstatus.mpp := PRV.M.U\n reset_mstatus.prv := PRV.M.U\n reset_mstatus.xs := (if (usingRoCC) 3.U else 0.U)\n val reg_mstatus = RegInit(reset_mstatus)\n\n val new_prv = WireDefault(reg_mstatus.prv)\n reg_mstatus.prv := legalizePrivilege(new_prv)\n\n val reset_dcsr = WireDefault(0.U.asTypeOf(new DCSR()))\n reset_dcsr.xdebugver := 1.U\n reset_dcsr.prv := PRV.M.U\n val reg_dcsr = RegInit(reset_dcsr)\n\n val (supported_interrupts, delegable_interrupts) = {\n val sup = Wire(new MIP)\n sup.usip := false.B\n sup.ssip := usingSupervisor.B\n sup.vssip := usingHypervisor.B\n sup.msip := true.B\n sup.utip := false.B\n sup.stip := usingSupervisor.B\n sup.vstip := usingHypervisor.B\n sup.mtip := true.B\n sup.ueip := false.B\n sup.seip := usingSupervisor.B\n sup.vseip := usingHypervisor.B\n sup.meip := true.B\n sup.sgeip := false.B\n sup.rocc := usingRoCC.B\n sup.debug := false.B\n sup.zero1 := false.B\n sup.lip foreach { _ := true.B }\n val supported_high_interrupts = if (io.interrupts.buserror.nonEmpty && !usingNMI) (BigInt(1) << CSR.busErrorIntCause).U else 0.U\n\n val del = WireDefault(sup)\n del.msip := false.B\n del.mtip := false.B\n del.meip := false.B\n\n (sup.asUInt | supported_high_interrupts, del.asUInt)\n }\n val delegable_base_exceptions = Seq(\n Causes.misaligned_fetch,\n Causes.fetch_page_fault,\n Causes.breakpoint,\n Causes.load_page_fault,\n Causes.store_page_fault,\n Causes.misaligned_load,\n Causes.misaligned_store,\n Causes.illegal_instruction,\n Causes.user_ecall,\n )\n val delegable_hypervisor_exceptions = Seq(\n Causes.virtual_supervisor_ecall,\n Causes.fetch_guest_page_fault,\n Causes.load_guest_page_fault,\n Causes.virtual_instruction,\n Causes.store_guest_page_fault,\n )\n val delegable_exceptions = (\n delegable_base_exceptions\n ++ (if (usingHypervisor) delegable_hypervisor_exceptions else Seq())\n ).map(1 << _).sum.U\n\n val hs_delegable_exceptions = Seq(\n Causes.misaligned_fetch,\n Causes.fetch_access,\n Causes.illegal_instruction,\n Causes.breakpoint,\n Causes.misaligned_load,\n Causes.load_access,\n Causes.misaligned_store,\n Causes.store_access,\n Causes.user_ecall,\n Causes.fetch_page_fault,\n Causes.load_page_fault,\n Causes.store_page_fault).map(1 << _).sum.U\n\n val (hs_delegable_interrupts, mideleg_always_hs) = {\n val always = WireDefault(0.U.asTypeOf(new MIP()))\n always.vssip := usingHypervisor.B\n always.vstip := usingHypervisor.B\n always.vseip := usingHypervisor.B\n\n val deleg = WireDefault(always)\n deleg.lip.foreach { _ := usingHypervisor.B }\n\n (deleg.asUInt, always.asUInt)\n }\n\n val reg_debug = RegInit(false.B)\n val reg_dpc = Reg(UInt(vaddrBitsExtended.W))\n val reg_dscratch0 = Reg(UInt(xLen.W))\n val reg_dscratch1 = (p(DebugModuleKey).map(_.nDscratch).getOrElse(1) > 1).option(Reg(UInt(xLen.W)))\n val reg_singleStepped = Reg(Bool())\n\n val reg_mcontext = (coreParams.mcontextWidth > 0).option(RegInit(0.U(coreParams.mcontextWidth.W)))\n val reg_scontext = (coreParams.scontextWidth > 0).option(RegInit(0.U(coreParams.scontextWidth.W)))\n\n val reg_tselect = Reg(UInt(log2Up(nBreakpoints).W))\n val reg_bp = Reg(Vec(1 << log2Up(nBreakpoints), new BP))\n val reg_pmp = Reg(Vec(nPMPs, new PMPReg))\n\n val reg_mie = Reg(UInt(xLen.W))\n val (reg_mideleg, read_mideleg) = {\n val reg = Reg(UInt(xLen.W))\n (reg, Mux(usingSupervisor.B, reg & delegable_interrupts | mideleg_always_hs, 0.U))\n }\n val (reg_medeleg, read_medeleg) = {\n val reg = Reg(UInt(xLen.W))\n (reg, Mux(usingSupervisor.B, reg & delegable_exceptions, 0.U))\n }\n val reg_mip = Reg(new MIP)\n val reg_mepc = Reg(UInt(vaddrBitsExtended.W))\n val reg_mcause = RegInit(0.U(xLen.W))\n val reg_mtval = Reg(UInt(vaddrBitsExtended.W))\n val reg_mtval2 = Reg(UInt(((maxSVAddrBits + 1) min xLen).W))\n val reg_mscratch = Reg(Bits(xLen.W))\n val mtvecWidth = paddrBits min xLen\n val reg_mtvec = mtvecInit match {\n case Some(addr) => RegInit(addr.U(mtvecWidth.W))\n case None => Reg(UInt(mtvecWidth.W))\n }\n\n val reset_mnstatus = WireDefault(0.U.asTypeOf(new MNStatus()))\n reset_mnstatus.mpp := PRV.M.U\n val reg_mnscratch = Reg(Bits(xLen.W))\n val reg_mnepc = Reg(UInt(vaddrBitsExtended.W))\n val reg_mncause = RegInit(0.U(xLen.W))\n val reg_mnstatus = RegInit(reset_mnstatus)\n val reg_rnmie = RegInit(true.B)\n val nmie = reg_rnmie\n\n val reg_menvcfg = RegInit(0.U.asTypeOf(new Envcfg))\n val reg_senvcfg = RegInit(0.U.asTypeOf(new Envcfg))\n val reg_henvcfg = RegInit(0.U.asTypeOf(new Envcfg))\n\n val delegable_counters = ((BigInt(1) << (nPerfCounters + CSR.firstHPM)) - 1).U\n val (reg_mcounteren, read_mcounteren) = {\n val reg = Reg(UInt(32.W))\n (reg, Mux(usingUser.B, reg & delegable_counters, 0.U))\n }\n val (reg_scounteren, read_scounteren) = {\n val reg = Reg(UInt(32.W))\n (reg, Mux(usingSupervisor.B, reg & delegable_counters, 0.U))\n }\n\n val (reg_hideleg, read_hideleg) = {\n val reg = Reg(UInt(xLen.W))\n (reg, Mux(usingHypervisor.B, reg & hs_delegable_interrupts, 0.U))\n }\n val (reg_hedeleg, read_hedeleg) = {\n val reg = Reg(UInt(xLen.W))\n (reg, Mux(usingHypervisor.B, reg & hs_delegable_exceptions, 0.U))\n }\n val hs_delegable_counters = delegable_counters\n val (reg_hcounteren, read_hcounteren) = {\n val reg = Reg(UInt(32.W))\n (reg, Mux(usingHypervisor.B, reg & hs_delegable_counters, 0.U))\n }\n val reg_hstatus = RegInit(0.U.asTypeOf(new HStatus))\n val reg_hgatp = Reg(new PTBR)\n val reg_htval = Reg(reg_mtval2.cloneType)\n val read_hvip = reg_mip.asUInt & hs_delegable_interrupts\n val read_hie = reg_mie & hs_delegable_interrupts\n\n val (reg_vstvec, read_vstvec) = {\n val reg = Reg(UInt(vaddrBitsExtended.W))\n (reg, formTVec(reg).sextTo(xLen))\n }\n val reg_vsstatus = Reg(new MStatus)\n val reg_vsscratch = Reg(Bits(xLen.W))\n val reg_vsepc = Reg(UInt(vaddrBitsExtended.W))\n val reg_vscause = Reg(Bits(xLen.W))\n val reg_vstval = Reg(UInt(vaddrBitsExtended.W))\n val reg_vsatp = Reg(new PTBR)\n\n val reg_sepc = Reg(UInt(vaddrBitsExtended.W))\n val reg_scause = Reg(Bits(xLen.W))\n val reg_stval = Reg(UInt(vaddrBitsExtended.W))\n val reg_sscratch = Reg(Bits(xLen.W))\n val reg_stvec = Reg(UInt((if (usingHypervisor) vaddrBitsExtended else vaddrBits).W))\n val reg_satp = Reg(new PTBR)\n val reg_wfi = withClock(io.ungated_clock) { RegInit(false.B) }\n\n val reg_fflags = Reg(UInt(5.W))\n val reg_frm = Reg(UInt(3.W))\n val reg_vconfig = usingVector.option(Reg(new VConfig))\n val reg_vstart = usingVector.option(Reg(UInt(maxVLMax.log2.W)))\n val reg_vxsat = usingVector.option(Reg(Bool()))\n val reg_vxrm = usingVector.option(Reg(UInt(io.vector.get.vxrm.getWidth.W)))\n\n val reg_mtinst_read_pseudo = Reg(Bool())\n val reg_htinst_read_pseudo = Reg(Bool())\n // XLEN=32: 0x00002000\n // XLEN=64: 0x00003000\n val Seq(read_mtinst, read_htinst) = Seq(reg_mtinst_read_pseudo, reg_htinst_read_pseudo).map(r => Cat(r, (xLen == 32).option(0.U).getOrElse(r), 0.U(12.W)))\n\n val reg_mcountinhibit = RegInit(0.U((CSR.firstHPM + nPerfCounters).W))\n io.inhibit_cycle := reg_mcountinhibit(0)\n val reg_instret = WideCounter(64, io.retire, inhibit = reg_mcountinhibit(2))\n val reg_cycle = if (enableCommitLog) WideCounter(64, io.retire, inhibit = reg_mcountinhibit(0))\n else withClock(io.ungated_clock) { WideCounter(64, !io.csr_stall, inhibit = reg_mcountinhibit(0)) }\n val reg_hpmevent = io.counters.map(c => RegInit(0.U(xLen.W)))\n (io.counters zip reg_hpmevent) foreach { case (c, e) => c.eventSel := e }\n val reg_hpmcounter = io.counters.zipWithIndex.map { case (c, i) =>\n WideCounter(CSR.hpmWidth, c.inc, reset = false, inhibit = reg_mcountinhibit(CSR.firstHPM+i)) }\n\n val mip = WireDefault(reg_mip)\n mip.lip := (io.interrupts.lip: Seq[Bool])\n mip.mtip := io.interrupts.mtip\n mip.msip := io.interrupts.msip\n mip.meip := io.interrupts.meip\n // seip is the OR of reg_mip.seip and the actual line from the PLIC\n io.interrupts.seip.foreach { mip.seip := reg_mip.seip || _ }\n // Simimlar sort of thing would apply if the PLIC had a VSEIP line:\n //io.interrupts.vseip.foreach { mip.vseip := reg_mip.vseip || _ }\n mip.rocc := io.rocc_interrupt\n val read_mip = mip.asUInt & supported_interrupts\n val read_hip = read_mip & hs_delegable_interrupts\n val high_interrupts = (if (usingNMI) 0.U else io.interrupts.buserror.map(_ << CSR.busErrorIntCause).getOrElse(0.U))\n\n val pending_interrupts = high_interrupts | (read_mip & reg_mie)\n val d_interrupts = io.interrupts.debug << CSR.debugIntCause\n val (nmi_interrupts, nmiFlag) = io.interrupts.nmi.map(nmi =>\n (((nmi.rnmi && reg_rnmie) << CSR.rnmiIntCause) |\n io.interrupts.buserror.map(_ << CSR.rnmiBEUCause).getOrElse(0.U),\n !io.interrupts.debug && nmi.rnmi && reg_rnmie)).getOrElse(0.U, false.B)\n val m_interrupts = Mux(nmie && (reg_mstatus.prv <= PRV.S.U || reg_mstatus.mie), ~(~pending_interrupts | read_mideleg), 0.U)\n val s_interrupts = Mux(nmie && (reg_mstatus.v || reg_mstatus.prv < PRV.S.U || (reg_mstatus.prv === PRV.S.U && reg_mstatus.sie)), pending_interrupts & read_mideleg & ~read_hideleg, 0.U)\n val vs_interrupts = Mux(nmie && (reg_mstatus.v && (reg_mstatus.prv < PRV.S.U || reg_mstatus.prv === PRV.S.U && reg_vsstatus.sie)), pending_interrupts & read_hideleg, 0.U)\n val (anyInterrupt, whichInterrupt) = chooseInterrupt(Seq(vs_interrupts, s_interrupts, m_interrupts, nmi_interrupts, d_interrupts))\n val interruptMSB = BigInt(1) << (xLen-1)\n val interruptCause = interruptMSB.U + (nmiFlag << (xLen-2)) + whichInterrupt\n io.interrupt := (anyInterrupt && !io.singleStep || reg_singleStepped) && !(reg_debug || io.status.cease)\n io.interrupt_cause := interruptCause\n io.bp := reg_bp take nBreakpoints\n io.mcontext := reg_mcontext.getOrElse(0.U)\n io.scontext := reg_scontext.getOrElse(0.U)\n io.fiom := (reg_mstatus.prv < PRV.M.U && reg_menvcfg.fiom) || (reg_mstatus.prv < PRV.S.U && reg_senvcfg.fiom) || (reg_mstatus.v && reg_henvcfg.fiom)\n io.pmp := reg_pmp.map(PMP(_))\n\n val isaMaskString =\n (if (usingMulDiv) \"M\" else \"\") +\n (if (usingAtomics) \"A\" else \"\") +\n (if (fLen >= 32) \"F\" else \"\") +\n (if (fLen >= 64) \"D\" else \"\") +\n (if (coreParams.hasV) \"V\" else \"\") +\n (if (usingCompressed) \"C\" else \"\")\n val isaString = (if (coreParams.useRVE) \"E\" else \"I\") +\n isaMaskString +\n (if (customIsaExt.isDefined || usingRoCC) \"X\" else \"\") +\n (if (usingSupervisor) \"S\" else \"\") +\n (if (usingHypervisor) \"H\" else \"\") +\n (if (usingUser) \"U\" else \"\")\n val isaMax = (BigInt(log2Ceil(xLen) - 4) << (xLen-2)) | isaStringToMask(isaString)\n val reg_misa = RegInit(isaMax.U)\n val read_mstatus = io.status.asUInt.extract(xLen-1,0)\n val read_mtvec = formTVec(reg_mtvec).padTo(xLen)\n val read_stvec = formTVec(reg_stvec).sextTo(xLen)\n\n val read_mapping = LinkedHashMap[Int,Bits](\n CSRs.tselect -> reg_tselect,\n CSRs.tdata1 -> reg_bp(reg_tselect).control.asUInt,\n CSRs.tdata2 -> reg_bp(reg_tselect).address.sextTo(xLen),\n CSRs.tdata3 -> reg_bp(reg_tselect).textra.asUInt,\n CSRs.misa -> reg_misa,\n CSRs.mstatus -> read_mstatus,\n CSRs.mtvec -> read_mtvec,\n CSRs.mip -> read_mip,\n CSRs.mie -> reg_mie,\n CSRs.mscratch -> reg_mscratch,\n CSRs.mepc -> readEPC(reg_mepc).sextTo(xLen),\n CSRs.mtval -> reg_mtval.sextTo(xLen),\n CSRs.mcause -> reg_mcause,\n CSRs.mhartid -> io.hartid)\n\n val debug_csrs = if (!usingDebug) LinkedHashMap() else LinkedHashMap[Int,Bits](\n CSRs.dcsr -> reg_dcsr.asUInt,\n CSRs.dpc -> readEPC(reg_dpc).sextTo(xLen),\n CSRs.dscratch0 -> reg_dscratch0.asUInt) ++\n reg_dscratch1.map(r => CSRs.dscratch1 -> r)\n\n val read_mnstatus = WireInit(0.U.asTypeOf(new MNStatus()))\n read_mnstatus.mpp := reg_mnstatus.mpp\n read_mnstatus.mpv := reg_mnstatus.mpv\n read_mnstatus.mie := reg_rnmie\n val nmi_csrs = if (!usingNMI) LinkedHashMap() else LinkedHashMap[Int,Bits](\n CustomCSRs.mnscratch -> reg_mnscratch,\n CustomCSRs.mnepc -> readEPC(reg_mnepc).sextTo(xLen),\n CustomCSRs.mncause -> reg_mncause,\n CustomCSRs.mnstatus -> read_mnstatus.asUInt)\n\n val context_csrs = LinkedHashMap[Int,Bits]() ++\n reg_mcontext.map(r => CSRs.mcontext -> r) ++\n reg_scontext.map(r => CSRs.scontext -> r)\n\n val read_fcsr = Cat(reg_frm, reg_fflags)\n val fp_csrs = LinkedHashMap[Int,Bits]() ++\n usingFPU.option(CSRs.fflags -> reg_fflags) ++\n usingFPU.option(CSRs.frm -> reg_frm) ++\n (usingFPU || usingVector).option(CSRs.fcsr -> read_fcsr)\n\n val read_vcsr = Cat(reg_vxrm.getOrElse(0.U), reg_vxsat.getOrElse(0.U))\n val vector_csrs = if (!usingVector) LinkedHashMap() else LinkedHashMap[Int,Bits](\n CSRs.vxsat -> reg_vxsat.get,\n CSRs.vxrm -> reg_vxrm.get,\n CSRs.vcsr -> read_vcsr,\n CSRs.vstart -> reg_vstart.get,\n CSRs.vtype -> reg_vconfig.get.vtype.asUInt,\n CSRs.vl -> reg_vconfig.get.vl,\n CSRs.vlenb -> (vLen / 8).U)\n\n read_mapping ++= debug_csrs\n read_mapping ++= nmi_csrs\n read_mapping ++= context_csrs\n read_mapping ++= fp_csrs\n read_mapping ++= vector_csrs\n\n if (coreParams.haveBasicCounters) {\n read_mapping += CSRs.mcountinhibit -> reg_mcountinhibit\n read_mapping += CSRs.mcycle -> reg_cycle\n read_mapping += CSRs.minstret -> reg_instret\n\n for (((e, c), i) <- (reg_hpmevent.padTo(CSR.nHPM, 0.U)\n zip reg_hpmcounter.map(x => x: UInt).padTo(CSR.nHPM, 0.U)).zipWithIndex) {\n read_mapping += (i + CSR.firstHPE) -> e // mhpmeventN\n read_mapping += (i + CSR.firstMHPC) -> c // mhpmcounterN\n read_mapping += (i + CSR.firstHPC) -> c // hpmcounterN\n if (xLen == 32) {\n read_mapping += (i + CSR.firstMHPCH) -> (c >> 32) // mhpmcounterNh\n read_mapping += (i + CSR.firstHPCH) -> (c >> 32) // hpmcounterNh\n }\n }\n\n if (usingUser) {\n read_mapping += CSRs.mcounteren -> read_mcounteren\n }\n read_mapping += CSRs.cycle -> reg_cycle\n read_mapping += CSRs.instret -> reg_instret\n\n if (xLen == 32) {\n read_mapping += CSRs.mcycleh -> (reg_cycle >> 32)\n read_mapping += CSRs.minstreth -> (reg_instret >> 32)\n read_mapping += CSRs.cycleh -> (reg_cycle >> 32)\n read_mapping += CSRs.instreth -> (reg_instret >> 32)\n }\n }\n\n if (usingUser) {\n read_mapping += CSRs.menvcfg -> reg_menvcfg.asUInt\n if (xLen == 32)\n read_mapping += CSRs.menvcfgh -> (reg_menvcfg.asUInt >> 32)\n }\n\n val sie_mask = {\n val sgeip_mask = WireInit(0.U.asTypeOf(new MIP))\n sgeip_mask.sgeip := true.B\n read_mideleg & ~(hs_delegable_interrupts | sgeip_mask.asUInt)\n }\n if (usingSupervisor) {\n val read_sie = reg_mie & sie_mask\n val read_sip = read_mip & sie_mask\n val read_sstatus = WireDefault(0.U.asTypeOf(new MStatus))\n read_sstatus.sd := io.status.sd\n read_sstatus.uxl := io.status.uxl\n read_sstatus.sd_rv32 := io.status.sd_rv32\n read_sstatus.mxr := io.status.mxr\n read_sstatus.sum := io.status.sum\n read_sstatus.xs := io.status.xs\n read_sstatus.fs := io.status.fs\n read_sstatus.vs := io.status.vs\n read_sstatus.spp := io.status.spp\n read_sstatus.spie := io.status.spie\n read_sstatus.sie := io.status.sie\n\n read_mapping += CSRs.sstatus -> (read_sstatus.asUInt)(xLen-1,0)\n read_mapping += CSRs.sip -> read_sip.asUInt\n read_mapping += CSRs.sie -> read_sie.asUInt\n read_mapping += CSRs.sscratch -> reg_sscratch\n read_mapping += CSRs.scause -> reg_scause\n read_mapping += CSRs.stval -> reg_stval.sextTo(xLen)\n read_mapping += CSRs.satp -> reg_satp.asUInt\n read_mapping += CSRs.sepc -> readEPC(reg_sepc).sextTo(xLen)\n read_mapping += CSRs.stvec -> read_stvec\n read_mapping += CSRs.scounteren -> read_scounteren\n read_mapping += CSRs.mideleg -> read_mideleg\n read_mapping += CSRs.medeleg -> read_medeleg\n read_mapping += CSRs.senvcfg -> reg_senvcfg.asUInt\n }\n\n val pmpCfgPerCSR = xLen / new PMPConfig().getWidth\n def pmpCfgIndex(i: Int) = (xLen / 32) * (i / pmpCfgPerCSR)\n if (reg_pmp.nonEmpty) {\n require(reg_pmp.size <= CSR.maxPMPs)\n val read_pmp = reg_pmp.padTo(CSR.maxPMPs, 0.U.asTypeOf(new PMP))\n for (i <- 0 until read_pmp.size by pmpCfgPerCSR)\n read_mapping += (CSRs.pmpcfg0 + pmpCfgIndex(i)) -> read_pmp.map(_.cfg).slice(i, i + pmpCfgPerCSR).asUInt\n for ((pmp, i) <- read_pmp.zipWithIndex)\n read_mapping += (CSRs.pmpaddr0 + i) -> pmp.readAddr\n }\n\n // implementation-defined CSRs\n def generateCustomCSR(csr: CustomCSR, csr_io: CustomCSRIO) = {\n require(csr.mask >= 0 && csr.mask.bitLength <= xLen)\n require(!read_mapping.contains(csr.id))\n val reg = csr.init.map(init => RegInit(init.U(xLen.W))).getOrElse(Reg(UInt(xLen.W)))\n val read = io.rw.cmd =/= CSR.N && io.rw.addr === csr.id.U\n csr_io.ren := read\n when (read && csr_io.stall) { io.rw_stall := true.B }\n read_mapping += csr.id -> reg\n reg\n }\n val reg_custom = customCSRs.zip(io.customCSRs).map(t => generateCustomCSR(t._1, t._2))\n val reg_rocc = roccCSRs.zip(io.roccCSRs).map(t => generateCustomCSR(t._1, t._2))\n\n if (usingHypervisor) {\n read_mapping += CSRs.mtinst -> read_mtinst\n read_mapping += CSRs.mtval2 -> reg_mtval2\n\n val read_hstatus = io.hstatus.asUInt.extract(xLen-1,0)\n\n read_mapping += CSRs.hstatus -> read_hstatus\n read_mapping += CSRs.hedeleg -> read_hedeleg\n read_mapping += CSRs.hideleg -> read_hideleg\n read_mapping += CSRs.hcounteren-> read_hcounteren\n read_mapping += CSRs.hgatp -> reg_hgatp.asUInt\n read_mapping += CSRs.hip -> read_hip\n read_mapping += CSRs.hie -> read_hie\n read_mapping += CSRs.hvip -> read_hvip\n read_mapping += CSRs.hgeie -> 0.U\n read_mapping += CSRs.hgeip -> 0.U\n read_mapping += CSRs.htval -> reg_htval\n read_mapping += CSRs.htinst -> read_htinst\n read_mapping += CSRs.henvcfg -> reg_henvcfg.asUInt\n if (xLen == 32)\n read_mapping += CSRs.henvcfgh -> (reg_henvcfg.asUInt >> 32)\n\n val read_vsie = (read_hie & read_hideleg) >> 1\n val read_vsip = (read_hip & read_hideleg) >> 1\n val read_vsepc = readEPC(reg_vsepc).sextTo(xLen)\n val read_vstval = reg_vstval.sextTo(xLen)\n val read_vsstatus = io.gstatus.asUInt.extract(xLen-1,0)\n\n read_mapping += CSRs.vsstatus -> read_vsstatus\n read_mapping += CSRs.vsip -> read_vsip\n read_mapping += CSRs.vsie -> read_vsie\n read_mapping += CSRs.vsscratch -> reg_vsscratch\n read_mapping += CSRs.vscause -> reg_vscause\n read_mapping += CSRs.vstval -> read_vstval\n read_mapping += CSRs.vsatp -> reg_vsatp.asUInt\n read_mapping += CSRs.vsepc -> read_vsepc\n read_mapping += CSRs.vstvec -> read_vstvec\n }\n\n // mimpid, marchid, mvendorid, and mconfigptr are 0 unless overridden by customCSRs\n Seq(CSRs.mimpid, CSRs.marchid, CSRs.mvendorid, CSRs.mconfigptr).foreach(id => read_mapping.getOrElseUpdate(id, 0.U))\n\n val decoded_addr = {\n val addr = Cat(io.status.v, io.rw.addr)\n val pats = for (((k, _), i) <- read_mapping.zipWithIndex)\n yield (BitPat(k.U), (0 until read_mapping.size).map(j => BitPat((i == j).B)))\n val decoded = DecodeLogic(addr, Seq.fill(read_mapping.size)(X), pats)\n val unvirtualized_mapping = (for (((k, _), v) <- read_mapping zip decoded) yield k -> v.asBool).toMap\n\n for ((k, v) <- unvirtualized_mapping) yield k -> {\n val alt: Option[Bool] = CSR.mode(k) match {\n // hcontext was assigned an unfortunate address; it lives where a\n // hypothetical vscontext will live. Exclude them from the S/VS remapping.\n // (on separate lines so scala-lint doesnt do something stupid)\n case _ if k == CSRs.scontext => None\n case _ if k == CSRs.hcontext => None\n // When V=1, if a corresponding VS CSR exists, access it instead...\n case PRV.H => unvirtualized_mapping.lift(k - (1 << CSR.modeLSB))\n // ...and don't access the original S-mode version.\n case PRV.S => unvirtualized_mapping.contains(k + (1 << CSR.modeLSB)).option(false.B)\n case _ => None\n }\n alt.map(Mux(reg_mstatus.v, _, v)).getOrElse(v)\n }\n }\n\n val wdata = readModifyWriteCSR(io.rw.cmd, io.rw.rdata, io.rw.wdata)\n\n val system_insn = io.rw.cmd === CSR.I\n val hlsv = Seq(HLV_B, HLV_BU, HLV_H, HLV_HU, HLV_W, HLV_WU, HLV_D, HSV_B, HSV_H, HSV_W, HSV_D, HLVX_HU, HLVX_WU)\n val decode_table = Seq( ECALL-> List(Y,N,N,N,N,N,N,N,N),\n EBREAK-> List(N,Y,N,N,N,N,N,N,N),\n MRET-> List(N,N,Y,N,N,N,N,N,N),\n CEASE-> List(N,N,N,Y,N,N,N,N,N),\n WFI-> List(N,N,N,N,Y,N,N,N,N)) ++\n usingDebug.option( DRET-> List(N,N,Y,N,N,N,N,N,N)) ++\n usingNMI.option( MNRET-> List(N,N,Y,N,N,N,N,N,N)) ++\n coreParams.haveCFlush.option(CFLUSH_D_L1-> List(N,N,N,N,N,N,N,N,N)) ++\n usingSupervisor.option( SRET-> List(N,N,Y,N,N,N,N,N,N)) ++\n usingVM.option( SFENCE_VMA-> List(N,N,N,N,N,Y,N,N,N)) ++\n usingHypervisor.option( HFENCE_VVMA-> List(N,N,N,N,N,N,Y,N,N)) ++\n usingHypervisor.option( HFENCE_GVMA-> List(N,N,N,N,N,N,N,Y,N)) ++\n (if (usingHypervisor) hlsv.map(_-> List(N,N,N,N,N,N,N,N,Y)) else Seq())\n val insn_call :: insn_break :: insn_ret :: insn_cease :: insn_wfi :: _ :: _ :: _ :: _ :: Nil = {\n val insn = ECALL.value.U | (io.rw.addr << 20)\n DecodeLogic(insn, decode_table(0)._2.map(x=>X), decode_table).map(system_insn && _.asBool)\n }\n\n for (io_dec <- io.decode) {\n val addr = io_dec.inst(31, 20)\n\n def decodeAny(m: LinkedHashMap[Int,Bits]): Bool = m.map { case(k: Int, _: Bits) => addr === k.U }.reduce(_||_)\n def decodeFast(s: Seq[Int]): Bool = DecodeLogic(addr, s.map(_.U), (read_mapping -- s).keys.toList.map(_.U))\n\n val _ :: is_break :: is_ret :: _ :: is_wfi :: is_sfence :: is_hfence_vvma :: is_hfence_gvma :: is_hlsv :: Nil =\n DecodeLogic(io_dec.inst, decode_table(0)._2.map(x=>X), decode_table).map(_.asBool)\n val is_counter = (addr.inRange(CSR.firstCtr.U, (CSR.firstCtr + CSR.nCtr).U) || addr.inRange(CSR.firstCtrH.U, (CSR.firstCtrH + CSR.nCtr).U))\n\n val allow_wfi = (!usingSupervisor).B || reg_mstatus.prv > PRV.S.U || !reg_mstatus.tw && (!reg_mstatus.v || !reg_hstatus.vtw)\n val allow_sfence_vma = (!usingVM).B || reg_mstatus.prv > PRV.S.U || !Mux(reg_mstatus.v, reg_hstatus.vtvm, reg_mstatus.tvm)\n val allow_hfence_vvma = (!usingHypervisor).B || !reg_mstatus.v && (reg_mstatus.prv >= PRV.S.U)\n val allow_hlsv = (!usingHypervisor).B || !reg_mstatus.v && (reg_mstatus.prv >= PRV.S.U || reg_hstatus.hu)\n val allow_sret = (!usingSupervisor).B || reg_mstatus.prv > PRV.S.U || !Mux(reg_mstatus.v, reg_hstatus.vtsr, reg_mstatus.tsr)\n val counter_addr = addr(log2Ceil(read_mcounteren.getWidth)-1, 0)\n val allow_counter = (reg_mstatus.prv > PRV.S.U || read_mcounteren(counter_addr)) &&\n (!usingSupervisor.B || reg_mstatus.prv >= PRV.S.U || read_scounteren(counter_addr)) &&\n (!usingHypervisor.B || !reg_mstatus.v || read_hcounteren(counter_addr))\n io_dec.fp_illegal := io.status.fs === 0.U || reg_mstatus.v && reg_vsstatus.fs === 0.U || !reg_misa('f'-'a')\n io_dec.vector_illegal := io.status.vs === 0.U || reg_mstatus.v && reg_vsstatus.vs === 0.U || !reg_misa('v'-'a')\n io_dec.fp_csr := decodeFast(fp_csrs.keys.toList)\n io_dec.vector_csr := decodeFast(vector_csrs.keys.toList)\n io_dec.rocc_illegal := io.status.xs === 0.U || reg_mstatus.v && reg_vsstatus.xs === 0.U || !reg_misa('x'-'a')\n val csr_addr_legal = reg_mstatus.prv >= CSR.mode(addr) ||\n usingHypervisor.B && !reg_mstatus.v && reg_mstatus.prv === PRV.S.U && CSR.mode(addr) === PRV.H.U\n val csr_exists = decodeAny(read_mapping)\n io_dec.read_illegal := !csr_addr_legal ||\n !csr_exists ||\n ((addr === CSRs.satp.U || addr === CSRs.hgatp.U) && !allow_sfence_vma) ||\n is_counter && !allow_counter ||\n decodeFast(debug_csrs.keys.toList) && !reg_debug ||\n decodeFast(vector_csrs.keys.toList) && io_dec.vector_illegal ||\n io_dec.fp_csr && io_dec.fp_illegal\n io_dec.write_illegal := addr(11,10).andR\n io_dec.write_flush := {\n val addr_m = addr | (PRV.M.U << CSR.modeLSB)\n !(addr_m >= CSRs.mscratch.U && addr_m <= CSRs.mtval.U)\n }\n io_dec.system_illegal := !csr_addr_legal && !is_hlsv ||\n is_wfi && !allow_wfi ||\n is_ret && !allow_sret ||\n is_ret && addr(10) && addr(7) && !reg_debug ||\n (is_sfence || is_hfence_gvma) && !allow_sfence_vma ||\n is_hfence_vvma && !allow_hfence_vvma ||\n is_hlsv && !allow_hlsv\n\n io_dec.virtual_access_illegal := reg_mstatus.v && csr_exists && (\n CSR.mode(addr) === PRV.H.U ||\n is_counter && read_mcounteren(counter_addr) && (!read_hcounteren(counter_addr) || !reg_mstatus.prv(0) && !read_scounteren(counter_addr)) ||\n CSR.mode(addr) === PRV.S.U && !reg_mstatus.prv(0) ||\n addr === CSRs.satp.U && reg_mstatus.prv(0) && reg_hstatus.vtvm)\n\n io_dec.virtual_system_illegal := reg_mstatus.v && (\n is_hfence_vvma ||\n is_hfence_gvma ||\n is_hlsv ||\n is_wfi && (!reg_mstatus.prv(0) || !reg_mstatus.tw && reg_hstatus.vtw) ||\n is_ret && CSR.mode(addr) === PRV.S.U && (!reg_mstatus.prv(0) || reg_hstatus.vtsr) ||\n is_sfence && (!reg_mstatus.prv(0) || reg_hstatus.vtvm))\n }\n\n val cause =\n Mux(insn_call, Causes.user_ecall.U + Mux(reg_mstatus.prv(0) && reg_mstatus.v, PRV.H.U, reg_mstatus.prv),\n Mux[UInt](insn_break, Causes.breakpoint.U, io.cause))\n val cause_lsbs = cause(log2Ceil(1 + CSR.busErrorIntCause)-1, 0)\n val cause_deleg_lsbs = cause(log2Ceil(xLen)-1,0)\n val causeIsDebugInt = cause(xLen-1) && cause_lsbs === CSR.debugIntCause.U\n val causeIsDebugTrigger = !cause(xLen-1) && cause_lsbs === CSR.debugTriggerCause.U\n val causeIsDebugBreak = !cause(xLen-1) && insn_break && Cat(reg_dcsr.ebreakm, reg_dcsr.ebreakh, reg_dcsr.ebreaks, reg_dcsr.ebreaku)(reg_mstatus.prv)\n val trapToDebug = usingDebug.B && (reg_singleStepped || causeIsDebugInt || causeIsDebugTrigger || causeIsDebugBreak || reg_debug)\n val debugEntry = p(DebugModuleKey).map(_.debugEntry).getOrElse(BigInt(0x800))\n val debugException = p(DebugModuleKey).map(_.debugException).getOrElse(BigInt(0x808))\n val debugTVec = Mux(reg_debug, Mux(insn_break, debugEntry.U, debugException.U), debugEntry.U)\n val delegate = usingSupervisor.B && reg_mstatus.prv <= PRV.S.U && Mux(cause(xLen-1), read_mideleg(cause_deleg_lsbs), read_medeleg(cause_deleg_lsbs))\n val delegateVS = reg_mstatus.v && delegate && Mux(cause(xLen-1), read_hideleg(cause_deleg_lsbs), read_hedeleg(cause_deleg_lsbs))\n def mtvecBaseAlign = 2\n def mtvecInterruptAlign = {\n require(reg_mip.getWidth <= xLen)\n log2Ceil(xLen)\n }\n val notDebugTVec = {\n val base = Mux(delegate, Mux(delegateVS, read_vstvec, read_stvec), read_mtvec)\n val interruptOffset = cause(mtvecInterruptAlign-1, 0) << mtvecBaseAlign\n val interruptVec = Cat(base >> (mtvecInterruptAlign + mtvecBaseAlign), interruptOffset)\n val doVector = base(0) && cause(cause.getWidth-1) && (cause_lsbs >> mtvecInterruptAlign) === 0.U\n Mux(doVector, interruptVec, base >> mtvecBaseAlign << mtvecBaseAlign)\n }\n\n val causeIsRnmiInt = cause(xLen-1) && cause(xLen-2) && (cause_lsbs === CSR.rnmiIntCause.U || cause_lsbs === CSR.rnmiBEUCause.U)\n val causeIsRnmiBEU = cause(xLen-1) && cause(xLen-2) && cause_lsbs === CSR.rnmiBEUCause.U\n val causeIsNmi = causeIsRnmiInt\n val nmiTVecInt = io.interrupts.nmi.map(nmi => nmi.rnmi_interrupt_vector).getOrElse(0.U)\n val nmiTVecXcpt = io.interrupts.nmi.map(nmi => nmi.rnmi_exception_vector).getOrElse(0.U)\n val trapToNmiInt = usingNMI.B && causeIsNmi\n val trapToNmiXcpt = usingNMI.B && !nmie\n val trapToNmi = trapToNmiInt || trapToNmiXcpt\n val nmiTVec = (Mux(causeIsNmi, nmiTVecInt, nmiTVecXcpt)>>1)<<1\n\n val tvec = Mux(trapToDebug, debugTVec, Mux(trapToNmi, nmiTVec, notDebugTVec))\n io.evec := tvec\n io.ptbr := reg_satp\n io.hgatp := reg_hgatp\n io.vsatp := reg_vsatp\n io.eret := insn_call || insn_break || insn_ret\n io.singleStep := reg_dcsr.step && !reg_debug\n io.status := reg_mstatus\n io.status.sd := io.status.fs.andR || io.status.xs.andR || io.status.vs.andR\n io.status.debug := reg_debug\n io.status.isa := reg_misa\n io.status.uxl := (if (usingUser) log2Ceil(xLen) - 4 else 0).U\n io.status.sxl := (if (usingSupervisor) log2Ceil(xLen) - 4 else 0).U\n io.status.dprv := Mux(reg_mstatus.mprv && !reg_debug, reg_mstatus.mpp, reg_mstatus.prv)\n io.status.dv := reg_mstatus.v || Mux(reg_mstatus.mprv && !reg_debug, reg_mstatus.mpv, false.B)\n io.status.sd_rv32 := (xLen == 32).B && io.status.sd\n io.status.mpv := reg_mstatus.mpv\n io.status.gva := reg_mstatus.gva\n io.hstatus := reg_hstatus\n io.hstatus.vsxl := (if (usingSupervisor) log2Ceil(xLen) - 4 else 0).U\n io.gstatus := reg_vsstatus\n io.gstatus.sd := io.gstatus.fs.andR || io.gstatus.xs.andR || io.gstatus.vs.andR\n io.gstatus.uxl := (if (usingUser) log2Ceil(xLen) - 4 else 0).U\n io.gstatus.sd_rv32 := (xLen == 32).B && io.gstatus.sd\n\n val exception = insn_call || insn_break || io.exception\n assert(PopCount(insn_ret :: insn_call :: insn_break :: io.exception :: Nil) <= 1.U, \"these conditions must be mutually exclusive\")\n\n when (insn_wfi && !io.singleStep && !reg_debug) { reg_wfi := true.B }\n when (pending_interrupts.orR || io.interrupts.debug || exception) { reg_wfi := false.B }\n io.interrupts.nmi.map(nmi => when (nmi.rnmi) { reg_wfi := false.B } )\n\n when (io.retire(0) || exception) { reg_singleStepped := true.B }\n when (!io.singleStep) { reg_singleStepped := false.B }\n assert(!io.singleStep || io.retire <= 1.U)\n assert(!reg_singleStepped || io.retire === 0.U)\n\n val epc = formEPC(io.pc)\n val tval = Mux(insn_break, epc, io.tval)\n\n when (exception) {\n when (trapToDebug) {\n when (!reg_debug) {\n reg_mstatus.v := false.B\n reg_debug := true.B\n reg_dpc := epc\n reg_dcsr.cause := Mux(reg_singleStepped, 4.U, Mux(causeIsDebugInt, 3.U, Mux[UInt](causeIsDebugTrigger, 2.U, 1.U)))\n reg_dcsr.prv := trimPrivilege(reg_mstatus.prv)\n reg_dcsr.v := reg_mstatus.v\n new_prv := PRV.M.U\n }\n }.elsewhen (trapToNmiInt) {\n when (reg_rnmie) {\n reg_mstatus.v := false.B\n reg_mnstatus.mpv := reg_mstatus.v\n reg_rnmie := false.B\n reg_mnepc := epc\n reg_mncause := (BigInt(1) << (xLen-1)).U | Mux(causeIsRnmiBEU, 3.U, 2.U)\n reg_mnstatus.mpp := trimPrivilege(reg_mstatus.prv)\n new_prv := PRV.M.U\n }\n }.elsewhen (delegateVS && nmie) {\n reg_mstatus.v := true.B\n reg_vsstatus.spp := reg_mstatus.prv\n reg_vsepc := epc\n reg_vscause := Mux(cause(xLen-1), Cat(cause(xLen-1, 2), 1.U(2.W)), cause)\n reg_vstval := tval\n reg_vsstatus.spie := reg_vsstatus.sie\n reg_vsstatus.sie := false.B\n new_prv := PRV.S.U\n }.elsewhen (delegate && nmie) {\n reg_mstatus.v := false.B\n reg_hstatus.spvp := Mux(reg_mstatus.v, reg_mstatus.prv(0),reg_hstatus.spvp)\n reg_hstatus.gva := io.gva\n reg_hstatus.spv := reg_mstatus.v\n reg_sepc := epc\n reg_scause := cause\n reg_stval := tval\n reg_htval := io.htval\n reg_htinst_read_pseudo := io.mhtinst_read_pseudo\n reg_mstatus.spie := reg_mstatus.sie\n reg_mstatus.spp := reg_mstatus.prv\n reg_mstatus.sie := false.B\n new_prv := PRV.S.U\n }.otherwise {\n reg_mstatus.v := false.B\n reg_mstatus.mpv := reg_mstatus.v\n reg_mstatus.gva := io.gva\n reg_mepc := epc\n reg_mcause := cause\n reg_mtval := tval\n reg_mtval2 := io.htval\n reg_mtinst_read_pseudo := io.mhtinst_read_pseudo\n reg_mstatus.mpie := reg_mstatus.mie\n reg_mstatus.mpp := trimPrivilege(reg_mstatus.prv)\n reg_mstatus.mie := false.B\n new_prv := PRV.M.U\n }\n }\n\n for (i <- 0 until supported_interrupts.getWidth) {\n val en = exception && (supported_interrupts & (BigInt(1) << i).U) =/= 0.U && cause === (BigInt(1) << (xLen - 1)).U + i.U\n val delegable = (delegable_interrupts & (BigInt(1) << i).U) =/= 0.U\n property.cover(en && !delegate, s\"INTERRUPT_M_$i\")\n property.cover(en && delegable && delegate, s\"INTERRUPT_S_$i\")\n }\n for (i <- 0 until xLen) {\n val supported_exceptions: BigInt = 0x8fe |\n (if (usingCompressed && !coreParams.misaWritable) 0 else 1) |\n (if (usingUser) 0x100 else 0) |\n (if (usingSupervisor) 0x200 else 0) |\n (if (usingVM) 0xb000 else 0)\n if (((supported_exceptions >> i) & 1) != 0) {\n val en = exception && cause === i.U\n val delegable = (delegable_exceptions & (BigInt(1) << i).U) =/= 0.U\n property.cover(en && !delegate, s\"EXCEPTION_M_$i\")\n property.cover(en && delegable && delegate, s\"EXCEPTION_S_$i\")\n }\n }\n\n when (insn_ret) {\n val ret_prv = WireInit(UInt(), DontCare)\n when (usingSupervisor.B && !io.rw.addr(9)) {\n when (!reg_mstatus.v) {\n reg_mstatus.sie := reg_mstatus.spie\n reg_mstatus.spie := true.B\n reg_mstatus.spp := PRV.U.U\n ret_prv := reg_mstatus.spp\n reg_mstatus.v := usingHypervisor.B && reg_hstatus.spv\n io.evec := readEPC(reg_sepc)\n reg_hstatus.spv := false.B\n }.otherwise {\n reg_vsstatus.sie := reg_vsstatus.spie\n reg_vsstatus.spie := true.B\n reg_vsstatus.spp := PRV.U.U\n ret_prv := reg_vsstatus.spp\n reg_mstatus.v := usingHypervisor.B\n io.evec := readEPC(reg_vsepc)\n }\n }.elsewhen (usingDebug.B && io.rw.addr(10) && io.rw.addr(7)) {\n ret_prv := reg_dcsr.prv\n reg_mstatus.v := usingHypervisor.B && reg_dcsr.v && reg_dcsr.prv <= PRV.S.U\n reg_debug := false.B\n io.evec := readEPC(reg_dpc)\n }.elsewhen (usingNMI.B && io.rw.addr(10) && !io.rw.addr(7)) {\n ret_prv := reg_mnstatus.mpp\n reg_mstatus.v := usingHypervisor.B && reg_mnstatus.mpv && reg_mnstatus.mpp <= PRV.S.U\n reg_rnmie := true.B\n io.evec := readEPC(reg_mnepc)\n }.otherwise {\n reg_mstatus.mie := reg_mstatus.mpie\n reg_mstatus.mpie := true.B\n reg_mstatus.mpp := legalizePrivilege(PRV.U.U)\n reg_mstatus.mpv := false.B\n ret_prv := reg_mstatus.mpp\n reg_mstatus.v := usingHypervisor.B && reg_mstatus.mpv && reg_mstatus.mpp <= PRV.S.U\n io.evec := readEPC(reg_mepc)\n }\n\n new_prv := ret_prv\n when (usingUser.B && ret_prv <= PRV.S.U) {\n reg_mstatus.mprv := false.B\n }\n }\n\n io.time := reg_cycle\n io.csr_stall := reg_wfi || io.status.cease\n io.status.cease := RegEnable(true.B, false.B, insn_cease)\n io.status.wfi := reg_wfi\n\n for ((io, reg) <- io.customCSRs zip reg_custom) {\n io.wen := false.B\n io.wdata := wdata\n io.value := reg\n }\n\n for ((io, reg) <- io.roccCSRs zip reg_rocc) {\n io.wen := false.B\n io.wdata := wdata\n io.value := reg\n }\n\n io.rw.rdata := Mux1H(for ((k, v) <- read_mapping) yield decoded_addr(k) -> v)\n\n // cover access to register\n val coverable_counters = read_mapping.filterNot { case (k, _) =>\n k >= CSR.firstHPC + nPerfCounters && k < CSR.firstHPC + CSR.nHPM\n }\n coverable_counters.foreach( {case (k, v) => {\n when (!k.U(11,10).andR) { // Cover points for RW CSR registers\n property.cover(io.rw.cmd.isOneOf(CSR.W, CSR.S, CSR.C) && io.rw.addr===k.U, \"CSR_access_\"+k.toString, \"Cover Accessing Core CSR field\")\n } .otherwise { // Cover points for RO CSR registers\n property.cover(io.rw.cmd===CSR.R && io.rw.addr===k.U, \"CSR_access_\"+k.toString, \"Cover Accessing Core CSR field\")\n }\n }})\n\n val set_vs_dirty = WireDefault(io.vector.map(_.set_vs_dirty).getOrElse(false.B))\n io.vector.foreach { vio =>\n when (set_vs_dirty) {\n assert(reg_mstatus.vs > 0.U)\n when (reg_mstatus.v) { reg_vsstatus.vs := 3.U }\n reg_mstatus.vs := 3.U\n }\n }\n\n val set_fs_dirty = WireDefault(io.set_fs_dirty.getOrElse(false.B))\n if (coreParams.haveFSDirty) {\n when (set_fs_dirty) {\n assert(reg_mstatus.fs > 0.U)\n when (reg_mstatus.v) { reg_vsstatus.fs := 3.U }\n reg_mstatus.fs := 3.U\n }\n }\n\n io.fcsr_rm := reg_frm\n when (io.fcsr_flags.valid) {\n reg_fflags := reg_fflags | io.fcsr_flags.bits\n set_fs_dirty := true.B\n }\n\n io.vector.foreach { vio =>\n when (vio.set_vxsat) {\n reg_vxsat.get := true.B\n set_vs_dirty := true.B\n }\n }\n\n val csr_wen = io.rw.cmd.isOneOf(CSR.S, CSR.C, CSR.W) && !io.rw_stall\n io.csrw_counter := Mux(coreParams.haveBasicCounters.B && csr_wen && (io.rw.addr.inRange(CSRs.mcycle.U, (CSRs.mcycle + CSR.nCtr).U) || io.rw.addr.inRange(CSRs.mcycleh.U, (CSRs.mcycleh + CSR.nCtr).U)), UIntToOH(io.rw.addr(log2Ceil(CSR.nCtr+nPerfCounters)-1, 0)), 0.U)\n when (csr_wen) {\n val scause_mask = ((BigInt(1) << (xLen-1)) + 31).U /* only implement 5 LSBs and MSB */\n val satp_valid_modes = 0 +: (minPgLevels to pgLevels).map(new PTBR().pgLevelsToMode(_))\n\n when (decoded_addr(CSRs.mstatus)) {\n val new_mstatus = wdata.asTypeOf(new MStatus())\n reg_mstatus.mie := new_mstatus.mie\n reg_mstatus.mpie := new_mstatus.mpie\n\n if (usingUser) {\n reg_mstatus.mprv := new_mstatus.mprv\n reg_mstatus.mpp := legalizePrivilege(new_mstatus.mpp)\n if (usingSupervisor) {\n reg_mstatus.spp := new_mstatus.spp\n reg_mstatus.spie := new_mstatus.spie\n reg_mstatus.sie := new_mstatus.sie\n reg_mstatus.tw := new_mstatus.tw\n reg_mstatus.tsr := new_mstatus.tsr\n }\n if (usingVM) {\n reg_mstatus.mxr := new_mstatus.mxr\n reg_mstatus.sum := new_mstatus.sum\n reg_mstatus.tvm := new_mstatus.tvm\n }\n if (usingHypervisor) {\n reg_mstatus.mpv := new_mstatus.mpv\n reg_mstatus.gva := new_mstatus.gva\n }\n }\n\n if (usingSupervisor || usingFPU) reg_mstatus.fs := formFS(new_mstatus.fs)\n reg_mstatus.vs := formVS(new_mstatus.vs)\n }\n when (decoded_addr(CSRs.misa)) {\n val mask = isaStringToMask(isaMaskString).U(xLen.W)\n val f = wdata('f' - 'a')\n // suppress write if it would cause the next fetch to be misaligned\n when (!usingCompressed.B || !io.pc(1) || wdata('c' - 'a')) {\n if (coreParams.misaWritable)\n reg_misa := ~(~wdata | (!f << ('d' - 'a'))) & mask | reg_misa & ~mask\n }\n }\n when (decoded_addr(CSRs.mip)) {\n // MIP should be modified based on the value in reg_mip, not the value\n // in read_mip, since read_mip.seip is the OR of reg_mip.seip and\n // io.interrupts.seip. We don't want the value on the PLIC line to\n // inadvertently be OR'd into read_mip.seip.\n val new_mip = readModifyWriteCSR(io.rw.cmd, reg_mip.asUInt, io.rw.wdata).asTypeOf(new MIP)\n if (usingSupervisor) {\n reg_mip.ssip := new_mip.ssip\n reg_mip.stip := new_mip.stip\n reg_mip.seip := new_mip.seip\n }\n if (usingHypervisor) {\n reg_mip.vssip := new_mip.vssip\n }\n }\n when (decoded_addr(CSRs.mie)) { reg_mie := wdata & supported_interrupts }\n when (decoded_addr(CSRs.mepc)) { reg_mepc := formEPC(wdata) }\n when (decoded_addr(CSRs.mscratch)) { reg_mscratch := wdata }\n if (mtvecWritable)\n when (decoded_addr(CSRs.mtvec)) { reg_mtvec := wdata }\n when (decoded_addr(CSRs.mcause)) { reg_mcause := wdata & ((BigInt(1) << (xLen-1)) + (BigInt(1) << whichInterrupt.getWidth) - 1).U }\n when (decoded_addr(CSRs.mtval)) { reg_mtval := wdata }\n\n if (usingNMI) {\n val new_mnstatus = wdata.asTypeOf(new MNStatus())\n when (decoded_addr(CustomCSRs.mnscratch)) { reg_mnscratch := wdata }\n when (decoded_addr(CustomCSRs.mnepc)) { reg_mnepc := formEPC(wdata) }\n when (decoded_addr(CustomCSRs.mncause)) { reg_mncause := wdata & ((BigInt(1) << (xLen-1)) + BigInt(3)).U }\n when (decoded_addr(CustomCSRs.mnstatus)) {\n reg_mnstatus.mpp := legalizePrivilege(new_mnstatus.mpp)\n reg_mnstatus.mpv := usingHypervisor.B && new_mnstatus.mpv\n reg_rnmie := reg_rnmie | new_mnstatus.mie // mnie bit settable but not clearable from software\n }\n }\n\n for (((e, c), i) <- (reg_hpmevent zip reg_hpmcounter).zipWithIndex) {\n writeCounter(i + CSR.firstMHPC, c, wdata)\n when (decoded_addr(i + CSR.firstHPE)) { e := perfEventSets.maskEventSelector(wdata) }\n }\n if (coreParams.haveBasicCounters) {\n when (decoded_addr(CSRs.mcountinhibit)) { reg_mcountinhibit := wdata & ~2.U(xLen.W) } // mcountinhibit bit [1] is tied zero\n writeCounter(CSRs.mcycle, reg_cycle, wdata)\n writeCounter(CSRs.minstret, reg_instret, wdata)\n }\n\n if (usingFPU) {\n when (decoded_addr(CSRs.fflags)) { set_fs_dirty := true.B; reg_fflags := wdata }\n when (decoded_addr(CSRs.frm)) { set_fs_dirty := true.B; reg_frm := wdata }\n when (decoded_addr(CSRs.fcsr)) {\n set_fs_dirty := true.B\n reg_fflags := wdata\n reg_frm := wdata >> reg_fflags.getWidth\n }\n }\n if (usingDebug) {\n when (decoded_addr(CSRs.dcsr)) {\n val new_dcsr = wdata.asTypeOf(new DCSR())\n reg_dcsr.step := new_dcsr.step\n reg_dcsr.ebreakm := new_dcsr.ebreakm\n if (usingSupervisor) reg_dcsr.ebreaks := new_dcsr.ebreaks\n if (usingUser) reg_dcsr.ebreaku := new_dcsr.ebreaku\n if (usingUser) reg_dcsr.prv := legalizePrivilege(new_dcsr.prv)\n if (usingHypervisor) reg_dcsr.v := new_dcsr.v\n }\n when (decoded_addr(CSRs.dpc)) { reg_dpc := formEPC(wdata) }\n when (decoded_addr(CSRs.dscratch0)) { reg_dscratch0 := wdata }\n reg_dscratch1.foreach { r =>\n when (decoded_addr(CSRs.dscratch1)) { r := wdata }\n }\n }\n if (usingSupervisor) {\n when (decoded_addr(CSRs.sstatus)) {\n val new_sstatus = wdata.asTypeOf(new MStatus())\n reg_mstatus.sie := new_sstatus.sie\n reg_mstatus.spie := new_sstatus.spie\n reg_mstatus.spp := new_sstatus.spp\n reg_mstatus.fs := formFS(new_sstatus.fs)\n reg_mstatus.vs := formVS(new_sstatus.vs)\n if (usingVM) {\n reg_mstatus.mxr := new_sstatus.mxr\n reg_mstatus.sum := new_sstatus.sum\n }\n }\n when (decoded_addr(CSRs.sip)) {\n val new_sip = ((read_mip & ~read_mideleg) | (wdata & read_mideleg)).asTypeOf(new MIP())\n reg_mip.ssip := new_sip.ssip\n }\n when (decoded_addr(CSRs.satp)) {\n if (usingVM) {\n val new_satp = wdata.asTypeOf(new PTBR())\n when (new_satp.mode.isOneOf(satp_valid_modes.map(_.U))) {\n reg_satp.mode := new_satp.mode & satp_valid_modes.reduce(_|_).U\n reg_satp.ppn := new_satp.ppn(ppnBits-1,0)\n if (asIdBits > 0) reg_satp.asid := new_satp.asid(asIdBits-1,0)\n }\n }\n }\n when (decoded_addr(CSRs.sie)) { reg_mie := (reg_mie & ~sie_mask) | (wdata & sie_mask) }\n when (decoded_addr(CSRs.sscratch)) { reg_sscratch := wdata }\n when (decoded_addr(CSRs.sepc)) { reg_sepc := formEPC(wdata) }\n when (decoded_addr(CSRs.stvec)) { reg_stvec := wdata }\n when (decoded_addr(CSRs.scause)) { reg_scause := wdata & scause_mask }\n when (decoded_addr(CSRs.stval)) { reg_stval := wdata }\n when (decoded_addr(CSRs.mideleg)) { reg_mideleg := wdata }\n when (decoded_addr(CSRs.medeleg)) { reg_medeleg := wdata }\n when (decoded_addr(CSRs.scounteren)) { reg_scounteren := wdata }\n when (decoded_addr(CSRs.senvcfg)) { reg_senvcfg.write(wdata) }\n }\n\n if (usingHypervisor) {\n when (decoded_addr(CSRs.hstatus)) {\n val new_hstatus = wdata.asTypeOf(new HStatus())\n reg_hstatus.gva := new_hstatus.gva\n reg_hstatus.spv := new_hstatus.spv\n reg_hstatus.spvp := new_hstatus.spvp\n reg_hstatus.hu := new_hstatus.hu\n reg_hstatus.vtvm := new_hstatus.vtvm\n reg_hstatus.vtw := new_hstatus.vtw\n reg_hstatus.vtsr := new_hstatus.vtsr\n reg_hstatus.vsxl := new_hstatus.vsxl\n }\n when (decoded_addr(CSRs.hideleg)) { reg_hideleg := wdata }\n when (decoded_addr(CSRs.hedeleg)) { reg_hedeleg := wdata }\n when (decoded_addr(CSRs.hgatp)) {\n val new_hgatp = wdata.asTypeOf(new PTBR())\n val valid_modes = 0 +: (minPgLevels to pgLevels).map(new_hgatp.pgLevelsToMode(_))\n when (new_hgatp.mode.isOneOf(valid_modes.map(_.U))) {\n reg_hgatp.mode := new_hgatp.mode & valid_modes.reduce(_|_).U\n }\n reg_hgatp.ppn := Cat(new_hgatp.ppn(ppnBits-1,2), 0.U(2.W))\n if (vmIdBits > 0) reg_hgatp.asid := new_hgatp.asid(vmIdBits-1,0)\n }\n when (decoded_addr(CSRs.hip)) {\n val new_hip = ((read_mip & ~hs_delegable_interrupts) | (wdata & hs_delegable_interrupts)).asTypeOf(new MIP())\n reg_mip.vssip := new_hip.vssip\n }\n when (decoded_addr(CSRs.hie)) { reg_mie := (reg_mie & ~hs_delegable_interrupts) | (wdata & hs_delegable_interrupts) }\n when (decoded_addr(CSRs.hvip)) {\n val new_sip = ((read_mip & ~hs_delegable_interrupts) | (wdata & hs_delegable_interrupts)).asTypeOf(new MIP())\n reg_mip.vssip := new_sip.vssip\n reg_mip.vstip := new_sip.vstip\n reg_mip.vseip := new_sip.vseip\n }\n when (decoded_addr(CSRs.hcounteren)) { reg_hcounteren := wdata }\n when (decoded_addr(CSRs.htval)) { reg_htval := wdata }\n when (decoded_addr(CSRs.mtval2)) { reg_mtval2 := wdata }\n\n val write_mhtinst_read_pseudo = wdata(13) && (xLen == 32).option(true.B).getOrElse(wdata(12))\n when(decoded_addr(CSRs.mtinst)) { reg_mtinst_read_pseudo := write_mhtinst_read_pseudo }\n when(decoded_addr(CSRs.htinst)) { reg_htinst_read_pseudo := write_mhtinst_read_pseudo }\n\n when (decoded_addr(CSRs.vsstatus)) {\n val new_vsstatus = wdata.asTypeOf(new MStatus())\n reg_vsstatus.sie := new_vsstatus.sie\n reg_vsstatus.spie := new_vsstatus.spie\n reg_vsstatus.spp := new_vsstatus.spp\n reg_vsstatus.mxr := new_vsstatus.mxr\n reg_vsstatus.sum := new_vsstatus.sum\n reg_vsstatus.fs := formFS(new_vsstatus.fs)\n reg_vsstatus.vs := formVS(new_vsstatus.vs)\n }\n when (decoded_addr(CSRs.vsip)) {\n val new_vsip = ((read_hip & ~read_hideleg) | ((wdata << 1) & read_hideleg)).asTypeOf(new MIP())\n reg_mip.vssip := new_vsip.vssip\n }\n when (decoded_addr(CSRs.vsatp)) {\n val new_vsatp = wdata.asTypeOf(new PTBR())\n val mode_ok = new_vsatp.mode.isOneOf(satp_valid_modes.map(_.U))\n when (mode_ok) {\n reg_vsatp.mode := new_vsatp.mode & satp_valid_modes.reduce(_|_).U\n }\n when (mode_ok || !reg_mstatus.v) {\n reg_vsatp.ppn := new_vsatp.ppn(vpnBits.min(new_vsatp.ppn.getWidth)-1,0)\n if (asIdBits > 0) reg_vsatp.asid := new_vsatp.asid(asIdBits-1,0)\n }\n }\n when (decoded_addr(CSRs.vsie)) { reg_mie := (reg_mie & ~read_hideleg) | ((wdata << 1) & read_hideleg) }\n when (decoded_addr(CSRs.vsscratch)) { reg_vsscratch := wdata }\n when (decoded_addr(CSRs.vsepc)) { reg_vsepc := formEPC(wdata) }\n when (decoded_addr(CSRs.vstvec)) { reg_vstvec := wdata }\n when (decoded_addr(CSRs.vscause)) { reg_vscause := wdata & scause_mask }\n when (decoded_addr(CSRs.vstval)) { reg_vstval := wdata }\n when (decoded_addr(CSRs.henvcfg)) { reg_henvcfg.write(wdata) }\n }\n if (usingUser) {\n when (decoded_addr(CSRs.mcounteren)) { reg_mcounteren := wdata }\n when (decoded_addr(CSRs.menvcfg)) { reg_menvcfg.write(wdata) }\n }\n if (nBreakpoints > 0) {\n when (decoded_addr(CSRs.tselect)) { reg_tselect := wdata }\n\n for ((bp, i) <- reg_bp.zipWithIndex) {\n when (i.U === reg_tselect && (!bp.control.dmode || reg_debug)) {\n when (decoded_addr(CSRs.tdata2)) { bp.address := wdata }\n when (decoded_addr(CSRs.tdata3)) {\n if (coreParams.mcontextWidth > 0) {\n bp.textra.mselect := wdata(bp.textra.mselectPos)\n bp.textra.mvalue := wdata >> bp.textra.mvaluePos\n }\n if (coreParams.scontextWidth > 0) {\n bp.textra.sselect := wdata(bp.textra.sselectPos)\n bp.textra.svalue := wdata >> bp.textra.svaluePos\n }\n }\n when (decoded_addr(CSRs.tdata1)) {\n bp.control := wdata.asTypeOf(bp.control)\n\n val prevChain = if (i == 0) false.B else reg_bp(i-1).control.chain\n val prevDMode = if (i == 0) false.B else reg_bp(i-1).control.dmode\n val nextChain = if (i >= nBreakpoints-1) true.B else reg_bp(i+1).control.chain\n val nextDMode = if (i >= nBreakpoints-1) true.B else reg_bp(i+1).control.dmode\n val newBPC = readModifyWriteCSR(io.rw.cmd, bp.control.asUInt, io.rw.wdata).asTypeOf(bp.control)\n val dMode = newBPC.dmode && reg_debug && (prevDMode || !prevChain)\n bp.control.dmode := dMode\n when (dMode || (newBPC.action > 1.U)) { bp.control.action := newBPC.action }.otherwise { bp.control.action := 0.U }\n bp.control.chain := newBPC.chain && !(prevChain || nextChain) && (dMode || !nextDMode)\n }\n }\n }\n }\n reg_mcontext.foreach { r => when (decoded_addr(CSRs.mcontext)) { r := wdata }}\n reg_scontext.foreach { r => when (decoded_addr(CSRs.scontext)) { r := wdata }}\n if (reg_pmp.nonEmpty) for (((pmp, next), i) <- (reg_pmp zip (reg_pmp.tail :+ reg_pmp.last)).zipWithIndex) {\n require(xLen % pmp.cfg.getWidth == 0)\n when (decoded_addr(CSRs.pmpcfg0 + pmpCfgIndex(i)) && !pmp.cfgLocked) {\n val newCfg = (wdata >> ((i * pmp.cfg.getWidth) % xLen)).asTypeOf(new PMPConfig())\n pmp.cfg := newCfg\n // disallow unreadable but writable PMPs\n pmp.cfg.w := newCfg.w && newCfg.r\n // can't select a=NA4 with coarse-grained PMPs\n if (pmpGranularity.log2 > PMP.lgAlign)\n pmp.cfg.a := Cat(newCfg.a(1), newCfg.a.orR)\n }\n when (decoded_addr(CSRs.pmpaddr0 + i) && !pmp.addrLocked(next)) {\n pmp.addr := wdata\n }\n }\n def writeCustomCSR(io: CustomCSRIO, csr: CustomCSR, reg: UInt) = {\n val mask = csr.mask.U(xLen.W)\n when (decoded_addr(csr.id)) {\n reg := (wdata & mask) | (reg & ~mask)\n io.wen := true.B\n }\n }\n for ((io, csr, reg) <- (io.customCSRs, customCSRs, reg_custom).zipped) {\n writeCustomCSR(io, csr, reg)\n }\n for ((io, csr, reg) <- (io.roccCSRs, roccCSRs, reg_rocc).zipped) {\n writeCustomCSR(io, csr, reg)\n }\n if (usingVector) {\n when (decoded_addr(CSRs.vstart)) { set_vs_dirty := true.B; reg_vstart.get := wdata }\n when (decoded_addr(CSRs.vxrm)) { set_vs_dirty := true.B; reg_vxrm.get := wdata }\n when (decoded_addr(CSRs.vxsat)) { set_vs_dirty := true.B; reg_vxsat.get := wdata }\n when (decoded_addr(CSRs.vcsr)) {\n set_vs_dirty := true.B\n reg_vxsat.get := wdata\n reg_vxrm.get := wdata >> 1\n }\n }\n }\n\n def setCustomCSR(io: CustomCSRIO, csr: CustomCSR, reg: UInt) = {\n val mask = csr.mask.U(xLen.W)\n when (io.set) {\n reg := (io.sdata & mask) | (reg & ~mask)\n }\n }\n for ((io, csr, reg) <- (io.customCSRs, customCSRs, reg_custom).zipped) {\n setCustomCSR(io, csr, reg)\n }\n for ((io, csr, reg) <- (io.roccCSRs, roccCSRs, reg_rocc).zipped) {\n setCustomCSR(io, csr, reg)\n }\n\n io.vector.map { vio =>\n when (vio.set_vconfig.valid) {\n // user of CSRFile is responsible for set_vs_dirty in this case\n assert(vio.set_vconfig.bits.vl <= vio.set_vconfig.bits.vtype.vlMax)\n reg_vconfig.get := vio.set_vconfig.bits\n }\n when (vio.set_vstart.valid) {\n set_vs_dirty := true.B\n reg_vstart.get := vio.set_vstart.bits\n }\n vio.vstart := reg_vstart.get\n vio.vconfig := reg_vconfig.get\n vio.vxrm := reg_vxrm.get\n\n when (reset.asBool) {\n reg_vconfig.get.vl := 0.U\n reg_vconfig.get.vtype := 0.U.asTypeOf(new VType)\n reg_vconfig.get.vtype.vill := true.B\n }\n }\n\n when(reset.asBool) {\n reg_satp.mode := 0.U\n reg_vsatp.mode := 0.U\n reg_hgatp.mode := 0.U\n }\n if (!usingVM) {\n reg_satp.mode := 0.U\n reg_satp.ppn := 0.U\n reg_satp.asid := 0.U\n }\n if (!usingHypervisor) {\n reg_vsatp.mode := 0.U\n reg_vsatp.ppn := 0.U\n reg_vsatp.asid := 0.U\n reg_hgatp.mode := 0.U\n reg_hgatp.ppn := 0.U\n reg_hgatp.asid := 0.U\n }\n if (!(asIdBits > 0)) {\n reg_satp.asid := 0.U\n reg_vsatp.asid := 0.U\n }\n if (!(vmIdBits > 0)) {\n reg_hgatp.asid := 0.U\n }\n reg_vsstatus.xs := (if (usingRoCC) 3.U else 0.U)\n\n if (nBreakpoints <= 1) reg_tselect := 0.U\n for (bpc <- reg_bp map {_.control}) {\n bpc.ttype := bpc.tType.U\n bpc.maskmax := bpc.maskMax.U\n bpc.reserved := 0.U\n bpc.zero := 0.U\n bpc.h := false.B\n if (!usingSupervisor) bpc.s := false.B\n if (!usingUser) bpc.u := false.B\n if (!usingSupervisor && !usingUser) bpc.m := true.B\n when (reset.asBool) {\n bpc.action := 0.U\n bpc.dmode := false.B\n bpc.chain := false.B\n bpc.r := false.B\n bpc.w := false.B\n bpc.x := false.B\n }\n }\n for (bpx <- reg_bp map {_.textra}) {\n if (coreParams.mcontextWidth == 0) bpx.mselect := false.B\n if (coreParams.scontextWidth == 0) bpx.sselect := false.B\n }\n for (bp <- reg_bp drop nBreakpoints)\n bp := 0.U.asTypeOf(new BP())\n for (pmp <- reg_pmp) {\n pmp.cfg.res := 0.U\n when (reset.asBool) { pmp.reset() }\n }\n\n for (((t, insn), i) <- (io.trace zip io.inst).zipWithIndex) {\n t.exception := io.retire >= i.U && exception\n t.valid := io.retire > i.U || t.exception\n t.insn := insn\n t.iaddr := io.pc\n t.priv := Cat(reg_debug, reg_mstatus.prv)\n t.cause := cause\n t.interrupt := cause(xLen-1)\n t.tval := io.tval\n t.wdata.foreach(_ := DontCare)\n }\n\n def chooseInterrupt(masksIn: Seq[UInt]): (Bool, UInt) = {\n val nonstandard = supported_interrupts.getWidth-1 to 12 by -1\n // MEI, MSI, MTI, SEI, SSI, STI, VSEI, VSSI, VSTI, UEI, USI, UTI\n val standard = Seq(11, 3, 7, 9, 1, 5, 10, 2, 6, 8, 0, 4)\n val priority = nonstandard ++ standard\n val masks = masksIn.reverse\n val any = masks.flatMap(m => priority.filter(_ < m.getWidth).map(i => m(i))).reduce(_||_)\n val which = PriorityMux(masks.flatMap(m => priority.filter(_ < m.getWidth).map(i => (m(i), i.U))))\n (any, which)\n }\n\n def readModifyWriteCSR(cmd: UInt, rdata: UInt, wdata: UInt) = {\n (Mux(cmd(1), rdata, 0.U) | wdata) & ~Mux(cmd(1,0).andR, wdata, 0.U)\n }\n\n def legalizePrivilege(priv: UInt): UInt =\n if (usingSupervisor) Mux(priv === PRV.H.U, PRV.U.U, priv)\n else if (usingUser) Fill(2, priv(0))\n else PRV.M.U\n\n def trimPrivilege(priv: UInt): UInt =\n if (usingSupervisor) priv\n else legalizePrivilege(priv)\n\n def writeCounter(lo: Int, ctr: WideCounter, wdata: UInt) = {\n if (xLen == 32) {\n val hi = lo + CSRs.mcycleh - CSRs.mcycle\n when (decoded_addr(lo)) { ctr := Cat(ctr(ctr.getWidth-1, 32), wdata) }\n when (decoded_addr(hi)) { ctr := Cat(wdata(ctr.getWidth-33, 0), ctr(31, 0)) }\n } else {\n when (decoded_addr(lo)) { ctr := wdata(ctr.getWidth-1, 0) }\n }\n }\n def formEPC(x: UInt) = ~(~x | (if (usingCompressed) 1.U else 3.U))\n def readEPC(x: UInt) = ~(~x | Mux(reg_misa('c' - 'a'), 1.U, 3.U))\n def formTVec(x: UInt) = x andNot Mux(x(0), ((((BigInt(1) << mtvecInterruptAlign) - 1) << mtvecBaseAlign) | 2).U, 2.U)\n def isaStringToMask(s: String) = s.map(x => 1 << (x - 'A')).foldLeft(0)(_|_)\n def formFS(fs: UInt) = if (coreParams.haveFSDirty) fs else Fill(2, fs.orR)\n def formVS(vs: UInt) = if (usingVector) vs else 0.U\n}\n"},"response":{"kind":"string","value":"module BoomCore(\t// @[core.scala:51:7]\n input clock,\t// @[core.scala:51:7]\n input reset,\t// @[core.scala:51:7]\n input io_hartid,\t// @[core.scala:54:14]\n input io_interrupts_debug,\t// @[core.scala:54:14]\n input io_interrupts_mtip,\t// @[core.scala:54:14]\n input io_interrupts_msip,\t// @[core.scala:54:14]\n input io_interrupts_meip,\t// @[core.scala:54:14]\n input io_interrupts_seip,\t// @[core.scala:54:14]\n output io_ifu_fetchpacket_ready,\t// @[core.scala:54:14]\n input io_ifu_fetchpacket_valid,\t// @[core.scala:54:14]\n input io_ifu_fetchpacket_bits_uops_0_valid,\t// @[core.scala:54:14]\n input [31:0] io_ifu_fetchpacket_bits_uops_0_bits_inst,\t// @[core.scala:54:14]\n input [31:0] io_ifu_fetchpacket_bits_uops_0_bits_debug_inst,\t// @[core.scala:54:14]\n input io_ifu_fetchpacket_bits_uops_0_bits_is_rvc,\t// @[core.scala:54:14]\n input [39:0] io_ifu_fetchpacket_bits_uops_0_bits_debug_pc,\t// @[core.scala:54:14]\n input io_ifu_fetchpacket_bits_uops_0_bits_is_sfb,\t// @[core.scala:54:14]\n input [4:0] io_ifu_fetchpacket_bits_uops_0_bits_ftq_idx,\t// @[core.scala:54:14]\n input io_ifu_fetchpacket_bits_uops_0_bits_edge_inst,\t// @[core.scala:54:14]\n input [5:0] io_ifu_fetchpacket_bits_uops_0_bits_pc_lob,\t// @[core.scala:54:14]\n input io_ifu_fetchpacket_bits_uops_0_bits_taken,\t// @[core.scala:54:14]\n input io_ifu_fetchpacket_bits_uops_0_bits_xcpt_pf_if,\t// @[core.scala:54:14]\n input io_ifu_fetchpacket_bits_uops_0_bits_xcpt_ae_if,\t// @[core.scala:54:14]\n input io_ifu_fetchpacket_bits_uops_0_bits_bp_debug_if,\t// @[core.scala:54:14]\n input io_ifu_fetchpacket_bits_uops_0_bits_bp_xcpt_if,\t// @[core.scala:54:14]\n input [1:0] io_ifu_fetchpacket_bits_uops_0_bits_debug_fsrc,\t// @[core.scala:54:14]\n input io_ifu_fetchpacket_bits_uops_1_valid,\t// @[core.scala:54:14]\n input [31:0] io_ifu_fetchpacket_bits_uops_1_bits_inst,\t// @[core.scala:54:14]\n input [31:0] io_ifu_fetchpacket_bits_uops_1_bits_debug_inst,\t// @[core.scala:54:14]\n input io_ifu_fetchpacket_bits_uops_1_bits_is_rvc,\t// @[core.scala:54:14]\n input [39:0] io_ifu_fetchpacket_bits_uops_1_bits_debug_pc,\t// @[core.scala:54:14]\n input io_ifu_fetchpacket_bits_uops_1_bits_is_sfb,\t// @[core.scala:54:14]\n input [4:0] io_ifu_fetchpacket_bits_uops_1_bits_ftq_idx,\t// @[core.scala:54:14]\n input io_ifu_fetchpacket_bits_uops_1_bits_edge_inst,\t// @[core.scala:54:14]\n input [5:0] io_ifu_fetchpacket_bits_uops_1_bits_pc_lob,\t// @[core.scala:54:14]\n input io_ifu_fetchpacket_bits_uops_1_bits_taken,\t// @[core.scala:54:14]\n input io_ifu_fetchpacket_bits_uops_1_bits_xcpt_pf_if,\t// @[core.scala:54:14]\n input io_ifu_fetchpacket_bits_uops_1_bits_xcpt_ae_if,\t// @[core.scala:54:14]\n input io_ifu_fetchpacket_bits_uops_1_bits_bp_debug_if,\t// @[core.scala:54:14]\n input io_ifu_fetchpacket_bits_uops_1_bits_bp_xcpt_if,\t// @[core.scala:54:14]\n input [1:0] io_ifu_fetchpacket_bits_uops_1_bits_debug_fsrc,\t// @[core.scala:54:14]\n input io_ifu_fetchpacket_bits_uops_2_valid,\t// @[core.scala:54:14]\n input [31:0] io_ifu_fetchpacket_bits_uops_2_bits_inst,\t// @[core.scala:54:14]\n input [31:0] io_ifu_fetchpacket_bits_uops_2_bits_debug_inst,\t// @[core.scala:54:14]\n input io_ifu_fetchpacket_bits_uops_2_bits_is_rvc,\t// @[core.scala:54:14]\n input [39:0] io_ifu_fetchpacket_bits_uops_2_bits_debug_pc,\t// @[core.scala:54:14]\n input io_ifu_fetchpacket_bits_uops_2_bits_is_sfb,\t// @[core.scala:54:14]\n input [4:0] io_ifu_fetchpacket_bits_uops_2_bits_ftq_idx,\t// @[core.scala:54:14]\n input io_ifu_fetchpacket_bits_uops_2_bits_edge_inst,\t// @[core.scala:54:14]\n input [5:0] io_ifu_fetchpacket_bits_uops_2_bits_pc_lob,\t// @[core.scala:54:14]\n input io_ifu_fetchpacket_bits_uops_2_bits_taken,\t// @[core.scala:54:14]\n input io_ifu_fetchpacket_bits_uops_2_bits_xcpt_pf_if,\t// @[core.scala:54:14]\n input io_ifu_fetchpacket_bits_uops_2_bits_xcpt_ae_if,\t// @[core.scala:54:14]\n input io_ifu_fetchpacket_bits_uops_2_bits_bp_debug_if,\t// @[core.scala:54:14]\n input io_ifu_fetchpacket_bits_uops_2_bits_bp_xcpt_if,\t// @[core.scala:54:14]\n input [1:0] io_ifu_fetchpacket_bits_uops_2_bits_debug_fsrc,\t// @[core.scala:54:14]\n output [4:0] io_ifu_get_pc_0_ftq_idx,\t// @[core.scala:54:14]\n input io_ifu_get_pc_0_entry_cfi_idx_valid,\t// @[core.scala:54:14]\n input [2:0] io_ifu_get_pc_0_entry_cfi_idx_bits,\t// @[core.scala:54:14]\n input io_ifu_get_pc_0_entry_cfi_taken,\t// @[core.scala:54:14]\n input io_ifu_get_pc_0_entry_cfi_mispredicted,\t// @[core.scala:54:14]\n input [2:0] io_ifu_get_pc_0_entry_cfi_type,\t// @[core.scala:54:14]\n input [7:0] io_ifu_get_pc_0_entry_br_mask,\t// @[core.scala:54:14]\n input io_ifu_get_pc_0_entry_cfi_is_call,\t// @[core.scala:54:14]\n input io_ifu_get_pc_0_entry_cfi_is_ret,\t// @[core.scala:54:14]\n input io_ifu_get_pc_0_entry_cfi_npc_plus4,\t// @[core.scala:54:14]\n input [39:0] io_ifu_get_pc_0_entry_ras_top,\t// @[core.scala:54:14]\n input [4:0] io_ifu_get_pc_0_entry_ras_idx,\t// @[core.scala:54:14]\n input io_ifu_get_pc_0_entry_start_bank,\t// @[core.scala:54:14]\n input [39:0] io_ifu_get_pc_0_pc,\t// @[core.scala:54:14]\n input [39:0] io_ifu_get_pc_0_com_pc,\t// @[core.scala:54:14]\n input io_ifu_get_pc_0_next_val,\t// @[core.scala:54:14]\n input [39:0] io_ifu_get_pc_0_next_pc,\t// @[core.scala:54:14]\n output [4:0] io_ifu_get_pc_1_ftq_idx,\t// @[core.scala:54:14]\n input io_ifu_get_pc_1_entry_cfi_idx_valid,\t// @[core.scala:54:14]\n input [2:0] io_ifu_get_pc_1_entry_cfi_idx_bits,\t// @[core.scala:54:14]\n input io_ifu_get_pc_1_entry_cfi_taken,\t// @[core.scala:54:14]\n input io_ifu_get_pc_1_entry_cfi_mispredicted,\t// @[core.scala:54:14]\n input [2:0] io_ifu_get_pc_1_entry_cfi_type,\t// @[core.scala:54:14]\n input [7:0] io_ifu_get_pc_1_entry_br_mask,\t// @[core.scala:54:14]\n input io_ifu_get_pc_1_entry_cfi_is_call,\t// @[core.scala:54:14]\n input io_ifu_get_pc_1_entry_cfi_is_ret,\t// @[core.scala:54:14]\n input io_ifu_get_pc_1_entry_cfi_npc_plus4,\t// @[core.scala:54:14]\n input [39:0] io_ifu_get_pc_1_entry_ras_top,\t// @[core.scala:54:14]\n input [4:0] io_ifu_get_pc_1_entry_ras_idx,\t// @[core.scala:54:14]\n input io_ifu_get_pc_1_entry_start_bank,\t// @[core.scala:54:14]\n input [63:0] io_ifu_get_pc_1_ghist_old_history,\t// @[core.scala:54:14]\n input io_ifu_get_pc_1_ghist_current_saw_branch_not_taken,\t// @[core.scala:54:14]\n input io_ifu_get_pc_1_ghist_new_saw_branch_not_taken,\t// @[core.scala:54:14]\n input io_ifu_get_pc_1_ghist_new_saw_branch_taken,\t// @[core.scala:54:14]\n input [4:0] io_ifu_get_pc_1_ghist_ras_idx,\t// @[core.scala:54:14]\n input [39:0] io_ifu_get_pc_1_pc,\t// @[core.scala:54:14]\n input [39:0] io_ifu_get_pc_1_com_pc,\t// @[core.scala:54:14]\n input io_ifu_get_pc_1_next_val,\t// @[core.scala:54:14]\n input [39:0] io_ifu_get_pc_1_next_pc,\t// @[core.scala:54:14]\n input [39:0] io_ifu_debug_fetch_pc_0,\t// @[core.scala:54:14]\n input [39:0] io_ifu_debug_fetch_pc_1,\t// @[core.scala:54:14]\n input [39:0] io_ifu_debug_fetch_pc_2,\t// @[core.scala:54:14]\n output io_ifu_status_debug,\t// @[core.scala:54:14]\n output io_ifu_status_cease,\t// @[core.scala:54:14]\n output io_ifu_status_wfi,\t// @[core.scala:54:14]\n output [1:0] io_ifu_status_dprv,\t// @[core.scala:54:14]\n output io_ifu_status_dv,\t// @[core.scala:54:14]\n output [1:0] io_ifu_status_prv,\t// @[core.scala:54:14]\n output io_ifu_status_v,\t// @[core.scala:54:14]\n output io_ifu_status_sd,\t// @[core.scala:54:14]\n output io_ifu_status_mpv,\t// @[core.scala:54:14]\n output io_ifu_status_gva,\t// @[core.scala:54:14]\n output io_ifu_status_tsr,\t// @[core.scala:54:14]\n output io_ifu_status_tw,\t// @[core.scala:54:14]\n output io_ifu_status_tvm,\t// @[core.scala:54:14]\n output io_ifu_status_mxr,\t// @[core.scala:54:14]\n output io_ifu_status_sum,\t// @[core.scala:54:14]\n output io_ifu_status_mprv,\t// @[core.scala:54:14]\n output [1:0] io_ifu_status_fs,\t// @[core.scala:54:14]\n output [1:0] io_ifu_status_mpp,\t// @[core.scala:54:14]\n output io_ifu_status_spp,\t// @[core.scala:54:14]\n output io_ifu_status_mpie,\t// @[core.scala:54:14]\n output io_ifu_status_spie,\t// @[core.scala:54:14]\n output io_ifu_status_mie,\t// @[core.scala:54:14]\n output io_ifu_status_sie,\t// @[core.scala:54:14]\n output io_ifu_sfence_valid,\t// @[core.scala:54:14]\n output io_ifu_sfence_bits_rs1,\t// @[core.scala:54:14]\n output io_ifu_sfence_bits_rs2,\t// @[core.scala:54:14]\n output [38:0] io_ifu_sfence_bits_addr,\t// @[core.scala:54:14]\n output io_ifu_sfence_bits_asid,\t// @[core.scala:54:14]\n output [15:0] io_ifu_brupdate_b1_resolve_mask,\t// @[core.scala:54:14]\n output [15:0] io_ifu_brupdate_b1_mispredict_mask,\t// @[core.scala:54:14]\n output [6:0] io_ifu_brupdate_b2_uop_uopc,\t// @[core.scala:54:14]\n output [31:0] io_ifu_brupdate_b2_uop_inst,\t// @[core.scala:54:14]\n output [31:0] io_ifu_brupdate_b2_uop_debug_inst,\t// @[core.scala:54:14]\n output io_ifu_brupdate_b2_uop_is_rvc,\t// @[core.scala:54:14]\n output [39:0] io_ifu_brupdate_b2_uop_debug_pc,\t// @[core.scala:54:14]\n output [2:0] io_ifu_brupdate_b2_uop_iq_type,\t// @[core.scala:54:14]\n output [9:0] io_ifu_brupdate_b2_uop_fu_code,\t// @[core.scala:54:14]\n output [3:0] io_ifu_brupdate_b2_uop_ctrl_br_type,\t// @[core.scala:54:14]\n output [1:0] io_ifu_brupdate_b2_uop_ctrl_op1_sel,\t// @[core.scala:54:14]\n output [2:0] io_ifu_brupdate_b2_uop_ctrl_op2_sel,\t// @[core.scala:54:14]\n output [2:0] io_ifu_brupdate_b2_uop_ctrl_imm_sel,\t// @[core.scala:54:14]\n output [4:0] io_ifu_brupdate_b2_uop_ctrl_op_fcn,\t// @[core.scala:54:14]\n output io_ifu_brupdate_b2_uop_ctrl_fcn_dw,\t// @[core.scala:54:14]\n output [2:0] io_ifu_brupdate_b2_uop_ctrl_csr_cmd,\t// @[core.scala:54:14]\n output io_ifu_brupdate_b2_uop_ctrl_is_load,\t// @[core.scala:54:14]\n output io_ifu_brupdate_b2_uop_ctrl_is_sta,\t// @[core.scala:54:14]\n output io_ifu_brupdate_b2_uop_ctrl_is_std,\t// @[core.scala:54:14]\n output [1:0] io_ifu_brupdate_b2_uop_iw_state,\t// @[core.scala:54:14]\n output io_ifu_brupdate_b2_uop_iw_p1_poisoned,\t// @[core.scala:54:14]\n output io_ifu_brupdate_b2_uop_iw_p2_poisoned,\t// @[core.scala:54:14]\n output io_ifu_brupdate_b2_uop_is_br,\t// @[core.scala:54:14]\n output io_ifu_brupdate_b2_uop_is_jalr,\t// @[core.scala:54:14]\n output io_ifu_brupdate_b2_uop_is_jal,\t// @[core.scala:54:14]\n output io_ifu_brupdate_b2_uop_is_sfb,\t// @[core.scala:54:14]\n output [15:0] io_ifu_brupdate_b2_uop_br_mask,\t// @[core.scala:54:14]\n output [3:0] io_ifu_brupdate_b2_uop_br_tag,\t// @[core.scala:54:14]\n output [4:0] io_ifu_brupdate_b2_uop_ftq_idx,\t// @[core.scala:54:14]\n output io_ifu_brupdate_b2_uop_edge_inst,\t// @[core.scala:54:14]\n output [5:0] io_ifu_brupdate_b2_uop_pc_lob,\t// @[core.scala:54:14]\n output io_ifu_brupdate_b2_uop_taken,\t// @[core.scala:54:14]\n output [19:0] io_ifu_brupdate_b2_uop_imm_packed,\t// @[core.scala:54:14]\n output [11:0] io_ifu_brupdate_b2_uop_csr_addr,\t// @[core.scala:54:14]\n output [6:0] io_ifu_brupdate_b2_uop_rob_idx,\t// @[core.scala:54:14]\n output [4:0] io_ifu_brupdate_b2_uop_ldq_idx,\t// @[core.scala:54:14]\n output [4:0] io_ifu_brupdate_b2_uop_stq_idx,\t// @[core.scala:54:14]\n output [1:0] io_ifu_brupdate_b2_uop_rxq_idx,\t// @[core.scala:54:14]\n output [6:0] io_ifu_brupdate_b2_uop_pdst,\t// @[core.scala:54:14]\n output [6:0] io_ifu_brupdate_b2_uop_prs1,\t// @[core.scala:54:14]\n output [6:0] io_ifu_brupdate_b2_uop_prs2,\t// @[core.scala:54:14]\n output [6:0] io_ifu_brupdate_b2_uop_prs3,\t// @[core.scala:54:14]\n output [4:0] io_ifu_brupdate_b2_uop_ppred,\t// @[core.scala:54:14]\n output io_ifu_brupdate_b2_uop_prs1_busy,\t// @[core.scala:54:14]\n output io_ifu_brupdate_b2_uop_prs2_busy,\t// @[core.scala:54:14]\n output io_ifu_brupdate_b2_uop_prs3_busy,\t// @[core.scala:54:14]\n output io_ifu_brupdate_b2_uop_ppred_busy,\t// @[core.scala:54:14]\n output [6:0] io_ifu_brupdate_b2_uop_stale_pdst,\t// @[core.scala:54:14]\n output io_ifu_brupdate_b2_uop_exception,\t// @[core.scala:54:14]\n output [63:0] io_ifu_brupdate_b2_uop_exc_cause,\t// @[core.scala:54:14]\n output io_ifu_brupdate_b2_uop_bypassable,\t// @[core.scala:54:14]\n output [4:0] io_ifu_brupdate_b2_uop_mem_cmd,\t// @[core.scala:54:14]\n output [1:0] io_ifu_brupdate_b2_uop_mem_size,\t// @[core.scala:54:14]\n output io_ifu_brupdate_b2_uop_mem_signed,\t// @[core.scala:54:14]\n output io_ifu_brupdate_b2_uop_is_fence,\t// @[core.scala:54:14]\n output io_ifu_brupdate_b2_uop_is_fencei,\t// @[core.scala:54:14]\n output io_ifu_brupdate_b2_uop_is_amo,\t// @[core.scala:54:14]\n output io_ifu_brupdate_b2_uop_uses_ldq,\t// @[core.scala:54:14]\n output io_ifu_brupdate_b2_uop_uses_stq,\t// @[core.scala:54:14]\n output io_ifu_brupdate_b2_uop_is_sys_pc2epc,\t// @[core.scala:54:14]\n output io_ifu_brupdate_b2_uop_is_unique,\t// @[core.scala:54:14]\n output io_ifu_brupdate_b2_uop_flush_on_commit,\t// @[core.scala:54:14]\n output io_ifu_brupdate_b2_uop_ldst_is_rs1,\t// @[core.scala:54:14]\n output [5:0] io_ifu_brupdate_b2_uop_ldst,\t// @[core.scala:54:14]\n output [5:0] io_ifu_brupdate_b2_uop_lrs1,\t// @[core.scala:54:14]\n output [5:0] io_ifu_brupdate_b2_uop_lrs2,\t// @[core.scala:54:14]\n output [5:0] io_ifu_brupdate_b2_uop_lrs3,\t// @[core.scala:54:14]\n output io_ifu_brupdate_b2_uop_ldst_val,\t// @[core.scala:54:14]\n output [1:0] io_ifu_brupdate_b2_uop_dst_rtype,\t// @[core.scala:54:14]\n output [1:0] io_ifu_brupdate_b2_uop_lrs1_rtype,\t// @[core.scala:54:14]\n output [1:0] io_ifu_brupdate_b2_uop_lrs2_rtype,\t// @[core.scala:54:14]\n output io_ifu_brupdate_b2_uop_frs3_en,\t// @[core.scala:54:14]\n output io_ifu_brupdate_b2_uop_fp_val,\t// @[core.scala:54:14]\n output io_ifu_brupdate_b2_uop_fp_single,\t// @[core.scala:54:14]\n output io_ifu_brupdate_b2_uop_xcpt_pf_if,\t// @[core.scala:54:14]\n output io_ifu_brupdate_b2_uop_xcpt_ae_if,\t// @[core.scala:54:14]\n output io_ifu_brupdate_b2_uop_xcpt_ma_if,\t// @[core.scala:54:14]\n output io_ifu_brupdate_b2_uop_bp_debug_if,\t// @[core.scala:54:14]\n output io_ifu_brupdate_b2_uop_bp_xcpt_if,\t// @[core.scala:54:14]\n output [1:0] io_ifu_brupdate_b2_uop_debug_fsrc,\t// @[core.scala:54:14]\n output [1:0] io_ifu_brupdate_b2_uop_debug_tsrc,\t// @[core.scala:54:14]\n output io_ifu_brupdate_b2_valid,\t// @[core.scala:54:14]\n output io_ifu_brupdate_b2_mispredict,\t// @[core.scala:54:14]\n output io_ifu_brupdate_b2_taken,\t// @[core.scala:54:14]\n output [2:0] io_ifu_brupdate_b2_cfi_type,\t// @[core.scala:54:14]\n output [1:0] io_ifu_brupdate_b2_pc_sel,\t// @[core.scala:54:14]\n output [39:0] io_ifu_brupdate_b2_jalr_target,\t// @[core.scala:54:14]\n output [20:0] io_ifu_brupdate_b2_target_offset,\t// @[core.scala:54:14]\n output io_ifu_redirect_flush,\t// @[core.scala:54:14]\n output io_ifu_redirect_val,\t// @[core.scala:54:14]\n output [39:0] io_ifu_redirect_pc,\t// @[core.scala:54:14]\n output [4:0] io_ifu_redirect_ftq_idx,\t// @[core.scala:54:14]\n output [63:0] io_ifu_redirect_ghist_old_history,\t// @[core.scala:54:14]\n output io_ifu_redirect_ghist_current_saw_branch_not_taken,\t// @[core.scala:54:14]\n output io_ifu_redirect_ghist_new_saw_branch_not_taken,\t// @[core.scala:54:14]\n output io_ifu_redirect_ghist_new_saw_branch_taken,\t// @[core.scala:54:14]\n output [4:0] io_ifu_redirect_ghist_ras_idx,\t// @[core.scala:54:14]\n output io_ifu_commit_valid,\t// @[core.scala:54:14]\n output [31:0] io_ifu_commit_bits,\t// @[core.scala:54:14]\n output io_ifu_flush_icache,\t// @[core.scala:54:14]\n input io_ifu_perf_acquire,\t// @[core.scala:54:14]\n input io_ifu_perf_tlbMiss,\t// @[core.scala:54:14]\n output [3:0] io_ptw_ptbr_mode,\t// @[core.scala:54:14]\n output [43:0] io_ptw_ptbr_ppn,\t// @[core.scala:54:14]\n output io_ptw_sfence_valid,\t// @[core.scala:54:14]\n output io_ptw_sfence_bits_rs1,\t// @[core.scala:54:14]\n output io_ptw_sfence_bits_rs2,\t// @[core.scala:54:14]\n output [38:0] io_ptw_sfence_bits_addr,\t// @[core.scala:54:14]\n output io_ptw_sfence_bits_asid,\t// @[core.scala:54:14]\n output io_ptw_status_debug,\t// @[core.scala:54:14]\n output io_ptw_status_cease,\t// @[core.scala:54:14]\n output io_ptw_status_wfi,\t// @[core.scala:54:14]\n output [1:0] io_ptw_status_dprv,\t// @[core.scala:54:14]\n output io_ptw_status_dv,\t// @[core.scala:54:14]\n output [1:0] io_ptw_status_prv,\t// @[core.scala:54:14]\n output io_ptw_status_v,\t// @[core.scala:54:14]\n output io_ptw_status_sd,\t// @[core.scala:54:14]\n output io_ptw_status_mpv,\t// @[core.scala:54:14]\n output io_ptw_status_gva,\t// @[core.scala:54:14]\n output io_ptw_status_tsr,\t// @[core.scala:54:14]\n output io_ptw_status_tw,\t// @[core.scala:54:14]\n output io_ptw_status_tvm,\t// @[core.scala:54:14]\n output io_ptw_status_mxr,\t// @[core.scala:54:14]\n output io_ptw_status_sum,\t// @[core.scala:54:14]\n output io_ptw_status_mprv,\t// @[core.scala:54:14]\n output [1:0] io_ptw_status_fs,\t// @[core.scala:54:14]\n output [1:0] io_ptw_status_mpp,\t// @[core.scala:54:14]\n output io_ptw_status_spp,\t// @[core.scala:54:14]\n output io_ptw_status_mpie,\t// @[core.scala:54:14]\n output io_ptw_status_spie,\t// @[core.scala:54:14]\n output io_ptw_status_mie,\t// @[core.scala:54:14]\n output io_ptw_status_sie,\t// @[core.scala:54:14]\n output io_ptw_pmp_0_cfg_l,\t// @[core.scala:54:14]\n output [1:0] io_ptw_pmp_0_cfg_a,\t// @[core.scala:54:14]\n output io_ptw_pmp_0_cfg_x,\t// @[core.scala:54:14]\n output io_ptw_pmp_0_cfg_w,\t// @[core.scala:54:14]\n output io_ptw_pmp_0_cfg_r,\t// @[core.scala:54:14]\n output [29:0] io_ptw_pmp_0_addr,\t// @[core.scala:54:14]\n output [31:0] io_ptw_pmp_0_mask,\t// @[core.scala:54:14]\n output io_ptw_pmp_1_cfg_l,\t// @[core.scala:54:14]\n output [1:0] io_ptw_pmp_1_cfg_a,\t// @[core.scala:54:14]\n output io_ptw_pmp_1_cfg_x,\t// @[core.scala:54:14]\n output io_ptw_pmp_1_cfg_w,\t// @[core.scala:54:14]\n output io_ptw_pmp_1_cfg_r,\t// @[core.scala:54:14]\n output [29:0] io_ptw_pmp_1_addr,\t// @[core.scala:54:14]\n output [31:0] io_ptw_pmp_1_mask,\t// @[core.scala:54:14]\n output io_ptw_pmp_2_cfg_l,\t// @[core.scala:54:14]\n output [1:0] io_ptw_pmp_2_cfg_a,\t// @[core.scala:54:14]\n output io_ptw_pmp_2_cfg_x,\t// @[core.scala:54:14]\n output io_ptw_pmp_2_cfg_w,\t// @[core.scala:54:14]\n output io_ptw_pmp_2_cfg_r,\t// @[core.scala:54:14]\n output [29:0] io_ptw_pmp_2_addr,\t// @[core.scala:54:14]\n output [31:0] io_ptw_pmp_2_mask,\t// @[core.scala:54:14]\n output io_ptw_pmp_3_cfg_l,\t// @[core.scala:54:14]\n output [1:0] io_ptw_pmp_3_cfg_a,\t// @[core.scala:54:14]\n output io_ptw_pmp_3_cfg_x,\t// @[core.scala:54:14]\n output io_ptw_pmp_3_cfg_w,\t// @[core.scala:54:14]\n output io_ptw_pmp_3_cfg_r,\t// @[core.scala:54:14]\n output [29:0] io_ptw_pmp_3_addr,\t// @[core.scala:54:14]\n output [31:0] io_ptw_pmp_3_mask,\t// @[core.scala:54:14]\n output io_ptw_pmp_4_cfg_l,\t// @[core.scala:54:14]\n output [1:0] io_ptw_pmp_4_cfg_a,\t// @[core.scala:54:14]\n output io_ptw_pmp_4_cfg_x,\t// @[core.scala:54:14]\n output io_ptw_pmp_4_cfg_w,\t// @[core.scala:54:14]\n output io_ptw_pmp_4_cfg_r,\t// @[core.scala:54:14]\n output [29:0] io_ptw_pmp_4_addr,\t// @[core.scala:54:14]\n output [31:0] io_ptw_pmp_4_mask,\t// @[core.scala:54:14]\n output io_ptw_pmp_5_cfg_l,\t// @[core.scala:54:14]\n output [1:0] io_ptw_pmp_5_cfg_a,\t// @[core.scala:54:14]\n output io_ptw_pmp_5_cfg_x,\t// @[core.scala:54:14]\n output io_ptw_pmp_5_cfg_w,\t// @[core.scala:54:14]\n output io_ptw_pmp_5_cfg_r,\t// @[core.scala:54:14]\n output [29:0] io_ptw_pmp_5_addr,\t// @[core.scala:54:14]\n output [31:0] io_ptw_pmp_5_mask,\t// @[core.scala:54:14]\n output io_ptw_pmp_6_cfg_l,\t// @[core.scala:54:14]\n output [1:0] io_ptw_pmp_6_cfg_a,\t// @[core.scala:54:14]\n output io_ptw_pmp_6_cfg_x,\t// @[core.scala:54:14]\n output io_ptw_pmp_6_cfg_w,\t// @[core.scala:54:14]\n output io_ptw_pmp_6_cfg_r,\t// @[core.scala:54:14]\n output [29:0] io_ptw_pmp_6_addr,\t// @[core.scala:54:14]\n output [31:0] io_ptw_pmp_6_mask,\t// @[core.scala:54:14]\n output io_ptw_pmp_7_cfg_l,\t// @[core.scala:54:14]\n output [1:0] io_ptw_pmp_7_cfg_a,\t// @[core.scala:54:14]\n output io_ptw_pmp_7_cfg_x,\t// @[core.scala:54:14]\n output io_ptw_pmp_7_cfg_w,\t// @[core.scala:54:14]\n output io_ptw_pmp_7_cfg_r,\t// @[core.scala:54:14]\n output [29:0] io_ptw_pmp_7_addr,\t// @[core.scala:54:14]\n output [31:0] io_ptw_pmp_7_mask,\t// @[core.scala:54:14]\n input io_ptw_perf_l2miss,\t// @[core.scala:54:14]\n input io_ptw_perf_l2hit,\t// @[core.scala:54:14]\n input io_ptw_perf_pte_miss,\t// @[core.scala:54:14]\n input io_ptw_perf_pte_hit,\t// @[core.scala:54:14]\n input io_ptw_clock_enabled,\t// @[core.scala:54:14]\n output io_lsu_exe_0_req_valid,\t// @[core.scala:54:14]\n output [6:0] io_lsu_exe_0_req_bits_uop_uopc,\t// @[core.scala:54:14]\n output [31:0] io_lsu_exe_0_req_bits_uop_inst,\t// @[core.scala:54:14]\n output [31:0] io_lsu_exe_0_req_bits_uop_debug_inst,\t// @[core.scala:54:14]\n output io_lsu_exe_0_req_bits_uop_is_rvc,\t// @[core.scala:54:14]\n output [39:0] io_lsu_exe_0_req_bits_uop_debug_pc,\t// @[core.scala:54:14]\n output [2:0] io_lsu_exe_0_req_bits_uop_iq_type,\t// @[core.scala:54:14]\n output [9:0] io_lsu_exe_0_req_bits_uop_fu_code,\t// @[core.scala:54:14]\n output [3:0] io_lsu_exe_0_req_bits_uop_ctrl_br_type,\t// @[core.scala:54:14]\n output [1:0] io_lsu_exe_0_req_bits_uop_ctrl_op1_sel,\t// @[core.scala:54:14]\n output [2:0] io_lsu_exe_0_req_bits_uop_ctrl_op2_sel,\t// @[core.scala:54:14]\n output [2:0] io_lsu_exe_0_req_bits_uop_ctrl_imm_sel,\t// @[core.scala:54:14]\n output [4:0] io_lsu_exe_0_req_bits_uop_ctrl_op_fcn,\t// @[core.scala:54:14]\n output io_lsu_exe_0_req_bits_uop_ctrl_fcn_dw,\t// @[core.scala:54:14]\n output [2:0] io_lsu_exe_0_req_bits_uop_ctrl_csr_cmd,\t// @[core.scala:54:14]\n output io_lsu_exe_0_req_bits_uop_ctrl_is_load,\t// @[core.scala:54:14]\n output io_lsu_exe_0_req_bits_uop_ctrl_is_sta,\t// @[core.scala:54:14]\n output io_lsu_exe_0_req_bits_uop_ctrl_is_std,\t// @[core.scala:54:14]\n output [1:0] io_lsu_exe_0_req_bits_uop_iw_state,\t// @[core.scala:54:14]\n output io_lsu_exe_0_req_bits_uop_iw_p1_poisoned,\t// @[core.scala:54:14]\n output io_lsu_exe_0_req_bits_uop_iw_p2_poisoned,\t// @[core.scala:54:14]\n output io_lsu_exe_0_req_bits_uop_is_br,\t// @[core.scala:54:14]\n output io_lsu_exe_0_req_bits_uop_is_jalr,\t// @[core.scala:54:14]\n output io_lsu_exe_0_req_bits_uop_is_jal,\t// @[core.scala:54:14]\n output io_lsu_exe_0_req_bits_uop_is_sfb,\t// @[core.scala:54:14]\n output [15:0] io_lsu_exe_0_req_bits_uop_br_mask,\t// @[core.scala:54:14]\n output [3:0] io_lsu_exe_0_req_bits_uop_br_tag,\t// @[core.scala:54:14]\n output [4:0] io_lsu_exe_0_req_bits_uop_ftq_idx,\t// @[core.scala:54:14]\n output io_lsu_exe_0_req_bits_uop_edge_inst,\t// @[core.scala:54:14]\n output [5:0] io_lsu_exe_0_req_bits_uop_pc_lob,\t// @[core.scala:54:14]\n output io_lsu_exe_0_req_bits_uop_taken,\t// @[core.scala:54:14]\n output [19:0] io_lsu_exe_0_req_bits_uop_imm_packed,\t// @[core.scala:54:14]\n output [11:0] io_lsu_exe_0_req_bits_uop_csr_addr,\t// @[core.scala:54:14]\n output [6:0] io_lsu_exe_0_req_bits_uop_rob_idx,\t// @[core.scala:54:14]\n output [4:0] io_lsu_exe_0_req_bits_uop_ldq_idx,\t// @[core.scala:54:14]\n output [4:0] io_lsu_exe_0_req_bits_uop_stq_idx,\t// @[core.scala:54:14]\n output [1:0] io_lsu_exe_0_req_bits_uop_rxq_idx,\t// @[core.scala:54:14]\n output [6:0] io_lsu_exe_0_req_bits_uop_pdst,\t// @[core.scala:54:14]\n output [6:0] io_lsu_exe_0_req_bits_uop_prs1,\t// @[core.scala:54:14]\n output [6:0] io_lsu_exe_0_req_bits_uop_prs2,\t// @[core.scala:54:14]\n output [6:0] io_lsu_exe_0_req_bits_uop_prs3,\t// @[core.scala:54:14]\n output [4:0] io_lsu_exe_0_req_bits_uop_ppred,\t// @[core.scala:54:14]\n output io_lsu_exe_0_req_bits_uop_prs1_busy,\t// @[core.scala:54:14]\n output io_lsu_exe_0_req_bits_uop_prs2_busy,\t// @[core.scala:54:14]\n output io_lsu_exe_0_req_bits_uop_prs3_busy,\t// @[core.scala:54:14]\n output io_lsu_exe_0_req_bits_uop_ppred_busy,\t// @[core.scala:54:14]\n output [6:0] io_lsu_exe_0_req_bits_uop_stale_pdst,\t// @[core.scala:54:14]\n output io_lsu_exe_0_req_bits_uop_exception,\t// @[core.scala:54:14]\n output [63:0] io_lsu_exe_0_req_bits_uop_exc_cause,\t// @[core.scala:54:14]\n output io_lsu_exe_0_req_bits_uop_bypassable,\t// @[core.scala:54:14]\n output [4:0] io_lsu_exe_0_req_bits_uop_mem_cmd,\t// @[core.scala:54:14]\n output [1:0] io_lsu_exe_0_req_bits_uop_mem_size,\t// @[core.scala:54:14]\n output io_lsu_exe_0_req_bits_uop_mem_signed,\t// @[core.scala:54:14]\n output io_lsu_exe_0_req_bits_uop_is_fence,\t// @[core.scala:54:14]\n output io_lsu_exe_0_req_bits_uop_is_fencei,\t// @[core.scala:54:14]\n output io_lsu_exe_0_req_bits_uop_is_amo,\t// @[core.scala:54:14]\n output io_lsu_exe_0_req_bits_uop_uses_ldq,\t// @[core.scala:54:14]\n output io_lsu_exe_0_req_bits_uop_uses_stq,\t// @[core.scala:54:14]\n output io_lsu_exe_0_req_bits_uop_is_sys_pc2epc,\t// @[core.scala:54:14]\n output io_lsu_exe_0_req_bits_uop_is_unique,\t// @[core.scala:54:14]\n output io_lsu_exe_0_req_bits_uop_flush_on_commit,\t// @[core.scala:54:14]\n output io_lsu_exe_0_req_bits_uop_ldst_is_rs1,\t// @[core.scala:54:14]\n output [5:0] io_lsu_exe_0_req_bits_uop_ldst,\t// @[core.scala:54:14]\n output [5:0] io_lsu_exe_0_req_bits_uop_lrs1,\t// @[core.scala:54:14]\n output [5:0] io_lsu_exe_0_req_bits_uop_lrs2,\t// @[core.scala:54:14]\n output [5:0] io_lsu_exe_0_req_bits_uop_lrs3,\t// @[core.scala:54:14]\n output io_lsu_exe_0_req_bits_uop_ldst_val,\t// @[core.scala:54:14]\n output [1:0] io_lsu_exe_0_req_bits_uop_dst_rtype,\t// @[core.scala:54:14]\n output [1:0] io_lsu_exe_0_req_bits_uop_lrs1_rtype,\t// @[core.scala:54:14]\n output [1:0] io_lsu_exe_0_req_bits_uop_lrs2_rtype,\t// @[core.scala:54:14]\n output io_lsu_exe_0_req_bits_uop_frs3_en,\t// @[core.scala:54:14]\n output io_lsu_exe_0_req_bits_uop_fp_val,\t// @[core.scala:54:14]\n output io_lsu_exe_0_req_bits_uop_fp_single,\t// @[core.scala:54:14]\n output io_lsu_exe_0_req_bits_uop_xcpt_pf_if,\t// @[core.scala:54:14]\n output io_lsu_exe_0_req_bits_uop_xcpt_ae_if,\t// @[core.scala:54:14]\n output io_lsu_exe_0_req_bits_uop_xcpt_ma_if,\t// @[core.scala:54:14]\n output io_lsu_exe_0_req_bits_uop_bp_debug_if,\t// @[core.scala:54:14]\n output io_lsu_exe_0_req_bits_uop_bp_xcpt_if,\t// @[core.scala:54:14]\n output [1:0] io_lsu_exe_0_req_bits_uop_debug_fsrc,\t// @[core.scala:54:14]\n output [1:0] io_lsu_exe_0_req_bits_uop_debug_tsrc,\t// @[core.scala:54:14]\n output [63:0] io_lsu_exe_0_req_bits_data,\t// @[core.scala:54:14]\n output [39:0] io_lsu_exe_0_req_bits_addr,\t// @[core.scala:54:14]\n output io_lsu_exe_0_req_bits_mxcpt_valid,\t// @[core.scala:54:14]\n output [24:0] io_lsu_exe_0_req_bits_mxcpt_bits,\t// @[core.scala:54:14]\n output io_lsu_exe_0_req_bits_sfence_valid,\t// @[core.scala:54:14]\n output io_lsu_exe_0_req_bits_sfence_bits_rs1,\t// @[core.scala:54:14]\n output io_lsu_exe_0_req_bits_sfence_bits_rs2,\t// @[core.scala:54:14]\n output [38:0] io_lsu_exe_0_req_bits_sfence_bits_addr,\t// @[core.scala:54:14]\n output io_lsu_exe_0_req_bits_sfence_bits_asid,\t// @[core.scala:54:14]\n input io_lsu_exe_0_iresp_valid,\t// @[core.scala:54:14]\n input [6:0] io_lsu_exe_0_iresp_bits_uop_uopc,\t// @[core.scala:54:14]\n input [31:0] io_lsu_exe_0_iresp_bits_uop_inst,\t// @[core.scala:54:14]\n input [31:0] io_lsu_exe_0_iresp_bits_uop_debug_inst,\t// @[core.scala:54:14]\n input io_lsu_exe_0_iresp_bits_uop_is_rvc,\t// @[core.scala:54:14]\n input [39:0] io_lsu_exe_0_iresp_bits_uop_debug_pc,\t// @[core.scala:54:14]\n input [2:0] io_lsu_exe_0_iresp_bits_uop_iq_type,\t// @[core.scala:54:14]\n input [9:0] io_lsu_exe_0_iresp_bits_uop_fu_code,\t// @[core.scala:54:14]\n input [3:0] io_lsu_exe_0_iresp_bits_uop_ctrl_br_type,\t// @[core.scala:54:14]\n input [1:0] io_lsu_exe_0_iresp_bits_uop_ctrl_op1_sel,\t// @[core.scala:54:14]\n input [2:0] io_lsu_exe_0_iresp_bits_uop_ctrl_op2_sel,\t// @[core.scala:54:14]\n input [2:0] io_lsu_exe_0_iresp_bits_uop_ctrl_imm_sel,\t// @[core.scala:54:14]\n input [4:0] io_lsu_exe_0_iresp_bits_uop_ctrl_op_fcn,\t// @[core.scala:54:14]\n input io_lsu_exe_0_iresp_bits_uop_ctrl_fcn_dw,\t// @[core.scala:54:14]\n input [2:0] io_lsu_exe_0_iresp_bits_uop_ctrl_csr_cmd,\t// @[core.scala:54:14]\n input io_lsu_exe_0_iresp_bits_uop_ctrl_is_load,\t// @[core.scala:54:14]\n input io_lsu_exe_0_iresp_bits_uop_ctrl_is_sta,\t// @[core.scala:54:14]\n input io_lsu_exe_0_iresp_bits_uop_ctrl_is_std,\t// @[core.scala:54:14]\n input [1:0] io_lsu_exe_0_iresp_bits_uop_iw_state,\t// @[core.scala:54:14]\n input io_lsu_exe_0_iresp_bits_uop_iw_p1_poisoned,\t// @[core.scala:54:14]\n input io_lsu_exe_0_iresp_bits_uop_iw_p2_poisoned,\t// @[core.scala:54:14]\n input io_lsu_exe_0_iresp_bits_uop_is_br,\t// @[core.scala:54:14]\n input io_lsu_exe_0_iresp_bits_uop_is_jalr,\t// @[core.scala:54:14]\n input io_lsu_exe_0_iresp_bits_uop_is_jal,\t// @[core.scala:54:14]\n input io_lsu_exe_0_iresp_bits_uop_is_sfb,\t// @[core.scala:54:14]\n input [15:0] io_lsu_exe_0_iresp_bits_uop_br_mask,\t// @[core.scala:54:14]\n input [3:0] io_lsu_exe_0_iresp_bits_uop_br_tag,\t// @[core.scala:54:14]\n input [4:0] io_lsu_exe_0_iresp_bits_uop_ftq_idx,\t// @[core.scala:54:14]\n input io_lsu_exe_0_iresp_bits_uop_edge_inst,\t// @[core.scala:54:14]\n input [5:0] io_lsu_exe_0_iresp_bits_uop_pc_lob,\t// @[core.scala:54:14]\n input io_lsu_exe_0_iresp_bits_uop_taken,\t// @[core.scala:54:14]\n input [19:0] io_lsu_exe_0_iresp_bits_uop_imm_packed,\t// @[core.scala:54:14]\n input [11:0] io_lsu_exe_0_iresp_bits_uop_csr_addr,\t// @[core.scala:54:14]\n input [6:0] io_lsu_exe_0_iresp_bits_uop_rob_idx,\t// @[core.scala:54:14]\n input [4:0] io_lsu_exe_0_iresp_bits_uop_ldq_idx,\t// @[core.scala:54:14]\n input [4:0] io_lsu_exe_0_iresp_bits_uop_stq_idx,\t// @[core.scala:54:14]\n input [1:0] io_lsu_exe_0_iresp_bits_uop_rxq_idx,\t// @[core.scala:54:14]\n input [6:0] io_lsu_exe_0_iresp_bits_uop_pdst,\t// @[core.scala:54:14]\n input [6:0] io_lsu_exe_0_iresp_bits_uop_prs1,\t// @[core.scala:54:14]\n input [6:0] io_lsu_exe_0_iresp_bits_uop_prs2,\t// @[core.scala:54:14]\n input [6:0] io_lsu_exe_0_iresp_bits_uop_prs3,\t// @[core.scala:54:14]\n input [4:0] io_lsu_exe_0_iresp_bits_uop_ppred,\t// @[core.scala:54:14]\n input io_lsu_exe_0_iresp_bits_uop_prs1_busy,\t// @[core.scala:54:14]\n input io_lsu_exe_0_iresp_bits_uop_prs2_busy,\t// @[core.scala:54:14]\n input io_lsu_exe_0_iresp_bits_uop_prs3_busy,\t// @[core.scala:54:14]\n input io_lsu_exe_0_iresp_bits_uop_ppred_busy,\t// @[core.scala:54:14]\n input [6:0] io_lsu_exe_0_iresp_bits_uop_stale_pdst,\t// @[core.scala:54:14]\n input io_lsu_exe_0_iresp_bits_uop_exception,\t// @[core.scala:54:14]\n input [63:0] io_lsu_exe_0_iresp_bits_uop_exc_cause,\t// @[core.scala:54:14]\n input io_lsu_exe_0_iresp_bits_uop_bypassable,\t// @[core.scala:54:14]\n input [4:0] io_lsu_exe_0_iresp_bits_uop_mem_cmd,\t// @[core.scala:54:14]\n input [1:0] io_lsu_exe_0_iresp_bits_uop_mem_size,\t// @[core.scala:54:14]\n input io_lsu_exe_0_iresp_bits_uop_mem_signed,\t// @[core.scala:54:14]\n input io_lsu_exe_0_iresp_bits_uop_is_fence,\t// @[core.scala:54:14]\n input io_lsu_exe_0_iresp_bits_uop_is_fencei,\t// @[core.scala:54:14]\n input io_lsu_exe_0_iresp_bits_uop_is_amo,\t// @[core.scala:54:14]\n input io_lsu_exe_0_iresp_bits_uop_uses_ldq,\t// @[core.scala:54:14]\n input io_lsu_exe_0_iresp_bits_uop_uses_stq,\t// @[core.scala:54:14]\n input io_lsu_exe_0_iresp_bits_uop_is_sys_pc2epc,\t// @[core.scala:54:14]\n input io_lsu_exe_0_iresp_bits_uop_is_unique,\t// @[core.scala:54:14]\n input io_lsu_exe_0_iresp_bits_uop_flush_on_commit,\t// @[core.scala:54:14]\n input io_lsu_exe_0_iresp_bits_uop_ldst_is_rs1,\t// @[core.scala:54:14]\n input [5:0] io_lsu_exe_0_iresp_bits_uop_ldst,\t// @[core.scala:54:14]\n input [5:0] io_lsu_exe_0_iresp_bits_uop_lrs1,\t// @[core.scala:54:14]\n input [5:0] io_lsu_exe_0_iresp_bits_uop_lrs2,\t// @[core.scala:54:14]\n input [5:0] io_lsu_exe_0_iresp_bits_uop_lrs3,\t// @[core.scala:54:14]\n input io_lsu_exe_0_iresp_bits_uop_ldst_val,\t// @[core.scala:54:14]\n input [1:0] io_lsu_exe_0_iresp_bits_uop_dst_rtype,\t// @[core.scala:54:14]\n input [1:0] io_lsu_exe_0_iresp_bits_uop_lrs1_rtype,\t// @[core.scala:54:14]\n input [1:0] io_lsu_exe_0_iresp_bits_uop_lrs2_rtype,\t// @[core.scala:54:14]\n input io_lsu_exe_0_iresp_bits_uop_frs3_en,\t// @[core.scala:54:14]\n input io_lsu_exe_0_iresp_bits_uop_fp_val,\t// @[core.scala:54:14]\n input io_lsu_exe_0_iresp_bits_uop_fp_single,\t// @[core.scala:54:14]\n input io_lsu_exe_0_iresp_bits_uop_xcpt_pf_if,\t// @[core.scala:54:14]\n input io_lsu_exe_0_iresp_bits_uop_xcpt_ae_if,\t// @[core.scala:54:14]\n input io_lsu_exe_0_iresp_bits_uop_xcpt_ma_if,\t// @[core.scala:54:14]\n input io_lsu_exe_0_iresp_bits_uop_bp_debug_if,\t// @[core.scala:54:14]\n input io_lsu_exe_0_iresp_bits_uop_bp_xcpt_if,\t// @[core.scala:54:14]\n input [1:0] io_lsu_exe_0_iresp_bits_uop_debug_fsrc,\t// @[core.scala:54:14]\n input [1:0] io_lsu_exe_0_iresp_bits_uop_debug_tsrc,\t// @[core.scala:54:14]\n input [63:0] io_lsu_exe_0_iresp_bits_data,\t// @[core.scala:54:14]\n input io_lsu_exe_0_fresp_valid,\t// @[core.scala:54:14]\n input [6:0] io_lsu_exe_0_fresp_bits_uop_uopc,\t// @[core.scala:54:14]\n input [31:0] io_lsu_exe_0_fresp_bits_uop_inst,\t// @[core.scala:54:14]\n input [31:0] io_lsu_exe_0_fresp_bits_uop_debug_inst,\t// @[core.scala:54:14]\n input io_lsu_exe_0_fresp_bits_uop_is_rvc,\t// @[core.scala:54:14]\n input [39:0] io_lsu_exe_0_fresp_bits_uop_debug_pc,\t// @[core.scala:54:14]\n input [2:0] io_lsu_exe_0_fresp_bits_uop_iq_type,\t// @[core.scala:54:14]\n input [9:0] io_lsu_exe_0_fresp_bits_uop_fu_code,\t// @[core.scala:54:14]\n input [3:0] io_lsu_exe_0_fresp_bits_uop_ctrl_br_type,\t// @[core.scala:54:14]\n input [1:0] io_lsu_exe_0_fresp_bits_uop_ctrl_op1_sel,\t// @[core.scala:54:14]\n input [2:0] io_lsu_exe_0_fresp_bits_uop_ctrl_op2_sel,\t// @[core.scala:54:14]\n input [2:0] io_lsu_exe_0_fresp_bits_uop_ctrl_imm_sel,\t// @[core.scala:54:14]\n input [4:0] io_lsu_exe_0_fresp_bits_uop_ctrl_op_fcn,\t// @[core.scala:54:14]\n input io_lsu_exe_0_fresp_bits_uop_ctrl_fcn_dw,\t// @[core.scala:54:14]\n input [2:0] io_lsu_exe_0_fresp_bits_uop_ctrl_csr_cmd,\t// @[core.scala:54:14]\n input io_lsu_exe_0_fresp_bits_uop_ctrl_is_load,\t// @[core.scala:54:14]\n input io_lsu_exe_0_fresp_bits_uop_ctrl_is_sta,\t// @[core.scala:54:14]\n input io_lsu_exe_0_fresp_bits_uop_ctrl_is_std,\t// @[core.scala:54:14]\n input [1:0] io_lsu_exe_0_fresp_bits_uop_iw_state,\t// @[core.scala:54:14]\n input io_lsu_exe_0_fresp_bits_uop_iw_p1_poisoned,\t// @[core.scala:54:14]\n input io_lsu_exe_0_fresp_bits_uop_iw_p2_poisoned,\t// @[core.scala:54:14]\n input io_lsu_exe_0_fresp_bits_uop_is_br,\t// @[core.scala:54:14]\n input io_lsu_exe_0_fresp_bits_uop_is_jalr,\t// @[core.scala:54:14]\n input io_lsu_exe_0_fresp_bits_uop_is_jal,\t// @[core.scala:54:14]\n input io_lsu_exe_0_fresp_bits_uop_is_sfb,\t// @[core.scala:54:14]\n input [15:0] io_lsu_exe_0_fresp_bits_uop_br_mask,\t// @[core.scala:54:14]\n input [3:0] io_lsu_exe_0_fresp_bits_uop_br_tag,\t// @[core.scala:54:14]\n input [4:0] io_lsu_exe_0_fresp_bits_uop_ftq_idx,\t// @[core.scala:54:14]\n input io_lsu_exe_0_fresp_bits_uop_edge_inst,\t// @[core.scala:54:14]\n input [5:0] io_lsu_exe_0_fresp_bits_uop_pc_lob,\t// @[core.scala:54:14]\n input io_lsu_exe_0_fresp_bits_uop_taken,\t// @[core.scala:54:14]\n input [19:0] io_lsu_exe_0_fresp_bits_uop_imm_packed,\t// @[core.scala:54:14]\n input [11:0] io_lsu_exe_0_fresp_bits_uop_csr_addr,\t// @[core.scala:54:14]\n input [6:0] io_lsu_exe_0_fresp_bits_uop_rob_idx,\t// @[core.scala:54:14]\n input [4:0] io_lsu_exe_0_fresp_bits_uop_ldq_idx,\t// @[core.scala:54:14]\n input [4:0] io_lsu_exe_0_fresp_bits_uop_stq_idx,\t// @[core.scala:54:14]\n input [1:0] io_lsu_exe_0_fresp_bits_uop_rxq_idx,\t// @[core.scala:54:14]\n input [6:0] io_lsu_exe_0_fresp_bits_uop_pdst,\t// @[core.scala:54:14]\n input [6:0] io_lsu_exe_0_fresp_bits_uop_prs1,\t// @[core.scala:54:14]\n input [6:0] io_lsu_exe_0_fresp_bits_uop_prs2,\t// @[core.scala:54:14]\n input [6:0] io_lsu_exe_0_fresp_bits_uop_prs3,\t// @[core.scala:54:14]\n input [4:0] io_lsu_exe_0_fresp_bits_uop_ppred,\t// @[core.scala:54:14]\n input io_lsu_exe_0_fresp_bits_uop_prs1_busy,\t// @[core.scala:54:14]\n input io_lsu_exe_0_fresp_bits_uop_prs2_busy,\t// @[core.scala:54:14]\n input io_lsu_exe_0_fresp_bits_uop_prs3_busy,\t// @[core.scala:54:14]\n input io_lsu_exe_0_fresp_bits_uop_ppred_busy,\t// @[core.scala:54:14]\n input [6:0] io_lsu_exe_0_fresp_bits_uop_stale_pdst,\t// @[core.scala:54:14]\n input io_lsu_exe_0_fresp_bits_uop_exception,\t// @[core.scala:54:14]\n input [63:0] io_lsu_exe_0_fresp_bits_uop_exc_cause,\t// @[core.scala:54:14]\n input io_lsu_exe_0_fresp_bits_uop_bypassable,\t// @[core.scala:54:14]\n input [4:0] io_lsu_exe_0_fresp_bits_uop_mem_cmd,\t// @[core.scala:54:14]\n input [1:0] io_lsu_exe_0_fresp_bits_uop_mem_size,\t// @[core.scala:54:14]\n input io_lsu_exe_0_fresp_bits_uop_mem_signed,\t// @[core.scala:54:14]\n input io_lsu_exe_0_fresp_bits_uop_is_fence,\t// @[core.scala:54:14]\n input io_lsu_exe_0_fresp_bits_uop_is_fencei,\t// @[core.scala:54:14]\n input io_lsu_exe_0_fresp_bits_uop_is_amo,\t// @[core.scala:54:14]\n input io_lsu_exe_0_fresp_bits_uop_uses_ldq,\t// @[core.scala:54:14]\n input io_lsu_exe_0_fresp_bits_uop_uses_stq,\t// @[core.scala:54:14]\n input io_lsu_exe_0_fresp_bits_uop_is_sys_pc2epc,\t// @[core.scala:54:14]\n input io_lsu_exe_0_fresp_bits_uop_is_unique,\t// @[core.scala:54:14]\n input io_lsu_exe_0_fresp_bits_uop_flush_on_commit,\t// @[core.scala:54:14]\n input io_lsu_exe_0_fresp_bits_uop_ldst_is_rs1,\t// @[core.scala:54:14]\n input [5:0] io_lsu_exe_0_fresp_bits_uop_ldst,\t// @[core.scala:54:14]\n input [5:0] io_lsu_exe_0_fresp_bits_uop_lrs1,\t// @[core.scala:54:14]\n input [5:0] io_lsu_exe_0_fresp_bits_uop_lrs2,\t// @[core.scala:54:14]\n input [5:0] io_lsu_exe_0_fresp_bits_uop_lrs3,\t// @[core.scala:54:14]\n input io_lsu_exe_0_fresp_bits_uop_ldst_val,\t// @[core.scala:54:14]\n input [1:0] io_lsu_exe_0_fresp_bits_uop_dst_rtype,\t// @[core.scala:54:14]\n input [1:0] io_lsu_exe_0_fresp_bits_uop_lrs1_rtype,\t// @[core.scala:54:14]\n input [1:0] io_lsu_exe_0_fresp_bits_uop_lrs2_rtype,\t// @[core.scala:54:14]\n input io_lsu_exe_0_fresp_bits_uop_frs3_en,\t// @[core.scala:54:14]\n input io_lsu_exe_0_fresp_bits_uop_fp_val,\t// @[core.scala:54:14]\n input io_lsu_exe_0_fresp_bits_uop_fp_single,\t// @[core.scala:54:14]\n input io_lsu_exe_0_fresp_bits_uop_xcpt_pf_if,\t// @[core.scala:54:14]\n input io_lsu_exe_0_fresp_bits_uop_xcpt_ae_if,\t// @[core.scala:54:14]\n input io_lsu_exe_0_fresp_bits_uop_xcpt_ma_if,\t// @[core.scala:54:14]\n input io_lsu_exe_0_fresp_bits_uop_bp_debug_if,\t// @[core.scala:54:14]\n input io_lsu_exe_0_fresp_bits_uop_bp_xcpt_if,\t// @[core.scala:54:14]\n input [1:0] io_lsu_exe_0_fresp_bits_uop_debug_fsrc,\t// @[core.scala:54:14]\n input [1:0] io_lsu_exe_0_fresp_bits_uop_debug_tsrc,\t// @[core.scala:54:14]\n input [64:0] io_lsu_exe_0_fresp_bits_data,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_0_valid,\t// @[core.scala:54:14]\n output [6:0] io_lsu_dis_uops_0_bits_uopc,\t// @[core.scala:54:14]\n output [31:0] io_lsu_dis_uops_0_bits_inst,\t// @[core.scala:54:14]\n output [31:0] io_lsu_dis_uops_0_bits_debug_inst,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_0_bits_is_rvc,\t// @[core.scala:54:14]\n output [39:0] io_lsu_dis_uops_0_bits_debug_pc,\t// @[core.scala:54:14]\n output [2:0] io_lsu_dis_uops_0_bits_iq_type,\t// @[core.scala:54:14]\n output [9:0] io_lsu_dis_uops_0_bits_fu_code,\t// @[core.scala:54:14]\n output [3:0] io_lsu_dis_uops_0_bits_ctrl_br_type,\t// @[core.scala:54:14]\n output [1:0] io_lsu_dis_uops_0_bits_ctrl_op1_sel,\t// @[core.scala:54:14]\n output [2:0] io_lsu_dis_uops_0_bits_ctrl_op2_sel,\t// @[core.scala:54:14]\n output [2:0] io_lsu_dis_uops_0_bits_ctrl_imm_sel,\t// @[core.scala:54:14]\n output [4:0] io_lsu_dis_uops_0_bits_ctrl_op_fcn,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_0_bits_ctrl_fcn_dw,\t// @[core.scala:54:14]\n output [2:0] io_lsu_dis_uops_0_bits_ctrl_csr_cmd,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_0_bits_ctrl_is_load,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_0_bits_ctrl_is_sta,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_0_bits_ctrl_is_std,\t// @[core.scala:54:14]\n output [1:0] io_lsu_dis_uops_0_bits_iw_state,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_0_bits_iw_p1_poisoned,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_0_bits_iw_p2_poisoned,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_0_bits_is_br,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_0_bits_is_jalr,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_0_bits_is_jal,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_0_bits_is_sfb,\t// @[core.scala:54:14]\n output [15:0] io_lsu_dis_uops_0_bits_br_mask,\t// @[core.scala:54:14]\n output [3:0] io_lsu_dis_uops_0_bits_br_tag,\t// @[core.scala:54:14]\n output [4:0] io_lsu_dis_uops_0_bits_ftq_idx,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_0_bits_edge_inst,\t// @[core.scala:54:14]\n output [5:0] io_lsu_dis_uops_0_bits_pc_lob,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_0_bits_taken,\t// @[core.scala:54:14]\n output [19:0] io_lsu_dis_uops_0_bits_imm_packed,\t// @[core.scala:54:14]\n output [11:0] io_lsu_dis_uops_0_bits_csr_addr,\t// @[core.scala:54:14]\n output [6:0] io_lsu_dis_uops_0_bits_rob_idx,\t// @[core.scala:54:14]\n output [4:0] io_lsu_dis_uops_0_bits_ldq_idx,\t// @[core.scala:54:14]\n output [4:0] io_lsu_dis_uops_0_bits_stq_idx,\t// @[core.scala:54:14]\n output [1:0] io_lsu_dis_uops_0_bits_rxq_idx,\t// @[core.scala:54:14]\n output [6:0] io_lsu_dis_uops_0_bits_pdst,\t// @[core.scala:54:14]\n output [6:0] io_lsu_dis_uops_0_bits_prs1,\t// @[core.scala:54:14]\n output [6:0] io_lsu_dis_uops_0_bits_prs2,\t// @[core.scala:54:14]\n output [6:0] io_lsu_dis_uops_0_bits_prs3,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_0_bits_prs1_busy,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_0_bits_prs2_busy,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_0_bits_prs3_busy,\t// @[core.scala:54:14]\n output [6:0] io_lsu_dis_uops_0_bits_stale_pdst,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_0_bits_exception,\t// @[core.scala:54:14]\n output [63:0] io_lsu_dis_uops_0_bits_exc_cause,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_0_bits_bypassable,\t// @[core.scala:54:14]\n output [4:0] io_lsu_dis_uops_0_bits_mem_cmd,\t// @[core.scala:54:14]\n output [1:0] io_lsu_dis_uops_0_bits_mem_size,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_0_bits_mem_signed,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_0_bits_is_fence,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_0_bits_is_fencei,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_0_bits_is_amo,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_0_bits_uses_ldq,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_0_bits_uses_stq,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_0_bits_is_sys_pc2epc,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_0_bits_is_unique,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_0_bits_flush_on_commit,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_0_bits_ldst_is_rs1,\t// @[core.scala:54:14]\n output [5:0] io_lsu_dis_uops_0_bits_ldst,\t// @[core.scala:54:14]\n output [5:0] io_lsu_dis_uops_0_bits_lrs1,\t// @[core.scala:54:14]\n output [5:0] io_lsu_dis_uops_0_bits_lrs2,\t// @[core.scala:54:14]\n output [5:0] io_lsu_dis_uops_0_bits_lrs3,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_0_bits_ldst_val,\t// @[core.scala:54:14]\n output [1:0] io_lsu_dis_uops_0_bits_dst_rtype,\t// @[core.scala:54:14]\n output [1:0] io_lsu_dis_uops_0_bits_lrs1_rtype,\t// @[core.scala:54:14]\n output [1:0] io_lsu_dis_uops_0_bits_lrs2_rtype,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_0_bits_frs3_en,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_0_bits_fp_val,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_0_bits_fp_single,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_0_bits_xcpt_pf_if,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_0_bits_xcpt_ae_if,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_0_bits_xcpt_ma_if,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_0_bits_bp_debug_if,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_0_bits_bp_xcpt_if,\t// @[core.scala:54:14]\n output [1:0] io_lsu_dis_uops_0_bits_debug_fsrc,\t// @[core.scala:54:14]\n output [1:0] io_lsu_dis_uops_0_bits_debug_tsrc,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_1_valid,\t// @[core.scala:54:14]\n output [6:0] io_lsu_dis_uops_1_bits_uopc,\t// @[core.scala:54:14]\n output [31:0] io_lsu_dis_uops_1_bits_inst,\t// @[core.scala:54:14]\n output [31:0] io_lsu_dis_uops_1_bits_debug_inst,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_1_bits_is_rvc,\t// @[core.scala:54:14]\n output [39:0] io_lsu_dis_uops_1_bits_debug_pc,\t// @[core.scala:54:14]\n output [2:0] io_lsu_dis_uops_1_bits_iq_type,\t// @[core.scala:54:14]\n output [9:0] io_lsu_dis_uops_1_bits_fu_code,\t// @[core.scala:54:14]\n output [3:0] io_lsu_dis_uops_1_bits_ctrl_br_type,\t// @[core.scala:54:14]\n output [1:0] io_lsu_dis_uops_1_bits_ctrl_op1_sel,\t// @[core.scala:54:14]\n output [2:0] io_lsu_dis_uops_1_bits_ctrl_op2_sel,\t// @[core.scala:54:14]\n output [2:0] io_lsu_dis_uops_1_bits_ctrl_imm_sel,\t// @[core.scala:54:14]\n output [4:0] io_lsu_dis_uops_1_bits_ctrl_op_fcn,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_1_bits_ctrl_fcn_dw,\t// @[core.scala:54:14]\n output [2:0] io_lsu_dis_uops_1_bits_ctrl_csr_cmd,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_1_bits_ctrl_is_load,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_1_bits_ctrl_is_sta,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_1_bits_ctrl_is_std,\t// @[core.scala:54:14]\n output [1:0] io_lsu_dis_uops_1_bits_iw_state,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_1_bits_iw_p1_poisoned,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_1_bits_iw_p2_poisoned,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_1_bits_is_br,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_1_bits_is_jalr,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_1_bits_is_jal,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_1_bits_is_sfb,\t// @[core.scala:54:14]\n output [15:0] io_lsu_dis_uops_1_bits_br_mask,\t// @[core.scala:54:14]\n output [3:0] io_lsu_dis_uops_1_bits_br_tag,\t// @[core.scala:54:14]\n output [4:0] io_lsu_dis_uops_1_bits_ftq_idx,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_1_bits_edge_inst,\t// @[core.scala:54:14]\n output [5:0] io_lsu_dis_uops_1_bits_pc_lob,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_1_bits_taken,\t// @[core.scala:54:14]\n output [19:0] io_lsu_dis_uops_1_bits_imm_packed,\t// @[core.scala:54:14]\n output [11:0] io_lsu_dis_uops_1_bits_csr_addr,\t// @[core.scala:54:14]\n output [6:0] io_lsu_dis_uops_1_bits_rob_idx,\t// @[core.scala:54:14]\n output [4:0] io_lsu_dis_uops_1_bits_ldq_idx,\t// @[core.scala:54:14]\n output [4:0] io_lsu_dis_uops_1_bits_stq_idx,\t// @[core.scala:54:14]\n output [1:0] io_lsu_dis_uops_1_bits_rxq_idx,\t// @[core.scala:54:14]\n output [6:0] io_lsu_dis_uops_1_bits_pdst,\t// @[core.scala:54:14]\n output [6:0] io_lsu_dis_uops_1_bits_prs1,\t// @[core.scala:54:14]\n output [6:0] io_lsu_dis_uops_1_bits_prs2,\t// @[core.scala:54:14]\n output [6:0] io_lsu_dis_uops_1_bits_prs3,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_1_bits_prs1_busy,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_1_bits_prs2_busy,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_1_bits_prs3_busy,\t// @[core.scala:54:14]\n output [6:0] io_lsu_dis_uops_1_bits_stale_pdst,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_1_bits_exception,\t// @[core.scala:54:14]\n output [63:0] io_lsu_dis_uops_1_bits_exc_cause,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_1_bits_bypassable,\t// @[core.scala:54:14]\n output [4:0] io_lsu_dis_uops_1_bits_mem_cmd,\t// @[core.scala:54:14]\n output [1:0] io_lsu_dis_uops_1_bits_mem_size,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_1_bits_mem_signed,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_1_bits_is_fence,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_1_bits_is_fencei,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_1_bits_is_amo,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_1_bits_uses_ldq,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_1_bits_uses_stq,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_1_bits_is_sys_pc2epc,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_1_bits_is_unique,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_1_bits_flush_on_commit,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_1_bits_ldst_is_rs1,\t// @[core.scala:54:14]\n output [5:0] io_lsu_dis_uops_1_bits_ldst,\t// @[core.scala:54:14]\n output [5:0] io_lsu_dis_uops_1_bits_lrs1,\t// @[core.scala:54:14]\n output [5:0] io_lsu_dis_uops_1_bits_lrs2,\t// @[core.scala:54:14]\n output [5:0] io_lsu_dis_uops_1_bits_lrs3,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_1_bits_ldst_val,\t// @[core.scala:54:14]\n output [1:0] io_lsu_dis_uops_1_bits_dst_rtype,\t// @[core.scala:54:14]\n output [1:0] io_lsu_dis_uops_1_bits_lrs1_rtype,\t// @[core.scala:54:14]\n output [1:0] io_lsu_dis_uops_1_bits_lrs2_rtype,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_1_bits_frs3_en,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_1_bits_fp_val,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_1_bits_fp_single,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_1_bits_xcpt_pf_if,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_1_bits_xcpt_ae_if,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_1_bits_xcpt_ma_if,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_1_bits_bp_debug_if,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_1_bits_bp_xcpt_if,\t// @[core.scala:54:14]\n output [1:0] io_lsu_dis_uops_1_bits_debug_fsrc,\t// @[core.scala:54:14]\n output [1:0] io_lsu_dis_uops_1_bits_debug_tsrc,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_2_valid,\t// @[core.scala:54:14]\n output [6:0] io_lsu_dis_uops_2_bits_uopc,\t// @[core.scala:54:14]\n output [31:0] io_lsu_dis_uops_2_bits_inst,\t// @[core.scala:54:14]\n output [31:0] io_lsu_dis_uops_2_bits_debug_inst,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_2_bits_is_rvc,\t// @[core.scala:54:14]\n output [39:0] io_lsu_dis_uops_2_bits_debug_pc,\t// @[core.scala:54:14]\n output [2:0] io_lsu_dis_uops_2_bits_iq_type,\t// @[core.scala:54:14]\n output [9:0] io_lsu_dis_uops_2_bits_fu_code,\t// @[core.scala:54:14]\n output [3:0] io_lsu_dis_uops_2_bits_ctrl_br_type,\t// @[core.scala:54:14]\n output [1:0] io_lsu_dis_uops_2_bits_ctrl_op1_sel,\t// @[core.scala:54:14]\n output [2:0] io_lsu_dis_uops_2_bits_ctrl_op2_sel,\t// @[core.scala:54:14]\n output [2:0] io_lsu_dis_uops_2_bits_ctrl_imm_sel,\t// @[core.scala:54:14]\n output [4:0] io_lsu_dis_uops_2_bits_ctrl_op_fcn,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_2_bits_ctrl_fcn_dw,\t// @[core.scala:54:14]\n output [2:0] io_lsu_dis_uops_2_bits_ctrl_csr_cmd,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_2_bits_ctrl_is_load,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_2_bits_ctrl_is_sta,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_2_bits_ctrl_is_std,\t// @[core.scala:54:14]\n output [1:0] io_lsu_dis_uops_2_bits_iw_state,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_2_bits_iw_p1_poisoned,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_2_bits_iw_p2_poisoned,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_2_bits_is_br,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_2_bits_is_jalr,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_2_bits_is_jal,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_2_bits_is_sfb,\t// @[core.scala:54:14]\n output [15:0] io_lsu_dis_uops_2_bits_br_mask,\t// @[core.scala:54:14]\n output [3:0] io_lsu_dis_uops_2_bits_br_tag,\t// @[core.scala:54:14]\n output [4:0] io_lsu_dis_uops_2_bits_ftq_idx,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_2_bits_edge_inst,\t// @[core.scala:54:14]\n output [5:0] io_lsu_dis_uops_2_bits_pc_lob,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_2_bits_taken,\t// @[core.scala:54:14]\n output [19:0] io_lsu_dis_uops_2_bits_imm_packed,\t// @[core.scala:54:14]\n output [11:0] io_lsu_dis_uops_2_bits_csr_addr,\t// @[core.scala:54:14]\n output [6:0] io_lsu_dis_uops_2_bits_rob_idx,\t// @[core.scala:54:14]\n output [4:0] io_lsu_dis_uops_2_bits_ldq_idx,\t// @[core.scala:54:14]\n output [4:0] io_lsu_dis_uops_2_bits_stq_idx,\t// @[core.scala:54:14]\n output [1:0] io_lsu_dis_uops_2_bits_rxq_idx,\t// @[core.scala:54:14]\n output [6:0] io_lsu_dis_uops_2_bits_pdst,\t// @[core.scala:54:14]\n output [6:0] io_lsu_dis_uops_2_bits_prs1,\t// @[core.scala:54:14]\n output [6:0] io_lsu_dis_uops_2_bits_prs2,\t// @[core.scala:54:14]\n output [6:0] io_lsu_dis_uops_2_bits_prs3,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_2_bits_prs1_busy,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_2_bits_prs2_busy,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_2_bits_prs3_busy,\t// @[core.scala:54:14]\n output [6:0] io_lsu_dis_uops_2_bits_stale_pdst,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_2_bits_exception,\t// @[core.scala:54:14]\n output [63:0] io_lsu_dis_uops_2_bits_exc_cause,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_2_bits_bypassable,\t// @[core.scala:54:14]\n output [4:0] io_lsu_dis_uops_2_bits_mem_cmd,\t// @[core.scala:54:14]\n output [1:0] io_lsu_dis_uops_2_bits_mem_size,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_2_bits_mem_signed,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_2_bits_is_fence,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_2_bits_is_fencei,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_2_bits_is_amo,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_2_bits_uses_ldq,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_2_bits_uses_stq,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_2_bits_is_sys_pc2epc,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_2_bits_is_unique,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_2_bits_flush_on_commit,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_2_bits_ldst_is_rs1,\t// @[core.scala:54:14]\n output [5:0] io_lsu_dis_uops_2_bits_ldst,\t// @[core.scala:54:14]\n output [5:0] io_lsu_dis_uops_2_bits_lrs1,\t// @[core.scala:54:14]\n output [5:0] io_lsu_dis_uops_2_bits_lrs2,\t// @[core.scala:54:14]\n output [5:0] io_lsu_dis_uops_2_bits_lrs3,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_2_bits_ldst_val,\t// @[core.scala:54:14]\n output [1:0] io_lsu_dis_uops_2_bits_dst_rtype,\t// @[core.scala:54:14]\n output [1:0] io_lsu_dis_uops_2_bits_lrs1_rtype,\t// @[core.scala:54:14]\n output [1:0] io_lsu_dis_uops_2_bits_lrs2_rtype,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_2_bits_frs3_en,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_2_bits_fp_val,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_2_bits_fp_single,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_2_bits_xcpt_pf_if,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_2_bits_xcpt_ae_if,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_2_bits_xcpt_ma_if,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_2_bits_bp_debug_if,\t// @[core.scala:54:14]\n output io_lsu_dis_uops_2_bits_bp_xcpt_if,\t// @[core.scala:54:14]\n output [1:0] io_lsu_dis_uops_2_bits_debug_fsrc,\t// @[core.scala:54:14]\n output [1:0] io_lsu_dis_uops_2_bits_debug_tsrc,\t// @[core.scala:54:14]\n input [4:0] io_lsu_dis_ldq_idx_0,\t// @[core.scala:54:14]\n input [4:0] io_lsu_dis_ldq_idx_1,\t// @[core.scala:54:14]\n input [4:0] io_lsu_dis_ldq_idx_2,\t// @[core.scala:54:14]\n input [4:0] io_lsu_dis_stq_idx_0,\t// @[core.scala:54:14]\n input [4:0] io_lsu_dis_stq_idx_1,\t// @[core.scala:54:14]\n input [4:0] io_lsu_dis_stq_idx_2,\t// @[core.scala:54:14]\n input io_lsu_ldq_full_0,\t// @[core.scala:54:14]\n input io_lsu_ldq_full_1,\t// @[core.scala:54:14]\n input io_lsu_ldq_full_2,\t// @[core.scala:54:14]\n input io_lsu_stq_full_0,\t// @[core.scala:54:14]\n input io_lsu_stq_full_1,\t// @[core.scala:54:14]\n input io_lsu_stq_full_2,\t// @[core.scala:54:14]\n input io_lsu_fp_stdata_ready,\t// @[core.scala:54:14]\n output io_lsu_fp_stdata_valid,\t// @[core.scala:54:14]\n output [6:0] io_lsu_fp_stdata_bits_uop_uopc,\t// @[core.scala:54:14]\n output [31:0] io_lsu_fp_stdata_bits_uop_inst,\t// @[core.scala:54:14]\n output [31:0] io_lsu_fp_stdata_bits_uop_debug_inst,\t// @[core.scala:54:14]\n output io_lsu_fp_stdata_bits_uop_is_rvc,\t// @[core.scala:54:14]\n output [39:0] io_lsu_fp_stdata_bits_uop_debug_pc,\t// @[core.scala:54:14]\n output [2:0] io_lsu_fp_stdata_bits_uop_iq_type,\t// @[core.scala:54:14]\n output [9:0] io_lsu_fp_stdata_bits_uop_fu_code,\t// @[core.scala:54:14]\n output [3:0] io_lsu_fp_stdata_bits_uop_ctrl_br_type,\t// @[core.scala:54:14]\n output [1:0] io_lsu_fp_stdata_bits_uop_ctrl_op1_sel,\t// @[core.scala:54:14]\n output [2:0] io_lsu_fp_stdata_bits_uop_ctrl_op2_sel,\t// @[core.scala:54:14]\n output [2:0] io_lsu_fp_stdata_bits_uop_ctrl_imm_sel,\t// @[core.scala:54:14]\n output [4:0] io_lsu_fp_stdata_bits_uop_ctrl_op_fcn,\t// @[core.scala:54:14]\n output io_lsu_fp_stdata_bits_uop_ctrl_fcn_dw,\t// @[core.scala:54:14]\n output [2:0] io_lsu_fp_stdata_bits_uop_ctrl_csr_cmd,\t// @[core.scala:54:14]\n output io_lsu_fp_stdata_bits_uop_ctrl_is_load,\t// @[core.scala:54:14]\n output io_lsu_fp_stdata_bits_uop_ctrl_is_sta,\t// @[core.scala:54:14]\n output io_lsu_fp_stdata_bits_uop_ctrl_is_std,\t// @[core.scala:54:14]\n output [1:0] io_lsu_fp_stdata_bits_uop_iw_state,\t// @[core.scala:54:14]\n output io_lsu_fp_stdata_bits_uop_iw_p1_poisoned,\t// @[core.scala:54:14]\n output io_lsu_fp_stdata_bits_uop_iw_p2_poisoned,\t// @[core.scala:54:14]\n output io_lsu_fp_stdata_bits_uop_is_br,\t// @[core.scala:54:14]\n output io_lsu_fp_stdata_bits_uop_is_jalr,\t// @[core.scala:54:14]\n output io_lsu_fp_stdata_bits_uop_is_jal,\t// @[core.scala:54:14]\n output io_lsu_fp_stdata_bits_uop_is_sfb,\t// @[core.scala:54:14]\n output [15:0] io_lsu_fp_stdata_bits_uop_br_mask,\t// @[core.scala:54:14]\n output [3:0] io_lsu_fp_stdata_bits_uop_br_tag,\t// @[core.scala:54:14]\n output [4:0] io_lsu_fp_stdata_bits_uop_ftq_idx,\t// @[core.scala:54:14]\n output io_lsu_fp_stdata_bits_uop_edge_inst,\t// @[core.scala:54:14]\n output [5:0] io_lsu_fp_stdata_bits_uop_pc_lob,\t// @[core.scala:54:14]\n output io_lsu_fp_stdata_bits_uop_taken,\t// @[core.scala:54:14]\n output [19:0] io_lsu_fp_stdata_bits_uop_imm_packed,\t// @[core.scala:54:14]\n output [11:0] io_lsu_fp_stdata_bits_uop_csr_addr,\t// @[core.scala:54:14]\n output [6:0] io_lsu_fp_stdata_bits_uop_rob_idx,\t// @[core.scala:54:14]\n output [4:0] io_lsu_fp_stdata_bits_uop_ldq_idx,\t// @[core.scala:54:14]\n output [4:0] io_lsu_fp_stdata_bits_uop_stq_idx,\t// @[core.scala:54:14]\n output [1:0] io_lsu_fp_stdata_bits_uop_rxq_idx,\t// @[core.scala:54:14]\n output [6:0] io_lsu_fp_stdata_bits_uop_pdst,\t// @[core.scala:54:14]\n output [6:0] io_lsu_fp_stdata_bits_uop_prs1,\t// @[core.scala:54:14]\n output [6:0] io_lsu_fp_stdata_bits_uop_prs2,\t// @[core.scala:54:14]\n output [6:0] io_lsu_fp_stdata_bits_uop_prs3,\t// @[core.scala:54:14]\n output [4:0] io_lsu_fp_stdata_bits_uop_ppred,\t// @[core.scala:54:14]\n output io_lsu_fp_stdata_bits_uop_prs1_busy,\t// @[core.scala:54:14]\n output io_lsu_fp_stdata_bits_uop_prs2_busy,\t// @[core.scala:54:14]\n output io_lsu_fp_stdata_bits_uop_prs3_busy,\t// @[core.scala:54:14]\n output io_lsu_fp_stdata_bits_uop_ppred_busy,\t// @[core.scala:54:14]\n output [6:0] io_lsu_fp_stdata_bits_uop_stale_pdst,\t// @[core.scala:54:14]\n output io_lsu_fp_stdata_bits_uop_exception,\t// @[core.scala:54:14]\n output [63:0] io_lsu_fp_stdata_bits_uop_exc_cause,\t// @[core.scala:54:14]\n output io_lsu_fp_stdata_bits_uop_bypassable,\t// @[core.scala:54:14]\n output [4:0] io_lsu_fp_stdata_bits_uop_mem_cmd,\t// @[core.scala:54:14]\n output [1:0] io_lsu_fp_stdata_bits_uop_mem_size,\t// @[core.scala:54:14]\n output io_lsu_fp_stdata_bits_uop_mem_signed,\t// @[core.scala:54:14]\n output io_lsu_fp_stdata_bits_uop_is_fence,\t// @[core.scala:54:14]\n output io_lsu_fp_stdata_bits_uop_is_fencei,\t// @[core.scala:54:14]\n output io_lsu_fp_stdata_bits_uop_is_amo,\t// @[core.scala:54:14]\n output io_lsu_fp_stdata_bits_uop_uses_ldq,\t// @[core.scala:54:14]\n output io_lsu_fp_stdata_bits_uop_uses_stq,\t// @[core.scala:54:14]\n output io_lsu_fp_stdata_bits_uop_is_sys_pc2epc,\t// @[core.scala:54:14]\n output io_lsu_fp_stdata_bits_uop_is_unique,\t// @[core.scala:54:14]\n output io_lsu_fp_stdata_bits_uop_flush_on_commit,\t// @[core.scala:54:14]\n output io_lsu_fp_stdata_bits_uop_ldst_is_rs1,\t// @[core.scala:54:14]\n output [5:0] io_lsu_fp_stdata_bits_uop_ldst,\t// @[core.scala:54:14]\n output [5:0] io_lsu_fp_stdata_bits_uop_lrs1,\t// @[core.scala:54:14]\n output [5:0] io_lsu_fp_stdata_bits_uop_lrs2,\t// @[core.scala:54:14]\n output [5:0] io_lsu_fp_stdata_bits_uop_lrs3,\t// @[core.scala:54:14]\n output io_lsu_fp_stdata_bits_uop_ldst_val,\t// @[core.scala:54:14]\n output [1:0] io_lsu_fp_stdata_bits_uop_dst_rtype,\t// @[core.scala:54:14]\n output [1:0] io_lsu_fp_stdata_bits_uop_lrs1_rtype,\t// @[core.scala:54:14]\n output [1:0] io_lsu_fp_stdata_bits_uop_lrs2_rtype,\t// @[core.scala:54:14]\n output io_lsu_fp_stdata_bits_uop_frs3_en,\t// @[core.scala:54:14]\n output io_lsu_fp_stdata_bits_uop_fp_val,\t// @[core.scala:54:14]\n output io_lsu_fp_stdata_bits_uop_fp_single,\t// @[core.scala:54:14]\n output io_lsu_fp_stdata_bits_uop_xcpt_pf_if,\t// @[core.scala:54:14]\n output io_lsu_fp_stdata_bits_uop_xcpt_ae_if,\t// @[core.scala:54:14]\n output io_lsu_fp_stdata_bits_uop_xcpt_ma_if,\t// @[core.scala:54:14]\n output io_lsu_fp_stdata_bits_uop_bp_debug_if,\t// @[core.scala:54:14]\n output io_lsu_fp_stdata_bits_uop_bp_xcpt_if,\t// @[core.scala:54:14]\n output [1:0] io_lsu_fp_stdata_bits_uop_debug_fsrc,\t// @[core.scala:54:14]\n output [1:0] io_lsu_fp_stdata_bits_uop_debug_tsrc,\t// @[core.scala:54:14]\n output [63:0] io_lsu_fp_stdata_bits_data,\t// @[core.scala:54:14]\n output io_lsu_fp_stdata_bits_predicated,\t// @[core.scala:54:14]\n output io_lsu_fp_stdata_bits_fflags_valid,\t// @[core.scala:54:14]\n output [6:0] io_lsu_fp_stdata_bits_fflags_bits_uop_uopc,\t// @[core.scala:54:14]\n output [31:0] io_lsu_fp_stdata_bits_fflags_bits_uop_inst,\t// @[core.scala:54:14]\n output [31:0] io_lsu_fp_stdata_bits_fflags_bits_uop_debug_inst,\t// @[core.scala:54:14]\n output io_lsu_fp_stdata_bits_fflags_bits_uop_is_rvc,\t// @[core.scala:54:14]\n output [39:0] io_lsu_fp_stdata_bits_fflags_bits_uop_debug_pc,\t// @[core.scala:54:14]\n output [2:0] io_lsu_fp_stdata_bits_fflags_bits_uop_iq_type,\t// @[core.scala:54:14]\n output [9:0] io_lsu_fp_stdata_bits_fflags_bits_uop_fu_code,\t// @[core.scala:54:14]\n output [3:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_br_type,\t// @[core.scala:54:14]\n output [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_op1_sel,\t// @[core.scala:54:14]\n output [2:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_op2_sel,\t// @[core.scala:54:14]\n output [2:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_imm_sel,\t// @[core.scala:54:14]\n output [4:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_op_fcn,\t// @[core.scala:54:14]\n output io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_fcn_dw,\t// @[core.scala:54:14]\n output [2:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_csr_cmd,\t// @[core.scala:54:14]\n output io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_is_load,\t// @[core.scala:54:14]\n output io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_is_sta,\t// @[core.scala:54:14]\n output io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_is_std,\t// @[core.scala:54:14]\n output [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_iw_state,\t// @[core.scala:54:14]\n output io_lsu_fp_stdata_bits_fflags_bits_uop_iw_p1_poisoned,\t// @[core.scala:54:14]\n output io_lsu_fp_stdata_bits_fflags_bits_uop_iw_p2_poisoned,\t// @[core.scala:54:14]\n output io_lsu_fp_stdata_bits_fflags_bits_uop_is_br,\t// @[core.scala:54:14]\n output io_lsu_fp_stdata_bits_fflags_bits_uop_is_jalr,\t// @[core.scala:54:14]\n output io_lsu_fp_stdata_bits_fflags_bits_uop_is_jal,\t// @[core.scala:54:14]\n output io_lsu_fp_stdata_bits_fflags_bits_uop_is_sfb,\t// @[core.scala:54:14]\n output [15:0] io_lsu_fp_stdata_bits_fflags_bits_uop_br_mask,\t// @[core.scala:54:14]\n output [3:0] io_lsu_fp_stdata_bits_fflags_bits_uop_br_tag,\t// @[core.scala:54:14]\n output [4:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ftq_idx,\t// @[core.scala:54:14]\n output io_lsu_fp_stdata_bits_fflags_bits_uop_edge_inst,\t// @[core.scala:54:14]\n output [5:0] io_lsu_fp_stdata_bits_fflags_bits_uop_pc_lob,\t// @[core.scala:54:14]\n output io_lsu_fp_stdata_bits_fflags_bits_uop_taken,\t// @[core.scala:54:14]\n output [19:0] io_lsu_fp_stdata_bits_fflags_bits_uop_imm_packed,\t// @[core.scala:54:14]\n output [11:0] io_lsu_fp_stdata_bits_fflags_bits_uop_csr_addr,\t// @[core.scala:54:14]\n output [6:0] io_lsu_fp_stdata_bits_fflags_bits_uop_rob_idx,\t// @[core.scala:54:14]\n output [4:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ldq_idx,\t// @[core.scala:54:14]\n output [4:0] io_lsu_fp_stdata_bits_fflags_bits_uop_stq_idx,\t// @[core.scala:54:14]\n output [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_rxq_idx,\t// @[core.scala:54:14]\n output [6:0] io_lsu_fp_stdata_bits_fflags_bits_uop_pdst,\t// @[core.scala:54:14]\n output [6:0] io_lsu_fp_stdata_bits_fflags_bits_uop_prs1,\t// @[core.scala:54:14]\n output [6:0] io_lsu_fp_stdata_bits_fflags_bits_uop_prs2,\t// @[core.scala:54:14]\n output [6:0] io_lsu_fp_stdata_bits_fflags_bits_uop_prs3,\t// @[core.scala:54:14]\n output [4:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ppred,\t// @[core.scala:54:14]\n output io_lsu_fp_stdata_bits_fflags_bits_uop_prs1_busy,\t// @[core.scala:54:14]\n output io_lsu_fp_stdata_bits_fflags_bits_uop_prs2_busy,\t// @[core.scala:54:14]\n output io_lsu_fp_stdata_bits_fflags_bits_uop_prs3_busy,\t// @[core.scala:54:14]\n output io_lsu_fp_stdata_bits_fflags_bits_uop_ppred_busy,\t// @[core.scala:54:14]\n output [6:0] io_lsu_fp_stdata_bits_fflags_bits_uop_stale_pdst,\t// @[core.scala:54:14]\n output io_lsu_fp_stdata_bits_fflags_bits_uop_exception,\t// @[core.scala:54:14]\n output [63:0] io_lsu_fp_stdata_bits_fflags_bits_uop_exc_cause,\t// @[core.scala:54:14]\n output io_lsu_fp_stdata_bits_fflags_bits_uop_bypassable,\t// @[core.scala:54:14]\n output [4:0] io_lsu_fp_stdata_bits_fflags_bits_uop_mem_cmd,\t// @[core.scala:54:14]\n output [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_mem_size,\t// @[core.scala:54:14]\n output io_lsu_fp_stdata_bits_fflags_bits_uop_mem_signed,\t// @[core.scala:54:14]\n output io_lsu_fp_stdata_bits_fflags_bits_uop_is_fence,\t// @[core.scala:54:14]\n output io_lsu_fp_stdata_bits_fflags_bits_uop_is_fencei,\t// @[core.scala:54:14]\n output io_lsu_fp_stdata_bits_fflags_bits_uop_is_amo,\t// @[core.scala:54:14]\n output io_lsu_fp_stdata_bits_fflags_bits_uop_uses_ldq,\t// @[core.scala:54:14]\n output io_lsu_fp_stdata_bits_fflags_bits_uop_uses_stq,\t// @[core.scala:54:14]\n output io_lsu_fp_stdata_bits_fflags_bits_uop_is_sys_pc2epc,\t// @[core.scala:54:14]\n output io_lsu_fp_stdata_bits_fflags_bits_uop_is_unique,\t// @[core.scala:54:14]\n output io_lsu_fp_stdata_bits_fflags_bits_uop_flush_on_commit,\t// @[core.scala:54:14]\n output io_lsu_fp_stdata_bits_fflags_bits_uop_ldst_is_rs1,\t// @[core.scala:54:14]\n output [5:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ldst,\t// @[core.scala:54:14]\n output [5:0] io_lsu_fp_stdata_bits_fflags_bits_uop_lrs1,\t// @[core.scala:54:14]\n output [5:0] io_lsu_fp_stdata_bits_fflags_bits_uop_lrs2,\t// @[core.scala:54:14]\n output [5:0] io_lsu_fp_stdata_bits_fflags_bits_uop_lrs3,\t// @[core.scala:54:14]\n output io_lsu_fp_stdata_bits_fflags_bits_uop_ldst_val,\t// @[core.scala:54:14]\n output [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_dst_rtype,\t// @[core.scala:54:14]\n output [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_lrs1_rtype,\t// @[core.scala:54:14]\n output [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_lrs2_rtype,\t// @[core.scala:54:14]\n output io_lsu_fp_stdata_bits_fflags_bits_uop_frs3_en,\t// @[core.scala:54:14]\n output io_lsu_fp_stdata_bits_fflags_bits_uop_fp_val,\t// @[core.scala:54:14]\n output io_lsu_fp_stdata_bits_fflags_bits_uop_fp_single,\t// @[core.scala:54:14]\n output io_lsu_fp_stdata_bits_fflags_bits_uop_xcpt_pf_if,\t// @[core.scala:54:14]\n output io_lsu_fp_stdata_bits_fflags_bits_uop_xcpt_ae_if,\t// @[core.scala:54:14]\n output io_lsu_fp_stdata_bits_fflags_bits_uop_xcpt_ma_if,\t// @[core.scala:54:14]\n output io_lsu_fp_stdata_bits_fflags_bits_uop_bp_debug_if,\t// @[core.scala:54:14]\n output io_lsu_fp_stdata_bits_fflags_bits_uop_bp_xcpt_if,\t// @[core.scala:54:14]\n output [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_debug_fsrc,\t// @[core.scala:54:14]\n output [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_debug_tsrc,\t// @[core.scala:54:14]\n output [4:0] io_lsu_fp_stdata_bits_fflags_bits_flags,\t// @[core.scala:54:14]\n output io_lsu_commit_valids_0,\t// @[core.scala:54:14]\n output io_lsu_commit_valids_1,\t// @[core.scala:54:14]\n output io_lsu_commit_valids_2,\t// @[core.scala:54:14]\n output io_lsu_commit_arch_valids_0,\t// @[core.scala:54:14]\n output io_lsu_commit_arch_valids_1,\t// @[core.scala:54:14]\n output io_lsu_commit_arch_valids_2,\t// @[core.scala:54:14]\n output [6:0] io_lsu_commit_uops_0_uopc,\t// @[core.scala:54:14]\n output [31:0] io_lsu_commit_uops_0_inst,\t// @[core.scala:54:14]\n output [31:0] io_lsu_commit_uops_0_debug_inst,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_0_is_rvc,\t// @[core.scala:54:14]\n output [39:0] io_lsu_commit_uops_0_debug_pc,\t// @[core.scala:54:14]\n output [2:0] io_lsu_commit_uops_0_iq_type,\t// @[core.scala:54:14]\n output [9:0] io_lsu_commit_uops_0_fu_code,\t// @[core.scala:54:14]\n output [3:0] io_lsu_commit_uops_0_ctrl_br_type,\t// @[core.scala:54:14]\n output [1:0] io_lsu_commit_uops_0_ctrl_op1_sel,\t// @[core.scala:54:14]\n output [2:0] io_lsu_commit_uops_0_ctrl_op2_sel,\t// @[core.scala:54:14]\n output [2:0] io_lsu_commit_uops_0_ctrl_imm_sel,\t// @[core.scala:54:14]\n output [4:0] io_lsu_commit_uops_0_ctrl_op_fcn,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_0_ctrl_fcn_dw,\t// @[core.scala:54:14]\n output [2:0] io_lsu_commit_uops_0_ctrl_csr_cmd,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_0_ctrl_is_load,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_0_ctrl_is_sta,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_0_ctrl_is_std,\t// @[core.scala:54:14]\n output [1:0] io_lsu_commit_uops_0_iw_state,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_0_iw_p1_poisoned,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_0_iw_p2_poisoned,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_0_is_br,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_0_is_jalr,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_0_is_jal,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_0_is_sfb,\t// @[core.scala:54:14]\n output [15:0] io_lsu_commit_uops_0_br_mask,\t// @[core.scala:54:14]\n output [3:0] io_lsu_commit_uops_0_br_tag,\t// @[core.scala:54:14]\n output [4:0] io_lsu_commit_uops_0_ftq_idx,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_0_edge_inst,\t// @[core.scala:54:14]\n output [5:0] io_lsu_commit_uops_0_pc_lob,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_0_taken,\t// @[core.scala:54:14]\n output [19:0] io_lsu_commit_uops_0_imm_packed,\t// @[core.scala:54:14]\n output [11:0] io_lsu_commit_uops_0_csr_addr,\t// @[core.scala:54:14]\n output [6:0] io_lsu_commit_uops_0_rob_idx,\t// @[core.scala:54:14]\n output [4:0] io_lsu_commit_uops_0_ldq_idx,\t// @[core.scala:54:14]\n output [4:0] io_lsu_commit_uops_0_stq_idx,\t// @[core.scala:54:14]\n output [1:0] io_lsu_commit_uops_0_rxq_idx,\t// @[core.scala:54:14]\n output [6:0] io_lsu_commit_uops_0_pdst,\t// @[core.scala:54:14]\n output [6:0] io_lsu_commit_uops_0_prs1,\t// @[core.scala:54:14]\n output [6:0] io_lsu_commit_uops_0_prs2,\t// @[core.scala:54:14]\n output [6:0] io_lsu_commit_uops_0_prs3,\t// @[core.scala:54:14]\n output [4:0] io_lsu_commit_uops_0_ppred,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_0_prs1_busy,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_0_prs2_busy,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_0_prs3_busy,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_0_ppred_busy,\t// @[core.scala:54:14]\n output [6:0] io_lsu_commit_uops_0_stale_pdst,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_0_exception,\t// @[core.scala:54:14]\n output [63:0] io_lsu_commit_uops_0_exc_cause,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_0_bypassable,\t// @[core.scala:54:14]\n output [4:0] io_lsu_commit_uops_0_mem_cmd,\t// @[core.scala:54:14]\n output [1:0] io_lsu_commit_uops_0_mem_size,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_0_mem_signed,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_0_is_fence,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_0_is_fencei,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_0_is_amo,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_0_uses_ldq,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_0_uses_stq,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_0_is_sys_pc2epc,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_0_is_unique,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_0_flush_on_commit,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_0_ldst_is_rs1,\t// @[core.scala:54:14]\n output [5:0] io_lsu_commit_uops_0_ldst,\t// @[core.scala:54:14]\n output [5:0] io_lsu_commit_uops_0_lrs1,\t// @[core.scala:54:14]\n output [5:0] io_lsu_commit_uops_0_lrs2,\t// @[core.scala:54:14]\n output [5:0] io_lsu_commit_uops_0_lrs3,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_0_ldst_val,\t// @[core.scala:54:14]\n output [1:0] io_lsu_commit_uops_0_dst_rtype,\t// @[core.scala:54:14]\n output [1:0] io_lsu_commit_uops_0_lrs1_rtype,\t// @[core.scala:54:14]\n output [1:0] io_lsu_commit_uops_0_lrs2_rtype,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_0_frs3_en,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_0_fp_val,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_0_fp_single,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_0_xcpt_pf_if,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_0_xcpt_ae_if,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_0_xcpt_ma_if,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_0_bp_debug_if,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_0_bp_xcpt_if,\t// @[core.scala:54:14]\n output [1:0] io_lsu_commit_uops_0_debug_fsrc,\t// @[core.scala:54:14]\n output [1:0] io_lsu_commit_uops_0_debug_tsrc,\t// @[core.scala:54:14]\n output [6:0] io_lsu_commit_uops_1_uopc,\t// @[core.scala:54:14]\n output [31:0] io_lsu_commit_uops_1_inst,\t// @[core.scala:54:14]\n output [31:0] io_lsu_commit_uops_1_debug_inst,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_1_is_rvc,\t// @[core.scala:54:14]\n output [39:0] io_lsu_commit_uops_1_debug_pc,\t// @[core.scala:54:14]\n output [2:0] io_lsu_commit_uops_1_iq_type,\t// @[core.scala:54:14]\n output [9:0] io_lsu_commit_uops_1_fu_code,\t// @[core.scala:54:14]\n output [3:0] io_lsu_commit_uops_1_ctrl_br_type,\t// @[core.scala:54:14]\n output [1:0] io_lsu_commit_uops_1_ctrl_op1_sel,\t// @[core.scala:54:14]\n output [2:0] io_lsu_commit_uops_1_ctrl_op2_sel,\t// @[core.scala:54:14]\n output [2:0] io_lsu_commit_uops_1_ctrl_imm_sel,\t// @[core.scala:54:14]\n output [4:0] io_lsu_commit_uops_1_ctrl_op_fcn,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_1_ctrl_fcn_dw,\t// @[core.scala:54:14]\n output [2:0] io_lsu_commit_uops_1_ctrl_csr_cmd,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_1_ctrl_is_load,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_1_ctrl_is_sta,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_1_ctrl_is_std,\t// @[core.scala:54:14]\n output [1:0] io_lsu_commit_uops_1_iw_state,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_1_iw_p1_poisoned,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_1_iw_p2_poisoned,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_1_is_br,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_1_is_jalr,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_1_is_jal,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_1_is_sfb,\t// @[core.scala:54:14]\n output [15:0] io_lsu_commit_uops_1_br_mask,\t// @[core.scala:54:14]\n output [3:0] io_lsu_commit_uops_1_br_tag,\t// @[core.scala:54:14]\n output [4:0] io_lsu_commit_uops_1_ftq_idx,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_1_edge_inst,\t// @[core.scala:54:14]\n output [5:0] io_lsu_commit_uops_1_pc_lob,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_1_taken,\t// @[core.scala:54:14]\n output [19:0] io_lsu_commit_uops_1_imm_packed,\t// @[core.scala:54:14]\n output [11:0] io_lsu_commit_uops_1_csr_addr,\t// @[core.scala:54:14]\n output [6:0] io_lsu_commit_uops_1_rob_idx,\t// @[core.scala:54:14]\n output [4:0] io_lsu_commit_uops_1_ldq_idx,\t// @[core.scala:54:14]\n output [4:0] io_lsu_commit_uops_1_stq_idx,\t// @[core.scala:54:14]\n output [1:0] io_lsu_commit_uops_1_rxq_idx,\t// @[core.scala:54:14]\n output [6:0] io_lsu_commit_uops_1_pdst,\t// @[core.scala:54:14]\n output [6:0] io_lsu_commit_uops_1_prs1,\t// @[core.scala:54:14]\n output [6:0] io_lsu_commit_uops_1_prs2,\t// @[core.scala:54:14]\n output [6:0] io_lsu_commit_uops_1_prs3,\t// @[core.scala:54:14]\n output [4:0] io_lsu_commit_uops_1_ppred,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_1_prs1_busy,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_1_prs2_busy,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_1_prs3_busy,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_1_ppred_busy,\t// @[core.scala:54:14]\n output [6:0] io_lsu_commit_uops_1_stale_pdst,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_1_exception,\t// @[core.scala:54:14]\n output [63:0] io_lsu_commit_uops_1_exc_cause,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_1_bypassable,\t// @[core.scala:54:14]\n output [4:0] io_lsu_commit_uops_1_mem_cmd,\t// @[core.scala:54:14]\n output [1:0] io_lsu_commit_uops_1_mem_size,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_1_mem_signed,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_1_is_fence,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_1_is_fencei,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_1_is_amo,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_1_uses_ldq,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_1_uses_stq,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_1_is_sys_pc2epc,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_1_is_unique,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_1_flush_on_commit,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_1_ldst_is_rs1,\t// @[core.scala:54:14]\n output [5:0] io_lsu_commit_uops_1_ldst,\t// @[core.scala:54:14]\n output [5:0] io_lsu_commit_uops_1_lrs1,\t// @[core.scala:54:14]\n output [5:0] io_lsu_commit_uops_1_lrs2,\t// @[core.scala:54:14]\n output [5:0] io_lsu_commit_uops_1_lrs3,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_1_ldst_val,\t// @[core.scala:54:14]\n output [1:0] io_lsu_commit_uops_1_dst_rtype,\t// @[core.scala:54:14]\n output [1:0] io_lsu_commit_uops_1_lrs1_rtype,\t// @[core.scala:54:14]\n output [1:0] io_lsu_commit_uops_1_lrs2_rtype,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_1_frs3_en,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_1_fp_val,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_1_fp_single,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_1_xcpt_pf_if,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_1_xcpt_ae_if,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_1_xcpt_ma_if,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_1_bp_debug_if,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_1_bp_xcpt_if,\t// @[core.scala:54:14]\n output [1:0] io_lsu_commit_uops_1_debug_fsrc,\t// @[core.scala:54:14]\n output [1:0] io_lsu_commit_uops_1_debug_tsrc,\t// @[core.scala:54:14]\n output [6:0] io_lsu_commit_uops_2_uopc,\t// @[core.scala:54:14]\n output [31:0] io_lsu_commit_uops_2_inst,\t// @[core.scala:54:14]\n output [31:0] io_lsu_commit_uops_2_debug_inst,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_2_is_rvc,\t// @[core.scala:54:14]\n output [39:0] io_lsu_commit_uops_2_debug_pc,\t// @[core.scala:54:14]\n output [2:0] io_lsu_commit_uops_2_iq_type,\t// @[core.scala:54:14]\n output [9:0] io_lsu_commit_uops_2_fu_code,\t// @[core.scala:54:14]\n output [3:0] io_lsu_commit_uops_2_ctrl_br_type,\t// @[core.scala:54:14]\n output [1:0] io_lsu_commit_uops_2_ctrl_op1_sel,\t// @[core.scala:54:14]\n output [2:0] io_lsu_commit_uops_2_ctrl_op2_sel,\t// @[core.scala:54:14]\n output [2:0] io_lsu_commit_uops_2_ctrl_imm_sel,\t// @[core.scala:54:14]\n output [4:0] io_lsu_commit_uops_2_ctrl_op_fcn,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_2_ctrl_fcn_dw,\t// @[core.scala:54:14]\n output [2:0] io_lsu_commit_uops_2_ctrl_csr_cmd,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_2_ctrl_is_load,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_2_ctrl_is_sta,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_2_ctrl_is_std,\t// @[core.scala:54:14]\n output [1:0] io_lsu_commit_uops_2_iw_state,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_2_iw_p1_poisoned,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_2_iw_p2_poisoned,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_2_is_br,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_2_is_jalr,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_2_is_jal,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_2_is_sfb,\t// @[core.scala:54:14]\n output [15:0] io_lsu_commit_uops_2_br_mask,\t// @[core.scala:54:14]\n output [3:0] io_lsu_commit_uops_2_br_tag,\t// @[core.scala:54:14]\n output [4:0] io_lsu_commit_uops_2_ftq_idx,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_2_edge_inst,\t// @[core.scala:54:14]\n output [5:0] io_lsu_commit_uops_2_pc_lob,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_2_taken,\t// @[core.scala:54:14]\n output [19:0] io_lsu_commit_uops_2_imm_packed,\t// @[core.scala:54:14]\n output [11:0] io_lsu_commit_uops_2_csr_addr,\t// @[core.scala:54:14]\n output [6:0] io_lsu_commit_uops_2_rob_idx,\t// @[core.scala:54:14]\n output [4:0] io_lsu_commit_uops_2_ldq_idx,\t// @[core.scala:54:14]\n output [4:0] io_lsu_commit_uops_2_stq_idx,\t// @[core.scala:54:14]\n output [1:0] io_lsu_commit_uops_2_rxq_idx,\t// @[core.scala:54:14]\n output [6:0] io_lsu_commit_uops_2_pdst,\t// @[core.scala:54:14]\n output [6:0] io_lsu_commit_uops_2_prs1,\t// @[core.scala:54:14]\n output [6:0] io_lsu_commit_uops_2_prs2,\t// @[core.scala:54:14]\n output [6:0] io_lsu_commit_uops_2_prs3,\t// @[core.scala:54:14]\n output [4:0] io_lsu_commit_uops_2_ppred,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_2_prs1_busy,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_2_prs2_busy,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_2_prs3_busy,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_2_ppred_busy,\t// @[core.scala:54:14]\n output [6:0] io_lsu_commit_uops_2_stale_pdst,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_2_exception,\t// @[core.scala:54:14]\n output [63:0] io_lsu_commit_uops_2_exc_cause,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_2_bypassable,\t// @[core.scala:54:14]\n output [4:0] io_lsu_commit_uops_2_mem_cmd,\t// @[core.scala:54:14]\n output [1:0] io_lsu_commit_uops_2_mem_size,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_2_mem_signed,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_2_is_fence,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_2_is_fencei,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_2_is_amo,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_2_uses_ldq,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_2_uses_stq,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_2_is_sys_pc2epc,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_2_is_unique,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_2_flush_on_commit,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_2_ldst_is_rs1,\t// @[core.scala:54:14]\n output [5:0] io_lsu_commit_uops_2_ldst,\t// @[core.scala:54:14]\n output [5:0] io_lsu_commit_uops_2_lrs1,\t// @[core.scala:54:14]\n output [5:0] io_lsu_commit_uops_2_lrs2,\t// @[core.scala:54:14]\n output [5:0] io_lsu_commit_uops_2_lrs3,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_2_ldst_val,\t// @[core.scala:54:14]\n output [1:0] io_lsu_commit_uops_2_dst_rtype,\t// @[core.scala:54:14]\n output [1:0] io_lsu_commit_uops_2_lrs1_rtype,\t// @[core.scala:54:14]\n output [1:0] io_lsu_commit_uops_2_lrs2_rtype,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_2_frs3_en,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_2_fp_val,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_2_fp_single,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_2_xcpt_pf_if,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_2_xcpt_ae_if,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_2_xcpt_ma_if,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_2_bp_debug_if,\t// @[core.scala:54:14]\n output io_lsu_commit_uops_2_bp_xcpt_if,\t// @[core.scala:54:14]\n output [1:0] io_lsu_commit_uops_2_debug_fsrc,\t// @[core.scala:54:14]\n output [1:0] io_lsu_commit_uops_2_debug_tsrc,\t// @[core.scala:54:14]\n output io_lsu_commit_fflags_valid,\t// @[core.scala:54:14]\n output [4:0] io_lsu_commit_fflags_bits,\t// @[core.scala:54:14]\n output [31:0] io_lsu_commit_debug_insts_0,\t// @[core.scala:54:14]\n output [31:0] io_lsu_commit_debug_insts_1,\t// @[core.scala:54:14]\n output [31:0] io_lsu_commit_debug_insts_2,\t// @[core.scala:54:14]\n output io_lsu_commit_rbk_valids_0,\t// @[core.scala:54:14]\n output io_lsu_commit_rbk_valids_1,\t// @[core.scala:54:14]\n output io_lsu_commit_rbk_valids_2,\t// @[core.scala:54:14]\n output io_lsu_commit_rollback,\t// @[core.scala:54:14]\n output [63:0] io_lsu_commit_debug_wdata_0,\t// @[core.scala:54:14]\n output [63:0] io_lsu_commit_debug_wdata_1,\t// @[core.scala:54:14]\n output [63:0] io_lsu_commit_debug_wdata_2,\t// @[core.scala:54:14]\n output io_lsu_commit_load_at_rob_head,\t// @[core.scala:54:14]\n input io_lsu_clr_bsy_0_valid,\t// @[core.scala:54:14]\n input [6:0] io_lsu_clr_bsy_0_bits,\t// @[core.scala:54:14]\n input io_lsu_clr_bsy_1_valid,\t// @[core.scala:54:14]\n input [6:0] io_lsu_clr_bsy_1_bits,\t// @[core.scala:54:14]\n input [6:0] io_lsu_clr_unsafe_0_bits,\t// @[core.scala:54:14]\n output io_lsu_fence_dmem,\t// @[core.scala:54:14]\n input io_lsu_spec_ld_wakeup_0_valid,\t// @[core.scala:54:14]\n input [6:0] io_lsu_spec_ld_wakeup_0_bits,\t// @[core.scala:54:14]\n input io_lsu_ld_miss,\t// @[core.scala:54:14]\n output [15:0] io_lsu_brupdate_b1_resolve_mask,\t// @[core.scala:54:14]\n output [15:0] io_lsu_brupdate_b1_mispredict_mask,\t// @[core.scala:54:14]\n output [6:0] io_lsu_brupdate_b2_uop_uopc,\t// @[core.scala:54:14]\n output [31:0] io_lsu_brupdate_b2_uop_inst,\t// @[core.scala:54:14]\n output [31:0] io_lsu_brupdate_b2_uop_debug_inst,\t// @[core.scala:54:14]\n output io_lsu_brupdate_b2_uop_is_rvc,\t// @[core.scala:54:14]\n output [39:0] io_lsu_brupdate_b2_uop_debug_pc,\t// @[core.scala:54:14]\n output [2:0] io_lsu_brupdate_b2_uop_iq_type,\t// @[core.scala:54:14]\n output [9:0] io_lsu_brupdate_b2_uop_fu_code,\t// @[core.scala:54:14]\n output [3:0] io_lsu_brupdate_b2_uop_ctrl_br_type,\t// @[core.scala:54:14]\n output [1:0] io_lsu_brupdate_b2_uop_ctrl_op1_sel,\t// @[core.scala:54:14]\n output [2:0] io_lsu_brupdate_b2_uop_ctrl_op2_sel,\t// @[core.scala:54:14]\n output [2:0] io_lsu_brupdate_b2_uop_ctrl_imm_sel,\t// @[core.scala:54:14]\n output [4:0] io_lsu_brupdate_b2_uop_ctrl_op_fcn,\t// @[core.scala:54:14]\n output io_lsu_brupdate_b2_uop_ctrl_fcn_dw,\t// @[core.scala:54:14]\n output [2:0] io_lsu_brupdate_b2_uop_ctrl_csr_cmd,\t// @[core.scala:54:14]\n output io_lsu_brupdate_b2_uop_ctrl_is_load,\t// @[core.scala:54:14]\n output io_lsu_brupdate_b2_uop_ctrl_is_sta,\t// @[core.scala:54:14]\n output io_lsu_brupdate_b2_uop_ctrl_is_std,\t// @[core.scala:54:14]\n output [1:0] io_lsu_brupdate_b2_uop_iw_state,\t// @[core.scala:54:14]\n output io_lsu_brupdate_b2_uop_iw_p1_poisoned,\t// @[core.scala:54:14]\n output io_lsu_brupdate_b2_uop_iw_p2_poisoned,\t// @[core.scala:54:14]\n output io_lsu_brupdate_b2_uop_is_br,\t// @[core.scala:54:14]\n output io_lsu_brupdate_b2_uop_is_jalr,\t// @[core.scala:54:14]\n output io_lsu_brupdate_b2_uop_is_jal,\t// @[core.scala:54:14]\n output io_lsu_brupdate_b2_uop_is_sfb,\t// @[core.scala:54:14]\n output [15:0] io_lsu_brupdate_b2_uop_br_mask,\t// @[core.scala:54:14]\n output [3:0] io_lsu_brupdate_b2_uop_br_tag,\t// @[core.scala:54:14]\n output [4:0] io_lsu_brupdate_b2_uop_ftq_idx,\t// @[core.scala:54:14]\n output io_lsu_brupdate_b2_uop_edge_inst,\t// @[core.scala:54:14]\n output [5:0] io_lsu_brupdate_b2_uop_pc_lob,\t// @[core.scala:54:14]\n output io_lsu_brupdate_b2_uop_taken,\t// @[core.scala:54:14]\n output [19:0] io_lsu_brupdate_b2_uop_imm_packed,\t// @[core.scala:54:14]\n output [11:0] io_lsu_brupdate_b2_uop_csr_addr,\t// @[core.scala:54:14]\n output [6:0] io_lsu_brupdate_b2_uop_rob_idx,\t// @[core.scala:54:14]\n output [4:0] io_lsu_brupdate_b2_uop_ldq_idx,\t// @[core.scala:54:14]\n output [4:0] io_lsu_brupdate_b2_uop_stq_idx,\t// @[core.scala:54:14]\n output [1:0] io_lsu_brupdate_b2_uop_rxq_idx,\t// @[core.scala:54:14]\n output [6:0] io_lsu_brupdate_b2_uop_pdst,\t// @[core.scala:54:14]\n output [6:0] io_lsu_brupdate_b2_uop_prs1,\t// @[core.scala:54:14]\n output [6:0] io_lsu_brupdate_b2_uop_prs2,\t// @[core.scala:54:14]\n output [6:0] io_lsu_brupdate_b2_uop_prs3,\t// @[core.scala:54:14]\n output [4:0] io_lsu_brupdate_b2_uop_ppred,\t// @[core.scala:54:14]\n output io_lsu_brupdate_b2_uop_prs1_busy,\t// @[core.scala:54:14]\n output io_lsu_brupdate_b2_uop_prs2_busy,\t// @[core.scala:54:14]\n output io_lsu_brupdate_b2_uop_prs3_busy,\t// @[core.scala:54:14]\n output io_lsu_brupdate_b2_uop_ppred_busy,\t// @[core.scala:54:14]\n output [6:0] io_lsu_brupdate_b2_uop_stale_pdst,\t// @[core.scala:54:14]\n output io_lsu_brupdate_b2_uop_exception,\t// @[core.scala:54:14]\n output [63:0] io_lsu_brupdate_b2_uop_exc_cause,\t// @[core.scala:54:14]\n output io_lsu_brupdate_b2_uop_bypassable,\t// @[core.scala:54:14]\n output [4:0] io_lsu_brupdate_b2_uop_mem_cmd,\t// @[core.scala:54:14]\n output [1:0] io_lsu_brupdate_b2_uop_mem_size,\t// @[core.scala:54:14]\n output io_lsu_brupdate_b2_uop_mem_signed,\t// @[core.scala:54:14]\n output io_lsu_brupdate_b2_uop_is_fence,\t// @[core.scala:54:14]\n output io_lsu_brupdate_b2_uop_is_fencei,\t// @[core.scala:54:14]\n output io_lsu_brupdate_b2_uop_is_amo,\t// @[core.scala:54:14]\n output io_lsu_brupdate_b2_uop_uses_ldq,\t// @[core.scala:54:14]\n output io_lsu_brupdate_b2_uop_uses_stq,\t// @[core.scala:54:14]\n output io_lsu_brupdate_b2_uop_is_sys_pc2epc,\t// @[core.scala:54:14]\n output io_lsu_brupdate_b2_uop_is_unique,\t// @[core.scala:54:14]\n output io_lsu_brupdate_b2_uop_flush_on_commit,\t// @[core.scala:54:14]\n output io_lsu_brupdate_b2_uop_ldst_is_rs1,\t// @[core.scala:54:14]\n output [5:0] io_lsu_brupdate_b2_uop_ldst,\t// @[core.scala:54:14]\n output [5:0] io_lsu_brupdate_b2_uop_lrs1,\t// @[core.scala:54:14]\n output [5:0] io_lsu_brupdate_b2_uop_lrs2,\t// @[core.scala:54:14]\n output [5:0] io_lsu_brupdate_b2_uop_lrs3,\t// @[core.scala:54:14]\n output io_lsu_brupdate_b2_uop_ldst_val,\t// @[core.scala:54:14]\n output [1:0] io_lsu_brupdate_b2_uop_dst_rtype,\t// @[core.scala:54:14]\n output [1:0] io_lsu_brupdate_b2_uop_lrs1_rtype,\t// @[core.scala:54:14]\n output [1:0] io_lsu_brupdate_b2_uop_lrs2_rtype,\t// @[core.scala:54:14]\n output io_lsu_brupdate_b2_uop_frs3_en,\t// @[core.scala:54:14]\n output io_lsu_brupdate_b2_uop_fp_val,\t// @[core.scala:54:14]\n output io_lsu_brupdate_b2_uop_fp_single,\t// @[core.scala:54:14]\n output io_lsu_brupdate_b2_uop_xcpt_pf_if,\t// @[core.scala:54:14]\n output io_lsu_brupdate_b2_uop_xcpt_ae_if,\t// @[core.scala:54:14]\n output io_lsu_brupdate_b2_uop_xcpt_ma_if,\t// @[core.scala:54:14]\n output io_lsu_brupdate_b2_uop_bp_debug_if,\t// @[core.scala:54:14]\n output io_lsu_brupdate_b2_uop_bp_xcpt_if,\t// @[core.scala:54:14]\n output [1:0] io_lsu_brupdate_b2_uop_debug_fsrc,\t// @[core.scala:54:14]\n output [1:0] io_lsu_brupdate_b2_uop_debug_tsrc,\t// @[core.scala:54:14]\n output io_lsu_brupdate_b2_valid,\t// @[core.scala:54:14]\n output io_lsu_brupdate_b2_mispredict,\t// @[core.scala:54:14]\n output io_lsu_brupdate_b2_taken,\t// @[core.scala:54:14]\n output [2:0] io_lsu_brupdate_b2_cfi_type,\t// @[core.scala:54:14]\n output [1:0] io_lsu_brupdate_b2_pc_sel,\t// @[core.scala:54:14]\n output [39:0] io_lsu_brupdate_b2_jalr_target,\t// @[core.scala:54:14]\n output [20:0] io_lsu_brupdate_b2_target_offset,\t// @[core.scala:54:14]\n output [6:0] io_lsu_rob_pnr_idx,\t// @[core.scala:54:14]\n output [6:0] io_lsu_rob_head_idx,\t// @[core.scala:54:14]\n output io_lsu_exception,\t// @[core.scala:54:14]\n input io_lsu_fencei_rdy,\t// @[core.scala:54:14]\n input io_lsu_lxcpt_valid,\t// @[core.scala:54:14]\n input [6:0] io_lsu_lxcpt_bits_uop_uopc,\t// @[core.scala:54:14]\n input [31:0] io_lsu_lxcpt_bits_uop_inst,\t// @[core.scala:54:14]\n input [31:0] io_lsu_lxcpt_bits_uop_debug_inst,\t// @[core.scala:54:14]\n input io_lsu_lxcpt_bits_uop_is_rvc,\t// @[core.scala:54:14]\n input [39:0] io_lsu_lxcpt_bits_uop_debug_pc,\t// @[core.scala:54:14]\n input [2:0] io_lsu_lxcpt_bits_uop_iq_type,\t// @[core.scala:54:14]\n input [9:0] io_lsu_lxcpt_bits_uop_fu_code,\t// @[core.scala:54:14]\n input [3:0] io_lsu_lxcpt_bits_uop_ctrl_br_type,\t// @[core.scala:54:14]\n input [1:0] io_lsu_lxcpt_bits_uop_ctrl_op1_sel,\t// @[core.scala:54:14]\n input [2:0] io_lsu_lxcpt_bits_uop_ctrl_op2_sel,\t// @[core.scala:54:14]\n input [2:0] io_lsu_lxcpt_bits_uop_ctrl_imm_sel,\t// @[core.scala:54:14]\n input [4:0] io_lsu_lxcpt_bits_uop_ctrl_op_fcn,\t// @[core.scala:54:14]\n input io_lsu_lxcpt_bits_uop_ctrl_fcn_dw,\t// @[core.scala:54:14]\n input [2:0] io_lsu_lxcpt_bits_uop_ctrl_csr_cmd,\t// @[core.scala:54:14]\n input io_lsu_lxcpt_bits_uop_ctrl_is_load,\t// @[core.scala:54:14]\n input io_lsu_lxcpt_bits_uop_ctrl_is_sta,\t// @[core.scala:54:14]\n input io_lsu_lxcpt_bits_uop_ctrl_is_std,\t// @[core.scala:54:14]\n input [1:0] io_lsu_lxcpt_bits_uop_iw_state,\t// @[core.scala:54:14]\n input io_lsu_lxcpt_bits_uop_iw_p1_poisoned,\t// @[core.scala:54:14]\n input io_lsu_lxcpt_bits_uop_iw_p2_poisoned,\t// @[core.scala:54:14]\n input io_lsu_lxcpt_bits_uop_is_br,\t// @[core.scala:54:14]\n input io_lsu_lxcpt_bits_uop_is_jalr,\t// @[core.scala:54:14]\n input io_lsu_lxcpt_bits_uop_is_jal,\t// @[core.scala:54:14]\n input io_lsu_lxcpt_bits_uop_is_sfb,\t// @[core.scala:54:14]\n input [15:0] io_lsu_lxcpt_bits_uop_br_mask,\t// @[core.scala:54:14]\n input [3:0] io_lsu_lxcpt_bits_uop_br_tag,\t// @[core.scala:54:14]\n input [4:0] io_lsu_lxcpt_bits_uop_ftq_idx,\t// @[core.scala:54:14]\n input io_lsu_lxcpt_bits_uop_edge_inst,\t// @[core.scala:54:14]\n input [5:0] io_lsu_lxcpt_bits_uop_pc_lob,\t// @[core.scala:54:14]\n input io_lsu_lxcpt_bits_uop_taken,\t// @[core.scala:54:14]\n input [19:0] io_lsu_lxcpt_bits_uop_imm_packed,\t// @[core.scala:54:14]\n input [11:0] io_lsu_lxcpt_bits_uop_csr_addr,\t// @[core.scala:54:14]\n input [6:0] io_lsu_lxcpt_bits_uop_rob_idx,\t// @[core.scala:54:14]\n input [4:0] io_lsu_lxcpt_bits_uop_ldq_idx,\t// @[core.scala:54:14]\n input [4:0] io_lsu_lxcpt_bits_uop_stq_idx,\t// @[core.scala:54:14]\n input [1:0] io_lsu_lxcpt_bits_uop_rxq_idx,\t// @[core.scala:54:14]\n input [6:0] io_lsu_lxcpt_bits_uop_pdst,\t// @[core.scala:54:14]\n input [6:0] io_lsu_lxcpt_bits_uop_prs1,\t// @[core.scala:54:14]\n input [6:0] io_lsu_lxcpt_bits_uop_prs2,\t// @[core.scala:54:14]\n input [6:0] io_lsu_lxcpt_bits_uop_prs3,\t// @[core.scala:54:14]\n input [4:0] io_lsu_lxcpt_bits_uop_ppred,\t// @[core.scala:54:14]\n input io_lsu_lxcpt_bits_uop_prs1_busy,\t// @[core.scala:54:14]\n input io_lsu_lxcpt_bits_uop_prs2_busy,\t// @[core.scala:54:14]\n input io_lsu_lxcpt_bits_uop_prs3_busy,\t// @[core.scala:54:14]\n input io_lsu_lxcpt_bits_uop_ppred_busy,\t// @[core.scala:54:14]\n input [6:0] io_lsu_lxcpt_bits_uop_stale_pdst,\t// @[core.scala:54:14]\n input io_lsu_lxcpt_bits_uop_exception,\t// @[core.scala:54:14]\n input [63:0] io_lsu_lxcpt_bits_uop_exc_cause,\t// @[core.scala:54:14]\n input io_lsu_lxcpt_bits_uop_bypassable,\t// @[core.scala:54:14]\n input [4:0] io_lsu_lxcpt_bits_uop_mem_cmd,\t// @[core.scala:54:14]\n input [1:0] io_lsu_lxcpt_bits_uop_mem_size,\t// @[core.scala:54:14]\n input io_lsu_lxcpt_bits_uop_mem_signed,\t// @[core.scala:54:14]\n input io_lsu_lxcpt_bits_uop_is_fence,\t// @[core.scala:54:14]\n input io_lsu_lxcpt_bits_uop_is_fencei,\t// @[core.scala:54:14]\n input io_lsu_lxcpt_bits_uop_is_amo,\t// @[core.scala:54:14]\n input io_lsu_lxcpt_bits_uop_uses_ldq,\t// @[core.scala:54:14]\n input io_lsu_lxcpt_bits_uop_uses_stq,\t// @[core.scala:54:14]\n input io_lsu_lxcpt_bits_uop_is_sys_pc2epc,\t// @[core.scala:54:14]\n input io_lsu_lxcpt_bits_uop_is_unique,\t// @[core.scala:54:14]\n input io_lsu_lxcpt_bits_uop_flush_on_commit,\t// @[core.scala:54:14]\n input io_lsu_lxcpt_bits_uop_ldst_is_rs1,\t// @[core.scala:54:14]\n input [5:0] io_lsu_lxcpt_bits_uop_ldst,\t// @[core.scala:54:14]\n input [5:0] io_lsu_lxcpt_bits_uop_lrs1,\t// @[core.scala:54:14]\n input [5:0] io_lsu_lxcpt_bits_uop_lrs2,\t// @[core.scala:54:14]\n input [5:0] io_lsu_lxcpt_bits_uop_lrs3,\t// @[core.scala:54:14]\n input io_lsu_lxcpt_bits_uop_ldst_val,\t// @[core.scala:54:14]\n input [1:0] io_lsu_lxcpt_bits_uop_dst_rtype,\t// @[core.scala:54:14]\n input [1:0] io_lsu_lxcpt_bits_uop_lrs1_rtype,\t// @[core.scala:54:14]\n input [1:0] io_lsu_lxcpt_bits_uop_lrs2_rtype,\t// @[core.scala:54:14]\n input io_lsu_lxcpt_bits_uop_frs3_en,\t// @[core.scala:54:14]\n input io_lsu_lxcpt_bits_uop_fp_val,\t// @[core.scala:54:14]\n input io_lsu_lxcpt_bits_uop_fp_single,\t// @[core.scala:54:14]\n input io_lsu_lxcpt_bits_uop_xcpt_pf_if,\t// @[core.scala:54:14]\n input io_lsu_lxcpt_bits_uop_xcpt_ae_if,\t// @[core.scala:54:14]\n input io_lsu_lxcpt_bits_uop_xcpt_ma_if,\t// @[core.scala:54:14]\n input io_lsu_lxcpt_bits_uop_bp_debug_if,\t// @[core.scala:54:14]\n input io_lsu_lxcpt_bits_uop_bp_xcpt_if,\t// @[core.scala:54:14]\n input [1:0] io_lsu_lxcpt_bits_uop_debug_fsrc,\t// @[core.scala:54:14]\n input [1:0] io_lsu_lxcpt_bits_uop_debug_tsrc,\t// @[core.scala:54:14]\n input [4:0] io_lsu_lxcpt_bits_cause,\t// @[core.scala:54:14]\n input [39:0] io_lsu_lxcpt_bits_badvaddr,\t// @[core.scala:54:14]\n output [63:0] io_lsu_tsc_reg,\t// @[core.scala:54:14]\n input io_lsu_perf_acquire,\t// @[core.scala:54:14]\n input io_lsu_perf_release,\t// @[core.scala:54:14]\n input io_lsu_perf_tlbMiss,\t// @[core.scala:54:14]\n input io_ptw_tlb_req_ready,\t// @[core.scala:54:14]\n input io_ptw_tlb_resp_valid,\t// @[core.scala:54:14]\n input io_ptw_tlb_resp_bits_ae_ptw,\t// @[core.scala:54:14]\n input io_ptw_tlb_resp_bits_ae_final,\t// @[core.scala:54:14]\n input io_ptw_tlb_resp_bits_pf,\t// @[core.scala:54:14]\n input io_ptw_tlb_resp_bits_gf,\t// @[core.scala:54:14]\n input io_ptw_tlb_resp_bits_hr,\t// @[core.scala:54:14]\n input io_ptw_tlb_resp_bits_hw,\t// @[core.scala:54:14]\n input io_ptw_tlb_resp_bits_hx,\t// @[core.scala:54:14]\n input [9:0] io_ptw_tlb_resp_bits_pte_reserved_for_future,\t// @[core.scala:54:14]\n input [43:0] io_ptw_tlb_resp_bits_pte_ppn,\t// @[core.scala:54:14]\n input [1:0] io_ptw_tlb_resp_bits_pte_reserved_for_software,\t// @[core.scala:54:14]\n input io_ptw_tlb_resp_bits_pte_d,\t// @[core.scala:54:14]\n input io_ptw_tlb_resp_bits_pte_a,\t// @[core.scala:54:14]\n input io_ptw_tlb_resp_bits_pte_g,\t// @[core.scala:54:14]\n input io_ptw_tlb_resp_bits_pte_u,\t// @[core.scala:54:14]\n input io_ptw_tlb_resp_bits_pte_x,\t// @[core.scala:54:14]\n input io_ptw_tlb_resp_bits_pte_w,\t// @[core.scala:54:14]\n input io_ptw_tlb_resp_bits_pte_r,\t// @[core.scala:54:14]\n input io_ptw_tlb_resp_bits_pte_v,\t// @[core.scala:54:14]\n input [1:0] io_ptw_tlb_resp_bits_level,\t// @[core.scala:54:14]\n input io_ptw_tlb_resp_bits_homogeneous,\t// @[core.scala:54:14]\n input io_ptw_tlb_resp_bits_gpa_valid,\t// @[core.scala:54:14]\n input [38:0] io_ptw_tlb_resp_bits_gpa_bits,\t// @[core.scala:54:14]\n input io_ptw_tlb_resp_bits_gpa_is_pte,\t// @[core.scala:54:14]\n input [3:0] io_ptw_tlb_ptbr_mode,\t// @[core.scala:54:14]\n input [43:0] io_ptw_tlb_ptbr_ppn,\t// @[core.scala:54:14]\n input io_ptw_tlb_status_debug,\t// @[core.scala:54:14]\n input io_ptw_tlb_status_cease,\t// @[core.scala:54:14]\n input io_ptw_tlb_status_wfi,\t// @[core.scala:54:14]\n input [1:0] io_ptw_tlb_status_dprv,\t// @[core.scala:54:14]\n input io_ptw_tlb_status_dv,\t// @[core.scala:54:14]\n input [1:0] io_ptw_tlb_status_prv,\t// @[core.scala:54:14]\n input io_ptw_tlb_status_v,\t// @[core.scala:54:14]\n input io_ptw_tlb_status_sd,\t// @[core.scala:54:14]\n input io_ptw_tlb_status_mpv,\t// @[core.scala:54:14]\n input io_ptw_tlb_status_gva,\t// @[core.scala:54:14]\n input io_ptw_tlb_status_tsr,\t// @[core.scala:54:14]\n input io_ptw_tlb_status_tw,\t// @[core.scala:54:14]\n input io_ptw_tlb_status_tvm,\t// @[core.scala:54:14]\n input io_ptw_tlb_status_mxr,\t// @[core.scala:54:14]\n input io_ptw_tlb_status_sum,\t// @[core.scala:54:14]\n input io_ptw_tlb_status_mprv,\t// @[core.scala:54:14]\n input [1:0] io_ptw_tlb_status_fs,\t// @[core.scala:54:14]\n input [1:0] io_ptw_tlb_status_mpp,\t// @[core.scala:54:14]\n input io_ptw_tlb_status_spp,\t// @[core.scala:54:14]\n input io_ptw_tlb_status_mpie,\t// @[core.scala:54:14]\n input io_ptw_tlb_status_spie,\t// @[core.scala:54:14]\n input io_ptw_tlb_status_mie,\t// @[core.scala:54:14]\n input io_ptw_tlb_status_sie,\t// @[core.scala:54:14]\n input io_ptw_tlb_pmp_0_cfg_l,\t// @[core.scala:54:14]\n input [1:0] io_ptw_tlb_pmp_0_cfg_a,\t// @[core.scala:54:14]\n input io_ptw_tlb_pmp_0_cfg_x,\t// @[core.scala:54:14]\n input io_ptw_tlb_pmp_0_cfg_w,\t// @[core.scala:54:14]\n input io_ptw_tlb_pmp_0_cfg_r,\t// @[core.scala:54:14]\n input [29:0] io_ptw_tlb_pmp_0_addr,\t// @[core.scala:54:14]\n input [31:0] io_ptw_tlb_pmp_0_mask,\t// @[core.scala:54:14]\n input io_ptw_tlb_pmp_1_cfg_l,\t// @[core.scala:54:14]\n input [1:0] io_ptw_tlb_pmp_1_cfg_a,\t// @[core.scala:54:14]\n input io_ptw_tlb_pmp_1_cfg_x,\t// @[core.scala:54:14]\n input io_ptw_tlb_pmp_1_cfg_w,\t// @[core.scala:54:14]\n input io_ptw_tlb_pmp_1_cfg_r,\t// @[core.scala:54:14]\n input [29:0] io_ptw_tlb_pmp_1_addr,\t// @[core.scala:54:14]\n input [31:0] io_ptw_tlb_pmp_1_mask,\t// @[core.scala:54:14]\n input io_ptw_tlb_pmp_2_cfg_l,\t// @[core.scala:54:14]\n input [1:0] io_ptw_tlb_pmp_2_cfg_a,\t// @[core.scala:54:14]\n input io_ptw_tlb_pmp_2_cfg_x,\t// @[core.scala:54:14]\n input io_ptw_tlb_pmp_2_cfg_w,\t// @[core.scala:54:14]\n input io_ptw_tlb_pmp_2_cfg_r,\t// @[core.scala:54:14]\n input [29:0] io_ptw_tlb_pmp_2_addr,\t// @[core.scala:54:14]\n input [31:0] io_ptw_tlb_pmp_2_mask,\t// @[core.scala:54:14]\n input io_ptw_tlb_pmp_3_cfg_l,\t// @[core.scala:54:14]\n input [1:0] io_ptw_tlb_pmp_3_cfg_a,\t// @[core.scala:54:14]\n input io_ptw_tlb_pmp_3_cfg_x,\t// @[core.scala:54:14]\n input io_ptw_tlb_pmp_3_cfg_w,\t// @[core.scala:54:14]\n input io_ptw_tlb_pmp_3_cfg_r,\t// @[core.scala:54:14]\n input [29:0] io_ptw_tlb_pmp_3_addr,\t// @[core.scala:54:14]\n input [31:0] io_ptw_tlb_pmp_3_mask,\t// @[core.scala:54:14]\n input io_ptw_tlb_pmp_4_cfg_l,\t// @[core.scala:54:14]\n input [1:0] io_ptw_tlb_pmp_4_cfg_a,\t// @[core.scala:54:14]\n input io_ptw_tlb_pmp_4_cfg_x,\t// @[core.scala:54:14]\n input io_ptw_tlb_pmp_4_cfg_w,\t// @[core.scala:54:14]\n input io_ptw_tlb_pmp_4_cfg_r,\t// @[core.scala:54:14]\n input [29:0] io_ptw_tlb_pmp_4_addr,\t// @[core.scala:54:14]\n input [31:0] io_ptw_tlb_pmp_4_mask,\t// @[core.scala:54:14]\n input io_ptw_tlb_pmp_5_cfg_l,\t// @[core.scala:54:14]\n input [1:0] io_ptw_tlb_pmp_5_cfg_a,\t// @[core.scala:54:14]\n input io_ptw_tlb_pmp_5_cfg_x,\t// @[core.scala:54:14]\n input io_ptw_tlb_pmp_5_cfg_w,\t// @[core.scala:54:14]\n input io_ptw_tlb_pmp_5_cfg_r,\t// @[core.scala:54:14]\n input [29:0] io_ptw_tlb_pmp_5_addr,\t// @[core.scala:54:14]\n input [31:0] io_ptw_tlb_pmp_5_mask,\t// @[core.scala:54:14]\n input io_ptw_tlb_pmp_6_cfg_l,\t// @[core.scala:54:14]\n input [1:0] io_ptw_tlb_pmp_6_cfg_a,\t// @[core.scala:54:14]\n input io_ptw_tlb_pmp_6_cfg_x,\t// @[core.scala:54:14]\n input io_ptw_tlb_pmp_6_cfg_w,\t// @[core.scala:54:14]\n input io_ptw_tlb_pmp_6_cfg_r,\t// @[core.scala:54:14]\n input [29:0] io_ptw_tlb_pmp_6_addr,\t// @[core.scala:54:14]\n input [31:0] io_ptw_tlb_pmp_6_mask,\t// @[core.scala:54:14]\n input io_ptw_tlb_pmp_7_cfg_l,\t// @[core.scala:54:14]\n input [1:0] io_ptw_tlb_pmp_7_cfg_a,\t// @[core.scala:54:14]\n input io_ptw_tlb_pmp_7_cfg_x,\t// @[core.scala:54:14]\n input io_ptw_tlb_pmp_7_cfg_w,\t// @[core.scala:54:14]\n input io_ptw_tlb_pmp_7_cfg_r,\t// @[core.scala:54:14]\n input [29:0] io_ptw_tlb_pmp_7_addr,\t// @[core.scala:54:14]\n input [31:0] io_ptw_tlb_pmp_7_mask,\t// @[core.scala:54:14]\n output [63:0] io_trace_time,\t// @[core.scala:54:14]\n output io_trace_custom_rob_empty\t// @[core.scala:54:14]\n);\n\n wire [1:0] iss_uops_3_debug_tsrc;\t// @[core.scala:173:24]\n wire [1:0] iss_uops_3_debug_fsrc;\t// @[core.scala:173:24]\n wire iss_uops_3_bp_xcpt_if;\t// @[core.scala:173:24]\n wire iss_uops_3_bp_debug_if;\t// @[core.scala:173:24]\n wire iss_uops_3_xcpt_ma_if;\t// @[core.scala:173:24]\n wire iss_uops_3_xcpt_ae_if;\t// @[core.scala:173:24]\n wire iss_uops_3_xcpt_pf_if;\t// @[core.scala:173:24]\n wire iss_uops_3_fp_single;\t// @[core.scala:173:24]\n wire iss_uops_3_fp_val;\t// @[core.scala:173:24]\n wire iss_uops_3_frs3_en;\t// @[core.scala:173:24]\n wire [1:0] iss_uops_3_lrs2_rtype;\t// @[core.scala:173:24]\n wire [1:0] iss_uops_3_lrs1_rtype;\t// @[core.scala:173:24]\n wire [1:0] iss_uops_3_dst_rtype;\t// @[core.scala:173:24]\n wire iss_uops_3_ldst_val;\t// @[core.scala:173:24]\n wire [5:0] iss_uops_3_lrs3;\t// @[core.scala:173:24]\n wire [5:0] iss_uops_3_lrs2;\t// @[core.scala:173:24]\n wire [5:0] iss_uops_3_lrs1;\t// @[core.scala:173:24]\n wire [5:0] iss_uops_3_ldst;\t// @[core.scala:173:24]\n wire iss_uops_3_ldst_is_rs1;\t// @[core.scala:173:24]\n wire iss_uops_3_flush_on_commit;\t// @[core.scala:173:24]\n wire iss_uops_3_is_unique;\t// @[core.scala:173:24]\n wire iss_uops_3_is_sys_pc2epc;\t// @[core.scala:173:24]\n wire iss_uops_3_uses_stq;\t// @[core.scala:173:24]\n wire iss_uops_3_uses_ldq;\t// @[core.scala:173:24]\n wire iss_uops_3_is_amo;\t// @[core.scala:173:24]\n wire iss_uops_3_is_fencei;\t// @[core.scala:173:24]\n wire iss_uops_3_is_fence;\t// @[core.scala:173:24]\n wire iss_uops_3_mem_signed;\t// @[core.scala:173:24]\n wire [1:0] iss_uops_3_mem_size;\t// @[core.scala:173:24]\n wire [4:0] iss_uops_3_mem_cmd;\t// @[core.scala:173:24]\n wire iss_uops_3_bypassable;\t// @[core.scala:173:24]\n wire [63:0] iss_uops_3_exc_cause;\t// @[core.scala:173:24]\n wire iss_uops_3_exception;\t// @[core.scala:173:24]\n wire [6:0] iss_uops_3_stale_pdst;\t// @[core.scala:173:24]\n wire iss_uops_3_ppred_busy;\t// @[core.scala:173:24]\n wire iss_uops_3_prs3_busy;\t// @[core.scala:173:24]\n wire iss_uops_3_prs2_busy;\t// @[core.scala:173:24]\n wire iss_uops_3_prs1_busy;\t// @[core.scala:173:24]\n wire [4:0] iss_uops_3_ppred;\t// @[core.scala:173:24]\n wire [6:0] iss_uops_3_prs3;\t// @[core.scala:173:24]\n wire [6:0] iss_uops_3_prs2;\t// @[core.scala:173:24]\n wire [6:0] iss_uops_3_prs1;\t// @[core.scala:173:24]\n wire [6:0] iss_uops_3_pdst;\t// @[core.scala:173:24]\n wire [1:0] iss_uops_3_rxq_idx;\t// @[core.scala:173:24]\n wire [4:0] iss_uops_3_stq_idx;\t// @[core.scala:173:24]\n wire [4:0] iss_uops_3_ldq_idx;\t// @[core.scala:173:24]\n wire [6:0] iss_uops_3_rob_idx;\t// @[core.scala:173:24]\n wire [11:0] iss_uops_3_csr_addr;\t// @[core.scala:173:24]\n wire [19:0] iss_uops_3_imm_packed;\t// @[core.scala:173:24]\n wire iss_uops_3_taken;\t// @[core.scala:173:24]\n wire [5:0] iss_uops_3_pc_lob;\t// @[core.scala:173:24]\n wire iss_uops_3_edge_inst;\t// @[core.scala:173:24]\n wire [4:0] iss_uops_3_ftq_idx;\t// @[core.scala:173:24]\n wire [3:0] iss_uops_3_br_tag;\t// @[core.scala:173:24]\n wire [15:0] iss_uops_3_br_mask;\t// @[core.scala:173:24]\n wire iss_uops_3_is_sfb;\t// @[core.scala:173:24]\n wire iss_uops_3_is_jal;\t// @[core.scala:173:24]\n wire iss_uops_3_is_jalr;\t// @[core.scala:173:24]\n wire iss_uops_3_is_br;\t// @[core.scala:173:24]\n wire iss_uops_3_iw_p2_poisoned;\t// @[core.scala:173:24]\n wire iss_uops_3_iw_p1_poisoned;\t// @[core.scala:173:24]\n wire [1:0] iss_uops_3_iw_state;\t// @[core.scala:173:24]\n wire [9:0] iss_uops_3_fu_code;\t// @[core.scala:173:24]\n wire [2:0] iss_uops_3_iq_type;\t// @[core.scala:173:24]\n wire [39:0] iss_uops_3_debug_pc;\t// @[core.scala:173:24]\n wire iss_uops_3_is_rvc;\t// @[core.scala:173:24]\n wire [31:0] iss_uops_3_debug_inst;\t// @[core.scala:173:24]\n wire [31:0] iss_uops_3_inst;\t// @[core.scala:173:24]\n wire [6:0] iss_uops_3_uopc;\t// @[core.scala:173:24]\n wire iss_uops_3_ctrl_is_std;\t// @[core.scala:173:24]\n wire iss_uops_3_ctrl_is_sta;\t// @[core.scala:173:24]\n wire iss_uops_3_ctrl_is_load;\t// @[core.scala:173:24]\n wire [2:0] iss_uops_3_ctrl_csr_cmd;\t// @[core.scala:173:24]\n wire iss_uops_3_ctrl_fcn_dw;\t// @[core.scala:173:24]\n wire [4:0] iss_uops_3_ctrl_op_fcn;\t// @[core.scala:173:24]\n wire [2:0] iss_uops_3_ctrl_imm_sel;\t// @[core.scala:173:24]\n wire [2:0] iss_uops_3_ctrl_op2_sel;\t// @[core.scala:173:24]\n wire [1:0] iss_uops_3_ctrl_op1_sel;\t// @[core.scala:173:24]\n wire [3:0] iss_uops_3_ctrl_br_type;\t// @[core.scala:173:24]\n wire [1:0] iss_uops_2_debug_tsrc;\t// @[core.scala:173:24]\n wire [1:0] iss_uops_2_debug_fsrc;\t// @[core.scala:173:24]\n wire iss_uops_2_bp_xcpt_if;\t// @[core.scala:173:24]\n wire iss_uops_2_bp_debug_if;\t// @[core.scala:173:24]\n wire iss_uops_2_xcpt_ma_if;\t// @[core.scala:173:24]\n wire iss_uops_2_xcpt_ae_if;\t// @[core.scala:173:24]\n wire iss_uops_2_xcpt_pf_if;\t// @[core.scala:173:24]\n wire iss_uops_2_fp_single;\t// @[core.scala:173:24]\n wire iss_uops_2_fp_val;\t// @[core.scala:173:24]\n wire iss_uops_2_frs3_en;\t// @[core.scala:173:24]\n wire [1:0] iss_uops_2_lrs2_rtype;\t// @[core.scala:173:24]\n wire [1:0] iss_uops_2_lrs1_rtype;\t// @[core.scala:173:24]\n wire [1:0] iss_uops_2_dst_rtype;\t// @[core.scala:173:24]\n wire iss_uops_2_ldst_val;\t// @[core.scala:173:24]\n wire [5:0] iss_uops_2_lrs3;\t// @[core.scala:173:24]\n wire [5:0] iss_uops_2_lrs2;\t// @[core.scala:173:24]\n wire [5:0] iss_uops_2_lrs1;\t// @[core.scala:173:24]\n wire [5:0] iss_uops_2_ldst;\t// @[core.scala:173:24]\n wire iss_uops_2_ldst_is_rs1;\t// @[core.scala:173:24]\n wire iss_uops_2_flush_on_commit;\t// @[core.scala:173:24]\n wire iss_uops_2_is_unique;\t// @[core.scala:173:24]\n wire iss_uops_2_is_sys_pc2epc;\t// @[core.scala:173:24]\n wire iss_uops_2_uses_stq;\t// @[core.scala:173:24]\n wire iss_uops_2_uses_ldq;\t// @[core.scala:173:24]\n wire iss_uops_2_is_amo;\t// @[core.scala:173:24]\n wire iss_uops_2_is_fencei;\t// @[core.scala:173:24]\n wire iss_uops_2_is_fence;\t// @[core.scala:173:24]\n wire iss_uops_2_mem_signed;\t// @[core.scala:173:24]\n wire [1:0] iss_uops_2_mem_size;\t// @[core.scala:173:24]\n wire [4:0] iss_uops_2_mem_cmd;\t// @[core.scala:173:24]\n wire iss_uops_2_bypassable;\t// @[core.scala:173:24]\n wire [63:0] iss_uops_2_exc_cause;\t// @[core.scala:173:24]\n wire iss_uops_2_exception;\t// @[core.scala:173:24]\n wire [6:0] iss_uops_2_stale_pdst;\t// @[core.scala:173:24]\n wire iss_uops_2_ppred_busy;\t// @[core.scala:173:24]\n wire iss_uops_2_prs3_busy;\t// @[core.scala:173:24]\n wire iss_uops_2_prs2_busy;\t// @[core.scala:173:24]\n wire iss_uops_2_prs1_busy;\t// @[core.scala:173:24]\n wire [4:0] iss_uops_2_ppred;\t// @[core.scala:173:24]\n wire [6:0] iss_uops_2_prs3;\t// @[core.scala:173:24]\n wire [6:0] iss_uops_2_prs2;\t// @[core.scala:173:24]\n wire [6:0] iss_uops_2_prs1;\t// @[core.scala:173:24]\n wire [6:0] iss_uops_2_pdst;\t// @[core.scala:173:24]\n wire [1:0] iss_uops_2_rxq_idx;\t// @[core.scala:173:24]\n wire [4:0] iss_uops_2_stq_idx;\t// @[core.scala:173:24]\n wire [4:0] iss_uops_2_ldq_idx;\t// @[core.scala:173:24]\n wire [6:0] iss_uops_2_rob_idx;\t// @[core.scala:173:24]\n wire [11:0] iss_uops_2_csr_addr;\t// @[core.scala:173:24]\n wire [19:0] iss_uops_2_imm_packed;\t// @[core.scala:173:24]\n wire iss_uops_2_taken;\t// @[core.scala:173:24]\n wire [5:0] iss_uops_2_pc_lob;\t// @[core.scala:173:24]\n wire iss_uops_2_edge_inst;\t// @[core.scala:173:24]\n wire [4:0] iss_uops_2_ftq_idx;\t// @[core.scala:173:24]\n wire [3:0] iss_uops_2_br_tag;\t// @[core.scala:173:24]\n wire [15:0] iss_uops_2_br_mask;\t// @[core.scala:173:24]\n wire iss_uops_2_is_sfb;\t// @[core.scala:173:24]\n wire iss_uops_2_is_jal;\t// @[core.scala:173:24]\n wire iss_uops_2_is_jalr;\t// @[core.scala:173:24]\n wire iss_uops_2_is_br;\t// @[core.scala:173:24]\n wire iss_uops_2_iw_p2_poisoned;\t// @[core.scala:173:24]\n wire iss_uops_2_iw_p1_poisoned;\t// @[core.scala:173:24]\n wire [1:0] iss_uops_2_iw_state;\t// @[core.scala:173:24]\n wire [9:0] iss_uops_2_fu_code;\t// @[core.scala:173:24]\n wire [2:0] iss_uops_2_iq_type;\t// @[core.scala:173:24]\n wire [39:0] iss_uops_2_debug_pc;\t// @[core.scala:173:24]\n wire iss_uops_2_is_rvc;\t// @[core.scala:173:24]\n wire [31:0] iss_uops_2_debug_inst;\t// @[core.scala:173:24]\n wire [31:0] iss_uops_2_inst;\t// @[core.scala:173:24]\n wire [6:0] iss_uops_2_uopc;\t// @[core.scala:173:24]\n wire iss_uops_2_ctrl_is_std;\t// @[core.scala:173:24]\n wire iss_uops_2_ctrl_is_sta;\t// @[core.scala:173:24]\n wire iss_uops_2_ctrl_is_load;\t// @[core.scala:173:24]\n wire [2:0] iss_uops_2_ctrl_csr_cmd;\t// @[core.scala:173:24]\n wire iss_uops_2_ctrl_fcn_dw;\t// @[core.scala:173:24]\n wire [4:0] iss_uops_2_ctrl_op_fcn;\t// @[core.scala:173:24]\n wire [2:0] iss_uops_2_ctrl_imm_sel;\t// @[core.scala:173:24]\n wire [2:0] iss_uops_2_ctrl_op2_sel;\t// @[core.scala:173:24]\n wire [1:0] iss_uops_2_ctrl_op1_sel;\t// @[core.scala:173:24]\n wire [3:0] iss_uops_2_ctrl_br_type;\t// @[core.scala:173:24]\n wire dis_valids_0;\t// @[core.scala:166:24]\n wire io_ifu_sfence_bits_asid_0;\t// @[core.scala:51:7]\n wire [38:0] io_ifu_sfence_bits_addr_0;\t// @[core.scala:51:7]\n wire io_ifu_sfence_bits_rs2_0;\t// @[core.scala:51:7]\n wire io_ifu_sfence_bits_rs1_0;\t// @[core.scala:51:7]\n wire io_ifu_sfence_valid_0;\t// @[core.scala:51:7]\n wire [63:0] _csr_io_rw_rdata;\t// @[core.scala:271:19]\n wire _csr_io_decode_0_fp_illegal;\t// @[core.scala:271:19]\n wire _csr_io_decode_0_fp_csr;\t// @[core.scala:271:19]\n wire _csr_io_decode_0_read_illegal;\t// @[core.scala:271:19]\n wire _csr_io_decode_0_write_illegal;\t// @[core.scala:271:19]\n wire _csr_io_decode_0_write_flush;\t// @[core.scala:271:19]\n wire _csr_io_decode_0_system_illegal;\t// @[core.scala:271:19]\n wire _csr_io_decode_0_virtual_access_illegal;\t// @[core.scala:271:19]\n wire _csr_io_decode_0_virtual_system_illegal;\t// @[core.scala:271:19]\n wire _csr_io_decode_1_fp_illegal;\t// @[core.scala:271:19]\n wire _csr_io_decode_1_fp_csr;\t// @[core.scala:271:19]\n wire _csr_io_decode_1_read_illegal;\t// @[core.scala:271:19]\n wire _csr_io_decode_1_write_illegal;\t// @[core.scala:271:19]\n wire _csr_io_decode_1_write_flush;\t// @[core.scala:271:19]\n wire _csr_io_decode_1_system_illegal;\t// @[core.scala:271:19]\n wire _csr_io_decode_1_virtual_access_illegal;\t// @[core.scala:271:19]\n wire _csr_io_decode_1_virtual_system_illegal;\t// @[core.scala:271:19]\n wire _csr_io_decode_2_fp_illegal;\t// @[core.scala:271:19]\n wire _csr_io_decode_2_fp_csr;\t// @[core.scala:271:19]\n wire _csr_io_decode_2_read_illegal;\t// @[core.scala:271:19]\n wire _csr_io_decode_2_write_illegal;\t// @[core.scala:271:19]\n wire _csr_io_decode_2_write_flush;\t// @[core.scala:271:19]\n wire _csr_io_decode_2_system_illegal;\t// @[core.scala:271:19]\n wire _csr_io_decode_2_virtual_access_illegal;\t// @[core.scala:271:19]\n wire _csr_io_decode_2_virtual_system_illegal;\t// @[core.scala:271:19]\n wire _csr_io_csr_stall;\t// @[core.scala:271:19]\n wire _csr_io_singleStep;\t// @[core.scala:271:19]\n wire _csr_io_status_debug;\t// @[core.scala:271:19]\n wire _csr_io_status_cease;\t// @[core.scala:271:19]\n wire _csr_io_status_wfi;\t// @[core.scala:271:19]\n wire [1:0] _csr_io_status_dprv;\t// @[core.scala:271:19]\n wire _csr_io_status_dv;\t// @[core.scala:271:19]\n wire [1:0] _csr_io_status_prv;\t// @[core.scala:271:19]\n wire _csr_io_status_v;\t// @[core.scala:271:19]\n wire _csr_io_status_sd;\t// @[core.scala:271:19]\n wire _csr_io_status_mpv;\t// @[core.scala:271:19]\n wire _csr_io_status_gva;\t// @[core.scala:271:19]\n wire _csr_io_status_tsr;\t// @[core.scala:271:19]\n wire _csr_io_status_tw;\t// @[core.scala:271:19]\n wire _csr_io_status_tvm;\t// @[core.scala:271:19]\n wire _csr_io_status_mxr;\t// @[core.scala:271:19]\n wire _csr_io_status_sum;\t// @[core.scala:271:19]\n wire _csr_io_status_mprv;\t// @[core.scala:271:19]\n wire [1:0] _csr_io_status_fs;\t// @[core.scala:271:19]\n wire [1:0] _csr_io_status_mpp;\t// @[core.scala:271:19]\n wire _csr_io_status_spp;\t// @[core.scala:271:19]\n wire _csr_io_status_mpie;\t// @[core.scala:271:19]\n wire _csr_io_status_spie;\t// @[core.scala:271:19]\n wire _csr_io_status_mie;\t// @[core.scala:271:19]\n wire _csr_io_status_sie;\t// @[core.scala:271:19]\n wire [39:0] _csr_io_evec;\t// @[core.scala:271:19]\n wire [2:0] _csr_io_fcsr_rm;\t// @[core.scala:271:19]\n wire _csr_io_interrupt;\t// @[core.scala:271:19]\n wire [63:0] _csr_io_interrupt_cause;\t// @[core.scala:271:19]\n wire [6:0] _rob_io_rob_tail_idx;\t// @[core.scala:143:32]\n wire [6:0] _rob_io_rob_head_idx;\t// @[core.scala:143:32]\n wire _rob_io_commit_valids_0;\t// @[core.scala:143:32]\n wire _rob_io_commit_valids_1;\t// @[core.scala:143:32]\n wire _rob_io_commit_valids_2;\t// @[core.scala:143:32]\n wire _rob_io_commit_arch_valids_0;\t// @[core.scala:143:32]\n wire _rob_io_commit_arch_valids_1;\t// @[core.scala:143:32]\n wire _rob_io_commit_arch_valids_2;\t// @[core.scala:143:32]\n wire [6:0] _rob_io_commit_uops_0_uopc;\t// @[core.scala:143:32]\n wire [31:0] _rob_io_commit_uops_0_inst;\t// @[core.scala:143:32]\n wire [31:0] _rob_io_commit_uops_0_debug_inst;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_0_is_rvc;\t// @[core.scala:143:32]\n wire [39:0] _rob_io_commit_uops_0_debug_pc;\t// @[core.scala:143:32]\n wire [2:0] _rob_io_commit_uops_0_iq_type;\t// @[core.scala:143:32]\n wire [9:0] _rob_io_commit_uops_0_fu_code;\t// @[core.scala:143:32]\n wire [3:0] _rob_io_commit_uops_0_ctrl_br_type;\t// @[core.scala:143:32]\n wire [1:0] _rob_io_commit_uops_0_ctrl_op1_sel;\t// @[core.scala:143:32]\n wire [2:0] _rob_io_commit_uops_0_ctrl_op2_sel;\t// @[core.scala:143:32]\n wire [2:0] _rob_io_commit_uops_0_ctrl_imm_sel;\t// @[core.scala:143:32]\n wire [4:0] _rob_io_commit_uops_0_ctrl_op_fcn;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_0_ctrl_fcn_dw;\t// @[core.scala:143:32]\n wire [2:0] _rob_io_commit_uops_0_ctrl_csr_cmd;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_0_ctrl_is_load;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_0_ctrl_is_sta;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_0_ctrl_is_std;\t// @[core.scala:143:32]\n wire [1:0] _rob_io_commit_uops_0_iw_state;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_0_iw_p1_poisoned;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_0_iw_p2_poisoned;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_0_is_br;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_0_is_jalr;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_0_is_jal;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_0_is_sfb;\t// @[core.scala:143:32]\n wire [15:0] _rob_io_commit_uops_0_br_mask;\t// @[core.scala:143:32]\n wire [3:0] _rob_io_commit_uops_0_br_tag;\t// @[core.scala:143:32]\n wire [4:0] _rob_io_commit_uops_0_ftq_idx;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_0_edge_inst;\t// @[core.scala:143:32]\n wire [5:0] _rob_io_commit_uops_0_pc_lob;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_0_taken;\t// @[core.scala:143:32]\n wire [19:0] _rob_io_commit_uops_0_imm_packed;\t// @[core.scala:143:32]\n wire [11:0] _rob_io_commit_uops_0_csr_addr;\t// @[core.scala:143:32]\n wire [6:0] _rob_io_commit_uops_0_rob_idx;\t// @[core.scala:143:32]\n wire [4:0] _rob_io_commit_uops_0_ldq_idx;\t// @[core.scala:143:32]\n wire [4:0] _rob_io_commit_uops_0_stq_idx;\t// @[core.scala:143:32]\n wire [1:0] _rob_io_commit_uops_0_rxq_idx;\t// @[core.scala:143:32]\n wire [6:0] _rob_io_commit_uops_0_pdst;\t// @[core.scala:143:32]\n wire [6:0] _rob_io_commit_uops_0_prs1;\t// @[core.scala:143:32]\n wire [6:0] _rob_io_commit_uops_0_prs2;\t// @[core.scala:143:32]\n wire [6:0] _rob_io_commit_uops_0_prs3;\t// @[core.scala:143:32]\n wire [4:0] _rob_io_commit_uops_0_ppred;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_0_prs1_busy;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_0_prs2_busy;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_0_prs3_busy;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_0_ppred_busy;\t// @[core.scala:143:32]\n wire [6:0] _rob_io_commit_uops_0_stale_pdst;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_0_exception;\t// @[core.scala:143:32]\n wire [63:0] _rob_io_commit_uops_0_exc_cause;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_0_bypassable;\t// @[core.scala:143:32]\n wire [4:0] _rob_io_commit_uops_0_mem_cmd;\t// @[core.scala:143:32]\n wire [1:0] _rob_io_commit_uops_0_mem_size;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_0_mem_signed;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_0_is_fence;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_0_is_fencei;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_0_is_amo;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_0_uses_ldq;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_0_uses_stq;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_0_is_sys_pc2epc;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_0_is_unique;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_0_flush_on_commit;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_0_ldst_is_rs1;\t// @[core.scala:143:32]\n wire [5:0] _rob_io_commit_uops_0_ldst;\t// @[core.scala:143:32]\n wire [5:0] _rob_io_commit_uops_0_lrs1;\t// @[core.scala:143:32]\n wire [5:0] _rob_io_commit_uops_0_lrs2;\t// @[core.scala:143:32]\n wire [5:0] _rob_io_commit_uops_0_lrs3;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_0_ldst_val;\t// @[core.scala:143:32]\n wire [1:0] _rob_io_commit_uops_0_dst_rtype;\t// @[core.scala:143:32]\n wire [1:0] _rob_io_commit_uops_0_lrs1_rtype;\t// @[core.scala:143:32]\n wire [1:0] _rob_io_commit_uops_0_lrs2_rtype;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_0_frs3_en;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_0_fp_val;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_0_fp_single;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_0_xcpt_pf_if;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_0_xcpt_ae_if;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_0_xcpt_ma_if;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_0_bp_debug_if;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_0_bp_xcpt_if;\t// @[core.scala:143:32]\n wire [1:0] _rob_io_commit_uops_0_debug_fsrc;\t// @[core.scala:143:32]\n wire [1:0] _rob_io_commit_uops_0_debug_tsrc;\t// @[core.scala:143:32]\n wire [6:0] _rob_io_commit_uops_1_uopc;\t// @[core.scala:143:32]\n wire [31:0] _rob_io_commit_uops_1_inst;\t// @[core.scala:143:32]\n wire [31:0] _rob_io_commit_uops_1_debug_inst;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_1_is_rvc;\t// @[core.scala:143:32]\n wire [39:0] _rob_io_commit_uops_1_debug_pc;\t// @[core.scala:143:32]\n wire [2:0] _rob_io_commit_uops_1_iq_type;\t// @[core.scala:143:32]\n wire [9:0] _rob_io_commit_uops_1_fu_code;\t// @[core.scala:143:32]\n wire [3:0] _rob_io_commit_uops_1_ctrl_br_type;\t// @[core.scala:143:32]\n wire [1:0] _rob_io_commit_uops_1_ctrl_op1_sel;\t// @[core.scala:143:32]\n wire [2:0] _rob_io_commit_uops_1_ctrl_op2_sel;\t// @[core.scala:143:32]\n wire [2:0] _rob_io_commit_uops_1_ctrl_imm_sel;\t// @[core.scala:143:32]\n wire [4:0] _rob_io_commit_uops_1_ctrl_op_fcn;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_1_ctrl_fcn_dw;\t// @[core.scala:143:32]\n wire [2:0] _rob_io_commit_uops_1_ctrl_csr_cmd;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_1_ctrl_is_load;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_1_ctrl_is_sta;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_1_ctrl_is_std;\t// @[core.scala:143:32]\n wire [1:0] _rob_io_commit_uops_1_iw_state;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_1_iw_p1_poisoned;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_1_iw_p2_poisoned;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_1_is_br;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_1_is_jalr;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_1_is_jal;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_1_is_sfb;\t// @[core.scala:143:32]\n wire [15:0] _rob_io_commit_uops_1_br_mask;\t// @[core.scala:143:32]\n wire [3:0] _rob_io_commit_uops_1_br_tag;\t// @[core.scala:143:32]\n wire [4:0] _rob_io_commit_uops_1_ftq_idx;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_1_edge_inst;\t// @[core.scala:143:32]\n wire [5:0] _rob_io_commit_uops_1_pc_lob;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_1_taken;\t// @[core.scala:143:32]\n wire [19:0] _rob_io_commit_uops_1_imm_packed;\t// @[core.scala:143:32]\n wire [11:0] _rob_io_commit_uops_1_csr_addr;\t// @[core.scala:143:32]\n wire [6:0] _rob_io_commit_uops_1_rob_idx;\t// @[core.scala:143:32]\n wire [4:0] _rob_io_commit_uops_1_ldq_idx;\t// @[core.scala:143:32]\n wire [4:0] _rob_io_commit_uops_1_stq_idx;\t// @[core.scala:143:32]\n wire [1:0] _rob_io_commit_uops_1_rxq_idx;\t// @[core.scala:143:32]\n wire [6:0] _rob_io_commit_uops_1_pdst;\t// @[core.scala:143:32]\n wire [6:0] _rob_io_commit_uops_1_prs1;\t// @[core.scala:143:32]\n wire [6:0] _rob_io_commit_uops_1_prs2;\t// @[core.scala:143:32]\n wire [6:0] _rob_io_commit_uops_1_prs3;\t// @[core.scala:143:32]\n wire [4:0] _rob_io_commit_uops_1_ppred;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_1_prs1_busy;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_1_prs2_busy;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_1_prs3_busy;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_1_ppred_busy;\t// @[core.scala:143:32]\n wire [6:0] _rob_io_commit_uops_1_stale_pdst;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_1_exception;\t// @[core.scala:143:32]\n wire [63:0] _rob_io_commit_uops_1_exc_cause;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_1_bypassable;\t// @[core.scala:143:32]\n wire [4:0] _rob_io_commit_uops_1_mem_cmd;\t// @[core.scala:143:32]\n wire [1:0] _rob_io_commit_uops_1_mem_size;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_1_mem_signed;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_1_is_fence;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_1_is_fencei;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_1_is_amo;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_1_uses_ldq;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_1_uses_stq;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_1_is_sys_pc2epc;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_1_is_unique;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_1_flush_on_commit;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_1_ldst_is_rs1;\t// @[core.scala:143:32]\n wire [5:0] _rob_io_commit_uops_1_ldst;\t// @[core.scala:143:32]\n wire [5:0] _rob_io_commit_uops_1_lrs1;\t// @[core.scala:143:32]\n wire [5:0] _rob_io_commit_uops_1_lrs2;\t// @[core.scala:143:32]\n wire [5:0] _rob_io_commit_uops_1_lrs3;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_1_ldst_val;\t// @[core.scala:143:32]\n wire [1:0] _rob_io_commit_uops_1_dst_rtype;\t// @[core.scala:143:32]\n wire [1:0] _rob_io_commit_uops_1_lrs1_rtype;\t// @[core.scala:143:32]\n wire [1:0] _rob_io_commit_uops_1_lrs2_rtype;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_1_frs3_en;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_1_fp_val;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_1_fp_single;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_1_xcpt_pf_if;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_1_xcpt_ae_if;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_1_xcpt_ma_if;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_1_bp_debug_if;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_1_bp_xcpt_if;\t// @[core.scala:143:32]\n wire [1:0] _rob_io_commit_uops_1_debug_fsrc;\t// @[core.scala:143:32]\n wire [1:0] _rob_io_commit_uops_1_debug_tsrc;\t// @[core.scala:143:32]\n wire [6:0] _rob_io_commit_uops_2_uopc;\t// @[core.scala:143:32]\n wire [31:0] _rob_io_commit_uops_2_inst;\t// @[core.scala:143:32]\n wire [31:0] _rob_io_commit_uops_2_debug_inst;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_2_is_rvc;\t// @[core.scala:143:32]\n wire [39:0] _rob_io_commit_uops_2_debug_pc;\t// @[core.scala:143:32]\n wire [2:0] _rob_io_commit_uops_2_iq_type;\t// @[core.scala:143:32]\n wire [9:0] _rob_io_commit_uops_2_fu_code;\t// @[core.scala:143:32]\n wire [3:0] _rob_io_commit_uops_2_ctrl_br_type;\t// @[core.scala:143:32]\n wire [1:0] _rob_io_commit_uops_2_ctrl_op1_sel;\t// @[core.scala:143:32]\n wire [2:0] _rob_io_commit_uops_2_ctrl_op2_sel;\t// @[core.scala:143:32]\n wire [2:0] _rob_io_commit_uops_2_ctrl_imm_sel;\t// @[core.scala:143:32]\n wire [4:0] _rob_io_commit_uops_2_ctrl_op_fcn;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_2_ctrl_fcn_dw;\t// @[core.scala:143:32]\n wire [2:0] _rob_io_commit_uops_2_ctrl_csr_cmd;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_2_ctrl_is_load;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_2_ctrl_is_sta;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_2_ctrl_is_std;\t// @[core.scala:143:32]\n wire [1:0] _rob_io_commit_uops_2_iw_state;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_2_iw_p1_poisoned;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_2_iw_p2_poisoned;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_2_is_br;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_2_is_jalr;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_2_is_jal;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_2_is_sfb;\t// @[core.scala:143:32]\n wire [15:0] _rob_io_commit_uops_2_br_mask;\t// @[core.scala:143:32]\n wire [3:0] _rob_io_commit_uops_2_br_tag;\t// @[core.scala:143:32]\n wire [4:0] _rob_io_commit_uops_2_ftq_idx;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_2_edge_inst;\t// @[core.scala:143:32]\n wire [5:0] _rob_io_commit_uops_2_pc_lob;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_2_taken;\t// @[core.scala:143:32]\n wire [19:0] _rob_io_commit_uops_2_imm_packed;\t// @[core.scala:143:32]\n wire [11:0] _rob_io_commit_uops_2_csr_addr;\t// @[core.scala:143:32]\n wire [6:0] _rob_io_commit_uops_2_rob_idx;\t// @[core.scala:143:32]\n wire [4:0] _rob_io_commit_uops_2_ldq_idx;\t// @[core.scala:143:32]\n wire [4:0] _rob_io_commit_uops_2_stq_idx;\t// @[core.scala:143:32]\n wire [1:0] _rob_io_commit_uops_2_rxq_idx;\t// @[core.scala:143:32]\n wire [6:0] _rob_io_commit_uops_2_pdst;\t// @[core.scala:143:32]\n wire [6:0] _rob_io_commit_uops_2_prs1;\t// @[core.scala:143:32]\n wire [6:0] _rob_io_commit_uops_2_prs2;\t// @[core.scala:143:32]\n wire [6:0] _rob_io_commit_uops_2_prs3;\t// @[core.scala:143:32]\n wire [4:0] _rob_io_commit_uops_2_ppred;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_2_prs1_busy;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_2_prs2_busy;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_2_prs3_busy;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_2_ppred_busy;\t// @[core.scala:143:32]\n wire [6:0] _rob_io_commit_uops_2_stale_pdst;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_2_exception;\t// @[core.scala:143:32]\n wire [63:0] _rob_io_commit_uops_2_exc_cause;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_2_bypassable;\t// @[core.scala:143:32]\n wire [4:0] _rob_io_commit_uops_2_mem_cmd;\t// @[core.scala:143:32]\n wire [1:0] _rob_io_commit_uops_2_mem_size;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_2_mem_signed;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_2_is_fence;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_2_is_fencei;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_2_is_amo;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_2_uses_ldq;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_2_uses_stq;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_2_is_sys_pc2epc;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_2_is_unique;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_2_flush_on_commit;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_2_ldst_is_rs1;\t// @[core.scala:143:32]\n wire [5:0] _rob_io_commit_uops_2_ldst;\t// @[core.scala:143:32]\n wire [5:0] _rob_io_commit_uops_2_lrs1;\t// @[core.scala:143:32]\n wire [5:0] _rob_io_commit_uops_2_lrs2;\t// @[core.scala:143:32]\n wire [5:0] _rob_io_commit_uops_2_lrs3;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_2_ldst_val;\t// @[core.scala:143:32]\n wire [1:0] _rob_io_commit_uops_2_dst_rtype;\t// @[core.scala:143:32]\n wire [1:0] _rob_io_commit_uops_2_lrs1_rtype;\t// @[core.scala:143:32]\n wire [1:0] _rob_io_commit_uops_2_lrs2_rtype;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_2_frs3_en;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_2_fp_val;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_2_fp_single;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_2_xcpt_pf_if;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_2_xcpt_ae_if;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_2_xcpt_ma_if;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_2_bp_debug_if;\t// @[core.scala:143:32]\n wire _rob_io_commit_uops_2_bp_xcpt_if;\t// @[core.scala:143:32]\n wire [1:0] _rob_io_commit_uops_2_debug_fsrc;\t// @[core.scala:143:32]\n wire [1:0] _rob_io_commit_uops_2_debug_tsrc;\t// @[core.scala:143:32]\n wire _rob_io_commit_fflags_valid;\t// @[core.scala:143:32]\n wire [4:0] _rob_io_commit_fflags_bits;\t// @[core.scala:143:32]\n wire _rob_io_commit_rbk_valids_0;\t// @[core.scala:143:32]\n wire _rob_io_commit_rbk_valids_1;\t// @[core.scala:143:32]\n wire _rob_io_commit_rbk_valids_2;\t// @[core.scala:143:32]\n wire _rob_io_commit_rollback;\t// @[core.scala:143:32]\n wire _rob_io_com_xcpt_valid;\t// @[core.scala:143:32]\n wire [4:0] _rob_io_com_xcpt_bits_ftq_idx;\t// @[core.scala:143:32]\n wire _rob_io_com_xcpt_bits_edge_inst;\t// @[core.scala:143:32]\n wire [5:0] _rob_io_com_xcpt_bits_pc_lob;\t// @[core.scala:143:32]\n wire [63:0] _rob_io_com_xcpt_bits_cause;\t// @[core.scala:143:32]\n wire [63:0] _rob_io_com_xcpt_bits_badvaddr;\t// @[core.scala:143:32]\n wire _rob_io_flush_valid;\t// @[core.scala:143:32]\n wire [4:0] _rob_io_flush_bits_ftq_idx;\t// @[core.scala:143:32]\n wire _rob_io_flush_bits_edge_inst;\t// @[core.scala:143:32]\n wire _rob_io_flush_bits_is_rvc;\t// @[core.scala:143:32]\n wire [5:0] _rob_io_flush_bits_pc_lob;\t// @[core.scala:143:32]\n wire [2:0] _rob_io_flush_bits_flush_typ;\t// @[core.scala:143:32]\n wire _rob_io_empty;\t// @[core.scala:143:32]\n wire _rob_io_ready;\t// @[core.scala:143:32]\n wire _rob_io_flush_frontend;\t// @[core.scala:143:32]\n wire [6:0] _iregister_read_io_rf_read_ports_0_addr;\t// @[core.scala:135:32]\n wire [6:0] _iregister_read_io_rf_read_ports_1_addr;\t// @[core.scala:135:32]\n wire [6:0] _iregister_read_io_rf_read_ports_2_addr;\t// @[core.scala:135:32]\n wire [6:0] _iregister_read_io_rf_read_ports_3_addr;\t// @[core.scala:135:32]\n wire [6:0] _iregister_read_io_rf_read_ports_4_addr;\t// @[core.scala:135:32]\n wire [6:0] _iregister_read_io_rf_read_ports_5_addr;\t// @[core.scala:135:32]\n wire [6:0] _iregister_read_io_rf_read_ports_6_addr;\t// @[core.scala:135:32]\n wire [6:0] _iregister_read_io_rf_read_ports_7_addr;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_0_valid;\t// @[core.scala:135:32]\n wire [6:0] _iregister_read_io_exe_reqs_0_bits_uop_uopc;\t// @[core.scala:135:32]\n wire [31:0] _iregister_read_io_exe_reqs_0_bits_uop_inst;\t// @[core.scala:135:32]\n wire [31:0] _iregister_read_io_exe_reqs_0_bits_uop_debug_inst;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_0_bits_uop_is_rvc;\t// @[core.scala:135:32]\n wire [39:0] _iregister_read_io_exe_reqs_0_bits_uop_debug_pc;\t// @[core.scala:135:32]\n wire [2:0] _iregister_read_io_exe_reqs_0_bits_uop_iq_type;\t// @[core.scala:135:32]\n wire [9:0] _iregister_read_io_exe_reqs_0_bits_uop_fu_code;\t// @[core.scala:135:32]\n wire [3:0] _iregister_read_io_exe_reqs_0_bits_uop_ctrl_br_type;\t// @[core.scala:135:32]\n wire [1:0] _iregister_read_io_exe_reqs_0_bits_uop_ctrl_op1_sel;\t// @[core.scala:135:32]\n wire [2:0] _iregister_read_io_exe_reqs_0_bits_uop_ctrl_op2_sel;\t// @[core.scala:135:32]\n wire [2:0] _iregister_read_io_exe_reqs_0_bits_uop_ctrl_imm_sel;\t// @[core.scala:135:32]\n wire [4:0] _iregister_read_io_exe_reqs_0_bits_uop_ctrl_op_fcn;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_0_bits_uop_ctrl_fcn_dw;\t// @[core.scala:135:32]\n wire [2:0] _iregister_read_io_exe_reqs_0_bits_uop_ctrl_csr_cmd;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_0_bits_uop_ctrl_is_load;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_0_bits_uop_ctrl_is_sta;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_0_bits_uop_ctrl_is_std;\t// @[core.scala:135:32]\n wire [1:0] _iregister_read_io_exe_reqs_0_bits_uop_iw_state;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_0_bits_uop_iw_p1_poisoned;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_0_bits_uop_iw_p2_poisoned;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_0_bits_uop_is_br;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_0_bits_uop_is_jalr;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_0_bits_uop_is_jal;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_0_bits_uop_is_sfb;\t// @[core.scala:135:32]\n wire [15:0] _iregister_read_io_exe_reqs_0_bits_uop_br_mask;\t// @[core.scala:135:32]\n wire [3:0] _iregister_read_io_exe_reqs_0_bits_uop_br_tag;\t// @[core.scala:135:32]\n wire [4:0] _iregister_read_io_exe_reqs_0_bits_uop_ftq_idx;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_0_bits_uop_edge_inst;\t// @[core.scala:135:32]\n wire [5:0] _iregister_read_io_exe_reqs_0_bits_uop_pc_lob;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_0_bits_uop_taken;\t// @[core.scala:135:32]\n wire [19:0] _iregister_read_io_exe_reqs_0_bits_uop_imm_packed;\t// @[core.scala:135:32]\n wire [11:0] _iregister_read_io_exe_reqs_0_bits_uop_csr_addr;\t// @[core.scala:135:32]\n wire [6:0] _iregister_read_io_exe_reqs_0_bits_uop_rob_idx;\t// @[core.scala:135:32]\n wire [4:0] _iregister_read_io_exe_reqs_0_bits_uop_ldq_idx;\t// @[core.scala:135:32]\n wire [4:0] _iregister_read_io_exe_reqs_0_bits_uop_stq_idx;\t// @[core.scala:135:32]\n wire [1:0] _iregister_read_io_exe_reqs_0_bits_uop_rxq_idx;\t// @[core.scala:135:32]\n wire [6:0] _iregister_read_io_exe_reqs_0_bits_uop_pdst;\t// @[core.scala:135:32]\n wire [6:0] _iregister_read_io_exe_reqs_0_bits_uop_prs1;\t// @[core.scala:135:32]\n wire [6:0] _iregister_read_io_exe_reqs_0_bits_uop_prs2;\t// @[core.scala:135:32]\n wire [6:0] _iregister_read_io_exe_reqs_0_bits_uop_prs3;\t// @[core.scala:135:32]\n wire [4:0] _iregister_read_io_exe_reqs_0_bits_uop_ppred;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_0_bits_uop_prs1_busy;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_0_bits_uop_prs2_busy;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_0_bits_uop_prs3_busy;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_0_bits_uop_ppred_busy;\t// @[core.scala:135:32]\n wire [6:0] _iregister_read_io_exe_reqs_0_bits_uop_stale_pdst;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_0_bits_uop_exception;\t// @[core.scala:135:32]\n wire [63:0] _iregister_read_io_exe_reqs_0_bits_uop_exc_cause;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_0_bits_uop_bypassable;\t// @[core.scala:135:32]\n wire [4:0] _iregister_read_io_exe_reqs_0_bits_uop_mem_cmd;\t// @[core.scala:135:32]\n wire [1:0] _iregister_read_io_exe_reqs_0_bits_uop_mem_size;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_0_bits_uop_mem_signed;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_0_bits_uop_is_fence;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_0_bits_uop_is_fencei;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_0_bits_uop_is_amo;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_0_bits_uop_uses_ldq;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_0_bits_uop_uses_stq;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_0_bits_uop_is_sys_pc2epc;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_0_bits_uop_is_unique;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_0_bits_uop_flush_on_commit;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_0_bits_uop_ldst_is_rs1;\t// @[core.scala:135:32]\n wire [5:0] _iregister_read_io_exe_reqs_0_bits_uop_ldst;\t// @[core.scala:135:32]\n wire [5:0] _iregister_read_io_exe_reqs_0_bits_uop_lrs1;\t// @[core.scala:135:32]\n wire [5:0] _iregister_read_io_exe_reqs_0_bits_uop_lrs2;\t// @[core.scala:135:32]\n wire [5:0] _iregister_read_io_exe_reqs_0_bits_uop_lrs3;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_0_bits_uop_ldst_val;\t// @[core.scala:135:32]\n wire [1:0] _iregister_read_io_exe_reqs_0_bits_uop_dst_rtype;\t// @[core.scala:135:32]\n wire [1:0] _iregister_read_io_exe_reqs_0_bits_uop_lrs1_rtype;\t// @[core.scala:135:32]\n wire [1:0] _iregister_read_io_exe_reqs_0_bits_uop_lrs2_rtype;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_0_bits_uop_frs3_en;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_0_bits_uop_fp_val;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_0_bits_uop_fp_single;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_0_bits_uop_xcpt_pf_if;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_0_bits_uop_xcpt_ae_if;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_0_bits_uop_xcpt_ma_if;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_0_bits_uop_bp_debug_if;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_0_bits_uop_bp_xcpt_if;\t// @[core.scala:135:32]\n wire [1:0] _iregister_read_io_exe_reqs_0_bits_uop_debug_fsrc;\t// @[core.scala:135:32]\n wire [1:0] _iregister_read_io_exe_reqs_0_bits_uop_debug_tsrc;\t// @[core.scala:135:32]\n wire [63:0] _iregister_read_io_exe_reqs_0_bits_rs1_data;\t// @[core.scala:135:32]\n wire [63:0] _iregister_read_io_exe_reqs_0_bits_rs2_data;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_1_valid;\t// @[core.scala:135:32]\n wire [6:0] _iregister_read_io_exe_reqs_1_bits_uop_uopc;\t// @[core.scala:135:32]\n wire [31:0] _iregister_read_io_exe_reqs_1_bits_uop_inst;\t// @[core.scala:135:32]\n wire [31:0] _iregister_read_io_exe_reqs_1_bits_uop_debug_inst;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_1_bits_uop_is_rvc;\t// @[core.scala:135:32]\n wire [39:0] _iregister_read_io_exe_reqs_1_bits_uop_debug_pc;\t// @[core.scala:135:32]\n wire [2:0] _iregister_read_io_exe_reqs_1_bits_uop_iq_type;\t// @[core.scala:135:32]\n wire [9:0] _iregister_read_io_exe_reqs_1_bits_uop_fu_code;\t// @[core.scala:135:32]\n wire [3:0] _iregister_read_io_exe_reqs_1_bits_uop_ctrl_br_type;\t// @[core.scala:135:32]\n wire [1:0] _iregister_read_io_exe_reqs_1_bits_uop_ctrl_op1_sel;\t// @[core.scala:135:32]\n wire [2:0] _iregister_read_io_exe_reqs_1_bits_uop_ctrl_op2_sel;\t// @[core.scala:135:32]\n wire [2:0] _iregister_read_io_exe_reqs_1_bits_uop_ctrl_imm_sel;\t// @[core.scala:135:32]\n wire [4:0] _iregister_read_io_exe_reqs_1_bits_uop_ctrl_op_fcn;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_1_bits_uop_ctrl_fcn_dw;\t// @[core.scala:135:32]\n wire [2:0] _iregister_read_io_exe_reqs_1_bits_uop_ctrl_csr_cmd;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_1_bits_uop_ctrl_is_load;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_1_bits_uop_ctrl_is_sta;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_1_bits_uop_ctrl_is_std;\t// @[core.scala:135:32]\n wire [1:0] _iregister_read_io_exe_reqs_1_bits_uop_iw_state;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_1_bits_uop_iw_p1_poisoned;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_1_bits_uop_iw_p2_poisoned;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_1_bits_uop_is_br;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_1_bits_uop_is_jalr;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_1_bits_uop_is_jal;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_1_bits_uop_is_sfb;\t// @[core.scala:135:32]\n wire [15:0] _iregister_read_io_exe_reqs_1_bits_uop_br_mask;\t// @[core.scala:135:32]\n wire [3:0] _iregister_read_io_exe_reqs_1_bits_uop_br_tag;\t// @[core.scala:135:32]\n wire [4:0] _iregister_read_io_exe_reqs_1_bits_uop_ftq_idx;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_1_bits_uop_edge_inst;\t// @[core.scala:135:32]\n wire [5:0] _iregister_read_io_exe_reqs_1_bits_uop_pc_lob;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_1_bits_uop_taken;\t// @[core.scala:135:32]\n wire [19:0] _iregister_read_io_exe_reqs_1_bits_uop_imm_packed;\t// @[core.scala:135:32]\n wire [11:0] _iregister_read_io_exe_reqs_1_bits_uop_csr_addr;\t// @[core.scala:135:32]\n wire [6:0] _iregister_read_io_exe_reqs_1_bits_uop_rob_idx;\t// @[core.scala:135:32]\n wire [4:0] _iregister_read_io_exe_reqs_1_bits_uop_ldq_idx;\t// @[core.scala:135:32]\n wire [4:0] _iregister_read_io_exe_reqs_1_bits_uop_stq_idx;\t// @[core.scala:135:32]\n wire [1:0] _iregister_read_io_exe_reqs_1_bits_uop_rxq_idx;\t// @[core.scala:135:32]\n wire [6:0] _iregister_read_io_exe_reqs_1_bits_uop_pdst;\t// @[core.scala:135:32]\n wire [6:0] _iregister_read_io_exe_reqs_1_bits_uop_prs1;\t// @[core.scala:135:32]\n wire [6:0] _iregister_read_io_exe_reqs_1_bits_uop_prs2;\t// @[core.scala:135:32]\n wire [6:0] _iregister_read_io_exe_reqs_1_bits_uop_prs3;\t// @[core.scala:135:32]\n wire [4:0] _iregister_read_io_exe_reqs_1_bits_uop_ppred;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_1_bits_uop_prs1_busy;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_1_bits_uop_prs2_busy;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_1_bits_uop_prs3_busy;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_1_bits_uop_ppred_busy;\t// @[core.scala:135:32]\n wire [6:0] _iregister_read_io_exe_reqs_1_bits_uop_stale_pdst;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_1_bits_uop_exception;\t// @[core.scala:135:32]\n wire [63:0] _iregister_read_io_exe_reqs_1_bits_uop_exc_cause;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_1_bits_uop_bypassable;\t// @[core.scala:135:32]\n wire [4:0] _iregister_read_io_exe_reqs_1_bits_uop_mem_cmd;\t// @[core.scala:135:32]\n wire [1:0] _iregister_read_io_exe_reqs_1_bits_uop_mem_size;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_1_bits_uop_mem_signed;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_1_bits_uop_is_fence;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_1_bits_uop_is_fencei;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_1_bits_uop_is_amo;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_1_bits_uop_uses_ldq;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_1_bits_uop_uses_stq;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_1_bits_uop_is_sys_pc2epc;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_1_bits_uop_is_unique;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_1_bits_uop_flush_on_commit;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_1_bits_uop_ldst_is_rs1;\t// @[core.scala:135:32]\n wire [5:0] _iregister_read_io_exe_reqs_1_bits_uop_ldst;\t// @[core.scala:135:32]\n wire [5:0] _iregister_read_io_exe_reqs_1_bits_uop_lrs1;\t// @[core.scala:135:32]\n wire [5:0] _iregister_read_io_exe_reqs_1_bits_uop_lrs2;\t// @[core.scala:135:32]\n wire [5:0] _iregister_read_io_exe_reqs_1_bits_uop_lrs3;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_1_bits_uop_ldst_val;\t// @[core.scala:135:32]\n wire [1:0] _iregister_read_io_exe_reqs_1_bits_uop_dst_rtype;\t// @[core.scala:135:32]\n wire [1:0] _iregister_read_io_exe_reqs_1_bits_uop_lrs1_rtype;\t// @[core.scala:135:32]\n wire [1:0] _iregister_read_io_exe_reqs_1_bits_uop_lrs2_rtype;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_1_bits_uop_frs3_en;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_1_bits_uop_fp_val;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_1_bits_uop_fp_single;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_1_bits_uop_xcpt_pf_if;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_1_bits_uop_xcpt_ae_if;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_1_bits_uop_xcpt_ma_if;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_1_bits_uop_bp_debug_if;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_1_bits_uop_bp_xcpt_if;\t// @[core.scala:135:32]\n wire [1:0] _iregister_read_io_exe_reqs_1_bits_uop_debug_fsrc;\t// @[core.scala:135:32]\n wire [1:0] _iregister_read_io_exe_reqs_1_bits_uop_debug_tsrc;\t// @[core.scala:135:32]\n wire [63:0] _iregister_read_io_exe_reqs_1_bits_rs1_data;\t// @[core.scala:135:32]\n wire [63:0] _iregister_read_io_exe_reqs_1_bits_rs2_data;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_2_valid;\t// @[core.scala:135:32]\n wire [6:0] _iregister_read_io_exe_reqs_2_bits_uop_uopc;\t// @[core.scala:135:32]\n wire [31:0] _iregister_read_io_exe_reqs_2_bits_uop_inst;\t// @[core.scala:135:32]\n wire [31:0] _iregister_read_io_exe_reqs_2_bits_uop_debug_inst;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_2_bits_uop_is_rvc;\t// @[core.scala:135:32]\n wire [39:0] _iregister_read_io_exe_reqs_2_bits_uop_debug_pc;\t// @[core.scala:135:32]\n wire [2:0] _iregister_read_io_exe_reqs_2_bits_uop_iq_type;\t// @[core.scala:135:32]\n wire [9:0] _iregister_read_io_exe_reqs_2_bits_uop_fu_code;\t// @[core.scala:135:32]\n wire [3:0] _iregister_read_io_exe_reqs_2_bits_uop_ctrl_br_type;\t// @[core.scala:135:32]\n wire [1:0] _iregister_read_io_exe_reqs_2_bits_uop_ctrl_op1_sel;\t// @[core.scala:135:32]\n wire [2:0] _iregister_read_io_exe_reqs_2_bits_uop_ctrl_op2_sel;\t// @[core.scala:135:32]\n wire [2:0] _iregister_read_io_exe_reqs_2_bits_uop_ctrl_imm_sel;\t// @[core.scala:135:32]\n wire [4:0] _iregister_read_io_exe_reqs_2_bits_uop_ctrl_op_fcn;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_2_bits_uop_ctrl_fcn_dw;\t// @[core.scala:135:32]\n wire [2:0] _iregister_read_io_exe_reqs_2_bits_uop_ctrl_csr_cmd;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_2_bits_uop_ctrl_is_load;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_2_bits_uop_ctrl_is_sta;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_2_bits_uop_ctrl_is_std;\t// @[core.scala:135:32]\n wire [1:0] _iregister_read_io_exe_reqs_2_bits_uop_iw_state;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_2_bits_uop_iw_p1_poisoned;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_2_bits_uop_iw_p2_poisoned;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_2_bits_uop_is_br;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_2_bits_uop_is_jalr;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_2_bits_uop_is_jal;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_2_bits_uop_is_sfb;\t// @[core.scala:135:32]\n wire [15:0] _iregister_read_io_exe_reqs_2_bits_uop_br_mask;\t// @[core.scala:135:32]\n wire [3:0] _iregister_read_io_exe_reqs_2_bits_uop_br_tag;\t// @[core.scala:135:32]\n wire [4:0] _iregister_read_io_exe_reqs_2_bits_uop_ftq_idx;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_2_bits_uop_edge_inst;\t// @[core.scala:135:32]\n wire [5:0] _iregister_read_io_exe_reqs_2_bits_uop_pc_lob;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_2_bits_uop_taken;\t// @[core.scala:135:32]\n wire [19:0] _iregister_read_io_exe_reqs_2_bits_uop_imm_packed;\t// @[core.scala:135:32]\n wire [11:0] _iregister_read_io_exe_reqs_2_bits_uop_csr_addr;\t// @[core.scala:135:32]\n wire [6:0] _iregister_read_io_exe_reqs_2_bits_uop_rob_idx;\t// @[core.scala:135:32]\n wire [4:0] _iregister_read_io_exe_reqs_2_bits_uop_ldq_idx;\t// @[core.scala:135:32]\n wire [4:0] _iregister_read_io_exe_reqs_2_bits_uop_stq_idx;\t// @[core.scala:135:32]\n wire [1:0] _iregister_read_io_exe_reqs_2_bits_uop_rxq_idx;\t// @[core.scala:135:32]\n wire [6:0] _iregister_read_io_exe_reqs_2_bits_uop_pdst;\t// @[core.scala:135:32]\n wire [6:0] _iregister_read_io_exe_reqs_2_bits_uop_prs1;\t// @[core.scala:135:32]\n wire [6:0] _iregister_read_io_exe_reqs_2_bits_uop_prs2;\t// @[core.scala:135:32]\n wire [6:0] _iregister_read_io_exe_reqs_2_bits_uop_prs3;\t// @[core.scala:135:32]\n wire [4:0] _iregister_read_io_exe_reqs_2_bits_uop_ppred;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_2_bits_uop_prs1_busy;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_2_bits_uop_prs2_busy;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_2_bits_uop_prs3_busy;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_2_bits_uop_ppred_busy;\t// @[core.scala:135:32]\n wire [6:0] _iregister_read_io_exe_reqs_2_bits_uop_stale_pdst;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_2_bits_uop_exception;\t// @[core.scala:135:32]\n wire [63:0] _iregister_read_io_exe_reqs_2_bits_uop_exc_cause;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_2_bits_uop_bypassable;\t// @[core.scala:135:32]\n wire [4:0] _iregister_read_io_exe_reqs_2_bits_uop_mem_cmd;\t// @[core.scala:135:32]\n wire [1:0] _iregister_read_io_exe_reqs_2_bits_uop_mem_size;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_2_bits_uop_mem_signed;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_2_bits_uop_is_fence;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_2_bits_uop_is_fencei;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_2_bits_uop_is_amo;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_2_bits_uop_uses_ldq;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_2_bits_uop_uses_stq;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_2_bits_uop_is_sys_pc2epc;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_2_bits_uop_is_unique;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_2_bits_uop_flush_on_commit;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_2_bits_uop_ldst_is_rs1;\t// @[core.scala:135:32]\n wire [5:0] _iregister_read_io_exe_reqs_2_bits_uop_ldst;\t// @[core.scala:135:32]\n wire [5:0] _iregister_read_io_exe_reqs_2_bits_uop_lrs1;\t// @[core.scala:135:32]\n wire [5:0] _iregister_read_io_exe_reqs_2_bits_uop_lrs2;\t// @[core.scala:135:32]\n wire [5:0] _iregister_read_io_exe_reqs_2_bits_uop_lrs3;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_2_bits_uop_ldst_val;\t// @[core.scala:135:32]\n wire [1:0] _iregister_read_io_exe_reqs_2_bits_uop_dst_rtype;\t// @[core.scala:135:32]\n wire [1:0] _iregister_read_io_exe_reqs_2_bits_uop_lrs1_rtype;\t// @[core.scala:135:32]\n wire [1:0] _iregister_read_io_exe_reqs_2_bits_uop_lrs2_rtype;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_2_bits_uop_frs3_en;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_2_bits_uop_fp_val;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_2_bits_uop_fp_single;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_2_bits_uop_xcpt_pf_if;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_2_bits_uop_xcpt_ae_if;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_2_bits_uop_xcpt_ma_if;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_2_bits_uop_bp_debug_if;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_2_bits_uop_bp_xcpt_if;\t// @[core.scala:135:32]\n wire [1:0] _iregister_read_io_exe_reqs_2_bits_uop_debug_fsrc;\t// @[core.scala:135:32]\n wire [1:0] _iregister_read_io_exe_reqs_2_bits_uop_debug_tsrc;\t// @[core.scala:135:32]\n wire [63:0] _iregister_read_io_exe_reqs_2_bits_rs1_data;\t// @[core.scala:135:32]\n wire [63:0] _iregister_read_io_exe_reqs_2_bits_rs2_data;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_3_valid;\t// @[core.scala:135:32]\n wire [6:0] _iregister_read_io_exe_reqs_3_bits_uop_uopc;\t// @[core.scala:135:32]\n wire [31:0] _iregister_read_io_exe_reqs_3_bits_uop_inst;\t// @[core.scala:135:32]\n wire [31:0] _iregister_read_io_exe_reqs_3_bits_uop_debug_inst;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_3_bits_uop_is_rvc;\t// @[core.scala:135:32]\n wire [39:0] _iregister_read_io_exe_reqs_3_bits_uop_debug_pc;\t// @[core.scala:135:32]\n wire [2:0] _iregister_read_io_exe_reqs_3_bits_uop_iq_type;\t// @[core.scala:135:32]\n wire [9:0] _iregister_read_io_exe_reqs_3_bits_uop_fu_code;\t// @[core.scala:135:32]\n wire [3:0] _iregister_read_io_exe_reqs_3_bits_uop_ctrl_br_type;\t// @[core.scala:135:32]\n wire [1:0] _iregister_read_io_exe_reqs_3_bits_uop_ctrl_op1_sel;\t// @[core.scala:135:32]\n wire [2:0] _iregister_read_io_exe_reqs_3_bits_uop_ctrl_op2_sel;\t// @[core.scala:135:32]\n wire [2:0] _iregister_read_io_exe_reqs_3_bits_uop_ctrl_imm_sel;\t// @[core.scala:135:32]\n wire [4:0] _iregister_read_io_exe_reqs_3_bits_uop_ctrl_op_fcn;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_3_bits_uop_ctrl_fcn_dw;\t// @[core.scala:135:32]\n wire [2:0] _iregister_read_io_exe_reqs_3_bits_uop_ctrl_csr_cmd;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_3_bits_uop_ctrl_is_load;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_3_bits_uop_ctrl_is_sta;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_3_bits_uop_ctrl_is_std;\t// @[core.scala:135:32]\n wire [1:0] _iregister_read_io_exe_reqs_3_bits_uop_iw_state;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_3_bits_uop_iw_p1_poisoned;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_3_bits_uop_iw_p2_poisoned;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_3_bits_uop_is_br;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_3_bits_uop_is_jalr;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_3_bits_uop_is_jal;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_3_bits_uop_is_sfb;\t// @[core.scala:135:32]\n wire [15:0] _iregister_read_io_exe_reqs_3_bits_uop_br_mask;\t// @[core.scala:135:32]\n wire [3:0] _iregister_read_io_exe_reqs_3_bits_uop_br_tag;\t// @[core.scala:135:32]\n wire [4:0] _iregister_read_io_exe_reqs_3_bits_uop_ftq_idx;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_3_bits_uop_edge_inst;\t// @[core.scala:135:32]\n wire [5:0] _iregister_read_io_exe_reqs_3_bits_uop_pc_lob;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_3_bits_uop_taken;\t// @[core.scala:135:32]\n wire [19:0] _iregister_read_io_exe_reqs_3_bits_uop_imm_packed;\t// @[core.scala:135:32]\n wire [11:0] _iregister_read_io_exe_reqs_3_bits_uop_csr_addr;\t// @[core.scala:135:32]\n wire [6:0] _iregister_read_io_exe_reqs_3_bits_uop_rob_idx;\t// @[core.scala:135:32]\n wire [4:0] _iregister_read_io_exe_reqs_3_bits_uop_ldq_idx;\t// @[core.scala:135:32]\n wire [4:0] _iregister_read_io_exe_reqs_3_bits_uop_stq_idx;\t// @[core.scala:135:32]\n wire [1:0] _iregister_read_io_exe_reqs_3_bits_uop_rxq_idx;\t// @[core.scala:135:32]\n wire [6:0] _iregister_read_io_exe_reqs_3_bits_uop_pdst;\t// @[core.scala:135:32]\n wire [6:0] _iregister_read_io_exe_reqs_3_bits_uop_prs1;\t// @[core.scala:135:32]\n wire [6:0] _iregister_read_io_exe_reqs_3_bits_uop_prs2;\t// @[core.scala:135:32]\n wire [6:0] _iregister_read_io_exe_reqs_3_bits_uop_prs3;\t// @[core.scala:135:32]\n wire [4:0] _iregister_read_io_exe_reqs_3_bits_uop_ppred;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_3_bits_uop_prs1_busy;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_3_bits_uop_prs2_busy;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_3_bits_uop_prs3_busy;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_3_bits_uop_ppred_busy;\t// @[core.scala:135:32]\n wire [6:0] _iregister_read_io_exe_reqs_3_bits_uop_stale_pdst;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_3_bits_uop_exception;\t// @[core.scala:135:32]\n wire [63:0] _iregister_read_io_exe_reqs_3_bits_uop_exc_cause;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_3_bits_uop_bypassable;\t// @[core.scala:135:32]\n wire [4:0] _iregister_read_io_exe_reqs_3_bits_uop_mem_cmd;\t// @[core.scala:135:32]\n wire [1:0] _iregister_read_io_exe_reqs_3_bits_uop_mem_size;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_3_bits_uop_mem_signed;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_3_bits_uop_is_fence;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_3_bits_uop_is_fencei;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_3_bits_uop_is_amo;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_3_bits_uop_uses_ldq;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_3_bits_uop_uses_stq;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_3_bits_uop_is_sys_pc2epc;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_3_bits_uop_is_unique;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_3_bits_uop_flush_on_commit;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_3_bits_uop_ldst_is_rs1;\t// @[core.scala:135:32]\n wire [5:0] _iregister_read_io_exe_reqs_3_bits_uop_ldst;\t// @[core.scala:135:32]\n wire [5:0] _iregister_read_io_exe_reqs_3_bits_uop_lrs1;\t// @[core.scala:135:32]\n wire [5:0] _iregister_read_io_exe_reqs_3_bits_uop_lrs2;\t// @[core.scala:135:32]\n wire [5:0] _iregister_read_io_exe_reqs_3_bits_uop_lrs3;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_3_bits_uop_ldst_val;\t// @[core.scala:135:32]\n wire [1:0] _iregister_read_io_exe_reqs_3_bits_uop_dst_rtype;\t// @[core.scala:135:32]\n wire [1:0] _iregister_read_io_exe_reqs_3_bits_uop_lrs1_rtype;\t// @[core.scala:135:32]\n wire [1:0] _iregister_read_io_exe_reqs_3_bits_uop_lrs2_rtype;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_3_bits_uop_frs3_en;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_3_bits_uop_fp_val;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_3_bits_uop_fp_single;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_3_bits_uop_xcpt_pf_if;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_3_bits_uop_xcpt_ae_if;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_3_bits_uop_xcpt_ma_if;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_3_bits_uop_bp_debug_if;\t// @[core.scala:135:32]\n wire _iregister_read_io_exe_reqs_3_bits_uop_bp_xcpt_if;\t// @[core.scala:135:32]\n wire [1:0] _iregister_read_io_exe_reqs_3_bits_uop_debug_fsrc;\t// @[core.scala:135:32]\n wire [1:0] _iregister_read_io_exe_reqs_3_bits_uop_debug_tsrc;\t// @[core.scala:135:32]\n wire [63:0] _iregister_read_io_exe_reqs_3_bits_rs1_data;\t// @[core.scala:135:32]\n wire [63:0] _iregister_read_io_exe_reqs_3_bits_rs2_data;\t// @[core.scala:135:32]\n wire _ll_wbarb_io_in_1_ready;\t// @[core.scala:132:32]\n wire _ll_wbarb_io_out_valid;\t// @[core.scala:132:32]\n wire [6:0] _ll_wbarb_io_out_bits_uop_uopc;\t// @[core.scala:132:32]\n wire [31:0] _ll_wbarb_io_out_bits_uop_inst;\t// @[core.scala:132:32]\n wire [31:0] _ll_wbarb_io_out_bits_uop_debug_inst;\t// @[core.scala:132:32]\n wire _ll_wbarb_io_out_bits_uop_is_rvc;\t// @[core.scala:132:32]\n wire [39:0] _ll_wbarb_io_out_bits_uop_debug_pc;\t// @[core.scala:132:32]\n wire [2:0] _ll_wbarb_io_out_bits_uop_iq_type;\t// @[core.scala:132:32]\n wire [9:0] _ll_wbarb_io_out_bits_uop_fu_code;\t// @[core.scala:132:32]\n wire [3:0] _ll_wbarb_io_out_bits_uop_ctrl_br_type;\t// @[core.scala:132:32]\n wire [1:0] _ll_wbarb_io_out_bits_uop_ctrl_op1_sel;\t// @[core.scala:132:32]\n wire [2:0] _ll_wbarb_io_out_bits_uop_ctrl_op2_sel;\t// @[core.scala:132:32]\n wire [2:0] _ll_wbarb_io_out_bits_uop_ctrl_imm_sel;\t// @[core.scala:132:32]\n wire [4:0] _ll_wbarb_io_out_bits_uop_ctrl_op_fcn;\t// @[core.scala:132:32]\n wire _ll_wbarb_io_out_bits_uop_ctrl_fcn_dw;\t// @[core.scala:132:32]\n wire [2:0] _ll_wbarb_io_out_bits_uop_ctrl_csr_cmd;\t// @[core.scala:132:32]\n wire _ll_wbarb_io_out_bits_uop_ctrl_is_load;\t// @[core.scala:132:32]\n wire _ll_wbarb_io_out_bits_uop_ctrl_is_sta;\t// @[core.scala:132:32]\n wire _ll_wbarb_io_out_bits_uop_ctrl_is_std;\t// @[core.scala:132:32]\n wire [1:0] _ll_wbarb_io_out_bits_uop_iw_state;\t// @[core.scala:132:32]\n wire _ll_wbarb_io_out_bits_uop_iw_p1_poisoned;\t// @[core.scala:132:32]\n wire _ll_wbarb_io_out_bits_uop_iw_p2_poisoned;\t// @[core.scala:132:32]\n wire _ll_wbarb_io_out_bits_uop_is_br;\t// @[core.scala:132:32]\n wire _ll_wbarb_io_out_bits_uop_is_jalr;\t// @[core.scala:132:32]\n wire _ll_wbarb_io_out_bits_uop_is_jal;\t// @[core.scala:132:32]\n wire _ll_wbarb_io_out_bits_uop_is_sfb;\t// @[core.scala:132:32]\n wire [15:0] _ll_wbarb_io_out_bits_uop_br_mask;\t// @[core.scala:132:32]\n wire [3:0] _ll_wbarb_io_out_bits_uop_br_tag;\t// @[core.scala:132:32]\n wire [4:0] _ll_wbarb_io_out_bits_uop_ftq_idx;\t// @[core.scala:132:32]\n wire _ll_wbarb_io_out_bits_uop_edge_inst;\t// @[core.scala:132:32]\n wire [5:0] _ll_wbarb_io_out_bits_uop_pc_lob;\t// @[core.scala:132:32]\n wire _ll_wbarb_io_out_bits_uop_taken;\t// @[core.scala:132:32]\n wire [19:0] _ll_wbarb_io_out_bits_uop_imm_packed;\t// @[core.scala:132:32]\n wire [11:0] _ll_wbarb_io_out_bits_uop_csr_addr;\t// @[core.scala:132:32]\n wire [6:0] _ll_wbarb_io_out_bits_uop_rob_idx;\t// @[core.scala:132:32]\n wire [4:0] _ll_wbarb_io_out_bits_uop_ldq_idx;\t// @[core.scala:132:32]\n wire [4:0] _ll_wbarb_io_out_bits_uop_stq_idx;\t// @[core.scala:132:32]\n wire [1:0] _ll_wbarb_io_out_bits_uop_rxq_idx;\t// @[core.scala:132:32]\n wire [6:0] _ll_wbarb_io_out_bits_uop_pdst;\t// @[core.scala:132:32]\n wire [6:0] _ll_wbarb_io_out_bits_uop_prs1;\t// @[core.scala:132:32]\n wire [6:0] _ll_wbarb_io_out_bits_uop_prs2;\t// @[core.scala:132:32]\n wire [6:0] _ll_wbarb_io_out_bits_uop_prs3;\t// @[core.scala:132:32]\n wire [4:0] _ll_wbarb_io_out_bits_uop_ppred;\t// @[core.scala:132:32]\n wire _ll_wbarb_io_out_bits_uop_prs1_busy;\t// @[core.scala:132:32]\n wire _ll_wbarb_io_out_bits_uop_prs2_busy;\t// @[core.scala:132:32]\n wire _ll_wbarb_io_out_bits_uop_prs3_busy;\t// @[core.scala:132:32]\n wire _ll_wbarb_io_out_bits_uop_ppred_busy;\t// @[core.scala:132:32]\n wire [6:0] _ll_wbarb_io_out_bits_uop_stale_pdst;\t// @[core.scala:132:32]\n wire _ll_wbarb_io_out_bits_uop_exception;\t// @[core.scala:132:32]\n wire [63:0] _ll_wbarb_io_out_bits_uop_exc_cause;\t// @[core.scala:132:32]\n wire _ll_wbarb_io_out_bits_uop_bypassable;\t// @[core.scala:132:32]\n wire [4:0] _ll_wbarb_io_out_bits_uop_mem_cmd;\t// @[core.scala:132:32]\n wire [1:0] _ll_wbarb_io_out_bits_uop_mem_size;\t// @[core.scala:132:32]\n wire _ll_wbarb_io_out_bits_uop_mem_signed;\t// @[core.scala:132:32]\n wire _ll_wbarb_io_out_bits_uop_is_fence;\t// @[core.scala:132:32]\n wire _ll_wbarb_io_out_bits_uop_is_fencei;\t// @[core.scala:132:32]\n wire _ll_wbarb_io_out_bits_uop_is_amo;\t// @[core.scala:132:32]\n wire _ll_wbarb_io_out_bits_uop_uses_ldq;\t// @[core.scala:132:32]\n wire _ll_wbarb_io_out_bits_uop_uses_stq;\t// @[core.scala:132:32]\n wire _ll_wbarb_io_out_bits_uop_is_sys_pc2epc;\t// @[core.scala:132:32]\n wire _ll_wbarb_io_out_bits_uop_is_unique;\t// @[core.scala:132:32]\n wire _ll_wbarb_io_out_bits_uop_flush_on_commit;\t// @[core.scala:132:32]\n wire _ll_wbarb_io_out_bits_uop_ldst_is_rs1;\t// @[core.scala:132:32]\n wire [5:0] _ll_wbarb_io_out_bits_uop_ldst;\t// @[core.scala:132:32]\n wire [5:0] _ll_wbarb_io_out_bits_uop_lrs1;\t// @[core.scala:132:32]\n wire [5:0] _ll_wbarb_io_out_bits_uop_lrs2;\t// @[core.scala:132:32]\n wire [5:0] _ll_wbarb_io_out_bits_uop_lrs3;\t// @[core.scala:132:32]\n wire _ll_wbarb_io_out_bits_uop_ldst_val;\t// @[core.scala:132:32]\n wire [1:0] _ll_wbarb_io_out_bits_uop_dst_rtype;\t// @[core.scala:132:32]\n wire [1:0] _ll_wbarb_io_out_bits_uop_lrs1_rtype;\t// @[core.scala:132:32]\n wire [1:0] _ll_wbarb_io_out_bits_uop_lrs2_rtype;\t// @[core.scala:132:32]\n wire _ll_wbarb_io_out_bits_uop_frs3_en;\t// @[core.scala:132:32]\n wire _ll_wbarb_io_out_bits_uop_fp_val;\t// @[core.scala:132:32]\n wire _ll_wbarb_io_out_bits_uop_fp_single;\t// @[core.scala:132:32]\n wire _ll_wbarb_io_out_bits_uop_xcpt_pf_if;\t// @[core.scala:132:32]\n wire _ll_wbarb_io_out_bits_uop_xcpt_ae_if;\t// @[core.scala:132:32]\n wire _ll_wbarb_io_out_bits_uop_xcpt_ma_if;\t// @[core.scala:132:32]\n wire _ll_wbarb_io_out_bits_uop_bp_debug_if;\t// @[core.scala:132:32]\n wire _ll_wbarb_io_out_bits_uop_bp_xcpt_if;\t// @[core.scala:132:32]\n wire [1:0] _ll_wbarb_io_out_bits_uop_debug_fsrc;\t// @[core.scala:132:32]\n wire [1:0] _ll_wbarb_io_out_bits_uop_debug_tsrc;\t// @[core.scala:132:32]\n wire [63:0] _ll_wbarb_io_out_bits_data;\t// @[core.scala:132:32]\n wire _ll_wbarb_io_out_bits_predicated;\t// @[core.scala:132:32]\n wire _ll_wbarb_io_out_bits_fflags_valid;\t// @[core.scala:132:32]\n wire [6:0] _ll_wbarb_io_out_bits_fflags_bits_uop_uopc;\t// @[core.scala:132:32]\n wire [31:0] _ll_wbarb_io_out_bits_fflags_bits_uop_inst;\t// @[core.scala:132:32]\n wire [31:0] _ll_wbarb_io_out_bits_fflags_bits_uop_debug_inst;\t// @[core.scala:132:32]\n wire _ll_wbarb_io_out_bits_fflags_bits_uop_is_rvc;\t// @[core.scala:132:32]\n wire [39:0] _ll_wbarb_io_out_bits_fflags_bits_uop_debug_pc;\t// @[core.scala:132:32]\n wire [2:0] _ll_wbarb_io_out_bits_fflags_bits_uop_iq_type;\t// @[core.scala:132:32]\n wire [9:0] _ll_wbarb_io_out_bits_fflags_bits_uop_fu_code;\t// @[core.scala:132:32]\n wire [3:0] _ll_wbarb_io_out_bits_fflags_bits_uop_ctrl_br_type;\t// @[core.scala:132:32]\n wire [1:0] _ll_wbarb_io_out_bits_fflags_bits_uop_ctrl_op1_sel;\t// @[core.scala:132:32]\n wire [2:0] _ll_wbarb_io_out_bits_fflags_bits_uop_ctrl_op2_sel;\t// @[core.scala:132:32]\n wire [2:0] _ll_wbarb_io_out_bits_fflags_bits_uop_ctrl_imm_sel;\t// @[core.scala:132:32]\n wire [4:0] _ll_wbarb_io_out_bits_fflags_bits_uop_ctrl_op_fcn;\t// @[core.scala:132:32]\n wire _ll_wbarb_io_out_bits_fflags_bits_uop_ctrl_fcn_dw;\t// @[core.scala:132:32]\n wire [2:0] _ll_wbarb_io_out_bits_fflags_bits_uop_ctrl_csr_cmd;\t// @[core.scala:132:32]\n wire _ll_wbarb_io_out_bits_fflags_bits_uop_ctrl_is_load;\t// @[core.scala:132:32]\n wire _ll_wbarb_io_out_bits_fflags_bits_uop_ctrl_is_sta;\t// @[core.scala:132:32]\n wire _ll_wbarb_io_out_bits_fflags_bits_uop_ctrl_is_std;\t// @[core.scala:132:32]\n wire [1:0] _ll_wbarb_io_out_bits_fflags_bits_uop_iw_state;\t// @[core.scala:132:32]\n wire _ll_wbarb_io_out_bits_fflags_bits_uop_iw_p1_poisoned;\t// @[core.scala:132:32]\n wire _ll_wbarb_io_out_bits_fflags_bits_uop_iw_p2_poisoned;\t// @[core.scala:132:32]\n wire _ll_wbarb_io_out_bits_fflags_bits_uop_is_br;\t// @[core.scala:132:32]\n wire _ll_wbarb_io_out_bits_fflags_bits_uop_is_jalr;\t// @[core.scala:132:32]\n wire _ll_wbarb_io_out_bits_fflags_bits_uop_is_jal;\t// @[core.scala:132:32]\n wire _ll_wbarb_io_out_bits_fflags_bits_uop_is_sfb;\t// @[core.scala:132:32]\n wire [15:0] _ll_wbarb_io_out_bits_fflags_bits_uop_br_mask;\t// @[core.scala:132:32]\n wire [3:0] _ll_wbarb_io_out_bits_fflags_bits_uop_br_tag;\t// @[core.scala:132:32]\n wire [4:0] _ll_wbarb_io_out_bits_fflags_bits_uop_ftq_idx;\t// @[core.scala:132:32]\n wire _ll_wbarb_io_out_bits_fflags_bits_uop_edge_inst;\t// @[core.scala:132:32]\n wire [5:0] _ll_wbarb_io_out_bits_fflags_bits_uop_pc_lob;\t// @[core.scala:132:32]\n wire _ll_wbarb_io_out_bits_fflags_bits_uop_taken;\t// @[core.scala:132:32]\n wire [19:0] _ll_wbarb_io_out_bits_fflags_bits_uop_imm_packed;\t// @[core.scala:132:32]\n wire [11:0] _ll_wbarb_io_out_bits_fflags_bits_uop_csr_addr;\t// @[core.scala:132:32]\n wire [6:0] _ll_wbarb_io_out_bits_fflags_bits_uop_rob_idx;\t// @[core.scala:132:32]\n wire [4:0] _ll_wbarb_io_out_bits_fflags_bits_uop_ldq_idx;\t// @[core.scala:132:32]\n wire [4:0] _ll_wbarb_io_out_bits_fflags_bits_uop_stq_idx;\t// @[core.scala:132:32]\n wire [1:0] _ll_wbarb_io_out_bits_fflags_bits_uop_rxq_idx;\t// @[core.scala:132:32]\n wire [6:0] _ll_wbarb_io_out_bits_fflags_bits_uop_pdst;\t// @[core.scala:132:32]\n wire [6:0] _ll_wbarb_io_out_bits_fflags_bits_uop_prs1;\t// @[core.scala:132:32]\n wire [6:0] _ll_wbarb_io_out_bits_fflags_bits_uop_prs2;\t// @[core.scala:132:32]\n wire [6:0] _ll_wbarb_io_out_bits_fflags_bits_uop_prs3;\t// @[core.scala:132:32]\n wire [4:0] _ll_wbarb_io_out_bits_fflags_bits_uop_ppred;\t// @[core.scala:132:32]\n wire _ll_wbarb_io_out_bits_fflags_bits_uop_prs1_busy;\t// @[core.scala:132:32]\n wire _ll_wbarb_io_out_bits_fflags_bits_uop_prs2_busy;\t// @[core.scala:132:32]\n wire _ll_wbarb_io_out_bits_fflags_bits_uop_prs3_busy;\t// @[core.scala:132:32]\n wire _ll_wbarb_io_out_bits_fflags_bits_uop_ppred_busy;\t// @[core.scala:132:32]\n wire [6:0] _ll_wbarb_io_out_bits_fflags_bits_uop_stale_pdst;\t// @[core.scala:132:32]\n wire _ll_wbarb_io_out_bits_fflags_bits_uop_exception;\t// @[core.scala:132:32]\n wire [63:0] _ll_wbarb_io_out_bits_fflags_bits_uop_exc_cause;\t// @[core.scala:132:32]\n wire _ll_wbarb_io_out_bits_fflags_bits_uop_bypassable;\t// @[core.scala:132:32]\n wire [4:0] _ll_wbarb_io_out_bits_fflags_bits_uop_mem_cmd;\t// @[core.scala:132:32]\n wire [1:0] _ll_wbarb_io_out_bits_fflags_bits_uop_mem_size;\t// @[core.scala:132:32]\n wire _ll_wbarb_io_out_bits_fflags_bits_uop_mem_signed;\t// @[core.scala:132:32]\n wire _ll_wbarb_io_out_bits_fflags_bits_uop_is_fence;\t// @[core.scala:132:32]\n wire _ll_wbarb_io_out_bits_fflags_bits_uop_is_fencei;\t// @[core.scala:132:32]\n wire _ll_wbarb_io_out_bits_fflags_bits_uop_is_amo;\t// @[core.scala:132:32]\n wire _ll_wbarb_io_out_bits_fflags_bits_uop_uses_ldq;\t// @[core.scala:132:32]\n wire _ll_wbarb_io_out_bits_fflags_bits_uop_uses_stq;\t// @[core.scala:132:32]\n wire _ll_wbarb_io_out_bits_fflags_bits_uop_is_sys_pc2epc;\t// @[core.scala:132:32]\n wire _ll_wbarb_io_out_bits_fflags_bits_uop_is_unique;\t// @[core.scala:132:32]\n wire _ll_wbarb_io_out_bits_fflags_bits_uop_flush_on_commit;\t// @[core.scala:132:32]\n wire _ll_wbarb_io_out_bits_fflags_bits_uop_ldst_is_rs1;\t// @[core.scala:132:32]\n wire [5:0] _ll_wbarb_io_out_bits_fflags_bits_uop_ldst;\t// @[core.scala:132:32]\n wire [5:0] _ll_wbarb_io_out_bits_fflags_bits_uop_lrs1;\t// @[core.scala:132:32]\n wire [5:0] _ll_wbarb_io_out_bits_fflags_bits_uop_lrs2;\t// @[core.scala:132:32]\n wire [5:0] _ll_wbarb_io_out_bits_fflags_bits_uop_lrs3;\t// @[core.scala:132:32]\n wire _ll_wbarb_io_out_bits_fflags_bits_uop_ldst_val;\t// @[core.scala:132:32]\n wire [1:0] _ll_wbarb_io_out_bits_fflags_bits_uop_dst_rtype;\t// @[core.scala:132:32]\n wire [1:0] _ll_wbarb_io_out_bits_fflags_bits_uop_lrs1_rtype;\t// @[core.scala:132:32]\n wire [1:0] _ll_wbarb_io_out_bits_fflags_bits_uop_lrs2_rtype;\t// @[core.scala:132:32]\n wire _ll_wbarb_io_out_bits_fflags_bits_uop_frs3_en;\t// @[core.scala:132:32]\n wire _ll_wbarb_io_out_bits_fflags_bits_uop_fp_val;\t// @[core.scala:132:32]\n wire _ll_wbarb_io_out_bits_fflags_bits_uop_fp_single;\t// @[core.scala:132:32]\n wire _ll_wbarb_io_out_bits_fflags_bits_uop_xcpt_pf_if;\t// @[core.scala:132:32]\n wire _ll_wbarb_io_out_bits_fflags_bits_uop_xcpt_ae_if;\t// @[core.scala:132:32]\n wire _ll_wbarb_io_out_bits_fflags_bits_uop_xcpt_ma_if;\t// @[core.scala:132:32]\n wire _ll_wbarb_io_out_bits_fflags_bits_uop_bp_debug_if;\t// @[core.scala:132:32]\n wire _ll_wbarb_io_out_bits_fflags_bits_uop_bp_xcpt_if;\t// @[core.scala:132:32]\n wire [1:0] _ll_wbarb_io_out_bits_fflags_bits_uop_debug_fsrc;\t// @[core.scala:132:32]\n wire [1:0] _ll_wbarb_io_out_bits_fflags_bits_uop_debug_tsrc;\t// @[core.scala:132:32]\n wire [4:0] _ll_wbarb_io_out_bits_fflags_bits_flags;\t// @[core.scala:132:32]\n wire [63:0] _iregfile_io_read_ports_0_data;\t// @[core.scala:116:32]\n wire [63:0] _iregfile_io_read_ports_1_data;\t// @[core.scala:116:32]\n wire [63:0] _iregfile_io_read_ports_2_data;\t// @[core.scala:116:32]\n wire [63:0] _iregfile_io_read_ports_3_data;\t// @[core.scala:116:32]\n wire [63:0] _iregfile_io_read_ports_4_data;\t// @[core.scala:116:32]\n wire [63:0] _iregfile_io_read_ports_5_data;\t// @[core.scala:116:32]\n wire [63:0] _iregfile_io_read_ports_6_data;\t// @[core.scala:116:32]\n wire [63:0] _iregfile_io_read_ports_7_data;\t// @[core.scala:116:32]\n wire _dispatcher_io_ren_uops_0_ready;\t// @[core.scala:114:32]\n wire _dispatcher_io_ren_uops_1_ready;\t// @[core.scala:114:32]\n wire _dispatcher_io_ren_uops_2_ready;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_0_valid;\t// @[core.scala:114:32]\n wire [6:0] _dispatcher_io_dis_uops_2_0_bits_uopc;\t// @[core.scala:114:32]\n wire [31:0] _dispatcher_io_dis_uops_2_0_bits_inst;\t// @[core.scala:114:32]\n wire [31:0] _dispatcher_io_dis_uops_2_0_bits_debug_inst;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_0_bits_is_rvc;\t// @[core.scala:114:32]\n wire [39:0] _dispatcher_io_dis_uops_2_0_bits_debug_pc;\t// @[core.scala:114:32]\n wire [2:0] _dispatcher_io_dis_uops_2_0_bits_iq_type;\t// @[core.scala:114:32]\n wire [9:0] _dispatcher_io_dis_uops_2_0_bits_fu_code;\t// @[core.scala:114:32]\n wire [3:0] _dispatcher_io_dis_uops_2_0_bits_ctrl_br_type;\t// @[core.scala:114:32]\n wire [1:0] _dispatcher_io_dis_uops_2_0_bits_ctrl_op1_sel;\t// @[core.scala:114:32]\n wire [2:0] _dispatcher_io_dis_uops_2_0_bits_ctrl_op2_sel;\t// @[core.scala:114:32]\n wire [2:0] _dispatcher_io_dis_uops_2_0_bits_ctrl_imm_sel;\t// @[core.scala:114:32]\n wire [4:0] _dispatcher_io_dis_uops_2_0_bits_ctrl_op_fcn;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_0_bits_ctrl_fcn_dw;\t// @[core.scala:114:32]\n wire [2:0] _dispatcher_io_dis_uops_2_0_bits_ctrl_csr_cmd;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_0_bits_ctrl_is_load;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_0_bits_ctrl_is_sta;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_0_bits_ctrl_is_std;\t// @[core.scala:114:32]\n wire [1:0] _dispatcher_io_dis_uops_2_0_bits_iw_state;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_0_bits_iw_p1_poisoned;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_0_bits_iw_p2_poisoned;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_0_bits_is_br;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_0_bits_is_jalr;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_0_bits_is_jal;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_0_bits_is_sfb;\t// @[core.scala:114:32]\n wire [15:0] _dispatcher_io_dis_uops_2_0_bits_br_mask;\t// @[core.scala:114:32]\n wire [3:0] _dispatcher_io_dis_uops_2_0_bits_br_tag;\t// @[core.scala:114:32]\n wire [4:0] _dispatcher_io_dis_uops_2_0_bits_ftq_idx;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_0_bits_edge_inst;\t// @[core.scala:114:32]\n wire [5:0] _dispatcher_io_dis_uops_2_0_bits_pc_lob;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_0_bits_taken;\t// @[core.scala:114:32]\n wire [19:0] _dispatcher_io_dis_uops_2_0_bits_imm_packed;\t// @[core.scala:114:32]\n wire [11:0] _dispatcher_io_dis_uops_2_0_bits_csr_addr;\t// @[core.scala:114:32]\n wire [6:0] _dispatcher_io_dis_uops_2_0_bits_rob_idx;\t// @[core.scala:114:32]\n wire [4:0] _dispatcher_io_dis_uops_2_0_bits_ldq_idx;\t// @[core.scala:114:32]\n wire [4:0] _dispatcher_io_dis_uops_2_0_bits_stq_idx;\t// @[core.scala:114:32]\n wire [1:0] _dispatcher_io_dis_uops_2_0_bits_rxq_idx;\t// @[core.scala:114:32]\n wire [6:0] _dispatcher_io_dis_uops_2_0_bits_pdst;\t// @[core.scala:114:32]\n wire [6:0] _dispatcher_io_dis_uops_2_0_bits_prs1;\t// @[core.scala:114:32]\n wire [6:0] _dispatcher_io_dis_uops_2_0_bits_prs2;\t// @[core.scala:114:32]\n wire [6:0] _dispatcher_io_dis_uops_2_0_bits_prs3;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_0_bits_prs1_busy;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_0_bits_prs2_busy;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_0_bits_prs3_busy;\t// @[core.scala:114:32]\n wire [6:0] _dispatcher_io_dis_uops_2_0_bits_stale_pdst;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_0_bits_exception;\t// @[core.scala:114:32]\n wire [63:0] _dispatcher_io_dis_uops_2_0_bits_exc_cause;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_0_bits_bypassable;\t// @[core.scala:114:32]\n wire [4:0] _dispatcher_io_dis_uops_2_0_bits_mem_cmd;\t// @[core.scala:114:32]\n wire [1:0] _dispatcher_io_dis_uops_2_0_bits_mem_size;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_0_bits_mem_signed;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_0_bits_is_fence;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_0_bits_is_fencei;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_0_bits_is_amo;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_0_bits_uses_ldq;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_0_bits_uses_stq;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_0_bits_is_sys_pc2epc;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_0_bits_is_unique;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_0_bits_flush_on_commit;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_0_bits_ldst_is_rs1;\t// @[core.scala:114:32]\n wire [5:0] _dispatcher_io_dis_uops_2_0_bits_ldst;\t// @[core.scala:114:32]\n wire [5:0] _dispatcher_io_dis_uops_2_0_bits_lrs1;\t// @[core.scala:114:32]\n wire [5:0] _dispatcher_io_dis_uops_2_0_bits_lrs2;\t// @[core.scala:114:32]\n wire [5:0] _dispatcher_io_dis_uops_2_0_bits_lrs3;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_0_bits_ldst_val;\t// @[core.scala:114:32]\n wire [1:0] _dispatcher_io_dis_uops_2_0_bits_dst_rtype;\t// @[core.scala:114:32]\n wire [1:0] _dispatcher_io_dis_uops_2_0_bits_lrs1_rtype;\t// @[core.scala:114:32]\n wire [1:0] _dispatcher_io_dis_uops_2_0_bits_lrs2_rtype;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_0_bits_frs3_en;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_0_bits_fp_val;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_0_bits_fp_single;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_0_bits_xcpt_pf_if;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_0_bits_xcpt_ae_if;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_0_bits_xcpt_ma_if;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_0_bits_bp_debug_if;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_0_bits_bp_xcpt_if;\t// @[core.scala:114:32]\n wire [1:0] _dispatcher_io_dis_uops_2_0_bits_debug_fsrc;\t// @[core.scala:114:32]\n wire [1:0] _dispatcher_io_dis_uops_2_0_bits_debug_tsrc;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_1_valid;\t// @[core.scala:114:32]\n wire [6:0] _dispatcher_io_dis_uops_2_1_bits_uopc;\t// @[core.scala:114:32]\n wire [31:0] _dispatcher_io_dis_uops_2_1_bits_inst;\t// @[core.scala:114:32]\n wire [31:0] _dispatcher_io_dis_uops_2_1_bits_debug_inst;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_1_bits_is_rvc;\t// @[core.scala:114:32]\n wire [39:0] _dispatcher_io_dis_uops_2_1_bits_debug_pc;\t// @[core.scala:114:32]\n wire [2:0] _dispatcher_io_dis_uops_2_1_bits_iq_type;\t// @[core.scala:114:32]\n wire [9:0] _dispatcher_io_dis_uops_2_1_bits_fu_code;\t// @[core.scala:114:32]\n wire [3:0] _dispatcher_io_dis_uops_2_1_bits_ctrl_br_type;\t// @[core.scala:114:32]\n wire [1:0] _dispatcher_io_dis_uops_2_1_bits_ctrl_op1_sel;\t// @[core.scala:114:32]\n wire [2:0] _dispatcher_io_dis_uops_2_1_bits_ctrl_op2_sel;\t// @[core.scala:114:32]\n wire [2:0] _dispatcher_io_dis_uops_2_1_bits_ctrl_imm_sel;\t// @[core.scala:114:32]\n wire [4:0] _dispatcher_io_dis_uops_2_1_bits_ctrl_op_fcn;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_1_bits_ctrl_fcn_dw;\t// @[core.scala:114:32]\n wire [2:0] _dispatcher_io_dis_uops_2_1_bits_ctrl_csr_cmd;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_1_bits_ctrl_is_load;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_1_bits_ctrl_is_sta;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_1_bits_ctrl_is_std;\t// @[core.scala:114:32]\n wire [1:0] _dispatcher_io_dis_uops_2_1_bits_iw_state;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_1_bits_iw_p1_poisoned;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_1_bits_iw_p2_poisoned;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_1_bits_is_br;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_1_bits_is_jalr;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_1_bits_is_jal;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_1_bits_is_sfb;\t// @[core.scala:114:32]\n wire [15:0] _dispatcher_io_dis_uops_2_1_bits_br_mask;\t// @[core.scala:114:32]\n wire [3:0] _dispatcher_io_dis_uops_2_1_bits_br_tag;\t// @[core.scala:114:32]\n wire [4:0] _dispatcher_io_dis_uops_2_1_bits_ftq_idx;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_1_bits_edge_inst;\t// @[core.scala:114:32]\n wire [5:0] _dispatcher_io_dis_uops_2_1_bits_pc_lob;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_1_bits_taken;\t// @[core.scala:114:32]\n wire [19:0] _dispatcher_io_dis_uops_2_1_bits_imm_packed;\t// @[core.scala:114:32]\n wire [11:0] _dispatcher_io_dis_uops_2_1_bits_csr_addr;\t// @[core.scala:114:32]\n wire [6:0] _dispatcher_io_dis_uops_2_1_bits_rob_idx;\t// @[core.scala:114:32]\n wire [4:0] _dispatcher_io_dis_uops_2_1_bits_ldq_idx;\t// @[core.scala:114:32]\n wire [4:0] _dispatcher_io_dis_uops_2_1_bits_stq_idx;\t// @[core.scala:114:32]\n wire [1:0] _dispatcher_io_dis_uops_2_1_bits_rxq_idx;\t// @[core.scala:114:32]\n wire [6:0] _dispatcher_io_dis_uops_2_1_bits_pdst;\t// @[core.scala:114:32]\n wire [6:0] _dispatcher_io_dis_uops_2_1_bits_prs1;\t// @[core.scala:114:32]\n wire [6:0] _dispatcher_io_dis_uops_2_1_bits_prs2;\t// @[core.scala:114:32]\n wire [6:0] _dispatcher_io_dis_uops_2_1_bits_prs3;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_1_bits_prs1_busy;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_1_bits_prs2_busy;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_1_bits_prs3_busy;\t// @[core.scala:114:32]\n wire [6:0] _dispatcher_io_dis_uops_2_1_bits_stale_pdst;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_1_bits_exception;\t// @[core.scala:114:32]\n wire [63:0] _dispatcher_io_dis_uops_2_1_bits_exc_cause;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_1_bits_bypassable;\t// @[core.scala:114:32]\n wire [4:0] _dispatcher_io_dis_uops_2_1_bits_mem_cmd;\t// @[core.scala:114:32]\n wire [1:0] _dispatcher_io_dis_uops_2_1_bits_mem_size;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_1_bits_mem_signed;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_1_bits_is_fence;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_1_bits_is_fencei;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_1_bits_is_amo;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_1_bits_uses_ldq;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_1_bits_uses_stq;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_1_bits_is_sys_pc2epc;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_1_bits_is_unique;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_1_bits_flush_on_commit;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_1_bits_ldst_is_rs1;\t// @[core.scala:114:32]\n wire [5:0] _dispatcher_io_dis_uops_2_1_bits_ldst;\t// @[core.scala:114:32]\n wire [5:0] _dispatcher_io_dis_uops_2_1_bits_lrs1;\t// @[core.scala:114:32]\n wire [5:0] _dispatcher_io_dis_uops_2_1_bits_lrs2;\t// @[core.scala:114:32]\n wire [5:0] _dispatcher_io_dis_uops_2_1_bits_lrs3;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_1_bits_ldst_val;\t// @[core.scala:114:32]\n wire [1:0] _dispatcher_io_dis_uops_2_1_bits_dst_rtype;\t// @[core.scala:114:32]\n wire [1:0] _dispatcher_io_dis_uops_2_1_bits_lrs1_rtype;\t// @[core.scala:114:32]\n wire [1:0] _dispatcher_io_dis_uops_2_1_bits_lrs2_rtype;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_1_bits_frs3_en;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_1_bits_fp_val;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_1_bits_fp_single;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_1_bits_xcpt_pf_if;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_1_bits_xcpt_ae_if;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_1_bits_xcpt_ma_if;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_1_bits_bp_debug_if;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_1_bits_bp_xcpt_if;\t// @[core.scala:114:32]\n wire [1:0] _dispatcher_io_dis_uops_2_1_bits_debug_fsrc;\t// @[core.scala:114:32]\n wire [1:0] _dispatcher_io_dis_uops_2_1_bits_debug_tsrc;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_2_valid;\t// @[core.scala:114:32]\n wire [6:0] _dispatcher_io_dis_uops_2_2_bits_uopc;\t// @[core.scala:114:32]\n wire [31:0] _dispatcher_io_dis_uops_2_2_bits_inst;\t// @[core.scala:114:32]\n wire [31:0] _dispatcher_io_dis_uops_2_2_bits_debug_inst;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_2_bits_is_rvc;\t// @[core.scala:114:32]\n wire [39:0] _dispatcher_io_dis_uops_2_2_bits_debug_pc;\t// @[core.scala:114:32]\n wire [2:0] _dispatcher_io_dis_uops_2_2_bits_iq_type;\t// @[core.scala:114:32]\n wire [9:0] _dispatcher_io_dis_uops_2_2_bits_fu_code;\t// @[core.scala:114:32]\n wire [3:0] _dispatcher_io_dis_uops_2_2_bits_ctrl_br_type;\t// @[core.scala:114:32]\n wire [1:0] _dispatcher_io_dis_uops_2_2_bits_ctrl_op1_sel;\t// @[core.scala:114:32]\n wire [2:0] _dispatcher_io_dis_uops_2_2_bits_ctrl_op2_sel;\t// @[core.scala:114:32]\n wire [2:0] _dispatcher_io_dis_uops_2_2_bits_ctrl_imm_sel;\t// @[core.scala:114:32]\n wire [4:0] _dispatcher_io_dis_uops_2_2_bits_ctrl_op_fcn;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_2_bits_ctrl_fcn_dw;\t// @[core.scala:114:32]\n wire [2:0] _dispatcher_io_dis_uops_2_2_bits_ctrl_csr_cmd;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_2_bits_ctrl_is_load;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_2_bits_ctrl_is_sta;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_2_bits_ctrl_is_std;\t// @[core.scala:114:32]\n wire [1:0] _dispatcher_io_dis_uops_2_2_bits_iw_state;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_2_bits_iw_p1_poisoned;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_2_bits_iw_p2_poisoned;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_2_bits_is_br;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_2_bits_is_jalr;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_2_bits_is_jal;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_2_bits_is_sfb;\t// @[core.scala:114:32]\n wire [15:0] _dispatcher_io_dis_uops_2_2_bits_br_mask;\t// @[core.scala:114:32]\n wire [3:0] _dispatcher_io_dis_uops_2_2_bits_br_tag;\t// @[core.scala:114:32]\n wire [4:0] _dispatcher_io_dis_uops_2_2_bits_ftq_idx;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_2_bits_edge_inst;\t// @[core.scala:114:32]\n wire [5:0] _dispatcher_io_dis_uops_2_2_bits_pc_lob;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_2_bits_taken;\t// @[core.scala:114:32]\n wire [19:0] _dispatcher_io_dis_uops_2_2_bits_imm_packed;\t// @[core.scala:114:32]\n wire [11:0] _dispatcher_io_dis_uops_2_2_bits_csr_addr;\t// @[core.scala:114:32]\n wire [6:0] _dispatcher_io_dis_uops_2_2_bits_rob_idx;\t// @[core.scala:114:32]\n wire [4:0] _dispatcher_io_dis_uops_2_2_bits_ldq_idx;\t// @[core.scala:114:32]\n wire [4:0] _dispatcher_io_dis_uops_2_2_bits_stq_idx;\t// @[core.scala:114:32]\n wire [1:0] _dispatcher_io_dis_uops_2_2_bits_rxq_idx;\t// @[core.scala:114:32]\n wire [6:0] _dispatcher_io_dis_uops_2_2_bits_pdst;\t// @[core.scala:114:32]\n wire [6:0] _dispatcher_io_dis_uops_2_2_bits_prs1;\t// @[core.scala:114:32]\n wire [6:0] _dispatcher_io_dis_uops_2_2_bits_prs2;\t// @[core.scala:114:32]\n wire [6:0] _dispatcher_io_dis_uops_2_2_bits_prs3;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_2_bits_prs1_busy;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_2_bits_prs2_busy;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_2_bits_prs3_busy;\t// @[core.scala:114:32]\n wire [6:0] _dispatcher_io_dis_uops_2_2_bits_stale_pdst;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_2_bits_exception;\t// @[core.scala:114:32]\n wire [63:0] _dispatcher_io_dis_uops_2_2_bits_exc_cause;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_2_bits_bypassable;\t// @[core.scala:114:32]\n wire [4:0] _dispatcher_io_dis_uops_2_2_bits_mem_cmd;\t// @[core.scala:114:32]\n wire [1:0] _dispatcher_io_dis_uops_2_2_bits_mem_size;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_2_bits_mem_signed;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_2_bits_is_fence;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_2_bits_is_fencei;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_2_bits_is_amo;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_2_bits_uses_ldq;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_2_bits_uses_stq;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_2_bits_is_sys_pc2epc;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_2_bits_is_unique;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_2_bits_flush_on_commit;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_2_bits_ldst_is_rs1;\t// @[core.scala:114:32]\n wire [5:0] _dispatcher_io_dis_uops_2_2_bits_ldst;\t// @[core.scala:114:32]\n wire [5:0] _dispatcher_io_dis_uops_2_2_bits_lrs1;\t// @[core.scala:114:32]\n wire [5:0] _dispatcher_io_dis_uops_2_2_bits_lrs2;\t// @[core.scala:114:32]\n wire [5:0] _dispatcher_io_dis_uops_2_2_bits_lrs3;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_2_bits_ldst_val;\t// @[core.scala:114:32]\n wire [1:0] _dispatcher_io_dis_uops_2_2_bits_dst_rtype;\t// @[core.scala:114:32]\n wire [1:0] _dispatcher_io_dis_uops_2_2_bits_lrs1_rtype;\t// @[core.scala:114:32]\n wire [1:0] _dispatcher_io_dis_uops_2_2_bits_lrs2_rtype;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_2_bits_frs3_en;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_2_bits_fp_val;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_2_bits_fp_single;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_2_bits_xcpt_pf_if;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_2_bits_xcpt_ae_if;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_2_bits_xcpt_ma_if;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_2_bits_bp_debug_if;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_2_2_bits_bp_xcpt_if;\t// @[core.scala:114:32]\n wire [1:0] _dispatcher_io_dis_uops_2_2_bits_debug_fsrc;\t// @[core.scala:114:32]\n wire [1:0] _dispatcher_io_dis_uops_2_2_bits_debug_tsrc;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_0_valid;\t// @[core.scala:114:32]\n wire [6:0] _dispatcher_io_dis_uops_1_0_bits_uopc;\t// @[core.scala:114:32]\n wire [31:0] _dispatcher_io_dis_uops_1_0_bits_inst;\t// @[core.scala:114:32]\n wire [31:0] _dispatcher_io_dis_uops_1_0_bits_debug_inst;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_0_bits_is_rvc;\t// @[core.scala:114:32]\n wire [39:0] _dispatcher_io_dis_uops_1_0_bits_debug_pc;\t// @[core.scala:114:32]\n wire [2:0] _dispatcher_io_dis_uops_1_0_bits_iq_type;\t// @[core.scala:114:32]\n wire [9:0] _dispatcher_io_dis_uops_1_0_bits_fu_code;\t// @[core.scala:114:32]\n wire [3:0] _dispatcher_io_dis_uops_1_0_bits_ctrl_br_type;\t// @[core.scala:114:32]\n wire [1:0] _dispatcher_io_dis_uops_1_0_bits_ctrl_op1_sel;\t// @[core.scala:114:32]\n wire [2:0] _dispatcher_io_dis_uops_1_0_bits_ctrl_op2_sel;\t// @[core.scala:114:32]\n wire [2:0] _dispatcher_io_dis_uops_1_0_bits_ctrl_imm_sel;\t// @[core.scala:114:32]\n wire [4:0] _dispatcher_io_dis_uops_1_0_bits_ctrl_op_fcn;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_0_bits_ctrl_fcn_dw;\t// @[core.scala:114:32]\n wire [2:0] _dispatcher_io_dis_uops_1_0_bits_ctrl_csr_cmd;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_0_bits_ctrl_is_load;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_0_bits_ctrl_is_sta;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_0_bits_ctrl_is_std;\t// @[core.scala:114:32]\n wire [1:0] _dispatcher_io_dis_uops_1_0_bits_iw_state;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_0_bits_iw_p1_poisoned;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_0_bits_iw_p2_poisoned;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_0_bits_is_br;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_0_bits_is_jalr;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_0_bits_is_jal;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_0_bits_is_sfb;\t// @[core.scala:114:32]\n wire [15:0] _dispatcher_io_dis_uops_1_0_bits_br_mask;\t// @[core.scala:114:32]\n wire [3:0] _dispatcher_io_dis_uops_1_0_bits_br_tag;\t// @[core.scala:114:32]\n wire [4:0] _dispatcher_io_dis_uops_1_0_bits_ftq_idx;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_0_bits_edge_inst;\t// @[core.scala:114:32]\n wire [5:0] _dispatcher_io_dis_uops_1_0_bits_pc_lob;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_0_bits_taken;\t// @[core.scala:114:32]\n wire [19:0] _dispatcher_io_dis_uops_1_0_bits_imm_packed;\t// @[core.scala:114:32]\n wire [11:0] _dispatcher_io_dis_uops_1_0_bits_csr_addr;\t// @[core.scala:114:32]\n wire [6:0] _dispatcher_io_dis_uops_1_0_bits_rob_idx;\t// @[core.scala:114:32]\n wire [4:0] _dispatcher_io_dis_uops_1_0_bits_ldq_idx;\t// @[core.scala:114:32]\n wire [4:0] _dispatcher_io_dis_uops_1_0_bits_stq_idx;\t// @[core.scala:114:32]\n wire [1:0] _dispatcher_io_dis_uops_1_0_bits_rxq_idx;\t// @[core.scala:114:32]\n wire [6:0] _dispatcher_io_dis_uops_1_0_bits_pdst;\t// @[core.scala:114:32]\n wire [6:0] _dispatcher_io_dis_uops_1_0_bits_prs1;\t// @[core.scala:114:32]\n wire [6:0] _dispatcher_io_dis_uops_1_0_bits_prs2;\t// @[core.scala:114:32]\n wire [6:0] _dispatcher_io_dis_uops_1_0_bits_prs3;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_0_bits_prs1_busy;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_0_bits_prs2_busy;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_0_bits_prs3_busy;\t// @[core.scala:114:32]\n wire [6:0] _dispatcher_io_dis_uops_1_0_bits_stale_pdst;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_0_bits_exception;\t// @[core.scala:114:32]\n wire [63:0] _dispatcher_io_dis_uops_1_0_bits_exc_cause;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_0_bits_bypassable;\t// @[core.scala:114:32]\n wire [4:0] _dispatcher_io_dis_uops_1_0_bits_mem_cmd;\t// @[core.scala:114:32]\n wire [1:0] _dispatcher_io_dis_uops_1_0_bits_mem_size;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_0_bits_mem_signed;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_0_bits_is_fence;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_0_bits_is_fencei;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_0_bits_is_amo;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_0_bits_uses_ldq;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_0_bits_uses_stq;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_0_bits_is_sys_pc2epc;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_0_bits_is_unique;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_0_bits_flush_on_commit;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_0_bits_ldst_is_rs1;\t// @[core.scala:114:32]\n wire [5:0] _dispatcher_io_dis_uops_1_0_bits_ldst;\t// @[core.scala:114:32]\n wire [5:0] _dispatcher_io_dis_uops_1_0_bits_lrs1;\t// @[core.scala:114:32]\n wire [5:0] _dispatcher_io_dis_uops_1_0_bits_lrs2;\t// @[core.scala:114:32]\n wire [5:0] _dispatcher_io_dis_uops_1_0_bits_lrs3;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_0_bits_ldst_val;\t// @[core.scala:114:32]\n wire [1:0] _dispatcher_io_dis_uops_1_0_bits_dst_rtype;\t// @[core.scala:114:32]\n wire [1:0] _dispatcher_io_dis_uops_1_0_bits_lrs1_rtype;\t// @[core.scala:114:32]\n wire [1:0] _dispatcher_io_dis_uops_1_0_bits_lrs2_rtype;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_0_bits_frs3_en;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_0_bits_fp_val;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_0_bits_fp_single;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_0_bits_xcpt_pf_if;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_0_bits_xcpt_ae_if;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_0_bits_xcpt_ma_if;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_0_bits_bp_debug_if;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_0_bits_bp_xcpt_if;\t// @[core.scala:114:32]\n wire [1:0] _dispatcher_io_dis_uops_1_0_bits_debug_fsrc;\t// @[core.scala:114:32]\n wire [1:0] _dispatcher_io_dis_uops_1_0_bits_debug_tsrc;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_1_valid;\t// @[core.scala:114:32]\n wire [6:0] _dispatcher_io_dis_uops_1_1_bits_uopc;\t// @[core.scala:114:32]\n wire [31:0] _dispatcher_io_dis_uops_1_1_bits_inst;\t// @[core.scala:114:32]\n wire [31:0] _dispatcher_io_dis_uops_1_1_bits_debug_inst;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_1_bits_is_rvc;\t// @[core.scala:114:32]\n wire [39:0] _dispatcher_io_dis_uops_1_1_bits_debug_pc;\t// @[core.scala:114:32]\n wire [2:0] _dispatcher_io_dis_uops_1_1_bits_iq_type;\t// @[core.scala:114:32]\n wire [9:0] _dispatcher_io_dis_uops_1_1_bits_fu_code;\t// @[core.scala:114:32]\n wire [3:0] _dispatcher_io_dis_uops_1_1_bits_ctrl_br_type;\t// @[core.scala:114:32]\n wire [1:0] _dispatcher_io_dis_uops_1_1_bits_ctrl_op1_sel;\t// @[core.scala:114:32]\n wire [2:0] _dispatcher_io_dis_uops_1_1_bits_ctrl_op2_sel;\t// @[core.scala:114:32]\n wire [2:0] _dispatcher_io_dis_uops_1_1_bits_ctrl_imm_sel;\t// @[core.scala:114:32]\n wire [4:0] _dispatcher_io_dis_uops_1_1_bits_ctrl_op_fcn;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_1_bits_ctrl_fcn_dw;\t// @[core.scala:114:32]\n wire [2:0] _dispatcher_io_dis_uops_1_1_bits_ctrl_csr_cmd;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_1_bits_ctrl_is_load;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_1_bits_ctrl_is_sta;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_1_bits_ctrl_is_std;\t// @[core.scala:114:32]\n wire [1:0] _dispatcher_io_dis_uops_1_1_bits_iw_state;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_1_bits_iw_p1_poisoned;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_1_bits_iw_p2_poisoned;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_1_bits_is_br;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_1_bits_is_jalr;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_1_bits_is_jal;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_1_bits_is_sfb;\t// @[core.scala:114:32]\n wire [15:0] _dispatcher_io_dis_uops_1_1_bits_br_mask;\t// @[core.scala:114:32]\n wire [3:0] _dispatcher_io_dis_uops_1_1_bits_br_tag;\t// @[core.scala:114:32]\n wire [4:0] _dispatcher_io_dis_uops_1_1_bits_ftq_idx;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_1_bits_edge_inst;\t// @[core.scala:114:32]\n wire [5:0] _dispatcher_io_dis_uops_1_1_bits_pc_lob;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_1_bits_taken;\t// @[core.scala:114:32]\n wire [19:0] _dispatcher_io_dis_uops_1_1_bits_imm_packed;\t// @[core.scala:114:32]\n wire [11:0] _dispatcher_io_dis_uops_1_1_bits_csr_addr;\t// @[core.scala:114:32]\n wire [6:0] _dispatcher_io_dis_uops_1_1_bits_rob_idx;\t// @[core.scala:114:32]\n wire [4:0] _dispatcher_io_dis_uops_1_1_bits_ldq_idx;\t// @[core.scala:114:32]\n wire [4:0] _dispatcher_io_dis_uops_1_1_bits_stq_idx;\t// @[core.scala:114:32]\n wire [1:0] _dispatcher_io_dis_uops_1_1_bits_rxq_idx;\t// @[core.scala:114:32]\n wire [6:0] _dispatcher_io_dis_uops_1_1_bits_pdst;\t// @[core.scala:114:32]\n wire [6:0] _dispatcher_io_dis_uops_1_1_bits_prs1;\t// @[core.scala:114:32]\n wire [6:0] _dispatcher_io_dis_uops_1_1_bits_prs2;\t// @[core.scala:114:32]\n wire [6:0] _dispatcher_io_dis_uops_1_1_bits_prs3;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_1_bits_prs1_busy;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_1_bits_prs2_busy;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_1_bits_prs3_busy;\t// @[core.scala:114:32]\n wire [6:0] _dispatcher_io_dis_uops_1_1_bits_stale_pdst;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_1_bits_exception;\t// @[core.scala:114:32]\n wire [63:0] _dispatcher_io_dis_uops_1_1_bits_exc_cause;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_1_bits_bypassable;\t// @[core.scala:114:32]\n wire [4:0] _dispatcher_io_dis_uops_1_1_bits_mem_cmd;\t// @[core.scala:114:32]\n wire [1:0] _dispatcher_io_dis_uops_1_1_bits_mem_size;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_1_bits_mem_signed;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_1_bits_is_fence;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_1_bits_is_fencei;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_1_bits_is_amo;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_1_bits_uses_ldq;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_1_bits_uses_stq;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_1_bits_is_sys_pc2epc;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_1_bits_is_unique;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_1_bits_flush_on_commit;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_1_bits_ldst_is_rs1;\t// @[core.scala:114:32]\n wire [5:0] _dispatcher_io_dis_uops_1_1_bits_ldst;\t// @[core.scala:114:32]\n wire [5:0] _dispatcher_io_dis_uops_1_1_bits_lrs1;\t// @[core.scala:114:32]\n wire [5:0] _dispatcher_io_dis_uops_1_1_bits_lrs2;\t// @[core.scala:114:32]\n wire [5:0] _dispatcher_io_dis_uops_1_1_bits_lrs3;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_1_bits_ldst_val;\t// @[core.scala:114:32]\n wire [1:0] _dispatcher_io_dis_uops_1_1_bits_dst_rtype;\t// @[core.scala:114:32]\n wire [1:0] _dispatcher_io_dis_uops_1_1_bits_lrs1_rtype;\t// @[core.scala:114:32]\n wire [1:0] _dispatcher_io_dis_uops_1_1_bits_lrs2_rtype;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_1_bits_frs3_en;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_1_bits_fp_val;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_1_bits_fp_single;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_1_bits_xcpt_pf_if;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_1_bits_xcpt_ae_if;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_1_bits_xcpt_ma_if;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_1_bits_bp_debug_if;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_1_bits_bp_xcpt_if;\t// @[core.scala:114:32]\n wire [1:0] _dispatcher_io_dis_uops_1_1_bits_debug_fsrc;\t// @[core.scala:114:32]\n wire [1:0] _dispatcher_io_dis_uops_1_1_bits_debug_tsrc;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_2_valid;\t// @[core.scala:114:32]\n wire [6:0] _dispatcher_io_dis_uops_1_2_bits_uopc;\t// @[core.scala:114:32]\n wire [31:0] _dispatcher_io_dis_uops_1_2_bits_inst;\t// @[core.scala:114:32]\n wire [31:0] _dispatcher_io_dis_uops_1_2_bits_debug_inst;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_2_bits_is_rvc;\t// @[core.scala:114:32]\n wire [39:0] _dispatcher_io_dis_uops_1_2_bits_debug_pc;\t// @[core.scala:114:32]\n wire [2:0] _dispatcher_io_dis_uops_1_2_bits_iq_type;\t// @[core.scala:114:32]\n wire [9:0] _dispatcher_io_dis_uops_1_2_bits_fu_code;\t// @[core.scala:114:32]\n wire [3:0] _dispatcher_io_dis_uops_1_2_bits_ctrl_br_type;\t// @[core.scala:114:32]\n wire [1:0] _dispatcher_io_dis_uops_1_2_bits_ctrl_op1_sel;\t// @[core.scala:114:32]\n wire [2:0] _dispatcher_io_dis_uops_1_2_bits_ctrl_op2_sel;\t// @[core.scala:114:32]\n wire [2:0] _dispatcher_io_dis_uops_1_2_bits_ctrl_imm_sel;\t// @[core.scala:114:32]\n wire [4:0] _dispatcher_io_dis_uops_1_2_bits_ctrl_op_fcn;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_2_bits_ctrl_fcn_dw;\t// @[core.scala:114:32]\n wire [2:0] _dispatcher_io_dis_uops_1_2_bits_ctrl_csr_cmd;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_2_bits_ctrl_is_load;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_2_bits_ctrl_is_sta;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_2_bits_ctrl_is_std;\t// @[core.scala:114:32]\n wire [1:0] _dispatcher_io_dis_uops_1_2_bits_iw_state;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_2_bits_iw_p1_poisoned;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_2_bits_iw_p2_poisoned;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_2_bits_is_br;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_2_bits_is_jalr;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_2_bits_is_jal;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_2_bits_is_sfb;\t// @[core.scala:114:32]\n wire [15:0] _dispatcher_io_dis_uops_1_2_bits_br_mask;\t// @[core.scala:114:32]\n wire [3:0] _dispatcher_io_dis_uops_1_2_bits_br_tag;\t// @[core.scala:114:32]\n wire [4:0] _dispatcher_io_dis_uops_1_2_bits_ftq_idx;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_2_bits_edge_inst;\t// @[core.scala:114:32]\n wire [5:0] _dispatcher_io_dis_uops_1_2_bits_pc_lob;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_2_bits_taken;\t// @[core.scala:114:32]\n wire [19:0] _dispatcher_io_dis_uops_1_2_bits_imm_packed;\t// @[core.scala:114:32]\n wire [11:0] _dispatcher_io_dis_uops_1_2_bits_csr_addr;\t// @[core.scala:114:32]\n wire [6:0] _dispatcher_io_dis_uops_1_2_bits_rob_idx;\t// @[core.scala:114:32]\n wire [4:0] _dispatcher_io_dis_uops_1_2_bits_ldq_idx;\t// @[core.scala:114:32]\n wire [4:0] _dispatcher_io_dis_uops_1_2_bits_stq_idx;\t// @[core.scala:114:32]\n wire [1:0] _dispatcher_io_dis_uops_1_2_bits_rxq_idx;\t// @[core.scala:114:32]\n wire [6:0] _dispatcher_io_dis_uops_1_2_bits_pdst;\t// @[core.scala:114:32]\n wire [6:0] _dispatcher_io_dis_uops_1_2_bits_prs1;\t// @[core.scala:114:32]\n wire [6:0] _dispatcher_io_dis_uops_1_2_bits_prs2;\t// @[core.scala:114:32]\n wire [6:0] _dispatcher_io_dis_uops_1_2_bits_prs3;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_2_bits_prs1_busy;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_2_bits_prs2_busy;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_2_bits_prs3_busy;\t// @[core.scala:114:32]\n wire [6:0] _dispatcher_io_dis_uops_1_2_bits_stale_pdst;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_2_bits_exception;\t// @[core.scala:114:32]\n wire [63:0] _dispatcher_io_dis_uops_1_2_bits_exc_cause;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_2_bits_bypassable;\t// @[core.scala:114:32]\n wire [4:0] _dispatcher_io_dis_uops_1_2_bits_mem_cmd;\t// @[core.scala:114:32]\n wire [1:0] _dispatcher_io_dis_uops_1_2_bits_mem_size;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_2_bits_mem_signed;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_2_bits_is_fence;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_2_bits_is_fencei;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_2_bits_is_amo;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_2_bits_uses_ldq;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_2_bits_uses_stq;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_2_bits_is_sys_pc2epc;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_2_bits_is_unique;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_2_bits_flush_on_commit;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_2_bits_ldst_is_rs1;\t// @[core.scala:114:32]\n wire [5:0] _dispatcher_io_dis_uops_1_2_bits_ldst;\t// @[core.scala:114:32]\n wire [5:0] _dispatcher_io_dis_uops_1_2_bits_lrs1;\t// @[core.scala:114:32]\n wire [5:0] _dispatcher_io_dis_uops_1_2_bits_lrs2;\t// @[core.scala:114:32]\n wire [5:0] _dispatcher_io_dis_uops_1_2_bits_lrs3;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_2_bits_ldst_val;\t// @[core.scala:114:32]\n wire [1:0] _dispatcher_io_dis_uops_1_2_bits_dst_rtype;\t// @[core.scala:114:32]\n wire [1:0] _dispatcher_io_dis_uops_1_2_bits_lrs1_rtype;\t// @[core.scala:114:32]\n wire [1:0] _dispatcher_io_dis_uops_1_2_bits_lrs2_rtype;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_2_bits_frs3_en;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_2_bits_fp_val;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_2_bits_fp_single;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_2_bits_xcpt_pf_if;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_2_bits_xcpt_ae_if;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_2_bits_xcpt_ma_if;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_2_bits_bp_debug_if;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_1_2_bits_bp_xcpt_if;\t// @[core.scala:114:32]\n wire [1:0] _dispatcher_io_dis_uops_1_2_bits_debug_fsrc;\t// @[core.scala:114:32]\n wire [1:0] _dispatcher_io_dis_uops_1_2_bits_debug_tsrc;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_0_valid;\t// @[core.scala:114:32]\n wire [6:0] _dispatcher_io_dis_uops_0_0_bits_uopc;\t// @[core.scala:114:32]\n wire [31:0] _dispatcher_io_dis_uops_0_0_bits_inst;\t// @[core.scala:114:32]\n wire [31:0] _dispatcher_io_dis_uops_0_0_bits_debug_inst;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_0_bits_is_rvc;\t// @[core.scala:114:32]\n wire [39:0] _dispatcher_io_dis_uops_0_0_bits_debug_pc;\t// @[core.scala:114:32]\n wire [2:0] _dispatcher_io_dis_uops_0_0_bits_iq_type;\t// @[core.scala:114:32]\n wire [9:0] _dispatcher_io_dis_uops_0_0_bits_fu_code;\t// @[core.scala:114:32]\n wire [3:0] _dispatcher_io_dis_uops_0_0_bits_ctrl_br_type;\t// @[core.scala:114:32]\n wire [1:0] _dispatcher_io_dis_uops_0_0_bits_ctrl_op1_sel;\t// @[core.scala:114:32]\n wire [2:0] _dispatcher_io_dis_uops_0_0_bits_ctrl_op2_sel;\t// @[core.scala:114:32]\n wire [2:0] _dispatcher_io_dis_uops_0_0_bits_ctrl_imm_sel;\t// @[core.scala:114:32]\n wire [4:0] _dispatcher_io_dis_uops_0_0_bits_ctrl_op_fcn;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_0_bits_ctrl_fcn_dw;\t// @[core.scala:114:32]\n wire [2:0] _dispatcher_io_dis_uops_0_0_bits_ctrl_csr_cmd;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_0_bits_ctrl_is_load;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_0_bits_ctrl_is_sta;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_0_bits_ctrl_is_std;\t// @[core.scala:114:32]\n wire [1:0] _dispatcher_io_dis_uops_0_0_bits_iw_state;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_0_bits_iw_p1_poisoned;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_0_bits_iw_p2_poisoned;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_0_bits_is_br;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_0_bits_is_jalr;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_0_bits_is_jal;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_0_bits_is_sfb;\t// @[core.scala:114:32]\n wire [15:0] _dispatcher_io_dis_uops_0_0_bits_br_mask;\t// @[core.scala:114:32]\n wire [3:0] _dispatcher_io_dis_uops_0_0_bits_br_tag;\t// @[core.scala:114:32]\n wire [4:0] _dispatcher_io_dis_uops_0_0_bits_ftq_idx;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_0_bits_edge_inst;\t// @[core.scala:114:32]\n wire [5:0] _dispatcher_io_dis_uops_0_0_bits_pc_lob;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_0_bits_taken;\t// @[core.scala:114:32]\n wire [19:0] _dispatcher_io_dis_uops_0_0_bits_imm_packed;\t// @[core.scala:114:32]\n wire [11:0] _dispatcher_io_dis_uops_0_0_bits_csr_addr;\t// @[core.scala:114:32]\n wire [6:0] _dispatcher_io_dis_uops_0_0_bits_rob_idx;\t// @[core.scala:114:32]\n wire [4:0] _dispatcher_io_dis_uops_0_0_bits_ldq_idx;\t// @[core.scala:114:32]\n wire [4:0] _dispatcher_io_dis_uops_0_0_bits_stq_idx;\t// @[core.scala:114:32]\n wire [1:0] _dispatcher_io_dis_uops_0_0_bits_rxq_idx;\t// @[core.scala:114:32]\n wire [6:0] _dispatcher_io_dis_uops_0_0_bits_pdst;\t// @[core.scala:114:32]\n wire [6:0] _dispatcher_io_dis_uops_0_0_bits_prs1;\t// @[core.scala:114:32]\n wire [6:0] _dispatcher_io_dis_uops_0_0_bits_prs2;\t// @[core.scala:114:32]\n wire [6:0] _dispatcher_io_dis_uops_0_0_bits_prs3;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_0_bits_prs1_busy;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_0_bits_prs2_busy;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_0_bits_prs3_busy;\t// @[core.scala:114:32]\n wire [6:0] _dispatcher_io_dis_uops_0_0_bits_stale_pdst;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_0_bits_exception;\t// @[core.scala:114:32]\n wire [63:0] _dispatcher_io_dis_uops_0_0_bits_exc_cause;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_0_bits_bypassable;\t// @[core.scala:114:32]\n wire [4:0] _dispatcher_io_dis_uops_0_0_bits_mem_cmd;\t// @[core.scala:114:32]\n wire [1:0] _dispatcher_io_dis_uops_0_0_bits_mem_size;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_0_bits_mem_signed;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_0_bits_is_fence;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_0_bits_is_fencei;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_0_bits_is_amo;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_0_bits_uses_ldq;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_0_bits_uses_stq;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_0_bits_is_sys_pc2epc;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_0_bits_is_unique;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_0_bits_flush_on_commit;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_0_bits_ldst_is_rs1;\t// @[core.scala:114:32]\n wire [5:0] _dispatcher_io_dis_uops_0_0_bits_ldst;\t// @[core.scala:114:32]\n wire [5:0] _dispatcher_io_dis_uops_0_0_bits_lrs1;\t// @[core.scala:114:32]\n wire [5:0] _dispatcher_io_dis_uops_0_0_bits_lrs2;\t// @[core.scala:114:32]\n wire [5:0] _dispatcher_io_dis_uops_0_0_bits_lrs3;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_0_bits_ldst_val;\t// @[core.scala:114:32]\n wire [1:0] _dispatcher_io_dis_uops_0_0_bits_dst_rtype;\t// @[core.scala:114:32]\n wire [1:0] _dispatcher_io_dis_uops_0_0_bits_lrs1_rtype;\t// @[core.scala:114:32]\n wire [1:0] _dispatcher_io_dis_uops_0_0_bits_lrs2_rtype;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_0_bits_frs3_en;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_0_bits_fp_val;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_0_bits_fp_single;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_0_bits_xcpt_pf_if;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_0_bits_xcpt_ae_if;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_0_bits_xcpt_ma_if;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_0_bits_bp_debug_if;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_0_bits_bp_xcpt_if;\t// @[core.scala:114:32]\n wire [1:0] _dispatcher_io_dis_uops_0_0_bits_debug_fsrc;\t// @[core.scala:114:32]\n wire [1:0] _dispatcher_io_dis_uops_0_0_bits_debug_tsrc;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_1_valid;\t// @[core.scala:114:32]\n wire [6:0] _dispatcher_io_dis_uops_0_1_bits_uopc;\t// @[core.scala:114:32]\n wire [31:0] _dispatcher_io_dis_uops_0_1_bits_inst;\t// @[core.scala:114:32]\n wire [31:0] _dispatcher_io_dis_uops_0_1_bits_debug_inst;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_1_bits_is_rvc;\t// @[core.scala:114:32]\n wire [39:0] _dispatcher_io_dis_uops_0_1_bits_debug_pc;\t// @[core.scala:114:32]\n wire [2:0] _dispatcher_io_dis_uops_0_1_bits_iq_type;\t// @[core.scala:114:32]\n wire [9:0] _dispatcher_io_dis_uops_0_1_bits_fu_code;\t// @[core.scala:114:32]\n wire [3:0] _dispatcher_io_dis_uops_0_1_bits_ctrl_br_type;\t// @[core.scala:114:32]\n wire [1:0] _dispatcher_io_dis_uops_0_1_bits_ctrl_op1_sel;\t// @[core.scala:114:32]\n wire [2:0] _dispatcher_io_dis_uops_0_1_bits_ctrl_op2_sel;\t// @[core.scala:114:32]\n wire [2:0] _dispatcher_io_dis_uops_0_1_bits_ctrl_imm_sel;\t// @[core.scala:114:32]\n wire [4:0] _dispatcher_io_dis_uops_0_1_bits_ctrl_op_fcn;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_1_bits_ctrl_fcn_dw;\t// @[core.scala:114:32]\n wire [2:0] _dispatcher_io_dis_uops_0_1_bits_ctrl_csr_cmd;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_1_bits_ctrl_is_load;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_1_bits_ctrl_is_sta;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_1_bits_ctrl_is_std;\t// @[core.scala:114:32]\n wire [1:0] _dispatcher_io_dis_uops_0_1_bits_iw_state;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_1_bits_iw_p1_poisoned;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_1_bits_iw_p2_poisoned;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_1_bits_is_br;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_1_bits_is_jalr;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_1_bits_is_jal;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_1_bits_is_sfb;\t// @[core.scala:114:32]\n wire [15:0] _dispatcher_io_dis_uops_0_1_bits_br_mask;\t// @[core.scala:114:32]\n wire [3:0] _dispatcher_io_dis_uops_0_1_bits_br_tag;\t// @[core.scala:114:32]\n wire [4:0] _dispatcher_io_dis_uops_0_1_bits_ftq_idx;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_1_bits_edge_inst;\t// @[core.scala:114:32]\n wire [5:0] _dispatcher_io_dis_uops_0_1_bits_pc_lob;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_1_bits_taken;\t// @[core.scala:114:32]\n wire [19:0] _dispatcher_io_dis_uops_0_1_bits_imm_packed;\t// @[core.scala:114:32]\n wire [11:0] _dispatcher_io_dis_uops_0_1_bits_csr_addr;\t// @[core.scala:114:32]\n wire [6:0] _dispatcher_io_dis_uops_0_1_bits_rob_idx;\t// @[core.scala:114:32]\n wire [4:0] _dispatcher_io_dis_uops_0_1_bits_ldq_idx;\t// @[core.scala:114:32]\n wire [4:0] _dispatcher_io_dis_uops_0_1_bits_stq_idx;\t// @[core.scala:114:32]\n wire [1:0] _dispatcher_io_dis_uops_0_1_bits_rxq_idx;\t// @[core.scala:114:32]\n wire [6:0] _dispatcher_io_dis_uops_0_1_bits_pdst;\t// @[core.scala:114:32]\n wire [6:0] _dispatcher_io_dis_uops_0_1_bits_prs1;\t// @[core.scala:114:32]\n wire [6:0] _dispatcher_io_dis_uops_0_1_bits_prs2;\t// @[core.scala:114:32]\n wire [6:0] _dispatcher_io_dis_uops_0_1_bits_prs3;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_1_bits_prs1_busy;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_1_bits_prs2_busy;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_1_bits_prs3_busy;\t// @[core.scala:114:32]\n wire [6:0] _dispatcher_io_dis_uops_0_1_bits_stale_pdst;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_1_bits_exception;\t// @[core.scala:114:32]\n wire [63:0] _dispatcher_io_dis_uops_0_1_bits_exc_cause;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_1_bits_bypassable;\t// @[core.scala:114:32]\n wire [4:0] _dispatcher_io_dis_uops_0_1_bits_mem_cmd;\t// @[core.scala:114:32]\n wire [1:0] _dispatcher_io_dis_uops_0_1_bits_mem_size;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_1_bits_mem_signed;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_1_bits_is_fence;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_1_bits_is_fencei;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_1_bits_is_amo;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_1_bits_uses_ldq;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_1_bits_uses_stq;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_1_bits_is_sys_pc2epc;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_1_bits_is_unique;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_1_bits_flush_on_commit;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_1_bits_ldst_is_rs1;\t// @[core.scala:114:32]\n wire [5:0] _dispatcher_io_dis_uops_0_1_bits_ldst;\t// @[core.scala:114:32]\n wire [5:0] _dispatcher_io_dis_uops_0_1_bits_lrs1;\t// @[core.scala:114:32]\n wire [5:0] _dispatcher_io_dis_uops_0_1_bits_lrs2;\t// @[core.scala:114:32]\n wire [5:0] _dispatcher_io_dis_uops_0_1_bits_lrs3;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_1_bits_ldst_val;\t// @[core.scala:114:32]\n wire [1:0] _dispatcher_io_dis_uops_0_1_bits_dst_rtype;\t// @[core.scala:114:32]\n wire [1:0] _dispatcher_io_dis_uops_0_1_bits_lrs1_rtype;\t// @[core.scala:114:32]\n wire [1:0] _dispatcher_io_dis_uops_0_1_bits_lrs2_rtype;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_1_bits_frs3_en;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_1_bits_fp_val;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_1_bits_fp_single;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_1_bits_xcpt_pf_if;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_1_bits_xcpt_ae_if;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_1_bits_xcpt_ma_if;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_1_bits_bp_debug_if;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_1_bits_bp_xcpt_if;\t// @[core.scala:114:32]\n wire [1:0] _dispatcher_io_dis_uops_0_1_bits_debug_fsrc;\t// @[core.scala:114:32]\n wire [1:0] _dispatcher_io_dis_uops_0_1_bits_debug_tsrc;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_2_valid;\t// @[core.scala:114:32]\n wire [6:0] _dispatcher_io_dis_uops_0_2_bits_uopc;\t// @[core.scala:114:32]\n wire [31:0] _dispatcher_io_dis_uops_0_2_bits_inst;\t// @[core.scala:114:32]\n wire [31:0] _dispatcher_io_dis_uops_0_2_bits_debug_inst;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_2_bits_is_rvc;\t// @[core.scala:114:32]\n wire [39:0] _dispatcher_io_dis_uops_0_2_bits_debug_pc;\t// @[core.scala:114:32]\n wire [2:0] _dispatcher_io_dis_uops_0_2_bits_iq_type;\t// @[core.scala:114:32]\n wire [9:0] _dispatcher_io_dis_uops_0_2_bits_fu_code;\t// @[core.scala:114:32]\n wire [3:0] _dispatcher_io_dis_uops_0_2_bits_ctrl_br_type;\t// @[core.scala:114:32]\n wire [1:0] _dispatcher_io_dis_uops_0_2_bits_ctrl_op1_sel;\t// @[core.scala:114:32]\n wire [2:0] _dispatcher_io_dis_uops_0_2_bits_ctrl_op2_sel;\t// @[core.scala:114:32]\n wire [2:0] _dispatcher_io_dis_uops_0_2_bits_ctrl_imm_sel;\t// @[core.scala:114:32]\n wire [4:0] _dispatcher_io_dis_uops_0_2_bits_ctrl_op_fcn;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_2_bits_ctrl_fcn_dw;\t// @[core.scala:114:32]\n wire [2:0] _dispatcher_io_dis_uops_0_2_bits_ctrl_csr_cmd;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_2_bits_ctrl_is_load;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_2_bits_ctrl_is_sta;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_2_bits_ctrl_is_std;\t// @[core.scala:114:32]\n wire [1:0] _dispatcher_io_dis_uops_0_2_bits_iw_state;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_2_bits_iw_p1_poisoned;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_2_bits_iw_p2_poisoned;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_2_bits_is_br;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_2_bits_is_jalr;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_2_bits_is_jal;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_2_bits_is_sfb;\t// @[core.scala:114:32]\n wire [15:0] _dispatcher_io_dis_uops_0_2_bits_br_mask;\t// @[core.scala:114:32]\n wire [3:0] _dispatcher_io_dis_uops_0_2_bits_br_tag;\t// @[core.scala:114:32]\n wire [4:0] _dispatcher_io_dis_uops_0_2_bits_ftq_idx;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_2_bits_edge_inst;\t// @[core.scala:114:32]\n wire [5:0] _dispatcher_io_dis_uops_0_2_bits_pc_lob;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_2_bits_taken;\t// @[core.scala:114:32]\n wire [19:0] _dispatcher_io_dis_uops_0_2_bits_imm_packed;\t// @[core.scala:114:32]\n wire [11:0] _dispatcher_io_dis_uops_0_2_bits_csr_addr;\t// @[core.scala:114:32]\n wire [6:0] _dispatcher_io_dis_uops_0_2_bits_rob_idx;\t// @[core.scala:114:32]\n wire [4:0] _dispatcher_io_dis_uops_0_2_bits_ldq_idx;\t// @[core.scala:114:32]\n wire [4:0] _dispatcher_io_dis_uops_0_2_bits_stq_idx;\t// @[core.scala:114:32]\n wire [1:0] _dispatcher_io_dis_uops_0_2_bits_rxq_idx;\t// @[core.scala:114:32]\n wire [6:0] _dispatcher_io_dis_uops_0_2_bits_pdst;\t// @[core.scala:114:32]\n wire [6:0] _dispatcher_io_dis_uops_0_2_bits_prs1;\t// @[core.scala:114:32]\n wire [6:0] _dispatcher_io_dis_uops_0_2_bits_prs2;\t// @[core.scala:114:32]\n wire [6:0] _dispatcher_io_dis_uops_0_2_bits_prs3;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_2_bits_prs1_busy;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_2_bits_prs2_busy;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_2_bits_prs3_busy;\t// @[core.scala:114:32]\n wire [6:0] _dispatcher_io_dis_uops_0_2_bits_stale_pdst;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_2_bits_exception;\t// @[core.scala:114:32]\n wire [63:0] _dispatcher_io_dis_uops_0_2_bits_exc_cause;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_2_bits_bypassable;\t// @[core.scala:114:32]\n wire [4:0] _dispatcher_io_dis_uops_0_2_bits_mem_cmd;\t// @[core.scala:114:32]\n wire [1:0] _dispatcher_io_dis_uops_0_2_bits_mem_size;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_2_bits_mem_signed;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_2_bits_is_fence;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_2_bits_is_fencei;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_2_bits_is_amo;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_2_bits_uses_ldq;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_2_bits_uses_stq;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_2_bits_is_sys_pc2epc;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_2_bits_is_unique;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_2_bits_flush_on_commit;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_2_bits_ldst_is_rs1;\t// @[core.scala:114:32]\n wire [5:0] _dispatcher_io_dis_uops_0_2_bits_ldst;\t// @[core.scala:114:32]\n wire [5:0] _dispatcher_io_dis_uops_0_2_bits_lrs1;\t// @[core.scala:114:32]\n wire [5:0] _dispatcher_io_dis_uops_0_2_bits_lrs2;\t// @[core.scala:114:32]\n wire [5:0] _dispatcher_io_dis_uops_0_2_bits_lrs3;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_2_bits_ldst_val;\t// @[core.scala:114:32]\n wire [1:0] _dispatcher_io_dis_uops_0_2_bits_dst_rtype;\t// @[core.scala:114:32]\n wire [1:0] _dispatcher_io_dis_uops_0_2_bits_lrs1_rtype;\t// @[core.scala:114:32]\n wire [1:0] _dispatcher_io_dis_uops_0_2_bits_lrs2_rtype;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_2_bits_frs3_en;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_2_bits_fp_val;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_2_bits_fp_single;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_2_bits_xcpt_pf_if;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_2_bits_xcpt_ae_if;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_2_bits_xcpt_ma_if;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_2_bits_bp_debug_if;\t// @[core.scala:114:32]\n wire _dispatcher_io_dis_uops_0_2_bits_bp_xcpt_if;\t// @[core.scala:114:32]\n wire [1:0] _dispatcher_io_dis_uops_0_2_bits_debug_fsrc;\t// @[core.scala:114:32]\n wire [1:0] _dispatcher_io_dis_uops_0_2_bits_debug_tsrc;\t// @[core.scala:114:32]\n wire _int_issue_unit_io_dis_uops_0_ready;\t// @[core.scala:110:32]\n wire _int_issue_unit_io_dis_uops_1_ready;\t// @[core.scala:110:32]\n wire _int_issue_unit_io_dis_uops_2_ready;\t// @[core.scala:110:32]\n wire _mem_issue_unit_io_dis_uops_0_ready;\t// @[core.scala:108:32]\n wire _mem_issue_unit_io_dis_uops_1_ready;\t// @[core.scala:108:32]\n wire _mem_issue_unit_io_dis_uops_2_ready;\t// @[core.scala:108:32]\n wire _mem_issue_unit_io_iss_valids_0;\t// @[core.scala:108:32]\n wire _mem_issue_unit_io_iss_uops_0_uses_ldq;\t// @[core.scala:108:32]\n wire _fp_rename_stage_io_ren_stalls_0;\t// @[core.scala:104:46]\n wire _fp_rename_stage_io_ren_stalls_1;\t// @[core.scala:104:46]\n wire _fp_rename_stage_io_ren_stalls_2;\t// @[core.scala:104:46]\n wire [6:0] _fp_rename_stage_io_ren2_uops_0_pdst;\t// @[core.scala:104:46]\n wire [6:0] _fp_rename_stage_io_ren2_uops_0_prs1;\t// @[core.scala:104:46]\n wire [6:0] _fp_rename_stage_io_ren2_uops_0_prs2;\t// @[core.scala:104:46]\n wire _fp_rename_stage_io_ren2_uops_0_prs1_busy;\t// @[core.scala:104:46]\n wire _fp_rename_stage_io_ren2_uops_0_prs2_busy;\t// @[core.scala:104:46]\n wire _fp_rename_stage_io_ren2_uops_0_prs3_busy;\t// @[core.scala:104:46]\n wire [6:0] _fp_rename_stage_io_ren2_uops_0_stale_pdst;\t// @[core.scala:104:46]\n wire [6:0] _fp_rename_stage_io_ren2_uops_1_pdst;\t// @[core.scala:104:46]\n wire [6:0] _fp_rename_stage_io_ren2_uops_1_prs1;\t// @[core.scala:104:46]\n wire [6:0] _fp_rename_stage_io_ren2_uops_1_prs2;\t// @[core.scala:104:46]\n wire _fp_rename_stage_io_ren2_uops_1_prs1_busy;\t// @[core.scala:104:46]\n wire _fp_rename_stage_io_ren2_uops_1_prs2_busy;\t// @[core.scala:104:46]\n wire _fp_rename_stage_io_ren2_uops_1_prs3_busy;\t// @[core.scala:104:46]\n wire [6:0] _fp_rename_stage_io_ren2_uops_1_stale_pdst;\t// @[core.scala:104:46]\n wire [6:0] _fp_rename_stage_io_ren2_uops_2_pdst;\t// @[core.scala:104:46]\n wire [6:0] _fp_rename_stage_io_ren2_uops_2_prs1;\t// @[core.scala:104:46]\n wire [6:0] _fp_rename_stage_io_ren2_uops_2_prs2;\t// @[core.scala:104:46]\n wire _fp_rename_stage_io_ren2_uops_2_prs1_busy;\t// @[core.scala:104:46]\n wire _fp_rename_stage_io_ren2_uops_2_prs2_busy;\t// @[core.scala:104:46]\n wire _fp_rename_stage_io_ren2_uops_2_prs3_busy;\t// @[core.scala:104:46]\n wire [6:0] _fp_rename_stage_io_ren2_uops_2_stale_pdst;\t// @[core.scala:104:46]\n wire _rename_stage_io_ren_stalls_0;\t// @[core.scala:103:32]\n wire _rename_stage_io_ren_stalls_1;\t// @[core.scala:103:32]\n wire _rename_stage_io_ren_stalls_2;\t// @[core.scala:103:32]\n wire [6:0] _rename_stage_io_ren2_uops_0_pdst;\t// @[core.scala:103:32]\n wire [6:0] _rename_stage_io_ren2_uops_0_prs1;\t// @[core.scala:103:32]\n wire [6:0] _rename_stage_io_ren2_uops_0_prs2;\t// @[core.scala:103:32]\n wire _rename_stage_io_ren2_uops_0_prs1_busy;\t// @[core.scala:103:32]\n wire _rename_stage_io_ren2_uops_0_prs2_busy;\t// @[core.scala:103:32]\n wire [6:0] _rename_stage_io_ren2_uops_0_stale_pdst;\t// @[core.scala:103:32]\n wire [6:0] _rename_stage_io_ren2_uops_1_pdst;\t// @[core.scala:103:32]\n wire [6:0] _rename_stage_io_ren2_uops_1_prs1;\t// @[core.scala:103:32]\n wire [6:0] _rename_stage_io_ren2_uops_1_prs2;\t// @[core.scala:103:32]\n wire _rename_stage_io_ren2_uops_1_prs1_busy;\t// @[core.scala:103:32]\n wire _rename_stage_io_ren2_uops_1_prs2_busy;\t// @[core.scala:103:32]\n wire [6:0] _rename_stage_io_ren2_uops_1_stale_pdst;\t// @[core.scala:103:32]\n wire [6:0] _rename_stage_io_ren2_uops_2_pdst;\t// @[core.scala:103:32]\n wire [6:0] _rename_stage_io_ren2_uops_2_prs1;\t// @[core.scala:103:32]\n wire [6:0] _rename_stage_io_ren2_uops_2_prs2;\t// @[core.scala:103:32]\n wire _rename_stage_io_ren2_uops_2_prs1_busy;\t// @[core.scala:103:32]\n wire _rename_stage_io_ren2_uops_2_prs2_busy;\t// @[core.scala:103:32]\n wire [6:0] _rename_stage_io_ren2_uops_2_stale_pdst;\t// @[core.scala:103:32]\n wire [31:0] _decode_units_2_io_csr_decode_inst;\t// @[core.scala:101:79]\n wire [31:0] _decode_units_1_io_csr_decode_inst;\t// @[core.scala:101:79]\n wire [31:0] _decode_units_0_io_csr_decode_inst;\t// @[core.scala:101:79]\n wire _FpPipeline_io_dis_uops_0_ready;\t// @[core.scala:80:37]\n wire _FpPipeline_io_dis_uops_1_ready;\t// @[core.scala:80:37]\n wire _FpPipeline_io_dis_uops_2_ready;\t// @[core.scala:80:37]\n wire _FpPipeline_io_from_int_ready;\t// @[core.scala:80:37]\n wire _FpPipeline_io_to_int_valid;\t// @[core.scala:80:37]\n wire [6:0] _FpPipeline_io_to_int_bits_uop_uopc;\t// @[core.scala:80:37]\n wire [31:0] _FpPipeline_io_to_int_bits_uop_inst;\t// @[core.scala:80:37]\n wire [31:0] _FpPipeline_io_to_int_bits_uop_debug_inst;\t// @[core.scala:80:37]\n wire _FpPipeline_io_to_int_bits_uop_is_rvc;\t// @[core.scala:80:37]\n wire [39:0] _FpPipeline_io_to_int_bits_uop_debug_pc;\t// @[core.scala:80:37]\n wire [2:0] _FpPipeline_io_to_int_bits_uop_iq_type;\t// @[core.scala:80:37]\n wire [9:0] _FpPipeline_io_to_int_bits_uop_fu_code;\t// @[core.scala:80:37]\n wire [3:0] _FpPipeline_io_to_int_bits_uop_ctrl_br_type;\t// @[core.scala:80:37]\n wire [1:0] _FpPipeline_io_to_int_bits_uop_ctrl_op1_sel;\t// @[core.scala:80:37]\n wire [2:0] _FpPipeline_io_to_int_bits_uop_ctrl_op2_sel;\t// @[core.scala:80:37]\n wire [2:0] _FpPipeline_io_to_int_bits_uop_ctrl_imm_sel;\t// @[core.scala:80:37]\n wire [4:0] _FpPipeline_io_to_int_bits_uop_ctrl_op_fcn;\t// @[core.scala:80:37]\n wire _FpPipeline_io_to_int_bits_uop_ctrl_fcn_dw;\t// @[core.scala:80:37]\n wire [2:0] _FpPipeline_io_to_int_bits_uop_ctrl_csr_cmd;\t// @[core.scala:80:37]\n wire _FpPipeline_io_to_int_bits_uop_ctrl_is_load;\t// @[core.scala:80:37]\n wire _FpPipeline_io_to_int_bits_uop_ctrl_is_sta;\t// @[core.scala:80:37]\n wire _FpPipeline_io_to_int_bits_uop_ctrl_is_std;\t// @[core.scala:80:37]\n wire [1:0] _FpPipeline_io_to_int_bits_uop_iw_state;\t// @[core.scala:80:37]\n wire _FpPipeline_io_to_int_bits_uop_iw_p1_poisoned;\t// @[core.scala:80:37]\n wire _FpPipeline_io_to_int_bits_uop_iw_p2_poisoned;\t// @[core.scala:80:37]\n wire _FpPipeline_io_to_int_bits_uop_is_br;\t// @[core.scala:80:37]\n wire _FpPipeline_io_to_int_bits_uop_is_jalr;\t// @[core.scala:80:37]\n wire _FpPipeline_io_to_int_bits_uop_is_jal;\t// @[core.scala:80:37]\n wire _FpPipeline_io_to_int_bits_uop_is_sfb;\t// @[core.scala:80:37]\n wire [15:0] _FpPipeline_io_to_int_bits_uop_br_mask;\t// @[core.scala:80:37]\n wire [3:0] _FpPipeline_io_to_int_bits_uop_br_tag;\t// @[core.scala:80:37]\n wire [4:0] _FpPipeline_io_to_int_bits_uop_ftq_idx;\t// @[core.scala:80:37]\n wire _FpPipeline_io_to_int_bits_uop_edge_inst;\t// @[core.scala:80:37]\n wire [5:0] _FpPipeline_io_to_int_bits_uop_pc_lob;\t// @[core.scala:80:37]\n wire _FpPipeline_io_to_int_bits_uop_taken;\t// @[core.scala:80:37]\n wire [19:0] _FpPipeline_io_to_int_bits_uop_imm_packed;\t// @[core.scala:80:37]\n wire [11:0] _FpPipeline_io_to_int_bits_uop_csr_addr;\t// @[core.scala:80:37]\n wire [6:0] _FpPipeline_io_to_int_bits_uop_rob_idx;\t// @[core.scala:80:37]\n wire [4:0] _FpPipeline_io_to_int_bits_uop_ldq_idx;\t// @[core.scala:80:37]\n wire [4:0] _FpPipeline_io_to_int_bits_uop_stq_idx;\t// @[core.scala:80:37]\n wire [1:0] _FpPipeline_io_to_int_bits_uop_rxq_idx;\t// @[core.scala:80:37]\n wire [6:0] _FpPipeline_io_to_int_bits_uop_pdst;\t// @[core.scala:80:37]\n wire [6:0] _FpPipeline_io_to_int_bits_uop_prs1;\t// @[core.scala:80:37]\n wire [6:0] _FpPipeline_io_to_int_bits_uop_prs2;\t// @[core.scala:80:37]\n wire [6:0] _FpPipeline_io_to_int_bits_uop_prs3;\t// @[core.scala:80:37]\n wire [4:0] _FpPipeline_io_to_int_bits_uop_ppred;\t// @[core.scala:80:37]\n wire _FpPipeline_io_to_int_bits_uop_prs1_busy;\t// @[core.scala:80:37]\n wire _FpPipeline_io_to_int_bits_uop_prs2_busy;\t// @[core.scala:80:37]\n wire _FpPipeline_io_to_int_bits_uop_prs3_busy;\t// @[core.scala:80:37]\n wire _FpPipeline_io_to_int_bits_uop_ppred_busy;\t// @[core.scala:80:37]\n wire [6:0] _FpPipeline_io_to_int_bits_uop_stale_pdst;\t// @[core.scala:80:37]\n wire _FpPipeline_io_to_int_bits_uop_exception;\t// @[core.scala:80:37]\n wire [63:0] _FpPipeline_io_to_int_bits_uop_exc_cause;\t// @[core.scala:80:37]\n wire _FpPipeline_io_to_int_bits_uop_bypassable;\t// @[core.scala:80:37]\n wire [4:0] _FpPipeline_io_to_int_bits_uop_mem_cmd;\t// @[core.scala:80:37]\n wire [1:0] _FpPipeline_io_to_int_bits_uop_mem_size;\t// @[core.scala:80:37]\n wire _FpPipeline_io_to_int_bits_uop_mem_signed;\t// @[core.scala:80:37]\n wire _FpPipeline_io_to_int_bits_uop_is_fence;\t// @[core.scala:80:37]\n wire _FpPipeline_io_to_int_bits_uop_is_fencei;\t// @[core.scala:80:37]\n wire _FpPipeline_io_to_int_bits_uop_is_amo;\t// @[core.scala:80:37]\n wire _FpPipeline_io_to_int_bits_uop_uses_ldq;\t// @[core.scala:80:37]\n wire _FpPipeline_io_to_int_bits_uop_uses_stq;\t// @[core.scala:80:37]\n wire _FpPipeline_io_to_int_bits_uop_is_sys_pc2epc;\t// @[core.scala:80:37]\n wire _FpPipeline_io_to_int_bits_uop_is_unique;\t// @[core.scala:80:37]\n wire _FpPipeline_io_to_int_bits_uop_flush_on_commit;\t// @[core.scala:80:37]\n wire _FpPipeline_io_to_int_bits_uop_ldst_is_rs1;\t// @[core.scala:80:37]\n wire [5:0] _FpPipeline_io_to_int_bits_uop_ldst;\t// @[core.scala:80:37]\n wire [5:0] _FpPipeline_io_to_int_bits_uop_lrs1;\t// @[core.scala:80:37]\n wire [5:0] _FpPipeline_io_to_int_bits_uop_lrs2;\t// @[core.scala:80:37]\n wire [5:0] _FpPipeline_io_to_int_bits_uop_lrs3;\t// @[core.scala:80:37]\n wire _FpPipeline_io_to_int_bits_uop_ldst_val;\t// @[core.scala:80:37]\n wire [1:0] _FpPipeline_io_to_int_bits_uop_dst_rtype;\t// @[core.scala:80:37]\n wire [1:0] _FpPipeline_io_to_int_bits_uop_lrs1_rtype;\t// @[core.scala:80:37]\n wire [1:0] _FpPipeline_io_to_int_bits_uop_lrs2_rtype;\t// @[core.scala:80:37]\n wire _FpPipeline_io_to_int_bits_uop_frs3_en;\t// @[core.scala:80:37]\n wire _FpPipeline_io_to_int_bits_uop_fp_val;\t// @[core.scala:80:37]\n wire _FpPipeline_io_to_int_bits_uop_fp_single;\t// @[core.scala:80:37]\n wire _FpPipeline_io_to_int_bits_uop_xcpt_pf_if;\t// @[core.scala:80:37]\n wire _FpPipeline_io_to_int_bits_uop_xcpt_ae_if;\t// @[core.scala:80:37]\n wire _FpPipeline_io_to_int_bits_uop_xcpt_ma_if;\t// @[core.scala:80:37]\n wire _FpPipeline_io_to_int_bits_uop_bp_debug_if;\t// @[core.scala:80:37]\n wire _FpPipeline_io_to_int_bits_uop_bp_xcpt_if;\t// @[core.scala:80:37]\n wire [1:0] _FpPipeline_io_to_int_bits_uop_debug_fsrc;\t// @[core.scala:80:37]\n wire [1:0] _FpPipeline_io_to_int_bits_uop_debug_tsrc;\t// @[core.scala:80:37]\n wire [63:0] _FpPipeline_io_to_int_bits_data;\t// @[core.scala:80:37]\n wire _FpPipeline_io_to_int_bits_predicated;\t// @[core.scala:80:37]\n wire _FpPipeline_io_to_int_bits_fflags_valid;\t// @[core.scala:80:37]\n wire [6:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_uopc;\t// @[core.scala:80:37]\n wire [31:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_inst;\t// @[core.scala:80:37]\n wire [31:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_debug_inst;\t// @[core.scala:80:37]\n wire _FpPipeline_io_to_int_bits_fflags_bits_uop_is_rvc;\t// @[core.scala:80:37]\n wire [39:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_debug_pc;\t// @[core.scala:80:37]\n wire [2:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_iq_type;\t// @[core.scala:80:37]\n wire [9:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_fu_code;\t// @[core.scala:80:37]\n wire [3:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_ctrl_br_type;\t// @[core.scala:80:37]\n wire [1:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_ctrl_op1_sel;\t// @[core.scala:80:37]\n wire [2:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_ctrl_op2_sel;\t// @[core.scala:80:37]\n wire [2:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_ctrl_imm_sel;\t// @[core.scala:80:37]\n wire [4:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_ctrl_op_fcn;\t// @[core.scala:80:37]\n wire _FpPipeline_io_to_int_bits_fflags_bits_uop_ctrl_fcn_dw;\t// @[core.scala:80:37]\n wire [2:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_ctrl_csr_cmd;\t// @[core.scala:80:37]\n wire _FpPipeline_io_to_int_bits_fflags_bits_uop_ctrl_is_load;\t// @[core.scala:80:37]\n wire _FpPipeline_io_to_int_bits_fflags_bits_uop_ctrl_is_sta;\t// @[core.scala:80:37]\n wire _FpPipeline_io_to_int_bits_fflags_bits_uop_ctrl_is_std;\t// @[core.scala:80:37]\n wire [1:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_iw_state;\t// @[core.scala:80:37]\n wire _FpPipeline_io_to_int_bits_fflags_bits_uop_iw_p1_poisoned;\t// @[core.scala:80:37]\n wire _FpPipeline_io_to_int_bits_fflags_bits_uop_iw_p2_poisoned;\t// @[core.scala:80:37]\n wire _FpPipeline_io_to_int_bits_fflags_bits_uop_is_br;\t// @[core.scala:80:37]\n wire _FpPipeline_io_to_int_bits_fflags_bits_uop_is_jalr;\t// @[core.scala:80:37]\n wire _FpPipeline_io_to_int_bits_fflags_bits_uop_is_jal;\t// @[core.scala:80:37]\n wire _FpPipeline_io_to_int_bits_fflags_bits_uop_is_sfb;\t// @[core.scala:80:37]\n wire [15:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_br_mask;\t// @[core.scala:80:37]\n wire [3:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_br_tag;\t// @[core.scala:80:37]\n wire [4:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_ftq_idx;\t// @[core.scala:80:37]\n wire _FpPipeline_io_to_int_bits_fflags_bits_uop_edge_inst;\t// @[core.scala:80:37]\n wire [5:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_pc_lob;\t// @[core.scala:80:37]\n wire _FpPipeline_io_to_int_bits_fflags_bits_uop_taken;\t// @[core.scala:80:37]\n wire [19:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_imm_packed;\t// @[core.scala:80:37]\n wire [11:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_csr_addr;\t// @[core.scala:80:37]\n wire [6:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_rob_idx;\t// @[core.scala:80:37]\n wire [4:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_ldq_idx;\t// @[core.scala:80:37]\n wire [4:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_stq_idx;\t// @[core.scala:80:37]\n wire [1:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_rxq_idx;\t// @[core.scala:80:37]\n wire [6:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_pdst;\t// @[core.scala:80:37]\n wire [6:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_prs1;\t// @[core.scala:80:37]\n wire [6:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_prs2;\t// @[core.scala:80:37]\n wire [6:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_prs3;\t// @[core.scala:80:37]\n wire [4:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_ppred;\t// @[core.scala:80:37]\n wire _FpPipeline_io_to_int_bits_fflags_bits_uop_prs1_busy;\t// @[core.scala:80:37]\n wire _FpPipeline_io_to_int_bits_fflags_bits_uop_prs2_busy;\t// @[core.scala:80:37]\n wire _FpPipeline_io_to_int_bits_fflags_bits_uop_prs3_busy;\t// @[core.scala:80:37]\n wire _FpPipeline_io_to_int_bits_fflags_bits_uop_ppred_busy;\t// @[core.scala:80:37]\n wire [6:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_stale_pdst;\t// @[core.scala:80:37]\n wire _FpPipeline_io_to_int_bits_fflags_bits_uop_exception;\t// @[core.scala:80:37]\n wire [63:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_exc_cause;\t// @[core.scala:80:37]\n wire _FpPipeline_io_to_int_bits_fflags_bits_uop_bypassable;\t// @[core.scala:80:37]\n wire [4:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_mem_cmd;\t// @[core.scala:80:37]\n wire [1:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_mem_size;\t// @[core.scala:80:37]\n wire _FpPipeline_io_to_int_bits_fflags_bits_uop_mem_signed;\t// @[core.scala:80:37]\n wire _FpPipeline_io_to_int_bits_fflags_bits_uop_is_fence;\t// @[core.scala:80:37]\n wire _FpPipeline_io_to_int_bits_fflags_bits_uop_is_fencei;\t// @[core.scala:80:37]\n wire _FpPipeline_io_to_int_bits_fflags_bits_uop_is_amo;\t// @[core.scala:80:37]\n wire _FpPipeline_io_to_int_bits_fflags_bits_uop_uses_ldq;\t// @[core.scala:80:37]\n wire _FpPipeline_io_to_int_bits_fflags_bits_uop_uses_stq;\t// @[core.scala:80:37]\n wire _FpPipeline_io_to_int_bits_fflags_bits_uop_is_sys_pc2epc;\t// @[core.scala:80:37]\n wire _FpPipeline_io_to_int_bits_fflags_bits_uop_is_unique;\t// @[core.scala:80:37]\n wire _FpPipeline_io_to_int_bits_fflags_bits_uop_flush_on_commit;\t// @[core.scala:80:37]\n wire _FpPipeline_io_to_int_bits_fflags_bits_uop_ldst_is_rs1;\t// @[core.scala:80:37]\n wire [5:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_ldst;\t// @[core.scala:80:37]\n wire [5:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_lrs1;\t// @[core.scala:80:37]\n wire [5:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_lrs2;\t// @[core.scala:80:37]\n wire [5:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_lrs3;\t// @[core.scala:80:37]\n wire _FpPipeline_io_to_int_bits_fflags_bits_uop_ldst_val;\t// @[core.scala:80:37]\n wire [1:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_dst_rtype;\t// @[core.scala:80:37]\n wire [1:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_lrs1_rtype;\t// @[core.scala:80:37]\n wire [1:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_lrs2_rtype;\t// @[core.scala:80:37]\n wire _FpPipeline_io_to_int_bits_fflags_bits_uop_frs3_en;\t// @[core.scala:80:37]\n wire _FpPipeline_io_to_int_bits_fflags_bits_uop_fp_val;\t// @[core.scala:80:37]\n wire _FpPipeline_io_to_int_bits_fflags_bits_uop_fp_single;\t// @[core.scala:80:37]\n wire _FpPipeline_io_to_int_bits_fflags_bits_uop_xcpt_pf_if;\t// @[core.scala:80:37]\n wire _FpPipeline_io_to_int_bits_fflags_bits_uop_xcpt_ae_if;\t// @[core.scala:80:37]\n wire _FpPipeline_io_to_int_bits_fflags_bits_uop_xcpt_ma_if;\t// @[core.scala:80:37]\n wire _FpPipeline_io_to_int_bits_fflags_bits_uop_bp_debug_if;\t// @[core.scala:80:37]\n wire _FpPipeline_io_to_int_bits_fflags_bits_uop_bp_xcpt_if;\t// @[core.scala:80:37]\n wire [1:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_debug_fsrc;\t// @[core.scala:80:37]\n wire [1:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_debug_tsrc;\t// @[core.scala:80:37]\n wire [4:0] _FpPipeline_io_to_int_bits_fflags_bits_flags;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_0_valid;\t// @[core.scala:80:37]\n wire [6:0] _FpPipeline_io_wakeups_0_bits_uop_uopc;\t// @[core.scala:80:37]\n wire [31:0] _FpPipeline_io_wakeups_0_bits_uop_inst;\t// @[core.scala:80:37]\n wire [31:0] _FpPipeline_io_wakeups_0_bits_uop_debug_inst;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_0_bits_uop_is_rvc;\t// @[core.scala:80:37]\n wire [39:0] _FpPipeline_io_wakeups_0_bits_uop_debug_pc;\t// @[core.scala:80:37]\n wire [2:0] _FpPipeline_io_wakeups_0_bits_uop_iq_type;\t// @[core.scala:80:37]\n wire [9:0] _FpPipeline_io_wakeups_0_bits_uop_fu_code;\t// @[core.scala:80:37]\n wire [3:0] _FpPipeline_io_wakeups_0_bits_uop_ctrl_br_type;\t// @[core.scala:80:37]\n wire [1:0] _FpPipeline_io_wakeups_0_bits_uop_ctrl_op1_sel;\t// @[core.scala:80:37]\n wire [2:0] _FpPipeline_io_wakeups_0_bits_uop_ctrl_op2_sel;\t// @[core.scala:80:37]\n wire [2:0] _FpPipeline_io_wakeups_0_bits_uop_ctrl_imm_sel;\t// @[core.scala:80:37]\n wire [4:0] _FpPipeline_io_wakeups_0_bits_uop_ctrl_op_fcn;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_0_bits_uop_ctrl_fcn_dw;\t// @[core.scala:80:37]\n wire [2:0] _FpPipeline_io_wakeups_0_bits_uop_ctrl_csr_cmd;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_0_bits_uop_ctrl_is_load;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_0_bits_uop_ctrl_is_sta;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_0_bits_uop_ctrl_is_std;\t// @[core.scala:80:37]\n wire [1:0] _FpPipeline_io_wakeups_0_bits_uop_iw_state;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_0_bits_uop_iw_p1_poisoned;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_0_bits_uop_iw_p2_poisoned;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_0_bits_uop_is_br;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_0_bits_uop_is_jalr;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_0_bits_uop_is_jal;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_0_bits_uop_is_sfb;\t// @[core.scala:80:37]\n wire [15:0] _FpPipeline_io_wakeups_0_bits_uop_br_mask;\t// @[core.scala:80:37]\n wire [3:0] _FpPipeline_io_wakeups_0_bits_uop_br_tag;\t// @[core.scala:80:37]\n wire [4:0] _FpPipeline_io_wakeups_0_bits_uop_ftq_idx;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_0_bits_uop_edge_inst;\t// @[core.scala:80:37]\n wire [5:0] _FpPipeline_io_wakeups_0_bits_uop_pc_lob;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_0_bits_uop_taken;\t// @[core.scala:80:37]\n wire [19:0] _FpPipeline_io_wakeups_0_bits_uop_imm_packed;\t// @[core.scala:80:37]\n wire [11:0] _FpPipeline_io_wakeups_0_bits_uop_csr_addr;\t// @[core.scala:80:37]\n wire [6:0] _FpPipeline_io_wakeups_0_bits_uop_rob_idx;\t// @[core.scala:80:37]\n wire [4:0] _FpPipeline_io_wakeups_0_bits_uop_ldq_idx;\t// @[core.scala:80:37]\n wire [4:0] _FpPipeline_io_wakeups_0_bits_uop_stq_idx;\t// @[core.scala:80:37]\n wire [1:0] _FpPipeline_io_wakeups_0_bits_uop_rxq_idx;\t// @[core.scala:80:37]\n wire [6:0] _FpPipeline_io_wakeups_0_bits_uop_pdst;\t// @[core.scala:80:37]\n wire [6:0] _FpPipeline_io_wakeups_0_bits_uop_prs1;\t// @[core.scala:80:37]\n wire [6:0] _FpPipeline_io_wakeups_0_bits_uop_prs2;\t// @[core.scala:80:37]\n wire [6:0] _FpPipeline_io_wakeups_0_bits_uop_prs3;\t// @[core.scala:80:37]\n wire [4:0] _FpPipeline_io_wakeups_0_bits_uop_ppred;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_0_bits_uop_prs1_busy;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_0_bits_uop_prs2_busy;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_0_bits_uop_prs3_busy;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_0_bits_uop_ppred_busy;\t// @[core.scala:80:37]\n wire [6:0] _FpPipeline_io_wakeups_0_bits_uop_stale_pdst;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_0_bits_uop_exception;\t// @[core.scala:80:37]\n wire [63:0] _FpPipeline_io_wakeups_0_bits_uop_exc_cause;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_0_bits_uop_bypassable;\t// @[core.scala:80:37]\n wire [4:0] _FpPipeline_io_wakeups_0_bits_uop_mem_cmd;\t// @[core.scala:80:37]\n wire [1:0] _FpPipeline_io_wakeups_0_bits_uop_mem_size;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_0_bits_uop_mem_signed;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_0_bits_uop_is_fence;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_0_bits_uop_is_fencei;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_0_bits_uop_is_amo;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_0_bits_uop_uses_ldq;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_0_bits_uop_uses_stq;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_0_bits_uop_is_sys_pc2epc;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_0_bits_uop_is_unique;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_0_bits_uop_flush_on_commit;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_0_bits_uop_ldst_is_rs1;\t// @[core.scala:80:37]\n wire [5:0] _FpPipeline_io_wakeups_0_bits_uop_ldst;\t// @[core.scala:80:37]\n wire [5:0] _FpPipeline_io_wakeups_0_bits_uop_lrs1;\t// @[core.scala:80:37]\n wire [5:0] _FpPipeline_io_wakeups_0_bits_uop_lrs2;\t// @[core.scala:80:37]\n wire [5:0] _FpPipeline_io_wakeups_0_bits_uop_lrs3;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_0_bits_uop_ldst_val;\t// @[core.scala:80:37]\n wire [1:0] _FpPipeline_io_wakeups_0_bits_uop_dst_rtype;\t// @[core.scala:80:37]\n wire [1:0] _FpPipeline_io_wakeups_0_bits_uop_lrs1_rtype;\t// @[core.scala:80:37]\n wire [1:0] _FpPipeline_io_wakeups_0_bits_uop_lrs2_rtype;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_0_bits_uop_frs3_en;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_0_bits_uop_fp_val;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_0_bits_uop_fp_single;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_0_bits_uop_xcpt_pf_if;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_0_bits_uop_xcpt_ae_if;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_0_bits_uop_xcpt_ma_if;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_0_bits_uop_bp_debug_if;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_0_bits_uop_bp_xcpt_if;\t// @[core.scala:80:37]\n wire [1:0] _FpPipeline_io_wakeups_0_bits_uop_debug_fsrc;\t// @[core.scala:80:37]\n wire [1:0] _FpPipeline_io_wakeups_0_bits_uop_debug_tsrc;\t// @[core.scala:80:37]\n wire [64:0] _FpPipeline_io_wakeups_0_bits_data;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_0_bits_predicated;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_0_bits_fflags_valid;\t// @[core.scala:80:37]\n wire [6:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_uopc;\t// @[core.scala:80:37]\n wire [31:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_inst;\t// @[core.scala:80:37]\n wire [31:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_debug_inst;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_is_rvc;\t// @[core.scala:80:37]\n wire [39:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_debug_pc;\t// @[core.scala:80:37]\n wire [2:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_iq_type;\t// @[core.scala:80:37]\n wire [9:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_fu_code;\t// @[core.scala:80:37]\n wire [3:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_ctrl_br_type;\t// @[core.scala:80:37]\n wire [1:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_ctrl_op1_sel;\t// @[core.scala:80:37]\n wire [2:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_ctrl_op2_sel;\t// @[core.scala:80:37]\n wire [2:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_ctrl_imm_sel;\t// @[core.scala:80:37]\n wire [4:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_ctrl_op_fcn;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_ctrl_fcn_dw;\t// @[core.scala:80:37]\n wire [2:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_ctrl_csr_cmd;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_ctrl_is_load;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_ctrl_is_sta;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_ctrl_is_std;\t// @[core.scala:80:37]\n wire [1:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_iw_state;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_iw_p1_poisoned;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_iw_p2_poisoned;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_is_br;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_is_jalr;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_is_jal;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_is_sfb;\t// @[core.scala:80:37]\n wire [15:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_br_mask;\t// @[core.scala:80:37]\n wire [3:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_br_tag;\t// @[core.scala:80:37]\n wire [4:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_ftq_idx;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_edge_inst;\t// @[core.scala:80:37]\n wire [5:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_pc_lob;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_taken;\t// @[core.scala:80:37]\n wire [19:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_imm_packed;\t// @[core.scala:80:37]\n wire [11:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_csr_addr;\t// @[core.scala:80:37]\n wire [6:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_rob_idx;\t// @[core.scala:80:37]\n wire [4:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_ldq_idx;\t// @[core.scala:80:37]\n wire [4:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_stq_idx;\t// @[core.scala:80:37]\n wire [1:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_rxq_idx;\t// @[core.scala:80:37]\n wire [6:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_pdst;\t// @[core.scala:80:37]\n wire [6:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_prs1;\t// @[core.scala:80:37]\n wire [6:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_prs2;\t// @[core.scala:80:37]\n wire [6:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_prs3;\t// @[core.scala:80:37]\n wire [4:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_ppred;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_prs1_busy;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_prs2_busy;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_prs3_busy;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_ppred_busy;\t// @[core.scala:80:37]\n wire [6:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_stale_pdst;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_exception;\t// @[core.scala:80:37]\n wire [63:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_exc_cause;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_bypassable;\t// @[core.scala:80:37]\n wire [4:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_mem_cmd;\t// @[core.scala:80:37]\n wire [1:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_mem_size;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_mem_signed;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_is_fence;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_is_fencei;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_is_amo;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_uses_ldq;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_uses_stq;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_is_sys_pc2epc;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_is_unique;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_flush_on_commit;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_ldst_is_rs1;\t// @[core.scala:80:37]\n wire [5:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_ldst;\t// @[core.scala:80:37]\n wire [5:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_lrs1;\t// @[core.scala:80:37]\n wire [5:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_lrs2;\t// @[core.scala:80:37]\n wire [5:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_lrs3;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_ldst_val;\t// @[core.scala:80:37]\n wire [1:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_dst_rtype;\t// @[core.scala:80:37]\n wire [1:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_lrs1_rtype;\t// @[core.scala:80:37]\n wire [1:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_lrs2_rtype;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_frs3_en;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_fp_val;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_fp_single;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_xcpt_pf_if;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_xcpt_ae_if;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_xcpt_ma_if;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_bp_debug_if;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_bp_xcpt_if;\t// @[core.scala:80:37]\n wire [1:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_debug_fsrc;\t// @[core.scala:80:37]\n wire [1:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_debug_tsrc;\t// @[core.scala:80:37]\n wire [4:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_flags;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_1_valid;\t// @[core.scala:80:37]\n wire [6:0] _FpPipeline_io_wakeups_1_bits_uop_uopc;\t// @[core.scala:80:37]\n wire [31:0] _FpPipeline_io_wakeups_1_bits_uop_inst;\t// @[core.scala:80:37]\n wire [31:0] _FpPipeline_io_wakeups_1_bits_uop_debug_inst;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_1_bits_uop_is_rvc;\t// @[core.scala:80:37]\n wire [39:0] _FpPipeline_io_wakeups_1_bits_uop_debug_pc;\t// @[core.scala:80:37]\n wire [2:0] _FpPipeline_io_wakeups_1_bits_uop_iq_type;\t// @[core.scala:80:37]\n wire [9:0] _FpPipeline_io_wakeups_1_bits_uop_fu_code;\t// @[core.scala:80:37]\n wire [3:0] _FpPipeline_io_wakeups_1_bits_uop_ctrl_br_type;\t// @[core.scala:80:37]\n wire [1:0] _FpPipeline_io_wakeups_1_bits_uop_ctrl_op1_sel;\t// @[core.scala:80:37]\n wire [2:0] _FpPipeline_io_wakeups_1_bits_uop_ctrl_op2_sel;\t// @[core.scala:80:37]\n wire [2:0] _FpPipeline_io_wakeups_1_bits_uop_ctrl_imm_sel;\t// @[core.scala:80:37]\n wire [4:0] _FpPipeline_io_wakeups_1_bits_uop_ctrl_op_fcn;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_1_bits_uop_ctrl_fcn_dw;\t// @[core.scala:80:37]\n wire [2:0] _FpPipeline_io_wakeups_1_bits_uop_ctrl_csr_cmd;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_1_bits_uop_ctrl_is_load;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_1_bits_uop_ctrl_is_sta;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_1_bits_uop_ctrl_is_std;\t// @[core.scala:80:37]\n wire [1:0] _FpPipeline_io_wakeups_1_bits_uop_iw_state;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_1_bits_uop_iw_p1_poisoned;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_1_bits_uop_iw_p2_poisoned;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_1_bits_uop_is_br;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_1_bits_uop_is_jalr;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_1_bits_uop_is_jal;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_1_bits_uop_is_sfb;\t// @[core.scala:80:37]\n wire [15:0] _FpPipeline_io_wakeups_1_bits_uop_br_mask;\t// @[core.scala:80:37]\n wire [3:0] _FpPipeline_io_wakeups_1_bits_uop_br_tag;\t// @[core.scala:80:37]\n wire [4:0] _FpPipeline_io_wakeups_1_bits_uop_ftq_idx;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_1_bits_uop_edge_inst;\t// @[core.scala:80:37]\n wire [5:0] _FpPipeline_io_wakeups_1_bits_uop_pc_lob;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_1_bits_uop_taken;\t// @[core.scala:80:37]\n wire [19:0] _FpPipeline_io_wakeups_1_bits_uop_imm_packed;\t// @[core.scala:80:37]\n wire [11:0] _FpPipeline_io_wakeups_1_bits_uop_csr_addr;\t// @[core.scala:80:37]\n wire [6:0] _FpPipeline_io_wakeups_1_bits_uop_rob_idx;\t// @[core.scala:80:37]\n wire [4:0] _FpPipeline_io_wakeups_1_bits_uop_ldq_idx;\t// @[core.scala:80:37]\n wire [4:0] _FpPipeline_io_wakeups_1_bits_uop_stq_idx;\t// @[core.scala:80:37]\n wire [1:0] _FpPipeline_io_wakeups_1_bits_uop_rxq_idx;\t// @[core.scala:80:37]\n wire [6:0] _FpPipeline_io_wakeups_1_bits_uop_pdst;\t// @[core.scala:80:37]\n wire [6:0] _FpPipeline_io_wakeups_1_bits_uop_prs1;\t// @[core.scala:80:37]\n wire [6:0] _FpPipeline_io_wakeups_1_bits_uop_prs2;\t// @[core.scala:80:37]\n wire [6:0] _FpPipeline_io_wakeups_1_bits_uop_prs3;\t// @[core.scala:80:37]\n wire [4:0] _FpPipeline_io_wakeups_1_bits_uop_ppred;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_1_bits_uop_prs1_busy;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_1_bits_uop_prs2_busy;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_1_bits_uop_prs3_busy;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_1_bits_uop_ppred_busy;\t// @[core.scala:80:37]\n wire [6:0] _FpPipeline_io_wakeups_1_bits_uop_stale_pdst;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_1_bits_uop_exception;\t// @[core.scala:80:37]\n wire [63:0] _FpPipeline_io_wakeups_1_bits_uop_exc_cause;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_1_bits_uop_bypassable;\t// @[core.scala:80:37]\n wire [4:0] _FpPipeline_io_wakeups_1_bits_uop_mem_cmd;\t// @[core.scala:80:37]\n wire [1:0] _FpPipeline_io_wakeups_1_bits_uop_mem_size;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_1_bits_uop_mem_signed;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_1_bits_uop_is_fence;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_1_bits_uop_is_fencei;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_1_bits_uop_is_amo;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_1_bits_uop_uses_ldq;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_1_bits_uop_uses_stq;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_1_bits_uop_is_sys_pc2epc;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_1_bits_uop_is_unique;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_1_bits_uop_flush_on_commit;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_1_bits_uop_ldst_is_rs1;\t// @[core.scala:80:37]\n wire [5:0] _FpPipeline_io_wakeups_1_bits_uop_ldst;\t// @[core.scala:80:37]\n wire [5:0] _FpPipeline_io_wakeups_1_bits_uop_lrs1;\t// @[core.scala:80:37]\n wire [5:0] _FpPipeline_io_wakeups_1_bits_uop_lrs2;\t// @[core.scala:80:37]\n wire [5:0] _FpPipeline_io_wakeups_1_bits_uop_lrs3;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_1_bits_uop_ldst_val;\t// @[core.scala:80:37]\n wire [1:0] _FpPipeline_io_wakeups_1_bits_uop_dst_rtype;\t// @[core.scala:80:37]\n wire [1:0] _FpPipeline_io_wakeups_1_bits_uop_lrs1_rtype;\t// @[core.scala:80:37]\n wire [1:0] _FpPipeline_io_wakeups_1_bits_uop_lrs2_rtype;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_1_bits_uop_frs3_en;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_1_bits_uop_fp_val;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_1_bits_uop_fp_single;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_1_bits_uop_xcpt_pf_if;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_1_bits_uop_xcpt_ae_if;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_1_bits_uop_xcpt_ma_if;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_1_bits_uop_bp_debug_if;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_1_bits_uop_bp_xcpt_if;\t// @[core.scala:80:37]\n wire [1:0] _FpPipeline_io_wakeups_1_bits_uop_debug_fsrc;\t// @[core.scala:80:37]\n wire [1:0] _FpPipeline_io_wakeups_1_bits_uop_debug_tsrc;\t// @[core.scala:80:37]\n wire [64:0] _FpPipeline_io_wakeups_1_bits_data;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_1_bits_fflags_valid;\t// @[core.scala:80:37]\n wire [6:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_uopc;\t// @[core.scala:80:37]\n wire [31:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_inst;\t// @[core.scala:80:37]\n wire [31:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_debug_inst;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_is_rvc;\t// @[core.scala:80:37]\n wire [39:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_debug_pc;\t// @[core.scala:80:37]\n wire [2:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_iq_type;\t// @[core.scala:80:37]\n wire [9:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_fu_code;\t// @[core.scala:80:37]\n wire [3:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_ctrl_br_type;\t// @[core.scala:80:37]\n wire [1:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_ctrl_op1_sel;\t// @[core.scala:80:37]\n wire [2:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_ctrl_op2_sel;\t// @[core.scala:80:37]\n wire [2:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_ctrl_imm_sel;\t// @[core.scala:80:37]\n wire [4:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_ctrl_op_fcn;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_ctrl_fcn_dw;\t// @[core.scala:80:37]\n wire [2:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_ctrl_csr_cmd;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_ctrl_is_load;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_ctrl_is_sta;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_ctrl_is_std;\t// @[core.scala:80:37]\n wire [1:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_iw_state;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_iw_p1_poisoned;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_iw_p2_poisoned;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_is_br;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_is_jalr;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_is_jal;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_is_sfb;\t// @[core.scala:80:37]\n wire [15:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_br_mask;\t// @[core.scala:80:37]\n wire [3:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_br_tag;\t// @[core.scala:80:37]\n wire [4:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_ftq_idx;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_edge_inst;\t// @[core.scala:80:37]\n wire [5:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_pc_lob;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_taken;\t// @[core.scala:80:37]\n wire [19:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_imm_packed;\t// @[core.scala:80:37]\n wire [11:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_csr_addr;\t// @[core.scala:80:37]\n wire [6:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_rob_idx;\t// @[core.scala:80:37]\n wire [4:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_ldq_idx;\t// @[core.scala:80:37]\n wire [4:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_stq_idx;\t// @[core.scala:80:37]\n wire [1:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_rxq_idx;\t// @[core.scala:80:37]\n wire [6:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_pdst;\t// @[core.scala:80:37]\n wire [6:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_prs1;\t// @[core.scala:80:37]\n wire [6:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_prs2;\t// @[core.scala:80:37]\n wire [6:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_prs3;\t// @[core.scala:80:37]\n wire [4:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_ppred;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_prs1_busy;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_prs2_busy;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_prs3_busy;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_ppred_busy;\t// @[core.scala:80:37]\n wire [6:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_stale_pdst;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_exception;\t// @[core.scala:80:37]\n wire [63:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_exc_cause;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_bypassable;\t// @[core.scala:80:37]\n wire [4:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_mem_cmd;\t// @[core.scala:80:37]\n wire [1:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_mem_size;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_mem_signed;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_is_fence;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_is_fencei;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_is_amo;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_uses_ldq;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_uses_stq;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_is_sys_pc2epc;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_is_unique;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_flush_on_commit;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_ldst_is_rs1;\t// @[core.scala:80:37]\n wire [5:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_ldst;\t// @[core.scala:80:37]\n wire [5:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_lrs1;\t// @[core.scala:80:37]\n wire [5:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_lrs2;\t// @[core.scala:80:37]\n wire [5:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_lrs3;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_ldst_val;\t// @[core.scala:80:37]\n wire [1:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_dst_rtype;\t// @[core.scala:80:37]\n wire [1:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_lrs1_rtype;\t// @[core.scala:80:37]\n wire [1:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_lrs2_rtype;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_frs3_en;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_fp_val;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_fp_single;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_xcpt_pf_if;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_xcpt_ae_if;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_xcpt_ma_if;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_bp_debug_if;\t// @[core.scala:80:37]\n wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_bp_xcpt_if;\t// @[core.scala:80:37]\n wire [1:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_debug_fsrc;\t// @[core.scala:80:37]\n wire [1:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_debug_tsrc;\t// @[core.scala:80:37]\n wire [4:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_flags;\t// @[core.scala:80:37]\n wire [64:0] _FpPipeline_io_debug_wb_wdata_0;\t// @[core.scala:80:37]\n wire [64:0] _FpPipeline_io_debug_wb_wdata_1;\t// @[core.scala:80:37]\n wire _alu_exe_unit_2_io_iresp_valid;\t// @[execution-units.scala:119:32]\n wire [6:0] _alu_exe_unit_2_io_iresp_bits_uop_uopc;\t// @[execution-units.scala:119:32]\n wire [31:0] _alu_exe_unit_2_io_iresp_bits_uop_inst;\t// @[execution-units.scala:119:32]\n wire [31:0] _alu_exe_unit_2_io_iresp_bits_uop_debug_inst;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_2_io_iresp_bits_uop_is_rvc;\t// @[execution-units.scala:119:32]\n wire [39:0] _alu_exe_unit_2_io_iresp_bits_uop_debug_pc;\t// @[execution-units.scala:119:32]\n wire [2:0] _alu_exe_unit_2_io_iresp_bits_uop_iq_type;\t// @[execution-units.scala:119:32]\n wire [9:0] _alu_exe_unit_2_io_iresp_bits_uop_fu_code;\t// @[execution-units.scala:119:32]\n wire [3:0] _alu_exe_unit_2_io_iresp_bits_uop_ctrl_br_type;\t// @[execution-units.scala:119:32]\n wire [1:0] _alu_exe_unit_2_io_iresp_bits_uop_ctrl_op1_sel;\t// @[execution-units.scala:119:32]\n wire [2:0] _alu_exe_unit_2_io_iresp_bits_uop_ctrl_op2_sel;\t// @[execution-units.scala:119:32]\n wire [2:0] _alu_exe_unit_2_io_iresp_bits_uop_ctrl_imm_sel;\t// @[execution-units.scala:119:32]\n wire [4:0] _alu_exe_unit_2_io_iresp_bits_uop_ctrl_op_fcn;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_2_io_iresp_bits_uop_ctrl_fcn_dw;\t// @[execution-units.scala:119:32]\n wire [2:0] _alu_exe_unit_2_io_iresp_bits_uop_ctrl_csr_cmd;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_2_io_iresp_bits_uop_ctrl_is_load;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_2_io_iresp_bits_uop_ctrl_is_sta;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_2_io_iresp_bits_uop_ctrl_is_std;\t// @[execution-units.scala:119:32]\n wire [1:0] _alu_exe_unit_2_io_iresp_bits_uop_iw_state;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_2_io_iresp_bits_uop_iw_p1_poisoned;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_2_io_iresp_bits_uop_iw_p2_poisoned;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_2_io_iresp_bits_uop_is_br;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_2_io_iresp_bits_uop_is_jalr;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_2_io_iresp_bits_uop_is_jal;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_2_io_iresp_bits_uop_is_sfb;\t// @[execution-units.scala:119:32]\n wire [15:0] _alu_exe_unit_2_io_iresp_bits_uop_br_mask;\t// @[execution-units.scala:119:32]\n wire [3:0] _alu_exe_unit_2_io_iresp_bits_uop_br_tag;\t// @[execution-units.scala:119:32]\n wire [4:0] _alu_exe_unit_2_io_iresp_bits_uop_ftq_idx;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_2_io_iresp_bits_uop_edge_inst;\t// @[execution-units.scala:119:32]\n wire [5:0] _alu_exe_unit_2_io_iresp_bits_uop_pc_lob;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_2_io_iresp_bits_uop_taken;\t// @[execution-units.scala:119:32]\n wire [19:0] _alu_exe_unit_2_io_iresp_bits_uop_imm_packed;\t// @[execution-units.scala:119:32]\n wire [11:0] _alu_exe_unit_2_io_iresp_bits_uop_csr_addr;\t// @[execution-units.scala:119:32]\n wire [6:0] _alu_exe_unit_2_io_iresp_bits_uop_rob_idx;\t// @[execution-units.scala:119:32]\n wire [4:0] _alu_exe_unit_2_io_iresp_bits_uop_ldq_idx;\t// @[execution-units.scala:119:32]\n wire [4:0] _alu_exe_unit_2_io_iresp_bits_uop_stq_idx;\t// @[execution-units.scala:119:32]\n wire [1:0] _alu_exe_unit_2_io_iresp_bits_uop_rxq_idx;\t// @[execution-units.scala:119:32]\n wire [6:0] _alu_exe_unit_2_io_iresp_bits_uop_pdst;\t// @[execution-units.scala:119:32]\n wire [6:0] _alu_exe_unit_2_io_iresp_bits_uop_prs1;\t// @[execution-units.scala:119:32]\n wire [6:0] _alu_exe_unit_2_io_iresp_bits_uop_prs2;\t// @[execution-units.scala:119:32]\n wire [6:0] _alu_exe_unit_2_io_iresp_bits_uop_prs3;\t// @[execution-units.scala:119:32]\n wire [4:0] _alu_exe_unit_2_io_iresp_bits_uop_ppred;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_2_io_iresp_bits_uop_prs1_busy;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_2_io_iresp_bits_uop_prs2_busy;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_2_io_iresp_bits_uop_prs3_busy;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_2_io_iresp_bits_uop_ppred_busy;\t// @[execution-units.scala:119:32]\n wire [6:0] _alu_exe_unit_2_io_iresp_bits_uop_stale_pdst;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_2_io_iresp_bits_uop_exception;\t// @[execution-units.scala:119:32]\n wire [63:0] _alu_exe_unit_2_io_iresp_bits_uop_exc_cause;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_2_io_iresp_bits_uop_bypassable;\t// @[execution-units.scala:119:32]\n wire [4:0] _alu_exe_unit_2_io_iresp_bits_uop_mem_cmd;\t// @[execution-units.scala:119:32]\n wire [1:0] _alu_exe_unit_2_io_iresp_bits_uop_mem_size;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_2_io_iresp_bits_uop_mem_signed;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_2_io_iresp_bits_uop_is_fence;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_2_io_iresp_bits_uop_is_fencei;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_2_io_iresp_bits_uop_is_amo;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_2_io_iresp_bits_uop_uses_ldq;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_2_io_iresp_bits_uop_uses_stq;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_2_io_iresp_bits_uop_is_sys_pc2epc;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_2_io_iresp_bits_uop_is_unique;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_2_io_iresp_bits_uop_flush_on_commit;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_2_io_iresp_bits_uop_ldst_is_rs1;\t// @[execution-units.scala:119:32]\n wire [5:0] _alu_exe_unit_2_io_iresp_bits_uop_ldst;\t// @[execution-units.scala:119:32]\n wire [5:0] _alu_exe_unit_2_io_iresp_bits_uop_lrs1;\t// @[execution-units.scala:119:32]\n wire [5:0] _alu_exe_unit_2_io_iresp_bits_uop_lrs2;\t// @[execution-units.scala:119:32]\n wire [5:0] _alu_exe_unit_2_io_iresp_bits_uop_lrs3;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_2_io_iresp_bits_uop_ldst_val;\t// @[execution-units.scala:119:32]\n wire [1:0] _alu_exe_unit_2_io_iresp_bits_uop_dst_rtype;\t// @[execution-units.scala:119:32]\n wire [1:0] _alu_exe_unit_2_io_iresp_bits_uop_lrs1_rtype;\t// @[execution-units.scala:119:32]\n wire [1:0] _alu_exe_unit_2_io_iresp_bits_uop_lrs2_rtype;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_2_io_iresp_bits_uop_frs3_en;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_2_io_iresp_bits_uop_fp_val;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_2_io_iresp_bits_uop_fp_single;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_2_io_iresp_bits_uop_xcpt_pf_if;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_2_io_iresp_bits_uop_xcpt_ae_if;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_2_io_iresp_bits_uop_xcpt_ma_if;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_2_io_iresp_bits_uop_bp_debug_if;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_2_io_iresp_bits_uop_bp_xcpt_if;\t// @[execution-units.scala:119:32]\n wire [1:0] _alu_exe_unit_2_io_iresp_bits_uop_debug_fsrc;\t// @[execution-units.scala:119:32]\n wire [1:0] _alu_exe_unit_2_io_iresp_bits_uop_debug_tsrc;\t// @[execution-units.scala:119:32]\n wire [64:0] _alu_exe_unit_2_io_iresp_bits_data;\t// @[execution-units.scala:119:32]\n wire [64:0] _alu_exe_unit_2_io_bypass_0_bits_data;\t// @[execution-units.scala:119:32]\n wire [64:0] _alu_exe_unit_2_io_bypass_1_bits_data;\t// @[execution-units.scala:119:32]\n wire [64:0] _alu_exe_unit_2_io_bypass_2_bits_data;\t// @[execution-units.scala:119:32]\n wire [6:0] _alu_exe_unit_2_io_brinfo_uop_uopc;\t// @[execution-units.scala:119:32]\n wire [31:0] _alu_exe_unit_2_io_brinfo_uop_inst;\t// @[execution-units.scala:119:32]\n wire [31:0] _alu_exe_unit_2_io_brinfo_uop_debug_inst;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_2_io_brinfo_uop_is_rvc;\t// @[execution-units.scala:119:32]\n wire [39:0] _alu_exe_unit_2_io_brinfo_uop_debug_pc;\t// @[execution-units.scala:119:32]\n wire [2:0] _alu_exe_unit_2_io_brinfo_uop_iq_type;\t// @[execution-units.scala:119:32]\n wire [9:0] _alu_exe_unit_2_io_brinfo_uop_fu_code;\t// @[execution-units.scala:119:32]\n wire [3:0] _alu_exe_unit_2_io_brinfo_uop_ctrl_br_type;\t// @[execution-units.scala:119:32]\n wire [1:0] _alu_exe_unit_2_io_brinfo_uop_ctrl_op1_sel;\t// @[execution-units.scala:119:32]\n wire [2:0] _alu_exe_unit_2_io_brinfo_uop_ctrl_op2_sel;\t// @[execution-units.scala:119:32]\n wire [2:0] _alu_exe_unit_2_io_brinfo_uop_ctrl_imm_sel;\t// @[execution-units.scala:119:32]\n wire [4:0] _alu_exe_unit_2_io_brinfo_uop_ctrl_op_fcn;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_2_io_brinfo_uop_ctrl_fcn_dw;\t// @[execution-units.scala:119:32]\n wire [2:0] _alu_exe_unit_2_io_brinfo_uop_ctrl_csr_cmd;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_2_io_brinfo_uop_ctrl_is_load;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_2_io_brinfo_uop_ctrl_is_sta;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_2_io_brinfo_uop_ctrl_is_std;\t// @[execution-units.scala:119:32]\n wire [1:0] _alu_exe_unit_2_io_brinfo_uop_iw_state;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_2_io_brinfo_uop_iw_p1_poisoned;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_2_io_brinfo_uop_iw_p2_poisoned;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_2_io_brinfo_uop_is_br;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_2_io_brinfo_uop_is_jalr;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_2_io_brinfo_uop_is_jal;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_2_io_brinfo_uop_is_sfb;\t// @[execution-units.scala:119:32]\n wire [15:0] _alu_exe_unit_2_io_brinfo_uop_br_mask;\t// @[execution-units.scala:119:32]\n wire [3:0] _alu_exe_unit_2_io_brinfo_uop_br_tag;\t// @[execution-units.scala:119:32]\n wire [4:0] _alu_exe_unit_2_io_brinfo_uop_ftq_idx;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_2_io_brinfo_uop_edge_inst;\t// @[execution-units.scala:119:32]\n wire [5:0] _alu_exe_unit_2_io_brinfo_uop_pc_lob;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_2_io_brinfo_uop_taken;\t// @[execution-units.scala:119:32]\n wire [19:0] _alu_exe_unit_2_io_brinfo_uop_imm_packed;\t// @[execution-units.scala:119:32]\n wire [11:0] _alu_exe_unit_2_io_brinfo_uop_csr_addr;\t// @[execution-units.scala:119:32]\n wire [6:0] _alu_exe_unit_2_io_brinfo_uop_rob_idx;\t// @[execution-units.scala:119:32]\n wire [4:0] _alu_exe_unit_2_io_brinfo_uop_ldq_idx;\t// @[execution-units.scala:119:32]\n wire [4:0] _alu_exe_unit_2_io_brinfo_uop_stq_idx;\t// @[execution-units.scala:119:32]\n wire [1:0] _alu_exe_unit_2_io_brinfo_uop_rxq_idx;\t// @[execution-units.scala:119:32]\n wire [6:0] _alu_exe_unit_2_io_brinfo_uop_pdst;\t// @[execution-units.scala:119:32]\n wire [6:0] _alu_exe_unit_2_io_brinfo_uop_prs1;\t// @[execution-units.scala:119:32]\n wire [6:0] _alu_exe_unit_2_io_brinfo_uop_prs2;\t// @[execution-units.scala:119:32]\n wire [6:0] _alu_exe_unit_2_io_brinfo_uop_prs3;\t// @[execution-units.scala:119:32]\n wire [4:0] _alu_exe_unit_2_io_brinfo_uop_ppred;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_2_io_brinfo_uop_prs1_busy;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_2_io_brinfo_uop_prs2_busy;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_2_io_brinfo_uop_prs3_busy;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_2_io_brinfo_uop_ppred_busy;\t// @[execution-units.scala:119:32]\n wire [6:0] _alu_exe_unit_2_io_brinfo_uop_stale_pdst;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_2_io_brinfo_uop_exception;\t// @[execution-units.scala:119:32]\n wire [63:0] _alu_exe_unit_2_io_brinfo_uop_exc_cause;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_2_io_brinfo_uop_bypassable;\t// @[execution-units.scala:119:32]\n wire [4:0] _alu_exe_unit_2_io_brinfo_uop_mem_cmd;\t// @[execution-units.scala:119:32]\n wire [1:0] _alu_exe_unit_2_io_brinfo_uop_mem_size;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_2_io_brinfo_uop_mem_signed;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_2_io_brinfo_uop_is_fence;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_2_io_brinfo_uop_is_fencei;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_2_io_brinfo_uop_is_amo;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_2_io_brinfo_uop_uses_ldq;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_2_io_brinfo_uop_uses_stq;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_2_io_brinfo_uop_is_sys_pc2epc;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_2_io_brinfo_uop_is_unique;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_2_io_brinfo_uop_flush_on_commit;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_2_io_brinfo_uop_ldst_is_rs1;\t// @[execution-units.scala:119:32]\n wire [5:0] _alu_exe_unit_2_io_brinfo_uop_ldst;\t// @[execution-units.scala:119:32]\n wire [5:0] _alu_exe_unit_2_io_brinfo_uop_lrs1;\t// @[execution-units.scala:119:32]\n wire [5:0] _alu_exe_unit_2_io_brinfo_uop_lrs2;\t// @[execution-units.scala:119:32]\n wire [5:0] _alu_exe_unit_2_io_brinfo_uop_lrs3;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_2_io_brinfo_uop_ldst_val;\t// @[execution-units.scala:119:32]\n wire [1:0] _alu_exe_unit_2_io_brinfo_uop_dst_rtype;\t// @[execution-units.scala:119:32]\n wire [1:0] _alu_exe_unit_2_io_brinfo_uop_lrs1_rtype;\t// @[execution-units.scala:119:32]\n wire [1:0] _alu_exe_unit_2_io_brinfo_uop_lrs2_rtype;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_2_io_brinfo_uop_frs3_en;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_2_io_brinfo_uop_fp_val;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_2_io_brinfo_uop_fp_single;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_2_io_brinfo_uop_xcpt_pf_if;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_2_io_brinfo_uop_xcpt_ae_if;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_2_io_brinfo_uop_xcpt_ma_if;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_2_io_brinfo_uop_bp_debug_if;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_2_io_brinfo_uop_bp_xcpt_if;\t// @[execution-units.scala:119:32]\n wire [1:0] _alu_exe_unit_2_io_brinfo_uop_debug_fsrc;\t// @[execution-units.scala:119:32]\n wire [1:0] _alu_exe_unit_2_io_brinfo_uop_debug_tsrc;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_2_io_brinfo_valid;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_2_io_brinfo_mispredict;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_2_io_brinfo_taken;\t// @[execution-units.scala:119:32]\n wire [2:0] _alu_exe_unit_2_io_brinfo_cfi_type;\t// @[execution-units.scala:119:32]\n wire [1:0] _alu_exe_unit_2_io_brinfo_pc_sel;\t// @[execution-units.scala:119:32]\n wire [20:0] _alu_exe_unit_2_io_brinfo_target_offset;\t// @[execution-units.scala:119:32]\n wire [9:0] _alu_exe_unit_1_io_fu_types;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_iresp_valid;\t// @[execution-units.scala:119:32]\n wire [6:0] _alu_exe_unit_1_io_iresp_bits_uop_uopc;\t// @[execution-units.scala:119:32]\n wire [31:0] _alu_exe_unit_1_io_iresp_bits_uop_inst;\t// @[execution-units.scala:119:32]\n wire [31:0] _alu_exe_unit_1_io_iresp_bits_uop_debug_inst;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_iresp_bits_uop_is_rvc;\t// @[execution-units.scala:119:32]\n wire [39:0] _alu_exe_unit_1_io_iresp_bits_uop_debug_pc;\t// @[execution-units.scala:119:32]\n wire [2:0] _alu_exe_unit_1_io_iresp_bits_uop_iq_type;\t// @[execution-units.scala:119:32]\n wire [9:0] _alu_exe_unit_1_io_iresp_bits_uop_fu_code;\t// @[execution-units.scala:119:32]\n wire [3:0] _alu_exe_unit_1_io_iresp_bits_uop_ctrl_br_type;\t// @[execution-units.scala:119:32]\n wire [1:0] _alu_exe_unit_1_io_iresp_bits_uop_ctrl_op1_sel;\t// @[execution-units.scala:119:32]\n wire [2:0] _alu_exe_unit_1_io_iresp_bits_uop_ctrl_op2_sel;\t// @[execution-units.scala:119:32]\n wire [2:0] _alu_exe_unit_1_io_iresp_bits_uop_ctrl_imm_sel;\t// @[execution-units.scala:119:32]\n wire [4:0] _alu_exe_unit_1_io_iresp_bits_uop_ctrl_op_fcn;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_iresp_bits_uop_ctrl_fcn_dw;\t// @[execution-units.scala:119:32]\n wire [2:0] _alu_exe_unit_1_io_iresp_bits_uop_ctrl_csr_cmd;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_iresp_bits_uop_ctrl_is_load;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_iresp_bits_uop_ctrl_is_sta;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_iresp_bits_uop_ctrl_is_std;\t// @[execution-units.scala:119:32]\n wire [1:0] _alu_exe_unit_1_io_iresp_bits_uop_iw_state;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_iresp_bits_uop_iw_p1_poisoned;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_iresp_bits_uop_iw_p2_poisoned;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_iresp_bits_uop_is_br;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_iresp_bits_uop_is_jalr;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_iresp_bits_uop_is_jal;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_iresp_bits_uop_is_sfb;\t// @[execution-units.scala:119:32]\n wire [15:0] _alu_exe_unit_1_io_iresp_bits_uop_br_mask;\t// @[execution-units.scala:119:32]\n wire [3:0] _alu_exe_unit_1_io_iresp_bits_uop_br_tag;\t// @[execution-units.scala:119:32]\n wire [4:0] _alu_exe_unit_1_io_iresp_bits_uop_ftq_idx;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_iresp_bits_uop_edge_inst;\t// @[execution-units.scala:119:32]\n wire [5:0] _alu_exe_unit_1_io_iresp_bits_uop_pc_lob;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_iresp_bits_uop_taken;\t// @[execution-units.scala:119:32]\n wire [19:0] _alu_exe_unit_1_io_iresp_bits_uop_imm_packed;\t// @[execution-units.scala:119:32]\n wire [11:0] _alu_exe_unit_1_io_iresp_bits_uop_csr_addr;\t// @[execution-units.scala:119:32]\n wire [6:0] _alu_exe_unit_1_io_iresp_bits_uop_rob_idx;\t// @[execution-units.scala:119:32]\n wire [4:0] _alu_exe_unit_1_io_iresp_bits_uop_ldq_idx;\t// @[execution-units.scala:119:32]\n wire [4:0] _alu_exe_unit_1_io_iresp_bits_uop_stq_idx;\t// @[execution-units.scala:119:32]\n wire [1:0] _alu_exe_unit_1_io_iresp_bits_uop_rxq_idx;\t// @[execution-units.scala:119:32]\n wire [6:0] _alu_exe_unit_1_io_iresp_bits_uop_pdst;\t// @[execution-units.scala:119:32]\n wire [6:0] _alu_exe_unit_1_io_iresp_bits_uop_prs1;\t// @[execution-units.scala:119:32]\n wire [6:0] _alu_exe_unit_1_io_iresp_bits_uop_prs2;\t// @[execution-units.scala:119:32]\n wire [6:0] _alu_exe_unit_1_io_iresp_bits_uop_prs3;\t// @[execution-units.scala:119:32]\n wire [4:0] _alu_exe_unit_1_io_iresp_bits_uop_ppred;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_iresp_bits_uop_prs1_busy;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_iresp_bits_uop_prs2_busy;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_iresp_bits_uop_prs3_busy;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_iresp_bits_uop_ppred_busy;\t// @[execution-units.scala:119:32]\n wire [6:0] _alu_exe_unit_1_io_iresp_bits_uop_stale_pdst;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_iresp_bits_uop_exception;\t// @[execution-units.scala:119:32]\n wire [63:0] _alu_exe_unit_1_io_iresp_bits_uop_exc_cause;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_iresp_bits_uop_bypassable;\t// @[execution-units.scala:119:32]\n wire [4:0] _alu_exe_unit_1_io_iresp_bits_uop_mem_cmd;\t// @[execution-units.scala:119:32]\n wire [1:0] _alu_exe_unit_1_io_iresp_bits_uop_mem_size;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_iresp_bits_uop_mem_signed;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_iresp_bits_uop_is_fence;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_iresp_bits_uop_is_fencei;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_iresp_bits_uop_is_amo;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_iresp_bits_uop_uses_ldq;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_iresp_bits_uop_uses_stq;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_iresp_bits_uop_is_sys_pc2epc;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_iresp_bits_uop_is_unique;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_iresp_bits_uop_flush_on_commit;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_iresp_bits_uop_ldst_is_rs1;\t// @[execution-units.scala:119:32]\n wire [5:0] _alu_exe_unit_1_io_iresp_bits_uop_ldst;\t// @[execution-units.scala:119:32]\n wire [5:0] _alu_exe_unit_1_io_iresp_bits_uop_lrs1;\t// @[execution-units.scala:119:32]\n wire [5:0] _alu_exe_unit_1_io_iresp_bits_uop_lrs2;\t// @[execution-units.scala:119:32]\n wire [5:0] _alu_exe_unit_1_io_iresp_bits_uop_lrs3;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_iresp_bits_uop_ldst_val;\t// @[execution-units.scala:119:32]\n wire [1:0] _alu_exe_unit_1_io_iresp_bits_uop_dst_rtype;\t// @[execution-units.scala:119:32]\n wire [1:0] _alu_exe_unit_1_io_iresp_bits_uop_lrs1_rtype;\t// @[execution-units.scala:119:32]\n wire [1:0] _alu_exe_unit_1_io_iresp_bits_uop_lrs2_rtype;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_iresp_bits_uop_frs3_en;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_iresp_bits_uop_fp_val;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_iresp_bits_uop_fp_single;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_iresp_bits_uop_xcpt_pf_if;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_iresp_bits_uop_xcpt_ae_if;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_iresp_bits_uop_xcpt_ma_if;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_iresp_bits_uop_bp_debug_if;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_iresp_bits_uop_bp_xcpt_if;\t// @[execution-units.scala:119:32]\n wire [1:0] _alu_exe_unit_1_io_iresp_bits_uop_debug_fsrc;\t// @[execution-units.scala:119:32]\n wire [1:0] _alu_exe_unit_1_io_iresp_bits_uop_debug_tsrc;\t// @[execution-units.scala:119:32]\n wire [64:0] _alu_exe_unit_1_io_iresp_bits_data;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_ll_fresp_valid;\t// @[execution-units.scala:119:32]\n wire [6:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_uopc;\t// @[execution-units.scala:119:32]\n wire [31:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_inst;\t// @[execution-units.scala:119:32]\n wire [31:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_debug_inst;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_ll_fresp_bits_uop_is_rvc;\t// @[execution-units.scala:119:32]\n wire [39:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_debug_pc;\t// @[execution-units.scala:119:32]\n wire [2:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_iq_type;\t// @[execution-units.scala:119:32]\n wire [9:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_fu_code;\t// @[execution-units.scala:119:32]\n wire [3:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_ctrl_br_type;\t// @[execution-units.scala:119:32]\n wire [1:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_ctrl_op1_sel;\t// @[execution-units.scala:119:32]\n wire [2:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_ctrl_op2_sel;\t// @[execution-units.scala:119:32]\n wire [2:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_ctrl_imm_sel;\t// @[execution-units.scala:119:32]\n wire [4:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_ctrl_op_fcn;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_ll_fresp_bits_uop_ctrl_fcn_dw;\t// @[execution-units.scala:119:32]\n wire [2:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_ctrl_csr_cmd;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_ll_fresp_bits_uop_ctrl_is_load;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_ll_fresp_bits_uop_ctrl_is_sta;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_ll_fresp_bits_uop_ctrl_is_std;\t// @[execution-units.scala:119:32]\n wire [1:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_iw_state;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_ll_fresp_bits_uop_iw_p1_poisoned;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_ll_fresp_bits_uop_iw_p2_poisoned;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_ll_fresp_bits_uop_is_br;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_ll_fresp_bits_uop_is_jalr;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_ll_fresp_bits_uop_is_jal;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_ll_fresp_bits_uop_is_sfb;\t// @[execution-units.scala:119:32]\n wire [15:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_br_mask;\t// @[execution-units.scala:119:32]\n wire [3:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_br_tag;\t// @[execution-units.scala:119:32]\n wire [4:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_ftq_idx;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_ll_fresp_bits_uop_edge_inst;\t// @[execution-units.scala:119:32]\n wire [5:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_pc_lob;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_ll_fresp_bits_uop_taken;\t// @[execution-units.scala:119:32]\n wire [19:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_imm_packed;\t// @[execution-units.scala:119:32]\n wire [11:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_csr_addr;\t// @[execution-units.scala:119:32]\n wire [6:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_rob_idx;\t// @[execution-units.scala:119:32]\n wire [4:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_ldq_idx;\t// @[execution-units.scala:119:32]\n wire [4:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_stq_idx;\t// @[execution-units.scala:119:32]\n wire [1:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_rxq_idx;\t// @[execution-units.scala:119:32]\n wire [6:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_pdst;\t// @[execution-units.scala:119:32]\n wire [6:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_prs1;\t// @[execution-units.scala:119:32]\n wire [6:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_prs2;\t// @[execution-units.scala:119:32]\n wire [6:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_prs3;\t// @[execution-units.scala:119:32]\n wire [4:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_ppred;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_ll_fresp_bits_uop_prs1_busy;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_ll_fresp_bits_uop_prs2_busy;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_ll_fresp_bits_uop_prs3_busy;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_ll_fresp_bits_uop_ppred_busy;\t// @[execution-units.scala:119:32]\n wire [6:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_stale_pdst;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_ll_fresp_bits_uop_exception;\t// @[execution-units.scala:119:32]\n wire [63:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_exc_cause;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_ll_fresp_bits_uop_bypassable;\t// @[execution-units.scala:119:32]\n wire [4:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_mem_cmd;\t// @[execution-units.scala:119:32]\n wire [1:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_mem_size;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_ll_fresp_bits_uop_mem_signed;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_ll_fresp_bits_uop_is_fence;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_ll_fresp_bits_uop_is_fencei;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_ll_fresp_bits_uop_is_amo;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_ll_fresp_bits_uop_uses_ldq;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_ll_fresp_bits_uop_uses_stq;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_ll_fresp_bits_uop_is_sys_pc2epc;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_ll_fresp_bits_uop_is_unique;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_ll_fresp_bits_uop_flush_on_commit;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_ll_fresp_bits_uop_ldst_is_rs1;\t// @[execution-units.scala:119:32]\n wire [5:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_ldst;\t// @[execution-units.scala:119:32]\n wire [5:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_lrs1;\t// @[execution-units.scala:119:32]\n wire [5:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_lrs2;\t// @[execution-units.scala:119:32]\n wire [5:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_lrs3;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_ll_fresp_bits_uop_ldst_val;\t// @[execution-units.scala:119:32]\n wire [1:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_dst_rtype;\t// @[execution-units.scala:119:32]\n wire [1:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_lrs1_rtype;\t// @[execution-units.scala:119:32]\n wire [1:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_lrs2_rtype;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_ll_fresp_bits_uop_frs3_en;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_ll_fresp_bits_uop_fp_val;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_ll_fresp_bits_uop_fp_single;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_ll_fresp_bits_uop_xcpt_pf_if;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_ll_fresp_bits_uop_xcpt_ae_if;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_ll_fresp_bits_uop_xcpt_ma_if;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_ll_fresp_bits_uop_bp_debug_if;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_ll_fresp_bits_uop_bp_xcpt_if;\t// @[execution-units.scala:119:32]\n wire [1:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_debug_fsrc;\t// @[execution-units.scala:119:32]\n wire [1:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_debug_tsrc;\t// @[execution-units.scala:119:32]\n wire [64:0] _alu_exe_unit_1_io_ll_fresp_bits_data;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_ll_fresp_bits_predicated;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_valid;\t// @[execution-units.scala:119:32]\n wire [6:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_uopc;\t// @[execution-units.scala:119:32]\n wire [31:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_inst;\t// @[execution-units.scala:119:32]\n wire [31:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_debug_inst;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_is_rvc;\t// @[execution-units.scala:119:32]\n wire [39:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_debug_pc;\t// @[execution-units.scala:119:32]\n wire [2:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_iq_type;\t// @[execution-units.scala:119:32]\n wire [9:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_fu_code;\t// @[execution-units.scala:119:32]\n wire [3:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_ctrl_br_type;\t// @[execution-units.scala:119:32]\n wire [1:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_ctrl_op1_sel;\t// @[execution-units.scala:119:32]\n wire [2:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_ctrl_op2_sel;\t// @[execution-units.scala:119:32]\n wire [2:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_ctrl_imm_sel;\t// @[execution-units.scala:119:32]\n wire [4:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_ctrl_op_fcn;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_ctrl_fcn_dw;\t// @[execution-units.scala:119:32]\n wire [2:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_ctrl_csr_cmd;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_ctrl_is_load;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_ctrl_is_sta;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_ctrl_is_std;\t// @[execution-units.scala:119:32]\n wire [1:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_iw_state;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_iw_p1_poisoned;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_iw_p2_poisoned;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_is_br;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_is_jalr;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_is_jal;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_is_sfb;\t// @[execution-units.scala:119:32]\n wire [15:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_br_mask;\t// @[execution-units.scala:119:32]\n wire [3:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_br_tag;\t// @[execution-units.scala:119:32]\n wire [4:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_ftq_idx;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_edge_inst;\t// @[execution-units.scala:119:32]\n wire [5:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_pc_lob;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_taken;\t// @[execution-units.scala:119:32]\n wire [19:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_imm_packed;\t// @[execution-units.scala:119:32]\n wire [11:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_csr_addr;\t// @[execution-units.scala:119:32]\n wire [6:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_rob_idx;\t// @[execution-units.scala:119:32]\n wire [4:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_ldq_idx;\t// @[execution-units.scala:119:32]\n wire [4:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_stq_idx;\t// @[execution-units.scala:119:32]\n wire [1:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_rxq_idx;\t// @[execution-units.scala:119:32]\n wire [6:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_pdst;\t// @[execution-units.scala:119:32]\n wire [6:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_prs1;\t// @[execution-units.scala:119:32]\n wire [6:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_prs2;\t// @[execution-units.scala:119:32]\n wire [6:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_prs3;\t// @[execution-units.scala:119:32]\n wire [4:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_ppred;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_prs1_busy;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_prs2_busy;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_prs3_busy;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_ppred_busy;\t// @[execution-units.scala:119:32]\n wire [6:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_stale_pdst;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_exception;\t// @[execution-units.scala:119:32]\n wire [63:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_exc_cause;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_bypassable;\t// @[execution-units.scala:119:32]\n wire [4:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_mem_cmd;\t// @[execution-units.scala:119:32]\n wire [1:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_mem_size;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_mem_signed;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_is_fence;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_is_fencei;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_is_amo;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_uses_ldq;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_uses_stq;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_is_sys_pc2epc;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_is_unique;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_flush_on_commit;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_ldst_is_rs1;\t// @[execution-units.scala:119:32]\n wire [5:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_ldst;\t// @[execution-units.scala:119:32]\n wire [5:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_lrs1;\t// @[execution-units.scala:119:32]\n wire [5:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_lrs2;\t// @[execution-units.scala:119:32]\n wire [5:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_lrs3;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_ldst_val;\t// @[execution-units.scala:119:32]\n wire [1:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_dst_rtype;\t// @[execution-units.scala:119:32]\n wire [1:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_lrs1_rtype;\t// @[execution-units.scala:119:32]\n wire [1:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_lrs2_rtype;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_frs3_en;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_fp_val;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_fp_single;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_xcpt_pf_if;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_xcpt_ae_if;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_xcpt_ma_if;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_bp_debug_if;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_bp_xcpt_if;\t// @[execution-units.scala:119:32]\n wire [1:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_debug_fsrc;\t// @[execution-units.scala:119:32]\n wire [1:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_debug_tsrc;\t// @[execution-units.scala:119:32]\n wire [4:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_flags;\t// @[execution-units.scala:119:32]\n wire [64:0] _alu_exe_unit_1_io_bypass_0_bits_data;\t// @[execution-units.scala:119:32]\n wire [6:0] _alu_exe_unit_1_io_brinfo_uop_uopc;\t// @[execution-units.scala:119:32]\n wire [31:0] _alu_exe_unit_1_io_brinfo_uop_inst;\t// @[execution-units.scala:119:32]\n wire [31:0] _alu_exe_unit_1_io_brinfo_uop_debug_inst;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_brinfo_uop_is_rvc;\t// @[execution-units.scala:119:32]\n wire [39:0] _alu_exe_unit_1_io_brinfo_uop_debug_pc;\t// @[execution-units.scala:119:32]\n wire [2:0] _alu_exe_unit_1_io_brinfo_uop_iq_type;\t// @[execution-units.scala:119:32]\n wire [9:0] _alu_exe_unit_1_io_brinfo_uop_fu_code;\t// @[execution-units.scala:119:32]\n wire [3:0] _alu_exe_unit_1_io_brinfo_uop_ctrl_br_type;\t// @[execution-units.scala:119:32]\n wire [1:0] _alu_exe_unit_1_io_brinfo_uop_ctrl_op1_sel;\t// @[execution-units.scala:119:32]\n wire [2:0] _alu_exe_unit_1_io_brinfo_uop_ctrl_op2_sel;\t// @[execution-units.scala:119:32]\n wire [2:0] _alu_exe_unit_1_io_brinfo_uop_ctrl_imm_sel;\t// @[execution-units.scala:119:32]\n wire [4:0] _alu_exe_unit_1_io_brinfo_uop_ctrl_op_fcn;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_brinfo_uop_ctrl_fcn_dw;\t// @[execution-units.scala:119:32]\n wire [2:0] _alu_exe_unit_1_io_brinfo_uop_ctrl_csr_cmd;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_brinfo_uop_ctrl_is_load;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_brinfo_uop_ctrl_is_sta;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_brinfo_uop_ctrl_is_std;\t// @[execution-units.scala:119:32]\n wire [1:0] _alu_exe_unit_1_io_brinfo_uop_iw_state;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_brinfo_uop_iw_p1_poisoned;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_brinfo_uop_iw_p2_poisoned;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_brinfo_uop_is_br;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_brinfo_uop_is_jalr;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_brinfo_uop_is_jal;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_brinfo_uop_is_sfb;\t// @[execution-units.scala:119:32]\n wire [15:0] _alu_exe_unit_1_io_brinfo_uop_br_mask;\t// @[execution-units.scala:119:32]\n wire [3:0] _alu_exe_unit_1_io_brinfo_uop_br_tag;\t// @[execution-units.scala:119:32]\n wire [4:0] _alu_exe_unit_1_io_brinfo_uop_ftq_idx;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_brinfo_uop_edge_inst;\t// @[execution-units.scala:119:32]\n wire [5:0] _alu_exe_unit_1_io_brinfo_uop_pc_lob;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_brinfo_uop_taken;\t// @[execution-units.scala:119:32]\n wire [19:0] _alu_exe_unit_1_io_brinfo_uop_imm_packed;\t// @[execution-units.scala:119:32]\n wire [11:0] _alu_exe_unit_1_io_brinfo_uop_csr_addr;\t// @[execution-units.scala:119:32]\n wire [6:0] _alu_exe_unit_1_io_brinfo_uop_rob_idx;\t// @[execution-units.scala:119:32]\n wire [4:0] _alu_exe_unit_1_io_brinfo_uop_ldq_idx;\t// @[execution-units.scala:119:32]\n wire [4:0] _alu_exe_unit_1_io_brinfo_uop_stq_idx;\t// @[execution-units.scala:119:32]\n wire [1:0] _alu_exe_unit_1_io_brinfo_uop_rxq_idx;\t// @[execution-units.scala:119:32]\n wire [6:0] _alu_exe_unit_1_io_brinfo_uop_pdst;\t// @[execution-units.scala:119:32]\n wire [6:0] _alu_exe_unit_1_io_brinfo_uop_prs1;\t// @[execution-units.scala:119:32]\n wire [6:0] _alu_exe_unit_1_io_brinfo_uop_prs2;\t// @[execution-units.scala:119:32]\n wire [6:0] _alu_exe_unit_1_io_brinfo_uop_prs3;\t// @[execution-units.scala:119:32]\n wire [4:0] _alu_exe_unit_1_io_brinfo_uop_ppred;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_brinfo_uop_prs1_busy;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_brinfo_uop_prs2_busy;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_brinfo_uop_prs3_busy;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_brinfo_uop_ppred_busy;\t// @[execution-units.scala:119:32]\n wire [6:0] _alu_exe_unit_1_io_brinfo_uop_stale_pdst;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_brinfo_uop_exception;\t// @[execution-units.scala:119:32]\n wire [63:0] _alu_exe_unit_1_io_brinfo_uop_exc_cause;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_brinfo_uop_bypassable;\t// @[execution-units.scala:119:32]\n wire [4:0] _alu_exe_unit_1_io_brinfo_uop_mem_cmd;\t// @[execution-units.scala:119:32]\n wire [1:0] _alu_exe_unit_1_io_brinfo_uop_mem_size;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_brinfo_uop_mem_signed;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_brinfo_uop_is_fence;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_brinfo_uop_is_fencei;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_brinfo_uop_is_amo;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_brinfo_uop_uses_ldq;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_brinfo_uop_uses_stq;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_brinfo_uop_is_sys_pc2epc;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_brinfo_uop_is_unique;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_brinfo_uop_flush_on_commit;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_brinfo_uop_ldst_is_rs1;\t// @[execution-units.scala:119:32]\n wire [5:0] _alu_exe_unit_1_io_brinfo_uop_ldst;\t// @[execution-units.scala:119:32]\n wire [5:0] _alu_exe_unit_1_io_brinfo_uop_lrs1;\t// @[execution-units.scala:119:32]\n wire [5:0] _alu_exe_unit_1_io_brinfo_uop_lrs2;\t// @[execution-units.scala:119:32]\n wire [5:0] _alu_exe_unit_1_io_brinfo_uop_lrs3;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_brinfo_uop_ldst_val;\t// @[execution-units.scala:119:32]\n wire [1:0] _alu_exe_unit_1_io_brinfo_uop_dst_rtype;\t// @[execution-units.scala:119:32]\n wire [1:0] _alu_exe_unit_1_io_brinfo_uop_lrs1_rtype;\t// @[execution-units.scala:119:32]\n wire [1:0] _alu_exe_unit_1_io_brinfo_uop_lrs2_rtype;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_brinfo_uop_frs3_en;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_brinfo_uop_fp_val;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_brinfo_uop_fp_single;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_brinfo_uop_xcpt_pf_if;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_brinfo_uop_xcpt_ae_if;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_brinfo_uop_xcpt_ma_if;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_brinfo_uop_bp_debug_if;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_brinfo_uop_bp_xcpt_if;\t// @[execution-units.scala:119:32]\n wire [1:0] _alu_exe_unit_1_io_brinfo_uop_debug_fsrc;\t// @[execution-units.scala:119:32]\n wire [1:0] _alu_exe_unit_1_io_brinfo_uop_debug_tsrc;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_brinfo_valid;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_brinfo_mispredict;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_1_io_brinfo_taken;\t// @[execution-units.scala:119:32]\n wire [2:0] _alu_exe_unit_1_io_brinfo_cfi_type;\t// @[execution-units.scala:119:32]\n wire [1:0] _alu_exe_unit_1_io_brinfo_pc_sel;\t// @[execution-units.scala:119:32]\n wire [20:0] _alu_exe_unit_1_io_brinfo_target_offset;\t// @[execution-units.scala:119:32]\n wire [9:0] _alu_exe_unit_io_fu_types;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_iresp_valid;\t// @[execution-units.scala:119:32]\n wire [6:0] _alu_exe_unit_io_iresp_bits_uop_uopc;\t// @[execution-units.scala:119:32]\n wire [31:0] _alu_exe_unit_io_iresp_bits_uop_inst;\t// @[execution-units.scala:119:32]\n wire [31:0] _alu_exe_unit_io_iresp_bits_uop_debug_inst;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_iresp_bits_uop_is_rvc;\t// @[execution-units.scala:119:32]\n wire [39:0] _alu_exe_unit_io_iresp_bits_uop_debug_pc;\t// @[execution-units.scala:119:32]\n wire [2:0] _alu_exe_unit_io_iresp_bits_uop_iq_type;\t// @[execution-units.scala:119:32]\n wire [9:0] _alu_exe_unit_io_iresp_bits_uop_fu_code;\t// @[execution-units.scala:119:32]\n wire [3:0] _alu_exe_unit_io_iresp_bits_uop_ctrl_br_type;\t// @[execution-units.scala:119:32]\n wire [1:0] _alu_exe_unit_io_iresp_bits_uop_ctrl_op1_sel;\t// @[execution-units.scala:119:32]\n wire [2:0] _alu_exe_unit_io_iresp_bits_uop_ctrl_op2_sel;\t// @[execution-units.scala:119:32]\n wire [2:0] _alu_exe_unit_io_iresp_bits_uop_ctrl_imm_sel;\t// @[execution-units.scala:119:32]\n wire [4:0] _alu_exe_unit_io_iresp_bits_uop_ctrl_op_fcn;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_iresp_bits_uop_ctrl_fcn_dw;\t// @[execution-units.scala:119:32]\n wire [2:0] _alu_exe_unit_io_iresp_bits_uop_ctrl_csr_cmd;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_iresp_bits_uop_ctrl_is_load;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_iresp_bits_uop_ctrl_is_sta;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_iresp_bits_uop_ctrl_is_std;\t// @[execution-units.scala:119:32]\n wire [1:0] _alu_exe_unit_io_iresp_bits_uop_iw_state;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_iresp_bits_uop_iw_p1_poisoned;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_iresp_bits_uop_iw_p2_poisoned;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_iresp_bits_uop_is_br;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_iresp_bits_uop_is_jalr;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_iresp_bits_uop_is_jal;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_iresp_bits_uop_is_sfb;\t// @[execution-units.scala:119:32]\n wire [15:0] _alu_exe_unit_io_iresp_bits_uop_br_mask;\t// @[execution-units.scala:119:32]\n wire [3:0] _alu_exe_unit_io_iresp_bits_uop_br_tag;\t// @[execution-units.scala:119:32]\n wire [4:0] _alu_exe_unit_io_iresp_bits_uop_ftq_idx;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_iresp_bits_uop_edge_inst;\t// @[execution-units.scala:119:32]\n wire [5:0] _alu_exe_unit_io_iresp_bits_uop_pc_lob;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_iresp_bits_uop_taken;\t// @[execution-units.scala:119:32]\n wire [19:0] _alu_exe_unit_io_iresp_bits_uop_imm_packed;\t// @[execution-units.scala:119:32]\n wire [11:0] _alu_exe_unit_io_iresp_bits_uop_csr_addr;\t// @[execution-units.scala:119:32]\n wire [6:0] _alu_exe_unit_io_iresp_bits_uop_rob_idx;\t// @[execution-units.scala:119:32]\n wire [4:0] _alu_exe_unit_io_iresp_bits_uop_ldq_idx;\t// @[execution-units.scala:119:32]\n wire [4:0] _alu_exe_unit_io_iresp_bits_uop_stq_idx;\t// @[execution-units.scala:119:32]\n wire [1:0] _alu_exe_unit_io_iresp_bits_uop_rxq_idx;\t// @[execution-units.scala:119:32]\n wire [6:0] _alu_exe_unit_io_iresp_bits_uop_pdst;\t// @[execution-units.scala:119:32]\n wire [6:0] _alu_exe_unit_io_iresp_bits_uop_prs1;\t// @[execution-units.scala:119:32]\n wire [6:0] _alu_exe_unit_io_iresp_bits_uop_prs2;\t// @[execution-units.scala:119:32]\n wire [6:0] _alu_exe_unit_io_iresp_bits_uop_prs3;\t// @[execution-units.scala:119:32]\n wire [4:0] _alu_exe_unit_io_iresp_bits_uop_ppred;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_iresp_bits_uop_prs1_busy;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_iresp_bits_uop_prs2_busy;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_iresp_bits_uop_prs3_busy;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_iresp_bits_uop_ppred_busy;\t// @[execution-units.scala:119:32]\n wire [6:0] _alu_exe_unit_io_iresp_bits_uop_stale_pdst;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_iresp_bits_uop_exception;\t// @[execution-units.scala:119:32]\n wire [63:0] _alu_exe_unit_io_iresp_bits_uop_exc_cause;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_iresp_bits_uop_bypassable;\t// @[execution-units.scala:119:32]\n wire [4:0] _alu_exe_unit_io_iresp_bits_uop_mem_cmd;\t// @[execution-units.scala:119:32]\n wire [1:0] _alu_exe_unit_io_iresp_bits_uop_mem_size;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_iresp_bits_uop_mem_signed;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_iresp_bits_uop_is_fence;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_iresp_bits_uop_is_fencei;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_iresp_bits_uop_is_amo;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_iresp_bits_uop_uses_ldq;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_iresp_bits_uop_uses_stq;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_iresp_bits_uop_is_sys_pc2epc;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_iresp_bits_uop_is_unique;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_iresp_bits_uop_flush_on_commit;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_iresp_bits_uop_ldst_is_rs1;\t// @[execution-units.scala:119:32]\n wire [5:0] _alu_exe_unit_io_iresp_bits_uop_ldst;\t// @[execution-units.scala:119:32]\n wire [5:0] _alu_exe_unit_io_iresp_bits_uop_lrs1;\t// @[execution-units.scala:119:32]\n wire [5:0] _alu_exe_unit_io_iresp_bits_uop_lrs2;\t// @[execution-units.scala:119:32]\n wire [5:0] _alu_exe_unit_io_iresp_bits_uop_lrs3;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_iresp_bits_uop_ldst_val;\t// @[execution-units.scala:119:32]\n wire [1:0] _alu_exe_unit_io_iresp_bits_uop_dst_rtype;\t// @[execution-units.scala:119:32]\n wire [1:0] _alu_exe_unit_io_iresp_bits_uop_lrs1_rtype;\t// @[execution-units.scala:119:32]\n wire [1:0] _alu_exe_unit_io_iresp_bits_uop_lrs2_rtype;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_iresp_bits_uop_frs3_en;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_iresp_bits_uop_fp_val;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_iresp_bits_uop_fp_single;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_iresp_bits_uop_xcpt_pf_if;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_iresp_bits_uop_xcpt_ae_if;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_iresp_bits_uop_xcpt_ma_if;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_iresp_bits_uop_bp_debug_if;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_iresp_bits_uop_bp_xcpt_if;\t// @[execution-units.scala:119:32]\n wire [1:0] _alu_exe_unit_io_iresp_bits_uop_debug_fsrc;\t// @[execution-units.scala:119:32]\n wire [1:0] _alu_exe_unit_io_iresp_bits_uop_debug_tsrc;\t// @[execution-units.scala:119:32]\n wire [64:0] _alu_exe_unit_io_iresp_bits_data;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_bypass_0_valid;\t// @[execution-units.scala:119:32]\n wire [6:0] _alu_exe_unit_io_bypass_0_bits_uop_uopc;\t// @[execution-units.scala:119:32]\n wire [31:0] _alu_exe_unit_io_bypass_0_bits_uop_inst;\t// @[execution-units.scala:119:32]\n wire [31:0] _alu_exe_unit_io_bypass_0_bits_uop_debug_inst;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_bypass_0_bits_uop_is_rvc;\t// @[execution-units.scala:119:32]\n wire [39:0] _alu_exe_unit_io_bypass_0_bits_uop_debug_pc;\t// @[execution-units.scala:119:32]\n wire [2:0] _alu_exe_unit_io_bypass_0_bits_uop_iq_type;\t// @[execution-units.scala:119:32]\n wire [9:0] _alu_exe_unit_io_bypass_0_bits_uop_fu_code;\t// @[execution-units.scala:119:32]\n wire [3:0] _alu_exe_unit_io_bypass_0_bits_uop_ctrl_br_type;\t// @[execution-units.scala:119:32]\n wire [1:0] _alu_exe_unit_io_bypass_0_bits_uop_ctrl_op1_sel;\t// @[execution-units.scala:119:32]\n wire [2:0] _alu_exe_unit_io_bypass_0_bits_uop_ctrl_op2_sel;\t// @[execution-units.scala:119:32]\n wire [2:0] _alu_exe_unit_io_bypass_0_bits_uop_ctrl_imm_sel;\t// @[execution-units.scala:119:32]\n wire [4:0] _alu_exe_unit_io_bypass_0_bits_uop_ctrl_op_fcn;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_bypass_0_bits_uop_ctrl_fcn_dw;\t// @[execution-units.scala:119:32]\n wire [2:0] _alu_exe_unit_io_bypass_0_bits_uop_ctrl_csr_cmd;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_bypass_0_bits_uop_ctrl_is_load;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_bypass_0_bits_uop_ctrl_is_sta;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_bypass_0_bits_uop_ctrl_is_std;\t// @[execution-units.scala:119:32]\n wire [1:0] _alu_exe_unit_io_bypass_0_bits_uop_iw_state;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_bypass_0_bits_uop_iw_p1_poisoned;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_bypass_0_bits_uop_iw_p2_poisoned;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_bypass_0_bits_uop_is_br;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_bypass_0_bits_uop_is_jalr;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_bypass_0_bits_uop_is_jal;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_bypass_0_bits_uop_is_sfb;\t// @[execution-units.scala:119:32]\n wire [15:0] _alu_exe_unit_io_bypass_0_bits_uop_br_mask;\t// @[execution-units.scala:119:32]\n wire [3:0] _alu_exe_unit_io_bypass_0_bits_uop_br_tag;\t// @[execution-units.scala:119:32]\n wire [4:0] _alu_exe_unit_io_bypass_0_bits_uop_ftq_idx;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_bypass_0_bits_uop_edge_inst;\t// @[execution-units.scala:119:32]\n wire [5:0] _alu_exe_unit_io_bypass_0_bits_uop_pc_lob;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_bypass_0_bits_uop_taken;\t// @[execution-units.scala:119:32]\n wire [19:0] _alu_exe_unit_io_bypass_0_bits_uop_imm_packed;\t// @[execution-units.scala:119:32]\n wire [11:0] _alu_exe_unit_io_bypass_0_bits_uop_csr_addr;\t// @[execution-units.scala:119:32]\n wire [6:0] _alu_exe_unit_io_bypass_0_bits_uop_rob_idx;\t// @[execution-units.scala:119:32]\n wire [4:0] _alu_exe_unit_io_bypass_0_bits_uop_ldq_idx;\t// @[execution-units.scala:119:32]\n wire [4:0] _alu_exe_unit_io_bypass_0_bits_uop_stq_idx;\t// @[execution-units.scala:119:32]\n wire [1:0] _alu_exe_unit_io_bypass_0_bits_uop_rxq_idx;\t// @[execution-units.scala:119:32]\n wire [6:0] _alu_exe_unit_io_bypass_0_bits_uop_pdst;\t// @[execution-units.scala:119:32]\n wire [6:0] _alu_exe_unit_io_bypass_0_bits_uop_prs1;\t// @[execution-units.scala:119:32]\n wire [6:0] _alu_exe_unit_io_bypass_0_bits_uop_prs2;\t// @[execution-units.scala:119:32]\n wire [6:0] _alu_exe_unit_io_bypass_0_bits_uop_prs3;\t// @[execution-units.scala:119:32]\n wire [4:0] _alu_exe_unit_io_bypass_0_bits_uop_ppred;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_bypass_0_bits_uop_prs1_busy;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_bypass_0_bits_uop_prs2_busy;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_bypass_0_bits_uop_prs3_busy;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_bypass_0_bits_uop_ppred_busy;\t// @[execution-units.scala:119:32]\n wire [6:0] _alu_exe_unit_io_bypass_0_bits_uop_stale_pdst;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_bypass_0_bits_uop_exception;\t// @[execution-units.scala:119:32]\n wire [63:0] _alu_exe_unit_io_bypass_0_bits_uop_exc_cause;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_bypass_0_bits_uop_bypassable;\t// @[execution-units.scala:119:32]\n wire [4:0] _alu_exe_unit_io_bypass_0_bits_uop_mem_cmd;\t// @[execution-units.scala:119:32]\n wire [1:0] _alu_exe_unit_io_bypass_0_bits_uop_mem_size;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_bypass_0_bits_uop_mem_signed;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_bypass_0_bits_uop_is_fence;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_bypass_0_bits_uop_is_fencei;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_bypass_0_bits_uop_is_amo;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_bypass_0_bits_uop_uses_ldq;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_bypass_0_bits_uop_uses_stq;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_bypass_0_bits_uop_is_sys_pc2epc;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_bypass_0_bits_uop_is_unique;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_bypass_0_bits_uop_flush_on_commit;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_bypass_0_bits_uop_ldst_is_rs1;\t// @[execution-units.scala:119:32]\n wire [5:0] _alu_exe_unit_io_bypass_0_bits_uop_ldst;\t// @[execution-units.scala:119:32]\n wire [5:0] _alu_exe_unit_io_bypass_0_bits_uop_lrs1;\t// @[execution-units.scala:119:32]\n wire [5:0] _alu_exe_unit_io_bypass_0_bits_uop_lrs2;\t// @[execution-units.scala:119:32]\n wire [5:0] _alu_exe_unit_io_bypass_0_bits_uop_lrs3;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_bypass_0_bits_uop_ldst_val;\t// @[execution-units.scala:119:32]\n wire [1:0] _alu_exe_unit_io_bypass_0_bits_uop_dst_rtype;\t// @[execution-units.scala:119:32]\n wire [1:0] _alu_exe_unit_io_bypass_0_bits_uop_lrs1_rtype;\t// @[execution-units.scala:119:32]\n wire [1:0] _alu_exe_unit_io_bypass_0_bits_uop_lrs2_rtype;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_bypass_0_bits_uop_frs3_en;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_bypass_0_bits_uop_fp_val;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_bypass_0_bits_uop_fp_single;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_bypass_0_bits_uop_xcpt_pf_if;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_bypass_0_bits_uop_xcpt_ae_if;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_bypass_0_bits_uop_xcpt_ma_if;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_bypass_0_bits_uop_bp_debug_if;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_bypass_0_bits_uop_bp_xcpt_if;\t// @[execution-units.scala:119:32]\n wire [1:0] _alu_exe_unit_io_bypass_0_bits_uop_debug_fsrc;\t// @[execution-units.scala:119:32]\n wire [1:0] _alu_exe_unit_io_bypass_0_bits_uop_debug_tsrc;\t// @[execution-units.scala:119:32]\n wire [64:0] _alu_exe_unit_io_bypass_0_bits_data;\t// @[execution-units.scala:119:32]\n wire [6:0] _alu_exe_unit_io_brinfo_uop_uopc;\t// @[execution-units.scala:119:32]\n wire [31:0] _alu_exe_unit_io_brinfo_uop_inst;\t// @[execution-units.scala:119:32]\n wire [31:0] _alu_exe_unit_io_brinfo_uop_debug_inst;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_brinfo_uop_is_rvc;\t// @[execution-units.scala:119:32]\n wire [39:0] _alu_exe_unit_io_brinfo_uop_debug_pc;\t// @[execution-units.scala:119:32]\n wire [2:0] _alu_exe_unit_io_brinfo_uop_iq_type;\t// @[execution-units.scala:119:32]\n wire [9:0] _alu_exe_unit_io_brinfo_uop_fu_code;\t// @[execution-units.scala:119:32]\n wire [3:0] _alu_exe_unit_io_brinfo_uop_ctrl_br_type;\t// @[execution-units.scala:119:32]\n wire [1:0] _alu_exe_unit_io_brinfo_uop_ctrl_op1_sel;\t// @[execution-units.scala:119:32]\n wire [2:0] _alu_exe_unit_io_brinfo_uop_ctrl_op2_sel;\t// @[execution-units.scala:119:32]\n wire [2:0] _alu_exe_unit_io_brinfo_uop_ctrl_imm_sel;\t// @[execution-units.scala:119:32]\n wire [4:0] _alu_exe_unit_io_brinfo_uop_ctrl_op_fcn;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_brinfo_uop_ctrl_fcn_dw;\t// @[execution-units.scala:119:32]\n wire [2:0] _alu_exe_unit_io_brinfo_uop_ctrl_csr_cmd;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_brinfo_uop_ctrl_is_load;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_brinfo_uop_ctrl_is_sta;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_brinfo_uop_ctrl_is_std;\t// @[execution-units.scala:119:32]\n wire [1:0] _alu_exe_unit_io_brinfo_uop_iw_state;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_brinfo_uop_iw_p1_poisoned;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_brinfo_uop_iw_p2_poisoned;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_brinfo_uop_is_br;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_brinfo_uop_is_jalr;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_brinfo_uop_is_jal;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_brinfo_uop_is_sfb;\t// @[execution-units.scala:119:32]\n wire [15:0] _alu_exe_unit_io_brinfo_uop_br_mask;\t// @[execution-units.scala:119:32]\n wire [3:0] _alu_exe_unit_io_brinfo_uop_br_tag;\t// @[execution-units.scala:119:32]\n wire [4:0] _alu_exe_unit_io_brinfo_uop_ftq_idx;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_brinfo_uop_edge_inst;\t// @[execution-units.scala:119:32]\n wire [5:0] _alu_exe_unit_io_brinfo_uop_pc_lob;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_brinfo_uop_taken;\t// @[execution-units.scala:119:32]\n wire [19:0] _alu_exe_unit_io_brinfo_uop_imm_packed;\t// @[execution-units.scala:119:32]\n wire [11:0] _alu_exe_unit_io_brinfo_uop_csr_addr;\t// @[execution-units.scala:119:32]\n wire [6:0] _alu_exe_unit_io_brinfo_uop_rob_idx;\t// @[execution-units.scala:119:32]\n wire [4:0] _alu_exe_unit_io_brinfo_uop_ldq_idx;\t// @[execution-units.scala:119:32]\n wire [4:0] _alu_exe_unit_io_brinfo_uop_stq_idx;\t// @[execution-units.scala:119:32]\n wire [1:0] _alu_exe_unit_io_brinfo_uop_rxq_idx;\t// @[execution-units.scala:119:32]\n wire [6:0] _alu_exe_unit_io_brinfo_uop_pdst;\t// @[execution-units.scala:119:32]\n wire [6:0] _alu_exe_unit_io_brinfo_uop_prs1;\t// @[execution-units.scala:119:32]\n wire [6:0] _alu_exe_unit_io_brinfo_uop_prs2;\t// @[execution-units.scala:119:32]\n wire [6:0] _alu_exe_unit_io_brinfo_uop_prs3;\t// @[execution-units.scala:119:32]\n wire [4:0] _alu_exe_unit_io_brinfo_uop_ppred;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_brinfo_uop_prs1_busy;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_brinfo_uop_prs2_busy;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_brinfo_uop_prs3_busy;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_brinfo_uop_ppred_busy;\t// @[execution-units.scala:119:32]\n wire [6:0] _alu_exe_unit_io_brinfo_uop_stale_pdst;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_brinfo_uop_exception;\t// @[execution-units.scala:119:32]\n wire [63:0] _alu_exe_unit_io_brinfo_uop_exc_cause;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_brinfo_uop_bypassable;\t// @[execution-units.scala:119:32]\n wire [4:0] _alu_exe_unit_io_brinfo_uop_mem_cmd;\t// @[execution-units.scala:119:32]\n wire [1:0] _alu_exe_unit_io_brinfo_uop_mem_size;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_brinfo_uop_mem_signed;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_brinfo_uop_is_fence;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_brinfo_uop_is_fencei;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_brinfo_uop_is_amo;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_brinfo_uop_uses_ldq;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_brinfo_uop_uses_stq;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_brinfo_uop_is_sys_pc2epc;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_brinfo_uop_is_unique;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_brinfo_uop_flush_on_commit;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_brinfo_uop_ldst_is_rs1;\t// @[execution-units.scala:119:32]\n wire [5:0] _alu_exe_unit_io_brinfo_uop_ldst;\t// @[execution-units.scala:119:32]\n wire [5:0] _alu_exe_unit_io_brinfo_uop_lrs1;\t// @[execution-units.scala:119:32]\n wire [5:0] _alu_exe_unit_io_brinfo_uop_lrs2;\t// @[execution-units.scala:119:32]\n wire [5:0] _alu_exe_unit_io_brinfo_uop_lrs3;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_brinfo_uop_ldst_val;\t// @[execution-units.scala:119:32]\n wire [1:0] _alu_exe_unit_io_brinfo_uop_dst_rtype;\t// @[execution-units.scala:119:32]\n wire [1:0] _alu_exe_unit_io_brinfo_uop_lrs1_rtype;\t// @[execution-units.scala:119:32]\n wire [1:0] _alu_exe_unit_io_brinfo_uop_lrs2_rtype;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_brinfo_uop_frs3_en;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_brinfo_uop_fp_val;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_brinfo_uop_fp_single;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_brinfo_uop_xcpt_pf_if;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_brinfo_uop_xcpt_ae_if;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_brinfo_uop_xcpt_ma_if;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_brinfo_uop_bp_debug_if;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_brinfo_uop_bp_xcpt_if;\t// @[execution-units.scala:119:32]\n wire [1:0] _alu_exe_unit_io_brinfo_uop_debug_fsrc;\t// @[execution-units.scala:119:32]\n wire [1:0] _alu_exe_unit_io_brinfo_uop_debug_tsrc;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_brinfo_valid;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_brinfo_mispredict;\t// @[execution-units.scala:119:32]\n wire _alu_exe_unit_io_brinfo_taken;\t// @[execution-units.scala:119:32]\n wire [2:0] _alu_exe_unit_io_brinfo_cfi_type;\t// @[execution-units.scala:119:32]\n wire [1:0] _alu_exe_unit_io_brinfo_pc_sel;\t// @[execution-units.scala:119:32]\n wire [39:0] _alu_exe_unit_io_brinfo_jalr_target;\t// @[execution-units.scala:119:32]\n wire [20:0] _alu_exe_unit_io_brinfo_target_offset;\t// @[execution-units.scala:119:32]\n wire _memExeUnit_io_ll_iresp_valid;\t// @[execution-units.scala:108:30]\n wire [6:0] _memExeUnit_io_ll_iresp_bits_uop_uopc;\t// @[execution-units.scala:108:30]\n wire [31:0] _memExeUnit_io_ll_iresp_bits_uop_inst;\t// @[execution-units.scala:108:30]\n wire [31:0] _memExeUnit_io_ll_iresp_bits_uop_debug_inst;\t// @[execution-units.scala:108:30]\n wire _memExeUnit_io_ll_iresp_bits_uop_is_rvc;\t// @[execution-units.scala:108:30]\n wire [39:0] _memExeUnit_io_ll_iresp_bits_uop_debug_pc;\t// @[execution-units.scala:108:30]\n wire [2:0] _memExeUnit_io_ll_iresp_bits_uop_iq_type;\t// @[execution-units.scala:108:30]\n wire [9:0] _memExeUnit_io_ll_iresp_bits_uop_fu_code;\t// @[execution-units.scala:108:30]\n wire [3:0] _memExeUnit_io_ll_iresp_bits_uop_ctrl_br_type;\t// @[execution-units.scala:108:30]\n wire [1:0] _memExeUnit_io_ll_iresp_bits_uop_ctrl_op1_sel;\t// @[execution-units.scala:108:30]\n wire [2:0] _memExeUnit_io_ll_iresp_bits_uop_ctrl_op2_sel;\t// @[execution-units.scala:108:30]\n wire [2:0] _memExeUnit_io_ll_iresp_bits_uop_ctrl_imm_sel;\t// @[execution-units.scala:108:30]\n wire [4:0] _memExeUnit_io_ll_iresp_bits_uop_ctrl_op_fcn;\t// @[execution-units.scala:108:30]\n wire _memExeUnit_io_ll_iresp_bits_uop_ctrl_fcn_dw;\t// @[execution-units.scala:108:30]\n wire [2:0] _memExeUnit_io_ll_iresp_bits_uop_ctrl_csr_cmd;\t// @[execution-units.scala:108:30]\n wire _memExeUnit_io_ll_iresp_bits_uop_ctrl_is_load;\t// @[execution-units.scala:108:30]\n wire _memExeUnit_io_ll_iresp_bits_uop_ctrl_is_sta;\t// @[execution-units.scala:108:30]\n wire _memExeUnit_io_ll_iresp_bits_uop_ctrl_is_std;\t// @[execution-units.scala:108:30]\n wire [1:0] _memExeUnit_io_ll_iresp_bits_uop_iw_state;\t// @[execution-units.scala:108:30]\n wire _memExeUnit_io_ll_iresp_bits_uop_iw_p1_poisoned;\t// @[execution-units.scala:108:30]\n wire _memExeUnit_io_ll_iresp_bits_uop_iw_p2_poisoned;\t// @[execution-units.scala:108:30]\n wire _memExeUnit_io_ll_iresp_bits_uop_is_br;\t// @[execution-units.scala:108:30]\n wire _memExeUnit_io_ll_iresp_bits_uop_is_jalr;\t// @[execution-units.scala:108:30]\n wire _memExeUnit_io_ll_iresp_bits_uop_is_jal;\t// @[execution-units.scala:108:30]\n wire _memExeUnit_io_ll_iresp_bits_uop_is_sfb;\t// @[execution-units.scala:108:30]\n wire [15:0] _memExeUnit_io_ll_iresp_bits_uop_br_mask;\t// @[execution-units.scala:108:30]\n wire [3:0] _memExeUnit_io_ll_iresp_bits_uop_br_tag;\t// @[execution-units.scala:108:30]\n wire [4:0] _memExeUnit_io_ll_iresp_bits_uop_ftq_idx;\t// @[execution-units.scala:108:30]\n wire _memExeUnit_io_ll_iresp_bits_uop_edge_inst;\t// @[execution-units.scala:108:30]\n wire [5:0] _memExeUnit_io_ll_iresp_bits_uop_pc_lob;\t// @[execution-units.scala:108:30]\n wire _memExeUnit_io_ll_iresp_bits_uop_taken;\t// @[execution-units.scala:108:30]\n wire [19:0] _memExeUnit_io_ll_iresp_bits_uop_imm_packed;\t// @[execution-units.scala:108:30]\n wire [11:0] _memExeUnit_io_ll_iresp_bits_uop_csr_addr;\t// @[execution-units.scala:108:30]\n wire [6:0] _memExeUnit_io_ll_iresp_bits_uop_rob_idx;\t// @[execution-units.scala:108:30]\n wire [4:0] _memExeUnit_io_ll_iresp_bits_uop_ldq_idx;\t// @[execution-units.scala:108:30]\n wire [4:0] _memExeUnit_io_ll_iresp_bits_uop_stq_idx;\t// @[execution-units.scala:108:30]\n wire [1:0] _memExeUnit_io_ll_iresp_bits_uop_rxq_idx;\t// @[execution-units.scala:108:30]\n wire [6:0] _memExeUnit_io_ll_iresp_bits_uop_pdst;\t// @[execution-units.scala:108:30]\n wire [6:0] _memExeUnit_io_ll_iresp_bits_uop_prs1;\t// @[execution-units.scala:108:30]\n wire [6:0] _memExeUnit_io_ll_iresp_bits_uop_prs2;\t// @[execution-units.scala:108:30]\n wire [6:0] _memExeUnit_io_ll_iresp_bits_uop_prs3;\t// @[execution-units.scala:108:30]\n wire [4:0] _memExeUnit_io_ll_iresp_bits_uop_ppred;\t// @[execution-units.scala:108:30]\n wire _memExeUnit_io_ll_iresp_bits_uop_prs1_busy;\t// @[execution-units.scala:108:30]\n wire _memExeUnit_io_ll_iresp_bits_uop_prs2_busy;\t// @[execution-units.scala:108:30]\n wire _memExeUnit_io_ll_iresp_bits_uop_prs3_busy;\t// @[execution-units.scala:108:30]\n wire _memExeUnit_io_ll_iresp_bits_uop_ppred_busy;\t// @[execution-units.scala:108:30]\n wire [6:0] _memExeUnit_io_ll_iresp_bits_uop_stale_pdst;\t// @[execution-units.scala:108:30]\n wire _memExeUnit_io_ll_iresp_bits_uop_exception;\t// @[execution-units.scala:108:30]\n wire [63:0] _memExeUnit_io_ll_iresp_bits_uop_exc_cause;\t// @[execution-units.scala:108:30]\n wire _memExeUnit_io_ll_iresp_bits_uop_bypassable;\t// @[execution-units.scala:108:30]\n wire [4:0] _memExeUnit_io_ll_iresp_bits_uop_mem_cmd;\t// @[execution-units.scala:108:30]\n wire [1:0] _memExeUnit_io_ll_iresp_bits_uop_mem_size;\t// @[execution-units.scala:108:30]\n wire _memExeUnit_io_ll_iresp_bits_uop_mem_signed;\t// @[execution-units.scala:108:30]\n wire _memExeUnit_io_ll_iresp_bits_uop_is_fence;\t// @[execution-units.scala:108:30]\n wire _memExeUnit_io_ll_iresp_bits_uop_is_fencei;\t// @[execution-units.scala:108:30]\n wire _memExeUnit_io_ll_iresp_bits_uop_is_amo;\t// @[execution-units.scala:108:30]\n wire _memExeUnit_io_ll_iresp_bits_uop_uses_ldq;\t// @[execution-units.scala:108:30]\n wire _memExeUnit_io_ll_iresp_bits_uop_uses_stq;\t// @[execution-units.scala:108:30]\n wire _memExeUnit_io_ll_iresp_bits_uop_is_sys_pc2epc;\t// @[execution-units.scala:108:30]\n wire _memExeUnit_io_ll_iresp_bits_uop_is_unique;\t// @[execution-units.scala:108:30]\n wire _memExeUnit_io_ll_iresp_bits_uop_flush_on_commit;\t// @[execution-units.scala:108:30]\n wire _memExeUnit_io_ll_iresp_bits_uop_ldst_is_rs1;\t// @[execution-units.scala:108:30]\n wire [5:0] _memExeUnit_io_ll_iresp_bits_uop_ldst;\t// @[execution-units.scala:108:30]\n wire [5:0] _memExeUnit_io_ll_iresp_bits_uop_lrs1;\t// @[execution-units.scala:108:30]\n wire [5:0] _memExeUnit_io_ll_iresp_bits_uop_lrs2;\t// @[execution-units.scala:108:30]\n wire [5:0] _memExeUnit_io_ll_iresp_bits_uop_lrs3;\t// @[execution-units.scala:108:30]\n wire _memExeUnit_io_ll_iresp_bits_uop_ldst_val;\t// @[execution-units.scala:108:30]\n wire [1:0] _memExeUnit_io_ll_iresp_bits_uop_dst_rtype;\t// @[execution-units.scala:108:30]\n wire [1:0] _memExeUnit_io_ll_iresp_bits_uop_lrs1_rtype;\t// @[execution-units.scala:108:30]\n wire [1:0] _memExeUnit_io_ll_iresp_bits_uop_lrs2_rtype;\t// @[execution-units.scala:108:30]\n wire _memExeUnit_io_ll_iresp_bits_uop_frs3_en;\t// @[execution-units.scala:108:30]\n wire _memExeUnit_io_ll_iresp_bits_uop_fp_val;\t// @[execution-units.scala:108:30]\n wire _memExeUnit_io_ll_iresp_bits_uop_fp_single;\t// @[execution-units.scala:108:30]\n wire _memExeUnit_io_ll_iresp_bits_uop_xcpt_pf_if;\t// @[execution-units.scala:108:30]\n wire _memExeUnit_io_ll_iresp_bits_uop_xcpt_ae_if;\t// @[execution-units.scala:108:30]\n wire _memExeUnit_io_ll_iresp_bits_uop_xcpt_ma_if;\t// @[execution-units.scala:108:30]\n wire _memExeUnit_io_ll_iresp_bits_uop_bp_debug_if;\t// @[execution-units.scala:108:30]\n wire _memExeUnit_io_ll_iresp_bits_uop_bp_xcpt_if;\t// @[execution-units.scala:108:30]\n wire [1:0] _memExeUnit_io_ll_iresp_bits_uop_debug_fsrc;\t// @[execution-units.scala:108:30]\n wire [1:0] _memExeUnit_io_ll_iresp_bits_uop_debug_tsrc;\t// @[execution-units.scala:108:30]\n wire [64:0] _memExeUnit_io_ll_iresp_bits_data;\t// @[execution-units.scala:108:30]\n wire _memExeUnit_io_ll_fresp_valid;\t// @[execution-units.scala:108:30]\n wire [6:0] _memExeUnit_io_ll_fresp_bits_uop_uopc;\t// @[execution-units.scala:108:30]\n wire [31:0] _memExeUnit_io_ll_fresp_bits_uop_inst;\t// @[execution-units.scala:108:30]\n wire [31:0] _memExeUnit_io_ll_fresp_bits_uop_debug_inst;\t// @[execution-units.scala:108:30]\n wire _memExeUnit_io_ll_fresp_bits_uop_is_rvc;\t// @[execution-units.scala:108:30]\n wire [39:0] _memExeUnit_io_ll_fresp_bits_uop_debug_pc;\t// @[execution-units.scala:108:30]\n wire [2:0] _memExeUnit_io_ll_fresp_bits_uop_iq_type;\t// @[execution-units.scala:108:30]\n wire [9:0] _memExeUnit_io_ll_fresp_bits_uop_fu_code;\t// @[execution-units.scala:108:30]\n wire [3:0] _memExeUnit_io_ll_fresp_bits_uop_ctrl_br_type;\t// @[execution-units.scala:108:30]\n wire [1:0] _memExeUnit_io_ll_fresp_bits_uop_ctrl_op1_sel;\t// @[execution-units.scala:108:30]\n wire [2:0] _memExeUnit_io_ll_fresp_bits_uop_ctrl_op2_sel;\t// @[execution-units.scala:108:30]\n wire [2:0] _memExeUnit_io_ll_fresp_bits_uop_ctrl_imm_sel;\t// @[execution-units.scala:108:30]\n wire [4:0] _memExeUnit_io_ll_fresp_bits_uop_ctrl_op_fcn;\t// @[execution-units.scala:108:30]\n wire _memExeUnit_io_ll_fresp_bits_uop_ctrl_fcn_dw;\t// @[execution-units.scala:108:30]\n wire [2:0] _memExeUnit_io_ll_fresp_bits_uop_ctrl_csr_cmd;\t// @[execution-units.scala:108:30]\n wire _memExeUnit_io_ll_fresp_bits_uop_ctrl_is_load;\t// @[execution-units.scala:108:30]\n wire _memExeUnit_io_ll_fresp_bits_uop_ctrl_is_sta;\t// @[execution-units.scala:108:30]\n wire _memExeUnit_io_ll_fresp_bits_uop_ctrl_is_std;\t// @[execution-units.scala:108:30]\n wire [1:0] _memExeUnit_io_ll_fresp_bits_uop_iw_state;\t// @[execution-units.scala:108:30]\n wire _memExeUnit_io_ll_fresp_bits_uop_iw_p1_poisoned;\t// @[execution-units.scala:108:30]\n wire _memExeUnit_io_ll_fresp_bits_uop_iw_p2_poisoned;\t// @[execution-units.scala:108:30]\n wire _memExeUnit_io_ll_fresp_bits_uop_is_br;\t// @[execution-units.scala:108:30]\n wire _memExeUnit_io_ll_fresp_bits_uop_is_jalr;\t// @[execution-units.scala:108:30]\n wire _memExeUnit_io_ll_fresp_bits_uop_is_jal;\t// @[execution-units.scala:108:30]\n wire _memExeUnit_io_ll_fresp_bits_uop_is_sfb;\t// @[execution-units.scala:108:30]\n wire [15:0] _memExeUnit_io_ll_fresp_bits_uop_br_mask;\t// @[execution-units.scala:108:30]\n wire [3:0] _memExeUnit_io_ll_fresp_bits_uop_br_tag;\t// @[execution-units.scala:108:30]\n wire [4:0] _memExeUnit_io_ll_fresp_bits_uop_ftq_idx;\t// @[execution-units.scala:108:30]\n wire _memExeUnit_io_ll_fresp_bits_uop_edge_inst;\t// @[execution-units.scala:108:30]\n wire [5:0] _memExeUnit_io_ll_fresp_bits_uop_pc_lob;\t// @[execution-units.scala:108:30]\n wire _memExeUnit_io_ll_fresp_bits_uop_taken;\t// @[execution-units.scala:108:30]\n wire [19:0] _memExeUnit_io_ll_fresp_bits_uop_imm_packed;\t// @[execution-units.scala:108:30]\n wire [11:0] _memExeUnit_io_ll_fresp_bits_uop_csr_addr;\t// @[execution-units.scala:108:30]\n wire [6:0] _memExeUnit_io_ll_fresp_bits_uop_rob_idx;\t// @[execution-units.scala:108:30]\n wire [4:0] _memExeUnit_io_ll_fresp_bits_uop_ldq_idx;\t// @[execution-units.scala:108:30]\n wire [4:0] _memExeUnit_io_ll_fresp_bits_uop_stq_idx;\t// @[execution-units.scala:108:30]\n wire [1:0] _memExeUnit_io_ll_fresp_bits_uop_rxq_idx;\t// @[execution-units.scala:108:30]\n wire [6:0] _memExeUnit_io_ll_fresp_bits_uop_pdst;\t// @[execution-units.scala:108:30]\n wire [6:0] _memExeUnit_io_ll_fresp_bits_uop_prs1;\t// @[execution-units.scala:108:30]\n wire [6:0] _memExeUnit_io_ll_fresp_bits_uop_prs2;\t// @[execution-units.scala:108:30]\n wire [6:0] _memExeUnit_io_ll_fresp_bits_uop_prs3;\t// @[execution-units.scala:108:30]\n wire [4:0] _memExeUnit_io_ll_fresp_bits_uop_ppred;\t// @[execution-units.scala:108:30]\n wire _memExeUnit_io_ll_fresp_bits_uop_prs1_busy;\t// @[execution-units.scala:108:30]\n wire _memExeUnit_io_ll_fresp_bits_uop_prs2_busy;\t// @[execution-units.scala:108:30]\n wire _memExeUnit_io_ll_fresp_bits_uop_prs3_busy;\t// @[execution-units.scala:108:30]\n wire _memExeUnit_io_ll_fresp_bits_uop_ppred_busy;\t// @[execution-units.scala:108:30]\n wire [6:0] _memExeUnit_io_ll_fresp_bits_uop_stale_pdst;\t// @[execution-units.scala:108:30]\n wire _memExeUnit_io_ll_fresp_bits_uop_exception;\t// @[execution-units.scala:108:30]\n wire [63:0] _memExeUnit_io_ll_fresp_bits_uop_exc_cause;\t// @[execution-units.scala:108:30]\n wire _memExeUnit_io_ll_fresp_bits_uop_bypassable;\t// @[execution-units.scala:108:30]\n wire [4:0] _memExeUnit_io_ll_fresp_bits_uop_mem_cmd;\t// @[execution-units.scala:108:30]\n wire [1:0] _memExeUnit_io_ll_fresp_bits_uop_mem_size;\t// @[execution-units.scala:108:30]\n wire _memExeUnit_io_ll_fresp_bits_uop_mem_signed;\t// @[execution-units.scala:108:30]\n wire _memExeUnit_io_ll_fresp_bits_uop_is_fence;\t// @[execution-units.scala:108:30]\n wire _memExeUnit_io_ll_fresp_bits_uop_is_fencei;\t// @[execution-units.scala:108:30]\n wire _memExeUnit_io_ll_fresp_bits_uop_is_amo;\t// @[execution-units.scala:108:30]\n wire _memExeUnit_io_ll_fresp_bits_uop_uses_ldq;\t// @[execution-units.scala:108:30]\n wire _memExeUnit_io_ll_fresp_bits_uop_uses_stq;\t// @[execution-units.scala:108:30]\n wire _memExeUnit_io_ll_fresp_bits_uop_is_sys_pc2epc;\t// @[execution-units.scala:108:30]\n wire _memExeUnit_io_ll_fresp_bits_uop_is_unique;\t// @[execution-units.scala:108:30]\n wire _memExeUnit_io_ll_fresp_bits_uop_flush_on_commit;\t// @[execution-units.scala:108:30]\n wire _memExeUnit_io_ll_fresp_bits_uop_ldst_is_rs1;\t// @[execution-units.scala:108:30]\n wire [5:0] _memExeUnit_io_ll_fresp_bits_uop_ldst;\t// @[execution-units.scala:108:30]\n wire [5:0] _memExeUnit_io_ll_fresp_bits_uop_lrs1;\t// @[execution-units.scala:108:30]\n wire [5:0] _memExeUnit_io_ll_fresp_bits_uop_lrs2;\t// @[execution-units.scala:108:30]\n wire [5:0] _memExeUnit_io_ll_fresp_bits_uop_lrs3;\t// @[execution-units.scala:108:30]\n wire _memExeUnit_io_ll_fresp_bits_uop_ldst_val;\t// @[execution-units.scala:108:30]\n wire [1:0] _memExeUnit_io_ll_fresp_bits_uop_dst_rtype;\t// @[execution-units.scala:108:30]\n wire [1:0] _memExeUnit_io_ll_fresp_bits_uop_lrs1_rtype;\t// @[execution-units.scala:108:30]\n wire [1:0] _memExeUnit_io_ll_fresp_bits_uop_lrs2_rtype;\t// @[execution-units.scala:108:30]\n wire _memExeUnit_io_ll_fresp_bits_uop_frs3_en;\t// @[execution-units.scala:108:30]\n wire _memExeUnit_io_ll_fresp_bits_uop_fp_val;\t// @[execution-units.scala:108:30]\n wire _memExeUnit_io_ll_fresp_bits_uop_fp_single;\t// @[execution-units.scala:108:30]\n wire _memExeUnit_io_ll_fresp_bits_uop_xcpt_pf_if;\t// @[execution-units.scala:108:30]\n wire _memExeUnit_io_ll_fresp_bits_uop_xcpt_ae_if;\t// @[execution-units.scala:108:30]\n wire _memExeUnit_io_ll_fresp_bits_uop_xcpt_ma_if;\t// @[execution-units.scala:108:30]\n wire _memExeUnit_io_ll_fresp_bits_uop_bp_debug_if;\t// @[execution-units.scala:108:30]\n wire _memExeUnit_io_ll_fresp_bits_uop_bp_xcpt_if;\t// @[execution-units.scala:108:30]\n wire [1:0] _memExeUnit_io_ll_fresp_bits_uop_debug_fsrc;\t// @[execution-units.scala:108:30]\n wire [1:0] _memExeUnit_io_ll_fresp_bits_uop_debug_tsrc;\t// @[execution-units.scala:108:30]\n wire [64:0] _memExeUnit_io_ll_fresp_bits_data;\t// @[execution-units.scala:108:30]\n wire io_hartid_0 = io_hartid;\t// @[core.scala:51:7]\n wire io_interrupts_debug_0 = io_interrupts_debug;\t// @[core.scala:51:7]\n wire io_interrupts_mtip_0 = io_interrupts_mtip;\t// @[core.scala:51:7]\n wire io_interrupts_msip_0 = io_interrupts_msip;\t// @[core.scala:51:7]\n wire io_interrupts_meip_0 = io_interrupts_meip;\t// @[core.scala:51:7]\n wire io_interrupts_seip_0 = io_interrupts_seip;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_valid_0 = io_ifu_fetchpacket_valid;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_0_valid_0 = io_ifu_fetchpacket_bits_uops_0_valid;\t// @[core.scala:51:7]\n wire [31:0] io_ifu_fetchpacket_bits_uops_0_bits_inst_0 = io_ifu_fetchpacket_bits_uops_0_bits_inst;\t// @[core.scala:51:7]\n wire [31:0] io_ifu_fetchpacket_bits_uops_0_bits_debug_inst_0 = io_ifu_fetchpacket_bits_uops_0_bits_debug_inst;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_0_bits_is_rvc_0 = io_ifu_fetchpacket_bits_uops_0_bits_is_rvc;\t// @[core.scala:51:7]\n wire [39:0] io_ifu_fetchpacket_bits_uops_0_bits_debug_pc_0 = io_ifu_fetchpacket_bits_uops_0_bits_debug_pc;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_0_bits_is_sfb_0 = io_ifu_fetchpacket_bits_uops_0_bits_is_sfb;\t// @[core.scala:51:7]\n wire [4:0] io_ifu_fetchpacket_bits_uops_0_bits_ftq_idx_0 = io_ifu_fetchpacket_bits_uops_0_bits_ftq_idx;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_0_bits_edge_inst_0 = io_ifu_fetchpacket_bits_uops_0_bits_edge_inst;\t// @[core.scala:51:7]\n wire [5:0] io_ifu_fetchpacket_bits_uops_0_bits_pc_lob_0 = io_ifu_fetchpacket_bits_uops_0_bits_pc_lob;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_0_bits_taken_0 = io_ifu_fetchpacket_bits_uops_0_bits_taken;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_0_bits_xcpt_pf_if_0 = io_ifu_fetchpacket_bits_uops_0_bits_xcpt_pf_if;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_0_bits_xcpt_ae_if_0 = io_ifu_fetchpacket_bits_uops_0_bits_xcpt_ae_if;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_0_bits_bp_debug_if_0 = io_ifu_fetchpacket_bits_uops_0_bits_bp_debug_if;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_0_bits_bp_xcpt_if_0 = io_ifu_fetchpacket_bits_uops_0_bits_bp_xcpt_if;\t// @[core.scala:51:7]\n wire [1:0] io_ifu_fetchpacket_bits_uops_0_bits_debug_fsrc_0 = io_ifu_fetchpacket_bits_uops_0_bits_debug_fsrc;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_1_valid_0 = io_ifu_fetchpacket_bits_uops_1_valid;\t// @[core.scala:51:7]\n wire [31:0] io_ifu_fetchpacket_bits_uops_1_bits_inst_0 = io_ifu_fetchpacket_bits_uops_1_bits_inst;\t// @[core.scala:51:7]\n wire [31:0] io_ifu_fetchpacket_bits_uops_1_bits_debug_inst_0 = io_ifu_fetchpacket_bits_uops_1_bits_debug_inst;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_1_bits_is_rvc_0 = io_ifu_fetchpacket_bits_uops_1_bits_is_rvc;\t// @[core.scala:51:7]\n wire [39:0] io_ifu_fetchpacket_bits_uops_1_bits_debug_pc_0 = io_ifu_fetchpacket_bits_uops_1_bits_debug_pc;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_1_bits_is_sfb_0 = io_ifu_fetchpacket_bits_uops_1_bits_is_sfb;\t// @[core.scala:51:7]\n wire [4:0] io_ifu_fetchpacket_bits_uops_1_bits_ftq_idx_0 = io_ifu_fetchpacket_bits_uops_1_bits_ftq_idx;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_1_bits_edge_inst_0 = io_ifu_fetchpacket_bits_uops_1_bits_edge_inst;\t// @[core.scala:51:7]\n wire [5:0] io_ifu_fetchpacket_bits_uops_1_bits_pc_lob_0 = io_ifu_fetchpacket_bits_uops_1_bits_pc_lob;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_1_bits_taken_0 = io_ifu_fetchpacket_bits_uops_1_bits_taken;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_1_bits_xcpt_pf_if_0 = io_ifu_fetchpacket_bits_uops_1_bits_xcpt_pf_if;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_1_bits_xcpt_ae_if_0 = io_ifu_fetchpacket_bits_uops_1_bits_xcpt_ae_if;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_1_bits_bp_debug_if_0 = io_ifu_fetchpacket_bits_uops_1_bits_bp_debug_if;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_1_bits_bp_xcpt_if_0 = io_ifu_fetchpacket_bits_uops_1_bits_bp_xcpt_if;\t// @[core.scala:51:7]\n wire [1:0] io_ifu_fetchpacket_bits_uops_1_bits_debug_fsrc_0 = io_ifu_fetchpacket_bits_uops_1_bits_debug_fsrc;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_2_valid_0 = io_ifu_fetchpacket_bits_uops_2_valid;\t// @[core.scala:51:7]\n wire [31:0] io_ifu_fetchpacket_bits_uops_2_bits_inst_0 = io_ifu_fetchpacket_bits_uops_2_bits_inst;\t// @[core.scala:51:7]\n wire [31:0] io_ifu_fetchpacket_bits_uops_2_bits_debug_inst_0 = io_ifu_fetchpacket_bits_uops_2_bits_debug_inst;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_2_bits_is_rvc_0 = io_ifu_fetchpacket_bits_uops_2_bits_is_rvc;\t// @[core.scala:51:7]\n wire [39:0] io_ifu_fetchpacket_bits_uops_2_bits_debug_pc_0 = io_ifu_fetchpacket_bits_uops_2_bits_debug_pc;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_2_bits_is_sfb_0 = io_ifu_fetchpacket_bits_uops_2_bits_is_sfb;\t// @[core.scala:51:7]\n wire [4:0] io_ifu_fetchpacket_bits_uops_2_bits_ftq_idx_0 = io_ifu_fetchpacket_bits_uops_2_bits_ftq_idx;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_2_bits_edge_inst_0 = io_ifu_fetchpacket_bits_uops_2_bits_edge_inst;\t// @[core.scala:51:7]\n wire [5:0] io_ifu_fetchpacket_bits_uops_2_bits_pc_lob_0 = io_ifu_fetchpacket_bits_uops_2_bits_pc_lob;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_2_bits_taken_0 = io_ifu_fetchpacket_bits_uops_2_bits_taken;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_2_bits_xcpt_pf_if_0 = io_ifu_fetchpacket_bits_uops_2_bits_xcpt_pf_if;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_2_bits_xcpt_ae_if_0 = io_ifu_fetchpacket_bits_uops_2_bits_xcpt_ae_if;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_2_bits_bp_debug_if_0 = io_ifu_fetchpacket_bits_uops_2_bits_bp_debug_if;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_2_bits_bp_xcpt_if_0 = io_ifu_fetchpacket_bits_uops_2_bits_bp_xcpt_if;\t// @[core.scala:51:7]\n wire [1:0] io_ifu_fetchpacket_bits_uops_2_bits_debug_fsrc_0 = io_ifu_fetchpacket_bits_uops_2_bits_debug_fsrc;\t// @[core.scala:51:7]\n wire io_ifu_get_pc_0_entry_cfi_idx_valid_0 = io_ifu_get_pc_0_entry_cfi_idx_valid;\t// @[core.scala:51:7]\n wire [2:0] io_ifu_get_pc_0_entry_cfi_idx_bits_0 = io_ifu_get_pc_0_entry_cfi_idx_bits;\t// @[core.scala:51:7]\n wire io_ifu_get_pc_0_entry_cfi_taken_0 = io_ifu_get_pc_0_entry_cfi_taken;\t// @[core.scala:51:7]\n wire io_ifu_get_pc_0_entry_cfi_mispredicted_0 = io_ifu_get_pc_0_entry_cfi_mispredicted;\t// @[core.scala:51:7]\n wire [2:0] io_ifu_get_pc_0_entry_cfi_type_0 = io_ifu_get_pc_0_entry_cfi_type;\t// @[core.scala:51:7]\n wire [7:0] io_ifu_get_pc_0_entry_br_mask_0 = io_ifu_get_pc_0_entry_br_mask;\t// @[core.scala:51:7]\n wire io_ifu_get_pc_0_entry_cfi_is_call_0 = io_ifu_get_pc_0_entry_cfi_is_call;\t// @[core.scala:51:7]\n wire io_ifu_get_pc_0_entry_cfi_is_ret_0 = io_ifu_get_pc_0_entry_cfi_is_ret;\t// @[core.scala:51:7]\n wire io_ifu_get_pc_0_entry_cfi_npc_plus4_0 = io_ifu_get_pc_0_entry_cfi_npc_plus4;\t// @[core.scala:51:7]\n wire [39:0] io_ifu_get_pc_0_entry_ras_top_0 = io_ifu_get_pc_0_entry_ras_top;\t// @[core.scala:51:7]\n wire [4:0] io_ifu_get_pc_0_entry_ras_idx_0 = io_ifu_get_pc_0_entry_ras_idx;\t// @[core.scala:51:7]\n wire io_ifu_get_pc_0_entry_start_bank_0 = io_ifu_get_pc_0_entry_start_bank;\t// @[core.scala:51:7]\n wire [39:0] io_ifu_get_pc_0_pc_0 = io_ifu_get_pc_0_pc;\t// @[core.scala:51:7]\n wire [39:0] io_ifu_get_pc_0_com_pc_0 = io_ifu_get_pc_0_com_pc;\t// @[core.scala:51:7]\n wire io_ifu_get_pc_0_next_val_0 = io_ifu_get_pc_0_next_val;\t// @[core.scala:51:7]\n wire [39:0] io_ifu_get_pc_0_next_pc_0 = io_ifu_get_pc_0_next_pc;\t// @[core.scala:51:7]\n wire io_ifu_get_pc_1_entry_cfi_idx_valid_0 = io_ifu_get_pc_1_entry_cfi_idx_valid;\t// @[core.scala:51:7]\n wire [2:0] io_ifu_get_pc_1_entry_cfi_idx_bits_0 = io_ifu_get_pc_1_entry_cfi_idx_bits;\t// @[core.scala:51:7]\n wire io_ifu_get_pc_1_entry_cfi_taken_0 = io_ifu_get_pc_1_entry_cfi_taken;\t// @[core.scala:51:7]\n wire io_ifu_get_pc_1_entry_cfi_mispredicted_0 = io_ifu_get_pc_1_entry_cfi_mispredicted;\t// @[core.scala:51:7]\n wire [2:0] io_ifu_get_pc_1_entry_cfi_type_0 = io_ifu_get_pc_1_entry_cfi_type;\t// @[core.scala:51:7]\n wire [7:0] io_ifu_get_pc_1_entry_br_mask_0 = io_ifu_get_pc_1_entry_br_mask;\t// @[core.scala:51:7]\n wire io_ifu_get_pc_1_entry_cfi_is_call_0 = io_ifu_get_pc_1_entry_cfi_is_call;\t// @[core.scala:51:7]\n wire io_ifu_get_pc_1_entry_cfi_is_ret_0 = io_ifu_get_pc_1_entry_cfi_is_ret;\t// @[core.scala:51:7]\n wire io_ifu_get_pc_1_entry_cfi_npc_plus4_0 = io_ifu_get_pc_1_entry_cfi_npc_plus4;\t// @[core.scala:51:7]\n wire [39:0] io_ifu_get_pc_1_entry_ras_top_0 = io_ifu_get_pc_1_entry_ras_top;\t// @[core.scala:51:7]\n wire [4:0] io_ifu_get_pc_1_entry_ras_idx_0 = io_ifu_get_pc_1_entry_ras_idx;\t// @[core.scala:51:7]\n wire io_ifu_get_pc_1_entry_start_bank_0 = io_ifu_get_pc_1_entry_start_bank;\t// @[core.scala:51:7]\n wire [63:0] io_ifu_get_pc_1_ghist_old_history_0 = io_ifu_get_pc_1_ghist_old_history;\t// @[core.scala:51:7]\n wire io_ifu_get_pc_1_ghist_current_saw_branch_not_taken_0 = io_ifu_get_pc_1_ghist_current_saw_branch_not_taken;\t// @[core.scala:51:7]\n wire io_ifu_get_pc_1_ghist_new_saw_branch_not_taken_0 = io_ifu_get_pc_1_ghist_new_saw_branch_not_taken;\t// @[core.scala:51:7]\n wire io_ifu_get_pc_1_ghist_new_saw_branch_taken_0 = io_ifu_get_pc_1_ghist_new_saw_branch_taken;\t// @[core.scala:51:7]\n wire [4:0] io_ifu_get_pc_1_ghist_ras_idx_0 = io_ifu_get_pc_1_ghist_ras_idx;\t// @[core.scala:51:7]\n wire [39:0] io_ifu_get_pc_1_pc_0 = io_ifu_get_pc_1_pc;\t// @[core.scala:51:7]\n wire [39:0] io_ifu_get_pc_1_com_pc_0 = io_ifu_get_pc_1_com_pc;\t// @[core.scala:51:7]\n wire io_ifu_get_pc_1_next_val_0 = io_ifu_get_pc_1_next_val;\t// @[core.scala:51:7]\n wire [39:0] io_ifu_get_pc_1_next_pc_0 = io_ifu_get_pc_1_next_pc;\t// @[core.scala:51:7]\n wire [39:0] io_ifu_debug_fetch_pc_0_0 = io_ifu_debug_fetch_pc_0;\t// @[core.scala:51:7]\n wire [39:0] io_ifu_debug_fetch_pc_1_0 = io_ifu_debug_fetch_pc_1;\t// @[core.scala:51:7]\n wire [39:0] io_ifu_debug_fetch_pc_2_0 = io_ifu_debug_fetch_pc_2;\t// @[core.scala:51:7]\n wire io_ifu_perf_acquire_0 = io_ifu_perf_acquire;\t// @[core.scala:51:7]\n wire io_ifu_perf_tlbMiss_0 = io_ifu_perf_tlbMiss;\t// @[core.scala:51:7]\n wire io_ptw_perf_l2miss_0 = io_ptw_perf_l2miss;\t// @[core.scala:51:7]\n wire io_ptw_perf_l2hit_0 = io_ptw_perf_l2hit;\t// @[core.scala:51:7]\n wire io_ptw_perf_pte_miss_0 = io_ptw_perf_pte_miss;\t// @[core.scala:51:7]\n wire io_ptw_perf_pte_hit_0 = io_ptw_perf_pte_hit;\t// @[core.scala:51:7]\n wire io_ptw_clock_enabled_0 = io_ptw_clock_enabled;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_iresp_valid_0 = io_lsu_exe_0_iresp_valid;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_exe_0_iresp_bits_uop_uopc_0 = io_lsu_exe_0_iresp_bits_uop_uopc;\t// @[core.scala:51:7]\n wire [31:0] io_lsu_exe_0_iresp_bits_uop_inst_0 = io_lsu_exe_0_iresp_bits_uop_inst;\t// @[core.scala:51:7]\n wire [31:0] io_lsu_exe_0_iresp_bits_uop_debug_inst_0 = io_lsu_exe_0_iresp_bits_uop_debug_inst;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_iresp_bits_uop_is_rvc_0 = io_lsu_exe_0_iresp_bits_uop_is_rvc;\t// @[core.scala:51:7]\n wire [39:0] io_lsu_exe_0_iresp_bits_uop_debug_pc_0 = io_lsu_exe_0_iresp_bits_uop_debug_pc;\t// @[core.scala:51:7]\n wire [2:0] io_lsu_exe_0_iresp_bits_uop_iq_type_0 = io_lsu_exe_0_iresp_bits_uop_iq_type;\t// @[core.scala:51:7]\n wire [9:0] io_lsu_exe_0_iresp_bits_uop_fu_code_0 = io_lsu_exe_0_iresp_bits_uop_fu_code;\t// @[core.scala:51:7]\n wire [3:0] io_lsu_exe_0_iresp_bits_uop_ctrl_br_type_0 = io_lsu_exe_0_iresp_bits_uop_ctrl_br_type;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_exe_0_iresp_bits_uop_ctrl_op1_sel_0 = io_lsu_exe_0_iresp_bits_uop_ctrl_op1_sel;\t// @[core.scala:51:7]\n wire [2:0] io_lsu_exe_0_iresp_bits_uop_ctrl_op2_sel_0 = io_lsu_exe_0_iresp_bits_uop_ctrl_op2_sel;\t// @[core.scala:51:7]\n wire [2:0] io_lsu_exe_0_iresp_bits_uop_ctrl_imm_sel_0 = io_lsu_exe_0_iresp_bits_uop_ctrl_imm_sel;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_exe_0_iresp_bits_uop_ctrl_op_fcn_0 = io_lsu_exe_0_iresp_bits_uop_ctrl_op_fcn;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_iresp_bits_uop_ctrl_fcn_dw_0 = io_lsu_exe_0_iresp_bits_uop_ctrl_fcn_dw;\t// @[core.scala:51:7]\n wire [2:0] io_lsu_exe_0_iresp_bits_uop_ctrl_csr_cmd_0 = io_lsu_exe_0_iresp_bits_uop_ctrl_csr_cmd;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_iresp_bits_uop_ctrl_is_load_0 = io_lsu_exe_0_iresp_bits_uop_ctrl_is_load;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_iresp_bits_uop_ctrl_is_sta_0 = io_lsu_exe_0_iresp_bits_uop_ctrl_is_sta;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_iresp_bits_uop_ctrl_is_std_0 = io_lsu_exe_0_iresp_bits_uop_ctrl_is_std;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_exe_0_iresp_bits_uop_iw_state_0 = io_lsu_exe_0_iresp_bits_uop_iw_state;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_iresp_bits_uop_iw_p1_poisoned_0 = io_lsu_exe_0_iresp_bits_uop_iw_p1_poisoned;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_iresp_bits_uop_iw_p2_poisoned_0 = io_lsu_exe_0_iresp_bits_uop_iw_p2_poisoned;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_iresp_bits_uop_is_br_0 = io_lsu_exe_0_iresp_bits_uop_is_br;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_iresp_bits_uop_is_jalr_0 = io_lsu_exe_0_iresp_bits_uop_is_jalr;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_iresp_bits_uop_is_jal_0 = io_lsu_exe_0_iresp_bits_uop_is_jal;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_iresp_bits_uop_is_sfb_0 = io_lsu_exe_0_iresp_bits_uop_is_sfb;\t// @[core.scala:51:7]\n wire [15:0] io_lsu_exe_0_iresp_bits_uop_br_mask_0 = io_lsu_exe_0_iresp_bits_uop_br_mask;\t// @[core.scala:51:7]\n wire [3:0] io_lsu_exe_0_iresp_bits_uop_br_tag_0 = io_lsu_exe_0_iresp_bits_uop_br_tag;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_exe_0_iresp_bits_uop_ftq_idx_0 = io_lsu_exe_0_iresp_bits_uop_ftq_idx;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_iresp_bits_uop_edge_inst_0 = io_lsu_exe_0_iresp_bits_uop_edge_inst;\t// @[core.scala:51:7]\n wire [5:0] io_lsu_exe_0_iresp_bits_uop_pc_lob_0 = io_lsu_exe_0_iresp_bits_uop_pc_lob;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_iresp_bits_uop_taken_0 = io_lsu_exe_0_iresp_bits_uop_taken;\t// @[core.scala:51:7]\n wire [19:0] io_lsu_exe_0_iresp_bits_uop_imm_packed_0 = io_lsu_exe_0_iresp_bits_uop_imm_packed;\t// @[core.scala:51:7]\n wire [11:0] io_lsu_exe_0_iresp_bits_uop_csr_addr_0 = io_lsu_exe_0_iresp_bits_uop_csr_addr;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_exe_0_iresp_bits_uop_rob_idx_0 = io_lsu_exe_0_iresp_bits_uop_rob_idx;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_exe_0_iresp_bits_uop_ldq_idx_0 = io_lsu_exe_0_iresp_bits_uop_ldq_idx;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_exe_0_iresp_bits_uop_stq_idx_0 = io_lsu_exe_0_iresp_bits_uop_stq_idx;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_exe_0_iresp_bits_uop_rxq_idx_0 = io_lsu_exe_0_iresp_bits_uop_rxq_idx;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_exe_0_iresp_bits_uop_pdst_0 = io_lsu_exe_0_iresp_bits_uop_pdst;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_exe_0_iresp_bits_uop_prs1_0 = io_lsu_exe_0_iresp_bits_uop_prs1;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_exe_0_iresp_bits_uop_prs2_0 = io_lsu_exe_0_iresp_bits_uop_prs2;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_exe_0_iresp_bits_uop_prs3_0 = io_lsu_exe_0_iresp_bits_uop_prs3;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_exe_0_iresp_bits_uop_ppred_0 = io_lsu_exe_0_iresp_bits_uop_ppred;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_iresp_bits_uop_prs1_busy_0 = io_lsu_exe_0_iresp_bits_uop_prs1_busy;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_iresp_bits_uop_prs2_busy_0 = io_lsu_exe_0_iresp_bits_uop_prs2_busy;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_iresp_bits_uop_prs3_busy_0 = io_lsu_exe_0_iresp_bits_uop_prs3_busy;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_iresp_bits_uop_ppred_busy_0 = io_lsu_exe_0_iresp_bits_uop_ppred_busy;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_exe_0_iresp_bits_uop_stale_pdst_0 = io_lsu_exe_0_iresp_bits_uop_stale_pdst;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_iresp_bits_uop_exception_0 = io_lsu_exe_0_iresp_bits_uop_exception;\t// @[core.scala:51:7]\n wire [63:0] io_lsu_exe_0_iresp_bits_uop_exc_cause_0 = io_lsu_exe_0_iresp_bits_uop_exc_cause;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_iresp_bits_uop_bypassable_0 = io_lsu_exe_0_iresp_bits_uop_bypassable;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_exe_0_iresp_bits_uop_mem_cmd_0 = io_lsu_exe_0_iresp_bits_uop_mem_cmd;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_exe_0_iresp_bits_uop_mem_size_0 = io_lsu_exe_0_iresp_bits_uop_mem_size;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_iresp_bits_uop_mem_signed_0 = io_lsu_exe_0_iresp_bits_uop_mem_signed;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_iresp_bits_uop_is_fence_0 = io_lsu_exe_0_iresp_bits_uop_is_fence;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_iresp_bits_uop_is_fencei_0 = io_lsu_exe_0_iresp_bits_uop_is_fencei;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_iresp_bits_uop_is_amo_0 = io_lsu_exe_0_iresp_bits_uop_is_amo;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_iresp_bits_uop_uses_ldq_0 = io_lsu_exe_0_iresp_bits_uop_uses_ldq;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_iresp_bits_uop_uses_stq_0 = io_lsu_exe_0_iresp_bits_uop_uses_stq;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_iresp_bits_uop_is_sys_pc2epc_0 = io_lsu_exe_0_iresp_bits_uop_is_sys_pc2epc;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_iresp_bits_uop_is_unique_0 = io_lsu_exe_0_iresp_bits_uop_is_unique;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_iresp_bits_uop_flush_on_commit_0 = io_lsu_exe_0_iresp_bits_uop_flush_on_commit;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_iresp_bits_uop_ldst_is_rs1_0 = io_lsu_exe_0_iresp_bits_uop_ldst_is_rs1;\t// @[core.scala:51:7]\n wire [5:0] io_lsu_exe_0_iresp_bits_uop_ldst_0 = io_lsu_exe_0_iresp_bits_uop_ldst;\t// @[core.scala:51:7]\n wire [5:0] io_lsu_exe_0_iresp_bits_uop_lrs1_0 = io_lsu_exe_0_iresp_bits_uop_lrs1;\t// @[core.scala:51:7]\n wire [5:0] io_lsu_exe_0_iresp_bits_uop_lrs2_0 = io_lsu_exe_0_iresp_bits_uop_lrs2;\t// @[core.scala:51:7]\n wire [5:0] io_lsu_exe_0_iresp_bits_uop_lrs3_0 = io_lsu_exe_0_iresp_bits_uop_lrs3;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_iresp_bits_uop_ldst_val_0 = io_lsu_exe_0_iresp_bits_uop_ldst_val;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_exe_0_iresp_bits_uop_dst_rtype_0 = io_lsu_exe_0_iresp_bits_uop_dst_rtype;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_exe_0_iresp_bits_uop_lrs1_rtype_0 = io_lsu_exe_0_iresp_bits_uop_lrs1_rtype;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_exe_0_iresp_bits_uop_lrs2_rtype_0 = io_lsu_exe_0_iresp_bits_uop_lrs2_rtype;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_iresp_bits_uop_frs3_en_0 = io_lsu_exe_0_iresp_bits_uop_frs3_en;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_iresp_bits_uop_fp_val_0 = io_lsu_exe_0_iresp_bits_uop_fp_val;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_iresp_bits_uop_fp_single_0 = io_lsu_exe_0_iresp_bits_uop_fp_single;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_iresp_bits_uop_xcpt_pf_if_0 = io_lsu_exe_0_iresp_bits_uop_xcpt_pf_if;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_iresp_bits_uop_xcpt_ae_if_0 = io_lsu_exe_0_iresp_bits_uop_xcpt_ae_if;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_iresp_bits_uop_xcpt_ma_if_0 = io_lsu_exe_0_iresp_bits_uop_xcpt_ma_if;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_iresp_bits_uop_bp_debug_if_0 = io_lsu_exe_0_iresp_bits_uop_bp_debug_if;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_iresp_bits_uop_bp_xcpt_if_0 = io_lsu_exe_0_iresp_bits_uop_bp_xcpt_if;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_exe_0_iresp_bits_uop_debug_fsrc_0 = io_lsu_exe_0_iresp_bits_uop_debug_fsrc;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_exe_0_iresp_bits_uop_debug_tsrc_0 = io_lsu_exe_0_iresp_bits_uop_debug_tsrc;\t// @[core.scala:51:7]\n wire [63:0] io_lsu_exe_0_iresp_bits_data_0 = io_lsu_exe_0_iresp_bits_data;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_fresp_valid_0 = io_lsu_exe_0_fresp_valid;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_exe_0_fresp_bits_uop_uopc_0 = io_lsu_exe_0_fresp_bits_uop_uopc;\t// @[core.scala:51:7]\n wire [31:0] io_lsu_exe_0_fresp_bits_uop_inst_0 = io_lsu_exe_0_fresp_bits_uop_inst;\t// @[core.scala:51:7]\n wire [31:0] io_lsu_exe_0_fresp_bits_uop_debug_inst_0 = io_lsu_exe_0_fresp_bits_uop_debug_inst;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_fresp_bits_uop_is_rvc_0 = io_lsu_exe_0_fresp_bits_uop_is_rvc;\t// @[core.scala:51:7]\n wire [39:0] io_lsu_exe_0_fresp_bits_uop_debug_pc_0 = io_lsu_exe_0_fresp_bits_uop_debug_pc;\t// @[core.scala:51:7]\n wire [2:0] io_lsu_exe_0_fresp_bits_uop_iq_type_0 = io_lsu_exe_0_fresp_bits_uop_iq_type;\t// @[core.scala:51:7]\n wire [9:0] io_lsu_exe_0_fresp_bits_uop_fu_code_0 = io_lsu_exe_0_fresp_bits_uop_fu_code;\t// @[core.scala:51:7]\n wire [3:0] io_lsu_exe_0_fresp_bits_uop_ctrl_br_type_0 = io_lsu_exe_0_fresp_bits_uop_ctrl_br_type;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_exe_0_fresp_bits_uop_ctrl_op1_sel_0 = io_lsu_exe_0_fresp_bits_uop_ctrl_op1_sel;\t// @[core.scala:51:7]\n wire [2:0] io_lsu_exe_0_fresp_bits_uop_ctrl_op2_sel_0 = io_lsu_exe_0_fresp_bits_uop_ctrl_op2_sel;\t// @[core.scala:51:7]\n wire [2:0] io_lsu_exe_0_fresp_bits_uop_ctrl_imm_sel_0 = io_lsu_exe_0_fresp_bits_uop_ctrl_imm_sel;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_exe_0_fresp_bits_uop_ctrl_op_fcn_0 = io_lsu_exe_0_fresp_bits_uop_ctrl_op_fcn;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_fresp_bits_uop_ctrl_fcn_dw_0 = io_lsu_exe_0_fresp_bits_uop_ctrl_fcn_dw;\t// @[core.scala:51:7]\n wire [2:0] io_lsu_exe_0_fresp_bits_uop_ctrl_csr_cmd_0 = io_lsu_exe_0_fresp_bits_uop_ctrl_csr_cmd;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_fresp_bits_uop_ctrl_is_load_0 = io_lsu_exe_0_fresp_bits_uop_ctrl_is_load;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_fresp_bits_uop_ctrl_is_sta_0 = io_lsu_exe_0_fresp_bits_uop_ctrl_is_sta;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_fresp_bits_uop_ctrl_is_std_0 = io_lsu_exe_0_fresp_bits_uop_ctrl_is_std;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_exe_0_fresp_bits_uop_iw_state_0 = io_lsu_exe_0_fresp_bits_uop_iw_state;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_fresp_bits_uop_iw_p1_poisoned_0 = io_lsu_exe_0_fresp_bits_uop_iw_p1_poisoned;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_fresp_bits_uop_iw_p2_poisoned_0 = io_lsu_exe_0_fresp_bits_uop_iw_p2_poisoned;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_fresp_bits_uop_is_br_0 = io_lsu_exe_0_fresp_bits_uop_is_br;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_fresp_bits_uop_is_jalr_0 = io_lsu_exe_0_fresp_bits_uop_is_jalr;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_fresp_bits_uop_is_jal_0 = io_lsu_exe_0_fresp_bits_uop_is_jal;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_fresp_bits_uop_is_sfb_0 = io_lsu_exe_0_fresp_bits_uop_is_sfb;\t// @[core.scala:51:7]\n wire [15:0] io_lsu_exe_0_fresp_bits_uop_br_mask_0 = io_lsu_exe_0_fresp_bits_uop_br_mask;\t// @[core.scala:51:7]\n wire [3:0] io_lsu_exe_0_fresp_bits_uop_br_tag_0 = io_lsu_exe_0_fresp_bits_uop_br_tag;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_exe_0_fresp_bits_uop_ftq_idx_0 = io_lsu_exe_0_fresp_bits_uop_ftq_idx;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_fresp_bits_uop_edge_inst_0 = io_lsu_exe_0_fresp_bits_uop_edge_inst;\t// @[core.scala:51:7]\n wire [5:0] io_lsu_exe_0_fresp_bits_uop_pc_lob_0 = io_lsu_exe_0_fresp_bits_uop_pc_lob;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_fresp_bits_uop_taken_0 = io_lsu_exe_0_fresp_bits_uop_taken;\t// @[core.scala:51:7]\n wire [19:0] io_lsu_exe_0_fresp_bits_uop_imm_packed_0 = io_lsu_exe_0_fresp_bits_uop_imm_packed;\t// @[core.scala:51:7]\n wire [11:0] io_lsu_exe_0_fresp_bits_uop_csr_addr_0 = io_lsu_exe_0_fresp_bits_uop_csr_addr;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_exe_0_fresp_bits_uop_rob_idx_0 = io_lsu_exe_0_fresp_bits_uop_rob_idx;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_exe_0_fresp_bits_uop_ldq_idx_0 = io_lsu_exe_0_fresp_bits_uop_ldq_idx;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_exe_0_fresp_bits_uop_stq_idx_0 = io_lsu_exe_0_fresp_bits_uop_stq_idx;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_exe_0_fresp_bits_uop_rxq_idx_0 = io_lsu_exe_0_fresp_bits_uop_rxq_idx;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_exe_0_fresp_bits_uop_pdst_0 = io_lsu_exe_0_fresp_bits_uop_pdst;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_exe_0_fresp_bits_uop_prs1_0 = io_lsu_exe_0_fresp_bits_uop_prs1;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_exe_0_fresp_bits_uop_prs2_0 = io_lsu_exe_0_fresp_bits_uop_prs2;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_exe_0_fresp_bits_uop_prs3_0 = io_lsu_exe_0_fresp_bits_uop_prs3;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_exe_0_fresp_bits_uop_ppred_0 = io_lsu_exe_0_fresp_bits_uop_ppred;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_fresp_bits_uop_prs1_busy_0 = io_lsu_exe_0_fresp_bits_uop_prs1_busy;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_fresp_bits_uop_prs2_busy_0 = io_lsu_exe_0_fresp_bits_uop_prs2_busy;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_fresp_bits_uop_prs3_busy_0 = io_lsu_exe_0_fresp_bits_uop_prs3_busy;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_fresp_bits_uop_ppred_busy_0 = io_lsu_exe_0_fresp_bits_uop_ppred_busy;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_exe_0_fresp_bits_uop_stale_pdst_0 = io_lsu_exe_0_fresp_bits_uop_stale_pdst;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_fresp_bits_uop_exception_0 = io_lsu_exe_0_fresp_bits_uop_exception;\t// @[core.scala:51:7]\n wire [63:0] io_lsu_exe_0_fresp_bits_uop_exc_cause_0 = io_lsu_exe_0_fresp_bits_uop_exc_cause;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_fresp_bits_uop_bypassable_0 = io_lsu_exe_0_fresp_bits_uop_bypassable;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_exe_0_fresp_bits_uop_mem_cmd_0 = io_lsu_exe_0_fresp_bits_uop_mem_cmd;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_exe_0_fresp_bits_uop_mem_size_0 = io_lsu_exe_0_fresp_bits_uop_mem_size;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_fresp_bits_uop_mem_signed_0 = io_lsu_exe_0_fresp_bits_uop_mem_signed;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_fresp_bits_uop_is_fence_0 = io_lsu_exe_0_fresp_bits_uop_is_fence;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_fresp_bits_uop_is_fencei_0 = io_lsu_exe_0_fresp_bits_uop_is_fencei;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_fresp_bits_uop_is_amo_0 = io_lsu_exe_0_fresp_bits_uop_is_amo;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_fresp_bits_uop_uses_ldq_0 = io_lsu_exe_0_fresp_bits_uop_uses_ldq;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_fresp_bits_uop_uses_stq_0 = io_lsu_exe_0_fresp_bits_uop_uses_stq;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_fresp_bits_uop_is_sys_pc2epc_0 = io_lsu_exe_0_fresp_bits_uop_is_sys_pc2epc;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_fresp_bits_uop_is_unique_0 = io_lsu_exe_0_fresp_bits_uop_is_unique;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_fresp_bits_uop_flush_on_commit_0 = io_lsu_exe_0_fresp_bits_uop_flush_on_commit;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_fresp_bits_uop_ldst_is_rs1_0 = io_lsu_exe_0_fresp_bits_uop_ldst_is_rs1;\t// @[core.scala:51:7]\n wire [5:0] io_lsu_exe_0_fresp_bits_uop_ldst_0 = io_lsu_exe_0_fresp_bits_uop_ldst;\t// @[core.scala:51:7]\n wire [5:0] io_lsu_exe_0_fresp_bits_uop_lrs1_0 = io_lsu_exe_0_fresp_bits_uop_lrs1;\t// @[core.scala:51:7]\n wire [5:0] io_lsu_exe_0_fresp_bits_uop_lrs2_0 = io_lsu_exe_0_fresp_bits_uop_lrs2;\t// @[core.scala:51:7]\n wire [5:0] io_lsu_exe_0_fresp_bits_uop_lrs3_0 = io_lsu_exe_0_fresp_bits_uop_lrs3;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_fresp_bits_uop_ldst_val_0 = io_lsu_exe_0_fresp_bits_uop_ldst_val;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_exe_0_fresp_bits_uop_dst_rtype_0 = io_lsu_exe_0_fresp_bits_uop_dst_rtype;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_exe_0_fresp_bits_uop_lrs1_rtype_0 = io_lsu_exe_0_fresp_bits_uop_lrs1_rtype;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_exe_0_fresp_bits_uop_lrs2_rtype_0 = io_lsu_exe_0_fresp_bits_uop_lrs2_rtype;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_fresp_bits_uop_frs3_en_0 = io_lsu_exe_0_fresp_bits_uop_frs3_en;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_fresp_bits_uop_fp_val_0 = io_lsu_exe_0_fresp_bits_uop_fp_val;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_fresp_bits_uop_fp_single_0 = io_lsu_exe_0_fresp_bits_uop_fp_single;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_fresp_bits_uop_xcpt_pf_if_0 = io_lsu_exe_0_fresp_bits_uop_xcpt_pf_if;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_fresp_bits_uop_xcpt_ae_if_0 = io_lsu_exe_0_fresp_bits_uop_xcpt_ae_if;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_fresp_bits_uop_xcpt_ma_if_0 = io_lsu_exe_0_fresp_bits_uop_xcpt_ma_if;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_fresp_bits_uop_bp_debug_if_0 = io_lsu_exe_0_fresp_bits_uop_bp_debug_if;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_fresp_bits_uop_bp_xcpt_if_0 = io_lsu_exe_0_fresp_bits_uop_bp_xcpt_if;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_exe_0_fresp_bits_uop_debug_fsrc_0 = io_lsu_exe_0_fresp_bits_uop_debug_fsrc;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_exe_0_fresp_bits_uop_debug_tsrc_0 = io_lsu_exe_0_fresp_bits_uop_debug_tsrc;\t// @[core.scala:51:7]\n wire [64:0] io_lsu_exe_0_fresp_bits_data_0 = io_lsu_exe_0_fresp_bits_data;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_dis_ldq_idx_0_0 = io_lsu_dis_ldq_idx_0;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_dis_ldq_idx_1_0 = io_lsu_dis_ldq_idx_1;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_dis_ldq_idx_2_0 = io_lsu_dis_ldq_idx_2;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_dis_stq_idx_0_0 = io_lsu_dis_stq_idx_0;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_dis_stq_idx_1_0 = io_lsu_dis_stq_idx_1;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_dis_stq_idx_2_0 = io_lsu_dis_stq_idx_2;\t// @[core.scala:51:7]\n wire io_lsu_ldq_full_0_0 = io_lsu_ldq_full_0;\t// @[core.scala:51:7]\n wire io_lsu_ldq_full_1_0 = io_lsu_ldq_full_1;\t// @[core.scala:51:7]\n wire io_lsu_ldq_full_2_0 = io_lsu_ldq_full_2;\t// @[core.scala:51:7]\n wire io_lsu_stq_full_0_0 = io_lsu_stq_full_0;\t// @[core.scala:51:7]\n wire io_lsu_stq_full_1_0 = io_lsu_stq_full_1;\t// @[core.scala:51:7]\n wire io_lsu_stq_full_2_0 = io_lsu_stq_full_2;\t// @[core.scala:51:7]\n wire io_lsu_fp_stdata_ready_0 = io_lsu_fp_stdata_ready;\t// @[core.scala:51:7]\n wire io_lsu_clr_bsy_0_valid_0 = io_lsu_clr_bsy_0_valid;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_clr_bsy_0_bits_0 = io_lsu_clr_bsy_0_bits;\t// @[core.scala:51:7]\n wire io_lsu_clr_bsy_1_valid_0 = io_lsu_clr_bsy_1_valid;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_clr_bsy_1_bits_0 = io_lsu_clr_bsy_1_bits;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_clr_unsafe_0_bits_0 = io_lsu_clr_unsafe_0_bits;\t// @[core.scala:51:7]\n wire io_lsu_spec_ld_wakeup_0_valid_0 = io_lsu_spec_ld_wakeup_0_valid;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_spec_ld_wakeup_0_bits_0 = io_lsu_spec_ld_wakeup_0_bits;\t// @[core.scala:51:7]\n wire io_lsu_ld_miss_0 = io_lsu_ld_miss;\t// @[core.scala:51:7]\n wire io_lsu_fencei_rdy_0 = io_lsu_fencei_rdy;\t// @[core.scala:51:7]\n wire io_lsu_lxcpt_valid_0 = io_lsu_lxcpt_valid;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_lxcpt_bits_uop_uopc_0 = io_lsu_lxcpt_bits_uop_uopc;\t// @[core.scala:51:7]\n wire [31:0] io_lsu_lxcpt_bits_uop_inst_0 = io_lsu_lxcpt_bits_uop_inst;\t// @[core.scala:51:7]\n wire [31:0] io_lsu_lxcpt_bits_uop_debug_inst_0 = io_lsu_lxcpt_bits_uop_debug_inst;\t// @[core.scala:51:7]\n wire io_lsu_lxcpt_bits_uop_is_rvc_0 = io_lsu_lxcpt_bits_uop_is_rvc;\t// @[core.scala:51:7]\n wire [39:0] io_lsu_lxcpt_bits_uop_debug_pc_0 = io_lsu_lxcpt_bits_uop_debug_pc;\t// @[core.scala:51:7]\n wire [2:0] io_lsu_lxcpt_bits_uop_iq_type_0 = io_lsu_lxcpt_bits_uop_iq_type;\t// @[core.scala:51:7]\n wire [9:0] io_lsu_lxcpt_bits_uop_fu_code_0 = io_lsu_lxcpt_bits_uop_fu_code;\t// @[core.scala:51:7]\n wire [3:0] io_lsu_lxcpt_bits_uop_ctrl_br_type_0 = io_lsu_lxcpt_bits_uop_ctrl_br_type;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_lxcpt_bits_uop_ctrl_op1_sel_0 = io_lsu_lxcpt_bits_uop_ctrl_op1_sel;\t// @[core.scala:51:7]\n wire [2:0] io_lsu_lxcpt_bits_uop_ctrl_op2_sel_0 = io_lsu_lxcpt_bits_uop_ctrl_op2_sel;\t// @[core.scala:51:7]\n wire [2:0] io_lsu_lxcpt_bits_uop_ctrl_imm_sel_0 = io_lsu_lxcpt_bits_uop_ctrl_imm_sel;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_lxcpt_bits_uop_ctrl_op_fcn_0 = io_lsu_lxcpt_bits_uop_ctrl_op_fcn;\t// @[core.scala:51:7]\n wire io_lsu_lxcpt_bits_uop_ctrl_fcn_dw_0 = io_lsu_lxcpt_bits_uop_ctrl_fcn_dw;\t// @[core.scala:51:7]\n wire [2:0] io_lsu_lxcpt_bits_uop_ctrl_csr_cmd_0 = io_lsu_lxcpt_bits_uop_ctrl_csr_cmd;\t// @[core.scala:51:7]\n wire io_lsu_lxcpt_bits_uop_ctrl_is_load_0 = io_lsu_lxcpt_bits_uop_ctrl_is_load;\t// @[core.scala:51:7]\n wire io_lsu_lxcpt_bits_uop_ctrl_is_sta_0 = io_lsu_lxcpt_bits_uop_ctrl_is_sta;\t// @[core.scala:51:7]\n wire io_lsu_lxcpt_bits_uop_ctrl_is_std_0 = io_lsu_lxcpt_bits_uop_ctrl_is_std;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_lxcpt_bits_uop_iw_state_0 = io_lsu_lxcpt_bits_uop_iw_state;\t// @[core.scala:51:7]\n wire io_lsu_lxcpt_bits_uop_iw_p1_poisoned_0 = io_lsu_lxcpt_bits_uop_iw_p1_poisoned;\t// @[core.scala:51:7]\n wire io_lsu_lxcpt_bits_uop_iw_p2_poisoned_0 = io_lsu_lxcpt_bits_uop_iw_p2_poisoned;\t// @[core.scala:51:7]\n wire io_lsu_lxcpt_bits_uop_is_br_0 = io_lsu_lxcpt_bits_uop_is_br;\t// @[core.scala:51:7]\n wire io_lsu_lxcpt_bits_uop_is_jalr_0 = io_lsu_lxcpt_bits_uop_is_jalr;\t// @[core.scala:51:7]\n wire io_lsu_lxcpt_bits_uop_is_jal_0 = io_lsu_lxcpt_bits_uop_is_jal;\t// @[core.scala:51:7]\n wire io_lsu_lxcpt_bits_uop_is_sfb_0 = io_lsu_lxcpt_bits_uop_is_sfb;\t// @[core.scala:51:7]\n wire [15:0] io_lsu_lxcpt_bits_uop_br_mask_0 = io_lsu_lxcpt_bits_uop_br_mask;\t// @[core.scala:51:7]\n wire [3:0] io_lsu_lxcpt_bits_uop_br_tag_0 = io_lsu_lxcpt_bits_uop_br_tag;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_lxcpt_bits_uop_ftq_idx_0 = io_lsu_lxcpt_bits_uop_ftq_idx;\t// @[core.scala:51:7]\n wire io_lsu_lxcpt_bits_uop_edge_inst_0 = io_lsu_lxcpt_bits_uop_edge_inst;\t// @[core.scala:51:7]\n wire [5:0] io_lsu_lxcpt_bits_uop_pc_lob_0 = io_lsu_lxcpt_bits_uop_pc_lob;\t// @[core.scala:51:7]\n wire io_lsu_lxcpt_bits_uop_taken_0 = io_lsu_lxcpt_bits_uop_taken;\t// @[core.scala:51:7]\n wire [19:0] io_lsu_lxcpt_bits_uop_imm_packed_0 = io_lsu_lxcpt_bits_uop_imm_packed;\t// @[core.scala:51:7]\n wire [11:0] io_lsu_lxcpt_bits_uop_csr_addr_0 = io_lsu_lxcpt_bits_uop_csr_addr;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_lxcpt_bits_uop_rob_idx_0 = io_lsu_lxcpt_bits_uop_rob_idx;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_lxcpt_bits_uop_ldq_idx_0 = io_lsu_lxcpt_bits_uop_ldq_idx;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_lxcpt_bits_uop_stq_idx_0 = io_lsu_lxcpt_bits_uop_stq_idx;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_lxcpt_bits_uop_rxq_idx_0 = io_lsu_lxcpt_bits_uop_rxq_idx;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_lxcpt_bits_uop_pdst_0 = io_lsu_lxcpt_bits_uop_pdst;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_lxcpt_bits_uop_prs1_0 = io_lsu_lxcpt_bits_uop_prs1;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_lxcpt_bits_uop_prs2_0 = io_lsu_lxcpt_bits_uop_prs2;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_lxcpt_bits_uop_prs3_0 = io_lsu_lxcpt_bits_uop_prs3;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_lxcpt_bits_uop_ppred_0 = io_lsu_lxcpt_bits_uop_ppred;\t// @[core.scala:51:7]\n wire io_lsu_lxcpt_bits_uop_prs1_busy_0 = io_lsu_lxcpt_bits_uop_prs1_busy;\t// @[core.scala:51:7]\n wire io_lsu_lxcpt_bits_uop_prs2_busy_0 = io_lsu_lxcpt_bits_uop_prs2_busy;\t// @[core.scala:51:7]\n wire io_lsu_lxcpt_bits_uop_prs3_busy_0 = io_lsu_lxcpt_bits_uop_prs3_busy;\t// @[core.scala:51:7]\n wire io_lsu_lxcpt_bits_uop_ppred_busy_0 = io_lsu_lxcpt_bits_uop_ppred_busy;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_lxcpt_bits_uop_stale_pdst_0 = io_lsu_lxcpt_bits_uop_stale_pdst;\t// @[core.scala:51:7]\n wire io_lsu_lxcpt_bits_uop_exception_0 = io_lsu_lxcpt_bits_uop_exception;\t// @[core.scala:51:7]\n wire [63:0] io_lsu_lxcpt_bits_uop_exc_cause_0 = io_lsu_lxcpt_bits_uop_exc_cause;\t// @[core.scala:51:7]\n wire io_lsu_lxcpt_bits_uop_bypassable_0 = io_lsu_lxcpt_bits_uop_bypassable;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_lxcpt_bits_uop_mem_cmd_0 = io_lsu_lxcpt_bits_uop_mem_cmd;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_lxcpt_bits_uop_mem_size_0 = io_lsu_lxcpt_bits_uop_mem_size;\t// @[core.scala:51:7]\n wire io_lsu_lxcpt_bits_uop_mem_signed_0 = io_lsu_lxcpt_bits_uop_mem_signed;\t// @[core.scala:51:7]\n wire io_lsu_lxcpt_bits_uop_is_fence_0 = io_lsu_lxcpt_bits_uop_is_fence;\t// @[core.scala:51:7]\n wire io_lsu_lxcpt_bits_uop_is_fencei_0 = io_lsu_lxcpt_bits_uop_is_fencei;\t// @[core.scala:51:7]\n wire io_lsu_lxcpt_bits_uop_is_amo_0 = io_lsu_lxcpt_bits_uop_is_amo;\t// @[core.scala:51:7]\n wire io_lsu_lxcpt_bits_uop_uses_ldq_0 = io_lsu_lxcpt_bits_uop_uses_ldq;\t// @[core.scala:51:7]\n wire io_lsu_lxcpt_bits_uop_uses_stq_0 = io_lsu_lxcpt_bits_uop_uses_stq;\t// @[core.scala:51:7]\n wire io_lsu_lxcpt_bits_uop_is_sys_pc2epc_0 = io_lsu_lxcpt_bits_uop_is_sys_pc2epc;\t// @[core.scala:51:7]\n wire io_lsu_lxcpt_bits_uop_is_unique_0 = io_lsu_lxcpt_bits_uop_is_unique;\t// @[core.scala:51:7]\n wire io_lsu_lxcpt_bits_uop_flush_on_commit_0 = io_lsu_lxcpt_bits_uop_flush_on_commit;\t// @[core.scala:51:7]\n wire io_lsu_lxcpt_bits_uop_ldst_is_rs1_0 = io_lsu_lxcpt_bits_uop_ldst_is_rs1;\t// @[core.scala:51:7]\n wire [5:0] io_lsu_lxcpt_bits_uop_ldst_0 = io_lsu_lxcpt_bits_uop_ldst;\t// @[core.scala:51:7]\n wire [5:0] io_lsu_lxcpt_bits_uop_lrs1_0 = io_lsu_lxcpt_bits_uop_lrs1;\t// @[core.scala:51:7]\n wire [5:0] io_lsu_lxcpt_bits_uop_lrs2_0 = io_lsu_lxcpt_bits_uop_lrs2;\t// @[core.scala:51:7]\n wire [5:0] io_lsu_lxcpt_bits_uop_lrs3_0 = io_lsu_lxcpt_bits_uop_lrs3;\t// @[core.scala:51:7]\n wire io_lsu_lxcpt_bits_uop_ldst_val_0 = io_lsu_lxcpt_bits_uop_ldst_val;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_lxcpt_bits_uop_dst_rtype_0 = io_lsu_lxcpt_bits_uop_dst_rtype;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_lxcpt_bits_uop_lrs1_rtype_0 = io_lsu_lxcpt_bits_uop_lrs1_rtype;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_lxcpt_bits_uop_lrs2_rtype_0 = io_lsu_lxcpt_bits_uop_lrs2_rtype;\t// @[core.scala:51:7]\n wire io_lsu_lxcpt_bits_uop_frs3_en_0 = io_lsu_lxcpt_bits_uop_frs3_en;\t// @[core.scala:51:7]\n wire io_lsu_lxcpt_bits_uop_fp_val_0 = io_lsu_lxcpt_bits_uop_fp_val;\t// @[core.scala:51:7]\n wire io_lsu_lxcpt_bits_uop_fp_single_0 = io_lsu_lxcpt_bits_uop_fp_single;\t// @[core.scala:51:7]\n wire io_lsu_lxcpt_bits_uop_xcpt_pf_if_0 = io_lsu_lxcpt_bits_uop_xcpt_pf_if;\t// @[core.scala:51:7]\n wire io_lsu_lxcpt_bits_uop_xcpt_ae_if_0 = io_lsu_lxcpt_bits_uop_xcpt_ae_if;\t// @[core.scala:51:7]\n wire io_lsu_lxcpt_bits_uop_xcpt_ma_if_0 = io_lsu_lxcpt_bits_uop_xcpt_ma_if;\t// @[core.scala:51:7]\n wire io_lsu_lxcpt_bits_uop_bp_debug_if_0 = io_lsu_lxcpt_bits_uop_bp_debug_if;\t// @[core.scala:51:7]\n wire io_lsu_lxcpt_bits_uop_bp_xcpt_if_0 = io_lsu_lxcpt_bits_uop_bp_xcpt_if;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_lxcpt_bits_uop_debug_fsrc_0 = io_lsu_lxcpt_bits_uop_debug_fsrc;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_lxcpt_bits_uop_debug_tsrc_0 = io_lsu_lxcpt_bits_uop_debug_tsrc;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_lxcpt_bits_cause_0 = io_lsu_lxcpt_bits_cause;\t// @[core.scala:51:7]\n wire [39:0] io_lsu_lxcpt_bits_badvaddr_0 = io_lsu_lxcpt_bits_badvaddr;\t// @[core.scala:51:7]\n wire io_lsu_perf_acquire_0 = io_lsu_perf_acquire;\t// @[core.scala:51:7]\n wire io_lsu_perf_release_0 = io_lsu_perf_release;\t// @[core.scala:51:7]\n wire io_lsu_perf_tlbMiss_0 = io_lsu_perf_tlbMiss;\t// @[core.scala:51:7]\n wire io_ptw_tlb_req_ready_0 = io_ptw_tlb_req_ready;\t// @[core.scala:51:7]\n wire io_ptw_tlb_resp_valid_0 = io_ptw_tlb_resp_valid;\t// @[core.scala:51:7]\n wire io_ptw_tlb_resp_bits_ae_ptw_0 = io_ptw_tlb_resp_bits_ae_ptw;\t// @[core.scala:51:7]\n wire io_ptw_tlb_resp_bits_ae_final_0 = io_ptw_tlb_resp_bits_ae_final;\t// @[core.scala:51:7]\n wire io_ptw_tlb_resp_bits_pf_0 = io_ptw_tlb_resp_bits_pf;\t// @[core.scala:51:7]\n wire io_ptw_tlb_resp_bits_gf_0 = io_ptw_tlb_resp_bits_gf;\t// @[core.scala:51:7]\n wire io_ptw_tlb_resp_bits_hr_0 = io_ptw_tlb_resp_bits_hr;\t// @[core.scala:51:7]\n wire io_ptw_tlb_resp_bits_hw_0 = io_ptw_tlb_resp_bits_hw;\t// @[core.scala:51:7]\n wire io_ptw_tlb_resp_bits_hx_0 = io_ptw_tlb_resp_bits_hx;\t// @[core.scala:51:7]\n wire [9:0] io_ptw_tlb_resp_bits_pte_reserved_for_future_0 = io_ptw_tlb_resp_bits_pte_reserved_for_future;\t// @[core.scala:51:7]\n wire [43:0] io_ptw_tlb_resp_bits_pte_ppn_0 = io_ptw_tlb_resp_bits_pte_ppn;\t// @[core.scala:51:7]\n wire [1:0] io_ptw_tlb_resp_bits_pte_reserved_for_software_0 = io_ptw_tlb_resp_bits_pte_reserved_for_software;\t// @[core.scala:51:7]\n wire io_ptw_tlb_resp_bits_pte_d_0 = io_ptw_tlb_resp_bits_pte_d;\t// @[core.scala:51:7]\n wire io_ptw_tlb_resp_bits_pte_a_0 = io_ptw_tlb_resp_bits_pte_a;\t// @[core.scala:51:7]\n wire io_ptw_tlb_resp_bits_pte_g_0 = io_ptw_tlb_resp_bits_pte_g;\t// @[core.scala:51:7]\n wire io_ptw_tlb_resp_bits_pte_u_0 = io_ptw_tlb_resp_bits_pte_u;\t// @[core.scala:51:7]\n wire io_ptw_tlb_resp_bits_pte_x_0 = io_ptw_tlb_resp_bits_pte_x;\t// @[core.scala:51:7]\n wire io_ptw_tlb_resp_bits_pte_w_0 = io_ptw_tlb_resp_bits_pte_w;\t// @[core.scala:51:7]\n wire io_ptw_tlb_resp_bits_pte_r_0 = io_ptw_tlb_resp_bits_pte_r;\t// @[core.scala:51:7]\n wire io_ptw_tlb_resp_bits_pte_v_0 = io_ptw_tlb_resp_bits_pte_v;\t// @[core.scala:51:7]\n wire [1:0] io_ptw_tlb_resp_bits_level_0 = io_ptw_tlb_resp_bits_level;\t// @[core.scala:51:7]\n wire io_ptw_tlb_resp_bits_homogeneous_0 = io_ptw_tlb_resp_bits_homogeneous;\t// @[core.scala:51:7]\n wire io_ptw_tlb_resp_bits_gpa_valid_0 = io_ptw_tlb_resp_bits_gpa_valid;\t// @[core.scala:51:7]\n wire [38:0] io_ptw_tlb_resp_bits_gpa_bits_0 = io_ptw_tlb_resp_bits_gpa_bits;\t// @[core.scala:51:7]\n wire io_ptw_tlb_resp_bits_gpa_is_pte_0 = io_ptw_tlb_resp_bits_gpa_is_pte;\t// @[core.scala:51:7]\n wire [3:0] io_ptw_tlb_ptbr_mode_0 = io_ptw_tlb_ptbr_mode;\t// @[core.scala:51:7]\n wire [43:0] io_ptw_tlb_ptbr_ppn_0 = io_ptw_tlb_ptbr_ppn;\t// @[core.scala:51:7]\n wire io_ptw_tlb_status_debug_0 = io_ptw_tlb_status_debug;\t// @[core.scala:51:7]\n wire io_ptw_tlb_status_cease_0 = io_ptw_tlb_status_cease;\t// @[core.scala:51:7]\n wire io_ptw_tlb_status_wfi_0 = io_ptw_tlb_status_wfi;\t// @[core.scala:51:7]\n wire [1:0] io_ptw_tlb_status_dprv_0 = io_ptw_tlb_status_dprv;\t// @[core.scala:51:7]\n wire io_ptw_tlb_status_dv_0 = io_ptw_tlb_status_dv;\t// @[core.scala:51:7]\n wire [1:0] io_ptw_tlb_status_prv_0 = io_ptw_tlb_status_prv;\t// @[core.scala:51:7]\n wire io_ptw_tlb_status_v_0 = io_ptw_tlb_status_v;\t// @[core.scala:51:7]\n wire io_ptw_tlb_status_sd_0 = io_ptw_tlb_status_sd;\t// @[core.scala:51:7]\n wire io_ptw_tlb_status_mpv_0 = io_ptw_tlb_status_mpv;\t// @[core.scala:51:7]\n wire io_ptw_tlb_status_gva_0 = io_ptw_tlb_status_gva;\t// @[core.scala:51:7]\n wire io_ptw_tlb_status_tsr_0 = io_ptw_tlb_status_tsr;\t// @[core.scala:51:7]\n wire io_ptw_tlb_status_tw_0 = io_ptw_tlb_status_tw;\t// @[core.scala:51:7]\n wire io_ptw_tlb_status_tvm_0 = io_ptw_tlb_status_tvm;\t// @[core.scala:51:7]\n wire io_ptw_tlb_status_mxr_0 = io_ptw_tlb_status_mxr;\t// @[core.scala:51:7]\n wire io_ptw_tlb_status_sum_0 = io_ptw_tlb_status_sum;\t// @[core.scala:51:7]\n wire io_ptw_tlb_status_mprv_0 = io_ptw_tlb_status_mprv;\t// @[core.scala:51:7]\n wire [1:0] io_ptw_tlb_status_fs_0 = io_ptw_tlb_status_fs;\t// @[core.scala:51:7]\n wire [1:0] io_ptw_tlb_status_mpp_0 = io_ptw_tlb_status_mpp;\t// @[core.scala:51:7]\n wire io_ptw_tlb_status_spp_0 = io_ptw_tlb_status_spp;\t// @[core.scala:51:7]\n wire io_ptw_tlb_status_mpie_0 = io_ptw_tlb_status_mpie;\t// @[core.scala:51:7]\n wire io_ptw_tlb_status_spie_0 = io_ptw_tlb_status_spie;\t// @[core.scala:51:7]\n wire io_ptw_tlb_status_mie_0 = io_ptw_tlb_status_mie;\t// @[core.scala:51:7]\n wire io_ptw_tlb_status_sie_0 = io_ptw_tlb_status_sie;\t// @[core.scala:51:7]\n wire io_ptw_tlb_pmp_0_cfg_l_0 = io_ptw_tlb_pmp_0_cfg_l;\t// @[core.scala:51:7]\n wire [1:0] io_ptw_tlb_pmp_0_cfg_a_0 = io_ptw_tlb_pmp_0_cfg_a;\t// @[core.scala:51:7]\n wire io_ptw_tlb_pmp_0_cfg_x_0 = io_ptw_tlb_pmp_0_cfg_x;\t// @[core.scala:51:7]\n wire io_ptw_tlb_pmp_0_cfg_w_0 = io_ptw_tlb_pmp_0_cfg_w;\t// @[core.scala:51:7]\n wire io_ptw_tlb_pmp_0_cfg_r_0 = io_ptw_tlb_pmp_0_cfg_r;\t// @[core.scala:51:7]\n wire [29:0] io_ptw_tlb_pmp_0_addr_0 = io_ptw_tlb_pmp_0_addr;\t// @[core.scala:51:7]\n wire [31:0] io_ptw_tlb_pmp_0_mask_0 = io_ptw_tlb_pmp_0_mask;\t// @[core.scala:51:7]\n wire io_ptw_tlb_pmp_1_cfg_l_0 = io_ptw_tlb_pmp_1_cfg_l;\t// @[core.scala:51:7]\n wire [1:0] io_ptw_tlb_pmp_1_cfg_a_0 = io_ptw_tlb_pmp_1_cfg_a;\t// @[core.scala:51:7]\n wire io_ptw_tlb_pmp_1_cfg_x_0 = io_ptw_tlb_pmp_1_cfg_x;\t// @[core.scala:51:7]\n wire io_ptw_tlb_pmp_1_cfg_w_0 = io_ptw_tlb_pmp_1_cfg_w;\t// @[core.scala:51:7]\n wire io_ptw_tlb_pmp_1_cfg_r_0 = io_ptw_tlb_pmp_1_cfg_r;\t// @[core.scala:51:7]\n wire [29:0] io_ptw_tlb_pmp_1_addr_0 = io_ptw_tlb_pmp_1_addr;\t// @[core.scala:51:7]\n wire [31:0] io_ptw_tlb_pmp_1_mask_0 = io_ptw_tlb_pmp_1_mask;\t// @[core.scala:51:7]\n wire io_ptw_tlb_pmp_2_cfg_l_0 = io_ptw_tlb_pmp_2_cfg_l;\t// @[core.scala:51:7]\n wire [1:0] io_ptw_tlb_pmp_2_cfg_a_0 = io_ptw_tlb_pmp_2_cfg_a;\t// @[core.scala:51:7]\n wire io_ptw_tlb_pmp_2_cfg_x_0 = io_ptw_tlb_pmp_2_cfg_x;\t// @[core.scala:51:7]\n wire io_ptw_tlb_pmp_2_cfg_w_0 = io_ptw_tlb_pmp_2_cfg_w;\t// @[core.scala:51:7]\n wire io_ptw_tlb_pmp_2_cfg_r_0 = io_ptw_tlb_pmp_2_cfg_r;\t// @[core.scala:51:7]\n wire [29:0] io_ptw_tlb_pmp_2_addr_0 = io_ptw_tlb_pmp_2_addr;\t// @[core.scala:51:7]\n wire [31:0] io_ptw_tlb_pmp_2_mask_0 = io_ptw_tlb_pmp_2_mask;\t// @[core.scala:51:7]\n wire io_ptw_tlb_pmp_3_cfg_l_0 = io_ptw_tlb_pmp_3_cfg_l;\t// @[core.scala:51:7]\n wire [1:0] io_ptw_tlb_pmp_3_cfg_a_0 = io_ptw_tlb_pmp_3_cfg_a;\t// @[core.scala:51:7]\n wire io_ptw_tlb_pmp_3_cfg_x_0 = io_ptw_tlb_pmp_3_cfg_x;\t// @[core.scala:51:7]\n wire io_ptw_tlb_pmp_3_cfg_w_0 = io_ptw_tlb_pmp_3_cfg_w;\t// @[core.scala:51:7]\n wire io_ptw_tlb_pmp_3_cfg_r_0 = io_ptw_tlb_pmp_3_cfg_r;\t// @[core.scala:51:7]\n wire [29:0] io_ptw_tlb_pmp_3_addr_0 = io_ptw_tlb_pmp_3_addr;\t// @[core.scala:51:7]\n wire [31:0] io_ptw_tlb_pmp_3_mask_0 = io_ptw_tlb_pmp_3_mask;\t// @[core.scala:51:7]\n wire io_ptw_tlb_pmp_4_cfg_l_0 = io_ptw_tlb_pmp_4_cfg_l;\t// @[core.scala:51:7]\n wire [1:0] io_ptw_tlb_pmp_4_cfg_a_0 = io_ptw_tlb_pmp_4_cfg_a;\t// @[core.scala:51:7]\n wire io_ptw_tlb_pmp_4_cfg_x_0 = io_ptw_tlb_pmp_4_cfg_x;\t// @[core.scala:51:7]\n wire io_ptw_tlb_pmp_4_cfg_w_0 = io_ptw_tlb_pmp_4_cfg_w;\t// @[core.scala:51:7]\n wire io_ptw_tlb_pmp_4_cfg_r_0 = io_ptw_tlb_pmp_4_cfg_r;\t// @[core.scala:51:7]\n wire [29:0] io_ptw_tlb_pmp_4_addr_0 = io_ptw_tlb_pmp_4_addr;\t// @[core.scala:51:7]\n wire [31:0] io_ptw_tlb_pmp_4_mask_0 = io_ptw_tlb_pmp_4_mask;\t// @[core.scala:51:7]\n wire io_ptw_tlb_pmp_5_cfg_l_0 = io_ptw_tlb_pmp_5_cfg_l;\t// @[core.scala:51:7]\n wire [1:0] io_ptw_tlb_pmp_5_cfg_a_0 = io_ptw_tlb_pmp_5_cfg_a;\t// @[core.scala:51:7]\n wire io_ptw_tlb_pmp_5_cfg_x_0 = io_ptw_tlb_pmp_5_cfg_x;\t// @[core.scala:51:7]\n wire io_ptw_tlb_pmp_5_cfg_w_0 = io_ptw_tlb_pmp_5_cfg_w;\t// @[core.scala:51:7]\n wire io_ptw_tlb_pmp_5_cfg_r_0 = io_ptw_tlb_pmp_5_cfg_r;\t// @[core.scala:51:7]\n wire [29:0] io_ptw_tlb_pmp_5_addr_0 = io_ptw_tlb_pmp_5_addr;\t// @[core.scala:51:7]\n wire [31:0] io_ptw_tlb_pmp_5_mask_0 = io_ptw_tlb_pmp_5_mask;\t// @[core.scala:51:7]\n wire io_ptw_tlb_pmp_6_cfg_l_0 = io_ptw_tlb_pmp_6_cfg_l;\t// @[core.scala:51:7]\n wire [1:0] io_ptw_tlb_pmp_6_cfg_a_0 = io_ptw_tlb_pmp_6_cfg_a;\t// @[core.scala:51:7]\n wire io_ptw_tlb_pmp_6_cfg_x_0 = io_ptw_tlb_pmp_6_cfg_x;\t// @[core.scala:51:7]\n wire io_ptw_tlb_pmp_6_cfg_w_0 = io_ptw_tlb_pmp_6_cfg_w;\t// @[core.scala:51:7]\n wire io_ptw_tlb_pmp_6_cfg_r_0 = io_ptw_tlb_pmp_6_cfg_r;\t// @[core.scala:51:7]\n wire [29:0] io_ptw_tlb_pmp_6_addr_0 = io_ptw_tlb_pmp_6_addr;\t// @[core.scala:51:7]\n wire [31:0] io_ptw_tlb_pmp_6_mask_0 = io_ptw_tlb_pmp_6_mask;\t// @[core.scala:51:7]\n wire io_ptw_tlb_pmp_7_cfg_l_0 = io_ptw_tlb_pmp_7_cfg_l;\t// @[core.scala:51:7]\n wire [1:0] io_ptw_tlb_pmp_7_cfg_a_0 = io_ptw_tlb_pmp_7_cfg_a;\t// @[core.scala:51:7]\n wire io_ptw_tlb_pmp_7_cfg_x_0 = io_ptw_tlb_pmp_7_cfg_x;\t// @[core.scala:51:7]\n wire io_ptw_tlb_pmp_7_cfg_w_0 = io_ptw_tlb_pmp_7_cfg_w;\t// @[core.scala:51:7]\n wire io_ptw_tlb_pmp_7_cfg_r_0 = io_ptw_tlb_pmp_7_cfg_r;\t// @[core.scala:51:7]\n wire [29:0] io_ptw_tlb_pmp_7_addr_0 = io_ptw_tlb_pmp_7_addr;\t// @[core.scala:51:7]\n wire [31:0] io_ptw_tlb_pmp_7_mask_0 = io_ptw_tlb_pmp_7_mask;\t// @[core.scala:51:7]\n wire coreMonitorBundle_clock = clock;\t// @[core.scala:1405:31]\n wire coreMonitorBundle_reset = reset;\t// @[core.scala:1405:31]\n wire [6:0] io_ifu_fetchpacket_bits_uops_0_bits_uopc = 7'h0;\t// @[core.scala:51:7]\n wire [6:0] io_ifu_fetchpacket_bits_uops_0_bits_rob_idx = 7'h0;\t// @[core.scala:51:7]\n wire [6:0] io_ifu_fetchpacket_bits_uops_0_bits_pdst = 7'h0;\t// @[core.scala:51:7]\n wire [6:0] io_ifu_fetchpacket_bits_uops_0_bits_prs1 = 7'h0;\t// @[core.scala:51:7]\n wire [6:0] io_ifu_fetchpacket_bits_uops_0_bits_prs2 = 7'h0;\t// @[core.scala:51:7]\n wire [6:0] io_ifu_fetchpacket_bits_uops_0_bits_prs3 = 7'h0;\t// @[core.scala:51:7]\n wire [6:0] io_ifu_fetchpacket_bits_uops_0_bits_stale_pdst = 7'h0;\t// @[core.scala:51:7]\n wire [6:0] io_ifu_fetchpacket_bits_uops_1_bits_uopc = 7'h0;\t// @[core.scala:51:7]\n wire [6:0] io_ifu_fetchpacket_bits_uops_1_bits_rob_idx = 7'h0;\t// @[core.scala:51:7]\n wire [6:0] io_ifu_fetchpacket_bits_uops_1_bits_pdst = 7'h0;\t// @[core.scala:51:7]\n wire [6:0] io_ifu_fetchpacket_bits_uops_1_bits_prs1 = 7'h0;\t// @[core.scala:51:7]\n wire [6:0] io_ifu_fetchpacket_bits_uops_1_bits_prs2 = 7'h0;\t// @[core.scala:51:7]\n wire [6:0] io_ifu_fetchpacket_bits_uops_1_bits_prs3 = 7'h0;\t// @[core.scala:51:7]\n wire [6:0] io_ifu_fetchpacket_bits_uops_1_bits_stale_pdst = 7'h0;\t// @[core.scala:51:7]\n wire [6:0] io_ifu_fetchpacket_bits_uops_2_bits_uopc = 7'h0;\t// @[core.scala:51:7]\n wire [6:0] io_ifu_fetchpacket_bits_uops_2_bits_rob_idx = 7'h0;\t// @[core.scala:51:7]\n wire [6:0] io_ifu_fetchpacket_bits_uops_2_bits_pdst = 7'h0;\t// @[core.scala:51:7]\n wire [6:0] io_ifu_fetchpacket_bits_uops_2_bits_prs1 = 7'h0;\t// @[core.scala:51:7]\n wire [6:0] io_ifu_fetchpacket_bits_uops_2_bits_prs2 = 7'h0;\t// @[core.scala:51:7]\n wire [6:0] io_ifu_fetchpacket_bits_uops_2_bits_prs3 = 7'h0;\t// @[core.scala:51:7]\n wire [6:0] io_ifu_fetchpacket_bits_uops_2_bits_stale_pdst = 7'h0;\t// @[core.scala:51:7]\n wire [6:0] io_rocc_cmd_bits_inst_funct = 7'h0;\t// @[core.scala:51:7]\n wire [6:0] io_rocc_cmd_bits_inst_opcode = 7'h0;\t// @[core.scala:51:7]\n wire [6:0] io_rocc_mem_req_bits_tag = 7'h0;\t// @[core.scala:51:7]\n wire [6:0] io_rocc_mem_resp_bits_tag = 7'h0;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_exe_0_req_bits_fflags_bits_uop_uopc = 7'h0;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_exe_0_req_bits_fflags_bits_uop_rob_idx = 7'h0;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_exe_0_req_bits_fflags_bits_uop_pdst = 7'h0;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_exe_0_req_bits_fflags_bits_uop_prs1 = 7'h0;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_exe_0_req_bits_fflags_bits_uop_prs2 = 7'h0;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_exe_0_req_bits_fflags_bits_uop_prs3 = 7'h0;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_exe_0_req_bits_fflags_bits_uop_stale_pdst = 7'h0;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_uopc = 7'h0;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_rob_idx = 7'h0;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_pdst = 7'h0;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_prs1 = 7'h0;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_prs2 = 7'h0;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_prs3 = 7'h0;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_stale_pdst = 7'h0;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_uopc = 7'h0;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_rob_idx = 7'h0;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_pdst = 7'h0;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_prs1 = 7'h0;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_prs2 = 7'h0;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_prs3 = 7'h0;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_stale_pdst = 7'h0;\t// @[core.scala:51:7]\n wire [6:0] int_iss_wakeups_1_bits_fflags_bits_uop_uopc = 7'h0;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_1_bits_fflags_bits_uop_rob_idx = 7'h0;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_1_bits_fflags_bits_uop_pdst = 7'h0;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_1_bits_fflags_bits_uop_prs1 = 7'h0;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_1_bits_fflags_bits_uop_prs2 = 7'h0;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_1_bits_fflags_bits_uop_prs3 = 7'h0;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_1_bits_fflags_bits_uop_stale_pdst = 7'h0;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_2_bits_fflags_bits_uop_uopc = 7'h0;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_2_bits_fflags_bits_uop_rob_idx = 7'h0;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_2_bits_fflags_bits_uop_pdst = 7'h0;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_2_bits_fflags_bits_uop_prs1 = 7'h0;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_2_bits_fflags_bits_uop_prs2 = 7'h0;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_2_bits_fflags_bits_uop_prs3 = 7'h0;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_2_bits_fflags_bits_uop_stale_pdst = 7'h0;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_3_bits_fflags_bits_uop_uopc = 7'h0;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_3_bits_fflags_bits_uop_rob_idx = 7'h0;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_3_bits_fflags_bits_uop_pdst = 7'h0;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_3_bits_fflags_bits_uop_prs1 = 7'h0;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_3_bits_fflags_bits_uop_prs2 = 7'h0;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_3_bits_fflags_bits_uop_prs3 = 7'h0;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_3_bits_fflags_bits_uop_stale_pdst = 7'h0;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_4_bits_fflags_bits_uop_uopc = 7'h0;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_4_bits_fflags_bits_uop_rob_idx = 7'h0;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_4_bits_fflags_bits_uop_pdst = 7'h0;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_4_bits_fflags_bits_uop_prs1 = 7'h0;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_4_bits_fflags_bits_uop_prs2 = 7'h0;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_4_bits_fflags_bits_uop_prs3 = 7'h0;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_4_bits_fflags_bits_uop_stale_pdst = 7'h0;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_5_bits_fflags_bits_uop_uopc = 7'h0;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_5_bits_fflags_bits_uop_rob_idx = 7'h0;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_5_bits_fflags_bits_uop_pdst = 7'h0;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_5_bits_fflags_bits_uop_prs1 = 7'h0;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_5_bits_fflags_bits_uop_prs2 = 7'h0;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_5_bits_fflags_bits_uop_prs3 = 7'h0;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_5_bits_fflags_bits_uop_stale_pdst = 7'h0;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_6_bits_fflags_bits_uop_uopc = 7'h0;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_6_bits_fflags_bits_uop_rob_idx = 7'h0;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_6_bits_fflags_bits_uop_pdst = 7'h0;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_6_bits_fflags_bits_uop_prs1 = 7'h0;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_6_bits_fflags_bits_uop_prs2 = 7'h0;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_6_bits_fflags_bits_uop_prs3 = 7'h0;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_6_bits_fflags_bits_uop_stale_pdst = 7'h0;\t// @[core.scala:147:30]\n wire [6:0] int_ren_wakeups_1_bits_fflags_bits_uop_uopc = 7'h0;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_1_bits_fflags_bits_uop_rob_idx = 7'h0;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_1_bits_fflags_bits_uop_pdst = 7'h0;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_1_bits_fflags_bits_uop_prs1 = 7'h0;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_1_bits_fflags_bits_uop_prs2 = 7'h0;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_1_bits_fflags_bits_uop_prs3 = 7'h0;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_1_bits_fflags_bits_uop_stale_pdst = 7'h0;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_2_bits_fflags_bits_uop_uopc = 7'h0;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_2_bits_fflags_bits_uop_rob_idx = 7'h0;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_2_bits_fflags_bits_uop_pdst = 7'h0;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_2_bits_fflags_bits_uop_prs1 = 7'h0;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_2_bits_fflags_bits_uop_prs2 = 7'h0;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_2_bits_fflags_bits_uop_prs3 = 7'h0;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_2_bits_fflags_bits_uop_stale_pdst = 7'h0;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_3_bits_fflags_bits_uop_uopc = 7'h0;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_3_bits_fflags_bits_uop_rob_idx = 7'h0;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_3_bits_fflags_bits_uop_pdst = 7'h0;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_3_bits_fflags_bits_uop_prs1 = 7'h0;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_3_bits_fflags_bits_uop_prs2 = 7'h0;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_3_bits_fflags_bits_uop_prs3 = 7'h0;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_3_bits_fflags_bits_uop_stale_pdst = 7'h0;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_4_bits_fflags_bits_uop_uopc = 7'h0;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_4_bits_fflags_bits_uop_rob_idx = 7'h0;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_4_bits_fflags_bits_uop_pdst = 7'h0;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_4_bits_fflags_bits_uop_prs1 = 7'h0;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_4_bits_fflags_bits_uop_prs2 = 7'h0;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_4_bits_fflags_bits_uop_prs3 = 7'h0;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_4_bits_fflags_bits_uop_stale_pdst = 7'h0;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_5_bits_fflags_bits_uop_uopc = 7'h0;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_5_bits_fflags_bits_uop_rob_idx = 7'h0;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_5_bits_fflags_bits_uop_pdst = 7'h0;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_5_bits_fflags_bits_uop_prs1 = 7'h0;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_5_bits_fflags_bits_uop_prs2 = 7'h0;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_5_bits_fflags_bits_uop_prs3 = 7'h0;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_5_bits_fflags_bits_uop_stale_pdst = 7'h0;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_6_bits_fflags_bits_uop_uopc = 7'h0;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_6_bits_fflags_bits_uop_rob_idx = 7'h0;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_6_bits_fflags_bits_uop_pdst = 7'h0;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_6_bits_fflags_bits_uop_prs1 = 7'h0;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_6_bits_fflags_bits_uop_prs2 = 7'h0;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_6_bits_fflags_bits_uop_prs3 = 7'h0;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_6_bits_fflags_bits_uop_stale_pdst = 7'h0;\t// @[core.scala:148:30]\n wire [6:0] pred_wakeup_bits_fflags_bits_uop_uopc = 7'h0;\t// @[core.scala:149:26]\n wire [6:0] pred_wakeup_bits_fflags_bits_uop_rob_idx = 7'h0;\t// @[core.scala:149:26]\n wire [6:0] pred_wakeup_bits_fflags_bits_uop_pdst = 7'h0;\t// @[core.scala:149:26]\n wire [6:0] pred_wakeup_bits_fflags_bits_uop_prs1 = 7'h0;\t// @[core.scala:149:26]\n wire [6:0] pred_wakeup_bits_fflags_bits_uop_prs2 = 7'h0;\t// @[core.scala:149:26]\n wire [6:0] pred_wakeup_bits_fflags_bits_uop_prs3 = 7'h0;\t// @[core.scala:149:26]\n wire [6:0] pred_wakeup_bits_fflags_bits_uop_stale_pdst = 7'h0;\t// @[core.scala:149:26]\n wire [6:0] dec_uops_0_rob_idx = 7'h0;\t// @[core.scala:158:24]\n wire [6:0] dec_uops_0_pdst = 7'h0;\t// @[core.scala:158:24]\n wire [6:0] dec_uops_0_prs1 = 7'h0;\t// @[core.scala:158:24]\n wire [6:0] dec_uops_0_prs2 = 7'h0;\t// @[core.scala:158:24]\n wire [6:0] dec_uops_0_prs3 = 7'h0;\t// @[core.scala:158:24]\n wire [6:0] dec_uops_0_stale_pdst = 7'h0;\t// @[core.scala:158:24]\n wire [6:0] dec_uops_1_rob_idx = 7'h0;\t// @[core.scala:158:24]\n wire [6:0] dec_uops_1_pdst = 7'h0;\t// @[core.scala:158:24]\n wire [6:0] dec_uops_1_prs1 = 7'h0;\t// @[core.scala:158:24]\n wire [6:0] dec_uops_1_prs2 = 7'h0;\t// @[core.scala:158:24]\n wire [6:0] dec_uops_1_prs3 = 7'h0;\t// @[core.scala:158:24]\n wire [6:0] dec_uops_1_stale_pdst = 7'h0;\t// @[core.scala:158:24]\n wire [6:0] dec_uops_2_rob_idx = 7'h0;\t// @[core.scala:158:24]\n wire [6:0] dec_uops_2_pdst = 7'h0;\t// @[core.scala:158:24]\n wire [6:0] dec_uops_2_prs1 = 7'h0;\t// @[core.scala:158:24]\n wire [6:0] dec_uops_2_prs2 = 7'h0;\t// @[core.scala:158:24]\n wire [6:0] dec_uops_2_prs3 = 7'h0;\t// @[core.scala:158:24]\n wire [6:0] dec_uops_2_stale_pdst = 7'h0;\t// @[core.scala:158:24]\n wire [6:0] bypasses_0_bits_fflags_bits_uop_uopc = 7'h0;\t// @[core.scala:174:24]\n wire [6:0] bypasses_0_bits_fflags_bits_uop_rob_idx = 7'h0;\t// @[core.scala:174:24]\n wire [6:0] bypasses_0_bits_fflags_bits_uop_pdst = 7'h0;\t// @[core.scala:174:24]\n wire [6:0] bypasses_0_bits_fflags_bits_uop_prs1 = 7'h0;\t// @[core.scala:174:24]\n wire [6:0] bypasses_0_bits_fflags_bits_uop_prs2 = 7'h0;\t// @[core.scala:174:24]\n wire [6:0] bypasses_0_bits_fflags_bits_uop_prs3 = 7'h0;\t// @[core.scala:174:24]\n wire [6:0] bypasses_0_bits_fflags_bits_uop_stale_pdst = 7'h0;\t// @[core.scala:174:24]\n wire [6:0] bypasses_1_bits_fflags_bits_uop_uopc = 7'h0;\t// @[core.scala:174:24]\n wire [6:0] bypasses_1_bits_fflags_bits_uop_rob_idx = 7'h0;\t// @[core.scala:174:24]\n wire [6:0] bypasses_1_bits_fflags_bits_uop_pdst = 7'h0;\t// @[core.scala:174:24]\n wire [6:0] bypasses_1_bits_fflags_bits_uop_prs1 = 7'h0;\t// @[core.scala:174:24]\n wire [6:0] bypasses_1_bits_fflags_bits_uop_prs2 = 7'h0;\t// @[core.scala:174:24]\n wire [6:0] bypasses_1_bits_fflags_bits_uop_prs3 = 7'h0;\t// @[core.scala:174:24]\n wire [6:0] bypasses_1_bits_fflags_bits_uop_stale_pdst = 7'h0;\t// @[core.scala:174:24]\n wire [6:0] bypasses_2_bits_fflags_bits_uop_uopc = 7'h0;\t// @[core.scala:174:24]\n wire [6:0] bypasses_2_bits_fflags_bits_uop_rob_idx = 7'h0;\t// @[core.scala:174:24]\n wire [6:0] bypasses_2_bits_fflags_bits_uop_pdst = 7'h0;\t// @[core.scala:174:24]\n wire [6:0] bypasses_2_bits_fflags_bits_uop_prs1 = 7'h0;\t// @[core.scala:174:24]\n wire [6:0] bypasses_2_bits_fflags_bits_uop_prs2 = 7'h0;\t// @[core.scala:174:24]\n wire [6:0] bypasses_2_bits_fflags_bits_uop_prs3 = 7'h0;\t// @[core.scala:174:24]\n wire [6:0] bypasses_2_bits_fflags_bits_uop_stale_pdst = 7'h0;\t// @[core.scala:174:24]\n wire [6:0] bypasses_3_bits_fflags_bits_uop_uopc = 7'h0;\t// @[core.scala:174:24]\n wire [6:0] bypasses_3_bits_fflags_bits_uop_rob_idx = 7'h0;\t// @[core.scala:174:24]\n wire [6:0] bypasses_3_bits_fflags_bits_uop_pdst = 7'h0;\t// @[core.scala:174:24]\n wire [6:0] bypasses_3_bits_fflags_bits_uop_prs1 = 7'h0;\t// @[core.scala:174:24]\n wire [6:0] bypasses_3_bits_fflags_bits_uop_prs2 = 7'h0;\t// @[core.scala:174:24]\n wire [6:0] bypasses_3_bits_fflags_bits_uop_prs3 = 7'h0;\t// @[core.scala:174:24]\n wire [6:0] bypasses_3_bits_fflags_bits_uop_stale_pdst = 7'h0;\t// @[core.scala:174:24]\n wire [6:0] bypasses_4_bits_fflags_bits_uop_uopc = 7'h0;\t// @[core.scala:174:24]\n wire [6:0] bypasses_4_bits_fflags_bits_uop_rob_idx = 7'h0;\t// @[core.scala:174:24]\n wire [6:0] bypasses_4_bits_fflags_bits_uop_pdst = 7'h0;\t// @[core.scala:174:24]\n wire [6:0] bypasses_4_bits_fflags_bits_uop_prs1 = 7'h0;\t// @[core.scala:174:24]\n wire [6:0] bypasses_4_bits_fflags_bits_uop_prs2 = 7'h0;\t// @[core.scala:174:24]\n wire [6:0] bypasses_4_bits_fflags_bits_uop_prs3 = 7'h0;\t// @[core.scala:174:24]\n wire [6:0] bypasses_4_bits_fflags_bits_uop_stale_pdst = 7'h0;\t// @[core.scala:174:24]\n wire [6:0] pred_bypasses_0_bits_fflags_bits_uop_uopc = 7'h0;\t// @[core.scala:175:27]\n wire [6:0] pred_bypasses_0_bits_fflags_bits_uop_rob_idx = 7'h0;\t// @[core.scala:175:27]\n wire [6:0] pred_bypasses_0_bits_fflags_bits_uop_pdst = 7'h0;\t// @[core.scala:175:27]\n wire [6:0] pred_bypasses_0_bits_fflags_bits_uop_prs1 = 7'h0;\t// @[core.scala:175:27]\n wire [6:0] pred_bypasses_0_bits_fflags_bits_uop_prs2 = 7'h0;\t// @[core.scala:175:27]\n wire [6:0] pred_bypasses_0_bits_fflags_bits_uop_prs3 = 7'h0;\t// @[core.scala:175:27]\n wire [6:0] pred_bypasses_0_bits_fflags_bits_uop_stale_pdst = 7'h0;\t// @[core.scala:175:27]\n wire [6:0] p_uop_uopc = 7'h0;\t// @[consts.scala:269:19]\n wire [6:0] p_uop_rob_idx = 7'h0;\t// @[consts.scala:269:19]\n wire [6:0] p_uop_pdst = 7'h0;\t// @[consts.scala:269:19]\n wire [6:0] p_uop_prs1 = 7'h0;\t// @[consts.scala:269:19]\n wire [6:0] p_uop_prs2 = 7'h0;\t// @[consts.scala:269:19]\n wire [6:0] p_uop_prs3 = 7'h0;\t// @[consts.scala:269:19]\n wire [6:0] p_uop_stale_pdst = 7'h0;\t// @[consts.scala:269:19]\n wire [6:0] p_uop_1_uopc = 7'h0;\t// @[consts.scala:269:19]\n wire [6:0] p_uop_1_rob_idx = 7'h0;\t// @[consts.scala:269:19]\n wire [6:0] p_uop_1_pdst = 7'h0;\t// @[consts.scala:269:19]\n wire [6:0] p_uop_1_prs1 = 7'h0;\t// @[consts.scala:269:19]\n wire [6:0] p_uop_1_prs2 = 7'h0;\t// @[consts.scala:269:19]\n wire [6:0] p_uop_1_prs3 = 7'h0;\t// @[consts.scala:269:19]\n wire [6:0] p_uop_1_stale_pdst = 7'h0;\t// @[consts.scala:269:19]\n wire [6:0] p_uop_2_uopc = 7'h0;\t// @[consts.scala:269:19]\n wire [6:0] p_uop_2_rob_idx = 7'h0;\t// @[consts.scala:269:19]\n wire [6:0] p_uop_2_pdst = 7'h0;\t// @[consts.scala:269:19]\n wire [6:0] p_uop_2_prs1 = 7'h0;\t// @[consts.scala:269:19]\n wire [6:0] p_uop_2_prs2 = 7'h0;\t// @[consts.scala:269:19]\n wire [6:0] p_uop_2_prs3 = 7'h0;\t// @[consts.scala:269:19]\n wire [6:0] p_uop_2_stale_pdst = 7'h0;\t// @[consts.scala:269:19]\n wire [6:0] fast_wakeup_bits_fflags_bits_uop_uopc = 7'h0;\t// @[core.scala:814:29]\n wire [6:0] fast_wakeup_bits_fflags_bits_uop_rob_idx = 7'h0;\t// @[core.scala:814:29]\n wire [6:0] fast_wakeup_bits_fflags_bits_uop_pdst = 7'h0;\t// @[core.scala:814:29]\n wire [6:0] fast_wakeup_bits_fflags_bits_uop_prs1 = 7'h0;\t// @[core.scala:814:29]\n wire [6:0] fast_wakeup_bits_fflags_bits_uop_prs2 = 7'h0;\t// @[core.scala:814:29]\n wire [6:0] fast_wakeup_bits_fflags_bits_uop_prs3 = 7'h0;\t// @[core.scala:814:29]\n wire [6:0] fast_wakeup_bits_fflags_bits_uop_stale_pdst = 7'h0;\t// @[core.scala:814:29]\n wire [6:0] slow_wakeup_bits_fflags_bits_uop_uopc = 7'h0;\t// @[core.scala:815:29]\n wire [6:0] slow_wakeup_bits_fflags_bits_uop_rob_idx = 7'h0;\t// @[core.scala:815:29]\n wire [6:0] slow_wakeup_bits_fflags_bits_uop_pdst = 7'h0;\t// @[core.scala:815:29]\n wire [6:0] slow_wakeup_bits_fflags_bits_uop_prs1 = 7'h0;\t// @[core.scala:815:29]\n wire [6:0] slow_wakeup_bits_fflags_bits_uop_prs2 = 7'h0;\t// @[core.scala:815:29]\n wire [6:0] slow_wakeup_bits_fflags_bits_uop_prs3 = 7'h0;\t// @[core.scala:815:29]\n wire [6:0] slow_wakeup_bits_fflags_bits_uop_stale_pdst = 7'h0;\t// @[core.scala:815:29]\n wire [6:0] fast_wakeup_1_bits_fflags_bits_uop_uopc = 7'h0;\t// @[core.scala:814:29]\n wire [6:0] fast_wakeup_1_bits_fflags_bits_uop_rob_idx = 7'h0;\t// @[core.scala:814:29]\n wire [6:0] fast_wakeup_1_bits_fflags_bits_uop_pdst = 7'h0;\t// @[core.scala:814:29]\n wire [6:0] fast_wakeup_1_bits_fflags_bits_uop_prs1 = 7'h0;\t// @[core.scala:814:29]\n wire [6:0] fast_wakeup_1_bits_fflags_bits_uop_prs2 = 7'h0;\t// @[core.scala:814:29]\n wire [6:0] fast_wakeup_1_bits_fflags_bits_uop_prs3 = 7'h0;\t// @[core.scala:814:29]\n wire [6:0] fast_wakeup_1_bits_fflags_bits_uop_stale_pdst = 7'h0;\t// @[core.scala:814:29]\n wire [6:0] slow_wakeup_1_bits_fflags_bits_uop_uopc = 7'h0;\t// @[core.scala:815:29]\n wire [6:0] slow_wakeup_1_bits_fflags_bits_uop_rob_idx = 7'h0;\t// @[core.scala:815:29]\n wire [6:0] slow_wakeup_1_bits_fflags_bits_uop_pdst = 7'h0;\t// @[core.scala:815:29]\n wire [6:0] slow_wakeup_1_bits_fflags_bits_uop_prs1 = 7'h0;\t// @[core.scala:815:29]\n wire [6:0] slow_wakeup_1_bits_fflags_bits_uop_prs2 = 7'h0;\t// @[core.scala:815:29]\n wire [6:0] slow_wakeup_1_bits_fflags_bits_uop_prs3 = 7'h0;\t// @[core.scala:815:29]\n wire [6:0] slow_wakeup_1_bits_fflags_bits_uop_stale_pdst = 7'h0;\t// @[core.scala:815:29]\n wire [6:0] fast_wakeup_2_bits_fflags_bits_uop_uopc = 7'h0;\t// @[core.scala:814:29]\n wire [6:0] fast_wakeup_2_bits_fflags_bits_uop_rob_idx = 7'h0;\t// @[core.scala:814:29]\n wire [6:0] fast_wakeup_2_bits_fflags_bits_uop_pdst = 7'h0;\t// @[core.scala:814:29]\n wire [6:0] fast_wakeup_2_bits_fflags_bits_uop_prs1 = 7'h0;\t// @[core.scala:814:29]\n wire [6:0] fast_wakeup_2_bits_fflags_bits_uop_prs2 = 7'h0;\t// @[core.scala:814:29]\n wire [6:0] fast_wakeup_2_bits_fflags_bits_uop_prs3 = 7'h0;\t// @[core.scala:814:29]\n wire [6:0] fast_wakeup_2_bits_fflags_bits_uop_stale_pdst = 7'h0;\t// @[core.scala:814:29]\n wire [6:0] slow_wakeup_2_bits_fflags_bits_uop_uopc = 7'h0;\t// @[core.scala:815:29]\n wire [6:0] slow_wakeup_2_bits_fflags_bits_uop_rob_idx = 7'h0;\t// @[core.scala:815:29]\n wire [6:0] slow_wakeup_2_bits_fflags_bits_uop_pdst = 7'h0;\t// @[core.scala:815:29]\n wire [6:0] slow_wakeup_2_bits_fflags_bits_uop_prs1 = 7'h0;\t// @[core.scala:815:29]\n wire [6:0] slow_wakeup_2_bits_fflags_bits_uop_prs2 = 7'h0;\t// @[core.scala:815:29]\n wire [6:0] slow_wakeup_2_bits_fflags_bits_uop_prs3 = 7'h0;\t// @[core.scala:815:29]\n wire [6:0] slow_wakeup_2_bits_fflags_bits_uop_stale_pdst = 7'h0;\t// @[core.scala:815:29]\n wire [2:0] io_ifu_fetchpacket_bits_uops_0_bits_iq_type = 3'h0;\t// @[core.scala:51:7]\n wire [2:0] io_ifu_fetchpacket_bits_uops_0_bits_ctrl_op2_sel = 3'h0;\t// @[core.scala:51:7]\n wire [2:0] io_ifu_fetchpacket_bits_uops_0_bits_ctrl_imm_sel = 3'h0;\t// @[core.scala:51:7]\n wire [2:0] io_ifu_fetchpacket_bits_uops_0_bits_ctrl_csr_cmd = 3'h0;\t// @[core.scala:51:7]\n wire [2:0] io_ifu_fetchpacket_bits_uops_1_bits_iq_type = 3'h0;\t// @[core.scala:51:7]\n wire [2:0] io_ifu_fetchpacket_bits_uops_1_bits_ctrl_op2_sel = 3'h0;\t// @[core.scala:51:7]\n wire [2:0] io_ifu_fetchpacket_bits_uops_1_bits_ctrl_imm_sel = 3'h0;\t// @[core.scala:51:7]\n wire [2:0] io_ifu_fetchpacket_bits_uops_1_bits_ctrl_csr_cmd = 3'h0;\t// @[core.scala:51:7]\n wire [2:0] io_ifu_fetchpacket_bits_uops_2_bits_iq_type = 3'h0;\t// @[core.scala:51:7]\n wire [2:0] io_ifu_fetchpacket_bits_uops_2_bits_ctrl_op2_sel = 3'h0;\t// @[core.scala:51:7]\n wire [2:0] io_ifu_fetchpacket_bits_uops_2_bits_ctrl_imm_sel = 3'h0;\t// @[core.scala:51:7]\n wire [2:0] io_ifu_fetchpacket_bits_uops_2_bits_ctrl_csr_cmd = 3'h0;\t// @[core.scala:51:7]\n wire [2:0] io_lsu_exe_0_req_bits_fflags_bits_uop_iq_type = 3'h0;\t// @[core.scala:51:7]\n wire [2:0] io_lsu_exe_0_req_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0;\t// @[core.scala:51:7]\n wire [2:0] io_lsu_exe_0_req_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0;\t// @[core.scala:51:7]\n wire [2:0] io_lsu_exe_0_req_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0;\t// @[core.scala:51:7]\n wire [2:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_iq_type = 3'h0;\t// @[core.scala:51:7]\n wire [2:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0;\t// @[core.scala:51:7]\n wire [2:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0;\t// @[core.scala:51:7]\n wire [2:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0;\t// @[core.scala:51:7]\n wire [2:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_iq_type = 3'h0;\t// @[core.scala:51:7]\n wire [2:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0;\t// @[core.scala:51:7]\n wire [2:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0;\t// @[core.scala:51:7]\n wire [2:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0;\t// @[core.scala:51:7]\n wire [2:0] io_trace_insns_0_priv = 3'h0;\t// @[core.scala:51:7]\n wire [2:0] io_trace_insns_1_priv = 3'h0;\t// @[core.scala:51:7]\n wire [2:0] io_trace_insns_2_priv = 3'h0;\t// @[core.scala:51:7]\n wire [2:0] int_iss_wakeups_1_bits_fflags_bits_uop_iq_type = 3'h0;\t// @[core.scala:147:30]\n wire [2:0] int_iss_wakeups_1_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0;\t// @[core.scala:147:30]\n wire [2:0] int_iss_wakeups_1_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0;\t// @[core.scala:147:30]\n wire [2:0] int_iss_wakeups_1_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0;\t// @[core.scala:147:30]\n wire [2:0] int_iss_wakeups_2_bits_fflags_bits_uop_iq_type = 3'h0;\t// @[core.scala:147:30]\n wire [2:0] int_iss_wakeups_2_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0;\t// @[core.scala:147:30]\n wire [2:0] int_iss_wakeups_2_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0;\t// @[core.scala:147:30]\n wire [2:0] int_iss_wakeups_2_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0;\t// @[core.scala:147:30]\n wire [2:0] int_iss_wakeups_3_bits_fflags_bits_uop_iq_type = 3'h0;\t// @[core.scala:147:30]\n wire [2:0] int_iss_wakeups_3_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0;\t// @[core.scala:147:30]\n wire [2:0] int_iss_wakeups_3_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0;\t// @[core.scala:147:30]\n wire [2:0] int_iss_wakeups_3_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0;\t// @[core.scala:147:30]\n wire [2:0] int_iss_wakeups_4_bits_fflags_bits_uop_iq_type = 3'h0;\t// @[core.scala:147:30]\n wire [2:0] int_iss_wakeups_4_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0;\t// @[core.scala:147:30]\n wire [2:0] int_iss_wakeups_4_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0;\t// @[core.scala:147:30]\n wire [2:0] int_iss_wakeups_4_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0;\t// @[core.scala:147:30]\n wire [2:0] int_iss_wakeups_5_bits_fflags_bits_uop_iq_type = 3'h0;\t// @[core.scala:147:30]\n wire [2:0] int_iss_wakeups_5_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0;\t// @[core.scala:147:30]\n wire [2:0] int_iss_wakeups_5_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0;\t// @[core.scala:147:30]\n wire [2:0] int_iss_wakeups_5_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0;\t// @[core.scala:147:30]\n wire [2:0] int_iss_wakeups_6_bits_fflags_bits_uop_iq_type = 3'h0;\t// @[core.scala:147:30]\n wire [2:0] int_iss_wakeups_6_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0;\t// @[core.scala:147:30]\n wire [2:0] int_iss_wakeups_6_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0;\t// @[core.scala:147:30]\n wire [2:0] int_iss_wakeups_6_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0;\t// @[core.scala:147:30]\n wire [2:0] int_ren_wakeups_1_bits_fflags_bits_uop_iq_type = 3'h0;\t// @[core.scala:148:30]\n wire [2:0] int_ren_wakeups_1_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0;\t// @[core.scala:148:30]\n wire [2:0] int_ren_wakeups_1_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0;\t// @[core.scala:148:30]\n wire [2:0] int_ren_wakeups_1_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0;\t// @[core.scala:148:30]\n wire [2:0] int_ren_wakeups_2_bits_fflags_bits_uop_iq_type = 3'h0;\t// @[core.scala:148:30]\n wire [2:0] int_ren_wakeups_2_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0;\t// @[core.scala:148:30]\n wire [2:0] int_ren_wakeups_2_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0;\t// @[core.scala:148:30]\n wire [2:0] int_ren_wakeups_2_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0;\t// @[core.scala:148:30]\n wire [2:0] int_ren_wakeups_3_bits_fflags_bits_uop_iq_type = 3'h0;\t// @[core.scala:148:30]\n wire [2:0] int_ren_wakeups_3_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0;\t// @[core.scala:148:30]\n wire [2:0] int_ren_wakeups_3_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0;\t// @[core.scala:148:30]\n wire [2:0] int_ren_wakeups_3_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0;\t// @[core.scala:148:30]\n wire [2:0] int_ren_wakeups_4_bits_fflags_bits_uop_iq_type = 3'h0;\t// @[core.scala:148:30]\n wire [2:0] int_ren_wakeups_4_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0;\t// @[core.scala:148:30]\n wire [2:0] int_ren_wakeups_4_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0;\t// @[core.scala:148:30]\n wire [2:0] int_ren_wakeups_4_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0;\t// @[core.scala:148:30]\n wire [2:0] int_ren_wakeups_5_bits_fflags_bits_uop_iq_type = 3'h0;\t// @[core.scala:148:30]\n wire [2:0] int_ren_wakeups_5_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0;\t// @[core.scala:148:30]\n wire [2:0] int_ren_wakeups_5_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0;\t// @[core.scala:148:30]\n wire [2:0] int_ren_wakeups_5_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0;\t// @[core.scala:148:30]\n wire [2:0] int_ren_wakeups_6_bits_fflags_bits_uop_iq_type = 3'h0;\t// @[core.scala:148:30]\n wire [2:0] int_ren_wakeups_6_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0;\t// @[core.scala:148:30]\n wire [2:0] int_ren_wakeups_6_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0;\t// @[core.scala:148:30]\n wire [2:0] int_ren_wakeups_6_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0;\t// @[core.scala:148:30]\n wire [2:0] pred_wakeup_bits_fflags_bits_uop_iq_type = 3'h0;\t// @[core.scala:149:26]\n wire [2:0] pred_wakeup_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0;\t// @[core.scala:149:26]\n wire [2:0] pred_wakeup_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0;\t// @[core.scala:149:26]\n wire [2:0] pred_wakeup_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0;\t// @[core.scala:149:26]\n wire [2:0] dec_uops_0_ctrl_op2_sel = 3'h0;\t// @[core.scala:158:24]\n wire [2:0] dec_uops_0_ctrl_imm_sel = 3'h0;\t// @[core.scala:158:24]\n wire [2:0] dec_uops_0_ctrl_csr_cmd = 3'h0;\t// @[core.scala:158:24]\n wire [2:0] dec_uops_1_ctrl_op2_sel = 3'h0;\t// @[core.scala:158:24]\n wire [2:0] dec_uops_1_ctrl_imm_sel = 3'h0;\t// @[core.scala:158:24]\n wire [2:0] dec_uops_1_ctrl_csr_cmd = 3'h0;\t// @[core.scala:158:24]\n wire [2:0] dec_uops_2_ctrl_op2_sel = 3'h0;\t// @[core.scala:158:24]\n wire [2:0] dec_uops_2_ctrl_imm_sel = 3'h0;\t// @[core.scala:158:24]\n wire [2:0] dec_uops_2_ctrl_csr_cmd = 3'h0;\t// @[core.scala:158:24]\n wire [2:0] bypasses_0_bits_fflags_bits_uop_iq_type = 3'h0;\t// @[core.scala:174:24]\n wire [2:0] bypasses_0_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0;\t// @[core.scala:174:24]\n wire [2:0] bypasses_0_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0;\t// @[core.scala:174:24]\n wire [2:0] bypasses_0_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0;\t// @[core.scala:174:24]\n wire [2:0] bypasses_1_bits_fflags_bits_uop_iq_type = 3'h0;\t// @[core.scala:174:24]\n wire [2:0] bypasses_1_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0;\t// @[core.scala:174:24]\n wire [2:0] bypasses_1_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0;\t// @[core.scala:174:24]\n wire [2:0] bypasses_1_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0;\t// @[core.scala:174:24]\n wire [2:0] bypasses_2_bits_fflags_bits_uop_iq_type = 3'h0;\t// @[core.scala:174:24]\n wire [2:0] bypasses_2_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0;\t// @[core.scala:174:24]\n wire [2:0] bypasses_2_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0;\t// @[core.scala:174:24]\n wire [2:0] bypasses_2_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0;\t// @[core.scala:174:24]\n wire [2:0] bypasses_3_bits_fflags_bits_uop_iq_type = 3'h0;\t// @[core.scala:174:24]\n wire [2:0] bypasses_3_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0;\t// @[core.scala:174:24]\n wire [2:0] bypasses_3_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0;\t// @[core.scala:174:24]\n wire [2:0] bypasses_3_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0;\t// @[core.scala:174:24]\n wire [2:0] bypasses_4_bits_fflags_bits_uop_iq_type = 3'h0;\t// @[core.scala:174:24]\n wire [2:0] bypasses_4_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0;\t// @[core.scala:174:24]\n wire [2:0] bypasses_4_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0;\t// @[core.scala:174:24]\n wire [2:0] bypasses_4_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0;\t// @[core.scala:174:24]\n wire [2:0] pred_bypasses_0_bits_fflags_bits_uop_iq_type = 3'h0;\t// @[core.scala:175:27]\n wire [2:0] pred_bypasses_0_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0;\t// @[core.scala:175:27]\n wire [2:0] pred_bypasses_0_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0;\t// @[core.scala:175:27]\n wire [2:0] pred_bypasses_0_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0;\t// @[core.scala:175:27]\n wire [2:0] p_uop_iq_type = 3'h0;\t// @[consts.scala:269:19]\n wire [2:0] p_uop_ctrl_op2_sel = 3'h0;\t// @[consts.scala:269:19]\n wire [2:0] p_uop_ctrl_imm_sel = 3'h0;\t// @[consts.scala:269:19]\n wire [2:0] p_uop_ctrl_csr_cmd = 3'h0;\t// @[consts.scala:269:19]\n wire [2:0] p_uop_cs_op2_sel = 3'h0;\t// @[consts.scala:279:18]\n wire [2:0] p_uop_cs_imm_sel = 3'h0;\t// @[consts.scala:279:18]\n wire [2:0] p_uop_cs_csr_cmd = 3'h0;\t// @[consts.scala:279:18]\n wire [2:0] p_uop_1_iq_type = 3'h0;\t// @[consts.scala:269:19]\n wire [2:0] p_uop_1_ctrl_op2_sel = 3'h0;\t// @[consts.scala:269:19]\n wire [2:0] p_uop_1_ctrl_imm_sel = 3'h0;\t// @[consts.scala:269:19]\n wire [2:0] p_uop_1_ctrl_csr_cmd = 3'h0;\t// @[consts.scala:269:19]\n wire [2:0] p_uop_cs_1_op2_sel = 3'h0;\t// @[consts.scala:279:18]\n wire [2:0] p_uop_cs_1_imm_sel = 3'h0;\t// @[consts.scala:279:18]\n wire [2:0] p_uop_cs_1_csr_cmd = 3'h0;\t// @[consts.scala:279:18]\n wire [2:0] p_uop_2_iq_type = 3'h0;\t// @[consts.scala:269:19]\n wire [2:0] p_uop_2_ctrl_op2_sel = 3'h0;\t// @[consts.scala:269:19]\n wire [2:0] p_uop_2_ctrl_imm_sel = 3'h0;\t// @[consts.scala:269:19]\n wire [2:0] p_uop_2_ctrl_csr_cmd = 3'h0;\t// @[consts.scala:269:19]\n wire [2:0] p_uop_cs_2_op2_sel = 3'h0;\t// @[consts.scala:279:18]\n wire [2:0] p_uop_cs_2_imm_sel = 3'h0;\t// @[consts.scala:279:18]\n wire [2:0] p_uop_cs_2_csr_cmd = 3'h0;\t// @[consts.scala:279:18]\n wire [2:0] fast_wakeup_bits_fflags_bits_uop_iq_type = 3'h0;\t// @[core.scala:814:29]\n wire [2:0] fast_wakeup_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0;\t// @[core.scala:814:29]\n wire [2:0] fast_wakeup_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0;\t// @[core.scala:814:29]\n wire [2:0] fast_wakeup_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0;\t// @[core.scala:814:29]\n wire [2:0] slow_wakeup_bits_fflags_bits_uop_iq_type = 3'h0;\t// @[core.scala:815:29]\n wire [2:0] slow_wakeup_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0;\t// @[core.scala:815:29]\n wire [2:0] slow_wakeup_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0;\t// @[core.scala:815:29]\n wire [2:0] slow_wakeup_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0;\t// @[core.scala:815:29]\n wire [2:0] fast_wakeup_1_bits_fflags_bits_uop_iq_type = 3'h0;\t// @[core.scala:814:29]\n wire [2:0] fast_wakeup_1_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0;\t// @[core.scala:814:29]\n wire [2:0] fast_wakeup_1_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0;\t// @[core.scala:814:29]\n wire [2:0] fast_wakeup_1_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0;\t// @[core.scala:814:29]\n wire [2:0] slow_wakeup_1_bits_fflags_bits_uop_iq_type = 3'h0;\t// @[core.scala:815:29]\n wire [2:0] slow_wakeup_1_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0;\t// @[core.scala:815:29]\n wire [2:0] slow_wakeup_1_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0;\t// @[core.scala:815:29]\n wire [2:0] slow_wakeup_1_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0;\t// @[core.scala:815:29]\n wire [2:0] fast_wakeup_2_bits_fflags_bits_uop_iq_type = 3'h0;\t// @[core.scala:814:29]\n wire [2:0] fast_wakeup_2_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0;\t// @[core.scala:814:29]\n wire [2:0] fast_wakeup_2_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0;\t// @[core.scala:814:29]\n wire [2:0] fast_wakeup_2_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0;\t// @[core.scala:814:29]\n wire [2:0] slow_wakeup_2_bits_fflags_bits_uop_iq_type = 3'h0;\t// @[core.scala:815:29]\n wire [2:0] slow_wakeup_2_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0;\t// @[core.scala:815:29]\n wire [2:0] slow_wakeup_2_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0;\t// @[core.scala:815:29]\n wire [2:0] slow_wakeup_2_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0;\t// @[core.scala:815:29]\n wire [2:0] coreMonitorBundle_priv_mode = 3'h0;\t// @[core.scala:1405:31]\n wire [9:0] io_ifu_fetchpacket_bits_uops_0_bits_fu_code = 10'h0;\t// @[core.scala:51:7]\n wire [9:0] io_ifu_fetchpacket_bits_uops_1_bits_fu_code = 10'h0;\t// @[core.scala:51:7]\n wire [9:0] io_ifu_fetchpacket_bits_uops_2_bits_fu_code = 10'h0;\t// @[core.scala:51:7]\n wire [9:0] io_lsu_exe_0_req_bits_fflags_bits_uop_fu_code = 10'h0;\t// @[core.scala:51:7]\n wire [9:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_fu_code = 10'h0;\t// @[core.scala:51:7]\n wire [9:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_fu_code = 10'h0;\t// @[core.scala:51:7]\n wire [9:0] int_iss_wakeups_1_bits_fflags_bits_uop_fu_code = 10'h0;\t// @[core.scala:147:30]\n wire [9:0] int_iss_wakeups_2_bits_fflags_bits_uop_fu_code = 10'h0;\t// @[core.scala:147:30]\n wire [9:0] int_iss_wakeups_3_bits_fflags_bits_uop_fu_code = 10'h0;\t// @[core.scala:147:30]\n wire [9:0] int_iss_wakeups_4_bits_fflags_bits_uop_fu_code = 10'h0;\t// @[core.scala:147:30]\n wire [9:0] int_iss_wakeups_5_bits_fflags_bits_uop_fu_code = 10'h0;\t// @[core.scala:147:30]\n wire [9:0] int_iss_wakeups_6_bits_fflags_bits_uop_fu_code = 10'h0;\t// @[core.scala:147:30]\n wire [9:0] int_ren_wakeups_1_bits_fflags_bits_uop_fu_code = 10'h0;\t// @[core.scala:148:30]\n wire [9:0] int_ren_wakeups_2_bits_fflags_bits_uop_fu_code = 10'h0;\t// @[core.scala:148:30]\n wire [9:0] int_ren_wakeups_3_bits_fflags_bits_uop_fu_code = 10'h0;\t// @[core.scala:148:30]\n wire [9:0] int_ren_wakeups_4_bits_fflags_bits_uop_fu_code = 10'h0;\t// @[core.scala:148:30]\n wire [9:0] int_ren_wakeups_5_bits_fflags_bits_uop_fu_code = 10'h0;\t// @[core.scala:148:30]\n wire [9:0] int_ren_wakeups_6_bits_fflags_bits_uop_fu_code = 10'h0;\t// @[core.scala:148:30]\n wire [9:0] pred_wakeup_bits_fflags_bits_uop_fu_code = 10'h0;\t// @[core.scala:149:26]\n wire [9:0] bypasses_0_bits_fflags_bits_uop_fu_code = 10'h0;\t// @[core.scala:174:24]\n wire [9:0] bypasses_1_bits_fflags_bits_uop_fu_code = 10'h0;\t// @[core.scala:174:24]\n wire [9:0] bypasses_2_bits_fflags_bits_uop_fu_code = 10'h0;\t// @[core.scala:174:24]\n wire [9:0] bypasses_3_bits_fflags_bits_uop_fu_code = 10'h0;\t// @[core.scala:174:24]\n wire [9:0] bypasses_4_bits_fflags_bits_uop_fu_code = 10'h0;\t// @[core.scala:174:24]\n wire [9:0] pred_bypasses_0_bits_fflags_bits_uop_fu_code = 10'h0;\t// @[core.scala:175:27]\n wire [9:0] p_uop_fu_code = 10'h0;\t// @[consts.scala:269:19]\n wire [9:0] p_uop_1_fu_code = 10'h0;\t// @[consts.scala:269:19]\n wire [9:0] p_uop_2_fu_code = 10'h0;\t// @[consts.scala:269:19]\n wire [9:0] fast_wakeup_bits_fflags_bits_uop_fu_code = 10'h0;\t// @[core.scala:814:29]\n wire [9:0] slow_wakeup_bits_fflags_bits_uop_fu_code = 10'h0;\t// @[core.scala:815:29]\n wire [9:0] fast_wakeup_1_bits_fflags_bits_uop_fu_code = 10'h0;\t// @[core.scala:814:29]\n wire [9:0] slow_wakeup_1_bits_fflags_bits_uop_fu_code = 10'h0;\t// @[core.scala:815:29]\n wire [9:0] fast_wakeup_2_bits_fflags_bits_uop_fu_code = 10'h0;\t// @[core.scala:814:29]\n wire [9:0] slow_wakeup_2_bits_fflags_bits_uop_fu_code = 10'h0;\t// @[core.scala:815:29]\n wire [3:0] io_ifu_fetchpacket_bits_uops_0_bits_ctrl_br_type = 4'h0;\t// @[core.scala:51:7]\n wire [3:0] io_ifu_fetchpacket_bits_uops_0_bits_br_tag = 4'h0;\t// @[core.scala:51:7]\n wire [3:0] io_ifu_fetchpacket_bits_uops_1_bits_ctrl_br_type = 4'h0;\t// @[core.scala:51:7]\n wire [3:0] io_ifu_fetchpacket_bits_uops_1_bits_br_tag = 4'h0;\t// @[core.scala:51:7]\n wire [3:0] io_ifu_fetchpacket_bits_uops_2_bits_ctrl_br_type = 4'h0;\t// @[core.scala:51:7]\n wire [3:0] io_ifu_fetchpacket_bits_uops_2_bits_br_tag = 4'h0;\t// @[core.scala:51:7]\n wire [3:0] io_ptw_hgatp_mode = 4'h0;\t// @[core.scala:51:7]\n wire [3:0] io_ptw_vsatp_mode = 4'h0;\t// @[core.scala:51:7]\n wire [3:0] io_lsu_exe_0_req_bits_fflags_bits_uop_ctrl_br_type = 4'h0;\t// @[core.scala:51:7]\n wire [3:0] io_lsu_exe_0_req_bits_fflags_bits_uop_br_tag = 4'h0;\t// @[core.scala:51:7]\n wire [3:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_ctrl_br_type = 4'h0;\t// @[core.scala:51:7]\n wire [3:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_br_tag = 4'h0;\t// @[core.scala:51:7]\n wire [3:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_ctrl_br_type = 4'h0;\t// @[core.scala:51:7]\n wire [3:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_br_tag = 4'h0;\t// @[core.scala:51:7]\n wire [3:0] io_ptw_tlb_hgatp_mode = 4'h0;\t// @[core.scala:51:7]\n wire [3:0] io_ptw_tlb_vsatp_mode = 4'h0;\t// @[core.scala:51:7]\n wire [3:0] int_iss_wakeups_1_bits_fflags_bits_uop_ctrl_br_type = 4'h0;\t// @[core.scala:147:30]\n wire [3:0] int_iss_wakeups_1_bits_fflags_bits_uop_br_tag = 4'h0;\t// @[core.scala:147:30]\n wire [3:0] int_iss_wakeups_2_bits_fflags_bits_uop_ctrl_br_type = 4'h0;\t// @[core.scala:147:30]\n wire [3:0] int_iss_wakeups_2_bits_fflags_bits_uop_br_tag = 4'h0;\t// @[core.scala:147:30]\n wire [3:0] int_iss_wakeups_3_bits_fflags_bits_uop_ctrl_br_type = 4'h0;\t// @[core.scala:147:30]\n wire [3:0] int_iss_wakeups_3_bits_fflags_bits_uop_br_tag = 4'h0;\t// @[core.scala:147:30]\n wire [3:0] int_iss_wakeups_4_bits_fflags_bits_uop_ctrl_br_type = 4'h0;\t// @[core.scala:147:30]\n wire [3:0] int_iss_wakeups_4_bits_fflags_bits_uop_br_tag = 4'h0;\t// @[core.scala:147:30]\n wire [3:0] int_iss_wakeups_5_bits_fflags_bits_uop_ctrl_br_type = 4'h0;\t// @[core.scala:147:30]\n wire [3:0] int_iss_wakeups_5_bits_fflags_bits_uop_br_tag = 4'h0;\t// @[core.scala:147:30]\n wire [3:0] int_iss_wakeups_6_bits_fflags_bits_uop_ctrl_br_type = 4'h0;\t// @[core.scala:147:30]\n wire [3:0] int_iss_wakeups_6_bits_fflags_bits_uop_br_tag = 4'h0;\t// @[core.scala:147:30]\n wire [3:0] int_ren_wakeups_1_bits_fflags_bits_uop_ctrl_br_type = 4'h0;\t// @[core.scala:148:30]\n wire [3:0] int_ren_wakeups_1_bits_fflags_bits_uop_br_tag = 4'h0;\t// @[core.scala:148:30]\n wire [3:0] int_ren_wakeups_2_bits_fflags_bits_uop_ctrl_br_type = 4'h0;\t// @[core.scala:148:30]\n wire [3:0] int_ren_wakeups_2_bits_fflags_bits_uop_br_tag = 4'h0;\t// @[core.scala:148:30]\n wire [3:0] int_ren_wakeups_3_bits_fflags_bits_uop_ctrl_br_type = 4'h0;\t// @[core.scala:148:30]\n wire [3:0] int_ren_wakeups_3_bits_fflags_bits_uop_br_tag = 4'h0;\t// @[core.scala:148:30]\n wire [3:0] int_ren_wakeups_4_bits_fflags_bits_uop_ctrl_br_type = 4'h0;\t// @[core.scala:148:30]\n wire [3:0] int_ren_wakeups_4_bits_fflags_bits_uop_br_tag = 4'h0;\t// @[core.scala:148:30]\n wire [3:0] int_ren_wakeups_5_bits_fflags_bits_uop_ctrl_br_type = 4'h0;\t// @[core.scala:148:30]\n wire [3:0] int_ren_wakeups_5_bits_fflags_bits_uop_br_tag = 4'h0;\t// @[core.scala:148:30]\n wire [3:0] int_ren_wakeups_6_bits_fflags_bits_uop_ctrl_br_type = 4'h0;\t// @[core.scala:148:30]\n wire [3:0] int_ren_wakeups_6_bits_fflags_bits_uop_br_tag = 4'h0;\t// @[core.scala:148:30]\n wire [3:0] pred_wakeup_bits_fflags_bits_uop_ctrl_br_type = 4'h0;\t// @[core.scala:149:26]\n wire [3:0] pred_wakeup_bits_fflags_bits_uop_br_tag = 4'h0;\t// @[core.scala:149:26]\n wire [3:0] dec_uops_0_ctrl_br_type = 4'h0;\t// @[core.scala:158:24]\n wire [3:0] dec_uops_1_ctrl_br_type = 4'h0;\t// @[core.scala:158:24]\n wire [3:0] dec_uops_2_ctrl_br_type = 4'h0;\t// @[core.scala:158:24]\n wire [3:0] bypasses_0_bits_fflags_bits_uop_ctrl_br_type = 4'h0;\t// @[core.scala:174:24]\n wire [3:0] bypasses_0_bits_fflags_bits_uop_br_tag = 4'h0;\t// @[core.scala:174:24]\n wire [3:0] bypasses_1_bits_fflags_bits_uop_ctrl_br_type = 4'h0;\t// @[core.scala:174:24]\n wire [3:0] bypasses_1_bits_fflags_bits_uop_br_tag = 4'h0;\t// @[core.scala:174:24]\n wire [3:0] bypasses_2_bits_fflags_bits_uop_ctrl_br_type = 4'h0;\t// @[core.scala:174:24]\n wire [3:0] bypasses_2_bits_fflags_bits_uop_br_tag = 4'h0;\t// @[core.scala:174:24]\n wire [3:0] bypasses_3_bits_fflags_bits_uop_ctrl_br_type = 4'h0;\t// @[core.scala:174:24]\n wire [3:0] bypasses_3_bits_fflags_bits_uop_br_tag = 4'h0;\t// @[core.scala:174:24]\n wire [3:0] bypasses_4_bits_fflags_bits_uop_ctrl_br_type = 4'h0;\t// @[core.scala:174:24]\n wire [3:0] bypasses_4_bits_fflags_bits_uop_br_tag = 4'h0;\t// @[core.scala:174:24]\n wire [3:0] pred_bypasses_0_bits_fflags_bits_uop_ctrl_br_type = 4'h0;\t// @[core.scala:175:27]\n wire [3:0] pred_bypasses_0_bits_fflags_bits_uop_br_tag = 4'h0;\t// @[core.scala:175:27]\n wire [3:0] p_uop_ctrl_br_type = 4'h0;\t// @[consts.scala:269:19]\n wire [3:0] p_uop_br_tag = 4'h0;\t// @[consts.scala:269:19]\n wire [3:0] p_uop_cs_br_type = 4'h0;\t// @[consts.scala:279:18]\n wire [3:0] p_uop_1_ctrl_br_type = 4'h0;\t// @[consts.scala:269:19]\n wire [3:0] p_uop_1_br_tag = 4'h0;\t// @[consts.scala:269:19]\n wire [3:0] p_uop_cs_1_br_type = 4'h0;\t// @[consts.scala:279:18]\n wire [3:0] p_uop_2_ctrl_br_type = 4'h0;\t// @[consts.scala:269:19]\n wire [3:0] p_uop_2_br_tag = 4'h0;\t// @[consts.scala:269:19]\n wire [3:0] p_uop_cs_2_br_type = 4'h0;\t// @[consts.scala:279:18]\n wire [3:0] fast_wakeup_bits_fflags_bits_uop_ctrl_br_type = 4'h0;\t// @[core.scala:814:29]\n wire [3:0] fast_wakeup_bits_fflags_bits_uop_br_tag = 4'h0;\t// @[core.scala:814:29]\n wire [3:0] slow_wakeup_bits_fflags_bits_uop_ctrl_br_type = 4'h0;\t// @[core.scala:815:29]\n wire [3:0] slow_wakeup_bits_fflags_bits_uop_br_tag = 4'h0;\t// @[core.scala:815:29]\n wire [3:0] fast_wakeup_1_bits_fflags_bits_uop_ctrl_br_type = 4'h0;\t// @[core.scala:814:29]\n wire [3:0] fast_wakeup_1_bits_fflags_bits_uop_br_tag = 4'h0;\t// @[core.scala:814:29]\n wire [3:0] slow_wakeup_1_bits_fflags_bits_uop_ctrl_br_type = 4'h0;\t// @[core.scala:815:29]\n wire [3:0] slow_wakeup_1_bits_fflags_bits_uop_br_tag = 4'h0;\t// @[core.scala:815:29]\n wire [3:0] fast_wakeup_2_bits_fflags_bits_uop_ctrl_br_type = 4'h0;\t// @[core.scala:814:29]\n wire [3:0] fast_wakeup_2_bits_fflags_bits_uop_br_tag = 4'h0;\t// @[core.scala:814:29]\n wire [3:0] slow_wakeup_2_bits_fflags_bits_uop_ctrl_br_type = 4'h0;\t// @[core.scala:815:29]\n wire [3:0] slow_wakeup_2_bits_fflags_bits_uop_br_tag = 4'h0;\t// @[core.scala:815:29]\n wire [1:0] io_ifu_fetchpacket_bits_uops_0_bits_ctrl_op1_sel = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_ifu_fetchpacket_bits_uops_0_bits_iw_state = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_ifu_fetchpacket_bits_uops_0_bits_rxq_idx = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_ifu_fetchpacket_bits_uops_0_bits_mem_size = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_ifu_fetchpacket_bits_uops_0_bits_dst_rtype = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_ifu_fetchpacket_bits_uops_0_bits_lrs1_rtype = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_ifu_fetchpacket_bits_uops_0_bits_lrs2_rtype = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_ifu_fetchpacket_bits_uops_0_bits_debug_tsrc = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_ifu_fetchpacket_bits_uops_1_bits_ctrl_op1_sel = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_ifu_fetchpacket_bits_uops_1_bits_iw_state = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_ifu_fetchpacket_bits_uops_1_bits_rxq_idx = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_ifu_fetchpacket_bits_uops_1_bits_mem_size = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_ifu_fetchpacket_bits_uops_1_bits_dst_rtype = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_ifu_fetchpacket_bits_uops_1_bits_lrs1_rtype = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_ifu_fetchpacket_bits_uops_1_bits_lrs2_rtype = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_ifu_fetchpacket_bits_uops_1_bits_debug_tsrc = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_ifu_fetchpacket_bits_uops_2_bits_ctrl_op1_sel = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_ifu_fetchpacket_bits_uops_2_bits_iw_state = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_ifu_fetchpacket_bits_uops_2_bits_rxq_idx = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_ifu_fetchpacket_bits_uops_2_bits_mem_size = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_ifu_fetchpacket_bits_uops_2_bits_dst_rtype = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_ifu_fetchpacket_bits_uops_2_bits_lrs1_rtype = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_ifu_fetchpacket_bits_uops_2_bits_lrs2_rtype = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_ifu_fetchpacket_bits_uops_2_bits_debug_tsrc = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_ifu_status_xs = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_ifu_status_vs = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_ptw_status_xs = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_ptw_status_vs = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_ptw_hstatus_vsxl = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_ptw_hstatus_zero3 = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_ptw_hstatus_zero2 = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_ptw_gstatus_dprv = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_ptw_gstatus_prv = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_ptw_gstatus_sxl = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_ptw_gstatus_uxl = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_ptw_gstatus_xs = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_ptw_gstatus_fs = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_ptw_gstatus_mpp = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_ptw_gstatus_vs = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_ptw_pmp_0_cfg_res = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_ptw_pmp_1_cfg_res = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_ptw_pmp_2_cfg_res = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_ptw_pmp_3_cfg_res = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_ptw_pmp_4_cfg_res = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_ptw_pmp_5_cfg_res = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_ptw_pmp_6_cfg_res = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_ptw_pmp_7_cfg_res = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_rocc_cmd_bits_status_dprv = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_rocc_cmd_bits_status_prv = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_rocc_cmd_bits_status_sxl = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_rocc_cmd_bits_status_uxl = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_rocc_cmd_bits_status_xs = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_rocc_cmd_bits_status_fs = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_rocc_cmd_bits_status_mpp = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_rocc_cmd_bits_status_vs = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_rocc_mem_req_bits_size = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_rocc_mem_req_bits_dprv = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_rocc_mem_resp_bits_size = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_rocc_mem_resp_bits_dprv = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_exe_0_req_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_exe_0_req_bits_fflags_bits_uop_iw_state = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_exe_0_req_bits_fflags_bits_uop_rxq_idx = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_exe_0_req_bits_fflags_bits_uop_mem_size = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_exe_0_req_bits_fflags_bits_uop_dst_rtype = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_exe_0_req_bits_fflags_bits_uop_lrs1_rtype = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_exe_0_req_bits_fflags_bits_uop_lrs2_rtype = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_exe_0_req_bits_fflags_bits_uop_debug_fsrc = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_exe_0_req_bits_fflags_bits_uop_debug_tsrc = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_iw_state = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_rxq_idx = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_mem_size = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_dst_rtype = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_lrs1_rtype = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_lrs2_rtype = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_debug_fsrc = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_debug_tsrc = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_iw_state = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_rxq_idx = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_mem_size = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_dst_rtype = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_lrs1_rtype = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_lrs2_rtype = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_debug_fsrc = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_debug_tsrc = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_ptw_tlb_status_xs = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_ptw_tlb_status_vs = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_ptw_tlb_hstatus_vsxl = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_ptw_tlb_hstatus_zero3 = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_ptw_tlb_hstatus_zero2 = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_ptw_tlb_gstatus_dprv = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_ptw_tlb_gstatus_prv = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_ptw_tlb_gstatus_sxl = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_ptw_tlb_gstatus_uxl = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_ptw_tlb_gstatus_xs = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_ptw_tlb_gstatus_fs = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_ptw_tlb_gstatus_mpp = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_ptw_tlb_gstatus_vs = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_ptw_tlb_pmp_0_cfg_res = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_ptw_tlb_pmp_1_cfg_res = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_ptw_tlb_pmp_2_cfg_res = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_ptw_tlb_pmp_3_cfg_res = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_ptw_tlb_pmp_4_cfg_res = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_ptw_tlb_pmp_5_cfg_res = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_ptw_tlb_pmp_6_cfg_res = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] io_ptw_tlb_pmp_7_cfg_res = 2'h0;\t// @[core.scala:51:7]\n wire [1:0] int_iss_wakeups_1_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_1_bits_fflags_bits_uop_iw_state = 2'h0;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_1_bits_fflags_bits_uop_rxq_idx = 2'h0;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_1_bits_fflags_bits_uop_mem_size = 2'h0;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_1_bits_fflags_bits_uop_dst_rtype = 2'h0;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_1_bits_fflags_bits_uop_lrs1_rtype = 2'h0;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_1_bits_fflags_bits_uop_lrs2_rtype = 2'h0;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_1_bits_fflags_bits_uop_debug_fsrc = 2'h0;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_1_bits_fflags_bits_uop_debug_tsrc = 2'h0;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_2_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_2_bits_fflags_bits_uop_iw_state = 2'h0;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_2_bits_fflags_bits_uop_rxq_idx = 2'h0;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_2_bits_fflags_bits_uop_mem_size = 2'h0;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_2_bits_fflags_bits_uop_dst_rtype = 2'h0;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_2_bits_fflags_bits_uop_lrs1_rtype = 2'h0;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_2_bits_fflags_bits_uop_lrs2_rtype = 2'h0;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_2_bits_fflags_bits_uop_debug_fsrc = 2'h0;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_2_bits_fflags_bits_uop_debug_tsrc = 2'h0;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_3_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_3_bits_fflags_bits_uop_iw_state = 2'h0;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_3_bits_fflags_bits_uop_rxq_idx = 2'h0;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_3_bits_fflags_bits_uop_mem_size = 2'h0;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_3_bits_fflags_bits_uop_dst_rtype = 2'h0;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_3_bits_fflags_bits_uop_lrs1_rtype = 2'h0;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_3_bits_fflags_bits_uop_lrs2_rtype = 2'h0;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_3_bits_fflags_bits_uop_debug_fsrc = 2'h0;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_3_bits_fflags_bits_uop_debug_tsrc = 2'h0;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_4_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_4_bits_fflags_bits_uop_iw_state = 2'h0;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_4_bits_fflags_bits_uop_rxq_idx = 2'h0;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_4_bits_fflags_bits_uop_mem_size = 2'h0;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_4_bits_fflags_bits_uop_dst_rtype = 2'h0;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_4_bits_fflags_bits_uop_lrs1_rtype = 2'h0;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_4_bits_fflags_bits_uop_lrs2_rtype = 2'h0;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_4_bits_fflags_bits_uop_debug_fsrc = 2'h0;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_4_bits_fflags_bits_uop_debug_tsrc = 2'h0;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_5_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_5_bits_fflags_bits_uop_iw_state = 2'h0;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_5_bits_fflags_bits_uop_rxq_idx = 2'h0;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_5_bits_fflags_bits_uop_mem_size = 2'h0;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_5_bits_fflags_bits_uop_dst_rtype = 2'h0;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_5_bits_fflags_bits_uop_lrs1_rtype = 2'h0;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_5_bits_fflags_bits_uop_lrs2_rtype = 2'h0;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_5_bits_fflags_bits_uop_debug_fsrc = 2'h0;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_5_bits_fflags_bits_uop_debug_tsrc = 2'h0;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_6_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_6_bits_fflags_bits_uop_iw_state = 2'h0;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_6_bits_fflags_bits_uop_rxq_idx = 2'h0;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_6_bits_fflags_bits_uop_mem_size = 2'h0;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_6_bits_fflags_bits_uop_dst_rtype = 2'h0;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_6_bits_fflags_bits_uop_lrs1_rtype = 2'h0;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_6_bits_fflags_bits_uop_lrs2_rtype = 2'h0;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_6_bits_fflags_bits_uop_debug_fsrc = 2'h0;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_6_bits_fflags_bits_uop_debug_tsrc = 2'h0;\t// @[core.scala:147:30]\n wire [1:0] int_ren_wakeups_1_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_1_bits_fflags_bits_uop_iw_state = 2'h0;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_1_bits_fflags_bits_uop_rxq_idx = 2'h0;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_1_bits_fflags_bits_uop_mem_size = 2'h0;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_1_bits_fflags_bits_uop_dst_rtype = 2'h0;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_1_bits_fflags_bits_uop_lrs1_rtype = 2'h0;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_1_bits_fflags_bits_uop_lrs2_rtype = 2'h0;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_1_bits_fflags_bits_uop_debug_fsrc = 2'h0;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_1_bits_fflags_bits_uop_debug_tsrc = 2'h0;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_2_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_2_bits_fflags_bits_uop_iw_state = 2'h0;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_2_bits_fflags_bits_uop_rxq_idx = 2'h0;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_2_bits_fflags_bits_uop_mem_size = 2'h0;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_2_bits_fflags_bits_uop_dst_rtype = 2'h0;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_2_bits_fflags_bits_uop_lrs1_rtype = 2'h0;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_2_bits_fflags_bits_uop_lrs2_rtype = 2'h0;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_2_bits_fflags_bits_uop_debug_fsrc = 2'h0;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_2_bits_fflags_bits_uop_debug_tsrc = 2'h0;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_3_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_3_bits_fflags_bits_uop_iw_state = 2'h0;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_3_bits_fflags_bits_uop_rxq_idx = 2'h0;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_3_bits_fflags_bits_uop_mem_size = 2'h0;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_3_bits_fflags_bits_uop_dst_rtype = 2'h0;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_3_bits_fflags_bits_uop_lrs1_rtype = 2'h0;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_3_bits_fflags_bits_uop_lrs2_rtype = 2'h0;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_3_bits_fflags_bits_uop_debug_fsrc = 2'h0;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_3_bits_fflags_bits_uop_debug_tsrc = 2'h0;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_4_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_4_bits_fflags_bits_uop_iw_state = 2'h0;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_4_bits_fflags_bits_uop_rxq_idx = 2'h0;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_4_bits_fflags_bits_uop_mem_size = 2'h0;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_4_bits_fflags_bits_uop_dst_rtype = 2'h0;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_4_bits_fflags_bits_uop_lrs1_rtype = 2'h0;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_4_bits_fflags_bits_uop_lrs2_rtype = 2'h0;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_4_bits_fflags_bits_uop_debug_fsrc = 2'h0;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_4_bits_fflags_bits_uop_debug_tsrc = 2'h0;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_5_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_5_bits_fflags_bits_uop_iw_state = 2'h0;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_5_bits_fflags_bits_uop_rxq_idx = 2'h0;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_5_bits_fflags_bits_uop_mem_size = 2'h0;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_5_bits_fflags_bits_uop_dst_rtype = 2'h0;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_5_bits_fflags_bits_uop_lrs1_rtype = 2'h0;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_5_bits_fflags_bits_uop_lrs2_rtype = 2'h0;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_5_bits_fflags_bits_uop_debug_fsrc = 2'h0;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_5_bits_fflags_bits_uop_debug_tsrc = 2'h0;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_6_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_6_bits_fflags_bits_uop_iw_state = 2'h0;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_6_bits_fflags_bits_uop_rxq_idx = 2'h0;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_6_bits_fflags_bits_uop_mem_size = 2'h0;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_6_bits_fflags_bits_uop_dst_rtype = 2'h0;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_6_bits_fflags_bits_uop_lrs1_rtype = 2'h0;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_6_bits_fflags_bits_uop_lrs2_rtype = 2'h0;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_6_bits_fflags_bits_uop_debug_fsrc = 2'h0;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_6_bits_fflags_bits_uop_debug_tsrc = 2'h0;\t// @[core.scala:148:30]\n wire [1:0] pred_wakeup_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0;\t// @[core.scala:149:26]\n wire [1:0] pred_wakeup_bits_fflags_bits_uop_iw_state = 2'h0;\t// @[core.scala:149:26]\n wire [1:0] pred_wakeup_bits_fflags_bits_uop_rxq_idx = 2'h0;\t// @[core.scala:149:26]\n wire [1:0] pred_wakeup_bits_fflags_bits_uop_mem_size = 2'h0;\t// @[core.scala:149:26]\n wire [1:0] pred_wakeup_bits_fflags_bits_uop_dst_rtype = 2'h0;\t// @[core.scala:149:26]\n wire [1:0] pred_wakeup_bits_fflags_bits_uop_lrs1_rtype = 2'h0;\t// @[core.scala:149:26]\n wire [1:0] pred_wakeup_bits_fflags_bits_uop_lrs2_rtype = 2'h0;\t// @[core.scala:149:26]\n wire [1:0] pred_wakeup_bits_fflags_bits_uop_debug_fsrc = 2'h0;\t// @[core.scala:149:26]\n wire [1:0] pred_wakeup_bits_fflags_bits_uop_debug_tsrc = 2'h0;\t// @[core.scala:149:26]\n wire [1:0] dec_uops_0_ctrl_op1_sel = 2'h0;\t// @[core.scala:158:24]\n wire [1:0] dec_uops_0_iw_state = 2'h0;\t// @[core.scala:158:24]\n wire [1:0] dec_uops_0_rxq_idx = 2'h0;\t// @[core.scala:158:24]\n wire [1:0] dec_uops_0_debug_tsrc = 2'h0;\t// @[core.scala:158:24]\n wire [1:0] dec_uops_1_ctrl_op1_sel = 2'h0;\t// @[core.scala:158:24]\n wire [1:0] dec_uops_1_iw_state = 2'h0;\t// @[core.scala:158:24]\n wire [1:0] dec_uops_1_rxq_idx = 2'h0;\t// @[core.scala:158:24]\n wire [1:0] dec_uops_1_debug_tsrc = 2'h0;\t// @[core.scala:158:24]\n wire [1:0] dec_uops_2_ctrl_op1_sel = 2'h0;\t// @[core.scala:158:24]\n wire [1:0] dec_uops_2_iw_state = 2'h0;\t// @[core.scala:158:24]\n wire [1:0] dec_uops_2_rxq_idx = 2'h0;\t// @[core.scala:158:24]\n wire [1:0] dec_uops_2_debug_tsrc = 2'h0;\t// @[core.scala:158:24]\n wire [1:0] bypasses_0_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0;\t// @[core.scala:174:24]\n wire [1:0] bypasses_0_bits_fflags_bits_uop_iw_state = 2'h0;\t// @[core.scala:174:24]\n wire [1:0] bypasses_0_bits_fflags_bits_uop_rxq_idx = 2'h0;\t// @[core.scala:174:24]\n wire [1:0] bypasses_0_bits_fflags_bits_uop_mem_size = 2'h0;\t// @[core.scala:174:24]\n wire [1:0] bypasses_0_bits_fflags_bits_uop_dst_rtype = 2'h0;\t// @[core.scala:174:24]\n wire [1:0] bypasses_0_bits_fflags_bits_uop_lrs1_rtype = 2'h0;\t// @[core.scala:174:24]\n wire [1:0] bypasses_0_bits_fflags_bits_uop_lrs2_rtype = 2'h0;\t// @[core.scala:174:24]\n wire [1:0] bypasses_0_bits_fflags_bits_uop_debug_fsrc = 2'h0;\t// @[core.scala:174:24]\n wire [1:0] bypasses_0_bits_fflags_bits_uop_debug_tsrc = 2'h0;\t// @[core.scala:174:24]\n wire [1:0] bypasses_1_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0;\t// @[core.scala:174:24]\n wire [1:0] bypasses_1_bits_fflags_bits_uop_iw_state = 2'h0;\t// @[core.scala:174:24]\n wire [1:0] bypasses_1_bits_fflags_bits_uop_rxq_idx = 2'h0;\t// @[core.scala:174:24]\n wire [1:0] bypasses_1_bits_fflags_bits_uop_mem_size = 2'h0;\t// @[core.scala:174:24]\n wire [1:0] bypasses_1_bits_fflags_bits_uop_dst_rtype = 2'h0;\t// @[core.scala:174:24]\n wire [1:0] bypasses_1_bits_fflags_bits_uop_lrs1_rtype = 2'h0;\t// @[core.scala:174:24]\n wire [1:0] bypasses_1_bits_fflags_bits_uop_lrs2_rtype = 2'h0;\t// @[core.scala:174:24]\n wire [1:0] bypasses_1_bits_fflags_bits_uop_debug_fsrc = 2'h0;\t// @[core.scala:174:24]\n wire [1:0] bypasses_1_bits_fflags_bits_uop_debug_tsrc = 2'h0;\t// @[core.scala:174:24]\n wire [1:0] bypasses_2_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0;\t// @[core.scala:174:24]\n wire [1:0] bypasses_2_bits_fflags_bits_uop_iw_state = 2'h0;\t// @[core.scala:174:24]\n wire [1:0] bypasses_2_bits_fflags_bits_uop_rxq_idx = 2'h0;\t// @[core.scala:174:24]\n wire [1:0] bypasses_2_bits_fflags_bits_uop_mem_size = 2'h0;\t// @[core.scala:174:24]\n wire [1:0] bypasses_2_bits_fflags_bits_uop_dst_rtype = 2'h0;\t// @[core.scala:174:24]\n wire [1:0] bypasses_2_bits_fflags_bits_uop_lrs1_rtype = 2'h0;\t// @[core.scala:174:24]\n wire [1:0] bypasses_2_bits_fflags_bits_uop_lrs2_rtype = 2'h0;\t// @[core.scala:174:24]\n wire [1:0] bypasses_2_bits_fflags_bits_uop_debug_fsrc = 2'h0;\t// @[core.scala:174:24]\n wire [1:0] bypasses_2_bits_fflags_bits_uop_debug_tsrc = 2'h0;\t// @[core.scala:174:24]\n wire [1:0] bypasses_3_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0;\t// @[core.scala:174:24]\n wire [1:0] bypasses_3_bits_fflags_bits_uop_iw_state = 2'h0;\t// @[core.scala:174:24]\n wire [1:0] bypasses_3_bits_fflags_bits_uop_rxq_idx = 2'h0;\t// @[core.scala:174:24]\n wire [1:0] bypasses_3_bits_fflags_bits_uop_mem_size = 2'h0;\t// @[core.scala:174:24]\n wire [1:0] bypasses_3_bits_fflags_bits_uop_dst_rtype = 2'h0;\t// @[core.scala:174:24]\n wire [1:0] bypasses_3_bits_fflags_bits_uop_lrs1_rtype = 2'h0;\t// @[core.scala:174:24]\n wire [1:0] bypasses_3_bits_fflags_bits_uop_lrs2_rtype = 2'h0;\t// @[core.scala:174:24]\n wire [1:0] bypasses_3_bits_fflags_bits_uop_debug_fsrc = 2'h0;\t// @[core.scala:174:24]\n wire [1:0] bypasses_3_bits_fflags_bits_uop_debug_tsrc = 2'h0;\t// @[core.scala:174:24]\n wire [1:0] bypasses_4_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0;\t// @[core.scala:174:24]\n wire [1:0] bypasses_4_bits_fflags_bits_uop_iw_state = 2'h0;\t// @[core.scala:174:24]\n wire [1:0] bypasses_4_bits_fflags_bits_uop_rxq_idx = 2'h0;\t// @[core.scala:174:24]\n wire [1:0] bypasses_4_bits_fflags_bits_uop_mem_size = 2'h0;\t// @[core.scala:174:24]\n wire [1:0] bypasses_4_bits_fflags_bits_uop_dst_rtype = 2'h0;\t// @[core.scala:174:24]\n wire [1:0] bypasses_4_bits_fflags_bits_uop_lrs1_rtype = 2'h0;\t// @[core.scala:174:24]\n wire [1:0] bypasses_4_bits_fflags_bits_uop_lrs2_rtype = 2'h0;\t// @[core.scala:174:24]\n wire [1:0] bypasses_4_bits_fflags_bits_uop_debug_fsrc = 2'h0;\t// @[core.scala:174:24]\n wire [1:0] bypasses_4_bits_fflags_bits_uop_debug_tsrc = 2'h0;\t// @[core.scala:174:24]\n wire [1:0] pred_bypasses_0_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0;\t// @[core.scala:175:27]\n wire [1:0] pred_bypasses_0_bits_fflags_bits_uop_iw_state = 2'h0;\t// @[core.scala:175:27]\n wire [1:0] pred_bypasses_0_bits_fflags_bits_uop_rxq_idx = 2'h0;\t// @[core.scala:175:27]\n wire [1:0] pred_bypasses_0_bits_fflags_bits_uop_mem_size = 2'h0;\t// @[core.scala:175:27]\n wire [1:0] pred_bypasses_0_bits_fflags_bits_uop_dst_rtype = 2'h0;\t// @[core.scala:175:27]\n wire [1:0] pred_bypasses_0_bits_fflags_bits_uop_lrs1_rtype = 2'h0;\t// @[core.scala:175:27]\n wire [1:0] pred_bypasses_0_bits_fflags_bits_uop_lrs2_rtype = 2'h0;\t// @[core.scala:175:27]\n wire [1:0] pred_bypasses_0_bits_fflags_bits_uop_debug_fsrc = 2'h0;\t// @[core.scala:175:27]\n wire [1:0] pred_bypasses_0_bits_fflags_bits_uop_debug_tsrc = 2'h0;\t// @[core.scala:175:27]\n wire [1:0] p_uop_ctrl_op1_sel = 2'h0;\t// @[consts.scala:269:19]\n wire [1:0] p_uop_iw_state = 2'h0;\t// @[consts.scala:269:19]\n wire [1:0] p_uop_rxq_idx = 2'h0;\t// @[consts.scala:269:19]\n wire [1:0] p_uop_mem_size = 2'h0;\t// @[consts.scala:269:19]\n wire [1:0] p_uop_lrs1_rtype = 2'h0;\t// @[consts.scala:269:19]\n wire [1:0] p_uop_lrs2_rtype = 2'h0;\t// @[consts.scala:269:19]\n wire [1:0] p_uop_debug_fsrc = 2'h0;\t// @[consts.scala:269:19]\n wire [1:0] p_uop_debug_tsrc = 2'h0;\t// @[consts.scala:269:19]\n wire [1:0] p_uop_cs_op1_sel = 2'h0;\t// @[consts.scala:279:18]\n wire [1:0] p_uop_1_ctrl_op1_sel = 2'h0;\t// @[consts.scala:269:19]\n wire [1:0] p_uop_1_iw_state = 2'h0;\t// @[consts.scala:269:19]\n wire [1:0] p_uop_1_rxq_idx = 2'h0;\t// @[consts.scala:269:19]\n wire [1:0] p_uop_1_mem_size = 2'h0;\t// @[consts.scala:269:19]\n wire [1:0] p_uop_1_lrs1_rtype = 2'h0;\t// @[consts.scala:269:19]\n wire [1:0] p_uop_1_lrs2_rtype = 2'h0;\t// @[consts.scala:269:19]\n wire [1:0] p_uop_1_debug_fsrc = 2'h0;\t// @[consts.scala:269:19]\n wire [1:0] p_uop_1_debug_tsrc = 2'h0;\t// @[consts.scala:269:19]\n wire [1:0] p_uop_cs_1_op1_sel = 2'h0;\t// @[consts.scala:279:18]\n wire [1:0] p_uop_2_ctrl_op1_sel = 2'h0;\t// @[consts.scala:269:19]\n wire [1:0] p_uop_2_iw_state = 2'h0;\t// @[consts.scala:269:19]\n wire [1:0] p_uop_2_rxq_idx = 2'h0;\t// @[consts.scala:269:19]\n wire [1:0] p_uop_2_mem_size = 2'h0;\t// @[consts.scala:269:19]\n wire [1:0] p_uop_2_lrs1_rtype = 2'h0;\t// @[consts.scala:269:19]\n wire [1:0] p_uop_2_lrs2_rtype = 2'h0;\t// @[consts.scala:269:19]\n wire [1:0] p_uop_2_debug_fsrc = 2'h0;\t// @[consts.scala:269:19]\n wire [1:0] p_uop_2_debug_tsrc = 2'h0;\t// @[consts.scala:269:19]\n wire [1:0] p_uop_cs_2_op1_sel = 2'h0;\t// @[consts.scala:279:18]\n wire [1:0] fast_wakeup_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0;\t// @[core.scala:814:29]\n wire [1:0] fast_wakeup_bits_fflags_bits_uop_iw_state = 2'h0;\t// @[core.scala:814:29]\n wire [1:0] fast_wakeup_bits_fflags_bits_uop_rxq_idx = 2'h0;\t// @[core.scala:814:29]\n wire [1:0] fast_wakeup_bits_fflags_bits_uop_mem_size = 2'h0;\t// @[core.scala:814:29]\n wire [1:0] fast_wakeup_bits_fflags_bits_uop_dst_rtype = 2'h0;\t// @[core.scala:814:29]\n wire [1:0] fast_wakeup_bits_fflags_bits_uop_lrs1_rtype = 2'h0;\t// @[core.scala:814:29]\n wire [1:0] fast_wakeup_bits_fflags_bits_uop_lrs2_rtype = 2'h0;\t// @[core.scala:814:29]\n wire [1:0] fast_wakeup_bits_fflags_bits_uop_debug_fsrc = 2'h0;\t// @[core.scala:814:29]\n wire [1:0] fast_wakeup_bits_fflags_bits_uop_debug_tsrc = 2'h0;\t// @[core.scala:814:29]\n wire [1:0] slow_wakeup_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0;\t// @[core.scala:815:29]\n wire [1:0] slow_wakeup_bits_fflags_bits_uop_iw_state = 2'h0;\t// @[core.scala:815:29]\n wire [1:0] slow_wakeup_bits_fflags_bits_uop_rxq_idx = 2'h0;\t// @[core.scala:815:29]\n wire [1:0] slow_wakeup_bits_fflags_bits_uop_mem_size = 2'h0;\t// @[core.scala:815:29]\n wire [1:0] slow_wakeup_bits_fflags_bits_uop_dst_rtype = 2'h0;\t// @[core.scala:815:29]\n wire [1:0] slow_wakeup_bits_fflags_bits_uop_lrs1_rtype = 2'h0;\t// @[core.scala:815:29]\n wire [1:0] slow_wakeup_bits_fflags_bits_uop_lrs2_rtype = 2'h0;\t// @[core.scala:815:29]\n wire [1:0] slow_wakeup_bits_fflags_bits_uop_debug_fsrc = 2'h0;\t// @[core.scala:815:29]\n wire [1:0] slow_wakeup_bits_fflags_bits_uop_debug_tsrc = 2'h0;\t// @[core.scala:815:29]\n wire [1:0] fast_wakeup_1_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0;\t// @[core.scala:814:29]\n wire [1:0] fast_wakeup_1_bits_fflags_bits_uop_iw_state = 2'h0;\t// @[core.scala:814:29]\n wire [1:0] fast_wakeup_1_bits_fflags_bits_uop_rxq_idx = 2'h0;\t// @[core.scala:814:29]\n wire [1:0] fast_wakeup_1_bits_fflags_bits_uop_mem_size = 2'h0;\t// @[core.scala:814:29]\n wire [1:0] fast_wakeup_1_bits_fflags_bits_uop_dst_rtype = 2'h0;\t// @[core.scala:814:29]\n wire [1:0] fast_wakeup_1_bits_fflags_bits_uop_lrs1_rtype = 2'h0;\t// @[core.scala:814:29]\n wire [1:0] fast_wakeup_1_bits_fflags_bits_uop_lrs2_rtype = 2'h0;\t// @[core.scala:814:29]\n wire [1:0] fast_wakeup_1_bits_fflags_bits_uop_debug_fsrc = 2'h0;\t// @[core.scala:814:29]\n wire [1:0] fast_wakeup_1_bits_fflags_bits_uop_debug_tsrc = 2'h0;\t// @[core.scala:814:29]\n wire [1:0] slow_wakeup_1_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0;\t// @[core.scala:815:29]\n wire [1:0] slow_wakeup_1_bits_fflags_bits_uop_iw_state = 2'h0;\t// @[core.scala:815:29]\n wire [1:0] slow_wakeup_1_bits_fflags_bits_uop_rxq_idx = 2'h0;\t// @[core.scala:815:29]\n wire [1:0] slow_wakeup_1_bits_fflags_bits_uop_mem_size = 2'h0;\t// @[core.scala:815:29]\n wire [1:0] slow_wakeup_1_bits_fflags_bits_uop_dst_rtype = 2'h0;\t// @[core.scala:815:29]\n wire [1:0] slow_wakeup_1_bits_fflags_bits_uop_lrs1_rtype = 2'h0;\t// @[core.scala:815:29]\n wire [1:0] slow_wakeup_1_bits_fflags_bits_uop_lrs2_rtype = 2'h0;\t// @[core.scala:815:29]\n wire [1:0] slow_wakeup_1_bits_fflags_bits_uop_debug_fsrc = 2'h0;\t// @[core.scala:815:29]\n wire [1:0] slow_wakeup_1_bits_fflags_bits_uop_debug_tsrc = 2'h0;\t// @[core.scala:815:29]\n wire [1:0] fast_wakeup_2_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0;\t// @[core.scala:814:29]\n wire [1:0] fast_wakeup_2_bits_fflags_bits_uop_iw_state = 2'h0;\t// @[core.scala:814:29]\n wire [1:0] fast_wakeup_2_bits_fflags_bits_uop_rxq_idx = 2'h0;\t// @[core.scala:814:29]\n wire [1:0] fast_wakeup_2_bits_fflags_bits_uop_mem_size = 2'h0;\t// @[core.scala:814:29]\n wire [1:0] fast_wakeup_2_bits_fflags_bits_uop_dst_rtype = 2'h0;\t// @[core.scala:814:29]\n wire [1:0] fast_wakeup_2_bits_fflags_bits_uop_lrs1_rtype = 2'h0;\t// @[core.scala:814:29]\n wire [1:0] fast_wakeup_2_bits_fflags_bits_uop_lrs2_rtype = 2'h0;\t// @[core.scala:814:29]\n wire [1:0] fast_wakeup_2_bits_fflags_bits_uop_debug_fsrc = 2'h0;\t// @[core.scala:814:29]\n wire [1:0] fast_wakeup_2_bits_fflags_bits_uop_debug_tsrc = 2'h0;\t// @[core.scala:814:29]\n wire [1:0] slow_wakeup_2_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0;\t// @[core.scala:815:29]\n wire [1:0] slow_wakeup_2_bits_fflags_bits_uop_iw_state = 2'h0;\t// @[core.scala:815:29]\n wire [1:0] slow_wakeup_2_bits_fflags_bits_uop_rxq_idx = 2'h0;\t// @[core.scala:815:29]\n wire [1:0] slow_wakeup_2_bits_fflags_bits_uop_mem_size = 2'h0;\t// @[core.scala:815:29]\n wire [1:0] slow_wakeup_2_bits_fflags_bits_uop_dst_rtype = 2'h0;\t// @[core.scala:815:29]\n wire [1:0] slow_wakeup_2_bits_fflags_bits_uop_lrs1_rtype = 2'h0;\t// @[core.scala:815:29]\n wire [1:0] slow_wakeup_2_bits_fflags_bits_uop_lrs2_rtype = 2'h0;\t// @[core.scala:815:29]\n wire [1:0] slow_wakeup_2_bits_fflags_bits_uop_debug_fsrc = 2'h0;\t// @[core.scala:815:29]\n wire [1:0] slow_wakeup_2_bits_fflags_bits_uop_debug_tsrc = 2'h0;\t// @[core.scala:815:29]\n wire [4:0] io_ifu_fetchpacket_bits_uops_0_bits_ctrl_op_fcn = 5'h0;\t// @[core.scala:51:7]\n wire [4:0] io_ifu_fetchpacket_bits_uops_0_bits_ldq_idx = 5'h0;\t// @[core.scala:51:7]\n wire [4:0] io_ifu_fetchpacket_bits_uops_0_bits_stq_idx = 5'h0;\t// @[core.scala:51:7]\n wire [4:0] io_ifu_fetchpacket_bits_uops_0_bits_ppred = 5'h0;\t// @[core.scala:51:7]\n wire [4:0] io_ifu_fetchpacket_bits_uops_0_bits_mem_cmd = 5'h0;\t// @[core.scala:51:7]\n wire [4:0] io_ifu_fetchpacket_bits_uops_1_bits_ctrl_op_fcn = 5'h0;\t// @[core.scala:51:7]\n wire [4:0] io_ifu_fetchpacket_bits_uops_1_bits_ldq_idx = 5'h0;\t// @[core.scala:51:7]\n wire [4:0] io_ifu_fetchpacket_bits_uops_1_bits_stq_idx = 5'h0;\t// @[core.scala:51:7]\n wire [4:0] io_ifu_fetchpacket_bits_uops_1_bits_ppred = 5'h0;\t// @[core.scala:51:7]\n wire [4:0] io_ifu_fetchpacket_bits_uops_1_bits_mem_cmd = 5'h0;\t// @[core.scala:51:7]\n wire [4:0] io_ifu_fetchpacket_bits_uops_2_bits_ctrl_op_fcn = 5'h0;\t// @[core.scala:51:7]\n wire [4:0] io_ifu_fetchpacket_bits_uops_2_bits_ldq_idx = 5'h0;\t// @[core.scala:51:7]\n wire [4:0] io_ifu_fetchpacket_bits_uops_2_bits_stq_idx = 5'h0;\t// @[core.scala:51:7]\n wire [4:0] io_ifu_fetchpacket_bits_uops_2_bits_ppred = 5'h0;\t// @[core.scala:51:7]\n wire [4:0] io_ifu_fetchpacket_bits_uops_2_bits_mem_cmd = 5'h0;\t// @[core.scala:51:7]\n wire [4:0] io_ifu_get_pc_0_ghist_ras_idx = 5'h0;\t// @[core.scala:51:7]\n wire [4:0] io_ifu_debug_ftq_idx_0 = 5'h0;\t// @[core.scala:51:7]\n wire [4:0] io_ifu_debug_ftq_idx_1 = 5'h0;\t// @[core.scala:51:7]\n wire [4:0] io_ifu_debug_ftq_idx_2 = 5'h0;\t// @[core.scala:51:7]\n wire [4:0] io_ptw_hstatus_zero1 = 5'h0;\t// @[core.scala:51:7]\n wire [4:0] io_rocc_cmd_bits_inst_rs2 = 5'h0;\t// @[core.scala:51:7]\n wire [4:0] io_rocc_cmd_bits_inst_rs1 = 5'h0;\t// @[core.scala:51:7]\n wire [4:0] io_rocc_cmd_bits_inst_rd = 5'h0;\t// @[core.scala:51:7]\n wire [4:0] io_rocc_resp_bits_rd = 5'h0;\t// @[core.scala:51:7]\n wire [4:0] io_rocc_mem_req_bits_cmd = 5'h0;\t// @[core.scala:51:7]\n wire [4:0] io_rocc_mem_resp_bits_cmd = 5'h0;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_exe_0_req_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_exe_0_req_bits_fflags_bits_uop_ftq_idx = 5'h0;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_exe_0_req_bits_fflags_bits_uop_ldq_idx = 5'h0;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_exe_0_req_bits_fflags_bits_uop_stq_idx = 5'h0;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_exe_0_req_bits_fflags_bits_uop_ppred = 5'h0;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_exe_0_req_bits_fflags_bits_uop_mem_cmd = 5'h0;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_exe_0_req_bits_fflags_bits_flags = 5'h0;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_ftq_idx = 5'h0;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_ldq_idx = 5'h0;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_stq_idx = 5'h0;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_ppred = 5'h0;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_mem_cmd = 5'h0;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_exe_0_iresp_bits_fflags_bits_flags = 5'h0;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_ftq_idx = 5'h0;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_ldq_idx = 5'h0;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_stq_idx = 5'h0;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_ppred = 5'h0;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_mem_cmd = 5'h0;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_exe_0_fresp_bits_fflags_bits_flags = 5'h0;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_dis_uops_0_bits_ppred = 5'h0;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_dis_uops_1_bits_ppred = 5'h0;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_dis_uops_2_bits_ppred = 5'h0;\t// @[core.scala:51:7]\n wire [4:0] io_ptw_tlb_hstatus_zero1 = 5'h0;\t// @[core.scala:51:7]\n wire [4:0] int_iss_wakeups_1_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0;\t// @[core.scala:147:30]\n wire [4:0] int_iss_wakeups_1_bits_fflags_bits_uop_ftq_idx = 5'h0;\t// @[core.scala:147:30]\n wire [4:0] int_iss_wakeups_1_bits_fflags_bits_uop_ldq_idx = 5'h0;\t// @[core.scala:147:30]\n wire [4:0] int_iss_wakeups_1_bits_fflags_bits_uop_stq_idx = 5'h0;\t// @[core.scala:147:30]\n wire [4:0] int_iss_wakeups_1_bits_fflags_bits_uop_ppred = 5'h0;\t// @[core.scala:147:30]\n wire [4:0] int_iss_wakeups_1_bits_fflags_bits_uop_mem_cmd = 5'h0;\t// @[core.scala:147:30]\n wire [4:0] int_iss_wakeups_1_bits_fflags_bits_flags = 5'h0;\t// @[core.scala:147:30]\n wire [4:0] int_iss_wakeups_2_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0;\t// @[core.scala:147:30]\n wire [4:0] int_iss_wakeups_2_bits_fflags_bits_uop_ftq_idx = 5'h0;\t// @[core.scala:147:30]\n wire [4:0] int_iss_wakeups_2_bits_fflags_bits_uop_ldq_idx = 5'h0;\t// @[core.scala:147:30]\n wire [4:0] int_iss_wakeups_2_bits_fflags_bits_uop_stq_idx = 5'h0;\t// @[core.scala:147:30]\n wire [4:0] int_iss_wakeups_2_bits_fflags_bits_uop_ppred = 5'h0;\t// @[core.scala:147:30]\n wire [4:0] int_iss_wakeups_2_bits_fflags_bits_uop_mem_cmd = 5'h0;\t// @[core.scala:147:30]\n wire [4:0] int_iss_wakeups_2_bits_fflags_bits_flags = 5'h0;\t// @[core.scala:147:30]\n wire [4:0] int_iss_wakeups_3_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0;\t// @[core.scala:147:30]\n wire [4:0] int_iss_wakeups_3_bits_fflags_bits_uop_ftq_idx = 5'h0;\t// @[core.scala:147:30]\n wire [4:0] int_iss_wakeups_3_bits_fflags_bits_uop_ldq_idx = 5'h0;\t// @[core.scala:147:30]\n wire [4:0] int_iss_wakeups_3_bits_fflags_bits_uop_stq_idx = 5'h0;\t// @[core.scala:147:30]\n wire [4:0] int_iss_wakeups_3_bits_fflags_bits_uop_ppred = 5'h0;\t// @[core.scala:147:30]\n wire [4:0] int_iss_wakeups_3_bits_fflags_bits_uop_mem_cmd = 5'h0;\t// @[core.scala:147:30]\n wire [4:0] int_iss_wakeups_3_bits_fflags_bits_flags = 5'h0;\t// @[core.scala:147:30]\n wire [4:0] int_iss_wakeups_4_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0;\t// @[core.scala:147:30]\n wire [4:0] int_iss_wakeups_4_bits_fflags_bits_uop_ftq_idx = 5'h0;\t// @[core.scala:147:30]\n wire [4:0] int_iss_wakeups_4_bits_fflags_bits_uop_ldq_idx = 5'h0;\t// @[core.scala:147:30]\n wire [4:0] int_iss_wakeups_4_bits_fflags_bits_uop_stq_idx = 5'h0;\t// @[core.scala:147:30]\n wire [4:0] int_iss_wakeups_4_bits_fflags_bits_uop_ppred = 5'h0;\t// @[core.scala:147:30]\n wire [4:0] int_iss_wakeups_4_bits_fflags_bits_uop_mem_cmd = 5'h0;\t// @[core.scala:147:30]\n wire [4:0] int_iss_wakeups_4_bits_fflags_bits_flags = 5'h0;\t// @[core.scala:147:30]\n wire [4:0] int_iss_wakeups_5_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0;\t// @[core.scala:147:30]\n wire [4:0] int_iss_wakeups_5_bits_fflags_bits_uop_ftq_idx = 5'h0;\t// @[core.scala:147:30]\n wire [4:0] int_iss_wakeups_5_bits_fflags_bits_uop_ldq_idx = 5'h0;\t// @[core.scala:147:30]\n wire [4:0] int_iss_wakeups_5_bits_fflags_bits_uop_stq_idx = 5'h0;\t// @[core.scala:147:30]\n wire [4:0] int_iss_wakeups_5_bits_fflags_bits_uop_ppred = 5'h0;\t// @[core.scala:147:30]\n wire [4:0] int_iss_wakeups_5_bits_fflags_bits_uop_mem_cmd = 5'h0;\t// @[core.scala:147:30]\n wire [4:0] int_iss_wakeups_5_bits_fflags_bits_flags = 5'h0;\t// @[core.scala:147:30]\n wire [4:0] int_iss_wakeups_6_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0;\t// @[core.scala:147:30]\n wire [4:0] int_iss_wakeups_6_bits_fflags_bits_uop_ftq_idx = 5'h0;\t// @[core.scala:147:30]\n wire [4:0] int_iss_wakeups_6_bits_fflags_bits_uop_ldq_idx = 5'h0;\t// @[core.scala:147:30]\n wire [4:0] int_iss_wakeups_6_bits_fflags_bits_uop_stq_idx = 5'h0;\t// @[core.scala:147:30]\n wire [4:0] int_iss_wakeups_6_bits_fflags_bits_uop_ppred = 5'h0;\t// @[core.scala:147:30]\n wire [4:0] int_iss_wakeups_6_bits_fflags_bits_uop_mem_cmd = 5'h0;\t// @[core.scala:147:30]\n wire [4:0] int_iss_wakeups_6_bits_fflags_bits_flags = 5'h0;\t// @[core.scala:147:30]\n wire [4:0] int_ren_wakeups_1_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0;\t// @[core.scala:148:30]\n wire [4:0] int_ren_wakeups_1_bits_fflags_bits_uop_ftq_idx = 5'h0;\t// @[core.scala:148:30]\n wire [4:0] int_ren_wakeups_1_bits_fflags_bits_uop_ldq_idx = 5'h0;\t// @[core.scala:148:30]\n wire [4:0] int_ren_wakeups_1_bits_fflags_bits_uop_stq_idx = 5'h0;\t// @[core.scala:148:30]\n wire [4:0] int_ren_wakeups_1_bits_fflags_bits_uop_ppred = 5'h0;\t// @[core.scala:148:30]\n wire [4:0] int_ren_wakeups_1_bits_fflags_bits_uop_mem_cmd = 5'h0;\t// @[core.scala:148:30]\n wire [4:0] int_ren_wakeups_1_bits_fflags_bits_flags = 5'h0;\t// @[core.scala:148:30]\n wire [4:0] int_ren_wakeups_2_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0;\t// @[core.scala:148:30]\n wire [4:0] int_ren_wakeups_2_bits_fflags_bits_uop_ftq_idx = 5'h0;\t// @[core.scala:148:30]\n wire [4:0] int_ren_wakeups_2_bits_fflags_bits_uop_ldq_idx = 5'h0;\t// @[core.scala:148:30]\n wire [4:0] int_ren_wakeups_2_bits_fflags_bits_uop_stq_idx = 5'h0;\t// @[core.scala:148:30]\n wire [4:0] int_ren_wakeups_2_bits_fflags_bits_uop_ppred = 5'h0;\t// @[core.scala:148:30]\n wire [4:0] int_ren_wakeups_2_bits_fflags_bits_uop_mem_cmd = 5'h0;\t// @[core.scala:148:30]\n wire [4:0] int_ren_wakeups_2_bits_fflags_bits_flags = 5'h0;\t// @[core.scala:148:30]\n wire [4:0] int_ren_wakeups_3_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0;\t// @[core.scala:148:30]\n wire [4:0] int_ren_wakeups_3_bits_fflags_bits_uop_ftq_idx = 5'h0;\t// @[core.scala:148:30]\n wire [4:0] int_ren_wakeups_3_bits_fflags_bits_uop_ldq_idx = 5'h0;\t// @[core.scala:148:30]\n wire [4:0] int_ren_wakeups_3_bits_fflags_bits_uop_stq_idx = 5'h0;\t// @[core.scala:148:30]\n wire [4:0] int_ren_wakeups_3_bits_fflags_bits_uop_ppred = 5'h0;\t// @[core.scala:148:30]\n wire [4:0] int_ren_wakeups_3_bits_fflags_bits_uop_mem_cmd = 5'h0;\t// @[core.scala:148:30]\n wire [4:0] int_ren_wakeups_3_bits_fflags_bits_flags = 5'h0;\t// @[core.scala:148:30]\n wire [4:0] int_ren_wakeups_4_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0;\t// @[core.scala:148:30]\n wire [4:0] int_ren_wakeups_4_bits_fflags_bits_uop_ftq_idx = 5'h0;\t// @[core.scala:148:30]\n wire [4:0] int_ren_wakeups_4_bits_fflags_bits_uop_ldq_idx = 5'h0;\t// @[core.scala:148:30]\n wire [4:0] int_ren_wakeups_4_bits_fflags_bits_uop_stq_idx = 5'h0;\t// @[core.scala:148:30]\n wire [4:0] int_ren_wakeups_4_bits_fflags_bits_uop_ppred = 5'h0;\t// @[core.scala:148:30]\n wire [4:0] int_ren_wakeups_4_bits_fflags_bits_uop_mem_cmd = 5'h0;\t// @[core.scala:148:30]\n wire [4:0] int_ren_wakeups_4_bits_fflags_bits_flags = 5'h0;\t// @[core.scala:148:30]\n wire [4:0] int_ren_wakeups_5_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0;\t// @[core.scala:148:30]\n wire [4:0] int_ren_wakeups_5_bits_fflags_bits_uop_ftq_idx = 5'h0;\t// @[core.scala:148:30]\n wire [4:0] int_ren_wakeups_5_bits_fflags_bits_uop_ldq_idx = 5'h0;\t// @[core.scala:148:30]\n wire [4:0] int_ren_wakeups_5_bits_fflags_bits_uop_stq_idx = 5'h0;\t// @[core.scala:148:30]\n wire [4:0] int_ren_wakeups_5_bits_fflags_bits_uop_ppred = 5'h0;\t// @[core.scala:148:30]\n wire [4:0] int_ren_wakeups_5_bits_fflags_bits_uop_mem_cmd = 5'h0;\t// @[core.scala:148:30]\n wire [4:0] int_ren_wakeups_5_bits_fflags_bits_flags = 5'h0;\t// @[core.scala:148:30]\n wire [4:0] int_ren_wakeups_6_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0;\t// @[core.scala:148:30]\n wire [4:0] int_ren_wakeups_6_bits_fflags_bits_uop_ftq_idx = 5'h0;\t// @[core.scala:148:30]\n wire [4:0] int_ren_wakeups_6_bits_fflags_bits_uop_ldq_idx = 5'h0;\t// @[core.scala:148:30]\n wire [4:0] int_ren_wakeups_6_bits_fflags_bits_uop_stq_idx = 5'h0;\t// @[core.scala:148:30]\n wire [4:0] int_ren_wakeups_6_bits_fflags_bits_uop_ppred = 5'h0;\t// @[core.scala:148:30]\n wire [4:0] int_ren_wakeups_6_bits_fflags_bits_uop_mem_cmd = 5'h0;\t// @[core.scala:148:30]\n wire [4:0] int_ren_wakeups_6_bits_fflags_bits_flags = 5'h0;\t// @[core.scala:148:30]\n wire [4:0] pred_wakeup_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0;\t// @[core.scala:149:26]\n wire [4:0] pred_wakeup_bits_fflags_bits_uop_ftq_idx = 5'h0;\t// @[core.scala:149:26]\n wire [4:0] pred_wakeup_bits_fflags_bits_uop_ldq_idx = 5'h0;\t// @[core.scala:149:26]\n wire [4:0] pred_wakeup_bits_fflags_bits_uop_stq_idx = 5'h0;\t// @[core.scala:149:26]\n wire [4:0] pred_wakeup_bits_fflags_bits_uop_ppred = 5'h0;\t// @[core.scala:149:26]\n wire [4:0] pred_wakeup_bits_fflags_bits_uop_mem_cmd = 5'h0;\t// @[core.scala:149:26]\n wire [4:0] pred_wakeup_bits_fflags_bits_flags = 5'h0;\t// @[core.scala:149:26]\n wire [4:0] dec_uops_0_ctrl_op_fcn = 5'h0;\t// @[core.scala:158:24]\n wire [4:0] dec_uops_0_ldq_idx = 5'h0;\t// @[core.scala:158:24]\n wire [4:0] dec_uops_0_stq_idx = 5'h0;\t// @[core.scala:158:24]\n wire [4:0] dec_uops_0_ppred = 5'h0;\t// @[core.scala:158:24]\n wire [4:0] dec_uops_1_ctrl_op_fcn = 5'h0;\t// @[core.scala:158:24]\n wire [4:0] dec_uops_1_ldq_idx = 5'h0;\t// @[core.scala:158:24]\n wire [4:0] dec_uops_1_stq_idx = 5'h0;\t// @[core.scala:158:24]\n wire [4:0] dec_uops_1_ppred = 5'h0;\t// @[core.scala:158:24]\n wire [4:0] dec_uops_2_ctrl_op_fcn = 5'h0;\t// @[core.scala:158:24]\n wire [4:0] dec_uops_2_ldq_idx = 5'h0;\t// @[core.scala:158:24]\n wire [4:0] dec_uops_2_stq_idx = 5'h0;\t// @[core.scala:158:24]\n wire [4:0] dec_uops_2_ppred = 5'h0;\t// @[core.scala:158:24]\n wire [4:0] dis_uops_0_ppred = 5'h0;\t// @[core.scala:167:24]\n wire [4:0] dis_uops_1_ppred = 5'h0;\t// @[core.scala:167:24]\n wire [4:0] dis_uops_2_ppred = 5'h0;\t// @[core.scala:167:24]\n wire [4:0] bypasses_0_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0;\t// @[core.scala:174:24]\n wire [4:0] bypasses_0_bits_fflags_bits_uop_ftq_idx = 5'h0;\t// @[core.scala:174:24]\n wire [4:0] bypasses_0_bits_fflags_bits_uop_ldq_idx = 5'h0;\t// @[core.scala:174:24]\n wire [4:0] bypasses_0_bits_fflags_bits_uop_stq_idx = 5'h0;\t// @[core.scala:174:24]\n wire [4:0] bypasses_0_bits_fflags_bits_uop_ppred = 5'h0;\t// @[core.scala:174:24]\n wire [4:0] bypasses_0_bits_fflags_bits_uop_mem_cmd = 5'h0;\t// @[core.scala:174:24]\n wire [4:0] bypasses_0_bits_fflags_bits_flags = 5'h0;\t// @[core.scala:174:24]\n wire [4:0] bypasses_1_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0;\t// @[core.scala:174:24]\n wire [4:0] bypasses_1_bits_fflags_bits_uop_ftq_idx = 5'h0;\t// @[core.scala:174:24]\n wire [4:0] bypasses_1_bits_fflags_bits_uop_ldq_idx = 5'h0;\t// @[core.scala:174:24]\n wire [4:0] bypasses_1_bits_fflags_bits_uop_stq_idx = 5'h0;\t// @[core.scala:174:24]\n wire [4:0] bypasses_1_bits_fflags_bits_uop_ppred = 5'h0;\t// @[core.scala:174:24]\n wire [4:0] bypasses_1_bits_fflags_bits_uop_mem_cmd = 5'h0;\t// @[core.scala:174:24]\n wire [4:0] bypasses_1_bits_fflags_bits_flags = 5'h0;\t// @[core.scala:174:24]\n wire [4:0] bypasses_2_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0;\t// @[core.scala:174:24]\n wire [4:0] bypasses_2_bits_fflags_bits_uop_ftq_idx = 5'h0;\t// @[core.scala:174:24]\n wire [4:0] bypasses_2_bits_fflags_bits_uop_ldq_idx = 5'h0;\t// @[core.scala:174:24]\n wire [4:0] bypasses_2_bits_fflags_bits_uop_stq_idx = 5'h0;\t// @[core.scala:174:24]\n wire [4:0] bypasses_2_bits_fflags_bits_uop_ppred = 5'h0;\t// @[core.scala:174:24]\n wire [4:0] bypasses_2_bits_fflags_bits_uop_mem_cmd = 5'h0;\t// @[core.scala:174:24]\n wire [4:0] bypasses_2_bits_fflags_bits_flags = 5'h0;\t// @[core.scala:174:24]\n wire [4:0] bypasses_3_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0;\t// @[core.scala:174:24]\n wire [4:0] bypasses_3_bits_fflags_bits_uop_ftq_idx = 5'h0;\t// @[core.scala:174:24]\n wire [4:0] bypasses_3_bits_fflags_bits_uop_ldq_idx = 5'h0;\t// @[core.scala:174:24]\n wire [4:0] bypasses_3_bits_fflags_bits_uop_stq_idx = 5'h0;\t// @[core.scala:174:24]\n wire [4:0] bypasses_3_bits_fflags_bits_uop_ppred = 5'h0;\t// @[core.scala:174:24]\n wire [4:0] bypasses_3_bits_fflags_bits_uop_mem_cmd = 5'h0;\t// @[core.scala:174:24]\n wire [4:0] bypasses_3_bits_fflags_bits_flags = 5'h0;\t// @[core.scala:174:24]\n wire [4:0] bypasses_4_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0;\t// @[core.scala:174:24]\n wire [4:0] bypasses_4_bits_fflags_bits_uop_ftq_idx = 5'h0;\t// @[core.scala:174:24]\n wire [4:0] bypasses_4_bits_fflags_bits_uop_ldq_idx = 5'h0;\t// @[core.scala:174:24]\n wire [4:0] bypasses_4_bits_fflags_bits_uop_stq_idx = 5'h0;\t// @[core.scala:174:24]\n wire [4:0] bypasses_4_bits_fflags_bits_uop_ppred = 5'h0;\t// @[core.scala:174:24]\n wire [4:0] bypasses_4_bits_fflags_bits_uop_mem_cmd = 5'h0;\t// @[core.scala:174:24]\n wire [4:0] bypasses_4_bits_fflags_bits_flags = 5'h0;\t// @[core.scala:174:24]\n wire [4:0] pred_bypasses_0_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0;\t// @[core.scala:175:27]\n wire [4:0] pred_bypasses_0_bits_fflags_bits_uop_ftq_idx = 5'h0;\t// @[core.scala:175:27]\n wire [4:0] pred_bypasses_0_bits_fflags_bits_uop_ldq_idx = 5'h0;\t// @[core.scala:175:27]\n wire [4:0] pred_bypasses_0_bits_fflags_bits_uop_stq_idx = 5'h0;\t// @[core.scala:175:27]\n wire [4:0] pred_bypasses_0_bits_fflags_bits_uop_ppred = 5'h0;\t// @[core.scala:175:27]\n wire [4:0] pred_bypasses_0_bits_fflags_bits_uop_mem_cmd = 5'h0;\t// @[core.scala:175:27]\n wire [4:0] pred_bypasses_0_bits_fflags_bits_flags = 5'h0;\t// @[core.scala:175:27]\n wire [4:0] _new_ghist_WIRE_ras_idx = 5'h0;\t// @[core.scala:406:44]\n wire [4:0] p_uop_ctrl_op_fcn = 5'h0;\t// @[consts.scala:269:19]\n wire [4:0] p_uop_ftq_idx = 5'h0;\t// @[consts.scala:269:19]\n wire [4:0] p_uop_ldq_idx = 5'h0;\t// @[consts.scala:269:19]\n wire [4:0] p_uop_stq_idx = 5'h0;\t// @[consts.scala:269:19]\n wire [4:0] p_uop_ppred = 5'h0;\t// @[consts.scala:269:19]\n wire [4:0] p_uop_mem_cmd = 5'h0;\t// @[consts.scala:269:19]\n wire [4:0] p_uop_cs_op_fcn = 5'h0;\t// @[consts.scala:279:18]\n wire [4:0] p_uop_1_ctrl_op_fcn = 5'h0;\t// @[consts.scala:269:19]\n wire [4:0] p_uop_1_ftq_idx = 5'h0;\t// @[consts.scala:269:19]\n wire [4:0] p_uop_1_ldq_idx = 5'h0;\t// @[consts.scala:269:19]\n wire [4:0] p_uop_1_stq_idx = 5'h0;\t// @[consts.scala:269:19]\n wire [4:0] p_uop_1_ppred = 5'h0;\t// @[consts.scala:269:19]\n wire [4:0] p_uop_1_mem_cmd = 5'h0;\t// @[consts.scala:269:19]\n wire [4:0] p_uop_cs_1_op_fcn = 5'h0;\t// @[consts.scala:279:18]\n wire [4:0] p_uop_2_ctrl_op_fcn = 5'h0;\t// @[consts.scala:269:19]\n wire [4:0] p_uop_2_ftq_idx = 5'h0;\t// @[consts.scala:269:19]\n wire [4:0] p_uop_2_ldq_idx = 5'h0;\t// @[consts.scala:269:19]\n wire [4:0] p_uop_2_stq_idx = 5'h0;\t// @[consts.scala:269:19]\n wire [4:0] p_uop_2_ppred = 5'h0;\t// @[consts.scala:269:19]\n wire [4:0] p_uop_2_mem_cmd = 5'h0;\t// @[consts.scala:269:19]\n wire [4:0] p_uop_cs_2_op_fcn = 5'h0;\t// @[consts.scala:279:18]\n wire [4:0] fast_wakeup_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0;\t// @[core.scala:814:29]\n wire [4:0] fast_wakeup_bits_fflags_bits_uop_ftq_idx = 5'h0;\t// @[core.scala:814:29]\n wire [4:0] fast_wakeup_bits_fflags_bits_uop_ldq_idx = 5'h0;\t// @[core.scala:814:29]\n wire [4:0] fast_wakeup_bits_fflags_bits_uop_stq_idx = 5'h0;\t// @[core.scala:814:29]\n wire [4:0] fast_wakeup_bits_fflags_bits_uop_ppred = 5'h0;\t// @[core.scala:814:29]\n wire [4:0] fast_wakeup_bits_fflags_bits_uop_mem_cmd = 5'h0;\t// @[core.scala:814:29]\n wire [4:0] fast_wakeup_bits_fflags_bits_flags = 5'h0;\t// @[core.scala:814:29]\n wire [4:0] slow_wakeup_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0;\t// @[core.scala:815:29]\n wire [4:0] slow_wakeup_bits_fflags_bits_uop_ftq_idx = 5'h0;\t// @[core.scala:815:29]\n wire [4:0] slow_wakeup_bits_fflags_bits_uop_ldq_idx = 5'h0;\t// @[core.scala:815:29]\n wire [4:0] slow_wakeup_bits_fflags_bits_uop_stq_idx = 5'h0;\t// @[core.scala:815:29]\n wire [4:0] slow_wakeup_bits_fflags_bits_uop_ppred = 5'h0;\t// @[core.scala:815:29]\n wire [4:0] slow_wakeup_bits_fflags_bits_uop_mem_cmd = 5'h0;\t// @[core.scala:815:29]\n wire [4:0] slow_wakeup_bits_fflags_bits_flags = 5'h0;\t// @[core.scala:815:29]\n wire [4:0] fast_wakeup_1_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0;\t// @[core.scala:814:29]\n wire [4:0] fast_wakeup_1_bits_fflags_bits_uop_ftq_idx = 5'h0;\t// @[core.scala:814:29]\n wire [4:0] fast_wakeup_1_bits_fflags_bits_uop_ldq_idx = 5'h0;\t// @[core.scala:814:29]\n wire [4:0] fast_wakeup_1_bits_fflags_bits_uop_stq_idx = 5'h0;\t// @[core.scala:814:29]\n wire [4:0] fast_wakeup_1_bits_fflags_bits_uop_ppred = 5'h0;\t// @[core.scala:814:29]\n wire [4:0] fast_wakeup_1_bits_fflags_bits_uop_mem_cmd = 5'h0;\t// @[core.scala:814:29]\n wire [4:0] fast_wakeup_1_bits_fflags_bits_flags = 5'h0;\t// @[core.scala:814:29]\n wire [4:0] slow_wakeup_1_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0;\t// @[core.scala:815:29]\n wire [4:0] slow_wakeup_1_bits_fflags_bits_uop_ftq_idx = 5'h0;\t// @[core.scala:815:29]\n wire [4:0] slow_wakeup_1_bits_fflags_bits_uop_ldq_idx = 5'h0;\t// @[core.scala:815:29]\n wire [4:0] slow_wakeup_1_bits_fflags_bits_uop_stq_idx = 5'h0;\t// @[core.scala:815:29]\n wire [4:0] slow_wakeup_1_bits_fflags_bits_uop_ppred = 5'h0;\t// @[core.scala:815:29]\n wire [4:0] slow_wakeup_1_bits_fflags_bits_uop_mem_cmd = 5'h0;\t// @[core.scala:815:29]\n wire [4:0] slow_wakeup_1_bits_fflags_bits_flags = 5'h0;\t// @[core.scala:815:29]\n wire [4:0] fast_wakeup_2_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0;\t// @[core.scala:814:29]\n wire [4:0] fast_wakeup_2_bits_fflags_bits_uop_ftq_idx = 5'h0;\t// @[core.scala:814:29]\n wire [4:0] fast_wakeup_2_bits_fflags_bits_uop_ldq_idx = 5'h0;\t// @[core.scala:814:29]\n wire [4:0] fast_wakeup_2_bits_fflags_bits_uop_stq_idx = 5'h0;\t// @[core.scala:814:29]\n wire [4:0] fast_wakeup_2_bits_fflags_bits_uop_ppred = 5'h0;\t// @[core.scala:814:29]\n wire [4:0] fast_wakeup_2_bits_fflags_bits_uop_mem_cmd = 5'h0;\t// @[core.scala:814:29]\n wire [4:0] fast_wakeup_2_bits_fflags_bits_flags = 5'h0;\t// @[core.scala:814:29]\n wire [4:0] slow_wakeup_2_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0;\t// @[core.scala:815:29]\n wire [4:0] slow_wakeup_2_bits_fflags_bits_uop_ftq_idx = 5'h0;\t// @[core.scala:815:29]\n wire [4:0] slow_wakeup_2_bits_fflags_bits_uop_ldq_idx = 5'h0;\t// @[core.scala:815:29]\n wire [4:0] slow_wakeup_2_bits_fflags_bits_uop_stq_idx = 5'h0;\t// @[core.scala:815:29]\n wire [4:0] slow_wakeup_2_bits_fflags_bits_uop_ppred = 5'h0;\t// @[core.scala:815:29]\n wire [4:0] slow_wakeup_2_bits_fflags_bits_uop_mem_cmd = 5'h0;\t// @[core.scala:815:29]\n wire [4:0] slow_wakeup_2_bits_fflags_bits_flags = 5'h0;\t// @[core.scala:815:29]\n wire [4:0] coreMonitorBundle_wrdst = 5'h0;\t// @[core.scala:1405:31]\n wire [4:0] coreMonitorBundle_rd0src = 5'h0;\t// @[core.scala:1405:31]\n wire [4:0] coreMonitorBundle_rd1src = 5'h0;\t// @[core.scala:1405:31]\n wire io_ifu_fetchpacket_bits_uops_0_bits_ctrl_fcn_dw = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_0_bits_ctrl_is_load = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_0_bits_ctrl_is_sta = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_0_bits_ctrl_is_std = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_0_bits_iw_p1_poisoned = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_0_bits_iw_p2_poisoned = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_0_bits_is_br = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_0_bits_is_jalr = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_0_bits_is_jal = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_0_bits_prs1_busy = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_0_bits_prs2_busy = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_0_bits_prs3_busy = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_0_bits_ppred_busy = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_0_bits_exception = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_0_bits_bypassable = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_0_bits_mem_signed = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_0_bits_is_fence = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_0_bits_is_fencei = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_0_bits_is_amo = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_0_bits_uses_ldq = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_0_bits_uses_stq = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_0_bits_is_sys_pc2epc = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_0_bits_is_unique = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_0_bits_flush_on_commit = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_0_bits_ldst_is_rs1 = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_0_bits_ldst_val = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_0_bits_frs3_en = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_0_bits_fp_val = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_0_bits_fp_single = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_0_bits_xcpt_ma_if = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_1_bits_ctrl_fcn_dw = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_1_bits_ctrl_is_load = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_1_bits_ctrl_is_sta = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_1_bits_ctrl_is_std = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_1_bits_iw_p1_poisoned = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_1_bits_iw_p2_poisoned = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_1_bits_is_br = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_1_bits_is_jalr = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_1_bits_is_jal = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_1_bits_prs1_busy = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_1_bits_prs2_busy = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_1_bits_prs3_busy = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_1_bits_ppred_busy = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_1_bits_exception = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_1_bits_bypassable = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_1_bits_mem_signed = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_1_bits_is_fence = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_1_bits_is_fencei = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_1_bits_is_amo = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_1_bits_uses_ldq = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_1_bits_uses_stq = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_1_bits_is_sys_pc2epc = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_1_bits_is_unique = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_1_bits_flush_on_commit = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_1_bits_ldst_is_rs1 = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_1_bits_ldst_val = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_1_bits_frs3_en = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_1_bits_fp_val = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_1_bits_fp_single = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_1_bits_xcpt_ma_if = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_2_bits_ctrl_fcn_dw = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_2_bits_ctrl_is_load = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_2_bits_ctrl_is_sta = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_2_bits_ctrl_is_std = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_2_bits_iw_p1_poisoned = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_2_bits_iw_p2_poisoned = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_2_bits_is_br = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_2_bits_is_jalr = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_2_bits_is_jal = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_2_bits_prs1_busy = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_2_bits_prs2_busy = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_2_bits_prs3_busy = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_2_bits_ppred_busy = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_2_bits_exception = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_2_bits_bypassable = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_2_bits_mem_signed = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_2_bits_is_fence = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_2_bits_is_fencei = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_2_bits_is_amo = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_2_bits_uses_ldq = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_2_bits_uses_stq = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_2_bits_is_sys_pc2epc = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_2_bits_is_unique = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_2_bits_flush_on_commit = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_2_bits_ldst_is_rs1 = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_2_bits_ldst_val = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_2_bits_frs3_en = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_2_bits_fp_val = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_2_bits_fp_single = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_fetchpacket_bits_uops_2_bits_xcpt_ma_if = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_get_pc_0_ghist_current_saw_branch_not_taken = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_get_pc_0_ghist_new_saw_branch_not_taken = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_get_pc_0_ghist_new_saw_branch_taken = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_status_mbe = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_status_sbe = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_status_sd_rv32 = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_status_ube = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_status_upie = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_status_hie = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_status_uie = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_sfence_bits_hv = 1'h0;\t// @[core.scala:51:7]\n wire io_ifu_sfence_bits_hg = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_sfence_bits_hv = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_sfence_bits_hg = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_status_mbe = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_status_sbe = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_status_sd_rv32 = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_status_ube = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_status_upie = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_status_hie = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_status_uie = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_hstatus_vtsr = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_hstatus_vtw = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_hstatus_vtvm = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_hstatus_hu = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_hstatus_spvp = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_hstatus_spv = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_hstatus_gva = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_hstatus_vsbe = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_gstatus_debug = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_gstatus_cease = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_gstatus_wfi = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_gstatus_dv = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_gstatus_v = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_gstatus_sd = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_gstatus_mpv = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_gstatus_gva = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_gstatus_mbe = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_gstatus_sbe = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_gstatus_sd_rv32 = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_gstatus_tsr = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_gstatus_tw = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_gstatus_tvm = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_gstatus_mxr = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_gstatus_sum = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_gstatus_mprv = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_gstatus_spp = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_gstatus_mpie = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_gstatus_ube = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_gstatus_spie = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_gstatus_upie = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_gstatus_mie = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_gstatus_hie = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_gstatus_sie = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_gstatus_uie = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_customCSRs_csrs_0_ren = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_customCSRs_csrs_0_wen = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_customCSRs_csrs_0_stall = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_customCSRs_csrs_0_set = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_customCSRs_csrs_1_ren = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_customCSRs_csrs_1_wen = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_customCSRs_csrs_1_stall = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_customCSRs_csrs_1_set = 1'h0;\t// @[core.scala:51:7]\n wire io_rocc_cmd_ready = 1'h0;\t// @[core.scala:51:7]\n wire io_rocc_cmd_valid = 1'h0;\t// @[core.scala:51:7]\n wire io_rocc_cmd_bits_inst_xd = 1'h0;\t// @[core.scala:51:7]\n wire io_rocc_cmd_bits_inst_xs1 = 1'h0;\t// @[core.scala:51:7]\n wire io_rocc_cmd_bits_inst_xs2 = 1'h0;\t// @[core.scala:51:7]\n wire io_rocc_cmd_bits_status_debug = 1'h0;\t// @[core.scala:51:7]\n wire io_rocc_cmd_bits_status_cease = 1'h0;\t// @[core.scala:51:7]\n wire io_rocc_cmd_bits_status_wfi = 1'h0;\t// @[core.scala:51:7]\n wire io_rocc_cmd_bits_status_dv = 1'h0;\t// @[core.scala:51:7]\n wire io_rocc_cmd_bits_status_v = 1'h0;\t// @[core.scala:51:7]\n wire io_rocc_cmd_bits_status_sd = 1'h0;\t// @[core.scala:51:7]\n wire io_rocc_cmd_bits_status_mpv = 1'h0;\t// @[core.scala:51:7]\n wire io_rocc_cmd_bits_status_gva = 1'h0;\t// @[core.scala:51:7]\n wire io_rocc_cmd_bits_status_mbe = 1'h0;\t// @[core.scala:51:7]\n wire io_rocc_cmd_bits_status_sbe = 1'h0;\t// @[core.scala:51:7]\n wire io_rocc_cmd_bits_status_sd_rv32 = 1'h0;\t// @[core.scala:51:7]\n wire io_rocc_cmd_bits_status_tsr = 1'h0;\t// @[core.scala:51:7]\n wire io_rocc_cmd_bits_status_tw = 1'h0;\t// @[core.scala:51:7]\n wire io_rocc_cmd_bits_status_tvm = 1'h0;\t// @[core.scala:51:7]\n wire io_rocc_cmd_bits_status_mxr = 1'h0;\t// @[core.scala:51:7]\n wire io_rocc_cmd_bits_status_sum = 1'h0;\t// @[core.scala:51:7]\n wire io_rocc_cmd_bits_status_mprv = 1'h0;\t// @[core.scala:51:7]\n wire io_rocc_cmd_bits_status_spp = 1'h0;\t// @[core.scala:51:7]\n wire io_rocc_cmd_bits_status_mpie = 1'h0;\t// @[core.scala:51:7]\n wire io_rocc_cmd_bits_status_ube = 1'h0;\t// @[core.scala:51:7]\n wire io_rocc_cmd_bits_status_spie = 1'h0;\t// @[core.scala:51:7]\n wire io_rocc_cmd_bits_status_upie = 1'h0;\t// @[core.scala:51:7]\n wire io_rocc_cmd_bits_status_mie = 1'h0;\t// @[core.scala:51:7]\n wire io_rocc_cmd_bits_status_hie = 1'h0;\t// @[core.scala:51:7]\n wire io_rocc_cmd_bits_status_sie = 1'h0;\t// @[core.scala:51:7]\n wire io_rocc_cmd_bits_status_uie = 1'h0;\t// @[core.scala:51:7]\n wire io_rocc_resp_ready = 1'h0;\t// @[core.scala:51:7]\n wire io_rocc_resp_valid = 1'h0;\t// @[core.scala:51:7]\n wire io_rocc_mem_req_ready = 1'h0;\t// @[core.scala:51:7]\n wire io_rocc_mem_req_valid = 1'h0;\t// @[core.scala:51:7]\n wire io_rocc_mem_req_bits_signed = 1'h0;\t// @[core.scala:51:7]\n wire io_rocc_mem_req_bits_dv = 1'h0;\t// @[core.scala:51:7]\n wire io_rocc_mem_req_bits_phys = 1'h0;\t// @[core.scala:51:7]\n wire io_rocc_mem_req_bits_no_resp = 1'h0;\t// @[core.scala:51:7]\n wire io_rocc_mem_req_bits_no_alloc = 1'h0;\t// @[core.scala:51:7]\n wire io_rocc_mem_req_bits_no_xcpt = 1'h0;\t// @[core.scala:51:7]\n wire io_rocc_mem_s1_kill = 1'h0;\t// @[core.scala:51:7]\n wire io_rocc_mem_s2_nack = 1'h0;\t// @[core.scala:51:7]\n wire io_rocc_mem_s2_nack_cause_raw = 1'h0;\t// @[core.scala:51:7]\n wire io_rocc_mem_s2_kill = 1'h0;\t// @[core.scala:51:7]\n wire io_rocc_mem_s2_uncached = 1'h0;\t// @[core.scala:51:7]\n wire io_rocc_mem_resp_valid = 1'h0;\t// @[core.scala:51:7]\n wire io_rocc_mem_resp_bits_signed = 1'h0;\t// @[core.scala:51:7]\n wire io_rocc_mem_resp_bits_dv = 1'h0;\t// @[core.scala:51:7]\n wire io_rocc_mem_resp_bits_replay = 1'h0;\t// @[core.scala:51:7]\n wire io_rocc_mem_resp_bits_has_data = 1'h0;\t// @[core.scala:51:7]\n wire io_rocc_mem_replay_next = 1'h0;\t// @[core.scala:51:7]\n wire io_rocc_mem_s2_xcpt_ma_ld = 1'h0;\t// @[core.scala:51:7]\n wire io_rocc_mem_s2_xcpt_ma_st = 1'h0;\t// @[core.scala:51:7]\n wire io_rocc_mem_s2_xcpt_pf_ld = 1'h0;\t// @[core.scala:51:7]\n wire io_rocc_mem_s2_xcpt_pf_st = 1'h0;\t// @[core.scala:51:7]\n wire io_rocc_mem_s2_xcpt_gf_ld = 1'h0;\t// @[core.scala:51:7]\n wire io_rocc_mem_s2_xcpt_gf_st = 1'h0;\t// @[core.scala:51:7]\n wire io_rocc_mem_s2_xcpt_ae_ld = 1'h0;\t// @[core.scala:51:7]\n wire io_rocc_mem_s2_xcpt_ae_st = 1'h0;\t// @[core.scala:51:7]\n wire io_rocc_mem_s2_gpa_is_pte = 1'h0;\t// @[core.scala:51:7]\n wire io_rocc_mem_ordered = 1'h0;\t// @[core.scala:51:7]\n wire io_rocc_mem_store_pending = 1'h0;\t// @[core.scala:51:7]\n wire io_rocc_mem_perf_acquire = 1'h0;\t// @[core.scala:51:7]\n wire io_rocc_mem_perf_release = 1'h0;\t// @[core.scala:51:7]\n wire io_rocc_mem_perf_grant = 1'h0;\t// @[core.scala:51:7]\n wire io_rocc_mem_perf_tlbMiss = 1'h0;\t// @[core.scala:51:7]\n wire io_rocc_mem_perf_blocked = 1'h0;\t// @[core.scala:51:7]\n wire io_rocc_mem_perf_canAcceptStoreThenLoad = 1'h0;\t// @[core.scala:51:7]\n wire io_rocc_mem_perf_canAcceptStoreThenRMW = 1'h0;\t// @[core.scala:51:7]\n wire io_rocc_mem_perf_canAcceptLoadThenLoad = 1'h0;\t// @[core.scala:51:7]\n wire io_rocc_mem_perf_storeBufferEmptyAfterLoad = 1'h0;\t// @[core.scala:51:7]\n wire io_rocc_mem_perf_storeBufferEmptyAfterStore = 1'h0;\t// @[core.scala:51:7]\n wire io_rocc_mem_keep_clock_enabled = 1'h0;\t// @[core.scala:51:7]\n wire io_rocc_mem_clock_enabled = 1'h0;\t// @[core.scala:51:7]\n wire io_rocc_busy = 1'h0;\t// @[core.scala:51:7]\n wire io_rocc_interrupt = 1'h0;\t// @[core.scala:51:7]\n wire io_rocc_exception = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_req_bits_predicated = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_req_bits_fflags_valid = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_req_bits_fflags_bits_uop_is_rvc = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_req_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_req_bits_fflags_bits_uop_ctrl_is_load = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_req_bits_fflags_bits_uop_ctrl_is_sta = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_req_bits_fflags_bits_uop_ctrl_is_std = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_req_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_req_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_req_bits_fflags_bits_uop_is_br = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_req_bits_fflags_bits_uop_is_jalr = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_req_bits_fflags_bits_uop_is_jal = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_req_bits_fflags_bits_uop_is_sfb = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_req_bits_fflags_bits_uop_edge_inst = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_req_bits_fflags_bits_uop_taken = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_req_bits_fflags_bits_uop_prs1_busy = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_req_bits_fflags_bits_uop_prs2_busy = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_req_bits_fflags_bits_uop_prs3_busy = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_req_bits_fflags_bits_uop_ppred_busy = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_req_bits_fflags_bits_uop_exception = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_req_bits_fflags_bits_uop_bypassable = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_req_bits_fflags_bits_uop_mem_signed = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_req_bits_fflags_bits_uop_is_fence = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_req_bits_fflags_bits_uop_is_fencei = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_req_bits_fflags_bits_uop_is_amo = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_req_bits_fflags_bits_uop_uses_ldq = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_req_bits_fflags_bits_uop_uses_stq = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_req_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_req_bits_fflags_bits_uop_is_unique = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_req_bits_fflags_bits_uop_flush_on_commit = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_req_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_req_bits_fflags_bits_uop_ldst_val = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_req_bits_fflags_bits_uop_frs3_en = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_req_bits_fflags_bits_uop_fp_val = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_req_bits_fflags_bits_uop_fp_single = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_req_bits_fflags_bits_uop_xcpt_pf_if = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_req_bits_fflags_bits_uop_xcpt_ae_if = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_req_bits_fflags_bits_uop_xcpt_ma_if = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_req_bits_fflags_bits_uop_bp_debug_if = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_req_bits_fflags_bits_uop_bp_xcpt_if = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_req_bits_sfence_bits_hv = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_req_bits_sfence_bits_hg = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_iresp_bits_predicated = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_iresp_bits_fflags_valid = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_is_rvc = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_ctrl_is_load = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_ctrl_is_sta = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_ctrl_is_std = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_is_br = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_is_jalr = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_is_jal = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_is_sfb = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_edge_inst = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_taken = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_prs1_busy = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_prs2_busy = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_prs3_busy = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_ppred_busy = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_exception = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_bypassable = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_mem_signed = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_is_fence = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_is_fencei = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_is_amo = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_uses_ldq = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_uses_stq = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_is_unique = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_flush_on_commit = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_ldst_val = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_frs3_en = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_fp_val = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_fp_single = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_xcpt_pf_if = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_xcpt_ae_if = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_xcpt_ma_if = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_bp_debug_if = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_bp_xcpt_if = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_fresp_bits_predicated = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_fresp_bits_fflags_valid = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_is_rvc = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_ctrl_is_load = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_ctrl_is_sta = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_ctrl_is_std = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_is_br = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_is_jalr = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_is_jal = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_is_sfb = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_edge_inst = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_taken = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_prs1_busy = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_prs2_busy = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_prs3_busy = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_ppred_busy = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_exception = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_bypassable = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_mem_signed = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_is_fence = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_is_fencei = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_is_amo = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_uses_ldq = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_uses_stq = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_is_unique = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_flush_on_commit = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_ldst_val = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_frs3_en = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_fp_val = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_fp_single = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_xcpt_pf_if = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_xcpt_ae_if = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_xcpt_ma_if = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_bp_debug_if = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_bp_xcpt_if = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_0_bits_ppred_busy = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_1_bits_ppred_busy = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_2_bits_ppred_busy = 1'h0;\t// @[core.scala:51:7]\n wire io_lsu_clr_unsafe_0_valid = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_tlb_req_valid = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_tlb_req_bits_valid = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_tlb_req_bits_bits_need_gpa = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_tlb_req_bits_bits_vstage1 = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_tlb_req_bits_bits_stage2 = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_tlb_resp_bits_fragmented_superpage = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_tlb_status_mbe = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_tlb_status_sbe = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_tlb_status_sd_rv32 = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_tlb_status_ube = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_tlb_status_upie = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_tlb_status_hie = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_tlb_status_uie = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_tlb_hstatus_vtsr = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_tlb_hstatus_vtw = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_tlb_hstatus_vtvm = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_tlb_hstatus_hu = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_tlb_hstatus_spvp = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_tlb_hstatus_spv = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_tlb_hstatus_gva = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_tlb_hstatus_vsbe = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_tlb_gstatus_debug = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_tlb_gstatus_cease = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_tlb_gstatus_wfi = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_tlb_gstatus_dv = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_tlb_gstatus_v = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_tlb_gstatus_sd = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_tlb_gstatus_mpv = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_tlb_gstatus_gva = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_tlb_gstatus_mbe = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_tlb_gstatus_sbe = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_tlb_gstatus_sd_rv32 = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_tlb_gstatus_tsr = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_tlb_gstatus_tw = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_tlb_gstatus_tvm = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_tlb_gstatus_mxr = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_tlb_gstatus_sum = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_tlb_gstatus_mprv = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_tlb_gstatus_spp = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_tlb_gstatus_mpie = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_tlb_gstatus_ube = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_tlb_gstatus_spie = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_tlb_gstatus_upie = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_tlb_gstatus_mie = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_tlb_gstatus_hie = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_tlb_gstatus_sie = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_tlb_gstatus_uie = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_tlb_customCSRs_csrs_0_ren = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_tlb_customCSRs_csrs_0_wen = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_tlb_customCSRs_csrs_0_stall = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_tlb_customCSRs_csrs_0_set = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_tlb_customCSRs_csrs_1_ren = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_tlb_customCSRs_csrs_1_wen = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_tlb_customCSRs_csrs_1_stall = 1'h0;\t// @[core.scala:51:7]\n wire io_ptw_tlb_customCSRs_csrs_1_set = 1'h0;\t// @[core.scala:51:7]\n wire io_trace_insns_0_valid = 1'h0;\t// @[core.scala:51:7]\n wire io_trace_insns_0_exception = 1'h0;\t// @[core.scala:51:7]\n wire io_trace_insns_0_interrupt = 1'h0;\t// @[core.scala:51:7]\n wire io_trace_insns_1_valid = 1'h0;\t// @[core.scala:51:7]\n wire io_trace_insns_1_exception = 1'h0;\t// @[core.scala:51:7]\n wire io_trace_insns_1_interrupt = 1'h0;\t// @[core.scala:51:7]\n wire io_trace_insns_2_valid = 1'h0;\t// @[core.scala:51:7]\n wire io_trace_insns_2_exception = 1'h0;\t// @[core.scala:51:7]\n wire io_trace_insns_2_interrupt = 1'h0;\t// @[core.scala:51:7]\n wire int_iss_wakeups_1_bits_predicated = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_1_bits_fflags_valid = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_1_bits_fflags_bits_uop_is_rvc = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_1_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_1_bits_fflags_bits_uop_ctrl_is_load = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_1_bits_fflags_bits_uop_ctrl_is_sta = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_1_bits_fflags_bits_uop_ctrl_is_std = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_1_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_1_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_1_bits_fflags_bits_uop_is_br = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_1_bits_fflags_bits_uop_is_jalr = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_1_bits_fflags_bits_uop_is_jal = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_1_bits_fflags_bits_uop_is_sfb = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_1_bits_fflags_bits_uop_edge_inst = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_1_bits_fflags_bits_uop_taken = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_1_bits_fflags_bits_uop_prs1_busy = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_1_bits_fflags_bits_uop_prs2_busy = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_1_bits_fflags_bits_uop_prs3_busy = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_1_bits_fflags_bits_uop_ppred_busy = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_1_bits_fflags_bits_uop_exception = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_1_bits_fflags_bits_uop_bypassable = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_1_bits_fflags_bits_uop_mem_signed = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_1_bits_fflags_bits_uop_is_fence = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_1_bits_fflags_bits_uop_is_fencei = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_1_bits_fflags_bits_uop_is_amo = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_1_bits_fflags_bits_uop_uses_ldq = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_1_bits_fflags_bits_uop_uses_stq = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_1_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_1_bits_fflags_bits_uop_is_unique = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_1_bits_fflags_bits_uop_flush_on_commit = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_1_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_1_bits_fflags_bits_uop_ldst_val = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_1_bits_fflags_bits_uop_frs3_en = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_1_bits_fflags_bits_uop_fp_val = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_1_bits_fflags_bits_uop_fp_single = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_1_bits_fflags_bits_uop_xcpt_pf_if = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_1_bits_fflags_bits_uop_xcpt_ae_if = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_1_bits_fflags_bits_uop_xcpt_ma_if = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_1_bits_fflags_bits_uop_bp_debug_if = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_1_bits_fflags_bits_uop_bp_xcpt_if = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_2_bits_predicated = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_2_bits_fflags_valid = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_2_bits_fflags_bits_uop_is_rvc = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_2_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_2_bits_fflags_bits_uop_ctrl_is_load = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_2_bits_fflags_bits_uop_ctrl_is_sta = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_2_bits_fflags_bits_uop_ctrl_is_std = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_2_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_2_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_2_bits_fflags_bits_uop_is_br = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_2_bits_fflags_bits_uop_is_jalr = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_2_bits_fflags_bits_uop_is_jal = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_2_bits_fflags_bits_uop_is_sfb = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_2_bits_fflags_bits_uop_edge_inst = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_2_bits_fflags_bits_uop_taken = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_2_bits_fflags_bits_uop_prs1_busy = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_2_bits_fflags_bits_uop_prs2_busy = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_2_bits_fflags_bits_uop_prs3_busy = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_2_bits_fflags_bits_uop_ppred_busy = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_2_bits_fflags_bits_uop_exception = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_2_bits_fflags_bits_uop_bypassable = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_2_bits_fflags_bits_uop_mem_signed = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_2_bits_fflags_bits_uop_is_fence = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_2_bits_fflags_bits_uop_is_fencei = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_2_bits_fflags_bits_uop_is_amo = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_2_bits_fflags_bits_uop_uses_ldq = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_2_bits_fflags_bits_uop_uses_stq = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_2_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_2_bits_fflags_bits_uop_is_unique = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_2_bits_fflags_bits_uop_flush_on_commit = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_2_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_2_bits_fflags_bits_uop_ldst_val = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_2_bits_fflags_bits_uop_frs3_en = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_2_bits_fflags_bits_uop_fp_val = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_2_bits_fflags_bits_uop_fp_single = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_2_bits_fflags_bits_uop_xcpt_pf_if = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_2_bits_fflags_bits_uop_xcpt_ae_if = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_2_bits_fflags_bits_uop_xcpt_ma_if = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_2_bits_fflags_bits_uop_bp_debug_if = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_2_bits_fflags_bits_uop_bp_xcpt_if = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_3_bits_predicated = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_3_bits_fflags_valid = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_3_bits_fflags_bits_uop_is_rvc = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_3_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_3_bits_fflags_bits_uop_ctrl_is_load = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_3_bits_fflags_bits_uop_ctrl_is_sta = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_3_bits_fflags_bits_uop_ctrl_is_std = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_3_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_3_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_3_bits_fflags_bits_uop_is_br = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_3_bits_fflags_bits_uop_is_jalr = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_3_bits_fflags_bits_uop_is_jal = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_3_bits_fflags_bits_uop_is_sfb = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_3_bits_fflags_bits_uop_edge_inst = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_3_bits_fflags_bits_uop_taken = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_3_bits_fflags_bits_uop_prs1_busy = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_3_bits_fflags_bits_uop_prs2_busy = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_3_bits_fflags_bits_uop_prs3_busy = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_3_bits_fflags_bits_uop_ppred_busy = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_3_bits_fflags_bits_uop_exception = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_3_bits_fflags_bits_uop_bypassable = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_3_bits_fflags_bits_uop_mem_signed = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_3_bits_fflags_bits_uop_is_fence = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_3_bits_fflags_bits_uop_is_fencei = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_3_bits_fflags_bits_uop_is_amo = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_3_bits_fflags_bits_uop_uses_ldq = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_3_bits_fflags_bits_uop_uses_stq = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_3_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_3_bits_fflags_bits_uop_is_unique = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_3_bits_fflags_bits_uop_flush_on_commit = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_3_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_3_bits_fflags_bits_uop_ldst_val = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_3_bits_fflags_bits_uop_frs3_en = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_3_bits_fflags_bits_uop_fp_val = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_3_bits_fflags_bits_uop_fp_single = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_3_bits_fflags_bits_uop_xcpt_pf_if = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_3_bits_fflags_bits_uop_xcpt_ae_if = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_3_bits_fflags_bits_uop_xcpt_ma_if = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_3_bits_fflags_bits_uop_bp_debug_if = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_3_bits_fflags_bits_uop_bp_xcpt_if = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_4_bits_predicated = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_4_bits_fflags_valid = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_4_bits_fflags_bits_uop_is_rvc = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_4_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_4_bits_fflags_bits_uop_ctrl_is_load = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_4_bits_fflags_bits_uop_ctrl_is_sta = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_4_bits_fflags_bits_uop_ctrl_is_std = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_4_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_4_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_4_bits_fflags_bits_uop_is_br = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_4_bits_fflags_bits_uop_is_jalr = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_4_bits_fflags_bits_uop_is_jal = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_4_bits_fflags_bits_uop_is_sfb = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_4_bits_fflags_bits_uop_edge_inst = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_4_bits_fflags_bits_uop_taken = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_4_bits_fflags_bits_uop_prs1_busy = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_4_bits_fflags_bits_uop_prs2_busy = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_4_bits_fflags_bits_uop_prs3_busy = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_4_bits_fflags_bits_uop_ppred_busy = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_4_bits_fflags_bits_uop_exception = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_4_bits_fflags_bits_uop_bypassable = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_4_bits_fflags_bits_uop_mem_signed = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_4_bits_fflags_bits_uop_is_fence = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_4_bits_fflags_bits_uop_is_fencei = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_4_bits_fflags_bits_uop_is_amo = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_4_bits_fflags_bits_uop_uses_ldq = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_4_bits_fflags_bits_uop_uses_stq = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_4_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_4_bits_fflags_bits_uop_is_unique = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_4_bits_fflags_bits_uop_flush_on_commit = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_4_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_4_bits_fflags_bits_uop_ldst_val = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_4_bits_fflags_bits_uop_frs3_en = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_4_bits_fflags_bits_uop_fp_val = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_4_bits_fflags_bits_uop_fp_single = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_4_bits_fflags_bits_uop_xcpt_pf_if = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_4_bits_fflags_bits_uop_xcpt_ae_if = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_4_bits_fflags_bits_uop_xcpt_ma_if = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_4_bits_fflags_bits_uop_bp_debug_if = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_4_bits_fflags_bits_uop_bp_xcpt_if = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_5_bits_predicated = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_5_bits_fflags_valid = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_5_bits_fflags_bits_uop_is_rvc = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_5_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_5_bits_fflags_bits_uop_ctrl_is_load = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_5_bits_fflags_bits_uop_ctrl_is_sta = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_5_bits_fflags_bits_uop_ctrl_is_std = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_5_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_5_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_5_bits_fflags_bits_uop_is_br = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_5_bits_fflags_bits_uop_is_jalr = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_5_bits_fflags_bits_uop_is_jal = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_5_bits_fflags_bits_uop_is_sfb = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_5_bits_fflags_bits_uop_edge_inst = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_5_bits_fflags_bits_uop_taken = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_5_bits_fflags_bits_uop_prs1_busy = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_5_bits_fflags_bits_uop_prs2_busy = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_5_bits_fflags_bits_uop_prs3_busy = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_5_bits_fflags_bits_uop_ppred_busy = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_5_bits_fflags_bits_uop_exception = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_5_bits_fflags_bits_uop_bypassable = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_5_bits_fflags_bits_uop_mem_signed = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_5_bits_fflags_bits_uop_is_fence = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_5_bits_fflags_bits_uop_is_fencei = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_5_bits_fflags_bits_uop_is_amo = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_5_bits_fflags_bits_uop_uses_ldq = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_5_bits_fflags_bits_uop_uses_stq = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_5_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_5_bits_fflags_bits_uop_is_unique = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_5_bits_fflags_bits_uop_flush_on_commit = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_5_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_5_bits_fflags_bits_uop_ldst_val = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_5_bits_fflags_bits_uop_frs3_en = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_5_bits_fflags_bits_uop_fp_val = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_5_bits_fflags_bits_uop_fp_single = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_5_bits_fflags_bits_uop_xcpt_pf_if = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_5_bits_fflags_bits_uop_xcpt_ae_if = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_5_bits_fflags_bits_uop_xcpt_ma_if = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_5_bits_fflags_bits_uop_bp_debug_if = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_5_bits_fflags_bits_uop_bp_xcpt_if = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_6_bits_predicated = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_6_bits_fflags_valid = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_6_bits_fflags_bits_uop_is_rvc = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_6_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_6_bits_fflags_bits_uop_ctrl_is_load = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_6_bits_fflags_bits_uop_ctrl_is_sta = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_6_bits_fflags_bits_uop_ctrl_is_std = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_6_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_6_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_6_bits_fflags_bits_uop_is_br = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_6_bits_fflags_bits_uop_is_jalr = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_6_bits_fflags_bits_uop_is_jal = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_6_bits_fflags_bits_uop_is_sfb = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_6_bits_fflags_bits_uop_edge_inst = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_6_bits_fflags_bits_uop_taken = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_6_bits_fflags_bits_uop_prs1_busy = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_6_bits_fflags_bits_uop_prs2_busy = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_6_bits_fflags_bits_uop_prs3_busy = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_6_bits_fflags_bits_uop_ppred_busy = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_6_bits_fflags_bits_uop_exception = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_6_bits_fflags_bits_uop_bypassable = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_6_bits_fflags_bits_uop_mem_signed = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_6_bits_fflags_bits_uop_is_fence = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_6_bits_fflags_bits_uop_is_fencei = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_6_bits_fflags_bits_uop_is_amo = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_6_bits_fflags_bits_uop_uses_ldq = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_6_bits_fflags_bits_uop_uses_stq = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_6_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_6_bits_fflags_bits_uop_is_unique = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_6_bits_fflags_bits_uop_flush_on_commit = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_6_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_6_bits_fflags_bits_uop_ldst_val = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_6_bits_fflags_bits_uop_frs3_en = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_6_bits_fflags_bits_uop_fp_val = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_6_bits_fflags_bits_uop_fp_single = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_6_bits_fflags_bits_uop_xcpt_pf_if = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_6_bits_fflags_bits_uop_xcpt_ae_if = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_6_bits_fflags_bits_uop_xcpt_ma_if = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_6_bits_fflags_bits_uop_bp_debug_if = 1'h0;\t// @[core.scala:147:30]\n wire int_iss_wakeups_6_bits_fflags_bits_uop_bp_xcpt_if = 1'h0;\t// @[core.scala:147:30]\n wire int_ren_wakeups_1_bits_predicated = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_1_bits_fflags_valid = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_1_bits_fflags_bits_uop_is_rvc = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_1_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_1_bits_fflags_bits_uop_ctrl_is_load = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_1_bits_fflags_bits_uop_ctrl_is_sta = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_1_bits_fflags_bits_uop_ctrl_is_std = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_1_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_1_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_1_bits_fflags_bits_uop_is_br = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_1_bits_fflags_bits_uop_is_jalr = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_1_bits_fflags_bits_uop_is_jal = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_1_bits_fflags_bits_uop_is_sfb = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_1_bits_fflags_bits_uop_edge_inst = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_1_bits_fflags_bits_uop_taken = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_1_bits_fflags_bits_uop_prs1_busy = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_1_bits_fflags_bits_uop_prs2_busy = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_1_bits_fflags_bits_uop_prs3_busy = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_1_bits_fflags_bits_uop_ppred_busy = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_1_bits_fflags_bits_uop_exception = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_1_bits_fflags_bits_uop_bypassable = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_1_bits_fflags_bits_uop_mem_signed = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_1_bits_fflags_bits_uop_is_fence = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_1_bits_fflags_bits_uop_is_fencei = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_1_bits_fflags_bits_uop_is_amo = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_1_bits_fflags_bits_uop_uses_ldq = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_1_bits_fflags_bits_uop_uses_stq = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_1_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_1_bits_fflags_bits_uop_is_unique = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_1_bits_fflags_bits_uop_flush_on_commit = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_1_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_1_bits_fflags_bits_uop_ldst_val = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_1_bits_fflags_bits_uop_frs3_en = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_1_bits_fflags_bits_uop_fp_val = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_1_bits_fflags_bits_uop_fp_single = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_1_bits_fflags_bits_uop_xcpt_pf_if = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_1_bits_fflags_bits_uop_xcpt_ae_if = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_1_bits_fflags_bits_uop_xcpt_ma_if = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_1_bits_fflags_bits_uop_bp_debug_if = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_1_bits_fflags_bits_uop_bp_xcpt_if = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_2_bits_predicated = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_2_bits_fflags_valid = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_2_bits_fflags_bits_uop_is_rvc = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_2_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_2_bits_fflags_bits_uop_ctrl_is_load = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_2_bits_fflags_bits_uop_ctrl_is_sta = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_2_bits_fflags_bits_uop_ctrl_is_std = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_2_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_2_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_2_bits_fflags_bits_uop_is_br = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_2_bits_fflags_bits_uop_is_jalr = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_2_bits_fflags_bits_uop_is_jal = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_2_bits_fflags_bits_uop_is_sfb = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_2_bits_fflags_bits_uop_edge_inst = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_2_bits_fflags_bits_uop_taken = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_2_bits_fflags_bits_uop_prs1_busy = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_2_bits_fflags_bits_uop_prs2_busy = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_2_bits_fflags_bits_uop_prs3_busy = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_2_bits_fflags_bits_uop_ppred_busy = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_2_bits_fflags_bits_uop_exception = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_2_bits_fflags_bits_uop_bypassable = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_2_bits_fflags_bits_uop_mem_signed = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_2_bits_fflags_bits_uop_is_fence = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_2_bits_fflags_bits_uop_is_fencei = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_2_bits_fflags_bits_uop_is_amo = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_2_bits_fflags_bits_uop_uses_ldq = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_2_bits_fflags_bits_uop_uses_stq = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_2_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_2_bits_fflags_bits_uop_is_unique = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_2_bits_fflags_bits_uop_flush_on_commit = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_2_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_2_bits_fflags_bits_uop_ldst_val = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_2_bits_fflags_bits_uop_frs3_en = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_2_bits_fflags_bits_uop_fp_val = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_2_bits_fflags_bits_uop_fp_single = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_2_bits_fflags_bits_uop_xcpt_pf_if = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_2_bits_fflags_bits_uop_xcpt_ae_if = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_2_bits_fflags_bits_uop_xcpt_ma_if = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_2_bits_fflags_bits_uop_bp_debug_if = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_2_bits_fflags_bits_uop_bp_xcpt_if = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_3_bits_predicated = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_3_bits_fflags_valid = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_3_bits_fflags_bits_uop_is_rvc = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_3_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_3_bits_fflags_bits_uop_ctrl_is_load = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_3_bits_fflags_bits_uop_ctrl_is_sta = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_3_bits_fflags_bits_uop_ctrl_is_std = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_3_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_3_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_3_bits_fflags_bits_uop_is_br = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_3_bits_fflags_bits_uop_is_jalr = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_3_bits_fflags_bits_uop_is_jal = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_3_bits_fflags_bits_uop_is_sfb = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_3_bits_fflags_bits_uop_edge_inst = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_3_bits_fflags_bits_uop_taken = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_3_bits_fflags_bits_uop_prs1_busy = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_3_bits_fflags_bits_uop_prs2_busy = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_3_bits_fflags_bits_uop_prs3_busy = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_3_bits_fflags_bits_uop_ppred_busy = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_3_bits_fflags_bits_uop_exception = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_3_bits_fflags_bits_uop_bypassable = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_3_bits_fflags_bits_uop_mem_signed = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_3_bits_fflags_bits_uop_is_fence = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_3_bits_fflags_bits_uop_is_fencei = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_3_bits_fflags_bits_uop_is_amo = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_3_bits_fflags_bits_uop_uses_ldq = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_3_bits_fflags_bits_uop_uses_stq = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_3_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_3_bits_fflags_bits_uop_is_unique = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_3_bits_fflags_bits_uop_flush_on_commit = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_3_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_3_bits_fflags_bits_uop_ldst_val = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_3_bits_fflags_bits_uop_frs3_en = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_3_bits_fflags_bits_uop_fp_val = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_3_bits_fflags_bits_uop_fp_single = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_3_bits_fflags_bits_uop_xcpt_pf_if = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_3_bits_fflags_bits_uop_xcpt_ae_if = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_3_bits_fflags_bits_uop_xcpt_ma_if = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_3_bits_fflags_bits_uop_bp_debug_if = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_3_bits_fflags_bits_uop_bp_xcpt_if = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_4_bits_predicated = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_4_bits_fflags_valid = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_4_bits_fflags_bits_uop_is_rvc = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_4_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_4_bits_fflags_bits_uop_ctrl_is_load = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_4_bits_fflags_bits_uop_ctrl_is_sta = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_4_bits_fflags_bits_uop_ctrl_is_std = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_4_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_4_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_4_bits_fflags_bits_uop_is_br = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_4_bits_fflags_bits_uop_is_jalr = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_4_bits_fflags_bits_uop_is_jal = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_4_bits_fflags_bits_uop_is_sfb = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_4_bits_fflags_bits_uop_edge_inst = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_4_bits_fflags_bits_uop_taken = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_4_bits_fflags_bits_uop_prs1_busy = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_4_bits_fflags_bits_uop_prs2_busy = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_4_bits_fflags_bits_uop_prs3_busy = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_4_bits_fflags_bits_uop_ppred_busy = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_4_bits_fflags_bits_uop_exception = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_4_bits_fflags_bits_uop_bypassable = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_4_bits_fflags_bits_uop_mem_signed = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_4_bits_fflags_bits_uop_is_fence = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_4_bits_fflags_bits_uop_is_fencei = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_4_bits_fflags_bits_uop_is_amo = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_4_bits_fflags_bits_uop_uses_ldq = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_4_bits_fflags_bits_uop_uses_stq = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_4_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_4_bits_fflags_bits_uop_is_unique = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_4_bits_fflags_bits_uop_flush_on_commit = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_4_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_4_bits_fflags_bits_uop_ldst_val = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_4_bits_fflags_bits_uop_frs3_en = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_4_bits_fflags_bits_uop_fp_val = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_4_bits_fflags_bits_uop_fp_single = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_4_bits_fflags_bits_uop_xcpt_pf_if = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_4_bits_fflags_bits_uop_xcpt_ae_if = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_4_bits_fflags_bits_uop_xcpt_ma_if = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_4_bits_fflags_bits_uop_bp_debug_if = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_4_bits_fflags_bits_uop_bp_xcpt_if = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_5_bits_predicated = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_5_bits_fflags_valid = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_5_bits_fflags_bits_uop_is_rvc = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_5_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_5_bits_fflags_bits_uop_ctrl_is_load = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_5_bits_fflags_bits_uop_ctrl_is_sta = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_5_bits_fflags_bits_uop_ctrl_is_std = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_5_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_5_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_5_bits_fflags_bits_uop_is_br = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_5_bits_fflags_bits_uop_is_jalr = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_5_bits_fflags_bits_uop_is_jal = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_5_bits_fflags_bits_uop_is_sfb = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_5_bits_fflags_bits_uop_edge_inst = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_5_bits_fflags_bits_uop_taken = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_5_bits_fflags_bits_uop_prs1_busy = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_5_bits_fflags_bits_uop_prs2_busy = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_5_bits_fflags_bits_uop_prs3_busy = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_5_bits_fflags_bits_uop_ppred_busy = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_5_bits_fflags_bits_uop_exception = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_5_bits_fflags_bits_uop_bypassable = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_5_bits_fflags_bits_uop_mem_signed = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_5_bits_fflags_bits_uop_is_fence = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_5_bits_fflags_bits_uop_is_fencei = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_5_bits_fflags_bits_uop_is_amo = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_5_bits_fflags_bits_uop_uses_ldq = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_5_bits_fflags_bits_uop_uses_stq = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_5_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_5_bits_fflags_bits_uop_is_unique = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_5_bits_fflags_bits_uop_flush_on_commit = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_5_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_5_bits_fflags_bits_uop_ldst_val = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_5_bits_fflags_bits_uop_frs3_en = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_5_bits_fflags_bits_uop_fp_val = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_5_bits_fflags_bits_uop_fp_single = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_5_bits_fflags_bits_uop_xcpt_pf_if = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_5_bits_fflags_bits_uop_xcpt_ae_if = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_5_bits_fflags_bits_uop_xcpt_ma_if = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_5_bits_fflags_bits_uop_bp_debug_if = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_5_bits_fflags_bits_uop_bp_xcpt_if = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_6_bits_predicated = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_6_bits_fflags_valid = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_6_bits_fflags_bits_uop_is_rvc = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_6_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_6_bits_fflags_bits_uop_ctrl_is_load = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_6_bits_fflags_bits_uop_ctrl_is_sta = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_6_bits_fflags_bits_uop_ctrl_is_std = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_6_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_6_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_6_bits_fflags_bits_uop_is_br = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_6_bits_fflags_bits_uop_is_jalr = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_6_bits_fflags_bits_uop_is_jal = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_6_bits_fflags_bits_uop_is_sfb = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_6_bits_fflags_bits_uop_edge_inst = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_6_bits_fflags_bits_uop_taken = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_6_bits_fflags_bits_uop_prs1_busy = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_6_bits_fflags_bits_uop_prs2_busy = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_6_bits_fflags_bits_uop_prs3_busy = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_6_bits_fflags_bits_uop_ppred_busy = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_6_bits_fflags_bits_uop_exception = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_6_bits_fflags_bits_uop_bypassable = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_6_bits_fflags_bits_uop_mem_signed = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_6_bits_fflags_bits_uop_is_fence = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_6_bits_fflags_bits_uop_is_fencei = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_6_bits_fflags_bits_uop_is_amo = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_6_bits_fflags_bits_uop_uses_ldq = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_6_bits_fflags_bits_uop_uses_stq = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_6_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_6_bits_fflags_bits_uop_is_unique = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_6_bits_fflags_bits_uop_flush_on_commit = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_6_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_6_bits_fflags_bits_uop_ldst_val = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_6_bits_fflags_bits_uop_frs3_en = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_6_bits_fflags_bits_uop_fp_val = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_6_bits_fflags_bits_uop_fp_single = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_6_bits_fflags_bits_uop_xcpt_pf_if = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_6_bits_fflags_bits_uop_xcpt_ae_if = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_6_bits_fflags_bits_uop_xcpt_ma_if = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_6_bits_fflags_bits_uop_bp_debug_if = 1'h0;\t// @[core.scala:148:30]\n wire int_ren_wakeups_6_bits_fflags_bits_uop_bp_xcpt_if = 1'h0;\t// @[core.scala:148:30]\n wire pred_wakeup_valid = 1'h0;\t// @[core.scala:149:26]\n wire pred_wakeup_bits_data = 1'h0;\t// @[core.scala:149:26]\n wire pred_wakeup_bits_predicated = 1'h0;\t// @[core.scala:149:26]\n wire pred_wakeup_bits_fflags_valid = 1'h0;\t// @[core.scala:149:26]\n wire pred_wakeup_bits_fflags_bits_uop_is_rvc = 1'h0;\t// @[core.scala:149:26]\n wire pred_wakeup_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0;\t// @[core.scala:149:26]\n wire pred_wakeup_bits_fflags_bits_uop_ctrl_is_load = 1'h0;\t// @[core.scala:149:26]\n wire pred_wakeup_bits_fflags_bits_uop_ctrl_is_sta = 1'h0;\t// @[core.scala:149:26]\n wire pred_wakeup_bits_fflags_bits_uop_ctrl_is_std = 1'h0;\t// @[core.scala:149:26]\n wire pred_wakeup_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0;\t// @[core.scala:149:26]\n wire pred_wakeup_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0;\t// @[core.scala:149:26]\n wire pred_wakeup_bits_fflags_bits_uop_is_br = 1'h0;\t// @[core.scala:149:26]\n wire pred_wakeup_bits_fflags_bits_uop_is_jalr = 1'h0;\t// @[core.scala:149:26]\n wire pred_wakeup_bits_fflags_bits_uop_is_jal = 1'h0;\t// @[core.scala:149:26]\n wire pred_wakeup_bits_fflags_bits_uop_is_sfb = 1'h0;\t// @[core.scala:149:26]\n wire pred_wakeup_bits_fflags_bits_uop_edge_inst = 1'h0;\t// @[core.scala:149:26]\n wire pred_wakeup_bits_fflags_bits_uop_taken = 1'h0;\t// @[core.scala:149:26]\n wire pred_wakeup_bits_fflags_bits_uop_prs1_busy = 1'h0;\t// @[core.scala:149:26]\n wire pred_wakeup_bits_fflags_bits_uop_prs2_busy = 1'h0;\t// @[core.scala:149:26]\n wire pred_wakeup_bits_fflags_bits_uop_prs3_busy = 1'h0;\t// @[core.scala:149:26]\n wire pred_wakeup_bits_fflags_bits_uop_ppred_busy = 1'h0;\t// @[core.scala:149:26]\n wire pred_wakeup_bits_fflags_bits_uop_exception = 1'h0;\t// @[core.scala:149:26]\n wire pred_wakeup_bits_fflags_bits_uop_bypassable = 1'h0;\t// @[core.scala:149:26]\n wire pred_wakeup_bits_fflags_bits_uop_mem_signed = 1'h0;\t// @[core.scala:149:26]\n wire pred_wakeup_bits_fflags_bits_uop_is_fence = 1'h0;\t// @[core.scala:149:26]\n wire pred_wakeup_bits_fflags_bits_uop_is_fencei = 1'h0;\t// @[core.scala:149:26]\n wire pred_wakeup_bits_fflags_bits_uop_is_amo = 1'h0;\t// @[core.scala:149:26]\n wire pred_wakeup_bits_fflags_bits_uop_uses_ldq = 1'h0;\t// @[core.scala:149:26]\n wire pred_wakeup_bits_fflags_bits_uop_uses_stq = 1'h0;\t// @[core.scala:149:26]\n wire pred_wakeup_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0;\t// @[core.scala:149:26]\n wire pred_wakeup_bits_fflags_bits_uop_is_unique = 1'h0;\t// @[core.scala:149:26]\n wire pred_wakeup_bits_fflags_bits_uop_flush_on_commit = 1'h0;\t// @[core.scala:149:26]\n wire pred_wakeup_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0;\t// @[core.scala:149:26]\n wire pred_wakeup_bits_fflags_bits_uop_ldst_val = 1'h0;\t// @[core.scala:149:26]\n wire pred_wakeup_bits_fflags_bits_uop_frs3_en = 1'h0;\t// @[core.scala:149:26]\n wire pred_wakeup_bits_fflags_bits_uop_fp_val = 1'h0;\t// @[core.scala:149:26]\n wire pred_wakeup_bits_fflags_bits_uop_fp_single = 1'h0;\t// @[core.scala:149:26]\n wire pred_wakeup_bits_fflags_bits_uop_xcpt_pf_if = 1'h0;\t// @[core.scala:149:26]\n wire pred_wakeup_bits_fflags_bits_uop_xcpt_ae_if = 1'h0;\t// @[core.scala:149:26]\n wire pred_wakeup_bits_fflags_bits_uop_xcpt_ma_if = 1'h0;\t// @[core.scala:149:26]\n wire pred_wakeup_bits_fflags_bits_uop_bp_debug_if = 1'h0;\t// @[core.scala:149:26]\n wire pred_wakeup_bits_fflags_bits_uop_bp_xcpt_if = 1'h0;\t// @[core.scala:149:26]\n wire dec_uops_0_ctrl_fcn_dw = 1'h0;\t// @[core.scala:158:24]\n wire dec_uops_0_ctrl_is_load = 1'h0;\t// @[core.scala:158:24]\n wire dec_uops_0_ctrl_is_sta = 1'h0;\t// @[core.scala:158:24]\n wire dec_uops_0_ctrl_is_std = 1'h0;\t// @[core.scala:158:24]\n wire dec_uops_0_iw_p1_poisoned = 1'h0;\t// @[core.scala:158:24]\n wire dec_uops_0_iw_p2_poisoned = 1'h0;\t// @[core.scala:158:24]\n wire dec_uops_0_prs1_busy = 1'h0;\t// @[core.scala:158:24]\n wire dec_uops_0_prs2_busy = 1'h0;\t// @[core.scala:158:24]\n wire dec_uops_0_prs3_busy = 1'h0;\t// @[core.scala:158:24]\n wire dec_uops_0_ppred_busy = 1'h0;\t// @[core.scala:158:24]\n wire dec_uops_0_ldst_is_rs1 = 1'h0;\t// @[core.scala:158:24]\n wire dec_uops_0_xcpt_ma_if = 1'h0;\t// @[core.scala:158:24]\n wire dec_uops_1_ctrl_fcn_dw = 1'h0;\t// @[core.scala:158:24]\n wire dec_uops_1_ctrl_is_load = 1'h0;\t// @[core.scala:158:24]\n wire dec_uops_1_ctrl_is_sta = 1'h0;\t// @[core.scala:158:24]\n wire dec_uops_1_ctrl_is_std = 1'h0;\t// @[core.scala:158:24]\n wire dec_uops_1_iw_p1_poisoned = 1'h0;\t// @[core.scala:158:24]\n wire dec_uops_1_iw_p2_poisoned = 1'h0;\t// @[core.scala:158:24]\n wire dec_uops_1_prs1_busy = 1'h0;\t// @[core.scala:158:24]\n wire dec_uops_1_prs2_busy = 1'h0;\t// @[core.scala:158:24]\n wire dec_uops_1_prs3_busy = 1'h0;\t// @[core.scala:158:24]\n wire dec_uops_1_ppred_busy = 1'h0;\t// @[core.scala:158:24]\n wire dec_uops_1_ldst_is_rs1 = 1'h0;\t// @[core.scala:158:24]\n wire dec_uops_1_xcpt_ma_if = 1'h0;\t// @[core.scala:158:24]\n wire dec_uops_2_ctrl_fcn_dw = 1'h0;\t// @[core.scala:158:24]\n wire dec_uops_2_ctrl_is_load = 1'h0;\t// @[core.scala:158:24]\n wire dec_uops_2_ctrl_is_sta = 1'h0;\t// @[core.scala:158:24]\n wire dec_uops_2_ctrl_is_std = 1'h0;\t// @[core.scala:158:24]\n wire dec_uops_2_iw_p1_poisoned = 1'h0;\t// @[core.scala:158:24]\n wire dec_uops_2_iw_p2_poisoned = 1'h0;\t// @[core.scala:158:24]\n wire dec_uops_2_prs1_busy = 1'h0;\t// @[core.scala:158:24]\n wire dec_uops_2_prs2_busy = 1'h0;\t// @[core.scala:158:24]\n wire dec_uops_2_prs3_busy = 1'h0;\t// @[core.scala:158:24]\n wire dec_uops_2_ppred_busy = 1'h0;\t// @[core.scala:158:24]\n wire dec_uops_2_ldst_is_rs1 = 1'h0;\t// @[core.scala:158:24]\n wire dec_uops_2_xcpt_ma_if = 1'h0;\t// @[core.scala:158:24]\n wire dis_uops_0_ppred_busy = 1'h0;\t// @[core.scala:167:24]\n wire dis_uops_1_ppred_busy = 1'h0;\t// @[core.scala:167:24]\n wire dis_uops_2_ppred_busy = 1'h0;\t// @[core.scala:167:24]\n wire bypasses_0_bits_predicated = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_0_bits_fflags_valid = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_0_bits_fflags_bits_uop_is_rvc = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_0_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_0_bits_fflags_bits_uop_ctrl_is_load = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_0_bits_fflags_bits_uop_ctrl_is_sta = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_0_bits_fflags_bits_uop_ctrl_is_std = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_0_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_0_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_0_bits_fflags_bits_uop_is_br = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_0_bits_fflags_bits_uop_is_jalr = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_0_bits_fflags_bits_uop_is_jal = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_0_bits_fflags_bits_uop_is_sfb = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_0_bits_fflags_bits_uop_edge_inst = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_0_bits_fflags_bits_uop_taken = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_0_bits_fflags_bits_uop_prs1_busy = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_0_bits_fflags_bits_uop_prs2_busy = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_0_bits_fflags_bits_uop_prs3_busy = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_0_bits_fflags_bits_uop_ppred_busy = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_0_bits_fflags_bits_uop_exception = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_0_bits_fflags_bits_uop_bypassable = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_0_bits_fflags_bits_uop_mem_signed = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_0_bits_fflags_bits_uop_is_fence = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_0_bits_fflags_bits_uop_is_fencei = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_0_bits_fflags_bits_uop_is_amo = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_0_bits_fflags_bits_uop_uses_ldq = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_0_bits_fflags_bits_uop_uses_stq = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_0_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_0_bits_fflags_bits_uop_is_unique = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_0_bits_fflags_bits_uop_flush_on_commit = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_0_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_0_bits_fflags_bits_uop_ldst_val = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_0_bits_fflags_bits_uop_frs3_en = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_0_bits_fflags_bits_uop_fp_val = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_0_bits_fflags_bits_uop_fp_single = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_0_bits_fflags_bits_uop_xcpt_pf_if = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_0_bits_fflags_bits_uop_xcpt_ae_if = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_0_bits_fflags_bits_uop_xcpt_ma_if = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_0_bits_fflags_bits_uop_bp_debug_if = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_0_bits_fflags_bits_uop_bp_xcpt_if = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_1_bits_predicated = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_1_bits_fflags_valid = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_1_bits_fflags_bits_uop_is_rvc = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_1_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_1_bits_fflags_bits_uop_ctrl_is_load = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_1_bits_fflags_bits_uop_ctrl_is_sta = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_1_bits_fflags_bits_uop_ctrl_is_std = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_1_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_1_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_1_bits_fflags_bits_uop_is_br = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_1_bits_fflags_bits_uop_is_jalr = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_1_bits_fflags_bits_uop_is_jal = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_1_bits_fflags_bits_uop_is_sfb = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_1_bits_fflags_bits_uop_edge_inst = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_1_bits_fflags_bits_uop_taken = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_1_bits_fflags_bits_uop_prs1_busy = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_1_bits_fflags_bits_uop_prs2_busy = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_1_bits_fflags_bits_uop_prs3_busy = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_1_bits_fflags_bits_uop_ppred_busy = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_1_bits_fflags_bits_uop_exception = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_1_bits_fflags_bits_uop_bypassable = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_1_bits_fflags_bits_uop_mem_signed = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_1_bits_fflags_bits_uop_is_fence = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_1_bits_fflags_bits_uop_is_fencei = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_1_bits_fflags_bits_uop_is_amo = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_1_bits_fflags_bits_uop_uses_ldq = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_1_bits_fflags_bits_uop_uses_stq = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_1_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_1_bits_fflags_bits_uop_is_unique = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_1_bits_fflags_bits_uop_flush_on_commit = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_1_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_1_bits_fflags_bits_uop_ldst_val = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_1_bits_fflags_bits_uop_frs3_en = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_1_bits_fflags_bits_uop_fp_val = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_1_bits_fflags_bits_uop_fp_single = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_1_bits_fflags_bits_uop_xcpt_pf_if = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_1_bits_fflags_bits_uop_xcpt_ae_if = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_1_bits_fflags_bits_uop_xcpt_ma_if = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_1_bits_fflags_bits_uop_bp_debug_if = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_1_bits_fflags_bits_uop_bp_xcpt_if = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_2_bits_predicated = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_2_bits_fflags_valid = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_2_bits_fflags_bits_uop_is_rvc = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_2_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_2_bits_fflags_bits_uop_ctrl_is_load = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_2_bits_fflags_bits_uop_ctrl_is_sta = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_2_bits_fflags_bits_uop_ctrl_is_std = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_2_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_2_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_2_bits_fflags_bits_uop_is_br = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_2_bits_fflags_bits_uop_is_jalr = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_2_bits_fflags_bits_uop_is_jal = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_2_bits_fflags_bits_uop_is_sfb = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_2_bits_fflags_bits_uop_edge_inst = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_2_bits_fflags_bits_uop_taken = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_2_bits_fflags_bits_uop_prs1_busy = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_2_bits_fflags_bits_uop_prs2_busy = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_2_bits_fflags_bits_uop_prs3_busy = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_2_bits_fflags_bits_uop_ppred_busy = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_2_bits_fflags_bits_uop_exception = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_2_bits_fflags_bits_uop_bypassable = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_2_bits_fflags_bits_uop_mem_signed = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_2_bits_fflags_bits_uop_is_fence = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_2_bits_fflags_bits_uop_is_fencei = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_2_bits_fflags_bits_uop_is_amo = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_2_bits_fflags_bits_uop_uses_ldq = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_2_bits_fflags_bits_uop_uses_stq = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_2_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_2_bits_fflags_bits_uop_is_unique = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_2_bits_fflags_bits_uop_flush_on_commit = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_2_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_2_bits_fflags_bits_uop_ldst_val = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_2_bits_fflags_bits_uop_frs3_en = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_2_bits_fflags_bits_uop_fp_val = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_2_bits_fflags_bits_uop_fp_single = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_2_bits_fflags_bits_uop_xcpt_pf_if = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_2_bits_fflags_bits_uop_xcpt_ae_if = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_2_bits_fflags_bits_uop_xcpt_ma_if = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_2_bits_fflags_bits_uop_bp_debug_if = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_2_bits_fflags_bits_uop_bp_xcpt_if = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_3_bits_predicated = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_3_bits_fflags_valid = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_3_bits_fflags_bits_uop_is_rvc = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_3_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_3_bits_fflags_bits_uop_ctrl_is_load = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_3_bits_fflags_bits_uop_ctrl_is_sta = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_3_bits_fflags_bits_uop_ctrl_is_std = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_3_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_3_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_3_bits_fflags_bits_uop_is_br = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_3_bits_fflags_bits_uop_is_jalr = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_3_bits_fflags_bits_uop_is_jal = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_3_bits_fflags_bits_uop_is_sfb = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_3_bits_fflags_bits_uop_edge_inst = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_3_bits_fflags_bits_uop_taken = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_3_bits_fflags_bits_uop_prs1_busy = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_3_bits_fflags_bits_uop_prs2_busy = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_3_bits_fflags_bits_uop_prs3_busy = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_3_bits_fflags_bits_uop_ppred_busy = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_3_bits_fflags_bits_uop_exception = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_3_bits_fflags_bits_uop_bypassable = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_3_bits_fflags_bits_uop_mem_signed = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_3_bits_fflags_bits_uop_is_fence = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_3_bits_fflags_bits_uop_is_fencei = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_3_bits_fflags_bits_uop_is_amo = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_3_bits_fflags_bits_uop_uses_ldq = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_3_bits_fflags_bits_uop_uses_stq = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_3_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_3_bits_fflags_bits_uop_is_unique = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_3_bits_fflags_bits_uop_flush_on_commit = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_3_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_3_bits_fflags_bits_uop_ldst_val = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_3_bits_fflags_bits_uop_frs3_en = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_3_bits_fflags_bits_uop_fp_val = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_3_bits_fflags_bits_uop_fp_single = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_3_bits_fflags_bits_uop_xcpt_pf_if = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_3_bits_fflags_bits_uop_xcpt_ae_if = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_3_bits_fflags_bits_uop_xcpt_ma_if = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_3_bits_fflags_bits_uop_bp_debug_if = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_3_bits_fflags_bits_uop_bp_xcpt_if = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_4_bits_predicated = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_4_bits_fflags_valid = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_4_bits_fflags_bits_uop_is_rvc = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_4_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_4_bits_fflags_bits_uop_ctrl_is_load = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_4_bits_fflags_bits_uop_ctrl_is_sta = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_4_bits_fflags_bits_uop_ctrl_is_std = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_4_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_4_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_4_bits_fflags_bits_uop_is_br = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_4_bits_fflags_bits_uop_is_jalr = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_4_bits_fflags_bits_uop_is_jal = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_4_bits_fflags_bits_uop_is_sfb = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_4_bits_fflags_bits_uop_edge_inst = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_4_bits_fflags_bits_uop_taken = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_4_bits_fflags_bits_uop_prs1_busy = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_4_bits_fflags_bits_uop_prs2_busy = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_4_bits_fflags_bits_uop_prs3_busy = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_4_bits_fflags_bits_uop_ppred_busy = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_4_bits_fflags_bits_uop_exception = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_4_bits_fflags_bits_uop_bypassable = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_4_bits_fflags_bits_uop_mem_signed = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_4_bits_fflags_bits_uop_is_fence = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_4_bits_fflags_bits_uop_is_fencei = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_4_bits_fflags_bits_uop_is_amo = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_4_bits_fflags_bits_uop_uses_ldq = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_4_bits_fflags_bits_uop_uses_stq = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_4_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_4_bits_fflags_bits_uop_is_unique = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_4_bits_fflags_bits_uop_flush_on_commit = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_4_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_4_bits_fflags_bits_uop_ldst_val = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_4_bits_fflags_bits_uop_frs3_en = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_4_bits_fflags_bits_uop_fp_val = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_4_bits_fflags_bits_uop_fp_single = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_4_bits_fflags_bits_uop_xcpt_pf_if = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_4_bits_fflags_bits_uop_xcpt_ae_if = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_4_bits_fflags_bits_uop_xcpt_ma_if = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_4_bits_fflags_bits_uop_bp_debug_if = 1'h0;\t// @[core.scala:174:24]\n wire bypasses_4_bits_fflags_bits_uop_bp_xcpt_if = 1'h0;\t// @[core.scala:174:24]\n wire pred_bypasses_0_bits_predicated = 1'h0;\t// @[core.scala:175:27]\n wire pred_bypasses_0_bits_fflags_valid = 1'h0;\t// @[core.scala:175:27]\n wire pred_bypasses_0_bits_fflags_bits_uop_is_rvc = 1'h0;\t// @[core.scala:175:27]\n wire pred_bypasses_0_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0;\t// @[core.scala:175:27]\n wire pred_bypasses_0_bits_fflags_bits_uop_ctrl_is_load = 1'h0;\t// @[core.scala:175:27]\n wire pred_bypasses_0_bits_fflags_bits_uop_ctrl_is_sta = 1'h0;\t// @[core.scala:175:27]\n wire pred_bypasses_0_bits_fflags_bits_uop_ctrl_is_std = 1'h0;\t// @[core.scala:175:27]\n wire pred_bypasses_0_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0;\t// @[core.scala:175:27]\n wire pred_bypasses_0_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0;\t// @[core.scala:175:27]\n wire pred_bypasses_0_bits_fflags_bits_uop_is_br = 1'h0;\t// @[core.scala:175:27]\n wire pred_bypasses_0_bits_fflags_bits_uop_is_jalr = 1'h0;\t// @[core.scala:175:27]\n wire pred_bypasses_0_bits_fflags_bits_uop_is_jal = 1'h0;\t// @[core.scala:175:27]\n wire pred_bypasses_0_bits_fflags_bits_uop_is_sfb = 1'h0;\t// @[core.scala:175:27]\n wire pred_bypasses_0_bits_fflags_bits_uop_edge_inst = 1'h0;\t// @[core.scala:175:27]\n wire pred_bypasses_0_bits_fflags_bits_uop_taken = 1'h0;\t// @[core.scala:175:27]\n wire pred_bypasses_0_bits_fflags_bits_uop_prs1_busy = 1'h0;\t// @[core.scala:175:27]\n wire pred_bypasses_0_bits_fflags_bits_uop_prs2_busy = 1'h0;\t// @[core.scala:175:27]\n wire pred_bypasses_0_bits_fflags_bits_uop_prs3_busy = 1'h0;\t// @[core.scala:175:27]\n wire pred_bypasses_0_bits_fflags_bits_uop_ppred_busy = 1'h0;\t// @[core.scala:175:27]\n wire pred_bypasses_0_bits_fflags_bits_uop_exception = 1'h0;\t// @[core.scala:175:27]\n wire pred_bypasses_0_bits_fflags_bits_uop_bypassable = 1'h0;\t// @[core.scala:175:27]\n wire pred_bypasses_0_bits_fflags_bits_uop_mem_signed = 1'h0;\t// @[core.scala:175:27]\n wire pred_bypasses_0_bits_fflags_bits_uop_is_fence = 1'h0;\t// @[core.scala:175:27]\n wire pred_bypasses_0_bits_fflags_bits_uop_is_fencei = 1'h0;\t// @[core.scala:175:27]\n wire pred_bypasses_0_bits_fflags_bits_uop_is_amo = 1'h0;\t// @[core.scala:175:27]\n wire pred_bypasses_0_bits_fflags_bits_uop_uses_ldq = 1'h0;\t// @[core.scala:175:27]\n wire pred_bypasses_0_bits_fflags_bits_uop_uses_stq = 1'h0;\t// @[core.scala:175:27]\n wire pred_bypasses_0_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0;\t// @[core.scala:175:27]\n wire pred_bypasses_0_bits_fflags_bits_uop_is_unique = 1'h0;\t// @[core.scala:175:27]\n wire pred_bypasses_0_bits_fflags_bits_uop_flush_on_commit = 1'h0;\t// @[core.scala:175:27]\n wire pred_bypasses_0_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0;\t// @[core.scala:175:27]\n wire pred_bypasses_0_bits_fflags_bits_uop_ldst_val = 1'h0;\t// @[core.scala:175:27]\n wire pred_bypasses_0_bits_fflags_bits_uop_frs3_en = 1'h0;\t// @[core.scala:175:27]\n wire pred_bypasses_0_bits_fflags_bits_uop_fp_val = 1'h0;\t// @[core.scala:175:27]\n wire pred_bypasses_0_bits_fflags_bits_uop_fp_single = 1'h0;\t// @[core.scala:175:27]\n wire pred_bypasses_0_bits_fflags_bits_uop_xcpt_pf_if = 1'h0;\t// @[core.scala:175:27]\n wire pred_bypasses_0_bits_fflags_bits_uop_xcpt_ae_if = 1'h0;\t// @[core.scala:175:27]\n wire pred_bypasses_0_bits_fflags_bits_uop_xcpt_ma_if = 1'h0;\t// @[core.scala:175:27]\n wire pred_bypasses_0_bits_fflags_bits_uop_bp_debug_if = 1'h0;\t// @[core.scala:175:27]\n wire pred_bypasses_0_bits_fflags_bits_uop_bp_xcpt_if = 1'h0;\t// @[core.scala:175:27]\n wire brupdate_b2_valid = 1'h0;\t// @[core.scala:188:23]\n wire _use_this_mispredict_T_2 = 1'h0;\t// @[util.scala:363:52]\n wire _hits_WIRE_0 = 1'h0;\t// @[Events.scala:13:33]\n wire _hits_WIRE_1 = 1'h0;\t// @[Events.scala:13:33]\n wire _hits_WIRE_2 = 1'h0;\t// @[Events.scala:13:33]\n wire _hits_WIRE_3 = 1'h0;\t// @[Events.scala:13:33]\n wire hits_0 = 1'h0;\t// @[Events.scala:13:25]\n wire hits_1 = 1'h0;\t// @[Events.scala:13:25]\n wire hits_2 = 1'h0;\t// @[Events.scala:13:25]\n wire hits_3 = 1'h0;\t// @[Events.scala:13:25]\n wire _hits_WIRE_1_0 = 1'h0;\t// @[Events.scala:13:33]\n wire _hits_WIRE_1_1 = 1'h0;\t// @[Events.scala:13:33]\n wire _hits_WIRE_1_2 = 1'h0;\t// @[Events.scala:13:33]\n wire _hits_WIRE_1_3 = 1'h0;\t// @[Events.scala:13:33]\n wire _hits_WIRE_1_4 = 1'h0;\t// @[Events.scala:13:33]\n wire hits_1_0 = 1'h0;\t// @[Events.scala:13:25]\n wire hits_1_1 = 1'h0;\t// @[Events.scala:13:25]\n wire hits_1_2 = 1'h0;\t// @[Events.scala:13:25]\n wire hits_1_3 = 1'h0;\t// @[Events.scala:13:25]\n wire hits_1_4 = 1'h0;\t// @[Events.scala:13:25]\n wire _hits_WIRE_2_0 = 1'h0;\t// @[Events.scala:13:33]\n wire _hits_WIRE_2_1 = 1'h0;\t// @[Events.scala:13:33]\n wire _hits_WIRE_2_2 = 1'h0;\t// @[Events.scala:13:33]\n wire _hits_WIRE_2_3 = 1'h0;\t// @[Events.scala:13:33]\n wire _hits_WIRE_2_4 = 1'h0;\t// @[Events.scala:13:33]\n wire _hits_WIRE_2_5 = 1'h0;\t// @[Events.scala:13:33]\n wire hits_2_0 = 1'h0;\t// @[Events.scala:13:25]\n wire hits_2_1 = 1'h0;\t// @[Events.scala:13:25]\n wire hits_2_2 = 1'h0;\t// @[Events.scala:13:25]\n wire hits_2_3 = 1'h0;\t// @[Events.scala:13:25]\n wire hits_2_4 = 1'h0;\t// @[Events.scala:13:25]\n wire hits_2_5 = 1'h0;\t// @[Events.scala:13:25]\n wire custom_csrs_csrs_0_stall = 1'h0;\t// @[core.scala:276:25]\n wire custom_csrs_csrs_0_set = 1'h0;\t// @[core.scala:276:25]\n wire custom_csrs_csrs_1_stall = 1'h0;\t// @[core.scala:276:25]\n wire custom_csrs_csrs_1_set = 1'h0;\t// @[core.scala:276:25]\n wire _new_ghist_WIRE_current_saw_branch_not_taken = 1'h0;\t// @[core.scala:406:44]\n wire _new_ghist_WIRE_new_saw_branch_not_taken = 1'h0;\t// @[core.scala:406:44]\n wire _new_ghist_WIRE_new_saw_branch_taken = 1'h0;\t// @[core.scala:406:44]\n wire new_ghist_new_saw_branch_not_taken = 1'h0;\t// @[core.scala:406:29]\n wire new_ghist_new_saw_branch_taken = 1'h0;\t// @[core.scala:406:29]\n wire next_ghist_current_saw_branch_not_taken = 1'h0;\t// @[frontend.scala:87:27]\n wire p_uop_is_rvc = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_ctrl_fcn_dw = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_ctrl_is_load = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_ctrl_is_sta = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_ctrl_is_std = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_iw_p1_poisoned = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_iw_p2_poisoned = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_is_br = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_is_jalr = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_is_jal = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_is_sfb = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_edge_inst = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_taken = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_prs1_busy = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_prs2_busy = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_prs3_busy = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_ppred_busy = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_exception = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_bypassable = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_mem_signed = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_is_fence = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_is_fencei = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_is_amo = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_uses_ldq = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_uses_stq = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_is_sys_pc2epc = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_is_unique = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_flush_on_commit = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_ldst_is_rs1 = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_ldst_val = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_frs3_en = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_fp_val = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_fp_single = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_xcpt_pf_if = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_xcpt_ae_if = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_xcpt_ma_if = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_bp_debug_if = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_bp_xcpt_if = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_cs_fcn_dw = 1'h0;\t// @[consts.scala:279:18]\n wire p_uop_cs_is_load = 1'h0;\t// @[consts.scala:279:18]\n wire p_uop_cs_is_sta = 1'h0;\t// @[consts.scala:279:18]\n wire p_uop_cs_is_std = 1'h0;\t// @[consts.scala:279:18]\n wire _dis_uops_0_ppred_busy_T_2 = 1'h0;\t// @[micro-op.scala:110:43]\n wire _dis_uops_0_ppred_busy_T_3 = 1'h0;\t// @[core.scala:669:48]\n wire p_uop_1_is_rvc = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_1_ctrl_fcn_dw = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_1_ctrl_is_load = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_1_ctrl_is_sta = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_1_ctrl_is_std = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_1_iw_p1_poisoned = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_1_iw_p2_poisoned = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_1_is_br = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_1_is_jalr = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_1_is_jal = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_1_is_sfb = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_1_edge_inst = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_1_taken = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_1_prs1_busy = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_1_prs2_busy = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_1_prs3_busy = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_1_ppred_busy = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_1_exception = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_1_bypassable = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_1_mem_signed = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_1_is_fence = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_1_is_fencei = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_1_is_amo = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_1_uses_ldq = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_1_uses_stq = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_1_is_sys_pc2epc = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_1_is_unique = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_1_flush_on_commit = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_1_ldst_is_rs1 = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_1_ldst_val = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_1_frs3_en = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_1_fp_val = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_1_fp_single = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_1_xcpt_pf_if = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_1_xcpt_ae_if = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_1_xcpt_ma_if = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_1_bp_debug_if = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_1_bp_xcpt_if = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_cs_1_fcn_dw = 1'h0;\t// @[consts.scala:279:18]\n wire p_uop_cs_1_is_load = 1'h0;\t// @[consts.scala:279:18]\n wire p_uop_cs_1_is_sta = 1'h0;\t// @[consts.scala:279:18]\n wire p_uop_cs_1_is_std = 1'h0;\t// @[consts.scala:279:18]\n wire _dis_uops_1_ppred_busy_T_2 = 1'h0;\t// @[micro-op.scala:110:43]\n wire _dis_uops_1_ppred_busy_T_3 = 1'h0;\t// @[core.scala:669:48]\n wire p_uop_2_is_rvc = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_2_ctrl_fcn_dw = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_2_ctrl_is_load = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_2_ctrl_is_sta = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_2_ctrl_is_std = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_2_iw_p1_poisoned = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_2_iw_p2_poisoned = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_2_is_br = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_2_is_jalr = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_2_is_jal = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_2_is_sfb = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_2_edge_inst = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_2_taken = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_2_prs1_busy = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_2_prs2_busy = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_2_prs3_busy = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_2_ppred_busy = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_2_exception = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_2_bypassable = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_2_mem_signed = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_2_is_fence = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_2_is_fencei = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_2_is_amo = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_2_uses_ldq = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_2_uses_stq = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_2_is_sys_pc2epc = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_2_is_unique = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_2_flush_on_commit = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_2_ldst_is_rs1 = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_2_ldst_val = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_2_frs3_en = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_2_fp_val = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_2_fp_single = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_2_xcpt_pf_if = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_2_xcpt_ae_if = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_2_xcpt_ma_if = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_2_bp_debug_if = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_2_bp_xcpt_if = 1'h0;\t// @[consts.scala:269:19]\n wire p_uop_cs_2_fcn_dw = 1'h0;\t// @[consts.scala:279:18]\n wire p_uop_cs_2_is_load = 1'h0;\t// @[consts.scala:279:18]\n wire p_uop_cs_2_is_sta = 1'h0;\t// @[consts.scala:279:18]\n wire p_uop_cs_2_is_std = 1'h0;\t// @[consts.scala:279:18]\n wire _dis_uops_2_ppred_busy_T_2 = 1'h0;\t// @[micro-op.scala:110:43]\n wire _dis_uops_2_ppred_busy_T_3 = 1'h0;\t// @[core.scala:669:48]\n wire _wait_for_rocc_T_1 = 1'h0;\t// @[core.scala:689:90]\n wire wait_for_rocc_0 = 1'h0;\t// @[core.scala:689:73]\n wire _wait_for_rocc_T_3 = 1'h0;\t// @[core.scala:689:90]\n wire wait_for_rocc_1 = 1'h0;\t// @[core.scala:689:73]\n wire _wait_for_rocc_T_5 = 1'h0;\t// @[core.scala:689:90]\n wire wait_for_rocc_2 = 1'h0;\t// @[core.scala:689:73]\n wire fast_wakeup_bits_predicated = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_bits_fflags_valid = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_bits_fflags_bits_uop_is_rvc = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_bits_fflags_bits_uop_ctrl_is_load = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_bits_fflags_bits_uop_ctrl_is_sta = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_bits_fflags_bits_uop_ctrl_is_std = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_bits_fflags_bits_uop_is_br = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_bits_fflags_bits_uop_is_jalr = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_bits_fflags_bits_uop_is_jal = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_bits_fflags_bits_uop_is_sfb = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_bits_fflags_bits_uop_edge_inst = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_bits_fflags_bits_uop_taken = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_bits_fflags_bits_uop_prs1_busy = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_bits_fflags_bits_uop_prs2_busy = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_bits_fflags_bits_uop_prs3_busy = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_bits_fflags_bits_uop_ppred_busy = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_bits_fflags_bits_uop_exception = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_bits_fflags_bits_uop_bypassable = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_bits_fflags_bits_uop_mem_signed = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_bits_fflags_bits_uop_is_fence = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_bits_fflags_bits_uop_is_fencei = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_bits_fflags_bits_uop_is_amo = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_bits_fflags_bits_uop_uses_ldq = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_bits_fflags_bits_uop_uses_stq = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_bits_fflags_bits_uop_is_unique = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_bits_fflags_bits_uop_flush_on_commit = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_bits_fflags_bits_uop_ldst_val = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_bits_fflags_bits_uop_frs3_en = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_bits_fflags_bits_uop_fp_val = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_bits_fflags_bits_uop_fp_single = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_bits_fflags_bits_uop_xcpt_pf_if = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_bits_fflags_bits_uop_xcpt_ae_if = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_bits_fflags_bits_uop_xcpt_ma_if = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_bits_fflags_bits_uop_bp_debug_if = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_bits_fflags_bits_uop_bp_xcpt_if = 1'h0;\t// @[core.scala:814:29]\n wire slow_wakeup_bits_predicated = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_bits_fflags_valid = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_bits_fflags_bits_uop_is_rvc = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_bits_fflags_bits_uop_ctrl_is_load = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_bits_fflags_bits_uop_ctrl_is_sta = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_bits_fflags_bits_uop_ctrl_is_std = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_bits_fflags_bits_uop_is_br = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_bits_fflags_bits_uop_is_jalr = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_bits_fflags_bits_uop_is_jal = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_bits_fflags_bits_uop_is_sfb = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_bits_fflags_bits_uop_edge_inst = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_bits_fflags_bits_uop_taken = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_bits_fflags_bits_uop_prs1_busy = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_bits_fflags_bits_uop_prs2_busy = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_bits_fflags_bits_uop_prs3_busy = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_bits_fflags_bits_uop_ppred_busy = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_bits_fflags_bits_uop_exception = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_bits_fflags_bits_uop_bypassable = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_bits_fflags_bits_uop_mem_signed = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_bits_fflags_bits_uop_is_fence = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_bits_fflags_bits_uop_is_fencei = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_bits_fflags_bits_uop_is_amo = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_bits_fflags_bits_uop_uses_ldq = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_bits_fflags_bits_uop_uses_stq = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_bits_fflags_bits_uop_is_unique = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_bits_fflags_bits_uop_flush_on_commit = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_bits_fflags_bits_uop_ldst_val = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_bits_fflags_bits_uop_frs3_en = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_bits_fflags_bits_uop_fp_val = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_bits_fflags_bits_uop_fp_single = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_bits_fflags_bits_uop_xcpt_pf_if = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_bits_fflags_bits_uop_xcpt_ae_if = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_bits_fflags_bits_uop_xcpt_ma_if = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_bits_fflags_bits_uop_bp_debug_if = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_bits_fflags_bits_uop_bp_xcpt_if = 1'h0;\t// @[core.scala:815:29]\n wire fast_wakeup_1_bits_predicated = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_1_bits_fflags_valid = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_1_bits_fflags_bits_uop_is_rvc = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_1_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_1_bits_fflags_bits_uop_ctrl_is_load = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_1_bits_fflags_bits_uop_ctrl_is_sta = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_1_bits_fflags_bits_uop_ctrl_is_std = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_1_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_1_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_1_bits_fflags_bits_uop_is_br = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_1_bits_fflags_bits_uop_is_jalr = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_1_bits_fflags_bits_uop_is_jal = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_1_bits_fflags_bits_uop_is_sfb = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_1_bits_fflags_bits_uop_edge_inst = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_1_bits_fflags_bits_uop_taken = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_1_bits_fflags_bits_uop_prs1_busy = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_1_bits_fflags_bits_uop_prs2_busy = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_1_bits_fflags_bits_uop_prs3_busy = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_1_bits_fflags_bits_uop_ppred_busy = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_1_bits_fflags_bits_uop_exception = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_1_bits_fflags_bits_uop_bypassable = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_1_bits_fflags_bits_uop_mem_signed = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_1_bits_fflags_bits_uop_is_fence = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_1_bits_fflags_bits_uop_is_fencei = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_1_bits_fflags_bits_uop_is_amo = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_1_bits_fflags_bits_uop_uses_ldq = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_1_bits_fflags_bits_uop_uses_stq = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_1_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_1_bits_fflags_bits_uop_is_unique = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_1_bits_fflags_bits_uop_flush_on_commit = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_1_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_1_bits_fflags_bits_uop_ldst_val = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_1_bits_fflags_bits_uop_frs3_en = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_1_bits_fflags_bits_uop_fp_val = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_1_bits_fflags_bits_uop_fp_single = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_1_bits_fflags_bits_uop_xcpt_pf_if = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_1_bits_fflags_bits_uop_xcpt_ae_if = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_1_bits_fflags_bits_uop_xcpt_ma_if = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_1_bits_fflags_bits_uop_bp_debug_if = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_1_bits_fflags_bits_uop_bp_xcpt_if = 1'h0;\t// @[core.scala:814:29]\n wire slow_wakeup_1_bits_predicated = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_1_bits_fflags_valid = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_1_bits_fflags_bits_uop_is_rvc = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_1_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_1_bits_fflags_bits_uop_ctrl_is_load = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_1_bits_fflags_bits_uop_ctrl_is_sta = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_1_bits_fflags_bits_uop_ctrl_is_std = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_1_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_1_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_1_bits_fflags_bits_uop_is_br = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_1_bits_fflags_bits_uop_is_jalr = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_1_bits_fflags_bits_uop_is_jal = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_1_bits_fflags_bits_uop_is_sfb = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_1_bits_fflags_bits_uop_edge_inst = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_1_bits_fflags_bits_uop_taken = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_1_bits_fflags_bits_uop_prs1_busy = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_1_bits_fflags_bits_uop_prs2_busy = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_1_bits_fflags_bits_uop_prs3_busy = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_1_bits_fflags_bits_uop_ppred_busy = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_1_bits_fflags_bits_uop_exception = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_1_bits_fflags_bits_uop_bypassable = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_1_bits_fflags_bits_uop_mem_signed = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_1_bits_fflags_bits_uop_is_fence = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_1_bits_fflags_bits_uop_is_fencei = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_1_bits_fflags_bits_uop_is_amo = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_1_bits_fflags_bits_uop_uses_ldq = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_1_bits_fflags_bits_uop_uses_stq = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_1_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_1_bits_fflags_bits_uop_is_unique = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_1_bits_fflags_bits_uop_flush_on_commit = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_1_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_1_bits_fflags_bits_uop_ldst_val = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_1_bits_fflags_bits_uop_frs3_en = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_1_bits_fflags_bits_uop_fp_val = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_1_bits_fflags_bits_uop_fp_single = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_1_bits_fflags_bits_uop_xcpt_pf_if = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_1_bits_fflags_bits_uop_xcpt_ae_if = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_1_bits_fflags_bits_uop_xcpt_ma_if = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_1_bits_fflags_bits_uop_bp_debug_if = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_1_bits_fflags_bits_uop_bp_xcpt_if = 1'h0;\t// @[core.scala:815:29]\n wire fast_wakeup_2_bits_predicated = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_2_bits_fflags_valid = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_2_bits_fflags_bits_uop_is_rvc = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_2_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_2_bits_fflags_bits_uop_ctrl_is_load = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_2_bits_fflags_bits_uop_ctrl_is_sta = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_2_bits_fflags_bits_uop_ctrl_is_std = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_2_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_2_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_2_bits_fflags_bits_uop_is_br = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_2_bits_fflags_bits_uop_is_jalr = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_2_bits_fflags_bits_uop_is_jal = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_2_bits_fflags_bits_uop_is_sfb = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_2_bits_fflags_bits_uop_edge_inst = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_2_bits_fflags_bits_uop_taken = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_2_bits_fflags_bits_uop_prs1_busy = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_2_bits_fflags_bits_uop_prs2_busy = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_2_bits_fflags_bits_uop_prs3_busy = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_2_bits_fflags_bits_uop_ppred_busy = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_2_bits_fflags_bits_uop_exception = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_2_bits_fflags_bits_uop_bypassable = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_2_bits_fflags_bits_uop_mem_signed = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_2_bits_fflags_bits_uop_is_fence = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_2_bits_fflags_bits_uop_is_fencei = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_2_bits_fflags_bits_uop_is_amo = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_2_bits_fflags_bits_uop_uses_ldq = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_2_bits_fflags_bits_uop_uses_stq = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_2_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_2_bits_fflags_bits_uop_is_unique = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_2_bits_fflags_bits_uop_flush_on_commit = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_2_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_2_bits_fflags_bits_uop_ldst_val = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_2_bits_fflags_bits_uop_frs3_en = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_2_bits_fflags_bits_uop_fp_val = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_2_bits_fflags_bits_uop_fp_single = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_2_bits_fflags_bits_uop_xcpt_pf_if = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_2_bits_fflags_bits_uop_xcpt_ae_if = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_2_bits_fflags_bits_uop_xcpt_ma_if = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_2_bits_fflags_bits_uop_bp_debug_if = 1'h0;\t// @[core.scala:814:29]\n wire fast_wakeup_2_bits_fflags_bits_uop_bp_xcpt_if = 1'h0;\t// @[core.scala:814:29]\n wire slow_wakeup_2_bits_predicated = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_2_bits_fflags_valid = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_2_bits_fflags_bits_uop_is_rvc = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_2_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_2_bits_fflags_bits_uop_ctrl_is_load = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_2_bits_fflags_bits_uop_ctrl_is_sta = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_2_bits_fflags_bits_uop_ctrl_is_std = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_2_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_2_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_2_bits_fflags_bits_uop_is_br = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_2_bits_fflags_bits_uop_is_jalr = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_2_bits_fflags_bits_uop_is_jal = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_2_bits_fflags_bits_uop_is_sfb = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_2_bits_fflags_bits_uop_edge_inst = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_2_bits_fflags_bits_uop_taken = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_2_bits_fflags_bits_uop_prs1_busy = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_2_bits_fflags_bits_uop_prs2_busy = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_2_bits_fflags_bits_uop_prs3_busy = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_2_bits_fflags_bits_uop_ppred_busy = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_2_bits_fflags_bits_uop_exception = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_2_bits_fflags_bits_uop_bypassable = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_2_bits_fflags_bits_uop_mem_signed = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_2_bits_fflags_bits_uop_is_fence = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_2_bits_fflags_bits_uop_is_fencei = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_2_bits_fflags_bits_uop_is_amo = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_2_bits_fflags_bits_uop_uses_ldq = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_2_bits_fflags_bits_uop_uses_stq = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_2_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_2_bits_fflags_bits_uop_is_unique = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_2_bits_fflags_bits_uop_flush_on_commit = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_2_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_2_bits_fflags_bits_uop_ldst_val = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_2_bits_fflags_bits_uop_frs3_en = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_2_bits_fflags_bits_uop_fp_val = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_2_bits_fflags_bits_uop_fp_single = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_2_bits_fflags_bits_uop_xcpt_pf_if = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_2_bits_fflags_bits_uop_xcpt_ae_if = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_2_bits_fflags_bits_uop_xcpt_ma_if = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_2_bits_fflags_bits_uop_bp_debug_if = 1'h0;\t// @[core.scala:815:29]\n wire slow_wakeup_2_bits_fflags_bits_uop_bp_xcpt_if = 1'h0;\t// @[core.scala:815:29]\n wire _pred_wakeup_valid_T_1 = 1'h0;\t// @[micro-op.scala:109:42]\n wire _pred_wakeup_valid_T_2 = 1'h0;\t// @[core.scala:862:50]\n wire _pred_wakeup_valid_T_6 = 1'h0;\t// @[core.scala:863:58]\n wire _rob_io_csr_replay_valid_T = 1'h0;\t// @[core.scala:1008:58]\n wire _large_T_3 = 1'h0;\t// @[Counters.scala:68:28]\n wire coreMonitorBundle_excpt = 1'h0;\t// @[core.scala:1405:31]\n wire coreMonitorBundle_valid = 1'h0;\t// @[core.scala:1405:31]\n wire coreMonitorBundle_wrenx = 1'h0;\t// @[core.scala:1405:31]\n wire coreMonitorBundle_wrenf = 1'h0;\t// @[core.scala:1405:31]\n wire _io_rocc_exception_T = 1'h0;\t// @[core.scala:1424:61]\n wire _io_rocc_exception_T_1 = 1'h0;\t// @[core.scala:1424:41]\n wire [15:0] io_ifu_fetchpacket_bits_uops_0_bits_br_mask = 16'h0;\t// @[core.scala:51:7]\n wire [15:0] io_ifu_fetchpacket_bits_uops_1_bits_br_mask = 16'h0;\t// @[core.scala:51:7]\n wire [15:0] io_ifu_fetchpacket_bits_uops_2_bits_br_mask = 16'h0;\t// @[core.scala:51:7]\n wire [15:0] io_ptw_ptbr_asid = 16'h0;\t// @[core.scala:51:7]\n wire [15:0] io_ptw_hgatp_asid = 16'h0;\t// @[core.scala:51:7]\n wire [15:0] io_ptw_vsatp_asid = 16'h0;\t// @[core.scala:51:7]\n wire [15:0] io_lsu_exe_0_req_bits_fflags_bits_uop_br_mask = 16'h0;\t// @[core.scala:51:7]\n wire [15:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_br_mask = 16'h0;\t// @[core.scala:51:7]\n wire [15:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_br_mask = 16'h0;\t// @[core.scala:51:7]\n wire [15:0] io_ptw_tlb_ptbr_asid = 16'h0;\t// @[core.scala:51:7]\n wire [15:0] io_ptw_tlb_hgatp_asid = 16'h0;\t// @[core.scala:51:7]\n wire [15:0] io_ptw_tlb_vsatp_asid = 16'h0;\t// @[core.scala:51:7]\n wire [15:0] int_iss_wakeups_1_bits_fflags_bits_uop_br_mask = 16'h0;\t// @[core.scala:147:30]\n wire [15:0] int_iss_wakeups_2_bits_fflags_bits_uop_br_mask = 16'h0;\t// @[core.scala:147:30]\n wire [15:0] int_iss_wakeups_3_bits_fflags_bits_uop_br_mask = 16'h0;\t// @[core.scala:147:30]\n wire [15:0] int_iss_wakeups_4_bits_fflags_bits_uop_br_mask = 16'h0;\t// @[core.scala:147:30]\n wire [15:0] int_iss_wakeups_5_bits_fflags_bits_uop_br_mask = 16'h0;\t// @[core.scala:147:30]\n wire [15:0] int_iss_wakeups_6_bits_fflags_bits_uop_br_mask = 16'h0;\t// @[core.scala:147:30]\n wire [15:0] int_ren_wakeups_1_bits_fflags_bits_uop_br_mask = 16'h0;\t// @[core.scala:148:30]\n wire [15:0] int_ren_wakeups_2_bits_fflags_bits_uop_br_mask = 16'h0;\t// @[core.scala:148:30]\n wire [15:0] int_ren_wakeups_3_bits_fflags_bits_uop_br_mask = 16'h0;\t// @[core.scala:148:30]\n wire [15:0] int_ren_wakeups_4_bits_fflags_bits_uop_br_mask = 16'h0;\t// @[core.scala:148:30]\n wire [15:0] int_ren_wakeups_5_bits_fflags_bits_uop_br_mask = 16'h0;\t// @[core.scala:148:30]\n wire [15:0] int_ren_wakeups_6_bits_fflags_bits_uop_br_mask = 16'h0;\t// @[core.scala:148:30]\n wire [15:0] pred_wakeup_bits_fflags_bits_uop_br_mask = 16'h0;\t// @[core.scala:149:26]\n wire [15:0] bypasses_0_bits_fflags_bits_uop_br_mask = 16'h0;\t// @[core.scala:174:24]\n wire [15:0] bypasses_1_bits_fflags_bits_uop_br_mask = 16'h0;\t// @[core.scala:174:24]\n wire [15:0] bypasses_2_bits_fflags_bits_uop_br_mask = 16'h0;\t// @[core.scala:174:24]\n wire [15:0] bypasses_3_bits_fflags_bits_uop_br_mask = 16'h0;\t// @[core.scala:174:24]\n wire [15:0] bypasses_4_bits_fflags_bits_uop_br_mask = 16'h0;\t// @[core.scala:174:24]\n wire [15:0] pred_bypasses_0_bits_fflags_bits_uop_br_mask = 16'h0;\t// @[core.scala:175:27]\n wire [15:0] p_uop_br_mask = 16'h0;\t// @[consts.scala:269:19]\n wire [15:0] p_uop_1_br_mask = 16'h0;\t// @[consts.scala:269:19]\n wire [15:0] p_uop_2_br_mask = 16'h0;\t// @[consts.scala:269:19]\n wire [15:0] fast_wakeup_bits_fflags_bits_uop_br_mask = 16'h0;\t// @[core.scala:814:29]\n wire [15:0] slow_wakeup_bits_fflags_bits_uop_br_mask = 16'h0;\t// @[core.scala:815:29]\n wire [15:0] fast_wakeup_1_bits_fflags_bits_uop_br_mask = 16'h0;\t// @[core.scala:814:29]\n wire [15:0] slow_wakeup_1_bits_fflags_bits_uop_br_mask = 16'h0;\t// @[core.scala:815:29]\n wire [15:0] fast_wakeup_2_bits_fflags_bits_uop_br_mask = 16'h0;\t// @[core.scala:814:29]\n wire [15:0] slow_wakeup_2_bits_fflags_bits_uop_br_mask = 16'h0;\t// @[core.scala:815:29]\n wire [19:0] io_ifu_fetchpacket_bits_uops_0_bits_imm_packed = 20'h0;\t// @[core.scala:51:7]\n wire [19:0] io_ifu_fetchpacket_bits_uops_1_bits_imm_packed = 20'h0;\t// @[core.scala:51:7]\n wire [19:0] io_ifu_fetchpacket_bits_uops_2_bits_imm_packed = 20'h0;\t// @[core.scala:51:7]\n wire [19:0] io_lsu_exe_0_req_bits_fflags_bits_uop_imm_packed = 20'h0;\t// @[core.scala:51:7]\n wire [19:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_imm_packed = 20'h0;\t// @[core.scala:51:7]\n wire [19:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_imm_packed = 20'h0;\t// @[core.scala:51:7]\n wire [19:0] int_iss_wakeups_1_bits_fflags_bits_uop_imm_packed = 20'h0;\t// @[core.scala:147:30]\n wire [19:0] int_iss_wakeups_2_bits_fflags_bits_uop_imm_packed = 20'h0;\t// @[core.scala:147:30]\n wire [19:0] int_iss_wakeups_3_bits_fflags_bits_uop_imm_packed = 20'h0;\t// @[core.scala:147:30]\n wire [19:0] int_iss_wakeups_4_bits_fflags_bits_uop_imm_packed = 20'h0;\t// @[core.scala:147:30]\n wire [19:0] int_iss_wakeups_5_bits_fflags_bits_uop_imm_packed = 20'h0;\t// @[core.scala:147:30]\n wire [19:0] int_iss_wakeups_6_bits_fflags_bits_uop_imm_packed = 20'h0;\t// @[core.scala:147:30]\n wire [19:0] int_ren_wakeups_1_bits_fflags_bits_uop_imm_packed = 20'h0;\t// @[core.scala:148:30]\n wire [19:0] int_ren_wakeups_2_bits_fflags_bits_uop_imm_packed = 20'h0;\t// @[core.scala:148:30]\n wire [19:0] int_ren_wakeups_3_bits_fflags_bits_uop_imm_packed = 20'h0;\t// @[core.scala:148:30]\n wire [19:0] int_ren_wakeups_4_bits_fflags_bits_uop_imm_packed = 20'h0;\t// @[core.scala:148:30]\n wire [19:0] int_ren_wakeups_5_bits_fflags_bits_uop_imm_packed = 20'h0;\t// @[core.scala:148:30]\n wire [19:0] int_ren_wakeups_6_bits_fflags_bits_uop_imm_packed = 20'h0;\t// @[core.scala:148:30]\n wire [19:0] pred_wakeup_bits_fflags_bits_uop_imm_packed = 20'h0;\t// @[core.scala:149:26]\n wire [19:0] bypasses_0_bits_fflags_bits_uop_imm_packed = 20'h0;\t// @[core.scala:174:24]\n wire [19:0] bypasses_1_bits_fflags_bits_uop_imm_packed = 20'h0;\t// @[core.scala:174:24]\n wire [19:0] bypasses_2_bits_fflags_bits_uop_imm_packed = 20'h0;\t// @[core.scala:174:24]\n wire [19:0] bypasses_3_bits_fflags_bits_uop_imm_packed = 20'h0;\t// @[core.scala:174:24]\n wire [19:0] bypasses_4_bits_fflags_bits_uop_imm_packed = 20'h0;\t// @[core.scala:174:24]\n wire [19:0] pred_bypasses_0_bits_fflags_bits_uop_imm_packed = 20'h0;\t// @[core.scala:175:27]\n wire [19:0] p_uop_imm_packed = 20'h0;\t// @[consts.scala:269:19]\n wire [19:0] p_uop_1_imm_packed = 20'h0;\t// @[consts.scala:269:19]\n wire [19:0] p_uop_2_imm_packed = 20'h0;\t// @[consts.scala:269:19]\n wire [19:0] fast_wakeup_bits_fflags_bits_uop_imm_packed = 20'h0;\t// @[core.scala:814:29]\n wire [19:0] slow_wakeup_bits_fflags_bits_uop_imm_packed = 20'h0;\t// @[core.scala:815:29]\n wire [19:0] fast_wakeup_1_bits_fflags_bits_uop_imm_packed = 20'h0;\t// @[core.scala:814:29]\n wire [19:0] slow_wakeup_1_bits_fflags_bits_uop_imm_packed = 20'h0;\t// @[core.scala:815:29]\n wire [19:0] fast_wakeup_2_bits_fflags_bits_uop_imm_packed = 20'h0;\t// @[core.scala:814:29]\n wire [19:0] slow_wakeup_2_bits_fflags_bits_uop_imm_packed = 20'h0;\t// @[core.scala:815:29]\n wire [11:0] io_ifu_fetchpacket_bits_uops_0_bits_csr_addr = 12'h0;\t// @[core.scala:51:7]\n wire [11:0] io_ifu_fetchpacket_bits_uops_1_bits_csr_addr = 12'h0;\t// @[core.scala:51:7]\n wire [11:0] io_ifu_fetchpacket_bits_uops_2_bits_csr_addr = 12'h0;\t// @[core.scala:51:7]\n wire [11:0] io_lsu_exe_0_req_bits_fflags_bits_uop_csr_addr = 12'h0;\t// @[core.scala:51:7]\n wire [11:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_csr_addr = 12'h0;\t// @[core.scala:51:7]\n wire [11:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_csr_addr = 12'h0;\t// @[core.scala:51:7]\n wire [11:0] int_iss_wakeups_1_bits_fflags_bits_uop_csr_addr = 12'h0;\t// @[core.scala:147:30]\n wire [11:0] int_iss_wakeups_2_bits_fflags_bits_uop_csr_addr = 12'h0;\t// @[core.scala:147:30]\n wire [11:0] int_iss_wakeups_3_bits_fflags_bits_uop_csr_addr = 12'h0;\t// @[core.scala:147:30]\n wire [11:0] int_iss_wakeups_4_bits_fflags_bits_uop_csr_addr = 12'h0;\t// @[core.scala:147:30]\n wire [11:0] int_iss_wakeups_5_bits_fflags_bits_uop_csr_addr = 12'h0;\t// @[core.scala:147:30]\n wire [11:0] int_iss_wakeups_6_bits_fflags_bits_uop_csr_addr = 12'h0;\t// @[core.scala:147:30]\n wire [11:0] int_ren_wakeups_1_bits_fflags_bits_uop_csr_addr = 12'h0;\t// @[core.scala:148:30]\n wire [11:0] int_ren_wakeups_2_bits_fflags_bits_uop_csr_addr = 12'h0;\t// @[core.scala:148:30]\n wire [11:0] int_ren_wakeups_3_bits_fflags_bits_uop_csr_addr = 12'h0;\t// @[core.scala:148:30]\n wire [11:0] int_ren_wakeups_4_bits_fflags_bits_uop_csr_addr = 12'h0;\t// @[core.scala:148:30]\n wire [11:0] int_ren_wakeups_5_bits_fflags_bits_uop_csr_addr = 12'h0;\t// @[core.scala:148:30]\n wire [11:0] int_ren_wakeups_6_bits_fflags_bits_uop_csr_addr = 12'h0;\t// @[core.scala:148:30]\n wire [11:0] pred_wakeup_bits_fflags_bits_uop_csr_addr = 12'h0;\t// @[core.scala:149:26]\n wire [11:0] dec_uops_0_csr_addr = 12'h0;\t// @[core.scala:158:24]\n wire [11:0] dec_uops_1_csr_addr = 12'h0;\t// @[core.scala:158:24]\n wire [11:0] dec_uops_2_csr_addr = 12'h0;\t// @[core.scala:158:24]\n wire [11:0] bypasses_0_bits_fflags_bits_uop_csr_addr = 12'h0;\t// @[core.scala:174:24]\n wire [11:0] bypasses_1_bits_fflags_bits_uop_csr_addr = 12'h0;\t// @[core.scala:174:24]\n wire [11:0] bypasses_2_bits_fflags_bits_uop_csr_addr = 12'h0;\t// @[core.scala:174:24]\n wire [11:0] bypasses_3_bits_fflags_bits_uop_csr_addr = 12'h0;\t// @[core.scala:174:24]\n wire [11:0] bypasses_4_bits_fflags_bits_uop_csr_addr = 12'h0;\t// @[core.scala:174:24]\n wire [11:0] pred_bypasses_0_bits_fflags_bits_uop_csr_addr = 12'h0;\t// @[core.scala:175:27]\n wire [11:0] p_uop_csr_addr = 12'h0;\t// @[consts.scala:269:19]\n wire [11:0] p_uop_1_csr_addr = 12'h0;\t// @[consts.scala:269:19]\n wire [11:0] p_uop_2_csr_addr = 12'h0;\t// @[consts.scala:269:19]\n wire [11:0] fast_wakeup_bits_fflags_bits_uop_csr_addr = 12'h0;\t// @[core.scala:814:29]\n wire [11:0] slow_wakeup_bits_fflags_bits_uop_csr_addr = 12'h0;\t// @[core.scala:815:29]\n wire [11:0] fast_wakeup_1_bits_fflags_bits_uop_csr_addr = 12'h0;\t// @[core.scala:814:29]\n wire [11:0] slow_wakeup_1_bits_fflags_bits_uop_csr_addr = 12'h0;\t// @[core.scala:815:29]\n wire [11:0] fast_wakeup_2_bits_fflags_bits_uop_csr_addr = 12'h0;\t// @[core.scala:814:29]\n wire [11:0] slow_wakeup_2_bits_fflags_bits_uop_csr_addr = 12'h0;\t// @[core.scala:815:29]\n wire [63:0] io_ifu_fetchpacket_bits_uops_0_bits_exc_cause = 64'h0;\t// @[core.scala:51:7]\n wire [63:0] io_ifu_fetchpacket_bits_uops_1_bits_exc_cause = 64'h0;\t// @[core.scala:51:7]\n wire [63:0] io_ifu_fetchpacket_bits_uops_2_bits_exc_cause = 64'h0;\t// @[core.scala:51:7]\n wire [63:0] io_ifu_get_pc_0_ghist_old_history = 64'h0;\t// @[core.scala:51:7]\n wire [63:0] io_ptw_customCSRs_csrs_0_wdata = 64'h0;\t// @[core.scala:51:7]\n wire [63:0] io_ptw_customCSRs_csrs_0_value = 64'h0;\t// @[core.scala:51:7]\n wire [63:0] io_ptw_customCSRs_csrs_0_sdata = 64'h0;\t// @[core.scala:51:7]\n wire [63:0] io_ptw_customCSRs_csrs_1_wdata = 64'h0;\t// @[core.scala:51:7]\n wire [63:0] io_ptw_customCSRs_csrs_1_value = 64'h0;\t// @[core.scala:51:7]\n wire [63:0] io_ptw_customCSRs_csrs_1_sdata = 64'h0;\t// @[core.scala:51:7]\n wire [63:0] io_rocc_cmd_bits_rs1 = 64'h0;\t// @[core.scala:51:7]\n wire [63:0] io_rocc_cmd_bits_rs2 = 64'h0;\t// @[core.scala:51:7]\n wire [63:0] io_rocc_resp_bits_data = 64'h0;\t// @[core.scala:51:7]\n wire [63:0] io_rocc_mem_req_bits_data = 64'h0;\t// @[core.scala:51:7]\n wire [63:0] io_rocc_mem_s1_data_data = 64'h0;\t// @[core.scala:51:7]\n wire [63:0] io_rocc_mem_resp_bits_data = 64'h0;\t// @[core.scala:51:7]\n wire [63:0] io_rocc_mem_resp_bits_data_word_bypass = 64'h0;\t// @[core.scala:51:7]\n wire [63:0] io_rocc_mem_resp_bits_data_raw = 64'h0;\t// @[core.scala:51:7]\n wire [63:0] io_rocc_mem_resp_bits_store_data = 64'h0;\t// @[core.scala:51:7]\n wire [63:0] io_lsu_exe_0_req_bits_fflags_bits_uop_exc_cause = 64'h0;\t// @[core.scala:51:7]\n wire [63:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_exc_cause = 64'h0;\t// @[core.scala:51:7]\n wire [63:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_exc_cause = 64'h0;\t// @[core.scala:51:7]\n wire [63:0] io_ptw_tlb_customCSRs_csrs_0_wdata = 64'h0;\t// @[core.scala:51:7]\n wire [63:0] io_ptw_tlb_customCSRs_csrs_0_value = 64'h0;\t// @[core.scala:51:7]\n wire [63:0] io_ptw_tlb_customCSRs_csrs_0_sdata = 64'h0;\t// @[core.scala:51:7]\n wire [63:0] io_ptw_tlb_customCSRs_csrs_1_wdata = 64'h0;\t// @[core.scala:51:7]\n wire [63:0] io_ptw_tlb_customCSRs_csrs_1_value = 64'h0;\t// @[core.scala:51:7]\n wire [63:0] io_ptw_tlb_customCSRs_csrs_1_sdata = 64'h0;\t// @[core.scala:51:7]\n wire [63:0] io_trace_insns_0_cause = 64'h0;\t// @[core.scala:51:7]\n wire [63:0] io_trace_insns_1_cause = 64'h0;\t// @[core.scala:51:7]\n wire [63:0] io_trace_insns_2_cause = 64'h0;\t// @[core.scala:51:7]\n wire [63:0] int_iss_wakeups_1_bits_data = 64'h0;\t// @[core.scala:147:30]\n wire [63:0] int_iss_wakeups_1_bits_fflags_bits_uop_exc_cause = 64'h0;\t// @[core.scala:147:30]\n wire [63:0] int_iss_wakeups_2_bits_data = 64'h0;\t// @[core.scala:147:30]\n wire [63:0] int_iss_wakeups_2_bits_fflags_bits_uop_exc_cause = 64'h0;\t// @[core.scala:147:30]\n wire [63:0] int_iss_wakeups_3_bits_data = 64'h0;\t// @[core.scala:147:30]\n wire [63:0] int_iss_wakeups_3_bits_fflags_bits_uop_exc_cause = 64'h0;\t// @[core.scala:147:30]\n wire [63:0] int_iss_wakeups_4_bits_data = 64'h0;\t// @[core.scala:147:30]\n wire [63:0] int_iss_wakeups_4_bits_fflags_bits_uop_exc_cause = 64'h0;\t// @[core.scala:147:30]\n wire [63:0] int_iss_wakeups_5_bits_data = 64'h0;\t// @[core.scala:147:30]\n wire [63:0] int_iss_wakeups_5_bits_fflags_bits_uop_exc_cause = 64'h0;\t// @[core.scala:147:30]\n wire [63:0] int_iss_wakeups_6_bits_data = 64'h0;\t// @[core.scala:147:30]\n wire [63:0] int_iss_wakeups_6_bits_fflags_bits_uop_exc_cause = 64'h0;\t// @[core.scala:147:30]\n wire [63:0] int_ren_wakeups_1_bits_data = 64'h0;\t// @[core.scala:148:30]\n wire [63:0] int_ren_wakeups_1_bits_fflags_bits_uop_exc_cause = 64'h0;\t// @[core.scala:148:30]\n wire [63:0] int_ren_wakeups_2_bits_data = 64'h0;\t// @[core.scala:148:30]\n wire [63:0] int_ren_wakeups_2_bits_fflags_bits_uop_exc_cause = 64'h0;\t// @[core.scala:148:30]\n wire [63:0] int_ren_wakeups_3_bits_data = 64'h0;\t// @[core.scala:148:30]\n wire [63:0] int_ren_wakeups_3_bits_fflags_bits_uop_exc_cause = 64'h0;\t// @[core.scala:148:30]\n wire [63:0] int_ren_wakeups_4_bits_data = 64'h0;\t// @[core.scala:148:30]\n wire [63:0] int_ren_wakeups_4_bits_fflags_bits_uop_exc_cause = 64'h0;\t// @[core.scala:148:30]\n wire [63:0] int_ren_wakeups_5_bits_data = 64'h0;\t// @[core.scala:148:30]\n wire [63:0] int_ren_wakeups_5_bits_fflags_bits_uop_exc_cause = 64'h0;\t// @[core.scala:148:30]\n wire [63:0] int_ren_wakeups_6_bits_data = 64'h0;\t// @[core.scala:148:30]\n wire [63:0] int_ren_wakeups_6_bits_fflags_bits_uop_exc_cause = 64'h0;\t// @[core.scala:148:30]\n wire [63:0] pred_wakeup_bits_fflags_bits_uop_exc_cause = 64'h0;\t// @[core.scala:149:26]\n wire [63:0] bypasses_0_bits_fflags_bits_uop_exc_cause = 64'h0;\t// @[core.scala:174:24]\n wire [63:0] bypasses_1_bits_fflags_bits_uop_exc_cause = 64'h0;\t// @[core.scala:174:24]\n wire [63:0] bypasses_2_bits_fflags_bits_uop_exc_cause = 64'h0;\t// @[core.scala:174:24]\n wire [63:0] bypasses_3_bits_fflags_bits_uop_exc_cause = 64'h0;\t// @[core.scala:174:24]\n wire [63:0] bypasses_4_bits_fflags_bits_uop_exc_cause = 64'h0;\t// @[core.scala:174:24]\n wire [63:0] pred_bypasses_0_bits_fflags_bits_uop_exc_cause = 64'h0;\t// @[core.scala:175:27]\n wire [63:0] custom_csrs_csrs_0_sdata = 64'h0;\t// @[core.scala:276:25]\n wire [63:0] custom_csrs_csrs_1_sdata = 64'h0;\t// @[core.scala:276:25]\n wire [63:0] _new_ghist_WIRE_old_history = 64'h0;\t// @[core.scala:406:44]\n wire [63:0] new_ghist_old_history = 64'h0;\t// @[core.scala:406:29]\n wire [63:0] p_uop_exc_cause = 64'h0;\t// @[consts.scala:269:19]\n wire [63:0] p_uop_1_exc_cause = 64'h0;\t// @[consts.scala:269:19]\n wire [63:0] p_uop_2_exc_cause = 64'h0;\t// @[consts.scala:269:19]\n wire [63:0] fast_wakeup_bits_data = 64'h0;\t// @[core.scala:814:29]\n wire [63:0] fast_wakeup_bits_fflags_bits_uop_exc_cause = 64'h0;\t// @[core.scala:814:29]\n wire [63:0] slow_wakeup_bits_data = 64'h0;\t// @[core.scala:815:29]\n wire [63:0] slow_wakeup_bits_fflags_bits_uop_exc_cause = 64'h0;\t// @[core.scala:815:29]\n wire [63:0] fast_wakeup_1_bits_data = 64'h0;\t// @[core.scala:814:29]\n wire [63:0] fast_wakeup_1_bits_fflags_bits_uop_exc_cause = 64'h0;\t// @[core.scala:814:29]\n wire [63:0] slow_wakeup_1_bits_data = 64'h0;\t// @[core.scala:815:29]\n wire [63:0] slow_wakeup_1_bits_fflags_bits_uop_exc_cause = 64'h0;\t// @[core.scala:815:29]\n wire [63:0] fast_wakeup_2_bits_data = 64'h0;\t// @[core.scala:814:29]\n wire [63:0] fast_wakeup_2_bits_fflags_bits_uop_exc_cause = 64'h0;\t// @[core.scala:814:29]\n wire [63:0] slow_wakeup_2_bits_data = 64'h0;\t// @[core.scala:815:29]\n wire [63:0] slow_wakeup_2_bits_fflags_bits_uop_exc_cause = 64'h0;\t// @[core.scala:815:29]\n wire [63:0] coreMonitorBundle_hartid = 64'h0;\t// @[core.scala:1405:31]\n wire [63:0] coreMonitorBundle_pc = 64'h0;\t// @[core.scala:1405:31]\n wire [63:0] coreMonitorBundle_wrdata = 64'h0;\t// @[core.scala:1405:31]\n wire [63:0] coreMonitorBundle_rd0val = 64'h0;\t// @[core.scala:1405:31]\n wire [63:0] coreMonitorBundle_rd1val = 64'h0;\t// @[core.scala:1405:31]\n wire [5:0] io_ifu_fetchpacket_bits_uops_0_bits_ldst = 6'h0;\t// @[core.scala:51:7]\n wire [5:0] io_ifu_fetchpacket_bits_uops_0_bits_lrs1 = 6'h0;\t// @[core.scala:51:7]\n wire [5:0] io_ifu_fetchpacket_bits_uops_0_bits_lrs2 = 6'h0;\t// @[core.scala:51:7]\n wire [5:0] io_ifu_fetchpacket_bits_uops_0_bits_lrs3 = 6'h0;\t// @[core.scala:51:7]\n wire [5:0] io_ifu_fetchpacket_bits_uops_1_bits_ldst = 6'h0;\t// @[core.scala:51:7]\n wire [5:0] io_ifu_fetchpacket_bits_uops_1_bits_lrs1 = 6'h0;\t// @[core.scala:51:7]\n wire [5:0] io_ifu_fetchpacket_bits_uops_1_bits_lrs2 = 6'h0;\t// @[core.scala:51:7]\n wire [5:0] io_ifu_fetchpacket_bits_uops_1_bits_lrs3 = 6'h0;\t// @[core.scala:51:7]\n wire [5:0] io_ifu_fetchpacket_bits_uops_2_bits_ldst = 6'h0;\t// @[core.scala:51:7]\n wire [5:0] io_ifu_fetchpacket_bits_uops_2_bits_lrs1 = 6'h0;\t// @[core.scala:51:7]\n wire [5:0] io_ifu_fetchpacket_bits_uops_2_bits_lrs2 = 6'h0;\t// @[core.scala:51:7]\n wire [5:0] io_ifu_fetchpacket_bits_uops_2_bits_lrs3 = 6'h0;\t// @[core.scala:51:7]\n wire [5:0] io_ptw_hstatus_vgein = 6'h0;\t// @[core.scala:51:7]\n wire [5:0] io_lsu_exe_0_req_bits_fflags_bits_uop_pc_lob = 6'h0;\t// @[core.scala:51:7]\n wire [5:0] io_lsu_exe_0_req_bits_fflags_bits_uop_ldst = 6'h0;\t// @[core.scala:51:7]\n wire [5:0] io_lsu_exe_0_req_bits_fflags_bits_uop_lrs1 = 6'h0;\t// @[core.scala:51:7]\n wire [5:0] io_lsu_exe_0_req_bits_fflags_bits_uop_lrs2 = 6'h0;\t// @[core.scala:51:7]\n wire [5:0] io_lsu_exe_0_req_bits_fflags_bits_uop_lrs3 = 6'h0;\t// @[core.scala:51:7]\n wire [5:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_pc_lob = 6'h0;\t// @[core.scala:51:7]\n wire [5:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_ldst = 6'h0;\t// @[core.scala:51:7]\n wire [5:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_lrs1 = 6'h0;\t// @[core.scala:51:7]\n wire [5:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_lrs2 = 6'h0;\t// @[core.scala:51:7]\n wire [5:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_lrs3 = 6'h0;\t// @[core.scala:51:7]\n wire [5:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_pc_lob = 6'h0;\t// @[core.scala:51:7]\n wire [5:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_ldst = 6'h0;\t// @[core.scala:51:7]\n wire [5:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_lrs1 = 6'h0;\t// @[core.scala:51:7]\n wire [5:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_lrs2 = 6'h0;\t// @[core.scala:51:7]\n wire [5:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_lrs3 = 6'h0;\t// @[core.scala:51:7]\n wire [5:0] io_ptw_tlb_hstatus_vgein = 6'h0;\t// @[core.scala:51:7]\n wire [5:0] int_iss_wakeups_1_bits_fflags_bits_uop_pc_lob = 6'h0;\t// @[core.scala:147:30]\n wire [5:0] int_iss_wakeups_1_bits_fflags_bits_uop_ldst = 6'h0;\t// @[core.scala:147:30]\n wire [5:0] int_iss_wakeups_1_bits_fflags_bits_uop_lrs1 = 6'h0;\t// @[core.scala:147:30]\n wire [5:0] int_iss_wakeups_1_bits_fflags_bits_uop_lrs2 = 6'h0;\t// @[core.scala:147:30]\n wire [5:0] int_iss_wakeups_1_bits_fflags_bits_uop_lrs3 = 6'h0;\t// @[core.scala:147:30]\n wire [5:0] int_iss_wakeups_2_bits_fflags_bits_uop_pc_lob = 6'h0;\t// @[core.scala:147:30]\n wire [5:0] int_iss_wakeups_2_bits_fflags_bits_uop_ldst = 6'h0;\t// @[core.scala:147:30]\n wire [5:0] int_iss_wakeups_2_bits_fflags_bits_uop_lrs1 = 6'h0;\t// @[core.scala:147:30]\n wire [5:0] int_iss_wakeups_2_bits_fflags_bits_uop_lrs2 = 6'h0;\t// @[core.scala:147:30]\n wire [5:0] int_iss_wakeups_2_bits_fflags_bits_uop_lrs3 = 6'h0;\t// @[core.scala:147:30]\n wire [5:0] int_iss_wakeups_3_bits_fflags_bits_uop_pc_lob = 6'h0;\t// @[core.scala:147:30]\n wire [5:0] int_iss_wakeups_3_bits_fflags_bits_uop_ldst = 6'h0;\t// @[core.scala:147:30]\n wire [5:0] int_iss_wakeups_3_bits_fflags_bits_uop_lrs1 = 6'h0;\t// @[core.scala:147:30]\n wire [5:0] int_iss_wakeups_3_bits_fflags_bits_uop_lrs2 = 6'h0;\t// @[core.scala:147:30]\n wire [5:0] int_iss_wakeups_3_bits_fflags_bits_uop_lrs3 = 6'h0;\t// @[core.scala:147:30]\n wire [5:0] int_iss_wakeups_4_bits_fflags_bits_uop_pc_lob = 6'h0;\t// @[core.scala:147:30]\n wire [5:0] int_iss_wakeups_4_bits_fflags_bits_uop_ldst = 6'h0;\t// @[core.scala:147:30]\n wire [5:0] int_iss_wakeups_4_bits_fflags_bits_uop_lrs1 = 6'h0;\t// @[core.scala:147:30]\n wire [5:0] int_iss_wakeups_4_bits_fflags_bits_uop_lrs2 = 6'h0;\t// @[core.scala:147:30]\n wire [5:0] int_iss_wakeups_4_bits_fflags_bits_uop_lrs3 = 6'h0;\t// @[core.scala:147:30]\n wire [5:0] int_iss_wakeups_5_bits_fflags_bits_uop_pc_lob = 6'h0;\t// @[core.scala:147:30]\n wire [5:0] int_iss_wakeups_5_bits_fflags_bits_uop_ldst = 6'h0;\t// @[core.scala:147:30]\n wire [5:0] int_iss_wakeups_5_bits_fflags_bits_uop_lrs1 = 6'h0;\t// @[core.scala:147:30]\n wire [5:0] int_iss_wakeups_5_bits_fflags_bits_uop_lrs2 = 6'h0;\t// @[core.scala:147:30]\n wire [5:0] int_iss_wakeups_5_bits_fflags_bits_uop_lrs3 = 6'h0;\t// @[core.scala:147:30]\n wire [5:0] int_iss_wakeups_6_bits_fflags_bits_uop_pc_lob = 6'h0;\t// @[core.scala:147:30]\n wire [5:0] int_iss_wakeups_6_bits_fflags_bits_uop_ldst = 6'h0;\t// @[core.scala:147:30]\n wire [5:0] int_iss_wakeups_6_bits_fflags_bits_uop_lrs1 = 6'h0;\t// @[core.scala:147:30]\n wire [5:0] int_iss_wakeups_6_bits_fflags_bits_uop_lrs2 = 6'h0;\t// @[core.scala:147:30]\n wire [5:0] int_iss_wakeups_6_bits_fflags_bits_uop_lrs3 = 6'h0;\t// @[core.scala:147:30]\n wire [5:0] int_ren_wakeups_1_bits_fflags_bits_uop_pc_lob = 6'h0;\t// @[core.scala:148:30]\n wire [5:0] int_ren_wakeups_1_bits_fflags_bits_uop_ldst = 6'h0;\t// @[core.scala:148:30]\n wire [5:0] int_ren_wakeups_1_bits_fflags_bits_uop_lrs1 = 6'h0;\t// @[core.scala:148:30]\n wire [5:0] int_ren_wakeups_1_bits_fflags_bits_uop_lrs2 = 6'h0;\t// @[core.scala:148:30]\n wire [5:0] int_ren_wakeups_1_bits_fflags_bits_uop_lrs3 = 6'h0;\t// @[core.scala:148:30]\n wire [5:0] int_ren_wakeups_2_bits_fflags_bits_uop_pc_lob = 6'h0;\t// @[core.scala:148:30]\n wire [5:0] int_ren_wakeups_2_bits_fflags_bits_uop_ldst = 6'h0;\t// @[core.scala:148:30]\n wire [5:0] int_ren_wakeups_2_bits_fflags_bits_uop_lrs1 = 6'h0;\t// @[core.scala:148:30]\n wire [5:0] int_ren_wakeups_2_bits_fflags_bits_uop_lrs2 = 6'h0;\t// @[core.scala:148:30]\n wire [5:0] int_ren_wakeups_2_bits_fflags_bits_uop_lrs3 = 6'h0;\t// @[core.scala:148:30]\n wire [5:0] int_ren_wakeups_3_bits_fflags_bits_uop_pc_lob = 6'h0;\t// @[core.scala:148:30]\n wire [5:0] int_ren_wakeups_3_bits_fflags_bits_uop_ldst = 6'h0;\t// @[core.scala:148:30]\n wire [5:0] int_ren_wakeups_3_bits_fflags_bits_uop_lrs1 = 6'h0;\t// @[core.scala:148:30]\n wire [5:0] int_ren_wakeups_3_bits_fflags_bits_uop_lrs2 = 6'h0;\t// @[core.scala:148:30]\n wire [5:0] int_ren_wakeups_3_bits_fflags_bits_uop_lrs3 = 6'h0;\t// @[core.scala:148:30]\n wire [5:0] int_ren_wakeups_4_bits_fflags_bits_uop_pc_lob = 6'h0;\t// @[core.scala:148:30]\n wire [5:0] int_ren_wakeups_4_bits_fflags_bits_uop_ldst = 6'h0;\t// @[core.scala:148:30]\n wire [5:0] int_ren_wakeups_4_bits_fflags_bits_uop_lrs1 = 6'h0;\t// @[core.scala:148:30]\n wire [5:0] int_ren_wakeups_4_bits_fflags_bits_uop_lrs2 = 6'h0;\t// @[core.scala:148:30]\n wire [5:0] int_ren_wakeups_4_bits_fflags_bits_uop_lrs3 = 6'h0;\t// @[core.scala:148:30]\n wire [5:0] int_ren_wakeups_5_bits_fflags_bits_uop_pc_lob = 6'h0;\t// @[core.scala:148:30]\n wire [5:0] int_ren_wakeups_5_bits_fflags_bits_uop_ldst = 6'h0;\t// @[core.scala:148:30]\n wire [5:0] int_ren_wakeups_5_bits_fflags_bits_uop_lrs1 = 6'h0;\t// @[core.scala:148:30]\n wire [5:0] int_ren_wakeups_5_bits_fflags_bits_uop_lrs2 = 6'h0;\t// @[core.scala:148:30]\n wire [5:0] int_ren_wakeups_5_bits_fflags_bits_uop_lrs3 = 6'h0;\t// @[core.scala:148:30]\n wire [5:0] int_ren_wakeups_6_bits_fflags_bits_uop_pc_lob = 6'h0;\t// @[core.scala:148:30]\n wire [5:0] int_ren_wakeups_6_bits_fflags_bits_uop_ldst = 6'h0;\t// @[core.scala:148:30]\n wire [5:0] int_ren_wakeups_6_bits_fflags_bits_uop_lrs1 = 6'h0;\t// @[core.scala:148:30]\n wire [5:0] int_ren_wakeups_6_bits_fflags_bits_uop_lrs2 = 6'h0;\t// @[core.scala:148:30]\n wire [5:0] int_ren_wakeups_6_bits_fflags_bits_uop_lrs3 = 6'h0;\t// @[core.scala:148:30]\n wire [5:0] pred_wakeup_bits_fflags_bits_uop_pc_lob = 6'h0;\t// @[core.scala:149:26]\n wire [5:0] pred_wakeup_bits_fflags_bits_uop_ldst = 6'h0;\t// @[core.scala:149:26]\n wire [5:0] pred_wakeup_bits_fflags_bits_uop_lrs1 = 6'h0;\t// @[core.scala:149:26]\n wire [5:0] pred_wakeup_bits_fflags_bits_uop_lrs2 = 6'h0;\t// @[core.scala:149:26]\n wire [5:0] pred_wakeup_bits_fflags_bits_uop_lrs3 = 6'h0;\t// @[core.scala:149:26]\n wire [5:0] bypasses_0_bits_fflags_bits_uop_pc_lob = 6'h0;\t// @[core.scala:174:24]\n wire [5:0] bypasses_0_bits_fflags_bits_uop_ldst = 6'h0;\t// @[core.scala:174:24]\n wire [5:0] bypasses_0_bits_fflags_bits_uop_lrs1 = 6'h0;\t// @[core.scala:174:24]\n wire [5:0] bypasses_0_bits_fflags_bits_uop_lrs2 = 6'h0;\t// @[core.scala:174:24]\n wire [5:0] bypasses_0_bits_fflags_bits_uop_lrs3 = 6'h0;\t// @[core.scala:174:24]\n wire [5:0] bypasses_1_bits_fflags_bits_uop_pc_lob = 6'h0;\t// @[core.scala:174:24]\n wire [5:0] bypasses_1_bits_fflags_bits_uop_ldst = 6'h0;\t// @[core.scala:174:24]\n wire [5:0] bypasses_1_bits_fflags_bits_uop_lrs1 = 6'h0;\t// @[core.scala:174:24]\n wire [5:0] bypasses_1_bits_fflags_bits_uop_lrs2 = 6'h0;\t// @[core.scala:174:24]\n wire [5:0] bypasses_1_bits_fflags_bits_uop_lrs3 = 6'h0;\t// @[core.scala:174:24]\n wire [5:0] bypasses_2_bits_fflags_bits_uop_pc_lob = 6'h0;\t// @[core.scala:174:24]\n wire [5:0] bypasses_2_bits_fflags_bits_uop_ldst = 6'h0;\t// @[core.scala:174:24]\n wire [5:0] bypasses_2_bits_fflags_bits_uop_lrs1 = 6'h0;\t// @[core.scala:174:24]\n wire [5:0] bypasses_2_bits_fflags_bits_uop_lrs2 = 6'h0;\t// @[core.scala:174:24]\n wire [5:0] bypasses_2_bits_fflags_bits_uop_lrs3 = 6'h0;\t// @[core.scala:174:24]\n wire [5:0] bypasses_3_bits_fflags_bits_uop_pc_lob = 6'h0;\t// @[core.scala:174:24]\n wire [5:0] bypasses_3_bits_fflags_bits_uop_ldst = 6'h0;\t// @[core.scala:174:24]\n wire [5:0] bypasses_3_bits_fflags_bits_uop_lrs1 = 6'h0;\t// @[core.scala:174:24]\n wire [5:0] bypasses_3_bits_fflags_bits_uop_lrs2 = 6'h0;\t// @[core.scala:174:24]\n wire [5:0] bypasses_3_bits_fflags_bits_uop_lrs3 = 6'h0;\t// @[core.scala:174:24]\n wire [5:0] bypasses_4_bits_fflags_bits_uop_pc_lob = 6'h0;\t// @[core.scala:174:24]\n wire [5:0] bypasses_4_bits_fflags_bits_uop_ldst = 6'h0;\t// @[core.scala:174:24]\n wire [5:0] bypasses_4_bits_fflags_bits_uop_lrs1 = 6'h0;\t// @[core.scala:174:24]\n wire [5:0] bypasses_4_bits_fflags_bits_uop_lrs2 = 6'h0;\t// @[core.scala:174:24]\n wire [5:0] bypasses_4_bits_fflags_bits_uop_lrs3 = 6'h0;\t// @[core.scala:174:24]\n wire [5:0] pred_bypasses_0_bits_fflags_bits_uop_pc_lob = 6'h0;\t// @[core.scala:175:27]\n wire [5:0] pred_bypasses_0_bits_fflags_bits_uop_ldst = 6'h0;\t// @[core.scala:175:27]\n wire [5:0] pred_bypasses_0_bits_fflags_bits_uop_lrs1 = 6'h0;\t// @[core.scala:175:27]\n wire [5:0] pred_bypasses_0_bits_fflags_bits_uop_lrs2 = 6'h0;\t// @[core.scala:175:27]\n wire [5:0] pred_bypasses_0_bits_fflags_bits_uop_lrs3 = 6'h0;\t// @[core.scala:175:27]\n wire [5:0] p_uop_pc_lob = 6'h0;\t// @[consts.scala:269:19]\n wire [5:0] p_uop_ldst = 6'h0;\t// @[consts.scala:269:19]\n wire [5:0] p_uop_lrs1 = 6'h0;\t// @[consts.scala:269:19]\n wire [5:0] p_uop_lrs2 = 6'h0;\t// @[consts.scala:269:19]\n wire [5:0] p_uop_lrs3 = 6'h0;\t// @[consts.scala:269:19]\n wire [5:0] p_uop_1_pc_lob = 6'h0;\t// @[consts.scala:269:19]\n wire [5:0] p_uop_1_ldst = 6'h0;\t// @[consts.scala:269:19]\n wire [5:0] p_uop_1_lrs1 = 6'h0;\t// @[consts.scala:269:19]\n wire [5:0] p_uop_1_lrs2 = 6'h0;\t// @[consts.scala:269:19]\n wire [5:0] p_uop_1_lrs3 = 6'h0;\t// @[consts.scala:269:19]\n wire [5:0] p_uop_2_pc_lob = 6'h0;\t// @[consts.scala:269:19]\n wire [5:0] p_uop_2_ldst = 6'h0;\t// @[consts.scala:269:19]\n wire [5:0] p_uop_2_lrs1 = 6'h0;\t// @[consts.scala:269:19]\n wire [5:0] p_uop_2_lrs2 = 6'h0;\t// @[consts.scala:269:19]\n wire [5:0] p_uop_2_lrs3 = 6'h0;\t// @[consts.scala:269:19]\n wire [5:0] fast_wakeup_bits_fflags_bits_uop_pc_lob = 6'h0;\t// @[core.scala:814:29]\n wire [5:0] fast_wakeup_bits_fflags_bits_uop_ldst = 6'h0;\t// @[core.scala:814:29]\n wire [5:0] fast_wakeup_bits_fflags_bits_uop_lrs1 = 6'h0;\t// @[core.scala:814:29]\n wire [5:0] fast_wakeup_bits_fflags_bits_uop_lrs2 = 6'h0;\t// @[core.scala:814:29]\n wire [5:0] fast_wakeup_bits_fflags_bits_uop_lrs3 = 6'h0;\t// @[core.scala:814:29]\n wire [5:0] slow_wakeup_bits_fflags_bits_uop_pc_lob = 6'h0;\t// @[core.scala:815:29]\n wire [5:0] slow_wakeup_bits_fflags_bits_uop_ldst = 6'h0;\t// @[core.scala:815:29]\n wire [5:0] slow_wakeup_bits_fflags_bits_uop_lrs1 = 6'h0;\t// @[core.scala:815:29]\n wire [5:0] slow_wakeup_bits_fflags_bits_uop_lrs2 = 6'h0;\t// @[core.scala:815:29]\n wire [5:0] slow_wakeup_bits_fflags_bits_uop_lrs3 = 6'h0;\t// @[core.scala:815:29]\n wire [5:0] fast_wakeup_1_bits_fflags_bits_uop_pc_lob = 6'h0;\t// @[core.scala:814:29]\n wire [5:0] fast_wakeup_1_bits_fflags_bits_uop_ldst = 6'h0;\t// @[core.scala:814:29]\n wire [5:0] fast_wakeup_1_bits_fflags_bits_uop_lrs1 = 6'h0;\t// @[core.scala:814:29]\n wire [5:0] fast_wakeup_1_bits_fflags_bits_uop_lrs2 = 6'h0;\t// @[core.scala:814:29]\n wire [5:0] fast_wakeup_1_bits_fflags_bits_uop_lrs3 = 6'h0;\t// @[core.scala:814:29]\n wire [5:0] slow_wakeup_1_bits_fflags_bits_uop_pc_lob = 6'h0;\t// @[core.scala:815:29]\n wire [5:0] slow_wakeup_1_bits_fflags_bits_uop_ldst = 6'h0;\t// @[core.scala:815:29]\n wire [5:0] slow_wakeup_1_bits_fflags_bits_uop_lrs1 = 6'h0;\t// @[core.scala:815:29]\n wire [5:0] slow_wakeup_1_bits_fflags_bits_uop_lrs2 = 6'h0;\t// @[core.scala:815:29]\n wire [5:0] slow_wakeup_1_bits_fflags_bits_uop_lrs3 = 6'h0;\t// @[core.scala:815:29]\n wire [5:0] fast_wakeup_2_bits_fflags_bits_uop_pc_lob = 6'h0;\t// @[core.scala:814:29]\n wire [5:0] fast_wakeup_2_bits_fflags_bits_uop_ldst = 6'h0;\t// @[core.scala:814:29]\n wire [5:0] fast_wakeup_2_bits_fflags_bits_uop_lrs1 = 6'h0;\t// @[core.scala:814:29]\n wire [5:0] fast_wakeup_2_bits_fflags_bits_uop_lrs2 = 6'h0;\t// @[core.scala:814:29]\n wire [5:0] fast_wakeup_2_bits_fflags_bits_uop_lrs3 = 6'h0;\t// @[core.scala:814:29]\n wire [5:0] slow_wakeup_2_bits_fflags_bits_uop_pc_lob = 6'h0;\t// @[core.scala:815:29]\n wire [5:0] slow_wakeup_2_bits_fflags_bits_uop_ldst = 6'h0;\t// @[core.scala:815:29]\n wire [5:0] slow_wakeup_2_bits_fflags_bits_uop_lrs1 = 6'h0;\t// @[core.scala:815:29]\n wire [5:0] slow_wakeup_2_bits_fflags_bits_uop_lrs2 = 6'h0;\t// @[core.scala:815:29]\n wire [5:0] slow_wakeup_2_bits_fflags_bits_uop_lrs3 = 6'h0;\t// @[core.scala:815:29]\n wire [31:0] io_ifu_status_isa = 32'h14112D;\t// @[core.scala:51:7]\n wire [31:0] io_ptw_status_isa = 32'h14112D;\t// @[core.scala:51:7]\n wire [31:0] io_ptw_tlb_status_isa = 32'h14112D;\t// @[core.scala:51:7]\n wire [22:0] io_ifu_status_zero2 = 23'h0;\t// @[core.scala:51:7]\n wire [22:0] io_ptw_status_zero2 = 23'h0;\t// @[core.scala:51:7]\n wire [22:0] io_ptw_gstatus_zero2 = 23'h0;\t// @[core.scala:51:7]\n wire [22:0] io_rocc_cmd_bits_status_zero2 = 23'h0;\t// @[core.scala:51:7]\n wire [22:0] io_ptw_tlb_status_zero2 = 23'h0;\t// @[core.scala:51:7]\n wire [22:0] io_ptw_tlb_gstatus_zero2 = 23'h0;\t// @[core.scala:51:7]\n wire [7:0] io_ifu_status_zero1 = 8'h0;\t// @[core.scala:51:7]\n wire [7:0] io_ptw_status_zero1 = 8'h0;\t// @[core.scala:51:7]\n wire [7:0] io_ptw_gstatus_zero1 = 8'h0;\t// @[core.scala:51:7]\n wire [7:0] io_rocc_cmd_bits_status_zero1 = 8'h0;\t// @[core.scala:51:7]\n wire [7:0] io_rocc_mem_req_bits_mask = 8'h0;\t// @[core.scala:51:7]\n wire [7:0] io_rocc_mem_s1_data_mask = 8'h0;\t// @[core.scala:51:7]\n wire [7:0] io_rocc_mem_resp_bits_mask = 8'h0;\t// @[core.scala:51:7]\n wire [7:0] io_ptw_tlb_status_zero1 = 8'h0;\t// @[core.scala:51:7]\n wire [7:0] io_ptw_tlb_gstatus_zero1 = 8'h0;\t// @[core.scala:51:7]\n wire [39:0] io_rocc_mem_req_bits_addr = 40'h0;\t// @[core.scala:51:7]\n wire [39:0] io_rocc_mem_resp_bits_addr = 40'h0;\t// @[core.scala:51:7]\n wire [39:0] io_rocc_mem_s2_gpa = 40'h0;\t// @[core.scala:51:7]\n wire [39:0] io_lsu_exe_0_req_bits_fflags_bits_uop_debug_pc = 40'h0;\t// @[core.scala:51:7]\n wire [39:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_debug_pc = 40'h0;\t// @[core.scala:51:7]\n wire [39:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_debug_pc = 40'h0;\t// @[core.scala:51:7]\n wire [39:0] io_trace_insns_0_iaddr = 40'h0;\t// @[core.scala:51:7]\n wire [39:0] io_trace_insns_0_tval = 40'h0;\t// @[core.scala:51:7]\n wire [39:0] io_trace_insns_1_iaddr = 40'h0;\t// @[core.scala:51:7]\n wire [39:0] io_trace_insns_1_tval = 40'h0;\t// @[core.scala:51:7]\n wire [39:0] io_trace_insns_2_iaddr = 40'h0;\t// @[core.scala:51:7]\n wire [39:0] io_trace_insns_2_tval = 40'h0;\t// @[core.scala:51:7]\n wire [39:0] int_iss_wakeups_1_bits_fflags_bits_uop_debug_pc = 40'h0;\t// @[core.scala:147:30]\n wire [39:0] int_iss_wakeups_2_bits_fflags_bits_uop_debug_pc = 40'h0;\t// @[core.scala:147:30]\n wire [39:0] int_iss_wakeups_3_bits_fflags_bits_uop_debug_pc = 40'h0;\t// @[core.scala:147:30]\n wire [39:0] int_iss_wakeups_4_bits_fflags_bits_uop_debug_pc = 40'h0;\t// @[core.scala:147:30]\n wire [39:0] int_iss_wakeups_5_bits_fflags_bits_uop_debug_pc = 40'h0;\t// @[core.scala:147:30]\n wire [39:0] int_iss_wakeups_6_bits_fflags_bits_uop_debug_pc = 40'h0;\t// @[core.scala:147:30]\n wire [39:0] int_ren_wakeups_1_bits_fflags_bits_uop_debug_pc = 40'h0;\t// @[core.scala:148:30]\n wire [39:0] int_ren_wakeups_2_bits_fflags_bits_uop_debug_pc = 40'h0;\t// @[core.scala:148:30]\n wire [39:0] int_ren_wakeups_3_bits_fflags_bits_uop_debug_pc = 40'h0;\t// @[core.scala:148:30]\n wire [39:0] int_ren_wakeups_4_bits_fflags_bits_uop_debug_pc = 40'h0;\t// @[core.scala:148:30]\n wire [39:0] int_ren_wakeups_5_bits_fflags_bits_uop_debug_pc = 40'h0;\t// @[core.scala:148:30]\n wire [39:0] int_ren_wakeups_6_bits_fflags_bits_uop_debug_pc = 40'h0;\t// @[core.scala:148:30]\n wire [39:0] pred_wakeup_bits_fflags_bits_uop_debug_pc = 40'h0;\t// @[core.scala:149:26]\n wire [39:0] bypasses_0_bits_fflags_bits_uop_debug_pc = 40'h0;\t// @[core.scala:174:24]\n wire [39:0] bypasses_1_bits_fflags_bits_uop_debug_pc = 40'h0;\t// @[core.scala:174:24]\n wire [39:0] bypasses_2_bits_fflags_bits_uop_debug_pc = 40'h0;\t// @[core.scala:174:24]\n wire [39:0] bypasses_3_bits_fflags_bits_uop_debug_pc = 40'h0;\t// @[core.scala:174:24]\n wire [39:0] bypasses_4_bits_fflags_bits_uop_debug_pc = 40'h0;\t// @[core.scala:174:24]\n wire [39:0] pred_bypasses_0_bits_fflags_bits_uop_debug_pc = 40'h0;\t// @[core.scala:175:27]\n wire [39:0] p_uop_debug_pc = 40'h0;\t// @[consts.scala:269:19]\n wire [39:0] p_uop_1_debug_pc = 40'h0;\t// @[consts.scala:269:19]\n wire [39:0] p_uop_2_debug_pc = 40'h0;\t// @[consts.scala:269:19]\n wire [39:0] fast_wakeup_bits_fflags_bits_uop_debug_pc = 40'h0;\t// @[core.scala:814:29]\n wire [39:0] slow_wakeup_bits_fflags_bits_uop_debug_pc = 40'h0;\t// @[core.scala:815:29]\n wire [39:0] fast_wakeup_1_bits_fflags_bits_uop_debug_pc = 40'h0;\t// @[core.scala:814:29]\n wire [39:0] slow_wakeup_1_bits_fflags_bits_uop_debug_pc = 40'h0;\t// @[core.scala:815:29]\n wire [39:0] fast_wakeup_2_bits_fflags_bits_uop_debug_pc = 40'h0;\t// @[core.scala:814:29]\n wire [39:0] slow_wakeup_2_bits_fflags_bits_uop_debug_pc = 40'h0;\t// @[core.scala:815:29]\n wire [1:0] io_ifu_status_sxl = 2'h2;\t// @[core.scala:51:7]\n wire [1:0] io_ifu_status_uxl = 2'h2;\t// @[core.scala:51:7]\n wire [1:0] io_ptw_status_sxl = 2'h2;\t// @[core.scala:51:7]\n wire [1:0] io_ptw_status_uxl = 2'h2;\t// @[core.scala:51:7]\n wire [1:0] io_ptw_tlb_status_sxl = 2'h2;\t// @[core.scala:51:7]\n wire [1:0] io_ptw_tlb_status_uxl = 2'h2;\t// @[core.scala:51:7]\n wire [1:0] p_uop_dst_rtype = 2'h2;\t// @[consts.scala:269:19]\n wire [1:0] p_uop_1_dst_rtype = 2'h2;\t// @[consts.scala:269:19]\n wire [1:0] p_uop_2_dst_rtype = 2'h2;\t// @[consts.scala:269:19]\n wire [43:0] io_ptw_hgatp_ppn = 44'h0;\t// @[core.scala:51:7]\n wire [43:0] io_ptw_vsatp_ppn = 44'h0;\t// @[core.scala:51:7]\n wire [43:0] io_ptw_tlb_hgatp_ppn = 44'h0;\t// @[core.scala:51:7]\n wire [43:0] io_ptw_tlb_vsatp_ppn = 44'h0;\t// @[core.scala:51:7]\n wire [29:0] io_ptw_hstatus_zero6 = 30'h0;\t// @[core.scala:51:7]\n wire [29:0] io_ptw_tlb_hstatus_zero6 = 30'h0;\t// @[core.scala:51:7]\n wire [8:0] io_ptw_hstatus_zero5 = 9'h0;\t// @[core.scala:51:7]\n wire [8:0] io_ptw_tlb_hstatus_zero5 = 9'h0;\t// @[core.scala:51:7]\n wire [31:0] io_ptw_gstatus_isa = 32'h0;\t// @[core.scala:51:7]\n wire [31:0] io_rocc_cmd_bits_status_isa = 32'h0;\t// @[core.scala:51:7]\n wire [31:0] io_rocc_mem_s2_paddr = 32'h0;\t// @[core.scala:51:7]\n wire [31:0] io_lsu_exe_0_req_bits_fflags_bits_uop_inst = 32'h0;\t// @[core.scala:51:7]\n wire [31:0] io_lsu_exe_0_req_bits_fflags_bits_uop_debug_inst = 32'h0;\t// @[core.scala:51:7]\n wire [31:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_inst = 32'h0;\t// @[core.scala:51:7]\n wire [31:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_debug_inst = 32'h0;\t// @[core.scala:51:7]\n wire [31:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_inst = 32'h0;\t// @[core.scala:51:7]\n wire [31:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_debug_inst = 32'h0;\t// @[core.scala:51:7]\n wire [31:0] io_ptw_tlb_gstatus_isa = 32'h0;\t// @[core.scala:51:7]\n wire [31:0] io_trace_insns_0_insn = 32'h0;\t// @[core.scala:51:7]\n wire [31:0] io_trace_insns_1_insn = 32'h0;\t// @[core.scala:51:7]\n wire [31:0] io_trace_insns_2_insn = 32'h0;\t// @[core.scala:51:7]\n wire [31:0] int_iss_wakeups_1_bits_fflags_bits_uop_inst = 32'h0;\t// @[core.scala:147:30]\n wire [31:0] int_iss_wakeups_1_bits_fflags_bits_uop_debug_inst = 32'h0;\t// @[core.scala:147:30]\n wire [31:0] int_iss_wakeups_2_bits_fflags_bits_uop_inst = 32'h0;\t// @[core.scala:147:30]\n wire [31:0] int_iss_wakeups_2_bits_fflags_bits_uop_debug_inst = 32'h0;\t// @[core.scala:147:30]\n wire [31:0] int_iss_wakeups_3_bits_fflags_bits_uop_inst = 32'h0;\t// @[core.scala:147:30]\n wire [31:0] int_iss_wakeups_3_bits_fflags_bits_uop_debug_inst = 32'h0;\t// @[core.scala:147:30]\n wire [31:0] int_iss_wakeups_4_bits_fflags_bits_uop_inst = 32'h0;\t// @[core.scala:147:30]\n wire [31:0] int_iss_wakeups_4_bits_fflags_bits_uop_debug_inst = 32'h0;\t// @[core.scala:147:30]\n wire [31:0] int_iss_wakeups_5_bits_fflags_bits_uop_inst = 32'h0;\t// @[core.scala:147:30]\n wire [31:0] int_iss_wakeups_5_bits_fflags_bits_uop_debug_inst = 32'h0;\t// @[core.scala:147:30]\n wire [31:0] int_iss_wakeups_6_bits_fflags_bits_uop_inst = 32'h0;\t// @[core.scala:147:30]\n wire [31:0] int_iss_wakeups_6_bits_fflags_bits_uop_debug_inst = 32'h0;\t// @[core.scala:147:30]\n wire [31:0] int_ren_wakeups_1_bits_fflags_bits_uop_inst = 32'h0;\t// @[core.scala:148:30]\n wire [31:0] int_ren_wakeups_1_bits_fflags_bits_uop_debug_inst = 32'h0;\t// @[core.scala:148:30]\n wire [31:0] int_ren_wakeups_2_bits_fflags_bits_uop_inst = 32'h0;\t// @[core.scala:148:30]\n wire [31:0] int_ren_wakeups_2_bits_fflags_bits_uop_debug_inst = 32'h0;\t// @[core.scala:148:30]\n wire [31:0] int_ren_wakeups_3_bits_fflags_bits_uop_inst = 32'h0;\t// @[core.scala:148:30]\n wire [31:0] int_ren_wakeups_3_bits_fflags_bits_uop_debug_inst = 32'h0;\t// @[core.scala:148:30]\n wire [31:0] int_ren_wakeups_4_bits_fflags_bits_uop_inst = 32'h0;\t// @[core.scala:148:30]\n wire [31:0] int_ren_wakeups_4_bits_fflags_bits_uop_debug_inst = 32'h0;\t// @[core.scala:148:30]\n wire [31:0] int_ren_wakeups_5_bits_fflags_bits_uop_inst = 32'h0;\t// @[core.scala:148:30]\n wire [31:0] int_ren_wakeups_5_bits_fflags_bits_uop_debug_inst = 32'h0;\t// @[core.scala:148:30]\n wire [31:0] int_ren_wakeups_6_bits_fflags_bits_uop_inst = 32'h0;\t// @[core.scala:148:30]\n wire [31:0] int_ren_wakeups_6_bits_fflags_bits_uop_debug_inst = 32'h0;\t// @[core.scala:148:30]\n wire [31:0] pred_wakeup_bits_fflags_bits_uop_inst = 32'h0;\t// @[core.scala:149:26]\n wire [31:0] pred_wakeup_bits_fflags_bits_uop_debug_inst = 32'h0;\t// @[core.scala:149:26]\n wire [31:0] bypasses_0_bits_fflags_bits_uop_inst = 32'h0;\t// @[core.scala:174:24]\n wire [31:0] bypasses_0_bits_fflags_bits_uop_debug_inst = 32'h0;\t// @[core.scala:174:24]\n wire [31:0] bypasses_1_bits_fflags_bits_uop_inst = 32'h0;\t// @[core.scala:174:24]\n wire [31:0] bypasses_1_bits_fflags_bits_uop_debug_inst = 32'h0;\t// @[core.scala:174:24]\n wire [31:0] bypasses_2_bits_fflags_bits_uop_inst = 32'h0;\t// @[core.scala:174:24]\n wire [31:0] bypasses_2_bits_fflags_bits_uop_debug_inst = 32'h0;\t// @[core.scala:174:24]\n wire [31:0] bypasses_3_bits_fflags_bits_uop_inst = 32'h0;\t// @[core.scala:174:24]\n wire [31:0] bypasses_3_bits_fflags_bits_uop_debug_inst = 32'h0;\t// @[core.scala:174:24]\n wire [31:0] bypasses_4_bits_fflags_bits_uop_inst = 32'h0;\t// @[core.scala:174:24]\n wire [31:0] bypasses_4_bits_fflags_bits_uop_debug_inst = 32'h0;\t// @[core.scala:174:24]\n wire [31:0] pred_bypasses_0_bits_fflags_bits_uop_inst = 32'h0;\t// @[core.scala:175:27]\n wire [31:0] pred_bypasses_0_bits_fflags_bits_uop_debug_inst = 32'h0;\t// @[core.scala:175:27]\n wire [31:0] p_uop_inst = 32'h0;\t// @[consts.scala:269:19]\n wire [31:0] p_uop_debug_inst = 32'h0;\t// @[consts.scala:269:19]\n wire [31:0] p_uop_1_inst = 32'h0;\t// @[consts.scala:269:19]\n wire [31:0] p_uop_1_debug_inst = 32'h0;\t// @[consts.scala:269:19]\n wire [31:0] p_uop_2_inst = 32'h0;\t// @[consts.scala:269:19]\n wire [31:0] p_uop_2_debug_inst = 32'h0;\t// @[consts.scala:269:19]\n wire [31:0] fast_wakeup_bits_fflags_bits_uop_inst = 32'h0;\t// @[core.scala:814:29]\n wire [31:0] fast_wakeup_bits_fflags_bits_uop_debug_inst = 32'h0;\t// @[core.scala:814:29]\n wire [31:0] slow_wakeup_bits_fflags_bits_uop_inst = 32'h0;\t// @[core.scala:815:29]\n wire [31:0] slow_wakeup_bits_fflags_bits_uop_debug_inst = 32'h0;\t// @[core.scala:815:29]\n wire [31:0] fast_wakeup_1_bits_fflags_bits_uop_inst = 32'h0;\t// @[core.scala:814:29]\n wire [31:0] fast_wakeup_1_bits_fflags_bits_uop_debug_inst = 32'h0;\t// @[core.scala:814:29]\n wire [31:0] slow_wakeup_1_bits_fflags_bits_uop_inst = 32'h0;\t// @[core.scala:815:29]\n wire [31:0] slow_wakeup_1_bits_fflags_bits_uop_debug_inst = 32'h0;\t// @[core.scala:815:29]\n wire [31:0] fast_wakeup_2_bits_fflags_bits_uop_inst = 32'h0;\t// @[core.scala:814:29]\n wire [31:0] fast_wakeup_2_bits_fflags_bits_uop_debug_inst = 32'h0;\t// @[core.scala:814:29]\n wire [31:0] slow_wakeup_2_bits_fflags_bits_uop_inst = 32'h0;\t// @[core.scala:815:29]\n wire [31:0] slow_wakeup_2_bits_fflags_bits_uop_debug_inst = 32'h0;\t// @[core.scala:815:29]\n wire [31:0] coreMonitorBundle_timer = 32'h0;\t// @[core.scala:1405:31]\n wire [31:0] coreMonitorBundle_inst = 32'h0;\t// @[core.scala:1405:31]\n wire io_lsu_exe_0_iresp_ready = 1'h1;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_fresp_ready = 1'h1;\t// @[core.scala:51:7]\n wire _use_this_mispredict_T = 1'h1;\t// @[core.scala:206:31]\n wire use_this_mispredict = 1'h1;\t// @[core.scala:206:47]\n wire new_ghist_current_saw_branch_not_taken = 1'h1;\t// @[core.scala:406:29]\n wire flush_pc_req_ready = 1'h1;\t// @[core.scala:524:26]\n wire _large_T_1 = 1'h1;\t// @[Counters.scala:51:36]\n wire [26:0] io_ptw_tlb_req_bits_bits_addr = 27'h0;\t// @[core.scala:51:7]\n wire [4:0] _pause_mem_T = 5'h1F;\t// @[core.scala:912:77]\n wire [3:0] _cfi_idx_T_1 = 4'h8;\t// @[core.scala:442:45]\n wire [7:0] _next_ghist_not_taken_branches_T_19 = 8'hFF;\t// @[frontend.scala:91:45]\n wire dec_ready;\t// @[core.scala:161:24]\n wire [4:0] new_ghist_ras_idx = io_ifu_get_pc_0_entry_ras_idx_0;\t// @[core.scala:51:7, :406:29]\n wire _cfi_idx_T = io_ifu_get_pc_1_entry_start_bank_0;\t// @[core.scala:51:7, :442:32]\n wire io_ptw_sfence_valid_0 = io_ifu_sfence_valid_0;\t// @[core.scala:51:7]\n wire io_ptw_sfence_bits_rs1_0 = io_ifu_sfence_bits_rs1_0;\t// @[core.scala:51:7]\n wire io_ptw_sfence_bits_rs2_0 = io_ifu_sfence_bits_rs2_0;\t// @[core.scala:51:7]\n wire [38:0] io_ptw_sfence_bits_addr_0 = io_ifu_sfence_bits_addr_0;\t// @[core.scala:51:7]\n wire io_ptw_sfence_bits_asid_0 = io_ifu_sfence_bits_asid_0;\t// @[core.scala:51:7]\n wire [15:0] brupdate_b1_resolve_mask;\t// @[core.scala:188:23]\n wire [15:0] brupdate_b1_mispredict_mask;\t// @[core.scala:188:23]\n wire [6:0] brupdate_b2_uop_uopc;\t// @[core.scala:188:23]\n wire [31:0] brupdate_b2_uop_inst;\t// @[core.scala:188:23]\n wire [31:0] brupdate_b2_uop_debug_inst;\t// @[core.scala:188:23]\n wire brupdate_b2_uop_is_rvc;\t// @[core.scala:188:23]\n wire [39:0] brupdate_b2_uop_debug_pc;\t// @[core.scala:188:23]\n wire [2:0] brupdate_b2_uop_iq_type;\t// @[core.scala:188:23]\n wire [9:0] brupdate_b2_uop_fu_code;\t// @[core.scala:188:23]\n wire [3:0] brupdate_b2_uop_ctrl_br_type;\t// @[core.scala:188:23]\n wire [1:0] brupdate_b2_uop_ctrl_op1_sel;\t// @[core.scala:188:23]\n wire [2:0] brupdate_b2_uop_ctrl_op2_sel;\t// @[core.scala:188:23]\n wire [2:0] brupdate_b2_uop_ctrl_imm_sel;\t// @[core.scala:188:23]\n wire [4:0] brupdate_b2_uop_ctrl_op_fcn;\t// @[core.scala:188:23]\n wire brupdate_b2_uop_ctrl_fcn_dw;\t// @[core.scala:188:23]\n wire [2:0] brupdate_b2_uop_ctrl_csr_cmd;\t// @[core.scala:188:23]\n wire brupdate_b2_uop_ctrl_is_load;\t// @[core.scala:188:23]\n wire brupdate_b2_uop_ctrl_is_sta;\t// @[core.scala:188:23]\n wire brupdate_b2_uop_ctrl_is_std;\t// @[core.scala:188:23]\n wire [1:0] brupdate_b2_uop_iw_state;\t// @[core.scala:188:23]\n wire brupdate_b2_uop_iw_p1_poisoned;\t// @[core.scala:188:23]\n wire brupdate_b2_uop_iw_p2_poisoned;\t// @[core.scala:188:23]\n wire brupdate_b2_uop_is_br;\t// @[core.scala:188:23]\n wire brupdate_b2_uop_is_jalr;\t// @[core.scala:188:23]\n wire brupdate_b2_uop_is_jal;\t// @[core.scala:188:23]\n wire brupdate_b2_uop_is_sfb;\t// @[core.scala:188:23]\n wire [15:0] brupdate_b2_uop_br_mask;\t// @[core.scala:188:23]\n wire [3:0] brupdate_b2_uop_br_tag;\t// @[core.scala:188:23]\n wire [4:0] brupdate_b2_uop_ftq_idx;\t// @[core.scala:188:23]\n wire brupdate_b2_uop_edge_inst;\t// @[core.scala:188:23]\n wire [5:0] brupdate_b2_uop_pc_lob;\t// @[core.scala:188:23]\n wire brupdate_b2_uop_taken;\t// @[core.scala:188:23]\n wire [19:0] brupdate_b2_uop_imm_packed;\t// @[core.scala:188:23]\n wire [11:0] brupdate_b2_uop_csr_addr;\t// @[core.scala:188:23]\n wire [6:0] brupdate_b2_uop_rob_idx;\t// @[core.scala:188:23]\n wire [4:0] brupdate_b2_uop_ldq_idx;\t// @[core.scala:188:23]\n wire [4:0] brupdate_b2_uop_stq_idx;\t// @[core.scala:188:23]\n wire [1:0] brupdate_b2_uop_rxq_idx;\t// @[core.scala:188:23]\n wire [6:0] brupdate_b2_uop_pdst;\t// @[core.scala:188:23]\n wire [6:0] brupdate_b2_uop_prs1;\t// @[core.scala:188:23]\n wire [6:0] brupdate_b2_uop_prs2;\t// @[core.scala:188:23]\n wire [6:0] brupdate_b2_uop_prs3;\t// @[core.scala:188:23]\n wire [4:0] brupdate_b2_uop_ppred;\t// @[core.scala:188:23]\n wire brupdate_b2_uop_prs1_busy;\t// @[core.scala:188:23]\n wire brupdate_b2_uop_prs2_busy;\t// @[core.scala:188:23]\n wire brupdate_b2_uop_prs3_busy;\t// @[core.scala:188:23]\n wire brupdate_b2_uop_ppred_busy;\t// @[core.scala:188:23]\n wire [6:0] brupdate_b2_uop_stale_pdst;\t// @[core.scala:188:23]\n wire brupdate_b2_uop_exception;\t// @[core.scala:188:23]\n wire [63:0] brupdate_b2_uop_exc_cause;\t// @[core.scala:188:23]\n wire brupdate_b2_uop_bypassable;\t// @[core.scala:188:23]\n wire [4:0] brupdate_b2_uop_mem_cmd;\t// @[core.scala:188:23]\n wire [1:0] brupdate_b2_uop_mem_size;\t// @[core.scala:188:23]\n wire brupdate_b2_uop_mem_signed;\t// @[core.scala:188:23]\n wire brupdate_b2_uop_is_fence;\t// @[core.scala:188:23]\n wire brupdate_b2_uop_is_fencei;\t// @[core.scala:188:23]\n wire brupdate_b2_uop_is_amo;\t// @[core.scala:188:23]\n wire brupdate_b2_uop_uses_ldq;\t// @[core.scala:188:23]\n wire brupdate_b2_uop_uses_stq;\t// @[core.scala:188:23]\n wire brupdate_b2_uop_is_sys_pc2epc;\t// @[core.scala:188:23]\n wire brupdate_b2_uop_is_unique;\t// @[core.scala:188:23]\n wire brupdate_b2_uop_flush_on_commit;\t// @[core.scala:188:23]\n wire brupdate_b2_uop_ldst_is_rs1;\t// @[core.scala:188:23]\n wire [5:0] brupdate_b2_uop_ldst;\t// @[core.scala:188:23]\n wire [5:0] brupdate_b2_uop_lrs1;\t// @[core.scala:188:23]\n wire [5:0] brupdate_b2_uop_lrs2;\t// @[core.scala:188:23]\n wire [5:0] brupdate_b2_uop_lrs3;\t// @[core.scala:188:23]\n wire brupdate_b2_uop_ldst_val;\t// @[core.scala:188:23]\n wire [1:0] brupdate_b2_uop_dst_rtype;\t// @[core.scala:188:23]\n wire [1:0] brupdate_b2_uop_lrs1_rtype;\t// @[core.scala:188:23]\n wire [1:0] brupdate_b2_uop_lrs2_rtype;\t// @[core.scala:188:23]\n wire brupdate_b2_uop_frs3_en;\t// @[core.scala:188:23]\n wire brupdate_b2_uop_fp_val;\t// @[core.scala:188:23]\n wire brupdate_b2_uop_fp_single;\t// @[core.scala:188:23]\n wire brupdate_b2_uop_xcpt_pf_if;\t// @[core.scala:188:23]\n wire brupdate_b2_uop_xcpt_ae_if;\t// @[core.scala:188:23]\n wire brupdate_b2_uop_xcpt_ma_if;\t// @[core.scala:188:23]\n wire brupdate_b2_uop_bp_debug_if;\t// @[core.scala:188:23]\n wire brupdate_b2_uop_bp_xcpt_if;\t// @[core.scala:188:23]\n wire [1:0] brupdate_b2_uop_debug_fsrc;\t// @[core.scala:188:23]\n wire [1:0] brupdate_b2_uop_debug_tsrc;\t// @[core.scala:188:23]\n wire brupdate_b2_mispredict;\t// @[core.scala:188:23]\n wire brupdate_b2_taken;\t// @[core.scala:188:23]\n wire [2:0] brupdate_b2_cfi_type;\t// @[core.scala:188:23]\n wire [1:0] brupdate_b2_pc_sel;\t// @[core.scala:188:23]\n wire [39:0] brupdate_b2_jalr_target;\t// @[core.scala:188:23]\n wire [20:0] brupdate_b2_target_offset;\t// @[core.scala:188:23]\n wire _io_ifu_flush_icache_T_13;\t// @[core.scala:390:13]\n wire dis_fire_0;\t// @[core.scala:168:24]\n wire [6:0] dis_uops_0_uopc;\t// @[core.scala:167:24]\n wire [31:0] dis_uops_0_inst;\t// @[core.scala:167:24]\n wire [31:0] dis_uops_0_debug_inst;\t// @[core.scala:167:24]\n wire dis_uops_0_is_rvc;\t// @[core.scala:167:24]\n wire [39:0] dis_uops_0_debug_pc;\t// @[core.scala:167:24]\n wire [2:0] dis_uops_0_iq_type;\t// @[core.scala:167:24]\n wire [9:0] dis_uops_0_fu_code;\t// @[core.scala:167:24]\n wire [3:0] dis_uops_0_ctrl_br_type;\t// @[core.scala:167:24]\n wire [1:0] dis_uops_0_ctrl_op1_sel;\t// @[core.scala:167:24]\n wire [2:0] dis_uops_0_ctrl_op2_sel;\t// @[core.scala:167:24]\n wire [2:0] dis_uops_0_ctrl_imm_sel;\t// @[core.scala:167:24]\n wire [4:0] dis_uops_0_ctrl_op_fcn;\t// @[core.scala:167:24]\n wire dis_uops_0_ctrl_fcn_dw;\t// @[core.scala:167:24]\n wire [2:0] dis_uops_0_ctrl_csr_cmd;\t// @[core.scala:167:24]\n wire dis_uops_0_ctrl_is_load;\t// @[core.scala:167:24]\n wire dis_uops_0_ctrl_is_sta;\t// @[core.scala:167:24]\n wire dis_uops_0_ctrl_is_std;\t// @[core.scala:167:24]\n wire [1:0] dis_uops_0_iw_state;\t// @[core.scala:167:24]\n wire dis_uops_0_iw_p1_poisoned;\t// @[core.scala:167:24]\n wire dis_uops_0_iw_p2_poisoned;\t// @[core.scala:167:24]\n wire dis_uops_0_is_br;\t// @[core.scala:167:24]\n wire dis_uops_0_is_jalr;\t// @[core.scala:167:24]\n wire dis_uops_0_is_jal;\t// @[core.scala:167:24]\n wire dis_uops_0_is_sfb;\t// @[core.scala:167:24]\n wire [15:0] dis_uops_0_br_mask;\t// @[core.scala:167:24]\n wire [3:0] dis_uops_0_br_tag;\t// @[core.scala:167:24]\n wire [4:0] dis_uops_0_ftq_idx;\t// @[core.scala:167:24]\n wire dis_uops_0_edge_inst;\t// @[core.scala:167:24]\n wire [5:0] dis_uops_0_pc_lob;\t// @[core.scala:167:24]\n wire dis_uops_0_taken;\t// @[core.scala:167:24]\n wire [19:0] dis_uops_0_imm_packed;\t// @[core.scala:167:24]\n wire [11:0] dis_uops_0_csr_addr;\t// @[core.scala:167:24]\n wire [6:0] dis_uops_0_rob_idx;\t// @[core.scala:167:24]\n wire [4:0] dis_uops_0_ldq_idx;\t// @[core.scala:167:24]\n wire [4:0] dis_uops_0_stq_idx;\t// @[core.scala:167:24]\n wire [1:0] dis_uops_0_rxq_idx;\t// @[core.scala:167:24]\n wire [6:0] dis_uops_0_pdst;\t// @[core.scala:167:24]\n wire [6:0] dis_uops_0_prs1;\t// @[core.scala:167:24]\n wire [6:0] dis_uops_0_prs2;\t// @[core.scala:167:24]\n wire [6:0] dis_uops_0_prs3;\t// @[core.scala:167:24]\n wire dis_uops_0_prs1_busy;\t// @[core.scala:167:24]\n wire dis_uops_0_prs2_busy;\t// @[core.scala:167:24]\n wire dis_uops_0_prs3_busy;\t// @[core.scala:167:24]\n wire [6:0] dis_uops_0_stale_pdst;\t// @[core.scala:167:24]\n wire dis_uops_0_exception;\t// @[core.scala:167:24]\n wire [63:0] dis_uops_0_exc_cause;\t// @[core.scala:167:24]\n wire dis_uops_0_bypassable;\t// @[core.scala:167:24]\n wire [4:0] dis_uops_0_mem_cmd;\t// @[core.scala:167:24]\n wire [1:0] dis_uops_0_mem_size;\t// @[core.scala:167:24]\n wire dis_uops_0_mem_signed;\t// @[core.scala:167:24]\n wire dis_uops_0_is_fence;\t// @[core.scala:167:24]\n wire dis_uops_0_is_fencei;\t// @[core.scala:167:24]\n wire dis_uops_0_is_amo;\t// @[core.scala:167:24]\n wire dis_uops_0_uses_ldq;\t// @[core.scala:167:24]\n wire dis_uops_0_uses_stq;\t// @[core.scala:167:24]\n wire dis_uops_0_is_sys_pc2epc;\t// @[core.scala:167:24]\n wire dis_uops_0_is_unique;\t// @[core.scala:167:24]\n wire dis_uops_0_flush_on_commit;\t// @[core.scala:167:24]\n wire dis_uops_0_ldst_is_rs1;\t// @[core.scala:167:24]\n wire [5:0] dis_uops_0_ldst;\t// @[core.scala:167:24]\n wire [5:0] dis_uops_0_lrs1;\t// @[core.scala:167:24]\n wire [5:0] dis_uops_0_lrs2;\t// @[core.scala:167:24]\n wire [5:0] dis_uops_0_lrs3;\t// @[core.scala:167:24]\n wire dis_uops_0_ldst_val;\t// @[core.scala:167:24]\n wire [1:0] dis_uops_0_dst_rtype;\t// @[core.scala:167:24]\n wire [1:0] dis_uops_0_lrs1_rtype;\t// @[core.scala:167:24]\n wire [1:0] dis_uops_0_lrs2_rtype;\t// @[core.scala:167:24]\n wire dis_uops_0_frs3_en;\t// @[core.scala:167:24]\n wire dis_uops_0_fp_val;\t// @[core.scala:167:24]\n wire dis_uops_0_fp_single;\t// @[core.scala:167:24]\n wire dis_uops_0_xcpt_pf_if;\t// @[core.scala:167:24]\n wire dis_uops_0_xcpt_ae_if;\t// @[core.scala:167:24]\n wire dis_uops_0_xcpt_ma_if;\t// @[core.scala:167:24]\n wire dis_uops_0_bp_debug_if;\t// @[core.scala:167:24]\n wire dis_uops_0_bp_xcpt_if;\t// @[core.scala:167:24]\n wire [1:0] dis_uops_0_debug_fsrc;\t// @[core.scala:167:24]\n wire [1:0] dis_uops_0_debug_tsrc;\t// @[core.scala:167:24]\n wire dis_fire_1;\t// @[core.scala:168:24]\n wire [6:0] dis_uops_1_uopc;\t// @[core.scala:167:24]\n wire [31:0] dis_uops_1_inst;\t// @[core.scala:167:24]\n wire [31:0] dis_uops_1_debug_inst;\t// @[core.scala:167:24]\n wire dis_uops_1_is_rvc;\t// @[core.scala:167:24]\n wire [39:0] dis_uops_1_debug_pc;\t// @[core.scala:167:24]\n wire [2:0] dis_uops_1_iq_type;\t// @[core.scala:167:24]\n wire [9:0] dis_uops_1_fu_code;\t// @[core.scala:167:24]\n wire [3:0] dis_uops_1_ctrl_br_type;\t// @[core.scala:167:24]\n wire [1:0] dis_uops_1_ctrl_op1_sel;\t// @[core.scala:167:24]\n wire [2:0] dis_uops_1_ctrl_op2_sel;\t// @[core.scala:167:24]\n wire [2:0] dis_uops_1_ctrl_imm_sel;\t// @[core.scala:167:24]\n wire [4:0] dis_uops_1_ctrl_op_fcn;\t// @[core.scala:167:24]\n wire dis_uops_1_ctrl_fcn_dw;\t// @[core.scala:167:24]\n wire [2:0] dis_uops_1_ctrl_csr_cmd;\t// @[core.scala:167:24]\n wire dis_uops_1_ctrl_is_load;\t// @[core.scala:167:24]\n wire dis_uops_1_ctrl_is_sta;\t// @[core.scala:167:24]\n wire dis_uops_1_ctrl_is_std;\t// @[core.scala:167:24]\n wire [1:0] dis_uops_1_iw_state;\t// @[core.scala:167:24]\n wire dis_uops_1_iw_p1_poisoned;\t// @[core.scala:167:24]\n wire dis_uops_1_iw_p2_poisoned;\t// @[core.scala:167:24]\n wire dis_uops_1_is_br;\t// @[core.scala:167:24]\n wire dis_uops_1_is_jalr;\t// @[core.scala:167:24]\n wire dis_uops_1_is_jal;\t// @[core.scala:167:24]\n wire dis_uops_1_is_sfb;\t// @[core.scala:167:24]\n wire [15:0] dis_uops_1_br_mask;\t// @[core.scala:167:24]\n wire [3:0] dis_uops_1_br_tag;\t// @[core.scala:167:24]\n wire [4:0] dis_uops_1_ftq_idx;\t// @[core.scala:167:24]\n wire dis_uops_1_edge_inst;\t// @[core.scala:167:24]\n wire [5:0] dis_uops_1_pc_lob;\t// @[core.scala:167:24]\n wire dis_uops_1_taken;\t// @[core.scala:167:24]\n wire [19:0] dis_uops_1_imm_packed;\t// @[core.scala:167:24]\n wire [11:0] dis_uops_1_csr_addr;\t// @[core.scala:167:24]\n wire [6:0] dis_uops_1_rob_idx;\t// @[core.scala:167:24]\n wire [4:0] dis_uops_1_ldq_idx;\t// @[core.scala:167:24]\n wire [4:0] dis_uops_1_stq_idx;\t// @[core.scala:167:24]\n wire [1:0] dis_uops_1_rxq_idx;\t// @[core.scala:167:24]\n wire [6:0] dis_uops_1_pdst;\t// @[core.scala:167:24]\n wire [6:0] dis_uops_1_prs1;\t// @[core.scala:167:24]\n wire [6:0] dis_uops_1_prs2;\t// @[core.scala:167:24]\n wire [6:0] dis_uops_1_prs3;\t// @[core.scala:167:24]\n wire dis_uops_1_prs1_busy;\t// @[core.scala:167:24]\n wire dis_uops_1_prs2_busy;\t// @[core.scala:167:24]\n wire dis_uops_1_prs3_busy;\t// @[core.scala:167:24]\n wire [6:0] dis_uops_1_stale_pdst;\t// @[core.scala:167:24]\n wire dis_uops_1_exception;\t// @[core.scala:167:24]\n wire [63:0] dis_uops_1_exc_cause;\t// @[core.scala:167:24]\n wire dis_uops_1_bypassable;\t// @[core.scala:167:24]\n wire [4:0] dis_uops_1_mem_cmd;\t// @[core.scala:167:24]\n wire [1:0] dis_uops_1_mem_size;\t// @[core.scala:167:24]\n wire dis_uops_1_mem_signed;\t// @[core.scala:167:24]\n wire dis_uops_1_is_fence;\t// @[core.scala:167:24]\n wire dis_uops_1_is_fencei;\t// @[core.scala:167:24]\n wire dis_uops_1_is_amo;\t// @[core.scala:167:24]\n wire dis_uops_1_uses_ldq;\t// @[core.scala:167:24]\n wire dis_uops_1_uses_stq;\t// @[core.scala:167:24]\n wire dis_uops_1_is_sys_pc2epc;\t// @[core.scala:167:24]\n wire dis_uops_1_is_unique;\t// @[core.scala:167:24]\n wire dis_uops_1_flush_on_commit;\t// @[core.scala:167:24]\n wire dis_uops_1_ldst_is_rs1;\t// @[core.scala:167:24]\n wire [5:0] dis_uops_1_ldst;\t// @[core.scala:167:24]\n wire [5:0] dis_uops_1_lrs1;\t// @[core.scala:167:24]\n wire [5:0] dis_uops_1_lrs2;\t// @[core.scala:167:24]\n wire [5:0] dis_uops_1_lrs3;\t// @[core.scala:167:24]\n wire dis_uops_1_ldst_val;\t// @[core.scala:167:24]\n wire [1:0] dis_uops_1_dst_rtype;\t// @[core.scala:167:24]\n wire [1:0] dis_uops_1_lrs1_rtype;\t// @[core.scala:167:24]\n wire [1:0] dis_uops_1_lrs2_rtype;\t// @[core.scala:167:24]\n wire dis_uops_1_frs3_en;\t// @[core.scala:167:24]\n wire dis_uops_1_fp_val;\t// @[core.scala:167:24]\n wire dis_uops_1_fp_single;\t// @[core.scala:167:24]\n wire dis_uops_1_xcpt_pf_if;\t// @[core.scala:167:24]\n wire dis_uops_1_xcpt_ae_if;\t// @[core.scala:167:24]\n wire dis_uops_1_xcpt_ma_if;\t// @[core.scala:167:24]\n wire dis_uops_1_bp_debug_if;\t// @[core.scala:167:24]\n wire dis_uops_1_bp_xcpt_if;\t// @[core.scala:167:24]\n wire [1:0] dis_uops_1_debug_fsrc;\t// @[core.scala:167:24]\n wire [1:0] dis_uops_1_debug_tsrc;\t// @[core.scala:167:24]\n wire dis_fire_2;\t// @[core.scala:168:24]\n wire [6:0] dis_uops_2_uopc;\t// @[core.scala:167:24]\n wire [31:0] dis_uops_2_inst;\t// @[core.scala:167:24]\n wire [31:0] dis_uops_2_debug_inst;\t// @[core.scala:167:24]\n wire dis_uops_2_is_rvc;\t// @[core.scala:167:24]\n wire [39:0] dis_uops_2_debug_pc;\t// @[core.scala:167:24]\n wire [2:0] dis_uops_2_iq_type;\t// @[core.scala:167:24]\n wire [9:0] dis_uops_2_fu_code;\t// @[core.scala:167:24]\n wire [3:0] dis_uops_2_ctrl_br_type;\t// @[core.scala:167:24]\n wire [1:0] dis_uops_2_ctrl_op1_sel;\t// @[core.scala:167:24]\n wire [2:0] dis_uops_2_ctrl_op2_sel;\t// @[core.scala:167:24]\n wire [2:0] dis_uops_2_ctrl_imm_sel;\t// @[core.scala:167:24]\n wire [4:0] dis_uops_2_ctrl_op_fcn;\t// @[core.scala:167:24]\n wire dis_uops_2_ctrl_fcn_dw;\t// @[core.scala:167:24]\n wire [2:0] dis_uops_2_ctrl_csr_cmd;\t// @[core.scala:167:24]\n wire dis_uops_2_ctrl_is_load;\t// @[core.scala:167:24]\n wire dis_uops_2_ctrl_is_sta;\t// @[core.scala:167:24]\n wire dis_uops_2_ctrl_is_std;\t// @[core.scala:167:24]\n wire [1:0] dis_uops_2_iw_state;\t// @[core.scala:167:24]\n wire dis_uops_2_iw_p1_poisoned;\t// @[core.scala:167:24]\n wire dis_uops_2_iw_p2_poisoned;\t// @[core.scala:167:24]\n wire dis_uops_2_is_br;\t// @[core.scala:167:24]\n wire dis_uops_2_is_jalr;\t// @[core.scala:167:24]\n wire dis_uops_2_is_jal;\t// @[core.scala:167:24]\n wire dis_uops_2_is_sfb;\t// @[core.scala:167:24]\n wire [15:0] dis_uops_2_br_mask;\t// @[core.scala:167:24]\n wire [3:0] dis_uops_2_br_tag;\t// @[core.scala:167:24]\n wire [4:0] dis_uops_2_ftq_idx;\t// @[core.scala:167:24]\n wire dis_uops_2_edge_inst;\t// @[core.scala:167:24]\n wire [5:0] dis_uops_2_pc_lob;\t// @[core.scala:167:24]\n wire dis_uops_2_taken;\t// @[core.scala:167:24]\n wire [19:0] dis_uops_2_imm_packed;\t// @[core.scala:167:24]\n wire [11:0] dis_uops_2_csr_addr;\t// @[core.scala:167:24]\n wire [6:0] dis_uops_2_rob_idx;\t// @[core.scala:167:24]\n wire [4:0] dis_uops_2_ldq_idx;\t// @[core.scala:167:24]\n wire [4:0] dis_uops_2_stq_idx;\t// @[core.scala:167:24]\n wire [1:0] dis_uops_2_rxq_idx;\t// @[core.scala:167:24]\n wire [6:0] dis_uops_2_pdst;\t// @[core.scala:167:24]\n wire [6:0] dis_uops_2_prs1;\t// @[core.scala:167:24]\n wire [6:0] dis_uops_2_prs2;\t// @[core.scala:167:24]\n wire [6:0] dis_uops_2_prs3;\t// @[core.scala:167:24]\n wire dis_uops_2_prs1_busy;\t// @[core.scala:167:24]\n wire dis_uops_2_prs2_busy;\t// @[core.scala:167:24]\n wire dis_uops_2_prs3_busy;\t// @[core.scala:167:24]\n wire [6:0] dis_uops_2_stale_pdst;\t// @[core.scala:167:24]\n wire dis_uops_2_exception;\t// @[core.scala:167:24]\n wire [63:0] dis_uops_2_exc_cause;\t// @[core.scala:167:24]\n wire dis_uops_2_bypassable;\t// @[core.scala:167:24]\n wire [4:0] dis_uops_2_mem_cmd;\t// @[core.scala:167:24]\n wire [1:0] dis_uops_2_mem_size;\t// @[core.scala:167:24]\n wire dis_uops_2_mem_signed;\t// @[core.scala:167:24]\n wire dis_uops_2_is_fence;\t// @[core.scala:167:24]\n wire dis_uops_2_is_fencei;\t// @[core.scala:167:24]\n wire dis_uops_2_is_amo;\t// @[core.scala:167:24]\n wire dis_uops_2_uses_ldq;\t// @[core.scala:167:24]\n wire dis_uops_2_uses_stq;\t// @[core.scala:167:24]\n wire dis_uops_2_is_sys_pc2epc;\t// @[core.scala:167:24]\n wire dis_uops_2_is_unique;\t// @[core.scala:167:24]\n wire dis_uops_2_flush_on_commit;\t// @[core.scala:167:24]\n wire dis_uops_2_ldst_is_rs1;\t// @[core.scala:167:24]\n wire [5:0] dis_uops_2_ldst;\t// @[core.scala:167:24]\n wire [5:0] dis_uops_2_lrs1;\t// @[core.scala:167:24]\n wire [5:0] dis_uops_2_lrs2;\t// @[core.scala:167:24]\n wire [5:0] dis_uops_2_lrs3;\t// @[core.scala:167:24]\n wire dis_uops_2_ldst_val;\t// @[core.scala:167:24]\n wire [1:0] dis_uops_2_dst_rtype;\t// @[core.scala:167:24]\n wire [1:0] dis_uops_2_lrs1_rtype;\t// @[core.scala:167:24]\n wire [1:0] dis_uops_2_lrs2_rtype;\t// @[core.scala:167:24]\n wire dis_uops_2_frs3_en;\t// @[core.scala:167:24]\n wire dis_uops_2_fp_val;\t// @[core.scala:167:24]\n wire dis_uops_2_fp_single;\t// @[core.scala:167:24]\n wire dis_uops_2_xcpt_pf_if;\t// @[core.scala:167:24]\n wire dis_uops_2_xcpt_ae_if;\t// @[core.scala:167:24]\n wire dis_uops_2_xcpt_ma_if;\t// @[core.scala:167:24]\n wire dis_uops_2_bp_debug_if;\t// @[core.scala:167:24]\n wire dis_uops_2_bp_xcpt_if;\t// @[core.scala:167:24]\n wire [1:0] dis_uops_2_debug_fsrc;\t// @[core.scala:167:24]\n wire [1:0] dis_uops_2_debug_tsrc;\t// @[core.scala:167:24]\n assign dis_uops_0_ldq_idx = io_lsu_dis_ldq_idx_0_0;\t// @[core.scala:51:7, :167:24]\n assign dis_uops_1_ldq_idx = io_lsu_dis_ldq_idx_1_0;\t// @[core.scala:51:7, :167:24]\n assign dis_uops_2_ldq_idx = io_lsu_dis_ldq_idx_2_0;\t// @[core.scala:51:7, :167:24]\n assign dis_uops_0_stq_idx = io_lsu_dis_stq_idx_0_0;\t// @[core.scala:51:7, :167:24]\n assign dis_uops_1_stq_idx = io_lsu_dis_stq_idx_1_0;\t// @[core.scala:51:7, :167:24]\n assign dis_uops_2_stq_idx = io_lsu_dis_stq_idx_2_0;\t// @[core.scala:51:7, :167:24]\n wire _io_lsu_fence_dmem_T_4;\t// @[core.scala:711:101]\n wire io_ifu_fetchpacket_ready_0;\t// @[core.scala:51:7]\n wire [4:0] io_ifu_get_pc_0_ftq_idx_0;\t// @[core.scala:51:7]\n wire [4:0] io_ifu_get_pc_1_ftq_idx_0;\t// @[core.scala:51:7]\n wire io_ifu_status_debug_0;\t// @[core.scala:51:7]\n wire io_ifu_status_cease_0;\t// @[core.scala:51:7]\n wire io_ifu_status_wfi_0;\t// @[core.scala:51:7]\n wire [1:0] io_ifu_status_dprv_0;\t// @[core.scala:51:7]\n wire io_ifu_status_dv_0;\t// @[core.scala:51:7]\n wire [1:0] io_ifu_status_prv_0;\t// @[core.scala:51:7]\n wire io_ifu_status_v_0;\t// @[core.scala:51:7]\n wire io_ifu_status_sd_0;\t// @[core.scala:51:7]\n wire io_ifu_status_mpv_0;\t// @[core.scala:51:7]\n wire io_ifu_status_gva_0;\t// @[core.scala:51:7]\n wire io_ifu_status_tsr_0;\t// @[core.scala:51:7]\n wire io_ifu_status_tw_0;\t// @[core.scala:51:7]\n wire io_ifu_status_tvm_0;\t// @[core.scala:51:7]\n wire io_ifu_status_mxr_0;\t// @[core.scala:51:7]\n wire io_ifu_status_sum_0;\t// @[core.scala:51:7]\n wire io_ifu_status_mprv_0;\t// @[core.scala:51:7]\n wire [1:0] io_ifu_status_fs_0;\t// @[core.scala:51:7]\n wire [1:0] io_ifu_status_mpp_0;\t// @[core.scala:51:7]\n wire io_ifu_status_spp_0;\t// @[core.scala:51:7]\n wire io_ifu_status_mpie_0;\t// @[core.scala:51:7]\n wire io_ifu_status_spie_0;\t// @[core.scala:51:7]\n wire io_ifu_status_mie_0;\t// @[core.scala:51:7]\n wire io_ifu_status_sie_0;\t// @[core.scala:51:7]\n wire [15:0] io_ifu_brupdate_b1_resolve_mask_0;\t// @[core.scala:51:7]\n wire [15:0] io_ifu_brupdate_b1_mispredict_mask_0;\t// @[core.scala:51:7]\n wire [3:0] io_ifu_brupdate_b2_uop_ctrl_br_type_0;\t// @[core.scala:51:7]\n wire [1:0] io_ifu_brupdate_b2_uop_ctrl_op1_sel_0;\t// @[core.scala:51:7]\n wire [2:0] io_ifu_brupdate_b2_uop_ctrl_op2_sel_0;\t// @[core.scala:51:7]\n wire [2:0] io_ifu_brupdate_b2_uop_ctrl_imm_sel_0;\t// @[core.scala:51:7]\n wire [4:0] io_ifu_brupdate_b2_uop_ctrl_op_fcn_0;\t// @[core.scala:51:7]\n wire io_ifu_brupdate_b2_uop_ctrl_fcn_dw_0;\t// @[core.scala:51:7]\n wire [2:0] io_ifu_brupdate_b2_uop_ctrl_csr_cmd_0;\t// @[core.scala:51:7]\n wire io_ifu_brupdate_b2_uop_ctrl_is_load_0;\t// @[core.scala:51:7]\n wire io_ifu_brupdate_b2_uop_ctrl_is_sta_0;\t// @[core.scala:51:7]\n wire io_ifu_brupdate_b2_uop_ctrl_is_std_0;\t// @[core.scala:51:7]\n wire [6:0] io_ifu_brupdate_b2_uop_uopc_0;\t// @[core.scala:51:7]\n wire [31:0] io_ifu_brupdate_b2_uop_inst_0;\t// @[core.scala:51:7]\n wire [31:0] io_ifu_brupdate_b2_uop_debug_inst_0;\t// @[core.scala:51:7]\n wire io_ifu_brupdate_b2_uop_is_rvc_0;\t// @[core.scala:51:7]\n wire [39:0] io_ifu_brupdate_b2_uop_debug_pc_0;\t// @[core.scala:51:7]\n wire [2:0] io_ifu_brupdate_b2_uop_iq_type_0;\t// @[core.scala:51:7]\n wire [9:0] io_ifu_brupdate_b2_uop_fu_code_0;\t// @[core.scala:51:7]\n wire [1:0] io_ifu_brupdate_b2_uop_iw_state_0;\t// @[core.scala:51:7]\n wire io_ifu_brupdate_b2_uop_iw_p1_poisoned_0;\t// @[core.scala:51:7]\n wire io_ifu_brupdate_b2_uop_iw_p2_poisoned_0;\t// @[core.scala:51:7]\n wire io_ifu_brupdate_b2_uop_is_br_0;\t// @[core.scala:51:7]\n wire io_ifu_brupdate_b2_uop_is_jalr_0;\t// @[core.scala:51:7]\n wire io_ifu_brupdate_b2_uop_is_jal_0;\t// @[core.scala:51:7]\n wire io_ifu_brupdate_b2_uop_is_sfb_0;\t// @[core.scala:51:7]\n wire [15:0] io_ifu_brupdate_b2_uop_br_mask_0;\t// @[core.scala:51:7]\n wire [3:0] io_ifu_brupdate_b2_uop_br_tag_0;\t// @[core.scala:51:7]\n wire [4:0] io_ifu_brupdate_b2_uop_ftq_idx_0;\t// @[core.scala:51:7]\n wire io_ifu_brupdate_b2_uop_edge_inst_0;\t// @[core.scala:51:7]\n wire [5:0] io_ifu_brupdate_b2_uop_pc_lob_0;\t// @[core.scala:51:7]\n wire io_ifu_brupdate_b2_uop_taken_0;\t// @[core.scala:51:7]\n wire [19:0] io_ifu_brupdate_b2_uop_imm_packed_0;\t// @[core.scala:51:7]\n wire [11:0] io_ifu_brupdate_b2_uop_csr_addr_0;\t// @[core.scala:51:7]\n wire [6:0] io_ifu_brupdate_b2_uop_rob_idx_0;\t// @[core.scala:51:7]\n wire [4:0] io_ifu_brupdate_b2_uop_ldq_idx_0;\t// @[core.scala:51:7]\n wire [4:0] io_ifu_brupdate_b2_uop_stq_idx_0;\t// @[core.scala:51:7]\n wire [1:0] io_ifu_brupdate_b2_uop_rxq_idx_0;\t// @[core.scala:51:7]\n wire [6:0] io_ifu_brupdate_b2_uop_pdst_0;\t// @[core.scala:51:7]\n wire [6:0] io_ifu_brupdate_b2_uop_prs1_0;\t// @[core.scala:51:7]\n wire [6:0] io_ifu_brupdate_b2_uop_prs2_0;\t// @[core.scala:51:7]\n wire [6:0] io_ifu_brupdate_b2_uop_prs3_0;\t// @[core.scala:51:7]\n wire [4:0] io_ifu_brupdate_b2_uop_ppred_0;\t// @[core.scala:51:7]\n wire io_ifu_brupdate_b2_uop_prs1_busy_0;\t// @[core.scala:51:7]\n wire io_ifu_brupdate_b2_uop_prs2_busy_0;\t// @[core.scala:51:7]\n wire io_ifu_brupdate_b2_uop_prs3_busy_0;\t// @[core.scala:51:7]\n wire io_ifu_brupdate_b2_uop_ppred_busy_0;\t// @[core.scala:51:7]\n wire [6:0] io_ifu_brupdate_b2_uop_stale_pdst_0;\t// @[core.scala:51:7]\n wire io_ifu_brupdate_b2_uop_exception_0;\t// @[core.scala:51:7]\n wire [63:0] io_ifu_brupdate_b2_uop_exc_cause_0;\t// @[core.scala:51:7]\n wire io_ifu_brupdate_b2_uop_bypassable_0;\t// @[core.scala:51:7]\n wire [4:0] io_ifu_brupdate_b2_uop_mem_cmd_0;\t// @[core.scala:51:7]\n wire [1:0] io_ifu_brupdate_b2_uop_mem_size_0;\t// @[core.scala:51:7]\n wire io_ifu_brupdate_b2_uop_mem_signed_0;\t// @[core.scala:51:7]\n wire io_ifu_brupdate_b2_uop_is_fence_0;\t// @[core.scala:51:7]\n wire io_ifu_brupdate_b2_uop_is_fencei_0;\t// @[core.scala:51:7]\n wire io_ifu_brupdate_b2_uop_is_amo_0;\t// @[core.scala:51:7]\n wire io_ifu_brupdate_b2_uop_uses_ldq_0;\t// @[core.scala:51:7]\n wire io_ifu_brupdate_b2_uop_uses_stq_0;\t// @[core.scala:51:7]\n wire io_ifu_brupdate_b2_uop_is_sys_pc2epc_0;\t// @[core.scala:51:7]\n wire io_ifu_brupdate_b2_uop_is_unique_0;\t// @[core.scala:51:7]\n wire io_ifu_brupdate_b2_uop_flush_on_commit_0;\t// @[core.scala:51:7]\n wire io_ifu_brupdate_b2_uop_ldst_is_rs1_0;\t// @[core.scala:51:7]\n wire [5:0] io_ifu_brupdate_b2_uop_ldst_0;\t// @[core.scala:51:7]\n wire [5:0] io_ifu_brupdate_b2_uop_lrs1_0;\t// @[core.scala:51:7]\n wire [5:0] io_ifu_brupdate_b2_uop_lrs2_0;\t// @[core.scala:51:7]\n wire [5:0] io_ifu_brupdate_b2_uop_lrs3_0;\t// @[core.scala:51:7]\n wire io_ifu_brupdate_b2_uop_ldst_val_0;\t// @[core.scala:51:7]\n wire [1:0] io_ifu_brupdate_b2_uop_dst_rtype_0;\t// @[core.scala:51:7]\n wire [1:0] io_ifu_brupdate_b2_uop_lrs1_rtype_0;\t// @[core.scala:51:7]\n wire [1:0] io_ifu_brupdate_b2_uop_lrs2_rtype_0;\t// @[core.scala:51:7]\n wire io_ifu_brupdate_b2_uop_frs3_en_0;\t// @[core.scala:51:7]\n wire io_ifu_brupdate_b2_uop_fp_val_0;\t// @[core.scala:51:7]\n wire io_ifu_brupdate_b2_uop_fp_single_0;\t// @[core.scala:51:7]\n wire io_ifu_brupdate_b2_uop_xcpt_pf_if_0;\t// @[core.scala:51:7]\n wire io_ifu_brupdate_b2_uop_xcpt_ae_if_0;\t// @[core.scala:51:7]\n wire io_ifu_brupdate_b2_uop_xcpt_ma_if_0;\t// @[core.scala:51:7]\n wire io_ifu_brupdate_b2_uop_bp_debug_if_0;\t// @[core.scala:51:7]\n wire io_ifu_brupdate_b2_uop_bp_xcpt_if_0;\t// @[core.scala:51:7]\n wire [1:0] io_ifu_brupdate_b2_uop_debug_fsrc_0;\t// @[core.scala:51:7]\n wire [1:0] io_ifu_brupdate_b2_uop_debug_tsrc_0;\t// @[core.scala:51:7]\n wire io_ifu_brupdate_b2_valid_0;\t// @[core.scala:51:7]\n wire io_ifu_brupdate_b2_mispredict_0;\t// @[core.scala:51:7]\n wire io_ifu_brupdate_b2_taken_0;\t// @[core.scala:51:7]\n wire [2:0] io_ifu_brupdate_b2_cfi_type_0;\t// @[core.scala:51:7]\n wire [1:0] io_ifu_brupdate_b2_pc_sel_0;\t// @[core.scala:51:7]\n wire [39:0] io_ifu_brupdate_b2_jalr_target_0;\t// @[core.scala:51:7]\n wire [20:0] io_ifu_brupdate_b2_target_offset_0;\t// @[core.scala:51:7]\n wire [63:0] io_ifu_redirect_ghist_old_history_0;\t// @[core.scala:51:7]\n wire io_ifu_redirect_ghist_current_saw_branch_not_taken_0;\t// @[core.scala:51:7]\n wire io_ifu_redirect_ghist_new_saw_branch_not_taken_0;\t// @[core.scala:51:7]\n wire io_ifu_redirect_ghist_new_saw_branch_taken_0;\t// @[core.scala:51:7]\n wire [4:0] io_ifu_redirect_ghist_ras_idx_0;\t// @[core.scala:51:7]\n wire io_ifu_commit_valid_0;\t// @[core.scala:51:7]\n wire [31:0] io_ifu_commit_bits_0;\t// @[core.scala:51:7]\n wire io_ifu_redirect_flush_0;\t// @[core.scala:51:7]\n wire io_ifu_redirect_val_0;\t// @[core.scala:51:7]\n wire [39:0] io_ifu_redirect_pc_0;\t// @[core.scala:51:7]\n wire [4:0] io_ifu_redirect_ftq_idx_0;\t// @[core.scala:51:7]\n wire io_ifu_flush_icache_0;\t// @[core.scala:51:7]\n wire [3:0] io_ptw_ptbr_mode_0;\t// @[core.scala:51:7]\n wire [43:0] io_ptw_ptbr_ppn_0;\t// @[core.scala:51:7]\n wire io_ptw_status_debug_0;\t// @[core.scala:51:7]\n wire io_ptw_status_cease_0;\t// @[core.scala:51:7]\n wire io_ptw_status_wfi_0;\t// @[core.scala:51:7]\n wire [1:0] io_ptw_status_dprv_0;\t// @[core.scala:51:7]\n wire io_ptw_status_dv_0;\t// @[core.scala:51:7]\n wire [1:0] io_ptw_status_prv_0;\t// @[core.scala:51:7]\n wire io_ptw_status_v_0;\t// @[core.scala:51:7]\n wire io_ptw_status_sd_0;\t// @[core.scala:51:7]\n wire io_ptw_status_mpv_0;\t// @[core.scala:51:7]\n wire io_ptw_status_gva_0;\t// @[core.scala:51:7]\n wire io_ptw_status_tsr_0;\t// @[core.scala:51:7]\n wire io_ptw_status_tw_0;\t// @[core.scala:51:7]\n wire io_ptw_status_tvm_0;\t// @[core.scala:51:7]\n wire io_ptw_status_mxr_0;\t// @[core.scala:51:7]\n wire io_ptw_status_sum_0;\t// @[core.scala:51:7]\n wire io_ptw_status_mprv_0;\t// @[core.scala:51:7]\n wire [1:0] io_ptw_status_fs_0;\t// @[core.scala:51:7]\n wire [1:0] io_ptw_status_mpp_0;\t// @[core.scala:51:7]\n wire io_ptw_status_spp_0;\t// @[core.scala:51:7]\n wire io_ptw_status_mpie_0;\t// @[core.scala:51:7]\n wire io_ptw_status_spie_0;\t// @[core.scala:51:7]\n wire io_ptw_status_mie_0;\t// @[core.scala:51:7]\n wire io_ptw_status_sie_0;\t// @[core.scala:51:7]\n wire io_ptw_pmp_0_cfg_l_0;\t// @[core.scala:51:7]\n wire [1:0] io_ptw_pmp_0_cfg_a_0;\t// @[core.scala:51:7]\n wire io_ptw_pmp_0_cfg_x_0;\t// @[core.scala:51:7]\n wire io_ptw_pmp_0_cfg_w_0;\t// @[core.scala:51:7]\n wire io_ptw_pmp_0_cfg_r_0;\t// @[core.scala:51:7]\n wire [29:0] io_ptw_pmp_0_addr_0;\t// @[core.scala:51:7]\n wire [31:0] io_ptw_pmp_0_mask_0;\t// @[core.scala:51:7]\n wire io_ptw_pmp_1_cfg_l_0;\t// @[core.scala:51:7]\n wire [1:0] io_ptw_pmp_1_cfg_a_0;\t// @[core.scala:51:7]\n wire io_ptw_pmp_1_cfg_x_0;\t// @[core.scala:51:7]\n wire io_ptw_pmp_1_cfg_w_0;\t// @[core.scala:51:7]\n wire io_ptw_pmp_1_cfg_r_0;\t// @[core.scala:51:7]\n wire [29:0] io_ptw_pmp_1_addr_0;\t// @[core.scala:51:7]\n wire [31:0] io_ptw_pmp_1_mask_0;\t// @[core.scala:51:7]\n wire io_ptw_pmp_2_cfg_l_0;\t// @[core.scala:51:7]\n wire [1:0] io_ptw_pmp_2_cfg_a_0;\t// @[core.scala:51:7]\n wire io_ptw_pmp_2_cfg_x_0;\t// @[core.scala:51:7]\n wire io_ptw_pmp_2_cfg_w_0;\t// @[core.scala:51:7]\n wire io_ptw_pmp_2_cfg_r_0;\t// @[core.scala:51:7]\n wire [29:0] io_ptw_pmp_2_addr_0;\t// @[core.scala:51:7]\n wire [31:0] io_ptw_pmp_2_mask_0;\t// @[core.scala:51:7]\n wire io_ptw_pmp_3_cfg_l_0;\t// @[core.scala:51:7]\n wire [1:0] io_ptw_pmp_3_cfg_a_0;\t// @[core.scala:51:7]\n wire io_ptw_pmp_3_cfg_x_0;\t// @[core.scala:51:7]\n wire io_ptw_pmp_3_cfg_w_0;\t// @[core.scala:51:7]\n wire io_ptw_pmp_3_cfg_r_0;\t// @[core.scala:51:7]\n wire [29:0] io_ptw_pmp_3_addr_0;\t// @[core.scala:51:7]\n wire [31:0] io_ptw_pmp_3_mask_0;\t// @[core.scala:51:7]\n wire io_ptw_pmp_4_cfg_l_0;\t// @[core.scala:51:7]\n wire [1:0] io_ptw_pmp_4_cfg_a_0;\t// @[core.scala:51:7]\n wire io_ptw_pmp_4_cfg_x_0;\t// @[core.scala:51:7]\n wire io_ptw_pmp_4_cfg_w_0;\t// @[core.scala:51:7]\n wire io_ptw_pmp_4_cfg_r_0;\t// @[core.scala:51:7]\n wire [29:0] io_ptw_pmp_4_addr_0;\t// @[core.scala:51:7]\n wire [31:0] io_ptw_pmp_4_mask_0;\t// @[core.scala:51:7]\n wire io_ptw_pmp_5_cfg_l_0;\t// @[core.scala:51:7]\n wire [1:0] io_ptw_pmp_5_cfg_a_0;\t// @[core.scala:51:7]\n wire io_ptw_pmp_5_cfg_x_0;\t// @[core.scala:51:7]\n wire io_ptw_pmp_5_cfg_w_0;\t// @[core.scala:51:7]\n wire io_ptw_pmp_5_cfg_r_0;\t// @[core.scala:51:7]\n wire [29:0] io_ptw_pmp_5_addr_0;\t// @[core.scala:51:7]\n wire [31:0] io_ptw_pmp_5_mask_0;\t// @[core.scala:51:7]\n wire io_ptw_pmp_6_cfg_l_0;\t// @[core.scala:51:7]\n wire [1:0] io_ptw_pmp_6_cfg_a_0;\t// @[core.scala:51:7]\n wire io_ptw_pmp_6_cfg_x_0;\t// @[core.scala:51:7]\n wire io_ptw_pmp_6_cfg_w_0;\t// @[core.scala:51:7]\n wire io_ptw_pmp_6_cfg_r_0;\t// @[core.scala:51:7]\n wire [29:0] io_ptw_pmp_6_addr_0;\t// @[core.scala:51:7]\n wire [31:0] io_ptw_pmp_6_mask_0;\t// @[core.scala:51:7]\n wire io_ptw_pmp_7_cfg_l_0;\t// @[core.scala:51:7]\n wire [1:0] io_ptw_pmp_7_cfg_a_0;\t// @[core.scala:51:7]\n wire io_ptw_pmp_7_cfg_x_0;\t// @[core.scala:51:7]\n wire io_ptw_pmp_7_cfg_w_0;\t// @[core.scala:51:7]\n wire io_ptw_pmp_7_cfg_r_0;\t// @[core.scala:51:7]\n wire [29:0] io_ptw_pmp_7_addr_0;\t// @[core.scala:51:7]\n wire [31:0] io_ptw_pmp_7_mask_0;\t// @[core.scala:51:7]\n wire [3:0] io_lsu_exe_0_req_bits_uop_ctrl_br_type_0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_exe_0_req_bits_uop_ctrl_op1_sel_0;\t// @[core.scala:51:7]\n wire [2:0] io_lsu_exe_0_req_bits_uop_ctrl_op2_sel_0;\t// @[core.scala:51:7]\n wire [2:0] io_lsu_exe_0_req_bits_uop_ctrl_imm_sel_0;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_exe_0_req_bits_uop_ctrl_op_fcn_0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_req_bits_uop_ctrl_fcn_dw_0;\t// @[core.scala:51:7]\n wire [2:0] io_lsu_exe_0_req_bits_uop_ctrl_csr_cmd_0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_req_bits_uop_ctrl_is_load_0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_req_bits_uop_ctrl_is_sta_0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_req_bits_uop_ctrl_is_std_0;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_exe_0_req_bits_uop_uopc_0;\t// @[core.scala:51:7]\n wire [31:0] io_lsu_exe_0_req_bits_uop_inst_0;\t// @[core.scala:51:7]\n wire [31:0] io_lsu_exe_0_req_bits_uop_debug_inst_0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_req_bits_uop_is_rvc_0;\t// @[core.scala:51:7]\n wire [39:0] io_lsu_exe_0_req_bits_uop_debug_pc_0;\t// @[core.scala:51:7]\n wire [2:0] io_lsu_exe_0_req_bits_uop_iq_type_0;\t// @[core.scala:51:7]\n wire [9:0] io_lsu_exe_0_req_bits_uop_fu_code_0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_exe_0_req_bits_uop_iw_state_0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_req_bits_uop_iw_p1_poisoned_0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_req_bits_uop_iw_p2_poisoned_0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_req_bits_uop_is_br_0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_req_bits_uop_is_jalr_0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_req_bits_uop_is_jal_0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_req_bits_uop_is_sfb_0;\t// @[core.scala:51:7]\n wire [15:0] io_lsu_exe_0_req_bits_uop_br_mask_0;\t// @[core.scala:51:7]\n wire [3:0] io_lsu_exe_0_req_bits_uop_br_tag_0;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_exe_0_req_bits_uop_ftq_idx_0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_req_bits_uop_edge_inst_0;\t// @[core.scala:51:7]\n wire [5:0] io_lsu_exe_0_req_bits_uop_pc_lob_0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_req_bits_uop_taken_0;\t// @[core.scala:51:7]\n wire [19:0] io_lsu_exe_0_req_bits_uop_imm_packed_0;\t// @[core.scala:51:7]\n wire [11:0] io_lsu_exe_0_req_bits_uop_csr_addr_0;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_exe_0_req_bits_uop_rob_idx_0;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_exe_0_req_bits_uop_ldq_idx_0;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_exe_0_req_bits_uop_stq_idx_0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_exe_0_req_bits_uop_rxq_idx_0;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_exe_0_req_bits_uop_pdst_0;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_exe_0_req_bits_uop_prs1_0;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_exe_0_req_bits_uop_prs2_0;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_exe_0_req_bits_uop_prs3_0;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_exe_0_req_bits_uop_ppred_0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_req_bits_uop_prs1_busy_0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_req_bits_uop_prs2_busy_0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_req_bits_uop_prs3_busy_0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_req_bits_uop_ppred_busy_0;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_exe_0_req_bits_uop_stale_pdst_0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_req_bits_uop_exception_0;\t// @[core.scala:51:7]\n wire [63:0] io_lsu_exe_0_req_bits_uop_exc_cause_0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_req_bits_uop_bypassable_0;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_exe_0_req_bits_uop_mem_cmd_0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_exe_0_req_bits_uop_mem_size_0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_req_bits_uop_mem_signed_0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_req_bits_uop_is_fence_0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_req_bits_uop_is_fencei_0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_req_bits_uop_is_amo_0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_req_bits_uop_uses_ldq_0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_req_bits_uop_uses_stq_0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_req_bits_uop_is_sys_pc2epc_0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_req_bits_uop_is_unique_0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_req_bits_uop_flush_on_commit_0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_req_bits_uop_ldst_is_rs1_0;\t// @[core.scala:51:7]\n wire [5:0] io_lsu_exe_0_req_bits_uop_ldst_0;\t// @[core.scala:51:7]\n wire [5:0] io_lsu_exe_0_req_bits_uop_lrs1_0;\t// @[core.scala:51:7]\n wire [5:0] io_lsu_exe_0_req_bits_uop_lrs2_0;\t// @[core.scala:51:7]\n wire [5:0] io_lsu_exe_0_req_bits_uop_lrs3_0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_req_bits_uop_ldst_val_0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_exe_0_req_bits_uop_dst_rtype_0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_exe_0_req_bits_uop_lrs1_rtype_0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_exe_0_req_bits_uop_lrs2_rtype_0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_req_bits_uop_frs3_en_0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_req_bits_uop_fp_val_0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_req_bits_uop_fp_single_0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_req_bits_uop_xcpt_pf_if_0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_req_bits_uop_xcpt_ae_if_0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_req_bits_uop_xcpt_ma_if_0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_req_bits_uop_bp_debug_if_0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_req_bits_uop_bp_xcpt_if_0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_exe_0_req_bits_uop_debug_fsrc_0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_exe_0_req_bits_uop_debug_tsrc_0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_req_bits_mxcpt_valid_0;\t// @[core.scala:51:7]\n wire [24:0] io_lsu_exe_0_req_bits_mxcpt_bits_0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_req_bits_sfence_bits_rs1_0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_req_bits_sfence_bits_rs2_0;\t// @[core.scala:51:7]\n wire [38:0] io_lsu_exe_0_req_bits_sfence_bits_addr_0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_req_bits_sfence_bits_asid_0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_req_bits_sfence_valid_0;\t// @[core.scala:51:7]\n wire [63:0] io_lsu_exe_0_req_bits_data_0;\t// @[core.scala:51:7]\n wire [39:0] io_lsu_exe_0_req_bits_addr_0;\t// @[core.scala:51:7]\n wire io_lsu_exe_0_req_valid_0;\t// @[core.scala:51:7]\n wire [3:0] io_lsu_dis_uops_0_bits_ctrl_br_type_0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_dis_uops_0_bits_ctrl_op1_sel_0;\t// @[core.scala:51:7]\n wire [2:0] io_lsu_dis_uops_0_bits_ctrl_op2_sel_0;\t// @[core.scala:51:7]\n wire [2:0] io_lsu_dis_uops_0_bits_ctrl_imm_sel_0;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_dis_uops_0_bits_ctrl_op_fcn_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_0_bits_ctrl_fcn_dw_0;\t// @[core.scala:51:7]\n wire [2:0] io_lsu_dis_uops_0_bits_ctrl_csr_cmd_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_0_bits_ctrl_is_load_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_0_bits_ctrl_is_sta_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_0_bits_ctrl_is_std_0;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_dis_uops_0_bits_uopc_0;\t// @[core.scala:51:7]\n wire [31:0] io_lsu_dis_uops_0_bits_inst_0;\t// @[core.scala:51:7]\n wire [31:0] io_lsu_dis_uops_0_bits_debug_inst_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_0_bits_is_rvc_0;\t// @[core.scala:51:7]\n wire [39:0] io_lsu_dis_uops_0_bits_debug_pc_0;\t// @[core.scala:51:7]\n wire [2:0] io_lsu_dis_uops_0_bits_iq_type_0;\t// @[core.scala:51:7]\n wire [9:0] io_lsu_dis_uops_0_bits_fu_code_0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_dis_uops_0_bits_iw_state_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_0_bits_iw_p1_poisoned_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_0_bits_iw_p2_poisoned_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_0_bits_is_br_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_0_bits_is_jalr_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_0_bits_is_jal_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_0_bits_is_sfb_0;\t// @[core.scala:51:7]\n wire [15:0] io_lsu_dis_uops_0_bits_br_mask_0;\t// @[core.scala:51:7]\n wire [3:0] io_lsu_dis_uops_0_bits_br_tag_0;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_dis_uops_0_bits_ftq_idx_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_0_bits_edge_inst_0;\t// @[core.scala:51:7]\n wire [5:0] io_lsu_dis_uops_0_bits_pc_lob_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_0_bits_taken_0;\t// @[core.scala:51:7]\n wire [19:0] io_lsu_dis_uops_0_bits_imm_packed_0;\t// @[core.scala:51:7]\n wire [11:0] io_lsu_dis_uops_0_bits_csr_addr_0;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_dis_uops_0_bits_rob_idx_0;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_dis_uops_0_bits_ldq_idx_0;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_dis_uops_0_bits_stq_idx_0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_dis_uops_0_bits_rxq_idx_0;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_dis_uops_0_bits_pdst_0;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_dis_uops_0_bits_prs1_0;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_dis_uops_0_bits_prs2_0;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_dis_uops_0_bits_prs3_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_0_bits_prs1_busy_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_0_bits_prs2_busy_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_0_bits_prs3_busy_0;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_dis_uops_0_bits_stale_pdst_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_0_bits_exception_0;\t// @[core.scala:51:7]\n wire [63:0] io_lsu_dis_uops_0_bits_exc_cause_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_0_bits_bypassable_0;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_dis_uops_0_bits_mem_cmd_0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_dis_uops_0_bits_mem_size_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_0_bits_mem_signed_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_0_bits_is_fence_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_0_bits_is_fencei_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_0_bits_is_amo_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_0_bits_uses_ldq_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_0_bits_uses_stq_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_0_bits_is_sys_pc2epc_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_0_bits_is_unique_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_0_bits_flush_on_commit_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_0_bits_ldst_is_rs1_0;\t// @[core.scala:51:7]\n wire [5:0] io_lsu_dis_uops_0_bits_ldst_0;\t// @[core.scala:51:7]\n wire [5:0] io_lsu_dis_uops_0_bits_lrs1_0;\t// @[core.scala:51:7]\n wire [5:0] io_lsu_dis_uops_0_bits_lrs2_0;\t// @[core.scala:51:7]\n wire [5:0] io_lsu_dis_uops_0_bits_lrs3_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_0_bits_ldst_val_0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_dis_uops_0_bits_dst_rtype_0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_dis_uops_0_bits_lrs1_rtype_0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_dis_uops_0_bits_lrs2_rtype_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_0_bits_frs3_en_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_0_bits_fp_val_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_0_bits_fp_single_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_0_bits_xcpt_pf_if_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_0_bits_xcpt_ae_if_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_0_bits_xcpt_ma_if_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_0_bits_bp_debug_if_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_0_bits_bp_xcpt_if_0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_dis_uops_0_bits_debug_fsrc_0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_dis_uops_0_bits_debug_tsrc_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_0_valid_0;\t// @[core.scala:51:7]\n wire [3:0] io_lsu_dis_uops_1_bits_ctrl_br_type_0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_dis_uops_1_bits_ctrl_op1_sel_0;\t// @[core.scala:51:7]\n wire [2:0] io_lsu_dis_uops_1_bits_ctrl_op2_sel_0;\t// @[core.scala:51:7]\n wire [2:0] io_lsu_dis_uops_1_bits_ctrl_imm_sel_0;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_dis_uops_1_bits_ctrl_op_fcn_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_1_bits_ctrl_fcn_dw_0;\t// @[core.scala:51:7]\n wire [2:0] io_lsu_dis_uops_1_bits_ctrl_csr_cmd_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_1_bits_ctrl_is_load_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_1_bits_ctrl_is_sta_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_1_bits_ctrl_is_std_0;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_dis_uops_1_bits_uopc_0;\t// @[core.scala:51:7]\n wire [31:0] io_lsu_dis_uops_1_bits_inst_0;\t// @[core.scala:51:7]\n wire [31:0] io_lsu_dis_uops_1_bits_debug_inst_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_1_bits_is_rvc_0;\t// @[core.scala:51:7]\n wire [39:0] io_lsu_dis_uops_1_bits_debug_pc_0;\t// @[core.scala:51:7]\n wire [2:0] io_lsu_dis_uops_1_bits_iq_type_0;\t// @[core.scala:51:7]\n wire [9:0] io_lsu_dis_uops_1_bits_fu_code_0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_dis_uops_1_bits_iw_state_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_1_bits_iw_p1_poisoned_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_1_bits_iw_p2_poisoned_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_1_bits_is_br_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_1_bits_is_jalr_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_1_bits_is_jal_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_1_bits_is_sfb_0;\t// @[core.scala:51:7]\n wire [15:0] io_lsu_dis_uops_1_bits_br_mask_0;\t// @[core.scala:51:7]\n wire [3:0] io_lsu_dis_uops_1_bits_br_tag_0;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_dis_uops_1_bits_ftq_idx_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_1_bits_edge_inst_0;\t// @[core.scala:51:7]\n wire [5:0] io_lsu_dis_uops_1_bits_pc_lob_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_1_bits_taken_0;\t// @[core.scala:51:7]\n wire [19:0] io_lsu_dis_uops_1_bits_imm_packed_0;\t// @[core.scala:51:7]\n wire [11:0] io_lsu_dis_uops_1_bits_csr_addr_0;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_dis_uops_1_bits_rob_idx_0;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_dis_uops_1_bits_ldq_idx_0;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_dis_uops_1_bits_stq_idx_0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_dis_uops_1_bits_rxq_idx_0;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_dis_uops_1_bits_pdst_0;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_dis_uops_1_bits_prs1_0;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_dis_uops_1_bits_prs2_0;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_dis_uops_1_bits_prs3_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_1_bits_prs1_busy_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_1_bits_prs2_busy_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_1_bits_prs3_busy_0;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_dis_uops_1_bits_stale_pdst_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_1_bits_exception_0;\t// @[core.scala:51:7]\n wire [63:0] io_lsu_dis_uops_1_bits_exc_cause_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_1_bits_bypassable_0;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_dis_uops_1_bits_mem_cmd_0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_dis_uops_1_bits_mem_size_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_1_bits_mem_signed_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_1_bits_is_fence_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_1_bits_is_fencei_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_1_bits_is_amo_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_1_bits_uses_ldq_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_1_bits_uses_stq_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_1_bits_is_sys_pc2epc_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_1_bits_is_unique_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_1_bits_flush_on_commit_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_1_bits_ldst_is_rs1_0;\t// @[core.scala:51:7]\n wire [5:0] io_lsu_dis_uops_1_bits_ldst_0;\t// @[core.scala:51:7]\n wire [5:0] io_lsu_dis_uops_1_bits_lrs1_0;\t// @[core.scala:51:7]\n wire [5:0] io_lsu_dis_uops_1_bits_lrs2_0;\t// @[core.scala:51:7]\n wire [5:0] io_lsu_dis_uops_1_bits_lrs3_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_1_bits_ldst_val_0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_dis_uops_1_bits_dst_rtype_0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_dis_uops_1_bits_lrs1_rtype_0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_dis_uops_1_bits_lrs2_rtype_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_1_bits_frs3_en_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_1_bits_fp_val_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_1_bits_fp_single_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_1_bits_xcpt_pf_if_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_1_bits_xcpt_ae_if_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_1_bits_xcpt_ma_if_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_1_bits_bp_debug_if_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_1_bits_bp_xcpt_if_0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_dis_uops_1_bits_debug_fsrc_0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_dis_uops_1_bits_debug_tsrc_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_1_valid_0;\t// @[core.scala:51:7]\n wire [3:0] io_lsu_dis_uops_2_bits_ctrl_br_type_0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_dis_uops_2_bits_ctrl_op1_sel_0;\t// @[core.scala:51:7]\n wire [2:0] io_lsu_dis_uops_2_bits_ctrl_op2_sel_0;\t// @[core.scala:51:7]\n wire [2:0] io_lsu_dis_uops_2_bits_ctrl_imm_sel_0;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_dis_uops_2_bits_ctrl_op_fcn_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_2_bits_ctrl_fcn_dw_0;\t// @[core.scala:51:7]\n wire [2:0] io_lsu_dis_uops_2_bits_ctrl_csr_cmd_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_2_bits_ctrl_is_load_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_2_bits_ctrl_is_sta_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_2_bits_ctrl_is_std_0;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_dis_uops_2_bits_uopc_0;\t// @[core.scala:51:7]\n wire [31:0] io_lsu_dis_uops_2_bits_inst_0;\t// @[core.scala:51:7]\n wire [31:0] io_lsu_dis_uops_2_bits_debug_inst_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_2_bits_is_rvc_0;\t// @[core.scala:51:7]\n wire [39:0] io_lsu_dis_uops_2_bits_debug_pc_0;\t// @[core.scala:51:7]\n wire [2:0] io_lsu_dis_uops_2_bits_iq_type_0;\t// @[core.scala:51:7]\n wire [9:0] io_lsu_dis_uops_2_bits_fu_code_0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_dis_uops_2_bits_iw_state_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_2_bits_iw_p1_poisoned_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_2_bits_iw_p2_poisoned_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_2_bits_is_br_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_2_bits_is_jalr_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_2_bits_is_jal_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_2_bits_is_sfb_0;\t// @[core.scala:51:7]\n wire [15:0] io_lsu_dis_uops_2_bits_br_mask_0;\t// @[core.scala:51:7]\n wire [3:0] io_lsu_dis_uops_2_bits_br_tag_0;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_dis_uops_2_bits_ftq_idx_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_2_bits_edge_inst_0;\t// @[core.scala:51:7]\n wire [5:0] io_lsu_dis_uops_2_bits_pc_lob_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_2_bits_taken_0;\t// @[core.scala:51:7]\n wire [19:0] io_lsu_dis_uops_2_bits_imm_packed_0;\t// @[core.scala:51:7]\n wire [11:0] io_lsu_dis_uops_2_bits_csr_addr_0;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_dis_uops_2_bits_rob_idx_0;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_dis_uops_2_bits_ldq_idx_0;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_dis_uops_2_bits_stq_idx_0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_dis_uops_2_bits_rxq_idx_0;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_dis_uops_2_bits_pdst_0;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_dis_uops_2_bits_prs1_0;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_dis_uops_2_bits_prs2_0;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_dis_uops_2_bits_prs3_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_2_bits_prs1_busy_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_2_bits_prs2_busy_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_2_bits_prs3_busy_0;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_dis_uops_2_bits_stale_pdst_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_2_bits_exception_0;\t// @[core.scala:51:7]\n wire [63:0] io_lsu_dis_uops_2_bits_exc_cause_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_2_bits_bypassable_0;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_dis_uops_2_bits_mem_cmd_0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_dis_uops_2_bits_mem_size_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_2_bits_mem_signed_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_2_bits_is_fence_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_2_bits_is_fencei_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_2_bits_is_amo_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_2_bits_uses_ldq_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_2_bits_uses_stq_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_2_bits_is_sys_pc2epc_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_2_bits_is_unique_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_2_bits_flush_on_commit_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_2_bits_ldst_is_rs1_0;\t// @[core.scala:51:7]\n wire [5:0] io_lsu_dis_uops_2_bits_ldst_0;\t// @[core.scala:51:7]\n wire [5:0] io_lsu_dis_uops_2_bits_lrs1_0;\t// @[core.scala:51:7]\n wire [5:0] io_lsu_dis_uops_2_bits_lrs2_0;\t// @[core.scala:51:7]\n wire [5:0] io_lsu_dis_uops_2_bits_lrs3_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_2_bits_ldst_val_0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_dis_uops_2_bits_dst_rtype_0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_dis_uops_2_bits_lrs1_rtype_0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_dis_uops_2_bits_lrs2_rtype_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_2_bits_frs3_en_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_2_bits_fp_val_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_2_bits_fp_single_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_2_bits_xcpt_pf_if_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_2_bits_xcpt_ae_if_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_2_bits_xcpt_ma_if_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_2_bits_bp_debug_if_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_2_bits_bp_xcpt_if_0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_dis_uops_2_bits_debug_fsrc_0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_dis_uops_2_bits_debug_tsrc_0;\t// @[core.scala:51:7]\n wire io_lsu_dis_uops_2_valid_0;\t// @[core.scala:51:7]\n wire [3:0] io_lsu_fp_stdata_bits_uop_ctrl_br_type_0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_fp_stdata_bits_uop_ctrl_op1_sel_0;\t// @[core.scala:51:7]\n wire [2:0] io_lsu_fp_stdata_bits_uop_ctrl_op2_sel_0;\t// @[core.scala:51:7]\n wire [2:0] io_lsu_fp_stdata_bits_uop_ctrl_imm_sel_0;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_fp_stdata_bits_uop_ctrl_op_fcn_0;\t// @[core.scala:51:7]\n wire io_lsu_fp_stdata_bits_uop_ctrl_fcn_dw_0;\t// @[core.scala:51:7]\n wire [2:0] io_lsu_fp_stdata_bits_uop_ctrl_csr_cmd_0;\t// @[core.scala:51:7]\n wire io_lsu_fp_stdata_bits_uop_ctrl_is_load_0;\t// @[core.scala:51:7]\n wire io_lsu_fp_stdata_bits_uop_ctrl_is_sta_0;\t// @[core.scala:51:7]\n wire io_lsu_fp_stdata_bits_uop_ctrl_is_std_0;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_fp_stdata_bits_uop_uopc_0;\t// @[core.scala:51:7]\n wire [31:0] io_lsu_fp_stdata_bits_uop_inst_0;\t// @[core.scala:51:7]\n wire [31:0] io_lsu_fp_stdata_bits_uop_debug_inst_0;\t// @[core.scala:51:7]\n wire io_lsu_fp_stdata_bits_uop_is_rvc_0;\t// @[core.scala:51:7]\n wire [39:0] io_lsu_fp_stdata_bits_uop_debug_pc_0;\t// @[core.scala:51:7]\n wire [2:0] io_lsu_fp_stdata_bits_uop_iq_type_0;\t// @[core.scala:51:7]\n wire [9:0] io_lsu_fp_stdata_bits_uop_fu_code_0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_fp_stdata_bits_uop_iw_state_0;\t// @[core.scala:51:7]\n wire io_lsu_fp_stdata_bits_uop_iw_p1_poisoned_0;\t// @[core.scala:51:7]\n wire io_lsu_fp_stdata_bits_uop_iw_p2_poisoned_0;\t// @[core.scala:51:7]\n wire io_lsu_fp_stdata_bits_uop_is_br_0;\t// @[core.scala:51:7]\n wire io_lsu_fp_stdata_bits_uop_is_jalr_0;\t// @[core.scala:51:7]\n wire io_lsu_fp_stdata_bits_uop_is_jal_0;\t// @[core.scala:51:7]\n wire io_lsu_fp_stdata_bits_uop_is_sfb_0;\t// @[core.scala:51:7]\n wire [15:0] io_lsu_fp_stdata_bits_uop_br_mask_0;\t// @[core.scala:51:7]\n wire [3:0] io_lsu_fp_stdata_bits_uop_br_tag_0;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_fp_stdata_bits_uop_ftq_idx_0;\t// @[core.scala:51:7]\n wire io_lsu_fp_stdata_bits_uop_edge_inst_0;\t// @[core.scala:51:7]\n wire [5:0] io_lsu_fp_stdata_bits_uop_pc_lob_0;\t// @[core.scala:51:7]\n wire io_lsu_fp_stdata_bits_uop_taken_0;\t// @[core.scala:51:7]\n wire [19:0] io_lsu_fp_stdata_bits_uop_imm_packed_0;\t// @[core.scala:51:7]\n wire [11:0] io_lsu_fp_stdata_bits_uop_csr_addr_0;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_fp_stdata_bits_uop_rob_idx_0;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_fp_stdata_bits_uop_ldq_idx_0;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_fp_stdata_bits_uop_stq_idx_0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_fp_stdata_bits_uop_rxq_idx_0;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_fp_stdata_bits_uop_pdst_0;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_fp_stdata_bits_uop_prs1_0;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_fp_stdata_bits_uop_prs2_0;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_fp_stdata_bits_uop_prs3_0;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_fp_stdata_bits_uop_ppred_0;\t// @[core.scala:51:7]\n wire io_lsu_fp_stdata_bits_uop_prs1_busy_0;\t// @[core.scala:51:7]\n wire io_lsu_fp_stdata_bits_uop_prs2_busy_0;\t// @[core.scala:51:7]\n wire io_lsu_fp_stdata_bits_uop_prs3_busy_0;\t// @[core.scala:51:7]\n wire io_lsu_fp_stdata_bits_uop_ppred_busy_0;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_fp_stdata_bits_uop_stale_pdst_0;\t// @[core.scala:51:7]\n wire io_lsu_fp_stdata_bits_uop_exception_0;\t// @[core.scala:51:7]\n wire [63:0] io_lsu_fp_stdata_bits_uop_exc_cause_0;\t// @[core.scala:51:7]\n wire io_lsu_fp_stdata_bits_uop_bypassable_0;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_fp_stdata_bits_uop_mem_cmd_0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_fp_stdata_bits_uop_mem_size_0;\t// @[core.scala:51:7]\n wire io_lsu_fp_stdata_bits_uop_mem_signed_0;\t// @[core.scala:51:7]\n wire io_lsu_fp_stdata_bits_uop_is_fence_0;\t// @[core.scala:51:7]\n wire io_lsu_fp_stdata_bits_uop_is_fencei_0;\t// @[core.scala:51:7]\n wire io_lsu_fp_stdata_bits_uop_is_amo_0;\t// @[core.scala:51:7]\n wire io_lsu_fp_stdata_bits_uop_uses_ldq_0;\t// @[core.scala:51:7]\n wire io_lsu_fp_stdata_bits_uop_uses_stq_0;\t// @[core.scala:51:7]\n wire io_lsu_fp_stdata_bits_uop_is_sys_pc2epc_0;\t// @[core.scala:51:7]\n wire io_lsu_fp_stdata_bits_uop_is_unique_0;\t// @[core.scala:51:7]\n wire io_lsu_fp_stdata_bits_uop_flush_on_commit_0;\t// @[core.scala:51:7]\n wire io_lsu_fp_stdata_bits_uop_ldst_is_rs1_0;\t// @[core.scala:51:7]\n wire [5:0] io_lsu_fp_stdata_bits_uop_ldst_0;\t// @[core.scala:51:7]\n wire [5:0] io_lsu_fp_stdata_bits_uop_lrs1_0;\t// @[core.scala:51:7]\n wire [5:0] io_lsu_fp_stdata_bits_uop_lrs2_0;\t// @[core.scala:51:7]\n wire [5:0] io_lsu_fp_stdata_bits_uop_lrs3_0;\t// @[core.scala:51:7]\n wire io_lsu_fp_stdata_bits_uop_ldst_val_0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_fp_stdata_bits_uop_dst_rtype_0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_fp_stdata_bits_uop_lrs1_rtype_0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_fp_stdata_bits_uop_lrs2_rtype_0;\t// @[core.scala:51:7]\n wire io_lsu_fp_stdata_bits_uop_frs3_en_0;\t// @[core.scala:51:7]\n wire io_lsu_fp_stdata_bits_uop_fp_val_0;\t// @[core.scala:51:7]\n wire io_lsu_fp_stdata_bits_uop_fp_single_0;\t// @[core.scala:51:7]\n wire io_lsu_fp_stdata_bits_uop_xcpt_pf_if_0;\t// @[core.scala:51:7]\n wire io_lsu_fp_stdata_bits_uop_xcpt_ae_if_0;\t// @[core.scala:51:7]\n wire io_lsu_fp_stdata_bits_uop_xcpt_ma_if_0;\t// @[core.scala:51:7]\n wire io_lsu_fp_stdata_bits_uop_bp_debug_if_0;\t// @[core.scala:51:7]\n wire io_lsu_fp_stdata_bits_uop_bp_xcpt_if_0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_fp_stdata_bits_uop_debug_fsrc_0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_fp_stdata_bits_uop_debug_tsrc_0;\t// @[core.scala:51:7]\n wire [3:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_br_type_0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_op1_sel_0;\t// @[core.scala:51:7]\n wire [2:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_op2_sel_0;\t// @[core.scala:51:7]\n wire [2:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_imm_sel_0;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_op_fcn_0;\t// @[core.scala:51:7]\n wire io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_fcn_dw_0;\t// @[core.scala:51:7]\n wire [2:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_csr_cmd_0;\t// @[core.scala:51:7]\n wire io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_is_load_0;\t// @[core.scala:51:7]\n wire io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_is_sta_0;\t// @[core.scala:51:7]\n wire io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_is_std_0;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_fp_stdata_bits_fflags_bits_uop_uopc_0;\t// @[core.scala:51:7]\n wire [31:0] io_lsu_fp_stdata_bits_fflags_bits_uop_inst_0;\t// @[core.scala:51:7]\n wire [31:0] io_lsu_fp_stdata_bits_fflags_bits_uop_debug_inst_0;\t// @[core.scala:51:7]\n wire io_lsu_fp_stdata_bits_fflags_bits_uop_is_rvc_0;\t// @[core.scala:51:7]\n wire [39:0] io_lsu_fp_stdata_bits_fflags_bits_uop_debug_pc_0;\t// @[core.scala:51:7]\n wire [2:0] io_lsu_fp_stdata_bits_fflags_bits_uop_iq_type_0;\t// @[core.scala:51:7]\n wire [9:0] io_lsu_fp_stdata_bits_fflags_bits_uop_fu_code_0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_iw_state_0;\t// @[core.scala:51:7]\n wire io_lsu_fp_stdata_bits_fflags_bits_uop_iw_p1_poisoned_0;\t// @[core.scala:51:7]\n wire io_lsu_fp_stdata_bits_fflags_bits_uop_iw_p2_poisoned_0;\t// @[core.scala:51:7]\n wire io_lsu_fp_stdata_bits_fflags_bits_uop_is_br_0;\t// @[core.scala:51:7]\n wire io_lsu_fp_stdata_bits_fflags_bits_uop_is_jalr_0;\t// @[core.scala:51:7]\n wire io_lsu_fp_stdata_bits_fflags_bits_uop_is_jal_0;\t// @[core.scala:51:7]\n wire io_lsu_fp_stdata_bits_fflags_bits_uop_is_sfb_0;\t// @[core.scala:51:7]\n wire [15:0] io_lsu_fp_stdata_bits_fflags_bits_uop_br_mask_0;\t// @[core.scala:51:7]\n wire [3:0] io_lsu_fp_stdata_bits_fflags_bits_uop_br_tag_0;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ftq_idx_0;\t// @[core.scala:51:7]\n wire io_lsu_fp_stdata_bits_fflags_bits_uop_edge_inst_0;\t// @[core.scala:51:7]\n wire [5:0] io_lsu_fp_stdata_bits_fflags_bits_uop_pc_lob_0;\t// @[core.scala:51:7]\n wire io_lsu_fp_stdata_bits_fflags_bits_uop_taken_0;\t// @[core.scala:51:7]\n wire [19:0] io_lsu_fp_stdata_bits_fflags_bits_uop_imm_packed_0;\t// @[core.scala:51:7]\n wire [11:0] io_lsu_fp_stdata_bits_fflags_bits_uop_csr_addr_0;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_fp_stdata_bits_fflags_bits_uop_rob_idx_0;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ldq_idx_0;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_fp_stdata_bits_fflags_bits_uop_stq_idx_0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_rxq_idx_0;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_fp_stdata_bits_fflags_bits_uop_pdst_0;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_fp_stdata_bits_fflags_bits_uop_prs1_0;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_fp_stdata_bits_fflags_bits_uop_prs2_0;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_fp_stdata_bits_fflags_bits_uop_prs3_0;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ppred_0;\t// @[core.scala:51:7]\n wire io_lsu_fp_stdata_bits_fflags_bits_uop_prs1_busy_0;\t// @[core.scala:51:7]\n wire io_lsu_fp_stdata_bits_fflags_bits_uop_prs2_busy_0;\t// @[core.scala:51:7]\n wire io_lsu_fp_stdata_bits_fflags_bits_uop_prs3_busy_0;\t// @[core.scala:51:7]\n wire io_lsu_fp_stdata_bits_fflags_bits_uop_ppred_busy_0;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_fp_stdata_bits_fflags_bits_uop_stale_pdst_0;\t// @[core.scala:51:7]\n wire io_lsu_fp_stdata_bits_fflags_bits_uop_exception_0;\t// @[core.scala:51:7]\n wire [63:0] io_lsu_fp_stdata_bits_fflags_bits_uop_exc_cause_0;\t// @[core.scala:51:7]\n wire io_lsu_fp_stdata_bits_fflags_bits_uop_bypassable_0;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_fp_stdata_bits_fflags_bits_uop_mem_cmd_0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_mem_size_0;\t// @[core.scala:51:7]\n wire io_lsu_fp_stdata_bits_fflags_bits_uop_mem_signed_0;\t// @[core.scala:51:7]\n wire io_lsu_fp_stdata_bits_fflags_bits_uop_is_fence_0;\t// @[core.scala:51:7]\n wire io_lsu_fp_stdata_bits_fflags_bits_uop_is_fencei_0;\t// @[core.scala:51:7]\n wire io_lsu_fp_stdata_bits_fflags_bits_uop_is_amo_0;\t// @[core.scala:51:7]\n wire io_lsu_fp_stdata_bits_fflags_bits_uop_uses_ldq_0;\t// @[core.scala:51:7]\n wire io_lsu_fp_stdata_bits_fflags_bits_uop_uses_stq_0;\t// @[core.scala:51:7]\n wire io_lsu_fp_stdata_bits_fflags_bits_uop_is_sys_pc2epc_0;\t// @[core.scala:51:7]\n wire io_lsu_fp_stdata_bits_fflags_bits_uop_is_unique_0;\t// @[core.scala:51:7]\n wire io_lsu_fp_stdata_bits_fflags_bits_uop_flush_on_commit_0;\t// @[core.scala:51:7]\n wire io_lsu_fp_stdata_bits_fflags_bits_uop_ldst_is_rs1_0;\t// @[core.scala:51:7]\n wire [5:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ldst_0;\t// @[core.scala:51:7]\n wire [5:0] io_lsu_fp_stdata_bits_fflags_bits_uop_lrs1_0;\t// @[core.scala:51:7]\n wire [5:0] io_lsu_fp_stdata_bits_fflags_bits_uop_lrs2_0;\t// @[core.scala:51:7]\n wire [5:0] io_lsu_fp_stdata_bits_fflags_bits_uop_lrs3_0;\t// @[core.scala:51:7]\n wire io_lsu_fp_stdata_bits_fflags_bits_uop_ldst_val_0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_dst_rtype_0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_lrs1_rtype_0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_lrs2_rtype_0;\t// @[core.scala:51:7]\n wire io_lsu_fp_stdata_bits_fflags_bits_uop_frs3_en_0;\t// @[core.scala:51:7]\n wire io_lsu_fp_stdata_bits_fflags_bits_uop_fp_val_0;\t// @[core.scala:51:7]\n wire io_lsu_fp_stdata_bits_fflags_bits_uop_fp_single_0;\t// @[core.scala:51:7]\n wire io_lsu_fp_stdata_bits_fflags_bits_uop_xcpt_pf_if_0;\t// @[core.scala:51:7]\n wire io_lsu_fp_stdata_bits_fflags_bits_uop_xcpt_ae_if_0;\t// @[core.scala:51:7]\n wire io_lsu_fp_stdata_bits_fflags_bits_uop_xcpt_ma_if_0;\t// @[core.scala:51:7]\n wire io_lsu_fp_stdata_bits_fflags_bits_uop_bp_debug_if_0;\t// @[core.scala:51:7]\n wire io_lsu_fp_stdata_bits_fflags_bits_uop_bp_xcpt_if_0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_debug_fsrc_0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_debug_tsrc_0;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_fp_stdata_bits_fflags_bits_flags_0;\t// @[core.scala:51:7]\n wire io_lsu_fp_stdata_bits_fflags_valid_0;\t// @[core.scala:51:7]\n wire [63:0] io_lsu_fp_stdata_bits_data_0;\t// @[core.scala:51:7]\n wire io_lsu_fp_stdata_bits_predicated_0;\t// @[core.scala:51:7]\n wire io_lsu_fp_stdata_valid_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_valids_0_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_valids_1_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_valids_2_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_arch_valids_0_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_arch_valids_1_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_arch_valids_2_0;\t// @[core.scala:51:7]\n wire [3:0] io_lsu_commit_uops_0_ctrl_br_type_0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_commit_uops_0_ctrl_op1_sel_0;\t// @[core.scala:51:7]\n wire [2:0] io_lsu_commit_uops_0_ctrl_op2_sel_0;\t// @[core.scala:51:7]\n wire [2:0] io_lsu_commit_uops_0_ctrl_imm_sel_0;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_commit_uops_0_ctrl_op_fcn_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_0_ctrl_fcn_dw_0;\t// @[core.scala:51:7]\n wire [2:0] io_lsu_commit_uops_0_ctrl_csr_cmd_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_0_ctrl_is_load_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_0_ctrl_is_sta_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_0_ctrl_is_std_0;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_commit_uops_0_uopc_0;\t// @[core.scala:51:7]\n wire [31:0] io_lsu_commit_uops_0_inst_0;\t// @[core.scala:51:7]\n wire [31:0] io_lsu_commit_uops_0_debug_inst_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_0_is_rvc_0;\t// @[core.scala:51:7]\n wire [39:0] io_lsu_commit_uops_0_debug_pc_0;\t// @[core.scala:51:7]\n wire [2:0] io_lsu_commit_uops_0_iq_type_0;\t// @[core.scala:51:7]\n wire [9:0] io_lsu_commit_uops_0_fu_code_0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_commit_uops_0_iw_state_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_0_iw_p1_poisoned_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_0_iw_p2_poisoned_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_0_is_br_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_0_is_jalr_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_0_is_jal_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_0_is_sfb_0;\t// @[core.scala:51:7]\n wire [15:0] io_lsu_commit_uops_0_br_mask_0;\t// @[core.scala:51:7]\n wire [3:0] io_lsu_commit_uops_0_br_tag_0;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_commit_uops_0_ftq_idx_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_0_edge_inst_0;\t// @[core.scala:51:7]\n wire [5:0] io_lsu_commit_uops_0_pc_lob_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_0_taken_0;\t// @[core.scala:51:7]\n wire [19:0] io_lsu_commit_uops_0_imm_packed_0;\t// @[core.scala:51:7]\n wire [11:0] io_lsu_commit_uops_0_csr_addr_0;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_commit_uops_0_rob_idx_0;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_commit_uops_0_ldq_idx_0;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_commit_uops_0_stq_idx_0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_commit_uops_0_rxq_idx_0;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_commit_uops_0_pdst_0;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_commit_uops_0_prs1_0;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_commit_uops_0_prs2_0;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_commit_uops_0_prs3_0;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_commit_uops_0_ppred_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_0_prs1_busy_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_0_prs2_busy_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_0_prs3_busy_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_0_ppred_busy_0;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_commit_uops_0_stale_pdst_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_0_exception_0;\t// @[core.scala:51:7]\n wire [63:0] io_lsu_commit_uops_0_exc_cause_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_0_bypassable_0;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_commit_uops_0_mem_cmd_0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_commit_uops_0_mem_size_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_0_mem_signed_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_0_is_fence_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_0_is_fencei_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_0_is_amo_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_0_uses_ldq_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_0_uses_stq_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_0_is_sys_pc2epc_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_0_is_unique_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_0_flush_on_commit_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_0_ldst_is_rs1_0;\t// @[core.scala:51:7]\n wire [5:0] io_lsu_commit_uops_0_ldst_0;\t// @[core.scala:51:7]\n wire [5:0] io_lsu_commit_uops_0_lrs1_0;\t// @[core.scala:51:7]\n wire [5:0] io_lsu_commit_uops_0_lrs2_0;\t// @[core.scala:51:7]\n wire [5:0] io_lsu_commit_uops_0_lrs3_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_0_ldst_val_0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_commit_uops_0_dst_rtype_0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_commit_uops_0_lrs1_rtype_0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_commit_uops_0_lrs2_rtype_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_0_frs3_en_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_0_fp_val_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_0_fp_single_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_0_xcpt_pf_if_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_0_xcpt_ae_if_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_0_xcpt_ma_if_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_0_bp_debug_if_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_0_bp_xcpt_if_0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_commit_uops_0_debug_fsrc_0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_commit_uops_0_debug_tsrc_0;\t// @[core.scala:51:7]\n wire [3:0] io_lsu_commit_uops_1_ctrl_br_type_0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_commit_uops_1_ctrl_op1_sel_0;\t// @[core.scala:51:7]\n wire [2:0] io_lsu_commit_uops_1_ctrl_op2_sel_0;\t// @[core.scala:51:7]\n wire [2:0] io_lsu_commit_uops_1_ctrl_imm_sel_0;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_commit_uops_1_ctrl_op_fcn_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_1_ctrl_fcn_dw_0;\t// @[core.scala:51:7]\n wire [2:0] io_lsu_commit_uops_1_ctrl_csr_cmd_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_1_ctrl_is_load_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_1_ctrl_is_sta_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_1_ctrl_is_std_0;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_commit_uops_1_uopc_0;\t// @[core.scala:51:7]\n wire [31:0] io_lsu_commit_uops_1_inst_0;\t// @[core.scala:51:7]\n wire [31:0] io_lsu_commit_uops_1_debug_inst_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_1_is_rvc_0;\t// @[core.scala:51:7]\n wire [39:0] io_lsu_commit_uops_1_debug_pc_0;\t// @[core.scala:51:7]\n wire [2:0] io_lsu_commit_uops_1_iq_type_0;\t// @[core.scala:51:7]\n wire [9:0] io_lsu_commit_uops_1_fu_code_0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_commit_uops_1_iw_state_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_1_iw_p1_poisoned_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_1_iw_p2_poisoned_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_1_is_br_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_1_is_jalr_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_1_is_jal_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_1_is_sfb_0;\t// @[core.scala:51:7]\n wire [15:0] io_lsu_commit_uops_1_br_mask_0;\t// @[core.scala:51:7]\n wire [3:0] io_lsu_commit_uops_1_br_tag_0;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_commit_uops_1_ftq_idx_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_1_edge_inst_0;\t// @[core.scala:51:7]\n wire [5:0] io_lsu_commit_uops_1_pc_lob_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_1_taken_0;\t// @[core.scala:51:7]\n wire [19:0] io_lsu_commit_uops_1_imm_packed_0;\t// @[core.scala:51:7]\n wire [11:0] io_lsu_commit_uops_1_csr_addr_0;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_commit_uops_1_rob_idx_0;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_commit_uops_1_ldq_idx_0;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_commit_uops_1_stq_idx_0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_commit_uops_1_rxq_idx_0;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_commit_uops_1_pdst_0;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_commit_uops_1_prs1_0;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_commit_uops_1_prs2_0;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_commit_uops_1_prs3_0;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_commit_uops_1_ppred_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_1_prs1_busy_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_1_prs2_busy_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_1_prs3_busy_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_1_ppred_busy_0;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_commit_uops_1_stale_pdst_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_1_exception_0;\t// @[core.scala:51:7]\n wire [63:0] io_lsu_commit_uops_1_exc_cause_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_1_bypassable_0;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_commit_uops_1_mem_cmd_0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_commit_uops_1_mem_size_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_1_mem_signed_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_1_is_fence_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_1_is_fencei_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_1_is_amo_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_1_uses_ldq_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_1_uses_stq_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_1_is_sys_pc2epc_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_1_is_unique_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_1_flush_on_commit_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_1_ldst_is_rs1_0;\t// @[core.scala:51:7]\n wire [5:0] io_lsu_commit_uops_1_ldst_0;\t// @[core.scala:51:7]\n wire [5:0] io_lsu_commit_uops_1_lrs1_0;\t// @[core.scala:51:7]\n wire [5:0] io_lsu_commit_uops_1_lrs2_0;\t// @[core.scala:51:7]\n wire [5:0] io_lsu_commit_uops_1_lrs3_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_1_ldst_val_0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_commit_uops_1_dst_rtype_0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_commit_uops_1_lrs1_rtype_0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_commit_uops_1_lrs2_rtype_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_1_frs3_en_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_1_fp_val_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_1_fp_single_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_1_xcpt_pf_if_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_1_xcpt_ae_if_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_1_xcpt_ma_if_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_1_bp_debug_if_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_1_bp_xcpt_if_0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_commit_uops_1_debug_fsrc_0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_commit_uops_1_debug_tsrc_0;\t// @[core.scala:51:7]\n wire [3:0] io_lsu_commit_uops_2_ctrl_br_type_0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_commit_uops_2_ctrl_op1_sel_0;\t// @[core.scala:51:7]\n wire [2:0] io_lsu_commit_uops_2_ctrl_op2_sel_0;\t// @[core.scala:51:7]\n wire [2:0] io_lsu_commit_uops_2_ctrl_imm_sel_0;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_commit_uops_2_ctrl_op_fcn_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_2_ctrl_fcn_dw_0;\t// @[core.scala:51:7]\n wire [2:0] io_lsu_commit_uops_2_ctrl_csr_cmd_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_2_ctrl_is_load_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_2_ctrl_is_sta_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_2_ctrl_is_std_0;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_commit_uops_2_uopc_0;\t// @[core.scala:51:7]\n wire [31:0] io_lsu_commit_uops_2_inst_0;\t// @[core.scala:51:7]\n wire [31:0] io_lsu_commit_uops_2_debug_inst_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_2_is_rvc_0;\t// @[core.scala:51:7]\n wire [39:0] io_lsu_commit_uops_2_debug_pc_0;\t// @[core.scala:51:7]\n wire [2:0] io_lsu_commit_uops_2_iq_type_0;\t// @[core.scala:51:7]\n wire [9:0] io_lsu_commit_uops_2_fu_code_0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_commit_uops_2_iw_state_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_2_iw_p1_poisoned_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_2_iw_p2_poisoned_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_2_is_br_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_2_is_jalr_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_2_is_jal_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_2_is_sfb_0;\t// @[core.scala:51:7]\n wire [15:0] io_lsu_commit_uops_2_br_mask_0;\t// @[core.scala:51:7]\n wire [3:0] io_lsu_commit_uops_2_br_tag_0;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_commit_uops_2_ftq_idx_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_2_edge_inst_0;\t// @[core.scala:51:7]\n wire [5:0] io_lsu_commit_uops_2_pc_lob_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_2_taken_0;\t// @[core.scala:51:7]\n wire [19:0] io_lsu_commit_uops_2_imm_packed_0;\t// @[core.scala:51:7]\n wire [11:0] io_lsu_commit_uops_2_csr_addr_0;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_commit_uops_2_rob_idx_0;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_commit_uops_2_ldq_idx_0;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_commit_uops_2_stq_idx_0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_commit_uops_2_rxq_idx_0;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_commit_uops_2_pdst_0;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_commit_uops_2_prs1_0;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_commit_uops_2_prs2_0;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_commit_uops_2_prs3_0;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_commit_uops_2_ppred_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_2_prs1_busy_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_2_prs2_busy_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_2_prs3_busy_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_2_ppred_busy_0;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_commit_uops_2_stale_pdst_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_2_exception_0;\t// @[core.scala:51:7]\n wire [63:0] io_lsu_commit_uops_2_exc_cause_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_2_bypassable_0;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_commit_uops_2_mem_cmd_0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_commit_uops_2_mem_size_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_2_mem_signed_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_2_is_fence_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_2_is_fencei_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_2_is_amo_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_2_uses_ldq_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_2_uses_stq_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_2_is_sys_pc2epc_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_2_is_unique_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_2_flush_on_commit_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_2_ldst_is_rs1_0;\t// @[core.scala:51:7]\n wire [5:0] io_lsu_commit_uops_2_ldst_0;\t// @[core.scala:51:7]\n wire [5:0] io_lsu_commit_uops_2_lrs1_0;\t// @[core.scala:51:7]\n wire [5:0] io_lsu_commit_uops_2_lrs2_0;\t// @[core.scala:51:7]\n wire [5:0] io_lsu_commit_uops_2_lrs3_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_2_ldst_val_0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_commit_uops_2_dst_rtype_0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_commit_uops_2_lrs1_rtype_0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_commit_uops_2_lrs2_rtype_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_2_frs3_en_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_2_fp_val_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_2_fp_single_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_2_xcpt_pf_if_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_2_xcpt_ae_if_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_2_xcpt_ma_if_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_2_bp_debug_if_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_uops_2_bp_xcpt_if_0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_commit_uops_2_debug_fsrc_0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_commit_uops_2_debug_tsrc_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_fflags_valid_0;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_commit_fflags_bits_0;\t// @[core.scala:51:7]\n wire [31:0] io_lsu_commit_debug_insts_0_0;\t// @[core.scala:51:7]\n wire [31:0] io_lsu_commit_debug_insts_1_0;\t// @[core.scala:51:7]\n wire [31:0] io_lsu_commit_debug_insts_2_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_rbk_valids_0_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_rbk_valids_1_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_rbk_valids_2_0;\t// @[core.scala:51:7]\n wire [63:0] io_lsu_commit_debug_wdata_0_0;\t// @[core.scala:51:7]\n wire [63:0] io_lsu_commit_debug_wdata_1_0;\t// @[core.scala:51:7]\n wire [63:0] io_lsu_commit_debug_wdata_2_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_rollback_0;\t// @[core.scala:51:7]\n wire [15:0] io_lsu_brupdate_b1_resolve_mask_0;\t// @[core.scala:51:7]\n wire [15:0] io_lsu_brupdate_b1_mispredict_mask_0;\t// @[core.scala:51:7]\n wire [3:0] io_lsu_brupdate_b2_uop_ctrl_br_type_0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_brupdate_b2_uop_ctrl_op1_sel_0;\t// @[core.scala:51:7]\n wire [2:0] io_lsu_brupdate_b2_uop_ctrl_op2_sel_0;\t// @[core.scala:51:7]\n wire [2:0] io_lsu_brupdate_b2_uop_ctrl_imm_sel_0;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_brupdate_b2_uop_ctrl_op_fcn_0;\t// @[core.scala:51:7]\n wire io_lsu_brupdate_b2_uop_ctrl_fcn_dw_0;\t// @[core.scala:51:7]\n wire [2:0] io_lsu_brupdate_b2_uop_ctrl_csr_cmd_0;\t// @[core.scala:51:7]\n wire io_lsu_brupdate_b2_uop_ctrl_is_load_0;\t// @[core.scala:51:7]\n wire io_lsu_brupdate_b2_uop_ctrl_is_sta_0;\t// @[core.scala:51:7]\n wire io_lsu_brupdate_b2_uop_ctrl_is_std_0;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_brupdate_b2_uop_uopc_0;\t// @[core.scala:51:7]\n wire [31:0] io_lsu_brupdate_b2_uop_inst_0;\t// @[core.scala:51:7]\n wire [31:0] io_lsu_brupdate_b2_uop_debug_inst_0;\t// @[core.scala:51:7]\n wire io_lsu_brupdate_b2_uop_is_rvc_0;\t// @[core.scala:51:7]\n wire [39:0] io_lsu_brupdate_b2_uop_debug_pc_0;\t// @[core.scala:51:7]\n wire [2:0] io_lsu_brupdate_b2_uop_iq_type_0;\t// @[core.scala:51:7]\n wire [9:0] io_lsu_brupdate_b2_uop_fu_code_0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_brupdate_b2_uop_iw_state_0;\t// @[core.scala:51:7]\n wire io_lsu_brupdate_b2_uop_iw_p1_poisoned_0;\t// @[core.scala:51:7]\n wire io_lsu_brupdate_b2_uop_iw_p2_poisoned_0;\t// @[core.scala:51:7]\n wire io_lsu_brupdate_b2_uop_is_br_0;\t// @[core.scala:51:7]\n wire io_lsu_brupdate_b2_uop_is_jalr_0;\t// @[core.scala:51:7]\n wire io_lsu_brupdate_b2_uop_is_jal_0;\t// @[core.scala:51:7]\n wire io_lsu_brupdate_b2_uop_is_sfb_0;\t// @[core.scala:51:7]\n wire [15:0] io_lsu_brupdate_b2_uop_br_mask_0;\t// @[core.scala:51:7]\n wire [3:0] io_lsu_brupdate_b2_uop_br_tag_0;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_brupdate_b2_uop_ftq_idx_0;\t// @[core.scala:51:7]\n wire io_lsu_brupdate_b2_uop_edge_inst_0;\t// @[core.scala:51:7]\n wire [5:0] io_lsu_brupdate_b2_uop_pc_lob_0;\t// @[core.scala:51:7]\n wire io_lsu_brupdate_b2_uop_taken_0;\t// @[core.scala:51:7]\n wire [19:0] io_lsu_brupdate_b2_uop_imm_packed_0;\t// @[core.scala:51:7]\n wire [11:0] io_lsu_brupdate_b2_uop_csr_addr_0;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_brupdate_b2_uop_rob_idx_0;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_brupdate_b2_uop_ldq_idx_0;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_brupdate_b2_uop_stq_idx_0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_brupdate_b2_uop_rxq_idx_0;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_brupdate_b2_uop_pdst_0;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_brupdate_b2_uop_prs1_0;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_brupdate_b2_uop_prs2_0;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_brupdate_b2_uop_prs3_0;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_brupdate_b2_uop_ppred_0;\t// @[core.scala:51:7]\n wire io_lsu_brupdate_b2_uop_prs1_busy_0;\t// @[core.scala:51:7]\n wire io_lsu_brupdate_b2_uop_prs2_busy_0;\t// @[core.scala:51:7]\n wire io_lsu_brupdate_b2_uop_prs3_busy_0;\t// @[core.scala:51:7]\n wire io_lsu_brupdate_b2_uop_ppred_busy_0;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_brupdate_b2_uop_stale_pdst_0;\t// @[core.scala:51:7]\n wire io_lsu_brupdate_b2_uop_exception_0;\t// @[core.scala:51:7]\n wire [63:0] io_lsu_brupdate_b2_uop_exc_cause_0;\t// @[core.scala:51:7]\n wire io_lsu_brupdate_b2_uop_bypassable_0;\t// @[core.scala:51:7]\n wire [4:0] io_lsu_brupdate_b2_uop_mem_cmd_0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_brupdate_b2_uop_mem_size_0;\t// @[core.scala:51:7]\n wire io_lsu_brupdate_b2_uop_mem_signed_0;\t// @[core.scala:51:7]\n wire io_lsu_brupdate_b2_uop_is_fence_0;\t// @[core.scala:51:7]\n wire io_lsu_brupdate_b2_uop_is_fencei_0;\t// @[core.scala:51:7]\n wire io_lsu_brupdate_b2_uop_is_amo_0;\t// @[core.scala:51:7]\n wire io_lsu_brupdate_b2_uop_uses_ldq_0;\t// @[core.scala:51:7]\n wire io_lsu_brupdate_b2_uop_uses_stq_0;\t// @[core.scala:51:7]\n wire io_lsu_brupdate_b2_uop_is_sys_pc2epc_0;\t// @[core.scala:51:7]\n wire io_lsu_brupdate_b2_uop_is_unique_0;\t// @[core.scala:51:7]\n wire io_lsu_brupdate_b2_uop_flush_on_commit_0;\t// @[core.scala:51:7]\n wire io_lsu_brupdate_b2_uop_ldst_is_rs1_0;\t// @[core.scala:51:7]\n wire [5:0] io_lsu_brupdate_b2_uop_ldst_0;\t// @[core.scala:51:7]\n wire [5:0] io_lsu_brupdate_b2_uop_lrs1_0;\t// @[core.scala:51:7]\n wire [5:0] io_lsu_brupdate_b2_uop_lrs2_0;\t// @[core.scala:51:7]\n wire [5:0] io_lsu_brupdate_b2_uop_lrs3_0;\t// @[core.scala:51:7]\n wire io_lsu_brupdate_b2_uop_ldst_val_0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_brupdate_b2_uop_dst_rtype_0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_brupdate_b2_uop_lrs1_rtype_0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_brupdate_b2_uop_lrs2_rtype_0;\t// @[core.scala:51:7]\n wire io_lsu_brupdate_b2_uop_frs3_en_0;\t// @[core.scala:51:7]\n wire io_lsu_brupdate_b2_uop_fp_val_0;\t// @[core.scala:51:7]\n wire io_lsu_brupdate_b2_uop_fp_single_0;\t// @[core.scala:51:7]\n wire io_lsu_brupdate_b2_uop_xcpt_pf_if_0;\t// @[core.scala:51:7]\n wire io_lsu_brupdate_b2_uop_xcpt_ae_if_0;\t// @[core.scala:51:7]\n wire io_lsu_brupdate_b2_uop_xcpt_ma_if_0;\t// @[core.scala:51:7]\n wire io_lsu_brupdate_b2_uop_bp_debug_if_0;\t// @[core.scala:51:7]\n wire io_lsu_brupdate_b2_uop_bp_xcpt_if_0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_brupdate_b2_uop_debug_fsrc_0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_brupdate_b2_uop_debug_tsrc_0;\t// @[core.scala:51:7]\n wire io_lsu_brupdate_b2_valid_0;\t// @[core.scala:51:7]\n wire io_lsu_brupdate_b2_mispredict_0;\t// @[core.scala:51:7]\n wire io_lsu_brupdate_b2_taken_0;\t// @[core.scala:51:7]\n wire [2:0] io_lsu_brupdate_b2_cfi_type_0;\t// @[core.scala:51:7]\n wire [1:0] io_lsu_brupdate_b2_pc_sel_0;\t// @[core.scala:51:7]\n wire [39:0] io_lsu_brupdate_b2_jalr_target_0;\t// @[core.scala:51:7]\n wire [20:0] io_lsu_brupdate_b2_target_offset_0;\t// @[core.scala:51:7]\n wire io_lsu_commit_load_at_rob_head_0;\t// @[core.scala:51:7]\n wire io_lsu_fence_dmem_0;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_rob_pnr_idx_0;\t// @[core.scala:51:7]\n wire [6:0] io_lsu_rob_head_idx_0;\t// @[core.scala:51:7]\n wire io_lsu_exception_0;\t// @[core.scala:51:7]\n wire [63:0] io_lsu_tsc_reg_0;\t// @[core.scala:51:7]\n wire io_trace_custom_rob_empty_0;\t// @[core.scala:51:7]\n wire [63:0] io_trace_time_0;\t// @[core.scala:51:7]\n wire [2:0] io_fcsr_rm;\t// @[core.scala:51:7]\n wire _int_iss_wakeups_0_valid_T_2;\t// @[core.scala:795:52]\n wire fast_wakeup_valid;\t// @[core.scala:814:29]\n wire [6:0] fast_wakeup_bits_uop_uopc;\t// @[core.scala:814:29]\n wire [31:0] fast_wakeup_bits_uop_inst;\t// @[core.scala:814:29]\n wire [31:0] fast_wakeup_bits_uop_debug_inst;\t// @[core.scala:814:29]\n wire fast_wakeup_bits_uop_is_rvc;\t// @[core.scala:814:29]\n wire [39:0] fast_wakeup_bits_uop_debug_pc;\t// @[core.scala:814:29]\n wire [2:0] fast_wakeup_bits_uop_iq_type;\t// @[core.scala:814:29]\n wire [9:0] fast_wakeup_bits_uop_fu_code;\t// @[core.scala:814:29]\n wire [3:0] fast_wakeup_bits_uop_ctrl_br_type;\t// @[core.scala:814:29]\n wire [1:0] fast_wakeup_bits_uop_ctrl_op1_sel;\t// @[core.scala:814:29]\n wire [2:0] fast_wakeup_bits_uop_ctrl_op2_sel;\t// @[core.scala:814:29]\n wire [2:0] fast_wakeup_bits_uop_ctrl_imm_sel;\t// @[core.scala:814:29]\n wire [4:0] fast_wakeup_bits_uop_ctrl_op_fcn;\t// @[core.scala:814:29]\n wire fast_wakeup_bits_uop_ctrl_fcn_dw;\t// @[core.scala:814:29]\n wire [2:0] fast_wakeup_bits_uop_ctrl_csr_cmd;\t// @[core.scala:814:29]\n wire fast_wakeup_bits_uop_ctrl_is_load;\t// @[core.scala:814:29]\n wire fast_wakeup_bits_uop_ctrl_is_sta;\t// @[core.scala:814:29]\n wire fast_wakeup_bits_uop_ctrl_is_std;\t// @[core.scala:814:29]\n wire [1:0] fast_wakeup_bits_uop_iw_state;\t// @[core.scala:814:29]\n wire fast_wakeup_bits_uop_iw_p1_poisoned;\t// @[core.scala:814:29]\n wire fast_wakeup_bits_uop_iw_p2_poisoned;\t// @[core.scala:814:29]\n wire fast_wakeup_bits_uop_is_br;\t// @[core.scala:814:29]\n wire fast_wakeup_bits_uop_is_jalr;\t// @[core.scala:814:29]\n wire fast_wakeup_bits_uop_is_jal;\t// @[core.scala:814:29]\n wire fast_wakeup_bits_uop_is_sfb;\t// @[core.scala:814:29]\n wire [15:0] fast_wakeup_bits_uop_br_mask;\t// @[core.scala:814:29]\n wire [3:0] fast_wakeup_bits_uop_br_tag;\t// @[core.scala:814:29]\n wire [4:0] fast_wakeup_bits_uop_ftq_idx;\t// @[core.scala:814:29]\n wire fast_wakeup_bits_uop_edge_inst;\t// @[core.scala:814:29]\n wire [5:0] fast_wakeup_bits_uop_pc_lob;\t// @[core.scala:814:29]\n wire fast_wakeup_bits_uop_taken;\t// @[core.scala:814:29]\n wire [19:0] fast_wakeup_bits_uop_imm_packed;\t// @[core.scala:814:29]\n wire [11:0] fast_wakeup_bits_uop_csr_addr;\t// @[core.scala:814:29]\n wire [6:0] fast_wakeup_bits_uop_rob_idx;\t// @[core.scala:814:29]\n wire [4:0] fast_wakeup_bits_uop_ldq_idx;\t// @[core.scala:814:29]\n wire [4:0] fast_wakeup_bits_uop_stq_idx;\t// @[core.scala:814:29]\n wire [1:0] fast_wakeup_bits_uop_rxq_idx;\t// @[core.scala:814:29]\n wire [6:0] fast_wakeup_bits_uop_pdst;\t// @[core.scala:814:29]\n wire [6:0] fast_wakeup_bits_uop_prs1;\t// @[core.scala:814:29]\n wire [6:0] fast_wakeup_bits_uop_prs2;\t// @[core.scala:814:29]\n wire [6:0] fast_wakeup_bits_uop_prs3;\t// @[core.scala:814:29]\n wire [4:0] fast_wakeup_bits_uop_ppred;\t// @[core.scala:814:29]\n wire fast_wakeup_bits_uop_prs1_busy;\t// @[core.scala:814:29]\n wire fast_wakeup_bits_uop_prs2_busy;\t// @[core.scala:814:29]\n wire fast_wakeup_bits_uop_prs3_busy;\t// @[core.scala:814:29]\n wire fast_wakeup_bits_uop_ppred_busy;\t// @[core.scala:814:29]\n wire [6:0] fast_wakeup_bits_uop_stale_pdst;\t// @[core.scala:814:29]\n wire fast_wakeup_bits_uop_exception;\t// @[core.scala:814:29]\n wire [63:0] fast_wakeup_bits_uop_exc_cause;\t// @[core.scala:814:29]\n wire fast_wakeup_bits_uop_bypassable;\t// @[core.scala:814:29]\n wire [4:0] fast_wakeup_bits_uop_mem_cmd;\t// @[core.scala:814:29]\n wire [1:0] fast_wakeup_bits_uop_mem_size;\t// @[core.scala:814:29]\n wire fast_wakeup_bits_uop_mem_signed;\t// @[core.scala:814:29]\n wire fast_wakeup_bits_uop_is_fence;\t// @[core.scala:814:29]\n wire fast_wakeup_bits_uop_is_fencei;\t// @[core.scala:814:29]\n wire fast_wakeup_bits_uop_is_amo;\t// @[core.scala:814:29]\n wire fast_wakeup_bits_uop_uses_ldq;\t// @[core.scala:814:29]\n wire fast_wakeup_bits_uop_uses_stq;\t// @[core.scala:814:29]\n wire fast_wakeup_bits_uop_is_sys_pc2epc;\t// @[core.scala:814:29]\n wire fast_wakeup_bits_uop_is_unique;\t// @[core.scala:814:29]\n wire fast_wakeup_bits_uop_flush_on_commit;\t// @[core.scala:814:29]\n wire fast_wakeup_bits_uop_ldst_is_rs1;\t// @[core.scala:814:29]\n wire [5:0] fast_wakeup_bits_uop_ldst;\t// @[core.scala:814:29]\n wire [5:0] fast_wakeup_bits_uop_lrs1;\t// @[core.scala:814:29]\n wire [5:0] fast_wakeup_bits_uop_lrs2;\t// @[core.scala:814:29]\n wire [5:0] fast_wakeup_bits_uop_lrs3;\t// @[core.scala:814:29]\n wire fast_wakeup_bits_uop_ldst_val;\t// @[core.scala:814:29]\n wire [1:0] fast_wakeup_bits_uop_dst_rtype;\t// @[core.scala:814:29]\n wire [1:0] fast_wakeup_bits_uop_lrs1_rtype;\t// @[core.scala:814:29]\n wire [1:0] fast_wakeup_bits_uop_lrs2_rtype;\t// @[core.scala:814:29]\n wire fast_wakeup_bits_uop_frs3_en;\t// @[core.scala:814:29]\n wire fast_wakeup_bits_uop_fp_val;\t// @[core.scala:814:29]\n wire fast_wakeup_bits_uop_fp_single;\t// @[core.scala:814:29]\n wire fast_wakeup_bits_uop_xcpt_pf_if;\t// @[core.scala:814:29]\n wire fast_wakeup_bits_uop_xcpt_ae_if;\t// @[core.scala:814:29]\n wire fast_wakeup_bits_uop_xcpt_ma_if;\t// @[core.scala:814:29]\n wire fast_wakeup_bits_uop_bp_debug_if;\t// @[core.scala:814:29]\n wire fast_wakeup_bits_uop_bp_xcpt_if;\t// @[core.scala:814:29]\n wire [1:0] fast_wakeup_bits_uop_debug_fsrc;\t// @[core.scala:814:29]\n wire [1:0] fast_wakeup_bits_uop_debug_tsrc;\t// @[core.scala:814:29]\n wire slow_wakeup_valid;\t// @[core.scala:815:29]\n wire [6:0] slow_wakeup_bits_uop_uopc;\t// @[core.scala:815:29]\n wire [31:0] slow_wakeup_bits_uop_inst;\t// @[core.scala:815:29]\n wire [31:0] slow_wakeup_bits_uop_debug_inst;\t// @[core.scala:815:29]\n wire slow_wakeup_bits_uop_is_rvc;\t// @[core.scala:815:29]\n wire [39:0] slow_wakeup_bits_uop_debug_pc;\t// @[core.scala:815:29]\n wire [2:0] slow_wakeup_bits_uop_iq_type;\t// @[core.scala:815:29]\n wire [9:0] slow_wakeup_bits_uop_fu_code;\t// @[core.scala:815:29]\n wire [3:0] slow_wakeup_bits_uop_ctrl_br_type;\t// @[core.scala:815:29]\n wire [1:0] slow_wakeup_bits_uop_ctrl_op1_sel;\t// @[core.scala:815:29]\n wire [2:0] slow_wakeup_bits_uop_ctrl_op2_sel;\t// @[core.scala:815:29]\n wire [2:0] slow_wakeup_bits_uop_ctrl_imm_sel;\t// @[core.scala:815:29]\n wire [4:0] slow_wakeup_bits_uop_ctrl_op_fcn;\t// @[core.scala:815:29]\n wire slow_wakeup_bits_uop_ctrl_fcn_dw;\t// @[core.scala:815:29]\n wire [2:0] slow_wakeup_bits_uop_ctrl_csr_cmd;\t// @[core.scala:815:29]\n wire slow_wakeup_bits_uop_ctrl_is_load;\t// @[core.scala:815:29]\n wire slow_wakeup_bits_uop_ctrl_is_sta;\t// @[core.scala:815:29]\n wire slow_wakeup_bits_uop_ctrl_is_std;\t// @[core.scala:815:29]\n wire [1:0] slow_wakeup_bits_uop_iw_state;\t// @[core.scala:815:29]\n wire slow_wakeup_bits_uop_iw_p1_poisoned;\t// @[core.scala:815:29]\n wire slow_wakeup_bits_uop_iw_p2_poisoned;\t// @[core.scala:815:29]\n wire slow_wakeup_bits_uop_is_br;\t// @[core.scala:815:29]\n wire slow_wakeup_bits_uop_is_jalr;\t// @[core.scala:815:29]\n wire slow_wakeup_bits_uop_is_jal;\t// @[core.scala:815:29]\n wire slow_wakeup_bits_uop_is_sfb;\t// @[core.scala:815:29]\n wire [15:0] slow_wakeup_bits_uop_br_mask;\t// @[core.scala:815:29]\n wire [3:0] slow_wakeup_bits_uop_br_tag;\t// @[core.scala:815:29]\n wire [4:0] slow_wakeup_bits_uop_ftq_idx;\t// @[core.scala:815:29]\n wire slow_wakeup_bits_uop_edge_inst;\t// @[core.scala:815:29]\n wire [5:0] slow_wakeup_bits_uop_pc_lob;\t// @[core.scala:815:29]\n wire slow_wakeup_bits_uop_taken;\t// @[core.scala:815:29]\n wire [19:0] slow_wakeup_bits_uop_imm_packed;\t// @[core.scala:815:29]\n wire [11:0] slow_wakeup_bits_uop_csr_addr;\t// @[core.scala:815:29]\n wire [6:0] slow_wakeup_bits_uop_rob_idx;\t// @[core.scala:815:29]\n wire [4:0] slow_wakeup_bits_uop_ldq_idx;\t// @[core.scala:815:29]\n wire [4:0] slow_wakeup_bits_uop_stq_idx;\t// @[core.scala:815:29]\n wire [1:0] slow_wakeup_bits_uop_rxq_idx;\t// @[core.scala:815:29]\n wire [6:0] slow_wakeup_bits_uop_pdst;\t// @[core.scala:815:29]\n wire [6:0] slow_wakeup_bits_uop_prs1;\t// @[core.scala:815:29]\n wire [6:0] slow_wakeup_bits_uop_prs2;\t// @[core.scala:815:29]\n wire [6:0] slow_wakeup_bits_uop_prs3;\t// @[core.scala:815:29]\n wire [4:0] slow_wakeup_bits_uop_ppred;\t// @[core.scala:815:29]\n wire slow_wakeup_bits_uop_prs1_busy;\t// @[core.scala:815:29]\n wire slow_wakeup_bits_uop_prs2_busy;\t// @[core.scala:815:29]\n wire slow_wakeup_bits_uop_prs3_busy;\t// @[core.scala:815:29]\n wire slow_wakeup_bits_uop_ppred_busy;\t// @[core.scala:815:29]\n wire [6:0] slow_wakeup_bits_uop_stale_pdst;\t// @[core.scala:815:29]\n wire slow_wakeup_bits_uop_exception;\t// @[core.scala:815:29]\n wire [63:0] slow_wakeup_bits_uop_exc_cause;\t// @[core.scala:815:29]\n wire slow_wakeup_bits_uop_bypassable;\t// @[core.scala:815:29]\n wire [4:0] slow_wakeup_bits_uop_mem_cmd;\t// @[core.scala:815:29]\n wire [1:0] slow_wakeup_bits_uop_mem_size;\t// @[core.scala:815:29]\n wire slow_wakeup_bits_uop_mem_signed;\t// @[core.scala:815:29]\n wire slow_wakeup_bits_uop_is_fence;\t// @[core.scala:815:29]\n wire slow_wakeup_bits_uop_is_fencei;\t// @[core.scala:815:29]\n wire slow_wakeup_bits_uop_is_amo;\t// @[core.scala:815:29]\n wire slow_wakeup_bits_uop_uses_ldq;\t// @[core.scala:815:29]\n wire slow_wakeup_bits_uop_uses_stq;\t// @[core.scala:815:29]\n wire slow_wakeup_bits_uop_is_sys_pc2epc;\t// @[core.scala:815:29]\n wire slow_wakeup_bits_uop_is_unique;\t// @[core.scala:815:29]\n wire slow_wakeup_bits_uop_flush_on_commit;\t// @[core.scala:815:29]\n wire slow_wakeup_bits_uop_ldst_is_rs1;\t// @[core.scala:815:29]\n wire [5:0] slow_wakeup_bits_uop_ldst;\t// @[core.scala:815:29]\n wire [5:0] slow_wakeup_bits_uop_lrs1;\t// @[core.scala:815:29]\n wire [5:0] slow_wakeup_bits_uop_lrs2;\t// @[core.scala:815:29]\n wire [5:0] slow_wakeup_bits_uop_lrs3;\t// @[core.scala:815:29]\n wire slow_wakeup_bits_uop_ldst_val;\t// @[core.scala:815:29]\n wire [1:0] slow_wakeup_bits_uop_dst_rtype;\t// @[core.scala:815:29]\n wire [1:0] slow_wakeup_bits_uop_lrs1_rtype;\t// @[core.scala:815:29]\n wire [1:0] slow_wakeup_bits_uop_lrs2_rtype;\t// @[core.scala:815:29]\n wire slow_wakeup_bits_uop_frs3_en;\t// @[core.scala:815:29]\n wire slow_wakeup_bits_uop_fp_val;\t// @[core.scala:815:29]\n wire slow_wakeup_bits_uop_fp_single;\t// @[core.scala:815:29]\n wire slow_wakeup_bits_uop_xcpt_pf_if;\t// @[core.scala:815:29]\n wire slow_wakeup_bits_uop_xcpt_ae_if;\t// @[core.scala:815:29]\n wire slow_wakeup_bits_uop_xcpt_ma_if;\t// @[core.scala:815:29]\n wire slow_wakeup_bits_uop_bp_debug_if;\t// @[core.scala:815:29]\n wire slow_wakeup_bits_uop_bp_xcpt_if;\t// @[core.scala:815:29]\n wire [1:0] slow_wakeup_bits_uop_debug_fsrc;\t// @[core.scala:815:29]\n wire [1:0] slow_wakeup_bits_uop_debug_tsrc;\t// @[core.scala:815:29]\n wire fast_wakeup_1_valid;\t// @[core.scala:814:29]\n wire [6:0] fast_wakeup_1_bits_uop_uopc;\t// @[core.scala:814:29]\n wire [31:0] fast_wakeup_1_bits_uop_inst;\t// @[core.scala:814:29]\n wire [31:0] fast_wakeup_1_bits_uop_debug_inst;\t// @[core.scala:814:29]\n wire fast_wakeup_1_bits_uop_is_rvc;\t// @[core.scala:814:29]\n wire [39:0] fast_wakeup_1_bits_uop_debug_pc;\t// @[core.scala:814:29]\n wire [2:0] fast_wakeup_1_bits_uop_iq_type;\t// @[core.scala:814:29]\n wire [9:0] fast_wakeup_1_bits_uop_fu_code;\t// @[core.scala:814:29]\n wire [3:0] fast_wakeup_1_bits_uop_ctrl_br_type;\t// @[core.scala:814:29]\n wire [1:0] fast_wakeup_1_bits_uop_ctrl_op1_sel;\t// @[core.scala:814:29]\n wire [2:0] fast_wakeup_1_bits_uop_ctrl_op2_sel;\t// @[core.scala:814:29]\n wire [2:0] fast_wakeup_1_bits_uop_ctrl_imm_sel;\t// @[core.scala:814:29]\n wire [4:0] fast_wakeup_1_bits_uop_ctrl_op_fcn;\t// @[core.scala:814:29]\n wire fast_wakeup_1_bits_uop_ctrl_fcn_dw;\t// @[core.scala:814:29]\n wire [2:0] fast_wakeup_1_bits_uop_ctrl_csr_cmd;\t// @[core.scala:814:29]\n wire fast_wakeup_1_bits_uop_ctrl_is_load;\t// @[core.scala:814:29]\n wire fast_wakeup_1_bits_uop_ctrl_is_sta;\t// @[core.scala:814:29]\n wire fast_wakeup_1_bits_uop_ctrl_is_std;\t// @[core.scala:814:29]\n wire [1:0] fast_wakeup_1_bits_uop_iw_state;\t// @[core.scala:814:29]\n wire fast_wakeup_1_bits_uop_iw_p1_poisoned;\t// @[core.scala:814:29]\n wire fast_wakeup_1_bits_uop_iw_p2_poisoned;\t// @[core.scala:814:29]\n wire fast_wakeup_1_bits_uop_is_br;\t// @[core.scala:814:29]\n wire fast_wakeup_1_bits_uop_is_jalr;\t// @[core.scala:814:29]\n wire fast_wakeup_1_bits_uop_is_jal;\t// @[core.scala:814:29]\n wire fast_wakeup_1_bits_uop_is_sfb;\t// @[core.scala:814:29]\n wire [15:0] fast_wakeup_1_bits_uop_br_mask;\t// @[core.scala:814:29]\n wire [3:0] fast_wakeup_1_bits_uop_br_tag;\t// @[core.scala:814:29]\n wire [4:0] fast_wakeup_1_bits_uop_ftq_idx;\t// @[core.scala:814:29]\n wire fast_wakeup_1_bits_uop_edge_inst;\t// @[core.scala:814:29]\n wire [5:0] fast_wakeup_1_bits_uop_pc_lob;\t// @[core.scala:814:29]\n wire fast_wakeup_1_bits_uop_taken;\t// @[core.scala:814:29]\n wire [19:0] fast_wakeup_1_bits_uop_imm_packed;\t// @[core.scala:814:29]\n wire [11:0] fast_wakeup_1_bits_uop_csr_addr;\t// @[core.scala:814:29]\n wire [6:0] fast_wakeup_1_bits_uop_rob_idx;\t// @[core.scala:814:29]\n wire [4:0] fast_wakeup_1_bits_uop_ldq_idx;\t// @[core.scala:814:29]\n wire [4:0] fast_wakeup_1_bits_uop_stq_idx;\t// @[core.scala:814:29]\n wire [1:0] fast_wakeup_1_bits_uop_rxq_idx;\t// @[core.scala:814:29]\n wire [6:0] fast_wakeup_1_bits_uop_pdst;\t// @[core.scala:814:29]\n wire [6:0] fast_wakeup_1_bits_uop_prs1;\t// @[core.scala:814:29]\n wire [6:0] fast_wakeup_1_bits_uop_prs2;\t// @[core.scala:814:29]\n wire [6:0] fast_wakeup_1_bits_uop_prs3;\t// @[core.scala:814:29]\n wire [4:0] fast_wakeup_1_bits_uop_ppred;\t// @[core.scala:814:29]\n wire fast_wakeup_1_bits_uop_prs1_busy;\t// @[core.scala:814:29]\n wire fast_wakeup_1_bits_uop_prs2_busy;\t// @[core.scala:814:29]\n wire fast_wakeup_1_bits_uop_prs3_busy;\t// @[core.scala:814:29]\n wire fast_wakeup_1_bits_uop_ppred_busy;\t// @[core.scala:814:29]\n wire [6:0] fast_wakeup_1_bits_uop_stale_pdst;\t// @[core.scala:814:29]\n wire fast_wakeup_1_bits_uop_exception;\t// @[core.scala:814:29]\n wire [63:0] fast_wakeup_1_bits_uop_exc_cause;\t// @[core.scala:814:29]\n wire fast_wakeup_1_bits_uop_bypassable;\t// @[core.scala:814:29]\n wire [4:0] fast_wakeup_1_bits_uop_mem_cmd;\t// @[core.scala:814:29]\n wire [1:0] fast_wakeup_1_bits_uop_mem_size;\t// @[core.scala:814:29]\n wire fast_wakeup_1_bits_uop_mem_signed;\t// @[core.scala:814:29]\n wire fast_wakeup_1_bits_uop_is_fence;\t// @[core.scala:814:29]\n wire fast_wakeup_1_bits_uop_is_fencei;\t// @[core.scala:814:29]\n wire fast_wakeup_1_bits_uop_is_amo;\t// @[core.scala:814:29]\n wire fast_wakeup_1_bits_uop_uses_ldq;\t// @[core.scala:814:29]\n wire fast_wakeup_1_bits_uop_uses_stq;\t// @[core.scala:814:29]\n wire fast_wakeup_1_bits_uop_is_sys_pc2epc;\t// @[core.scala:814:29]\n wire fast_wakeup_1_bits_uop_is_unique;\t// @[core.scala:814:29]\n wire fast_wakeup_1_bits_uop_flush_on_commit;\t// @[core.scala:814:29]\n wire fast_wakeup_1_bits_uop_ldst_is_rs1;\t// @[core.scala:814:29]\n wire [5:0] fast_wakeup_1_bits_uop_ldst;\t// @[core.scala:814:29]\n wire [5:0] fast_wakeup_1_bits_uop_lrs1;\t// @[core.scala:814:29]\n wire [5:0] fast_wakeup_1_bits_uop_lrs2;\t// @[core.scala:814:29]\n wire [5:0] fast_wakeup_1_bits_uop_lrs3;\t// @[core.scala:814:29]\n wire fast_wakeup_1_bits_uop_ldst_val;\t// @[core.scala:814:29]\n wire [1:0] fast_wakeup_1_bits_uop_dst_rtype;\t// @[core.scala:814:29]\n wire [1:0] fast_wakeup_1_bits_uop_lrs1_rtype;\t// @[core.scala:814:29]\n wire [1:0] fast_wakeup_1_bits_uop_lrs2_rtype;\t// @[core.scala:814:29]\n wire fast_wakeup_1_bits_uop_frs3_en;\t// @[core.scala:814:29]\n wire fast_wakeup_1_bits_uop_fp_val;\t// @[core.scala:814:29]\n wire fast_wakeup_1_bits_uop_fp_single;\t// @[core.scala:814:29]\n wire fast_wakeup_1_bits_uop_xcpt_pf_if;\t// @[core.scala:814:29]\n wire fast_wakeup_1_bits_uop_xcpt_ae_if;\t// @[core.scala:814:29]\n wire fast_wakeup_1_bits_uop_xcpt_ma_if;\t// @[core.scala:814:29]\n wire fast_wakeup_1_bits_uop_bp_debug_if;\t// @[core.scala:814:29]\n wire fast_wakeup_1_bits_uop_bp_xcpt_if;\t// @[core.scala:814:29]\n wire [1:0] fast_wakeup_1_bits_uop_debug_fsrc;\t// @[core.scala:814:29]\n wire [1:0] fast_wakeup_1_bits_uop_debug_tsrc;\t// @[core.scala:814:29]\n wire slow_wakeup_1_valid;\t// @[core.scala:815:29]\n wire [6:0] slow_wakeup_1_bits_uop_uopc;\t// @[core.scala:815:29]\n wire [31:0] slow_wakeup_1_bits_uop_inst;\t// @[core.scala:815:29]\n wire [31:0] slow_wakeup_1_bits_uop_debug_inst;\t// @[core.scala:815:29]\n wire slow_wakeup_1_bits_uop_is_rvc;\t// @[core.scala:815:29]\n wire [39:0] slow_wakeup_1_bits_uop_debug_pc;\t// @[core.scala:815:29]\n wire [2:0] slow_wakeup_1_bits_uop_iq_type;\t// @[core.scala:815:29]\n wire [9:0] slow_wakeup_1_bits_uop_fu_code;\t// @[core.scala:815:29]\n wire [3:0] slow_wakeup_1_bits_uop_ctrl_br_type;\t// @[core.scala:815:29]\n wire [1:0] slow_wakeup_1_bits_uop_ctrl_op1_sel;\t// @[core.scala:815:29]\n wire [2:0] slow_wakeup_1_bits_uop_ctrl_op2_sel;\t// @[core.scala:815:29]\n wire [2:0] slow_wakeup_1_bits_uop_ctrl_imm_sel;\t// @[core.scala:815:29]\n wire [4:0] slow_wakeup_1_bits_uop_ctrl_op_fcn;\t// @[core.scala:815:29]\n wire slow_wakeup_1_bits_uop_ctrl_fcn_dw;\t// @[core.scala:815:29]\n wire [2:0] slow_wakeup_1_bits_uop_ctrl_csr_cmd;\t// @[core.scala:815:29]\n wire slow_wakeup_1_bits_uop_ctrl_is_load;\t// @[core.scala:815:29]\n wire slow_wakeup_1_bits_uop_ctrl_is_sta;\t// @[core.scala:815:29]\n wire slow_wakeup_1_bits_uop_ctrl_is_std;\t// @[core.scala:815:29]\n wire [1:0] slow_wakeup_1_bits_uop_iw_state;\t// @[core.scala:815:29]\n wire slow_wakeup_1_bits_uop_iw_p1_poisoned;\t// @[core.scala:815:29]\n wire slow_wakeup_1_bits_uop_iw_p2_poisoned;\t// @[core.scala:815:29]\n wire slow_wakeup_1_bits_uop_is_br;\t// @[core.scala:815:29]\n wire slow_wakeup_1_bits_uop_is_jalr;\t// @[core.scala:815:29]\n wire slow_wakeup_1_bits_uop_is_jal;\t// @[core.scala:815:29]\n wire slow_wakeup_1_bits_uop_is_sfb;\t// @[core.scala:815:29]\n wire [15:0] slow_wakeup_1_bits_uop_br_mask;\t// @[core.scala:815:29]\n wire [3:0] slow_wakeup_1_bits_uop_br_tag;\t// @[core.scala:815:29]\n wire [4:0] slow_wakeup_1_bits_uop_ftq_idx;\t// @[core.scala:815:29]\n wire slow_wakeup_1_bits_uop_edge_inst;\t// @[core.scala:815:29]\n wire [5:0] slow_wakeup_1_bits_uop_pc_lob;\t// @[core.scala:815:29]\n wire slow_wakeup_1_bits_uop_taken;\t// @[core.scala:815:29]\n wire [19:0] slow_wakeup_1_bits_uop_imm_packed;\t// @[core.scala:815:29]\n wire [11:0] slow_wakeup_1_bits_uop_csr_addr;\t// @[core.scala:815:29]\n wire [6:0] slow_wakeup_1_bits_uop_rob_idx;\t// @[core.scala:815:29]\n wire [4:0] slow_wakeup_1_bits_uop_ldq_idx;\t// @[core.scala:815:29]\n wire [4:0] slow_wakeup_1_bits_uop_stq_idx;\t// @[core.scala:815:29]\n wire [1:0] slow_wakeup_1_bits_uop_rxq_idx;\t// @[core.scala:815:29]\n wire [6:0] slow_wakeup_1_bits_uop_pdst;\t// @[core.scala:815:29]\n wire [6:0] slow_wakeup_1_bits_uop_prs1;\t// @[core.scala:815:29]\n wire [6:0] slow_wakeup_1_bits_uop_prs2;\t// @[core.scala:815:29]\n wire [6:0] slow_wakeup_1_bits_uop_prs3;\t// @[core.scala:815:29]\n wire [4:0] slow_wakeup_1_bits_uop_ppred;\t// @[core.scala:815:29]\n wire slow_wakeup_1_bits_uop_prs1_busy;\t// @[core.scala:815:29]\n wire slow_wakeup_1_bits_uop_prs2_busy;\t// @[core.scala:815:29]\n wire slow_wakeup_1_bits_uop_prs3_busy;\t// @[core.scala:815:29]\n wire slow_wakeup_1_bits_uop_ppred_busy;\t// @[core.scala:815:29]\n wire [6:0] slow_wakeup_1_bits_uop_stale_pdst;\t// @[core.scala:815:29]\n wire slow_wakeup_1_bits_uop_exception;\t// @[core.scala:815:29]\n wire [63:0] slow_wakeup_1_bits_uop_exc_cause;\t// @[core.scala:815:29]\n wire slow_wakeup_1_bits_uop_bypassable;\t// @[core.scala:815:29]\n wire [4:0] slow_wakeup_1_bits_uop_mem_cmd;\t// @[core.scala:815:29]\n wire [1:0] slow_wakeup_1_bits_uop_mem_size;\t// @[core.scala:815:29]\n wire slow_wakeup_1_bits_uop_mem_signed;\t// @[core.scala:815:29]\n wire slow_wakeup_1_bits_uop_is_fence;\t// @[core.scala:815:29]\n wire slow_wakeup_1_bits_uop_is_fencei;\t// @[core.scala:815:29]\n wire slow_wakeup_1_bits_uop_is_amo;\t// @[core.scala:815:29]\n wire slow_wakeup_1_bits_uop_uses_ldq;\t// @[core.scala:815:29]\n wire slow_wakeup_1_bits_uop_uses_stq;\t// @[core.scala:815:29]\n wire slow_wakeup_1_bits_uop_is_sys_pc2epc;\t// @[core.scala:815:29]\n wire slow_wakeup_1_bits_uop_is_unique;\t// @[core.scala:815:29]\n wire slow_wakeup_1_bits_uop_flush_on_commit;\t// @[core.scala:815:29]\n wire slow_wakeup_1_bits_uop_ldst_is_rs1;\t// @[core.scala:815:29]\n wire [5:0] slow_wakeup_1_bits_uop_ldst;\t// @[core.scala:815:29]\n wire [5:0] slow_wakeup_1_bits_uop_lrs1;\t// @[core.scala:815:29]\n wire [5:0] slow_wakeup_1_bits_uop_lrs2;\t// @[core.scala:815:29]\n wire [5:0] slow_wakeup_1_bits_uop_lrs3;\t// @[core.scala:815:29]\n wire slow_wakeup_1_bits_uop_ldst_val;\t// @[core.scala:815:29]\n wire [1:0] slow_wakeup_1_bits_uop_dst_rtype;\t// @[core.scala:815:29]\n wire [1:0] slow_wakeup_1_bits_uop_lrs1_rtype;\t// @[core.scala:815:29]\n wire [1:0] slow_wakeup_1_bits_uop_lrs2_rtype;\t// @[core.scala:815:29]\n wire slow_wakeup_1_bits_uop_frs3_en;\t// @[core.scala:815:29]\n wire slow_wakeup_1_bits_uop_fp_val;\t// @[core.scala:815:29]\n wire slow_wakeup_1_bits_uop_fp_single;\t// @[core.scala:815:29]\n wire slow_wakeup_1_bits_uop_xcpt_pf_if;\t// @[core.scala:815:29]\n wire slow_wakeup_1_bits_uop_xcpt_ae_if;\t// @[core.scala:815:29]\n wire slow_wakeup_1_bits_uop_xcpt_ma_if;\t// @[core.scala:815:29]\n wire slow_wakeup_1_bits_uop_bp_debug_if;\t// @[core.scala:815:29]\n wire slow_wakeup_1_bits_uop_bp_xcpt_if;\t// @[core.scala:815:29]\n wire [1:0] slow_wakeup_1_bits_uop_debug_fsrc;\t// @[core.scala:815:29]\n wire [1:0] slow_wakeup_1_bits_uop_debug_tsrc;\t// @[core.scala:815:29]\n wire fast_wakeup_2_valid;\t// @[core.scala:814:29]\n wire [6:0] fast_wakeup_2_bits_uop_uopc;\t// @[core.scala:814:29]\n wire [31:0] fast_wakeup_2_bits_uop_inst;\t// @[core.scala:814:29]\n wire [31:0] fast_wakeup_2_bits_uop_debug_inst;\t// @[core.scala:814:29]\n wire fast_wakeup_2_bits_uop_is_rvc;\t// @[core.scala:814:29]\n wire [39:0] fast_wakeup_2_bits_uop_debug_pc;\t// @[core.scala:814:29]\n wire [2:0] fast_wakeup_2_bits_uop_iq_type;\t// @[core.scala:814:29]\n wire [9:0] fast_wakeup_2_bits_uop_fu_code;\t// @[core.scala:814:29]\n wire [3:0] fast_wakeup_2_bits_uop_ctrl_br_type;\t// @[core.scala:814:29]\n wire [1:0] fast_wakeup_2_bits_uop_ctrl_op1_sel;\t// @[core.scala:814:29]\n wire [2:0] fast_wakeup_2_bits_uop_ctrl_op2_sel;\t// @[core.scala:814:29]\n wire [2:0] fast_wakeup_2_bits_uop_ctrl_imm_sel;\t// @[core.scala:814:29]\n wire [4:0] fast_wakeup_2_bits_uop_ctrl_op_fcn;\t// @[core.scala:814:29]\n wire fast_wakeup_2_bits_uop_ctrl_fcn_dw;\t// @[core.scala:814:29]\n wire [2:0] fast_wakeup_2_bits_uop_ctrl_csr_cmd;\t// @[core.scala:814:29]\n wire fast_wakeup_2_bits_uop_ctrl_is_load;\t// @[core.scala:814:29]\n wire fast_wakeup_2_bits_uop_ctrl_is_sta;\t// @[core.scala:814:29]\n wire fast_wakeup_2_bits_uop_ctrl_is_std;\t// @[core.scala:814:29]\n wire [1:0] fast_wakeup_2_bits_uop_iw_state;\t// @[core.scala:814:29]\n wire fast_wakeup_2_bits_uop_iw_p1_poisoned;\t// @[core.scala:814:29]\n wire fast_wakeup_2_bits_uop_iw_p2_poisoned;\t// @[core.scala:814:29]\n wire fast_wakeup_2_bits_uop_is_br;\t// @[core.scala:814:29]\n wire fast_wakeup_2_bits_uop_is_jalr;\t// @[core.scala:814:29]\n wire fast_wakeup_2_bits_uop_is_jal;\t// @[core.scala:814:29]\n wire fast_wakeup_2_bits_uop_is_sfb;\t// @[core.scala:814:29]\n wire [15:0] fast_wakeup_2_bits_uop_br_mask;\t// @[core.scala:814:29]\n wire [3:0] fast_wakeup_2_bits_uop_br_tag;\t// @[core.scala:814:29]\n wire [4:0] fast_wakeup_2_bits_uop_ftq_idx;\t// @[core.scala:814:29]\n wire fast_wakeup_2_bits_uop_edge_inst;\t// @[core.scala:814:29]\n wire [5:0] fast_wakeup_2_bits_uop_pc_lob;\t// @[core.scala:814:29]\n wire fast_wakeup_2_bits_uop_taken;\t// @[core.scala:814:29]\n wire [19:0] fast_wakeup_2_bits_uop_imm_packed;\t// @[core.scala:814:29]\n wire [11:0] fast_wakeup_2_bits_uop_csr_addr;\t// @[core.scala:814:29]\n wire [6:0] fast_wakeup_2_bits_uop_rob_idx;\t// @[core.scala:814:29]\n wire [4:0] fast_wakeup_2_bits_uop_ldq_idx;\t// @[core.scala:814:29]\n wire [4:0] fast_wakeup_2_bits_uop_stq_idx;\t// @[core.scala:814:29]\n wire [1:0] fast_wakeup_2_bits_uop_rxq_idx;\t// @[core.scala:814:29]\n wire [6:0] fast_wakeup_2_bits_uop_pdst;\t// @[core.scala:814:29]\n wire [6:0] fast_wakeup_2_bits_uop_prs1;\t// @[core.scala:814:29]\n wire [6:0] fast_wakeup_2_bits_uop_prs2;\t// @[core.scala:814:29]\n wire [6:0] fast_wakeup_2_bits_uop_prs3;\t// @[core.scala:814:29]\n wire [4:0] fast_wakeup_2_bits_uop_ppred;\t// @[core.scala:814:29]\n wire fast_wakeup_2_bits_uop_prs1_busy;\t// @[core.scala:814:29]\n wire fast_wakeup_2_bits_uop_prs2_busy;\t// @[core.scala:814:29]\n wire fast_wakeup_2_bits_uop_prs3_busy;\t// @[core.scala:814:29]\n wire fast_wakeup_2_bits_uop_ppred_busy;\t// @[core.scala:814:29]\n wire [6:0] fast_wakeup_2_bits_uop_stale_pdst;\t// @[core.scala:814:29]\n wire fast_wakeup_2_bits_uop_exception;\t// @[core.scala:814:29]\n wire [63:0] fast_wakeup_2_bits_uop_exc_cause;\t// @[core.scala:814:29]\n wire fast_wakeup_2_bits_uop_bypassable;\t// @[core.scala:814:29]\n wire [4:0] fast_wakeup_2_bits_uop_mem_cmd;\t// @[core.scala:814:29]\n wire [1:0] fast_wakeup_2_bits_uop_mem_size;\t// @[core.scala:814:29]\n wire fast_wakeup_2_bits_uop_mem_signed;\t// @[core.scala:814:29]\n wire fast_wakeup_2_bits_uop_is_fence;\t// @[core.scala:814:29]\n wire fast_wakeup_2_bits_uop_is_fencei;\t// @[core.scala:814:29]\n wire fast_wakeup_2_bits_uop_is_amo;\t// @[core.scala:814:29]\n wire fast_wakeup_2_bits_uop_uses_ldq;\t// @[core.scala:814:29]\n wire fast_wakeup_2_bits_uop_uses_stq;\t// @[core.scala:814:29]\n wire fast_wakeup_2_bits_uop_is_sys_pc2epc;\t// @[core.scala:814:29]\n wire fast_wakeup_2_bits_uop_is_unique;\t// @[core.scala:814:29]\n wire fast_wakeup_2_bits_uop_flush_on_commit;\t// @[core.scala:814:29]\n wire fast_wakeup_2_bits_uop_ldst_is_rs1;\t// @[core.scala:814:29]\n wire [5:0] fast_wakeup_2_bits_uop_ldst;\t// @[core.scala:814:29]\n wire [5:0] fast_wakeup_2_bits_uop_lrs1;\t// @[core.scala:814:29]\n wire [5:0] fast_wakeup_2_bits_uop_lrs2;\t// @[core.scala:814:29]\n wire [5:0] fast_wakeup_2_bits_uop_lrs3;\t// @[core.scala:814:29]\n wire fast_wakeup_2_bits_uop_ldst_val;\t// @[core.scala:814:29]\n wire [1:0] fast_wakeup_2_bits_uop_dst_rtype;\t// @[core.scala:814:29]\n wire [1:0] fast_wakeup_2_bits_uop_lrs1_rtype;\t// @[core.scala:814:29]\n wire [1:0] fast_wakeup_2_bits_uop_lrs2_rtype;\t// @[core.scala:814:29]\n wire fast_wakeup_2_bits_uop_frs3_en;\t// @[core.scala:814:29]\n wire fast_wakeup_2_bits_uop_fp_val;\t// @[core.scala:814:29]\n wire fast_wakeup_2_bits_uop_fp_single;\t// @[core.scala:814:29]\n wire fast_wakeup_2_bits_uop_xcpt_pf_if;\t// @[core.scala:814:29]\n wire fast_wakeup_2_bits_uop_xcpt_ae_if;\t// @[core.scala:814:29]\n wire fast_wakeup_2_bits_uop_xcpt_ma_if;\t// @[core.scala:814:29]\n wire fast_wakeup_2_bits_uop_bp_debug_if;\t// @[core.scala:814:29]\n wire fast_wakeup_2_bits_uop_bp_xcpt_if;\t// @[core.scala:814:29]\n wire [1:0] fast_wakeup_2_bits_uop_debug_fsrc;\t// @[core.scala:814:29]\n wire [1:0] fast_wakeup_2_bits_uop_debug_tsrc;\t// @[core.scala:814:29]\n wire slow_wakeup_2_valid;\t// @[core.scala:815:29]\n wire [6:0] slow_wakeup_2_bits_uop_uopc;\t// @[core.scala:815:29]\n wire [31:0] slow_wakeup_2_bits_uop_inst;\t// @[core.scala:815:29]\n wire [31:0] slow_wakeup_2_bits_uop_debug_inst;\t// @[core.scala:815:29]\n wire slow_wakeup_2_bits_uop_is_rvc;\t// @[core.scala:815:29]\n wire [39:0] slow_wakeup_2_bits_uop_debug_pc;\t// @[core.scala:815:29]\n wire [2:0] slow_wakeup_2_bits_uop_iq_type;\t// @[core.scala:815:29]\n wire [9:0] slow_wakeup_2_bits_uop_fu_code;\t// @[core.scala:815:29]\n wire [3:0] slow_wakeup_2_bits_uop_ctrl_br_type;\t// @[core.scala:815:29]\n wire [1:0] slow_wakeup_2_bits_uop_ctrl_op1_sel;\t// @[core.scala:815:29]\n wire [2:0] slow_wakeup_2_bits_uop_ctrl_op2_sel;\t// @[core.scala:815:29]\n wire [2:0] slow_wakeup_2_bits_uop_ctrl_imm_sel;\t// @[core.scala:815:29]\n wire [4:0] slow_wakeup_2_bits_uop_ctrl_op_fcn;\t// @[core.scala:815:29]\n wire slow_wakeup_2_bits_uop_ctrl_fcn_dw;\t// @[core.scala:815:29]\n wire [2:0] slow_wakeup_2_bits_uop_ctrl_csr_cmd;\t// @[core.scala:815:29]\n wire slow_wakeup_2_bits_uop_ctrl_is_load;\t// @[core.scala:815:29]\n wire slow_wakeup_2_bits_uop_ctrl_is_sta;\t// @[core.scala:815:29]\n wire slow_wakeup_2_bits_uop_ctrl_is_std;\t// @[core.scala:815:29]\n wire [1:0] slow_wakeup_2_bits_uop_iw_state;\t// @[core.scala:815:29]\n wire slow_wakeup_2_bits_uop_iw_p1_poisoned;\t// @[core.scala:815:29]\n wire slow_wakeup_2_bits_uop_iw_p2_poisoned;\t// @[core.scala:815:29]\n wire slow_wakeup_2_bits_uop_is_br;\t// @[core.scala:815:29]\n wire slow_wakeup_2_bits_uop_is_jalr;\t// @[core.scala:815:29]\n wire slow_wakeup_2_bits_uop_is_jal;\t// @[core.scala:815:29]\n wire slow_wakeup_2_bits_uop_is_sfb;\t// @[core.scala:815:29]\n wire [15:0] slow_wakeup_2_bits_uop_br_mask;\t// @[core.scala:815:29]\n wire [3:0] slow_wakeup_2_bits_uop_br_tag;\t// @[core.scala:815:29]\n wire [4:0] slow_wakeup_2_bits_uop_ftq_idx;\t// @[core.scala:815:29]\n wire slow_wakeup_2_bits_uop_edge_inst;\t// @[core.scala:815:29]\n wire [5:0] slow_wakeup_2_bits_uop_pc_lob;\t// @[core.scala:815:29]\n wire slow_wakeup_2_bits_uop_taken;\t// @[core.scala:815:29]\n wire [19:0] slow_wakeup_2_bits_uop_imm_packed;\t// @[core.scala:815:29]\n wire [11:0] slow_wakeup_2_bits_uop_csr_addr;\t// @[core.scala:815:29]\n wire [6:0] slow_wakeup_2_bits_uop_rob_idx;\t// @[core.scala:815:29]\n wire [4:0] slow_wakeup_2_bits_uop_ldq_idx;\t// @[core.scala:815:29]\n wire [4:0] slow_wakeup_2_bits_uop_stq_idx;\t// @[core.scala:815:29]\n wire [1:0] slow_wakeup_2_bits_uop_rxq_idx;\t// @[core.scala:815:29]\n wire [6:0] slow_wakeup_2_bits_uop_pdst;\t// @[core.scala:815:29]\n wire [6:0] slow_wakeup_2_bits_uop_prs1;\t// @[core.scala:815:29]\n wire [6:0] slow_wakeup_2_bits_uop_prs2;\t// @[core.scala:815:29]\n wire [6:0] slow_wakeup_2_bits_uop_prs3;\t// @[core.scala:815:29]\n wire [4:0] slow_wakeup_2_bits_uop_ppred;\t// @[core.scala:815:29]\n wire slow_wakeup_2_bits_uop_prs1_busy;\t// @[core.scala:815:29]\n wire slow_wakeup_2_bits_uop_prs2_busy;\t// @[core.scala:815:29]\n wire slow_wakeup_2_bits_uop_prs3_busy;\t// @[core.scala:815:29]\n wire slow_wakeup_2_bits_uop_ppred_busy;\t// @[core.scala:815:29]\n wire [6:0] slow_wakeup_2_bits_uop_stale_pdst;\t// @[core.scala:815:29]\n wire slow_wakeup_2_bits_uop_exception;\t// @[core.scala:815:29]\n wire [63:0] slow_wakeup_2_bits_uop_exc_cause;\t// @[core.scala:815:29]\n wire slow_wakeup_2_bits_uop_bypassable;\t// @[core.scala:815:29]\n wire [4:0] slow_wakeup_2_bits_uop_mem_cmd;\t// @[core.scala:815:29]\n wire [1:0] slow_wakeup_2_bits_uop_mem_size;\t// @[core.scala:815:29]\n wire slow_wakeup_2_bits_uop_mem_signed;\t// @[core.scala:815:29]\n wire slow_wakeup_2_bits_uop_is_fence;\t// @[core.scala:815:29]\n wire slow_wakeup_2_bits_uop_is_fencei;\t// @[core.scala:815:29]\n wire slow_wakeup_2_bits_uop_is_amo;\t// @[core.scala:815:29]\n wire slow_wakeup_2_bits_uop_uses_ldq;\t// @[core.scala:815:29]\n wire slow_wakeup_2_bits_uop_uses_stq;\t// @[core.scala:815:29]\n wire slow_wakeup_2_bits_uop_is_sys_pc2epc;\t// @[core.scala:815:29]\n wire slow_wakeup_2_bits_uop_is_unique;\t// @[core.scala:815:29]\n wire slow_wakeup_2_bits_uop_flush_on_commit;\t// @[core.scala:815:29]\n wire slow_wakeup_2_bits_uop_ldst_is_rs1;\t// @[core.scala:815:29]\n wire [5:0] slow_wakeup_2_bits_uop_ldst;\t// @[core.scala:815:29]\n wire [5:0] slow_wakeup_2_bits_uop_lrs1;\t// @[core.scala:815:29]\n wire [5:0] slow_wakeup_2_bits_uop_lrs2;\t// @[core.scala:815:29]\n wire [5:0] slow_wakeup_2_bits_uop_lrs3;\t// @[core.scala:815:29]\n wire slow_wakeup_2_bits_uop_ldst_val;\t// @[core.scala:815:29]\n wire [1:0] slow_wakeup_2_bits_uop_dst_rtype;\t// @[core.scala:815:29]\n wire [1:0] slow_wakeup_2_bits_uop_lrs1_rtype;\t// @[core.scala:815:29]\n wire [1:0] slow_wakeup_2_bits_uop_lrs2_rtype;\t// @[core.scala:815:29]\n wire slow_wakeup_2_bits_uop_frs3_en;\t// @[core.scala:815:29]\n wire slow_wakeup_2_bits_uop_fp_val;\t// @[core.scala:815:29]\n wire slow_wakeup_2_bits_uop_fp_single;\t// @[core.scala:815:29]\n wire slow_wakeup_2_bits_uop_xcpt_pf_if;\t// @[core.scala:815:29]\n wire slow_wakeup_2_bits_uop_xcpt_ae_if;\t// @[core.scala:815:29]\n wire slow_wakeup_2_bits_uop_xcpt_ma_if;\t// @[core.scala:815:29]\n wire slow_wakeup_2_bits_uop_bp_debug_if;\t// @[core.scala:815:29]\n wire slow_wakeup_2_bits_uop_bp_xcpt_if;\t// @[core.scala:815:29]\n wire [1:0] slow_wakeup_2_bits_uop_debug_fsrc;\t// @[core.scala:815:29]\n wire [1:0] slow_wakeup_2_bits_uop_debug_tsrc;\t// @[core.scala:815:29]\n wire [3:0] int_iss_wakeups_0_bits_uop_ctrl_br_type;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_0_bits_uop_ctrl_op1_sel;\t// @[core.scala:147:30]\n wire [2:0] int_iss_wakeups_0_bits_uop_ctrl_op2_sel;\t// @[core.scala:147:30]\n wire [2:0] int_iss_wakeups_0_bits_uop_ctrl_imm_sel;\t// @[core.scala:147:30]\n wire [4:0] int_iss_wakeups_0_bits_uop_ctrl_op_fcn;\t// @[core.scala:147:30]\n wire int_iss_wakeups_0_bits_uop_ctrl_fcn_dw;\t// @[core.scala:147:30]\n wire [2:0] int_iss_wakeups_0_bits_uop_ctrl_csr_cmd;\t// @[core.scala:147:30]\n wire int_iss_wakeups_0_bits_uop_ctrl_is_load;\t// @[core.scala:147:30]\n wire int_iss_wakeups_0_bits_uop_ctrl_is_sta;\t// @[core.scala:147:30]\n wire int_iss_wakeups_0_bits_uop_ctrl_is_std;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_0_bits_uop_uopc;\t// @[core.scala:147:30]\n wire [31:0] int_iss_wakeups_0_bits_uop_inst;\t// @[core.scala:147:30]\n wire [31:0] int_iss_wakeups_0_bits_uop_debug_inst;\t// @[core.scala:147:30]\n wire int_iss_wakeups_0_bits_uop_is_rvc;\t// @[core.scala:147:30]\n wire [39:0] int_iss_wakeups_0_bits_uop_debug_pc;\t// @[core.scala:147:30]\n wire [2:0] int_iss_wakeups_0_bits_uop_iq_type;\t// @[core.scala:147:30]\n wire [9:0] int_iss_wakeups_0_bits_uop_fu_code;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_0_bits_uop_iw_state;\t// @[core.scala:147:30]\n wire int_iss_wakeups_0_bits_uop_iw_p1_poisoned;\t// @[core.scala:147:30]\n wire int_iss_wakeups_0_bits_uop_iw_p2_poisoned;\t// @[core.scala:147:30]\n wire int_iss_wakeups_0_bits_uop_is_br;\t// @[core.scala:147:30]\n wire int_iss_wakeups_0_bits_uop_is_jalr;\t// @[core.scala:147:30]\n wire int_iss_wakeups_0_bits_uop_is_jal;\t// @[core.scala:147:30]\n wire int_iss_wakeups_0_bits_uop_is_sfb;\t// @[core.scala:147:30]\n wire [15:0] int_iss_wakeups_0_bits_uop_br_mask;\t// @[core.scala:147:30]\n wire [3:0] int_iss_wakeups_0_bits_uop_br_tag;\t// @[core.scala:147:30]\n wire [4:0] int_iss_wakeups_0_bits_uop_ftq_idx;\t// @[core.scala:147:30]\n wire int_iss_wakeups_0_bits_uop_edge_inst;\t// @[core.scala:147:30]\n wire [5:0] int_iss_wakeups_0_bits_uop_pc_lob;\t// @[core.scala:147:30]\n wire int_iss_wakeups_0_bits_uop_taken;\t// @[core.scala:147:30]\n wire [19:0] int_iss_wakeups_0_bits_uop_imm_packed;\t// @[core.scala:147:30]\n wire [11:0] int_iss_wakeups_0_bits_uop_csr_addr;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_0_bits_uop_rob_idx;\t// @[core.scala:147:30]\n wire [4:0] int_iss_wakeups_0_bits_uop_ldq_idx;\t// @[core.scala:147:30]\n wire [4:0] int_iss_wakeups_0_bits_uop_stq_idx;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_0_bits_uop_rxq_idx;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_0_bits_uop_pdst;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_0_bits_uop_prs1;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_0_bits_uop_prs2;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_0_bits_uop_prs3;\t// @[core.scala:147:30]\n wire [4:0] int_iss_wakeups_0_bits_uop_ppred;\t// @[core.scala:147:30]\n wire int_iss_wakeups_0_bits_uop_prs1_busy;\t// @[core.scala:147:30]\n wire int_iss_wakeups_0_bits_uop_prs2_busy;\t// @[core.scala:147:30]\n wire int_iss_wakeups_0_bits_uop_prs3_busy;\t// @[core.scala:147:30]\n wire int_iss_wakeups_0_bits_uop_ppred_busy;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_0_bits_uop_stale_pdst;\t// @[core.scala:147:30]\n wire int_iss_wakeups_0_bits_uop_exception;\t// @[core.scala:147:30]\n wire [63:0] int_iss_wakeups_0_bits_uop_exc_cause;\t// @[core.scala:147:30]\n wire int_iss_wakeups_0_bits_uop_bypassable;\t// @[core.scala:147:30]\n wire [4:0] int_iss_wakeups_0_bits_uop_mem_cmd;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_0_bits_uop_mem_size;\t// @[core.scala:147:30]\n wire int_iss_wakeups_0_bits_uop_mem_signed;\t// @[core.scala:147:30]\n wire int_iss_wakeups_0_bits_uop_is_fence;\t// @[core.scala:147:30]\n wire int_iss_wakeups_0_bits_uop_is_fencei;\t// @[core.scala:147:30]\n wire int_iss_wakeups_0_bits_uop_is_amo;\t// @[core.scala:147:30]\n wire int_iss_wakeups_0_bits_uop_uses_ldq;\t// @[core.scala:147:30]\n wire int_iss_wakeups_0_bits_uop_uses_stq;\t// @[core.scala:147:30]\n wire int_iss_wakeups_0_bits_uop_is_sys_pc2epc;\t// @[core.scala:147:30]\n wire int_iss_wakeups_0_bits_uop_is_unique;\t// @[core.scala:147:30]\n wire int_iss_wakeups_0_bits_uop_flush_on_commit;\t// @[core.scala:147:30]\n wire int_iss_wakeups_0_bits_uop_ldst_is_rs1;\t// @[core.scala:147:30]\n wire [5:0] int_iss_wakeups_0_bits_uop_ldst;\t// @[core.scala:147:30]\n wire [5:0] int_iss_wakeups_0_bits_uop_lrs1;\t// @[core.scala:147:30]\n wire [5:0] int_iss_wakeups_0_bits_uop_lrs2;\t// @[core.scala:147:30]\n wire [5:0] int_iss_wakeups_0_bits_uop_lrs3;\t// @[core.scala:147:30]\n wire int_iss_wakeups_0_bits_uop_ldst_val;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_0_bits_uop_dst_rtype;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_0_bits_uop_lrs1_rtype;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_0_bits_uop_lrs2_rtype;\t// @[core.scala:147:30]\n wire int_iss_wakeups_0_bits_uop_frs3_en;\t// @[core.scala:147:30]\n wire int_iss_wakeups_0_bits_uop_fp_val;\t// @[core.scala:147:30]\n wire int_iss_wakeups_0_bits_uop_fp_single;\t// @[core.scala:147:30]\n wire int_iss_wakeups_0_bits_uop_xcpt_pf_if;\t// @[core.scala:147:30]\n wire int_iss_wakeups_0_bits_uop_xcpt_ae_if;\t// @[core.scala:147:30]\n wire int_iss_wakeups_0_bits_uop_xcpt_ma_if;\t// @[core.scala:147:30]\n wire int_iss_wakeups_0_bits_uop_bp_debug_if;\t// @[core.scala:147:30]\n wire int_iss_wakeups_0_bits_uop_bp_xcpt_if;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_0_bits_uop_debug_fsrc;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_0_bits_uop_debug_tsrc;\t// @[core.scala:147:30]\n wire [3:0] int_iss_wakeups_0_bits_fflags_bits_uop_ctrl_br_type;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_0_bits_fflags_bits_uop_ctrl_op1_sel;\t// @[core.scala:147:30]\n wire [2:0] int_iss_wakeups_0_bits_fflags_bits_uop_ctrl_op2_sel;\t// @[core.scala:147:30]\n wire [2:0] int_iss_wakeups_0_bits_fflags_bits_uop_ctrl_imm_sel;\t// @[core.scala:147:30]\n wire [4:0] int_iss_wakeups_0_bits_fflags_bits_uop_ctrl_op_fcn;\t// @[core.scala:147:30]\n wire int_iss_wakeups_0_bits_fflags_bits_uop_ctrl_fcn_dw;\t// @[core.scala:147:30]\n wire [2:0] int_iss_wakeups_0_bits_fflags_bits_uop_ctrl_csr_cmd;\t// @[core.scala:147:30]\n wire int_iss_wakeups_0_bits_fflags_bits_uop_ctrl_is_load;\t// @[core.scala:147:30]\n wire int_iss_wakeups_0_bits_fflags_bits_uop_ctrl_is_sta;\t// @[core.scala:147:30]\n wire int_iss_wakeups_0_bits_fflags_bits_uop_ctrl_is_std;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_0_bits_fflags_bits_uop_uopc;\t// @[core.scala:147:30]\n wire [31:0] int_iss_wakeups_0_bits_fflags_bits_uop_inst;\t// @[core.scala:147:30]\n wire [31:0] int_iss_wakeups_0_bits_fflags_bits_uop_debug_inst;\t// @[core.scala:147:30]\n wire int_iss_wakeups_0_bits_fflags_bits_uop_is_rvc;\t// @[core.scala:147:30]\n wire [39:0] int_iss_wakeups_0_bits_fflags_bits_uop_debug_pc;\t// @[core.scala:147:30]\n wire [2:0] int_iss_wakeups_0_bits_fflags_bits_uop_iq_type;\t// @[core.scala:147:30]\n wire [9:0] int_iss_wakeups_0_bits_fflags_bits_uop_fu_code;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_0_bits_fflags_bits_uop_iw_state;\t// @[core.scala:147:30]\n wire int_iss_wakeups_0_bits_fflags_bits_uop_iw_p1_poisoned;\t// @[core.scala:147:30]\n wire int_iss_wakeups_0_bits_fflags_bits_uop_iw_p2_poisoned;\t// @[core.scala:147:30]\n wire int_iss_wakeups_0_bits_fflags_bits_uop_is_br;\t// @[core.scala:147:30]\n wire int_iss_wakeups_0_bits_fflags_bits_uop_is_jalr;\t// @[core.scala:147:30]\n wire int_iss_wakeups_0_bits_fflags_bits_uop_is_jal;\t// @[core.scala:147:30]\n wire int_iss_wakeups_0_bits_fflags_bits_uop_is_sfb;\t// @[core.scala:147:30]\n wire [15:0] int_iss_wakeups_0_bits_fflags_bits_uop_br_mask;\t// @[core.scala:147:30]\n wire [3:0] int_iss_wakeups_0_bits_fflags_bits_uop_br_tag;\t// @[core.scala:147:30]\n wire [4:0] int_iss_wakeups_0_bits_fflags_bits_uop_ftq_idx;\t// @[core.scala:147:30]\n wire int_iss_wakeups_0_bits_fflags_bits_uop_edge_inst;\t// @[core.scala:147:30]\n wire [5:0] int_iss_wakeups_0_bits_fflags_bits_uop_pc_lob;\t// @[core.scala:147:30]\n wire int_iss_wakeups_0_bits_fflags_bits_uop_taken;\t// @[core.scala:147:30]\n wire [19:0] int_iss_wakeups_0_bits_fflags_bits_uop_imm_packed;\t// @[core.scala:147:30]\n wire [11:0] int_iss_wakeups_0_bits_fflags_bits_uop_csr_addr;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_0_bits_fflags_bits_uop_rob_idx;\t// @[core.scala:147:30]\n wire [4:0] int_iss_wakeups_0_bits_fflags_bits_uop_ldq_idx;\t// @[core.scala:147:30]\n wire [4:0] int_iss_wakeups_0_bits_fflags_bits_uop_stq_idx;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_0_bits_fflags_bits_uop_rxq_idx;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_0_bits_fflags_bits_uop_pdst;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_0_bits_fflags_bits_uop_prs1;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_0_bits_fflags_bits_uop_prs2;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_0_bits_fflags_bits_uop_prs3;\t// @[core.scala:147:30]\n wire [4:0] int_iss_wakeups_0_bits_fflags_bits_uop_ppred;\t// @[core.scala:147:30]\n wire int_iss_wakeups_0_bits_fflags_bits_uop_prs1_busy;\t// @[core.scala:147:30]\n wire int_iss_wakeups_0_bits_fflags_bits_uop_prs2_busy;\t// @[core.scala:147:30]\n wire int_iss_wakeups_0_bits_fflags_bits_uop_prs3_busy;\t// @[core.scala:147:30]\n wire int_iss_wakeups_0_bits_fflags_bits_uop_ppred_busy;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_0_bits_fflags_bits_uop_stale_pdst;\t// @[core.scala:147:30]\n wire int_iss_wakeups_0_bits_fflags_bits_uop_exception;\t// @[core.scala:147:30]\n wire [63:0] int_iss_wakeups_0_bits_fflags_bits_uop_exc_cause;\t// @[core.scala:147:30]\n wire int_iss_wakeups_0_bits_fflags_bits_uop_bypassable;\t// @[core.scala:147:30]\n wire [4:0] int_iss_wakeups_0_bits_fflags_bits_uop_mem_cmd;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_0_bits_fflags_bits_uop_mem_size;\t// @[core.scala:147:30]\n wire int_iss_wakeups_0_bits_fflags_bits_uop_mem_signed;\t// @[core.scala:147:30]\n wire int_iss_wakeups_0_bits_fflags_bits_uop_is_fence;\t// @[core.scala:147:30]\n wire int_iss_wakeups_0_bits_fflags_bits_uop_is_fencei;\t// @[core.scala:147:30]\n wire int_iss_wakeups_0_bits_fflags_bits_uop_is_amo;\t// @[core.scala:147:30]\n wire int_iss_wakeups_0_bits_fflags_bits_uop_uses_ldq;\t// @[core.scala:147:30]\n wire int_iss_wakeups_0_bits_fflags_bits_uop_uses_stq;\t// @[core.scala:147:30]\n wire int_iss_wakeups_0_bits_fflags_bits_uop_is_sys_pc2epc;\t// @[core.scala:147:30]\n wire int_iss_wakeups_0_bits_fflags_bits_uop_is_unique;\t// @[core.scala:147:30]\n wire int_iss_wakeups_0_bits_fflags_bits_uop_flush_on_commit;\t// @[core.scala:147:30]\n wire int_iss_wakeups_0_bits_fflags_bits_uop_ldst_is_rs1;\t// @[core.scala:147:30]\n wire [5:0] int_iss_wakeups_0_bits_fflags_bits_uop_ldst;\t// @[core.scala:147:30]\n wire [5:0] int_iss_wakeups_0_bits_fflags_bits_uop_lrs1;\t// @[core.scala:147:30]\n wire [5:0] int_iss_wakeups_0_bits_fflags_bits_uop_lrs2;\t// @[core.scala:147:30]\n wire [5:0] int_iss_wakeups_0_bits_fflags_bits_uop_lrs3;\t// @[core.scala:147:30]\n wire int_iss_wakeups_0_bits_fflags_bits_uop_ldst_val;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_0_bits_fflags_bits_uop_dst_rtype;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_0_bits_fflags_bits_uop_lrs1_rtype;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_0_bits_fflags_bits_uop_lrs2_rtype;\t// @[core.scala:147:30]\n wire int_iss_wakeups_0_bits_fflags_bits_uop_frs3_en;\t// @[core.scala:147:30]\n wire int_iss_wakeups_0_bits_fflags_bits_uop_fp_val;\t// @[core.scala:147:30]\n wire int_iss_wakeups_0_bits_fflags_bits_uop_fp_single;\t// @[core.scala:147:30]\n wire int_iss_wakeups_0_bits_fflags_bits_uop_xcpt_pf_if;\t// @[core.scala:147:30]\n wire int_iss_wakeups_0_bits_fflags_bits_uop_xcpt_ae_if;\t// @[core.scala:147:30]\n wire int_iss_wakeups_0_bits_fflags_bits_uop_xcpt_ma_if;\t// @[core.scala:147:30]\n wire int_iss_wakeups_0_bits_fflags_bits_uop_bp_debug_if;\t// @[core.scala:147:30]\n wire int_iss_wakeups_0_bits_fflags_bits_uop_bp_xcpt_if;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_0_bits_fflags_bits_uop_debug_fsrc;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_0_bits_fflags_bits_uop_debug_tsrc;\t// @[core.scala:147:30]\n wire [4:0] int_iss_wakeups_0_bits_fflags_bits_flags;\t// @[core.scala:147:30]\n wire int_iss_wakeups_0_bits_fflags_valid;\t// @[core.scala:147:30]\n wire [63:0] int_iss_wakeups_0_bits_data;\t// @[core.scala:147:30]\n wire int_iss_wakeups_0_bits_predicated;\t// @[core.scala:147:30]\n wire int_iss_wakeups_0_valid;\t// @[core.scala:147:30]\n wire [3:0] int_iss_wakeups_1_bits_uop_ctrl_br_type;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_1_bits_uop_ctrl_op1_sel;\t// @[core.scala:147:30]\n wire [2:0] int_iss_wakeups_1_bits_uop_ctrl_op2_sel;\t// @[core.scala:147:30]\n wire [2:0] int_iss_wakeups_1_bits_uop_ctrl_imm_sel;\t// @[core.scala:147:30]\n wire [4:0] int_iss_wakeups_1_bits_uop_ctrl_op_fcn;\t// @[core.scala:147:30]\n wire int_iss_wakeups_1_bits_uop_ctrl_fcn_dw;\t// @[core.scala:147:30]\n wire [2:0] int_iss_wakeups_1_bits_uop_ctrl_csr_cmd;\t// @[core.scala:147:30]\n wire int_iss_wakeups_1_bits_uop_ctrl_is_load;\t// @[core.scala:147:30]\n wire int_iss_wakeups_1_bits_uop_ctrl_is_sta;\t// @[core.scala:147:30]\n wire int_iss_wakeups_1_bits_uop_ctrl_is_std;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_1_bits_uop_uopc;\t// @[core.scala:147:30]\n wire [31:0] int_iss_wakeups_1_bits_uop_inst;\t// @[core.scala:147:30]\n wire [31:0] int_iss_wakeups_1_bits_uop_debug_inst;\t// @[core.scala:147:30]\n wire int_iss_wakeups_1_bits_uop_is_rvc;\t// @[core.scala:147:30]\n wire [39:0] int_iss_wakeups_1_bits_uop_debug_pc;\t// @[core.scala:147:30]\n wire [2:0] int_iss_wakeups_1_bits_uop_iq_type;\t// @[core.scala:147:30]\n wire [9:0] int_iss_wakeups_1_bits_uop_fu_code;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_1_bits_uop_iw_state;\t// @[core.scala:147:30]\n wire int_iss_wakeups_1_bits_uop_iw_p1_poisoned;\t// @[core.scala:147:30]\n wire int_iss_wakeups_1_bits_uop_iw_p2_poisoned;\t// @[core.scala:147:30]\n wire int_iss_wakeups_1_bits_uop_is_br;\t// @[core.scala:147:30]\n wire int_iss_wakeups_1_bits_uop_is_jalr;\t// @[core.scala:147:30]\n wire int_iss_wakeups_1_bits_uop_is_jal;\t// @[core.scala:147:30]\n wire int_iss_wakeups_1_bits_uop_is_sfb;\t// @[core.scala:147:30]\n wire [15:0] int_iss_wakeups_1_bits_uop_br_mask;\t// @[core.scala:147:30]\n wire [3:0] int_iss_wakeups_1_bits_uop_br_tag;\t// @[core.scala:147:30]\n wire [4:0] int_iss_wakeups_1_bits_uop_ftq_idx;\t// @[core.scala:147:30]\n wire int_iss_wakeups_1_bits_uop_edge_inst;\t// @[core.scala:147:30]\n wire [5:0] int_iss_wakeups_1_bits_uop_pc_lob;\t// @[core.scala:147:30]\n wire int_iss_wakeups_1_bits_uop_taken;\t// @[core.scala:147:30]\n wire [19:0] int_iss_wakeups_1_bits_uop_imm_packed;\t// @[core.scala:147:30]\n wire [11:0] int_iss_wakeups_1_bits_uop_csr_addr;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_1_bits_uop_rob_idx;\t// @[core.scala:147:30]\n wire [4:0] int_iss_wakeups_1_bits_uop_ldq_idx;\t// @[core.scala:147:30]\n wire [4:0] int_iss_wakeups_1_bits_uop_stq_idx;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_1_bits_uop_rxq_idx;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_1_bits_uop_pdst;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_1_bits_uop_prs1;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_1_bits_uop_prs2;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_1_bits_uop_prs3;\t// @[core.scala:147:30]\n wire [4:0] int_iss_wakeups_1_bits_uop_ppred;\t// @[core.scala:147:30]\n wire int_iss_wakeups_1_bits_uop_prs1_busy;\t// @[core.scala:147:30]\n wire int_iss_wakeups_1_bits_uop_prs2_busy;\t// @[core.scala:147:30]\n wire int_iss_wakeups_1_bits_uop_prs3_busy;\t// @[core.scala:147:30]\n wire int_iss_wakeups_1_bits_uop_ppred_busy;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_1_bits_uop_stale_pdst;\t// @[core.scala:147:30]\n wire int_iss_wakeups_1_bits_uop_exception;\t// @[core.scala:147:30]\n wire [63:0] int_iss_wakeups_1_bits_uop_exc_cause;\t// @[core.scala:147:30]\n wire int_iss_wakeups_1_bits_uop_bypassable;\t// @[core.scala:147:30]\n wire [4:0] int_iss_wakeups_1_bits_uop_mem_cmd;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_1_bits_uop_mem_size;\t// @[core.scala:147:30]\n wire int_iss_wakeups_1_bits_uop_mem_signed;\t// @[core.scala:147:30]\n wire int_iss_wakeups_1_bits_uop_is_fence;\t// @[core.scala:147:30]\n wire int_iss_wakeups_1_bits_uop_is_fencei;\t// @[core.scala:147:30]\n wire int_iss_wakeups_1_bits_uop_is_amo;\t// @[core.scala:147:30]\n wire int_iss_wakeups_1_bits_uop_uses_ldq;\t// @[core.scala:147:30]\n wire int_iss_wakeups_1_bits_uop_uses_stq;\t// @[core.scala:147:30]\n wire int_iss_wakeups_1_bits_uop_is_sys_pc2epc;\t// @[core.scala:147:30]\n wire int_iss_wakeups_1_bits_uop_is_unique;\t// @[core.scala:147:30]\n wire int_iss_wakeups_1_bits_uop_flush_on_commit;\t// @[core.scala:147:30]\n wire int_iss_wakeups_1_bits_uop_ldst_is_rs1;\t// @[core.scala:147:30]\n wire [5:0] int_iss_wakeups_1_bits_uop_ldst;\t// @[core.scala:147:30]\n wire [5:0] int_iss_wakeups_1_bits_uop_lrs1;\t// @[core.scala:147:30]\n wire [5:0] int_iss_wakeups_1_bits_uop_lrs2;\t// @[core.scala:147:30]\n wire [5:0] int_iss_wakeups_1_bits_uop_lrs3;\t// @[core.scala:147:30]\n wire int_iss_wakeups_1_bits_uop_ldst_val;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_1_bits_uop_dst_rtype;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_1_bits_uop_lrs1_rtype;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_1_bits_uop_lrs2_rtype;\t// @[core.scala:147:30]\n wire int_iss_wakeups_1_bits_uop_frs3_en;\t// @[core.scala:147:30]\n wire int_iss_wakeups_1_bits_uop_fp_val;\t// @[core.scala:147:30]\n wire int_iss_wakeups_1_bits_uop_fp_single;\t// @[core.scala:147:30]\n wire int_iss_wakeups_1_bits_uop_xcpt_pf_if;\t// @[core.scala:147:30]\n wire int_iss_wakeups_1_bits_uop_xcpt_ae_if;\t// @[core.scala:147:30]\n wire int_iss_wakeups_1_bits_uop_xcpt_ma_if;\t// @[core.scala:147:30]\n wire int_iss_wakeups_1_bits_uop_bp_debug_if;\t// @[core.scala:147:30]\n wire int_iss_wakeups_1_bits_uop_bp_xcpt_if;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_1_bits_uop_debug_fsrc;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_1_bits_uop_debug_tsrc;\t// @[core.scala:147:30]\n wire int_iss_wakeups_1_valid;\t// @[core.scala:147:30]\n wire [3:0] int_iss_wakeups_2_bits_uop_ctrl_br_type;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_2_bits_uop_ctrl_op1_sel;\t// @[core.scala:147:30]\n wire [2:0] int_iss_wakeups_2_bits_uop_ctrl_op2_sel;\t// @[core.scala:147:30]\n wire [2:0] int_iss_wakeups_2_bits_uop_ctrl_imm_sel;\t// @[core.scala:147:30]\n wire [4:0] int_iss_wakeups_2_bits_uop_ctrl_op_fcn;\t// @[core.scala:147:30]\n wire int_iss_wakeups_2_bits_uop_ctrl_fcn_dw;\t// @[core.scala:147:30]\n wire [2:0] int_iss_wakeups_2_bits_uop_ctrl_csr_cmd;\t// @[core.scala:147:30]\n wire int_iss_wakeups_2_bits_uop_ctrl_is_load;\t// @[core.scala:147:30]\n wire int_iss_wakeups_2_bits_uop_ctrl_is_sta;\t// @[core.scala:147:30]\n wire int_iss_wakeups_2_bits_uop_ctrl_is_std;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_2_bits_uop_uopc;\t// @[core.scala:147:30]\n wire [31:0] int_iss_wakeups_2_bits_uop_inst;\t// @[core.scala:147:30]\n wire [31:0] int_iss_wakeups_2_bits_uop_debug_inst;\t// @[core.scala:147:30]\n wire int_iss_wakeups_2_bits_uop_is_rvc;\t// @[core.scala:147:30]\n wire [39:0] int_iss_wakeups_2_bits_uop_debug_pc;\t// @[core.scala:147:30]\n wire [2:0] int_iss_wakeups_2_bits_uop_iq_type;\t// @[core.scala:147:30]\n wire [9:0] int_iss_wakeups_2_bits_uop_fu_code;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_2_bits_uop_iw_state;\t// @[core.scala:147:30]\n wire int_iss_wakeups_2_bits_uop_iw_p1_poisoned;\t// @[core.scala:147:30]\n wire int_iss_wakeups_2_bits_uop_iw_p2_poisoned;\t// @[core.scala:147:30]\n wire int_iss_wakeups_2_bits_uop_is_br;\t// @[core.scala:147:30]\n wire int_iss_wakeups_2_bits_uop_is_jalr;\t// @[core.scala:147:30]\n wire int_iss_wakeups_2_bits_uop_is_jal;\t// @[core.scala:147:30]\n wire int_iss_wakeups_2_bits_uop_is_sfb;\t// @[core.scala:147:30]\n wire [15:0] int_iss_wakeups_2_bits_uop_br_mask;\t// @[core.scala:147:30]\n wire [3:0] int_iss_wakeups_2_bits_uop_br_tag;\t// @[core.scala:147:30]\n wire [4:0] int_iss_wakeups_2_bits_uop_ftq_idx;\t// @[core.scala:147:30]\n wire int_iss_wakeups_2_bits_uop_edge_inst;\t// @[core.scala:147:30]\n wire [5:0] int_iss_wakeups_2_bits_uop_pc_lob;\t// @[core.scala:147:30]\n wire int_iss_wakeups_2_bits_uop_taken;\t// @[core.scala:147:30]\n wire [19:0] int_iss_wakeups_2_bits_uop_imm_packed;\t// @[core.scala:147:30]\n wire [11:0] int_iss_wakeups_2_bits_uop_csr_addr;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_2_bits_uop_rob_idx;\t// @[core.scala:147:30]\n wire [4:0] int_iss_wakeups_2_bits_uop_ldq_idx;\t// @[core.scala:147:30]\n wire [4:0] int_iss_wakeups_2_bits_uop_stq_idx;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_2_bits_uop_rxq_idx;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_2_bits_uop_pdst;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_2_bits_uop_prs1;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_2_bits_uop_prs2;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_2_bits_uop_prs3;\t// @[core.scala:147:30]\n wire [4:0] int_iss_wakeups_2_bits_uop_ppred;\t// @[core.scala:147:30]\n wire int_iss_wakeups_2_bits_uop_prs1_busy;\t// @[core.scala:147:30]\n wire int_iss_wakeups_2_bits_uop_prs2_busy;\t// @[core.scala:147:30]\n wire int_iss_wakeups_2_bits_uop_prs3_busy;\t// @[core.scala:147:30]\n wire int_iss_wakeups_2_bits_uop_ppred_busy;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_2_bits_uop_stale_pdst;\t// @[core.scala:147:30]\n wire int_iss_wakeups_2_bits_uop_exception;\t// @[core.scala:147:30]\n wire [63:0] int_iss_wakeups_2_bits_uop_exc_cause;\t// @[core.scala:147:30]\n wire int_iss_wakeups_2_bits_uop_bypassable;\t// @[core.scala:147:30]\n wire [4:0] int_iss_wakeups_2_bits_uop_mem_cmd;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_2_bits_uop_mem_size;\t// @[core.scala:147:30]\n wire int_iss_wakeups_2_bits_uop_mem_signed;\t// @[core.scala:147:30]\n wire int_iss_wakeups_2_bits_uop_is_fence;\t// @[core.scala:147:30]\n wire int_iss_wakeups_2_bits_uop_is_fencei;\t// @[core.scala:147:30]\n wire int_iss_wakeups_2_bits_uop_is_amo;\t// @[core.scala:147:30]\n wire int_iss_wakeups_2_bits_uop_uses_ldq;\t// @[core.scala:147:30]\n wire int_iss_wakeups_2_bits_uop_uses_stq;\t// @[core.scala:147:30]\n wire int_iss_wakeups_2_bits_uop_is_sys_pc2epc;\t// @[core.scala:147:30]\n wire int_iss_wakeups_2_bits_uop_is_unique;\t// @[core.scala:147:30]\n wire int_iss_wakeups_2_bits_uop_flush_on_commit;\t// @[core.scala:147:30]\n wire int_iss_wakeups_2_bits_uop_ldst_is_rs1;\t// @[core.scala:147:30]\n wire [5:0] int_iss_wakeups_2_bits_uop_ldst;\t// @[core.scala:147:30]\n wire [5:0] int_iss_wakeups_2_bits_uop_lrs1;\t// @[core.scala:147:30]\n wire [5:0] int_iss_wakeups_2_bits_uop_lrs2;\t// @[core.scala:147:30]\n wire [5:0] int_iss_wakeups_2_bits_uop_lrs3;\t// @[core.scala:147:30]\n wire int_iss_wakeups_2_bits_uop_ldst_val;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_2_bits_uop_dst_rtype;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_2_bits_uop_lrs1_rtype;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_2_bits_uop_lrs2_rtype;\t// @[core.scala:147:30]\n wire int_iss_wakeups_2_bits_uop_frs3_en;\t// @[core.scala:147:30]\n wire int_iss_wakeups_2_bits_uop_fp_val;\t// @[core.scala:147:30]\n wire int_iss_wakeups_2_bits_uop_fp_single;\t// @[core.scala:147:30]\n wire int_iss_wakeups_2_bits_uop_xcpt_pf_if;\t// @[core.scala:147:30]\n wire int_iss_wakeups_2_bits_uop_xcpt_ae_if;\t// @[core.scala:147:30]\n wire int_iss_wakeups_2_bits_uop_xcpt_ma_if;\t// @[core.scala:147:30]\n wire int_iss_wakeups_2_bits_uop_bp_debug_if;\t// @[core.scala:147:30]\n wire int_iss_wakeups_2_bits_uop_bp_xcpt_if;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_2_bits_uop_debug_fsrc;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_2_bits_uop_debug_tsrc;\t// @[core.scala:147:30]\n wire int_iss_wakeups_2_valid;\t// @[core.scala:147:30]\n wire [3:0] int_iss_wakeups_3_bits_uop_ctrl_br_type;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_3_bits_uop_ctrl_op1_sel;\t// @[core.scala:147:30]\n wire [2:0] int_iss_wakeups_3_bits_uop_ctrl_op2_sel;\t// @[core.scala:147:30]\n wire [2:0] int_iss_wakeups_3_bits_uop_ctrl_imm_sel;\t// @[core.scala:147:30]\n wire [4:0] int_iss_wakeups_3_bits_uop_ctrl_op_fcn;\t// @[core.scala:147:30]\n wire int_iss_wakeups_3_bits_uop_ctrl_fcn_dw;\t// @[core.scala:147:30]\n wire [2:0] int_iss_wakeups_3_bits_uop_ctrl_csr_cmd;\t// @[core.scala:147:30]\n wire int_iss_wakeups_3_bits_uop_ctrl_is_load;\t// @[core.scala:147:30]\n wire int_iss_wakeups_3_bits_uop_ctrl_is_sta;\t// @[core.scala:147:30]\n wire int_iss_wakeups_3_bits_uop_ctrl_is_std;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_3_bits_uop_uopc;\t// @[core.scala:147:30]\n wire [31:0] int_iss_wakeups_3_bits_uop_inst;\t// @[core.scala:147:30]\n wire [31:0] int_iss_wakeups_3_bits_uop_debug_inst;\t// @[core.scala:147:30]\n wire int_iss_wakeups_3_bits_uop_is_rvc;\t// @[core.scala:147:30]\n wire [39:0] int_iss_wakeups_3_bits_uop_debug_pc;\t// @[core.scala:147:30]\n wire [2:0] int_iss_wakeups_3_bits_uop_iq_type;\t// @[core.scala:147:30]\n wire [9:0] int_iss_wakeups_3_bits_uop_fu_code;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_3_bits_uop_iw_state;\t// @[core.scala:147:30]\n wire int_iss_wakeups_3_bits_uop_iw_p1_poisoned;\t// @[core.scala:147:30]\n wire int_iss_wakeups_3_bits_uop_iw_p2_poisoned;\t// @[core.scala:147:30]\n wire int_iss_wakeups_3_bits_uop_is_br;\t// @[core.scala:147:30]\n wire int_iss_wakeups_3_bits_uop_is_jalr;\t// @[core.scala:147:30]\n wire int_iss_wakeups_3_bits_uop_is_jal;\t// @[core.scala:147:30]\n wire int_iss_wakeups_3_bits_uop_is_sfb;\t// @[core.scala:147:30]\n wire [15:0] int_iss_wakeups_3_bits_uop_br_mask;\t// @[core.scala:147:30]\n wire [3:0] int_iss_wakeups_3_bits_uop_br_tag;\t// @[core.scala:147:30]\n wire [4:0] int_iss_wakeups_3_bits_uop_ftq_idx;\t// @[core.scala:147:30]\n wire int_iss_wakeups_3_bits_uop_edge_inst;\t// @[core.scala:147:30]\n wire [5:0] int_iss_wakeups_3_bits_uop_pc_lob;\t// @[core.scala:147:30]\n wire int_iss_wakeups_3_bits_uop_taken;\t// @[core.scala:147:30]\n wire [19:0] int_iss_wakeups_3_bits_uop_imm_packed;\t// @[core.scala:147:30]\n wire [11:0] int_iss_wakeups_3_bits_uop_csr_addr;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_3_bits_uop_rob_idx;\t// @[core.scala:147:30]\n wire [4:0] int_iss_wakeups_3_bits_uop_ldq_idx;\t// @[core.scala:147:30]\n wire [4:0] int_iss_wakeups_3_bits_uop_stq_idx;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_3_bits_uop_rxq_idx;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_3_bits_uop_pdst;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_3_bits_uop_prs1;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_3_bits_uop_prs2;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_3_bits_uop_prs3;\t// @[core.scala:147:30]\n wire [4:0] int_iss_wakeups_3_bits_uop_ppred;\t// @[core.scala:147:30]\n wire int_iss_wakeups_3_bits_uop_prs1_busy;\t// @[core.scala:147:30]\n wire int_iss_wakeups_3_bits_uop_prs2_busy;\t// @[core.scala:147:30]\n wire int_iss_wakeups_3_bits_uop_prs3_busy;\t// @[core.scala:147:30]\n wire int_iss_wakeups_3_bits_uop_ppred_busy;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_3_bits_uop_stale_pdst;\t// @[core.scala:147:30]\n wire int_iss_wakeups_3_bits_uop_exception;\t// @[core.scala:147:30]\n wire [63:0] int_iss_wakeups_3_bits_uop_exc_cause;\t// @[core.scala:147:30]\n wire int_iss_wakeups_3_bits_uop_bypassable;\t// @[core.scala:147:30]\n wire [4:0] int_iss_wakeups_3_bits_uop_mem_cmd;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_3_bits_uop_mem_size;\t// @[core.scala:147:30]\n wire int_iss_wakeups_3_bits_uop_mem_signed;\t// @[core.scala:147:30]\n wire int_iss_wakeups_3_bits_uop_is_fence;\t// @[core.scala:147:30]\n wire int_iss_wakeups_3_bits_uop_is_fencei;\t// @[core.scala:147:30]\n wire int_iss_wakeups_3_bits_uop_is_amo;\t// @[core.scala:147:30]\n wire int_iss_wakeups_3_bits_uop_uses_ldq;\t// @[core.scala:147:30]\n wire int_iss_wakeups_3_bits_uop_uses_stq;\t// @[core.scala:147:30]\n wire int_iss_wakeups_3_bits_uop_is_sys_pc2epc;\t// @[core.scala:147:30]\n wire int_iss_wakeups_3_bits_uop_is_unique;\t// @[core.scala:147:30]\n wire int_iss_wakeups_3_bits_uop_flush_on_commit;\t// @[core.scala:147:30]\n wire int_iss_wakeups_3_bits_uop_ldst_is_rs1;\t// @[core.scala:147:30]\n wire [5:0] int_iss_wakeups_3_bits_uop_ldst;\t// @[core.scala:147:30]\n wire [5:0] int_iss_wakeups_3_bits_uop_lrs1;\t// @[core.scala:147:30]\n wire [5:0] int_iss_wakeups_3_bits_uop_lrs2;\t// @[core.scala:147:30]\n wire [5:0] int_iss_wakeups_3_bits_uop_lrs3;\t// @[core.scala:147:30]\n wire int_iss_wakeups_3_bits_uop_ldst_val;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_3_bits_uop_dst_rtype;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_3_bits_uop_lrs1_rtype;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_3_bits_uop_lrs2_rtype;\t// @[core.scala:147:30]\n wire int_iss_wakeups_3_bits_uop_frs3_en;\t// @[core.scala:147:30]\n wire int_iss_wakeups_3_bits_uop_fp_val;\t// @[core.scala:147:30]\n wire int_iss_wakeups_3_bits_uop_fp_single;\t// @[core.scala:147:30]\n wire int_iss_wakeups_3_bits_uop_xcpt_pf_if;\t// @[core.scala:147:30]\n wire int_iss_wakeups_3_bits_uop_xcpt_ae_if;\t// @[core.scala:147:30]\n wire int_iss_wakeups_3_bits_uop_xcpt_ma_if;\t// @[core.scala:147:30]\n wire int_iss_wakeups_3_bits_uop_bp_debug_if;\t// @[core.scala:147:30]\n wire int_iss_wakeups_3_bits_uop_bp_xcpt_if;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_3_bits_uop_debug_fsrc;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_3_bits_uop_debug_tsrc;\t// @[core.scala:147:30]\n wire int_iss_wakeups_3_valid;\t// @[core.scala:147:30]\n wire [3:0] int_iss_wakeups_4_bits_uop_ctrl_br_type;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_4_bits_uop_ctrl_op1_sel;\t// @[core.scala:147:30]\n wire [2:0] int_iss_wakeups_4_bits_uop_ctrl_op2_sel;\t// @[core.scala:147:30]\n wire [2:0] int_iss_wakeups_4_bits_uop_ctrl_imm_sel;\t// @[core.scala:147:30]\n wire [4:0] int_iss_wakeups_4_bits_uop_ctrl_op_fcn;\t// @[core.scala:147:30]\n wire int_iss_wakeups_4_bits_uop_ctrl_fcn_dw;\t// @[core.scala:147:30]\n wire [2:0] int_iss_wakeups_4_bits_uop_ctrl_csr_cmd;\t// @[core.scala:147:30]\n wire int_iss_wakeups_4_bits_uop_ctrl_is_load;\t// @[core.scala:147:30]\n wire int_iss_wakeups_4_bits_uop_ctrl_is_sta;\t// @[core.scala:147:30]\n wire int_iss_wakeups_4_bits_uop_ctrl_is_std;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_4_bits_uop_uopc;\t// @[core.scala:147:30]\n wire [31:0] int_iss_wakeups_4_bits_uop_inst;\t// @[core.scala:147:30]\n wire [31:0] int_iss_wakeups_4_bits_uop_debug_inst;\t// @[core.scala:147:30]\n wire int_iss_wakeups_4_bits_uop_is_rvc;\t// @[core.scala:147:30]\n wire [39:0] int_iss_wakeups_4_bits_uop_debug_pc;\t// @[core.scala:147:30]\n wire [2:0] int_iss_wakeups_4_bits_uop_iq_type;\t// @[core.scala:147:30]\n wire [9:0] int_iss_wakeups_4_bits_uop_fu_code;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_4_bits_uop_iw_state;\t// @[core.scala:147:30]\n wire int_iss_wakeups_4_bits_uop_iw_p1_poisoned;\t// @[core.scala:147:30]\n wire int_iss_wakeups_4_bits_uop_iw_p2_poisoned;\t// @[core.scala:147:30]\n wire int_iss_wakeups_4_bits_uop_is_br;\t// @[core.scala:147:30]\n wire int_iss_wakeups_4_bits_uop_is_jalr;\t// @[core.scala:147:30]\n wire int_iss_wakeups_4_bits_uop_is_jal;\t// @[core.scala:147:30]\n wire int_iss_wakeups_4_bits_uop_is_sfb;\t// @[core.scala:147:30]\n wire [15:0] int_iss_wakeups_4_bits_uop_br_mask;\t// @[core.scala:147:30]\n wire [3:0] int_iss_wakeups_4_bits_uop_br_tag;\t// @[core.scala:147:30]\n wire [4:0] int_iss_wakeups_4_bits_uop_ftq_idx;\t// @[core.scala:147:30]\n wire int_iss_wakeups_4_bits_uop_edge_inst;\t// @[core.scala:147:30]\n wire [5:0] int_iss_wakeups_4_bits_uop_pc_lob;\t// @[core.scala:147:30]\n wire int_iss_wakeups_4_bits_uop_taken;\t// @[core.scala:147:30]\n wire [19:0] int_iss_wakeups_4_bits_uop_imm_packed;\t// @[core.scala:147:30]\n wire [11:0] int_iss_wakeups_4_bits_uop_csr_addr;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_4_bits_uop_rob_idx;\t// @[core.scala:147:30]\n wire [4:0] int_iss_wakeups_4_bits_uop_ldq_idx;\t// @[core.scala:147:30]\n wire [4:0] int_iss_wakeups_4_bits_uop_stq_idx;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_4_bits_uop_rxq_idx;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_4_bits_uop_pdst;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_4_bits_uop_prs1;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_4_bits_uop_prs2;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_4_bits_uop_prs3;\t// @[core.scala:147:30]\n wire [4:0] int_iss_wakeups_4_bits_uop_ppred;\t// @[core.scala:147:30]\n wire int_iss_wakeups_4_bits_uop_prs1_busy;\t// @[core.scala:147:30]\n wire int_iss_wakeups_4_bits_uop_prs2_busy;\t// @[core.scala:147:30]\n wire int_iss_wakeups_4_bits_uop_prs3_busy;\t// @[core.scala:147:30]\n wire int_iss_wakeups_4_bits_uop_ppred_busy;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_4_bits_uop_stale_pdst;\t// @[core.scala:147:30]\n wire int_iss_wakeups_4_bits_uop_exception;\t// @[core.scala:147:30]\n wire [63:0] int_iss_wakeups_4_bits_uop_exc_cause;\t// @[core.scala:147:30]\n wire int_iss_wakeups_4_bits_uop_bypassable;\t// @[core.scala:147:30]\n wire [4:0] int_iss_wakeups_4_bits_uop_mem_cmd;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_4_bits_uop_mem_size;\t// @[core.scala:147:30]\n wire int_iss_wakeups_4_bits_uop_mem_signed;\t// @[core.scala:147:30]\n wire int_iss_wakeups_4_bits_uop_is_fence;\t// @[core.scala:147:30]\n wire int_iss_wakeups_4_bits_uop_is_fencei;\t// @[core.scala:147:30]\n wire int_iss_wakeups_4_bits_uop_is_amo;\t// @[core.scala:147:30]\n wire int_iss_wakeups_4_bits_uop_uses_ldq;\t// @[core.scala:147:30]\n wire int_iss_wakeups_4_bits_uop_uses_stq;\t// @[core.scala:147:30]\n wire int_iss_wakeups_4_bits_uop_is_sys_pc2epc;\t// @[core.scala:147:30]\n wire int_iss_wakeups_4_bits_uop_is_unique;\t// @[core.scala:147:30]\n wire int_iss_wakeups_4_bits_uop_flush_on_commit;\t// @[core.scala:147:30]\n wire int_iss_wakeups_4_bits_uop_ldst_is_rs1;\t// @[core.scala:147:30]\n wire [5:0] int_iss_wakeups_4_bits_uop_ldst;\t// @[core.scala:147:30]\n wire [5:0] int_iss_wakeups_4_bits_uop_lrs1;\t// @[core.scala:147:30]\n wire [5:0] int_iss_wakeups_4_bits_uop_lrs2;\t// @[core.scala:147:30]\n wire [5:0] int_iss_wakeups_4_bits_uop_lrs3;\t// @[core.scala:147:30]\n wire int_iss_wakeups_4_bits_uop_ldst_val;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_4_bits_uop_dst_rtype;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_4_bits_uop_lrs1_rtype;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_4_bits_uop_lrs2_rtype;\t// @[core.scala:147:30]\n wire int_iss_wakeups_4_bits_uop_frs3_en;\t// @[core.scala:147:30]\n wire int_iss_wakeups_4_bits_uop_fp_val;\t// @[core.scala:147:30]\n wire int_iss_wakeups_4_bits_uop_fp_single;\t// @[core.scala:147:30]\n wire int_iss_wakeups_4_bits_uop_xcpt_pf_if;\t// @[core.scala:147:30]\n wire int_iss_wakeups_4_bits_uop_xcpt_ae_if;\t// @[core.scala:147:30]\n wire int_iss_wakeups_4_bits_uop_xcpt_ma_if;\t// @[core.scala:147:30]\n wire int_iss_wakeups_4_bits_uop_bp_debug_if;\t// @[core.scala:147:30]\n wire int_iss_wakeups_4_bits_uop_bp_xcpt_if;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_4_bits_uop_debug_fsrc;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_4_bits_uop_debug_tsrc;\t// @[core.scala:147:30]\n wire int_iss_wakeups_4_valid;\t// @[core.scala:147:30]\n wire [3:0] int_iss_wakeups_5_bits_uop_ctrl_br_type;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_5_bits_uop_ctrl_op1_sel;\t// @[core.scala:147:30]\n wire [2:0] int_iss_wakeups_5_bits_uop_ctrl_op2_sel;\t// @[core.scala:147:30]\n wire [2:0] int_iss_wakeups_5_bits_uop_ctrl_imm_sel;\t// @[core.scala:147:30]\n wire [4:0] int_iss_wakeups_5_bits_uop_ctrl_op_fcn;\t// @[core.scala:147:30]\n wire int_iss_wakeups_5_bits_uop_ctrl_fcn_dw;\t// @[core.scala:147:30]\n wire [2:0] int_iss_wakeups_5_bits_uop_ctrl_csr_cmd;\t// @[core.scala:147:30]\n wire int_iss_wakeups_5_bits_uop_ctrl_is_load;\t// @[core.scala:147:30]\n wire int_iss_wakeups_5_bits_uop_ctrl_is_sta;\t// @[core.scala:147:30]\n wire int_iss_wakeups_5_bits_uop_ctrl_is_std;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_5_bits_uop_uopc;\t// @[core.scala:147:30]\n wire [31:0] int_iss_wakeups_5_bits_uop_inst;\t// @[core.scala:147:30]\n wire [31:0] int_iss_wakeups_5_bits_uop_debug_inst;\t// @[core.scala:147:30]\n wire int_iss_wakeups_5_bits_uop_is_rvc;\t// @[core.scala:147:30]\n wire [39:0] int_iss_wakeups_5_bits_uop_debug_pc;\t// @[core.scala:147:30]\n wire [2:0] int_iss_wakeups_5_bits_uop_iq_type;\t// @[core.scala:147:30]\n wire [9:0] int_iss_wakeups_5_bits_uop_fu_code;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_5_bits_uop_iw_state;\t// @[core.scala:147:30]\n wire int_iss_wakeups_5_bits_uop_iw_p1_poisoned;\t// @[core.scala:147:30]\n wire int_iss_wakeups_5_bits_uop_iw_p2_poisoned;\t// @[core.scala:147:30]\n wire int_iss_wakeups_5_bits_uop_is_br;\t// @[core.scala:147:30]\n wire int_iss_wakeups_5_bits_uop_is_jalr;\t// @[core.scala:147:30]\n wire int_iss_wakeups_5_bits_uop_is_jal;\t// @[core.scala:147:30]\n wire int_iss_wakeups_5_bits_uop_is_sfb;\t// @[core.scala:147:30]\n wire [15:0] int_iss_wakeups_5_bits_uop_br_mask;\t// @[core.scala:147:30]\n wire [3:0] int_iss_wakeups_5_bits_uop_br_tag;\t// @[core.scala:147:30]\n wire [4:0] int_iss_wakeups_5_bits_uop_ftq_idx;\t// @[core.scala:147:30]\n wire int_iss_wakeups_5_bits_uop_edge_inst;\t// @[core.scala:147:30]\n wire [5:0] int_iss_wakeups_5_bits_uop_pc_lob;\t// @[core.scala:147:30]\n wire int_iss_wakeups_5_bits_uop_taken;\t// @[core.scala:147:30]\n wire [19:0] int_iss_wakeups_5_bits_uop_imm_packed;\t// @[core.scala:147:30]\n wire [11:0] int_iss_wakeups_5_bits_uop_csr_addr;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_5_bits_uop_rob_idx;\t// @[core.scala:147:30]\n wire [4:0] int_iss_wakeups_5_bits_uop_ldq_idx;\t// @[core.scala:147:30]\n wire [4:0] int_iss_wakeups_5_bits_uop_stq_idx;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_5_bits_uop_rxq_idx;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_5_bits_uop_pdst;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_5_bits_uop_prs1;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_5_bits_uop_prs2;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_5_bits_uop_prs3;\t// @[core.scala:147:30]\n wire [4:0] int_iss_wakeups_5_bits_uop_ppred;\t// @[core.scala:147:30]\n wire int_iss_wakeups_5_bits_uop_prs1_busy;\t// @[core.scala:147:30]\n wire int_iss_wakeups_5_bits_uop_prs2_busy;\t// @[core.scala:147:30]\n wire int_iss_wakeups_5_bits_uop_prs3_busy;\t// @[core.scala:147:30]\n wire int_iss_wakeups_5_bits_uop_ppred_busy;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_5_bits_uop_stale_pdst;\t// @[core.scala:147:30]\n wire int_iss_wakeups_5_bits_uop_exception;\t// @[core.scala:147:30]\n wire [63:0] int_iss_wakeups_5_bits_uop_exc_cause;\t// @[core.scala:147:30]\n wire int_iss_wakeups_5_bits_uop_bypassable;\t// @[core.scala:147:30]\n wire [4:0] int_iss_wakeups_5_bits_uop_mem_cmd;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_5_bits_uop_mem_size;\t// @[core.scala:147:30]\n wire int_iss_wakeups_5_bits_uop_mem_signed;\t// @[core.scala:147:30]\n wire int_iss_wakeups_5_bits_uop_is_fence;\t// @[core.scala:147:30]\n wire int_iss_wakeups_5_bits_uop_is_fencei;\t// @[core.scala:147:30]\n wire int_iss_wakeups_5_bits_uop_is_amo;\t// @[core.scala:147:30]\n wire int_iss_wakeups_5_bits_uop_uses_ldq;\t// @[core.scala:147:30]\n wire int_iss_wakeups_5_bits_uop_uses_stq;\t// @[core.scala:147:30]\n wire int_iss_wakeups_5_bits_uop_is_sys_pc2epc;\t// @[core.scala:147:30]\n wire int_iss_wakeups_5_bits_uop_is_unique;\t// @[core.scala:147:30]\n wire int_iss_wakeups_5_bits_uop_flush_on_commit;\t// @[core.scala:147:30]\n wire int_iss_wakeups_5_bits_uop_ldst_is_rs1;\t// @[core.scala:147:30]\n wire [5:0] int_iss_wakeups_5_bits_uop_ldst;\t// @[core.scala:147:30]\n wire [5:0] int_iss_wakeups_5_bits_uop_lrs1;\t// @[core.scala:147:30]\n wire [5:0] int_iss_wakeups_5_bits_uop_lrs2;\t// @[core.scala:147:30]\n wire [5:0] int_iss_wakeups_5_bits_uop_lrs3;\t// @[core.scala:147:30]\n wire int_iss_wakeups_5_bits_uop_ldst_val;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_5_bits_uop_dst_rtype;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_5_bits_uop_lrs1_rtype;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_5_bits_uop_lrs2_rtype;\t// @[core.scala:147:30]\n wire int_iss_wakeups_5_bits_uop_frs3_en;\t// @[core.scala:147:30]\n wire int_iss_wakeups_5_bits_uop_fp_val;\t// @[core.scala:147:30]\n wire int_iss_wakeups_5_bits_uop_fp_single;\t// @[core.scala:147:30]\n wire int_iss_wakeups_5_bits_uop_xcpt_pf_if;\t// @[core.scala:147:30]\n wire int_iss_wakeups_5_bits_uop_xcpt_ae_if;\t// @[core.scala:147:30]\n wire int_iss_wakeups_5_bits_uop_xcpt_ma_if;\t// @[core.scala:147:30]\n wire int_iss_wakeups_5_bits_uop_bp_debug_if;\t// @[core.scala:147:30]\n wire int_iss_wakeups_5_bits_uop_bp_xcpt_if;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_5_bits_uop_debug_fsrc;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_5_bits_uop_debug_tsrc;\t// @[core.scala:147:30]\n wire int_iss_wakeups_5_valid;\t// @[core.scala:147:30]\n wire [3:0] int_iss_wakeups_6_bits_uop_ctrl_br_type;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_6_bits_uop_ctrl_op1_sel;\t// @[core.scala:147:30]\n wire [2:0] int_iss_wakeups_6_bits_uop_ctrl_op2_sel;\t// @[core.scala:147:30]\n wire [2:0] int_iss_wakeups_6_bits_uop_ctrl_imm_sel;\t// @[core.scala:147:30]\n wire [4:0] int_iss_wakeups_6_bits_uop_ctrl_op_fcn;\t// @[core.scala:147:30]\n wire int_iss_wakeups_6_bits_uop_ctrl_fcn_dw;\t// @[core.scala:147:30]\n wire [2:0] int_iss_wakeups_6_bits_uop_ctrl_csr_cmd;\t// @[core.scala:147:30]\n wire int_iss_wakeups_6_bits_uop_ctrl_is_load;\t// @[core.scala:147:30]\n wire int_iss_wakeups_6_bits_uop_ctrl_is_sta;\t// @[core.scala:147:30]\n wire int_iss_wakeups_6_bits_uop_ctrl_is_std;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_6_bits_uop_uopc;\t// @[core.scala:147:30]\n wire [31:0] int_iss_wakeups_6_bits_uop_inst;\t// @[core.scala:147:30]\n wire [31:0] int_iss_wakeups_6_bits_uop_debug_inst;\t// @[core.scala:147:30]\n wire int_iss_wakeups_6_bits_uop_is_rvc;\t// @[core.scala:147:30]\n wire [39:0] int_iss_wakeups_6_bits_uop_debug_pc;\t// @[core.scala:147:30]\n wire [2:0] int_iss_wakeups_6_bits_uop_iq_type;\t// @[core.scala:147:30]\n wire [9:0] int_iss_wakeups_6_bits_uop_fu_code;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_6_bits_uop_iw_state;\t// @[core.scala:147:30]\n wire int_iss_wakeups_6_bits_uop_iw_p1_poisoned;\t// @[core.scala:147:30]\n wire int_iss_wakeups_6_bits_uop_iw_p2_poisoned;\t// @[core.scala:147:30]\n wire int_iss_wakeups_6_bits_uop_is_br;\t// @[core.scala:147:30]\n wire int_iss_wakeups_6_bits_uop_is_jalr;\t// @[core.scala:147:30]\n wire int_iss_wakeups_6_bits_uop_is_jal;\t// @[core.scala:147:30]\n wire int_iss_wakeups_6_bits_uop_is_sfb;\t// @[core.scala:147:30]\n wire [15:0] int_iss_wakeups_6_bits_uop_br_mask;\t// @[core.scala:147:30]\n wire [3:0] int_iss_wakeups_6_bits_uop_br_tag;\t// @[core.scala:147:30]\n wire [4:0] int_iss_wakeups_6_bits_uop_ftq_idx;\t// @[core.scala:147:30]\n wire int_iss_wakeups_6_bits_uop_edge_inst;\t// @[core.scala:147:30]\n wire [5:0] int_iss_wakeups_6_bits_uop_pc_lob;\t// @[core.scala:147:30]\n wire int_iss_wakeups_6_bits_uop_taken;\t// @[core.scala:147:30]\n wire [19:0] int_iss_wakeups_6_bits_uop_imm_packed;\t// @[core.scala:147:30]\n wire [11:0] int_iss_wakeups_6_bits_uop_csr_addr;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_6_bits_uop_rob_idx;\t// @[core.scala:147:30]\n wire [4:0] int_iss_wakeups_6_bits_uop_ldq_idx;\t// @[core.scala:147:30]\n wire [4:0] int_iss_wakeups_6_bits_uop_stq_idx;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_6_bits_uop_rxq_idx;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_6_bits_uop_pdst;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_6_bits_uop_prs1;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_6_bits_uop_prs2;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_6_bits_uop_prs3;\t// @[core.scala:147:30]\n wire [4:0] int_iss_wakeups_6_bits_uop_ppred;\t// @[core.scala:147:30]\n wire int_iss_wakeups_6_bits_uop_prs1_busy;\t// @[core.scala:147:30]\n wire int_iss_wakeups_6_bits_uop_prs2_busy;\t// @[core.scala:147:30]\n wire int_iss_wakeups_6_bits_uop_prs3_busy;\t// @[core.scala:147:30]\n wire int_iss_wakeups_6_bits_uop_ppred_busy;\t// @[core.scala:147:30]\n wire [6:0] int_iss_wakeups_6_bits_uop_stale_pdst;\t// @[core.scala:147:30]\n wire int_iss_wakeups_6_bits_uop_exception;\t// @[core.scala:147:30]\n wire [63:0] int_iss_wakeups_6_bits_uop_exc_cause;\t// @[core.scala:147:30]\n wire int_iss_wakeups_6_bits_uop_bypassable;\t// @[core.scala:147:30]\n wire [4:0] int_iss_wakeups_6_bits_uop_mem_cmd;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_6_bits_uop_mem_size;\t// @[core.scala:147:30]\n wire int_iss_wakeups_6_bits_uop_mem_signed;\t// @[core.scala:147:30]\n wire int_iss_wakeups_6_bits_uop_is_fence;\t// @[core.scala:147:30]\n wire int_iss_wakeups_6_bits_uop_is_fencei;\t// @[core.scala:147:30]\n wire int_iss_wakeups_6_bits_uop_is_amo;\t// @[core.scala:147:30]\n wire int_iss_wakeups_6_bits_uop_uses_ldq;\t// @[core.scala:147:30]\n wire int_iss_wakeups_6_bits_uop_uses_stq;\t// @[core.scala:147:30]\n wire int_iss_wakeups_6_bits_uop_is_sys_pc2epc;\t// @[core.scala:147:30]\n wire int_iss_wakeups_6_bits_uop_is_unique;\t// @[core.scala:147:30]\n wire int_iss_wakeups_6_bits_uop_flush_on_commit;\t// @[core.scala:147:30]\n wire int_iss_wakeups_6_bits_uop_ldst_is_rs1;\t// @[core.scala:147:30]\n wire [5:0] int_iss_wakeups_6_bits_uop_ldst;\t// @[core.scala:147:30]\n wire [5:0] int_iss_wakeups_6_bits_uop_lrs1;\t// @[core.scala:147:30]\n wire [5:0] int_iss_wakeups_6_bits_uop_lrs2;\t// @[core.scala:147:30]\n wire [5:0] int_iss_wakeups_6_bits_uop_lrs3;\t// @[core.scala:147:30]\n wire int_iss_wakeups_6_bits_uop_ldst_val;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_6_bits_uop_dst_rtype;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_6_bits_uop_lrs1_rtype;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_6_bits_uop_lrs2_rtype;\t// @[core.scala:147:30]\n wire int_iss_wakeups_6_bits_uop_frs3_en;\t// @[core.scala:147:30]\n wire int_iss_wakeups_6_bits_uop_fp_val;\t// @[core.scala:147:30]\n wire int_iss_wakeups_6_bits_uop_fp_single;\t// @[core.scala:147:30]\n wire int_iss_wakeups_6_bits_uop_xcpt_pf_if;\t// @[core.scala:147:30]\n wire int_iss_wakeups_6_bits_uop_xcpt_ae_if;\t// @[core.scala:147:30]\n wire int_iss_wakeups_6_bits_uop_xcpt_ma_if;\t// @[core.scala:147:30]\n wire int_iss_wakeups_6_bits_uop_bp_debug_if;\t// @[core.scala:147:30]\n wire int_iss_wakeups_6_bits_uop_bp_xcpt_if;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_6_bits_uop_debug_fsrc;\t// @[core.scala:147:30]\n wire [1:0] int_iss_wakeups_6_bits_uop_debug_tsrc;\t// @[core.scala:147:30]\n wire int_iss_wakeups_6_valid;\t// @[core.scala:147:30]\n wire _int_ren_wakeups_0_valid_T_2;\t// @[core.scala:798:52]\n wire [3:0] int_ren_wakeups_0_bits_uop_ctrl_br_type;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_0_bits_uop_ctrl_op1_sel;\t// @[core.scala:148:30]\n wire [2:0] int_ren_wakeups_0_bits_uop_ctrl_op2_sel;\t// @[core.scala:148:30]\n wire [2:0] int_ren_wakeups_0_bits_uop_ctrl_imm_sel;\t// @[core.scala:148:30]\n wire [4:0] int_ren_wakeups_0_bits_uop_ctrl_op_fcn;\t// @[core.scala:148:30]\n wire int_ren_wakeups_0_bits_uop_ctrl_fcn_dw;\t// @[core.scala:148:30]\n wire [2:0] int_ren_wakeups_0_bits_uop_ctrl_csr_cmd;\t// @[core.scala:148:30]\n wire int_ren_wakeups_0_bits_uop_ctrl_is_load;\t// @[core.scala:148:30]\n wire int_ren_wakeups_0_bits_uop_ctrl_is_sta;\t// @[core.scala:148:30]\n wire int_ren_wakeups_0_bits_uop_ctrl_is_std;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_0_bits_uop_uopc;\t// @[core.scala:148:30]\n wire [31:0] int_ren_wakeups_0_bits_uop_inst;\t// @[core.scala:148:30]\n wire [31:0] int_ren_wakeups_0_bits_uop_debug_inst;\t// @[core.scala:148:30]\n wire int_ren_wakeups_0_bits_uop_is_rvc;\t// @[core.scala:148:30]\n wire [39:0] int_ren_wakeups_0_bits_uop_debug_pc;\t// @[core.scala:148:30]\n wire [2:0] int_ren_wakeups_0_bits_uop_iq_type;\t// @[core.scala:148:30]\n wire [9:0] int_ren_wakeups_0_bits_uop_fu_code;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_0_bits_uop_iw_state;\t// @[core.scala:148:30]\n wire int_ren_wakeups_0_bits_uop_iw_p1_poisoned;\t// @[core.scala:148:30]\n wire int_ren_wakeups_0_bits_uop_iw_p2_poisoned;\t// @[core.scala:148:30]\n wire int_ren_wakeups_0_bits_uop_is_br;\t// @[core.scala:148:30]\n wire int_ren_wakeups_0_bits_uop_is_jalr;\t// @[core.scala:148:30]\n wire int_ren_wakeups_0_bits_uop_is_jal;\t// @[core.scala:148:30]\n wire int_ren_wakeups_0_bits_uop_is_sfb;\t// @[core.scala:148:30]\n wire [15:0] int_ren_wakeups_0_bits_uop_br_mask;\t// @[core.scala:148:30]\n wire [3:0] int_ren_wakeups_0_bits_uop_br_tag;\t// @[core.scala:148:30]\n wire [4:0] int_ren_wakeups_0_bits_uop_ftq_idx;\t// @[core.scala:148:30]\n wire int_ren_wakeups_0_bits_uop_edge_inst;\t// @[core.scala:148:30]\n wire [5:0] int_ren_wakeups_0_bits_uop_pc_lob;\t// @[core.scala:148:30]\n wire int_ren_wakeups_0_bits_uop_taken;\t// @[core.scala:148:30]\n wire [19:0] int_ren_wakeups_0_bits_uop_imm_packed;\t// @[core.scala:148:30]\n wire [11:0] int_ren_wakeups_0_bits_uop_csr_addr;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_0_bits_uop_rob_idx;\t// @[core.scala:148:30]\n wire [4:0] int_ren_wakeups_0_bits_uop_ldq_idx;\t// @[core.scala:148:30]\n wire [4:0] int_ren_wakeups_0_bits_uop_stq_idx;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_0_bits_uop_rxq_idx;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_0_bits_uop_pdst;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_0_bits_uop_prs1;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_0_bits_uop_prs2;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_0_bits_uop_prs3;\t// @[core.scala:148:30]\n wire [4:0] int_ren_wakeups_0_bits_uop_ppred;\t// @[core.scala:148:30]\n wire int_ren_wakeups_0_bits_uop_prs1_busy;\t// @[core.scala:148:30]\n wire int_ren_wakeups_0_bits_uop_prs2_busy;\t// @[core.scala:148:30]\n wire int_ren_wakeups_0_bits_uop_prs3_busy;\t// @[core.scala:148:30]\n wire int_ren_wakeups_0_bits_uop_ppred_busy;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_0_bits_uop_stale_pdst;\t// @[core.scala:148:30]\n wire int_ren_wakeups_0_bits_uop_exception;\t// @[core.scala:148:30]\n wire [63:0] int_ren_wakeups_0_bits_uop_exc_cause;\t// @[core.scala:148:30]\n wire int_ren_wakeups_0_bits_uop_bypassable;\t// @[core.scala:148:30]\n wire [4:0] int_ren_wakeups_0_bits_uop_mem_cmd;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_0_bits_uop_mem_size;\t// @[core.scala:148:30]\n wire int_ren_wakeups_0_bits_uop_mem_signed;\t// @[core.scala:148:30]\n wire int_ren_wakeups_0_bits_uop_is_fence;\t// @[core.scala:148:30]\n wire int_ren_wakeups_0_bits_uop_is_fencei;\t// @[core.scala:148:30]\n wire int_ren_wakeups_0_bits_uop_is_amo;\t// @[core.scala:148:30]\n wire int_ren_wakeups_0_bits_uop_uses_ldq;\t// @[core.scala:148:30]\n wire int_ren_wakeups_0_bits_uop_uses_stq;\t// @[core.scala:148:30]\n wire int_ren_wakeups_0_bits_uop_is_sys_pc2epc;\t// @[core.scala:148:30]\n wire int_ren_wakeups_0_bits_uop_is_unique;\t// @[core.scala:148:30]\n wire int_ren_wakeups_0_bits_uop_flush_on_commit;\t// @[core.scala:148:30]\n wire int_ren_wakeups_0_bits_uop_ldst_is_rs1;\t// @[core.scala:148:30]\n wire [5:0] int_ren_wakeups_0_bits_uop_ldst;\t// @[core.scala:148:30]\n wire [5:0] int_ren_wakeups_0_bits_uop_lrs1;\t// @[core.scala:148:30]\n wire [5:0] int_ren_wakeups_0_bits_uop_lrs2;\t// @[core.scala:148:30]\n wire [5:0] int_ren_wakeups_0_bits_uop_lrs3;\t// @[core.scala:148:30]\n wire int_ren_wakeups_0_bits_uop_ldst_val;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_0_bits_uop_dst_rtype;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_0_bits_uop_lrs1_rtype;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_0_bits_uop_lrs2_rtype;\t// @[core.scala:148:30]\n wire int_ren_wakeups_0_bits_uop_frs3_en;\t// @[core.scala:148:30]\n wire int_ren_wakeups_0_bits_uop_fp_val;\t// @[core.scala:148:30]\n wire int_ren_wakeups_0_bits_uop_fp_single;\t// @[core.scala:148:30]\n wire int_ren_wakeups_0_bits_uop_xcpt_pf_if;\t// @[core.scala:148:30]\n wire int_ren_wakeups_0_bits_uop_xcpt_ae_if;\t// @[core.scala:148:30]\n wire int_ren_wakeups_0_bits_uop_xcpt_ma_if;\t// @[core.scala:148:30]\n wire int_ren_wakeups_0_bits_uop_bp_debug_if;\t// @[core.scala:148:30]\n wire int_ren_wakeups_0_bits_uop_bp_xcpt_if;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_0_bits_uop_debug_fsrc;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_0_bits_uop_debug_tsrc;\t// @[core.scala:148:30]\n wire [3:0] int_ren_wakeups_0_bits_fflags_bits_uop_ctrl_br_type;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_0_bits_fflags_bits_uop_ctrl_op1_sel;\t// @[core.scala:148:30]\n wire [2:0] int_ren_wakeups_0_bits_fflags_bits_uop_ctrl_op2_sel;\t// @[core.scala:148:30]\n wire [2:0] int_ren_wakeups_0_bits_fflags_bits_uop_ctrl_imm_sel;\t// @[core.scala:148:30]\n wire [4:0] int_ren_wakeups_0_bits_fflags_bits_uop_ctrl_op_fcn;\t// @[core.scala:148:30]\n wire int_ren_wakeups_0_bits_fflags_bits_uop_ctrl_fcn_dw;\t// @[core.scala:148:30]\n wire [2:0] int_ren_wakeups_0_bits_fflags_bits_uop_ctrl_csr_cmd;\t// @[core.scala:148:30]\n wire int_ren_wakeups_0_bits_fflags_bits_uop_ctrl_is_load;\t// @[core.scala:148:30]\n wire int_ren_wakeups_0_bits_fflags_bits_uop_ctrl_is_sta;\t// @[core.scala:148:30]\n wire int_ren_wakeups_0_bits_fflags_bits_uop_ctrl_is_std;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_0_bits_fflags_bits_uop_uopc;\t// @[core.scala:148:30]\n wire [31:0] int_ren_wakeups_0_bits_fflags_bits_uop_inst;\t// @[core.scala:148:30]\n wire [31:0] int_ren_wakeups_0_bits_fflags_bits_uop_debug_inst;\t// @[core.scala:148:30]\n wire int_ren_wakeups_0_bits_fflags_bits_uop_is_rvc;\t// @[core.scala:148:30]\n wire [39:0] int_ren_wakeups_0_bits_fflags_bits_uop_debug_pc;\t// @[core.scala:148:30]\n wire [2:0] int_ren_wakeups_0_bits_fflags_bits_uop_iq_type;\t// @[core.scala:148:30]\n wire [9:0] int_ren_wakeups_0_bits_fflags_bits_uop_fu_code;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_0_bits_fflags_bits_uop_iw_state;\t// @[core.scala:148:30]\n wire int_ren_wakeups_0_bits_fflags_bits_uop_iw_p1_poisoned;\t// @[core.scala:148:30]\n wire int_ren_wakeups_0_bits_fflags_bits_uop_iw_p2_poisoned;\t// @[core.scala:148:30]\n wire int_ren_wakeups_0_bits_fflags_bits_uop_is_br;\t// @[core.scala:148:30]\n wire int_ren_wakeups_0_bits_fflags_bits_uop_is_jalr;\t// @[core.scala:148:30]\n wire int_ren_wakeups_0_bits_fflags_bits_uop_is_jal;\t// @[core.scala:148:30]\n wire int_ren_wakeups_0_bits_fflags_bits_uop_is_sfb;\t// @[core.scala:148:30]\n wire [15:0] int_ren_wakeups_0_bits_fflags_bits_uop_br_mask;\t// @[core.scala:148:30]\n wire [3:0] int_ren_wakeups_0_bits_fflags_bits_uop_br_tag;\t// @[core.scala:148:30]\n wire [4:0] int_ren_wakeups_0_bits_fflags_bits_uop_ftq_idx;\t// @[core.scala:148:30]\n wire int_ren_wakeups_0_bits_fflags_bits_uop_edge_inst;\t// @[core.scala:148:30]\n wire [5:0] int_ren_wakeups_0_bits_fflags_bits_uop_pc_lob;\t// @[core.scala:148:30]\n wire int_ren_wakeups_0_bits_fflags_bits_uop_taken;\t// @[core.scala:148:30]\n wire [19:0] int_ren_wakeups_0_bits_fflags_bits_uop_imm_packed;\t// @[core.scala:148:30]\n wire [11:0] int_ren_wakeups_0_bits_fflags_bits_uop_csr_addr;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_0_bits_fflags_bits_uop_rob_idx;\t// @[core.scala:148:30]\n wire [4:0] int_ren_wakeups_0_bits_fflags_bits_uop_ldq_idx;\t// @[core.scala:148:30]\n wire [4:0] int_ren_wakeups_0_bits_fflags_bits_uop_stq_idx;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_0_bits_fflags_bits_uop_rxq_idx;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_0_bits_fflags_bits_uop_pdst;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_0_bits_fflags_bits_uop_prs1;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_0_bits_fflags_bits_uop_prs2;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_0_bits_fflags_bits_uop_prs3;\t// @[core.scala:148:30]\n wire [4:0] int_ren_wakeups_0_bits_fflags_bits_uop_ppred;\t// @[core.scala:148:30]\n wire int_ren_wakeups_0_bits_fflags_bits_uop_prs1_busy;\t// @[core.scala:148:30]\n wire int_ren_wakeups_0_bits_fflags_bits_uop_prs2_busy;\t// @[core.scala:148:30]\n wire int_ren_wakeups_0_bits_fflags_bits_uop_prs3_busy;\t// @[core.scala:148:30]\n wire int_ren_wakeups_0_bits_fflags_bits_uop_ppred_busy;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_0_bits_fflags_bits_uop_stale_pdst;\t// @[core.scala:148:30]\n wire int_ren_wakeups_0_bits_fflags_bits_uop_exception;\t// @[core.scala:148:30]\n wire [63:0] int_ren_wakeups_0_bits_fflags_bits_uop_exc_cause;\t// @[core.scala:148:30]\n wire int_ren_wakeups_0_bits_fflags_bits_uop_bypassable;\t// @[core.scala:148:30]\n wire [4:0] int_ren_wakeups_0_bits_fflags_bits_uop_mem_cmd;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_0_bits_fflags_bits_uop_mem_size;\t// @[core.scala:148:30]\n wire int_ren_wakeups_0_bits_fflags_bits_uop_mem_signed;\t// @[core.scala:148:30]\n wire int_ren_wakeups_0_bits_fflags_bits_uop_is_fence;\t// @[core.scala:148:30]\n wire int_ren_wakeups_0_bits_fflags_bits_uop_is_fencei;\t// @[core.scala:148:30]\n wire int_ren_wakeups_0_bits_fflags_bits_uop_is_amo;\t// @[core.scala:148:30]\n wire int_ren_wakeups_0_bits_fflags_bits_uop_uses_ldq;\t// @[core.scala:148:30]\n wire int_ren_wakeups_0_bits_fflags_bits_uop_uses_stq;\t// @[core.scala:148:30]\n wire int_ren_wakeups_0_bits_fflags_bits_uop_is_sys_pc2epc;\t// @[core.scala:148:30]\n wire int_ren_wakeups_0_bits_fflags_bits_uop_is_unique;\t// @[core.scala:148:30]\n wire int_ren_wakeups_0_bits_fflags_bits_uop_flush_on_commit;\t// @[core.scala:148:30]\n wire int_ren_wakeups_0_bits_fflags_bits_uop_ldst_is_rs1;\t// @[core.scala:148:30]\n wire [5:0] int_ren_wakeups_0_bits_fflags_bits_uop_ldst;\t// @[core.scala:148:30]\n wire [5:0] int_ren_wakeups_0_bits_fflags_bits_uop_lrs1;\t// @[core.scala:148:30]\n wire [5:0] int_ren_wakeups_0_bits_fflags_bits_uop_lrs2;\t// @[core.scala:148:30]\n wire [5:0] int_ren_wakeups_0_bits_fflags_bits_uop_lrs3;\t// @[core.scala:148:30]\n wire int_ren_wakeups_0_bits_fflags_bits_uop_ldst_val;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_0_bits_fflags_bits_uop_dst_rtype;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_0_bits_fflags_bits_uop_lrs1_rtype;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_0_bits_fflags_bits_uop_lrs2_rtype;\t// @[core.scala:148:30]\n wire int_ren_wakeups_0_bits_fflags_bits_uop_frs3_en;\t// @[core.scala:148:30]\n wire int_ren_wakeups_0_bits_fflags_bits_uop_fp_val;\t// @[core.scala:148:30]\n wire int_ren_wakeups_0_bits_fflags_bits_uop_fp_single;\t// @[core.scala:148:30]\n wire int_ren_wakeups_0_bits_fflags_bits_uop_xcpt_pf_if;\t// @[core.scala:148:30]\n wire int_ren_wakeups_0_bits_fflags_bits_uop_xcpt_ae_if;\t// @[core.scala:148:30]\n wire int_ren_wakeups_0_bits_fflags_bits_uop_xcpt_ma_if;\t// @[core.scala:148:30]\n wire int_ren_wakeups_0_bits_fflags_bits_uop_bp_debug_if;\t// @[core.scala:148:30]\n wire int_ren_wakeups_0_bits_fflags_bits_uop_bp_xcpt_if;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_0_bits_fflags_bits_uop_debug_fsrc;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_0_bits_fflags_bits_uop_debug_tsrc;\t// @[core.scala:148:30]\n wire [4:0] int_ren_wakeups_0_bits_fflags_bits_flags;\t// @[core.scala:148:30]\n wire int_ren_wakeups_0_bits_fflags_valid;\t// @[core.scala:148:30]\n wire [63:0] int_ren_wakeups_0_bits_data;\t// @[core.scala:148:30]\n wire int_ren_wakeups_0_bits_predicated;\t// @[core.scala:148:30]\n wire int_ren_wakeups_0_valid;\t// @[core.scala:148:30]\n wire [3:0] int_ren_wakeups_1_bits_uop_ctrl_br_type;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_1_bits_uop_ctrl_op1_sel;\t// @[core.scala:148:30]\n wire [2:0] int_ren_wakeups_1_bits_uop_ctrl_op2_sel;\t// @[core.scala:148:30]\n wire [2:0] int_ren_wakeups_1_bits_uop_ctrl_imm_sel;\t// @[core.scala:148:30]\n wire [4:0] int_ren_wakeups_1_bits_uop_ctrl_op_fcn;\t// @[core.scala:148:30]\n wire int_ren_wakeups_1_bits_uop_ctrl_fcn_dw;\t// @[core.scala:148:30]\n wire [2:0] int_ren_wakeups_1_bits_uop_ctrl_csr_cmd;\t// @[core.scala:148:30]\n wire int_ren_wakeups_1_bits_uop_ctrl_is_load;\t// @[core.scala:148:30]\n wire int_ren_wakeups_1_bits_uop_ctrl_is_sta;\t// @[core.scala:148:30]\n wire int_ren_wakeups_1_bits_uop_ctrl_is_std;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_1_bits_uop_uopc;\t// @[core.scala:148:30]\n wire [31:0] int_ren_wakeups_1_bits_uop_inst;\t// @[core.scala:148:30]\n wire [31:0] int_ren_wakeups_1_bits_uop_debug_inst;\t// @[core.scala:148:30]\n wire int_ren_wakeups_1_bits_uop_is_rvc;\t// @[core.scala:148:30]\n wire [39:0] int_ren_wakeups_1_bits_uop_debug_pc;\t// @[core.scala:148:30]\n wire [2:0] int_ren_wakeups_1_bits_uop_iq_type;\t// @[core.scala:148:30]\n wire [9:0] int_ren_wakeups_1_bits_uop_fu_code;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_1_bits_uop_iw_state;\t// @[core.scala:148:30]\n wire int_ren_wakeups_1_bits_uop_iw_p1_poisoned;\t// @[core.scala:148:30]\n wire int_ren_wakeups_1_bits_uop_iw_p2_poisoned;\t// @[core.scala:148:30]\n wire int_ren_wakeups_1_bits_uop_is_br;\t// @[core.scala:148:30]\n wire int_ren_wakeups_1_bits_uop_is_jalr;\t// @[core.scala:148:30]\n wire int_ren_wakeups_1_bits_uop_is_jal;\t// @[core.scala:148:30]\n wire int_ren_wakeups_1_bits_uop_is_sfb;\t// @[core.scala:148:30]\n wire [15:0] int_ren_wakeups_1_bits_uop_br_mask;\t// @[core.scala:148:30]\n wire [3:0] int_ren_wakeups_1_bits_uop_br_tag;\t// @[core.scala:148:30]\n wire [4:0] int_ren_wakeups_1_bits_uop_ftq_idx;\t// @[core.scala:148:30]\n wire int_ren_wakeups_1_bits_uop_edge_inst;\t// @[core.scala:148:30]\n wire [5:0] int_ren_wakeups_1_bits_uop_pc_lob;\t// @[core.scala:148:30]\n wire int_ren_wakeups_1_bits_uop_taken;\t// @[core.scala:148:30]\n wire [19:0] int_ren_wakeups_1_bits_uop_imm_packed;\t// @[core.scala:148:30]\n wire [11:0] int_ren_wakeups_1_bits_uop_csr_addr;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_1_bits_uop_rob_idx;\t// @[core.scala:148:30]\n wire [4:0] int_ren_wakeups_1_bits_uop_ldq_idx;\t// @[core.scala:148:30]\n wire [4:0] int_ren_wakeups_1_bits_uop_stq_idx;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_1_bits_uop_rxq_idx;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_1_bits_uop_pdst;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_1_bits_uop_prs1;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_1_bits_uop_prs2;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_1_bits_uop_prs3;\t// @[core.scala:148:30]\n wire [4:0] int_ren_wakeups_1_bits_uop_ppred;\t// @[core.scala:148:30]\n wire int_ren_wakeups_1_bits_uop_prs1_busy;\t// @[core.scala:148:30]\n wire int_ren_wakeups_1_bits_uop_prs2_busy;\t// @[core.scala:148:30]\n wire int_ren_wakeups_1_bits_uop_prs3_busy;\t// @[core.scala:148:30]\n wire int_ren_wakeups_1_bits_uop_ppred_busy;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_1_bits_uop_stale_pdst;\t// @[core.scala:148:30]\n wire int_ren_wakeups_1_bits_uop_exception;\t// @[core.scala:148:30]\n wire [63:0] int_ren_wakeups_1_bits_uop_exc_cause;\t// @[core.scala:148:30]\n wire int_ren_wakeups_1_bits_uop_bypassable;\t// @[core.scala:148:30]\n wire [4:0] int_ren_wakeups_1_bits_uop_mem_cmd;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_1_bits_uop_mem_size;\t// @[core.scala:148:30]\n wire int_ren_wakeups_1_bits_uop_mem_signed;\t// @[core.scala:148:30]\n wire int_ren_wakeups_1_bits_uop_is_fence;\t// @[core.scala:148:30]\n wire int_ren_wakeups_1_bits_uop_is_fencei;\t// @[core.scala:148:30]\n wire int_ren_wakeups_1_bits_uop_is_amo;\t// @[core.scala:148:30]\n wire int_ren_wakeups_1_bits_uop_uses_ldq;\t// @[core.scala:148:30]\n wire int_ren_wakeups_1_bits_uop_uses_stq;\t// @[core.scala:148:30]\n wire int_ren_wakeups_1_bits_uop_is_sys_pc2epc;\t// @[core.scala:148:30]\n wire int_ren_wakeups_1_bits_uop_is_unique;\t// @[core.scala:148:30]\n wire int_ren_wakeups_1_bits_uop_flush_on_commit;\t// @[core.scala:148:30]\n wire int_ren_wakeups_1_bits_uop_ldst_is_rs1;\t// @[core.scala:148:30]\n wire [5:0] int_ren_wakeups_1_bits_uop_ldst;\t// @[core.scala:148:30]\n wire [5:0] int_ren_wakeups_1_bits_uop_lrs1;\t// @[core.scala:148:30]\n wire [5:0] int_ren_wakeups_1_bits_uop_lrs2;\t// @[core.scala:148:30]\n wire [5:0] int_ren_wakeups_1_bits_uop_lrs3;\t// @[core.scala:148:30]\n wire int_ren_wakeups_1_bits_uop_ldst_val;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_1_bits_uop_dst_rtype;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_1_bits_uop_lrs1_rtype;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_1_bits_uop_lrs2_rtype;\t// @[core.scala:148:30]\n wire int_ren_wakeups_1_bits_uop_frs3_en;\t// @[core.scala:148:30]\n wire int_ren_wakeups_1_bits_uop_fp_val;\t// @[core.scala:148:30]\n wire int_ren_wakeups_1_bits_uop_fp_single;\t// @[core.scala:148:30]\n wire int_ren_wakeups_1_bits_uop_xcpt_pf_if;\t// @[core.scala:148:30]\n wire int_ren_wakeups_1_bits_uop_xcpt_ae_if;\t// @[core.scala:148:30]\n wire int_ren_wakeups_1_bits_uop_xcpt_ma_if;\t// @[core.scala:148:30]\n wire int_ren_wakeups_1_bits_uop_bp_debug_if;\t// @[core.scala:148:30]\n wire int_ren_wakeups_1_bits_uop_bp_xcpt_if;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_1_bits_uop_debug_fsrc;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_1_bits_uop_debug_tsrc;\t// @[core.scala:148:30]\n wire int_ren_wakeups_1_valid;\t// @[core.scala:148:30]\n wire [3:0] int_ren_wakeups_2_bits_uop_ctrl_br_type;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_2_bits_uop_ctrl_op1_sel;\t// @[core.scala:148:30]\n wire [2:0] int_ren_wakeups_2_bits_uop_ctrl_op2_sel;\t// @[core.scala:148:30]\n wire [2:0] int_ren_wakeups_2_bits_uop_ctrl_imm_sel;\t// @[core.scala:148:30]\n wire [4:0] int_ren_wakeups_2_bits_uop_ctrl_op_fcn;\t// @[core.scala:148:30]\n wire int_ren_wakeups_2_bits_uop_ctrl_fcn_dw;\t// @[core.scala:148:30]\n wire [2:0] int_ren_wakeups_2_bits_uop_ctrl_csr_cmd;\t// @[core.scala:148:30]\n wire int_ren_wakeups_2_bits_uop_ctrl_is_load;\t// @[core.scala:148:30]\n wire int_ren_wakeups_2_bits_uop_ctrl_is_sta;\t// @[core.scala:148:30]\n wire int_ren_wakeups_2_bits_uop_ctrl_is_std;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_2_bits_uop_uopc;\t// @[core.scala:148:30]\n wire [31:0] int_ren_wakeups_2_bits_uop_inst;\t// @[core.scala:148:30]\n wire [31:0] int_ren_wakeups_2_bits_uop_debug_inst;\t// @[core.scala:148:30]\n wire int_ren_wakeups_2_bits_uop_is_rvc;\t// @[core.scala:148:30]\n wire [39:0] int_ren_wakeups_2_bits_uop_debug_pc;\t// @[core.scala:148:30]\n wire [2:0] int_ren_wakeups_2_bits_uop_iq_type;\t// @[core.scala:148:30]\n wire [9:0] int_ren_wakeups_2_bits_uop_fu_code;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_2_bits_uop_iw_state;\t// @[core.scala:148:30]\n wire int_ren_wakeups_2_bits_uop_iw_p1_poisoned;\t// @[core.scala:148:30]\n wire int_ren_wakeups_2_bits_uop_iw_p2_poisoned;\t// @[core.scala:148:30]\n wire int_ren_wakeups_2_bits_uop_is_br;\t// @[core.scala:148:30]\n wire int_ren_wakeups_2_bits_uop_is_jalr;\t// @[core.scala:148:30]\n wire int_ren_wakeups_2_bits_uop_is_jal;\t// @[core.scala:148:30]\n wire int_ren_wakeups_2_bits_uop_is_sfb;\t// @[core.scala:148:30]\n wire [15:0] int_ren_wakeups_2_bits_uop_br_mask;\t// @[core.scala:148:30]\n wire [3:0] int_ren_wakeups_2_bits_uop_br_tag;\t// @[core.scala:148:30]\n wire [4:0] int_ren_wakeups_2_bits_uop_ftq_idx;\t// @[core.scala:148:30]\n wire int_ren_wakeups_2_bits_uop_edge_inst;\t// @[core.scala:148:30]\n wire [5:0] int_ren_wakeups_2_bits_uop_pc_lob;\t// @[core.scala:148:30]\n wire int_ren_wakeups_2_bits_uop_taken;\t// @[core.scala:148:30]\n wire [19:0] int_ren_wakeups_2_bits_uop_imm_packed;\t// @[core.scala:148:30]\n wire [11:0] int_ren_wakeups_2_bits_uop_csr_addr;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_2_bits_uop_rob_idx;\t// @[core.scala:148:30]\n wire [4:0] int_ren_wakeups_2_bits_uop_ldq_idx;\t// @[core.scala:148:30]\n wire [4:0] int_ren_wakeups_2_bits_uop_stq_idx;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_2_bits_uop_rxq_idx;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_2_bits_uop_pdst;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_2_bits_uop_prs1;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_2_bits_uop_prs2;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_2_bits_uop_prs3;\t// @[core.scala:148:30]\n wire [4:0] int_ren_wakeups_2_bits_uop_ppred;\t// @[core.scala:148:30]\n wire int_ren_wakeups_2_bits_uop_prs1_busy;\t// @[core.scala:148:30]\n wire int_ren_wakeups_2_bits_uop_prs2_busy;\t// @[core.scala:148:30]\n wire int_ren_wakeups_2_bits_uop_prs3_busy;\t// @[core.scala:148:30]\n wire int_ren_wakeups_2_bits_uop_ppred_busy;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_2_bits_uop_stale_pdst;\t// @[core.scala:148:30]\n wire int_ren_wakeups_2_bits_uop_exception;\t// @[core.scala:148:30]\n wire [63:0] int_ren_wakeups_2_bits_uop_exc_cause;\t// @[core.scala:148:30]\n wire int_ren_wakeups_2_bits_uop_bypassable;\t// @[core.scala:148:30]\n wire [4:0] int_ren_wakeups_2_bits_uop_mem_cmd;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_2_bits_uop_mem_size;\t// @[core.scala:148:30]\n wire int_ren_wakeups_2_bits_uop_mem_signed;\t// @[core.scala:148:30]\n wire int_ren_wakeups_2_bits_uop_is_fence;\t// @[core.scala:148:30]\n wire int_ren_wakeups_2_bits_uop_is_fencei;\t// @[core.scala:148:30]\n wire int_ren_wakeups_2_bits_uop_is_amo;\t// @[core.scala:148:30]\n wire int_ren_wakeups_2_bits_uop_uses_ldq;\t// @[core.scala:148:30]\n wire int_ren_wakeups_2_bits_uop_uses_stq;\t// @[core.scala:148:30]\n wire int_ren_wakeups_2_bits_uop_is_sys_pc2epc;\t// @[core.scala:148:30]\n wire int_ren_wakeups_2_bits_uop_is_unique;\t// @[core.scala:148:30]\n wire int_ren_wakeups_2_bits_uop_flush_on_commit;\t// @[core.scala:148:30]\n wire int_ren_wakeups_2_bits_uop_ldst_is_rs1;\t// @[core.scala:148:30]\n wire [5:0] int_ren_wakeups_2_bits_uop_ldst;\t// @[core.scala:148:30]\n wire [5:0] int_ren_wakeups_2_bits_uop_lrs1;\t// @[core.scala:148:30]\n wire [5:0] int_ren_wakeups_2_bits_uop_lrs2;\t// @[core.scala:148:30]\n wire [5:0] int_ren_wakeups_2_bits_uop_lrs3;\t// @[core.scala:148:30]\n wire int_ren_wakeups_2_bits_uop_ldst_val;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_2_bits_uop_dst_rtype;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_2_bits_uop_lrs1_rtype;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_2_bits_uop_lrs2_rtype;\t// @[core.scala:148:30]\n wire int_ren_wakeups_2_bits_uop_frs3_en;\t// @[core.scala:148:30]\n wire int_ren_wakeups_2_bits_uop_fp_val;\t// @[core.scala:148:30]\n wire int_ren_wakeups_2_bits_uop_fp_single;\t// @[core.scala:148:30]\n wire int_ren_wakeups_2_bits_uop_xcpt_pf_if;\t// @[core.scala:148:30]\n wire int_ren_wakeups_2_bits_uop_xcpt_ae_if;\t// @[core.scala:148:30]\n wire int_ren_wakeups_2_bits_uop_xcpt_ma_if;\t// @[core.scala:148:30]\n wire int_ren_wakeups_2_bits_uop_bp_debug_if;\t// @[core.scala:148:30]\n wire int_ren_wakeups_2_bits_uop_bp_xcpt_if;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_2_bits_uop_debug_fsrc;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_2_bits_uop_debug_tsrc;\t// @[core.scala:148:30]\n wire int_ren_wakeups_2_valid;\t// @[core.scala:148:30]\n wire [3:0] int_ren_wakeups_3_bits_uop_ctrl_br_type;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_3_bits_uop_ctrl_op1_sel;\t// @[core.scala:148:30]\n wire [2:0] int_ren_wakeups_3_bits_uop_ctrl_op2_sel;\t// @[core.scala:148:30]\n wire [2:0] int_ren_wakeups_3_bits_uop_ctrl_imm_sel;\t// @[core.scala:148:30]\n wire [4:0] int_ren_wakeups_3_bits_uop_ctrl_op_fcn;\t// @[core.scala:148:30]\n wire int_ren_wakeups_3_bits_uop_ctrl_fcn_dw;\t// @[core.scala:148:30]\n wire [2:0] int_ren_wakeups_3_bits_uop_ctrl_csr_cmd;\t// @[core.scala:148:30]\n wire int_ren_wakeups_3_bits_uop_ctrl_is_load;\t// @[core.scala:148:30]\n wire int_ren_wakeups_3_bits_uop_ctrl_is_sta;\t// @[core.scala:148:30]\n wire int_ren_wakeups_3_bits_uop_ctrl_is_std;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_3_bits_uop_uopc;\t// @[core.scala:148:30]\n wire [31:0] int_ren_wakeups_3_bits_uop_inst;\t// @[core.scala:148:30]\n wire [31:0] int_ren_wakeups_3_bits_uop_debug_inst;\t// @[core.scala:148:30]\n wire int_ren_wakeups_3_bits_uop_is_rvc;\t// @[core.scala:148:30]\n wire [39:0] int_ren_wakeups_3_bits_uop_debug_pc;\t// @[core.scala:148:30]\n wire [2:0] int_ren_wakeups_3_bits_uop_iq_type;\t// @[core.scala:148:30]\n wire [9:0] int_ren_wakeups_3_bits_uop_fu_code;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_3_bits_uop_iw_state;\t// @[core.scala:148:30]\n wire int_ren_wakeups_3_bits_uop_iw_p1_poisoned;\t// @[core.scala:148:30]\n wire int_ren_wakeups_3_bits_uop_iw_p2_poisoned;\t// @[core.scala:148:30]\n wire int_ren_wakeups_3_bits_uop_is_br;\t// @[core.scala:148:30]\n wire int_ren_wakeups_3_bits_uop_is_jalr;\t// @[core.scala:148:30]\n wire int_ren_wakeups_3_bits_uop_is_jal;\t// @[core.scala:148:30]\n wire int_ren_wakeups_3_bits_uop_is_sfb;\t// @[core.scala:148:30]\n wire [15:0] int_ren_wakeups_3_bits_uop_br_mask;\t// @[core.scala:148:30]\n wire [3:0] int_ren_wakeups_3_bits_uop_br_tag;\t// @[core.scala:148:30]\n wire [4:0] int_ren_wakeups_3_bits_uop_ftq_idx;\t// @[core.scala:148:30]\n wire int_ren_wakeups_3_bits_uop_edge_inst;\t// @[core.scala:148:30]\n wire [5:0] int_ren_wakeups_3_bits_uop_pc_lob;\t// @[core.scala:148:30]\n wire int_ren_wakeups_3_bits_uop_taken;\t// @[core.scala:148:30]\n wire [19:0] int_ren_wakeups_3_bits_uop_imm_packed;\t// @[core.scala:148:30]\n wire [11:0] int_ren_wakeups_3_bits_uop_csr_addr;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_3_bits_uop_rob_idx;\t// @[core.scala:148:30]\n wire [4:0] int_ren_wakeups_3_bits_uop_ldq_idx;\t// @[core.scala:148:30]\n wire [4:0] int_ren_wakeups_3_bits_uop_stq_idx;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_3_bits_uop_rxq_idx;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_3_bits_uop_pdst;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_3_bits_uop_prs1;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_3_bits_uop_prs2;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_3_bits_uop_prs3;\t// @[core.scala:148:30]\n wire [4:0] int_ren_wakeups_3_bits_uop_ppred;\t// @[core.scala:148:30]\n wire int_ren_wakeups_3_bits_uop_prs1_busy;\t// @[core.scala:148:30]\n wire int_ren_wakeups_3_bits_uop_prs2_busy;\t// @[core.scala:148:30]\n wire int_ren_wakeups_3_bits_uop_prs3_busy;\t// @[core.scala:148:30]\n wire int_ren_wakeups_3_bits_uop_ppred_busy;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_3_bits_uop_stale_pdst;\t// @[core.scala:148:30]\n wire int_ren_wakeups_3_bits_uop_exception;\t// @[core.scala:148:30]\n wire [63:0] int_ren_wakeups_3_bits_uop_exc_cause;\t// @[core.scala:148:30]\n wire int_ren_wakeups_3_bits_uop_bypassable;\t// @[core.scala:148:30]\n wire [4:0] int_ren_wakeups_3_bits_uop_mem_cmd;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_3_bits_uop_mem_size;\t// @[core.scala:148:30]\n wire int_ren_wakeups_3_bits_uop_mem_signed;\t// @[core.scala:148:30]\n wire int_ren_wakeups_3_bits_uop_is_fence;\t// @[core.scala:148:30]\n wire int_ren_wakeups_3_bits_uop_is_fencei;\t// @[core.scala:148:30]\n wire int_ren_wakeups_3_bits_uop_is_amo;\t// @[core.scala:148:30]\n wire int_ren_wakeups_3_bits_uop_uses_ldq;\t// @[core.scala:148:30]\n wire int_ren_wakeups_3_bits_uop_uses_stq;\t// @[core.scala:148:30]\n wire int_ren_wakeups_3_bits_uop_is_sys_pc2epc;\t// @[core.scala:148:30]\n wire int_ren_wakeups_3_bits_uop_is_unique;\t// @[core.scala:148:30]\n wire int_ren_wakeups_3_bits_uop_flush_on_commit;\t// @[core.scala:148:30]\n wire int_ren_wakeups_3_bits_uop_ldst_is_rs1;\t// @[core.scala:148:30]\n wire [5:0] int_ren_wakeups_3_bits_uop_ldst;\t// @[core.scala:148:30]\n wire [5:0] int_ren_wakeups_3_bits_uop_lrs1;\t// @[core.scala:148:30]\n wire [5:0] int_ren_wakeups_3_bits_uop_lrs2;\t// @[core.scala:148:30]\n wire [5:0] int_ren_wakeups_3_bits_uop_lrs3;\t// @[core.scala:148:30]\n wire int_ren_wakeups_3_bits_uop_ldst_val;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_3_bits_uop_dst_rtype;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_3_bits_uop_lrs1_rtype;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_3_bits_uop_lrs2_rtype;\t// @[core.scala:148:30]\n wire int_ren_wakeups_3_bits_uop_frs3_en;\t// @[core.scala:148:30]\n wire int_ren_wakeups_3_bits_uop_fp_val;\t// @[core.scala:148:30]\n wire int_ren_wakeups_3_bits_uop_fp_single;\t// @[core.scala:148:30]\n wire int_ren_wakeups_3_bits_uop_xcpt_pf_if;\t// @[core.scala:148:30]\n wire int_ren_wakeups_3_bits_uop_xcpt_ae_if;\t// @[core.scala:148:30]\n wire int_ren_wakeups_3_bits_uop_xcpt_ma_if;\t// @[core.scala:148:30]\n wire int_ren_wakeups_3_bits_uop_bp_debug_if;\t// @[core.scala:148:30]\n wire int_ren_wakeups_3_bits_uop_bp_xcpt_if;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_3_bits_uop_debug_fsrc;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_3_bits_uop_debug_tsrc;\t// @[core.scala:148:30]\n wire int_ren_wakeups_3_valid;\t// @[core.scala:148:30]\n wire [3:0] int_ren_wakeups_4_bits_uop_ctrl_br_type;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_4_bits_uop_ctrl_op1_sel;\t// @[core.scala:148:30]\n wire [2:0] int_ren_wakeups_4_bits_uop_ctrl_op2_sel;\t// @[core.scala:148:30]\n wire [2:0] int_ren_wakeups_4_bits_uop_ctrl_imm_sel;\t// @[core.scala:148:30]\n wire [4:0] int_ren_wakeups_4_bits_uop_ctrl_op_fcn;\t// @[core.scala:148:30]\n wire int_ren_wakeups_4_bits_uop_ctrl_fcn_dw;\t// @[core.scala:148:30]\n wire [2:0] int_ren_wakeups_4_bits_uop_ctrl_csr_cmd;\t// @[core.scala:148:30]\n wire int_ren_wakeups_4_bits_uop_ctrl_is_load;\t// @[core.scala:148:30]\n wire int_ren_wakeups_4_bits_uop_ctrl_is_sta;\t// @[core.scala:148:30]\n wire int_ren_wakeups_4_bits_uop_ctrl_is_std;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_4_bits_uop_uopc;\t// @[core.scala:148:30]\n wire [31:0] int_ren_wakeups_4_bits_uop_inst;\t// @[core.scala:148:30]\n wire [31:0] int_ren_wakeups_4_bits_uop_debug_inst;\t// @[core.scala:148:30]\n wire int_ren_wakeups_4_bits_uop_is_rvc;\t// @[core.scala:148:30]\n wire [39:0] int_ren_wakeups_4_bits_uop_debug_pc;\t// @[core.scala:148:30]\n wire [2:0] int_ren_wakeups_4_bits_uop_iq_type;\t// @[core.scala:148:30]\n wire [9:0] int_ren_wakeups_4_bits_uop_fu_code;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_4_bits_uop_iw_state;\t// @[core.scala:148:30]\n wire int_ren_wakeups_4_bits_uop_iw_p1_poisoned;\t// @[core.scala:148:30]\n wire int_ren_wakeups_4_bits_uop_iw_p2_poisoned;\t// @[core.scala:148:30]\n wire int_ren_wakeups_4_bits_uop_is_br;\t// @[core.scala:148:30]\n wire int_ren_wakeups_4_bits_uop_is_jalr;\t// @[core.scala:148:30]\n wire int_ren_wakeups_4_bits_uop_is_jal;\t// @[core.scala:148:30]\n wire int_ren_wakeups_4_bits_uop_is_sfb;\t// @[core.scala:148:30]\n wire [15:0] int_ren_wakeups_4_bits_uop_br_mask;\t// @[core.scala:148:30]\n wire [3:0] int_ren_wakeups_4_bits_uop_br_tag;\t// @[core.scala:148:30]\n wire [4:0] int_ren_wakeups_4_bits_uop_ftq_idx;\t// @[core.scala:148:30]\n wire int_ren_wakeups_4_bits_uop_edge_inst;\t// @[core.scala:148:30]\n wire [5:0] int_ren_wakeups_4_bits_uop_pc_lob;\t// @[core.scala:148:30]\n wire int_ren_wakeups_4_bits_uop_taken;\t// @[core.scala:148:30]\n wire [19:0] int_ren_wakeups_4_bits_uop_imm_packed;\t// @[core.scala:148:30]\n wire [11:0] int_ren_wakeups_4_bits_uop_csr_addr;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_4_bits_uop_rob_idx;\t// @[core.scala:148:30]\n wire [4:0] int_ren_wakeups_4_bits_uop_ldq_idx;\t// @[core.scala:148:30]\n wire [4:0] int_ren_wakeups_4_bits_uop_stq_idx;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_4_bits_uop_rxq_idx;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_4_bits_uop_pdst;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_4_bits_uop_prs1;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_4_bits_uop_prs2;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_4_bits_uop_prs3;\t// @[core.scala:148:30]\n wire [4:0] int_ren_wakeups_4_bits_uop_ppred;\t// @[core.scala:148:30]\n wire int_ren_wakeups_4_bits_uop_prs1_busy;\t// @[core.scala:148:30]\n wire int_ren_wakeups_4_bits_uop_prs2_busy;\t// @[core.scala:148:30]\n wire int_ren_wakeups_4_bits_uop_prs3_busy;\t// @[core.scala:148:30]\n wire int_ren_wakeups_4_bits_uop_ppred_busy;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_4_bits_uop_stale_pdst;\t// @[core.scala:148:30]\n wire int_ren_wakeups_4_bits_uop_exception;\t// @[core.scala:148:30]\n wire [63:0] int_ren_wakeups_4_bits_uop_exc_cause;\t// @[core.scala:148:30]\n wire int_ren_wakeups_4_bits_uop_bypassable;\t// @[core.scala:148:30]\n wire [4:0] int_ren_wakeups_4_bits_uop_mem_cmd;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_4_bits_uop_mem_size;\t// @[core.scala:148:30]\n wire int_ren_wakeups_4_bits_uop_mem_signed;\t// @[core.scala:148:30]\n wire int_ren_wakeups_4_bits_uop_is_fence;\t// @[core.scala:148:30]\n wire int_ren_wakeups_4_bits_uop_is_fencei;\t// @[core.scala:148:30]\n wire int_ren_wakeups_4_bits_uop_is_amo;\t// @[core.scala:148:30]\n wire int_ren_wakeups_4_bits_uop_uses_ldq;\t// @[core.scala:148:30]\n wire int_ren_wakeups_4_bits_uop_uses_stq;\t// @[core.scala:148:30]\n wire int_ren_wakeups_4_bits_uop_is_sys_pc2epc;\t// @[core.scala:148:30]\n wire int_ren_wakeups_4_bits_uop_is_unique;\t// @[core.scala:148:30]\n wire int_ren_wakeups_4_bits_uop_flush_on_commit;\t// @[core.scala:148:30]\n wire int_ren_wakeups_4_bits_uop_ldst_is_rs1;\t// @[core.scala:148:30]\n wire [5:0] int_ren_wakeups_4_bits_uop_ldst;\t// @[core.scala:148:30]\n wire [5:0] int_ren_wakeups_4_bits_uop_lrs1;\t// @[core.scala:148:30]\n wire [5:0] int_ren_wakeups_4_bits_uop_lrs2;\t// @[core.scala:148:30]\n wire [5:0] int_ren_wakeups_4_bits_uop_lrs3;\t// @[core.scala:148:30]\n wire int_ren_wakeups_4_bits_uop_ldst_val;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_4_bits_uop_dst_rtype;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_4_bits_uop_lrs1_rtype;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_4_bits_uop_lrs2_rtype;\t// @[core.scala:148:30]\n wire int_ren_wakeups_4_bits_uop_frs3_en;\t// @[core.scala:148:30]\n wire int_ren_wakeups_4_bits_uop_fp_val;\t// @[core.scala:148:30]\n wire int_ren_wakeups_4_bits_uop_fp_single;\t// @[core.scala:148:30]\n wire int_ren_wakeups_4_bits_uop_xcpt_pf_if;\t// @[core.scala:148:30]\n wire int_ren_wakeups_4_bits_uop_xcpt_ae_if;\t// @[core.scala:148:30]\n wire int_ren_wakeups_4_bits_uop_xcpt_ma_if;\t// @[core.scala:148:30]\n wire int_ren_wakeups_4_bits_uop_bp_debug_if;\t// @[core.scala:148:30]\n wire int_ren_wakeups_4_bits_uop_bp_xcpt_if;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_4_bits_uop_debug_fsrc;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_4_bits_uop_debug_tsrc;\t// @[core.scala:148:30]\n wire int_ren_wakeups_4_valid;\t// @[core.scala:148:30]\n wire [3:0] int_ren_wakeups_5_bits_uop_ctrl_br_type;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_5_bits_uop_ctrl_op1_sel;\t// @[core.scala:148:30]\n wire [2:0] int_ren_wakeups_5_bits_uop_ctrl_op2_sel;\t// @[core.scala:148:30]\n wire [2:0] int_ren_wakeups_5_bits_uop_ctrl_imm_sel;\t// @[core.scala:148:30]\n wire [4:0] int_ren_wakeups_5_bits_uop_ctrl_op_fcn;\t// @[core.scala:148:30]\n wire int_ren_wakeups_5_bits_uop_ctrl_fcn_dw;\t// @[core.scala:148:30]\n wire [2:0] int_ren_wakeups_5_bits_uop_ctrl_csr_cmd;\t// @[core.scala:148:30]\n wire int_ren_wakeups_5_bits_uop_ctrl_is_load;\t// @[core.scala:148:30]\n wire int_ren_wakeups_5_bits_uop_ctrl_is_sta;\t// @[core.scala:148:30]\n wire int_ren_wakeups_5_bits_uop_ctrl_is_std;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_5_bits_uop_uopc;\t// @[core.scala:148:30]\n wire [31:0] int_ren_wakeups_5_bits_uop_inst;\t// @[core.scala:148:30]\n wire [31:0] int_ren_wakeups_5_bits_uop_debug_inst;\t// @[core.scala:148:30]\n wire int_ren_wakeups_5_bits_uop_is_rvc;\t// @[core.scala:148:30]\n wire [39:0] int_ren_wakeups_5_bits_uop_debug_pc;\t// @[core.scala:148:30]\n wire [2:0] int_ren_wakeups_5_bits_uop_iq_type;\t// @[core.scala:148:30]\n wire [9:0] int_ren_wakeups_5_bits_uop_fu_code;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_5_bits_uop_iw_state;\t// @[core.scala:148:30]\n wire int_ren_wakeups_5_bits_uop_iw_p1_poisoned;\t// @[core.scala:148:30]\n wire int_ren_wakeups_5_bits_uop_iw_p2_poisoned;\t// @[core.scala:148:30]\n wire int_ren_wakeups_5_bits_uop_is_br;\t// @[core.scala:148:30]\n wire int_ren_wakeups_5_bits_uop_is_jalr;\t// @[core.scala:148:30]\n wire int_ren_wakeups_5_bits_uop_is_jal;\t// @[core.scala:148:30]\n wire int_ren_wakeups_5_bits_uop_is_sfb;\t// @[core.scala:148:30]\n wire [15:0] int_ren_wakeups_5_bits_uop_br_mask;\t// @[core.scala:148:30]\n wire [3:0] int_ren_wakeups_5_bits_uop_br_tag;\t// @[core.scala:148:30]\n wire [4:0] int_ren_wakeups_5_bits_uop_ftq_idx;\t// @[core.scala:148:30]\n wire int_ren_wakeups_5_bits_uop_edge_inst;\t// @[core.scala:148:30]\n wire [5:0] int_ren_wakeups_5_bits_uop_pc_lob;\t// @[core.scala:148:30]\n wire int_ren_wakeups_5_bits_uop_taken;\t// @[core.scala:148:30]\n wire [19:0] int_ren_wakeups_5_bits_uop_imm_packed;\t// @[core.scala:148:30]\n wire [11:0] int_ren_wakeups_5_bits_uop_csr_addr;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_5_bits_uop_rob_idx;\t// @[core.scala:148:30]\n wire [4:0] int_ren_wakeups_5_bits_uop_ldq_idx;\t// @[core.scala:148:30]\n wire [4:0] int_ren_wakeups_5_bits_uop_stq_idx;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_5_bits_uop_rxq_idx;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_5_bits_uop_pdst;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_5_bits_uop_prs1;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_5_bits_uop_prs2;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_5_bits_uop_prs3;\t// @[core.scala:148:30]\n wire [4:0] int_ren_wakeups_5_bits_uop_ppred;\t// @[core.scala:148:30]\n wire int_ren_wakeups_5_bits_uop_prs1_busy;\t// @[core.scala:148:30]\n wire int_ren_wakeups_5_bits_uop_prs2_busy;\t// @[core.scala:148:30]\n wire int_ren_wakeups_5_bits_uop_prs3_busy;\t// @[core.scala:148:30]\n wire int_ren_wakeups_5_bits_uop_ppred_busy;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_5_bits_uop_stale_pdst;\t// @[core.scala:148:30]\n wire int_ren_wakeups_5_bits_uop_exception;\t// @[core.scala:148:30]\n wire [63:0] int_ren_wakeups_5_bits_uop_exc_cause;\t// @[core.scala:148:30]\n wire int_ren_wakeups_5_bits_uop_bypassable;\t// @[core.scala:148:30]\n wire [4:0] int_ren_wakeups_5_bits_uop_mem_cmd;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_5_bits_uop_mem_size;\t// @[core.scala:148:30]\n wire int_ren_wakeups_5_bits_uop_mem_signed;\t// @[core.scala:148:30]\n wire int_ren_wakeups_5_bits_uop_is_fence;\t// @[core.scala:148:30]\n wire int_ren_wakeups_5_bits_uop_is_fencei;\t// @[core.scala:148:30]\n wire int_ren_wakeups_5_bits_uop_is_amo;\t// @[core.scala:148:30]\n wire int_ren_wakeups_5_bits_uop_uses_ldq;\t// @[core.scala:148:30]\n wire int_ren_wakeups_5_bits_uop_uses_stq;\t// @[core.scala:148:30]\n wire int_ren_wakeups_5_bits_uop_is_sys_pc2epc;\t// @[core.scala:148:30]\n wire int_ren_wakeups_5_bits_uop_is_unique;\t// @[core.scala:148:30]\n wire int_ren_wakeups_5_bits_uop_flush_on_commit;\t// @[core.scala:148:30]\n wire int_ren_wakeups_5_bits_uop_ldst_is_rs1;\t// @[core.scala:148:30]\n wire [5:0] int_ren_wakeups_5_bits_uop_ldst;\t// @[core.scala:148:30]\n wire [5:0] int_ren_wakeups_5_bits_uop_lrs1;\t// @[core.scala:148:30]\n wire [5:0] int_ren_wakeups_5_bits_uop_lrs2;\t// @[core.scala:148:30]\n wire [5:0] int_ren_wakeups_5_bits_uop_lrs3;\t// @[core.scala:148:30]\n wire int_ren_wakeups_5_bits_uop_ldst_val;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_5_bits_uop_dst_rtype;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_5_bits_uop_lrs1_rtype;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_5_bits_uop_lrs2_rtype;\t// @[core.scala:148:30]\n wire int_ren_wakeups_5_bits_uop_frs3_en;\t// @[core.scala:148:30]\n wire int_ren_wakeups_5_bits_uop_fp_val;\t// @[core.scala:148:30]\n wire int_ren_wakeups_5_bits_uop_fp_single;\t// @[core.scala:148:30]\n wire int_ren_wakeups_5_bits_uop_xcpt_pf_if;\t// @[core.scala:148:30]\n wire int_ren_wakeups_5_bits_uop_xcpt_ae_if;\t// @[core.scala:148:30]\n wire int_ren_wakeups_5_bits_uop_xcpt_ma_if;\t// @[core.scala:148:30]\n wire int_ren_wakeups_5_bits_uop_bp_debug_if;\t// @[core.scala:148:30]\n wire int_ren_wakeups_5_bits_uop_bp_xcpt_if;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_5_bits_uop_debug_fsrc;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_5_bits_uop_debug_tsrc;\t// @[core.scala:148:30]\n wire int_ren_wakeups_5_valid;\t// @[core.scala:148:30]\n wire [3:0] int_ren_wakeups_6_bits_uop_ctrl_br_type;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_6_bits_uop_ctrl_op1_sel;\t// @[core.scala:148:30]\n wire [2:0] int_ren_wakeups_6_bits_uop_ctrl_op2_sel;\t// @[core.scala:148:30]\n wire [2:0] int_ren_wakeups_6_bits_uop_ctrl_imm_sel;\t// @[core.scala:148:30]\n wire [4:0] int_ren_wakeups_6_bits_uop_ctrl_op_fcn;\t// @[core.scala:148:30]\n wire int_ren_wakeups_6_bits_uop_ctrl_fcn_dw;\t// @[core.scala:148:30]\n wire [2:0] int_ren_wakeups_6_bits_uop_ctrl_csr_cmd;\t// @[core.scala:148:30]\n wire int_ren_wakeups_6_bits_uop_ctrl_is_load;\t// @[core.scala:148:30]\n wire int_ren_wakeups_6_bits_uop_ctrl_is_sta;\t// @[core.scala:148:30]\n wire int_ren_wakeups_6_bits_uop_ctrl_is_std;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_6_bits_uop_uopc;\t// @[core.scala:148:30]\n wire [31:0] int_ren_wakeups_6_bits_uop_inst;\t// @[core.scala:148:30]\n wire [31:0] int_ren_wakeups_6_bits_uop_debug_inst;\t// @[core.scala:148:30]\n wire int_ren_wakeups_6_bits_uop_is_rvc;\t// @[core.scala:148:30]\n wire [39:0] int_ren_wakeups_6_bits_uop_debug_pc;\t// @[core.scala:148:30]\n wire [2:0] int_ren_wakeups_6_bits_uop_iq_type;\t// @[core.scala:148:30]\n wire [9:0] int_ren_wakeups_6_bits_uop_fu_code;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_6_bits_uop_iw_state;\t// @[core.scala:148:30]\n wire int_ren_wakeups_6_bits_uop_iw_p1_poisoned;\t// @[core.scala:148:30]\n wire int_ren_wakeups_6_bits_uop_iw_p2_poisoned;\t// @[core.scala:148:30]\n wire int_ren_wakeups_6_bits_uop_is_br;\t// @[core.scala:148:30]\n wire int_ren_wakeups_6_bits_uop_is_jalr;\t// @[core.scala:148:30]\n wire int_ren_wakeups_6_bits_uop_is_jal;\t// @[core.scala:148:30]\n wire int_ren_wakeups_6_bits_uop_is_sfb;\t// @[core.scala:148:30]\n wire [15:0] int_ren_wakeups_6_bits_uop_br_mask;\t// @[core.scala:148:30]\n wire [3:0] int_ren_wakeups_6_bits_uop_br_tag;\t// @[core.scala:148:30]\n wire [4:0] int_ren_wakeups_6_bits_uop_ftq_idx;\t// @[core.scala:148:30]\n wire int_ren_wakeups_6_bits_uop_edge_inst;\t// @[core.scala:148:30]\n wire [5:0] int_ren_wakeups_6_bits_uop_pc_lob;\t// @[core.scala:148:30]\n wire int_ren_wakeups_6_bits_uop_taken;\t// @[core.scala:148:30]\n wire [19:0] int_ren_wakeups_6_bits_uop_imm_packed;\t// @[core.scala:148:30]\n wire [11:0] int_ren_wakeups_6_bits_uop_csr_addr;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_6_bits_uop_rob_idx;\t// @[core.scala:148:30]\n wire [4:0] int_ren_wakeups_6_bits_uop_ldq_idx;\t// @[core.scala:148:30]\n wire [4:0] int_ren_wakeups_6_bits_uop_stq_idx;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_6_bits_uop_rxq_idx;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_6_bits_uop_pdst;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_6_bits_uop_prs1;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_6_bits_uop_prs2;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_6_bits_uop_prs3;\t// @[core.scala:148:30]\n wire [4:0] int_ren_wakeups_6_bits_uop_ppred;\t// @[core.scala:148:30]\n wire int_ren_wakeups_6_bits_uop_prs1_busy;\t// @[core.scala:148:30]\n wire int_ren_wakeups_6_bits_uop_prs2_busy;\t// @[core.scala:148:30]\n wire int_ren_wakeups_6_bits_uop_prs3_busy;\t// @[core.scala:148:30]\n wire int_ren_wakeups_6_bits_uop_ppred_busy;\t// @[core.scala:148:30]\n wire [6:0] int_ren_wakeups_6_bits_uop_stale_pdst;\t// @[core.scala:148:30]\n wire int_ren_wakeups_6_bits_uop_exception;\t// @[core.scala:148:30]\n wire [63:0] int_ren_wakeups_6_bits_uop_exc_cause;\t// @[core.scala:148:30]\n wire int_ren_wakeups_6_bits_uop_bypassable;\t// @[core.scala:148:30]\n wire [4:0] int_ren_wakeups_6_bits_uop_mem_cmd;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_6_bits_uop_mem_size;\t// @[core.scala:148:30]\n wire int_ren_wakeups_6_bits_uop_mem_signed;\t// @[core.scala:148:30]\n wire int_ren_wakeups_6_bits_uop_is_fence;\t// @[core.scala:148:30]\n wire int_ren_wakeups_6_bits_uop_is_fencei;\t// @[core.scala:148:30]\n wire int_ren_wakeups_6_bits_uop_is_amo;\t// @[core.scala:148:30]\n wire int_ren_wakeups_6_bits_uop_uses_ldq;\t// @[core.scala:148:30]\n wire int_ren_wakeups_6_bits_uop_uses_stq;\t// @[core.scala:148:30]\n wire int_ren_wakeups_6_bits_uop_is_sys_pc2epc;\t// @[core.scala:148:30]\n wire int_ren_wakeups_6_bits_uop_is_unique;\t// @[core.scala:148:30]\n wire int_ren_wakeups_6_bits_uop_flush_on_commit;\t// @[core.scala:148:30]\n wire int_ren_wakeups_6_bits_uop_ldst_is_rs1;\t// @[core.scala:148:30]\n wire [5:0] int_ren_wakeups_6_bits_uop_ldst;\t// @[core.scala:148:30]\n wire [5:0] int_ren_wakeups_6_bits_uop_lrs1;\t// @[core.scala:148:30]\n wire [5:0] int_ren_wakeups_6_bits_uop_lrs2;\t// @[core.scala:148:30]\n wire [5:0] int_ren_wakeups_6_bits_uop_lrs3;\t// @[core.scala:148:30]\n wire int_ren_wakeups_6_bits_uop_ldst_val;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_6_bits_uop_dst_rtype;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_6_bits_uop_lrs1_rtype;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_6_bits_uop_lrs2_rtype;\t// @[core.scala:148:30]\n wire int_ren_wakeups_6_bits_uop_frs3_en;\t// @[core.scala:148:30]\n wire int_ren_wakeups_6_bits_uop_fp_val;\t// @[core.scala:148:30]\n wire int_ren_wakeups_6_bits_uop_fp_single;\t// @[core.scala:148:30]\n wire int_ren_wakeups_6_bits_uop_xcpt_pf_if;\t// @[core.scala:148:30]\n wire int_ren_wakeups_6_bits_uop_xcpt_ae_if;\t// @[core.scala:148:30]\n wire int_ren_wakeups_6_bits_uop_xcpt_ma_if;\t// @[core.scala:148:30]\n wire int_ren_wakeups_6_bits_uop_bp_debug_if;\t// @[core.scala:148:30]\n wire int_ren_wakeups_6_bits_uop_bp_xcpt_if;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_6_bits_uop_debug_fsrc;\t// @[core.scala:148:30]\n wire [1:0] int_ren_wakeups_6_bits_uop_debug_tsrc;\t// @[core.scala:148:30]\n wire int_ren_wakeups_6_valid;\t// @[core.scala:148:30]\n wire [6:0] iss_uops_1_uopc;\t// @[core.scala:173:24]\n wire [31:0] iss_uops_1_inst;\t// @[core.scala:173:24]\n wire [31:0] iss_uops_1_debug_inst;\t// @[core.scala:173:24]\n wire iss_uops_1_is_rvc;\t// @[core.scala:173:24]\n wire [39:0] iss_uops_1_debug_pc;\t// @[core.scala:173:24]\n wire [2:0] iss_uops_1_iq_type;\t// @[core.scala:173:24]\n wire [9:0] iss_uops_1_fu_code;\t// @[core.scala:173:24]\n wire [3:0] iss_uops_1_ctrl_br_type;\t// @[core.scala:173:24]\n wire [1:0] iss_uops_1_ctrl_op1_sel;\t// @[core.scala:173:24]\n wire [2:0] iss_uops_1_ctrl_op2_sel;\t// @[core.scala:173:24]\n wire [2:0] iss_uops_1_ctrl_imm_sel;\t// @[core.scala:173:24]\n wire [4:0] iss_uops_1_ctrl_op_fcn;\t// @[core.scala:173:24]\n wire iss_uops_1_ctrl_fcn_dw;\t// @[core.scala:173:24]\n wire [2:0] iss_uops_1_ctrl_csr_cmd;\t// @[core.scala:173:24]\n wire iss_uops_1_ctrl_is_load;\t// @[core.scala:173:24]\n wire iss_uops_1_ctrl_is_sta;\t// @[core.scala:173:24]\n wire iss_uops_1_ctrl_is_std;\t// @[core.scala:173:24]\n wire [1:0] iss_uops_1_iw_state;\t// @[core.scala:173:24]\n wire iss_uops_1_iw_p1_poisoned;\t// @[core.scala:173:24]\n wire iss_uops_1_iw_p2_poisoned;\t// @[core.scala:173:24]\n wire iss_uops_1_is_br;\t// @[core.scala:173:24]\n wire iss_uops_1_is_jalr;\t// @[core.scala:173:24]\n wire iss_uops_1_is_jal;\t// @[core.scala:173:24]\n wire iss_uops_1_is_sfb;\t// @[core.scala:173:24]\n wire [15:0] iss_uops_1_br_mask;\t// @[core.scala:173:24]\n wire [3:0] iss_uops_1_br_tag;\t// @[core.scala:173:24]\n wire [4:0] iss_uops_1_ftq_idx;\t// @[core.scala:173:24]\n wire iss_uops_1_edge_inst;\t// @[core.scala:173:24]\n wire [5:0] iss_uops_1_pc_lob;\t// @[core.scala:173:24]\n wire iss_uops_1_taken;\t// @[core.scala:173:24]\n wire [19:0] iss_uops_1_imm_packed;\t// @[core.scala:173:24]\n wire [11:0] iss_uops_1_csr_addr;\t// @[core.scala:173:24]\n wire [6:0] iss_uops_1_rob_idx;\t// @[core.scala:173:24]\n wire [4:0] iss_uops_1_ldq_idx;\t// @[core.scala:173:24]\n wire [4:0] iss_uops_1_stq_idx;\t// @[core.scala:173:24]\n wire [1:0] iss_uops_1_rxq_idx;\t// @[core.scala:173:24]\n wire [6:0] iss_uops_1_pdst;\t// @[core.scala:173:24]\n wire [6:0] iss_uops_1_prs1;\t// @[core.scala:173:24]\n wire [6:0] iss_uops_1_prs2;\t// @[core.scala:173:24]\n wire [6:0] iss_uops_1_prs3;\t// @[core.scala:173:24]\n wire [4:0] iss_uops_1_ppred;\t// @[core.scala:173:24]\n wire iss_uops_1_prs1_busy;\t// @[core.scala:173:24]\n wire iss_uops_1_prs2_busy;\t// @[core.scala:173:24]\n wire iss_uops_1_prs3_busy;\t// @[core.scala:173:24]\n wire iss_uops_1_ppred_busy;\t// @[core.scala:173:24]\n wire [6:0] iss_uops_1_stale_pdst;\t// @[core.scala:173:24]\n wire iss_uops_1_exception;\t// @[core.scala:173:24]\n wire [63:0] iss_uops_1_exc_cause;\t// @[core.scala:173:24]\n wire iss_uops_1_bypassable;\t// @[core.scala:173:24]\n wire [4:0] iss_uops_1_mem_cmd;\t// @[core.scala:173:24]\n wire [1:0] iss_uops_1_mem_size;\t// @[core.scala:173:24]\n wire iss_uops_1_mem_signed;\t// @[core.scala:173:24]\n wire iss_uops_1_is_fence;\t// @[core.scala:173:24]\n wire iss_uops_1_is_fencei;\t// @[core.scala:173:24]\n wire iss_uops_1_is_amo;\t// @[core.scala:173:24]\n wire iss_uops_1_uses_ldq;\t// @[core.scala:173:24]\n wire iss_uops_1_uses_stq;\t// @[core.scala:173:24]\n wire iss_uops_1_is_sys_pc2epc;\t// @[core.scala:173:24]\n wire iss_uops_1_is_unique;\t// @[core.scala:173:24]\n wire iss_uops_1_flush_on_commit;\t// @[core.scala:173:24]\n wire iss_uops_1_ldst_is_rs1;\t// @[core.scala:173:24]\n wire [5:0] iss_uops_1_ldst;\t// @[core.scala:173:24]\n wire [5:0] iss_uops_1_lrs1;\t// @[core.scala:173:24]\n wire [5:0] iss_uops_1_lrs2;\t// @[core.scala:173:24]\n wire [5:0] iss_uops_1_lrs3;\t// @[core.scala:173:24]\n wire iss_uops_1_ldst_val;\t// @[core.scala:173:24]\n wire [1:0] iss_uops_1_dst_rtype;\t// @[core.scala:173:24]\n wire [1:0] iss_uops_1_lrs1_rtype;\t// @[core.scala:173:24]\n wire [1:0] iss_uops_1_lrs2_rtype;\t// @[core.scala:173:24]\n wire iss_uops_1_frs3_en;\t// @[core.scala:173:24]\n wire iss_uops_1_fp_val;\t// @[core.scala:173:24]\n wire iss_uops_1_fp_single;\t// @[core.scala:173:24]\n wire iss_uops_1_xcpt_pf_if;\t// @[core.scala:173:24]\n wire iss_uops_1_xcpt_ae_if;\t// @[core.scala:173:24]\n wire iss_uops_1_xcpt_ma_if;\t// @[core.scala:173:24]\n wire iss_uops_1_bp_debug_if;\t// @[core.scala:173:24]\n wire iss_uops_1_bp_xcpt_if;\t// @[core.scala:173:24]\n wire [1:0] iss_uops_1_debug_fsrc;\t// @[core.scala:173:24]\n wire [1:0] iss_uops_1_debug_tsrc;\t// @[core.scala:173:24]\n wire [3:0] pred_wakeup_bits_uop_ctrl_br_type;\t// @[core.scala:149:26]\n wire [1:0] pred_wakeup_bits_uop_ctrl_op1_sel;\t// @[core.scala:149:26]\n wire [2:0] pred_wakeup_bits_uop_ctrl_op2_sel;\t// @[core.scala:149:26]\n wire [2:0] pred_wakeup_bits_uop_ctrl_imm_sel;\t// @[core.scala:149:26]\n wire [4:0] pred_wakeup_bits_uop_ctrl_op_fcn;\t// @[core.scala:149:26]\n wire pred_wakeup_bits_uop_ctrl_fcn_dw;\t// @[core.scala:149:26]\n wire [2:0] pred_wakeup_bits_uop_ctrl_csr_cmd;\t// @[core.scala:149:26]\n wire pred_wakeup_bits_uop_ctrl_is_load;\t// @[core.scala:149:26]\n wire pred_wakeup_bits_uop_ctrl_is_sta;\t// @[core.scala:149:26]\n wire pred_wakeup_bits_uop_ctrl_is_std;\t// @[core.scala:149:26]\n wire [6:0] pred_wakeup_bits_uop_uopc;\t// @[core.scala:149:26]\n wire [31:0] pred_wakeup_bits_uop_inst;\t// @[core.scala:149:26]\n wire [31:0] pred_wakeup_bits_uop_debug_inst;\t// @[core.scala:149:26]\n wire pred_wakeup_bits_uop_is_rvc;\t// @[core.scala:149:26]\n wire [39:0] pred_wakeup_bits_uop_debug_pc;\t// @[core.scala:149:26]\n wire [2:0] pred_wakeup_bits_uop_iq_type;\t// @[core.scala:149:26]\n wire [9:0] pred_wakeup_bits_uop_fu_code;\t// @[core.scala:149:26]\n wire [1:0] pred_wakeup_bits_uop_iw_state;\t// @[core.scala:149:26]\n wire pred_wakeup_bits_uop_iw_p1_poisoned;\t// @[core.scala:149:26]\n wire pred_wakeup_bits_uop_iw_p2_poisoned;\t// @[core.scala:149:26]\n wire pred_wakeup_bits_uop_is_br;\t// @[core.scala:149:26]\n wire pred_wakeup_bits_uop_is_jalr;\t// @[core.scala:149:26]\n wire pred_wakeup_bits_uop_is_jal;\t// @[core.scala:149:26]\n wire pred_wakeup_bits_uop_is_sfb;\t// @[core.scala:149:26]\n wire [15:0] pred_wakeup_bits_uop_br_mask;\t// @[core.scala:149:26]\n wire [3:0] pred_wakeup_bits_uop_br_tag;\t// @[core.scala:149:26]\n wire [4:0] pred_wakeup_bits_uop_ftq_idx;\t// @[core.scala:149:26]\n wire pred_wakeup_bits_uop_edge_inst;\t// @[core.scala:149:26]\n wire [5:0] pred_wakeup_bits_uop_pc_lob;\t// @[core.scala:149:26]\n wire pred_wakeup_bits_uop_taken;\t// @[core.scala:149:26]\n wire [19:0] pred_wakeup_bits_uop_imm_packed;\t// @[core.scala:149:26]\n wire [11:0] pred_wakeup_bits_uop_csr_addr;\t// @[core.scala:149:26]\n wire [6:0] pred_wakeup_bits_uop_rob_idx;\t// @[core.scala:149:26]\n wire [4:0] pred_wakeup_bits_uop_ldq_idx;\t// @[core.scala:149:26]\n wire [4:0] pred_wakeup_bits_uop_stq_idx;\t// @[core.scala:149:26]\n wire [1:0] pred_wakeup_bits_uop_rxq_idx;\t// @[core.scala:149:26]\n wire [6:0] pred_wakeup_bits_uop_pdst;\t// @[core.scala:149:26]\n wire [6:0] pred_wakeup_bits_uop_prs1;\t// @[core.scala:149:26]\n wire [6:0] pred_wakeup_bits_uop_prs2;\t// @[core.scala:149:26]\n wire [6:0] pred_wakeup_bits_uop_prs3;\t// @[core.scala:149:26]\n wire [4:0] pred_wakeup_bits_uop_ppred;\t// @[core.scala:149:26]\n wire pred_wakeup_bits_uop_prs1_busy;\t// @[core.scala:149:26]\n wire pred_wakeup_bits_uop_prs2_busy;\t// @[core.scala:149:26]\n wire pred_wakeup_bits_uop_prs3_busy;\t// @[core.scala:149:26]\n wire pred_wakeup_bits_uop_ppred_busy;\t// @[core.scala:149:26]\n wire [6:0] pred_wakeup_bits_uop_stale_pdst;\t// @[core.scala:149:26]\n wire pred_wakeup_bits_uop_exception;\t// @[core.scala:149:26]\n wire [63:0] pred_wakeup_bits_uop_exc_cause;\t// @[core.scala:149:26]\n wire pred_wakeup_bits_uop_bypassable;\t// @[core.scala:149:26]\n wire [4:0] pred_wakeup_bits_uop_mem_cmd;\t// @[core.scala:149:26]\n wire [1:0] pred_wakeup_bits_uop_mem_size;\t// @[core.scala:149:26]\n wire pred_wakeup_bits_uop_mem_signed;\t// @[core.scala:149:26]\n wire pred_wakeup_bits_uop_is_fence;\t// @[core.scala:149:26]\n wire pred_wakeup_bits_uop_is_fencei;\t// @[core.scala:149:26]\n wire pred_wakeup_bits_uop_is_amo;\t// @[core.scala:149:26]\n wire pred_wakeup_bits_uop_uses_ldq;\t// @[core.scala:149:26]\n wire pred_wakeup_bits_uop_uses_stq;\t// @[core.scala:149:26]\n wire pred_wakeup_bits_uop_is_sys_pc2epc;\t// @[core.scala:149:26]\n wire pred_wakeup_bits_uop_is_unique;\t// @[core.scala:149:26]\n wire pred_wakeup_bits_uop_flush_on_commit;\t// @[core.scala:149:26]\n wire pred_wakeup_bits_uop_ldst_is_rs1;\t// @[core.scala:149:26]\n wire [5:0] pred_wakeup_bits_uop_ldst;\t// @[core.scala:149:26]\n wire [5:0] pred_wakeup_bits_uop_lrs1;\t// @[core.scala:149:26]\n wire [5:0] pred_wakeup_bits_uop_lrs2;\t// @[core.scala:149:26]\n wire [5:0] pred_wakeup_bits_uop_lrs3;\t// @[core.scala:149:26]\n wire pred_wakeup_bits_uop_ldst_val;\t// @[core.scala:149:26]\n wire [1:0] pred_wakeup_bits_uop_dst_rtype;\t// @[core.scala:149:26]\n wire [1:0] pred_wakeup_bits_uop_lrs1_rtype;\t// @[core.scala:149:26]\n wire [1:0] pred_wakeup_bits_uop_lrs2_rtype;\t// @[core.scala:149:26]\n wire pred_wakeup_bits_uop_frs3_en;\t// @[core.scala:149:26]\n wire pred_wakeup_bits_uop_fp_val;\t// @[core.scala:149:26]\n wire pred_wakeup_bits_uop_fp_single;\t// @[core.scala:149:26]\n wire pred_wakeup_bits_uop_xcpt_pf_if;\t// @[core.scala:149:26]\n wire pred_wakeup_bits_uop_xcpt_ae_if;\t// @[core.scala:149:26]\n wire pred_wakeup_bits_uop_xcpt_ma_if;\t// @[core.scala:149:26]\n wire pred_wakeup_bits_uop_bp_debug_if;\t// @[core.scala:149:26]\n wire pred_wakeup_bits_uop_bp_xcpt_if;\t// @[core.scala:149:26]\n wire [1:0] pred_wakeup_bits_uop_debug_fsrc;\t// @[core.scala:149:26]\n wire [1:0] pred_wakeup_bits_uop_debug_tsrc;\t// @[core.scala:149:26]\n wire _dec_valids_0_T_3;\t// @[core.scala:508:97]\n wire _dec_valids_1_T_3;\t// @[core.scala:508:97]\n wire _dec_valids_2_T_3;\t// @[core.scala:508:97]\n wire dec_valids_0;\t// @[core.scala:157:24]\n wire dec_valids_1;\t// @[core.scala:157:24]\n wire dec_valids_2;\t// @[core.scala:157:24]\n wire [6:0] dec_uops_0_uopc;\t// @[core.scala:158:24]\n wire [31:0] dec_uops_0_inst;\t// @[core.scala:158:24]\n wire [31:0] dec_uops_0_debug_inst;\t// @[core.scala:158:24]\n wire dec_uops_0_is_rvc;\t// @[core.scala:158:24]\n wire [39:0] dec_uops_0_debug_pc;\t// @[core.scala:158:24]\n wire [2:0] dec_uops_0_iq_type;\t// @[core.scala:158:24]\n wire [9:0] dec_uops_0_fu_code;\t// @[core.scala:158:24]\n wire dec_uops_0_is_br;\t// @[core.scala:158:24]\n wire dec_uops_0_is_jalr;\t// @[core.scala:158:24]\n wire dec_uops_0_is_jal;\t// @[core.scala:158:24]\n wire dec_uops_0_is_sfb;\t// @[core.scala:158:24]\n wire [15:0] dec_uops_0_br_mask;\t// @[core.scala:158:24]\n wire [3:0] dec_uops_0_br_tag;\t// @[core.scala:158:24]\n wire [4:0] dec_uops_0_ftq_idx;\t// @[core.scala:158:24]\n wire dec_uops_0_edge_inst;\t// @[core.scala:158:24]\n wire [5:0] dec_uops_0_pc_lob;\t// @[core.scala:158:24]\n wire dec_uops_0_taken;\t// @[core.scala:158:24]\n wire [19:0] dec_uops_0_imm_packed;\t// @[core.scala:158:24]\n wire dec_uops_0_exception;\t// @[core.scala:158:24]\n wire [63:0] dec_uops_0_exc_cause;\t// @[core.scala:158:24]\n wire dec_uops_0_bypassable;\t// @[core.scala:158:24]\n wire [4:0] dec_uops_0_mem_cmd;\t// @[core.scala:158:24]\n wire [1:0] dec_uops_0_mem_size;\t// @[core.scala:158:24]\n wire dec_uops_0_mem_signed;\t// @[core.scala:158:24]\n wire dec_uops_0_is_fence;\t// @[core.scala:158:24]\n wire dec_uops_0_is_fencei;\t// @[core.scala:158:24]\n wire dec_uops_0_is_amo;\t// @[core.scala:158:24]\n wire dec_uops_0_uses_ldq;\t// @[core.scala:158:24]\n wire dec_uops_0_uses_stq;\t// @[core.scala:158:24]\n wire dec_uops_0_is_sys_pc2epc;\t// @[core.scala:158:24]\n wire dec_uops_0_is_unique;\t// @[core.scala:158:24]\n wire dec_uops_0_flush_on_commit;\t// @[core.scala:158:24]\n wire [5:0] dec_uops_0_ldst;\t// @[core.scala:158:24]\n wire [5:0] dec_uops_0_lrs1;\t// @[core.scala:158:24]\n wire [5:0] dec_uops_0_lrs2;\t// @[core.scala:158:24]\n wire [5:0] dec_uops_0_lrs3;\t// @[core.scala:158:24]\n wire dec_uops_0_ldst_val;\t// @[core.scala:158:24]\n wire [1:0] dec_uops_0_dst_rtype;\t// @[core.scala:158:24]\n wire [1:0] dec_uops_0_lrs1_rtype;\t// @[core.scala:158:24]\n wire [1:0] dec_uops_0_lrs2_rtype;\t// @[core.scala:158:24]\n wire dec_uops_0_frs3_en;\t// @[core.scala:158:24]\n wire dec_uops_0_fp_val;\t// @[core.scala:158:24]\n wire dec_uops_0_fp_single;\t// @[core.scala:158:24]\n wire dec_uops_0_xcpt_pf_if;\t// @[core.scala:158:24]\n wire dec_uops_0_xcpt_ae_if;\t// @[core.scala:158:24]\n wire dec_uops_0_bp_debug_if;\t// @[core.scala:158:24]\n wire dec_uops_0_bp_xcpt_if;\t// @[core.scala:158:24]\n wire [1:0] dec_uops_0_debug_fsrc;\t// @[core.scala:158:24]\n wire [6:0] dec_uops_1_uopc;\t// @[core.scala:158:24]\n wire [31:0] dec_uops_1_inst;\t// @[core.scala:158:24]\n wire [31:0] dec_uops_1_debug_inst;\t// @[core.scala:158:24]\n wire dec_uops_1_is_rvc;\t// @[core.scala:158:24]\n wire [39:0] dec_uops_1_debug_pc;\t// @[core.scala:158:24]\n wire [2:0] dec_uops_1_iq_type;\t// @[core.scala:158:24]\n wire [9:0] dec_uops_1_fu_code;\t// @[core.scala:158:24]\n wire dec_uops_1_is_br;\t// @[core.scala:158:24]\n wire dec_uops_1_is_jalr;\t// @[core.scala:158:24]\n wire dec_uops_1_is_jal;\t// @[core.scala:158:24]\n wire dec_uops_1_is_sfb;\t// @[core.scala:158:24]\n wire [15:0] dec_uops_1_br_mask;\t// @[core.scala:158:24]\n wire [3:0] dec_uops_1_br_tag;\t// @[core.scala:158:24]\n wire [4:0] dec_uops_1_ftq_idx;\t// @[core.scala:158:24]\n wire dec_uops_1_edge_inst;\t// @[core.scala:158:24]\n wire [5:0] dec_uops_1_pc_lob;\t// @[core.scala:158:24]\n wire dec_uops_1_taken;\t// @[core.scala:158:24]\n wire [19:0] dec_uops_1_imm_packed;\t// @[core.scala:158:24]\n wire dec_uops_1_exception;\t// @[core.scala:158:24]\n wire [63:0] dec_uops_1_exc_cause;\t// @[core.scala:158:24]\n wire dec_uops_1_bypassable;\t// @[core.scala:158:24]\n wire [4:0] dec_uops_1_mem_cmd;\t// @[core.scala:158:24]\n wire [1:0] dec_uops_1_mem_size;\t// @[core.scala:158:24]\n wire dec_uops_1_mem_signed;\t// @[core.scala:158:24]\n wire dec_uops_1_is_fence;\t// @[core.scala:158:24]\n wire dec_uops_1_is_fencei;\t// @[core.scala:158:24]\n wire dec_uops_1_is_amo;\t// @[core.scala:158:24]\n wire dec_uops_1_uses_ldq;\t// @[core.scala:158:24]\n wire dec_uops_1_uses_stq;\t// @[core.scala:158:24]\n wire dec_uops_1_is_sys_pc2epc;\t// @[core.scala:158:24]\n wire dec_uops_1_is_unique;\t// @[core.scala:158:24]\n wire dec_uops_1_flush_on_commit;\t// @[core.scala:158:24]\n wire [5:0] dec_uops_1_ldst;\t// @[core.scala:158:24]\n wire [5:0] dec_uops_1_lrs1;\t// @[core.scala:158:24]\n wire [5:0] dec_uops_1_lrs2;\t// @[core.scala:158:24]\n wire [5:0] dec_uops_1_lrs3;\t// @[core.scala:158:24]\n wire dec_uops_1_ldst_val;\t// @[core.scala:158:24]\n wire [1:0] dec_uops_1_dst_rtype;\t// @[core.scala:158:24]\n wire [1:0] dec_uops_1_lrs1_rtype;\t// @[core.scala:158:24]\n wire [1:0] dec_uops_1_lrs2_rtype;\t// @[core.scala:158:24]\n wire dec_uops_1_frs3_en;\t// @[core.scala:158:24]\n wire dec_uops_1_fp_val;\t// @[core.scala:158:24]\n wire dec_uops_1_fp_single;\t// @[core.scala:158:24]\n wire dec_uops_1_xcpt_pf_if;\t// @[core.scala:158:24]\n wire dec_uops_1_xcpt_ae_if;\t// @[core.scala:158:24]\n wire dec_uops_1_bp_debug_if;\t// @[core.scala:158:24]\n wire dec_uops_1_bp_xcpt_if;\t// @[core.scala:158:24]\n wire [1:0] dec_uops_1_debug_fsrc;\t// @[core.scala:158:24]\n wire [6:0] dec_uops_2_uopc;\t// @[core.scala:158:24]\n wire [31:0] dec_uops_2_inst;\t// @[core.scala:158:24]\n wire [31:0] dec_uops_2_debug_inst;\t// @[core.scala:158:24]\n wire dec_uops_2_is_rvc;\t// @[core.scala:158:24]\n wire [39:0] dec_uops_2_debug_pc;\t// @[core.scala:158:24]\n wire [2:0] dec_uops_2_iq_type;\t// @[core.scala:158:24]\n wire [9:0] dec_uops_2_fu_code;\t// @[core.scala:158:24]\n wire dec_uops_2_is_br;\t// @[core.scala:158:24]\n wire dec_uops_2_is_jalr;\t// @[core.scala:158:24]\n wire dec_uops_2_is_jal;\t// @[core.scala:158:24]\n wire dec_uops_2_is_sfb;\t// @[core.scala:158:24]\n wire [15:0] dec_uops_2_br_mask;\t// @[core.scala:158:24]\n wire [3:0] dec_uops_2_br_tag;\t// @[core.scala:158:24]\n wire [4:0] dec_uops_2_ftq_idx;\t// @[core.scala:158:24]\n wire dec_uops_2_edge_inst;\t// @[core.scala:158:24]\n wire [5:0] dec_uops_2_pc_lob;\t// @[core.scala:158:24]\n wire dec_uops_2_taken;\t// @[core.scala:158:24]\n wire [19:0] dec_uops_2_imm_packed;\t// @[core.scala:158:24]\n wire dec_uops_2_exception;\t// @[core.scala:158:24]\n wire [63:0] dec_uops_2_exc_cause;\t// @[core.scala:158:24]\n wire dec_uops_2_bypassable;\t// @[core.scala:158:24]\n wire [4:0] dec_uops_2_mem_cmd;\t// @[core.scala:158:24]\n wire [1:0] dec_uops_2_mem_size;\t// @[core.scala:158:24]\n wire dec_uops_2_mem_signed;\t// @[core.scala:158:24]\n wire dec_uops_2_is_fence;\t// @[core.scala:158:24]\n wire dec_uops_2_is_fencei;\t// @[core.scala:158:24]\n wire dec_uops_2_is_amo;\t// @[core.scala:158:24]\n wire dec_uops_2_uses_ldq;\t// @[core.scala:158:24]\n wire dec_uops_2_uses_stq;\t// @[core.scala:158:24]\n wire dec_uops_2_is_sys_pc2epc;\t// @[core.scala:158:24]\n wire dec_uops_2_is_unique;\t// @[core.scala:158:24]\n wire dec_uops_2_flush_on_commit;\t// @[core.scala:158:24]\n wire [5:0] dec_uops_2_ldst;\t// @[core.scala:158:24]\n wire [5:0] dec_uops_2_lrs1;\t// @[core.scala:158:24]\n wire [5:0] dec_uops_2_lrs2;\t// @[core.scala:158:24]\n wire [5:0] dec_uops_2_lrs3;\t// @[core.scala:158:24]\n wire dec_uops_2_ldst_val;\t// @[core.scala:158:24]\n wire [1:0] dec_uops_2_dst_rtype;\t// @[core.scala:158:24]\n wire [1:0] dec_uops_2_lrs1_rtype;\t// @[core.scala:158:24]\n wire [1:0] dec_uops_2_lrs2_rtype;\t// @[core.scala:158:24]\n wire dec_uops_2_frs3_en;\t// @[core.scala:158:24]\n wire dec_uops_2_fp_val;\t// @[core.scala:158:24]\n wire dec_uops_2_fp_single;\t// @[core.scala:158:24]\n wire dec_uops_2_xcpt_pf_if;\t// @[core.scala:158:24]\n wire dec_uops_2_xcpt_ae_if;\t// @[core.scala:158:24]\n wire dec_uops_2_bp_debug_if;\t// @[core.scala:158:24]\n wire dec_uops_2_bp_xcpt_if;\t// @[core.scala:158:24]\n wire [1:0] dec_uops_2_debug_fsrc;\t// @[core.scala:158:24]\n wire dec_fire_0;\t// @[core.scala:159:24]\n wire dec_fire_1;\t// @[core.scala:159:24]\n wire dec_fire_2;\t// @[core.scala:159:24]\n assign dec_ready = dec_fire_2;\t// @[core.scala:159:24, :161:24]\n assign io_ifu_fetchpacket_ready_0 = dec_ready;\t// @[core.scala:51:7, :161:24]\n wire dec_xcpts_0;\t// @[core.scala:162:24]\n wire dec_xcpts_1;\t// @[core.scala:162:24]\n wire dec_xcpts_2;\t// @[core.scala:162:24]\n wire _ren_stalls_0_T_1;\t// @[core.scala:671:63]\n wire _ren_stalls_1_T_1;\t// @[core.scala:671:63]\n wire _ren_stalls_2_T_1;\t// @[core.scala:671:63]\n wire ren_stalls_0;\t// @[core.scala:163:24]\n wire ren_stalls_1;\t// @[core.scala:163:24]\n wire ren_stalls_2;\t// @[core.scala:163:24]\n wire dis_prior_slot_valid_1 = dis_valids_0;\t// @[core.scala:166:24, :683:71]\n wire dis_valids_1;\t// @[core.scala:166:24]\n wire dis_valids_2;\t// @[core.scala:166:24]\n assign io_lsu_dis_uops_0_bits_uopc_0 = dis_uops_0_uopc;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_0_bits_inst_0 = dis_uops_0_inst;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_0_bits_debug_inst_0 = dis_uops_0_debug_inst;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_0_bits_is_rvc_0 = dis_uops_0_is_rvc;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_0_bits_debug_pc_0 = dis_uops_0_debug_pc;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_0_bits_iq_type_0 = dis_uops_0_iq_type;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_0_bits_fu_code_0 = dis_uops_0_fu_code;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_0_bits_ctrl_br_type_0 = dis_uops_0_ctrl_br_type;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_0_bits_ctrl_op1_sel_0 = dis_uops_0_ctrl_op1_sel;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_0_bits_ctrl_op2_sel_0 = dis_uops_0_ctrl_op2_sel;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_0_bits_ctrl_imm_sel_0 = dis_uops_0_ctrl_imm_sel;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_0_bits_ctrl_op_fcn_0 = dis_uops_0_ctrl_op_fcn;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_0_bits_ctrl_fcn_dw_0 = dis_uops_0_ctrl_fcn_dw;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_0_bits_ctrl_csr_cmd_0 = dis_uops_0_ctrl_csr_cmd;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_0_bits_ctrl_is_load_0 = dis_uops_0_ctrl_is_load;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_0_bits_ctrl_is_sta_0 = dis_uops_0_ctrl_is_sta;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_0_bits_ctrl_is_std_0 = dis_uops_0_ctrl_is_std;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_0_bits_iw_state_0 = dis_uops_0_iw_state;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_0_bits_iw_p1_poisoned_0 = dis_uops_0_iw_p1_poisoned;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_0_bits_iw_p2_poisoned_0 = dis_uops_0_iw_p2_poisoned;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_0_bits_is_br_0 = dis_uops_0_is_br;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_0_bits_is_jalr_0 = dis_uops_0_is_jalr;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_0_bits_is_jal_0 = dis_uops_0_is_jal;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_0_bits_is_sfb_0 = dis_uops_0_is_sfb;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_0_bits_br_mask_0 = dis_uops_0_br_mask;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_0_bits_br_tag_0 = dis_uops_0_br_tag;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_0_bits_ftq_idx_0 = dis_uops_0_ftq_idx;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_0_bits_edge_inst_0 = dis_uops_0_edge_inst;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_0_bits_pc_lob_0 = dis_uops_0_pc_lob;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_0_bits_taken_0 = dis_uops_0_taken;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_0_bits_imm_packed_0 = dis_uops_0_imm_packed;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_0_bits_csr_addr_0 = dis_uops_0_csr_addr;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_0_bits_rob_idx_0 = dis_uops_0_rob_idx;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_0_bits_ldq_idx_0 = dis_uops_0_ldq_idx;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_0_bits_stq_idx_0 = dis_uops_0_stq_idx;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_0_bits_rxq_idx_0 = dis_uops_0_rxq_idx;\t// @[core.scala:51:7, :167:24]\n wire [6:0] _dis_uops_0_pdst_T_3;\t// @[core.scala:659:28]\n assign io_lsu_dis_uops_0_bits_pdst_0 = dis_uops_0_pdst;\t// @[core.scala:51:7, :167:24]\n wire [6:0] _dis_uops_0_prs1_T_3;\t// @[core.scala:654:28]\n assign io_lsu_dis_uops_0_bits_prs1_0 = dis_uops_0_prs1;\t// @[core.scala:51:7, :167:24]\n wire [6:0] _dis_uops_0_prs2_T_1;\t// @[core.scala:656:28]\n assign io_lsu_dis_uops_0_bits_prs2_0 = dis_uops_0_prs2;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_0_bits_prs3_0 = dis_uops_0_prs3;\t// @[core.scala:51:7, :167:24]\n wire _dis_uops_0_prs1_busy_T_4;\t// @[core.scala:664:85]\n assign io_lsu_dis_uops_0_bits_prs1_busy_0 = dis_uops_0_prs1_busy;\t// @[core.scala:51:7, :167:24]\n wire _dis_uops_0_prs2_busy_T_4;\t// @[core.scala:666:85]\n assign io_lsu_dis_uops_0_bits_prs2_busy_0 = dis_uops_0_prs2_busy;\t// @[core.scala:51:7, :167:24]\n wire _dis_uops_0_prs3_busy_T;\t// @[core.scala:668:46]\n assign io_lsu_dis_uops_0_bits_prs3_busy_0 = dis_uops_0_prs3_busy;\t// @[core.scala:51:7, :167:24]\n wire [6:0] _dis_uops_0_stale_pdst_T_1;\t// @[core.scala:662:34]\n assign io_lsu_dis_uops_0_bits_stale_pdst_0 = dis_uops_0_stale_pdst;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_0_bits_exception_0 = dis_uops_0_exception;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_0_bits_exc_cause_0 = dis_uops_0_exc_cause;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_0_bits_bypassable_0 = dis_uops_0_bypassable;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_0_bits_mem_cmd_0 = dis_uops_0_mem_cmd;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_0_bits_mem_size_0 = dis_uops_0_mem_size;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_0_bits_mem_signed_0 = dis_uops_0_mem_signed;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_0_bits_is_fence_0 = dis_uops_0_is_fence;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_0_bits_is_fencei_0 = dis_uops_0_is_fencei;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_0_bits_is_amo_0 = dis_uops_0_is_amo;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_0_bits_uses_ldq_0 = dis_uops_0_uses_ldq;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_0_bits_uses_stq_0 = dis_uops_0_uses_stq;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_0_bits_is_sys_pc2epc_0 = dis_uops_0_is_sys_pc2epc;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_0_bits_is_unique_0 = dis_uops_0_is_unique;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_0_bits_flush_on_commit_0 = dis_uops_0_flush_on_commit;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_0_bits_ldst_is_rs1_0 = dis_uops_0_ldst_is_rs1;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_0_bits_ldst_0 = dis_uops_0_ldst;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_0_bits_lrs1_0 = dis_uops_0_lrs1;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_0_bits_lrs2_0 = dis_uops_0_lrs2;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_0_bits_lrs3_0 = dis_uops_0_lrs3;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_0_bits_ldst_val_0 = dis_uops_0_ldst_val;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_0_bits_dst_rtype_0 = dis_uops_0_dst_rtype;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_0_bits_lrs1_rtype_0 = dis_uops_0_lrs1_rtype;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_0_bits_lrs2_rtype_0 = dis_uops_0_lrs2_rtype;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_0_bits_frs3_en_0 = dis_uops_0_frs3_en;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_0_bits_fp_val_0 = dis_uops_0_fp_val;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_0_bits_fp_single_0 = dis_uops_0_fp_single;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_0_bits_xcpt_pf_if_0 = dis_uops_0_xcpt_pf_if;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_0_bits_xcpt_ae_if_0 = dis_uops_0_xcpt_ae_if;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_0_bits_xcpt_ma_if_0 = dis_uops_0_xcpt_ma_if;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_0_bits_bp_debug_if_0 = dis_uops_0_bp_debug_if;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_0_bits_bp_xcpt_if_0 = dis_uops_0_bp_xcpt_if;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_0_bits_debug_fsrc_0 = dis_uops_0_debug_fsrc;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_0_bits_debug_tsrc_0 = dis_uops_0_debug_tsrc;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_1_bits_uopc_0 = dis_uops_1_uopc;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_1_bits_inst_0 = dis_uops_1_inst;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_1_bits_debug_inst_0 = dis_uops_1_debug_inst;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_1_bits_is_rvc_0 = dis_uops_1_is_rvc;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_1_bits_debug_pc_0 = dis_uops_1_debug_pc;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_1_bits_iq_type_0 = dis_uops_1_iq_type;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_1_bits_fu_code_0 = dis_uops_1_fu_code;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_1_bits_ctrl_br_type_0 = dis_uops_1_ctrl_br_type;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_1_bits_ctrl_op1_sel_0 = dis_uops_1_ctrl_op1_sel;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_1_bits_ctrl_op2_sel_0 = dis_uops_1_ctrl_op2_sel;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_1_bits_ctrl_imm_sel_0 = dis_uops_1_ctrl_imm_sel;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_1_bits_ctrl_op_fcn_0 = dis_uops_1_ctrl_op_fcn;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_1_bits_ctrl_fcn_dw_0 = dis_uops_1_ctrl_fcn_dw;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_1_bits_ctrl_csr_cmd_0 = dis_uops_1_ctrl_csr_cmd;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_1_bits_ctrl_is_load_0 = dis_uops_1_ctrl_is_load;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_1_bits_ctrl_is_sta_0 = dis_uops_1_ctrl_is_sta;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_1_bits_ctrl_is_std_0 = dis_uops_1_ctrl_is_std;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_1_bits_iw_state_0 = dis_uops_1_iw_state;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_1_bits_iw_p1_poisoned_0 = dis_uops_1_iw_p1_poisoned;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_1_bits_iw_p2_poisoned_0 = dis_uops_1_iw_p2_poisoned;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_1_bits_is_br_0 = dis_uops_1_is_br;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_1_bits_is_jalr_0 = dis_uops_1_is_jalr;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_1_bits_is_jal_0 = dis_uops_1_is_jal;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_1_bits_is_sfb_0 = dis_uops_1_is_sfb;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_1_bits_br_mask_0 = dis_uops_1_br_mask;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_1_bits_br_tag_0 = dis_uops_1_br_tag;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_1_bits_ftq_idx_0 = dis_uops_1_ftq_idx;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_1_bits_edge_inst_0 = dis_uops_1_edge_inst;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_1_bits_pc_lob_0 = dis_uops_1_pc_lob;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_1_bits_taken_0 = dis_uops_1_taken;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_1_bits_imm_packed_0 = dis_uops_1_imm_packed;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_1_bits_csr_addr_0 = dis_uops_1_csr_addr;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_1_bits_rob_idx_0 = dis_uops_1_rob_idx;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_1_bits_ldq_idx_0 = dis_uops_1_ldq_idx;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_1_bits_stq_idx_0 = dis_uops_1_stq_idx;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_1_bits_rxq_idx_0 = dis_uops_1_rxq_idx;\t// @[core.scala:51:7, :167:24]\n wire [6:0] _dis_uops_1_pdst_T_3;\t// @[core.scala:659:28]\n assign io_lsu_dis_uops_1_bits_pdst_0 = dis_uops_1_pdst;\t// @[core.scala:51:7, :167:24]\n wire [6:0] _dis_uops_1_prs1_T_3;\t// @[core.scala:654:28]\n assign io_lsu_dis_uops_1_bits_prs1_0 = dis_uops_1_prs1;\t// @[core.scala:51:7, :167:24]\n wire [6:0] _dis_uops_1_prs2_T_1;\t// @[core.scala:656:28]\n assign io_lsu_dis_uops_1_bits_prs2_0 = dis_uops_1_prs2;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_1_bits_prs3_0 = dis_uops_1_prs3;\t// @[core.scala:51:7, :167:24]\n wire _dis_uops_1_prs1_busy_T_4;\t// @[core.scala:664:85]\n assign io_lsu_dis_uops_1_bits_prs1_busy_0 = dis_uops_1_prs1_busy;\t// @[core.scala:51:7, :167:24]\n wire _dis_uops_1_prs2_busy_T_4;\t// @[core.scala:666:85]\n assign io_lsu_dis_uops_1_bits_prs2_busy_0 = dis_uops_1_prs2_busy;\t// @[core.scala:51:7, :167:24]\n wire _dis_uops_1_prs3_busy_T;\t// @[core.scala:668:46]\n assign io_lsu_dis_uops_1_bits_prs3_busy_0 = dis_uops_1_prs3_busy;\t// @[core.scala:51:7, :167:24]\n wire [6:0] _dis_uops_1_stale_pdst_T_1;\t// @[core.scala:662:34]\n assign io_lsu_dis_uops_1_bits_stale_pdst_0 = dis_uops_1_stale_pdst;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_1_bits_exception_0 = dis_uops_1_exception;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_1_bits_exc_cause_0 = dis_uops_1_exc_cause;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_1_bits_bypassable_0 = dis_uops_1_bypassable;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_1_bits_mem_cmd_0 = dis_uops_1_mem_cmd;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_1_bits_mem_size_0 = dis_uops_1_mem_size;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_1_bits_mem_signed_0 = dis_uops_1_mem_signed;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_1_bits_is_fence_0 = dis_uops_1_is_fence;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_1_bits_is_fencei_0 = dis_uops_1_is_fencei;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_1_bits_is_amo_0 = dis_uops_1_is_amo;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_1_bits_uses_ldq_0 = dis_uops_1_uses_ldq;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_1_bits_uses_stq_0 = dis_uops_1_uses_stq;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_1_bits_is_sys_pc2epc_0 = dis_uops_1_is_sys_pc2epc;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_1_bits_is_unique_0 = dis_uops_1_is_unique;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_1_bits_flush_on_commit_0 = dis_uops_1_flush_on_commit;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_1_bits_ldst_is_rs1_0 = dis_uops_1_ldst_is_rs1;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_1_bits_ldst_0 = dis_uops_1_ldst;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_1_bits_lrs1_0 = dis_uops_1_lrs1;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_1_bits_lrs2_0 = dis_uops_1_lrs2;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_1_bits_lrs3_0 = dis_uops_1_lrs3;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_1_bits_ldst_val_0 = dis_uops_1_ldst_val;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_1_bits_dst_rtype_0 = dis_uops_1_dst_rtype;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_1_bits_lrs1_rtype_0 = dis_uops_1_lrs1_rtype;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_1_bits_lrs2_rtype_0 = dis_uops_1_lrs2_rtype;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_1_bits_frs3_en_0 = dis_uops_1_frs3_en;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_1_bits_fp_val_0 = dis_uops_1_fp_val;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_1_bits_fp_single_0 = dis_uops_1_fp_single;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_1_bits_xcpt_pf_if_0 = dis_uops_1_xcpt_pf_if;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_1_bits_xcpt_ae_if_0 = dis_uops_1_xcpt_ae_if;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_1_bits_xcpt_ma_if_0 = dis_uops_1_xcpt_ma_if;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_1_bits_bp_debug_if_0 = dis_uops_1_bp_debug_if;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_1_bits_bp_xcpt_if_0 = dis_uops_1_bp_xcpt_if;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_1_bits_debug_fsrc_0 = dis_uops_1_debug_fsrc;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_1_bits_debug_tsrc_0 = dis_uops_1_debug_tsrc;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_2_bits_uopc_0 = dis_uops_2_uopc;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_2_bits_inst_0 = dis_uops_2_inst;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_2_bits_debug_inst_0 = dis_uops_2_debug_inst;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_2_bits_is_rvc_0 = dis_uops_2_is_rvc;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_2_bits_debug_pc_0 = dis_uops_2_debug_pc;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_2_bits_iq_type_0 = dis_uops_2_iq_type;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_2_bits_fu_code_0 = dis_uops_2_fu_code;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_2_bits_ctrl_br_type_0 = dis_uops_2_ctrl_br_type;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_2_bits_ctrl_op1_sel_0 = dis_uops_2_ctrl_op1_sel;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_2_bits_ctrl_op2_sel_0 = dis_uops_2_ctrl_op2_sel;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_2_bits_ctrl_imm_sel_0 = dis_uops_2_ctrl_imm_sel;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_2_bits_ctrl_op_fcn_0 = dis_uops_2_ctrl_op_fcn;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_2_bits_ctrl_fcn_dw_0 = dis_uops_2_ctrl_fcn_dw;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_2_bits_ctrl_csr_cmd_0 = dis_uops_2_ctrl_csr_cmd;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_2_bits_ctrl_is_load_0 = dis_uops_2_ctrl_is_load;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_2_bits_ctrl_is_sta_0 = dis_uops_2_ctrl_is_sta;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_2_bits_ctrl_is_std_0 = dis_uops_2_ctrl_is_std;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_2_bits_iw_state_0 = dis_uops_2_iw_state;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_2_bits_iw_p1_poisoned_0 = dis_uops_2_iw_p1_poisoned;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_2_bits_iw_p2_poisoned_0 = dis_uops_2_iw_p2_poisoned;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_2_bits_is_br_0 = dis_uops_2_is_br;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_2_bits_is_jalr_0 = dis_uops_2_is_jalr;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_2_bits_is_jal_0 = dis_uops_2_is_jal;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_2_bits_is_sfb_0 = dis_uops_2_is_sfb;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_2_bits_br_mask_0 = dis_uops_2_br_mask;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_2_bits_br_tag_0 = dis_uops_2_br_tag;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_2_bits_ftq_idx_0 = dis_uops_2_ftq_idx;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_2_bits_edge_inst_0 = dis_uops_2_edge_inst;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_2_bits_pc_lob_0 = dis_uops_2_pc_lob;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_2_bits_taken_0 = dis_uops_2_taken;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_2_bits_imm_packed_0 = dis_uops_2_imm_packed;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_2_bits_csr_addr_0 = dis_uops_2_csr_addr;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_2_bits_rob_idx_0 = dis_uops_2_rob_idx;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_2_bits_ldq_idx_0 = dis_uops_2_ldq_idx;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_2_bits_stq_idx_0 = dis_uops_2_stq_idx;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_2_bits_rxq_idx_0 = dis_uops_2_rxq_idx;\t// @[core.scala:51:7, :167:24]\n wire [6:0] _dis_uops_2_pdst_T_3;\t// @[core.scala:659:28]\n assign io_lsu_dis_uops_2_bits_pdst_0 = dis_uops_2_pdst;\t// @[core.scala:51:7, :167:24]\n wire [6:0] _dis_uops_2_prs1_T_3;\t// @[core.scala:654:28]\n assign io_lsu_dis_uops_2_bits_prs1_0 = dis_uops_2_prs1;\t// @[core.scala:51:7, :167:24]\n wire [6:0] _dis_uops_2_prs2_T_1;\t// @[core.scala:656:28]\n assign io_lsu_dis_uops_2_bits_prs2_0 = dis_uops_2_prs2;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_2_bits_prs3_0 = dis_uops_2_prs3;\t// @[core.scala:51:7, :167:24]\n wire _dis_uops_2_prs1_busy_T_4;\t// @[core.scala:664:85]\n assign io_lsu_dis_uops_2_bits_prs1_busy_0 = dis_uops_2_prs1_busy;\t// @[core.scala:51:7, :167:24]\n wire _dis_uops_2_prs2_busy_T_4;\t// @[core.scala:666:85]\n assign io_lsu_dis_uops_2_bits_prs2_busy_0 = dis_uops_2_prs2_busy;\t// @[core.scala:51:7, :167:24]\n wire _dis_uops_2_prs3_busy_T;\t// @[core.scala:668:46]\n assign io_lsu_dis_uops_2_bits_prs3_busy_0 = dis_uops_2_prs3_busy;\t// @[core.scala:51:7, :167:24]\n wire [6:0] _dis_uops_2_stale_pdst_T_1;\t// @[core.scala:662:34]\n assign io_lsu_dis_uops_2_bits_stale_pdst_0 = dis_uops_2_stale_pdst;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_2_bits_exception_0 = dis_uops_2_exception;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_2_bits_exc_cause_0 = dis_uops_2_exc_cause;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_2_bits_bypassable_0 = dis_uops_2_bypassable;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_2_bits_mem_cmd_0 = dis_uops_2_mem_cmd;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_2_bits_mem_size_0 = dis_uops_2_mem_size;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_2_bits_mem_signed_0 = dis_uops_2_mem_signed;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_2_bits_is_fence_0 = dis_uops_2_is_fence;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_2_bits_is_fencei_0 = dis_uops_2_is_fencei;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_2_bits_is_amo_0 = dis_uops_2_is_amo;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_2_bits_uses_ldq_0 = dis_uops_2_uses_ldq;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_2_bits_uses_stq_0 = dis_uops_2_uses_stq;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_2_bits_is_sys_pc2epc_0 = dis_uops_2_is_sys_pc2epc;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_2_bits_is_unique_0 = dis_uops_2_is_unique;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_2_bits_flush_on_commit_0 = dis_uops_2_flush_on_commit;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_2_bits_ldst_is_rs1_0 = dis_uops_2_ldst_is_rs1;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_2_bits_ldst_0 = dis_uops_2_ldst;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_2_bits_lrs1_0 = dis_uops_2_lrs1;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_2_bits_lrs2_0 = dis_uops_2_lrs2;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_2_bits_lrs3_0 = dis_uops_2_lrs3;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_2_bits_ldst_val_0 = dis_uops_2_ldst_val;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_2_bits_dst_rtype_0 = dis_uops_2_dst_rtype;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_2_bits_lrs1_rtype_0 = dis_uops_2_lrs1_rtype;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_2_bits_lrs2_rtype_0 = dis_uops_2_lrs2_rtype;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_2_bits_frs3_en_0 = dis_uops_2_frs3_en;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_2_bits_fp_val_0 = dis_uops_2_fp_val;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_2_bits_fp_single_0 = dis_uops_2_fp_single;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_2_bits_xcpt_pf_if_0 = dis_uops_2_xcpt_pf_if;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_2_bits_xcpt_ae_if_0 = dis_uops_2_xcpt_ae_if;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_2_bits_xcpt_ma_if_0 = dis_uops_2_xcpt_ma_if;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_2_bits_bp_debug_if_0 = dis_uops_2_bp_debug_if;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_2_bits_bp_xcpt_if_0 = dis_uops_2_bp_xcpt_if;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_2_bits_debug_fsrc_0 = dis_uops_2_debug_fsrc;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_2_bits_debug_tsrc_0 = dis_uops_2_debug_tsrc;\t// @[core.scala:51:7, :167:24]\n assign io_lsu_dis_uops_0_valid_0 = dis_fire_0;\t// @[core.scala:51:7, :168:24]\n assign io_lsu_dis_uops_1_valid_0 = dis_fire_1;\t// @[core.scala:51:7, :168:24]\n assign io_lsu_dis_uops_2_valid_0 = dis_fire_2;\t// @[core.scala:51:7, :168:24]\n wire _dis_ready_T;\t// @[core.scala:715:16]\n wire dis_ready;\t// @[core.scala:169:24]\n wire iss_valids_0;\t// @[core.scala:172:24]\n wire iss_valids_1;\t// @[core.scala:172:24]\n wire iss_valids_2;\t// @[core.scala:172:24]\n wire iss_valids_3;\t// @[core.scala:172:24]\n assign pred_wakeup_bits_uop_uopc = iss_uops_1_uopc;\t// @[core.scala:149:26, :173:24]\n assign fast_wakeup_bits_uop_uopc = iss_uops_1_uopc;\t// @[core.scala:173:24, :814:29]\n assign pred_wakeup_bits_uop_inst = iss_uops_1_inst;\t// @[core.scala:149:26, :173:24]\n assign fast_wakeup_bits_uop_inst = iss_uops_1_inst;\t// @[core.scala:173:24, :814:29]\n assign pred_wakeup_bits_uop_debug_inst = iss_uops_1_debug_inst;\t// @[core.scala:149:26, :173:24]\n assign fast_wakeup_bits_uop_debug_inst = iss_uops_1_debug_inst;\t// @[core.scala:173:24, :814:29]\n assign pred_wakeup_bits_uop_is_rvc = iss_uops_1_is_rvc;\t// @[core.scala:149:26, :173:24]\n assign fast_wakeup_bits_uop_is_rvc = iss_uops_1_is_rvc;\t// @[core.scala:173:24, :814:29]\n assign pred_wakeup_bits_uop_debug_pc = iss_uops_1_debug_pc;\t// @[core.scala:149:26, :173:24]\n assign fast_wakeup_bits_uop_debug_pc = iss_uops_1_debug_pc;\t// @[core.scala:173:24, :814:29]\n assign pred_wakeup_bits_uop_iq_type = iss_uops_1_iq_type;\t// @[core.scala:149:26, :173:24]\n assign fast_wakeup_bits_uop_iq_type = iss_uops_1_iq_type;\t// @[core.scala:173:24, :814:29]\n assign pred_wakeup_bits_uop_fu_code = iss_uops_1_fu_code;\t// @[core.scala:149:26, :173:24]\n assign fast_wakeup_bits_uop_fu_code = iss_uops_1_fu_code;\t// @[core.scala:173:24, :814:29]\n assign pred_wakeup_bits_uop_ctrl_br_type = iss_uops_1_ctrl_br_type;\t// @[core.scala:149:26, :173:24]\n assign fast_wakeup_bits_uop_ctrl_br_type = iss_uops_1_ctrl_br_type;\t// @[core.scala:173:24, :814:29]\n assign pred_wakeup_bits_uop_ctrl_op1_sel = iss_uops_1_ctrl_op1_sel;\t// @[core.scala:149:26, :173:24]\n assign fast_wakeup_bits_uop_ctrl_op1_sel = iss_uops_1_ctrl_op1_sel;\t// @[core.scala:173:24, :814:29]\n assign pred_wakeup_bits_uop_ctrl_op2_sel = iss_uops_1_ctrl_op2_sel;\t// @[core.scala:149:26, :173:24]\n assign fast_wakeup_bits_uop_ctrl_op2_sel = iss_uops_1_ctrl_op2_sel;\t// @[core.scala:173:24, :814:29]\n assign pred_wakeup_bits_uop_ctrl_imm_sel = iss_uops_1_ctrl_imm_sel;\t// @[core.scala:149:26, :173:24]\n assign fast_wakeup_bits_uop_ctrl_imm_sel = iss_uops_1_ctrl_imm_sel;\t// @[core.scala:173:24, :814:29]\n assign pred_wakeup_bits_uop_ctrl_op_fcn = iss_uops_1_ctrl_op_fcn;\t// @[core.scala:149:26, :173:24]\n assign fast_wakeup_bits_uop_ctrl_op_fcn = iss_uops_1_ctrl_op_fcn;\t// @[core.scala:173:24, :814:29]\n assign pred_wakeup_bits_uop_ctrl_fcn_dw = iss_uops_1_ctrl_fcn_dw;\t// @[core.scala:149:26, :173:24]\n assign fast_wakeup_bits_uop_ctrl_fcn_dw = iss_uops_1_ctrl_fcn_dw;\t// @[core.scala:173:24, :814:29]\n assign pred_wakeup_bits_uop_ctrl_csr_cmd = iss_uops_1_ctrl_csr_cmd;\t// @[core.scala:149:26, :173:24]\n assign fast_wakeup_bits_uop_ctrl_csr_cmd = iss_uops_1_ctrl_csr_cmd;\t// @[core.scala:173:24, :814:29]\n assign pred_wakeup_bits_uop_ctrl_is_load = iss_uops_1_ctrl_is_load;\t// @[core.scala:149:26, :173:24]\n assign fast_wakeup_bits_uop_ctrl_is_load = iss_uops_1_ctrl_is_load;\t// @[core.scala:173:24, :814:29]\n assign pred_wakeup_bits_uop_ctrl_is_sta = iss_uops_1_ctrl_is_sta;\t// @[core.scala:149:26, :173:24]\n assign fast_wakeup_bits_uop_ctrl_is_sta = iss_uops_1_ctrl_is_sta;\t// @[core.scala:173:24, :814:29]\n assign pred_wakeup_bits_uop_ctrl_is_std = iss_uops_1_ctrl_is_std;\t// @[core.scala:149:26, :173:24]\n assign fast_wakeup_bits_uop_ctrl_is_std = iss_uops_1_ctrl_is_std;\t// @[core.scala:173:24, :814:29]\n assign pred_wakeup_bits_uop_iw_state = iss_uops_1_iw_state;\t// @[core.scala:149:26, :173:24]\n assign fast_wakeup_bits_uop_iw_state = iss_uops_1_iw_state;\t// @[core.scala:173:24, :814:29]\n assign pred_wakeup_bits_uop_iw_p1_poisoned = iss_uops_1_iw_p1_poisoned;\t// @[core.scala:149:26, :173:24]\n assign fast_wakeup_bits_uop_iw_p1_poisoned = iss_uops_1_iw_p1_poisoned;\t// @[core.scala:173:24, :814:29]\n assign pred_wakeup_bits_uop_iw_p2_poisoned = iss_uops_1_iw_p2_poisoned;\t// @[core.scala:149:26, :173:24]\n assign fast_wakeup_bits_uop_iw_p2_poisoned = iss_uops_1_iw_p2_poisoned;\t// @[core.scala:173:24, :814:29]\n assign pred_wakeup_bits_uop_is_br = iss_uops_1_is_br;\t// @[core.scala:149:26, :173:24]\n assign fast_wakeup_bits_uop_is_br = iss_uops_1_is_br;\t// @[core.scala:173:24, :814:29]\n assign pred_wakeup_bits_uop_is_jalr = iss_uops_1_is_jalr;\t// @[core.scala:149:26, :173:24]\n assign fast_wakeup_bits_uop_is_jalr = iss_uops_1_is_jalr;\t// @[core.scala:173:24, :814:29]\n assign pred_wakeup_bits_uop_is_jal = iss_uops_1_is_jal;\t// @[core.scala:149:26, :173:24]\n assign fast_wakeup_bits_uop_is_jal = iss_uops_1_is_jal;\t// @[core.scala:173:24, :814:29]\n assign pred_wakeup_bits_uop_is_sfb = iss_uops_1_is_sfb;\t// @[core.scala:149:26, :173:24]\n assign fast_wakeup_bits_uop_is_sfb = iss_uops_1_is_sfb;\t// @[core.scala:173:24, :814:29]\n assign pred_wakeup_bits_uop_br_mask = iss_uops_1_br_mask;\t// @[core.scala:149:26, :173:24]\n assign fast_wakeup_bits_uop_br_mask = iss_uops_1_br_mask;\t// @[core.scala:173:24, :814:29]\n assign pred_wakeup_bits_uop_br_tag = iss_uops_1_br_tag;\t// @[core.scala:149:26, :173:24]\n assign fast_wakeup_bits_uop_br_tag = iss_uops_1_br_tag;\t// @[core.scala:173:24, :814:29]\n assign pred_wakeup_bits_uop_ftq_idx = iss_uops_1_ftq_idx;\t// @[core.scala:149:26, :173:24]\n assign fast_wakeup_bits_uop_ftq_idx = iss_uops_1_ftq_idx;\t// @[core.scala:173:24, :814:29]\n assign pred_wakeup_bits_uop_edge_inst = iss_uops_1_edge_inst;\t// @[core.scala:149:26, :173:24]\n assign fast_wakeup_bits_uop_edge_inst = iss_uops_1_edge_inst;\t// @[core.scala:173:24, :814:29]\n assign pred_wakeup_bits_uop_pc_lob = iss_uops_1_pc_lob;\t// @[core.scala:149:26, :173:24]\n assign fast_wakeup_bits_uop_pc_lob = iss_uops_1_pc_lob;\t// @[core.scala:173:24, :814:29]\n assign pred_wakeup_bits_uop_taken = iss_uops_1_taken;\t// @[core.scala:149:26, :173:24]\n assign fast_wakeup_bits_uop_taken = iss_uops_1_taken;\t// @[core.scala:173:24, :814:29]\n assign pred_wakeup_bits_uop_imm_packed = iss_uops_1_imm_packed;\t// @[core.scala:149:26, :173:24]\n assign fast_wakeup_bits_uop_imm_packed = iss_uops_1_imm_packed;\t// @[core.scala:173:24, :814:29]\n assign pred_wakeup_bits_uop_csr_addr = iss_uops_1_csr_addr;\t// @[core.scala:149:26, :173:24]\n assign fast_wakeup_bits_uop_csr_addr = iss_uops_1_csr_addr;\t// @[core.scala:173:24, :814:29]\n assign pred_wakeup_bits_uop_rob_idx = iss_uops_1_rob_idx;\t// @[core.scala:149:26, :173:24]\n assign fast_wakeup_bits_uop_rob_idx = iss_uops_1_rob_idx;\t// @[core.scala:173:24, :814:29]\n assign pred_wakeup_bits_uop_ldq_idx = iss_uops_1_ldq_idx;\t// @[core.scala:149:26, :173:24]\n assign fast_wakeup_bits_uop_ldq_idx = iss_uops_1_ldq_idx;\t// @[core.scala:173:24, :814:29]\n assign pred_wakeup_bits_uop_stq_idx = iss_uops_1_stq_idx;\t// @[core.scala:149:26, :173:24]\n assign fast_wakeup_bits_uop_stq_idx = iss_uops_1_stq_idx;\t// @[core.scala:173:24, :814:29]\n assign pred_wakeup_bits_uop_rxq_idx = iss_uops_1_rxq_idx;\t// @[core.scala:149:26, :173:24]\n assign fast_wakeup_bits_uop_rxq_idx = iss_uops_1_rxq_idx;\t// @[core.scala:173:24, :814:29]\n assign pred_wakeup_bits_uop_pdst = iss_uops_1_pdst;\t// @[core.scala:149:26, :173:24]\n assign fast_wakeup_bits_uop_pdst = iss_uops_1_pdst;\t// @[core.scala:173:24, :814:29]\n assign pred_wakeup_bits_uop_prs1 = iss_uops_1_prs1;\t// @[core.scala:149:26, :173:24]\n assign fast_wakeup_bits_uop_prs1 = iss_uops_1_prs1;\t// @[core.scala:173:24, :814:29]\n assign pred_wakeup_bits_uop_prs2 = iss_uops_1_prs2;\t// @[core.scala:149:26, :173:24]\n assign fast_wakeup_bits_uop_prs2 = iss_uops_1_prs2;\t// @[core.scala:173:24, :814:29]\n assign pred_wakeup_bits_uop_prs3 = iss_uops_1_prs3;\t// @[core.scala:149:26, :173:24]\n assign fast_wakeup_bits_uop_prs3 = iss_uops_1_prs3;\t// @[core.scala:173:24, :814:29]\n assign pred_wakeup_bits_uop_ppred = iss_uops_1_ppred;\t// @[core.scala:149:26, :173:24]\n assign fast_wakeup_bits_uop_ppred = iss_uops_1_ppred;\t// @[core.scala:173:24, :814:29]\n assign pred_wakeup_bits_uop_prs1_busy = iss_uops_1_prs1_busy;\t// @[core.scala:149:26, :173:24]\n assign fast_wakeup_bits_uop_prs1_busy = iss_uops_1_prs1_busy;\t// @[core.scala:173:24, :814:29]\n assign pred_wakeup_bits_uop_prs2_busy = iss_uops_1_prs2_busy;\t// @[core.scala:149:26, :173:24]\n assign fast_wakeup_bits_uop_prs2_busy = iss_uops_1_prs2_busy;\t// @[core.scala:173:24, :814:29]\n assign pred_wakeup_bits_uop_prs3_busy = iss_uops_1_prs3_busy;\t// @[core.scala:149:26, :173:24]\n assign fast_wakeup_bits_uop_prs3_busy = iss_uops_1_prs3_busy;\t// @[core.scala:173:24, :814:29]\n assign pred_wakeup_bits_uop_ppred_busy = iss_uops_1_ppred_busy;\t// @[core.scala:149:26, :173:24]\n assign fast_wakeup_bits_uop_ppred_busy = iss_uops_1_ppred_busy;\t// @[core.scala:173:24, :814:29]\n assign pred_wakeup_bits_uop_stale_pdst = iss_uops_1_stale_pdst;\t// @[core.scala:149:26, :173:24]\n assign fast_wakeup_bits_uop_stale_pdst = iss_uops_1_stale_pdst;\t// @[core.scala:173:24, :814:29]\n assign pred_wakeup_bits_uop_exception = iss_uops_1_exception;\t// @[core.scala:149:26, :173:24]\n assign fast_wakeup_bits_uop_exception = iss_uops_1_exception;\t// @[core.scala:173:24, :814:29]\n assign pred_wakeup_bits_uop_exc_cause = iss_uops_1_exc_cause;\t// @[core.scala:149:26, :173:24]\n assign fast_wakeup_bits_uop_exc_cause = iss_uops_1_exc_cause;\t// @[core.scala:173:24, :814:29]\n assign pred_wakeup_bits_uop_bypassable = iss_uops_1_bypassable;\t// @[core.scala:149:26, :173:24]\n assign fast_wakeup_bits_uop_bypassable = iss_uops_1_bypassable;\t// @[core.scala:173:24, :814:29]\n assign pred_wakeup_bits_uop_mem_cmd = iss_uops_1_mem_cmd;\t// @[core.scala:149:26, :173:24]\n assign fast_wakeup_bits_uop_mem_cmd = iss_uops_1_mem_cmd;\t// @[core.scala:173:24, :814:29]\n assign pred_wakeup_bits_uop_mem_size = iss_uops_1_mem_size;\t// @[core.scala:149:26, :173:24]\n assign fast_wakeup_bits_uop_mem_size = iss_uops_1_mem_size;\t// @[core.scala:173:24, :814:29]\n assign pred_wakeup_bits_uop_mem_signed = iss_uops_1_mem_signed;\t// @[core.scala:149:26, :173:24]\n assign fast_wakeup_bits_uop_mem_signed = iss_uops_1_mem_signed;\t// @[core.scala:173:24, :814:29]\n assign pred_wakeup_bits_uop_is_fence = iss_uops_1_is_fence;\t// @[core.scala:149:26, :173:24]\n assign fast_wakeup_bits_uop_is_fence = iss_uops_1_is_fence;\t// @[core.scala:173:24, :814:29]\n assign pred_wakeup_bits_uop_is_fencei = iss_uops_1_is_fencei;\t// @[core.scala:149:26, :173:24]\n assign fast_wakeup_bits_uop_is_fencei = iss_uops_1_is_fencei;\t// @[core.scala:173:24, :814:29]\n assign pred_wakeup_bits_uop_is_amo = iss_uops_1_is_amo;\t// @[core.scala:149:26, :173:24]\n assign fast_wakeup_bits_uop_is_amo = iss_uops_1_is_amo;\t// @[core.scala:173:24, :814:29]\n assign pred_wakeup_bits_uop_uses_ldq = iss_uops_1_uses_ldq;\t// @[core.scala:149:26, :173:24]\n assign fast_wakeup_bits_uop_uses_ldq = iss_uops_1_uses_ldq;\t// @[core.scala:173:24, :814:29]\n assign pred_wakeup_bits_uop_uses_stq = iss_uops_1_uses_stq;\t// @[core.scala:149:26, :173:24]\n assign fast_wakeup_bits_uop_uses_stq = iss_uops_1_uses_stq;\t// @[core.scala:173:24, :814:29]\n assign pred_wakeup_bits_uop_is_sys_pc2epc = iss_uops_1_is_sys_pc2epc;\t// @[core.scala:149:26, :173:24]\n assign fast_wakeup_bits_uop_is_sys_pc2epc = iss_uops_1_is_sys_pc2epc;\t// @[core.scala:173:24, :814:29]\n assign pred_wakeup_bits_uop_is_unique = iss_uops_1_is_unique;\t// @[core.scala:149:26, :173:24]\n assign fast_wakeup_bits_uop_is_unique = iss_uops_1_is_unique;\t// @[core.scala:173:24, :814:29]\n assign pred_wakeup_bits_uop_flush_on_commit = iss_uops_1_flush_on_commit;\t// @[core.scala:149:26, :173:24]\n assign fast_wakeup_bits_uop_flush_on_commit = iss_uops_1_flush_on_commit;\t// @[core.scala:173:24, :814:29]\n assign pred_wakeup_bits_uop_ldst_is_rs1 = iss_uops_1_ldst_is_rs1;\t// @[core.scala:149:26, :173:24]\n assign fast_wakeup_bits_uop_ldst_is_rs1 = iss_uops_1_ldst_is_rs1;\t// @[core.scala:173:24, :814:29]\n assign pred_wakeup_bits_uop_ldst = iss_uops_1_ldst;\t// @[core.scala:149:26, :173:24]\n assign fast_wakeup_bits_uop_ldst = iss_uops_1_ldst;\t// @[core.scala:173:24, :814:29]\n assign pred_wakeup_bits_uop_lrs1 = iss_uops_1_lrs1;\t// @[core.scala:149:26, :173:24]\n assign fast_wakeup_bits_uop_lrs1 = iss_uops_1_lrs1;\t// @[core.scala:173:24, :814:29]\n assign pred_wakeup_bits_uop_lrs2 = iss_uops_1_lrs2;\t// @[core.scala:149:26, :173:24]\n assign fast_wakeup_bits_uop_lrs2 = iss_uops_1_lrs2;\t// @[core.scala:173:24, :814:29]\n assign pred_wakeup_bits_uop_lrs3 = iss_uops_1_lrs3;\t// @[core.scala:149:26, :173:24]\n assign fast_wakeup_bits_uop_lrs3 = iss_uops_1_lrs3;\t// @[core.scala:173:24, :814:29]\n assign pred_wakeup_bits_uop_ldst_val = iss_uops_1_ldst_val;\t// @[core.scala:149:26, :173:24]\n assign fast_wakeup_bits_uop_ldst_val = iss_uops_1_ldst_val;\t// @[core.scala:173:24, :814:29]\n assign pred_wakeup_bits_uop_dst_rtype = iss_uops_1_dst_rtype;\t// @[core.scala:149:26, :173:24]\n assign fast_wakeup_bits_uop_dst_rtype = iss_uops_1_dst_rtype;\t// @[core.scala:173:24, :814:29]\n assign pred_wakeup_bits_uop_lrs1_rtype = iss_uops_1_lrs1_rtype;\t// @[core.scala:149:26, :173:24]\n assign fast_wakeup_bits_uop_lrs1_rtype = iss_uops_1_lrs1_rtype;\t// @[core.scala:173:24, :814:29]\n assign pred_wakeup_bits_uop_lrs2_rtype = iss_uops_1_lrs2_rtype;\t// @[core.scala:149:26, :173:24]\n assign fast_wakeup_bits_uop_lrs2_rtype = iss_uops_1_lrs2_rtype;\t// @[core.scala:173:24, :814:29]\n assign pred_wakeup_bits_uop_frs3_en = iss_uops_1_frs3_en;\t// @[core.scala:149:26, :173:24]\n assign fast_wakeup_bits_uop_frs3_en = iss_uops_1_frs3_en;\t// @[core.scala:173:24, :814:29]\n assign pred_wakeup_bits_uop_fp_val = iss_uops_1_fp_val;\t// @[core.scala:149:26, :173:24]\n assign fast_wakeup_bits_uop_fp_val = iss_uops_1_fp_val;\t// @[core.scala:173:24, :814:29]\n assign pred_wakeup_bits_uop_fp_single = iss_uops_1_fp_single;\t// @[core.scala:149:26, :173:24]\n assign fast_wakeup_bits_uop_fp_single = iss_uops_1_fp_single;\t// @[core.scala:173:24, :814:29]\n assign pred_wakeup_bits_uop_xcpt_pf_if = iss_uops_1_xcpt_pf_if;\t// @[core.scala:149:26, :173:24]\n assign fast_wakeup_bits_uop_xcpt_pf_if = iss_uops_1_xcpt_pf_if;\t// @[core.scala:173:24, :814:29]\n assign pred_wakeup_bits_uop_xcpt_ae_if = iss_uops_1_xcpt_ae_if;\t// @[core.scala:149:26, :173:24]\n assign fast_wakeup_bits_uop_xcpt_ae_if = iss_uops_1_xcpt_ae_if;\t// @[core.scala:173:24, :814:29]\n assign pred_wakeup_bits_uop_xcpt_ma_if = iss_uops_1_xcpt_ma_if;\t// @[core.scala:149:26, :173:24]\n assign fast_wakeup_bits_uop_xcpt_ma_if = iss_uops_1_xcpt_ma_if;\t// @[core.scala:173:24, :814:29]\n assign pred_wakeup_bits_uop_bp_debug_if = iss_uops_1_bp_debug_if;\t// @[core.scala:149:26, :173:24]\n assign fast_wakeup_bits_uop_bp_debug_if = iss_uops_1_bp_debug_if;\t// @[core.scala:173:24, :814:29]\n assign pred_wakeup_bits_uop_bp_xcpt_if = iss_uops_1_bp_xcpt_if;\t// @[core.scala:149:26, :173:24]\n assign fast_wakeup_bits_uop_bp_xcpt_if = iss_uops_1_bp_xcpt_if;\t// @[core.scala:173:24, :814:29]\n assign pred_wakeup_bits_uop_debug_fsrc = iss_uops_1_debug_fsrc;\t// @[core.scala:149:26, :173:24]\n assign fast_wakeup_bits_uop_debug_fsrc = iss_uops_1_debug_fsrc;\t// @[core.scala:173:24, :814:29]\n assign pred_wakeup_bits_uop_debug_tsrc = iss_uops_1_debug_tsrc;\t// @[core.scala:149:26, :173:24]\n assign fast_wakeup_bits_uop_debug_tsrc = iss_uops_1_debug_tsrc;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_1_bits_uop_uopc = iss_uops_2_uopc;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_1_bits_uop_inst = iss_uops_2_inst;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_1_bits_uop_debug_inst = iss_uops_2_debug_inst;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_1_bits_uop_is_rvc = iss_uops_2_is_rvc;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_1_bits_uop_debug_pc = iss_uops_2_debug_pc;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_1_bits_uop_iq_type = iss_uops_2_iq_type;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_1_bits_uop_fu_code = iss_uops_2_fu_code;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_1_bits_uop_ctrl_br_type = iss_uops_2_ctrl_br_type;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_1_bits_uop_ctrl_op1_sel = iss_uops_2_ctrl_op1_sel;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_1_bits_uop_ctrl_op2_sel = iss_uops_2_ctrl_op2_sel;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_1_bits_uop_ctrl_imm_sel = iss_uops_2_ctrl_imm_sel;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_1_bits_uop_ctrl_op_fcn = iss_uops_2_ctrl_op_fcn;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_1_bits_uop_ctrl_fcn_dw = iss_uops_2_ctrl_fcn_dw;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_1_bits_uop_ctrl_csr_cmd = iss_uops_2_ctrl_csr_cmd;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_1_bits_uop_ctrl_is_load = iss_uops_2_ctrl_is_load;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_1_bits_uop_ctrl_is_sta = iss_uops_2_ctrl_is_sta;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_1_bits_uop_ctrl_is_std = iss_uops_2_ctrl_is_std;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_1_bits_uop_iw_state = iss_uops_2_iw_state;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_1_bits_uop_iw_p1_poisoned = iss_uops_2_iw_p1_poisoned;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_1_bits_uop_iw_p2_poisoned = iss_uops_2_iw_p2_poisoned;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_1_bits_uop_is_br = iss_uops_2_is_br;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_1_bits_uop_is_jalr = iss_uops_2_is_jalr;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_1_bits_uop_is_jal = iss_uops_2_is_jal;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_1_bits_uop_is_sfb = iss_uops_2_is_sfb;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_1_bits_uop_br_mask = iss_uops_2_br_mask;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_1_bits_uop_br_tag = iss_uops_2_br_tag;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_1_bits_uop_ftq_idx = iss_uops_2_ftq_idx;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_1_bits_uop_edge_inst = iss_uops_2_edge_inst;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_1_bits_uop_pc_lob = iss_uops_2_pc_lob;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_1_bits_uop_taken = iss_uops_2_taken;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_1_bits_uop_imm_packed = iss_uops_2_imm_packed;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_1_bits_uop_csr_addr = iss_uops_2_csr_addr;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_1_bits_uop_rob_idx = iss_uops_2_rob_idx;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_1_bits_uop_ldq_idx = iss_uops_2_ldq_idx;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_1_bits_uop_stq_idx = iss_uops_2_stq_idx;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_1_bits_uop_rxq_idx = iss_uops_2_rxq_idx;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_1_bits_uop_pdst = iss_uops_2_pdst;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_1_bits_uop_prs1 = iss_uops_2_prs1;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_1_bits_uop_prs2 = iss_uops_2_prs2;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_1_bits_uop_prs3 = iss_uops_2_prs3;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_1_bits_uop_ppred = iss_uops_2_ppred;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_1_bits_uop_prs1_busy = iss_uops_2_prs1_busy;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_1_bits_uop_prs2_busy = iss_uops_2_prs2_busy;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_1_bits_uop_prs3_busy = iss_uops_2_prs3_busy;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_1_bits_uop_ppred_busy = iss_uops_2_ppred_busy;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_1_bits_uop_stale_pdst = iss_uops_2_stale_pdst;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_1_bits_uop_exception = iss_uops_2_exception;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_1_bits_uop_exc_cause = iss_uops_2_exc_cause;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_1_bits_uop_bypassable = iss_uops_2_bypassable;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_1_bits_uop_mem_cmd = iss_uops_2_mem_cmd;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_1_bits_uop_mem_size = iss_uops_2_mem_size;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_1_bits_uop_mem_signed = iss_uops_2_mem_signed;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_1_bits_uop_is_fence = iss_uops_2_is_fence;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_1_bits_uop_is_fencei = iss_uops_2_is_fencei;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_1_bits_uop_is_amo = iss_uops_2_is_amo;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_1_bits_uop_uses_ldq = iss_uops_2_uses_ldq;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_1_bits_uop_uses_stq = iss_uops_2_uses_stq;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_1_bits_uop_is_sys_pc2epc = iss_uops_2_is_sys_pc2epc;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_1_bits_uop_is_unique = iss_uops_2_is_unique;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_1_bits_uop_flush_on_commit = iss_uops_2_flush_on_commit;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_1_bits_uop_ldst_is_rs1 = iss_uops_2_ldst_is_rs1;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_1_bits_uop_ldst = iss_uops_2_ldst;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_1_bits_uop_lrs1 = iss_uops_2_lrs1;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_1_bits_uop_lrs2 = iss_uops_2_lrs2;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_1_bits_uop_lrs3 = iss_uops_2_lrs3;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_1_bits_uop_ldst_val = iss_uops_2_ldst_val;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_1_bits_uop_dst_rtype = iss_uops_2_dst_rtype;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_1_bits_uop_lrs1_rtype = iss_uops_2_lrs1_rtype;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_1_bits_uop_lrs2_rtype = iss_uops_2_lrs2_rtype;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_1_bits_uop_frs3_en = iss_uops_2_frs3_en;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_1_bits_uop_fp_val = iss_uops_2_fp_val;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_1_bits_uop_fp_single = iss_uops_2_fp_single;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_1_bits_uop_xcpt_pf_if = iss_uops_2_xcpt_pf_if;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_1_bits_uop_xcpt_ae_if = iss_uops_2_xcpt_ae_if;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_1_bits_uop_xcpt_ma_if = iss_uops_2_xcpt_ma_if;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_1_bits_uop_bp_debug_if = iss_uops_2_bp_debug_if;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_1_bits_uop_bp_xcpt_if = iss_uops_2_bp_xcpt_if;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_1_bits_uop_debug_fsrc = iss_uops_2_debug_fsrc;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_1_bits_uop_debug_tsrc = iss_uops_2_debug_tsrc;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_2_bits_uop_uopc = iss_uops_3_uopc;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_2_bits_uop_inst = iss_uops_3_inst;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_2_bits_uop_debug_inst = iss_uops_3_debug_inst;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_2_bits_uop_is_rvc = iss_uops_3_is_rvc;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_2_bits_uop_debug_pc = iss_uops_3_debug_pc;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_2_bits_uop_iq_type = iss_uops_3_iq_type;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_2_bits_uop_fu_code = iss_uops_3_fu_code;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_2_bits_uop_ctrl_br_type = iss_uops_3_ctrl_br_type;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_2_bits_uop_ctrl_op1_sel = iss_uops_3_ctrl_op1_sel;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_2_bits_uop_ctrl_op2_sel = iss_uops_3_ctrl_op2_sel;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_2_bits_uop_ctrl_imm_sel = iss_uops_3_ctrl_imm_sel;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_2_bits_uop_ctrl_op_fcn = iss_uops_3_ctrl_op_fcn;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_2_bits_uop_ctrl_fcn_dw = iss_uops_3_ctrl_fcn_dw;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_2_bits_uop_ctrl_csr_cmd = iss_uops_3_ctrl_csr_cmd;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_2_bits_uop_ctrl_is_load = iss_uops_3_ctrl_is_load;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_2_bits_uop_ctrl_is_sta = iss_uops_3_ctrl_is_sta;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_2_bits_uop_ctrl_is_std = iss_uops_3_ctrl_is_std;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_2_bits_uop_iw_state = iss_uops_3_iw_state;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_2_bits_uop_iw_p1_poisoned = iss_uops_3_iw_p1_poisoned;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_2_bits_uop_iw_p2_poisoned = iss_uops_3_iw_p2_poisoned;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_2_bits_uop_is_br = iss_uops_3_is_br;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_2_bits_uop_is_jalr = iss_uops_3_is_jalr;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_2_bits_uop_is_jal = iss_uops_3_is_jal;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_2_bits_uop_is_sfb = iss_uops_3_is_sfb;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_2_bits_uop_br_mask = iss_uops_3_br_mask;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_2_bits_uop_br_tag = iss_uops_3_br_tag;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_2_bits_uop_ftq_idx = iss_uops_3_ftq_idx;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_2_bits_uop_edge_inst = iss_uops_3_edge_inst;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_2_bits_uop_pc_lob = iss_uops_3_pc_lob;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_2_bits_uop_taken = iss_uops_3_taken;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_2_bits_uop_imm_packed = iss_uops_3_imm_packed;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_2_bits_uop_csr_addr = iss_uops_3_csr_addr;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_2_bits_uop_rob_idx = iss_uops_3_rob_idx;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_2_bits_uop_ldq_idx = iss_uops_3_ldq_idx;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_2_bits_uop_stq_idx = iss_uops_3_stq_idx;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_2_bits_uop_rxq_idx = iss_uops_3_rxq_idx;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_2_bits_uop_pdst = iss_uops_3_pdst;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_2_bits_uop_prs1 = iss_uops_3_prs1;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_2_bits_uop_prs2 = iss_uops_3_prs2;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_2_bits_uop_prs3 = iss_uops_3_prs3;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_2_bits_uop_ppred = iss_uops_3_ppred;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_2_bits_uop_prs1_busy = iss_uops_3_prs1_busy;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_2_bits_uop_prs2_busy = iss_uops_3_prs2_busy;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_2_bits_uop_prs3_busy = iss_uops_3_prs3_busy;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_2_bits_uop_ppred_busy = iss_uops_3_ppred_busy;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_2_bits_uop_stale_pdst = iss_uops_3_stale_pdst;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_2_bits_uop_exception = iss_uops_3_exception;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_2_bits_uop_exc_cause = iss_uops_3_exc_cause;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_2_bits_uop_bypassable = iss_uops_3_bypassable;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_2_bits_uop_mem_cmd = iss_uops_3_mem_cmd;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_2_bits_uop_mem_size = iss_uops_3_mem_size;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_2_bits_uop_mem_signed = iss_uops_3_mem_signed;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_2_bits_uop_is_fence = iss_uops_3_is_fence;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_2_bits_uop_is_fencei = iss_uops_3_is_fencei;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_2_bits_uop_is_amo = iss_uops_3_is_amo;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_2_bits_uop_uses_ldq = iss_uops_3_uses_ldq;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_2_bits_uop_uses_stq = iss_uops_3_uses_stq;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_2_bits_uop_is_sys_pc2epc = iss_uops_3_is_sys_pc2epc;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_2_bits_uop_is_unique = iss_uops_3_is_unique;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_2_bits_uop_flush_on_commit = iss_uops_3_flush_on_commit;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_2_bits_uop_ldst_is_rs1 = iss_uops_3_ldst_is_rs1;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_2_bits_uop_ldst = iss_uops_3_ldst;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_2_bits_uop_lrs1 = iss_uops_3_lrs1;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_2_bits_uop_lrs2 = iss_uops_3_lrs2;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_2_bits_uop_lrs3 = iss_uops_3_lrs3;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_2_bits_uop_ldst_val = iss_uops_3_ldst_val;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_2_bits_uop_dst_rtype = iss_uops_3_dst_rtype;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_2_bits_uop_lrs1_rtype = iss_uops_3_lrs1_rtype;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_2_bits_uop_lrs2_rtype = iss_uops_3_lrs2_rtype;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_2_bits_uop_frs3_en = iss_uops_3_frs3_en;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_2_bits_uop_fp_val = iss_uops_3_fp_val;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_2_bits_uop_fp_single = iss_uops_3_fp_single;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_2_bits_uop_xcpt_pf_if = iss_uops_3_xcpt_pf_if;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_2_bits_uop_xcpt_ae_if = iss_uops_3_xcpt_ae_if;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_2_bits_uop_xcpt_ma_if = iss_uops_3_xcpt_ma_if;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_2_bits_uop_bp_debug_if = iss_uops_3_bp_debug_if;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_2_bits_uop_bp_xcpt_if = iss_uops_3_bp_xcpt_if;\t// @[core.scala:173:24, :814:29]\n assign fast_wakeup_2_bits_uop_debug_fsrc = iss_uops_3_debug_fsrc;\t// @[core.scala:173:24, :814:29]\n wire [3:0] iss_uops_0_ctrl_br_type;\t// @[core.scala:173:24]\n wire [1:0] iss_uops_0_ctrl_op1_sel;\t// @[core.scala:173:24]\n wire [2:0] iss_uops_0_ctrl_op2_sel;\t// @[core.scala:173:24]\n wire [2:0] iss_uops_0_ctrl_imm_sel;\t// @[core.scala:173:24]\n wire [4:0] iss_uops_0_ctrl_op_fcn;\t// @[core.scala:173:24]\n wire iss_uops_0_ctrl_fcn_dw;\t// @[core.scala:173:24]\n wire [2:0] iss_uops_0_ctrl_csr_cmd;\t// @[core.scala:173:24]\n wire iss_uops_0_ctrl_is_load;\t// @[core.scala:173:24]\n wire iss_uops_0_ctrl_is_sta;\t// @[core.scala:173:24]\n wire iss_uops_0_ctrl_is_std;\t// @[core.scala:173:24]\n assign fast_wakeup_2_bits_uop_debug_tsrc = iss_uops_3_debug_tsrc;\t// @[core.scala:173:24, :814:29]\n wire [6:0] iss_uops_0_uopc;\t// @[core.scala:173:24]\n wire [31:0] iss_uops_0_inst;\t// @[core.scala:173:24]\n wire [31:0] iss_uops_0_debug_inst;\t// @[core.scala:173:24]\n wire iss_uops_0_is_rvc;\t// @[core.scala:173:24]\n wire [39:0] iss_uops_0_debug_pc;\t// @[core.scala:173:24]\n wire [2:0] iss_uops_0_iq_type;\t// @[core.scala:173:24]\n wire [9:0] iss_uops_0_fu_code;\t// @[core.scala:173:24]\n wire [1:0] iss_uops_0_iw_state;\t// @[core.scala:173:24]\n wire iss_uops_0_iw_p1_poisoned;\t// @[core.scala:173:24]\n wire iss_uops_0_iw_p2_poisoned;\t// @[core.scala:173:24]\n wire iss_uops_0_is_br;\t// @[core.scala:173:24]\n wire iss_uops_0_is_jalr;\t// @[core.scala:173:24]\n wire iss_uops_0_is_jal;\t// @[core.scala:173:24]\n wire iss_uops_0_is_sfb;\t// @[core.scala:173:24]\n wire [15:0] iss_uops_0_br_mask;\t// @[core.scala:173:24]\n wire [3:0] iss_uops_0_br_tag;\t// @[core.scala:173:24]\n wire [4:0] iss_uops_0_ftq_idx;\t// @[core.scala:173:24]\n wire iss_uops_0_edge_inst;\t// @[core.scala:173:24]\n wire [5:0] iss_uops_0_pc_lob;\t// @[core.scala:173:24]\n wire iss_uops_0_taken;\t// @[core.scala:173:24]\n wire [19:0] iss_uops_0_imm_packed;\t// @[core.scala:173:24]\n wire [11:0] iss_uops_0_csr_addr;\t// @[core.scala:173:24]\n wire [6:0] iss_uops_0_rob_idx;\t// @[core.scala:173:24]\n wire [4:0] iss_uops_0_ldq_idx;\t// @[core.scala:173:24]\n wire [4:0] iss_uops_0_stq_idx;\t// @[core.scala:173:24]\n wire [1:0] iss_uops_0_rxq_idx;\t// @[core.scala:173:24]\n wire [6:0] iss_uops_0_pdst;\t// @[core.scala:173:24]\n wire [6:0] iss_uops_0_prs1;\t// @[core.scala:173:24]\n wire [6:0] iss_uops_0_prs2;\t// @[core.scala:173:24]\n wire [6:0] iss_uops_0_prs3;\t// @[core.scala:173:24]\n wire [4:0] iss_uops_0_ppred;\t// @[core.scala:173:24]\n wire iss_uops_0_prs1_busy;\t// @[core.scala:173:24]\n wire iss_uops_0_prs2_busy;\t// @[core.scala:173:24]\n wire iss_uops_0_prs3_busy;\t// @[core.scala:173:24]\n wire iss_uops_0_ppred_busy;\t// @[core.scala:173:24]\n wire [6:0] iss_uops_0_stale_pdst;\t// @[core.scala:173:24]\n wire iss_uops_0_exception;\t// @[core.scala:173:24]\n wire [63:0] iss_uops_0_exc_cause;\t// @[core.scala:173:24]\n wire iss_uops_0_bypassable;\t// @[core.scala:173:24]\n wire [4:0] iss_uops_0_mem_cmd;\t// @[core.scala:173:24]\n wire [1:0] iss_uops_0_mem_size;\t// @[core.scala:173:24]\n wire iss_uops_0_mem_signed;\t// @[core.scala:173:24]\n wire iss_uops_0_is_fence;\t// @[core.scala:173:24]\n wire iss_uops_0_is_fencei;\t// @[core.scala:173:24]\n wire iss_uops_0_is_amo;\t// @[core.scala:173:24]\n wire iss_uops_0_uses_ldq;\t// @[core.scala:173:24]\n wire iss_uops_0_uses_stq;\t// @[core.scala:173:24]\n wire iss_uops_0_is_sys_pc2epc;\t// @[core.scala:173:24]\n wire iss_uops_0_is_unique;\t// @[core.scala:173:24]\n wire iss_uops_0_flush_on_commit;\t// @[core.scala:173:24]\n wire iss_uops_0_ldst_is_rs1;\t// @[core.scala:173:24]\n wire [5:0] iss_uops_0_ldst;\t// @[core.scala:173:24]\n wire [5:0] iss_uops_0_lrs1;\t// @[core.scala:173:24]\n wire [5:0] iss_uops_0_lrs2;\t// @[core.scala:173:24]\n wire [5:0] iss_uops_0_lrs3;\t// @[core.scala:173:24]\n wire iss_uops_0_ldst_val;\t// @[core.scala:173:24]\n wire [1:0] iss_uops_0_dst_rtype;\t// @[core.scala:173:24]\n wire [1:0] iss_uops_0_lrs1_rtype;\t// @[core.scala:173:24]\n wire [1:0] iss_uops_0_lrs2_rtype;\t// @[core.scala:173:24]\n wire iss_uops_0_frs3_en;\t// @[core.scala:173:24]\n wire iss_uops_0_fp_val;\t// @[core.scala:173:24]\n wire iss_uops_0_fp_single;\t// @[core.scala:173:24]\n wire iss_uops_0_xcpt_pf_if;\t// @[core.scala:173:24]\n wire iss_uops_0_xcpt_ae_if;\t// @[core.scala:173:24]\n wire iss_uops_0_xcpt_ma_if;\t// @[core.scala:173:24]\n wire iss_uops_0_bp_debug_if;\t// @[core.scala:173:24]\n wire iss_uops_0_bp_xcpt_if;\t// @[core.scala:173:24]\n wire [1:0] iss_uops_0_debug_fsrc;\t// @[core.scala:173:24]\n wire [1:0] iss_uops_0_debug_tsrc;\t// @[core.scala:173:24]\n wire [3:0] bypasses_0_bits_uop_ctrl_br_type;\t// @[core.scala:174:24]\n wire [1:0] bypasses_0_bits_uop_ctrl_op1_sel;\t// @[core.scala:174:24]\n wire [2:0] bypasses_0_bits_uop_ctrl_op2_sel;\t// @[core.scala:174:24]\n wire [2:0] bypasses_0_bits_uop_ctrl_imm_sel;\t// @[core.scala:174:24]\n wire [4:0] bypasses_0_bits_uop_ctrl_op_fcn;\t// @[core.scala:174:24]\n wire bypasses_0_bits_uop_ctrl_fcn_dw;\t// @[core.scala:174:24]\n wire [2:0] bypasses_0_bits_uop_ctrl_csr_cmd;\t// @[core.scala:174:24]\n wire bypasses_0_bits_uop_ctrl_is_load;\t// @[core.scala:174:24]\n wire bypasses_0_bits_uop_ctrl_is_sta;\t// @[core.scala:174:24]\n wire bypasses_0_bits_uop_ctrl_is_std;\t// @[core.scala:174:24]\n wire [6:0] bypasses_0_bits_uop_uopc;\t// @[core.scala:174:24]\n wire [31:0] bypasses_0_bits_uop_inst;\t// @[core.scala:174:24]\n wire [31:0] bypasses_0_bits_uop_debug_inst;\t// @[core.scala:174:24]\n wire bypasses_0_bits_uop_is_rvc;\t// @[core.scala:174:24]\n wire [39:0] bypasses_0_bits_uop_debug_pc;\t// @[core.scala:174:24]\n wire [2:0] bypasses_0_bits_uop_iq_type;\t// @[core.scala:174:24]\n wire [9:0] bypasses_0_bits_uop_fu_code;\t// @[core.scala:174:24]\n wire [1:0] bypasses_0_bits_uop_iw_state;\t// @[core.scala:174:24]\n wire bypasses_0_bits_uop_iw_p1_poisoned;\t// @[core.scala:174:24]\n wire bypasses_0_bits_uop_iw_p2_poisoned;\t// @[core.scala:174:24]\n wire bypasses_0_bits_uop_is_br;\t// @[core.scala:174:24]\n wire bypasses_0_bits_uop_is_jalr;\t// @[core.scala:174:24]\n wire bypasses_0_bits_uop_is_jal;\t// @[core.scala:174:24]\n wire bypasses_0_bits_uop_is_sfb;\t// @[core.scala:174:24]\n wire [15:0] bypasses_0_bits_uop_br_mask;\t// @[core.scala:174:24]\n wire [3:0] bypasses_0_bits_uop_br_tag;\t// @[core.scala:174:24]\n wire [4:0] bypasses_0_bits_uop_ftq_idx;\t// @[core.scala:174:24]\n wire bypasses_0_bits_uop_edge_inst;\t// @[core.scala:174:24]\n wire [5:0] bypasses_0_bits_uop_pc_lob;\t// @[core.scala:174:24]\n wire bypasses_0_bits_uop_taken;\t// @[core.scala:174:24]\n wire [19:0] bypasses_0_bits_uop_imm_packed;\t// @[core.scala:174:24]\n wire [11:0] bypasses_0_bits_uop_csr_addr;\t// @[core.scala:174:24]\n wire [6:0] bypasses_0_bits_uop_rob_idx;\t// @[core.scala:174:24]\n wire [4:0] bypasses_0_bits_uop_ldq_idx;\t// @[core.scala:174:24]\n wire [4:0] bypasses_0_bits_uop_stq_idx;\t// @[core.scala:174:24]\n wire [1:0] bypasses_0_bits_uop_rxq_idx;\t// @[core.scala:174:24]\n wire [6:0] bypasses_0_bits_uop_pdst;\t// @[core.scala:174:24]\n wire [6:0] bypasses_0_bits_uop_prs1;\t// @[core.scala:174:24]\n wire [6:0] bypasses_0_bits_uop_prs2;\t// @[core.scala:174:24]\n wire [6:0] bypasses_0_bits_uop_prs3;\t// @[core.scala:174:24]\n wire [4:0] bypasses_0_bits_uop_ppred;\t// @[core.scala:174:24]\n wire bypasses_0_bits_uop_prs1_busy;\t// @[core.scala:174:24]\n wire bypasses_0_bits_uop_prs2_busy;\t// @[core.scala:174:24]\n wire bypasses_0_bits_uop_prs3_busy;\t// @[core.scala:174:24]\n wire bypasses_0_bits_uop_ppred_busy;\t// @[core.scala:174:24]\n wire [6:0] bypasses_0_bits_uop_stale_pdst;\t// @[core.scala:174:24]\n wire bypasses_0_bits_uop_exception;\t// @[core.scala:174:24]\n wire [63:0] bypasses_0_bits_uop_exc_cause;\t// @[core.scala:174:24]\n wire bypasses_0_bits_uop_bypassable;\t// @[core.scala:174:24]\n wire [4:0] bypasses_0_bits_uop_mem_cmd;\t// @[core.scala:174:24]\n wire [1:0] bypasses_0_bits_uop_mem_size;\t// @[core.scala:174:24]\n wire bypasses_0_bits_uop_mem_signed;\t// @[core.scala:174:24]\n wire bypasses_0_bits_uop_is_fence;\t// @[core.scala:174:24]\n wire bypasses_0_bits_uop_is_fencei;\t// @[core.scala:174:24]\n wire bypasses_0_bits_uop_is_amo;\t// @[core.scala:174:24]\n wire bypasses_0_bits_uop_uses_ldq;\t// @[core.scala:174:24]\n wire bypasses_0_bits_uop_uses_stq;\t// @[core.scala:174:24]\n wire bypasses_0_bits_uop_is_sys_pc2epc;\t// @[core.scala:174:24]\n wire bypasses_0_bits_uop_is_unique;\t// @[core.scala:174:24]\n wire bypasses_0_bits_uop_flush_on_commit;\t// @[core.scala:174:24]\n wire bypasses_0_bits_uop_ldst_is_rs1;\t// @[core.scala:174:24]\n wire [5:0] bypasses_0_bits_uop_ldst;\t// @[core.scala:174:24]\n wire [5:0] bypasses_0_bits_uop_lrs1;\t// @[core.scala:174:24]\n wire [5:0] bypasses_0_bits_uop_lrs2;\t// @[core.scala:174:24]\n wire [5:0] bypasses_0_bits_uop_lrs3;\t// @[core.scala:174:24]\n wire bypasses_0_bits_uop_ldst_val;\t// @[core.scala:174:24]\n wire [1:0] bypasses_0_bits_uop_dst_rtype;\t// @[core.scala:174:24]\n wire [1:0] bypasses_0_bits_uop_lrs1_rtype;\t// @[core.scala:174:24]\n wire [1:0] bypasses_0_bits_uop_lrs2_rtype;\t// @[core.scala:174:24]\n wire bypasses_0_bits_uop_frs3_en;\t// @[core.scala:174:24]\n wire bypasses_0_bits_uop_fp_val;\t// @[core.scala:174:24]\n wire bypasses_0_bits_uop_fp_single;\t// @[core.scala:174:24]\n wire bypasses_0_bits_uop_xcpt_pf_if;\t// @[core.scala:174:24]\n wire bypasses_0_bits_uop_xcpt_ae_if;\t// @[core.scala:174:24]\n wire bypasses_0_bits_uop_xcpt_ma_if;\t// @[core.scala:174:24]\n wire bypasses_0_bits_uop_bp_debug_if;\t// @[core.scala:174:24]\n wire bypasses_0_bits_uop_bp_xcpt_if;\t// @[core.scala:174:24]\n wire [1:0] bypasses_0_bits_uop_debug_fsrc;\t// @[core.scala:174:24]\n wire [1:0] bypasses_0_bits_uop_debug_tsrc;\t// @[core.scala:174:24]\n wire [63:0] bypasses_0_bits_data;\t// @[core.scala:174:24]\n wire bypasses_0_valid;\t// @[core.scala:174:24]\n wire [3:0] bypasses_1_bits_uop_ctrl_br_type;\t// @[core.scala:174:24]\n wire [1:0] bypasses_1_bits_uop_ctrl_op1_sel;\t// @[core.scala:174:24]\n wire [2:0] bypasses_1_bits_uop_ctrl_op2_sel;\t// @[core.scala:174:24]\n wire [2:0] bypasses_1_bits_uop_ctrl_imm_sel;\t// @[core.scala:174:24]\n wire [4:0] bypasses_1_bits_uop_ctrl_op_fcn;\t// @[core.scala:174:24]\n wire bypasses_1_bits_uop_ctrl_fcn_dw;\t// @[core.scala:174:24]\n wire [2:0] bypasses_1_bits_uop_ctrl_csr_cmd;\t// @[core.scala:174:24]\n wire bypasses_1_bits_uop_ctrl_is_load;\t// @[core.scala:174:24]\n wire bypasses_1_bits_uop_ctrl_is_sta;\t// @[core.scala:174:24]\n wire bypasses_1_bits_uop_ctrl_is_std;\t// @[core.scala:174:24]\n wire [6:0] bypasses_1_bits_uop_uopc;\t// @[core.scala:174:24]\n wire [31:0] bypasses_1_bits_uop_inst;\t// @[core.scala:174:24]\n wire [31:0] bypasses_1_bits_uop_debug_inst;\t// @[core.scala:174:24]\n wire bypasses_1_bits_uop_is_rvc;\t// @[core.scala:174:24]\n wire [39:0] bypasses_1_bits_uop_debug_pc;\t// @[core.scala:174:24]\n wire [2:0] bypasses_1_bits_uop_iq_type;\t// @[core.scala:174:24]\n wire [9:0] bypasses_1_bits_uop_fu_code;\t// @[core.scala:174:24]\n wire [1:0] bypasses_1_bits_uop_iw_state;\t// @[core.scala:174:24]\n wire bypasses_1_bits_uop_iw_p1_poisoned;\t// @[core.scala:174:24]\n wire bypasses_1_bits_uop_iw_p2_poisoned;\t// @[core.scala:174:24]\n wire bypasses_1_bits_uop_is_br;\t// @[core.scala:174:24]\n wire bypasses_1_bits_uop_is_jalr;\t// @[core.scala:174:24]\n wire bypasses_1_bits_uop_is_jal;\t// @[core.scala:174:24]\n wire bypasses_1_bits_uop_is_sfb;\t// @[core.scala:174:24]\n wire [15:0] bypasses_1_bits_uop_br_mask;\t// @[core.scala:174:24]\n wire [3:0] bypasses_1_bits_uop_br_tag;\t// @[core.scala:174:24]\n wire [4:0] bypasses_1_bits_uop_ftq_idx;\t// @[core.scala:174:24]\n wire bypasses_1_bits_uop_edge_inst;\t// @[core.scala:174:24]\n wire [5:0] bypasses_1_bits_uop_pc_lob;\t// @[core.scala:174:24]\n wire bypasses_1_bits_uop_taken;\t// @[core.scala:174:24]\n wire [19:0] bypasses_1_bits_uop_imm_packed;\t// @[core.scala:174:24]\n wire [11:0] bypasses_1_bits_uop_csr_addr;\t// @[core.scala:174:24]\n wire [6:0] bypasses_1_bits_uop_rob_idx;\t// @[core.scala:174:24]\n wire [4:0] bypasses_1_bits_uop_ldq_idx;\t// @[core.scala:174:24]\n wire [4:0] bypasses_1_bits_uop_stq_idx;\t// @[core.scala:174:24]\n wire [1:0] bypasses_1_bits_uop_rxq_idx;\t// @[core.scala:174:24]\n wire [6:0] bypasses_1_bits_uop_pdst;\t// @[core.scala:174:24]\n wire [6:0] bypasses_1_bits_uop_prs1;\t// @[core.scala:174:24]\n wire [6:0] bypasses_1_bits_uop_prs2;\t// @[core.scala:174:24]\n wire [6:0] bypasses_1_bits_uop_prs3;\t// @[core.scala:174:24]\n wire [4:0] bypasses_1_bits_uop_ppred;\t// @[core.scala:174:24]\n wire bypasses_1_bits_uop_prs1_busy;\t// @[core.scala:174:24]\n wire bypasses_1_bits_uop_prs2_busy;\t// @[core.scala:174:24]\n wire bypasses_1_bits_uop_prs3_busy;\t// @[core.scala:174:24]\n wire bypasses_1_bits_uop_ppred_busy;\t// @[core.scala:174:24]\n wire [6:0] bypasses_1_bits_uop_stale_pdst;\t// @[core.scala:174:24]\n wire bypasses_1_bits_uop_exception;\t// @[core.scala:174:24]\n wire [63:0] bypasses_1_bits_uop_exc_cause;\t// @[core.scala:174:24]\n wire bypasses_1_bits_uop_bypassable;\t// @[core.scala:174:24]\n wire [4:0] bypasses_1_bits_uop_mem_cmd;\t// @[core.scala:174:24]\n wire [1:0] bypasses_1_bits_uop_mem_size;\t// @[core.scala:174:24]\n wire bypasses_1_bits_uop_mem_signed;\t// @[core.scala:174:24]\n wire bypasses_1_bits_uop_is_fence;\t// @[core.scala:174:24]\n wire bypasses_1_bits_uop_is_fencei;\t// @[core.scala:174:24]\n wire bypasses_1_bits_uop_is_amo;\t// @[core.scala:174:24]\n wire bypasses_1_bits_uop_uses_ldq;\t// @[core.scala:174:24]\n wire bypasses_1_bits_uop_uses_stq;\t// @[core.scala:174:24]\n wire bypasses_1_bits_uop_is_sys_pc2epc;\t// @[core.scala:174:24]\n wire bypasses_1_bits_uop_is_unique;\t// @[core.scala:174:24]\n wire bypasses_1_bits_uop_flush_on_commit;\t// @[core.scala:174:24]\n wire bypasses_1_bits_uop_ldst_is_rs1;\t// @[core.scala:174:24]\n wire [5:0] bypasses_1_bits_uop_ldst;\t// @[core.scala:174:24]\n wire [5:0] bypasses_1_bits_uop_lrs1;\t// @[core.scala:174:24]\n wire [5:0] bypasses_1_bits_uop_lrs2;\t// @[core.scala:174:24]\n wire [5:0] bypasses_1_bits_uop_lrs3;\t// @[core.scala:174:24]\n wire bypasses_1_bits_uop_ldst_val;\t// @[core.scala:174:24]\n wire [1:0] bypasses_1_bits_uop_dst_rtype;\t// @[core.scala:174:24]\n wire [1:0] bypasses_1_bits_uop_lrs1_rtype;\t// @[core.scala:174:24]\n wire [1:0] bypasses_1_bits_uop_lrs2_rtype;\t// @[core.scala:174:24]\n wire bypasses_1_bits_uop_frs3_en;\t// @[core.scala:174:24]\n wire bypasses_1_bits_uop_fp_val;\t// @[core.scala:174:24]\n wire bypasses_1_bits_uop_fp_single;\t// @[core.scala:174:24]\n wire bypasses_1_bits_uop_xcpt_pf_if;\t// @[core.scala:174:24]\n wire bypasses_1_bits_uop_xcpt_ae_if;\t// @[core.scala:174:24]\n wire bypasses_1_bits_uop_xcpt_ma_if;\t// @[core.scala:174:24]\n wire bypasses_1_bits_uop_bp_debug_if;\t// @[core.scala:174:24]\n wire bypasses_1_bits_uop_bp_xcpt_if;\t// @[core.scala:174:24]\n wire [1:0] bypasses_1_bits_uop_debug_fsrc;\t// @[core.scala:174:24]\n wire [1:0] bypasses_1_bits_uop_debug_tsrc;\t// @[core.scala:174:24]\n wire [63:0] bypasses_1_bits_data;\t// @[core.scala:174:24]\n wire bypasses_1_valid;\t// @[core.scala:174:24]\n wire [3:0] bypasses_2_bits_uop_ctrl_br_type;\t// @[core.scala:174:24]\n wire [1:0] bypasses_2_bits_uop_ctrl_op1_sel;\t// @[core.scala:174:24]\n wire [2:0] bypasses_2_bits_uop_ctrl_op2_sel;\t// @[core.scala:174:24]\n wire [2:0] bypasses_2_bits_uop_ctrl_imm_sel;\t// @[core.scala:174:24]\n wire [4:0] bypasses_2_bits_uop_ctrl_op_fcn;\t// @[core.scala:174:24]\n wire bypasses_2_bits_uop_ctrl_fcn_dw;\t// @[core.scala:174:24]\n wire [2:0] bypasses_2_bits_uop_ctrl_csr_cmd;\t// @[core.scala:174:24]\n wire bypasses_2_bits_uop_ctrl_is_load;\t// @[core.scala:174:24]\n wire bypasses_2_bits_uop_ctrl_is_sta;\t// @[core.scala:174:24]\n wire bypasses_2_bits_uop_ctrl_is_std;\t// @[core.scala:174:24]\n wire [6:0] bypasses_2_bits_uop_uopc;\t// @[core.scala:174:24]\n wire [31:0] bypasses_2_bits_uop_inst;\t// @[core.scala:174:24]\n wire [31:0] bypasses_2_bits_uop_debug_inst;\t// @[core.scala:174:24]\n wire bypasses_2_bits_uop_is_rvc;\t// @[core.scala:174:24]\n wire [39:0] bypasses_2_bits_uop_debug_pc;\t// @[core.scala:174:24]\n wire [2:0] bypasses_2_bits_uop_iq_type;\t// @[core.scala:174:24]\n wire [9:0] bypasses_2_bits_uop_fu_code;\t// @[core.scala:174:24]\n wire [1:0] bypasses_2_bits_uop_iw_state;\t// @[core.scala:174:24]\n wire bypasses_2_bits_uop_iw_p1_poisoned;\t// @[core.scala:174:24]\n wire bypasses_2_bits_uop_iw_p2_poisoned;\t// @[core.scala:174:24]\n wire bypasses_2_bits_uop_is_br;\t// @[core.scala:174:24]\n wire bypasses_2_bits_uop_is_jalr;\t// @[core.scala:174:24]\n wire bypasses_2_bits_uop_is_jal;\t// @[core.scala:174:24]\n wire bypasses_2_bits_uop_is_sfb;\t// @[core.scala:174:24]\n wire [15:0] bypasses_2_bits_uop_br_mask;\t// @[core.scala:174:24]\n wire [3:0] bypasses_2_bits_uop_br_tag;\t// @[core.scala:174:24]\n wire [4:0] bypasses_2_bits_uop_ftq_idx;\t// @[core.scala:174:24]\n wire bypasses_2_bits_uop_edge_inst;\t// @[core.scala:174:24]\n wire [5:0] bypasses_2_bits_uop_pc_lob;\t// @[core.scala:174:24]\n wire bypasses_2_bits_uop_taken;\t// @[core.scala:174:24]\n wire [19:0] bypasses_2_bits_uop_imm_packed;\t// @[core.scala:174:24]\n wire [11:0] bypasses_2_bits_uop_csr_addr;\t// @[core.scala:174:24]\n wire [6:0] bypasses_2_bits_uop_rob_idx;\t// @[core.scala:174:24]\n wire [4:0] bypasses_2_bits_uop_ldq_idx;\t// @[core.scala:174:24]\n wire [4:0] bypasses_2_bits_uop_stq_idx;\t// @[core.scala:174:24]\n wire [1:0] bypasses_2_bits_uop_rxq_idx;\t// @[core.scala:174:24]\n wire [6:0] bypasses_2_bits_uop_pdst;\t// @[core.scala:174:24]\n wire [6:0] bypasses_2_bits_uop_prs1;\t// @[core.scala:174:24]\n wire [6:0] bypasses_2_bits_uop_prs2;\t// @[core.scala:174:24]\n wire [6:0] bypasses_2_bits_uop_prs3;\t// @[core.scala:174:24]\n wire [4:0] bypasses_2_bits_uop_ppred;\t// @[core.scala:174:24]\n wire bypasses_2_bits_uop_prs1_busy;\t// @[core.scala:174:24]\n wire bypasses_2_bits_uop_prs2_busy;\t// @[core.scala:174:24]\n wire bypasses_2_bits_uop_prs3_busy;\t// @[core.scala:174:24]\n wire bypasses_2_bits_uop_ppred_busy;\t// @[core.scala:174:24]\n wire [6:0] bypasses_2_bits_uop_stale_pdst;\t// @[core.scala:174:24]\n wire bypasses_2_bits_uop_exception;\t// @[core.scala:174:24]\n wire [63:0] bypasses_2_bits_uop_exc_cause;\t// @[core.scala:174:24]\n wire bypasses_2_bits_uop_bypassable;\t// @[core.scala:174:24]\n wire [4:0] bypasses_2_bits_uop_mem_cmd;\t// @[core.scala:174:24]\n wire [1:0] bypasses_2_bits_uop_mem_size;\t// @[core.scala:174:24]\n wire bypasses_2_bits_uop_mem_signed;\t// @[core.scala:174:24]\n wire bypasses_2_bits_uop_is_fence;\t// @[core.scala:174:24]\n wire bypasses_2_bits_uop_is_fencei;\t// @[core.scala:174:24]\n wire bypasses_2_bits_uop_is_amo;\t// @[core.scala:174:24]\n wire bypasses_2_bits_uop_uses_ldq;\t// @[core.scala:174:24]\n wire bypasses_2_bits_uop_uses_stq;\t// @[core.scala:174:24]\n wire bypasses_2_bits_uop_is_sys_pc2epc;\t// @[core.scala:174:24]\n wire bypasses_2_bits_uop_is_unique;\t// @[core.scala:174:24]\n wire bypasses_2_bits_uop_flush_on_commit;\t// @[core.scala:174:24]\n wire bypasses_2_bits_uop_ldst_is_rs1;\t// @[core.scala:174:24]\n wire [5:0] bypasses_2_bits_uop_ldst;\t// @[core.scala:174:24]\n wire [5:0] bypasses_2_bits_uop_lrs1;\t// @[core.scala:174:24]\n wire [5:0] bypasses_2_bits_uop_lrs2;\t// @[core.scala:174:24]\n wire [5:0] bypasses_2_bits_uop_lrs3;\t// @[core.scala:174:24]\n wire bypasses_2_bits_uop_ldst_val;\t// @[core.scala:174:24]\n wire [1:0] bypasses_2_bits_uop_dst_rtype;\t// @[core.scala:174:24]\n wire [1:0] bypasses_2_bits_uop_lrs1_rtype;\t// @[core.scala:174:24]\n wire [1:0] bypasses_2_bits_uop_lrs2_rtype;\t// @[core.scala:174:24]\n wire bypasses_2_bits_uop_frs3_en;\t// @[core.scala:174:24]\n wire bypasses_2_bits_uop_fp_val;\t// @[core.scala:174:24]\n wire bypasses_2_bits_uop_fp_single;\t// @[core.scala:174:24]\n wire bypasses_2_bits_uop_xcpt_pf_if;\t// @[core.scala:174:24]\n wire bypasses_2_bits_uop_xcpt_ae_if;\t// @[core.scala:174:24]\n wire bypasses_2_bits_uop_xcpt_ma_if;\t// @[core.scala:174:24]\n wire bypasses_2_bits_uop_bp_debug_if;\t// @[core.scala:174:24]\n wire bypasses_2_bits_uop_bp_xcpt_if;\t// @[core.scala:174:24]\n wire [1:0] bypasses_2_bits_uop_debug_fsrc;\t// @[core.scala:174:24]\n wire [1:0] bypasses_2_bits_uop_debug_tsrc;\t// @[core.scala:174:24]\n wire [63:0] bypasses_2_bits_data;\t// @[core.scala:174:24]\n wire bypasses_2_valid;\t// @[core.scala:174:24]\n wire [3:0] bypasses_3_bits_uop_ctrl_br_type;\t// @[core.scala:174:24]\n wire [1:0] bypasses_3_bits_uop_ctrl_op1_sel;\t// @[core.scala:174:24]\n wire [2:0] bypasses_3_bits_uop_ctrl_op2_sel;\t// @[core.scala:174:24]\n wire [2:0] bypasses_3_bits_uop_ctrl_imm_sel;\t// @[core.scala:174:24]\n wire [4:0] bypasses_3_bits_uop_ctrl_op_fcn;\t// @[core.scala:174:24]\n wire bypasses_3_bits_uop_ctrl_fcn_dw;\t// @[core.scala:174:24]\n wire [2:0] bypasses_3_bits_uop_ctrl_csr_cmd;\t// @[core.scala:174:24]\n wire bypasses_3_bits_uop_ctrl_is_load;\t// @[core.scala:174:24]\n wire bypasses_3_bits_uop_ctrl_is_sta;\t// @[core.scala:174:24]\n wire bypasses_3_bits_uop_ctrl_is_std;\t// @[core.scala:174:24]\n wire [6:0] bypasses_3_bits_uop_uopc;\t// @[core.scala:174:24]\n wire [31:0] bypasses_3_bits_uop_inst;\t// @[core.scala:174:24]\n wire [31:0] bypasses_3_bits_uop_debug_inst;\t// @[core.scala:174:24]\n wire bypasses_3_bits_uop_is_rvc;\t// @[core.scala:174:24]\n wire [39:0] bypasses_3_bits_uop_debug_pc;\t// @[core.scala:174:24]\n wire [2:0] bypasses_3_bits_uop_iq_type;\t// @[core.scala:174:24]\n wire [9:0] bypasses_3_bits_uop_fu_code;\t// @[core.scala:174:24]\n wire [1:0] bypasses_3_bits_uop_iw_state;\t// @[core.scala:174:24]\n wire bypasses_3_bits_uop_iw_p1_poisoned;\t// @[core.scala:174:24]\n wire bypasses_3_bits_uop_iw_p2_poisoned;\t// @[core.scala:174:24]\n wire bypasses_3_bits_uop_is_br;\t// @[core.scala:174:24]\n wire bypasses_3_bits_uop_is_jalr;\t// @[core.scala:174:24]\n wire bypasses_3_bits_uop_is_jal;\t// @[core.scala:174:24]\n wire bypasses_3_bits_uop_is_sfb;\t// @[core.scala:174:24]\n wire [15:0] bypasses_3_bits_uop_br_mask;\t// @[core.scala:174:24]\n wire [3:0] bypasses_3_bits_uop_br_tag;\t// @[core.scala:174:24]\n wire [4:0] bypasses_3_bits_uop_ftq_idx;\t// @[core.scala:174:24]\n wire bypasses_3_bits_uop_edge_inst;\t// @[core.scala:174:24]\n wire [5:0] bypasses_3_bits_uop_pc_lob;\t// @[core.scala:174:24]\n wire bypasses_3_bits_uop_taken;\t// @[core.scala:174:24]\n wire [19:0] bypasses_3_bits_uop_imm_packed;\t// @[core.scala:174:24]\n wire [11:0] bypasses_3_bits_uop_csr_addr;\t// @[core.scala:174:24]\n wire [6:0] bypasses_3_bits_uop_rob_idx;\t// @[core.scala:174:24]\n wire [4:0] bypasses_3_bits_uop_ldq_idx;\t// @[core.scala:174:24]\n wire [4:0] bypasses_3_bits_uop_stq_idx;\t// @[core.scala:174:24]\n wire [1:0] bypasses_3_bits_uop_rxq_idx;\t// @[core.scala:174:24]\n wire [6:0] bypasses_3_bits_uop_pdst;\t// @[core.scala:174:24]\n wire [6:0] bypasses_3_bits_uop_prs1;\t// @[core.scala:174:24]\n wire [6:0] bypasses_3_bits_uop_prs2;\t// @[core.scala:174:24]\n wire [6:0] bypasses_3_bits_uop_prs3;\t// @[core.scala:174:24]\n wire [4:0] bypasses_3_bits_uop_ppred;\t// @[core.scala:174:24]\n wire bypasses_3_bits_uop_prs1_busy;\t// @[core.scala:174:24]\n wire bypasses_3_bits_uop_prs2_busy;\t// @[core.scala:174:24]\n wire bypasses_3_bits_uop_prs3_busy;\t// @[core.scala:174:24]\n wire bypasses_3_bits_uop_ppred_busy;\t// @[core.scala:174:24]\n wire [6:0] bypasses_3_bits_uop_stale_pdst;\t// @[core.scala:174:24]\n wire bypasses_3_bits_uop_exception;\t// @[core.scala:174:24]\n wire [63:0] bypasses_3_bits_uop_exc_cause;\t// @[core.scala:174:24]\n wire bypasses_3_bits_uop_bypassable;\t// @[core.scala:174:24]\n wire [4:0] bypasses_3_bits_uop_mem_cmd;\t// @[core.scala:174:24]\n wire [1:0] bypasses_3_bits_uop_mem_size;\t// @[core.scala:174:24]\n wire bypasses_3_bits_uop_mem_signed;\t// @[core.scala:174:24]\n wire bypasses_3_bits_uop_is_fence;\t// @[core.scala:174:24]\n wire bypasses_3_bits_uop_is_fencei;\t// @[core.scala:174:24]\n wire bypasses_3_bits_uop_is_amo;\t// @[core.scala:174:24]\n wire bypasses_3_bits_uop_uses_ldq;\t// @[core.scala:174:24]\n wire bypasses_3_bits_uop_uses_stq;\t// @[core.scala:174:24]\n wire bypasses_3_bits_uop_is_sys_pc2epc;\t// @[core.scala:174:24]\n wire bypasses_3_bits_uop_is_unique;\t// @[core.scala:174:24]\n wire bypasses_3_bits_uop_flush_on_commit;\t// @[core.scala:174:24]\n wire bypasses_3_bits_uop_ldst_is_rs1;\t// @[core.scala:174:24]\n wire [5:0] bypasses_3_bits_uop_ldst;\t// @[core.scala:174:24]\n wire [5:0] bypasses_3_bits_uop_lrs1;\t// @[core.scala:174:24]\n wire [5:0] bypasses_3_bits_uop_lrs2;\t// @[core.scala:174:24]\n wire [5:0] bypasses_3_bits_uop_lrs3;\t// @[core.scala:174:24]\n wire bypasses_3_bits_uop_ldst_val;\t// @[core.scala:174:24]\n wire [1:0] bypasses_3_bits_uop_dst_rtype;\t// @[core.scala:174:24]\n wire [1:0] bypasses_3_bits_uop_lrs1_rtype;\t// @[core.scala:174:24]\n wire [1:0] bypasses_3_bits_uop_lrs2_rtype;\t// @[core.scala:174:24]\n wire bypasses_3_bits_uop_frs3_en;\t// @[core.scala:174:24]\n wire bypasses_3_bits_uop_fp_val;\t// @[core.scala:174:24]\n wire bypasses_3_bits_uop_fp_single;\t// @[core.scala:174:24]\n wire bypasses_3_bits_uop_xcpt_pf_if;\t// @[core.scala:174:24]\n wire bypasses_3_bits_uop_xcpt_ae_if;\t// @[core.scala:174:24]\n wire bypasses_3_bits_uop_xcpt_ma_if;\t// @[core.scala:174:24]\n wire bypasses_3_bits_uop_bp_debug_if;\t// @[core.scala:174:24]\n wire bypasses_3_bits_uop_bp_xcpt_if;\t// @[core.scala:174:24]\n wire [1:0] bypasses_3_bits_uop_debug_fsrc;\t// @[core.scala:174:24]\n wire [1:0] bypasses_3_bits_uop_debug_tsrc;\t// @[core.scala:174:24]\n wire [63:0] bypasses_3_bits_data;\t// @[core.scala:174:24]\n wire bypasses_3_valid;\t// @[core.scala:174:24]\n wire [3:0] bypasses_4_bits_uop_ctrl_br_type;\t// @[core.scala:174:24]\n wire [1:0] bypasses_4_bits_uop_ctrl_op1_sel;\t// @[core.scala:174:24]\n wire [2:0] bypasses_4_bits_uop_ctrl_op2_sel;\t// @[core.scala:174:24]\n wire [2:0] bypasses_4_bits_uop_ctrl_imm_sel;\t// @[core.scala:174:24]\n wire [4:0] bypasses_4_bits_uop_ctrl_op_fcn;\t// @[core.scala:174:24]\n wire bypasses_4_bits_uop_ctrl_fcn_dw;\t// @[core.scala:174:24]\n wire [2:0] bypasses_4_bits_uop_ctrl_csr_cmd;\t// @[core.scala:174:24]\n wire bypasses_4_bits_uop_ctrl_is_load;\t// @[core.scala:174:24]\n wire bypasses_4_bits_uop_ctrl_is_sta;\t// @[core.scala:174:24]\n wire bypasses_4_bits_uop_ctrl_is_std;\t// @[core.scala:174:24]\n wire [6:0] bypasses_4_bits_uop_uopc;\t// @[core.scala:174:24]\n wire [31:0] bypasses_4_bits_uop_inst;\t// @[core.scala:174:24]\n wire [31:0] bypasses_4_bits_uop_debug_inst;\t// @[core.scala:174:24]\n wire bypasses_4_bits_uop_is_rvc;\t// @[core.scala:174:24]\n wire [39:0] bypasses_4_bits_uop_debug_pc;\t// @[core.scala:174:24]\n wire [2:0] bypasses_4_bits_uop_iq_type;\t// @[core.scala:174:24]\n wire [9:0] bypasses_4_bits_uop_fu_code;\t// @[core.scala:174:24]\n wire [1:0] bypasses_4_bits_uop_iw_state;\t// @[core.scala:174:24]\n wire bypasses_4_bits_uop_iw_p1_poisoned;\t// @[core.scala:174:24]\n wire bypasses_4_bits_uop_iw_p2_poisoned;\t// @[core.scala:174:24]\n wire bypasses_4_bits_uop_is_br;\t// @[core.scala:174:24]\n wire bypasses_4_bits_uop_is_jalr;\t// @[core.scala:174:24]\n wire bypasses_4_bits_uop_is_jal;\t// @[core.scala:174:24]\n wire bypasses_4_bits_uop_is_sfb;\t// @[core.scala:174:24]\n wire [15:0] bypasses_4_bits_uop_br_mask;\t// @[core.scala:174:24]\n wire [3:0] bypasses_4_bits_uop_br_tag;\t// @[core.scala:174:24]\n wire [4:0] bypasses_4_bits_uop_ftq_idx;\t// @[core.scala:174:24]\n wire bypasses_4_bits_uop_edge_inst;\t// @[core.scala:174:24]\n wire [5:0] bypasses_4_bits_uop_pc_lob;\t// @[core.scala:174:24]\n wire bypasses_4_bits_uop_taken;\t// @[core.scala:174:24]\n wire [19:0] bypasses_4_bits_uop_imm_packed;\t// @[core.scala:174:24]\n wire [11:0] bypasses_4_bits_uop_csr_addr;\t// @[core.scala:174:24]\n wire [6:0] bypasses_4_bits_uop_rob_idx;\t// @[core.scala:174:24]\n wire [4:0] bypasses_4_bits_uop_ldq_idx;\t// @[core.scala:174:24]\n wire [4:0] bypasses_4_bits_uop_stq_idx;\t// @[core.scala:174:24]\n wire [1:0] bypasses_4_bits_uop_rxq_idx;\t// @[core.scala:174:24]\n wire [6:0] bypasses_4_bits_uop_pdst;\t// @[core.scala:174:24]\n wire [6:0] bypasses_4_bits_uop_prs1;\t// @[core.scala:174:24]\n wire [6:0] bypasses_4_bits_uop_prs2;\t// @[core.scala:174:24]\n wire [6:0] bypasses_4_bits_uop_prs3;\t// @[core.scala:174:24]\n wire [4:0] bypasses_4_bits_uop_ppred;\t// @[core.scala:174:24]\n wire bypasses_4_bits_uop_prs1_busy;\t// @[core.scala:174:24]\n wire bypasses_4_bits_uop_prs2_busy;\t// @[core.scala:174:24]\n wire bypasses_4_bits_uop_prs3_busy;\t// @[core.scala:174:24]\n wire bypasses_4_bits_uop_ppred_busy;\t// @[core.scala:174:24]\n wire [6:0] bypasses_4_bits_uop_stale_pdst;\t// @[core.scala:174:24]\n wire bypasses_4_bits_uop_exception;\t// @[core.scala:174:24]\n wire [63:0] bypasses_4_bits_uop_exc_cause;\t// @[core.scala:174:24]\n wire bypasses_4_bits_uop_bypassable;\t// @[core.scala:174:24]\n wire [4:0] bypasses_4_bits_uop_mem_cmd;\t// @[core.scala:174:24]\n wire [1:0] bypasses_4_bits_uop_mem_size;\t// @[core.scala:174:24]\n wire bypasses_4_bits_uop_mem_signed;\t// @[core.scala:174:24]\n wire bypasses_4_bits_uop_is_fence;\t// @[core.scala:174:24]\n wire bypasses_4_bits_uop_is_fencei;\t// @[core.scala:174:24]\n wire bypasses_4_bits_uop_is_amo;\t// @[core.scala:174:24]\n wire bypasses_4_bits_uop_uses_ldq;\t// @[core.scala:174:24]\n wire bypasses_4_bits_uop_uses_stq;\t// @[core.scala:174:24]\n wire bypasses_4_bits_uop_is_sys_pc2epc;\t// @[core.scala:174:24]\n wire bypasses_4_bits_uop_is_unique;\t// @[core.scala:174:24]\n wire bypasses_4_bits_uop_flush_on_commit;\t// @[core.scala:174:24]\n wire bypasses_4_bits_uop_ldst_is_rs1;\t// @[core.scala:174:24]\n wire [5:0] bypasses_4_bits_uop_ldst;\t// @[core.scala:174:24]\n wire [5:0] bypasses_4_bits_uop_lrs1;\t// @[core.scala:174:24]\n wire [5:0] bypasses_4_bits_uop_lrs2;\t// @[core.scala:174:24]\n wire [5:0] bypasses_4_bits_uop_lrs3;\t// @[core.scala:174:24]\n wire bypasses_4_bits_uop_ldst_val;\t// @[core.scala:174:24]\n wire [1:0] bypasses_4_bits_uop_dst_rtype;\t// @[core.scala:174:24]\n wire [1:0] bypasses_4_bits_uop_lrs1_rtype;\t// @[core.scala:174:24]\n wire [1:0] bypasses_4_bits_uop_lrs2_rtype;\t// @[core.scala:174:24]\n wire bypasses_4_bits_uop_frs3_en;\t// @[core.scala:174:24]\n wire bypasses_4_bits_uop_fp_val;\t// @[core.scala:174:24]\n wire bypasses_4_bits_uop_fp_single;\t// @[core.scala:174:24]\n wire bypasses_4_bits_uop_xcpt_pf_if;\t// @[core.scala:174:24]\n wire bypasses_4_bits_uop_xcpt_ae_if;\t// @[core.scala:174:24]\n wire bypasses_4_bits_uop_xcpt_ma_if;\t// @[core.scala:174:24]\n wire bypasses_4_bits_uop_bp_debug_if;\t// @[core.scala:174:24]\n wire bypasses_4_bits_uop_bp_xcpt_if;\t// @[core.scala:174:24]\n wire [1:0] bypasses_4_bits_uop_debug_fsrc;\t// @[core.scala:174:24]\n wire [1:0] bypasses_4_bits_uop_debug_tsrc;\t// @[core.scala:174:24]\n wire [63:0] bypasses_4_bits_data;\t// @[core.scala:174:24]\n wire bypasses_4_valid;\t// @[core.scala:174:24]\n wire [3:0] pred_bypasses_0_bits_uop_ctrl_br_type;\t// @[core.scala:175:27]\n wire [1:0] pred_bypasses_0_bits_uop_ctrl_op1_sel;\t// @[core.scala:175:27]\n wire [2:0] pred_bypasses_0_bits_uop_ctrl_op2_sel;\t// @[core.scala:175:27]\n wire [2:0] pred_bypasses_0_bits_uop_ctrl_imm_sel;\t// @[core.scala:175:27]\n wire [4:0] pred_bypasses_0_bits_uop_ctrl_op_fcn;\t// @[core.scala:175:27]\n wire pred_bypasses_0_bits_uop_ctrl_fcn_dw;\t// @[core.scala:175:27]\n wire [2:0] pred_bypasses_0_bits_uop_ctrl_csr_cmd;\t// @[core.scala:175:27]\n wire pred_bypasses_0_bits_uop_ctrl_is_load;\t// @[core.scala:175:27]\n wire pred_bypasses_0_bits_uop_ctrl_is_sta;\t// @[core.scala:175:27]\n wire pred_bypasses_0_bits_uop_ctrl_is_std;\t// @[core.scala:175:27]\n wire [6:0] pred_bypasses_0_bits_uop_uopc;\t// @[core.scala:175:27]\n wire [31:0] pred_bypasses_0_bits_uop_inst;\t// @[core.scala:175:27]\n wire [31:0] pred_bypasses_0_bits_uop_debug_inst;\t// @[core.scala:175:27]\n wire pred_bypasses_0_bits_uop_is_rvc;\t// @[core.scala:175:27]\n wire [39:0] pred_bypasses_0_bits_uop_debug_pc;\t// @[core.scala:175:27]\n wire [2:0] pred_bypasses_0_bits_uop_iq_type;\t// @[core.scala:175:27]\n wire [9:0] pred_bypasses_0_bits_uop_fu_code;\t// @[core.scala:175:27]\n wire [1:0] pred_bypasses_0_bits_uop_iw_state;\t// @[core.scala:175:27]\n wire pred_bypasses_0_bits_uop_iw_p1_poisoned;\t// @[core.scala:175:27]\n wire pred_bypasses_0_bits_uop_iw_p2_poisoned;\t// @[core.scala:175:27]\n wire pred_bypasses_0_bits_uop_is_br;\t// @[core.scala:175:27]\n wire pred_bypasses_0_bits_uop_is_jalr;\t// @[core.scala:175:27]\n wire pred_bypasses_0_bits_uop_is_jal;\t// @[core.scala:175:27]\n wire pred_bypasses_0_bits_uop_is_sfb;\t// @[core.scala:175:27]\n wire [15:0] pred_bypasses_0_bits_uop_br_mask;\t// @[core.scala:175:27]\n wire [3:0] pred_bypasses_0_bits_uop_br_tag;\t// @[core.scala:175:27]\n wire [4:0] pred_bypasses_0_bits_uop_ftq_idx;\t// @[core.scala:175:27]\n wire pred_bypasses_0_bits_uop_edge_inst;\t// @[core.scala:175:27]\n wire [5:0] pred_bypasses_0_bits_uop_pc_lob;\t// @[core.scala:175:27]\n wire pred_bypasses_0_bits_uop_taken;\t// @[core.scala:175:27]\n wire [19:0] pred_bypasses_0_bits_uop_imm_packed;\t// @[core.scala:175:27]\n wire [11:0] pred_bypasses_0_bits_uop_csr_addr;\t// @[core.scala:175:27]\n wire [6:0] pred_bypasses_0_bits_uop_rob_idx;\t// @[core.scala:175:27]\n wire [4:0] pred_bypasses_0_bits_uop_ldq_idx;\t// @[core.scala:175:27]\n wire [4:0] pred_bypasses_0_bits_uop_stq_idx;\t// @[core.scala:175:27]\n wire [1:0] pred_bypasses_0_bits_uop_rxq_idx;\t// @[core.scala:175:27]\n wire [6:0] pred_bypasses_0_bits_uop_pdst;\t// @[core.scala:175:27]\n wire [6:0] pred_bypasses_0_bits_uop_prs1;\t// @[core.scala:175:27]\n wire [6:0] pred_bypasses_0_bits_uop_prs2;\t// @[core.scala:175:27]\n wire [6:0] pred_bypasses_0_bits_uop_prs3;\t// @[core.scala:175:27]\n wire [4:0] pred_bypasses_0_bits_uop_ppred;\t// @[core.scala:175:27]\n wire pred_bypasses_0_bits_uop_prs1_busy;\t// @[core.scala:175:27]\n wire pred_bypasses_0_bits_uop_prs2_busy;\t// @[core.scala:175:27]\n wire pred_bypasses_0_bits_uop_prs3_busy;\t// @[core.scala:175:27]\n wire pred_bypasses_0_bits_uop_ppred_busy;\t// @[core.scala:175:27]\n wire [6:0] pred_bypasses_0_bits_uop_stale_pdst;\t// @[core.scala:175:27]\n wire pred_bypasses_0_bits_uop_exception;\t// @[core.scala:175:27]\n wire [63:0] pred_bypasses_0_bits_uop_exc_cause;\t// @[core.scala:175:27]\n wire pred_bypasses_0_bits_uop_bypassable;\t// @[core.scala:175:27]\n wire [4:0] pred_bypasses_0_bits_uop_mem_cmd;\t// @[core.scala:175:27]\n wire [1:0] pred_bypasses_0_bits_uop_mem_size;\t// @[core.scala:175:27]\n wire pred_bypasses_0_bits_uop_mem_signed;\t// @[core.scala:175:27]\n wire pred_bypasses_0_bits_uop_is_fence;\t// @[core.scala:175:27]\n wire pred_bypasses_0_bits_uop_is_fencei;\t// @[core.scala:175:27]\n wire pred_bypasses_0_bits_uop_is_amo;\t// @[core.scala:175:27]\n wire pred_bypasses_0_bits_uop_uses_ldq;\t// @[core.scala:175:27]\n wire pred_bypasses_0_bits_uop_uses_stq;\t// @[core.scala:175:27]\n wire pred_bypasses_0_bits_uop_is_sys_pc2epc;\t// @[core.scala:175:27]\n wire pred_bypasses_0_bits_uop_is_unique;\t// @[core.scala:175:27]\n wire pred_bypasses_0_bits_uop_flush_on_commit;\t// @[core.scala:175:27]\n wire pred_bypasses_0_bits_uop_ldst_is_rs1;\t// @[core.scala:175:27]\n wire [5:0] pred_bypasses_0_bits_uop_ldst;\t// @[core.scala:175:27]\n wire [5:0] pred_bypasses_0_bits_uop_lrs1;\t// @[core.scala:175:27]\n wire [5:0] pred_bypasses_0_bits_uop_lrs2;\t// @[core.scala:175:27]\n wire [5:0] pred_bypasses_0_bits_uop_lrs3;\t// @[core.scala:175:27]\n wire pred_bypasses_0_bits_uop_ldst_val;\t// @[core.scala:175:27]\n wire [1:0] pred_bypasses_0_bits_uop_dst_rtype;\t// @[core.scala:175:27]\n wire [1:0] pred_bypasses_0_bits_uop_lrs1_rtype;\t// @[core.scala:175:27]\n wire [1:0] pred_bypasses_0_bits_uop_lrs2_rtype;\t// @[core.scala:175:27]\n wire pred_bypasses_0_bits_uop_frs3_en;\t// @[core.scala:175:27]\n wire pred_bypasses_0_bits_uop_fp_val;\t// @[core.scala:175:27]\n wire pred_bypasses_0_bits_uop_fp_single;\t// @[core.scala:175:27]\n wire pred_bypasses_0_bits_uop_xcpt_pf_if;\t// @[core.scala:175:27]\n wire pred_bypasses_0_bits_uop_xcpt_ae_if;\t// @[core.scala:175:27]\n wire pred_bypasses_0_bits_uop_xcpt_ma_if;\t// @[core.scala:175:27]\n wire pred_bypasses_0_bits_uop_bp_debug_if;\t// @[core.scala:175:27]\n wire pred_bypasses_0_bits_uop_bp_xcpt_if;\t// @[core.scala:175:27]\n wire [1:0] pred_bypasses_0_bits_uop_debug_fsrc;\t// @[core.scala:175:27]\n wire [1:0] pred_bypasses_0_bits_uop_debug_tsrc;\t// @[core.scala:175:27]\n wire pred_bypasses_0_bits_data;\t// @[core.scala:175:27]\n wire pred_bypasses_0_valid;\t// @[core.scala:175:27]\n reg [6:0] brinfos_0_uop_uopc;\t// @[core.scala:182:20]\n reg [31:0] brinfos_0_uop_inst;\t// @[core.scala:182:20]\n reg [31:0] brinfos_0_uop_debug_inst;\t// @[core.scala:182:20]\n reg brinfos_0_uop_is_rvc;\t// @[core.scala:182:20]\n reg [39:0] brinfos_0_uop_debug_pc;\t// @[core.scala:182:20]\n reg [2:0] brinfos_0_uop_iq_type;\t// @[core.scala:182:20]\n reg [9:0] brinfos_0_uop_fu_code;\t// @[core.scala:182:20]\n reg [3:0] brinfos_0_uop_ctrl_br_type;\t// @[core.scala:182:20]\n reg [1:0] brinfos_0_uop_ctrl_op1_sel;\t// @[core.scala:182:20]\n reg [2:0] brinfos_0_uop_ctrl_op2_sel;\t// @[core.scala:182:20]\n reg [2:0] brinfos_0_uop_ctrl_imm_sel;\t// @[core.scala:182:20]\n reg [4:0] brinfos_0_uop_ctrl_op_fcn;\t// @[core.scala:182:20]\n reg brinfos_0_uop_ctrl_fcn_dw;\t// @[core.scala:182:20]\n reg [2:0] brinfos_0_uop_ctrl_csr_cmd;\t// @[core.scala:182:20]\n reg brinfos_0_uop_ctrl_is_load;\t// @[core.scala:182:20]\n reg brinfos_0_uop_ctrl_is_sta;\t// @[core.scala:182:20]\n reg brinfos_0_uop_ctrl_is_std;\t// @[core.scala:182:20]\n reg [1:0] brinfos_0_uop_iw_state;\t// @[core.scala:182:20]\n reg brinfos_0_uop_iw_p1_poisoned;\t// @[core.scala:182:20]\n reg brinfos_0_uop_iw_p2_poisoned;\t// @[core.scala:182:20]\n reg brinfos_0_uop_is_br;\t// @[core.scala:182:20]\n reg brinfos_0_uop_is_jalr;\t// @[core.scala:182:20]\n reg brinfos_0_uop_is_jal;\t// @[core.scala:182:20]\n reg brinfos_0_uop_is_sfb;\t// @[core.scala:182:20]\n reg [15:0] brinfos_0_uop_br_mask;\t// @[core.scala:182:20]\n reg [3:0] brinfos_0_uop_br_tag;\t// @[core.scala:182:20]\n reg [4:0] brinfos_0_uop_ftq_idx;\t// @[core.scala:182:20]\n reg brinfos_0_uop_edge_inst;\t// @[core.scala:182:20]\n reg [5:0] brinfos_0_uop_pc_lob;\t// @[core.scala:182:20]\n reg brinfos_0_uop_taken;\t// @[core.scala:182:20]\n reg [19:0] brinfos_0_uop_imm_packed;\t// @[core.scala:182:20]\n reg [11:0] brinfos_0_uop_csr_addr;\t// @[core.scala:182:20]\n reg [6:0] brinfos_0_uop_rob_idx;\t// @[core.scala:182:20]\n reg [4:0] brinfos_0_uop_ldq_idx;\t// @[core.scala:182:20]\n reg [4:0] brinfos_0_uop_stq_idx;\t// @[core.scala:182:20]\n reg [1:0] brinfos_0_uop_rxq_idx;\t// @[core.scala:182:20]\n reg [6:0] brinfos_0_uop_pdst;\t// @[core.scala:182:20]\n reg [6:0] brinfos_0_uop_prs1;\t// @[core.scala:182:20]\n reg [6:0] brinfos_0_uop_prs2;\t// @[core.scala:182:20]\n reg [6:0] brinfos_0_uop_prs3;\t// @[core.scala:182:20]\n reg [4:0] brinfos_0_uop_ppred;\t// @[core.scala:182:20]\n reg brinfos_0_uop_prs1_busy;\t// @[core.scala:182:20]\n reg brinfos_0_uop_prs2_busy;\t// @[core.scala:182:20]\n reg brinfos_0_uop_prs3_busy;\t// @[core.scala:182:20]\n reg brinfos_0_uop_ppred_busy;\t// @[core.scala:182:20]\n reg [6:0] brinfos_0_uop_stale_pdst;\t// @[core.scala:182:20]\n reg brinfos_0_uop_exception;\t// @[core.scala:182:20]\n reg [63:0] brinfos_0_uop_exc_cause;\t// @[core.scala:182:20]\n reg brinfos_0_uop_bypassable;\t// @[core.scala:182:20]\n reg [4:0] brinfos_0_uop_mem_cmd;\t// @[core.scala:182:20]\n reg [1:0] brinfos_0_uop_mem_size;\t// @[core.scala:182:20]\n reg brinfos_0_uop_mem_signed;\t// @[core.scala:182:20]\n reg brinfos_0_uop_is_fence;\t// @[core.scala:182:20]\n reg brinfos_0_uop_is_fencei;\t// @[core.scala:182:20]\n reg brinfos_0_uop_is_amo;\t// @[core.scala:182:20]\n reg brinfos_0_uop_uses_ldq;\t// @[core.scala:182:20]\n reg brinfos_0_uop_uses_stq;\t// @[core.scala:182:20]\n reg brinfos_0_uop_is_sys_pc2epc;\t// @[core.scala:182:20]\n reg brinfos_0_uop_is_unique;\t// @[core.scala:182:20]\n reg brinfos_0_uop_flush_on_commit;\t// @[core.scala:182:20]\n reg brinfos_0_uop_ldst_is_rs1;\t// @[core.scala:182:20]\n reg [5:0] brinfos_0_uop_ldst;\t// @[core.scala:182:20]\n reg [5:0] brinfos_0_uop_lrs1;\t// @[core.scala:182:20]\n reg [5:0] brinfos_0_uop_lrs2;\t// @[core.scala:182:20]\n reg [5:0] brinfos_0_uop_lrs3;\t// @[core.scala:182:20]\n reg brinfos_0_uop_ldst_val;\t// @[core.scala:182:20]\n reg [1:0] brinfos_0_uop_dst_rtype;\t// @[core.scala:182:20]\n reg [1:0] brinfos_0_uop_lrs1_rtype;\t// @[core.scala:182:20]\n reg [1:0] brinfos_0_uop_lrs2_rtype;\t// @[core.scala:182:20]\n reg brinfos_0_uop_frs3_en;\t// @[core.scala:182:20]\n reg brinfos_0_uop_fp_val;\t// @[core.scala:182:20]\n reg brinfos_0_uop_fp_single;\t// @[core.scala:182:20]\n reg brinfos_0_uop_xcpt_pf_if;\t// @[core.scala:182:20]\n reg brinfos_0_uop_xcpt_ae_if;\t// @[core.scala:182:20]\n reg brinfos_0_uop_xcpt_ma_if;\t// @[core.scala:182:20]\n reg brinfos_0_uop_bp_debug_if;\t// @[core.scala:182:20]\n reg brinfos_0_uop_bp_xcpt_if;\t// @[core.scala:182:20]\n reg [1:0] brinfos_0_uop_debug_fsrc;\t// @[core.scala:182:20]\n reg [1:0] brinfos_0_uop_debug_tsrc;\t// @[core.scala:182:20]\n reg brinfos_0_valid;\t// @[core.scala:182:20]\n reg brinfos_0_mispredict;\t// @[core.scala:182:20]\n reg brinfos_0_taken;\t// @[core.scala:182:20]\n reg [2:0] brinfos_0_cfi_type;\t// @[core.scala:182:20]\n reg [1:0] brinfos_0_pc_sel;\t// @[core.scala:182:20]\n reg [39:0] brinfos_0_jalr_target;\t// @[core.scala:182:20]\n reg [20:0] brinfos_0_target_offset;\t// @[core.scala:182:20]\n reg [6:0] brinfos_1_uop_uopc;\t// @[core.scala:182:20]\n reg [31:0] brinfos_1_uop_inst;\t// @[core.scala:182:20]\n reg [31:0] brinfos_1_uop_debug_inst;\t// @[core.scala:182:20]\n reg brinfos_1_uop_is_rvc;\t// @[core.scala:182:20]\n reg [39:0] brinfos_1_uop_debug_pc;\t// @[core.scala:182:20]\n reg [2:0] brinfos_1_uop_iq_type;\t// @[core.scala:182:20]\n reg [9:0] brinfos_1_uop_fu_code;\t// @[core.scala:182:20]\n reg [3:0] brinfos_1_uop_ctrl_br_type;\t// @[core.scala:182:20]\n reg [1:0] brinfos_1_uop_ctrl_op1_sel;\t// @[core.scala:182:20]\n reg [2:0] brinfos_1_uop_ctrl_op2_sel;\t// @[core.scala:182:20]\n reg [2:0] brinfos_1_uop_ctrl_imm_sel;\t// @[core.scala:182:20]\n reg [4:0] brinfos_1_uop_ctrl_op_fcn;\t// @[core.scala:182:20]\n reg brinfos_1_uop_ctrl_fcn_dw;\t// @[core.scala:182:20]\n reg [2:0] brinfos_1_uop_ctrl_csr_cmd;\t// @[core.scala:182:20]\n reg brinfos_1_uop_ctrl_is_load;\t// @[core.scala:182:20]\n reg brinfos_1_uop_ctrl_is_sta;\t// @[core.scala:182:20]\n reg brinfos_1_uop_ctrl_is_std;\t// @[core.scala:182:20]\n reg [1:0] brinfos_1_uop_iw_state;\t// @[core.scala:182:20]\n reg brinfos_1_uop_iw_p1_poisoned;\t// @[core.scala:182:20]\n reg brinfos_1_uop_iw_p2_poisoned;\t// @[core.scala:182:20]\n reg brinfos_1_uop_is_br;\t// @[core.scala:182:20]\n reg brinfos_1_uop_is_jalr;\t// @[core.scala:182:20]\n reg brinfos_1_uop_is_jal;\t// @[core.scala:182:20]\n reg brinfos_1_uop_is_sfb;\t// @[core.scala:182:20]\n reg [15:0] brinfos_1_uop_br_mask;\t// @[core.scala:182:20]\n reg [3:0] brinfos_1_uop_br_tag;\t// @[core.scala:182:20]\n reg [4:0] brinfos_1_uop_ftq_idx;\t// @[core.scala:182:20]\n reg brinfos_1_uop_edge_inst;\t// @[core.scala:182:20]\n reg [5:0] brinfos_1_uop_pc_lob;\t// @[core.scala:182:20]\n reg brinfos_1_uop_taken;\t// @[core.scala:182:20]\n reg [19:0] brinfos_1_uop_imm_packed;\t// @[core.scala:182:20]\n reg [11:0] brinfos_1_uop_csr_addr;\t// @[core.scala:182:20]\n reg [6:0] brinfos_1_uop_rob_idx;\t// @[core.scala:182:20]\n reg [4:0] brinfos_1_uop_ldq_idx;\t// @[core.scala:182:20]\n reg [4:0] brinfos_1_uop_stq_idx;\t// @[core.scala:182:20]\n reg [1:0] brinfos_1_uop_rxq_idx;\t// @[core.scala:182:20]\n reg [6:0] brinfos_1_uop_pdst;\t// @[core.scala:182:20]\n reg [6:0] brinfos_1_uop_prs1;\t// @[core.scala:182:20]\n reg [6:0] brinfos_1_uop_prs2;\t// @[core.scala:182:20]\n reg [6:0] brinfos_1_uop_prs3;\t// @[core.scala:182:20]\n reg [4:0] brinfos_1_uop_ppred;\t// @[core.scala:182:20]\n reg brinfos_1_uop_prs1_busy;\t// @[core.scala:182:20]\n reg brinfos_1_uop_prs2_busy;\t// @[core.scala:182:20]\n reg brinfos_1_uop_prs3_busy;\t// @[core.scala:182:20]\n reg brinfos_1_uop_ppred_busy;\t// @[core.scala:182:20]\n reg [6:0] brinfos_1_uop_stale_pdst;\t// @[core.scala:182:20]\n reg brinfos_1_uop_exception;\t// @[core.scala:182:20]\n reg [63:0] brinfos_1_uop_exc_cause;\t// @[core.scala:182:20]\n reg brinfos_1_uop_bypassable;\t// @[core.scala:182:20]\n reg [4:0] brinfos_1_uop_mem_cmd;\t// @[core.scala:182:20]\n reg [1:0] brinfos_1_uop_mem_size;\t// @[core.scala:182:20]\n reg brinfos_1_uop_mem_signed;\t// @[core.scala:182:20]\n reg brinfos_1_uop_is_fence;\t// @[core.scala:182:20]\n reg brinfos_1_uop_is_fencei;\t// @[core.scala:182:20]\n reg brinfos_1_uop_is_amo;\t// @[core.scala:182:20]\n reg brinfos_1_uop_uses_ldq;\t// @[core.scala:182:20]\n reg brinfos_1_uop_uses_stq;\t// @[core.scala:182:20]\n reg brinfos_1_uop_is_sys_pc2epc;\t// @[core.scala:182:20]\n reg brinfos_1_uop_is_unique;\t// @[core.scala:182:20]\n reg brinfos_1_uop_flush_on_commit;\t// @[core.scala:182:20]\n reg brinfos_1_uop_ldst_is_rs1;\t// @[core.scala:182:20]\n reg [5:0] brinfos_1_uop_ldst;\t// @[core.scala:182:20]\n reg [5:0] brinfos_1_uop_lrs1;\t// @[core.scala:182:20]\n reg [5:0] brinfos_1_uop_lrs2;\t// @[core.scala:182:20]\n reg [5:0] brinfos_1_uop_lrs3;\t// @[core.scala:182:20]\n reg brinfos_1_uop_ldst_val;\t// @[core.scala:182:20]\n reg [1:0] brinfos_1_uop_dst_rtype;\t// @[core.scala:182:20]\n reg [1:0] brinfos_1_uop_lrs1_rtype;\t// @[core.scala:182:20]\n reg [1:0] brinfos_1_uop_lrs2_rtype;\t// @[core.scala:182:20]\n reg brinfos_1_uop_frs3_en;\t// @[core.scala:182:20]\n reg brinfos_1_uop_fp_val;\t// @[core.scala:182:20]\n reg brinfos_1_uop_fp_single;\t// @[core.scala:182:20]\n reg brinfos_1_uop_xcpt_pf_if;\t// @[core.scala:182:20]\n reg brinfos_1_uop_xcpt_ae_if;\t// @[core.scala:182:20]\n reg brinfos_1_uop_xcpt_ma_if;\t// @[core.scala:182:20]\n reg brinfos_1_uop_bp_debug_if;\t// @[core.scala:182:20]\n reg brinfos_1_uop_bp_xcpt_if;\t// @[core.scala:182:20]\n reg [1:0] brinfos_1_uop_debug_fsrc;\t// @[core.scala:182:20]\n reg [1:0] brinfos_1_uop_debug_tsrc;\t// @[core.scala:182:20]\n reg brinfos_1_valid;\t// @[core.scala:182:20]\n reg brinfos_1_mispredict;\t// @[core.scala:182:20]\n reg brinfos_1_taken;\t// @[core.scala:182:20]\n reg [2:0] brinfos_1_cfi_type;\t// @[core.scala:182:20]\n reg [1:0] brinfos_1_pc_sel;\t// @[core.scala:182:20]\n reg [20:0] brinfos_1_target_offset;\t// @[core.scala:182:20]\n reg [6:0] brinfos_2_uop_uopc;\t// @[core.scala:182:20]\n reg [31:0] brinfos_2_uop_inst;\t// @[core.scala:182:20]\n reg [31:0] brinfos_2_uop_debug_inst;\t// @[core.scala:182:20]\n reg brinfos_2_uop_is_rvc;\t// @[core.scala:182:20]\n reg [39:0] brinfos_2_uop_debug_pc;\t// @[core.scala:182:20]\n reg [2:0] brinfos_2_uop_iq_type;\t// @[core.scala:182:20]\n reg [9:0] brinfos_2_uop_fu_code;\t// @[core.scala:182:20]\n reg [3:0] brinfos_2_uop_ctrl_br_type;\t// @[core.scala:182:20]\n reg [1:0] brinfos_2_uop_ctrl_op1_sel;\t// @[core.scala:182:20]\n reg [2:0] brinfos_2_uop_ctrl_op2_sel;\t// @[core.scala:182:20]\n reg [2:0] brinfos_2_uop_ctrl_imm_sel;\t// @[core.scala:182:20]\n reg [4:0] brinfos_2_uop_ctrl_op_fcn;\t// @[core.scala:182:20]\n reg brinfos_2_uop_ctrl_fcn_dw;\t// @[core.scala:182:20]\n reg [2:0] brinfos_2_uop_ctrl_csr_cmd;\t// @[core.scala:182:20]\n reg brinfos_2_uop_ctrl_is_load;\t// @[core.scala:182:20]\n reg brinfos_2_uop_ctrl_is_sta;\t// @[core.scala:182:20]\n reg brinfos_2_uop_ctrl_is_std;\t// @[core.scala:182:20]\n reg [1:0] brinfos_2_uop_iw_state;\t// @[core.scala:182:20]\n reg brinfos_2_uop_iw_p1_poisoned;\t// @[core.scala:182:20]\n reg brinfos_2_uop_iw_p2_poisoned;\t// @[core.scala:182:20]\n reg brinfos_2_uop_is_br;\t// @[core.scala:182:20]\n reg brinfos_2_uop_is_jalr;\t// @[core.scala:182:20]\n reg brinfos_2_uop_is_jal;\t// @[core.scala:182:20]\n reg brinfos_2_uop_is_sfb;\t// @[core.scala:182:20]\n reg [15:0] brinfos_2_uop_br_mask;\t// @[core.scala:182:20]\n reg [3:0] brinfos_2_uop_br_tag;\t// @[core.scala:182:20]\n reg [4:0] brinfos_2_uop_ftq_idx;\t// @[core.scala:182:20]\n reg brinfos_2_uop_edge_inst;\t// @[core.scala:182:20]\n reg [5:0] brinfos_2_uop_pc_lob;\t// @[core.scala:182:20]\n reg brinfos_2_uop_taken;\t// @[core.scala:182:20]\n reg [19:0] brinfos_2_uop_imm_packed;\t// @[core.scala:182:20]\n reg [11:0] brinfos_2_uop_csr_addr;\t// @[core.scala:182:20]\n reg [6:0] brinfos_2_uop_rob_idx;\t// @[core.scala:182:20]\n reg [4:0] brinfos_2_uop_ldq_idx;\t// @[core.scala:182:20]\n reg [4:0] brinfos_2_uop_stq_idx;\t// @[core.scala:182:20]\n reg [1:0] brinfos_2_uop_rxq_idx;\t// @[core.scala:182:20]\n reg [6:0] brinfos_2_uop_pdst;\t// @[core.scala:182:20]\n reg [6:0] brinfos_2_uop_prs1;\t// @[core.scala:182:20]\n reg [6:0] brinfos_2_uop_prs2;\t// @[core.scala:182:20]\n reg [6:0] brinfos_2_uop_prs3;\t// @[core.scala:182:20]\n reg [4:0] brinfos_2_uop_ppred;\t// @[core.scala:182:20]\n reg brinfos_2_uop_prs1_busy;\t// @[core.scala:182:20]\n reg brinfos_2_uop_prs2_busy;\t// @[core.scala:182:20]\n reg brinfos_2_uop_prs3_busy;\t// @[core.scala:182:20]\n reg brinfos_2_uop_ppred_busy;\t// @[core.scala:182:20]\n reg [6:0] brinfos_2_uop_stale_pdst;\t// @[core.scala:182:20]\n reg brinfos_2_uop_exception;\t// @[core.scala:182:20]\n reg [63:0] brinfos_2_uop_exc_cause;\t// @[core.scala:182:20]\n reg brinfos_2_uop_bypassable;\t// @[core.scala:182:20]\n reg [4:0] brinfos_2_uop_mem_cmd;\t// @[core.scala:182:20]\n reg [1:0] brinfos_2_uop_mem_size;\t// @[core.scala:182:20]\n reg brinfos_2_uop_mem_signed;\t// @[core.scala:182:20]\n reg brinfos_2_uop_is_fence;\t// @[core.scala:182:20]\n reg brinfos_2_uop_is_fencei;\t// @[core.scala:182:20]\n reg brinfos_2_uop_is_amo;\t// @[core.scala:182:20]\n reg brinfos_2_uop_uses_ldq;\t// @[core.scala:182:20]\n reg brinfos_2_uop_uses_stq;\t// @[core.scala:182:20]\n reg brinfos_2_uop_is_sys_pc2epc;\t// @[core.scala:182:20]\n reg brinfos_2_uop_is_unique;\t// @[core.scala:182:20]\n reg brinfos_2_uop_flush_on_commit;\t// @[core.scala:182:20]\n reg brinfos_2_uop_ldst_is_rs1;\t// @[core.scala:182:20]\n reg [5:0] brinfos_2_uop_ldst;\t// @[core.scala:182:20]\n reg [5:0] brinfos_2_uop_lrs1;\t// @[core.scala:182:20]\n reg [5:0] brinfos_2_uop_lrs2;\t// @[core.scala:182:20]\n reg [5:0] brinfos_2_uop_lrs3;\t// @[core.scala:182:20]\n reg brinfos_2_uop_ldst_val;\t// @[core.scala:182:20]\n reg [1:0] brinfos_2_uop_dst_rtype;\t// @[core.scala:182:20]\n reg [1:0] brinfos_2_uop_lrs1_rtype;\t// @[core.scala:182:20]\n reg [1:0] brinfos_2_uop_lrs2_rtype;\t// @[core.scala:182:20]\n reg brinfos_2_uop_frs3_en;\t// @[core.scala:182:20]\n reg brinfos_2_uop_fp_val;\t// @[core.scala:182:20]\n reg brinfos_2_uop_fp_single;\t// @[core.scala:182:20]\n reg brinfos_2_uop_xcpt_pf_if;\t// @[core.scala:182:20]\n reg brinfos_2_uop_xcpt_ae_if;\t// @[core.scala:182:20]\n reg brinfos_2_uop_xcpt_ma_if;\t// @[core.scala:182:20]\n reg brinfos_2_uop_bp_debug_if;\t// @[core.scala:182:20]\n reg brinfos_2_uop_bp_xcpt_if;\t// @[core.scala:182:20]\n reg [1:0] brinfos_2_uop_debug_fsrc;\t// @[core.scala:182:20]\n reg [1:0] brinfos_2_uop_debug_tsrc;\t// @[core.scala:182:20]\n reg brinfos_2_valid;\t// @[core.scala:182:20]\n reg brinfos_2_mispredict;\t// @[core.scala:182:20]\n reg brinfos_2_taken;\t// @[core.scala:182:20]\n reg [2:0] brinfos_2_cfi_type;\t// @[core.scala:182:20]\n reg [1:0] brinfos_2_pc_sel;\t// @[core.scala:182:20]\n reg [20:0] brinfos_2_target_offset;\t// @[core.scala:182:20]\n wire [15:0] b1_resolve_mask;\t// @[core.scala:189:19]\n assign io_ifu_brupdate_b1_resolve_mask_0 = brupdate_b1_resolve_mask;\t// @[core.scala:51:7, :188:23]\n assign io_lsu_brupdate_b1_resolve_mask_0 = brupdate_b1_resolve_mask;\t// @[core.scala:51:7, :188:23]\n wire [15:0] b1_mispredict_mask;\t// @[core.scala:189:19]\n assign io_ifu_brupdate_b1_mispredict_mask_0 = brupdate_b1_mispredict_mask;\t// @[core.scala:51:7, :188:23]\n assign io_lsu_brupdate_b1_mispredict_mask_0 = brupdate_b1_mispredict_mask;\t// @[core.scala:51:7, :188:23]\n assign io_ifu_brupdate_b2_uop_uopc_0 = brupdate_b2_uop_uopc;\t// @[core.scala:51:7, :188:23]\n assign io_lsu_brupdate_b2_uop_uopc_0 = brupdate_b2_uop_uopc;\t// @[core.scala:51:7, :188:23]\n assign io_ifu_brupdate_b2_uop_inst_0 = brupdate_b2_uop_inst;\t// @[core.scala:51:7, :188:23]\n assign io_lsu_brupdate_b2_uop_inst_0 = brupdate_b2_uop_inst;\t// @[core.scala:51:7, :188:23]\n assign io_ifu_brupdate_b2_uop_debug_inst_0 = brupdate_b2_uop_debug_inst;\t// @[core.scala:51:7, :188:23]\n assign io_lsu_brupdate_b2_uop_debug_inst_0 = brupdate_b2_uop_debug_inst;\t// @[core.scala:51:7, :188:23]\n assign io_ifu_brupdate_b2_uop_is_rvc_0 = brupdate_b2_uop_is_rvc;\t// @[core.scala:51:7, :188:23]\n assign io_lsu_brupdate_b2_uop_is_rvc_0 = brupdate_b2_uop_is_rvc;\t// @[core.scala:51:7, :188:23]\n assign io_ifu_brupdate_b2_uop_debug_pc_0 = brupdate_b2_uop_debug_pc;\t// @[core.scala:51:7, :188:23]\n assign io_lsu_brupdate_b2_uop_debug_pc_0 = brupdate_b2_uop_debug_pc;\t// @[core.scala:51:7, :188:23]\n assign io_ifu_brupdate_b2_uop_iq_type_0 = brupdate_b2_uop_iq_type;\t// @[core.scala:51:7, :188:23]\n assign io_lsu_brupdate_b2_uop_iq_type_0 = brupdate_b2_uop_iq_type;\t// @[core.scala:51:7, :188:23]\n assign io_ifu_brupdate_b2_uop_fu_code_0 = brupdate_b2_uop_fu_code;\t// @[core.scala:51:7, :188:23]\n assign io_lsu_brupdate_b2_uop_fu_code_0 = brupdate_b2_uop_fu_code;\t// @[core.scala:51:7, :188:23]\n assign io_ifu_brupdate_b2_uop_ctrl_br_type_0 = brupdate_b2_uop_ctrl_br_type;\t// @[core.scala:51:7, :188:23]\n assign io_lsu_brupdate_b2_uop_ctrl_br_type_0 = brupdate_b2_uop_ctrl_br_type;\t// @[core.scala:51:7, :188:23]\n assign io_ifu_brupdate_b2_uop_ctrl_op1_sel_0 = brupdate_b2_uop_ctrl_op1_sel;\t// @[core.scala:51:7, :188:23]\n assign io_lsu_brupdate_b2_uop_ctrl_op1_sel_0 = brupdate_b2_uop_ctrl_op1_sel;\t// @[core.scala:51:7, :188:23]\n assign io_ifu_brupdate_b2_uop_ctrl_op2_sel_0 = brupdate_b2_uop_ctrl_op2_sel;\t// @[core.scala:51:7, :188:23]\n assign io_lsu_brupdate_b2_uop_ctrl_op2_sel_0 = brupdate_b2_uop_ctrl_op2_sel;\t// @[core.scala:51:7, :188:23]\n assign io_ifu_brupdate_b2_uop_ctrl_imm_sel_0 = brupdate_b2_uop_ctrl_imm_sel;\t// @[core.scala:51:7, :188:23]\n assign io_lsu_brupdate_b2_uop_ctrl_imm_sel_0 = brupdate_b2_uop_ctrl_imm_sel;\t// @[core.scala:51:7, :188:23]\n assign io_ifu_brupdate_b2_uop_ctrl_op_fcn_0 = brupdate_b2_uop_ctrl_op_fcn;\t// @[core.scala:51:7, :188:23]\n assign io_lsu_brupdate_b2_uop_ctrl_op_fcn_0 = brupdate_b2_uop_ctrl_op_fcn;\t// @[core.scala:51:7, :188:23]\n assign io_ifu_brupdate_b2_uop_ctrl_fcn_dw_0 = brupdate_b2_uop_ctrl_fcn_dw;\t// @[core.scala:51:7, :188:23]\n assign io_lsu_brupdate_b2_uop_ctrl_fcn_dw_0 = brupdate_b2_uop_ctrl_fcn_dw;\t// @[core.scala:51:7, :188:23]\n assign io_ifu_brupdate_b2_uop_ctrl_csr_cmd_0 = brupdate_b2_uop_ctrl_csr_cmd;\t// @[core.scala:51:7, :188:23]\n assign io_lsu_brupdate_b2_uop_ctrl_csr_cmd_0 = brupdate_b2_uop_ctrl_csr_cmd;\t// @[core.scala:51:7, :188:23]\n assign io_ifu_brupdate_b2_uop_ctrl_is_load_0 = brupdate_b2_uop_ctrl_is_load;\t// @[core.scala:51:7, :188:23]\n assign io_lsu_brupdate_b2_uop_ctrl_is_load_0 = brupdate_b2_uop_ctrl_is_load;\t// @[core.scala:51:7, :188:23]\n assign io_ifu_brupdate_b2_uop_ctrl_is_sta_0 = brupdate_b2_uop_ctrl_is_sta;\t// @[core.scala:51:7, :188:23]\n assign io_lsu_brupdate_b2_uop_ctrl_is_sta_0 = brupdate_b2_uop_ctrl_is_sta;\t// @[core.scala:51:7, :188:23]\n assign io_ifu_brupdate_b2_uop_ctrl_is_std_0 = brupdate_b2_uop_ctrl_is_std;\t// @[core.scala:51:7, :188:23]\n assign io_lsu_brupdate_b2_uop_ctrl_is_std_0 = brupdate_b2_uop_ctrl_is_std;\t// @[core.scala:51:7, :188:23]\n assign io_ifu_brupdate_b2_uop_iw_state_0 = brupdate_b2_uop_iw_state;\t// @[core.scala:51:7, :188:23]\n assign io_lsu_brupdate_b2_uop_iw_state_0 = brupdate_b2_uop_iw_state;\t// @[core.scala:51:7, :188:23]\n assign io_ifu_brupdate_b2_uop_iw_p1_poisoned_0 = brupdate_b2_uop_iw_p1_poisoned;\t// @[core.scala:51:7, :188:23]\n assign io_lsu_brupdate_b2_uop_iw_p1_poisoned_0 = brupdate_b2_uop_iw_p1_poisoned;\t// @[core.scala:51:7, :188:23]\n assign io_ifu_brupdate_b2_uop_iw_p2_poisoned_0 = brupdate_b2_uop_iw_p2_poisoned;\t// @[core.scala:51:7, :188:23]\n assign io_lsu_brupdate_b2_uop_iw_p2_poisoned_0 = brupdate_b2_uop_iw_p2_poisoned;\t// @[core.scala:51:7, :188:23]\n assign io_ifu_brupdate_b2_uop_is_br_0 = brupdate_b2_uop_is_br;\t// @[core.scala:51:7, :188:23]\n assign io_lsu_brupdate_b2_uop_is_br_0 = brupdate_b2_uop_is_br;\t// @[core.scala:51:7, :188:23]\n assign io_ifu_brupdate_b2_uop_is_jalr_0 = brupdate_b2_uop_is_jalr;\t// @[core.scala:51:7, :188:23]\n assign io_lsu_brupdate_b2_uop_is_jalr_0 = brupdate_b2_uop_is_jalr;\t// @[core.scala:51:7, :188:23]\n assign io_ifu_brupdate_b2_uop_is_jal_0 = brupdate_b2_uop_is_jal;\t// @[core.scala:51:7, :188:23]\n assign io_lsu_brupdate_b2_uop_is_jal_0 = brupdate_b2_uop_is_jal;\t// @[core.scala:51:7, :188:23]\n assign io_ifu_brupdate_b2_uop_is_sfb_0 = brupdate_b2_uop_is_sfb;\t// @[core.scala:51:7, :188:23]\n assign io_lsu_brupdate_b2_uop_is_sfb_0 = brupdate_b2_uop_is_sfb;\t// @[core.scala:51:7, :188:23]\n assign io_ifu_brupdate_b2_uop_br_mask_0 = brupdate_b2_uop_br_mask;\t// @[core.scala:51:7, :188:23]\n assign io_lsu_brupdate_b2_uop_br_mask_0 = brupdate_b2_uop_br_mask;\t// @[core.scala:51:7, :188:23]\n assign io_ifu_brupdate_b2_uop_br_tag_0 = brupdate_b2_uop_br_tag;\t// @[core.scala:51:7, :188:23]\n assign io_lsu_brupdate_b2_uop_br_tag_0 = brupdate_b2_uop_br_tag;\t// @[core.scala:51:7, :188:23]\n assign io_ifu_brupdate_b2_uop_ftq_idx_0 = brupdate_b2_uop_ftq_idx;\t// @[core.scala:51:7, :188:23]\n assign io_lsu_brupdate_b2_uop_ftq_idx_0 = brupdate_b2_uop_ftq_idx;\t// @[core.scala:51:7, :188:23]\n assign io_ifu_brupdate_b2_uop_edge_inst_0 = brupdate_b2_uop_edge_inst;\t// @[core.scala:51:7, :188:23]\n assign io_lsu_brupdate_b2_uop_edge_inst_0 = brupdate_b2_uop_edge_inst;\t// @[core.scala:51:7, :188:23]\n assign io_ifu_brupdate_b2_uop_pc_lob_0 = brupdate_b2_uop_pc_lob;\t// @[core.scala:51:7, :188:23]\n assign io_lsu_brupdate_b2_uop_pc_lob_0 = brupdate_b2_uop_pc_lob;\t// @[core.scala:51:7, :188:23]\n assign io_ifu_brupdate_b2_uop_taken_0 = brupdate_b2_uop_taken;\t// @[core.scala:51:7, :188:23]\n assign io_lsu_brupdate_b2_uop_taken_0 = brupdate_b2_uop_taken;\t// @[core.scala:51:7, :188:23]\n assign io_ifu_brupdate_b2_uop_imm_packed_0 = brupdate_b2_uop_imm_packed;\t// @[core.scala:51:7, :188:23]\n assign io_lsu_brupdate_b2_uop_imm_packed_0 = brupdate_b2_uop_imm_packed;\t// @[core.scala:51:7, :188:23]\n assign io_ifu_brupdate_b2_uop_csr_addr_0 = brupdate_b2_uop_csr_addr;\t// @[core.scala:51:7, :188:23]\n assign io_lsu_brupdate_b2_uop_csr_addr_0 = brupdate_b2_uop_csr_addr;\t// @[core.scala:51:7, :188:23]\n assign io_ifu_brupdate_b2_uop_rob_idx_0 = brupdate_b2_uop_rob_idx;\t// @[core.scala:51:7, :188:23]\n assign io_lsu_brupdate_b2_uop_rob_idx_0 = brupdate_b2_uop_rob_idx;\t// @[core.scala:51:7, :188:23]\n assign io_ifu_brupdate_b2_uop_ldq_idx_0 = brupdate_b2_uop_ldq_idx;\t// @[core.scala:51:7, :188:23]\n assign io_lsu_brupdate_b2_uop_ldq_idx_0 = brupdate_b2_uop_ldq_idx;\t// @[core.scala:51:7, :188:23]\n assign io_ifu_brupdate_b2_uop_stq_idx_0 = brupdate_b2_uop_stq_idx;\t// @[core.scala:51:7, :188:23]\n assign io_lsu_brupdate_b2_uop_stq_idx_0 = brupdate_b2_uop_stq_idx;\t// @[core.scala:51:7, :188:23]\n assign io_ifu_brupdate_b2_uop_rxq_idx_0 = brupdate_b2_uop_rxq_idx;\t// @[core.scala:51:7, :188:23]\n assign io_lsu_brupdate_b2_uop_rxq_idx_0 = brupdate_b2_uop_rxq_idx;\t// @[core.scala:51:7, :188:23]\n assign io_ifu_brupdate_b2_uop_pdst_0 = brupdate_b2_uop_pdst;\t// @[core.scala:51:7, :188:23]\n assign io_lsu_brupdate_b2_uop_pdst_0 = brupdate_b2_uop_pdst;\t// @[core.scala:51:7, :188:23]\n assign io_ifu_brupdate_b2_uop_prs1_0 = brupdate_b2_uop_prs1;\t// @[core.scala:51:7, :188:23]\n assign io_lsu_brupdate_b2_uop_prs1_0 = brupdate_b2_uop_prs1;\t// @[core.scala:51:7, :188:23]\n assign io_ifu_brupdate_b2_uop_prs2_0 = brupdate_b2_uop_prs2;\t// @[core.scala:51:7, :188:23]\n assign io_lsu_brupdate_b2_uop_prs2_0 = brupdate_b2_uop_prs2;\t// @[core.scala:51:7, :188:23]\n assign io_ifu_brupdate_b2_uop_prs3_0 = brupdate_b2_uop_prs3;\t// @[core.scala:51:7, :188:23]\n assign io_lsu_brupdate_b2_uop_prs3_0 = brupdate_b2_uop_prs3;\t// @[core.scala:51:7, :188:23]\n assign io_ifu_brupdate_b2_uop_ppred_0 = brupdate_b2_uop_ppred;\t// @[core.scala:51:7, :188:23]\n assign io_lsu_brupdate_b2_uop_ppred_0 = brupdate_b2_uop_ppred;\t// @[core.scala:51:7, :188:23]\n assign io_ifu_brupdate_b2_uop_prs1_busy_0 = brupdate_b2_uop_prs1_busy;\t// @[core.scala:51:7, :188:23]\n assign io_lsu_brupdate_b2_uop_prs1_busy_0 = brupdate_b2_uop_prs1_busy;\t// @[core.scala:51:7, :188:23]\n assign io_ifu_brupdate_b2_uop_prs2_busy_0 = brupdate_b2_uop_prs2_busy;\t// @[core.scala:51:7, :188:23]\n assign io_lsu_brupdate_b2_uop_prs2_busy_0 = brupdate_b2_uop_prs2_busy;\t// @[core.scala:51:7, :188:23]\n assign io_ifu_brupdate_b2_uop_prs3_busy_0 = brupdate_b2_uop_prs3_busy;\t// @[core.scala:51:7, :188:23]\n assign io_lsu_brupdate_b2_uop_prs3_busy_0 = brupdate_b2_uop_prs3_busy;\t// @[core.scala:51:7, :188:23]\n assign io_ifu_brupdate_b2_uop_ppred_busy_0 = brupdate_b2_uop_ppred_busy;\t// @[core.scala:51:7, :188:23]\n assign io_lsu_brupdate_b2_uop_ppred_busy_0 = brupdate_b2_uop_ppred_busy;\t// @[core.scala:51:7, :188:23]\n assign io_ifu_brupdate_b2_uop_stale_pdst_0 = brupdate_b2_uop_stale_pdst;\t// @[core.scala:51:7, :188:23]\n assign io_lsu_brupdate_b2_uop_stale_pdst_0 = brupdate_b2_uop_stale_pdst;\t// @[core.scala:51:7, :188:23]\n assign io_ifu_brupdate_b2_uop_exception_0 = brupdate_b2_uop_exception;\t// @[core.scala:51:7, :188:23]\n assign io_lsu_brupdate_b2_uop_exception_0 = brupdate_b2_uop_exception;\t// @[core.scala:51:7, :188:23]\n assign io_ifu_brupdate_b2_uop_exc_cause_0 = brupdate_b2_uop_exc_cause;\t// @[core.scala:51:7, :188:23]\n assign io_lsu_brupdate_b2_uop_exc_cause_0 = brupdate_b2_uop_exc_cause;\t// @[core.scala:51:7, :188:23]\n assign io_ifu_brupdate_b2_uop_bypassable_0 = brupdate_b2_uop_bypassable;\t// @[core.scala:51:7, :188:23]\n assign io_lsu_brupdate_b2_uop_bypassable_0 = brupdate_b2_uop_bypassable;\t// @[core.scala:51:7, :188:23]\n assign io_ifu_brupdate_b2_uop_mem_cmd_0 = brupdate_b2_uop_mem_cmd;\t// @[core.scala:51:7, :188:23]\n assign io_lsu_brupdate_b2_uop_mem_cmd_0 = brupdate_b2_uop_mem_cmd;\t// @[core.scala:51:7, :188:23]\n assign io_ifu_brupdate_b2_uop_mem_size_0 = brupdate_b2_uop_mem_size;\t// @[core.scala:51:7, :188:23]\n assign io_lsu_brupdate_b2_uop_mem_size_0 = brupdate_b2_uop_mem_size;\t// @[core.scala:51:7, :188:23]\n assign io_ifu_brupdate_b2_uop_mem_signed_0 = brupdate_b2_uop_mem_signed;\t// @[core.scala:51:7, :188:23]\n assign io_lsu_brupdate_b2_uop_mem_signed_0 = brupdate_b2_uop_mem_signed;\t// @[core.scala:51:7, :188:23]\n assign io_ifu_brupdate_b2_uop_is_fence_0 = brupdate_b2_uop_is_fence;\t// @[core.scala:51:7, :188:23]\n assign io_lsu_brupdate_b2_uop_is_fence_0 = brupdate_b2_uop_is_fence;\t// @[core.scala:51:7, :188:23]\n assign io_ifu_brupdate_b2_uop_is_fencei_0 = brupdate_b2_uop_is_fencei;\t// @[core.scala:51:7, :188:23]\n assign io_lsu_brupdate_b2_uop_is_fencei_0 = brupdate_b2_uop_is_fencei;\t// @[core.scala:51:7, :188:23]\n assign io_ifu_brupdate_b2_uop_is_amo_0 = brupdate_b2_uop_is_amo;\t// @[core.scala:51:7, :188:23]\n assign io_lsu_brupdate_b2_uop_is_amo_0 = brupdate_b2_uop_is_amo;\t// @[core.scala:51:7, :188:23]\n assign io_ifu_brupdate_b2_uop_uses_ldq_0 = brupdate_b2_uop_uses_ldq;\t// @[core.scala:51:7, :188:23]\n assign io_lsu_brupdate_b2_uop_uses_ldq_0 = brupdate_b2_uop_uses_ldq;\t// @[core.scala:51:7, :188:23]\n assign io_ifu_brupdate_b2_uop_uses_stq_0 = brupdate_b2_uop_uses_stq;\t// @[core.scala:51:7, :188:23]\n assign io_lsu_brupdate_b2_uop_uses_stq_0 = brupdate_b2_uop_uses_stq;\t// @[core.scala:51:7, :188:23]\n assign io_ifu_brupdate_b2_uop_is_sys_pc2epc_0 = brupdate_b2_uop_is_sys_pc2epc;\t// @[core.scala:51:7, :188:23]\n assign io_lsu_brupdate_b2_uop_is_sys_pc2epc_0 = brupdate_b2_uop_is_sys_pc2epc;\t// @[core.scala:51:7, :188:23]\n assign io_ifu_brupdate_b2_uop_is_unique_0 = brupdate_b2_uop_is_unique;\t// @[core.scala:51:7, :188:23]\n assign io_lsu_brupdate_b2_uop_is_unique_0 = brupdate_b2_uop_is_unique;\t// @[core.scala:51:7, :188:23]\n assign io_ifu_brupdate_b2_uop_flush_on_commit_0 = brupdate_b2_uop_flush_on_commit;\t// @[core.scala:51:7, :188:23]\n assign io_lsu_brupdate_b2_uop_flush_on_commit_0 = brupdate_b2_uop_flush_on_commit;\t// @[core.scala:51:7, :188:23]\n assign io_ifu_brupdate_b2_uop_ldst_is_rs1_0 = brupdate_b2_uop_ldst_is_rs1;\t// @[core.scala:51:7, :188:23]\n assign io_lsu_brupdate_b2_uop_ldst_is_rs1_0 = brupdate_b2_uop_ldst_is_rs1;\t// @[core.scala:51:7, :188:23]\n assign io_ifu_brupdate_b2_uop_ldst_0 = brupdate_b2_uop_ldst;\t// @[core.scala:51:7, :188:23]\n assign io_lsu_brupdate_b2_uop_ldst_0 = brupdate_b2_uop_ldst;\t// @[core.scala:51:7, :188:23]\n assign io_ifu_brupdate_b2_uop_lrs1_0 = brupdate_b2_uop_lrs1;\t// @[core.scala:51:7, :188:23]\n assign io_lsu_brupdate_b2_uop_lrs1_0 = brupdate_b2_uop_lrs1;\t// @[core.scala:51:7, :188:23]\n assign io_ifu_brupdate_b2_uop_lrs2_0 = brupdate_b2_uop_lrs2;\t// @[core.scala:51:7, :188:23]\n assign io_lsu_brupdate_b2_uop_lrs2_0 = brupdate_b2_uop_lrs2;\t// @[core.scala:51:7, :188:23]\n assign io_ifu_brupdate_b2_uop_lrs3_0 = brupdate_b2_uop_lrs3;\t// @[core.scala:51:7, :188:23]\n assign io_lsu_brupdate_b2_uop_lrs3_0 = brupdate_b2_uop_lrs3;\t// @[core.scala:51:7, :188:23]\n assign io_ifu_brupdate_b2_uop_ldst_val_0 = brupdate_b2_uop_ldst_val;\t// @[core.scala:51:7, :188:23]\n assign io_lsu_brupdate_b2_uop_ldst_val_0 = brupdate_b2_uop_ldst_val;\t// @[core.scala:51:7, :188:23]\n assign io_ifu_brupdate_b2_uop_dst_rtype_0 = brupdate_b2_uop_dst_rtype;\t// @[core.scala:51:7, :188:23]\n assign io_lsu_brupdate_b2_uop_dst_rtype_0 = brupdate_b2_uop_dst_rtype;\t// @[core.scala:51:7, :188:23]\n assign io_ifu_brupdate_b2_uop_lrs1_rtype_0 = brupdate_b2_uop_lrs1_rtype;\t// @[core.scala:51:7, :188:23]\n assign io_lsu_brupdate_b2_uop_lrs1_rtype_0 = brupdate_b2_uop_lrs1_rtype;\t// @[core.scala:51:7, :188:23]\n assign io_ifu_brupdate_b2_uop_lrs2_rtype_0 = brupdate_b2_uop_lrs2_rtype;\t// @[core.scala:51:7, :188:23]\n assign io_lsu_brupdate_b2_uop_lrs2_rtype_0 = brupdate_b2_uop_lrs2_rtype;\t// @[core.scala:51:7, :188:23]\n assign io_ifu_brupdate_b2_uop_frs3_en_0 = brupdate_b2_uop_frs3_en;\t// @[core.scala:51:7, :188:23]\n assign io_lsu_brupdate_b2_uop_frs3_en_0 = brupdate_b2_uop_frs3_en;\t// @[core.scala:51:7, :188:23]\n assign io_ifu_brupdate_b2_uop_fp_val_0 = brupdate_b2_uop_fp_val;\t// @[core.scala:51:7, :188:23]\n assign io_lsu_brupdate_b2_uop_fp_val_0 = brupdate_b2_uop_fp_val;\t// @[core.scala:51:7, :188:23]\n assign io_ifu_brupdate_b2_uop_fp_single_0 = brupdate_b2_uop_fp_single;\t// @[core.scala:51:7, :188:23]\n assign io_lsu_brupdate_b2_uop_fp_single_0 = brupdate_b2_uop_fp_single;\t// @[core.scala:51:7, :188:23]\n assign io_ifu_brupdate_b2_uop_xcpt_pf_if_0 = brupdate_b2_uop_xcpt_pf_if;\t// @[core.scala:51:7, :188:23]\n assign io_lsu_brupdate_b2_uop_xcpt_pf_if_0 = brupdate_b2_uop_xcpt_pf_if;\t// @[core.scala:51:7, :188:23]\n assign io_ifu_brupdate_b2_uop_xcpt_ae_if_0 = brupdate_b2_uop_xcpt_ae_if;\t// @[core.scala:51:7, :188:23]\n assign io_lsu_brupdate_b2_uop_xcpt_ae_if_0 = brupdate_b2_uop_xcpt_ae_if;\t// @[core.scala:51:7, :188:23]\n assign io_ifu_brupdate_b2_uop_xcpt_ma_if_0 = brupdate_b2_uop_xcpt_ma_if;\t// @[core.scala:51:7, :188:23]\n assign io_lsu_brupdate_b2_uop_xcpt_ma_if_0 = brupdate_b2_uop_xcpt_ma_if;\t// @[core.scala:51:7, :188:23]\n assign io_ifu_brupdate_b2_uop_bp_debug_if_0 = brupdate_b2_uop_bp_debug_if;\t// @[core.scala:51:7, :188:23]\n assign io_lsu_brupdate_b2_uop_bp_debug_if_0 = brupdate_b2_uop_bp_debug_if;\t// @[core.scala:51:7, :188:23]\n assign io_ifu_brupdate_b2_uop_bp_xcpt_if_0 = brupdate_b2_uop_bp_xcpt_if;\t// @[core.scala:51:7, :188:23]\n assign io_lsu_brupdate_b2_uop_bp_xcpt_if_0 = brupdate_b2_uop_bp_xcpt_if;\t// @[core.scala:51:7, :188:23]\n assign io_ifu_brupdate_b2_uop_debug_fsrc_0 = brupdate_b2_uop_debug_fsrc;\t// @[core.scala:51:7, :188:23]\n assign io_lsu_brupdate_b2_uop_debug_fsrc_0 = brupdate_b2_uop_debug_fsrc;\t// @[core.scala:51:7, :188:23]\n assign io_ifu_brupdate_b2_uop_debug_tsrc_0 = brupdate_b2_uop_debug_tsrc;\t// @[core.scala:51:7, :188:23]\n assign io_lsu_brupdate_b2_uop_debug_tsrc_0 = brupdate_b2_uop_debug_tsrc;\t// @[core.scala:51:7, :188:23]\n assign io_ifu_brupdate_b2_valid_0 = brupdate_b2_valid;\t// @[core.scala:51:7, :188:23]\n assign io_lsu_brupdate_b2_valid_0 = brupdate_b2_valid;\t// @[core.scala:51:7, :188:23]\n assign io_ifu_brupdate_b2_mispredict_0 = brupdate_b2_mispredict;\t// @[core.scala:51:7, :188:23]\n assign io_lsu_brupdate_b2_mispredict_0 = brupdate_b2_mispredict;\t// @[core.scala:51:7, :188:23]\n assign io_ifu_brupdate_b2_taken_0 = brupdate_b2_taken;\t// @[core.scala:51:7, :188:23]\n assign io_lsu_brupdate_b2_taken_0 = brupdate_b2_taken;\t// @[core.scala:51:7, :188:23]\n wire _next_ghist_cfi_in_bank_0_T = brupdate_b2_taken;\t// @[frontend.scala:104:37]\n wire _next_ghist_new_history_new_saw_branch_taken_T_1 = brupdate_b2_taken;\t// @[frontend.scala:119:59]\n assign io_ifu_brupdate_b2_cfi_type_0 = brupdate_b2_cfi_type;\t// @[core.scala:51:7, :188:23]\n assign io_lsu_brupdate_b2_cfi_type_0 = brupdate_b2_cfi_type;\t// @[core.scala:51:7, :188:23]\n assign io_ifu_brupdate_b2_pc_sel_0 = brupdate_b2_pc_sel;\t// @[core.scala:51:7, :188:23]\n assign io_lsu_brupdate_b2_pc_sel_0 = brupdate_b2_pc_sel;\t// @[core.scala:51:7, :188:23]\n assign io_ifu_brupdate_b2_jalr_target_0 = brupdate_b2_jalr_target;\t// @[core.scala:51:7, :188:23]\n assign io_lsu_brupdate_b2_jalr_target_0 = brupdate_b2_jalr_target;\t// @[core.scala:51:7, :188:23]\n assign io_ifu_brupdate_b2_target_offset_0 = brupdate_b2_target_offset;\t// @[core.scala:51:7, :188:23]\n assign io_lsu_brupdate_b2_target_offset_0 = brupdate_b2_target_offset;\t// @[core.scala:51:7, :188:23]\n wire [15:0] _b1_resolve_mask_T_4;\t// @[core.scala:199:72]\n assign brupdate_b1_resolve_mask = b1_resolve_mask;\t// @[core.scala:188:23, :189:19]\n wire [15:0] _b1_mispredict_mask_T_7;\t// @[core.scala:200:93]\n assign brupdate_b1_mispredict_mask = b1_mispredict_mask;\t// @[core.scala:188:23, :189:19]\n reg [6:0] b2_uop_uopc;\t// @[core.scala:190:18]\n assign brupdate_b2_uop_uopc = b2_uop_uopc;\t// @[core.scala:188:23, :190:18]\n reg [31:0] b2_uop_inst;\t// @[core.scala:190:18]\n assign brupdate_b2_uop_inst = b2_uop_inst;\t// @[core.scala:188:23, :190:18]\n reg [31:0] b2_uop_debug_inst;\t// @[core.scala:190:18]\n assign brupdate_b2_uop_debug_inst = b2_uop_debug_inst;\t// @[core.scala:188:23, :190:18]\n reg b2_uop_is_rvc;\t// @[core.scala:190:18]\n assign brupdate_b2_uop_is_rvc = b2_uop_is_rvc;\t// @[core.scala:188:23, :190:18]\n reg [39:0] b2_uop_debug_pc;\t// @[core.scala:190:18]\n assign brupdate_b2_uop_debug_pc = b2_uop_debug_pc;\t// @[core.scala:188:23, :190:18]\n reg [2:0] b2_uop_iq_type;\t// @[core.scala:190:18]\n assign brupdate_b2_uop_iq_type = b2_uop_iq_type;\t// @[core.scala:188:23, :190:18]\n reg [9:0] b2_uop_fu_code;\t// @[core.scala:190:18]\n assign brupdate_b2_uop_fu_code = b2_uop_fu_code;\t// @[core.scala:188:23, :190:18]\n reg [3:0] b2_uop_ctrl_br_type;\t// @[core.scala:190:18]\n assign brupdate_b2_uop_ctrl_br_type = b2_uop_ctrl_br_type;\t// @[core.scala:188:23, :190:18]\n reg [1:0] b2_uop_ctrl_op1_sel;\t// @[core.scala:190:18]\n assign brupdate_b2_uop_ctrl_op1_sel = b2_uop_ctrl_op1_sel;\t// @[core.scala:188:23, :190:18]\n reg [2:0] b2_uop_ctrl_op2_sel;\t// @[core.scala:190:18]\n assign brupdate_b2_uop_ctrl_op2_sel = b2_uop_ctrl_op2_sel;\t// @[core.scala:188:23, :190:18]\n reg [2:0] b2_uop_ctrl_imm_sel;\t// @[core.scala:190:18]\n assign brupdate_b2_uop_ctrl_imm_sel = b2_uop_ctrl_imm_sel;\t// @[core.scala:188:23, :190:18]\n reg [4:0] b2_uop_ctrl_op_fcn;\t// @[core.scala:190:18]\n assign brupdate_b2_uop_ctrl_op_fcn = b2_uop_ctrl_op_fcn;\t// @[core.scala:188:23, :190:18]\n reg b2_uop_ctrl_fcn_dw;\t// @[core.scala:190:18]\n assign brupdate_b2_uop_ctrl_fcn_dw = b2_uop_ctrl_fcn_dw;\t// @[core.scala:188:23, :190:18]\n reg [2:0] b2_uop_ctrl_csr_cmd;\t// @[core.scala:190:18]\n assign brupdate_b2_uop_ctrl_csr_cmd = b2_uop_ctrl_csr_cmd;\t// @[core.scala:188:23, :190:18]\n reg b2_uop_ctrl_is_load;\t// @[core.scala:190:18]\n assign brupdate_b2_uop_ctrl_is_load = b2_uop_ctrl_is_load;\t// @[core.scala:188:23, :190:18]\n reg b2_uop_ctrl_is_sta;\t// @[core.scala:190:18]\n assign brupdate_b2_uop_ctrl_is_sta = b2_uop_ctrl_is_sta;\t// @[core.scala:188:23, :190:18]\n reg b2_uop_ctrl_is_std;\t// @[core.scala:190:18]\n assign brupdate_b2_uop_ctrl_is_std = b2_uop_ctrl_is_std;\t// @[core.scala:188:23, :190:18]\n reg [1:0] b2_uop_iw_state;\t// @[core.scala:190:18]\n assign brupdate_b2_uop_iw_state = b2_uop_iw_state;\t// @[core.scala:188:23, :190:18]\n reg b2_uop_iw_p1_poisoned;\t// @[core.scala:190:18]\n assign brupdate_b2_uop_iw_p1_poisoned = b2_uop_iw_p1_poisoned;\t// @[core.scala:188:23, :190:18]\n reg b2_uop_iw_p2_poisoned;\t// @[core.scala:190:18]\n assign brupdate_b2_uop_iw_p2_poisoned = b2_uop_iw_p2_poisoned;\t// @[core.scala:188:23, :190:18]\n reg b2_uop_is_br;\t// @[core.scala:190:18]\n assign brupdate_b2_uop_is_br = b2_uop_is_br;\t// @[core.scala:188:23, :190:18]\n reg b2_uop_is_jalr;\t// @[core.scala:190:18]\n assign brupdate_b2_uop_is_jalr = b2_uop_is_jalr;\t// @[core.scala:188:23, :190:18]\n reg b2_uop_is_jal;\t// @[core.scala:190:18]\n assign brupdate_b2_uop_is_jal = b2_uop_is_jal;\t// @[core.scala:188:23, :190:18]\n reg b2_uop_is_sfb;\t// @[core.scala:190:18]\n assign brupdate_b2_uop_is_sfb = b2_uop_is_sfb;\t// @[core.scala:188:23, :190:18]\n reg [15:0] b2_uop_br_mask;\t// @[core.scala:190:18]\n assign brupdate_b2_uop_br_mask = b2_uop_br_mask;\t// @[core.scala:188:23, :190:18]\n reg [3:0] b2_uop_br_tag;\t// @[core.scala:190:18]\n assign brupdate_b2_uop_br_tag = b2_uop_br_tag;\t// @[core.scala:188:23, :190:18]\n reg [4:0] b2_uop_ftq_idx;\t// @[core.scala:190:18]\n assign brupdate_b2_uop_ftq_idx = b2_uop_ftq_idx;\t// @[core.scala:188:23, :190:18]\n reg b2_uop_edge_inst;\t// @[core.scala:190:18]\n assign brupdate_b2_uop_edge_inst = b2_uop_edge_inst;\t// @[core.scala:188:23, :190:18]\n reg [5:0] b2_uop_pc_lob;\t// @[core.scala:190:18]\n assign brupdate_b2_uop_pc_lob = b2_uop_pc_lob;\t// @[core.scala:188:23, :190:18]\n reg b2_uop_taken;\t// @[core.scala:190:18]\n assign brupdate_b2_uop_taken = b2_uop_taken;\t// @[core.scala:188:23, :190:18]\n reg [19:0] b2_uop_imm_packed;\t// @[core.scala:190:18]\n assign brupdate_b2_uop_imm_packed = b2_uop_imm_packed;\t// @[core.scala:188:23, :190:18]\n reg [11:0] b2_uop_csr_addr;\t// @[core.scala:190:18]\n assign brupdate_b2_uop_csr_addr = b2_uop_csr_addr;\t// @[core.scala:188:23, :190:18]\n reg [6:0] b2_uop_rob_idx;\t// @[core.scala:190:18]\n assign brupdate_b2_uop_rob_idx = b2_uop_rob_idx;\t// @[core.scala:188:23, :190:18]\n reg [4:0] b2_uop_ldq_idx;\t// @[core.scala:190:18]\n assign brupdate_b2_uop_ldq_idx = b2_uop_ldq_idx;\t// @[core.scala:188:23, :190:18]\n reg [4:0] b2_uop_stq_idx;\t// @[core.scala:190:18]\n assign brupdate_b2_uop_stq_idx = b2_uop_stq_idx;\t// @[core.scala:188:23, :190:18]\n reg [1:0] b2_uop_rxq_idx;\t// @[core.scala:190:18]\n assign brupdate_b2_uop_rxq_idx = b2_uop_rxq_idx;\t// @[core.scala:188:23, :190:18]\n reg [6:0] b2_uop_pdst;\t// @[core.scala:190:18]\n assign brupdate_b2_uop_pdst = b2_uop_pdst;\t// @[core.scala:188:23, :190:18]\n reg [6:0] b2_uop_prs1;\t// @[core.scala:190:18]\n assign brupdate_b2_uop_prs1 = b2_uop_prs1;\t// @[core.scala:188:23, :190:18]\n reg [6:0] b2_uop_prs2;\t// @[core.scala:190:18]\n assign brupdate_b2_uop_prs2 = b2_uop_prs2;\t// @[core.scala:188:23, :190:18]\n reg [6:0] b2_uop_prs3;\t// @[core.scala:190:18]\n assign brupdate_b2_uop_prs3 = b2_uop_prs3;\t// @[core.scala:188:23, :190:18]\n reg [4:0] b2_uop_ppred;\t// @[core.scala:190:18]\n assign brupdate_b2_uop_ppred = b2_uop_ppred;\t// @[core.scala:188:23, :190:18]\n reg b2_uop_prs1_busy;\t// @[core.scala:190:18]\n assign brupdate_b2_uop_prs1_busy = b2_uop_prs1_busy;\t// @[core.scala:188:23, :190:18]\n reg b2_uop_prs2_busy;\t// @[core.scala:190:18]\n assign brupdate_b2_uop_prs2_busy = b2_uop_prs2_busy;\t// @[core.scala:188:23, :190:18]\n reg b2_uop_prs3_busy;\t// @[core.scala:190:18]\n assign brupdate_b2_uop_prs3_busy = b2_uop_prs3_busy;\t// @[core.scala:188:23, :190:18]\n reg b2_uop_ppred_busy;\t// @[core.scala:190:18]\n assign brupdate_b2_uop_ppred_busy = b2_uop_ppred_busy;\t// @[core.scala:188:23, :190:18]\n reg [6:0] b2_uop_stale_pdst;\t// @[core.scala:190:18]\n assign brupdate_b2_uop_stale_pdst = b2_uop_stale_pdst;\t// @[core.scala:188:23, :190:18]\n reg b2_uop_exception;\t// @[core.scala:190:18]\n assign brupdate_b2_uop_exception = b2_uop_exception;\t// @[core.scala:188:23, :190:18]\n reg [63:0] b2_uop_exc_cause;\t// @[core.scala:190:18]\n assign brupdate_b2_uop_exc_cause = b2_uop_exc_cause;\t// @[core.scala:188:23, :190:18]\n reg b2_uop_bypassable;\t// @[core.scala:190:18]\n assign brupdate_b2_uop_bypassable = b2_uop_bypassable;\t// @[core.scala:188:23, :190:18]\n reg [4:0] b2_uop_mem_cmd;\t// @[core.scala:190:18]\n assign brupdate_b2_uop_mem_cmd = b2_uop_mem_cmd;\t// @[core.scala:188:23, :190:18]\n reg [1:0] b2_uop_mem_size;\t// @[core.scala:190:18]\n assign brupdate_b2_uop_mem_size = b2_uop_mem_size;\t// @[core.scala:188:23, :190:18]\n reg b2_uop_mem_signed;\t// @[core.scala:190:18]\n assign brupdate_b2_uop_mem_signed = b2_uop_mem_signed;\t// @[core.scala:188:23, :190:18]\n reg b2_uop_is_fence;\t// @[core.scala:190:18]\n assign brupdate_b2_uop_is_fence = b2_uop_is_fence;\t// @[core.scala:188:23, :190:18]\n reg b2_uop_is_fencei;\t// @[core.scala:190:18]\n assign brupdate_b2_uop_is_fencei = b2_uop_is_fencei;\t// @[core.scala:188:23, :190:18]\n reg b2_uop_is_amo;\t// @[core.scala:190:18]\n assign brupdate_b2_uop_is_amo = b2_uop_is_amo;\t// @[core.scala:188:23, :190:18]\n reg b2_uop_uses_ldq;\t// @[core.scala:190:18]\n assign brupdate_b2_uop_uses_ldq = b2_uop_uses_ldq;\t// @[core.scala:188:23, :190:18]\n reg b2_uop_uses_stq;\t// @[core.scala:190:18]\n assign brupdate_b2_uop_uses_stq = b2_uop_uses_stq;\t// @[core.scala:188:23, :190:18]\n reg b2_uop_is_sys_pc2epc;\t// @[core.scala:190:18]\n assign brupdate_b2_uop_is_sys_pc2epc = b2_uop_is_sys_pc2epc;\t// @[core.scala:188:23, :190:18]\n reg b2_uop_is_unique;\t// @[core.scala:190:18]\n assign brupdate_b2_uop_is_unique = b2_uop_is_unique;\t// @[core.scala:188:23, :190:18]\n reg b2_uop_flush_on_commit;\t// @[core.scala:190:18]\n assign brupdate_b2_uop_flush_on_commit = b2_uop_flush_on_commit;\t// @[core.scala:188:23, :190:18]\n reg b2_uop_ldst_is_rs1;\t// @[core.scala:190:18]\n assign brupdate_b2_uop_ldst_is_rs1 = b2_uop_ldst_is_rs1;\t// @[core.scala:188:23, :190:18]\n reg [5:0] b2_uop_ldst;\t// @[core.scala:190:18]\n assign brupdate_b2_uop_ldst = b2_uop_ldst;\t// @[core.scala:188:23, :190:18]\n reg [5:0] b2_uop_lrs1;\t// @[core.scala:190:18]\n assign brupdate_b2_uop_lrs1 = b2_uop_lrs1;\t// @[core.scala:188:23, :190:18]\n reg [5:0] b2_uop_lrs2;\t// @[core.scala:190:18]\n assign brupdate_b2_uop_lrs2 = b2_uop_lrs2;\t// @[core.scala:188:23, :190:18]\n reg [5:0] b2_uop_lrs3;\t// @[core.scala:190:18]\n assign brupdate_b2_uop_lrs3 = b2_uop_lrs3;\t// @[core.scala:188:23, :190:18]\n reg b2_uop_ldst_val;\t// @[core.scala:190:18]\n assign brupdate_b2_uop_ldst_val = b2_uop_ldst_val;\t// @[core.scala:188:23, :190:18]\n reg [1:0] b2_uop_dst_rtype;\t// @[core.scala:190:18]\n assign brupdate_b2_uop_dst_rtype = b2_uop_dst_rtype;\t// @[core.scala:188:23, :190:18]\n reg [1:0] b2_uop_lrs1_rtype;\t// @[core.scala:190:18]\n assign brupdate_b2_uop_lrs1_rtype = b2_uop_lrs1_rtype;\t// @[core.scala:188:23, :190:18]\n reg [1:0] b2_uop_lrs2_rtype;\t// @[core.scala:190:18]\n assign brupdate_b2_uop_lrs2_rtype = b2_uop_lrs2_rtype;\t// @[core.scala:188:23, :190:18]\n reg b2_uop_frs3_en;\t// @[core.scala:190:18]\n assign brupdate_b2_uop_frs3_en = b2_uop_frs3_en;\t// @[core.scala:188:23, :190:18]\n reg b2_uop_fp_val;\t// @[core.scala:190:18]\n assign brupdate_b2_uop_fp_val = b2_uop_fp_val;\t// @[core.scala:188:23, :190:18]\n reg b2_uop_fp_single;\t// @[core.scala:190:18]\n assign brupdate_b2_uop_fp_single = b2_uop_fp_single;\t// @[core.scala:188:23, :190:18]\n reg b2_uop_xcpt_pf_if;\t// @[core.scala:190:18]\n assign brupdate_b2_uop_xcpt_pf_if = b2_uop_xcpt_pf_if;\t// @[core.scala:188:23, :190:18]\n reg b2_uop_xcpt_ae_if;\t// @[core.scala:190:18]\n assign brupdate_b2_uop_xcpt_ae_if = b2_uop_xcpt_ae_if;\t// @[core.scala:188:23, :190:18]\n reg b2_uop_xcpt_ma_if;\t// @[core.scala:190:18]\n assign brupdate_b2_uop_xcpt_ma_if = b2_uop_xcpt_ma_if;\t// @[core.scala:188:23, :190:18]\n reg b2_uop_bp_debug_if;\t// @[core.scala:190:18]\n assign brupdate_b2_uop_bp_debug_if = b2_uop_bp_debug_if;\t// @[core.scala:188:23, :190:18]\n reg b2_uop_bp_xcpt_if;\t// @[core.scala:190:18]\n assign brupdate_b2_uop_bp_xcpt_if = b2_uop_bp_xcpt_if;\t// @[core.scala:188:23, :190:18]\n reg [1:0] b2_uop_debug_fsrc;\t// @[core.scala:190:18]\n assign brupdate_b2_uop_debug_fsrc = b2_uop_debug_fsrc;\t// @[core.scala:188:23, :190:18]\n reg [1:0] b2_uop_debug_tsrc;\t// @[core.scala:190:18]\n assign brupdate_b2_uop_debug_tsrc = b2_uop_debug_tsrc;\t// @[core.scala:188:23, :190:18]\n reg b2_mispredict;\t// @[core.scala:190:18]\n assign brupdate_b2_mispredict = b2_mispredict;\t// @[core.scala:188:23, :190:18]\n reg b2_taken;\t// @[core.scala:190:18]\n assign brupdate_b2_taken = b2_taken;\t// @[core.scala:188:23, :190:18]\n reg [2:0] b2_cfi_type;\t// @[core.scala:190:18]\n assign brupdate_b2_cfi_type = b2_cfi_type;\t// @[core.scala:188:23, :190:18]\n reg [1:0] b2_pc_sel;\t// @[core.scala:190:18]\n assign brupdate_b2_pc_sel = b2_pc_sel;\t// @[core.scala:188:23, :190:18]\n reg [39:0] b2_jalr_target;\t// @[core.scala:190:18]\n assign brupdate_b2_jalr_target = b2_jalr_target;\t// @[core.scala:188:23, :190:18]\n reg [20:0] b2_target_offset;\t// @[core.scala:190:18]\n assign brupdate_b2_target_offset = b2_target_offset;\t// @[core.scala:188:23, :190:18]\n wire _brinfos_0_valid_T = ~_rob_io_flush_valid;\t// @[core.scala:143:32, :197:37]\n wire _brinfos_0_valid_T_1 = _alu_exe_unit_io_brinfo_valid & _brinfos_0_valid_T;\t// @[execution-units.scala:119:32]\n wire _brinfos_1_valid_T = ~_rob_io_flush_valid;\t// @[core.scala:143:32, :197:37]\n wire _brinfos_1_valid_T_1 = _alu_exe_unit_1_io_brinfo_valid & _brinfos_1_valid_T;\t// @[execution-units.scala:119:32]\n wire _brinfos_2_valid_T = ~_rob_io_flush_valid;\t// @[core.scala:143:32, :197:37]\n wire _brinfos_2_valid_T_1 = _alu_exe_unit_2_io_brinfo_valid & _brinfos_2_valid_T;\t// @[execution-units.scala:119:32]\n wire [15:0] _GEN = {12'h0, brinfos_0_uop_br_tag};\t// @[core.scala:182:20, :199:47]\n wire [15:0] _b1_resolve_mask_T = {15'h0, brinfos_0_valid} << _GEN;\t// @[core.scala:182:20, :199:47]\n wire [15:0] _GEN_0 = {12'h0, brinfos_1_uop_br_tag};\t// @[core.scala:182:20, :199:47]\n wire [15:0] _b1_resolve_mask_T_1 = {15'h0, brinfos_1_valid} << _GEN_0;\t// @[core.scala:182:20, :199:47]\n wire [15:0] _GEN_1 = {12'h0, brinfos_2_uop_br_tag};\t// @[core.scala:182:20, :199:47]\n wire [15:0] _b1_resolve_mask_T_2 = {15'h0, brinfos_2_valid} << _GEN_1;\t// @[core.scala:182:20, :199:47]\n wire [15:0] _b1_resolve_mask_T_3 = _b1_resolve_mask_T | _b1_resolve_mask_T_1;\t// @[core.scala:199:{47,72}]\n assign _b1_resolve_mask_T_4 = _b1_resolve_mask_T_3 | _b1_resolve_mask_T_2;\t// @[core.scala:199:{47,72}]\n assign b1_resolve_mask = _b1_resolve_mask_T_4;\t// @[core.scala:189:19, :199:72]\n wire _T_1 = brinfos_0_valid & brinfos_0_mispredict;\t// @[core.scala:182:20, :200:51]\n wire _b1_mispredict_mask_T;\t// @[core.scala:200:51]\n assign _b1_mispredict_mask_T = _T_1;\t// @[core.scala:200:51]\n wire _use_this_mispredict_T_1;\t// @[core.scala:207:13]\n assign _use_this_mispredict_T_1 = _T_1;\t// @[core.scala:200:51, :207:13]\n wire [15:0] _b1_mispredict_mask_T_1 = {15'h0, _b1_mispredict_mask_T} << _GEN;\t// @[core.scala:199:47, :200:{51,68}]\n wire _T_3 = brinfos_1_valid & brinfos_1_mispredict;\t// @[core.scala:182:20, :200:51]\n wire _b1_mispredict_mask_T_2;\t// @[core.scala:200:51]\n assign _b1_mispredict_mask_T_2 = _T_3;\t// @[core.scala:200:51]\n wire _use_this_mispredict_T_9;\t// @[core.scala:207:13]\n assign _use_this_mispredict_T_9 = _T_3;\t// @[core.scala:200:51, :207:13]\n wire [15:0] _b1_mispredict_mask_T_3 = {15'h0, _b1_mispredict_mask_T_2} << _GEN_0;\t// @[core.scala:199:47, :200:{51,68}]\n wire _T_6 = brinfos_2_valid & brinfos_2_mispredict;\t// @[core.scala:182:20, :200:51]\n wire _b1_mispredict_mask_T_4;\t// @[core.scala:200:51]\n assign _b1_mispredict_mask_T_4 = _T_6;\t// @[core.scala:200:51]\n wire _use_this_mispredict_T_17;\t// @[core.scala:207:13]\n assign _use_this_mispredict_T_17 = _T_6;\t// @[core.scala:200:51, :207:13]\n wire [15:0] _b1_mispredict_mask_T_5 = {15'h0, _b1_mispredict_mask_T_4} << _GEN_1;\t// @[core.scala:199:47, :200:{51,68}]\n wire [15:0] _b1_mispredict_mask_T_6 = _b1_mispredict_mask_T_1 | _b1_mispredict_mask_T_3;\t// @[core.scala:200:{68,93}]\n assign _b1_mispredict_mask_T_7 = _b1_mispredict_mask_T_6 | _b1_mispredict_mask_T_5;\t// @[core.scala:200:{68,93}]\n assign b1_mispredict_mask = _b1_mispredict_mask_T_7;\t// @[core.scala:189:19, :200:93]\n wire _GEN_2 = brinfos_0_uop_rob_idx < _rob_io_rob_head_idx;\t// @[util.scala:363:64]\n wire _use_this_mispredict_T_3;\t// @[util.scala:363:64]\n assign _use_this_mispredict_T_3 = _GEN_2;\t// @[util.scala:363:64]\n wire _use_this_mispredict_T_5;\t// @[util.scala:363:78]\n assign _use_this_mispredict_T_5 = _GEN_2;\t// @[util.scala:363:{64,78}]\n wire _use_this_mispredict_T_13;\t// @[util.scala:363:78]\n assign _use_this_mispredict_T_13 = _GEN_2;\t// @[util.scala:363:{64,78}]\n wire _use_this_mispredict_T_4 = _use_this_mispredict_T_3;\t// @[util.scala:363:{58,64}]\n wire _use_this_mispredict_T_6 = _use_this_mispredict_T_4 ^ _use_this_mispredict_T_5;\t// @[util.scala:363:{58,72,78}]\n wire _use_this_mispredict_T_7 = _use_this_mispredict_T_1 & _use_this_mispredict_T_6;\t// @[util.scala:363:72]\n wire _use_this_mispredict_T_8 = ~_T_1;\t// @[core.scala:200:51, :206:31]\n wire _use_this_mispredict_T_10 = brinfos_1_uop_rob_idx < brinfos_0_uop_rob_idx;\t// @[util.scala:363:52]\n wire _use_this_mispredict_T_11 = brinfos_1_uop_rob_idx < _rob_io_rob_head_idx;\t// @[util.scala:363:64]\n wire _use_this_mispredict_T_12 = _use_this_mispredict_T_10 ^ _use_this_mispredict_T_11;\t// @[util.scala:363:{52,58,64}]\n wire _use_this_mispredict_T_14 = _use_this_mispredict_T_12 ^ _use_this_mispredict_T_13;\t// @[util.scala:363:{58,72,78}]\n wire _use_this_mispredict_T_15 = _use_this_mispredict_T_9 & _use_this_mispredict_T_14;\t// @[util.scala:363:72]\n wire use_this_mispredict_1 = _use_this_mispredict_T_8 | _use_this_mispredict_T_15;\t// @[core.scala:206:{31,47}, :207:29]\n wire _T_4 = _T_1 | _T_3;\t// @[core.scala:200:51, :209:37]\n wire [6:0] _T_5_uop_rob_idx = use_this_mispredict_1 ? brinfos_1_uop_rob_idx : brinfos_0_uop_rob_idx;\t// @[core.scala:182:20, :206:47, :210:28]\n wire _use_this_mispredict_T_16 = ~_T_4;\t// @[core.scala:206:31, :209:37]\n wire _use_this_mispredict_T_18 = brinfos_2_uop_rob_idx < _T_5_uop_rob_idx;\t// @[util.scala:363:52]\n wire _use_this_mispredict_T_19 = brinfos_2_uop_rob_idx < _rob_io_rob_head_idx;\t// @[util.scala:363:64]\n wire _use_this_mispredict_T_20 = _use_this_mispredict_T_18 ^ _use_this_mispredict_T_19;\t// @[util.scala:363:{52,58,64}]\n wire _use_this_mispredict_T_21 = _T_5_uop_rob_idx < _rob_io_rob_head_idx;\t// @[util.scala:363:78]\n wire _use_this_mispredict_T_22 = _use_this_mispredict_T_20 ^ _use_this_mispredict_T_21;\t// @[util.scala:363:{58,72,78}]\n wire _use_this_mispredict_T_23 = _use_this_mispredict_T_17 & _use_this_mispredict_T_22;\t// @[util.scala:363:72]\n wire use_this_mispredict_2 = _use_this_mispredict_T_16 | _use_this_mispredict_T_23;\t// @[core.scala:206:{31,47}, :207:29]\n wire [6:0] b2_uop_out_uopc = use_this_mispredict_2 ? brinfos_2_uop_uopc : use_this_mispredict_1 ? brinfos_1_uop_uopc : brinfos_0_uop_uopc;\t// @[util.scala:96:23]\n wire [31:0] b2_uop_out_inst = use_this_mispredict_2 ? brinfos_2_uop_inst : use_this_mispredict_1 ? brinfos_1_uop_inst : brinfos_0_uop_inst;\t// @[util.scala:96:23]\n wire [31:0] b2_uop_out_debug_inst = use_this_mispredict_2 ? brinfos_2_uop_debug_inst : use_this_mispredict_1 ? brinfos_1_uop_debug_inst : brinfos_0_uop_debug_inst;\t// @[util.scala:96:23]\n wire b2_uop_out_is_rvc = use_this_mispredict_2 ? brinfos_2_uop_is_rvc : use_this_mispredict_1 ? brinfos_1_uop_is_rvc : brinfos_0_uop_is_rvc;\t// @[util.scala:96:23]\n wire [39:0] b2_uop_out_debug_pc = use_this_mispredict_2 ? brinfos_2_uop_debug_pc : use_this_mispredict_1 ? brinfos_1_uop_debug_pc : brinfos_0_uop_debug_pc;\t// @[util.scala:96:23]\n wire [2:0] b2_uop_out_iq_type = use_this_mispredict_2 ? brinfos_2_uop_iq_type : use_this_mispredict_1 ? brinfos_1_uop_iq_type : brinfos_0_uop_iq_type;\t// @[util.scala:96:23]\n wire [9:0] b2_uop_out_fu_code = use_this_mispredict_2 ? brinfos_2_uop_fu_code : use_this_mispredict_1 ? brinfos_1_uop_fu_code : brinfos_0_uop_fu_code;\t// @[util.scala:96:23]\n wire [3:0] b2_uop_out_ctrl_br_type = use_this_mispredict_2 ? brinfos_2_uop_ctrl_br_type : use_this_mispredict_1 ? brinfos_1_uop_ctrl_br_type : brinfos_0_uop_ctrl_br_type;\t// @[util.scala:96:23]\n wire [1:0] b2_uop_out_ctrl_op1_sel = use_this_mispredict_2 ? brinfos_2_uop_ctrl_op1_sel : use_this_mispredict_1 ? brinfos_1_uop_ctrl_op1_sel : brinfos_0_uop_ctrl_op1_sel;\t// @[util.scala:96:23]\n wire [2:0] b2_uop_out_ctrl_op2_sel = use_this_mispredict_2 ? brinfos_2_uop_ctrl_op2_sel : use_this_mispredict_1 ? brinfos_1_uop_ctrl_op2_sel : brinfos_0_uop_ctrl_op2_sel;\t// @[util.scala:96:23]\n wire [2:0] b2_uop_out_ctrl_imm_sel = use_this_mispredict_2 ? brinfos_2_uop_ctrl_imm_sel : use_this_mispredict_1 ? brinfos_1_uop_ctrl_imm_sel : brinfos_0_uop_ctrl_imm_sel;\t// @[util.scala:96:23]\n wire [4:0] b2_uop_out_ctrl_op_fcn = use_this_mispredict_2 ? brinfos_2_uop_ctrl_op_fcn : use_this_mispredict_1 ? brinfos_1_uop_ctrl_op_fcn : brinfos_0_uop_ctrl_op_fcn;\t// @[util.scala:96:23]\n wire b2_uop_out_ctrl_fcn_dw = use_this_mispredict_2 ? brinfos_2_uop_ctrl_fcn_dw : use_this_mispredict_1 ? brinfos_1_uop_ctrl_fcn_dw : brinfos_0_uop_ctrl_fcn_dw;\t// @[util.scala:96:23]\n wire [2:0] b2_uop_out_ctrl_csr_cmd = use_this_mispredict_2 ? brinfos_2_uop_ctrl_csr_cmd : use_this_mispredict_1 ? brinfos_1_uop_ctrl_csr_cmd : brinfos_0_uop_ctrl_csr_cmd;\t// @[util.scala:96:23]\n wire b2_uop_out_ctrl_is_load = use_this_mispredict_2 ? brinfos_2_uop_ctrl_is_load : use_this_mispredict_1 ? brinfos_1_uop_ctrl_is_load : brinfos_0_uop_ctrl_is_load;\t// @[util.scala:96:23]\n wire b2_uop_out_ctrl_is_sta = use_this_mispredict_2 ? brinfos_2_uop_ctrl_is_sta : use_this_mispredict_1 ? brinfos_1_uop_ctrl_is_sta : brinfos_0_uop_ctrl_is_sta;\t// @[util.scala:96:23]\n wire b2_uop_out_ctrl_is_std = use_this_mispredict_2 ? brinfos_2_uop_ctrl_is_std : use_this_mispredict_1 ? brinfos_1_uop_ctrl_is_std : brinfos_0_uop_ctrl_is_std;\t// @[util.scala:96:23]\n wire [1:0] b2_uop_out_iw_state = use_this_mispredict_2 ? brinfos_2_uop_iw_state : use_this_mispredict_1 ? brinfos_1_uop_iw_state : brinfos_0_uop_iw_state;\t// @[util.scala:96:23]\n wire b2_uop_out_iw_p1_poisoned = use_this_mispredict_2 ? brinfos_2_uop_iw_p1_poisoned : use_this_mispredict_1 ? brinfos_1_uop_iw_p1_poisoned : brinfos_0_uop_iw_p1_poisoned;\t// @[util.scala:96:23]\n wire b2_uop_out_iw_p2_poisoned = use_this_mispredict_2 ? brinfos_2_uop_iw_p2_poisoned : use_this_mispredict_1 ? brinfos_1_uop_iw_p2_poisoned : brinfos_0_uop_iw_p2_poisoned;\t// @[util.scala:96:23]\n wire b2_uop_out_is_br = use_this_mispredict_2 ? brinfos_2_uop_is_br : use_this_mispredict_1 ? brinfos_1_uop_is_br : brinfos_0_uop_is_br;\t// @[util.scala:96:23]\n wire b2_uop_out_is_jalr = use_this_mispredict_2 ? brinfos_2_uop_is_jalr : use_this_mispredict_1 ? brinfos_1_uop_is_jalr : brinfos_0_uop_is_jalr;\t// @[util.scala:96:23]\n wire b2_uop_out_is_jal = use_this_mispredict_2 ? brinfos_2_uop_is_jal : use_this_mispredict_1 ? brinfos_1_uop_is_jal : brinfos_0_uop_is_jal;\t// @[util.scala:96:23]\n wire b2_uop_out_is_sfb = use_this_mispredict_2 ? brinfos_2_uop_is_sfb : use_this_mispredict_1 ? brinfos_1_uop_is_sfb : brinfos_0_uop_is_sfb;\t// @[util.scala:96:23]\n wire [3:0] b2_uop_out_br_tag = use_this_mispredict_2 ? brinfos_2_uop_br_tag : use_this_mispredict_1 ? brinfos_1_uop_br_tag : brinfos_0_uop_br_tag;\t// @[util.scala:96:23]\n wire [4:0] _T_8_uop_ftq_idx = use_this_mispredict_2 ? brinfos_2_uop_ftq_idx : use_this_mispredict_1 ? brinfos_1_uop_ftq_idx : brinfos_0_uop_ftq_idx;\t// @[core.scala:182:20, :206:47, :210:28]\n assign io_ifu_get_pc_1_ftq_idx_0 = _T_8_uop_ftq_idx;\t// @[core.scala:51:7, :210:28]\n wire [4:0] b2_uop_out_ftq_idx;\t// @[util.scala:96:23]\n assign b2_uop_out_ftq_idx = _T_8_uop_ftq_idx;\t// @[util.scala:96:23]\n wire b2_uop_out_edge_inst = use_this_mispredict_2 ? brinfos_2_uop_edge_inst : use_this_mispredict_1 ? brinfos_1_uop_edge_inst : brinfos_0_uop_edge_inst;\t// @[util.scala:96:23]\n wire [5:0] b2_uop_out_pc_lob = use_this_mispredict_2 ? brinfos_2_uop_pc_lob : use_this_mispredict_1 ? brinfos_1_uop_pc_lob : brinfos_0_uop_pc_lob;\t// @[util.scala:96:23]\n wire b2_uop_out_taken = use_this_mispredict_2 ? brinfos_2_uop_taken : use_this_mispredict_1 ? brinfos_1_uop_taken : brinfos_0_uop_taken;\t// @[util.scala:96:23]\n wire [19:0] b2_uop_out_imm_packed = use_this_mispredict_2 ? brinfos_2_uop_imm_packed : use_this_mispredict_1 ? brinfos_1_uop_imm_packed : brinfos_0_uop_imm_packed;\t// @[util.scala:96:23]\n wire [11:0] b2_uop_out_csr_addr = use_this_mispredict_2 ? brinfos_2_uop_csr_addr : use_this_mispredict_1 ? brinfos_1_uop_csr_addr : brinfos_0_uop_csr_addr;\t// @[util.scala:96:23]\n wire [6:0] b2_uop_out_rob_idx = use_this_mispredict_2 ? brinfos_2_uop_rob_idx : _T_5_uop_rob_idx;\t// @[util.scala:96:23]\n wire [4:0] b2_uop_out_ldq_idx = use_this_mispredict_2 ? brinfos_2_uop_ldq_idx : use_this_mispredict_1 ? brinfos_1_uop_ldq_idx : brinfos_0_uop_ldq_idx;\t// @[util.scala:96:23]\n wire [4:0] b2_uop_out_stq_idx = use_this_mispredict_2 ? brinfos_2_uop_stq_idx : use_this_mispredict_1 ? brinfos_1_uop_stq_idx : brinfos_0_uop_stq_idx;\t// @[util.scala:96:23]\n wire [1:0] b2_uop_out_rxq_idx = use_this_mispredict_2 ? brinfos_2_uop_rxq_idx : use_this_mispredict_1 ? brinfos_1_uop_rxq_idx : brinfos_0_uop_rxq_idx;\t// @[util.scala:96:23]\n wire [6:0] b2_uop_out_pdst = use_this_mispredict_2 ? brinfos_2_uop_pdst : use_this_mispredict_1 ? brinfos_1_uop_pdst : brinfos_0_uop_pdst;\t// @[util.scala:96:23]\n wire [6:0] b2_uop_out_prs1 = use_this_mispredict_2 ? brinfos_2_uop_prs1 : use_this_mispredict_1 ? brinfos_1_uop_prs1 : brinfos_0_uop_prs1;\t// @[util.scala:96:23]\n wire [6:0] b2_uop_out_prs2 = use_this_mispredict_2 ? brinfos_2_uop_prs2 : use_this_mispredict_1 ? brinfos_1_uop_prs2 : brinfos_0_uop_prs2;\t// @[util.scala:96:23]\n wire [6:0] b2_uop_out_prs3 = use_this_mispredict_2 ? brinfos_2_uop_prs3 : use_this_mispredict_1 ? brinfos_1_uop_prs3 : brinfos_0_uop_prs3;\t// @[util.scala:96:23]\n wire [4:0] b2_uop_out_ppred = use_this_mispredict_2 ? brinfos_2_uop_ppred : use_this_mispredict_1 ? brinfos_1_uop_ppred : brinfos_0_uop_ppred;\t// @[util.scala:96:23]\n wire b2_uop_out_prs1_busy = use_this_mispredict_2 ? brinfos_2_uop_prs1_busy : use_this_mispredict_1 ? brinfos_1_uop_prs1_busy : brinfos_0_uop_prs1_busy;\t// @[util.scala:96:23]\n wire b2_uop_out_prs2_busy = use_this_mispredict_2 ? brinfos_2_uop_prs2_busy : use_this_mispredict_1 ? brinfos_1_uop_prs2_busy : brinfos_0_uop_prs2_busy;\t// @[util.scala:96:23]\n wire b2_uop_out_prs3_busy = use_this_mispredict_2 ? brinfos_2_uop_prs3_busy : use_this_mispredict_1 ? brinfos_1_uop_prs3_busy : brinfos_0_uop_prs3_busy;\t// @[util.scala:96:23]\n wire b2_uop_out_ppred_busy = use_this_mispredict_2 ? brinfos_2_uop_ppred_busy : use_this_mispredict_1 ? brinfos_1_uop_ppred_busy : brinfos_0_uop_ppred_busy;\t// @[util.scala:96:23]\n wire [6:0] b2_uop_out_stale_pdst = use_this_mispredict_2 ? brinfos_2_uop_stale_pdst : use_this_mispredict_1 ? brinfos_1_uop_stale_pdst : brinfos_0_uop_stale_pdst;\t// @[util.scala:96:23]\n wire b2_uop_out_exception = use_this_mispredict_2 ? brinfos_2_uop_exception : use_this_mispredict_1 ? brinfos_1_uop_exception : brinfos_0_uop_exception;\t// @[util.scala:96:23]\n wire [63:0] b2_uop_out_exc_cause = use_this_mispredict_2 ? brinfos_2_uop_exc_cause : use_this_mispredict_1 ? brinfos_1_uop_exc_cause : brinfos_0_uop_exc_cause;\t// @[util.scala:96:23]\n wire b2_uop_out_bypassable = use_this_mispredict_2 ? brinfos_2_uop_bypassable : use_this_mispredict_1 ? brinfos_1_uop_bypassable : brinfos_0_uop_bypassable;\t// @[util.scala:96:23]\n wire [4:0] b2_uop_out_mem_cmd = use_this_mispredict_2 ? brinfos_2_uop_mem_cmd : use_this_mispredict_1 ? brinfos_1_uop_mem_cmd : brinfos_0_uop_mem_cmd;\t// @[util.scala:96:23]\n wire [1:0] b2_uop_out_mem_size = use_this_mispredict_2 ? brinfos_2_uop_mem_size : use_this_mispredict_1 ? brinfos_1_uop_mem_size : brinfos_0_uop_mem_size;\t// @[util.scala:96:23]\n wire b2_uop_out_mem_signed = use_this_mispredict_2 ? brinfos_2_uop_mem_signed : use_this_mispredict_1 ? brinfos_1_uop_mem_signed : brinfos_0_uop_mem_signed;\t// @[util.scala:96:23]\n wire b2_uop_out_is_fence = use_this_mispredict_2 ? brinfos_2_uop_is_fence : use_this_mispredict_1 ? brinfos_1_uop_is_fence : brinfos_0_uop_is_fence;\t// @[util.scala:96:23]\n wire b2_uop_out_is_fencei = use_this_mispredict_2 ? brinfos_2_uop_is_fencei : use_this_mispredict_1 ? brinfos_1_uop_is_fencei : brinfos_0_uop_is_fencei;\t// @[util.scala:96:23]\n wire b2_uop_out_is_amo = use_this_mispredict_2 ? brinfos_2_uop_is_amo : use_this_mispredict_1 ? brinfos_1_uop_is_amo : brinfos_0_uop_is_amo;\t// @[util.scala:96:23]\n wire b2_uop_out_uses_ldq = use_this_mispredict_2 ? brinfos_2_uop_uses_ldq : use_this_mispredict_1 ? brinfos_1_uop_uses_ldq : brinfos_0_uop_uses_ldq;\t// @[util.scala:96:23]\n wire b2_uop_out_uses_stq = use_this_mispredict_2 ? brinfos_2_uop_uses_stq : use_this_mispredict_1 ? brinfos_1_uop_uses_stq : brinfos_0_uop_uses_stq;\t// @[util.scala:96:23]\n wire b2_uop_out_is_sys_pc2epc = use_this_mispredict_2 ? brinfos_2_uop_is_sys_pc2epc : use_this_mispredict_1 ? brinfos_1_uop_is_sys_pc2epc : brinfos_0_uop_is_sys_pc2epc;\t// @[util.scala:96:23]\n wire b2_uop_out_is_unique = use_this_mispredict_2 ? brinfos_2_uop_is_unique : use_this_mispredict_1 ? brinfos_1_uop_is_unique : brinfos_0_uop_is_unique;\t// @[util.scala:96:23]\n wire b2_uop_out_flush_on_commit = use_this_mispredict_2 ? brinfos_2_uop_flush_on_commit : use_this_mispredict_1 ? brinfos_1_uop_flush_on_commit : brinfos_0_uop_flush_on_commit;\t// @[util.scala:96:23]\n wire b2_uop_out_ldst_is_rs1 = use_this_mispredict_2 ? brinfos_2_uop_ldst_is_rs1 : use_this_mispredict_1 ? brinfos_1_uop_ldst_is_rs1 : brinfos_0_uop_ldst_is_rs1;\t// @[util.scala:96:23]\n wire [5:0] b2_uop_out_ldst = use_this_mispredict_2 ? brinfos_2_uop_ldst : use_this_mispredict_1 ? brinfos_1_uop_ldst : brinfos_0_uop_ldst;\t// @[util.scala:96:23]\n wire [5:0] b2_uop_out_lrs1 = use_this_mispredict_2 ? brinfos_2_uop_lrs1 : use_this_mispredict_1 ? brinfos_1_uop_lrs1 : brinfos_0_uop_lrs1;\t// @[util.scala:96:23]\n wire [5:0] b2_uop_out_lrs2 = use_this_mispredict_2 ? brinfos_2_uop_lrs2 : use_this_mispredict_1 ? brinfos_1_uop_lrs2 : brinfos_0_uop_lrs2;\t// @[util.scala:96:23]\n wire [5:0] b2_uop_out_lrs3 = use_this_mispredict_2 ? brinfos_2_uop_lrs3 : use_this_mispredict_1 ? brinfos_1_uop_lrs3 : brinfos_0_uop_lrs3;\t// @[util.scala:96:23]\n wire b2_uop_out_ldst_val = use_this_mispredict_2 ? brinfos_2_uop_ldst_val : use_this_mispredict_1 ? brinfos_1_uop_ldst_val : brinfos_0_uop_ldst_val;\t// @[util.scala:96:23]\n wire [1:0] b2_uop_out_dst_rtype = use_this_mispredict_2 ? brinfos_2_uop_dst_rtype : use_this_mispredict_1 ? brinfos_1_uop_dst_rtype : brinfos_0_uop_dst_rtype;\t// @[util.scala:96:23]\n wire [1:0] b2_uop_out_lrs1_rtype = use_this_mispredict_2 ? brinfos_2_uop_lrs1_rtype : use_this_mispredict_1 ? brinfos_1_uop_lrs1_rtype : brinfos_0_uop_lrs1_rtype;\t// @[util.scala:96:23]\n wire [1:0] b2_uop_out_lrs2_rtype = use_this_mispredict_2 ? brinfos_2_uop_lrs2_rtype : use_this_mispredict_1 ? brinfos_1_uop_lrs2_rtype : brinfos_0_uop_lrs2_rtype;\t// @[util.scala:96:23]\n wire b2_uop_out_frs3_en = use_this_mispredict_2 ? brinfos_2_uop_frs3_en : use_this_mispredict_1 ? brinfos_1_uop_frs3_en : brinfos_0_uop_frs3_en;\t// @[util.scala:96:23]\n wire b2_uop_out_fp_val = use_this_mispredict_2 ? brinfos_2_uop_fp_val : use_this_mispredict_1 ? brinfos_1_uop_fp_val : brinfos_0_uop_fp_val;\t// @[util.scala:96:23]\n wire b2_uop_out_fp_single = use_this_mispredict_2 ? brinfos_2_uop_fp_single : use_this_mispredict_1 ? brinfos_1_uop_fp_single : brinfos_0_uop_fp_single;\t// @[util.scala:96:23]\n wire b2_uop_out_xcpt_pf_if = use_this_mispredict_2 ? brinfos_2_uop_xcpt_pf_if : use_this_mispredict_1 ? brinfos_1_uop_xcpt_pf_if : brinfos_0_uop_xcpt_pf_if;\t// @[util.scala:96:23]\n wire b2_uop_out_xcpt_ae_if = use_this_mispredict_2 ? brinfos_2_uop_xcpt_ae_if : use_this_mispredict_1 ? brinfos_1_uop_xcpt_ae_if : brinfos_0_uop_xcpt_ae_if;\t// @[util.scala:96:23]\n wire b2_uop_out_xcpt_ma_if = use_this_mispredict_2 ? brinfos_2_uop_xcpt_ma_if : use_this_mispredict_1 ? brinfos_1_uop_xcpt_ma_if : brinfos_0_uop_xcpt_ma_if;\t// @[util.scala:96:23]\n wire b2_uop_out_bp_debug_if = use_this_mispredict_2 ? brinfos_2_uop_bp_debug_if : use_this_mispredict_1 ? brinfos_1_uop_bp_debug_if : brinfos_0_uop_bp_debug_if;\t// @[util.scala:96:23]\n wire b2_uop_out_bp_xcpt_if = use_this_mispredict_2 ? brinfos_2_uop_bp_xcpt_if : use_this_mispredict_1 ? brinfos_1_uop_bp_xcpt_if : brinfos_0_uop_bp_xcpt_if;\t// @[util.scala:96:23]\n wire [1:0] b2_uop_out_debug_fsrc = use_this_mispredict_2 ? brinfos_2_uop_debug_fsrc : use_this_mispredict_1 ? brinfos_1_uop_debug_fsrc : brinfos_0_uop_debug_fsrc;\t// @[util.scala:96:23]\n wire [1:0] b2_uop_out_debug_tsrc = use_this_mispredict_2 ? brinfos_2_uop_debug_tsrc : use_this_mispredict_1 ? brinfos_1_uop_debug_tsrc : brinfos_0_uop_debug_tsrc;\t// @[util.scala:96:23]\n wire [15:0] _b2_uop_out_br_mask_T_1;\t// @[util.scala:85:25]\n wire [15:0] b2_uop_out_br_mask;\t// @[util.scala:96:23]\n wire [15:0] _b2_uop_out_br_mask_T = ~brupdate_b1_resolve_mask;\t// @[util.scala:85:27]\n assign _b2_uop_out_br_mask_T_1 = (use_this_mispredict_2 ? brinfos_2_uop_br_mask : use_this_mispredict_1 ? brinfos_1_uop_br_mask : brinfos_0_uop_br_mask) & _b2_uop_out_br_mask_T;\t// @[util.scala:85:{25,27}]\n assign b2_uop_out_br_mask = _b2_uop_out_br_mask_T_1;\t// @[util.scala:85:25, :96:23]\n reg [39:0] b2_jalr_target_REG;\t// @[core.scala:218:28]\n wire custom_csrs_csrs_0_ren;\t// @[core.scala:276:25]\n wire custom_csrs_csrs_0_wen;\t// @[core.scala:276:25]\n wire [63:0] custom_csrs_csrs_0_wdata;\t// @[core.scala:276:25]\n wire [63:0] custom_csrs_csrs_0_value;\t// @[core.scala:276:25]\n wire custom_csrs_csrs_1_ren;\t// @[core.scala:276:25]\n wire custom_csrs_csrs_1_wen;\t// @[core.scala:276:25]\n wire [63:0] custom_csrs_csrs_1_wdata;\t// @[core.scala:276:25]\n wire [63:0] custom_csrs_csrs_1_value;\t// @[core.scala:276:25]\n reg [63:0] debug_tsc_reg;\t// @[core.scala:288:30]\n assign io_lsu_tsc_reg_0 = debug_tsc_reg;\t// @[core.scala:51:7, :288:30]\n reg [63:0] debug_irt_reg;\t// @[core.scala:289:30]\n reg [63:0] debug_brs_0;\t// @[core.scala:290:26]\n reg [63:0] debug_brs_1;\t// @[core.scala:290:26]\n reg [63:0] debug_brs_2;\t// @[core.scala:290:26]\n reg [63:0] debug_brs_3;\t// @[core.scala:290:26]\n reg [63:0] debug_jals_0;\t// @[core.scala:291:26]\n reg [63:0] debug_jals_1;\t// @[core.scala:291:26]\n reg [63:0] debug_jals_2;\t// @[core.scala:291:26]\n reg [63:0] debug_jals_3;\t// @[core.scala:291:26]\n reg [63:0] debug_jalrs_0;\t// @[core.scala:292:26]\n reg [63:0] debug_jalrs_1;\t// @[core.scala:292:26]\n reg [63:0] debug_jalrs_2;\t// @[core.scala:292:26]\n reg [63:0] debug_jalrs_3;\t// @[core.scala:292:26]\n wire _GEN_3 = _rob_io_commit_uops_0_debug_fsrc == 2'h0;\t// @[core.scala:143:32, :297:41]\n wire _debug_brs_0_T;\t// @[core.scala:297:41]\n assign _debug_brs_0_T = _GEN_3;\t// @[core.scala:297:41]\n wire _debug_jals_0_T;\t// @[core.scala:302:41]\n assign _debug_jals_0_T = _GEN_3;\t// @[core.scala:297:41, :302:41]\n wire _debug_jalrs_0_T;\t// @[core.scala:307:41]\n assign _debug_jalrs_0_T = _GEN_3;\t// @[core.scala:297:41, :307:41]\n wire _debug_brs_0_T_1 = _rob_io_commit_arch_valids_0 & _debug_brs_0_T;\t// @[core.scala:143:32, :296:36, :297:41]\n wire _debug_brs_0_T_2 = _debug_brs_0_T_1 & _rob_io_commit_uops_0_is_br;\t// @[core.scala:143:32, :296:36, :297:50]\n wire _debug_brs_0_WIRE_0 = _debug_brs_0_T_2;\t// @[core.scala:295:52, :297:50]\n wire _GEN_4 = _rob_io_commit_uops_1_debug_fsrc == 2'h0;\t// @[core.scala:143:32, :297:41]\n wire _debug_brs_0_T_3;\t// @[core.scala:297:41]\n assign _debug_brs_0_T_3 = _GEN_4;\t// @[core.scala:297:41]\n wire _debug_jals_0_T_3;\t// @[core.scala:302:41]\n assign _debug_jals_0_T_3 = _GEN_4;\t// @[core.scala:297:41, :302:41]\n wire _debug_jalrs_0_T_3;\t// @[core.scala:307:41]\n assign _debug_jalrs_0_T_3 = _GEN_4;\t// @[core.scala:297:41, :307:41]\n wire _debug_brs_0_T_4 = _rob_io_commit_arch_valids_1 & _debug_brs_0_T_3;\t// @[core.scala:143:32, :296:36, :297:41]\n wire _debug_brs_0_T_5 = _debug_brs_0_T_4 & _rob_io_commit_uops_1_is_br;\t// @[core.scala:143:32, :296:36, :297:50]\n wire _debug_brs_0_WIRE_1 = _debug_brs_0_T_5;\t// @[core.scala:295:52, :297:50]\n wire _GEN_5 = _rob_io_commit_uops_2_debug_fsrc == 2'h0;\t// @[core.scala:143:32, :297:41]\n wire _debug_brs_0_T_6;\t// @[core.scala:297:41]\n assign _debug_brs_0_T_6 = _GEN_5;\t// @[core.scala:297:41]\n wire _debug_jals_0_T_6;\t// @[core.scala:302:41]\n assign _debug_jals_0_T_6 = _GEN_5;\t// @[core.scala:297:41, :302:41]\n wire _debug_jalrs_0_T_6;\t// @[core.scala:307:41]\n assign _debug_jalrs_0_T_6 = _GEN_5;\t// @[core.scala:297:41, :307:41]\n wire _debug_brs_0_T_7 = _rob_io_commit_arch_valids_2 & _debug_brs_0_T_6;\t// @[core.scala:143:32, :296:36, :297:41]\n wire _debug_brs_0_T_8 = _debug_brs_0_T_7 & _rob_io_commit_uops_2_is_br;\t// @[core.scala:143:32, :296:36, :297:50]\n wire _debug_brs_0_WIRE_2 = _debug_brs_0_T_8;\t// @[core.scala:295:52, :297:50]\n wire [1:0] _debug_brs_0_T_9 = {1'h0, _debug_brs_0_WIRE_1} + {1'h0, _debug_brs_0_WIRE_2};\t// @[core.scala:295:{44,52}]\n wire [1:0] _debug_brs_0_T_10 = _debug_brs_0_T_9;\t// @[core.scala:295:44]\n wire [2:0] _debug_brs_0_T_11 = {2'h0, _debug_brs_0_WIRE_0} + {1'h0, _debug_brs_0_T_10};\t// @[core.scala:295:{44,52}]\n wire [1:0] _debug_brs_0_T_12 = _debug_brs_0_T_11[1:0];\t// @[core.scala:295:44]\n wire [64:0] _debug_brs_0_T_13 = {1'h0, debug_brs_0} + {63'h0, _debug_brs_0_T_12};\t// @[core.scala:290:26, :295:{34,44}]\n wire [63:0] _debug_brs_0_T_14 = _debug_brs_0_T_13[63:0];\t// @[core.scala:295:34]\n wire _debug_jals_0_T_1 = _rob_io_commit_arch_valids_0 & _debug_jals_0_T;\t// @[core.scala:143:32, :301:36, :302:41]\n wire _debug_jals_0_T_2 = _debug_jals_0_T_1 & _rob_io_commit_uops_0_is_jal;\t// @[core.scala:143:32, :301:36, :302:50]\n wire _debug_jals_0_WIRE_0 = _debug_jals_0_T_2;\t// @[core.scala:300:54, :302:50]\n wire _debug_jals_0_T_4 = _rob_io_commit_arch_valids_1 & _debug_jals_0_T_3;\t// @[core.scala:143:32, :301:36, :302:41]\n wire _debug_jals_0_T_5 = _debug_jals_0_T_4 & _rob_io_commit_uops_1_is_jal;\t// @[core.scala:143:32, :301:36, :302:50]\n wire _debug_jals_0_WIRE_1 = _debug_jals_0_T_5;\t// @[core.scala:300:54, :302:50]\n wire _debug_jals_0_T_7 = _rob_io_commit_arch_valids_2 & _debug_jals_0_T_6;\t// @[core.scala:143:32, :301:36, :302:41]\n wire _debug_jals_0_T_8 = _debug_jals_0_T_7 & _rob_io_commit_uops_2_is_jal;\t// @[core.scala:143:32, :301:36, :302:50]\n wire _debug_jals_0_WIRE_2 = _debug_jals_0_T_8;\t// @[core.scala:300:54, :302:50]\n wire [1:0] _debug_jals_0_T_9 = {1'h0, _debug_jals_0_WIRE_1} + {1'h0, _debug_jals_0_WIRE_2};\t// @[core.scala:300:{46,54}]\n wire [1:0] _debug_jals_0_T_10 = _debug_jals_0_T_9;\t// @[core.scala:300:46]\n wire [2:0] _debug_jals_0_T_11 = {2'h0, _debug_jals_0_WIRE_0} + {1'h0, _debug_jals_0_T_10};\t// @[core.scala:300:{46,54}]\n wire [1:0] _debug_jals_0_T_12 = _debug_jals_0_T_11[1:0];\t// @[core.scala:300:46]\n wire [64:0] _debug_jals_0_T_13 = {1'h0, debug_jals_0} + {63'h0, _debug_jals_0_T_12};\t// @[core.scala:291:26, :295:34, :300:{36,46}]\n wire [63:0] _debug_jals_0_T_14 = _debug_jals_0_T_13[63:0];\t// @[core.scala:300:36]\n wire _debug_jalrs_0_T_1 = _rob_io_commit_arch_valids_0 & _debug_jalrs_0_T;\t// @[core.scala:143:32, :306:36, :307:41]\n wire _debug_jalrs_0_T_2 = _debug_jalrs_0_T_1 & _rob_io_commit_uops_0_is_jalr;\t// @[core.scala:143:32, :306:36, :307:50]\n wire _debug_jalrs_0_WIRE_0 = _debug_jalrs_0_T_2;\t// @[core.scala:305:56, :307:50]\n wire _debug_jalrs_0_T_4 = _rob_io_commit_arch_valids_1 & _debug_jalrs_0_T_3;\t// @[core.scala:143:32, :306:36, :307:41]\n wire _debug_jalrs_0_T_5 = _debug_jalrs_0_T_4 & _rob_io_commit_uops_1_is_jalr;\t// @[core.scala:143:32, :306:36, :307:50]\n wire _debug_jalrs_0_WIRE_1 = _debug_jalrs_0_T_5;\t// @[core.scala:305:56, :307:50]\n wire _debug_jalrs_0_T_7 = _rob_io_commit_arch_valids_2 & _debug_jalrs_0_T_6;\t// @[core.scala:143:32, :306:36, :307:41]\n wire _debug_jalrs_0_T_8 = _debug_jalrs_0_T_7 & _rob_io_commit_uops_2_is_jalr;\t// @[core.scala:143:32, :306:36, :307:50]\n wire _debug_jalrs_0_WIRE_2 = _debug_jalrs_0_T_8;\t// @[core.scala:305:56, :307:50]\n wire [1:0] _debug_jalrs_0_T_9 = {1'h0, _debug_jalrs_0_WIRE_1} + {1'h0, _debug_jalrs_0_WIRE_2};\t// @[core.scala:305:{48,56}]\n wire [1:0] _debug_jalrs_0_T_10 = _debug_jalrs_0_T_9;\t// @[core.scala:305:48]\n wire [2:0] _debug_jalrs_0_T_11 = {2'h0, _debug_jalrs_0_WIRE_0} + {1'h0, _debug_jalrs_0_T_10};\t// @[core.scala:305:{48,56}]\n wire [1:0] _debug_jalrs_0_T_12 = _debug_jalrs_0_T_11[1:0];\t// @[core.scala:305:48]\n wire [64:0] _debug_jalrs_0_T_13 = {1'h0, debug_jalrs_0} + {63'h0, _debug_jalrs_0_T_12};\t// @[core.scala:292:26, :295:34, :305:{38,48}]\n wire [63:0] _debug_jalrs_0_T_14 = _debug_jalrs_0_T_13[63:0];\t// @[core.scala:305:38]\n wire _GEN_6 = _rob_io_commit_uops_0_debug_fsrc == 2'h1;\t// @[core.scala:143:32, :297:41]\n wire _debug_brs_1_T;\t// @[core.scala:297:41]\n assign _debug_brs_1_T = _GEN_6;\t// @[core.scala:297:41]\n wire _debug_jals_1_T;\t// @[core.scala:302:41]\n assign _debug_jals_1_T = _GEN_6;\t// @[core.scala:297:41, :302:41]\n wire _debug_jalrs_1_T;\t// @[core.scala:307:41]\n assign _debug_jalrs_1_T = _GEN_6;\t// @[core.scala:297:41, :307:41]\n wire _debug_brs_1_T_1 = _rob_io_commit_arch_valids_0 & _debug_brs_1_T;\t// @[core.scala:143:32, :296:36, :297:41]\n wire _debug_brs_1_T_2 = _debug_brs_1_T_1 & _rob_io_commit_uops_0_is_br;\t// @[core.scala:143:32, :296:36, :297:50]\n wire _debug_brs_1_WIRE_0 = _debug_brs_1_T_2;\t// @[core.scala:295:52, :297:50]\n wire _GEN_7 = _rob_io_commit_uops_1_debug_fsrc == 2'h1;\t// @[core.scala:143:32, :297:41]\n wire _debug_brs_1_T_3;\t// @[core.scala:297:41]\n assign _debug_brs_1_T_3 = _GEN_7;\t// @[core.scala:297:41]\n wire _debug_jals_1_T_3;\t// @[core.scala:302:41]\n assign _debug_jals_1_T_3 = _GEN_7;\t// @[core.scala:297:41, :302:41]\n wire _debug_jalrs_1_T_3;\t// @[core.scala:307:41]\n assign _debug_jalrs_1_T_3 = _GEN_7;\t// @[core.scala:297:41, :307:41]\n wire _debug_brs_1_T_4 = _rob_io_commit_arch_valids_1 & _debug_brs_1_T_3;\t// @[core.scala:143:32, :296:36, :297:41]\n wire _debug_brs_1_T_5 = _debug_brs_1_T_4 & _rob_io_commit_uops_1_is_br;\t// @[core.scala:143:32, :296:36, :297:50]\n wire _debug_brs_1_WIRE_1 = _debug_brs_1_T_5;\t// @[core.scala:295:52, :297:50]\n wire _GEN_8 = _rob_io_commit_uops_2_debug_fsrc == 2'h1;\t// @[core.scala:143:32, :297:41]\n wire _debug_brs_1_T_6;\t// @[core.scala:297:41]\n assign _debug_brs_1_T_6 = _GEN_8;\t// @[core.scala:297:41]\n wire _debug_jals_1_T_6;\t// @[core.scala:302:41]\n assign _debug_jals_1_T_6 = _GEN_8;\t// @[core.scala:297:41, :302:41]\n wire _debug_jalrs_1_T_6;\t// @[core.scala:307:41]\n assign _debug_jalrs_1_T_6 = _GEN_8;\t// @[core.scala:297:41, :307:41]\n wire _debug_brs_1_T_7 = _rob_io_commit_arch_valids_2 & _debug_brs_1_T_6;\t// @[core.scala:143:32, :296:36, :297:41]\n wire _debug_brs_1_T_8 = _debug_brs_1_T_7 & _rob_io_commit_uops_2_is_br;\t// @[core.scala:143:32, :296:36, :297:50]\n wire _debug_brs_1_WIRE_2 = _debug_brs_1_T_8;\t// @[core.scala:295:52, :297:50]\n wire [1:0] _debug_brs_1_T_9 = {1'h0, _debug_brs_1_WIRE_1} + {1'h0, _debug_brs_1_WIRE_2};\t// @[core.scala:295:{44,52}]\n wire [1:0] _debug_brs_1_T_10 = _debug_brs_1_T_9;\t// @[core.scala:295:44]\n wire [2:0] _debug_brs_1_T_11 = {2'h0, _debug_brs_1_WIRE_0} + {1'h0, _debug_brs_1_T_10};\t// @[core.scala:295:{44,52}]\n wire [1:0] _debug_brs_1_T_12 = _debug_brs_1_T_11[1:0];\t// @[core.scala:295:44]\n wire [64:0] _debug_brs_1_T_13 = {1'h0, debug_brs_1} + {63'h0, _debug_brs_1_T_12};\t// @[core.scala:290:26, :295:{34,44}]\n wire [63:0] _debug_brs_1_T_14 = _debug_brs_1_T_13[63:0];\t// @[core.scala:295:34]\n wire _debug_jals_1_T_1 = _rob_io_commit_arch_valids_0 & _debug_jals_1_T;\t// @[core.scala:143:32, :301:36, :302:41]\n wire _debug_jals_1_T_2 = _debug_jals_1_T_1 & _rob_io_commit_uops_0_is_jal;\t// @[core.scala:143:32, :301:36, :302:50]\n wire _debug_jals_1_WIRE_0 = _debug_jals_1_T_2;\t// @[core.scala:300:54, :302:50]\n wire _debug_jals_1_T_4 = _rob_io_commit_arch_valids_1 & _debug_jals_1_T_3;\t// @[core.scala:143:32, :301:36, :302:41]\n wire _debug_jals_1_T_5 = _debug_jals_1_T_4 & _rob_io_commit_uops_1_is_jal;\t// @[core.scala:143:32, :301:36, :302:50]\n wire _debug_jals_1_WIRE_1 = _debug_jals_1_T_5;\t// @[core.scala:300:54, :302:50]\n wire _debug_jals_1_T_7 = _rob_io_commit_arch_valids_2 & _debug_jals_1_T_6;\t// @[core.scala:143:32, :301:36, :302:41]\n wire _debug_jals_1_T_8 = _debug_jals_1_T_7 & _rob_io_commit_uops_2_is_jal;\t// @[core.scala:143:32, :301:36, :302:50]\n wire _debug_jals_1_WIRE_2 = _debug_jals_1_T_8;\t// @[core.scala:300:54, :302:50]\n wire [1:0] _debug_jals_1_T_9 = {1'h0, _debug_jals_1_WIRE_1} + {1'h0, _debug_jals_1_WIRE_2};\t// @[core.scala:300:{46,54}]\n wire [1:0] _debug_jals_1_T_10 = _debug_jals_1_T_9;\t// @[core.scala:300:46]\n wire [2:0] _debug_jals_1_T_11 = {2'h0, _debug_jals_1_WIRE_0} + {1'h0, _debug_jals_1_T_10};\t// @[core.scala:300:{46,54}]\n wire [1:0] _debug_jals_1_T_12 = _debug_jals_1_T_11[1:0];\t// @[core.scala:300:46]\n wire [64:0] _debug_jals_1_T_13 = {1'h0, debug_jals_1} + {63'h0, _debug_jals_1_T_12};\t// @[core.scala:291:26, :295:34, :300:{36,46}]\n wire [63:0] _debug_jals_1_T_14 = _debug_jals_1_T_13[63:0];\t// @[core.scala:300:36]\n wire _debug_jalrs_1_T_1 = _rob_io_commit_arch_valids_0 & _debug_jalrs_1_T;\t// @[core.scala:143:32, :306:36, :307:41]\n wire _debug_jalrs_1_T_2 = _debug_jalrs_1_T_1 & _rob_io_commit_uops_0_is_jalr;\t// @[core.scala:143:32, :306:36, :307:50]\n wire _debug_jalrs_1_WIRE_0 = _debug_jalrs_1_T_2;\t// @[core.scala:305:56, :307:50]\n wire _debug_jalrs_1_T_4 = _rob_io_commit_arch_valids_1 & _debug_jalrs_1_T_3;\t// @[core.scala:143:32, :306:36, :307:41]\n wire _debug_jalrs_1_T_5 = _debug_jalrs_1_T_4 & _rob_io_commit_uops_1_is_jalr;\t// @[core.scala:143:32, :306:36, :307:50]\n wire _debug_jalrs_1_WIRE_1 = _debug_jalrs_1_T_5;\t// @[core.scala:305:56, :307:50]\n wire _debug_jalrs_1_T_7 = _rob_io_commit_arch_valids_2 & _debug_jalrs_1_T_6;\t// @[core.scala:143:32, :306:36, :307:41]\n wire _debug_jalrs_1_T_8 = _debug_jalrs_1_T_7 & _rob_io_commit_uops_2_is_jalr;\t// @[core.scala:143:32, :306:36, :307:50]\n wire _debug_jalrs_1_WIRE_2 = _debug_jalrs_1_T_8;\t// @[core.scala:305:56, :307:50]\n wire [1:0] _debug_jalrs_1_T_9 = {1'h0, _debug_jalrs_1_WIRE_1} + {1'h0, _debug_jalrs_1_WIRE_2};\t// @[core.scala:305:{48,56}]\n wire [1:0] _debug_jalrs_1_T_10 = _debug_jalrs_1_T_9;\t// @[core.scala:305:48]\n wire [2:0] _debug_jalrs_1_T_11 = {2'h0, _debug_jalrs_1_WIRE_0} + {1'h0, _debug_jalrs_1_T_10};\t// @[core.scala:305:{48,56}]\n wire [1:0] _debug_jalrs_1_T_12 = _debug_jalrs_1_T_11[1:0];\t// @[core.scala:305:48]\n wire [64:0] _debug_jalrs_1_T_13 = {1'h0, debug_jalrs_1} + {63'h0, _debug_jalrs_1_T_12};\t// @[core.scala:292:26, :295:34, :305:{38,48}]\n wire [63:0] _debug_jalrs_1_T_14 = _debug_jalrs_1_T_13[63:0];\t// @[core.scala:305:38]\n wire _GEN_9 = _rob_io_commit_uops_0_debug_fsrc == 2'h2;\t// @[core.scala:143:32, :297:41]\n wire _debug_brs_2_T;\t// @[core.scala:297:41]\n assign _debug_brs_2_T = _GEN_9;\t// @[core.scala:297:41]\n wire _debug_jals_2_T;\t// @[core.scala:302:41]\n assign _debug_jals_2_T = _GEN_9;\t// @[core.scala:297:41, :302:41]\n wire _debug_jalrs_2_T;\t// @[core.scala:307:41]\n assign _debug_jalrs_2_T = _GEN_9;\t// @[core.scala:297:41, :307:41]\n wire _debug_brs_2_T_1 = _rob_io_commit_arch_valids_0 & _debug_brs_2_T;\t// @[core.scala:143:32, :296:36, :297:41]\n wire _debug_brs_2_T_2 = _debug_brs_2_T_1 & _rob_io_commit_uops_0_is_br;\t// @[core.scala:143:32, :296:36, :297:50]\n wire _debug_brs_2_WIRE_0 = _debug_brs_2_T_2;\t// @[core.scala:295:52, :297:50]\n wire _GEN_10 = _rob_io_commit_uops_1_debug_fsrc == 2'h2;\t// @[core.scala:143:32, :297:41]\n wire _debug_brs_2_T_3;\t// @[core.scala:297:41]\n assign _debug_brs_2_T_3 = _GEN_10;\t// @[core.scala:297:41]\n wire _debug_jals_2_T_3;\t// @[core.scala:302:41]\n assign _debug_jals_2_T_3 = _GEN_10;\t// @[core.scala:297:41, :302:41]\n wire _debug_jalrs_2_T_3;\t// @[core.scala:307:41]\n assign _debug_jalrs_2_T_3 = _GEN_10;\t// @[core.scala:297:41, :307:41]\n wire _debug_brs_2_T_4 = _rob_io_commit_arch_valids_1 & _debug_brs_2_T_3;\t// @[core.scala:143:32, :296:36, :297:41]\n wire _debug_brs_2_T_5 = _debug_brs_2_T_4 & _rob_io_commit_uops_1_is_br;\t// @[core.scala:143:32, :296:36, :297:50]\n wire _debug_brs_2_WIRE_1 = _debug_brs_2_T_5;\t// @[core.scala:295:52, :297:50]\n wire _GEN_11 = _rob_io_commit_uops_2_debug_fsrc == 2'h2;\t// @[core.scala:143:32, :297:41]\n wire _debug_brs_2_T_6;\t// @[core.scala:297:41]\n assign _debug_brs_2_T_6 = _GEN_11;\t// @[core.scala:297:41]\n wire _debug_jals_2_T_6;\t// @[core.scala:302:41]\n assign _debug_jals_2_T_6 = _GEN_11;\t// @[core.scala:297:41, :302:41]\n wire _debug_jalrs_2_T_6;\t// @[core.scala:307:41]\n assign _debug_jalrs_2_T_6 = _GEN_11;\t// @[core.scala:297:41, :307:41]\n wire _debug_brs_2_T_7 = _rob_io_commit_arch_valids_2 & _debug_brs_2_T_6;\t// @[core.scala:143:32, :296:36, :297:41]\n wire _debug_brs_2_T_8 = _debug_brs_2_T_7 & _rob_io_commit_uops_2_is_br;\t// @[core.scala:143:32, :296:36, :297:50]\n wire _debug_brs_2_WIRE_2 = _debug_brs_2_T_8;\t// @[core.scala:295:52, :297:50]\n wire [1:0] _debug_brs_2_T_9 = {1'h0, _debug_brs_2_WIRE_1} + {1'h0, _debug_brs_2_WIRE_2};\t// @[core.scala:295:{44,52}]\n wire [1:0] _debug_brs_2_T_10 = _debug_brs_2_T_9;\t// @[core.scala:295:44]\n wire [2:0] _debug_brs_2_T_11 = {2'h0, _debug_brs_2_WIRE_0} + {1'h0, _debug_brs_2_T_10};\t// @[core.scala:295:{44,52}]\n wire [1:0] _debug_brs_2_T_12 = _debug_brs_2_T_11[1:0];\t// @[core.scala:295:44]\n wire [64:0] _debug_brs_2_T_13 = {1'h0, debug_brs_2} + {63'h0, _debug_brs_2_T_12};\t// @[core.scala:290:26, :295:{34,44}]\n wire [63:0] _debug_brs_2_T_14 = _debug_brs_2_T_13[63:0];\t// @[core.scala:295:34]\n wire _debug_jals_2_T_1 = _rob_io_commit_arch_valids_0 & _debug_jals_2_T;\t// @[core.scala:143:32, :301:36, :302:41]\n wire _debug_jals_2_T_2 = _debug_jals_2_T_1 & _rob_io_commit_uops_0_is_jal;\t// @[core.scala:143:32, :301:36, :302:50]\n wire _debug_jals_2_WIRE_0 = _debug_jals_2_T_2;\t// @[core.scala:300:54, :302:50]\n wire _debug_jals_2_T_4 = _rob_io_commit_arch_valids_1 & _debug_jals_2_T_3;\t// @[core.scala:143:32, :301:36, :302:41]\n wire _debug_jals_2_T_5 = _debug_jals_2_T_4 & _rob_io_commit_uops_1_is_jal;\t// @[core.scala:143:32, :301:36, :302:50]\n wire _debug_jals_2_WIRE_1 = _debug_jals_2_T_5;\t// @[core.scala:300:54, :302:50]\n wire _debug_jals_2_T_7 = _rob_io_commit_arch_valids_2 & _debug_jals_2_T_6;\t// @[core.scala:143:32, :301:36, :302:41]\n wire _debug_jals_2_T_8 = _debug_jals_2_T_7 & _rob_io_commit_uops_2_is_jal;\t// @[core.scala:143:32, :301:36, :302:50]\n wire _debug_jals_2_WIRE_2 = _debug_jals_2_T_8;\t// @[core.scala:300:54, :302:50]\n wire [1:0] _debug_jals_2_T_9 = {1'h0, _debug_jals_2_WIRE_1} + {1'h0, _debug_jals_2_WIRE_2};\t// @[core.scala:300:{46,54}]\n wire [1:0] _debug_jals_2_T_10 = _debug_jals_2_T_9;\t// @[core.scala:300:46]\n wire [2:0] _debug_jals_2_T_11 = {2'h0, _debug_jals_2_WIRE_0} + {1'h0, _debug_jals_2_T_10};\t// @[core.scala:300:{46,54}]\n wire [1:0] _debug_jals_2_T_12 = _debug_jals_2_T_11[1:0];\t// @[core.scala:300:46]\n wire [64:0] _debug_jals_2_T_13 = {1'h0, debug_jals_2} + {63'h0, _debug_jals_2_T_12};\t// @[core.scala:291:26, :295:34, :300:{36,46}]\n wire [63:0] _debug_jals_2_T_14 = _debug_jals_2_T_13[63:0];\t// @[core.scala:300:36]\n wire _debug_jalrs_2_T_1 = _rob_io_commit_arch_valids_0 & _debug_jalrs_2_T;\t// @[core.scala:143:32, :306:36, :307:41]\n wire _debug_jalrs_2_T_2 = _debug_jalrs_2_T_1 & _rob_io_commit_uops_0_is_jalr;\t// @[core.scala:143:32, :306:36, :307:50]\n wire _debug_jalrs_2_WIRE_0 = _debug_jalrs_2_T_2;\t// @[core.scala:305:56, :307:50]\n wire _debug_jalrs_2_T_4 = _rob_io_commit_arch_valids_1 & _debug_jalrs_2_T_3;\t// @[core.scala:143:32, :306:36, :307:41]\n wire _debug_jalrs_2_T_5 = _debug_jalrs_2_T_4 & _rob_io_commit_uops_1_is_jalr;\t// @[core.scala:143:32, :306:36, :307:50]\n wire _debug_jalrs_2_WIRE_1 = _debug_jalrs_2_T_5;\t// @[core.scala:305:56, :307:50]\n wire _debug_jalrs_2_T_7 = _rob_io_commit_arch_valids_2 & _debug_jalrs_2_T_6;\t// @[core.scala:143:32, :306:36, :307:41]\n wire _debug_jalrs_2_T_8 = _debug_jalrs_2_T_7 & _rob_io_commit_uops_2_is_jalr;\t// @[core.scala:143:32, :306:36, :307:50]\n wire _debug_jalrs_2_WIRE_2 = _debug_jalrs_2_T_8;\t// @[core.scala:305:56, :307:50]\n wire [1:0] _debug_jalrs_2_T_9 = {1'h0, _debug_jalrs_2_WIRE_1} + {1'h0, _debug_jalrs_2_WIRE_2};\t// @[core.scala:305:{48,56}]\n wire [1:0] _debug_jalrs_2_T_10 = _debug_jalrs_2_T_9;\t// @[core.scala:305:48]\n wire [2:0] _debug_jalrs_2_T_11 = {2'h0, _debug_jalrs_2_WIRE_0} + {1'h0, _debug_jalrs_2_T_10};\t// @[core.scala:305:{48,56}]\n wire [1:0] _debug_jalrs_2_T_12 = _debug_jalrs_2_T_11[1:0];\t// @[core.scala:305:48]\n wire [64:0] _debug_jalrs_2_T_13 = {1'h0, debug_jalrs_2} + {63'h0, _debug_jalrs_2_T_12};\t// @[core.scala:292:26, :295:34, :305:{38,48}]\n wire [63:0] _debug_jalrs_2_T_14 = _debug_jalrs_2_T_13[63:0];\t// @[core.scala:305:38]\n wire _debug_brs_3_T = &_rob_io_commit_uops_0_debug_fsrc;\t// @[core.scala:143:32, :297:41]\n wire _debug_brs_3_T_1 = _rob_io_commit_arch_valids_0 & _debug_brs_3_T;\t// @[core.scala:143:32, :296:36, :297:41]\n wire _debug_brs_3_T_2 = _debug_brs_3_T_1 & _rob_io_commit_uops_0_is_br;\t// @[core.scala:143:32, :296:36, :297:50]\n wire _debug_brs_3_WIRE_0 = _debug_brs_3_T_2;\t// @[core.scala:295:52, :297:50]\n wire _debug_brs_3_T_3 = &_rob_io_commit_uops_1_debug_fsrc;\t// @[core.scala:143:32, :297:41]\n wire _debug_brs_3_T_4 = _rob_io_commit_arch_valids_1 & _debug_brs_3_T_3;\t// @[core.scala:143:32, :296:36, :297:41]\n wire _debug_brs_3_T_5 = _debug_brs_3_T_4 & _rob_io_commit_uops_1_is_br;\t// @[core.scala:143:32, :296:36, :297:50]\n wire _debug_brs_3_WIRE_1 = _debug_brs_3_T_5;\t// @[core.scala:295:52, :297:50]\n wire _debug_brs_3_T_6 = &_rob_io_commit_uops_2_debug_fsrc;\t// @[core.scala:143:32, :297:41]\n wire _debug_brs_3_T_7 = _rob_io_commit_arch_valids_2 & _debug_brs_3_T_6;\t// @[core.scala:143:32, :296:36, :297:41]\n wire _debug_brs_3_T_8 = _debug_brs_3_T_7 & _rob_io_commit_uops_2_is_br;\t// @[core.scala:143:32, :296:36, :297:50]\n wire _debug_brs_3_WIRE_2 = _debug_brs_3_T_8;\t// @[core.scala:295:52, :297:50]\n wire [1:0] _debug_brs_3_T_9 = {1'h0, _debug_brs_3_WIRE_1} + {1'h0, _debug_brs_3_WIRE_2};\t// @[core.scala:295:{44,52}]\n wire [1:0] _debug_brs_3_T_10 = _debug_brs_3_T_9;\t// @[core.scala:295:44]\n wire [2:0] _debug_brs_3_T_11 = {2'h0, _debug_brs_3_WIRE_0} + {1'h0, _debug_brs_3_T_10};\t// @[core.scala:295:{44,52}]\n wire [1:0] _debug_brs_3_T_12 = _debug_brs_3_T_11[1:0];\t// @[core.scala:295:44]\n wire [64:0] _debug_brs_3_T_13 = {1'h0, debug_brs_3} + {63'h0, _debug_brs_3_T_12};\t// @[core.scala:290:26, :295:{34,44}]\n wire [63:0] _debug_brs_3_T_14 = _debug_brs_3_T_13[63:0];\t// @[core.scala:295:34]\n wire _debug_jals_3_T = &_rob_io_commit_uops_0_debug_fsrc;\t// @[core.scala:143:32, :297:41, :302:41]\n wire _debug_jals_3_T_1 = _rob_io_commit_arch_valids_0 & _debug_jals_3_T;\t// @[core.scala:143:32, :301:36, :302:41]\n wire _debug_jals_3_T_2 = _debug_jals_3_T_1 & _rob_io_commit_uops_0_is_jal;\t// @[core.scala:143:32, :301:36, :302:50]\n wire _debug_jals_3_WIRE_0 = _debug_jals_3_T_2;\t// @[core.scala:300:54, :302:50]\n wire _debug_jals_3_T_3 = &_rob_io_commit_uops_1_debug_fsrc;\t// @[core.scala:143:32, :297:41, :302:41]\n wire _debug_jals_3_T_4 = _rob_io_commit_arch_valids_1 & _debug_jals_3_T_3;\t// @[core.scala:143:32, :301:36, :302:41]\n wire _debug_jals_3_T_5 = _debug_jals_3_T_4 & _rob_io_commit_uops_1_is_jal;\t// @[core.scala:143:32, :301:36, :302:50]\n wire _debug_jals_3_WIRE_1 = _debug_jals_3_T_5;\t// @[core.scala:300:54, :302:50]\n wire _debug_jals_3_T_6 = &_rob_io_commit_uops_2_debug_fsrc;\t// @[core.scala:143:32, :297:41, :302:41]\n wire _debug_jals_3_T_7 = _rob_io_commit_arch_valids_2 & _debug_jals_3_T_6;\t// @[core.scala:143:32, :301:36, :302:41]\n wire _debug_jals_3_T_8 = _debug_jals_3_T_7 & _rob_io_commit_uops_2_is_jal;\t// @[core.scala:143:32, :301:36, :302:50]\n wire _debug_jals_3_WIRE_2 = _debug_jals_3_T_8;\t// @[core.scala:300:54, :302:50]\n wire [1:0] _debug_jals_3_T_9 = {1'h0, _debug_jals_3_WIRE_1} + {1'h0, _debug_jals_3_WIRE_2};\t// @[core.scala:300:{46,54}]\n wire [1:0] _debug_jals_3_T_10 = _debug_jals_3_T_9;\t// @[core.scala:300:46]\n wire [2:0] _debug_jals_3_T_11 = {2'h0, _debug_jals_3_WIRE_0} + {1'h0, _debug_jals_3_T_10};\t// @[core.scala:300:{46,54}]\n wire [1:0] _debug_jals_3_T_12 = _debug_jals_3_T_11[1:0];\t// @[core.scala:300:46]\n wire [64:0] _debug_jals_3_T_13 = {1'h0, debug_jals_3} + {63'h0, _debug_jals_3_T_12};\t// @[core.scala:291:26, :295:34, :300:{36,46}]\n wire [63:0] _debug_jals_3_T_14 = _debug_jals_3_T_13[63:0];\t// @[core.scala:300:36]\n wire _debug_jalrs_3_T = &_rob_io_commit_uops_0_debug_fsrc;\t// @[core.scala:143:32, :297:41, :307:41]\n wire _debug_jalrs_3_T_1 = _rob_io_commit_arch_valids_0 & _debug_jalrs_3_T;\t// @[core.scala:143:32, :306:36, :307:41]\n wire _debug_jalrs_3_T_2 = _debug_jalrs_3_T_1 & _rob_io_commit_uops_0_is_jalr;\t// @[core.scala:143:32, :306:36, :307:50]\n wire _debug_jalrs_3_WIRE_0 = _debug_jalrs_3_T_2;\t// @[core.scala:305:56, :307:50]\n wire _debug_jalrs_3_T_3 = &_rob_io_commit_uops_1_debug_fsrc;\t// @[core.scala:143:32, :297:41, :307:41]\n wire _debug_jalrs_3_T_4 = _rob_io_commit_arch_valids_1 & _debug_jalrs_3_T_3;\t// @[core.scala:143:32, :306:36, :307:41]\n wire _debug_jalrs_3_T_5 = _debug_jalrs_3_T_4 & _rob_io_commit_uops_1_is_jalr;\t// @[core.scala:143:32, :306:36, :307:50]\n wire _debug_jalrs_3_WIRE_1 = _debug_jalrs_3_T_5;\t// @[core.scala:305:56, :307:50]\n wire _debug_jalrs_3_T_6 = &_rob_io_commit_uops_2_debug_fsrc;\t// @[core.scala:143:32, :297:41, :307:41]\n wire _debug_jalrs_3_T_7 = _rob_io_commit_arch_valids_2 & _debug_jalrs_3_T_6;\t// @[core.scala:143:32, :306:36, :307:41]\n wire _debug_jalrs_3_T_8 = _debug_jalrs_3_T_7 & _rob_io_commit_uops_2_is_jalr;\t// @[core.scala:143:32, :306:36, :307:50]\n wire _debug_jalrs_3_WIRE_2 = _debug_jalrs_3_T_8;\t// @[core.scala:305:56, :307:50]\n wire [1:0] _debug_jalrs_3_T_9 = {1'h0, _debug_jalrs_3_WIRE_1} + {1'h0, _debug_jalrs_3_WIRE_2};\t// @[core.scala:305:{48,56}]\n wire [1:0] _debug_jalrs_3_T_10 = _debug_jalrs_3_T_9;\t// @[core.scala:305:48]\n wire [2:0] _debug_jalrs_3_T_11 = {2'h0, _debug_jalrs_3_WIRE_0} + {1'h0, _debug_jalrs_3_T_10};\t// @[core.scala:305:{48,56}]\n wire [1:0] _debug_jalrs_3_T_12 = _debug_jalrs_3_T_11[1:0];\t// @[core.scala:305:48]\n wire [64:0] _debug_jalrs_3_T_13 = {1'h0, debug_jalrs_3} + {63'h0, _debug_jalrs_3_T_12};\t// @[core.scala:292:26, :295:34, :305:{38,48}]\n wire [63:0] _debug_jalrs_3_T_14 = _debug_jalrs_3_T_13[63:0];\t// @[core.scala:305:38]\n wire [64:0] _debug_tsc_reg_T = {1'h0, debug_tsc_reg} + 65'h1;\t// @[core.scala:288:30, :316:34]\n wire [63:0] _debug_tsc_reg_T_1 = _debug_tsc_reg_T[63:0];\t// @[core.scala:316:34]\n wire [1:0] _GEN_12 = {_rob_io_commit_arch_valids_2, _rob_io_commit_arch_valids_1};\t// @[core.scala:143:32, :317:71]\n wire [1:0] debug_irt_reg_hi;\t// @[core.scala:317:71]\n assign debug_irt_reg_hi = _GEN_12;\t// @[core.scala:317:71]\n wire [1:0] csr_io_retire_hi;\t// @[core.scala:1015:66]\n assign csr_io_retire_hi = _GEN_12;\t// @[core.scala:317:71, :1015:66]\n wire [2:0] _debug_irt_reg_T = {debug_irt_reg_hi, _rob_io_commit_arch_valids_0};\t// @[core.scala:143:32, :317:71]\n wire _debug_irt_reg_T_1 = _debug_irt_reg_T[0];\t// @[core.scala:317:{44,71}]\n wire _debug_irt_reg_T_2 = _debug_irt_reg_T[1];\t// @[core.scala:317:{44,71}]\n wire _debug_irt_reg_T_3 = _debug_irt_reg_T[2];\t// @[core.scala:317:{44,71}]\n wire [1:0] _debug_irt_reg_T_4 = {1'h0, _debug_irt_reg_T_2} + {1'h0, _debug_irt_reg_T_3};\t// @[core.scala:317:44]\n wire [1:0] _debug_irt_reg_T_5 = _debug_irt_reg_T_4;\t// @[core.scala:317:44]\n wire [2:0] _debug_irt_reg_T_6 = {2'h0, _debug_irt_reg_T_1} + {1'h0, _debug_irt_reg_T_5};\t// @[core.scala:317:44]\n wire [1:0] _debug_irt_reg_T_7 = _debug_irt_reg_T_6[1:0];\t// @[core.scala:317:44]\n wire [64:0] _debug_irt_reg_T_8 = {1'h0, debug_irt_reg} + {63'h0, _debug_irt_reg_T_7};\t// @[core.scala:289:30, :295:34, :317:{34,44}]\n wire [63:0] _debug_irt_reg_T_9 = _debug_irt_reg_T_8[63:0];\t// @[core.scala:317:34]\n wire _io_ifu_flush_icache_T = _rob_io_commit_arch_valids_0 & _rob_io_commit_uops_0_is_fencei;\t// @[core.scala:143:32, :388:35]\n wire _io_ifu_flush_icache_T_1 = dec_valids_0 & dec_uops_0_is_jalr;\t// @[core.scala:157:24, :158:24, :389:28]\n wire _io_ifu_flush_icache_T_2 = _io_ifu_flush_icache_T_1 & _csr_io_status_debug;\t// @[core.scala:271:19, :389:{28,51}]\n reg io_ifu_flush_icache_REG;\t// @[core.scala:389:13]\n wire _io_ifu_flush_icache_T_3 = _io_ifu_flush_icache_T | io_ifu_flush_icache_REG;\t// @[core.scala:388:{35,71}, :389:13]\n wire _io_ifu_flush_icache_T_4 = _rob_io_commit_arch_valids_1 & _rob_io_commit_uops_1_is_fencei;\t// @[core.scala:143:32, :388:35]\n wire _io_ifu_flush_icache_T_5 = dec_valids_1 & dec_uops_1_is_jalr;\t// @[core.scala:157:24, :158:24, :389:28]\n wire _io_ifu_flush_icache_T_6 = _io_ifu_flush_icache_T_5 & _csr_io_status_debug;\t// @[core.scala:271:19, :389:{28,51}]\n reg io_ifu_flush_icache_REG_1;\t// @[core.scala:389:13]\n wire _io_ifu_flush_icache_T_7 = _io_ifu_flush_icache_T_4 | io_ifu_flush_icache_REG_1;\t// @[core.scala:388:{35,71}, :389:13]\n wire _io_ifu_flush_icache_T_8 = _rob_io_commit_arch_valids_2 & _rob_io_commit_uops_2_is_fencei;\t// @[core.scala:143:32, :388:35]\n wire _io_ifu_flush_icache_T_9 = dec_valids_2 & dec_uops_2_is_jalr;\t// @[core.scala:157:24, :158:24, :389:28]\n wire _io_ifu_flush_icache_T_10 = _io_ifu_flush_icache_T_9 & _csr_io_status_debug;\t// @[core.scala:271:19, :389:{28,51}]\n reg io_ifu_flush_icache_REG_2;\t// @[core.scala:389:13]\n wire _io_ifu_flush_icache_T_11 = _io_ifu_flush_icache_T_8 | io_ifu_flush_icache_REG_2;\t// @[core.scala:388:{35,71}, :389:13]\n wire _io_ifu_flush_icache_T_12 = _io_ifu_flush_icache_T_3 | _io_ifu_flush_icache_T_7;\t// @[core.scala:388:71, :390:13]\n assign _io_ifu_flush_icache_T_13 = _io_ifu_flush_icache_T_12 | _io_ifu_flush_icache_T_11;\t// @[core.scala:388:71, :390:13]\n assign io_ifu_flush_icache_0 = _io_ifu_flush_icache_T_13;\t// @[core.scala:51:7, :390:13]\n reg REG;\t// @[core.scala:401:16]\n reg [2:0] flush_typ;\t// @[core.scala:404:28]\n wire _io_ifu_redirect_pc_T = flush_typ == 3'h3;\t// @[core.scala:404:28, :411:44]\n reg [39:0] io_ifu_redirect_pc_REG;\t// @[core.scala:412:49]\n reg [39:0] io_ifu_redirect_pc_REG_1;\t// @[core.scala:412:41]\n wire [39:0] _io_ifu_redirect_pc_T_1 = _io_ifu_redirect_pc_T ? io_ifu_redirect_pc_REG_1 : _csr_io_evec;\t// @[core.scala:271:19, :411:{33,44}, :412:41]\n wire [39:0] _flush_pc_T = ~io_ifu_get_pc_0_pc_0;\t// @[util.scala:237:7]\n wire [39:0] _flush_pc_T_1 = {_flush_pc_T[39:6], 6'h3F};\t// @[util.scala:237:{7,11}]\n wire [39:0] _flush_pc_T_2 = ~_flush_pc_T_1;\t// @[util.scala:237:{5,11}]\n reg [5:0] flush_pc_REG;\t// @[core.scala:416:32]\n wire [40:0] _flush_pc_T_3 = {1'h0, _flush_pc_T_2} + {35'h0, flush_pc_REG};\t// @[util.scala:237:5]\n wire [39:0] _flush_pc_T_4 = _flush_pc_T_3[39:0];\t// @[core.scala:416:23]\n reg flush_pc_REG_1;\t// @[core.scala:417:36]\n wire [1:0] _flush_pc_T_5 = {flush_pc_REG_1, 1'h0};\t// @[core.scala:417:{28,36}]\n wire [40:0] _flush_pc_T_6 = {1'h0, _flush_pc_T_4} - {39'h0, _flush_pc_T_5};\t// @[core.scala:416:23, :417:{23,28}]\n wire [39:0] flush_pc = _flush_pc_T_6[39:0];\t// @[core.scala:417:23]\n reg flush_pc_next_REG;\t// @[core.scala:418:49]\n wire [2:0] _flush_pc_next_T = flush_pc_next_REG ? 3'h2 : 3'h4;\t// @[core.scala:418:{41,49}]\n wire [40:0] _flush_pc_next_T_1 = {1'h0, flush_pc} + {38'h0, _flush_pc_next_T};\t// @[core.scala:417:23, :418:{36,41}]\n wire [39:0] flush_pc_next = _flush_pc_next_T_1[39:0];\t// @[core.scala:418:36]\n wire _io_ifu_redirect_pc_T_2 = flush_typ == 3'h2;\t// @[rob.scala:167:40]\n wire [39:0] _io_ifu_redirect_pc_T_3 = _io_ifu_redirect_pc_T_2 ? flush_pc : flush_pc_next;\t// @[rob.scala:167:40]\n reg [4:0] io_ifu_redirect_ftq_idx_REG;\t// @[core.scala:423:39]\n reg REG_1;\t// @[core.scala:424:50]\n wire _T_18 = brupdate_b2_mispredict & ~REG_1;\t// @[core.scala:188:23, :424:{39,42,50}]\n wire [39:0] _block_pc_T = ~io_ifu_get_pc_1_pc_0;\t// @[util.scala:237:7]\n wire [39:0] _block_pc_T_1 = {_block_pc_T[39:6], 6'h3F};\t// @[util.scala:237:{7,11}]\n wire [39:0] block_pc = ~_block_pc_T_1;\t// @[util.scala:237:{5,11}]\n wire [39:0] uop_maybe_pc = {block_pc[39:6], block_pc[5:0] | brupdate_b2_uop_pc_lob};\t// @[util.scala:237:5]\n wire [39:0] _jal_br_target_T = uop_maybe_pc;\t// @[core.scala:426:33, :429:36]\n wire _npc_T = brupdate_b2_uop_is_rvc | brupdate_b2_uop_edge_inst;\t// @[core.scala:188:23, :427:57]\n wire [2:0] _npc_T_1 = _npc_T ? 3'h2 : 3'h4;\t// @[core.scala:427:{33,57}]\n wire [40:0] _npc_T_2 = {1'h0, uop_maybe_pc} + {38'h0, _npc_T_1};\t// @[core.scala:418:36, :426:33, :427:{28,33}]\n wire [39:0] npc = _npc_T_2[39:0];\t// @[core.scala:427:28]\n wire [39:0] _jal_br_target_T_10;\t// @[core.scala:430:75]\n wire [39:0] jal_br_target;\t// @[core.scala:428:29]\n wire [40:0] _jal_br_target_T_1 = {_jal_br_target_T[39], _jal_br_target_T} + {{20{brupdate_b2_target_offset[20]}}, brupdate_b2_target_offset};\t// @[core.scala:188:23, :429:{36,43}]\n wire [39:0] _jal_br_target_T_2 = _jal_br_target_T_1[39:0];\t// @[core.scala:429:43]\n wire [39:0] _jal_br_target_T_3 = _jal_br_target_T_2;\t// @[core.scala:429:43]\n wire [38:0] _jal_br_target_T_4 = {39{brupdate_b2_uop_edge_inst}};\t// @[core.scala:188:23, :430:12]\n wire [39:0] _jal_br_target_T_5 = {_jal_br_target_T_4, 1'h0};\t// @[core.scala:430:{12,61}]\n wire [39:0] _jal_br_target_T_6 = _jal_br_target_T_5;\t// @[core.scala:430:{61,67}]\n wire [40:0] _jal_br_target_T_7 = {_jal_br_target_T_3[39], _jal_br_target_T_3} + {_jal_br_target_T_6[39], _jal_br_target_T_6};\t// @[core.scala:429:{43,71}, :430:67]\n wire [39:0] _jal_br_target_T_8 = _jal_br_target_T_7[39:0];\t// @[core.scala:429:71]\n wire [39:0] _jal_br_target_T_9 = _jal_br_target_T_8;\t// @[core.scala:429:71]\n assign _jal_br_target_T_10 = _jal_br_target_T_9;\t// @[core.scala:429:71, :430:75]\n assign jal_br_target = _jal_br_target_T_10;\t// @[core.scala:428:29, :430:75]\n wire _bj_addr_T = brupdate_b2_cfi_type == 3'h3;\t// @[core.scala:188:23, :431:44]\n wire [39:0] bj_addr = _bj_addr_T ? brupdate_b2_jalr_target : jal_br_target;\t// @[core.scala:188:23, :428:29, :431:{22,44}]\n wire _mispredict_target_T = brupdate_b2_pc_sel == 2'h0;\t// @[core.scala:188:23, :432:52]\n wire [39:0] mispredict_target = _mispredict_target_T ? npc : bj_addr;\t// @[core.scala:427:28, :431:22, :432:{32,52}]\n assign io_ifu_redirect_val_0 = REG | _T_18;\t// @[core.scala:51:7, :401:{16,38}, :402:27, :424:{39,72}]\n assign io_ifu_redirect_pc_0 = REG ? (flush_typ[0] ? _io_ifu_redirect_pc_T_1 : _io_ifu_redirect_pc_T_3) : mispredict_target;\t// @[rob.scala:166:40]\n assign io_ifu_redirect_ftq_idx_0 = REG ? io_ifu_redirect_ftq_idx_REG : brupdate_b2_uop_ftq_idx;\t// @[core.scala:51:7, :188:23, :401:{16,38}, :423:{29,39}, :424:72]\n wire _GEN_13 = brupdate_b2_cfi_type == 3'h1;\t// @[core.scala:188:23, :437:48]\n wire _use_same_ghist_T;\t// @[core.scala:437:48]\n assign _use_same_ghist_T = _GEN_13;\t// @[core.scala:437:48]\n wire _next_ghist_T;\t// @[core.scala:447:28]\n assign _next_ghist_T = _GEN_13;\t// @[core.scala:437:48, :447:28]\n wire _use_same_ghist_T_1 = ~brupdate_b2_taken;\t// @[core.scala:188:23, :438:27]\n wire _use_same_ghist_T_2 = _use_same_ghist_T & _use_same_ghist_T_1;\t// @[core.scala:437:{48,59}, :438:27]\n wire [39:0] _use_same_ghist_T_3 = ~block_pc;\t// @[util.scala:237:5]\n wire [39:0] _use_same_ghist_T_4 = {_use_same_ghist_T_3[39:3], 3'h7};\t// @[frontend.scala:160:{33,39}]\n wire [39:0] _use_same_ghist_T_5 = ~_use_same_ghist_T_4;\t// @[frontend.scala:160:{31,39}]\n wire [39:0] _use_same_ghist_T_6 = ~npc;\t// @[frontend.scala:160:33]\n wire [39:0] _use_same_ghist_T_7 = {_use_same_ghist_T_6[39:3], 3'h7};\t// @[frontend.scala:160:{33,39}]\n wire [39:0] _use_same_ghist_T_8 = ~_use_same_ghist_T_7;\t// @[frontend.scala:160:{31,39}]\n wire _use_same_ghist_T_9 = _use_same_ghist_T_5 == _use_same_ghist_T_8;\t// @[frontend.scala:160:31]\n wire use_same_ghist = _use_same_ghist_T_2 & _use_same_ghist_T_9;\t// @[core.scala:437:59, :438:46, :439:47]\n wire [3:0] _cfi_idx_T_2 = {_cfi_idx_T, 3'h0};\t// @[core.scala:442:{10,32}]\n wire [5:0] _cfi_idx_T_3 = {brupdate_b2_uop_pc_lob[5:4], brupdate_b2_uop_pc_lob[3:0] ^ _cfi_idx_T_2};\t// @[core.scala:188:23, :441:43, :442:10]\n wire [2:0] cfi_idx = _cfi_idx_T_3[3:1];\t// @[core.scala:441:43, :442:74]\n wire [2:0] next_ghist_cfi_idx_fixed = cfi_idx;\t// @[frontend.scala:85:32]\n wire _GEN_14 = io_ifu_get_pc_1_entry_cfi_idx_bits_0 == cfi_idx;\t// @[core.scala:51:7, :442:74, :451:55]\n wire _next_ghist_T_1;\t// @[core.scala:451:55]\n assign _next_ghist_T_1 = _GEN_14;\t// @[core.scala:451:55]\n wire _next_ghist_T_3;\t// @[core.scala:452:55]\n assign _next_ghist_T_3 = _GEN_14;\t// @[core.scala:451:55, :452:55]\n wire _next_ghist_T_2 = io_ifu_get_pc_1_entry_cfi_is_call_0 & _next_ghist_T_1;\t// @[core.scala:51:7, :451:{29,55}]\n wire _next_ghist_new_history_ras_idx_T = _next_ghist_T_2;\t// @[frontend.scala:123:42]\n wire _next_ghist_T_4 = io_ifu_get_pc_1_entry_cfi_is_ret_0 & _next_ghist_T_3;\t// @[core.scala:51:7, :452:{29,55}]\n wire _next_ghist_new_history_ras_idx_T_4 = _next_ghist_T_4;\t// @[frontend.scala:124:42]\n wire [7:0] next_ghist_cfi_idx_oh = 8'h1 << next_ghist_cfi_idx_fixed;\t// @[OneHot.scala:58:35]\n wire [7:0] _next_ghist_not_taken_branches_T = next_ghist_cfi_idx_oh;\t// @[OneHot.scala:58:35]\n wire [4:0] _next_ghist_new_history_ras_idx_T_9;\t// @[frontend.scala:123:31]\n wire [63:0] next_ghist_old_history;\t// @[frontend.scala:87:27]\n wire next_ghist_new_saw_branch_not_taken;\t// @[frontend.scala:87:27]\n wire next_ghist_new_saw_branch_taken;\t// @[frontend.scala:87:27]\n wire [4:0] next_ghist_ras_idx;\t// @[frontend.scala:87:27]\n wire [7:0] _next_ghist_not_taken_branches_T_1 = {1'h0, next_ghist_cfi_idx_oh[7:1]};\t// @[OneHot.scala:58:35]\n wire [7:0] _next_ghist_not_taken_branches_T_2 = {2'h0, next_ghist_cfi_idx_oh[7:2]};\t// @[OneHot.scala:58:35]\n wire [7:0] _next_ghist_not_taken_branches_T_3 = {3'h0, next_ghist_cfi_idx_oh[7:3]};\t// @[OneHot.scala:58:35]\n wire [7:0] _next_ghist_not_taken_branches_T_4 = {4'h0, next_ghist_cfi_idx_oh[7:4]};\t// @[OneHot.scala:58:35]\n wire [7:0] _next_ghist_not_taken_branches_T_5 = {5'h0, next_ghist_cfi_idx_oh[7:5]};\t// @[OneHot.scala:58:35]\n wire [7:0] _next_ghist_not_taken_branches_T_6 = {6'h0, next_ghist_cfi_idx_oh[7:6]};\t// @[OneHot.scala:58:35]\n wire [7:0] _next_ghist_not_taken_branches_T_7 = {7'h0, next_ghist_cfi_idx_oh[7]};\t// @[OneHot.scala:58:35]\n wire [7:0] _next_ghist_not_taken_branches_T_8 = _next_ghist_not_taken_branches_T | _next_ghist_not_taken_branches_T_1;\t// @[util.scala:373:{29,45}]\n wire [7:0] _next_ghist_not_taken_branches_T_9 = _next_ghist_not_taken_branches_T_8 | _next_ghist_not_taken_branches_T_2;\t// @[util.scala:373:{29,45}]\n wire [7:0] _next_ghist_not_taken_branches_T_10 = _next_ghist_not_taken_branches_T_9 | _next_ghist_not_taken_branches_T_3;\t// @[util.scala:373:{29,45}]\n wire [7:0] _next_ghist_not_taken_branches_T_11 = _next_ghist_not_taken_branches_T_10 | _next_ghist_not_taken_branches_T_4;\t// @[util.scala:373:{29,45}]\n wire [7:0] _next_ghist_not_taken_branches_T_12 = _next_ghist_not_taken_branches_T_11 | _next_ghist_not_taken_branches_T_5;\t// @[util.scala:373:{29,45}]\n wire [7:0] _next_ghist_not_taken_branches_T_13 = _next_ghist_not_taken_branches_T_12 | _next_ghist_not_taken_branches_T_6;\t// @[util.scala:373:{29,45}]\n wire [7:0] _next_ghist_not_taken_branches_T_14 = _next_ghist_not_taken_branches_T_13 | _next_ghist_not_taken_branches_T_7;\t// @[util.scala:373:{29,45}]\n wire _next_ghist_not_taken_branches_T_15 = _next_ghist_T & brupdate_b2_taken;\t// @[frontend.scala:90:84]\n wire [7:0] _next_ghist_not_taken_branches_T_16 = _next_ghist_not_taken_branches_T_15 ? next_ghist_cfi_idx_oh : 8'h0;\t// @[OneHot.scala:58:35]\n wire [7:0] _next_ghist_not_taken_branches_T_17 = ~_next_ghist_not_taken_branches_T_16;\t// @[frontend.scala:90:{69,73}]\n wire [7:0] _next_ghist_not_taken_branches_T_18 = _next_ghist_not_taken_branches_T_14 & _next_ghist_not_taken_branches_T_17;\t// @[util.scala:373:45]\n wire [7:0] _next_ghist_not_taken_branches_T_20 = _next_ghist_not_taken_branches_T_18;\t// @[frontend.scala:89:44, :90:67]\n wire [7:0] next_ghist_not_taken_branches = io_ifu_get_pc_1_entry_br_mask_0 & _next_ghist_not_taken_branches_T_20;\t// @[frontend.scala:89:{39,44}]\n wire [64:0] _GEN_15 = {io_ifu_get_pc_1_ghist_old_history_0, 1'h0};\t// @[frontend.scala:67:75]\n wire [64:0] _next_ghist_base_T;\t// @[frontend.scala:67:75]\n assign _next_ghist_base_T = _GEN_15;\t// @[frontend.scala:67:75]\n wire [64:0] _next_ghist_base_T_2;\t// @[frontend.scala:68:75]\n assign _next_ghist_base_T_2 = _GEN_15;\t// @[frontend.scala:67:75, :68:75]\n wire [64:0] _next_ghist_new_history_old_history_T;\t// @[frontend.scala:67:75]\n assign _next_ghist_new_history_old_history_T = _GEN_15;\t// @[frontend.scala:67:75]\n wire [64:0] _next_ghist_new_history_old_history_T_2;\t// @[frontend.scala:68:75]\n assign _next_ghist_new_history_old_history_T_2 = _GEN_15;\t// @[frontend.scala:67:75, :68:75]\n wire [64:0] _next_ghist_new_history_old_history_T_6;\t// @[frontend.scala:67:75]\n assign _next_ghist_new_history_old_history_T_6 = _GEN_15;\t// @[frontend.scala:67:75]\n wire [64:0] _next_ghist_new_history_old_history_T_8;\t// @[frontend.scala:68:75]\n assign _next_ghist_new_history_old_history_T_8 = _GEN_15;\t// @[frontend.scala:67:75, :68:75]\n wire [64:0] _next_ghist_new_history_old_history_T_13;\t// @[frontend.scala:67:75]\n assign _next_ghist_new_history_old_history_T_13 = _GEN_15;\t// @[frontend.scala:67:75]\n wire [64:0] _next_ghist_new_history_old_history_T_15;\t// @[frontend.scala:68:75]\n assign _next_ghist_new_history_old_history_T_15 = _GEN_15;\t// @[frontend.scala:67:75, :68:75]\n wire [64:0] _next_ghist_new_history_old_history_T_19;\t// @[frontend.scala:67:75]\n assign _next_ghist_new_history_old_history_T_19 = _GEN_15;\t// @[frontend.scala:67:75]\n wire [64:0] _next_ghist_new_history_old_history_T_21;\t// @[frontend.scala:68:75]\n assign _next_ghist_new_history_old_history_T_21 = _GEN_15;\t// @[frontend.scala:67:75, :68:75]\n wire [64:0] _next_ghist_base_T_1 = {_next_ghist_base_T[64:1], 1'h1};\t// @[frontend.scala:67:{75,80}]\n wire [64:0] _GEN_16 = {1'h0, io_ifu_get_pc_1_ghist_old_history_0};\t// @[frontend.scala:68:12]\n wire [64:0] _next_ghist_base_T_3 = io_ifu_get_pc_1_ghist_new_saw_branch_not_taken_0 ? _next_ghist_base_T_2 : _GEN_16;\t// @[frontend.scala:68:{12,75}]\n wire [64:0] next_ghist_base = io_ifu_get_pc_1_ghist_new_saw_branch_taken_0 ? _next_ghist_base_T_1 : _next_ghist_base_T_3;\t// @[frontend.scala:67:{12,80}, :68:12]\n wire _next_ghist_cfi_in_bank_0_T_1 = ~(next_ghist_cfi_idx_fixed[2]);\t// @[frontend.scala:85:32, :104:67]\n wire next_ghist_cfi_in_bank_0 = _next_ghist_cfi_in_bank_0_T & _next_ghist_cfi_in_bank_0_T_1;\t// @[frontend.scala:104:{37,50,67}]\n wire [2:0] _next_ghist_ignore_second_bank_T = io_ifu_get_pc_1_pc_0[5:3];\t// @[frontend.scala:152:28]\n wire _next_ghist_ignore_second_bank_T_1 = &_next_ghist_ignore_second_bank_T;\t// @[frontend.scala:152:{28,66}]\n wire _next_ghist_ignore_second_bank_T_2 = _next_ghist_ignore_second_bank_T_1;\t// @[frontend.scala:152:{21,66}]\n wire next_ghist_ignore_second_bank = next_ghist_cfi_in_bank_0 | _next_ghist_ignore_second_bank_T_2;\t// @[frontend.scala:104:50, :105:46, :152:21]\n wire [3:0] _next_ghist_first_bank_saw_not_taken_T = next_ghist_not_taken_branches[3:0];\t// @[frontend.scala:89:39, :107:56]\n wire _next_ghist_first_bank_saw_not_taken_T_1 = |_next_ghist_first_bank_saw_not_taken_T;\t// @[frontend.scala:107:{56,72}]\n wire next_ghist_first_bank_saw_not_taken = _next_ghist_first_bank_saw_not_taken_T_1 | io_ifu_get_pc_1_ghist_current_saw_branch_not_taken_0;\t// @[frontend.scala:107:{72,80}]\n wire [64:0] _next_ghist_new_history_old_history_T_1 = {_next_ghist_new_history_old_history_T[64:1], 1'h1};\t// @[frontend.scala:67:{75,80}]\n wire [64:0] _next_ghist_new_history_old_history_T_3 = io_ifu_get_pc_1_ghist_new_saw_branch_not_taken_0 ? _next_ghist_new_history_old_history_T_2 : _GEN_16;\t// @[frontend.scala:68:{12,75}]\n wire [64:0] _next_ghist_new_history_old_history_T_4 = io_ifu_get_pc_1_ghist_new_saw_branch_taken_0 ? _next_ghist_new_history_old_history_T_1 : _next_ghist_new_history_old_history_T_3;\t// @[frontend.scala:67:{12,80}, :68:12]\n wire _GEN_17 = _next_ghist_T & next_ghist_cfi_in_bank_0;\t// @[frontend.scala:104:50, :112:59]\n wire _next_ghist_new_history_new_saw_branch_taken_T;\t// @[frontend.scala:112:59]\n assign _next_ghist_new_history_new_saw_branch_taken_T = _GEN_17;\t// @[frontend.scala:112:59]\n wire _next_ghist_new_history_old_history_T_5;\t// @[frontend.scala:114:50]\n assign _next_ghist_new_history_old_history_T_5 = _GEN_17;\t// @[frontend.scala:112:59, :114:50]\n wire [64:0] _next_ghist_new_history_old_history_T_7 = {_next_ghist_new_history_old_history_T_6[64:1], 1'h1};\t// @[frontend.scala:67:{75,80}]\n wire [64:0] _next_ghist_new_history_old_history_T_9 = io_ifu_get_pc_1_ghist_new_saw_branch_not_taken_0 ? _next_ghist_new_history_old_history_T_8 : _GEN_16;\t// @[frontend.scala:68:{12,75}]\n wire [64:0] _next_ghist_new_history_old_history_T_10 = io_ifu_get_pc_1_ghist_new_saw_branch_taken_0 ? _next_ghist_new_history_old_history_T_7 : _next_ghist_new_history_old_history_T_9;\t// @[frontend.scala:67:{12,80}, :68:12]\n wire [65:0] _next_ghist_new_history_old_history_T_11 = {_next_ghist_new_history_old_history_T_10, 1'h0};\t// @[frontend.scala:67:12, :114:110]\n wire [65:0] _next_ghist_new_history_old_history_T_12 = {_next_ghist_new_history_old_history_T_11[65:1], 1'h1};\t// @[frontend.scala:114:{110,115}]\n wire [64:0] _next_ghist_new_history_old_history_T_14 = {_next_ghist_new_history_old_history_T_13[64:1], 1'h1};\t// @[frontend.scala:67:{75,80}]\n wire [64:0] _next_ghist_new_history_old_history_T_16 = io_ifu_get_pc_1_ghist_new_saw_branch_not_taken_0 ? _next_ghist_new_history_old_history_T_15 : _GEN_16;\t// @[frontend.scala:68:{12,75}]\n wire [64:0] _next_ghist_new_history_old_history_T_17 = io_ifu_get_pc_1_ghist_new_saw_branch_taken_0 ? _next_ghist_new_history_old_history_T_14 : _next_ghist_new_history_old_history_T_16;\t// @[frontend.scala:67:{12,80}, :68:12]\n wire [65:0] _next_ghist_new_history_old_history_T_18 = {_next_ghist_new_history_old_history_T_17, 1'h0};\t// @[frontend.scala:67:12, :115:110]\n wire [64:0] _next_ghist_new_history_old_history_T_20 = {_next_ghist_new_history_old_history_T_19[64:1], 1'h1};\t// @[frontend.scala:67:{75,80}]\n wire [64:0] _next_ghist_new_history_old_history_T_22 = io_ifu_get_pc_1_ghist_new_saw_branch_not_taken_0 ? _next_ghist_new_history_old_history_T_21 : _GEN_16;\t// @[frontend.scala:68:{12,75}]\n wire [64:0] _next_ghist_new_history_old_history_T_23 = io_ifu_get_pc_1_ghist_new_saw_branch_taken_0 ? _next_ghist_new_history_old_history_T_20 : _next_ghist_new_history_old_history_T_22;\t// @[frontend.scala:67:{12,80}, :68:12]\n wire [65:0] _next_ghist_new_history_old_history_T_24 = next_ghist_first_bank_saw_not_taken ? _next_ghist_new_history_old_history_T_18 : {1'h0, _next_ghist_new_history_old_history_T_23};\t// @[frontend.scala:67:12, :107:80, :115:{39,110}]\n wire [65:0] _next_ghist_new_history_old_history_T_25 = _next_ghist_new_history_old_history_T_5 ? _next_ghist_new_history_old_history_T_12 : _next_ghist_new_history_old_history_T_24;\t// @[frontend.scala:114:{39,50,115}, :115:39]\n assign next_ghist_old_history = next_ghist_ignore_second_bank ? _next_ghist_new_history_old_history_T_4[63:0] : _next_ghist_new_history_old_history_T_25[63:0];\t// @[frontend.scala:67:12, :87:27, :105:46, :109:33, :110:33, :114:{33,39}]\n wire [3:0] _next_ghist_new_history_new_saw_branch_not_taken_T = next_ghist_not_taken_branches[7:4];\t// @[frontend.scala:89:39, :118:67]\n wire _next_ghist_new_history_new_saw_branch_not_taken_T_1 = |_next_ghist_new_history_new_saw_branch_not_taken_T;\t// @[frontend.scala:118:{67,92}]\n assign next_ghist_new_saw_branch_not_taken = next_ghist_ignore_second_bank ? next_ghist_first_bank_saw_not_taken : _next_ghist_new_history_new_saw_branch_not_taken_T_1;\t// @[frontend.scala:87:27, :105:46, :107:80, :109:33, :111:46, :118:{46,92}]\n wire _next_ghist_new_history_new_saw_branch_taken_T_2 = _next_ghist_new_history_new_saw_branch_taken_T_1 & _next_ghist_T;\t// @[frontend.scala:119:{59,72}]\n wire _next_ghist_new_history_new_saw_branch_taken_T_3 = ~next_ghist_cfi_in_bank_0;\t// @[frontend.scala:104:50, :119:88]\n wire _next_ghist_new_history_new_saw_branch_taken_T_4 = _next_ghist_new_history_new_saw_branch_taken_T_2 & _next_ghist_new_history_new_saw_branch_taken_T_3;\t// @[frontend.scala:119:{72,85,88}]\n assign next_ghist_new_saw_branch_taken = next_ghist_ignore_second_bank ? _next_ghist_new_history_new_saw_branch_taken_T : _next_ghist_new_history_new_saw_branch_taken_T_4;\t// @[frontend.scala:87:27, :105:46, :109:33, :112:{46,59}, :119:{46,85}]\n wire [5:0] _GEN_18 = {1'h0, io_ifu_get_pc_1_ghist_ras_idx_0};\t// @[util.scala:203:14]\n wire [5:0] _next_ghist_new_history_ras_idx_T_1 = _GEN_18 + 6'h1;\t// @[util.scala:203:14]\n wire [4:0] _next_ghist_new_history_ras_idx_T_2 = _next_ghist_new_history_ras_idx_T_1[4:0];\t// @[util.scala:203:14]\n wire [4:0] _next_ghist_new_history_ras_idx_T_3 = _next_ghist_new_history_ras_idx_T_2;\t// @[util.scala:203:{14,20}]\n wire [5:0] _next_ghist_new_history_ras_idx_T_5 = _GEN_18 - 6'h1;\t// @[util.scala:203:14, :220:14]\n wire [4:0] _next_ghist_new_history_ras_idx_T_6 = _next_ghist_new_history_ras_idx_T_5[4:0];\t// @[util.scala:220:14]\n wire [4:0] _next_ghist_new_history_ras_idx_T_7 = _next_ghist_new_history_ras_idx_T_6;\t// @[util.scala:220:{14,20}]\n wire [4:0] _next_ghist_new_history_ras_idx_T_8 = _next_ghist_new_history_ras_idx_T_4 ? _next_ghist_new_history_ras_idx_T_7 : io_ifu_get_pc_1_ghist_ras_idx_0;\t// @[util.scala:220:20]\n assign _next_ghist_new_history_ras_idx_T_9 = _next_ghist_new_history_ras_idx_T ? _next_ghist_new_history_ras_idx_T_3 : _next_ghist_new_history_ras_idx_T_8;\t// @[util.scala:203:20]\n assign next_ghist_ras_idx = _next_ghist_new_history_ras_idx_T_9;\t// @[frontend.scala:87:27, :123:31]\n wire [63:0] _io_ifu_redirect_ghist_T_old_history = use_same_ghist ? io_ifu_get_pc_1_ghist_old_history_0 : next_ghist_old_history;\t// @[frontend.scala:87:27]\n wire _io_ifu_redirect_ghist_T_current_saw_branch_not_taken = use_same_ghist & io_ifu_get_pc_1_ghist_current_saw_branch_not_taken_0;\t// @[core.scala:51:7, :438:46, :455:35]\n wire _io_ifu_redirect_ghist_T_new_saw_branch_not_taken = use_same_ghist ? io_ifu_get_pc_1_ghist_new_saw_branch_not_taken_0 : next_ghist_new_saw_branch_not_taken;\t// @[frontend.scala:87:27]\n wire _io_ifu_redirect_ghist_T_new_saw_branch_taken = use_same_ghist ? io_ifu_get_pc_1_ghist_new_saw_branch_taken_0 : next_ghist_new_saw_branch_taken;\t// @[frontend.scala:87:27]\n wire [4:0] _io_ifu_redirect_ghist_T_ras_idx = use_same_ghist ? io_ifu_get_pc_1_ghist_ras_idx_0 : next_ghist_ras_idx;\t// @[frontend.scala:87:27]\n assign io_ifu_redirect_ghist_old_history_0 = REG ? 64'h0 : _io_ifu_redirect_ghist_T_old_history;\t// @[core.scala:51:7, :401:{16,38}, :409:27, :424:72, :455:35]\n assign io_ifu_redirect_ghist_new_saw_branch_not_taken_0 = ~REG & _io_ifu_redirect_ghist_T_new_saw_branch_not_taken;\t// @[core.scala:51:7, :401:{16,38}, :409:27, :424:72, :455:35]\n assign io_ifu_redirect_ghist_new_saw_branch_taken_0 = ~REG & _io_ifu_redirect_ghist_T_new_saw_branch_taken;\t// @[core.scala:51:7, :401:{16,38}, :409:27, :424:72, :455:35]\n assign io_ifu_redirect_ghist_ras_idx_0 = REG ? new_ghist_ras_idx : _io_ifu_redirect_ghist_T_ras_idx;\t// @[core.scala:51:7, :401:{16,38}, :406:29, :409:27, :424:72, :455:35]\n assign io_ifu_redirect_ghist_current_saw_branch_not_taken_0 = REG | use_same_ghist;\t// @[core.scala:51:7, :401:{16,38}, :409:27, :424:72, :438:46]\n assign io_ifu_redirect_flush_0 = REG | _T_18 | (|{_rob_io_flush_frontend, brupdate_b1_mispredict_mask});\t// @[core.scala:51:7, :143:32, :188:23, :224:42, :401:{16,38}, :403:27, :424:{39,72}, :435:29, :460:{38,78}]\n wire [1:0] _youngest_com_idx_T = _rob_io_commit_valids_1 ? 2'h1 : 2'h2;\t// @[Mux.scala:50:70]\n wire [1:0] _youngest_com_idx_T_1 = _rob_io_commit_valids_2 ? 2'h0 : _youngest_com_idx_T;\t// @[Mux.scala:50:70]\n wire [2:0] _youngest_com_idx_T_2 = 3'h2 - {1'h0, _youngest_com_idx_T_1};\t// @[Mux.scala:50:70]\n wire [1:0] youngest_com_idx = _youngest_com_idx_T_2[1:0];\t// @[core.scala:465:42]\n wire _io_ifu_commit_valid_T = _rob_io_commit_valids_0 | _rob_io_commit_valids_1;\t// @[core.scala:143:32, :466:55]\n wire _io_ifu_commit_valid_T_1 = _io_ifu_commit_valid_T | _rob_io_commit_valids_2;\t// @[core.scala:143:32, :466:55]\n wire _io_ifu_commit_valid_T_2 = _io_ifu_commit_valid_T_1 | _rob_io_com_xcpt_valid;\t// @[core.scala:143:32, :466:{55,59}]\n wire [3:0][4:0] _GEN_19 = {{_rob_io_commit_uops_0_ftq_idx}, {_rob_io_commit_uops_2_ftq_idx}, {_rob_io_commit_uops_1_ftq_idx}, {_rob_io_commit_uops_0_ftq_idx}};\t// @[core.scala:143:32, :467:29]\n wire [4:0] _io_ifu_commit_bits_T = _rob_io_com_xcpt_valid ? _rob_io_com_xcpt_bits_ftq_idx : _GEN_19[youngest_com_idx];\t// @[core.scala:143:32, :465:42, :467:29]\n reg REG_2;\t// @[core.scala:475:18]\n reg io_ifu_sfence_REG_valid;\t// @[core.scala:476:31]\n assign io_ifu_sfence_valid_0 = io_ifu_sfence_REG_valid;\t// @[core.scala:51:7, :476:31]\n reg io_ifu_sfence_REG_bits_rs1;\t// @[core.scala:476:31]\n assign io_ifu_sfence_bits_rs1_0 = io_ifu_sfence_REG_bits_rs1;\t// @[core.scala:51:7, :476:31]\n reg io_ifu_sfence_REG_bits_rs2;\t// @[core.scala:476:31]\n assign io_ifu_sfence_bits_rs2_0 = io_ifu_sfence_REG_bits_rs2;\t// @[core.scala:51:7, :476:31]\n reg [38:0] io_ifu_sfence_REG_bits_addr;\t// @[core.scala:476:31]\n assign io_ifu_sfence_bits_addr_0 = io_ifu_sfence_REG_bits_addr;\t// @[core.scala:51:7, :476:31]\n reg io_ifu_sfence_REG_bits_asid;\t// @[core.scala:476:31]\n assign io_ifu_sfence_bits_asid_0 = io_ifu_sfence_REG_bits_asid;\t// @[core.scala:51:7, :476:31]\n reg [2:0] dec_finished_mask;\t// @[core.scala:496:34]\n wire _dec_valids_0_T = io_ifu_fetchpacket_valid_0 & io_ifu_fetchpacket_bits_uops_0_valid_0;\t// @[core.scala:51:7, :508:68]\n wire _dec_valids_0_T_1 = dec_finished_mask[0];\t// @[core.scala:496:34, :509:61]\n wire _dec_brmask_logic_io_is_branch_0_T = dec_finished_mask[0];\t// @[core.scala:496:34, :509:61, :600:59]\n wire _dec_valids_0_T_2 = ~_dec_valids_0_T_1;\t// @[core.scala:509:{43,61}]\n assign _dec_valids_0_T_3 = _dec_valids_0_T & _dec_valids_0_T_2;\t// @[core.scala:508:{68,97}, :509:43]\n assign dec_valids_0 = _dec_valids_0_T_3;\t// @[core.scala:157:24, :508:97]\n wire _dec_valids_1_T = io_ifu_fetchpacket_valid_0 & io_ifu_fetchpacket_bits_uops_1_valid_0;\t// @[core.scala:51:7, :508:68]\n wire _dec_valids_1_T_1 = dec_finished_mask[1];\t// @[core.scala:496:34, :509:61]\n wire _dec_brmask_logic_io_is_branch_1_T = dec_finished_mask[1];\t// @[core.scala:496:34, :509:61, :600:59]\n wire _dec_valids_1_T_2 = ~_dec_valids_1_T_1;\t// @[core.scala:509:{43,61}]\n assign _dec_valids_1_T_3 = _dec_valids_1_T & _dec_valids_1_T_2;\t// @[core.scala:508:{68,97}, :509:43]\n assign dec_valids_1 = _dec_valids_1_T_3;\t// @[core.scala:157:24, :508:97]\n wire _dec_valids_2_T = io_ifu_fetchpacket_valid_0 & io_ifu_fetchpacket_bits_uops_2_valid_0;\t// @[core.scala:51:7, :508:68]\n wire _dec_valids_2_T_1 = dec_finished_mask[2];\t// @[core.scala:496:34, :509:61]\n wire _dec_brmask_logic_io_is_branch_2_T = dec_finished_mask[2];\t// @[core.scala:496:34, :509:61, :600:59]\n wire _dec_valids_2_T_2 = ~_dec_valids_2_T_1;\t// @[core.scala:509:{43,61}]\n assign _dec_valids_2_T_3 = _dec_valids_2_T & _dec_valids_2_T_2;\t// @[core.scala:508:{68,97}, :509:43]\n assign dec_valids_2 = _dec_valids_2_T_3;\t// @[core.scala:157:24, :508:97]\n wire jmp_pc_req_ready;\t// @[core.scala:522:25]\n wire jmp_pc_req_valid;\t// @[core.scala:522:25]\n wire [4:0] jmp_pc_req_bits;\t// @[core.scala:522:25]\n wire _xcpt_pc_req_valid_T_1;\t// @[core.scala:551:45]\n wire xcpt_pc_req_ready;\t// @[core.scala:523:25]\n wire xcpt_pc_req_valid;\t// @[core.scala:523:25]\n wire [4:0] xcpt_pc_req_bits;\t// @[core.scala:523:25]\n wire flush_pc_req_valid;\t// @[core.scala:524:26]\n wire [4:0] flush_pc_req_bits;\t// @[core.scala:524:26]\n wire _jmp_pc_req_valid_T = iss_uops_1_fu_code == 10'h2;\t// @[core.scala:173:24, :539:90]\n wire _jmp_pc_req_valid_T_1 = iss_valids_1 & _jmp_pc_req_valid_T;\t// @[core.scala:172:24, :539:{56,90}]\n reg jmp_pc_req_valid_REG;\t// @[core.scala:539:30]\n assign jmp_pc_req_valid = jmp_pc_req_valid_REG;\t// @[core.scala:522:25, :539:30]\n reg [4:0] jmp_pc_req_bits_REG;\t// @[core.scala:540:30]\n assign jmp_pc_req_bits = jmp_pc_req_bits_REG;\t// @[core.scala:522:25, :540:30]\n wire [1:0] _xcpt_idx_T = dec_xcpts_1 ? 2'h1 : 2'h2;\t// @[Mux.scala:50:70]\n wire [1:0] xcpt_idx = dec_xcpts_0 ? 2'h0 : _xcpt_idx_T;\t// @[Mux.scala:50:70]\n wire _GEN_20 = dec_xcpts_0 | dec_xcpts_1;\t// @[core.scala:162:24, :551:45]\n wire _xcpt_pc_req_valid_T;\t// @[core.scala:551:45]\n assign _xcpt_pc_req_valid_T = _GEN_20;\t// @[core.scala:551:45]\n wire _dec_xcpt_stall_T;\t// @[core.scala:567:42]\n assign _dec_xcpt_stall_T = _GEN_20;\t// @[core.scala:551:45, :567:42]\n assign _xcpt_pc_req_valid_T_1 = _xcpt_pc_req_valid_T | dec_xcpts_2;\t// @[core.scala:162:24, :551:45]\n assign xcpt_pc_req_valid = _xcpt_pc_req_valid_T_1;\t// @[core.scala:523:25, :551:45]\n wire [3:0][4:0] _GEN_21 = {{dec_uops_0_ftq_idx}, {dec_uops_2_ftq_idx}, {dec_uops_1_ftq_idx}, {dec_uops_0_ftq_idx}};\t// @[core.scala:158:24, :552:24]\n assign xcpt_pc_req_bits = _GEN_21[xcpt_idx];\t// @[Mux.scala:50:70]\n assign dec_xcpts_0 = dec_uops_0_exception & dec_valids_0;\t// @[core.scala:157:24, :158:24, :162:24, :566:71]\n assign dec_xcpts_1 = dec_uops_1_exception & dec_valids_1;\t// @[core.scala:157:24, :158:24, :162:24, :566:71]\n assign dec_xcpts_2 = dec_uops_2_exception & dec_valids_2;\t// @[core.scala:157:24, :158:24, :162:24, :566:71]\n wire _dec_xcpt_stall_T_1 = _dec_xcpt_stall_T | dec_xcpts_2;\t// @[core.scala:162:24, :567:42]\n wire _dec_xcpt_stall_T_2 = ~xcpt_pc_req_ready;\t// @[core.scala:523:25, :567:50]\n wire dec_xcpt_stall = _dec_xcpt_stall_T_1 & _dec_xcpt_stall_T_2;\t// @[core.scala:567:{42,47,50}]\n wire branch_mask_full_0;\t// @[core.scala:569:30]\n wire branch_mask_full_1;\t// @[core.scala:569:30]\n wire branch_mask_full_2;\t// @[core.scala:569:30]\n wire _dec_hazards_T = ~dis_ready;\t// @[core.scala:169:24, :573:26]\n wire _dec_hazards_T_1 = _dec_hazards_T | _rob_io_commit_rollback;\t// @[core.scala:143:32, :573:26, :574:23]\n wire _dec_hazards_T_2 = _dec_hazards_T_1 | dec_xcpt_stall;\t// @[core.scala:567:47, :574:23, :575:23]\n wire _dec_hazards_T_3 = _dec_hazards_T_2 | branch_mask_full_0;\t// @[core.scala:569:30, :575:23, :576:23]\n wire _dec_hazards_T_4 = |brupdate_b1_mispredict_mask;\t// @[core.scala:188:23, :224:42, :577:54]\n wire _dec_hazards_T_5 = _dec_hazards_T_3 | _dec_hazards_T_4;\t// @[core.scala:576:23, :577:{23,54}]\n wire _dec_hazards_T_6 = _dec_hazards_T_5 | brupdate_b2_mispredict;\t// @[core.scala:188:23, :577:23, :578:23]\n wire _dec_hazards_T_7 = _dec_hazards_T_6 | io_ifu_redirect_flush_0;\t// @[core.scala:51:7, :578:23, :579:23]\n wire dec_hazards_0 = dec_valids_0 & _dec_hazards_T_7;\t// @[core.scala:157:24, :572:37, :579:23]\n wire dec_stalls_0 = dec_hazards_0;\t// @[core.scala:572:37, :581:62]\n wire _dec_hazards_T_8 = ~dis_ready;\t// @[core.scala:169:24, :573:26]\n wire _dec_hazards_T_9 = _dec_hazards_T_8 | _rob_io_commit_rollback;\t// @[core.scala:143:32, :573:26, :574:23]\n wire _dec_hazards_T_10 = _dec_hazards_T_9 | dec_xcpt_stall;\t// @[core.scala:567:47, :574:23, :575:23]\n wire _dec_hazards_T_11 = _dec_hazards_T_10 | branch_mask_full_1;\t// @[core.scala:569:30, :575:23, :576:23]\n wire _dec_hazards_T_12 = |brupdate_b1_mispredict_mask;\t// @[core.scala:188:23, :224:42, :577:54]\n wire _dec_hazards_T_13 = _dec_hazards_T_11 | _dec_hazards_T_12;\t// @[core.scala:576:23, :577:{23,54}]\n wire _dec_hazards_T_14 = _dec_hazards_T_13 | brupdate_b2_mispredict;\t// @[core.scala:188:23, :577:23, :578:23]\n wire _dec_hazards_T_15 = _dec_hazards_T_14 | io_ifu_redirect_flush_0;\t// @[core.scala:51:7, :578:23, :579:23]\n wire dec_hazards_1 = dec_valids_1 & _dec_hazards_T_15;\t// @[core.scala:157:24, :572:37, :579:23]\n wire _dec_hazards_T_16 = ~dis_ready;\t// @[core.scala:169:24, :573:26]\n wire _dec_hazards_T_17 = _dec_hazards_T_16 | _rob_io_commit_rollback;\t// @[core.scala:143:32, :573:26, :574:23]\n wire _dec_hazards_T_18 = _dec_hazards_T_17 | dec_xcpt_stall;\t// @[core.scala:567:47, :574:23, :575:23]\n wire _dec_hazards_T_19 = _dec_hazards_T_18 | branch_mask_full_2;\t// @[core.scala:569:30, :575:23, :576:23]\n wire _dec_hazards_T_20 = |brupdate_b1_mispredict_mask;\t// @[core.scala:188:23, :224:42, :577:54]\n wire _dec_hazards_T_21 = _dec_hazards_T_19 | _dec_hazards_T_20;\t// @[core.scala:576:23, :577:{23,54}]\n wire _dec_hazards_T_22 = _dec_hazards_T_21 | brupdate_b2_mispredict;\t// @[core.scala:188:23, :577:23, :578:23]\n wire _dec_hazards_T_23 = _dec_hazards_T_22 | io_ifu_redirect_flush_0;\t// @[core.scala:51:7, :578:23, :579:23]\n wire dec_hazards_2 = dec_valids_2 & _dec_hazards_T_23;\t// @[core.scala:157:24, :572:37, :579:23]\n wire dec_stalls_1 = dec_stalls_0 | dec_hazards_1;\t// @[core.scala:572:37, :581:62]\n wire dec_stalls_2 = dec_stalls_1 | dec_hazards_2;\t// @[core.scala:572:37, :581:62]\n assign dec_fire_0 = dec_valids_0 & ~dec_stalls_0;\t// @[core.scala:157:24, :159:24, :581:62, :582:{58,61}]\n assign dec_fire_1 = dec_valids_1 & ~dec_stalls_1;\t// @[core.scala:157:24, :159:24, :581:62, :582:{58,61}]\n assign dec_fire_2 = dec_valids_2 & ~dec_stalls_2;\t// @[core.scala:157:24, :159:24, :581:62, :582:{58,61}]\n wire [1:0] dec_finished_mask_hi = {dec_fire_2, dec_fire_1};\t// @[core.scala:159:24, :590:35]\n wire [2:0] _dec_finished_mask_T = {dec_finished_mask_hi, dec_fire_0};\t// @[core.scala:159:24, :590:35]\n wire [2:0] _dec_finished_mask_T_1 = _dec_finished_mask_T | dec_finished_mask;\t// @[core.scala:496:34, :590:{35,42}]\n reg dec_brmask_logic_io_flush_pipeline_REG;\t// @[core.scala:597:48]\n wire _dec_brmask_logic_io_is_branch_0_T_1 = ~_dec_brmask_logic_io_is_branch_0_T;\t// @[core.scala:600:{41,59}]\n wire _dec_brmask_logic_io_is_branch_0_T_2 = ~dec_uops_0_is_sfb;\t// @[core.scala:158:24]\n wire _dec_brmask_logic_io_is_branch_0_T_3 = dec_uops_0_is_br & _dec_brmask_logic_io_is_branch_0_T_2;\t// @[core.scala:158:24]\n wire _dec_brmask_logic_io_is_branch_0_T_4 = _dec_brmask_logic_io_is_branch_0_T_3 | dec_uops_0_is_jalr;\t// @[core.scala:158:24]\n wire _dec_brmask_logic_io_is_branch_0_T_5 = _dec_brmask_logic_io_is_branch_0_T_1 & _dec_brmask_logic_io_is_branch_0_T_4;\t// @[core.scala:600:{41,63}]\n wire _dec_brmask_logic_io_will_fire_0_T = ~dec_uops_0_is_sfb;\t// @[core.scala:158:24]\n wire _dec_brmask_logic_io_will_fire_0_T_1 = dec_uops_0_is_br & _dec_brmask_logic_io_will_fire_0_T;\t// @[core.scala:158:24]\n wire _dec_brmask_logic_io_will_fire_0_T_2 = _dec_brmask_logic_io_will_fire_0_T_1 | dec_uops_0_is_jalr;\t// @[core.scala:158:24]\n wire _dec_brmask_logic_io_will_fire_0_T_3 = dec_fire_0 & _dec_brmask_logic_io_will_fire_0_T_2;\t// @[core.scala:159:24, :601:54]\n wire _dec_brmask_logic_io_is_branch_1_T_1 = ~_dec_brmask_logic_io_is_branch_1_T;\t// @[core.scala:600:{41,59}]\n wire _dec_brmask_logic_io_is_branch_1_T_2 = ~dec_uops_1_is_sfb;\t// @[core.scala:158:24]\n wire _dec_brmask_logic_io_is_branch_1_T_3 = dec_uops_1_is_br & _dec_brmask_logic_io_is_branch_1_T_2;\t// @[core.scala:158:24]\n wire _dec_brmask_logic_io_is_branch_1_T_4 = _dec_brmask_logic_io_is_branch_1_T_3 | dec_uops_1_is_jalr;\t// @[core.scala:158:24]\n wire _dec_brmask_logic_io_is_branch_1_T_5 = _dec_brmask_logic_io_is_branch_1_T_1 & _dec_brmask_logic_io_is_branch_1_T_4;\t// @[core.scala:600:{41,63}]\n wire _dec_brmask_logic_io_will_fire_1_T = ~dec_uops_1_is_sfb;\t// @[core.scala:158:24]\n wire _dec_brmask_logic_io_will_fire_1_T_1 = dec_uops_1_is_br & _dec_brmask_logic_io_will_fire_1_T;\t// @[core.scala:158:24]\n wire _dec_brmask_logic_io_will_fire_1_T_2 = _dec_brmask_logic_io_will_fire_1_T_1 | dec_uops_1_is_jalr;\t// @[core.scala:158:24]\n wire _dec_brmask_logic_io_will_fire_1_T_3 = dec_fire_1 & _dec_brmask_logic_io_will_fire_1_T_2;\t// @[core.scala:159:24, :601:54]\n wire _dec_brmask_logic_io_is_branch_2_T_1 = ~_dec_brmask_logic_io_is_branch_2_T;\t// @[core.scala:600:{41,59}]\n wire _dec_brmask_logic_io_is_branch_2_T_2 = ~dec_uops_2_is_sfb;\t// @[core.scala:158:24]\n wire _dec_brmask_logic_io_is_branch_2_T_3 = dec_uops_2_is_br & _dec_brmask_logic_io_is_branch_2_T_2;\t// @[core.scala:158:24]\n wire _dec_brmask_logic_io_is_branch_2_T_4 = _dec_brmask_logic_io_is_branch_2_T_3 | dec_uops_2_is_jalr;\t// @[core.scala:158:24]\n wire _dec_brmask_logic_io_is_branch_2_T_5 = _dec_brmask_logic_io_is_branch_2_T_1 & _dec_brmask_logic_io_is_branch_2_T_4;\t// @[core.scala:600:{41,63}]\n wire _dec_brmask_logic_io_will_fire_2_T = ~dec_uops_2_is_sfb;\t// @[core.scala:158:24]\n wire _dec_brmask_logic_io_will_fire_2_T_1 = dec_uops_2_is_br & _dec_brmask_logic_io_will_fire_2_T;\t// @[core.scala:158:24]\n wire _dec_brmask_logic_io_will_fire_2_T_2 = _dec_brmask_logic_io_will_fire_2_T_1 | dec_uops_2_is_jalr;\t// @[core.scala:158:24]\n wire _dec_brmask_logic_io_will_fire_2_T_3 = dec_fire_2 & _dec_brmask_logic_io_will_fire_2_T_2;\t// @[core.scala:159:24, :601:54]\n wire _GEN_22 = dis_uops_0_lrs1_rtype == 2'h1;\t// @[core.scala:167:24, :654:52]\n wire _dis_uops_0_prs1_T;\t// @[core.scala:654:52]\n assign _dis_uops_0_prs1_T = _GEN_22;\t// @[core.scala:654:52]\n wire _dis_uops_0_prs1_busy_T_2;\t// @[core.scala:665:73]\n assign _dis_uops_0_prs1_busy_T_2 = _GEN_22;\t// @[core.scala:654:52, :665:73]\n wire _GEN_23 = dis_uops_0_lrs1_rtype == 2'h0;\t// @[core.scala:167:24, :655:52]\n wire _dis_uops_0_prs1_T_1;\t// @[core.scala:655:52]\n assign _dis_uops_0_prs1_T_1 = _GEN_23;\t// @[core.scala:655:52]\n wire _dis_uops_0_prs1_busy_T;\t// @[core.scala:664:73]\n assign _dis_uops_0_prs1_busy_T = _GEN_23;\t// @[core.scala:655:52, :664:73]\n wire [6:0] _dis_uops_0_prs1_T_2 = _dis_uops_0_prs1_T_1 ? _rename_stage_io_ren2_uops_0_prs1 : {1'h0, dis_uops_0_lrs1};\t// @[core.scala:103:32, :167:24, :655:{28,52}]\n assign _dis_uops_0_prs1_T_3 = _dis_uops_0_prs1_T ? _fp_rename_stage_io_ren2_uops_0_prs1 : _dis_uops_0_prs1_T_2;\t// @[core.scala:104:46, :654:{28,52}, :655:28]\n assign dis_uops_0_prs1 = _dis_uops_0_prs1_T_3;\t// @[core.scala:167:24, :654:28]\n wire _GEN_24 = dis_uops_0_lrs2_rtype == 2'h1;\t// @[core.scala:167:24, :656:52]\n wire _dis_uops_0_prs2_T;\t// @[core.scala:656:52]\n assign _dis_uops_0_prs2_T = _GEN_24;\t// @[core.scala:656:52]\n wire _dis_uops_0_prs2_busy_T_2;\t// @[core.scala:667:73]\n assign _dis_uops_0_prs2_busy_T_2 = _GEN_24;\t// @[core.scala:656:52, :667:73]\n assign _dis_uops_0_prs2_T_1 = _dis_uops_0_prs2_T ? _fp_rename_stage_io_ren2_uops_0_prs2 : _rename_stage_io_ren2_uops_0_prs2;\t// @[core.scala:103:32, :104:46, :656:{28,52}]\n assign dis_uops_0_prs2 = _dis_uops_0_prs2_T_1;\t// @[core.scala:167:24, :656:28]\n wire _GEN_25 = dis_uops_0_dst_rtype == 2'h1;\t// @[core.scala:167:24, :659:52]\n wire _dis_uops_0_pdst_T;\t// @[core.scala:659:52]\n assign _dis_uops_0_pdst_T = _GEN_25;\t// @[core.scala:659:52]\n wire _dis_uops_0_stale_pdst_T;\t// @[core.scala:662:57]\n assign _dis_uops_0_stale_pdst_T = _GEN_25;\t// @[core.scala:659:52, :662:57]\n wire _dis_uops_0_pdst_T_1 = dis_uops_0_dst_rtype == 2'h0;\t// @[core.scala:167:24, :660:52]\n wire [6:0] _dis_uops_0_pdst_T_2 = _dis_uops_0_pdst_T_1 ? _rename_stage_io_ren2_uops_0_pdst : 7'h0;\t// @[core.scala:103:32, :660:{28,52}]\n assign _dis_uops_0_pdst_T_3 = _dis_uops_0_pdst_T ? _fp_rename_stage_io_ren2_uops_0_pdst : _dis_uops_0_pdst_T_2;\t// @[core.scala:104:46, :659:{28,52}, :660:28]\n assign dis_uops_0_pdst = _dis_uops_0_pdst_T_3;\t// @[core.scala:167:24, :659:28]\n assign _dis_uops_0_stale_pdst_T_1 = _dis_uops_0_stale_pdst_T ? _fp_rename_stage_io_ren2_uops_0_stale_pdst : _rename_stage_io_ren2_uops_0_stale_pdst;\t// @[core.scala:103:32, :104:46, :662:{34,57}]\n assign dis_uops_0_stale_pdst = _dis_uops_0_stale_pdst_T_1;\t// @[core.scala:167:24, :662:34]\n wire _dis_uops_0_prs1_busy_T_1 = _rename_stage_io_ren2_uops_0_prs1_busy & _dis_uops_0_prs1_busy_T;\t// @[core.scala:103:32, :664:{46,73}]\n wire _dis_uops_0_prs1_busy_T_3 = _fp_rename_stage_io_ren2_uops_0_prs1_busy & _dis_uops_0_prs1_busy_T_2;\t// @[core.scala:104:46, :665:{46,73}]\n assign _dis_uops_0_prs1_busy_T_4 = _dis_uops_0_prs1_busy_T_1 | _dis_uops_0_prs1_busy_T_3;\t// @[core.scala:664:{46,85}, :665:46]\n assign dis_uops_0_prs1_busy = _dis_uops_0_prs1_busy_T_4;\t// @[core.scala:167:24, :664:85]\n wire _dis_uops_0_prs2_busy_T = dis_uops_0_lrs2_rtype == 2'h0;\t// @[core.scala:167:24, :666:73]\n wire _dis_uops_0_prs2_busy_T_1 = _rename_stage_io_ren2_uops_0_prs2_busy & _dis_uops_0_prs2_busy_T;\t// @[core.scala:103:32, :666:{46,73}]\n wire _dis_uops_0_prs2_busy_T_3 = _fp_rename_stage_io_ren2_uops_0_prs2_busy & _dis_uops_0_prs2_busy_T_2;\t// @[core.scala:104:46, :667:{46,73}]\n assign _dis_uops_0_prs2_busy_T_4 = _dis_uops_0_prs2_busy_T_1 | _dis_uops_0_prs2_busy_T_3;\t// @[core.scala:666:{46,85}, :667:46]\n assign dis_uops_0_prs2_busy = _dis_uops_0_prs2_busy_T_4;\t// @[core.scala:167:24, :666:85]\n assign _dis_uops_0_prs3_busy_T = _fp_rename_stage_io_ren2_uops_0_prs3_busy & dis_uops_0_frs3_en;\t// @[core.scala:104:46, :167:24, :668:46]\n assign dis_uops_0_prs3_busy = _dis_uops_0_prs3_busy_T;\t// @[core.scala:167:24, :668:46]\n wire _dis_uops_0_ppred_busy_T = ~dis_uops_0_is_br;\t// @[core.scala:167:24]\n wire _dis_uops_0_ppred_busy_T_1 = _dis_uops_0_ppred_busy_T & dis_uops_0_is_sfb;\t// @[core.scala:167:24]\n wire _ren_stalls_0_T = _rename_stage_io_ren_stalls_0 | _fp_rename_stage_io_ren_stalls_0;\t// @[core.scala:103:32, :104:46, :671:52]\n assign _ren_stalls_0_T_1 = _ren_stalls_0_T;\t// @[core.scala:671:{52,63}]\n assign ren_stalls_0 = _ren_stalls_0_T_1;\t// @[core.scala:163:24, :671:63]\n wire _GEN_26 = dis_uops_1_lrs1_rtype == 2'h1;\t// @[core.scala:167:24, :654:52]\n wire _dis_uops_1_prs1_T;\t// @[core.scala:654:52]\n assign _dis_uops_1_prs1_T = _GEN_26;\t// @[core.scala:654:52]\n wire _dis_uops_1_prs1_busy_T_2;\t// @[core.scala:665:73]\n assign _dis_uops_1_prs1_busy_T_2 = _GEN_26;\t// @[core.scala:654:52, :665:73]\n wire _GEN_27 = dis_uops_1_lrs1_rtype == 2'h0;\t// @[core.scala:167:24, :655:52]\n wire _dis_uops_1_prs1_T_1;\t// @[core.scala:655:52]\n assign _dis_uops_1_prs1_T_1 = _GEN_27;\t// @[core.scala:655:52]\n wire _dis_uops_1_prs1_busy_T;\t// @[core.scala:664:73]\n assign _dis_uops_1_prs1_busy_T = _GEN_27;\t// @[core.scala:655:52, :664:73]\n wire [6:0] _dis_uops_1_prs1_T_2 = _dis_uops_1_prs1_T_1 ? _rename_stage_io_ren2_uops_1_prs1 : {1'h0, dis_uops_1_lrs1};\t// @[core.scala:103:32, :167:24, :655:{28,52}]\n assign _dis_uops_1_prs1_T_3 = _dis_uops_1_prs1_T ? _fp_rename_stage_io_ren2_uops_1_prs1 : _dis_uops_1_prs1_T_2;\t// @[core.scala:104:46, :654:{28,52}, :655:28]\n assign dis_uops_1_prs1 = _dis_uops_1_prs1_T_3;\t// @[core.scala:167:24, :654:28]\n wire _GEN_28 = dis_uops_1_lrs2_rtype == 2'h1;\t// @[core.scala:167:24, :656:52]\n wire _dis_uops_1_prs2_T;\t// @[core.scala:656:52]\n assign _dis_uops_1_prs2_T = _GEN_28;\t// @[core.scala:656:52]\n wire _dis_uops_1_prs2_busy_T_2;\t// @[core.scala:667:73]\n assign _dis_uops_1_prs2_busy_T_2 = _GEN_28;\t// @[core.scala:656:52, :667:73]\n assign _dis_uops_1_prs2_T_1 = _dis_uops_1_prs2_T ? _fp_rename_stage_io_ren2_uops_1_prs2 : _rename_stage_io_ren2_uops_1_prs2;\t// @[core.scala:103:32, :104:46, :656:{28,52}]\n assign dis_uops_1_prs2 = _dis_uops_1_prs2_T_1;\t// @[core.scala:167:24, :656:28]\n wire _GEN_29 = dis_uops_1_dst_rtype == 2'h1;\t// @[core.scala:167:24, :659:52]\n wire _dis_uops_1_pdst_T;\t// @[core.scala:659:52]\n assign _dis_uops_1_pdst_T = _GEN_29;\t// @[core.scala:659:52]\n wire _dis_uops_1_stale_pdst_T;\t// @[core.scala:662:57]\n assign _dis_uops_1_stale_pdst_T = _GEN_29;\t// @[core.scala:659:52, :662:57]\n wire _dis_uops_1_pdst_T_1 = dis_uops_1_dst_rtype == 2'h0;\t// @[core.scala:167:24, :660:52]\n wire [6:0] _dis_uops_1_pdst_T_2 = _dis_uops_1_pdst_T_1 ? _rename_stage_io_ren2_uops_1_pdst : 7'h0;\t// @[core.scala:103:32, :660:{28,52}]\n assign _dis_uops_1_pdst_T_3 = _dis_uops_1_pdst_T ? _fp_rename_stage_io_ren2_uops_1_pdst : _dis_uops_1_pdst_T_2;\t// @[core.scala:104:46, :659:{28,52}, :660:28]\n assign dis_uops_1_pdst = _dis_uops_1_pdst_T_3;\t// @[core.scala:167:24, :659:28]\n assign _dis_uops_1_stale_pdst_T_1 = _dis_uops_1_stale_pdst_T ? _fp_rename_stage_io_ren2_uops_1_stale_pdst : _rename_stage_io_ren2_uops_1_stale_pdst;\t// @[core.scala:103:32, :104:46, :662:{34,57}]\n assign dis_uops_1_stale_pdst = _dis_uops_1_stale_pdst_T_1;\t// @[core.scala:167:24, :662:34]\n wire _dis_uops_1_prs1_busy_T_1 = _rename_stage_io_ren2_uops_1_prs1_busy & _dis_uops_1_prs1_busy_T;\t// @[core.scala:103:32, :664:{46,73}]\n wire _dis_uops_1_prs1_busy_T_3 = _fp_rename_stage_io_ren2_uops_1_prs1_busy & _dis_uops_1_prs1_busy_T_2;\t// @[core.scala:104:46, :665:{46,73}]\n assign _dis_uops_1_prs1_busy_T_4 = _dis_uops_1_prs1_busy_T_1 | _dis_uops_1_prs1_busy_T_3;\t// @[core.scala:664:{46,85}, :665:46]\n assign dis_uops_1_prs1_busy = _dis_uops_1_prs1_busy_T_4;\t// @[core.scala:167:24, :664:85]\n wire _dis_uops_1_prs2_busy_T = dis_uops_1_lrs2_rtype == 2'h0;\t// @[core.scala:167:24, :666:73]\n wire _dis_uops_1_prs2_busy_T_1 = _rename_stage_io_ren2_uops_1_prs2_busy & _dis_uops_1_prs2_busy_T;\t// @[core.scala:103:32, :666:{46,73}]\n wire _dis_uops_1_prs2_busy_T_3 = _fp_rename_stage_io_ren2_uops_1_prs2_busy & _dis_uops_1_prs2_busy_T_2;\t// @[core.scala:104:46, :667:{46,73}]\n assign _dis_uops_1_prs2_busy_T_4 = _dis_uops_1_prs2_busy_T_1 | _dis_uops_1_prs2_busy_T_3;\t// @[core.scala:666:{46,85}, :667:46]\n assign dis_uops_1_prs2_busy = _dis_uops_1_prs2_busy_T_4;\t// @[core.scala:167:24, :666:85]\n assign _dis_uops_1_prs3_busy_T = _fp_rename_stage_io_ren2_uops_1_prs3_busy & dis_uops_1_frs3_en;\t// @[core.scala:104:46, :167:24, :668:46]\n assign dis_uops_1_prs3_busy = _dis_uops_1_prs3_busy_T;\t// @[core.scala:167:24, :668:46]\n wire _dis_uops_1_ppred_busy_T = ~dis_uops_1_is_br;\t// @[core.scala:167:24]\n wire _dis_uops_1_ppred_busy_T_1 = _dis_uops_1_ppred_busy_T & dis_uops_1_is_sfb;\t// @[core.scala:167:24]\n wire _ren_stalls_1_T = _rename_stage_io_ren_stalls_1 | _fp_rename_stage_io_ren_stalls_1;\t// @[core.scala:103:32, :104:46, :671:52]\n assign _ren_stalls_1_T_1 = _ren_stalls_1_T;\t// @[core.scala:671:{52,63}]\n assign ren_stalls_1 = _ren_stalls_1_T_1;\t// @[core.scala:163:24, :671:63]\n wire _GEN_30 = dis_uops_2_lrs1_rtype == 2'h1;\t// @[core.scala:167:24, :654:52]\n wire _dis_uops_2_prs1_T;\t// @[core.scala:654:52]\n assign _dis_uops_2_prs1_T = _GEN_30;\t// @[core.scala:654:52]\n wire _dis_uops_2_prs1_busy_T_2;\t// @[core.scala:665:73]\n assign _dis_uops_2_prs1_busy_T_2 = _GEN_30;\t// @[core.scala:654:52, :665:73]\n wire _GEN_31 = dis_uops_2_lrs1_rtype == 2'h0;\t// @[core.scala:167:24, :655:52]\n wire _dis_uops_2_prs1_T_1;\t// @[core.scala:655:52]\n assign _dis_uops_2_prs1_T_1 = _GEN_31;\t// @[core.scala:655:52]\n wire _dis_uops_2_prs1_busy_T;\t// @[core.scala:664:73]\n assign _dis_uops_2_prs1_busy_T = _GEN_31;\t// @[core.scala:655:52, :664:73]\n wire [6:0] _dis_uops_2_prs1_T_2 = _dis_uops_2_prs1_T_1 ? _rename_stage_io_ren2_uops_2_prs1 : {1'h0, dis_uops_2_lrs1};\t// @[core.scala:103:32, :167:24, :655:{28,52}]\n assign _dis_uops_2_prs1_T_3 = _dis_uops_2_prs1_T ? _fp_rename_stage_io_ren2_uops_2_prs1 : _dis_uops_2_prs1_T_2;\t// @[core.scala:104:46, :654:{28,52}, :655:28]\n assign dis_uops_2_prs1 = _dis_uops_2_prs1_T_3;\t// @[core.scala:167:24, :654:28]\n wire _GEN_32 = dis_uops_2_lrs2_rtype == 2'h1;\t// @[core.scala:167:24, :656:52]\n wire _dis_uops_2_prs2_T;\t// @[core.scala:656:52]\n assign _dis_uops_2_prs2_T = _GEN_32;\t// @[core.scala:656:52]\n wire _dis_uops_2_prs2_busy_T_2;\t// @[core.scala:667:73]\n assign _dis_uops_2_prs2_busy_T_2 = _GEN_32;\t// @[core.scala:656:52, :667:73]\n assign _dis_uops_2_prs2_T_1 = _dis_uops_2_prs2_T ? _fp_rename_stage_io_ren2_uops_2_prs2 : _rename_stage_io_ren2_uops_2_prs2;\t// @[core.scala:103:32, :104:46, :656:{28,52}]\n assign dis_uops_2_prs2 = _dis_uops_2_prs2_T_1;\t// @[core.scala:167:24, :656:28]\n wire _GEN_33 = dis_uops_2_dst_rtype == 2'h1;\t// @[core.scala:167:24, :659:52]\n wire _dis_uops_2_pdst_T;\t// @[core.scala:659:52]\n assign _dis_uops_2_pdst_T = _GEN_33;\t// @[core.scala:659:52]\n wire _dis_uops_2_stale_pdst_T;\t// @[core.scala:662:57]\n assign _dis_uops_2_stale_pdst_T = _GEN_33;\t// @[core.scala:659:52, :662:57]\n wire _dis_uops_2_pdst_T_1 = dis_uops_2_dst_rtype == 2'h0;\t// @[core.scala:167:24, :660:52]\n wire [6:0] _dis_uops_2_pdst_T_2 = _dis_uops_2_pdst_T_1 ? _rename_stage_io_ren2_uops_2_pdst : 7'h0;\t// @[core.scala:103:32, :660:{28,52}]\n assign _dis_uops_2_pdst_T_3 = _dis_uops_2_pdst_T ? _fp_rename_stage_io_ren2_uops_2_pdst : _dis_uops_2_pdst_T_2;\t// @[core.scala:104:46, :659:{28,52}, :660:28]\n assign dis_uops_2_pdst = _dis_uops_2_pdst_T_3;\t// @[core.scala:167:24, :659:28]\n assign _dis_uops_2_stale_pdst_T_1 = _dis_uops_2_stale_pdst_T ? _fp_rename_stage_io_ren2_uops_2_stale_pdst : _rename_stage_io_ren2_uops_2_stale_pdst;\t// @[core.scala:103:32, :104:46, :662:{34,57}]\n assign dis_uops_2_stale_pdst = _dis_uops_2_stale_pdst_T_1;\t// @[core.scala:167:24, :662:34]\n wire _dis_uops_2_prs1_busy_T_1 = _rename_stage_io_ren2_uops_2_prs1_busy & _dis_uops_2_prs1_busy_T;\t// @[core.scala:103:32, :664:{46,73}]\n wire _dis_uops_2_prs1_busy_T_3 = _fp_rename_stage_io_ren2_uops_2_prs1_busy & _dis_uops_2_prs1_busy_T_2;\t// @[core.scala:104:46, :665:{46,73}]\n assign _dis_uops_2_prs1_busy_T_4 = _dis_uops_2_prs1_busy_T_1 | _dis_uops_2_prs1_busy_T_3;\t// @[core.scala:664:{46,85}, :665:46]\n assign dis_uops_2_prs1_busy = _dis_uops_2_prs1_busy_T_4;\t// @[core.scala:167:24, :664:85]\n wire _dis_uops_2_prs2_busy_T = dis_uops_2_lrs2_rtype == 2'h0;\t// @[core.scala:167:24, :666:73]\n wire _dis_uops_2_prs2_busy_T_1 = _rename_stage_io_ren2_uops_2_prs2_busy & _dis_uops_2_prs2_busy_T;\t// @[core.scala:103:32, :666:{46,73}]\n wire _dis_uops_2_prs2_busy_T_3 = _fp_rename_stage_io_ren2_uops_2_prs2_busy & _dis_uops_2_prs2_busy_T_2;\t// @[core.scala:104:46, :667:{46,73}]\n assign _dis_uops_2_prs2_busy_T_4 = _dis_uops_2_prs2_busy_T_1 | _dis_uops_2_prs2_busy_T_3;\t// @[core.scala:666:{46,85}, :667:46]\n assign dis_uops_2_prs2_busy = _dis_uops_2_prs2_busy_T_4;\t// @[core.scala:167:24, :666:85]\n assign _dis_uops_2_prs3_busy_T = _fp_rename_stage_io_ren2_uops_2_prs3_busy & dis_uops_2_frs3_en;\t// @[core.scala:104:46, :167:24, :668:46]\n assign dis_uops_2_prs3_busy = _dis_uops_2_prs3_busy_T;\t// @[core.scala:167:24, :668:46]\n wire _dis_uops_2_ppred_busy_T = ~dis_uops_2_is_br;\t// @[core.scala:167:24]\n wire _dis_uops_2_ppred_busy_T_1 = _dis_uops_2_ppred_busy_T & dis_uops_2_is_sfb;\t// @[core.scala:167:24]\n wire _ren_stalls_2_T = _rename_stage_io_ren_stalls_2 | _fp_rename_stage_io_ren_stalls_2;\t// @[core.scala:103:32, :104:46, :671:52]\n assign _ren_stalls_2_T_1 = _ren_stalls_2_T;\t// @[core.scala:671:{52,63}]\n assign ren_stalls_2 = _ren_stalls_2_T_1;\t// @[core.scala:163:24, :671:63]\n wire dis_prior_slot_valid_2 = dis_prior_slot_valid_1 | dis_valids_1;\t// @[core.scala:166:24, :683:71]\n wire dis_prior_slot_valid_3 = dis_prior_slot_valid_2 | dis_valids_2;\t// @[core.scala:166:24, :683:71]\n wire _dis_prior_slot_unique_T = dis_valids_0 & dis_uops_0_is_unique;\t// @[core.scala:166:24, :167:24, :684:101]\n wire dis_prior_slot_unique_1 = _dis_prior_slot_unique_T;\t// @[core.scala:684:{96,101}]\n wire _dis_prior_slot_unique_T_1 = dis_valids_1 & dis_uops_1_is_unique;\t// @[core.scala:166:24, :167:24, :684:101]\n wire dis_prior_slot_unique_2 = dis_prior_slot_unique_1 | _dis_prior_slot_unique_T_1;\t// @[core.scala:684:{96,101}]\n wire _dis_prior_slot_unique_T_2 = dis_valids_2 & dis_uops_2_is_unique;\t// @[core.scala:166:24, :167:24, :684:101]\n wire dis_prior_slot_unique_3 = dis_prior_slot_unique_2 | _dis_prior_slot_unique_T_2;\t// @[core.scala:684:{96,101}]\n wire _wait_for_empty_pipeline_T = custom_csrs_csrs_0_value[3];\t// @[core.scala:276:25]\n wire _wait_for_empty_pipeline_T_6 = custom_csrs_csrs_0_value[3];\t// @[core.scala:276:25]\n wire _wait_for_empty_pipeline_T_12 = custom_csrs_csrs_0_value[3];\t// @[core.scala:276:25]\n wire _wait_for_empty_pipeline_T_1 = dis_uops_0_is_unique | _wait_for_empty_pipeline_T;\t// @[core.scala:167:24, :685:85]\n wire _wait_for_empty_pipeline_T_2 = ~_rob_io_empty;\t// @[core.scala:143:32, :686:36]\n wire _wait_for_empty_pipeline_T_3 = ~io_lsu_fencei_rdy_0;\t// @[core.scala:51:7, :686:53]\n wire _wait_for_empty_pipeline_T_4 = _wait_for_empty_pipeline_T_2 | _wait_for_empty_pipeline_T_3;\t// @[core.scala:686:{36,50,53}]\n wire _wait_for_empty_pipeline_T_5 = _wait_for_empty_pipeline_T_4;\t// @[core.scala:686:{50,72}]\n wire wait_for_empty_pipeline_0 = _wait_for_empty_pipeline_T_1 & _wait_for_empty_pipeline_T_5;\t// @[core.scala:685:{85,112}, :686:72]\n wire _wait_for_empty_pipeline_T_7 = dis_uops_1_is_unique | _wait_for_empty_pipeline_T_6;\t// @[core.scala:167:24, :685:85]\n wire _wait_for_empty_pipeline_T_8 = ~_rob_io_empty;\t// @[core.scala:143:32, :686:36]\n wire _wait_for_empty_pipeline_T_9 = ~io_lsu_fencei_rdy_0;\t// @[core.scala:51:7, :686:53]\n wire _wait_for_empty_pipeline_T_10 = _wait_for_empty_pipeline_T_8 | _wait_for_empty_pipeline_T_9;\t// @[core.scala:686:{36,50,53}]\n wire _wait_for_empty_pipeline_T_11 = _wait_for_empty_pipeline_T_10 | dis_prior_slot_valid_1;\t// @[core.scala:683:71, :686:{50,72}]\n wire wait_for_empty_pipeline_1 = _wait_for_empty_pipeline_T_7 & _wait_for_empty_pipeline_T_11;\t// @[core.scala:685:{85,112}, :686:72]\n wire _wait_for_empty_pipeline_T_13 = dis_uops_2_is_unique | _wait_for_empty_pipeline_T_12;\t// @[core.scala:167:24, :685:85]\n wire _wait_for_empty_pipeline_T_14 = ~_rob_io_empty;\t// @[core.scala:143:32, :686:36]\n wire _wait_for_empty_pipeline_T_15 = ~io_lsu_fencei_rdy_0;\t// @[core.scala:51:7, :686:53]\n wire _wait_for_empty_pipeline_T_16 = _wait_for_empty_pipeline_T_14 | _wait_for_empty_pipeline_T_15;\t// @[core.scala:686:{36,50,53}]\n wire _wait_for_empty_pipeline_T_17 = _wait_for_empty_pipeline_T_16 | dis_prior_slot_valid_2;\t// @[core.scala:683:71, :686:{50,72}]\n wire wait_for_empty_pipeline_2 = _wait_for_empty_pipeline_T_13 & _wait_for_empty_pipeline_T_17;\t// @[core.scala:685:{85,112}, :686:72]\n wire _wait_for_rocc_T = dis_uops_0_is_fence | dis_uops_0_is_fencei;\t// @[core.scala:167:24, :689:47]\n wire _wait_for_rocc_T_2 = dis_uops_1_is_fence | dis_uops_1_is_fencei;\t// @[core.scala:167:24, :689:47]\n wire _wait_for_rocc_T_4 = dis_uops_2_is_fence | dis_uops_2_is_fencei;\t// @[core.scala:167:24, :689:47]\n wire _GEN_34 = dis_uops_0_uopc == 7'h6C;\t// @[core.scala:167:24, :691:76]\n wire _block_rocc_T;\t// @[core.scala:691:76]\n assign _block_rocc_T = _GEN_34;\t// @[core.scala:691:76]\n wire _dis_rocc_alloc_stall_T;\t// @[core.scala:692:51]\n assign _dis_rocc_alloc_stall_T = _GEN_34;\t// @[core.scala:691:76, :692:51]\n wire _block_rocc_T_1 = dis_valids_0 & _block_rocc_T;\t// @[core.scala:166:24, :691:{66,76}]\n wire block_rocc_1 = _block_rocc_T_1;\t// @[core.scala:691:{66,109}]\n wire _GEN_35 = dis_uops_1_uopc == 7'h6C;\t// @[core.scala:167:24, :691:76]\n wire _block_rocc_T_2;\t// @[core.scala:691:76]\n assign _block_rocc_T_2 = _GEN_35;\t// @[core.scala:691:76]\n wire _dis_rocc_alloc_stall_T_1;\t// @[core.scala:692:51]\n assign _dis_rocc_alloc_stall_T_1 = _GEN_35;\t// @[core.scala:691:76, :692:51]\n wire _block_rocc_T_3 = dis_valids_1 & _block_rocc_T_2;\t// @[core.scala:166:24, :691:{66,76}]\n wire _GEN_36 = dis_uops_2_uopc == 7'h6C;\t// @[core.scala:167:24, :691:76]\n wire _block_rocc_T_4;\t// @[core.scala:691:76]\n assign _block_rocc_T_4 = _GEN_36;\t// @[core.scala:691:76]\n wire _dis_rocc_alloc_stall_T_2;\t// @[core.scala:692:51]\n assign _dis_rocc_alloc_stall_T_2 = _GEN_36;\t// @[core.scala:691:76, :692:51]\n wire _block_rocc_T_5 = dis_valids_2 & _block_rocc_T_4;\t// @[core.scala:166:24, :691:{66,76}]\n wire block_rocc_2 = block_rocc_1 | _block_rocc_T_3;\t// @[core.scala:691:{66,109}]\n wire block_rocc_3 = block_rocc_2 | _block_rocc_T_5;\t// @[core.scala:691:{66,109}]\n wire _dis_hazards_T = ~_rob_io_ready;\t// @[core.scala:143:32, :697:26]\n wire _dis_hazards_T_1 = _dis_hazards_T | ren_stalls_0;\t// @[core.scala:163:24, :697:26, :698:23]\n wire _dis_hazards_T_2 = io_lsu_ldq_full_0_0 & dis_uops_0_uses_ldq;\t// @[core.scala:51:7, :167:24, :699:45]\n wire _dis_hazards_T_3 = _dis_hazards_T_1 | _dis_hazards_T_2;\t// @[core.scala:698:23, :699:{23,45}]\n wire _dis_hazards_T_4 = io_lsu_stq_full_0_0 & dis_uops_0_uses_stq;\t// @[core.scala:51:7, :167:24, :700:45]\n wire _dis_hazards_T_5 = _dis_hazards_T_3 | _dis_hazards_T_4;\t// @[core.scala:699:23, :700:{23,45}]\n wire _dis_hazards_T_6 = ~_dispatcher_io_ren_uops_0_ready;\t// @[core.scala:114:32, :701:26]\n wire _dis_hazards_T_7 = _dis_hazards_T_5 | _dis_hazards_T_6;\t// @[core.scala:700:23, :701:{23,26}]\n wire _dis_hazards_T_8 = _dis_hazards_T_7 | wait_for_empty_pipeline_0;\t// @[core.scala:685:112, :701:23, :702:23]\n wire _dis_hazards_T_9 = _dis_hazards_T_8;\t// @[core.scala:702:23, :703:23]\n wire _dis_hazards_T_10 = _dis_hazards_T_9;\t// @[core.scala:703:23, :704:23]\n wire _dis_hazards_T_11 = _dis_hazards_T_10;\t// @[core.scala:704:23, :705:23]\n wire _dis_hazards_T_12 = |brupdate_b1_mispredict_mask;\t// @[core.scala:188:23, :224:42, :706:54]\n wire _dis_hazards_T_13 = _dis_hazards_T_11 | _dis_hazards_T_12;\t// @[core.scala:705:23, :706:{23,54}]\n wire _dis_hazards_T_14 = _dis_hazards_T_13 | brupdate_b2_mispredict;\t// @[core.scala:188:23, :706:23, :707:23]\n wire _dis_hazards_T_15 = _dis_hazards_T_14 | io_ifu_redirect_flush_0;\t// @[core.scala:51:7, :707:23, :708:23]\n wire dis_hazards_0 = dis_valids_0 & _dis_hazards_T_15;\t// @[core.scala:166:24, :696:37, :708:23]\n wire dis_stalls_0 = dis_hazards_0;\t// @[core.scala:696:37, :713:62]\n wire _dis_hazards_T_16 = ~_rob_io_ready;\t// @[core.scala:143:32, :697:26]\n wire _dis_hazards_T_17 = _dis_hazards_T_16 | ren_stalls_1;\t// @[core.scala:163:24, :697:26, :698:23]\n wire _dis_hazards_T_18 = io_lsu_ldq_full_1_0 & dis_uops_1_uses_ldq;\t// @[core.scala:51:7, :167:24, :699:45]\n wire _dis_hazards_T_19 = _dis_hazards_T_17 | _dis_hazards_T_18;\t// @[core.scala:698:23, :699:{23,45}]\n wire _dis_hazards_T_20 = io_lsu_stq_full_1_0 & dis_uops_1_uses_stq;\t// @[core.scala:51:7, :167:24, :700:45]\n wire _dis_hazards_T_21 = _dis_hazards_T_19 | _dis_hazards_T_20;\t// @[core.scala:699:23, :700:{23,45}]\n wire _dis_hazards_T_22 = ~_dispatcher_io_ren_uops_1_ready;\t// @[core.scala:114:32, :701:26]\n wire _dis_hazards_T_23 = _dis_hazards_T_21 | _dis_hazards_T_22;\t// @[core.scala:700:23, :701:{23,26}]\n wire _dis_hazards_T_24 = _dis_hazards_T_23 | wait_for_empty_pipeline_1;\t// @[core.scala:685:112, :701:23, :702:23]\n wire _dis_hazards_T_25 = _dis_hazards_T_24;\t// @[core.scala:702:23, :703:23]\n wire _dis_hazards_T_26 = _dis_hazards_T_25 | dis_prior_slot_unique_1;\t// @[core.scala:684:96, :703:23, :704:23]\n wire _dis_hazards_T_27 = _dis_hazards_T_26;\t// @[core.scala:704:23, :705:23]\n wire _dis_hazards_T_28 = |brupdate_b1_mispredict_mask;\t// @[core.scala:188:23, :224:42, :706:54]\n wire _dis_hazards_T_29 = _dis_hazards_T_27 | _dis_hazards_T_28;\t// @[core.scala:705:23, :706:{23,54}]\n wire _dis_hazards_T_30 = _dis_hazards_T_29 | brupdate_b2_mispredict;\t// @[core.scala:188:23, :706:23, :707:23]\n wire _dis_hazards_T_31 = _dis_hazards_T_30 | io_ifu_redirect_flush_0;\t// @[core.scala:51:7, :707:23, :708:23]\n wire dis_hazards_1 = dis_valids_1 & _dis_hazards_T_31;\t// @[core.scala:166:24, :696:37, :708:23]\n wire _dis_hazards_T_32 = ~_rob_io_ready;\t// @[core.scala:143:32, :697:26]\n wire _dis_hazards_T_33 = _dis_hazards_T_32 | ren_stalls_2;\t// @[core.scala:163:24, :697:26, :698:23]\n wire _dis_hazards_T_34 = io_lsu_ldq_full_2_0 & dis_uops_2_uses_ldq;\t// @[core.scala:51:7, :167:24, :699:45]\n wire _dis_hazards_T_35 = _dis_hazards_T_33 | _dis_hazards_T_34;\t// @[core.scala:698:23, :699:{23,45}]\n wire _dis_hazards_T_36 = io_lsu_stq_full_2_0 & dis_uops_2_uses_stq;\t// @[core.scala:51:7, :167:24, :700:45]\n wire _dis_hazards_T_37 = _dis_hazards_T_35 | _dis_hazards_T_36;\t// @[core.scala:699:23, :700:{23,45}]\n wire _dis_hazards_T_38 = ~_dispatcher_io_ren_uops_2_ready;\t// @[core.scala:114:32, :701:26]\n wire _dis_hazards_T_39 = _dis_hazards_T_37 | _dis_hazards_T_38;\t// @[core.scala:700:23, :701:{23,26}]\n wire _dis_hazards_T_40 = _dis_hazards_T_39 | wait_for_empty_pipeline_2;\t// @[core.scala:685:112, :701:23, :702:23]\n wire _dis_hazards_T_41 = _dis_hazards_T_40;\t// @[core.scala:702:23, :703:23]\n wire _dis_hazards_T_42 = _dis_hazards_T_41 | dis_prior_slot_unique_2;\t// @[core.scala:684:96, :703:23, :704:23]\n wire _dis_hazards_T_43 = _dis_hazards_T_42;\t// @[core.scala:704:23, :705:23]\n wire _dis_hazards_T_44 = |brupdate_b1_mispredict_mask;\t// @[core.scala:188:23, :224:42, :706:54]\n wire _dis_hazards_T_45 = _dis_hazards_T_43 | _dis_hazards_T_44;\t// @[core.scala:705:23, :706:{23,54}]\n wire _dis_hazards_T_46 = _dis_hazards_T_45 | brupdate_b2_mispredict;\t// @[core.scala:188:23, :706:23, :707:23]\n wire _dis_hazards_T_47 = _dis_hazards_T_46 | io_ifu_redirect_flush_0;\t// @[core.scala:51:7, :707:23, :708:23]\n wire dis_hazards_2 = dis_valids_2 & _dis_hazards_T_47;\t// @[core.scala:166:24, :696:37, :708:23]\n wire _io_lsu_fence_dmem_T = dis_valids_0 & wait_for_empty_pipeline_0;\t// @[core.scala:166:24, :685:112, :711:86]\n wire _io_lsu_fence_dmem_T_1 = dis_valids_1 & wait_for_empty_pipeline_1;\t// @[core.scala:166:24, :685:112, :711:86]\n wire _io_lsu_fence_dmem_T_2 = dis_valids_2 & wait_for_empty_pipeline_2;\t// @[core.scala:166:24, :685:112, :711:86]\n wire _io_lsu_fence_dmem_T_3 = _io_lsu_fence_dmem_T | _io_lsu_fence_dmem_T_1;\t// @[core.scala:711:{86,101}]\n assign _io_lsu_fence_dmem_T_4 = _io_lsu_fence_dmem_T_3 | _io_lsu_fence_dmem_T_2;\t// @[core.scala:711:{86,101}]\n assign io_lsu_fence_dmem_0 = _io_lsu_fence_dmem_T_4;\t// @[core.scala:51:7, :711:101]\n wire dis_stalls_1 = dis_stalls_0 | dis_hazards_1;\t// @[core.scala:696:37, :713:62]\n wire dis_stalls_2 = dis_stalls_1 | dis_hazards_2;\t// @[core.scala:696:37, :713:62]\n assign dis_fire_0 = dis_valids_0 & ~dis_stalls_0;\t// @[core.scala:166:24, :168:24, :713:62, :714:{62,65}]\n assign dis_fire_1 = dis_valids_1 & ~dis_stalls_1;\t// @[core.scala:166:24, :168:24, :713:62, :714:{62,65}]\n assign dis_fire_2 = dis_valids_2 & ~dis_stalls_2;\t// @[core.scala:166:24, :168:24, :713:62, :714:{62,65}]\n assign _dis_ready_T = ~dis_stalls_2;\t// @[core.scala:713:62, :714:65, :715:16]\n assign dis_ready = _dis_ready_T;\t// @[core.scala:169:24, :715:16]\n reg REG_3;\t// @[core.scala:738:16]\n assign io_ifu_commit_valid_0 = REG_3 | _io_ifu_commit_valid_T_2;\t// @[core.scala:51:7, :466:{23,59}, :738:{16,94}, :739:25]\n wire [1:0] _io_ifu_commit_bits_T_1 = dis_valids_1 ? 2'h1 : 2'h2;\t// @[Mux.scala:50:70]\n wire [1:0] _io_ifu_commit_bits_T_2 = dis_valids_0 ? 2'h0 : _io_ifu_commit_bits_T_1;\t// @[Mux.scala:50:70]\n reg [4:0] io_ifu_commit_bits_REG;\t// @[core.scala:740:35]\n assign io_ifu_commit_bits_0 = {27'h0, REG_3 ? io_ifu_commit_bits_REG : _io_ifu_commit_bits_T};\t// @[core.scala:51:7, :467:{23,29}, :738:{16,94}, :740:{25,35}]\n wire [6:0] _GEN_37 = {2'h0, _rob_io_rob_tail_idx[6:2]};\t// @[core.scala:143:32, :749:54]\n wire [6:0] _dis_uops_0_rob_idx_T;\t// @[core.scala:749:54]\n assign _dis_uops_0_rob_idx_T = _GEN_37;\t// @[core.scala:749:54]\n wire [6:0] _dis_uops_1_rob_idx_T;\t// @[core.scala:749:54]\n assign _dis_uops_1_rob_idx_T = _GEN_37;\t// @[core.scala:749:54]\n wire [6:0] _dis_uops_2_rob_idx_T;\t// @[core.scala:749:54]\n assign _dis_uops_2_rob_idx_T = _GEN_37;\t// @[core.scala:749:54]\n wire [8:0] _dis_uops_0_rob_idx_T_1 = {_dis_uops_0_rob_idx_T, 2'h0};\t// @[core.scala:749:{33,54}]\n assign dis_uops_0_rob_idx = _dis_uops_0_rob_idx_T_1[6:0];\t// @[core.scala:167:24, :749:{27,33}]\n wire [8:0] _dis_uops_1_rob_idx_T_1 = {_dis_uops_1_rob_idx_T, 2'h1};\t// @[core.scala:749:{33,54}]\n assign dis_uops_1_rob_idx = _dis_uops_1_rob_idx_T_1[6:0];\t// @[core.scala:167:24, :749:{27,33}]\n wire [8:0] _dis_uops_2_rob_idx_T_1 = {_dis_uops_2_rob_idx_T, 2'h2};\t// @[core.scala:749:{33,54}]\n assign dis_uops_2_rob_idx = _dis_uops_2_rob_idx_T_1[6:0];\t// @[core.scala:167:24, :749:{27,33}]\n wire _GEN_38 = _ll_wbarb_io_out_bits_uop_dst_rtype == 2'h0;\t// @[core.scala:132:32, :795:90]\n wire _int_iss_wakeups_0_valid_T_1;\t// @[core.scala:795:90]\n assign _int_iss_wakeups_0_valid_T_1 = _GEN_38;\t// @[core.scala:795:90]\n wire _int_ren_wakeups_0_valid_T_1;\t// @[core.scala:798:90]\n assign _int_ren_wakeups_0_valid_T_1 = _GEN_38;\t// @[core.scala:795:90, :798:90]\n wire _iregfile_io_write_ports_0_wport_valid_T;\t// @[regfile.scala:57:61]\n assign _iregfile_io_write_ports_0_wport_valid_T = _GEN_38;\t// @[regfile.scala:57:61]\n wire _int_iss_wakeups_0_valid_T;\t// @[Decoupled.scala:51:35]\n assign _int_iss_wakeups_0_valid_T_2 = _int_iss_wakeups_0_valid_T & _int_iss_wakeups_0_valid_T_1;\t// @[Decoupled.scala:51:35]\n assign int_iss_wakeups_0_valid = _int_iss_wakeups_0_valid_T_2;\t// @[core.scala:147:30, :795:52]\n wire _int_ren_wakeups_0_valid_T;\t// @[Decoupled.scala:51:35]\n assign _int_ren_wakeups_0_valid_T_2 = _int_ren_wakeups_0_valid_T & _int_ren_wakeups_0_valid_T_1;\t// @[Decoupled.scala:51:35]\n assign int_ren_wakeups_0_valid = _int_ren_wakeups_0_valid_T_2;\t// @[core.scala:148:30, :798:52]\n wire _fast_wakeup_valid_T_7;\t// @[core.scala:827:52]\n assign int_iss_wakeups_1_valid = fast_wakeup_valid;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_1_valid = fast_wakeup_valid;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_1_bits_uop_uopc = fast_wakeup_bits_uop_uopc;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_1_bits_uop_uopc = fast_wakeup_bits_uop_uopc;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_1_bits_uop_inst = fast_wakeup_bits_uop_inst;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_1_bits_uop_inst = fast_wakeup_bits_uop_inst;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_1_bits_uop_debug_inst = fast_wakeup_bits_uop_debug_inst;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_1_bits_uop_debug_inst = fast_wakeup_bits_uop_debug_inst;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_1_bits_uop_is_rvc = fast_wakeup_bits_uop_is_rvc;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_1_bits_uop_is_rvc = fast_wakeup_bits_uop_is_rvc;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_1_bits_uop_debug_pc = fast_wakeup_bits_uop_debug_pc;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_1_bits_uop_debug_pc = fast_wakeup_bits_uop_debug_pc;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_1_bits_uop_iq_type = fast_wakeup_bits_uop_iq_type;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_1_bits_uop_iq_type = fast_wakeup_bits_uop_iq_type;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_1_bits_uop_fu_code = fast_wakeup_bits_uop_fu_code;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_1_bits_uop_fu_code = fast_wakeup_bits_uop_fu_code;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_1_bits_uop_ctrl_br_type = fast_wakeup_bits_uop_ctrl_br_type;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_1_bits_uop_ctrl_br_type = fast_wakeup_bits_uop_ctrl_br_type;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_1_bits_uop_ctrl_op1_sel = fast_wakeup_bits_uop_ctrl_op1_sel;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_1_bits_uop_ctrl_op1_sel = fast_wakeup_bits_uop_ctrl_op1_sel;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_1_bits_uop_ctrl_op2_sel = fast_wakeup_bits_uop_ctrl_op2_sel;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_1_bits_uop_ctrl_op2_sel = fast_wakeup_bits_uop_ctrl_op2_sel;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_1_bits_uop_ctrl_imm_sel = fast_wakeup_bits_uop_ctrl_imm_sel;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_1_bits_uop_ctrl_imm_sel = fast_wakeup_bits_uop_ctrl_imm_sel;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_1_bits_uop_ctrl_op_fcn = fast_wakeup_bits_uop_ctrl_op_fcn;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_1_bits_uop_ctrl_op_fcn = fast_wakeup_bits_uop_ctrl_op_fcn;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_1_bits_uop_ctrl_fcn_dw = fast_wakeup_bits_uop_ctrl_fcn_dw;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_1_bits_uop_ctrl_fcn_dw = fast_wakeup_bits_uop_ctrl_fcn_dw;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_1_bits_uop_ctrl_csr_cmd = fast_wakeup_bits_uop_ctrl_csr_cmd;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_1_bits_uop_ctrl_csr_cmd = fast_wakeup_bits_uop_ctrl_csr_cmd;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_1_bits_uop_ctrl_is_load = fast_wakeup_bits_uop_ctrl_is_load;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_1_bits_uop_ctrl_is_load = fast_wakeup_bits_uop_ctrl_is_load;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_1_bits_uop_ctrl_is_sta = fast_wakeup_bits_uop_ctrl_is_sta;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_1_bits_uop_ctrl_is_sta = fast_wakeup_bits_uop_ctrl_is_sta;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_1_bits_uop_ctrl_is_std = fast_wakeup_bits_uop_ctrl_is_std;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_1_bits_uop_ctrl_is_std = fast_wakeup_bits_uop_ctrl_is_std;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_1_bits_uop_iw_state = fast_wakeup_bits_uop_iw_state;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_1_bits_uop_iw_state = fast_wakeup_bits_uop_iw_state;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_1_bits_uop_iw_p1_poisoned = fast_wakeup_bits_uop_iw_p1_poisoned;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_1_bits_uop_iw_p1_poisoned = fast_wakeup_bits_uop_iw_p1_poisoned;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_1_bits_uop_iw_p2_poisoned = fast_wakeup_bits_uop_iw_p2_poisoned;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_1_bits_uop_iw_p2_poisoned = fast_wakeup_bits_uop_iw_p2_poisoned;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_1_bits_uop_is_br = fast_wakeup_bits_uop_is_br;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_1_bits_uop_is_br = fast_wakeup_bits_uop_is_br;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_1_bits_uop_is_jalr = fast_wakeup_bits_uop_is_jalr;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_1_bits_uop_is_jalr = fast_wakeup_bits_uop_is_jalr;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_1_bits_uop_is_jal = fast_wakeup_bits_uop_is_jal;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_1_bits_uop_is_jal = fast_wakeup_bits_uop_is_jal;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_1_bits_uop_is_sfb = fast_wakeup_bits_uop_is_sfb;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_1_bits_uop_is_sfb = fast_wakeup_bits_uop_is_sfb;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_1_bits_uop_br_mask = fast_wakeup_bits_uop_br_mask;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_1_bits_uop_br_mask = fast_wakeup_bits_uop_br_mask;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_1_bits_uop_br_tag = fast_wakeup_bits_uop_br_tag;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_1_bits_uop_br_tag = fast_wakeup_bits_uop_br_tag;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_1_bits_uop_ftq_idx = fast_wakeup_bits_uop_ftq_idx;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_1_bits_uop_ftq_idx = fast_wakeup_bits_uop_ftq_idx;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_1_bits_uop_edge_inst = fast_wakeup_bits_uop_edge_inst;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_1_bits_uop_edge_inst = fast_wakeup_bits_uop_edge_inst;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_1_bits_uop_pc_lob = fast_wakeup_bits_uop_pc_lob;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_1_bits_uop_pc_lob = fast_wakeup_bits_uop_pc_lob;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_1_bits_uop_taken = fast_wakeup_bits_uop_taken;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_1_bits_uop_taken = fast_wakeup_bits_uop_taken;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_1_bits_uop_imm_packed = fast_wakeup_bits_uop_imm_packed;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_1_bits_uop_imm_packed = fast_wakeup_bits_uop_imm_packed;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_1_bits_uop_csr_addr = fast_wakeup_bits_uop_csr_addr;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_1_bits_uop_csr_addr = fast_wakeup_bits_uop_csr_addr;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_1_bits_uop_rob_idx = fast_wakeup_bits_uop_rob_idx;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_1_bits_uop_rob_idx = fast_wakeup_bits_uop_rob_idx;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_1_bits_uop_ldq_idx = fast_wakeup_bits_uop_ldq_idx;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_1_bits_uop_ldq_idx = fast_wakeup_bits_uop_ldq_idx;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_1_bits_uop_stq_idx = fast_wakeup_bits_uop_stq_idx;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_1_bits_uop_stq_idx = fast_wakeup_bits_uop_stq_idx;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_1_bits_uop_rxq_idx = fast_wakeup_bits_uop_rxq_idx;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_1_bits_uop_rxq_idx = fast_wakeup_bits_uop_rxq_idx;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_1_bits_uop_pdst = fast_wakeup_bits_uop_pdst;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_1_bits_uop_pdst = fast_wakeup_bits_uop_pdst;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_1_bits_uop_prs1 = fast_wakeup_bits_uop_prs1;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_1_bits_uop_prs1 = fast_wakeup_bits_uop_prs1;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_1_bits_uop_prs2 = fast_wakeup_bits_uop_prs2;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_1_bits_uop_prs2 = fast_wakeup_bits_uop_prs2;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_1_bits_uop_prs3 = fast_wakeup_bits_uop_prs3;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_1_bits_uop_prs3 = fast_wakeup_bits_uop_prs3;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_1_bits_uop_ppred = fast_wakeup_bits_uop_ppred;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_1_bits_uop_ppred = fast_wakeup_bits_uop_ppred;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_1_bits_uop_prs1_busy = fast_wakeup_bits_uop_prs1_busy;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_1_bits_uop_prs1_busy = fast_wakeup_bits_uop_prs1_busy;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_1_bits_uop_prs2_busy = fast_wakeup_bits_uop_prs2_busy;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_1_bits_uop_prs2_busy = fast_wakeup_bits_uop_prs2_busy;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_1_bits_uop_prs3_busy = fast_wakeup_bits_uop_prs3_busy;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_1_bits_uop_prs3_busy = fast_wakeup_bits_uop_prs3_busy;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_1_bits_uop_ppred_busy = fast_wakeup_bits_uop_ppred_busy;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_1_bits_uop_ppred_busy = fast_wakeup_bits_uop_ppred_busy;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_1_bits_uop_stale_pdst = fast_wakeup_bits_uop_stale_pdst;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_1_bits_uop_stale_pdst = fast_wakeup_bits_uop_stale_pdst;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_1_bits_uop_exception = fast_wakeup_bits_uop_exception;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_1_bits_uop_exception = fast_wakeup_bits_uop_exception;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_1_bits_uop_exc_cause = fast_wakeup_bits_uop_exc_cause;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_1_bits_uop_exc_cause = fast_wakeup_bits_uop_exc_cause;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_1_bits_uop_bypassable = fast_wakeup_bits_uop_bypassable;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_1_bits_uop_bypassable = fast_wakeup_bits_uop_bypassable;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_1_bits_uop_mem_cmd = fast_wakeup_bits_uop_mem_cmd;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_1_bits_uop_mem_cmd = fast_wakeup_bits_uop_mem_cmd;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_1_bits_uop_mem_size = fast_wakeup_bits_uop_mem_size;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_1_bits_uop_mem_size = fast_wakeup_bits_uop_mem_size;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_1_bits_uop_mem_signed = fast_wakeup_bits_uop_mem_signed;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_1_bits_uop_mem_signed = fast_wakeup_bits_uop_mem_signed;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_1_bits_uop_is_fence = fast_wakeup_bits_uop_is_fence;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_1_bits_uop_is_fence = fast_wakeup_bits_uop_is_fence;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_1_bits_uop_is_fencei = fast_wakeup_bits_uop_is_fencei;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_1_bits_uop_is_fencei = fast_wakeup_bits_uop_is_fencei;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_1_bits_uop_is_amo = fast_wakeup_bits_uop_is_amo;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_1_bits_uop_is_amo = fast_wakeup_bits_uop_is_amo;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_1_bits_uop_uses_ldq = fast_wakeup_bits_uop_uses_ldq;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_1_bits_uop_uses_ldq = fast_wakeup_bits_uop_uses_ldq;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_1_bits_uop_uses_stq = fast_wakeup_bits_uop_uses_stq;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_1_bits_uop_uses_stq = fast_wakeup_bits_uop_uses_stq;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_1_bits_uop_is_sys_pc2epc = fast_wakeup_bits_uop_is_sys_pc2epc;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_1_bits_uop_is_sys_pc2epc = fast_wakeup_bits_uop_is_sys_pc2epc;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_1_bits_uop_is_unique = fast_wakeup_bits_uop_is_unique;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_1_bits_uop_is_unique = fast_wakeup_bits_uop_is_unique;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_1_bits_uop_flush_on_commit = fast_wakeup_bits_uop_flush_on_commit;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_1_bits_uop_flush_on_commit = fast_wakeup_bits_uop_flush_on_commit;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_1_bits_uop_ldst_is_rs1 = fast_wakeup_bits_uop_ldst_is_rs1;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_1_bits_uop_ldst_is_rs1 = fast_wakeup_bits_uop_ldst_is_rs1;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_1_bits_uop_ldst = fast_wakeup_bits_uop_ldst;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_1_bits_uop_ldst = fast_wakeup_bits_uop_ldst;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_1_bits_uop_lrs1 = fast_wakeup_bits_uop_lrs1;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_1_bits_uop_lrs1 = fast_wakeup_bits_uop_lrs1;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_1_bits_uop_lrs2 = fast_wakeup_bits_uop_lrs2;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_1_bits_uop_lrs2 = fast_wakeup_bits_uop_lrs2;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_1_bits_uop_lrs3 = fast_wakeup_bits_uop_lrs3;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_1_bits_uop_lrs3 = fast_wakeup_bits_uop_lrs3;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_1_bits_uop_ldst_val = fast_wakeup_bits_uop_ldst_val;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_1_bits_uop_ldst_val = fast_wakeup_bits_uop_ldst_val;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_1_bits_uop_dst_rtype = fast_wakeup_bits_uop_dst_rtype;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_1_bits_uop_dst_rtype = fast_wakeup_bits_uop_dst_rtype;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_1_bits_uop_lrs1_rtype = fast_wakeup_bits_uop_lrs1_rtype;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_1_bits_uop_lrs1_rtype = fast_wakeup_bits_uop_lrs1_rtype;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_1_bits_uop_lrs2_rtype = fast_wakeup_bits_uop_lrs2_rtype;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_1_bits_uop_lrs2_rtype = fast_wakeup_bits_uop_lrs2_rtype;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_1_bits_uop_frs3_en = fast_wakeup_bits_uop_frs3_en;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_1_bits_uop_frs3_en = fast_wakeup_bits_uop_frs3_en;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_1_bits_uop_fp_val = fast_wakeup_bits_uop_fp_val;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_1_bits_uop_fp_val = fast_wakeup_bits_uop_fp_val;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_1_bits_uop_fp_single = fast_wakeup_bits_uop_fp_single;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_1_bits_uop_fp_single = fast_wakeup_bits_uop_fp_single;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_1_bits_uop_xcpt_pf_if = fast_wakeup_bits_uop_xcpt_pf_if;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_1_bits_uop_xcpt_pf_if = fast_wakeup_bits_uop_xcpt_pf_if;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_1_bits_uop_xcpt_ae_if = fast_wakeup_bits_uop_xcpt_ae_if;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_1_bits_uop_xcpt_ae_if = fast_wakeup_bits_uop_xcpt_ae_if;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_1_bits_uop_xcpt_ma_if = fast_wakeup_bits_uop_xcpt_ma_if;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_1_bits_uop_xcpt_ma_if = fast_wakeup_bits_uop_xcpt_ma_if;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_1_bits_uop_bp_debug_if = fast_wakeup_bits_uop_bp_debug_if;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_1_bits_uop_bp_debug_if = fast_wakeup_bits_uop_bp_debug_if;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_1_bits_uop_bp_xcpt_if = fast_wakeup_bits_uop_bp_xcpt_if;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_1_bits_uop_bp_xcpt_if = fast_wakeup_bits_uop_bp_xcpt_if;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_1_bits_uop_debug_fsrc = fast_wakeup_bits_uop_debug_fsrc;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_1_bits_uop_debug_fsrc = fast_wakeup_bits_uop_debug_fsrc;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_1_bits_uop_debug_tsrc = fast_wakeup_bits_uop_debug_tsrc;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_1_bits_uop_debug_tsrc = fast_wakeup_bits_uop_debug_tsrc;\t// @[core.scala:148:30, :814:29]\n wire _slow_wakeup_valid_T_5;\t// @[core.scala:834:59]\n assign int_iss_wakeups_2_valid = slow_wakeup_valid;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_2_valid = slow_wakeup_valid;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_2_bits_uop_uopc = slow_wakeup_bits_uop_uopc;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_2_bits_uop_uopc = slow_wakeup_bits_uop_uopc;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_2_bits_uop_inst = slow_wakeup_bits_uop_inst;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_2_bits_uop_inst = slow_wakeup_bits_uop_inst;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_2_bits_uop_debug_inst = slow_wakeup_bits_uop_debug_inst;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_2_bits_uop_debug_inst = slow_wakeup_bits_uop_debug_inst;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_2_bits_uop_is_rvc = slow_wakeup_bits_uop_is_rvc;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_2_bits_uop_is_rvc = slow_wakeup_bits_uop_is_rvc;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_2_bits_uop_debug_pc = slow_wakeup_bits_uop_debug_pc;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_2_bits_uop_debug_pc = slow_wakeup_bits_uop_debug_pc;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_2_bits_uop_iq_type = slow_wakeup_bits_uop_iq_type;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_2_bits_uop_iq_type = slow_wakeup_bits_uop_iq_type;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_2_bits_uop_fu_code = slow_wakeup_bits_uop_fu_code;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_2_bits_uop_fu_code = slow_wakeup_bits_uop_fu_code;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_2_bits_uop_ctrl_br_type = slow_wakeup_bits_uop_ctrl_br_type;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_2_bits_uop_ctrl_br_type = slow_wakeup_bits_uop_ctrl_br_type;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_2_bits_uop_ctrl_op1_sel = slow_wakeup_bits_uop_ctrl_op1_sel;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_2_bits_uop_ctrl_op1_sel = slow_wakeup_bits_uop_ctrl_op1_sel;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_2_bits_uop_ctrl_op2_sel = slow_wakeup_bits_uop_ctrl_op2_sel;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_2_bits_uop_ctrl_op2_sel = slow_wakeup_bits_uop_ctrl_op2_sel;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_2_bits_uop_ctrl_imm_sel = slow_wakeup_bits_uop_ctrl_imm_sel;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_2_bits_uop_ctrl_imm_sel = slow_wakeup_bits_uop_ctrl_imm_sel;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_2_bits_uop_ctrl_op_fcn = slow_wakeup_bits_uop_ctrl_op_fcn;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_2_bits_uop_ctrl_op_fcn = slow_wakeup_bits_uop_ctrl_op_fcn;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_2_bits_uop_ctrl_fcn_dw = slow_wakeup_bits_uop_ctrl_fcn_dw;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_2_bits_uop_ctrl_fcn_dw = slow_wakeup_bits_uop_ctrl_fcn_dw;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_2_bits_uop_ctrl_csr_cmd = slow_wakeup_bits_uop_ctrl_csr_cmd;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_2_bits_uop_ctrl_csr_cmd = slow_wakeup_bits_uop_ctrl_csr_cmd;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_2_bits_uop_ctrl_is_load = slow_wakeup_bits_uop_ctrl_is_load;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_2_bits_uop_ctrl_is_load = slow_wakeup_bits_uop_ctrl_is_load;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_2_bits_uop_ctrl_is_sta = slow_wakeup_bits_uop_ctrl_is_sta;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_2_bits_uop_ctrl_is_sta = slow_wakeup_bits_uop_ctrl_is_sta;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_2_bits_uop_ctrl_is_std = slow_wakeup_bits_uop_ctrl_is_std;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_2_bits_uop_ctrl_is_std = slow_wakeup_bits_uop_ctrl_is_std;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_2_bits_uop_iw_state = slow_wakeup_bits_uop_iw_state;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_2_bits_uop_iw_state = slow_wakeup_bits_uop_iw_state;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_2_bits_uop_iw_p1_poisoned = slow_wakeup_bits_uop_iw_p1_poisoned;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_2_bits_uop_iw_p1_poisoned = slow_wakeup_bits_uop_iw_p1_poisoned;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_2_bits_uop_iw_p2_poisoned = slow_wakeup_bits_uop_iw_p2_poisoned;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_2_bits_uop_iw_p2_poisoned = slow_wakeup_bits_uop_iw_p2_poisoned;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_2_bits_uop_is_br = slow_wakeup_bits_uop_is_br;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_2_bits_uop_is_br = slow_wakeup_bits_uop_is_br;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_2_bits_uop_is_jalr = slow_wakeup_bits_uop_is_jalr;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_2_bits_uop_is_jalr = slow_wakeup_bits_uop_is_jalr;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_2_bits_uop_is_jal = slow_wakeup_bits_uop_is_jal;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_2_bits_uop_is_jal = slow_wakeup_bits_uop_is_jal;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_2_bits_uop_is_sfb = slow_wakeup_bits_uop_is_sfb;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_2_bits_uop_is_sfb = slow_wakeup_bits_uop_is_sfb;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_2_bits_uop_br_mask = slow_wakeup_bits_uop_br_mask;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_2_bits_uop_br_mask = slow_wakeup_bits_uop_br_mask;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_2_bits_uop_br_tag = slow_wakeup_bits_uop_br_tag;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_2_bits_uop_br_tag = slow_wakeup_bits_uop_br_tag;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_2_bits_uop_ftq_idx = slow_wakeup_bits_uop_ftq_idx;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_2_bits_uop_ftq_idx = slow_wakeup_bits_uop_ftq_idx;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_2_bits_uop_edge_inst = slow_wakeup_bits_uop_edge_inst;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_2_bits_uop_edge_inst = slow_wakeup_bits_uop_edge_inst;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_2_bits_uop_pc_lob = slow_wakeup_bits_uop_pc_lob;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_2_bits_uop_pc_lob = slow_wakeup_bits_uop_pc_lob;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_2_bits_uop_taken = slow_wakeup_bits_uop_taken;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_2_bits_uop_taken = slow_wakeup_bits_uop_taken;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_2_bits_uop_imm_packed = slow_wakeup_bits_uop_imm_packed;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_2_bits_uop_imm_packed = slow_wakeup_bits_uop_imm_packed;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_2_bits_uop_csr_addr = slow_wakeup_bits_uop_csr_addr;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_2_bits_uop_csr_addr = slow_wakeup_bits_uop_csr_addr;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_2_bits_uop_rob_idx = slow_wakeup_bits_uop_rob_idx;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_2_bits_uop_rob_idx = slow_wakeup_bits_uop_rob_idx;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_2_bits_uop_ldq_idx = slow_wakeup_bits_uop_ldq_idx;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_2_bits_uop_ldq_idx = slow_wakeup_bits_uop_ldq_idx;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_2_bits_uop_stq_idx = slow_wakeup_bits_uop_stq_idx;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_2_bits_uop_stq_idx = slow_wakeup_bits_uop_stq_idx;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_2_bits_uop_rxq_idx = slow_wakeup_bits_uop_rxq_idx;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_2_bits_uop_rxq_idx = slow_wakeup_bits_uop_rxq_idx;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_2_bits_uop_pdst = slow_wakeup_bits_uop_pdst;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_2_bits_uop_pdst = slow_wakeup_bits_uop_pdst;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_2_bits_uop_prs1 = slow_wakeup_bits_uop_prs1;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_2_bits_uop_prs1 = slow_wakeup_bits_uop_prs1;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_2_bits_uop_prs2 = slow_wakeup_bits_uop_prs2;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_2_bits_uop_prs2 = slow_wakeup_bits_uop_prs2;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_2_bits_uop_prs3 = slow_wakeup_bits_uop_prs3;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_2_bits_uop_prs3 = slow_wakeup_bits_uop_prs3;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_2_bits_uop_ppred = slow_wakeup_bits_uop_ppred;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_2_bits_uop_ppred = slow_wakeup_bits_uop_ppred;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_2_bits_uop_prs1_busy = slow_wakeup_bits_uop_prs1_busy;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_2_bits_uop_prs1_busy = slow_wakeup_bits_uop_prs1_busy;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_2_bits_uop_prs2_busy = slow_wakeup_bits_uop_prs2_busy;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_2_bits_uop_prs2_busy = slow_wakeup_bits_uop_prs2_busy;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_2_bits_uop_prs3_busy = slow_wakeup_bits_uop_prs3_busy;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_2_bits_uop_prs3_busy = slow_wakeup_bits_uop_prs3_busy;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_2_bits_uop_ppred_busy = slow_wakeup_bits_uop_ppred_busy;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_2_bits_uop_ppred_busy = slow_wakeup_bits_uop_ppred_busy;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_2_bits_uop_stale_pdst = slow_wakeup_bits_uop_stale_pdst;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_2_bits_uop_stale_pdst = slow_wakeup_bits_uop_stale_pdst;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_2_bits_uop_exception = slow_wakeup_bits_uop_exception;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_2_bits_uop_exception = slow_wakeup_bits_uop_exception;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_2_bits_uop_exc_cause = slow_wakeup_bits_uop_exc_cause;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_2_bits_uop_exc_cause = slow_wakeup_bits_uop_exc_cause;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_2_bits_uop_bypassable = slow_wakeup_bits_uop_bypassable;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_2_bits_uop_bypassable = slow_wakeup_bits_uop_bypassable;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_2_bits_uop_mem_cmd = slow_wakeup_bits_uop_mem_cmd;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_2_bits_uop_mem_cmd = slow_wakeup_bits_uop_mem_cmd;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_2_bits_uop_mem_size = slow_wakeup_bits_uop_mem_size;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_2_bits_uop_mem_size = slow_wakeup_bits_uop_mem_size;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_2_bits_uop_mem_signed = slow_wakeup_bits_uop_mem_signed;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_2_bits_uop_mem_signed = slow_wakeup_bits_uop_mem_signed;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_2_bits_uop_is_fence = slow_wakeup_bits_uop_is_fence;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_2_bits_uop_is_fence = slow_wakeup_bits_uop_is_fence;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_2_bits_uop_is_fencei = slow_wakeup_bits_uop_is_fencei;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_2_bits_uop_is_fencei = slow_wakeup_bits_uop_is_fencei;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_2_bits_uop_is_amo = slow_wakeup_bits_uop_is_amo;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_2_bits_uop_is_amo = slow_wakeup_bits_uop_is_amo;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_2_bits_uop_uses_ldq = slow_wakeup_bits_uop_uses_ldq;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_2_bits_uop_uses_ldq = slow_wakeup_bits_uop_uses_ldq;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_2_bits_uop_uses_stq = slow_wakeup_bits_uop_uses_stq;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_2_bits_uop_uses_stq = slow_wakeup_bits_uop_uses_stq;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_2_bits_uop_is_sys_pc2epc = slow_wakeup_bits_uop_is_sys_pc2epc;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_2_bits_uop_is_sys_pc2epc = slow_wakeup_bits_uop_is_sys_pc2epc;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_2_bits_uop_is_unique = slow_wakeup_bits_uop_is_unique;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_2_bits_uop_is_unique = slow_wakeup_bits_uop_is_unique;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_2_bits_uop_flush_on_commit = slow_wakeup_bits_uop_flush_on_commit;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_2_bits_uop_flush_on_commit = slow_wakeup_bits_uop_flush_on_commit;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_2_bits_uop_ldst_is_rs1 = slow_wakeup_bits_uop_ldst_is_rs1;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_2_bits_uop_ldst_is_rs1 = slow_wakeup_bits_uop_ldst_is_rs1;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_2_bits_uop_ldst = slow_wakeup_bits_uop_ldst;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_2_bits_uop_ldst = slow_wakeup_bits_uop_ldst;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_2_bits_uop_lrs1 = slow_wakeup_bits_uop_lrs1;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_2_bits_uop_lrs1 = slow_wakeup_bits_uop_lrs1;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_2_bits_uop_lrs2 = slow_wakeup_bits_uop_lrs2;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_2_bits_uop_lrs2 = slow_wakeup_bits_uop_lrs2;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_2_bits_uop_lrs3 = slow_wakeup_bits_uop_lrs3;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_2_bits_uop_lrs3 = slow_wakeup_bits_uop_lrs3;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_2_bits_uop_ldst_val = slow_wakeup_bits_uop_ldst_val;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_2_bits_uop_ldst_val = slow_wakeup_bits_uop_ldst_val;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_2_bits_uop_dst_rtype = slow_wakeup_bits_uop_dst_rtype;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_2_bits_uop_dst_rtype = slow_wakeup_bits_uop_dst_rtype;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_2_bits_uop_lrs1_rtype = slow_wakeup_bits_uop_lrs1_rtype;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_2_bits_uop_lrs1_rtype = slow_wakeup_bits_uop_lrs1_rtype;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_2_bits_uop_lrs2_rtype = slow_wakeup_bits_uop_lrs2_rtype;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_2_bits_uop_lrs2_rtype = slow_wakeup_bits_uop_lrs2_rtype;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_2_bits_uop_frs3_en = slow_wakeup_bits_uop_frs3_en;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_2_bits_uop_frs3_en = slow_wakeup_bits_uop_frs3_en;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_2_bits_uop_fp_val = slow_wakeup_bits_uop_fp_val;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_2_bits_uop_fp_val = slow_wakeup_bits_uop_fp_val;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_2_bits_uop_fp_single = slow_wakeup_bits_uop_fp_single;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_2_bits_uop_fp_single = slow_wakeup_bits_uop_fp_single;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_2_bits_uop_xcpt_pf_if = slow_wakeup_bits_uop_xcpt_pf_if;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_2_bits_uop_xcpt_pf_if = slow_wakeup_bits_uop_xcpt_pf_if;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_2_bits_uop_xcpt_ae_if = slow_wakeup_bits_uop_xcpt_ae_if;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_2_bits_uop_xcpt_ae_if = slow_wakeup_bits_uop_xcpt_ae_if;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_2_bits_uop_xcpt_ma_if = slow_wakeup_bits_uop_xcpt_ma_if;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_2_bits_uop_xcpt_ma_if = slow_wakeup_bits_uop_xcpt_ma_if;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_2_bits_uop_bp_debug_if = slow_wakeup_bits_uop_bp_debug_if;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_2_bits_uop_bp_debug_if = slow_wakeup_bits_uop_bp_debug_if;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_2_bits_uop_bp_xcpt_if = slow_wakeup_bits_uop_bp_xcpt_if;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_2_bits_uop_bp_xcpt_if = slow_wakeup_bits_uop_bp_xcpt_if;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_2_bits_uop_debug_fsrc = slow_wakeup_bits_uop_debug_fsrc;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_2_bits_uop_debug_fsrc = slow_wakeup_bits_uop_debug_fsrc;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_2_bits_uop_debug_tsrc = slow_wakeup_bits_uop_debug_tsrc;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_2_bits_uop_debug_tsrc = slow_wakeup_bits_uop_debug_tsrc;\t// @[core.scala:148:30, :815:29]\n wire _T_99 = _alu_exe_unit_io_iresp_bits_uop_dst_rtype != 2'h2;\t// @[execution-units.scala:119:32]\n wire _slow_wakeup_valid_T;\t// @[micro-op.scala:149:36]\n assign _slow_wakeup_valid_T = _T_99;\t// @[micro-op.scala:149:36]\n wire _iregfile_io_write_ports_1_valid_T;\t// @[micro-op.scala:149:36]\n assign _iregfile_io_write_ports_1_valid_T = _T_99;\t// @[micro-op.scala:149:36]\n wire _rob_io_debug_wb_valids_1_T;\t// @[micro-op.scala:149:36]\n assign _rob_io_debug_wb_valids_1_T = _T_99;\t// @[micro-op.scala:149:36]\n wire _fast_wakeup_valid_T = iss_valids_1 & iss_uops_1_bypassable;\t// @[core.scala:172:24, :173:24, :824:45]\n wire _fast_wakeup_valid_T_1 = iss_uops_1_dst_rtype == 2'h0;\t// @[core.scala:173:24, :826:53]\n wire _fast_wakeup_valid_T_2 = _fast_wakeup_valid_T & _fast_wakeup_valid_T_1;\t// @[core.scala:824:45, :825:54, :826:53]\n wire _fast_wakeup_valid_T_3 = _fast_wakeup_valid_T_2 & iss_uops_1_ldst_val;\t// @[core.scala:173:24, :825:54, :826:64]\n wire _GEN_39 = iss_uops_1_iw_p1_poisoned | iss_uops_1_iw_p2_poisoned;\t// @[core.scala:173:24, :828:79]\n wire _fast_wakeup_valid_T_4;\t// @[core.scala:828:79]\n assign _fast_wakeup_valid_T_4 = _GEN_39;\t// @[core.scala:828:79]\n wire _pred_wakeup_valid_T_3;\t// @[core.scala:864:84]\n assign _pred_wakeup_valid_T_3 = _GEN_39;\t// @[core.scala:828:79, :864:84]\n wire _iregister_read_io_iss_valids_1_T;\t// @[core.scala:981:72]\n assign _iregister_read_io_iss_valids_1_T = _GEN_39;\t// @[core.scala:828:79, :981:72]\n wire _fast_wakeup_valid_T_5 = io_lsu_ld_miss_0 & _fast_wakeup_valid_T_4;\t// @[core.scala:51:7, :828:{48,79}]\n wire _fast_wakeup_valid_T_6 = ~_fast_wakeup_valid_T_5;\t// @[core.scala:828:{31,48}]\n assign _fast_wakeup_valid_T_7 = _fast_wakeup_valid_T_3 & _fast_wakeup_valid_T_6;\t// @[core.scala:826:64, :827:52, :828:31]\n assign fast_wakeup_valid = _fast_wakeup_valid_T_7;\t// @[core.scala:814:29, :827:52]\n wire _slow_wakeup_valid_T_1 = _alu_exe_unit_io_iresp_valid & _slow_wakeup_valid_T;\t// @[execution-units.scala:119:32]\n wire _slow_wakeup_valid_T_2 = ~_alu_exe_unit_io_iresp_bits_uop_bypassable;\t// @[execution-units.scala:119:32]\n wire _slow_wakeup_valid_T_3 = _slow_wakeup_valid_T_1 & _slow_wakeup_valid_T_2;\t// @[core.scala:832:42, :833:54, :834:33]\n wire _T_93 = _alu_exe_unit_io_iresp_bits_uop_dst_rtype == 2'h0;\t// @[execution-units.scala:119:32]\n wire _slow_wakeup_valid_T_4;\t// @[core.scala:835:57]\n assign _slow_wakeup_valid_T_4 = _T_93;\t// @[core.scala:835:57]\n wire _iregfile_io_write_ports_1_valid_T_2;\t// @[core.scala:1160:77]\n assign _iregfile_io_write_ports_1_valid_T_2 = _T_93;\t// @[core.scala:835:57, :1160:77]\n wire _rob_io_debug_wb_valids_1_T_2;\t// @[core.scala:1240:86]\n assign _rob_io_debug_wb_valids_1_T_2 = _T_93;\t// @[core.scala:835:57, :1240:86]\n assign _slow_wakeup_valid_T_5 = _slow_wakeup_valid_T_3 & _slow_wakeup_valid_T_4;\t// @[core.scala:833:54, :834:59, :835:57]\n assign slow_wakeup_valid = _slow_wakeup_valid_T_5;\t// @[core.scala:815:29, :834:59]\n wire _fast_wakeup_valid_T_15;\t// @[core.scala:827:52]\n assign int_iss_wakeups_3_valid = fast_wakeup_1_valid;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_3_valid = fast_wakeup_1_valid;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_3_bits_uop_uopc = fast_wakeup_1_bits_uop_uopc;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_3_bits_uop_uopc = fast_wakeup_1_bits_uop_uopc;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_3_bits_uop_inst = fast_wakeup_1_bits_uop_inst;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_3_bits_uop_inst = fast_wakeup_1_bits_uop_inst;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_3_bits_uop_debug_inst = fast_wakeup_1_bits_uop_debug_inst;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_3_bits_uop_debug_inst = fast_wakeup_1_bits_uop_debug_inst;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_3_bits_uop_is_rvc = fast_wakeup_1_bits_uop_is_rvc;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_3_bits_uop_is_rvc = fast_wakeup_1_bits_uop_is_rvc;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_3_bits_uop_debug_pc = fast_wakeup_1_bits_uop_debug_pc;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_3_bits_uop_debug_pc = fast_wakeup_1_bits_uop_debug_pc;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_3_bits_uop_iq_type = fast_wakeup_1_bits_uop_iq_type;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_3_bits_uop_iq_type = fast_wakeup_1_bits_uop_iq_type;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_3_bits_uop_fu_code = fast_wakeup_1_bits_uop_fu_code;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_3_bits_uop_fu_code = fast_wakeup_1_bits_uop_fu_code;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_3_bits_uop_ctrl_br_type = fast_wakeup_1_bits_uop_ctrl_br_type;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_3_bits_uop_ctrl_br_type = fast_wakeup_1_bits_uop_ctrl_br_type;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_3_bits_uop_ctrl_op1_sel = fast_wakeup_1_bits_uop_ctrl_op1_sel;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_3_bits_uop_ctrl_op1_sel = fast_wakeup_1_bits_uop_ctrl_op1_sel;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_3_bits_uop_ctrl_op2_sel = fast_wakeup_1_bits_uop_ctrl_op2_sel;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_3_bits_uop_ctrl_op2_sel = fast_wakeup_1_bits_uop_ctrl_op2_sel;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_3_bits_uop_ctrl_imm_sel = fast_wakeup_1_bits_uop_ctrl_imm_sel;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_3_bits_uop_ctrl_imm_sel = fast_wakeup_1_bits_uop_ctrl_imm_sel;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_3_bits_uop_ctrl_op_fcn = fast_wakeup_1_bits_uop_ctrl_op_fcn;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_3_bits_uop_ctrl_op_fcn = fast_wakeup_1_bits_uop_ctrl_op_fcn;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_3_bits_uop_ctrl_fcn_dw = fast_wakeup_1_bits_uop_ctrl_fcn_dw;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_3_bits_uop_ctrl_fcn_dw = fast_wakeup_1_bits_uop_ctrl_fcn_dw;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_3_bits_uop_ctrl_csr_cmd = fast_wakeup_1_bits_uop_ctrl_csr_cmd;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_3_bits_uop_ctrl_csr_cmd = fast_wakeup_1_bits_uop_ctrl_csr_cmd;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_3_bits_uop_ctrl_is_load = fast_wakeup_1_bits_uop_ctrl_is_load;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_3_bits_uop_ctrl_is_load = fast_wakeup_1_bits_uop_ctrl_is_load;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_3_bits_uop_ctrl_is_sta = fast_wakeup_1_bits_uop_ctrl_is_sta;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_3_bits_uop_ctrl_is_sta = fast_wakeup_1_bits_uop_ctrl_is_sta;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_3_bits_uop_ctrl_is_std = fast_wakeup_1_bits_uop_ctrl_is_std;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_3_bits_uop_ctrl_is_std = fast_wakeup_1_bits_uop_ctrl_is_std;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_3_bits_uop_iw_state = fast_wakeup_1_bits_uop_iw_state;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_3_bits_uop_iw_state = fast_wakeup_1_bits_uop_iw_state;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_3_bits_uop_iw_p1_poisoned = fast_wakeup_1_bits_uop_iw_p1_poisoned;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_3_bits_uop_iw_p1_poisoned = fast_wakeup_1_bits_uop_iw_p1_poisoned;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_3_bits_uop_iw_p2_poisoned = fast_wakeup_1_bits_uop_iw_p2_poisoned;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_3_bits_uop_iw_p2_poisoned = fast_wakeup_1_bits_uop_iw_p2_poisoned;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_3_bits_uop_is_br = fast_wakeup_1_bits_uop_is_br;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_3_bits_uop_is_br = fast_wakeup_1_bits_uop_is_br;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_3_bits_uop_is_jalr = fast_wakeup_1_bits_uop_is_jalr;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_3_bits_uop_is_jalr = fast_wakeup_1_bits_uop_is_jalr;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_3_bits_uop_is_jal = fast_wakeup_1_bits_uop_is_jal;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_3_bits_uop_is_jal = fast_wakeup_1_bits_uop_is_jal;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_3_bits_uop_is_sfb = fast_wakeup_1_bits_uop_is_sfb;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_3_bits_uop_is_sfb = fast_wakeup_1_bits_uop_is_sfb;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_3_bits_uop_br_mask = fast_wakeup_1_bits_uop_br_mask;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_3_bits_uop_br_mask = fast_wakeup_1_bits_uop_br_mask;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_3_bits_uop_br_tag = fast_wakeup_1_bits_uop_br_tag;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_3_bits_uop_br_tag = fast_wakeup_1_bits_uop_br_tag;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_3_bits_uop_ftq_idx = fast_wakeup_1_bits_uop_ftq_idx;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_3_bits_uop_ftq_idx = fast_wakeup_1_bits_uop_ftq_idx;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_3_bits_uop_edge_inst = fast_wakeup_1_bits_uop_edge_inst;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_3_bits_uop_edge_inst = fast_wakeup_1_bits_uop_edge_inst;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_3_bits_uop_pc_lob = fast_wakeup_1_bits_uop_pc_lob;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_3_bits_uop_pc_lob = fast_wakeup_1_bits_uop_pc_lob;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_3_bits_uop_taken = fast_wakeup_1_bits_uop_taken;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_3_bits_uop_taken = fast_wakeup_1_bits_uop_taken;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_3_bits_uop_imm_packed = fast_wakeup_1_bits_uop_imm_packed;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_3_bits_uop_imm_packed = fast_wakeup_1_bits_uop_imm_packed;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_3_bits_uop_csr_addr = fast_wakeup_1_bits_uop_csr_addr;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_3_bits_uop_csr_addr = fast_wakeup_1_bits_uop_csr_addr;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_3_bits_uop_rob_idx = fast_wakeup_1_bits_uop_rob_idx;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_3_bits_uop_rob_idx = fast_wakeup_1_bits_uop_rob_idx;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_3_bits_uop_ldq_idx = fast_wakeup_1_bits_uop_ldq_idx;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_3_bits_uop_ldq_idx = fast_wakeup_1_bits_uop_ldq_idx;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_3_bits_uop_stq_idx = fast_wakeup_1_bits_uop_stq_idx;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_3_bits_uop_stq_idx = fast_wakeup_1_bits_uop_stq_idx;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_3_bits_uop_rxq_idx = fast_wakeup_1_bits_uop_rxq_idx;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_3_bits_uop_rxq_idx = fast_wakeup_1_bits_uop_rxq_idx;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_3_bits_uop_pdst = fast_wakeup_1_bits_uop_pdst;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_3_bits_uop_pdst = fast_wakeup_1_bits_uop_pdst;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_3_bits_uop_prs1 = fast_wakeup_1_bits_uop_prs1;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_3_bits_uop_prs1 = fast_wakeup_1_bits_uop_prs1;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_3_bits_uop_prs2 = fast_wakeup_1_bits_uop_prs2;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_3_bits_uop_prs2 = fast_wakeup_1_bits_uop_prs2;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_3_bits_uop_prs3 = fast_wakeup_1_bits_uop_prs3;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_3_bits_uop_prs3 = fast_wakeup_1_bits_uop_prs3;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_3_bits_uop_ppred = fast_wakeup_1_bits_uop_ppred;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_3_bits_uop_ppred = fast_wakeup_1_bits_uop_ppred;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_3_bits_uop_prs1_busy = fast_wakeup_1_bits_uop_prs1_busy;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_3_bits_uop_prs1_busy = fast_wakeup_1_bits_uop_prs1_busy;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_3_bits_uop_prs2_busy = fast_wakeup_1_bits_uop_prs2_busy;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_3_bits_uop_prs2_busy = fast_wakeup_1_bits_uop_prs2_busy;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_3_bits_uop_prs3_busy = fast_wakeup_1_bits_uop_prs3_busy;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_3_bits_uop_prs3_busy = fast_wakeup_1_bits_uop_prs3_busy;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_3_bits_uop_ppred_busy = fast_wakeup_1_bits_uop_ppred_busy;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_3_bits_uop_ppred_busy = fast_wakeup_1_bits_uop_ppred_busy;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_3_bits_uop_stale_pdst = fast_wakeup_1_bits_uop_stale_pdst;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_3_bits_uop_stale_pdst = fast_wakeup_1_bits_uop_stale_pdst;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_3_bits_uop_exception = fast_wakeup_1_bits_uop_exception;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_3_bits_uop_exception = fast_wakeup_1_bits_uop_exception;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_3_bits_uop_exc_cause = fast_wakeup_1_bits_uop_exc_cause;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_3_bits_uop_exc_cause = fast_wakeup_1_bits_uop_exc_cause;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_3_bits_uop_bypassable = fast_wakeup_1_bits_uop_bypassable;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_3_bits_uop_bypassable = fast_wakeup_1_bits_uop_bypassable;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_3_bits_uop_mem_cmd = fast_wakeup_1_bits_uop_mem_cmd;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_3_bits_uop_mem_cmd = fast_wakeup_1_bits_uop_mem_cmd;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_3_bits_uop_mem_size = fast_wakeup_1_bits_uop_mem_size;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_3_bits_uop_mem_size = fast_wakeup_1_bits_uop_mem_size;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_3_bits_uop_mem_signed = fast_wakeup_1_bits_uop_mem_signed;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_3_bits_uop_mem_signed = fast_wakeup_1_bits_uop_mem_signed;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_3_bits_uop_is_fence = fast_wakeup_1_bits_uop_is_fence;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_3_bits_uop_is_fence = fast_wakeup_1_bits_uop_is_fence;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_3_bits_uop_is_fencei = fast_wakeup_1_bits_uop_is_fencei;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_3_bits_uop_is_fencei = fast_wakeup_1_bits_uop_is_fencei;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_3_bits_uop_is_amo = fast_wakeup_1_bits_uop_is_amo;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_3_bits_uop_is_amo = fast_wakeup_1_bits_uop_is_amo;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_3_bits_uop_uses_ldq = fast_wakeup_1_bits_uop_uses_ldq;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_3_bits_uop_uses_ldq = fast_wakeup_1_bits_uop_uses_ldq;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_3_bits_uop_uses_stq = fast_wakeup_1_bits_uop_uses_stq;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_3_bits_uop_uses_stq = fast_wakeup_1_bits_uop_uses_stq;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_3_bits_uop_is_sys_pc2epc = fast_wakeup_1_bits_uop_is_sys_pc2epc;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_3_bits_uop_is_sys_pc2epc = fast_wakeup_1_bits_uop_is_sys_pc2epc;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_3_bits_uop_is_unique = fast_wakeup_1_bits_uop_is_unique;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_3_bits_uop_is_unique = fast_wakeup_1_bits_uop_is_unique;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_3_bits_uop_flush_on_commit = fast_wakeup_1_bits_uop_flush_on_commit;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_3_bits_uop_flush_on_commit = fast_wakeup_1_bits_uop_flush_on_commit;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_3_bits_uop_ldst_is_rs1 = fast_wakeup_1_bits_uop_ldst_is_rs1;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_3_bits_uop_ldst_is_rs1 = fast_wakeup_1_bits_uop_ldst_is_rs1;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_3_bits_uop_ldst = fast_wakeup_1_bits_uop_ldst;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_3_bits_uop_ldst = fast_wakeup_1_bits_uop_ldst;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_3_bits_uop_lrs1 = fast_wakeup_1_bits_uop_lrs1;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_3_bits_uop_lrs1 = fast_wakeup_1_bits_uop_lrs1;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_3_bits_uop_lrs2 = fast_wakeup_1_bits_uop_lrs2;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_3_bits_uop_lrs2 = fast_wakeup_1_bits_uop_lrs2;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_3_bits_uop_lrs3 = fast_wakeup_1_bits_uop_lrs3;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_3_bits_uop_lrs3 = fast_wakeup_1_bits_uop_lrs3;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_3_bits_uop_ldst_val = fast_wakeup_1_bits_uop_ldst_val;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_3_bits_uop_ldst_val = fast_wakeup_1_bits_uop_ldst_val;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_3_bits_uop_dst_rtype = fast_wakeup_1_bits_uop_dst_rtype;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_3_bits_uop_dst_rtype = fast_wakeup_1_bits_uop_dst_rtype;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_3_bits_uop_lrs1_rtype = fast_wakeup_1_bits_uop_lrs1_rtype;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_3_bits_uop_lrs1_rtype = fast_wakeup_1_bits_uop_lrs1_rtype;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_3_bits_uop_lrs2_rtype = fast_wakeup_1_bits_uop_lrs2_rtype;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_3_bits_uop_lrs2_rtype = fast_wakeup_1_bits_uop_lrs2_rtype;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_3_bits_uop_frs3_en = fast_wakeup_1_bits_uop_frs3_en;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_3_bits_uop_frs3_en = fast_wakeup_1_bits_uop_frs3_en;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_3_bits_uop_fp_val = fast_wakeup_1_bits_uop_fp_val;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_3_bits_uop_fp_val = fast_wakeup_1_bits_uop_fp_val;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_3_bits_uop_fp_single = fast_wakeup_1_bits_uop_fp_single;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_3_bits_uop_fp_single = fast_wakeup_1_bits_uop_fp_single;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_3_bits_uop_xcpt_pf_if = fast_wakeup_1_bits_uop_xcpt_pf_if;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_3_bits_uop_xcpt_pf_if = fast_wakeup_1_bits_uop_xcpt_pf_if;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_3_bits_uop_xcpt_ae_if = fast_wakeup_1_bits_uop_xcpt_ae_if;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_3_bits_uop_xcpt_ae_if = fast_wakeup_1_bits_uop_xcpt_ae_if;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_3_bits_uop_xcpt_ma_if = fast_wakeup_1_bits_uop_xcpt_ma_if;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_3_bits_uop_xcpt_ma_if = fast_wakeup_1_bits_uop_xcpt_ma_if;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_3_bits_uop_bp_debug_if = fast_wakeup_1_bits_uop_bp_debug_if;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_3_bits_uop_bp_debug_if = fast_wakeup_1_bits_uop_bp_debug_if;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_3_bits_uop_bp_xcpt_if = fast_wakeup_1_bits_uop_bp_xcpt_if;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_3_bits_uop_bp_xcpt_if = fast_wakeup_1_bits_uop_bp_xcpt_if;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_3_bits_uop_debug_fsrc = fast_wakeup_1_bits_uop_debug_fsrc;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_3_bits_uop_debug_fsrc = fast_wakeup_1_bits_uop_debug_fsrc;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_3_bits_uop_debug_tsrc = fast_wakeup_1_bits_uop_debug_tsrc;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_3_bits_uop_debug_tsrc = fast_wakeup_1_bits_uop_debug_tsrc;\t// @[core.scala:148:30, :814:29]\n wire _slow_wakeup_valid_T_11;\t// @[core.scala:834:59]\n assign int_iss_wakeups_4_valid = slow_wakeup_1_valid;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_4_valid = slow_wakeup_1_valid;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_4_bits_uop_uopc = slow_wakeup_1_bits_uop_uopc;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_4_bits_uop_uopc = slow_wakeup_1_bits_uop_uopc;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_4_bits_uop_inst = slow_wakeup_1_bits_uop_inst;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_4_bits_uop_inst = slow_wakeup_1_bits_uop_inst;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_4_bits_uop_debug_inst = slow_wakeup_1_bits_uop_debug_inst;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_4_bits_uop_debug_inst = slow_wakeup_1_bits_uop_debug_inst;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_4_bits_uop_is_rvc = slow_wakeup_1_bits_uop_is_rvc;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_4_bits_uop_is_rvc = slow_wakeup_1_bits_uop_is_rvc;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_4_bits_uop_debug_pc = slow_wakeup_1_bits_uop_debug_pc;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_4_bits_uop_debug_pc = slow_wakeup_1_bits_uop_debug_pc;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_4_bits_uop_iq_type = slow_wakeup_1_bits_uop_iq_type;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_4_bits_uop_iq_type = slow_wakeup_1_bits_uop_iq_type;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_4_bits_uop_fu_code = slow_wakeup_1_bits_uop_fu_code;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_4_bits_uop_fu_code = slow_wakeup_1_bits_uop_fu_code;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_4_bits_uop_ctrl_br_type = slow_wakeup_1_bits_uop_ctrl_br_type;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_4_bits_uop_ctrl_br_type = slow_wakeup_1_bits_uop_ctrl_br_type;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_4_bits_uop_ctrl_op1_sel = slow_wakeup_1_bits_uop_ctrl_op1_sel;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_4_bits_uop_ctrl_op1_sel = slow_wakeup_1_bits_uop_ctrl_op1_sel;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_4_bits_uop_ctrl_op2_sel = slow_wakeup_1_bits_uop_ctrl_op2_sel;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_4_bits_uop_ctrl_op2_sel = slow_wakeup_1_bits_uop_ctrl_op2_sel;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_4_bits_uop_ctrl_imm_sel = slow_wakeup_1_bits_uop_ctrl_imm_sel;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_4_bits_uop_ctrl_imm_sel = slow_wakeup_1_bits_uop_ctrl_imm_sel;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_4_bits_uop_ctrl_op_fcn = slow_wakeup_1_bits_uop_ctrl_op_fcn;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_4_bits_uop_ctrl_op_fcn = slow_wakeup_1_bits_uop_ctrl_op_fcn;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_4_bits_uop_ctrl_fcn_dw = slow_wakeup_1_bits_uop_ctrl_fcn_dw;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_4_bits_uop_ctrl_fcn_dw = slow_wakeup_1_bits_uop_ctrl_fcn_dw;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_4_bits_uop_ctrl_csr_cmd = slow_wakeup_1_bits_uop_ctrl_csr_cmd;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_4_bits_uop_ctrl_csr_cmd = slow_wakeup_1_bits_uop_ctrl_csr_cmd;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_4_bits_uop_ctrl_is_load = slow_wakeup_1_bits_uop_ctrl_is_load;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_4_bits_uop_ctrl_is_load = slow_wakeup_1_bits_uop_ctrl_is_load;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_4_bits_uop_ctrl_is_sta = slow_wakeup_1_bits_uop_ctrl_is_sta;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_4_bits_uop_ctrl_is_sta = slow_wakeup_1_bits_uop_ctrl_is_sta;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_4_bits_uop_ctrl_is_std = slow_wakeup_1_bits_uop_ctrl_is_std;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_4_bits_uop_ctrl_is_std = slow_wakeup_1_bits_uop_ctrl_is_std;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_4_bits_uop_iw_state = slow_wakeup_1_bits_uop_iw_state;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_4_bits_uop_iw_state = slow_wakeup_1_bits_uop_iw_state;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_4_bits_uop_iw_p1_poisoned = slow_wakeup_1_bits_uop_iw_p1_poisoned;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_4_bits_uop_iw_p1_poisoned = slow_wakeup_1_bits_uop_iw_p1_poisoned;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_4_bits_uop_iw_p2_poisoned = slow_wakeup_1_bits_uop_iw_p2_poisoned;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_4_bits_uop_iw_p2_poisoned = slow_wakeup_1_bits_uop_iw_p2_poisoned;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_4_bits_uop_is_br = slow_wakeup_1_bits_uop_is_br;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_4_bits_uop_is_br = slow_wakeup_1_bits_uop_is_br;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_4_bits_uop_is_jalr = slow_wakeup_1_bits_uop_is_jalr;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_4_bits_uop_is_jalr = slow_wakeup_1_bits_uop_is_jalr;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_4_bits_uop_is_jal = slow_wakeup_1_bits_uop_is_jal;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_4_bits_uop_is_jal = slow_wakeup_1_bits_uop_is_jal;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_4_bits_uop_is_sfb = slow_wakeup_1_bits_uop_is_sfb;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_4_bits_uop_is_sfb = slow_wakeup_1_bits_uop_is_sfb;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_4_bits_uop_br_mask = slow_wakeup_1_bits_uop_br_mask;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_4_bits_uop_br_mask = slow_wakeup_1_bits_uop_br_mask;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_4_bits_uop_br_tag = slow_wakeup_1_bits_uop_br_tag;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_4_bits_uop_br_tag = slow_wakeup_1_bits_uop_br_tag;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_4_bits_uop_ftq_idx = slow_wakeup_1_bits_uop_ftq_idx;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_4_bits_uop_ftq_idx = slow_wakeup_1_bits_uop_ftq_idx;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_4_bits_uop_edge_inst = slow_wakeup_1_bits_uop_edge_inst;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_4_bits_uop_edge_inst = slow_wakeup_1_bits_uop_edge_inst;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_4_bits_uop_pc_lob = slow_wakeup_1_bits_uop_pc_lob;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_4_bits_uop_pc_lob = slow_wakeup_1_bits_uop_pc_lob;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_4_bits_uop_taken = slow_wakeup_1_bits_uop_taken;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_4_bits_uop_taken = slow_wakeup_1_bits_uop_taken;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_4_bits_uop_imm_packed = slow_wakeup_1_bits_uop_imm_packed;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_4_bits_uop_imm_packed = slow_wakeup_1_bits_uop_imm_packed;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_4_bits_uop_csr_addr = slow_wakeup_1_bits_uop_csr_addr;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_4_bits_uop_csr_addr = slow_wakeup_1_bits_uop_csr_addr;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_4_bits_uop_rob_idx = slow_wakeup_1_bits_uop_rob_idx;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_4_bits_uop_rob_idx = slow_wakeup_1_bits_uop_rob_idx;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_4_bits_uop_ldq_idx = slow_wakeup_1_bits_uop_ldq_idx;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_4_bits_uop_ldq_idx = slow_wakeup_1_bits_uop_ldq_idx;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_4_bits_uop_stq_idx = slow_wakeup_1_bits_uop_stq_idx;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_4_bits_uop_stq_idx = slow_wakeup_1_bits_uop_stq_idx;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_4_bits_uop_rxq_idx = slow_wakeup_1_bits_uop_rxq_idx;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_4_bits_uop_rxq_idx = slow_wakeup_1_bits_uop_rxq_idx;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_4_bits_uop_pdst = slow_wakeup_1_bits_uop_pdst;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_4_bits_uop_pdst = slow_wakeup_1_bits_uop_pdst;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_4_bits_uop_prs1 = slow_wakeup_1_bits_uop_prs1;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_4_bits_uop_prs1 = slow_wakeup_1_bits_uop_prs1;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_4_bits_uop_prs2 = slow_wakeup_1_bits_uop_prs2;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_4_bits_uop_prs2 = slow_wakeup_1_bits_uop_prs2;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_4_bits_uop_prs3 = slow_wakeup_1_bits_uop_prs3;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_4_bits_uop_prs3 = slow_wakeup_1_bits_uop_prs3;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_4_bits_uop_ppred = slow_wakeup_1_bits_uop_ppred;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_4_bits_uop_ppred = slow_wakeup_1_bits_uop_ppred;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_4_bits_uop_prs1_busy = slow_wakeup_1_bits_uop_prs1_busy;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_4_bits_uop_prs1_busy = slow_wakeup_1_bits_uop_prs1_busy;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_4_bits_uop_prs2_busy = slow_wakeup_1_bits_uop_prs2_busy;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_4_bits_uop_prs2_busy = slow_wakeup_1_bits_uop_prs2_busy;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_4_bits_uop_prs3_busy = slow_wakeup_1_bits_uop_prs3_busy;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_4_bits_uop_prs3_busy = slow_wakeup_1_bits_uop_prs3_busy;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_4_bits_uop_ppred_busy = slow_wakeup_1_bits_uop_ppred_busy;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_4_bits_uop_ppred_busy = slow_wakeup_1_bits_uop_ppred_busy;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_4_bits_uop_stale_pdst = slow_wakeup_1_bits_uop_stale_pdst;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_4_bits_uop_stale_pdst = slow_wakeup_1_bits_uop_stale_pdst;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_4_bits_uop_exception = slow_wakeup_1_bits_uop_exception;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_4_bits_uop_exception = slow_wakeup_1_bits_uop_exception;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_4_bits_uop_exc_cause = slow_wakeup_1_bits_uop_exc_cause;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_4_bits_uop_exc_cause = slow_wakeup_1_bits_uop_exc_cause;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_4_bits_uop_bypassable = slow_wakeup_1_bits_uop_bypassable;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_4_bits_uop_bypassable = slow_wakeup_1_bits_uop_bypassable;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_4_bits_uop_mem_cmd = slow_wakeup_1_bits_uop_mem_cmd;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_4_bits_uop_mem_cmd = slow_wakeup_1_bits_uop_mem_cmd;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_4_bits_uop_mem_size = slow_wakeup_1_bits_uop_mem_size;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_4_bits_uop_mem_size = slow_wakeup_1_bits_uop_mem_size;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_4_bits_uop_mem_signed = slow_wakeup_1_bits_uop_mem_signed;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_4_bits_uop_mem_signed = slow_wakeup_1_bits_uop_mem_signed;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_4_bits_uop_is_fence = slow_wakeup_1_bits_uop_is_fence;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_4_bits_uop_is_fence = slow_wakeup_1_bits_uop_is_fence;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_4_bits_uop_is_fencei = slow_wakeup_1_bits_uop_is_fencei;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_4_bits_uop_is_fencei = slow_wakeup_1_bits_uop_is_fencei;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_4_bits_uop_is_amo = slow_wakeup_1_bits_uop_is_amo;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_4_bits_uop_is_amo = slow_wakeup_1_bits_uop_is_amo;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_4_bits_uop_uses_ldq = slow_wakeup_1_bits_uop_uses_ldq;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_4_bits_uop_uses_ldq = slow_wakeup_1_bits_uop_uses_ldq;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_4_bits_uop_uses_stq = slow_wakeup_1_bits_uop_uses_stq;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_4_bits_uop_uses_stq = slow_wakeup_1_bits_uop_uses_stq;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_4_bits_uop_is_sys_pc2epc = slow_wakeup_1_bits_uop_is_sys_pc2epc;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_4_bits_uop_is_sys_pc2epc = slow_wakeup_1_bits_uop_is_sys_pc2epc;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_4_bits_uop_is_unique = slow_wakeup_1_bits_uop_is_unique;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_4_bits_uop_is_unique = slow_wakeup_1_bits_uop_is_unique;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_4_bits_uop_flush_on_commit = slow_wakeup_1_bits_uop_flush_on_commit;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_4_bits_uop_flush_on_commit = slow_wakeup_1_bits_uop_flush_on_commit;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_4_bits_uop_ldst_is_rs1 = slow_wakeup_1_bits_uop_ldst_is_rs1;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_4_bits_uop_ldst_is_rs1 = slow_wakeup_1_bits_uop_ldst_is_rs1;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_4_bits_uop_ldst = slow_wakeup_1_bits_uop_ldst;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_4_bits_uop_ldst = slow_wakeup_1_bits_uop_ldst;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_4_bits_uop_lrs1 = slow_wakeup_1_bits_uop_lrs1;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_4_bits_uop_lrs1 = slow_wakeup_1_bits_uop_lrs1;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_4_bits_uop_lrs2 = slow_wakeup_1_bits_uop_lrs2;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_4_bits_uop_lrs2 = slow_wakeup_1_bits_uop_lrs2;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_4_bits_uop_lrs3 = slow_wakeup_1_bits_uop_lrs3;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_4_bits_uop_lrs3 = slow_wakeup_1_bits_uop_lrs3;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_4_bits_uop_ldst_val = slow_wakeup_1_bits_uop_ldst_val;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_4_bits_uop_ldst_val = slow_wakeup_1_bits_uop_ldst_val;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_4_bits_uop_dst_rtype = slow_wakeup_1_bits_uop_dst_rtype;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_4_bits_uop_dst_rtype = slow_wakeup_1_bits_uop_dst_rtype;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_4_bits_uop_lrs1_rtype = slow_wakeup_1_bits_uop_lrs1_rtype;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_4_bits_uop_lrs1_rtype = slow_wakeup_1_bits_uop_lrs1_rtype;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_4_bits_uop_lrs2_rtype = slow_wakeup_1_bits_uop_lrs2_rtype;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_4_bits_uop_lrs2_rtype = slow_wakeup_1_bits_uop_lrs2_rtype;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_4_bits_uop_frs3_en = slow_wakeup_1_bits_uop_frs3_en;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_4_bits_uop_frs3_en = slow_wakeup_1_bits_uop_frs3_en;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_4_bits_uop_fp_val = slow_wakeup_1_bits_uop_fp_val;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_4_bits_uop_fp_val = slow_wakeup_1_bits_uop_fp_val;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_4_bits_uop_fp_single = slow_wakeup_1_bits_uop_fp_single;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_4_bits_uop_fp_single = slow_wakeup_1_bits_uop_fp_single;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_4_bits_uop_xcpt_pf_if = slow_wakeup_1_bits_uop_xcpt_pf_if;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_4_bits_uop_xcpt_pf_if = slow_wakeup_1_bits_uop_xcpt_pf_if;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_4_bits_uop_xcpt_ae_if = slow_wakeup_1_bits_uop_xcpt_ae_if;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_4_bits_uop_xcpt_ae_if = slow_wakeup_1_bits_uop_xcpt_ae_if;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_4_bits_uop_xcpt_ma_if = slow_wakeup_1_bits_uop_xcpt_ma_if;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_4_bits_uop_xcpt_ma_if = slow_wakeup_1_bits_uop_xcpt_ma_if;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_4_bits_uop_bp_debug_if = slow_wakeup_1_bits_uop_bp_debug_if;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_4_bits_uop_bp_debug_if = slow_wakeup_1_bits_uop_bp_debug_if;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_4_bits_uop_bp_xcpt_if = slow_wakeup_1_bits_uop_bp_xcpt_if;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_4_bits_uop_bp_xcpt_if = slow_wakeup_1_bits_uop_bp_xcpt_if;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_4_bits_uop_debug_fsrc = slow_wakeup_1_bits_uop_debug_fsrc;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_4_bits_uop_debug_fsrc = slow_wakeup_1_bits_uop_debug_fsrc;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_4_bits_uop_debug_tsrc = slow_wakeup_1_bits_uop_debug_tsrc;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_4_bits_uop_debug_tsrc = slow_wakeup_1_bits_uop_debug_tsrc;\t// @[core.scala:148:30, :815:29]\n wire _T_124 = _alu_exe_unit_1_io_iresp_bits_uop_dst_rtype != 2'h2;\t// @[execution-units.scala:119:32]\n wire _slow_wakeup_valid_T_6;\t// @[micro-op.scala:149:36]\n assign _slow_wakeup_valid_T_6 = _T_124;\t// @[micro-op.scala:149:36]\n wire _iregfile_io_write_ports_2_valid_T;\t// @[micro-op.scala:149:36]\n assign _iregfile_io_write_ports_2_valid_T = _T_124;\t// @[micro-op.scala:149:36]\n wire _rob_io_debug_wb_valids_2_T;\t// @[micro-op.scala:149:36]\n assign _rob_io_debug_wb_valids_2_T = _T_124;\t// @[micro-op.scala:149:36]\n wire _fast_wakeup_valid_T_8 = iss_valids_2 & iss_uops_2_bypassable;\t// @[core.scala:172:24, :173:24, :824:45]\n wire _fast_wakeup_valid_T_9 = iss_uops_2_dst_rtype == 2'h0;\t// @[core.scala:173:24, :826:53]\n wire _fast_wakeup_valid_T_10 = _fast_wakeup_valid_T_8 & _fast_wakeup_valid_T_9;\t// @[core.scala:824:45, :825:54, :826:53]\n wire _fast_wakeup_valid_T_11 = _fast_wakeup_valid_T_10 & iss_uops_2_ldst_val;\t// @[core.scala:173:24, :825:54, :826:64]\n wire _GEN_40 = iss_uops_2_iw_p1_poisoned | iss_uops_2_iw_p2_poisoned;\t// @[core.scala:173:24, :828:79]\n wire _fast_wakeup_valid_T_12;\t// @[core.scala:828:79]\n assign _fast_wakeup_valid_T_12 = _GEN_40;\t// @[core.scala:828:79]\n wire _iregister_read_io_iss_valids_2_T;\t// @[core.scala:981:72]\n assign _iregister_read_io_iss_valids_2_T = _GEN_40;\t// @[core.scala:828:79, :981:72]\n wire _fast_wakeup_valid_T_13 = io_lsu_ld_miss_0 & _fast_wakeup_valid_T_12;\t// @[core.scala:51:7, :828:{48,79}]\n wire _fast_wakeup_valid_T_14 = ~_fast_wakeup_valid_T_13;\t// @[core.scala:828:{31,48}]\n assign _fast_wakeup_valid_T_15 = _fast_wakeup_valid_T_11 & _fast_wakeup_valid_T_14;\t// @[core.scala:826:64, :827:52, :828:31]\n assign fast_wakeup_1_valid = _fast_wakeup_valid_T_15;\t// @[core.scala:814:29, :827:52]\n wire _slow_wakeup_valid_T_7 = _alu_exe_unit_1_io_iresp_valid & _slow_wakeup_valid_T_6;\t// @[execution-units.scala:119:32]\n wire _slow_wakeup_valid_T_8 = ~_alu_exe_unit_1_io_iresp_bits_uop_bypassable;\t// @[execution-units.scala:119:32]\n wire _slow_wakeup_valid_T_9 = _slow_wakeup_valid_T_7 & _slow_wakeup_valid_T_8;\t// @[core.scala:832:42, :833:54, :834:33]\n wire _T_118 = _alu_exe_unit_1_io_iresp_bits_uop_dst_rtype == 2'h0;\t// @[execution-units.scala:119:32]\n wire _slow_wakeup_valid_T_10;\t// @[core.scala:835:57]\n assign _slow_wakeup_valid_T_10 = _T_118;\t// @[core.scala:835:57]\n wire _iregfile_io_write_ports_2_valid_T_2;\t// @[core.scala:1160:77]\n assign _iregfile_io_write_ports_2_valid_T_2 = _T_118;\t// @[core.scala:835:57, :1160:77]\n wire _rob_io_debug_wb_valids_2_T_2;\t// @[core.scala:1240:86]\n assign _rob_io_debug_wb_valids_2_T_2 = _T_118;\t// @[core.scala:835:57, :1240:86]\n assign _slow_wakeup_valid_T_11 = _slow_wakeup_valid_T_9 & _slow_wakeup_valid_T_10;\t// @[core.scala:833:54, :834:59, :835:57]\n assign slow_wakeup_1_valid = _slow_wakeup_valid_T_11;\t// @[core.scala:815:29, :834:59]\n wire _fast_wakeup_valid_T_23;\t// @[core.scala:827:52]\n assign int_iss_wakeups_5_valid = fast_wakeup_2_valid;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_5_valid = fast_wakeup_2_valid;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_5_bits_uop_uopc = fast_wakeup_2_bits_uop_uopc;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_5_bits_uop_uopc = fast_wakeup_2_bits_uop_uopc;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_5_bits_uop_inst = fast_wakeup_2_bits_uop_inst;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_5_bits_uop_inst = fast_wakeup_2_bits_uop_inst;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_5_bits_uop_debug_inst = fast_wakeup_2_bits_uop_debug_inst;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_5_bits_uop_debug_inst = fast_wakeup_2_bits_uop_debug_inst;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_5_bits_uop_is_rvc = fast_wakeup_2_bits_uop_is_rvc;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_5_bits_uop_is_rvc = fast_wakeup_2_bits_uop_is_rvc;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_5_bits_uop_debug_pc = fast_wakeup_2_bits_uop_debug_pc;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_5_bits_uop_debug_pc = fast_wakeup_2_bits_uop_debug_pc;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_5_bits_uop_iq_type = fast_wakeup_2_bits_uop_iq_type;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_5_bits_uop_iq_type = fast_wakeup_2_bits_uop_iq_type;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_5_bits_uop_fu_code = fast_wakeup_2_bits_uop_fu_code;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_5_bits_uop_fu_code = fast_wakeup_2_bits_uop_fu_code;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_5_bits_uop_ctrl_br_type = fast_wakeup_2_bits_uop_ctrl_br_type;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_5_bits_uop_ctrl_br_type = fast_wakeup_2_bits_uop_ctrl_br_type;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_5_bits_uop_ctrl_op1_sel = fast_wakeup_2_bits_uop_ctrl_op1_sel;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_5_bits_uop_ctrl_op1_sel = fast_wakeup_2_bits_uop_ctrl_op1_sel;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_5_bits_uop_ctrl_op2_sel = fast_wakeup_2_bits_uop_ctrl_op2_sel;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_5_bits_uop_ctrl_op2_sel = fast_wakeup_2_bits_uop_ctrl_op2_sel;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_5_bits_uop_ctrl_imm_sel = fast_wakeup_2_bits_uop_ctrl_imm_sel;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_5_bits_uop_ctrl_imm_sel = fast_wakeup_2_bits_uop_ctrl_imm_sel;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_5_bits_uop_ctrl_op_fcn = fast_wakeup_2_bits_uop_ctrl_op_fcn;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_5_bits_uop_ctrl_op_fcn = fast_wakeup_2_bits_uop_ctrl_op_fcn;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_5_bits_uop_ctrl_fcn_dw = fast_wakeup_2_bits_uop_ctrl_fcn_dw;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_5_bits_uop_ctrl_fcn_dw = fast_wakeup_2_bits_uop_ctrl_fcn_dw;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_5_bits_uop_ctrl_csr_cmd = fast_wakeup_2_bits_uop_ctrl_csr_cmd;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_5_bits_uop_ctrl_csr_cmd = fast_wakeup_2_bits_uop_ctrl_csr_cmd;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_5_bits_uop_ctrl_is_load = fast_wakeup_2_bits_uop_ctrl_is_load;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_5_bits_uop_ctrl_is_load = fast_wakeup_2_bits_uop_ctrl_is_load;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_5_bits_uop_ctrl_is_sta = fast_wakeup_2_bits_uop_ctrl_is_sta;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_5_bits_uop_ctrl_is_sta = fast_wakeup_2_bits_uop_ctrl_is_sta;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_5_bits_uop_ctrl_is_std = fast_wakeup_2_bits_uop_ctrl_is_std;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_5_bits_uop_ctrl_is_std = fast_wakeup_2_bits_uop_ctrl_is_std;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_5_bits_uop_iw_state = fast_wakeup_2_bits_uop_iw_state;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_5_bits_uop_iw_state = fast_wakeup_2_bits_uop_iw_state;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_5_bits_uop_iw_p1_poisoned = fast_wakeup_2_bits_uop_iw_p1_poisoned;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_5_bits_uop_iw_p1_poisoned = fast_wakeup_2_bits_uop_iw_p1_poisoned;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_5_bits_uop_iw_p2_poisoned = fast_wakeup_2_bits_uop_iw_p2_poisoned;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_5_bits_uop_iw_p2_poisoned = fast_wakeup_2_bits_uop_iw_p2_poisoned;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_5_bits_uop_is_br = fast_wakeup_2_bits_uop_is_br;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_5_bits_uop_is_br = fast_wakeup_2_bits_uop_is_br;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_5_bits_uop_is_jalr = fast_wakeup_2_bits_uop_is_jalr;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_5_bits_uop_is_jalr = fast_wakeup_2_bits_uop_is_jalr;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_5_bits_uop_is_jal = fast_wakeup_2_bits_uop_is_jal;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_5_bits_uop_is_jal = fast_wakeup_2_bits_uop_is_jal;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_5_bits_uop_is_sfb = fast_wakeup_2_bits_uop_is_sfb;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_5_bits_uop_is_sfb = fast_wakeup_2_bits_uop_is_sfb;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_5_bits_uop_br_mask = fast_wakeup_2_bits_uop_br_mask;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_5_bits_uop_br_mask = fast_wakeup_2_bits_uop_br_mask;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_5_bits_uop_br_tag = fast_wakeup_2_bits_uop_br_tag;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_5_bits_uop_br_tag = fast_wakeup_2_bits_uop_br_tag;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_5_bits_uop_ftq_idx = fast_wakeup_2_bits_uop_ftq_idx;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_5_bits_uop_ftq_idx = fast_wakeup_2_bits_uop_ftq_idx;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_5_bits_uop_edge_inst = fast_wakeup_2_bits_uop_edge_inst;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_5_bits_uop_edge_inst = fast_wakeup_2_bits_uop_edge_inst;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_5_bits_uop_pc_lob = fast_wakeup_2_bits_uop_pc_lob;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_5_bits_uop_pc_lob = fast_wakeup_2_bits_uop_pc_lob;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_5_bits_uop_taken = fast_wakeup_2_bits_uop_taken;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_5_bits_uop_taken = fast_wakeup_2_bits_uop_taken;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_5_bits_uop_imm_packed = fast_wakeup_2_bits_uop_imm_packed;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_5_bits_uop_imm_packed = fast_wakeup_2_bits_uop_imm_packed;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_5_bits_uop_csr_addr = fast_wakeup_2_bits_uop_csr_addr;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_5_bits_uop_csr_addr = fast_wakeup_2_bits_uop_csr_addr;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_5_bits_uop_rob_idx = fast_wakeup_2_bits_uop_rob_idx;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_5_bits_uop_rob_idx = fast_wakeup_2_bits_uop_rob_idx;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_5_bits_uop_ldq_idx = fast_wakeup_2_bits_uop_ldq_idx;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_5_bits_uop_ldq_idx = fast_wakeup_2_bits_uop_ldq_idx;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_5_bits_uop_stq_idx = fast_wakeup_2_bits_uop_stq_idx;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_5_bits_uop_stq_idx = fast_wakeup_2_bits_uop_stq_idx;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_5_bits_uop_rxq_idx = fast_wakeup_2_bits_uop_rxq_idx;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_5_bits_uop_rxq_idx = fast_wakeup_2_bits_uop_rxq_idx;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_5_bits_uop_pdst = fast_wakeup_2_bits_uop_pdst;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_5_bits_uop_pdst = fast_wakeup_2_bits_uop_pdst;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_5_bits_uop_prs1 = fast_wakeup_2_bits_uop_prs1;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_5_bits_uop_prs1 = fast_wakeup_2_bits_uop_prs1;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_5_bits_uop_prs2 = fast_wakeup_2_bits_uop_prs2;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_5_bits_uop_prs2 = fast_wakeup_2_bits_uop_prs2;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_5_bits_uop_prs3 = fast_wakeup_2_bits_uop_prs3;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_5_bits_uop_prs3 = fast_wakeup_2_bits_uop_prs3;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_5_bits_uop_ppred = fast_wakeup_2_bits_uop_ppred;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_5_bits_uop_ppred = fast_wakeup_2_bits_uop_ppred;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_5_bits_uop_prs1_busy = fast_wakeup_2_bits_uop_prs1_busy;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_5_bits_uop_prs1_busy = fast_wakeup_2_bits_uop_prs1_busy;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_5_bits_uop_prs2_busy = fast_wakeup_2_bits_uop_prs2_busy;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_5_bits_uop_prs2_busy = fast_wakeup_2_bits_uop_prs2_busy;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_5_bits_uop_prs3_busy = fast_wakeup_2_bits_uop_prs3_busy;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_5_bits_uop_prs3_busy = fast_wakeup_2_bits_uop_prs3_busy;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_5_bits_uop_ppred_busy = fast_wakeup_2_bits_uop_ppred_busy;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_5_bits_uop_ppred_busy = fast_wakeup_2_bits_uop_ppred_busy;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_5_bits_uop_stale_pdst = fast_wakeup_2_bits_uop_stale_pdst;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_5_bits_uop_stale_pdst = fast_wakeup_2_bits_uop_stale_pdst;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_5_bits_uop_exception = fast_wakeup_2_bits_uop_exception;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_5_bits_uop_exception = fast_wakeup_2_bits_uop_exception;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_5_bits_uop_exc_cause = fast_wakeup_2_bits_uop_exc_cause;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_5_bits_uop_exc_cause = fast_wakeup_2_bits_uop_exc_cause;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_5_bits_uop_bypassable = fast_wakeup_2_bits_uop_bypassable;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_5_bits_uop_bypassable = fast_wakeup_2_bits_uop_bypassable;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_5_bits_uop_mem_cmd = fast_wakeup_2_bits_uop_mem_cmd;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_5_bits_uop_mem_cmd = fast_wakeup_2_bits_uop_mem_cmd;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_5_bits_uop_mem_size = fast_wakeup_2_bits_uop_mem_size;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_5_bits_uop_mem_size = fast_wakeup_2_bits_uop_mem_size;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_5_bits_uop_mem_signed = fast_wakeup_2_bits_uop_mem_signed;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_5_bits_uop_mem_signed = fast_wakeup_2_bits_uop_mem_signed;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_5_bits_uop_is_fence = fast_wakeup_2_bits_uop_is_fence;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_5_bits_uop_is_fence = fast_wakeup_2_bits_uop_is_fence;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_5_bits_uop_is_fencei = fast_wakeup_2_bits_uop_is_fencei;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_5_bits_uop_is_fencei = fast_wakeup_2_bits_uop_is_fencei;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_5_bits_uop_is_amo = fast_wakeup_2_bits_uop_is_amo;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_5_bits_uop_is_amo = fast_wakeup_2_bits_uop_is_amo;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_5_bits_uop_uses_ldq = fast_wakeup_2_bits_uop_uses_ldq;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_5_bits_uop_uses_ldq = fast_wakeup_2_bits_uop_uses_ldq;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_5_bits_uop_uses_stq = fast_wakeup_2_bits_uop_uses_stq;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_5_bits_uop_uses_stq = fast_wakeup_2_bits_uop_uses_stq;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_5_bits_uop_is_sys_pc2epc = fast_wakeup_2_bits_uop_is_sys_pc2epc;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_5_bits_uop_is_sys_pc2epc = fast_wakeup_2_bits_uop_is_sys_pc2epc;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_5_bits_uop_is_unique = fast_wakeup_2_bits_uop_is_unique;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_5_bits_uop_is_unique = fast_wakeup_2_bits_uop_is_unique;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_5_bits_uop_flush_on_commit = fast_wakeup_2_bits_uop_flush_on_commit;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_5_bits_uop_flush_on_commit = fast_wakeup_2_bits_uop_flush_on_commit;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_5_bits_uop_ldst_is_rs1 = fast_wakeup_2_bits_uop_ldst_is_rs1;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_5_bits_uop_ldst_is_rs1 = fast_wakeup_2_bits_uop_ldst_is_rs1;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_5_bits_uop_ldst = fast_wakeup_2_bits_uop_ldst;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_5_bits_uop_ldst = fast_wakeup_2_bits_uop_ldst;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_5_bits_uop_lrs1 = fast_wakeup_2_bits_uop_lrs1;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_5_bits_uop_lrs1 = fast_wakeup_2_bits_uop_lrs1;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_5_bits_uop_lrs2 = fast_wakeup_2_bits_uop_lrs2;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_5_bits_uop_lrs2 = fast_wakeup_2_bits_uop_lrs2;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_5_bits_uop_lrs3 = fast_wakeup_2_bits_uop_lrs3;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_5_bits_uop_lrs3 = fast_wakeup_2_bits_uop_lrs3;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_5_bits_uop_ldst_val = fast_wakeup_2_bits_uop_ldst_val;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_5_bits_uop_ldst_val = fast_wakeup_2_bits_uop_ldst_val;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_5_bits_uop_dst_rtype = fast_wakeup_2_bits_uop_dst_rtype;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_5_bits_uop_dst_rtype = fast_wakeup_2_bits_uop_dst_rtype;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_5_bits_uop_lrs1_rtype = fast_wakeup_2_bits_uop_lrs1_rtype;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_5_bits_uop_lrs1_rtype = fast_wakeup_2_bits_uop_lrs1_rtype;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_5_bits_uop_lrs2_rtype = fast_wakeup_2_bits_uop_lrs2_rtype;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_5_bits_uop_lrs2_rtype = fast_wakeup_2_bits_uop_lrs2_rtype;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_5_bits_uop_frs3_en = fast_wakeup_2_bits_uop_frs3_en;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_5_bits_uop_frs3_en = fast_wakeup_2_bits_uop_frs3_en;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_5_bits_uop_fp_val = fast_wakeup_2_bits_uop_fp_val;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_5_bits_uop_fp_val = fast_wakeup_2_bits_uop_fp_val;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_5_bits_uop_fp_single = fast_wakeup_2_bits_uop_fp_single;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_5_bits_uop_fp_single = fast_wakeup_2_bits_uop_fp_single;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_5_bits_uop_xcpt_pf_if = fast_wakeup_2_bits_uop_xcpt_pf_if;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_5_bits_uop_xcpt_pf_if = fast_wakeup_2_bits_uop_xcpt_pf_if;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_5_bits_uop_xcpt_ae_if = fast_wakeup_2_bits_uop_xcpt_ae_if;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_5_bits_uop_xcpt_ae_if = fast_wakeup_2_bits_uop_xcpt_ae_if;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_5_bits_uop_xcpt_ma_if = fast_wakeup_2_bits_uop_xcpt_ma_if;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_5_bits_uop_xcpt_ma_if = fast_wakeup_2_bits_uop_xcpt_ma_if;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_5_bits_uop_bp_debug_if = fast_wakeup_2_bits_uop_bp_debug_if;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_5_bits_uop_bp_debug_if = fast_wakeup_2_bits_uop_bp_debug_if;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_5_bits_uop_bp_xcpt_if = fast_wakeup_2_bits_uop_bp_xcpt_if;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_5_bits_uop_bp_xcpt_if = fast_wakeup_2_bits_uop_bp_xcpt_if;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_5_bits_uop_debug_fsrc = fast_wakeup_2_bits_uop_debug_fsrc;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_5_bits_uop_debug_fsrc = fast_wakeup_2_bits_uop_debug_fsrc;\t// @[core.scala:148:30, :814:29]\n assign int_iss_wakeups_5_bits_uop_debug_tsrc = fast_wakeup_2_bits_uop_debug_tsrc;\t// @[core.scala:147:30, :814:29]\n assign int_ren_wakeups_5_bits_uop_debug_tsrc = fast_wakeup_2_bits_uop_debug_tsrc;\t// @[core.scala:148:30, :814:29]\n wire _slow_wakeup_valid_T_17;\t// @[core.scala:834:59]\n assign int_iss_wakeups_6_valid = slow_wakeup_2_valid;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_6_valid = slow_wakeup_2_valid;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_6_bits_uop_uopc = slow_wakeup_2_bits_uop_uopc;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_6_bits_uop_uopc = slow_wakeup_2_bits_uop_uopc;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_6_bits_uop_inst = slow_wakeup_2_bits_uop_inst;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_6_bits_uop_inst = slow_wakeup_2_bits_uop_inst;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_6_bits_uop_debug_inst = slow_wakeup_2_bits_uop_debug_inst;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_6_bits_uop_debug_inst = slow_wakeup_2_bits_uop_debug_inst;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_6_bits_uop_is_rvc = slow_wakeup_2_bits_uop_is_rvc;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_6_bits_uop_is_rvc = slow_wakeup_2_bits_uop_is_rvc;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_6_bits_uop_debug_pc = slow_wakeup_2_bits_uop_debug_pc;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_6_bits_uop_debug_pc = slow_wakeup_2_bits_uop_debug_pc;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_6_bits_uop_iq_type = slow_wakeup_2_bits_uop_iq_type;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_6_bits_uop_iq_type = slow_wakeup_2_bits_uop_iq_type;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_6_bits_uop_fu_code = slow_wakeup_2_bits_uop_fu_code;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_6_bits_uop_fu_code = slow_wakeup_2_bits_uop_fu_code;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_6_bits_uop_ctrl_br_type = slow_wakeup_2_bits_uop_ctrl_br_type;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_6_bits_uop_ctrl_br_type = slow_wakeup_2_bits_uop_ctrl_br_type;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_6_bits_uop_ctrl_op1_sel = slow_wakeup_2_bits_uop_ctrl_op1_sel;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_6_bits_uop_ctrl_op1_sel = slow_wakeup_2_bits_uop_ctrl_op1_sel;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_6_bits_uop_ctrl_op2_sel = slow_wakeup_2_bits_uop_ctrl_op2_sel;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_6_bits_uop_ctrl_op2_sel = slow_wakeup_2_bits_uop_ctrl_op2_sel;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_6_bits_uop_ctrl_imm_sel = slow_wakeup_2_bits_uop_ctrl_imm_sel;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_6_bits_uop_ctrl_imm_sel = slow_wakeup_2_bits_uop_ctrl_imm_sel;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_6_bits_uop_ctrl_op_fcn = slow_wakeup_2_bits_uop_ctrl_op_fcn;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_6_bits_uop_ctrl_op_fcn = slow_wakeup_2_bits_uop_ctrl_op_fcn;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_6_bits_uop_ctrl_fcn_dw = slow_wakeup_2_bits_uop_ctrl_fcn_dw;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_6_bits_uop_ctrl_fcn_dw = slow_wakeup_2_bits_uop_ctrl_fcn_dw;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_6_bits_uop_ctrl_csr_cmd = slow_wakeup_2_bits_uop_ctrl_csr_cmd;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_6_bits_uop_ctrl_csr_cmd = slow_wakeup_2_bits_uop_ctrl_csr_cmd;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_6_bits_uop_ctrl_is_load = slow_wakeup_2_bits_uop_ctrl_is_load;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_6_bits_uop_ctrl_is_load = slow_wakeup_2_bits_uop_ctrl_is_load;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_6_bits_uop_ctrl_is_sta = slow_wakeup_2_bits_uop_ctrl_is_sta;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_6_bits_uop_ctrl_is_sta = slow_wakeup_2_bits_uop_ctrl_is_sta;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_6_bits_uop_ctrl_is_std = slow_wakeup_2_bits_uop_ctrl_is_std;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_6_bits_uop_ctrl_is_std = slow_wakeup_2_bits_uop_ctrl_is_std;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_6_bits_uop_iw_state = slow_wakeup_2_bits_uop_iw_state;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_6_bits_uop_iw_state = slow_wakeup_2_bits_uop_iw_state;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_6_bits_uop_iw_p1_poisoned = slow_wakeup_2_bits_uop_iw_p1_poisoned;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_6_bits_uop_iw_p1_poisoned = slow_wakeup_2_bits_uop_iw_p1_poisoned;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_6_bits_uop_iw_p2_poisoned = slow_wakeup_2_bits_uop_iw_p2_poisoned;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_6_bits_uop_iw_p2_poisoned = slow_wakeup_2_bits_uop_iw_p2_poisoned;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_6_bits_uop_is_br = slow_wakeup_2_bits_uop_is_br;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_6_bits_uop_is_br = slow_wakeup_2_bits_uop_is_br;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_6_bits_uop_is_jalr = slow_wakeup_2_bits_uop_is_jalr;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_6_bits_uop_is_jalr = slow_wakeup_2_bits_uop_is_jalr;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_6_bits_uop_is_jal = slow_wakeup_2_bits_uop_is_jal;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_6_bits_uop_is_jal = slow_wakeup_2_bits_uop_is_jal;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_6_bits_uop_is_sfb = slow_wakeup_2_bits_uop_is_sfb;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_6_bits_uop_is_sfb = slow_wakeup_2_bits_uop_is_sfb;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_6_bits_uop_br_mask = slow_wakeup_2_bits_uop_br_mask;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_6_bits_uop_br_mask = slow_wakeup_2_bits_uop_br_mask;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_6_bits_uop_br_tag = slow_wakeup_2_bits_uop_br_tag;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_6_bits_uop_br_tag = slow_wakeup_2_bits_uop_br_tag;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_6_bits_uop_ftq_idx = slow_wakeup_2_bits_uop_ftq_idx;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_6_bits_uop_ftq_idx = slow_wakeup_2_bits_uop_ftq_idx;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_6_bits_uop_edge_inst = slow_wakeup_2_bits_uop_edge_inst;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_6_bits_uop_edge_inst = slow_wakeup_2_bits_uop_edge_inst;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_6_bits_uop_pc_lob = slow_wakeup_2_bits_uop_pc_lob;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_6_bits_uop_pc_lob = slow_wakeup_2_bits_uop_pc_lob;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_6_bits_uop_taken = slow_wakeup_2_bits_uop_taken;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_6_bits_uop_taken = slow_wakeup_2_bits_uop_taken;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_6_bits_uop_imm_packed = slow_wakeup_2_bits_uop_imm_packed;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_6_bits_uop_imm_packed = slow_wakeup_2_bits_uop_imm_packed;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_6_bits_uop_csr_addr = slow_wakeup_2_bits_uop_csr_addr;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_6_bits_uop_csr_addr = slow_wakeup_2_bits_uop_csr_addr;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_6_bits_uop_rob_idx = slow_wakeup_2_bits_uop_rob_idx;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_6_bits_uop_rob_idx = slow_wakeup_2_bits_uop_rob_idx;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_6_bits_uop_ldq_idx = slow_wakeup_2_bits_uop_ldq_idx;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_6_bits_uop_ldq_idx = slow_wakeup_2_bits_uop_ldq_idx;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_6_bits_uop_stq_idx = slow_wakeup_2_bits_uop_stq_idx;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_6_bits_uop_stq_idx = slow_wakeup_2_bits_uop_stq_idx;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_6_bits_uop_rxq_idx = slow_wakeup_2_bits_uop_rxq_idx;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_6_bits_uop_rxq_idx = slow_wakeup_2_bits_uop_rxq_idx;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_6_bits_uop_pdst = slow_wakeup_2_bits_uop_pdst;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_6_bits_uop_pdst = slow_wakeup_2_bits_uop_pdst;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_6_bits_uop_prs1 = slow_wakeup_2_bits_uop_prs1;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_6_bits_uop_prs1 = slow_wakeup_2_bits_uop_prs1;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_6_bits_uop_prs2 = slow_wakeup_2_bits_uop_prs2;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_6_bits_uop_prs2 = slow_wakeup_2_bits_uop_prs2;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_6_bits_uop_prs3 = slow_wakeup_2_bits_uop_prs3;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_6_bits_uop_prs3 = slow_wakeup_2_bits_uop_prs3;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_6_bits_uop_ppred = slow_wakeup_2_bits_uop_ppred;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_6_bits_uop_ppred = slow_wakeup_2_bits_uop_ppred;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_6_bits_uop_prs1_busy = slow_wakeup_2_bits_uop_prs1_busy;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_6_bits_uop_prs1_busy = slow_wakeup_2_bits_uop_prs1_busy;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_6_bits_uop_prs2_busy = slow_wakeup_2_bits_uop_prs2_busy;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_6_bits_uop_prs2_busy = slow_wakeup_2_bits_uop_prs2_busy;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_6_bits_uop_prs3_busy = slow_wakeup_2_bits_uop_prs3_busy;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_6_bits_uop_prs3_busy = slow_wakeup_2_bits_uop_prs3_busy;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_6_bits_uop_ppred_busy = slow_wakeup_2_bits_uop_ppred_busy;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_6_bits_uop_ppred_busy = slow_wakeup_2_bits_uop_ppred_busy;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_6_bits_uop_stale_pdst = slow_wakeup_2_bits_uop_stale_pdst;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_6_bits_uop_stale_pdst = slow_wakeup_2_bits_uop_stale_pdst;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_6_bits_uop_exception = slow_wakeup_2_bits_uop_exception;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_6_bits_uop_exception = slow_wakeup_2_bits_uop_exception;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_6_bits_uop_exc_cause = slow_wakeup_2_bits_uop_exc_cause;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_6_bits_uop_exc_cause = slow_wakeup_2_bits_uop_exc_cause;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_6_bits_uop_bypassable = slow_wakeup_2_bits_uop_bypassable;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_6_bits_uop_bypassable = slow_wakeup_2_bits_uop_bypassable;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_6_bits_uop_mem_cmd = slow_wakeup_2_bits_uop_mem_cmd;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_6_bits_uop_mem_cmd = slow_wakeup_2_bits_uop_mem_cmd;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_6_bits_uop_mem_size = slow_wakeup_2_bits_uop_mem_size;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_6_bits_uop_mem_size = slow_wakeup_2_bits_uop_mem_size;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_6_bits_uop_mem_signed = slow_wakeup_2_bits_uop_mem_signed;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_6_bits_uop_mem_signed = slow_wakeup_2_bits_uop_mem_signed;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_6_bits_uop_is_fence = slow_wakeup_2_bits_uop_is_fence;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_6_bits_uop_is_fence = slow_wakeup_2_bits_uop_is_fence;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_6_bits_uop_is_fencei = slow_wakeup_2_bits_uop_is_fencei;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_6_bits_uop_is_fencei = slow_wakeup_2_bits_uop_is_fencei;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_6_bits_uop_is_amo = slow_wakeup_2_bits_uop_is_amo;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_6_bits_uop_is_amo = slow_wakeup_2_bits_uop_is_amo;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_6_bits_uop_uses_ldq = slow_wakeup_2_bits_uop_uses_ldq;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_6_bits_uop_uses_ldq = slow_wakeup_2_bits_uop_uses_ldq;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_6_bits_uop_uses_stq = slow_wakeup_2_bits_uop_uses_stq;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_6_bits_uop_uses_stq = slow_wakeup_2_bits_uop_uses_stq;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_6_bits_uop_is_sys_pc2epc = slow_wakeup_2_bits_uop_is_sys_pc2epc;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_6_bits_uop_is_sys_pc2epc = slow_wakeup_2_bits_uop_is_sys_pc2epc;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_6_bits_uop_is_unique = slow_wakeup_2_bits_uop_is_unique;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_6_bits_uop_is_unique = slow_wakeup_2_bits_uop_is_unique;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_6_bits_uop_flush_on_commit = slow_wakeup_2_bits_uop_flush_on_commit;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_6_bits_uop_flush_on_commit = slow_wakeup_2_bits_uop_flush_on_commit;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_6_bits_uop_ldst_is_rs1 = slow_wakeup_2_bits_uop_ldst_is_rs1;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_6_bits_uop_ldst_is_rs1 = slow_wakeup_2_bits_uop_ldst_is_rs1;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_6_bits_uop_ldst = slow_wakeup_2_bits_uop_ldst;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_6_bits_uop_ldst = slow_wakeup_2_bits_uop_ldst;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_6_bits_uop_lrs1 = slow_wakeup_2_bits_uop_lrs1;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_6_bits_uop_lrs1 = slow_wakeup_2_bits_uop_lrs1;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_6_bits_uop_lrs2 = slow_wakeup_2_bits_uop_lrs2;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_6_bits_uop_lrs2 = slow_wakeup_2_bits_uop_lrs2;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_6_bits_uop_lrs3 = slow_wakeup_2_bits_uop_lrs3;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_6_bits_uop_lrs3 = slow_wakeup_2_bits_uop_lrs3;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_6_bits_uop_ldst_val = slow_wakeup_2_bits_uop_ldst_val;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_6_bits_uop_ldst_val = slow_wakeup_2_bits_uop_ldst_val;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_6_bits_uop_dst_rtype = slow_wakeup_2_bits_uop_dst_rtype;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_6_bits_uop_dst_rtype = slow_wakeup_2_bits_uop_dst_rtype;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_6_bits_uop_lrs1_rtype = slow_wakeup_2_bits_uop_lrs1_rtype;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_6_bits_uop_lrs1_rtype = slow_wakeup_2_bits_uop_lrs1_rtype;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_6_bits_uop_lrs2_rtype = slow_wakeup_2_bits_uop_lrs2_rtype;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_6_bits_uop_lrs2_rtype = slow_wakeup_2_bits_uop_lrs2_rtype;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_6_bits_uop_frs3_en = slow_wakeup_2_bits_uop_frs3_en;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_6_bits_uop_frs3_en = slow_wakeup_2_bits_uop_frs3_en;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_6_bits_uop_fp_val = slow_wakeup_2_bits_uop_fp_val;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_6_bits_uop_fp_val = slow_wakeup_2_bits_uop_fp_val;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_6_bits_uop_fp_single = slow_wakeup_2_bits_uop_fp_single;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_6_bits_uop_fp_single = slow_wakeup_2_bits_uop_fp_single;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_6_bits_uop_xcpt_pf_if = slow_wakeup_2_bits_uop_xcpt_pf_if;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_6_bits_uop_xcpt_pf_if = slow_wakeup_2_bits_uop_xcpt_pf_if;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_6_bits_uop_xcpt_ae_if = slow_wakeup_2_bits_uop_xcpt_ae_if;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_6_bits_uop_xcpt_ae_if = slow_wakeup_2_bits_uop_xcpt_ae_if;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_6_bits_uop_xcpt_ma_if = slow_wakeup_2_bits_uop_xcpt_ma_if;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_6_bits_uop_xcpt_ma_if = slow_wakeup_2_bits_uop_xcpt_ma_if;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_6_bits_uop_bp_debug_if = slow_wakeup_2_bits_uop_bp_debug_if;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_6_bits_uop_bp_debug_if = slow_wakeup_2_bits_uop_bp_debug_if;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_6_bits_uop_bp_xcpt_if = slow_wakeup_2_bits_uop_bp_xcpt_if;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_6_bits_uop_bp_xcpt_if = slow_wakeup_2_bits_uop_bp_xcpt_if;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_6_bits_uop_debug_fsrc = slow_wakeup_2_bits_uop_debug_fsrc;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_6_bits_uop_debug_fsrc = slow_wakeup_2_bits_uop_debug_fsrc;\t// @[core.scala:148:30, :815:29]\n assign int_iss_wakeups_6_bits_uop_debug_tsrc = slow_wakeup_2_bits_uop_debug_tsrc;\t// @[core.scala:147:30, :815:29]\n assign int_ren_wakeups_6_bits_uop_debug_tsrc = slow_wakeup_2_bits_uop_debug_tsrc;\t// @[core.scala:148:30, :815:29]\n wire _T_149 = _alu_exe_unit_2_io_iresp_bits_uop_dst_rtype != 2'h2;\t// @[execution-units.scala:119:32]\n wire _slow_wakeup_valid_T_12;\t// @[micro-op.scala:149:36]\n assign _slow_wakeup_valid_T_12 = _T_149;\t// @[micro-op.scala:149:36]\n wire _iregfile_io_write_ports_3_valid_T;\t// @[micro-op.scala:149:36]\n assign _iregfile_io_write_ports_3_valid_T = _T_149;\t// @[micro-op.scala:149:36]\n wire _rob_io_debug_wb_valids_3_T;\t// @[micro-op.scala:149:36]\n assign _rob_io_debug_wb_valids_3_T = _T_149;\t// @[micro-op.scala:149:36]\n wire _fast_wakeup_valid_T_16 = iss_valids_3 & iss_uops_3_bypassable;\t// @[core.scala:172:24, :173:24, :824:45]\n wire _fast_wakeup_valid_T_17 = iss_uops_3_dst_rtype == 2'h0;\t// @[core.scala:173:24, :826:53]\n wire _fast_wakeup_valid_T_18 = _fast_wakeup_valid_T_16 & _fast_wakeup_valid_T_17;\t// @[core.scala:824:45, :825:54, :826:53]\n wire _fast_wakeup_valid_T_19 = _fast_wakeup_valid_T_18 & iss_uops_3_ldst_val;\t// @[core.scala:173:24, :825:54, :826:64]\n wire _GEN_41 = iss_uops_3_iw_p1_poisoned | iss_uops_3_iw_p2_poisoned;\t// @[core.scala:173:24, :828:79]\n wire _fast_wakeup_valid_T_20;\t// @[core.scala:828:79]\n assign _fast_wakeup_valid_T_20 = _GEN_41;\t// @[core.scala:828:79]\n wire _iregister_read_io_iss_valids_3_T;\t// @[core.scala:981:72]\n assign _iregister_read_io_iss_valids_3_T = _GEN_41;\t// @[core.scala:828:79, :981:72]\n wire _fast_wakeup_valid_T_21 = io_lsu_ld_miss_0 & _fast_wakeup_valid_T_20;\t// @[core.scala:51:7, :828:{48,79}]\n wire _fast_wakeup_valid_T_22 = ~_fast_wakeup_valid_T_21;\t// @[core.scala:828:{31,48}]\n assign _fast_wakeup_valid_T_23 = _fast_wakeup_valid_T_19 & _fast_wakeup_valid_T_22;\t// @[core.scala:826:64, :827:52, :828:31]\n assign fast_wakeup_2_valid = _fast_wakeup_valid_T_23;\t// @[core.scala:814:29, :827:52]\n wire _slow_wakeup_valid_T_13 = _alu_exe_unit_2_io_iresp_valid & _slow_wakeup_valid_T_12;\t// @[execution-units.scala:119:32]\n wire _slow_wakeup_valid_T_14 = ~_alu_exe_unit_2_io_iresp_bits_uop_bypassable;\t// @[execution-units.scala:119:32]\n wire _slow_wakeup_valid_T_15 = _slow_wakeup_valid_T_13 & _slow_wakeup_valid_T_14;\t// @[core.scala:832:42, :833:54, :834:33]\n wire _T_143 = _alu_exe_unit_2_io_iresp_bits_uop_dst_rtype == 2'h0;\t// @[execution-units.scala:119:32]\n wire _slow_wakeup_valid_T_16;\t// @[core.scala:835:57]\n assign _slow_wakeup_valid_T_16 = _T_143;\t// @[core.scala:835:57]\n wire _iregfile_io_write_ports_3_valid_T_2;\t// @[core.scala:1160:77]\n assign _iregfile_io_write_ports_3_valid_T_2 = _T_143;\t// @[core.scala:835:57, :1160:77]\n wire _rob_io_debug_wb_valids_3_T_2;\t// @[core.scala:1240:86]\n assign _rob_io_debug_wb_valids_3_T_2 = _T_143;\t// @[core.scala:835:57, :1240:86]\n assign _slow_wakeup_valid_T_17 = _slow_wakeup_valid_T_15 & _slow_wakeup_valid_T_16;\t// @[core.scala:833:54, :834:59, :835:57]\n assign slow_wakeup_2_valid = _slow_wakeup_valid_T_17;\t// @[core.scala:815:29, :834:59]\n wire _pred_wakeup_valid_T = iss_uops_1_is_br & iss_uops_1_is_sfb;\t// @[core.scala:173:24]\n wire _pred_wakeup_valid_T_4 = io_lsu_ld_miss_0 & _pred_wakeup_valid_T_3;\t// @[core.scala:51:7, :864:{42,84}]\n wire _pred_wakeup_valid_T_5 = ~_pred_wakeup_valid_T_4;\t// @[core.scala:864:{25,42}]\n wire loads_saturating = _mem_issue_unit_io_iss_valids_0 & _mem_issue_unit_io_iss_uops_0_uses_ldq;\t// @[core.scala:108:32, :908:57]\n reg [4:0] saturating_loads_counter;\t// @[core.scala:909:41]\n wire [5:0] _saturating_loads_counter_T = {1'h0, saturating_loads_counter} + 6'h1;\t// @[core.scala:909:41, :910:82]\n wire [4:0] _saturating_loads_counter_T_1 = _saturating_loads_counter_T[4:0];\t// @[core.scala:910:82]\n reg pause_mem_REG;\t// @[core.scala:912:26]\n wire _pause_mem_T_1 = &saturating_loads_counter;\t// @[core.scala:909:41, :912:73]\n wire pause_mem = pause_mem_REG & _pause_mem_T_1;\t// @[core.scala:912:{26,45,73}]\n wire [9:0] _mem_issue_unit_io_fu_types_0_T = {7'h0, ~pause_mem, 2'h0};\t// @[core.scala:912:45, :931:53]\n wire [9:0] _idiv_issued_T = iss_uops_1_fu_code & 10'h10;\t// @[core.scala:173:24]\n wire _idiv_issued_T_1 = |_idiv_issued_T;\t// @[micro-op.scala:154:{40,47}]\n wire idiv_issued = iss_valids_1 & _idiv_issued_T_1;\t// @[core.scala:172:24, :924:47]\n reg [9:0] REG_4;\t// @[core.scala:925:38]\n wire [9:0] _idiv_issued_T_2 = iss_uops_3_fu_code & 10'h10;\t// @[core.scala:173:24]\n wire _idiv_issued_T_3 = |_idiv_issued_T_2;\t// @[micro-op.scala:154:{40,47}]\n wire idiv_issued_1 = iss_valids_3 & _idiv_issued_T_3;\t// @[core.scala:172:24, :924:47]\n reg [9:0] REG_5;\t// @[core.scala:925:38]\n reg mem_issue_unit_io_flush_pipeline_REG;\t// @[core.scala:946:49]\n reg int_issue_unit_io_flush_pipeline_REG;\t// @[core.scala:946:49]\n reg memExeUnit_io_com_exception_REG;\t// @[core.scala:952:51]\n wire _GEN_42 = int_iss_wakeups_0_bits_uop_iw_p1_poisoned | int_iss_wakeups_0_bits_uop_iw_p2_poisoned;\t// @[core.scala:147:30, :961:61]\n wire _mem_issue_unit_io_wakeup_ports_0_bits_poisoned_T;\t// @[core.scala:961:61]\n assign _mem_issue_unit_io_wakeup_ports_0_bits_poisoned_T = _GEN_42;\t// @[core.scala:961:61]\n wire _int_issue_unit_io_wakeup_ports_0_bits_poisoned_T;\t// @[core.scala:961:61]\n assign _int_issue_unit_io_wakeup_ports_0_bits_poisoned_T = _GEN_42;\t// @[core.scala:961:61]\n wire _GEN_43 = int_iss_wakeups_1_bits_uop_iw_p1_poisoned | int_iss_wakeups_1_bits_uop_iw_p2_poisoned;\t// @[core.scala:147:30, :961:61]\n wire _mem_issue_unit_io_wakeup_ports_1_bits_poisoned_T;\t// @[core.scala:961:61]\n assign _mem_issue_unit_io_wakeup_ports_1_bits_poisoned_T = _GEN_43;\t// @[core.scala:961:61]\n wire _int_issue_unit_io_wakeup_ports_1_bits_poisoned_T;\t// @[core.scala:961:61]\n assign _int_issue_unit_io_wakeup_ports_1_bits_poisoned_T = _GEN_43;\t// @[core.scala:961:61]\n wire _GEN_44 = int_iss_wakeups_2_bits_uop_iw_p1_poisoned | int_iss_wakeups_2_bits_uop_iw_p2_poisoned;\t// @[core.scala:147:30, :961:61]\n wire _mem_issue_unit_io_wakeup_ports_2_bits_poisoned_T;\t// @[core.scala:961:61]\n assign _mem_issue_unit_io_wakeup_ports_2_bits_poisoned_T = _GEN_44;\t// @[core.scala:961:61]\n wire _int_issue_unit_io_wakeup_ports_2_bits_poisoned_T;\t// @[core.scala:961:61]\n assign _int_issue_unit_io_wakeup_ports_2_bits_poisoned_T = _GEN_44;\t// @[core.scala:961:61]\n wire _GEN_45 = int_iss_wakeups_3_bits_uop_iw_p1_poisoned | int_iss_wakeups_3_bits_uop_iw_p2_poisoned;\t// @[core.scala:147:30, :961:61]\n wire _mem_issue_unit_io_wakeup_ports_3_bits_poisoned_T;\t// @[core.scala:961:61]\n assign _mem_issue_unit_io_wakeup_ports_3_bits_poisoned_T = _GEN_45;\t// @[core.scala:961:61]\n wire _int_issue_unit_io_wakeup_ports_3_bits_poisoned_T;\t// @[core.scala:961:61]\n assign _int_issue_unit_io_wakeup_ports_3_bits_poisoned_T = _GEN_45;\t// @[core.scala:961:61]\n wire _GEN_46 = int_iss_wakeups_4_bits_uop_iw_p1_poisoned | int_iss_wakeups_4_bits_uop_iw_p2_poisoned;\t// @[core.scala:147:30, :961:61]\n wire _mem_issue_unit_io_wakeup_ports_4_bits_poisoned_T;\t// @[core.scala:961:61]\n assign _mem_issue_unit_io_wakeup_ports_4_bits_poisoned_T = _GEN_46;\t// @[core.scala:961:61]\n wire _int_issue_unit_io_wakeup_ports_4_bits_poisoned_T;\t// @[core.scala:961:61]\n assign _int_issue_unit_io_wakeup_ports_4_bits_poisoned_T = _GEN_46;\t// @[core.scala:961:61]\n wire _GEN_47 = int_iss_wakeups_5_bits_uop_iw_p1_poisoned | int_iss_wakeups_5_bits_uop_iw_p2_poisoned;\t// @[core.scala:147:30, :961:61]\n wire _mem_issue_unit_io_wakeup_ports_5_bits_poisoned_T;\t// @[core.scala:961:61]\n assign _mem_issue_unit_io_wakeup_ports_5_bits_poisoned_T = _GEN_47;\t// @[core.scala:961:61]\n wire _int_issue_unit_io_wakeup_ports_5_bits_poisoned_T;\t// @[core.scala:961:61]\n assign _int_issue_unit_io_wakeup_ports_5_bits_poisoned_T = _GEN_47;\t// @[core.scala:961:61]\n wire _GEN_48 = int_iss_wakeups_6_bits_uop_iw_p1_poisoned | int_iss_wakeups_6_bits_uop_iw_p2_poisoned;\t// @[core.scala:147:30, :961:61]\n wire _mem_issue_unit_io_wakeup_ports_6_bits_poisoned_T;\t// @[core.scala:961:61]\n assign _mem_issue_unit_io_wakeup_ports_6_bits_poisoned_T = _GEN_48;\t// @[core.scala:961:61]\n wire _int_issue_unit_io_wakeup_ports_6_bits_poisoned_T;\t// @[core.scala:961:61]\n assign _int_issue_unit_io_wakeup_ports_6_bits_poisoned_T = _GEN_48;\t// @[core.scala:961:61]\n wire _iregister_read_io_iss_valids_0_T = iss_uops_0_iw_p1_poisoned | iss_uops_0_iw_p2_poisoned;\t// @[core.scala:173:24, :981:72]\n wire _iregister_read_io_iss_valids_0_T_1 = io_lsu_ld_miss_0 & _iregister_read_io_iss_valids_0_T;\t// @[core.scala:51:7, :981:{41,72}]\n wire _iregister_read_io_iss_valids_0_T_2 = ~_iregister_read_io_iss_valids_0_T_1;\t// @[core.scala:981:{24,41}]\n wire _iregister_read_io_iss_valids_0_T_3 = iss_valids_0 & _iregister_read_io_iss_valids_0_T_2;\t// @[core.scala:172:24, :981:{21,24}]\n wire _iregister_read_io_iss_valids_1_T_1 = io_lsu_ld_miss_0 & _iregister_read_io_iss_valids_1_T;\t// @[core.scala:51:7, :981:{41,72}]\n wire _iregister_read_io_iss_valids_1_T_2 = ~_iregister_read_io_iss_valids_1_T_1;\t// @[core.scala:981:{24,41}]\n wire _iregister_read_io_iss_valids_1_T_3 = iss_valids_1 & _iregister_read_io_iss_valids_1_T_2;\t// @[core.scala:172:24, :981:{21,24}]\n wire _iregister_read_io_iss_valids_2_T_1 = io_lsu_ld_miss_0 & _iregister_read_io_iss_valids_2_T;\t// @[core.scala:51:7, :981:{41,72}]\n wire _iregister_read_io_iss_valids_2_T_2 = ~_iregister_read_io_iss_valids_2_T_1;\t// @[core.scala:981:{24,41}]\n wire _iregister_read_io_iss_valids_2_T_3 = iss_valids_2 & _iregister_read_io_iss_valids_2_T_2;\t// @[core.scala:172:24, :981:{21,24}]\n wire _iregister_read_io_iss_valids_3_T_1 = io_lsu_ld_miss_0 & _iregister_read_io_iss_valids_3_T;\t// @[core.scala:51:7, :981:{41,72}]\n wire _iregister_read_io_iss_valids_3_T_2 = ~_iregister_read_io_iss_valids_3_T_1;\t// @[core.scala:981:{24,41}]\n wire _iregister_read_io_iss_valids_3_T_3 = iss_valids_3 & _iregister_read_io_iss_valids_3_T_2;\t// @[core.scala:172:24, :981:{21,24}]\n reg iregister_read_io_kill_REG;\t// @[core.scala:987:38]\n wire [2:0] _csr_io_rw_cmd_T = {~_alu_exe_unit_1_io_iresp_valid, 2'h0};\t// @[CSR.scala:183:15]\n wire [2:0] _csr_io_rw_cmd_T_1 = ~_csr_io_rw_cmd_T;\t// @[CSR.scala:183:{11,15}]\n wire [2:0] _csr_io_rw_cmd_T_2 = _alu_exe_unit_1_io_iresp_bits_uop_ctrl_csr_cmd & _csr_io_rw_cmd_T_1;\t// @[CSR.scala:183:{9,11}]\n wire [2:0] _csr_io_retire_T = {csr_io_retire_hi, _rob_io_commit_arch_valids_0};\t// @[core.scala:143:32, :1015:66]\n wire _csr_io_retire_T_1 = _csr_io_retire_T[0];\t// @[core.scala:1015:{39,66}]\n wire _csr_io_retire_T_2 = _csr_io_retire_T[1];\t// @[core.scala:1015:{39,66}]\n wire _csr_io_retire_T_3 = _csr_io_retire_T[2];\t// @[core.scala:1015:{39,66}]\n wire [1:0] _csr_io_retire_T_4 = {1'h0, _csr_io_retire_T_2} + {1'h0, _csr_io_retire_T_3};\t// @[core.scala:1015:39]\n wire [1:0] _csr_io_retire_T_5 = _csr_io_retire_T_4;\t// @[core.scala:1015:39]\n wire [2:0] _csr_io_retire_T_6 = {2'h0, _csr_io_retire_T_1} + {1'h0, _csr_io_retire_T_5};\t// @[core.scala:1015:39]\n wire [1:0] _csr_io_retire_T_7 = _csr_io_retire_T_6[1:0];\t// @[core.scala:1015:39]\n reg [1:0] csr_io_retire_REG;\t// @[core.scala:1015:30]\n reg csr_io_exception_REG;\t// @[core.scala:1016:30]\n wire [39:0] _csr_io_pc_T = ~io_ifu_get_pc_0_com_pc_0;\t// @[util.scala:237:7]\n wire [39:0] _csr_io_pc_T_1 = {_csr_io_pc_T[39:6], 6'h3F};\t// @[util.scala:237:{7,11}]\n wire [39:0] _csr_io_pc_T_2 = ~_csr_io_pc_T_1;\t// @[util.scala:237:{5,11}]\n reg [5:0] csr_io_pc_REG;\t// @[core.scala:1020:31]\n wire [40:0] _csr_io_pc_T_3 = {1'h0, _csr_io_pc_T_2} + {35'h0, csr_io_pc_REG};\t// @[util.scala:237:5]\n wire [39:0] _csr_io_pc_T_4 = _csr_io_pc_T_3[39:0];\t// @[core.scala:1020:22]\n reg csr_io_pc_REG_1;\t// @[core.scala:1021:35]\n wire [1:0] _csr_io_pc_T_5 = {csr_io_pc_REG_1, 1'h0};\t// @[core.scala:1021:{27,35}]\n wire [40:0] _csr_io_pc_T_6 = {1'h0, _csr_io_pc_T_4} - {39'h0, _csr_io_pc_T_5};\t// @[core.scala:1020:22, :1021:{22,27}]\n wire [39:0] _csr_io_pc_T_7 = _csr_io_pc_T_6[39:0];\t// @[core.scala:1021:22]\n reg [63:0] csr_io_cause_REG;\t// @[core.scala:1023:30]\n wire _tval_valid_T = csr_io_cause_REG == 64'h3;\t// @[package.scala:16:47]\n wire _tval_valid_T_1 = csr_io_cause_REG == 64'h4;\t// @[package.scala:16:47]\n wire _tval_valid_T_2 = csr_io_cause_REG == 64'h6;\t// @[package.scala:16:47]\n wire _tval_valid_T_3 = csr_io_cause_REG == 64'h5;\t// @[package.scala:16:47]\n wire _tval_valid_T_4 = csr_io_cause_REG == 64'h7;\t// @[package.scala:16:47]\n wire _tval_valid_T_5 = csr_io_cause_REG == 64'h1;\t// @[package.scala:16:47]\n wire _tval_valid_T_6 = csr_io_cause_REG == 64'hD;\t// @[package.scala:16:47]\n wire _tval_valid_T_7 = csr_io_cause_REG == 64'hF;\t// @[package.scala:16:47]\n wire _tval_valid_T_8 = csr_io_cause_REG == 64'hC;\t// @[package.scala:16:47]\n wire _tval_valid_T_9 = _tval_valid_T | _tval_valid_T_1;\t// @[package.scala:16:47, :81:59]\n wire _tval_valid_T_10 = _tval_valid_T_9 | _tval_valid_T_2;\t// @[package.scala:16:47, :81:59]\n wire _tval_valid_T_11 = _tval_valid_T_10 | _tval_valid_T_3;\t// @[package.scala:16:47, :81:59]\n wire _tval_valid_T_12 = _tval_valid_T_11 | _tval_valid_T_4;\t// @[package.scala:16:47, :81:59]\n wire _tval_valid_T_13 = _tval_valid_T_12 | _tval_valid_T_5;\t// @[package.scala:16:47, :81:59]\n wire _tval_valid_T_14 = _tval_valid_T_13 | _tval_valid_T_6;\t// @[package.scala:16:47, :81:59]\n wire _tval_valid_T_15 = _tval_valid_T_14 | _tval_valid_T_7;\t// @[package.scala:16:47, :81:59]\n wire _tval_valid_T_16 = _tval_valid_T_15 | _tval_valid_T_8;\t// @[package.scala:16:47, :81:59]\n wire tval_valid = csr_io_exception_REG & _tval_valid_T_16;\t// @[package.scala:81:59]\n wire [63:0] _csr_io_tval_a_T;\t// @[core.scala:1049:18]\n wire [24:0] csr_io_tval_a = _csr_io_tval_a_T[63:39];\t// @[core.scala:1049:{18,25}]\n wire _csr_io_tval_msb_T = csr_io_tval_a == 25'h0;\t// @[core.scala:1049:25, :1050:23]\n wire _csr_io_tval_msb_T_1 = &csr_io_tval_a;\t// @[core.scala:1049:25, :1050:36]\n wire _csr_io_tval_msb_T_2 = _csr_io_tval_msb_T | _csr_io_tval_msb_T_1;\t// @[core.scala:1050:{23,31,36}]\n wire _csr_io_tval_msb_T_3 = _rob_io_com_xcpt_bits_badvaddr[39];\t// @[core.scala:143:32, :1050:48]\n wire _csr_io_tval_msb_T_4 = _rob_io_com_xcpt_bits_badvaddr[38];\t// @[core.scala:143:32, :1050:64]\n wire _csr_io_tval_msb_T_5 = ~_csr_io_tval_msb_T_4;\t// @[core.scala:1050:{61,64}]\n wire csr_io_tval_msb = _csr_io_tval_msb_T_2 ? _csr_io_tval_msb_T_3 : _csr_io_tval_msb_T_5;\t// @[core.scala:1050:{20,31,48,61}]\n wire [38:0] _csr_io_tval_T = _rob_io_com_xcpt_bits_badvaddr[38:0];\t// @[core.scala:143:32, :1051:18]\n wire [39:0] _csr_io_tval_T_1 = {csr_io_tval_msb, _csr_io_tval_T};\t// @[core.scala:1050:20, :1051:{10,18}]\n reg [39:0] csr_io_tval_REG;\t// @[core.scala:1040:12]\n wire [39:0] _csr_io_tval_T_2 = tval_valid ? csr_io_tval_REG : 40'h0;\t// @[core.scala:1026:37, :1039:21, :1040:12]\n assign bypasses_0_bits_data = _alu_exe_unit_io_bypass_0_bits_data[63:0];\t// @[execution-units.scala:119:32]\n assign bypasses_1_bits_data = _alu_exe_unit_1_io_bypass_0_bits_data[63:0];\t// @[execution-units.scala:119:32]\n assign bypasses_2_bits_data = _alu_exe_unit_2_io_bypass_0_bits_data[63:0];\t// @[execution-units.scala:119:32]\n assign bypasses_3_bits_data = _alu_exe_unit_2_io_bypass_1_bits_data[63:0];\t// @[execution-units.scala:119:32]\n assign bypasses_4_bits_data = _alu_exe_unit_2_io_bypass_2_bits_data[63:0];\t// @[execution-units.scala:119:32]\n assign pred_bypasses_0_bits_data = _alu_exe_unit_io_bypass_0_bits_data[0];\t// @[execution-units.scala:119:32]\n reg io_lsu_exception_REG;\t// @[core.scala:1124:30]\n assign io_lsu_exception_0 = io_lsu_exception_REG;\t// @[core.scala:51:7, :1124:30]\n wire _iregfile_io_write_ports_0_wport_valid_T_1;\t// @[regfile.scala:57:35]\n wire [6:0] iregfile_io_write_ports_0_wport_bits_addr;\t// @[regfile.scala:55:22]\n wire [63:0] iregfile_io_write_ports_0_wport_bits_data;\t// @[regfile.scala:55:22]\n wire iregfile_io_write_ports_0_wport_valid;\t// @[regfile.scala:55:22]\n assign _iregfile_io_write_ports_0_wport_valid_T_1 = _ll_wbarb_io_out_valid & _iregfile_io_write_ports_0_wport_valid_T;\t// @[regfile.scala:57:{35,61}]\n assign iregfile_io_write_ports_0_wport_valid = _iregfile_io_write_ports_0_wport_valid_T_1;\t// @[regfile.scala:55:22, :57:35]\n wire wbReadsCSR = |_alu_exe_unit_io_iresp_bits_uop_ctrl_csr_cmd;\t// @[execution-units.scala:119:32]\n wire _iregfile_io_write_ports_1_valid_T_1 = _alu_exe_unit_io_iresp_valid & _iregfile_io_write_ports_1_valid_T;\t// @[execution-units.scala:119:32]\n wire _iregfile_io_write_ports_1_valid_T_3 = _iregfile_io_write_ports_1_valid_T_1 & _iregfile_io_write_ports_1_valid_T_2;\t// @[core.scala:1160:{22,48,77}]\n wire wbReadsCSR_1 = |_alu_exe_unit_1_io_iresp_bits_uop_ctrl_csr_cmd;\t// @[execution-units.scala:119:32]\n wire _iregfile_io_write_ports_2_valid_T_1 = _alu_exe_unit_1_io_iresp_valid & _iregfile_io_write_ports_2_valid_T;\t// @[execution-units.scala:119:32]\n wire _iregfile_io_write_ports_2_valid_T_3 = _iregfile_io_write_ports_2_valid_T_1 & _iregfile_io_write_ports_2_valid_T_2;\t// @[core.scala:1160:{22,48,77}]\n wire [64:0] _GEN_49 = {1'h0, _csr_io_rw_rdata};\t// @[core.scala:271:19, :1167:56]\n wire [64:0] _iregfile_io_write_ports_2_bits_data_T = wbReadsCSR_1 ? _GEN_49 : _alu_exe_unit_1_io_iresp_bits_data;\t// @[execution-units.scala:119:32]\n wire wbReadsCSR_2 = |_alu_exe_unit_2_io_iresp_bits_uop_ctrl_csr_cmd;\t// @[execution-units.scala:119:32]\n wire _iregfile_io_write_ports_3_valid_T_1 = _alu_exe_unit_2_io_iresp_valid & _iregfile_io_write_ports_3_valid_T;\t// @[execution-units.scala:119:32]\n wire _iregfile_io_write_ports_3_valid_T_3 = _iregfile_io_write_ports_3_valid_T_1 & _iregfile_io_write_ports_3_valid_T_2;\t// @[core.scala:1160:{22,48,77}]\n wire _rob_io_wb_resps_0_valid_T = ~_ll_wbarb_io_out_bits_uop_is_amo;\t// @[core.scala:132:32, :1217:78]\n wire _rob_io_wb_resps_0_valid_T_1 = _ll_wbarb_io_out_bits_uop_uses_stq & _rob_io_wb_resps_0_valid_T;\t// @[core.scala:132:32, :1217:{75,78}]\n wire _rob_io_wb_resps_0_valid_T_2 = ~_rob_io_wb_resps_0_valid_T_1;\t// @[core.scala:1217:{57,75}]\n wire _rob_io_wb_resps_0_valid_T_3 = _ll_wbarb_io_out_valid & _rob_io_wb_resps_0_valid_T_2;\t// @[core.scala:132:32, :1217:{54,57}]\n wire _rob_io_debug_wb_valids_0_T = _ll_wbarb_io_out_bits_uop_dst_rtype != 2'h2;\t// @[core.scala:132:32, :1219:74]\n wire _rob_io_debug_wb_valids_0_T_1 = _ll_wbarb_io_out_valid & _rob_io_debug_wb_valids_0_T;\t// @[core.scala:132:32, :1219:{54,74}]\n wire _rob_io_wb_resps_1_valid_T = ~_alu_exe_unit_io_iresp_bits_uop_is_amo;\t// @[execution-units.scala:119:32]\n wire _rob_io_wb_resps_1_valid_T_1 = _alu_exe_unit_io_iresp_bits_uop_uses_stq & _rob_io_wb_resps_1_valid_T;\t// @[execution-units.scala:119:32]\n wire _rob_io_wb_resps_1_valid_T_2 = ~_rob_io_wb_resps_1_valid_T_1;\t// @[core.scala:1238:{51,69}]\n wire _rob_io_wb_resps_1_valid_T_3 = _alu_exe_unit_io_iresp_valid & _rob_io_wb_resps_1_valid_T_2;\t// @[execution-units.scala:119:32]\n wire _rob_io_debug_wb_valids_1_T_1 = _alu_exe_unit_io_iresp_valid & _rob_io_debug_wb_valids_1_T;\t// @[execution-units.scala:119:32]\n wire _rob_io_debug_wb_valids_1_T_3 = _rob_io_debug_wb_valids_1_T_1 & _rob_io_debug_wb_valids_1_T_2;\t// @[core.scala:1240:{49,66,86}]\n wire _rob_io_wb_resps_2_valid_T = ~_alu_exe_unit_1_io_iresp_bits_uop_is_amo;\t// @[execution-units.scala:119:32]\n wire _rob_io_wb_resps_2_valid_T_1 = _alu_exe_unit_1_io_iresp_bits_uop_uses_stq & _rob_io_wb_resps_2_valid_T;\t// @[execution-units.scala:119:32]\n wire _rob_io_wb_resps_2_valid_T_2 = ~_rob_io_wb_resps_2_valid_T_1;\t// @[core.scala:1238:{51,69}]\n wire _rob_io_wb_resps_2_valid_T_3 = _alu_exe_unit_1_io_iresp_valid & _rob_io_wb_resps_2_valid_T_2;\t// @[execution-units.scala:119:32]\n wire _rob_io_debug_wb_valids_2_T_1 = _alu_exe_unit_1_io_iresp_valid & _rob_io_debug_wb_valids_2_T;\t// @[execution-units.scala:119:32]\n wire _rob_io_debug_wb_valids_2_T_3 = _rob_io_debug_wb_valids_2_T_1 & _rob_io_debug_wb_valids_2_T_2;\t// @[core.scala:1240:{49,66,86}]\n wire _rob_io_debug_wb_wdata_2_T = |_alu_exe_unit_1_io_iresp_bits_uop_ctrl_csr_cmd;\t// @[execution-units.scala:119:32]\n wire [64:0] _rob_io_debug_wb_wdata_2_T_1 = _rob_io_debug_wb_wdata_2_T ? _GEN_49 : _alu_exe_unit_1_io_iresp_bits_data;\t// @[execution-units.scala:119:32]\n wire _rob_io_wb_resps_3_valid_T = ~_alu_exe_unit_2_io_iresp_bits_uop_is_amo;\t// @[execution-units.scala:119:32]\n wire _rob_io_wb_resps_3_valid_T_1 = _alu_exe_unit_2_io_iresp_bits_uop_uses_stq & _rob_io_wb_resps_3_valid_T;\t// @[execution-units.scala:119:32]\n wire _rob_io_wb_resps_3_valid_T_2 = ~_rob_io_wb_resps_3_valid_T_1;\t// @[core.scala:1238:{51,69}]\n wire _rob_io_wb_resps_3_valid_T_3 = _alu_exe_unit_2_io_iresp_valid & _rob_io_wb_resps_3_valid_T_2;\t// @[execution-units.scala:119:32]\n wire _rob_io_debug_wb_valids_3_T_1 = _alu_exe_unit_2_io_iresp_valid & _rob_io_debug_wb_valids_3_T;\t// @[execution-units.scala:119:32]\n wire _rob_io_debug_wb_valids_3_T_3 = _rob_io_debug_wb_valids_3_T_1 & _rob_io_debug_wb_valids_3_T_2;\t// @[core.scala:1240:{49,66,86}]\n reg REG_6;\t// @[core.scala:1306:45]\n reg memExeUnit_io_req_bits_kill_REG;\t// @[core.scala:1310:45]\n reg alu_exe_unit_io_req_bits_kill_REG;\t// @[core.scala:1310:45]\n reg alu_exe_unit_io_req_bits_kill_REG_1;\t// @[core.scala:1310:45]\n reg alu_exe_unit_io_req_bits_kill_REG_2;\t// @[core.scala:1310:45]\n reg [4:0] small_0;\t// @[Counters.scala:45:41]\n wire [5:0] nextSmall = {1'h0, small_0} + 6'h1;\t// @[Counters.scala:45:41, :46:33]\n reg [26:0] large_0;\t// @[Counters.scala:50:31]\n wire _large_T = nextSmall[5];\t// @[Counters.scala:46:33, :51:20]\n wire _large_T_2 = _large_T;\t// @[Counters.scala:51:{20,33}]\n wire [27:0] _large_r_T = {1'h0, large_0} + 28'h1;\t// @[Counters.scala:50:31, :51:55]\n wire [26:0] _large_r_T_1 = _large_r_T[26:0];\t// @[Counters.scala:51:55]\n wire [31:0] value = {large_0, small_0};\t// @[Counters.scala:45:41, :50:31, :55:30]\n wire [1:0] hi = {_rob_io_commit_valids_2, _rob_io_commit_valids_1};\t// @[core.scala:143:32, :1324:30]"}}},{"rowIdx":599,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to the following Chisel files.\nFile Monitor.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.tilelink\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.experimental.SourceLine\n\nimport org.chipsalliance.cde.config._\nimport org.chipsalliance.diplomacy._\n\nimport freechips.rocketchip.diplomacy.EnableMonitors\nimport freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}\nimport freechips.rocketchip.util.PlusArg\n\ncase class TLMonitorArgs(edge: TLEdge)\n\nabstract class TLMonitorBase(args: TLMonitorArgs) extends Module\n{\n val io = IO(new Bundle {\n val in = Input(new TLBundle(args.edge.bundle))\n })\n\n def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit\n legalize(io.in, args.edge, reset)\n}\n\nobject TLMonitor {\n def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {\n if (enable) {\n EnableMonitors { implicit p => node := TLEphemeralNode()(ValName(\"monitor\")) }\n } else { node }\n }\n}\n\nclass TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)\n{\n require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))\n\n val cover_prop_class = PropertyClass.Default\n\n //Like assert but can flip to being an assumption for formal verification\n def monAssert(cond: Bool, message: String): Unit =\n if (monitorDir == MonitorDirection.Monitor) {\n assert(cond, message)\n } else {\n Property(monitorDir, cond, message, PropertyClass.Default)\n }\n\n def assume(cond: Bool, message: String): Unit =\n if (monitorDir == MonitorDirection.Monitor) {\n assert(cond, message)\n } else {\n Property(monitorDir.flip, cond, message, PropertyClass.Default)\n }\n\n def extra = {\n args.edge.sourceInfo match {\n case SourceLine(filename, line, col) => s\" (connected at $filename:$line:$col)\"\n case _ => \"\"\n }\n }\n\n def visible(address: UInt, source: UInt, edge: TLEdge) =\n edge.client.clients.map { c =>\n !c.sourceId.contains(source) ||\n c.visibility.map(_.contains(address)).reduce(_ || _)\n }.reduce(_ && _)\n\n def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {\n //switch this flag to turn on diplomacy in error messages\n def diplomacyInfo = if (true) \"\" else \"\\nThe diplomacy information for the edge is as follows:\\n\" + edge.formatEdge + \"\\n\"\n monAssert (TLMessages.isA(bundle.opcode), \"'A' channel has invalid opcode\" + extra)\n\n // Reuse these subexpressions to save some firrtl lines\n val source_ok = edge.client.contains(bundle.source)\n val is_aligned = edge.isAligned(bundle.address, bundle.size)\n val mask = edge.full_mask(bundle)\n\n monAssert (visible(edge.address(bundle), bundle.source, edge), \"'A' channel carries an address illegal for the specified bank visibility\")\n\n //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B\n //TODO: check for acquireT?\n when (bundle.opcode === TLMessages.AcquireBlock) {\n monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters\" + diplomacyInfo + extra)\n monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock from a client which does not support Probe\" + diplomacyInfo + extra)\n monAssert (source_ok, \"'A' channel AcquireBlock carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'A' channel AcquireBlock smaller than a beat\" + extra)\n monAssert (is_aligned, \"'A' channel AcquireBlock address not aligned to size\" + extra)\n monAssert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquireBlock carries invalid grow param\" + extra)\n monAssert (~bundle.mask === 0.U, \"'A' channel AcquireBlock contains invalid mask\" + extra)\n monAssert (!bundle.corrupt, \"'A' channel AcquireBlock is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.AcquirePerm) {\n monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters\" + diplomacyInfo + extra)\n monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm from a client which does not support Probe\" + diplomacyInfo + extra)\n monAssert (source_ok, \"'A' channel AcquirePerm carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'A' channel AcquirePerm smaller than a beat\" + extra)\n monAssert (is_aligned, \"'A' channel AcquirePerm address not aligned to size\" + extra)\n monAssert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquirePerm carries invalid grow param\" + extra)\n monAssert (bundle.param =/= TLPermissions.NtoB, \"'A' channel AcquirePerm requests NtoB\" + extra)\n monAssert (~bundle.mask === 0.U, \"'A' channel AcquirePerm contains invalid mask\" + extra)\n monAssert (!bundle.corrupt, \"'A' channel AcquirePerm is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.Get) {\n monAssert (edge.master.emitsGet(bundle.source, bundle.size), \"'A' channel carries Get type which master claims it can't emit\" + diplomacyInfo + extra)\n monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), \"'A' channel carries Get type which slave claims it can't support\" + diplomacyInfo + extra)\n monAssert (source_ok, \"'A' channel Get carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'A' channel Get carries invalid param\" + extra)\n monAssert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n monAssert (!bundle.corrupt, \"'A' channel Get is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.PutFullData) {\n monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type which is unexpected using diplomatic parameters\" + diplomacyInfo + extra)\n monAssert (source_ok, \"'A' channel PutFull carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'A' channel PutFull carries invalid param\" + extra)\n monAssert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.PutPartialData) {\n monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type which is unexpected using diplomatic parameters\" + extra)\n monAssert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'A' channel PutPartial carries invalid param\" + extra)\n monAssert ((bundle.mask & ~mask) === 0.U, \"'A' channel PutPartial contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.ArithmeticData) {\n monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type which is unexpected using diplomatic parameters\" + extra)\n monAssert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n monAssert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n monAssert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.LogicalData) {\n monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type which is unexpected using diplomatic parameters\" + extra)\n monAssert (source_ok, \"'A' channel Logical carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n monAssert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n monAssert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.Hint) {\n monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type which is unexpected using diplomatic parameters\" + extra)\n monAssert (source_ok, \"'A' channel Hint carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n monAssert (TLHints.isHints(bundle.param), \"'A' channel Hint carries invalid opcode param\" + extra)\n monAssert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n monAssert (!bundle.corrupt, \"'A' channel Hint is corrupt\" + extra)\n }\n }\n\n def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {\n monAssert (TLMessages.isB(bundle.opcode), \"'B' channel has invalid opcode\" + extra)\n\n monAssert (visible(edge.address(bundle), bundle.source, edge), \"'B' channel carries an address illegal for the specified bank visibility\")\n\n // Reuse these subexpressions to save some firrtl lines\n val address_ok = edge.manager.containsSafe(edge.address(bundle))\n val is_aligned = edge.isAligned(bundle.address, bundle.size)\n val mask = edge.full_mask(bundle)\n val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source\n\n when (bundle.opcode === TLMessages.Probe) {\n assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), \"'B' channel carries Probe type which is unexpected using diplomatic parameters\" + extra)\n assume (address_ok, \"'B' channel Probe carries unmanaged address\" + extra)\n assume (legal_source, \"'B' channel Probe carries source that is not first source\" + extra)\n assume (is_aligned, \"'B' channel Probe address not aligned to size\" + extra)\n assume (TLPermissions.isCap(bundle.param), \"'B' channel Probe carries invalid cap param\" + extra)\n assume (bundle.mask === mask, \"'B' channel Probe contains invalid mask\" + extra)\n assume (!bundle.corrupt, \"'B' channel Probe is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.Get) {\n monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), \"'B' channel carries Get type which is unexpected using diplomatic parameters\" + extra)\n monAssert (address_ok, \"'B' channel Get carries unmanaged address\" + extra)\n monAssert (legal_source, \"'B' channel Get carries source that is not first source\" + extra)\n monAssert (is_aligned, \"'B' channel Get address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'B' channel Get carries invalid param\" + extra)\n monAssert (bundle.mask === mask, \"'B' channel Get contains invalid mask\" + extra)\n monAssert (!bundle.corrupt, \"'B' channel Get is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.PutFullData) {\n monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), \"'B' channel carries PutFull type which is unexpected using diplomatic parameters\" + extra)\n monAssert (address_ok, \"'B' channel PutFull carries unmanaged address\" + extra)\n monAssert (legal_source, \"'B' channel PutFull carries source that is not first source\" + extra)\n monAssert (is_aligned, \"'B' channel PutFull address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'B' channel PutFull carries invalid param\" + extra)\n monAssert (bundle.mask === mask, \"'B' channel PutFull contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.PutPartialData) {\n monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), \"'B' channel carries PutPartial type which is unexpected using diplomatic parameters\" + extra)\n monAssert (address_ok, \"'B' channel PutPartial carries unmanaged address\" + extra)\n monAssert (legal_source, \"'B' channel PutPartial carries source that is not first source\" + extra)\n monAssert (is_aligned, \"'B' channel PutPartial address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'B' channel PutPartial carries invalid param\" + extra)\n monAssert ((bundle.mask & ~mask) === 0.U, \"'B' channel PutPartial contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.ArithmeticData) {\n monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), \"'B' channel carries Arithmetic type unsupported by master\" + extra)\n monAssert (address_ok, \"'B' channel Arithmetic carries unmanaged address\" + extra)\n monAssert (legal_source, \"'B' channel Arithmetic carries source that is not first source\" + extra)\n monAssert (is_aligned, \"'B' channel Arithmetic address not aligned to size\" + extra)\n monAssert (TLAtomics.isArithmetic(bundle.param), \"'B' channel Arithmetic carries invalid opcode param\" + extra)\n monAssert (bundle.mask === mask, \"'B' channel Arithmetic contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.LogicalData) {\n monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), \"'B' channel carries Logical type unsupported by client\" + extra)\n monAssert (address_ok, \"'B' channel Logical carries unmanaged address\" + extra)\n monAssert (legal_source, \"'B' channel Logical carries source that is not first source\" + extra)\n monAssert (is_aligned, \"'B' channel Logical address not aligned to size\" + extra)\n monAssert (TLAtomics.isLogical(bundle.param), \"'B' channel Logical carries invalid opcode param\" + extra)\n monAssert (bundle.mask === mask, \"'B' channel Logical contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.Hint) {\n monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), \"'B' channel carries Hint type unsupported by client\" + extra)\n monAssert (address_ok, \"'B' channel Hint carries unmanaged address\" + extra)\n monAssert (legal_source, \"'B' channel Hint carries source that is not first source\" + extra)\n monAssert (is_aligned, \"'B' channel Hint address not aligned to size\" + extra)\n monAssert (bundle.mask === mask, \"'B' channel Hint contains invalid mask\" + extra)\n monAssert (!bundle.corrupt, \"'B' channel Hint is corrupt\" + extra)\n }\n }\n\n def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {\n monAssert (TLMessages.isC(bundle.opcode), \"'C' channel has invalid opcode\" + extra)\n\n val source_ok = edge.client.contains(bundle.source)\n val is_aligned = edge.isAligned(bundle.address, bundle.size)\n val address_ok = edge.manager.containsSafe(edge.address(bundle))\n\n monAssert (visible(edge.address(bundle), bundle.source, edge), \"'C' channel carries an address illegal for the specified bank visibility\")\n\n when (bundle.opcode === TLMessages.ProbeAck) {\n monAssert (address_ok, \"'C' channel ProbeAck carries unmanaged address\" + extra)\n monAssert (source_ok, \"'C' channel ProbeAck carries invalid source ID\" + extra)\n monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'C' channel ProbeAck smaller than a beat\" + extra)\n monAssert (is_aligned, \"'C' channel ProbeAck address not aligned to size\" + extra)\n monAssert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAck carries invalid report param\" + extra)\n monAssert (!bundle.corrupt, \"'C' channel ProbeAck is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.ProbeAckData) {\n monAssert (address_ok, \"'C' channel ProbeAckData carries unmanaged address\" + extra)\n monAssert (source_ok, \"'C' channel ProbeAckData carries invalid source ID\" + extra)\n monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'C' channel ProbeAckData smaller than a beat\" + extra)\n monAssert (is_aligned, \"'C' channel ProbeAckData address not aligned to size\" + extra)\n monAssert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAckData carries invalid report param\" + extra)\n }\n\n when (bundle.opcode === TLMessages.Release) {\n monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries Release type unsupported by manager\" + extra)\n monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), \"'C' channel carries Release from a client which does not support Probe\" + extra)\n monAssert (source_ok, \"'C' channel Release carries invalid source ID\" + extra)\n monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'C' channel Release smaller than a beat\" + extra)\n monAssert (is_aligned, \"'C' channel Release address not aligned to size\" + extra)\n monAssert (TLPermissions.isReport(bundle.param), \"'C' channel Release carries invalid report param\" + extra)\n monAssert (!bundle.corrupt, \"'C' channel Release is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.ReleaseData) {\n monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries ReleaseData type unsupported by manager\" + extra)\n monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), \"'C' channel carries Release from a client which does not support Probe\" + extra)\n monAssert (source_ok, \"'C' channel ReleaseData carries invalid source ID\" + extra)\n monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'C' channel ReleaseData smaller than a beat\" + extra)\n monAssert (is_aligned, \"'C' channel ReleaseData address not aligned to size\" + extra)\n monAssert (TLPermissions.isReport(bundle.param), \"'C' channel ReleaseData carries invalid report param\" + extra)\n }\n\n when (bundle.opcode === TLMessages.AccessAck) {\n monAssert (address_ok, \"'C' channel AccessAck carries unmanaged address\" + extra)\n monAssert (source_ok, \"'C' channel AccessAck carries invalid source ID\" + extra)\n monAssert (is_aligned, \"'C' channel AccessAck address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'C' channel AccessAck carries invalid param\" + extra)\n monAssert (!bundle.corrupt, \"'C' channel AccessAck is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.AccessAckData) {\n monAssert (address_ok, \"'C' channel AccessAckData carries unmanaged address\" + extra)\n monAssert (source_ok, \"'C' channel AccessAckData carries invalid source ID\" + extra)\n monAssert (is_aligned, \"'C' channel AccessAckData address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'C' channel AccessAckData carries invalid param\" + extra)\n }\n\n when (bundle.opcode === TLMessages.HintAck) {\n monAssert (address_ok, \"'C' channel HintAck carries unmanaged address\" + extra)\n monAssert (source_ok, \"'C' channel HintAck carries invalid source ID\" + extra)\n monAssert (is_aligned, \"'C' channel HintAck address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'C' channel HintAck carries invalid param\" + extra)\n monAssert (!bundle.corrupt, \"'C' channel HintAck is corrupt\" + extra)\n }\n }\n\n def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {\n assume (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n\n val source_ok = edge.client.contains(bundle.source)\n val sink_ok = bundle.sink < edge.manager.endSinkId.U\n val deny_put_ok = edge.manager.mayDenyPut.B\n val deny_get_ok = edge.manager.mayDenyGet.B\n\n when (bundle.opcode === TLMessages.ReleaseAck) {\n assume (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'D' channel ReleaseAck smaller than a beat\" + extra)\n assume (bundle.param === 0.U, \"'D' channel ReleaseeAck carries invalid param\" + extra)\n assume (!bundle.corrupt, \"'D' channel ReleaseAck is corrupt\" + extra)\n assume (!bundle.denied, \"'D' channel ReleaseAck is denied\" + extra)\n }\n\n when (bundle.opcode === TLMessages.Grant) {\n assume (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n assume (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'D' channel Grant smaller than a beat\" + extra)\n assume (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n assume (bundle.param =/= TLPermissions.toN, \"'D' channel Grant carries toN param\" + extra)\n assume (!bundle.corrupt, \"'D' channel Grant is corrupt\" + extra)\n assume (deny_put_ok || !bundle.denied, \"'D' channel Grant is denied\" + extra)\n }\n\n when (bundle.opcode === TLMessages.GrantData) {\n assume (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n assume (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'D' channel GrantData smaller than a beat\" + extra)\n assume (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n assume (bundle.param =/= TLPermissions.toN, \"'D' channel GrantData carries toN param\" + extra)\n assume (!bundle.denied || bundle.corrupt, \"'D' channel GrantData is denied but not corrupt\" + extra)\n assume (deny_get_ok || !bundle.denied, \"'D' channel GrantData is denied\" + extra)\n }\n\n when (bundle.opcode === TLMessages.AccessAck) {\n assume (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n // size is ignored\n assume (bundle.param === 0.U, \"'D' channel AccessAck carries invalid param\" + extra)\n assume (!bundle.corrupt, \"'D' channel AccessAck is corrupt\" + extra)\n assume (deny_put_ok || !bundle.denied, \"'D' channel AccessAck is denied\" + extra)\n }\n\n when (bundle.opcode === TLMessages.AccessAckData) {\n assume (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n // size is ignored\n assume (bundle.param === 0.U, \"'D' channel AccessAckData carries invalid param\" + extra)\n assume (!bundle.denied || bundle.corrupt, \"'D' channel AccessAckData is denied but not corrupt\" + extra)\n assume (deny_get_ok || !bundle.denied, \"'D' channel AccessAckData is denied\" + extra)\n }\n\n when (bundle.opcode === TLMessages.HintAck) {\n assume (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n // size is ignored\n assume (bundle.param === 0.U, \"'D' channel HintAck carries invalid param\" + extra)\n assume (!bundle.corrupt, \"'D' channel HintAck is corrupt\" + extra)\n assume (deny_put_ok || !bundle.denied, \"'D' channel HintAck is denied\" + extra)\n }\n }\n\n def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {\n val sink_ok = bundle.sink < edge.manager.endSinkId.U\n monAssert (sink_ok, \"'E' channels carries invalid sink ID\" + extra)\n }\n\n def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {\n when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }\n when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }\n if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {\n when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }\n when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }\n when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }\n } else {\n monAssert (!bundle.b.valid, \"'B' channel valid and not TL-C\" + extra)\n monAssert (!bundle.c.valid, \"'C' channel valid and not TL-C\" + extra)\n monAssert (!bundle.e.valid, \"'E' channel valid and not TL-C\" + extra)\n }\n }\n\n def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {\n val a_first = edge.first(a.bits, a.fire)\n val opcode = Reg(UInt())\n val param = Reg(UInt())\n val size = Reg(UInt())\n val source = Reg(UInt())\n val address = Reg(UInt())\n when (a.valid && !a_first) {\n monAssert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n monAssert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n monAssert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n monAssert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n monAssert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n }\n when (a.fire && a_first) {\n opcode := a.bits.opcode\n param := a.bits.param\n size := a.bits.size\n source := a.bits.source\n address := a.bits.address\n }\n }\n\n def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {\n val b_first = edge.first(b.bits, b.fire)\n val opcode = Reg(UInt())\n val param = Reg(UInt())\n val size = Reg(UInt())\n val source = Reg(UInt())\n val address = Reg(UInt())\n when (b.valid && !b_first) {\n monAssert (b.bits.opcode === opcode, \"'B' channel opcode changed within multibeat operation\" + extra)\n monAssert (b.bits.param === param, \"'B' channel param changed within multibeat operation\" + extra)\n monAssert (b.bits.size === size, \"'B' channel size changed within multibeat operation\" + extra)\n monAssert (b.bits.source === source, \"'B' channel source changed within multibeat operation\" + extra)\n monAssert (b.bits.address=== address,\"'B' channel addresss changed with multibeat operation\" + extra)\n }\n when (b.fire && b_first) {\n opcode := b.bits.opcode\n param := b.bits.param\n size := b.bits.size\n source := b.bits.source\n address := b.bits.address\n }\n }\n\n def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {\n // Symbolic variable\n val sym_source = Wire(UInt(edge.client.endSourceId.W))\n // TODO: Connect sym_source to a fixed value for simulation and to a\n // free wire in formal\n sym_source := 0.U\n\n // Type casting Int to UInt\n val maxSourceId = Wire(UInt(edge.client.endSourceId.W))\n maxSourceId := edge.client.endSourceId.U\n\n // Delayed verison of sym_source\n val sym_source_d = Reg(UInt(edge.client.endSourceId.W))\n sym_source_d := sym_source\n\n // These will be constraints for FV setup\n Property(\n MonitorDirection.Monitor,\n (sym_source === sym_source_d),\n \"sym_source should remain stable\",\n PropertyClass.Default)\n Property(\n MonitorDirection.Monitor,\n (sym_source <= maxSourceId),\n \"sym_source should take legal value\",\n PropertyClass.Default)\n\n val my_resp_pend = RegInit(false.B)\n val my_opcode = Reg(UInt())\n val my_size = Reg(UInt())\n\n val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)\n val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)\n\n val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)\n val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)\n\n val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)\n val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)\n when (my_set_resp_pend) {\n my_resp_pend := true.B\n } .elsewhen (my_clr_resp_pend) {\n my_resp_pend := false.B\n }\n\n when (my_a_first_beat) {\n my_opcode := bundle.a.bits.opcode\n my_size := bundle.a.bits.size\n }\n\n val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)\n val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)\n\n val my_resp_opcode_legal = Wire(Bool())\n when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||\n (my_resp_opcode === TLMessages.LogicalData)) {\n my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)\n } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {\n my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)\n } .otherwise {\n my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)\n }\n\n monAssert (IfThen(my_resp_pend, !my_a_first_beat),\n \"Request message should not be sent with a source ID, for which a response message\" +\n \"is already pending (not received until current cycle) for a prior request message\" +\n \"with the same source ID\" + extra)\n\n assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),\n \"Response message should be accepted with a source ID only if a request message with the\" +\n \"same source ID has been accepted or is being accepted in the current cycle\" + extra)\n assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),\n \"Response message should be sent with a source ID only if a request message with the\" +\n \"same source ID has been accepted or is being sent in the current cycle\" + extra)\n assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),\n \"If d_valid is 1, then d_size should be same as a_size of the corresponding request\" +\n \"message\" + extra)\n assume (IfThen(my_d_first_beat, my_resp_opcode_legal),\n \"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding\" +\n \"request message\" + extra)\n }\n\n def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {\n val c_first = edge.first(c.bits, c.fire)\n val opcode = Reg(UInt())\n val param = Reg(UInt())\n val size = Reg(UInt())\n val source = Reg(UInt())\n val address = Reg(UInt())\n when (c.valid && !c_first) {\n monAssert (c.bits.opcode === opcode, \"'C' channel opcode changed within multibeat operation\" + extra)\n monAssert (c.bits.param === param, \"'C' channel param changed within multibeat operation\" + extra)\n monAssert (c.bits.size === size, \"'C' channel size changed within multibeat operation\" + extra)\n monAssert (c.bits.source === source, \"'C' channel source changed within multibeat operation\" + extra)\n monAssert (c.bits.address=== address,\"'C' channel address changed with multibeat operation\" + extra)\n }\n when (c.fire && c_first) {\n opcode := c.bits.opcode\n param := c.bits.param\n size := c.bits.size\n source := c.bits.source\n address := c.bits.address\n }\n }\n\n def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {\n val d_first = edge.first(d.bits, d.fire)\n val opcode = Reg(UInt())\n val param = Reg(UInt())\n val size = Reg(UInt())\n val source = Reg(UInt())\n val sink = Reg(UInt())\n val denied = Reg(Bool())\n when (d.valid && !d_first) {\n assume (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n assume (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n assume (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n assume (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n assume (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n assume (d.bits.denied === denied, \"'D' channel denied changed with multibeat operation\" + extra)\n }\n when (d.fire && d_first) {\n opcode := d.bits.opcode\n param := d.bits.param\n size := d.bits.size\n source := d.bits.source\n sink := d.bits.sink\n denied := d.bits.denied\n }\n }\n\n def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {\n legalizeMultibeatA(bundle.a, edge)\n legalizeMultibeatD(bundle.d, edge)\n if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {\n legalizeMultibeatB(bundle.b, edge)\n legalizeMultibeatC(bundle.c, edge)\n }\n }\n\n //This is left in for almond which doesn't adhere to the tilelink protocol\n @deprecated(\"Use legalizeADSource instead if possible\",\"\")\n def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {\n val inflight = RegInit(0.U(edge.client.endSourceId.W))\n\n val a_first = edge.first(bundle.a.bits, bundle.a.fire)\n val d_first = edge.first(bundle.d.bits, bundle.d.fire)\n\n val a_set = WireInit(0.U(edge.client.endSourceId.W))\n when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {\n a_set := UIntToOH(bundle.a.bits.source)\n assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n }\n\n val d_clr = WireInit(0.U(edge.client.endSourceId.W))\n val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck\n when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {\n d_clr := UIntToOH(bundle.d.bits.source)\n assume((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n }\n\n if (edge.manager.minLatency > 0) {\n assume(a_set =/= d_clr || !a_set.orR, s\"'A' and 'D' concurrent, despite minlatency > 0\" + extra)\n }\n\n inflight := (inflight | a_set) & ~d_clr\n\n val watchdog = RegInit(0.U(32.W))\n val limit = PlusArg(\"tilelink_timeout\",\n docstring=\"Kill emulation after INT waiting TileLink cycles. Off if 0.\")\n assert (!inflight.orR || limit === 0.U || watchdog < limit, \"TileLink timeout expired\" + extra)\n\n watchdog := watchdog + 1.U\n when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }\n }\n\n def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {\n val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)\n val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything\n val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)\n val log_a_size_bus_size = log2Ceil(a_size_bus_size)\n def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits\n\n val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error\n inflight.suggestName(\"inflight\")\n val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))\n inflight_opcodes.suggestName(\"inflight_opcodes\")\n val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))\n inflight_sizes.suggestName(\"inflight_sizes\")\n\n val a_first = edge.first(bundle.a.bits, bundle.a.fire)\n a_first.suggestName(\"a_first\")\n val d_first = edge.first(bundle.d.bits, bundle.d.fire)\n d_first.suggestName(\"d_first\")\n\n val a_set = WireInit(0.U(edge.client.endSourceId.W))\n val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))\n a_set.suggestName(\"a_set\")\n a_set_wo_ready.suggestName(\"a_set_wo_ready\")\n val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))\n a_opcodes_set.suggestName(\"a_opcodes_set\")\n val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))\n a_sizes_set.suggestName(\"a_sizes_set\")\n\n val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))\n a_opcode_lookup.suggestName(\"a_opcode_lookup\")\n a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U\n\n val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))\n a_size_lookup.suggestName(\"a_size_lookup\")\n a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U\n\n val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))\n val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))\n\n val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))\n a_opcodes_set_interm.suggestName(\"a_opcodes_set_interm\")\n val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))\n a_sizes_set_interm.suggestName(\"a_sizes_set_interm\")\n\n when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {\n a_set_wo_ready := UIntToOH(bundle.a.bits.source)\n }\n\n when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {\n a_set := UIntToOH(bundle.a.bits.source)\n a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U\n a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U\n a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)\n a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)\n monAssert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n }\n\n val d_clr = WireInit(0.U(edge.client.endSourceId.W))\n val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))\n d_clr.suggestName(\"d_clr\")\n d_clr_wo_ready.suggestName(\"d_clr_wo_ready\")\n val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))\n d_opcodes_clr.suggestName(\"d_opcodes_clr\")\n val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))\n d_sizes_clr.suggestName(\"d_sizes_clr\")\n\n val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck\n when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {\n d_clr_wo_ready := UIntToOH(bundle.d.bits.source)\n }\n\n when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {\n d_clr := UIntToOH(bundle.d.bits.source)\n d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)\n d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)\n }\n when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {\n val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)\n assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, \"'D' channel acknowledged for nothing inflight\" + extra)\n\n when (same_cycle_resp) {\n assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||\n (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), \"'D' channel contains improper opcode response\" + extra)\n assume((bundle.a.bits.size === bundle.d.bits.size), \"'D' channel contains improper response size\" + extra)\n } .otherwise {\n assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||\n (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), \"'D' channel contains improper opcode response\" + extra)\n assume((bundle.d.bits.size === a_size_lookup), \"'D' channel contains improper response size\" + extra)\n }\n }\n when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {\n assume((!bundle.d.ready) || bundle.a.ready, \"ready check\")\n }\n\n if (edge.manager.minLatency > 0) {\n assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s\"'A' and 'D' concurrent, despite minlatency > 0\" + extra)\n }\n\n inflight := (inflight | a_set) & ~d_clr\n inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr\n inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr\n\n val watchdog = RegInit(0.U(32.W))\n val limit = PlusArg(\"tilelink_timeout\",\n docstring=\"Kill emulation after INT waiting TileLink cycles. Off if 0.\")\n monAssert (!inflight.orR || limit === 0.U || watchdog < limit, \"TileLink timeout expired\" + extra)\n\n watchdog := watchdog + 1.U\n when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }\n }\n\n def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {\n val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)\n val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything\n\n val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)\n val log_c_size_bus_size = log2Ceil(c_size_bus_size)\n def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits\n\n val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))\n val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))\n val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))\n inflight.suggestName(\"inflight\")\n inflight_opcodes.suggestName(\"inflight_opcodes\")\n inflight_sizes.suggestName(\"inflight_sizes\")\n\n val c_first = edge.first(bundle.c.bits, bundle.c.fire)\n val d_first = edge.first(bundle.d.bits, bundle.d.fire)\n c_first.suggestName(\"c_first\")\n d_first.suggestName(\"d_first\")\n\n val c_set = WireInit(0.U(edge.client.endSourceId.W))\n val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))\n val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))\n val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))\n c_set.suggestName(\"c_set\")\n c_set_wo_ready.suggestName(\"c_set_wo_ready\")\n c_opcodes_set.suggestName(\"c_opcodes_set\")\n c_sizes_set.suggestName(\"c_sizes_set\")\n\n val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))\n val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))\n c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U\n c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U\n c_opcode_lookup.suggestName(\"c_opcode_lookup\")\n c_size_lookup.suggestName(\"c_size_lookup\")\n\n val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))\n val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))\n c_opcodes_set_interm.suggestName(\"c_opcodes_set_interm\")\n c_sizes_set_interm.suggestName(\"c_sizes_set_interm\")\n\n when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {\n c_set_wo_ready := UIntToOH(bundle.c.bits.source)\n }\n\n when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {\n c_set := UIntToOH(bundle.c.bits.source)\n c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U\n c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U\n c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)\n c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)\n monAssert(!inflight(bundle.c.bits.source), \"'C' channel re-used a source ID\" + extra)\n }\n\n val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData\n\n val d_clr = WireInit(0.U(edge.client.endSourceId.W))\n val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))\n val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))\n val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))\n d_clr.suggestName(\"d_clr\")\n d_clr_wo_ready.suggestName(\"d_clr_wo_ready\")\n d_opcodes_clr.suggestName(\"d_opcodes_clr\")\n d_sizes_clr.suggestName(\"d_sizes_clr\")\n\n val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck\n when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {\n d_clr_wo_ready := UIntToOH(bundle.d.bits.source)\n }\n\n when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {\n d_clr := UIntToOH(bundle.d.bits.source)\n d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)\n d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)\n }\n\n when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {\n val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)\n assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, \"'D' channel acknowledged for nothing inflight\" + extra)\n when (same_cycle_resp) {\n assume((bundle.d.bits.size === bundle.c.bits.size), \"'D' channel contains improper response size\" + extra)\n } .otherwise {\n assume((bundle.d.bits.size === c_size_lookup), \"'D' channel contains improper response size\" + extra)\n }\n }\n\n when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {\n assume((!bundle.d.ready) || bundle.c.ready, \"ready check\")\n }\n\n if (edge.manager.minLatency > 0) {\n when (c_set_wo_ready.orR) {\n assume(c_set_wo_ready =/= d_clr_wo_ready, s\"'C' and 'D' concurrent, despite minlatency > 0\" + extra)\n }\n }\n\n inflight := (inflight | c_set) & ~d_clr\n inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr\n inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr\n\n val watchdog = RegInit(0.U(32.W))\n val limit = PlusArg(\"tilelink_timeout\",\n docstring=\"Kill emulation after INT waiting TileLink cycles. Off if 0.\")\n monAssert (!inflight.orR || limit === 0.U || watchdog < limit, \"TileLink timeout expired\" + extra)\n\n watchdog := watchdog + 1.U\n when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }\n }\n\n def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {\n val inflight = RegInit(0.U(edge.manager.endSinkId.W))\n\n val d_first = edge.first(bundle.d.bits, bundle.d.fire)\n val e_first = true.B\n\n val d_set = WireInit(0.U(edge.manager.endSinkId.W))\n when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {\n d_set := UIntToOH(bundle.d.bits.sink)\n assume(!inflight(bundle.d.bits.sink), \"'D' channel re-used a sink ID\" + extra)\n }\n\n val e_clr = WireInit(0.U(edge.manager.endSinkId.W))\n when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {\n e_clr := UIntToOH(bundle.e.bits.sink)\n monAssert((d_set | inflight)(bundle.e.bits.sink), \"'E' channel acknowledged for nothing inflight\" + extra)\n }\n\n // edge.client.minLatency applies to BC, not DE\n\n inflight := (inflight | d_set) & ~e_clr\n }\n\n def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {\n val sourceBits = log2Ceil(edge.client.endSourceId)\n val tooBig = 14 // >16kB worth of flight information gets to be too much\n if (sourceBits > tooBig) {\n println(s\"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked\")\n } else {\n if (args.edge.params(TestplanTestType).simulation) {\n if (args.edge.params(TLMonitorStrictMode)) {\n legalizeADSource(bundle, edge)\n legalizeCDSource(bundle, edge)\n } else {\n legalizeADSourceOld(bundle, edge)\n }\n }\n if (args.edge.params(TestplanTestType).formal) {\n legalizeADSourceFormal(bundle, edge)\n }\n }\n if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {\n // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...\n val sinkBits = log2Ceil(edge.manager.endSinkId)\n if (sinkBits > tooBig) {\n println(s\"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked\")\n } else {\n legalizeDESink(bundle, edge)\n }\n }\n }\n\n def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {\n legalizeFormat (bundle, edge)\n legalizeMultibeat (bundle, edge)\n legalizeUnique (bundle, edge)\n }\n}\nFile Misc.scala:\n// See LICENSE.Berkeley for license details.\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.util.random.LFSR\nimport org.chipsalliance.cde.config.Parameters\nimport scala.math._\n\nclass ParameterizedBundle(implicit p: Parameters) extends Bundle\n\ntrait Clocked extends Bundle {\n val clock = Clock()\n val reset = Bool() \n}\n\nobject DecoupledHelper {\n def apply(rvs: Bool*) = new DecoupledHelper(rvs)\n}\n\nclass DecoupledHelper(val rvs: Seq[Bool]) {\n def fire(exclude: Bool, includes: Bool*) = {\n require(rvs.contains(exclude), \"Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!\")\n (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)\n }\n def fire() = {\n rvs.reduce(_ && _)\n }\n}\n\nobject MuxT {\n def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =\n (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))\n\n def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =\n (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))\n\n def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =\n (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))\n}\n\n/** Creates a cascade of n MuxTs to search for a key value. */\nobject MuxTLookup {\n def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {\n var res = default\n for ((k, v) <- mapping.reverse)\n res = MuxT(k === key, v, res)\n res\n }\n\n def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {\n var res = default\n for ((k, v) <- mapping.reverse)\n res = MuxT(k === key, v, res)\n res\n }\n}\n\nobject ValidMux {\n def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {\n apply(v1 +: v2.toSeq)\n }\n def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {\n val out = Wire(Valid(valids.head.bits.cloneType))\n out.valid := valids.map(_.valid).reduce(_ || _)\n out.bits := MuxCase(valids.head.bits,\n valids.map(v => (v.valid -> v.bits)))\n out\n }\n}\n\nobject Str\n{\n def apply(s: String): UInt = {\n var i = BigInt(0)\n require(s.forall(validChar _))\n for (c <- s)\n i = (i << 8) | c\n i.U((s.length*8).W)\n }\n def apply(x: Char): UInt = {\n require(validChar(x))\n x.U(8.W)\n }\n def apply(x: UInt): UInt = apply(x, 10)\n def apply(x: UInt, radix: Int): UInt = {\n val rad = radix.U\n val w = x.getWidth\n require(w > 0)\n\n var q = x\n var s = digit(q % rad)\n for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {\n q = q / rad\n s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)\n }\n s\n }\n def apply(x: SInt): UInt = apply(x, 10)\n def apply(x: SInt, radix: Int): UInt = {\n val neg = x < 0.S\n val abs = x.abs.asUInt\n if (radix != 10) {\n Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))\n } else {\n val rad = radix.U\n val w = abs.getWidth\n require(w > 0)\n\n var q = abs\n var s = digit(q % rad)\n var needSign = neg\n for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {\n q = q / rad\n val placeSpace = q === 0.U\n val space = Mux(needSign, Str('-'), Str(' '))\n needSign = needSign && !placeSpace\n s = Cat(Mux(placeSpace, space, digit(q % rad)), s)\n }\n Cat(Mux(needSign, Str('-'), Str(' ')), s)\n }\n }\n\n private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)\n private def validChar(x: Char) = x == (x & 0xFF)\n}\n\nobject Split\n{\n def apply(x: UInt, n0: Int) = {\n val w = x.getWidth\n (x.extract(w-1,n0), x.extract(n0-1,0))\n }\n def apply(x: UInt, n1: Int, n0: Int) = {\n val w = x.getWidth\n (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))\n }\n def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {\n val w = x.getWidth\n (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))\n }\n}\n\nobject Random\n{\n def apply(mod: Int, random: UInt): UInt = {\n if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)\n else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))\n }\n def apply(mod: Int): UInt = apply(mod, randomizer)\n def oneHot(mod: Int, random: UInt): UInt = {\n if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))\n else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt\n }\n def oneHot(mod: Int): UInt = oneHot(mod, randomizer)\n\n private def randomizer = LFSR(16)\n private def partition(value: UInt, slices: Int) =\n Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)\n}\n\nobject Majority {\n def apply(in: Set[Bool]): Bool = {\n val n = (in.size >> 1) + 1\n val clauses = in.subsets(n).map(_.reduce(_ && _))\n clauses.reduce(_ || _)\n }\n\n def apply(in: Seq[Bool]): Bool = apply(in.toSet)\n\n def apply(in: UInt): Bool = apply(in.asBools.toSet)\n}\n\nobject PopCountAtLeast {\n private def two(x: UInt): (Bool, Bool) = x.getWidth match {\n case 1 => (x.asBool, false.B)\n case n =>\n val half = x.getWidth / 2\n val (leftOne, leftTwo) = two(x(half - 1, 0))\n val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))\n (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))\n }\n def apply(x: UInt, n: Int): Bool = n match {\n case 0 => true.B\n case 1 => x.orR\n case 2 => two(x)._2\n case 3 => PopCount(x) >= n.U\n }\n}\n\n// This gets used everywhere, so make the smallest circuit possible ...\n// Given an address and size, create a mask of beatBytes size\n// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111\n// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01\nobject MaskGen {\n def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {\n require (groupBy >= 1 && beatBytes >= groupBy)\n require (isPow2(beatBytes) && isPow2(groupBy))\n val lgBytes = log2Ceil(beatBytes)\n val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U\n\n def helper(i: Int): Seq[(Bool, Bool)] = {\n if (i == 0) {\n Seq((lgSize >= lgBytes.asUInt, true.B))\n } else {\n val sub = helper(i-1)\n val size = sizeOH(lgBytes - i)\n val bit = addr_lo(lgBytes - i)\n val nbit = !bit\n Seq.tabulate (1 << i) { j =>\n val (sub_acc, sub_eq) = sub(j/2)\n val eq = sub_eq && (if (j % 2 == 1) bit else nbit)\n val acc = sub_acc || (size && eq)\n (acc, eq)\n }\n }\n }\n\n if (groupBy == beatBytes) 1.U else\n Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)\n }\n}\nFile PlusArg.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3._\nimport chisel3.experimental._\nimport chisel3.util.HasBlackBoxResource\n\n@deprecated(\"This will be removed in Rocket Chip 2020.08\", \"Rocket Chip 2020.05\")\ncase class PlusArgInfo(default: BigInt, docstring: String)\n\n/** Case class for PlusArg information\n *\n * @tparam A scala type of the PlusArg value\n * @param default optional default value\n * @param docstring text to include in the help\n * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)\n */\nprivate case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)\n\n/** Typeclass for converting a type to a doctype string\n * @tparam A some type\n */\ntrait Doctypeable[A] {\n\n /** Return the doctype string for some option */\n def toDoctype(a: Option[A]): String\n\n}\n\n/** Object containing implementations of the Doctypeable typeclass */\nobject Doctypes {\n\n /** Converts an Int => \"INT\" */\n implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = \"INT\" }\n\n /** Converts a BigInt => \"INT\" */\n implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = \"INT\" }\n\n /** Converts a String => \"STRING\" */\n implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = \"STRING\" }\n\n}\n\nclass plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(\n \"FORMAT\" -> StringParam(format),\n \"DEFAULT\" -> IntParam(default),\n \"WIDTH\" -> IntParam(width)\n )) with HasBlackBoxResource {\n val io = IO(new Bundle {\n val out = Output(UInt(width.W))\n })\n\n addResource(\"/vsrc/plusarg_reader.v\")\n}\n\n/* This wrapper class has no outputs, making it clear it is a simulation-only construct */\nclass PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {\n val io = IO(new Bundle {\n val count = Input(UInt(width.W))\n })\n val max = Module(new plusarg_reader(format, default, docstring, width)).io.out\n when (max > 0.U) {\n assert (io.count < max, s\"Timeout exceeded: $docstring\")\n }\n}\n\nimport Doctypes._\n\nobject PlusArg\n{\n /** PlusArg(\"foo\") will return 42.U if the simulation is run with +foo=42\n * Do not use this as an initial register value. The value is set in an\n * initial block and thus accessing it from another initial is racey.\n * Add a docstring to document the arg, which can be dumped in an elaboration\n * pass.\n */\n def apply(name: String, default: BigInt = 0, docstring: String = \"\", width: Int = 32): UInt = {\n PlusArgArtefacts.append(name, Some(default), docstring)\n Module(new plusarg_reader(name + \"=%d\", default, docstring, width)).io.out\n }\n\n /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert\n * to kill the simulation when count exceeds the specified integer argument.\n * Default 0 will never assert.\n */\n def timeout(name: String, default: BigInt = 0, docstring: String = \"\", width: Int = 32)(count: UInt): Unit = {\n PlusArgArtefacts.append(name, Some(default), docstring)\n Module(new PlusArgTimeout(name + \"=%d\", default, docstring, width)).io.count := count\n }\n}\n\nobject PlusArgArtefacts {\n private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty\n\n /* Add a new PlusArg */\n @deprecated(\n \"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08\",\n \"Rocket Chip 2020.05\"\n )\n def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)\n\n /** Add a new PlusArg\n *\n * @tparam A scala type of the PlusArg value\n * @param name name for the PlusArg\n * @param default optional default value\n * @param docstring text to include in the help\n */\n def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =\n artefacts = artefacts ++\n Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))\n\n /* From plus args, generate help text */\n private def serializeHelp_cHeader(tab: String = \"\"): String = artefacts\n .map{ case(arg, info) =>\n s\"\"\"|$tab+$arg=${info.doctype}\\\\n\\\\\n |$tab${\" \"*20}${info.docstring}\\\\n\\\\\n |\"\"\".stripMargin ++ info.default.map{ case default =>\n s\"$tab${\" \"*22}(default=${default})\\\\n\\\\\\n\"}.getOrElse(\"\")\n }.toSeq.mkString(\"\\\\n\\\\\\n\") ++ \"\\\"\"\n\n /* From plus args, generate a char array of their names */\n private def serializeArray_cHeader(tab: String = \"\"): String = {\n val prettyTab = tab + \" \" * 44 // Length of 'static const ...'\n s\"${tab}static const char * verilog_plusargs [] = {\\\\\\n\" ++\n artefacts\n .map{ case(arg, _) => s\"\"\"$prettyTab\"$arg\",\\\\\\n\"\"\" }\n .mkString(\"\")++\n s\"${prettyTab}0};\"\n }\n\n /* Generate C code to be included in emulator.cc that helps with\n * argument parsing based on available Verilog PlusArgs */\n def serialize_cHeader(): String =\n s\"\"\"|#define PLUSARG_USAGE_OPTIONS \\\"EMULATOR VERILOG PLUSARGS\\\\n\\\\\n |${serializeHelp_cHeader(\" \"*7)}\n |${serializeArray_cHeader()}\n |\"\"\".stripMargin\n}\nFile package.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip\n\nimport chisel3._\nimport chisel3.util._\nimport scala.math.min\nimport scala.collection.{immutable, mutable}\n\npackage object util {\n implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {\n def unzip = (x.map(_._1), x.map(_._2))\n }\n\n implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {\n def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR\n \n def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)\n }\n\n implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {\n\n /** Like Vec.apply(idx), but tolerates indices of mismatched width */\n def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))\n }\n\n implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {\n def apply(idx: UInt): T = {\n if (x.size <= 1) {\n x.head\n } else if (!isPow2(x.size)) {\n // For non-power-of-2 seqs, reflect elements to simplify decoder\n (x ++ x.takeRight(x.size & -x.size)).toSeq(idx)\n } else {\n // Ignore MSBs of idx\n val truncIdx =\n if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx\n else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)\n x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }\n }\n }\n\n def extract(idx: UInt): T = VecInit(x).extract(idx)\n\n def asUInt: UInt = Cat(x.map(_.asUInt).reverse)\n\n def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)\n\n def rotate(n: UInt): Seq[T] = {\n if (x.size <= 1) {\n x\n } else {\n require(isPow2(x.size))\n val amt = n.padTo(log2Ceil(x.size))\n (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })\n }\n }\n\n def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)\n\n def rotateRight(n: UInt): Seq[T] = {\n if (x.size <= 1) {\n x\n } else {\n require(isPow2(x.size))\n val amt = n.padTo(log2Ceil(x.size))\n (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })\n }\n }\n }\n\n // allow bitwise ops on Seq[Bool] just like UInt\n implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {\n def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }\n def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }\n def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }\n def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x\n def >> (n: Int): Seq[Bool] = x drop n\n def unary_~ : Seq[Bool] = x.map(!_)\n def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)\n def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)\n def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)\n\n private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)\n }\n\n implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {\n def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))\n\n def getElements: Seq[Element] = x match {\n case e: Element => Seq(e)\n case a: Aggregate => a.getElements.flatMap(_.getElements)\n }\n }\n\n /** Any Data subtype that has a Bool member named valid. */\n type DataCanBeValid = Data { val valid: Bool }\n\n implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {\n def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)\n }\n\n implicit class StringToAugmentedString(private val x: String) extends AnyVal {\n /** converts from camel case to to underscores, also removing all spaces */\n def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + \"\") getOrElse \"\") {\n case (acc, c) if c.isUpper => acc + \"_\" + c.toLower\n case (acc, c) if c == ' ' => acc\n case (acc, c) => acc + c\n }\n\n /** converts spaces or underscores to hyphens, also lowering case */\n def kebab: String = x.toLowerCase map {\n case ' ' => '-'\n case '_' => '-'\n case c => c\n }\n\n def named(name: Option[String]): String = {\n x + name.map(\"_named_\" + _ ).getOrElse(\"_with_no_name\")\n }\n\n def named(name: String): String = named(Some(name))\n }\n\n implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)\n implicit def wcToUInt(c: WideCounter): UInt = c.value\n\n implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {\n def sextTo(n: Int): UInt = {\n require(x.getWidth <= n)\n if (x.getWidth == n) x\n else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)\n }\n\n def padTo(n: Int): UInt = {\n require(x.getWidth <= n)\n if (x.getWidth == n) x\n else Cat(0.U((n - x.getWidth).W), x)\n }\n\n // shifts left by n if n >= 0, or right by -n if n < 0\n def << (n: SInt): UInt = {\n val w = n.getWidth - 1\n require(w <= 30)\n\n val shifted = x << n(w-1, 0)\n Mux(n(w), shifted >> (1 << w), shifted)\n }\n\n // shifts right by n if n >= 0, or left by -n if n < 0\n def >> (n: SInt): UInt = {\n val w = n.getWidth - 1\n require(w <= 30)\n\n val shifted = x << (1 << w) >> n(w-1, 0)\n Mux(n(w), shifted, shifted >> (1 << w))\n }\n\n // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts\n def extract(hi: Int, lo: Int): UInt = {\n require(hi >= lo-1)\n if (hi == lo-1) 0.U\n else x(hi, lo)\n }\n\n // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts\n def extractOption(hi: Int, lo: Int): Option[UInt] = {\n require(hi >= lo-1)\n if (hi == lo-1) None\n else Some(x(hi, lo))\n }\n\n // like x & ~y, but first truncate or zero-extend y to x's width\n def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))\n\n def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)\n\n def rotateRight(n: UInt): UInt = {\n if (x.getWidth <= 1) {\n x\n } else {\n val amt = n.padTo(log2Ceil(x.getWidth))\n (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))\n }\n }\n\n def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))\n\n def rotateLeft(n: UInt): UInt = {\n if (x.getWidth <= 1) {\n x\n } else {\n val amt = n.padTo(log2Ceil(x.getWidth))\n (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))\n }\n }\n\n // compute (this + y) % n, given (this < n) and (y < n)\n def addWrap(y: UInt, n: Int): UInt = {\n val z = x +& y\n if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)\n }\n\n // compute (this - y) % n, given (this < n) and (y < n)\n def subWrap(y: UInt, n: Int): UInt = {\n val z = x -& y\n if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)\n }\n\n def grouped(width: Int): Seq[UInt] =\n (0 until x.getWidth by width).map(base => x(base + width - 1, base))\n\n def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds\n\n def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)\n\n // Like >=, but prevents x-prop for ('x >= 0)\n def >== (y: UInt): Bool = x >= y || y === 0.U\n }\n\n implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {\n def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)\n def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)\n }\n\n implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {\n def toInt: Int = if (x) 1 else 0\n\n // this one's snagged from scalaz\n def option[T](z: => T): Option[T] = if (x) Some(z) else None\n }\n\n implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {\n // exact log2\n def log2: Int = {\n require(isPow2(x))\n log2Ceil(x)\n }\n }\n\n def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)\n def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))\n def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)\n def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)\n\n def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None\n\n // Fill 1s from low bits to high bits\n def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)\n def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {\n val stop = min(width, cap)\n def helper(s: Int, x: UInt): UInt =\n if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))\n helper(1, x)(width-1, 0)\n }\n\n // Fill 1s form high bits to low bits\n def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)\n def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {\n val stop = min(width, cap)\n def helper(s: Int, x: UInt): UInt =\n if (s >= stop) x else helper(s+s, x | (x >> s))\n helper(1, x)(width-1, 0)\n }\n\n def OptimizationBarrier[T <: Data](in: T): T = {\n val barrier = Module(new Module {\n val io = IO(new Bundle {\n val x = Input(chiselTypeOf(in))\n val y = Output(chiselTypeOf(in))\n })\n io.y := io.x\n override def desiredName = s\"OptimizationBarrier_${in.typeName}\"\n })\n barrier.io.x := in\n barrier.io.y\n }\n\n /** Similar to Seq.groupBy except this returns a Seq instead of a Map\n * Useful for deterministic code generation\n */\n def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {\n val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]\n for (x <- xs) {\n val key = f(x)\n val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])\n l += x\n }\n map.view.map({ case (k, vs) => k -> vs.toList }).toList\n }\n\n def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {\n case 1 => List.fill(n)(in.head)\n case x if x == n => in\n case _ => throw new Exception(s\"must provide exactly 1 or $n of some field, but got:\\n$in\")\n }\n\n // HeterogeneousBag moved to standalond diplomacy\n @deprecated(\"HeterogeneousBag has been absorbed into standalone diplomacy library\", \"rocketchip 2.0.0\")\n def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)\n @deprecated(\"HeterogeneousBag has been absorbed into standalone diplomacy library\", \"rocketchip 2.0.0\")\n val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag\n}\nFile Bundles.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.tilelink\n\nimport chisel3._\nimport freechips.rocketchip.util._\nimport scala.collection.immutable.ListMap\nimport chisel3.util.Decoupled\nimport chisel3.util.DecoupledIO\nimport chisel3.reflect.DataMirror\n\nabstract class TLBundleBase(val params: TLBundleParameters) extends Bundle\n\n// common combos in lazy policy:\n// Put + Acquire\n// Release + AccessAck\n\nobject TLMessages\n{\n // A B C D E\n def PutFullData = 0.U // . . => AccessAck\n def PutPartialData = 1.U // . . => AccessAck\n def ArithmeticData = 2.U // . . => AccessAckData\n def LogicalData = 3.U // . . => AccessAckData\n def Get = 4.U // . . => AccessAckData\n def Hint = 5.U // . . => HintAck\n def AcquireBlock = 6.U // . => Grant[Data]\n def AcquirePerm = 7.U // . => Grant[Data]\n def Probe = 6.U // . => ProbeAck[Data]\n def AccessAck = 0.U // . .\n def AccessAckData = 1.U // . .\n def HintAck = 2.U // . .\n def ProbeAck = 4.U // .\n def ProbeAckData = 5.U // .\n def Release = 6.U // . => ReleaseAck\n def ReleaseData = 7.U // . => ReleaseAck\n def Grant = 4.U // . => GrantAck\n def GrantData = 5.U // . => GrantAck\n def ReleaseAck = 6.U // .\n def GrantAck = 0.U // .\n\n def isA(x: UInt) = x <= AcquirePerm\n def isB(x: UInt) = x <= Probe\n def isC(x: UInt) = x <= ReleaseData\n def isD(x: UInt) = x <= ReleaseAck\n\n def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant)\n def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck)\n\n def a = Seq( (\"PutFullData\",TLPermissions.PermMsgReserved),\n (\"PutPartialData\",TLPermissions.PermMsgReserved),\n (\"ArithmeticData\",TLAtomics.ArithMsg),\n (\"LogicalData\",TLAtomics.LogicMsg),\n (\"Get\",TLPermissions.PermMsgReserved),\n (\"Hint\",TLHints.HintsMsg),\n (\"AcquireBlock\",TLPermissions.PermMsgGrow),\n (\"AcquirePerm\",TLPermissions.PermMsgGrow))\n\n def b = Seq( (\"PutFullData\",TLPermissions.PermMsgReserved),\n (\"PutPartialData\",TLPermissions.PermMsgReserved),\n (\"ArithmeticData\",TLAtomics.ArithMsg),\n (\"LogicalData\",TLAtomics.LogicMsg),\n (\"Get\",TLPermissions.PermMsgReserved),\n (\"Hint\",TLHints.HintsMsg),\n (\"Probe\",TLPermissions.PermMsgCap))\n\n def c = Seq( (\"AccessAck\",TLPermissions.PermMsgReserved),\n (\"AccessAckData\",TLPermissions.PermMsgReserved),\n (\"HintAck\",TLPermissions.PermMsgReserved),\n (\"Invalid Opcode\",TLPermissions.PermMsgReserved),\n (\"ProbeAck\",TLPermissions.PermMsgReport),\n (\"ProbeAckData\",TLPermissions.PermMsgReport),\n (\"Release\",TLPermissions.PermMsgReport),\n (\"ReleaseData\",TLPermissions.PermMsgReport))\n\n def d = Seq( (\"AccessAck\",TLPermissions.PermMsgReserved),\n (\"AccessAckData\",TLPermissions.PermMsgReserved),\n (\"HintAck\",TLPermissions.PermMsgReserved),\n (\"Invalid Opcode\",TLPermissions.PermMsgReserved),\n (\"Grant\",TLPermissions.PermMsgCap),\n (\"GrantData\",TLPermissions.PermMsgCap),\n (\"ReleaseAck\",TLPermissions.PermMsgReserved))\n\n}\n\n/**\n * The three primary TileLink permissions are:\n * (T)runk: the agent is (or is on inwards path to) the global point of serialization.\n * (B)ranch: the agent is on an outwards path to\n * (N)one:\n * These permissions are permuted by transfer operations in various ways.\n * Operations can cap permissions, request for them to be grown or shrunk,\n * or for a report on their current status.\n */\nobject TLPermissions\n{\n val aWidth = 2\n val bdWidth = 2\n val cWidth = 3\n\n // Cap types (Grant = new permissions, Probe = permisions <= target)\n def toT = 0.U(bdWidth.W)\n def toB = 1.U(bdWidth.W)\n def toN = 2.U(bdWidth.W)\n def isCap(x: UInt) = x <= toN\n\n // Grow types (Acquire = permissions >= target)\n def NtoB = 0.U(aWidth.W)\n def NtoT = 1.U(aWidth.W)\n def BtoT = 2.U(aWidth.W)\n def isGrow(x: UInt) = x <= BtoT\n\n // Shrink types (ProbeAck, Release)\n def TtoB = 0.U(cWidth.W)\n def TtoN = 1.U(cWidth.W)\n def BtoN = 2.U(cWidth.W)\n def isShrink(x: UInt) = x <= BtoN\n\n // Report types (ProbeAck, Release)\n def TtoT = 3.U(cWidth.W)\n def BtoB = 4.U(cWidth.W)\n def NtoN = 5.U(cWidth.W)\n def isReport(x: UInt) = x <= NtoN\n\n def PermMsgGrow:Seq[String] = Seq(\"Grow NtoB\", \"Grow NtoT\", \"Grow BtoT\")\n def PermMsgCap:Seq[String] = Seq(\"Cap toT\", \"Cap toB\", \"Cap toN\")\n def PermMsgReport:Seq[String] = Seq(\"Shrink TtoB\", \"Shrink TtoN\", \"Shrink BtoN\", \"Report TotT\", \"Report BtoB\", \"Report NtoN\")\n def PermMsgReserved:Seq[String] = Seq(\"Reserved\")\n}\n\nobject TLAtomics\n{\n val width = 3\n\n // Arithmetic types\n def MIN = 0.U(width.W)\n def MAX = 1.U(width.W)\n def MINU = 2.U(width.W)\n def MAXU = 3.U(width.W)\n def ADD = 4.U(width.W)\n def isArithmetic(x: UInt) = x <= ADD\n\n // Logical types\n def XOR = 0.U(width.W)\n def OR = 1.U(width.W)\n def AND = 2.U(width.W)\n def SWAP = 3.U(width.W)\n def isLogical(x: UInt) = x <= SWAP\n\n def ArithMsg:Seq[String] = Seq(\"MIN\", \"MAX\", \"MINU\", \"MAXU\", \"ADD\")\n def LogicMsg:Seq[String] = Seq(\"XOR\", \"OR\", \"AND\", \"SWAP\")\n}\n\n\nobject TLHints\n{\n val width = 1\n\n def PREFETCH_READ = 0.U(width.W)\n def PREFETCH_WRITE = 1.U(width.W)\n def isHints(x: UInt) = x <= PREFETCH_WRITE\n\n def HintsMsg:Seq[String] = Seq(\"PrefetchRead\", \"PrefetchWrite\")\n}\n\nsealed trait TLChannel extends TLBundleBase {\n val channelName: String\n}\n\nsealed trait TLDataChannel extends TLChannel\nsealed trait TLAddrChannel extends TLDataChannel\n\nfinal class TLBundleA(params: TLBundleParameters)\n extends TLBundleBase(params) with TLAddrChannel\n{\n override def typeName = s\"TLBundleA_${params.shortName}\"\n val channelName = \"'A' channel\"\n // fixed fields during multibeat:\n val opcode = UInt(3.W)\n val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint\n val size = UInt(params.sizeBits.W)\n val source = UInt(params.sourceBits.W) // from\n val address = UInt(params.addressBits.W) // to\n val user = BundleMap(params.requestFields)\n val echo = BundleMap(params.echoFields)\n // variable fields during multibeat:\n val mask = UInt((params.dataBits/8).W)\n val data = UInt(params.dataBits.W)\n val corrupt = Bool() // only applies to *Data messages\n}\nfinal class TLBundleB(params: TLBundleParameters)\n extends TLBundleBase(params) with TLAddrChannel\n{\n override def typeName = s\"TLBundleB_${params.shortName}\"\n val channelName = \"'B' channel\"\n // fixed fields during multibeat:\n val opcode = UInt(3.W)\n val param = UInt(TLPermissions.bdWidth.W) // cap perms\n val size = UInt(params.sizeBits.W)\n val source = UInt(params.sourceBits.W) // to\n val address = UInt(params.addressBits.W) // from\n // variable fields during multibeat:\n val mask = UInt((params.dataBits/8).W)\n val data = UInt(params.dataBits.W)\n val corrupt = Bool() // only applies to *Data messages\n}\n\nfinal class TLBundleC(params: TLBundleParameters)\n extends TLBundleBase(params) with TLAddrChannel\n{\n override def typeName = s\"TLBundleC_${params.shortName}\"\n val channelName = \"'C' channel\"\n // fixed fields during multibeat:\n val opcode = UInt(3.W)\n val param = UInt(TLPermissions.cWidth.W) // shrink or report perms\n val size = UInt(params.sizeBits.W)\n val source = UInt(params.sourceBits.W) // from\n val address = UInt(params.addressBits.W) // to\n val user = BundleMap(params.requestFields)\n val echo = BundleMap(params.echoFields)\n // variable fields during multibeat:\n val data = UInt(params.dataBits.W)\n val corrupt = Bool() // only applies to *Data messages\n}\n\nfinal class TLBundleD(params: TLBundleParameters)\n extends TLBundleBase(params) with TLDataChannel\n{\n override def typeName = s\"TLBundleD_${params.shortName}\"\n val channelName = \"'D' channel\"\n // fixed fields during multibeat:\n val opcode = UInt(3.W)\n val param = UInt(TLPermissions.bdWidth.W) // cap perms\n val size = UInt(params.sizeBits.W)\n val source = UInt(params.sourceBits.W) // to\n val sink = UInt(params.sinkBits.W) // from\n val denied = Bool() // implies corrupt iff *Data\n val user = BundleMap(params.responseFields)\n val echo = BundleMap(params.echoFields)\n // variable fields during multibeat:\n val data = UInt(params.dataBits.W)\n val corrupt = Bool() // only applies to *Data messages\n}\n\nfinal class TLBundleE(params: TLBundleParameters)\n extends TLBundleBase(params) with TLChannel\n{\n override def typeName = s\"TLBundleE_${params.shortName}\"\n val channelName = \"'E' channel\"\n val sink = UInt(params.sinkBits.W) // to\n}\n\nclass TLBundle(val params: TLBundleParameters) extends Record\n{\n // Emulate a Bundle with elements abcde or ad depending on params.hasBCE\n\n private val optA = Some (Decoupled(new TLBundleA(params)))\n private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params))))\n private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params)))\n private val optD = Some (Flipped(Decoupled(new TLBundleD(params))))\n private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params)))\n\n def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params)))))\n def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params)))))\n def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params)))))\n def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params)))))\n def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params)))))\n\n val elements =\n if (params.hasBCE) ListMap(\"e\" -> e, \"d\" -> d, \"c\" -> c, \"b\" -> b, \"a\" -> a)\n else ListMap(\"d\" -> d, \"a\" -> a)\n\n def tieoff(): Unit = {\n DataMirror.specifiedDirectionOf(a.ready) match {\n case SpecifiedDirection.Input =>\n a.ready := false.B\n c.ready := false.B\n e.ready := false.B\n b.valid := false.B\n d.valid := false.B\n case SpecifiedDirection.Output =>\n a.valid := false.B\n c.valid := false.B\n e.valid := false.B\n b.ready := false.B\n d.ready := false.B\n case _ =>\n }\n }\n}\n\nobject TLBundle\n{\n def apply(params: TLBundleParameters) = new TLBundle(params)\n}\n\nclass TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle\n\nclass TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params)\n{\n val a = new AsyncBundle(new TLBundleA(params.base), params.async)\n val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async))\n val c = new AsyncBundle(new TLBundleC(params.base), params.async)\n val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async))\n val e = new AsyncBundle(new TLBundleE(params.base), params.async)\n}\n\nclass TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params)\n{\n val a = RationalIO(new TLBundleA(params))\n val b = Flipped(RationalIO(new TLBundleB(params)))\n val c = RationalIO(new TLBundleC(params))\n val d = Flipped(RationalIO(new TLBundleD(params)))\n val e = RationalIO(new TLBundleE(params))\n}\n\nclass TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params)\n{\n val a = CreditedIO(new TLBundleA(params))\n val b = Flipped(CreditedIO(new TLBundleB(params)))\n val c = CreditedIO(new TLBundleC(params))\n val d = Flipped(CreditedIO(new TLBundleD(params)))\n val e = CreditedIO(new TLBundleE(params))\n}\nFile Parameters.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.diplomacy\n\nimport chisel3._\nimport chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}\nimport freechips.rocketchip.util.ShiftQueue\n\n/** Options for describing the attributes of memory regions */\nobject RegionType {\n // Define the 'more relaxed than' ordering\n val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)\n sealed trait T extends Ordered[T] {\n def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)\n }\n\n case object CACHED extends T // an intermediate agent may have cached a copy of the region for you\n case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided\n case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible\n case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached\n case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects\n case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed\n case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively\n}\n\n// A non-empty half-open range; [start, end)\ncase class IdRange(start: Int, end: Int) extends Ordered[IdRange]\n{\n require (start >= 0, s\"Ids cannot be negative, but got: $start.\")\n require (start <= end, \"Id ranges cannot be negative.\")\n\n def compare(x: IdRange) = {\n val primary = (this.start - x.start).signum\n val secondary = (x.end - this.end).signum\n if (primary != 0) primary else secondary\n }\n\n def overlaps(x: IdRange) = start < x.end && x.start < end\n def contains(x: IdRange) = start <= x.start && x.end <= end\n\n def contains(x: Int) = start <= x && x < end\n def contains(x: UInt) =\n if (size == 0) {\n false.B\n } else if (size == 1) { // simple comparison\n x === start.U\n } else {\n // find index of largest different bit\n val largestDeltaBit = log2Floor(start ^ (end-1))\n val smallestCommonBit = largestDeltaBit + 1 // may not exist in x\n val uncommonMask = (1 << smallestCommonBit) - 1\n val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)\n // the prefix must match exactly (note: may shift ALL bits away)\n (x >> smallestCommonBit) === (start >> smallestCommonBit).U &&\n // firrtl constant prop range analysis can eliminate these two:\n (start & uncommonMask).U <= uncommonBits &&\n uncommonBits <= ((end-1) & uncommonMask).U\n }\n\n def shift(x: Int) = IdRange(start+x, end+x)\n def size = end - start\n def isEmpty = end == start\n\n def range = start until end\n}\n\nobject IdRange\n{\n def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {\n val ranges = s.sorted\n (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }\n }\n}\n\n// An potentially empty inclusive range of 2-powers [min, max] (in bytes)\ncase class TransferSizes(min: Int, max: Int)\n{\n def this(x: Int) = this(x, x)\n\n require (min <= max, s\"Min transfer $min > max transfer $max\")\n require (min >= 0 && max >= 0, s\"TransferSizes must be positive, got: ($min, $max)\")\n require (max == 0 || isPow2(max), s\"TransferSizes must be a power of 2, got: $max\")\n require (min == 0 || isPow2(min), s\"TransferSizes must be a power of 2, got: $min\")\n require (max == 0 || min != 0, s\"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)\")\n\n def none = min == 0\n def contains(x: Int) = isPow2(x) && min <= x && x <= max\n def containsLg(x: Int) = contains(1 << x)\n def containsLg(x: UInt) =\n if (none) false.B\n else if (min == max) { log2Ceil(min).U === x }\n else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }\n\n def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)\n\n def intersect(x: TransferSizes) =\n if (x.max < min || max < x.min) TransferSizes.none\n else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))\n\n // Not a union, because the result may contain sizes contained by neither term\n // NOT TO BE CONFUSED WITH COVERPOINTS\n def mincover(x: TransferSizes) = {\n if (none) {\n x\n } else if (x.none) {\n this\n } else {\n TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))\n }\n }\n\n override def toString() = \"TransferSizes[%d, %d]\".format(min, max)\n}\n\nobject TransferSizes {\n def apply(x: Int) = new TransferSizes(x)\n val none = new TransferSizes(0)\n\n def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)\n def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)\n\n implicit def asBool(x: TransferSizes) = !x.none\n}\n\n// AddressSets specify the address space managed by the manager\n// Base is the base address, and mask are the bits consumed by the manager\n// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff\n// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...\ncase class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]\n{\n // Forbid misaligned base address (and empty sets)\n require ((base & mask) == 0, s\"Mis-aligned AddressSets are forbidden, got: ${this.toString}\")\n require (base >= 0, s\"AddressSet negative base is ambiguous: $base\") // TL2 address widths are not fixed => negative is ambiguous\n // We do allow negative mask (=> ignore all high bits)\n\n def contains(x: BigInt) = ((x ^ base) & ~mask) == 0\n def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S\n\n // turn x into an address contained in this set\n def legalize(x: UInt): UInt = base.U | (mask.U & x)\n\n // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)\n def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0\n // contains iff bitwise: x.mask => mask && contains(x.base)\n def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0\n\n // The number of bytes to which the manager must be aligned\n def alignment = ((mask + 1) & ~mask)\n // Is this a contiguous memory range\n def contiguous = alignment == mask+1\n\n def finite = mask >= 0\n def max = { require (finite, \"Max cannot be calculated on infinite mask\"); base | mask }\n\n // Widen the match function to ignore all bits in imask\n def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)\n\n // Return an AddressSet that only contains the addresses both sets contain\n def intersect(x: AddressSet): Option[AddressSet] = {\n if (!overlaps(x)) {\n None\n } else {\n val r_mask = mask & x.mask\n val r_base = base | x.base\n Some(AddressSet(r_base, r_mask))\n }\n }\n\n def subtract(x: AddressSet): Seq[AddressSet] = {\n intersect(x) match {\n case None => Seq(this)\n case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>\n val nmask = (mask & (bit-1)) | remove.mask\n val nbase = (remove.base ^ bit) & ~nmask\n AddressSet(nbase, nmask)\n }\n }\n }\n\n // AddressSets have one natural Ordering (the containment order, if contiguous)\n def compare(x: AddressSet) = {\n val primary = (this.base - x.base).signum // smallest address first\n val secondary = (x.mask - this.mask).signum // largest mask first\n if (primary != 0) primary else secondary\n }\n\n // We always want to see things in hex\n override def toString() = {\n if (mask >= 0) {\n \"AddressSet(0x%x, 0x%x)\".format(base, mask)\n } else {\n \"AddressSet(0x%x, ~0x%x)\".format(base, ~mask)\n }\n }\n\n def toRanges = {\n require (finite, \"Ranges cannot be calculated on infinite mask\")\n val size = alignment\n val fragments = mask & ~(size-1)\n val bits = bitIndexes(fragments)\n (BigInt(0) until (BigInt(1) << bits.size)).map { i =>\n val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }\n AddressRange(off, size)\n }\n }\n}\n\nobject AddressSet\n{\n val everything = AddressSet(0, -1)\n def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {\n if (size == 0) tail.reverse else {\n val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)\n val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size\n val step =\n if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)\n maxSizeAlignment else maxBaseAlignment\n misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)\n }\n }\n\n def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {\n // Pair terms up by ignoring 'bit'\n seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>\n if (seq.size == 1) {\n seq.head // singleton -> unaffected\n } else {\n key.copy(mask = key.mask | bit) // pair - widen mask by bit\n }\n }.toList\n }\n\n def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {\n val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)\n AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted\n }\n\n def enumerateMask(mask: BigInt): Seq[BigInt] = {\n def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =\n if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)\n helper(0, Nil)\n }\n\n def enumerateBits(mask: BigInt): Seq[BigInt] = {\n def helper(x: BigInt): Seq[BigInt] = {\n if (x == 0) {\n Nil\n } else {\n val bit = x & (-x)\n bit +: helper(x & ~bit)\n }\n }\n helper(mask)\n }\n}\n\ncase class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)\n{\n require (depth >= 0, \"Buffer depth must be >= 0\")\n def isDefined = depth > 0\n def latency = if (isDefined && !flow) 1 else 0\n\n def apply[T <: Data](x: DecoupledIO[T]) =\n if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)\n else x\n\n def irrevocable[T <: Data](x: ReadyValidIO[T]) =\n if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)\n else x\n\n def sq[T <: Data](x: DecoupledIO[T]) =\n if (!isDefined) x else {\n val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))\n sq.io.enq <> x\n sq.io.deq\n }\n\n override def toString() = \"BufferParams:%d%s%s\".format(depth, if (flow) \"F\" else \"\", if (pipe) \"P\" else \"\")\n\n}\n\nobject BufferParams\n{\n implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)\n\n val default = BufferParams(2)\n val none = BufferParams(0)\n val flow = BufferParams(1, true, false)\n val pipe = BufferParams(1, false, true)\n}\n\ncase class TriStateValue(value: Boolean, set: Boolean)\n{\n def update(orig: Boolean) = if (set) value else orig\n}\n\nobject TriStateValue\n{\n implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)\n def unset = TriStateValue(false, false)\n}\n\ntrait DirectedBuffers[T] {\n def copyIn(x: BufferParams): T\n def copyOut(x: BufferParams): T\n def copyInOut(x: BufferParams): T\n}\n\ntrait IdMapEntry {\n def name: String\n def from: IdRange\n def to: IdRange\n def isCache: Boolean\n def requestFifo: Boolean\n def maxTransactionsInFlight: Option[Int]\n def pretty(fmt: String) =\n if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5\n fmt.format(to.start, to.end, from.start, from.end, s\"\"\"\"$name\"\"\"\", if (isCache) \" [CACHE]\" else \"\", if (requestFifo) \" [FIFO]\" else \"\")\n } else {\n fmt.format(from.start, from.end, s\"\"\"\"$name\"\"\"\", if (isCache) \" [CACHE]\" else \"\", if (requestFifo) \" [FIFO]\" else \"\")\n }\n}\n\nabstract class IdMap[T <: IdMapEntry] {\n protected val fmt: String\n val mapping: Seq[T]\n def pretty: String = mapping.map(_.pretty(fmt)).mkString(\",\\n\")\n}\nFile Edges.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.tilelink\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.experimental.SourceInfo\nimport org.chipsalliance.cde.config.Parameters\nimport freechips.rocketchip.util._\n\nclass TLEdge(\n client: TLClientPortParameters,\n manager: TLManagerPortParameters,\n params: Parameters,\n sourceInfo: SourceInfo)\n extends TLEdgeParameters(client, manager, params, sourceInfo)\n{\n def isAligned(address: UInt, lgSize: UInt): Bool = {\n if (maxLgSize == 0) true.B else {\n val mask = UIntToOH1(lgSize, maxLgSize)\n (address & mask) === 0.U\n }\n }\n\n def mask(address: UInt, lgSize: UInt): UInt =\n MaskGen(address, lgSize, manager.beatBytes)\n\n def staticHasData(bundle: TLChannel): Option[Boolean] = {\n bundle match {\n case _:TLBundleA => {\n // Do there exist A messages with Data?\n val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial\n // Do there exist A messages without Data?\n val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint\n // Statically optimize the case where hasData is a constant\n if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None\n }\n case _:TLBundleB => {\n // Do there exist B messages with Data?\n val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial\n // Do there exist B messages without Data?\n val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint\n // Statically optimize the case where hasData is a constant\n if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None\n }\n case _:TLBundleC => {\n // Do there eixst C messages with Data?\n val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe\n // Do there exist C messages without Data?\n val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe\n if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None\n }\n case _:TLBundleD => {\n // Do there eixst D messages with Data?\n val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB\n // Do there exist D messages without Data?\n val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT\n if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None\n }\n case _:TLBundleE => Some(false)\n }\n }\n\n def isRequest(x: TLChannel): Bool = {\n x match {\n case a: TLBundleA => true.B\n case b: TLBundleB => true.B\n case c: TLBundleC => c.opcode(2) && c.opcode(1)\n // opcode === TLMessages.Release ||\n // opcode === TLMessages.ReleaseData\n case d: TLBundleD => d.opcode(2) && !d.opcode(1)\n // opcode === TLMessages.Grant ||\n // opcode === TLMessages.GrantData\n case e: TLBundleE => false.B\n }\n }\n\n def isResponse(x: TLChannel): Bool = {\n x match {\n case a: TLBundleA => false.B\n case b: TLBundleB => false.B\n case c: TLBundleC => !c.opcode(2) || !c.opcode(1)\n // opcode =/= TLMessages.Release &&\n // opcode =/= TLMessages.ReleaseData\n case d: TLBundleD => true.B // Grant isResponse + isRequest\n case e: TLBundleE => true.B\n }\n }\n\n def hasData(x: TLChannel): Bool = {\n val opdata = x match {\n case a: TLBundleA => !a.opcode(2)\n // opcode === TLMessages.PutFullData ||\n // opcode === TLMessages.PutPartialData ||\n // opcode === TLMessages.ArithmeticData ||\n // opcode === TLMessages.LogicalData\n case b: TLBundleB => !b.opcode(2)\n // opcode === TLMessages.PutFullData ||\n // opcode === TLMessages.PutPartialData ||\n // opcode === TLMessages.ArithmeticData ||\n // opcode === TLMessages.LogicalData\n case c: TLBundleC => c.opcode(0)\n // opcode === TLMessages.AccessAckData ||\n // opcode === TLMessages.ProbeAckData ||\n // opcode === TLMessages.ReleaseData\n case d: TLBundleD => d.opcode(0)\n // opcode === TLMessages.AccessAckData ||\n // opcode === TLMessages.GrantData\n case e: TLBundleE => false.B\n }\n staticHasData(x).map(_.B).getOrElse(opdata)\n }\n\n def opcode(x: TLDataChannel): UInt = {\n x match {\n case a: TLBundleA => a.opcode\n case b: TLBundleB => b.opcode\n case c: TLBundleC => c.opcode\n case d: TLBundleD => d.opcode\n }\n }\n\n def param(x: TLDataChannel): UInt = {\n x match {\n case a: TLBundleA => a.param\n case b: TLBundleB => b.param\n case c: TLBundleC => c.param\n case d: TLBundleD => d.param\n }\n }\n\n def size(x: TLDataChannel): UInt = {\n x match {\n case a: TLBundleA => a.size\n case b: TLBundleB => b.size\n case c: TLBundleC => c.size\n case d: TLBundleD => d.size\n }\n }\n\n def data(x: TLDataChannel): UInt = {\n x match {\n case a: TLBundleA => a.data\n case b: TLBundleB => b.data\n case c: TLBundleC => c.data\n case d: TLBundleD => d.data\n }\n }\n\n def corrupt(x: TLDataChannel): Bool = {\n x match {\n case a: TLBundleA => a.corrupt\n case b: TLBundleB => b.corrupt\n case c: TLBundleC => c.corrupt\n case d: TLBundleD => d.corrupt\n }\n }\n\n def mask(x: TLAddrChannel): UInt = {\n x match {\n case a: TLBundleA => a.mask\n case b: TLBundleB => b.mask\n case c: TLBundleC => mask(c.address, c.size)\n }\n }\n\n def full_mask(x: TLAddrChannel): UInt = {\n x match {\n case a: TLBundleA => mask(a.address, a.size)\n case b: TLBundleB => mask(b.address, b.size)\n case c: TLBundleC => mask(c.address, c.size)\n }\n }\n\n def address(x: TLAddrChannel): UInt = {\n x match {\n case a: TLBundleA => a.address\n case b: TLBundleB => b.address\n case c: TLBundleC => c.address\n }\n }\n\n def source(x: TLDataChannel): UInt = {\n x match {\n case a: TLBundleA => a.source\n case b: TLBundleB => b.source\n case c: TLBundleC => c.source\n case d: TLBundleD => d.source\n }\n }\n\n def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)\n def addr_lo(x: UInt): UInt =\n if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)\n\n def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))\n def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))\n\n def numBeats(x: TLChannel): UInt = {\n x match {\n case _: TLBundleE => 1.U\n case bundle: TLDataChannel => {\n val hasData = this.hasData(bundle)\n val size = this.size(bundle)\n val cutoff = log2Ceil(manager.beatBytes)\n val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U\n val decode = UIntToOH(size, maxLgSize+1) >> cutoff\n Mux(hasData, decode | small.asUInt, 1.U)\n }\n }\n }\n\n def numBeats1(x: TLChannel): UInt = {\n x match {\n case _: TLBundleE => 0.U\n case bundle: TLDataChannel => {\n if (maxLgSize == 0) {\n 0.U\n } else {\n val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)\n Mux(hasData(bundle), decode, 0.U)\n }\n }\n }\n }\n\n def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {\n val beats1 = numBeats1(bits)\n val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))\n val counter1 = counter - 1.U\n val first = counter === 0.U\n val last = counter === 1.U || beats1 === 0.U\n val done = last && fire\n val count = (beats1 & ~counter1)\n when (fire) {\n counter := Mux(first, beats1, counter1)\n }\n (first, last, done, count)\n }\n\n def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1\n def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)\n def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)\n\n def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2\n def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)\n def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)\n\n def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3\n def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)\n def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)\n\n def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {\n val r = firstlastHelper(bits, fire)\n (r._1, r._2, r._3)\n }\n def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)\n def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)\n\n def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {\n val r = firstlastHelper(bits, fire)\n (r._1, r._2, r._3, r._4)\n }\n def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)\n def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)\n\n def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {\n val r = firstlastHelper(bits, fire)\n (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))\n }\n def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)\n def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)\n\n // Does the request need T permissions to be executed?\n def needT(a: TLBundleA): Bool = {\n val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(\n TLPermissions.NtoB -> false.B,\n TLPermissions.NtoT -> true.B,\n TLPermissions.BtoT -> true.B))\n MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(\n TLMessages.PutFullData -> true.B,\n TLMessages.PutPartialData -> true.B,\n TLMessages.ArithmeticData -> true.B,\n TLMessages.LogicalData -> true.B,\n TLMessages.Get -> false.B,\n TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(\n TLHints.PREFETCH_READ -> false.B,\n TLHints.PREFETCH_WRITE -> true.B)),\n TLMessages.AcquireBlock -> acq_needT,\n TLMessages.AcquirePerm -> acq_needT))\n }\n\n // This is a very expensive circuit; use only if you really mean it!\n def inFlight(x: TLBundle): (UInt, UInt) = {\n val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))\n val bce = manager.anySupportAcquireB && client.anySupportProbe\n\n val (a_first, a_last, _) = firstlast(x.a)\n val (b_first, b_last, _) = firstlast(x.b)\n val (c_first, c_last, _) = firstlast(x.c)\n val (d_first, d_last, _) = firstlast(x.d)\n val (e_first, e_last, _) = firstlast(x.e)\n\n val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))\n val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))\n val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))\n val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))\n val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))\n\n val a_inc = x.a.fire && a_first && a_request\n val b_inc = x.b.fire && b_first && b_request\n val c_inc = x.c.fire && c_first && c_request\n val d_inc = x.d.fire && d_first && d_request\n val e_inc = x.e.fire && e_first && e_request\n val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))\n\n val a_dec = x.a.fire && a_last && a_response\n val b_dec = x.b.fire && b_last && b_response\n val c_dec = x.c.fire && c_last && c_response\n val d_dec = x.d.fire && d_last && d_response\n val e_dec = x.e.fire && e_last && e_response\n val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))\n\n val next_flight = flight + PopCount(inc) - PopCount(dec)\n flight := next_flight\n\n (flight, next_flight)\n }\n\n def prettySourceMapping(context: String): String = {\n s\"TL-Source mapping for $context:\\n${(new TLSourceIdMap(client)).pretty}\\n\"\n }\n}\n\nclass TLEdgeOut(\n client: TLClientPortParameters,\n manager: TLManagerPortParameters,\n params: Parameters,\n sourceInfo: SourceInfo)\n extends TLEdge(client, manager, params, sourceInfo)\n{\n // Transfers\n def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {\n require (manager.anySupportAcquireB, s\"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsAcquireBFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.AcquireBlock\n a.param := growPermissions\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := DontCare\n a.corrupt := false.B\n (legal, a)\n }\n\n def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {\n require (manager.anySupportAcquireB, s\"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsAcquireBFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.AcquirePerm\n a.param := growPermissions\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := DontCare\n a.corrupt := false.B\n (legal, a)\n }\n\n def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {\n require (manager.anySupportAcquireB, s\"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsAcquireBFast(toAddress, lgSize)\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.Release\n c.param := shrinkPermissions\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := DontCare\n c.corrupt := false.B\n (legal, c)\n }\n\n def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {\n require (manager.anySupportAcquireB, s\"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsAcquireBFast(toAddress, lgSize)\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.ReleaseData\n c.param := shrinkPermissions\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := data\n c.corrupt := corrupt\n (legal, c)\n }\n\n def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =\n Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)\n\n def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =\n ProbeAck(b.source, b.address, b.size, reportPermissions)\n\n def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.ProbeAck\n c.param := reportPermissions\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := DontCare\n c.corrupt := false.B\n c\n }\n\n def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =\n ProbeAck(b.source, b.address, b.size, reportPermissions, data)\n\n def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.ProbeAckData\n c.param := reportPermissions\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := data\n c.corrupt := corrupt\n c\n }\n\n def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =\n ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)\n\n def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)\n def GrantAck(toSink: UInt): TLBundleE = {\n val e = Wire(new TLBundleE(bundle))\n e.sink := toSink\n e\n }\n\n // Accesses\n def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {\n require (manager.anySupportGet, s\"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsGetFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.Get\n a.param := 0.U\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := DontCare\n a.corrupt := false.B\n (legal, a)\n }\n\n def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =\n Put(fromSource, toAddress, lgSize, data, false.B)\n\n def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {\n require (manager.anySupportPutFull, s\"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsPutFullFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.PutFullData\n a.param := 0.U\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := data\n a.corrupt := corrupt\n (legal, a)\n }\n\n def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =\n Put(fromSource, toAddress, lgSize, data, mask, false.B)\n\n def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {\n require (manager.anySupportPutPartial, s\"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsPutPartialFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.PutPartialData\n a.param := 0.U\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask\n a.data := data\n a.corrupt := corrupt\n (legal, a)\n }\n\n def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {\n require (manager.anySupportArithmetic, s\"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsArithmeticFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.ArithmeticData\n a.param := atomic\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := data\n a.corrupt := corrupt\n (legal, a)\n }\n\n def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {\n require (manager.anySupportLogical, s\"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsLogicalFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.LogicalData\n a.param := atomic\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := data\n a.corrupt := corrupt\n (legal, a)\n }\n\n def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {\n require (manager.anySupportHint, s\"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsHintFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.Hint\n a.param := param\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := DontCare\n a.corrupt := false.B\n (legal, a)\n }\n\n def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)\n def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.AccessAck\n c.param := 0.U\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := DontCare\n c.corrupt := false.B\n c\n }\n\n def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)\n def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)\n def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)\n def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.AccessAckData\n c.param := 0.U\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := data\n c.corrupt := corrupt\n c\n }\n\n def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)\n def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.HintAck\n c.param := 0.U\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := DontCare\n c.corrupt := false.B\n c\n }\n}\n\nclass TLEdgeIn(\n client: TLClientPortParameters,\n manager: TLManagerPortParameters,\n params: Parameters,\n sourceInfo: SourceInfo)\n extends TLEdge(client, manager, params, sourceInfo)\n{\n private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {\n val todo = x.filter(!_.isEmpty)\n val heads = todo.map(_.head)\n val tails = todo.map(_.tail)\n if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }\n }\n\n // Transfers\n def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {\n require (client.anySupportProbe, s\"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}\")\n val legal = client.supportsProbe(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.Probe\n b.param := capPermissions\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask(fromAddress, lgSize)\n b.data := DontCare\n b.corrupt := false.B\n (legal, b)\n }\n\n def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)\n def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {\n val d = Wire(new TLBundleD(bundle))\n d.opcode := TLMessages.Grant\n d.param := capPermissions\n d.size := lgSize\n d.source := toSource\n d.sink := fromSink\n d.denied := denied\n d.user := DontCare\n d.echo := DontCare\n d.data := DontCare\n d.corrupt := false.B\n d\n }\n\n def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)\n def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {\n val d = Wire(new TLBundleD(bundle))\n d.opcode := TLMessages.GrantData\n d.param := capPermissions\n d.size := lgSize\n d.source := toSource\n d.sink := fromSink\n d.denied := denied\n d.user := DontCare\n d.echo := DontCare\n d.data := data\n d.corrupt := corrupt\n d\n }\n\n def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)\n def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {\n val d = Wire(new TLBundleD(bundle))\n d.opcode := TLMessages.ReleaseAck\n d.param := 0.U\n d.size := lgSize\n d.source := toSource\n d.sink := 0.U\n d.denied := denied\n d.user := DontCare\n d.echo := DontCare\n d.data := DontCare\n d.corrupt := false.B\n d\n }\n\n // Accesses\n def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {\n require (client.anySupportGet, s\"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}\")\n val legal = client.supportsGet(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.Get\n b.param := 0.U\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask(fromAddress, lgSize)\n b.data := DontCare\n b.corrupt := false.B\n (legal, b)\n }\n\n def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =\n Put(fromAddress, toSource, lgSize, data, false.B)\n\n def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {\n require (client.anySupportPutFull, s\"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}\")\n val legal = client.supportsPutFull(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.PutFullData\n b.param := 0.U\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask(fromAddress, lgSize)\n b.data := data\n b.corrupt := corrupt\n (legal, b)\n }\n\n def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =\n Put(fromAddress, toSource, lgSize, data, mask, false.B)\n\n def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {\n require (client.anySupportPutPartial, s\"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}\")\n val legal = client.supportsPutPartial(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.PutPartialData\n b.param := 0.U\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask\n b.data := data\n b.corrupt := corrupt\n (legal, b)\n }\n\n def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {\n require (client.anySupportArithmetic, s\"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}\")\n val legal = client.supportsArithmetic(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.ArithmeticData\n b.param := atomic\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask(fromAddress, lgSize)\n b.data := data\n b.corrupt := corrupt\n (legal, b)\n }\n\n def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {\n require (client.anySupportLogical, s\"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}\")\n val legal = client.supportsLogical(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.LogicalData\n b.param := atomic\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask(fromAddress, lgSize)\n b.data := data\n b.corrupt := corrupt\n (legal, b)\n }\n\n def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {\n require (client.anySupportHint, s\"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}\")\n val legal = client.supportsHint(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.Hint\n b.param := param\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask(fromAddress, lgSize)\n b.data := DontCare\n b.corrupt := false.B\n (legal, b)\n }\n\n def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)\n def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)\n def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)\n def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {\n val d = Wire(new TLBundleD(bundle))\n d.opcode := TLMessages.AccessAck\n d.param := 0.U\n d.size := lgSize\n d.source := toSource\n d.sink := 0.U\n d.denied := denied\n d.user := DontCare\n d.echo := DontCare\n d.data := DontCare\n d.corrupt := false.B\n d\n }\n\n def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)\n def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)\n def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)\n def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {\n val d = Wire(new TLBundleD(bundle))\n d.opcode := TLMessages.AccessAckData\n d.param := 0.U\n d.size := lgSize\n d.source := toSource\n d.sink := 0.U\n d.denied := denied\n d.user := DontCare\n d.echo := DontCare\n d.data := data\n d.corrupt := corrupt\n d\n }\n\n def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)\n def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)\n def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)\n def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {\n val d = Wire(new TLBundleD(bundle))\n d.opcode := TLMessages.HintAck\n d.param := 0.U\n d.size := lgSize\n d.source := toSource\n d.sink := 0.U\n d.denied := denied\n d.user := DontCare\n d.echo := DontCare\n d.data := DontCare\n d.corrupt := false.B\n d\n }\n}\n"},"response":{"kind":"string","value":"module TLMonitor_27(\t// @[Monitor.scala:36:7]\n input clock,\t// @[Monitor.scala:36:7]\n input reset,\t// @[Monitor.scala:36:7]\n input io_in_a_ready,\t// @[Monitor.scala:20:14]\n input io_in_a_valid,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_a_bits_opcode,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_a_bits_param,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_a_bits_size,\t// @[Monitor.scala:20:14]\n input [8:0] io_in_a_bits_source,\t// @[Monitor.scala:20:14]\n input [20:0] io_in_a_bits_address,\t// @[Monitor.scala:20:14]\n input [7:0] io_in_a_bits_mask,\t// @[Monitor.scala:20:14]\n input [63:0] io_in_a_bits_data,\t// @[Monitor.scala:20:14]\n input io_in_a_bits_corrupt,\t// @[Monitor.scala:20:14]\n input io_in_d_ready,\t// @[Monitor.scala:20:14]\n input io_in_d_valid,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_d_bits_opcode,\t// @[Monitor.scala:20:14]\n input [1:0] io_in_d_bits_param,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_d_bits_size,\t// @[Monitor.scala:20:14]\n input [8:0] io_in_d_bits_source,\t// @[Monitor.scala:20:14]\n input io_in_d_bits_sink,\t// @[Monitor.scala:20:14]\n input io_in_d_bits_denied,\t// @[Monitor.scala:20:14]\n input [63:0] io_in_d_bits_data,\t// @[Monitor.scala:20:14]\n input io_in_d_bits_corrupt\t// @[Monitor.scala:20:14]\n);\n\n wire [31:0] _plusarg_reader_1_out;\t// @[PlusArg.scala:80:11]\n wire [31:0] _plusarg_reader_out;\t// @[PlusArg.scala:80:11]\n wire io_in_a_ready_0 = io_in_a_ready;\t// @[Monitor.scala:36:7]\n wire io_in_a_valid_0 = io_in_a_valid;\t// @[Monitor.scala:36:7]\n wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode;\t// @[Monitor.scala:36:7]\n wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param;\t// @[Monitor.scala:36:7]\n wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size;\t// @[Monitor.scala:36:7]\n wire [8:0] io_in_a_bits_source_0 = io_in_a_bits_source;\t// @[Monitor.scala:36:7]\n wire [20:0] io_in_a_bits_address_0 = io_in_a_bits_address;\t// @[Monitor.scala:36:7]\n wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask;\t// @[Monitor.scala:36:7]\n wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data;\t// @[Monitor.scala:36:7]\n wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt;\t// @[Monitor.scala:36:7]\n wire io_in_d_ready_0 = io_in_d_ready;\t// @[Monitor.scala:36:7]\n wire io_in_d_valid_0 = io_in_d_valid;\t// @[Monitor.scala:36:7]\n wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode;\t// @[Monitor.scala:36:7]\n wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param;\t// @[Monitor.scala:36:7]\n wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size;\t// @[Monitor.scala:36:7]\n wire [8:0] io_in_d_bits_source_0 = io_in_d_bits_source;\t// @[Monitor.scala:36:7]\n wire io_in_d_bits_sink_0 = io_in_d_bits_sink;\t// @[Monitor.scala:36:7]\n wire io_in_d_bits_denied_0 = io_in_d_bits_denied;\t// @[Monitor.scala:36:7]\n wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data;\t// @[Monitor.scala:36:7]\n wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt;\t// @[Monitor.scala:36:7]\n wire sink_ok = 1'h0;\t// @[Monitor.scala:309:31]\n wire _c_first_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_2_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_2_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_2_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_3_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_3_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_3_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_T = 1'h0;\t// @[Decoupled.scala:51:35]\n wire c_first_beats1_opdata = 1'h0;\t// @[Edges.scala:102:36]\n wire _c_first_last_T = 1'h0;\t// @[Edges.scala:232:25]\n wire c_first_done = 1'h0;\t// @[Edges.scala:233:22]\n wire _c_set_wo_ready_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_wo_ready_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_wo_ready_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_wo_ready_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_interm_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_interm_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_interm_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_interm_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_interm_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_interm_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_T = 1'h0;\t// @[Monitor.scala:772:47]\n wire _c_probe_ack_WIRE_2_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_2_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_3_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_3_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_T_1 = 1'h0;\t// @[Monitor.scala:772:95]\n wire c_probe_ack = 1'h0;\t// @[Monitor.scala:772:71]\n wire _same_cycle_resp_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_T_3 = 1'h0;\t// @[Monitor.scala:795:44]\n wire _same_cycle_resp_WIRE_2_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_2_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_3_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_3_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_T_4 = 1'h0;\t// @[Edges.scala:68:36]\n wire _same_cycle_resp_T_5 = 1'h0;\t// @[Edges.scala:68:51]\n wire _same_cycle_resp_T_6 = 1'h0;\t// @[Edges.scala:68:40]\n wire _same_cycle_resp_T_7 = 1'h0;\t// @[Monitor.scala:795:55]\n wire _same_cycle_resp_WIRE_4_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_4_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_5_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_5_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire same_cycle_resp_1 = 1'h0;\t// @[Monitor.scala:795:88]\n wire [2:0] responseMap_0 = 3'h0;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMap_1 = 3'h0;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMapSecondOption_0 = 3'h0;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMapSecondOption_1 = 3'h0;\t// @[Monitor.scala:644:42]\n wire [2:0] _c_first_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_first_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_first_WIRE_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_first_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_first_WIRE_1_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_first_WIRE_2_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_first_WIRE_2_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_first_WIRE_3_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_first_WIRE_3_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] c_first_beats1_decode = 3'h0;\t// @[Edges.scala:220:59]\n wire [2:0] c_first_beats1 = 3'h0;\t// @[Edges.scala:221:14]\n wire [2:0] _c_first_count_T = 3'h0;\t// @[Edges.scala:234:27]\n wire [2:0] c_first_count = 3'h0;\t// @[Edges.scala:234:25]\n wire [2:0] _c_first_counter_T = 3'h0;\t// @[Edges.scala:236:21]\n wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_set_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_set_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_set_WIRE_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_set_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_set_WIRE_1_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire _source_ok_T_3 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _source_ok_T_5 = 1'h1;\t// @[Parameters.scala:57:20]\n wire _source_ok_T_9 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _source_ok_T_11 = 1'h1;\t// @[Parameters.scala:57:20]\n wire _source_ok_T_15 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _source_ok_T_17 = 1'h1;\t// @[Parameters.scala:57:20]\n wire _source_ok_T_21 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _source_ok_T_23 = 1'h1;\t// @[Parameters.scala:57:20]\n wire _source_ok_T_30 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _source_ok_T_32 = 1'h1;\t// @[Parameters.scala:57:20]\n wire _source_ok_T_46 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _source_ok_T_48 = 1'h1;\t// @[Parameters.scala:57:20]\n wire _source_ok_T_52 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _source_ok_T_54 = 1'h1;\t// @[Parameters.scala:57:20]\n wire _source_ok_T_58 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _source_ok_T_60 = 1'h1;\t// @[Parameters.scala:57:20]\n wire _source_ok_T_64 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _source_ok_T_66 = 1'h1;\t// @[Parameters.scala:57:20]\n wire _source_ok_T_73 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _source_ok_T_75 = 1'h1;\t// @[Parameters.scala:57:20]\n wire c_first = 1'h1;\t// @[Edges.scala:231:25]\n wire _c_first_last_T_1 = 1'h1;\t// @[Edges.scala:232:43]\n wire c_first_last = 1'h1;\t// @[Edges.scala:232:33]\n wire [2:0] c_first_counter1 = 3'h7;\t// @[Edges.scala:230:28]\n wire [3:0] _c_first_counter1_T = 4'hF;\t// @[Edges.scala:230:28]\n wire [63:0] _c_first_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_first_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_first_WIRE_2_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_first_WIRE_3_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_set_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_set_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [20:0] _c_first_WIRE_bits_address = 21'h0;\t// @[Bundles.scala:265:74]\n wire [20:0] _c_first_WIRE_1_bits_address = 21'h0;\t// @[Bundles.scala:265:61]\n wire [20:0] _c_first_WIRE_2_bits_address = 21'h0;\t// @[Bundles.scala:265:74]\n wire [20:0] _c_first_WIRE_3_bits_address = 21'h0;\t// @[Bundles.scala:265:61]\n wire [20:0] _c_set_wo_ready_WIRE_bits_address = 21'h0;\t// @[Bundles.scala:265:74]\n wire [20:0] _c_set_wo_ready_WIRE_1_bits_address = 21'h0;\t// @[Bundles.scala:265:61]\n wire [20:0] _c_set_WIRE_bits_address = 21'h0;\t// @[Bundles.scala:265:74]\n wire [20:0] _c_set_WIRE_1_bits_address = 21'h0;\t// @[Bundles.scala:265:61]\n wire [20:0] _c_opcodes_set_interm_WIRE_bits_address = 21'h0;\t// @[Bundles.scala:265:74]\n wire [20:0] _c_opcodes_set_interm_WIRE_1_bits_address = 21'h0;\t// @[Bundles.scala:265:61]\n wire [20:0] _c_sizes_set_interm_WIRE_bits_address = 21'h0;\t// @[Bundles.scala:265:74]\n wire [20:0] _c_sizes_set_interm_WIRE_1_bits_address = 21'h0;\t// @[Bundles.scala:265:61]\n wire [20:0] _c_opcodes_set_WIRE_bits_address = 21'h0;\t// @[Bundles.scala:265:74]\n wire [20:0] _c_opcodes_set_WIRE_1_bits_address = 21'h0;\t// @[Bundles.scala:265:61]\n wire [20:0] _c_sizes_set_WIRE_bits_address = 21'h0;\t// @[Bundles.scala:265:74]\n wire [20:0] _c_sizes_set_WIRE_1_bits_address = 21'h0;\t// @[Bundles.scala:265:61]\n wire [20:0] _c_probe_ack_WIRE_bits_address = 21'h0;\t// @[Bundles.scala:265:74]\n wire [20:0] _c_probe_ack_WIRE_1_bits_address = 21'h0;\t// @[Bundles.scala:265:61]\n wire [20:0] _c_probe_ack_WIRE_2_bits_address = 21'h0;\t// @[Bundles.scala:265:74]\n wire [20:0] _c_probe_ack_WIRE_3_bits_address = 21'h0;\t// @[Bundles.scala:265:61]\n wire [20:0] _same_cycle_resp_WIRE_bits_address = 21'h0;\t// @[Bundles.scala:265:74]\n wire [20:0] _same_cycle_resp_WIRE_1_bits_address = 21'h0;\t// @[Bundles.scala:265:61]\n wire [20:0] _same_cycle_resp_WIRE_2_bits_address = 21'h0;\t// @[Bundles.scala:265:74]\n wire [20:0] _same_cycle_resp_WIRE_3_bits_address = 21'h0;\t// @[Bundles.scala:265:61]\n wire [20:0] _same_cycle_resp_WIRE_4_bits_address = 21'h0;\t// @[Bundles.scala:265:74]\n wire [20:0] _same_cycle_resp_WIRE_5_bits_address = 21'h0;\t// @[Bundles.scala:265:61]\n wire [8:0] _c_first_WIRE_bits_source = 9'h0;\t// @[Bundles.scala:265:74]\n wire [8:0] _c_first_WIRE_1_bits_source = 9'h0;\t// @[Bundles.scala:265:61]\n wire [8:0] _c_first_WIRE_2_bits_source = 9'h0;\t// @[Bundles.scala:265:74]\n wire [8:0] _c_first_WIRE_3_bits_source = 9'h0;\t// @[Bundles.scala:265:61]\n wire [8:0] _c_set_wo_ready_WIRE_bits_source = 9'h0;\t// @[Bundles.scala:265:74]\n wire [8:0] _c_set_wo_ready_WIRE_1_bits_source = 9'h0;\t// @[Bundles.scala:265:61]\n wire [8:0] _c_set_WIRE_bits_source = 9'h0;\t// @[Bundles.scala:265:74]\n wire [8:0] _c_set_WIRE_1_bits_source = 9'h0;\t// @[Bundles.scala:265:61]\n wire [8:0] _c_opcodes_set_interm_WIRE_bits_source = 9'h0;\t// @[Bundles.scala:265:74]\n wire [8:0] _c_opcodes_set_interm_WIRE_1_bits_source = 9'h0;\t// @[Bundles.scala:265:61]\n wire [8:0] _c_sizes_set_interm_WIRE_bits_source = 9'h0;\t// @[Bundles.scala:265:74]\n wire [8:0] _c_sizes_set_interm_WIRE_1_bits_source = 9'h0;\t// @[Bundles.scala:265:61]\n wire [8:0] _c_opcodes_set_WIRE_bits_source = 9'h0;\t// @[Bundles.scala:265:74]\n wire [8:0] _c_opcodes_set_WIRE_1_bits_source = 9'h0;\t// @[Bundles.scala:265:61]\n wire [8:0] _c_sizes_set_WIRE_bits_source = 9'h0;\t// @[Bundles.scala:265:74]\n wire [8:0] _c_sizes_set_WIRE_1_bits_source = 9'h0;\t// @[Bundles.scala:265:61]\n wire [8:0] _c_probe_ack_WIRE_bits_source = 9'h0;\t// @[Bundles.scala:265:74]\n wire [8:0] _c_probe_ack_WIRE_1_bits_source = 9'h0;\t// @[Bundles.scala:265:61]\n wire [8:0] _c_probe_ack_WIRE_2_bits_source = 9'h0;\t// @[Bundles.scala:265:74]\n wire [8:0] _c_probe_ack_WIRE_3_bits_source = 9'h0;\t// @[Bundles.scala:265:61]\n wire [8:0] _same_cycle_resp_WIRE_bits_source = 9'h0;\t// @[Bundles.scala:265:74]\n wire [8:0] _same_cycle_resp_WIRE_1_bits_source = 9'h0;\t// @[Bundles.scala:265:61]\n wire [8:0] _same_cycle_resp_WIRE_2_bits_source = 9'h0;\t// @[Bundles.scala:265:74]\n wire [8:0] _same_cycle_resp_WIRE_3_bits_source = 9'h0;\t// @[Bundles.scala:265:61]\n wire [8:0] _same_cycle_resp_WIRE_4_bits_source = 9'h0;\t// @[Bundles.scala:265:74]\n wire [8:0] _same_cycle_resp_WIRE_5_bits_source = 9'h0;\t// @[Bundles.scala:265:61]\n wire [15:0] _a_opcode_lookup_T_5 = 16'hF;\t// @[Monitor.scala:612:57]\n wire [15:0] _a_size_lookup_T_5 = 16'hF;\t// @[Monitor.scala:612:57]\n wire [15:0] _d_opcodes_clr_T_3 = 16'hF;\t// @[Monitor.scala:612:57]\n wire [15:0] _d_sizes_clr_T_3 = 16'hF;\t// @[Monitor.scala:612:57]\n wire [15:0] _c_opcode_lookup_T_5 = 16'hF;\t// @[Monitor.scala:724:57]\n wire [15:0] _c_size_lookup_T_5 = 16'hF;\t// @[Monitor.scala:724:57]\n wire [15:0] _d_opcodes_clr_T_9 = 16'hF;\t// @[Monitor.scala:724:57]\n wire [15:0] _d_sizes_clr_T_9 = 16'hF;\t// @[Monitor.scala:724:57]\n wire [16:0] _a_opcode_lookup_T_4 = 17'hF;\t// @[Monitor.scala:612:57]\n wire [16:0] _a_size_lookup_T_4 = 17'hF;\t// @[Monitor.scala:612:57]\n wire [16:0] _d_opcodes_clr_T_2 = 17'hF;\t// @[Monitor.scala:612:57]\n wire [16:0] _d_sizes_clr_T_2 = 17'hF;\t// @[Monitor.scala:612:57]\n wire [16:0] _c_opcode_lookup_T_4 = 17'hF;\t// @[Monitor.scala:724:57]\n wire [16:0] _c_size_lookup_T_4 = 17'hF;\t// @[Monitor.scala:724:57]\n wire [16:0] _d_opcodes_clr_T_8 = 17'hF;\t// @[Monitor.scala:724:57]\n wire [16:0] _d_sizes_clr_T_8 = 17'hF;\t// @[Monitor.scala:724:57]\n wire [15:0] _a_opcode_lookup_T_3 = 16'h10;\t// @[Monitor.scala:612:51]\n wire [15:0] _a_size_lookup_T_3 = 16'h10;\t// @[Monitor.scala:612:51]\n wire [15:0] _d_opcodes_clr_T_1 = 16'h10;\t// @[Monitor.scala:612:51]\n wire [15:0] _d_sizes_clr_T_1 = 16'h10;\t// @[Monitor.scala:612:51]\n wire [15:0] _c_opcode_lookup_T_3 = 16'h10;\t// @[Monitor.scala:724:51]\n wire [15:0] _c_size_lookup_T_3 = 16'h10;\t// @[Monitor.scala:724:51]\n wire [15:0] _d_opcodes_clr_T_7 = 16'h10;\t// @[Monitor.scala:724:51]\n wire [15:0] _d_sizes_clr_T_7 = 16'h10;\t// @[Monitor.scala:724:51]\n wire [4098:0] _c_opcodes_set_T_1 = 4099'h0;\t// @[Monitor.scala:767:54]\n wire [4098:0] _c_sizes_set_T_1 = 4099'h0;\t// @[Monitor.scala:768:52]\n wire [11:0] _c_opcodes_set_T = 12'h0;\t// @[Monitor.scala:767:79]\n wire [11:0] _c_sizes_set_T = 12'h0;\t// @[Monitor.scala:768:77]\n wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1;\t// @[Monitor.scala:765:61]\n wire [3:0] _c_sizes_set_interm_T_1 = 4'h1;\t// @[Monitor.scala:766:59]\n wire [3:0] c_opcodes_set_interm = 4'h0;\t// @[Monitor.scala:754:40]\n wire [3:0] c_sizes_set_interm = 4'h0;\t// @[Monitor.scala:755:40]\n wire [3:0] _c_opcodes_set_interm_T = 4'h0;\t// @[Monitor.scala:765:53]\n wire [3:0] _c_sizes_set_interm_T = 4'h0;\t// @[Monitor.scala:766:51]\n wire [511:0] _c_set_wo_ready_T = 512'h1;\t// @[OneHot.scala:58:35]\n wire [511:0] _c_set_T = 512'h1;\t// @[OneHot.scala:58:35]\n wire [1027:0] c_opcodes_set = 1028'h0;\t// @[Monitor.scala:740:34]\n wire [1027:0] c_sizes_set = 1028'h0;\t// @[Monitor.scala:741:34]\n wire [256:0] c_set = 257'h0;\t// @[Monitor.scala:738:34]\n wire [256:0] c_set_wo_ready = 257'h0;\t// @[Monitor.scala:739:34]\n wire [5:0] _c_first_beats1_decode_T_2 = 6'h0;\t// @[package.scala:243:46]\n wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F;\t// @[package.scala:243:76]\n wire [12:0] _c_first_beats1_decode_T = 13'h3F;\t// @[package.scala:243:71]\n wire [2:0] responseMap_6 = 3'h4;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMap_7 = 3'h4;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMapSecondOption_7 = 3'h4;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMapSecondOption_6 = 3'h5;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMap_5 = 3'h2;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMapSecondOption_5 = 3'h2;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMap_2 = 3'h1;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMap_3 = 3'h1;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMap_4 = 3'h1;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMapSecondOption_2 = 3'h1;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMapSecondOption_3 = 3'h1;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMapSecondOption_4 = 3'h1;\t// @[Monitor.scala:644:42]\n wire [3:0] _a_opcode_lookup_T_2 = 4'h4;\t// @[Monitor.scala:637:123]\n wire [3:0] _a_size_lookup_T_2 = 4'h4;\t// @[Monitor.scala:641:117]\n wire [3:0] _d_opcodes_clr_T = 4'h4;\t// @[Monitor.scala:680:48]\n wire [3:0] _d_sizes_clr_T = 4'h4;\t// @[Monitor.scala:681:48]\n wire [3:0] _c_opcode_lookup_T_2 = 4'h4;\t// @[Monitor.scala:749:123]\n wire [3:0] _c_size_lookup_T_2 = 4'h4;\t// @[Monitor.scala:750:119]\n wire [3:0] _d_opcodes_clr_T_6 = 4'h4;\t// @[Monitor.scala:790:48]\n wire [3:0] _d_sizes_clr_T_6 = 4'h4;\t// @[Monitor.scala:791:48]\n wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0;\t// @[Misc.scala:202:34]\n wire [8:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [8:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [8:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [8:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [8:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [8:0] _uncommonBits_T = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [8:0] _uncommonBits_T_1 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [8:0] _uncommonBits_T_2 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [8:0] _uncommonBits_T_3 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [8:0] _uncommonBits_T_4 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [8:0] _uncommonBits_T_5 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [8:0] _uncommonBits_T_6 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [8:0] _uncommonBits_T_7 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [8:0] _uncommonBits_T_8 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [8:0] _uncommonBits_T_9 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [8:0] _uncommonBits_T_10 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [8:0] _uncommonBits_T_11 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [8:0] _uncommonBits_T_12 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [8:0] _uncommonBits_T_13 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [8:0] _uncommonBits_T_14 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [8:0] _uncommonBits_T_15 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [8:0] _uncommonBits_T_16 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [8:0] _uncommonBits_T_17 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [8:0] _uncommonBits_T_18 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [8:0] _uncommonBits_T_19 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [8:0] _uncommonBits_T_20 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [8:0] _uncommonBits_T_21 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [8:0] _uncommonBits_T_22 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [8:0] _uncommonBits_T_23 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [8:0] _uncommonBits_T_24 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [8:0] _uncommonBits_T_25 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [8:0] _uncommonBits_T_26 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [8:0] _uncommonBits_T_27 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [8:0] _uncommonBits_T_28 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [8:0] _uncommonBits_T_29 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [8:0] _uncommonBits_T_30 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [8:0] _uncommonBits_T_31 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [8:0] _uncommonBits_T_32 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [8:0] _uncommonBits_T_33 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [8:0] _uncommonBits_T_34 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [8:0] _uncommonBits_T_35 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [8:0] _uncommonBits_T_36 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [8:0] _uncommonBits_T_37 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [8:0] _uncommonBits_T_38 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [8:0] _uncommonBits_T_39 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [8:0] _uncommonBits_T_40 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [8:0] _uncommonBits_T_41 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [8:0] _uncommonBits_T_42 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [8:0] _uncommonBits_T_43 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [8:0] _uncommonBits_T_44 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [8:0] _uncommonBits_T_45 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [8:0] _uncommonBits_T_46 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [8:0] _uncommonBits_T_47 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [8:0] _uncommonBits_T_48 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [8:0] _uncommonBits_T_49 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [8:0] _uncommonBits_T_50 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [8:0] _uncommonBits_T_51 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [8:0] _uncommonBits_T_52 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [8:0] _uncommonBits_T_53 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [8:0] _uncommonBits_T_54 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [8:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [8:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [8:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [8:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [8:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0;\t// @[Monitor.scala:36:7]\n wire _source_ok_T = io_in_a_bits_source_0 == 9'h90;\t// @[Monitor.scala:36:7]\n wire _source_ok_WIRE_0 = _source_ok_T;\t// @[Parameters.scala:1138:31]\n wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [6:0] _source_ok_T_1 = io_in_a_bits_source_0[8:2];\t// @[Monitor.scala:36:7]\n wire [6:0] _source_ok_T_7 = io_in_a_bits_source_0[8:2];\t// @[Monitor.scala:36:7]\n wire [6:0] _source_ok_T_13 = io_in_a_bits_source_0[8:2];\t// @[Monitor.scala:36:7]\n wire [6:0] _source_ok_T_19 = io_in_a_bits_source_0[8:2];\t// @[Monitor.scala:36:7]\n wire _source_ok_T_2 = _source_ok_T_1 == 7'h20;\t// @[Parameters.scala:54:{10,32}]\n wire _source_ok_T_4 = _source_ok_T_2;\t// @[Parameters.scala:54:{32,67}]\n wire _source_ok_T_6 = _source_ok_T_4;\t// @[Parameters.scala:54:67, :56:48]\n wire _source_ok_WIRE_1 = _source_ok_T_6;\t// @[Parameters.scala:1138:31]\n wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire _source_ok_T_8 = _source_ok_T_7 == 7'h21;\t// @[Parameters.scala:54:{10,32}]\n wire _source_ok_T_10 = _source_ok_T_8;\t// @[Parameters.scala:54:{32,67}]\n wire _source_ok_T_12 = _source_ok_T_10;\t// @[Parameters.scala:54:67, :56:48]\n wire _source_ok_WIRE_2 = _source_ok_T_12;\t// @[Parameters.scala:1138:31]\n wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire _source_ok_T_14 = _source_ok_T_13 == 7'h22;\t// @[Parameters.scala:54:{10,32}]\n wire _source_ok_T_16 = _source_ok_T_14;\t// @[Parameters.scala:54:{32,67}]\n wire _source_ok_T_18 = _source_ok_T_16;\t// @[Parameters.scala:54:67, :56:48]\n wire _source_ok_WIRE_3 = _source_ok_T_18;\t// @[Parameters.scala:1138:31]\n wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire _source_ok_T_20 = _source_ok_T_19 == 7'h23;\t// @[Parameters.scala:54:{10,32}]\n wire _source_ok_T_22 = _source_ok_T_20;\t// @[Parameters.scala:54:{32,67}]\n wire _source_ok_T_24 = _source_ok_T_22;\t// @[Parameters.scala:54:67, :56:48]\n wire _source_ok_WIRE_4 = _source_ok_T_24;\t// @[Parameters.scala:1138:31]\n wire _source_ok_T_25 = io_in_a_bits_source_0 == 9'h40;\t// @[Monitor.scala:36:7]\n wire _source_ok_WIRE_5 = _source_ok_T_25;\t// @[Parameters.scala:1138:31]\n wire _source_ok_T_26 = io_in_a_bits_source_0 == 9'h41;\t// @[Monitor.scala:36:7]\n wire _source_ok_WIRE_6 = _source_ok_T_26;\t// @[Parameters.scala:1138:31]\n wire _source_ok_T_27 = io_in_a_bits_source_0 == 9'h42;\t// @[Monitor.scala:36:7]\n wire _source_ok_WIRE_7 = _source_ok_T_27;\t// @[Parameters.scala:1138:31]\n wire [5:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[5:0];\t// @[Parameters.scala:52:{29,56}]\n wire [2:0] _source_ok_T_28 = io_in_a_bits_source_0[8:6];\t// @[Monitor.scala:36:7]\n wire _source_ok_T_29 = _source_ok_T_28 == 3'h0;\t// @[Parameters.scala:54:{10,32}]\n wire _source_ok_T_31 = _source_ok_T_29;\t// @[Parameters.scala:54:{32,67}]\n wire _source_ok_T_33 = _source_ok_T_31;\t// @[Parameters.scala:54:67, :56:48]\n wire _source_ok_WIRE_8 = _source_ok_T_33;\t// @[Parameters.scala:1138:31]\n wire _source_ok_T_34 = io_in_a_bits_source_0 == 9'h100;\t// @[Monitor.scala:36:7]\n wire _source_ok_WIRE_9 = _source_ok_T_34;\t// @[Parameters.scala:1138:31]\n wire _source_ok_T_35 = _source_ok_WIRE_0 | _source_ok_WIRE_1;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _source_ok_T_36 = _source_ok_T_35 | _source_ok_WIRE_2;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _source_ok_T_37 = _source_ok_T_36 | _source_ok_WIRE_3;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _source_ok_T_38 = _source_ok_T_37 | _source_ok_WIRE_4;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _source_ok_T_39 = _source_ok_T_38 | _source_ok_WIRE_5;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _source_ok_T_40 = _source_ok_T_39 | _source_ok_WIRE_6;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _source_ok_T_41 = _source_ok_T_40 | _source_ok_WIRE_7;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _source_ok_T_42 = _source_ok_T_41 | _source_ok_WIRE_8;\t// @[Parameters.scala:1138:31, :1139:46]\n wire source_ok = _source_ok_T_42 | _source_ok_WIRE_9;\t// @[Parameters.scala:1138:31, :1139:46]\n wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0;\t// @[package.scala:243:71]\n wire [12:0] _is_aligned_mask_T;\t// @[package.scala:243:71]\n assign _is_aligned_mask_T = _GEN;\t// @[package.scala:243:71]\n wire [12:0] _a_first_beats1_decode_T;\t// @[package.scala:243:71]\n assign _a_first_beats1_decode_T = _GEN;\t// @[package.scala:243:71]\n wire [12:0] _a_first_beats1_decode_T_3;\t// @[package.scala:243:71]\n assign _a_first_beats1_decode_T_3 = _GEN;\t// @[package.scala:243:71]\n wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0];\t// @[package.scala:243:{71,76}]\n wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1;\t// @[package.scala:243:{46,76}]\n wire [20:0] _is_aligned_T = {15'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask};\t// @[package.scala:243:46]\n wire is_aligned = _is_aligned_T == 21'h0;\t// @[Edges.scala:21:{16,24}]\n wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0];\t// @[OneHot.scala:64:49]\n wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount;\t// @[OneHot.scala:64:49, :65:12]\n wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0];\t// @[OneHot.scala:65:{12,27}]\n wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1};\t// @[OneHot.scala:65:27]\n wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2;\t// @[Misc.scala:206:21]\n wire mask_sub_sub_size = mask_sizeOH[2];\t// @[Misc.scala:202:81, :209:26]\n wire mask_sub_sub_bit = io_in_a_bits_address_0[2];\t// @[Misc.scala:210:26]\n wire mask_sub_sub_1_2 = mask_sub_sub_bit;\t// @[Misc.scala:210:26, :214:27]\n wire mask_sub_sub_nbit = ~mask_sub_sub_bit;\t// @[Misc.scala:210:26, :211:20]\n wire mask_sub_sub_0_2 = mask_sub_sub_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T;\t// @[Misc.scala:206:21, :215:{29,38}]\n wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1;\t// @[Misc.scala:206:21, :215:{29,38}]\n wire mask_sub_size = mask_sizeOH[1];\t// @[Misc.scala:202:81, :209:26]\n wire mask_sub_bit = io_in_a_bits_address_0[1];\t// @[Misc.scala:210:26]\n wire mask_sub_nbit = ~mask_sub_bit;\t// @[Misc.scala:210:26, :211:20]\n wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T;\t// @[Misc.scala:215:{29,38}]\n wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1;\t// @[Misc.scala:215:{29,38}]\n wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2;\t// @[Misc.scala:215:{29,38}]\n wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3;\t// @[Misc.scala:215:{29,38}]\n wire mask_size = mask_sizeOH[0];\t// @[Misc.scala:202:81, :209:26]\n wire mask_bit = io_in_a_bits_address_0[0];\t// @[Misc.scala:210:26]\n wire mask_nbit = ~mask_bit;\t// @[Misc.scala:210:26, :211:20]\n wire mask_eq = mask_sub_0_2 & mask_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_acc_T = mask_size & mask_eq;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc = mask_sub_0_1 | _mask_acc_T;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_1 = mask_sub_0_2 & mask_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_acc_T_1 = mask_size & mask_eq_1;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_2 = mask_sub_1_2 & mask_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_acc_T_2 = mask_size & mask_eq_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_3 = mask_sub_1_2 & mask_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_acc_T_3 = mask_size & mask_eq_3;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_4 = mask_sub_2_2 & mask_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_acc_T_4 = mask_size & mask_eq_4;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_5 = mask_sub_2_2 & mask_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_acc_T_5 = mask_size & mask_eq_5;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_6 = mask_sub_3_2 & mask_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_acc_T_6 = mask_size & mask_eq_6;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_7 = mask_sub_3_2 & mask_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_acc_T_7 = mask_size & mask_eq_7;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7;\t// @[Misc.scala:215:{29,38}]\n wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc};\t// @[Misc.scala:215:29, :222:10]\n wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2};\t// @[Misc.scala:215:29, :222:10]\n wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo};\t// @[Misc.scala:222:10]\n wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4};\t// @[Misc.scala:215:29, :222:10]\n wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6};\t// @[Misc.scala:215:29, :222:10]\n wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo};\t// @[Misc.scala:222:10]\n wire [7:0] mask = {mask_hi, mask_lo};\t// @[Misc.scala:222:10]\n wire [1:0] uncommonBits = _uncommonBits_T[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [5:0] uncommonBits_4 = _uncommonBits_T_4[5:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [5:0] uncommonBits_9 = _uncommonBits_T_9[5:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [5:0] uncommonBits_14 = _uncommonBits_T_14[5:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [5:0] uncommonBits_19 = _uncommonBits_T_19[5:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [5:0] uncommonBits_24 = _uncommonBits_T_24[5:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [5:0] uncommonBits_29 = _uncommonBits_T_29[5:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [5:0] uncommonBits_34 = _uncommonBits_T_34[5:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [5:0] uncommonBits_39 = _uncommonBits_T_39[5:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [5:0] uncommonBits_44 = _uncommonBits_T_44[5:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_46 = _uncommonBits_T_46[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_47 = _uncommonBits_T_47[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [5:0] uncommonBits_49 = _uncommonBits_T_49[5:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_52 = _uncommonBits_T_52[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_53 = _uncommonBits_T_53[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [5:0] uncommonBits_54 = _uncommonBits_T_54[5:0];\t// @[Parameters.scala:52:{29,56}]\n wire _source_ok_T_43 = io_in_d_bits_source_0 == 9'h90;\t// @[Monitor.scala:36:7]\n wire _source_ok_WIRE_1_0 = _source_ok_T_43;\t// @[Parameters.scala:1138:31]\n wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [6:0] _source_ok_T_44 = io_in_d_bits_source_0[8:2];\t// @[Monitor.scala:36:7]\n wire [6:0] _source_ok_T_50 = io_in_d_bits_source_0[8:2];\t// @[Monitor.scala:36:7]\n wire [6:0] _source_ok_T_56 = io_in_d_bits_source_0[8:2];\t// @[Monitor.scala:36:7]\n wire [6:0] _source_ok_T_62 = io_in_d_bits_source_0[8:2];\t// @[Monitor.scala:36:7]\n wire _source_ok_T_45 = _source_ok_T_44 == 7'h20;\t// @[Parameters.scala:54:{10,32}]\n wire _source_ok_T_47 = _source_ok_T_45;\t// @[Parameters.scala:54:{32,67}]\n wire _source_ok_T_49 = _source_ok_T_47;\t// @[Parameters.scala:54:67, :56:48]\n wire _source_ok_WIRE_1_1 = _source_ok_T_49;\t// @[Parameters.scala:1138:31]\n wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire _source_ok_T_51 = _source_ok_T_50 == 7'h21;\t// @[Parameters.scala:54:{10,32}]\n wire _source_ok_T_53 = _source_ok_T_51;\t// @[Parameters.scala:54:{32,67}]\n wire _source_ok_T_55 = _source_ok_T_53;\t// @[Parameters.scala:54:67, :56:48]\n wire _source_ok_WIRE_1_2 = _source_ok_T_55;\t// @[Parameters.scala:1138:31]\n wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire _source_ok_T_57 = _source_ok_T_56 == 7'h22;\t// @[Parameters.scala:54:{10,32}]\n wire _source_ok_T_59 = _source_ok_T_57;\t// @[Parameters.scala:54:{32,67}]\n wire _source_ok_T_61 = _source_ok_T_59;\t// @[Parameters.scala:54:67, :56:48]\n wire _source_ok_WIRE_1_3 = _source_ok_T_61;\t// @[Parameters.scala:1138:31]\n wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire _source_ok_T_63 = _source_ok_T_62 == 7'h23;\t// @[Parameters.scala:54:{10,32}]\n wire _source_ok_T_65 = _source_ok_T_63;\t// @[Parameters.scala:54:{32,67}]\n wire _source_ok_T_67 = _source_ok_T_65;\t// @[Parameters.scala:54:67, :56:48]\n wire _source_ok_WIRE_1_4 = _source_ok_T_67;\t// @[Parameters.scala:1138:31]\n wire _source_ok_T_68 = io_in_d_bits_source_0 == 9'h40;\t// @[Monitor.scala:36:7]\n wire _source_ok_WIRE_1_5 = _source_ok_T_68;\t// @[Parameters.scala:1138:31]\n wire _source_ok_T_69 = io_in_d_bits_source_0 == 9'h41;\t// @[Monitor.scala:36:7]\n wire _source_ok_WIRE_1_6 = _source_ok_T_69;\t// @[Parameters.scala:1138:31]\n wire _source_ok_T_70 = io_in_d_bits_source_0 == 9'h42;\t// @[Monitor.scala:36:7]\n wire _source_ok_WIRE_1_7 = _source_ok_T_70;\t// @[Parameters.scala:1138:31]\n wire [5:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[5:0];\t// @[Parameters.scala:52:{29,56}]\n wire [2:0] _source_ok_T_71 = io_in_d_bits_source_0[8:6];\t// @[Monitor.scala:36:7]\n wire _source_ok_T_72 = _source_ok_T_71 == 3'h0;\t// @[Parameters.scala:54:{10,32}]\n wire _source_ok_T_74 = _source_ok_T_72;\t// @[Parameters.scala:54:{32,67}]\n wire _source_ok_T_76 = _source_ok_T_74;\t// @[Parameters.scala:54:67, :56:48]\n wire _source_ok_WIRE_1_8 = _source_ok_T_76;\t// @[Parameters.scala:1138:31]\n wire _source_ok_T_77 = io_in_d_bits_source_0 == 9'h100;\t// @[Monitor.scala:36:7]\n wire _source_ok_WIRE_1_9 = _source_ok_T_77;\t// @[Parameters.scala:1138:31]\n wire _source_ok_T_78 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _source_ok_T_79 = _source_ok_T_78 | _source_ok_WIRE_1_2;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _source_ok_T_80 = _source_ok_T_79 | _source_ok_WIRE_1_3;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _source_ok_T_81 = _source_ok_T_80 | _source_ok_WIRE_1_4;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _source_ok_T_82 = _source_ok_T_81 | _source_ok_WIRE_1_5;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _source_ok_T_83 = _source_ok_T_82 | _source_ok_WIRE_1_6;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _source_ok_T_84 = _source_ok_T_83 | _source_ok_WIRE_1_7;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _source_ok_T_85 = _source_ok_T_84 | _source_ok_WIRE_1_8;\t// @[Parameters.scala:1138:31, :1139:46]\n wire source_ok_1 = _source_ok_T_85 | _source_ok_WIRE_1_9;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _T_1187 = io_in_a_ready_0 & io_in_a_valid_0;\t// @[Decoupled.scala:51:35]\n wire _a_first_T;\t// @[Decoupled.scala:51:35]\n assign _a_first_T = _T_1187;\t// @[Decoupled.scala:51:35]\n wire _a_first_T_1;\t// @[Decoupled.scala:51:35]\n assign _a_first_T_1 = _T_1187;\t// @[Decoupled.scala:51:35]\n wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0];\t// @[package.scala:243:{71,76}]\n wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1;\t// @[package.scala:243:{46,76}]\n wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3];\t// @[package.scala:243:46]\n wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2];\t// @[Monitor.scala:36:7]\n wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2];\t// @[Monitor.scala:36:7]\n wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T;\t// @[Edges.scala:92:{28,37}]\n wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0;\t// @[Edges.scala:92:28, :220:59, :221:14]\n reg [2:0] a_first_counter;\t// @[Edges.scala:229:27]\n wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1;\t// @[Edges.scala:229:27, :230:28]\n wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0];\t// @[Edges.scala:230:28]\n wire a_first = a_first_counter == 3'h0;\t// @[Edges.scala:229:27, :231:25]\n wire _a_first_last_T = a_first_counter == 3'h1;\t// @[Edges.scala:229:27, :232:25]\n wire _a_first_last_T_1 = a_first_beats1 == 3'h0;\t// @[Edges.scala:221:14, :232:43]\n wire a_first_last = _a_first_last_T | _a_first_last_T_1;\t// @[Edges.scala:232:{25,33,43}]\n wire a_first_done = a_first_last & _a_first_T;\t// @[Decoupled.scala:51:35]\n wire [2:0] _a_first_count_T = ~a_first_counter1;\t// @[Edges.scala:230:28, :234:27]\n wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T;\t// @[Edges.scala:221:14, :234:{25,27}]\n wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1;\t// @[Edges.scala:221:14, :230:28, :231:25, :236:21]\n reg [2:0] opcode;\t// @[Monitor.scala:387:22]\n reg [2:0] param;\t// @[Monitor.scala:388:22]\n reg [2:0] size;\t// @[Monitor.scala:389:22]\n reg [8:0] source;\t// @[Monitor.scala:390:22]\n reg [20:0] address;\t// @[Monitor.scala:391:22]\n wire _T_1260 = io_in_d_ready_0 & io_in_d_valid_0;\t// @[Decoupled.scala:51:35]\n wire _d_first_T;\t// @[Decoupled.scala:51:35]\n assign _d_first_T = _T_1260;\t// @[Decoupled.scala:51:35]\n wire _d_first_T_1;\t// @[Decoupled.scala:51:35]\n assign _d_first_T_1 = _T_1260;\t// @[Decoupled.scala:51:35]\n wire _d_first_T_2;\t// @[Decoupled.scala:51:35]\n assign _d_first_T_2 = _T_1260;\t// @[Decoupled.scala:51:35]\n wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0;\t// @[package.scala:243:71]\n wire [12:0] _d_first_beats1_decode_T;\t// @[package.scala:243:71]\n assign _d_first_beats1_decode_T = _GEN_0;\t// @[package.scala:243:71]\n wire [12:0] _d_first_beats1_decode_T_3;\t// @[package.scala:243:71]\n assign _d_first_beats1_decode_T_3 = _GEN_0;\t// @[package.scala:243:71]\n wire [12:0] _d_first_beats1_decode_T_6;\t// @[package.scala:243:71]\n assign _d_first_beats1_decode_T_6 = _GEN_0;\t// @[package.scala:243:71]\n wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0];\t// @[package.scala:243:{71,76}]\n wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1;\t// @[package.scala:243:{46,76}]\n wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3];\t// @[package.scala:243:46]\n wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0];\t// @[Monitor.scala:36:7]\n wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0];\t// @[Monitor.scala:36:7]\n wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0];\t// @[Monitor.scala:36:7]\n wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0;\t// @[Edges.scala:106:36, :220:59, :221:14]\n reg [2:0] d_first_counter;\t// @[Edges.scala:229:27]\n wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1;\t// @[Edges.scala:229:27, :230:28]\n wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0];\t// @[Edges.scala:230:28]\n wire d_first = d_first_counter == 3'h0;\t// @[Edges.scala:229:27, :231:25]\n wire _d_first_last_T = d_first_counter == 3'h1;\t// @[Edges.scala:229:27, :232:25]\n wire _d_first_last_T_1 = d_first_beats1 == 3'h0;\t// @[Edges.scala:221:14, :232:43]\n wire d_first_last = _d_first_last_T | _d_first_last_T_1;\t// @[Edges.scala:232:{25,33,43}]\n wire d_first_done = d_first_last & _d_first_T;\t// @[Decoupled.scala:51:35]\n wire [2:0] _d_first_count_T = ~d_first_counter1;\t// @[Edges.scala:230:28, :234:27]\n wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T;\t// @[Edges.scala:221:14, :234:{25,27}]\n wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1;\t// @[Edges.scala:221:14, :230:28, :231:25, :236:21]\n reg [2:0] opcode_1;\t// @[Monitor.scala:538:22]\n reg [1:0] param_1;\t// @[Monitor.scala:539:22]\n reg [2:0] size_1;\t// @[Monitor.scala:540:22]\n reg [8:0] source_1;\t// @[Monitor.scala:541:22]\n reg sink;\t// @[Monitor.scala:542:22]\n reg denied;\t// @[Monitor.scala:543:22]\n reg [256:0] inflight;\t// @[Monitor.scala:614:27]\n reg [1027:0] inflight_opcodes;\t// @[Monitor.scala:616:35]\n reg [1027:0] inflight_sizes;\t// @[Monitor.scala:618:33]\n wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0];\t// @[package.scala:243:{71,76}]\n wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4;\t// @[package.scala:243:{46,76}]\n wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3];\t// @[package.scala:243:46]\n wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1;\t// @[Edges.scala:92:{28,37}]\n wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0;\t// @[Edges.scala:92:28, :220:59, :221:14]\n reg [2:0] a_first_counter_1;\t// @[Edges.scala:229:27]\n wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1;\t// @[Edges.scala:229:27, :230:28]\n wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0];\t// @[Edges.scala:230:28]\n wire a_first_1 = a_first_counter_1 == 3'h0;\t// @[Edges.scala:229:27, :231:25]\n wire _a_first_last_T_2 = a_first_counter_1 == 3'h1;\t// @[Edges.scala:229:27, :232:25]\n wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0;\t// @[Edges.scala:221:14, :232:43]\n wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3;\t// @[Edges.scala:232:{25,33,43}]\n wire a_first_done_1 = a_first_last_1 & _a_first_T_1;\t// @[Decoupled.scala:51:35]\n wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1;\t// @[Edges.scala:230:28, :234:27]\n wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1;\t// @[Edges.scala:221:14, :234:{25,27}]\n wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1;\t// @[Edges.scala:221:14, :230:28, :231:25, :236:21]\n wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0];\t// @[package.scala:243:{71,76}]\n wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4;\t// @[package.scala:243:{46,76}]\n wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3];\t// @[package.scala:243:46]\n wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0;\t// @[Edges.scala:106:36, :220:59, :221:14]\n reg [2:0] d_first_counter_1;\t// @[Edges.scala:229:27]\n wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1;\t// @[Edges.scala:229:27, :230:28]\n wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0];\t// @[Edges.scala:230:28]\n wire d_first_1 = d_first_counter_1 == 3'h0;\t// @[Edges.scala:229:27, :231:25]\n wire _d_first_last_T_2 = d_first_counter_1 == 3'h1;\t// @[Edges.scala:229:27, :232:25]\n wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0;\t// @[Edges.scala:221:14, :232:43]\n wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3;\t// @[Edges.scala:232:{25,33,43}]\n wire d_first_done_1 = d_first_last_1 & _d_first_T_1;\t// @[Decoupled.scala:51:35]\n wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1;\t// @[Edges.scala:230:28, :234:27]\n wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1;\t// @[Edges.scala:221:14, :234:{25,27}]\n wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1;\t// @[Edges.scala:221:14, :230:28, :231:25, :236:21]\n wire [256:0] a_set;\t// @[Monitor.scala:626:34]\n wire [256:0] a_set_wo_ready;\t// @[Monitor.scala:627:34]\n wire [1027:0] a_opcodes_set;\t// @[Monitor.scala:630:33]\n wire [1027:0] a_sizes_set;\t// @[Monitor.scala:632:31]\n wire [2:0] a_opcode_lookup;\t// @[Monitor.scala:635:35]\n wire [11:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0};\t// @[Monitor.scala:36:7, :637:69]\n wire [11:0] _a_opcode_lookup_T;\t// @[Monitor.scala:637:69]\n assign _a_opcode_lookup_T = _GEN_1;\t// @[Monitor.scala:637:69]\n wire [11:0] _a_size_lookup_T;\t// @[Monitor.scala:641:65]\n assign _a_size_lookup_T = _GEN_1;\t// @[Monitor.scala:637:69, :641:65]\n wire [11:0] _d_opcodes_clr_T_4;\t// @[Monitor.scala:680:101]\n assign _d_opcodes_clr_T_4 = _GEN_1;\t// @[Monitor.scala:637:69, :680:101]\n wire [11:0] _d_sizes_clr_T_4;\t// @[Monitor.scala:681:99]\n assign _d_sizes_clr_T_4 = _GEN_1;\t// @[Monitor.scala:637:69, :681:99]\n wire [11:0] _c_opcode_lookup_T;\t// @[Monitor.scala:749:69]\n assign _c_opcode_lookup_T = _GEN_1;\t// @[Monitor.scala:637:69, :749:69]\n wire [11:0] _c_size_lookup_T;\t// @[Monitor.scala:750:67]\n assign _c_size_lookup_T = _GEN_1;\t// @[Monitor.scala:637:69, :750:67]\n wire [11:0] _d_opcodes_clr_T_10;\t// @[Monitor.scala:790:101]\n assign _d_opcodes_clr_T_10 = _GEN_1;\t// @[Monitor.scala:637:69, :790:101]\n wire [11:0] _d_sizes_clr_T_10;\t// @[Monitor.scala:791:99]\n assign _d_sizes_clr_T_10 = _GEN_1;\t// @[Monitor.scala:637:69, :791:99]\n wire [1027:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T;\t// @[Monitor.scala:616:35, :637:{44,69}]\n wire [1027:0] _a_opcode_lookup_T_6 = {1024'h0, _a_opcode_lookup_T_1[3:0]};\t// @[Monitor.scala:637:{44,97}]\n wire [1027:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[1027:1]};\t// @[Monitor.scala:637:{97,152}]\n assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0];\t// @[Monitor.scala:635:35, :637:{21,152}]\n wire [3:0] a_size_lookup;\t// @[Monitor.scala:639:33]\n wire [1027:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T;\t// @[Monitor.scala:618:33, :641:{40,65}]\n wire [1027:0] _a_size_lookup_T_6 = {1024'h0, _a_size_lookup_T_1[3:0]};\t// @[Monitor.scala:641:{40,91}]\n wire [1027:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[1027:1]};\t// @[Monitor.scala:641:{91,144}]\n assign a_size_lookup = _a_size_lookup_T_7[3:0];\t// @[Monitor.scala:639:33, :641:{19,144}]\n wire [3:0] a_opcodes_set_interm;\t// @[Monitor.scala:646:40]\n wire [3:0] a_sizes_set_interm;\t// @[Monitor.scala:648:38]\n wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1;\t// @[Monitor.scala:36:7, :651:26, :684:44]\n wire [511:0] _GEN_2 = 512'h1 << io_in_a_bits_source_0;\t// @[OneHot.scala:58:35]\n wire [511:0] _a_set_wo_ready_T;\t// @[OneHot.scala:58:35]\n assign _a_set_wo_ready_T = _GEN_2;\t// @[OneHot.scala:58:35]\n wire [511:0] _a_set_T;\t// @[OneHot.scala:58:35]\n assign _a_set_T = _GEN_2;\t// @[OneHot.scala:58:35]\n assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[256:0] : 257'h0;\t// @[OneHot.scala:58:35]\n wire _T_1113 = _T_1187 & a_first_1;\t// @[Decoupled.scala:51:35]\n assign a_set = _T_1113 ? _a_set_T[256:0] : 257'h0;\t// @[OneHot.scala:58:35]\n wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0};\t// @[Monitor.scala:36:7, :657:53]\n wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1};\t// @[Monitor.scala:657:{53,61}]\n assign a_opcodes_set_interm = _T_1113 ? _a_opcodes_set_interm_T_1 : 4'h0;\t// @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]\n wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0};\t// @[Monitor.scala:36:7, :658:51]\n wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1};\t// @[Monitor.scala:658:{51,59}]\n assign a_sizes_set_interm = _T_1113 ? _a_sizes_set_interm_T_1 : 4'h0;\t// @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]\n wire [11:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0};\t// @[Monitor.scala:36:7, :659:79]\n wire [11:0] _a_opcodes_set_T;\t// @[Monitor.scala:659:79]\n assign _a_opcodes_set_T = _GEN_3;\t// @[Monitor.scala:659:79]\n wire [11:0] _a_sizes_set_T;\t// @[Monitor.scala:660:77]\n assign _a_sizes_set_T = _GEN_3;\t// @[Monitor.scala:659:79, :660:77]\n wire [4098:0] _a_opcodes_set_T_1 = {4095'h0, a_opcodes_set_interm} << _a_opcodes_set_T;\t// @[Monitor.scala:646:40, :659:{54,79}]\n assign a_opcodes_set = _T_1113 ? _a_opcodes_set_T_1[1027:0] : 1028'h0;\t// @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]\n wire [4098:0] _a_sizes_set_T_1 = {4095'h0, a_sizes_set_interm} << _a_sizes_set_T;\t// @[Monitor.scala:648:38, :659:54, :660:{52,77}]\n assign a_sizes_set = _T_1113 ? _a_sizes_set_T_1[1027:0] : 1028'h0;\t// @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]\n wire [256:0] d_clr;\t// @[Monitor.scala:664:34]\n wire [256:0] d_clr_wo_ready;\t// @[Monitor.scala:665:34]\n wire [1027:0] d_opcodes_clr;\t// @[Monitor.scala:668:33]\n wire [1027:0] d_sizes_clr;\t// @[Monitor.scala:670:31]\n wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6;\t// @[Monitor.scala:36:7, :673:46]\n wire d_release_ack;\t// @[Monitor.scala:673:46]\n assign d_release_ack = _GEN_4;\t// @[Monitor.scala:673:46]\n wire d_release_ack_1;\t// @[Monitor.scala:783:46]\n assign d_release_ack_1 = _GEN_4;\t// @[Monitor.scala:673:46, :783:46]\n wire _T_1159 = io_in_d_valid_0 & d_first_1;\t// @[Monitor.scala:36:7, :674:26]\n wire [511:0] _GEN_5 = 512'h1 << io_in_d_bits_source_0;\t// @[OneHot.scala:58:35]\n wire [511:0] _d_clr_wo_ready_T;\t// @[OneHot.scala:58:35]\n assign _d_clr_wo_ready_T = _GEN_5;\t// @[OneHot.scala:58:35]\n wire [511:0] _d_clr_T;\t// @[OneHot.scala:58:35]\n assign _d_clr_T = _GEN_5;\t// @[OneHot.scala:58:35]\n wire [511:0] _d_clr_wo_ready_T_1;\t// @[OneHot.scala:58:35]\n assign _d_clr_wo_ready_T_1 = _GEN_5;\t// @[OneHot.scala:58:35]\n wire [511:0] _d_clr_T_1;\t// @[OneHot.scala:58:35]\n assign _d_clr_T_1 = _GEN_5;\t// @[OneHot.scala:58:35]\n assign d_clr_wo_ready = _T_1159 & ~d_release_ack ? _d_clr_wo_ready_T[256:0] : 257'h0;\t// @[OneHot.scala:58:35]\n wire _T_1128 = _T_1260 & d_first_1 & ~d_release_ack;\t// @[Decoupled.scala:51:35]\n assign d_clr = _T_1128 ? _d_clr_T[256:0] : 257'h0;\t// @[OneHot.scala:58:35]\n wire [4110:0] _d_opcodes_clr_T_5 = 4111'hF << _d_opcodes_clr_T_4;\t// @[Monitor.scala:680:{76,101}]\n assign d_opcodes_clr = _T_1128 ? _d_opcodes_clr_T_5[1027:0] : 1028'h0;\t// @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]\n wire [4110:0] _d_sizes_clr_T_5 = 4111'hF << _d_sizes_clr_T_4;\t// @[Monitor.scala:681:{74,99}]\n assign d_sizes_clr = _T_1128 ? _d_sizes_clr_T_5[1027:0] : 1028'h0;\t// @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]\n wire _same_cycle_resp_T_1 = _same_cycle_resp_T;\t// @[Monitor.scala:684:{44,55}]\n wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0;\t// @[Monitor.scala:36:7, :684:113]\n wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2;\t// @[Monitor.scala:684:{55,88,113}]\n wire [256:0] _inflight_T = inflight | a_set;\t// @[Monitor.scala:614:27, :626:34, :705:27]\n wire [256:0] _inflight_T_1 = ~d_clr;\t// @[Monitor.scala:664:34, :705:38]\n wire [256:0] _inflight_T_2 = _inflight_T & _inflight_T_1;\t// @[Monitor.scala:705:{27,36,38}]\n wire [1027:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set;\t// @[Monitor.scala:616:35, :630:33, :706:43]\n wire [1027:0] _inflight_opcodes_T_1 = ~d_opcodes_clr;\t// @[Monitor.scala:668:33, :706:62]\n wire [1027:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1;\t// @[Monitor.scala:706:{43,60,62}]\n wire [1027:0] _inflight_sizes_T = inflight_sizes | a_sizes_set;\t// @[Monitor.scala:618:33, :632:31, :707:39]\n wire [1027:0] _inflight_sizes_T_1 = ~d_sizes_clr;\t// @[Monitor.scala:670:31, :707:56]\n wire [1027:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1;\t// @[Monitor.scala:707:{39,54,56}]\n reg [31:0] watchdog;\t// @[Monitor.scala:709:27]\n wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1;\t// @[Monitor.scala:709:27, :714:26]\n wire [31:0] _watchdog_T_1 = _watchdog_T[31:0];\t// @[Monitor.scala:714:26]\n reg [256:0] inflight_1;\t// @[Monitor.scala:726:35]\n wire [256:0] _inflight_T_3 = inflight_1;\t// @[Monitor.scala:726:35, :814:35]\n reg [1027:0] inflight_opcodes_1;\t// @[Monitor.scala:727:35]\n wire [1027:0] _inflight_opcodes_T_3 = inflight_opcodes_1;\t// @[Monitor.scala:727:35, :815:43]\n reg [1027:0] inflight_sizes_1;\t// @[Monitor.scala:728:35]\n wire [1027:0] _inflight_sizes_T_3 = inflight_sizes_1;\t// @[Monitor.scala:728:35, :816:41]\n wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0];\t// @[package.scala:243:{71,76}]\n wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7;\t// @[package.scala:243:{46,76}]\n wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3];\t// @[package.scala:243:46]\n wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0;\t// @[Edges.scala:106:36, :220:59, :221:14]\n reg [2:0] d_first_counter_2;\t// @[Edges.scala:229:27]\n wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1;\t// @[Edges.scala:229:27, :230:28]\n wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0];\t// @[Edges.scala:230:28]\n wire d_first_2 = d_first_counter_2 == 3'h0;\t// @[Edges.scala:229:27, :231:25]\n wire _d_first_last_T_4 = d_first_counter_2 == 3'h1;\t// @[Edges.scala:229:27, :232:25]\n wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0;\t// @[Edges.scala:221:14, :232:43]\n wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5;\t// @[Edges.scala:232:{25,33,43}]\n wire d_first_done_2 = d_first_last_2 & _d_first_T_2;\t// @[Decoupled.scala:51:35]\n wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2;\t// @[Edges.scala:230:28, :234:27]\n wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2;\t// @[Edges.scala:221:14, :234:{25,27}]\n wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2;\t// @[Edges.scala:221:14, :230:28, :231:25, :236:21]\n wire [3:0] c_opcode_lookup;\t// @[Monitor.scala:747:35]\n wire [3:0] c_size_lookup;\t// @[Monitor.scala:748:35]\n wire [1027:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T;\t// @[Monitor.scala:727:35, :749:{44,69}]\n wire [1027:0] _c_opcode_lookup_T_6 = {1024'h0, _c_opcode_lookup_T_1[3:0]};\t// @[Monitor.scala:749:{44,97}]\n wire [1027:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[1027:1]};\t// @[Monitor.scala:749:{97,152}]\n assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0];\t// @[Monitor.scala:747:35, :749:{21,152}]\n wire [1027:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T;\t// @[Monitor.scala:728:35, :750:{42,67}]\n wire [1027:0] _c_size_lookup_T_6 = {1024'h0, _c_size_lookup_T_1[3:0]};\t// @[Monitor.scala:750:{42,93}]\n wire [1027:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[1027:1]};\t// @[Monitor.scala:750:{93,146}]\n assign c_size_lookup = _c_size_lookup_T_7[3:0];\t// @[Monitor.scala:748:35, :750:{21,146}]\n wire [256:0] d_clr_1;\t// @[Monitor.scala:774:34]\n wire [256:0] d_clr_wo_ready_1;\t// @[Monitor.scala:775:34]\n wire [1027:0] d_opcodes_clr_1;\t// @[Monitor.scala:776:34]\n wire [1027:0] d_sizes_clr_1;\t// @[Monitor.scala:777:34]\n wire _T_1231 = io_in_d_valid_0 & d_first_2;\t// @[Monitor.scala:36:7, :784:26]\n assign d_clr_wo_ready_1 = _T_1231 & d_release_ack_1 ? _d_clr_wo_ready_T_1[256:0] : 257'h0;\t// @[OneHot.scala:58:35]\n wire _T_1213 = _T_1260 & d_first_2 & d_release_ack_1;\t// @[Decoupled.scala:51:35]\n assign d_clr_1 = _T_1213 ? _d_clr_T_1[256:0] : 257'h0;\t// @[OneHot.scala:58:35]\n wire [4110:0] _d_opcodes_clr_T_11 = 4111'hF << _d_opcodes_clr_T_10;\t// @[Monitor.scala:790:{76,101}]\n assign d_opcodes_clr_1 = _T_1213 ? _d_opcodes_clr_T_11[1027:0] : 1028'h0;\t// @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]\n wire [4110:0] _d_sizes_clr_T_11 = 4111'hF << _d_sizes_clr_T_10;\t// @[Monitor.scala:791:{74,99}]\n assign d_sizes_clr_1 = _T_1213 ? _d_sizes_clr_T_11[1027:0] : 1028'h0;\t// @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]\n wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 9'h0;\t// @[Monitor.scala:36:7, :795:113]\n wire [256:0] _inflight_T_4 = ~d_clr_1;\t// @[Monitor.scala:774:34, :814:46]\n wire [256:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4;\t// @[Monitor.scala:814:{35,44,46}]\n wire [1027:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1;\t// @[Monitor.scala:776:34, :815:62]\n wire [1027:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4;\t// @[Monitor.scala:815:{43,60,62}]\n wire [1027:0] _inflight_sizes_T_4 = ~d_sizes_clr_1;\t// @[Monitor.scala:777:34, :816:58]\n wire [1027:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4;\t// @[Monitor.scala:816:{41,56,58}]\n reg [31:0] watchdog_1;\t// @[Monitor.scala:818:27]"}}}],"truncated":false,"partial":false},"paginationData":{"pageIndex":5,"numItemsPerPage":100,"numTotalItems":35529,"offset":500,"length":100}},"jwt":"eyJhbGciOiJFZERTQSJ9.eyJyZWFkIjp0cnVlLCJwZXJtaXNzaW9ucyI6eyJyZXBvLmNvbnRlbnQucmVhZCI6dHJ1ZX0sImlhdCI6MTc0NzExOTQzNSwic3ViIjoiL2RhdGFzZXRzL3J0bC1sbG0vY2hpc2VsLXZlcmlsb2ctcGFpcnMiLCJleHAiOjE3NDcxMjMwMzUsImlzcyI6Imh0dHBzOi8vaHVnZ2luZ2ZhY2UuY28ifQ.BvRQmoPPYs4OHQYG-LLIp_9X8zbFYHgQV9LP00UFzQQeiJQuw9hPg_6RXkWRR2U67TAA1lekHJAMZzRpkt6xCg","displayUrls":true},"discussionsStats":{"closed":0,"open":1,"total":1},"fullWidth":true,"hasGatedAccess":true,"hasFullAccess":true,"isEmbedded":false,"savedQueries":{"community":[],"user":[]}}">
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Generate the Verilog code corresponding to the following Chisel files.
File Tile.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
import Util._
/**
* A Tile is a purely combinational 2D array of passThrough PEs.
* a, b, s, and in_propag are broadcast across the entire array and are passed through to the Tile's outputs
* @param width The data width of each PE in bits
* @param rows Number of PEs on each row
* @param columns Number of PEs on each column
*/
class Tile[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, tree_reduction: Boolean, max_simultaneous_matmuls: Int, val rows: Int, val columns: Int)(implicit ev: Arithmetic[T]) extends Module {
val io = IO(new Bundle {
val in_a = Input(Vec(rows, inputType))
val in_b = Input(Vec(columns, outputType)) // This is the output of the tile next to it
val in_d = Input(Vec(columns, outputType))
val in_control = Input(Vec(columns, new PEControl(accType)))
val in_id = Input(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W)))
val in_last = Input(Vec(columns, Bool()))
val out_a = Output(Vec(rows, inputType))
val out_c = Output(Vec(columns, outputType))
val out_b = Output(Vec(columns, outputType))
val out_control = Output(Vec(columns, new PEControl(accType)))
val out_id = Output(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W)))
val out_last = Output(Vec(columns, Bool()))
val in_valid = Input(Vec(columns, Bool()))
val out_valid = Output(Vec(columns, Bool()))
val bad_dataflow = Output(Bool())
})
import ev._
val tile = Seq.fill(rows, columns)(Module(new PE(inputType, outputType, accType, df, max_simultaneous_matmuls)))
val tileT = tile.transpose
// TODO: abstract hori/vert broadcast, all these connections look the same
// Broadcast 'a' horizontally across the Tile
for (r <- 0 until rows) {
tile(r).foldLeft(io.in_a(r)) {
case (in_a, pe) =>
pe.io.in_a := in_a
pe.io.out_a
}
}
// Broadcast 'b' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_b(c)) {
case (in_b, pe) =>
pe.io.in_b := (if (tree_reduction) in_b.zero else in_b)
pe.io.out_b
}
}
// Broadcast 'd' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_d(c)) {
case (in_d, pe) =>
pe.io.in_d := in_d
pe.io.out_c
}
}
// Broadcast 'control' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_control(c)) {
case (in_ctrl, pe) =>
pe.io.in_control := in_ctrl
pe.io.out_control
}
}
// Broadcast 'garbage' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_valid(c)) {
case (v, pe) =>
pe.io.in_valid := v
pe.io.out_valid
}
}
// Broadcast 'id' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_id(c)) {
case (id, pe) =>
pe.io.in_id := id
pe.io.out_id
}
}
// Broadcast 'last' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_last(c)) {
case (last, pe) =>
pe.io.in_last := last
pe.io.out_last
}
}
// Drive the Tile's bottom IO
for (c <- 0 until columns) {
io.out_c(c) := tile(rows-1)(c).io.out_c
io.out_control(c) := tile(rows-1)(c).io.out_control
io.out_id(c) := tile(rows-1)(c).io.out_id
io.out_last(c) := tile(rows-1)(c).io.out_last
io.out_valid(c) := tile(rows-1)(c).io.out_valid
io.out_b(c) := {
if (tree_reduction) {
val prods = tileT(c).map(_.io.out_b)
accumulateTree(prods :+ io.in_b(c))
} else {
tile(rows - 1)(c).io.out_b
}
}
}
io.bad_dataflow := tile.map(_.map(_.io.bad_dataflow).reduce(_||_)).reduce(_||_)
// Drive the Tile's right IO
for (r <- 0 until rows) {
io.out_a(r) := tile(r)(columns-1).io.out_a
}
}
| module Tile_98( // @[Tile.scala:16:7]
input clock, // @[Tile.scala:16:7]
input reset, // @[Tile.scala:16:7]
input [7:0] io_in_a_0, // @[Tile.scala:17:14]
input [19:0] io_in_b_0, // @[Tile.scala:17:14]
input [19:0] io_in_d_0, // @[Tile.scala:17:14]
input io_in_control_0_dataflow, // @[Tile.scala:17:14]
input io_in_control_0_propagate, // @[Tile.scala:17:14]
input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14]
input [2:0] io_in_id_0, // @[Tile.scala:17:14]
input io_in_last_0, // @[Tile.scala:17:14]
output [7:0] io_out_a_0, // @[Tile.scala:17:14]
output [19:0] io_out_c_0, // @[Tile.scala:17:14]
output [19:0] io_out_b_0, // @[Tile.scala:17:14]
output io_out_control_0_dataflow, // @[Tile.scala:17:14]
output io_out_control_0_propagate, // @[Tile.scala:17:14]
output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14]
output [2:0] io_out_id_0, // @[Tile.scala:17:14]
output io_out_last_0, // @[Tile.scala:17:14]
input io_in_valid_0, // @[Tile.scala:17:14]
output io_out_valid_0, // @[Tile.scala:17:14]
output io_bad_dataflow // @[Tile.scala:17:14]
);
wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7]
wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7]
wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7]
wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7]
wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7]
wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7]
wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7]
wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7]
wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7]
wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7]
wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
wire io_out_control_0_propagate_0; // @[Tile.scala:16:7]
wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7]
wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7]
wire io_out_last_0_0; // @[Tile.scala:16:7]
wire io_out_valid_0_0; // @[Tile.scala:16:7]
wire io_bad_dataflow_0; // @[Tile.scala:16:7]
PE_354 tile_0_0 ( // @[Tile.scala:42:44]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0_0), // @[Tile.scala:16:7]
.io_in_b (io_in_b_0_0), // @[Tile.scala:16:7]
.io_in_d (io_in_d_0_0), // @[Tile.scala:16:7]
.io_out_a (io_out_a_0_0),
.io_out_b (io_out_b_0_0),
.io_out_c (io_out_c_0_0),
.io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7]
.io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7]
.io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7]
.io_out_control_dataflow (io_out_control_0_dataflow_0),
.io_out_control_propagate (io_out_control_0_propagate_0),
.io_out_control_shift (io_out_control_0_shift_0),
.io_in_id (io_in_id_0_0), // @[Tile.scala:16:7]
.io_out_id (io_out_id_0_0),
.io_in_last (io_in_last_0_0), // @[Tile.scala:16:7]
.io_out_last (io_out_last_0_0),
.io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7]
.io_out_valid (io_out_valid_0_0),
.io_bad_dataflow (io_bad_dataflow_0)
); // @[Tile.scala:42:44]
assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7]
assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7]
assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7]
assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7]
assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7]
assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7]
assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7]
assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7]
assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File util.scala:
//******************************************************************************
// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Utility Functions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v4.util
import chisel3._
import chisel3.util._
import freechips.rocketchip.rocket.Instructions._
import freechips.rocketchip.rocket._
import freechips.rocketchip.util.{Str}
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.tile.{TileKey}
import boom.v4.common.{MicroOp}
import boom.v4.exu.{BrUpdateInfo}
/**
* Object to XOR fold a input register of fullLength into a compressedLength.
*/
object Fold
{
def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = {
val clen = compressedLength
val hlen = fullLength
if (hlen <= clen) {
input
} else {
var res = 0.U(clen.W)
var remaining = input.asUInt
for (i <- 0 to hlen-1 by clen) {
val len = if (i + clen > hlen ) (hlen - i) else clen
require(len > 0)
res = res(clen-1,0) ^ remaining(len-1,0)
remaining = remaining >> len.U
}
res
}
}
}
/**
* Object to check if MicroOp was killed due to a branch mispredict.
* Uses "Fast" branch masks
*/
object IsKilledByBranch
{
def apply(brupdate: BrUpdateInfo, flush: Bool, uop: MicroOp): Bool = {
return apply(brupdate, flush, uop.br_mask)
}
def apply(brupdate: BrUpdateInfo, flush: Bool, uop_mask: UInt): Bool = {
return maskMatch(brupdate.b1.mispredict_mask, uop_mask) || flush
}
def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: T): Bool = {
return apply(brupdate, flush, bundle.uop)
}
def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Bool = {
return apply(brupdate, flush, bundle.bits)
}
}
/**
* Object to return new MicroOp with a new BR mask given a MicroOp mask
* and old BR mask.
*/
object GetNewUopAndBrMask
{
def apply(uop: MicroOp, brupdate: BrUpdateInfo)
(implicit p: Parameters): MicroOp = {
val newuop = WireInit(uop)
newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask
newuop
}
}
/**
* Object to return a BR mask given a MicroOp mask and old BR mask.
*/
object GetNewBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = {
return uop.br_mask & ~brupdate.b1.resolve_mask
}
def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = {
return br_mask & ~brupdate.b1.resolve_mask
}
}
object UpdateBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = {
val out = WireInit(uop)
out.br_mask := GetNewBrMask(brupdate, uop)
out
}
def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = {
val out = WireInit(bundle)
out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask)
out
}
def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Valid[T] = {
val out = WireInit(bundle)
out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask)
out.valid := bundle.valid && !IsKilledByBranch(brupdate, flush, bundle.bits.uop.br_mask)
out
}
}
/**
* Object to check if at least 1 bit matches in two masks
*/
object maskMatch
{
def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U
}
/**
* Object to clear one bit in a mask given an index
*/
object clearMaskBit
{
def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0)
}
/**
* Object to shift a register over by one bit and concat a new one
*/
object PerformShiftRegister
{
def apply(reg_val: UInt, new_bit: Bool): UInt = {
reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt
reg_val
}
}
/**
* Object to shift a register over by one bit, wrapping the top bit around to the bottom
* (XOR'ed with a new-bit), and evicting a bit at index HLEN.
* This is used to simulate a longer HLEN-width shift register that is folded
* down to a compressed CLEN.
*/
object PerformCircularShiftRegister
{
def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = {
val carry = csr(clen-1)
val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U)
newval
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapAdd
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, amt: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + amt)(log2Ceil(n)-1,0)
} else {
val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt)
Mux(sum >= n.U,
sum - n.U,
sum)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapSub
{
// "n" is the number of increments, so we wrap to n-1.
def apply(value: UInt, amt: Int, n: Int): UInt = {
if (isPow2(n)) {
(value - amt.U)(log2Ceil(n)-1,0)
} else {
val v = Cat(0.U(1.W), value)
val b = Cat(0.U(1.W), amt.U)
Mux(value >= amt.U,
value - amt.U,
n.U - amt.U + value)
}
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapInc
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === (n-1).U)
Mux(wrap, 0.U, value + 1.U)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapDec
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value - 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === 0.U)
Mux(wrap, (n-1).U, value - 1.U)
}
}
}
/**
* Object to mask off lower bits of a PC to align to a "b"
* Byte boundary.
*/
object AlignPCToBoundary
{
def apply(pc: UInt, b: Int): UInt = {
// Invert for scenario where pc longer than b
// (which would clear all bits above size(b)).
~(~pc | (b-1).U)
}
}
/**
* Object to rotate a signal left by one
*/
object RotateL1
{
def apply(signal: UInt): UInt = {
val w = signal.getWidth
val out = Cat(signal(w-2,0), signal(w-1))
return out
}
}
/**
* Object to sext a value to a particular length.
*/
object Sext
{
def apply(x: UInt, length: Int): UInt = {
if (x.getWidth == length) return x
else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x)
}
}
/**
* Object to translate from BOOM's special "packed immediate" to a 32b signed immediate
* Asking for U-type gives it shifted up 12 bits.
*/
object ImmGen
{
import boom.v4.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U, IS_N}
def apply(i: UInt, isel: UInt): UInt = {
val ip = Mux(isel === IS_N, 0.U(LONGEST_IMM_SZ.W), i)
val sign = ip(LONGEST_IMM_SZ-1).asSInt
val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign)
val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign)
val i11 = Mux(isel === IS_U, 0.S,
Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign))
val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt)
val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt)
val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S)
return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0)
}
}
/**
* Object to see if an instruction is a JALR.
*/
object DebugIsJALR
{
def apply(inst: UInt): Bool = {
// TODO Chisel not sure why this won't compile
// val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)),
// Array(
// JALR -> Bool(true)))
inst(6,0) === "b1100111".U
}
}
/**
* Object to take an instruction and output its branch or jal target. Only used
* for a debug assert (no where else would we jump straight from instruction
* bits to a target).
*/
object DebugGetBJImm
{
def apply(inst: UInt): UInt = {
// TODO Chisel not sure why this won't compile
//val csignals =
//rocket.DecodeLogic(inst,
// List(Bool(false), Bool(false)),
// Array(
// BEQ -> List(Bool(true ), Bool(false)),
// BNE -> List(Bool(true ), Bool(false)),
// BGE -> List(Bool(true ), Bool(false)),
// BGEU -> List(Bool(true ), Bool(false)),
// BLT -> List(Bool(true ), Bool(false)),
// BLTU -> List(Bool(true ), Bool(false))
// ))
//val is_br :: nothing :: Nil = csignals
val is_br = (inst(6,0) === "b1100011".U)
val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W))
val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W))
Mux(is_br, br_targ, jal_targ)
}
}
/**
* Object to return the lowest bit position after the head.
*/
object AgePriorityEncoder
{
def apply(in: Seq[Bool], head: UInt): UInt = {
val n = in.size
val width = log2Ceil(in.size)
val n_padded = 1 << width
val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in
val idx = PriorityEncoder(temp_vec)
idx(width-1, 0) //discard msb
}
}
/**
* Object to determine whether queue
* index i0 is older than index i1.
*/
object IsOlder
{
def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head))
}
object IsYoungerMask
{
def apply(i: UInt, head: UInt, n: Integer): UInt = {
val hi_mask = ~MaskLower(UIntToOH(i)(n-1,0))
val lo_mask = ~MaskUpper(UIntToOH(head)(n-1,0))
Mux(i < head, hi_mask & lo_mask, hi_mask | lo_mask)(n-1,0)
}
}
/**
* Set all bits at or below the highest order '1'.
*/
object MaskLower
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => in >> i.U).reduce(_|_)
}
}
/**
* Set all bits at or above the lowest order '1'.
*/
object MaskUpper
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_)
}
}
/**
* Transpose a matrix of Chisel Vecs.
*/
object Transpose
{
def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = {
val n = in(0).size
VecInit((0 until n).map(i => VecInit(in.map(row => row(i)))))
}
}
/**
* N-wide one-hot priority encoder.
*/
object SelectFirstN
{
def apply(in: UInt, n: Int) = {
val sels = Wire(Vec(n, UInt(in.getWidth.W)))
var mask = in
for (i <- 0 until n) {
sels(i) := PriorityEncoderOH(mask)
mask = mask & ~sels(i)
}
sels
}
}
/**
* Connect the first k of n valid input interfaces to k output interfaces.
*/
class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module
{
require(n >= k)
val io = IO(new Bundle {
val in = Vec(n, Flipped(DecoupledIO(gen)))
val out = Vec(k, DecoupledIO(gen))
})
if (n == k) {
io.out <> io.in
} else {
val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c))
val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col =>
(col zip io.in.map(_.valid)) map {case (c,v) => c && v})
val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_))
val out_valids = sels map (col => col.reduce(_||_))
val out_data = sels map (s => Mux1H(s, io.in.map(_.bits)))
in_readys zip io.in foreach {case (r,i) => i.ready := r}
out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d}
}
}
/**
* Create a queue that can be killed with a branch kill signal.
* Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq).
*/
class BranchKillableQueue[T <: boom.v4.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v4.common.MicroOp => Bool = u => true.B, fastDeq: Boolean = false)
(implicit p: org.chipsalliance.cde.config.Parameters)
extends boom.v4.common.BoomModule()(p)
with boom.v4.common.HasBoomCoreParameters
{
val io = IO(new Bundle {
val enq = Flipped(Decoupled(gen))
val deq = Decoupled(gen)
val brupdate = Input(new BrUpdateInfo())
val flush = Input(Bool())
val empty = Output(Bool())
val count = Output(UInt(log2Ceil(entries).W))
})
if (fastDeq && entries > 1) {
// Pipeline dequeue selection so the mux gets an entire cycle
val main = Module(new BranchKillableQueue(gen, entries-1, flush_fn, false))
val out_reg = Reg(gen)
val out_valid = RegInit(false.B)
val out_uop = Reg(new MicroOp)
main.io.enq <> io.enq
main.io.brupdate := io.brupdate
main.io.flush := io.flush
io.empty := main.io.empty && !out_valid
io.count := main.io.count + out_valid
io.deq.valid := out_valid
io.deq.bits := out_reg
io.deq.bits.uop := out_uop
out_uop := UpdateBrMask(io.brupdate, out_uop)
out_valid := out_valid && !IsKilledByBranch(io.brupdate, false.B, out_uop) && !(io.flush && flush_fn(out_uop))
main.io.deq.ready := false.B
when (io.deq.fire || !out_valid) {
out_valid := main.io.deq.valid && !IsKilledByBranch(io.brupdate, false.B, main.io.deq.bits.uop) && !(io.flush && flush_fn(main.io.deq.bits.uop))
out_reg := main.io.deq.bits
out_uop := UpdateBrMask(io.brupdate, main.io.deq.bits.uop)
main.io.deq.ready := true.B
}
} else {
val ram = Mem(entries, gen)
val valids = RegInit(VecInit(Seq.fill(entries) {false.B}))
val uops = Reg(Vec(entries, new MicroOp))
val enq_ptr = Counter(entries)
val deq_ptr = Counter(entries)
val maybe_full = RegInit(false.B)
val ptr_match = enq_ptr.value === deq_ptr.value
io.empty := ptr_match && !maybe_full
val full = ptr_match && maybe_full
val do_enq = WireInit(io.enq.fire && !IsKilledByBranch(io.brupdate, false.B, io.enq.bits.uop) && !(io.flush && flush_fn(io.enq.bits.uop)))
val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty)
for (i <- 0 until entries) {
val mask = uops(i).br_mask
val uop = uops(i)
valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, false.B, mask) && !(io.flush && flush_fn(uop))
when (valids(i)) {
uops(i).br_mask := GetNewBrMask(io.brupdate, mask)
}
}
when (do_enq) {
ram(enq_ptr.value) := io.enq.bits
valids(enq_ptr.value) := true.B
uops(enq_ptr.value) := io.enq.bits.uop
uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)
enq_ptr.inc()
}
when (do_deq) {
valids(deq_ptr.value) := false.B
deq_ptr.inc()
}
when (do_enq =/= do_deq) {
maybe_full := do_enq
}
io.enq.ready := !full
val out = Wire(gen)
out := ram(deq_ptr.value)
out.uop := uops(deq_ptr.value)
io.deq.valid := !io.empty && valids(deq_ptr.value)
io.deq.bits := out
val ptr_diff = enq_ptr.value - deq_ptr.value
if (isPow2(entries)) {
io.count := Cat(maybe_full && ptr_match, ptr_diff)
}
else {
io.count := Mux(ptr_match,
Mux(maybe_full,
entries.asUInt, 0.U),
Mux(deq_ptr.value > enq_ptr.value,
entries.asUInt + ptr_diff, ptr_diff))
}
}
}
// ------------------------------------------
// Printf helper functions
// ------------------------------------------
object BoolToChar
{
/**
* Take in a Chisel Bool and convert it into a Str
* based on the Chars given
*
* @param c_bool Chisel Bool
* @param trueChar Scala Char if bool is true
* @param falseChar Scala Char if bool is false
* @return UInt ASCII Char for "trueChar" or "falseChar"
*/
def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = {
Mux(c_bool, Str(trueChar), Str(falseChar))
}
}
object CfiTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param cfi_type specific cfi type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(cfi_type: UInt) = {
val strings = Seq("----", "BR ", "JAL ", "JALR")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(cfi_type)
}
}
object BpdTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param bpd_type specific bpd type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(bpd_type: UInt) = {
val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(bpd_type)
}
}
object RobTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param rob_type specific rob type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(rob_type: UInt) = {
val strings = Seq("RST", "NML", "RBK", " WT")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(rob_type)
}
}
object XRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param xreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(xreg: UInt) = {
val strings = Seq(" x0", " ra", " sp", " gp",
" tp", " t0", " t1", " t2",
" s0", " s1", " a0", " a1",
" a2", " a3", " a4", " a5",
" a6", " a7", " s2", " s3",
" s4", " s5", " s6", " s7",
" s8", " s9", "s10", "s11",
" t3", " t4", " t5", " t6")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(xreg)
}
}
object FPRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param fpreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(fpreg: UInt) = {
val strings = Seq(" ft0", " ft1", " ft2", " ft3",
" ft4", " ft5", " ft6", " ft7",
" fs0", " fs1", " fa0", " fa1",
" fa2", " fa3", " fa4", " fa5",
" fa6", " fa7", " fs2", " fs3",
" fs4", " fs5", " fs6", " fs7",
" fs8", " fs9", "fs10", "fs11",
" ft8", " ft9", "ft10", "ft11")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(fpreg)
}
}
object BoomCoreStringPrefix
{
/**
* Add prefix to BOOM strings (currently only adds the hartId)
*
* @param strs list of strings
* @return String combining the list with the prefix per line
*/
def apply(strs: String*)(implicit p: Parameters) = {
val prefix = "[C" + s"${p(TileKey).tileId}" + "] "
strs.map(str => prefix + str + "\n").mkString("")
}
}
class BranchKillablePipeline[T <: boom.v4.common.HasBoomUOP](gen: T, stages: Int)
(implicit p: org.chipsalliance.cde.config.Parameters)
extends boom.v4.common.BoomModule()(p)
with boom.v4.common.HasBoomCoreParameters
{
val io = IO(new Bundle {
val req = Input(Valid(gen))
val flush = Input(Bool())
val brupdate = Input(new BrUpdateInfo)
val resp = Output(Vec(stages, Valid(gen)))
})
require(stages > 0)
val uops = Reg(Vec(stages, Valid(gen)))
uops(0).valid := io.req.valid && !IsKilledByBranch(io.brupdate, io.flush, io.req.bits)
uops(0).bits := UpdateBrMask(io.brupdate, io.req.bits)
for (i <- 1 until stages) {
uops(i).valid := uops(i-1).valid && !IsKilledByBranch(io.brupdate, io.flush, uops(i-1).bits)
uops(i).bits := UpdateBrMask(io.brupdate, uops(i-1).bits)
}
for (i <- 0 until stages) { when (reset.asBool) { uops(i).valid := false.B } }
io.resp := uops
}
| module BranchKillableQueue_11( // @[util.scala:458:7]
input clock, // @[util.scala:458:7]
input reset, // @[util.scala:458:7]
output io_enq_ready, // @[util.scala:463:14]
input io_enq_valid, // @[util.scala:463:14]
input [31:0] io_enq_bits_uop_inst, // @[util.scala:463:14]
input [31:0] io_enq_bits_uop_debug_inst, // @[util.scala:463:14]
input io_enq_bits_uop_is_rvc, // @[util.scala:463:14]
input [33:0] io_enq_bits_uop_debug_pc, // @[util.scala:463:14]
input io_enq_bits_uop_iq_type_0, // @[util.scala:463:14]
input io_enq_bits_uop_iq_type_1, // @[util.scala:463:14]
input io_enq_bits_uop_iq_type_2, // @[util.scala:463:14]
input io_enq_bits_uop_iq_type_3, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_0, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_1, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_2, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_3, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_4, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_5, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_6, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_7, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_8, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_9, // @[util.scala:463:14]
input io_enq_bits_uop_iw_issued, // @[util.scala:463:14]
input io_enq_bits_uop_iw_issued_partial_agen, // @[util.scala:463:14]
input io_enq_bits_uop_iw_issued_partial_dgen, // @[util.scala:463:14]
input io_enq_bits_uop_iw_p1_speculative_child, // @[util.scala:463:14]
input io_enq_bits_uop_iw_p2_speculative_child, // @[util.scala:463:14]
input io_enq_bits_uop_iw_p1_bypass_hint, // @[util.scala:463:14]
input io_enq_bits_uop_iw_p2_bypass_hint, // @[util.scala:463:14]
input io_enq_bits_uop_iw_p3_bypass_hint, // @[util.scala:463:14]
input io_enq_bits_uop_dis_col_sel, // @[util.scala:463:14]
input [3:0] io_enq_bits_uop_br_mask, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_br_tag, // @[util.scala:463:14]
input [3:0] io_enq_bits_uop_br_type, // @[util.scala:463:14]
input io_enq_bits_uop_is_sfb, // @[util.scala:463:14]
input io_enq_bits_uop_is_fence, // @[util.scala:463:14]
input io_enq_bits_uop_is_fencei, // @[util.scala:463:14]
input io_enq_bits_uop_is_sfence, // @[util.scala:463:14]
input io_enq_bits_uop_is_amo, // @[util.scala:463:14]
input io_enq_bits_uop_is_eret, // @[util.scala:463:14]
input io_enq_bits_uop_is_sys_pc2epc, // @[util.scala:463:14]
input io_enq_bits_uop_is_rocc, // @[util.scala:463:14]
input io_enq_bits_uop_is_mov, // @[util.scala:463:14]
input [3:0] io_enq_bits_uop_ftq_idx, // @[util.scala:463:14]
input io_enq_bits_uop_edge_inst, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_pc_lob, // @[util.scala:463:14]
input io_enq_bits_uop_taken, // @[util.scala:463:14]
input io_enq_bits_uop_imm_rename, // @[util.scala:463:14]
input [2:0] io_enq_bits_uop_imm_sel, // @[util.scala:463:14]
input [4:0] io_enq_bits_uop_pimm, // @[util.scala:463:14]
input [19:0] io_enq_bits_uop_imm_packed, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_op1_sel, // @[util.scala:463:14]
input [2:0] io_enq_bits_uop_op2_sel, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_ldst, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_wen, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_ren1, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_ren2, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_ren3, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_swap12, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_swap23, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_fp_ctrl_typeTagIn, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_fp_ctrl_typeTagOut, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_fromint, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_toint, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_fastpipe, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_fma, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_div, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_sqrt, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_wflags, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_vec, // @[util.scala:463:14]
input [4:0] io_enq_bits_uop_rob_idx, // @[util.scala:463:14]
input [3:0] io_enq_bits_uop_ldq_idx, // @[util.scala:463:14]
input [3:0] io_enq_bits_uop_stq_idx, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_rxq_idx, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_pdst, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_prs1, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_prs2, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_prs3, // @[util.scala:463:14]
input [3:0] io_enq_bits_uop_ppred, // @[util.scala:463:14]
input io_enq_bits_uop_prs1_busy, // @[util.scala:463:14]
input io_enq_bits_uop_prs2_busy, // @[util.scala:463:14]
input io_enq_bits_uop_prs3_busy, // @[util.scala:463:14]
input io_enq_bits_uop_ppred_busy, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_stale_pdst, // @[util.scala:463:14]
input io_enq_bits_uop_exception, // @[util.scala:463:14]
input [63:0] io_enq_bits_uop_exc_cause, // @[util.scala:463:14]
input [4:0] io_enq_bits_uop_mem_cmd, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_mem_size, // @[util.scala:463:14]
input io_enq_bits_uop_mem_signed, // @[util.scala:463:14]
input io_enq_bits_uop_uses_ldq, // @[util.scala:463:14]
input io_enq_bits_uop_uses_stq, // @[util.scala:463:14]
input io_enq_bits_uop_is_unique, // @[util.scala:463:14]
input io_enq_bits_uop_flush_on_commit, // @[util.scala:463:14]
input [2:0] io_enq_bits_uop_csr_cmd, // @[util.scala:463:14]
input io_enq_bits_uop_ldst_is_rs1, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_ldst, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_lrs1, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_lrs2, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_lrs3, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_dst_rtype, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_lrs1_rtype, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_lrs2_rtype, // @[util.scala:463:14]
input io_enq_bits_uop_frs3_en, // @[util.scala:463:14]
input io_enq_bits_uop_fcn_dw, // @[util.scala:463:14]
input [4:0] io_enq_bits_uop_fcn_op, // @[util.scala:463:14]
input io_enq_bits_uop_fp_val, // @[util.scala:463:14]
input [2:0] io_enq_bits_uop_fp_rm, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_fp_typ, // @[util.scala:463:14]
input io_enq_bits_uop_xcpt_pf_if, // @[util.scala:463:14]
input io_enq_bits_uop_xcpt_ae_if, // @[util.scala:463:14]
input io_enq_bits_uop_xcpt_ma_if, // @[util.scala:463:14]
input io_enq_bits_uop_bp_debug_if, // @[util.scala:463:14]
input io_enq_bits_uop_bp_xcpt_if, // @[util.scala:463:14]
input [2:0] io_enq_bits_uop_debug_fsrc, // @[util.scala:463:14]
input [2:0] io_enq_bits_uop_debug_tsrc, // @[util.scala:463:14]
input [33:0] io_enq_bits_addr, // @[util.scala:463:14]
input [63:0] io_enq_bits_data, // @[util.scala:463:14]
input io_enq_bits_is_hella, // @[util.scala:463:14]
input io_enq_bits_tag_match, // @[util.scala:463:14]
input [1:0] io_enq_bits_old_meta_coh_state, // @[util.scala:463:14]
input [21:0] io_enq_bits_old_meta_tag, // @[util.scala:463:14]
input [1:0] io_enq_bits_way_en, // @[util.scala:463:14]
input [4:0] io_enq_bits_sdq_id, // @[util.scala:463:14]
input io_deq_ready, // @[util.scala:463:14]
output io_deq_valid, // @[util.scala:463:14]
output [31:0] io_deq_bits_uop_inst, // @[util.scala:463:14]
output [31:0] io_deq_bits_uop_debug_inst, // @[util.scala:463:14]
output io_deq_bits_uop_is_rvc, // @[util.scala:463:14]
output [33:0] io_deq_bits_uop_debug_pc, // @[util.scala:463:14]
output io_deq_bits_uop_iq_type_0, // @[util.scala:463:14]
output io_deq_bits_uop_iq_type_1, // @[util.scala:463:14]
output io_deq_bits_uop_iq_type_2, // @[util.scala:463:14]
output io_deq_bits_uop_iq_type_3, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_0, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_1, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_2, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_3, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_4, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_5, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_6, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_7, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_8, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_9, // @[util.scala:463:14]
output io_deq_bits_uop_iw_issued, // @[util.scala:463:14]
output io_deq_bits_uop_iw_issued_partial_agen, // @[util.scala:463:14]
output io_deq_bits_uop_iw_issued_partial_dgen, // @[util.scala:463:14]
output io_deq_bits_uop_iw_p1_speculative_child, // @[util.scala:463:14]
output io_deq_bits_uop_iw_p2_speculative_child, // @[util.scala:463:14]
output io_deq_bits_uop_iw_p1_bypass_hint, // @[util.scala:463:14]
output io_deq_bits_uop_iw_p2_bypass_hint, // @[util.scala:463:14]
output io_deq_bits_uop_iw_p3_bypass_hint, // @[util.scala:463:14]
output io_deq_bits_uop_dis_col_sel, // @[util.scala:463:14]
output [3:0] io_deq_bits_uop_br_mask, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_br_tag, // @[util.scala:463:14]
output [3:0] io_deq_bits_uop_br_type, // @[util.scala:463:14]
output io_deq_bits_uop_is_sfb, // @[util.scala:463:14]
output io_deq_bits_uop_is_fence, // @[util.scala:463:14]
output io_deq_bits_uop_is_fencei, // @[util.scala:463:14]
output io_deq_bits_uop_is_sfence, // @[util.scala:463:14]
output io_deq_bits_uop_is_amo, // @[util.scala:463:14]
output io_deq_bits_uop_is_eret, // @[util.scala:463:14]
output io_deq_bits_uop_is_sys_pc2epc, // @[util.scala:463:14]
output io_deq_bits_uop_is_rocc, // @[util.scala:463:14]
output io_deq_bits_uop_is_mov, // @[util.scala:463:14]
output [3:0] io_deq_bits_uop_ftq_idx, // @[util.scala:463:14]
output io_deq_bits_uop_edge_inst, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_pc_lob, // @[util.scala:463:14]
output io_deq_bits_uop_taken, // @[util.scala:463:14]
output io_deq_bits_uop_imm_rename, // @[util.scala:463:14]
output [2:0] io_deq_bits_uop_imm_sel, // @[util.scala:463:14]
output [4:0] io_deq_bits_uop_pimm, // @[util.scala:463:14]
output [19:0] io_deq_bits_uop_imm_packed, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_op1_sel, // @[util.scala:463:14]
output [2:0] io_deq_bits_uop_op2_sel, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_ldst, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_wen, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_ren1, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_ren2, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_ren3, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_swap12, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_swap23, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_fp_ctrl_typeTagIn, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_fp_ctrl_typeTagOut, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_fromint, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_toint, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_fastpipe, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_fma, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_div, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_sqrt, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_wflags, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_vec, // @[util.scala:463:14]
output [4:0] io_deq_bits_uop_rob_idx, // @[util.scala:463:14]
output [3:0] io_deq_bits_uop_ldq_idx, // @[util.scala:463:14]
output [3:0] io_deq_bits_uop_stq_idx, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_rxq_idx, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_pdst, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_prs1, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_prs2, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_prs3, // @[util.scala:463:14]
output [3:0] io_deq_bits_uop_ppred, // @[util.scala:463:14]
output io_deq_bits_uop_prs1_busy, // @[util.scala:463:14]
output io_deq_bits_uop_prs2_busy, // @[util.scala:463:14]
output io_deq_bits_uop_prs3_busy, // @[util.scala:463:14]
output io_deq_bits_uop_ppred_busy, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_stale_pdst, // @[util.scala:463:14]
output io_deq_bits_uop_exception, // @[util.scala:463:14]
output [63:0] io_deq_bits_uop_exc_cause, // @[util.scala:463:14]
output [4:0] io_deq_bits_uop_mem_cmd, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_mem_size, // @[util.scala:463:14]
output io_deq_bits_uop_mem_signed, // @[util.scala:463:14]
output io_deq_bits_uop_uses_ldq, // @[util.scala:463:14]
output io_deq_bits_uop_uses_stq, // @[util.scala:463:14]
output io_deq_bits_uop_is_unique, // @[util.scala:463:14]
output io_deq_bits_uop_flush_on_commit, // @[util.scala:463:14]
output [2:0] io_deq_bits_uop_csr_cmd, // @[util.scala:463:14]
output io_deq_bits_uop_ldst_is_rs1, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_ldst, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_lrs1, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_lrs2, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_lrs3, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_dst_rtype, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_lrs1_rtype, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_lrs2_rtype, // @[util.scala:463:14]
output io_deq_bits_uop_frs3_en, // @[util.scala:463:14]
output io_deq_bits_uop_fcn_dw, // @[util.scala:463:14]
output [4:0] io_deq_bits_uop_fcn_op, // @[util.scala:463:14]
output io_deq_bits_uop_fp_val, // @[util.scala:463:14]
output [2:0] io_deq_bits_uop_fp_rm, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_fp_typ, // @[util.scala:463:14]
output io_deq_bits_uop_xcpt_pf_if, // @[util.scala:463:14]
output io_deq_bits_uop_xcpt_ae_if, // @[util.scala:463:14]
output io_deq_bits_uop_xcpt_ma_if, // @[util.scala:463:14]
output io_deq_bits_uop_bp_debug_if, // @[util.scala:463:14]
output io_deq_bits_uop_bp_xcpt_if, // @[util.scala:463:14]
output [2:0] io_deq_bits_uop_debug_fsrc, // @[util.scala:463:14]
output [2:0] io_deq_bits_uop_debug_tsrc, // @[util.scala:463:14]
output [33:0] io_deq_bits_addr, // @[util.scala:463:14]
output [63:0] io_deq_bits_data, // @[util.scala:463:14]
output io_deq_bits_is_hella, // @[util.scala:463:14]
output io_deq_bits_tag_match, // @[util.scala:463:14]
output [1:0] io_deq_bits_old_meta_coh_state, // @[util.scala:463:14]
output [21:0] io_deq_bits_old_meta_tag, // @[util.scala:463:14]
output [1:0] io_deq_bits_way_en, // @[util.scala:463:14]
output [4:0] io_deq_bits_sdq_id, // @[util.scala:463:14]
output io_empty // @[util.scala:463:14]
);
wire _out_valid_T_12; // @[util.scala:496:38]
wire [31:0] _main_io_deq_bits_uop_inst; // @[util.scala:476:22]
wire [31:0] _main_io_deq_bits_uop_debug_inst; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_is_rvc; // @[util.scala:476:22]
wire [33:0] _main_io_deq_bits_uop_debug_pc; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_iq_type_0; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_iq_type_1; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_iq_type_2; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_iq_type_3; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fu_code_0; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fu_code_1; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fu_code_2; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fu_code_3; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fu_code_4; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fu_code_5; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fu_code_6; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fu_code_7; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fu_code_8; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fu_code_9; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_iw_issued; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_iw_issued_partial_agen; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_iw_issued_partial_dgen; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_iw_p1_speculative_child; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_iw_p2_speculative_child; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_iw_p1_bypass_hint; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_iw_p2_bypass_hint; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_iw_p3_bypass_hint; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_dis_col_sel; // @[util.scala:476:22]
wire [3:0] _main_io_deq_bits_uop_br_mask; // @[util.scala:476:22]
wire [1:0] _main_io_deq_bits_uop_br_tag; // @[util.scala:476:22]
wire [3:0] _main_io_deq_bits_uop_br_type; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_is_sfb; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_is_fence; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_is_fencei; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_is_sfence; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_is_amo; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_is_eret; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_is_sys_pc2epc; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_is_rocc; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_is_mov; // @[util.scala:476:22]
wire [3:0] _main_io_deq_bits_uop_ftq_idx; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_edge_inst; // @[util.scala:476:22]
wire [5:0] _main_io_deq_bits_uop_pc_lob; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_taken; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_imm_rename; // @[util.scala:476:22]
wire [2:0] _main_io_deq_bits_uop_imm_sel; // @[util.scala:476:22]
wire [4:0] _main_io_deq_bits_uop_pimm; // @[util.scala:476:22]
wire [19:0] _main_io_deq_bits_uop_imm_packed; // @[util.scala:476:22]
wire [1:0] _main_io_deq_bits_uop_op1_sel; // @[util.scala:476:22]
wire [2:0] _main_io_deq_bits_uop_op2_sel; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_ldst; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_wen; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_ren1; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_ren2; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_ren3; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_swap12; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_swap23; // @[util.scala:476:22]
wire [1:0] _main_io_deq_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:476:22]
wire [1:0] _main_io_deq_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_fromint; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_toint; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_fastpipe; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_fma; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_div; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_sqrt; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_wflags; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_vec; // @[util.scala:476:22]
wire [4:0] _main_io_deq_bits_uop_rob_idx; // @[util.scala:476:22]
wire [3:0] _main_io_deq_bits_uop_ldq_idx; // @[util.scala:476:22]
wire [3:0] _main_io_deq_bits_uop_stq_idx; // @[util.scala:476:22]
wire [1:0] _main_io_deq_bits_uop_rxq_idx; // @[util.scala:476:22]
wire [5:0] _main_io_deq_bits_uop_pdst; // @[util.scala:476:22]
wire [5:0] _main_io_deq_bits_uop_prs1; // @[util.scala:476:22]
wire [5:0] _main_io_deq_bits_uop_prs2; // @[util.scala:476:22]
wire [5:0] _main_io_deq_bits_uop_prs3; // @[util.scala:476:22]
wire [3:0] _main_io_deq_bits_uop_ppred; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_prs1_busy; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_prs2_busy; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_prs3_busy; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_ppred_busy; // @[util.scala:476:22]
wire [5:0] _main_io_deq_bits_uop_stale_pdst; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_exception; // @[util.scala:476:22]
wire [63:0] _main_io_deq_bits_uop_exc_cause; // @[util.scala:476:22]
wire [4:0] _main_io_deq_bits_uop_mem_cmd; // @[util.scala:476:22]
wire [1:0] _main_io_deq_bits_uop_mem_size; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_mem_signed; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_uses_ldq; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_uses_stq; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_is_unique; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_flush_on_commit; // @[util.scala:476:22]
wire [2:0] _main_io_deq_bits_uop_csr_cmd; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_ldst_is_rs1; // @[util.scala:476:22]
wire [5:0] _main_io_deq_bits_uop_ldst; // @[util.scala:476:22]
wire [5:0] _main_io_deq_bits_uop_lrs1; // @[util.scala:476:22]
wire [5:0] _main_io_deq_bits_uop_lrs2; // @[util.scala:476:22]
wire [5:0] _main_io_deq_bits_uop_lrs3; // @[util.scala:476:22]
wire [1:0] _main_io_deq_bits_uop_dst_rtype; // @[util.scala:476:22]
wire [1:0] _main_io_deq_bits_uop_lrs1_rtype; // @[util.scala:476:22]
wire [1:0] _main_io_deq_bits_uop_lrs2_rtype; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_frs3_en; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fcn_dw; // @[util.scala:476:22]
wire [4:0] _main_io_deq_bits_uop_fcn_op; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_val; // @[util.scala:476:22]
wire [2:0] _main_io_deq_bits_uop_fp_rm; // @[util.scala:476:22]
wire [1:0] _main_io_deq_bits_uop_fp_typ; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_xcpt_pf_if; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_xcpt_ae_if; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_xcpt_ma_if; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_bp_debug_if; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_bp_xcpt_if; // @[util.scala:476:22]
wire [2:0] _main_io_deq_bits_uop_debug_fsrc; // @[util.scala:476:22]
wire [2:0] _main_io_deq_bits_uop_debug_tsrc; // @[util.scala:476:22]
wire [33:0] _main_io_deq_bits_addr; // @[util.scala:476:22]
wire [63:0] _main_io_deq_bits_data; // @[util.scala:476:22]
wire _main_io_deq_bits_is_hella; // @[util.scala:476:22]
wire _main_io_deq_bits_tag_match; // @[util.scala:476:22]
wire [1:0] _main_io_deq_bits_old_meta_coh_state; // @[util.scala:476:22]
wire [21:0] _main_io_deq_bits_old_meta_tag; // @[util.scala:476:22]
wire [1:0] _main_io_deq_bits_way_en; // @[util.scala:476:22]
wire [4:0] _main_io_deq_bits_sdq_id; // @[util.scala:476:22]
wire _main_io_empty; // @[util.scala:476:22]
wire [3:0] _main_io_count; // @[util.scala:476:22]
wire io_enq_valid_0 = io_enq_valid; // @[util.scala:458:7]
wire [31:0] io_enq_bits_uop_inst_0 = io_enq_bits_uop_inst; // @[util.scala:458:7]
wire [31:0] io_enq_bits_uop_debug_inst_0 = io_enq_bits_uop_debug_inst; // @[util.scala:458:7]
wire io_enq_bits_uop_is_rvc_0 = io_enq_bits_uop_is_rvc; // @[util.scala:458:7]
wire [33:0] io_enq_bits_uop_debug_pc_0 = io_enq_bits_uop_debug_pc; // @[util.scala:458:7]
wire io_enq_bits_uop_iq_type_0_0 = io_enq_bits_uop_iq_type_0; // @[util.scala:458:7]
wire io_enq_bits_uop_iq_type_1_0 = io_enq_bits_uop_iq_type_1; // @[util.scala:458:7]
wire io_enq_bits_uop_iq_type_2_0 = io_enq_bits_uop_iq_type_2; // @[util.scala:458:7]
wire io_enq_bits_uop_iq_type_3_0 = io_enq_bits_uop_iq_type_3; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_0_0 = io_enq_bits_uop_fu_code_0; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_1_0 = io_enq_bits_uop_fu_code_1; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_2_0 = io_enq_bits_uop_fu_code_2; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_3_0 = io_enq_bits_uop_fu_code_3; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_4_0 = io_enq_bits_uop_fu_code_4; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_5_0 = io_enq_bits_uop_fu_code_5; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_6_0 = io_enq_bits_uop_fu_code_6; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_7_0 = io_enq_bits_uop_fu_code_7; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_8_0 = io_enq_bits_uop_fu_code_8; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_9_0 = io_enq_bits_uop_fu_code_9; // @[util.scala:458:7]
wire io_enq_bits_uop_iw_issued_0 = io_enq_bits_uop_iw_issued; // @[util.scala:458:7]
wire io_enq_bits_uop_iw_issued_partial_agen_0 = io_enq_bits_uop_iw_issued_partial_agen; // @[util.scala:458:7]
wire io_enq_bits_uop_iw_issued_partial_dgen_0 = io_enq_bits_uop_iw_issued_partial_dgen; // @[util.scala:458:7]
wire io_enq_bits_uop_iw_p1_speculative_child_0 = io_enq_bits_uop_iw_p1_speculative_child; // @[util.scala:458:7]
wire io_enq_bits_uop_iw_p2_speculative_child_0 = io_enq_bits_uop_iw_p2_speculative_child; // @[util.scala:458:7]
wire io_enq_bits_uop_iw_p1_bypass_hint_0 = io_enq_bits_uop_iw_p1_bypass_hint; // @[util.scala:458:7]
wire io_enq_bits_uop_iw_p2_bypass_hint_0 = io_enq_bits_uop_iw_p2_bypass_hint; // @[util.scala:458:7]
wire io_enq_bits_uop_iw_p3_bypass_hint_0 = io_enq_bits_uop_iw_p3_bypass_hint; // @[util.scala:458:7]
wire io_enq_bits_uop_dis_col_sel_0 = io_enq_bits_uop_dis_col_sel; // @[util.scala:458:7]
wire [3:0] io_enq_bits_uop_br_mask_0 = io_enq_bits_uop_br_mask; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_br_tag_0 = io_enq_bits_uop_br_tag; // @[util.scala:458:7]
wire [3:0] io_enq_bits_uop_br_type_0 = io_enq_bits_uop_br_type; // @[util.scala:458:7]
wire io_enq_bits_uop_is_sfb_0 = io_enq_bits_uop_is_sfb; // @[util.scala:458:7]
wire io_enq_bits_uop_is_fence_0 = io_enq_bits_uop_is_fence; // @[util.scala:458:7]
wire io_enq_bits_uop_is_fencei_0 = io_enq_bits_uop_is_fencei; // @[util.scala:458:7]
wire io_enq_bits_uop_is_sfence_0 = io_enq_bits_uop_is_sfence; // @[util.scala:458:7]
wire io_enq_bits_uop_is_amo_0 = io_enq_bits_uop_is_amo; // @[util.scala:458:7]
wire io_enq_bits_uop_is_eret_0 = io_enq_bits_uop_is_eret; // @[util.scala:458:7]
wire io_enq_bits_uop_is_sys_pc2epc_0 = io_enq_bits_uop_is_sys_pc2epc; // @[util.scala:458:7]
wire io_enq_bits_uop_is_rocc_0 = io_enq_bits_uop_is_rocc; // @[util.scala:458:7]
wire io_enq_bits_uop_is_mov_0 = io_enq_bits_uop_is_mov; // @[util.scala:458:7]
wire [3:0] io_enq_bits_uop_ftq_idx_0 = io_enq_bits_uop_ftq_idx; // @[util.scala:458:7]
wire io_enq_bits_uop_edge_inst_0 = io_enq_bits_uop_edge_inst; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_pc_lob_0 = io_enq_bits_uop_pc_lob; // @[util.scala:458:7]
wire io_enq_bits_uop_taken_0 = io_enq_bits_uop_taken; // @[util.scala:458:7]
wire io_enq_bits_uop_imm_rename_0 = io_enq_bits_uop_imm_rename; // @[util.scala:458:7]
wire [2:0] io_enq_bits_uop_imm_sel_0 = io_enq_bits_uop_imm_sel; // @[util.scala:458:7]
wire [4:0] io_enq_bits_uop_pimm_0 = io_enq_bits_uop_pimm; // @[util.scala:458:7]
wire [19:0] io_enq_bits_uop_imm_packed_0 = io_enq_bits_uop_imm_packed; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_op1_sel_0 = io_enq_bits_uop_op1_sel; // @[util.scala:458:7]
wire [2:0] io_enq_bits_uop_op2_sel_0 = io_enq_bits_uop_op2_sel; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_ldst_0 = io_enq_bits_uop_fp_ctrl_ldst; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_wen_0 = io_enq_bits_uop_fp_ctrl_wen; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_ren1_0 = io_enq_bits_uop_fp_ctrl_ren1; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_ren2_0 = io_enq_bits_uop_fp_ctrl_ren2; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_ren3_0 = io_enq_bits_uop_fp_ctrl_ren3; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_swap12_0 = io_enq_bits_uop_fp_ctrl_swap12; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_swap23_0 = io_enq_bits_uop_fp_ctrl_swap23; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_fp_ctrl_typeTagIn_0 = io_enq_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_fp_ctrl_typeTagOut_0 = io_enq_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_fromint_0 = io_enq_bits_uop_fp_ctrl_fromint; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_toint_0 = io_enq_bits_uop_fp_ctrl_toint; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_fastpipe_0 = io_enq_bits_uop_fp_ctrl_fastpipe; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_fma_0 = io_enq_bits_uop_fp_ctrl_fma; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_div_0 = io_enq_bits_uop_fp_ctrl_div; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_sqrt_0 = io_enq_bits_uop_fp_ctrl_sqrt; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_wflags_0 = io_enq_bits_uop_fp_ctrl_wflags; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_vec_0 = io_enq_bits_uop_fp_ctrl_vec; // @[util.scala:458:7]
wire [4:0] io_enq_bits_uop_rob_idx_0 = io_enq_bits_uop_rob_idx; // @[util.scala:458:7]
wire [3:0] io_enq_bits_uop_ldq_idx_0 = io_enq_bits_uop_ldq_idx; // @[util.scala:458:7]
wire [3:0] io_enq_bits_uop_stq_idx_0 = io_enq_bits_uop_stq_idx; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_rxq_idx_0 = io_enq_bits_uop_rxq_idx; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_pdst_0 = io_enq_bits_uop_pdst; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_prs1_0 = io_enq_bits_uop_prs1; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_prs2_0 = io_enq_bits_uop_prs2; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_prs3_0 = io_enq_bits_uop_prs3; // @[util.scala:458:7]
wire [3:0] io_enq_bits_uop_ppred_0 = io_enq_bits_uop_ppred; // @[util.scala:458:7]
wire io_enq_bits_uop_prs1_busy_0 = io_enq_bits_uop_prs1_busy; // @[util.scala:458:7]
wire io_enq_bits_uop_prs2_busy_0 = io_enq_bits_uop_prs2_busy; // @[util.scala:458:7]
wire io_enq_bits_uop_prs3_busy_0 = io_enq_bits_uop_prs3_busy; // @[util.scala:458:7]
wire io_enq_bits_uop_ppred_busy_0 = io_enq_bits_uop_ppred_busy; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_stale_pdst_0 = io_enq_bits_uop_stale_pdst; // @[util.scala:458:7]
wire io_enq_bits_uop_exception_0 = io_enq_bits_uop_exception; // @[util.scala:458:7]
wire [63:0] io_enq_bits_uop_exc_cause_0 = io_enq_bits_uop_exc_cause; // @[util.scala:458:7]
wire [4:0] io_enq_bits_uop_mem_cmd_0 = io_enq_bits_uop_mem_cmd; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_mem_size_0 = io_enq_bits_uop_mem_size; // @[util.scala:458:7]
wire io_enq_bits_uop_mem_signed_0 = io_enq_bits_uop_mem_signed; // @[util.scala:458:7]
wire io_enq_bits_uop_uses_ldq_0 = io_enq_bits_uop_uses_ldq; // @[util.scala:458:7]
wire io_enq_bits_uop_uses_stq_0 = io_enq_bits_uop_uses_stq; // @[util.scala:458:7]
wire io_enq_bits_uop_is_unique_0 = io_enq_bits_uop_is_unique; // @[util.scala:458:7]
wire io_enq_bits_uop_flush_on_commit_0 = io_enq_bits_uop_flush_on_commit; // @[util.scala:458:7]
wire [2:0] io_enq_bits_uop_csr_cmd_0 = io_enq_bits_uop_csr_cmd; // @[util.scala:458:7]
wire io_enq_bits_uop_ldst_is_rs1_0 = io_enq_bits_uop_ldst_is_rs1; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_ldst_0 = io_enq_bits_uop_ldst; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_lrs1_0 = io_enq_bits_uop_lrs1; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_lrs2_0 = io_enq_bits_uop_lrs2; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_lrs3_0 = io_enq_bits_uop_lrs3; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_dst_rtype_0 = io_enq_bits_uop_dst_rtype; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_lrs1_rtype_0 = io_enq_bits_uop_lrs1_rtype; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_lrs2_rtype_0 = io_enq_bits_uop_lrs2_rtype; // @[util.scala:458:7]
wire io_enq_bits_uop_frs3_en_0 = io_enq_bits_uop_frs3_en; // @[util.scala:458:7]
wire io_enq_bits_uop_fcn_dw_0 = io_enq_bits_uop_fcn_dw; // @[util.scala:458:7]
wire [4:0] io_enq_bits_uop_fcn_op_0 = io_enq_bits_uop_fcn_op; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_val_0 = io_enq_bits_uop_fp_val; // @[util.scala:458:7]
wire [2:0] io_enq_bits_uop_fp_rm_0 = io_enq_bits_uop_fp_rm; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_fp_typ_0 = io_enq_bits_uop_fp_typ; // @[util.scala:458:7]
wire io_enq_bits_uop_xcpt_pf_if_0 = io_enq_bits_uop_xcpt_pf_if; // @[util.scala:458:7]
wire io_enq_bits_uop_xcpt_ae_if_0 = io_enq_bits_uop_xcpt_ae_if; // @[util.scala:458:7]
wire io_enq_bits_uop_xcpt_ma_if_0 = io_enq_bits_uop_xcpt_ma_if; // @[util.scala:458:7]
wire io_enq_bits_uop_bp_debug_if_0 = io_enq_bits_uop_bp_debug_if; // @[util.scala:458:7]
wire io_enq_bits_uop_bp_xcpt_if_0 = io_enq_bits_uop_bp_xcpt_if; // @[util.scala:458:7]
wire [2:0] io_enq_bits_uop_debug_fsrc_0 = io_enq_bits_uop_debug_fsrc; // @[util.scala:458:7]
wire [2:0] io_enq_bits_uop_debug_tsrc_0 = io_enq_bits_uop_debug_tsrc; // @[util.scala:458:7]
wire [33:0] io_enq_bits_addr_0 = io_enq_bits_addr; // @[util.scala:458:7]
wire [63:0] io_enq_bits_data_0 = io_enq_bits_data; // @[util.scala:458:7]
wire io_enq_bits_is_hella_0 = io_enq_bits_is_hella; // @[util.scala:458:7]
wire io_enq_bits_tag_match_0 = io_enq_bits_tag_match; // @[util.scala:458:7]
wire [1:0] io_enq_bits_old_meta_coh_state_0 = io_enq_bits_old_meta_coh_state; // @[util.scala:458:7]
wire [21:0] io_enq_bits_old_meta_tag_0 = io_enq_bits_old_meta_tag; // @[util.scala:458:7]
wire [1:0] io_enq_bits_way_en_0 = io_enq_bits_way_en; // @[util.scala:458:7]
wire [4:0] io_enq_bits_sdq_id_0 = io_enq_bits_sdq_id; // @[util.scala:458:7]
wire io_deq_ready_0 = io_deq_ready; // @[util.scala:458:7]
wire _out_valid_T_3 = 1'h1; // @[util.scala:492:{31,83}, :496:{41,106}]
wire _out_valid_T_6 = 1'h1; // @[util.scala:492:{31,83}, :496:{41,106}]
wire _out_valid_T_11 = 1'h1; // @[util.scala:492:{31,83}, :496:{41,106}]
wire _out_valid_T_14 = 1'h1; // @[util.scala:492:{31,83}, :496:{41,106}]
wire [3:0] _out_uop_out_br_mask_T = 4'hF; // @[util.scala:93:27]
wire [3:0] _out_uop_out_br_mask_T_2 = 4'hF; // @[util.scala:93:27]
wire [20:0] io_brupdate_b2_target_offset = 21'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [63:0] io_brupdate_b2_uop_exc_cause = 64'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [19:0] io_brupdate_b2_uop_imm_packed = 20'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [4:0] io_brupdate_b2_uop_pimm = 5'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [4:0] io_brupdate_b2_uop_rob_idx = 5'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [4:0] io_brupdate_b2_uop_mem_cmd = 5'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [4:0] io_brupdate_b2_uop_fcn_op = 5'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [2:0] io_brupdate_b2_uop_imm_sel = 3'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [2:0] io_brupdate_b2_uop_op2_sel = 3'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [2:0] io_brupdate_b2_uop_csr_cmd = 3'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [2:0] io_brupdate_b2_uop_fp_rm = 3'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [2:0] io_brupdate_b2_uop_debug_fsrc = 3'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [2:0] io_brupdate_b2_uop_debug_tsrc = 3'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [2:0] io_brupdate_b2_cfi_type = 3'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [5:0] io_brupdate_b2_uop_pc_lob = 6'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [5:0] io_brupdate_b2_uop_pdst = 6'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [5:0] io_brupdate_b2_uop_prs1 = 6'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [5:0] io_brupdate_b2_uop_prs2 = 6'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [5:0] io_brupdate_b2_uop_prs3 = 6'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [5:0] io_brupdate_b2_uop_stale_pdst = 6'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [5:0] io_brupdate_b2_uop_ldst = 6'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [5:0] io_brupdate_b2_uop_lrs1 = 6'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [5:0] io_brupdate_b2_uop_lrs2 = 6'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [5:0] io_brupdate_b2_uop_lrs3 = 6'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [1:0] io_brupdate_b2_uop_br_tag = 2'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [1:0] io_brupdate_b2_uop_op1_sel = 2'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn = 2'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut = 2'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [1:0] io_brupdate_b2_uop_rxq_idx = 2'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [1:0] io_brupdate_b2_uop_mem_size = 2'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [1:0] io_brupdate_b2_uop_dst_rtype = 2'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype = 2'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype = 2'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [1:0] io_brupdate_b2_uop_fp_typ = 2'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [1:0] io_brupdate_b2_pc_sel = 2'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [33:0] io_brupdate_b2_uop_debug_pc = 34'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [33:0] io_brupdate_b2_jalr_target = 34'h0; // @[util.scala:458:7, :463:14, :476:22]
wire io_brupdate_b2_uop_is_rvc = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iq_type_0 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iq_type_1 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iq_type_2 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iq_type_3 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_0 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_1 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_2 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_3 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_4 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_5 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_6 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_7 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_8 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_9 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iw_issued = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iw_issued_partial_agen = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iw_issued_partial_dgen = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iw_p1_speculative_child = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iw_p2_speculative_child = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iw_p1_bypass_hint = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iw_p2_bypass_hint = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iw_p3_bypass_hint = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_dis_col_sel = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_sfb = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_fence = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_fencei = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_sfence = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_amo = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_eret = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_sys_pc2epc = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_rocc = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_mov = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_edge_inst = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_taken = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_imm_rename = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_ldst = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_wen = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_ren1 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_ren2 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_ren3 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_swap12 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_swap23 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_fromint = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_toint = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_fastpipe = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_fma = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_div = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_sqrt = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_wflags = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_vec = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_prs1_busy = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_prs2_busy = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_prs3_busy = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_ppred_busy = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_exception = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_mem_signed = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_uses_ldq = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_uses_stq = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_unique = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_flush_on_commit = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_ldst_is_rs1 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_frs3_en = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fcn_dw = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_val = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_xcpt_pf_if = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_xcpt_ae_if = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_xcpt_ma_if = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_bp_debug_if = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_bp_xcpt_if = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_mispredict = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_taken = 1'h0; // @[util.scala:458:7]
wire io_flush = 1'h0; // @[util.scala:458:7]
wire _out_valid_T_1 = 1'h0; // @[util.scala:126:59]
wire _out_valid_T_2 = 1'h0; // @[util.scala:61:61]
wire _out_valid_T_5 = 1'h0; // @[util.scala:492:94]
wire _out_valid_T_9 = 1'h0; // @[util.scala:126:59]
wire _out_valid_T_10 = 1'h0; // @[util.scala:61:61]
wire _out_valid_T_13 = 1'h0; // @[util.scala:496:117]
wire [31:0] io_brupdate_b2_uop_inst = 32'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [31:0] io_brupdate_b2_uop_debug_inst = 32'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [3:0] io_brupdate_b1_resolve_mask = 4'h0; // @[util.scala:126:51, :458:7, :463:14, :476:22]
wire [3:0] io_brupdate_b1_mispredict_mask = 4'h0; // @[util.scala:126:51, :458:7, :463:14, :476:22]
wire [3:0] io_brupdate_b2_uop_br_mask = 4'h0; // @[util.scala:126:51, :458:7, :463:14, :476:22]
wire [3:0] io_brupdate_b2_uop_br_type = 4'h0; // @[util.scala:126:51, :458:7, :463:14, :476:22]
wire [3:0] io_brupdate_b2_uop_ftq_idx = 4'h0; // @[util.scala:126:51, :458:7, :463:14, :476:22]
wire [3:0] io_brupdate_b2_uop_ldq_idx = 4'h0; // @[util.scala:126:51, :458:7, :463:14, :476:22]
wire [3:0] io_brupdate_b2_uop_stq_idx = 4'h0; // @[util.scala:126:51, :458:7, :463:14, :476:22]
wire [3:0] io_brupdate_b2_uop_ppred = 4'h0; // @[util.scala:126:51, :458:7, :463:14, :476:22]
wire [3:0] _out_valid_T = 4'h0; // @[util.scala:126:51, :458:7, :463:14, :476:22]
wire [3:0] _out_valid_T_8 = 4'h0; // @[util.scala:126:51, :458:7, :463:14, :476:22]
wire _io_empty_T_1; // @[util.scala:484:31]
wire [3:0] _io_count_T_1; // @[util.scala:485:31]
wire io_enq_ready_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iq_type_0_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iq_type_1_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iq_type_2_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iq_type_3_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_0_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_1_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_2_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_3_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_4_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_5_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_6_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_7_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_8_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_9_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7]
wire [31:0] io_deq_bits_uop_inst_0; // @[util.scala:458:7]
wire [31:0] io_deq_bits_uop_debug_inst_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_rvc_0; // @[util.scala:458:7]
wire [33:0] io_deq_bits_uop_debug_pc_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iw_issued_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7]
wire io_deq_bits_uop_dis_col_sel_0; // @[util.scala:458:7]
wire [3:0] io_deq_bits_uop_br_mask_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_br_tag_0; // @[util.scala:458:7]
wire [3:0] io_deq_bits_uop_br_type_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_sfb_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_fence_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_fencei_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_sfence_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_amo_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_eret_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_rocc_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_mov_0; // @[util.scala:458:7]
wire [3:0] io_deq_bits_uop_ftq_idx_0; // @[util.scala:458:7]
wire io_deq_bits_uop_edge_inst_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_pc_lob_0; // @[util.scala:458:7]
wire io_deq_bits_uop_taken_0; // @[util.scala:458:7]
wire io_deq_bits_uop_imm_rename_0; // @[util.scala:458:7]
wire [2:0] io_deq_bits_uop_imm_sel_0; // @[util.scala:458:7]
wire [4:0] io_deq_bits_uop_pimm_0; // @[util.scala:458:7]
wire [19:0] io_deq_bits_uop_imm_packed_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_op1_sel_0; // @[util.scala:458:7]
wire [2:0] io_deq_bits_uop_op2_sel_0; // @[util.scala:458:7]
wire [4:0] io_deq_bits_uop_rob_idx_0; // @[util.scala:458:7]
wire [3:0] io_deq_bits_uop_ldq_idx_0; // @[util.scala:458:7]
wire [3:0] io_deq_bits_uop_stq_idx_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_rxq_idx_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_pdst_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_prs1_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_prs2_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_prs3_0; // @[util.scala:458:7]
wire [3:0] io_deq_bits_uop_ppred_0; // @[util.scala:458:7]
wire io_deq_bits_uop_prs1_busy_0; // @[util.scala:458:7]
wire io_deq_bits_uop_prs2_busy_0; // @[util.scala:458:7]
wire io_deq_bits_uop_prs3_busy_0; // @[util.scala:458:7]
wire io_deq_bits_uop_ppred_busy_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_stale_pdst_0; // @[util.scala:458:7]
wire io_deq_bits_uop_exception_0; // @[util.scala:458:7]
wire [63:0] io_deq_bits_uop_exc_cause_0; // @[util.scala:458:7]
wire [4:0] io_deq_bits_uop_mem_cmd_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_mem_size_0; // @[util.scala:458:7]
wire io_deq_bits_uop_mem_signed_0; // @[util.scala:458:7]
wire io_deq_bits_uop_uses_ldq_0; // @[util.scala:458:7]
wire io_deq_bits_uop_uses_stq_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_unique_0; // @[util.scala:458:7]
wire io_deq_bits_uop_flush_on_commit_0; // @[util.scala:458:7]
wire [2:0] io_deq_bits_uop_csr_cmd_0; // @[util.scala:458:7]
wire io_deq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_ldst_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_lrs1_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_lrs2_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_lrs3_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_dst_rtype_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7]
wire io_deq_bits_uop_frs3_en_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fcn_dw_0; // @[util.scala:458:7]
wire [4:0] io_deq_bits_uop_fcn_op_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_val_0; // @[util.scala:458:7]
wire [2:0] io_deq_bits_uop_fp_rm_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_fp_typ_0; // @[util.scala:458:7]
wire io_deq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7]
wire io_deq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7]
wire io_deq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7]
wire io_deq_bits_uop_bp_debug_if_0; // @[util.scala:458:7]
wire io_deq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7]
wire [2:0] io_deq_bits_uop_debug_fsrc_0; // @[util.scala:458:7]
wire [2:0] io_deq_bits_uop_debug_tsrc_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_old_meta_coh_state_0; // @[util.scala:458:7]
wire [21:0] io_deq_bits_old_meta_tag_0; // @[util.scala:458:7]
wire [33:0] io_deq_bits_addr_0; // @[util.scala:458:7]
wire [63:0] io_deq_bits_data_0; // @[util.scala:458:7]
wire io_deq_bits_is_hella_0; // @[util.scala:458:7]
wire io_deq_bits_tag_match_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_way_en_0; // @[util.scala:458:7]
wire [4:0] io_deq_bits_sdq_id_0; // @[util.scala:458:7]
wire io_deq_valid_0; // @[util.scala:458:7]
wire io_empty_0; // @[util.scala:458:7]
wire [3:0] io_count; // @[util.scala:458:7]
reg [31:0] out_reg_uop_inst; // @[util.scala:477:22]
reg [31:0] out_reg_uop_debug_inst; // @[util.scala:477:22]
reg out_reg_uop_is_rvc; // @[util.scala:477:22]
reg [33:0] out_reg_uop_debug_pc; // @[util.scala:477:22]
reg out_reg_uop_iq_type_0; // @[util.scala:477:22]
reg out_reg_uop_iq_type_1; // @[util.scala:477:22]
reg out_reg_uop_iq_type_2; // @[util.scala:477:22]
reg out_reg_uop_iq_type_3; // @[util.scala:477:22]
reg out_reg_uop_fu_code_0; // @[util.scala:477:22]
reg out_reg_uop_fu_code_1; // @[util.scala:477:22]
reg out_reg_uop_fu_code_2; // @[util.scala:477:22]
reg out_reg_uop_fu_code_3; // @[util.scala:477:22]
reg out_reg_uop_fu_code_4; // @[util.scala:477:22]
reg out_reg_uop_fu_code_5; // @[util.scala:477:22]
reg out_reg_uop_fu_code_6; // @[util.scala:477:22]
reg out_reg_uop_fu_code_7; // @[util.scala:477:22]
reg out_reg_uop_fu_code_8; // @[util.scala:477:22]
reg out_reg_uop_fu_code_9; // @[util.scala:477:22]
reg out_reg_uop_iw_issued; // @[util.scala:477:22]
reg out_reg_uop_iw_issued_partial_agen; // @[util.scala:477:22]
reg out_reg_uop_iw_issued_partial_dgen; // @[util.scala:477:22]
reg out_reg_uop_iw_p1_speculative_child; // @[util.scala:477:22]
reg out_reg_uop_iw_p2_speculative_child; // @[util.scala:477:22]
reg out_reg_uop_iw_p1_bypass_hint; // @[util.scala:477:22]
reg out_reg_uop_iw_p2_bypass_hint; // @[util.scala:477:22]
reg out_reg_uop_iw_p3_bypass_hint; // @[util.scala:477:22]
reg out_reg_uop_dis_col_sel; // @[util.scala:477:22]
reg [3:0] out_reg_uop_br_mask; // @[util.scala:477:22]
reg [1:0] out_reg_uop_br_tag; // @[util.scala:477:22]
reg [3:0] out_reg_uop_br_type; // @[util.scala:477:22]
reg out_reg_uop_is_sfb; // @[util.scala:477:22]
reg out_reg_uop_is_fence; // @[util.scala:477:22]
reg out_reg_uop_is_fencei; // @[util.scala:477:22]
reg out_reg_uop_is_sfence; // @[util.scala:477:22]
reg out_reg_uop_is_amo; // @[util.scala:477:22]
reg out_reg_uop_is_eret; // @[util.scala:477:22]
reg out_reg_uop_is_sys_pc2epc; // @[util.scala:477:22]
reg out_reg_uop_is_rocc; // @[util.scala:477:22]
reg out_reg_uop_is_mov; // @[util.scala:477:22]
reg [3:0] out_reg_uop_ftq_idx; // @[util.scala:477:22]
reg out_reg_uop_edge_inst; // @[util.scala:477:22]
reg [5:0] out_reg_uop_pc_lob; // @[util.scala:477:22]
reg out_reg_uop_taken; // @[util.scala:477:22]
reg out_reg_uop_imm_rename; // @[util.scala:477:22]
reg [2:0] out_reg_uop_imm_sel; // @[util.scala:477:22]
reg [4:0] out_reg_uop_pimm; // @[util.scala:477:22]
reg [19:0] out_reg_uop_imm_packed; // @[util.scala:477:22]
reg [1:0] out_reg_uop_op1_sel; // @[util.scala:477:22]
reg [2:0] out_reg_uop_op2_sel; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_ldst; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_wen; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_ren1; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_ren2; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_ren3; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_swap12; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_swap23; // @[util.scala:477:22]
reg [1:0] out_reg_uop_fp_ctrl_typeTagIn; // @[util.scala:477:22]
reg [1:0] out_reg_uop_fp_ctrl_typeTagOut; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_fromint; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_toint; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_fastpipe; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_fma; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_div; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_sqrt; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_wflags; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_vec; // @[util.scala:477:22]
reg [4:0] out_reg_uop_rob_idx; // @[util.scala:477:22]
reg [3:0] out_reg_uop_ldq_idx; // @[util.scala:477:22]
reg [3:0] out_reg_uop_stq_idx; // @[util.scala:477:22]
reg [1:0] out_reg_uop_rxq_idx; // @[util.scala:477:22]
reg [5:0] out_reg_uop_pdst; // @[util.scala:477:22]
reg [5:0] out_reg_uop_prs1; // @[util.scala:477:22]
reg [5:0] out_reg_uop_prs2; // @[util.scala:477:22]
reg [5:0] out_reg_uop_prs3; // @[util.scala:477:22]
reg [3:0] out_reg_uop_ppred; // @[util.scala:477:22]
reg out_reg_uop_prs1_busy; // @[util.scala:477:22]
reg out_reg_uop_prs2_busy; // @[util.scala:477:22]
reg out_reg_uop_prs3_busy; // @[util.scala:477:22]
reg out_reg_uop_ppred_busy; // @[util.scala:477:22]
reg [5:0] out_reg_uop_stale_pdst; // @[util.scala:477:22]
reg out_reg_uop_exception; // @[util.scala:477:22]
reg [63:0] out_reg_uop_exc_cause; // @[util.scala:477:22]
reg [4:0] out_reg_uop_mem_cmd; // @[util.scala:477:22]
reg [1:0] out_reg_uop_mem_size; // @[util.scala:477:22]
reg out_reg_uop_mem_signed; // @[util.scala:477:22]
reg out_reg_uop_uses_ldq; // @[util.scala:477:22]
reg out_reg_uop_uses_stq; // @[util.scala:477:22]
reg out_reg_uop_is_unique; // @[util.scala:477:22]
reg out_reg_uop_flush_on_commit; // @[util.scala:477:22]
reg [2:0] out_reg_uop_csr_cmd; // @[util.scala:477:22]
reg out_reg_uop_ldst_is_rs1; // @[util.scala:477:22]
reg [5:0] out_reg_uop_ldst; // @[util.scala:477:22]
reg [5:0] out_reg_uop_lrs1; // @[util.scala:477:22]
reg [5:0] out_reg_uop_lrs2; // @[util.scala:477:22]
reg [5:0] out_reg_uop_lrs3; // @[util.scala:477:22]
reg [1:0] out_reg_uop_dst_rtype; // @[util.scala:477:22]
reg [1:0] out_reg_uop_lrs1_rtype; // @[util.scala:477:22]
reg [1:0] out_reg_uop_lrs2_rtype; // @[util.scala:477:22]
reg out_reg_uop_frs3_en; // @[util.scala:477:22]
reg out_reg_uop_fcn_dw; // @[util.scala:477:22]
reg [4:0] out_reg_uop_fcn_op; // @[util.scala:477:22]
reg out_reg_uop_fp_val; // @[util.scala:477:22]
reg [2:0] out_reg_uop_fp_rm; // @[util.scala:477:22]
reg [1:0] out_reg_uop_fp_typ; // @[util.scala:477:22]
reg out_reg_uop_xcpt_pf_if; // @[util.scala:477:22]
reg out_reg_uop_xcpt_ae_if; // @[util.scala:477:22]
reg out_reg_uop_xcpt_ma_if; // @[util.scala:477:22]
reg out_reg_uop_bp_debug_if; // @[util.scala:477:22]
reg out_reg_uop_bp_xcpt_if; // @[util.scala:477:22]
reg [2:0] out_reg_uop_debug_fsrc; // @[util.scala:477:22]
reg [2:0] out_reg_uop_debug_tsrc; // @[util.scala:477:22]
reg [33:0] out_reg_addr; // @[util.scala:477:22]
assign io_deq_bits_addr_0 = out_reg_addr; // @[util.scala:458:7, :477:22]
reg [63:0] out_reg_data; // @[util.scala:477:22]
assign io_deq_bits_data_0 = out_reg_data; // @[util.scala:458:7, :477:22]
reg out_reg_is_hella; // @[util.scala:477:22]
assign io_deq_bits_is_hella_0 = out_reg_is_hella; // @[util.scala:458:7, :477:22]
reg out_reg_tag_match; // @[util.scala:477:22]
assign io_deq_bits_tag_match_0 = out_reg_tag_match; // @[util.scala:458:7, :477:22]
reg [1:0] out_reg_old_meta_coh_state; // @[util.scala:477:22]
assign io_deq_bits_old_meta_coh_state_0 = out_reg_old_meta_coh_state; // @[util.scala:458:7, :477:22]
reg [21:0] out_reg_old_meta_tag; // @[util.scala:477:22]
assign io_deq_bits_old_meta_tag_0 = out_reg_old_meta_tag; // @[util.scala:458:7, :477:22]
reg [1:0] out_reg_way_en; // @[util.scala:477:22]
assign io_deq_bits_way_en_0 = out_reg_way_en; // @[util.scala:458:7, :477:22]
reg [4:0] out_reg_sdq_id; // @[util.scala:477:22]
assign io_deq_bits_sdq_id_0 = out_reg_sdq_id; // @[util.scala:458:7, :477:22]
reg out_valid; // @[util.scala:478:28]
assign io_deq_valid_0 = out_valid; // @[util.scala:458:7, :478:28]
wire _out_valid_T_4 = out_valid; // @[util.scala:478:28, :492:28]
reg [31:0] out_uop_inst; // @[util.scala:479:22]
assign io_deq_bits_uop_inst_0 = out_uop_inst; // @[util.scala:458:7, :479:22]
wire [31:0] out_uop_out_inst = out_uop_inst; // @[util.scala:104:23, :479:22]
reg [31:0] out_uop_debug_inst; // @[util.scala:479:22]
assign io_deq_bits_uop_debug_inst_0 = out_uop_debug_inst; // @[util.scala:458:7, :479:22]
wire [31:0] out_uop_out_debug_inst = out_uop_debug_inst; // @[util.scala:104:23, :479:22]
reg out_uop_is_rvc; // @[util.scala:479:22]
assign io_deq_bits_uop_is_rvc_0 = out_uop_is_rvc; // @[util.scala:458:7, :479:22]
wire out_uop_out_is_rvc = out_uop_is_rvc; // @[util.scala:104:23, :479:22]
reg [33:0] out_uop_debug_pc; // @[util.scala:479:22]
assign io_deq_bits_uop_debug_pc_0 = out_uop_debug_pc; // @[util.scala:458:7, :479:22]
wire [33:0] out_uop_out_debug_pc = out_uop_debug_pc; // @[util.scala:104:23, :479:22]
reg out_uop_iq_type_0; // @[util.scala:479:22]
assign io_deq_bits_uop_iq_type_0_0 = out_uop_iq_type_0; // @[util.scala:458:7, :479:22]
wire out_uop_out_iq_type_0 = out_uop_iq_type_0; // @[util.scala:104:23, :479:22]
reg out_uop_iq_type_1; // @[util.scala:479:22]
assign io_deq_bits_uop_iq_type_1_0 = out_uop_iq_type_1; // @[util.scala:458:7, :479:22]
wire out_uop_out_iq_type_1 = out_uop_iq_type_1; // @[util.scala:104:23, :479:22]
reg out_uop_iq_type_2; // @[util.scala:479:22]
assign io_deq_bits_uop_iq_type_2_0 = out_uop_iq_type_2; // @[util.scala:458:7, :479:22]
wire out_uop_out_iq_type_2 = out_uop_iq_type_2; // @[util.scala:104:23, :479:22]
reg out_uop_iq_type_3; // @[util.scala:479:22]
assign io_deq_bits_uop_iq_type_3_0 = out_uop_iq_type_3; // @[util.scala:458:7, :479:22]
wire out_uop_out_iq_type_3 = out_uop_iq_type_3; // @[util.scala:104:23, :479:22]
reg out_uop_fu_code_0; // @[util.scala:479:22]
assign io_deq_bits_uop_fu_code_0_0 = out_uop_fu_code_0; // @[util.scala:458:7, :479:22]
wire out_uop_out_fu_code_0 = out_uop_fu_code_0; // @[util.scala:104:23, :479:22]
reg out_uop_fu_code_1; // @[util.scala:479:22]
assign io_deq_bits_uop_fu_code_1_0 = out_uop_fu_code_1; // @[util.scala:458:7, :479:22]
wire out_uop_out_fu_code_1 = out_uop_fu_code_1; // @[util.scala:104:23, :479:22]
reg out_uop_fu_code_2; // @[util.scala:479:22]
assign io_deq_bits_uop_fu_code_2_0 = out_uop_fu_code_2; // @[util.scala:458:7, :479:22]
wire out_uop_out_fu_code_2 = out_uop_fu_code_2; // @[util.scala:104:23, :479:22]
reg out_uop_fu_code_3; // @[util.scala:479:22]
assign io_deq_bits_uop_fu_code_3_0 = out_uop_fu_code_3; // @[util.scala:458:7, :479:22]
wire out_uop_out_fu_code_3 = out_uop_fu_code_3; // @[util.scala:104:23, :479:22]
reg out_uop_fu_code_4; // @[util.scala:479:22]
assign io_deq_bits_uop_fu_code_4_0 = out_uop_fu_code_4; // @[util.scala:458:7, :479:22]
wire out_uop_out_fu_code_4 = out_uop_fu_code_4; // @[util.scala:104:23, :479:22]
reg out_uop_fu_code_5; // @[util.scala:479:22]
assign io_deq_bits_uop_fu_code_5_0 = out_uop_fu_code_5; // @[util.scala:458:7, :479:22]
wire out_uop_out_fu_code_5 = out_uop_fu_code_5; // @[util.scala:104:23, :479:22]
reg out_uop_fu_code_6; // @[util.scala:479:22]
assign io_deq_bits_uop_fu_code_6_0 = out_uop_fu_code_6; // @[util.scala:458:7, :479:22]
wire out_uop_out_fu_code_6 = out_uop_fu_code_6; // @[util.scala:104:23, :479:22]
reg out_uop_fu_code_7; // @[util.scala:479:22]
assign io_deq_bits_uop_fu_code_7_0 = out_uop_fu_code_7; // @[util.scala:458:7, :479:22]
wire out_uop_out_fu_code_7 = out_uop_fu_code_7; // @[util.scala:104:23, :479:22]
reg out_uop_fu_code_8; // @[util.scala:479:22]
assign io_deq_bits_uop_fu_code_8_0 = out_uop_fu_code_8; // @[util.scala:458:7, :479:22]
wire out_uop_out_fu_code_8 = out_uop_fu_code_8; // @[util.scala:104:23, :479:22]
reg out_uop_fu_code_9; // @[util.scala:479:22]
assign io_deq_bits_uop_fu_code_9_0 = out_uop_fu_code_9; // @[util.scala:458:7, :479:22]
wire out_uop_out_fu_code_9 = out_uop_fu_code_9; // @[util.scala:104:23, :479:22]
reg out_uop_iw_issued; // @[util.scala:479:22]
assign io_deq_bits_uop_iw_issued_0 = out_uop_iw_issued; // @[util.scala:458:7, :479:22]
wire out_uop_out_iw_issued = out_uop_iw_issued; // @[util.scala:104:23, :479:22]
reg out_uop_iw_issued_partial_agen; // @[util.scala:479:22]
assign io_deq_bits_uop_iw_issued_partial_agen_0 = out_uop_iw_issued_partial_agen; // @[util.scala:458:7, :479:22]
wire out_uop_out_iw_issued_partial_agen = out_uop_iw_issued_partial_agen; // @[util.scala:104:23, :479:22]
reg out_uop_iw_issued_partial_dgen; // @[util.scala:479:22]
assign io_deq_bits_uop_iw_issued_partial_dgen_0 = out_uop_iw_issued_partial_dgen; // @[util.scala:458:7, :479:22]
wire out_uop_out_iw_issued_partial_dgen = out_uop_iw_issued_partial_dgen; // @[util.scala:104:23, :479:22]
reg out_uop_iw_p1_speculative_child; // @[util.scala:479:22]
assign io_deq_bits_uop_iw_p1_speculative_child_0 = out_uop_iw_p1_speculative_child; // @[util.scala:458:7, :479:22]
wire out_uop_out_iw_p1_speculative_child = out_uop_iw_p1_speculative_child; // @[util.scala:104:23, :479:22]
reg out_uop_iw_p2_speculative_child; // @[util.scala:479:22]
assign io_deq_bits_uop_iw_p2_speculative_child_0 = out_uop_iw_p2_speculative_child; // @[util.scala:458:7, :479:22]
wire out_uop_out_iw_p2_speculative_child = out_uop_iw_p2_speculative_child; // @[util.scala:104:23, :479:22]
reg out_uop_iw_p1_bypass_hint; // @[util.scala:479:22]
assign io_deq_bits_uop_iw_p1_bypass_hint_0 = out_uop_iw_p1_bypass_hint; // @[util.scala:458:7, :479:22]
wire out_uop_out_iw_p1_bypass_hint = out_uop_iw_p1_bypass_hint; // @[util.scala:104:23, :479:22]
reg out_uop_iw_p2_bypass_hint; // @[util.scala:479:22]
assign io_deq_bits_uop_iw_p2_bypass_hint_0 = out_uop_iw_p2_bypass_hint; // @[util.scala:458:7, :479:22]
wire out_uop_out_iw_p2_bypass_hint = out_uop_iw_p2_bypass_hint; // @[util.scala:104:23, :479:22]
reg out_uop_iw_p3_bypass_hint; // @[util.scala:479:22]
assign io_deq_bits_uop_iw_p3_bypass_hint_0 = out_uop_iw_p3_bypass_hint; // @[util.scala:458:7, :479:22]
wire out_uop_out_iw_p3_bypass_hint = out_uop_iw_p3_bypass_hint; // @[util.scala:104:23, :479:22]
reg out_uop_dis_col_sel; // @[util.scala:479:22]
assign io_deq_bits_uop_dis_col_sel_0 = out_uop_dis_col_sel; // @[util.scala:458:7, :479:22]
wire out_uop_out_dis_col_sel = out_uop_dis_col_sel; // @[util.scala:104:23, :479:22]
reg [3:0] out_uop_br_mask; // @[util.scala:479:22]
assign io_deq_bits_uop_br_mask_0 = out_uop_br_mask; // @[util.scala:458:7, :479:22]
wire [3:0] _out_uop_out_br_mask_T_1 = out_uop_br_mask; // @[util.scala:93:25, :479:22]
reg [1:0] out_uop_br_tag; // @[util.scala:479:22]
assign io_deq_bits_uop_br_tag_0 = out_uop_br_tag; // @[util.scala:458:7, :479:22]
wire [1:0] out_uop_out_br_tag = out_uop_br_tag; // @[util.scala:104:23, :479:22]
reg [3:0] out_uop_br_type; // @[util.scala:479:22]
assign io_deq_bits_uop_br_type_0 = out_uop_br_type; // @[util.scala:458:7, :479:22]
wire [3:0] out_uop_out_br_type = out_uop_br_type; // @[util.scala:104:23, :479:22]
reg out_uop_is_sfb; // @[util.scala:479:22]
assign io_deq_bits_uop_is_sfb_0 = out_uop_is_sfb; // @[util.scala:458:7, :479:22]
wire out_uop_out_is_sfb = out_uop_is_sfb; // @[util.scala:104:23, :479:22]
reg out_uop_is_fence; // @[util.scala:479:22]
assign io_deq_bits_uop_is_fence_0 = out_uop_is_fence; // @[util.scala:458:7, :479:22]
wire out_uop_out_is_fence = out_uop_is_fence; // @[util.scala:104:23, :479:22]
reg out_uop_is_fencei; // @[util.scala:479:22]
assign io_deq_bits_uop_is_fencei_0 = out_uop_is_fencei; // @[util.scala:458:7, :479:22]
wire out_uop_out_is_fencei = out_uop_is_fencei; // @[util.scala:104:23, :479:22]
reg out_uop_is_sfence; // @[util.scala:479:22]
assign io_deq_bits_uop_is_sfence_0 = out_uop_is_sfence; // @[util.scala:458:7, :479:22]
wire out_uop_out_is_sfence = out_uop_is_sfence; // @[util.scala:104:23, :479:22]
reg out_uop_is_amo; // @[util.scala:479:22]
assign io_deq_bits_uop_is_amo_0 = out_uop_is_amo; // @[util.scala:458:7, :479:22]
wire out_uop_out_is_amo = out_uop_is_amo; // @[util.scala:104:23, :479:22]
reg out_uop_is_eret; // @[util.scala:479:22]
assign io_deq_bits_uop_is_eret_0 = out_uop_is_eret; // @[util.scala:458:7, :479:22]
wire out_uop_out_is_eret = out_uop_is_eret; // @[util.scala:104:23, :479:22]
reg out_uop_is_sys_pc2epc; // @[util.scala:479:22]
assign io_deq_bits_uop_is_sys_pc2epc_0 = out_uop_is_sys_pc2epc; // @[util.scala:458:7, :479:22]
wire out_uop_out_is_sys_pc2epc = out_uop_is_sys_pc2epc; // @[util.scala:104:23, :479:22]
reg out_uop_is_rocc; // @[util.scala:479:22]
assign io_deq_bits_uop_is_rocc_0 = out_uop_is_rocc; // @[util.scala:458:7, :479:22]
wire out_uop_out_is_rocc = out_uop_is_rocc; // @[util.scala:104:23, :479:22]
reg out_uop_is_mov; // @[util.scala:479:22]
assign io_deq_bits_uop_is_mov_0 = out_uop_is_mov; // @[util.scala:458:7, :479:22]
wire out_uop_out_is_mov = out_uop_is_mov; // @[util.scala:104:23, :479:22]
reg [3:0] out_uop_ftq_idx; // @[util.scala:479:22]
assign io_deq_bits_uop_ftq_idx_0 = out_uop_ftq_idx; // @[util.scala:458:7, :479:22]
wire [3:0] out_uop_out_ftq_idx = out_uop_ftq_idx; // @[util.scala:104:23, :479:22]
reg out_uop_edge_inst; // @[util.scala:479:22]
assign io_deq_bits_uop_edge_inst_0 = out_uop_edge_inst; // @[util.scala:458:7, :479:22]
wire out_uop_out_edge_inst = out_uop_edge_inst; // @[util.scala:104:23, :479:22]
reg [5:0] out_uop_pc_lob; // @[util.scala:479:22]
assign io_deq_bits_uop_pc_lob_0 = out_uop_pc_lob; // @[util.scala:458:7, :479:22]
wire [5:0] out_uop_out_pc_lob = out_uop_pc_lob; // @[util.scala:104:23, :479:22]
reg out_uop_taken; // @[util.scala:479:22]
assign io_deq_bits_uop_taken_0 = out_uop_taken; // @[util.scala:458:7, :479:22]
wire out_uop_out_taken = out_uop_taken; // @[util.scala:104:23, :479:22]
reg out_uop_imm_rename; // @[util.scala:479:22]
assign io_deq_bits_uop_imm_rename_0 = out_uop_imm_rename; // @[util.scala:458:7, :479:22]
wire out_uop_out_imm_rename = out_uop_imm_rename; // @[util.scala:104:23, :479:22]
reg [2:0] out_uop_imm_sel; // @[util.scala:479:22]
assign io_deq_bits_uop_imm_sel_0 = out_uop_imm_sel; // @[util.scala:458:7, :479:22]
wire [2:0] out_uop_out_imm_sel = out_uop_imm_sel; // @[util.scala:104:23, :479:22]
reg [4:0] out_uop_pimm; // @[util.scala:479:22]
assign io_deq_bits_uop_pimm_0 = out_uop_pimm; // @[util.scala:458:7, :479:22]
wire [4:0] out_uop_out_pimm = out_uop_pimm; // @[util.scala:104:23, :479:22]
reg [19:0] out_uop_imm_packed; // @[util.scala:479:22]
assign io_deq_bits_uop_imm_packed_0 = out_uop_imm_packed; // @[util.scala:458:7, :479:22]
wire [19:0] out_uop_out_imm_packed = out_uop_imm_packed; // @[util.scala:104:23, :479:22]
reg [1:0] out_uop_op1_sel; // @[util.scala:479:22]
assign io_deq_bits_uop_op1_sel_0 = out_uop_op1_sel; // @[util.scala:458:7, :479:22]
wire [1:0] out_uop_out_op1_sel = out_uop_op1_sel; // @[util.scala:104:23, :479:22]
reg [2:0] out_uop_op2_sel; // @[util.scala:479:22]
assign io_deq_bits_uop_op2_sel_0 = out_uop_op2_sel; // @[util.scala:458:7, :479:22]
wire [2:0] out_uop_out_op2_sel = out_uop_op2_sel; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_ldst; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_ldst_0 = out_uop_fp_ctrl_ldst; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_ldst = out_uop_fp_ctrl_ldst; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_wen; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_wen_0 = out_uop_fp_ctrl_wen; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_wen = out_uop_fp_ctrl_wen; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_ren1; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_ren1_0 = out_uop_fp_ctrl_ren1; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_ren1 = out_uop_fp_ctrl_ren1; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_ren2; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_ren2_0 = out_uop_fp_ctrl_ren2; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_ren2 = out_uop_fp_ctrl_ren2; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_ren3; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_ren3_0 = out_uop_fp_ctrl_ren3; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_ren3 = out_uop_fp_ctrl_ren3; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_swap12; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_swap12_0 = out_uop_fp_ctrl_swap12; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_swap12 = out_uop_fp_ctrl_swap12; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_swap23; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_swap23_0 = out_uop_fp_ctrl_swap23; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_swap23 = out_uop_fp_ctrl_swap23; // @[util.scala:104:23, :479:22]
reg [1:0] out_uop_fp_ctrl_typeTagIn; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_typeTagIn_0 = out_uop_fp_ctrl_typeTagIn; // @[util.scala:458:7, :479:22]
wire [1:0] out_uop_out_fp_ctrl_typeTagIn = out_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23, :479:22]
reg [1:0] out_uop_fp_ctrl_typeTagOut; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_typeTagOut_0 = out_uop_fp_ctrl_typeTagOut; // @[util.scala:458:7, :479:22]
wire [1:0] out_uop_out_fp_ctrl_typeTagOut = out_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_fromint; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_fromint_0 = out_uop_fp_ctrl_fromint; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_fromint = out_uop_fp_ctrl_fromint; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_toint; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_toint_0 = out_uop_fp_ctrl_toint; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_toint = out_uop_fp_ctrl_toint; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_fastpipe; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_fastpipe_0 = out_uop_fp_ctrl_fastpipe; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_fastpipe = out_uop_fp_ctrl_fastpipe; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_fma; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_fma_0 = out_uop_fp_ctrl_fma; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_fma = out_uop_fp_ctrl_fma; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_div; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_div_0 = out_uop_fp_ctrl_div; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_div = out_uop_fp_ctrl_div; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_sqrt; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_sqrt_0 = out_uop_fp_ctrl_sqrt; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_sqrt = out_uop_fp_ctrl_sqrt; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_wflags; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_wflags_0 = out_uop_fp_ctrl_wflags; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_wflags = out_uop_fp_ctrl_wflags; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_vec; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_vec_0 = out_uop_fp_ctrl_vec; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_vec = out_uop_fp_ctrl_vec; // @[util.scala:104:23, :479:22]
reg [4:0] out_uop_rob_idx; // @[util.scala:479:22]
assign io_deq_bits_uop_rob_idx_0 = out_uop_rob_idx; // @[util.scala:458:7, :479:22]
wire [4:0] out_uop_out_rob_idx = out_uop_rob_idx; // @[util.scala:104:23, :479:22]
reg [3:0] out_uop_ldq_idx; // @[util.scala:479:22]
assign io_deq_bits_uop_ldq_idx_0 = out_uop_ldq_idx; // @[util.scala:458:7, :479:22]
wire [3:0] out_uop_out_ldq_idx = out_uop_ldq_idx; // @[util.scala:104:23, :479:22]
reg [3:0] out_uop_stq_idx; // @[util.scala:479:22]
assign io_deq_bits_uop_stq_idx_0 = out_uop_stq_idx; // @[util.scala:458:7, :479:22]
wire [3:0] out_uop_out_stq_idx = out_uop_stq_idx; // @[util.scala:104:23, :479:22]
reg [1:0] out_uop_rxq_idx; // @[util.scala:479:22]
assign io_deq_bits_uop_rxq_idx_0 = out_uop_rxq_idx; // @[util.scala:458:7, :479:22]
wire [1:0] out_uop_out_rxq_idx = out_uop_rxq_idx; // @[util.scala:104:23, :479:22]
reg [5:0] out_uop_pdst; // @[util.scala:479:22]
assign io_deq_bits_uop_pdst_0 = out_uop_pdst; // @[util.scala:458:7, :479:22]
wire [5:0] out_uop_out_pdst = out_uop_pdst; // @[util.scala:104:23, :479:22]
reg [5:0] out_uop_prs1; // @[util.scala:479:22]
assign io_deq_bits_uop_prs1_0 = out_uop_prs1; // @[util.scala:458:7, :479:22]
wire [5:0] out_uop_out_prs1 = out_uop_prs1; // @[util.scala:104:23, :479:22]
reg [5:0] out_uop_prs2; // @[util.scala:479:22]
assign io_deq_bits_uop_prs2_0 = out_uop_prs2; // @[util.scala:458:7, :479:22]
wire [5:0] out_uop_out_prs2 = out_uop_prs2; // @[util.scala:104:23, :479:22]
reg [5:0] out_uop_prs3; // @[util.scala:479:22]
assign io_deq_bits_uop_prs3_0 = out_uop_prs3; // @[util.scala:458:7, :479:22]
wire [5:0] out_uop_out_prs3 = out_uop_prs3; // @[util.scala:104:23, :479:22]
reg [3:0] out_uop_ppred; // @[util.scala:479:22]
assign io_deq_bits_uop_ppred_0 = out_uop_ppred; // @[util.scala:458:7, :479:22]
wire [3:0] out_uop_out_ppred = out_uop_ppred; // @[util.scala:104:23, :479:22]
reg out_uop_prs1_busy; // @[util.scala:479:22]
assign io_deq_bits_uop_prs1_busy_0 = out_uop_prs1_busy; // @[util.scala:458:7, :479:22]
wire out_uop_out_prs1_busy = out_uop_prs1_busy; // @[util.scala:104:23, :479:22]
reg out_uop_prs2_busy; // @[util.scala:479:22]
assign io_deq_bits_uop_prs2_busy_0 = out_uop_prs2_busy; // @[util.scala:458:7, :479:22]
wire out_uop_out_prs2_busy = out_uop_prs2_busy; // @[util.scala:104:23, :479:22]
reg out_uop_prs3_busy; // @[util.scala:479:22]
assign io_deq_bits_uop_prs3_busy_0 = out_uop_prs3_busy; // @[util.scala:458:7, :479:22]
wire out_uop_out_prs3_busy = out_uop_prs3_busy; // @[util.scala:104:23, :479:22]
reg out_uop_ppred_busy; // @[util.scala:479:22]
assign io_deq_bits_uop_ppred_busy_0 = out_uop_ppred_busy; // @[util.scala:458:7, :479:22]
wire out_uop_out_ppred_busy = out_uop_ppred_busy; // @[util.scala:104:23, :479:22]
reg [5:0] out_uop_stale_pdst; // @[util.scala:479:22]
assign io_deq_bits_uop_stale_pdst_0 = out_uop_stale_pdst; // @[util.scala:458:7, :479:22]
wire [5:0] out_uop_out_stale_pdst = out_uop_stale_pdst; // @[util.scala:104:23, :479:22]
reg out_uop_exception; // @[util.scala:479:22]
assign io_deq_bits_uop_exception_0 = out_uop_exception; // @[util.scala:458:7, :479:22]
wire out_uop_out_exception = out_uop_exception; // @[util.scala:104:23, :479:22]
reg [63:0] out_uop_exc_cause; // @[util.scala:479:22]
assign io_deq_bits_uop_exc_cause_0 = out_uop_exc_cause; // @[util.scala:458:7, :479:22]
wire [63:0] out_uop_out_exc_cause = out_uop_exc_cause; // @[util.scala:104:23, :479:22]
reg [4:0] out_uop_mem_cmd; // @[util.scala:479:22]
assign io_deq_bits_uop_mem_cmd_0 = out_uop_mem_cmd; // @[util.scala:458:7, :479:22]
wire [4:0] out_uop_out_mem_cmd = out_uop_mem_cmd; // @[util.scala:104:23, :479:22]
reg [1:0] out_uop_mem_size; // @[util.scala:479:22]
assign io_deq_bits_uop_mem_size_0 = out_uop_mem_size; // @[util.scala:458:7, :479:22]
wire [1:0] out_uop_out_mem_size = out_uop_mem_size; // @[util.scala:104:23, :479:22]
reg out_uop_mem_signed; // @[util.scala:479:22]
assign io_deq_bits_uop_mem_signed_0 = out_uop_mem_signed; // @[util.scala:458:7, :479:22]
wire out_uop_out_mem_signed = out_uop_mem_signed; // @[util.scala:104:23, :479:22]
reg out_uop_uses_ldq; // @[util.scala:479:22]
assign io_deq_bits_uop_uses_ldq_0 = out_uop_uses_ldq; // @[util.scala:458:7, :479:22]
wire out_uop_out_uses_ldq = out_uop_uses_ldq; // @[util.scala:104:23, :479:22]
reg out_uop_uses_stq; // @[util.scala:479:22]
assign io_deq_bits_uop_uses_stq_0 = out_uop_uses_stq; // @[util.scala:458:7, :479:22]
wire out_uop_out_uses_stq = out_uop_uses_stq; // @[util.scala:104:23, :479:22]
reg out_uop_is_unique; // @[util.scala:479:22]
assign io_deq_bits_uop_is_unique_0 = out_uop_is_unique; // @[util.scala:458:7, :479:22]
wire out_uop_out_is_unique = out_uop_is_unique; // @[util.scala:104:23, :479:22]
reg out_uop_flush_on_commit; // @[util.scala:479:22]
assign io_deq_bits_uop_flush_on_commit_0 = out_uop_flush_on_commit; // @[util.scala:458:7, :479:22]
wire out_uop_out_flush_on_commit = out_uop_flush_on_commit; // @[util.scala:104:23, :479:22]
reg [2:0] out_uop_csr_cmd; // @[util.scala:479:22]
assign io_deq_bits_uop_csr_cmd_0 = out_uop_csr_cmd; // @[util.scala:458:7, :479:22]
wire [2:0] out_uop_out_csr_cmd = out_uop_csr_cmd; // @[util.scala:104:23, :479:22]
reg out_uop_ldst_is_rs1; // @[util.scala:479:22]
assign io_deq_bits_uop_ldst_is_rs1_0 = out_uop_ldst_is_rs1; // @[util.scala:458:7, :479:22]
wire out_uop_out_ldst_is_rs1 = out_uop_ldst_is_rs1; // @[util.scala:104:23, :479:22]
reg [5:0] out_uop_ldst; // @[util.scala:479:22]
assign io_deq_bits_uop_ldst_0 = out_uop_ldst; // @[util.scala:458:7, :479:22]
wire [5:0] out_uop_out_ldst = out_uop_ldst; // @[util.scala:104:23, :479:22]
reg [5:0] out_uop_lrs1; // @[util.scala:479:22]
assign io_deq_bits_uop_lrs1_0 = out_uop_lrs1; // @[util.scala:458:7, :479:22]
wire [5:0] out_uop_out_lrs1 = out_uop_lrs1; // @[util.scala:104:23, :479:22]
reg [5:0] out_uop_lrs2; // @[util.scala:479:22]
assign io_deq_bits_uop_lrs2_0 = out_uop_lrs2; // @[util.scala:458:7, :479:22]
wire [5:0] out_uop_out_lrs2 = out_uop_lrs2; // @[util.scala:104:23, :479:22]
reg [5:0] out_uop_lrs3; // @[util.scala:479:22]
assign io_deq_bits_uop_lrs3_0 = out_uop_lrs3; // @[util.scala:458:7, :479:22]
wire [5:0] out_uop_out_lrs3 = out_uop_lrs3; // @[util.scala:104:23, :479:22]
reg [1:0] out_uop_dst_rtype; // @[util.scala:479:22]
assign io_deq_bits_uop_dst_rtype_0 = out_uop_dst_rtype; // @[util.scala:458:7, :479:22]
wire [1:0] out_uop_out_dst_rtype = out_uop_dst_rtype; // @[util.scala:104:23, :479:22]
reg [1:0] out_uop_lrs1_rtype; // @[util.scala:479:22]
assign io_deq_bits_uop_lrs1_rtype_0 = out_uop_lrs1_rtype; // @[util.scala:458:7, :479:22]
wire [1:0] out_uop_out_lrs1_rtype = out_uop_lrs1_rtype; // @[util.scala:104:23, :479:22]
reg [1:0] out_uop_lrs2_rtype; // @[util.scala:479:22]
assign io_deq_bits_uop_lrs2_rtype_0 = out_uop_lrs2_rtype; // @[util.scala:458:7, :479:22]
wire [1:0] out_uop_out_lrs2_rtype = out_uop_lrs2_rtype; // @[util.scala:104:23, :479:22]
reg out_uop_frs3_en; // @[util.scala:479:22]
assign io_deq_bits_uop_frs3_en_0 = out_uop_frs3_en; // @[util.scala:458:7, :479:22]
wire out_uop_out_frs3_en = out_uop_frs3_en; // @[util.scala:104:23, :479:22]
reg out_uop_fcn_dw; // @[util.scala:479:22]
assign io_deq_bits_uop_fcn_dw_0 = out_uop_fcn_dw; // @[util.scala:458:7, :479:22]
wire out_uop_out_fcn_dw = out_uop_fcn_dw; // @[util.scala:104:23, :479:22]
reg [4:0] out_uop_fcn_op; // @[util.scala:479:22]
assign io_deq_bits_uop_fcn_op_0 = out_uop_fcn_op; // @[util.scala:458:7, :479:22]
wire [4:0] out_uop_out_fcn_op = out_uop_fcn_op; // @[util.scala:104:23, :479:22]
reg out_uop_fp_val; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_val_0 = out_uop_fp_val; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_val = out_uop_fp_val; // @[util.scala:104:23, :479:22]
reg [2:0] out_uop_fp_rm; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_rm_0 = out_uop_fp_rm; // @[util.scala:458:7, :479:22]
wire [2:0] out_uop_out_fp_rm = out_uop_fp_rm; // @[util.scala:104:23, :479:22]
reg [1:0] out_uop_fp_typ; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_typ_0 = out_uop_fp_typ; // @[util.scala:458:7, :479:22]
wire [1:0] out_uop_out_fp_typ = out_uop_fp_typ; // @[util.scala:104:23, :479:22]
reg out_uop_xcpt_pf_if; // @[util.scala:479:22]
assign io_deq_bits_uop_xcpt_pf_if_0 = out_uop_xcpt_pf_if; // @[util.scala:458:7, :479:22]
wire out_uop_out_xcpt_pf_if = out_uop_xcpt_pf_if; // @[util.scala:104:23, :479:22]
reg out_uop_xcpt_ae_if; // @[util.scala:479:22]
assign io_deq_bits_uop_xcpt_ae_if_0 = out_uop_xcpt_ae_if; // @[util.scala:458:7, :479:22]
wire out_uop_out_xcpt_ae_if = out_uop_xcpt_ae_if; // @[util.scala:104:23, :479:22]
reg out_uop_xcpt_ma_if; // @[util.scala:479:22]
assign io_deq_bits_uop_xcpt_ma_if_0 = out_uop_xcpt_ma_if; // @[util.scala:458:7, :479:22]
wire out_uop_out_xcpt_ma_if = out_uop_xcpt_ma_if; // @[util.scala:104:23, :479:22]
reg out_uop_bp_debug_if; // @[util.scala:479:22]
assign io_deq_bits_uop_bp_debug_if_0 = out_uop_bp_debug_if; // @[util.scala:458:7, :479:22]
wire out_uop_out_bp_debug_if = out_uop_bp_debug_if; // @[util.scala:104:23, :479:22]
reg out_uop_bp_xcpt_if; // @[util.scala:479:22]
assign io_deq_bits_uop_bp_xcpt_if_0 = out_uop_bp_xcpt_if; // @[util.scala:458:7, :479:22]
wire out_uop_out_bp_xcpt_if = out_uop_bp_xcpt_if; // @[util.scala:104:23, :479:22]
reg [2:0] out_uop_debug_fsrc; // @[util.scala:479:22]
assign io_deq_bits_uop_debug_fsrc_0 = out_uop_debug_fsrc; // @[util.scala:458:7, :479:22]
wire [2:0] out_uop_out_debug_fsrc = out_uop_debug_fsrc; // @[util.scala:104:23, :479:22]
reg [2:0] out_uop_debug_tsrc; // @[util.scala:479:22]
assign io_deq_bits_uop_debug_tsrc_0 = out_uop_debug_tsrc; // @[util.scala:458:7, :479:22]
wire [2:0] out_uop_out_debug_tsrc = out_uop_debug_tsrc; // @[util.scala:104:23, :479:22]
wire _io_empty_T = ~out_valid; // @[util.scala:478:28, :484:34]
assign _io_empty_T_1 = _main_io_empty & _io_empty_T; // @[util.scala:476:22, :484:{31,34}]
assign io_empty_0 = _io_empty_T_1; // @[util.scala:458:7, :484:31]
wire [4:0] _io_count_T = {1'h0, _main_io_count} + {4'h0, out_valid}; // @[util.scala:126:51, :458:7, :463:14, :476:22, :478:28, :485:31]
assign _io_count_T_1 = _io_count_T[3:0]; // @[util.scala:485:31]
assign io_count = _io_count_T_1; // @[util.scala:458:7, :485:31]
wire [3:0] out_uop_out_br_mask; // @[util.scala:104:23]
assign out_uop_out_br_mask = _out_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23]
wire _out_valid_T_7 = _out_valid_T_4; // @[util.scala:492:{28,80}]
wire main_io_deq_ready = io_deq_ready_0 & io_deq_valid_0 | ~out_valid; // @[Decoupled.scala:51:35]
wire _out_valid_T_15 = _out_valid_T_12; // @[util.scala:496:{38,103}]
wire [3:0] _out_uop_out_br_mask_T_3; // @[util.scala:93:25]
wire out_uop_out_1_iq_type_0; // @[util.scala:104:23]
wire out_uop_out_1_iq_type_1; // @[util.scala:104:23]
wire out_uop_out_1_iq_type_2; // @[util.scala:104:23]
wire out_uop_out_1_iq_type_3; // @[util.scala:104:23]
wire out_uop_out_1_fu_code_0; // @[util.scala:104:23]
wire out_uop_out_1_fu_code_1; // @[util.scala:104:23]
wire out_uop_out_1_fu_code_2; // @[util.scala:104:23]
wire out_uop_out_1_fu_code_3; // @[util.scala:104:23]
wire out_uop_out_1_fu_code_4; // @[util.scala:104:23]
wire out_uop_out_1_fu_code_5; // @[util.scala:104:23]
wire out_uop_out_1_fu_code_6; // @[util.scala:104:23]
wire out_uop_out_1_fu_code_7; // @[util.scala:104:23]
wire out_uop_out_1_fu_code_8; // @[util.scala:104:23]
wire out_uop_out_1_fu_code_9; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_ldst; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_wen; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_ren1; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_ren2; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_ren3; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_swap12; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_swap23; // @[util.scala:104:23]
wire [1:0] out_uop_out_1_fp_ctrl_typeTagIn; // @[util.scala:104:23]
wire [1:0] out_uop_out_1_fp_ctrl_typeTagOut; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_fromint; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_toint; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_fastpipe; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_fma; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_div; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_sqrt; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_wflags; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_vec; // @[util.scala:104:23]
wire [31:0] out_uop_out_1_inst; // @[util.scala:104:23]
wire [31:0] out_uop_out_1_debug_inst; // @[util.scala:104:23]
wire out_uop_out_1_is_rvc; // @[util.scala:104:23]
wire [33:0] out_uop_out_1_debug_pc; // @[util.scala:104:23]
wire out_uop_out_1_iw_issued; // @[util.scala:104:23]
wire out_uop_out_1_iw_issued_partial_agen; // @[util.scala:104:23]
wire out_uop_out_1_iw_issued_partial_dgen; // @[util.scala:104:23]
wire out_uop_out_1_iw_p1_speculative_child; // @[util.scala:104:23]
wire out_uop_out_1_iw_p2_speculative_child; // @[util.scala:104:23]
wire out_uop_out_1_iw_p1_bypass_hint; // @[util.scala:104:23]
wire out_uop_out_1_iw_p2_bypass_hint; // @[util.scala:104:23]
wire out_uop_out_1_iw_p3_bypass_hint; // @[util.scala:104:23]
wire out_uop_out_1_dis_col_sel; // @[util.scala:104:23]
wire [3:0] out_uop_out_1_br_mask; // @[util.scala:104:23]
wire [1:0] out_uop_out_1_br_tag; // @[util.scala:104:23]
wire [3:0] out_uop_out_1_br_type; // @[util.scala:104:23]
wire out_uop_out_1_is_sfb; // @[util.scala:104:23]
wire out_uop_out_1_is_fence; // @[util.scala:104:23]
wire out_uop_out_1_is_fencei; // @[util.scala:104:23]
wire out_uop_out_1_is_sfence; // @[util.scala:104:23]
wire out_uop_out_1_is_amo; // @[util.scala:104:23]
wire out_uop_out_1_is_eret; // @[util.scala:104:23]
wire out_uop_out_1_is_sys_pc2epc; // @[util.scala:104:23]
wire out_uop_out_1_is_rocc; // @[util.scala:104:23]
wire out_uop_out_1_is_mov; // @[util.scala:104:23]
wire [3:0] out_uop_out_1_ftq_idx; // @[util.scala:104:23]
wire out_uop_out_1_edge_inst; // @[util.scala:104:23]
wire [5:0] out_uop_out_1_pc_lob; // @[util.scala:104:23]
wire out_uop_out_1_taken; // @[util.scala:104:23]
wire out_uop_out_1_imm_rename; // @[util.scala:104:23]
wire [2:0] out_uop_out_1_imm_sel; // @[util.scala:104:23]
wire [4:0] out_uop_out_1_pimm; // @[util.scala:104:23]
wire [19:0] out_uop_out_1_imm_packed; // @[util.scala:104:23]
wire [1:0] out_uop_out_1_op1_sel; // @[util.scala:104:23]
wire [2:0] out_uop_out_1_op2_sel; // @[util.scala:104:23]
wire [4:0] out_uop_out_1_rob_idx; // @[util.scala:104:23]
wire [3:0] out_uop_out_1_ldq_idx; // @[util.scala:104:23]
wire [3:0] out_uop_out_1_stq_idx; // @[util.scala:104:23]
wire [1:0] out_uop_out_1_rxq_idx; // @[util.scala:104:23]
wire [5:0] out_uop_out_1_pdst; // @[util.scala:104:23]
wire [5:0] out_uop_out_1_prs1; // @[util.scala:104:23]
wire [5:0] out_uop_out_1_prs2; // @[util.scala:104:23]
wire [5:0] out_uop_out_1_prs3; // @[util.scala:104:23]
wire [3:0] out_uop_out_1_ppred; // @[util.scala:104:23]
wire out_uop_out_1_prs1_busy; // @[util.scala:104:23]
wire out_uop_out_1_prs2_busy; // @[util.scala:104:23]
wire out_uop_out_1_prs3_busy; // @[util.scala:104:23]
wire out_uop_out_1_ppred_busy; // @[util.scala:104:23]
wire [5:0] out_uop_out_1_stale_pdst; // @[util.scala:104:23]
wire out_uop_out_1_exception; // @[util.scala:104:23]
wire [63:0] out_uop_out_1_exc_cause; // @[util.scala:104:23]
wire [4:0] out_uop_out_1_mem_cmd; // @[util.scala:104:23]
wire [1:0] out_uop_out_1_mem_size; // @[util.scala:104:23]
wire out_uop_out_1_mem_signed; // @[util.scala:104:23]
wire out_uop_out_1_uses_ldq; // @[util.scala:104:23]
wire out_uop_out_1_uses_stq; // @[util.scala:104:23]
wire out_uop_out_1_is_unique; // @[util.scala:104:23]
wire out_uop_out_1_flush_on_commit; // @[util.scala:104:23]
wire [2:0] out_uop_out_1_csr_cmd; // @[util.scala:104:23]
wire out_uop_out_1_ldst_is_rs1; // @[util.scala:104:23]
wire [5:0] out_uop_out_1_ldst; // @[util.scala:104:23]
wire [5:0] out_uop_out_1_lrs1; // @[util.scala:104:23]
wire [5:0] out_uop_out_1_lrs2; // @[util.scala:104:23]
wire [5:0] out_uop_out_1_lrs3; // @[util.scala:104:23]
wire [1:0] out_uop_out_1_dst_rtype; // @[util.scala:104:23]
wire [1:0] out_uop_out_1_lrs1_rtype; // @[util.scala:104:23]
wire [1:0] out_uop_out_1_lrs2_rtype; // @[util.scala:104:23]
wire out_uop_out_1_frs3_en; // @[util.scala:104:23]
wire out_uop_out_1_fcn_dw; // @[util.scala:104:23]
wire [4:0] out_uop_out_1_fcn_op; // @[util.scala:104:23]
wire out_uop_out_1_fp_val; // @[util.scala:104:23]
wire [2:0] out_uop_out_1_fp_rm; // @[util.scala:104:23]
wire [1:0] out_uop_out_1_fp_typ; // @[util.scala:104:23]
wire out_uop_out_1_xcpt_pf_if; // @[util.scala:104:23]
wire out_uop_out_1_xcpt_ae_if; // @[util.scala:104:23]
wire out_uop_out_1_xcpt_ma_if; // @[util.scala:104:23]
wire out_uop_out_1_bp_debug_if; // @[util.scala:104:23]
wire out_uop_out_1_bp_xcpt_if; // @[util.scala:104:23]
wire [2:0] out_uop_out_1_debug_fsrc; // @[util.scala:104:23]
wire [2:0] out_uop_out_1_debug_tsrc; // @[util.scala:104:23]
assign out_uop_out_1_br_mask = _out_uop_out_br_mask_T_3; // @[util.scala:93:25, :104:23]
always @(posedge clock) begin // @[util.scala:458:7]
if (main_io_deq_ready) begin // @[util.scala:495:23]
out_reg_uop_inst <= _main_io_deq_bits_uop_inst; // @[util.scala:476:22, :477:22]
out_reg_uop_debug_inst <= _main_io_deq_bits_uop_debug_inst; // @[util.scala:476:22, :477:22]
out_reg_uop_is_rvc <= _main_io_deq_bits_uop_is_rvc; // @[util.scala:476:22, :477:22]
out_reg_uop_debug_pc <= _main_io_deq_bits_uop_debug_pc; // @[util.scala:476:22, :477:22]
out_reg_uop_iq_type_0 <= _main_io_deq_bits_uop_iq_type_0; // @[util.scala:476:22, :477:22]
out_reg_uop_iq_type_1 <= _main_io_deq_bits_uop_iq_type_1; // @[util.scala:476:22, :477:22]
out_reg_uop_iq_type_2 <= _main_io_deq_bits_uop_iq_type_2; // @[util.scala:476:22, :477:22]
out_reg_uop_iq_type_3 <= _main_io_deq_bits_uop_iq_type_3; // @[util.scala:476:22, :477:22]
out_reg_uop_fu_code_0 <= _main_io_deq_bits_uop_fu_code_0; // @[util.scala:476:22, :477:22]
out_reg_uop_fu_code_1 <= _main_io_deq_bits_uop_fu_code_1; // @[util.scala:476:22, :477:22]
out_reg_uop_fu_code_2 <= _main_io_deq_bits_uop_fu_code_2; // @[util.scala:476:22, :477:22]
out_reg_uop_fu_code_3 <= _main_io_deq_bits_uop_fu_code_3; // @[util.scala:476:22, :477:22]
out_reg_uop_fu_code_4 <= _main_io_deq_bits_uop_fu_code_4; // @[util.scala:476:22, :477:22]
out_reg_uop_fu_code_5 <= _main_io_deq_bits_uop_fu_code_5; // @[util.scala:476:22, :477:22]
out_reg_uop_fu_code_6 <= _main_io_deq_bits_uop_fu_code_6; // @[util.scala:476:22, :477:22]
out_reg_uop_fu_code_7 <= _main_io_deq_bits_uop_fu_code_7; // @[util.scala:476:22, :477:22]
out_reg_uop_fu_code_8 <= _main_io_deq_bits_uop_fu_code_8; // @[util.scala:476:22, :477:22]
out_reg_uop_fu_code_9 <= _main_io_deq_bits_uop_fu_code_9; // @[util.scala:476:22, :477:22]
out_reg_uop_iw_issued <= _main_io_deq_bits_uop_iw_issued; // @[util.scala:476:22, :477:22]
out_reg_uop_iw_issued_partial_agen <= _main_io_deq_bits_uop_iw_issued_partial_agen; // @[util.scala:476:22, :477:22]
out_reg_uop_iw_issued_partial_dgen <= _main_io_deq_bits_uop_iw_issued_partial_dgen; // @[util.scala:476:22, :477:22]
out_reg_uop_iw_p1_speculative_child <= _main_io_deq_bits_uop_iw_p1_speculative_child; // @[util.scala:476:22, :477:22]
out_reg_uop_iw_p2_speculative_child <= _main_io_deq_bits_uop_iw_p2_speculative_child; // @[util.scala:476:22, :477:22]
out_reg_uop_iw_p1_bypass_hint <= _main_io_deq_bits_uop_iw_p1_bypass_hint; // @[util.scala:476:22, :477:22]
out_reg_uop_iw_p2_bypass_hint <= _main_io_deq_bits_uop_iw_p2_bypass_hint; // @[util.scala:476:22, :477:22]
out_reg_uop_iw_p3_bypass_hint <= _main_io_deq_bits_uop_iw_p3_bypass_hint; // @[util.scala:476:22, :477:22]
out_reg_uop_dis_col_sel <= _main_io_deq_bits_uop_dis_col_sel; // @[util.scala:476:22, :477:22]
out_reg_uop_br_mask <= _main_io_deq_bits_uop_br_mask; // @[util.scala:476:22, :477:22]
out_reg_uop_br_tag <= _main_io_deq_bits_uop_br_tag; // @[util.scala:476:22, :477:22]
out_reg_uop_br_type <= _main_io_deq_bits_uop_br_type; // @[util.scala:476:22, :477:22]
out_reg_uop_is_sfb <= _main_io_deq_bits_uop_is_sfb; // @[util.scala:476:22, :477:22]
out_reg_uop_is_fence <= _main_io_deq_bits_uop_is_fence; // @[util.scala:476:22, :477:22]
out_reg_uop_is_fencei <= _main_io_deq_bits_uop_is_fencei; // @[util.scala:476:22, :477:22]
out_reg_uop_is_sfence <= _main_io_deq_bits_uop_is_sfence; // @[util.scala:476:22, :477:22]
out_reg_uop_is_amo <= _main_io_deq_bits_uop_is_amo; // @[util.scala:476:22, :477:22]
out_reg_uop_is_eret <= _main_io_deq_bits_uop_is_eret; // @[util.scala:476:22, :477:22]
out_reg_uop_is_sys_pc2epc <= _main_io_deq_bits_uop_is_sys_pc2epc; // @[util.scala:476:22, :477:22]
out_reg_uop_is_rocc <= _main_io_deq_bits_uop_is_rocc; // @[util.scala:476:22, :477:22]
out_reg_uop_is_mov <= _main_io_deq_bits_uop_is_mov; // @[util.scala:476:22, :477:22]
out_reg_uop_ftq_idx <= _main_io_deq_bits_uop_ftq_idx; // @[util.scala:476:22, :477:22]
out_reg_uop_edge_inst <= _main_io_deq_bits_uop_edge_inst; // @[util.scala:476:22, :477:22]
out_reg_uop_pc_lob <= _main_io_deq_bits_uop_pc_lob; // @[util.scala:476:22, :477:22]
out_reg_uop_taken <= _main_io_deq_bits_uop_taken; // @[util.scala:476:22, :477:22]
out_reg_uop_imm_rename <= _main_io_deq_bits_uop_imm_rename; // @[util.scala:476:22, :477:22]
out_reg_uop_imm_sel <= _main_io_deq_bits_uop_imm_sel; // @[util.scala:476:22, :477:22]
out_reg_uop_pimm <= _main_io_deq_bits_uop_pimm; // @[util.scala:476:22, :477:22]
out_reg_uop_imm_packed <= _main_io_deq_bits_uop_imm_packed; // @[util.scala:476:22, :477:22]
out_reg_uop_op1_sel <= _main_io_deq_bits_uop_op1_sel; // @[util.scala:476:22, :477:22]
out_reg_uop_op2_sel <= _main_io_deq_bits_uop_op2_sel; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_ldst <= _main_io_deq_bits_uop_fp_ctrl_ldst; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_wen <= _main_io_deq_bits_uop_fp_ctrl_wen; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_ren1 <= _main_io_deq_bits_uop_fp_ctrl_ren1; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_ren2 <= _main_io_deq_bits_uop_fp_ctrl_ren2; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_ren3 <= _main_io_deq_bits_uop_fp_ctrl_ren3; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_swap12 <= _main_io_deq_bits_uop_fp_ctrl_swap12; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_swap23 <= _main_io_deq_bits_uop_fp_ctrl_swap23; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_typeTagIn <= _main_io_deq_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_typeTagOut <= _main_io_deq_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_fromint <= _main_io_deq_bits_uop_fp_ctrl_fromint; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_toint <= _main_io_deq_bits_uop_fp_ctrl_toint; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_fastpipe <= _main_io_deq_bits_uop_fp_ctrl_fastpipe; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_fma <= _main_io_deq_bits_uop_fp_ctrl_fma; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_div <= _main_io_deq_bits_uop_fp_ctrl_div; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_sqrt <= _main_io_deq_bits_uop_fp_ctrl_sqrt; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_wflags <= _main_io_deq_bits_uop_fp_ctrl_wflags; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_vec <= _main_io_deq_bits_uop_fp_ctrl_vec; // @[util.scala:476:22, :477:22]
out_reg_uop_rob_idx <= _main_io_deq_bits_uop_rob_idx; // @[util.scala:476:22, :477:22]
out_reg_uop_ldq_idx <= _main_io_deq_bits_uop_ldq_idx; // @[util.scala:476:22, :477:22]
out_reg_uop_stq_idx <= _main_io_deq_bits_uop_stq_idx; // @[util.scala:476:22, :477:22]
out_reg_uop_rxq_idx <= _main_io_deq_bits_uop_rxq_idx; // @[util.scala:476:22, :477:22]
out_reg_uop_pdst <= _main_io_deq_bits_uop_pdst; // @[util.scala:476:22, :477:22]
out_reg_uop_prs1 <= _main_io_deq_bits_uop_prs1; // @[util.scala:476:22, :477:22]
out_reg_uop_prs2 <= _main_io_deq_bits_uop_prs2; // @[util.scala:476:22, :477:22]
out_reg_uop_prs3 <= _main_io_deq_bits_uop_prs3; // @[util.scala:476:22, :477:22]
out_reg_uop_ppred <= _main_io_deq_bits_uop_ppred; // @[util.scala:476:22, :477:22]
out_reg_uop_prs1_busy <= _main_io_deq_bits_uop_prs1_busy; // @[util.scala:476:22, :477:22]
out_reg_uop_prs2_busy <= _main_io_deq_bits_uop_prs2_busy; // @[util.scala:476:22, :477:22]
out_reg_uop_prs3_busy <= _main_io_deq_bits_uop_prs3_busy; // @[util.scala:476:22, :477:22]
out_reg_uop_ppred_busy <= _main_io_deq_bits_uop_ppred_busy; // @[util.scala:476:22, :477:22]
out_reg_uop_stale_pdst <= _main_io_deq_bits_uop_stale_pdst; // @[util.scala:476:22, :477:22]
out_reg_uop_exception <= _main_io_deq_bits_uop_exception; // @[util.scala:476:22, :477:22]
out_reg_uop_exc_cause <= _main_io_deq_bits_uop_exc_cause; // @[util.scala:476:22, :477:22]
out_reg_uop_mem_cmd <= _main_io_deq_bits_uop_mem_cmd; // @[util.scala:476:22, :477:22]
out_reg_uop_mem_size <= _main_io_deq_bits_uop_mem_size; // @[util.scala:476:22, :477:22]
out_reg_uop_mem_signed <= _main_io_deq_bits_uop_mem_signed; // @[util.scala:476:22, :477:22]
out_reg_uop_uses_ldq <= _main_io_deq_bits_uop_uses_ldq; // @[util.scala:476:22, :477:22]
out_reg_uop_uses_stq <= _main_io_deq_bits_uop_uses_stq; // @[util.scala:476:22, :477:22]
out_reg_uop_is_unique <= _main_io_deq_bits_uop_is_unique; // @[util.scala:476:22, :477:22]
out_reg_uop_flush_on_commit <= _main_io_deq_bits_uop_flush_on_commit; // @[util.scala:476:22, :477:22]
out_reg_uop_csr_cmd <= _main_io_deq_bits_uop_csr_cmd; // @[util.scala:476:22, :477:22]
out_reg_uop_ldst_is_rs1 <= _main_io_deq_bits_uop_ldst_is_rs1; // @[util.scala:476:22, :477:22]
out_reg_uop_ldst <= _main_io_deq_bits_uop_ldst; // @[util.scala:476:22, :477:22]
out_reg_uop_lrs1 <= _main_io_deq_bits_uop_lrs1; // @[util.scala:476:22, :477:22]
out_reg_uop_lrs2 <= _main_io_deq_bits_uop_lrs2; // @[util.scala:476:22, :477:22]
out_reg_uop_lrs3 <= _main_io_deq_bits_uop_lrs3; // @[util.scala:476:22, :477:22]
out_reg_uop_dst_rtype <= _main_io_deq_bits_uop_dst_rtype; // @[util.scala:476:22, :477:22]
out_reg_uop_lrs1_rtype <= _main_io_deq_bits_uop_lrs1_rtype; // @[util.scala:476:22, :477:22]
out_reg_uop_lrs2_rtype <= _main_io_deq_bits_uop_lrs2_rtype; // @[util.scala:476:22, :477:22]
out_reg_uop_frs3_en <= _main_io_deq_bits_uop_frs3_en; // @[util.scala:476:22, :477:22]
out_reg_uop_fcn_dw <= _main_io_deq_bits_uop_fcn_dw; // @[util.scala:476:22, :477:22]
out_reg_uop_fcn_op <= _main_io_deq_bits_uop_fcn_op; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_val <= _main_io_deq_bits_uop_fp_val; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_rm <= _main_io_deq_bits_uop_fp_rm; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_typ <= _main_io_deq_bits_uop_fp_typ; // @[util.scala:476:22, :477:22]
out_reg_uop_xcpt_pf_if <= _main_io_deq_bits_uop_xcpt_pf_if; // @[util.scala:476:22, :477:22]
out_reg_uop_xcpt_ae_if <= _main_io_deq_bits_uop_xcpt_ae_if; // @[util.scala:476:22, :477:22]
out_reg_uop_xcpt_ma_if <= _main_io_deq_bits_uop_xcpt_ma_if; // @[util.scala:476:22, :477:22]
out_reg_uop_bp_debug_if <= _main_io_deq_bits_uop_bp_debug_if; // @[util.scala:476:22, :477:22]
out_reg_uop_bp_xcpt_if <= _main_io_deq_bits_uop_bp_xcpt_if; // @[util.scala:476:22, :477:22]
out_reg_uop_debug_fsrc <= _main_io_deq_bits_uop_debug_fsrc; // @[util.scala:476:22, :477:22]
out_reg_uop_debug_tsrc <= _main_io_deq_bits_uop_debug_tsrc; // @[util.scala:476:22, :477:22]
out_reg_addr <= _main_io_deq_bits_addr; // @[util.scala:476:22, :477:22]
out_reg_data <= _main_io_deq_bits_data; // @[util.scala:476:22, :477:22]
out_reg_is_hella <= _main_io_deq_bits_is_hella; // @[util.scala:476:22, :477:22]
out_reg_tag_match <= _main_io_deq_bits_tag_match; // @[util.scala:476:22, :477:22]
out_reg_old_meta_coh_state <= _main_io_deq_bits_old_meta_coh_state; // @[util.scala:476:22, :477:22]
out_reg_old_meta_tag <= _main_io_deq_bits_old_meta_tag; // @[util.scala:476:22, :477:22]
out_reg_way_en <= _main_io_deq_bits_way_en; // @[util.scala:476:22, :477:22]
out_reg_sdq_id <= _main_io_deq_bits_sdq_id; // @[util.scala:476:22, :477:22]
end
out_uop_inst <= main_io_deq_ready ? out_uop_out_1_inst : out_uop_out_inst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_debug_inst <= main_io_deq_ready ? out_uop_out_1_debug_inst : out_uop_out_debug_inst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_is_rvc <= main_io_deq_ready ? out_uop_out_1_is_rvc : out_uop_out_is_rvc; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_debug_pc <= main_io_deq_ready ? out_uop_out_1_debug_pc : out_uop_out_debug_pc; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_iq_type_0 <= main_io_deq_ready ? out_uop_out_1_iq_type_0 : out_uop_out_iq_type_0; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_iq_type_1 <= main_io_deq_ready ? out_uop_out_1_iq_type_1 : out_uop_out_iq_type_1; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_iq_type_2 <= main_io_deq_ready ? out_uop_out_1_iq_type_2 : out_uop_out_iq_type_2; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_iq_type_3 <= main_io_deq_ready ? out_uop_out_1_iq_type_3 : out_uop_out_iq_type_3; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fu_code_0 <= main_io_deq_ready ? out_uop_out_1_fu_code_0 : out_uop_out_fu_code_0; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fu_code_1 <= main_io_deq_ready ? out_uop_out_1_fu_code_1 : out_uop_out_fu_code_1; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fu_code_2 <= main_io_deq_ready ? out_uop_out_1_fu_code_2 : out_uop_out_fu_code_2; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fu_code_3 <= main_io_deq_ready ? out_uop_out_1_fu_code_3 : out_uop_out_fu_code_3; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fu_code_4 <= main_io_deq_ready ? out_uop_out_1_fu_code_4 : out_uop_out_fu_code_4; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fu_code_5 <= main_io_deq_ready ? out_uop_out_1_fu_code_5 : out_uop_out_fu_code_5; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fu_code_6 <= main_io_deq_ready ? out_uop_out_1_fu_code_6 : out_uop_out_fu_code_6; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fu_code_7 <= main_io_deq_ready ? out_uop_out_1_fu_code_7 : out_uop_out_fu_code_7; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fu_code_8 <= main_io_deq_ready ? out_uop_out_1_fu_code_8 : out_uop_out_fu_code_8; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fu_code_9 <= main_io_deq_ready ? out_uop_out_1_fu_code_9 : out_uop_out_fu_code_9; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_iw_issued <= main_io_deq_ready ? out_uop_out_1_iw_issued : out_uop_out_iw_issued; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_iw_issued_partial_agen <= main_io_deq_ready ? out_uop_out_1_iw_issued_partial_agen : out_uop_out_iw_issued_partial_agen; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_iw_issued_partial_dgen <= main_io_deq_ready ? out_uop_out_1_iw_issued_partial_dgen : out_uop_out_iw_issued_partial_dgen; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_iw_p1_speculative_child <= main_io_deq_ready ? out_uop_out_1_iw_p1_speculative_child : out_uop_out_iw_p1_speculative_child; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_iw_p2_speculative_child <= main_io_deq_ready ? out_uop_out_1_iw_p2_speculative_child : out_uop_out_iw_p2_speculative_child; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_iw_p1_bypass_hint <= main_io_deq_ready ? out_uop_out_1_iw_p1_bypass_hint : out_uop_out_iw_p1_bypass_hint; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_iw_p2_bypass_hint <= main_io_deq_ready ? out_uop_out_1_iw_p2_bypass_hint : out_uop_out_iw_p2_bypass_hint; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_iw_p3_bypass_hint <= main_io_deq_ready ? out_uop_out_1_iw_p3_bypass_hint : out_uop_out_iw_p3_bypass_hint; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_dis_col_sel <= main_io_deq_ready ? out_uop_out_1_dis_col_sel : out_uop_out_dis_col_sel; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_br_mask <= main_io_deq_ready ? out_uop_out_1_br_mask : out_uop_out_br_mask; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_br_tag <= main_io_deq_ready ? out_uop_out_1_br_tag : out_uop_out_br_tag; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_br_type <= main_io_deq_ready ? out_uop_out_1_br_type : out_uop_out_br_type; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_is_sfb <= main_io_deq_ready ? out_uop_out_1_is_sfb : out_uop_out_is_sfb; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_is_fence <= main_io_deq_ready ? out_uop_out_1_is_fence : out_uop_out_is_fence; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_is_fencei <= main_io_deq_ready ? out_uop_out_1_is_fencei : out_uop_out_is_fencei; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_is_sfence <= main_io_deq_ready ? out_uop_out_1_is_sfence : out_uop_out_is_sfence; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_is_amo <= main_io_deq_ready ? out_uop_out_1_is_amo : out_uop_out_is_amo; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_is_eret <= main_io_deq_ready ? out_uop_out_1_is_eret : out_uop_out_is_eret; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_is_sys_pc2epc <= main_io_deq_ready ? out_uop_out_1_is_sys_pc2epc : out_uop_out_is_sys_pc2epc; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_is_rocc <= main_io_deq_ready ? out_uop_out_1_is_rocc : out_uop_out_is_rocc; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_is_mov <= main_io_deq_ready ? out_uop_out_1_is_mov : out_uop_out_is_mov; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_ftq_idx <= main_io_deq_ready ? out_uop_out_1_ftq_idx : out_uop_out_ftq_idx; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_edge_inst <= main_io_deq_ready ? out_uop_out_1_edge_inst : out_uop_out_edge_inst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_pc_lob <= main_io_deq_ready ? out_uop_out_1_pc_lob : out_uop_out_pc_lob; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_taken <= main_io_deq_ready ? out_uop_out_1_taken : out_uop_out_taken; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_imm_rename <= main_io_deq_ready ? out_uop_out_1_imm_rename : out_uop_out_imm_rename; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_imm_sel <= main_io_deq_ready ? out_uop_out_1_imm_sel : out_uop_out_imm_sel; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_pimm <= main_io_deq_ready ? out_uop_out_1_pimm : out_uop_out_pimm; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_imm_packed <= main_io_deq_ready ? out_uop_out_1_imm_packed : out_uop_out_imm_packed; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_op1_sel <= main_io_deq_ready ? out_uop_out_1_op1_sel : out_uop_out_op1_sel; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_op2_sel <= main_io_deq_ready ? out_uop_out_1_op2_sel : out_uop_out_op2_sel; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_ldst <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_ldst : out_uop_out_fp_ctrl_ldst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_wen <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_wen : out_uop_out_fp_ctrl_wen; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_ren1 <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_ren1 : out_uop_out_fp_ctrl_ren1; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_ren2 <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_ren2 : out_uop_out_fp_ctrl_ren2; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_ren3 <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_ren3 : out_uop_out_fp_ctrl_ren3; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_swap12 <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_swap12 : out_uop_out_fp_ctrl_swap12; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_swap23 <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_swap23 : out_uop_out_fp_ctrl_swap23; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_typeTagIn <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_typeTagIn : out_uop_out_fp_ctrl_typeTagIn; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_typeTagOut <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_typeTagOut : out_uop_out_fp_ctrl_typeTagOut; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_fromint <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_fromint : out_uop_out_fp_ctrl_fromint; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_toint <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_toint : out_uop_out_fp_ctrl_toint; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_fastpipe <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_fastpipe : out_uop_out_fp_ctrl_fastpipe; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_fma <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_fma : out_uop_out_fp_ctrl_fma; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_div <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_div : out_uop_out_fp_ctrl_div; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_sqrt <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_sqrt : out_uop_out_fp_ctrl_sqrt; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_wflags <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_wflags : out_uop_out_fp_ctrl_wflags; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_vec <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_vec : out_uop_out_fp_ctrl_vec; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_rob_idx <= main_io_deq_ready ? out_uop_out_1_rob_idx : out_uop_out_rob_idx; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_ldq_idx <= main_io_deq_ready ? out_uop_out_1_ldq_idx : out_uop_out_ldq_idx; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_stq_idx <= main_io_deq_ready ? out_uop_out_1_stq_idx : out_uop_out_stq_idx; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_rxq_idx <= main_io_deq_ready ? out_uop_out_1_rxq_idx : out_uop_out_rxq_idx; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_pdst <= main_io_deq_ready ? out_uop_out_1_pdst : out_uop_out_pdst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_prs1 <= main_io_deq_ready ? out_uop_out_1_prs1 : out_uop_out_prs1; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_prs2 <= main_io_deq_ready ? out_uop_out_1_prs2 : out_uop_out_prs2; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_prs3 <= main_io_deq_ready ? out_uop_out_1_prs3 : out_uop_out_prs3; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_ppred <= main_io_deq_ready ? out_uop_out_1_ppred : out_uop_out_ppred; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_prs1_busy <= main_io_deq_ready ? out_uop_out_1_prs1_busy : out_uop_out_prs1_busy; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_prs2_busy <= main_io_deq_ready ? out_uop_out_1_prs2_busy : out_uop_out_prs2_busy; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_prs3_busy <= main_io_deq_ready ? out_uop_out_1_prs3_busy : out_uop_out_prs3_busy; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_ppred_busy <= main_io_deq_ready ? out_uop_out_1_ppred_busy : out_uop_out_ppred_busy; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_stale_pdst <= main_io_deq_ready ? out_uop_out_1_stale_pdst : out_uop_out_stale_pdst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_exception <= main_io_deq_ready ? out_uop_out_1_exception : out_uop_out_exception; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_exc_cause <= main_io_deq_ready ? out_uop_out_1_exc_cause : out_uop_out_exc_cause; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_mem_cmd <= main_io_deq_ready ? out_uop_out_1_mem_cmd : out_uop_out_mem_cmd; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_mem_size <= main_io_deq_ready ? out_uop_out_1_mem_size : out_uop_out_mem_size; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_mem_signed <= main_io_deq_ready ? out_uop_out_1_mem_signed : out_uop_out_mem_signed; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_uses_ldq <= main_io_deq_ready ? out_uop_out_1_uses_ldq : out_uop_out_uses_ldq; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_uses_stq <= main_io_deq_ready ? out_uop_out_1_uses_stq : out_uop_out_uses_stq; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_is_unique <= main_io_deq_ready ? out_uop_out_1_is_unique : out_uop_out_is_unique; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_flush_on_commit <= main_io_deq_ready ? out_uop_out_1_flush_on_commit : out_uop_out_flush_on_commit; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_csr_cmd <= main_io_deq_ready ? out_uop_out_1_csr_cmd : out_uop_out_csr_cmd; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_ldst_is_rs1 <= main_io_deq_ready ? out_uop_out_1_ldst_is_rs1 : out_uop_out_ldst_is_rs1; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_ldst <= main_io_deq_ready ? out_uop_out_1_ldst : out_uop_out_ldst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_lrs1 <= main_io_deq_ready ? out_uop_out_1_lrs1 : out_uop_out_lrs1; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_lrs2 <= main_io_deq_ready ? out_uop_out_1_lrs2 : out_uop_out_lrs2; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_lrs3 <= main_io_deq_ready ? out_uop_out_1_lrs3 : out_uop_out_lrs3; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_dst_rtype <= main_io_deq_ready ? out_uop_out_1_dst_rtype : out_uop_out_dst_rtype; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_lrs1_rtype <= main_io_deq_ready ? out_uop_out_1_lrs1_rtype : out_uop_out_lrs1_rtype; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_lrs2_rtype <= main_io_deq_ready ? out_uop_out_1_lrs2_rtype : out_uop_out_lrs2_rtype; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_frs3_en <= main_io_deq_ready ? out_uop_out_1_frs3_en : out_uop_out_frs3_en; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fcn_dw <= main_io_deq_ready ? out_uop_out_1_fcn_dw : out_uop_out_fcn_dw; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fcn_op <= main_io_deq_ready ? out_uop_out_1_fcn_op : out_uop_out_fcn_op; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_val <= main_io_deq_ready ? out_uop_out_1_fp_val : out_uop_out_fp_val; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_rm <= main_io_deq_ready ? out_uop_out_1_fp_rm : out_uop_out_fp_rm; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_typ <= main_io_deq_ready ? out_uop_out_1_fp_typ : out_uop_out_fp_typ; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_xcpt_pf_if <= main_io_deq_ready ? out_uop_out_1_xcpt_pf_if : out_uop_out_xcpt_pf_if; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_xcpt_ae_if <= main_io_deq_ready ? out_uop_out_1_xcpt_ae_if : out_uop_out_xcpt_ae_if; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_xcpt_ma_if <= main_io_deq_ready ? out_uop_out_1_xcpt_ma_if : out_uop_out_xcpt_ma_if; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_bp_debug_if <= main_io_deq_ready ? out_uop_out_1_bp_debug_if : out_uop_out_bp_debug_if; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_bp_xcpt_if <= main_io_deq_ready ? out_uop_out_1_bp_xcpt_if : out_uop_out_bp_xcpt_if; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_debug_fsrc <= main_io_deq_ready ? out_uop_out_1_debug_fsrc : out_uop_out_debug_fsrc; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_debug_tsrc <= main_io_deq_ready ? out_uop_out_1_debug_tsrc : out_uop_out_debug_tsrc; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
if (reset) // @[util.scala:458:7]
out_valid <= 1'h0; // @[util.scala:478:28]
else // @[util.scala:458:7]
out_valid <= main_io_deq_ready ? _out_valid_T_15 : _out_valid_T_7; // @[util.scala:478:28, :492:{15,80}, :495:{23,38}, :496:{17,103}]
always @(posedge)
BranchKillableQueue_10 main ( // @[util.scala:476:22]
.clock (clock),
.reset (reset),
.io_enq_ready (io_enq_ready_0),
.io_enq_valid (io_enq_valid_0), // @[util.scala:458:7]
.io_enq_bits_uop_inst (io_enq_bits_uop_inst_0), // @[util.scala:458:7]
.io_enq_bits_uop_debug_inst (io_enq_bits_uop_debug_inst_0), // @[util.scala:458:7]
.io_enq_bits_uop_is_rvc (io_enq_bits_uop_is_rvc_0), // @[util.scala:458:7]
.io_enq_bits_uop_debug_pc (io_enq_bits_uop_debug_pc_0), // @[util.scala:458:7]
.io_enq_bits_uop_iq_type_0 (io_enq_bits_uop_iq_type_0_0), // @[util.scala:458:7]
.io_enq_bits_uop_iq_type_1 (io_enq_bits_uop_iq_type_1_0), // @[util.scala:458:7]
.io_enq_bits_uop_iq_type_2 (io_enq_bits_uop_iq_type_2_0), // @[util.scala:458:7]
.io_enq_bits_uop_iq_type_3 (io_enq_bits_uop_iq_type_3_0), // @[util.scala:458:7]
.io_enq_bits_uop_fu_code_0 (io_enq_bits_uop_fu_code_0_0), // @[util.scala:458:7]
.io_enq_bits_uop_fu_code_1 (io_enq_bits_uop_fu_code_1_0), // @[util.scala:458:7]
.io_enq_bits_uop_fu_code_2 (io_enq_bits_uop_fu_code_2_0), // @[util.scala:458:7]
.io_enq_bits_uop_fu_code_3 (io_enq_bits_uop_fu_code_3_0), // @[util.scala:458:7]
.io_enq_bits_uop_fu_code_4 (io_enq_bits_uop_fu_code_4_0), // @[util.scala:458:7]
.io_enq_bits_uop_fu_code_5 (io_enq_bits_uop_fu_code_5_0), // @[util.scala:458:7]
.io_enq_bits_uop_fu_code_6 (io_enq_bits_uop_fu_code_6_0), // @[util.scala:458:7]
.io_enq_bits_uop_fu_code_7 (io_enq_bits_uop_fu_code_7_0), // @[util.scala:458:7]
.io_enq_bits_uop_fu_code_8 (io_enq_bits_uop_fu_code_8_0), // @[util.scala:458:7]
.io_enq_bits_uop_fu_code_9 (io_enq_bits_uop_fu_code_9_0), // @[util.scala:458:7]
.io_enq_bits_uop_iw_issued (io_enq_bits_uop_iw_issued_0), // @[util.scala:458:7]
.io_enq_bits_uop_iw_issued_partial_agen (io_enq_bits_uop_iw_issued_partial_agen_0), // @[util.scala:458:7]
.io_enq_bits_uop_iw_issued_partial_dgen (io_enq_bits_uop_iw_issued_partial_dgen_0), // @[util.scala:458:7]
.io_enq_bits_uop_iw_p1_speculative_child (io_enq_bits_uop_iw_p1_speculative_child_0), // @[util.scala:458:7]
.io_enq_bits_uop_iw_p2_speculative_child (io_enq_bits_uop_iw_p2_speculative_child_0), // @[util.scala:458:7]
.io_enq_bits_uop_iw_p1_bypass_hint (io_enq_bits_uop_iw_p1_bypass_hint_0), // @[util.scala:458:7]
.io_enq_bits_uop_iw_p2_bypass_hint (io_enq_bits_uop_iw_p2_bypass_hint_0), // @[util.scala:458:7]
.io_enq_bits_uop_iw_p3_bypass_hint (io_enq_bits_uop_iw_p3_bypass_hint_0), // @[util.scala:458:7]
.io_enq_bits_uop_dis_col_sel (io_enq_bits_uop_dis_col_sel_0), // @[util.scala:458:7]
.io_enq_bits_uop_br_mask (io_enq_bits_uop_br_mask_0), // @[util.scala:458:7]
.io_enq_bits_uop_br_tag (io_enq_bits_uop_br_tag_0), // @[util.scala:458:7]
.io_enq_bits_uop_br_type (io_enq_bits_uop_br_type_0), // @[util.scala:458:7]
.io_enq_bits_uop_is_sfb (io_enq_bits_uop_is_sfb_0), // @[util.scala:458:7]
.io_enq_bits_uop_is_fence (io_enq_bits_uop_is_fence_0), // @[util.scala:458:7]
.io_enq_bits_uop_is_fencei (io_enq_bits_uop_is_fencei_0), // @[util.scala:458:7]
.io_enq_bits_uop_is_sfence (io_enq_bits_uop_is_sfence_0), // @[util.scala:458:7]
.io_enq_bits_uop_is_amo (io_enq_bits_uop_is_amo_0), // @[util.scala:458:7]
.io_enq_bits_uop_is_eret (io_enq_bits_uop_is_eret_0), // @[util.scala:458:7]
.io_enq_bits_uop_is_sys_pc2epc (io_enq_bits_uop_is_sys_pc2epc_0), // @[util.scala:458:7]
.io_enq_bits_uop_is_rocc (io_enq_bits_uop_is_rocc_0), // @[util.scala:458:7]
.io_enq_bits_uop_is_mov (io_enq_bits_uop_is_mov_0), // @[util.scala:458:7]
.io_enq_bits_uop_ftq_idx (io_enq_bits_uop_ftq_idx_0), // @[util.scala:458:7]
.io_enq_bits_uop_edge_inst (io_enq_bits_uop_edge_inst_0), // @[util.scala:458:7]
.io_enq_bits_uop_pc_lob (io_enq_bits_uop_pc_lob_0), // @[util.scala:458:7]
.io_enq_bits_uop_taken (io_enq_bits_uop_taken_0), // @[util.scala:458:7]
.io_enq_bits_uop_imm_rename (io_enq_bits_uop_imm_rename_0), // @[util.scala:458:7]
.io_enq_bits_uop_imm_sel (io_enq_bits_uop_imm_sel_0), // @[util.scala:458:7]
.io_enq_bits_uop_pimm (io_enq_bits_uop_pimm_0), // @[util.scala:458:7]
.io_enq_bits_uop_imm_packed (io_enq_bits_uop_imm_packed_0), // @[util.scala:458:7]
.io_enq_bits_uop_op1_sel (io_enq_bits_uop_op1_sel_0), // @[util.scala:458:7]
.io_enq_bits_uop_op2_sel (io_enq_bits_uop_op2_sel_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_ldst (io_enq_bits_uop_fp_ctrl_ldst_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_wen (io_enq_bits_uop_fp_ctrl_wen_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_ren1 (io_enq_bits_uop_fp_ctrl_ren1_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_ren2 (io_enq_bits_uop_fp_ctrl_ren2_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_ren3 (io_enq_bits_uop_fp_ctrl_ren3_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_swap12 (io_enq_bits_uop_fp_ctrl_swap12_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_swap23 (io_enq_bits_uop_fp_ctrl_swap23_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_typeTagIn (io_enq_bits_uop_fp_ctrl_typeTagIn_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_typeTagOut (io_enq_bits_uop_fp_ctrl_typeTagOut_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_fromint (io_enq_bits_uop_fp_ctrl_fromint_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_toint (io_enq_bits_uop_fp_ctrl_toint_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_fastpipe (io_enq_bits_uop_fp_ctrl_fastpipe_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_fma (io_enq_bits_uop_fp_ctrl_fma_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_div (io_enq_bits_uop_fp_ctrl_div_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_sqrt (io_enq_bits_uop_fp_ctrl_sqrt_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_wflags (io_enq_bits_uop_fp_ctrl_wflags_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_vec (io_enq_bits_uop_fp_ctrl_vec_0), // @[util.scala:458:7]
.io_enq_bits_uop_rob_idx (io_enq_bits_uop_rob_idx_0), // @[util.scala:458:7]
.io_enq_bits_uop_ldq_idx (io_enq_bits_uop_ldq_idx_0), // @[util.scala:458:7]
.io_enq_bits_uop_stq_idx (io_enq_bits_uop_stq_idx_0), // @[util.scala:458:7]
.io_enq_bits_uop_rxq_idx (io_enq_bits_uop_rxq_idx_0), // @[util.scala:458:7]
.io_enq_bits_uop_pdst (io_enq_bits_uop_pdst_0), // @[util.scala:458:7]
.io_enq_bits_uop_prs1 (io_enq_bits_uop_prs1_0), // @[util.scala:458:7]
.io_enq_bits_uop_prs2 (io_enq_bits_uop_prs2_0), // @[util.scala:458:7]
.io_enq_bits_uop_prs3 (io_enq_bits_uop_prs3_0), // @[util.scala:458:7]
.io_enq_bits_uop_ppred (io_enq_bits_uop_ppred_0), // @[util.scala:458:7]
.io_enq_bits_uop_prs1_busy (io_enq_bits_uop_prs1_busy_0), // @[util.scala:458:7]
.io_enq_bits_uop_prs2_busy (io_enq_bits_uop_prs2_busy_0), // @[util.scala:458:7]
.io_enq_bits_uop_prs3_busy (io_enq_bits_uop_prs3_busy_0), // @[util.scala:458:7]
.io_enq_bits_uop_ppred_busy (io_enq_bits_uop_ppred_busy_0), // @[util.scala:458:7]
.io_enq_bits_uop_stale_pdst (io_enq_bits_uop_stale_pdst_0), // @[util.scala:458:7]
.io_enq_bits_uop_exception (io_enq_bits_uop_exception_0), // @[util.scala:458:7]
.io_enq_bits_uop_exc_cause (io_enq_bits_uop_exc_cause_0), // @[util.scala:458:7]
.io_enq_bits_uop_mem_cmd (io_enq_bits_uop_mem_cmd_0), // @[util.scala:458:7]
.io_enq_bits_uop_mem_size (io_enq_bits_uop_mem_size_0), // @[util.scala:458:7]
.io_enq_bits_uop_mem_signed (io_enq_bits_uop_mem_signed_0), // @[util.scala:458:7]
.io_enq_bits_uop_uses_ldq (io_enq_bits_uop_uses_ldq_0), // @[util.scala:458:7]
.io_enq_bits_uop_uses_stq (io_enq_bits_uop_uses_stq_0), // @[util.scala:458:7]
.io_enq_bits_uop_is_unique (io_enq_bits_uop_is_unique_0), // @[util.scala:458:7]
.io_enq_bits_uop_flush_on_commit (io_enq_bits_uop_flush_on_commit_0), // @[util.scala:458:7]
.io_enq_bits_uop_csr_cmd (io_enq_bits_uop_csr_cmd_0), // @[util.scala:458:7]
.io_enq_bits_uop_ldst_is_rs1 (io_enq_bits_uop_ldst_is_rs1_0), // @[util.scala:458:7]
.io_enq_bits_uop_ldst (io_enq_bits_uop_ldst_0), // @[util.scala:458:7]
.io_enq_bits_uop_lrs1 (io_enq_bits_uop_lrs1_0), // @[util.scala:458:7]
.io_enq_bits_uop_lrs2 (io_enq_bits_uop_lrs2_0), // @[util.scala:458:7]
.io_enq_bits_uop_lrs3 (io_enq_bits_uop_lrs3_0), // @[util.scala:458:7]
.io_enq_bits_uop_dst_rtype (io_enq_bits_uop_dst_rtype_0), // @[util.scala:458:7]
.io_enq_bits_uop_lrs1_rtype (io_enq_bits_uop_lrs1_rtype_0), // @[util.scala:458:7]
.io_enq_bits_uop_lrs2_rtype (io_enq_bits_uop_lrs2_rtype_0), // @[util.scala:458:7]
.io_enq_bits_uop_frs3_en (io_enq_bits_uop_frs3_en_0), // @[util.scala:458:7]
.io_enq_bits_uop_fcn_dw (io_enq_bits_uop_fcn_dw_0), // @[util.scala:458:7]
.io_enq_bits_uop_fcn_op (io_enq_bits_uop_fcn_op_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_val (io_enq_bits_uop_fp_val_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_rm (io_enq_bits_uop_fp_rm_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_typ (io_enq_bits_uop_fp_typ_0), // @[util.scala:458:7]
.io_enq_bits_uop_xcpt_pf_if (io_enq_bits_uop_xcpt_pf_if_0), // @[util.scala:458:7]
.io_enq_bits_uop_xcpt_ae_if (io_enq_bits_uop_xcpt_ae_if_0), // @[util.scala:458:7]
.io_enq_bits_uop_xcpt_ma_if (io_enq_bits_uop_xcpt_ma_if_0), // @[util.scala:458:7]
.io_enq_bits_uop_bp_debug_if (io_enq_bits_uop_bp_debug_if_0), // @[util.scala:458:7]
.io_enq_bits_uop_bp_xcpt_if (io_enq_bits_uop_bp_xcpt_if_0), // @[util.scala:458:7]
.io_enq_bits_uop_debug_fsrc (io_enq_bits_uop_debug_fsrc_0), // @[util.scala:458:7]
.io_enq_bits_uop_debug_tsrc (io_enq_bits_uop_debug_tsrc_0), // @[util.scala:458:7]
.io_enq_bits_addr (io_enq_bits_addr_0), // @[util.scala:458:7]
.io_enq_bits_data (io_enq_bits_data_0), // @[util.scala:458:7]
.io_enq_bits_is_hella (io_enq_bits_is_hella_0), // @[util.scala:458:7]
.io_enq_bits_tag_match (io_enq_bits_tag_match_0), // @[util.scala:458:7]
.io_enq_bits_old_meta_coh_state (io_enq_bits_old_meta_coh_state_0), // @[util.scala:458:7]
.io_enq_bits_old_meta_tag (io_enq_bits_old_meta_tag_0), // @[util.scala:458:7]
.io_enq_bits_way_en (io_enq_bits_way_en_0), // @[util.scala:458:7]
.io_enq_bits_sdq_id (io_enq_bits_sdq_id_0), // @[util.scala:458:7]
.io_deq_ready (main_io_deq_ready), // @[util.scala:495:23]
.io_deq_valid (_out_valid_T_12),
.io_deq_bits_uop_inst (_main_io_deq_bits_uop_inst),
.io_deq_bits_uop_debug_inst (_main_io_deq_bits_uop_debug_inst),
.io_deq_bits_uop_is_rvc (_main_io_deq_bits_uop_is_rvc),
.io_deq_bits_uop_debug_pc (_main_io_deq_bits_uop_debug_pc),
.io_deq_bits_uop_iq_type_0 (_main_io_deq_bits_uop_iq_type_0),
.io_deq_bits_uop_iq_type_1 (_main_io_deq_bits_uop_iq_type_1),
.io_deq_bits_uop_iq_type_2 (_main_io_deq_bits_uop_iq_type_2),
.io_deq_bits_uop_iq_type_3 (_main_io_deq_bits_uop_iq_type_3),
.io_deq_bits_uop_fu_code_0 (_main_io_deq_bits_uop_fu_code_0),
.io_deq_bits_uop_fu_code_1 (_main_io_deq_bits_uop_fu_code_1),
.io_deq_bits_uop_fu_code_2 (_main_io_deq_bits_uop_fu_code_2),
.io_deq_bits_uop_fu_code_3 (_main_io_deq_bits_uop_fu_code_3),
.io_deq_bits_uop_fu_code_4 (_main_io_deq_bits_uop_fu_code_4),
.io_deq_bits_uop_fu_code_5 (_main_io_deq_bits_uop_fu_code_5),
.io_deq_bits_uop_fu_code_6 (_main_io_deq_bits_uop_fu_code_6),
.io_deq_bits_uop_fu_code_7 (_main_io_deq_bits_uop_fu_code_7),
.io_deq_bits_uop_fu_code_8 (_main_io_deq_bits_uop_fu_code_8),
.io_deq_bits_uop_fu_code_9 (_main_io_deq_bits_uop_fu_code_9),
.io_deq_bits_uop_iw_issued (_main_io_deq_bits_uop_iw_issued),
.io_deq_bits_uop_iw_issued_partial_agen (_main_io_deq_bits_uop_iw_issued_partial_agen),
.io_deq_bits_uop_iw_issued_partial_dgen (_main_io_deq_bits_uop_iw_issued_partial_dgen),
.io_deq_bits_uop_iw_p1_speculative_child (_main_io_deq_bits_uop_iw_p1_speculative_child),
.io_deq_bits_uop_iw_p2_speculative_child (_main_io_deq_bits_uop_iw_p2_speculative_child),
.io_deq_bits_uop_iw_p1_bypass_hint (_main_io_deq_bits_uop_iw_p1_bypass_hint),
.io_deq_bits_uop_iw_p2_bypass_hint (_main_io_deq_bits_uop_iw_p2_bypass_hint),
.io_deq_bits_uop_iw_p3_bypass_hint (_main_io_deq_bits_uop_iw_p3_bypass_hint),
.io_deq_bits_uop_dis_col_sel (_main_io_deq_bits_uop_dis_col_sel),
.io_deq_bits_uop_br_mask (_main_io_deq_bits_uop_br_mask),
.io_deq_bits_uop_br_tag (_main_io_deq_bits_uop_br_tag),
.io_deq_bits_uop_br_type (_main_io_deq_bits_uop_br_type),
.io_deq_bits_uop_is_sfb (_main_io_deq_bits_uop_is_sfb),
.io_deq_bits_uop_is_fence (_main_io_deq_bits_uop_is_fence),
.io_deq_bits_uop_is_fencei (_main_io_deq_bits_uop_is_fencei),
.io_deq_bits_uop_is_sfence (_main_io_deq_bits_uop_is_sfence),
.io_deq_bits_uop_is_amo (_main_io_deq_bits_uop_is_amo),
.io_deq_bits_uop_is_eret (_main_io_deq_bits_uop_is_eret),
.io_deq_bits_uop_is_sys_pc2epc (_main_io_deq_bits_uop_is_sys_pc2epc),
.io_deq_bits_uop_is_rocc (_main_io_deq_bits_uop_is_rocc),
.io_deq_bits_uop_is_mov (_main_io_deq_bits_uop_is_mov),
.io_deq_bits_uop_ftq_idx (_main_io_deq_bits_uop_ftq_idx),
.io_deq_bits_uop_edge_inst (_main_io_deq_bits_uop_edge_inst),
.io_deq_bits_uop_pc_lob (_main_io_deq_bits_uop_pc_lob),
.io_deq_bits_uop_taken (_main_io_deq_bits_uop_taken),
.io_deq_bits_uop_imm_rename (_main_io_deq_bits_uop_imm_rename),
.io_deq_bits_uop_imm_sel (_main_io_deq_bits_uop_imm_sel),
.io_deq_bits_uop_pimm (_main_io_deq_bits_uop_pimm),
.io_deq_bits_uop_imm_packed (_main_io_deq_bits_uop_imm_packed),
.io_deq_bits_uop_op1_sel (_main_io_deq_bits_uop_op1_sel),
.io_deq_bits_uop_op2_sel (_main_io_deq_bits_uop_op2_sel),
.io_deq_bits_uop_fp_ctrl_ldst (_main_io_deq_bits_uop_fp_ctrl_ldst),
.io_deq_bits_uop_fp_ctrl_wen (_main_io_deq_bits_uop_fp_ctrl_wen),
.io_deq_bits_uop_fp_ctrl_ren1 (_main_io_deq_bits_uop_fp_ctrl_ren1),
.io_deq_bits_uop_fp_ctrl_ren2 (_main_io_deq_bits_uop_fp_ctrl_ren2),
.io_deq_bits_uop_fp_ctrl_ren3 (_main_io_deq_bits_uop_fp_ctrl_ren3),
.io_deq_bits_uop_fp_ctrl_swap12 (_main_io_deq_bits_uop_fp_ctrl_swap12),
.io_deq_bits_uop_fp_ctrl_swap23 (_main_io_deq_bits_uop_fp_ctrl_swap23),
.io_deq_bits_uop_fp_ctrl_typeTagIn (_main_io_deq_bits_uop_fp_ctrl_typeTagIn),
.io_deq_bits_uop_fp_ctrl_typeTagOut (_main_io_deq_bits_uop_fp_ctrl_typeTagOut),
.io_deq_bits_uop_fp_ctrl_fromint (_main_io_deq_bits_uop_fp_ctrl_fromint),
.io_deq_bits_uop_fp_ctrl_toint (_main_io_deq_bits_uop_fp_ctrl_toint),
.io_deq_bits_uop_fp_ctrl_fastpipe (_main_io_deq_bits_uop_fp_ctrl_fastpipe),
.io_deq_bits_uop_fp_ctrl_fma (_main_io_deq_bits_uop_fp_ctrl_fma),
.io_deq_bits_uop_fp_ctrl_div (_main_io_deq_bits_uop_fp_ctrl_div),
.io_deq_bits_uop_fp_ctrl_sqrt (_main_io_deq_bits_uop_fp_ctrl_sqrt),
.io_deq_bits_uop_fp_ctrl_wflags (_main_io_deq_bits_uop_fp_ctrl_wflags),
.io_deq_bits_uop_fp_ctrl_vec (_main_io_deq_bits_uop_fp_ctrl_vec),
.io_deq_bits_uop_rob_idx (_main_io_deq_bits_uop_rob_idx),
.io_deq_bits_uop_ldq_idx (_main_io_deq_bits_uop_ldq_idx),
.io_deq_bits_uop_stq_idx (_main_io_deq_bits_uop_stq_idx),
.io_deq_bits_uop_rxq_idx (_main_io_deq_bits_uop_rxq_idx),
.io_deq_bits_uop_pdst (_main_io_deq_bits_uop_pdst),
.io_deq_bits_uop_prs1 (_main_io_deq_bits_uop_prs1),
.io_deq_bits_uop_prs2 (_main_io_deq_bits_uop_prs2),
.io_deq_bits_uop_prs3 (_main_io_deq_bits_uop_prs3),
.io_deq_bits_uop_ppred (_main_io_deq_bits_uop_ppred),
.io_deq_bits_uop_prs1_busy (_main_io_deq_bits_uop_prs1_busy),
.io_deq_bits_uop_prs2_busy (_main_io_deq_bits_uop_prs2_busy),
.io_deq_bits_uop_prs3_busy (_main_io_deq_bits_uop_prs3_busy),
.io_deq_bits_uop_ppred_busy (_main_io_deq_bits_uop_ppred_busy),
.io_deq_bits_uop_stale_pdst (_main_io_deq_bits_uop_stale_pdst),
.io_deq_bits_uop_exception (_main_io_deq_bits_uop_exception),
.io_deq_bits_uop_exc_cause (_main_io_deq_bits_uop_exc_cause),
.io_deq_bits_uop_mem_cmd (_main_io_deq_bits_uop_mem_cmd),
.io_deq_bits_uop_mem_size (_main_io_deq_bits_uop_mem_size),
.io_deq_bits_uop_mem_signed (_main_io_deq_bits_uop_mem_signed),
.io_deq_bits_uop_uses_ldq (_main_io_deq_bits_uop_uses_ldq),
.io_deq_bits_uop_uses_stq (_main_io_deq_bits_uop_uses_stq),
.io_deq_bits_uop_is_unique (_main_io_deq_bits_uop_is_unique),
.io_deq_bits_uop_flush_on_commit (_main_io_deq_bits_uop_flush_on_commit),
.io_deq_bits_uop_csr_cmd (_main_io_deq_bits_uop_csr_cmd),
.io_deq_bits_uop_ldst_is_rs1 (_main_io_deq_bits_uop_ldst_is_rs1),
.io_deq_bits_uop_ldst (_main_io_deq_bits_uop_ldst),
.io_deq_bits_uop_lrs1 (_main_io_deq_bits_uop_lrs1),
.io_deq_bits_uop_lrs2 (_main_io_deq_bits_uop_lrs2),
.io_deq_bits_uop_lrs3 (_main_io_deq_bits_uop_lrs3),
.io_deq_bits_uop_dst_rtype (_main_io_deq_bits_uop_dst_rtype),
.io_deq_bits_uop_lrs1_rtype (_main_io_deq_bits_uop_lrs1_rtype),
.io_deq_bits_uop_lrs2_rtype (_main_io_deq_bits_uop_lrs2_rtype),
.io_deq_bits_uop_frs3_en (_main_io_deq_bits_uop_frs3_en),
.io_deq_bits_uop_fcn_dw (_main_io_deq_bits_uop_fcn_dw),
.io_deq_bits_uop_fcn_op (_main_io_deq_bits_uop_fcn_op),
.io_deq_bits_uop_fp_val (_main_io_deq_bits_uop_fp_val),
.io_deq_bits_uop_fp_rm (_main_io_deq_bits_uop_fp_rm),
.io_deq_bits_uop_fp_typ (_main_io_deq_bits_uop_fp_typ),
.io_deq_bits_uop_xcpt_pf_if (_main_io_deq_bits_uop_xcpt_pf_if),
.io_deq_bits_uop_xcpt_ae_if (_main_io_deq_bits_uop_xcpt_ae_if),
.io_deq_bits_uop_xcpt_ma_if (_main_io_deq_bits_uop_xcpt_ma_if),
.io_deq_bits_uop_bp_debug_if (_main_io_deq_bits_uop_bp_debug_if),
.io_deq_bits_uop_bp_xcpt_if (_main_io_deq_bits_uop_bp_xcpt_if),
.io_deq_bits_uop_debug_fsrc (_main_io_deq_bits_uop_debug_fsrc),
.io_deq_bits_uop_debug_tsrc (_main_io_deq_bits_uop_debug_tsrc),
.io_deq_bits_addr (_main_io_deq_bits_addr),
.io_deq_bits_data (_main_io_deq_bits_data),
.io_deq_bits_is_hella (_main_io_deq_bits_is_hella),
.io_deq_bits_tag_match (_main_io_deq_bits_tag_match),
.io_deq_bits_old_meta_coh_state (_main_io_deq_bits_old_meta_coh_state),
.io_deq_bits_old_meta_tag (_main_io_deq_bits_old_meta_tag),
.io_deq_bits_way_en (_main_io_deq_bits_way_en),
.io_deq_bits_sdq_id (_main_io_deq_bits_sdq_id),
.io_empty (_main_io_empty),
.io_count (_main_io_count)
); // @[util.scala:476:22]
assign out_uop_out_1_inst = _main_io_deq_bits_uop_inst; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_debug_inst = _main_io_deq_bits_uop_debug_inst; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_is_rvc = _main_io_deq_bits_uop_is_rvc; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_debug_pc = _main_io_deq_bits_uop_debug_pc; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_iq_type_0 = _main_io_deq_bits_uop_iq_type_0; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_iq_type_1 = _main_io_deq_bits_uop_iq_type_1; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_iq_type_2 = _main_io_deq_bits_uop_iq_type_2; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_iq_type_3 = _main_io_deq_bits_uop_iq_type_3; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fu_code_0 = _main_io_deq_bits_uop_fu_code_0; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fu_code_1 = _main_io_deq_bits_uop_fu_code_1; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fu_code_2 = _main_io_deq_bits_uop_fu_code_2; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fu_code_3 = _main_io_deq_bits_uop_fu_code_3; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fu_code_4 = _main_io_deq_bits_uop_fu_code_4; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fu_code_5 = _main_io_deq_bits_uop_fu_code_5; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fu_code_6 = _main_io_deq_bits_uop_fu_code_6; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fu_code_7 = _main_io_deq_bits_uop_fu_code_7; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fu_code_8 = _main_io_deq_bits_uop_fu_code_8; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fu_code_9 = _main_io_deq_bits_uop_fu_code_9; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_iw_issued = _main_io_deq_bits_uop_iw_issued; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_iw_issued_partial_agen = _main_io_deq_bits_uop_iw_issued_partial_agen; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_iw_issued_partial_dgen = _main_io_deq_bits_uop_iw_issued_partial_dgen; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_iw_p1_speculative_child = _main_io_deq_bits_uop_iw_p1_speculative_child; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_iw_p2_speculative_child = _main_io_deq_bits_uop_iw_p2_speculative_child; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_iw_p1_bypass_hint = _main_io_deq_bits_uop_iw_p1_bypass_hint; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_iw_p2_bypass_hint = _main_io_deq_bits_uop_iw_p2_bypass_hint; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_iw_p3_bypass_hint = _main_io_deq_bits_uop_iw_p3_bypass_hint; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_dis_col_sel = _main_io_deq_bits_uop_dis_col_sel; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_br_tag = _main_io_deq_bits_uop_br_tag; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_br_type = _main_io_deq_bits_uop_br_type; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_is_sfb = _main_io_deq_bits_uop_is_sfb; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_is_fence = _main_io_deq_bits_uop_is_fence; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_is_fencei = _main_io_deq_bits_uop_is_fencei; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_is_sfence = _main_io_deq_bits_uop_is_sfence; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_is_amo = _main_io_deq_bits_uop_is_amo; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_is_eret = _main_io_deq_bits_uop_is_eret; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_is_sys_pc2epc = _main_io_deq_bits_uop_is_sys_pc2epc; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_is_rocc = _main_io_deq_bits_uop_is_rocc; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_is_mov = _main_io_deq_bits_uop_is_mov; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_ftq_idx = _main_io_deq_bits_uop_ftq_idx; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_edge_inst = _main_io_deq_bits_uop_edge_inst; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_pc_lob = _main_io_deq_bits_uop_pc_lob; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_taken = _main_io_deq_bits_uop_taken; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_imm_rename = _main_io_deq_bits_uop_imm_rename; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_imm_sel = _main_io_deq_bits_uop_imm_sel; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_pimm = _main_io_deq_bits_uop_pimm; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_imm_packed = _main_io_deq_bits_uop_imm_packed; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_op1_sel = _main_io_deq_bits_uop_op1_sel; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_op2_sel = _main_io_deq_bits_uop_op2_sel; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_ldst = _main_io_deq_bits_uop_fp_ctrl_ldst; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_wen = _main_io_deq_bits_uop_fp_ctrl_wen; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_ren1 = _main_io_deq_bits_uop_fp_ctrl_ren1; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_ren2 = _main_io_deq_bits_uop_fp_ctrl_ren2; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_ren3 = _main_io_deq_bits_uop_fp_ctrl_ren3; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_swap12 = _main_io_deq_bits_uop_fp_ctrl_swap12; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_swap23 = _main_io_deq_bits_uop_fp_ctrl_swap23; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_typeTagIn = _main_io_deq_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_typeTagOut = _main_io_deq_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_fromint = _main_io_deq_bits_uop_fp_ctrl_fromint; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_toint = _main_io_deq_bits_uop_fp_ctrl_toint; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_fastpipe = _main_io_deq_bits_uop_fp_ctrl_fastpipe; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_fma = _main_io_deq_bits_uop_fp_ctrl_fma; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_div = _main_io_deq_bits_uop_fp_ctrl_div; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_sqrt = _main_io_deq_bits_uop_fp_ctrl_sqrt; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_wflags = _main_io_deq_bits_uop_fp_ctrl_wflags; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_vec = _main_io_deq_bits_uop_fp_ctrl_vec; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_rob_idx = _main_io_deq_bits_uop_rob_idx; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_ldq_idx = _main_io_deq_bits_uop_ldq_idx; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_stq_idx = _main_io_deq_bits_uop_stq_idx; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_rxq_idx = _main_io_deq_bits_uop_rxq_idx; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_pdst = _main_io_deq_bits_uop_pdst; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_prs1 = _main_io_deq_bits_uop_prs1; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_prs2 = _main_io_deq_bits_uop_prs2; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_prs3 = _main_io_deq_bits_uop_prs3; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_ppred = _main_io_deq_bits_uop_ppred; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_prs1_busy = _main_io_deq_bits_uop_prs1_busy; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_prs2_busy = _main_io_deq_bits_uop_prs2_busy; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_prs3_busy = _main_io_deq_bits_uop_prs3_busy; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_ppred_busy = _main_io_deq_bits_uop_ppred_busy; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_stale_pdst = _main_io_deq_bits_uop_stale_pdst; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_exception = _main_io_deq_bits_uop_exception; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_exc_cause = _main_io_deq_bits_uop_exc_cause; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_mem_cmd = _main_io_deq_bits_uop_mem_cmd; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_mem_size = _main_io_deq_bits_uop_mem_size; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_mem_signed = _main_io_deq_bits_uop_mem_signed; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_uses_ldq = _main_io_deq_bits_uop_uses_ldq; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_uses_stq = _main_io_deq_bits_uop_uses_stq; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_is_unique = _main_io_deq_bits_uop_is_unique; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_flush_on_commit = _main_io_deq_bits_uop_flush_on_commit; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_csr_cmd = _main_io_deq_bits_uop_csr_cmd; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_ldst_is_rs1 = _main_io_deq_bits_uop_ldst_is_rs1; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_ldst = _main_io_deq_bits_uop_ldst; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_lrs1 = _main_io_deq_bits_uop_lrs1; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_lrs2 = _main_io_deq_bits_uop_lrs2; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_lrs3 = _main_io_deq_bits_uop_lrs3; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_dst_rtype = _main_io_deq_bits_uop_dst_rtype; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_lrs1_rtype = _main_io_deq_bits_uop_lrs1_rtype; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_lrs2_rtype = _main_io_deq_bits_uop_lrs2_rtype; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_frs3_en = _main_io_deq_bits_uop_frs3_en; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fcn_dw = _main_io_deq_bits_uop_fcn_dw; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fcn_op = _main_io_deq_bits_uop_fcn_op; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_val = _main_io_deq_bits_uop_fp_val; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_rm = _main_io_deq_bits_uop_fp_rm; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_typ = _main_io_deq_bits_uop_fp_typ; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_xcpt_pf_if = _main_io_deq_bits_uop_xcpt_pf_if; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_xcpt_ae_if = _main_io_deq_bits_uop_xcpt_ae_if; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_xcpt_ma_if = _main_io_deq_bits_uop_xcpt_ma_if; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_bp_debug_if = _main_io_deq_bits_uop_bp_debug_if; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_bp_xcpt_if = _main_io_deq_bits_uop_bp_xcpt_if; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_debug_fsrc = _main_io_deq_bits_uop_debug_fsrc; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_debug_tsrc = _main_io_deq_bits_uop_debug_tsrc; // @[util.scala:104:23, :476:22]
assign _out_uop_out_br_mask_T_3 = _main_io_deq_bits_uop_br_mask; // @[util.scala:93:25, :476:22]
assign io_enq_ready = io_enq_ready_0; // @[util.scala:458:7]
assign io_deq_valid = io_deq_valid_0; // @[util.scala:458:7]
assign io_deq_bits_uop_inst = io_deq_bits_uop_inst_0; // @[util.scala:458:7]
assign io_deq_bits_uop_debug_inst = io_deq_bits_uop_debug_inst_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_rvc = io_deq_bits_uop_is_rvc_0; // @[util.scala:458:7]
assign io_deq_bits_uop_debug_pc = io_deq_bits_uop_debug_pc_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iq_type_0 = io_deq_bits_uop_iq_type_0_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iq_type_1 = io_deq_bits_uop_iq_type_1_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iq_type_2 = io_deq_bits_uop_iq_type_2_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iq_type_3 = io_deq_bits_uop_iq_type_3_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_0 = io_deq_bits_uop_fu_code_0_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_1 = io_deq_bits_uop_fu_code_1_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_2 = io_deq_bits_uop_fu_code_2_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_3 = io_deq_bits_uop_fu_code_3_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_4 = io_deq_bits_uop_fu_code_4_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_5 = io_deq_bits_uop_fu_code_5_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_6 = io_deq_bits_uop_fu_code_6_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_7 = io_deq_bits_uop_fu_code_7_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_8 = io_deq_bits_uop_fu_code_8_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_9 = io_deq_bits_uop_fu_code_9_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_issued = io_deq_bits_uop_iw_issued_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_issued_partial_agen = io_deq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_issued_partial_dgen = io_deq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_p1_speculative_child = io_deq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_p2_speculative_child = io_deq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_p1_bypass_hint = io_deq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_p2_bypass_hint = io_deq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_p3_bypass_hint = io_deq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7]
assign io_deq_bits_uop_dis_col_sel = io_deq_bits_uop_dis_col_sel_0; // @[util.scala:458:7]
assign io_deq_bits_uop_br_mask = io_deq_bits_uop_br_mask_0; // @[util.scala:458:7]
assign io_deq_bits_uop_br_tag = io_deq_bits_uop_br_tag_0; // @[util.scala:458:7]
assign io_deq_bits_uop_br_type = io_deq_bits_uop_br_type_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_sfb = io_deq_bits_uop_is_sfb_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_fence = io_deq_bits_uop_is_fence_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_fencei = io_deq_bits_uop_is_fencei_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_sfence = io_deq_bits_uop_is_sfence_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_amo = io_deq_bits_uop_is_amo_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_eret = io_deq_bits_uop_is_eret_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_sys_pc2epc = io_deq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_rocc = io_deq_bits_uop_is_rocc_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_mov = io_deq_bits_uop_is_mov_0; // @[util.scala:458:7]
assign io_deq_bits_uop_ftq_idx = io_deq_bits_uop_ftq_idx_0; // @[util.scala:458:7]
assign io_deq_bits_uop_edge_inst = io_deq_bits_uop_edge_inst_0; // @[util.scala:458:7]
assign io_deq_bits_uop_pc_lob = io_deq_bits_uop_pc_lob_0; // @[util.scala:458:7]
assign io_deq_bits_uop_taken = io_deq_bits_uop_taken_0; // @[util.scala:458:7]
assign io_deq_bits_uop_imm_rename = io_deq_bits_uop_imm_rename_0; // @[util.scala:458:7]
assign io_deq_bits_uop_imm_sel = io_deq_bits_uop_imm_sel_0; // @[util.scala:458:7]
assign io_deq_bits_uop_pimm = io_deq_bits_uop_pimm_0; // @[util.scala:458:7]
assign io_deq_bits_uop_imm_packed = io_deq_bits_uop_imm_packed_0; // @[util.scala:458:7]
assign io_deq_bits_uop_op1_sel = io_deq_bits_uop_op1_sel_0; // @[util.scala:458:7]
assign io_deq_bits_uop_op2_sel = io_deq_bits_uop_op2_sel_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_ldst = io_deq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_wen = io_deq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_ren1 = io_deq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_ren2 = io_deq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_ren3 = io_deq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_swap12 = io_deq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_swap23 = io_deq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_typeTagIn = io_deq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_typeTagOut = io_deq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_fromint = io_deq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_toint = io_deq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_fastpipe = io_deq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_fma = io_deq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_div = io_deq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_sqrt = io_deq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_wflags = io_deq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_vec = io_deq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7]
assign io_deq_bits_uop_rob_idx = io_deq_bits_uop_rob_idx_0; // @[util.scala:458:7]
assign io_deq_bits_uop_ldq_idx = io_deq_bits_uop_ldq_idx_0; // @[util.scala:458:7]
assign io_deq_bits_uop_stq_idx = io_deq_bits_uop_stq_idx_0; // @[util.scala:458:7]
assign io_deq_bits_uop_rxq_idx = io_deq_bits_uop_rxq_idx_0; // @[util.scala:458:7]
assign io_deq_bits_uop_pdst = io_deq_bits_uop_pdst_0; // @[util.scala:458:7]
assign io_deq_bits_uop_prs1 = io_deq_bits_uop_prs1_0; // @[util.scala:458:7]
assign io_deq_bits_uop_prs2 = io_deq_bits_uop_prs2_0; // @[util.scala:458:7]
assign io_deq_bits_uop_prs3 = io_deq_bits_uop_prs3_0; // @[util.scala:458:7]
assign io_deq_bits_uop_ppred = io_deq_bits_uop_ppred_0; // @[util.scala:458:7]
assign io_deq_bits_uop_prs1_busy = io_deq_bits_uop_prs1_busy_0; // @[util.scala:458:7]
assign io_deq_bits_uop_prs2_busy = io_deq_bits_uop_prs2_busy_0; // @[util.scala:458:7]
assign io_deq_bits_uop_prs3_busy = io_deq_bits_uop_prs3_busy_0; // @[util.scala:458:7]
assign io_deq_bits_uop_ppred_busy = io_deq_bits_uop_ppred_busy_0; // @[util.scala:458:7]
assign io_deq_bits_uop_stale_pdst = io_deq_bits_uop_stale_pdst_0; // @[util.scala:458:7]
assign io_deq_bits_uop_exception = io_deq_bits_uop_exception_0; // @[util.scala:458:7]
assign io_deq_bits_uop_exc_cause = io_deq_bits_uop_exc_cause_0; // @[util.scala:458:7]
assign io_deq_bits_uop_mem_cmd = io_deq_bits_uop_mem_cmd_0; // @[util.scala:458:7]
assign io_deq_bits_uop_mem_size = io_deq_bits_uop_mem_size_0; // @[util.scala:458:7]
assign io_deq_bits_uop_mem_signed = io_deq_bits_uop_mem_signed_0; // @[util.scala:458:7]
assign io_deq_bits_uop_uses_ldq = io_deq_bits_uop_uses_ldq_0; // @[util.scala:458:7]
assign io_deq_bits_uop_uses_stq = io_deq_bits_uop_uses_stq_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_unique = io_deq_bits_uop_is_unique_0; // @[util.scala:458:7]
assign io_deq_bits_uop_flush_on_commit = io_deq_bits_uop_flush_on_commit_0; // @[util.scala:458:7]
assign io_deq_bits_uop_csr_cmd = io_deq_bits_uop_csr_cmd_0; // @[util.scala:458:7]
assign io_deq_bits_uop_ldst_is_rs1 = io_deq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7]
assign io_deq_bits_uop_ldst = io_deq_bits_uop_ldst_0; // @[util.scala:458:7]
assign io_deq_bits_uop_lrs1 = io_deq_bits_uop_lrs1_0; // @[util.scala:458:7]
assign io_deq_bits_uop_lrs2 = io_deq_bits_uop_lrs2_0; // @[util.scala:458:7]
assign io_deq_bits_uop_lrs3 = io_deq_bits_uop_lrs3_0; // @[util.scala:458:7]
assign io_deq_bits_uop_dst_rtype = io_deq_bits_uop_dst_rtype_0; // @[util.scala:458:7]
assign io_deq_bits_uop_lrs1_rtype = io_deq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7]
assign io_deq_bits_uop_lrs2_rtype = io_deq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7]
assign io_deq_bits_uop_frs3_en = io_deq_bits_uop_frs3_en_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fcn_dw = io_deq_bits_uop_fcn_dw_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fcn_op = io_deq_bits_uop_fcn_op_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_val = io_deq_bits_uop_fp_val_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_rm = io_deq_bits_uop_fp_rm_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_typ = io_deq_bits_uop_fp_typ_0; // @[util.scala:458:7]
assign io_deq_bits_uop_xcpt_pf_if = io_deq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7]
assign io_deq_bits_uop_xcpt_ae_if = io_deq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7]
assign io_deq_bits_uop_xcpt_ma_if = io_deq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7]
assign io_deq_bits_uop_bp_debug_if = io_deq_bits_uop_bp_debug_if_0; // @[util.scala:458:7]
assign io_deq_bits_uop_bp_xcpt_if = io_deq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7]
assign io_deq_bits_uop_debug_fsrc = io_deq_bits_uop_debug_fsrc_0; // @[util.scala:458:7]
assign io_deq_bits_uop_debug_tsrc = io_deq_bits_uop_debug_tsrc_0; // @[util.scala:458:7]
assign io_deq_bits_addr = io_deq_bits_addr_0; // @[util.scala:458:7]
assign io_deq_bits_data = io_deq_bits_data_0; // @[util.scala:458:7]
assign io_deq_bits_is_hella = io_deq_bits_is_hella_0; // @[util.scala:458:7]
assign io_deq_bits_tag_match = io_deq_bits_tag_match_0; // @[util.scala:458:7]
assign io_deq_bits_old_meta_coh_state = io_deq_bits_old_meta_coh_state_0; // @[util.scala:458:7]
assign io_deq_bits_old_meta_tag = io_deq_bits_old_meta_tag_0; // @[util.scala:458:7]
assign io_deq_bits_way_en = io_deq_bits_way_en_0; // @[util.scala:458:7]
assign io_deq_bits_sdq_id = io_deq_bits_sdq_id_0; // @[util.scala:458:7]
assign io_empty = io_empty_0; // @[util.scala:458:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor_34( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_b_ready, // @[Monitor.scala:20:14]
input io_in_b_valid, // @[Monitor.scala:20:14]
input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14]
input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14]
input io_in_c_ready, // @[Monitor.scala:20:14]
input io_in_c_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_c_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_c_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14]
input io_in_c_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_e_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_e_bits_sink // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71]
wire [12:0] _GEN_0 = {10'h0, io_in_c_bits_size}; // @[package.scala:243:71]
wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [6:0] source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
wire _d_first_T_3 = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala:51:35]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [6:0] source_1; // @[Monitor.scala:541:22]
reg [2:0] sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [2:0] b_first_counter; // @[Edges.scala:229:27]
reg [1:0] param_2; // @[Monitor.scala:411:22]
reg [31:0] address_1; // @[Monitor.scala:414:22]
wire _c_first_T_1 = io_in_c_ready & io_in_c_valid; // @[Decoupled.scala:51:35]
reg [2:0] c_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_3; // @[Monitor.scala:515:22]
reg [2:0] param_3; // @[Monitor.scala:516:22]
reg [2:0] size_3; // @[Monitor.scala:517:22]
reg [6:0] source_3; // @[Monitor.scala:518:22]
reg [31:0] address_2; // @[Monitor.scala:519:22]
reg [80:0] inflight; // @[Monitor.scala:614:27]
reg [323:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [323:0] inflight_sizes; // @[Monitor.scala:618:33]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire [127:0] _GEN_1 = {121'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35]
wire _GEN_2 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35]
wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46]
wire _GEN_3 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74]
wire [127:0] _GEN_4 = {121'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [80:0] inflight_1; // @[Monitor.scala:726:35]
reg [323:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg [2:0] c_first_counter_1; // @[Edges.scala:229:27]
wire c_first_1 = c_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _GEN_5 = io_in_c_bits_opcode[2] & io_in_c_bits_opcode[1]; // @[Edges.scala:68:{36,40,51}]
wire [127:0] _GEN_6 = {121'h0, io_in_c_bits_source}; // @[OneHot.scala:58:35]
wire _GEN_7 = _c_first_T_1 & c_first_1 & _GEN_5; // @[Decoupled.scala:51:35]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
reg [6:0] inflight_2; // @[Monitor.scala:828:27]
reg [2:0] d_first_counter_3; // @[Edges.scala:229:27]
wire d_first_3 = d_first_counter_3 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _GEN_8 = _d_first_T_3 & d_first_3 & io_in_d_bits_opcode[2] & ~(io_in_d_bits_opcode[1]); // @[Decoupled.scala:51:35]
wire [7:0] _d_set_T = 8'h1 << io_in_d_bits_sink; // @[OneHot.scala:58:35]
wire [6:0] d_set = _GEN_8 ? _d_set_T[6:0] : 7'h0; // @[OneHot.scala:58:35] |
Generate the Verilog code corresponding to the following Chisel files.
File SwitchAllocator.scala:
package constellation.router
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.util._
import constellation.channel._
class SwitchAllocReq(val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams])
(implicit val p: Parameters) extends Bundle with HasRouterOutputParams {
val vc_sel = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) })
val tail = Bool()
}
class SwitchArbiter(inN: Int, outN: Int, outParams: Seq[ChannelParams], egressParams: Seq[EgressChannelParams])(implicit val p: Parameters) extends Module {
val io = IO(new Bundle {
val in = Flipped(Vec(inN, Decoupled(new SwitchAllocReq(outParams, egressParams))))
val out = Vec(outN, Decoupled(new SwitchAllocReq(outParams, egressParams)))
val chosen_oh = Vec(outN, Output(UInt(inN.W)))
})
val lock = Seq.fill(outN) { RegInit(0.U(inN.W)) }
val unassigned = Cat(io.in.map(_.valid).reverse) & ~(lock.reduce(_|_))
val mask = RegInit(0.U(inN.W))
val choices = Wire(Vec(outN, UInt(inN.W)))
var sel = PriorityEncoderOH(Cat(unassigned, unassigned & ~mask))
for (i <- 0 until outN) {
choices(i) := sel | (sel >> inN)
sel = PriorityEncoderOH(unassigned & ~choices(i))
}
io.in.foreach(_.ready := false.B)
var chosens = 0.U(inN.W)
val in_tails = Cat(io.in.map(_.bits.tail).reverse)
for (i <- 0 until outN) {
val in_valids = Cat((0 until inN).map { j => io.in(j).valid && !chosens(j) }.reverse)
val chosen = Mux((in_valids & lock(i) & ~chosens).orR, lock(i), choices(i))
io.chosen_oh(i) := chosen
io.out(i).valid := (in_valids & chosen).orR
io.out(i).bits := Mux1H(chosen, io.in.map(_.bits))
for (j <- 0 until inN) {
when (chosen(j) && io.out(i).ready) {
io.in(j).ready := true.B
}
}
chosens = chosens | chosen
when (io.out(i).fire) {
lock(i) := chosen & ~in_tails
}
}
when (io.out(0).fire) {
mask := (0 until inN).map { i => (io.chosen_oh(0) >> i) }.reduce(_|_)
} .otherwise {
mask := Mux(~mask === 0.U, 0.U, (mask << 1) | 1.U(1.W))
}
}
class SwitchAllocator(
val routerParams: RouterParams,
val inParams: Seq[ChannelParams],
val outParams: Seq[ChannelParams],
val ingressParams: Seq[IngressChannelParams],
val egressParams: Seq[EgressChannelParams]
)(implicit val p: Parameters) extends Module
with HasRouterParams
with HasRouterInputParams
with HasRouterOutputParams {
val io = IO(new Bundle {
val req = MixedVec(allInParams.map(u =>
Vec(u.destSpeedup, Flipped(Decoupled(new SwitchAllocReq(outParams, egressParams))))))
val credit_alloc = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Output(new OutputCreditAlloc))})
val switch_sel = MixedVec(allOutParams.map { o => Vec(o.srcSpeedup,
MixedVec(allInParams.map { i => Vec(i.destSpeedup, Output(Bool())) })) })
})
val nInputChannels = allInParams.map(_.nVirtualChannels).sum
val arbs = allOutParams.map { oP => Module(new SwitchArbiter(
allInParams.map(_.destSpeedup).reduce(_+_),
oP.srcSpeedup,
outParams,
egressParams
))}
arbs.foreach(_.io.out.foreach(_.ready := true.B))
var idx = 0
io.req.foreach(_.foreach { o =>
val fires = Wire(Vec(arbs.size, Bool()))
arbs.zipWithIndex.foreach { case (a,i) =>
a.io.in(idx).valid := o.valid && o.bits.vc_sel(i).reduce(_||_)
a.io.in(idx).bits := o.bits
fires(i) := a.io.in(idx).fire
}
o.ready := fires.reduce(_||_)
idx += 1
})
for (i <- 0 until nAllOutputs) {
for (j <- 0 until allOutParams(i).srcSpeedup) {
idx = 0
for (m <- 0 until nAllInputs) {
for (n <- 0 until allInParams(m).destSpeedup) {
io.switch_sel(i)(j)(m)(n) := arbs(i).io.in(idx).valid && arbs(i).io.chosen_oh(j)(idx) && arbs(i).io.out(j).valid
idx += 1
}
}
}
}
io.credit_alloc.foreach(_.foreach(_.alloc := false.B))
io.credit_alloc.foreach(_.foreach(_.tail := false.B))
(arbs zip io.credit_alloc).zipWithIndex.map { case ((a,i),t) =>
for (j <- 0 until i.size) {
for (k <- 0 until a.io.out.size) {
when (a.io.out(k).valid && a.io.out(k).bits.vc_sel(t)(j)) {
i(j).alloc := true.B
i(j).tail := a.io.out(k).bits.tail
}
}
}
}
}
| module SwitchArbiter_45( // @[SwitchAllocator.scala:17:7]
input clock, // @[SwitchAllocator.scala:17:7]
input reset, // @[SwitchAllocator.scala:17:7]
output io_in_0_ready, // @[SwitchAllocator.scala:18:14]
input io_in_0_valid, // @[SwitchAllocator.scala:18:14]
input io_in_0_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14]
input io_in_0_bits_vc_sel_0_0, // @[SwitchAllocator.scala:18:14]
input io_in_0_bits_tail, // @[SwitchAllocator.scala:18:14]
output io_in_1_ready, // @[SwitchAllocator.scala:18:14]
input io_in_1_valid, // @[SwitchAllocator.scala:18:14]
input io_in_1_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14]
input io_in_1_bits_vc_sel_0_0, // @[SwitchAllocator.scala:18:14]
input io_in_1_bits_vc_sel_0_1, // @[SwitchAllocator.scala:18:14]
input io_in_1_bits_tail, // @[SwitchAllocator.scala:18:14]
output io_in_2_ready, // @[SwitchAllocator.scala:18:14]
input io_in_2_valid, // @[SwitchAllocator.scala:18:14]
input io_in_2_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14]
input io_in_2_bits_vc_sel_0_2, // @[SwitchAllocator.scala:18:14]
input io_in_2_bits_tail, // @[SwitchAllocator.scala:18:14]
output io_in_3_ready, // @[SwitchAllocator.scala:18:14]
input io_in_3_valid, // @[SwitchAllocator.scala:18:14]
input io_in_3_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14]
input io_in_3_bits_vc_sel_0_2, // @[SwitchAllocator.scala:18:14]
input io_in_3_bits_vc_sel_0_3, // @[SwitchAllocator.scala:18:14]
input io_in_3_bits_tail, // @[SwitchAllocator.scala:18:14]
input io_out_0_ready, // @[SwitchAllocator.scala:18:14]
output io_out_0_valid, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_vc_sel_0_0, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_vc_sel_0_1, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_vc_sel_0_2, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_vc_sel_0_3, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_tail, // @[SwitchAllocator.scala:18:14]
output [3:0] io_chosen_oh_0 // @[SwitchAllocator.scala:18:14]
);
reg [3:0] lock_0; // @[SwitchAllocator.scala:24:38]
wire [3:0] unassigned = {io_in_3_valid, io_in_2_valid, io_in_1_valid, io_in_0_valid} & ~lock_0; // @[SwitchAllocator.scala:24:38, :25:{23,52,54}]
reg [3:0] mask; // @[SwitchAllocator.scala:27:21]
wire [3:0] _sel_T_1 = unassigned & ~mask; // @[SwitchAllocator.scala:25:52, :27:21, :30:{58,60}]
wire [7:0] sel = _sel_T_1[0] ? 8'h1 : _sel_T_1[1] ? 8'h2 : _sel_T_1[2] ? 8'h4 : _sel_T_1[3] ? 8'h8 : unassigned[0] ? 8'h10 : unassigned[1] ? 8'h20 : unassigned[2] ? 8'h40 : {unassigned[3], 7'h0}; // @[OneHot.scala:85:71]
wire [3:0] in_valids = {io_in_3_valid, io_in_2_valid, io_in_1_valid, io_in_0_valid}; // @[SwitchAllocator.scala:41:24]
wire [3:0] chosen = (|(in_valids & lock_0)) ? lock_0 : sel[3:0] | sel[7:4]; // @[Mux.scala:50:70]
wire [3:0] _io_out_0_valid_T = in_valids & chosen; // @[SwitchAllocator.scala:41:24, :42:21, :44:35]
wire _GEN = io_out_0_ready & (|_io_out_0_valid_T); // @[Decoupled.scala:51:35]
wire [2:0] _GEN_0 = chosen[2:0] | chosen[3:1]; // @[SwitchAllocator.scala:42:21, :58:{55,71}]
wire [1:0] _GEN_1 = _GEN_0[1:0] | chosen[3:2]; // @[SwitchAllocator.scala:42:21, :58:{55,71}]
always @(posedge clock) begin // @[SwitchAllocator.scala:17:7]
if (reset) begin // @[SwitchAllocator.scala:17:7]
lock_0 <= 4'h0; // @[SwitchAllocator.scala:24:38]
mask <= 4'h0; // @[SwitchAllocator.scala:27:21]
end
else begin // @[SwitchAllocator.scala:17:7]
if (_GEN) // @[Decoupled.scala:51:35]
lock_0 <= chosen & ~{io_in_3_bits_tail, io_in_2_bits_tail, io_in_1_bits_tail, io_in_0_bits_tail}; // @[SwitchAllocator.scala:24:38, :39:21, :42:21, :53:{25,27}]
mask <= _GEN ? {chosen[3], _GEN_0[2], _GEN_1[1], _GEN_1[0] | chosen[3]} : (&mask) ? 4'h0 : {mask[2:0], 1'h1}; // @[Decoupled.scala:51:35]
end
always @(posedge) |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Bundles.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import freechips.rocketchip.util._
import scala.collection.immutable.ListMap
import chisel3.util.Decoupled
import chisel3.util.DecoupledIO
import chisel3.reflect.DataMirror
abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle
// common combos in lazy policy:
// Put + Acquire
// Release + AccessAck
object TLMessages
{
// A B C D E
def PutFullData = 0.U // . . => AccessAck
def PutPartialData = 1.U // . . => AccessAck
def ArithmeticData = 2.U // . . => AccessAckData
def LogicalData = 3.U // . . => AccessAckData
def Get = 4.U // . . => AccessAckData
def Hint = 5.U // . . => HintAck
def AcquireBlock = 6.U // . => Grant[Data]
def AcquirePerm = 7.U // . => Grant[Data]
def Probe = 6.U // . => ProbeAck[Data]
def AccessAck = 0.U // . .
def AccessAckData = 1.U // . .
def HintAck = 2.U // . .
def ProbeAck = 4.U // .
def ProbeAckData = 5.U // .
def Release = 6.U // . => ReleaseAck
def ReleaseData = 7.U // . => ReleaseAck
def Grant = 4.U // . => GrantAck
def GrantData = 5.U // . => GrantAck
def ReleaseAck = 6.U // .
def GrantAck = 0.U // .
def isA(x: UInt) = x <= AcquirePerm
def isB(x: UInt) = x <= Probe
def isC(x: UInt) = x <= ReleaseData
def isD(x: UInt) = x <= ReleaseAck
def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant)
def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck)
def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("AcquireBlock",TLPermissions.PermMsgGrow),
("AcquirePerm",TLPermissions.PermMsgGrow))
def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("Probe",TLPermissions.PermMsgCap))
def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("ProbeAck",TLPermissions.PermMsgReport),
("ProbeAckData",TLPermissions.PermMsgReport),
("Release",TLPermissions.PermMsgReport),
("ReleaseData",TLPermissions.PermMsgReport))
def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("Grant",TLPermissions.PermMsgCap),
("GrantData",TLPermissions.PermMsgCap),
("ReleaseAck",TLPermissions.PermMsgReserved))
}
/**
* The three primary TileLink permissions are:
* (T)runk: the agent is (or is on inwards path to) the global point of serialization.
* (B)ranch: the agent is on an outwards path to
* (N)one:
* These permissions are permuted by transfer operations in various ways.
* Operations can cap permissions, request for them to be grown or shrunk,
* or for a report on their current status.
*/
object TLPermissions
{
val aWidth = 2
val bdWidth = 2
val cWidth = 3
// Cap types (Grant = new permissions, Probe = permisions <= target)
def toT = 0.U(bdWidth.W)
def toB = 1.U(bdWidth.W)
def toN = 2.U(bdWidth.W)
def isCap(x: UInt) = x <= toN
// Grow types (Acquire = permissions >= target)
def NtoB = 0.U(aWidth.W)
def NtoT = 1.U(aWidth.W)
def BtoT = 2.U(aWidth.W)
def isGrow(x: UInt) = x <= BtoT
// Shrink types (ProbeAck, Release)
def TtoB = 0.U(cWidth.W)
def TtoN = 1.U(cWidth.W)
def BtoN = 2.U(cWidth.W)
def isShrink(x: UInt) = x <= BtoN
// Report types (ProbeAck, Release)
def TtoT = 3.U(cWidth.W)
def BtoB = 4.U(cWidth.W)
def NtoN = 5.U(cWidth.W)
def isReport(x: UInt) = x <= NtoN
def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT")
def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN")
def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN")
def PermMsgReserved:Seq[String] = Seq("Reserved")
}
object TLAtomics
{
val width = 3
// Arithmetic types
def MIN = 0.U(width.W)
def MAX = 1.U(width.W)
def MINU = 2.U(width.W)
def MAXU = 3.U(width.W)
def ADD = 4.U(width.W)
def isArithmetic(x: UInt) = x <= ADD
// Logical types
def XOR = 0.U(width.W)
def OR = 1.U(width.W)
def AND = 2.U(width.W)
def SWAP = 3.U(width.W)
def isLogical(x: UInt) = x <= SWAP
def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD")
def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP")
}
object TLHints
{
val width = 1
def PREFETCH_READ = 0.U(width.W)
def PREFETCH_WRITE = 1.U(width.W)
def isHints(x: UInt) = x <= PREFETCH_WRITE
def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite")
}
sealed trait TLChannel extends TLBundleBase {
val channelName: String
}
sealed trait TLDataChannel extends TLChannel
sealed trait TLAddrChannel extends TLDataChannel
final class TLBundleA(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleA_${params.shortName}"
val channelName = "'A' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleB(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleB_${params.shortName}"
val channelName = "'B' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val address = UInt(params.addressBits.W) // from
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleC(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleC_${params.shortName}"
val channelName = "'C' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.cWidth.W) // shrink or report perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleD(params: TLBundleParameters)
extends TLBundleBase(params) with TLDataChannel
{
override def typeName = s"TLBundleD_${params.shortName}"
val channelName = "'D' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val sink = UInt(params.sinkBits.W) // from
val denied = Bool() // implies corrupt iff *Data
val user = BundleMap(params.responseFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleE(params: TLBundleParameters)
extends TLBundleBase(params) with TLChannel
{
override def typeName = s"TLBundleE_${params.shortName}"
val channelName = "'E' channel"
val sink = UInt(params.sinkBits.W) // to
}
class TLBundle(val params: TLBundleParameters) extends Record
{
// Emulate a Bundle with elements abcde or ad depending on params.hasBCE
private val optA = Some (Decoupled(new TLBundleA(params)))
private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params))))
private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params)))
private val optD = Some (Flipped(Decoupled(new TLBundleD(params))))
private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params)))
def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params)))))
def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params)))))
def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params)))))
def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params)))))
def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params)))))
val elements =
if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a)
else ListMap("d" -> d, "a" -> a)
def tieoff(): Unit = {
DataMirror.specifiedDirectionOf(a.ready) match {
case SpecifiedDirection.Input =>
a.ready := false.B
c.ready := false.B
e.ready := false.B
b.valid := false.B
d.valid := false.B
case SpecifiedDirection.Output =>
a.valid := false.B
c.valid := false.B
e.valid := false.B
b.ready := false.B
d.ready := false.B
case _ =>
}
}
}
object TLBundle
{
def apply(params: TLBundleParameters) = new TLBundle(params)
}
class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle
class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params)
{
val a = new AsyncBundle(new TLBundleA(params.base), params.async)
val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async))
val c = new AsyncBundle(new TLBundleC(params.base), params.async)
val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async))
val e = new AsyncBundle(new TLBundleE(params.base), params.async)
}
class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = RationalIO(new TLBundleA(params))
val b = Flipped(RationalIO(new TLBundleB(params)))
val c = RationalIO(new TLBundleC(params))
val d = Flipped(RationalIO(new TLBundleD(params)))
val e = RationalIO(new TLBundleE(params))
}
class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = CreditedIO(new TLBundleA(params))
val b = Flipped(CreditedIO(new TLBundleB(params)))
val c = CreditedIO(new TLBundleC(params))
val d = Flipped(CreditedIO(new TLBundleD(params)))
val e = CreditedIO(new TLBundleE(params))
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor_23( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [7:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [7:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59]
wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27]
wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25]
wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_41 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_67 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_69 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_73 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_75 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_79 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_81 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_85 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_87 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_97 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_105 = 1'h1; // @[Parameters.scala:56:32]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28]
wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_first_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_first_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_first_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_first_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_set_wo_ready_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_set_wo_ready_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_opcodes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_opcodes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_sizes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_sizes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_opcodes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_opcodes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_sizes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_sizes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_probe_ack_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_probe_ack_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_probe_ack_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_probe_ack_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _same_cycle_resp_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _same_cycle_resp_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _same_cycle_resp_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _same_cycle_resp_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _same_cycle_resp_WIRE_4_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _same_cycle_resp_WIRE_5_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57]
wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57]
wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [2051:0] _c_sizes_set_T_1 = 2052'h0; // @[Monitor.scala:768:52]
wire [10:0] _c_opcodes_set_T = 11'h0; // @[Monitor.scala:767:79]
wire [10:0] _c_sizes_set_T = 11'h0; // @[Monitor.scala:768:77]
wire [2050:0] _c_opcodes_set_T_1 = 2051'h0; // @[Monitor.scala:767:54]
wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59]
wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40]
wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [255:0] _c_set_wo_ready_T = 256'h1; // @[OneHot.scala:58:35]
wire [255:0] _c_set_T = 256'h1; // @[OneHot.scala:58:35]
wire [1031:0] c_sizes_set = 1032'h0; // @[Monitor.scala:741:34]
wire [515:0] c_opcodes_set = 516'h0; // @[Monitor.scala:740:34]
wire [128:0] c_set = 129'h0; // @[Monitor.scala:738:34]
wire [128:0] c_set_wo_ready = 129'h0; // @[Monitor.scala:739:34]
wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117]
wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48]
wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119]
wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [7:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 8'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] _source_ok_T_1 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_7 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_13 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_19 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 6'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 6'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_14 = _source_ok_T_13 == 6'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 6'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire _source_ok_T_25 = io_in_a_bits_source_0 == 8'h44; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31]
wire _source_ok_T_26 = io_in_a_bits_source_0 == 8'h45; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31]
wire _source_ok_T_27 = io_in_a_bits_source_0 == 8'h46; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_7 = _source_ok_T_27; // @[Parameters.scala:1138:31]
wire _source_ok_T_28 = io_in_a_bits_source_0 == 8'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_8 = _source_ok_T_28; // @[Parameters.scala:1138:31]
wire _source_ok_T_29 = io_in_a_bits_source_0 == 8'h41; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_9 = _source_ok_T_29; // @[Parameters.scala:1138:31]
wire _source_ok_T_30 = io_in_a_bits_source_0 == 8'h42; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_10 = _source_ok_T_30; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_31 = io_in_a_bits_source_0[7:3]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_39 = io_in_a_bits_source_0[7:3]; // @[Monitor.scala:36:7]
wire _source_ok_T_32 = _source_ok_T_31 == 5'h6; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_35 = source_ok_uncommonBits_4 < 3'h5; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_36 = _source_ok_T_34 & _source_ok_T_35; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_11 = _source_ok_T_36; // @[Parameters.scala:1138:31]
wire _source_ok_T_37 = io_in_a_bits_source_0 == 8'h35; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_12 = _source_ok_T_37; // @[Parameters.scala:1138:31]
wire _source_ok_T_38 = io_in_a_bits_source_0 == 8'h38; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_13 = _source_ok_T_38; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_40 = _source_ok_T_39 == 5'h4; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_42 = _source_ok_T_40; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_43 = source_ok_uncommonBits_5 < 3'h5; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_44 = _source_ok_T_42 & _source_ok_T_43; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_14 = _source_ok_T_44; // @[Parameters.scala:1138:31]
wire _source_ok_T_45 = io_in_a_bits_source_0 == 8'h25; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_15 = _source_ok_T_45; // @[Parameters.scala:1138:31]
wire _source_ok_T_46 = io_in_a_bits_source_0 == 8'h28; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_16 = _source_ok_T_46; // @[Parameters.scala:1138:31]
wire _source_ok_T_47 = io_in_a_bits_source_0 == 8'h80; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_17 = _source_ok_T_47; // @[Parameters.scala:1138:31]
wire _source_ok_T_48 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_49 = _source_ok_T_48 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_50 = _source_ok_T_49 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_51 = _source_ok_T_50 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_52 = _source_ok_T_51 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_53 = _source_ok_T_52 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_54 = _source_ok_T_53 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_55 = _source_ok_T_54 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_56 = _source_ok_T_55 | _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_57 = _source_ok_T_56 | _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_58 = _source_ok_T_57 | _source_ok_WIRE_11; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_59 = _source_ok_T_58 | _source_ok_WIRE_12; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_60 = _source_ok_T_59 | _source_ok_WIRE_13; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_61 = _source_ok_T_60 | _source_ok_WIRE_14; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_62 = _source_ok_T_61 | _source_ok_WIRE_15; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_63 = _source_ok_T_62 | _source_ok_WIRE_16; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_63 | _source_ok_WIRE_17; // @[Parameters.scala:1138:31, :1139:46]
wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [28:0] _is_aligned_T = {17'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_4 = _uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_5 = _uncommonBits_T_5[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_10 = _uncommonBits_T_10[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_11 = _uncommonBits_T_11[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_16 = _uncommonBits_T_16[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_17 = _uncommonBits_T_17[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_22 = _uncommonBits_T_22[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_23 = _uncommonBits_T_23[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_28 = _uncommonBits_T_28[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_29 = _uncommonBits_T_29[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_34 = _uncommonBits_T_34[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_35 = _uncommonBits_T_35[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_40 = _uncommonBits_T_40[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_41 = _uncommonBits_T_41[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_46 = _uncommonBits_T_46[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_47 = _uncommonBits_T_47[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_52 = _uncommonBits_T_52[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_53 = _uncommonBits_T_53[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_54 = _uncommonBits_T_54[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_55 = _uncommonBits_T_55[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_58 = _uncommonBits_T_58[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_59 = _uncommonBits_T_59[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_60 = _uncommonBits_T_60[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_61 = _uncommonBits_T_61[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_62 = _uncommonBits_T_62[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_63 = _uncommonBits_T_63[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_64 = _uncommonBits_T_64[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_65 = _uncommonBits_T_65[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_64 = io_in_d_bits_source_0 == 8'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_64; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] _source_ok_T_65 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_71 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_77 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_83 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_66 = _source_ok_T_65 == 6'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_68 = _source_ok_T_66; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_70 = _source_ok_T_68; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_70; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_72 = _source_ok_T_71 == 6'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_74 = _source_ok_T_72; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_76 = _source_ok_T_74; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_76; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_78 = _source_ok_T_77 == 6'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_80 = _source_ok_T_78; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_82 = _source_ok_T_80; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_82; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_84 = _source_ok_T_83 == 6'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_86 = _source_ok_T_84; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_88 = _source_ok_T_86; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_88; // @[Parameters.scala:1138:31]
wire _source_ok_T_89 = io_in_d_bits_source_0 == 8'h44; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_5 = _source_ok_T_89; // @[Parameters.scala:1138:31]
wire _source_ok_T_90 = io_in_d_bits_source_0 == 8'h45; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_6 = _source_ok_T_90; // @[Parameters.scala:1138:31]
wire _source_ok_T_91 = io_in_d_bits_source_0 == 8'h46; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_7 = _source_ok_T_91; // @[Parameters.scala:1138:31]
wire _source_ok_T_92 = io_in_d_bits_source_0 == 8'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_8 = _source_ok_T_92; // @[Parameters.scala:1138:31]
wire _source_ok_T_93 = io_in_d_bits_source_0 == 8'h41; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_9 = _source_ok_T_93; // @[Parameters.scala:1138:31]
wire _source_ok_T_94 = io_in_d_bits_source_0 == 8'h42; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_10 = _source_ok_T_94; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[2:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_95 = io_in_d_bits_source_0[7:3]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_103 = io_in_d_bits_source_0[7:3]; // @[Monitor.scala:36:7]
wire _source_ok_T_96 = _source_ok_T_95 == 5'h6; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_98 = _source_ok_T_96; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_99 = source_ok_uncommonBits_10 < 3'h5; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_100 = _source_ok_T_98 & _source_ok_T_99; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_1_11 = _source_ok_T_100; // @[Parameters.scala:1138:31]
wire _source_ok_T_101 = io_in_d_bits_source_0 == 8'h35; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_12 = _source_ok_T_101; // @[Parameters.scala:1138:31]
wire _source_ok_T_102 = io_in_d_bits_source_0 == 8'h38; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_13 = _source_ok_T_102; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_104 = _source_ok_T_103 == 5'h4; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_106 = _source_ok_T_104; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_107 = source_ok_uncommonBits_11 < 3'h5; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_108 = _source_ok_T_106 & _source_ok_T_107; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_1_14 = _source_ok_T_108; // @[Parameters.scala:1138:31]
wire _source_ok_T_109 = io_in_d_bits_source_0 == 8'h25; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_15 = _source_ok_T_109; // @[Parameters.scala:1138:31]
wire _source_ok_T_110 = io_in_d_bits_source_0 == 8'h28; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_16 = _source_ok_T_110; // @[Parameters.scala:1138:31]
wire _source_ok_T_111 = io_in_d_bits_source_0 == 8'h80; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_17 = _source_ok_T_111; // @[Parameters.scala:1138:31]
wire _source_ok_T_112 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_113 = _source_ok_T_112 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_114 = _source_ok_T_113 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_115 = _source_ok_T_114 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_116 = _source_ok_T_115 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_117 = _source_ok_T_116 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_118 = _source_ok_T_117 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_119 = _source_ok_T_118 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_120 = _source_ok_T_119 | _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_121 = _source_ok_T_120 | _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_122 = _source_ok_T_121 | _source_ok_WIRE_1_11; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_123 = _source_ok_T_122 | _source_ok_WIRE_1_12; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_124 = _source_ok_T_123 | _source_ok_WIRE_1_13; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_125 = _source_ok_T_124 | _source_ok_WIRE_1_14; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_126 = _source_ok_T_125 | _source_ok_WIRE_1_15; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_127 = _source_ok_T_126 | _source_ok_WIRE_1_16; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_127 | _source_ok_WIRE_1_17; // @[Parameters.scala:1138:31, :1139:46]
wire _T_1950 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1950; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1950; // @[Decoupled.scala:51:35]
wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg [7:0] source; // @[Monitor.scala:390:22]
reg [28:0] address; // @[Monitor.scala:391:22]
wire _T_2023 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_2023; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_2023; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_2023; // @[Decoupled.scala:51:35]
wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg [7:0] source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [128:0] inflight; // @[Monitor.scala:614:27]
reg [515:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [1031:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [128:0] a_set; // @[Monitor.scala:626:34]
wire [128:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [515:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [1031:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [10:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [10:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [10:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [10:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [10:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [515:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [515:0] _a_opcode_lookup_T_6 = {512'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [515:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[515:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [7:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [10:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65]
wire [10:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65]
wire [10:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99]
wire [10:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67]
wire [10:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99]
wire [1031:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [1031:0] _a_size_lookup_T_6 = {1024'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}]
wire [1031:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[1031:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [255:0] _GEN_3 = 256'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [255:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35]
wire [255:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire _T_1876 = _T_1950 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1876 ? _a_set_T[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1876 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1876 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [10:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [2050:0] _a_opcodes_set_T_1 = {2047'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1876 ? _a_opcodes_set_T_1[515:0] : 516'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [10:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77]
wire [2051:0] _a_sizes_set_T_1 = {2047'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1876 ? _a_sizes_set_T_1[1031:0] : 1032'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [128:0] d_clr; // @[Monitor.scala:664:34]
wire [128:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [515:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [1031:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_1922 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [255:0] _GEN_5 = 256'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1922 & ~d_release_ack ? _d_clr_wo_ready_T[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire _T_1891 = _T_2023 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1891 ? _d_clr_T[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire [2062:0] _d_opcodes_clr_T_5 = 2063'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1891 ? _d_opcodes_clr_T_5[515:0] : 516'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [2062:0] _d_sizes_clr_T_5 = 2063'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1891 ? _d_sizes_clr_T_5[1031:0] : 1032'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [128:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [128:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [128:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [515:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [515:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [515:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [1031:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [1031:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [1031:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [128:0] inflight_1; // @[Monitor.scala:726:35]
wire [128:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [515:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [515:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [1031:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [1031:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [7:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [515:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [515:0] _c_opcode_lookup_T_6 = {512'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [515:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[515:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [1031:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [1031:0] _c_size_lookup_T_6 = {1024'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}]
wire [1031:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[1031:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [128:0] d_clr_1; // @[Monitor.scala:774:34]
wire [128:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [515:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [1031:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1994 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1994 & d_release_ack_1 ? _d_clr_wo_ready_T_1[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire _T_1976 = _T_2023 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1976 ? _d_clr_T_1[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire [2062:0] _d_opcodes_clr_T_11 = 2063'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1976 ? _d_opcodes_clr_T_11[515:0] : 516'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [2062:0] _d_sizes_clr_T_11 = 2063'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1976 ? _d_sizes_clr_T_11[1031:0] : 1032'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 8'h0; // @[Monitor.scala:36:7, :795:113]
wire [128:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [128:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [515:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [515:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [1031:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [1031:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to the following Chisel files.
File TilelinkAdapters.scala:
package constellation.protocol
import chisel3._
import chisel3.util._
import constellation.channel._
import constellation.noc._
import constellation.soc.{CanAttachToGlobalNoC}
import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.util._
import freechips.rocketchip.tilelink._
import scala.collection.immutable.{ListMap}
abstract class TLChannelToNoC[T <: TLChannel](gen: => T, edge: TLEdge, idToEgress: Int => Int)(implicit val p: Parameters) extends Module with TLFieldHelper {
val flitWidth = minTLPayloadWidth(gen)
val io = IO(new Bundle {
val protocol = Flipped(Decoupled(gen))
val flit = Decoupled(new IngressFlit(flitWidth))
})
def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B
// convert decoupled to irrevocable
val q = Module(new Queue(gen, 1, pipe=true, flow=true))
val protocol = q.io.deq
val has_body = Wire(Bool())
val body_fields = getBodyFields(protocol.bits)
val const_fields = getConstFields(protocol.bits)
val head = edge.first(protocol.bits, protocol.fire)
val tail = edge.last(protocol.bits, protocol.fire)
def requestOH: Seq[Bool]
val body = Cat( body_fields.filter(_.getWidth > 0).map(_.asUInt))
val const = Cat(const_fields.filter(_.getWidth > 0).map(_.asUInt))
val is_body = RegInit(false.B)
io.flit.valid := protocol.valid
protocol.ready := io.flit.ready && (is_body || !has_body)
io.flit.bits.head := head && !is_body
io.flit.bits.tail := tail && (is_body || !has_body)
io.flit.bits.egress_id := Mux1H(requestOH.zipWithIndex.map { case (r, i) =>
r -> idToEgress(i).U
})
io.flit.bits.payload := Mux(is_body, body, const)
when (io.flit.fire && io.flit.bits.head) { is_body := true.B }
when (io.flit.fire && io.flit.bits.tail) { is_body := false.B }
}
abstract class TLChannelFromNoC[T <: TLChannel](gen: => T)(implicit val p: Parameters) extends Module with TLFieldHelper {
val flitWidth = minTLPayloadWidth(gen)
val io = IO(new Bundle {
val protocol = Decoupled(gen)
val flit = Flipped(Decoupled(new EgressFlit(flitWidth)))
})
// Handle size = 1 gracefully (Chisel3 empty range is broken)
def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0)
val protocol = Wire(Decoupled(gen))
val body_fields = getBodyFields(protocol.bits)
val const_fields = getConstFields(protocol.bits)
val is_const = RegInit(true.B)
val const_reg = Reg(UInt(const_fields.map(_.getWidth).sum.W))
val const = Mux(io.flit.bits.head, io.flit.bits.payload, const_reg)
io.flit.ready := (is_const && !io.flit.bits.tail) || protocol.ready
protocol.valid := (!is_const || io.flit.bits.tail) && io.flit.valid
def assign(i: UInt, sigs: Seq[Data]) = {
var t = i
for (s <- sigs.reverse) {
s := t.asTypeOf(s.cloneType)
t = t >> s.getWidth
}
}
assign(const, const_fields)
assign(io.flit.bits.payload, body_fields)
when (io.flit.fire && io.flit.bits.head) { is_const := false.B; const_reg := io.flit.bits.payload }
when (io.flit.fire && io.flit.bits.tail) { is_const := true.B }
}
trait HasAddressDecoder {
// Filter a list to only those elements selected
def filter[T](data: Seq[T], mask: Seq[Boolean]) = (data zip mask).filter(_._2).map(_._1)
val edgeIn: TLEdge
val edgesOut: Seq[TLEdge]
lazy val reacheableIO = edgesOut.map { mp =>
edgeIn.client.clients.exists { c => mp.manager.managers.exists { m =>
c.visibility.exists { ca => m.address.exists { ma =>
ca.overlaps(ma)
}}
}}
}.toVector
lazy val releaseIO = (edgesOut zip reacheableIO).map { case (mp, reachable) =>
reachable && edgeIn.client.anySupportProbe && mp.manager.anySupportAcquireB
}.toVector
def outputPortFn(connectIO: Seq[Boolean]) = {
val port_addrs = edgesOut.map(_.manager.managers.flatMap(_.address))
val routingMask = AddressDecoder(filter(port_addrs, connectIO))
val route_addrs = port_addrs.map(seq => AddressSet.unify(seq.map(_.widen(~routingMask)).distinct))
route_addrs.map(seq => (addr: UInt) => seq.map(_.contains(addr)).reduce(_||_))
}
}
class TLAToNoC(
val edgeIn: TLEdge,
val edgesOut: Seq[TLEdge],
bundle: TLBundleParameters,
slaveToAEgress: Int => Int,
sourceStart: Int
)(implicit p: Parameters) extends TLChannelToNoC(new TLBundleA(bundle), edgeIn, slaveToAEgress)(p) with HasAddressDecoder {
has_body := edgeIn.hasData(protocol.bits) || (~protocol.bits.mask =/= 0.U)
lazy val connectAIO = reacheableIO
lazy val requestOH = outputPortFn(connectAIO).zipWithIndex.map { case (o, j) =>
connectAIO(j).B && (unique(connectAIO) || o(protocol.bits.address))
}
q.io.enq <> io.protocol
q.io.enq.bits.source := io.protocol.bits.source | sourceStart.U
}
class TLAFromNoC(edgeOut: TLEdge, bundle: TLBundleParameters)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleA(bundle))(p) {
io.protocol <> protocol
when (io.flit.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) }
}
class TLBToNoC(
edgeOut: TLEdge,
edgesIn: Seq[TLEdge],
bundle: TLBundleParameters,
masterToBIngress: Int => Int
)(implicit p: Parameters) extends TLChannelToNoC(new TLBundleB(bundle), edgeOut, masterToBIngress)(p) {
has_body := edgeOut.hasData(protocol.bits) || (~protocol.bits.mask =/= 0.U)
lazy val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client))
lazy val requestOH = inputIdRanges.map { i => i.contains(protocol.bits.source) }
q.io.enq <> io.protocol
}
class TLBFromNoC(edgeIn: TLEdge, bundle: TLBundleParameters, sourceSize: Int)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleB(bundle))(p) {
io.protocol <> protocol
io.protocol.bits.source := trim(protocol.bits.source, sourceSize)
when (io.flit.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) }
}
class TLCToNoC(
val edgeIn: TLEdge,
val edgesOut: Seq[TLEdge],
bundle: TLBundleParameters,
slaveToCEgress: Int => Int,
sourceStart: Int
)(implicit p: Parameters) extends TLChannelToNoC(new TLBundleC(bundle), edgeIn, slaveToCEgress)(p) with HasAddressDecoder {
has_body := edgeIn.hasData(protocol.bits)
lazy val connectCIO = releaseIO
lazy val requestOH = outputPortFn(connectCIO).zipWithIndex.map {
case (o, j) => connectCIO(j).B && (unique(connectCIO) || o(protocol.bits.address))
}
q.io.enq <> io.protocol
q.io.enq.bits.source := io.protocol.bits.source | sourceStart.U
}
class TLCFromNoC(edgeOut: TLEdge, bundle: TLBundleParameters)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleC(bundle))(p) {
io.protocol <> protocol
}
class TLDToNoC(
edgeOut: TLEdge,
edgesIn: Seq[TLEdge],
bundle: TLBundleParameters,
masterToDIngress: Int => Int,
sourceStart: Int
)(implicit p: Parameters) extends TLChannelToNoC(new TLBundleD(bundle), edgeOut, masterToDIngress)(p) {
has_body := edgeOut.hasData(protocol.bits)
lazy val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client))
lazy val requestOH = inputIdRanges.map { i => i.contains(protocol.bits.source) }
q.io.enq <> io.protocol
q.io.enq.bits.sink := io.protocol.bits.sink | sourceStart.U
}
class TLDFromNoC(edgeIn: TLEdge, bundle: TLBundleParameters, sourceSize: Int)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleD(bundle))(p)
{
io.protocol <> protocol
io.protocol.bits.source := trim(protocol.bits.source, sourceSize)
}
class TLEToNoC(
val edgeIn: TLEdge,
val edgesOut: Seq[TLEdge],
bundle: TLBundleParameters,
slaveToEEgress: Int => Int
)(implicit p: Parameters) extends TLChannelToNoC(new TLBundleE(bundle), edgeIn, slaveToEEgress)(p) {
has_body := edgeIn.hasData(protocol.bits)
lazy val outputIdRanges = TLXbar.mapOutputIds(edgesOut.map(_.manager))
lazy val requestOH = outputIdRanges.map { o => o.contains(protocol.bits.sink) }
q.io.enq <> io.protocol
}
class TLEFromNoC(edgeOut: TLEdge, bundle: TLBundleParameters, sourceSize: Int)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleE(bundle))(p) {
io.protocol <> protocol
io.protocol.bits.sink := trim(protocol.bits.sink, sourceSize)
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLAToNoC_9( // @[TilelinkAdapters.scala:112:7]
input clock, // @[TilelinkAdapters.scala:112:7]
input reset, // @[TilelinkAdapters.scala:112:7]
output io_protocol_ready, // @[TilelinkAdapters.scala:19:14]
input io_protocol_valid, // @[TilelinkAdapters.scala:19:14]
input [2:0] io_protocol_bits_opcode, // @[TilelinkAdapters.scala:19:14]
input [2:0] io_protocol_bits_param, // @[TilelinkAdapters.scala:19:14]
input [3:0] io_protocol_bits_size, // @[TilelinkAdapters.scala:19:14]
input [5:0] io_protocol_bits_source, // @[TilelinkAdapters.scala:19:14]
input [31:0] io_protocol_bits_address, // @[TilelinkAdapters.scala:19:14]
input [7:0] io_protocol_bits_mask, // @[TilelinkAdapters.scala:19:14]
input [63:0] io_protocol_bits_data, // @[TilelinkAdapters.scala:19:14]
input io_protocol_bits_corrupt, // @[TilelinkAdapters.scala:19:14]
input io_flit_ready, // @[TilelinkAdapters.scala:19:14]
output io_flit_valid, // @[TilelinkAdapters.scala:19:14]
output io_flit_bits_head, // @[TilelinkAdapters.scala:19:14]
output io_flit_bits_tail, // @[TilelinkAdapters.scala:19:14]
output [72:0] io_flit_bits_payload, // @[TilelinkAdapters.scala:19:14]
output [5:0] io_flit_bits_egress_id // @[TilelinkAdapters.scala:19:14]
);
wire [8:0] _GEN; // @[TilelinkAdapters.scala:119:{45,69}]
wire _q_io_deq_valid; // @[TilelinkAdapters.scala:26:17]
wire [2:0] _q_io_deq_bits_opcode; // @[TilelinkAdapters.scala:26:17]
wire [2:0] _q_io_deq_bits_param; // @[TilelinkAdapters.scala:26:17]
wire [3:0] _q_io_deq_bits_size; // @[TilelinkAdapters.scala:26:17]
wire [5:0] _q_io_deq_bits_source; // @[TilelinkAdapters.scala:26:17]
wire [31:0] _q_io_deq_bits_address; // @[TilelinkAdapters.scala:26:17]
wire [7:0] _q_io_deq_bits_mask; // @[TilelinkAdapters.scala:26:17]
wire [63:0] _q_io_deq_bits_data; // @[TilelinkAdapters.scala:26:17]
wire _q_io_deq_bits_corrupt; // @[TilelinkAdapters.scala:26:17]
wire [26:0] _tail_beats1_decode_T = 27'hFFF << _q_io_deq_bits_size; // @[package.scala:243:71]
reg [8:0] head_counter; // @[Edges.scala:229:27]
wire head = head_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire [8:0] tail_beats1 = _q_io_deq_bits_opcode[2] ? 9'h0 : ~(_tail_beats1_decode_T[11:3]); // @[package.scala:243:{46,71,76}]
reg [8:0] tail_counter; // @[Edges.scala:229:27]
reg is_body; // @[TilelinkAdapters.scala:39:24]
wire _io_flit_bits_tail_T = _GEN == 9'h0; // @[TilelinkAdapters.scala:119:{45,69}]
wire q_io_deq_ready = io_flit_ready & (is_body | _io_flit_bits_tail_T); // @[TilelinkAdapters.scala:39:24, :41:{35,47}, :119:{45,69}]
wire io_flit_bits_head_0 = head & ~is_body; // @[Edges.scala:231:25]
wire io_flit_bits_tail_0 = (tail_counter == 9'h1 | tail_beats1 == 9'h0) & (is_body | _io_flit_bits_tail_T); // @[Edges.scala:221:14, :229:27, :232:{25,33,43}]
wire [21:0] _GEN_0 = _q_io_deq_bits_address[27:6] ^ 22'h200001; // @[Parameters.scala:137:31]
wire [25:0] _io_flit_bits_egress_id_requestOH_T_35 = _q_io_deq_bits_address[31:6] ^ 26'h2000001; // @[Parameters.scala:137:31]
wire [21:0] _GEN_1 = _q_io_deq_bits_address[27:6] ^ 22'h200002; // @[Parameters.scala:137:31]
wire [25:0] _io_flit_bits_egress_id_requestOH_T_47 = _q_io_deq_bits_address[31:6] ^ 26'h2000002; // @[Parameters.scala:137:31]
wire [21:0] _GEN_2 = _q_io_deq_bits_address[27:6] ^ 22'h200003; // @[Parameters.scala:137:31]
wire [25:0] _io_flit_bits_egress_id_requestOH_T_59 = _q_io_deq_bits_address[31:6] ^ 26'h2000003; // @[Parameters.scala:137:31]
assign _GEN = {~(_q_io_deq_bits_opcode[2]), ~_q_io_deq_bits_mask}; // @[Edges.scala:92:{28,37}]
wire _GEN_3 = io_flit_ready & _q_io_deq_valid; // @[Decoupled.scala:51:35]
always @(posedge clock) begin // @[TilelinkAdapters.scala:112:7]
if (reset) begin // @[TilelinkAdapters.scala:112:7]
head_counter <= 9'h0; // @[Edges.scala:229:27]
tail_counter <= 9'h0; // @[Edges.scala:229:27]
is_body <= 1'h0; // @[TilelinkAdapters.scala:39:24, :112:7]
end
else begin // @[TilelinkAdapters.scala:112:7]
if (q_io_deq_ready & _q_io_deq_valid) begin // @[Decoupled.scala:51:35]
head_counter <= head ? (_q_io_deq_bits_opcode[2] ? 9'h0 : ~(_tail_beats1_decode_T[11:3])) : head_counter - 9'h1; // @[package.scala:243:{46,71,76}]
tail_counter <= tail_counter == 9'h0 ? tail_beats1 : tail_counter - 9'h1; // @[Edges.scala:221:14, :229:27, :230:28, :231:25, :236:21]
end
is_body <= ~(_GEN_3 & io_flit_bits_tail_0) & (_GEN_3 & io_flit_bits_head_0 | is_body); // @[Decoupled.scala:51:35]
end
always @(posedge) |
Generate the Verilog code corresponding to the following Chisel files.
File Tile.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
import Util._
/**
* A Tile is a purely combinational 2D array of passThrough PEs.
* a, b, s, and in_propag are broadcast across the entire array and are passed through to the Tile's outputs
* @param width The data width of each PE in bits
* @param rows Number of PEs on each row
* @param columns Number of PEs on each column
*/
class Tile[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, tree_reduction: Boolean, max_simultaneous_matmuls: Int, val rows: Int, val columns: Int)(implicit ev: Arithmetic[T]) extends Module {
val io = IO(new Bundle {
val in_a = Input(Vec(rows, inputType))
val in_b = Input(Vec(columns, outputType)) // This is the output of the tile next to it
val in_d = Input(Vec(columns, outputType))
val in_control = Input(Vec(columns, new PEControl(accType)))
val in_id = Input(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W)))
val in_last = Input(Vec(columns, Bool()))
val out_a = Output(Vec(rows, inputType))
val out_c = Output(Vec(columns, outputType))
val out_b = Output(Vec(columns, outputType))
val out_control = Output(Vec(columns, new PEControl(accType)))
val out_id = Output(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W)))
val out_last = Output(Vec(columns, Bool()))
val in_valid = Input(Vec(columns, Bool()))
val out_valid = Output(Vec(columns, Bool()))
val bad_dataflow = Output(Bool())
})
import ev._
val tile = Seq.fill(rows, columns)(Module(new PE(inputType, outputType, accType, df, max_simultaneous_matmuls)))
val tileT = tile.transpose
// TODO: abstract hori/vert broadcast, all these connections look the same
// Broadcast 'a' horizontally across the Tile
for (r <- 0 until rows) {
tile(r).foldLeft(io.in_a(r)) {
case (in_a, pe) =>
pe.io.in_a := in_a
pe.io.out_a
}
}
// Broadcast 'b' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_b(c)) {
case (in_b, pe) =>
pe.io.in_b := (if (tree_reduction) in_b.zero else in_b)
pe.io.out_b
}
}
// Broadcast 'd' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_d(c)) {
case (in_d, pe) =>
pe.io.in_d := in_d
pe.io.out_c
}
}
// Broadcast 'control' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_control(c)) {
case (in_ctrl, pe) =>
pe.io.in_control := in_ctrl
pe.io.out_control
}
}
// Broadcast 'garbage' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_valid(c)) {
case (v, pe) =>
pe.io.in_valid := v
pe.io.out_valid
}
}
// Broadcast 'id' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_id(c)) {
case (id, pe) =>
pe.io.in_id := id
pe.io.out_id
}
}
// Broadcast 'last' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_last(c)) {
case (last, pe) =>
pe.io.in_last := last
pe.io.out_last
}
}
// Drive the Tile's bottom IO
for (c <- 0 until columns) {
io.out_c(c) := tile(rows-1)(c).io.out_c
io.out_control(c) := tile(rows-1)(c).io.out_control
io.out_id(c) := tile(rows-1)(c).io.out_id
io.out_last(c) := tile(rows-1)(c).io.out_last
io.out_valid(c) := tile(rows-1)(c).io.out_valid
io.out_b(c) := {
if (tree_reduction) {
val prods = tileT(c).map(_.io.out_b)
accumulateTree(prods :+ io.in_b(c))
} else {
tile(rows - 1)(c).io.out_b
}
}
}
io.bad_dataflow := tile.map(_.map(_.io.bad_dataflow).reduce(_||_)).reduce(_||_)
// Drive the Tile's right IO
for (r <- 0 until rows) {
io.out_a(r) := tile(r)(columns-1).io.out_a
}
}
| module Tile_150( // @[Tile.scala:16:7]
input clock, // @[Tile.scala:16:7]
input reset, // @[Tile.scala:16:7]
input [7:0] io_in_a_0, // @[Tile.scala:17:14]
input [19:0] io_in_b_0, // @[Tile.scala:17:14]
input [19:0] io_in_d_0, // @[Tile.scala:17:14]
input io_in_control_0_dataflow, // @[Tile.scala:17:14]
input io_in_control_0_propagate, // @[Tile.scala:17:14]
input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14]
input [2:0] io_in_id_0, // @[Tile.scala:17:14]
input io_in_last_0, // @[Tile.scala:17:14]
output [7:0] io_out_a_0, // @[Tile.scala:17:14]
output [19:0] io_out_c_0, // @[Tile.scala:17:14]
output [19:0] io_out_b_0, // @[Tile.scala:17:14]
output io_out_control_0_dataflow, // @[Tile.scala:17:14]
output io_out_control_0_propagate, // @[Tile.scala:17:14]
output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14]
output [2:0] io_out_id_0, // @[Tile.scala:17:14]
output io_out_last_0, // @[Tile.scala:17:14]
input io_in_valid_0, // @[Tile.scala:17:14]
output io_out_valid_0 // @[Tile.scala:17:14]
);
wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7]
wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7]
wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7]
wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7]
wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7]
wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7]
wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7]
wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7]
wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7]
wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44]
wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7]
wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
wire io_out_control_0_propagate_0; // @[Tile.scala:16:7]
wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7]
wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7]
wire io_out_last_0_0; // @[Tile.scala:16:7]
wire io_out_valid_0_0; // @[Tile.scala:16:7]
PE_406 tile_0_0 ( // @[Tile.scala:42:44]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0_0), // @[Tile.scala:16:7]
.io_in_b (io_in_b_0_0), // @[Tile.scala:16:7]
.io_in_d (io_in_d_0_0), // @[Tile.scala:16:7]
.io_out_a (io_out_a_0_0),
.io_out_b (io_out_b_0_0),
.io_out_c (io_out_c_0_0),
.io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7]
.io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7]
.io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7]
.io_out_control_dataflow (io_out_control_0_dataflow_0),
.io_out_control_propagate (io_out_control_0_propagate_0),
.io_out_control_shift (io_out_control_0_shift_0),
.io_in_id (io_in_id_0_0), // @[Tile.scala:16:7]
.io_out_id (io_out_id_0_0),
.io_in_last (io_in_last_0_0), // @[Tile.scala:16:7]
.io_out_last (io_out_last_0_0),
.io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7]
.io_out_valid (io_out_valid_0_0)
); // @[Tile.scala:42:44]
assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7]
assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7]
assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7]
assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7]
assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7]
assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7]
assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7]
assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File primitives.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object lowMask
{
def apply(in: UInt, topBound: BigInt, bottomBound: BigInt): UInt =
{
require(topBound != bottomBound)
val numInVals = BigInt(1)<<in.getWidth
if (topBound < bottomBound) {
lowMask(~in, numInVals - 1 - topBound, numInVals - 1 - bottomBound)
} else if (numInVals > 64 /* Empirical */) {
// For simulation performance, we should avoid generating
// exteremely wide shifters, so we divide and conquer.
// Empirically, this does not impact synthesis QoR.
val mid = numInVals / 2
val msb = in(in.getWidth - 1)
val lsbs = in(in.getWidth - 2, 0)
if (mid < topBound) {
if (mid <= bottomBound) {
Mux(msb,
lowMask(lsbs, topBound - mid, bottomBound - mid),
0.U
)
} else {
Mux(msb,
lowMask(lsbs, topBound - mid, 0) ## ((BigInt(1)<<(mid - bottomBound).toInt) - 1).U,
lowMask(lsbs, mid, bottomBound)
)
}
} else {
~Mux(msb, 0.U, ~lowMask(lsbs, topBound, bottomBound))
}
} else {
val shift = (BigInt(-1)<<numInVals.toInt).S>>in
Reverse(
shift(
(numInVals - 1 - bottomBound).toInt,
(numInVals - topBound).toInt
)
)
}
}
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object countLeadingZeros
{
def apply(in: UInt): UInt = PriorityEncoder(in.asBools.reverse)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object orReduceBy2
{
def apply(in: UInt): UInt =
{
val reducedWidth = (in.getWidth + 1)>>1
val reducedVec = Wire(Vec(reducedWidth, Bool()))
for (ix <- 0 until reducedWidth - 1) {
reducedVec(ix) := in(ix * 2 + 1, ix * 2).orR
}
reducedVec(reducedWidth - 1) :=
in(in.getWidth - 1, (reducedWidth - 1) * 2).orR
reducedVec.asUInt
}
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object orReduceBy4
{
def apply(in: UInt): UInt =
{
val reducedWidth = (in.getWidth + 3)>>2
val reducedVec = Wire(Vec(reducedWidth, Bool()))
for (ix <- 0 until reducedWidth - 1) {
reducedVec(ix) := in(ix * 4 + 3, ix * 4).orR
}
reducedVec(reducedWidth - 1) :=
in(in.getWidth - 1, (reducedWidth - 1) * 4).orR
reducedVec.asUInt
}
}
File RoundAnyRawFNToRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util.Fill
import consts._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class
RoundAnyRawFNToRecFN(
inExpWidth: Int,
inSigWidth: Int,
outExpWidth: Int,
outSigWidth: Int,
options: Int
)
extends RawModule
{
override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}"
val io = IO(new Bundle {
val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'
val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'
val in = Input(new RawFloat(inExpWidth, inSigWidth))
// (allowed exponent range has limits)
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((outExpWidth + outSigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0)
val effectiveInSigWidth =
if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1
val neverUnderflows =
((options &
(flRoundOpt_neverUnderflows | flRoundOpt_subnormsAlwaysExact)
) != 0) ||
(inExpWidth < outExpWidth)
val neverOverflows =
((options & flRoundOpt_neverOverflows) != 0) ||
(inExpWidth < outExpWidth)
val outNaNExp = BigInt(7)<<(outExpWidth - 2)
val outInfExp = BigInt(6)<<(outExpWidth - 2)
val outMaxFiniteExp = outInfExp - 1
val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2
val outMinNonzeroExp = outMinNormExp - outSigWidth + 1
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundingMode_near_even = (io.roundingMode === round_near_even)
val roundingMode_minMag = (io.roundingMode === round_minMag)
val roundingMode_min = (io.roundingMode === round_min)
val roundingMode_max = (io.roundingMode === round_max)
val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag)
val roundingMode_odd = (io.roundingMode === round_odd)
val roundMagUp =
(roundingMode_min && io.in.sign) || (roundingMode_max && ! io.in.sign)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sAdjustedExp =
if (inExpWidth < outExpWidth)
(io.in.sExp +&
((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S
)(outExpWidth, 0).zext
else if (inExpWidth == outExpWidth)
io.in.sExp
else
io.in.sExp +&
((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S
val adjustedSig =
if (inSigWidth <= outSigWidth + 2)
io.in.sig<<(outSigWidth - inSigWidth + 2)
else
(io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ##
io.in.sig(inSigWidth - outSigWidth - 2, 0).orR
)
val doShiftSigDown1 =
if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2)
val common_expOut = Wire(UInt((outExpWidth + 1).W))
val common_fractOut = Wire(UInt((outSigWidth - 1).W))
val common_overflow = Wire(Bool())
val common_totalUnderflow = Wire(Bool())
val common_underflow = Wire(Bool())
val common_inexact = Wire(Bool())
if (
neverOverflows && neverUnderflows
&& (effectiveInSigWidth <= outSigWidth)
) {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1
common_fractOut :=
Mux(doShiftSigDown1,
adjustedSig(outSigWidth + 1, 3),
adjustedSig(outSigWidth, 2)
)
common_overflow := false.B
common_totalUnderflow := false.B
common_underflow := false.B
common_inexact := false.B
} else {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
val roundMask =
if (neverUnderflows)
0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W)
else
(lowMask(
sAdjustedExp(outExpWidth, 0),
outMinNormExp - outSigWidth - 1,
outMinNormExp
) | doShiftSigDown1) ##
3.U(2.W)
val shiftedRoundMask = 0.U(1.W) ## roundMask>>1
val roundPosMask = ~shiftedRoundMask & roundMask
val roundPosBit = (adjustedSig & roundPosMask).orR
val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR
val anyRound = roundPosBit || anyRoundExtra
val roundIncr =
((roundingMode_near_even || roundingMode_near_maxMag) &&
roundPosBit) ||
(roundMagUp && anyRound)
val roundedSig: Bits =
Mux(roundIncr,
(((adjustedSig | roundMask)>>2) +& 1.U) &
~Mux(roundingMode_near_even && roundPosBit &&
! anyRoundExtra,
roundMask>>1,
0.U((outSigWidth + 2).W)
),
(adjustedSig & ~roundMask)>>2 |
Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U)
)
//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING
//*** M.S. BIT OF SUBNORMAL SIG?
val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext
common_expOut := sRoundedExp(outExpWidth, 0)
common_fractOut :=
Mux(doShiftSigDown1,
roundedSig(outSigWidth - 1, 1),
roundedSig(outSigWidth - 2, 0)
)
common_overflow :=
(if (neverOverflows) false.B else
//*** REWRITE BASED ON BEFORE-ROUNDING EXPONENT?:
(sRoundedExp>>(outExpWidth - 1) >= 3.S))
common_totalUnderflow :=
(if (neverUnderflows) false.B else
//*** WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?:
(sRoundedExp < outMinNonzeroExp.S))
val unboundedRange_roundPosBit =
Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1))
val unboundedRange_anyRound =
(doShiftSigDown1 && adjustedSig(2)) || adjustedSig(1, 0).orR
val unboundedRange_roundIncr =
((roundingMode_near_even || roundingMode_near_maxMag) &&
unboundedRange_roundPosBit) ||
(roundMagUp && unboundedRange_anyRound)
val roundCarry =
Mux(doShiftSigDown1,
roundedSig(outSigWidth + 1),
roundedSig(outSigWidth)
)
common_underflow :=
(if (neverUnderflows) false.B else
common_totalUnderflow ||
//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING
//*** M.S. BIT OF SUBNORMAL SIG?
(anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) &&
Mux(doShiftSigDown1, roundMask(3), roundMask(2)) &&
! ((io.detectTininess === tininess_afterRounding) &&
! Mux(doShiftSigDown1,
roundMask(4),
roundMask(3)
) &&
roundCarry && roundPosBit &&
unboundedRange_roundIncr)))
common_inexact := common_totalUnderflow || anyRound
}
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val isNaNOut = io.invalidExc || io.in.isNaN
val notNaN_isSpecialInfOut = io.infiniteExc || io.in.isInf
val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero
val overflow = commonCase && common_overflow
val underflow = commonCase && common_underflow
val inexact = overflow || (commonCase && common_inexact)
val overflow_roundMagUp =
roundingMode_near_even || roundingMode_near_maxMag || roundMagUp
val pegMinNonzeroMagOut =
commonCase && common_totalUnderflow && (roundMagUp || roundingMode_odd)
val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp
val notNaN_isInfOut =
notNaN_isSpecialInfOut || (overflow && overflow_roundMagUp)
val signOut = Mux(isNaNOut, false.B, io.in.sign)
val expOut =
(common_expOut &
~Mux(io.in.isZero || common_totalUnderflow,
(BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W),
0.U
) &
~Mux(pegMinNonzeroMagOut,
~outMinNonzeroExp.U((outExpWidth + 1).W),
0.U
) &
~Mux(pegMaxFiniteMagOut,
(BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W),
0.U
) &
~Mux(notNaN_isInfOut,
(BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W),
0.U
)) |
Mux(pegMinNonzeroMagOut,
outMinNonzeroExp.U((outExpWidth + 1).W),
0.U
) |
Mux(pegMaxFiniteMagOut,
outMaxFiniteExp.U((outExpWidth + 1).W),
0.U
) |
Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) |
Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U)
val fractOut =
Mux(isNaNOut || io.in.isZero || common_totalUnderflow,
Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U),
common_fractOut
) |
Fill(outSigWidth - 1, pegMaxFiniteMagOut)
io.out := signOut ## expOut ## fractOut
io.exceptionFlags :=
io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class
RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int)
extends RawModule
{
override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'
val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'
val in = Input(new RawFloat(expWidth, sigWidth + 2))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
val roundAnyRawFNToRecFN =
Module(
new RoundAnyRawFNToRecFN(
expWidth, sigWidth + 2, expWidth, sigWidth, options))
roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc
roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc
roundAnyRawFNToRecFN.io.in := io.in
roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode
roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundAnyRawFNToRecFN.io.out
io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags
}
| module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_47(); // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19]
wire [8:0] _roundMask_T = 9'hFF; // @[RoundAnyRawFNToRecFN.scala:156:37]
wire [6:0] roundMask_lsbs_1 = 7'h0; // @[primitives.scala:59:26]
wire [15:0] _roundMask_T_5 = 16'hFF; // @[primitives.scala:77:20]
wire [7:0] roundMask_lsbs = 8'h0; // @[primitives.scala:59:26, :77:20]
wire [7:0] _roundMask_T_6 = 8'h0; // @[primitives.scala:59:26, :77:20]
wire [7:0] _roundMask_T_8 = 8'h0; // @[primitives.scala:59:26, :77:20]
wire [15:0] _roundMask_T_4 = 16'hFF00; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_10 = 16'hFF00; // @[primitives.scala:77:20]
wire [11:0] _roundMask_T_13 = 12'hFF; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_14 = 16'hFF0; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_15 = 16'hF0F; // @[primitives.scala:77:20]
wire [11:0] _roundMask_T_16 = 12'h0; // @[primitives.scala:77:20]
wire [11:0] _roundMask_T_18 = 12'h0; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_20 = 16'hF0F0; // @[primitives.scala:77:20]
wire [13:0] _roundMask_T_23 = 14'hF0F; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_24 = 16'h3C3C; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_25 = 16'h3333; // @[primitives.scala:77:20]
wire [13:0] _roundMask_T_26 = 14'h0; // @[primitives.scala:77:20]
wire [13:0] _roundMask_T_28 = 14'h0; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_30 = 16'hCCCC; // @[primitives.scala:77:20]
wire [14:0] _roundMask_T_33 = 15'h3333; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_34 = 16'h6666; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_35 = 16'h5555; // @[primitives.scala:77:20]
wire [14:0] _roundMask_T_36 = 15'h0; // @[primitives.scala:77:20]
wire [14:0] _roundMask_T_38 = 15'h0; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_40 = 16'hAAAA; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_3 = 16'h0; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_7 = 16'h0; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_9 = 16'h0; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_11 = 16'h0; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_12 = 16'h0; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_17 = 16'h0; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_19 = 16'h0; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_21 = 16'h0; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_22 = 16'h0; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_27 = 16'h0; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_29 = 16'h0; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_31 = 16'h0; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_32 = 16'h0; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_37 = 16'h0; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_39 = 16'h0; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_41 = 16'h0; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_42 = 16'h0; // @[primitives.scala:77:20]
wire [21:0] _roundMask_T_60 = 22'h3FFFFF; // @[primitives.scala:73:{21,32}]
wire [21:0] _roundMask_T_61 = 22'h3FFFFF; // @[primitives.scala:73:{21,32}]
wire [21:0] _roundMask_T_2 = 22'h0; // @[primitives.scala:73:17, :77:20, :78:22]
wire [21:0] _roundMask_T_59 = 22'h0; // @[primitives.scala:73:17, :77:20, :78:22]
wire [21:0] _roundMask_T_62 = 22'h0; // @[primitives.scala:73:17, :77:20, :78:22]
wire [24:0] _roundMask_T_63 = 25'h7; // @[primitives.scala:68:58]
wire [5:0] roundMask_lsbs_2 = 6'h0; // @[primitives.scala:59:26, :77:20]
wire [5:0] _roundMask_T_43 = 6'h0; // @[primitives.scala:59:26, :77:20]
wire [5:0] _roundMask_T_58 = 6'h0; // @[primitives.scala:59:26, :77:20]
wire [5:0] roundMask_lsbs_3 = 6'h0; // @[primitives.scala:59:26, :77:20]
wire [64:0] roundMask_shift = 65'h10000000000000000; // @[primitives.scala:76:56]
wire [64:0] roundMask_shift_1 = 65'h10000000000000000; // @[primitives.scala:76:56]
wire [24:0] _roundMask_T_72 = 25'h0; // @[primitives.scala:62:24, :67:24]
wire [24:0] _roundMask_T_73 = 25'h0; // @[primitives.scala:62:24, :67:24]
wire [24:0] _roundMask_T_74 = 25'h1; // @[RoundAnyRawFNToRecFN.scala:159:23]
wire [26:0] roundMask = 27'h7; // @[RoundAnyRawFNToRecFN.scala:159:42]
wire [27:0] _shiftedRoundMask_T = 28'h7; // @[RoundAnyRawFNToRecFN.scala:162:41]
wire [26:0] shiftedRoundMask = 27'h3; // @[RoundAnyRawFNToRecFN.scala:162:53]
wire [26:0] _roundPosMask_T = 27'h7FFFFFC; // @[RoundAnyRawFNToRecFN.scala:163:28]
wire [26:0] roundPosMask = 27'h4; // @[RoundAnyRawFNToRecFN.scala:163:46]
wire [26:0] _roundPosBit_T = 27'h0; // @[RoundAnyRawFNToRecFN.scala:164:40, :165:42]
wire [26:0] _anyRoundExtra_T = 27'h0; // @[RoundAnyRawFNToRecFN.scala:164:40, :165:42]
wire [26:0] _roundedSig_T = 27'h4000007; // @[RoundAnyRawFNToRecFN.scala:174:32]
wire [24:0] _roundedSig_T_1 = 25'h1000001; // @[RoundAnyRawFNToRecFN.scala:174:44]
wire [25:0] _roundedSig_T_6 = 26'h3; // @[RoundAnyRawFNToRecFN.scala:177:35]
wire [25:0] _roundedSig_T_8 = 26'h3FFFFFF; // @[RoundAnyRawFNToRecFN.scala:175:21]
wire [25:0] _roundedSig_T_2 = 26'h1000002; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}]
wire [25:0] _roundedSig_T_9 = 26'h1000002; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}]
wire [26:0] _roundedSig_T_10 = 27'h7FFFFF8; // @[RoundAnyRawFNToRecFN.scala:180:32]
wire [24:0] _roundedSig_T_12 = 25'h1000000; // @[RoundAnyRawFNToRecFN.scala:180:43]
wire [25:0] _roundedSig_T_14 = 26'h2; // @[RoundAnyRawFNToRecFN.scala:181:67]
wire [25:0] _roundedSig_T_7 = 26'h0; // @[RoundAnyRawFNToRecFN.scala:175:25, :181:24]
wire [25:0] _roundedSig_T_15 = 26'h0; // @[RoundAnyRawFNToRecFN.scala:175:25, :181:24]
wire [25:0] _roundedSig_T_16 = 26'h1000000; // @[RoundAnyRawFNToRecFN.scala:173:16, :180:47]
wire [25:0] roundedSig = 26'h1000000; // @[RoundAnyRawFNToRecFN.scala:173:16, :180:47]
wire [1:0] _sRoundedExp_T = 2'h1; // @[RoundAnyRawFNToRecFN.scala:185:54]
wire [2:0] _sRoundedExp_T_1 = 3'h1; // @[RoundAnyRawFNToRecFN.scala:185:76]
wire [10:0] sRoundedExp = 11'h100; // @[RoundAnyRawFNToRecFN.scala:185:40]
wire [3:0] _common_overflow_T = 4'h2; // @[RoundAnyRawFNToRecFN.scala:196:30]
wire [8:0] _expOut_T_2 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14]
wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14]
wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14]
wire [8:0] _expOut_T_12 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14]
wire [8:0] _expOut_T_1 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _expOut_T_11 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _expOut_T_18 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _expOut_T_20 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] common_expOut = 9'h100; // @[primitives.scala:52:21]
wire [8:0] _roundMask_T_1 = 9'h100; // @[primitives.scala:52:21]
wire [8:0] _common_expOut_T = 9'h100; // @[primitives.scala:52:21]
wire [8:0] _expOut_T_3 = 9'h100; // @[primitives.scala:52:21]
wire [8:0] _expOut_T_7 = 9'h100; // @[primitives.scala:52:21]
wire [8:0] _expOut_T_10 = 9'h100; // @[primitives.scala:52:21]
wire [8:0] _expOut_T_13 = 9'h100; // @[primitives.scala:52:21]
wire [8:0] _expOut_T_15 = 9'h100; // @[primitives.scala:52:21]
wire [8:0] _expOut_T_17 = 9'h100; // @[primitives.scala:52:21]
wire [8:0] _expOut_T_19 = 9'h100; // @[primitives.scala:52:21]
wire [8:0] expOut = 9'h100; // @[primitives.scala:52:21]
wire [22:0] common_fractOut = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16, :190:27, :191:27, :280:12, :281:16, :283:11, :284:13]
wire [22:0] _common_fractOut_T = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16, :190:27, :191:27, :280:12, :281:16, :283:11, :284:13]
wire [22:0] _common_fractOut_T_1 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16, :190:27, :191:27, :280:12, :281:16, :283:11, :284:13]
wire [22:0] _common_fractOut_T_2 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16, :190:27, :191:27, :280:12, :281:16, :283:11, :284:13]
wire [22:0] _fractOut_T_2 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16, :190:27, :191:27, :280:12, :281:16, :283:11, :284:13]
wire [22:0] _fractOut_T_3 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16, :190:27, :191:27, :280:12, :281:16, :283:11, :284:13]
wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16, :190:27, :191:27, :280:12, :281:16, :283:11, :284:13]
wire [22:0] fractOut = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16, :190:27, :191:27, :280:12, :281:16, :283:11, :284:13]
wire [9:0] _io_out_T = 10'h300; // @[RoundAnyRawFNToRecFN.scala:286:23]
wire [1:0] _roundMask_T_45 = 2'h0; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_48 = 2'h0; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_49 = 2'h0; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_52 = 2'h0; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_54 = 2'h0; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_57 = 2'h0; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_65 = 2'h0; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_68 = 2'h0; // @[primitives.scala:77:20]
wire [1:0] _unboundedRange_anyRound_T_2 = 2'h0; // @[primitives.scala:77:20]
wire [1:0] _common_underflow_T = 2'h0; // @[primitives.scala:77:20]
wire [1:0] _io_exceptionFlags_T = 2'h0; // @[primitives.scala:77:20]
wire [3:0] _roundMask_T_44 = 4'h0; // @[primitives.scala:77:20]
wire [3:0] _roundMask_T_53 = 4'h0; // @[primitives.scala:77:20]
wire [3:0] _io_exceptionFlags_T_2 = 4'h0; // @[primitives.scala:77:20]
wire [4:0] io_exceptionFlags = 5'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:66]
wire [4:0] _io_exceptionFlags_T_3 = 5'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:66]
wire [32:0] io_out = 33'h180000000; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :286:33]
wire [32:0] _io_out_T_1 = 33'h180000000; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :286:33]
wire [2:0] io_roundingMode = 3'h0; // @[primitives.scala:62:24, :77:20, :78:22]
wire [2:0] _roundMask_T_64 = 3'h0; // @[primitives.scala:62:24, :77:20, :78:22]
wire [2:0] _roundMask_T_70 = 3'h0; // @[primitives.scala:62:24, :77:20, :78:22]
wire [2:0] _roundMask_T_71 = 3'h0; // @[primitives.scala:62:24, :77:20, :78:22]
wire [2:0] _io_exceptionFlags_T_1 = 3'h0; // @[primitives.scala:62:24, :77:20, :78:22]
wire [26:0] io_in_sig = 27'h4000000; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :114:22, :180:30]
wire [26:0] adjustedSig = 27'h4000000; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :114:22, :180:30]
wire [26:0] _roundedSig_T_11 = 27'h4000000; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :114:22, :180:30]
wire [9:0] io_in_sExp = 10'hFF; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16]
wire io_in_sign = 1'h1; // @[primitives.scala:58:25]
wire io_detectTininess = 1'h1; // @[primitives.scala:58:25]
wire roundingMode_near_even = 1'h1; // @[primitives.scala:58:25]
wire doShiftSigDown1 = 1'h1; // @[primitives.scala:58:25]
wire roundMask_msb = 1'h1; // @[primitives.scala:58:25]
wire _roundIncr_T = 1'h1; // @[primitives.scala:58:25]
wire _roundedSig_T_4 = 1'h1; // @[primitives.scala:58:25]
wire _unboundedRange_roundIncr_T = 1'h1; // @[primitives.scala:58:25]
wire _roundCarry_T_1 = 1'h1; // @[primitives.scala:58:25]
wire _common_underflow_T_1 = 1'h1; // @[primitives.scala:58:25]
wire _common_underflow_T_4 = 1'h1; // @[primitives.scala:58:25]
wire _common_underflow_T_7 = 1'h1; // @[primitives.scala:58:25]
wire _common_underflow_T_11 = 1'h1; // @[primitives.scala:58:25]
wire _common_underflow_T_12 = 1'h1; // @[primitives.scala:58:25]
wire _common_underflow_T_16 = 1'h1; // @[primitives.scala:58:25]
wire _commonCase_T = 1'h1; // @[primitives.scala:58:25]
wire _commonCase_T_1 = 1'h1; // @[primitives.scala:58:25]
wire _commonCase_T_2 = 1'h1; // @[primitives.scala:58:25]
wire _commonCase_T_3 = 1'h1; // @[primitives.scala:58:25]
wire commonCase = 1'h1; // @[primitives.scala:58:25]
wire _overflow_roundMagUp_T = 1'h1; // @[primitives.scala:58:25]
wire overflow_roundMagUp = 1'h1; // @[primitives.scala:58:25]
wire signOut = 1'h1; // @[primitives.scala:58:25]
wire io_invalidExc = 1'h0; // @[primitives.scala:58:25, :77:20]
wire io_infiniteExc = 1'h0; // @[primitives.scala:58:25, :77:20]
wire io_in_isNaN = 1'h0; // @[primitives.scala:58:25, :77:20]
wire io_in_isInf = 1'h0; // @[primitives.scala:58:25, :77:20]
wire io_in_isZero = 1'h0; // @[primitives.scala:58:25, :77:20]
wire roundingMode_minMag = 1'h0; // @[primitives.scala:58:25, :77:20]
wire roundingMode_min = 1'h0; // @[primitives.scala:58:25, :77:20]
wire roundingMode_max = 1'h0; // @[primitives.scala:58:25, :77:20]
wire roundingMode_near_maxMag = 1'h0; // @[primitives.scala:58:25, :77:20]
wire roundingMode_odd = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _roundMagUp_T = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _roundMagUp_T_1 = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _roundMagUp_T_2 = 1'h0; // @[primitives.scala:58:25, :77:20]
wire roundMagUp = 1'h0; // @[primitives.scala:58:25, :77:20]
wire common_overflow = 1'h0; // @[primitives.scala:58:25, :77:20]
wire common_totalUnderflow = 1'h0; // @[primitives.scala:58:25, :77:20]
wire common_underflow = 1'h0; // @[primitives.scala:58:25, :77:20]
wire common_inexact = 1'h0; // @[primitives.scala:58:25, :77:20]
wire roundMask_msb_1 = 1'h0; // @[primitives.scala:58:25, :77:20]
wire roundMask_msb_2 = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _roundMask_T_46 = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _roundMask_T_47 = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _roundMask_T_50 = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _roundMask_T_51 = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _roundMask_T_55 = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _roundMask_T_56 = 1'h0; // @[primitives.scala:58:25, :77:20]
wire roundMask_msb_3 = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _roundMask_T_66 = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _roundMask_T_67 = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _roundMask_T_69 = 1'h0; // @[primitives.scala:58:25, :77:20]
wire roundPosBit = 1'h0; // @[primitives.scala:58:25, :77:20]
wire anyRoundExtra = 1'h0; // @[primitives.scala:58:25, :77:20]
wire anyRound = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _roundIncr_T_1 = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _roundIncr_T_2 = 1'h0; // @[primitives.scala:58:25, :77:20]
wire roundIncr = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _roundedSig_T_3 = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _roundedSig_T_5 = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _roundedSig_T_13 = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _common_overflow_T_1 = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _common_totalUnderflow_T = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _unboundedRange_roundPosBit_T = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _unboundedRange_roundPosBit_T_1 = 1'h0; // @[primitives.scala:58:25, :77:20]
wire unboundedRange_roundPosBit = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _unboundedRange_anyRound_T = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _unboundedRange_anyRound_T_1 = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _unboundedRange_anyRound_T_3 = 1'h0; // @[primitives.scala:58:25, :77:20]
wire unboundedRange_anyRound = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _unboundedRange_roundIncr_T_1 = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _unboundedRange_roundIncr_T_2 = 1'h0; // @[primitives.scala:58:25, :77:20]
wire unboundedRange_roundIncr = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _roundCarry_T = 1'h0; // @[primitives.scala:58:25, :77:20]
wire roundCarry = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _common_underflow_T_2 = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _common_underflow_T_3 = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _common_underflow_T_5 = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _common_underflow_T_6 = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _common_underflow_T_8 = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _common_underflow_T_9 = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _common_underflow_T_10 = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _common_underflow_T_13 = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _common_underflow_T_14 = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _common_underflow_T_15 = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _common_underflow_T_17 = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _common_underflow_T_18 = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _common_inexact_T = 1'h0; // @[primitives.scala:58:25, :77:20]
wire isNaNOut = 1'h0; // @[primitives.scala:58:25, :77:20]
wire notNaN_isSpecialInfOut = 1'h0; // @[primitives.scala:58:25, :77:20]
wire overflow = 1'h0; // @[primitives.scala:58:25, :77:20]
wire underflow = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _inexact_T = 1'h0; // @[primitives.scala:58:25, :77:20]
wire inexact = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _pegMinNonzeroMagOut_T = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[primitives.scala:58:25, :77:20]
wire pegMinNonzeroMagOut = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _pegMaxFiniteMagOut_T = 1'h0; // @[primitives.scala:58:25, :77:20]
wire pegMaxFiniteMagOut = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _notNaN_isInfOut_T = 1'h0; // @[primitives.scala:58:25, :77:20]
wire notNaN_isInfOut = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _expOut_T = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _fractOut_T = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _fractOut_T_1 = 1'h0; // @[primitives.scala:58:25, :77:20]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor_98( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_d_bits_source // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71]
wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [6:0] source; // @[Monitor.scala:390:22]
reg [20:0] address; // @[Monitor.scala:391:22]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [6:0] source_1; // @[Monitor.scala:541:22]
reg [64:0] inflight; // @[Monitor.scala:614:27]
reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [259:0] inflight_sizes; // @[Monitor.scala:618:33]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _GEN_0 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35]
wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46]
wire _GEN_1 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [64:0] inflight_1; // @[Monitor.scala:726:35]
reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to the following Chisel files.
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Nodes.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection}
case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args))
object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
{
def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo)
def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo)
def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle)
def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle)
def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString)
override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = {
val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge)))
monitor.io.in := bundle
}
override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters =
pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })
override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters =
pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })
}
trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut]
case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode
case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode
case class TLAdapterNode(
clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s },
managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLJunctionNode(
clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters],
managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])(
implicit valName: ValName)
extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode
object TLNameNode {
def apply(name: ValName) = TLIdentityNode()(name)
def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLIdentityNode = apply(Some(name))
}
case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)()
object TLTempNode {
def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp"))
}
case class TLNexusNode(
clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters,
managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)(
implicit valName: ValName)
extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode
abstract class TLCustomNode(implicit valName: ValName)
extends CustomNode(TLImp) with TLFormatNode
// Asynchronous crossings
trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters]
object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle]
{
def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle)
def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString)
override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLAsyncAdapterNode(
clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s },
managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode
case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode
object TLAsyncNameNode {
def apply(name: ValName) = TLAsyncIdentityNode()(name)
def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLAsyncIdentityNode = apply(Some(name))
}
case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLAsyncImp)(
dFn = { p => TLAsyncClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain
case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName)
extends MixedAdapterNode(TLAsyncImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) },
uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut]
// Rationally related crossings
trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters]
object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle]
{
def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle)
def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */)
override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLRationalAdapterNode(
clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s },
managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode
case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode
object TLRationalNameNode {
def apply(name: ValName) = TLRationalIdentityNode()(name)
def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLRationalIdentityNode = apply(Some(name))
}
case class TLRationalSourceNode()(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLRationalImp)(
dFn = { p => TLRationalClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain
case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName)
extends MixedAdapterNode(TLRationalImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut]
// Credited version of TileLink channels
trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters]
object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle]
{
def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle)
def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString)
override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLCreditedAdapterNode(
clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s },
managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode
case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode
object TLCreditedNameNode {
def apply(name: ValName) = TLCreditedIdentityNode()(name)
def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLCreditedIdentityNode = apply(Some(name))
}
case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLCreditedImp)(
dFn = { p => TLCreditedClientPortParameters(delay, p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain
case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLCreditedImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut]
File ToAXI4.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.lazymodule._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.amba.{AMBACorrupt, AMBACorruptField, AMBAProt, AMBAProtField}
import freechips.rocketchip.amba.axi4.{AXI4BundleARW, AXI4MasterParameters, AXI4MasterPortParameters, AXI4Parameters, AXI4Imp}
import freechips.rocketchip.diplomacy.{IdMap, IdMapEntry, IdRange}
import freechips.rocketchip.util.{BundleField, ControlKey, ElaborationArtefacts, UIntToOH1}
import freechips.rocketchip.util.DataToAugmentedData
class AXI4TLStateBundle(val sourceBits: Int) extends Bundle {
val size = UInt(4.W)
val source = UInt((sourceBits max 1).W)
}
case object AXI4TLState extends ControlKey[AXI4TLStateBundle]("tl_state")
case class AXI4TLStateField(sourceBits: Int) extends BundleField[AXI4TLStateBundle](AXI4TLState, Output(new AXI4TLStateBundle(sourceBits)), x => {
x.size := 0.U
x.source := 0.U
})
/** TLtoAXI4IdMap serves as a record for the translation performed between id spaces.
*
* Its member [axi4Masters] is used as the new AXI4MasterParameters in diplomacy.
* Its member [mapping] is used as the template for the circuit generated in TLToAXI4Node.module.
*/
class TLtoAXI4IdMap(tlPort: TLMasterPortParameters) extends IdMap[TLToAXI4IdMapEntry]
{
val tlMasters = tlPort.masters.sortBy(_.sourceId).sortWith(TLToAXI4.sortByType)
private val axi4IdSize = tlMasters.map { tl => if (tl.requestFifo) 1 else tl.sourceId.size }
private val axi4IdStart = axi4IdSize.scanLeft(0)(_+_).init
val axi4Masters = axi4IdStart.zip(axi4IdSize).zip(tlMasters).map { case ((start, size), tl) =>
AXI4MasterParameters(
name = tl.name,
id = IdRange(start, start+size),
aligned = true,
maxFlight = Some(if (tl.requestFifo) tl.sourceId.size else 1),
nodePath = tl.nodePath)
}
private val axi4IdEnd = axi4Masters.map(_.id.end).max
private val axiDigits = String.valueOf(axi4IdEnd-1).length()
private val tlDigits = String.valueOf(tlPort.endSourceId-1).length()
protected val fmt = s"\t[%${axiDigits}d, %${axiDigits}d) <= [%${tlDigits}d, %${tlDigits}d) %s%s%s"
val mapping: Seq[TLToAXI4IdMapEntry] = tlMasters.zip(axi4Masters).map { case (tl, axi) =>
TLToAXI4IdMapEntry(axi.id, tl.sourceId, tl.name, tl.supports.probe, tl.requestFifo)
}
}
case class TLToAXI4IdMapEntry(axi4Id: IdRange, tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean)
extends IdMapEntry
{
val from = tlId
val to = axi4Id
val maxTransactionsInFlight = Some(tlId.size)
}
case class TLToAXI4Node(wcorrupt: Boolean = true)(implicit valName: ValName) extends MixedAdapterNode(TLImp, AXI4Imp)(
dFn = { p =>
AXI4MasterPortParameters(
masters = (new TLtoAXI4IdMap(p)).axi4Masters,
requestFields = (if (wcorrupt) Seq(AMBACorruptField()) else Seq()) ++ p.requestFields.filter(!_.isInstanceOf[AMBAProtField]),
echoFields = AXI4TLStateField(log2Ceil(p.endSourceId)) +: p.echoFields,
responseKeys = p.responseKeys)
},
uFn = { p => TLSlavePortParameters.v1(
managers = p.slaves.map { case s =>
TLSlaveParameters.v1(
address = s.address,
resources = s.resources,
regionType = s.regionType,
executable = s.executable,
nodePath = s.nodePath,
supportsGet = s.supportsRead,
supportsPutFull = s.supportsWrite,
supportsPutPartial = s.supportsWrite,
fifoId = Some(0),
mayDenyPut = true,
mayDenyGet = true)},
beatBytes = p.beatBytes,
minLatency = p.minLatency,
responseFields = p.responseFields,
requestKeys = AMBAProt +: p.requestKeys)
})
// wcorrupt alone is not enough; a slave must include AMBACorrupt in the slave port's requestKeys
class TLToAXI4(val combinational: Boolean = true, val adapterName: Option[String] = None, val stripBits: Int = 0, val wcorrupt: Boolean = true)(implicit p: Parameters) extends LazyModule
{
require(stripBits == 0, "stripBits > 0 is no longer supported on TLToAXI4")
val node = TLToAXI4Node(wcorrupt)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
val slaves = edgeOut.slave.slaves
// All pairs of slaves must promise that they will never interleave data
require (slaves(0).interleavedId.isDefined)
slaves.foreach { s => require (s.interleavedId == slaves(0).interleavedId) }
// Construct the source=>ID mapping table
val map = new TLtoAXI4IdMap(edgeIn.client)
val sourceStall = WireDefault(VecInit.fill(edgeIn.client.endSourceId)(false.B))
val sourceTable = WireDefault(VecInit.fill(edgeIn.client.endSourceId)(0.U.asTypeOf(out.aw.bits.id)))
val idStall = WireDefault(VecInit.fill(edgeOut.master.endId)(false.B))
var idCount = Array.fill(edgeOut.master.endId) { None:Option[Int] }
map.mapping.foreach { case TLToAXI4IdMapEntry(axi4Id, tlId, _, _, fifo) =>
for (i <- 0 until tlId.size) {
val id = axi4Id.start + (if (fifo) 0 else i)
sourceStall(tlId.start + i) := idStall(id)
sourceTable(tlId.start + i) := id.U
}
if (fifo) { idCount(axi4Id.start) = Some(tlId.size) }
}
adapterName.foreach { n =>
println(s"$n AXI4-ID <= TL-Source mapping:\n${map.pretty}\n")
ElaborationArtefacts.add(s"$n.axi4.json", s"""{"mapping":[${map.mapping.mkString(",")}]}""")
}
// We need to keep the following state from A => D: (size, source)
// All of those fields could potentially require 0 bits (argh. Chisel.)
// We will pack all of that extra information into the echo bits.
require (log2Ceil(edgeIn.maxLgSize+1) <= 4)
val a_address = edgeIn.address(in.a.bits)
val a_source = in.a.bits.source
val a_size = edgeIn.size(in.a.bits)
val a_isPut = edgeIn.hasData(in.a.bits)
val (a_first, a_last, _) = edgeIn.firstlast(in.a)
val r_state = out.r.bits.echo(AXI4TLState)
val r_source = r_state.source
val r_size = r_state.size
val b_state = out.b.bits.echo(AXI4TLState)
val b_source = b_state.source
val b_size = b_state.size
// We need these Queues because AXI4 queues are irrevocable
val depth = if (combinational) 1 else 2
val out_arw = Wire(Decoupled(new AXI4BundleARW(out.params)))
val out_w = Wire(chiselTypeOf(out.w))
out.w :<>= Queue.irrevocable(out_w, entries=depth, flow=combinational)
val queue_arw = Queue.irrevocable(out_arw, entries=depth, flow=combinational)
// Fan out the ARW channel to AR and AW
out.ar.bits := queue_arw.bits
out.aw.bits := queue_arw.bits
out.ar.valid := queue_arw.valid && !queue_arw.bits.wen
out.aw.valid := queue_arw.valid && queue_arw.bits.wen
queue_arw.ready := Mux(queue_arw.bits.wen, out.aw.ready, out.ar.ready)
val beatBytes = edgeIn.manager.beatBytes
val maxSize = log2Ceil(beatBytes).U
val doneAW = RegInit(false.B)
when (in.a.fire) { doneAW := !a_last }
val arw = out_arw.bits
arw.wen := a_isPut
arw.id := sourceTable(a_source)
arw.addr := a_address
arw.len := UIntToOH1(a_size, AXI4Parameters.lenBits + log2Ceil(beatBytes)) >> log2Ceil(beatBytes)
arw.size := Mux(a_size >= maxSize, maxSize, a_size)
arw.burst := AXI4Parameters.BURST_INCR
arw.lock := 0.U // not exclusive (LR/SC unsupported b/c no forward progress guarantee)
arw.cache := 0.U // do not allow AXI to modify our transactions
arw.prot := AXI4Parameters.PROT_PRIVILEGED
arw.qos := 0.U // no QoS
Connectable.waiveUnmatched(arw.user, in.a.bits.user) match {
case (lhs, rhs) => lhs :<= rhs
}
Connectable.waiveUnmatched(arw.echo, in.a.bits.echo) match {
case (lhs, rhs) => lhs :<= rhs
}
val a_extra = arw.echo(AXI4TLState)
a_extra.source := a_source
a_extra.size := a_size
in.a.bits.user.lift(AMBAProt).foreach { x =>
val prot = Wire(Vec(3, Bool()))
val cache = Wire(Vec(4, Bool()))
prot(0) := x.privileged
prot(1) := !x.secure
prot(2) := x.fetch
cache(0) := x.bufferable
cache(1) := x.modifiable
cache(2) := x.readalloc
cache(3) := x.writealloc
arw.prot := Cat(prot.reverse)
arw.cache := Cat(cache.reverse)
}
val stall = sourceStall(in.a.bits.source) && a_first
in.a.ready := !stall && Mux(a_isPut, (doneAW || out_arw.ready) && out_w.ready, out_arw.ready)
out_arw.valid := !stall && in.a.valid && Mux(a_isPut, !doneAW && out_w.ready, true.B)
out_w.valid := !stall && in.a.valid && a_isPut && (doneAW || out_arw.ready)
out_w.bits.data := in.a.bits.data
out_w.bits.strb := in.a.bits.mask
out_w.bits.last := a_last
out_w.bits.user.lift(AMBACorrupt).foreach { _ := in.a.bits.corrupt }
// R and B => D arbitration
val r_holds_d = RegInit(false.B)
when (out.r.fire) { r_holds_d := !out.r.bits.last }
// Give R higher priority than B, unless B has been delayed for 8 cycles
val b_delay = Reg(UInt(3.W))
when (out.b.valid && !out.b.ready) {
b_delay := b_delay + 1.U
} .otherwise {
b_delay := 0.U
}
val r_wins = (out.r.valid && b_delay =/= 7.U) || r_holds_d
out.r.ready := in.d.ready && r_wins
out.b.ready := in.d.ready && !r_wins
in.d.valid := Mux(r_wins, out.r.valid, out.b.valid)
// If the first beat of the AXI RRESP is RESP_DECERR, treat this as a denied
// request. We must pulse extend this value as AXI is allowed to change the
// value of RRESP on every beat, and ChipLink may not.
val r_first = RegInit(true.B)
when (out.r.fire) { r_first := out.r.bits.last }
val r_denied = out.r.bits.resp === AXI4Parameters.RESP_DECERR holdUnless r_first
val r_corrupt = out.r.bits.resp =/= AXI4Parameters.RESP_OKAY
val b_denied = out.b.bits.resp =/= AXI4Parameters.RESP_OKAY
val r_d = edgeIn.AccessAck(r_source, r_size, 0.U, denied = r_denied, corrupt = r_corrupt || r_denied)
val b_d = edgeIn.AccessAck(b_source, b_size, denied = b_denied)
Connectable.waiveUnmatched(r_d.user, out.r.bits.user) match {
case (lhs, rhs) => lhs.squeezeAll :<= rhs.squeezeAll
}
Connectable.waiveUnmatched(r_d.echo, out.r.bits.echo) match {
case (lhs, rhs) => lhs.squeezeAll :<= rhs.squeezeAll
}
Connectable.waiveUnmatched(b_d.user, out.b.bits.user) match {
case (lhs, rhs) => lhs.squeezeAll :<= rhs.squeezeAll
}
Connectable.waiveUnmatched(b_d.echo, out.b.bits.echo) match {
case (lhs, rhs) => lhs.squeezeAll :<= rhs.squeezeAll
}
in.d.bits := Mux(r_wins, r_d, b_d)
in.d.bits.data := out.r.bits.data // avoid a costly Mux
// We need to track if any reads or writes are inflight for a given ID.
// If the opposite type arrives, we must stall until it completes.
val a_sel = UIntToOH(arw.id, edgeOut.master.endId).asBools
val d_sel = UIntToOH(Mux(r_wins, out.r.bits.id, out.b.bits.id), edgeOut.master.endId).asBools
val d_last = Mux(r_wins, out.r.bits.last, true.B)
// If FIFO was requested, ensure that R+W ordering is preserved
(a_sel zip d_sel zip idStall zip idCount) foreach { case (((as, ds), s), n) =>
// AXI does not guarantee read vs. write ordering. In particular, if we
// are in the middle of receiving a read burst and then issue a write,
// the write might affect the read burst. This violates FIFO behaviour.
// To solve this, we must wait until the last beat of a burst, but this
// means that a TileLink master which performs early source reuse can
// have one more transaction inflight than we promised AXI; stall it too.
val maxCount = n.getOrElse(1)
val count = RegInit(0.U(log2Ceil(maxCount + 1).W))
val write = Reg(Bool())
val idle = count === 0.U
val inc = as && out_arw.fire
val dec = ds && d_last && in.d.fire
count := count + inc.asUInt - dec.asUInt
assert (!dec || count =/= 0.U) // underflow
assert (!inc || count =/= maxCount.U) // overflow
when (inc) { write := arw.wen }
// If only one transaction can be inflight, it can't mismatch
val mismatch = if (maxCount > 1) { write =/= arw.wen } else { false.B }
s := (!idle && mismatch) || (count === maxCount.U)
}
// Tie off unused channels
in.b.valid := false.B
in.c.ready := true.B
in.e.ready := true.B
}
}
}
object TLToAXI4
{
def apply(combinational: Boolean = true, adapterName: Option[String] = None, stripBits: Int = 0, wcorrupt: Boolean = true)(implicit p: Parameters) =
{
val tl2axi4 = LazyModule(new TLToAXI4(combinational, adapterName, stripBits, wcorrupt))
tl2axi4.node
}
def sortByType(a: TLMasterParameters, b: TLMasterParameters): Boolean = {
if ( a.supports.probe && !b.supports.probe) return false
if (!a.supports.probe && b.supports.probe) return true
if ( a.requestFifo && !b.requestFifo ) return false
if (!a.requestFifo && b.requestFifo ) return true
return false
}
}
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLToAXI4( // @[ToAXI4.scala:103:9]
input clock, // @[ToAXI4.scala:103:9]
input reset, // @[ToAXI4.scala:103:9]
output auto_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_aw_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_aw_valid, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_out_aw_bits_id, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_aw_bits_addr, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_aw_bits_len, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_aw_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_out_aw_bits_burst, // @[LazyModuleImp.scala:107:25]
output auto_out_aw_bits_lock, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_aw_bits_cache, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_aw_bits_prot, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_aw_bits_qos, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_aw_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_out_aw_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25]
input auto_out_w_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_w_valid, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_w_bits_data, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_w_bits_strb, // @[LazyModuleImp.scala:107:25]
output auto_out_w_bits_last, // @[LazyModuleImp.scala:107:25]
output auto_out_b_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_b_valid, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_out_b_bits_id, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_b_bits_resp, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_b_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_out_b_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25]
input auto_out_ar_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_ar_valid, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_out_ar_bits_id, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_ar_bits_addr, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_ar_bits_len, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_ar_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_out_ar_bits_burst, // @[LazyModuleImp.scala:107:25]
output auto_out_ar_bits_lock, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_ar_bits_cache, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_ar_bits_prot, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_ar_bits_qos, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_ar_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_out_ar_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25]
output auto_out_r_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_r_valid, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_out_r_bits_id, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_r_bits_data, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_r_bits_resp, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_r_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_out_r_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25]
input auto_out_r_bits_last // @[LazyModuleImp.scala:107:25]
);
reg count_115; // @[ToAXI4.scala:272:28]
reg count_114; // @[ToAXI4.scala:272:28]
reg count_113; // @[ToAXI4.scala:272:28]
reg count_112; // @[ToAXI4.scala:272:28]
reg count_111; // @[ToAXI4.scala:272:28]
reg count_110; // @[ToAXI4.scala:272:28]
reg count_109; // @[ToAXI4.scala:272:28]
reg count_108; // @[ToAXI4.scala:272:28]
reg count_107; // @[ToAXI4.scala:272:28]
reg count_106; // @[ToAXI4.scala:272:28]
reg count_105; // @[ToAXI4.scala:272:28]
reg count_104; // @[ToAXI4.scala:272:28]
reg count_103; // @[ToAXI4.scala:272:28]
reg count_102; // @[ToAXI4.scala:272:28]
reg count_101; // @[ToAXI4.scala:272:28]
reg count_100; // @[ToAXI4.scala:272:28]
reg count_99; // @[ToAXI4.scala:272:28]
reg count_98; // @[ToAXI4.scala:272:28]
reg count_97; // @[ToAXI4.scala:272:28]
reg count_96; // @[ToAXI4.scala:272:28]
reg count_95; // @[ToAXI4.scala:272:28]
reg count_94; // @[ToAXI4.scala:272:28]
reg count_93; // @[ToAXI4.scala:272:28]
reg count_92; // @[ToAXI4.scala:272:28]
reg count_91; // @[ToAXI4.scala:272:28]
reg count_90; // @[ToAXI4.scala:272:28]
reg count_89; // @[ToAXI4.scala:272:28]
reg count_88; // @[ToAXI4.scala:272:28]
reg count_87; // @[ToAXI4.scala:272:28]
reg count_86; // @[ToAXI4.scala:272:28]
reg count_85; // @[ToAXI4.scala:272:28]
reg count_84; // @[ToAXI4.scala:272:28]
reg count_83; // @[ToAXI4.scala:272:28]
reg count_82; // @[ToAXI4.scala:272:28]
reg count_81; // @[ToAXI4.scala:272:28]
reg count_80; // @[ToAXI4.scala:272:28]
reg count_79; // @[ToAXI4.scala:272:28]
reg count_78; // @[ToAXI4.scala:272:28]
reg count_77; // @[ToAXI4.scala:272:28]
reg count_76; // @[ToAXI4.scala:272:28]
reg count_75; // @[ToAXI4.scala:272:28]
reg count_74; // @[ToAXI4.scala:272:28]
reg count_73; // @[ToAXI4.scala:272:28]
reg count_72; // @[ToAXI4.scala:272:28]
reg count_71; // @[ToAXI4.scala:272:28]
reg count_70; // @[ToAXI4.scala:272:28]
reg count_69; // @[ToAXI4.scala:272:28]
reg count_68; // @[ToAXI4.scala:272:28]
reg count_67; // @[ToAXI4.scala:272:28]
reg count_66; // @[ToAXI4.scala:272:28]
reg count_65; // @[ToAXI4.scala:272:28]
reg count_64; // @[ToAXI4.scala:272:28]
reg count_63; // @[ToAXI4.scala:272:28]
reg count_62; // @[ToAXI4.scala:272:28]
reg count_61; // @[ToAXI4.scala:272:28]
reg count_60; // @[ToAXI4.scala:272:28]
reg count_59; // @[ToAXI4.scala:272:28]
reg count_58; // @[ToAXI4.scala:272:28]
reg count_57; // @[ToAXI4.scala:272:28]
reg count_56; // @[ToAXI4.scala:272:28]
reg count_55; // @[ToAXI4.scala:272:28]
reg count_54; // @[ToAXI4.scala:272:28]
reg count_53; // @[ToAXI4.scala:272:28]
reg count_52; // @[ToAXI4.scala:272:28]
reg count_51; // @[ToAXI4.scala:272:28]
reg count_50; // @[ToAXI4.scala:272:28]
reg count_49; // @[ToAXI4.scala:272:28]
reg count_48; // @[ToAXI4.scala:272:28]
reg count_47; // @[ToAXI4.scala:272:28]
reg count_46; // @[ToAXI4.scala:272:28]
reg count_45; // @[ToAXI4.scala:272:28]
reg count_44; // @[ToAXI4.scala:272:28]
reg count_43; // @[ToAXI4.scala:272:28]
reg count_42; // @[ToAXI4.scala:272:28]
reg count_41; // @[ToAXI4.scala:272:28]
reg count_40; // @[ToAXI4.scala:272:28]
reg count_39; // @[ToAXI4.scala:272:28]
reg count_38; // @[ToAXI4.scala:272:28]
reg count_37; // @[ToAXI4.scala:272:28]
reg count_36; // @[ToAXI4.scala:272:28]
reg count_35; // @[ToAXI4.scala:272:28]
reg count_34; // @[ToAXI4.scala:272:28]
reg count_33; // @[ToAXI4.scala:272:28]
reg count_32; // @[ToAXI4.scala:272:28]
reg count_31; // @[ToAXI4.scala:272:28]
reg count_30; // @[ToAXI4.scala:272:28]
reg count_29; // @[ToAXI4.scala:272:28]
reg count_28; // @[ToAXI4.scala:272:28]
reg count_27; // @[ToAXI4.scala:272:28]
reg count_26; // @[ToAXI4.scala:272:28]
reg count_25; // @[ToAXI4.scala:272:28]
reg count_24; // @[ToAXI4.scala:272:28]
reg count_23; // @[ToAXI4.scala:272:28]
reg count_22; // @[ToAXI4.scala:272:28]
reg count_21; // @[ToAXI4.scala:272:28]
reg count_20; // @[ToAXI4.scala:272:28]
reg count_19; // @[ToAXI4.scala:272:28]
reg count_18; // @[ToAXI4.scala:272:28]
reg count_17; // @[ToAXI4.scala:272:28]
reg count_16; // @[ToAXI4.scala:272:28]
reg count_15; // @[ToAXI4.scala:272:28]
reg count_14; // @[ToAXI4.scala:272:28]
reg count_13; // @[ToAXI4.scala:272:28]
reg count_12; // @[ToAXI4.scala:272:28]
reg count_11; // @[ToAXI4.scala:272:28]
reg count_10; // @[ToAXI4.scala:272:28]
reg count_9; // @[ToAXI4.scala:272:28]
reg count_8; // @[ToAXI4.scala:272:28]
reg count_7; // @[ToAXI4.scala:272:28]
reg count_6; // @[ToAXI4.scala:272:28]
reg count_5; // @[ToAXI4.scala:272:28]
reg count_4; // @[ToAXI4.scala:272:28]
reg count_3; // @[ToAXI4.scala:272:28]
reg count_2; // @[ToAXI4.scala:272:28]
reg count_1; // @[ToAXI4.scala:272:28]
reg count; // @[ToAXI4.scala:272:28]
wire _queue_arw_deq_q_io_enq_ready; // @[Decoupled.scala:362:21]
wire _queue_arw_deq_q_io_deq_valid; // @[Decoupled.scala:362:21]
wire [6:0] _queue_arw_deq_q_io_deq_bits_id; // @[Decoupled.scala:362:21]
wire [31:0] _queue_arw_deq_q_io_deq_bits_addr; // @[Decoupled.scala:362:21]
wire [7:0] _queue_arw_deq_q_io_deq_bits_len; // @[Decoupled.scala:362:21]
wire [2:0] _queue_arw_deq_q_io_deq_bits_size; // @[Decoupled.scala:362:21]
wire [1:0] _queue_arw_deq_q_io_deq_bits_burst; // @[Decoupled.scala:362:21]
wire _queue_arw_deq_q_io_deq_bits_lock; // @[Decoupled.scala:362:21]
wire [3:0] _queue_arw_deq_q_io_deq_bits_cache; // @[Decoupled.scala:362:21]
wire [2:0] _queue_arw_deq_q_io_deq_bits_prot; // @[Decoupled.scala:362:21]
wire [3:0] _queue_arw_deq_q_io_deq_bits_qos; // @[Decoupled.scala:362:21]
wire [3:0] _queue_arw_deq_q_io_deq_bits_echo_tl_state_size; // @[Decoupled.scala:362:21]
wire [6:0] _queue_arw_deq_q_io_deq_bits_echo_tl_state_source; // @[Decoupled.scala:362:21]
wire _queue_arw_deq_q_io_deq_bits_wen; // @[Decoupled.scala:362:21]
wire _nodeOut_w_deq_q_io_enq_ready; // @[Decoupled.scala:362:21]
wire [127:0][6:0] _GEN = '{7'h0, 7'h0, 7'h0, 7'h0, 7'h0, 7'h0, 7'h0, 7'h0, 7'h0, 7'h0, 7'h0, 7'h0, 7'h73, 7'h72, 7'h71, 7'h70, 7'h6F, 7'h6E, 7'h6D, 7'h6C, 7'h6B, 7'h6A, 7'h69, 7'h68, 7'h67, 7'h66, 7'h65, 7'h64, 7'h63, 7'h62, 7'h61, 7'h60, 7'h5F, 7'h5E, 7'h5D, 7'h5C, 7'h5B, 7'h5A, 7'h59, 7'h58, 7'h57, 7'h56, 7'h55, 7'h54, 7'h53, 7'h52, 7'h51, 7'h50, 7'h4F, 7'h4E, 7'h4D, 7'h4C, 7'h4B, 7'h4A, 7'h49, 7'h48, 7'h47, 7'h46, 7'h45, 7'h44, 7'h43, 7'h42, 7'h41, 7'h40, 7'h3F, 7'h3E, 7'h3D, 7'h3C, 7'h3B, 7'h3A, 7'h39, 7'h38, 7'h37, 7'h36, 7'h35, 7'h34, 7'h33, 7'h32, 7'h31, 7'h30, 7'h2F, 7'h2E, 7'h2D, 7'h2C, 7'h2B, 7'h2A, 7'h29, 7'h28, 7'h27, 7'h26, 7'h25, 7'h24, 7'h23, 7'h22, 7'h21, 7'h20, 7'h1F, 7'h1E, 7'h1D, 7'h1C, 7'h1B, 7'h1A, 7'h19, 7'h18, 7'h17, 7'h16, 7'h15, 7'h14, 7'h13, 7'h12, 7'h11, 7'h10, 7'hF, 7'hE, 7'hD, 7'hC, 7'hB, 7'hA, 7'h9, 7'h8, 7'h7, 7'h6, 7'h5, 7'h4, 7'h3, 7'h2, 7'h1, 7'h0};
wire [12:0] _r_beats1_decode_T = 13'h3F << auto_in_a_bits_size; // @[package.scala:243:71]
wire [2:0] r_beats1 = auto_in_a_bits_opcode[2] ? 3'h0 : ~(_r_beats1_decode_T[5:3]); // @[package.scala:243:{46,71,76}]
reg [2:0] r_counter; // @[Edges.scala:229:27]
wire a_first = r_counter == 3'h0; // @[ToAXI4.scala:103:9]
wire a_last = r_counter == 3'h1 | r_beats1 == 3'h0; // @[ToAXI4.scala:103:9]
reg doneAW; // @[ToAXI4.scala:167:30]
wire [17:0] _out_arw_bits_len_T = 18'h7FF << auto_in_a_bits_size; // @[package.scala:243:71]
wire [127:0] _GEN_0 = {{count}, {count}, {count}, {count}, {count}, {count}, {count}, {count}, {count}, {count}, {count}, {count}, {count_115}, {count_114}, {count_113}, {count_112}, {count_111}, {count_110}, {count_109}, {count_108}, {count_107}, {count_106}, {count_105}, {count_104}, {count_103}, {count_102}, {count_101}, {count_100}, {count_99}, {count_98}, {count_97}, {count_96}, {count_95}, {count_94}, {count_93}, {count_92}, {count_91}, {count_90}, {count_89}, {count_88}, {count_87}, {count_86}, {count_85}, {count_84}, {count_83}, {count_82}, {count_81}, {count_80}, {count_79}, {count_78}, {count_77}, {count_76}, {count_75}, {count_74}, {count_73}, {count_72}, {count_71}, {count_70}, {count_69}, {count_68}, {count_67}, {count_66}, {count_65}, {count_64}, {count_63}, {count_62}, {count_61}, {count_60}, {count_59}, {count_58}, {count_57}, {count_56}, {count_55}, {count_54}, {count_53}, {count_52}, {count_51}, {count_50}, {count_49}, {count_48}, {count_47}, {count_46}, {count_45}, {count_44}, {count_43}, {count_42}, {count_41}, {count_40}, {count_39}, {count_38}, {count_37}, {count_36}, {count_35}, {count_34}, {count_33}, {count_32}, {count_31}, {count_30}, {count_29}, {count_28}, {count_27}, {count_26}, {count_25}, {count_24}, {count_23}, {count_22}, {count_21}, {count_20}, {count_19}, {count_18}, {count_17}, {count_16}, {count_15}, {count_14}, {count_13}, {count_12}, {count_11}, {count_10}, {count_9}, {count_8}, {count_7}, {count_6}, {count_5}, {count_4}, {count_3}, {count_2}, {count_1}, {count}}; // @[ToAXI4.scala:205:49, :272:28]
wire stall = _GEN_0[auto_in_a_bits_source] & a_first; // @[ToAXI4.scala:205:49]
wire _out_w_valid_T_3 = doneAW | _queue_arw_deq_q_io_enq_ready; // @[Decoupled.scala:362:21]
wire nodeIn_a_ready = ~stall & (auto_in_a_bits_opcode[2] ? _queue_arw_deq_q_io_enq_ready : _out_w_valid_T_3 & _nodeOut_w_deq_q_io_enq_ready); // @[Decoupled.scala:362:21]
wire out_arw_valid = ~stall & auto_in_a_valid & (auto_in_a_bits_opcode[2] | ~doneAW & _nodeOut_w_deq_q_io_enq_ready); // @[Decoupled.scala:362:21]
reg r_holds_d; // @[ToAXI4.scala:216:30]
reg [2:0] b_delay; // @[ToAXI4.scala:219:24]
wire r_wins = auto_out_r_valid & b_delay != 3'h7 | r_holds_d; // @[ToAXI4.scala:103:9, :216:30, :219:24, :225:{33,44,53}]
wire nodeOut_r_ready = auto_in_d_ready & r_wins; // @[ToAXI4.scala:225:53, :227:33]
wire nodeOut_b_ready = auto_in_d_ready & ~r_wins; // @[ToAXI4.scala:225:53, :228:{33,36}]
wire nodeIn_d_valid = r_wins ? auto_out_r_valid : auto_out_b_valid; // @[ToAXI4.scala:225:53, :229:24]
reg r_first; // @[ToAXI4.scala:234:28]
reg r_denied_r; // @[package.scala:88:63]
wire r_denied = r_first ? (&auto_out_r_bits_resp) : r_denied_r; // @[package.scala:88:{42,63}]
wire [2:0] nodeIn_d_bits_opcode = {2'h0, r_wins}; // @[ToAXI4.scala:225:53, :255:23]
wire [2:0] nodeIn_d_bits_size = r_wins ? auto_out_r_bits_echo_tl_state_size[2:0] : auto_out_b_bits_echo_tl_state_size[2:0]; // @[ToAXI4.scala:225:53, :255:23]
wire [6:0] nodeIn_d_bits_source = r_wins ? auto_out_r_bits_echo_tl_state_source : auto_out_b_bits_echo_tl_state_source; // @[ToAXI4.scala:225:53, :255:23]
wire nodeIn_d_bits_denied = r_wins ? r_denied : (|auto_out_b_bits_resp); // @[package.scala:88:42]
wire nodeIn_d_bits_corrupt = r_wins & ((|auto_out_r_bits_resp) | r_denied); // @[package.scala:88:42]
wire [6:0] d_sel_shiftAmount = r_wins ? auto_out_r_bits_id : auto_out_b_bits_id; // @[ToAXI4.scala:225:53, :261:31]
wire d_last = ~r_wins | auto_out_r_bits_last; // @[ToAXI4.scala:225:53, :262:23]
wire _inc_T_115 = _queue_arw_deq_q_io_enq_ready & out_arw_valid; // @[Decoupled.scala:51:35, :362:21]
wire inc = _GEN[auto_in_a_bits_source] == 7'h0 & _inc_T_115; // @[OneHot.scala:65:27]
wire _dec_T_231 = auto_in_d_ready & nodeIn_d_valid; // @[Decoupled.scala:51:35]
wire dec = d_sel_shiftAmount == 7'h0 & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_1 = _GEN[auto_in_a_bits_source] == 7'h1 & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_1 = d_sel_shiftAmount == 7'h1 & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_2 = _GEN[auto_in_a_bits_source] == 7'h2 & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_2 = d_sel_shiftAmount == 7'h2 & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_3 = _GEN[auto_in_a_bits_source] == 7'h3 & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_3 = d_sel_shiftAmount == 7'h3 & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_4 = _GEN[auto_in_a_bits_source] == 7'h4 & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_4 = d_sel_shiftAmount == 7'h4 & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_5 = _GEN[auto_in_a_bits_source] == 7'h5 & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_5 = d_sel_shiftAmount == 7'h5 & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_6 = _GEN[auto_in_a_bits_source] == 7'h6 & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_6 = d_sel_shiftAmount == 7'h6 & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_7 = _GEN[auto_in_a_bits_source] == 7'h7 & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_7 = d_sel_shiftAmount == 7'h7 & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_8 = _GEN[auto_in_a_bits_source] == 7'h8 & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_8 = d_sel_shiftAmount == 7'h8 & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_9 = _GEN[auto_in_a_bits_source] == 7'h9 & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_9 = d_sel_shiftAmount == 7'h9 & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_10 = _GEN[auto_in_a_bits_source] == 7'hA & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_10 = d_sel_shiftAmount == 7'hA & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_11 = _GEN[auto_in_a_bits_source] == 7'hB & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_11 = d_sel_shiftAmount == 7'hB & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_12 = _GEN[auto_in_a_bits_source] == 7'hC & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_12 = d_sel_shiftAmount == 7'hC & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_13 = _GEN[auto_in_a_bits_source] == 7'hD & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_13 = d_sel_shiftAmount == 7'hD & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_14 = _GEN[auto_in_a_bits_source] == 7'hE & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_14 = d_sel_shiftAmount == 7'hE & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_15 = _GEN[auto_in_a_bits_source] == 7'hF & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_15 = d_sel_shiftAmount == 7'hF & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_16 = _GEN[auto_in_a_bits_source] == 7'h10 & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_16 = d_sel_shiftAmount == 7'h10 & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_17 = _GEN[auto_in_a_bits_source] == 7'h11 & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_17 = d_sel_shiftAmount == 7'h11 & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_18 = _GEN[auto_in_a_bits_source] == 7'h12 & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_18 = d_sel_shiftAmount == 7'h12 & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_19 = _GEN[auto_in_a_bits_source] == 7'h13 & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_19 = d_sel_shiftAmount == 7'h13 & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_20 = _GEN[auto_in_a_bits_source] == 7'h14 & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_20 = d_sel_shiftAmount == 7'h14 & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_21 = _GEN[auto_in_a_bits_source] == 7'h15 & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_21 = d_sel_shiftAmount == 7'h15 & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_22 = _GEN[auto_in_a_bits_source] == 7'h16 & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_22 = d_sel_shiftAmount == 7'h16 & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_23 = _GEN[auto_in_a_bits_source] == 7'h17 & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_23 = d_sel_shiftAmount == 7'h17 & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_24 = _GEN[auto_in_a_bits_source] == 7'h18 & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_24 = d_sel_shiftAmount == 7'h18 & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_25 = _GEN[auto_in_a_bits_source] == 7'h19 & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_25 = d_sel_shiftAmount == 7'h19 & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_26 = _GEN[auto_in_a_bits_source] == 7'h1A & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_26 = d_sel_shiftAmount == 7'h1A & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_27 = _GEN[auto_in_a_bits_source] == 7'h1B & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_27 = d_sel_shiftAmount == 7'h1B & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_28 = _GEN[auto_in_a_bits_source] == 7'h1C & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_28 = d_sel_shiftAmount == 7'h1C & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_29 = _GEN[auto_in_a_bits_source] == 7'h1D & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_29 = d_sel_shiftAmount == 7'h1D & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_30 = _GEN[auto_in_a_bits_source] == 7'h1E & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_30 = d_sel_shiftAmount == 7'h1E & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_31 = _GEN[auto_in_a_bits_source] == 7'h1F & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_31 = d_sel_shiftAmount == 7'h1F & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_32 = _GEN[auto_in_a_bits_source] == 7'h20 & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_32 = d_sel_shiftAmount == 7'h20 & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_33 = _GEN[auto_in_a_bits_source] == 7'h21 & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_33 = d_sel_shiftAmount == 7'h21 & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_34 = _GEN[auto_in_a_bits_source] == 7'h22 & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_34 = d_sel_shiftAmount == 7'h22 & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_35 = _GEN[auto_in_a_bits_source] == 7'h23 & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_35 = d_sel_shiftAmount == 7'h23 & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_36 = _GEN[auto_in_a_bits_source] == 7'h24 & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_36 = d_sel_shiftAmount == 7'h24 & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_37 = _GEN[auto_in_a_bits_source] == 7'h25 & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_37 = d_sel_shiftAmount == 7'h25 & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_38 = _GEN[auto_in_a_bits_source] == 7'h26 & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_38 = d_sel_shiftAmount == 7'h26 & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_39 = _GEN[auto_in_a_bits_source] == 7'h27 & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_39 = d_sel_shiftAmount == 7'h27 & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_40 = _GEN[auto_in_a_bits_source] == 7'h28 & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_40 = d_sel_shiftAmount == 7'h28 & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_41 = _GEN[auto_in_a_bits_source] == 7'h29 & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_41 = d_sel_shiftAmount == 7'h29 & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_42 = _GEN[auto_in_a_bits_source] == 7'h2A & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_42 = d_sel_shiftAmount == 7'h2A & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_43 = _GEN[auto_in_a_bits_source] == 7'h2B & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_43 = d_sel_shiftAmount == 7'h2B & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_44 = _GEN[auto_in_a_bits_source] == 7'h2C & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_44 = d_sel_shiftAmount == 7'h2C & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_45 = _GEN[auto_in_a_bits_source] == 7'h2D & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_45 = d_sel_shiftAmount == 7'h2D & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_46 = _GEN[auto_in_a_bits_source] == 7'h2E & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_46 = d_sel_shiftAmount == 7'h2E & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_47 = _GEN[auto_in_a_bits_source] == 7'h2F & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_47 = d_sel_shiftAmount == 7'h2F & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_48 = _GEN[auto_in_a_bits_source] == 7'h30 & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_48 = d_sel_shiftAmount == 7'h30 & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_49 = _GEN[auto_in_a_bits_source] == 7'h31 & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_49 = d_sel_shiftAmount == 7'h31 & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_50 = _GEN[auto_in_a_bits_source] == 7'h32 & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_50 = d_sel_shiftAmount == 7'h32 & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_51 = _GEN[auto_in_a_bits_source] == 7'h33 & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_51 = d_sel_shiftAmount == 7'h33 & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_52 = _GEN[auto_in_a_bits_source] == 7'h34 & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_52 = d_sel_shiftAmount == 7'h34 & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_53 = _GEN[auto_in_a_bits_source] == 7'h35 & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_53 = d_sel_shiftAmount == 7'h35 & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_54 = _GEN[auto_in_a_bits_source] == 7'h36 & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_54 = d_sel_shiftAmount == 7'h36 & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_55 = _GEN[auto_in_a_bits_source] == 7'h37 & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_55 = d_sel_shiftAmount == 7'h37 & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_56 = _GEN[auto_in_a_bits_source] == 7'h38 & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_56 = d_sel_shiftAmount == 7'h38 & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_57 = _GEN[auto_in_a_bits_source] == 7'h39 & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_57 = d_sel_shiftAmount == 7'h39 & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_58 = _GEN[auto_in_a_bits_source] == 7'h3A & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_58 = d_sel_shiftAmount == 7'h3A & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_59 = _GEN[auto_in_a_bits_source] == 7'h3B & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_59 = d_sel_shiftAmount == 7'h3B & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_60 = _GEN[auto_in_a_bits_source] == 7'h3C & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_60 = d_sel_shiftAmount == 7'h3C & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_61 = _GEN[auto_in_a_bits_source] == 7'h3D & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_61 = d_sel_shiftAmount == 7'h3D & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_62 = _GEN[auto_in_a_bits_source] == 7'h3E & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_62 = d_sel_shiftAmount == 7'h3E & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_63 = _GEN[auto_in_a_bits_source] == 7'h3F & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_63 = d_sel_shiftAmount == 7'h3F & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_64 = _GEN[auto_in_a_bits_source] == 7'h40 & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_64 = d_sel_shiftAmount == 7'h40 & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_65 = _GEN[auto_in_a_bits_source] == 7'h41 & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_65 = d_sel_shiftAmount == 7'h41 & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_66 = _GEN[auto_in_a_bits_source] == 7'h42 & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_66 = d_sel_shiftAmount == 7'h42 & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_67 = _GEN[auto_in_a_bits_source] == 7'h43 & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_67 = d_sel_shiftAmount == 7'h43 & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_68 = _GEN[auto_in_a_bits_source] == 7'h44 & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_68 = d_sel_shiftAmount == 7'h44 & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_69 = _GEN[auto_in_a_bits_source] == 7'h45 & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_69 = d_sel_shiftAmount == 7'h45 & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_70 = _GEN[auto_in_a_bits_source] == 7'h46 & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_70 = d_sel_shiftAmount == 7'h46 & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_71 = _GEN[auto_in_a_bits_source] == 7'h47 & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_71 = d_sel_shiftAmount == 7'h47 & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_72 = _GEN[auto_in_a_bits_source] == 7'h48 & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_72 = d_sel_shiftAmount == 7'h48 & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_73 = _GEN[auto_in_a_bits_source] == 7'h49 & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_73 = d_sel_shiftAmount == 7'h49 & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_74 = _GEN[auto_in_a_bits_source] == 7'h4A & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_74 = d_sel_shiftAmount == 7'h4A & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_75 = _GEN[auto_in_a_bits_source] == 7'h4B & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_75 = d_sel_shiftAmount == 7'h4B & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_76 = _GEN[auto_in_a_bits_source] == 7'h4C & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_76 = d_sel_shiftAmount == 7'h4C & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_77 = _GEN[auto_in_a_bits_source] == 7'h4D & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_77 = d_sel_shiftAmount == 7'h4D & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_78 = _GEN[auto_in_a_bits_source] == 7'h4E & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_78 = d_sel_shiftAmount == 7'h4E & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_79 = _GEN[auto_in_a_bits_source] == 7'h4F & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_79 = d_sel_shiftAmount == 7'h4F & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_80 = _GEN[auto_in_a_bits_source] == 7'h50 & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_80 = d_sel_shiftAmount == 7'h50 & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_81 = _GEN[auto_in_a_bits_source] == 7'h51 & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_81 = d_sel_shiftAmount == 7'h51 & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_82 = _GEN[auto_in_a_bits_source] == 7'h52 & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_82 = d_sel_shiftAmount == 7'h52 & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_83 = _GEN[auto_in_a_bits_source] == 7'h53 & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_83 = d_sel_shiftAmount == 7'h53 & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_84 = _GEN[auto_in_a_bits_source] == 7'h54 & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_84 = d_sel_shiftAmount == 7'h54 & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_85 = _GEN[auto_in_a_bits_source] == 7'h55 & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_85 = d_sel_shiftAmount == 7'h55 & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_86 = _GEN[auto_in_a_bits_source] == 7'h56 & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_86 = d_sel_shiftAmount == 7'h56 & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_87 = _GEN[auto_in_a_bits_source] == 7'h57 & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_87 = d_sel_shiftAmount == 7'h57 & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_88 = _GEN[auto_in_a_bits_source] == 7'h58 & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_88 = d_sel_shiftAmount == 7'h58 & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_89 = _GEN[auto_in_a_bits_source] == 7'h59 & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_89 = d_sel_shiftAmount == 7'h59 & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_90 = _GEN[auto_in_a_bits_source] == 7'h5A & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_90 = d_sel_shiftAmount == 7'h5A & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_91 = _GEN[auto_in_a_bits_source] == 7'h5B & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_91 = d_sel_shiftAmount == 7'h5B & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_92 = _GEN[auto_in_a_bits_source] == 7'h5C & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_92 = d_sel_shiftAmount == 7'h5C & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_93 = _GEN[auto_in_a_bits_source] == 7'h5D & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_93 = d_sel_shiftAmount == 7'h5D & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_94 = _GEN[auto_in_a_bits_source] == 7'h5E & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_94 = d_sel_shiftAmount == 7'h5E & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_95 = _GEN[auto_in_a_bits_source] == 7'h5F & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_95 = d_sel_shiftAmount == 7'h5F & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_96 = _GEN[auto_in_a_bits_source] == 7'h60 & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_96 = d_sel_shiftAmount == 7'h60 & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_97 = _GEN[auto_in_a_bits_source] == 7'h61 & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_97 = d_sel_shiftAmount == 7'h61 & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_98 = _GEN[auto_in_a_bits_source] == 7'h62 & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_98 = d_sel_shiftAmount == 7'h62 & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_99 = _GEN[auto_in_a_bits_source] == 7'h63 & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_99 = d_sel_shiftAmount == 7'h63 & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_100 = _GEN[auto_in_a_bits_source] == 7'h64 & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_100 = d_sel_shiftAmount == 7'h64 & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_101 = _GEN[auto_in_a_bits_source] == 7'h65 & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_101 = d_sel_shiftAmount == 7'h65 & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_102 = _GEN[auto_in_a_bits_source] == 7'h66 & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_102 = d_sel_shiftAmount == 7'h66 & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_103 = _GEN[auto_in_a_bits_source] == 7'h67 & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_103 = d_sel_shiftAmount == 7'h67 & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_104 = _GEN[auto_in_a_bits_source] == 7'h68 & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_104 = d_sel_shiftAmount == 7'h68 & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_105 = _GEN[auto_in_a_bits_source] == 7'h69 & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_105 = d_sel_shiftAmount == 7'h69 & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_106 = _GEN[auto_in_a_bits_source] == 7'h6A & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_106 = d_sel_shiftAmount == 7'h6A & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_107 = _GEN[auto_in_a_bits_source] == 7'h6B & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_107 = d_sel_shiftAmount == 7'h6B & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_108 = _GEN[auto_in_a_bits_source] == 7'h6C & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_108 = d_sel_shiftAmount == 7'h6C & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_109 = _GEN[auto_in_a_bits_source] == 7'h6D & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_109 = d_sel_shiftAmount == 7'h6D & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_110 = _GEN[auto_in_a_bits_source] == 7'h6E & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_110 = d_sel_shiftAmount == 7'h6E & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_111 = _GEN[auto_in_a_bits_source] == 7'h6F & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_111 = d_sel_shiftAmount == 7'h6F & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_112 = _GEN[auto_in_a_bits_source] == 7'h70 & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_112 = d_sel_shiftAmount == 7'h70 & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_113 = _GEN[auto_in_a_bits_source] == 7'h71 & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_113 = d_sel_shiftAmount == 7'h71 & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_114 = _GEN[auto_in_a_bits_source] == 7'h72 & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_114 = d_sel_shiftAmount == 7'h72 & d_last & _dec_T_231; // @[OneHot.scala:65:27]
wire inc_115 = _GEN[auto_in_a_bits_source] == 7'h73 & _inc_T_115; // @[OneHot.scala:65:27]
wire dec_115 = d_sel_shiftAmount == 7'h73 & d_last & _dec_T_231; // @[OneHot.scala:65:27] |
Generate the Verilog code corresponding to the following Chisel files.
File PE.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle {
val dataflow = UInt(1.W) // TODO make this an Enum
val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)?
val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats
}
class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module {
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(inputType)
val in_c = Input(cType)
val out_d = Output(dType)
})
io.out_d := io.in_c.mac(io.in_a, io.in_b)
}
// TODO update documentation
/**
* A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh.
* @param width Data width of operands
*/
class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int)
(implicit ev: Arithmetic[T]) extends Module { // Debugging variables
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(outputType)
val in_d = Input(outputType)
val out_a = Output(inputType)
val out_b = Output(outputType)
val out_c = Output(outputType)
val in_control = Input(new PEControl(accType))
val out_control = Output(new PEControl(accType))
val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W))
val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W))
val in_last = Input(Bool())
val out_last = Output(Bool())
val in_valid = Input(Bool())
val out_valid = Output(Bool())
val bad_dataflow = Output(Bool())
})
val cType = if (df == Dataflow.WS) inputType else accType
// When creating PEs that support multiple dataflows, the
// elaboration/synthesis tools often fail to consolidate and de-duplicate
// MAC units. To force mac circuitry to be re-used, we create a "mac_unit"
// module here which just performs a single MAC operation
val mac_unit = Module(new MacUnit(inputType,
if (df == Dataflow.WS) outputType else accType, outputType))
val a = io.in_a
val b = io.in_b
val d = io.in_d
val c1 = Reg(cType)
val c2 = Reg(cType)
val dataflow = io.in_control.dataflow
val prop = io.in_control.propagate
val shift = io.in_control.shift
val id = io.in_id
val last = io.in_last
val valid = io.in_valid
io.out_a := a
io.out_control.dataflow := dataflow
io.out_control.propagate := prop
io.out_control.shift := shift
io.out_id := id
io.out_last := last
io.out_valid := valid
mac_unit.io.in_a := a
val last_s = RegEnable(prop, valid)
val flip = last_s =/= prop
val shift_offset = Mux(flip, shift, 0.U)
// Which dataflow are we using?
val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W)
val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W)
// Is c1 being computed on, or propagated forward (in the output-stationary dataflow)?
val COMPUTE = 0.U(1.W)
val PROPAGATE = 1.U(1.W)
io.bad_dataflow := false.B
when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
c2 := mac_unit.io.out_d
c1 := d.withWidthOf(cType)
}.otherwise {
io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c1
c1 := mac_unit.io.out_d
c2 := d.withWidthOf(cType)
}
}.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := c1
mac_unit.io.in_b := c2.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c1 := d
}.otherwise {
io.out_c := c2
mac_unit.io.in_b := c1.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c2 := d
}
}.otherwise {
io.bad_dataflow := true.B
//assert(false.B, "unknown dataflow")
io.out_c := DontCare
io.out_b := DontCare
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
}
when (!valid) {
c1 := c1
c2 := c2
mac_unit.io.in_b := DontCare
mac_unit.io.in_c := DontCare
}
}
File Arithmetic.scala:
// A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own:
// implicit MyTypeArithmetic extends Arithmetic[MyType] { ... }
package gemmini
import chisel3._
import chisel3.util._
import hardfloat._
// Bundles that represent the raw bits of custom datatypes
case class Float(expWidth: Int, sigWidth: Int) extends Bundle {
val bits = UInt((expWidth + sigWidth).W)
val bias: Int = (1 << (expWidth-1)) - 1
}
case class DummySInt(w: Int) extends Bundle {
val bits = UInt(w.W)
def dontCare: DummySInt = {
val o = Wire(new DummySInt(w))
o.bits := 0.U
o
}
}
// The Arithmetic typeclass which implements various arithmetic operations on custom datatypes
abstract class Arithmetic[T <: Data] {
implicit def cast(t: T): ArithmeticOps[T]
}
abstract class ArithmeticOps[T <: Data](self: T) {
def *(t: T): T
def mac(m1: T, m2: T): T // Returns (m1 * m2 + self)
def +(t: T): T
def -(t: T): T
def >>(u: UInt): T // This is a rounding shift! Rounds away from 0
def >(t: T): Bool
def identity: T
def withWidthOf(t: T): T
def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates
def relu: T
def zero: T
def minimum: T
// Optional parameters, which only need to be defined if you want to enable various optimizations for transformers
def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None
def mult_with_reciprocal[U <: Data](reciprocal: U) = self
}
object Arithmetic {
implicit object UIntArithmetic extends Arithmetic[UInt] {
override implicit def cast(self: UInt) = new ArithmeticOps(self) {
override def *(t: UInt) = self * t
override def mac(m1: UInt, m2: UInt) = m1 * m2 + self
override def +(t: UInt) = self + t
override def -(t: UInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = point_five & (zeros | ones_digit)
(self >> u).asUInt + r
}
override def >(t: UInt): Bool = self > t
override def withWidthOf(t: UInt) = self.asTypeOf(t)
override def clippedToWidthOf(t: UInt) = {
val sat = ((1 << (t.getWidth-1))-1).U
Mux(self > sat, sat, self)(t.getWidth-1, 0)
}
override def relu: UInt = self
override def zero: UInt = 0.U
override def identity: UInt = 1.U
override def minimum: UInt = 0.U
}
}
implicit object SIntArithmetic extends Arithmetic[SInt] {
override implicit def cast(self: SInt) = new ArithmeticOps(self) {
override def *(t: SInt) = self * t
override def mac(m1: SInt, m2: SInt) = m1 * m2 + self
override def +(t: SInt) = self + t
override def -(t: SInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = (point_five & (zeros | ones_digit)).asBool
(self >> u).asSInt + Mux(r, 1.S, 0.S)
}
override def >(t: SInt): Bool = self > t
override def withWidthOf(t: SInt) = {
if (self.getWidth >= t.getWidth)
self(t.getWidth-1, 0).asSInt
else {
val sign_bits = t.getWidth - self.getWidth
val sign = self(self.getWidth-1)
Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t)
}
}
override def clippedToWidthOf(t: SInt): SInt = {
val maxsat = ((1 << (t.getWidth-1))-1).S
val minsat = (-(1 << (t.getWidth-1))).S
MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt
}
override def relu: SInt = Mux(self >= 0.S, self, 0.S)
override def zero: SInt = 0.S
override def identity: SInt = 1.S
override def minimum: SInt = (-(1 << (self.getWidth-1))).S
override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(denom_t.cloneType))
val output = Wire(Decoupled(self.cloneType))
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def sin_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def uin_to_float(x: UInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := x
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = sin_to_float(self)
val denom_rec = uin_to_float(input.bits)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := self_rec
divider.io.b := denom_rec
divider.io.roundingMode := consts.round_minMag
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := float_to_in(divider.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(self.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
// Instantiate the hardloat sqrt
val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0))
input.ready := sqrter.io.inReady
sqrter.io.inValid := input.valid
sqrter.io.sqrtOp := true.B
sqrter.io.a := self_rec
sqrter.io.b := DontCare
sqrter.io.roundingMode := consts.round_minMag
sqrter.io.detectTininess := consts.tininess_afterRounding
output.valid := sqrter.io.outValid_sqrt
output.bits := float_to_in(sqrter.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match {
case Float(expWidth, sigWidth) =>
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(u.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
val self_rec = in_to_float(self)
val one_rec = in_to_float(1.S)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := one_rec
divider.io.b := self_rec
divider.io.roundingMode := consts.round_near_even
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u)
assert(!output.valid || output.ready)
Some((input, output))
case _ => None
}
override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match {
case recip @ Float(expWidth, sigWidth) =>
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits)
// Instantiate the hardloat divider
val muladder = Module(new MulRecFN(expWidth, sigWidth))
muladder.io.roundingMode := consts.round_near_even
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := reciprocal_rec
float_to_in(muladder.io.out)
case _ => self
}
}
}
implicit object FloatArithmetic extends Arithmetic[Float] {
// TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array
override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) {
override def *(t: Float): Float = {
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := t_rec_resized
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def mac(m1: Float, m2: Float): Float = {
// Recode all operands
val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits)
val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize m1 to self's width
val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth))
m1_resizer.io.in := m1_rec
m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m1_resizer.io.detectTininess := consts.tininess_afterRounding
val m1_rec_resized = m1_resizer.io.out
// Resize m2 to self's width
val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth))
m2_resizer.io.in := m2_rec
m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m2_resizer.io.detectTininess := consts.tininess_afterRounding
val m2_rec_resized = m2_resizer.io.out
// Perform multiply-add
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := m1_rec_resized
muladder.io.b := m2_rec_resized
muladder.io.c := self_rec
// Convert result to standard format // TODO remove these intermediate recodings
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def +(t: Float): Float = {
require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Generate 1 as a float
val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := 1.U
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
val one_rec = in_to_rec_fn.io.out
// Resize t
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
// Perform addition
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := t_rec_resized
muladder.io.b := one_rec
muladder.io.c := self_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def -(t: Float): Float = {
val t_sgn = t.bits(t.getWidth-1)
val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t)
self + neg_t
}
override def >>(u: UInt): Float = {
// Recode self
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Get 2^(-u) as a recoded float
val shift_exp = Wire(UInt(self.expWidth.W))
shift_exp := self.bias.U - u
val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W))
val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn)
assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported")
// Multiply self and 2^(-u)
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := shift_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def >(t: Float): Bool = {
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize t to self's width
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth))
comparator.io.a := self_rec
comparator.io.b := t_rec_resized
comparator.io.signaling := false.B
comparator.io.gt
}
override def withWidthOf(t: Float): Float = {
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def clippedToWidthOf(t: Float): Float = {
// TODO check for overflow. Right now, we just assume that overflow doesn't happen
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def relu: Float = {
val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits)
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits)
result
}
override def zero: Float = 0.U.asTypeOf(self)
override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
}
}
implicit object DummySIntArithmetic extends Arithmetic[DummySInt] {
override implicit def cast(self: DummySInt) = new ArithmeticOps(self) {
override def *(t: DummySInt) = self.dontCare
override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare
override def +(t: DummySInt) = self.dontCare
override def -(t: DummySInt) = self.dontCare
override def >>(t: UInt) = self.dontCare
override def >(t: DummySInt): Bool = false.B
override def identity = self.dontCare
override def withWidthOf(t: DummySInt) = self.dontCare
override def clippedToWidthOf(t: DummySInt) = self.dontCare
override def relu = self.dontCare
override def zero = self.dontCare
override def minimum: DummySInt = self.dontCare
}
}
}
| module PE_466( // @[PE.scala:31:7]
input clock, // @[PE.scala:31:7]
input reset, // @[PE.scala:31:7]
input [7:0] io_in_a, // @[PE.scala:35:14]
input [19:0] io_in_b, // @[PE.scala:35:14]
input [19:0] io_in_d, // @[PE.scala:35:14]
output [7:0] io_out_a, // @[PE.scala:35:14]
output [19:0] io_out_b, // @[PE.scala:35:14]
output [19:0] io_out_c, // @[PE.scala:35:14]
input io_in_control_dataflow, // @[PE.scala:35:14]
input io_in_control_propagate, // @[PE.scala:35:14]
input [4:0] io_in_control_shift, // @[PE.scala:35:14]
output io_out_control_dataflow, // @[PE.scala:35:14]
output io_out_control_propagate, // @[PE.scala:35:14]
output [4:0] io_out_control_shift, // @[PE.scala:35:14]
input [2:0] io_in_id, // @[PE.scala:35:14]
output [2:0] io_out_id, // @[PE.scala:35:14]
input io_in_last, // @[PE.scala:35:14]
output io_out_last, // @[PE.scala:35:14]
input io_in_valid, // @[PE.scala:35:14]
output io_out_valid // @[PE.scala:35:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7]
wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7]
wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7]
wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7]
wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7]
wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7]
wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7]
wire io_in_last_0 = io_in_last; // @[PE.scala:31:7]
wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7]
wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7]
wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33]
wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60]
wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33]
wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60]
wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7]
wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37]
wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37]
wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35]
wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7]
wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7]
wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7]
wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7]
wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7]
wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7]
wire [19:0] io_out_b_0; // @[PE.scala:31:7]
wire [19:0] io_out_c_0; // @[PE.scala:31:7]
reg [7:0] c1; // @[PE.scala:70:15]
wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15]
wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38]
reg [7:0] c2; // @[PE.scala:71:15]
wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15]
wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38]
reg last_s; // @[PE.scala:89:25]
wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21]
wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25]
wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25]
wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32]
wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32]
wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25]
wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53]
wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15]
wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}]
wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25]
wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27]
wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27]
wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}]
wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25]
wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15]
wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30]
wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15]
assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33]
wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}]
wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28]
wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28]
wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37]
wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37]
wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7]
wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7]
wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}]
wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53]
wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15]
wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}]
wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}]
wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15]
wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30]
wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15]
assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33]
wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}]
wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28]
wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28]
wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37]
wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37]
wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}]
wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38]
assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38]
wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38]
assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16]
wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38]
assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38]
wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38]
wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35]
wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35]
always @(posedge clock) begin // @[PE.scala:31:7]
if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8]
c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15]
if (~(~io_in_valid_0 | io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8]
c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15]
if (io_in_valid_0) // @[PE.scala:31:7]
last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25]
always @(posedge)
MacUnit_210 mac_unit ( // @[PE.scala:64:24]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0), // @[PE.scala:31:7]
.io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}]
.io_in_c (io_in_b_0), // @[PE.scala:31:7]
.io_out_d (io_out_b_0)
); // @[PE.scala:64:24]
assign io_out_a = io_out_a_0; // @[PE.scala:31:7]
assign io_out_b = io_out_b_0; // @[PE.scala:31:7]
assign io_out_c = io_out_c_0; // @[PE.scala:31:7]
assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7]
assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7]
assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7]
assign io_out_id = io_out_id_0; // @[PE.scala:31:7]
assign io_out_last = io_out_last_0; // @[PE.scala:31:7]
assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
| module AsyncResetSynchronizerShiftReg_w4_d3_i0_29( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input [3:0] io_d, // @[ShiftReg.scala:36:14]
output [3:0] io_q // @[ShiftReg.scala:36:14]
);
wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21]
wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14]
wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7]
wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_1; // @[ShiftReg.scala:48:24]
wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_2; // @[ShiftReg.scala:48:24]
wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_3; // @[ShiftReg.scala:48:24]
wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14]
wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14]
assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14]
assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_266 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_267 output_chain_1 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_2), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_3), // @[SynchronizerReg.scala:87:41]
.io_q (output_1)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_268 output_chain_2 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_4), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_5), // @[SynchronizerReg.scala:87:41]
.io_q (output_2)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_269 output_chain_3 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_6), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_7), // @[SynchronizerReg.scala:87:41]
.io_q (output_3)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
| module AsyncResetSynchronizerShiftReg_w4_d3_i0_25( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input [3:0] io_d, // @[ShiftReg.scala:36:14]
output [3:0] io_q // @[ShiftReg.scala:36:14]
);
wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21]
wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14]
wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7]
wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_1; // @[ShiftReg.scala:48:24]
wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_2; // @[ShiftReg.scala:48:24]
wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_3; // @[ShiftReg.scala:48:24]
wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14]
wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14]
assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14]
assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_239 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_240 output_chain_1 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_2), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_3), // @[SynchronizerReg.scala:87:41]
.io_q (output_1)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_241 output_chain_2 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_4), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_5), // @[SynchronizerReg.scala:87:41]
.io_q (output_2)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_242 output_chain_3 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_6), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_7), // @[SynchronizerReg.scala:87:41]
.io_q (output_3)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Nodes.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection}
case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args))
object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
{
def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo)
def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo)
def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle)
def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle)
def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString)
override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = {
val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge)))
monitor.io.in := bundle
}
override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters =
pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })
override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters =
pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })
}
trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut]
case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode
case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode
case class TLAdapterNode(
clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s },
managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLJunctionNode(
clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters],
managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])(
implicit valName: ValName)
extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode
object TLNameNode {
def apply(name: ValName) = TLIdentityNode()(name)
def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLIdentityNode = apply(Some(name))
}
case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)()
object TLTempNode {
def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp"))
}
case class TLNexusNode(
clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters,
managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)(
implicit valName: ValName)
extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode
abstract class TLCustomNode(implicit valName: ValName)
extends CustomNode(TLImp) with TLFormatNode
// Asynchronous crossings
trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters]
object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle]
{
def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle)
def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString)
override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLAsyncAdapterNode(
clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s },
managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode
case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode
object TLAsyncNameNode {
def apply(name: ValName) = TLAsyncIdentityNode()(name)
def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLAsyncIdentityNode = apply(Some(name))
}
case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLAsyncImp)(
dFn = { p => TLAsyncClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain
case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName)
extends MixedAdapterNode(TLAsyncImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) },
uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut]
// Rationally related crossings
trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters]
object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle]
{
def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle)
def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */)
override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLRationalAdapterNode(
clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s },
managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode
case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode
object TLRationalNameNode {
def apply(name: ValName) = TLRationalIdentityNode()(name)
def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLRationalIdentityNode = apply(Some(name))
}
case class TLRationalSourceNode()(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLRationalImp)(
dFn = { p => TLRationalClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain
case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName)
extends MixedAdapterNode(TLRationalImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut]
// Credited version of TileLink channels
trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters]
object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle]
{
def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle)
def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString)
override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLCreditedAdapterNode(
clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s },
managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode
case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode
object TLCreditedNameNode {
def apply(name: ValName) = TLCreditedIdentityNode()(name)
def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLCreditedIdentityNode = apply(Some(name))
}
case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLCreditedImp)(
dFn = { p => TLCreditedClientPortParameters(delay, p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain
case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLCreditedImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut]
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File TLSerdes.scala:
package testchipip.serdes
import chisel3._
import chisel3.util._
import freechips.rocketchip.diplomacy._
import org.chipsalliance.cde.config._
import freechips.rocketchip.util._
import freechips.rocketchip.tilelink._
object TLSerdesser {
// This should be the standard bundle type for TLSerdesser
val STANDARD_TLBUNDLE_PARAMS = TLBundleParameters(
addressBits=64, dataBits=64,
sourceBits=8, sinkBits=8, sizeBits=8,
echoFields=Nil, requestFields=Nil, responseFields=Nil,
hasBCE=true)
}
class SerdesDebugIO extends Bundle {
val ser_busy = Output(Bool())
val des_busy = Output(Bool())
}
class TLSerdesser(
val flitWidth: Int,
clientPortParams: Option[TLMasterPortParameters],
managerPortParams: Option[TLSlavePortParameters],
val bundleParams: TLBundleParameters = TLSerdesser.STANDARD_TLBUNDLE_PARAMS,
nameSuffix: Option[String] = None
)
(implicit p: Parameters) extends LazyModule {
require (clientPortParams.isDefined || managerPortParams.isDefined)
val clientNode = clientPortParams.map { c => TLClientNode(Seq(c)) }
val managerNode = managerPortParams.map { m => TLManagerNode(Seq(m)) }
override lazy val desiredName = (Seq("TLSerdesser") ++ nameSuffix).mkString("_")
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
val io = IO(new Bundle {
val ser = Vec(5, new DecoupledFlitIO(flitWidth))
val debug = new SerdesDebugIO
})
val client_tl = clientNode.map(_.out(0)._1).getOrElse(0.U.asTypeOf(new TLBundle(bundleParams)))
val client_edge = clientNode.map(_.out(0)._2)
val manager_tl = managerNode.map(_.in(0)._1).getOrElse(0.U.asTypeOf(new TLBundle(bundleParams)))
val manager_edge = managerNode.map(_.in(0)._2)
val clientParams = client_edge.map(_.bundle).getOrElse(bundleParams)
val managerParams = manager_edge.map(_.bundle).getOrElse(bundleParams)
val mergedParams = clientParams.union(managerParams).union(bundleParams)
require(mergedParams.echoFields.isEmpty, "TLSerdesser does not support TileLink with echo fields")
require(mergedParams.requestFields.isEmpty, "TLSerdesser does not support TileLink with request fields")
require(mergedParams.responseFields.isEmpty, "TLSerdesser does not support TileLink with response fields")
require(mergedParams == bundleParams, s"TLSerdesser is misconfigured, the combined inwards/outwards parameters cannot be serialized using the provided bundle params\n$mergedParams > $bundleParams")
val out_channels = Seq(
(manager_tl.e, manager_edge.map(e => Module(new TLEToBeat(e, mergedParams, nameSuffix)))),
(client_tl.d, client_edge.map (e => Module(new TLDToBeat(e, mergedParams, nameSuffix)))),
(manager_tl.c, manager_edge.map(e => Module(new TLCToBeat(e, mergedParams, nameSuffix)))),
(client_tl.b, client_edge.map (e => Module(new TLBToBeat(e, mergedParams, nameSuffix)))),
(manager_tl.a, manager_edge.map(e => Module(new TLAToBeat(e, mergedParams, nameSuffix))))
)
io.ser.map(_.out.valid := false.B)
io.ser.map(_.out.bits := DontCare)
val out_sers = out_channels.zipWithIndex.map { case ((c,b),i) => b.map { b =>
b.io.protocol <> c
val ser = Module(new GenericSerializer(b.io.beat.bits.cloneType, flitWidth)).suggestName(s"ser_$i")
ser.io.in <> b.io.beat
io.ser(i).out <> ser.io.out
ser
}}.flatten
io.debug.ser_busy := out_sers.map(_.io.busy).orR
val in_channels = Seq(
(client_tl.e, Module(new TLEFromBeat(mergedParams, nameSuffix))),
(manager_tl.d, Module(new TLDFromBeat(mergedParams, nameSuffix))),
(client_tl.c, Module(new TLCFromBeat(mergedParams, nameSuffix))),
(manager_tl.b, Module(new TLBFromBeat(mergedParams, nameSuffix))),
(client_tl.a, Module(new TLAFromBeat(mergedParams, nameSuffix)))
)
val in_desers = in_channels.zipWithIndex.map { case ((c,b),i) =>
c <> b.io.protocol
val des = Module(new GenericDeserializer(b.io.beat.bits.cloneType, flitWidth)).suggestName(s"des_$i")
des.io.in <> io.ser(i).in
b.io.beat <> des.io.out
des
}
io.debug.des_busy := in_desers.map(_.io.busy).orR
}
}
| module TLSerdesser_SerialRAM( // @[TLSerdes.scala:39:9]
input clock, // @[TLSerdes.scala:39:9]
input reset, // @[TLSerdes.scala:39:9]
output auto_manager_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_manager_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_manager_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_manager_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_manager_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input auto_manager_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_manager_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_manager_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_manager_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_manager_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_manager_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_manager_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_manager_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_manager_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_manager_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output auto_manager_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_manager_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_manager_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_manager_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_manager_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output io_ser_0_in_ready, // @[TLSerdes.scala:40:16]
input io_ser_0_in_valid, // @[TLSerdes.scala:40:16]
input [31:0] io_ser_0_in_bits_flit, // @[TLSerdes.scala:40:16]
output [31:0] io_ser_0_out_bits_flit, // @[TLSerdes.scala:40:16]
output io_ser_1_in_ready, // @[TLSerdes.scala:40:16]
input io_ser_1_in_valid, // @[TLSerdes.scala:40:16]
input [31:0] io_ser_1_in_bits_flit, // @[TLSerdes.scala:40:16]
output io_ser_2_in_ready, // @[TLSerdes.scala:40:16]
input io_ser_2_in_valid, // @[TLSerdes.scala:40:16]
input [31:0] io_ser_2_in_bits_flit, // @[TLSerdes.scala:40:16]
input io_ser_2_out_ready, // @[TLSerdes.scala:40:16]
output io_ser_2_out_valid, // @[TLSerdes.scala:40:16]
output [31:0] io_ser_2_out_bits_flit, // @[TLSerdes.scala:40:16]
output io_ser_3_in_ready, // @[TLSerdes.scala:40:16]
input io_ser_3_in_valid, // @[TLSerdes.scala:40:16]
input [31:0] io_ser_3_in_bits_flit, // @[TLSerdes.scala:40:16]
output io_ser_4_in_ready, // @[TLSerdes.scala:40:16]
input io_ser_4_in_valid, // @[TLSerdes.scala:40:16]
input [31:0] io_ser_4_in_bits_flit, // @[TLSerdes.scala:40:16]
input io_ser_4_out_ready, // @[TLSerdes.scala:40:16]
output io_ser_4_out_valid, // @[TLSerdes.scala:40:16]
output [31:0] io_ser_4_out_bits_flit // @[TLSerdes.scala:40:16]
);
wire _des_4_io_out_valid; // @[TLSerdes.scala:86:23]
wire _des_4_io_out_bits_head; // @[TLSerdes.scala:86:23]
wire _des_4_io_out_bits_tail; // @[TLSerdes.scala:86:23]
wire _des_3_io_out_valid; // @[TLSerdes.scala:86:23]
wire _des_3_io_out_bits_head; // @[TLSerdes.scala:86:23]
wire _des_3_io_out_bits_tail; // @[TLSerdes.scala:86:23]
wire _des_2_io_out_valid; // @[TLSerdes.scala:86:23]
wire _des_2_io_out_bits_head; // @[TLSerdes.scala:86:23]
wire _des_2_io_out_bits_tail; // @[TLSerdes.scala:86:23]
wire _des_1_io_out_valid; // @[TLSerdes.scala:86:23]
wire [64:0] _des_1_io_out_bits_payload; // @[TLSerdes.scala:86:23]
wire _des_1_io_out_bits_head; // @[TLSerdes.scala:86:23]
wire _des_1_io_out_bits_tail; // @[TLSerdes.scala:86:23]
wire _des_0_io_out_valid; // @[TLSerdes.scala:86:23]
wire _des_0_io_out_bits_head; // @[TLSerdes.scala:86:23]
wire _des_0_io_out_bits_tail; // @[TLSerdes.scala:86:23]
wire _in_channels_4_2_io_beat_ready; // @[TLSerdes.scala:82:28]
wire _in_channels_3_2_io_beat_ready; // @[TLSerdes.scala:81:28]
wire _in_channels_2_2_io_beat_ready; // @[TLSerdes.scala:80:28]
wire _in_channels_1_2_io_protocol_valid; // @[TLSerdes.scala:79:28]
wire [2:0] _in_channels_1_2_io_protocol_bits_opcode; // @[TLSerdes.scala:79:28]
wire [1:0] _in_channels_1_2_io_protocol_bits_param; // @[TLSerdes.scala:79:28]
wire [7:0] _in_channels_1_2_io_protocol_bits_size; // @[TLSerdes.scala:79:28]
wire [7:0] _in_channels_1_2_io_protocol_bits_source; // @[TLSerdes.scala:79:28]
wire [7:0] _in_channels_1_2_io_protocol_bits_sink; // @[TLSerdes.scala:79:28]
wire _in_channels_1_2_io_protocol_bits_denied; // @[TLSerdes.scala:79:28]
wire _in_channels_1_2_io_protocol_bits_corrupt; // @[TLSerdes.scala:79:28]
wire _in_channels_1_2_io_beat_ready; // @[TLSerdes.scala:79:28]
wire _in_channels_0_2_io_beat_ready; // @[TLSerdes.scala:78:28]
wire _ser_4_io_in_ready; // @[TLSerdes.scala:69:23]
wire _out_channels_4_2_io_protocol_ready; // @[TLSerdes.scala:63:50]
wire _out_channels_4_2_io_beat_valid; // @[TLSerdes.scala:63:50]
wire [85:0] _out_channels_4_2_io_beat_bits_payload; // @[TLSerdes.scala:63:50]
wire _out_channels_4_2_io_beat_bits_head; // @[TLSerdes.scala:63:50]
wire _out_channels_4_2_io_beat_bits_tail; // @[TLSerdes.scala:63:50]
wire _out_channels_2_2_io_beat_bits_head; // @[TLSerdes.scala:61:50]
wire _out_channels_0_2_io_beat_bits_head; // @[TLSerdes.scala:59:50]
TLMonitor_64 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (_out_channels_4_2_io_protocol_ready), // @[TLSerdes.scala:63:50]
.io_in_a_valid (auto_manager_in_a_valid),
.io_in_a_bits_opcode (auto_manager_in_a_bits_opcode),
.io_in_a_bits_param (auto_manager_in_a_bits_param),
.io_in_a_bits_size (auto_manager_in_a_bits_size),
.io_in_a_bits_source (auto_manager_in_a_bits_source),
.io_in_a_bits_address (auto_manager_in_a_bits_address),
.io_in_a_bits_mask (auto_manager_in_a_bits_mask),
.io_in_a_bits_corrupt (auto_manager_in_a_bits_corrupt),
.io_in_d_ready (auto_manager_in_d_ready),
.io_in_d_valid (_in_channels_1_2_io_protocol_valid), // @[TLSerdes.scala:79:28]
.io_in_d_bits_opcode (_in_channels_1_2_io_protocol_bits_opcode), // @[TLSerdes.scala:79:28]
.io_in_d_bits_param (_in_channels_1_2_io_protocol_bits_param), // @[TLSerdes.scala:79:28]
.io_in_d_bits_size (_in_channels_1_2_io_protocol_bits_size[3:0]), // @[TLSerdes.scala:79:28, :85:9]
.io_in_d_bits_source (_in_channels_1_2_io_protocol_bits_source[0]), // @[TLSerdes.scala:79:28, :85:9]
.io_in_d_bits_sink (_in_channels_1_2_io_protocol_bits_sink[2:0]), // @[TLSerdes.scala:79:28, :85:9]
.io_in_d_bits_denied (_in_channels_1_2_io_protocol_bits_denied), // @[TLSerdes.scala:79:28]
.io_in_d_bits_corrupt (_in_channels_1_2_io_protocol_bits_corrupt) // @[TLSerdes.scala:79:28]
); // @[Nodes.scala:27:25]
TLEToBeat_SerialRAM_a64d64s8k8z8c out_channels_0_2 ( // @[TLSerdes.scala:59:50]
.clock (clock),
.reset (reset),
.io_beat_bits_head (_out_channels_0_2_io_beat_bits_head)
); // @[TLSerdes.scala:59:50]
TLCToBeat_SerialRAM_a64d64s8k8z8c out_channels_2_2 ( // @[TLSerdes.scala:61:50]
.clock (clock),
.reset (reset),
.io_beat_bits_head (_out_channels_2_2_io_beat_bits_head)
); // @[TLSerdes.scala:61:50]
TLAToBeat_SerialRAM_a64d64s8k8z8c out_channels_4_2 ( // @[TLSerdes.scala:63:50]
.clock (clock),
.reset (reset),
.io_protocol_ready (_out_channels_4_2_io_protocol_ready),
.io_protocol_valid (auto_manager_in_a_valid),
.io_protocol_bits_opcode (auto_manager_in_a_bits_opcode),
.io_protocol_bits_param (auto_manager_in_a_bits_param),
.io_protocol_bits_size ({4'h0, auto_manager_in_a_bits_size}), // @[TLSerdes.scala:68:21]
.io_protocol_bits_source ({7'h0, auto_manager_in_a_bits_source}), // @[TLSerdes.scala:68:21]
.io_protocol_bits_address ({32'h0, auto_manager_in_a_bits_address}), // @[TLSerdes.scala:68:21]
.io_protocol_bits_mask (auto_manager_in_a_bits_mask),
.io_protocol_bits_data (auto_manager_in_a_bits_data),
.io_protocol_bits_corrupt (auto_manager_in_a_bits_corrupt),
.io_beat_ready (_ser_4_io_in_ready), // @[TLSerdes.scala:69:23]
.io_beat_valid (_out_channels_4_2_io_beat_valid),
.io_beat_bits_payload (_out_channels_4_2_io_beat_bits_payload),
.io_beat_bits_head (_out_channels_4_2_io_beat_bits_head),
.io_beat_bits_tail (_out_channels_4_2_io_beat_bits_tail)
); // @[TLSerdes.scala:63:50]
GenericSerializer_TLBeatw10_f32 ser_0 ( // @[TLSerdes.scala:69:23]
.io_in_bits_head (_out_channels_0_2_io_beat_bits_head), // @[TLSerdes.scala:59:50]
.io_out_bits_flit (io_ser_0_out_bits_flit)
); // @[TLSerdes.scala:69:23]
GenericSerializer_TLBeatw88_f32 ser_2 ( // @[TLSerdes.scala:69:23]
.clock (clock),
.reset (reset),
.io_in_ready (/* unused */),
.io_in_valid (1'h0), // @[TLSerdes.scala:39:9, :40:16, :59:50, :61:50, :69:23]
.io_in_bits_payload (86'h0), // @[TLSerdes.scala:61:50, :69:23]
.io_in_bits_head (_out_channels_2_2_io_beat_bits_head), // @[TLSerdes.scala:61:50]
.io_in_bits_tail (1'h1), // @[TLSerdes.scala:59:50, :61:50, :69:23]
.io_out_ready (io_ser_2_out_ready),
.io_out_valid (io_ser_2_out_valid),
.io_out_bits_flit (io_ser_2_out_bits_flit)
); // @[TLSerdes.scala:69:23]
GenericSerializer_TLBeatw88_f32 ser_4 ( // @[TLSerdes.scala:69:23]
.clock (clock),
.reset (reset),
.io_in_ready (_ser_4_io_in_ready),
.io_in_valid (_out_channels_4_2_io_beat_valid), // @[TLSerdes.scala:63:50]
.io_in_bits_payload (_out_channels_4_2_io_beat_bits_payload), // @[TLSerdes.scala:63:50]
.io_in_bits_head (_out_channels_4_2_io_beat_bits_head), // @[TLSerdes.scala:63:50]
.io_in_bits_tail (_out_channels_4_2_io_beat_bits_tail), // @[TLSerdes.scala:63:50]
.io_out_ready (io_ser_4_out_ready),
.io_out_valid (io_ser_4_out_valid),
.io_out_bits_flit (io_ser_4_out_bits_flit)
); // @[TLSerdes.scala:69:23]
TLEFromBeat_SerialRAM_a64d64s8k8z8c in_channels_0_2 ( // @[TLSerdes.scala:78:28]
.clock (clock),
.reset (reset),
.io_beat_ready (_in_channels_0_2_io_beat_ready),
.io_beat_valid (_des_0_io_out_valid), // @[TLSerdes.scala:86:23]
.io_beat_bits_head (_des_0_io_out_bits_head), // @[TLSerdes.scala:86:23]
.io_beat_bits_tail (_des_0_io_out_bits_tail) // @[TLSerdes.scala:86:23]
); // @[TLSerdes.scala:78:28]
TLDFromBeat_SerialRAM_a64d64s8k8z8c in_channels_1_2 ( // @[TLSerdes.scala:79:28]
.clock (clock),
.reset (reset),
.io_protocol_ready (auto_manager_in_d_ready),
.io_protocol_valid (_in_channels_1_2_io_protocol_valid),
.io_protocol_bits_opcode (_in_channels_1_2_io_protocol_bits_opcode),
.io_protocol_bits_param (_in_channels_1_2_io_protocol_bits_param),
.io_protocol_bits_size (_in_channels_1_2_io_protocol_bits_size),
.io_protocol_bits_source (_in_channels_1_2_io_protocol_bits_source),
.io_protocol_bits_sink (_in_channels_1_2_io_protocol_bits_sink),
.io_protocol_bits_denied (_in_channels_1_2_io_protocol_bits_denied),
.io_protocol_bits_data (auto_manager_in_d_bits_data),
.io_protocol_bits_corrupt (_in_channels_1_2_io_protocol_bits_corrupt),
.io_beat_ready (_in_channels_1_2_io_beat_ready),
.io_beat_valid (_des_1_io_out_valid), // @[TLSerdes.scala:86:23]
.io_beat_bits_payload (_des_1_io_out_bits_payload), // @[TLSerdes.scala:86:23]
.io_beat_bits_head (_des_1_io_out_bits_head), // @[TLSerdes.scala:86:23]
.io_beat_bits_tail (_des_1_io_out_bits_tail) // @[TLSerdes.scala:86:23]
); // @[TLSerdes.scala:79:28]
TLCFromBeat_SerialRAM_a64d64s8k8z8c in_channels_2_2 ( // @[TLSerdes.scala:80:28]
.clock (clock),
.reset (reset),
.io_beat_ready (_in_channels_2_2_io_beat_ready),
.io_beat_valid (_des_2_io_out_valid), // @[TLSerdes.scala:86:23]
.io_beat_bits_head (_des_2_io_out_bits_head), // @[TLSerdes.scala:86:23]
.io_beat_bits_tail (_des_2_io_out_bits_tail) // @[TLSerdes.scala:86:23]
); // @[TLSerdes.scala:80:28]
TLBFromBeat_SerialRAM_a64d64s8k8z8c in_channels_3_2 ( // @[TLSerdes.scala:81:28]
.clock (clock),
.reset (reset),
.io_beat_ready (_in_channels_3_2_io_beat_ready),
.io_beat_valid (_des_3_io_out_valid), // @[TLSerdes.scala:86:23]
.io_beat_bits_head (_des_3_io_out_bits_head), // @[TLSerdes.scala:86:23]
.io_beat_bits_tail (_des_3_io_out_bits_tail) // @[TLSerdes.scala:86:23]
); // @[TLSerdes.scala:81:28]
TLAFromBeat_SerialRAM_a64d64s8k8z8c in_channels_4_2 ( // @[TLSerdes.scala:82:28]
.clock (clock),
.reset (reset),
.io_beat_ready (_in_channels_4_2_io_beat_ready),
.io_beat_valid (_des_4_io_out_valid), // @[TLSerdes.scala:86:23]
.io_beat_bits_head (_des_4_io_out_bits_head), // @[TLSerdes.scala:86:23]
.io_beat_bits_tail (_des_4_io_out_bits_tail) // @[TLSerdes.scala:86:23]
); // @[TLSerdes.scala:82:28]
GenericDeserializer_TLBeatw10_f32 des_0 ( // @[TLSerdes.scala:86:23]
.io_in_ready (io_ser_0_in_ready),
.io_in_valid (io_ser_0_in_valid),
.io_in_bits_flit (io_ser_0_in_bits_flit),
.io_out_ready (_in_channels_0_2_io_beat_ready), // @[TLSerdes.scala:78:28]
.io_out_valid (_des_0_io_out_valid),
.io_out_bits_head (_des_0_io_out_bits_head),
.io_out_bits_tail (_des_0_io_out_bits_tail)
); // @[TLSerdes.scala:86:23]
GenericDeserializer_TLBeatw67_f32 des_1 ( // @[TLSerdes.scala:86:23]
.clock (clock),
.reset (reset),
.io_in_ready (io_ser_1_in_ready),
.io_in_valid (io_ser_1_in_valid),
.io_in_bits_flit (io_ser_1_in_bits_flit),
.io_out_ready (_in_channels_1_2_io_beat_ready), // @[TLSerdes.scala:79:28]
.io_out_valid (_des_1_io_out_valid),
.io_out_bits_payload (_des_1_io_out_bits_payload),
.io_out_bits_head (_des_1_io_out_bits_head),
.io_out_bits_tail (_des_1_io_out_bits_tail)
); // @[TLSerdes.scala:86:23]
GenericDeserializer_TLBeatw88_f32 des_2 ( // @[TLSerdes.scala:86:23]
.clock (clock),
.reset (reset),
.io_in_ready (io_ser_2_in_ready),
.io_in_valid (io_ser_2_in_valid),
.io_in_bits_flit (io_ser_2_in_bits_flit),
.io_out_ready (_in_channels_2_2_io_beat_ready), // @[TLSerdes.scala:80:28]
.io_out_valid (_des_2_io_out_valid),
.io_out_bits_payload (/* unused */),
.io_out_bits_head (_des_2_io_out_bits_head),
.io_out_bits_tail (_des_2_io_out_bits_tail)
); // @[TLSerdes.scala:86:23]
GenericDeserializer_TLBeatw87_f32 des_3 ( // @[TLSerdes.scala:86:23]
.clock (clock),
.reset (reset),
.io_in_ready (io_ser_3_in_ready),
.io_in_valid (io_ser_3_in_valid),
.io_in_bits_flit (io_ser_3_in_bits_flit),
.io_out_ready (_in_channels_3_2_io_beat_ready), // @[TLSerdes.scala:81:28]
.io_out_valid (_des_3_io_out_valid),
.io_out_bits_head (_des_3_io_out_bits_head),
.io_out_bits_tail (_des_3_io_out_bits_tail)
); // @[TLSerdes.scala:86:23]
GenericDeserializer_TLBeatw88_f32 des_4 ( // @[TLSerdes.scala:86:23]
.clock (clock),
.reset (reset),
.io_in_ready (io_ser_4_in_ready),
.io_in_valid (io_ser_4_in_valid),
.io_in_bits_flit (io_ser_4_in_bits_flit),
.io_out_ready (_in_channels_4_2_io_beat_ready), // @[TLSerdes.scala:82:28]
.io_out_valid (_des_4_io_out_valid),
.io_out_bits_payload (/* unused */),
.io_out_bits_head (_des_4_io_out_bits_head),
.io_out_bits_tail (_des_4_io_out_bits_tail)
); // @[TLSerdes.scala:86:23]
assign auto_manager_in_a_ready = _out_channels_4_2_io_protocol_ready; // @[TLSerdes.scala:39:9, :63:50]
assign auto_manager_in_d_valid = _in_channels_1_2_io_protocol_valid; // @[TLSerdes.scala:39:9, :79:28]
assign auto_manager_in_d_bits_opcode = _in_channels_1_2_io_protocol_bits_opcode; // @[TLSerdes.scala:39:9, :79:28]
assign auto_manager_in_d_bits_param = _in_channels_1_2_io_protocol_bits_param; // @[TLSerdes.scala:39:9, :79:28]
assign auto_manager_in_d_bits_size = _in_channels_1_2_io_protocol_bits_size[3:0]; // @[TLSerdes.scala:39:9, :79:28, :85:9]
assign auto_manager_in_d_bits_source = _in_channels_1_2_io_protocol_bits_source[0]; // @[TLSerdes.scala:39:9, :79:28, :85:9]
assign auto_manager_in_d_bits_sink = _in_channels_1_2_io_protocol_bits_sink[2:0]; // @[TLSerdes.scala:39:9, :79:28, :85:9]
assign auto_manager_in_d_bits_denied = _in_channels_1_2_io_protocol_bits_denied; // @[TLSerdes.scala:39:9, :79:28]
assign auto_manager_in_d_bits_corrupt = _in_channels_1_2_io_protocol_bits_corrupt; // @[TLSerdes.scala:39:9, :79:28]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File PE.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle {
val dataflow = UInt(1.W) // TODO make this an Enum
val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)?
val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats
}
class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module {
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(inputType)
val in_c = Input(cType)
val out_d = Output(dType)
})
io.out_d := io.in_c.mac(io.in_a, io.in_b)
}
// TODO update documentation
/**
* A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh.
* @param width Data width of operands
*/
class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int)
(implicit ev: Arithmetic[T]) extends Module { // Debugging variables
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(outputType)
val in_d = Input(outputType)
val out_a = Output(inputType)
val out_b = Output(outputType)
val out_c = Output(outputType)
val in_control = Input(new PEControl(accType))
val out_control = Output(new PEControl(accType))
val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W))
val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W))
val in_last = Input(Bool())
val out_last = Output(Bool())
val in_valid = Input(Bool())
val out_valid = Output(Bool())
val bad_dataflow = Output(Bool())
})
val cType = if (df == Dataflow.WS) inputType else accType
// When creating PEs that support multiple dataflows, the
// elaboration/synthesis tools often fail to consolidate and de-duplicate
// MAC units. To force mac circuitry to be re-used, we create a "mac_unit"
// module here which just performs a single MAC operation
val mac_unit = Module(new MacUnit(inputType,
if (df == Dataflow.WS) outputType else accType, outputType))
val a = io.in_a
val b = io.in_b
val d = io.in_d
val c1 = Reg(cType)
val c2 = Reg(cType)
val dataflow = io.in_control.dataflow
val prop = io.in_control.propagate
val shift = io.in_control.shift
val id = io.in_id
val last = io.in_last
val valid = io.in_valid
io.out_a := a
io.out_control.dataflow := dataflow
io.out_control.propagate := prop
io.out_control.shift := shift
io.out_id := id
io.out_last := last
io.out_valid := valid
mac_unit.io.in_a := a
val last_s = RegEnable(prop, valid)
val flip = last_s =/= prop
val shift_offset = Mux(flip, shift, 0.U)
// Which dataflow are we using?
val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W)
val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W)
// Is c1 being computed on, or propagated forward (in the output-stationary dataflow)?
val COMPUTE = 0.U(1.W)
val PROPAGATE = 1.U(1.W)
io.bad_dataflow := false.B
when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
c2 := mac_unit.io.out_d
c1 := d.withWidthOf(cType)
}.otherwise {
io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c1
c1 := mac_unit.io.out_d
c2 := d.withWidthOf(cType)
}
}.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := c1
mac_unit.io.in_b := c2.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c1 := d
}.otherwise {
io.out_c := c2
mac_unit.io.in_b := c1.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c2 := d
}
}.otherwise {
io.bad_dataflow := true.B
//assert(false.B, "unknown dataflow")
io.out_c := DontCare
io.out_b := DontCare
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
}
when (!valid) {
c1 := c1
c2 := c2
mac_unit.io.in_b := DontCare
mac_unit.io.in_c := DontCare
}
}
File Arithmetic.scala:
// A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own:
// implicit MyTypeArithmetic extends Arithmetic[MyType] { ... }
package gemmini
import chisel3._
import chisel3.util._
import hardfloat._
// Bundles that represent the raw bits of custom datatypes
case class Float(expWidth: Int, sigWidth: Int) extends Bundle {
val bits = UInt((expWidth + sigWidth).W)
val bias: Int = (1 << (expWidth-1)) - 1
}
case class DummySInt(w: Int) extends Bundle {
val bits = UInt(w.W)
def dontCare: DummySInt = {
val o = Wire(new DummySInt(w))
o.bits := 0.U
o
}
}
// The Arithmetic typeclass which implements various arithmetic operations on custom datatypes
abstract class Arithmetic[T <: Data] {
implicit def cast(t: T): ArithmeticOps[T]
}
abstract class ArithmeticOps[T <: Data](self: T) {
def *(t: T): T
def mac(m1: T, m2: T): T // Returns (m1 * m2 + self)
def +(t: T): T
def -(t: T): T
def >>(u: UInt): T // This is a rounding shift! Rounds away from 0
def >(t: T): Bool
def identity: T
def withWidthOf(t: T): T
def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates
def relu: T
def zero: T
def minimum: T
// Optional parameters, which only need to be defined if you want to enable various optimizations for transformers
def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None
def mult_with_reciprocal[U <: Data](reciprocal: U) = self
}
object Arithmetic {
implicit object UIntArithmetic extends Arithmetic[UInt] {
override implicit def cast(self: UInt) = new ArithmeticOps(self) {
override def *(t: UInt) = self * t
override def mac(m1: UInt, m2: UInt) = m1 * m2 + self
override def +(t: UInt) = self + t
override def -(t: UInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = point_five & (zeros | ones_digit)
(self >> u).asUInt + r
}
override def >(t: UInt): Bool = self > t
override def withWidthOf(t: UInt) = self.asTypeOf(t)
override def clippedToWidthOf(t: UInt) = {
val sat = ((1 << (t.getWidth-1))-1).U
Mux(self > sat, sat, self)(t.getWidth-1, 0)
}
override def relu: UInt = self
override def zero: UInt = 0.U
override def identity: UInt = 1.U
override def minimum: UInt = 0.U
}
}
implicit object SIntArithmetic extends Arithmetic[SInt] {
override implicit def cast(self: SInt) = new ArithmeticOps(self) {
override def *(t: SInt) = self * t
override def mac(m1: SInt, m2: SInt) = m1 * m2 + self
override def +(t: SInt) = self + t
override def -(t: SInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = (point_five & (zeros | ones_digit)).asBool
(self >> u).asSInt + Mux(r, 1.S, 0.S)
}
override def >(t: SInt): Bool = self > t
override def withWidthOf(t: SInt) = {
if (self.getWidth >= t.getWidth)
self(t.getWidth-1, 0).asSInt
else {
val sign_bits = t.getWidth - self.getWidth
val sign = self(self.getWidth-1)
Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t)
}
}
override def clippedToWidthOf(t: SInt): SInt = {
val maxsat = ((1 << (t.getWidth-1))-1).S
val minsat = (-(1 << (t.getWidth-1))).S
MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt
}
override def relu: SInt = Mux(self >= 0.S, self, 0.S)
override def zero: SInt = 0.S
override def identity: SInt = 1.S
override def minimum: SInt = (-(1 << (self.getWidth-1))).S
override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(denom_t.cloneType))
val output = Wire(Decoupled(self.cloneType))
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def sin_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def uin_to_float(x: UInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := x
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = sin_to_float(self)
val denom_rec = uin_to_float(input.bits)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := self_rec
divider.io.b := denom_rec
divider.io.roundingMode := consts.round_minMag
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := float_to_in(divider.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(self.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
// Instantiate the hardloat sqrt
val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0))
input.ready := sqrter.io.inReady
sqrter.io.inValid := input.valid
sqrter.io.sqrtOp := true.B
sqrter.io.a := self_rec
sqrter.io.b := DontCare
sqrter.io.roundingMode := consts.round_minMag
sqrter.io.detectTininess := consts.tininess_afterRounding
output.valid := sqrter.io.outValid_sqrt
output.bits := float_to_in(sqrter.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match {
case Float(expWidth, sigWidth) =>
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(u.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
val self_rec = in_to_float(self)
val one_rec = in_to_float(1.S)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := one_rec
divider.io.b := self_rec
divider.io.roundingMode := consts.round_near_even
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u)
assert(!output.valid || output.ready)
Some((input, output))
case _ => None
}
override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match {
case recip @ Float(expWidth, sigWidth) =>
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits)
// Instantiate the hardloat divider
val muladder = Module(new MulRecFN(expWidth, sigWidth))
muladder.io.roundingMode := consts.round_near_even
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := reciprocal_rec
float_to_in(muladder.io.out)
case _ => self
}
}
}
implicit object FloatArithmetic extends Arithmetic[Float] {
// TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array
override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) {
override def *(t: Float): Float = {
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := t_rec_resized
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def mac(m1: Float, m2: Float): Float = {
// Recode all operands
val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits)
val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize m1 to self's width
val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth))
m1_resizer.io.in := m1_rec
m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m1_resizer.io.detectTininess := consts.tininess_afterRounding
val m1_rec_resized = m1_resizer.io.out
// Resize m2 to self's width
val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth))
m2_resizer.io.in := m2_rec
m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m2_resizer.io.detectTininess := consts.tininess_afterRounding
val m2_rec_resized = m2_resizer.io.out
// Perform multiply-add
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := m1_rec_resized
muladder.io.b := m2_rec_resized
muladder.io.c := self_rec
// Convert result to standard format // TODO remove these intermediate recodings
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def +(t: Float): Float = {
require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Generate 1 as a float
val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := 1.U
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
val one_rec = in_to_rec_fn.io.out
// Resize t
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
// Perform addition
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := t_rec_resized
muladder.io.b := one_rec
muladder.io.c := self_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def -(t: Float): Float = {
val t_sgn = t.bits(t.getWidth-1)
val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t)
self + neg_t
}
override def >>(u: UInt): Float = {
// Recode self
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Get 2^(-u) as a recoded float
val shift_exp = Wire(UInt(self.expWidth.W))
shift_exp := self.bias.U - u
val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W))
val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn)
assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported")
// Multiply self and 2^(-u)
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := shift_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def >(t: Float): Bool = {
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize t to self's width
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth))
comparator.io.a := self_rec
comparator.io.b := t_rec_resized
comparator.io.signaling := false.B
comparator.io.gt
}
override def withWidthOf(t: Float): Float = {
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def clippedToWidthOf(t: Float): Float = {
// TODO check for overflow. Right now, we just assume that overflow doesn't happen
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def relu: Float = {
val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits)
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits)
result
}
override def zero: Float = 0.U.asTypeOf(self)
override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
}
}
implicit object DummySIntArithmetic extends Arithmetic[DummySInt] {
override implicit def cast(self: DummySInt) = new ArithmeticOps(self) {
override def *(t: DummySInt) = self.dontCare
override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare
override def +(t: DummySInt) = self.dontCare
override def -(t: DummySInt) = self.dontCare
override def >>(t: UInt) = self.dontCare
override def >(t: DummySInt): Bool = false.B
override def identity = self.dontCare
override def withWidthOf(t: DummySInt) = self.dontCare
override def clippedToWidthOf(t: DummySInt) = self.dontCare
override def relu = self.dontCare
override def zero = self.dontCare
override def minimum: DummySInt = self.dontCare
}
}
}
| module MacUnit_35( // @[PE.scala:14:7]
input clock, // @[PE.scala:14:7]
input reset, // @[PE.scala:14:7]
input [7:0] io_in_a, // @[PE.scala:16:14]
input [7:0] io_in_b, // @[PE.scala:16:14]
input [19:0] io_in_c, // @[PE.scala:16:14]
output [19:0] io_out_d // @[PE.scala:16:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7]
wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7]
wire [19:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7]
wire [19:0] _io_out_d_T_3; // @[Arithmetic.scala:93:54]
wire [19:0] io_out_d_0; // @[PE.scala:14:7]
wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7]
wire [20:0] _io_out_d_T_1 = {{5{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[19], io_in_c_0}; // @[PE.scala:14:7]
wire [19:0] _io_out_d_T_2 = _io_out_d_T_1[19:0]; // @[Arithmetic.scala:93:54]
assign _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54]
assign io_out_d_0 = _io_out_d_T_3; // @[PE.scala:14:7]
assign io_out_d = io_out_d_0; // @[PE.scala:14:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Tile.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
import Util._
/**
* A Tile is a purely combinational 2D array of passThrough PEs.
* a, b, s, and in_propag are broadcast across the entire array and are passed through to the Tile's outputs
* @param width The data width of each PE in bits
* @param rows Number of PEs on each row
* @param columns Number of PEs on each column
*/
class Tile[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, tree_reduction: Boolean, max_simultaneous_matmuls: Int, val rows: Int, val columns: Int)(implicit ev: Arithmetic[T]) extends Module {
val io = IO(new Bundle {
val in_a = Input(Vec(rows, inputType))
val in_b = Input(Vec(columns, outputType)) // This is the output of the tile next to it
val in_d = Input(Vec(columns, outputType))
val in_control = Input(Vec(columns, new PEControl(accType)))
val in_id = Input(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W)))
val in_last = Input(Vec(columns, Bool()))
val out_a = Output(Vec(rows, inputType))
val out_c = Output(Vec(columns, outputType))
val out_b = Output(Vec(columns, outputType))
val out_control = Output(Vec(columns, new PEControl(accType)))
val out_id = Output(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W)))
val out_last = Output(Vec(columns, Bool()))
val in_valid = Input(Vec(columns, Bool()))
val out_valid = Output(Vec(columns, Bool()))
val bad_dataflow = Output(Bool())
})
import ev._
val tile = Seq.fill(rows, columns)(Module(new PE(inputType, outputType, accType, df, max_simultaneous_matmuls)))
val tileT = tile.transpose
// TODO: abstract hori/vert broadcast, all these connections look the same
// Broadcast 'a' horizontally across the Tile
for (r <- 0 until rows) {
tile(r).foldLeft(io.in_a(r)) {
case (in_a, pe) =>
pe.io.in_a := in_a
pe.io.out_a
}
}
// Broadcast 'b' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_b(c)) {
case (in_b, pe) =>
pe.io.in_b := (if (tree_reduction) in_b.zero else in_b)
pe.io.out_b
}
}
// Broadcast 'd' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_d(c)) {
case (in_d, pe) =>
pe.io.in_d := in_d
pe.io.out_c
}
}
// Broadcast 'control' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_control(c)) {
case (in_ctrl, pe) =>
pe.io.in_control := in_ctrl
pe.io.out_control
}
}
// Broadcast 'garbage' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_valid(c)) {
case (v, pe) =>
pe.io.in_valid := v
pe.io.out_valid
}
}
// Broadcast 'id' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_id(c)) {
case (id, pe) =>
pe.io.in_id := id
pe.io.out_id
}
}
// Broadcast 'last' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_last(c)) {
case (last, pe) =>
pe.io.in_last := last
pe.io.out_last
}
}
// Drive the Tile's bottom IO
for (c <- 0 until columns) {
io.out_c(c) := tile(rows-1)(c).io.out_c
io.out_control(c) := tile(rows-1)(c).io.out_control
io.out_id(c) := tile(rows-1)(c).io.out_id
io.out_last(c) := tile(rows-1)(c).io.out_last
io.out_valid(c) := tile(rows-1)(c).io.out_valid
io.out_b(c) := {
if (tree_reduction) {
val prods = tileT(c).map(_.io.out_b)
accumulateTree(prods :+ io.in_b(c))
} else {
tile(rows - 1)(c).io.out_b
}
}
}
io.bad_dataflow := tile.map(_.map(_.io.bad_dataflow).reduce(_||_)).reduce(_||_)
// Drive the Tile's right IO
for (r <- 0 until rows) {
io.out_a(r) := tile(r)(columns-1).io.out_a
}
}
| module Tile_65( // @[Tile.scala:16:7]
input clock, // @[Tile.scala:16:7]
input reset, // @[Tile.scala:16:7]
input [7:0] io_in_a_0, // @[Tile.scala:17:14]
input [19:0] io_in_b_0, // @[Tile.scala:17:14]
input [19:0] io_in_d_0, // @[Tile.scala:17:14]
input io_in_control_0_dataflow, // @[Tile.scala:17:14]
input io_in_control_0_propagate, // @[Tile.scala:17:14]
input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14]
input [2:0] io_in_id_0, // @[Tile.scala:17:14]
input io_in_last_0, // @[Tile.scala:17:14]
output [7:0] io_out_a_0, // @[Tile.scala:17:14]
output [19:0] io_out_c_0, // @[Tile.scala:17:14]
output [19:0] io_out_b_0, // @[Tile.scala:17:14]
output io_out_control_0_dataflow, // @[Tile.scala:17:14]
output io_out_control_0_propagate, // @[Tile.scala:17:14]
output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14]
output [2:0] io_out_id_0, // @[Tile.scala:17:14]
output io_out_last_0, // @[Tile.scala:17:14]
input io_in_valid_0, // @[Tile.scala:17:14]
output io_out_valid_0, // @[Tile.scala:17:14]
output io_bad_dataflow // @[Tile.scala:17:14]
);
wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7]
wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7]
wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7]
wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7]
wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7]
wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7]
wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7]
wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7]
wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7]
wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7]
wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
wire io_out_control_0_propagate_0; // @[Tile.scala:16:7]
wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7]
wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7]
wire io_out_last_0_0; // @[Tile.scala:16:7]
wire io_out_valid_0_0; // @[Tile.scala:16:7]
wire io_bad_dataflow_0; // @[Tile.scala:16:7]
PE_321 tile_0_0 ( // @[Tile.scala:42:44]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0_0), // @[Tile.scala:16:7]
.io_in_b (io_in_b_0_0), // @[Tile.scala:16:7]
.io_in_d (io_in_d_0_0), // @[Tile.scala:16:7]
.io_out_a (io_out_a_0_0),
.io_out_b (io_out_b_0_0),
.io_out_c (io_out_c_0_0),
.io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7]
.io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7]
.io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7]
.io_out_control_dataflow (io_out_control_0_dataflow_0),
.io_out_control_propagate (io_out_control_0_propagate_0),
.io_out_control_shift (io_out_control_0_shift_0),
.io_in_id (io_in_id_0_0), // @[Tile.scala:16:7]
.io_out_id (io_out_id_0_0),
.io_in_last (io_in_last_0_0), // @[Tile.scala:16:7]
.io_out_last (io_out_last_0_0),
.io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7]
.io_out_valid (io_out_valid_0_0),
.io_bad_dataflow (io_bad_dataflow_0)
); // @[Tile.scala:42:44]
assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7]
assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7]
assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7]
assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7]
assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7]
assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7]
assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7]
assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7]
assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Bundles.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import freechips.rocketchip.util._
import scala.collection.immutable.ListMap
import chisel3.util.Decoupled
import chisel3.util.DecoupledIO
import chisel3.reflect.DataMirror
abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle
// common combos in lazy policy:
// Put + Acquire
// Release + AccessAck
object TLMessages
{
// A B C D E
def PutFullData = 0.U // . . => AccessAck
def PutPartialData = 1.U // . . => AccessAck
def ArithmeticData = 2.U // . . => AccessAckData
def LogicalData = 3.U // . . => AccessAckData
def Get = 4.U // . . => AccessAckData
def Hint = 5.U // . . => HintAck
def AcquireBlock = 6.U // . => Grant[Data]
def AcquirePerm = 7.U // . => Grant[Data]
def Probe = 6.U // . => ProbeAck[Data]
def AccessAck = 0.U // . .
def AccessAckData = 1.U // . .
def HintAck = 2.U // . .
def ProbeAck = 4.U // .
def ProbeAckData = 5.U // .
def Release = 6.U // . => ReleaseAck
def ReleaseData = 7.U // . => ReleaseAck
def Grant = 4.U // . => GrantAck
def GrantData = 5.U // . => GrantAck
def ReleaseAck = 6.U // .
def GrantAck = 0.U // .
def isA(x: UInt) = x <= AcquirePerm
def isB(x: UInt) = x <= Probe
def isC(x: UInt) = x <= ReleaseData
def isD(x: UInt) = x <= ReleaseAck
def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant)
def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck)
def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("AcquireBlock",TLPermissions.PermMsgGrow),
("AcquirePerm",TLPermissions.PermMsgGrow))
def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("Probe",TLPermissions.PermMsgCap))
def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("ProbeAck",TLPermissions.PermMsgReport),
("ProbeAckData",TLPermissions.PermMsgReport),
("Release",TLPermissions.PermMsgReport),
("ReleaseData",TLPermissions.PermMsgReport))
def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("Grant",TLPermissions.PermMsgCap),
("GrantData",TLPermissions.PermMsgCap),
("ReleaseAck",TLPermissions.PermMsgReserved))
}
/**
* The three primary TileLink permissions are:
* (T)runk: the agent is (or is on inwards path to) the global point of serialization.
* (B)ranch: the agent is on an outwards path to
* (N)one:
* These permissions are permuted by transfer operations in various ways.
* Operations can cap permissions, request for them to be grown or shrunk,
* or for a report on their current status.
*/
object TLPermissions
{
val aWidth = 2
val bdWidth = 2
val cWidth = 3
// Cap types (Grant = new permissions, Probe = permisions <= target)
def toT = 0.U(bdWidth.W)
def toB = 1.U(bdWidth.W)
def toN = 2.U(bdWidth.W)
def isCap(x: UInt) = x <= toN
// Grow types (Acquire = permissions >= target)
def NtoB = 0.U(aWidth.W)
def NtoT = 1.U(aWidth.W)
def BtoT = 2.U(aWidth.W)
def isGrow(x: UInt) = x <= BtoT
// Shrink types (ProbeAck, Release)
def TtoB = 0.U(cWidth.W)
def TtoN = 1.U(cWidth.W)
def BtoN = 2.U(cWidth.W)
def isShrink(x: UInt) = x <= BtoN
// Report types (ProbeAck, Release)
def TtoT = 3.U(cWidth.W)
def BtoB = 4.U(cWidth.W)
def NtoN = 5.U(cWidth.W)
def isReport(x: UInt) = x <= NtoN
def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT")
def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN")
def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN")
def PermMsgReserved:Seq[String] = Seq("Reserved")
}
object TLAtomics
{
val width = 3
// Arithmetic types
def MIN = 0.U(width.W)
def MAX = 1.U(width.W)
def MINU = 2.U(width.W)
def MAXU = 3.U(width.W)
def ADD = 4.U(width.W)
def isArithmetic(x: UInt) = x <= ADD
// Logical types
def XOR = 0.U(width.W)
def OR = 1.U(width.W)
def AND = 2.U(width.W)
def SWAP = 3.U(width.W)
def isLogical(x: UInt) = x <= SWAP
def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD")
def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP")
}
object TLHints
{
val width = 1
def PREFETCH_READ = 0.U(width.W)
def PREFETCH_WRITE = 1.U(width.W)
def isHints(x: UInt) = x <= PREFETCH_WRITE
def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite")
}
sealed trait TLChannel extends TLBundleBase {
val channelName: String
}
sealed trait TLDataChannel extends TLChannel
sealed trait TLAddrChannel extends TLDataChannel
final class TLBundleA(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleA_${params.shortName}"
val channelName = "'A' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleB(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleB_${params.shortName}"
val channelName = "'B' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val address = UInt(params.addressBits.W) // from
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleC(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleC_${params.shortName}"
val channelName = "'C' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.cWidth.W) // shrink or report perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleD(params: TLBundleParameters)
extends TLBundleBase(params) with TLDataChannel
{
override def typeName = s"TLBundleD_${params.shortName}"
val channelName = "'D' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val sink = UInt(params.sinkBits.W) // from
val denied = Bool() // implies corrupt iff *Data
val user = BundleMap(params.responseFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleE(params: TLBundleParameters)
extends TLBundleBase(params) with TLChannel
{
override def typeName = s"TLBundleE_${params.shortName}"
val channelName = "'E' channel"
val sink = UInt(params.sinkBits.W) // to
}
class TLBundle(val params: TLBundleParameters) extends Record
{
// Emulate a Bundle with elements abcde or ad depending on params.hasBCE
private val optA = Some (Decoupled(new TLBundleA(params)))
private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params))))
private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params)))
private val optD = Some (Flipped(Decoupled(new TLBundleD(params))))
private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params)))
def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params)))))
def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params)))))
def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params)))))
def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params)))))
def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params)))))
val elements =
if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a)
else ListMap("d" -> d, "a" -> a)
def tieoff(): Unit = {
DataMirror.specifiedDirectionOf(a.ready) match {
case SpecifiedDirection.Input =>
a.ready := false.B
c.ready := false.B
e.ready := false.B
b.valid := false.B
d.valid := false.B
case SpecifiedDirection.Output =>
a.valid := false.B
c.valid := false.B
e.valid := false.B
b.ready := false.B
d.ready := false.B
case _ =>
}
}
}
object TLBundle
{
def apply(params: TLBundleParameters) = new TLBundle(params)
}
class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle
class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params)
{
val a = new AsyncBundle(new TLBundleA(params.base), params.async)
val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async))
val c = new AsyncBundle(new TLBundleC(params.base), params.async)
val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async))
val e = new AsyncBundle(new TLBundleE(params.base), params.async)
}
class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = RationalIO(new TLBundleA(params))
val b = Flipped(RationalIO(new TLBundleB(params)))
val c = RationalIO(new TLBundleC(params))
val d = Flipped(RationalIO(new TLBundleD(params)))
val e = RationalIO(new TLBundleE(params))
}
class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = CreditedIO(new TLBundleA(params))
val b = Flipped(CreditedIO(new TLBundleB(params)))
val c = CreditedIO(new TLBundleC(params))
val d = Flipped(CreditedIO(new TLBundleD(params)))
val e = CreditedIO(new TLBundleE(params))
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor_17( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59]
wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27]
wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25]
wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_81 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_83 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_87 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_89 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_93 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_95 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_99 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_101 = 1'h1; // @[Parameters.scala:57:20]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28]
wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57]
wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57]
wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [1027:0] _c_sizes_set_T_1 = 1028'h0; // @[Monitor.scala:768:52]
wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79]
wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77]
wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54]
wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59]
wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40]
wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35]
wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35]
wire [519:0] c_sizes_set = 520'h0; // @[Monitor.scala:741:34]
wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34]
wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34]
wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34]
wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117]
wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48]
wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119]
wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire _source_ok_T_25 = io_in_a_bits_source_0 == 7'h3C; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31]
wire _source_ok_T_26 = io_in_a_bits_source_0 == 7'h3D; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31]
wire _source_ok_T_27 = io_in_a_bits_source_0 == 7'h3E; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_7 = _source_ok_T_27; // @[Parameters.scala:1138:31]
wire _source_ok_T_28 = io_in_a_bits_source_0 == 7'h38; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_8 = _source_ok_T_28; // @[Parameters.scala:1138:31]
wire _source_ok_T_29 = io_in_a_bits_source_0 == 7'h39; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_9 = _source_ok_T_29; // @[Parameters.scala:1138:31]
wire _source_ok_T_30 = io_in_a_bits_source_0 == 7'h3A; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_10 = _source_ok_T_30; // @[Parameters.scala:1138:31]
wire _source_ok_T_31 = io_in_a_bits_source_0 == 7'h34; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_11 = _source_ok_T_31; // @[Parameters.scala:1138:31]
wire _source_ok_T_32 = io_in_a_bits_source_0 == 7'h35; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_12 = _source_ok_T_32; // @[Parameters.scala:1138:31]
wire _source_ok_T_33 = io_in_a_bits_source_0 == 7'h36; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_13 = _source_ok_T_33; // @[Parameters.scala:1138:31]
wire _source_ok_T_34 = io_in_a_bits_source_0 == 7'h30; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_14 = _source_ok_T_34; // @[Parameters.scala:1138:31]
wire _source_ok_T_35 = io_in_a_bits_source_0 == 7'h31; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_15 = _source_ok_T_35; // @[Parameters.scala:1138:31]
wire _source_ok_T_36 = io_in_a_bits_source_0 == 7'h32; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_16 = _source_ok_T_36; // @[Parameters.scala:1138:31]
wire _source_ok_T_37 = io_in_a_bits_source_0 == 7'h2C; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_17 = _source_ok_T_37; // @[Parameters.scala:1138:31]
wire _source_ok_T_38 = io_in_a_bits_source_0 == 7'h2D; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_18 = _source_ok_T_38; // @[Parameters.scala:1138:31]
wire _source_ok_T_39 = io_in_a_bits_source_0 == 7'h2E; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_19 = _source_ok_T_39; // @[Parameters.scala:1138:31]
wire _source_ok_T_40 = io_in_a_bits_source_0 == 7'h28; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_20 = _source_ok_T_40; // @[Parameters.scala:1138:31]
wire _source_ok_T_41 = io_in_a_bits_source_0 == 7'h29; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_21 = _source_ok_T_41; // @[Parameters.scala:1138:31]
wire _source_ok_T_42 = io_in_a_bits_source_0 == 7'h2A; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_22 = _source_ok_T_42; // @[Parameters.scala:1138:31]
wire _source_ok_T_43 = io_in_a_bits_source_0 == 7'h24; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_23 = _source_ok_T_43; // @[Parameters.scala:1138:31]
wire _source_ok_T_44 = io_in_a_bits_source_0 == 7'h25; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_24 = _source_ok_T_44; // @[Parameters.scala:1138:31]
wire _source_ok_T_45 = io_in_a_bits_source_0 == 7'h26; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_25 = _source_ok_T_45; // @[Parameters.scala:1138:31]
wire _source_ok_T_46 = io_in_a_bits_source_0 == 7'h20; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_26 = _source_ok_T_46; // @[Parameters.scala:1138:31]
wire _source_ok_T_47 = io_in_a_bits_source_0 == 7'h21; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_27 = _source_ok_T_47; // @[Parameters.scala:1138:31]
wire _source_ok_T_48 = io_in_a_bits_source_0 == 7'h22; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_28 = _source_ok_T_48; // @[Parameters.scala:1138:31]
wire _source_ok_T_49 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_29 = _source_ok_T_49; // @[Parameters.scala:1138:31]
wire _source_ok_T_50 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_51 = _source_ok_T_50 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_52 = _source_ok_T_51 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_53 = _source_ok_T_52 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_54 = _source_ok_T_53 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_55 = _source_ok_T_54 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_56 = _source_ok_T_55 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_57 = _source_ok_T_56 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_58 = _source_ok_T_57 | _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_59 = _source_ok_T_58 | _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_60 = _source_ok_T_59 | _source_ok_WIRE_11; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_61 = _source_ok_T_60 | _source_ok_WIRE_12; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_62 = _source_ok_T_61 | _source_ok_WIRE_13; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_63 = _source_ok_T_62 | _source_ok_WIRE_14; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_64 = _source_ok_T_63 | _source_ok_WIRE_15; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_65 = _source_ok_T_64 | _source_ok_WIRE_16; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_66 = _source_ok_T_65 | _source_ok_WIRE_17; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_67 = _source_ok_T_66 | _source_ok_WIRE_18; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_68 = _source_ok_T_67 | _source_ok_WIRE_19; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_69 = _source_ok_T_68 | _source_ok_WIRE_20; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_70 = _source_ok_T_69 | _source_ok_WIRE_21; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_71 = _source_ok_T_70 | _source_ok_WIRE_22; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_72 = _source_ok_T_71 | _source_ok_WIRE_23; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_73 = _source_ok_T_72 | _source_ok_WIRE_24; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_74 = _source_ok_T_73 | _source_ok_WIRE_25; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_75 = _source_ok_T_74 | _source_ok_WIRE_26; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_76 = _source_ok_T_75 | _source_ok_WIRE_27; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_77 = _source_ok_T_76 | _source_ok_WIRE_28; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_77 | _source_ok_WIRE_29; // @[Parameters.scala:1138:31, :1139:46]
wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [28:0] _is_aligned_T = {17'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_78 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_78; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_79 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_85 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_91 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_97 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_80 = _source_ok_T_79 == 5'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_82 = _source_ok_T_80; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_84 = _source_ok_T_82; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_84; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_86 = _source_ok_T_85 == 5'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_88 = _source_ok_T_86; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_90 = _source_ok_T_88; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_90; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_92 = _source_ok_T_91 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_94 = _source_ok_T_92; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_96 = _source_ok_T_94; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_96; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_98 = _source_ok_T_97 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_100 = _source_ok_T_98; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_102 = _source_ok_T_100; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_102; // @[Parameters.scala:1138:31]
wire _source_ok_T_103 = io_in_d_bits_source_0 == 7'h3C; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_5 = _source_ok_T_103; // @[Parameters.scala:1138:31]
wire _source_ok_T_104 = io_in_d_bits_source_0 == 7'h3D; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_6 = _source_ok_T_104; // @[Parameters.scala:1138:31]
wire _source_ok_T_105 = io_in_d_bits_source_0 == 7'h3E; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_7 = _source_ok_T_105; // @[Parameters.scala:1138:31]
wire _source_ok_T_106 = io_in_d_bits_source_0 == 7'h38; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_8 = _source_ok_T_106; // @[Parameters.scala:1138:31]
wire _source_ok_T_107 = io_in_d_bits_source_0 == 7'h39; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_9 = _source_ok_T_107; // @[Parameters.scala:1138:31]
wire _source_ok_T_108 = io_in_d_bits_source_0 == 7'h3A; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_10 = _source_ok_T_108; // @[Parameters.scala:1138:31]
wire _source_ok_T_109 = io_in_d_bits_source_0 == 7'h34; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_11 = _source_ok_T_109; // @[Parameters.scala:1138:31]
wire _source_ok_T_110 = io_in_d_bits_source_0 == 7'h35; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_12 = _source_ok_T_110; // @[Parameters.scala:1138:31]
wire _source_ok_T_111 = io_in_d_bits_source_0 == 7'h36; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_13 = _source_ok_T_111; // @[Parameters.scala:1138:31]
wire _source_ok_T_112 = io_in_d_bits_source_0 == 7'h30; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_14 = _source_ok_T_112; // @[Parameters.scala:1138:31]
wire _source_ok_T_113 = io_in_d_bits_source_0 == 7'h31; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_15 = _source_ok_T_113; // @[Parameters.scala:1138:31]
wire _source_ok_T_114 = io_in_d_bits_source_0 == 7'h32; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_16 = _source_ok_T_114; // @[Parameters.scala:1138:31]
wire _source_ok_T_115 = io_in_d_bits_source_0 == 7'h2C; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_17 = _source_ok_T_115; // @[Parameters.scala:1138:31]
wire _source_ok_T_116 = io_in_d_bits_source_0 == 7'h2D; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_18 = _source_ok_T_116; // @[Parameters.scala:1138:31]
wire _source_ok_T_117 = io_in_d_bits_source_0 == 7'h2E; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_19 = _source_ok_T_117; // @[Parameters.scala:1138:31]
wire _source_ok_T_118 = io_in_d_bits_source_0 == 7'h28; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_20 = _source_ok_T_118; // @[Parameters.scala:1138:31]
wire _source_ok_T_119 = io_in_d_bits_source_0 == 7'h29; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_21 = _source_ok_T_119; // @[Parameters.scala:1138:31]
wire _source_ok_T_120 = io_in_d_bits_source_0 == 7'h2A; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_22 = _source_ok_T_120; // @[Parameters.scala:1138:31]
wire _source_ok_T_121 = io_in_d_bits_source_0 == 7'h24; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_23 = _source_ok_T_121; // @[Parameters.scala:1138:31]
wire _source_ok_T_122 = io_in_d_bits_source_0 == 7'h25; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_24 = _source_ok_T_122; // @[Parameters.scala:1138:31]
wire _source_ok_T_123 = io_in_d_bits_source_0 == 7'h26; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_25 = _source_ok_T_123; // @[Parameters.scala:1138:31]
wire _source_ok_T_124 = io_in_d_bits_source_0 == 7'h20; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_26 = _source_ok_T_124; // @[Parameters.scala:1138:31]
wire _source_ok_T_125 = io_in_d_bits_source_0 == 7'h21; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_27 = _source_ok_T_125; // @[Parameters.scala:1138:31]
wire _source_ok_T_126 = io_in_d_bits_source_0 == 7'h22; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_28 = _source_ok_T_126; // @[Parameters.scala:1138:31]
wire _source_ok_T_127 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_29 = _source_ok_T_127; // @[Parameters.scala:1138:31]
wire _source_ok_T_128 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_129 = _source_ok_T_128 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_130 = _source_ok_T_129 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_131 = _source_ok_T_130 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_132 = _source_ok_T_131 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_133 = _source_ok_T_132 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_134 = _source_ok_T_133 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_135 = _source_ok_T_134 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_136 = _source_ok_T_135 | _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_137 = _source_ok_T_136 | _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_138 = _source_ok_T_137 | _source_ok_WIRE_1_11; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_139 = _source_ok_T_138 | _source_ok_WIRE_1_12; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_140 = _source_ok_T_139 | _source_ok_WIRE_1_13; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_141 = _source_ok_T_140 | _source_ok_WIRE_1_14; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_142 = _source_ok_T_141 | _source_ok_WIRE_1_15; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_143 = _source_ok_T_142 | _source_ok_WIRE_1_16; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_144 = _source_ok_T_143 | _source_ok_WIRE_1_17; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_145 = _source_ok_T_144 | _source_ok_WIRE_1_18; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_146 = _source_ok_T_145 | _source_ok_WIRE_1_19; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_147 = _source_ok_T_146 | _source_ok_WIRE_1_20; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_148 = _source_ok_T_147 | _source_ok_WIRE_1_21; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_149 = _source_ok_T_148 | _source_ok_WIRE_1_22; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_150 = _source_ok_T_149 | _source_ok_WIRE_1_23; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_151 = _source_ok_T_150 | _source_ok_WIRE_1_24; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_152 = _source_ok_T_151 | _source_ok_WIRE_1_25; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_153 = _source_ok_T_152 | _source_ok_WIRE_1_26; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_154 = _source_ok_T_153 | _source_ok_WIRE_1_27; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_155 = _source_ok_T_154 | _source_ok_WIRE_1_28; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_155 | _source_ok_WIRE_1_29; // @[Parameters.scala:1138:31, :1139:46]
wire _T_2213 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_2213; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_2213; // @[Decoupled.scala:51:35]
wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg [6:0] source; // @[Monitor.scala:390:22]
reg [28:0] address; // @[Monitor.scala:391:22]
wire _T_2281 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_2281; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_2281; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_2281; // @[Decoupled.scala:51:35]
wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg [6:0] source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [64:0] inflight; // @[Monitor.scala:614:27]
reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [519:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [64:0] a_set; // @[Monitor.scala:626:34]
wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [519:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [7:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [9:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65]
wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65]
wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99]
wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67]
wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99]
wire [519:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [519:0] _a_size_lookup_T_6 = {512'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}]
wire [519:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[519:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [127:0] _GEN_3 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35]
wire [127:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_2146 = _T_2213 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_2146 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_2146 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_2146 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [9:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_2146 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [9:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77]
wire [1027:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_2146 ? _a_sizes_set_T_1[519:0] : 520'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [64:0] d_clr; // @[Monitor.scala:664:34]
wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [519:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_2192 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_2192 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_2161 = _T_2281 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_2161 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_2161 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [1038:0] _d_sizes_clr_T_5 = 1039'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_2161 ? _d_sizes_clr_T_5[519:0] : 520'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [64:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [259:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [519:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [519:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [519:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [64:0] inflight_1; // @[Monitor.scala:726:35]
wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [519:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [519:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [7:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [519:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [519:0] _c_size_lookup_T_6 = {512'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}]
wire [519:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[519:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [64:0] d_clr_1; // @[Monitor.scala:774:34]
wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [519:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_2257 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_2257 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_2239 = _T_2281 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_2239 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_2239 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [1038:0] _d_sizes_clr_T_11 = 1039'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_2239 ? _d_sizes_clr_T_11[519:0] : 520'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113]
wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [519:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [519:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
| module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_484( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19]
wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to the following Chisel files.
File PE.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle {
val dataflow = UInt(1.W) // TODO make this an Enum
val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)?
val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats
}
class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module {
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(inputType)
val in_c = Input(cType)
val out_d = Output(dType)
})
io.out_d := io.in_c.mac(io.in_a, io.in_b)
}
// TODO update documentation
/**
* A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh.
* @param width Data width of operands
*/
class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int)
(implicit ev: Arithmetic[T]) extends Module { // Debugging variables
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(outputType)
val in_d = Input(outputType)
val out_a = Output(inputType)
val out_b = Output(outputType)
val out_c = Output(outputType)
val in_control = Input(new PEControl(accType))
val out_control = Output(new PEControl(accType))
val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W))
val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W))
val in_last = Input(Bool())
val out_last = Output(Bool())
val in_valid = Input(Bool())
val out_valid = Output(Bool())
val bad_dataflow = Output(Bool())
})
val cType = if (df == Dataflow.WS) inputType else accType
// When creating PEs that support multiple dataflows, the
// elaboration/synthesis tools often fail to consolidate and de-duplicate
// MAC units. To force mac circuitry to be re-used, we create a "mac_unit"
// module here which just performs a single MAC operation
val mac_unit = Module(new MacUnit(inputType,
if (df == Dataflow.WS) outputType else accType, outputType))
val a = io.in_a
val b = io.in_b
val d = io.in_d
val c1 = Reg(cType)
val c2 = Reg(cType)
val dataflow = io.in_control.dataflow
val prop = io.in_control.propagate
val shift = io.in_control.shift
val id = io.in_id
val last = io.in_last
val valid = io.in_valid
io.out_a := a
io.out_control.dataflow := dataflow
io.out_control.propagate := prop
io.out_control.shift := shift
io.out_id := id
io.out_last := last
io.out_valid := valid
mac_unit.io.in_a := a
val last_s = RegEnable(prop, valid)
val flip = last_s =/= prop
val shift_offset = Mux(flip, shift, 0.U)
// Which dataflow are we using?
val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W)
val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W)
// Is c1 being computed on, or propagated forward (in the output-stationary dataflow)?
val COMPUTE = 0.U(1.W)
val PROPAGATE = 1.U(1.W)
io.bad_dataflow := false.B
when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
c2 := mac_unit.io.out_d
c1 := d.withWidthOf(cType)
}.otherwise {
io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c1
c1 := mac_unit.io.out_d
c2 := d.withWidthOf(cType)
}
}.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := c1
mac_unit.io.in_b := c2.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c1 := d
}.otherwise {
io.out_c := c2
mac_unit.io.in_b := c1.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c2 := d
}
}.otherwise {
io.bad_dataflow := true.B
//assert(false.B, "unknown dataflow")
io.out_c := DontCare
io.out_b := DontCare
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
}
when (!valid) {
c1 := c1
c2 := c2
mac_unit.io.in_b := DontCare
mac_unit.io.in_c := DontCare
}
}
File Arithmetic.scala:
// A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own:
// implicit MyTypeArithmetic extends Arithmetic[MyType] { ... }
package gemmini
import chisel3._
import chisel3.util._
import hardfloat._
// Bundles that represent the raw bits of custom datatypes
case class Float(expWidth: Int, sigWidth: Int) extends Bundle {
val bits = UInt((expWidth + sigWidth).W)
val bias: Int = (1 << (expWidth-1)) - 1
}
case class DummySInt(w: Int) extends Bundle {
val bits = UInt(w.W)
def dontCare: DummySInt = {
val o = Wire(new DummySInt(w))
o.bits := 0.U
o
}
}
// The Arithmetic typeclass which implements various arithmetic operations on custom datatypes
abstract class Arithmetic[T <: Data] {
implicit def cast(t: T): ArithmeticOps[T]
}
abstract class ArithmeticOps[T <: Data](self: T) {
def *(t: T): T
def mac(m1: T, m2: T): T // Returns (m1 * m2 + self)
def +(t: T): T
def -(t: T): T
def >>(u: UInt): T // This is a rounding shift! Rounds away from 0
def >(t: T): Bool
def identity: T
def withWidthOf(t: T): T
def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates
def relu: T
def zero: T
def minimum: T
// Optional parameters, which only need to be defined if you want to enable various optimizations for transformers
def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None
def mult_with_reciprocal[U <: Data](reciprocal: U) = self
}
object Arithmetic {
implicit object UIntArithmetic extends Arithmetic[UInt] {
override implicit def cast(self: UInt) = new ArithmeticOps(self) {
override def *(t: UInt) = self * t
override def mac(m1: UInt, m2: UInt) = m1 * m2 + self
override def +(t: UInt) = self + t
override def -(t: UInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = point_five & (zeros | ones_digit)
(self >> u).asUInt + r
}
override def >(t: UInt): Bool = self > t
override def withWidthOf(t: UInt) = self.asTypeOf(t)
override def clippedToWidthOf(t: UInt) = {
val sat = ((1 << (t.getWidth-1))-1).U
Mux(self > sat, sat, self)(t.getWidth-1, 0)
}
override def relu: UInt = self
override def zero: UInt = 0.U
override def identity: UInt = 1.U
override def minimum: UInt = 0.U
}
}
implicit object SIntArithmetic extends Arithmetic[SInt] {
override implicit def cast(self: SInt) = new ArithmeticOps(self) {
override def *(t: SInt) = self * t
override def mac(m1: SInt, m2: SInt) = m1 * m2 + self
override def +(t: SInt) = self + t
override def -(t: SInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = (point_five & (zeros | ones_digit)).asBool
(self >> u).asSInt + Mux(r, 1.S, 0.S)
}
override def >(t: SInt): Bool = self > t
override def withWidthOf(t: SInt) = {
if (self.getWidth >= t.getWidth)
self(t.getWidth-1, 0).asSInt
else {
val sign_bits = t.getWidth - self.getWidth
val sign = self(self.getWidth-1)
Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t)
}
}
override def clippedToWidthOf(t: SInt): SInt = {
val maxsat = ((1 << (t.getWidth-1))-1).S
val minsat = (-(1 << (t.getWidth-1))).S
MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt
}
override def relu: SInt = Mux(self >= 0.S, self, 0.S)
override def zero: SInt = 0.S
override def identity: SInt = 1.S
override def minimum: SInt = (-(1 << (self.getWidth-1))).S
override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(denom_t.cloneType))
val output = Wire(Decoupled(self.cloneType))
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def sin_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def uin_to_float(x: UInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := x
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = sin_to_float(self)
val denom_rec = uin_to_float(input.bits)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := self_rec
divider.io.b := denom_rec
divider.io.roundingMode := consts.round_minMag
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := float_to_in(divider.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(self.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
// Instantiate the hardloat sqrt
val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0))
input.ready := sqrter.io.inReady
sqrter.io.inValid := input.valid
sqrter.io.sqrtOp := true.B
sqrter.io.a := self_rec
sqrter.io.b := DontCare
sqrter.io.roundingMode := consts.round_minMag
sqrter.io.detectTininess := consts.tininess_afterRounding
output.valid := sqrter.io.outValid_sqrt
output.bits := float_to_in(sqrter.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match {
case Float(expWidth, sigWidth) =>
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(u.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
val self_rec = in_to_float(self)
val one_rec = in_to_float(1.S)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := one_rec
divider.io.b := self_rec
divider.io.roundingMode := consts.round_near_even
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u)
assert(!output.valid || output.ready)
Some((input, output))
case _ => None
}
override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match {
case recip @ Float(expWidth, sigWidth) =>
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits)
// Instantiate the hardloat divider
val muladder = Module(new MulRecFN(expWidth, sigWidth))
muladder.io.roundingMode := consts.round_near_even
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := reciprocal_rec
float_to_in(muladder.io.out)
case _ => self
}
}
}
implicit object FloatArithmetic extends Arithmetic[Float] {
// TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array
override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) {
override def *(t: Float): Float = {
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := t_rec_resized
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def mac(m1: Float, m2: Float): Float = {
// Recode all operands
val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits)
val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize m1 to self's width
val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth))
m1_resizer.io.in := m1_rec
m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m1_resizer.io.detectTininess := consts.tininess_afterRounding
val m1_rec_resized = m1_resizer.io.out
// Resize m2 to self's width
val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth))
m2_resizer.io.in := m2_rec
m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m2_resizer.io.detectTininess := consts.tininess_afterRounding
val m2_rec_resized = m2_resizer.io.out
// Perform multiply-add
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := m1_rec_resized
muladder.io.b := m2_rec_resized
muladder.io.c := self_rec
// Convert result to standard format // TODO remove these intermediate recodings
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def +(t: Float): Float = {
require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Generate 1 as a float
val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := 1.U
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
val one_rec = in_to_rec_fn.io.out
// Resize t
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
// Perform addition
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := t_rec_resized
muladder.io.b := one_rec
muladder.io.c := self_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def -(t: Float): Float = {
val t_sgn = t.bits(t.getWidth-1)
val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t)
self + neg_t
}
override def >>(u: UInt): Float = {
// Recode self
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Get 2^(-u) as a recoded float
val shift_exp = Wire(UInt(self.expWidth.W))
shift_exp := self.bias.U - u
val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W))
val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn)
assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported")
// Multiply self and 2^(-u)
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := shift_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def >(t: Float): Bool = {
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize t to self's width
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth))
comparator.io.a := self_rec
comparator.io.b := t_rec_resized
comparator.io.signaling := false.B
comparator.io.gt
}
override def withWidthOf(t: Float): Float = {
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def clippedToWidthOf(t: Float): Float = {
// TODO check for overflow. Right now, we just assume that overflow doesn't happen
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def relu: Float = {
val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits)
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits)
result
}
override def zero: Float = 0.U.asTypeOf(self)
override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
}
}
implicit object DummySIntArithmetic extends Arithmetic[DummySInt] {
override implicit def cast(self: DummySInt) = new ArithmeticOps(self) {
override def *(t: DummySInt) = self.dontCare
override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare
override def +(t: DummySInt) = self.dontCare
override def -(t: DummySInt) = self.dontCare
override def >>(t: UInt) = self.dontCare
override def >(t: DummySInt): Bool = false.B
override def identity = self.dontCare
override def withWidthOf(t: DummySInt) = self.dontCare
override def clippedToWidthOf(t: DummySInt) = self.dontCare
override def relu = self.dontCare
override def zero = self.dontCare
override def minimum: DummySInt = self.dontCare
}
}
}
| module PE_414( // @[PE.scala:31:7]
input clock, // @[PE.scala:31:7]
input reset, // @[PE.scala:31:7]
input [7:0] io_in_a, // @[PE.scala:35:14]
input [19:0] io_in_b, // @[PE.scala:35:14]
input [19:0] io_in_d, // @[PE.scala:35:14]
output [7:0] io_out_a, // @[PE.scala:35:14]
output [19:0] io_out_b, // @[PE.scala:35:14]
output [19:0] io_out_c, // @[PE.scala:35:14]
input io_in_control_dataflow, // @[PE.scala:35:14]
input io_in_control_propagate, // @[PE.scala:35:14]
input [4:0] io_in_control_shift, // @[PE.scala:35:14]
output io_out_control_dataflow, // @[PE.scala:35:14]
output io_out_control_propagate, // @[PE.scala:35:14]
output [4:0] io_out_control_shift, // @[PE.scala:35:14]
input [2:0] io_in_id, // @[PE.scala:35:14]
output [2:0] io_out_id, // @[PE.scala:35:14]
input io_in_last, // @[PE.scala:35:14]
output io_out_last, // @[PE.scala:35:14]
input io_in_valid, // @[PE.scala:35:14]
output io_out_valid, // @[PE.scala:35:14]
output io_bad_dataflow // @[PE.scala:35:14]
);
wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24]
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7]
wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7]
wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7]
wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7]
wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7]
wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7]
wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7]
wire io_in_last_0 = io_in_last; // @[PE.scala:31:7]
wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7]
wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7]
wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7]
wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37]
wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37]
wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35]
wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7]
wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7]
wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7]
wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7]
wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7]
wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7]
wire [19:0] io_out_b_0; // @[PE.scala:31:7]
wire [19:0] io_out_c_0; // @[PE.scala:31:7]
reg [31:0] c1; // @[PE.scala:70:15]
wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15]
wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38]
reg [31:0] c2; // @[PE.scala:71:15]
wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15]
wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38]
reg last_s; // @[PE.scala:89:25]
wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21]
wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25]
wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25]
wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32]
wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32]
wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25]
wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15]
wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}]
wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25]
wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27]
wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27]
wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25]
wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15]
wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15]
assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37]
wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37]
wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61]
wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15]
wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}]
wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15]
wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15]
assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37]
wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37]
wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61]
wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38]
wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38]
wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38]
wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38]
assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16]
assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101]
wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35]
wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35]
wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10]
wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10]
always @(posedge clock) begin // @[PE.scala:31:7]
if (io_in_valid_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10]
c1 <= _GEN_7; // @[PE.scala:70:15, :124:10]
if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30]
end
else // @[PE.scala:71:15, :118:101, :119:30]
c2 <= _GEN_7; // @[PE.scala:71:15, :124:10]
end
else begin // @[PE.scala:31:7]
c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10]
c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10]
end
last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25]
end
always @(posedge)
MacUnit_158 mac_unit ( // @[PE.scala:64:24]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0), // @[PE.scala:31:7]
.io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}]
.io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24]
.io_out_d (_mac_unit_io_out_d)
); // @[PE.scala:64:24]
assign io_out_a = io_out_a_0; // @[PE.scala:31:7]
assign io_out_b = io_out_b_0; // @[PE.scala:31:7]
assign io_out_c = io_out_c_0; // @[PE.scala:31:7]
assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7]
assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7]
assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7]
assign io_out_id = io_out_id_0; // @[PE.scala:31:7]
assign io_out_last = io_out_last_0; // @[PE.scala:31:7]
assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7]
assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Crossing.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.interrupts
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.util.{SynchronizerShiftReg, AsyncResetReg}
@deprecated("IntXing does not ensure interrupt source is glitch free. Use IntSyncSource and IntSyncSink", "rocket-chip 1.2")
class IntXing(sync: Int = 3)(implicit p: Parameters) extends LazyModule
{
val intnode = IntAdapterNode()
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
(intnode.in zip intnode.out) foreach { case ((in, _), (out, _)) =>
out := SynchronizerShiftReg(in, sync)
}
}
}
object IntSyncCrossingSource
{
def apply(alreadyRegistered: Boolean = false)(implicit p: Parameters) =
{
val intsource = LazyModule(new IntSyncCrossingSource(alreadyRegistered))
intsource.node
}
}
class IntSyncCrossingSource(alreadyRegistered: Boolean = false)(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSourceNode(alreadyRegistered)
lazy val module = if (alreadyRegistered) (new ImplRegistered) else (new Impl)
class Impl extends LazyModuleImp(this) {
def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0)
override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out.sync := AsyncResetReg(Cat(in.reverse)).asBools
}
}
class ImplRegistered extends LazyRawModuleImp(this) {
def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0)
override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}_Registered"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out.sync := in
}
}
}
object IntSyncCrossingSink
{
@deprecated("IntSyncCrossingSink which used the `sync` parameter to determine crossing type is deprecated. Use IntSyncAsyncCrossingSink, IntSyncRationalCrossingSink, or IntSyncSyncCrossingSink instead for > 1, 1, and 0 sync values respectively", "rocket-chip 1.2")
def apply(sync: Int = 3)(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync))
intsink.node
}
}
class IntSyncAsyncCrossingSink(sync: Int = 3)(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSinkNode(sync)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
override def desiredName = s"IntSyncAsyncCrossingSink_n${node.out.size}x${node.out.head._1.size}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out := SynchronizerShiftReg(in.sync, sync)
}
}
}
object IntSyncAsyncCrossingSink
{
def apply(sync: Int = 3)(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync))
intsink.node
}
}
class IntSyncSyncCrossingSink()(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSinkNode(0)
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
def outSize = node.out.headOption.map(_._1.size).getOrElse(0)
override def desiredName = s"IntSyncSyncCrossingSink_n${node.out.size}x${outSize}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out := in.sync
}
}
}
object IntSyncSyncCrossingSink
{
def apply()(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncSyncCrossingSink())
intsink.node
}
}
class IntSyncRationalCrossingSink()(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSinkNode(1)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
def outSize = node.out.headOption.map(_._1.size).getOrElse(0)
override def desiredName = s"IntSyncRationalCrossingSink_n${node.out.size}x${outSize}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out := RegNext(in.sync)
}
}
}
object IntSyncRationalCrossingSink
{
def apply()(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncRationalCrossingSink())
intsink.node
}
}
File AtomicAutomata.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes}
import freechips.rocketchip.util.leftOR
import scala.math.{min,max}
// Ensures that all downstream RW managers support Atomic operations.
// If !passthrough, intercept all Atomics. Otherwise, only intercept those unsupported downstream.
class TLAtomicAutomata(logical: Boolean = true, arithmetic: Boolean = true, concurrency: Int = 1, passthrough: Boolean = true)(implicit p: Parameters) extends LazyModule
{
require (concurrency >= 1)
val node = TLAdapterNode(
managerFn = { case mp => mp.v1copy(managers = mp.managers.map { m =>
val ourSupport = TransferSizes(1, mp.beatBytes)
def widen(x: TransferSizes) = if (passthrough && x.min <= 2*mp.beatBytes) TransferSizes(1, max(mp.beatBytes, x.max)) else ourSupport
val canDoit = m.supportsPutFull.contains(ourSupport) && m.supportsGet.contains(ourSupport)
// Blow up if there are devices to which we cannot add Atomics, because their R|W are too inflexible
require (!m.supportsPutFull || !m.supportsGet || canDoit, s"${m.name} has $ourSupport, needed PutFull(${m.supportsPutFull}) or Get(${m.supportsGet})")
m.v1copy(
supportsArithmetic = if (!arithmetic || !canDoit) m.supportsArithmetic else widen(m.supportsArithmetic),
supportsLogical = if (!logical || !canDoit) m.supportsLogical else widen(m.supportsLogical),
mayDenyGet = m.mayDenyGet || m.mayDenyPut)
})})
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
val managers = edgeOut.manager.managers
val beatBytes = edgeOut.manager.beatBytes
// To which managers are we adding atomic support?
val ourSupport = TransferSizes(1, beatBytes)
val managersNeedingHelp = managers.filter { m =>
m.supportsPutFull.contains(ourSupport) &&
m.supportsGet.contains(ourSupport) &&
((logical && !m.supportsLogical .contains(ourSupport)) ||
(arithmetic && !m.supportsArithmetic.contains(ourSupport)) ||
!passthrough) // we will do atomics for everyone we can
}
// Managers that need help with atomics must necessarily have this node as the root of a tree in the node graph.
// (But they must also ensure no sideband operations can get between the read and write.)
val violations = managersNeedingHelp.flatMap(_.findTreeViolation()).map { node => (node.name, node.inputs.map(_._1.name)) }
require(violations.isEmpty,
s"AtomicAutomata can only help nodes for which it is at the root of a diplomatic node tree," +
"but the following violations were found:\n" +
violations.map(v => s"(${v._1} has parents ${v._2})").mkString("\n"))
// We cannot add atomics to a non-FIFO manager
managersNeedingHelp foreach { m => require (m.fifoId.isDefined) }
// We need to preserve FIFO semantics across FIFO domains, not managers
// Suppose you have Put(42) Atomic(+1) both inflight; valid results: 42 or 43
// If we allow Put(42) Get() Put(+1) concurrent; valid results: 42 43 OR undef
// Making non-FIFO work requires waiting for all Acks to come back (=> use FIFOFixer)
val domainsNeedingHelp = managersNeedingHelp.map(_.fifoId.get).distinct
// Don't overprovision the CAM
val camSize = min(domainsNeedingHelp.size, concurrency)
// Compact the fifoIds to only those we care about
def camFifoId(m: TLSlaveParameters) = m.fifoId.map(id => max(0, domainsNeedingHelp.indexOf(id))).getOrElse(0)
// CAM entry state machine
val FREE = 0.U // unused waiting on Atomic from A
val GET = 3.U // Get sent down A waiting on AccessDataAck from D
val AMO = 2.U // AccessDataAck sent up D waiting for A availability
val ACK = 1.U // Put sent down A waiting for PutAck from D
val params = TLAtomicAutomata.CAMParams(out.a.bits.params, domainsNeedingHelp.size)
// Do we need to do anything at all?
if (camSize > 0) {
val initval = Wire(new TLAtomicAutomata.CAM_S(params))
initval.state := FREE
val cam_s = RegInit(VecInit.fill(camSize)(initval))
val cam_a = Reg(Vec(camSize, new TLAtomicAutomata.CAM_A(params)))
val cam_d = Reg(Vec(camSize, new TLAtomicAutomata.CAM_D(params)))
val cam_free = cam_s.map(_.state === FREE)
val cam_amo = cam_s.map(_.state === AMO)
val cam_abusy = cam_s.map(e => e.state === GET || e.state === AMO) // A is blocked
val cam_dmatch = cam_s.map(e => e.state =/= FREE) // D should inspect these entries
// Can the manager already handle this message?
val a_address = edgeIn.address(in.a.bits)
val a_size = edgeIn.size(in.a.bits)
val a_canLogical = passthrough.B && edgeOut.manager.supportsLogicalFast (a_address, a_size)
val a_canArithmetic = passthrough.B && edgeOut.manager.supportsArithmeticFast(a_address, a_size)
val a_isLogical = in.a.bits.opcode === TLMessages.LogicalData
val a_isArithmetic = in.a.bits.opcode === TLMessages.ArithmeticData
val a_isSupported = Mux(a_isLogical, a_canLogical, Mux(a_isArithmetic, a_canArithmetic, true.B))
// Must we do a Put?
val a_cam_any_put = cam_amo.reduce(_ || _)
val a_cam_por_put = cam_amo.scanLeft(false.B)(_||_).init
val a_cam_sel_put = (cam_amo zip a_cam_por_put) map { case (a, b) => a && !b }
val a_cam_a = PriorityMux(cam_amo, cam_a)
val a_cam_d = PriorityMux(cam_amo, cam_d)
val a_a = a_cam_a.bits.data
val a_d = a_cam_d.data
// Does the A request conflict with an inflight AMO?
val a_fifoId = edgeOut.manager.fastProperty(a_address, camFifoId _, (i:Int) => i.U)
val a_cam_busy = (cam_abusy zip cam_a.map(_.fifoId === a_fifoId)) map { case (a,b) => a&&b } reduce (_||_)
// (Where) are we are allocating in the CAM?
val a_cam_any_free = cam_free.reduce(_ || _)
val a_cam_por_free = cam_free.scanLeft(false.B)(_||_).init
val a_cam_sel_free = (cam_free zip a_cam_por_free) map { case (a,b) => a && !b }
// Logical AMO
val indexes = Seq.tabulate(beatBytes*8) { i => Cat(a_a(i,i), a_d(i,i)) }
val logic_out = Cat(indexes.map(x => a_cam_a.lut(x).asUInt).reverse)
// Arithmetic AMO
val unsigned = a_cam_a.bits.param(1)
val take_max = a_cam_a.bits.param(0)
val adder = a_cam_a.bits.param(2)
val mask = a_cam_a.bits.mask
val signSel = ~(~mask | (mask >> 1))
val signbits_a = Cat(Seq.tabulate(beatBytes) { i => a_a(8*i+7,8*i+7) } .reverse)
val signbits_d = Cat(Seq.tabulate(beatBytes) { i => a_d(8*i+7,8*i+7) } .reverse)
// Move the selected sign bit into the first byte position it will extend
val signbit_a = ((signbits_a & signSel) << 1)(beatBytes-1, 0)
val signbit_d = ((signbits_d & signSel) << 1)(beatBytes-1, 0)
val signext_a = FillInterleaved(8, leftOR(signbit_a))
val signext_d = FillInterleaved(8, leftOR(signbit_d))
// NOTE: sign-extension does not change the relative ordering in EITHER unsigned or signed arithmetic
val wide_mask = FillInterleaved(8, mask)
val a_a_ext = (a_a & wide_mask) | signext_a
val a_d_ext = (a_d & wide_mask) | signext_d
val a_d_inv = Mux(adder, a_d_ext, ~a_d_ext)
val adder_out = a_a_ext + a_d_inv
val h = 8*beatBytes-1 // now sign-extended; use biggest bit
val a_bigger_uneq = unsigned === a_a_ext(h) // result if high bits are unequal
val a_bigger = Mux(a_a_ext(h) === a_d_ext(h), !adder_out(h), a_bigger_uneq)
val pick_a = take_max === a_bigger
val arith_out = Mux(adder, adder_out, Mux(pick_a, a_a, a_d))
// AMO result data
val amo_data =
if (!logical) arith_out else
if (!arithmetic) logic_out else
Mux(a_cam_a.bits.opcode(0), logic_out, arith_out)
// Potentially mutate the message from inner
val source_i = Wire(chiselTypeOf(in.a))
val a_allow = !a_cam_busy && (a_isSupported || a_cam_any_free)
in.a.ready := source_i.ready && a_allow
source_i.valid := in.a.valid && a_allow
source_i.bits := in.a.bits
when (!a_isSupported) { // minimal mux difference
source_i.bits.opcode := TLMessages.Get
source_i.bits.param := 0.U
}
// Potentially take the message from the CAM
val source_c = Wire(chiselTypeOf(in.a))
source_c.valid := a_cam_any_put
source_c.bits := edgeOut.Put(
fromSource = a_cam_a.bits.source,
toAddress = edgeIn.address(a_cam_a.bits),
lgSize = a_cam_a.bits.size,
data = amo_data,
corrupt = a_cam_a.bits.corrupt || a_cam_d.corrupt)._2
source_c.bits.user :<= a_cam_a.bits.user
source_c.bits.echo :<= a_cam_a.bits.echo
// Finishing an AMO from the CAM has highest priority
TLArbiter(TLArbiter.lowestIndexFirst)(out.a, (0.U, source_c), (edgeOut.numBeats1(in.a.bits), source_i))
// Capture the A state into the CAM
when (source_i.fire && !a_isSupported) {
(a_cam_sel_free zip cam_a) foreach { case (en, r) =>
when (en) {
r.fifoId := a_fifoId
r.bits := in.a.bits
r.lut := MuxLookup(in.a.bits.param(1, 0), 0.U(4.W))(Array(
TLAtomics.AND -> 0x8.U,
TLAtomics.OR -> 0xe.U,
TLAtomics.XOR -> 0x6.U,
TLAtomics.SWAP -> 0xc.U))
}
}
(a_cam_sel_free zip cam_s) foreach { case (en, r) =>
when (en) {
r.state := GET
}
}
}
// Advance the put state
when (source_c.fire) {
(a_cam_sel_put zip cam_s) foreach { case (en, r) =>
when (en) {
r.state := ACK
}
}
}
// We need to deal with a potential D response in the same cycle as the A request
val d_first = edgeOut.first(out.d)
val d_cam_sel_raw = cam_a.map(_.bits.source === in.d.bits.source)
val d_cam_sel_match = (d_cam_sel_raw zip cam_dmatch) map { case (a,b) => a&&b }
val d_cam_data = Mux1H(d_cam_sel_match, cam_d.map(_.data))
val d_cam_denied = Mux1H(d_cam_sel_match, cam_d.map(_.denied))
val d_cam_corrupt = Mux1H(d_cam_sel_match, cam_d.map(_.corrupt))
val d_cam_sel_bypass = if (edgeOut.manager.minLatency > 0) false.B else
out.d.bits.source === in.a.bits.source && in.a.valid && !a_isSupported
val d_cam_sel = (a_cam_sel_free zip d_cam_sel_match) map { case (a,d) => Mux(d_cam_sel_bypass, a, d) }
val d_cam_sel_any = d_cam_sel_bypass || d_cam_sel_match.reduce(_ || _)
val d_ackd = out.d.bits.opcode === TLMessages.AccessAckData
val d_ack = out.d.bits.opcode === TLMessages.AccessAck
when (out.d.fire && d_first) {
(d_cam_sel zip cam_d) foreach { case (en, r) =>
when (en && d_ackd) {
r.data := out.d.bits.data
r.denied := out.d.bits.denied
r.corrupt := out.d.bits.corrupt
}
}
(d_cam_sel zip cam_s) foreach { case (en, r) =>
when (en) {
// Note: it is important that this comes AFTER the := GET, so we can go FREE=>GET=>AMO in one cycle
r.state := Mux(d_ackd, AMO, FREE)
}
}
}
val d_drop = d_first && d_ackd && d_cam_sel_any
val d_replace = d_first && d_ack && d_cam_sel_match.reduce(_ || _)
in.d.valid := out.d.valid && !d_drop
out.d.ready := in.d.ready || d_drop
in.d.bits := out.d.bits
when (d_replace) { // minimal muxes
in.d.bits.opcode := TLMessages.AccessAckData
in.d.bits.data := d_cam_data
in.d.bits.corrupt := d_cam_corrupt || out.d.bits.denied
in.d.bits.denied := d_cam_denied || out.d.bits.denied
}
} else {
out.a.valid := in.a.valid
in.a.ready := out.a.ready
out.a.bits := in.a.bits
in.d.valid := out.d.valid
out.d.ready := in.d.ready
in.d.bits := out.d.bits
}
if (edgeOut.manager.anySupportAcquireB && edgeIn.client.anySupportProbe) {
in.b.valid := out.b.valid
out.b.ready := in.b.ready
in.b.bits := out.b.bits
out.c.valid := in.c.valid
in.c.ready := out.c.ready
out.c.bits := in.c.bits
out.e.valid := in.e.valid
in.e.ready := out.e.ready
out.e.bits := in.e.bits
} else {
in.b.valid := false.B
in.c.ready := true.B
in.e.ready := true.B
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
}
}
}
}
object TLAtomicAutomata
{
def apply(logical: Boolean = true, arithmetic: Boolean = true, concurrency: Int = 1, passthrough: Boolean = true, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode =
{
val atomics = LazyModule(new TLAtomicAutomata(logical, arithmetic, concurrency, passthrough) {
override lazy val desiredName = (Seq("TLAtomicAutomata") ++ nameSuffix).mkString("_")
})
atomics.node
}
case class CAMParams(a: TLBundleParameters, domainsNeedingHelp: Int)
class CAM_S(val params: CAMParams) extends Bundle {
val state = UInt(2.W)
}
class CAM_A(val params: CAMParams) extends Bundle {
val bits = new TLBundleA(params.a)
val fifoId = UInt(log2Up(params.domainsNeedingHelp).W)
val lut = UInt(4.W)
}
class CAM_D(val params: CAMParams) extends Bundle {
val data = UInt(params.a.dataBits.W)
val denied = Bool()
val corrupt = Bool()
}
}
// Synthesizable unit tests
import freechips.rocketchip.unittest._
class TLRAMAtomicAutomata(txns: Int)(implicit p: Parameters) extends LazyModule {
val fuzz = LazyModule(new TLFuzzer(txns))
val model = LazyModule(new TLRAMModel("AtomicAutomata"))
val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff)))
// Confirm that the AtomicAutomata combines read + write errors
import TLMessages._
val test = new RequestPattern({a: TLBundleA =>
val doesA = a.opcode === ArithmeticData || a.opcode === LogicalData
val doesR = a.opcode === Get || doesA
val doesW = a.opcode === PutFullData || a.opcode === PutPartialData || doesA
(doesR && RequestPattern.overlaps(Seq(AddressSet(0x08, ~0x08)))(a)) ||
(doesW && RequestPattern.overlaps(Seq(AddressSet(0x10, ~0x10)))(a))
})
(ram.node
:= TLErrorEvaluator(test)
:= TLFragmenter(4, 256)
:= TLDelayer(0.1)
:= TLAtomicAutomata()
:= TLDelayer(0.1)
:= TLErrorEvaluator(test, testOn=true, testOff=true)
:= model.node
:= fuzz.node)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) with UnitTestModule {
io.finished := fuzz.module.io.finished
}
}
class TLRAMAtomicAutomataTest(txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
val dut = Module(LazyModule(new TLRAMAtomicAutomata(txns)).module)
io.finished := dut.io.finished
dut.io.start := io.start
}
File NIC.scala:
package icenet
import chisel3._
import chisel3.util._
import chisel3.reflect.DataMirror
import freechips.rocketchip.subsystem.{BaseSubsystem, TLBusWrapperLocation, PBUS, FBUS}
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.prci._
import freechips.rocketchip.regmapper._
import freechips.rocketchip.interrupts._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
import IceNetConsts._
// This is copied from testchipip to avoid dependencies
class ClockedIO[T <: Data](private val gen: T) extends Bundle {
val clock = Output(Clock())
val bits = DataMirror.internal.chiselTypeClone[T](gen)
}
/**
* @inBufFlits How many flits in the input buffer(s)
* @outBufFlits Number of flits in the output buffer
* @nMemXacts Maximum number of transactions that the send/receive path can send to memory
* @maxAcquireBytes Cache block size
* @ctrlQueueDepth Depth of the MMIO control queues
* @usePauser Hardware support for Ethernet pause frames
* @checksumOffload TCP checksum offload engine
* @packetMaxBytes Maximum number of bytes in a packet (header size + MTU)
*/
case class NICConfig(
inBufFlits: Int = 2 * ETH_STANDARD_MAX_BYTES / NET_IF_BYTES,
outBufFlits: Int = 2 * ETH_STANDARD_MAX_BYTES / NET_IF_BYTES,
nMemXacts: Int = 8,
maxAcquireBytes: Int = 64,
ctrlQueueDepth: Int = 10,
usePauser: Boolean = false,
checksumOffload: Boolean = false,
packetMaxBytes: Int = ETH_STANDARD_MAX_BYTES)
case class NICAttachParams(
masterWhere: TLBusWrapperLocation = FBUS,
slaveWhere: TLBusWrapperLocation = PBUS
)
case object NICKey extends Field[Option[NICConfig]](None)
case object NICAttachKey extends Field[NICAttachParams](NICAttachParams())
trait HasNICParameters {
implicit val p: Parameters
val nicExternal = p(NICKey).get
val inBufFlits = nicExternal.inBufFlits
val outBufFlits = nicExternal.outBufFlits
val nMemXacts = nicExternal.nMemXacts
val maxAcquireBytes = nicExternal.maxAcquireBytes
val ctrlQueueDepth = nicExternal.ctrlQueueDepth
val usePauser = nicExternal.usePauser
val checksumOffload = nicExternal.checksumOffload
val packetMaxBytes = nicExternal.packetMaxBytes
}
abstract class NICLazyModule(implicit p: Parameters)
extends LazyModule with HasNICParameters
abstract class NICModule(implicit val p: Parameters)
extends Module with HasNICParameters
abstract class NICBundle(implicit val p: Parameters)
extends Bundle with HasNICParameters
class PacketArbiter(arbN: Int, rr: Boolean = false)
extends HellaPeekingArbiter(
new StreamChannel(NET_IF_WIDTH), arbN,
(ch: StreamChannel) => ch.last, rr = rr)
class IceNicSendIO extends Bundle {
val req = Decoupled(UInt(NET_IF_WIDTH.W))
val comp = Flipped(Decoupled(Bool()))
}
class IceNicRecvIO extends Bundle {
val req = Decoupled(UInt(NET_IF_WIDTH.W))
val comp = Flipped(Decoupled(UInt(NET_LEN_BITS.W)))
}
trait IceNicControllerBundle extends Bundle {
val send = new IceNicSendIO
val recv = new IceNicRecvIO
val macAddr = Input(UInt(ETH_MAC_BITS.W))
val txcsumReq = Decoupled(new ChecksumRewriteRequest)
val rxcsumRes = Flipped(Decoupled(new TCPChecksumOffloadResult))
val csumEnable = Output(Bool())
}
case class IceNicControllerParams(address: BigInt, beatBytes: Int)
/*
* Take commands from the CPU over TL2, expose as Queues
*/
class IceNicController(c: IceNicControllerParams)(implicit p: Parameters)
extends RegisterRouter(RegisterRouterParams("ice-nic", Seq("ucb-bar,ice-nic"),
c.address, beatBytes=c.beatBytes))
with HasTLControlRegMap
with HasInterruptSources
with HasNICParameters {
override def nInterrupts = 2
def tlRegmap(mapping: RegField.Map*): Unit = regmap(mapping:_*)
override lazy val module = new IceNiCControllerModuleImp(this)
}
class IceNiCControllerModuleImp(outer: IceNicController)(implicit p: Parameters) extends LazyModuleImp(outer) with HasNICParameters {
val io = IO(new Bundle with IceNicControllerBundle)
val sendCompDown = WireInit(false.B)
val qDepth = ctrlQueueDepth
require(qDepth < (1 << 8))
def queueCount[T <: Data](qio: QueueIO[T], depth: Int): UInt =
TwoWayCounter(qio.enq.fire, qio.deq.fire, depth)
// hold (len, addr) of packets that we need to send out
val sendReqQueue = Module(new HellaQueue(qDepth)(UInt(NET_IF_WIDTH.W)))
val sendReqCount = queueCount(sendReqQueue.io, qDepth)
// hold addr of buffers we can write received packets into
val recvReqQueue = Module(new HellaQueue(qDepth)(UInt(NET_IF_WIDTH.W)))
val recvReqCount = queueCount(recvReqQueue.io, qDepth)
// count number of sends completed
val sendCompCount = TwoWayCounter(io.send.comp.fire, sendCompDown, qDepth)
// hold length of received packets
val recvCompQueue = Module(new HellaQueue(qDepth)(UInt(NET_LEN_BITS.W)))
val recvCompCount = queueCount(recvCompQueue.io, qDepth)
val sendCompValid = sendCompCount > 0.U
val intMask = RegInit(0.U(2.W))
io.send.req <> sendReqQueue.io.deq
io.recv.req <> recvReqQueue.io.deq
io.send.comp.ready := sendCompCount < qDepth.U
recvCompQueue.io.enq <> io.recv.comp
outer.interrupts(0) := sendCompValid && intMask(0)
outer.interrupts(1) := recvCompQueue.io.deq.valid && intMask(1)
val sendReqSpace = (qDepth.U - sendReqCount)
val recvReqSpace = (qDepth.U - recvReqCount)
def sendCompRead = (ready: Bool) => {
sendCompDown := sendCompValid && ready
(sendCompValid, true.B)
}
val txcsumReqQueue = Module(new HellaQueue(qDepth)(UInt(49.W)))
val rxcsumResQueue = Module(new HellaQueue(qDepth)(UInt(2.W)))
val csumEnable = RegInit(false.B)
io.txcsumReq.valid := txcsumReqQueue.io.deq.valid
io.txcsumReq.bits := txcsumReqQueue.io.deq.bits.asTypeOf(new ChecksumRewriteRequest)
txcsumReqQueue.io.deq.ready := io.txcsumReq.ready
rxcsumResQueue.io.enq.valid := io.rxcsumRes.valid
rxcsumResQueue.io.enq.bits := io.rxcsumRes.bits.asUInt
io.rxcsumRes.ready := rxcsumResQueue.io.enq.ready
io.csumEnable := csumEnable
outer.tlRegmap(
0x00 -> Seq(RegField.w(NET_IF_WIDTH, sendReqQueue.io.enq)),
0x08 -> Seq(RegField.w(NET_IF_WIDTH, recvReqQueue.io.enq)),
0x10 -> Seq(RegField.r(1, sendCompRead)),
0x12 -> Seq(RegField.r(NET_LEN_BITS, recvCompQueue.io.deq)),
0x14 -> Seq(
RegField.r(8, sendReqSpace),
RegField.r(8, recvReqSpace),
RegField.r(8, sendCompCount),
RegField.r(8, recvCompCount)),
0x18 -> Seq(RegField.r(ETH_MAC_BITS, io.macAddr)),
0x20 -> Seq(RegField(2, intMask)),
0x28 -> Seq(RegField.w(49, txcsumReqQueue.io.enq)),
0x30 -> Seq(RegField.r(2, rxcsumResQueue.io.deq)),
0x31 -> Seq(RegField(1, csumEnable)))
}
class IceNicSendPath(nInputTaps: Int = 0)(implicit p: Parameters)
extends NICLazyModule {
val reader = LazyModule(new StreamReader(
nMemXacts, outBufFlits, maxAcquireBytes))
val node = reader.node
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
val io = IO(new Bundle {
val send = Flipped(new IceNicSendIO)
val tap = Flipped(Vec(nInputTaps, Decoupled(new StreamChannel(NET_IF_WIDTH))))
val out = Decoupled(new StreamChannel(NET_IF_WIDTH))
val rlimit = Input(new RateLimiterSettings)
val csum = checksumOffload.option(new Bundle {
val req = Flipped(Decoupled(new ChecksumRewriteRequest))
val enable = Input(Bool())
})
})
val readreq = reader.module.io.req
io.send.req.ready := readreq.ready
readreq.valid := io.send.req.valid
readreq.bits.address := io.send.req.bits(47, 0)
readreq.bits.length := io.send.req.bits(62, 48)
readreq.bits.partial := io.send.req.bits(63)
io.send.comp <> reader.module.io.resp
val preArbOut = if (checksumOffload) {
val readerOut = reader.module.io.out
val arb = Module(new PacketArbiter(2))
val bufFlits = (packetMaxBytes - 1) / NET_IF_BYTES + 1
val rewriter = Module(new ChecksumRewrite(NET_IF_WIDTH, bufFlits))
val enable = io.csum.get.enable
rewriter.io.req <> io.csum.get.req
arb.io.in(0) <> rewriter.io.stream.out
arb.io.in(1).valid := !enable && readerOut.valid
arb.io.in(1).bits := readerOut.bits
rewriter.io.stream.in.valid := enable && readerOut.valid
rewriter.io.stream.in.bits := readerOut.bits
readerOut.ready := Mux(enable,
rewriter.io.stream.in.ready, arb.io.in(1).ready)
arb.io.out
} else { reader.module.io.out }
val unlimitedOut = if (nInputTaps > 0) {
val bufWords = (packetMaxBytes - 1) / NET_IF_BYTES + 1
val inputs = (preArbOut +: io.tap).map { in =>
// The packet collection buffer doesn't allow sending the first flit
// of a packet until the last flit is received.
// This ensures that we don't lock the arbiter while waiting for data
// to arrive, which could cause deadocks.
val buffer = Module(new PacketCollectionBuffer(bufWords))
buffer.io.in <> in
buffer.io.out
}
val arb = Module(new PacketArbiter(inputs.size, rr = true))
arb.io.in <> inputs
arb.io.out
} else { preArbOut }
val limiter = Module(new RateLimiter(new StreamChannel(NET_IF_WIDTH)))
limiter.io.in <> unlimitedOut
limiter.io.settings := io.rlimit
io.out <> limiter.io.out
}
}
class IceNicWriter(implicit p: Parameters) extends NICLazyModule {
val writer = LazyModule(new StreamWriter(nMemXacts, maxAcquireBytes))
val node = writer.node
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
val io = IO(new Bundle {
val recv = Flipped(new IceNicRecvIO)
val in = Flipped(Decoupled(new StreamChannel(NET_IF_WIDTH)))
val length = Flipped(Valid(UInt(NET_LEN_BITS.W)))
})
val streaming = RegInit(false.B)
val byteAddrBits = log2Ceil(NET_IF_BYTES)
val helper = DecoupledHelper(
io.recv.req.valid,
writer.module.io.req.ready,
io.length.valid, !streaming)
writer.module.io.req.valid := helper.fire(writer.module.io.req.ready)
writer.module.io.req.bits.address := io.recv.req.bits
writer.module.io.req.bits.length := io.length.bits
io.recv.req.ready := helper.fire(io.recv.req.valid)
writer.module.io.in.valid := io.in.valid && streaming
writer.module.io.in.bits := io.in.bits
io.in.ready := writer.module.io.in.ready && streaming
io.recv.comp <> writer.module.io.resp
when (io.recv.req.fire) { streaming := true.B }
when (io.in.fire && io.in.bits.last) { streaming := false.B }
}
}
/*
* Recv frames
*/
class IceNicRecvPath(val tapFuncs: Seq[EthernetHeader => Bool] = Nil)
(implicit p: Parameters) extends LazyModule {
val writer = LazyModule(new IceNicWriter)
val node = TLIdentityNode()
node := writer.node
lazy val module = new IceNicRecvPathModule(this)
}
class IceNicRecvPathModule(val outer: IceNicRecvPath)
extends LazyModuleImp(outer) with HasNICParameters {
val io = IO(new Bundle {
val recv = Flipped(new IceNicRecvIO)
val in = Flipped(Decoupled(new StreamChannel(NET_IF_WIDTH))) // input stream
val tap = Vec(outer.tapFuncs.length, Decoupled(new StreamChannel(NET_IF_WIDTH)))
val csum = checksumOffload.option(new Bundle {
val res = Decoupled(new TCPChecksumOffloadResult)
val enable = Input(Bool())
})
val buf_free = Output(Vec(1 + outer.tapFuncs.length, UInt(8.W)))
})
def tapOutToDropCheck(tapOut: EthernetHeader => Bool) = {
(header: EthernetHeader, ch: StreamChannel, update: Bool) => {
val first = RegInit(true.B)
val drop = tapOut(header) && first
val dropReg = RegInit(false.B)
when (update && first) { first := false.B; dropReg := drop }
when (update && ch.last) { first := true.B; dropReg := false.B }
drop || dropReg
}
}
def duplicateStream(in: DecoupledIO[StreamChannel], outs: Seq[DecoupledIO[StreamChannel]]) = {
outs.foreach { out =>
out.valid := in.valid
out.bits := in.bits
}
in.ready := outs.head.ready
val outReadys = Cat(outs.map(_.ready))
assert(outReadys.andR || !outReadys.orR,
"Duplicated streams must all be ready simultaneously")
outs
}
def invertCheck(check: (EthernetHeader, StreamChannel, Bool) => Bool) =
(eth: EthernetHeader, ch: StreamChannel, up: Bool) => !check(eth, ch, up)
val tapDropChecks = outer.tapFuncs.map(func => tapOutToDropCheck(func))
val pauseDropCheck = if (usePauser) Some(PauseDropCheck(_, _, _)) else None
val allDropChecks =
// Drop checks for the primary buffer
// Drop if the packet should be tapped out or is a pause frame
Seq(tapDropChecks ++ pauseDropCheck.toSeq) ++
// Drop checks for the tap buffers
// For each tap, drop if the packet doesn't match the tap function or is a pause frame
tapDropChecks.map(check => invertCheck(check) +: pauseDropCheck.toSeq)
val buffers = allDropChecks.map(dropChecks =>
Module(new NetworkPacketBuffer(
inBufFlits,
maxBytes = packetMaxBytes,
dropChecks = dropChecks, dropless = usePauser)))
duplicateStream(io.in, buffers.map(_.io.stream.in))
io.buf_free := buffers.map(_.io.free)
io.tap <> buffers.tail.map(_.io.stream.out)
val bufout = buffers.head.io.stream.out
val buflen = buffers.head.io.length
val (csumout, recvreq) = (if (checksumOffload) {
val offload = Module(new TCPChecksumOffload(NET_IF_WIDTH))
val offloadReady = offload.io.in.ready || !io.csum.get.enable
val out = Wire(Decoupled(new StreamChannel(NET_IF_WIDTH)))
val recvreq = Wire(Decoupled(UInt(NET_IF_WIDTH.W)))
val reqq = Module(new Queue(UInt(NET_IF_WIDTH.W), 1))
val enqHelper = DecoupledHelper(
io.recv.req.valid, reqq.io.enq.ready, recvreq.ready)
val deqHelper = DecoupledHelper(
bufout.valid, offloadReady, out.ready, reqq.io.deq.valid)
reqq.io.enq.valid := enqHelper.fire(reqq.io.enq.ready)
reqq.io.enq.bits := io.recv.req.bits
io.recv.req.ready := enqHelper.fire(io.recv.req.valid)
recvreq.valid := enqHelper.fire(recvreq.ready)
recvreq.bits := io.recv.req.bits
out.valid := deqHelper.fire(out.ready)
out.bits := bufout.bits
offload.io.in.valid := deqHelper.fire(offloadReady, io.csum.get.enable)
offload.io.in.bits := bufout.bits
bufout.ready := deqHelper.fire(bufout.valid)
reqq.io.deq.ready := deqHelper.fire(reqq.io.deq.valid, bufout.bits.last)
io.csum.get.res <> offload.io.result
(out, recvreq)
} else { (bufout, io.recv.req) })
val writer = outer.writer.module
writer.io.recv.req <> Queue(recvreq, 1)
io.recv.comp <> writer.io.recv.comp
writer.io.in <> csumout
writer.io.length.valid := buflen.valid
writer.io.length.bits := buflen.bits
}
class NICIO extends StreamIO(NET_IF_WIDTH) {
val macAddr = Input(UInt(ETH_MAC_BITS.W))
val rlimit = Input(new RateLimiterSettings)
val pauser = Input(new PauserSettings)
}
/*
* A simple NIC
*
* Expects ethernet frames (see below), but uses a custom transport
* (see ExtBundle)
*
* Ethernet Frame format:
* 2 bytes | 6 bytes | 6 bytes | 2 bytes | 46-1500B
* Padding | Dest Addr | Source Addr | Type/Len | Data
*
* @address Starting address of MMIO control registers
* @beatBytes Width of memory interface (in bytes)
* @tapOutFuncs Sequence of functions for each output tap.
* Each function takes the header of an Ethernet frame
* and returns Bool that is true if matching and false if not.
* @nInputTaps Number of input taps
*
*/
class IceNIC(address: BigInt, beatBytes: Int = 8,
tapOutFuncs: Seq[EthernetHeader => Bool] = Nil,
nInputTaps: Int = 0)
(implicit p: Parameters) extends NICLazyModule {
val control = LazyModule(new IceNicController(
IceNicControllerParams(address, beatBytes)))
val sendPath = LazyModule(new IceNicSendPath(nInputTaps))
val recvPath = LazyModule(new IceNicRecvPath(tapOutFuncs))
val mmionode = TLIdentityNode()
val dmanode = TLIdentityNode()
val intnode = control.intXing(NoCrossing)
control.node := TLAtomicAutomata() := mmionode
dmanode := TLWidthWidget(NET_IF_BYTES) := sendPath.node
dmanode := TLWidthWidget(NET_IF_BYTES) := recvPath.node
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
val io = IO(new Bundle {
val ext = new NICIO
val tapOut = Vec(tapOutFuncs.length, Decoupled(new StreamChannel(NET_IF_WIDTH)))
val tapIn = Flipped(Vec(nInputTaps, Decoupled(new StreamChannel(NET_IF_WIDTH))))
})
sendPath.module.io.send <> control.module.io.send
recvPath.module.io.recv <> control.module.io.recv
// connect externally
if (usePauser) {
val pauser = Module(new Pauser(inBufFlits, 1 + tapOutFuncs.length))
pauser.io.int.out <> sendPath.module.io.out
recvPath.module.io.in <> pauser.io.int.in
io.ext.out <> pauser.io.ext.out
pauser.io.ext.in <> io.ext.in
pauser.io.in_free := recvPath.module.io.buf_free
pauser.io.macAddr := io.ext.macAddr
pauser.io.settings := io.ext.pauser
} else {
recvPath.module.io.in <> io.ext.in
io.ext.out <> sendPath.module.io.out
}
control.module.io.macAddr := io.ext.macAddr
sendPath.module.io.rlimit := io.ext.rlimit
io.tapOut <> recvPath.module.io.tap
sendPath.module.io.tap <> io.tapIn
if (checksumOffload) {
sendPath.module.io.csum.get.req <> control.module.io.txcsumReq
sendPath.module.io.csum.get.enable := control.module.io.csumEnable
control.module.io.rxcsumRes <> recvPath.module.io.csum.get.res
recvPath.module.io.csum.get.enable := control.module.io.csumEnable
} else {
control.module.io.txcsumReq.ready := false.B
control.module.io.rxcsumRes.valid := false.B
control.module.io.rxcsumRes.bits := DontCare
}
}
}
class SimNetwork extends BlackBox with HasBlackBoxResource {
val io = IO(new Bundle {
val clock = Input(Clock())
val reset = Input(Bool())
val net = Flipped(new NICIOvonly)
})
addResource("/vsrc/SimNetwork.v")
addResource("/csrc/SimNetwork.cc")
addResource("/csrc/device.h")
addResource("/csrc/device.cc")
addResource("/csrc/switch.h")
addResource("/csrc/switch.cc")
addResource("/csrc/packet.h")
}
class NICIOvonly extends Bundle {
val in = Flipped(Valid(new StreamChannel(NET_IF_WIDTH)))
val out = Valid(new StreamChannel(NET_IF_WIDTH))
val macAddr = Input(UInt(ETH_MAC_BITS.W))
val rlimit = Input(new RateLimiterSettings)
val pauser = Input(new PauserSettings)
}
object NICIOvonly {
def apply(nicio: NICIO): NICIOvonly = {
val vonly = Wire(new NICIOvonly)
vonly.out.valid := nicio.out.valid
vonly.out.bits := nicio.out.bits
nicio.out.ready := true.B
nicio.in.valid := vonly.in.valid
nicio.in.bits := vonly.in.bits
assert(!vonly.in.valid || nicio.in.ready, "NIC input not ready for valid")
nicio.macAddr := vonly.macAddr
nicio.rlimit := vonly.rlimit
nicio.pauser := vonly.pauser
vonly
}
}
object NICIO {
def apply(vonly: NICIOvonly): NICIO = {
val nicio = Wire(new NICIO)
assert(!vonly.out.valid || nicio.out.ready)
nicio.out.valid := vonly.out.valid
nicio.out.bits := vonly.out.bits
vonly.in.valid := nicio.in.valid
vonly.in.bits := nicio.in.bits
nicio.in.ready := true.B
vonly.macAddr := nicio.macAddr
vonly.rlimit := nicio.rlimit
vonly.pauser := nicio.pauser
nicio
}
}
trait CanHavePeripheryIceNIC { this: BaseSubsystem =>
private val address = BigInt(0x10016000)
private val portName = "Ice-NIC"
val icenicOpt = p(NICKey).map { params =>
val manager = locateTLBusWrapper(p(NICAttachKey).slaveWhere)
val client = locateTLBusWrapper(p(NICAttachKey).masterWhere)
// TODO: currently the controller is in the clock domain of the bus which masters it
// we assume this is same as the clock domain of the bus the controller masters
val domain = manager.generateSynchronousDomain.suggestName("icenic_domain")
val icenic = domain { LazyModule(new IceNIC(address, manager.beatBytes)) }
manager.coupleTo(portName) { icenic.mmionode := TLFragmenter(manager.beatBytes, manager.blockBytes) := _ }
client.coupleFrom(portName) { _ :=* icenic.dmanode }
ibus.fromSync := icenic.intnode
val inner_io = domain { InModuleBody {
val inner_io = IO(new NICIOvonly).suggestName("nic")
inner_io <> NICIOvonly(icenic.module.io.ext)
inner_io
} }
val outer_io = InModuleBody {
val outer_io = IO(new ClockedIO(new NICIOvonly)).suggestName("nic")
outer_io.bits <> inner_io
outer_io.clock := domain.module.clock
outer_io
}
outer_io
}
}
object NicLoopback {
def connect(net: Option[NICIOvonly], nicConf: Option[NICConfig], qDepth: Int, latency: Int = 10): Unit = {
net.foreach { netio =>
import PauseConsts.BT_PER_QUANTA
val packetWords = nicConf.get.packetMaxBytes / NET_IF_BYTES
val packetQuanta = (nicConf.get.packetMaxBytes * 8) / BT_PER_QUANTA
netio.macAddr := PlusArg("macaddr")
netio.rlimit.inc := PlusArg("rlimit-inc", 1)
netio.rlimit.period := PlusArg("rlimit-period", 1)
netio.rlimit.size := PlusArg("rlimit-size", 8)
netio.pauser.threshold := PlusArg("pauser-threshold", 2 * packetWords + latency)
netio.pauser.quanta := PlusArg("pauser-quanta", 2 * packetQuanta)
netio.pauser.refresh := PlusArg("pauser-refresh", packetWords)
if (nicConf.get.usePauser) {
val pauser = Module(new PauserComplex(qDepth))
pauser.io.ext.flipConnect(NetDelay(NICIO(netio), latency))
pauser.io.int.out <> pauser.io.int.in
pauser.io.macAddr := netio.macAddr + (1 << 40).U
pauser.io.settings := netio.pauser
} else {
netio.in := Pipe(netio.out, latency)
}
netio.in.bits.keep := NET_FULL_KEEP
}
}
def connect(net: NICIOvonly, nicConf: NICConfig): Unit = {
val packetWords = nicConf.packetMaxBytes / NET_IF_BYTES
NicLoopback.connect(Some(net), Some(nicConf), 4 * packetWords)
}
}
object SimNetwork {
def connect(net: Option[NICIOvonly], clock: Clock, reset: Bool) {
net.foreach { netio =>
val sim = Module(new SimNetwork)
sim.io.clock := clock
sim.io.reset := reset
sim.io.net <> netio
}
}
}
File WidthWidget.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.AddressSet
import freechips.rocketchip.util.{Repeater, UIntToOH1}
// innBeatBytes => the new client-facing bus width
class TLWidthWidget(innerBeatBytes: Int)(implicit p: Parameters) extends LazyModule
{
private def noChangeRequired(manager: TLManagerPortParameters) = manager.beatBytes == innerBeatBytes
val node = new TLAdapterNode(
clientFn = { case c => c },
managerFn = { case m => m.v1copy(beatBytes = innerBeatBytes) }){
override def circuitIdentity = edges.out.map(_.manager).forall(noChangeRequired)
}
override lazy val desiredName = s"TLWidthWidget$innerBeatBytes"
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
def merge[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T]) = {
val inBytes = edgeIn.manager.beatBytes
val outBytes = edgeOut.manager.beatBytes
val ratio = outBytes / inBytes
val keepBits = log2Ceil(outBytes)
val dropBits = log2Ceil(inBytes)
val countBits = log2Ceil(ratio)
val size = edgeIn.size(in.bits)
val hasData = edgeIn.hasData(in.bits)
val limit = UIntToOH1(size, keepBits) >> dropBits
val count = RegInit(0.U(countBits.W))
val first = count === 0.U
val last = count === limit || !hasData
val enable = Seq.tabulate(ratio) { i => !((count ^ i.U) & limit).orR }
val corrupt_reg = RegInit(false.B)
val corrupt_in = edgeIn.corrupt(in.bits)
val corrupt_out = corrupt_in || corrupt_reg
when (in.fire) {
count := count + 1.U
corrupt_reg := corrupt_out
when (last) {
count := 0.U
corrupt_reg := false.B
}
}
def helper(idata: UInt): UInt = {
// rdata is X until the first time a multi-beat write occurs.
// Prevent the X from leaking outside by jamming the mux control until
// the first time rdata is written (and hence no longer X).
val rdata_written_once = RegInit(false.B)
val masked_enable = enable.map(_ || !rdata_written_once)
val odata = Seq.fill(ratio) { WireInit(idata) }
val rdata = Reg(Vec(ratio-1, chiselTypeOf(idata)))
val pdata = rdata :+ idata
val mdata = (masked_enable zip (odata zip pdata)) map { case (e, (o, p)) => Mux(e, o, p) }
when (in.fire && !last) {
rdata_written_once := true.B
(rdata zip mdata) foreach { case (r, m) => r := m }
}
Cat(mdata.reverse)
}
in.ready := out.ready || !last
out.valid := in.valid && last
out.bits := in.bits
// Don't put down hardware if we never carry data
edgeOut.data(out.bits) := (if (edgeIn.staticHasData(in.bits) == Some(false)) 0.U else helper(edgeIn.data(in.bits)))
edgeOut.corrupt(out.bits) := corrupt_out
(out.bits, in.bits) match {
case (o: TLBundleA, i: TLBundleA) => o.mask := edgeOut.mask(o.address, o.size) & Mux(hasData, helper(i.mask), ~0.U(outBytes.W))
case (o: TLBundleB, i: TLBundleB) => o.mask := edgeOut.mask(o.address, o.size) & Mux(hasData, helper(i.mask), ~0.U(outBytes.W))
case (o: TLBundleC, i: TLBundleC) => ()
case (o: TLBundleD, i: TLBundleD) => ()
case _ => require(false, "Impossible bundle combination in WidthWidget")
}
}
def split[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T], sourceMap: UInt => UInt) = {
val inBytes = edgeIn.manager.beatBytes
val outBytes = edgeOut.manager.beatBytes
val ratio = inBytes / outBytes
val keepBits = log2Ceil(inBytes)
val dropBits = log2Ceil(outBytes)
val countBits = log2Ceil(ratio)
val size = edgeIn.size(in.bits)
val hasData = edgeIn.hasData(in.bits)
val limit = UIntToOH1(size, keepBits) >> dropBits
val count = RegInit(0.U(countBits.W))
val first = count === 0.U
val last = count === limit || !hasData
when (out.fire) {
count := count + 1.U
when (last) { count := 0.U }
}
// For sub-beat transfer, extract which part matters
val sel = in.bits match {
case a: TLBundleA => a.address(keepBits-1, dropBits)
case b: TLBundleB => b.address(keepBits-1, dropBits)
case c: TLBundleC => c.address(keepBits-1, dropBits)
case d: TLBundleD => {
val sel = sourceMap(d.source)
val hold = Mux(first, sel, RegEnable(sel, first)) // a_first is not for whole xfer
hold & ~limit // if more than one a_first/xfer, the address must be aligned anyway
}
}
val index = sel | count
def helper(idata: UInt, width: Int): UInt = {
val mux = VecInit.tabulate(ratio) { i => idata((i+1)*outBytes*width-1, i*outBytes*width) }
mux(index)
}
out.bits := in.bits
out.valid := in.valid
in.ready := out.ready
// Don't put down hardware if we never carry data
edgeOut.data(out.bits) := (if (edgeIn.staticHasData(in.bits) == Some(false)) 0.U else helper(edgeIn.data(in.bits), 8))
(out.bits, in.bits) match {
case (o: TLBundleA, i: TLBundleA) => o.mask := helper(i.mask, 1)
case (o: TLBundleB, i: TLBundleB) => o.mask := helper(i.mask, 1)
case (o: TLBundleC, i: TLBundleC) => () // replicating corrupt to all beats is ok
case (o: TLBundleD, i: TLBundleD) => ()
case _ => require(false, "Impossbile bundle combination in WidthWidget")
}
// Repeat the input if we're not last
!last
}
def splice[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T], sourceMap: UInt => UInt) = {
if (edgeIn.manager.beatBytes == edgeOut.manager.beatBytes) {
// nothing to do; pass it through
out.bits := in.bits
out.valid := in.valid
in.ready := out.ready
} else if (edgeIn.manager.beatBytes > edgeOut.manager.beatBytes) {
// split input to output
val repeat = Wire(Bool())
val repeated = Repeater(in, repeat)
val cated = Wire(chiselTypeOf(repeated))
cated <> repeated
edgeIn.data(cated.bits) := Cat(
edgeIn.data(repeated.bits)(edgeIn.manager.beatBytes*8-1, edgeOut.manager.beatBytes*8),
edgeIn.data(in.bits)(edgeOut.manager.beatBytes*8-1, 0))
repeat := split(edgeIn, cated, edgeOut, out, sourceMap)
} else {
// merge input to output
merge(edgeIn, in, edgeOut, out)
}
}
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
// If the master is narrower than the slave, the D channel must be narrowed.
// This is tricky, because the D channel has no address data.
// Thus, you don't know which part of a sub-beat transfer to extract.
// To fix this, we record the relevant address bits for all sources.
// The assumption is that this sort of situation happens only where
// you connect a narrow master to the system bus, so there are few sources.
def sourceMap(source_bits: UInt) = {
val source = if (edgeIn.client.endSourceId == 1) 0.U(0.W) else source_bits
require (edgeOut.manager.beatBytes > edgeIn.manager.beatBytes)
val keepBits = log2Ceil(edgeOut.manager.beatBytes)
val dropBits = log2Ceil(edgeIn.manager.beatBytes)
val sources = Reg(Vec(edgeIn.client.endSourceId, UInt((keepBits-dropBits).W)))
val a_sel = in.a.bits.address(keepBits-1, dropBits)
when (in.a.fire) {
if (edgeIn.client.endSourceId == 1) { // avoid extraction-index-width warning
sources(0) := a_sel
} else {
sources(in.a.bits.source) := a_sel
}
}
// depopulate unused source registers:
edgeIn.client.unusedSources.foreach { id => sources(id) := 0.U }
val bypass = in.a.valid && in.a.bits.source === source
if (edgeIn.manager.minLatency > 0) sources(source)
else Mux(bypass, a_sel, sources(source))
}
splice(edgeIn, in.a, edgeOut, out.a, sourceMap)
splice(edgeOut, out.d, edgeIn, in.d, sourceMap)
if (edgeOut.manager.anySupportAcquireB && edgeIn.client.anySupportProbe) {
splice(edgeOut, out.b, edgeIn, in.b, sourceMap)
splice(edgeIn, in.c, edgeOut, out.c, sourceMap)
out.e.valid := in.e.valid
out.e.bits := in.e.bits
in.e.ready := out.e.ready
} else {
in.b.valid := false.B
in.c.ready := true.B
in.e.ready := true.B
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
}
}
}
}
object TLWidthWidget
{
def apply(innerBeatBytes: Int)(implicit p: Parameters): TLNode =
{
val widget = LazyModule(new TLWidthWidget(innerBeatBytes))
widget.node
}
def apply(wrapper: TLBusWrapper)(implicit p: Parameters): TLNode = apply(wrapper.beatBytes)
}
// Synthesizable unit tests
import freechips.rocketchip.unittest._
class TLRAMWidthWidget(first: Int, second: Int, txns: Int)(implicit p: Parameters) extends LazyModule {
val fuzz = LazyModule(new TLFuzzer(txns))
val model = LazyModule(new TLRAMModel("WidthWidget"))
val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff)))
(ram.node
:= TLDelayer(0.1)
:= TLFragmenter(4, 256)
:= TLWidthWidget(second)
:= TLWidthWidget(first)
:= TLDelayer(0.1)
:= model.node
:= fuzz.node)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) with UnitTestModule {
io.finished := fuzz.module.io.finished
}
}
class TLRAMWidthWidgetTest(little: Int, big: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
val dut = Module(LazyModule(new TLRAMWidthWidget(little,big,txns)).module)
dut.io.start := DontCare
io.finished := dut.io.finished
}
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
| module IceNIC( // @[NIC.scala:448:9]
input clock, // @[NIC.scala:448:9]
input reset, // @[NIC.scala:448:9]
output auto_intsink_out_0, // @[LazyModuleImp.scala:107:25]
output auto_intsink_out_1, // @[LazyModuleImp.scala:107:25]
input auto_dma_out_1_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_dma_out_1_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_dma_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_dma_out_1_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_dma_out_1_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_dma_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_dma_out_1_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_dma_out_1_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_dma_out_1_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_dma_out_1_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_dma_out_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_dma_out_1_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_dma_out_1_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_dma_out_1_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_dma_out_1_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_dma_out_1_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_dma_out_1_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_dma_out_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_dma_out_0_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_dma_out_0_a_valid, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_dma_out_0_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_dma_out_0_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_dma_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_dma_out_0_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input auto_dma_out_0_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_dma_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_dma_out_0_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_dma_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_dma_out_0_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_dma_out_0_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_dma_out_0_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_dma_out_0_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_dma_out_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_mmio_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_mmio_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_mmio_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_mmio_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_mmio_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [11:0] auto_mmio_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [28:0] auto_mmio_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_mmio_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_mmio_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_mmio_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_mmio_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_mmio_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_mmio_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_mmio_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [11:0] auto_mmio_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_mmio_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
input io_ext_in_valid, // @[NIC.scala:449:16]
input [63:0] io_ext_in_bits_data, // @[NIC.scala:449:16]
input [7:0] io_ext_in_bits_keep, // @[NIC.scala:449:16]
input io_ext_in_bits_last, // @[NIC.scala:449:16]
output io_ext_out_valid, // @[NIC.scala:449:16]
output [63:0] io_ext_out_bits_data, // @[NIC.scala:449:16]
output [7:0] io_ext_out_bits_keep, // @[NIC.scala:449:16]
output io_ext_out_bits_last, // @[NIC.scala:449:16]
input [47:0] io_ext_macAddr, // @[NIC.scala:449:16]
input [7:0] io_ext_rlimit_inc, // @[NIC.scala:449:16]
input [7:0] io_ext_rlimit_period, // @[NIC.scala:449:16]
input [7:0] io_ext_rlimit_size, // @[NIC.scala:449:16]
input [15:0] io_ext_pauser_threshold, // @[NIC.scala:449:16]
input [15:0] io_ext_pauser_quanta, // @[NIC.scala:449:16]
input [15:0] io_ext_pauser_refresh // @[NIC.scala:449:16]
);
wire controlXingOut_d_valid; // @[MixedNode.scala:542:17]
wire [63:0] controlXingOut_d_bits_data; // @[MixedNode.scala:542:17]
wire [11:0] controlXingOut_d_bits_source; // @[MixedNode.scala:542:17]
wire [1:0] controlXingOut_d_bits_size; // @[MixedNode.scala:542:17]
wire [2:0] controlXingOut_d_bits_opcode; // @[MixedNode.scala:542:17]
wire controlXingOut_a_ready; // @[MixedNode.scala:542:17]
wire mmionodeOut_d_valid; // @[MixedNode.scala:542:17]
wire [63:0] mmionodeOut_d_bits_data; // @[MixedNode.scala:542:17]
wire [11:0] mmionodeOut_d_bits_source; // @[MixedNode.scala:542:17]
wire [1:0] mmionodeOut_d_bits_size; // @[MixedNode.scala:542:17]
wire [2:0] mmionodeOut_d_bits_opcode; // @[MixedNode.scala:542:17]
wire mmionodeOut_a_ready; // @[MixedNode.scala:542:17]
wire widget_1_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9]
wire widget_1_auto_anon_out_d_ready; // @[WidthWidget.scala:27:9]
wire widget_1_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire [63:0] widget_1_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9]
wire widget_1_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [3:0] widget_1_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9]
wire [2:0] widget_1_auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9]
wire [3:0] widget_1_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9]
wire [1:0] widget_1_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] widget_1_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire widget_1_auto_anon_out_a_valid; // @[WidthWidget.scala:27:9]
wire widget_1_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9]
wire [63:0] widget_1_auto_anon_out_a_bits_data; // @[WidthWidget.scala:27:9]
wire [7:0] widget_1_auto_anon_out_a_bits_mask; // @[WidthWidget.scala:27:9]
wire [31:0] widget_1_auto_anon_out_a_bits_address; // @[WidthWidget.scala:27:9]
wire [2:0] widget_1_auto_anon_out_a_bits_source; // @[WidthWidget.scala:27:9]
wire [3:0] widget_1_auto_anon_out_a_bits_size; // @[WidthWidget.scala:27:9]
wire [2:0] widget_1_auto_anon_out_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire widget_1_auto_anon_in_d_ready; // @[WidthWidget.scala:27:9]
wire widget_1_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9]
wire [63:0] widget_1_auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9]
wire [7:0] widget_1_auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9]
wire [31:0] widget_1_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9]
wire [2:0] widget_1_auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9]
wire [3:0] widget_1_auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9]
wire [2:0] widget_1_auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire [63:0] widget_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [3:0] widget_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9]
wire [3:0] widget_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9]
wire [1:0] widget_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_a_valid; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9]
wire [7:0] widget_auto_anon_out_a_bits_mask; // @[WidthWidget.scala:27:9]
wire [31:0] widget_auto_anon_out_a_bits_address; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_out_a_bits_source; // @[WidthWidget.scala:27:9]
wire [3:0] widget_auto_anon_out_a_bits_size; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9]
wire [7:0] widget_auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9]
wire [31:0] widget_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9]
wire [3:0] widget_auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9]
wire _recvPath_io_recv_req_ready; // @[NIC.scala:437:28]
wire _recvPath_io_recv_comp_valid; // @[NIC.scala:437:28]
wire [15:0] _recvPath_io_recv_comp_bits; // @[NIC.scala:437:28]
wire _recvPath_io_csum_res_valid; // @[NIC.scala:437:28]
wire _recvPath_io_csum_res_bits_correct; // @[NIC.scala:437:28]
wire _recvPath_io_csum_res_bits_checked; // @[NIC.scala:437:28]
wire _sendPath_io_send_req_ready; // @[NIC.scala:436:28]
wire _sendPath_io_send_comp_valid; // @[NIC.scala:436:28]
wire _sendPath_io_csum_req_ready; // @[NIC.scala:436:28]
wire _control_io_send_req_valid; // @[NIC.scala:434:27]
wire [63:0] _control_io_send_req_bits; // @[NIC.scala:434:27]
wire _control_io_send_comp_ready; // @[NIC.scala:434:27]
wire _control_io_recv_req_valid; // @[NIC.scala:434:27]
wire [63:0] _control_io_recv_req_bits; // @[NIC.scala:434:27]
wire _control_io_recv_comp_ready; // @[NIC.scala:434:27]
wire _control_io_txcsumReq_valid; // @[NIC.scala:434:27]
wire _control_io_txcsumReq_bits_check; // @[NIC.scala:434:27]
wire [15:0] _control_io_txcsumReq_bits_offset; // @[NIC.scala:434:27]
wire [15:0] _control_io_txcsumReq_bits_start; // @[NIC.scala:434:27]
wire [15:0] _control_io_txcsumReq_bits_init; // @[NIC.scala:434:27]
wire _control_io_rxcsumRes_ready; // @[NIC.scala:434:27]
wire _control_io_csumEnable; // @[NIC.scala:434:27]
wire auto_dma_out_1_a_ready_0 = auto_dma_out_1_a_ready; // @[NIC.scala:448:9]
wire auto_dma_out_1_d_valid_0 = auto_dma_out_1_d_valid; // @[NIC.scala:448:9]
wire [2:0] auto_dma_out_1_d_bits_opcode_0 = auto_dma_out_1_d_bits_opcode; // @[NIC.scala:448:9]
wire [1:0] auto_dma_out_1_d_bits_param_0 = auto_dma_out_1_d_bits_param; // @[NIC.scala:448:9]
wire [3:0] auto_dma_out_1_d_bits_size_0 = auto_dma_out_1_d_bits_size; // @[NIC.scala:448:9]
wire [2:0] auto_dma_out_1_d_bits_source_0 = auto_dma_out_1_d_bits_source; // @[NIC.scala:448:9]
wire [3:0] auto_dma_out_1_d_bits_sink_0 = auto_dma_out_1_d_bits_sink; // @[NIC.scala:448:9]
wire auto_dma_out_1_d_bits_denied_0 = auto_dma_out_1_d_bits_denied; // @[NIC.scala:448:9]
wire [63:0] auto_dma_out_1_d_bits_data_0 = auto_dma_out_1_d_bits_data; // @[NIC.scala:448:9]
wire auto_dma_out_1_d_bits_corrupt_0 = auto_dma_out_1_d_bits_corrupt; // @[NIC.scala:448:9]
wire auto_dma_out_0_a_ready_0 = auto_dma_out_0_a_ready; // @[NIC.scala:448:9]
wire auto_dma_out_0_d_valid_0 = auto_dma_out_0_d_valid; // @[NIC.scala:448:9]
wire [2:0] auto_dma_out_0_d_bits_opcode_0 = auto_dma_out_0_d_bits_opcode; // @[NIC.scala:448:9]
wire [1:0] auto_dma_out_0_d_bits_param_0 = auto_dma_out_0_d_bits_param; // @[NIC.scala:448:9]
wire [3:0] auto_dma_out_0_d_bits_size_0 = auto_dma_out_0_d_bits_size; // @[NIC.scala:448:9]
wire [2:0] auto_dma_out_0_d_bits_source_0 = auto_dma_out_0_d_bits_source; // @[NIC.scala:448:9]
wire [3:0] auto_dma_out_0_d_bits_sink_0 = auto_dma_out_0_d_bits_sink; // @[NIC.scala:448:9]
wire auto_dma_out_0_d_bits_denied_0 = auto_dma_out_0_d_bits_denied; // @[NIC.scala:448:9]
wire [63:0] auto_dma_out_0_d_bits_data_0 = auto_dma_out_0_d_bits_data; // @[NIC.scala:448:9]
wire auto_dma_out_0_d_bits_corrupt_0 = auto_dma_out_0_d_bits_corrupt; // @[NIC.scala:448:9]
wire auto_mmio_in_a_valid_0 = auto_mmio_in_a_valid; // @[NIC.scala:448:9]
wire [2:0] auto_mmio_in_a_bits_opcode_0 = auto_mmio_in_a_bits_opcode; // @[NIC.scala:448:9]
wire [2:0] auto_mmio_in_a_bits_param_0 = auto_mmio_in_a_bits_param; // @[NIC.scala:448:9]
wire [1:0] auto_mmio_in_a_bits_size_0 = auto_mmio_in_a_bits_size; // @[NIC.scala:448:9]
wire [11:0] auto_mmio_in_a_bits_source_0 = auto_mmio_in_a_bits_source; // @[NIC.scala:448:9]
wire [28:0] auto_mmio_in_a_bits_address_0 = auto_mmio_in_a_bits_address; // @[NIC.scala:448:9]
wire [7:0] auto_mmio_in_a_bits_mask_0 = auto_mmio_in_a_bits_mask; // @[NIC.scala:448:9]
wire [63:0] auto_mmio_in_a_bits_data_0 = auto_mmio_in_a_bits_data; // @[NIC.scala:448:9]
wire auto_mmio_in_a_bits_corrupt_0 = auto_mmio_in_a_bits_corrupt; // @[NIC.scala:448:9]
wire auto_mmio_in_d_ready_0 = auto_mmio_in_d_ready; // @[NIC.scala:448:9]
wire io_ext_in_valid_0 = io_ext_in_valid; // @[NIC.scala:448:9]
wire [63:0] io_ext_in_bits_data_0 = io_ext_in_bits_data; // @[NIC.scala:448:9]
wire [7:0] io_ext_in_bits_keep_0 = io_ext_in_bits_keep; // @[NIC.scala:448:9]
wire io_ext_in_bits_last_0 = io_ext_in_bits_last; // @[NIC.scala:448:9]
wire [47:0] io_ext_macAddr_0 = io_ext_macAddr; // @[NIC.scala:448:9]
wire [7:0] io_ext_rlimit_inc_0 = io_ext_rlimit_inc; // @[NIC.scala:448:9]
wire [7:0] io_ext_rlimit_period_0 = io_ext_rlimit_period; // @[NIC.scala:448:9]
wire [7:0] io_ext_rlimit_size_0 = io_ext_rlimit_size; // @[NIC.scala:448:9]
wire [15:0] io_ext_pauser_threshold_0 = io_ext_pauser_threshold; // @[NIC.scala:448:9]
wire [15:0] io_ext_pauser_quanta_0 = io_ext_pauser_quanta; // @[NIC.scala:448:9]
wire [15:0] io_ext_pauser_refresh_0 = io_ext_pauser_refresh; // @[NIC.scala:448:9]
wire [1:0] auto_mmio_in_d_bits_param = 2'h0; // @[AtomicAutomata.scala:289:29]
wire [1:0] mmionodeOut_d_bits_param = 2'h0; // @[AtomicAutomata.scala:289:29]
wire [1:0] mmionodeIn_d_bits_param = 2'h0; // @[AtomicAutomata.scala:289:29]
wire [1:0] controlXingOut_d_bits_param = 2'h0; // @[AtomicAutomata.scala:289:29]
wire [1:0] controlXingIn_d_bits_param = 2'h0; // @[AtomicAutomata.scala:289:29]
wire auto_dma_out_0_d_ready = 1'h1; // @[WidthWidget.scala:27:9, :230:28]
wire io_ext_in_ready = 1'h1; // @[WidthWidget.scala:27:9, :230:28]
wire io_ext_out_ready = 1'h1; // @[WidthWidget.scala:27:9, :230:28]
wire widget_auto_anon_in_d_ready = 1'h1; // @[WidthWidget.scala:27:9, :230:28]
wire widget_auto_anon_out_d_ready = 1'h1; // @[WidthWidget.scala:27:9, :230:28]
wire widget_anonOut_d_ready = 1'h1; // @[WidthWidget.scala:27:9, :230:28]
wire widget_anonIn_d_ready = 1'h1; // @[WidthWidget.scala:27:9, :230:28]
wire dmanodeOut_d_ready = 1'h1; // @[WidthWidget.scala:27:9, :230:28]
wire dmanodeIn_d_ready = 1'h1; // @[WidthWidget.scala:27:9, :230:28]
wire [63:0] auto_dma_out_0_a_bits_data = 64'h0; // @[WidthWidget.scala:27:9, :230:28]
wire [63:0] widget_auto_anon_in_a_bits_data = 64'h0; // @[WidthWidget.scala:27:9, :230:28]
wire [63:0] widget_auto_anon_out_a_bits_data = 64'h0; // @[WidthWidget.scala:27:9, :230:28]
wire [63:0] widget_anonOut_a_bits_data = 64'h0; // @[WidthWidget.scala:27:9, :230:28]
wire [63:0] widget_anonIn_a_bits_data = 64'h0; // @[WidthWidget.scala:27:9, :230:28]
wire [63:0] dmanodeOut_a_bits_data = 64'h0; // @[WidthWidget.scala:27:9, :230:28]
wire [63:0] dmanodeIn_a_bits_data = 64'h0; // @[WidthWidget.scala:27:9, :230:28]
wire [2:0] auto_dma_out_0_a_bits_opcode = 3'h4; // @[WidthWidget.scala:27:9, :230:28]
wire [2:0] widget_auto_anon_in_a_bits_opcode = 3'h4; // @[WidthWidget.scala:27:9, :230:28]
wire [2:0] widget_auto_anon_out_a_bits_opcode = 3'h4; // @[WidthWidget.scala:27:9, :230:28]
wire [2:0] widget_anonOut_a_bits_opcode = 3'h4; // @[WidthWidget.scala:27:9, :230:28]
wire [2:0] widget_anonIn_a_bits_opcode = 3'h4; // @[WidthWidget.scala:27:9, :230:28]
wire [2:0] dmanodeOut_a_bits_opcode = 3'h4; // @[WidthWidget.scala:27:9, :230:28]
wire [2:0] dmanodeIn_a_bits_opcode = 3'h4; // @[WidthWidget.scala:27:9, :230:28]
wire [2:0] auto_dma_out_1_a_bits_param = 3'h0; // @[WidthWidget.scala:27:9, :230:28]
wire [2:0] auto_dma_out_0_a_bits_param = 3'h0; // @[WidthWidget.scala:27:9, :230:28]
wire [2:0] widget_auto_anon_in_a_bits_param = 3'h0; // @[WidthWidget.scala:27:9, :230:28]
wire [2:0] widget_auto_anon_out_a_bits_param = 3'h0; // @[WidthWidget.scala:27:9, :230:28]
wire [2:0] widget_anonOut_a_bits_param = 3'h0; // @[WidthWidget.scala:27:9, :230:28]
wire [2:0] widget_anonIn_a_bits_param = 3'h0; // @[WidthWidget.scala:27:9, :230:28]
wire [2:0] widget_1_auto_anon_in_a_bits_param = 3'h0; // @[WidthWidget.scala:27:9, :230:28]
wire [2:0] widget_1_auto_anon_out_a_bits_param = 3'h0; // @[WidthWidget.scala:27:9, :230:28]
wire [2:0] widget_1_anonOut_a_bits_param = 3'h0; // @[WidthWidget.scala:27:9, :230:28]
wire [2:0] widget_1_anonIn_a_bits_param = 3'h0; // @[WidthWidget.scala:27:9, :230:28]
wire [2:0] dmanodeOut_a_bits_param = 3'h0; // @[WidthWidget.scala:27:9, :230:28]
wire [2:0] x1_dmanodeOut_a_bits_param = 3'h0; // @[WidthWidget.scala:27:9, :230:28]
wire [2:0] dmanodeIn_a_bits_param = 3'h0; // @[WidthWidget.scala:27:9, :230:28]
wire [2:0] x1_dmanodeIn_a_bits_param = 3'h0; // @[WidthWidget.scala:27:9, :230:28]
wire auto_dma_out_1_a_bits_corrupt = 1'h0; // @[NIC.scala:448:9]
wire auto_dma_out_0_a_bits_corrupt = 1'h0; // @[NIC.scala:448:9]
wire auto_mmio_in_d_bits_sink = 1'h0; // @[NIC.scala:448:9]
wire auto_mmio_in_d_bits_denied = 1'h0; // @[NIC.scala:448:9]
wire auto_mmio_in_d_bits_corrupt = 1'h0; // @[NIC.scala:448:9]
wire widget_auto_anon_in_a_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_a_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9]
wire widget_anonOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire widget_anonIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire widget_1_auto_anon_in_a_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9]
wire widget_1_auto_anon_out_a_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9]
wire widget_1_anonOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire widget_1_anonIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire mmionodeOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17]
wire mmionodeOut_d_bits_denied = 1'h0; // @[MixedNode.scala:542:17]
wire mmionodeOut_d_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire mmionodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17]
wire mmionodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17]
wire mmionodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire dmanodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire x1_dmanodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire dmanodeIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire x1_dmanodeIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire controlXingOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17]
wire controlXingOut_d_bits_denied = 1'h0; // @[MixedNode.scala:542:17]
wire controlXingOut_d_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire controlXingIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17]
wire controlXingIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17]
wire controlXingIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire x1_dmanodeOut_a_ready = auto_dma_out_1_a_ready_0; // @[NIC.scala:448:9]
wire x1_dmanodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] x1_dmanodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [3:0] x1_dmanodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [2:0] x1_dmanodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] x1_dmanodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] x1_dmanodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] x1_dmanodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire x1_dmanodeOut_d_ready; // @[MixedNode.scala:542:17]
wire x1_dmanodeOut_d_valid = auto_dma_out_1_d_valid_0; // @[NIC.scala:448:9]
wire [2:0] x1_dmanodeOut_d_bits_opcode = auto_dma_out_1_d_bits_opcode_0; // @[NIC.scala:448:9]
wire [1:0] x1_dmanodeOut_d_bits_param = auto_dma_out_1_d_bits_param_0; // @[NIC.scala:448:9]
wire [3:0] x1_dmanodeOut_d_bits_size = auto_dma_out_1_d_bits_size_0; // @[NIC.scala:448:9]
wire [2:0] x1_dmanodeOut_d_bits_source = auto_dma_out_1_d_bits_source_0; // @[NIC.scala:448:9]
wire [3:0] x1_dmanodeOut_d_bits_sink = auto_dma_out_1_d_bits_sink_0; // @[NIC.scala:448:9]
wire x1_dmanodeOut_d_bits_denied = auto_dma_out_1_d_bits_denied_0; // @[NIC.scala:448:9]
wire [63:0] x1_dmanodeOut_d_bits_data = auto_dma_out_1_d_bits_data_0; // @[NIC.scala:448:9]
wire x1_dmanodeOut_d_bits_corrupt = auto_dma_out_1_d_bits_corrupt_0; // @[NIC.scala:448:9]
wire dmanodeOut_a_ready = auto_dma_out_0_a_ready_0; // @[NIC.scala:448:9]
wire dmanodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [3:0] dmanodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [2:0] dmanodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] dmanodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] dmanodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire dmanodeOut_d_valid = auto_dma_out_0_d_valid_0; // @[NIC.scala:448:9]
wire [2:0] dmanodeOut_d_bits_opcode = auto_dma_out_0_d_bits_opcode_0; // @[NIC.scala:448:9]
wire [1:0] dmanodeOut_d_bits_param = auto_dma_out_0_d_bits_param_0; // @[NIC.scala:448:9]
wire [3:0] dmanodeOut_d_bits_size = auto_dma_out_0_d_bits_size_0; // @[NIC.scala:448:9]
wire [2:0] dmanodeOut_d_bits_source = auto_dma_out_0_d_bits_source_0; // @[NIC.scala:448:9]
wire [3:0] dmanodeOut_d_bits_sink = auto_dma_out_0_d_bits_sink_0; // @[NIC.scala:448:9]
wire dmanodeOut_d_bits_denied = auto_dma_out_0_d_bits_denied_0; // @[NIC.scala:448:9]
wire [63:0] dmanodeOut_d_bits_data = auto_dma_out_0_d_bits_data_0; // @[NIC.scala:448:9]
wire mmionodeIn_a_ready; // @[MixedNode.scala:551:17]
wire dmanodeOut_d_bits_corrupt = auto_dma_out_0_d_bits_corrupt_0; // @[NIC.scala:448:9]
wire mmionodeIn_a_valid = auto_mmio_in_a_valid_0; // @[NIC.scala:448:9]
wire [2:0] mmionodeIn_a_bits_opcode = auto_mmio_in_a_bits_opcode_0; // @[NIC.scala:448:9]
wire [2:0] mmionodeIn_a_bits_param = auto_mmio_in_a_bits_param_0; // @[NIC.scala:448:9]
wire [1:0] mmionodeIn_a_bits_size = auto_mmio_in_a_bits_size_0; // @[NIC.scala:448:9]
wire [11:0] mmionodeIn_a_bits_source = auto_mmio_in_a_bits_source_0; // @[NIC.scala:448:9]
wire [28:0] mmionodeIn_a_bits_address = auto_mmio_in_a_bits_address_0; // @[NIC.scala:448:9]
wire [7:0] mmionodeIn_a_bits_mask = auto_mmio_in_a_bits_mask_0; // @[NIC.scala:448:9]
wire [63:0] mmionodeIn_a_bits_data = auto_mmio_in_a_bits_data_0; // @[NIC.scala:448:9]
wire mmionodeIn_a_bits_corrupt = auto_mmio_in_a_bits_corrupt_0; // @[NIC.scala:448:9]
wire mmionodeIn_d_ready = auto_mmio_in_d_ready_0; // @[NIC.scala:448:9]
wire mmionodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] mmionodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] mmionodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [11:0] mmionodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [63:0] mmionodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire auto_intsink_out_0_0; // @[NIC.scala:448:9]
wire auto_intsink_out_1_0; // @[NIC.scala:448:9]
wire [2:0] auto_dma_out_1_a_bits_opcode_0; // @[NIC.scala:448:9]
wire [3:0] auto_dma_out_1_a_bits_size_0; // @[NIC.scala:448:9]
wire [2:0] auto_dma_out_1_a_bits_source_0; // @[NIC.scala:448:9]
wire [31:0] auto_dma_out_1_a_bits_address_0; // @[NIC.scala:448:9]
wire [7:0] auto_dma_out_1_a_bits_mask_0; // @[NIC.scala:448:9]
wire [63:0] auto_dma_out_1_a_bits_data_0; // @[NIC.scala:448:9]
wire auto_dma_out_1_a_valid_0; // @[NIC.scala:448:9]
wire auto_dma_out_1_d_ready_0; // @[NIC.scala:448:9]
wire [3:0] auto_dma_out_0_a_bits_size_0; // @[NIC.scala:448:9]
wire [2:0] auto_dma_out_0_a_bits_source_0; // @[NIC.scala:448:9]
wire [31:0] auto_dma_out_0_a_bits_address_0; // @[NIC.scala:448:9]
wire [7:0] auto_dma_out_0_a_bits_mask_0; // @[NIC.scala:448:9]
wire auto_dma_out_0_a_valid_0; // @[NIC.scala:448:9]
wire auto_mmio_in_a_ready_0; // @[NIC.scala:448:9]
wire [2:0] auto_mmio_in_d_bits_opcode_0; // @[NIC.scala:448:9]
wire [1:0] auto_mmio_in_d_bits_size_0; // @[NIC.scala:448:9]
wire [11:0] auto_mmio_in_d_bits_source_0; // @[NIC.scala:448:9]
wire [63:0] auto_mmio_in_d_bits_data_0; // @[NIC.scala:448:9]
wire auto_mmio_in_d_valid_0; // @[NIC.scala:448:9]
wire [63:0] io_ext_out_bits_data_0; // @[NIC.scala:448:9]
wire [7:0] io_ext_out_bits_keep_0; // @[NIC.scala:448:9]
wire io_ext_out_bits_last_0; // @[NIC.scala:448:9]
wire io_ext_out_valid_0; // @[NIC.scala:448:9]
wire widget_anonIn_a_ready; // @[MixedNode.scala:551:17]
wire widget_anonIn_a_valid = widget_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9]
wire [3:0] widget_anonIn_a_bits_size = widget_auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9]
wire [2:0] widget_anonIn_a_bits_source = widget_auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9]
wire [31:0] widget_anonIn_a_bits_address = widget_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9]
wire [7:0] widget_anonIn_a_bits_mask = widget_auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9]
wire widget_anonIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] widget_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] widget_anonIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] widget_anonIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [2:0] widget_anonIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [3:0] widget_anonIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire widget_anonIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] widget_anonIn_d_bits_data; // @[MixedNode.scala:551:17]
wire widget_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire dmanodeIn_a_ready; // @[MixedNode.scala:551:17]
wire widget_anonOut_a_ready = widget_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9]
wire widget_anonOut_a_valid; // @[MixedNode.scala:542:17]
wire dmanodeIn_a_valid = widget_auto_anon_out_a_valid; // @[WidthWidget.scala:27:9]
wire [3:0] widget_anonOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [2:0] widget_anonOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [3:0] dmanodeIn_a_bits_size = widget_auto_anon_out_a_bits_size; // @[WidthWidget.scala:27:9]
wire [31:0] widget_anonOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [2:0] dmanodeIn_a_bits_source = widget_auto_anon_out_a_bits_source; // @[WidthWidget.scala:27:9]
wire [7:0] widget_anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [31:0] dmanodeIn_a_bits_address = widget_auto_anon_out_a_bits_address; // @[WidthWidget.scala:27:9]
wire [7:0] dmanodeIn_a_bits_mask = widget_auto_anon_out_a_bits_mask; // @[WidthWidget.scala:27:9]
wire dmanodeIn_d_valid; // @[MixedNode.scala:551:17]
wire widget_anonOut_d_valid = widget_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9]
wire [2:0] dmanodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [2:0] widget_anonOut_d_bits_opcode = widget_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] dmanodeIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [1:0] widget_anonOut_d_bits_param = widget_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] dmanodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [3:0] widget_anonOut_d_bits_size = widget_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9]
wire [2:0] dmanodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [2:0] widget_anonOut_d_bits_source = widget_auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9]
wire [3:0] dmanodeIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire [3:0] widget_anonOut_d_bits_sink = widget_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9]
wire dmanodeIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire widget_anonOut_d_bits_denied = widget_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [63:0] dmanodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire [63:0] widget_anonOut_d_bits_data = widget_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9]
wire dmanodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire widget_anonOut_d_bits_corrupt = widget_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_a_ready; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] widget_auto_anon_in_d_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] widget_auto_anon_in_d_bits_size; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_in_d_bits_source; // @[WidthWidget.scala:27:9]
wire [3:0] widget_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [63:0] widget_auto_anon_in_d_bits_data; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_d_valid; // @[WidthWidget.scala:27:9]
assign widget_anonIn_a_ready = widget_anonOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign widget_auto_anon_out_a_valid = widget_anonOut_a_valid; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_a_bits_size = widget_anonOut_a_bits_size; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_a_bits_source = widget_anonOut_a_bits_source; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_a_bits_address = widget_anonOut_a_bits_address; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_a_bits_mask = widget_anonOut_a_bits_mask; // @[WidthWidget.scala:27:9]
assign widget_anonIn_d_valid = widget_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_d_bits_opcode = widget_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_d_bits_param = widget_anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_d_bits_size = widget_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_d_bits_source = widget_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_d_bits_sink = widget_anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_d_bits_denied = widget_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_d_bits_data = widget_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_d_bits_corrupt = widget_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign widget_auto_anon_in_a_ready = widget_anonIn_a_ready; // @[WidthWidget.scala:27:9]
assign widget_anonOut_a_valid = widget_anonIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_a_bits_size = widget_anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_a_bits_source = widget_anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_a_bits_address = widget_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_a_bits_mask = widget_anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign widget_auto_anon_in_d_valid = widget_anonIn_d_valid; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_d_bits_opcode = widget_anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_d_bits_param = widget_anonIn_d_bits_param; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_d_bits_size = widget_anonIn_d_bits_size; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_d_bits_source = widget_anonIn_d_bits_source; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_d_bits_sink = widget_anonIn_d_bits_sink; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_d_bits_denied = widget_anonIn_d_bits_denied; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_d_bits_data = widget_anonIn_d_bits_data; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_d_bits_corrupt = widget_anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire widget_1_anonIn_a_ready; // @[MixedNode.scala:551:17]
wire widget_1_anonIn_a_valid = widget_1_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9]
wire [2:0] widget_1_anonIn_a_bits_opcode = widget_1_auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire [3:0] widget_1_anonIn_a_bits_size = widget_1_auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9]
wire [2:0] widget_1_anonIn_a_bits_source = widget_1_auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9]
wire [31:0] widget_1_anonIn_a_bits_address = widget_1_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9]
wire [7:0] widget_1_anonIn_a_bits_mask = widget_1_auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9]
wire [63:0] widget_1_anonIn_a_bits_data = widget_1_auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9]
wire widget_1_anonIn_d_ready = widget_1_auto_anon_in_d_ready; // @[WidthWidget.scala:27:9]
wire widget_1_anonIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] widget_1_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] widget_1_anonIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] widget_1_anonIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [2:0] widget_1_anonIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [3:0] widget_1_anonIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire widget_1_anonIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] widget_1_anonIn_d_bits_data; // @[MixedNode.scala:551:17]
wire widget_1_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire x1_dmanodeIn_a_ready; // @[MixedNode.scala:551:17]
wire widget_1_anonOut_a_ready = widget_1_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9]
wire widget_1_anonOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] widget_1_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire x1_dmanodeIn_a_valid = widget_1_auto_anon_out_a_valid; // @[WidthWidget.scala:27:9]
wire [2:0] x1_dmanodeIn_a_bits_opcode = widget_1_auto_anon_out_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire [3:0] widget_1_anonOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [2:0] widget_1_anonOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [3:0] x1_dmanodeIn_a_bits_size = widget_1_auto_anon_out_a_bits_size; // @[WidthWidget.scala:27:9]
wire [31:0] widget_1_anonOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [2:0] x1_dmanodeIn_a_bits_source = widget_1_auto_anon_out_a_bits_source; // @[WidthWidget.scala:27:9]
wire [7:0] widget_1_anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [31:0] x1_dmanodeIn_a_bits_address = widget_1_auto_anon_out_a_bits_address; // @[WidthWidget.scala:27:9]
wire [63:0] widget_1_anonOut_a_bits_data; // @[MixedNode.scala:542:17]
wire [7:0] x1_dmanodeIn_a_bits_mask = widget_1_auto_anon_out_a_bits_mask; // @[WidthWidget.scala:27:9]
wire [63:0] x1_dmanodeIn_a_bits_data = widget_1_auto_anon_out_a_bits_data; // @[WidthWidget.scala:27:9]
wire widget_1_anonOut_d_ready; // @[MixedNode.scala:542:17]
wire x1_dmanodeIn_d_ready = widget_1_auto_anon_out_d_ready; // @[WidthWidget.scala:27:9]
wire x1_dmanodeIn_d_valid; // @[MixedNode.scala:551:17]
wire widget_1_anonOut_d_valid = widget_1_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9]
wire [2:0] x1_dmanodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [2:0] widget_1_anonOut_d_bits_opcode = widget_1_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] x1_dmanodeIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [1:0] widget_1_anonOut_d_bits_param = widget_1_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] x1_dmanodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [3:0] widget_1_anonOut_d_bits_size = widget_1_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9]
wire [2:0] x1_dmanodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [2:0] widget_1_anonOut_d_bits_source = widget_1_auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9]
wire [3:0] x1_dmanodeIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire [3:0] widget_1_anonOut_d_bits_sink = widget_1_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9]
wire x1_dmanodeIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire widget_1_anonOut_d_bits_denied = widget_1_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [63:0] x1_dmanodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire [63:0] widget_1_anonOut_d_bits_data = widget_1_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9]
wire x1_dmanodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire widget_1_anonOut_d_bits_corrupt = widget_1_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire widget_1_auto_anon_in_a_ready; // @[WidthWidget.scala:27:9]
wire [2:0] widget_1_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] widget_1_auto_anon_in_d_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] widget_1_auto_anon_in_d_bits_size; // @[WidthWidget.scala:27:9]
wire [2:0] widget_1_auto_anon_in_d_bits_source; // @[WidthWidget.scala:27:9]
wire [3:0] widget_1_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:27:9]
wire widget_1_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [63:0] widget_1_auto_anon_in_d_bits_data; // @[WidthWidget.scala:27:9]
wire widget_1_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire widget_1_auto_anon_in_d_valid; // @[WidthWidget.scala:27:9]
assign widget_1_anonIn_a_ready = widget_1_anonOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign widget_1_auto_anon_out_a_valid = widget_1_anonOut_a_valid; // @[WidthWidget.scala:27:9]
assign widget_1_auto_anon_out_a_bits_opcode = widget_1_anonOut_a_bits_opcode; // @[WidthWidget.scala:27:9]
assign widget_1_auto_anon_out_a_bits_size = widget_1_anonOut_a_bits_size; // @[WidthWidget.scala:27:9]
assign widget_1_auto_anon_out_a_bits_source = widget_1_anonOut_a_bits_source; // @[WidthWidget.scala:27:9]
assign widget_1_auto_anon_out_a_bits_address = widget_1_anonOut_a_bits_address; // @[WidthWidget.scala:27:9]
assign widget_1_auto_anon_out_a_bits_mask = widget_1_anonOut_a_bits_mask; // @[WidthWidget.scala:27:9]
assign widget_1_auto_anon_out_a_bits_data = widget_1_anonOut_a_bits_data; // @[WidthWidget.scala:27:9]
assign widget_1_auto_anon_out_d_ready = widget_1_anonOut_d_ready; // @[WidthWidget.scala:27:9]
assign widget_1_anonIn_d_valid = widget_1_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign widget_1_anonIn_d_bits_opcode = widget_1_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign widget_1_anonIn_d_bits_param = widget_1_anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign widget_1_anonIn_d_bits_size = widget_1_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign widget_1_anonIn_d_bits_source = widget_1_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign widget_1_anonIn_d_bits_sink = widget_1_anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign widget_1_anonIn_d_bits_denied = widget_1_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign widget_1_anonIn_d_bits_data = widget_1_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign widget_1_anonIn_d_bits_corrupt = widget_1_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign widget_1_auto_anon_in_a_ready = widget_1_anonIn_a_ready; // @[WidthWidget.scala:27:9]
assign widget_1_anonOut_a_valid = widget_1_anonIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign widget_1_anonOut_a_bits_opcode = widget_1_anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign widget_1_anonOut_a_bits_size = widget_1_anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign widget_1_anonOut_a_bits_source = widget_1_anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign widget_1_anonOut_a_bits_address = widget_1_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign widget_1_anonOut_a_bits_mask = widget_1_anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign widget_1_anonOut_a_bits_data = widget_1_anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign widget_1_anonOut_d_ready = widget_1_anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign widget_1_auto_anon_in_d_valid = widget_1_anonIn_d_valid; // @[WidthWidget.scala:27:9]
assign widget_1_auto_anon_in_d_bits_opcode = widget_1_anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9]
assign widget_1_auto_anon_in_d_bits_param = widget_1_anonIn_d_bits_param; // @[WidthWidget.scala:27:9]
assign widget_1_auto_anon_in_d_bits_size = widget_1_anonIn_d_bits_size; // @[WidthWidget.scala:27:9]
assign widget_1_auto_anon_in_d_bits_source = widget_1_anonIn_d_bits_source; // @[WidthWidget.scala:27:9]
assign widget_1_auto_anon_in_d_bits_sink = widget_1_anonIn_d_bits_sink; // @[WidthWidget.scala:27:9]
assign widget_1_auto_anon_in_d_bits_denied = widget_1_anonIn_d_bits_denied; // @[WidthWidget.scala:27:9]
assign widget_1_auto_anon_in_d_bits_data = widget_1_anonIn_d_bits_data; // @[WidthWidget.scala:27:9]
assign widget_1_auto_anon_in_d_bits_corrupt = widget_1_anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9]
assign mmionodeIn_a_ready = mmionodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign mmionodeIn_d_valid = mmionodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign mmionodeIn_d_bits_opcode = mmionodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign mmionodeIn_d_bits_size = mmionodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign mmionodeIn_d_bits_source = mmionodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign mmionodeIn_d_bits_data = mmionodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] mmionodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] mmionodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [1:0] mmionodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [11:0] mmionodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [28:0] mmionodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] mmionodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] mmionodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire mmionodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire mmionodeOut_a_valid; // @[MixedNode.scala:542:17]
wire mmionodeOut_d_ready; // @[MixedNode.scala:542:17]
assign auto_mmio_in_a_ready_0 = mmionodeIn_a_ready; // @[NIC.scala:448:9]
assign mmionodeOut_a_valid = mmionodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign mmionodeOut_a_bits_opcode = mmionodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign mmionodeOut_a_bits_param = mmionodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign mmionodeOut_a_bits_size = mmionodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign mmionodeOut_a_bits_source = mmionodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign mmionodeOut_a_bits_address = mmionodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign mmionodeOut_a_bits_mask = mmionodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign mmionodeOut_a_bits_data = mmionodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign mmionodeOut_a_bits_corrupt = mmionodeIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign mmionodeOut_d_ready = mmionodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign auto_mmio_in_d_valid_0 = mmionodeIn_d_valid; // @[NIC.scala:448:9]
assign auto_mmio_in_d_bits_opcode_0 = mmionodeIn_d_bits_opcode; // @[NIC.scala:448:9]
assign auto_mmio_in_d_bits_size_0 = mmionodeIn_d_bits_size; // @[NIC.scala:448:9]
assign auto_mmio_in_d_bits_source_0 = mmionodeIn_d_bits_source; // @[NIC.scala:448:9]
assign auto_mmio_in_d_bits_data_0 = mmionodeIn_d_bits_data; // @[NIC.scala:448:9]
assign dmanodeIn_a_ready = dmanodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign auto_dma_out_0_a_valid_0 = dmanodeOut_a_valid; // @[NIC.scala:448:9]
assign auto_dma_out_0_a_bits_size_0 = dmanodeOut_a_bits_size; // @[NIC.scala:448:9]
assign auto_dma_out_0_a_bits_source_0 = dmanodeOut_a_bits_source; // @[NIC.scala:448:9]
assign auto_dma_out_0_a_bits_address_0 = dmanodeOut_a_bits_address; // @[NIC.scala:448:9]
assign auto_dma_out_0_a_bits_mask_0 = dmanodeOut_a_bits_mask; // @[NIC.scala:448:9]
assign dmanodeIn_d_valid = dmanodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign dmanodeIn_d_bits_opcode = dmanodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign dmanodeIn_d_bits_param = dmanodeOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign dmanodeIn_d_bits_size = dmanodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign dmanodeIn_d_bits_source = dmanodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign dmanodeIn_d_bits_sink = dmanodeOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign dmanodeIn_d_bits_denied = dmanodeOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign dmanodeIn_d_bits_data = dmanodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign dmanodeIn_d_bits_corrupt = dmanodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign x1_dmanodeIn_a_ready = x1_dmanodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign auto_dma_out_1_a_valid_0 = x1_dmanodeOut_a_valid; // @[NIC.scala:448:9]
assign auto_dma_out_1_a_bits_opcode_0 = x1_dmanodeOut_a_bits_opcode; // @[NIC.scala:448:9]
assign auto_dma_out_1_a_bits_size_0 = x1_dmanodeOut_a_bits_size; // @[NIC.scala:448:9]
assign auto_dma_out_1_a_bits_source_0 = x1_dmanodeOut_a_bits_source; // @[NIC.scala:448:9]
assign auto_dma_out_1_a_bits_address_0 = x1_dmanodeOut_a_bits_address; // @[NIC.scala:448:9]
assign auto_dma_out_1_a_bits_mask_0 = x1_dmanodeOut_a_bits_mask; // @[NIC.scala:448:9]
assign auto_dma_out_1_a_bits_data_0 = x1_dmanodeOut_a_bits_data; // @[NIC.scala:448:9]
assign auto_dma_out_1_d_ready_0 = x1_dmanodeOut_d_ready; // @[NIC.scala:448:9]
assign x1_dmanodeIn_d_valid = x1_dmanodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign x1_dmanodeIn_d_bits_opcode = x1_dmanodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign x1_dmanodeIn_d_bits_param = x1_dmanodeOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign x1_dmanodeIn_d_bits_size = x1_dmanodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign x1_dmanodeIn_d_bits_source = x1_dmanodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign x1_dmanodeIn_d_bits_sink = x1_dmanodeOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign x1_dmanodeIn_d_bits_denied = x1_dmanodeOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign x1_dmanodeIn_d_bits_data = x1_dmanodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign x1_dmanodeIn_d_bits_corrupt = x1_dmanodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign widget_auto_anon_out_a_ready = dmanodeIn_a_ready; // @[WidthWidget.scala:27:9]
assign dmanodeOut_a_valid = dmanodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign dmanodeOut_a_bits_size = dmanodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign dmanodeOut_a_bits_source = dmanodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign dmanodeOut_a_bits_address = dmanodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign dmanodeOut_a_bits_mask = dmanodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign widget_auto_anon_out_d_valid = dmanodeIn_d_valid; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_d_bits_opcode = dmanodeIn_d_bits_opcode; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_d_bits_param = dmanodeIn_d_bits_param; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_d_bits_size = dmanodeIn_d_bits_size; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_d_bits_source = dmanodeIn_d_bits_source; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_d_bits_sink = dmanodeIn_d_bits_sink; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_d_bits_denied = dmanodeIn_d_bits_denied; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_d_bits_data = dmanodeIn_d_bits_data; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_d_bits_corrupt = dmanodeIn_d_bits_corrupt; // @[WidthWidget.scala:27:9]
assign widget_1_auto_anon_out_a_ready = x1_dmanodeIn_a_ready; // @[WidthWidget.scala:27:9]
assign x1_dmanodeOut_a_valid = x1_dmanodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign x1_dmanodeOut_a_bits_opcode = x1_dmanodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign x1_dmanodeOut_a_bits_size = x1_dmanodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign x1_dmanodeOut_a_bits_source = x1_dmanodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign x1_dmanodeOut_a_bits_address = x1_dmanodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign x1_dmanodeOut_a_bits_mask = x1_dmanodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign x1_dmanodeOut_a_bits_data = x1_dmanodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign x1_dmanodeOut_d_ready = x1_dmanodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign widget_1_auto_anon_out_d_valid = x1_dmanodeIn_d_valid; // @[WidthWidget.scala:27:9]
assign widget_1_auto_anon_out_d_bits_opcode = x1_dmanodeIn_d_bits_opcode; // @[WidthWidget.scala:27:9]
assign widget_1_auto_anon_out_d_bits_param = x1_dmanodeIn_d_bits_param; // @[WidthWidget.scala:27:9]
assign widget_1_auto_anon_out_d_bits_size = x1_dmanodeIn_d_bits_size; // @[WidthWidget.scala:27:9]
assign widget_1_auto_anon_out_d_bits_source = x1_dmanodeIn_d_bits_source; // @[WidthWidget.scala:27:9]
assign widget_1_auto_anon_out_d_bits_sink = x1_dmanodeIn_d_bits_sink; // @[WidthWidget.scala:27:9]
assign widget_1_auto_anon_out_d_bits_denied = x1_dmanodeIn_d_bits_denied; // @[WidthWidget.scala:27:9]
assign widget_1_auto_anon_out_d_bits_data = x1_dmanodeIn_d_bits_data; // @[WidthWidget.scala:27:9]
assign widget_1_auto_anon_out_d_bits_corrupt = x1_dmanodeIn_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire intXingIn_sync_0; // @[MixedNode.scala:551:17]
wire intXingIn_sync_1; // @[MixedNode.scala:551:17]
wire intXingOut_sync_0; // @[MixedNode.scala:542:17]
wire intXingOut_sync_1; // @[MixedNode.scala:542:17]
assign intXingOut_sync_0 = intXingIn_sync_0; // @[MixedNode.scala:542:17, :551:17]
assign intXingOut_sync_1 = intXingIn_sync_1; // @[MixedNode.scala:542:17, :551:17]
wire controlXingIn_a_ready = controlXingOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
wire controlXingIn_a_valid; // @[MixedNode.scala:551:17]
wire [2:0] controlXingIn_a_bits_opcode; // @[MixedNode.scala:551:17]
wire [2:0] controlXingIn_a_bits_param; // @[MixedNode.scala:551:17]
wire [1:0] controlXingIn_a_bits_size; // @[MixedNode.scala:551:17]
wire [11:0] controlXingIn_a_bits_source; // @[MixedNode.scala:551:17]
wire [28:0] controlXingIn_a_bits_address; // @[MixedNode.scala:551:17]
wire [7:0] controlXingIn_a_bits_mask; // @[MixedNode.scala:551:17]
wire [63:0] controlXingIn_a_bits_data; // @[MixedNode.scala:551:17]
wire controlXingIn_a_bits_corrupt; // @[MixedNode.scala:551:17]
wire controlXingIn_d_ready; // @[MixedNode.scala:551:17]
wire controlXingIn_d_valid = controlXingOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] controlXingIn_d_bits_opcode = controlXingOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] controlXingIn_d_bits_size = controlXingOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [11:0] controlXingIn_d_bits_source = controlXingOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] controlXingIn_d_bits_data = controlXingOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] controlXingOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] controlXingOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [1:0] controlXingOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [11:0] controlXingOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [28:0] controlXingOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] controlXingOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] controlXingOut_a_bits_data; // @[MixedNode.scala:542:17]
wire controlXingOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire controlXingOut_a_valid; // @[MixedNode.scala:542:17]
wire controlXingOut_d_ready; // @[MixedNode.scala:542:17]
assign controlXingOut_a_valid = controlXingIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign controlXingOut_a_bits_opcode = controlXingIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign controlXingOut_a_bits_param = controlXingIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign controlXingOut_a_bits_size = controlXingIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign controlXingOut_a_bits_source = controlXingIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign controlXingOut_a_bits_address = controlXingIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign controlXingOut_a_bits_mask = controlXingIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign controlXingOut_a_bits_data = controlXingIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign controlXingOut_a_bits_corrupt = controlXingIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign controlXingOut_d_ready = controlXingIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
IceNicController control ( // @[NIC.scala:434:27]
.clock (clock),
.reset (reset),
.auto_control_xing_in_a_ready (controlXingOut_a_ready),
.auto_control_xing_in_a_valid (controlXingOut_a_valid), // @[MixedNode.scala:542:17]
.auto_control_xing_in_a_bits_opcode (controlXingOut_a_bits_opcode), // @[MixedNode.scala:542:17]
.auto_control_xing_in_a_bits_param (controlXingOut_a_bits_param), // @[MixedNode.scala:542:17]
.auto_control_xing_in_a_bits_size (controlXingOut_a_bits_size), // @[MixedNode.scala:542:17]
.auto_control_xing_in_a_bits_source (controlXingOut_a_bits_source), // @[MixedNode.scala:542:17]
.auto_control_xing_in_a_bits_address (controlXingOut_a_bits_address), // @[MixedNode.scala:542:17]
.auto_control_xing_in_a_bits_mask (controlXingOut_a_bits_mask), // @[MixedNode.scala:542:17]
.auto_control_xing_in_a_bits_data (controlXingOut_a_bits_data), // @[MixedNode.scala:542:17]
.auto_control_xing_in_a_bits_corrupt (controlXingOut_a_bits_corrupt), // @[MixedNode.scala:542:17]
.auto_control_xing_in_d_ready (controlXingOut_d_ready), // @[MixedNode.scala:542:17]
.auto_control_xing_in_d_valid (controlXingOut_d_valid),
.auto_control_xing_in_d_bits_opcode (controlXingOut_d_bits_opcode),
.auto_control_xing_in_d_bits_size (controlXingOut_d_bits_size),
.auto_control_xing_in_d_bits_source (controlXingOut_d_bits_source),
.auto_control_xing_in_d_bits_data (controlXingOut_d_bits_data),
.auto_int_xing_out_sync_0 (intXingIn_sync_0),
.auto_int_xing_out_sync_1 (intXingIn_sync_1),
.io_send_req_ready (_sendPath_io_send_req_ready), // @[NIC.scala:436:28]
.io_send_req_valid (_control_io_send_req_valid),
.io_send_req_bits (_control_io_send_req_bits),
.io_send_comp_ready (_control_io_send_comp_ready),
.io_send_comp_valid (_sendPath_io_send_comp_valid), // @[NIC.scala:436:28]
.io_recv_req_ready (_recvPath_io_recv_req_ready), // @[NIC.scala:437:28]
.io_recv_req_valid (_control_io_recv_req_valid),
.io_recv_req_bits (_control_io_recv_req_bits),
.io_recv_comp_ready (_control_io_recv_comp_ready),
.io_recv_comp_valid (_recvPath_io_recv_comp_valid), // @[NIC.scala:437:28]
.io_recv_comp_bits (_recvPath_io_recv_comp_bits), // @[NIC.scala:437:28]
.io_macAddr (io_ext_macAddr_0), // @[NIC.scala:448:9]
.io_txcsumReq_ready (_sendPath_io_csum_req_ready), // @[NIC.scala:436:28]
.io_txcsumReq_valid (_control_io_txcsumReq_valid),
.io_txcsumReq_bits_check (_control_io_txcsumReq_bits_check),
.io_txcsumReq_bits_offset (_control_io_txcsumReq_bits_offset),
.io_txcsumReq_bits_start (_control_io_txcsumReq_bits_start),
.io_txcsumReq_bits_init (_control_io_txcsumReq_bits_init),
.io_rxcsumRes_ready (_control_io_rxcsumRes_ready),
.io_rxcsumRes_valid (_recvPath_io_csum_res_valid), // @[NIC.scala:437:28]
.io_rxcsumRes_bits_correct (_recvPath_io_csum_res_bits_correct), // @[NIC.scala:437:28]
.io_rxcsumRes_bits_checked (_recvPath_io_csum_res_bits_checked), // @[NIC.scala:437:28]
.io_csumEnable (_control_io_csumEnable)
); // @[NIC.scala:434:27]
IceNicSendPath sendPath ( // @[NIC.scala:436:28]
.clock (clock),
.reset (reset),
.auto_reader_core_out_a_ready (widget_auto_anon_in_a_ready), // @[WidthWidget.scala:27:9]
.auto_reader_core_out_a_valid (widget_auto_anon_in_a_valid),
.auto_reader_core_out_a_bits_size (widget_auto_anon_in_a_bits_size),
.auto_reader_core_out_a_bits_source (widget_auto_anon_in_a_bits_source),
.auto_reader_core_out_a_bits_address (widget_auto_anon_in_a_bits_address),
.auto_reader_core_out_a_bits_mask (widget_auto_anon_in_a_bits_mask),
.auto_reader_core_out_d_valid (widget_auto_anon_in_d_valid), // @[WidthWidget.scala:27:9]
.auto_reader_core_out_d_bits_opcode (widget_auto_anon_in_d_bits_opcode), // @[WidthWidget.scala:27:9]
.auto_reader_core_out_d_bits_param (widget_auto_anon_in_d_bits_param), // @[WidthWidget.scala:27:9]
.auto_reader_core_out_d_bits_size (widget_auto_anon_in_d_bits_size), // @[WidthWidget.scala:27:9]
.auto_reader_core_out_d_bits_source (widget_auto_anon_in_d_bits_source), // @[WidthWidget.scala:27:9]
.auto_reader_core_out_d_bits_sink (widget_auto_anon_in_d_bits_sink), // @[WidthWidget.scala:27:9]
.auto_reader_core_out_d_bits_denied (widget_auto_anon_in_d_bits_denied), // @[WidthWidget.scala:27:9]
.auto_reader_core_out_d_bits_data (widget_auto_anon_in_d_bits_data), // @[WidthWidget.scala:27:9]
.auto_reader_core_out_d_bits_corrupt (widget_auto_anon_in_d_bits_corrupt), // @[WidthWidget.scala:27:9]
.io_send_req_ready (_sendPath_io_send_req_ready),
.io_send_req_valid (_control_io_send_req_valid), // @[NIC.scala:434:27]
.io_send_req_bits (_control_io_send_req_bits), // @[NIC.scala:434:27]
.io_send_comp_ready (_control_io_send_comp_ready), // @[NIC.scala:434:27]
.io_send_comp_valid (_sendPath_io_send_comp_valid),
.io_out_valid (io_ext_out_valid_0),
.io_out_bits_data (io_ext_out_bits_data_0),
.io_out_bits_keep (io_ext_out_bits_keep_0),
.io_out_bits_last (io_ext_out_bits_last_0),
.io_rlimit_inc (io_ext_rlimit_inc_0), // @[NIC.scala:448:9]
.io_rlimit_period (io_ext_rlimit_period_0), // @[NIC.scala:448:9]
.io_rlimit_size (io_ext_rlimit_size_0), // @[NIC.scala:448:9]
.io_csum_req_ready (_sendPath_io_csum_req_ready),
.io_csum_req_valid (_control_io_txcsumReq_valid), // @[NIC.scala:434:27]
.io_csum_req_bits_check (_control_io_txcsumReq_bits_check), // @[NIC.scala:434:27]
.io_csum_req_bits_offset (_control_io_txcsumReq_bits_offset), // @[NIC.scala:434:27]
.io_csum_req_bits_start (_control_io_txcsumReq_bits_start), // @[NIC.scala:434:27]
.io_csum_req_bits_init (_control_io_txcsumReq_bits_init), // @[NIC.scala:434:27]
.io_csum_enable (_control_io_csumEnable) // @[NIC.scala:434:27]
); // @[NIC.scala:436:28]
IceNicRecvPath recvPath ( // @[NIC.scala:437:28]
.clock (clock),
.reset (reset),
.auto_out_a_ready (widget_1_auto_anon_in_a_ready), // @[WidthWidget.scala:27:9]
.auto_out_a_valid (widget_1_auto_anon_in_a_valid),
.auto_out_a_bits_opcode (widget_1_auto_anon_in_a_bits_opcode),
.auto_out_a_bits_size (widget_1_auto_anon_in_a_bits_size),
.auto_out_a_bits_source (widget_1_auto_anon_in_a_bits_source),
.auto_out_a_bits_address (widget_1_auto_anon_in_a_bits_address),
.auto_out_a_bits_mask (widget_1_auto_anon_in_a_bits_mask),
.auto_out_a_bits_data (widget_1_auto_anon_in_a_bits_data),
.auto_out_d_ready (widget_1_auto_anon_in_d_ready),
.auto_out_d_valid (widget_1_auto_anon_in_d_valid), // @[WidthWidget.scala:27:9]
.auto_out_d_bits_opcode (widget_1_auto_anon_in_d_bits_opcode), // @[WidthWidget.scala:27:9]
.auto_out_d_bits_param (widget_1_auto_anon_in_d_bits_param), // @[WidthWidget.scala:27:9]
.auto_out_d_bits_size (widget_1_auto_anon_in_d_bits_size), // @[WidthWidget.scala:27:9]
.auto_out_d_bits_source (widget_1_auto_anon_in_d_bits_source), // @[WidthWidget.scala:27:9]
.auto_out_d_bits_sink (widget_1_auto_anon_in_d_bits_sink), // @[WidthWidget.scala:27:9]
.auto_out_d_bits_denied (widget_1_auto_anon_in_d_bits_denied), // @[WidthWidget.scala:27:9]
.auto_out_d_bits_data (widget_1_auto_anon_in_d_bits_data), // @[WidthWidget.scala:27:9]
.auto_out_d_bits_corrupt (widget_1_auto_anon_in_d_bits_corrupt), // @[WidthWidget.scala:27:9]
.io_recv_req_ready (_recvPath_io_recv_req_ready),
.io_recv_req_valid (_control_io_recv_req_valid), // @[NIC.scala:434:27]
.io_recv_req_bits (_control_io_recv_req_bits), // @[NIC.scala:434:27]
.io_recv_comp_ready (_control_io_recv_comp_ready), // @[NIC.scala:434:27]
.io_recv_comp_valid (_recvPath_io_recv_comp_valid),
.io_recv_comp_bits (_recvPath_io_recv_comp_bits),
.io_in_valid (io_ext_in_valid_0), // @[NIC.scala:448:9]
.io_in_bits_data (io_ext_in_bits_data_0), // @[NIC.scala:448:9]
.io_in_bits_keep (io_ext_in_bits_keep_0), // @[NIC.scala:448:9]
.io_in_bits_last (io_ext_in_bits_last_0), // @[NIC.scala:448:9]
.io_csum_res_ready (_control_io_rxcsumRes_ready), // @[NIC.scala:434:27]
.io_csum_res_valid (_recvPath_io_csum_res_valid),
.io_csum_res_bits_correct (_recvPath_io_csum_res_bits_correct),
.io_csum_res_bits_checked (_recvPath_io_csum_res_bits_checked),
.io_csum_enable (_control_io_csumEnable) // @[NIC.scala:434:27]
); // @[NIC.scala:437:28]
IntSyncSyncCrossingSink_n1x2_1 intsink ( // @[Crossing.scala:109:29]
.auto_in_sync_0 (intXingOut_sync_0), // @[MixedNode.scala:542:17]
.auto_in_sync_1 (intXingOut_sync_1), // @[MixedNode.scala:542:17]
.auto_out_0 (auto_intsink_out_0_0),
.auto_out_1 (auto_intsink_out_1_0)
); // @[Crossing.scala:109:29]
TLAtomicAutomata atomics ( // @[AtomicAutomata.scala:289:29]
.clock (clock),
.reset (reset),
.auto_in_a_ready (mmionodeOut_a_ready),
.auto_in_a_valid (mmionodeOut_a_valid), // @[MixedNode.scala:542:17]
.auto_in_a_bits_opcode (mmionodeOut_a_bits_opcode), // @[MixedNode.scala:542:17]
.auto_in_a_bits_param (mmionodeOut_a_bits_param), // @[MixedNode.scala:542:17]
.auto_in_a_bits_size (mmionodeOut_a_bits_size), // @[MixedNode.scala:542:17]
.auto_in_a_bits_source (mmionodeOut_a_bits_source), // @[MixedNode.scala:542:17]
.auto_in_a_bits_address (mmionodeOut_a_bits_address), // @[MixedNode.scala:542:17]
.auto_in_a_bits_mask (mmionodeOut_a_bits_mask), // @[MixedNode.scala:542:17]
.auto_in_a_bits_data (mmionodeOut_a_bits_data), // @[MixedNode.scala:542:17]
.auto_in_a_bits_corrupt (mmionodeOut_a_bits_corrupt), // @[MixedNode.scala:542:17]
.auto_in_d_ready (mmionodeOut_d_ready), // @[MixedNode.scala:542:17]
.auto_in_d_valid (mmionodeOut_d_valid),
.auto_in_d_bits_opcode (mmionodeOut_d_bits_opcode),
.auto_in_d_bits_size (mmionodeOut_d_bits_size),
.auto_in_d_bits_source (mmionodeOut_d_bits_source),
.auto_in_d_bits_data (mmionodeOut_d_bits_data),
.auto_out_a_ready (controlXingIn_a_ready), // @[MixedNode.scala:551:17]
.auto_out_a_valid (controlXingIn_a_valid),
.auto_out_a_bits_opcode (controlXingIn_a_bits_opcode),
.auto_out_a_bits_param (controlXingIn_a_bits_param),
.auto_out_a_bits_size (controlXingIn_a_bits_size),
.auto_out_a_bits_source (controlXingIn_a_bits_source),
.auto_out_a_bits_address (controlXingIn_a_bits_address),
.auto_out_a_bits_mask (controlXingIn_a_bits_mask),
.auto_out_a_bits_data (controlXingIn_a_bits_data),
.auto_out_a_bits_corrupt (controlXingIn_a_bits_corrupt),
.auto_out_d_ready (controlXingIn_d_ready),
.auto_out_d_valid (controlXingIn_d_valid), // @[MixedNode.scala:551:17]
.auto_out_d_bits_opcode (controlXingIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.auto_out_d_bits_size (controlXingIn_d_bits_size), // @[MixedNode.scala:551:17]
.auto_out_d_bits_source (controlXingIn_d_bits_source), // @[MixedNode.scala:551:17]
.auto_out_d_bits_data (controlXingIn_d_bits_data) // @[MixedNode.scala:551:17]
); // @[AtomicAutomata.scala:289:29]
assign auto_intsink_out_0 = auto_intsink_out_0_0; // @[NIC.scala:448:9]
assign auto_intsink_out_1 = auto_intsink_out_1_0; // @[NIC.scala:448:9]
assign auto_dma_out_1_a_valid = auto_dma_out_1_a_valid_0; // @[NIC.scala:448:9]
assign auto_dma_out_1_a_bits_opcode = auto_dma_out_1_a_bits_opcode_0; // @[NIC.scala:448:9]
assign auto_dma_out_1_a_bits_size = auto_dma_out_1_a_bits_size_0; // @[NIC.scala:448:9]
assign auto_dma_out_1_a_bits_source = auto_dma_out_1_a_bits_source_0; // @[NIC.scala:448:9]
assign auto_dma_out_1_a_bits_address = auto_dma_out_1_a_bits_address_0; // @[NIC.scala:448:9]
assign auto_dma_out_1_a_bits_mask = auto_dma_out_1_a_bits_mask_0; // @[NIC.scala:448:9]
assign auto_dma_out_1_a_bits_data = auto_dma_out_1_a_bits_data_0; // @[NIC.scala:448:9]
assign auto_dma_out_1_d_ready = auto_dma_out_1_d_ready_0; // @[NIC.scala:448:9]
assign auto_dma_out_0_a_valid = auto_dma_out_0_a_valid_0; // @[NIC.scala:448:9]
assign auto_dma_out_0_a_bits_size = auto_dma_out_0_a_bits_size_0; // @[NIC.scala:448:9]
assign auto_dma_out_0_a_bits_source = auto_dma_out_0_a_bits_source_0; // @[NIC.scala:448:9]
assign auto_dma_out_0_a_bits_address = auto_dma_out_0_a_bits_address_0; // @[NIC.scala:448:9]
assign auto_dma_out_0_a_bits_mask = auto_dma_out_0_a_bits_mask_0; // @[NIC.scala:448:9]
assign auto_mmio_in_a_ready = auto_mmio_in_a_ready_0; // @[NIC.scala:448:9]
assign auto_mmio_in_d_valid = auto_mmio_in_d_valid_0; // @[NIC.scala:448:9]
assign auto_mmio_in_d_bits_opcode = auto_mmio_in_d_bits_opcode_0; // @[NIC.scala:448:9]
assign auto_mmio_in_d_bits_size = auto_mmio_in_d_bits_size_0; // @[NIC.scala:448:9]
assign auto_mmio_in_d_bits_source = auto_mmio_in_d_bits_source_0; // @[NIC.scala:448:9]
assign auto_mmio_in_d_bits_data = auto_mmio_in_d_bits_data_0; // @[NIC.scala:448:9]
assign io_ext_out_valid = io_ext_out_valid_0; // @[NIC.scala:448:9]
assign io_ext_out_bits_data = io_ext_out_bits_data_0; // @[NIC.scala:448:9]
assign io_ext_out_bits_keep = io_ext_out_bits_keep_0; // @[NIC.scala:448:9]
assign io_ext_out_bits_last = io_ext_out_bits_last_0; // @[NIC.scala:448:9]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File util.scala:
//******************************************************************************
// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Utility Functions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v4.util
import chisel3._
import chisel3.util._
import freechips.rocketchip.rocket.Instructions._
import freechips.rocketchip.rocket._
import freechips.rocketchip.util.{Str}
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.tile.{TileKey}
import boom.v4.common.{MicroOp}
import boom.v4.exu.{BrUpdateInfo}
/**
* Object to XOR fold a input register of fullLength into a compressedLength.
*/
object Fold
{
def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = {
val clen = compressedLength
val hlen = fullLength
if (hlen <= clen) {
input
} else {
var res = 0.U(clen.W)
var remaining = input.asUInt
for (i <- 0 to hlen-1 by clen) {
val len = if (i + clen > hlen ) (hlen - i) else clen
require(len > 0)
res = res(clen-1,0) ^ remaining(len-1,0)
remaining = remaining >> len.U
}
res
}
}
}
/**
* Object to check if MicroOp was killed due to a branch mispredict.
* Uses "Fast" branch masks
*/
object IsKilledByBranch
{
def apply(brupdate: BrUpdateInfo, flush: Bool, uop: MicroOp): Bool = {
return apply(brupdate, flush, uop.br_mask)
}
def apply(brupdate: BrUpdateInfo, flush: Bool, uop_mask: UInt): Bool = {
return maskMatch(brupdate.b1.mispredict_mask, uop_mask) || flush
}
def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: T): Bool = {
return apply(brupdate, flush, bundle.uop)
}
def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Bool = {
return apply(brupdate, flush, bundle.bits)
}
}
/**
* Object to return new MicroOp with a new BR mask given a MicroOp mask
* and old BR mask.
*/
object GetNewUopAndBrMask
{
def apply(uop: MicroOp, brupdate: BrUpdateInfo)
(implicit p: Parameters): MicroOp = {
val newuop = WireInit(uop)
newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask
newuop
}
}
/**
* Object to return a BR mask given a MicroOp mask and old BR mask.
*/
object GetNewBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = {
return uop.br_mask & ~brupdate.b1.resolve_mask
}
def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = {
return br_mask & ~brupdate.b1.resolve_mask
}
}
object UpdateBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = {
val out = WireInit(uop)
out.br_mask := GetNewBrMask(brupdate, uop)
out
}
def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = {
val out = WireInit(bundle)
out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask)
out
}
def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Valid[T] = {
val out = WireInit(bundle)
out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask)
out.valid := bundle.valid && !IsKilledByBranch(brupdate, flush, bundle.bits.uop.br_mask)
out
}
}
/**
* Object to check if at least 1 bit matches in two masks
*/
object maskMatch
{
def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U
}
/**
* Object to clear one bit in a mask given an index
*/
object clearMaskBit
{
def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0)
}
/**
* Object to shift a register over by one bit and concat a new one
*/
object PerformShiftRegister
{
def apply(reg_val: UInt, new_bit: Bool): UInt = {
reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt
reg_val
}
}
/**
* Object to shift a register over by one bit, wrapping the top bit around to the bottom
* (XOR'ed with a new-bit), and evicting a bit at index HLEN.
* This is used to simulate a longer HLEN-width shift register that is folded
* down to a compressed CLEN.
*/
object PerformCircularShiftRegister
{
def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = {
val carry = csr(clen-1)
val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U)
newval
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapAdd
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, amt: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + amt)(log2Ceil(n)-1,0)
} else {
val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt)
Mux(sum >= n.U,
sum - n.U,
sum)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapSub
{
// "n" is the number of increments, so we wrap to n-1.
def apply(value: UInt, amt: Int, n: Int): UInt = {
if (isPow2(n)) {
(value - amt.U)(log2Ceil(n)-1,0)
} else {
val v = Cat(0.U(1.W), value)
val b = Cat(0.U(1.W), amt.U)
Mux(value >= amt.U,
value - amt.U,
n.U - amt.U + value)
}
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapInc
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === (n-1).U)
Mux(wrap, 0.U, value + 1.U)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapDec
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value - 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === 0.U)
Mux(wrap, (n-1).U, value - 1.U)
}
}
}
/**
* Object to mask off lower bits of a PC to align to a "b"
* Byte boundary.
*/
object AlignPCToBoundary
{
def apply(pc: UInt, b: Int): UInt = {
// Invert for scenario where pc longer than b
// (which would clear all bits above size(b)).
~(~pc | (b-1).U)
}
}
/**
* Object to rotate a signal left by one
*/
object RotateL1
{
def apply(signal: UInt): UInt = {
val w = signal.getWidth
val out = Cat(signal(w-2,0), signal(w-1))
return out
}
}
/**
* Object to sext a value to a particular length.
*/
object Sext
{
def apply(x: UInt, length: Int): UInt = {
if (x.getWidth == length) return x
else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x)
}
}
/**
* Object to translate from BOOM's special "packed immediate" to a 32b signed immediate
* Asking for U-type gives it shifted up 12 bits.
*/
object ImmGen
{
import boom.v4.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U, IS_N}
def apply(i: UInt, isel: UInt): UInt = {
val ip = Mux(isel === IS_N, 0.U(LONGEST_IMM_SZ.W), i)
val sign = ip(LONGEST_IMM_SZ-1).asSInt
val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign)
val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign)
val i11 = Mux(isel === IS_U, 0.S,
Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign))
val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt)
val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt)
val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S)
return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0)
}
}
/**
* Object to see if an instruction is a JALR.
*/
object DebugIsJALR
{
def apply(inst: UInt): Bool = {
// TODO Chisel not sure why this won't compile
// val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)),
// Array(
// JALR -> Bool(true)))
inst(6,0) === "b1100111".U
}
}
/**
* Object to take an instruction and output its branch or jal target. Only used
* for a debug assert (no where else would we jump straight from instruction
* bits to a target).
*/
object DebugGetBJImm
{
def apply(inst: UInt): UInt = {
// TODO Chisel not sure why this won't compile
//val csignals =
//rocket.DecodeLogic(inst,
// List(Bool(false), Bool(false)),
// Array(
// BEQ -> List(Bool(true ), Bool(false)),
// BNE -> List(Bool(true ), Bool(false)),
// BGE -> List(Bool(true ), Bool(false)),
// BGEU -> List(Bool(true ), Bool(false)),
// BLT -> List(Bool(true ), Bool(false)),
// BLTU -> List(Bool(true ), Bool(false))
// ))
//val is_br :: nothing :: Nil = csignals
val is_br = (inst(6,0) === "b1100011".U)
val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W))
val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W))
Mux(is_br, br_targ, jal_targ)
}
}
/**
* Object to return the lowest bit position after the head.
*/
object AgePriorityEncoder
{
def apply(in: Seq[Bool], head: UInt): UInt = {
val n = in.size
val width = log2Ceil(in.size)
val n_padded = 1 << width
val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in
val idx = PriorityEncoder(temp_vec)
idx(width-1, 0) //discard msb
}
}
/**
* Object to determine whether queue
* index i0 is older than index i1.
*/
object IsOlder
{
def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head))
}
object IsYoungerMask
{
def apply(i: UInt, head: UInt, n: Integer): UInt = {
val hi_mask = ~MaskLower(UIntToOH(i)(n-1,0))
val lo_mask = ~MaskUpper(UIntToOH(head)(n-1,0))
Mux(i < head, hi_mask & lo_mask, hi_mask | lo_mask)(n-1,0)
}
}
/**
* Set all bits at or below the highest order '1'.
*/
object MaskLower
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => in >> i.U).reduce(_|_)
}
}
/**
* Set all bits at or above the lowest order '1'.
*/
object MaskUpper
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_)
}
}
/**
* Transpose a matrix of Chisel Vecs.
*/
object Transpose
{
def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = {
val n = in(0).size
VecInit((0 until n).map(i => VecInit(in.map(row => row(i)))))
}
}
/**
* N-wide one-hot priority encoder.
*/
object SelectFirstN
{
def apply(in: UInt, n: Int) = {
val sels = Wire(Vec(n, UInt(in.getWidth.W)))
var mask = in
for (i <- 0 until n) {
sels(i) := PriorityEncoderOH(mask)
mask = mask & ~sels(i)
}
sels
}
}
/**
* Connect the first k of n valid input interfaces to k output interfaces.
*/
class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module
{
require(n >= k)
val io = IO(new Bundle {
val in = Vec(n, Flipped(DecoupledIO(gen)))
val out = Vec(k, DecoupledIO(gen))
})
if (n == k) {
io.out <> io.in
} else {
val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c))
val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col =>
(col zip io.in.map(_.valid)) map {case (c,v) => c && v})
val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_))
val out_valids = sels map (col => col.reduce(_||_))
val out_data = sels map (s => Mux1H(s, io.in.map(_.bits)))
in_readys zip io.in foreach {case (r,i) => i.ready := r}
out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d}
}
}
/**
* Create a queue that can be killed with a branch kill signal.
* Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq).
*/
class BranchKillableQueue[T <: boom.v4.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v4.common.MicroOp => Bool = u => true.B, fastDeq: Boolean = false)
(implicit p: org.chipsalliance.cde.config.Parameters)
extends boom.v4.common.BoomModule()(p)
with boom.v4.common.HasBoomCoreParameters
{
val io = IO(new Bundle {
val enq = Flipped(Decoupled(gen))
val deq = Decoupled(gen)
val brupdate = Input(new BrUpdateInfo())
val flush = Input(Bool())
val empty = Output(Bool())
val count = Output(UInt(log2Ceil(entries).W))
})
if (fastDeq && entries > 1) {
// Pipeline dequeue selection so the mux gets an entire cycle
val main = Module(new BranchKillableQueue(gen, entries-1, flush_fn, false))
val out_reg = Reg(gen)
val out_valid = RegInit(false.B)
val out_uop = Reg(new MicroOp)
main.io.enq <> io.enq
main.io.brupdate := io.brupdate
main.io.flush := io.flush
io.empty := main.io.empty && !out_valid
io.count := main.io.count + out_valid
io.deq.valid := out_valid
io.deq.bits := out_reg
io.deq.bits.uop := out_uop
out_uop := UpdateBrMask(io.brupdate, out_uop)
out_valid := out_valid && !IsKilledByBranch(io.brupdate, false.B, out_uop) && !(io.flush && flush_fn(out_uop))
main.io.deq.ready := false.B
when (io.deq.fire || !out_valid) {
out_valid := main.io.deq.valid && !IsKilledByBranch(io.brupdate, false.B, main.io.deq.bits.uop) && !(io.flush && flush_fn(main.io.deq.bits.uop))
out_reg := main.io.deq.bits
out_uop := UpdateBrMask(io.brupdate, main.io.deq.bits.uop)
main.io.deq.ready := true.B
}
} else {
val ram = Mem(entries, gen)
val valids = RegInit(VecInit(Seq.fill(entries) {false.B}))
val uops = Reg(Vec(entries, new MicroOp))
val enq_ptr = Counter(entries)
val deq_ptr = Counter(entries)
val maybe_full = RegInit(false.B)
val ptr_match = enq_ptr.value === deq_ptr.value
io.empty := ptr_match && !maybe_full
val full = ptr_match && maybe_full
val do_enq = WireInit(io.enq.fire && !IsKilledByBranch(io.brupdate, false.B, io.enq.bits.uop) && !(io.flush && flush_fn(io.enq.bits.uop)))
val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty)
for (i <- 0 until entries) {
val mask = uops(i).br_mask
val uop = uops(i)
valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, false.B, mask) && !(io.flush && flush_fn(uop))
when (valids(i)) {
uops(i).br_mask := GetNewBrMask(io.brupdate, mask)
}
}
when (do_enq) {
ram(enq_ptr.value) := io.enq.bits
valids(enq_ptr.value) := true.B
uops(enq_ptr.value) := io.enq.bits.uop
uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)
enq_ptr.inc()
}
when (do_deq) {
valids(deq_ptr.value) := false.B
deq_ptr.inc()
}
when (do_enq =/= do_deq) {
maybe_full := do_enq
}
io.enq.ready := !full
val out = Wire(gen)
out := ram(deq_ptr.value)
out.uop := uops(deq_ptr.value)
io.deq.valid := !io.empty && valids(deq_ptr.value)
io.deq.bits := out
val ptr_diff = enq_ptr.value - deq_ptr.value
if (isPow2(entries)) {
io.count := Cat(maybe_full && ptr_match, ptr_diff)
}
else {
io.count := Mux(ptr_match,
Mux(maybe_full,
entries.asUInt, 0.U),
Mux(deq_ptr.value > enq_ptr.value,
entries.asUInt + ptr_diff, ptr_diff))
}
}
}
// ------------------------------------------
// Printf helper functions
// ------------------------------------------
object BoolToChar
{
/**
* Take in a Chisel Bool and convert it into a Str
* based on the Chars given
*
* @param c_bool Chisel Bool
* @param trueChar Scala Char if bool is true
* @param falseChar Scala Char if bool is false
* @return UInt ASCII Char for "trueChar" or "falseChar"
*/
def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = {
Mux(c_bool, Str(trueChar), Str(falseChar))
}
}
object CfiTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param cfi_type specific cfi type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(cfi_type: UInt) = {
val strings = Seq("----", "BR ", "JAL ", "JALR")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(cfi_type)
}
}
object BpdTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param bpd_type specific bpd type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(bpd_type: UInt) = {
val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(bpd_type)
}
}
object RobTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param rob_type specific rob type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(rob_type: UInt) = {
val strings = Seq("RST", "NML", "RBK", " WT")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(rob_type)
}
}
object XRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param xreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(xreg: UInt) = {
val strings = Seq(" x0", " ra", " sp", " gp",
" tp", " t0", " t1", " t2",
" s0", " s1", " a0", " a1",
" a2", " a3", " a4", " a5",
" a6", " a7", " s2", " s3",
" s4", " s5", " s6", " s7",
" s8", " s9", "s10", "s11",
" t3", " t4", " t5", " t6")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(xreg)
}
}
object FPRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param fpreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(fpreg: UInt) = {
val strings = Seq(" ft0", " ft1", " ft2", " ft3",
" ft4", " ft5", " ft6", " ft7",
" fs0", " fs1", " fa0", " fa1",
" fa2", " fa3", " fa4", " fa5",
" fa6", " fa7", " fs2", " fs3",
" fs4", " fs5", " fs6", " fs7",
" fs8", " fs9", "fs10", "fs11",
" ft8", " ft9", "ft10", "ft11")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(fpreg)
}
}
object BoomCoreStringPrefix
{
/**
* Add prefix to BOOM strings (currently only adds the hartId)
*
* @param strs list of strings
* @return String combining the list with the prefix per line
*/
def apply(strs: String*)(implicit p: Parameters) = {
val prefix = "[C" + s"${p(TileKey).tileId}" + "] "
strs.map(str => prefix + str + "\n").mkString("")
}
}
class BranchKillablePipeline[T <: boom.v4.common.HasBoomUOP](gen: T, stages: Int)
(implicit p: org.chipsalliance.cde.config.Parameters)
extends boom.v4.common.BoomModule()(p)
with boom.v4.common.HasBoomCoreParameters
{
val io = IO(new Bundle {
val req = Input(Valid(gen))
val flush = Input(Bool())
val brupdate = Input(new BrUpdateInfo)
val resp = Output(Vec(stages, Valid(gen)))
})
require(stages > 0)
val uops = Reg(Vec(stages, Valid(gen)))
uops(0).valid := io.req.valid && !IsKilledByBranch(io.brupdate, io.flush, io.req.bits)
uops(0).bits := UpdateBrMask(io.brupdate, io.req.bits)
for (i <- 1 until stages) {
uops(i).valid := uops(i-1).valid && !IsKilledByBranch(io.brupdate, io.flush, uops(i-1).bits)
uops(i).bits := UpdateBrMask(io.brupdate, uops(i-1).bits)
}
for (i <- 0 until stages) { when (reset.asBool) { uops(i).valid := false.B } }
io.resp := uops
}
File tage.scala:
package boom.v4.ifu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import boom.v4.common._
import boom.v4.util.{BoomCoreStringPrefix, MaskLower, WrapInc}
import scala.math.min
class TageResp extends Bundle {
val ctr = UInt(3.W)
val u = UInt(2.W)
}
class TageTable(val nRows: Int, val tagSz: Int, val histLength: Int, val uBitPeriod: Int, val singlePorted: Boolean)
(implicit p: Parameters) extends BoomModule()(p)
with HasBoomFrontendParameters
{
require(histLength <= globalHistoryLength)
val nWrBypassEntries = 2
val io = IO( new Bundle {
val f1_req_valid = Input(Bool())
val f1_req_pc = Input(UInt(vaddrBitsExtended.W))
val f1_req_ghist = Input(UInt(globalHistoryLength.W))
val f2_resp = Output(Vec(bankWidth, Valid(new TageResp)))
val update_mask = Input(Vec(bankWidth, Bool()))
val update_taken = Input(Vec(bankWidth, Bool()))
val update_alloc = Input(Vec(bankWidth, Bool()))
val update_old_ctr = Input(Vec(bankWidth, UInt(3.W)))
val update_pc = Input(UInt())
val update_hist = Input(UInt())
val update_u_mask = Input(Vec(bankWidth, Bool()))
val update_u = Input(Vec(bankWidth, UInt(2.W)))
})
def compute_folded_hist(hist: UInt, l: Int) = {
val nChunks = (histLength + l - 1) / l
val hist_chunks = (0 until nChunks) map {i =>
hist(min((i+1)*l, histLength)-1, i*l)
}
hist_chunks.reduce(_^_)
}
def compute_tag_and_hash(unhashed_idx: UInt, hist: UInt) = {
val idx_history = compute_folded_hist(hist, log2Ceil(nRows))
val idx = (unhashed_idx ^ idx_history)(log2Ceil(nRows)-1,0)
val tag_history = compute_folded_hist(hist, tagSz)
val tag = ((unhashed_idx >> log2Ceil(nRows)) ^ tag_history)(tagSz-1,0)
(idx, tag)
}
def inc_ctr(ctr: UInt, taken: Bool): UInt = {
Mux(!taken, Mux(ctr === 0.U, 0.U, ctr - 1.U),
Mux(ctr === 7.U, 7.U, ctr + 1.U))
}
val doing_reset = RegInit(true.B)
val reset_idx = RegInit(0.U(log2Ceil(nRows).W))
reset_idx := reset_idx + doing_reset
when (reset_idx === (nRows-1).U) { doing_reset := false.B }
class TageEntry extends Bundle {
val valid = Bool() // TODO: Remove this valid bit
val tag = UInt(tagSz.W)
val ctr = UInt(3.W)
}
val tageEntrySz = 1 + tagSz + 3
val (s1_hashed_idx, s1_tag) = compute_tag_and_hash(fetchIdx(io.f1_req_pc), io.f1_req_ghist)
val us = SyncReadMem(nRows, Vec(bankWidth*2, Bool()))
val table = SyncReadMem(nRows, Vec(bankWidth, UInt(tageEntrySz.W)))
us.suggestName(s"tage_u_${histLength}")
table.suggestName(s"tage_table_${histLength}")
val mems = Seq((f"tage_l$histLength", nRows, bankWidth * tageEntrySz))
val s2_tag = RegNext(s1_tag)
val s2_req_rtage = Wire(Vec(bankWidth, new TageEntry))
val s2_req_rus = Wire(Vec(bankWidth*2, Bool()))
val s2_req_rhits = VecInit(s2_req_rtage.map(e => e.valid && e.tag === s2_tag && !doing_reset))
for (w <- 0 until bankWidth) {
// This bit indicates the TAGE table matched here
io.f2_resp(w).valid := s2_req_rhits(w)
io.f2_resp(w).bits.u := Cat(s2_req_rus(w*2+1), s2_req_rus(w*2))
io.f2_resp(w).bits.ctr := s2_req_rtage(w).ctr
}
val clear_u_ctr = RegInit(0.U((log2Ceil(uBitPeriod) + log2Ceil(nRows) + 1).W))
when (doing_reset) { clear_u_ctr := 1.U } .otherwise { clear_u_ctr := clear_u_ctr + 1.U }
val doing_clear_u = clear_u_ctr(log2Ceil(uBitPeriod)-1,0) === 0.U
val clear_u_hi = clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 1.U
val clear_u_lo = clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 0.U
val clear_u_idx = clear_u_ctr >> log2Ceil(uBitPeriod)
val clear_u_mask = VecInit((0 until bankWidth*2) map { i => if (i % 2 == 0) clear_u_lo else clear_u_hi }).asUInt
val (update_idx, update_tag) = compute_tag_and_hash(fetchIdx(io.update_pc), io.update_hist)
val update_wdata = Wire(Vec(bankWidth, new TageEntry))
val wen = WireInit(doing_reset || io.update_mask.reduce(_||_))
val rdata = if (singlePorted) table.read(s1_hashed_idx, !wen && io.f1_req_valid) else table.read(s1_hashed_idx, io.f1_req_valid)
when (RegNext(wen) && singlePorted.B) {
s2_req_rtage := 0.U.asTypeOf(Vec(bankWidth, new TageEntry))
} .otherwise {
s2_req_rtage := VecInit(rdata.map(_.asTypeOf(new TageEntry)))
}
when (wen) {
val widx = Mux(doing_reset, reset_idx, update_idx)
val wdata = Mux(doing_reset, VecInit(Seq.fill(bankWidth) { 0.U(tageEntrySz.W) }), VecInit(update_wdata.map(_.asUInt)))
val wmask = Mux(doing_reset, ~(0.U(bankWidth.W)), io.update_mask.asUInt)
table.write(widx, wdata, wmask.asBools)
}
val update_u_mask = VecInit((0 until bankWidth*2) map {i => io.update_u_mask(i / 2)})
val update_u_wen = WireInit(doing_reset || doing_clear_u || update_u_mask.reduce(_||_))
val u_rdata = if (singlePorted) {
us.read(s1_hashed_idx, !update_u_wen && io.f1_req_valid)
} else {
us.read(s1_hashed_idx, io.f1_req_valid)
}
s2_req_rus := u_rdata
when (update_u_wen) {
val widx = Mux(doing_reset, reset_idx, Mux(doing_clear_u, clear_u_idx, update_idx))
val wdata = Mux(doing_reset || doing_clear_u, VecInit(0.U((bankWidth*2).W).asBools), VecInit(io.update_u.asUInt.asBools))
val wmask = Mux(doing_reset, ~(0.U((bankWidth*2).W)), Mux(doing_clear_u, clear_u_mask, update_u_mask.asUInt))
us.write(widx, wdata, wmask.asBools)
}
val wrbypass_tags = Reg(Vec(nWrBypassEntries, UInt(tagSz.W)))
val wrbypass_idxs = Reg(Vec(nWrBypassEntries, UInt(log2Ceil(nRows).W)))
val wrbypass = Reg(Vec(nWrBypassEntries, Vec(bankWidth, UInt(3.W))))
val wrbypass_enq_idx = RegInit(0.U(log2Ceil(nWrBypassEntries).W))
val wrbypass_hits = VecInit((0 until nWrBypassEntries) map { i =>
!doing_reset &&
wrbypass_tags(i) === update_tag &&
wrbypass_idxs(i) === update_idx
})
val wrbypass_hit = wrbypass_hits.reduce(_||_)
val wrbypass_hit_idx = PriorityEncoder(wrbypass_hits)
for (w <- 0 until bankWidth) {
update_wdata(w).ctr := Mux(io.update_alloc(w),
Mux(io.update_taken(w), 4.U,
3.U
),
Mux(wrbypass_hit, inc_ctr(wrbypass(wrbypass_hit_idx)(w), io.update_taken(w)),
inc_ctr(io.update_old_ctr(w), io.update_taken(w))
)
)
update_wdata(w).valid := true.B
update_wdata(w).tag := update_tag
}
when (io.update_mask.reduce(_||_)) {
when (wrbypass_hits.reduce(_||_)) {
wrbypass(wrbypass_hit_idx) := VecInit(update_wdata.map(_.ctr))
} .otherwise {
wrbypass (wrbypass_enq_idx) := VecInit(update_wdata.map(_.ctr))
wrbypass_tags(wrbypass_enq_idx) := update_tag
wrbypass_idxs(wrbypass_enq_idx) := update_idx
wrbypass_enq_idx := WrapInc(wrbypass_enq_idx, nWrBypassEntries)
}
}
}
case class BoomTageParams(
// nSets, histLen, tagSz
tableInfo: Seq[Tuple3[Int, Int, Int]] = Seq(( 128, 2, 7),
( 128, 4, 7),
( 256, 8, 8),
( 256, 16, 8),
( 128, 32, 9),
( 128, 64, 9)),
uBitPeriod: Int = 2048,
singlePorted: Boolean = false
)
class TageBranchPredictorBank(params: BoomTageParams = BoomTageParams())(implicit p: Parameters) extends BranchPredictorBank()(p)
{
val tageUBitPeriod = params.uBitPeriod
val tageNTables = params.tableInfo.size
class TageMeta extends Bundle
{
val provider = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))
val alt_differs = Vec(bankWidth, Output(Bool()))
val provider_u = Vec(bankWidth, Output(UInt(2.W)))
val provider_ctr = Vec(bankWidth, Output(UInt(3.W)))
val allocate = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))
}
val f3_meta = Wire(new TageMeta)
override val metaSz = f3_meta.asUInt.getWidth
require(metaSz <= bpdMaxMetaLength)
def inc_u(u: UInt, alt_differs: Bool, mispredict: Bool): UInt = {
Mux(!alt_differs, u,
Mux(mispredict, Mux(u === 0.U, 0.U, u - 1.U),
Mux(u === 3.U, 3.U, u + 1.U)))
}
val tt = params.tableInfo map {
case (n, l, s) => {
val t = Module(new TageTable(n, s, l, params.uBitPeriod, params.singlePorted))
t.io.f1_req_valid := RegNext(io.f0_valid)
t.io.f1_req_pc := RegNext(bankAlign(io.f0_pc))
t.io.f1_req_ghist := io.f1_ghist
(t, t.mems)
}
}
val tables = tt.map(_._1)
val mems = tt.map(_._2).flatten
val f2_resps = VecInit(tables.map(_.io.f2_resp))
val f3_resps = RegNext(f2_resps)
val s1_update_meta = s1_update.bits.meta.asTypeOf(new TageMeta)
val s1_update_mispredict_mask = UIntToOH(s1_update.bits.cfi_idx.bits) &
Fill(bankWidth, s1_update.bits.cfi_mispredicted)
val s1_update_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, Bool()))))
val s1_update_u_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, UInt(1.W)))))
val s1_update_taken = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))
val s1_update_old_ctr = Wire(Vec(tageNTables, Vec(bankWidth, UInt(3.W))))
val s1_update_alloc = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))
val s1_update_u = Wire(Vec(tageNTables, Vec(bankWidth, UInt(2.W))))
s1_update_taken := DontCare
s1_update_old_ctr := DontCare
s1_update_alloc := DontCare
s1_update_u := DontCare
for (w <- 0 until bankWidth) {
var s2_provided = false.B
var s2_provider = 0.U
var s2_alt_provided = false.B
var s2_alt_provider = 0.U
for (i <- 0 until tageNTables) {
val hit = f2_resps(i)(w).valid
s2_alt_provided = s2_alt_provided || (s2_provided && hit)
s2_provided = s2_provided || hit
s2_alt_provider = Mux(hit, s2_provider, s2_alt_provider)
s2_provider = Mux(hit, i.U, s2_provider)
}
val s3_provided = RegNext(s2_provided)
val s3_provider = RegNext(s2_provider)
val s3_alt_provided = RegNext(s2_alt_provided)
val s3_alt_provider = RegNext(s2_alt_provider)
val prov = RegNext(f2_resps(s2_provider)(w).bits)
val alt = RegNext(f2_resps(s2_alt_provider)(w).bits)
io.resp.f3(w).taken := Mux(s3_provided,
Mux(prov.ctr === 3.U || prov.ctr === 4.U,
Mux(s3_alt_provided, alt.ctr(2), io.resp_in(0).f3(w).taken),
prov.ctr(2)),
io.resp_in(0).f3(w).taken
)
f3_meta.provider(w).valid := s3_provided
f3_meta.provider(w).bits := s3_provider
f3_meta.alt_differs(w) := s3_alt_provided && alt.ctr(2) =/= io.resp.f3(w).taken
f3_meta.provider_u(w) := prov.u
f3_meta.provider_ctr(w) := prov.ctr
// Create a mask of tables which did not hit our query, and also contain useless entries
// and also uses a longer history than the provider
val allocatable_slots = (
VecInit(f3_resps.map(r => !r(w).valid && r(w).bits.u === 0.U)).asUInt &
~(MaskLower(UIntToOH(f3_meta.provider(w).bits)) & Fill(tageNTables, f3_meta.provider(w).valid))
)
val alloc_lfsr = random.LFSR(tageNTables max 2)
val first_entry = PriorityEncoder(allocatable_slots)
val masked_entry = PriorityEncoder(allocatable_slots & alloc_lfsr)
val alloc_entry = Mux(allocatable_slots(masked_entry),
masked_entry,
first_entry)
f3_meta.allocate(w).valid := allocatable_slots =/= 0.U
f3_meta.allocate(w).bits := alloc_entry
val update_was_taken = (s1_update.bits.cfi_idx.valid &&
(s1_update.bits.cfi_idx.bits === w.U) &&
s1_update.bits.cfi_taken)
when (s1_update.bits.br_mask(w) && s1_update.valid && s1_update.bits.is_commit_update) {
when (s1_update_meta.provider(w).valid) {
val provider = s1_update_meta.provider(w).bits
s1_update_mask(provider)(w) := true.B
s1_update_u_mask(provider)(w) := true.B
val new_u = inc_u(s1_update_meta.provider_u(w),
s1_update_meta.alt_differs(w),
s1_update_mispredict_mask(w))
s1_update_u (provider)(w) := new_u
s1_update_taken (provider)(w) := update_was_taken
s1_update_old_ctr(provider)(w) := s1_update_meta.provider_ctr(w)
s1_update_alloc (provider)(w) := false.B
}
}
}
when (s1_update.valid && s1_update.bits.is_commit_update && s1_update.bits.cfi_mispredicted && s1_update.bits.cfi_idx.valid) {
val idx = s1_update.bits.cfi_idx.bits
val allocate = s1_update_meta.allocate(idx)
when (allocate.valid) {
s1_update_mask (allocate.bits)(idx) := true.B
s1_update_taken(allocate.bits)(idx) := s1_update.bits.cfi_taken
s1_update_alloc(allocate.bits)(idx) := true.B
s1_update_u_mask(allocate.bits)(idx) := true.B
s1_update_u (allocate.bits)(idx) := 0.U
} .otherwise {
val provider = s1_update_meta.provider(idx)
val decr_mask = Mux(provider.valid, ~MaskLower(UIntToOH(provider.bits)), 0.U)
for (i <- 0 until tageNTables) {
when (decr_mask(i)) {
s1_update_u_mask(i)(idx) := true.B
s1_update_u (i)(idx) := 0.U
}
}
}
}
for (i <- 0 until tageNTables) {
for (w <- 0 until bankWidth) {
tables(i).io.update_mask(w) := RegNext(s1_update_mask(i)(w))
tables(i).io.update_taken(w) := RegNext(s1_update_taken(i)(w))
tables(i).io.update_alloc(w) := RegNext(s1_update_alloc(i)(w))
tables(i).io.update_old_ctr(w) := RegNext(s1_update_old_ctr(i)(w))
tables(i).io.update_u_mask(w) := RegNext(s1_update_u_mask(i)(w))
tables(i).io.update_u(w) := RegNext(s1_update_u(i)(w))
}
tables(i).io.update_pc := RegNext(s1_update.bits.pc)
tables(i).io.update_hist := RegNext(s1_update.bits.ghist)
}
//io.f3_meta := Cat(f3_meta.asUInt, micro.io.f3_meta(micro.metaSz-1,0), base.io.f3_meta(base.metaSz-1, 0))
io.f3_meta := f3_meta.asUInt
}
| module TageTable( // @[tage.scala:24:7]
input clock, // @[tage.scala:24:7]
input reset, // @[tage.scala:24:7]
input io_f1_req_valid, // @[tage.scala:31:14]
input [39:0] io_f1_req_pc, // @[tage.scala:31:14]
input [63:0] io_f1_req_ghist, // @[tage.scala:31:14]
output io_f2_resp_0_valid, // @[tage.scala:31:14]
output [2:0] io_f2_resp_0_bits_ctr, // @[tage.scala:31:14]
output [1:0] io_f2_resp_0_bits_u, // @[tage.scala:31:14]
output io_f2_resp_1_valid, // @[tage.scala:31:14]
output [2:0] io_f2_resp_1_bits_ctr, // @[tage.scala:31:14]
output [1:0] io_f2_resp_1_bits_u, // @[tage.scala:31:14]
output io_f2_resp_2_valid, // @[tage.scala:31:14]
output [2:0] io_f2_resp_2_bits_ctr, // @[tage.scala:31:14]
output [1:0] io_f2_resp_2_bits_u, // @[tage.scala:31:14]
output io_f2_resp_3_valid, // @[tage.scala:31:14]
output [2:0] io_f2_resp_3_bits_ctr, // @[tage.scala:31:14]
output [1:0] io_f2_resp_3_bits_u, // @[tage.scala:31:14]
input io_update_mask_0, // @[tage.scala:31:14]
input io_update_mask_1, // @[tage.scala:31:14]
input io_update_mask_2, // @[tage.scala:31:14]
input io_update_mask_3, // @[tage.scala:31:14]
input io_update_taken_0, // @[tage.scala:31:14]
input io_update_taken_1, // @[tage.scala:31:14]
input io_update_taken_2, // @[tage.scala:31:14]
input io_update_taken_3, // @[tage.scala:31:14]
input io_update_alloc_0, // @[tage.scala:31:14]
input io_update_alloc_1, // @[tage.scala:31:14]
input io_update_alloc_2, // @[tage.scala:31:14]
input io_update_alloc_3, // @[tage.scala:31:14]
input [2:0] io_update_old_ctr_0, // @[tage.scala:31:14]
input [2:0] io_update_old_ctr_1, // @[tage.scala:31:14]
input [2:0] io_update_old_ctr_2, // @[tage.scala:31:14]
input [2:0] io_update_old_ctr_3, // @[tage.scala:31:14]
input [39:0] io_update_pc, // @[tage.scala:31:14]
input [63:0] io_update_hist, // @[tage.scala:31:14]
input io_update_u_mask_0, // @[tage.scala:31:14]
input io_update_u_mask_1, // @[tage.scala:31:14]
input io_update_u_mask_2, // @[tage.scala:31:14]
input io_update_u_mask_3, // @[tage.scala:31:14]
input [1:0] io_update_u_0, // @[tage.scala:31:14]
input [1:0] io_update_u_1, // @[tage.scala:31:14]
input [1:0] io_update_u_2, // @[tage.scala:31:14]
input [1:0] io_update_u_3 // @[tage.scala:31:14]
);
wire [43:0] _tage_table_2_R0_data; // @[tage.scala:90:27]
wire [7:0] _tage_u_2_R0_data; // @[tage.scala:89:27]
wire io_f1_req_valid_0 = io_f1_req_valid; // @[tage.scala:24:7]
wire [39:0] io_f1_req_pc_0 = io_f1_req_pc; // @[tage.scala:24:7]
wire [63:0] io_f1_req_ghist_0 = io_f1_req_ghist; // @[tage.scala:24:7]
wire io_update_mask_0_0 = io_update_mask_0; // @[tage.scala:24:7]
wire io_update_mask_1_0 = io_update_mask_1; // @[tage.scala:24:7]
wire io_update_mask_2_0 = io_update_mask_2; // @[tage.scala:24:7]
wire io_update_mask_3_0 = io_update_mask_3; // @[tage.scala:24:7]
wire io_update_taken_0_0 = io_update_taken_0; // @[tage.scala:24:7]
wire io_update_taken_1_0 = io_update_taken_1; // @[tage.scala:24:7]
wire io_update_taken_2_0 = io_update_taken_2; // @[tage.scala:24:7]
wire io_update_taken_3_0 = io_update_taken_3; // @[tage.scala:24:7]
wire io_update_alloc_0_0 = io_update_alloc_0; // @[tage.scala:24:7]
wire io_update_alloc_1_0 = io_update_alloc_1; // @[tage.scala:24:7]
wire io_update_alloc_2_0 = io_update_alloc_2; // @[tage.scala:24:7]
wire io_update_alloc_3_0 = io_update_alloc_3; // @[tage.scala:24:7]
wire [2:0] io_update_old_ctr_0_0 = io_update_old_ctr_0; // @[tage.scala:24:7]
wire [2:0] io_update_old_ctr_1_0 = io_update_old_ctr_1; // @[tage.scala:24:7]
wire [2:0] io_update_old_ctr_2_0 = io_update_old_ctr_2; // @[tage.scala:24:7]
wire [2:0] io_update_old_ctr_3_0 = io_update_old_ctr_3; // @[tage.scala:24:7]
wire [39:0] io_update_pc_0 = io_update_pc; // @[tage.scala:24:7]
wire [63:0] io_update_hist_0 = io_update_hist; // @[tage.scala:24:7]
wire io_update_u_mask_0_0 = io_update_u_mask_0; // @[tage.scala:24:7]
wire io_update_u_mask_1_0 = io_update_u_mask_1; // @[tage.scala:24:7]
wire io_update_u_mask_2_0 = io_update_u_mask_2; // @[tage.scala:24:7]
wire io_update_u_mask_3_0 = io_update_u_mask_3; // @[tage.scala:24:7]
wire [1:0] io_update_u_0_0 = io_update_u_0; // @[tage.scala:24:7]
wire [1:0] io_update_u_1_0 = io_update_u_1; // @[tage.scala:24:7]
wire [1:0] io_update_u_2_0 = io_update_u_2; // @[tage.scala:24:7]
wire [1:0] io_update_u_3_0 = io_update_u_3; // @[tage.scala:24:7]
wire update_wdata_0_valid = 1'h1; // @[tage.scala:120:26]
wire update_wdata_1_valid = 1'h1; // @[tage.scala:120:26]
wire update_wdata_2_valid = 1'h1; // @[tage.scala:120:26]
wire update_wdata_3_valid = 1'h1; // @[tage.scala:120:26]
wire [10:0] _wdata_WIRE_0 = 11'h0; // @[tage.scala:130:41]
wire [10:0] _wdata_WIRE_1 = 11'h0; // @[tage.scala:130:41]
wire [10:0] _wdata_WIRE_2 = 11'h0; // @[tage.scala:130:41]
wire [10:0] _wdata_WIRE_3 = 11'h0; // @[tage.scala:130:41]
wire [3:0] _wmask_T = 4'hF; // @[tage.scala:131:34]
wire _wdata_WIRE_2_0 = 1'h0; // @[tage.scala:145:58]
wire _wdata_WIRE_2_1 = 1'h0; // @[tage.scala:145:58]
wire _wdata_WIRE_2_2 = 1'h0; // @[tage.scala:145:58]
wire _wdata_WIRE_2_3 = 1'h0; // @[tage.scala:145:58]
wire _wdata_WIRE_2_4 = 1'h0; // @[tage.scala:145:58]
wire _wdata_WIRE_2_5 = 1'h0; // @[tage.scala:145:58]
wire _wdata_WIRE_2_6 = 1'h0; // @[tage.scala:145:58]
wire _wdata_WIRE_2_7 = 1'h0; // @[tage.scala:145:58]
wire [7:0] _wmask_T_2 = 8'hFF; // @[tage.scala:146:34]
wire s2_req_rhits_0; // @[tage.scala:100:29]
wire [2:0] s2_req_rtage_0_ctr; // @[tage.scala:98:26]
wire [1:0] _io_f2_resp_0_bits_u_T; // @[tage.scala:105:34]
wire s2_req_rhits_1; // @[tage.scala:100:29]
wire [2:0] s2_req_rtage_1_ctr; // @[tage.scala:98:26]
wire [1:0] _io_f2_resp_1_bits_u_T; // @[tage.scala:105:34]
wire s2_req_rhits_2; // @[tage.scala:100:29]
wire [2:0] s2_req_rtage_2_ctr; // @[tage.scala:98:26]
wire [1:0] _io_f2_resp_2_bits_u_T; // @[tage.scala:105:34]
wire s2_req_rhits_3; // @[tage.scala:100:29]
wire [2:0] s2_req_rtage_3_ctr; // @[tage.scala:98:26]
wire [1:0] _io_f2_resp_3_bits_u_T; // @[tage.scala:105:34]
wire update_u_mask_0 = io_update_u_mask_0_0; // @[tage.scala:24:7, :135:30]
wire update_u_mask_1 = io_update_u_mask_0_0; // @[tage.scala:24:7, :135:30]
wire update_u_mask_2 = io_update_u_mask_1_0; // @[tage.scala:24:7, :135:30]
wire update_u_mask_3 = io_update_u_mask_1_0; // @[tage.scala:24:7, :135:30]
wire update_u_mask_4 = io_update_u_mask_2_0; // @[tage.scala:24:7, :135:30]
wire update_u_mask_5 = io_update_u_mask_2_0; // @[tage.scala:24:7, :135:30]
wire update_u_mask_6 = io_update_u_mask_3_0; // @[tage.scala:24:7, :135:30]
wire update_u_mask_7 = io_update_u_mask_3_0; // @[tage.scala:24:7, :135:30]
wire [2:0] io_f2_resp_0_bits_ctr_0; // @[tage.scala:24:7]
wire [1:0] io_f2_resp_0_bits_u_0; // @[tage.scala:24:7]
wire io_f2_resp_0_valid_0; // @[tage.scala:24:7]
wire [2:0] io_f2_resp_1_bits_ctr_0; // @[tage.scala:24:7]
wire [1:0] io_f2_resp_1_bits_u_0; // @[tage.scala:24:7]
wire io_f2_resp_1_valid_0; // @[tage.scala:24:7]
wire [2:0] io_f2_resp_2_bits_ctr_0; // @[tage.scala:24:7]
wire [1:0] io_f2_resp_2_bits_u_0; // @[tage.scala:24:7]
wire io_f2_resp_2_valid_0; // @[tage.scala:24:7]
wire [2:0] io_f2_resp_3_bits_ctr_0; // @[tage.scala:24:7]
wire [1:0] io_f2_resp_3_bits_u_0; // @[tage.scala:24:7]
wire io_f2_resp_3_valid_0; // @[tage.scala:24:7]
reg doing_reset; // @[tage.scala:72:28]
reg [6:0] reset_idx; // @[tage.scala:73:26]
wire [7:0] _GEN = {1'h0, reset_idx}; // @[tage.scala:73:26, :74:26]
wire [7:0] _reset_idx_T = _GEN + {7'h0, doing_reset}; // @[tage.scala:72:28, :74:26]
wire [6:0] _reset_idx_T_1 = _reset_idx_T[6:0]; // @[tage.scala:74:26]
wire [1:0] idx_history = io_f1_req_ghist_0[1:0]; // @[tage.scala:24:7, :53:11]
wire [1:0] tag_history = io_f1_req_ghist_0[1:0]; // @[tage.scala:24:7, :53:11]
wire [36:0] _idx_T = {io_f1_req_pc_0[39:5], io_f1_req_pc_0[4:3] ^ idx_history}; // @[frontend.scala:149:35]
wire [6:0] s1_hashed_idx = _idx_T[6:0]; // @[tage.scala:60:{29,43}]
wire [6:0] _rdata_WIRE = s1_hashed_idx; // @[tage.scala:60:43, :122:99]
wire [6:0] _u_rdata_WIRE = s1_hashed_idx; // @[tage.scala:60:43, :140:12]
wire [29:0] _tag_T = io_f1_req_pc_0[39:10]; // @[frontend.scala:149:35]
wire [29:0] _tag_T_1 = {_tag_T[29:2], _tag_T[1:0] ^ tag_history}; // @[tage.scala:53:11, :62:{30,50}]
wire [6:0] s1_tag = _tag_T_1[6:0]; // @[tage.scala:62:{50,64}]
wire wdata_1_0; // @[tage.scala:145:20]
wire wdata_1_1; // @[tage.scala:145:20]
wire wdata_1_2; // @[tage.scala:145:20]
wire wdata_1_3; // @[tage.scala:145:20]
wire wdata_1_4; // @[tage.scala:145:20]
wire wdata_1_5; // @[tage.scala:145:20]
wire wdata_1_6; // @[tage.scala:145:20]
wire wdata_1_7; // @[tage.scala:145:20]
wire s2_req_rus_0 = _tage_u_2_R0_data[0]; // @[tage.scala:89:27, :99:24]
wire s2_req_rus_1 = _tage_u_2_R0_data[1]; // @[tage.scala:89:27, :99:24]
wire s2_req_rus_2 = _tage_u_2_R0_data[2]; // @[tage.scala:89:27, :99:24]
wire s2_req_rus_3 = _tage_u_2_R0_data[3]; // @[tage.scala:89:27, :99:24]
wire s2_req_rus_4 = _tage_u_2_R0_data[4]; // @[tage.scala:89:27, :99:24]
wire s2_req_rus_5 = _tage_u_2_R0_data[5]; // @[tage.scala:89:27, :99:24]
wire s2_req_rus_6 = _tage_u_2_R0_data[6]; // @[tage.scala:89:27, :99:24]
wire s2_req_rus_7 = _tage_u_2_R0_data[7]; // @[tage.scala:89:27, :99:24]
wire [10:0] wdata_0; // @[tage.scala:130:20]
wire [10:0] wdata_1; // @[tage.scala:130:20]
wire [10:0] wdata_2; // @[tage.scala:130:20]
wire [10:0] wdata_3; // @[tage.scala:130:20]
reg [6:0] s2_tag; // @[tage.scala:96:29]
assign io_f2_resp_0_bits_ctr_0 = s2_req_rtage_0_ctr; // @[tage.scala:24:7, :98:26]
assign io_f2_resp_1_bits_ctr_0 = s2_req_rtage_1_ctr; // @[tage.scala:24:7, :98:26]
assign io_f2_resp_2_bits_ctr_0 = s2_req_rtage_2_ctr; // @[tage.scala:24:7, :98:26]
assign io_f2_resp_3_bits_ctr_0 = s2_req_rtage_3_ctr; // @[tage.scala:24:7, :98:26]
wire s2_req_rtage_0_valid; // @[tage.scala:98:26]
wire [6:0] s2_req_rtage_0_tag; // @[tage.scala:98:26]
wire s2_req_rtage_1_valid; // @[tage.scala:98:26]
wire [6:0] s2_req_rtage_1_tag; // @[tage.scala:98:26]
wire s2_req_rtage_2_valid; // @[tage.scala:98:26]
wire [6:0] s2_req_rtage_2_tag; // @[tage.scala:98:26]
wire s2_req_rtage_3_valid; // @[tage.scala:98:26]
wire [6:0] s2_req_rtage_3_tag; // @[tage.scala:98:26]
wire _s2_req_rhits_T = s2_req_rtage_0_tag == s2_tag; // @[tage.scala:96:29, :98:26, :100:69]
wire _s2_req_rhits_T_1 = s2_req_rtage_0_valid & _s2_req_rhits_T; // @[tage.scala:98:26, :100:{60,69}]
wire _s2_req_rhits_T_2 = ~doing_reset; // @[tage.scala:72:28, :100:83]
wire _s2_req_rhits_T_3 = _s2_req_rhits_T_1 & _s2_req_rhits_T_2; // @[tage.scala:100:{60,80,83}]
assign s2_req_rhits_0 = _s2_req_rhits_T_3; // @[tage.scala:100:{29,80}]
wire _s2_req_rhits_T_4 = s2_req_rtage_1_tag == s2_tag; // @[tage.scala:96:29, :98:26, :100:69]
wire _s2_req_rhits_T_5 = s2_req_rtage_1_valid & _s2_req_rhits_T_4; // @[tage.scala:98:26, :100:{60,69}]
wire _s2_req_rhits_T_6 = ~doing_reset; // @[tage.scala:72:28, :100:83]
wire _s2_req_rhits_T_7 = _s2_req_rhits_T_5 & _s2_req_rhits_T_6; // @[tage.scala:100:{60,80,83}]
assign s2_req_rhits_1 = _s2_req_rhits_T_7; // @[tage.scala:100:{29,80}]
wire _s2_req_rhits_T_8 = s2_req_rtage_2_tag == s2_tag; // @[tage.scala:96:29, :98:26, :100:69]
wire _s2_req_rhits_T_9 = s2_req_rtage_2_valid & _s2_req_rhits_T_8; // @[tage.scala:98:26, :100:{60,69}]
wire _s2_req_rhits_T_10 = ~doing_reset; // @[tage.scala:72:28, :100:83]
wire _s2_req_rhits_T_11 = _s2_req_rhits_T_9 & _s2_req_rhits_T_10; // @[tage.scala:100:{60,80,83}]
assign s2_req_rhits_2 = _s2_req_rhits_T_11; // @[tage.scala:100:{29,80}]
wire _s2_req_rhits_T_12 = s2_req_rtage_3_tag == s2_tag; // @[tage.scala:96:29, :98:26, :100:69]
wire _s2_req_rhits_T_13 = s2_req_rtage_3_valid & _s2_req_rhits_T_12; // @[tage.scala:98:26, :100:{60,69}]
wire _s2_req_rhits_T_14 = ~doing_reset; // @[tage.scala:72:28, :100:83]
wire _s2_req_rhits_T_15 = _s2_req_rhits_T_13 & _s2_req_rhits_T_14; // @[tage.scala:100:{60,80,83}]
assign s2_req_rhits_3 = _s2_req_rhits_T_15; // @[tage.scala:100:{29,80}]
assign io_f2_resp_0_valid_0 = s2_req_rhits_0; // @[tage.scala:24:7, :100:29]
assign io_f2_resp_1_valid_0 = s2_req_rhits_1; // @[tage.scala:24:7, :100:29]
assign io_f2_resp_2_valid_0 = s2_req_rhits_2; // @[tage.scala:24:7, :100:29]
assign io_f2_resp_3_valid_0 = s2_req_rhits_3; // @[tage.scala:24:7, :100:29]
assign _io_f2_resp_0_bits_u_T = {s2_req_rus_1, s2_req_rus_0}; // @[tage.scala:99:24, :105:34]
assign io_f2_resp_0_bits_u_0 = _io_f2_resp_0_bits_u_T; // @[tage.scala:24:7, :105:34]
assign _io_f2_resp_1_bits_u_T = {s2_req_rus_3, s2_req_rus_2}; // @[tage.scala:99:24, :105:34]
assign io_f2_resp_1_bits_u_0 = _io_f2_resp_1_bits_u_T; // @[tage.scala:24:7, :105:34]
assign _io_f2_resp_2_bits_u_T = {s2_req_rus_5, s2_req_rus_4}; // @[tage.scala:99:24, :105:34]
assign io_f2_resp_2_bits_u_0 = _io_f2_resp_2_bits_u_T; // @[tage.scala:24:7, :105:34]
assign _io_f2_resp_3_bits_u_T = {s2_req_rus_7, s2_req_rus_6}; // @[tage.scala:99:24, :105:34]
assign io_f2_resp_3_bits_u_0 = _io_f2_resp_3_bits_u_T; // @[tage.scala:24:7, :105:34]
reg [18:0] clear_u_ctr; // @[tage.scala:109:28]
wire [19:0] _clear_u_ctr_T = {1'h0, clear_u_ctr} + 20'h1; // @[tage.scala:109:28, :110:85]
wire [18:0] _clear_u_ctr_T_1 = _clear_u_ctr_T[18:0]; // @[tage.scala:110:85]
wire [10:0] _doing_clear_u_T = clear_u_ctr[10:0]; // @[tage.scala:109:28, :112:34]
wire doing_clear_u = _doing_clear_u_T == 11'h0; // @[tage.scala:112:{34,61}]
wire _clear_u_hi_T = clear_u_ctr[18]; // @[tage.scala:109:28, :113:31]
wire _clear_u_lo_T = clear_u_ctr[18]; // @[tage.scala:109:28, :113:31, :114:31]
wire clear_u_hi = _clear_u_hi_T; // @[tage.scala:113:{31,72}]
wire _clear_u_mask_WIRE_1 = clear_u_hi; // @[tage.scala:113:72, :116:29]
wire _clear_u_mask_WIRE_3 = clear_u_hi; // @[tage.scala:113:72, :116:29]
wire _clear_u_mask_WIRE_5 = clear_u_hi; // @[tage.scala:113:72, :116:29]
wire _clear_u_mask_WIRE_7 = clear_u_hi; // @[tage.scala:113:72, :116:29]
wire clear_u_lo = ~_clear_u_lo_T; // @[tage.scala:114:{31,72}]
wire _clear_u_mask_WIRE_0 = clear_u_lo; // @[tage.scala:114:72, :116:29]
wire _clear_u_mask_WIRE_2 = clear_u_lo; // @[tage.scala:114:72, :116:29]
wire _clear_u_mask_WIRE_4 = clear_u_lo; // @[tage.scala:114:72, :116:29]
wire _clear_u_mask_WIRE_6 = clear_u_lo; // @[tage.scala:114:72, :116:29]
wire [7:0] clear_u_idx = clear_u_ctr[18:11]; // @[tage.scala:109:28, :115:33]
wire [1:0] clear_u_mask_lo_lo = {_clear_u_mask_WIRE_1, _clear_u_mask_WIRE_0}; // @[tage.scala:116:{29,109}]
wire [1:0] clear_u_mask_lo_hi = {_clear_u_mask_WIRE_3, _clear_u_mask_WIRE_2}; // @[tage.scala:116:{29,109}]
wire [3:0] clear_u_mask_lo = {clear_u_mask_lo_hi, clear_u_mask_lo_lo}; // @[tage.scala:116:109]
wire [1:0] clear_u_mask_hi_lo = {_clear_u_mask_WIRE_5, _clear_u_mask_WIRE_4}; // @[tage.scala:116:{29,109}]
wire [1:0] clear_u_mask_hi_hi = {_clear_u_mask_WIRE_7, _clear_u_mask_WIRE_6}; // @[tage.scala:116:{29,109}]
wire [3:0] clear_u_mask_hi = {clear_u_mask_hi_hi, clear_u_mask_hi_lo}; // @[tage.scala:116:109]
wire [7:0] clear_u_mask = {clear_u_mask_hi, clear_u_mask_lo}; // @[tage.scala:116:109]
wire [1:0] idx_history_1 = io_update_hist_0[1:0]; // @[tage.scala:24:7, :53:11]
wire [1:0] tag_history_1 = io_update_hist_0[1:0]; // @[tage.scala:24:7, :53:11]
wire [36:0] _idx_T_1 = {io_update_pc_0[39:5], io_update_pc_0[4:3] ^ idx_history_1}; // @[frontend.scala:149:35]
wire [6:0] update_idx = _idx_T_1[6:0]; // @[tage.scala:60:{29,43}]
wire [29:0] _tag_T_2 = io_update_pc_0[39:10]; // @[frontend.scala:149:35]
wire [29:0] _tag_T_3 = {_tag_T_2[29:2], _tag_T_2[1:0] ^ tag_history_1}; // @[tage.scala:53:11, :62:{30,50}]
wire [6:0] update_tag = _tag_T_3[6:0]; // @[tage.scala:62:{50,64}]
wire [6:0] update_wdata_0_tag = update_tag; // @[tage.scala:62:64, :120:26]
wire [6:0] update_wdata_1_tag = update_tag; // @[tage.scala:62:64, :120:26]
wire [6:0] update_wdata_2_tag = update_tag; // @[tage.scala:62:64, :120:26]
wire [6:0] update_wdata_3_tag = update_tag; // @[tage.scala:62:64, :120:26]
wire [2:0] _update_wdata_0_ctr_T_22; // @[tage.scala:168:33]
wire [2:0] _update_wdata_1_ctr_T_22; // @[tage.scala:168:33]
wire [2:0] _update_wdata_2_ctr_T_22; // @[tage.scala:168:33]
wire [2:0] _update_wdata_3_ctr_T_22; // @[tage.scala:168:33]
wire [2:0] update_wdata_0_ctr; // @[tage.scala:120:26]
wire [2:0] update_wdata_1_ctr; // @[tage.scala:120:26]
wire [2:0] update_wdata_2_ctr; // @[tage.scala:120:26]
wire [2:0] update_wdata_3_ctr; // @[tage.scala:120:26]
wire _wen_T = io_update_mask_0_0 | io_update_mask_1_0; // @[tage.scala:24:7, :121:60]
wire _wen_T_1 = _wen_T | io_update_mask_2_0; // @[tage.scala:24:7, :121:60]
wire _wen_T_2 = _wen_T_1 | io_update_mask_3_0; // @[tage.scala:24:7, :121:60]
wire _wen_T_3 = doing_reset | _wen_T_2; // @[tage.scala:72:28, :121:{34,60}]
wire wen = _wen_T_3; // @[tage.scala:121:{21,34}]
reg REG; // @[tage.scala:123:16]
assign s2_req_rtage_0_ctr = _tage_table_2_R0_data[2:0]; // @[tage.scala:90:27, :98:26, :126:49]
assign s2_req_rtage_0_tag = _tage_table_2_R0_data[9:3]; // @[tage.scala:90:27, :98:26, :126:49]
assign s2_req_rtage_0_valid = _tage_table_2_R0_data[10]; // @[tage.scala:90:27, :98:26, :126:49]
assign s2_req_rtage_1_ctr = _tage_table_2_R0_data[13:11]; // @[tage.scala:90:27, :98:26, :126:49]
assign s2_req_rtage_1_tag = _tage_table_2_R0_data[20:14]; // @[tage.scala:90:27, :98:26, :126:49]
assign s2_req_rtage_1_valid = _tage_table_2_R0_data[21]; // @[tage.scala:90:27, :98:26, :126:49]
assign s2_req_rtage_2_ctr = _tage_table_2_R0_data[24:22]; // @[tage.scala:90:27, :98:26, :126:49]
assign s2_req_rtage_2_tag = _tage_table_2_R0_data[31:25]; // @[tage.scala:90:27, :98:26, :126:49]
assign s2_req_rtage_2_valid = _tage_table_2_R0_data[32]; // @[tage.scala:90:27, :98:26, :126:49]
assign s2_req_rtage_3_ctr = _tage_table_2_R0_data[35:33]; // @[tage.scala:90:27, :98:26, :126:49]
assign s2_req_rtage_3_tag = _tage_table_2_R0_data[42:36]; // @[tage.scala:90:27, :98:26, :126:49]
assign s2_req_rtage_3_valid = _tage_table_2_R0_data[43]; // @[tage.scala:90:27, :98:26, :126:49]
wire [6:0] widx = doing_reset ? reset_idx : update_idx; // @[tage.scala:60:43, :72:28, :73:26, :129:19]
wire [7:0] wdata_hi = {1'h1, update_wdata_0_tag}; // @[tage.scala:120:26, :130:114]
wire [10:0] _wdata_T = {wdata_hi, update_wdata_0_ctr}; // @[tage.scala:120:26, :130:114]
wire [10:0] _wdata_WIRE_1_0 = _wdata_T; // @[tage.scala:130:{94,114}]
wire [7:0] wdata_hi_1 = {1'h1, update_wdata_1_tag}; // @[tage.scala:120:26, :130:114]
wire [10:0] _wdata_T_1 = {wdata_hi_1, update_wdata_1_ctr}; // @[tage.scala:120:26, :130:114]
wire [10:0] _wdata_WIRE_1_1 = _wdata_T_1; // @[tage.scala:130:{94,114}]
wire [7:0] wdata_hi_2 = {1'h1, update_wdata_2_tag}; // @[tage.scala:120:26, :130:114]
wire [10:0] _wdata_T_2 = {wdata_hi_2, update_wdata_2_ctr}; // @[tage.scala:120:26, :130:114]
wire [10:0] _wdata_WIRE_1_2 = _wdata_T_2; // @[tage.scala:130:{94,114}]
wire [7:0] wdata_hi_3 = {1'h1, update_wdata_3_tag}; // @[tage.scala:120:26, :130:114]
wire [10:0] _wdata_T_3 = {wdata_hi_3, update_wdata_3_ctr}; // @[tage.scala:120:26, :130:114]
wire [10:0] _wdata_WIRE_1_3 = _wdata_T_3; // @[tage.scala:130:{94,114}]
assign wdata_0 = doing_reset ? 11'h0 : _wdata_WIRE_1_0; // @[tage.scala:72:28, :130:{20,94}]
assign wdata_1 = doing_reset ? 11'h0 : _wdata_WIRE_1_1; // @[tage.scala:72:28, :130:{20,94}]
assign wdata_2 = doing_reset ? 11'h0 : _wdata_WIRE_1_2; // @[tage.scala:72:28, :130:{20,94}]
assign wdata_3 = doing_reset ? 11'h0 : _wdata_WIRE_1_3; // @[tage.scala:72:28, :130:{20,94}]
wire [1:0] wmask_lo = {io_update_mask_1_0, io_update_mask_0_0}; // @[tage.scala:24:7, :131:70]
wire [1:0] wmask_hi = {io_update_mask_3_0, io_update_mask_2_0}; // @[tage.scala:24:7, :131:70]
wire [3:0] _wmask_T_1 = {wmask_hi, wmask_lo}; // @[tage.scala:131:70]
wire [3:0] wmask = doing_reset ? 4'hF : _wmask_T_1; // @[tage.scala:72:28, :131:{20,70}]
wire _GEN_0 = doing_reset | doing_clear_u; // @[tage.scala:72:28, :112:61, :136:43]
wire _update_u_wen_T; // @[tage.scala:136:43]
assign _update_u_wen_T = _GEN_0; // @[tage.scala:136:43]
wire _wdata_T_4; // @[tage.scala:145:33]
assign _wdata_T_4 = _GEN_0; // @[tage.scala:136:43, :145:33]
wire _update_u_wen_T_1 = update_u_mask_0 | update_u_mask_1; // @[tage.scala:135:30, :136:85]
wire _update_u_wen_T_2 = _update_u_wen_T_1 | update_u_mask_2; // @[tage.scala:135:30, :136:85]
wire _update_u_wen_T_3 = _update_u_wen_T_2 | update_u_mask_3; // @[tage.scala:135:30, :136:85]
wire _update_u_wen_T_4 = _update_u_wen_T_3 | update_u_mask_4; // @[tage.scala:135:30, :136:85]
wire _update_u_wen_T_5 = _update_u_wen_T_4 | update_u_mask_5; // @[tage.scala:135:30, :136:85]
wire _update_u_wen_T_6 = _update_u_wen_T_5 | update_u_mask_6; // @[tage.scala:135:30, :136:85]
wire _update_u_wen_T_7 = _update_u_wen_T_6 | update_u_mask_7; // @[tage.scala:135:30, :136:85]
wire _update_u_wen_T_8 = _update_u_wen_T | _update_u_wen_T_7; // @[tage.scala:136:{43,60,85}]
wire update_u_wen = _update_u_wen_T_8; // @[tage.scala:136:{30,60}]
wire [7:0] _widx_T = doing_clear_u ? clear_u_idx : {1'h0, update_idx}; // @[tage.scala:60:43, :112:61, :115:33, :144:47]
wire [7:0] widx_1 = doing_reset ? _GEN : _widx_T; // @[tage.scala:72:28, :74:26, :144:{19,47}]
wire [3:0] wdata_lo = {io_update_u_1_0, io_update_u_0_0}; // @[tage.scala:24:7, :145:110]
wire [3:0] wdata_hi_4 = {io_update_u_3_0, io_update_u_2_0}; // @[tage.scala:24:7, :145:110]
wire [7:0] _wdata_T_5 = {wdata_hi_4, wdata_lo}; // @[tage.scala:145:110]
wire _wdata_T_6 = _wdata_T_5[0]; // @[tage.scala:145:{110,117}]
wire _wdata_WIRE_3_0 = _wdata_T_6; // @[tage.scala:145:{97,117}]
wire _wdata_T_7 = _wdata_T_5[1]; // @[tage.scala:145:{110,117}]
wire _wdata_WIRE_3_1 = _wdata_T_7; // @[tage.scala:145:{97,117}]
wire _wdata_T_8 = _wdata_T_5[2]; // @[tage.scala:145:{110,117}]
wire _wdata_WIRE_3_2 = _wdata_T_8; // @[tage.scala:145:{97,117}]
wire _wdata_T_9 = _wdata_T_5[3]; // @[tage.scala:145:{110,117}]
wire _wdata_WIRE_3_3 = _wdata_T_9; // @[tage.scala:145:{97,117}]
wire _wdata_T_10 = _wdata_T_5[4]; // @[tage.scala:145:{110,117}]
wire _wdata_WIRE_3_4 = _wdata_T_10; // @[tage.scala:145:{97,117}]
wire _wdata_T_11 = _wdata_T_5[5]; // @[tage.scala:145:{110,117}]
wire _wdata_WIRE_3_5 = _wdata_T_11; // @[tage.scala:145:{97,117}]
wire _wdata_T_12 = _wdata_T_5[6]; // @[tage.scala:145:{110,117}]
wire _wdata_WIRE_3_6 = _wdata_T_12; // @[tage.scala:145:{97,117}]
wire _wdata_T_13 = _wdata_T_5[7]; // @[tage.scala:145:{110,117}]
wire _wdata_WIRE_3_7 = _wdata_T_13; // @[tage.scala:145:{97,117}]
assign wdata_1_0 = ~_wdata_T_4 & _wdata_WIRE_3_0; // @[tage.scala:145:{20,33,97}]
assign wdata_1_1 = ~_wdata_T_4 & _wdata_WIRE_3_1; // @[tage.scala:145:{20,33,97}]
assign wdata_1_2 = ~_wdata_T_4 & _wdata_WIRE_3_2; // @[tage.scala:145:{20,33,97}]
assign wdata_1_3 = ~_wdata_T_4 & _wdata_WIRE_3_3; // @[tage.scala:145:{20,33,97}]
assign wdata_1_4 = ~_wdata_T_4 & _wdata_WIRE_3_4; // @[tage.scala:145:{20,33,97}]
assign wdata_1_5 = ~_wdata_T_4 & _wdata_WIRE_3_5; // @[tage.scala:145:{20,33,97}]
assign wdata_1_6 = ~_wdata_T_4 & _wdata_WIRE_3_6; // @[tage.scala:145:{20,33,97}]
assign wdata_1_7 = ~_wdata_T_4 & _wdata_WIRE_3_7; // @[tage.scala:145:{20,33,97}]
wire [1:0] wmask_lo_lo = {update_u_mask_1, update_u_mask_0}; // @[tage.scala:135:30, :146:106]
wire [1:0] wmask_lo_hi = {update_u_mask_3, update_u_mask_2}; // @[tage.scala:135:30, :146:106]
wire [3:0] wmask_lo_1 = {wmask_lo_hi, wmask_lo_lo}; // @[tage.scala:146:106]
wire [1:0] wmask_hi_lo = {update_u_mask_5, update_u_mask_4}; // @[tage.scala:135:30, :146:106]
wire [1:0] wmask_hi_hi = {update_u_mask_7, update_u_mask_6}; // @[tage.scala:135:30, :146:106]
wire [3:0] wmask_hi_1 = {wmask_hi_hi, wmask_hi_lo}; // @[tage.scala:146:106]
wire [7:0] _wmask_T_3 = {wmask_hi_1, wmask_lo_1}; // @[tage.scala:146:106]
wire [7:0] _wmask_T_4 = doing_clear_u ? clear_u_mask : _wmask_T_3; // @[tage.scala:112:61, :116:109, :146:{62,106}]
wire [7:0] wmask_1 = doing_reset ? 8'hFF : _wmask_T_4; // @[tage.scala:72:28, :146:{20,62}]
reg [6:0] wrbypass_tags_0; // @[tage.scala:154:29]
reg [6:0] wrbypass_tags_1; // @[tage.scala:154:29]
reg [6:0] wrbypass_idxs_0; // @[tage.scala:155:29]
reg [6:0] wrbypass_idxs_1; // @[tage.scala:155:29]
reg [2:0] wrbypass_0_0; // @[tage.scala:156:29]
reg [2:0] wrbypass_0_1; // @[tage.scala:156:29]
reg [2:0] wrbypass_0_2; // @[tage.scala:156:29]
reg [2:0] wrbypass_0_3; // @[tage.scala:156:29]
reg [2:0] wrbypass_1_0; // @[tage.scala:156:29]
reg [2:0] wrbypass_1_1; // @[tage.scala:156:29]
reg [2:0] wrbypass_1_2; // @[tage.scala:156:29]
reg [2:0] wrbypass_1_3; // @[tage.scala:156:29]
reg wrbypass_enq_idx; // @[tage.scala:157:33]
wire _wrbypass_hits_T = ~doing_reset; // @[tage.scala:72:28, :100:83, :160:5]
wire _wrbypass_hits_T_1 = wrbypass_tags_0 == update_tag; // @[tage.scala:62:64, :154:29, :161:22]
wire _wrbypass_hits_T_2 = _wrbypass_hits_T & _wrbypass_hits_T_1; // @[tage.scala:160:{5,18}, :161:22]
wire _wrbypass_hits_T_3 = wrbypass_idxs_0 == update_idx; // @[tage.scala:60:43, :155:29, :162:22]
wire _wrbypass_hits_T_4 = _wrbypass_hits_T_2 & _wrbypass_hits_T_3; // @[tage.scala:160:18, :161:37, :162:22]
wire wrbypass_hits_0 = _wrbypass_hits_T_4; // @[tage.scala:159:33, :161:37]
wire _wrbypass_hits_T_5 = ~doing_reset; // @[tage.scala:72:28, :100:83, :160:5]
wire _wrbypass_hits_T_6 = wrbypass_tags_1 == update_tag; // @[tage.scala:62:64, :154:29, :161:22]
wire _wrbypass_hits_T_7 = _wrbypass_hits_T_5 & _wrbypass_hits_T_6; // @[tage.scala:160:{5,18}, :161:22]
wire _wrbypass_hits_T_8 = wrbypass_idxs_1 == update_idx; // @[tage.scala:60:43, :155:29, :162:22]
wire _wrbypass_hits_T_9 = _wrbypass_hits_T_7 & _wrbypass_hits_T_8; // @[tage.scala:160:18, :161:37, :162:22]
wire wrbypass_hits_1 = _wrbypass_hits_T_9; // @[tage.scala:159:33, :161:37]
wire wrbypass_hit = wrbypass_hits_0 | wrbypass_hits_1; // @[tage.scala:159:33, :164:48]
wire wrbypass_hit_idx = ~wrbypass_hits_0; // @[Mux.scala:50:70]
wire [2:0] _update_wdata_0_ctr_T = io_update_taken_0_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :169:10]
wire _update_wdata_0_ctr_T_1 = ~io_update_taken_0_0; // @[tage.scala:24:7, :67:9]
wire [2:0] _GEN_1 = wrbypass_hit_idx ? wrbypass_1_0 : wrbypass_0_0; // @[Mux.scala:50:70]
wire [2:0] _GEN_2 = wrbypass_hit_idx ? wrbypass_1_1 : wrbypass_0_1; // @[Mux.scala:50:70]
wire [2:0] _GEN_3 = wrbypass_hit_idx ? wrbypass_1_2 : wrbypass_0_2; // @[Mux.scala:50:70]
wire [2:0] _GEN_4 = wrbypass_hit_idx ? wrbypass_1_3 : wrbypass_0_3; // @[Mux.scala:50:70]
wire _update_wdata_0_ctr_T_2 = _GEN_1 == 3'h0; // @[tage.scala:67:25]
wire [3:0] _GEN_5 = {1'h0, _GEN_1}; // @[tage.scala:67:{25,43}]
wire [3:0] _update_wdata_0_ctr_T_3 = _GEN_5 - 4'h1; // @[tage.scala:67:43]
wire [2:0] _update_wdata_0_ctr_T_4 = _update_wdata_0_ctr_T_3[2:0]; // @[tage.scala:67:43]
wire [2:0] _update_wdata_0_ctr_T_5 = _update_wdata_0_ctr_T_2 ? 3'h0 : _update_wdata_0_ctr_T_4; // @[tage.scala:67:{20,25,43}]
wire _update_wdata_0_ctr_T_6 = &_GEN_1; // @[tage.scala:67:25, :68:25]
wire [3:0] _update_wdata_0_ctr_T_7 = _GEN_5 + 4'h1; // @[tage.scala:67:43, :68:43]
wire [2:0] _update_wdata_0_ctr_T_8 = _update_wdata_0_ctr_T_7[2:0]; // @[tage.scala:68:43]
wire [2:0] _update_wdata_0_ctr_T_9 = _update_wdata_0_ctr_T_6 ? 3'h7 : _update_wdata_0_ctr_T_8; // @[tage.scala:68:{20,25,43}]
wire [2:0] _update_wdata_0_ctr_T_10 = _update_wdata_0_ctr_T_1 ? _update_wdata_0_ctr_T_5 : _update_wdata_0_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20]
wire _update_wdata_0_ctr_T_11 = ~io_update_taken_0_0; // @[tage.scala:24:7, :67:9]
wire _update_wdata_0_ctr_T_12 = io_update_old_ctr_0_0 == 3'h0; // @[tage.scala:24:7, :67:25]
wire [3:0] _GEN_6 = {1'h0, io_update_old_ctr_0_0}; // @[tage.scala:24:7, :67:43]
wire [3:0] _update_wdata_0_ctr_T_13 = _GEN_6 - 4'h1; // @[tage.scala:67:43]
wire [2:0] _update_wdata_0_ctr_T_14 = _update_wdata_0_ctr_T_13[2:0]; // @[tage.scala:67:43]
wire [2:0] _update_wdata_0_ctr_T_15 = _update_wdata_0_ctr_T_12 ? 3'h0 : _update_wdata_0_ctr_T_14; // @[tage.scala:67:{20,25,43}]
wire _update_wdata_0_ctr_T_16 = &io_update_old_ctr_0_0; // @[tage.scala:24:7, :68:25]
wire [3:0] _update_wdata_0_ctr_T_17 = _GEN_6 + 4'h1; // @[tage.scala:67:43, :68:43]
wire [2:0] _update_wdata_0_ctr_T_18 = _update_wdata_0_ctr_T_17[2:0]; // @[tage.scala:68:43]
wire [2:0] _update_wdata_0_ctr_T_19 = _update_wdata_0_ctr_T_16 ? 3'h7 : _update_wdata_0_ctr_T_18; // @[tage.scala:68:{20,25,43}]
wire [2:0] _update_wdata_0_ctr_T_20 = _update_wdata_0_ctr_T_11 ? _update_wdata_0_ctr_T_15 : _update_wdata_0_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20]
wire [2:0] _update_wdata_0_ctr_T_21 = wrbypass_hit ? _update_wdata_0_ctr_T_10 : _update_wdata_0_ctr_T_20; // @[tage.scala:67:8, :164:48, :172:10]
assign _update_wdata_0_ctr_T_22 = io_update_alloc_0_0 ? _update_wdata_0_ctr_T : _update_wdata_0_ctr_T_21; // @[tage.scala:24:7, :168:33, :169:10, :172:10]
assign update_wdata_0_ctr = _update_wdata_0_ctr_T_22; // @[tage.scala:120:26, :168:33]
wire [2:0] _update_wdata_1_ctr_T = io_update_taken_1_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :169:10]
wire _update_wdata_1_ctr_T_1 = ~io_update_taken_1_0; // @[tage.scala:24:7, :67:9]
wire _update_wdata_1_ctr_T_2 = _GEN_2 == 3'h0; // @[tage.scala:67:25]
wire [3:0] _GEN_7 = {1'h0, _GEN_2}; // @[tage.scala:67:{25,43}]
wire [3:0] _update_wdata_1_ctr_T_3 = _GEN_7 - 4'h1; // @[tage.scala:67:43]
wire [2:0] _update_wdata_1_ctr_T_4 = _update_wdata_1_ctr_T_3[2:0]; // @[tage.scala:67:43]
wire [2:0] _update_wdata_1_ctr_T_5 = _update_wdata_1_ctr_T_2 ? 3'h0 : _update_wdata_1_ctr_T_4; // @[tage.scala:67:{20,25,43}]
wire _update_wdata_1_ctr_T_6 = &_GEN_2; // @[tage.scala:67:25, :68:25]
wire [3:0] _update_wdata_1_ctr_T_7 = _GEN_7 + 4'h1; // @[tage.scala:67:43, :68:43]
wire [2:0] _update_wdata_1_ctr_T_8 = _update_wdata_1_ctr_T_7[2:0]; // @[tage.scala:68:43]
wire [2:0] _update_wdata_1_ctr_T_9 = _update_wdata_1_ctr_T_6 ? 3'h7 : _update_wdata_1_ctr_T_8; // @[tage.scala:68:{20,25,43}]
wire [2:0] _update_wdata_1_ctr_T_10 = _update_wdata_1_ctr_T_1 ? _update_wdata_1_ctr_T_5 : _update_wdata_1_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20]
wire _update_wdata_1_ctr_T_11 = ~io_update_taken_1_0; // @[tage.scala:24:7, :67:9]
wire _update_wdata_1_ctr_T_12 = io_update_old_ctr_1_0 == 3'h0; // @[tage.scala:24:7, :67:25]
wire [3:0] _GEN_8 = {1'h0, io_update_old_ctr_1_0}; // @[tage.scala:24:7, :67:43]
wire [3:0] _update_wdata_1_ctr_T_13 = _GEN_8 - 4'h1; // @[tage.scala:67:43]
wire [2:0] _update_wdata_1_ctr_T_14 = _update_wdata_1_ctr_T_13[2:0]; // @[tage.scala:67:43]
wire [2:0] _update_wdata_1_ctr_T_15 = _update_wdata_1_ctr_T_12 ? 3'h0 : _update_wdata_1_ctr_T_14; // @[tage.scala:67:{20,25,43}]
wire _update_wdata_1_ctr_T_16 = &io_update_old_ctr_1_0; // @[tage.scala:24:7, :68:25]
wire [3:0] _update_wdata_1_ctr_T_17 = _GEN_8 + 4'h1; // @[tage.scala:67:43, :68:43]
wire [2:0] _update_wdata_1_ctr_T_18 = _update_wdata_1_ctr_T_17[2:0]; // @[tage.scala:68:43]
wire [2:0] _update_wdata_1_ctr_T_19 = _update_wdata_1_ctr_T_16 ? 3'h7 : _update_wdata_1_ctr_T_18; // @[tage.scala:68:{20,25,43}]
wire [2:0] _update_wdata_1_ctr_T_20 = _update_wdata_1_ctr_T_11 ? _update_wdata_1_ctr_T_15 : _update_wdata_1_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20]
wire [2:0] _update_wdata_1_ctr_T_21 = wrbypass_hit ? _update_wdata_1_ctr_T_10 : _update_wdata_1_ctr_T_20; // @[tage.scala:67:8, :164:48, :172:10]
assign _update_wdata_1_ctr_T_22 = io_update_alloc_1_0 ? _update_wdata_1_ctr_T : _update_wdata_1_ctr_T_21; // @[tage.scala:24:7, :168:33, :169:10, :172:10]
assign update_wdata_1_ctr = _update_wdata_1_ctr_T_22; // @[tage.scala:120:26, :168:33]
wire [2:0] _update_wdata_2_ctr_T = io_update_taken_2_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :169:10]
wire _update_wdata_2_ctr_T_1 = ~io_update_taken_2_0; // @[tage.scala:24:7, :67:9]
wire _update_wdata_2_ctr_T_2 = _GEN_3 == 3'h0; // @[tage.scala:67:25]
wire [3:0] _GEN_9 = {1'h0, _GEN_3}; // @[tage.scala:67:{25,43}]
wire [3:0] _update_wdata_2_ctr_T_3 = _GEN_9 - 4'h1; // @[tage.scala:67:43]
wire [2:0] _update_wdata_2_ctr_T_4 = _update_wdata_2_ctr_T_3[2:0]; // @[tage.scala:67:43]
wire [2:0] _update_wdata_2_ctr_T_5 = _update_wdata_2_ctr_T_2 ? 3'h0 : _update_wdata_2_ctr_T_4; // @[tage.scala:67:{20,25,43}]
wire _update_wdata_2_ctr_T_6 = &_GEN_3; // @[tage.scala:67:25, :68:25]
wire [3:0] _update_wdata_2_ctr_T_7 = _GEN_9 + 4'h1; // @[tage.scala:67:43, :68:43]
wire [2:0] _update_wdata_2_ctr_T_8 = _update_wdata_2_ctr_T_7[2:0]; // @[tage.scala:68:43]
wire [2:0] _update_wdata_2_ctr_T_9 = _update_wdata_2_ctr_T_6 ? 3'h7 : _update_wdata_2_ctr_T_8; // @[tage.scala:68:{20,25,43}]
wire [2:0] _update_wdata_2_ctr_T_10 = _update_wdata_2_ctr_T_1 ? _update_wdata_2_ctr_T_5 : _update_wdata_2_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20]
wire _update_wdata_2_ctr_T_11 = ~io_update_taken_2_0; // @[tage.scala:24:7, :67:9]
wire _update_wdata_2_ctr_T_12 = io_update_old_ctr_2_0 == 3'h0; // @[tage.scala:24:7, :67:25]
wire [3:0] _GEN_10 = {1'h0, io_update_old_ctr_2_0}; // @[tage.scala:24:7, :67:43]
wire [3:0] _update_wdata_2_ctr_T_13 = _GEN_10 - 4'h1; // @[tage.scala:67:43]
wire [2:0] _update_wdata_2_ctr_T_14 = _update_wdata_2_ctr_T_13[2:0]; // @[tage.scala:67:43]
wire [2:0] _update_wdata_2_ctr_T_15 = _update_wdata_2_ctr_T_12 ? 3'h0 : _update_wdata_2_ctr_T_14; // @[tage.scala:67:{20,25,43}]
wire _update_wdata_2_ctr_T_16 = &io_update_old_ctr_2_0; // @[tage.scala:24:7, :68:25]
wire [3:0] _update_wdata_2_ctr_T_17 = _GEN_10 + 4'h1; // @[tage.scala:67:43, :68:43]
wire [2:0] _update_wdata_2_ctr_T_18 = _update_wdata_2_ctr_T_17[2:0]; // @[tage.scala:68:43]
wire [2:0] _update_wdata_2_ctr_T_19 = _update_wdata_2_ctr_T_16 ? 3'h7 : _update_wdata_2_ctr_T_18; // @[tage.scala:68:{20,25,43}]
wire [2:0] _update_wdata_2_ctr_T_20 = _update_wdata_2_ctr_T_11 ? _update_wdata_2_ctr_T_15 : _update_wdata_2_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20]
wire [2:0] _update_wdata_2_ctr_T_21 = wrbypass_hit ? _update_wdata_2_ctr_T_10 : _update_wdata_2_ctr_T_20; // @[tage.scala:67:8, :164:48, :172:10]
assign _update_wdata_2_ctr_T_22 = io_update_alloc_2_0 ? _update_wdata_2_ctr_T : _update_wdata_2_ctr_T_21; // @[tage.scala:24:7, :168:33, :169:10, :172:10]
assign update_wdata_2_ctr = _update_wdata_2_ctr_T_22; // @[tage.scala:120:26, :168:33]
wire [2:0] _update_wdata_3_ctr_T = io_update_taken_3_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :169:10]
wire _update_wdata_3_ctr_T_1 = ~io_update_taken_3_0; // @[tage.scala:24:7, :67:9]
wire _update_wdata_3_ctr_T_2 = _GEN_4 == 3'h0; // @[tage.scala:67:25]
wire [3:0] _GEN_11 = {1'h0, _GEN_4}; // @[tage.scala:67:{25,43}]
wire [3:0] _update_wdata_3_ctr_T_3 = _GEN_11 - 4'h1; // @[tage.scala:67:43]
wire [2:0] _update_wdata_3_ctr_T_4 = _update_wdata_3_ctr_T_3[2:0]; // @[tage.scala:67:43]
wire [2:0] _update_wdata_3_ctr_T_5 = _update_wdata_3_ctr_T_2 ? 3'h0 : _update_wdata_3_ctr_T_4; // @[tage.scala:67:{20,25,43}]
wire _update_wdata_3_ctr_T_6 = &_GEN_4; // @[tage.scala:67:25, :68:25]
wire [3:0] _update_wdata_3_ctr_T_7 = _GEN_11 + 4'h1; // @[tage.scala:67:43, :68:43]
wire [2:0] _update_wdata_3_ctr_T_8 = _update_wdata_3_ctr_T_7[2:0]; // @[tage.scala:68:43]
wire [2:0] _update_wdata_3_ctr_T_9 = _update_wdata_3_ctr_T_6 ? 3'h7 : _update_wdata_3_ctr_T_8; // @[tage.scala:68:{20,25,43}]
wire [2:0] _update_wdata_3_ctr_T_10 = _update_wdata_3_ctr_T_1 ? _update_wdata_3_ctr_T_5 : _update_wdata_3_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20]
wire _update_wdata_3_ctr_T_11 = ~io_update_taken_3_0; // @[tage.scala:24:7, :67:9]
wire _update_wdata_3_ctr_T_12 = io_update_old_ctr_3_0 == 3'h0; // @[tage.scala:24:7, :67:25]
wire [3:0] _GEN_12 = {1'h0, io_update_old_ctr_3_0}; // @[tage.scala:24:7, :67:43]
wire [3:0] _update_wdata_3_ctr_T_13 = _GEN_12 - 4'h1; // @[tage.scala:67:43]
wire [2:0] _update_wdata_3_ctr_T_14 = _update_wdata_3_ctr_T_13[2:0]; // @[tage.scala:67:43]
wire [2:0] _update_wdata_3_ctr_T_15 = _update_wdata_3_ctr_T_12 ? 3'h0 : _update_wdata_3_ctr_T_14; // @[tage.scala:67:{20,25,43}]
wire _update_wdata_3_ctr_T_16 = &io_update_old_ctr_3_0; // @[tage.scala:24:7, :68:25]
wire [3:0] _update_wdata_3_ctr_T_17 = _GEN_12 + 4'h1; // @[tage.scala:67:43, :68:43]
wire [2:0] _update_wdata_3_ctr_T_18 = _update_wdata_3_ctr_T_17[2:0]; // @[tage.scala:68:43]
wire [2:0] _update_wdata_3_ctr_T_19 = _update_wdata_3_ctr_T_16 ? 3'h7 : _update_wdata_3_ctr_T_18; // @[tage.scala:68:{20,25,43}]
wire [2:0] _update_wdata_3_ctr_T_20 = _update_wdata_3_ctr_T_11 ? _update_wdata_3_ctr_T_15 : _update_wdata_3_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20]
wire [2:0] _update_wdata_3_ctr_T_21 = wrbypass_hit ? _update_wdata_3_ctr_T_10 : _update_wdata_3_ctr_T_20; // @[tage.scala:67:8, :164:48, :172:10]
assign _update_wdata_3_ctr_T_22 = io_update_alloc_3_0 ? _update_wdata_3_ctr_T : _update_wdata_3_ctr_T_21; // @[tage.scala:24:7, :168:33, :169:10, :172:10]
assign update_wdata_3_ctr = _update_wdata_3_ctr_T_22; // @[tage.scala:120:26, :168:33]
wire [1:0] _wrbypass_enq_idx_T = {1'h0, wrbypass_enq_idx} + 2'h1; // @[util.scala:211:14]
wire _wrbypass_enq_idx_T_1 = _wrbypass_enq_idx_T[0]; // @[util.scala:211:14]
wire _wrbypass_enq_idx_T_2 = _wrbypass_enq_idx_T_1; // @[util.scala:211:{14,20}]
wire _T_31 = _wen_T | io_update_mask_2_0 | io_update_mask_3_0; // @[tage.scala:24:7, :121:60, :180:32]
wire _GEN_13 = wrbypass_hit ? wrbypass_hit_idx : wrbypass_enq_idx; // @[Mux.scala:50:70]
wire _GEN_14 = ~_T_31 | wrbypass_hit | wrbypass_enq_idx; // @[tage.scala:154:29, :156:29, :157:33, :164:48, :180:{32,38}, :181:39, :185:39]
wire _GEN_15 = ~_T_31 | wrbypass_hit | ~wrbypass_enq_idx; // @[tage.scala:154:29, :156:29, :157:33, :164:48, :180:{32,38}, :181:39, :185:39]
always @(posedge clock) begin // @[tage.scala:24:7]
if (reset) begin // @[tage.scala:24:7]
doing_reset <= 1'h1; // @[tage.scala:72:28]
reset_idx <= 7'h0; // @[tage.scala:73:26]
clear_u_ctr <= 19'h0; // @[tage.scala:109:28]
wrbypass_enq_idx <= 1'h0; // @[tage.scala:157:33]
end
else begin // @[tage.scala:24:7]
doing_reset <= reset_idx != 7'h7F & doing_reset; // @[tage.scala:72:28, :73:26, :75:{19,36,50}]
reset_idx <= _reset_idx_T_1; // @[tage.scala:73:26, :74:26]
clear_u_ctr <= doing_reset ? 19'h1 : _clear_u_ctr_T_1; // @[tage.scala:72:28, :109:28, :110:{22,36,70,85}]
if (~_T_31 | wrbypass_hit) begin // @[tage.scala:156:29, :157:33, :164:48, :180:{32,38}, :181:39]
end
else // @[tage.scala:157:33, :180:38, :181:39]
wrbypass_enq_idx <= _wrbypass_enq_idx_T_2; // @[util.scala:211:20]
end
s2_tag <= s1_tag; // @[tage.scala:62:64, :96:29]
REG <= wen; // @[tage.scala:121:21, :123:16]
if (_GEN_14) begin // @[tage.scala:154:29, :180:38, :181:39, :185:39]
end
else // @[tage.scala:154:29, :180:38, :181:39, :185:39]
wrbypass_tags_0 <= update_tag; // @[tage.scala:62:64, :154:29]
if (_GEN_15) begin // @[tage.scala:154:29, :180:38, :181:39, :185:39]
end
else // @[tage.scala:154:29, :180:38, :181:39, :185:39]
wrbypass_tags_1 <= update_tag; // @[tage.scala:62:64, :154:29]
if (_GEN_14) begin // @[tage.scala:154:29, :155:29, :180:38, :181:39, :185:39, :186:39]
end
else // @[tage.scala:155:29, :180:38, :181:39, :186:39]
wrbypass_idxs_0 <= update_idx; // @[tage.scala:60:43, :155:29]
if (_GEN_15) begin // @[tage.scala:154:29, :155:29, :180:38, :181:39, :185:39, :186:39]
end
else // @[tage.scala:155:29, :180:38, :181:39, :186:39]
wrbypass_idxs_1 <= update_idx; // @[tage.scala:60:43, :155:29]
if (~_T_31 | _GEN_13) begin // @[tage.scala:156:29, :180:{32,38}, :181:39, :182:34, :184:39]
end
else begin // @[tage.scala:156:29, :180:38, :181:39]
wrbypass_0_0 <= update_wdata_0_ctr; // @[tage.scala:120:26, :156:29]
wrbypass_0_1 <= update_wdata_1_ctr; // @[tage.scala:120:26, :156:29]
wrbypass_0_2 <= update_wdata_2_ctr; // @[tage.scala:120:26, :156:29]
wrbypass_0_3 <= update_wdata_3_ctr; // @[tage.scala:120:26, :156:29]
end
if (_T_31 & _GEN_13) begin // @[tage.scala:156:29, :180:{32,38}, :181:39, :182:34, :184:39]
wrbypass_1_0 <= update_wdata_0_ctr; // @[tage.scala:120:26, :156:29]
wrbypass_1_1 <= update_wdata_1_ctr; // @[tage.scala:120:26, :156:29]
wrbypass_1_2 <= update_wdata_2_ctr; // @[tage.scala:120:26, :156:29]
wrbypass_1_3 <= update_wdata_3_ctr; // @[tage.scala:120:26, :156:29]
end
always @(posedge)
tage_u_2 tage_u_2 ( // @[tage.scala:89:27]
.R0_addr (_u_rdata_WIRE), // @[tage.scala:140:12]
.R0_en (io_f1_req_valid_0), // @[tage.scala:24:7]
.R0_clk (clock),
.R0_data (_tage_u_2_R0_data),
.W0_addr (widx_1[6:0]), // @[tage.scala:144:19, :147:13]
.W0_en (update_u_wen), // @[tage.scala:136:30]
.W0_clk (clock),
.W0_data ({wdata_1_7, wdata_1_6, wdata_1_5, wdata_1_4, wdata_1_3, wdata_1_2, wdata_1_1, wdata_1_0}), // @[tage.scala:89:27, :145:20]
.W0_mask (wmask_1) // @[tage.scala:146:20]
); // @[tage.scala:89:27]
tage_table_2 tage_table_2 ( // @[tage.scala:90:27]
.R0_addr (_rdata_WIRE), // @[tage.scala:122:99]
.R0_en (io_f1_req_valid_0), // @[tage.scala:24:7]
.R0_clk (clock),
.R0_data (_tage_table_2_R0_data),
.W0_addr (widx), // @[tage.scala:129:19]
.W0_en (wen), // @[tage.scala:121:21]
.W0_clk (clock),
.W0_data ({wdata_3, wdata_2, wdata_1, wdata_0}), // @[tage.scala:90:27, :130:20]
.W0_mask (wmask) // @[tage.scala:131:20]
); // @[tage.scala:90:27]
assign io_f2_resp_0_valid = io_f2_resp_0_valid_0; // @[tage.scala:24:7]
assign io_f2_resp_0_bits_ctr = io_f2_resp_0_bits_ctr_0; // @[tage.scala:24:7]
assign io_f2_resp_0_bits_u = io_f2_resp_0_bits_u_0; // @[tage.scala:24:7]
assign io_f2_resp_1_valid = io_f2_resp_1_valid_0; // @[tage.scala:24:7]
assign io_f2_resp_1_bits_ctr = io_f2_resp_1_bits_ctr_0; // @[tage.scala:24:7]
assign io_f2_resp_1_bits_u = io_f2_resp_1_bits_u_0; // @[tage.scala:24:7]
assign io_f2_resp_2_valid = io_f2_resp_2_valid_0; // @[tage.scala:24:7]
assign io_f2_resp_2_bits_ctr = io_f2_resp_2_bits_ctr_0; // @[tage.scala:24:7]
assign io_f2_resp_2_bits_u = io_f2_resp_2_bits_u_0; // @[tage.scala:24:7]
assign io_f2_resp_3_valid = io_f2_resp_3_valid_0; // @[tage.scala:24:7]
assign io_f2_resp_3_bits_ctr = io_f2_resp_3_bits_ctr_0; // @[tage.scala:24:7]
assign io_f2_resp_3_bits_u = io_f2_resp_3_bits_u_0; // @[tage.scala:24:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File PE.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle {
val dataflow = UInt(1.W) // TODO make this an Enum
val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)?
val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats
}
class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module {
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(inputType)
val in_c = Input(cType)
val out_d = Output(dType)
})
io.out_d := io.in_c.mac(io.in_a, io.in_b)
}
// TODO update documentation
/**
* A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh.
* @param width Data width of operands
*/
class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int)
(implicit ev: Arithmetic[T]) extends Module { // Debugging variables
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(outputType)
val in_d = Input(outputType)
val out_a = Output(inputType)
val out_b = Output(outputType)
val out_c = Output(outputType)
val in_control = Input(new PEControl(accType))
val out_control = Output(new PEControl(accType))
val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W))
val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W))
val in_last = Input(Bool())
val out_last = Output(Bool())
val in_valid = Input(Bool())
val out_valid = Output(Bool())
val bad_dataflow = Output(Bool())
})
val cType = if (df == Dataflow.WS) inputType else accType
// When creating PEs that support multiple dataflows, the
// elaboration/synthesis tools often fail to consolidate and de-duplicate
// MAC units. To force mac circuitry to be re-used, we create a "mac_unit"
// module here which just performs a single MAC operation
val mac_unit = Module(new MacUnit(inputType,
if (df == Dataflow.WS) outputType else accType, outputType))
val a = io.in_a
val b = io.in_b
val d = io.in_d
val c1 = Reg(cType)
val c2 = Reg(cType)
val dataflow = io.in_control.dataflow
val prop = io.in_control.propagate
val shift = io.in_control.shift
val id = io.in_id
val last = io.in_last
val valid = io.in_valid
io.out_a := a
io.out_control.dataflow := dataflow
io.out_control.propagate := prop
io.out_control.shift := shift
io.out_id := id
io.out_last := last
io.out_valid := valid
mac_unit.io.in_a := a
val last_s = RegEnable(prop, valid)
val flip = last_s =/= prop
val shift_offset = Mux(flip, shift, 0.U)
// Which dataflow are we using?
val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W)
val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W)
// Is c1 being computed on, or propagated forward (in the output-stationary dataflow)?
val COMPUTE = 0.U(1.W)
val PROPAGATE = 1.U(1.W)
io.bad_dataflow := false.B
when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
c2 := mac_unit.io.out_d
c1 := d.withWidthOf(cType)
}.otherwise {
io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c1
c1 := mac_unit.io.out_d
c2 := d.withWidthOf(cType)
}
}.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := c1
mac_unit.io.in_b := c2.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c1 := d
}.otherwise {
io.out_c := c2
mac_unit.io.in_b := c1.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c2 := d
}
}.otherwise {
io.bad_dataflow := true.B
//assert(false.B, "unknown dataflow")
io.out_c := DontCare
io.out_b := DontCare
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
}
when (!valid) {
c1 := c1
c2 := c2
mac_unit.io.in_b := DontCare
mac_unit.io.in_c := DontCare
}
}
File Arithmetic.scala:
// A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own:
// implicit MyTypeArithmetic extends Arithmetic[MyType] { ... }
package gemmini
import chisel3._
import chisel3.util._
import hardfloat._
// Bundles that represent the raw bits of custom datatypes
case class Float(expWidth: Int, sigWidth: Int) extends Bundle {
val bits = UInt((expWidth + sigWidth).W)
val bias: Int = (1 << (expWidth-1)) - 1
}
case class DummySInt(w: Int) extends Bundle {
val bits = UInt(w.W)
def dontCare: DummySInt = {
val o = Wire(new DummySInt(w))
o.bits := 0.U
o
}
}
// The Arithmetic typeclass which implements various arithmetic operations on custom datatypes
abstract class Arithmetic[T <: Data] {
implicit def cast(t: T): ArithmeticOps[T]
}
abstract class ArithmeticOps[T <: Data](self: T) {
def *(t: T): T
def mac(m1: T, m2: T): T // Returns (m1 * m2 + self)
def +(t: T): T
def -(t: T): T
def >>(u: UInt): T // This is a rounding shift! Rounds away from 0
def >(t: T): Bool
def identity: T
def withWidthOf(t: T): T
def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates
def relu: T
def zero: T
def minimum: T
// Optional parameters, which only need to be defined if you want to enable various optimizations for transformers
def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None
def mult_with_reciprocal[U <: Data](reciprocal: U) = self
}
object Arithmetic {
implicit object UIntArithmetic extends Arithmetic[UInt] {
override implicit def cast(self: UInt) = new ArithmeticOps(self) {
override def *(t: UInt) = self * t
override def mac(m1: UInt, m2: UInt) = m1 * m2 + self
override def +(t: UInt) = self + t
override def -(t: UInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = point_five & (zeros | ones_digit)
(self >> u).asUInt + r
}
override def >(t: UInt): Bool = self > t
override def withWidthOf(t: UInt) = self.asTypeOf(t)
override def clippedToWidthOf(t: UInt) = {
val sat = ((1 << (t.getWidth-1))-1).U
Mux(self > sat, sat, self)(t.getWidth-1, 0)
}
override def relu: UInt = self
override def zero: UInt = 0.U
override def identity: UInt = 1.U
override def minimum: UInt = 0.U
}
}
implicit object SIntArithmetic extends Arithmetic[SInt] {
override implicit def cast(self: SInt) = new ArithmeticOps(self) {
override def *(t: SInt) = self * t
override def mac(m1: SInt, m2: SInt) = m1 * m2 + self
override def +(t: SInt) = self + t
override def -(t: SInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = (point_five & (zeros | ones_digit)).asBool
(self >> u).asSInt + Mux(r, 1.S, 0.S)
}
override def >(t: SInt): Bool = self > t
override def withWidthOf(t: SInt) = {
if (self.getWidth >= t.getWidth)
self(t.getWidth-1, 0).asSInt
else {
val sign_bits = t.getWidth - self.getWidth
val sign = self(self.getWidth-1)
Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t)
}
}
override def clippedToWidthOf(t: SInt): SInt = {
val maxsat = ((1 << (t.getWidth-1))-1).S
val minsat = (-(1 << (t.getWidth-1))).S
MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt
}
override def relu: SInt = Mux(self >= 0.S, self, 0.S)
override def zero: SInt = 0.S
override def identity: SInt = 1.S
override def minimum: SInt = (-(1 << (self.getWidth-1))).S
override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(denom_t.cloneType))
val output = Wire(Decoupled(self.cloneType))
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def sin_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def uin_to_float(x: UInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := x
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = sin_to_float(self)
val denom_rec = uin_to_float(input.bits)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := self_rec
divider.io.b := denom_rec
divider.io.roundingMode := consts.round_minMag
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := float_to_in(divider.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(self.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
// Instantiate the hardloat sqrt
val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0))
input.ready := sqrter.io.inReady
sqrter.io.inValid := input.valid
sqrter.io.sqrtOp := true.B
sqrter.io.a := self_rec
sqrter.io.b := DontCare
sqrter.io.roundingMode := consts.round_minMag
sqrter.io.detectTininess := consts.tininess_afterRounding
output.valid := sqrter.io.outValid_sqrt
output.bits := float_to_in(sqrter.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match {
case Float(expWidth, sigWidth) =>
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(u.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
val self_rec = in_to_float(self)
val one_rec = in_to_float(1.S)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := one_rec
divider.io.b := self_rec
divider.io.roundingMode := consts.round_near_even
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u)
assert(!output.valid || output.ready)
Some((input, output))
case _ => None
}
override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match {
case recip @ Float(expWidth, sigWidth) =>
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits)
// Instantiate the hardloat divider
val muladder = Module(new MulRecFN(expWidth, sigWidth))
muladder.io.roundingMode := consts.round_near_even
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := reciprocal_rec
float_to_in(muladder.io.out)
case _ => self
}
}
}
implicit object FloatArithmetic extends Arithmetic[Float] {
// TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array
override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) {
override def *(t: Float): Float = {
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := t_rec_resized
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def mac(m1: Float, m2: Float): Float = {
// Recode all operands
val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits)
val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize m1 to self's width
val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth))
m1_resizer.io.in := m1_rec
m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m1_resizer.io.detectTininess := consts.tininess_afterRounding
val m1_rec_resized = m1_resizer.io.out
// Resize m2 to self's width
val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth))
m2_resizer.io.in := m2_rec
m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m2_resizer.io.detectTininess := consts.tininess_afterRounding
val m2_rec_resized = m2_resizer.io.out
// Perform multiply-add
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := m1_rec_resized
muladder.io.b := m2_rec_resized
muladder.io.c := self_rec
// Convert result to standard format // TODO remove these intermediate recodings
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def +(t: Float): Float = {
require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Generate 1 as a float
val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := 1.U
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
val one_rec = in_to_rec_fn.io.out
// Resize t
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
// Perform addition
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := t_rec_resized
muladder.io.b := one_rec
muladder.io.c := self_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def -(t: Float): Float = {
val t_sgn = t.bits(t.getWidth-1)
val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t)
self + neg_t
}
override def >>(u: UInt): Float = {
// Recode self
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Get 2^(-u) as a recoded float
val shift_exp = Wire(UInt(self.expWidth.W))
shift_exp := self.bias.U - u
val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W))
val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn)
assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported")
// Multiply self and 2^(-u)
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := shift_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def >(t: Float): Bool = {
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize t to self's width
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth))
comparator.io.a := self_rec
comparator.io.b := t_rec_resized
comparator.io.signaling := false.B
comparator.io.gt
}
override def withWidthOf(t: Float): Float = {
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def clippedToWidthOf(t: Float): Float = {
// TODO check for overflow. Right now, we just assume that overflow doesn't happen
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def relu: Float = {
val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits)
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits)
result
}
override def zero: Float = 0.U.asTypeOf(self)
override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
}
}
implicit object DummySIntArithmetic extends Arithmetic[DummySInt] {
override implicit def cast(self: DummySInt) = new ArithmeticOps(self) {
override def *(t: DummySInt) = self.dontCare
override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare
override def +(t: DummySInt) = self.dontCare
override def -(t: DummySInt) = self.dontCare
override def >>(t: UInt) = self.dontCare
override def >(t: DummySInt): Bool = false.B
override def identity = self.dontCare
override def withWidthOf(t: DummySInt) = self.dontCare
override def clippedToWidthOf(t: DummySInt) = self.dontCare
override def relu = self.dontCare
override def zero = self.dontCare
override def minimum: DummySInt = self.dontCare
}
}
}
| module MacUnit_114( // @[PE.scala:14:7]
input clock, // @[PE.scala:14:7]
input reset, // @[PE.scala:14:7]
input [7:0] io_in_a, // @[PE.scala:16:14]
input [7:0] io_in_b, // @[PE.scala:16:14]
input [31:0] io_in_c, // @[PE.scala:16:14]
output [19:0] io_out_d // @[PE.scala:16:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7]
wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7]
wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7]
wire [19:0] io_out_d_0; // @[PE.scala:14:7]
wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7]
wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7]
wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54]
wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54]
assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12]
assign io_out_d = io_out_d_0; // @[PE.scala:14:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Bundles.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import freechips.rocketchip.util._
import scala.collection.immutable.ListMap
import chisel3.util.Decoupled
import chisel3.util.DecoupledIO
import chisel3.reflect.DataMirror
abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle
// common combos in lazy policy:
// Put + Acquire
// Release + AccessAck
object TLMessages
{
// A B C D E
def PutFullData = 0.U // . . => AccessAck
def PutPartialData = 1.U // . . => AccessAck
def ArithmeticData = 2.U // . . => AccessAckData
def LogicalData = 3.U // . . => AccessAckData
def Get = 4.U // . . => AccessAckData
def Hint = 5.U // . . => HintAck
def AcquireBlock = 6.U // . => Grant[Data]
def AcquirePerm = 7.U // . => Grant[Data]
def Probe = 6.U // . => ProbeAck[Data]
def AccessAck = 0.U // . .
def AccessAckData = 1.U // . .
def HintAck = 2.U // . .
def ProbeAck = 4.U // .
def ProbeAckData = 5.U // .
def Release = 6.U // . => ReleaseAck
def ReleaseData = 7.U // . => ReleaseAck
def Grant = 4.U // . => GrantAck
def GrantData = 5.U // . => GrantAck
def ReleaseAck = 6.U // .
def GrantAck = 0.U // .
def isA(x: UInt) = x <= AcquirePerm
def isB(x: UInt) = x <= Probe
def isC(x: UInt) = x <= ReleaseData
def isD(x: UInt) = x <= ReleaseAck
def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant)
def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck)
def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("AcquireBlock",TLPermissions.PermMsgGrow),
("AcquirePerm",TLPermissions.PermMsgGrow))
def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("Probe",TLPermissions.PermMsgCap))
def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("ProbeAck",TLPermissions.PermMsgReport),
("ProbeAckData",TLPermissions.PermMsgReport),
("Release",TLPermissions.PermMsgReport),
("ReleaseData",TLPermissions.PermMsgReport))
def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("Grant",TLPermissions.PermMsgCap),
("GrantData",TLPermissions.PermMsgCap),
("ReleaseAck",TLPermissions.PermMsgReserved))
}
/**
* The three primary TileLink permissions are:
* (T)runk: the agent is (or is on inwards path to) the global point of serialization.
* (B)ranch: the agent is on an outwards path to
* (N)one:
* These permissions are permuted by transfer operations in various ways.
* Operations can cap permissions, request for them to be grown or shrunk,
* or for a report on their current status.
*/
object TLPermissions
{
val aWidth = 2
val bdWidth = 2
val cWidth = 3
// Cap types (Grant = new permissions, Probe = permisions <= target)
def toT = 0.U(bdWidth.W)
def toB = 1.U(bdWidth.W)
def toN = 2.U(bdWidth.W)
def isCap(x: UInt) = x <= toN
// Grow types (Acquire = permissions >= target)
def NtoB = 0.U(aWidth.W)
def NtoT = 1.U(aWidth.W)
def BtoT = 2.U(aWidth.W)
def isGrow(x: UInt) = x <= BtoT
// Shrink types (ProbeAck, Release)
def TtoB = 0.U(cWidth.W)
def TtoN = 1.U(cWidth.W)
def BtoN = 2.U(cWidth.W)
def isShrink(x: UInt) = x <= BtoN
// Report types (ProbeAck, Release)
def TtoT = 3.U(cWidth.W)
def BtoB = 4.U(cWidth.W)
def NtoN = 5.U(cWidth.W)
def isReport(x: UInt) = x <= NtoN
def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT")
def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN")
def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN")
def PermMsgReserved:Seq[String] = Seq("Reserved")
}
object TLAtomics
{
val width = 3
// Arithmetic types
def MIN = 0.U(width.W)
def MAX = 1.U(width.W)
def MINU = 2.U(width.W)
def MAXU = 3.U(width.W)
def ADD = 4.U(width.W)
def isArithmetic(x: UInt) = x <= ADD
// Logical types
def XOR = 0.U(width.W)
def OR = 1.U(width.W)
def AND = 2.U(width.W)
def SWAP = 3.U(width.W)
def isLogical(x: UInt) = x <= SWAP
def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD")
def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP")
}
object TLHints
{
val width = 1
def PREFETCH_READ = 0.U(width.W)
def PREFETCH_WRITE = 1.U(width.W)
def isHints(x: UInt) = x <= PREFETCH_WRITE
def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite")
}
sealed trait TLChannel extends TLBundleBase {
val channelName: String
}
sealed trait TLDataChannel extends TLChannel
sealed trait TLAddrChannel extends TLDataChannel
final class TLBundleA(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleA_${params.shortName}"
val channelName = "'A' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleB(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleB_${params.shortName}"
val channelName = "'B' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val address = UInt(params.addressBits.W) // from
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleC(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleC_${params.shortName}"
val channelName = "'C' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.cWidth.W) // shrink or report perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleD(params: TLBundleParameters)
extends TLBundleBase(params) with TLDataChannel
{
override def typeName = s"TLBundleD_${params.shortName}"
val channelName = "'D' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val sink = UInt(params.sinkBits.W) // from
val denied = Bool() // implies corrupt iff *Data
val user = BundleMap(params.responseFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleE(params: TLBundleParameters)
extends TLBundleBase(params) with TLChannel
{
override def typeName = s"TLBundleE_${params.shortName}"
val channelName = "'E' channel"
val sink = UInt(params.sinkBits.W) // to
}
class TLBundle(val params: TLBundleParameters) extends Record
{
// Emulate a Bundle with elements abcde or ad depending on params.hasBCE
private val optA = Some (Decoupled(new TLBundleA(params)))
private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params))))
private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params)))
private val optD = Some (Flipped(Decoupled(new TLBundleD(params))))
private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params)))
def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params)))))
def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params)))))
def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params)))))
def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params)))))
def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params)))))
val elements =
if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a)
else ListMap("d" -> d, "a" -> a)
def tieoff(): Unit = {
DataMirror.specifiedDirectionOf(a.ready) match {
case SpecifiedDirection.Input =>
a.ready := false.B
c.ready := false.B
e.ready := false.B
b.valid := false.B
d.valid := false.B
case SpecifiedDirection.Output =>
a.valid := false.B
c.valid := false.B
e.valid := false.B
b.ready := false.B
d.ready := false.B
case _ =>
}
}
}
object TLBundle
{
def apply(params: TLBundleParameters) = new TLBundle(params)
}
class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle
class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params)
{
val a = new AsyncBundle(new TLBundleA(params.base), params.async)
val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async))
val c = new AsyncBundle(new TLBundleC(params.base), params.async)
val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async))
val e = new AsyncBundle(new TLBundleE(params.base), params.async)
}
class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = RationalIO(new TLBundleA(params))
val b = Flipped(RationalIO(new TLBundleB(params)))
val c = RationalIO(new TLBundleC(params))
val d = Flipped(RationalIO(new TLBundleD(params)))
val e = RationalIO(new TLBundleE(params))
}
class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = CreditedIO(new TLBundleA(params))
val b = Flipped(CreditedIO(new TLBundleB(params)))
val c = CreditedIO(new TLBundleC(params))
val d = Flipped(CreditedIO(new TLBundleD(params)))
val e = CreditedIO(new TLBundleE(params))
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor_42( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [16:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [10:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [10:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [16:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [10:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10]
wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire a_first_count = 1'h0; // @[Edges.scala:234:25]
wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count = 1'h0; // @[Edges.scala:234:25]
wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25]
wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25]
wire d_release_ack = 1'h0; // @[Monitor.scala:673:46]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27]
wire c_first_count = 1'h0; // @[Edges.scala:234:25]
wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21]
wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire d_release_ack_1 = 1'h0; // @[Monitor.scala:783:46]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67]
wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last = 1'h1; // @[Edges.scala:232:33]
wire d_first_beats1_opdata = 1'h1; // @[Edges.scala:106:36]
wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last = 1'h1; // @[Edges.scala:232:33]
wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire d_first_beats1_opdata_1 = 1'h1; // @[Edges.scala:106:36]
wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire d_first_beats1_opdata_2 = 1'h1; // @[Edges.scala:106:36]
wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33]
wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28]
wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7]
wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [2:0] io_in_d_bits_opcode = 3'h1; // @[Monitor.scala:36:7]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59]
wire [4159:0] _inflight_opcodes_T_4 = 4160'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; // @[Monitor.scala:815:62]
wire [4159:0] _inflight_sizes_T_4 = 4160'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; // @[Monitor.scala:816:58]
wire [1039:0] _inflight_T_4 = 1040'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; // @[Monitor.scala:814:46]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [16:0] _c_first_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74]
wire [16:0] _c_first_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61]
wire [16:0] _c_first_WIRE_2_bits_address = 17'h0; // @[Bundles.scala:265:74]
wire [16:0] _c_first_WIRE_3_bits_address = 17'h0; // @[Bundles.scala:265:61]
wire [16:0] _c_set_wo_ready_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74]
wire [16:0] _c_set_wo_ready_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61]
wire [16:0] _c_set_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74]
wire [16:0] _c_set_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61]
wire [16:0] _c_opcodes_set_interm_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74]
wire [16:0] _c_opcodes_set_interm_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61]
wire [16:0] _c_sizes_set_interm_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74]
wire [16:0] _c_sizes_set_interm_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61]
wire [16:0] _c_opcodes_set_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74]
wire [16:0] _c_opcodes_set_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61]
wire [16:0] _c_sizes_set_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74]
wire [16:0] _c_sizes_set_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61]
wire [16:0] _c_probe_ack_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74]
wire [16:0] _c_probe_ack_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61]
wire [16:0] _c_probe_ack_WIRE_2_bits_address = 17'h0; // @[Bundles.scala:265:74]
wire [16:0] _c_probe_ack_WIRE_3_bits_address = 17'h0; // @[Bundles.scala:265:61]
wire [16:0] _same_cycle_resp_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74]
wire [16:0] _same_cycle_resp_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61]
wire [16:0] _same_cycle_resp_WIRE_2_bits_address = 17'h0; // @[Bundles.scala:265:74]
wire [16:0] _same_cycle_resp_WIRE_3_bits_address = 17'h0; // @[Bundles.scala:265:61]
wire [16:0] _same_cycle_resp_WIRE_4_bits_address = 17'h0; // @[Bundles.scala:265:74]
wire [16:0] _same_cycle_resp_WIRE_5_bits_address = 17'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_first_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_first_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_first_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_first_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_set_wo_ready_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_set_wo_ready_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_opcodes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_opcodes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_sizes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_sizes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_opcodes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_opcodes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_sizes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_sizes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_probe_ack_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_probe_ack_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_probe_ack_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_probe_ack_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _same_cycle_resp_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _same_cycle_resp_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _same_cycle_resp_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _same_cycle_resp_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _same_cycle_resp_WIRE_4_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _same_cycle_resp_WIRE_5_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46]
wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [4159:0] c_opcodes_set = 4160'h0; // @[Monitor.scala:740:34]
wire [4159:0] c_sizes_set = 4160'h0; // @[Monitor.scala:741:34]
wire [4159:0] d_opcodes_clr_1 = 4160'h0; // @[Monitor.scala:776:34]
wire [4159:0] d_sizes_clr_1 = 4160'h0; // @[Monitor.scala:777:34]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [1039:0] c_set = 1040'h0; // @[Monitor.scala:738:34]
wire [1039:0] c_set_wo_ready = 1040'h0; // @[Monitor.scala:739:34]
wire [1039:0] d_clr_1 = 1040'h0; // @[Monitor.scala:774:34]
wire [1039:0] d_clr_wo_ready_1 = 1040'h0; // @[Monitor.scala:775:34]
wire [16385:0] _c_sizes_set_T_1 = 16386'h0; // @[Monitor.scala:768:52]
wire [13:0] _c_opcodes_set_T = 14'h0; // @[Monitor.scala:767:79]
wire [13:0] _c_sizes_set_T = 14'h0; // @[Monitor.scala:768:77]
wire [16386:0] _c_opcodes_set_T_1 = 16387'h0; // @[Monitor.scala:767:54]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [2047:0] _c_set_wo_ready_T = 2048'h1; // @[OneHot.scala:58:35]
wire [2047:0] _c_set_T = 2048'h1; // @[OneHot.scala:58:35]
wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76]
wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [10:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_4 = source_ok_uncommonBits < 11'h410; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31]
wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [16:0] _is_aligned_T = {14'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 17'h0; // @[Edges.scala:21:{16,24}]
wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [10:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}]
wire [10:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_10 = source_ok_uncommonBits_1 < 11'h410; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31]
wire _T_659 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_659; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_659; // @[Decoupled.scala:51:35]
wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
reg a_first_counter; // @[Edges.scala:229:27]
wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28]
wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25]
wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [1:0] size; // @[Monitor.scala:389:22]
reg [10:0] source; // @[Monitor.scala:390:22]
reg [16:0] address; // @[Monitor.scala:391:22]
wire _T_727 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_727; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_727; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_727; // @[Decoupled.scala:51:35]
wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35]
wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
reg d_first_counter; // @[Edges.scala:229:27]
wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28]
wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [1:0] size_1; // @[Monitor.scala:540:22]
reg [10:0] source_1; // @[Monitor.scala:541:22]
reg [1039:0] inflight; // @[Monitor.scala:614:27]
reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33]
wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
reg a_first_counter_1; // @[Edges.scala:229:27]
wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28]
wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25]
wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
reg d_first_counter_1; // @[Edges.scala:229:27]
wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28]
wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire [1039:0] a_set; // @[Monitor.scala:626:34]
wire [1039:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [4159:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [4159:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [13:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [13:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [13:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [13:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [13:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [13:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [13:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [13:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [13:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [4159:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [4159:0] _a_opcode_lookup_T_6 = {4156'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [4159:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [4159:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [4159:0] _a_size_lookup_T_6 = {4156'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [4159:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[4159:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [2047:0] _GEN_2 = 2048'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [2047:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [2047:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire _T_592 = _T_659 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_592 ? _a_set_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_592 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_592 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [13:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [13:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [13:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [16386:0] _a_opcodes_set_T_1 = {16383'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_592 ? _a_opcodes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [16385:0] _a_sizes_set_T_1 = {16383'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_592 ? _a_sizes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [1039:0] d_clr; // @[Monitor.scala:664:34]
wire [1039:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [4159:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [4159:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _T_638 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [2047:0] _GEN_4 = 2048'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [2047:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35]
wire [2047:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_4; // @[OneHot.scala:58:35]
wire [2047:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_4; // @[OneHot.scala:58:35]
wire [2047:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_4; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_638 ? _d_clr_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire _T_605 = _T_727 & d_first_1; // @[Decoupled.scala:51:35]
assign d_clr = _T_605 ? _d_clr_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire [16398:0] _d_opcodes_clr_T_5 = 16399'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_605 ? _d_opcodes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:668:33, :678:{25,89}, :680:{21,76}]
wire [16398:0] _d_sizes_clr_T_5 = 16399'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_605 ? _d_sizes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:670:31, :678:{25,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [1039:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [1039:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [1039:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [4159:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [4159:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [4159:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [4159:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [4159:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [4159:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [1039:0] inflight_1; // @[Monitor.scala:726:35]
wire [1039:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [4159:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [4159:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [4159:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
reg d_first_counter_2; // @[Edges.scala:229:27]
wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28]
wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [4159:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [4159:0] _c_opcode_lookup_T_6 = {4156'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [4159:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [4159:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [4159:0] _c_size_lookup_T_6 = {4156'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [4159:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[4159:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [16398:0] _d_opcodes_clr_T_11 = 16399'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
wire [16398:0] _d_sizes_clr_T_11 = 16399'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 11'h0; // @[Monitor.scala:36:7, :795:113]
wire [1039:0] _inflight_T_5 = _inflight_T_3; // @[Monitor.scala:814:{35,44}]
wire [4159:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3; // @[Monitor.scala:815:{43,60}]
wire [4159:0] _inflight_sizes_T_5 = _inflight_sizes_T_3; // @[Monitor.scala:816:{41,56}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to the following Chisel files.
File RoundAnyRawFNToRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util.Fill
import consts._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class
RoundAnyRawFNToRecFN(
inExpWidth: Int,
inSigWidth: Int,
outExpWidth: Int,
outSigWidth: Int,
options: Int
)
extends RawModule
{
override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}"
val io = IO(new Bundle {
val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'
val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'
val in = Input(new RawFloat(inExpWidth, inSigWidth))
// (allowed exponent range has limits)
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((outExpWidth + outSigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0)
val effectiveInSigWidth =
if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1
val neverUnderflows =
((options &
(flRoundOpt_neverUnderflows | flRoundOpt_subnormsAlwaysExact)
) != 0) ||
(inExpWidth < outExpWidth)
val neverOverflows =
((options & flRoundOpt_neverOverflows) != 0) ||
(inExpWidth < outExpWidth)
val outNaNExp = BigInt(7)<<(outExpWidth - 2)
val outInfExp = BigInt(6)<<(outExpWidth - 2)
val outMaxFiniteExp = outInfExp - 1
val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2
val outMinNonzeroExp = outMinNormExp - outSigWidth + 1
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundingMode_near_even = (io.roundingMode === round_near_even)
val roundingMode_minMag = (io.roundingMode === round_minMag)
val roundingMode_min = (io.roundingMode === round_min)
val roundingMode_max = (io.roundingMode === round_max)
val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag)
val roundingMode_odd = (io.roundingMode === round_odd)
val roundMagUp =
(roundingMode_min && io.in.sign) || (roundingMode_max && ! io.in.sign)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sAdjustedExp =
if (inExpWidth < outExpWidth)
(io.in.sExp +&
((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S
)(outExpWidth, 0).zext
else if (inExpWidth == outExpWidth)
io.in.sExp
else
io.in.sExp +&
((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S
val adjustedSig =
if (inSigWidth <= outSigWidth + 2)
io.in.sig<<(outSigWidth - inSigWidth + 2)
else
(io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ##
io.in.sig(inSigWidth - outSigWidth - 2, 0).orR
)
val doShiftSigDown1 =
if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2)
val common_expOut = Wire(UInt((outExpWidth + 1).W))
val common_fractOut = Wire(UInt((outSigWidth - 1).W))
val common_overflow = Wire(Bool())
val common_totalUnderflow = Wire(Bool())
val common_underflow = Wire(Bool())
val common_inexact = Wire(Bool())
if (
neverOverflows && neverUnderflows
&& (effectiveInSigWidth <= outSigWidth)
) {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1
common_fractOut :=
Mux(doShiftSigDown1,
adjustedSig(outSigWidth + 1, 3),
adjustedSig(outSigWidth, 2)
)
common_overflow := false.B
common_totalUnderflow := false.B
common_underflow := false.B
common_inexact := false.B
} else {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
val roundMask =
if (neverUnderflows)
0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W)
else
(lowMask(
sAdjustedExp(outExpWidth, 0),
outMinNormExp - outSigWidth - 1,
outMinNormExp
) | doShiftSigDown1) ##
3.U(2.W)
val shiftedRoundMask = 0.U(1.W) ## roundMask>>1
val roundPosMask = ~shiftedRoundMask & roundMask
val roundPosBit = (adjustedSig & roundPosMask).orR
val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR
val anyRound = roundPosBit || anyRoundExtra
val roundIncr =
((roundingMode_near_even || roundingMode_near_maxMag) &&
roundPosBit) ||
(roundMagUp && anyRound)
val roundedSig: Bits =
Mux(roundIncr,
(((adjustedSig | roundMask)>>2) +& 1.U) &
~Mux(roundingMode_near_even && roundPosBit &&
! anyRoundExtra,
roundMask>>1,
0.U((outSigWidth + 2).W)
),
(adjustedSig & ~roundMask)>>2 |
Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U)
)
//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING
//*** M.S. BIT OF SUBNORMAL SIG?
val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext
common_expOut := sRoundedExp(outExpWidth, 0)
common_fractOut :=
Mux(doShiftSigDown1,
roundedSig(outSigWidth - 1, 1),
roundedSig(outSigWidth - 2, 0)
)
common_overflow :=
(if (neverOverflows) false.B else
//*** REWRITE BASED ON BEFORE-ROUNDING EXPONENT?:
(sRoundedExp>>(outExpWidth - 1) >= 3.S))
common_totalUnderflow :=
(if (neverUnderflows) false.B else
//*** WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?:
(sRoundedExp < outMinNonzeroExp.S))
val unboundedRange_roundPosBit =
Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1))
val unboundedRange_anyRound =
(doShiftSigDown1 && adjustedSig(2)) || adjustedSig(1, 0).orR
val unboundedRange_roundIncr =
((roundingMode_near_even || roundingMode_near_maxMag) &&
unboundedRange_roundPosBit) ||
(roundMagUp && unboundedRange_anyRound)
val roundCarry =
Mux(doShiftSigDown1,
roundedSig(outSigWidth + 1),
roundedSig(outSigWidth)
)
common_underflow :=
(if (neverUnderflows) false.B else
common_totalUnderflow ||
//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING
//*** M.S. BIT OF SUBNORMAL SIG?
(anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) &&
Mux(doShiftSigDown1, roundMask(3), roundMask(2)) &&
! ((io.detectTininess === tininess_afterRounding) &&
! Mux(doShiftSigDown1,
roundMask(4),
roundMask(3)
) &&
roundCarry && roundPosBit &&
unboundedRange_roundIncr)))
common_inexact := common_totalUnderflow || anyRound
}
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val isNaNOut = io.invalidExc || io.in.isNaN
val notNaN_isSpecialInfOut = io.infiniteExc || io.in.isInf
val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero
val overflow = commonCase && common_overflow
val underflow = commonCase && common_underflow
val inexact = overflow || (commonCase && common_inexact)
val overflow_roundMagUp =
roundingMode_near_even || roundingMode_near_maxMag || roundMagUp
val pegMinNonzeroMagOut =
commonCase && common_totalUnderflow && (roundMagUp || roundingMode_odd)
val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp
val notNaN_isInfOut =
notNaN_isSpecialInfOut || (overflow && overflow_roundMagUp)
val signOut = Mux(isNaNOut, false.B, io.in.sign)
val expOut =
(common_expOut &
~Mux(io.in.isZero || common_totalUnderflow,
(BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W),
0.U
) &
~Mux(pegMinNonzeroMagOut,
~outMinNonzeroExp.U((outExpWidth + 1).W),
0.U
) &
~Mux(pegMaxFiniteMagOut,
(BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W),
0.U
) &
~Mux(notNaN_isInfOut,
(BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W),
0.U
)) |
Mux(pegMinNonzeroMagOut,
outMinNonzeroExp.U((outExpWidth + 1).W),
0.U
) |
Mux(pegMaxFiniteMagOut,
outMaxFiniteExp.U((outExpWidth + 1).W),
0.U
) |
Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) |
Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U)
val fractOut =
Mux(isNaNOut || io.in.isZero || common_totalUnderflow,
Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U),
common_fractOut
) |
Fill(outSigWidth - 1, pegMaxFiniteMagOut)
io.out := signOut ## expOut ## fractOut
io.exceptionFlags :=
io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class
RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int)
extends RawModule
{
override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'
val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'
val in = Input(new RawFloat(expWidth, sigWidth + 2))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
val roundAnyRawFNToRecFN =
Module(
new RoundAnyRawFNToRecFN(
expWidth, sigWidth + 2, expWidth, sigWidth, options))
roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc
roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc
roundAnyRawFNToRecFN.io.in := io.in
roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode
roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundAnyRawFNToRecFN.io.out
io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags
}
| module RoundAnyRawFNToRecFN_ie4_is8_oe8_os24( // @[RoundAnyRawFNToRecFN.scala:48:5]
input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16]
input [5:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16]
input [8:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16]
output [32:0] io_out // @[RoundAnyRawFNToRecFN.scala:58:16]
);
wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [5:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [8:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19]
wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14, :265:14]
wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14, :265:14]
wire [8:0] _expOut_T_12 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14, :265:14]
wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:257:18]
wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:261:18]
wire [8:0] _expOut_T_11 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:265:18]
wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:269:16]
wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:273:16]
wire [8:0] _expOut_T_18 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:277:16]
wire [8:0] _expOut_T_20 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:278:16]
wire [22:0] _fractOut_T_2 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:281:16, :284:13]
wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:281:16, :284:13]
wire [1:0] _io_exceptionFlags_T = 2'h0; // @[RoundAnyRawFNToRecFN.scala:288:23]
wire [3:0] _io_exceptionFlags_T_2 = 4'h0; // @[RoundAnyRawFNToRecFN.scala:288:53]
wire [4:0] io_exceptionFlags = 5'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:66]
wire [4:0] _io_exceptionFlags_T_3 = 5'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:66]
wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :237:{22,33,36}, :243:{32,60}]
wire roundingMode_near_even = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :237:{22,33,36}, :243:{32,60}]
wire _commonCase_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :237:{22,33,36}, :243:{32,60}]
wire _commonCase_T_1 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :237:{22,33,36}, :243:{32,60}]
wire _commonCase_T_2 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :237:{22,33,36}, :243:{32,60}]
wire _overflow_roundMagUp_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :237:{22,33,36}, :243:{32,60}]
wire overflow_roundMagUp = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :237:{22,33,36}, :243:{32,60}]
wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:41]
wire [2:0] _io_exceptionFlags_T_1 = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:41]
wire io_invalidExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isNaN = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isInf = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire roundingMode_minMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:91:53]
wire roundingMode_min = 1'h0; // @[RoundAnyRawFNToRecFN.scala:92:53]
wire roundingMode_max = 1'h0; // @[RoundAnyRawFNToRecFN.scala:93:53]
wire roundingMode_near_maxMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:94:53]
wire roundingMode_odd = 1'h0; // @[RoundAnyRawFNToRecFN.scala:95:53]
wire _roundMagUp_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:27]
wire _roundMagUp_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:63]
wire roundMagUp = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:42]
wire common_overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:124:37]
wire common_totalUnderflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:125:37]
wire common_underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:126:37]
wire common_inexact = 1'h0; // @[RoundAnyRawFNToRecFN.scala:127:37]
wire isNaNOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:235:34]
wire notNaN_isSpecialInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:236:49]
wire overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:238:32]
wire underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:239:32]
wire _inexact_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:240:43]
wire inexact = 1'h0; // @[RoundAnyRawFNToRecFN.scala:240:28]
wire _pegMinNonzeroMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:20]
wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:60]
wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45]
wire _pegMaxFiniteMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:42]
wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39]
wire _notNaN_isInfOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:45]
wire notNaN_isInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:32]
wire _expOut_T = io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :253:32]
wire _fractOut_T = io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :280:22]
wire signOut = io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :250:22]
wire [32:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33]
wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66]
wire [9:0] _sAdjustedExp_T = {{4{io_in_sExp_0[5]}}, io_in_sExp_0} + 10'hF0; // @[RoundAnyRawFNToRecFN.scala:48:5, :104:25]
wire [8:0] _sAdjustedExp_T_1 = _sAdjustedExp_T[8:0]; // @[RoundAnyRawFNToRecFN.scala:104:25, :106:14]
wire [9:0] sAdjustedExp = {1'h0, _sAdjustedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:106:{14,31}]
wire [26:0] adjustedSig = {io_in_sig_0, 18'h0}; // @[RoundAnyRawFNToRecFN.scala:48:5, :114:22]
wire [8:0] _common_expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:136:55]
wire [8:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31]
wire [22:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:138:16]
wire [22:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31]
wire [8:0] _common_expOut_T = sAdjustedExp[8:0]; // @[RoundAnyRawFNToRecFN.scala:106:31, :136:38]
wire [9:0] _common_expOut_T_1 = {1'h0, _common_expOut_T}; // @[RoundAnyRawFNToRecFN.scala:136:{38,55}]
assign _common_expOut_T_2 = _common_expOut_T_1[8:0]; // @[RoundAnyRawFNToRecFN.scala:136:55]
assign common_expOut = _common_expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :136:55]
wire [22:0] _common_fractOut_T = adjustedSig[25:3]; // @[RoundAnyRawFNToRecFN.scala:114:22, :139:28]
wire [22:0] _common_fractOut_T_1 = adjustedSig[24:2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :140:28]
assign _common_fractOut_T_2 = _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:138:16, :140:28]
assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16]
wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64]
wire commonCase = _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{61,64}]
wire [8:0] _expOut_T_1 = _expOut_T ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}]
wire [8:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}]
wire [8:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14]
wire [8:0] _expOut_T_7 = _expOut_T_3; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17]
wire [8:0] _expOut_T_10 = _expOut_T_7; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17]
wire [8:0] _expOut_T_13 = _expOut_T_10; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17]
wire [8:0] _expOut_T_15 = _expOut_T_13; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18]
wire [8:0] _expOut_T_17 = _expOut_T_15; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15]
wire [8:0] _expOut_T_19 = _expOut_T_17; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15]
wire [8:0] expOut = _expOut_T_19; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73]
wire _fractOut_T_1 = _fractOut_T; // @[RoundAnyRawFNToRecFN.scala:280:{22,38}]
wire [22:0] _fractOut_T_3 = _fractOut_T_1 ? 23'h0 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16, :284:13]
wire [22:0] fractOut = _fractOut_T_3; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11]
wire [9:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23]
assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}]
assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33]
assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Crossing.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.interrupts
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.util.{SynchronizerShiftReg, AsyncResetReg}
@deprecated("IntXing does not ensure interrupt source is glitch free. Use IntSyncSource and IntSyncSink", "rocket-chip 1.2")
class IntXing(sync: Int = 3)(implicit p: Parameters) extends LazyModule
{
val intnode = IntAdapterNode()
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
(intnode.in zip intnode.out) foreach { case ((in, _), (out, _)) =>
out := SynchronizerShiftReg(in, sync)
}
}
}
object IntSyncCrossingSource
{
def apply(alreadyRegistered: Boolean = false)(implicit p: Parameters) =
{
val intsource = LazyModule(new IntSyncCrossingSource(alreadyRegistered))
intsource.node
}
}
class IntSyncCrossingSource(alreadyRegistered: Boolean = false)(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSourceNode(alreadyRegistered)
lazy val module = if (alreadyRegistered) (new ImplRegistered) else (new Impl)
class Impl extends LazyModuleImp(this) {
def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0)
override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out.sync := AsyncResetReg(Cat(in.reverse)).asBools
}
}
class ImplRegistered extends LazyRawModuleImp(this) {
def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0)
override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}_Registered"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out.sync := in
}
}
}
object IntSyncCrossingSink
{
@deprecated("IntSyncCrossingSink which used the `sync` parameter to determine crossing type is deprecated. Use IntSyncAsyncCrossingSink, IntSyncRationalCrossingSink, or IntSyncSyncCrossingSink instead for > 1, 1, and 0 sync values respectively", "rocket-chip 1.2")
def apply(sync: Int = 3)(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync))
intsink.node
}
}
class IntSyncAsyncCrossingSink(sync: Int = 3)(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSinkNode(sync)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
override def desiredName = s"IntSyncAsyncCrossingSink_n${node.out.size}x${node.out.head._1.size}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out := SynchronizerShiftReg(in.sync, sync)
}
}
}
object IntSyncAsyncCrossingSink
{
def apply(sync: Int = 3)(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync))
intsink.node
}
}
class IntSyncSyncCrossingSink()(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSinkNode(0)
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
def outSize = node.out.headOption.map(_._1.size).getOrElse(0)
override def desiredName = s"IntSyncSyncCrossingSink_n${node.out.size}x${outSize}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out := in.sync
}
}
}
object IntSyncSyncCrossingSink
{
def apply()(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncSyncCrossingSink())
intsink.node
}
}
class IntSyncRationalCrossingSink()(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSinkNode(1)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
def outSize = node.out.headOption.map(_._1.size).getOrElse(0)
override def desiredName = s"IntSyncRationalCrossingSink_n${node.out.size}x${outSize}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out := RegNext(in.sync)
}
}
}
object IntSyncRationalCrossingSink
{
def apply()(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncRationalCrossingSink())
intsink.node
}
}
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
| module IntSyncSyncCrossingSink_n1x1_28( // @[Crossing.scala:96:9]
input auto_in_sync_0, // @[LazyModuleImp.scala:107:25]
output auto_out_0 // @[LazyModuleImp.scala:107:25]
);
wire auto_in_sync_0_0 = auto_in_sync_0; // @[Crossing.scala:96:9]
wire childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire nodeIn_sync_0 = auto_in_sync_0_0; // @[Crossing.scala:96:9]
wire nodeOut_0; // @[MixedNode.scala:542:17]
wire auto_out_0_0; // @[Crossing.scala:96:9]
assign nodeOut_0 = nodeIn_sync_0; // @[MixedNode.scala:542:17, :551:17]
assign auto_out_0_0 = nodeOut_0; // @[Crossing.scala:96:9]
assign auto_out_0 = auto_out_0_0; // @[Crossing.scala:96:9]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File MSHR.scala:
/*
* Copyright 2019 SiFive, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You should have received a copy of LICENSE.Apache2 along with
* this software. If not, you may obtain a copy at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package sifive.blocks.inclusivecache
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import freechips.rocketchip.tilelink._
import TLPermissions._
import TLMessages._
import MetaData._
import chisel3.PrintableHelper
import chisel3.experimental.dataview._
class ScheduleRequest(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params)
{
val a = Valid(new SourceARequest(params))
val b = Valid(new SourceBRequest(params))
val c = Valid(new SourceCRequest(params))
val d = Valid(new SourceDRequest(params))
val e = Valid(new SourceERequest(params))
val x = Valid(new SourceXRequest(params))
val dir = Valid(new DirectoryWrite(params))
val reload = Bool() // get next request via allocate (if any)
}
class MSHRStatus(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params)
{
val set = UInt(params.setBits.W)
val tag = UInt(params.tagBits.W)
val way = UInt(params.wayBits.W)
val blockB = Bool()
val nestB = Bool()
val blockC = Bool()
val nestC = Bool()
}
class NestedWriteback(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params)
{
val set = UInt(params.setBits.W)
val tag = UInt(params.tagBits.W)
val b_toN = Bool() // nested Probes may unhit us
val b_toB = Bool() // nested Probes may demote us
val b_clr_dirty = Bool() // nested Probes clear dirty
val c_set_dirty = Bool() // nested Releases MAY set dirty
}
sealed trait CacheState
{
val code = CacheState.index.U
CacheState.index = CacheState.index + 1
}
object CacheState
{
var index = 0
}
case object S_INVALID extends CacheState
case object S_BRANCH extends CacheState
case object S_BRANCH_C extends CacheState
case object S_TIP extends CacheState
case object S_TIP_C extends CacheState
case object S_TIP_CD extends CacheState
case object S_TIP_D extends CacheState
case object S_TRUNK_C extends CacheState
case object S_TRUNK_CD extends CacheState
class MSHR(params: InclusiveCacheParameters) extends Module
{
val io = IO(new Bundle {
val allocate = Flipped(Valid(new AllocateRequest(params))) // refills MSHR for next cycle
val directory = Flipped(Valid(new DirectoryResult(params))) // triggers schedule setup
val status = Valid(new MSHRStatus(params))
val schedule = Decoupled(new ScheduleRequest(params))
val sinkc = Flipped(Valid(new SinkCResponse(params)))
val sinkd = Flipped(Valid(new SinkDResponse(params)))
val sinke = Flipped(Valid(new SinkEResponse(params)))
val nestedwb = Flipped(new NestedWriteback(params))
})
val request_valid = RegInit(false.B)
val request = Reg(new FullRequest(params))
val meta_valid = RegInit(false.B)
val meta = Reg(new DirectoryResult(params))
// Define which states are valid
when (meta_valid) {
when (meta.state === INVALID) {
assert (!meta.clients.orR)
assert (!meta.dirty)
}
when (meta.state === BRANCH) {
assert (!meta.dirty)
}
when (meta.state === TRUNK) {
assert (meta.clients.orR)
assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one
}
when (meta.state === TIP) {
// noop
}
}
// Completed transitions (s_ = scheduled), (w_ = waiting)
val s_rprobe = RegInit(true.B) // B
val w_rprobeackfirst = RegInit(true.B)
val w_rprobeacklast = RegInit(true.B)
val s_release = RegInit(true.B) // CW w_rprobeackfirst
val w_releaseack = RegInit(true.B)
val s_pprobe = RegInit(true.B) // B
val s_acquire = RegInit(true.B) // A s_release, s_pprobe [1]
val s_flush = RegInit(true.B) // X w_releaseack
val w_grantfirst = RegInit(true.B)
val w_grantlast = RegInit(true.B)
val w_grant = RegInit(true.B) // first | last depending on wormhole
val w_pprobeackfirst = RegInit(true.B)
val w_pprobeacklast = RegInit(true.B)
val w_pprobeack = RegInit(true.B) // first | last depending on wormhole
val s_probeack = RegInit(true.B) // C w_pprobeackfirst (mutually exclusive with next two s_*)
val s_grantack = RegInit(true.B) // E w_grantfirst ... CAN require both outE&inD to service outD
val s_execute = RegInit(true.B) // D w_pprobeack, w_grant
val w_grantack = RegInit(true.B)
val s_writeback = RegInit(true.B) // W w_*
// [1]: We cannot issue outer Acquire while holding blockB (=> outA can stall)
// However, inB and outC are higher priority than outB, so s_release and s_pprobe
// may be safely issued while blockB. Thus we must NOT try to schedule the
// potentially stuck s_acquire with either of them (scheduler is all or none).
// Meta-data that we discover underway
val sink = Reg(UInt(params.outer.bundle.sinkBits.W))
val gotT = Reg(Bool())
val bad_grant = Reg(Bool())
val probes_done = Reg(UInt(params.clientBits.W))
val probes_toN = Reg(UInt(params.clientBits.W))
val probes_noT = Reg(Bool())
// When a nested transaction completes, update our meta data
when (meta_valid && meta.state =/= INVALID &&
io.nestedwb.set === request.set && io.nestedwb.tag === meta.tag) {
when (io.nestedwb.b_clr_dirty) { meta.dirty := false.B }
when (io.nestedwb.c_set_dirty) { meta.dirty := true.B }
when (io.nestedwb.b_toB) { meta.state := BRANCH }
when (io.nestedwb.b_toN) { meta.hit := false.B }
}
// Scheduler status
io.status.valid := request_valid
io.status.bits.set := request.set
io.status.bits.tag := request.tag
io.status.bits.way := meta.way
io.status.bits.blockB := !meta_valid || ((!w_releaseack || !w_rprobeacklast || !w_pprobeacklast) && !w_grantfirst)
io.status.bits.nestB := meta_valid && w_releaseack && w_rprobeacklast && w_pprobeacklast && !w_grantfirst
// The above rules ensure we will block and not nest an outer probe while still doing our
// own inner probes. Thus every probe wakes exactly one MSHR.
io.status.bits.blockC := !meta_valid
io.status.bits.nestC := meta_valid && (!w_rprobeackfirst || !w_pprobeackfirst || !w_grantfirst)
// The w_grantfirst in nestC is necessary to deal with:
// acquire waiting for grant, inner release gets queued, outer probe -> inner probe -> deadlock
// ... this is possible because the release+probe can be for same set, but different tag
// We can only demand: block, nest, or queue
assert (!io.status.bits.nestB || !io.status.bits.blockB)
assert (!io.status.bits.nestC || !io.status.bits.blockC)
// Scheduler requests
val no_wait = w_rprobeacklast && w_releaseack && w_grantlast && w_pprobeacklast && w_grantack
io.schedule.bits.a.valid := !s_acquire && s_release && s_pprobe
io.schedule.bits.b.valid := !s_rprobe || !s_pprobe
io.schedule.bits.c.valid := (!s_release && w_rprobeackfirst) || (!s_probeack && w_pprobeackfirst)
io.schedule.bits.d.valid := !s_execute && w_pprobeack && w_grant
io.schedule.bits.e.valid := !s_grantack && w_grantfirst
io.schedule.bits.x.valid := !s_flush && w_releaseack
io.schedule.bits.dir.valid := (!s_release && w_rprobeackfirst) || (!s_writeback && no_wait)
io.schedule.bits.reload := no_wait
io.schedule.valid := io.schedule.bits.a.valid || io.schedule.bits.b.valid || io.schedule.bits.c.valid ||
io.schedule.bits.d.valid || io.schedule.bits.e.valid || io.schedule.bits.x.valid ||
io.schedule.bits.dir.valid
// Schedule completions
when (io.schedule.ready) {
s_rprobe := true.B
when (w_rprobeackfirst) { s_release := true.B }
s_pprobe := true.B
when (s_release && s_pprobe) { s_acquire := true.B }
when (w_releaseack) { s_flush := true.B }
when (w_pprobeackfirst) { s_probeack := true.B }
when (w_grantfirst) { s_grantack := true.B }
when (w_pprobeack && w_grant) { s_execute := true.B }
when (no_wait) { s_writeback := true.B }
// Await the next operation
when (no_wait) {
request_valid := false.B
meta_valid := false.B
}
}
// Resulting meta-data
val final_meta_writeback = WireInit(meta)
val req_clientBit = params.clientBit(request.source)
val req_needT = needT(request.opcode, request.param)
val req_acquire = request.opcode === AcquireBlock || request.opcode === AcquirePerm
val meta_no_clients = !meta.clients.orR
val req_promoteT = req_acquire && Mux(meta.hit, meta_no_clients && meta.state === TIP, gotT)
when (request.prio(2) && (!params.firstLevel).B) { // always a hit
final_meta_writeback.dirty := meta.dirty || request.opcode(0)
final_meta_writeback.state := Mux(request.param =/= TtoT && meta.state === TRUNK, TIP, meta.state)
final_meta_writeback.clients := meta.clients & ~Mux(isToN(request.param), req_clientBit, 0.U)
final_meta_writeback.hit := true.B // chained requests are hits
} .elsewhen (request.control && params.control.B) { // request.prio(0)
when (meta.hit) {
final_meta_writeback.dirty := false.B
final_meta_writeback.state := INVALID
final_meta_writeback.clients := meta.clients & ~probes_toN
}
final_meta_writeback.hit := false.B
} .otherwise {
final_meta_writeback.dirty := (meta.hit && meta.dirty) || !request.opcode(2)
final_meta_writeback.state := Mux(req_needT,
Mux(req_acquire, TRUNK, TIP),
Mux(!meta.hit, Mux(gotT, Mux(req_acquire, TRUNK, TIP), BRANCH),
MuxLookup(meta.state, 0.U(2.W))(Seq(
INVALID -> BRANCH,
BRANCH -> BRANCH,
TRUNK -> TIP,
TIP -> Mux(meta_no_clients && req_acquire, TRUNK, TIP)))))
final_meta_writeback.clients := Mux(meta.hit, meta.clients & ~probes_toN, 0.U) |
Mux(req_acquire, req_clientBit, 0.U)
final_meta_writeback.tag := request.tag
final_meta_writeback.hit := true.B
}
when (bad_grant) {
when (meta.hit) {
// upgrade failed (B -> T)
assert (!meta_valid || meta.state === BRANCH)
final_meta_writeback.hit := true.B
final_meta_writeback.dirty := false.B
final_meta_writeback.state := BRANCH
final_meta_writeback.clients := meta.clients & ~probes_toN
} .otherwise {
// failed N -> (T or B)
final_meta_writeback.hit := false.B
final_meta_writeback.dirty := false.B
final_meta_writeback.state := INVALID
final_meta_writeback.clients := 0.U
}
}
val invalid = Wire(new DirectoryEntry(params))
invalid.dirty := false.B
invalid.state := INVALID
invalid.clients := 0.U
invalid.tag := 0.U
// Just because a client says BtoT, by the time we process the request he may be N.
// Therefore, we must consult our own meta-data state to confirm he owns the line still.
val honour_BtoT = meta.hit && (meta.clients & req_clientBit).orR
// The client asking us to act is proof they don't have permissions.
val excluded_client = Mux(meta.hit && request.prio(0) && skipProbeN(request.opcode, params.cache.hintsSkipProbe), req_clientBit, 0.U)
io.schedule.bits.a.bits.tag := request.tag
io.schedule.bits.a.bits.set := request.set
io.schedule.bits.a.bits.param := Mux(req_needT, Mux(meta.hit, BtoT, NtoT), NtoB)
io.schedule.bits.a.bits.block := request.size =/= log2Ceil(params.cache.blockBytes).U ||
!(request.opcode === PutFullData || request.opcode === AcquirePerm)
io.schedule.bits.a.bits.source := 0.U
io.schedule.bits.b.bits.param := Mux(!s_rprobe, toN, Mux(request.prio(1), request.param, Mux(req_needT, toN, toB)))
io.schedule.bits.b.bits.tag := Mux(!s_rprobe, meta.tag, request.tag)
io.schedule.bits.b.bits.set := request.set
io.schedule.bits.b.bits.clients := meta.clients & ~excluded_client
io.schedule.bits.c.bits.opcode := Mux(meta.dirty, ReleaseData, Release)
io.schedule.bits.c.bits.param := Mux(meta.state === BRANCH, BtoN, TtoN)
io.schedule.bits.c.bits.source := 0.U
io.schedule.bits.c.bits.tag := meta.tag
io.schedule.bits.c.bits.set := request.set
io.schedule.bits.c.bits.way := meta.way
io.schedule.bits.c.bits.dirty := meta.dirty
io.schedule.bits.d.bits.viewAsSupertype(chiselTypeOf(request)) := request
io.schedule.bits.d.bits.param := Mux(!req_acquire, request.param,
MuxLookup(request.param, request.param)(Seq(
NtoB -> Mux(req_promoteT, NtoT, NtoB),
BtoT -> Mux(honour_BtoT, BtoT, NtoT),
NtoT -> NtoT)))
io.schedule.bits.d.bits.sink := 0.U
io.schedule.bits.d.bits.way := meta.way
io.schedule.bits.d.bits.bad := bad_grant
io.schedule.bits.e.bits.sink := sink
io.schedule.bits.x.bits.fail := false.B
io.schedule.bits.dir.bits.set := request.set
io.schedule.bits.dir.bits.way := meta.way
io.schedule.bits.dir.bits.data := Mux(!s_release, invalid, WireInit(new DirectoryEntry(params), init = final_meta_writeback))
// Coverage of state transitions
def cacheState(entry: DirectoryEntry, hit: Bool) = {
val out = WireDefault(0.U)
val c = entry.clients.orR
val d = entry.dirty
switch (entry.state) {
is (BRANCH) { out := Mux(c, S_BRANCH_C.code, S_BRANCH.code) }
is (TRUNK) { out := Mux(d, S_TRUNK_CD.code, S_TRUNK_C.code) }
is (TIP) { out := Mux(c, Mux(d, S_TIP_CD.code, S_TIP_C.code), Mux(d, S_TIP_D.code, S_TIP.code)) }
is (INVALID) { out := S_INVALID.code }
}
when (!hit) { out := S_INVALID.code }
out
}
val p = !params.lastLevel // can be probed
val c = !params.firstLevel // can be acquired
val m = params.inner.client.clients.exists(!_.supports.probe) // can be written (or read)
val r = params.outer.manager.managers.exists(!_.alwaysGrantsT) // read-only devices exist
val f = params.control // flush control register exists
val cfg = (p, c, m, r, f)
val b = r || p // can reach branch state (via probe downgrade or read-only device)
// The cache must be used for something or we would not be here
require(c || m)
val evict = cacheState(meta, !meta.hit)
val before = cacheState(meta, meta.hit)
val after = cacheState(final_meta_writeback, true.B)
def eviction(from: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) {
if (cover) {
params.ccover(evict === from.code, s"MSHR_${from}_EVICT", s"State transition from ${from} to evicted ${cfg}")
} else {
assert(!(evict === from.code), cf"State transition from ${from} to evicted should be impossible ${cfg}")
}
if (cover && f) {
params.ccover(before === from.code, s"MSHR_${from}_FLUSH", s"State transition from ${from} to flushed ${cfg}")
} else {
assert(!(before === from.code), cf"State transition from ${from} to flushed should be impossible ${cfg}")
}
}
def transition(from: CacheState, to: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) {
if (cover) {
params.ccover(before === from.code && after === to.code, s"MSHR_${from}_${to}", s"State transition from ${from} to ${to} ${cfg}")
} else {
assert(!(before === from.code && after === to.code), cf"State transition from ${from} to ${to} should be impossible ${cfg}")
}
}
when ((!s_release && w_rprobeackfirst) && io.schedule.ready) {
eviction(S_BRANCH, b) // MMIO read to read-only device
eviction(S_BRANCH_C, b && c) // you need children to become C
eviction(S_TIP, true) // MMIO read || clean release can lead to this state
eviction(S_TIP_C, c) // needs two clients || client + mmio || downgrading client
eviction(S_TIP_CD, c) // needs two clients || client + mmio || downgrading client
eviction(S_TIP_D, true) // MMIO write || dirty release lead here
eviction(S_TRUNK_C, c) // acquire for write
eviction(S_TRUNK_CD, c) // dirty release then reacquire
}
when ((!s_writeback && no_wait) && io.schedule.ready) {
transition(S_INVALID, S_BRANCH, b && m) // only MMIO can bring us to BRANCH state
transition(S_INVALID, S_BRANCH_C, b && c) // C state is only possible if there are inner caches
transition(S_INVALID, S_TIP, m) // MMIO read
transition(S_INVALID, S_TIP_C, false) // we would go S_TRUNK_C instead
transition(S_INVALID, S_TIP_CD, false) // acquire does not cause dirty immediately
transition(S_INVALID, S_TIP_D, m) // MMIO write
transition(S_INVALID, S_TRUNK_C, c) // acquire
transition(S_INVALID, S_TRUNK_CD, false) // acquire does not cause dirty immediately
transition(S_BRANCH, S_INVALID, b && p) // probe can do this (flushes run as evictions)
transition(S_BRANCH, S_BRANCH_C, b && c) // acquire
transition(S_BRANCH, S_TIP, b && m) // prefetch write
transition(S_BRANCH, S_TIP_C, false) // we would go S_TRUNK_C instead
transition(S_BRANCH, S_TIP_CD, false) // acquire does not cause dirty immediately
transition(S_BRANCH, S_TIP_D, b && m) // MMIO write
transition(S_BRANCH, S_TRUNK_C, b && c) // acquire
transition(S_BRANCH, S_TRUNK_CD, false) // acquire does not cause dirty immediately
transition(S_BRANCH_C, S_INVALID, b && c && p)
transition(S_BRANCH_C, S_BRANCH, b && c) // clean release (optional)
transition(S_BRANCH_C, S_TIP, b && c && m) // prefetch write
transition(S_BRANCH_C, S_TIP_C, false) // we would go S_TRUNK_C instead
transition(S_BRANCH_C, S_TIP_D, b && c && m) // MMIO write
transition(S_BRANCH_C, S_TIP_CD, false) // going dirty means we must shoot down clients
transition(S_BRANCH_C, S_TRUNK_C, b && c) // acquire
transition(S_BRANCH_C, S_TRUNK_CD, false) // acquire does not cause dirty immediately
transition(S_TIP, S_INVALID, p)
transition(S_TIP, S_BRANCH, p) // losing TIP only possible via probe
transition(S_TIP, S_BRANCH_C, false) // we would go S_TRUNK_C instead
transition(S_TIP, S_TIP_C, false) // we would go S_TRUNK_C instead
transition(S_TIP, S_TIP_D, m) // direct dirty only via MMIO write
transition(S_TIP, S_TIP_CD, false) // acquire does not make us dirty immediately
transition(S_TIP, S_TRUNK_C, c) // acquire
transition(S_TIP, S_TRUNK_CD, false) // acquire does not make us dirty immediately
transition(S_TIP_C, S_INVALID, c && p)
transition(S_TIP_C, S_BRANCH, c && p) // losing TIP only possible via probe
transition(S_TIP_C, S_BRANCH_C, c && p) // losing TIP only possible via probe
transition(S_TIP_C, S_TIP, c) // probed while MMIO read || clean release (optional)
transition(S_TIP_C, S_TIP_D, c && m) // direct dirty only via MMIO write
transition(S_TIP_C, S_TIP_CD, false) // going dirty means we must shoot down clients
transition(S_TIP_C, S_TRUNK_C, c) // acquire
transition(S_TIP_C, S_TRUNK_CD, false) // acquire does not make us immediately dirty
transition(S_TIP_D, S_INVALID, p)
transition(S_TIP_D, S_BRANCH, p) // losing D is only possible via probe
transition(S_TIP_D, S_BRANCH_C, p && c) // probed while acquire shared
transition(S_TIP_D, S_TIP, p) // probed while MMIO read || outer probe.toT (optional)
transition(S_TIP_D, S_TIP_C, false) // we would go S_TRUNK_C instead
transition(S_TIP_D, S_TIP_CD, false) // we would go S_TRUNK_CD instead
transition(S_TIP_D, S_TRUNK_C, p && c) // probed while acquired
transition(S_TIP_D, S_TRUNK_CD, c) // acquire
transition(S_TIP_CD, S_INVALID, c && p)
transition(S_TIP_CD, S_BRANCH, c && p) // losing D is only possible via probe
transition(S_TIP_CD, S_BRANCH_C, c && p) // losing D is only possible via probe
transition(S_TIP_CD, S_TIP, c && p) // probed while MMIO read || outer probe.toT (optional)
transition(S_TIP_CD, S_TIP_C, false) // we would go S_TRUNK_C instead
transition(S_TIP_CD, S_TIP_D, c) // MMIO write || clean release (optional)
transition(S_TIP_CD, S_TRUNK_C, c && p) // probed while acquire
transition(S_TIP_CD, S_TRUNK_CD, c) // acquire
transition(S_TRUNK_C, S_INVALID, c && p)
transition(S_TRUNK_C, S_BRANCH, c && p) // losing TIP only possible via probe
transition(S_TRUNK_C, S_BRANCH_C, c && p) // losing TIP only possible via probe
transition(S_TRUNK_C, S_TIP, c) // MMIO read || clean release (optional)
transition(S_TRUNK_C, S_TIP_C, c) // bounce shared
transition(S_TRUNK_C, S_TIP_D, c) // dirty release
transition(S_TRUNK_C, S_TIP_CD, c) // dirty bounce shared
transition(S_TRUNK_C, S_TRUNK_CD, c) // dirty bounce
transition(S_TRUNK_CD, S_INVALID, c && p)
transition(S_TRUNK_CD, S_BRANCH, c && p) // losing D only possible via probe
transition(S_TRUNK_CD, S_BRANCH_C, c && p) // losing D only possible via probe
transition(S_TRUNK_CD, S_TIP, c && p) // probed while MMIO read || outer probe.toT (optional)
transition(S_TRUNK_CD, S_TIP_C, false) // we would go S_TRUNK_C instead
transition(S_TRUNK_CD, S_TIP_D, c) // dirty release
transition(S_TRUNK_CD, S_TIP_CD, c) // bounce shared
transition(S_TRUNK_CD, S_TRUNK_C, c && p) // probed while acquire
}
// Handle response messages
val probe_bit = params.clientBit(io.sinkc.bits.source)
val last_probe = (probes_done | probe_bit) === (meta.clients & ~excluded_client)
val probe_toN = isToN(io.sinkc.bits.param)
if (!params.firstLevel) when (io.sinkc.valid) {
params.ccover( probe_toN && io.schedule.bits.b.bits.param === toB, "MSHR_PROBE_FULL", "Client downgraded to N when asked only to do B")
params.ccover(!probe_toN && io.schedule.bits.b.bits.param === toB, "MSHR_PROBE_HALF", "Client downgraded to B when asked only to do B")
// Caution: the probe matches us only in set.
// We would never allow an outer probe to nest until both w_[rp]probeack complete, so
// it is safe to just unguardedly update the probe FSM.
probes_done := probes_done | probe_bit
probes_toN := probes_toN | Mux(probe_toN, probe_bit, 0.U)
probes_noT := probes_noT || io.sinkc.bits.param =/= TtoT
w_rprobeackfirst := w_rprobeackfirst || last_probe
w_rprobeacklast := w_rprobeacklast || (last_probe && io.sinkc.bits.last)
w_pprobeackfirst := w_pprobeackfirst || last_probe
w_pprobeacklast := w_pprobeacklast || (last_probe && io.sinkc.bits.last)
// Allow wormhole routing from sinkC if the first request beat has offset 0
val set_pprobeack = last_probe && (io.sinkc.bits.last || request.offset === 0.U)
w_pprobeack := w_pprobeack || set_pprobeack
params.ccover(!set_pprobeack && w_rprobeackfirst, "MSHR_PROBE_SERIAL", "Sequential routing of probe response data")
params.ccover( set_pprobeack && w_rprobeackfirst, "MSHR_PROBE_WORMHOLE", "Wormhole routing of probe response data")
// However, meta-data updates need to be done more cautiously
when (meta.state =/= INVALID && io.sinkc.bits.tag === meta.tag && io.sinkc.bits.data) { meta.dirty := true.B } // !!!
}
when (io.sinkd.valid) {
when (io.sinkd.bits.opcode === Grant || io.sinkd.bits.opcode === GrantData) {
sink := io.sinkd.bits.sink
w_grantfirst := true.B
w_grantlast := io.sinkd.bits.last
// Record if we need to prevent taking ownership
bad_grant := io.sinkd.bits.denied
// Allow wormhole routing for requests whose first beat has offset 0
w_grant := request.offset === 0.U || io.sinkd.bits.last
params.ccover(io.sinkd.bits.opcode === GrantData && request.offset === 0.U, "MSHR_GRANT_WORMHOLE", "Wormhole routing of grant response data")
params.ccover(io.sinkd.bits.opcode === GrantData && request.offset =/= 0.U, "MSHR_GRANT_SERIAL", "Sequential routing of grant response data")
gotT := io.sinkd.bits.param === toT
}
.elsewhen (io.sinkd.bits.opcode === ReleaseAck) {
w_releaseack := true.B
}
}
when (io.sinke.valid) {
w_grantack := true.B
}
// Bootstrap new requests
val allocate_as_full = WireInit(new FullRequest(params), init = io.allocate.bits)
val new_meta = Mux(io.allocate.valid && io.allocate.bits.repeat, final_meta_writeback, io.directory.bits)
val new_request = Mux(io.allocate.valid, allocate_as_full, request)
val new_needT = needT(new_request.opcode, new_request.param)
val new_clientBit = params.clientBit(new_request.source)
val new_skipProbe = Mux(skipProbeN(new_request.opcode, params.cache.hintsSkipProbe), new_clientBit, 0.U)
val prior = cacheState(final_meta_writeback, true.B)
def bypass(from: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) {
if (cover) {
params.ccover(prior === from.code, s"MSHR_${from}_BYPASS", s"State bypass transition from ${from} ${cfg}")
} else {
assert(!(prior === from.code), cf"State bypass from ${from} should be impossible ${cfg}")
}
}
when (io.allocate.valid && io.allocate.bits.repeat) {
bypass(S_INVALID, f || p) // Can lose permissions (probe/flush)
bypass(S_BRANCH, b) // MMIO read to read-only device
bypass(S_BRANCH_C, b && c) // you need children to become C
bypass(S_TIP, true) // MMIO read || clean release can lead to this state
bypass(S_TIP_C, c) // needs two clients || client + mmio || downgrading client
bypass(S_TIP_CD, c) // needs two clients || client + mmio || downgrading client
bypass(S_TIP_D, true) // MMIO write || dirty release lead here
bypass(S_TRUNK_C, c) // acquire for write
bypass(S_TRUNK_CD, c) // dirty release then reacquire
}
when (io.allocate.valid) {
assert (!request_valid || (no_wait && io.schedule.fire))
request_valid := true.B
request := io.allocate.bits
}
// Create execution plan
when (io.directory.valid || (io.allocate.valid && io.allocate.bits.repeat)) {
meta_valid := true.B
meta := new_meta
probes_done := 0.U
probes_toN := 0.U
probes_noT := false.B
gotT := false.B
bad_grant := false.B
// These should already be either true or turning true
// We clear them here explicitly to simplify the mux tree
s_rprobe := true.B
w_rprobeackfirst := true.B
w_rprobeacklast := true.B
s_release := true.B
w_releaseack := true.B
s_pprobe := true.B
s_acquire := true.B
s_flush := true.B
w_grantfirst := true.B
w_grantlast := true.B
w_grant := true.B
w_pprobeackfirst := true.B
w_pprobeacklast := true.B
w_pprobeack := true.B
s_probeack := true.B
s_grantack := true.B
s_execute := true.B
w_grantack := true.B
s_writeback := true.B
// For C channel requests (ie: Release[Data])
when (new_request.prio(2) && (!params.firstLevel).B) {
s_execute := false.B
// Do we need to go dirty?
when (new_request.opcode(0) && !new_meta.dirty) {
s_writeback := false.B
}
// Does our state change?
when (isToB(new_request.param) && new_meta.state === TRUNK) {
s_writeback := false.B
}
// Do our clients change?
when (isToN(new_request.param) && (new_meta.clients & new_clientBit) =/= 0.U) {
s_writeback := false.B
}
assert (new_meta.hit)
}
// For X channel requests (ie: flush)
.elsewhen (new_request.control && params.control.B) { // new_request.prio(0)
s_flush := false.B
// Do we need to actually do something?
when (new_meta.hit) {
s_release := false.B
w_releaseack := false.B
// Do we need to shoot-down inner caches?
when ((!params.firstLevel).B && (new_meta.clients =/= 0.U)) {
s_rprobe := false.B
w_rprobeackfirst := false.B
w_rprobeacklast := false.B
}
}
}
// For A channel requests
.otherwise { // new_request.prio(0) && !new_request.control
s_execute := false.B
// Do we need an eviction?
when (!new_meta.hit && new_meta.state =/= INVALID) {
s_release := false.B
w_releaseack := false.B
// Do we need to shoot-down inner caches?
when ((!params.firstLevel).B & (new_meta.clients =/= 0.U)) {
s_rprobe := false.B
w_rprobeackfirst := false.B
w_rprobeacklast := false.B
}
}
// Do we need an acquire?
when (!new_meta.hit || (new_meta.state === BRANCH && new_needT)) {
s_acquire := false.B
w_grantfirst := false.B
w_grantlast := false.B
w_grant := false.B
s_grantack := false.B
s_writeback := false.B
}
// Do we need a probe?
when ((!params.firstLevel).B && (new_meta.hit &&
(new_needT || new_meta.state === TRUNK) &&
(new_meta.clients & ~new_skipProbe) =/= 0.U)) {
s_pprobe := false.B
w_pprobeackfirst := false.B
w_pprobeacklast := false.B
w_pprobeack := false.B
s_writeback := false.B
}
// Do we need a grantack?
when (new_request.opcode === AcquireBlock || new_request.opcode === AcquirePerm) {
w_grantack := false.B
s_writeback := false.B
}
// Becomes dirty?
when (!new_request.opcode(2) && new_meta.hit && !new_meta.dirty) {
s_writeback := false.B
}
}
}
}
File Parameters.scala:
/*
* Copyright 2019 SiFive, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You should have received a copy of LICENSE.Apache2 along with
* this software. If not, you may obtain a copy at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package sifive.blocks.inclusivecache
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
import freechips.rocketchip.util.property.cover
import scala.math.{min,max}
case class CacheParameters(
level: Int,
ways: Int,
sets: Int,
blockBytes: Int,
beatBytes: Int, // inner
hintsSkipProbe: Boolean)
{
require (ways > 0)
require (sets > 0)
require (blockBytes > 0 && isPow2(blockBytes))
require (beatBytes > 0 && isPow2(beatBytes))
require (blockBytes >= beatBytes)
val blocks = ways * sets
val sizeBytes = blocks * blockBytes
val blockBeats = blockBytes/beatBytes
}
case class InclusiveCachePortParameters(
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)
{
def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new TLBuffer(a, b, c, d, e))
}
object InclusiveCachePortParameters
{
val none = InclusiveCachePortParameters(
a = BufferParams.none,
b = BufferParams.none,
c = BufferParams.none,
d = BufferParams.none,
e = BufferParams.none)
val full = InclusiveCachePortParameters(
a = BufferParams.default,
b = BufferParams.default,
c = BufferParams.default,
d = BufferParams.default,
e = BufferParams.default)
// This removes feed-through paths from C=>A and A=>C
val fullC = InclusiveCachePortParameters(
a = BufferParams.none,
b = BufferParams.none,
c = BufferParams.default,
d = BufferParams.none,
e = BufferParams.none)
val flowAD = InclusiveCachePortParameters(
a = BufferParams.flow,
b = BufferParams.none,
c = BufferParams.none,
d = BufferParams.flow,
e = BufferParams.none)
val flowAE = InclusiveCachePortParameters(
a = BufferParams.flow,
b = BufferParams.none,
c = BufferParams.none,
d = BufferParams.none,
e = BufferParams.flow)
// For innerBuf:
// SinkA: no restrictions, flows into scheduler+putbuffer
// SourceB: no restrictions, flows out of scheduler
// sinkC: no restrictions, flows into scheduler+putbuffer & buffered to bankedStore
// SourceD: no restrictions, flows out of bankedStore/regout
// SinkE: no restrictions, flows into scheduler
//
// ... so while none is possible, you probably want at least flowAC to cut ready
// from the scheduler delay and flowD to ease SourceD back-pressure
// For outerBufer:
// SourceA: must not be pipe, flows out of scheduler
// SinkB: no restrictions, flows into scheduler
// SourceC: pipe is useless, flows out of bankedStore/regout, parameter depth ignored
// SinkD: no restrictions, flows into scheduler & bankedStore
// SourceE: must not be pipe, flows out of scheduler
//
// ... AE take the channel ready into the scheduler, so you need at least flowAE
}
case class InclusiveCacheMicroParameters(
writeBytes: Int, // backing store update granularity
memCycles: Int = 40, // # of L2 clock cycles for a memory round-trip (50ns @ 800MHz)
portFactor: Int = 4, // numSubBanks = (widest TL port * portFactor) / writeBytes
dirReg: Boolean = false,
innerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.fullC, // or none
outerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.full) // or flowAE
{
require (writeBytes > 0 && isPow2(writeBytes))
require (memCycles > 0)
require (portFactor >= 2) // for inner RMW and concurrent outer Relase + Grant
}
case class InclusiveCacheControlParameters(
address: BigInt,
beatBytes: Int,
bankedControl: Boolean)
case class InclusiveCacheParameters(
cache: CacheParameters,
micro: InclusiveCacheMicroParameters,
control: Boolean,
inner: TLEdgeIn,
outer: TLEdgeOut)(implicit val p: Parameters)
{
require (cache.ways > 1)
require (cache.sets > 1 && isPow2(cache.sets))
require (micro.writeBytes <= inner.manager.beatBytes)
require (micro.writeBytes <= outer.manager.beatBytes)
require (inner.manager.beatBytes <= cache.blockBytes)
require (outer.manager.beatBytes <= cache.blockBytes)
// Require that all cached address ranges have contiguous blocks
outer.manager.managers.flatMap(_.address).foreach { a =>
require (a.alignment >= cache.blockBytes)
}
// If we are the first level cache, we do not need to support inner-BCE
val firstLevel = !inner.client.clients.exists(_.supports.probe)
// If we are the last level cache, we do not need to support outer-B
val lastLevel = !outer.manager.managers.exists(_.regionType > RegionType.UNCACHED)
require (lastLevel)
// Provision enough resources to achieve full throughput with missing single-beat accesses
val mshrs = InclusiveCacheParameters.all_mshrs(cache, micro)
val secondary = max(mshrs, micro.memCycles - mshrs)
val putLists = micro.memCycles // allow every request to be single beat
val putBeats = max(2*cache.blockBeats, micro.memCycles)
val relLists = 2
val relBeats = relLists*cache.blockBeats
val flatAddresses = AddressSet.unify(outer.manager.managers.flatMap(_.address))
val pickMask = AddressDecoder(flatAddresses.map(Seq(_)), flatAddresses.map(_.mask).reduce(_|_))
def bitOffsets(x: BigInt, offset: Int = 0, tail: List[Int] = List.empty[Int]): List[Int] =
if (x == 0) tail.reverse else bitOffsets(x >> 1, offset + 1, if ((x & 1) == 1) offset :: tail else tail)
val addressMapping = bitOffsets(pickMask)
val addressBits = addressMapping.size
// println(s"addresses: ${flatAddresses} => ${pickMask} => ${addressBits}")
val allClients = inner.client.clients.size
val clientBitsRaw = inner.client.clients.filter(_.supports.probe).size
val clientBits = max(1, clientBitsRaw)
val stateBits = 2
val wayBits = log2Ceil(cache.ways)
val setBits = log2Ceil(cache.sets)
val offsetBits = log2Ceil(cache.blockBytes)
val tagBits = addressBits - setBits - offsetBits
val putBits = log2Ceil(max(putLists, relLists))
require (tagBits > 0)
require (offsetBits > 0)
val innerBeatBits = (offsetBits - log2Ceil(inner.manager.beatBytes)) max 1
val outerBeatBits = (offsetBits - log2Ceil(outer.manager.beatBytes)) max 1
val innerMaskBits = inner.manager.beatBytes / micro.writeBytes
val outerMaskBits = outer.manager.beatBytes / micro.writeBytes
def clientBit(source: UInt): UInt = {
if (clientBitsRaw == 0) {
0.U
} else {
Cat(inner.client.clients.filter(_.supports.probe).map(_.sourceId.contains(source)).reverse)
}
}
def clientSource(bit: UInt): UInt = {
if (clientBitsRaw == 0) {
0.U
} else {
Mux1H(bit, inner.client.clients.filter(_.supports.probe).map(c => c.sourceId.start.U))
}
}
def parseAddress(x: UInt): (UInt, UInt, UInt) = {
val offset = Cat(addressMapping.map(o => x(o,o)).reverse)
val set = offset >> offsetBits
val tag = set >> setBits
(tag(tagBits-1, 0), set(setBits-1, 0), offset(offsetBits-1, 0))
}
def widen(x: UInt, width: Int): UInt = {
val y = x | 0.U(width.W)
assert (y >> width === 0.U)
y(width-1, 0)
}
def expandAddress(tag: UInt, set: UInt, offset: UInt): UInt = {
val base = Cat(widen(tag, tagBits), widen(set, setBits), widen(offset, offsetBits))
val bits = Array.fill(outer.bundle.addressBits) { 0.U(1.W) }
addressMapping.zipWithIndex.foreach { case (a, i) => bits(a) = base(i,i) }
Cat(bits.reverse)
}
def restoreAddress(expanded: UInt): UInt = {
val missingBits = flatAddresses
.map { a => (a.widen(pickMask).base, a.widen(~pickMask)) } // key is the bits to restore on match
.groupBy(_._1)
.view
.mapValues(_.map(_._2))
val muxMask = AddressDecoder(missingBits.values.toList)
val mux = missingBits.toList.map { case (bits, addrs) =>
val widen = addrs.map(_.widen(~muxMask))
val matches = AddressSet
.unify(widen.distinct)
.map(_.contains(expanded))
.reduce(_ || _)
(matches, bits.U)
}
expanded | Mux1H(mux)
}
def dirReg[T <: Data](x: T, en: Bool = true.B): T = {
if (micro.dirReg) RegEnable(x, en) else x
}
def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) =
cover(cond, "CCACHE_L" + cache.level + "_" + label, "MemorySystem;;" + desc)
}
object MetaData
{
val stateBits = 2
def INVALID: UInt = 0.U(stateBits.W) // way is empty
def BRANCH: UInt = 1.U(stateBits.W) // outer slave cache is trunk
def TRUNK: UInt = 2.U(stateBits.W) // unique inner master cache is trunk
def TIP: UInt = 3.U(stateBits.W) // we are trunk, inner masters are branch
// Does a request need trunk?
def needT(opcode: UInt, param: UInt): Bool = {
!opcode(2) ||
(opcode === TLMessages.Hint && param === TLHints.PREFETCH_WRITE) ||
((opcode === TLMessages.AcquireBlock || opcode === TLMessages.AcquirePerm) && param =/= TLPermissions.NtoB)
}
// Does a request prove the client need not be probed?
def skipProbeN(opcode: UInt, hintsSkipProbe: Boolean): Bool = {
// Acquire(toB) and Get => is N, so no probe
// Acquire(*toT) => is N or B, but need T, so no probe
// Hint => could be anything, so probe IS needed, if hintsSkipProbe is enabled, skip probe the same client
// Put* => is N or B, so probe IS needed
opcode === TLMessages.AcquireBlock || opcode === TLMessages.AcquirePerm || opcode === TLMessages.Get || (opcode === TLMessages.Hint && hintsSkipProbe.B)
}
def isToN(param: UInt): Bool = {
param === TLPermissions.TtoN || param === TLPermissions.BtoN || param === TLPermissions.NtoN
}
def isToB(param: UInt): Bool = {
param === TLPermissions.TtoB || param === TLPermissions.BtoB
}
}
object InclusiveCacheParameters
{
val lfsrBits = 10
val L2ControlAddress = 0x2010000
val L2ControlSize = 0x1000
def out_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = {
// We need 2-3 normal MSHRs to cover the Directory latency
// To fully exploit memory bandwidth-delay-product, we need memCyles/blockBeats MSHRs
max(if (micro.dirReg) 3 else 2, (micro.memCycles + cache.blockBeats - 1) / cache.blockBeats)
}
def all_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int =
// We need a dedicated MSHR for B+C each
2 + out_mshrs(cache, micro)
}
class InclusiveCacheBundle(params: InclusiveCacheParameters) extends Bundle
| module MSHR( // @[MSHR.scala:84:7]
input clock, // @[MSHR.scala:84:7]
input reset, // @[MSHR.scala:84:7]
input io_allocate_valid, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_0, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_1, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_2, // @[MSHR.scala:86:14]
input io_allocate_bits_control, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14]
input [6:0] io_allocate_bits_source, // @[MSHR.scala:86:14]
input [12:0] io_allocate_bits_tag, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14]
input [9:0] io_allocate_bits_set, // @[MSHR.scala:86:14]
input io_allocate_bits_repeat, // @[MSHR.scala:86:14]
input io_directory_valid, // @[MSHR.scala:86:14]
input io_directory_bits_dirty, // @[MSHR.scala:86:14]
input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14]
input io_directory_bits_clients, // @[MSHR.scala:86:14]
input [12:0] io_directory_bits_tag, // @[MSHR.scala:86:14]
input io_directory_bits_hit, // @[MSHR.scala:86:14]
input [2:0] io_directory_bits_way, // @[MSHR.scala:86:14]
output io_status_valid, // @[MSHR.scala:86:14]
output [9:0] io_status_bits_set, // @[MSHR.scala:86:14]
output [12:0] io_status_bits_tag, // @[MSHR.scala:86:14]
output [2:0] io_status_bits_way, // @[MSHR.scala:86:14]
output io_status_bits_blockB, // @[MSHR.scala:86:14]
output io_status_bits_nestB, // @[MSHR.scala:86:14]
output io_status_bits_blockC, // @[MSHR.scala:86:14]
output io_status_bits_nestC, // @[MSHR.scala:86:14]
input io_schedule_ready, // @[MSHR.scala:86:14]
output io_schedule_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_a_valid, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14]
output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14]
output io_schedule_bits_b_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14]
output io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14]
output io_schedule_bits_c_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14]
output io_schedule_bits_d_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_0, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14]
output [6:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14]
output io_schedule_bits_e_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14]
output io_schedule_bits_x_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14]
output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14]
output io_schedule_bits_reload, // @[MSHR.scala:86:14]
input io_sinkc_valid, // @[MSHR.scala:86:14]
input io_sinkc_bits_last, // @[MSHR.scala:86:14]
input [9:0] io_sinkc_bits_set, // @[MSHR.scala:86:14]
input [12:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14]
input [6:0] io_sinkc_bits_source, // @[MSHR.scala:86:14]
input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14]
input io_sinkc_bits_data, // @[MSHR.scala:86:14]
input io_sinkd_valid, // @[MSHR.scala:86:14]
input io_sinkd_bits_last, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14]
input [3:0] io_sinkd_bits_source, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14]
input io_sinkd_bits_denied, // @[MSHR.scala:86:14]
input io_sinke_valid, // @[MSHR.scala:86:14]
input [3:0] io_sinke_bits_sink, // @[MSHR.scala:86:14]
input [9:0] io_nestedwb_set, // @[MSHR.scala:86:14]
input [12:0] io_nestedwb_tag, // @[MSHR.scala:86:14]
input io_nestedwb_b_toN, // @[MSHR.scala:86:14]
input io_nestedwb_b_toB, // @[MSHR.scala:86:14]
input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14]
input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14]
);
wire [12:0] final_meta_writeback_tag; // @[MSHR.scala:215:38]
wire final_meta_writeback_clients; // @[MSHR.scala:215:38]
wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38]
wire final_meta_writeback_dirty; // @[MSHR.scala:215:38]
wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_0_0 = io_allocate_bits_prio_0; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7]
wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7]
wire [6:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7]
wire [12:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7]
wire [9:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7]
wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7]
wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7]
wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7]
wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7]
wire io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7]
wire [12:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7]
wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7]
wire [2:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7]
wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7]
wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7]
wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7]
wire [9:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7]
wire [12:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7]
wire [6:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7]
wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7]
wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7]
wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7]
wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7]
wire [3:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7]
wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7]
wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7]
wire [3:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7]
wire [9:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7]
wire [12:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7]
wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7]
wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7]
wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7]
wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_a_bits_source = 4'h0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_c_bits_source = 4'h0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_d_bits_sink = 4'h0; // @[MSHR.scala:84:7]
wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7]
wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68]
wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80]
wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21]
wire invalid_clients = 1'h0; // @[MSHR.scala:268:21]
wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137]
wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11]
wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137]
wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11]
wire [12:0] invalid_tag = 13'h0; // @[MSHR.scala:268:21]
wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21]
wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70]
wire allocate_as_full_prio_0 = io_allocate_bits_prio_0_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34]
wire [6:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34]
wire [12:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34]
wire [9:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34]
wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40]
wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93]
wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28]
wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39]
wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105]
wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55]
wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91]
wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41]
wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41]
wire [12:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41]
wire _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51]
wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64]
wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41]
wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41]
wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57]
wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41]
wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43]
wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40]
wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66]
wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41]
wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41]
wire _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41]
wire [12:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41]
wire no_wait; // @[MSHR.scala:183:83]
wire [9:0] io_status_bits_set_0; // @[MSHR.scala:84:7]
wire [12:0] io_status_bits_tag_0; // @[MSHR.scala:84:7]
wire [2:0] io_status_bits_way_0; // @[MSHR.scala:84:7]
wire io_status_bits_blockB_0; // @[MSHR.scala:84:7]
wire io_status_bits_nestB_0; // @[MSHR.scala:84:7]
wire io_status_bits_blockC_0; // @[MSHR.scala:84:7]
wire io_status_bits_nestC_0; // @[MSHR.scala:84:7]
wire io_status_valid_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_0_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7]
wire [6:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7]
wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7]
wire io_schedule_valid_0; // @[MSHR.scala:84:7]
reg request_valid; // @[MSHR.scala:97:30]
assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30]
reg request_prio_0; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_0_0 = request_prio_0; // @[MSHR.scala:84:7, :98:20]
reg request_prio_1; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20]
reg request_prio_2; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20]
reg request_control; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20]
reg [2:0] request_opcode; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20]
reg [2:0] request_param; // @[MSHR.scala:98:20]
reg [2:0] request_size; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20]
reg [6:0] request_source; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20]
reg [12:0] request_tag; // @[MSHR.scala:98:20]
assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_offset; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_put; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20]
reg [9:0] request_set; // @[MSHR.scala:98:20]
assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
reg meta_valid; // @[MSHR.scala:99:27]
reg meta_dirty; // @[MSHR.scala:100:17]
assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17]
reg [1:0] meta_state; // @[MSHR.scala:100:17]
reg meta_clients; // @[MSHR.scala:100:17]
wire _meta_no_clients_T = meta_clients; // @[MSHR.scala:100:17, :220:39]
wire evict_c = meta_clients; // @[MSHR.scala:100:17, :315:27]
wire before_c = meta_clients; // @[MSHR.scala:100:17, :315:27]
reg [12:0] meta_tag; // @[MSHR.scala:100:17]
assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17]
reg meta_hit; // @[MSHR.scala:100:17]
reg [2:0] meta_way; // @[MSHR.scala:100:17]
assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
wire [2:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38]
reg s_rprobe; // @[MSHR.scala:121:33]
reg w_rprobeackfirst; // @[MSHR.scala:122:33]
reg w_rprobeacklast; // @[MSHR.scala:123:33]
reg s_release; // @[MSHR.scala:124:33]
reg w_releaseack; // @[MSHR.scala:125:33]
reg s_pprobe; // @[MSHR.scala:126:33]
reg s_acquire; // @[MSHR.scala:127:33]
reg s_flush; // @[MSHR.scala:128:33]
reg w_grantfirst; // @[MSHR.scala:129:33]
reg w_grantlast; // @[MSHR.scala:130:33]
reg w_grant; // @[MSHR.scala:131:33]
reg w_pprobeackfirst; // @[MSHR.scala:132:33]
reg w_pprobeacklast; // @[MSHR.scala:133:33]
reg w_pprobeack; // @[MSHR.scala:134:33]
reg s_grantack; // @[MSHR.scala:136:33]
reg s_execute; // @[MSHR.scala:137:33]
reg w_grantack; // @[MSHR.scala:138:33]
reg s_writeback; // @[MSHR.scala:139:33]
reg [2:0] sink; // @[MSHR.scala:147:17]
assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17]
reg gotT; // @[MSHR.scala:148:17]
reg bad_grant; // @[MSHR.scala:149:22]
assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22]
reg probes_done; // @[MSHR.scala:150:24]
reg probes_toN; // @[MSHR.scala:151:23]
reg probes_noT; // @[MSHR.scala:152:23]
wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28]
wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45]
wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62]
wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 | _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}]
wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82]
wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 | _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}]
wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103]
wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}]
assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T | _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}]
assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40]
wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39]
wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}]
wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}]
wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96]
assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}]
assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93]
assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28]
assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28]
wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43]
wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64]
wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T | _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}]
wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85]
wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 | _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}]
assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}]
assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39]
wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33]
wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}]
wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}]
assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}]
assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83]
wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31]
wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}]
assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}]
assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55]
wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31]
wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44]
assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T | _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}]
assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41]
wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32]
wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}]
assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}]
assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64]
wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31]
wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}]
assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}]
assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57]
wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31]
assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}]
assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43]
wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31]
assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}]
assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40]
wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34]
wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}]
wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70]
wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}]
assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 | _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}]
assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66]
wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 | io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49]
wire _io_schedule_valid_T_1 = _io_schedule_valid_T | io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}]
wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 | io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}]
wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 | io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49]
wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 | io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}]
assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 | io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}]
assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105]
wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71]
wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71]
wire _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71]
wire after_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27]
wire prior_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27]
wire [12:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71]
wire final_meta_writeback_hit; // @[MSHR.scala:215:38]
wire req_clientBit = request_source == 7'h20; // @[Parameters.scala:46:9]
wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12]
wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12]
wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}]
wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13]
wire _req_needT_T_2; // @[Parameters.scala:270:13]
assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13]
wire _excluded_client_T_6; // @[Parameters.scala:279:117]
assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117]
wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42]
wire _req_needT_T_3; // @[Parameters.scala:270:42]
assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42]
wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11]
assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11]
wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42]
wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}]
wire _req_needT_T_5 = _req_needT_T_1 | _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33]
wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14]
wire _req_needT_T_6; // @[Parameters.scala:271:14]
assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14]
wire _req_acquire_T; // @[MSHR.scala:219:36]
assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14]
wire _excluded_client_T_1; // @[Parameters.scala:279:12]
assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12]
wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52]
wire _req_needT_T_8 = _req_needT_T_6 | _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}]
wire _req_needT_T_9 = |request_param; // @[Parameters.scala:271:89]
wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}]
wire req_needT = _req_needT_T_5 | _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80]
wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52]
wire req_acquire = _req_acquire_T | _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}]
wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}]
wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81]
wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}]
wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}]
wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}]
wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65]
wire _final_meta_writeback_dirty_T_1 = meta_dirty | _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}]
wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55]
wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78]
wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78]
assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78]
wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70]
assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70]
wire _evict_T_2; // @[MSHR.scala:317:26]
assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26]
wire _before_T_1; // @[MSHR.scala:317:26]
assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26]
wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}]
wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}]
wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43]
wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43]
assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43]
wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43]
wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T | _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}]
wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75]
wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 | _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}]
wire _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 & req_clientBit; // @[Parameters.scala:46:9]
wire _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}]
wire _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}]
wire _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54]
wire _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}]
wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45]
wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}]
wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 | _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}]
wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40]
wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40]
assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40]
wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65]
assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65]
wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41]
wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}]
wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72]
wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}]
wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70]
wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70]
assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70]
wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53]
assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53]
wire _evict_T_1; // @[MSHR.scala:317:26]
assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26]
wire _before_T; // @[MSHR.scala:317:26]
assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26]
wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70]
wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70]
wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55]
wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70]
wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70]
wire _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66]
wire _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}]
wire _final_meta_writeback_clients_T_12 = meta_hit & _final_meta_writeback_clients_T_11; // @[MSHR.scala:100:17, :245:{40,64}]
wire _final_meta_writeback_clients_T_13 = req_acquire & req_clientBit; // @[Parameters.scala:46:9]
wire _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 | _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40]
assign final_meta_writeback_tag = request_prio_2 | request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30]
wire _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54]
wire _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}]
assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 | ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21]
assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21]
assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36]
assign final_meta_writeback_clients = bad_grant ? meta_hit & _final_meta_writeback_clients_T_16 : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36]
wire _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:46:9]
wire _honour_BtoT_T_1 = _honour_BtoT_T; // @[MSHR.scala:276:{47,64}]
wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}]
wire _excluded_client_T = meta_hit & request_prio_0; // @[MSHR.scala:98:20, :100:17, :279:38]
wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50]
wire _excluded_client_T_3 = _excluded_client_T_1 | _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}]
wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87]
wire _excluded_client_T_5 = _excluded_client_T_3 | _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}]
wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}]
wire _excluded_client_T_9 = _excluded_client_T & _excluded_client_T_8; // @[Parameters.scala:279:106]
wire excluded_client = _excluded_client_T_9 & req_clientBit; // @[Parameters.scala:46:9]
wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56]
wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70]
assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}]
wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51]
wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55]
wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52]
wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 | _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}]
wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}]
assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T | _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38]
assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91]
wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42]
wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70]
wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}]
assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}]
assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41]
wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42]
assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}]
assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41]
wire _io_schedule_bits_b_bits_clients_T = ~excluded_client; // @[MSHR.scala:279:28, :289:53]
assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients & _io_schedule_bits_b_bits_clients_T; // @[MSHR.scala:100:17, :289:{51,53}]
assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51]
assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41]
assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41]
assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}]
assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41]
wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42]
wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53]
wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53]
wire _io_schedule_bits_d_bits_param_T_3 = ~(|request_param); // @[Parameters.scala:271:89]
wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53]
wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53]
wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79]
assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41]
wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42]
assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_clients = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 13'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}]
assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41]
wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32]
wire [3:0] evict; // @[MSHR.scala:314:26]
wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32]
wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32]
wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32]
assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32]
wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32]
assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32]
wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26]
wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39]
wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39]
assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39]
wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39]
assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39]
wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76]
wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76]
assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76]
wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76]
assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76]
wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _evict_T_4 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26]
wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32]
assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}]
wire [3:0] before_0; // @[MSHR.scala:314:26]
wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32]
wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26]
wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _before_T_3 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26]
wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11]
assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}]
wire [3:0] after; // @[MSHR.scala:314:26]
wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26]
wire _after_T; // @[MSHR.scala:317:26]
assign _after_T = _GEN_9; // @[MSHR.scala:317:26]
wire _prior_T; // @[MSHR.scala:317:26]
assign _prior_T = _GEN_9; // @[MSHR.scala:317:26]
wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32]
wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26]
wire _after_T_1; // @[MSHR.scala:317:26]
assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26]
wire _prior_T_1; // @[MSHR.scala:317:26]
assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26]
wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32]
wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32]
assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32]
wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32]
assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32]
wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26]
wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39]
wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39]
assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39]
wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39]
assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39]
wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76]
wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76]
assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76]
wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76]
assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76]
wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26]
wire _after_T_3; // @[MSHR.scala:317:26]
assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26]
wire _prior_T_3; // @[MSHR.scala:317:26]
assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26]
assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26]
wire probe_bit = io_sinkc_bits_source_0 == 7'h20; // @[Parameters.scala:46:9]
wire _GEN_15 = probes_done | probe_bit; // @[Parameters.scala:46:9]
wire _last_probe_T; // @[MSHR.scala:459:33]
assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33]
wire _probes_done_T; // @[MSHR.scala:467:32]
assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32]
wire _last_probe_T_1 = ~excluded_client; // @[MSHR.scala:279:28, :289:53, :459:66]
wire _last_probe_T_2 = meta_clients & _last_probe_T_1; // @[MSHR.scala:100:17, :459:{64,66}]
wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}]
wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11]
wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43]
wire _probe_toN_T_2 = _probe_toN_T | _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}]
wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75]
wire probe_toN = _probe_toN_T_2 | _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}]
wire _probes_toN_T = probe_toN & probe_bit; // @[Parameters.scala:46:9]
wire _probes_toN_T_1 = probes_toN | _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}]
wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53]
wire _probes_noT_T_1 = probes_noT | _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}]
wire _w_rprobeackfirst_T = w_rprobeackfirst | last_probe; // @[MSHR.scala:122:33, :459:46, :470:42]
wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55]
wire _w_rprobeacklast_T; // @[MSHR.scala:471:55]
assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55]
wire _w_pprobeacklast_T; // @[MSHR.scala:473:55]
assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55]
wire _w_rprobeacklast_T_1 = w_rprobeacklast | _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}]
wire _w_pprobeackfirst_T = w_pprobeackfirst | last_probe; // @[MSHR.scala:132:33, :459:46, :472:42]
wire _w_pprobeacklast_T_1 = w_pprobeacklast | _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}]
wire _set_pprobeack_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77]
wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 | _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}]
wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}]
wire _w_pprobeack_T = w_pprobeack | set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32]
wire _w_grant_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33]
wire _w_grant_T_1 = _w_grant_T | io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}]
wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35]
wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40]
wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [12:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [2:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_request_prio_0 = io_allocate_valid_0 ? allocate_as_full_prio_0 : request_prio_0; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [6:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [12:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [9:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12]
wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}]
wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13]
wire _new_needT_T_2; // @[Parameters.scala:270:13]
assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13]
wire _new_skipProbe_T_5; // @[Parameters.scala:279:117]
assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117]
wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42]
wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}]
wire _new_needT_T_5 = _new_needT_T_1 | _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33]
wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14]
wire _new_needT_T_6; // @[Parameters.scala:271:14]
assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14]
wire _new_skipProbe_T; // @[Parameters.scala:279:12]
assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12]
wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52]
wire _new_needT_T_8 = _new_needT_T_6 | _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}]
wire _new_needT_T_9 = |new_request_param; // @[Parameters.scala:271:89]
wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}]
wire new_needT = _new_needT_T_5 | _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80]
wire new_clientBit = new_request_source == 7'h20; // @[Parameters.scala:46:9]
wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50]
wire _new_skipProbe_T_2 = _new_skipProbe_T | _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}]
wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87]
wire _new_skipProbe_T_4 = _new_skipProbe_T_2 | _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}]
wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}]
wire new_skipProbe = _new_skipProbe_T_7 & new_clientBit; // @[Parameters.scala:46:9]
wire [3:0] prior; // @[MSHR.scala:314:26]
wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32]
wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26]
wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26]
wire _T_574 = io_directory_valid_0 | _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28] |
Generate the Verilog code corresponding to the following Chisel files.
File Decode.scala:
// See LICENSE.Berkeley for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util.BitPat
import chisel3.util.experimental.decode._
object DecodeLogic
{
// TODO This should be a method on BitPat
private def hasDontCare(bp: BitPat): Boolean = bp.mask.bitCount != bp.width
// Pads BitPats that are safe to pad (no don't cares), errors otherwise
private def padBP(bp: BitPat, width: Int): BitPat = {
if (bp.width == width) bp
else {
require(!hasDontCare(bp), s"Cannot pad '$bp' to '$width' bits because it has don't cares")
val diff = width - bp.width
require(diff > 0, s"Cannot pad '$bp' to '$width' because it is already '${bp.width}' bits wide!")
BitPat(0.U(diff.W)) ## bp
}
}
def apply(addr: UInt, default: BitPat, mapping: Iterable[(BitPat, BitPat)]): UInt =
chisel3.util.experimental.decode.decoder(QMCMinimizer, addr, TruthTable(mapping, default))
def apply(addr: UInt, default: Seq[BitPat], mappingIn: Iterable[(BitPat, Seq[BitPat])]): Seq[UInt] = {
val nElts = default.size
require(mappingIn.forall(_._2.size == nElts),
s"All Seq[BitPat] must be of the same length, got $nElts vs. ${mappingIn.find(_._2.size != nElts).get}"
)
val elementsGrouped = mappingIn.map(_._2).transpose
val elementWidths = elementsGrouped.zip(default).map { case (elts, default) =>
(default :: elts.toList).map(_.getWidth).max
}
val resultWidth = elementWidths.sum
val elementIndices = elementWidths.scan(resultWidth - 1) { case (l, r) => l - r }
// All BitPats that correspond to a given element in the result must have the same width in the
// chisel3 decoder. We will zero pad any BitPats that are too small so long as they dont have
// any don't cares. If there are don't cares, it is an error and the user needs to pad the
// BitPat themselves
val defaultsPadded = default.zip(elementWidths).map { case (bp, w) => padBP(bp, w) }
val mappingInPadded = mappingIn.map { case (in, elts) =>
in -> elts.zip(elementWidths).map { case (bp, w) => padBP(bp, w) }
}
val decoded = apply(addr, defaultsPadded.reduce(_ ## _), mappingInPadded.map { case (in, out) => (in, out.reduce(_ ## _)) })
elementIndices.zip(elementIndices.tail).map { case (msb, lsb) => decoded(msb, lsb + 1) }.toList
}
def apply(addr: UInt, default: Seq[BitPat], mappingIn: List[(UInt, Seq[BitPat])]): Seq[UInt] =
apply(addr, default, mappingIn.map(m => (BitPat(m._1), m._2)).asInstanceOf[Iterable[(BitPat, Seq[BitPat])]])
def apply(addr: UInt, trues: Iterable[UInt], falses: Iterable[UInt]): Bool =
apply(addr, BitPat.dontCare(1), trues.map(BitPat(_) -> BitPat("b1")) ++ falses.map(BitPat(_) -> BitPat("b0"))).asBool
}
File fdiv.scala:
//******************************************************************************
// Copyright (c) 2016 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// FDiv/FSqrt Unit
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v3.exu
import chisel3._
import chisel3.util._
import chisel3.experimental.dataview._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.tile.FPConstants._
import freechips.rocketchip.tile
import boom.v3.common._
import boom.v3.util._
import freechips.rocketchip.tile.HasFPUParameters
import freechips.rocketchip.util.uintToBitPat
/**
* Decoder for FPU divide and square root signals
*/
class UOPCodeFDivDecoder(implicit p: Parameters) extends BoomModule
with HasFPUParameters
{
val io = IO(new Bundle {
val uopc = Input(Bits(UOPC_SZ.W))
val sigs = Output(new tile.FPUCtrlSigs())
})
val N = BitPat("b0")
val Y = BitPat("b1")
val X = BitPat("b?")
val decoder = freechips.rocketchip.rocket.DecodeLogic(io.uopc,
// Note: not all of these signals are used or necessary, but we're
// constrained by the need to fit the rocket.FPU units' ctrl signals.
// swap12 fma
// | swap32 | div
// | | typeTagIn | | sqrt
// ldst | | | typeTagOut | | wflags
// | wen | | | | from_int | | |
// | | ren1 | | | | | to_int | | |
// | | | ren2 | | | | | | fast | | |
// | | | | ren3 | | | | | | | | | |
// | | | | | | | | | | | | | | | |
/* Default */ List(X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X),
Array(
BitPat(uopFDIV_S) -> List(X,X,Y,Y,X, X,X,S,S,X,X,X, X,Y,N,Y),
BitPat(uopFDIV_D) -> List(X,X,Y,Y,X, X,X,D,D,X,X,X, X,Y,N,Y),
BitPat(uopFSQRT_S) -> List(X,X,Y,N,X, X,X,S,S,X,X,X, X,N,Y,Y),
BitPat(uopFSQRT_D) -> List(X,X,Y,N,X, X,X,D,D,X,X,X, X,N,Y,Y)
): Array[(BitPat, List[BitPat])])
val s = io.sigs
val sigs = Seq(s.ldst, s.wen, s.ren1, s.ren2, s.ren3, s.swap12,
s.swap23, s.typeTagIn, s.typeTagOut, s.fromint, s.toint, s.fastpipe, s.fma,
s.div, s.sqrt, s.wflags)
s.vec := false.B
sigs zip decoder map {case(s,d) => s := d}
}
/**
* fdiv/fsqrt is douple-precision. Must upconvert inputs and downconvert outputs
* as necessary. Must wait till killed uop finishes before we're ready again.
* fdiv/fsqrt unit uses an unstable FIFO interface, and thus we must spend a
* cycle buffering up an uop to provide slack between the issue queue and the
* fdiv/fsqrt unit. FDivUnit inherents directly from FunctionalUnit, because
* UnpipelinedFunctionalUnit can only handle 1 inflight uop, whereas FDivUnit
* contains up to 2 inflight uops due to the need to buffer the input as the
* fdiv unit uses an unstable FIFO interface.
* TODO extend UnpipelinedFunctionalUnit to handle a >1 uops inflight.
*
* @param isPipelined is the functional unit pipelined
* @param numStages number of stages for the functional unit
* @param numBypassStages number of bypass stages
* @param dataWidth width of the data out of the functional unit
*/
class FDivSqrtUnit(implicit p: Parameters)
extends FunctionalUnit(
isPipelined = false,
numStages = 1,
numBypassStages = 0,
dataWidth = 65,
needsFcsr = true)
with tile.HasFPUParameters
{
//--------------------------------------
// buffer inputs and upconvert as needed
// provide a one-entry queue to store incoming uops while waiting for the fdiv/fsqrt unit to become available.
val r_buffer_val = RegInit(false.B)
val r_buffer_req = Reg(new FuncUnitReq(dataWidth=65))
val r_buffer_fin = Reg(new tile.FPInput)
val fdiv_decoder = Module(new UOPCodeFDivDecoder)
fdiv_decoder.io.uopc := io.req.bits.uop.uopc
// handle branch kill on queued entry
r_buffer_val := !IsKilledByBranch(io.brupdate, r_buffer_req.uop) && !io.req.bits.kill && r_buffer_val
r_buffer_req.uop.br_mask := GetNewBrMask(io.brupdate, r_buffer_req.uop)
// handle incoming uop, including upconversion as needed, and push back if our input queue is already occupied
io.req.ready := !r_buffer_val
def upconvert(x: UInt) = {
val s2d = Module(new hardfloat.RecFNToRecFN(inExpWidth = 8, inSigWidth = 24, outExpWidth = 11, outSigWidth = 53))
s2d.io.in := x
s2d.io.roundingMode := 0.U
s2d.io.detectTininess := DontCare
s2d.io.out
}
val in1_upconvert = upconvert(unbox(io.req.bits.rs1_data, false.B, Some(tile.FType.S)))
val in2_upconvert = upconvert(unbox(io.req.bits.rs2_data, false.B, Some(tile.FType.S)))
when (io.req.valid && !IsKilledByBranch(io.brupdate, io.req.bits.uop) && !io.req.bits.kill) {
r_buffer_val := true.B
r_buffer_req := io.req.bits
r_buffer_req.uop.br_mask := GetNewBrMask(io.brupdate, io.req.bits.uop)
r_buffer_fin.viewAsSupertype(new tile.FPUCtrlSigs) := fdiv_decoder.io.sigs
r_buffer_fin.rm := Mux(ImmGenRm(io.req.bits.uop.imm_packed) === 7.U, io.fcsr_rm, ImmGenRm(io.req.bits.uop.imm_packed))
r_buffer_fin.typ := 0.U // unused for fdivsqrt
val tag = fdiv_decoder.io.sigs.typeTagIn
r_buffer_fin.in1 := unbox(io.req.bits.rs1_data, tag, Some(tile.FType.D))
r_buffer_fin.in2 := unbox(io.req.bits.rs2_data, tag, Some(tile.FType.D))
when (tag === S) {
r_buffer_fin.in1 := in1_upconvert
r_buffer_fin.in2 := in2_upconvert
}
}
assert (!(r_buffer_val && io.req.valid), "[fdiv] a request is incoming while the buffer is already full.")
//-----------
// fdiv/fsqrt
val divsqrt = Module(new hardfloat.DivSqrtRecF64)
val r_divsqrt_val = RegInit(false.B) // inflight uop?
val r_divsqrt_killed = Reg(Bool()) // has inflight uop been killed?
val r_divsqrt_fin = Reg(new tile.FPInput)
val r_divsqrt_uop = Reg(new MicroOp)
// Need to buffer output until RF writeport is available.
val output_buffer_available = Wire(Bool())
val may_fire_input =
r_buffer_val &&
(r_buffer_fin.div || r_buffer_fin.sqrt) &&
!r_divsqrt_val &&
output_buffer_available
val divsqrt_ready = Mux(divsqrt.io.sqrtOp, divsqrt.io.inReady_sqrt, divsqrt.io.inReady_div)
divsqrt.io.inValid := may_fire_input // must be setup early
divsqrt.io.sqrtOp := r_buffer_fin.sqrt
divsqrt.io.a := r_buffer_fin.in1
divsqrt.io.b := Mux(divsqrt.io.sqrtOp, r_buffer_fin.in1, r_buffer_fin.in2)
divsqrt.io.roundingMode := r_buffer_fin.rm
divsqrt.io.detectTininess := DontCare
r_divsqrt_killed := r_divsqrt_killed || IsKilledByBranch(io.brupdate, r_divsqrt_uop) || io.req.bits.kill
r_divsqrt_uop.br_mask := GetNewBrMask(io.brupdate, r_divsqrt_uop)
when (may_fire_input && divsqrt_ready) {
// Remove entry from the input buffer.
// We don't have time to kill divsqrt request so must track if killed on entry.
r_buffer_val := false.B
r_divsqrt_val := true.B
r_divsqrt_fin := r_buffer_fin
r_divsqrt_uop := r_buffer_req.uop
r_divsqrt_killed := IsKilledByBranch(io.brupdate, r_buffer_req.uop) || io.req.bits.kill
r_divsqrt_uop.br_mask := GetNewBrMask(io.brupdate, r_buffer_req.uop)
}
//-----------------------------------------
// buffer output and down-convert as needed
val r_out_val = RegInit(false.B)
val r_out_uop = Reg(new MicroOp)
val r_out_flags_double = Reg(Bits())
val r_out_wdata_double = Reg(Bits())
output_buffer_available := !r_out_val
r_out_uop.br_mask := GetNewBrMask(io.brupdate, r_out_uop)
when (io.resp.ready || IsKilledByBranch(io.brupdate, r_out_uop) || io.req.bits.kill) {
r_out_val := false.B
}
when (divsqrt.io.outValid_div || divsqrt.io.outValid_sqrt) {
r_divsqrt_val := false.B
r_out_val := !r_divsqrt_killed && !IsKilledByBranch(io.brupdate, r_divsqrt_uop) && !io.req.bits.kill
r_out_uop := r_divsqrt_uop
r_out_uop.br_mask := GetNewBrMask(io.brupdate, r_divsqrt_uop)
r_out_wdata_double := sanitizeNaN(divsqrt.io.out, tile.FType.D)
r_out_flags_double := divsqrt.io.exceptionFlags
assert (r_divsqrt_val, "[fdiv] a response is being generated for no request.")
}
assert (!(r_out_val && (divsqrt.io.outValid_div || divsqrt.io.outValid_sqrt)),
"[fdiv] Buffered output being overwritten by another output from the fdiv/fsqrt unit.")
val downvert_d2s = Module(new hardfloat.RecFNToRecFN(
inExpWidth = 11, inSigWidth = 53, outExpWidth = 8, outSigWidth = 24))
downvert_d2s.io.in := r_out_wdata_double
downvert_d2s.io.roundingMode := r_divsqrt_fin.rm
downvert_d2s.io.detectTininess := DontCare
val out_flags = r_out_flags_double | Mux(r_divsqrt_fin.typeTagIn === S, downvert_d2s.io.exceptionFlags, 0.U)
io.resp.valid := r_out_val && !IsKilledByBranch(io.brupdate, r_out_uop)
io.resp.bits.uop := r_out_uop
io.resp.bits.data :=
Mux(r_divsqrt_fin.typeTagIn === S,
box(downvert_d2s.io.out, false.B),
box(r_out_wdata_double, true.B))
io.resp.bits.fflags.valid := io.resp.valid
io.resp.bits.fflags.bits.uop := r_out_uop
io.resp.bits.fflags.bits.uop.br_mask := GetNewBrMask(io.brupdate, r_out_uop)
io.resp.bits.fflags.bits.flags := out_flags
}
| module UOPCodeFDivDecoder( // @[fdiv.scala:28:7]
input clock, // @[fdiv.scala:28:7]
input reset, // @[fdiv.scala:28:7]
input [6:0] io_uopc, // @[fdiv.scala:31:14]
output io_sigs_ldst, // @[fdiv.scala:31:14]
output io_sigs_wen, // @[fdiv.scala:31:14]
output io_sigs_ren1, // @[fdiv.scala:31:14]
output io_sigs_ren2, // @[fdiv.scala:31:14]
output io_sigs_ren3, // @[fdiv.scala:31:14]
output io_sigs_swap12, // @[fdiv.scala:31:14]
output io_sigs_swap23, // @[fdiv.scala:31:14]
output [1:0] io_sigs_typeTagIn, // @[fdiv.scala:31:14]
output [1:0] io_sigs_typeTagOut, // @[fdiv.scala:31:14]
output io_sigs_fromint, // @[fdiv.scala:31:14]
output io_sigs_toint, // @[fdiv.scala:31:14]
output io_sigs_fastpipe, // @[fdiv.scala:31:14]
output io_sigs_fma, // @[fdiv.scala:31:14]
output io_sigs_div, // @[fdiv.scala:31:14]
output io_sigs_sqrt, // @[fdiv.scala:31:14]
output io_sigs_wflags // @[fdiv.scala:31:14]
);
wire [6:0] io_uopc_0 = io_uopc; // @[fdiv.scala:28:7]
wire _decoder_decoded_orMatrixOutputs_T = 1'h1; // @[pla.scala:114:36]
wire _decoder_decoded_orMatrixOutputs_T_11 = 1'h1; // @[pla.scala:114:36]
wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_lo = 2'h0; // @[pla.scala:102:36]
wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_hi = 2'h0; // @[pla.scala:102:36]
wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi = 2'h0; // @[pla.scala:102:36]
wire io_sigs_vec = 1'h0; // @[fdiv.scala:28:7]
wire [6:0] decoder_decoded_plaInput = io_uopc_0; // @[pla.scala:77:22]
wire decoder_0; // @[Decode.scala:50:77]
wire decoder_1; // @[Decode.scala:50:77]
wire decoder_2; // @[Decode.scala:50:77]
wire decoder_3; // @[Decode.scala:50:77]
wire decoder_4; // @[Decode.scala:50:77]
wire decoder_5; // @[Decode.scala:50:77]
wire decoder_6; // @[Decode.scala:50:77]
wire decoder_9; // @[Decode.scala:50:77]
wire decoder_10; // @[Decode.scala:50:77]
wire decoder_11; // @[Decode.scala:50:77]
wire decoder_12; // @[Decode.scala:50:77]
wire decoder_13; // @[Decode.scala:50:77]
wire decoder_14; // @[Decode.scala:50:77]
wire decoder_15; // @[Decode.scala:50:77]
wire io_sigs_ldst_0; // @[fdiv.scala:28:7]
wire io_sigs_wen_0; // @[fdiv.scala:28:7]
wire io_sigs_ren1_0; // @[fdiv.scala:28:7]
wire io_sigs_ren2_0; // @[fdiv.scala:28:7]
wire io_sigs_ren3_0; // @[fdiv.scala:28:7]
wire io_sigs_swap12_0; // @[fdiv.scala:28:7]
wire io_sigs_swap23_0; // @[fdiv.scala:28:7]
wire [1:0] io_sigs_typeTagIn_0; // @[fdiv.scala:28:7]
wire [1:0] io_sigs_typeTagOut_0; // @[fdiv.scala:28:7]
wire io_sigs_fromint_0; // @[fdiv.scala:28:7]
wire io_sigs_toint_0; // @[fdiv.scala:28:7]
wire io_sigs_fastpipe_0; // @[fdiv.scala:28:7]
wire io_sigs_fma_0; // @[fdiv.scala:28:7]
wire io_sigs_div_0; // @[fdiv.scala:28:7]
wire io_sigs_sqrt_0; // @[fdiv.scala:28:7]
wire io_sigs_wflags_0; // @[fdiv.scala:28:7]
wire [6:0] decoder_decoded_invInputs = ~decoder_decoded_plaInput; // @[pla.scala:77:22, :78:21]
wire [15:0] decoder_decoded_invMatrixOutputs; // @[pla.scala:120:37]
wire [15:0] decoder_decoded; // @[pla.scala:81:23]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0 = decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1 = decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_1 = decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_2 = decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_1 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_2 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_1 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_2 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_3 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_1 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_2 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_3 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_1 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_3 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi = {decoder_decoded_andMatrixOutputs_andMatrixInput_3, decoder_decoded_andMatrixOutputs_andMatrixInput_4}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo = {decoder_decoded_andMatrixOutputs_lo_hi, decoder_decoded_andMatrixOutputs_andMatrixInput_5}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi = {decoder_decoded_andMatrixOutputs_andMatrixInput_0, decoder_decoded_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi = {decoder_decoded_andMatrixOutputs_hi_hi, decoder_decoded_andMatrixOutputs_andMatrixInput_2}; // @[pla.scala:91:29, :98:53]
wire [5:0] _decoder_decoded_andMatrixOutputs_T = {decoder_decoded_andMatrixOutputs_hi, decoder_decoded_andMatrixOutputs_lo}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_3_2 = &_decoder_decoded_andMatrixOutputs_T; // @[pla.scala:98:{53,70}]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_1 = decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_1 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_2 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_1 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_1, decoder_decoded_andMatrixOutputs_andMatrixInput_5_1}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_1 = {decoder_decoded_andMatrixOutputs_lo_hi_1, decoder_decoded_andMatrixOutputs_andMatrixInput_6}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_1, decoder_decoded_andMatrixOutputs_andMatrixInput_3_1}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_1 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_1, decoder_decoded_andMatrixOutputs_andMatrixInput_1_1}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_1 = {decoder_decoded_andMatrixOutputs_hi_hi_1, decoder_decoded_andMatrixOutputs_hi_lo}; // @[pla.scala:98:53]
wire [6:0] _decoder_decoded_andMatrixOutputs_T_1 = {decoder_decoded_andMatrixOutputs_hi_1, decoder_decoded_andMatrixOutputs_lo_1}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_4_2 = &_decoder_decoded_andMatrixOutputs_T_1; // @[pla.scala:98:{53,70}]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_2 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_2 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_2, decoder_decoded_andMatrixOutputs_andMatrixInput_5_2}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_2 = {decoder_decoded_andMatrixOutputs_lo_hi_2, decoder_decoded_andMatrixOutputs_andMatrixInput_6_1}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_1 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_2, decoder_decoded_andMatrixOutputs_andMatrixInput_3_2}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_2 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_2, decoder_decoded_andMatrixOutputs_andMatrixInput_1_2}; // @[pla.scala:90:45, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_2 = {decoder_decoded_andMatrixOutputs_hi_hi_2, decoder_decoded_andMatrixOutputs_hi_lo_1}; // @[pla.scala:98:53]
wire [6:0] _decoder_decoded_andMatrixOutputs_T_2 = {decoder_decoded_andMatrixOutputs_hi_2, decoder_decoded_andMatrixOutputs_lo_2}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_2_2 = &_decoder_decoded_andMatrixOutputs_T_2; // @[pla.scala:98:{53,70}]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_3 = decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_3 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_3, decoder_decoded_andMatrixOutputs_andMatrixInput_3_3}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_3 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_3, decoder_decoded_andMatrixOutputs_andMatrixInput_1_3}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] _decoder_decoded_andMatrixOutputs_T_3 = {decoder_decoded_andMatrixOutputs_hi_3, decoder_decoded_andMatrixOutputs_lo_3}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_0_2 = &_decoder_decoded_andMatrixOutputs_T_3; // @[pla.scala:98:{53,70}]
wire [1:0] _decoder_decoded_orMatrixOutputs_T_1 = {decoder_decoded_andMatrixOutputs_2_2, decoder_decoded_andMatrixOutputs_0_2}; // @[pla.scala:98:70, :114:19]
wire _decoder_decoded_orMatrixOutputs_T_2 = |_decoder_decoded_orMatrixOutputs_T_1; // @[pla.scala:114:{19,36}]
wire [1:0] _GEN = {decoder_decoded_andMatrixOutputs_3_2, decoder_decoded_andMatrixOutputs_4_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] _decoder_decoded_orMatrixOutputs_T_3; // @[pla.scala:114:19]
assign _decoder_decoded_orMatrixOutputs_T_3 = _GEN; // @[pla.scala:114:19]
wire [1:0] _decoder_decoded_orMatrixOutputs_T_9; // @[pla.scala:114:19]
assign _decoder_decoded_orMatrixOutputs_T_9 = _GEN; // @[pla.scala:114:19]
wire _decoder_decoded_orMatrixOutputs_T_4 = |_decoder_decoded_orMatrixOutputs_T_3; // @[pla.scala:114:{19,36}]
wire [1:0] _GEN_0 = {decoder_decoded_andMatrixOutputs_4_2, decoder_decoded_andMatrixOutputs_0_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] _decoder_decoded_orMatrixOutputs_T_5; // @[pla.scala:114:19]
assign _decoder_decoded_orMatrixOutputs_T_5 = _GEN_0; // @[pla.scala:114:19]
wire [1:0] _decoder_decoded_orMatrixOutputs_T_7; // @[pla.scala:114:19]
assign _decoder_decoded_orMatrixOutputs_T_7 = _GEN_0; // @[pla.scala:114:19]
wire _decoder_decoded_orMatrixOutputs_T_6 = |_decoder_decoded_orMatrixOutputs_T_5; // @[pla.scala:114:{19,36}]
wire _decoder_decoded_orMatrixOutputs_T_8 = |_decoder_decoded_orMatrixOutputs_T_7; // @[pla.scala:114:{19,36}]
wire _decoder_decoded_orMatrixOutputs_T_10 = |_decoder_decoded_orMatrixOutputs_T_9; // @[pla.scala:114:{19,36}]
wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_lo = {_decoder_decoded_orMatrixOutputs_T_2, 1'h1}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_hi = {1'h0, _decoder_decoded_orMatrixOutputs_T_4}; // @[pla.scala:102:36, :114:36]
wire [3:0] decoder_decoded_orMatrixOutputs_lo_lo = {decoder_decoded_orMatrixOutputs_lo_lo_hi, decoder_decoded_orMatrixOutputs_lo_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_hi = {_decoder_decoded_orMatrixOutputs_T_6, 1'h0}; // @[pla.scala:102:36, :114:36]
wire [3:0] decoder_decoded_orMatrixOutputs_lo_hi = {decoder_decoded_orMatrixOutputs_lo_hi_hi, 2'h0}; // @[pla.scala:102:36]
wire [7:0] decoder_decoded_orMatrixOutputs_lo = {decoder_decoded_orMatrixOutputs_lo_hi, decoder_decoded_orMatrixOutputs_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_lo = {1'h0, _decoder_decoded_orMatrixOutputs_T_8}; // @[pla.scala:102:36, :114:36]
wire [3:0] decoder_decoded_orMatrixOutputs_hi_lo = {2'h0, decoder_decoded_orMatrixOutputs_hi_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_lo = {1'h1, _decoder_decoded_orMatrixOutputs_T_10}; // @[pla.scala:102:36, :114:36]
wire [3:0] decoder_decoded_orMatrixOutputs_hi_hi = {2'h0, decoder_decoded_orMatrixOutputs_hi_hi_lo}; // @[pla.scala:102:36]
wire [7:0] decoder_decoded_orMatrixOutputs_hi = {decoder_decoded_orMatrixOutputs_hi_hi, decoder_decoded_orMatrixOutputs_hi_lo}; // @[pla.scala:102:36]
wire [15:0] decoder_decoded_orMatrixOutputs = {decoder_decoded_orMatrixOutputs_hi, decoder_decoded_orMatrixOutputs_lo}; // @[pla.scala:102:36]
wire _decoder_decoded_invMatrixOutputs_T = decoder_decoded_orMatrixOutputs[0]; // @[pla.scala:102:36, :124:31]
wire _decoder_decoded_invMatrixOutputs_T_1 = decoder_decoded_orMatrixOutputs[1]; // @[pla.scala:102:36, :124:31]
wire _decoder_decoded_invMatrixOutputs_T_2 = decoder_decoded_orMatrixOutputs[2]; // @[pla.scala:102:36, :124:31]
wire _decoder_decoded_invMatrixOutputs_T_3 = decoder_decoded_orMatrixOutputs[3]; // @[pla.scala:102:36, :124:31]
wire _decoder_decoded_invMatrixOutputs_T_4 = decoder_decoded_orMatrixOutputs[4]; // @[pla.scala:102:36, :124:31]
wire _decoder_decoded_invMatrixOutputs_T_5 = decoder_decoded_orMatrixOutputs[5]; // @[pla.scala:102:36, :124:31]
wire _decoder_decoded_invMatrixOutputs_T_6 = decoder_decoded_orMatrixOutputs[6]; // @[pla.scala:102:36, :124:31]
wire _decoder_decoded_invMatrixOutputs_T_7 = decoder_decoded_orMatrixOutputs[7]; // @[pla.scala:102:36, :124:31]
wire _decoder_decoded_invMatrixOutputs_T_8 = decoder_decoded_orMatrixOutputs[8]; // @[pla.scala:102:36, :124:31]
wire _decoder_decoded_invMatrixOutputs_T_9 = decoder_decoded_orMatrixOutputs[9]; // @[pla.scala:102:36, :124:31]
wire _decoder_decoded_invMatrixOutputs_T_10 = decoder_decoded_orMatrixOutputs[10]; // @[pla.scala:102:36, :124:31]
wire _decoder_decoded_invMatrixOutputs_T_11 = decoder_decoded_orMatrixOutputs[11]; // @[pla.scala:102:36, :124:31]
wire _decoder_decoded_invMatrixOutputs_T_12 = decoder_decoded_orMatrixOutputs[12]; // @[pla.scala:102:36, :124:31]
wire _decoder_decoded_invMatrixOutputs_T_13 = decoder_decoded_orMatrixOutputs[13]; // @[pla.scala:102:36, :124:31]
wire _decoder_decoded_invMatrixOutputs_T_14 = decoder_decoded_orMatrixOutputs[14]; // @[pla.scala:102:36, :124:31]
wire _decoder_decoded_invMatrixOutputs_T_15 = decoder_decoded_orMatrixOutputs[15]; // @[pla.scala:102:36, :124:31]
wire [1:0] decoder_decoded_invMatrixOutputs_lo_lo_lo = {_decoder_decoded_invMatrixOutputs_T_1, _decoder_decoded_invMatrixOutputs_T}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoder_decoded_invMatrixOutputs_lo_lo_hi = {_decoder_decoded_invMatrixOutputs_T_3, _decoder_decoded_invMatrixOutputs_T_2}; // @[pla.scala:120:37, :124:31]
wire [3:0] decoder_decoded_invMatrixOutputs_lo_lo = {decoder_decoded_invMatrixOutputs_lo_lo_hi, decoder_decoded_invMatrixOutputs_lo_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoder_decoded_invMatrixOutputs_lo_hi_lo = {_decoder_decoded_invMatrixOutputs_T_5, _decoder_decoded_invMatrixOutputs_T_4}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoder_decoded_invMatrixOutputs_lo_hi_hi = {_decoder_decoded_invMatrixOutputs_T_7, _decoder_decoded_invMatrixOutputs_T_6}; // @[pla.scala:120:37, :124:31]
wire [3:0] decoder_decoded_invMatrixOutputs_lo_hi = {decoder_decoded_invMatrixOutputs_lo_hi_hi, decoder_decoded_invMatrixOutputs_lo_hi_lo}; // @[pla.scala:120:37]
wire [7:0] decoder_decoded_invMatrixOutputs_lo = {decoder_decoded_invMatrixOutputs_lo_hi, decoder_decoded_invMatrixOutputs_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoder_decoded_invMatrixOutputs_hi_lo_lo = {_decoder_decoded_invMatrixOutputs_T_9, _decoder_decoded_invMatrixOutputs_T_8}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoder_decoded_invMatrixOutputs_hi_lo_hi = {_decoder_decoded_invMatrixOutputs_T_11, _decoder_decoded_invMatrixOutputs_T_10}; // @[pla.scala:120:37, :124:31]
wire [3:0] decoder_decoded_invMatrixOutputs_hi_lo = {decoder_decoded_invMatrixOutputs_hi_lo_hi, decoder_decoded_invMatrixOutputs_hi_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoder_decoded_invMatrixOutputs_hi_hi_lo = {_decoder_decoded_invMatrixOutputs_T_13, _decoder_decoded_invMatrixOutputs_T_12}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoder_decoded_invMatrixOutputs_hi_hi_hi = {_decoder_decoded_invMatrixOutputs_T_15, _decoder_decoded_invMatrixOutputs_T_14}; // @[pla.scala:120:37, :124:31]
wire [3:0] decoder_decoded_invMatrixOutputs_hi_hi = {decoder_decoded_invMatrixOutputs_hi_hi_hi, decoder_decoded_invMatrixOutputs_hi_hi_lo}; // @[pla.scala:120:37]
wire [7:0] decoder_decoded_invMatrixOutputs_hi = {decoder_decoded_invMatrixOutputs_hi_hi, decoder_decoded_invMatrixOutputs_hi_lo}; // @[pla.scala:120:37]
assign decoder_decoded_invMatrixOutputs = {decoder_decoded_invMatrixOutputs_hi, decoder_decoded_invMatrixOutputs_lo}; // @[pla.scala:120:37]
assign decoder_decoded = decoder_decoded_invMatrixOutputs; // @[pla.scala:81:23, :120:37]
assign decoder_0 = decoder_decoded[15]; // @[pla.scala:81:23]
assign io_sigs_ldst_0 = decoder_0; // @[Decode.scala:50:77]
assign decoder_1 = decoder_decoded[14]; // @[pla.scala:81:23]
assign io_sigs_wen_0 = decoder_1; // @[Decode.scala:50:77]
assign decoder_2 = decoder_decoded[13]; // @[pla.scala:81:23]
assign io_sigs_ren1_0 = decoder_2; // @[Decode.scala:50:77]
assign decoder_3 = decoder_decoded[12]; // @[pla.scala:81:23]
assign io_sigs_ren2_0 = decoder_3; // @[Decode.scala:50:77]
assign decoder_4 = decoder_decoded[11]; // @[pla.scala:81:23]
assign io_sigs_ren3_0 = decoder_4; // @[Decode.scala:50:77]
assign decoder_5 = decoder_decoded[10]; // @[pla.scala:81:23]
assign io_sigs_swap12_0 = decoder_5; // @[Decode.scala:50:77]
assign decoder_6 = decoder_decoded[9]; // @[pla.scala:81:23]
assign io_sigs_swap23_0 = decoder_6; // @[Decode.scala:50:77]
wire decoder_7 = decoder_decoded[8]; // @[pla.scala:81:23]
wire decoder_8 = decoder_decoded[7]; // @[pla.scala:81:23]
assign decoder_9 = decoder_decoded[6]; // @[pla.scala:81:23]
assign io_sigs_fromint_0 = decoder_9; // @[Decode.scala:50:77]
assign decoder_10 = decoder_decoded[5]; // @[pla.scala:81:23]
assign io_sigs_toint_0 = decoder_10; // @[Decode.scala:50:77]
assign decoder_11 = decoder_decoded[4]; // @[pla.scala:81:23]
assign io_sigs_fastpipe_0 = decoder_11; // @[Decode.scala:50:77]
assign decoder_12 = decoder_decoded[3]; // @[pla.scala:81:23]
assign io_sigs_fma_0 = decoder_12; // @[Decode.scala:50:77]
assign decoder_13 = decoder_decoded[2]; // @[pla.scala:81:23]
assign io_sigs_div_0 = decoder_13; // @[Decode.scala:50:77]
assign decoder_14 = decoder_decoded[1]; // @[pla.scala:81:23]
assign io_sigs_sqrt_0 = decoder_14; // @[Decode.scala:50:77]
assign decoder_15 = decoder_decoded[0]; // @[pla.scala:81:23]
assign io_sigs_wflags_0 = decoder_15; // @[Decode.scala:50:77]
assign io_sigs_typeTagIn_0 = {1'h0, decoder_7}; // @[Decode.scala:50:77]
assign io_sigs_typeTagOut_0 = {1'h0, decoder_8}; // @[Decode.scala:50:77]
assign io_sigs_ldst = io_sigs_ldst_0; // @[fdiv.scala:28:7]
assign io_sigs_wen = io_sigs_wen_0; // @[fdiv.scala:28:7]
assign io_sigs_ren1 = io_sigs_ren1_0; // @[fdiv.scala:28:7]
assign io_sigs_ren2 = io_sigs_ren2_0; // @[fdiv.scala:28:7]
assign io_sigs_ren3 = io_sigs_ren3_0; // @[fdiv.scala:28:7]
assign io_sigs_swap12 = io_sigs_swap12_0; // @[fdiv.scala:28:7]
assign io_sigs_swap23 = io_sigs_swap23_0; // @[fdiv.scala:28:7]
assign io_sigs_typeTagIn = io_sigs_typeTagIn_0; // @[fdiv.scala:28:7]
assign io_sigs_typeTagOut = io_sigs_typeTagOut_0; // @[fdiv.scala:28:7]
assign io_sigs_fromint = io_sigs_fromint_0; // @[fdiv.scala:28:7]
assign io_sigs_toint = io_sigs_toint_0; // @[fdiv.scala:28:7]
assign io_sigs_fastpipe = io_sigs_fastpipe_0; // @[fdiv.scala:28:7]
assign io_sigs_fma = io_sigs_fma_0; // @[fdiv.scala:28:7]
assign io_sigs_div = io_sigs_div_0; // @[fdiv.scala:28:7]
assign io_sigs_sqrt = io_sigs_sqrt_0; // @[fdiv.scala:28:7]
assign io_sigs_wflags = io_sigs_wflags_0; // @[fdiv.scala:28:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Tile.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
import Util._
/**
* A Tile is a purely combinational 2D array of passThrough PEs.
* a, b, s, and in_propag are broadcast across the entire array and are passed through to the Tile's outputs
* @param width The data width of each PE in bits
* @param rows Number of PEs on each row
* @param columns Number of PEs on each column
*/
class Tile[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, tree_reduction: Boolean, max_simultaneous_matmuls: Int, val rows: Int, val columns: Int)(implicit ev: Arithmetic[T]) extends Module {
val io = IO(new Bundle {
val in_a = Input(Vec(rows, inputType))
val in_b = Input(Vec(columns, outputType)) // This is the output of the tile next to it
val in_d = Input(Vec(columns, outputType))
val in_control = Input(Vec(columns, new PEControl(accType)))
val in_id = Input(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W)))
val in_last = Input(Vec(columns, Bool()))
val out_a = Output(Vec(rows, inputType))
val out_c = Output(Vec(columns, outputType))
val out_b = Output(Vec(columns, outputType))
val out_control = Output(Vec(columns, new PEControl(accType)))
val out_id = Output(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W)))
val out_last = Output(Vec(columns, Bool()))
val in_valid = Input(Vec(columns, Bool()))
val out_valid = Output(Vec(columns, Bool()))
val bad_dataflow = Output(Bool())
})
import ev._
val tile = Seq.fill(rows, columns)(Module(new PE(inputType, outputType, accType, df, max_simultaneous_matmuls)))
val tileT = tile.transpose
// TODO: abstract hori/vert broadcast, all these connections look the same
// Broadcast 'a' horizontally across the Tile
for (r <- 0 until rows) {
tile(r).foldLeft(io.in_a(r)) {
case (in_a, pe) =>
pe.io.in_a := in_a
pe.io.out_a
}
}
// Broadcast 'b' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_b(c)) {
case (in_b, pe) =>
pe.io.in_b := (if (tree_reduction) in_b.zero else in_b)
pe.io.out_b
}
}
// Broadcast 'd' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_d(c)) {
case (in_d, pe) =>
pe.io.in_d := in_d
pe.io.out_c
}
}
// Broadcast 'control' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_control(c)) {
case (in_ctrl, pe) =>
pe.io.in_control := in_ctrl
pe.io.out_control
}
}
// Broadcast 'garbage' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_valid(c)) {
case (v, pe) =>
pe.io.in_valid := v
pe.io.out_valid
}
}
// Broadcast 'id' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_id(c)) {
case (id, pe) =>
pe.io.in_id := id
pe.io.out_id
}
}
// Broadcast 'last' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_last(c)) {
case (last, pe) =>
pe.io.in_last := last
pe.io.out_last
}
}
// Drive the Tile's bottom IO
for (c <- 0 until columns) {
io.out_c(c) := tile(rows-1)(c).io.out_c
io.out_control(c) := tile(rows-1)(c).io.out_control
io.out_id(c) := tile(rows-1)(c).io.out_id
io.out_last(c) := tile(rows-1)(c).io.out_last
io.out_valid(c) := tile(rows-1)(c).io.out_valid
io.out_b(c) := {
if (tree_reduction) {
val prods = tileT(c).map(_.io.out_b)
accumulateTree(prods :+ io.in_b(c))
} else {
tile(rows - 1)(c).io.out_b
}
}
}
io.bad_dataflow := tile.map(_.map(_.io.bad_dataflow).reduce(_||_)).reduce(_||_)
// Drive the Tile's right IO
for (r <- 0 until rows) {
io.out_a(r) := tile(r)(columns-1).io.out_a
}
}
| module Tile_241( // @[Tile.scala:16:7]
input clock, // @[Tile.scala:16:7]
input reset, // @[Tile.scala:16:7]
input [7:0] io_in_a_0, // @[Tile.scala:17:14]
input [19:0] io_in_b_0, // @[Tile.scala:17:14]
input [19:0] io_in_d_0, // @[Tile.scala:17:14]
input io_in_control_0_dataflow, // @[Tile.scala:17:14]
input io_in_control_0_propagate, // @[Tile.scala:17:14]
input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14]
input [2:0] io_in_id_0, // @[Tile.scala:17:14]
input io_in_last_0, // @[Tile.scala:17:14]
output [7:0] io_out_a_0, // @[Tile.scala:17:14]
output [19:0] io_out_c_0, // @[Tile.scala:17:14]
output [19:0] io_out_b_0, // @[Tile.scala:17:14]
output io_out_control_0_dataflow, // @[Tile.scala:17:14]
output io_out_control_0_propagate, // @[Tile.scala:17:14]
output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14]
output [2:0] io_out_id_0, // @[Tile.scala:17:14]
output io_out_last_0, // @[Tile.scala:17:14]
input io_in_valid_0, // @[Tile.scala:17:14]
output io_out_valid_0, // @[Tile.scala:17:14]
output io_bad_dataflow // @[Tile.scala:17:14]
);
wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7]
wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7]
wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7]
wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7]
wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7]
wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7]
wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7]
wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7]
wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7]
wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7]
wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
wire io_out_control_0_propagate_0; // @[Tile.scala:16:7]
wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7]
wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7]
wire io_out_last_0_0; // @[Tile.scala:16:7]
wire io_out_valid_0_0; // @[Tile.scala:16:7]
wire io_bad_dataflow_0; // @[Tile.scala:16:7]
PE_497 tile_0_0 ( // @[Tile.scala:42:44]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0_0), // @[Tile.scala:16:7]
.io_in_b (io_in_b_0_0), // @[Tile.scala:16:7]
.io_in_d (io_in_d_0_0), // @[Tile.scala:16:7]
.io_out_a (io_out_a_0_0),
.io_out_b (io_out_b_0_0),
.io_out_c (io_out_c_0_0),
.io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7]
.io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7]
.io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7]
.io_out_control_dataflow (io_out_control_0_dataflow_0),
.io_out_control_propagate (io_out_control_0_propagate_0),
.io_out_control_shift (io_out_control_0_shift_0),
.io_in_id (io_in_id_0_0), // @[Tile.scala:16:7]
.io_out_id (io_out_id_0_0),
.io_in_last (io_in_last_0_0), // @[Tile.scala:16:7]
.io_out_last (io_out_last_0_0),
.io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7]
.io_out_valid (io_out_valid_0_0),
.io_bad_dataflow (io_bad_dataflow_0)
); // @[Tile.scala:42:44]
assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7]
assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7]
assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7]
assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7]
assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7]
assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7]
assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7]
assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7]
assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File OutputUnit.scala:
package constellation.router
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import constellation.channel._
import constellation.routing.{FlowRoutingBundle}
import constellation.noc.{HasNoCParams}
class OutputCreditAlloc extends Bundle {
val alloc = Bool()
val tail = Bool()
}
class OutputChannelStatus(implicit val p: Parameters) extends Bundle with HasNoCParams {
val occupied = Bool()
def available = !occupied
val flow = new FlowRoutingBundle
}
class OutputChannelAlloc(implicit val p: Parameters) extends Bundle with HasNoCParams {
val alloc = Bool()
val flow = new FlowRoutingBundle
}
class AbstractOutputUnitIO(
val inParams: Seq[ChannelParams],
val ingressParams: Seq[IngressChannelParams],
val cParam: BaseChannelParams
)(implicit val p: Parameters) extends Bundle with HasRouterInputParams {
val nodeId = cParam.srcId
val nVirtualChannels = cParam.nVirtualChannels
val in = Flipped(Vec(cParam.srcSpeedup, Valid(new Flit(cParam.payloadBits))))
val credit_available = Output(Vec(nVirtualChannels, Bool()))
val channel_status = Output(Vec(nVirtualChannels, new OutputChannelStatus))
val allocs = Input(Vec(nVirtualChannels, new OutputChannelAlloc))
val credit_alloc = Input(Vec(nVirtualChannels, new OutputCreditAlloc))
}
abstract class AbstractOutputUnit(
val inParams: Seq[ChannelParams],
val ingressParams: Seq[IngressChannelParams],
val cParam: BaseChannelParams
)(implicit val p: Parameters) extends Module with HasRouterInputParams with HasNoCParams {
val nodeId = cParam.srcId
def io: AbstractOutputUnitIO
}
class OutputUnit(inParams: Seq[ChannelParams], ingressParams: Seq[IngressChannelParams], cParam: ChannelParams)
(implicit p: Parameters) extends AbstractOutputUnit(inParams, ingressParams, cParam)(p) {
class OutputUnitIO extends AbstractOutputUnitIO(inParams, ingressParams, cParam) {
val out = new Channel(cParam.asInstanceOf[ChannelParams])
}
val io = IO(new OutputUnitIO)
class OutputState(val bufferSize: Int) extends Bundle {
val occupied = Bool()
val c = UInt(log2Up(1+bufferSize).W)
val flow = new FlowRoutingBundle
}
val states = Reg(MixedVec(cParam.virtualChannelParams.map { u => new OutputState(u.bufferSize) }))
(states zip io.channel_status).map { case (s,a) =>
a.occupied := s.occupied
a.flow := s.flow
}
io.out.flit := io.in
states.zipWithIndex.map { case (s,i) => if (cParam.virtualChannelParams(i).traversable) {
when (io.out.vc_free(i)) {
assert(s.occupied)
s.occupied := false.B
}
} }
(states zip io.allocs).zipWithIndex.map { case ((s,a),i) => if (cParam.virtualChannelParams(i).traversable) {
when (a.alloc) {
s.occupied := true.B
s.flow := a.flow
}
} }
(io.credit_available zip states).zipWithIndex.map { case ((c,s),i) =>
c := s.c =/= 0.U //|| (io.out.credit_return.valid && io.out.credit_return.bits === i.U)
}
states.zipWithIndex.map { case (s,i) =>
val free = io.out.credit_return(i)
val alloc = io.credit_alloc(i).alloc
if (cParam.virtualChannelParams(i).traversable) {
s.c := s.c +& free - alloc
}
}
when (reset.asBool) {
states.foreach(_.occupied := false.B)
states.foreach(s => s.c := s.bufferSize.U)
}
}
| module OutputUnit_19( // @[OutputUnit.scala:52:7]
input clock, // @[OutputUnit.scala:52:7]
input reset, // @[OutputUnit.scala:52:7]
input io_in_0_valid, // @[OutputUnit.scala:58:14]
input io_in_0_bits_head, // @[OutputUnit.scala:58:14]
input io_in_0_bits_tail, // @[OutputUnit.scala:58:14]
input [72:0] io_in_0_bits_payload, // @[OutputUnit.scala:58:14]
input [3:0] io_in_0_bits_flow_vnet_id, // @[OutputUnit.scala:58:14]
input [5:0] io_in_0_bits_flow_ingress_node, // @[OutputUnit.scala:58:14]
input [2:0] io_in_0_bits_flow_ingress_node_id, // @[OutputUnit.scala:58:14]
input [5:0] io_in_0_bits_flow_egress_node, // @[OutputUnit.scala:58:14]
input [2:0] io_in_0_bits_flow_egress_node_id, // @[OutputUnit.scala:58:14]
input [4:0] io_in_0_bits_virt_channel_id, // @[OutputUnit.scala:58:14]
output io_credit_available_2, // @[OutputUnit.scala:58:14]
output io_credit_available_3, // @[OutputUnit.scala:58:14]
output io_credit_available_10, // @[OutputUnit.scala:58:14]
output io_credit_available_11, // @[OutputUnit.scala:58:14]
output io_credit_available_12, // @[OutputUnit.scala:58:14]
output io_credit_available_13, // @[OutputUnit.scala:58:14]
output io_credit_available_14, // @[OutputUnit.scala:58:14]
output io_credit_available_15, // @[OutputUnit.scala:58:14]
output io_credit_available_16, // @[OutputUnit.scala:58:14]
output io_credit_available_17, // @[OutputUnit.scala:58:14]
output io_credit_available_18, // @[OutputUnit.scala:58:14]
output io_credit_available_19, // @[OutputUnit.scala:58:14]
output io_credit_available_20, // @[OutputUnit.scala:58:14]
output io_credit_available_21, // @[OutputUnit.scala:58:14]
output io_channel_status_2_occupied, // @[OutputUnit.scala:58:14]
output io_channel_status_3_occupied, // @[OutputUnit.scala:58:14]
output io_channel_status_10_occupied, // @[OutputUnit.scala:58:14]
output io_channel_status_11_occupied, // @[OutputUnit.scala:58:14]
output io_channel_status_12_occupied, // @[OutputUnit.scala:58:14]
output io_channel_status_13_occupied, // @[OutputUnit.scala:58:14]
output io_channel_status_14_occupied, // @[OutputUnit.scala:58:14]
output io_channel_status_15_occupied, // @[OutputUnit.scala:58:14]
output io_channel_status_16_occupied, // @[OutputUnit.scala:58:14]
output io_channel_status_17_occupied, // @[OutputUnit.scala:58:14]
output io_channel_status_18_occupied, // @[OutputUnit.scala:58:14]
output io_channel_status_19_occupied, // @[OutputUnit.scala:58:14]
output io_channel_status_20_occupied, // @[OutputUnit.scala:58:14]
output io_channel_status_21_occupied, // @[OutputUnit.scala:58:14]
input io_allocs_2_alloc, // @[OutputUnit.scala:58:14]
input io_allocs_3_alloc, // @[OutputUnit.scala:58:14]
input io_allocs_10_alloc, // @[OutputUnit.scala:58:14]
input io_allocs_11_alloc, // @[OutputUnit.scala:58:14]
input io_allocs_12_alloc, // @[OutputUnit.scala:58:14]
input io_allocs_13_alloc, // @[OutputUnit.scala:58:14]
input io_allocs_14_alloc, // @[OutputUnit.scala:58:14]
input io_allocs_15_alloc, // @[OutputUnit.scala:58:14]
input io_allocs_16_alloc, // @[OutputUnit.scala:58:14]
input io_allocs_17_alloc, // @[OutputUnit.scala:58:14]
input io_allocs_18_alloc, // @[OutputUnit.scala:58:14]
input io_allocs_19_alloc, // @[OutputUnit.scala:58:14]
input io_allocs_20_alloc, // @[OutputUnit.scala:58:14]
input io_allocs_21_alloc, // @[OutputUnit.scala:58:14]
input io_credit_alloc_2_alloc, // @[OutputUnit.scala:58:14]
input io_credit_alloc_3_alloc, // @[OutputUnit.scala:58:14]
input io_credit_alloc_10_alloc, // @[OutputUnit.scala:58:14]
input io_credit_alloc_11_alloc, // @[OutputUnit.scala:58:14]
input io_credit_alloc_12_alloc, // @[OutputUnit.scala:58:14]
input io_credit_alloc_13_alloc, // @[OutputUnit.scala:58:14]
input io_credit_alloc_14_alloc, // @[OutputUnit.scala:58:14]
input io_credit_alloc_15_alloc, // @[OutputUnit.scala:58:14]
input io_credit_alloc_16_alloc, // @[OutputUnit.scala:58:14]
input io_credit_alloc_17_alloc, // @[OutputUnit.scala:58:14]
input io_credit_alloc_18_alloc, // @[OutputUnit.scala:58:14]
input io_credit_alloc_19_alloc, // @[OutputUnit.scala:58:14]
input io_credit_alloc_20_alloc, // @[OutputUnit.scala:58:14]
input io_credit_alloc_21_alloc, // @[OutputUnit.scala:58:14]
output io_out_flit_0_valid, // @[OutputUnit.scala:58:14]
output io_out_flit_0_bits_head, // @[OutputUnit.scala:58:14]
output io_out_flit_0_bits_tail, // @[OutputUnit.scala:58:14]
output [72:0] io_out_flit_0_bits_payload, // @[OutputUnit.scala:58:14]
output [3:0] io_out_flit_0_bits_flow_vnet_id, // @[OutputUnit.scala:58:14]
output [5:0] io_out_flit_0_bits_flow_ingress_node, // @[OutputUnit.scala:58:14]
output [2:0] io_out_flit_0_bits_flow_ingress_node_id, // @[OutputUnit.scala:58:14]
output [5:0] io_out_flit_0_bits_flow_egress_node, // @[OutputUnit.scala:58:14]
output [2:0] io_out_flit_0_bits_flow_egress_node_id, // @[OutputUnit.scala:58:14]
output [4:0] io_out_flit_0_bits_virt_channel_id, // @[OutputUnit.scala:58:14]
input [21:0] io_out_credit_return, // @[OutputUnit.scala:58:14]
input [21:0] io_out_vc_free // @[OutputUnit.scala:58:14]
);
reg states_21_occupied; // @[OutputUnit.scala:66:19]
reg [2:0] states_21_c; // @[OutputUnit.scala:66:19]
reg states_20_occupied; // @[OutputUnit.scala:66:19]
reg [2:0] states_20_c; // @[OutputUnit.scala:66:19]
reg states_19_occupied; // @[OutputUnit.scala:66:19]
reg [2:0] states_19_c; // @[OutputUnit.scala:66:19]
reg states_18_occupied; // @[OutputUnit.scala:66:19]
reg [2:0] states_18_c; // @[OutputUnit.scala:66:19]
reg states_17_occupied; // @[OutputUnit.scala:66:19]
reg [2:0] states_17_c; // @[OutputUnit.scala:66:19]
reg states_16_occupied; // @[OutputUnit.scala:66:19]
reg [2:0] states_16_c; // @[OutputUnit.scala:66:19]
reg states_15_occupied; // @[OutputUnit.scala:66:19]
reg [2:0] states_15_c; // @[OutputUnit.scala:66:19]
reg states_14_occupied; // @[OutputUnit.scala:66:19]
reg [2:0] states_14_c; // @[OutputUnit.scala:66:19]
reg states_13_occupied; // @[OutputUnit.scala:66:19]
reg [2:0] states_13_c; // @[OutputUnit.scala:66:19]
reg states_12_occupied; // @[OutputUnit.scala:66:19]
reg [2:0] states_12_c; // @[OutputUnit.scala:66:19]
reg states_11_occupied; // @[OutputUnit.scala:66:19]
reg [2:0] states_11_c; // @[OutputUnit.scala:66:19]
reg states_10_occupied; // @[OutputUnit.scala:66:19]
reg [2:0] states_10_c; // @[OutputUnit.scala:66:19]
reg states_3_occupied; // @[OutputUnit.scala:66:19]
reg [2:0] states_3_c; // @[OutputUnit.scala:66:19]
reg states_2_occupied; // @[OutputUnit.scala:66:19]
reg [2:0] states_2_c; // @[OutputUnit.scala:66:19] |
Generate the Verilog code corresponding to the following Chisel files.
File Transposer.scala:
package gemmini
import chisel3._
import chisel3.util._
import Util._
trait Transposer[T <: Data] extends Module {
def dim: Int
def dataType: T
val io = IO(new Bundle {
val inRow = Flipped(Decoupled(Vec(dim, dataType)))
val outCol = Decoupled(Vec(dim, dataType))
})
}
class PipelinedTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] {
require(isPow2(dim))
val regArray = Seq.fill(dim, dim)(Reg(dataType))
val regArrayT = regArray.transpose
val sMoveUp :: sMoveLeft :: Nil = Enum(2)
val state = RegInit(sMoveUp)
val leftCounter = RegInit(0.U(log2Ceil(dim+1).W)) //(io.inRow.fire && state === sMoveLeft, dim+1)
val upCounter = RegInit(0.U(log2Ceil(dim+1).W)) //Counter(io.inRow.fire && state === sMoveUp, dim+1)
io.outCol.valid := 0.U
io.inRow.ready := 0.U
switch(state) {
is(sMoveUp) {
io.inRow.ready := upCounter <= dim.U
io.outCol.valid := leftCounter > 0.U
when(io.inRow.fire) {
upCounter := upCounter + 1.U
}
when(upCounter === (dim-1).U) {
state := sMoveLeft
leftCounter := 0.U
}
when(io.outCol.fire) {
leftCounter := leftCounter - 1.U
}
}
is(sMoveLeft) {
io.inRow.ready := leftCounter <= dim.U // TODO: this is naive
io.outCol.valid := upCounter > 0.U
when(leftCounter === (dim-1).U) {
state := sMoveUp
}
when(io.inRow.fire) {
leftCounter := leftCounter + 1.U
upCounter := 0.U
}
when(io.outCol.fire) {
upCounter := upCounter - 1.U
}
}
}
// Propagate input from bottom row to top row systolically in the move up phase
// TODO: need to iterate over columns to connect Chisel values of type T
// Should be able to operate directly on the Vec, but Seq and Vec don't mix (try Array?)
for (colIdx <- 0 until dim) {
regArray.foldRight(io.inRow.bits(colIdx)) {
case (regRow, prevReg) =>
when (state === sMoveUp) {
regRow(colIdx) := prevReg
}
regRow(colIdx)
}
}
// Propagate input from right side to left side systolically in the move left phase
for (rowIdx <- 0 until dim) {
regArrayT.foldRight(io.inRow.bits(rowIdx)) {
case (regCol, prevReg) =>
when (state === sMoveLeft) {
regCol(rowIdx) := prevReg
}
regCol(rowIdx)
}
}
// Pull from the left side or the top side based on the state
for (idx <- 0 until dim) {
when (state === sMoveUp) {
io.outCol.bits(idx) := regArray(0)(idx)
}.elsewhen(state === sMoveLeft) {
io.outCol.bits(idx) := regArrayT(0)(idx)
}.otherwise {
io.outCol.bits(idx) := DontCare
}
}
}
class AlwaysOutTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] {
require(isPow2(dim))
val LEFT_DIR = 0.U(1.W)
val UP_DIR = 1.U(1.W)
class PE extends Module {
val io = IO(new Bundle {
val inR = Input(dataType)
val inD = Input(dataType)
val outL = Output(dataType)
val outU = Output(dataType)
val dir = Input(UInt(1.W))
val en = Input(Bool())
})
val reg = RegEnable(Mux(io.dir === LEFT_DIR, io.inR, io.inD), io.en)
io.outU := reg
io.outL := reg
}
val pes = Seq.fill(dim,dim)(Module(new PE))
val counter = RegInit(0.U((log2Ceil(dim) max 1).W)) // TODO replace this with a standard Chisel counter
val dir = RegInit(LEFT_DIR)
// Wire up horizontal signals
for (row <- 0 until dim; col <- 0 until dim) {
val right_in = if (col == dim-1) io.inRow.bits(row) else pes(row)(col+1).io.outL
pes(row)(col).io.inR := right_in
}
// Wire up vertical signals
for (row <- 0 until dim; col <- 0 until dim) {
val down_in = if (row == dim-1) io.inRow.bits(col) else pes(row+1)(col).io.outU
pes(row)(col).io.inD := down_in
}
// Wire up global signals
pes.flatten.foreach(_.io.dir := dir)
pes.flatten.foreach(_.io.en := io.inRow.fire)
io.outCol.valid := true.B
io.inRow.ready := true.B
val left_out = VecInit(pes.transpose.head.map(_.io.outL))
val up_out = VecInit(pes.head.map(_.io.outU))
io.outCol.bits := Mux(dir === LEFT_DIR, left_out, up_out)
when (io.inRow.fire) {
counter := wrappingAdd(counter, 1.U, dim)
}
when (counter === (dim-1).U && io.inRow.fire) {
dir := ~dir
}
}
class NaiveTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] {
val regArray = Seq.fill(dim, dim)(Reg(dataType))
val regArrayT = regArray.transpose
// state = 0 => filling regArray row-wise, state = 1 => draining regArray column-wise
val state = RegInit(0.U(1.W))
val countInc = io.inRow.fire || io.outCol.fire
val (countValue, countWrap) = Counter(countInc, dim)
io.inRow.ready := state === 0.U
io.outCol.valid := state === 1.U
for (i <- 0 until dim) {
for (j <- 0 until dim) {
when(countValue === i.U && io.inRow.fire) {
regArray(i)(j) := io.inRow.bits(j)
}
}
}
for (i <- 0 until dim) {
io.outCol.bits(i) := 0.U
for (j <- 0 until dim) {
when(countValue === j.U) {
io.outCol.bits(i) := regArrayT(j)(i)
}
}
}
when (io.inRow.fire && countWrap) {
state := 1.U
}
when (io.outCol.fire && countWrap) {
state := 0.U
}
assert(!(state === 0.U) || !io.outCol.fire)
assert(!(state === 1.U) || !io.inRow.fire)
}
| module PE_110( // @[Transposer.scala:100:9]
input clock, // @[Transposer.scala:100:9]
input reset, // @[Transposer.scala:100:9]
input [7:0] io_inR, // @[Transposer.scala:101:16]
input [7:0] io_inD, // @[Transposer.scala:101:16]
output [7:0] io_outL, // @[Transposer.scala:101:16]
output [7:0] io_outU, // @[Transposer.scala:101:16]
input io_dir, // @[Transposer.scala:101:16]
input io_en // @[Transposer.scala:101:16]
);
wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9]
wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9]
wire io_dir_0 = io_dir; // @[Transposer.scala:100:9]
wire io_en_0 = io_en; // @[Transposer.scala:100:9]
wire [7:0] io_outL_0; // @[Transposer.scala:100:9]
wire [7:0] io_outU_0; // @[Transposer.scala:100:9]
wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36]
wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}]
reg [7:0] reg_0; // @[Transposer.scala:110:24]
assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24]
assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24]
always @(posedge clock) begin // @[Transposer.scala:100:9]
if (io_en_0) // @[Transposer.scala:100:9]
reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}]
always @(posedge)
assign io_outL = io_outL_0; // @[Transposer.scala:100:9]
assign io_outU = io_outU_0; // @[Transposer.scala:100:9]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File FIFOFixer.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.lazymodule._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.diplomacy.RegionType
import freechips.rocketchip.util.property
class TLFIFOFixer(policy: TLFIFOFixer.Policy = TLFIFOFixer.all)(implicit p: Parameters) extends LazyModule
{
private def fifoMap(seq: Seq[TLSlaveParameters]) = {
val (flatManagers, keepManagers) = seq.partition(policy)
// We need to be careful if one flatManager and one keepManager share an existing domain
// Erring on the side of caution, we will also flatten the keepManager in this case
val flatDomains = Set(flatManagers.flatMap(_.fifoId):_*) // => ID 0
val keepDomains = Set(keepManagers.flatMap(_.fifoId):_*) -- flatDomains // => IDs compacted
// Calculate what the FIFO domains look like after the fixer is applied
val flatMap = flatDomains.map { x => (x, 0) }.toMap
val keepMap = keepDomains.scanLeft((-1,0)) { case ((_,s),x) => (x, s+1) }.toMap
val map = flatMap ++ keepMap
val fixMap = seq.map { m => m.fifoId match {
case None => if (policy(m)) Some(0) else None
case Some(id) => Some(map(id)) // also flattens some who did not ask
} }
// Compress the FIFO domain space of those we are combining
val reMap = flatDomains.scanLeft((-1,-1)) { case ((_,s),x) => (x, s+1) }.toMap
val splatMap = seq.map { m => m.fifoId match {
case None => None
case Some(id) => reMap.lift(id)
} }
(fixMap, splatMap)
}
val node = new AdapterNode(TLImp)(
{ cp => cp },
{ mp =>
val (fixMap, _) = fifoMap(mp.managers)
mp.v1copy(managers = (fixMap zip mp.managers) map { case (id, m) => m.v1copy(fifoId = id) })
}) with TLFormatNode {
override def circuitIdentity = edges.in.map(_.client.clients.filter(c => c.requestFifo && c.sourceId.size > 1).size).sum == 0
}
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
val (fixMap, splatMap) = fifoMap(edgeOut.manager.managers)
// Do we need to serialize the request to this manager?
val a_notFIFO = edgeIn.manager.fastProperty(in.a.bits.address, _.fifoId != Some(0), (b:Boolean) => b.B)
// Compact the IDs of the cases we serialize
val compacted = ((fixMap zip splatMap) zip edgeOut.manager.managers) flatMap {
case ((f, s), m) => if (f == Some(0)) Some(m.v1copy(fifoId = s)) else None
}
val sinks = if (compacted.exists(_.supportsAcquireB)) edgeOut.manager.endSinkId else 0
val a_id = if (compacted.isEmpty) 0.U else
edgeOut.manager.v1copy(managers = compacted, endSinkId = sinks).findFifoIdFast(in.a.bits.address)
val a_noDomain = a_id === 0.U
if (false) {
println(s"FIFOFixer for: ${edgeIn.client.clients.map(_.name).mkString(", ")}")
println(s"make FIFO: ${edgeIn.manager.managers.filter(_.fifoId==Some(0)).map(_.name).mkString(", ")}")
println(s"not FIFO: ${edgeIn.manager.managers.filter(_.fifoId!=Some(0)).map(_.name).mkString(", ")}")
println(s"domains: ${compacted.groupBy(_.name).mapValues(_.map(_.fifoId))}")
println("")
}
// Count beats
val a_first = edgeIn.first(in.a)
val d_first = edgeOut.first(out.d) && out.d.bits.opcode =/= TLMessages.ReleaseAck
// Keep one bit for each source recording if there is an outstanding request that must be made FIFO
// Sources unused in the stall signal calculation should be pruned by DCE
val flight = RegInit(VecInit(Seq.fill(edgeIn.client.endSourceId) { false.B }))
when (a_first && in.a.fire) { flight(in.a.bits.source) := !a_notFIFO }
when (d_first && in.d.fire) { flight(in.d.bits.source) := false.B }
val stalls = edgeIn.client.clients.filter(c => c.requestFifo && c.sourceId.size > 1).map { c =>
val a_sel = c.sourceId.contains(in.a.bits.source)
val id = RegEnable(a_id, in.a.fire && a_sel && !a_notFIFO)
val track = flight.slice(c.sourceId.start, c.sourceId.end)
a_sel && a_first && track.reduce(_ || _) && (a_noDomain || id =/= a_id)
}
val stall = stalls.foldLeft(false.B)(_||_)
out.a <> in.a
in.d <> out.d
out.a.valid := in.a.valid && (a_notFIFO || !stall)
in.a.ready := out.a.ready && (a_notFIFO || !stall)
if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) {
in .b <> out.b
out.c <> in .c
out.e <> in .e
} else {
in.b.valid := false.B
in.c.ready := true.B
in.e.ready := true.B
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
}
//Functional cover properties
property.cover(in.a.valid && stall, "COVER FIFOFIXER STALL", "Cover: Stall occured for a valid transaction")
val SourceIdFIFOed = RegInit(0.U(edgeIn.client.endSourceId.W))
val SourceIdSet = WireDefault(0.U(edgeIn.client.endSourceId.W))
val SourceIdClear = WireDefault(0.U(edgeIn.client.endSourceId.W))
when (a_first && in.a.fire && !a_notFIFO) {
SourceIdSet := UIntToOH(in.a.bits.source)
}
when (d_first && in.d.fire) {
SourceIdClear := UIntToOH(in.d.bits.source)
}
SourceIdFIFOed := SourceIdFIFOed | SourceIdSet
val allIDs_FIFOed = SourceIdFIFOed===Fill(SourceIdFIFOed.getWidth, 1.U)
property.cover(allIDs_FIFOed, "COVER all sources", "Cover: FIFOFIXER covers all Source IDs")
//property.cover(flight.reduce(_ && _), "COVER full", "Cover: FIFO is full with all Source IDs")
property.cover(!(flight.reduce(_ || _)), "COVER empty", "Cover: FIFO is empty")
property.cover(SourceIdSet > 0.U, "COVER at least one push", "Cover: At least one Source ID is pushed")
property.cover(SourceIdClear > 0.U, "COVER at least one pop", "Cover: At least one Source ID is popped")
}
}
}
object TLFIFOFixer
{
// Which slaves should have their FIFOness combined?
// NOTE: this transformation is still only applied for masters with requestFifo
type Policy = TLSlaveParameters => Boolean
import RegionType._
val all: Policy = m => true
val allFIFO: Policy = m => m.fifoId.isDefined
val allVolatile: Policy = m => m.regionType <= VOLATILE
def apply(policy: Policy = all)(implicit p: Parameters): TLNode =
{
val fixer = LazyModule(new TLFIFOFixer(policy))
fixer.node
}
}
File Nodes.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection}
case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args))
object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
{
def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo)
def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo)
def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle)
def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle)
def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString)
override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = {
val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge)))
monitor.io.in := bundle
}
override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters =
pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })
override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters =
pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })
}
trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut]
case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode
case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode
case class TLAdapterNode(
clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s },
managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLJunctionNode(
clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters],
managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])(
implicit valName: ValName)
extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode
object TLNameNode {
def apply(name: ValName) = TLIdentityNode()(name)
def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLIdentityNode = apply(Some(name))
}
case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)()
object TLTempNode {
def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp"))
}
case class TLNexusNode(
clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters,
managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)(
implicit valName: ValName)
extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode
abstract class TLCustomNode(implicit valName: ValName)
extends CustomNode(TLImp) with TLFormatNode
// Asynchronous crossings
trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters]
object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle]
{
def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle)
def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString)
override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLAsyncAdapterNode(
clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s },
managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode
case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode
object TLAsyncNameNode {
def apply(name: ValName) = TLAsyncIdentityNode()(name)
def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLAsyncIdentityNode = apply(Some(name))
}
case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLAsyncImp)(
dFn = { p => TLAsyncClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain
case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName)
extends MixedAdapterNode(TLAsyncImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) },
uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut]
// Rationally related crossings
trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters]
object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle]
{
def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle)
def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */)
override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLRationalAdapterNode(
clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s },
managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode
case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode
object TLRationalNameNode {
def apply(name: ValName) = TLRationalIdentityNode()(name)
def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLRationalIdentityNode = apply(Some(name))
}
case class TLRationalSourceNode()(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLRationalImp)(
dFn = { p => TLRationalClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain
case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName)
extends MixedAdapterNode(TLRationalImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut]
// Credited version of TileLink channels
trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters]
object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle]
{
def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle)
def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString)
override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLCreditedAdapterNode(
clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s },
managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode
case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode
object TLCreditedNameNode {
def apply(name: ValName) = TLCreditedIdentityNode()(name)
def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLCreditedIdentityNode = apply(Some(name))
}
case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLCreditedImp)(
dFn = { p => TLCreditedClientPortParameters(delay, p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain
case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLCreditedImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut]
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLFIFOFixer_5( // @[FIFOFixer.scala:50:9]
input clock, // @[FIFOFixer.scala:50:9]
input reset, // @[FIFOFixer.scala:50:9]
output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [10:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [13:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [10:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [10:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [13:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [10:0] auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_out_d_bits_data // @[LazyModuleImp.scala:107:25]
);
wire [1:0] a_id = {auto_anon_in_a_bits_address[8], ~(auto_anon_in_a_bits_address[8])}; // @[Mux.scala:30:73]
reg a_first_counter; // @[Edges.scala:229:27]
reg d_first_counter; // @[Edges.scala:229:27]
reg flight_0; // @[FIFOFixer.scala:79:27]
reg flight_1; // @[FIFOFixer.scala:79:27]
reg flight_2; // @[FIFOFixer.scala:79:27]
reg flight_3; // @[FIFOFixer.scala:79:27]
reg flight_4; // @[FIFOFixer.scala:79:27]
reg flight_5; // @[FIFOFixer.scala:79:27]
reg flight_6; // @[FIFOFixer.scala:79:27]
reg flight_7; // @[FIFOFixer.scala:79:27]
reg flight_8; // @[FIFOFixer.scala:79:27]
reg flight_9; // @[FIFOFixer.scala:79:27]
reg flight_10; // @[FIFOFixer.scala:79:27]
reg flight_11; // @[FIFOFixer.scala:79:27]
reg flight_12; // @[FIFOFixer.scala:79:27]
reg flight_13; // @[FIFOFixer.scala:79:27]
reg flight_14; // @[FIFOFixer.scala:79:27]
reg flight_15; // @[FIFOFixer.scala:79:27]
reg flight_16; // @[FIFOFixer.scala:79:27]
reg flight_17; // @[FIFOFixer.scala:79:27]
reg flight_18; // @[FIFOFixer.scala:79:27]
reg flight_19; // @[FIFOFixer.scala:79:27]
reg flight_20; // @[FIFOFixer.scala:79:27]
reg flight_21; // @[FIFOFixer.scala:79:27]
reg flight_22; // @[FIFOFixer.scala:79:27]
reg flight_23; // @[FIFOFixer.scala:79:27]
reg flight_24; // @[FIFOFixer.scala:79:27]
reg flight_25; // @[FIFOFixer.scala:79:27]
reg flight_26; // @[FIFOFixer.scala:79:27]
reg flight_27; // @[FIFOFixer.scala:79:27]
reg flight_28; // @[FIFOFixer.scala:79:27]
reg flight_29; // @[FIFOFixer.scala:79:27]
reg flight_30; // @[FIFOFixer.scala:79:27]
reg flight_31; // @[FIFOFixer.scala:79:27]
reg flight_32; // @[FIFOFixer.scala:79:27]
reg flight_33; // @[FIFOFixer.scala:79:27]
reg flight_34; // @[FIFOFixer.scala:79:27]
reg flight_35; // @[FIFOFixer.scala:79:27]
reg flight_36; // @[FIFOFixer.scala:79:27]
reg flight_37; // @[FIFOFixer.scala:79:27]
reg flight_38; // @[FIFOFixer.scala:79:27]
reg flight_39; // @[FIFOFixer.scala:79:27]
reg flight_40; // @[FIFOFixer.scala:79:27]
reg flight_41; // @[FIFOFixer.scala:79:27]
reg flight_42; // @[FIFOFixer.scala:79:27]
reg flight_43; // @[FIFOFixer.scala:79:27]
reg flight_44; // @[FIFOFixer.scala:79:27]
reg flight_45; // @[FIFOFixer.scala:79:27]
reg flight_46; // @[FIFOFixer.scala:79:27]
reg flight_47; // @[FIFOFixer.scala:79:27]
reg flight_48; // @[FIFOFixer.scala:79:27]
reg flight_49; // @[FIFOFixer.scala:79:27]
reg flight_50; // @[FIFOFixer.scala:79:27]
reg flight_51; // @[FIFOFixer.scala:79:27]
reg flight_52; // @[FIFOFixer.scala:79:27]
reg flight_53; // @[FIFOFixer.scala:79:27]
reg flight_54; // @[FIFOFixer.scala:79:27]
reg flight_55; // @[FIFOFixer.scala:79:27]
reg flight_56; // @[FIFOFixer.scala:79:27]
reg flight_57; // @[FIFOFixer.scala:79:27]
reg flight_58; // @[FIFOFixer.scala:79:27]
reg flight_59; // @[FIFOFixer.scala:79:27]
reg flight_60; // @[FIFOFixer.scala:79:27]
reg flight_61; // @[FIFOFixer.scala:79:27]
reg flight_62; // @[FIFOFixer.scala:79:27]
reg flight_63; // @[FIFOFixer.scala:79:27]
reg flight_64; // @[FIFOFixer.scala:79:27]
reg flight_65; // @[FIFOFixer.scala:79:27]
reg flight_66; // @[FIFOFixer.scala:79:27]
reg flight_67; // @[FIFOFixer.scala:79:27]
reg flight_68; // @[FIFOFixer.scala:79:27]
reg flight_69; // @[FIFOFixer.scala:79:27]
reg flight_70; // @[FIFOFixer.scala:79:27]
reg flight_71; // @[FIFOFixer.scala:79:27]
reg flight_72; // @[FIFOFixer.scala:79:27]
reg flight_73; // @[FIFOFixer.scala:79:27]
reg flight_74; // @[FIFOFixer.scala:79:27]
reg flight_75; // @[FIFOFixer.scala:79:27]
reg flight_76; // @[FIFOFixer.scala:79:27]
reg flight_77; // @[FIFOFixer.scala:79:27]
reg flight_78; // @[FIFOFixer.scala:79:27]
reg flight_79; // @[FIFOFixer.scala:79:27]
reg flight_80; // @[FIFOFixer.scala:79:27]
reg flight_81; // @[FIFOFixer.scala:79:27]
reg flight_82; // @[FIFOFixer.scala:79:27]
reg flight_83; // @[FIFOFixer.scala:79:27]
reg flight_84; // @[FIFOFixer.scala:79:27]
reg flight_85; // @[FIFOFixer.scala:79:27]
reg flight_86; // @[FIFOFixer.scala:79:27]
reg flight_87; // @[FIFOFixer.scala:79:27]
reg flight_88; // @[FIFOFixer.scala:79:27]
reg flight_89; // @[FIFOFixer.scala:79:27]
reg flight_90; // @[FIFOFixer.scala:79:27]
reg flight_91; // @[FIFOFixer.scala:79:27]
reg flight_92; // @[FIFOFixer.scala:79:27]
reg flight_93; // @[FIFOFixer.scala:79:27]
reg flight_94; // @[FIFOFixer.scala:79:27]
reg flight_95; // @[FIFOFixer.scala:79:27]
reg flight_96; // @[FIFOFixer.scala:79:27]
reg flight_97; // @[FIFOFixer.scala:79:27]
reg flight_98; // @[FIFOFixer.scala:79:27]
reg flight_99; // @[FIFOFixer.scala:79:27]
reg flight_100; // @[FIFOFixer.scala:79:27]
reg flight_101; // @[FIFOFixer.scala:79:27]
reg flight_102; // @[FIFOFixer.scala:79:27]
reg flight_103; // @[FIFOFixer.scala:79:27]
reg flight_104; // @[FIFOFixer.scala:79:27]
reg flight_105; // @[FIFOFixer.scala:79:27]
reg flight_106; // @[FIFOFixer.scala:79:27]
reg flight_107; // @[FIFOFixer.scala:79:27]
reg flight_108; // @[FIFOFixer.scala:79:27]
reg flight_109; // @[FIFOFixer.scala:79:27]
reg flight_110; // @[FIFOFixer.scala:79:27]
reg flight_111; // @[FIFOFixer.scala:79:27]
reg flight_112; // @[FIFOFixer.scala:79:27]
reg flight_113; // @[FIFOFixer.scala:79:27]
reg flight_114; // @[FIFOFixer.scala:79:27]
reg flight_115; // @[FIFOFixer.scala:79:27]
reg flight_116; // @[FIFOFixer.scala:79:27]
reg flight_117; // @[FIFOFixer.scala:79:27]
reg flight_118; // @[FIFOFixer.scala:79:27]
reg flight_119; // @[FIFOFixer.scala:79:27]
reg flight_120; // @[FIFOFixer.scala:79:27]
reg flight_121; // @[FIFOFixer.scala:79:27]
reg flight_122; // @[FIFOFixer.scala:79:27]
reg flight_123; // @[FIFOFixer.scala:79:27]
reg flight_124; // @[FIFOFixer.scala:79:27]
reg flight_125; // @[FIFOFixer.scala:79:27]
reg flight_126; // @[FIFOFixer.scala:79:27]
reg flight_127; // @[FIFOFixer.scala:79:27]
reg flight_128; // @[FIFOFixer.scala:79:27]
reg flight_129; // @[FIFOFixer.scala:79:27]
reg flight_130; // @[FIFOFixer.scala:79:27]
reg flight_131; // @[FIFOFixer.scala:79:27]
reg flight_132; // @[FIFOFixer.scala:79:27]
reg flight_133; // @[FIFOFixer.scala:79:27]
reg flight_134; // @[FIFOFixer.scala:79:27]
reg flight_135; // @[FIFOFixer.scala:79:27]
reg flight_136; // @[FIFOFixer.scala:79:27]
reg flight_137; // @[FIFOFixer.scala:79:27]
reg flight_138; // @[FIFOFixer.scala:79:27]
reg flight_139; // @[FIFOFixer.scala:79:27]
reg flight_140; // @[FIFOFixer.scala:79:27]
reg flight_141; // @[FIFOFixer.scala:79:27]
reg flight_142; // @[FIFOFixer.scala:79:27]
reg flight_143; // @[FIFOFixer.scala:79:27]
reg flight_144; // @[FIFOFixer.scala:79:27]
reg flight_145; // @[FIFOFixer.scala:79:27]
reg flight_146; // @[FIFOFixer.scala:79:27]
reg flight_147; // @[FIFOFixer.scala:79:27]
reg flight_148; // @[FIFOFixer.scala:79:27]
reg flight_149; // @[FIFOFixer.scala:79:27]
reg flight_150; // @[FIFOFixer.scala:79:27]
reg flight_151; // @[FIFOFixer.scala:79:27]
reg flight_152; // @[FIFOFixer.scala:79:27]
reg flight_153; // @[FIFOFixer.scala:79:27]
reg flight_154; // @[FIFOFixer.scala:79:27]
reg flight_155; // @[FIFOFixer.scala:79:27]
reg flight_156; // @[FIFOFixer.scala:79:27]
reg flight_157; // @[FIFOFixer.scala:79:27]
reg flight_158; // @[FIFOFixer.scala:79:27]
reg flight_159; // @[FIFOFixer.scala:79:27]
reg flight_160; // @[FIFOFixer.scala:79:27]
reg flight_161; // @[FIFOFixer.scala:79:27]
reg flight_162; // @[FIFOFixer.scala:79:27]
reg flight_163; // @[FIFOFixer.scala:79:27]
reg flight_164; // @[FIFOFixer.scala:79:27]
reg flight_165; // @[FIFOFixer.scala:79:27]
reg flight_166; // @[FIFOFixer.scala:79:27]
reg flight_167; // @[FIFOFixer.scala:79:27]
reg flight_168; // @[FIFOFixer.scala:79:27]
reg flight_169; // @[FIFOFixer.scala:79:27]
reg flight_170; // @[FIFOFixer.scala:79:27]
reg flight_171; // @[FIFOFixer.scala:79:27]
reg flight_172; // @[FIFOFixer.scala:79:27]
reg flight_173; // @[FIFOFixer.scala:79:27]
reg flight_174; // @[FIFOFixer.scala:79:27]
reg flight_175; // @[FIFOFixer.scala:79:27]
reg flight_176; // @[FIFOFixer.scala:79:27]
reg flight_177; // @[FIFOFixer.scala:79:27]
reg flight_178; // @[FIFOFixer.scala:79:27]
reg flight_179; // @[FIFOFixer.scala:79:27]
reg flight_180; // @[FIFOFixer.scala:79:27]
reg flight_181; // @[FIFOFixer.scala:79:27]
reg flight_182; // @[FIFOFixer.scala:79:27]
reg flight_183; // @[FIFOFixer.scala:79:27]
reg flight_184; // @[FIFOFixer.scala:79:27]
reg flight_185; // @[FIFOFixer.scala:79:27]
reg flight_186; // @[FIFOFixer.scala:79:27]
reg flight_187; // @[FIFOFixer.scala:79:27]
reg flight_188; // @[FIFOFixer.scala:79:27]
reg flight_189; // @[FIFOFixer.scala:79:27]
reg flight_190; // @[FIFOFixer.scala:79:27]
reg flight_191; // @[FIFOFixer.scala:79:27]
reg flight_192; // @[FIFOFixer.scala:79:27]
reg flight_193; // @[FIFOFixer.scala:79:27]
reg flight_194; // @[FIFOFixer.scala:79:27]
reg flight_195; // @[FIFOFixer.scala:79:27]
reg flight_196; // @[FIFOFixer.scala:79:27]
reg flight_197; // @[FIFOFixer.scala:79:27]
reg flight_198; // @[FIFOFixer.scala:79:27]
reg flight_199; // @[FIFOFixer.scala:79:27]
reg flight_200; // @[FIFOFixer.scala:79:27]
reg flight_201; // @[FIFOFixer.scala:79:27]
reg flight_202; // @[FIFOFixer.scala:79:27]
reg flight_203; // @[FIFOFixer.scala:79:27]
reg flight_204; // @[FIFOFixer.scala:79:27]
reg flight_205; // @[FIFOFixer.scala:79:27]
reg flight_206; // @[FIFOFixer.scala:79:27]
reg flight_207; // @[FIFOFixer.scala:79:27]
reg flight_208; // @[FIFOFixer.scala:79:27]
reg flight_209; // @[FIFOFixer.scala:79:27]
reg flight_210; // @[FIFOFixer.scala:79:27]
reg flight_211; // @[FIFOFixer.scala:79:27]
reg flight_212; // @[FIFOFixer.scala:79:27]
reg flight_213; // @[FIFOFixer.scala:79:27]
reg flight_214; // @[FIFOFixer.scala:79:27]
reg flight_215; // @[FIFOFixer.scala:79:27]
reg flight_216; // @[FIFOFixer.scala:79:27]
reg flight_217; // @[FIFOFixer.scala:79:27]
reg flight_218; // @[FIFOFixer.scala:79:27]
reg flight_219; // @[FIFOFixer.scala:79:27]
reg flight_220; // @[FIFOFixer.scala:79:27]
reg flight_221; // @[FIFOFixer.scala:79:27]
reg flight_222; // @[FIFOFixer.scala:79:27]
reg flight_223; // @[FIFOFixer.scala:79:27]
reg flight_224; // @[FIFOFixer.scala:79:27]
reg flight_225; // @[FIFOFixer.scala:79:27]
reg flight_226; // @[FIFOFixer.scala:79:27]
reg flight_227; // @[FIFOFixer.scala:79:27]
reg flight_228; // @[FIFOFixer.scala:79:27]
reg flight_229; // @[FIFOFixer.scala:79:27]
reg flight_230; // @[FIFOFixer.scala:79:27]
reg flight_231; // @[FIFOFixer.scala:79:27]
reg flight_232; // @[FIFOFixer.scala:79:27]
reg flight_233; // @[FIFOFixer.scala:79:27]
reg flight_234; // @[FIFOFixer.scala:79:27]
reg flight_235; // @[FIFOFixer.scala:79:27]
reg flight_236; // @[FIFOFixer.scala:79:27]
reg flight_237; // @[FIFOFixer.scala:79:27]
reg flight_238; // @[FIFOFixer.scala:79:27]
reg flight_239; // @[FIFOFixer.scala:79:27]
reg flight_240; // @[FIFOFixer.scala:79:27]
reg flight_241; // @[FIFOFixer.scala:79:27]
reg flight_242; // @[FIFOFixer.scala:79:27]
reg flight_243; // @[FIFOFixer.scala:79:27]
reg flight_244; // @[FIFOFixer.scala:79:27]
reg flight_245; // @[FIFOFixer.scala:79:27]
reg flight_246; // @[FIFOFixer.scala:79:27]
reg flight_247; // @[FIFOFixer.scala:79:27]
reg flight_248; // @[FIFOFixer.scala:79:27]
reg flight_249; // @[FIFOFixer.scala:79:27]
reg flight_250; // @[FIFOFixer.scala:79:27]
reg flight_251; // @[FIFOFixer.scala:79:27]
reg flight_252; // @[FIFOFixer.scala:79:27]
reg flight_253; // @[FIFOFixer.scala:79:27]
reg flight_254; // @[FIFOFixer.scala:79:27]
reg flight_255; // @[FIFOFixer.scala:79:27]
reg flight_256; // @[FIFOFixer.scala:79:27]
reg flight_257; // @[FIFOFixer.scala:79:27]
reg flight_258; // @[FIFOFixer.scala:79:27]
reg flight_259; // @[FIFOFixer.scala:79:27]
reg flight_260; // @[FIFOFixer.scala:79:27]
reg flight_261; // @[FIFOFixer.scala:79:27]
reg flight_262; // @[FIFOFixer.scala:79:27]
reg flight_263; // @[FIFOFixer.scala:79:27]
reg flight_264; // @[FIFOFixer.scala:79:27]
reg flight_265; // @[FIFOFixer.scala:79:27]
reg flight_266; // @[FIFOFixer.scala:79:27]
reg flight_267; // @[FIFOFixer.scala:79:27]
reg flight_268; // @[FIFOFixer.scala:79:27]
reg flight_269; // @[FIFOFixer.scala:79:27]
reg flight_270; // @[FIFOFixer.scala:79:27]
reg flight_271; // @[FIFOFixer.scala:79:27]
reg flight_272; // @[FIFOFixer.scala:79:27]
reg flight_273; // @[FIFOFixer.scala:79:27]
reg flight_274; // @[FIFOFixer.scala:79:27]
reg flight_275; // @[FIFOFixer.scala:79:27]
reg flight_276; // @[FIFOFixer.scala:79:27]
reg flight_277; // @[FIFOFixer.scala:79:27]
reg flight_278; // @[FIFOFixer.scala:79:27]
reg flight_279; // @[FIFOFixer.scala:79:27]
reg flight_280; // @[FIFOFixer.scala:79:27]
reg flight_281; // @[FIFOFixer.scala:79:27]
reg flight_282; // @[FIFOFixer.scala:79:27]
reg flight_283; // @[FIFOFixer.scala:79:27]
reg flight_284; // @[FIFOFixer.scala:79:27]
reg flight_285; // @[FIFOFixer.scala:79:27]
reg flight_286; // @[FIFOFixer.scala:79:27]
reg flight_287; // @[FIFOFixer.scala:79:27]
reg flight_288; // @[FIFOFixer.scala:79:27]
reg flight_289; // @[FIFOFixer.scala:79:27]
reg flight_290; // @[FIFOFixer.scala:79:27]
reg flight_291; // @[FIFOFixer.scala:79:27]
reg flight_292; // @[FIFOFixer.scala:79:27]
reg flight_293; // @[FIFOFixer.scala:79:27]
reg flight_294; // @[FIFOFixer.scala:79:27]
reg flight_295; // @[FIFOFixer.scala:79:27]
reg flight_296; // @[FIFOFixer.scala:79:27]
reg flight_297; // @[FIFOFixer.scala:79:27]
reg flight_298; // @[FIFOFixer.scala:79:27]
reg flight_299; // @[FIFOFixer.scala:79:27]
reg flight_300; // @[FIFOFixer.scala:79:27]
reg flight_301; // @[FIFOFixer.scala:79:27]
reg flight_302; // @[FIFOFixer.scala:79:27]
reg flight_303; // @[FIFOFixer.scala:79:27]
reg flight_304; // @[FIFOFixer.scala:79:27]
reg flight_305; // @[FIFOFixer.scala:79:27]
reg flight_306; // @[FIFOFixer.scala:79:27]
reg flight_307; // @[FIFOFixer.scala:79:27]
reg flight_308; // @[FIFOFixer.scala:79:27]
reg flight_309; // @[FIFOFixer.scala:79:27]
reg flight_310; // @[FIFOFixer.scala:79:27]
reg flight_311; // @[FIFOFixer.scala:79:27]
reg flight_312; // @[FIFOFixer.scala:79:27]
reg flight_313; // @[FIFOFixer.scala:79:27]
reg flight_314; // @[FIFOFixer.scala:79:27]
reg flight_315; // @[FIFOFixer.scala:79:27]
reg flight_316; // @[FIFOFixer.scala:79:27]
reg flight_317; // @[FIFOFixer.scala:79:27]
reg flight_318; // @[FIFOFixer.scala:79:27]
reg flight_319; // @[FIFOFixer.scala:79:27]
reg flight_320; // @[FIFOFixer.scala:79:27]
reg flight_321; // @[FIFOFixer.scala:79:27]
reg flight_322; // @[FIFOFixer.scala:79:27]
reg flight_323; // @[FIFOFixer.scala:79:27]
reg flight_324; // @[FIFOFixer.scala:79:27]
reg flight_325; // @[FIFOFixer.scala:79:27]
reg flight_326; // @[FIFOFixer.scala:79:27]
reg flight_327; // @[FIFOFixer.scala:79:27]
reg flight_328; // @[FIFOFixer.scala:79:27]
reg flight_329; // @[FIFOFixer.scala:79:27]
reg flight_330; // @[FIFOFixer.scala:79:27]
reg flight_331; // @[FIFOFixer.scala:79:27]
reg flight_332; // @[FIFOFixer.scala:79:27]
reg flight_333; // @[FIFOFixer.scala:79:27]
reg flight_334; // @[FIFOFixer.scala:79:27]
reg flight_335; // @[FIFOFixer.scala:79:27]
reg flight_336; // @[FIFOFixer.scala:79:27]
reg flight_337; // @[FIFOFixer.scala:79:27]
reg flight_338; // @[FIFOFixer.scala:79:27]
reg flight_339; // @[FIFOFixer.scala:79:27]
reg flight_340; // @[FIFOFixer.scala:79:27]
reg flight_341; // @[FIFOFixer.scala:79:27]
reg flight_342; // @[FIFOFixer.scala:79:27]
reg flight_343; // @[FIFOFixer.scala:79:27]
reg flight_344; // @[FIFOFixer.scala:79:27]
reg flight_345; // @[FIFOFixer.scala:79:27]
reg flight_346; // @[FIFOFixer.scala:79:27]
reg flight_347; // @[FIFOFixer.scala:79:27]
reg flight_348; // @[FIFOFixer.scala:79:27]
reg flight_349; // @[FIFOFixer.scala:79:27]
reg flight_350; // @[FIFOFixer.scala:79:27]
reg flight_351; // @[FIFOFixer.scala:79:27]
reg flight_352; // @[FIFOFixer.scala:79:27]
reg flight_353; // @[FIFOFixer.scala:79:27]
reg flight_354; // @[FIFOFixer.scala:79:27]
reg flight_355; // @[FIFOFixer.scala:79:27]
reg flight_356; // @[FIFOFixer.scala:79:27]
reg flight_357; // @[FIFOFixer.scala:79:27]
reg flight_358; // @[FIFOFixer.scala:79:27]
reg flight_359; // @[FIFOFixer.scala:79:27]
reg flight_360; // @[FIFOFixer.scala:79:27]
reg flight_361; // @[FIFOFixer.scala:79:27]
reg flight_362; // @[FIFOFixer.scala:79:27]
reg flight_363; // @[FIFOFixer.scala:79:27]
reg flight_364; // @[FIFOFixer.scala:79:27]
reg flight_365; // @[FIFOFixer.scala:79:27]
reg flight_366; // @[FIFOFixer.scala:79:27]
reg flight_367; // @[FIFOFixer.scala:79:27]
reg flight_368; // @[FIFOFixer.scala:79:27]
reg flight_369; // @[FIFOFixer.scala:79:27]
reg flight_370; // @[FIFOFixer.scala:79:27]
reg flight_371; // @[FIFOFixer.scala:79:27]
reg flight_372; // @[FIFOFixer.scala:79:27]
reg flight_373; // @[FIFOFixer.scala:79:27]
reg flight_374; // @[FIFOFixer.scala:79:27]
reg flight_375; // @[FIFOFixer.scala:79:27]
reg flight_376; // @[FIFOFixer.scala:79:27]
reg flight_377; // @[FIFOFixer.scala:79:27]
reg flight_378; // @[FIFOFixer.scala:79:27]
reg flight_379; // @[FIFOFixer.scala:79:27]
reg flight_380; // @[FIFOFixer.scala:79:27]
reg flight_381; // @[FIFOFixer.scala:79:27]
reg flight_382; // @[FIFOFixer.scala:79:27]
reg flight_383; // @[FIFOFixer.scala:79:27]
reg flight_384; // @[FIFOFixer.scala:79:27]
reg flight_385; // @[FIFOFixer.scala:79:27]
reg flight_386; // @[FIFOFixer.scala:79:27]
reg flight_387; // @[FIFOFixer.scala:79:27]
reg flight_388; // @[FIFOFixer.scala:79:27]
reg flight_389; // @[FIFOFixer.scala:79:27]
reg flight_390; // @[FIFOFixer.scala:79:27]
reg flight_391; // @[FIFOFixer.scala:79:27]
reg flight_392; // @[FIFOFixer.scala:79:27]
reg flight_393; // @[FIFOFixer.scala:79:27]
reg flight_394; // @[FIFOFixer.scala:79:27]
reg flight_395; // @[FIFOFixer.scala:79:27]
reg flight_396; // @[FIFOFixer.scala:79:27]
reg flight_397; // @[FIFOFixer.scala:79:27]
reg flight_398; // @[FIFOFixer.scala:79:27]
reg flight_399; // @[FIFOFixer.scala:79:27]
reg flight_400; // @[FIFOFixer.scala:79:27]
reg flight_401; // @[FIFOFixer.scala:79:27]
reg flight_402; // @[FIFOFixer.scala:79:27]
reg flight_403; // @[FIFOFixer.scala:79:27]
reg flight_404; // @[FIFOFixer.scala:79:27]
reg flight_405; // @[FIFOFixer.scala:79:27]
reg flight_406; // @[FIFOFixer.scala:79:27]
reg flight_407; // @[FIFOFixer.scala:79:27]
reg flight_408; // @[FIFOFixer.scala:79:27]
reg flight_409; // @[FIFOFixer.scala:79:27]
reg flight_410; // @[FIFOFixer.scala:79:27]
reg flight_411; // @[FIFOFixer.scala:79:27]
reg flight_412; // @[FIFOFixer.scala:79:27]
reg flight_413; // @[FIFOFixer.scala:79:27]
reg flight_414; // @[FIFOFixer.scala:79:27]
reg flight_415; // @[FIFOFixer.scala:79:27]
reg flight_416; // @[FIFOFixer.scala:79:27]
reg flight_417; // @[FIFOFixer.scala:79:27]
reg flight_418; // @[FIFOFixer.scala:79:27]
reg flight_419; // @[FIFOFixer.scala:79:27]
reg flight_420; // @[FIFOFixer.scala:79:27]
reg flight_421; // @[FIFOFixer.scala:79:27]
reg flight_422; // @[FIFOFixer.scala:79:27]
reg flight_423; // @[FIFOFixer.scala:79:27]
reg flight_424; // @[FIFOFixer.scala:79:27]
reg flight_425; // @[FIFOFixer.scala:79:27]
reg flight_426; // @[FIFOFixer.scala:79:27]
reg flight_427; // @[FIFOFixer.scala:79:27]
reg flight_428; // @[FIFOFixer.scala:79:27]
reg flight_429; // @[FIFOFixer.scala:79:27]
reg flight_430; // @[FIFOFixer.scala:79:27]
reg flight_431; // @[FIFOFixer.scala:79:27]
reg flight_432; // @[FIFOFixer.scala:79:27]
reg flight_433; // @[FIFOFixer.scala:79:27]
reg flight_434; // @[FIFOFixer.scala:79:27]
reg flight_435; // @[FIFOFixer.scala:79:27]
reg flight_436; // @[FIFOFixer.scala:79:27]
reg flight_437; // @[FIFOFixer.scala:79:27]
reg flight_438; // @[FIFOFixer.scala:79:27]
reg flight_439; // @[FIFOFixer.scala:79:27]
reg flight_440; // @[FIFOFixer.scala:79:27]
reg flight_441; // @[FIFOFixer.scala:79:27]
reg flight_442; // @[FIFOFixer.scala:79:27]
reg flight_443; // @[FIFOFixer.scala:79:27]
reg flight_444; // @[FIFOFixer.scala:79:27]
reg flight_445; // @[FIFOFixer.scala:79:27]
reg flight_446; // @[FIFOFixer.scala:79:27]
reg flight_447; // @[FIFOFixer.scala:79:27]
reg flight_448; // @[FIFOFixer.scala:79:27]
reg flight_449; // @[FIFOFixer.scala:79:27]
reg flight_450; // @[FIFOFixer.scala:79:27]
reg flight_451; // @[FIFOFixer.scala:79:27]
reg flight_452; // @[FIFOFixer.scala:79:27]
reg flight_453; // @[FIFOFixer.scala:79:27]
reg flight_454; // @[FIFOFixer.scala:79:27]
reg flight_455; // @[FIFOFixer.scala:79:27]
reg flight_456; // @[FIFOFixer.scala:79:27]
reg flight_457; // @[FIFOFixer.scala:79:27]
reg flight_458; // @[FIFOFixer.scala:79:27]
reg flight_459; // @[FIFOFixer.scala:79:27]
reg flight_460; // @[FIFOFixer.scala:79:27]
reg flight_461; // @[FIFOFixer.scala:79:27]
reg flight_462; // @[FIFOFixer.scala:79:27]
reg flight_463; // @[FIFOFixer.scala:79:27]
reg flight_464; // @[FIFOFixer.scala:79:27]
reg flight_465; // @[FIFOFixer.scala:79:27]
reg flight_466; // @[FIFOFixer.scala:79:27]
reg flight_467; // @[FIFOFixer.scala:79:27]
reg flight_468; // @[FIFOFixer.scala:79:27]
reg flight_469; // @[FIFOFixer.scala:79:27]
reg flight_470; // @[FIFOFixer.scala:79:27]
reg flight_471; // @[FIFOFixer.scala:79:27]
reg flight_472; // @[FIFOFixer.scala:79:27]
reg flight_473; // @[FIFOFixer.scala:79:27]
reg flight_474; // @[FIFOFixer.scala:79:27]
reg flight_475; // @[FIFOFixer.scala:79:27]
reg flight_476; // @[FIFOFixer.scala:79:27]
reg flight_477; // @[FIFOFixer.scala:79:27]
reg flight_478; // @[FIFOFixer.scala:79:27]
reg flight_479; // @[FIFOFixer.scala:79:27]
reg flight_480; // @[FIFOFixer.scala:79:27]
reg flight_481; // @[FIFOFixer.scala:79:27]
reg flight_482; // @[FIFOFixer.scala:79:27]
reg flight_483; // @[FIFOFixer.scala:79:27]
reg flight_484; // @[FIFOFixer.scala:79:27]
reg flight_485; // @[FIFOFixer.scala:79:27]
reg flight_486; // @[FIFOFixer.scala:79:27]
reg flight_487; // @[FIFOFixer.scala:79:27]
reg flight_488; // @[FIFOFixer.scala:79:27]
reg flight_489; // @[FIFOFixer.scala:79:27]
reg flight_490; // @[FIFOFixer.scala:79:27]
reg flight_491; // @[FIFOFixer.scala:79:27]
reg flight_492; // @[FIFOFixer.scala:79:27]
reg flight_493; // @[FIFOFixer.scala:79:27]
reg flight_494; // @[FIFOFixer.scala:79:27]
reg flight_495; // @[FIFOFixer.scala:79:27]
reg flight_496; // @[FIFOFixer.scala:79:27]
reg flight_497; // @[FIFOFixer.scala:79:27]
reg flight_498; // @[FIFOFixer.scala:79:27]
reg flight_499; // @[FIFOFixer.scala:79:27]
reg flight_500; // @[FIFOFixer.scala:79:27]
reg flight_501; // @[FIFOFixer.scala:79:27]
reg flight_502; // @[FIFOFixer.scala:79:27]
reg flight_503; // @[FIFOFixer.scala:79:27]
reg flight_504; // @[FIFOFixer.scala:79:27]
reg flight_505; // @[FIFOFixer.scala:79:27]
reg flight_506; // @[FIFOFixer.scala:79:27]
reg flight_507; // @[FIFOFixer.scala:79:27]
reg flight_508; // @[FIFOFixer.scala:79:27]
reg flight_509; // @[FIFOFixer.scala:79:27]
reg flight_510; // @[FIFOFixer.scala:79:27]
reg flight_511; // @[FIFOFixer.scala:79:27]
reg flight_512; // @[FIFOFixer.scala:79:27]
reg flight_513; // @[FIFOFixer.scala:79:27]
reg flight_514; // @[FIFOFixer.scala:79:27]
reg flight_515; // @[FIFOFixer.scala:79:27]
reg flight_516; // @[FIFOFixer.scala:79:27]
reg flight_517; // @[FIFOFixer.scala:79:27]
reg flight_518; // @[FIFOFixer.scala:79:27]
reg flight_519; // @[FIFOFixer.scala:79:27]
reg flight_520; // @[FIFOFixer.scala:79:27]
reg flight_521; // @[FIFOFixer.scala:79:27]
reg flight_522; // @[FIFOFixer.scala:79:27]
reg flight_523; // @[FIFOFixer.scala:79:27]
reg flight_524; // @[FIFOFixer.scala:79:27]
reg flight_525; // @[FIFOFixer.scala:79:27]
reg flight_526; // @[FIFOFixer.scala:79:27]
reg flight_527; // @[FIFOFixer.scala:79:27]
reg flight_528; // @[FIFOFixer.scala:79:27]
reg flight_529; // @[FIFOFixer.scala:79:27]
reg flight_530; // @[FIFOFixer.scala:79:27]
reg flight_531; // @[FIFOFixer.scala:79:27]
reg flight_532; // @[FIFOFixer.scala:79:27]
reg flight_533; // @[FIFOFixer.scala:79:27]
reg flight_534; // @[FIFOFixer.scala:79:27]
reg flight_535; // @[FIFOFixer.scala:79:27]
reg flight_536; // @[FIFOFixer.scala:79:27]
reg flight_537; // @[FIFOFixer.scala:79:27]
reg flight_538; // @[FIFOFixer.scala:79:27]
reg flight_539; // @[FIFOFixer.scala:79:27]
reg flight_540; // @[FIFOFixer.scala:79:27]
reg flight_541; // @[FIFOFixer.scala:79:27]
reg flight_542; // @[FIFOFixer.scala:79:27]
reg flight_543; // @[FIFOFixer.scala:79:27]
reg flight_544; // @[FIFOFixer.scala:79:27]
reg flight_545; // @[FIFOFixer.scala:79:27]
reg flight_546; // @[FIFOFixer.scala:79:27]
reg flight_547; // @[FIFOFixer.scala:79:27]
reg flight_548; // @[FIFOFixer.scala:79:27]
reg flight_549; // @[FIFOFixer.scala:79:27]
reg flight_550; // @[FIFOFixer.scala:79:27]
reg flight_551; // @[FIFOFixer.scala:79:27]
reg flight_552; // @[FIFOFixer.scala:79:27]
reg flight_553; // @[FIFOFixer.scala:79:27]
reg flight_554; // @[FIFOFixer.scala:79:27]
reg flight_555; // @[FIFOFixer.scala:79:27]
reg flight_556; // @[FIFOFixer.scala:79:27]
reg flight_557; // @[FIFOFixer.scala:79:27]
reg flight_558; // @[FIFOFixer.scala:79:27]
reg flight_559; // @[FIFOFixer.scala:79:27]
reg flight_560; // @[FIFOFixer.scala:79:27]
reg flight_561; // @[FIFOFixer.scala:79:27]
reg flight_562; // @[FIFOFixer.scala:79:27]
reg flight_563; // @[FIFOFixer.scala:79:27]
reg flight_564; // @[FIFOFixer.scala:79:27]
reg flight_565; // @[FIFOFixer.scala:79:27]
reg flight_566; // @[FIFOFixer.scala:79:27]
reg flight_567; // @[FIFOFixer.scala:79:27]
reg flight_568; // @[FIFOFixer.scala:79:27]
reg flight_569; // @[FIFOFixer.scala:79:27]
reg flight_570; // @[FIFOFixer.scala:79:27]
reg flight_571; // @[FIFOFixer.scala:79:27]
reg flight_572; // @[FIFOFixer.scala:79:27]
reg flight_573; // @[FIFOFixer.scala:79:27]
reg flight_574; // @[FIFOFixer.scala:79:27]
reg flight_575; // @[FIFOFixer.scala:79:27]
reg flight_576; // @[FIFOFixer.scala:79:27]
reg flight_577; // @[FIFOFixer.scala:79:27]
reg flight_578; // @[FIFOFixer.scala:79:27]
reg flight_579; // @[FIFOFixer.scala:79:27]
reg flight_580; // @[FIFOFixer.scala:79:27]
reg flight_581; // @[FIFOFixer.scala:79:27]
reg flight_582; // @[FIFOFixer.scala:79:27]
reg flight_583; // @[FIFOFixer.scala:79:27]
reg flight_584; // @[FIFOFixer.scala:79:27]
reg flight_585; // @[FIFOFixer.scala:79:27]
reg flight_586; // @[FIFOFixer.scala:79:27]
reg flight_587; // @[FIFOFixer.scala:79:27]
reg flight_588; // @[FIFOFixer.scala:79:27]
reg flight_589; // @[FIFOFixer.scala:79:27]
reg flight_590; // @[FIFOFixer.scala:79:27]
reg flight_591; // @[FIFOFixer.scala:79:27]
reg flight_592; // @[FIFOFixer.scala:79:27]
reg flight_593; // @[FIFOFixer.scala:79:27]
reg flight_594; // @[FIFOFixer.scala:79:27]
reg flight_595; // @[FIFOFixer.scala:79:27]
reg flight_596; // @[FIFOFixer.scala:79:27]
reg flight_597; // @[FIFOFixer.scala:79:27]
reg flight_598; // @[FIFOFixer.scala:79:27]
reg flight_599; // @[FIFOFixer.scala:79:27]
reg flight_600; // @[FIFOFixer.scala:79:27]
reg flight_601; // @[FIFOFixer.scala:79:27]
reg flight_602; // @[FIFOFixer.scala:79:27]
reg flight_603; // @[FIFOFixer.scala:79:27]
reg flight_604; // @[FIFOFixer.scala:79:27]
reg flight_605; // @[FIFOFixer.scala:79:27]
reg flight_606; // @[FIFOFixer.scala:79:27]
reg flight_607; // @[FIFOFixer.scala:79:27]
reg flight_608; // @[FIFOFixer.scala:79:27]
reg flight_609; // @[FIFOFixer.scala:79:27]
reg flight_610; // @[FIFOFixer.scala:79:27]
reg flight_611; // @[FIFOFixer.scala:79:27]
reg flight_612; // @[FIFOFixer.scala:79:27]
reg flight_613; // @[FIFOFixer.scala:79:27]
reg flight_614; // @[FIFOFixer.scala:79:27]
reg flight_615; // @[FIFOFixer.scala:79:27]
reg flight_616; // @[FIFOFixer.scala:79:27]
reg flight_617; // @[FIFOFixer.scala:79:27]
reg flight_618; // @[FIFOFixer.scala:79:27]
reg flight_619; // @[FIFOFixer.scala:79:27]
reg flight_620; // @[FIFOFixer.scala:79:27]
reg flight_621; // @[FIFOFixer.scala:79:27]
reg flight_622; // @[FIFOFixer.scala:79:27]
reg flight_623; // @[FIFOFixer.scala:79:27]
reg flight_624; // @[FIFOFixer.scala:79:27]
reg flight_625; // @[FIFOFixer.scala:79:27]
reg flight_626; // @[FIFOFixer.scala:79:27]
reg flight_627; // @[FIFOFixer.scala:79:27]
reg flight_628; // @[FIFOFixer.scala:79:27]
reg flight_629; // @[FIFOFixer.scala:79:27]
reg flight_630; // @[FIFOFixer.scala:79:27]
reg flight_631; // @[FIFOFixer.scala:79:27]
reg flight_632; // @[FIFOFixer.scala:79:27]
reg flight_633; // @[FIFOFixer.scala:79:27]
reg flight_634; // @[FIFOFixer.scala:79:27]
reg flight_635; // @[FIFOFixer.scala:79:27]
reg flight_636; // @[FIFOFixer.scala:79:27]
reg flight_637; // @[FIFOFixer.scala:79:27]
reg flight_638; // @[FIFOFixer.scala:79:27]
reg flight_639; // @[FIFOFixer.scala:79:27]
reg flight_640; // @[FIFOFixer.scala:79:27]
reg flight_641; // @[FIFOFixer.scala:79:27]
reg flight_642; // @[FIFOFixer.scala:79:27]
reg flight_643; // @[FIFOFixer.scala:79:27]
reg flight_644; // @[FIFOFixer.scala:79:27]
reg flight_645; // @[FIFOFixer.scala:79:27]
reg flight_646; // @[FIFOFixer.scala:79:27]
reg flight_647; // @[FIFOFixer.scala:79:27]
reg flight_648; // @[FIFOFixer.scala:79:27]
reg flight_649; // @[FIFOFixer.scala:79:27]
reg flight_650; // @[FIFOFixer.scala:79:27]
reg flight_651; // @[FIFOFixer.scala:79:27]
reg flight_652; // @[FIFOFixer.scala:79:27]
reg flight_653; // @[FIFOFixer.scala:79:27]
reg flight_654; // @[FIFOFixer.scala:79:27]
reg flight_655; // @[FIFOFixer.scala:79:27]
reg flight_656; // @[FIFOFixer.scala:79:27]
reg flight_657; // @[FIFOFixer.scala:79:27]
reg flight_658; // @[FIFOFixer.scala:79:27]
reg flight_659; // @[FIFOFixer.scala:79:27]
reg flight_660; // @[FIFOFixer.scala:79:27]
reg flight_661; // @[FIFOFixer.scala:79:27]
reg flight_662; // @[FIFOFixer.scala:79:27]
reg flight_663; // @[FIFOFixer.scala:79:27]
reg flight_664; // @[FIFOFixer.scala:79:27]
reg flight_665; // @[FIFOFixer.scala:79:27]
reg flight_666; // @[FIFOFixer.scala:79:27]
reg flight_667; // @[FIFOFixer.scala:79:27]
reg flight_668; // @[FIFOFixer.scala:79:27]
reg flight_669; // @[FIFOFixer.scala:79:27]
reg flight_670; // @[FIFOFixer.scala:79:27]
reg flight_671; // @[FIFOFixer.scala:79:27]
reg flight_672; // @[FIFOFixer.scala:79:27]
reg flight_673; // @[FIFOFixer.scala:79:27]
reg flight_674; // @[FIFOFixer.scala:79:27]
reg flight_675; // @[FIFOFixer.scala:79:27]
reg flight_676; // @[FIFOFixer.scala:79:27]
reg flight_677; // @[FIFOFixer.scala:79:27]
reg flight_678; // @[FIFOFixer.scala:79:27]
reg flight_679; // @[FIFOFixer.scala:79:27]
reg flight_680; // @[FIFOFixer.scala:79:27]
reg flight_681; // @[FIFOFixer.scala:79:27]
reg flight_682; // @[FIFOFixer.scala:79:27]
reg flight_683; // @[FIFOFixer.scala:79:27]
reg flight_684; // @[FIFOFixer.scala:79:27]
reg flight_685; // @[FIFOFixer.scala:79:27]
reg flight_686; // @[FIFOFixer.scala:79:27]
reg flight_687; // @[FIFOFixer.scala:79:27]
reg flight_688; // @[FIFOFixer.scala:79:27]
reg flight_689; // @[FIFOFixer.scala:79:27]
reg flight_690; // @[FIFOFixer.scala:79:27]
reg flight_691; // @[FIFOFixer.scala:79:27]
reg flight_692; // @[FIFOFixer.scala:79:27]
reg flight_693; // @[FIFOFixer.scala:79:27]
reg flight_694; // @[FIFOFixer.scala:79:27]
reg flight_695; // @[FIFOFixer.scala:79:27]
reg flight_696; // @[FIFOFixer.scala:79:27]
reg flight_697; // @[FIFOFixer.scala:79:27]
reg flight_698; // @[FIFOFixer.scala:79:27]
reg flight_699; // @[FIFOFixer.scala:79:27]
reg flight_700; // @[FIFOFixer.scala:79:27]
reg flight_701; // @[FIFOFixer.scala:79:27]
reg flight_702; // @[FIFOFixer.scala:79:27]
reg flight_703; // @[FIFOFixer.scala:79:27]
reg flight_704; // @[FIFOFixer.scala:79:27]
reg flight_705; // @[FIFOFixer.scala:79:27]
reg flight_706; // @[FIFOFixer.scala:79:27]
reg flight_707; // @[FIFOFixer.scala:79:27]
reg flight_708; // @[FIFOFixer.scala:79:27]
reg flight_709; // @[FIFOFixer.scala:79:27]
reg flight_710; // @[FIFOFixer.scala:79:27]
reg flight_711; // @[FIFOFixer.scala:79:27]
reg flight_712; // @[FIFOFixer.scala:79:27]
reg flight_713; // @[FIFOFixer.scala:79:27]
reg flight_714; // @[FIFOFixer.scala:79:27]
reg flight_715; // @[FIFOFixer.scala:79:27]
reg flight_716; // @[FIFOFixer.scala:79:27]
reg flight_717; // @[FIFOFixer.scala:79:27]
reg flight_718; // @[FIFOFixer.scala:79:27]
reg flight_719; // @[FIFOFixer.scala:79:27]
reg flight_720; // @[FIFOFixer.scala:79:27]
reg flight_721; // @[FIFOFixer.scala:79:27]
reg flight_722; // @[FIFOFixer.scala:79:27]
reg flight_723; // @[FIFOFixer.scala:79:27]
reg flight_724; // @[FIFOFixer.scala:79:27]
reg flight_725; // @[FIFOFixer.scala:79:27]
reg flight_726; // @[FIFOFixer.scala:79:27]
reg flight_727; // @[FIFOFixer.scala:79:27]
reg flight_728; // @[FIFOFixer.scala:79:27]
reg flight_729; // @[FIFOFixer.scala:79:27]
reg flight_730; // @[FIFOFixer.scala:79:27]
reg flight_731; // @[FIFOFixer.scala:79:27]
reg flight_732; // @[FIFOFixer.scala:79:27]
reg flight_733; // @[FIFOFixer.scala:79:27]
reg flight_734; // @[FIFOFixer.scala:79:27]
reg flight_735; // @[FIFOFixer.scala:79:27]
reg flight_736; // @[FIFOFixer.scala:79:27]
reg flight_737; // @[FIFOFixer.scala:79:27]
reg flight_738; // @[FIFOFixer.scala:79:27]
reg flight_739; // @[FIFOFixer.scala:79:27]
reg flight_740; // @[FIFOFixer.scala:79:27]
reg flight_741; // @[FIFOFixer.scala:79:27]
reg flight_742; // @[FIFOFixer.scala:79:27]
reg flight_743; // @[FIFOFixer.scala:79:27]
reg flight_744; // @[FIFOFixer.scala:79:27]
reg flight_745; // @[FIFOFixer.scala:79:27]
reg flight_746; // @[FIFOFixer.scala:79:27]
reg flight_747; // @[FIFOFixer.scala:79:27]
reg flight_748; // @[FIFOFixer.scala:79:27]
reg flight_749; // @[FIFOFixer.scala:79:27]
reg flight_750; // @[FIFOFixer.scala:79:27]
reg flight_751; // @[FIFOFixer.scala:79:27]
reg flight_752; // @[FIFOFixer.scala:79:27]
reg flight_753; // @[FIFOFixer.scala:79:27]
reg flight_754; // @[FIFOFixer.scala:79:27]
reg flight_755; // @[FIFOFixer.scala:79:27]
reg flight_756; // @[FIFOFixer.scala:79:27]
reg flight_757; // @[FIFOFixer.scala:79:27]
reg flight_758; // @[FIFOFixer.scala:79:27]
reg flight_759; // @[FIFOFixer.scala:79:27]
reg flight_760; // @[FIFOFixer.scala:79:27]
reg flight_761; // @[FIFOFixer.scala:79:27]
reg flight_762; // @[FIFOFixer.scala:79:27]
reg flight_763; // @[FIFOFixer.scala:79:27]
reg flight_764; // @[FIFOFixer.scala:79:27]
reg flight_765; // @[FIFOFixer.scala:79:27]
reg flight_766; // @[FIFOFixer.scala:79:27]
reg flight_767; // @[FIFOFixer.scala:79:27]
reg flight_768; // @[FIFOFixer.scala:79:27]
reg flight_769; // @[FIFOFixer.scala:79:27]
reg flight_770; // @[FIFOFixer.scala:79:27]
reg flight_771; // @[FIFOFixer.scala:79:27]
reg flight_772; // @[FIFOFixer.scala:79:27]
reg flight_773; // @[FIFOFixer.scala:79:27]
reg flight_774; // @[FIFOFixer.scala:79:27]
reg flight_775; // @[FIFOFixer.scala:79:27]
reg flight_776; // @[FIFOFixer.scala:79:27]
reg flight_777; // @[FIFOFixer.scala:79:27]
reg flight_778; // @[FIFOFixer.scala:79:27]
reg flight_779; // @[FIFOFixer.scala:79:27]
reg flight_780; // @[FIFOFixer.scala:79:27]
reg flight_781; // @[FIFOFixer.scala:79:27]
reg flight_782; // @[FIFOFixer.scala:79:27]
reg flight_783; // @[FIFOFixer.scala:79:27]
reg flight_784; // @[FIFOFixer.scala:79:27]
reg flight_785; // @[FIFOFixer.scala:79:27]
reg flight_786; // @[FIFOFixer.scala:79:27]
reg flight_787; // @[FIFOFixer.scala:79:27]
reg flight_788; // @[FIFOFixer.scala:79:27]
reg flight_789; // @[FIFOFixer.scala:79:27]
reg flight_790; // @[FIFOFixer.scala:79:27]
reg flight_791; // @[FIFOFixer.scala:79:27]
reg flight_792; // @[FIFOFixer.scala:79:27]
reg flight_793; // @[FIFOFixer.scala:79:27]
reg flight_794; // @[FIFOFixer.scala:79:27]
reg flight_795; // @[FIFOFixer.scala:79:27]
reg flight_796; // @[FIFOFixer.scala:79:27]
reg flight_797; // @[FIFOFixer.scala:79:27]
reg flight_798; // @[FIFOFixer.scala:79:27]
reg flight_799; // @[FIFOFixer.scala:79:27]
reg flight_800; // @[FIFOFixer.scala:79:27]
reg flight_801; // @[FIFOFixer.scala:79:27]
reg flight_802; // @[FIFOFixer.scala:79:27]
reg flight_803; // @[FIFOFixer.scala:79:27]
reg flight_804; // @[FIFOFixer.scala:79:27]
reg flight_805; // @[FIFOFixer.scala:79:27]
reg flight_806; // @[FIFOFixer.scala:79:27]
reg flight_807; // @[FIFOFixer.scala:79:27]
reg flight_808; // @[FIFOFixer.scala:79:27]
reg flight_809; // @[FIFOFixer.scala:79:27]
reg flight_810; // @[FIFOFixer.scala:79:27]
reg flight_811; // @[FIFOFixer.scala:79:27]
reg flight_812; // @[FIFOFixer.scala:79:27]
reg flight_813; // @[FIFOFixer.scala:79:27]
reg flight_814; // @[FIFOFixer.scala:79:27]
reg flight_815; // @[FIFOFixer.scala:79:27]
reg flight_816; // @[FIFOFixer.scala:79:27]
reg flight_817; // @[FIFOFixer.scala:79:27]
reg flight_818; // @[FIFOFixer.scala:79:27]
reg flight_819; // @[FIFOFixer.scala:79:27]
reg flight_820; // @[FIFOFixer.scala:79:27]
reg flight_821; // @[FIFOFixer.scala:79:27]
reg flight_822; // @[FIFOFixer.scala:79:27]
reg flight_823; // @[FIFOFixer.scala:79:27]
reg flight_824; // @[FIFOFixer.scala:79:27]
reg flight_825; // @[FIFOFixer.scala:79:27]
reg flight_826; // @[FIFOFixer.scala:79:27]
reg flight_827; // @[FIFOFixer.scala:79:27]
reg flight_828; // @[FIFOFixer.scala:79:27]
reg flight_829; // @[FIFOFixer.scala:79:27]
reg flight_830; // @[FIFOFixer.scala:79:27]
reg flight_831; // @[FIFOFixer.scala:79:27]
reg flight_832; // @[FIFOFixer.scala:79:27]
reg flight_833; // @[FIFOFixer.scala:79:27]
reg flight_834; // @[FIFOFixer.scala:79:27]
reg flight_835; // @[FIFOFixer.scala:79:27]
reg flight_836; // @[FIFOFixer.scala:79:27]
reg flight_837; // @[FIFOFixer.scala:79:27]
reg flight_838; // @[FIFOFixer.scala:79:27]
reg flight_839; // @[FIFOFixer.scala:79:27]
reg flight_840; // @[FIFOFixer.scala:79:27]
reg flight_841; // @[FIFOFixer.scala:79:27]
reg flight_842; // @[FIFOFixer.scala:79:27]
reg flight_843; // @[FIFOFixer.scala:79:27]
reg flight_844; // @[FIFOFixer.scala:79:27]
reg flight_845; // @[FIFOFixer.scala:79:27]
reg flight_846; // @[FIFOFixer.scala:79:27]
reg flight_847; // @[FIFOFixer.scala:79:27]
reg flight_848; // @[FIFOFixer.scala:79:27]
reg flight_849; // @[FIFOFixer.scala:79:27]
reg flight_850; // @[FIFOFixer.scala:79:27]
reg flight_851; // @[FIFOFixer.scala:79:27]
reg flight_852; // @[FIFOFixer.scala:79:27]
reg flight_853; // @[FIFOFixer.scala:79:27]
reg flight_854; // @[FIFOFixer.scala:79:27]
reg flight_855; // @[FIFOFixer.scala:79:27]
reg flight_856; // @[FIFOFixer.scala:79:27]
reg flight_857; // @[FIFOFixer.scala:79:27]
reg flight_858; // @[FIFOFixer.scala:79:27]
reg flight_859; // @[FIFOFixer.scala:79:27]
reg flight_860; // @[FIFOFixer.scala:79:27]
reg flight_861; // @[FIFOFixer.scala:79:27]
reg flight_862; // @[FIFOFixer.scala:79:27]
reg flight_863; // @[FIFOFixer.scala:79:27]
reg flight_864; // @[FIFOFixer.scala:79:27]
reg flight_865; // @[FIFOFixer.scala:79:27]
reg flight_866; // @[FIFOFixer.scala:79:27]
reg flight_867; // @[FIFOFixer.scala:79:27]
reg flight_868; // @[FIFOFixer.scala:79:27]
reg flight_869; // @[FIFOFixer.scala:79:27]
reg flight_870; // @[FIFOFixer.scala:79:27]
reg flight_871; // @[FIFOFixer.scala:79:27]
reg flight_872; // @[FIFOFixer.scala:79:27]
reg flight_873; // @[FIFOFixer.scala:79:27]
reg flight_874; // @[FIFOFixer.scala:79:27]
reg flight_875; // @[FIFOFixer.scala:79:27]
reg flight_876; // @[FIFOFixer.scala:79:27]
reg flight_877; // @[FIFOFixer.scala:79:27]
reg flight_878; // @[FIFOFixer.scala:79:27]
reg flight_879; // @[FIFOFixer.scala:79:27]
reg flight_880; // @[FIFOFixer.scala:79:27]
reg flight_881; // @[FIFOFixer.scala:79:27]
reg flight_882; // @[FIFOFixer.scala:79:27]
reg flight_883; // @[FIFOFixer.scala:79:27]
reg flight_884; // @[FIFOFixer.scala:79:27]
reg flight_885; // @[FIFOFixer.scala:79:27]
reg flight_886; // @[FIFOFixer.scala:79:27]
reg flight_887; // @[FIFOFixer.scala:79:27]
reg flight_888; // @[FIFOFixer.scala:79:27]
reg flight_889; // @[FIFOFixer.scala:79:27]
reg flight_890; // @[FIFOFixer.scala:79:27]
reg flight_891; // @[FIFOFixer.scala:79:27]
reg flight_892; // @[FIFOFixer.scala:79:27]
reg flight_893; // @[FIFOFixer.scala:79:27]
reg flight_894; // @[FIFOFixer.scala:79:27]
reg flight_895; // @[FIFOFixer.scala:79:27]
reg flight_896; // @[FIFOFixer.scala:79:27]
reg flight_897; // @[FIFOFixer.scala:79:27]
reg flight_898; // @[FIFOFixer.scala:79:27]
reg flight_899; // @[FIFOFixer.scala:79:27]
reg flight_900; // @[FIFOFixer.scala:79:27]
reg flight_901; // @[FIFOFixer.scala:79:27]
reg flight_902; // @[FIFOFixer.scala:79:27]
reg flight_903; // @[FIFOFixer.scala:79:27]
reg flight_904; // @[FIFOFixer.scala:79:27]
reg flight_905; // @[FIFOFixer.scala:79:27]
reg flight_906; // @[FIFOFixer.scala:79:27]
reg flight_907; // @[FIFOFixer.scala:79:27]
reg flight_908; // @[FIFOFixer.scala:79:27]
reg flight_909; // @[FIFOFixer.scala:79:27]
reg flight_910; // @[FIFOFixer.scala:79:27]
reg flight_911; // @[FIFOFixer.scala:79:27]
reg flight_912; // @[FIFOFixer.scala:79:27]
reg flight_913; // @[FIFOFixer.scala:79:27]
reg flight_914; // @[FIFOFixer.scala:79:27]
reg flight_915; // @[FIFOFixer.scala:79:27]
reg flight_916; // @[FIFOFixer.scala:79:27]
reg flight_917; // @[FIFOFixer.scala:79:27]
reg flight_918; // @[FIFOFixer.scala:79:27]
reg flight_919; // @[FIFOFixer.scala:79:27]
reg flight_920; // @[FIFOFixer.scala:79:27]
reg flight_921; // @[FIFOFixer.scala:79:27]
reg flight_922; // @[FIFOFixer.scala:79:27]
reg flight_923; // @[FIFOFixer.scala:79:27]
reg flight_924; // @[FIFOFixer.scala:79:27]
reg flight_925; // @[FIFOFixer.scala:79:27]
reg flight_926; // @[FIFOFixer.scala:79:27]
reg flight_927; // @[FIFOFixer.scala:79:27]
reg flight_928; // @[FIFOFixer.scala:79:27]
reg flight_929; // @[FIFOFixer.scala:79:27]
reg flight_930; // @[FIFOFixer.scala:79:27]
reg flight_931; // @[FIFOFixer.scala:79:27]
reg flight_932; // @[FIFOFixer.scala:79:27]
reg flight_933; // @[FIFOFixer.scala:79:27]
reg flight_934; // @[FIFOFixer.scala:79:27]
reg flight_935; // @[FIFOFixer.scala:79:27]
reg flight_936; // @[FIFOFixer.scala:79:27]
reg flight_937; // @[FIFOFixer.scala:79:27]
reg flight_938; // @[FIFOFixer.scala:79:27]
reg flight_939; // @[FIFOFixer.scala:79:27]
reg flight_940; // @[FIFOFixer.scala:79:27]
reg flight_941; // @[FIFOFixer.scala:79:27]
reg flight_942; // @[FIFOFixer.scala:79:27]
reg flight_943; // @[FIFOFixer.scala:79:27]
reg flight_944; // @[FIFOFixer.scala:79:27]
reg flight_945; // @[FIFOFixer.scala:79:27]
reg flight_946; // @[FIFOFixer.scala:79:27]
reg flight_947; // @[FIFOFixer.scala:79:27]
reg flight_948; // @[FIFOFixer.scala:79:27]
reg flight_949; // @[FIFOFixer.scala:79:27]
reg flight_950; // @[FIFOFixer.scala:79:27]
reg flight_951; // @[FIFOFixer.scala:79:27]
reg flight_952; // @[FIFOFixer.scala:79:27]
reg flight_953; // @[FIFOFixer.scala:79:27]
reg flight_954; // @[FIFOFixer.scala:79:27]
reg flight_955; // @[FIFOFixer.scala:79:27]
reg flight_956; // @[FIFOFixer.scala:79:27]
reg flight_957; // @[FIFOFixer.scala:79:27]
reg flight_958; // @[FIFOFixer.scala:79:27]
reg flight_959; // @[FIFOFixer.scala:79:27]
reg flight_960; // @[FIFOFixer.scala:79:27]
reg flight_961; // @[FIFOFixer.scala:79:27]
reg flight_962; // @[FIFOFixer.scala:79:27]
reg flight_963; // @[FIFOFixer.scala:79:27]
reg flight_964; // @[FIFOFixer.scala:79:27]
reg flight_965; // @[FIFOFixer.scala:79:27]
reg flight_966; // @[FIFOFixer.scala:79:27]
reg flight_967; // @[FIFOFixer.scala:79:27]
reg flight_968; // @[FIFOFixer.scala:79:27]
reg flight_969; // @[FIFOFixer.scala:79:27]
reg flight_970; // @[FIFOFixer.scala:79:27]
reg flight_971; // @[FIFOFixer.scala:79:27]
reg flight_972; // @[FIFOFixer.scala:79:27]
reg flight_973; // @[FIFOFixer.scala:79:27]
reg flight_974; // @[FIFOFixer.scala:79:27]
reg flight_975; // @[FIFOFixer.scala:79:27]
reg flight_976; // @[FIFOFixer.scala:79:27]
reg flight_977; // @[FIFOFixer.scala:79:27]
reg flight_978; // @[FIFOFixer.scala:79:27]
reg flight_979; // @[FIFOFixer.scala:79:27]
reg flight_980; // @[FIFOFixer.scala:79:27]
reg flight_981; // @[FIFOFixer.scala:79:27]
reg flight_982; // @[FIFOFixer.scala:79:27]
reg flight_983; // @[FIFOFixer.scala:79:27]
reg flight_984; // @[FIFOFixer.scala:79:27]
reg flight_985; // @[FIFOFixer.scala:79:27]
reg flight_986; // @[FIFOFixer.scala:79:27]
reg flight_987; // @[FIFOFixer.scala:79:27]
reg flight_988; // @[FIFOFixer.scala:79:27]
reg flight_989; // @[FIFOFixer.scala:79:27]
reg flight_990; // @[FIFOFixer.scala:79:27]
reg flight_991; // @[FIFOFixer.scala:79:27]
reg flight_992; // @[FIFOFixer.scala:79:27]
reg flight_993; // @[FIFOFixer.scala:79:27]
reg flight_994; // @[FIFOFixer.scala:79:27]
reg flight_995; // @[FIFOFixer.scala:79:27]
reg flight_996; // @[FIFOFixer.scala:79:27]
reg flight_997; // @[FIFOFixer.scala:79:27]
reg flight_998; // @[FIFOFixer.scala:79:27]
reg flight_999; // @[FIFOFixer.scala:79:27]
reg flight_1000; // @[FIFOFixer.scala:79:27]
reg flight_1001; // @[FIFOFixer.scala:79:27]
reg flight_1002; // @[FIFOFixer.scala:79:27]
reg flight_1003; // @[FIFOFixer.scala:79:27]
reg flight_1004; // @[FIFOFixer.scala:79:27]
reg flight_1005; // @[FIFOFixer.scala:79:27]
reg flight_1006; // @[FIFOFixer.scala:79:27]
reg flight_1007; // @[FIFOFixer.scala:79:27]
reg flight_1008; // @[FIFOFixer.scala:79:27]
reg flight_1009; // @[FIFOFixer.scala:79:27]
reg flight_1010; // @[FIFOFixer.scala:79:27]
reg flight_1011; // @[FIFOFixer.scala:79:27]
reg flight_1012; // @[FIFOFixer.scala:79:27]
reg flight_1013; // @[FIFOFixer.scala:79:27]
reg flight_1014; // @[FIFOFixer.scala:79:27]
reg flight_1015; // @[FIFOFixer.scala:79:27]
reg flight_1016; // @[FIFOFixer.scala:79:27]
reg flight_1017; // @[FIFOFixer.scala:79:27]
reg flight_1018; // @[FIFOFixer.scala:79:27]
reg flight_1019; // @[FIFOFixer.scala:79:27]
reg flight_1020; // @[FIFOFixer.scala:79:27]
reg flight_1021; // @[FIFOFixer.scala:79:27]
reg flight_1022; // @[FIFOFixer.scala:79:27]
reg flight_1023; // @[FIFOFixer.scala:79:27]
reg flight_1024; // @[FIFOFixer.scala:79:27]
reg flight_1025; // @[FIFOFixer.scala:79:27]
reg flight_1026; // @[FIFOFixer.scala:79:27]
reg flight_1027; // @[FIFOFixer.scala:79:27]
reg flight_1028; // @[FIFOFixer.scala:79:27]
reg flight_1029; // @[FIFOFixer.scala:79:27]
reg flight_1030; // @[FIFOFixer.scala:79:27]
reg flight_1031; // @[FIFOFixer.scala:79:27]
reg flight_1032; // @[FIFOFixer.scala:79:27]
reg flight_1033; // @[FIFOFixer.scala:79:27]
reg flight_1034; // @[FIFOFixer.scala:79:27]
reg flight_1035; // @[FIFOFixer.scala:79:27]
reg flight_1036; // @[FIFOFixer.scala:79:27]
reg flight_1037; // @[FIFOFixer.scala:79:27]
reg flight_1038; // @[FIFOFixer.scala:79:27]
reg flight_1039; // @[FIFOFixer.scala:79:27]
wire stalls_a_sel = auto_anon_in_a_bits_source < 11'h410; // @[Parameters.scala:57:20]
reg [1:0] stalls_id; // @[FIFOFixer.scala:85:30]
wire _GEN =
flight_0 | flight_1 | flight_2 | flight_3 | flight_4 | flight_5 | flight_6 | flight_7 | flight_8 | flight_9 | flight_10 | flight_11 | flight_12 | flight_13 | flight_14 | flight_15 | flight_16 | flight_17 | flight_18 | flight_19 | flight_20 | flight_21 | flight_22 | flight_23 | flight_24 | flight_25 | flight_26 | flight_27 | flight_28 | flight_29 | flight_30 | flight_31 | flight_32 | flight_33 | flight_34 | flight_35 | flight_36 | flight_37 | flight_38 | flight_39 | flight_40 | flight_41 | flight_42 | flight_43 | flight_44 | flight_45 | flight_46 | flight_47 | flight_48 | flight_49 | flight_50 | flight_51 | flight_52 | flight_53 | flight_54 | flight_55 | flight_56 | flight_57 | flight_58 | flight_59 | flight_60 | flight_61 | flight_62 | flight_63 | flight_64 | flight_65 | flight_66 | flight_67 | flight_68 | flight_69 | flight_70 | flight_71 | flight_72 | flight_73 | flight_74 | flight_75 | flight_76 | flight_77 | flight_78 | flight_79 | flight_80 | flight_81 | flight_82 | flight_83 | flight_84 | flight_85 | flight_86 | flight_87 | flight_88 | flight_89 | flight_90 | flight_91 | flight_92 | flight_93 | flight_94 | flight_95 | flight_96 | flight_97 | flight_98 | flight_99 | flight_100 | flight_101 | flight_102 | flight_103 | flight_104 | flight_105 | flight_106 | flight_107 | flight_108 | flight_109 | flight_110 | flight_111 | flight_112 | flight_113 | flight_114 | flight_115 | flight_116 | flight_117 | flight_118 | flight_119 | flight_120 | flight_121 | flight_122 | flight_123 | flight_124 | flight_125 | flight_126 | flight_127 | flight_128 | flight_129 | flight_130 | flight_131 | flight_132 | flight_133 | flight_134 | flight_135 | flight_136 | flight_137 | flight_138 | flight_139 | flight_140 | flight_141 | flight_142 | flight_143 | flight_144 | flight_145 | flight_146 | flight_147 | flight_148 | flight_149 | flight_150 | flight_151 | flight_152 | flight_153 | flight_154 | flight_155 | flight_156 | flight_157 | flight_158 | flight_159 | flight_160 | flight_161 | flight_162 | flight_163 | flight_164
| flight_165 | flight_166 | flight_167 | flight_168 | flight_169 | flight_170 | flight_171 | flight_172 | flight_173 | flight_174 | flight_175 | flight_176 | flight_177 | flight_178 | flight_179 | flight_180 | flight_181 | flight_182 | flight_183 | flight_184 | flight_185 | flight_186 | flight_187 | flight_188 | flight_189 | flight_190 | flight_191 | flight_192 | flight_193 | flight_194 | flight_195 | flight_196 | flight_197 | flight_198 | flight_199 | flight_200 | flight_201 | flight_202 | flight_203 | flight_204 | flight_205 | flight_206 | flight_207 | flight_208 | flight_209 | flight_210 | flight_211 | flight_212 | flight_213 | flight_214 | flight_215 | flight_216 | flight_217 | flight_218 | flight_219 | flight_220 | flight_221 | flight_222 | flight_223 | flight_224 | flight_225 | flight_226 | flight_227 | flight_228 | flight_229 | flight_230 | flight_231 | flight_232 | flight_233 | flight_234 | flight_235 | flight_236 | flight_237 | flight_238 | flight_239 | flight_240 | flight_241 | flight_242 | flight_243 | flight_244 | flight_245 | flight_246 | flight_247 | flight_248 | flight_249 | flight_250 | flight_251 | flight_252 | flight_253 | flight_254 | flight_255 | flight_256 | flight_257 | flight_258 | flight_259; // @[FIFOFixer.scala:79:27, :88:44]
wire _GEN_0 =
flight_260 | flight_261 | flight_262 | flight_263 | flight_264 | flight_265 | flight_266 | flight_267 | flight_268 | flight_269 | flight_270 | flight_271 | flight_272 | flight_273 | flight_274 | flight_275 | flight_276 | flight_277 | flight_278 | flight_279 | flight_280 | flight_281 | flight_282 | flight_283 | flight_284 | flight_285 | flight_286 | flight_287 | flight_288 | flight_289 | flight_290 | flight_291 | flight_292 | flight_293 | flight_294 | flight_295 | flight_296 | flight_297 | flight_298 | flight_299 | flight_300 | flight_301 | flight_302 | flight_303 | flight_304 | flight_305 | flight_306 | flight_307 | flight_308 | flight_309 | flight_310 | flight_311 | flight_312 | flight_313 | flight_314 | flight_315 | flight_316 | flight_317 | flight_318 | flight_319 | flight_320 | flight_321 | flight_322 | flight_323 | flight_324 | flight_325 | flight_326 | flight_327 | flight_328 | flight_329 | flight_330 | flight_331 | flight_332 | flight_333 | flight_334 | flight_335 | flight_336 | flight_337 | flight_338 | flight_339 | flight_340 | flight_341 | flight_342 | flight_343 | flight_344 | flight_345 | flight_346 | flight_347 | flight_348 | flight_349 | flight_350 | flight_351 | flight_352 | flight_353 | flight_354 | flight_355 | flight_356 | flight_357 | flight_358 | flight_359 | flight_360 | flight_361 | flight_362 | flight_363 | flight_364 | flight_365 | flight_366 | flight_367 | flight_368 | flight_369 | flight_370 | flight_371 | flight_372 | flight_373 | flight_374 | flight_375 | flight_376 | flight_377 | flight_378 | flight_379 | flight_380 | flight_381 | flight_382 | flight_383 | flight_384 | flight_385 | flight_386 | flight_387 | flight_388 | flight_389 | flight_390 | flight_391 | flight_392 | flight_393 | flight_394 | flight_395 | flight_396 | flight_397 | flight_398 | flight_399 | flight_400 | flight_401 | flight_402 | flight_403 | flight_404 | flight_405 | flight_406 | flight_407 | flight_408 | flight_409 | flight_410 | flight_411 | flight_412 | flight_413 | flight_414 | flight_415 | flight_416
| flight_417 | flight_418 | flight_419 | flight_420 | flight_421 | flight_422 | flight_423 | flight_424 | flight_425 | flight_426 | flight_427 | flight_428 | flight_429 | flight_430 | flight_431 | flight_432 | flight_433 | flight_434 | flight_435 | flight_436 | flight_437 | flight_438 | flight_439 | flight_440 | flight_441 | flight_442 | flight_443 | flight_444 | flight_445 | flight_446 | flight_447 | flight_448 | flight_449 | flight_450 | flight_451 | flight_452 | flight_453 | flight_454 | flight_455 | flight_456 | flight_457 | flight_458 | flight_459 | flight_460 | flight_461 | flight_462 | flight_463 | flight_464 | flight_465 | flight_466 | flight_467 | flight_468 | flight_469 | flight_470 | flight_471 | flight_472 | flight_473 | flight_474 | flight_475 | flight_476 | flight_477 | flight_478 | flight_479 | flight_480 | flight_481 | flight_482 | flight_483 | flight_484 | flight_485 | flight_486 | flight_487 | flight_488 | flight_489 | flight_490 | flight_491 | flight_492 | flight_493 | flight_494 | flight_495 | flight_496 | flight_497 | flight_498 | flight_499 | flight_500 | flight_501 | flight_502 | flight_503 | flight_504 | flight_505 | flight_506 | flight_507 | flight_508 | flight_509 | flight_510 | flight_511 | flight_512 | flight_513 | flight_514 | flight_515 | flight_516 | flight_517 | flight_518 | flight_519; // @[FIFOFixer.scala:79:27, :88:44]
wire _GEN_1 =
flight_520 | flight_521 | flight_522 | flight_523 | flight_524 | flight_525 | flight_526 | flight_527 | flight_528 | flight_529 | flight_530 | flight_531 | flight_532 | flight_533 | flight_534 | flight_535 | flight_536 | flight_537 | flight_538 | flight_539 | flight_540 | flight_541 | flight_542 | flight_543 | flight_544 | flight_545 | flight_546 | flight_547 | flight_548 | flight_549 | flight_550 | flight_551 | flight_552 | flight_553 | flight_554 | flight_555 | flight_556 | flight_557 | flight_558 | flight_559 | flight_560 | flight_561 | flight_562 | flight_563 | flight_564 | flight_565 | flight_566 | flight_567 | flight_568 | flight_569 | flight_570 | flight_571 | flight_572 | flight_573 | flight_574 | flight_575 | flight_576 | flight_577 | flight_578 | flight_579 | flight_580 | flight_581 | flight_582 | flight_583 | flight_584 | flight_585 | flight_586 | flight_587 | flight_588 | flight_589 | flight_590 | flight_591 | flight_592 | flight_593 | flight_594 | flight_595 | flight_596 | flight_597 | flight_598 | flight_599 | flight_600 | flight_601 | flight_602 | flight_603 | flight_604 | flight_605 | flight_606 | flight_607 | flight_608 | flight_609 | flight_610 | flight_611 | flight_612 | flight_613 | flight_614 | flight_615 | flight_616 | flight_617 | flight_618 | flight_619 | flight_620 | flight_621 | flight_622 | flight_623 | flight_624 | flight_625 | flight_626 | flight_627 | flight_628 | flight_629 | flight_630 | flight_631 | flight_632 | flight_633 | flight_634 | flight_635 | flight_636 | flight_637 | flight_638 | flight_639 | flight_640 | flight_641 | flight_642 | flight_643 | flight_644 | flight_645 | flight_646 | flight_647 | flight_648 | flight_649 | flight_650 | flight_651 | flight_652 | flight_653 | flight_654 | flight_655 | flight_656 | flight_657 | flight_658 | flight_659 | flight_660 | flight_661 | flight_662 | flight_663 | flight_664 | flight_665 | flight_666 | flight_667 | flight_668 | flight_669 | flight_670 | flight_671 | flight_672 | flight_673 | flight_674 | flight_675 | flight_676
| flight_677 | flight_678 | flight_679 | flight_680 | flight_681 | flight_682 | flight_683 | flight_684 | flight_685 | flight_686 | flight_687 | flight_688 | flight_689 | flight_690 | flight_691 | flight_692 | flight_693 | flight_694 | flight_695 | flight_696 | flight_697 | flight_698 | flight_699 | flight_700 | flight_701 | flight_702 | flight_703 | flight_704 | flight_705 | flight_706 | flight_707 | flight_708 | flight_709 | flight_710 | flight_711 | flight_712 | flight_713 | flight_714 | flight_715 | flight_716 | flight_717 | flight_718 | flight_719 | flight_720 | flight_721 | flight_722 | flight_723 | flight_724 | flight_725 | flight_726 | flight_727 | flight_728 | flight_729 | flight_730 | flight_731 | flight_732 | flight_733 | flight_734 | flight_735 | flight_736 | flight_737 | flight_738 | flight_739 | flight_740 | flight_741 | flight_742 | flight_743 | flight_744 | flight_745 | flight_746 | flight_747 | flight_748 | flight_749 | flight_750 | flight_751 | flight_752 | flight_753 | flight_754 | flight_755 | flight_756 | flight_757 | flight_758 | flight_759 | flight_760 | flight_761 | flight_762 | flight_763 | flight_764 | flight_765 | flight_766 | flight_767 | flight_768 | flight_769 | flight_770 | flight_771 | flight_772 | flight_773 | flight_774 | flight_775 | flight_776 | flight_777 | flight_778 | flight_779; // @[FIFOFixer.scala:79:27, :88:44]
wire _GEN_2 =
flight_780 | flight_781 | flight_782 | flight_783 | flight_784 | flight_785 | flight_786 | flight_787 | flight_788 | flight_789 | flight_790 | flight_791 | flight_792 | flight_793 | flight_794 | flight_795 | flight_796 | flight_797 | flight_798 | flight_799 | flight_800 | flight_801 | flight_802 | flight_803 | flight_804 | flight_805 | flight_806 | flight_807 | flight_808 | flight_809 | flight_810 | flight_811 | flight_812 | flight_813 | flight_814 | flight_815 | flight_816 | flight_817 | flight_818 | flight_819 | flight_820 | flight_821 | flight_822 | flight_823 | flight_824 | flight_825 | flight_826 | flight_827 | flight_828 | flight_829 | flight_830 | flight_831 | flight_832 | flight_833 | flight_834 | flight_835 | flight_836 | flight_837 | flight_838 | flight_839 | flight_840 | flight_841 | flight_842 | flight_843 | flight_844 | flight_845 | flight_846 | flight_847 | flight_848 | flight_849 | flight_850 | flight_851 | flight_852 | flight_853 | flight_854 | flight_855 | flight_856 | flight_857 | flight_858 | flight_859 | flight_860 | flight_861 | flight_862 | flight_863 | flight_864 | flight_865 | flight_866 | flight_867 | flight_868 | flight_869 | flight_870 | flight_871 | flight_872 | flight_873 | flight_874 | flight_875 | flight_876 | flight_877 | flight_878 | flight_879 | flight_880 | flight_881 | flight_882 | flight_883 | flight_884 | flight_885 | flight_886 | flight_887 | flight_888 | flight_889 | flight_890 | flight_891 | flight_892 | flight_893 | flight_894 | flight_895 | flight_896 | flight_897 | flight_898 | flight_899 | flight_900 | flight_901 | flight_902 | flight_903 | flight_904 | flight_905 | flight_906 | flight_907 | flight_908 | flight_909 | flight_910 | flight_911 | flight_912 | flight_913 | flight_914 | flight_915 | flight_916 | flight_917 | flight_918 | flight_919 | flight_920 | flight_921 | flight_922 | flight_923 | flight_924 | flight_925 | flight_926 | flight_927 | flight_928 | flight_929 | flight_930 | flight_931 | flight_932 | flight_933 | flight_934 | flight_935 | flight_936
| flight_937 | flight_938 | flight_939 | flight_940 | flight_941 | flight_942 | flight_943 | flight_944 | flight_945 | flight_946 | flight_947 | flight_948 | flight_949 | flight_950 | flight_951 | flight_952 | flight_953 | flight_954 | flight_955 | flight_956 | flight_957 | flight_958 | flight_959 | flight_960 | flight_961 | flight_962 | flight_963 | flight_964 | flight_965 | flight_966 | flight_967 | flight_968 | flight_969 | flight_970 | flight_971 | flight_972 | flight_973 | flight_974 | flight_975 | flight_976 | flight_977 | flight_978 | flight_979 | flight_980 | flight_981 | flight_982 | flight_983 | flight_984 | flight_985 | flight_986 | flight_987 | flight_988 | flight_989 | flight_990 | flight_991 | flight_992 | flight_993 | flight_994 | flight_995 | flight_996 | flight_997 | flight_998 | flight_999 | flight_1000 | flight_1001 | flight_1002 | flight_1003 | flight_1004 | flight_1005 | flight_1006 | flight_1007 | flight_1008 | flight_1009 | flight_1010 | flight_1011 | flight_1012 | flight_1013 | flight_1014 | flight_1015 | flight_1016 | flight_1017 | flight_1018 | flight_1019 | flight_1020 | flight_1021 | flight_1022 | flight_1023 | flight_1024 | flight_1025 | flight_1026 | flight_1027 | flight_1028 | flight_1029 | flight_1030 | flight_1031 | flight_1032 | flight_1033 | flight_1034 | flight_1035 | flight_1036 | flight_1037 | flight_1038 | flight_1039; // @[FIFOFixer.scala:79:27, :88:44]
wire stall = stalls_a_sel & ~a_first_counter & (_GEN | _GEN_0 | _GEN_1 | _GEN_2) & (a_id == 2'h0 | stalls_id != a_id); // @[Mux.scala:30:73]
wire anonIn_a_ready = auto_anon_out_a_ready & ~stall; // @[FIFOFixer.scala:88:{15,26,50}, :95:50, :96:33]
wire _GEN_3 = ~d_first_counter & auto_anon_out_d_bits_opcode != 3'h6 & auto_anon_in_d_ready & auto_anon_out_d_valid; // @[Decoupled.scala:51:35]
wire a_first_done = anonIn_a_ready & auto_anon_in_a_valid; // @[Decoupled.scala:51:35]
wire _GEN_4 = ~a_first_counter & a_first_done; // @[Decoupled.scala:51:35]
always @(posedge clock) begin // @[FIFOFixer.scala:50:9]
if (reset) begin // @[FIFOFixer.scala:50:9]
a_first_counter <= 1'h0; // @[Edges.scala:229:27]
d_first_counter <= 1'h0; // @[Edges.scala:229:27]
flight_0 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_1 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_2 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_3 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_4 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_5 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_6 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_7 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_8 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_9 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_10 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_11 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_12 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_13 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_14 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_15 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_16 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_17 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_18 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_19 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_20 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_21 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_22 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_23 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_24 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_25 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_26 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_27 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_28 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_29 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_30 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_31 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_32 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_33 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_34 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_35 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_36 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_37 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_38 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_39 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_40 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_41 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_42 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_43 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_44 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_45 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_46 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_47 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_48 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_49 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_50 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_51 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_52 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_53 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_54 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_55 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_56 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_57 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_58 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_59 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_60 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_61 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_62 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_63 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_64 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_65 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_66 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_67 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_68 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_69 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_70 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_71 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_72 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_73 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_74 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_75 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_76 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_77 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_78 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_79 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_80 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_81 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_82 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_83 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_84 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_85 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_86 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_87 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_88 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_89 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_90 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_91 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_92 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_93 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_94 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_95 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_96 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_97 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_98 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_99 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_100 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_101 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_102 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_103 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_104 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_105 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_106 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_107 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_108 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_109 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_110 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_111 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_112 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_113 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_114 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_115 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_116 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_117 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_118 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_119 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_120 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_121 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_122 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_123 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_124 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_125 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_126 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_127 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_128 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_129 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_130 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_131 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_132 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_133 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_134 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_135 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_136 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_137 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_138 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_139 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_140 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_141 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_142 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_143 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_144 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_145 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_146 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_147 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_148 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_149 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_150 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_151 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_152 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_153 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_154 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_155 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_156 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_157 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_158 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_159 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_160 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_161 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_162 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_163 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_164 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_165 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_166 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_167 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_168 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_169 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_170 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_171 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_172 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_173 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_174 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_175 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_176 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_177 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_178 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_179 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_180 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_181 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_182 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_183 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_184 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_185 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_186 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_187 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_188 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_189 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_190 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_191 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_192 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_193 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_194 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_195 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_196 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_197 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_198 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_199 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_200 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_201 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_202 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_203 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_204 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_205 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_206 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_207 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_208 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_209 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_210 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_211 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_212 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_213 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_214 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_215 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_216 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_217 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_218 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_219 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_220 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_221 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_222 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_223 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_224 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_225 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_226 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_227 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_228 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_229 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_230 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_231 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_232 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_233 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_234 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_235 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_236 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_237 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_238 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_239 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_240 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_241 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_242 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_243 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_244 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_245 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_246 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_247 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_248 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_249 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_250 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_251 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_252 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_253 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_254 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_255 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_256 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_257 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_258 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_259 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_260 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_261 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_262 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_263 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_264 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_265 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_266 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_267 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_268 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_269 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_270 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_271 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_272 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_273 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_274 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_275 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_276 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_277 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_278 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_279 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_280 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_281 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_282 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_283 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_284 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_285 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_286 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_287 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_288 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_289 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_290 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_291 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_292 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_293 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_294 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_295 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_296 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_297 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_298 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_299 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_300 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_301 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_302 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_303 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_304 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_305 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_306 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_307 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_308 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_309 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_310 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_311 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_312 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_313 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_314 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_315 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_316 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_317 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_318 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_319 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_320 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_321 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_322 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_323 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_324 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_325 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_326 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_327 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_328 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_329 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_330 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_331 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_332 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_333 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_334 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_335 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_336 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_337 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_338 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_339 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_340 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_341 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_342 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_343 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_344 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_345 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_346 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_347 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_348 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_349 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_350 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_351 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_352 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_353 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_354 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_355 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_356 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_357 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_358 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_359 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_360 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_361 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_362 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_363 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_364 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_365 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_366 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_367 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_368 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_369 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_370 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_371 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_372 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_373 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_374 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_375 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_376 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_377 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_378 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_379 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_380 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_381 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_382 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_383 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_384 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_385 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_386 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_387 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_388 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_389 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_390 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_391 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_392 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_393 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_394 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_395 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_396 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_397 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_398 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_399 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_400 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_401 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_402 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_403 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_404 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_405 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_406 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_407 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_408 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_409 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_410 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_411 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_412 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_413 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_414 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_415 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_416 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_417 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_418 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_419 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_420 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_421 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_422 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_423 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_424 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_425 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_426 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_427 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_428 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_429 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_430 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_431 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_432 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_433 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_434 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_435 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_436 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_437 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_438 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_439 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_440 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_441 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_442 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_443 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_444 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_445 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_446 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_447 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_448 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_449 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_450 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_451 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_452 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_453 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_454 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_455 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_456 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_457 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_458 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_459 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_460 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_461 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_462 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_463 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_464 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_465 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_466 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_467 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_468 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_469 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_470 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_471 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_472 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_473 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_474 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_475 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_476 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_477 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_478 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_479 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_480 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_481 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_482 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_483 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_484 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_485 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_486 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_487 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_488 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_489 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_490 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_491 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_492 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_493 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_494 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_495 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_496 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_497 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_498 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_499 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_500 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_501 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_502 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_503 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_504 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_505 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_506 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_507 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_508 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_509 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_510 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_511 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_512 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_513 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_514 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_515 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_516 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_517 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_518 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_519 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_520 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_521 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_522 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_523 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_524 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_525 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_526 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_527 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_528 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_529 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_530 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_531 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_532 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_533 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_534 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_535 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_536 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_537 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_538 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_539 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_540 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_541 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_542 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_543 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_544 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_545 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_546 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_547 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_548 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_549 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_550 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_551 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_552 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_553 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_554 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_555 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_556 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_557 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_558 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_559 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_560 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_561 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_562 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_563 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_564 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_565 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_566 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_567 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_568 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_569 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_570 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_571 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_572 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_573 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_574 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_575 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_576 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_577 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_578 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_579 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_580 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_581 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_582 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_583 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_584 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_585 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_586 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_587 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_588 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_589 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_590 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_591 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_592 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_593 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_594 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_595 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_596 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_597 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_598 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_599 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_600 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_601 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_602 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_603 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_604 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_605 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_606 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_607 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_608 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_609 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_610 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_611 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_612 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_613 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_614 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_615 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_616 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_617 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_618 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_619 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_620 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_621 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_622 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_623 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_624 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_625 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_626 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_627 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_628 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_629 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_630 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_631 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_632 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_633 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_634 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_635 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_636 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_637 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_638 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_639 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_640 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_641 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_642 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_643 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_644 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_645 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_646 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_647 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_648 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_649 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_650 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_651 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_652 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_653 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_654 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_655 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_656 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_657 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_658 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_659 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_660 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_661 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_662 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_663 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_664 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_665 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_666 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_667 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_668 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_669 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_670 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_671 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_672 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_673 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_674 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_675 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_676 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_677 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_678 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_679 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_680 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_681 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_682 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_683 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_684 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_685 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_686 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_687 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_688 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_689 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_690 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_691 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_692 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_693 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_694 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_695 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_696 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_697 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_698 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_699 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_700 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_701 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_702 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_703 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_704 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_705 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_706 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_707 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_708 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_709 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_710 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_711 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_712 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_713 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_714 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_715 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_716 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_717 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_718 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_719 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_720 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_721 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_722 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_723 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_724 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_725 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_726 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_727 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_728 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_729 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_730 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_731 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_732 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_733 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_734 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_735 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_736 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_737 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_738 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_739 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_740 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_741 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_742 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_743 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_744 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_745 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_746 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_747 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_748 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_749 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_750 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_751 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_752 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_753 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_754 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_755 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_756 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_757 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_758 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_759 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_760 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_761 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_762 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_763 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_764 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_765 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_766 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_767 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_768 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_769 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_770 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_771 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_772 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_773 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_774 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_775 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_776 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_777 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_778 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_779 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_780 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_781 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_782 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_783 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_784 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_785 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_786 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_787 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_788 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_789 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_790 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_791 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_792 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_793 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_794 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_795 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_796 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_797 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_798 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_799 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_800 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_801 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_802 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_803 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_804 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_805 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_806 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_807 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_808 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_809 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_810 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_811 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_812 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_813 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_814 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_815 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_816 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_817 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_818 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_819 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_820 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_821 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_822 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_823 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_824 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_825 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_826 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_827 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_828 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_829 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_830 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_831 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_832 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_833 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_834 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_835 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_836 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_837 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_838 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_839 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_840 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_841 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_842 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_843 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_844 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_845 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_846 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_847 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_848 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_849 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_850 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_851 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_852 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_853 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_854 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_855 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_856 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_857 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_858 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_859 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_860 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_861 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_862 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_863 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_864 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_865 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_866 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_867 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_868 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_869 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_870 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_871 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_872 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_873 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_874 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_875 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_876 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_877 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_878 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_879 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_880 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_881 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_882 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_883 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_884 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_885 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_886 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_887 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_888 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_889 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_890 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_891 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_892 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_893 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_894 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_895 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_896 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_897 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_898 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_899 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_900 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_901 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_902 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_903 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_904 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_905 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_906 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_907 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_908 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_909 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_910 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_911 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_912 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_913 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_914 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_915 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_916 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_917 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_918 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_919 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_920 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_921 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_922 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_923 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_924 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_925 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_926 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_927 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_928 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_929 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_930 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_931 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_932 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_933 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_934 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_935 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_936 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_937 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_938 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_939 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_940 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_941 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_942 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_943 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_944 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_945 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_946 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_947 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_948 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_949 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_950 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_951 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_952 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_953 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_954 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_955 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_956 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_957 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_958 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_959 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_960 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_961 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_962 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_963 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_964 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_965 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_966 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_967 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_968 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_969 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_970 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_971 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_972 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_973 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_974 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_975 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_976 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_977 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_978 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_979 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_980 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_981 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_982 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_983 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_984 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_985 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_986 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_987 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_988 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_989 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_990 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_991 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_992 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_993 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_994 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_995 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_996 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_997 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_998 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_999 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_1000 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_1001 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_1002 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_1003 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_1004 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_1005 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_1006 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_1007 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_1008 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_1009 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_1010 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_1011 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_1012 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_1013 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_1014 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_1015 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_1016 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_1017 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_1018 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_1019 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_1020 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_1021 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_1022 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_1023 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_1024 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_1025 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_1026 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_1027 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_1028 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_1029 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_1030 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_1031 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_1032 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_1033 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_1034 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_1035 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_1036 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_1037 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_1038 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_1039 <= 1'h0; // @[FIFOFixer.scala:79:27]
end
else begin // @[FIFOFixer.scala:50:9]
a_first_counter <= (~a_first_done | a_first_counter - 1'h1) & a_first_counter; // @[Decoupled.scala:51:35]
d_first_counter <= (~(auto_anon_in_d_ready & auto_anon_out_d_valid) | d_first_counter - 1'h1) & d_first_counter; // @[Decoupled.scala:51:35]
flight_0 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h0) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h0 | flight_0); // @[Decoupled.scala:51:35]
flight_1 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1 | flight_1); // @[Decoupled.scala:51:35]
flight_2 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2 | flight_2); // @[Decoupled.scala:51:35]
flight_3 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3 | flight_3); // @[Decoupled.scala:51:35]
flight_4 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h4) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h4 | flight_4); // @[Decoupled.scala:51:35]
flight_5 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h5) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h5 | flight_5); // @[Decoupled.scala:51:35]
flight_6 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h6) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h6 | flight_6); // @[Decoupled.scala:51:35]
flight_7 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h7) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h7 | flight_7); // @[Decoupled.scala:51:35]
flight_8 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h8) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h8 | flight_8); // @[Decoupled.scala:51:35]
flight_9 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h9) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h9 | flight_9); // @[Decoupled.scala:51:35]
flight_10 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hA) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hA | flight_10); // @[Decoupled.scala:51:35]
flight_11 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hB) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hB | flight_11); // @[Decoupled.scala:51:35]
flight_12 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hC) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hC | flight_12); // @[Decoupled.scala:51:35]
flight_13 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hD) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hD | flight_13); // @[Decoupled.scala:51:35]
flight_14 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hE) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hE | flight_14); // @[Decoupled.scala:51:35]
flight_15 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hF) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hF | flight_15); // @[Decoupled.scala:51:35]
flight_16 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h10) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h10 | flight_16); // @[Decoupled.scala:51:35]
flight_17 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h11) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h11 | flight_17); // @[Decoupled.scala:51:35]
flight_18 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h12) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h12 | flight_18); // @[Decoupled.scala:51:35]
flight_19 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h13) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h13 | flight_19); // @[Decoupled.scala:51:35]
flight_20 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h14) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h14 | flight_20); // @[Decoupled.scala:51:35]
flight_21 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h15) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h15 | flight_21); // @[Decoupled.scala:51:35]
flight_22 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h16) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h16 | flight_22); // @[Decoupled.scala:51:35]
flight_23 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h17) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h17 | flight_23); // @[Decoupled.scala:51:35]
flight_24 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h18) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h18 | flight_24); // @[Decoupled.scala:51:35]
flight_25 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h19) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h19 | flight_25); // @[Decoupled.scala:51:35]
flight_26 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1A) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1A | flight_26); // @[Decoupled.scala:51:35]
flight_27 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1B) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1B | flight_27); // @[Decoupled.scala:51:35]
flight_28 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1C) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1C | flight_28); // @[Decoupled.scala:51:35]
flight_29 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1D) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1D | flight_29); // @[Decoupled.scala:51:35]
flight_30 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1E) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1E | flight_30); // @[Decoupled.scala:51:35]
flight_31 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1F) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1F | flight_31); // @[Decoupled.scala:51:35]
flight_32 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h20) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h20 | flight_32); // @[Decoupled.scala:51:35]
flight_33 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h21) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h21 | flight_33); // @[Decoupled.scala:51:35]
flight_34 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h22) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h22 | flight_34); // @[Decoupled.scala:51:35]
flight_35 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h23) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h23 | flight_35); // @[Decoupled.scala:51:35]
flight_36 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h24) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h24 | flight_36); // @[Decoupled.scala:51:35]
flight_37 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h25) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h25 | flight_37); // @[Decoupled.scala:51:35]
flight_38 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h26) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h26 | flight_38); // @[Decoupled.scala:51:35]
flight_39 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h27) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h27 | flight_39); // @[Decoupled.scala:51:35]
flight_40 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h28) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h28 | flight_40); // @[Decoupled.scala:51:35]
flight_41 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h29) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h29 | flight_41); // @[Decoupled.scala:51:35]
flight_42 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2A) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2A | flight_42); // @[Decoupled.scala:51:35]
flight_43 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2B) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2B | flight_43); // @[Decoupled.scala:51:35]
flight_44 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2C) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2C | flight_44); // @[Decoupled.scala:51:35]
flight_45 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2D) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2D | flight_45); // @[Decoupled.scala:51:35]
flight_46 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2E) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2E | flight_46); // @[Decoupled.scala:51:35]
flight_47 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2F) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2F | flight_47); // @[Decoupled.scala:51:35]
flight_48 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h30) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h30 | flight_48); // @[Decoupled.scala:51:35]
flight_49 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h31) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h31 | flight_49); // @[Decoupled.scala:51:35]
flight_50 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h32) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h32 | flight_50); // @[Decoupled.scala:51:35]
flight_51 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h33) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h33 | flight_51); // @[Decoupled.scala:51:35]
flight_52 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h34) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h34 | flight_52); // @[Decoupled.scala:51:35]
flight_53 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h35) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h35 | flight_53); // @[Decoupled.scala:51:35]
flight_54 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h36) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h36 | flight_54); // @[Decoupled.scala:51:35]
flight_55 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h37) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h37 | flight_55); // @[Decoupled.scala:51:35]
flight_56 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h38) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h38 | flight_56); // @[Decoupled.scala:51:35]
flight_57 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h39) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h39 | flight_57); // @[Decoupled.scala:51:35]
flight_58 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3A) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3A | flight_58); // @[Decoupled.scala:51:35]
flight_59 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3B) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3B | flight_59); // @[Decoupled.scala:51:35]
flight_60 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3C) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3C | flight_60); // @[Decoupled.scala:51:35]
flight_61 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3D) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3D | flight_61); // @[Decoupled.scala:51:35]
flight_62 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3E) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3E | flight_62); // @[Decoupled.scala:51:35]
flight_63 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3F) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3F | flight_63); // @[Decoupled.scala:51:35]
flight_64 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h40) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h40 | flight_64); // @[Decoupled.scala:51:35]
flight_65 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h41) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h41 | flight_65); // @[Decoupled.scala:51:35]
flight_66 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h42) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h42 | flight_66); // @[Decoupled.scala:51:35]
flight_67 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h43) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h43 | flight_67); // @[Decoupled.scala:51:35]
flight_68 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h44) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h44 | flight_68); // @[Decoupled.scala:51:35]
flight_69 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h45) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h45 | flight_69); // @[Decoupled.scala:51:35]
flight_70 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h46) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h46 | flight_70); // @[Decoupled.scala:51:35]
flight_71 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h47) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h47 | flight_71); // @[Decoupled.scala:51:35]
flight_72 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h48) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h48 | flight_72); // @[Decoupled.scala:51:35]
flight_73 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h49) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h49 | flight_73); // @[Decoupled.scala:51:35]
flight_74 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h4A) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h4A | flight_74); // @[Decoupled.scala:51:35]
flight_75 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h4B) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h4B | flight_75); // @[Decoupled.scala:51:35]
flight_76 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h4C) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h4C | flight_76); // @[Decoupled.scala:51:35]
flight_77 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h4D) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h4D | flight_77); // @[Decoupled.scala:51:35]
flight_78 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h4E) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h4E | flight_78); // @[Decoupled.scala:51:35]
flight_79 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h4F) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h4F | flight_79); // @[Decoupled.scala:51:35]
flight_80 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h50) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h50 | flight_80); // @[Decoupled.scala:51:35]
flight_81 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h51) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h51 | flight_81); // @[Decoupled.scala:51:35]
flight_82 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h52) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h52 | flight_82); // @[Decoupled.scala:51:35]
flight_83 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h53) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h53 | flight_83); // @[Decoupled.scala:51:35]
flight_84 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h54) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h54 | flight_84); // @[Decoupled.scala:51:35]
flight_85 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h55) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h55 | flight_85); // @[Decoupled.scala:51:35]
flight_86 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h56) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h56 | flight_86); // @[Decoupled.scala:51:35]
flight_87 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h57) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h57 | flight_87); // @[Decoupled.scala:51:35]
flight_88 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h58) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h58 | flight_88); // @[Decoupled.scala:51:35]
flight_89 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h59) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h59 | flight_89); // @[Decoupled.scala:51:35]
flight_90 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h5A) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h5A | flight_90); // @[Decoupled.scala:51:35]
flight_91 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h5B) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h5B | flight_91); // @[Decoupled.scala:51:35]
flight_92 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h5C) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h5C | flight_92); // @[Decoupled.scala:51:35]
flight_93 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h5D) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h5D | flight_93); // @[Decoupled.scala:51:35]
flight_94 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h5E) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h5E | flight_94); // @[Decoupled.scala:51:35]
flight_95 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h5F) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h5F | flight_95); // @[Decoupled.scala:51:35]
flight_96 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h60) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h60 | flight_96); // @[Decoupled.scala:51:35]
flight_97 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h61) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h61 | flight_97); // @[Decoupled.scala:51:35]
flight_98 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h62) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h62 | flight_98); // @[Decoupled.scala:51:35]
flight_99 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h63) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h63 | flight_99); // @[Decoupled.scala:51:35]
flight_100 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h64) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h64 | flight_100); // @[Decoupled.scala:51:35]
flight_101 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h65) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h65 | flight_101); // @[Decoupled.scala:51:35]
flight_102 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h66) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h66 | flight_102); // @[Decoupled.scala:51:35]
flight_103 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h67) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h67 | flight_103); // @[Decoupled.scala:51:35]
flight_104 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h68) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h68 | flight_104); // @[Decoupled.scala:51:35]
flight_105 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h69) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h69 | flight_105); // @[Decoupled.scala:51:35]
flight_106 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h6A) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h6A | flight_106); // @[Decoupled.scala:51:35]
flight_107 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h6B) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h6B | flight_107); // @[Decoupled.scala:51:35]
flight_108 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h6C) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h6C | flight_108); // @[Decoupled.scala:51:35]
flight_109 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h6D) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h6D | flight_109); // @[Decoupled.scala:51:35]
flight_110 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h6E) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h6E | flight_110); // @[Decoupled.scala:51:35]
flight_111 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h6F) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h6F | flight_111); // @[Decoupled.scala:51:35]
flight_112 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h70) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h70 | flight_112); // @[Decoupled.scala:51:35]
flight_113 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h71) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h71 | flight_113); // @[Decoupled.scala:51:35]
flight_114 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h72) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h72 | flight_114); // @[Decoupled.scala:51:35]
flight_115 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h73) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h73 | flight_115); // @[Decoupled.scala:51:35]
flight_116 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h74) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h74 | flight_116); // @[Decoupled.scala:51:35]
flight_117 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h75) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h75 | flight_117); // @[Decoupled.scala:51:35]
flight_118 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h76) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h76 | flight_118); // @[Decoupled.scala:51:35]
flight_119 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h77) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h77 | flight_119); // @[Decoupled.scala:51:35]
flight_120 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h78) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h78 | flight_120); // @[Decoupled.scala:51:35]
flight_121 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h79) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h79 | flight_121); // @[Decoupled.scala:51:35]
flight_122 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h7A) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h7A | flight_122); // @[Decoupled.scala:51:35]
flight_123 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h7B) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h7B | flight_123); // @[Decoupled.scala:51:35]
flight_124 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h7C) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h7C | flight_124); // @[Decoupled.scala:51:35]
flight_125 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h7D) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h7D | flight_125); // @[Decoupled.scala:51:35]
flight_126 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h7E) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h7E | flight_126); // @[Decoupled.scala:51:35]
flight_127 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h7F) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h7F | flight_127); // @[Decoupled.scala:51:35]
flight_128 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h80) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h80 | flight_128); // @[Decoupled.scala:51:35]
flight_129 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h81) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h81 | flight_129); // @[Decoupled.scala:51:35]
flight_130 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h82) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h82 | flight_130); // @[Decoupled.scala:51:35]
flight_131 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h83) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h83 | flight_131); // @[Decoupled.scala:51:35]
flight_132 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h84) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h84 | flight_132); // @[Decoupled.scala:51:35]
flight_133 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h85) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h85 | flight_133); // @[Decoupled.scala:51:35]
flight_134 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h86) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h86 | flight_134); // @[Decoupled.scala:51:35]
flight_135 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h87) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h87 | flight_135); // @[Decoupled.scala:51:35]
flight_136 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h88) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h88 | flight_136); // @[Decoupled.scala:51:35]
flight_137 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h89) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h89 | flight_137); // @[Decoupled.scala:51:35]
flight_138 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h8A) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h8A | flight_138); // @[Decoupled.scala:51:35]
flight_139 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h8B) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h8B | flight_139); // @[Decoupled.scala:51:35]
flight_140 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h8C) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h8C | flight_140); // @[Decoupled.scala:51:35]
flight_141 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h8D) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h8D | flight_141); // @[Decoupled.scala:51:35]
flight_142 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h8E) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h8E | flight_142); // @[Decoupled.scala:51:35]
flight_143 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h8F) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h8F | flight_143); // @[Decoupled.scala:51:35]
flight_144 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h90) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h90 | flight_144); // @[Decoupled.scala:51:35]
flight_145 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h91) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h91 | flight_145); // @[Decoupled.scala:51:35]
flight_146 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h92) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h92 | flight_146); // @[Decoupled.scala:51:35]
flight_147 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h93) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h93 | flight_147); // @[Decoupled.scala:51:35]
flight_148 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h94) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h94 | flight_148); // @[Decoupled.scala:51:35]
flight_149 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h95) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h95 | flight_149); // @[Decoupled.scala:51:35]
flight_150 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h96) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h96 | flight_150); // @[Decoupled.scala:51:35]
flight_151 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h97) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h97 | flight_151); // @[Decoupled.scala:51:35]
flight_152 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h98) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h98 | flight_152); // @[Decoupled.scala:51:35]
flight_153 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h99) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h99 | flight_153); // @[Decoupled.scala:51:35]
flight_154 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h9A) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h9A | flight_154); // @[Decoupled.scala:51:35]
flight_155 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h9B) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h9B | flight_155); // @[Decoupled.scala:51:35]
flight_156 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h9C) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h9C | flight_156); // @[Decoupled.scala:51:35]
flight_157 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h9D) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h9D | flight_157); // @[Decoupled.scala:51:35]
flight_158 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h9E) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h9E | flight_158); // @[Decoupled.scala:51:35]
flight_159 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h9F) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h9F | flight_159); // @[Decoupled.scala:51:35]
flight_160 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hA0) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hA0 | flight_160); // @[Decoupled.scala:51:35]
flight_161 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hA1) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hA1 | flight_161); // @[Decoupled.scala:51:35]
flight_162 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hA2) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hA2 | flight_162); // @[Decoupled.scala:51:35]
flight_163 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hA3) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hA3 | flight_163); // @[Decoupled.scala:51:35]
flight_164 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hA4) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hA4 | flight_164); // @[Decoupled.scala:51:35]
flight_165 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hA5) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hA5 | flight_165); // @[Decoupled.scala:51:35]
flight_166 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hA6) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hA6 | flight_166); // @[Decoupled.scala:51:35]
flight_167 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hA7) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hA7 | flight_167); // @[Decoupled.scala:51:35]
flight_168 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hA8) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hA8 | flight_168); // @[Decoupled.scala:51:35]
flight_169 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hA9) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hA9 | flight_169); // @[Decoupled.scala:51:35]
flight_170 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hAA) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hAA | flight_170); // @[Decoupled.scala:51:35]
flight_171 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hAB) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hAB | flight_171); // @[Decoupled.scala:51:35]
flight_172 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hAC) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hAC | flight_172); // @[Decoupled.scala:51:35]
flight_173 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hAD) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hAD | flight_173); // @[Decoupled.scala:51:35]
flight_174 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hAE) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hAE | flight_174); // @[Decoupled.scala:51:35]
flight_175 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hAF) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hAF | flight_175); // @[Decoupled.scala:51:35]
flight_176 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hB0) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hB0 | flight_176); // @[Decoupled.scala:51:35]
flight_177 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hB1) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hB1 | flight_177); // @[Decoupled.scala:51:35]
flight_178 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hB2) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hB2 | flight_178); // @[Decoupled.scala:51:35]
flight_179 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hB3) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hB3 | flight_179); // @[Decoupled.scala:51:35]
flight_180 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hB4) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hB4 | flight_180); // @[Decoupled.scala:51:35]
flight_181 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hB5) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hB5 | flight_181); // @[Decoupled.scala:51:35]
flight_182 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hB6) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hB6 | flight_182); // @[Decoupled.scala:51:35]
flight_183 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hB7) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hB7 | flight_183); // @[Decoupled.scala:51:35]
flight_184 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hB8) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hB8 | flight_184); // @[Decoupled.scala:51:35]
flight_185 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hB9) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hB9 | flight_185); // @[Decoupled.scala:51:35]
flight_186 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hBA) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hBA | flight_186); // @[Decoupled.scala:51:35]
flight_187 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hBB) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hBB | flight_187); // @[Decoupled.scala:51:35]
flight_188 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hBC) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hBC | flight_188); // @[Decoupled.scala:51:35]
flight_189 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hBD) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hBD | flight_189); // @[Decoupled.scala:51:35]
flight_190 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hBE) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hBE | flight_190); // @[Decoupled.scala:51:35]
flight_191 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hBF) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hBF | flight_191); // @[Decoupled.scala:51:35]
flight_192 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hC0) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hC0 | flight_192); // @[Decoupled.scala:51:35]
flight_193 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hC1) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hC1 | flight_193); // @[Decoupled.scala:51:35]
flight_194 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hC2) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hC2 | flight_194); // @[Decoupled.scala:51:35]
flight_195 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hC3) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hC3 | flight_195); // @[Decoupled.scala:51:35]
flight_196 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hC4) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hC4 | flight_196); // @[Decoupled.scala:51:35]
flight_197 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hC5) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hC5 | flight_197); // @[Decoupled.scala:51:35]
flight_198 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hC6) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hC6 | flight_198); // @[Decoupled.scala:51:35]
flight_199 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hC7) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hC7 | flight_199); // @[Decoupled.scala:51:35]
flight_200 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hC8) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hC8 | flight_200); // @[Decoupled.scala:51:35]
flight_201 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hC9) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hC9 | flight_201); // @[Decoupled.scala:51:35]
flight_202 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hCA) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hCA | flight_202); // @[Decoupled.scala:51:35]
flight_203 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hCB) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hCB | flight_203); // @[Decoupled.scala:51:35]
flight_204 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hCC) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hCC | flight_204); // @[Decoupled.scala:51:35]
flight_205 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hCD) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hCD | flight_205); // @[Decoupled.scala:51:35]
flight_206 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hCE) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hCE | flight_206); // @[Decoupled.scala:51:35]
flight_207 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hCF) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hCF | flight_207); // @[Decoupled.scala:51:35]
flight_208 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hD0) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hD0 | flight_208); // @[Decoupled.scala:51:35]
flight_209 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hD1) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hD1 | flight_209); // @[Decoupled.scala:51:35]
flight_210 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hD2) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hD2 | flight_210); // @[Decoupled.scala:51:35]
flight_211 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hD3) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hD3 | flight_211); // @[Decoupled.scala:51:35]
flight_212 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hD4) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hD4 | flight_212); // @[Decoupled.scala:51:35]
flight_213 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hD5) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hD5 | flight_213); // @[Decoupled.scala:51:35]
flight_214 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hD6) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hD6 | flight_214); // @[Decoupled.scala:51:35]
flight_215 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hD7) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hD7 | flight_215); // @[Decoupled.scala:51:35]
flight_216 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hD8) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hD8 | flight_216); // @[Decoupled.scala:51:35]
flight_217 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hD9) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hD9 | flight_217); // @[Decoupled.scala:51:35]
flight_218 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hDA) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hDA | flight_218); // @[Decoupled.scala:51:35]
flight_219 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hDB) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hDB | flight_219); // @[Decoupled.scala:51:35]
flight_220 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hDC) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hDC | flight_220); // @[Decoupled.scala:51:35]
flight_221 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hDD) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hDD | flight_221); // @[Decoupled.scala:51:35]
flight_222 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hDE) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hDE | flight_222); // @[Decoupled.scala:51:35]
flight_223 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hDF) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hDF | flight_223); // @[Decoupled.scala:51:35]
flight_224 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hE0) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hE0 | flight_224); // @[Decoupled.scala:51:35]
flight_225 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hE1) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hE1 | flight_225); // @[Decoupled.scala:51:35]
flight_226 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hE2) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hE2 | flight_226); // @[Decoupled.scala:51:35]
flight_227 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hE3) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hE3 | flight_227); // @[Decoupled.scala:51:35]
flight_228 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hE4) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hE4 | flight_228); // @[Decoupled.scala:51:35]
flight_229 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hE5) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hE5 | flight_229); // @[Decoupled.scala:51:35]
flight_230 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hE6) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hE6 | flight_230); // @[Decoupled.scala:51:35]
flight_231 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hE7) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hE7 | flight_231); // @[Decoupled.scala:51:35]
flight_232 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hE8) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hE8 | flight_232); // @[Decoupled.scala:51:35]
flight_233 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hE9) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hE9 | flight_233); // @[Decoupled.scala:51:35]
flight_234 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hEA) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hEA | flight_234); // @[Decoupled.scala:51:35]
flight_235 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hEB) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hEB | flight_235); // @[Decoupled.scala:51:35]
flight_236 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hEC) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hEC | flight_236); // @[Decoupled.scala:51:35]
flight_237 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hED) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hED | flight_237); // @[Decoupled.scala:51:35]
flight_238 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hEE) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hEE | flight_238); // @[Decoupled.scala:51:35]
flight_239 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hEF) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hEF | flight_239); // @[Decoupled.scala:51:35]
flight_240 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hF0) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hF0 | flight_240); // @[Decoupled.scala:51:35]
flight_241 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hF1) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hF1 | flight_241); // @[Decoupled.scala:51:35]
flight_242 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hF2) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hF2 | flight_242); // @[Decoupled.scala:51:35]
flight_243 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hF3) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hF3 | flight_243); // @[Decoupled.scala:51:35]
flight_244 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hF4) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hF4 | flight_244); // @[Decoupled.scala:51:35]
flight_245 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hF5) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hF5 | flight_245); // @[Decoupled.scala:51:35]
flight_246 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hF6) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hF6 | flight_246); // @[Decoupled.scala:51:35]
flight_247 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hF7) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hF7 | flight_247); // @[Decoupled.scala:51:35]
flight_248 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hF8) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hF8 | flight_248); // @[Decoupled.scala:51:35]
flight_249 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hF9) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hF9 | flight_249); // @[Decoupled.scala:51:35]
flight_250 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hFA) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hFA | flight_250); // @[Decoupled.scala:51:35]
flight_251 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hFB) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hFB | flight_251); // @[Decoupled.scala:51:35]
flight_252 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hFC) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hFC | flight_252); // @[Decoupled.scala:51:35]
flight_253 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hFD) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hFD | flight_253); // @[Decoupled.scala:51:35]
flight_254 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hFE) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hFE | flight_254); // @[Decoupled.scala:51:35]
flight_255 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'hFF) & (_GEN_4 & auto_anon_in_a_bits_source == 11'hFF | flight_255); // @[Decoupled.scala:51:35]
flight_256 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h100) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h100 | flight_256); // @[Decoupled.scala:51:35]
flight_257 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h101) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h101 | flight_257); // @[Decoupled.scala:51:35]
flight_258 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h102) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h102 | flight_258); // @[Decoupled.scala:51:35]
flight_259 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h103) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h103 | flight_259); // @[Decoupled.scala:51:35]
flight_260 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h104) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h104 | flight_260); // @[Decoupled.scala:51:35]
flight_261 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h105) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h105 | flight_261); // @[Decoupled.scala:51:35]
flight_262 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h106) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h106 | flight_262); // @[Decoupled.scala:51:35]
flight_263 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h107) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h107 | flight_263); // @[Decoupled.scala:51:35]
flight_264 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h108) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h108 | flight_264); // @[Decoupled.scala:51:35]
flight_265 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h109) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h109 | flight_265); // @[Decoupled.scala:51:35]
flight_266 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h10A) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h10A | flight_266); // @[Decoupled.scala:51:35]
flight_267 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h10B) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h10B | flight_267); // @[Decoupled.scala:51:35]
flight_268 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h10C) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h10C | flight_268); // @[Decoupled.scala:51:35]
flight_269 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h10D) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h10D | flight_269); // @[Decoupled.scala:51:35]
flight_270 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h10E) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h10E | flight_270); // @[Decoupled.scala:51:35]
flight_271 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h10F) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h10F | flight_271); // @[Decoupled.scala:51:35]
flight_272 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h110) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h110 | flight_272); // @[Decoupled.scala:51:35]
flight_273 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h111) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h111 | flight_273); // @[Decoupled.scala:51:35]
flight_274 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h112) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h112 | flight_274); // @[Decoupled.scala:51:35]
flight_275 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h113) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h113 | flight_275); // @[Decoupled.scala:51:35]
flight_276 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h114) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h114 | flight_276); // @[Decoupled.scala:51:35]
flight_277 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h115) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h115 | flight_277); // @[Decoupled.scala:51:35]
flight_278 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h116) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h116 | flight_278); // @[Decoupled.scala:51:35]
flight_279 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h117) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h117 | flight_279); // @[Decoupled.scala:51:35]
flight_280 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h118) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h118 | flight_280); // @[Decoupled.scala:51:35]
flight_281 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h119) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h119 | flight_281); // @[Decoupled.scala:51:35]
flight_282 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h11A) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h11A | flight_282); // @[Decoupled.scala:51:35]
flight_283 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h11B) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h11B | flight_283); // @[Decoupled.scala:51:35]
flight_284 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h11C) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h11C | flight_284); // @[Decoupled.scala:51:35]
flight_285 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h11D) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h11D | flight_285); // @[Decoupled.scala:51:35]
flight_286 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h11E) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h11E | flight_286); // @[Decoupled.scala:51:35]
flight_287 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h11F) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h11F | flight_287); // @[Decoupled.scala:51:35]
flight_288 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h120) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h120 | flight_288); // @[Decoupled.scala:51:35]
flight_289 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h121) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h121 | flight_289); // @[Decoupled.scala:51:35]
flight_290 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h122) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h122 | flight_290); // @[Decoupled.scala:51:35]
flight_291 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h123) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h123 | flight_291); // @[Decoupled.scala:51:35]
flight_292 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h124) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h124 | flight_292); // @[Decoupled.scala:51:35]
flight_293 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h125) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h125 | flight_293); // @[Decoupled.scala:51:35]
flight_294 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h126) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h126 | flight_294); // @[Decoupled.scala:51:35]
flight_295 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h127) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h127 | flight_295); // @[Decoupled.scala:51:35]
flight_296 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h128) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h128 | flight_296); // @[Decoupled.scala:51:35]
flight_297 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h129) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h129 | flight_297); // @[Decoupled.scala:51:35]
flight_298 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h12A) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h12A | flight_298); // @[Decoupled.scala:51:35]
flight_299 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h12B) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h12B | flight_299); // @[Decoupled.scala:51:35]
flight_300 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h12C) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h12C | flight_300); // @[Decoupled.scala:51:35]
flight_301 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h12D) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h12D | flight_301); // @[Decoupled.scala:51:35]
flight_302 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h12E) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h12E | flight_302); // @[Decoupled.scala:51:35]
flight_303 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h12F) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h12F | flight_303); // @[Decoupled.scala:51:35]
flight_304 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h130) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h130 | flight_304); // @[Decoupled.scala:51:35]
flight_305 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h131) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h131 | flight_305); // @[Decoupled.scala:51:35]
flight_306 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h132) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h132 | flight_306); // @[Decoupled.scala:51:35]
flight_307 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h133) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h133 | flight_307); // @[Decoupled.scala:51:35]
flight_308 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h134) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h134 | flight_308); // @[Decoupled.scala:51:35]
flight_309 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h135) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h135 | flight_309); // @[Decoupled.scala:51:35]
flight_310 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h136) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h136 | flight_310); // @[Decoupled.scala:51:35]
flight_311 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h137) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h137 | flight_311); // @[Decoupled.scala:51:35]
flight_312 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h138) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h138 | flight_312); // @[Decoupled.scala:51:35]
flight_313 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h139) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h139 | flight_313); // @[Decoupled.scala:51:35]
flight_314 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h13A) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h13A | flight_314); // @[Decoupled.scala:51:35]
flight_315 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h13B) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h13B | flight_315); // @[Decoupled.scala:51:35]
flight_316 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h13C) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h13C | flight_316); // @[Decoupled.scala:51:35]
flight_317 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h13D) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h13D | flight_317); // @[Decoupled.scala:51:35]
flight_318 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h13E) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h13E | flight_318); // @[Decoupled.scala:51:35]
flight_319 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h13F) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h13F | flight_319); // @[Decoupled.scala:51:35]
flight_320 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h140) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h140 | flight_320); // @[Decoupled.scala:51:35]
flight_321 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h141) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h141 | flight_321); // @[Decoupled.scala:51:35]
flight_322 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h142) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h142 | flight_322); // @[Decoupled.scala:51:35]
flight_323 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h143) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h143 | flight_323); // @[Decoupled.scala:51:35]
flight_324 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h144) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h144 | flight_324); // @[Decoupled.scala:51:35]
flight_325 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h145) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h145 | flight_325); // @[Decoupled.scala:51:35]
flight_326 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h146) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h146 | flight_326); // @[Decoupled.scala:51:35]
flight_327 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h147) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h147 | flight_327); // @[Decoupled.scala:51:35]
flight_328 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h148) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h148 | flight_328); // @[Decoupled.scala:51:35]
flight_329 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h149) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h149 | flight_329); // @[Decoupled.scala:51:35]
flight_330 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h14A) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h14A | flight_330); // @[Decoupled.scala:51:35]
flight_331 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h14B) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h14B | flight_331); // @[Decoupled.scala:51:35]
flight_332 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h14C) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h14C | flight_332); // @[Decoupled.scala:51:35]
flight_333 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h14D) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h14D | flight_333); // @[Decoupled.scala:51:35]
flight_334 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h14E) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h14E | flight_334); // @[Decoupled.scala:51:35]
flight_335 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h14F) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h14F | flight_335); // @[Decoupled.scala:51:35]
flight_336 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h150) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h150 | flight_336); // @[Decoupled.scala:51:35]
flight_337 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h151) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h151 | flight_337); // @[Decoupled.scala:51:35]
flight_338 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h152) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h152 | flight_338); // @[Decoupled.scala:51:35]
flight_339 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h153) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h153 | flight_339); // @[Decoupled.scala:51:35]
flight_340 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h154) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h154 | flight_340); // @[Decoupled.scala:51:35]
flight_341 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h155) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h155 | flight_341); // @[Decoupled.scala:51:35]
flight_342 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h156) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h156 | flight_342); // @[Decoupled.scala:51:35]
flight_343 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h157) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h157 | flight_343); // @[Decoupled.scala:51:35]
flight_344 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h158) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h158 | flight_344); // @[Decoupled.scala:51:35]
flight_345 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h159) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h159 | flight_345); // @[Decoupled.scala:51:35]
flight_346 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h15A) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h15A | flight_346); // @[Decoupled.scala:51:35]
flight_347 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h15B) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h15B | flight_347); // @[Decoupled.scala:51:35]
flight_348 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h15C) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h15C | flight_348); // @[Decoupled.scala:51:35]
flight_349 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h15D) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h15D | flight_349); // @[Decoupled.scala:51:35]
flight_350 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h15E) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h15E | flight_350); // @[Decoupled.scala:51:35]
flight_351 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h15F) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h15F | flight_351); // @[Decoupled.scala:51:35]
flight_352 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h160) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h160 | flight_352); // @[Decoupled.scala:51:35]
flight_353 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h161) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h161 | flight_353); // @[Decoupled.scala:51:35]
flight_354 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h162) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h162 | flight_354); // @[Decoupled.scala:51:35]
flight_355 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h163) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h163 | flight_355); // @[Decoupled.scala:51:35]
flight_356 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h164) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h164 | flight_356); // @[Decoupled.scala:51:35]
flight_357 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h165) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h165 | flight_357); // @[Decoupled.scala:51:35]
flight_358 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h166) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h166 | flight_358); // @[Decoupled.scala:51:35]
flight_359 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h167) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h167 | flight_359); // @[Decoupled.scala:51:35]
flight_360 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h168) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h168 | flight_360); // @[Decoupled.scala:51:35]
flight_361 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h169) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h169 | flight_361); // @[Decoupled.scala:51:35]
flight_362 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h16A) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h16A | flight_362); // @[Decoupled.scala:51:35]
flight_363 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h16B) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h16B | flight_363); // @[Decoupled.scala:51:35]
flight_364 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h16C) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h16C | flight_364); // @[Decoupled.scala:51:35]
flight_365 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h16D) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h16D | flight_365); // @[Decoupled.scala:51:35]
flight_366 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h16E) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h16E | flight_366); // @[Decoupled.scala:51:35]
flight_367 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h16F) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h16F | flight_367); // @[Decoupled.scala:51:35]
flight_368 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h170) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h170 | flight_368); // @[Decoupled.scala:51:35]
flight_369 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h171) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h171 | flight_369); // @[Decoupled.scala:51:35]
flight_370 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h172) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h172 | flight_370); // @[Decoupled.scala:51:35]
flight_371 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h173) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h173 | flight_371); // @[Decoupled.scala:51:35]
flight_372 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h174) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h174 | flight_372); // @[Decoupled.scala:51:35]
flight_373 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h175) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h175 | flight_373); // @[Decoupled.scala:51:35]
flight_374 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h176) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h176 | flight_374); // @[Decoupled.scala:51:35]
flight_375 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h177) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h177 | flight_375); // @[Decoupled.scala:51:35]
flight_376 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h178) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h178 | flight_376); // @[Decoupled.scala:51:35]
flight_377 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h179) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h179 | flight_377); // @[Decoupled.scala:51:35]
flight_378 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h17A) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h17A | flight_378); // @[Decoupled.scala:51:35]
flight_379 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h17B) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h17B | flight_379); // @[Decoupled.scala:51:35]
flight_380 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h17C) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h17C | flight_380); // @[Decoupled.scala:51:35]
flight_381 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h17D) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h17D | flight_381); // @[Decoupled.scala:51:35]
flight_382 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h17E) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h17E | flight_382); // @[Decoupled.scala:51:35]
flight_383 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h17F) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h17F | flight_383); // @[Decoupled.scala:51:35]
flight_384 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h180) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h180 | flight_384); // @[Decoupled.scala:51:35]
flight_385 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h181) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h181 | flight_385); // @[Decoupled.scala:51:35]
flight_386 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h182) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h182 | flight_386); // @[Decoupled.scala:51:35]
flight_387 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h183) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h183 | flight_387); // @[Decoupled.scala:51:35]
flight_388 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h184) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h184 | flight_388); // @[Decoupled.scala:51:35]
flight_389 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h185) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h185 | flight_389); // @[Decoupled.scala:51:35]
flight_390 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h186) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h186 | flight_390); // @[Decoupled.scala:51:35]
flight_391 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h187) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h187 | flight_391); // @[Decoupled.scala:51:35]
flight_392 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h188) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h188 | flight_392); // @[Decoupled.scala:51:35]
flight_393 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h189) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h189 | flight_393); // @[Decoupled.scala:51:35]
flight_394 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h18A) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h18A | flight_394); // @[Decoupled.scala:51:35]
flight_395 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h18B) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h18B | flight_395); // @[Decoupled.scala:51:35]
flight_396 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h18C) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h18C | flight_396); // @[Decoupled.scala:51:35]
flight_397 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h18D) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h18D | flight_397); // @[Decoupled.scala:51:35]
flight_398 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h18E) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h18E | flight_398); // @[Decoupled.scala:51:35]
flight_399 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h18F) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h18F | flight_399); // @[Decoupled.scala:51:35]
flight_400 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h190) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h190 | flight_400); // @[Decoupled.scala:51:35]
flight_401 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h191) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h191 | flight_401); // @[Decoupled.scala:51:35]
flight_402 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h192) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h192 | flight_402); // @[Decoupled.scala:51:35]
flight_403 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h193) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h193 | flight_403); // @[Decoupled.scala:51:35]
flight_404 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h194) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h194 | flight_404); // @[Decoupled.scala:51:35]
flight_405 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h195) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h195 | flight_405); // @[Decoupled.scala:51:35]
flight_406 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h196) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h196 | flight_406); // @[Decoupled.scala:51:35]
flight_407 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h197) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h197 | flight_407); // @[Decoupled.scala:51:35]
flight_408 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h198) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h198 | flight_408); // @[Decoupled.scala:51:35]
flight_409 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h199) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h199 | flight_409); // @[Decoupled.scala:51:35]
flight_410 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h19A) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h19A | flight_410); // @[Decoupled.scala:51:35]
flight_411 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h19B) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h19B | flight_411); // @[Decoupled.scala:51:35]
flight_412 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h19C) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h19C | flight_412); // @[Decoupled.scala:51:35]
flight_413 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h19D) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h19D | flight_413); // @[Decoupled.scala:51:35]
flight_414 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h19E) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h19E | flight_414); // @[Decoupled.scala:51:35]
flight_415 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h19F) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h19F | flight_415); // @[Decoupled.scala:51:35]
flight_416 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1A0) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1A0 | flight_416); // @[Decoupled.scala:51:35]
flight_417 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1A1) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1A1 | flight_417); // @[Decoupled.scala:51:35]
flight_418 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1A2) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1A2 | flight_418); // @[Decoupled.scala:51:35]
flight_419 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1A3) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1A3 | flight_419); // @[Decoupled.scala:51:35]
flight_420 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1A4) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1A4 | flight_420); // @[Decoupled.scala:51:35]
flight_421 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1A5) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1A5 | flight_421); // @[Decoupled.scala:51:35]
flight_422 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1A6) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1A6 | flight_422); // @[Decoupled.scala:51:35]
flight_423 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1A7) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1A7 | flight_423); // @[Decoupled.scala:51:35]
flight_424 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1A8) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1A8 | flight_424); // @[Decoupled.scala:51:35]
flight_425 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1A9) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1A9 | flight_425); // @[Decoupled.scala:51:35]
flight_426 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1AA) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1AA | flight_426); // @[Decoupled.scala:51:35]
flight_427 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1AB) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1AB | flight_427); // @[Decoupled.scala:51:35]
flight_428 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1AC) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1AC | flight_428); // @[Decoupled.scala:51:35]
flight_429 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1AD) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1AD | flight_429); // @[Decoupled.scala:51:35]
flight_430 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1AE) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1AE | flight_430); // @[Decoupled.scala:51:35]
flight_431 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1AF) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1AF | flight_431); // @[Decoupled.scala:51:35]
flight_432 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1B0) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1B0 | flight_432); // @[Decoupled.scala:51:35]
flight_433 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1B1) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1B1 | flight_433); // @[Decoupled.scala:51:35]
flight_434 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1B2) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1B2 | flight_434); // @[Decoupled.scala:51:35]
flight_435 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1B3) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1B3 | flight_435); // @[Decoupled.scala:51:35]
flight_436 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1B4) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1B4 | flight_436); // @[Decoupled.scala:51:35]
flight_437 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1B5) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1B5 | flight_437); // @[Decoupled.scala:51:35]
flight_438 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1B6) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1B6 | flight_438); // @[Decoupled.scala:51:35]
flight_439 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1B7) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1B7 | flight_439); // @[Decoupled.scala:51:35]
flight_440 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1B8) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1B8 | flight_440); // @[Decoupled.scala:51:35]
flight_441 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1B9) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1B9 | flight_441); // @[Decoupled.scala:51:35]
flight_442 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1BA) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1BA | flight_442); // @[Decoupled.scala:51:35]
flight_443 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1BB) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1BB | flight_443); // @[Decoupled.scala:51:35]
flight_444 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1BC) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1BC | flight_444); // @[Decoupled.scala:51:35]
flight_445 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1BD) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1BD | flight_445); // @[Decoupled.scala:51:35]
flight_446 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1BE) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1BE | flight_446); // @[Decoupled.scala:51:35]
flight_447 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1BF) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1BF | flight_447); // @[Decoupled.scala:51:35]
flight_448 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1C0) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1C0 | flight_448); // @[Decoupled.scala:51:35]
flight_449 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1C1) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1C1 | flight_449); // @[Decoupled.scala:51:35]
flight_450 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1C2) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1C2 | flight_450); // @[Decoupled.scala:51:35]
flight_451 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1C3) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1C3 | flight_451); // @[Decoupled.scala:51:35]
flight_452 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1C4) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1C4 | flight_452); // @[Decoupled.scala:51:35]
flight_453 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1C5) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1C5 | flight_453); // @[Decoupled.scala:51:35]
flight_454 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1C6) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1C6 | flight_454); // @[Decoupled.scala:51:35]
flight_455 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1C7) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1C7 | flight_455); // @[Decoupled.scala:51:35]
flight_456 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1C8) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1C8 | flight_456); // @[Decoupled.scala:51:35]
flight_457 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1C9) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1C9 | flight_457); // @[Decoupled.scala:51:35]
flight_458 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1CA) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1CA | flight_458); // @[Decoupled.scala:51:35]
flight_459 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1CB) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1CB | flight_459); // @[Decoupled.scala:51:35]
flight_460 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1CC) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1CC | flight_460); // @[Decoupled.scala:51:35]
flight_461 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1CD) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1CD | flight_461); // @[Decoupled.scala:51:35]
flight_462 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1CE) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1CE | flight_462); // @[Decoupled.scala:51:35]
flight_463 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1CF) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1CF | flight_463); // @[Decoupled.scala:51:35]
flight_464 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1D0) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1D0 | flight_464); // @[Decoupled.scala:51:35]
flight_465 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1D1) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1D1 | flight_465); // @[Decoupled.scala:51:35]
flight_466 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1D2) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1D2 | flight_466); // @[Decoupled.scala:51:35]
flight_467 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1D3) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1D3 | flight_467); // @[Decoupled.scala:51:35]
flight_468 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1D4) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1D4 | flight_468); // @[Decoupled.scala:51:35]
flight_469 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1D5) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1D5 | flight_469); // @[Decoupled.scala:51:35]
flight_470 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1D6) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1D6 | flight_470); // @[Decoupled.scala:51:35]
flight_471 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1D7) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1D7 | flight_471); // @[Decoupled.scala:51:35]
flight_472 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1D8) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1D8 | flight_472); // @[Decoupled.scala:51:35]
flight_473 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1D9) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1D9 | flight_473); // @[Decoupled.scala:51:35]
flight_474 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1DA) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1DA | flight_474); // @[Decoupled.scala:51:35]
flight_475 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1DB) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1DB | flight_475); // @[Decoupled.scala:51:35]
flight_476 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1DC) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1DC | flight_476); // @[Decoupled.scala:51:35]
flight_477 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1DD) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1DD | flight_477); // @[Decoupled.scala:51:35]
flight_478 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1DE) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1DE | flight_478); // @[Decoupled.scala:51:35]
flight_479 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1DF) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1DF | flight_479); // @[Decoupled.scala:51:35]
flight_480 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1E0) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1E0 | flight_480); // @[Decoupled.scala:51:35]
flight_481 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1E1) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1E1 | flight_481); // @[Decoupled.scala:51:35]
flight_482 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1E2) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1E2 | flight_482); // @[Decoupled.scala:51:35]
flight_483 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1E3) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1E3 | flight_483); // @[Decoupled.scala:51:35]
flight_484 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1E4) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1E4 | flight_484); // @[Decoupled.scala:51:35]
flight_485 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1E5) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1E5 | flight_485); // @[Decoupled.scala:51:35]
flight_486 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1E6) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1E6 | flight_486); // @[Decoupled.scala:51:35]
flight_487 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1E7) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1E7 | flight_487); // @[Decoupled.scala:51:35]
flight_488 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1E8) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1E8 | flight_488); // @[Decoupled.scala:51:35]
flight_489 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1E9) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1E9 | flight_489); // @[Decoupled.scala:51:35]
flight_490 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1EA) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1EA | flight_490); // @[Decoupled.scala:51:35]
flight_491 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1EB) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1EB | flight_491); // @[Decoupled.scala:51:35]
flight_492 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1EC) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1EC | flight_492); // @[Decoupled.scala:51:35]
flight_493 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1ED) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1ED | flight_493); // @[Decoupled.scala:51:35]
flight_494 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1EE) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1EE | flight_494); // @[Decoupled.scala:51:35]
flight_495 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1EF) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1EF | flight_495); // @[Decoupled.scala:51:35]
flight_496 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1F0) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1F0 | flight_496); // @[Decoupled.scala:51:35]
flight_497 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1F1) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1F1 | flight_497); // @[Decoupled.scala:51:35]
flight_498 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1F2) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1F2 | flight_498); // @[Decoupled.scala:51:35]
flight_499 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1F3) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1F3 | flight_499); // @[Decoupled.scala:51:35]
flight_500 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1F4) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1F4 | flight_500); // @[Decoupled.scala:51:35]
flight_501 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1F5) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1F5 | flight_501); // @[Decoupled.scala:51:35]
flight_502 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1F6) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1F6 | flight_502); // @[Decoupled.scala:51:35]
flight_503 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1F7) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1F7 | flight_503); // @[Decoupled.scala:51:35]
flight_504 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1F8) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1F8 | flight_504); // @[Decoupled.scala:51:35]
flight_505 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1F9) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1F9 | flight_505); // @[Decoupled.scala:51:35]
flight_506 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1FA) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1FA | flight_506); // @[Decoupled.scala:51:35]
flight_507 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1FB) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1FB | flight_507); // @[Decoupled.scala:51:35]
flight_508 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1FC) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1FC | flight_508); // @[Decoupled.scala:51:35]
flight_509 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1FD) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1FD | flight_509); // @[Decoupled.scala:51:35]
flight_510 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1FE) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1FE | flight_510); // @[Decoupled.scala:51:35]
flight_511 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h1FF) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h1FF | flight_511); // @[Decoupled.scala:51:35]
flight_512 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h200) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h200 | flight_512); // @[Decoupled.scala:51:35]
flight_513 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h201) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h201 | flight_513); // @[Decoupled.scala:51:35]
flight_514 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h202) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h202 | flight_514); // @[Decoupled.scala:51:35]
flight_515 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h203) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h203 | flight_515); // @[Decoupled.scala:51:35]
flight_516 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h204) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h204 | flight_516); // @[Decoupled.scala:51:35]
flight_517 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h205) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h205 | flight_517); // @[Decoupled.scala:51:35]
flight_518 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h206) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h206 | flight_518); // @[Decoupled.scala:51:35]
flight_519 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h207) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h207 | flight_519); // @[Decoupled.scala:51:35]
flight_520 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h208) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h208 | flight_520); // @[Decoupled.scala:51:35]
flight_521 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h209) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h209 | flight_521); // @[Decoupled.scala:51:35]
flight_522 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h20A) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h20A | flight_522); // @[Decoupled.scala:51:35]
flight_523 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h20B) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h20B | flight_523); // @[Decoupled.scala:51:35]
flight_524 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h20C) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h20C | flight_524); // @[Decoupled.scala:51:35]
flight_525 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h20D) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h20D | flight_525); // @[Decoupled.scala:51:35]
flight_526 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h20E) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h20E | flight_526); // @[Decoupled.scala:51:35]
flight_527 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h20F) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h20F | flight_527); // @[Decoupled.scala:51:35]
flight_528 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h210) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h210 | flight_528); // @[Decoupled.scala:51:35]
flight_529 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h211) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h211 | flight_529); // @[Decoupled.scala:51:35]
flight_530 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h212) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h212 | flight_530); // @[Decoupled.scala:51:35]
flight_531 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h213) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h213 | flight_531); // @[Decoupled.scala:51:35]
flight_532 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h214) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h214 | flight_532); // @[Decoupled.scala:51:35]
flight_533 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h215) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h215 | flight_533); // @[Decoupled.scala:51:35]
flight_534 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h216) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h216 | flight_534); // @[Decoupled.scala:51:35]
flight_535 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h217) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h217 | flight_535); // @[Decoupled.scala:51:35]
flight_536 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h218) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h218 | flight_536); // @[Decoupled.scala:51:35]
flight_537 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h219) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h219 | flight_537); // @[Decoupled.scala:51:35]
flight_538 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h21A) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h21A | flight_538); // @[Decoupled.scala:51:35]
flight_539 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h21B) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h21B | flight_539); // @[Decoupled.scala:51:35]
flight_540 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h21C) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h21C | flight_540); // @[Decoupled.scala:51:35]
flight_541 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h21D) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h21D | flight_541); // @[Decoupled.scala:51:35]
flight_542 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h21E) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h21E | flight_542); // @[Decoupled.scala:51:35]
flight_543 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h21F) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h21F | flight_543); // @[Decoupled.scala:51:35]
flight_544 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h220) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h220 | flight_544); // @[Decoupled.scala:51:35]
flight_545 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h221) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h221 | flight_545); // @[Decoupled.scala:51:35]
flight_546 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h222) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h222 | flight_546); // @[Decoupled.scala:51:35]
flight_547 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h223) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h223 | flight_547); // @[Decoupled.scala:51:35]
flight_548 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h224) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h224 | flight_548); // @[Decoupled.scala:51:35]
flight_549 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h225) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h225 | flight_549); // @[Decoupled.scala:51:35]
flight_550 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h226) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h226 | flight_550); // @[Decoupled.scala:51:35]
flight_551 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h227) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h227 | flight_551); // @[Decoupled.scala:51:35]
flight_552 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h228) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h228 | flight_552); // @[Decoupled.scala:51:35]
flight_553 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h229) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h229 | flight_553); // @[Decoupled.scala:51:35]
flight_554 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h22A) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h22A | flight_554); // @[Decoupled.scala:51:35]
flight_555 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h22B) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h22B | flight_555); // @[Decoupled.scala:51:35]
flight_556 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h22C) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h22C | flight_556); // @[Decoupled.scala:51:35]
flight_557 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h22D) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h22D | flight_557); // @[Decoupled.scala:51:35]
flight_558 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h22E) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h22E | flight_558); // @[Decoupled.scala:51:35]
flight_559 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h22F) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h22F | flight_559); // @[Decoupled.scala:51:35]
flight_560 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h230) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h230 | flight_560); // @[Decoupled.scala:51:35]
flight_561 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h231) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h231 | flight_561); // @[Decoupled.scala:51:35]
flight_562 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h232) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h232 | flight_562); // @[Decoupled.scala:51:35]
flight_563 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h233) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h233 | flight_563); // @[Decoupled.scala:51:35]
flight_564 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h234) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h234 | flight_564); // @[Decoupled.scala:51:35]
flight_565 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h235) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h235 | flight_565); // @[Decoupled.scala:51:35]
flight_566 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h236) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h236 | flight_566); // @[Decoupled.scala:51:35]
flight_567 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h237) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h237 | flight_567); // @[Decoupled.scala:51:35]
flight_568 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h238) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h238 | flight_568); // @[Decoupled.scala:51:35]
flight_569 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h239) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h239 | flight_569); // @[Decoupled.scala:51:35]
flight_570 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h23A) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h23A | flight_570); // @[Decoupled.scala:51:35]
flight_571 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h23B) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h23B | flight_571); // @[Decoupled.scala:51:35]
flight_572 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h23C) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h23C | flight_572); // @[Decoupled.scala:51:35]
flight_573 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h23D) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h23D | flight_573); // @[Decoupled.scala:51:35]
flight_574 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h23E) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h23E | flight_574); // @[Decoupled.scala:51:35]
flight_575 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h23F) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h23F | flight_575); // @[Decoupled.scala:51:35]
flight_576 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h240) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h240 | flight_576); // @[Decoupled.scala:51:35]
flight_577 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h241) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h241 | flight_577); // @[Decoupled.scala:51:35]
flight_578 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h242) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h242 | flight_578); // @[Decoupled.scala:51:35]
flight_579 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h243) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h243 | flight_579); // @[Decoupled.scala:51:35]
flight_580 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h244) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h244 | flight_580); // @[Decoupled.scala:51:35]
flight_581 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h245) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h245 | flight_581); // @[Decoupled.scala:51:35]
flight_582 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h246) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h246 | flight_582); // @[Decoupled.scala:51:35]
flight_583 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h247) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h247 | flight_583); // @[Decoupled.scala:51:35]
flight_584 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h248) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h248 | flight_584); // @[Decoupled.scala:51:35]
flight_585 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h249) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h249 | flight_585); // @[Decoupled.scala:51:35]
flight_586 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h24A) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h24A | flight_586); // @[Decoupled.scala:51:35]
flight_587 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h24B) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h24B | flight_587); // @[Decoupled.scala:51:35]
flight_588 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h24C) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h24C | flight_588); // @[Decoupled.scala:51:35]
flight_589 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h24D) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h24D | flight_589); // @[Decoupled.scala:51:35]
flight_590 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h24E) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h24E | flight_590); // @[Decoupled.scala:51:35]
flight_591 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h24F) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h24F | flight_591); // @[Decoupled.scala:51:35]
flight_592 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h250) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h250 | flight_592); // @[Decoupled.scala:51:35]
flight_593 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h251) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h251 | flight_593); // @[Decoupled.scala:51:35]
flight_594 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h252) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h252 | flight_594); // @[Decoupled.scala:51:35]
flight_595 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h253) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h253 | flight_595); // @[Decoupled.scala:51:35]
flight_596 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h254) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h254 | flight_596); // @[Decoupled.scala:51:35]
flight_597 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h255) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h255 | flight_597); // @[Decoupled.scala:51:35]
flight_598 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h256) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h256 | flight_598); // @[Decoupled.scala:51:35]
flight_599 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h257) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h257 | flight_599); // @[Decoupled.scala:51:35]
flight_600 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h258) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h258 | flight_600); // @[Decoupled.scala:51:35]
flight_601 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h259) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h259 | flight_601); // @[Decoupled.scala:51:35]
flight_602 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h25A) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h25A | flight_602); // @[Decoupled.scala:51:35]
flight_603 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h25B) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h25B | flight_603); // @[Decoupled.scala:51:35]
flight_604 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h25C) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h25C | flight_604); // @[Decoupled.scala:51:35]
flight_605 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h25D) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h25D | flight_605); // @[Decoupled.scala:51:35]
flight_606 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h25E) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h25E | flight_606); // @[Decoupled.scala:51:35]
flight_607 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h25F) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h25F | flight_607); // @[Decoupled.scala:51:35]
flight_608 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h260) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h260 | flight_608); // @[Decoupled.scala:51:35]
flight_609 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h261) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h261 | flight_609); // @[Decoupled.scala:51:35]
flight_610 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h262) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h262 | flight_610); // @[Decoupled.scala:51:35]
flight_611 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h263) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h263 | flight_611); // @[Decoupled.scala:51:35]
flight_612 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h264) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h264 | flight_612); // @[Decoupled.scala:51:35]
flight_613 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h265) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h265 | flight_613); // @[Decoupled.scala:51:35]
flight_614 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h266) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h266 | flight_614); // @[Decoupled.scala:51:35]
flight_615 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h267) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h267 | flight_615); // @[Decoupled.scala:51:35]
flight_616 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h268) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h268 | flight_616); // @[Decoupled.scala:51:35]
flight_617 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h269) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h269 | flight_617); // @[Decoupled.scala:51:35]
flight_618 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h26A) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h26A | flight_618); // @[Decoupled.scala:51:35]
flight_619 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h26B) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h26B | flight_619); // @[Decoupled.scala:51:35]
flight_620 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h26C) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h26C | flight_620); // @[Decoupled.scala:51:35]
flight_621 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h26D) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h26D | flight_621); // @[Decoupled.scala:51:35]
flight_622 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h26E) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h26E | flight_622); // @[Decoupled.scala:51:35]
flight_623 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h26F) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h26F | flight_623); // @[Decoupled.scala:51:35]
flight_624 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h270) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h270 | flight_624); // @[Decoupled.scala:51:35]
flight_625 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h271) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h271 | flight_625); // @[Decoupled.scala:51:35]
flight_626 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h272) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h272 | flight_626); // @[Decoupled.scala:51:35]
flight_627 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h273) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h273 | flight_627); // @[Decoupled.scala:51:35]
flight_628 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h274) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h274 | flight_628); // @[Decoupled.scala:51:35]
flight_629 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h275) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h275 | flight_629); // @[Decoupled.scala:51:35]
flight_630 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h276) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h276 | flight_630); // @[Decoupled.scala:51:35]
flight_631 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h277) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h277 | flight_631); // @[Decoupled.scala:51:35]
flight_632 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h278) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h278 | flight_632); // @[Decoupled.scala:51:35]
flight_633 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h279) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h279 | flight_633); // @[Decoupled.scala:51:35]
flight_634 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h27A) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h27A | flight_634); // @[Decoupled.scala:51:35]
flight_635 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h27B) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h27B | flight_635); // @[Decoupled.scala:51:35]
flight_636 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h27C) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h27C | flight_636); // @[Decoupled.scala:51:35]
flight_637 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h27D) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h27D | flight_637); // @[Decoupled.scala:51:35]
flight_638 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h27E) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h27E | flight_638); // @[Decoupled.scala:51:35]
flight_639 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h27F) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h27F | flight_639); // @[Decoupled.scala:51:35]
flight_640 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h280) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h280 | flight_640); // @[Decoupled.scala:51:35]
flight_641 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h281) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h281 | flight_641); // @[Decoupled.scala:51:35]
flight_642 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h282) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h282 | flight_642); // @[Decoupled.scala:51:35]
flight_643 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h283) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h283 | flight_643); // @[Decoupled.scala:51:35]
flight_644 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h284) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h284 | flight_644); // @[Decoupled.scala:51:35]
flight_645 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h285) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h285 | flight_645); // @[Decoupled.scala:51:35]
flight_646 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h286) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h286 | flight_646); // @[Decoupled.scala:51:35]
flight_647 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h287) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h287 | flight_647); // @[Decoupled.scala:51:35]
flight_648 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h288) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h288 | flight_648); // @[Decoupled.scala:51:35]
flight_649 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h289) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h289 | flight_649); // @[Decoupled.scala:51:35]
flight_650 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h28A) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h28A | flight_650); // @[Decoupled.scala:51:35]
flight_651 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h28B) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h28B | flight_651); // @[Decoupled.scala:51:35]
flight_652 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h28C) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h28C | flight_652); // @[Decoupled.scala:51:35]
flight_653 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h28D) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h28D | flight_653); // @[Decoupled.scala:51:35]
flight_654 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h28E) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h28E | flight_654); // @[Decoupled.scala:51:35]
flight_655 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h28F) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h28F | flight_655); // @[Decoupled.scala:51:35]
flight_656 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h290) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h290 | flight_656); // @[Decoupled.scala:51:35]
flight_657 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h291) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h291 | flight_657); // @[Decoupled.scala:51:35]
flight_658 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h292) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h292 | flight_658); // @[Decoupled.scala:51:35]
flight_659 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h293) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h293 | flight_659); // @[Decoupled.scala:51:35]
flight_660 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h294) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h294 | flight_660); // @[Decoupled.scala:51:35]
flight_661 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h295) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h295 | flight_661); // @[Decoupled.scala:51:35]
flight_662 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h296) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h296 | flight_662); // @[Decoupled.scala:51:35]
flight_663 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h297) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h297 | flight_663); // @[Decoupled.scala:51:35]
flight_664 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h298) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h298 | flight_664); // @[Decoupled.scala:51:35]
flight_665 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h299) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h299 | flight_665); // @[Decoupled.scala:51:35]
flight_666 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h29A) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h29A | flight_666); // @[Decoupled.scala:51:35]
flight_667 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h29B) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h29B | flight_667); // @[Decoupled.scala:51:35]
flight_668 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h29C) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h29C | flight_668); // @[Decoupled.scala:51:35]
flight_669 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h29D) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h29D | flight_669); // @[Decoupled.scala:51:35]
flight_670 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h29E) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h29E | flight_670); // @[Decoupled.scala:51:35]
flight_671 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h29F) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h29F | flight_671); // @[Decoupled.scala:51:35]
flight_672 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2A0) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2A0 | flight_672); // @[Decoupled.scala:51:35]
flight_673 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2A1) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2A1 | flight_673); // @[Decoupled.scala:51:35]
flight_674 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2A2) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2A2 | flight_674); // @[Decoupled.scala:51:35]
flight_675 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2A3) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2A3 | flight_675); // @[Decoupled.scala:51:35]
flight_676 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2A4) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2A4 | flight_676); // @[Decoupled.scala:51:35]
flight_677 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2A5) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2A5 | flight_677); // @[Decoupled.scala:51:35]
flight_678 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2A6) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2A6 | flight_678); // @[Decoupled.scala:51:35]
flight_679 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2A7) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2A7 | flight_679); // @[Decoupled.scala:51:35]
flight_680 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2A8) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2A8 | flight_680); // @[Decoupled.scala:51:35]
flight_681 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2A9) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2A9 | flight_681); // @[Decoupled.scala:51:35]
flight_682 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2AA) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2AA | flight_682); // @[Decoupled.scala:51:35]
flight_683 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2AB) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2AB | flight_683); // @[Decoupled.scala:51:35]
flight_684 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2AC) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2AC | flight_684); // @[Decoupled.scala:51:35]
flight_685 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2AD) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2AD | flight_685); // @[Decoupled.scala:51:35]
flight_686 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2AE) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2AE | flight_686); // @[Decoupled.scala:51:35]
flight_687 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2AF) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2AF | flight_687); // @[Decoupled.scala:51:35]
flight_688 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2B0) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2B0 | flight_688); // @[Decoupled.scala:51:35]
flight_689 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2B1) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2B1 | flight_689); // @[Decoupled.scala:51:35]
flight_690 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2B2) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2B2 | flight_690); // @[Decoupled.scala:51:35]
flight_691 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2B3) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2B3 | flight_691); // @[Decoupled.scala:51:35]
flight_692 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2B4) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2B4 | flight_692); // @[Decoupled.scala:51:35]
flight_693 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2B5) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2B5 | flight_693); // @[Decoupled.scala:51:35]
flight_694 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2B6) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2B6 | flight_694); // @[Decoupled.scala:51:35]
flight_695 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2B7) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2B7 | flight_695); // @[Decoupled.scala:51:35]
flight_696 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2B8) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2B8 | flight_696); // @[Decoupled.scala:51:35]
flight_697 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2B9) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2B9 | flight_697); // @[Decoupled.scala:51:35]
flight_698 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2BA) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2BA | flight_698); // @[Decoupled.scala:51:35]
flight_699 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2BB) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2BB | flight_699); // @[Decoupled.scala:51:35]
flight_700 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2BC) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2BC | flight_700); // @[Decoupled.scala:51:35]
flight_701 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2BD) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2BD | flight_701); // @[Decoupled.scala:51:35]
flight_702 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2BE) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2BE | flight_702); // @[Decoupled.scala:51:35]
flight_703 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2BF) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2BF | flight_703); // @[Decoupled.scala:51:35]
flight_704 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2C0) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2C0 | flight_704); // @[Decoupled.scala:51:35]
flight_705 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2C1) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2C1 | flight_705); // @[Decoupled.scala:51:35]
flight_706 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2C2) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2C2 | flight_706); // @[Decoupled.scala:51:35]
flight_707 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2C3) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2C3 | flight_707); // @[Decoupled.scala:51:35]
flight_708 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2C4) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2C4 | flight_708); // @[Decoupled.scala:51:35]
flight_709 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2C5) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2C5 | flight_709); // @[Decoupled.scala:51:35]
flight_710 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2C6) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2C6 | flight_710); // @[Decoupled.scala:51:35]
flight_711 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2C7) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2C7 | flight_711); // @[Decoupled.scala:51:35]
flight_712 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2C8) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2C8 | flight_712); // @[Decoupled.scala:51:35]
flight_713 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2C9) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2C9 | flight_713); // @[Decoupled.scala:51:35]
flight_714 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2CA) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2CA | flight_714); // @[Decoupled.scala:51:35]
flight_715 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2CB) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2CB | flight_715); // @[Decoupled.scala:51:35]
flight_716 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2CC) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2CC | flight_716); // @[Decoupled.scala:51:35]
flight_717 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2CD) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2CD | flight_717); // @[Decoupled.scala:51:35]
flight_718 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2CE) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2CE | flight_718); // @[Decoupled.scala:51:35]
flight_719 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2CF) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2CF | flight_719); // @[Decoupled.scala:51:35]
flight_720 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2D0) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2D0 | flight_720); // @[Decoupled.scala:51:35]
flight_721 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2D1) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2D1 | flight_721); // @[Decoupled.scala:51:35]
flight_722 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2D2) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2D2 | flight_722); // @[Decoupled.scala:51:35]
flight_723 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2D3) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2D3 | flight_723); // @[Decoupled.scala:51:35]
flight_724 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2D4) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2D4 | flight_724); // @[Decoupled.scala:51:35]
flight_725 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2D5) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2D5 | flight_725); // @[Decoupled.scala:51:35]
flight_726 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2D6) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2D6 | flight_726); // @[Decoupled.scala:51:35]
flight_727 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2D7) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2D7 | flight_727); // @[Decoupled.scala:51:35]
flight_728 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2D8) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2D8 | flight_728); // @[Decoupled.scala:51:35]
flight_729 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2D9) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2D9 | flight_729); // @[Decoupled.scala:51:35]
flight_730 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2DA) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2DA | flight_730); // @[Decoupled.scala:51:35]
flight_731 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2DB) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2DB | flight_731); // @[Decoupled.scala:51:35]
flight_732 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2DC) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2DC | flight_732); // @[Decoupled.scala:51:35]
flight_733 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2DD) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2DD | flight_733); // @[Decoupled.scala:51:35]
flight_734 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2DE) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2DE | flight_734); // @[Decoupled.scala:51:35]
flight_735 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2DF) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2DF | flight_735); // @[Decoupled.scala:51:35]
flight_736 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2E0) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2E0 | flight_736); // @[Decoupled.scala:51:35]
flight_737 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2E1) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2E1 | flight_737); // @[Decoupled.scala:51:35]
flight_738 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2E2) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2E2 | flight_738); // @[Decoupled.scala:51:35]
flight_739 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2E3) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2E3 | flight_739); // @[Decoupled.scala:51:35]
flight_740 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2E4) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2E4 | flight_740); // @[Decoupled.scala:51:35]
flight_741 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2E5) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2E5 | flight_741); // @[Decoupled.scala:51:35]
flight_742 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2E6) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2E6 | flight_742); // @[Decoupled.scala:51:35]
flight_743 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2E7) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2E7 | flight_743); // @[Decoupled.scala:51:35]
flight_744 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2E8) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2E8 | flight_744); // @[Decoupled.scala:51:35]
flight_745 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2E9) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2E9 | flight_745); // @[Decoupled.scala:51:35]
flight_746 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2EA) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2EA | flight_746); // @[Decoupled.scala:51:35]
flight_747 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2EB) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2EB | flight_747); // @[Decoupled.scala:51:35]
flight_748 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2EC) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2EC | flight_748); // @[Decoupled.scala:51:35]
flight_749 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2ED) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2ED | flight_749); // @[Decoupled.scala:51:35]
flight_750 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2EE) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2EE | flight_750); // @[Decoupled.scala:51:35]
flight_751 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2EF) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2EF | flight_751); // @[Decoupled.scala:51:35]
flight_752 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2F0) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2F0 | flight_752); // @[Decoupled.scala:51:35]
flight_753 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2F1) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2F1 | flight_753); // @[Decoupled.scala:51:35]
flight_754 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2F2) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2F2 | flight_754); // @[Decoupled.scala:51:35]
flight_755 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2F3) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2F3 | flight_755); // @[Decoupled.scala:51:35]
flight_756 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2F4) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2F4 | flight_756); // @[Decoupled.scala:51:35]
flight_757 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2F5) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2F5 | flight_757); // @[Decoupled.scala:51:35]
flight_758 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2F6) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2F6 | flight_758); // @[Decoupled.scala:51:35]
flight_759 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2F7) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2F7 | flight_759); // @[Decoupled.scala:51:35]
flight_760 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2F8) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2F8 | flight_760); // @[Decoupled.scala:51:35]
flight_761 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2F9) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2F9 | flight_761); // @[Decoupled.scala:51:35]
flight_762 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2FA) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2FA | flight_762); // @[Decoupled.scala:51:35]
flight_763 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2FB) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2FB | flight_763); // @[Decoupled.scala:51:35]
flight_764 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2FC) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2FC | flight_764); // @[Decoupled.scala:51:35]
flight_765 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2FD) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2FD | flight_765); // @[Decoupled.scala:51:35]
flight_766 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2FE) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2FE | flight_766); // @[Decoupled.scala:51:35]
flight_767 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h2FF) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h2FF | flight_767); // @[Decoupled.scala:51:35]
flight_768 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h300) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h300 | flight_768); // @[Decoupled.scala:51:35]
flight_769 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h301) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h301 | flight_769); // @[Decoupled.scala:51:35]
flight_770 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h302) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h302 | flight_770); // @[Decoupled.scala:51:35]
flight_771 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h303) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h303 | flight_771); // @[Decoupled.scala:51:35]
flight_772 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h304) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h304 | flight_772); // @[Decoupled.scala:51:35]
flight_773 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h305) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h305 | flight_773); // @[Decoupled.scala:51:35]
flight_774 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h306) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h306 | flight_774); // @[Decoupled.scala:51:35]
flight_775 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h307) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h307 | flight_775); // @[Decoupled.scala:51:35]
flight_776 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h308) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h308 | flight_776); // @[Decoupled.scala:51:35]
flight_777 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h309) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h309 | flight_777); // @[Decoupled.scala:51:35]
flight_778 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h30A) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h30A | flight_778); // @[Decoupled.scala:51:35]
flight_779 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h30B) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h30B | flight_779); // @[Decoupled.scala:51:35]
flight_780 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h30C) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h30C | flight_780); // @[Decoupled.scala:51:35]
flight_781 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h30D) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h30D | flight_781); // @[Decoupled.scala:51:35]
flight_782 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h30E) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h30E | flight_782); // @[Decoupled.scala:51:35]
flight_783 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h30F) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h30F | flight_783); // @[Decoupled.scala:51:35]
flight_784 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h310) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h310 | flight_784); // @[Decoupled.scala:51:35]
flight_785 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h311) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h311 | flight_785); // @[Decoupled.scala:51:35]
flight_786 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h312) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h312 | flight_786); // @[Decoupled.scala:51:35]
flight_787 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h313) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h313 | flight_787); // @[Decoupled.scala:51:35]
flight_788 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h314) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h314 | flight_788); // @[Decoupled.scala:51:35]
flight_789 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h315) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h315 | flight_789); // @[Decoupled.scala:51:35]
flight_790 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h316) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h316 | flight_790); // @[Decoupled.scala:51:35]
flight_791 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h317) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h317 | flight_791); // @[Decoupled.scala:51:35]
flight_792 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h318) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h318 | flight_792); // @[Decoupled.scala:51:35]
flight_793 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h319) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h319 | flight_793); // @[Decoupled.scala:51:35]
flight_794 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h31A) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h31A | flight_794); // @[Decoupled.scala:51:35]
flight_795 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h31B) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h31B | flight_795); // @[Decoupled.scala:51:35]
flight_796 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h31C) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h31C | flight_796); // @[Decoupled.scala:51:35]
flight_797 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h31D) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h31D | flight_797); // @[Decoupled.scala:51:35]
flight_798 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h31E) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h31E | flight_798); // @[Decoupled.scala:51:35]
flight_799 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h31F) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h31F | flight_799); // @[Decoupled.scala:51:35]
flight_800 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h320) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h320 | flight_800); // @[Decoupled.scala:51:35]
flight_801 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h321) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h321 | flight_801); // @[Decoupled.scala:51:35]
flight_802 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h322) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h322 | flight_802); // @[Decoupled.scala:51:35]
flight_803 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h323) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h323 | flight_803); // @[Decoupled.scala:51:35]
flight_804 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h324) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h324 | flight_804); // @[Decoupled.scala:51:35]
flight_805 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h325) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h325 | flight_805); // @[Decoupled.scala:51:35]
flight_806 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h326) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h326 | flight_806); // @[Decoupled.scala:51:35]
flight_807 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h327) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h327 | flight_807); // @[Decoupled.scala:51:35]
flight_808 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h328) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h328 | flight_808); // @[Decoupled.scala:51:35]
flight_809 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h329) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h329 | flight_809); // @[Decoupled.scala:51:35]
flight_810 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h32A) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h32A | flight_810); // @[Decoupled.scala:51:35]
flight_811 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h32B) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h32B | flight_811); // @[Decoupled.scala:51:35]
flight_812 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h32C) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h32C | flight_812); // @[Decoupled.scala:51:35]
flight_813 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h32D) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h32D | flight_813); // @[Decoupled.scala:51:35]
flight_814 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h32E) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h32E | flight_814); // @[Decoupled.scala:51:35]
flight_815 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h32F) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h32F | flight_815); // @[Decoupled.scala:51:35]
flight_816 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h330) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h330 | flight_816); // @[Decoupled.scala:51:35]
flight_817 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h331) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h331 | flight_817); // @[Decoupled.scala:51:35]
flight_818 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h332) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h332 | flight_818); // @[Decoupled.scala:51:35]
flight_819 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h333) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h333 | flight_819); // @[Decoupled.scala:51:35]
flight_820 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h334) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h334 | flight_820); // @[Decoupled.scala:51:35]
flight_821 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h335) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h335 | flight_821); // @[Decoupled.scala:51:35]
flight_822 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h336) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h336 | flight_822); // @[Decoupled.scala:51:35]
flight_823 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h337) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h337 | flight_823); // @[Decoupled.scala:51:35]
flight_824 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h338) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h338 | flight_824); // @[Decoupled.scala:51:35]
flight_825 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h339) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h339 | flight_825); // @[Decoupled.scala:51:35]
flight_826 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h33A) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h33A | flight_826); // @[Decoupled.scala:51:35]
flight_827 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h33B) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h33B | flight_827); // @[Decoupled.scala:51:35]
flight_828 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h33C) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h33C | flight_828); // @[Decoupled.scala:51:35]
flight_829 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h33D) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h33D | flight_829); // @[Decoupled.scala:51:35]
flight_830 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h33E) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h33E | flight_830); // @[Decoupled.scala:51:35]
flight_831 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h33F) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h33F | flight_831); // @[Decoupled.scala:51:35]
flight_832 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h340) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h340 | flight_832); // @[Decoupled.scala:51:35]
flight_833 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h341) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h341 | flight_833); // @[Decoupled.scala:51:35]
flight_834 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h342) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h342 | flight_834); // @[Decoupled.scala:51:35]
flight_835 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h343) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h343 | flight_835); // @[Decoupled.scala:51:35]
flight_836 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h344) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h344 | flight_836); // @[Decoupled.scala:51:35]
flight_837 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h345) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h345 | flight_837); // @[Decoupled.scala:51:35]
flight_838 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h346) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h346 | flight_838); // @[Decoupled.scala:51:35]
flight_839 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h347) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h347 | flight_839); // @[Decoupled.scala:51:35]
flight_840 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h348) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h348 | flight_840); // @[Decoupled.scala:51:35]
flight_841 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h349) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h349 | flight_841); // @[Decoupled.scala:51:35]
flight_842 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h34A) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h34A | flight_842); // @[Decoupled.scala:51:35]
flight_843 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h34B) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h34B | flight_843); // @[Decoupled.scala:51:35]
flight_844 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h34C) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h34C | flight_844); // @[Decoupled.scala:51:35]
flight_845 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h34D) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h34D | flight_845); // @[Decoupled.scala:51:35]
flight_846 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h34E) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h34E | flight_846); // @[Decoupled.scala:51:35]
flight_847 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h34F) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h34F | flight_847); // @[Decoupled.scala:51:35]
flight_848 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h350) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h350 | flight_848); // @[Decoupled.scala:51:35]
flight_849 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h351) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h351 | flight_849); // @[Decoupled.scala:51:35]
flight_850 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h352) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h352 | flight_850); // @[Decoupled.scala:51:35]
flight_851 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h353) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h353 | flight_851); // @[Decoupled.scala:51:35]
flight_852 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h354) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h354 | flight_852); // @[Decoupled.scala:51:35]
flight_853 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h355) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h355 | flight_853); // @[Decoupled.scala:51:35]
flight_854 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h356) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h356 | flight_854); // @[Decoupled.scala:51:35]
flight_855 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h357) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h357 | flight_855); // @[Decoupled.scala:51:35]
flight_856 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h358) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h358 | flight_856); // @[Decoupled.scala:51:35]
flight_857 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h359) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h359 | flight_857); // @[Decoupled.scala:51:35]
flight_858 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h35A) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h35A | flight_858); // @[Decoupled.scala:51:35]
flight_859 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h35B) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h35B | flight_859); // @[Decoupled.scala:51:35]
flight_860 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h35C) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h35C | flight_860); // @[Decoupled.scala:51:35]
flight_861 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h35D) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h35D | flight_861); // @[Decoupled.scala:51:35]
flight_862 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h35E) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h35E | flight_862); // @[Decoupled.scala:51:35]
flight_863 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h35F) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h35F | flight_863); // @[Decoupled.scala:51:35]
flight_864 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h360) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h360 | flight_864); // @[Decoupled.scala:51:35]
flight_865 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h361) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h361 | flight_865); // @[Decoupled.scala:51:35]
flight_866 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h362) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h362 | flight_866); // @[Decoupled.scala:51:35]
flight_867 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h363) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h363 | flight_867); // @[Decoupled.scala:51:35]
flight_868 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h364) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h364 | flight_868); // @[Decoupled.scala:51:35]
flight_869 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h365) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h365 | flight_869); // @[Decoupled.scala:51:35]
flight_870 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h366) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h366 | flight_870); // @[Decoupled.scala:51:35]
flight_871 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h367) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h367 | flight_871); // @[Decoupled.scala:51:35]
flight_872 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h368) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h368 | flight_872); // @[Decoupled.scala:51:35]
flight_873 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h369) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h369 | flight_873); // @[Decoupled.scala:51:35]
flight_874 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h36A) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h36A | flight_874); // @[Decoupled.scala:51:35]
flight_875 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h36B) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h36B | flight_875); // @[Decoupled.scala:51:35]
flight_876 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h36C) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h36C | flight_876); // @[Decoupled.scala:51:35]
flight_877 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h36D) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h36D | flight_877); // @[Decoupled.scala:51:35]
flight_878 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h36E) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h36E | flight_878); // @[Decoupled.scala:51:35]
flight_879 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h36F) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h36F | flight_879); // @[Decoupled.scala:51:35]
flight_880 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h370) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h370 | flight_880); // @[Decoupled.scala:51:35]
flight_881 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h371) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h371 | flight_881); // @[Decoupled.scala:51:35]
flight_882 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h372) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h372 | flight_882); // @[Decoupled.scala:51:35]
flight_883 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h373) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h373 | flight_883); // @[Decoupled.scala:51:35]
flight_884 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h374) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h374 | flight_884); // @[Decoupled.scala:51:35]
flight_885 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h375) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h375 | flight_885); // @[Decoupled.scala:51:35]
flight_886 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h376) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h376 | flight_886); // @[Decoupled.scala:51:35]
flight_887 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h377) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h377 | flight_887); // @[Decoupled.scala:51:35]
flight_888 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h378) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h378 | flight_888); // @[Decoupled.scala:51:35]
flight_889 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h379) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h379 | flight_889); // @[Decoupled.scala:51:35]
flight_890 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h37A) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h37A | flight_890); // @[Decoupled.scala:51:35]
flight_891 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h37B) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h37B | flight_891); // @[Decoupled.scala:51:35]
flight_892 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h37C) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h37C | flight_892); // @[Decoupled.scala:51:35]
flight_893 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h37D) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h37D | flight_893); // @[Decoupled.scala:51:35]
flight_894 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h37E) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h37E | flight_894); // @[Decoupled.scala:51:35]
flight_895 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h37F) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h37F | flight_895); // @[Decoupled.scala:51:35]
flight_896 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h380) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h380 | flight_896); // @[Decoupled.scala:51:35]
flight_897 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h381) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h381 | flight_897); // @[Decoupled.scala:51:35]
flight_898 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h382) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h382 | flight_898); // @[Decoupled.scala:51:35]
flight_899 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h383) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h383 | flight_899); // @[Decoupled.scala:51:35]
flight_900 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h384) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h384 | flight_900); // @[Decoupled.scala:51:35]
flight_901 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h385) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h385 | flight_901); // @[Decoupled.scala:51:35]
flight_902 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h386) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h386 | flight_902); // @[Decoupled.scala:51:35]
flight_903 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h387) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h387 | flight_903); // @[Decoupled.scala:51:35]
flight_904 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h388) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h388 | flight_904); // @[Decoupled.scala:51:35]
flight_905 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h389) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h389 | flight_905); // @[Decoupled.scala:51:35]
flight_906 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h38A) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h38A | flight_906); // @[Decoupled.scala:51:35]
flight_907 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h38B) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h38B | flight_907); // @[Decoupled.scala:51:35]
flight_908 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h38C) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h38C | flight_908); // @[Decoupled.scala:51:35]
flight_909 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h38D) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h38D | flight_909); // @[Decoupled.scala:51:35]
flight_910 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h38E) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h38E | flight_910); // @[Decoupled.scala:51:35]
flight_911 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h38F) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h38F | flight_911); // @[Decoupled.scala:51:35]
flight_912 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h390) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h390 | flight_912); // @[Decoupled.scala:51:35]
flight_913 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h391) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h391 | flight_913); // @[Decoupled.scala:51:35]
flight_914 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h392) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h392 | flight_914); // @[Decoupled.scala:51:35]
flight_915 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h393) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h393 | flight_915); // @[Decoupled.scala:51:35]
flight_916 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h394) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h394 | flight_916); // @[Decoupled.scala:51:35]
flight_917 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h395) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h395 | flight_917); // @[Decoupled.scala:51:35]
flight_918 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h396) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h396 | flight_918); // @[Decoupled.scala:51:35]
flight_919 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h397) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h397 | flight_919); // @[Decoupled.scala:51:35]
flight_920 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h398) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h398 | flight_920); // @[Decoupled.scala:51:35]
flight_921 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h399) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h399 | flight_921); // @[Decoupled.scala:51:35]
flight_922 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h39A) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h39A | flight_922); // @[Decoupled.scala:51:35]
flight_923 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h39B) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h39B | flight_923); // @[Decoupled.scala:51:35]
flight_924 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h39C) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h39C | flight_924); // @[Decoupled.scala:51:35]
flight_925 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h39D) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h39D | flight_925); // @[Decoupled.scala:51:35]
flight_926 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h39E) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h39E | flight_926); // @[Decoupled.scala:51:35]
flight_927 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h39F) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h39F | flight_927); // @[Decoupled.scala:51:35]
flight_928 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3A0) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3A0 | flight_928); // @[Decoupled.scala:51:35]
flight_929 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3A1) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3A1 | flight_929); // @[Decoupled.scala:51:35]
flight_930 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3A2) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3A2 | flight_930); // @[Decoupled.scala:51:35]
flight_931 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3A3) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3A3 | flight_931); // @[Decoupled.scala:51:35]
flight_932 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3A4) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3A4 | flight_932); // @[Decoupled.scala:51:35]
flight_933 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3A5) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3A5 | flight_933); // @[Decoupled.scala:51:35]
flight_934 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3A6) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3A6 | flight_934); // @[Decoupled.scala:51:35]
flight_935 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3A7) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3A7 | flight_935); // @[Decoupled.scala:51:35]
flight_936 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3A8) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3A8 | flight_936); // @[Decoupled.scala:51:35]
flight_937 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3A9) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3A9 | flight_937); // @[Decoupled.scala:51:35]
flight_938 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3AA) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3AA | flight_938); // @[Decoupled.scala:51:35]
flight_939 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3AB) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3AB | flight_939); // @[Decoupled.scala:51:35]
flight_940 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3AC) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3AC | flight_940); // @[Decoupled.scala:51:35]
flight_941 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3AD) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3AD | flight_941); // @[Decoupled.scala:51:35]
flight_942 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3AE) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3AE | flight_942); // @[Decoupled.scala:51:35]
flight_943 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3AF) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3AF | flight_943); // @[Decoupled.scala:51:35]
flight_944 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3B0) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3B0 | flight_944); // @[Decoupled.scala:51:35]
flight_945 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3B1) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3B1 | flight_945); // @[Decoupled.scala:51:35]
flight_946 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3B2) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3B2 | flight_946); // @[Decoupled.scala:51:35]
flight_947 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3B3) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3B3 | flight_947); // @[Decoupled.scala:51:35]
flight_948 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3B4) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3B4 | flight_948); // @[Decoupled.scala:51:35]
flight_949 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3B5) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3B5 | flight_949); // @[Decoupled.scala:51:35]
flight_950 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3B6) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3B6 | flight_950); // @[Decoupled.scala:51:35]
flight_951 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3B7) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3B7 | flight_951); // @[Decoupled.scala:51:35]
flight_952 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3B8) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3B8 | flight_952); // @[Decoupled.scala:51:35]
flight_953 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3B9) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3B9 | flight_953); // @[Decoupled.scala:51:35]
flight_954 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3BA) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3BA | flight_954); // @[Decoupled.scala:51:35]
flight_955 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3BB) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3BB | flight_955); // @[Decoupled.scala:51:35]
flight_956 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3BC) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3BC | flight_956); // @[Decoupled.scala:51:35]
flight_957 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3BD) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3BD | flight_957); // @[Decoupled.scala:51:35]
flight_958 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3BE) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3BE | flight_958); // @[Decoupled.scala:51:35]
flight_959 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3BF) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3BF | flight_959); // @[Decoupled.scala:51:35]
flight_960 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3C0) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3C0 | flight_960); // @[Decoupled.scala:51:35]
flight_961 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3C1) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3C1 | flight_961); // @[Decoupled.scala:51:35]
flight_962 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3C2) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3C2 | flight_962); // @[Decoupled.scala:51:35]
flight_963 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3C3) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3C3 | flight_963); // @[Decoupled.scala:51:35]
flight_964 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3C4) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3C4 | flight_964); // @[Decoupled.scala:51:35]
flight_965 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3C5) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3C5 | flight_965); // @[Decoupled.scala:51:35]
flight_966 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3C6) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3C6 | flight_966); // @[Decoupled.scala:51:35]
flight_967 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3C7) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3C7 | flight_967); // @[Decoupled.scala:51:35]
flight_968 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3C8) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3C8 | flight_968); // @[Decoupled.scala:51:35]
flight_969 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3C9) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3C9 | flight_969); // @[Decoupled.scala:51:35]
flight_970 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3CA) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3CA | flight_970); // @[Decoupled.scala:51:35]
flight_971 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3CB) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3CB | flight_971); // @[Decoupled.scala:51:35]
flight_972 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3CC) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3CC | flight_972); // @[Decoupled.scala:51:35]
flight_973 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3CD) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3CD | flight_973); // @[Decoupled.scala:51:35]
flight_974 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3CE) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3CE | flight_974); // @[Decoupled.scala:51:35]
flight_975 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3CF) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3CF | flight_975); // @[Decoupled.scala:51:35]
flight_976 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3D0) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3D0 | flight_976); // @[Decoupled.scala:51:35]
flight_977 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3D1) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3D1 | flight_977); // @[Decoupled.scala:51:35]
flight_978 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3D2) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3D2 | flight_978); // @[Decoupled.scala:51:35]
flight_979 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3D3) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3D3 | flight_979); // @[Decoupled.scala:51:35]
flight_980 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3D4) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3D4 | flight_980); // @[Decoupled.scala:51:35]
flight_981 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3D5) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3D5 | flight_981); // @[Decoupled.scala:51:35]
flight_982 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3D6) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3D6 | flight_982); // @[Decoupled.scala:51:35]
flight_983 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3D7) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3D7 | flight_983); // @[Decoupled.scala:51:35]
flight_984 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3D8) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3D8 | flight_984); // @[Decoupled.scala:51:35]
flight_985 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3D9) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3D9 | flight_985); // @[Decoupled.scala:51:35]
flight_986 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3DA) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3DA | flight_986); // @[Decoupled.scala:51:35]
flight_987 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3DB) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3DB | flight_987); // @[Decoupled.scala:51:35]
flight_988 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3DC) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3DC | flight_988); // @[Decoupled.scala:51:35]
flight_989 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3DD) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3DD | flight_989); // @[Decoupled.scala:51:35]
flight_990 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3DE) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3DE | flight_990); // @[Decoupled.scala:51:35]
flight_991 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3DF) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3DF | flight_991); // @[Decoupled.scala:51:35]
flight_992 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3E0) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3E0 | flight_992); // @[Decoupled.scala:51:35]
flight_993 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3E1) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3E1 | flight_993); // @[Decoupled.scala:51:35]
flight_994 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3E2) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3E2 | flight_994); // @[Decoupled.scala:51:35]
flight_995 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3E3) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3E3 | flight_995); // @[Decoupled.scala:51:35]
flight_996 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3E4) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3E4 | flight_996); // @[Decoupled.scala:51:35]
flight_997 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3E5) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3E5 | flight_997); // @[Decoupled.scala:51:35]
flight_998 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3E6) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3E6 | flight_998); // @[Decoupled.scala:51:35]
flight_999 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3E7) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3E7 | flight_999); // @[Decoupled.scala:51:35]
flight_1000 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3E8) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3E8 | flight_1000); // @[Decoupled.scala:51:35]
flight_1001 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3E9) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3E9 | flight_1001); // @[Decoupled.scala:51:35]
flight_1002 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3EA) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3EA | flight_1002); // @[Decoupled.scala:51:35]
flight_1003 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3EB) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3EB | flight_1003); // @[Decoupled.scala:51:35]
flight_1004 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3EC) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3EC | flight_1004); // @[Decoupled.scala:51:35]
flight_1005 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3ED) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3ED | flight_1005); // @[Decoupled.scala:51:35]
flight_1006 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3EE) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3EE | flight_1006); // @[Decoupled.scala:51:35]
flight_1007 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3EF) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3EF | flight_1007); // @[Decoupled.scala:51:35]
flight_1008 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3F0) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3F0 | flight_1008); // @[Decoupled.scala:51:35]
flight_1009 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3F1) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3F1 | flight_1009); // @[Decoupled.scala:51:35]
flight_1010 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3F2) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3F2 | flight_1010); // @[Decoupled.scala:51:35]
flight_1011 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3F3) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3F3 | flight_1011); // @[Decoupled.scala:51:35]
flight_1012 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3F4) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3F4 | flight_1012); // @[Decoupled.scala:51:35]
flight_1013 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3F5) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3F5 | flight_1013); // @[Decoupled.scala:51:35]
flight_1014 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3F6) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3F6 | flight_1014); // @[Decoupled.scala:51:35]
flight_1015 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3F7) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3F7 | flight_1015); // @[Decoupled.scala:51:35]
flight_1016 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3F8) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3F8 | flight_1016); // @[Decoupled.scala:51:35]
flight_1017 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3F9) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3F9 | flight_1017); // @[Decoupled.scala:51:35]
flight_1018 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3FA) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3FA | flight_1018); // @[Decoupled.scala:51:35]
flight_1019 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3FB) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3FB | flight_1019); // @[Decoupled.scala:51:35]
flight_1020 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3FC) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3FC | flight_1020); // @[Decoupled.scala:51:35]
flight_1021 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3FD) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3FD | flight_1021); // @[Decoupled.scala:51:35]
flight_1022 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3FE) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3FE | flight_1022); // @[Decoupled.scala:51:35]
flight_1023 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h3FF) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h3FF | flight_1023); // @[Decoupled.scala:51:35]
flight_1024 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h400) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h400 | flight_1024); // @[Decoupled.scala:51:35]
flight_1025 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h401) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h401 | flight_1025); // @[Decoupled.scala:51:35]
flight_1026 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h402) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h402 | flight_1026); // @[Decoupled.scala:51:35]
flight_1027 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h403) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h403 | flight_1027); // @[Decoupled.scala:51:35]
flight_1028 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h404) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h404 | flight_1028); // @[Decoupled.scala:51:35]
flight_1029 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h405) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h405 | flight_1029); // @[Decoupled.scala:51:35]
flight_1030 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h406) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h406 | flight_1030); // @[Decoupled.scala:51:35]
flight_1031 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h407) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h407 | flight_1031); // @[Decoupled.scala:51:35]
flight_1032 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h408) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h408 | flight_1032); // @[Decoupled.scala:51:35]
flight_1033 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h409) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h409 | flight_1033); // @[Decoupled.scala:51:35]
flight_1034 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h40A) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h40A | flight_1034); // @[Decoupled.scala:51:35]
flight_1035 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h40B) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h40B | flight_1035); // @[Decoupled.scala:51:35]
flight_1036 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h40C) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h40C | flight_1036); // @[Decoupled.scala:51:35]
flight_1037 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h40D) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h40D | flight_1037); // @[Decoupled.scala:51:35]
flight_1038 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h40E) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h40E | flight_1038); // @[Decoupled.scala:51:35]
flight_1039 <= ~(_GEN_3 & auto_anon_out_d_bits_source == 11'h40F) & (_GEN_4 & auto_anon_in_a_bits_source == 11'h40F | flight_1039); // @[Decoupled.scala:51:35]
end
if (a_first_done & stalls_a_sel) // @[Decoupled.scala:51:35]
stalls_id <= a_id; // @[Mux.scala:30:73]
always @(posedge) |
Generate the Verilog code corresponding to the following Chisel files.
File TilelinkAdapters.scala:
package constellation.protocol
import chisel3._
import chisel3.util._
import constellation.channel._
import constellation.noc._
import constellation.soc.{CanAttachToGlobalNoC}
import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.util._
import freechips.rocketchip.tilelink._
import scala.collection.immutable.{ListMap}
abstract class TLChannelToNoC[T <: TLChannel](gen: => T, edge: TLEdge, idToEgress: Int => Int)(implicit val p: Parameters) extends Module with TLFieldHelper {
val flitWidth = minTLPayloadWidth(gen)
val io = IO(new Bundle {
val protocol = Flipped(Decoupled(gen))
val flit = Decoupled(new IngressFlit(flitWidth))
})
def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B
// convert decoupled to irrevocable
val q = Module(new Queue(gen, 1, pipe=true, flow=true))
val protocol = q.io.deq
val has_body = Wire(Bool())
val body_fields = getBodyFields(protocol.bits)
val const_fields = getConstFields(protocol.bits)
val head = edge.first(protocol.bits, protocol.fire)
val tail = edge.last(protocol.bits, protocol.fire)
def requestOH: Seq[Bool]
val body = Cat( body_fields.filter(_.getWidth > 0).map(_.asUInt))
val const = Cat(const_fields.filter(_.getWidth > 0).map(_.asUInt))
val is_body = RegInit(false.B)
io.flit.valid := protocol.valid
protocol.ready := io.flit.ready && (is_body || !has_body)
io.flit.bits.head := head && !is_body
io.flit.bits.tail := tail && (is_body || !has_body)
io.flit.bits.egress_id := Mux1H(requestOH.zipWithIndex.map { case (r, i) =>
r -> idToEgress(i).U
})
io.flit.bits.payload := Mux(is_body, body, const)
when (io.flit.fire && io.flit.bits.head) { is_body := true.B }
when (io.flit.fire && io.flit.bits.tail) { is_body := false.B }
}
abstract class TLChannelFromNoC[T <: TLChannel](gen: => T)(implicit val p: Parameters) extends Module with TLFieldHelper {
val flitWidth = minTLPayloadWidth(gen)
val io = IO(new Bundle {
val protocol = Decoupled(gen)
val flit = Flipped(Decoupled(new EgressFlit(flitWidth)))
})
// Handle size = 1 gracefully (Chisel3 empty range is broken)
def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0)
val protocol = Wire(Decoupled(gen))
val body_fields = getBodyFields(protocol.bits)
val const_fields = getConstFields(protocol.bits)
val is_const = RegInit(true.B)
val const_reg = Reg(UInt(const_fields.map(_.getWidth).sum.W))
val const = Mux(io.flit.bits.head, io.flit.bits.payload, const_reg)
io.flit.ready := (is_const && !io.flit.bits.tail) || protocol.ready
protocol.valid := (!is_const || io.flit.bits.tail) && io.flit.valid
def assign(i: UInt, sigs: Seq[Data]) = {
var t = i
for (s <- sigs.reverse) {
s := t.asTypeOf(s.cloneType)
t = t >> s.getWidth
}
}
assign(const, const_fields)
assign(io.flit.bits.payload, body_fields)
when (io.flit.fire && io.flit.bits.head) { is_const := false.B; const_reg := io.flit.bits.payload }
when (io.flit.fire && io.flit.bits.tail) { is_const := true.B }
}
trait HasAddressDecoder {
// Filter a list to only those elements selected
def filter[T](data: Seq[T], mask: Seq[Boolean]) = (data zip mask).filter(_._2).map(_._1)
val edgeIn: TLEdge
val edgesOut: Seq[TLEdge]
lazy val reacheableIO = edgesOut.map { mp =>
edgeIn.client.clients.exists { c => mp.manager.managers.exists { m =>
c.visibility.exists { ca => m.address.exists { ma =>
ca.overlaps(ma)
}}
}}
}.toVector
lazy val releaseIO = (edgesOut zip reacheableIO).map { case (mp, reachable) =>
reachable && edgeIn.client.anySupportProbe && mp.manager.anySupportAcquireB
}.toVector
def outputPortFn(connectIO: Seq[Boolean]) = {
val port_addrs = edgesOut.map(_.manager.managers.flatMap(_.address))
val routingMask = AddressDecoder(filter(port_addrs, connectIO))
val route_addrs = port_addrs.map(seq => AddressSet.unify(seq.map(_.widen(~routingMask)).distinct))
route_addrs.map(seq => (addr: UInt) => seq.map(_.contains(addr)).reduce(_||_))
}
}
class TLAToNoC(
val edgeIn: TLEdge,
val edgesOut: Seq[TLEdge],
bundle: TLBundleParameters,
slaveToAEgress: Int => Int,
sourceStart: Int
)(implicit p: Parameters) extends TLChannelToNoC(new TLBundleA(bundle), edgeIn, slaveToAEgress)(p) with HasAddressDecoder {
has_body := edgeIn.hasData(protocol.bits) || (~protocol.bits.mask =/= 0.U)
lazy val connectAIO = reacheableIO
lazy val requestOH = outputPortFn(connectAIO).zipWithIndex.map { case (o, j) =>
connectAIO(j).B && (unique(connectAIO) || o(protocol.bits.address))
}
q.io.enq <> io.protocol
q.io.enq.bits.source := io.protocol.bits.source | sourceStart.U
}
class TLAFromNoC(edgeOut: TLEdge, bundle: TLBundleParameters)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleA(bundle))(p) {
io.protocol <> protocol
when (io.flit.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) }
}
class TLBToNoC(
edgeOut: TLEdge,
edgesIn: Seq[TLEdge],
bundle: TLBundleParameters,
masterToBIngress: Int => Int
)(implicit p: Parameters) extends TLChannelToNoC(new TLBundleB(bundle), edgeOut, masterToBIngress)(p) {
has_body := edgeOut.hasData(protocol.bits) || (~protocol.bits.mask =/= 0.U)
lazy val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client))
lazy val requestOH = inputIdRanges.map { i => i.contains(protocol.bits.source) }
q.io.enq <> io.protocol
}
class TLBFromNoC(edgeIn: TLEdge, bundle: TLBundleParameters, sourceSize: Int)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleB(bundle))(p) {
io.protocol <> protocol
io.protocol.bits.source := trim(protocol.bits.source, sourceSize)
when (io.flit.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) }
}
class TLCToNoC(
val edgeIn: TLEdge,
val edgesOut: Seq[TLEdge],
bundle: TLBundleParameters,
slaveToCEgress: Int => Int,
sourceStart: Int
)(implicit p: Parameters) extends TLChannelToNoC(new TLBundleC(bundle), edgeIn, slaveToCEgress)(p) with HasAddressDecoder {
has_body := edgeIn.hasData(protocol.bits)
lazy val connectCIO = releaseIO
lazy val requestOH = outputPortFn(connectCIO).zipWithIndex.map {
case (o, j) => connectCIO(j).B && (unique(connectCIO) || o(protocol.bits.address))
}
q.io.enq <> io.protocol
q.io.enq.bits.source := io.protocol.bits.source | sourceStart.U
}
class TLCFromNoC(edgeOut: TLEdge, bundle: TLBundleParameters)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleC(bundle))(p) {
io.protocol <> protocol
}
class TLDToNoC(
edgeOut: TLEdge,
edgesIn: Seq[TLEdge],
bundle: TLBundleParameters,
masterToDIngress: Int => Int,
sourceStart: Int
)(implicit p: Parameters) extends TLChannelToNoC(new TLBundleD(bundle), edgeOut, masterToDIngress)(p) {
has_body := edgeOut.hasData(protocol.bits)
lazy val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client))
lazy val requestOH = inputIdRanges.map { i => i.contains(protocol.bits.source) }
q.io.enq <> io.protocol
q.io.enq.bits.sink := io.protocol.bits.sink | sourceStart.U
}
class TLDFromNoC(edgeIn: TLEdge, bundle: TLBundleParameters, sourceSize: Int)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleD(bundle))(p)
{
io.protocol <> protocol
io.protocol.bits.source := trim(protocol.bits.source, sourceSize)
}
class TLEToNoC(
val edgeIn: TLEdge,
val edgesOut: Seq[TLEdge],
bundle: TLBundleParameters,
slaveToEEgress: Int => Int
)(implicit p: Parameters) extends TLChannelToNoC(new TLBundleE(bundle), edgeIn, slaveToEEgress)(p) {
has_body := edgeIn.hasData(protocol.bits)
lazy val outputIdRanges = TLXbar.mapOutputIds(edgesOut.map(_.manager))
lazy val requestOH = outputIdRanges.map { o => o.contains(protocol.bits.sink) }
q.io.enq <> io.protocol
}
class TLEFromNoC(edgeOut: TLEdge, bundle: TLBundleParameters, sourceSize: Int)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleE(bundle))(p) {
io.protocol <> protocol
io.protocol.bits.sink := trim(protocol.bits.sink, sourceSize)
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLAToNoC_4( // @[TilelinkAdapters.scala:112:7]
input clock, // @[TilelinkAdapters.scala:112:7]
input reset, // @[TilelinkAdapters.scala:112:7]
output io_protocol_ready, // @[TilelinkAdapters.scala:19:14]
input io_protocol_valid, // @[TilelinkAdapters.scala:19:14]
input [2:0] io_protocol_bits_opcode, // @[TilelinkAdapters.scala:19:14]
input [2:0] io_protocol_bits_param, // @[TilelinkAdapters.scala:19:14]
input [3:0] io_protocol_bits_size, // @[TilelinkAdapters.scala:19:14]
input [5:0] io_protocol_bits_source, // @[TilelinkAdapters.scala:19:14]
input [31:0] io_protocol_bits_address, // @[TilelinkAdapters.scala:19:14]
input [7:0] io_protocol_bits_mask, // @[TilelinkAdapters.scala:19:14]
input [63:0] io_protocol_bits_data, // @[TilelinkAdapters.scala:19:14]
input io_protocol_bits_corrupt, // @[TilelinkAdapters.scala:19:14]
input io_flit_ready, // @[TilelinkAdapters.scala:19:14]
output io_flit_valid, // @[TilelinkAdapters.scala:19:14]
output io_flit_bits_head, // @[TilelinkAdapters.scala:19:14]
output io_flit_bits_tail, // @[TilelinkAdapters.scala:19:14]
output [72:0] io_flit_bits_payload, // @[TilelinkAdapters.scala:19:14]
output [5:0] io_flit_bits_egress_id // @[TilelinkAdapters.scala:19:14]
);
wire [8:0] _GEN; // @[TilelinkAdapters.scala:119:{45,69}]
wire _q_io_deq_valid; // @[TilelinkAdapters.scala:26:17]
wire [2:0] _q_io_deq_bits_opcode; // @[TilelinkAdapters.scala:26:17]
wire [2:0] _q_io_deq_bits_param; // @[TilelinkAdapters.scala:26:17]
wire [3:0] _q_io_deq_bits_size; // @[TilelinkAdapters.scala:26:17]
wire [5:0] _q_io_deq_bits_source; // @[TilelinkAdapters.scala:26:17]
wire [31:0] _q_io_deq_bits_address; // @[TilelinkAdapters.scala:26:17]
wire [7:0] _q_io_deq_bits_mask; // @[TilelinkAdapters.scala:26:17]
wire [63:0] _q_io_deq_bits_data; // @[TilelinkAdapters.scala:26:17]
wire _q_io_deq_bits_corrupt; // @[TilelinkAdapters.scala:26:17]
wire [26:0] _tail_beats1_decode_T = 27'hFFF << _q_io_deq_bits_size; // @[package.scala:243:71]
reg [8:0] head_counter; // @[Edges.scala:229:27]
wire head = head_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire [8:0] tail_beats1 = _q_io_deq_bits_opcode[2] ? 9'h0 : ~(_tail_beats1_decode_T[11:3]); // @[package.scala:243:{46,71,76}]
reg [8:0] tail_counter; // @[Edges.scala:229:27]
reg is_body; // @[TilelinkAdapters.scala:39:24]
wire _io_flit_bits_tail_T = _GEN == 9'h0; // @[TilelinkAdapters.scala:119:{45,69}]
wire q_io_deq_ready = io_flit_ready & (is_body | _io_flit_bits_tail_T); // @[TilelinkAdapters.scala:39:24, :41:{35,47}, :119:{45,69}]
wire io_flit_bits_head_0 = head & ~is_body; // @[Edges.scala:231:25]
wire io_flit_bits_tail_0 = (tail_counter == 9'h1 | tail_beats1 == 9'h0) & (is_body | _io_flit_bits_tail_T); // @[Edges.scala:221:14, :229:27, :232:{25,33,43}]
wire [21:0] _GEN_0 = _q_io_deq_bits_address[27:6] ^ 22'h200001; // @[Parameters.scala:137:31]
wire [25:0] _io_flit_bits_egress_id_requestOH_T_35 = _q_io_deq_bits_address[31:6] ^ 26'h2000001; // @[Parameters.scala:137:31]
wire [21:0] _GEN_1 = _q_io_deq_bits_address[27:6] ^ 22'h200002; // @[Parameters.scala:137:31]
wire [25:0] _io_flit_bits_egress_id_requestOH_T_47 = _q_io_deq_bits_address[31:6] ^ 26'h2000002; // @[Parameters.scala:137:31]
wire [21:0] _GEN_2 = _q_io_deq_bits_address[27:6] ^ 22'h200003; // @[Parameters.scala:137:31]
wire [25:0] _io_flit_bits_egress_id_requestOH_T_59 = _q_io_deq_bits_address[31:6] ^ 26'h2000003; // @[Parameters.scala:137:31]
assign _GEN = {~(_q_io_deq_bits_opcode[2]), ~_q_io_deq_bits_mask}; // @[Edges.scala:92:{28,37}]
wire _GEN_3 = io_flit_ready & _q_io_deq_valid; // @[Decoupled.scala:51:35]
always @(posedge clock) begin // @[TilelinkAdapters.scala:112:7]
if (reset) begin // @[TilelinkAdapters.scala:112:7]
head_counter <= 9'h0; // @[Edges.scala:229:27]
tail_counter <= 9'h0; // @[Edges.scala:229:27]
is_body <= 1'h0; // @[TilelinkAdapters.scala:39:24, :112:7]
end
else begin // @[TilelinkAdapters.scala:112:7]
if (q_io_deq_ready & _q_io_deq_valid) begin // @[Decoupled.scala:51:35]
head_counter <= head ? (_q_io_deq_bits_opcode[2] ? 9'h0 : ~(_tail_beats1_decode_T[11:3])) : head_counter - 9'h1; // @[package.scala:243:{46,71,76}]
tail_counter <= tail_counter == 9'h0 ? tail_beats1 : tail_counter - 9'h1; // @[Edges.scala:221:14, :229:27, :230:28, :231:25, :236:21]
end
is_body <= ~(_GEN_3 & io_flit_bits_tail_0) & (_GEN_3 & io_flit_bits_head_0 | is_body); // @[Decoupled.scala:51:35]
end
always @(posedge) |
Generate the Verilog code corresponding to the following Chisel files.
File PE.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle {
val dataflow = UInt(1.W) // TODO make this an Enum
val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)?
val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats
}
class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module {
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(inputType)
val in_c = Input(cType)
val out_d = Output(dType)
})
io.out_d := io.in_c.mac(io.in_a, io.in_b)
}
// TODO update documentation
/**
* A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh.
* @param width Data width of operands
*/
class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int)
(implicit ev: Arithmetic[T]) extends Module { // Debugging variables
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(outputType)
val in_d = Input(outputType)
val out_a = Output(inputType)
val out_b = Output(outputType)
val out_c = Output(outputType)
val in_control = Input(new PEControl(accType))
val out_control = Output(new PEControl(accType))
val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W))
val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W))
val in_last = Input(Bool())
val out_last = Output(Bool())
val in_valid = Input(Bool())
val out_valid = Output(Bool())
val bad_dataflow = Output(Bool())
})
val cType = if (df == Dataflow.WS) inputType else accType
// When creating PEs that support multiple dataflows, the
// elaboration/synthesis tools often fail to consolidate and de-duplicate
// MAC units. To force mac circuitry to be re-used, we create a "mac_unit"
// module here which just performs a single MAC operation
val mac_unit = Module(new MacUnit(inputType,
if (df == Dataflow.WS) outputType else accType, outputType))
val a = io.in_a
val b = io.in_b
val d = io.in_d
val c1 = Reg(cType)
val c2 = Reg(cType)
val dataflow = io.in_control.dataflow
val prop = io.in_control.propagate
val shift = io.in_control.shift
val id = io.in_id
val last = io.in_last
val valid = io.in_valid
io.out_a := a
io.out_control.dataflow := dataflow
io.out_control.propagate := prop
io.out_control.shift := shift
io.out_id := id
io.out_last := last
io.out_valid := valid
mac_unit.io.in_a := a
val last_s = RegEnable(prop, valid)
val flip = last_s =/= prop
val shift_offset = Mux(flip, shift, 0.U)
// Which dataflow are we using?
val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W)
val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W)
// Is c1 being computed on, or propagated forward (in the output-stationary dataflow)?
val COMPUTE = 0.U(1.W)
val PROPAGATE = 1.U(1.W)
io.bad_dataflow := false.B
when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
c2 := mac_unit.io.out_d
c1 := d.withWidthOf(cType)
}.otherwise {
io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c1
c1 := mac_unit.io.out_d
c2 := d.withWidthOf(cType)
}
}.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := c1
mac_unit.io.in_b := c2.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c1 := d
}.otherwise {
io.out_c := c2
mac_unit.io.in_b := c1.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c2 := d
}
}.otherwise {
io.bad_dataflow := true.B
//assert(false.B, "unknown dataflow")
io.out_c := DontCare
io.out_b := DontCare
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
}
when (!valid) {
c1 := c1
c2 := c2
mac_unit.io.in_b := DontCare
mac_unit.io.in_c := DontCare
}
}
File Arithmetic.scala:
// A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own:
// implicit MyTypeArithmetic extends Arithmetic[MyType] { ... }
package gemmini
import chisel3._
import chisel3.util._
import hardfloat._
// Bundles that represent the raw bits of custom datatypes
case class Float(expWidth: Int, sigWidth: Int) extends Bundle {
val bits = UInt((expWidth + sigWidth).W)
val bias: Int = (1 << (expWidth-1)) - 1
}
case class DummySInt(w: Int) extends Bundle {
val bits = UInt(w.W)
def dontCare: DummySInt = {
val o = Wire(new DummySInt(w))
o.bits := 0.U
o
}
}
// The Arithmetic typeclass which implements various arithmetic operations on custom datatypes
abstract class Arithmetic[T <: Data] {
implicit def cast(t: T): ArithmeticOps[T]
}
abstract class ArithmeticOps[T <: Data](self: T) {
def *(t: T): T
def mac(m1: T, m2: T): T // Returns (m1 * m2 + self)
def +(t: T): T
def -(t: T): T
def >>(u: UInt): T // This is a rounding shift! Rounds away from 0
def >(t: T): Bool
def identity: T
def withWidthOf(t: T): T
def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates
def relu: T
def zero: T
def minimum: T
// Optional parameters, which only need to be defined if you want to enable various optimizations for transformers
def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None
def mult_with_reciprocal[U <: Data](reciprocal: U) = self
}
object Arithmetic {
implicit object UIntArithmetic extends Arithmetic[UInt] {
override implicit def cast(self: UInt) = new ArithmeticOps(self) {
override def *(t: UInt) = self * t
override def mac(m1: UInt, m2: UInt) = m1 * m2 + self
override def +(t: UInt) = self + t
override def -(t: UInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = point_five & (zeros | ones_digit)
(self >> u).asUInt + r
}
override def >(t: UInt): Bool = self > t
override def withWidthOf(t: UInt) = self.asTypeOf(t)
override def clippedToWidthOf(t: UInt) = {
val sat = ((1 << (t.getWidth-1))-1).U
Mux(self > sat, sat, self)(t.getWidth-1, 0)
}
override def relu: UInt = self
override def zero: UInt = 0.U
override def identity: UInt = 1.U
override def minimum: UInt = 0.U
}
}
implicit object SIntArithmetic extends Arithmetic[SInt] {
override implicit def cast(self: SInt) = new ArithmeticOps(self) {
override def *(t: SInt) = self * t
override def mac(m1: SInt, m2: SInt) = m1 * m2 + self
override def +(t: SInt) = self + t
override def -(t: SInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = (point_five & (zeros | ones_digit)).asBool
(self >> u).asSInt + Mux(r, 1.S, 0.S)
}
override def >(t: SInt): Bool = self > t
override def withWidthOf(t: SInt) = {
if (self.getWidth >= t.getWidth)
self(t.getWidth-1, 0).asSInt
else {
val sign_bits = t.getWidth - self.getWidth
val sign = self(self.getWidth-1)
Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t)
}
}
override def clippedToWidthOf(t: SInt): SInt = {
val maxsat = ((1 << (t.getWidth-1))-1).S
val minsat = (-(1 << (t.getWidth-1))).S
MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt
}
override def relu: SInt = Mux(self >= 0.S, self, 0.S)
override def zero: SInt = 0.S
override def identity: SInt = 1.S
override def minimum: SInt = (-(1 << (self.getWidth-1))).S
override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(denom_t.cloneType))
val output = Wire(Decoupled(self.cloneType))
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def sin_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def uin_to_float(x: UInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := x
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = sin_to_float(self)
val denom_rec = uin_to_float(input.bits)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := self_rec
divider.io.b := denom_rec
divider.io.roundingMode := consts.round_minMag
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := float_to_in(divider.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(self.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
// Instantiate the hardloat sqrt
val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0))
input.ready := sqrter.io.inReady
sqrter.io.inValid := input.valid
sqrter.io.sqrtOp := true.B
sqrter.io.a := self_rec
sqrter.io.b := DontCare
sqrter.io.roundingMode := consts.round_minMag
sqrter.io.detectTininess := consts.tininess_afterRounding
output.valid := sqrter.io.outValid_sqrt
output.bits := float_to_in(sqrter.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match {
case Float(expWidth, sigWidth) =>
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(u.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
val self_rec = in_to_float(self)
val one_rec = in_to_float(1.S)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := one_rec
divider.io.b := self_rec
divider.io.roundingMode := consts.round_near_even
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u)
assert(!output.valid || output.ready)
Some((input, output))
case _ => None
}
override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match {
case recip @ Float(expWidth, sigWidth) =>
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits)
// Instantiate the hardloat divider
val muladder = Module(new MulRecFN(expWidth, sigWidth))
muladder.io.roundingMode := consts.round_near_even
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := reciprocal_rec
float_to_in(muladder.io.out)
case _ => self
}
}
}
implicit object FloatArithmetic extends Arithmetic[Float] {
// TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array
override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) {
override def *(t: Float): Float = {
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := t_rec_resized
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def mac(m1: Float, m2: Float): Float = {
// Recode all operands
val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits)
val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize m1 to self's width
val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth))
m1_resizer.io.in := m1_rec
m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m1_resizer.io.detectTininess := consts.tininess_afterRounding
val m1_rec_resized = m1_resizer.io.out
// Resize m2 to self's width
val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth))
m2_resizer.io.in := m2_rec
m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m2_resizer.io.detectTininess := consts.tininess_afterRounding
val m2_rec_resized = m2_resizer.io.out
// Perform multiply-add
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := m1_rec_resized
muladder.io.b := m2_rec_resized
muladder.io.c := self_rec
// Convert result to standard format // TODO remove these intermediate recodings
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def +(t: Float): Float = {
require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Generate 1 as a float
val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := 1.U
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
val one_rec = in_to_rec_fn.io.out
// Resize t
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
// Perform addition
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := t_rec_resized
muladder.io.b := one_rec
muladder.io.c := self_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def -(t: Float): Float = {
val t_sgn = t.bits(t.getWidth-1)
val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t)
self + neg_t
}
override def >>(u: UInt): Float = {
// Recode self
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Get 2^(-u) as a recoded float
val shift_exp = Wire(UInt(self.expWidth.W))
shift_exp := self.bias.U - u
val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W))
val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn)
assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported")
// Multiply self and 2^(-u)
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := shift_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def >(t: Float): Bool = {
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize t to self's width
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth))
comparator.io.a := self_rec
comparator.io.b := t_rec_resized
comparator.io.signaling := false.B
comparator.io.gt
}
override def withWidthOf(t: Float): Float = {
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def clippedToWidthOf(t: Float): Float = {
// TODO check for overflow. Right now, we just assume that overflow doesn't happen
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def relu: Float = {
val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits)
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits)
result
}
override def zero: Float = 0.U.asTypeOf(self)
override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
}
}
implicit object DummySIntArithmetic extends Arithmetic[DummySInt] {
override implicit def cast(self: DummySInt) = new ArithmeticOps(self) {
override def *(t: DummySInt) = self.dontCare
override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare
override def +(t: DummySInt) = self.dontCare
override def -(t: DummySInt) = self.dontCare
override def >>(t: UInt) = self.dontCare
override def >(t: DummySInt): Bool = false.B
override def identity = self.dontCare
override def withWidthOf(t: DummySInt) = self.dontCare
override def clippedToWidthOf(t: DummySInt) = self.dontCare
override def relu = self.dontCare
override def zero = self.dontCare
override def minimum: DummySInt = self.dontCare
}
}
}
| module PE_360( // @[PE.scala:31:7]
input clock, // @[PE.scala:31:7]
input reset, // @[PE.scala:31:7]
input [7:0] io_in_a, // @[PE.scala:35:14]
input [19:0] io_in_b, // @[PE.scala:35:14]
input [19:0] io_in_d, // @[PE.scala:35:14]
output [7:0] io_out_a, // @[PE.scala:35:14]
output [19:0] io_out_b, // @[PE.scala:35:14]
output [19:0] io_out_c, // @[PE.scala:35:14]
input io_in_control_dataflow, // @[PE.scala:35:14]
input io_in_control_propagate, // @[PE.scala:35:14]
input [4:0] io_in_control_shift, // @[PE.scala:35:14]
output io_out_control_dataflow, // @[PE.scala:35:14]
output io_out_control_propagate, // @[PE.scala:35:14]
output [4:0] io_out_control_shift, // @[PE.scala:35:14]
input [2:0] io_in_id, // @[PE.scala:35:14]
output [2:0] io_out_id, // @[PE.scala:35:14]
input io_in_last, // @[PE.scala:35:14]
output io_out_last, // @[PE.scala:35:14]
input io_in_valid, // @[PE.scala:35:14]
output io_out_valid, // @[PE.scala:35:14]
output io_bad_dataflow // @[PE.scala:35:14]
);
wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24]
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7]
wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7]
wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7]
wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7]
wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7]
wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7]
wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7]
wire io_in_last_0 = io_in_last; // @[PE.scala:31:7]
wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7]
wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7]
wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7]
wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37]
wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37]
wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35]
wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7]
wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7]
wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7]
wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7]
wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7]
wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7]
wire [19:0] io_out_b_0; // @[PE.scala:31:7]
wire [19:0] io_out_c_0; // @[PE.scala:31:7]
reg [31:0] c1; // @[PE.scala:70:15]
wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15]
wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38]
reg [31:0] c2; // @[PE.scala:71:15]
wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15]
wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38]
reg last_s; // @[PE.scala:89:25]
wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21]
wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25]
wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25]
wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32]
wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32]
wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25]
wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15]
wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}]
wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25]
wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27]
wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27]
wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25]
wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15]
wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15]
assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37]
wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37]
wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61]
wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15]
wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}]
wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15]
wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15]
assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37]
wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37]
wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61]
wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38]
wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38]
wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38]
wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38]
assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16]
assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101]
wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35]
wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35]
wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10]
wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10]
always @(posedge clock) begin // @[PE.scala:31:7]
if (io_in_valid_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10]
c1 <= _GEN_7; // @[PE.scala:70:15, :124:10]
if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30]
end
else // @[PE.scala:71:15, :118:101, :119:30]
c2 <= _GEN_7; // @[PE.scala:71:15, :124:10]
end
else begin // @[PE.scala:31:7]
c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10]
c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10]
end
last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25]
end
always @(posedge)
MacUnit_104 mac_unit ( // @[PE.scala:64:24]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0), // @[PE.scala:31:7]
.io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}]
.io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24]
.io_out_d (_mac_unit_io_out_d)
); // @[PE.scala:64:24]
assign io_out_a = io_out_a_0; // @[PE.scala:31:7]
assign io_out_b = io_out_b_0; // @[PE.scala:31:7]
assign io_out_c = io_out_c_0; // @[PE.scala:31:7]
assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7]
assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7]
assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7]
assign io_out_id = io_out_id_0; // @[PE.scala:31:7]
assign io_out_last = io_out_last_0; // @[PE.scala:31:7]
assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7]
assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Bundles.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import freechips.rocketchip.util._
import scala.collection.immutable.ListMap
import chisel3.util.Decoupled
import chisel3.util.DecoupledIO
import chisel3.reflect.DataMirror
abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle
// common combos in lazy policy:
// Put + Acquire
// Release + AccessAck
object TLMessages
{
// A B C D E
def PutFullData = 0.U // . . => AccessAck
def PutPartialData = 1.U // . . => AccessAck
def ArithmeticData = 2.U // . . => AccessAckData
def LogicalData = 3.U // . . => AccessAckData
def Get = 4.U // . . => AccessAckData
def Hint = 5.U // . . => HintAck
def AcquireBlock = 6.U // . => Grant[Data]
def AcquirePerm = 7.U // . => Grant[Data]
def Probe = 6.U // . => ProbeAck[Data]
def AccessAck = 0.U // . .
def AccessAckData = 1.U // . .
def HintAck = 2.U // . .
def ProbeAck = 4.U // .
def ProbeAckData = 5.U // .
def Release = 6.U // . => ReleaseAck
def ReleaseData = 7.U // . => ReleaseAck
def Grant = 4.U // . => GrantAck
def GrantData = 5.U // . => GrantAck
def ReleaseAck = 6.U // .
def GrantAck = 0.U // .
def isA(x: UInt) = x <= AcquirePerm
def isB(x: UInt) = x <= Probe
def isC(x: UInt) = x <= ReleaseData
def isD(x: UInt) = x <= ReleaseAck
def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant)
def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck)
def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("AcquireBlock",TLPermissions.PermMsgGrow),
("AcquirePerm",TLPermissions.PermMsgGrow))
def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("Probe",TLPermissions.PermMsgCap))
def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("ProbeAck",TLPermissions.PermMsgReport),
("ProbeAckData",TLPermissions.PermMsgReport),
("Release",TLPermissions.PermMsgReport),
("ReleaseData",TLPermissions.PermMsgReport))
def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("Grant",TLPermissions.PermMsgCap),
("GrantData",TLPermissions.PermMsgCap),
("ReleaseAck",TLPermissions.PermMsgReserved))
}
/**
* The three primary TileLink permissions are:
* (T)runk: the agent is (or is on inwards path to) the global point of serialization.
* (B)ranch: the agent is on an outwards path to
* (N)one:
* These permissions are permuted by transfer operations in various ways.
* Operations can cap permissions, request for them to be grown or shrunk,
* or for a report on their current status.
*/
object TLPermissions
{
val aWidth = 2
val bdWidth = 2
val cWidth = 3
// Cap types (Grant = new permissions, Probe = permisions <= target)
def toT = 0.U(bdWidth.W)
def toB = 1.U(bdWidth.W)
def toN = 2.U(bdWidth.W)
def isCap(x: UInt) = x <= toN
// Grow types (Acquire = permissions >= target)
def NtoB = 0.U(aWidth.W)
def NtoT = 1.U(aWidth.W)
def BtoT = 2.U(aWidth.W)
def isGrow(x: UInt) = x <= BtoT
// Shrink types (ProbeAck, Release)
def TtoB = 0.U(cWidth.W)
def TtoN = 1.U(cWidth.W)
def BtoN = 2.U(cWidth.W)
def isShrink(x: UInt) = x <= BtoN
// Report types (ProbeAck, Release)
def TtoT = 3.U(cWidth.W)
def BtoB = 4.U(cWidth.W)
def NtoN = 5.U(cWidth.W)
def isReport(x: UInt) = x <= NtoN
def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT")
def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN")
def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN")
def PermMsgReserved:Seq[String] = Seq("Reserved")
}
object TLAtomics
{
val width = 3
// Arithmetic types
def MIN = 0.U(width.W)
def MAX = 1.U(width.W)
def MINU = 2.U(width.W)
def MAXU = 3.U(width.W)
def ADD = 4.U(width.W)
def isArithmetic(x: UInt) = x <= ADD
// Logical types
def XOR = 0.U(width.W)
def OR = 1.U(width.W)
def AND = 2.U(width.W)
def SWAP = 3.U(width.W)
def isLogical(x: UInt) = x <= SWAP
def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD")
def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP")
}
object TLHints
{
val width = 1
def PREFETCH_READ = 0.U(width.W)
def PREFETCH_WRITE = 1.U(width.W)
def isHints(x: UInt) = x <= PREFETCH_WRITE
def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite")
}
sealed trait TLChannel extends TLBundleBase {
val channelName: String
}
sealed trait TLDataChannel extends TLChannel
sealed trait TLAddrChannel extends TLDataChannel
final class TLBundleA(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleA_${params.shortName}"
val channelName = "'A' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleB(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleB_${params.shortName}"
val channelName = "'B' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val address = UInt(params.addressBits.W) // from
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleC(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleC_${params.shortName}"
val channelName = "'C' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.cWidth.W) // shrink or report perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleD(params: TLBundleParameters)
extends TLBundleBase(params) with TLDataChannel
{
override def typeName = s"TLBundleD_${params.shortName}"
val channelName = "'D' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val sink = UInt(params.sinkBits.W) // from
val denied = Bool() // implies corrupt iff *Data
val user = BundleMap(params.responseFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleE(params: TLBundleParameters)
extends TLBundleBase(params) with TLChannel
{
override def typeName = s"TLBundleE_${params.shortName}"
val channelName = "'E' channel"
val sink = UInt(params.sinkBits.W) // to
}
class TLBundle(val params: TLBundleParameters) extends Record
{
// Emulate a Bundle with elements abcde or ad depending on params.hasBCE
private val optA = Some (Decoupled(new TLBundleA(params)))
private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params))))
private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params)))
private val optD = Some (Flipped(Decoupled(new TLBundleD(params))))
private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params)))
def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params)))))
def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params)))))
def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params)))))
def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params)))))
def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params)))))
val elements =
if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a)
else ListMap("d" -> d, "a" -> a)
def tieoff(): Unit = {
DataMirror.specifiedDirectionOf(a.ready) match {
case SpecifiedDirection.Input =>
a.ready := false.B
c.ready := false.B
e.ready := false.B
b.valid := false.B
d.valid := false.B
case SpecifiedDirection.Output =>
a.valid := false.B
c.valid := false.B
e.valid := false.B
b.ready := false.B
d.ready := false.B
case _ =>
}
}
}
object TLBundle
{
def apply(params: TLBundleParameters) = new TLBundle(params)
}
class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle
class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params)
{
val a = new AsyncBundle(new TLBundleA(params.base), params.async)
val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async))
val c = new AsyncBundle(new TLBundleC(params.base), params.async)
val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async))
val e = new AsyncBundle(new TLBundleE(params.base), params.async)
}
class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = RationalIO(new TLBundleA(params))
val b = Flipped(RationalIO(new TLBundleB(params)))
val c = RationalIO(new TLBundleC(params))
val d = Flipped(RationalIO(new TLBundleD(params)))
val e = RationalIO(new TLBundleE(params))
}
class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = CreditedIO(new TLBundleA(params))
val b = Flipped(CreditedIO(new TLBundleB(params)))
val c = CreditedIO(new TLBundleC(params))
val d = Flipped(CreditedIO(new TLBundleD(params)))
val e = CreditedIO(new TLBundleE(params))
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor_5( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59]
wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27]
wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25]
wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_37 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_43 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_45 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_49 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_55 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_57 = 1'h1; // @[Parameters.scala:57:20]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28]
wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54]
wire [1026:0] _c_sizes_set_T_1 = 1027'h0; // @[Monitor.scala:768:52]
wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79]
wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51]
wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35]
wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35]
wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34]
wire [259:0] c_sizes_set = 260'h0; // @[Monitor.scala:741:34]
wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34]
wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34]
wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46]
wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76]
wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire _source_ok_T_25 = io_in_a_bits_source_0 == 7'h21; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31]
wire _source_ok_T_26 = io_in_a_bits_source_0 == 7'h20; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31]
wire _source_ok_T_27 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_7 = _source_ok_T_27; // @[Parameters.scala:1138:31]
wire _source_ok_T_28 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_29 = _source_ok_T_28 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_30 = _source_ok_T_29 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_31 = _source_ok_T_30 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_32 = _source_ok_T_31 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_33 = _source_ok_T_32 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_33 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46]
wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [28:0] _is_aligned_T = {23'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_34 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_34; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_35 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_41 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_47 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_53 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_36 = _source_ok_T_35 == 5'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_38 = _source_ok_T_36; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_40; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_42 = _source_ok_T_41 == 5'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_44 = _source_ok_T_42; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_46 = _source_ok_T_44; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_46; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_48 = _source_ok_T_47 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_50 = _source_ok_T_48; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_52; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_54 = _source_ok_T_53 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_56 = _source_ok_T_54; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_58 = _source_ok_T_56; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_58; // @[Parameters.scala:1138:31]
wire _source_ok_T_59 = io_in_d_bits_source_0 == 7'h21; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_5 = _source_ok_T_59; // @[Parameters.scala:1138:31]
wire _source_ok_T_60 = io_in_d_bits_source_0 == 7'h20; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_6 = _source_ok_T_60; // @[Parameters.scala:1138:31]
wire _source_ok_T_61 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_7 = _source_ok_T_61; // @[Parameters.scala:1138:31]
wire _source_ok_T_62 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_63 = _source_ok_T_62 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_64 = _source_ok_T_63 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_65 = _source_ok_T_64 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_66 = _source_ok_T_65 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_67 = _source_ok_T_66 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_67 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46]
wire _T_1042 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1042; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1042; // @[Decoupled.scala:51:35]
wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [6:0] source; // @[Monitor.scala:390:22]
reg [28:0] address; // @[Monitor.scala:391:22]
wire _T_1115 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1115; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1115; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1115; // @[Decoupled.scala:51:35]
wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [6:0] source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [64:0] inflight; // @[Monitor.scala:614:27]
reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [259:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [64:0] a_set; // @[Monitor.scala:626:34]
wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [259:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [259:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [259:0] _a_size_lookup_T_6 = {256'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [259:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[259:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [127:0] _GEN_2 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [127:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_968 = _T_1042 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_968 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_968 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_968 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [9:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_968 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_968 ? _a_sizes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [64:0] d_clr; // @[Monitor.scala:664:34]
wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [259:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_1014 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1014 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_983 = _T_1115 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_983 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_983 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_983 ? _d_sizes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [64:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [259:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [259:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [259:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [259:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [64:0] inflight_1; // @[Monitor.scala:726:35]
wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [259:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [259:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [259:0] _c_size_lookup_T_6 = {256'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [259:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[259:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [64:0] d_clr_1; // @[Monitor.scala:774:34]
wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [259:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1086 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1086 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1068 = _T_1115 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1068 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1068 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1068 ? _d_sizes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113]
wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [259:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [259:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to the following Chisel files.
File RoundAnyRawFNToRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util.Fill
import consts._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class
RoundAnyRawFNToRecFN(
inExpWidth: Int,
inSigWidth: Int,
outExpWidth: Int,
outSigWidth: Int,
options: Int
)
extends RawModule
{
override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}"
val io = IO(new Bundle {
val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'
val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'
val in = Input(new RawFloat(inExpWidth, inSigWidth))
// (allowed exponent range has limits)
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((outExpWidth + outSigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0)
val effectiveInSigWidth =
if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1
val neverUnderflows =
((options &
(flRoundOpt_neverUnderflows | flRoundOpt_subnormsAlwaysExact)
) != 0) ||
(inExpWidth < outExpWidth)
val neverOverflows =
((options & flRoundOpt_neverOverflows) != 0) ||
(inExpWidth < outExpWidth)
val outNaNExp = BigInt(7)<<(outExpWidth - 2)
val outInfExp = BigInt(6)<<(outExpWidth - 2)
val outMaxFiniteExp = outInfExp - 1
val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2
val outMinNonzeroExp = outMinNormExp - outSigWidth + 1
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundingMode_near_even = (io.roundingMode === round_near_even)
val roundingMode_minMag = (io.roundingMode === round_minMag)
val roundingMode_min = (io.roundingMode === round_min)
val roundingMode_max = (io.roundingMode === round_max)
val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag)
val roundingMode_odd = (io.roundingMode === round_odd)
val roundMagUp =
(roundingMode_min && io.in.sign) || (roundingMode_max && ! io.in.sign)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sAdjustedExp =
if (inExpWidth < outExpWidth)
(io.in.sExp +&
((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S
)(outExpWidth, 0).zext
else if (inExpWidth == outExpWidth)
io.in.sExp
else
io.in.sExp +&
((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S
val adjustedSig =
if (inSigWidth <= outSigWidth + 2)
io.in.sig<<(outSigWidth - inSigWidth + 2)
else
(io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ##
io.in.sig(inSigWidth - outSigWidth - 2, 0).orR
)
val doShiftSigDown1 =
if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2)
val common_expOut = Wire(UInt((outExpWidth + 1).W))
val common_fractOut = Wire(UInt((outSigWidth - 1).W))
val common_overflow = Wire(Bool())
val common_totalUnderflow = Wire(Bool())
val common_underflow = Wire(Bool())
val common_inexact = Wire(Bool())
if (
neverOverflows && neverUnderflows
&& (effectiveInSigWidth <= outSigWidth)
) {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1
common_fractOut :=
Mux(doShiftSigDown1,
adjustedSig(outSigWidth + 1, 3),
adjustedSig(outSigWidth, 2)
)
common_overflow := false.B
common_totalUnderflow := false.B
common_underflow := false.B
common_inexact := false.B
} else {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
val roundMask =
if (neverUnderflows)
0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W)
else
(lowMask(
sAdjustedExp(outExpWidth, 0),
outMinNormExp - outSigWidth - 1,
outMinNormExp
) | doShiftSigDown1) ##
3.U(2.W)
val shiftedRoundMask = 0.U(1.W) ## roundMask>>1
val roundPosMask = ~shiftedRoundMask & roundMask
val roundPosBit = (adjustedSig & roundPosMask).orR
val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR
val anyRound = roundPosBit || anyRoundExtra
val roundIncr =
((roundingMode_near_even || roundingMode_near_maxMag) &&
roundPosBit) ||
(roundMagUp && anyRound)
val roundedSig: Bits =
Mux(roundIncr,
(((adjustedSig | roundMask)>>2) +& 1.U) &
~Mux(roundingMode_near_even && roundPosBit &&
! anyRoundExtra,
roundMask>>1,
0.U((outSigWidth + 2).W)
),
(adjustedSig & ~roundMask)>>2 |
Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U)
)
//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING
//*** M.S. BIT OF SUBNORMAL SIG?
val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext
common_expOut := sRoundedExp(outExpWidth, 0)
common_fractOut :=
Mux(doShiftSigDown1,
roundedSig(outSigWidth - 1, 1),
roundedSig(outSigWidth - 2, 0)
)
common_overflow :=
(if (neverOverflows) false.B else
//*** REWRITE BASED ON BEFORE-ROUNDING EXPONENT?:
(sRoundedExp>>(outExpWidth - 1) >= 3.S))
common_totalUnderflow :=
(if (neverUnderflows) false.B else
//*** WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?:
(sRoundedExp < outMinNonzeroExp.S))
val unboundedRange_roundPosBit =
Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1))
val unboundedRange_anyRound =
(doShiftSigDown1 && adjustedSig(2)) || adjustedSig(1, 0).orR
val unboundedRange_roundIncr =
((roundingMode_near_even || roundingMode_near_maxMag) &&
unboundedRange_roundPosBit) ||
(roundMagUp && unboundedRange_anyRound)
val roundCarry =
Mux(doShiftSigDown1,
roundedSig(outSigWidth + 1),
roundedSig(outSigWidth)
)
common_underflow :=
(if (neverUnderflows) false.B else
common_totalUnderflow ||
//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING
//*** M.S. BIT OF SUBNORMAL SIG?
(anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) &&
Mux(doShiftSigDown1, roundMask(3), roundMask(2)) &&
! ((io.detectTininess === tininess_afterRounding) &&
! Mux(doShiftSigDown1,
roundMask(4),
roundMask(3)
) &&
roundCarry && roundPosBit &&
unboundedRange_roundIncr)))
common_inexact := common_totalUnderflow || anyRound
}
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val isNaNOut = io.invalidExc || io.in.isNaN
val notNaN_isSpecialInfOut = io.infiniteExc || io.in.isInf
val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero
val overflow = commonCase && common_overflow
val underflow = commonCase && common_underflow
val inexact = overflow || (commonCase && common_inexact)
val overflow_roundMagUp =
roundingMode_near_even || roundingMode_near_maxMag || roundMagUp
val pegMinNonzeroMagOut =
commonCase && common_totalUnderflow && (roundMagUp || roundingMode_odd)
val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp
val notNaN_isInfOut =
notNaN_isSpecialInfOut || (overflow && overflow_roundMagUp)
val signOut = Mux(isNaNOut, false.B, io.in.sign)
val expOut =
(common_expOut &
~Mux(io.in.isZero || common_totalUnderflow,
(BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W),
0.U
) &
~Mux(pegMinNonzeroMagOut,
~outMinNonzeroExp.U((outExpWidth + 1).W),
0.U
) &
~Mux(pegMaxFiniteMagOut,
(BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W),
0.U
) &
~Mux(notNaN_isInfOut,
(BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W),
0.U
)) |
Mux(pegMinNonzeroMagOut,
outMinNonzeroExp.U((outExpWidth + 1).W),
0.U
) |
Mux(pegMaxFiniteMagOut,
outMaxFiniteExp.U((outExpWidth + 1).W),
0.U
) |
Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) |
Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U)
val fractOut =
Mux(isNaNOut || io.in.isZero || common_totalUnderflow,
Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U),
common_fractOut
) |
Fill(outSigWidth - 1, pegMaxFiniteMagOut)
io.out := signOut ## expOut ## fractOut
io.exceptionFlags :=
io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class
RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int)
extends RawModule
{
override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'
val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'
val in = Input(new RawFloat(expWidth, sigWidth + 2))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
val roundAnyRawFNToRecFN =
Module(
new RoundAnyRawFNToRecFN(
expWidth, sigWidth + 2, expWidth, sigWidth, options))
roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc
roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc
roundAnyRawFNToRecFN.io.in := io.in
roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode
roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundAnyRawFNToRecFN.io.out
io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags
}
| module RoundRawFNToRecFN_e8_s24_133( // @[RoundAnyRawFNToRecFN.scala:295:5]
input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:299:16]
input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:299:16]
input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:299:16]
output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:299:16]
output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:299:16]
);
wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15]
wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15]
wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15]
wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_133 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala:310:15]
.io_invalidExc (io_invalidExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_isNaN (io_in_isNaN_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_isInf (io_in_isInf_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_isZero (io_in_isZero_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_sign (io_in_sign_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_sExp (io_in_sExp_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_sig (io_in_sig_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_out (io_out_0),
.io_exceptionFlags (io_exceptionFlags_0)
); // @[RoundAnyRawFNToRecFN.scala:310:15]
assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftRegisterPriorityQueue.scala:
package compressacc
import chisel3._
import chisel3.util._
import chisel3.util._
// TODO : support enq & deq at the same cycle
class PriorityQueueStageIO(keyWidth: Int, value: ValueInfo) extends Bundle {
val output_prev = KeyValue(keyWidth, value)
val output_nxt = KeyValue(keyWidth, value)
val input_prev = Flipped(KeyValue(keyWidth, value))
val input_nxt = Flipped(KeyValue(keyWidth, value))
val cmd = Flipped(Valid(UInt(1.W)))
val insert_here = Input(Bool())
val cur_input_keyval = Flipped(KeyValue(keyWidth, value))
val cur_output_keyval = KeyValue(keyWidth, value)
}
class PriorityQueueStage(keyWidth: Int, value: ValueInfo) extends Module {
val io = IO(new PriorityQueueStageIO(keyWidth, value))
dontTouch(io)
val CMD_DEQ = 0.U
val CMD_ENQ = 1.U
val MAX_VALUE = (1 << keyWidth) - 1
val key_reg = RegInit(MAX_VALUE.U(keyWidth.W))
val value_reg = Reg(value)
io.output_prev.key := key_reg
io.output_prev.value := value_reg
io.output_nxt.key := key_reg
io.output_nxt.value := value_reg
io.cur_output_keyval.key := key_reg
io.cur_output_keyval.value := value_reg
when (io.cmd.valid) {
switch (io.cmd.bits) {
is (CMD_DEQ) {
key_reg := io.input_nxt.key
value_reg := io.input_nxt.value
}
is (CMD_ENQ) {
when (io.insert_here) {
key_reg := io.cur_input_keyval.key
value_reg := io.cur_input_keyval.value
} .elsewhen (key_reg >= io.cur_input_keyval.key) {
key_reg := io.input_prev.key
value_reg := io.input_prev.value
} .otherwise {
// do nothing
}
}
}
}
}
object PriorityQueueStage {
def apply(keyWidth: Int, v: ValueInfo): PriorityQueueStage = new PriorityQueueStage(keyWidth, v)
}
// TODO
// - This design is not scalable as the enqued_keyval is broadcasted to all the stages
// - Add pipeline registers later
class PriorityQueueIO(queSize: Int, keyWidth: Int, value: ValueInfo) extends Bundle {
val cnt_bits = log2Ceil(queSize+1)
val counter = Output(UInt(cnt_bits.W))
val enq = Flipped(Decoupled(KeyValue(keyWidth, value)))
val deq = Decoupled(KeyValue(keyWidth, value))
}
class PriorityQueue(queSize: Int, keyWidth: Int, value: ValueInfo) extends Module {
val keyWidthInternal = keyWidth + 1
val CMD_DEQ = 0.U
val CMD_ENQ = 1.U
val io = IO(new PriorityQueueIO(queSize, keyWidthInternal, value))
dontTouch(io)
val MAX_VALUE = ((1 << keyWidthInternal) - 1).U
val cnt_bits = log2Ceil(queSize+1)
// do not consider cases where we are inserting more entries then the queSize
val counter = RegInit(0.U(cnt_bits.W))
io.counter := counter
val full = (counter === queSize.U)
val empty = (counter === 0.U)
io.deq.valid := !empty
io.enq.ready := !full
when (io.enq.fire) {
counter := counter + 1.U
}
when (io.deq.fire) {
counter := counter - 1.U
}
val cmd_valid = io.enq.valid || io.deq.ready
val cmd = Mux(io.enq.valid, CMD_ENQ, CMD_DEQ)
assert(!(io.enq.valid && io.deq.ready))
val stages = Seq.fill(queSize)(Module(new PriorityQueueStage(keyWidthInternal, value)))
for (i <- 0 until (queSize - 1)) {
stages(i+1).io.input_prev <> stages(i).io.output_nxt
stages(i).io.input_nxt <> stages(i+1).io.output_prev
}
stages(queSize-1).io.input_nxt.key := MAX_VALUE
// stages(queSize-1).io.input_nxt.value :=
stages(queSize-1).io.input_nxt.value.symbol := 0.U
// stages(queSize-1).io.input_nxt.value.child(0) := 0.U
// stages(queSize-1).io.input_nxt.value.child(1) := 0.U
stages(0).io.input_prev.key := io.enq.bits.key
stages(0).io.input_prev.value <> io.enq.bits.value
for (i <- 0 until queSize) {
stages(i).io.cmd.valid := cmd_valid
stages(i).io.cmd.bits := cmd
stages(i).io.cur_input_keyval <> io.enq.bits
}
val is_large_or_equal = WireInit(VecInit(Seq.fill(queSize)(false.B)))
for (i <- 0 until queSize) {
is_large_or_equal(i) := (stages(i).io.cur_output_keyval.key >= io.enq.bits.key)
}
val is_large_or_equal_cat = Wire(UInt(queSize.W))
is_large_or_equal_cat := Cat(is_large_or_equal.reverse)
val insert_here_idx = PriorityEncoder(is_large_or_equal_cat)
for (i <- 0 until queSize) {
when (i.U === insert_here_idx) {
stages(i).io.insert_here := true.B
} .otherwise {
stages(i).io.insert_here := false.B
}
}
io.deq.bits <> stages(0).io.output_prev
}
| module PriorityQueueStage_210( // @[ShiftRegisterPriorityQueue.scala:21:7]
input clock, // @[ShiftRegisterPriorityQueue.scala:21:7]
input reset, // @[ShiftRegisterPriorityQueue.scala:21:7]
output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14]
);
wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24]
assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22]
assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30]
always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24]
else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30]
key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
end
else // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
end
if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7]
value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30]
value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
end
else // @[ShiftRegisterPriorityQueue.scala:21:7]
value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
end
always @(posedge)
assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File RoundAnyRawFNToRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util.Fill
import consts._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class
RoundAnyRawFNToRecFN(
inExpWidth: Int,
inSigWidth: Int,
outExpWidth: Int,
outSigWidth: Int,
options: Int
)
extends RawModule
{
override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}"
val io = IO(new Bundle {
val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'
val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'
val in = Input(new RawFloat(inExpWidth, inSigWidth))
// (allowed exponent range has limits)
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((outExpWidth + outSigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0)
val effectiveInSigWidth =
if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1
val neverUnderflows =
((options &
(flRoundOpt_neverUnderflows | flRoundOpt_subnormsAlwaysExact)
) != 0) ||
(inExpWidth < outExpWidth)
val neverOverflows =
((options & flRoundOpt_neverOverflows) != 0) ||
(inExpWidth < outExpWidth)
val outNaNExp = BigInt(7)<<(outExpWidth - 2)
val outInfExp = BigInt(6)<<(outExpWidth - 2)
val outMaxFiniteExp = outInfExp - 1
val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2
val outMinNonzeroExp = outMinNormExp - outSigWidth + 1
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundingMode_near_even = (io.roundingMode === round_near_even)
val roundingMode_minMag = (io.roundingMode === round_minMag)
val roundingMode_min = (io.roundingMode === round_min)
val roundingMode_max = (io.roundingMode === round_max)
val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag)
val roundingMode_odd = (io.roundingMode === round_odd)
val roundMagUp =
(roundingMode_min && io.in.sign) || (roundingMode_max && ! io.in.sign)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sAdjustedExp =
if (inExpWidth < outExpWidth)
(io.in.sExp +&
((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S
)(outExpWidth, 0).zext
else if (inExpWidth == outExpWidth)
io.in.sExp
else
io.in.sExp +&
((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S
val adjustedSig =
if (inSigWidth <= outSigWidth + 2)
io.in.sig<<(outSigWidth - inSigWidth + 2)
else
(io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ##
io.in.sig(inSigWidth - outSigWidth - 2, 0).orR
)
val doShiftSigDown1 =
if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2)
val common_expOut = Wire(UInt((outExpWidth + 1).W))
val common_fractOut = Wire(UInt((outSigWidth - 1).W))
val common_overflow = Wire(Bool())
val common_totalUnderflow = Wire(Bool())
val common_underflow = Wire(Bool())
val common_inexact = Wire(Bool())
if (
neverOverflows && neverUnderflows
&& (effectiveInSigWidth <= outSigWidth)
) {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1
common_fractOut :=
Mux(doShiftSigDown1,
adjustedSig(outSigWidth + 1, 3),
adjustedSig(outSigWidth, 2)
)
common_overflow := false.B
common_totalUnderflow := false.B
common_underflow := false.B
common_inexact := false.B
} else {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
val roundMask =
if (neverUnderflows)
0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W)
else
(lowMask(
sAdjustedExp(outExpWidth, 0),
outMinNormExp - outSigWidth - 1,
outMinNormExp
) | doShiftSigDown1) ##
3.U(2.W)
val shiftedRoundMask = 0.U(1.W) ## roundMask>>1
val roundPosMask = ~shiftedRoundMask & roundMask
val roundPosBit = (adjustedSig & roundPosMask).orR
val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR
val anyRound = roundPosBit || anyRoundExtra
val roundIncr =
((roundingMode_near_even || roundingMode_near_maxMag) &&
roundPosBit) ||
(roundMagUp && anyRound)
val roundedSig: Bits =
Mux(roundIncr,
(((adjustedSig | roundMask)>>2) +& 1.U) &
~Mux(roundingMode_near_even && roundPosBit &&
! anyRoundExtra,
roundMask>>1,
0.U((outSigWidth + 2).W)
),
(adjustedSig & ~roundMask)>>2 |
Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U)
)
//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING
//*** M.S. BIT OF SUBNORMAL SIG?
val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext
common_expOut := sRoundedExp(outExpWidth, 0)
common_fractOut :=
Mux(doShiftSigDown1,
roundedSig(outSigWidth - 1, 1),
roundedSig(outSigWidth - 2, 0)
)
common_overflow :=
(if (neverOverflows) false.B else
//*** REWRITE BASED ON BEFORE-ROUNDING EXPONENT?:
(sRoundedExp>>(outExpWidth - 1) >= 3.S))
common_totalUnderflow :=
(if (neverUnderflows) false.B else
//*** WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?:
(sRoundedExp < outMinNonzeroExp.S))
val unboundedRange_roundPosBit =
Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1))
val unboundedRange_anyRound =
(doShiftSigDown1 && adjustedSig(2)) || adjustedSig(1, 0).orR
val unboundedRange_roundIncr =
((roundingMode_near_even || roundingMode_near_maxMag) &&
unboundedRange_roundPosBit) ||
(roundMagUp && unboundedRange_anyRound)
val roundCarry =
Mux(doShiftSigDown1,
roundedSig(outSigWidth + 1),
roundedSig(outSigWidth)
)
common_underflow :=
(if (neverUnderflows) false.B else
common_totalUnderflow ||
//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING
//*** M.S. BIT OF SUBNORMAL SIG?
(anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) &&
Mux(doShiftSigDown1, roundMask(3), roundMask(2)) &&
! ((io.detectTininess === tininess_afterRounding) &&
! Mux(doShiftSigDown1,
roundMask(4),
roundMask(3)
) &&
roundCarry && roundPosBit &&
unboundedRange_roundIncr)))
common_inexact := common_totalUnderflow || anyRound
}
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val isNaNOut = io.invalidExc || io.in.isNaN
val notNaN_isSpecialInfOut = io.infiniteExc || io.in.isInf
val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero
val overflow = commonCase && common_overflow
val underflow = commonCase && common_underflow
val inexact = overflow || (commonCase && common_inexact)
val overflow_roundMagUp =
roundingMode_near_even || roundingMode_near_maxMag || roundMagUp
val pegMinNonzeroMagOut =
commonCase && common_totalUnderflow && (roundMagUp || roundingMode_odd)
val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp
val notNaN_isInfOut =
notNaN_isSpecialInfOut || (overflow && overflow_roundMagUp)
val signOut = Mux(isNaNOut, false.B, io.in.sign)
val expOut =
(common_expOut &
~Mux(io.in.isZero || common_totalUnderflow,
(BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W),
0.U
) &
~Mux(pegMinNonzeroMagOut,
~outMinNonzeroExp.U((outExpWidth + 1).W),
0.U
) &
~Mux(pegMaxFiniteMagOut,
(BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W),
0.U
) &
~Mux(notNaN_isInfOut,
(BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W),
0.U
)) |
Mux(pegMinNonzeroMagOut,
outMinNonzeroExp.U((outExpWidth + 1).W),
0.U
) |
Mux(pegMaxFiniteMagOut,
outMaxFiniteExp.U((outExpWidth + 1).W),
0.U
) |
Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) |
Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U)
val fractOut =
Mux(isNaNOut || io.in.isZero || common_totalUnderflow,
Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U),
common_fractOut
) |
Fill(outSigWidth - 1, pegMaxFiniteMagOut)
io.out := signOut ## expOut ## fractOut
io.exceptionFlags :=
io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class
RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int)
extends RawModule
{
override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'
val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'
val in = Input(new RawFloat(expWidth, sigWidth + 2))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
val roundAnyRawFNToRecFN =
Module(
new RoundAnyRawFNToRecFN(
expWidth, sigWidth + 2, expWidth, sigWidth, options))
roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc
roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc
roundAnyRawFNToRecFN.io.in := io.in
roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode
roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundAnyRawFNToRecFN.io.out
io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags
}
| module RoundRawFNToRecFN_e8_s24_127( // @[RoundAnyRawFNToRecFN.scala:295:5]
input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:299:16]
input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:299:16]
input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:299:16]
output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:299:16]
output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:299:16]
);
wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15]
wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15]
wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15]
wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_127 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala:310:15]
.io_invalidExc (io_invalidExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_isNaN (io_in_isNaN_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_isInf (io_in_isInf_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_isZero (io_in_isZero_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_sign (io_in_sign_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_sExp (io_in_sExp_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_sig (io_in_sig_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_out (io_out_0),
.io_exceptionFlags (io_exceptionFlags_0)
); // @[RoundAnyRawFNToRecFN.scala:310:15]
assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File RecFNToRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import consts._
class
RecFNToRecFN(
inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int)
extends chisel3.RawModule
{
val io = IO(new Bundle {
val in = Input(Bits((inExpWidth + inSigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((outExpWidth + outSigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val rawIn = rawFloatFromRecFN(inExpWidth, inSigWidth, io.in);
if ((inExpWidth == outExpWidth) && (inSigWidth <= outSigWidth)) {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
io.out := io.in<<(outSigWidth - inSigWidth)
io.exceptionFlags := isSigNaNRawFloat(rawIn) ## 0.U(4.W)
} else {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
val roundAnyRawFNToRecFN =
Module(
new RoundAnyRawFNToRecFN(
inExpWidth,
inSigWidth,
outExpWidth,
outSigWidth,
flRoundOpt_sigMSBitAlwaysZero
))
roundAnyRawFNToRecFN.io.invalidExc := isSigNaNRawFloat(rawIn)
roundAnyRawFNToRecFN.io.infiniteExc := false.B
roundAnyRawFNToRecFN.io.in := rawIn
roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode
roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundAnyRawFNToRecFN.io.out
io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags
}
}
File rawFloatFromRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
/*----------------------------------------------------------------------------
| In the result, no more than one of 'isNaN', 'isInf', and 'isZero' will be
| set.
*----------------------------------------------------------------------------*/
object rawFloatFromRecFN
{
def apply(expWidth: Int, sigWidth: Int, in: Bits): RawFloat =
{
val exp = in(expWidth + sigWidth - 1, sigWidth - 1)
val isZero = exp(expWidth, expWidth - 2) === 0.U
val isSpecial = exp(expWidth, expWidth - 1) === 3.U
val out = Wire(new RawFloat(expWidth, sigWidth))
out.isNaN := isSpecial && exp(expWidth - 2)
out.isInf := isSpecial && ! exp(expWidth - 2)
out.isZero := isZero
out.sign := in(expWidth + sigWidth)
out.sExp := exp.zext
out.sig := 0.U(1.W) ## ! isZero ## in(sigWidth - 2, 0)
out
}
}
| module RecFNToRecFN_176( // @[RecFNToRecFN.scala:44:5]
input [32:0] io_in, // @[RecFNToRecFN.scala:48:16]
output [32:0] io_out // @[RecFNToRecFN.scala:48:16]
);
wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5]
wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16]
wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16]
wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35]
wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54]
wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5]
wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5]
wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35]
wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}]
wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23]
assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46]
assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54]
assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File FPU.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tile
import chisel3._
import chisel3.util._
import chisel3.{DontCare, WireInit, withClock, withReset}
import chisel3.experimental.SourceInfo
import chisel3.experimental.dataview._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.rocket._
import freechips.rocketchip.rocket.Instructions._
import freechips.rocketchip.util._
import freechips.rocketchip.util.property
case class FPUParams(
minFLen: Int = 32,
fLen: Int = 64,
divSqrt: Boolean = true,
sfmaLatency: Int = 3,
dfmaLatency: Int = 4,
fpmuLatency: Int = 2,
ifpuLatency: Int = 2
)
object FPConstants
{
val RM_SZ = 3
val FLAGS_SZ = 5
}
trait HasFPUCtrlSigs {
val ldst = Bool()
val wen = Bool()
val ren1 = Bool()
val ren2 = Bool()
val ren3 = Bool()
val swap12 = Bool()
val swap23 = Bool()
val typeTagIn = UInt(2.W)
val typeTagOut = UInt(2.W)
val fromint = Bool()
val toint = Bool()
val fastpipe = Bool()
val fma = Bool()
val div = Bool()
val sqrt = Bool()
val wflags = Bool()
val vec = Bool()
}
class FPUCtrlSigs extends Bundle with HasFPUCtrlSigs
class FPUDecoder(implicit p: Parameters) extends FPUModule()(p) {
val io = IO(new Bundle {
val inst = Input(Bits(32.W))
val sigs = Output(new FPUCtrlSigs())
})
private val X2 = BitPat.dontCare(2)
val default = List(X,X,X,X,X,X,X,X2,X2,X,X,X,X,X,X,X,N)
val h: Array[(BitPat, List[BitPat])] =
Array(FLH -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),
FSH -> List(Y,N,N,Y,N,Y,X, I, H,N,Y,N,N,N,N,N,N),
FMV_H_X -> List(N,Y,N,N,N,X,X, H, I,Y,N,N,N,N,N,N,N),
FCVT_H_W -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),
FCVT_H_WU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),
FCVT_H_L -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),
FCVT_H_LU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),
FMV_X_H -> List(N,N,Y,N,N,N,X, I, H,N,Y,N,N,N,N,N,N),
FCLASS_H -> List(N,N,Y,N,N,N,X, H, H,N,Y,N,N,N,N,N,N),
FCVT_W_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),
FCVT_WU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),
FCVT_L_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),
FCVT_LU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),
FCVT_S_H -> List(N,Y,Y,N,N,N,X, H, S,N,N,Y,N,N,N,Y,N),
FCVT_H_S -> List(N,Y,Y,N,N,N,X, S, H,N,N,Y,N,N,N,Y,N),
FEQ_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),
FLT_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),
FLE_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),
FSGNJ_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),
FSGNJN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),
FSGNJX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),
FMIN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N),
FMAX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N),
FADD_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N),
FSUB_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N),
FMUL_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,Y,N,N,Y,N),
FMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),
FMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),
FNMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),
FNMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),
FDIV_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,N,Y,N,Y,N),
FSQRT_H -> List(N,Y,Y,N,N,N,X, H, H,N,N,N,N,N,Y,Y,N))
val f: Array[(BitPat, List[BitPat])] =
Array(FLW -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),
FSW -> List(Y,N,N,Y,N,Y,X, I, S,N,Y,N,N,N,N,N,N),
FMV_W_X -> List(N,Y,N,N,N,X,X, S, I,Y,N,N,N,N,N,N,N),
FCVT_S_W -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),
FCVT_S_WU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),
FCVT_S_L -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),
FCVT_S_LU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),
FMV_X_W -> List(N,N,Y,N,N,N,X, I, S,N,Y,N,N,N,N,N,N),
FCLASS_S -> List(N,N,Y,N,N,N,X, S, S,N,Y,N,N,N,N,N,N),
FCVT_W_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),
FCVT_WU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),
FCVT_L_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),
FCVT_LU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),
FEQ_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),
FLT_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),
FLE_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),
FSGNJ_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),
FSGNJN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),
FSGNJX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),
FMIN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N),
FMAX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N),
FADD_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N),
FSUB_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N),
FMUL_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,Y,N,N,Y,N),
FMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),
FMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),
FNMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),
FNMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),
FDIV_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,N,Y,N,Y,N),
FSQRT_S -> List(N,Y,Y,N,N,N,X, S, S,N,N,N,N,N,Y,Y,N))
val d: Array[(BitPat, List[BitPat])] =
Array(FLD -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),
FSD -> List(Y,N,N,Y,N,Y,X, I, D,N,Y,N,N,N,N,N,N),
FMV_D_X -> List(N,Y,N,N,N,X,X, D, I,Y,N,N,N,N,N,N,N),
FCVT_D_W -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),
FCVT_D_WU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),
FCVT_D_L -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),
FCVT_D_LU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),
FMV_X_D -> List(N,N,Y,N,N,N,X, I, D,N,Y,N,N,N,N,N,N),
FCLASS_D -> List(N,N,Y,N,N,N,X, D, D,N,Y,N,N,N,N,N,N),
FCVT_W_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),
FCVT_WU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),
FCVT_L_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),
FCVT_LU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),
FCVT_S_D -> List(N,Y,Y,N,N,N,X, D, S,N,N,Y,N,N,N,Y,N),
FCVT_D_S -> List(N,Y,Y,N,N,N,X, S, D,N,N,Y,N,N,N,Y,N),
FEQ_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),
FLT_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),
FLE_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),
FSGNJ_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),
FSGNJN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),
FSGNJX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),
FMIN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N),
FMAX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N),
FADD_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N),
FSUB_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N),
FMUL_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,Y,N,N,Y,N),
FMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),
FMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),
FNMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),
FNMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),
FDIV_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,N,Y,N,Y,N),
FSQRT_D -> List(N,Y,Y,N,N,N,X, D, D,N,N,N,N,N,Y,Y,N))
val fcvt_hd: Array[(BitPat, List[BitPat])] =
Array(FCVT_H_D -> List(N,Y,Y,N,N,N,X, D, H,N,N,Y,N,N,N,Y,N),
FCVT_D_H -> List(N,Y,Y,N,N,N,X, H, D,N,N,Y,N,N,N,Y,N))
val vfmv_f_s: Array[(BitPat, List[BitPat])] =
Array(VFMV_F_S -> List(N,Y,N,N,N,N,X,X2,X2,N,N,N,N,N,N,N,Y))
val insns = ((minFLen, fLen) match {
case (32, 32) => f
case (16, 32) => h ++ f
case (32, 64) => f ++ d
case (16, 64) => h ++ f ++ d ++ fcvt_hd
case other => throw new Exception(s"minFLen = ${minFLen} & fLen = ${fLen} is an unsupported configuration")
}) ++ (if (usingVector) vfmv_f_s else Array[(BitPat, List[BitPat])]())
val decoder = DecodeLogic(io.inst, default, insns)
val s = io.sigs
val sigs = Seq(s.ldst, s.wen, s.ren1, s.ren2, s.ren3, s.swap12,
s.swap23, s.typeTagIn, s.typeTagOut, s.fromint, s.toint,
s.fastpipe, s.fma, s.div, s.sqrt, s.wflags, s.vec)
sigs zip decoder map {case(s,d) => s := d}
}
class FPUCoreIO(implicit p: Parameters) extends CoreBundle()(p) {
val hartid = Input(UInt(hartIdLen.W))
val time = Input(UInt(xLen.W))
val inst = Input(Bits(32.W))
val fromint_data = Input(Bits(xLen.W))
val fcsr_rm = Input(Bits(FPConstants.RM_SZ.W))
val fcsr_flags = Valid(Bits(FPConstants.FLAGS_SZ.W))
val v_sew = Input(UInt(3.W))
val store_data = Output(Bits(fLen.W))
val toint_data = Output(Bits(xLen.W))
val ll_resp_val = Input(Bool())
val ll_resp_type = Input(Bits(3.W))
val ll_resp_tag = Input(UInt(5.W))
val ll_resp_data = Input(Bits(fLen.W))
val valid = Input(Bool())
val fcsr_rdy = Output(Bool())
val nack_mem = Output(Bool())
val illegal_rm = Output(Bool())
val killx = Input(Bool())
val killm = Input(Bool())
val dec = Output(new FPUCtrlSigs())
val sboard_set = Output(Bool())
val sboard_clr = Output(Bool())
val sboard_clra = Output(UInt(5.W))
val keep_clock_enabled = Input(Bool())
}
class FPUIO(implicit p: Parameters) extends FPUCoreIO ()(p) {
val cp_req = Flipped(Decoupled(new FPInput())) //cp doesn't pay attn to kill sigs
val cp_resp = Decoupled(new FPResult())
}
class FPResult(implicit p: Parameters) extends CoreBundle()(p) {
val data = Bits((fLen+1).W)
val exc = Bits(FPConstants.FLAGS_SZ.W)
}
class IntToFPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs {
val rm = Bits(FPConstants.RM_SZ.W)
val typ = Bits(2.W)
val in1 = Bits(xLen.W)
}
class FPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs {
val rm = Bits(FPConstants.RM_SZ.W)
val fmaCmd = Bits(2.W)
val typ = Bits(2.W)
val fmt = Bits(2.W)
val in1 = Bits((fLen+1).W)
val in2 = Bits((fLen+1).W)
val in3 = Bits((fLen+1).W)
}
case class FType(exp: Int, sig: Int) {
def ieeeWidth = exp + sig
def recodedWidth = ieeeWidth + 1
def ieeeQNaN = ((BigInt(1) << (ieeeWidth - 1)) - (BigInt(1) << (sig - 2))).U(ieeeWidth.W)
def qNaN = ((BigInt(7) << (exp + sig - 3)) + (BigInt(1) << (sig - 2))).U(recodedWidth.W)
def isNaN(x: UInt) = x(sig + exp - 1, sig + exp - 3).andR
def isSNaN(x: UInt) = isNaN(x) && !x(sig - 2)
def classify(x: UInt) = {
val sign = x(sig + exp)
val code = x(exp + sig - 1, exp + sig - 3)
val codeHi = code(2, 1)
val isSpecial = codeHi === 3.U
val isHighSubnormalIn = x(exp + sig - 3, sig - 1) < 2.U
val isSubnormal = code === 1.U || codeHi === 1.U && isHighSubnormalIn
val isNormal = codeHi === 1.U && !isHighSubnormalIn || codeHi === 2.U
val isZero = code === 0.U
val isInf = isSpecial && !code(0)
val isNaN = code.andR
val isSNaN = isNaN && !x(sig-2)
val isQNaN = isNaN && x(sig-2)
Cat(isQNaN, isSNaN, isInf && !sign, isNormal && !sign,
isSubnormal && !sign, isZero && !sign, isZero && sign,
isSubnormal && sign, isNormal && sign, isInf && sign)
}
// convert between formats, ignoring rounding, range, NaN
def unsafeConvert(x: UInt, to: FType) = if (this == to) x else {
val sign = x(sig + exp)
val fractIn = x(sig - 2, 0)
val expIn = x(sig + exp - 1, sig - 1)
val fractOut = fractIn << to.sig >> sig
val expOut = {
val expCode = expIn(exp, exp - 2)
val commonCase = (expIn + (1 << to.exp).U) - (1 << exp).U
Mux(expCode === 0.U || expCode >= 6.U, Cat(expCode, commonCase(to.exp - 3, 0)), commonCase(to.exp, 0))
}
Cat(sign, expOut, fractOut)
}
private def ieeeBundle = {
val expWidth = exp
class IEEEBundle extends Bundle {
val sign = Bool()
val exp = UInt(expWidth.W)
val sig = UInt((ieeeWidth-expWidth-1).W)
}
new IEEEBundle
}
def unpackIEEE(x: UInt) = x.asTypeOf(ieeeBundle)
def recode(x: UInt) = hardfloat.recFNFromFN(exp, sig, x)
def ieee(x: UInt) = hardfloat.fNFromRecFN(exp, sig, x)
}
object FType {
val H = new FType(5, 11)
val S = new FType(8, 24)
val D = new FType(11, 53)
val all = List(H, S, D)
}
trait HasFPUParameters {
require(fLen == 0 || FType.all.exists(_.ieeeWidth == fLen))
val minFLen: Int
val fLen: Int
def xLen: Int
val minXLen = 32
val nIntTypes = log2Ceil(xLen/minXLen) + 1
def floatTypes = FType.all.filter(t => minFLen <= t.ieeeWidth && t.ieeeWidth <= fLen)
def minType = floatTypes.head
def maxType = floatTypes.last
def prevType(t: FType) = floatTypes(typeTag(t) - 1)
def maxExpWidth = maxType.exp
def maxSigWidth = maxType.sig
def typeTag(t: FType) = floatTypes.indexOf(t)
def typeTagWbOffset = (FType.all.indexOf(minType) + 1).U
def typeTagGroup(t: FType) = (if (floatTypes.contains(t)) typeTag(t) else typeTag(maxType)).U
// typeTag
def H = typeTagGroup(FType.H)
def S = typeTagGroup(FType.S)
def D = typeTagGroup(FType.D)
def I = typeTag(maxType).U
private def isBox(x: UInt, t: FType): Bool = x(t.sig + t.exp, t.sig + t.exp - 4).andR
private def box(x: UInt, xt: FType, y: UInt, yt: FType): UInt = {
require(xt.ieeeWidth == 2 * yt.ieeeWidth)
val swizzledNaN = Cat(
x(xt.sig + xt.exp, xt.sig + xt.exp - 3),
x(xt.sig - 2, yt.recodedWidth - 1).andR,
x(xt.sig + xt.exp - 5, xt.sig),
y(yt.recodedWidth - 2),
x(xt.sig - 2, yt.recodedWidth - 1),
y(yt.recodedWidth - 1),
y(yt.recodedWidth - 3, 0))
Mux(xt.isNaN(x), swizzledNaN, x)
}
// implement NaN unboxing for FU inputs
def unbox(x: UInt, tag: UInt, exactType: Option[FType]): UInt = {
val outType = exactType.getOrElse(maxType)
def helper(x: UInt, t: FType): Seq[(Bool, UInt)] = {
val prev =
if (t == minType) {
Seq()
} else {
val prevT = prevType(t)
val unswizzled = Cat(
x(prevT.sig + prevT.exp - 1),
x(t.sig - 1),
x(prevT.sig + prevT.exp - 2, 0))
val prev = helper(unswizzled, prevT)
val isbox = isBox(x, t)
prev.map(p => (isbox && p._1, p._2))
}
prev :+ (true.B, t.unsafeConvert(x, outType))
}
val (oks, floats) = helper(x, maxType).unzip
if (exactType.isEmpty || floatTypes.size == 1) {
Mux(oks(tag), floats(tag), maxType.qNaN)
} else {
val t = exactType.get
floats(typeTag(t)) | Mux(oks(typeTag(t)), 0.U, t.qNaN)
}
}
// make sure that the redundant bits in the NaN-boxed encoding are consistent
def consistent(x: UInt): Bool = {
def helper(x: UInt, t: FType): Bool = if (typeTag(t) == 0) true.B else {
val prevT = prevType(t)
val unswizzled = Cat(
x(prevT.sig + prevT.exp - 1),
x(t.sig - 1),
x(prevT.sig + prevT.exp - 2, 0))
val prevOK = !isBox(x, t) || helper(unswizzled, prevT)
val curOK = !t.isNaN(x) || x(t.sig + t.exp - 4) === x(t.sig - 2, prevT.recodedWidth - 1).andR
prevOK && curOK
}
helper(x, maxType)
}
// generate a NaN box from an FU result
def box(x: UInt, t: FType): UInt = {
if (t == maxType) {
x
} else {
val nt = floatTypes(typeTag(t) + 1)
val bigger = box(((BigInt(1) << nt.recodedWidth)-1).U, nt, x, t)
bigger | ((BigInt(1) << maxType.recodedWidth) - (BigInt(1) << nt.recodedWidth)).U
}
}
// generate a NaN box from an FU result
def box(x: UInt, tag: UInt): UInt = {
val opts = floatTypes.map(t => box(x, t))
opts(tag)
}
// zap bits that hardfloat thinks are don't-cares, but we do care about
def sanitizeNaN(x: UInt, t: FType): UInt = {
if (typeTag(t) == 0) {
x
} else {
val maskedNaN = x & ~((BigInt(1) << (t.sig-1)) | (BigInt(1) << (t.sig+t.exp-4))).U(t.recodedWidth.W)
Mux(t.isNaN(x), maskedNaN, x)
}
}
// implement NaN boxing and recoding for FL*/fmv.*.x
def recode(x: UInt, tag: UInt): UInt = {
def helper(x: UInt, t: FType): UInt = {
if (typeTag(t) == 0) {
t.recode(x)
} else {
val prevT = prevType(t)
box(t.recode(x), t, helper(x, prevT), prevT)
}
}
// fill MSBs of subword loads to emulate a wider load of a NaN-boxed value
val boxes = floatTypes.map(t => ((BigInt(1) << maxType.ieeeWidth) - (BigInt(1) << t.ieeeWidth)).U)
helper(boxes(tag) | x, maxType)
}
// implement NaN unboxing and un-recoding for FS*/fmv.x.*
def ieee(x: UInt, t: FType = maxType): UInt = {
if (typeTag(t) == 0) {
t.ieee(x)
} else {
val unrecoded = t.ieee(x)
val prevT = prevType(t)
val prevRecoded = Cat(
x(prevT.recodedWidth-2),
x(t.sig-1),
x(prevT.recodedWidth-3, 0))
val prevUnrecoded = ieee(prevRecoded, prevT)
Cat(unrecoded >> prevT.ieeeWidth, Mux(t.isNaN(x), prevUnrecoded, unrecoded(prevT.ieeeWidth-1, 0)))
}
}
}
abstract class FPUModule(implicit val p: Parameters) extends Module with HasCoreParameters with HasFPUParameters
class FPToInt(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {
class Output extends Bundle {
val in = new FPInput
val lt = Bool()
val store = Bits(fLen.W)
val toint = Bits(xLen.W)
val exc = Bits(FPConstants.FLAGS_SZ.W)
}
val io = IO(new Bundle {
val in = Flipped(Valid(new FPInput))
val out = Valid(new Output)
})
val in = RegEnable(io.in.bits, io.in.valid)
val valid = RegNext(io.in.valid)
val dcmp = Module(new hardfloat.CompareRecFN(maxExpWidth, maxSigWidth))
dcmp.io.a := in.in1
dcmp.io.b := in.in2
dcmp.io.signaling := !in.rm(1)
val tag = in.typeTagOut
val toint_ieee = (floatTypes.map(t => if (t == FType.H) Fill(maxType.ieeeWidth / minXLen, ieee(in.in1)(15, 0).sextTo(minXLen))
else Fill(maxType.ieeeWidth / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag)
val toint = WireDefault(toint_ieee)
val intType = WireDefault(in.fmt(0))
io.out.bits.store := (floatTypes.map(t => Fill(fLen / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag)
io.out.bits.toint := ((0 until nIntTypes).map(i => toint((minXLen << i) - 1, 0).sextTo(xLen)): Seq[UInt])(intType)
io.out.bits.exc := 0.U
when (in.rm(0)) {
val classify_out = (floatTypes.map(t => t.classify(maxType.unsafeConvert(in.in1, t))): Seq[UInt])(tag)
toint := classify_out | (toint_ieee >> minXLen << minXLen)
intType := false.B
}
when (in.wflags) { // feq/flt/fle, fcvt
toint := (~in.rm & Cat(dcmp.io.lt, dcmp.io.eq)).orR | (toint_ieee >> minXLen << minXLen)
io.out.bits.exc := dcmp.io.exceptionFlags
intType := false.B
when (!in.ren2) { // fcvt
val cvtType = in.typ.extract(log2Ceil(nIntTypes), 1)
intType := cvtType
val conv = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, xLen))
conv.io.in := in.in1
conv.io.roundingMode := in.rm
conv.io.signedOut := ~in.typ(0)
toint := conv.io.out
io.out.bits.exc := Cat(conv.io.intExceptionFlags(2, 1).orR, 0.U(3.W), conv.io.intExceptionFlags(0))
for (i <- 0 until nIntTypes-1) {
val w = minXLen << i
when (cvtType === i.U) {
val narrow = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, w))
narrow.io.in := in.in1
narrow.io.roundingMode := in.rm
narrow.io.signedOut := ~in.typ(0)
val excSign = in.in1(maxExpWidth + maxSigWidth) && !maxType.isNaN(in.in1)
val excOut = Cat(conv.io.signedOut === excSign, Fill(w-1, !excSign))
val invalid = conv.io.intExceptionFlags(2) || narrow.io.intExceptionFlags(1)
when (invalid) { toint := Cat(conv.io.out >> w, excOut) }
io.out.bits.exc := Cat(invalid, 0.U(3.W), !invalid && conv.io.intExceptionFlags(0))
}
}
}
}
io.out.valid := valid
io.out.bits.lt := dcmp.io.lt || (dcmp.io.a.asSInt < 0.S && dcmp.io.b.asSInt >= 0.S)
io.out.bits.in := in
}
class IntToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {
val io = IO(new Bundle {
val in = Flipped(Valid(new IntToFPInput))
val out = Valid(new FPResult)
})
val in = Pipe(io.in)
val tag = in.bits.typeTagIn
val mux = Wire(new FPResult)
mux.exc := 0.U
mux.data := recode(in.bits.in1, tag)
val intValue = {
val res = WireDefault(in.bits.in1.asSInt)
for (i <- 0 until nIntTypes-1) {
val smallInt = in.bits.in1((minXLen << i) - 1, 0)
when (in.bits.typ.extract(log2Ceil(nIntTypes), 1) === i.U) {
res := Mux(in.bits.typ(0), smallInt.zext, smallInt.asSInt)
}
}
res.asUInt
}
when (in.bits.wflags) { // fcvt
// could be improved for RVD/RVQ with a single variable-position rounding
// unit, rather than N fixed-position ones
val i2fResults = for (t <- floatTypes) yield {
val i2f = Module(new hardfloat.INToRecFN(xLen, t.exp, t.sig))
i2f.io.signedIn := ~in.bits.typ(0)
i2f.io.in := intValue
i2f.io.roundingMode := in.bits.rm
i2f.io.detectTininess := hardfloat.consts.tininess_afterRounding
(sanitizeNaN(i2f.io.out, t), i2f.io.exceptionFlags)
}
val (data, exc) = i2fResults.unzip
val dataPadded = data.init.map(d => Cat(data.last >> d.getWidth, d)) :+ data.last
mux.data := dataPadded(tag)
mux.exc := exc(tag)
}
io.out <> Pipe(in.valid, mux, latency-1)
}
class FPToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {
val io = IO(new Bundle {
val in = Flipped(Valid(new FPInput))
val out = Valid(new FPResult)
val lt = Input(Bool()) // from FPToInt
})
val in = Pipe(io.in)
val signNum = Mux(in.bits.rm(1), in.bits.in1 ^ in.bits.in2, Mux(in.bits.rm(0), ~in.bits.in2, in.bits.in2))
val fsgnj = Cat(signNum(fLen), in.bits.in1(fLen-1, 0))
val fsgnjMux = Wire(new FPResult)
fsgnjMux.exc := 0.U
fsgnjMux.data := fsgnj
when (in.bits.wflags) { // fmin/fmax
val isnan1 = maxType.isNaN(in.bits.in1)
val isnan2 = maxType.isNaN(in.bits.in2)
val isInvalid = maxType.isSNaN(in.bits.in1) || maxType.isSNaN(in.bits.in2)
val isNaNOut = isnan1 && isnan2
val isLHS = isnan2 || in.bits.rm(0) =/= io.lt && !isnan1
fsgnjMux.exc := isInvalid << 4
fsgnjMux.data := Mux(isNaNOut, maxType.qNaN, Mux(isLHS, in.bits.in1, in.bits.in2))
}
val inTag = in.bits.typeTagIn
val outTag = in.bits.typeTagOut
val mux = WireDefault(fsgnjMux)
for (t <- floatTypes.init) {
when (outTag === typeTag(t).U) {
mux.data := Cat(fsgnjMux.data >> t.recodedWidth, maxType.unsafeConvert(fsgnjMux.data, t))
}
}
when (in.bits.wflags && !in.bits.ren2) { // fcvt
if (floatTypes.size > 1) {
// widening conversions simply canonicalize NaN operands
val widened = Mux(maxType.isNaN(in.bits.in1), maxType.qNaN, in.bits.in1)
fsgnjMux.data := widened
fsgnjMux.exc := maxType.isSNaN(in.bits.in1) << 4
// narrowing conversions require rounding (for RVQ, this could be
// optimized to use a single variable-position rounding unit, rather
// than two fixed-position ones)
for (outType <- floatTypes.init) when (outTag === typeTag(outType).U && ((typeTag(outType) == 0).B || outTag < inTag)) {
val narrower = Module(new hardfloat.RecFNToRecFN(maxType.exp, maxType.sig, outType.exp, outType.sig))
narrower.io.in := in.bits.in1
narrower.io.roundingMode := in.bits.rm
narrower.io.detectTininess := hardfloat.consts.tininess_afterRounding
val narrowed = sanitizeNaN(narrower.io.out, outType)
mux.data := Cat(fsgnjMux.data >> narrowed.getWidth, narrowed)
mux.exc := narrower.io.exceptionFlags
}
}
}
io.out <> Pipe(in.valid, mux, latency-1)
}
class MulAddRecFNPipe(latency: Int, expWidth: Int, sigWidth: Int) extends Module
{
override def desiredName = s"MulAddRecFNPipe_l${latency}_e${expWidth}_s${sigWidth}"
require(latency<=2)
val io = IO(new Bundle {
val validin = Input(Bool())
val op = Input(Bits(2.W))
val a = Input(Bits((expWidth + sigWidth + 1).W))
val b = Input(Bits((expWidth + sigWidth + 1).W))
val c = Input(Bits((expWidth + sigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
val validout = Output(Bool())
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val mulAddRecFNToRaw_preMul = Module(new hardfloat.MulAddRecFNToRaw_preMul(expWidth, sigWidth))
val mulAddRecFNToRaw_postMul = Module(new hardfloat.MulAddRecFNToRaw_postMul(expWidth, sigWidth))
mulAddRecFNToRaw_preMul.io.op := io.op
mulAddRecFNToRaw_preMul.io.a := io.a
mulAddRecFNToRaw_preMul.io.b := io.b
mulAddRecFNToRaw_preMul.io.c := io.c
val mulAddResult =
(mulAddRecFNToRaw_preMul.io.mulAddA *
mulAddRecFNToRaw_preMul.io.mulAddB) +&
mulAddRecFNToRaw_preMul.io.mulAddC
val valid_stage0 = Wire(Bool())
val roundingMode_stage0 = Wire(UInt(3.W))
val detectTininess_stage0 = Wire(UInt(1.W))
val postmul_regs = if(latency>0) 1 else 0
mulAddRecFNToRaw_postMul.io.fromPreMul := Pipe(io.validin, mulAddRecFNToRaw_preMul.io.toPostMul, postmul_regs).bits
mulAddRecFNToRaw_postMul.io.mulAddResult := Pipe(io.validin, mulAddResult, postmul_regs).bits
mulAddRecFNToRaw_postMul.io.roundingMode := Pipe(io.validin, io.roundingMode, postmul_regs).bits
roundingMode_stage0 := Pipe(io.validin, io.roundingMode, postmul_regs).bits
detectTininess_stage0 := Pipe(io.validin, io.detectTininess, postmul_regs).bits
valid_stage0 := Pipe(io.validin, false.B, postmul_regs).valid
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundRawFNToRecFN = Module(new hardfloat.RoundRawFNToRecFN(expWidth, sigWidth, 0))
val round_regs = if(latency==2) 1 else 0
roundRawFNToRecFN.io.invalidExc := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.invalidExc, round_regs).bits
roundRawFNToRecFN.io.in := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.rawOut, round_regs).bits
roundRawFNToRecFN.io.roundingMode := Pipe(valid_stage0, roundingMode_stage0, round_regs).bits
roundRawFNToRecFN.io.detectTininess := Pipe(valid_stage0, detectTininess_stage0, round_regs).bits
io.validout := Pipe(valid_stage0, false.B, round_regs).valid
roundRawFNToRecFN.io.infiniteExc := false.B
io.out := roundRawFNToRecFN.io.out
io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags
}
class FPUFMAPipe(val latency: Int, val t: FType)
(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {
override def desiredName = s"FPUFMAPipe_l${latency}_f${t.ieeeWidth}"
require(latency>0)
val io = IO(new Bundle {
val in = Flipped(Valid(new FPInput))
val out = Valid(new FPResult)
})
val valid = RegNext(io.in.valid)
val in = Reg(new FPInput)
when (io.in.valid) {
val one = 1.U << (t.sig + t.exp - 1)
val zero = (io.in.bits.in1 ^ io.in.bits.in2) & (1.U << (t.sig + t.exp))
val cmd_fma = io.in.bits.ren3
val cmd_addsub = io.in.bits.swap23
in := io.in.bits
when (cmd_addsub) { in.in2 := one }
when (!(cmd_fma || cmd_addsub)) { in.in3 := zero }
}
val fma = Module(new MulAddRecFNPipe((latency-1) min 2, t.exp, t.sig))
fma.io.validin := valid
fma.io.op := in.fmaCmd
fma.io.roundingMode := in.rm
fma.io.detectTininess := hardfloat.consts.tininess_afterRounding
fma.io.a := in.in1
fma.io.b := in.in2
fma.io.c := in.in3
val res = Wire(new FPResult)
res.data := sanitizeNaN(fma.io.out, t)
res.exc := fma.io.exceptionFlags
io.out := Pipe(fma.io.validout, res, (latency-3) max 0)
}
class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) {
val io = IO(new FPUIO)
val (useClockGating, useDebugROB) = coreParams match {
case r: RocketCoreParams =>
val sz = if (r.debugROB.isDefined) r.debugROB.get.size else 1
(r.clockGate, sz < 1)
case _ => (false, false)
}
val clock_en_reg = Reg(Bool())
val clock_en = clock_en_reg || io.cp_req.valid
val gated_clock =
if (!useClockGating) clock
else ClockGate(clock, clock_en, "fpu_clock_gate")
val fp_decoder = Module(new FPUDecoder)
fp_decoder.io.inst := io.inst
val id_ctrl = WireInit(fp_decoder.io.sigs)
coreParams match { case r: RocketCoreParams => r.vector.map(v => {
val v_decode = v.decoder(p) // Only need to get ren1
v_decode.io.inst := io.inst
v_decode.io.vconfig := DontCare // core deals with this
when (v_decode.io.legal && v_decode.io.read_frs1) {
id_ctrl.ren1 := true.B
id_ctrl.swap12 := false.B
id_ctrl.toint := true.B
id_ctrl.typeTagIn := I
id_ctrl.typeTagOut := Mux(io.v_sew === 3.U, D, S)
}
when (v_decode.io.write_frd) { id_ctrl.wen := true.B }
})}
val ex_reg_valid = RegNext(io.valid, false.B)
val ex_reg_inst = RegEnable(io.inst, io.valid)
val ex_reg_ctrl = RegEnable(id_ctrl, io.valid)
val ex_ra = List.fill(3)(Reg(UInt()))
// load/vector response
val load_wb = RegNext(io.ll_resp_val)
val load_wb_typeTag = RegEnable(io.ll_resp_type(1,0) - typeTagWbOffset, io.ll_resp_val)
val load_wb_data = RegEnable(io.ll_resp_data, io.ll_resp_val)
val load_wb_tag = RegEnable(io.ll_resp_tag, io.ll_resp_val)
class FPUImpl { // entering gated-clock domain
val req_valid = ex_reg_valid || io.cp_req.valid
val ex_cp_valid = io.cp_req.fire
val mem_cp_valid = RegNext(ex_cp_valid, false.B)
val wb_cp_valid = RegNext(mem_cp_valid, false.B)
val mem_reg_valid = RegInit(false.B)
val killm = (io.killm || io.nack_mem) && !mem_cp_valid
// Kill X-stage instruction if M-stage is killed. This prevents it from
// speculatively being sent to the div-sqrt unit, which can cause priority
// inversion for two back-to-back divides, the first of which is killed.
val killx = io.killx || mem_reg_valid && killm
mem_reg_valid := ex_reg_valid && !killx || ex_cp_valid
val mem_reg_inst = RegEnable(ex_reg_inst, ex_reg_valid)
val wb_reg_valid = RegNext(mem_reg_valid && (!killm || mem_cp_valid), false.B)
val cp_ctrl = Wire(new FPUCtrlSigs)
cp_ctrl :<>= io.cp_req.bits.viewAsSupertype(new FPUCtrlSigs)
io.cp_resp.valid := false.B
io.cp_resp.bits.data := 0.U
io.cp_resp.bits.exc := DontCare
val ex_ctrl = Mux(ex_cp_valid, cp_ctrl, ex_reg_ctrl)
val mem_ctrl = RegEnable(ex_ctrl, req_valid)
val wb_ctrl = RegEnable(mem_ctrl, mem_reg_valid)
// CoreMonitorBundle to monitor fp register file writes
val frfWriteBundle = Seq.fill(2)(WireInit(new CoreMonitorBundle(xLen, fLen), DontCare))
frfWriteBundle.foreach { i =>
i.clock := clock
i.reset := reset
i.hartid := io.hartid
i.timer := io.time(31,0)
i.valid := false.B
i.wrenx := false.B
i.wrenf := false.B
i.excpt := false.B
}
// regfile
val regfile = Mem(32, Bits((fLen+1).W))
when (load_wb) {
val wdata = recode(load_wb_data, load_wb_typeTag)
regfile(load_wb_tag) := wdata
assert(consistent(wdata))
if (enableCommitLog)
printf("f%d p%d 0x%x\n", load_wb_tag, load_wb_tag + 32.U, ieee(wdata))
if (useDebugROB)
DebugROB.pushWb(clock, reset, io.hartid, load_wb, load_wb_tag + 32.U, ieee(wdata))
frfWriteBundle(0).wrdst := load_wb_tag
frfWriteBundle(0).wrenf := true.B
frfWriteBundle(0).wrdata := ieee(wdata)
}
val ex_rs = ex_ra.map(a => regfile(a))
when (io.valid) {
when (id_ctrl.ren1) {
when (!id_ctrl.swap12) { ex_ra(0) := io.inst(19,15) }
when (id_ctrl.swap12) { ex_ra(1) := io.inst(19,15) }
}
when (id_ctrl.ren2) {
when (id_ctrl.swap12) { ex_ra(0) := io.inst(24,20) }
when (id_ctrl.swap23) { ex_ra(2) := io.inst(24,20) }
when (!id_ctrl.swap12 && !id_ctrl.swap23) { ex_ra(1) := io.inst(24,20) }
}
when (id_ctrl.ren3) { ex_ra(2) := io.inst(31,27) }
}
val ex_rm = Mux(ex_reg_inst(14,12) === 7.U, io.fcsr_rm, ex_reg_inst(14,12))
def fuInput(minT: Option[FType]): FPInput = {
val req = Wire(new FPInput)
val tag = ex_ctrl.typeTagIn
req.viewAsSupertype(new Bundle with HasFPUCtrlSigs) :#= ex_ctrl.viewAsSupertype(new Bundle with HasFPUCtrlSigs)
req.rm := ex_rm
req.in1 := unbox(ex_rs(0), tag, minT)
req.in2 := unbox(ex_rs(1), tag, minT)
req.in3 := unbox(ex_rs(2), tag, minT)
req.typ := ex_reg_inst(21,20)
req.fmt := ex_reg_inst(26,25)
req.fmaCmd := ex_reg_inst(3,2) | (!ex_ctrl.ren3 && ex_reg_inst(27))
when (ex_cp_valid) {
req := io.cp_req.bits
when (io.cp_req.bits.swap12) {
req.in1 := io.cp_req.bits.in2
req.in2 := io.cp_req.bits.in1
}
when (io.cp_req.bits.swap23) {
req.in2 := io.cp_req.bits.in3
req.in3 := io.cp_req.bits.in2
}
}
req
}
val sfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.S))
sfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === S
sfma.io.in.bits := fuInput(Some(sfma.t))
val fpiu = Module(new FPToInt)
fpiu.io.in.valid := req_valid && (ex_ctrl.toint || ex_ctrl.div || ex_ctrl.sqrt || (ex_ctrl.fastpipe && ex_ctrl.wflags))
fpiu.io.in.bits := fuInput(None)
io.store_data := fpiu.io.out.bits.store
io.toint_data := fpiu.io.out.bits.toint
when(fpiu.io.out.valid && mem_cp_valid && mem_ctrl.toint){
io.cp_resp.bits.data := fpiu.io.out.bits.toint
io.cp_resp.valid := true.B
}
val ifpu = Module(new IntToFP(cfg.ifpuLatency))
ifpu.io.in.valid := req_valid && ex_ctrl.fromint
ifpu.io.in.bits := fpiu.io.in.bits
ifpu.io.in.bits.in1 := Mux(ex_cp_valid, io.cp_req.bits.in1, io.fromint_data)
val fpmu = Module(new FPToFP(cfg.fpmuLatency))
fpmu.io.in.valid := req_valid && ex_ctrl.fastpipe
fpmu.io.in.bits := fpiu.io.in.bits
fpmu.io.lt := fpiu.io.out.bits.lt
val divSqrt_wen = WireDefault(false.B)
val divSqrt_inFlight = WireDefault(false.B)
val divSqrt_waddr = Reg(UInt(5.W))
val divSqrt_cp = Reg(Bool())
val divSqrt_typeTag = Wire(UInt(log2Up(floatTypes.size).W))
val divSqrt_wdata = Wire(UInt((fLen+1).W))
val divSqrt_flags = Wire(UInt(FPConstants.FLAGS_SZ.W))
divSqrt_typeTag := DontCare
divSqrt_wdata := DontCare
divSqrt_flags := DontCare
// writeback arbitration
case class Pipe(p: Module, lat: Int, cond: (FPUCtrlSigs) => Bool, res: FPResult)
val pipes = List(
Pipe(fpmu, fpmu.latency, (c: FPUCtrlSigs) => c.fastpipe, fpmu.io.out.bits),
Pipe(ifpu, ifpu.latency, (c: FPUCtrlSigs) => c.fromint, ifpu.io.out.bits),
Pipe(sfma, sfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === S, sfma.io.out.bits)) ++
(fLen > 32).option({
val dfma = Module(new FPUFMAPipe(cfg.dfmaLatency, FType.D))
dfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === D
dfma.io.in.bits := fuInput(Some(dfma.t))
Pipe(dfma, dfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === D, dfma.io.out.bits)
}) ++
(minFLen == 16).option({
val hfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.H))
hfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === H
hfma.io.in.bits := fuInput(Some(hfma.t))
Pipe(hfma, hfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === H, hfma.io.out.bits)
})
def latencyMask(c: FPUCtrlSigs, offset: Int) = {
require(pipes.forall(_.lat >= offset))
pipes.map(p => Mux(p.cond(c), (1 << p.lat-offset).U, 0.U)).reduce(_|_)
}
def pipeid(c: FPUCtrlSigs) = pipes.zipWithIndex.map(p => Mux(p._1.cond(c), p._2.U, 0.U)).reduce(_|_)
val maxLatency = pipes.map(_.lat).max
val memLatencyMask = latencyMask(mem_ctrl, 2)
class WBInfo extends Bundle {
val rd = UInt(5.W)
val typeTag = UInt(log2Up(floatTypes.size).W)
val cp = Bool()
val pipeid = UInt(log2Ceil(pipes.size).W)
}
val wen = RegInit(0.U((maxLatency-1).W))
val wbInfo = Reg(Vec(maxLatency-1, new WBInfo))
val mem_wen = mem_reg_valid && (mem_ctrl.fma || mem_ctrl.fastpipe || mem_ctrl.fromint)
val write_port_busy = RegEnable(mem_wen && (memLatencyMask & latencyMask(ex_ctrl, 1)).orR || (wen & latencyMask(ex_ctrl, 0)).orR, req_valid)
ccover(mem_reg_valid && write_port_busy, "WB_STRUCTURAL", "structural hazard on writeback")
for (i <- 0 until maxLatency-2) {
when (wen(i+1)) { wbInfo(i) := wbInfo(i+1) }
}
wen := wen >> 1
when (mem_wen) {
when (!killm) {
wen := wen >> 1 | memLatencyMask
}
for (i <- 0 until maxLatency-1) {
when (!write_port_busy && memLatencyMask(i)) {
wbInfo(i).cp := mem_cp_valid
wbInfo(i).typeTag := mem_ctrl.typeTagOut
wbInfo(i).pipeid := pipeid(mem_ctrl)
wbInfo(i).rd := mem_reg_inst(11,7)
}
}
}
val waddr = Mux(divSqrt_wen, divSqrt_waddr, wbInfo(0).rd)
val wb_cp = Mux(divSqrt_wen, divSqrt_cp, wbInfo(0).cp)
val wtypeTag = Mux(divSqrt_wen, divSqrt_typeTag, wbInfo(0).typeTag)
val wdata = box(Mux(divSqrt_wen, divSqrt_wdata, (pipes.map(_.res.data): Seq[UInt])(wbInfo(0).pipeid)), wtypeTag)
val wexc = (pipes.map(_.res.exc): Seq[UInt])(wbInfo(0).pipeid)
when ((!wbInfo(0).cp && wen(0)) || divSqrt_wen) {
assert(consistent(wdata))
regfile(waddr) := wdata
if (enableCommitLog) {
printf("f%d p%d 0x%x\n", waddr, waddr + 32.U, ieee(wdata))
}
frfWriteBundle(1).wrdst := waddr
frfWriteBundle(1).wrenf := true.B
frfWriteBundle(1).wrdata := ieee(wdata)
}
if (useDebugROB) {
DebugROB.pushWb(clock, reset, io.hartid, (!wbInfo(0).cp && wen(0)) || divSqrt_wen, waddr + 32.U, ieee(wdata))
}
when (wb_cp && (wen(0) || divSqrt_wen)) {
io.cp_resp.bits.data := wdata
io.cp_resp.valid := true.B
}
assert(!io.cp_req.valid || pipes.forall(_.lat == pipes.head.lat).B,
s"FPU only supports coprocessor if FMA pipes have uniform latency ${pipes.map(_.lat)}")
// Avoid structural hazards and nacking of external requests
// toint responds in the MEM stage, so an incoming toint can induce a structural hazard against inflight FMAs
io.cp_req.ready := !ex_reg_valid && !(cp_ctrl.toint && wen =/= 0.U) && !divSqrt_inFlight
val wb_toint_valid = wb_reg_valid && wb_ctrl.toint
val wb_toint_exc = RegEnable(fpiu.io.out.bits.exc, mem_ctrl.toint)
io.fcsr_flags.valid := wb_toint_valid || divSqrt_wen || wen(0)
io.fcsr_flags.bits :=
Mux(wb_toint_valid, wb_toint_exc, 0.U) |
Mux(divSqrt_wen, divSqrt_flags, 0.U) |
Mux(wen(0), wexc, 0.U)
val divSqrt_write_port_busy = (mem_ctrl.div || mem_ctrl.sqrt) && wen.orR
io.fcsr_rdy := !(ex_reg_valid && ex_ctrl.wflags || mem_reg_valid && mem_ctrl.wflags || wb_reg_valid && wb_ctrl.toint || wen.orR || divSqrt_inFlight)
io.nack_mem := (write_port_busy || divSqrt_write_port_busy || divSqrt_inFlight) && !mem_cp_valid
io.dec <> id_ctrl
def useScoreboard(f: ((Pipe, Int)) => Bool) = pipes.zipWithIndex.filter(_._1.lat > 3).map(x => f(x)).fold(false.B)(_||_)
io.sboard_set := wb_reg_valid && !wb_cp_valid && RegNext(useScoreboard(_._1.cond(mem_ctrl)) || mem_ctrl.div || mem_ctrl.sqrt || mem_ctrl.vec)
io.sboard_clr := !wb_cp_valid && (divSqrt_wen || (wen(0) && useScoreboard(x => wbInfo(0).pipeid === x._2.U)))
io.sboard_clra := waddr
ccover(io.sboard_clr && load_wb, "DUAL_WRITEBACK", "load and FMA writeback on same cycle")
// we don't currently support round-max-magnitude (rm=4)
io.illegal_rm := io.inst(14,12).isOneOf(5.U, 6.U) || io.inst(14,12) === 7.U && io.fcsr_rm >= 5.U
if (cfg.divSqrt) {
val divSqrt_inValid = mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt) && !divSqrt_inFlight
val divSqrt_killed = RegNext(divSqrt_inValid && killm, true.B)
when (divSqrt_inValid) {
divSqrt_waddr := mem_reg_inst(11,7)
divSqrt_cp := mem_cp_valid
}
ccover(divSqrt_inFlight && divSqrt_killed, "DIV_KILLED", "divide killed after issued to divider")
ccover(divSqrt_inFlight && mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt), "DIV_BUSY", "divider structural hazard")
ccover(mem_reg_valid && divSqrt_write_port_busy, "DIV_WB_STRUCTURAL", "structural hazard on division writeback")
for (t <- floatTypes) {
val tag = mem_ctrl.typeTagOut
val divSqrt = withReset(divSqrt_killed) { Module(new hardfloat.DivSqrtRecFN_small(t.exp, t.sig, 0)) }
divSqrt.io.inValid := divSqrt_inValid && tag === typeTag(t).U
divSqrt.io.sqrtOp := mem_ctrl.sqrt
divSqrt.io.a := maxType.unsafeConvert(fpiu.io.out.bits.in.in1, t)
divSqrt.io.b := maxType.unsafeConvert(fpiu.io.out.bits.in.in2, t)
divSqrt.io.roundingMode := fpiu.io.out.bits.in.rm
divSqrt.io.detectTininess := hardfloat.consts.tininess_afterRounding
when (!divSqrt.io.inReady) { divSqrt_inFlight := true.B } // only 1 in flight
when (divSqrt.io.outValid_div || divSqrt.io.outValid_sqrt) {
divSqrt_wen := !divSqrt_killed
divSqrt_wdata := sanitizeNaN(divSqrt.io.out, t)
divSqrt_flags := divSqrt.io.exceptionFlags
divSqrt_typeTag := typeTag(t).U
}
}
when (divSqrt_killed) { divSqrt_inFlight := false.B }
} else {
when (id_ctrl.div || id_ctrl.sqrt) { io.illegal_rm := true.B }
}
// gate the clock
clock_en_reg := !useClockGating.B ||
io.keep_clock_enabled || // chicken bit
io.valid || // ID stage
req_valid || // EX stage
mem_reg_valid || mem_cp_valid || // MEM stage
wb_reg_valid || wb_cp_valid || // WB stage
wen.orR || divSqrt_inFlight || // post-WB stage
io.ll_resp_val // load writeback
} // leaving gated-clock domain
val fpuImpl = withClock (gated_clock) { new FPUImpl }
def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) =
property.cover(cond, s"FPU_$label", "Core;;" + desc)
}
| module MulAddRecFNPipe_l2_e11_s53_4( // @[FPU.scala:633:7]
input clock, // @[FPU.scala:633:7]
input reset, // @[FPU.scala:633:7]
input io_validin, // @[FPU.scala:638:16]
input [1:0] io_op, // @[FPU.scala:638:16]
input [64:0] io_a, // @[FPU.scala:638:16]
input [64:0] io_b, // @[FPU.scala:638:16]
input [64:0] io_c, // @[FPU.scala:638:16]
input [2:0] io_roundingMode, // @[FPU.scala:638:16]
output [64:0] io_out, // @[FPU.scala:638:16]
output [4:0] io_exceptionFlags, // @[FPU.scala:638:16]
output io_validout // @[FPU.scala:638:16]
);
wire _mulAddRecFNToRaw_postMul_io_invalidExc; // @[FPU.scala:655:42]
wire _mulAddRecFNToRaw_postMul_io_rawOut_isNaN; // @[FPU.scala:655:42]
wire _mulAddRecFNToRaw_postMul_io_rawOut_isInf; // @[FPU.scala:655:42]
wire _mulAddRecFNToRaw_postMul_io_rawOut_isZero; // @[FPU.scala:655:42]
wire _mulAddRecFNToRaw_postMul_io_rawOut_sign; // @[FPU.scala:655:42]
wire [12:0] _mulAddRecFNToRaw_postMul_io_rawOut_sExp; // @[FPU.scala:655:42]
wire [55:0] _mulAddRecFNToRaw_postMul_io_rawOut_sig; // @[FPU.scala:655:42]
wire [52:0] _mulAddRecFNToRaw_preMul_io_mulAddA; // @[FPU.scala:654:41]
wire [52:0] _mulAddRecFNToRaw_preMul_io_mulAddB; // @[FPU.scala:654:41]
wire [105:0] _mulAddRecFNToRaw_preMul_io_mulAddC; // @[FPU.scala:654:41]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny; // @[FPU.scala:654:41]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB; // @[FPU.scala:654:41]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfA; // @[FPU.scala:654:41]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA; // @[FPU.scala:654:41]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfB; // @[FPU.scala:654:41]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB; // @[FPU.scala:654:41]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_signProd; // @[FPU.scala:654:41]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC; // @[FPU.scala:654:41]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfC; // @[FPU.scala:654:41]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC; // @[FPU.scala:654:41]
wire [12:0] _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum; // @[FPU.scala:654:41]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags; // @[FPU.scala:654:41]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant; // @[FPU.scala:654:41]
wire [5:0] _mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist; // @[FPU.scala:654:41]
wire [54:0] _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC; // @[FPU.scala:654:41]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC; // @[FPU.scala:654:41]
wire io_validin_0 = io_validin; // @[FPU.scala:633:7]
wire [1:0] io_op_0 = io_op; // @[FPU.scala:633:7]
wire [64:0] io_a_0 = io_a; // @[FPU.scala:633:7]
wire [64:0] io_b_0 = io_b; // @[FPU.scala:633:7]
wire [64:0] io_c_0 = io_c; // @[FPU.scala:633:7]
wire [2:0] io_roundingMode_0 = io_roundingMode; // @[FPU.scala:633:7]
wire io_detectTininess = 1'h1; // @[FPU.scala:633:7]
wire detectTininess_stage0 = 1'h1; // @[FPU.scala:669:37]
wire detectTininess_stage0_pipe_out_bits = 1'h1; // @[Valid.scala:135:21]
wire valid_stage0_pipe_out_bits = 1'h0; // @[Valid.scala:135:21]
wire io_validout_pipe_out_bits = 1'h0; // @[Valid.scala:135:21]
wire io_validout_pipe_out_valid; // @[Valid.scala:135:21]
wire [64:0] io_out_0; // @[FPU.scala:633:7]
wire [4:0] io_exceptionFlags_0; // @[FPU.scala:633:7]
wire io_validout_0; // @[FPU.scala:633:7]
wire [105:0] _mulAddResult_T = {53'h0, _mulAddRecFNToRaw_preMul_io_mulAddA} * {53'h0, _mulAddRecFNToRaw_preMul_io_mulAddB}; // @[FPU.scala:654:41, :663:45]
wire [106:0] mulAddResult = {1'h0, _mulAddResult_T} + {1'h0, _mulAddRecFNToRaw_preMul_io_mulAddC}; // @[FPU.scala:654:41, :663:45, :664:50]
wire valid_stage0_pipe_out_valid; // @[Valid.scala:135:21]
wire valid_stage0; // @[FPU.scala:667:28]
wire [2:0] roundingMode_stage0_pipe_out_bits; // @[Valid.scala:135:21]
wire [2:0] roundingMode_stage0; // @[FPU.scala:668:35]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v; // @[Valid.scala:141:24]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_valid = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v; // @[Valid.scala:135:21, :141:24]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isSigNaNAny; // @[Valid.scala:142:26]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isSigNaNAny = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isSigNaNAny; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNAOrB; // @[Valid.scala:142:26]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isNaNAOrB = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNAOrB; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfA; // @[Valid.scala:142:26]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfA = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfA; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroA; // @[Valid.scala:142:26]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroA = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroA; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfB; // @[Valid.scala:142:26]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfB = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfB; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroB; // @[Valid.scala:142:26]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroB = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroB; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_signProd; // @[Valid.scala:142:26]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_signProd = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_signProd; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNC; // @[Valid.scala:142:26]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isNaNC = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNC; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfC; // @[Valid.scala:142:26]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfC = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfC; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroC; // @[Valid.scala:142:26]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroC = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroC; // @[Valid.scala:135:21, :142:26]
reg [12:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_sExpSum; // @[Valid.scala:142:26]
wire [12:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_sExpSum = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_sExpSum; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_doSubMags; // @[Valid.scala:142:26]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_doSubMags = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_doSubMags; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CIsDominant; // @[Valid.scala:142:26]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_CIsDominant = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CIsDominant; // @[Valid.scala:135:21, :142:26]
reg [5:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CDom_CAlignDist; // @[Valid.scala:142:26]
wire [5:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_CDom_CAlignDist = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CDom_CAlignDist; // @[Valid.scala:135:21, :142:26]
reg [54:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_highAlignedSigC; // @[Valid.scala:142:26]
wire [54:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_highAlignedSigC = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_highAlignedSigC; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_bit0AlignedSigC; // @[Valid.scala:142:26]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_bit0AlignedSigC = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_bit0AlignedSigC; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v; // @[Valid.scala:141:24]
wire mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out_valid = mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v; // @[Valid.scala:135:21, :141:24]
reg [106:0] mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b; // @[Valid.scala:142:26]
wire [106:0] mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out_bits = mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v; // @[Valid.scala:141:24]
wire mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out_valid = mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v; // @[Valid.scala:135:21, :141:24]
reg [2:0] mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b; // @[Valid.scala:142:26]
wire [2:0] mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out_bits = mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b; // @[Valid.scala:135:21, :142:26]
reg roundingMode_stage0_pipe_v; // @[Valid.scala:141:24]
wire roundingMode_stage0_pipe_out_valid = roundingMode_stage0_pipe_v; // @[Valid.scala:135:21, :141:24]
reg [2:0] roundingMode_stage0_pipe_b; // @[Valid.scala:142:26]
assign roundingMode_stage0_pipe_out_bits = roundingMode_stage0_pipe_b; // @[Valid.scala:135:21, :142:26]
assign roundingMode_stage0 = roundingMode_stage0_pipe_out_bits; // @[Valid.scala:135:21]
reg detectTininess_stage0_pipe_v; // @[Valid.scala:141:24]
wire detectTininess_stage0_pipe_out_valid = detectTininess_stage0_pipe_v; // @[Valid.scala:135:21, :141:24]
reg valid_stage0_pipe_v; // @[Valid.scala:141:24]
assign valid_stage0_pipe_out_valid = valid_stage0_pipe_v; // @[Valid.scala:135:21, :141:24]
assign valid_stage0 = valid_stage0_pipe_out_valid; // @[Valid.scala:135:21]
reg roundRawFNToRecFN_io_invalidExc_pipe_v; // @[Valid.scala:141:24]
wire roundRawFNToRecFN_io_invalidExc_pipe_out_valid = roundRawFNToRecFN_io_invalidExc_pipe_v; // @[Valid.scala:135:21, :141:24]
reg roundRawFNToRecFN_io_invalidExc_pipe_b; // @[Valid.scala:142:26]
wire roundRawFNToRecFN_io_invalidExc_pipe_out_bits = roundRawFNToRecFN_io_invalidExc_pipe_b; // @[Valid.scala:135:21, :142:26]
reg roundRawFNToRecFN_io_in_pipe_v; // @[Valid.scala:141:24]
wire roundRawFNToRecFN_io_in_pipe_out_valid = roundRawFNToRecFN_io_in_pipe_v; // @[Valid.scala:135:21, :141:24]
reg roundRawFNToRecFN_io_in_pipe_b_isNaN; // @[Valid.scala:142:26]
wire roundRawFNToRecFN_io_in_pipe_out_bits_isNaN = roundRawFNToRecFN_io_in_pipe_b_isNaN; // @[Valid.scala:135:21, :142:26]
reg roundRawFNToRecFN_io_in_pipe_b_isInf; // @[Valid.scala:142:26]
wire roundRawFNToRecFN_io_in_pipe_out_bits_isInf = roundRawFNToRecFN_io_in_pipe_b_isInf; // @[Valid.scala:135:21, :142:26]
reg roundRawFNToRecFN_io_in_pipe_b_isZero; // @[Valid.scala:142:26]
wire roundRawFNToRecFN_io_in_pipe_out_bits_isZero = roundRawFNToRecFN_io_in_pipe_b_isZero; // @[Valid.scala:135:21, :142:26]
reg roundRawFNToRecFN_io_in_pipe_b_sign; // @[Valid.scala:142:26]
wire roundRawFNToRecFN_io_in_pipe_out_bits_sign = roundRawFNToRecFN_io_in_pipe_b_sign; // @[Valid.scala:135:21, :142:26]
reg [12:0] roundRawFNToRecFN_io_in_pipe_b_sExp; // @[Valid.scala:142:26]
wire [12:0] roundRawFNToRecFN_io_in_pipe_out_bits_sExp = roundRawFNToRecFN_io_in_pipe_b_sExp; // @[Valid.scala:135:21, :142:26]
reg [55:0] roundRawFNToRecFN_io_in_pipe_b_sig; // @[Valid.scala:142:26]
wire [55:0] roundRawFNToRecFN_io_in_pipe_out_bits_sig = roundRawFNToRecFN_io_in_pipe_b_sig; // @[Valid.scala:135:21, :142:26]
reg roundRawFNToRecFN_io_roundingMode_pipe_v; // @[Valid.scala:141:24]
wire roundRawFNToRecFN_io_roundingMode_pipe_out_valid = roundRawFNToRecFN_io_roundingMode_pipe_v; // @[Valid.scala:135:21, :141:24]
reg [2:0] roundRawFNToRecFN_io_roundingMode_pipe_b; // @[Valid.scala:142:26]
wire [2:0] roundRawFNToRecFN_io_roundingMode_pipe_out_bits = roundRawFNToRecFN_io_roundingMode_pipe_b; // @[Valid.scala:135:21, :142:26]
reg roundRawFNToRecFN_io_detectTininess_pipe_v; // @[Valid.scala:141:24]
wire roundRawFNToRecFN_io_detectTininess_pipe_out_valid = roundRawFNToRecFN_io_detectTininess_pipe_v; // @[Valid.scala:135:21, :141:24]
reg roundRawFNToRecFN_io_detectTininess_pipe_b; // @[Valid.scala:142:26]
wire roundRawFNToRecFN_io_detectTininess_pipe_out_bits = roundRawFNToRecFN_io_detectTininess_pipe_b; // @[Valid.scala:135:21, :142:26]
reg io_validout_pipe_v; // @[Valid.scala:141:24]
assign io_validout_pipe_out_valid = io_validout_pipe_v; // @[Valid.scala:135:21, :141:24]
assign io_validout_0 = io_validout_pipe_out_valid; // @[Valid.scala:135:21]
always @(posedge clock) begin // @[FPU.scala:633:7]
if (reset) begin // @[FPU.scala:633:7]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v <= 1'h0; // @[Valid.scala:141:24]
mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v <= 1'h0; // @[Valid.scala:141:24]
mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v <= 1'h0; // @[Valid.scala:141:24]
roundingMode_stage0_pipe_v <= 1'h0; // @[Valid.scala:141:24]
detectTininess_stage0_pipe_v <= 1'h0; // @[Valid.scala:141:24]
valid_stage0_pipe_v <= 1'h0; // @[Valid.scala:141:24]
roundRawFNToRecFN_io_invalidExc_pipe_v <= 1'h0; // @[Valid.scala:141:24]
roundRawFNToRecFN_io_in_pipe_v <= 1'h0; // @[Valid.scala:141:24]
roundRawFNToRecFN_io_roundingMode_pipe_v <= 1'h0; // @[Valid.scala:141:24]
roundRawFNToRecFN_io_detectTininess_pipe_v <= 1'h0; // @[Valid.scala:141:24]
io_validout_pipe_v <= 1'h0; // @[Valid.scala:141:24]
end
else begin // @[FPU.scala:633:7]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v <= io_validin_0; // @[Valid.scala:141:24]
mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v <= io_validin_0; // @[Valid.scala:141:24]
mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v <= io_validin_0; // @[Valid.scala:141:24]
roundingMode_stage0_pipe_v <= io_validin_0; // @[Valid.scala:141:24]
detectTininess_stage0_pipe_v <= io_validin_0; // @[Valid.scala:141:24]
valid_stage0_pipe_v <= io_validin_0; // @[Valid.scala:141:24]
roundRawFNToRecFN_io_invalidExc_pipe_v <= valid_stage0; // @[Valid.scala:141:24]
roundRawFNToRecFN_io_in_pipe_v <= valid_stage0; // @[Valid.scala:141:24]
roundRawFNToRecFN_io_roundingMode_pipe_v <= valid_stage0; // @[Valid.scala:141:24]
roundRawFNToRecFN_io_detectTininess_pipe_v <= valid_stage0; // @[Valid.scala:141:24]
io_validout_pipe_v <= valid_stage0; // @[Valid.scala:141:24]
end
if (io_validin_0) begin // @[FPU.scala:633:7]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isSigNaNAny <= _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNAOrB <= _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfA <= _mulAddRecFNToRaw_preMul_io_toPostMul_isInfA; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroA <= _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfB <= _mulAddRecFNToRaw_preMul_io_toPostMul_isInfB; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroB <= _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_signProd <= _mulAddRecFNToRaw_preMul_io_toPostMul_signProd; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNC <= _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfC <= _mulAddRecFNToRaw_preMul_io_toPostMul_isInfC; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroC <= _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_sExpSum <= _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_doSubMags <= _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CIsDominant <= _mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CDom_CAlignDist <= _mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_highAlignedSigC <= _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_bit0AlignedSigC <= _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b <= mulAddResult; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b <= io_roundingMode_0; // @[Valid.scala:142:26]
roundingMode_stage0_pipe_b <= io_roundingMode_0; // @[Valid.scala:142:26]
end
if (valid_stage0) begin // @[FPU.scala:667:28]
roundRawFNToRecFN_io_invalidExc_pipe_b <= _mulAddRecFNToRaw_postMul_io_invalidExc; // @[Valid.scala:142:26]
roundRawFNToRecFN_io_in_pipe_b_isNaN <= _mulAddRecFNToRaw_postMul_io_rawOut_isNaN; // @[Valid.scala:142:26]
roundRawFNToRecFN_io_in_pipe_b_isInf <= _mulAddRecFNToRaw_postMul_io_rawOut_isInf; // @[Valid.scala:142:26]
roundRawFNToRecFN_io_in_pipe_b_isZero <= _mulAddRecFNToRaw_postMul_io_rawOut_isZero; // @[Valid.scala:142:26]
roundRawFNToRecFN_io_in_pipe_b_sign <= _mulAddRecFNToRaw_postMul_io_rawOut_sign; // @[Valid.scala:142:26]
roundRawFNToRecFN_io_in_pipe_b_sExp <= _mulAddRecFNToRaw_postMul_io_rawOut_sExp; // @[Valid.scala:142:26]
roundRawFNToRecFN_io_in_pipe_b_sig <= _mulAddRecFNToRaw_postMul_io_rawOut_sig; // @[Valid.scala:142:26]
roundRawFNToRecFN_io_roundingMode_pipe_b <= roundingMode_stage0; // @[Valid.scala:142:26]
end
roundRawFNToRecFN_io_detectTininess_pipe_b <= valid_stage0 | roundRawFNToRecFN_io_detectTininess_pipe_b; // @[Valid.scala:142:26]
always @(posedge)
MulAddRecFNToRaw_preMul_e11_s53_4 mulAddRecFNToRaw_preMul ( // @[FPU.scala:654:41]
.io_op (io_op_0), // @[FPU.scala:633:7]
.io_a (io_a_0), // @[FPU.scala:633:7]
.io_b (io_b_0), // @[FPU.scala:633:7]
.io_c (io_c_0), // @[FPU.scala:633:7]
.io_mulAddA (_mulAddRecFNToRaw_preMul_io_mulAddA),
.io_mulAddB (_mulAddRecFNToRaw_preMul_io_mulAddB),
.io_mulAddC (_mulAddRecFNToRaw_preMul_io_mulAddC),
.io_toPostMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny),
.io_toPostMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB),
.io_toPostMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA),
.io_toPostMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA),
.io_toPostMul_isInfB (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfB),
.io_toPostMul_isZeroB (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB),
.io_toPostMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd),
.io_toPostMul_isNaNC (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC),
.io_toPostMul_isInfC (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfC),
.io_toPostMul_isZeroC (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC),
.io_toPostMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum),
.io_toPostMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags),
.io_toPostMul_CIsDominant (_mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant),
.io_toPostMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist),
.io_toPostMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC),
.io_toPostMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC)
); // @[FPU.scala:654:41]
MulAddRecFNToRaw_postMul_e11_s53_4 mulAddRecFNToRaw_postMul ( // @[FPU.scala:655:42]
.io_fromPreMul_isSigNaNAny (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isSigNaNAny), // @[Valid.scala:135:21]
.io_fromPreMul_isNaNAOrB (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isNaNAOrB), // @[Valid.scala:135:21]
.io_fromPreMul_isInfA (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfA), // @[Valid.scala:135:21]
.io_fromPreMul_isZeroA (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroA), // @[Valid.scala:135:21]
.io_fromPreMul_isInfB (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfB), // @[Valid.scala:135:21]
.io_fromPreMul_isZeroB (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroB), // @[Valid.scala:135:21]
.io_fromPreMul_signProd (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_signProd), // @[Valid.scala:135:21]
.io_fromPreMul_isNaNC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isNaNC), // @[Valid.scala:135:21]
.io_fromPreMul_isInfC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfC), // @[Valid.scala:135:21]
.io_fromPreMul_isZeroC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroC), // @[Valid.scala:135:21]
.io_fromPreMul_sExpSum (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_sExpSum), // @[Valid.scala:135:21]
.io_fromPreMul_doSubMags (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_doSubMags), // @[Valid.scala:135:21]
.io_fromPreMul_CIsDominant (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_CIsDominant), // @[Valid.scala:135:21]
.io_fromPreMul_CDom_CAlignDist (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_CDom_CAlignDist), // @[Valid.scala:135:21]
.io_fromPreMul_highAlignedSigC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_highAlignedSigC), // @[Valid.scala:135:21]
.io_fromPreMul_bit0AlignedSigC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_bit0AlignedSigC), // @[Valid.scala:135:21]
.io_mulAddResult (mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out_bits), // @[Valid.scala:135:21]
.io_roundingMode (mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out_bits), // @[Valid.scala:135:21]
.io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc),
.io_rawOut_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN),
.io_rawOut_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf),
.io_rawOut_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero),
.io_rawOut_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign),
.io_rawOut_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp),
.io_rawOut_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig)
); // @[FPU.scala:655:42]
RoundRawFNToRecFN_e11_s53_8 roundRawFNToRecFN ( // @[FPU.scala:682:35]
.io_invalidExc (roundRawFNToRecFN_io_invalidExc_pipe_out_bits), // @[Valid.scala:135:21]
.io_in_isNaN (roundRawFNToRecFN_io_in_pipe_out_bits_isNaN), // @[Valid.scala:135:21]
.io_in_isInf (roundRawFNToRecFN_io_in_pipe_out_bits_isInf), // @[Valid.scala:135:21]
.io_in_isZero (roundRawFNToRecFN_io_in_pipe_out_bits_isZero), // @[Valid.scala:135:21]
.io_in_sign (roundRawFNToRecFN_io_in_pipe_out_bits_sign), // @[Valid.scala:135:21]
.io_in_sExp (roundRawFNToRecFN_io_in_pipe_out_bits_sExp), // @[Valid.scala:135:21]
.io_in_sig (roundRawFNToRecFN_io_in_pipe_out_bits_sig), // @[Valid.scala:135:21]
.io_roundingMode (roundRawFNToRecFN_io_roundingMode_pipe_out_bits), // @[Valid.scala:135:21]
.io_detectTininess (roundRawFNToRecFN_io_detectTininess_pipe_out_bits), // @[Valid.scala:135:21]
.io_out (io_out_0),
.io_exceptionFlags (io_exceptionFlags_0)
); // @[FPU.scala:682:35]
assign io_out = io_out_0; // @[FPU.scala:633:7]
assign io_exceptionFlags = io_exceptionFlags_0; // @[FPU.scala:633:7]
assign io_validout = io_validout_0; // @[FPU.scala:633:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
package constellation.channel
import chisel3._
import chisel3.util._
import freechips.rocketchip.diplomacy._
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.util._
import constellation.noc.{HasNoCParams}
class NoCMonitor(val cParam: ChannelParams)(implicit val p: Parameters) extends Module with HasNoCParams {
val io = IO(new Bundle {
val in = Input(new Channel(cParam))
})
val in_flight = RegInit(VecInit(Seq.fill(cParam.nVirtualChannels) { false.B }))
for (i <- 0 until cParam.srcSpeedup) {
val flit = io.in.flit(i)
when (flit.valid) {
when (flit.bits.head) {
in_flight(flit.bits.virt_channel_id) := true.B
assert (!in_flight(flit.bits.virt_channel_id), "Flit head/tail sequencing is broken")
}
when (flit.bits.tail) {
in_flight(flit.bits.virt_channel_id) := false.B
}
}
val possibleFlows = cParam.possibleFlows
when (flit.valid && flit.bits.head) {
cParam match {
case n: ChannelParams => n.virtualChannelParams.zipWithIndex.foreach { case (v,i) =>
assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)
}
case _ => assert(cParam.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)
}
}
}
}
File Types.scala:
package constellation.routing
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Parameters}
import constellation.noc.{HasNoCParams}
import constellation.channel.{Flit}
/** A representation for 1 specific virtual channel in wormhole routing
*
* @param src the source node
* @param vc ID for the virtual channel
* @param dst the destination node
* @param n_vc the number of virtual channels
*/
// BEGIN: ChannelRoutingInfo
case class ChannelRoutingInfo(
src: Int,
dst: Int,
vc: Int,
n_vc: Int
) {
// END: ChannelRoutingInfo
require (src >= -1 && dst >= -1 && vc >= 0, s"Illegal $this")
require (!(src == -1 && dst == -1), s"Illegal $this")
require (vc < n_vc, s"Illegal $this")
val isIngress = src == -1
val isEgress = dst == -1
}
/** Represents the properties of a packet that are relevant for routing
* ingressId and egressId uniquely identify a flow, but vnet and dst are used here
* to simplify the implementation of routingrelations
*
* @param ingressId packet's source ingress point
* @param egressId packet's destination egress point
* @param vNet virtual subnetwork identifier
* @param dst packet's destination node ID
*/
// BEGIN: FlowRoutingInfo
case class FlowRoutingInfo(
ingressId: Int,
egressId: Int,
vNetId: Int,
ingressNode: Int,
ingressNodeId: Int,
egressNode: Int,
egressNodeId: Int,
fifo: Boolean
) {
// END: FlowRoutingInfo
def isFlow(f: FlowRoutingBundle): Bool = {
(f.ingress_node === ingressNode.U &&
f.egress_node === egressNode.U &&
f.ingress_node_id === ingressNodeId.U &&
f.egress_node_id === egressNodeId.U)
}
def asLiteral(b: FlowRoutingBundle): BigInt = {
Seq(
(vNetId , b.vnet_id),
(ingressNode , b.ingress_node),
(ingressNodeId , b.ingress_node_id),
(egressNode , b.egress_node),
(egressNodeId , b.egress_node_id)
).foldLeft(0)((l, t) => {
(l << t._2.getWidth) | t._1
})
}
}
class FlowRoutingBundle(implicit val p: Parameters) extends Bundle with HasNoCParams {
// Instead of tracking ingress/egress ID, track the physical destination id and the offset at the destination
// This simplifies the routing tables
val vnet_id = UInt(log2Ceil(nVirtualNetworks).W)
val ingress_node = UInt(log2Ceil(nNodes).W)
val ingress_node_id = UInt(log2Ceil(maxIngressesAtNode).W)
val egress_node = UInt(log2Ceil(nNodes).W)
val egress_node_id = UInt(log2Ceil(maxEgressesAtNode).W)
}
| module NoCMonitor( // @[Monitor.scala:11:7]
input clock, // @[Monitor.scala:11:7]
input reset, // @[Monitor.scala:11:7]
input io_in_flit_0_valid, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_head, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14]
input [4:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14]
input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14]
input [4:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14]
input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14]
input [2:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14]
);
reg in_flight_0; // @[Monitor.scala:16:26]
reg in_flight_1; // @[Monitor.scala:16:26]
reg in_flight_2; // @[Monitor.scala:16:26]
reg in_flight_3; // @[Monitor.scala:16:26]
reg in_flight_4; // @[Monitor.scala:16:26]
reg in_flight_5; // @[Monitor.scala:16:26]
reg in_flight_6; // @[Monitor.scala:16:26]
reg in_flight_7; // @[Monitor.scala:16:26]
wire _GEN = io_in_flit_0_bits_virt_channel_id == 3'h0; // @[Monitor.scala:21:46] |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Bundles.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import freechips.rocketchip.util._
import scala.collection.immutable.ListMap
import chisel3.util.Decoupled
import chisel3.util.DecoupledIO
import chisel3.reflect.DataMirror
abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle
// common combos in lazy policy:
// Put + Acquire
// Release + AccessAck
object TLMessages
{
// A B C D E
def PutFullData = 0.U // . . => AccessAck
def PutPartialData = 1.U // . . => AccessAck
def ArithmeticData = 2.U // . . => AccessAckData
def LogicalData = 3.U // . . => AccessAckData
def Get = 4.U // . . => AccessAckData
def Hint = 5.U // . . => HintAck
def AcquireBlock = 6.U // . => Grant[Data]
def AcquirePerm = 7.U // . => Grant[Data]
def Probe = 6.U // . => ProbeAck[Data]
def AccessAck = 0.U // . .
def AccessAckData = 1.U // . .
def HintAck = 2.U // . .
def ProbeAck = 4.U // .
def ProbeAckData = 5.U // .
def Release = 6.U // . => ReleaseAck
def ReleaseData = 7.U // . => ReleaseAck
def Grant = 4.U // . => GrantAck
def GrantData = 5.U // . => GrantAck
def ReleaseAck = 6.U // .
def GrantAck = 0.U // .
def isA(x: UInt) = x <= AcquirePerm
def isB(x: UInt) = x <= Probe
def isC(x: UInt) = x <= ReleaseData
def isD(x: UInt) = x <= ReleaseAck
def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant)
def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck)
def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("AcquireBlock",TLPermissions.PermMsgGrow),
("AcquirePerm",TLPermissions.PermMsgGrow))
def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("Probe",TLPermissions.PermMsgCap))
def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("ProbeAck",TLPermissions.PermMsgReport),
("ProbeAckData",TLPermissions.PermMsgReport),
("Release",TLPermissions.PermMsgReport),
("ReleaseData",TLPermissions.PermMsgReport))
def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("Grant",TLPermissions.PermMsgCap),
("GrantData",TLPermissions.PermMsgCap),
("ReleaseAck",TLPermissions.PermMsgReserved))
}
/**
* The three primary TileLink permissions are:
* (T)runk: the agent is (or is on inwards path to) the global point of serialization.
* (B)ranch: the agent is on an outwards path to
* (N)one:
* These permissions are permuted by transfer operations in various ways.
* Operations can cap permissions, request for them to be grown or shrunk,
* or for a report on their current status.
*/
object TLPermissions
{
val aWidth = 2
val bdWidth = 2
val cWidth = 3
// Cap types (Grant = new permissions, Probe = permisions <= target)
def toT = 0.U(bdWidth.W)
def toB = 1.U(bdWidth.W)
def toN = 2.U(bdWidth.W)
def isCap(x: UInt) = x <= toN
// Grow types (Acquire = permissions >= target)
def NtoB = 0.U(aWidth.W)
def NtoT = 1.U(aWidth.W)
def BtoT = 2.U(aWidth.W)
def isGrow(x: UInt) = x <= BtoT
// Shrink types (ProbeAck, Release)
def TtoB = 0.U(cWidth.W)
def TtoN = 1.U(cWidth.W)
def BtoN = 2.U(cWidth.W)
def isShrink(x: UInt) = x <= BtoN
// Report types (ProbeAck, Release)
def TtoT = 3.U(cWidth.W)
def BtoB = 4.U(cWidth.W)
def NtoN = 5.U(cWidth.W)
def isReport(x: UInt) = x <= NtoN
def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT")
def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN")
def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN")
def PermMsgReserved:Seq[String] = Seq("Reserved")
}
object TLAtomics
{
val width = 3
// Arithmetic types
def MIN = 0.U(width.W)
def MAX = 1.U(width.W)
def MINU = 2.U(width.W)
def MAXU = 3.U(width.W)
def ADD = 4.U(width.W)
def isArithmetic(x: UInt) = x <= ADD
// Logical types
def XOR = 0.U(width.W)
def OR = 1.U(width.W)
def AND = 2.U(width.W)
def SWAP = 3.U(width.W)
def isLogical(x: UInt) = x <= SWAP
def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD")
def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP")
}
object TLHints
{
val width = 1
def PREFETCH_READ = 0.U(width.W)
def PREFETCH_WRITE = 1.U(width.W)
def isHints(x: UInt) = x <= PREFETCH_WRITE
def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite")
}
sealed trait TLChannel extends TLBundleBase {
val channelName: String
}
sealed trait TLDataChannel extends TLChannel
sealed trait TLAddrChannel extends TLDataChannel
final class TLBundleA(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleA_${params.shortName}"
val channelName = "'A' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleB(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleB_${params.shortName}"
val channelName = "'B' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val address = UInt(params.addressBits.W) // from
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleC(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleC_${params.shortName}"
val channelName = "'C' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.cWidth.W) // shrink or report perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleD(params: TLBundleParameters)
extends TLBundleBase(params) with TLDataChannel
{
override def typeName = s"TLBundleD_${params.shortName}"
val channelName = "'D' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val sink = UInt(params.sinkBits.W) // from
val denied = Bool() // implies corrupt iff *Data
val user = BundleMap(params.responseFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleE(params: TLBundleParameters)
extends TLBundleBase(params) with TLChannel
{
override def typeName = s"TLBundleE_${params.shortName}"
val channelName = "'E' channel"
val sink = UInt(params.sinkBits.W) // to
}
class TLBundle(val params: TLBundleParameters) extends Record
{
// Emulate a Bundle with elements abcde or ad depending on params.hasBCE
private val optA = Some (Decoupled(new TLBundleA(params)))
private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params))))
private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params)))
private val optD = Some (Flipped(Decoupled(new TLBundleD(params))))
private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params)))
def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params)))))
def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params)))))
def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params)))))
def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params)))))
def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params)))))
val elements =
if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a)
else ListMap("d" -> d, "a" -> a)
def tieoff(): Unit = {
DataMirror.specifiedDirectionOf(a.ready) match {
case SpecifiedDirection.Input =>
a.ready := false.B
c.ready := false.B
e.ready := false.B
b.valid := false.B
d.valid := false.B
case SpecifiedDirection.Output =>
a.valid := false.B
c.valid := false.B
e.valid := false.B
b.ready := false.B
d.ready := false.B
case _ =>
}
}
}
object TLBundle
{
def apply(params: TLBundleParameters) = new TLBundle(params)
}
class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle
class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params)
{
val a = new AsyncBundle(new TLBundleA(params.base), params.async)
val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async))
val c = new AsyncBundle(new TLBundleC(params.base), params.async)
val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async))
val e = new AsyncBundle(new TLBundleE(params.base), params.async)
}
class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = RationalIO(new TLBundleA(params))
val b = Flipped(RationalIO(new TLBundleB(params)))
val c = RationalIO(new TLBundleC(params))
val d = Flipped(RationalIO(new TLBundleD(params)))
val e = RationalIO(new TLBundleE(params))
}
class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = CreditedIO(new TLBundleA(params))
val b = Flipped(CreditedIO(new TLBundleB(params)))
val c = CreditedIO(new TLBundleC(params))
val d = Flipped(CreditedIO(new TLBundleD(params)))
val e = CreditedIO(new TLBundleE(params))
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor_34( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [27:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [10:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [10:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [27:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [10:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10]
wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire a_first_count = 1'h0; // @[Edges.scala:234:25]
wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count = 1'h0; // @[Edges.scala:234:25]
wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25]
wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27]
wire c_first_count = 1'h0; // @[Edges.scala:234:25]
wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21]
wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67]
wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last = 1'h1; // @[Edges.scala:232:33]
wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33]
wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28]
wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7]
wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_first_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_first_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_first_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_first_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_set_wo_ready_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_set_wo_ready_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_opcodes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_opcodes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_sizes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_sizes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_opcodes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_opcodes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_sizes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_sizes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_probe_ack_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_probe_ack_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_probe_ack_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_probe_ack_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _same_cycle_resp_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _same_cycle_resp_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _same_cycle_resp_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _same_cycle_resp_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _same_cycle_resp_WIRE_4_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _same_cycle_resp_WIRE_5_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_first_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_first_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_first_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_first_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_set_wo_ready_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_set_wo_ready_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_opcodes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_opcodes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_sizes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_sizes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_opcodes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_opcodes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_sizes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_sizes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_probe_ack_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_probe_ack_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_probe_ack_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_probe_ack_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _same_cycle_resp_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _same_cycle_resp_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _same_cycle_resp_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _same_cycle_resp_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _same_cycle_resp_WIRE_4_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _same_cycle_resp_WIRE_5_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46]
wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [16385:0] _c_sizes_set_T_1 = 16386'h0; // @[Monitor.scala:768:52]
wire [13:0] _c_opcodes_set_T = 14'h0; // @[Monitor.scala:767:79]
wire [13:0] _c_sizes_set_T = 14'h0; // @[Monitor.scala:768:77]
wire [16386:0] _c_opcodes_set_T_1 = 16387'h0; // @[Monitor.scala:767:54]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [2047:0] _c_set_wo_ready_T = 2048'h1; // @[OneHot.scala:58:35]
wire [2047:0] _c_set_T = 2048'h1; // @[OneHot.scala:58:35]
wire [4159:0] c_opcodes_set = 4160'h0; // @[Monitor.scala:740:34]
wire [4159:0] c_sizes_set = 4160'h0; // @[Monitor.scala:741:34]
wire [1039:0] c_set = 1040'h0; // @[Monitor.scala:738:34]
wire [1039:0] c_set_wo_ready = 1040'h0; // @[Monitor.scala:739:34]
wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76]
wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [10:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_4 = source_ok_uncommonBits < 11'h410; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31]
wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [27:0] _is_aligned_T = {25'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 28'h0; // @[Edges.scala:21:{16,24}]
wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [10:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}]
wire [10:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_10 = source_ok_uncommonBits_1 < 11'h410; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31]
wire _T_672 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_672; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_672; // @[Decoupled.scala:51:35]
wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
reg a_first_counter; // @[Edges.scala:229:27]
wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28]
wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25]
wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [1:0] size; // @[Monitor.scala:389:22]
reg [10:0] source; // @[Monitor.scala:390:22]
reg [27:0] address; // @[Monitor.scala:391:22]
wire _T_745 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_745; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_745; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_745; // @[Decoupled.scala:51:35]
wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35]
wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
reg d_first_counter; // @[Edges.scala:229:27]
wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28]
wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] size_1; // @[Monitor.scala:540:22]
reg [10:0] source_1; // @[Monitor.scala:541:22]
reg [1039:0] inflight; // @[Monitor.scala:614:27]
reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33]
wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
reg a_first_counter_1; // @[Edges.scala:229:27]
wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28]
wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25]
wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
reg d_first_counter_1; // @[Edges.scala:229:27]
wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28]
wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire [1039:0] a_set; // @[Monitor.scala:626:34]
wire [1039:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [4159:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [4159:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [13:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [13:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [13:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [13:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [13:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [13:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [13:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [13:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [13:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [4159:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [4159:0] _a_opcode_lookup_T_6 = {4156'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [4159:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [4159:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [4159:0] _a_size_lookup_T_6 = {4156'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [4159:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[4159:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [2047:0] _GEN_2 = 2048'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [2047:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [2047:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire _T_598 = _T_672 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_598 ? _a_set_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [13:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [13:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [13:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [16386:0] _a_opcodes_set_T_1 = {16383'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [16385:0] _a_sizes_set_T_1 = {16383'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [1039:0] d_clr; // @[Monitor.scala:664:34]
wire [1039:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [4159:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [4159:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [2047:0] _GEN_5 = 2048'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [2047:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [2047:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [2047:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [2047:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire _T_613 = _T_745 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_613 ? _d_clr_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire [16398:0] _d_opcodes_clr_T_5 = 16399'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [16398:0] _d_sizes_clr_T_5 = 16399'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [1039:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [1039:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [1039:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [4159:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [4159:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [4159:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [4159:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [4159:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [4159:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [1039:0] inflight_1; // @[Monitor.scala:726:35]
wire [1039:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [4159:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [4159:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [4159:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
reg d_first_counter_2; // @[Edges.scala:229:27]
wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28]
wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [4159:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [4159:0] _c_opcode_lookup_T_6 = {4156'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [4159:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [4159:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [4159:0] _c_size_lookup_T_6 = {4156'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [4159:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[4159:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [1039:0] d_clr_1; // @[Monitor.scala:774:34]
wire [1039:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [4159:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [4159:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_716 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_716 & d_release_ack_1 ? _d_clr_wo_ready_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire _T_698 = _T_745 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_698 ? _d_clr_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire [16398:0] _d_opcodes_clr_T_11 = 16399'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_698 ? _d_opcodes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [16398:0] _d_sizes_clr_T_11 = 16399'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_698 ? _d_sizes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 11'h0; // @[Monitor.scala:36:7, :795:113]
wire [1039:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [1039:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [4159:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [4159:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [4159:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [4159:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to the following Chisel files.
File PE.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle {
val dataflow = UInt(1.W) // TODO make this an Enum
val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)?
val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats
}
class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module {
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(inputType)
val in_c = Input(cType)
val out_d = Output(dType)
})
io.out_d := io.in_c.mac(io.in_a, io.in_b)
}
// TODO update documentation
/**
* A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh.
* @param width Data width of operands
*/
class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int)
(implicit ev: Arithmetic[T]) extends Module { // Debugging variables
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(outputType)
val in_d = Input(outputType)
val out_a = Output(inputType)
val out_b = Output(outputType)
val out_c = Output(outputType)
val in_control = Input(new PEControl(accType))
val out_control = Output(new PEControl(accType))
val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W))
val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W))
val in_last = Input(Bool())
val out_last = Output(Bool())
val in_valid = Input(Bool())
val out_valid = Output(Bool())
val bad_dataflow = Output(Bool())
})
val cType = if (df == Dataflow.WS) inputType else accType
// When creating PEs that support multiple dataflows, the
// elaboration/synthesis tools often fail to consolidate and de-duplicate
// MAC units. To force mac circuitry to be re-used, we create a "mac_unit"
// module here which just performs a single MAC operation
val mac_unit = Module(new MacUnit(inputType,
if (df == Dataflow.WS) outputType else accType, outputType))
val a = io.in_a
val b = io.in_b
val d = io.in_d
val c1 = Reg(cType)
val c2 = Reg(cType)
val dataflow = io.in_control.dataflow
val prop = io.in_control.propagate
val shift = io.in_control.shift
val id = io.in_id
val last = io.in_last
val valid = io.in_valid
io.out_a := a
io.out_control.dataflow := dataflow
io.out_control.propagate := prop
io.out_control.shift := shift
io.out_id := id
io.out_last := last
io.out_valid := valid
mac_unit.io.in_a := a
val last_s = RegEnable(prop, valid)
val flip = last_s =/= prop
val shift_offset = Mux(flip, shift, 0.U)
// Which dataflow are we using?
val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W)
val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W)
// Is c1 being computed on, or propagated forward (in the output-stationary dataflow)?
val COMPUTE = 0.U(1.W)
val PROPAGATE = 1.U(1.W)
io.bad_dataflow := false.B
when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
c2 := mac_unit.io.out_d
c1 := d.withWidthOf(cType)
}.otherwise {
io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c1
c1 := mac_unit.io.out_d
c2 := d.withWidthOf(cType)
}
}.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := c1
mac_unit.io.in_b := c2.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c1 := d
}.otherwise {
io.out_c := c2
mac_unit.io.in_b := c1.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c2 := d
}
}.otherwise {
io.bad_dataflow := true.B
//assert(false.B, "unknown dataflow")
io.out_c := DontCare
io.out_b := DontCare
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
}
when (!valid) {
c1 := c1
c2 := c2
mac_unit.io.in_b := DontCare
mac_unit.io.in_c := DontCare
}
}
File Arithmetic.scala:
// A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own:
// implicit MyTypeArithmetic extends Arithmetic[MyType] { ... }
package gemmini
import chisel3._
import chisel3.util._
import hardfloat._
// Bundles that represent the raw bits of custom datatypes
case class Float(expWidth: Int, sigWidth: Int) extends Bundle {
val bits = UInt((expWidth + sigWidth).W)
val bias: Int = (1 << (expWidth-1)) - 1
}
case class DummySInt(w: Int) extends Bundle {
val bits = UInt(w.W)
def dontCare: DummySInt = {
val o = Wire(new DummySInt(w))
o.bits := 0.U
o
}
}
// The Arithmetic typeclass which implements various arithmetic operations on custom datatypes
abstract class Arithmetic[T <: Data] {
implicit def cast(t: T): ArithmeticOps[T]
}
abstract class ArithmeticOps[T <: Data](self: T) {
def *(t: T): T
def mac(m1: T, m2: T): T // Returns (m1 * m2 + self)
def +(t: T): T
def -(t: T): T
def >>(u: UInt): T // This is a rounding shift! Rounds away from 0
def >(t: T): Bool
def identity: T
def withWidthOf(t: T): T
def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates
def relu: T
def zero: T
def minimum: T
// Optional parameters, which only need to be defined if you want to enable various optimizations for transformers
def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None
def mult_with_reciprocal[U <: Data](reciprocal: U) = self
}
object Arithmetic {
implicit object UIntArithmetic extends Arithmetic[UInt] {
override implicit def cast(self: UInt) = new ArithmeticOps(self) {
override def *(t: UInt) = self * t
override def mac(m1: UInt, m2: UInt) = m1 * m2 + self
override def +(t: UInt) = self + t
override def -(t: UInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = point_five & (zeros | ones_digit)
(self >> u).asUInt + r
}
override def >(t: UInt): Bool = self > t
override def withWidthOf(t: UInt) = self.asTypeOf(t)
override def clippedToWidthOf(t: UInt) = {
val sat = ((1 << (t.getWidth-1))-1).U
Mux(self > sat, sat, self)(t.getWidth-1, 0)
}
override def relu: UInt = self
override def zero: UInt = 0.U
override def identity: UInt = 1.U
override def minimum: UInt = 0.U
}
}
implicit object SIntArithmetic extends Arithmetic[SInt] {
override implicit def cast(self: SInt) = new ArithmeticOps(self) {
override def *(t: SInt) = self * t
override def mac(m1: SInt, m2: SInt) = m1 * m2 + self
override def +(t: SInt) = self + t
override def -(t: SInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = (point_five & (zeros | ones_digit)).asBool
(self >> u).asSInt + Mux(r, 1.S, 0.S)
}
override def >(t: SInt): Bool = self > t
override def withWidthOf(t: SInt) = {
if (self.getWidth >= t.getWidth)
self(t.getWidth-1, 0).asSInt
else {
val sign_bits = t.getWidth - self.getWidth
val sign = self(self.getWidth-1)
Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t)
}
}
override def clippedToWidthOf(t: SInt): SInt = {
val maxsat = ((1 << (t.getWidth-1))-1).S
val minsat = (-(1 << (t.getWidth-1))).S
MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt
}
override def relu: SInt = Mux(self >= 0.S, self, 0.S)
override def zero: SInt = 0.S
override def identity: SInt = 1.S
override def minimum: SInt = (-(1 << (self.getWidth-1))).S
override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(denom_t.cloneType))
val output = Wire(Decoupled(self.cloneType))
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def sin_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def uin_to_float(x: UInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := x
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = sin_to_float(self)
val denom_rec = uin_to_float(input.bits)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := self_rec
divider.io.b := denom_rec
divider.io.roundingMode := consts.round_minMag
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := float_to_in(divider.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(self.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
// Instantiate the hardloat sqrt
val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0))
input.ready := sqrter.io.inReady
sqrter.io.inValid := input.valid
sqrter.io.sqrtOp := true.B
sqrter.io.a := self_rec
sqrter.io.b := DontCare
sqrter.io.roundingMode := consts.round_minMag
sqrter.io.detectTininess := consts.tininess_afterRounding
output.valid := sqrter.io.outValid_sqrt
output.bits := float_to_in(sqrter.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match {
case Float(expWidth, sigWidth) =>
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(u.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
val self_rec = in_to_float(self)
val one_rec = in_to_float(1.S)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := one_rec
divider.io.b := self_rec
divider.io.roundingMode := consts.round_near_even
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u)
assert(!output.valid || output.ready)
Some((input, output))
case _ => None
}
override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match {
case recip @ Float(expWidth, sigWidth) =>
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits)
// Instantiate the hardloat divider
val muladder = Module(new MulRecFN(expWidth, sigWidth))
muladder.io.roundingMode := consts.round_near_even
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := reciprocal_rec
float_to_in(muladder.io.out)
case _ => self
}
}
}
implicit object FloatArithmetic extends Arithmetic[Float] {
// TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array
override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) {
override def *(t: Float): Float = {
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := t_rec_resized
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def mac(m1: Float, m2: Float): Float = {
// Recode all operands
val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits)
val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize m1 to self's width
val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth))
m1_resizer.io.in := m1_rec
m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m1_resizer.io.detectTininess := consts.tininess_afterRounding
val m1_rec_resized = m1_resizer.io.out
// Resize m2 to self's width
val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth))
m2_resizer.io.in := m2_rec
m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m2_resizer.io.detectTininess := consts.tininess_afterRounding
val m2_rec_resized = m2_resizer.io.out
// Perform multiply-add
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := m1_rec_resized
muladder.io.b := m2_rec_resized
muladder.io.c := self_rec
// Convert result to standard format // TODO remove these intermediate recodings
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def +(t: Float): Float = {
require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Generate 1 as a float
val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := 1.U
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
val one_rec = in_to_rec_fn.io.out
// Resize t
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
// Perform addition
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := t_rec_resized
muladder.io.b := one_rec
muladder.io.c := self_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def -(t: Float): Float = {
val t_sgn = t.bits(t.getWidth-1)
val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t)
self + neg_t
}
override def >>(u: UInt): Float = {
// Recode self
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Get 2^(-u) as a recoded float
val shift_exp = Wire(UInt(self.expWidth.W))
shift_exp := self.bias.U - u
val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W))
val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn)
assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported")
// Multiply self and 2^(-u)
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := shift_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def >(t: Float): Bool = {
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize t to self's width
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth))
comparator.io.a := self_rec
comparator.io.b := t_rec_resized
comparator.io.signaling := false.B
comparator.io.gt
}
override def withWidthOf(t: Float): Float = {
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def clippedToWidthOf(t: Float): Float = {
// TODO check for overflow. Right now, we just assume that overflow doesn't happen
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def relu: Float = {
val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits)
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits)
result
}
override def zero: Float = 0.U.asTypeOf(self)
override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
}
}
implicit object DummySIntArithmetic extends Arithmetic[DummySInt] {
override implicit def cast(self: DummySInt) = new ArithmeticOps(self) {
override def *(t: DummySInt) = self.dontCare
override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare
override def +(t: DummySInt) = self.dontCare
override def -(t: DummySInt) = self.dontCare
override def >>(t: UInt) = self.dontCare
override def >(t: DummySInt): Bool = false.B
override def identity = self.dontCare
override def withWidthOf(t: DummySInt) = self.dontCare
override def clippedToWidthOf(t: DummySInt) = self.dontCare
override def relu = self.dontCare
override def zero = self.dontCare
override def minimum: DummySInt = self.dontCare
}
}
}
| module PE_442( // @[PE.scala:31:7]
input clock, // @[PE.scala:31:7]
input reset, // @[PE.scala:31:7]
input [7:0] io_in_a, // @[PE.scala:35:14]
input [19:0] io_in_b, // @[PE.scala:35:14]
input [19:0] io_in_d, // @[PE.scala:35:14]
output [7:0] io_out_a, // @[PE.scala:35:14]
output [19:0] io_out_b, // @[PE.scala:35:14]
output [19:0] io_out_c, // @[PE.scala:35:14]
input io_in_control_dataflow, // @[PE.scala:35:14]
input io_in_control_propagate, // @[PE.scala:35:14]
input [4:0] io_in_control_shift, // @[PE.scala:35:14]
output io_out_control_dataflow, // @[PE.scala:35:14]
output io_out_control_propagate, // @[PE.scala:35:14]
output [4:0] io_out_control_shift, // @[PE.scala:35:14]
input [2:0] io_in_id, // @[PE.scala:35:14]
output [2:0] io_out_id, // @[PE.scala:35:14]
input io_in_last, // @[PE.scala:35:14]
output io_out_last, // @[PE.scala:35:14]
input io_in_valid, // @[PE.scala:35:14]
output io_out_valid, // @[PE.scala:35:14]
output io_bad_dataflow // @[PE.scala:35:14]
);
wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24]
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7]
wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7]
wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7]
wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7]
wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7]
wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7]
wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7]
wire io_in_last_0 = io_in_last; // @[PE.scala:31:7]
wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7]
wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7]
wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7]
wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37]
wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37]
wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35]
wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7]
wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7]
wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7]
wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7]
wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7]
wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7]
wire [19:0] io_out_b_0; // @[PE.scala:31:7]
wire [19:0] io_out_c_0; // @[PE.scala:31:7]
reg [31:0] c1; // @[PE.scala:70:15]
wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15]
wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38]
reg [31:0] c2; // @[PE.scala:71:15]
wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15]
wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38]
reg last_s; // @[PE.scala:89:25]
wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21]
wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25]
wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25]
wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32]
wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32]
wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25]
wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15]
wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}]
wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25]
wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27]
wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27]
wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25]
wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15]
wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15]
assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37]
wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37]
wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61]
wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15]
wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}]
wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15]
wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15]
assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37]
wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37]
wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61]
wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38]
wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38]
wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38]
wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38]
assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16]
assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101]
wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35]
wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35]
wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10]
wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10]
always @(posedge clock) begin // @[PE.scala:31:7]
if (io_in_valid_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10]
c1 <= _GEN_7; // @[PE.scala:70:15, :124:10]
if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30]
end
else // @[PE.scala:71:15, :118:101, :119:30]
c2 <= _GEN_7; // @[PE.scala:71:15, :124:10]
end
else begin // @[PE.scala:31:7]
c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10]
c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10]
end
last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25]
end
always @(posedge)
MacUnit_186 mac_unit ( // @[PE.scala:64:24]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0), // @[PE.scala:31:7]
.io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}]
.io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24]
.io_out_d (_mac_unit_io_out_d)
); // @[PE.scala:64:24]
assign io_out_a = io_out_a_0; // @[PE.scala:31:7]
assign io_out_b = io_out_b_0; // @[PE.scala:31:7]
assign io_out_c = io_out_c_0; // @[PE.scala:31:7]
assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7]
assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7]
assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7]
assign io_out_id = io_out_id_0; // @[PE.scala:31:7]
assign io_out_last = io_out_last_0; // @[PE.scala:31:7]
assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7]
assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File primitives.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object lowMask
{
def apply(in: UInt, topBound: BigInt, bottomBound: BigInt): UInt =
{
require(topBound != bottomBound)
val numInVals = BigInt(1)<<in.getWidth
if (topBound < bottomBound) {
lowMask(~in, numInVals - 1 - topBound, numInVals - 1 - bottomBound)
} else if (numInVals > 64 /* Empirical */) {
// For simulation performance, we should avoid generating
// exteremely wide shifters, so we divide and conquer.
// Empirically, this does not impact synthesis QoR.
val mid = numInVals / 2
val msb = in(in.getWidth - 1)
val lsbs = in(in.getWidth - 2, 0)
if (mid < topBound) {
if (mid <= bottomBound) {
Mux(msb,
lowMask(lsbs, topBound - mid, bottomBound - mid),
0.U
)
} else {
Mux(msb,
lowMask(lsbs, topBound - mid, 0) ## ((BigInt(1)<<(mid - bottomBound).toInt) - 1).U,
lowMask(lsbs, mid, bottomBound)
)
}
} else {
~Mux(msb, 0.U, ~lowMask(lsbs, topBound, bottomBound))
}
} else {
val shift = (BigInt(-1)<<numInVals.toInt).S>>in
Reverse(
shift(
(numInVals - 1 - bottomBound).toInt,
(numInVals - topBound).toInt
)
)
}
}
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object countLeadingZeros
{
def apply(in: UInt): UInt = PriorityEncoder(in.asBools.reverse)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object orReduceBy2
{
def apply(in: UInt): UInt =
{
val reducedWidth = (in.getWidth + 1)>>1
val reducedVec = Wire(Vec(reducedWidth, Bool()))
for (ix <- 0 until reducedWidth - 1) {
reducedVec(ix) := in(ix * 2 + 1, ix * 2).orR
}
reducedVec(reducedWidth - 1) :=
in(in.getWidth - 1, (reducedWidth - 1) * 2).orR
reducedVec.asUInt
}
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object orReduceBy4
{
def apply(in: UInt): UInt =
{
val reducedWidth = (in.getWidth + 3)>>2
val reducedVec = Wire(Vec(reducedWidth, Bool()))
for (ix <- 0 until reducedWidth - 1) {
reducedVec(ix) := in(ix * 4 + 3, ix * 4).orR
}
reducedVec(reducedWidth - 1) :=
in(in.getWidth - 1, (reducedWidth - 1) * 4).orR
reducedVec.asUInt
}
}
File MulAddRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
import consts._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFN_interIo(expWidth: Int, sigWidth: Int) extends Bundle
{
//*** ENCODE SOME OF THESE CASES IN FEWER BITS?:
val isSigNaNAny = Bool()
val isNaNAOrB = Bool()
val isInfA = Bool()
val isZeroA = Bool()
val isInfB = Bool()
val isZeroB = Bool()
val signProd = Bool()
val isNaNC = Bool()
val isInfC = Bool()
val isZeroC = Bool()
val sExpSum = SInt((expWidth + 2).W)
val doSubMags = Bool()
val CIsDominant = Bool()
val CDom_CAlignDist = UInt(log2Ceil(sigWidth + 1).W)
val highAlignedSigC = UInt((sigWidth + 2).W)
val bit0AlignedSigC = UInt(1.W)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFNToRaw_preMul(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFNToRaw_preMul_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val op = Input(Bits(2.W))
val a = Input(Bits((expWidth + sigWidth + 1).W))
val b = Input(Bits((expWidth + sigWidth + 1).W))
val c = Input(Bits((expWidth + sigWidth + 1).W))
val mulAddA = Output(UInt(sigWidth.W))
val mulAddB = Output(UInt(sigWidth.W))
val mulAddC = Output(UInt((sigWidth * 2).W))
val toPostMul = Output(new MulAddRecFN_interIo(expWidth, sigWidth))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
//*** POSSIBLE TO REDUCE THIS BY 1 OR 2 BITS? (CURRENTLY 2 BITS BETWEEN
//*** UNSHIFTED C AND PRODUCT):
val sigSumWidth = sigWidth * 3 + 3
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val rawA = rawFloatFromRecFN(expWidth, sigWidth, io.a)
val rawB = rawFloatFromRecFN(expWidth, sigWidth, io.b)
val rawC = rawFloatFromRecFN(expWidth, sigWidth, io.c)
val signProd = rawA.sign ^ rawB.sign ^ io.op(1)
//*** REVIEW THE BIAS FOR 'sExpAlignedProd':
val sExpAlignedProd =
rawA.sExp +& rawB.sExp + (-(BigInt(1)<<expWidth) + sigWidth + 3).S
val doSubMags = signProd ^ rawC.sign ^ io.op(0)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sNatCAlignDist = sExpAlignedProd - rawC.sExp
val posNatCAlignDist = sNatCAlignDist(expWidth + 1, 0)
val isMinCAlign = rawA.isZero || rawB.isZero || (sNatCAlignDist < 0.S)
val CIsDominant =
! rawC.isZero && (isMinCAlign || (posNatCAlignDist <= sigWidth.U))
val CAlignDist =
Mux(isMinCAlign,
0.U,
Mux(posNatCAlignDist < (sigSumWidth - 1).U,
posNatCAlignDist(log2Ceil(sigSumWidth) - 1, 0),
(sigSumWidth - 1).U
)
)
val mainAlignedSigC =
(Mux(doSubMags, ~rawC.sig, rawC.sig) ## Fill(sigSumWidth - sigWidth + 2, doSubMags)).asSInt>>CAlignDist
val reduced4CExtra =
(orReduceBy4(rawC.sig<<((sigSumWidth - sigWidth - 1) & 3)) &
lowMask(
CAlignDist>>2,
//*** NOT NEEDED?:
// (sigSumWidth + 2)>>2,
(sigSumWidth - 1)>>2,
(sigSumWidth - sigWidth - 1)>>2
)
).orR
val alignedSigC =
Cat(mainAlignedSigC>>3,
Mux(doSubMags,
mainAlignedSigC(2, 0).andR && ! reduced4CExtra,
mainAlignedSigC(2, 0).orR || reduced4CExtra
)
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
io.mulAddA := rawA.sig
io.mulAddB := rawB.sig
io.mulAddC := alignedSigC(sigWidth * 2, 1)
io.toPostMul.isSigNaNAny :=
isSigNaNRawFloat(rawA) || isSigNaNRawFloat(rawB) ||
isSigNaNRawFloat(rawC)
io.toPostMul.isNaNAOrB := rawA.isNaN || rawB.isNaN
io.toPostMul.isInfA := rawA.isInf
io.toPostMul.isZeroA := rawA.isZero
io.toPostMul.isInfB := rawB.isInf
io.toPostMul.isZeroB := rawB.isZero
io.toPostMul.signProd := signProd
io.toPostMul.isNaNC := rawC.isNaN
io.toPostMul.isInfC := rawC.isInf
io.toPostMul.isZeroC := rawC.isZero
io.toPostMul.sExpSum :=
Mux(CIsDominant, rawC.sExp, sExpAlignedProd - sigWidth.S)
io.toPostMul.doSubMags := doSubMags
io.toPostMul.CIsDominant := CIsDominant
io.toPostMul.CDom_CAlignDist := CAlignDist(log2Ceil(sigWidth + 1) - 1, 0)
io.toPostMul.highAlignedSigC :=
alignedSigC(sigSumWidth - 1, sigWidth * 2 + 1)
io.toPostMul.bit0AlignedSigC := alignedSigC(0)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFNToRaw_postMul(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFNToRaw_postMul_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val fromPreMul = Input(new MulAddRecFN_interIo(expWidth, sigWidth))
val mulAddResult = Input(UInt((sigWidth * 2 + 1).W))
val roundingMode = Input(UInt(3.W))
val invalidExc = Output(Bool())
val rawOut = Output(new RawFloat(expWidth, sigWidth + 2))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sigSumWidth = sigWidth * 3 + 3
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundingMode_min = (io.roundingMode === round_min)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val opSignC = io.fromPreMul.signProd ^ io.fromPreMul.doSubMags
val sigSum =
Cat(Mux(io.mulAddResult(sigWidth * 2),
io.fromPreMul.highAlignedSigC + 1.U,
io.fromPreMul.highAlignedSigC
),
io.mulAddResult(sigWidth * 2 - 1, 0),
io.fromPreMul.bit0AlignedSigC
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val CDom_sign = opSignC
val CDom_sExp = io.fromPreMul.sExpSum - io.fromPreMul.doSubMags.zext
val CDom_absSigSum =
Mux(io.fromPreMul.doSubMags,
~sigSum(sigSumWidth - 1, sigWidth + 1),
0.U(1.W) ##
//*** IF GAP IS REDUCED TO 1 BIT, MUST REDUCE THIS COMPONENT TO 1 BIT TOO:
io.fromPreMul.highAlignedSigC(sigWidth + 1, sigWidth) ##
sigSum(sigSumWidth - 3, sigWidth + 2)
)
val CDom_absSigSumExtra =
Mux(io.fromPreMul.doSubMags,
(~sigSum(sigWidth, 1)).orR,
sigSum(sigWidth + 1, 1).orR
)
val CDom_mainSig =
(CDom_absSigSum<<io.fromPreMul.CDom_CAlignDist)(
sigWidth * 2 + 1, sigWidth - 3)
val CDom_reduced4SigExtra =
(orReduceBy4(CDom_absSigSum(sigWidth - 1, 0)<<(~sigWidth & 3)) &
lowMask(io.fromPreMul.CDom_CAlignDist>>2, 0, sigWidth>>2)).orR
val CDom_sig =
Cat(CDom_mainSig>>3,
CDom_mainSig(2, 0).orR || CDom_reduced4SigExtra ||
CDom_absSigSumExtra
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val notCDom_signSigSum = sigSum(sigWidth * 2 + 3)
val notCDom_absSigSum =
Mux(notCDom_signSigSum,
~sigSum(sigWidth * 2 + 2, 0),
sigSum(sigWidth * 2 + 2, 0) + io.fromPreMul.doSubMags
)
val notCDom_reduced2AbsSigSum = orReduceBy2(notCDom_absSigSum)
val notCDom_normDistReduced2 = countLeadingZeros(notCDom_reduced2AbsSigSum)
val notCDom_nearNormDist = notCDom_normDistReduced2<<1
val notCDom_sExp = io.fromPreMul.sExpSum - notCDom_nearNormDist.asUInt.zext
val notCDom_mainSig =
(notCDom_absSigSum<<notCDom_nearNormDist)(
sigWidth * 2 + 3, sigWidth - 1)
val notCDom_reduced4SigExtra =
(orReduceBy2(
notCDom_reduced2AbsSigSum(sigWidth>>1, 0)<<((sigWidth>>1) & 1)) &
lowMask(notCDom_normDistReduced2>>1, 0, (sigWidth + 2)>>2)
).orR
val notCDom_sig =
Cat(notCDom_mainSig>>3,
notCDom_mainSig(2, 0).orR || notCDom_reduced4SigExtra
)
val notCDom_completeCancellation =
(notCDom_sig(sigWidth + 2, sigWidth + 1) === 0.U)
val notCDom_sign =
Mux(notCDom_completeCancellation,
roundingMode_min,
io.fromPreMul.signProd ^ notCDom_signSigSum
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val notNaN_isInfProd = io.fromPreMul.isInfA || io.fromPreMul.isInfB
val notNaN_isInfOut = notNaN_isInfProd || io.fromPreMul.isInfC
val notNaN_addZeros =
(io.fromPreMul.isZeroA || io.fromPreMul.isZeroB) &&
io.fromPreMul.isZeroC
io.invalidExc :=
io.fromPreMul.isSigNaNAny ||
(io.fromPreMul.isInfA && io.fromPreMul.isZeroB) ||
(io.fromPreMul.isZeroA && io.fromPreMul.isInfB) ||
(! io.fromPreMul.isNaNAOrB &&
(io.fromPreMul.isInfA || io.fromPreMul.isInfB) &&
io.fromPreMul.isInfC &&
io.fromPreMul.doSubMags)
io.rawOut.isNaN := io.fromPreMul.isNaNAOrB || io.fromPreMul.isNaNC
io.rawOut.isInf := notNaN_isInfOut
//*** IMPROVE?:
io.rawOut.isZero :=
notNaN_addZeros ||
(! io.fromPreMul.CIsDominant && notCDom_completeCancellation)
io.rawOut.sign :=
(notNaN_isInfProd && io.fromPreMul.signProd) ||
(io.fromPreMul.isInfC && opSignC) ||
(notNaN_addZeros && ! roundingMode_min &&
io.fromPreMul.signProd && opSignC) ||
(notNaN_addZeros && roundingMode_min &&
(io.fromPreMul.signProd || opSignC)) ||
(! notNaN_isInfOut && ! notNaN_addZeros &&
Mux(io.fromPreMul.CIsDominant, CDom_sign, notCDom_sign))
io.rawOut.sExp := Mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp)
io.rawOut.sig := Mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFN(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFN_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val op = Input(Bits(2.W))
val a = Input(Bits((expWidth + sigWidth + 1).W))
val b = Input(Bits((expWidth + sigWidth + 1).W))
val c = Input(Bits((expWidth + sigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val mulAddRecFNToRaw_preMul =
Module(new MulAddRecFNToRaw_preMul(expWidth, sigWidth))
val mulAddRecFNToRaw_postMul =
Module(new MulAddRecFNToRaw_postMul(expWidth, sigWidth))
mulAddRecFNToRaw_preMul.io.op := io.op
mulAddRecFNToRaw_preMul.io.a := io.a
mulAddRecFNToRaw_preMul.io.b := io.b
mulAddRecFNToRaw_preMul.io.c := io.c
val mulAddResult =
(mulAddRecFNToRaw_preMul.io.mulAddA *
mulAddRecFNToRaw_preMul.io.mulAddB) +&
mulAddRecFNToRaw_preMul.io.mulAddC
mulAddRecFNToRaw_postMul.io.fromPreMul :=
mulAddRecFNToRaw_preMul.io.toPostMul
mulAddRecFNToRaw_postMul.io.mulAddResult := mulAddResult
mulAddRecFNToRaw_postMul.io.roundingMode := io.roundingMode
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundRawFNToRecFN =
Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0))
roundRawFNToRecFN.io.invalidExc := mulAddRecFNToRaw_postMul.io.invalidExc
roundRawFNToRecFN.io.infiniteExc := false.B
roundRawFNToRecFN.io.in := mulAddRecFNToRaw_postMul.io.rawOut
roundRawFNToRecFN.io.roundingMode := io.roundingMode
roundRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundRawFNToRecFN.io.out
io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags
}
| module MulAddRecFNToRaw_postMul_e8_s24_25( // @[MulAddRecFN.scala:169:7]
input io_fromPreMul_isSigNaNAny, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isNaNAOrB, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isInfA, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isZeroA, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_signProd, // @[MulAddRecFN.scala:172:16]
input [9:0] io_fromPreMul_sExpSum, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_doSubMags, // @[MulAddRecFN.scala:172:16]
input [4:0] io_fromPreMul_CDom_CAlignDist, // @[MulAddRecFN.scala:172:16]
input [25:0] io_fromPreMul_highAlignedSigC, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_bit0AlignedSigC, // @[MulAddRecFN.scala:172:16]
input [48:0] io_mulAddResult, // @[MulAddRecFN.scala:172:16]
output io_invalidExc, // @[MulAddRecFN.scala:172:16]
output io_rawOut_isNaN, // @[MulAddRecFN.scala:172:16]
output io_rawOut_isInf, // @[MulAddRecFN.scala:172:16]
output io_rawOut_isZero, // @[MulAddRecFN.scala:172:16]
output io_rawOut_sign, // @[MulAddRecFN.scala:172:16]
output [9:0] io_rawOut_sExp, // @[MulAddRecFN.scala:172:16]
output [26:0] io_rawOut_sig // @[MulAddRecFN.scala:172:16]
);
wire io_fromPreMul_isSigNaNAny_0 = io_fromPreMul_isSigNaNAny; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isNaNAOrB_0 = io_fromPreMul_isNaNAOrB; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isInfA_0 = io_fromPreMul_isInfA; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isZeroA_0 = io_fromPreMul_isZeroA; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_signProd_0 = io_fromPreMul_signProd; // @[MulAddRecFN.scala:169:7]
wire [9:0] io_fromPreMul_sExpSum_0 = io_fromPreMul_sExpSum; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_doSubMags_0 = io_fromPreMul_doSubMags; // @[MulAddRecFN.scala:169:7]
wire [4:0] io_fromPreMul_CDom_CAlignDist_0 = io_fromPreMul_CDom_CAlignDist; // @[MulAddRecFN.scala:169:7]
wire [25:0] io_fromPreMul_highAlignedSigC_0 = io_fromPreMul_highAlignedSigC; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_bit0AlignedSigC_0 = io_fromPreMul_bit0AlignedSigC; // @[MulAddRecFN.scala:169:7]
wire [48:0] io_mulAddResult_0 = io_mulAddResult; // @[MulAddRecFN.scala:169:7]
wire [2:0] io_roundingMode = 3'h0; // @[MulAddRecFN.scala:169:7, :172:16]
wire io_fromPreMul_isZeroC = 1'h1; // @[MulAddRecFN.scala:169:7]
wire _io_rawOut_isZero_T = 1'h1; // @[MulAddRecFN.scala:283:14]
wire _io_rawOut_sign_T_3 = 1'h1; // @[MulAddRecFN.scala:287:29]
wire io_fromPreMul_isInfB = 1'h0; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isZeroB = 1'h0; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isNaNC = 1'h0; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isInfC = 1'h0; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_CIsDominant = 1'h0; // @[MulAddRecFN.scala:169:7]
wire roundingMode_min = 1'h0; // @[MulAddRecFN.scala:186:45]
wire _io_invalidExc_T = 1'h0; // @[MulAddRecFN.scala:272:31]
wire _io_invalidExc_T_2 = 1'h0; // @[MulAddRecFN.scala:273:32]
wire _io_invalidExc_T_7 = 1'h0; // @[MulAddRecFN.scala:275:61]
wire _io_invalidExc_T_8 = 1'h0; // @[MulAddRecFN.scala:276:35]
wire _io_rawOut_sign_T_1 = 1'h0; // @[MulAddRecFN.scala:286:31]
wire _io_rawOut_sign_T_8 = 1'h0; // @[MulAddRecFN.scala:289:26]
wire _io_rawOut_sign_T_10 = 1'h0; // @[MulAddRecFN.scala:289:46]
wire _io_invalidExc_T_1 = io_fromPreMul_isSigNaNAny_0; // @[MulAddRecFN.scala:169:7, :271:35]
wire _io_rawOut_isNaN_T = io_fromPreMul_isNaNAOrB_0; // @[MulAddRecFN.scala:169:7, :278:48]
wire notNaN_isInfProd = io_fromPreMul_isInfA_0; // @[MulAddRecFN.scala:169:7, :264:49]
wire _io_invalidExc_T_5 = io_fromPreMul_isInfA_0; // @[MulAddRecFN.scala:169:7, :275:36]
wire _notNaN_addZeros_T = io_fromPreMul_isZeroA_0; // @[MulAddRecFN.scala:169:7, :267:32]
wire _io_invalidExc_T_9; // @[MulAddRecFN.scala:273:57]
wire notNaN_isInfOut; // @[MulAddRecFN.scala:265:44]
wire _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:282:25]
wire _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:290:50]
wire [9:0] _io_rawOut_sExp_T; // @[MulAddRecFN.scala:293:26]
wire [26:0] _io_rawOut_sig_T; // @[MulAddRecFN.scala:294:25]
wire io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7]
wire io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7]
wire io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7]
wire io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7]
wire [9:0] io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7]
wire [26:0] io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7]
wire io_invalidExc_0; // @[MulAddRecFN.scala:169:7]
wire opSignC = io_fromPreMul_signProd_0 ^ io_fromPreMul_doSubMags_0; // @[MulAddRecFN.scala:169:7, :190:42]
wire _sigSum_T = io_mulAddResult_0[48]; // @[MulAddRecFN.scala:169:7, :192:32]
wire [26:0] _sigSum_T_1 = {1'h0, io_fromPreMul_highAlignedSigC_0} + 27'h1; // @[MulAddRecFN.scala:169:7, :193:47]
wire [25:0] _sigSum_T_2 = _sigSum_T_1[25:0]; // @[MulAddRecFN.scala:193:47]
wire [25:0] _sigSum_T_3 = _sigSum_T ? _sigSum_T_2 : io_fromPreMul_highAlignedSigC_0; // @[MulAddRecFN.scala:169:7, :192:{16,32}, :193:47]
wire [47:0] _sigSum_T_4 = io_mulAddResult_0[47:0]; // @[MulAddRecFN.scala:169:7, :196:28]
wire [73:0] sigSum_hi = {_sigSum_T_3, _sigSum_T_4}; // @[MulAddRecFN.scala:192:{12,16}, :196:28]
wire [74:0] sigSum = {sigSum_hi, io_fromPreMul_bit0AlignedSigC_0}; // @[MulAddRecFN.scala:169:7, :192:12]
wire [1:0] _CDom_sExp_T = {1'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :203:69]
wire [10:0] _GEN = {io_fromPreMul_sExpSum_0[9], io_fromPreMul_sExpSum_0}; // @[MulAddRecFN.scala:169:7, :203:43]
wire [10:0] _CDom_sExp_T_1 = _GEN - {{9{_CDom_sExp_T[1]}}, _CDom_sExp_T}; // @[MulAddRecFN.scala:203:{43,69}]
wire [9:0] _CDom_sExp_T_2 = _CDom_sExp_T_1[9:0]; // @[MulAddRecFN.scala:203:43]
wire [9:0] CDom_sExp = _CDom_sExp_T_2; // @[MulAddRecFN.scala:203:43]
wire [49:0] _CDom_absSigSum_T = sigSum[74:25]; // @[MulAddRecFN.scala:192:12, :206:20]
wire [49:0] _CDom_absSigSum_T_1 = ~_CDom_absSigSum_T; // @[MulAddRecFN.scala:206:{13,20}]
wire [1:0] _CDom_absSigSum_T_2 = io_fromPreMul_highAlignedSigC_0[25:24]; // @[MulAddRecFN.scala:169:7, :209:46]
wire [2:0] _CDom_absSigSum_T_3 = {1'h0, _CDom_absSigSum_T_2}; // @[MulAddRecFN.scala:207:22, :209:46]
wire [46:0] _CDom_absSigSum_T_4 = sigSum[72:26]; // @[MulAddRecFN.scala:192:12, :210:23]
wire [49:0] _CDom_absSigSum_T_5 = {_CDom_absSigSum_T_3, _CDom_absSigSum_T_4}; // @[MulAddRecFN.scala:207:22, :209:71, :210:23]
wire [49:0] CDom_absSigSum = io_fromPreMul_doSubMags_0 ? _CDom_absSigSum_T_1 : _CDom_absSigSum_T_5; // @[MulAddRecFN.scala:169:7, :205:12, :206:13, :209:71]
wire [23:0] _CDom_absSigSumExtra_T = sigSum[24:1]; // @[MulAddRecFN.scala:192:12, :215:21]
wire [23:0] _CDom_absSigSumExtra_T_1 = ~_CDom_absSigSumExtra_T; // @[MulAddRecFN.scala:215:{14,21}]
wire _CDom_absSigSumExtra_T_2 = |_CDom_absSigSumExtra_T_1; // @[MulAddRecFN.scala:215:{14,36}]
wire [24:0] _CDom_absSigSumExtra_T_3 = sigSum[25:1]; // @[MulAddRecFN.scala:192:12, :216:19]
wire _CDom_absSigSumExtra_T_4 = |_CDom_absSigSumExtra_T_3; // @[MulAddRecFN.scala:216:{19,37}]
wire CDom_absSigSumExtra = io_fromPreMul_doSubMags_0 ? _CDom_absSigSumExtra_T_2 : _CDom_absSigSumExtra_T_4; // @[MulAddRecFN.scala:169:7, :214:12, :215:36, :216:37]
wire [80:0] _CDom_mainSig_T = {31'h0, CDom_absSigSum} << io_fromPreMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:169:7, :205:12, :219:24]
wire [28:0] CDom_mainSig = _CDom_mainSig_T[49:21]; // @[MulAddRecFN.scala:219:{24,56}]
wire [23:0] _CDom_reduced4SigExtra_T = CDom_absSigSum[23:0]; // @[MulAddRecFN.scala:205:12, :222:36]
wire [26:0] _CDom_reduced4SigExtra_T_1 = {_CDom_reduced4SigExtra_T, 3'h0}; // @[MulAddRecFN.scala:169:7, :172:16, :222:{36,53}]
wire _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:123:57]
wire CDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:118:30]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_0_T = _CDom_reduced4SigExtra_T_1[3:0]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_0_T_1 = |_CDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_0 = _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_1_T = _CDom_reduced4SigExtra_T_1[7:4]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_1_T_1 = |_CDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_1 = _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_2_T = _CDom_reduced4SigExtra_T_1[11:8]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_2_T_1 = |_CDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_2 = _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_3_T = _CDom_reduced4SigExtra_T_1[15:12]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_3_T_1 = |_CDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_3 = _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_4_T = _CDom_reduced4SigExtra_T_1[19:16]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_4_T_1 = |_CDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_4 = _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_5_T = _CDom_reduced4SigExtra_T_1[23:20]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_5_T_1 = |_CDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_5 = _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:118:30, :120:54]
wire [2:0] _CDom_reduced4SigExtra_reducedVec_6_T = _CDom_reduced4SigExtra_T_1[26:24]; // @[primitives.scala:123:15]
assign _CDom_reduced4SigExtra_reducedVec_6_T_1 = |_CDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:123:{15,57}]
assign CDom_reduced4SigExtra_reducedVec_6 = _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:118:30, :123:57]
wire [1:0] CDom_reduced4SigExtra_lo_hi = {CDom_reduced4SigExtra_reducedVec_2, CDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20]
wire [2:0] CDom_reduced4SigExtra_lo = {CDom_reduced4SigExtra_lo_hi, CDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20]
wire [1:0] CDom_reduced4SigExtra_hi_lo = {CDom_reduced4SigExtra_reducedVec_4, CDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:118:30, :124:20]
wire [1:0] CDom_reduced4SigExtra_hi_hi = {CDom_reduced4SigExtra_reducedVec_6, CDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:118:30, :124:20]
wire [3:0] CDom_reduced4SigExtra_hi = {CDom_reduced4SigExtra_hi_hi, CDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:124:20]
wire [6:0] _CDom_reduced4SigExtra_T_2 = {CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_lo}; // @[primitives.scala:124:20]
wire [2:0] _CDom_reduced4SigExtra_T_3 = io_fromPreMul_CDom_CAlignDist_0[4:2]; // @[MulAddRecFN.scala:169:7, :223:51]
wire [2:0] _CDom_reduced4SigExtra_T_4 = ~_CDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21]
wire [8:0] CDom_reduced4SigExtra_shift = $signed(9'sh100 >>> _CDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56]
wire [5:0] _CDom_reduced4SigExtra_T_5 = CDom_reduced4SigExtra_shift[6:1]; // @[primitives.scala:76:56, :78:22]
wire [3:0] _CDom_reduced4SigExtra_T_6 = _CDom_reduced4SigExtra_T_5[3:0]; // @[primitives.scala:77:20, :78:22]
wire [1:0] _CDom_reduced4SigExtra_T_7 = _CDom_reduced4SigExtra_T_6[1:0]; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_8 = _CDom_reduced4SigExtra_T_7[0]; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_9 = _CDom_reduced4SigExtra_T_7[1]; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_10 = {_CDom_reduced4SigExtra_T_8, _CDom_reduced4SigExtra_T_9}; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_11 = _CDom_reduced4SigExtra_T_6[3:2]; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_12 = _CDom_reduced4SigExtra_T_11[0]; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_13 = _CDom_reduced4SigExtra_T_11[1]; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_14 = {_CDom_reduced4SigExtra_T_12, _CDom_reduced4SigExtra_T_13}; // @[primitives.scala:77:20]
wire [3:0] _CDom_reduced4SigExtra_T_15 = {_CDom_reduced4SigExtra_T_10, _CDom_reduced4SigExtra_T_14}; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_16 = _CDom_reduced4SigExtra_T_5[5:4]; // @[primitives.scala:77:20, :78:22]
wire _CDom_reduced4SigExtra_T_17 = _CDom_reduced4SigExtra_T_16[0]; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_18 = _CDom_reduced4SigExtra_T_16[1]; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_19 = {_CDom_reduced4SigExtra_T_17, _CDom_reduced4SigExtra_T_18}; // @[primitives.scala:77:20]
wire [5:0] _CDom_reduced4SigExtra_T_20 = {_CDom_reduced4SigExtra_T_15, _CDom_reduced4SigExtra_T_19}; // @[primitives.scala:77:20]
wire [6:0] _CDom_reduced4SigExtra_T_21 = {1'h0, _CDom_reduced4SigExtra_T_2[5:0] & _CDom_reduced4SigExtra_T_20}; // @[primitives.scala:77:20, :124:20]
wire CDom_reduced4SigExtra = |_CDom_reduced4SigExtra_T_21; // @[MulAddRecFN.scala:222:72, :223:73]
wire [25:0] _CDom_sig_T = CDom_mainSig[28:3]; // @[MulAddRecFN.scala:219:56, :225:25]
wire [2:0] _CDom_sig_T_1 = CDom_mainSig[2:0]; // @[MulAddRecFN.scala:219:56, :226:25]
wire _CDom_sig_T_2 = |_CDom_sig_T_1; // @[MulAddRecFN.scala:226:{25,32}]
wire _CDom_sig_T_3 = _CDom_sig_T_2 | CDom_reduced4SigExtra; // @[MulAddRecFN.scala:223:73, :226:{32,36}]
wire _CDom_sig_T_4 = _CDom_sig_T_3 | CDom_absSigSumExtra; // @[MulAddRecFN.scala:214:12, :226:{36,61}]
wire [26:0] CDom_sig = {_CDom_sig_T, _CDom_sig_T_4}; // @[MulAddRecFN.scala:225:{12,25}, :226:61]
wire notCDom_signSigSum = sigSum[51]; // @[MulAddRecFN.scala:192:12, :232:36]
wire [50:0] _notCDom_absSigSum_T = sigSum[50:0]; // @[MulAddRecFN.scala:192:12, :235:20]
wire [50:0] _notCDom_absSigSum_T_2 = sigSum[50:0]; // @[MulAddRecFN.scala:192:12, :235:20, :236:19]
wire [50:0] _notCDom_absSigSum_T_1 = ~_notCDom_absSigSum_T; // @[MulAddRecFN.scala:235:{13,20}]
wire [51:0] _notCDom_absSigSum_T_3 = {1'h0, _notCDom_absSigSum_T_2} + {51'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :236:{19,41}]
wire [50:0] _notCDom_absSigSum_T_4 = _notCDom_absSigSum_T_3[50:0]; // @[MulAddRecFN.scala:236:41]
wire [50:0] notCDom_absSigSum = notCDom_signSigSum ? _notCDom_absSigSum_T_1 : _notCDom_absSigSum_T_4; // @[MulAddRecFN.scala:232:36, :234:12, :235:13, :236:41]
wire _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:106:57]
wire notCDom_reduced2AbsSigSum_reducedVec_0; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_1; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_2; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_3; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_4; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_5; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_6; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_7; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_8; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_9; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_10; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_11; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_12; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_13; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_14; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_15; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_16; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_17; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_18; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_19; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_20; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_21; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_22; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_23; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_24; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_25; // @[primitives.scala:101:30]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_0_T = notCDom_absSigSum[1:0]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_0_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_0 = _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_1_T = notCDom_absSigSum[3:2]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_1_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_1 = _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_2_T = notCDom_absSigSum[5:4]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_2_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_2 = _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_3_T = notCDom_absSigSum[7:6]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_3_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_3 = _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_4_T = notCDom_absSigSum[9:8]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_4_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_4 = _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_5_T = notCDom_absSigSum[11:10]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_5_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_5 = _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_6_T = notCDom_absSigSum[13:12]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_6_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_6 = _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_7_T = notCDom_absSigSum[15:14]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_7_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_7 = _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_8_T = notCDom_absSigSum[17:16]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_8_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_8 = _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_9_T = notCDom_absSigSum[19:18]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_9_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_9 = _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_10_T = notCDom_absSigSum[21:20]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_10_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_10 = _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_11_T = notCDom_absSigSum[23:22]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_11_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_11 = _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_12_T = notCDom_absSigSum[25:24]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_12_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_12 = _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_13_T = notCDom_absSigSum[27:26]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_13_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_13 = _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_14_T = notCDom_absSigSum[29:28]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_14_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_14 = _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_15_T = notCDom_absSigSum[31:30]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_15_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_15 = _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_16_T = notCDom_absSigSum[33:32]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_16_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_16 = _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_17_T = notCDom_absSigSum[35:34]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_17_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_17 = _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_18_T = notCDom_absSigSum[37:36]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_18_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_18 = _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_19_T = notCDom_absSigSum[39:38]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_19_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_19 = _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_20_T = notCDom_absSigSum[41:40]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_20_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_20 = _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_21_T = notCDom_absSigSum[43:42]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_21_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_21 = _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_22_T = notCDom_absSigSum[45:44]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_22_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_22 = _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_23_T = notCDom_absSigSum[47:46]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_23_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_23 = _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_24_T = notCDom_absSigSum[49:48]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_24_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_24 = _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:101:30, :103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_25_T = notCDom_absSigSum[50]; // @[primitives.scala:106:15]
assign _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 = _notCDom_reduced2AbsSigSum_reducedVec_25_T; // @[primitives.scala:106:{15,57}]
assign notCDom_reduced2AbsSigSum_reducedVec_25 = _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:101:30, :106:57]
wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_2, notCDom_reduced2AbsSigSum_reducedVec_1}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_0}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_5, notCDom_reduced2AbsSigSum_reducedVec_4}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_hi = {notCDom_reduced2AbsSigSum_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_3}; // @[primitives.scala:101:30, :107:20]
wire [5:0] notCDom_reduced2AbsSigSum_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_lo_lo_lo}; // @[primitives.scala:107:20]
wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_8, notCDom_reduced2AbsSigSum_reducedVec_7}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_lo_hi_lo = {notCDom_reduced2AbsSigSum_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_6}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_10, notCDom_reduced2AbsSigSum_reducedVec_9}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_12, notCDom_reduced2AbsSigSum_reducedVec_11}; // @[primitives.scala:101:30, :107:20]
wire [3:0] notCDom_reduced2AbsSigSum_lo_hi_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_hi_lo}; // @[primitives.scala:107:20]
wire [6:0] notCDom_reduced2AbsSigSum_lo_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_lo}; // @[primitives.scala:107:20]
wire [12:0] notCDom_reduced2AbsSigSum_lo = {notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo}; // @[primitives.scala:107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_15, notCDom_reduced2AbsSigSum_reducedVec_14}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_lo = {notCDom_reduced2AbsSigSum_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_13}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_18, notCDom_reduced2AbsSigSum_reducedVec_17}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_hi = {notCDom_reduced2AbsSigSum_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_16}; // @[primitives.scala:101:30, :107:20]
wire [5:0] notCDom_reduced2AbsSigSum_hi_lo = {notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_hi_lo_lo}; // @[primitives.scala:107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_21, notCDom_reduced2AbsSigSum_reducedVec_20}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_hi_hi_lo = {notCDom_reduced2AbsSigSum_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_19}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_23, notCDom_reduced2AbsSigSum_reducedVec_22}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_25, notCDom_reduced2AbsSigSum_reducedVec_24}; // @[primitives.scala:101:30, :107:20]
wire [3:0] notCDom_reduced2AbsSigSum_hi_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_hi_lo}; // @[primitives.scala:107:20]
wire [6:0] notCDom_reduced2AbsSigSum_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo}; // @[primitives.scala:107:20]
wire [12:0] notCDom_reduced2AbsSigSum_hi = {notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo}; // @[primitives.scala:107:20]
wire [25:0] notCDom_reduced2AbsSigSum = {notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo}; // @[primitives.scala:107:20]
wire _notCDom_normDistReduced2_T = notCDom_reduced2AbsSigSum[0]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_1 = notCDom_reduced2AbsSigSum[1]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_2 = notCDom_reduced2AbsSigSum[2]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_3 = notCDom_reduced2AbsSigSum[3]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_4 = notCDom_reduced2AbsSigSum[4]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_5 = notCDom_reduced2AbsSigSum[5]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_6 = notCDom_reduced2AbsSigSum[6]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_7 = notCDom_reduced2AbsSigSum[7]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_8 = notCDom_reduced2AbsSigSum[8]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_9 = notCDom_reduced2AbsSigSum[9]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_10 = notCDom_reduced2AbsSigSum[10]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_11 = notCDom_reduced2AbsSigSum[11]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_12 = notCDom_reduced2AbsSigSum[12]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_13 = notCDom_reduced2AbsSigSum[13]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_14 = notCDom_reduced2AbsSigSum[14]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_15 = notCDom_reduced2AbsSigSum[15]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_16 = notCDom_reduced2AbsSigSum[16]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_17 = notCDom_reduced2AbsSigSum[17]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_18 = notCDom_reduced2AbsSigSum[18]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_19 = notCDom_reduced2AbsSigSum[19]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_20 = notCDom_reduced2AbsSigSum[20]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_21 = notCDom_reduced2AbsSigSum[21]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_22 = notCDom_reduced2AbsSigSum[22]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_23 = notCDom_reduced2AbsSigSum[23]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_24 = notCDom_reduced2AbsSigSum[24]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_25 = notCDom_reduced2AbsSigSum[25]; // @[primitives.scala:91:52, :107:20]
wire [4:0] _notCDom_normDistReduced2_T_26 = {4'hC, ~_notCDom_normDistReduced2_T_1}; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_27 = _notCDom_normDistReduced2_T_2 ? 5'h17 : _notCDom_normDistReduced2_T_26; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_28 = _notCDom_normDistReduced2_T_3 ? 5'h16 : _notCDom_normDistReduced2_T_27; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_29 = _notCDom_normDistReduced2_T_4 ? 5'h15 : _notCDom_normDistReduced2_T_28; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_30 = _notCDom_normDistReduced2_T_5 ? 5'h14 : _notCDom_normDistReduced2_T_29; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_31 = _notCDom_normDistReduced2_T_6 ? 5'h13 : _notCDom_normDistReduced2_T_30; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_32 = _notCDom_normDistReduced2_T_7 ? 5'h12 : _notCDom_normDistReduced2_T_31; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_33 = _notCDom_normDistReduced2_T_8 ? 5'h11 : _notCDom_normDistReduced2_T_32; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_34 = _notCDom_normDistReduced2_T_9 ? 5'h10 : _notCDom_normDistReduced2_T_33; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_35 = _notCDom_normDistReduced2_T_10 ? 5'hF : _notCDom_normDistReduced2_T_34; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_36 = _notCDom_normDistReduced2_T_11 ? 5'hE : _notCDom_normDistReduced2_T_35; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_37 = _notCDom_normDistReduced2_T_12 ? 5'hD : _notCDom_normDistReduced2_T_36; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_38 = _notCDom_normDistReduced2_T_13 ? 5'hC : _notCDom_normDistReduced2_T_37; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_39 = _notCDom_normDistReduced2_T_14 ? 5'hB : _notCDom_normDistReduced2_T_38; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_40 = _notCDom_normDistReduced2_T_15 ? 5'hA : _notCDom_normDistReduced2_T_39; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_41 = _notCDom_normDistReduced2_T_16 ? 5'h9 : _notCDom_normDistReduced2_T_40; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_42 = _notCDom_normDistReduced2_T_17 ? 5'h8 : _notCDom_normDistReduced2_T_41; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_43 = _notCDom_normDistReduced2_T_18 ? 5'h7 : _notCDom_normDistReduced2_T_42; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_44 = _notCDom_normDistReduced2_T_19 ? 5'h6 : _notCDom_normDistReduced2_T_43; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_45 = _notCDom_normDistReduced2_T_20 ? 5'h5 : _notCDom_normDistReduced2_T_44; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_46 = _notCDom_normDistReduced2_T_21 ? 5'h4 : _notCDom_normDistReduced2_T_45; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_47 = _notCDom_normDistReduced2_T_22 ? 5'h3 : _notCDom_normDistReduced2_T_46; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_48 = _notCDom_normDistReduced2_T_23 ? 5'h2 : _notCDom_normDistReduced2_T_47; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_49 = _notCDom_normDistReduced2_T_24 ? 5'h1 : _notCDom_normDistReduced2_T_48; // @[Mux.scala:50:70]
wire [4:0] notCDom_normDistReduced2 = _notCDom_normDistReduced2_T_25 ? 5'h0 : _notCDom_normDistReduced2_T_49; // @[Mux.scala:50:70]
wire [5:0] notCDom_nearNormDist = {notCDom_normDistReduced2, 1'h0}; // @[Mux.scala:50:70]
wire [6:0] _notCDom_sExp_T = {1'h0, notCDom_nearNormDist}; // @[MulAddRecFN.scala:240:56, :241:76]
wire [10:0] _notCDom_sExp_T_1 = _GEN - {{4{_notCDom_sExp_T[6]}}, _notCDom_sExp_T}; // @[MulAddRecFN.scala:203:43, :241:{46,76}]
wire [9:0] _notCDom_sExp_T_2 = _notCDom_sExp_T_1[9:0]; // @[MulAddRecFN.scala:241:46]
wire [9:0] notCDom_sExp = _notCDom_sExp_T_2; // @[MulAddRecFN.scala:241:46]
assign _io_rawOut_sExp_T = notCDom_sExp; // @[MulAddRecFN.scala:241:46, :293:26]
wire [113:0] _notCDom_mainSig_T = {63'h0, notCDom_absSigSum} << notCDom_nearNormDist; // @[MulAddRecFN.scala:234:12, :240:56, :243:27]
wire [28:0] notCDom_mainSig = _notCDom_mainSig_T[51:23]; // @[MulAddRecFN.scala:243:{27,50}]
wire [12:0] _notCDom_reduced4SigExtra_T = notCDom_reduced2AbsSigSum[12:0]; // @[primitives.scala:107:20]
wire [12:0] _notCDom_reduced4SigExtra_T_1 = _notCDom_reduced4SigExtra_T; // @[MulAddRecFN.scala:247:{39,55}]
wire _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:106:57]
wire notCDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:101:30]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_0_T = _notCDom_reduced4SigExtra_T_1[1:0]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_0_T_1 = |_notCDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_0 = _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_1_T = _notCDom_reduced4SigExtra_T_1[3:2]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_1_T_1 = |_notCDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_1 = _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_2_T = _notCDom_reduced4SigExtra_T_1[5:4]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_2_T_1 = |_notCDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_2 = _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_3_T = _notCDom_reduced4SigExtra_T_1[7:6]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_3_T_1 = |_notCDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_3 = _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_4_T = _notCDom_reduced4SigExtra_T_1[9:8]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_4_T_1 = |_notCDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_4 = _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_5_T = _notCDom_reduced4SigExtra_T_1[11:10]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_5_T_1 = |_notCDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_5 = _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54]
wire _notCDom_reduced4SigExtra_reducedVec_6_T = _notCDom_reduced4SigExtra_T_1[12]; // @[primitives.scala:106:15]
assign _notCDom_reduced4SigExtra_reducedVec_6_T_1 = _notCDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:106:{15,57}]
assign notCDom_reduced4SigExtra_reducedVec_6 = _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:101:30, :106:57]
wire [1:0] notCDom_reduced4SigExtra_lo_hi = {notCDom_reduced4SigExtra_reducedVec_2, notCDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced4SigExtra_lo = {notCDom_reduced4SigExtra_lo_hi, notCDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced4SigExtra_hi_lo = {notCDom_reduced4SigExtra_reducedVec_4, notCDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced4SigExtra_hi_hi = {notCDom_reduced4SigExtra_reducedVec_6, notCDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:101:30, :107:20]
wire [3:0] notCDom_reduced4SigExtra_hi = {notCDom_reduced4SigExtra_hi_hi, notCDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:107:20]
wire [6:0] _notCDom_reduced4SigExtra_T_2 = {notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo}; // @[primitives.scala:107:20]
wire [3:0] _notCDom_reduced4SigExtra_T_3 = notCDom_normDistReduced2[4:1]; // @[Mux.scala:50:70]
wire [3:0] _notCDom_reduced4SigExtra_T_4 = ~_notCDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21]
wire [16:0] notCDom_reduced4SigExtra_shift = $signed(17'sh10000 >>> _notCDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56]
wire [5:0] _notCDom_reduced4SigExtra_T_5 = notCDom_reduced4SigExtra_shift[6:1]; // @[primitives.scala:76:56, :78:22]
wire [3:0] _notCDom_reduced4SigExtra_T_6 = _notCDom_reduced4SigExtra_T_5[3:0]; // @[primitives.scala:77:20, :78:22]
wire [1:0] _notCDom_reduced4SigExtra_T_7 = _notCDom_reduced4SigExtra_T_6[1:0]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_8 = _notCDom_reduced4SigExtra_T_7[0]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_9 = _notCDom_reduced4SigExtra_T_7[1]; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_10 = {_notCDom_reduced4SigExtra_T_8, _notCDom_reduced4SigExtra_T_9}; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_11 = _notCDom_reduced4SigExtra_T_6[3:2]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_12 = _notCDom_reduced4SigExtra_T_11[0]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_13 = _notCDom_reduced4SigExtra_T_11[1]; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_14 = {_notCDom_reduced4SigExtra_T_12, _notCDom_reduced4SigExtra_T_13}; // @[primitives.scala:77:20]
wire [3:0] _notCDom_reduced4SigExtra_T_15 = {_notCDom_reduced4SigExtra_T_10, _notCDom_reduced4SigExtra_T_14}; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_16 = _notCDom_reduced4SigExtra_T_5[5:4]; // @[primitives.scala:77:20, :78:22]
wire _notCDom_reduced4SigExtra_T_17 = _notCDom_reduced4SigExtra_T_16[0]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_18 = _notCDom_reduced4SigExtra_T_16[1]; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_19 = {_notCDom_reduced4SigExtra_T_17, _notCDom_reduced4SigExtra_T_18}; // @[primitives.scala:77:20]
wire [5:0] _notCDom_reduced4SigExtra_T_20 = {_notCDom_reduced4SigExtra_T_15, _notCDom_reduced4SigExtra_T_19}; // @[primitives.scala:77:20]
wire [6:0] _notCDom_reduced4SigExtra_T_21 = {1'h0, _notCDom_reduced4SigExtra_T_2[5:0] & _notCDom_reduced4SigExtra_T_20}; // @[primitives.scala:77:20, :107:20]
wire notCDom_reduced4SigExtra = |_notCDom_reduced4SigExtra_T_21; // @[MulAddRecFN.scala:247:78, :249:11]
wire [25:0] _notCDom_sig_T = notCDom_mainSig[28:3]; // @[MulAddRecFN.scala:243:50, :251:28]
wire [2:0] _notCDom_sig_T_1 = notCDom_mainSig[2:0]; // @[MulAddRecFN.scala:243:50, :252:28]
wire _notCDom_sig_T_2 = |_notCDom_sig_T_1; // @[MulAddRecFN.scala:252:{28,35}]
wire _notCDom_sig_T_3 = _notCDom_sig_T_2 | notCDom_reduced4SigExtra; // @[MulAddRecFN.scala:249:11, :252:{35,39}]
wire [26:0] notCDom_sig = {_notCDom_sig_T, _notCDom_sig_T_3}; // @[MulAddRecFN.scala:251:{12,28}, :252:39]
assign _io_rawOut_sig_T = notCDom_sig; // @[MulAddRecFN.scala:251:12, :294:25]
wire [1:0] _notCDom_completeCancellation_T = notCDom_sig[26:25]; // @[MulAddRecFN.scala:251:12, :255:21]
wire notCDom_completeCancellation = _notCDom_completeCancellation_T == 2'h0; // @[primitives.scala:103:54]
wire _io_rawOut_isZero_T_1 = notCDom_completeCancellation; // @[MulAddRecFN.scala:255:50, :283:42]
wire _notCDom_sign_T = io_fromPreMul_signProd_0 ^ notCDom_signSigSum; // @[MulAddRecFN.scala:169:7, :232:36, :259:36]
wire notCDom_sign = ~notCDom_completeCancellation & _notCDom_sign_T; // @[MulAddRecFN.scala:255:50, :257:12, :259:36]
wire _io_rawOut_sign_T_15 = notCDom_sign; // @[MulAddRecFN.scala:257:12, :292:17]
assign notNaN_isInfOut = notNaN_isInfProd; // @[MulAddRecFN.scala:264:49, :265:44]
assign io_rawOut_isInf_0 = notNaN_isInfOut; // @[MulAddRecFN.scala:169:7, :265:44]
wire notNaN_addZeros = _notNaN_addZeros_T; // @[MulAddRecFN.scala:267:{32,58}]
wire _io_rawOut_sign_T_4 = notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :287:26]
wire _io_invalidExc_T_3 = _io_invalidExc_T_1; // @[MulAddRecFN.scala:271:35, :272:57]
assign _io_invalidExc_T_9 = _io_invalidExc_T_3; // @[MulAddRecFN.scala:272:57, :273:57]
wire _io_invalidExc_T_4 = ~io_fromPreMul_isNaNAOrB_0; // @[MulAddRecFN.scala:169:7, :274:10]
wire _io_invalidExc_T_6 = _io_invalidExc_T_4 & _io_invalidExc_T_5; // @[MulAddRecFN.scala:274:{10,36}, :275:36]
assign io_invalidExc_0 = _io_invalidExc_T_9; // @[MulAddRecFN.scala:169:7, :273:57]
assign io_rawOut_isNaN_0 = _io_rawOut_isNaN_T; // @[MulAddRecFN.scala:169:7, :278:48]
assign _io_rawOut_isZero_T_2 = notNaN_addZeros | _io_rawOut_isZero_T_1; // @[MulAddRecFN.scala:267:58, :282:25, :283:42]
assign io_rawOut_isZero_0 = _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:169:7, :282:25]
wire _io_rawOut_sign_T = notNaN_isInfProd & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :264:49, :285:27]
wire _io_rawOut_sign_T_2 = _io_rawOut_sign_T; // @[MulAddRecFN.scala:285:{27,54}]
wire _io_rawOut_sign_T_5 = _io_rawOut_sign_T_4 & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :287:{26,48}]
wire _io_rawOut_sign_T_6 = _io_rawOut_sign_T_5 & opSignC; // @[MulAddRecFN.scala:190:42, :287:48, :288:36]
wire _io_rawOut_sign_T_7 = _io_rawOut_sign_T_2 | _io_rawOut_sign_T_6; // @[MulAddRecFN.scala:285:54, :286:43, :288:36]
wire _io_rawOut_sign_T_11 = _io_rawOut_sign_T_7; // @[MulAddRecFN.scala:286:43, :288:48]
wire _io_rawOut_sign_T_9 = io_fromPreMul_signProd_0 | opSignC; // @[MulAddRecFN.scala:169:7, :190:42, :290:37]
wire _io_rawOut_sign_T_12 = ~notNaN_isInfOut; // @[MulAddRecFN.scala:265:44, :291:10]
wire _io_rawOut_sign_T_13 = ~notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :291:31]
wire _io_rawOut_sign_T_14 = _io_rawOut_sign_T_12 & _io_rawOut_sign_T_13; // @[MulAddRecFN.scala:291:{10,28,31}]
wire _io_rawOut_sign_T_16 = _io_rawOut_sign_T_14 & _io_rawOut_sign_T_15; // @[MulAddRecFN.scala:291:{28,49}, :292:17]
assign _io_rawOut_sign_T_17 = _io_rawOut_sign_T_11 | _io_rawOut_sign_T_16; // @[MulAddRecFN.scala:288:48, :290:50, :291:49]
assign io_rawOut_sign_0 = _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:169:7, :290:50]
assign io_rawOut_sExp_0 = _io_rawOut_sExp_T; // @[MulAddRecFN.scala:169:7, :293:26]
assign io_rawOut_sig_0 = _io_rawOut_sig_T; // @[MulAddRecFN.scala:169:7, :294:25]
assign io_invalidExc = io_invalidExc_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_sign = io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_sig = io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Buffer.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.BufferParams
class TLBufferNode (
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit valName: ValName) extends TLAdapterNode(
clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) },
managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) }
) {
override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}"
override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none)
}
class TLBuffer(
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit p: Parameters) extends LazyModule
{
def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace)
def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde)
def this()(implicit p: Parameters) = this(BufferParams.default)
val node = new TLBufferNode(a, b, c, d, e)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
def headBundle = node.out.head._2.bundle
override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_")
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out.a <> a(in .a)
in .d <> d(out.d)
if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) {
in .b <> b(out.b)
out.c <> c(in .c)
out.e <> e(in .e)
} else {
in.b.valid := false.B
in.c.ready := true.B
in.e.ready := true.B
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
}
}
}
}
object TLBuffer
{
def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default)
def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde)
def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace)
def apply(
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit p: Parameters): TLNode =
{
val buffer = LazyModule(new TLBuffer(a, b, c, d, e))
buffer.node
}
def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = {
val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) }
name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } }
buffers.map(_.node)
}
def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = {
chain(depth, name)
.reduceLeftOption(_ :*=* _)
.getOrElse(TLNameNode("no_buffer"))
}
}
File Fragmenter.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.{AddressSet, BufferParams, IdRange, TransferSizes}
import freechips.rocketchip.util.{Repeater, OH1ToUInt, UIntToOH1}
import scala.math.min
import freechips.rocketchip.util.DataToAugmentedData
object EarlyAck {
sealed trait T
case object AllPuts extends T
case object PutFulls extends T
case object None extends T
}
// minSize: minimum size of transfers supported by all outward managers
// maxSize: maximum size of transfers supported after the Fragmenter is applied
// alwaysMin: fragment all requests down to minSize (else fragment to maximum supported by manager)
// earlyAck: should a multibeat Put should be acknowledged on the first beat or last beat
// holdFirstDeny: allow the Fragmenter to unsafely combine multibeat Gets by taking the first denied for the whole burst
// nameSuffix: appends a suffix to the module name
// Fragmenter modifies: PutFull, PutPartial, LogicalData, Get, Hint
// Fragmenter passes: ArithmeticData (truncated to minSize if alwaysMin)
// Fragmenter cannot modify acquire (could livelock); thus it is unsafe to put caches on both sides
class TLFragmenter(val minSize: Int, val maxSize: Int, val alwaysMin: Boolean = false, val earlyAck: EarlyAck.T = EarlyAck.None, val holdFirstDeny: Boolean = false, val nameSuffix: Option[String] = None)(implicit p: Parameters) extends LazyModule
{
require(isPow2 (maxSize), s"TLFragmenter expects pow2(maxSize), but got $maxSize")
require(isPow2 (minSize), s"TLFragmenter expects pow2(minSize), but got $minSize")
require(minSize <= maxSize, s"TLFragmenter expects min <= max, but got $minSize > $maxSize")
val fragmentBits = log2Ceil(maxSize / minSize)
val fullBits = if (earlyAck == EarlyAck.PutFulls) 1 else 0
val toggleBits = 1
val addedBits = fragmentBits + toggleBits + fullBits
def expandTransfer(x: TransferSizes, op: String) = if (!x) x else {
// validate that we can apply the fragmenter correctly
require (x.max >= minSize, s"TLFragmenter (with parent $parent) max transfer size $op(${x.max}) must be >= min transfer size (${minSize})")
TransferSizes(x.min, maxSize)
}
private def noChangeRequired = minSize == maxSize
private def shrinkTransfer(x: TransferSizes) =
if (!alwaysMin) x
else if (x.min <= minSize) TransferSizes(x.min, min(minSize, x.max))
else TransferSizes.none
private def mapManager(m: TLSlaveParameters) = m.v1copy(
supportsArithmetic = shrinkTransfer(m.supportsArithmetic),
supportsLogical = shrinkTransfer(m.supportsLogical),
supportsGet = expandTransfer(m.supportsGet, "Get"),
supportsPutFull = expandTransfer(m.supportsPutFull, "PutFull"),
supportsPutPartial = expandTransfer(m.supportsPutPartial, "PutParital"),
supportsHint = expandTransfer(m.supportsHint, "Hint"))
val node = new TLAdapterNode(
// We require that all the responses are mutually FIFO
// Thus we need to compact all of the masters into one big master
clientFn = { c => (if (noChangeRequired) c else c.v2copy(
masters = Seq(TLMasterParameters.v2(
name = "TLFragmenter",
sourceId = IdRange(0, if (minSize == maxSize) c.endSourceId else (c.endSourceId << addedBits)),
requestFifo = true,
emits = TLMasterToSlaveTransferSizes(
acquireT = shrinkTransfer(c.masters.map(_.emits.acquireT) .reduce(_ mincover _)),
acquireB = shrinkTransfer(c.masters.map(_.emits.acquireB) .reduce(_ mincover _)),
arithmetic = shrinkTransfer(c.masters.map(_.emits.arithmetic).reduce(_ mincover _)),
logical = shrinkTransfer(c.masters.map(_.emits.logical) .reduce(_ mincover _)),
get = shrinkTransfer(c.masters.map(_.emits.get) .reduce(_ mincover _)),
putFull = shrinkTransfer(c.masters.map(_.emits.putFull) .reduce(_ mincover _)),
putPartial = shrinkTransfer(c.masters.map(_.emits.putPartial).reduce(_ mincover _)),
hint = shrinkTransfer(c.masters.map(_.emits.hint) .reduce(_ mincover _))
)
))
))},
managerFn = { m => if (noChangeRequired) m else m.v2copy(slaves = m.slaves.map(mapManager)) }
) {
override def circuitIdentity = noChangeRequired
}
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
override def desiredName = (Seq("TLFragmenter") ++ nameSuffix).mkString("_")
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
if (noChangeRequired) {
out <> in
} else {
// All managers must share a common FIFO domain (responses might end up interleaved)
val manager = edgeOut.manager
val managers = manager.managers
val beatBytes = manager.beatBytes
val fifoId = managers(0).fifoId
require (fifoId.isDefined && managers.map(_.fifoId == fifoId).reduce(_ && _))
require (!manager.anySupportAcquireB || !edgeOut.client.anySupportProbe,
s"TLFragmenter (with parent $parent) can't fragment a caching client's requests into a cacheable region")
require (minSize >= beatBytes, s"TLFragmenter (with parent $parent) can't support fragmenting ($minSize) to sub-beat ($beatBytes) accesses")
// We can't support devices which are cached on both sides of us
require (!edgeOut.manager.anySupportAcquireB || !edgeIn.client.anySupportProbe)
// We can't support denied because we reassemble fragments
require (!edgeOut.manager.mayDenyGet || holdFirstDeny, s"TLFragmenter (with parent $parent) can't support denials without holdFirstDeny=true")
require (!edgeOut.manager.mayDenyPut || earlyAck == EarlyAck.None)
/* The Fragmenter is a bit tricky, because there are 5 sizes in play:
* max size -- the maximum transfer size possible
* orig size -- the original pre-fragmenter size
* frag size -- the modified post-fragmenter size
* min size -- the threshold below which frag=orig
* beat size -- the amount transfered on any given beat
*
* The relationships are as follows:
* max >= orig >= frag
* max > min >= beat
* It IS possible that orig <= min (then frag=orig; ie: no fragmentation)
*
* The fragment# (sent via TL.source) is measured in multiples of min size.
* Meanwhile, to track the progress, counters measure in multiples of beat size.
*
* Here is an example of a bus with max=256, min=8, beat=4 and a device supporting 16.
*
* in.A out.A (frag#) out.D (frag#) in.D gen# ack#
* get64 get16 6 ackD16 6 ackD64 12 15
* ackD16 6 ackD64 14
* ackD16 6 ackD64 13
* ackD16 6 ackD64 12
* get16 4 ackD16 4 ackD64 8 11
* ackD16 4 ackD64 10
* ackD16 4 ackD64 9
* ackD16 4 ackD64 8
* get16 2 ackD16 2 ackD64 4 7
* ackD16 2 ackD64 6
* ackD16 2 ackD64 5
* ackD16 2 ackD64 4
* get16 0 ackD16 0 ackD64 0 3
* ackD16 0 ackD64 2
* ackD16 0 ackD64 1
* ackD16 0 ackD64 0
*
* get8 get8 0 ackD8 0 ackD8 0 1
* ackD8 0 ackD8 0
*
* get4 get4 0 ackD4 0 ackD4 0 0
* get1 get1 0 ackD1 0 ackD1 0 0
*
* put64 put16 6 15
* put64 put16 6 14
* put64 put16 6 13
* put64 put16 6 ack16 6 12 12
* put64 put16 4 11
* put64 put16 4 10
* put64 put16 4 9
* put64 put16 4 ack16 4 8 8
* put64 put16 2 7
* put64 put16 2 6
* put64 put16 2 5
* put64 put16 2 ack16 2 4 4
* put64 put16 0 3
* put64 put16 0 2
* put64 put16 0 1
* put64 put16 0 ack16 0 ack64 0 0
*
* put8 put8 0 1
* put8 put8 0 ack8 0 ack8 0 0
*
* put4 put4 0 ack4 0 ack4 0 0
* put1 put1 0 ack1 0 ack1 0 0
*/
val counterBits = log2Up(maxSize/beatBytes)
val maxDownSize = if (alwaysMin) minSize else min(manager.maxTransfer, maxSize)
// Consider the following waveform for two 4-beat bursts:
// ---A----A------------
// -------D-----DDD-DDDD
// Under TL rules, the second A can use the same source as the first A,
// because the source is released for reuse on the first response beat.
//
// However, if we fragment the requests, it looks like this:
// ---3210-3210---------
// -------3-----210-3210
// ... now we've broken the rules because 210 are twice inflight.
//
// This phenomenon means we can have essentially 2*maxSize/minSize-1
// fragmented transactions in flight per original transaction source.
//
// To keep the source unique, we encode the beat counter in the low
// bits of the source. To solve the overlap, we use a toggle bit.
// Whatever toggle bit the D is reassembling, A will use the opposite.
// First, handle the return path
val acknum = RegInit(0.U(counterBits.W))
val dOrig = Reg(UInt())
val dToggle = RegInit(false.B)
val dFragnum = out.d.bits.source(fragmentBits-1, 0)
val dFirst = acknum === 0.U
val dLast = dFragnum === 0.U // only for AccessAck (!Data)
val dsizeOH = UIntToOH (out.d.bits.size, log2Ceil(maxDownSize)+1)
val dsizeOH1 = UIntToOH1(out.d.bits.size, log2Up(maxDownSize))
val dHasData = edgeOut.hasData(out.d.bits)
// calculate new acknum
val acknum_fragment = dFragnum << log2Ceil(minSize/beatBytes)
val acknum_size = dsizeOH1 >> log2Ceil(beatBytes)
assert (!out.d.valid || (acknum_fragment & acknum_size) === 0.U)
val dFirst_acknum = acknum_fragment | Mux(dHasData, acknum_size, 0.U)
val ack_decrement = Mux(dHasData, 1.U, dsizeOH >> log2Ceil(beatBytes))
// calculate the original size
val dFirst_size = OH1ToUInt((dFragnum << log2Ceil(minSize)) | dsizeOH1)
when (out.d.fire) {
acknum := Mux(dFirst, dFirst_acknum, acknum - ack_decrement)
when (dFirst) {
dOrig := dFirst_size
dToggle := out.d.bits.source(fragmentBits)
}
}
// Swallow up non-data ack fragments
val doEarlyAck = earlyAck match {
case EarlyAck.AllPuts => true.B
case EarlyAck.PutFulls => out.d.bits.source(fragmentBits+1)
case EarlyAck.None => false.B
}
val drop = !dHasData && !Mux(doEarlyAck, dFirst, dLast)
out.d.ready := in.d.ready || drop
in.d.valid := out.d.valid && !drop
in.d.bits := out.d.bits // pass most stuff unchanged
in.d.bits.source := out.d.bits.source >> addedBits
in.d.bits.size := Mux(dFirst, dFirst_size, dOrig)
if (edgeOut.manager.mayDenyPut) {
val r_denied = Reg(Bool())
val d_denied = (!dFirst && r_denied) || out.d.bits.denied
when (out.d.fire) { r_denied := d_denied }
in.d.bits.denied := d_denied
}
if (edgeOut.manager.mayDenyGet) {
// Take denied only from the first beat and hold that value
val d_denied = out.d.bits.denied holdUnless dFirst
when (dHasData) {
in.d.bits.denied := d_denied
in.d.bits.corrupt := d_denied || out.d.bits.corrupt
}
}
// What maximum transfer sizes do downstream devices support?
val maxArithmetics = managers.map(_.supportsArithmetic.max)
val maxLogicals = managers.map(_.supportsLogical.max)
val maxGets = managers.map(_.supportsGet.max)
val maxPutFulls = managers.map(_.supportsPutFull.max)
val maxPutPartials = managers.map(_.supportsPutPartial.max)
val maxHints = managers.map(m => if (m.supportsHint) maxDownSize else 0)
// We assume that the request is valid => size 0 is impossible
val lgMinSize = log2Ceil(minSize).U
val maxLgArithmetics = maxArithmetics.map(m => if (m == 0) lgMinSize else log2Ceil(m).U)
val maxLgLogicals = maxLogicals .map(m => if (m == 0) lgMinSize else log2Ceil(m).U)
val maxLgGets = maxGets .map(m => if (m == 0) lgMinSize else log2Ceil(m).U)
val maxLgPutFulls = maxPutFulls .map(m => if (m == 0) lgMinSize else log2Ceil(m).U)
val maxLgPutPartials = maxPutPartials.map(m => if (m == 0) lgMinSize else log2Ceil(m).U)
val maxLgHints = maxHints .map(m => if (m == 0) lgMinSize else log2Ceil(m).U)
// Make the request repeatable
val repeater = Module(new Repeater(in.a.bits))
repeater.io.enq <> in.a
val in_a = repeater.io.deq
// If this is infront of a single manager, these become constants
val find = manager.findFast(edgeIn.address(in_a.bits))
val maxLgArithmetic = Mux1H(find, maxLgArithmetics)
val maxLgLogical = Mux1H(find, maxLgLogicals)
val maxLgGet = Mux1H(find, maxLgGets)
val maxLgPutFull = Mux1H(find, maxLgPutFulls)
val maxLgPutPartial = Mux1H(find, maxLgPutPartials)
val maxLgHint = Mux1H(find, maxLgHints)
val limit = if (alwaysMin) lgMinSize else
MuxLookup(in_a.bits.opcode, lgMinSize)(Array(
TLMessages.PutFullData -> maxLgPutFull,
TLMessages.PutPartialData -> maxLgPutPartial,
TLMessages.ArithmeticData -> maxLgArithmetic,
TLMessages.LogicalData -> maxLgLogical,
TLMessages.Get -> maxLgGet,
TLMessages.Hint -> maxLgHint))
val aOrig = in_a.bits.size
val aFrag = Mux(aOrig > limit, limit, aOrig)
val aOrigOH1 = UIntToOH1(aOrig, log2Ceil(maxSize))
val aFragOH1 = UIntToOH1(aFrag, log2Up(maxDownSize))
val aHasData = edgeIn.hasData(in_a.bits)
val aMask = Mux(aHasData, 0.U, aFragOH1)
val gennum = RegInit(0.U(counterBits.W))
val aFirst = gennum === 0.U
val old_gennum1 = Mux(aFirst, aOrigOH1 >> log2Ceil(beatBytes), gennum - 1.U)
val new_gennum = ~(~old_gennum1 | (aMask >> log2Ceil(beatBytes))) // ~(~x|y) is width safe
val aFragnum = ~(~(old_gennum1 >> log2Ceil(minSize/beatBytes)) | (aFragOH1 >> log2Ceil(minSize)))
val aLast = aFragnum === 0.U
val aToggle = !Mux(aFirst, dToggle, RegEnable(dToggle, aFirst))
val aFull = if (earlyAck == EarlyAck.PutFulls) Some(in_a.bits.opcode === TLMessages.PutFullData) else None
when (out.a.fire) { gennum := new_gennum }
repeater.io.repeat := !aHasData && aFragnum =/= 0.U
out.a <> in_a
out.a.bits.address := in_a.bits.address | ~(old_gennum1 << log2Ceil(beatBytes) | ~aOrigOH1 | aFragOH1 | (minSize-1).U)
out.a.bits.source := Cat(Seq(in_a.bits.source) ++ aFull ++ Seq(aToggle.asUInt, aFragnum))
out.a.bits.size := aFrag
// Optimize away some of the Repeater's registers
assert (!repeater.io.full || !aHasData)
out.a.bits.data := in.a.bits.data
val fullMask = ((BigInt(1) << beatBytes) - 1).U
assert (!repeater.io.full || in_a.bits.mask === fullMask)
out.a.bits.mask := Mux(repeater.io.full, fullMask, in.a.bits.mask)
out.a.bits.user.waiveAll :<= in.a.bits.user.subset(_.isData)
// Tie off unused channels
in.b.valid := false.B
in.c.ready := true.B
in.e.ready := true.B
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
}
}
}
}
object TLFragmenter
{
def apply(minSize: Int, maxSize: Int, alwaysMin: Boolean = false, earlyAck: EarlyAck.T = EarlyAck.None, holdFirstDeny: Boolean = false, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode =
{
if (minSize <= maxSize) {
val fragmenter = LazyModule(new TLFragmenter(minSize, maxSize, alwaysMin, earlyAck, holdFirstDeny, nameSuffix))
fragmenter.node
} else { TLEphemeralNode()(ValName("no_fragmenter")) }
}
def apply(wrapper: TLBusWrapper, nameSuffix: Option[String])(implicit p: Parameters): TLNode = apply(wrapper.beatBytes, wrapper.blockBytes, nameSuffix = nameSuffix)
def apply(wrapper: TLBusWrapper)(implicit p: Parameters): TLNode = apply(wrapper, None)
}
// Synthesizable unit tests
import freechips.rocketchip.unittest._
class TLRAMFragmenter(ramBeatBytes: Int, maxSize: Int, txns: Int)(implicit p: Parameters) extends LazyModule {
val fuzz = LazyModule(new TLFuzzer(txns))
val model = LazyModule(new TLRAMModel("Fragmenter"))
val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff), beatBytes = ramBeatBytes))
(ram.node
:= TLDelayer(0.1)
:= TLBuffer(BufferParams.flow)
:= TLDelayer(0.1)
:= TLFragmenter(ramBeatBytes, maxSize, earlyAck = EarlyAck.AllPuts)
:= TLDelayer(0.1)
:= TLBuffer(BufferParams.flow)
:= TLFragmenter(ramBeatBytes, maxSize/2)
:= TLDelayer(0.1)
:= TLBuffer(BufferParams.flow)
:= model.node
:= fuzz.node)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) with UnitTestModule {
io.finished := fuzz.module.io.finished
}
}
class TLRAMFragmenterTest(ramBeatBytes: Int, maxSize: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
val dut = Module(LazyModule(new TLRAMFragmenter(ramBeatBytes,maxSize,txns)).module)
io.finished := dut.io.finished
dut.io.start := io.start
}
File ClockDomain.scala:
package freechips.rocketchip.prci
import chisel3._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
abstract class Domain(implicit p: Parameters) extends LazyModule with HasDomainCrossing
{
def clockBundle: ClockBundle
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
childClock := clockBundle.clock
childReset := clockBundle.reset
override def provideImplicitClockToLazyChildren = true
// these are just for backwards compatibility with external devices
// that were manually wiring themselves to the domain's clock/reset input:
val clock = IO(Output(chiselTypeOf(clockBundle.clock)))
val reset = IO(Output(chiselTypeOf(clockBundle.reset)))
clock := clockBundle.clock
reset := clockBundle.reset
}
}
abstract class ClockDomain(implicit p: Parameters) extends Domain with HasClockDomainCrossing
class ClockSinkDomain(val clockSinkParams: ClockSinkParameters)(implicit p: Parameters) extends ClockDomain
{
def this(take: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSinkParameters(take = take, name = name))
val clockNode = ClockSinkNode(Seq(clockSinkParams))
def clockBundle = clockNode.in.head._1
override lazy val desiredName = (clockSinkParams.name.toSeq :+ "ClockSinkDomain").mkString
}
class ClockSourceDomain(val clockSourceParams: ClockSourceParameters)(implicit p: Parameters) extends ClockDomain
{
def this(give: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSourceParameters(give = give, name = name))
val clockNode = ClockSourceNode(Seq(clockSourceParams))
def clockBundle = clockNode.out.head._1
override lazy val desiredName = (clockSourceParams.name.toSeq :+ "ClockSourceDomain").mkString
}
abstract class ResetDomain(implicit p: Parameters) extends Domain with HasResetDomainCrossing
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File Scratchpad.scala:
package testchipip.soc
import chisel3._
import freechips.rocketchip.subsystem._
import org.chipsalliance.cde.config.{Field, Config, Parameters}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.resources.{DiplomacyUtils}
import freechips.rocketchip.prci.{ClockSinkDomain, ClockSinkParameters}
import scala.collection.immutable.{ListMap}
case class BankedScratchpadParams(
base: BigInt,
size: BigInt,
busWhere: TLBusWrapperLocation = SBUS,
banks: Int = 4,
subBanks: Int = 2,
name: String = "banked-scratchpad",
disableMonitors: Boolean = false,
buffer: BufferParams = BufferParams.none,
outerBuffer: BufferParams = BufferParams.none,
dtsEnabled: Boolean = false
)
case object BankedScratchpadKey extends Field[Seq[BankedScratchpadParams]](Nil)
class ScratchpadBank(subBanks: Int, address: AddressSet, beatBytes: Int, devOverride: MemoryDevice, buffer: BufferParams)(implicit p: Parameters) extends ClockSinkDomain(ClockSinkParameters())(p) {
val mask = (subBanks - 1) * p(CacheBlockBytes)
val xbar = TLXbar()
(0 until subBanks).map { sb =>
val ram = LazyModule(new TLRAM(
address = AddressSet(address.base + sb * p(CacheBlockBytes), address.mask - mask),
beatBytes = beatBytes,
devOverride = Some(devOverride)) {
override lazy val desiredName = s"TLRAM_ScratchpadBank"
})
ram.node := TLFragmenter(beatBytes, p(CacheBlockBytes), nameSuffix = Some("ScratchpadBank")) := TLBuffer(buffer) := xbar
}
override lazy val desiredName = "ScratchpadBank"
}
trait CanHaveBankedScratchpad { this: BaseSubsystem =>
p(BankedScratchpadKey).zipWithIndex.foreach { case (params, si) =>
val bus = locateTLBusWrapper(params.busWhere)
require (params.subBanks >= 1)
val name = params.name
val banks = params.banks
val bankStripe = p(CacheBlockBytes)*params.subBanks
val mask = (params.banks-1)*bankStripe
val device = new MemoryDevice {
override def describe(resources: ResourceBindings): Description = {
Description(describeName("memory", resources), ListMap(
"reg" -> resources.map.filterKeys(DiplomacyUtils.regFilter).flatMap(_._2).map(_.value).toList,
"device_type" -> Seq(ResourceString("memory")),
"status" -> Seq(ResourceString(if (params.dtsEnabled) "okay" else "disabled"))
))
}
}
def genBanks()(implicit p: Parameters) = (0 until banks).map { b =>
val bank = LazyModule(new ScratchpadBank(
params.subBanks,
AddressSet(params.base + bankStripe * b, params.size - 1 - mask),
bus.beatBytes,
device,
params.buffer))
bank.clockNode := bus.fixedClockNode
bus.coupleTo(s"$name-$si-$b") { bank.xbar := bus { TLBuffer(params.outerBuffer) } := _ }
}
if (params.disableMonitors) DisableMonitors { implicit p => genBanks()(p) } else genBanks()
}
}
| module ScratchpadBank( // @[ClockDomain.scala:14:9]
output auto_xbar_anon_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_xbar_anon_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_xbar_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_xbar_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_xbar_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_xbar_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [27:0] auto_xbar_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_xbar_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_xbar_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_xbar_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_xbar_anon_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_xbar_anon_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_xbar_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_xbar_anon_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_xbar_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_xbar_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_xbar_anon_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_xbar_anon_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_xbar_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_xbar_anon_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25]
input auto_clock_in_reset // @[LazyModuleImp.scala:107:25]
);
wire _buffer_auto_out_a_valid; // @[Buffer.scala:75:28]
wire [2:0] _buffer_auto_out_a_bits_opcode; // @[Buffer.scala:75:28]
wire [2:0] _buffer_auto_out_a_bits_param; // @[Buffer.scala:75:28]
wire [2:0] _buffer_auto_out_a_bits_size; // @[Buffer.scala:75:28]
wire [5:0] _buffer_auto_out_a_bits_source; // @[Buffer.scala:75:28]
wire [27:0] _buffer_auto_out_a_bits_address; // @[Buffer.scala:75:28]
wire [7:0] _buffer_auto_out_a_bits_mask; // @[Buffer.scala:75:28]
wire [63:0] _buffer_auto_out_a_bits_data; // @[Buffer.scala:75:28]
wire _buffer_auto_out_a_bits_corrupt; // @[Buffer.scala:75:28]
wire _buffer_auto_out_d_ready; // @[Buffer.scala:75:28]
wire _fragmenter_auto_anon_in_a_ready; // @[Fragmenter.scala:345:34]
wire _fragmenter_auto_anon_in_d_valid; // @[Fragmenter.scala:345:34]
wire [2:0] _fragmenter_auto_anon_in_d_bits_opcode; // @[Fragmenter.scala:345:34]
wire [2:0] _fragmenter_auto_anon_in_d_bits_size; // @[Fragmenter.scala:345:34]
wire [5:0] _fragmenter_auto_anon_in_d_bits_source; // @[Fragmenter.scala:345:34]
wire [63:0] _fragmenter_auto_anon_in_d_bits_data; // @[Fragmenter.scala:345:34]
wire _fragmenter_auto_anon_out_a_valid; // @[Fragmenter.scala:345:34]
wire [2:0] _fragmenter_auto_anon_out_a_bits_opcode; // @[Fragmenter.scala:345:34]
wire [2:0] _fragmenter_auto_anon_out_a_bits_param; // @[Fragmenter.scala:345:34]
wire [1:0] _fragmenter_auto_anon_out_a_bits_size; // @[Fragmenter.scala:345:34]
wire [9:0] _fragmenter_auto_anon_out_a_bits_source; // @[Fragmenter.scala:345:34]
wire [27:0] _fragmenter_auto_anon_out_a_bits_address; // @[Fragmenter.scala:345:34]
wire [7:0] _fragmenter_auto_anon_out_a_bits_mask; // @[Fragmenter.scala:345:34]
wire [63:0] _fragmenter_auto_anon_out_a_bits_data; // @[Fragmenter.scala:345:34]
wire _fragmenter_auto_anon_out_a_bits_corrupt; // @[Fragmenter.scala:345:34]
wire _fragmenter_auto_anon_out_d_ready; // @[Fragmenter.scala:345:34]
wire _ram_auto_in_a_ready; // @[Scratchpad.scala:33:25]
wire _ram_auto_in_d_valid; // @[Scratchpad.scala:33:25]
wire [2:0] _ram_auto_in_d_bits_opcode; // @[Scratchpad.scala:33:25]
wire [1:0] _ram_auto_in_d_bits_size; // @[Scratchpad.scala:33:25]
wire [9:0] _ram_auto_in_d_bits_source; // @[Scratchpad.scala:33:25]
wire [63:0] _ram_auto_in_d_bits_data; // @[Scratchpad.scala:33:25]
TLRAM_ScratchpadBank ram ( // @[Scratchpad.scala:33:25]
.clock (auto_clock_in_clock),
.reset (auto_clock_in_reset),
.auto_in_a_ready (_ram_auto_in_a_ready),
.auto_in_a_valid (_fragmenter_auto_anon_out_a_valid), // @[Fragmenter.scala:345:34]
.auto_in_a_bits_opcode (_fragmenter_auto_anon_out_a_bits_opcode), // @[Fragmenter.scala:345:34]
.auto_in_a_bits_param (_fragmenter_auto_anon_out_a_bits_param), // @[Fragmenter.scala:345:34]
.auto_in_a_bits_size (_fragmenter_auto_anon_out_a_bits_size), // @[Fragmenter.scala:345:34]
.auto_in_a_bits_source (_fragmenter_auto_anon_out_a_bits_source), // @[Fragmenter.scala:345:34]
.auto_in_a_bits_address (_fragmenter_auto_anon_out_a_bits_address), // @[Fragmenter.scala:345:34]
.auto_in_a_bits_mask (_fragmenter_auto_anon_out_a_bits_mask), // @[Fragmenter.scala:345:34]
.auto_in_a_bits_data (_fragmenter_auto_anon_out_a_bits_data), // @[Fragmenter.scala:345:34]
.auto_in_a_bits_corrupt (_fragmenter_auto_anon_out_a_bits_corrupt), // @[Fragmenter.scala:345:34]
.auto_in_d_ready (_fragmenter_auto_anon_out_d_ready), // @[Fragmenter.scala:345:34]
.auto_in_d_valid (_ram_auto_in_d_valid),
.auto_in_d_bits_opcode (_ram_auto_in_d_bits_opcode),
.auto_in_d_bits_size (_ram_auto_in_d_bits_size),
.auto_in_d_bits_source (_ram_auto_in_d_bits_source),
.auto_in_d_bits_data (_ram_auto_in_d_bits_data)
); // @[Scratchpad.scala:33:25]
TLFragmenter_ScratchpadBank fragmenter ( // @[Fragmenter.scala:345:34]
.clock (auto_clock_in_clock),
.reset (auto_clock_in_reset),
.auto_anon_in_a_ready (_fragmenter_auto_anon_in_a_ready),
.auto_anon_in_a_valid (_buffer_auto_out_a_valid), // @[Buffer.scala:75:28]
.auto_anon_in_a_bits_opcode (_buffer_auto_out_a_bits_opcode), // @[Buffer.scala:75:28]
.auto_anon_in_a_bits_param (_buffer_auto_out_a_bits_param), // @[Buffer.scala:75:28]
.auto_anon_in_a_bits_size (_buffer_auto_out_a_bits_size), // @[Buffer.scala:75:28]
.auto_anon_in_a_bits_source (_buffer_auto_out_a_bits_source), // @[Buffer.scala:75:28]
.auto_anon_in_a_bits_address (_buffer_auto_out_a_bits_address), // @[Buffer.scala:75:28]
.auto_anon_in_a_bits_mask (_buffer_auto_out_a_bits_mask), // @[Buffer.scala:75:28]
.auto_anon_in_a_bits_data (_buffer_auto_out_a_bits_data), // @[Buffer.scala:75:28]
.auto_anon_in_a_bits_corrupt (_buffer_auto_out_a_bits_corrupt), // @[Buffer.scala:75:28]
.auto_anon_in_d_ready (_buffer_auto_out_d_ready), // @[Buffer.scala:75:28]
.auto_anon_in_d_valid (_fragmenter_auto_anon_in_d_valid),
.auto_anon_in_d_bits_opcode (_fragmenter_auto_anon_in_d_bits_opcode),
.auto_anon_in_d_bits_size (_fragmenter_auto_anon_in_d_bits_size),
.auto_anon_in_d_bits_source (_fragmenter_auto_anon_in_d_bits_source),
.auto_anon_in_d_bits_data (_fragmenter_auto_anon_in_d_bits_data),
.auto_anon_out_a_ready (_ram_auto_in_a_ready), // @[Scratchpad.scala:33:25]
.auto_anon_out_a_valid (_fragmenter_auto_anon_out_a_valid),
.auto_anon_out_a_bits_opcode (_fragmenter_auto_anon_out_a_bits_opcode),
.auto_anon_out_a_bits_param (_fragmenter_auto_anon_out_a_bits_param),
.auto_anon_out_a_bits_size (_fragmenter_auto_anon_out_a_bits_size),
.auto_anon_out_a_bits_source (_fragmenter_auto_anon_out_a_bits_source),
.auto_anon_out_a_bits_address (_fragmenter_auto_anon_out_a_bits_address),
.auto_anon_out_a_bits_mask (_fragmenter_auto_anon_out_a_bits_mask),
.auto_anon_out_a_bits_data (_fragmenter_auto_anon_out_a_bits_data),
.auto_anon_out_a_bits_corrupt (_fragmenter_auto_anon_out_a_bits_corrupt),
.auto_anon_out_d_ready (_fragmenter_auto_anon_out_d_ready),
.auto_anon_out_d_valid (_ram_auto_in_d_valid), // @[Scratchpad.scala:33:25]
.auto_anon_out_d_bits_opcode (_ram_auto_in_d_bits_opcode), // @[Scratchpad.scala:33:25]
.auto_anon_out_d_bits_size (_ram_auto_in_d_bits_size), // @[Scratchpad.scala:33:25]
.auto_anon_out_d_bits_source (_ram_auto_in_d_bits_source), // @[Scratchpad.scala:33:25]
.auto_anon_out_d_bits_data (_ram_auto_in_d_bits_data) // @[Scratchpad.scala:33:25]
); // @[Fragmenter.scala:345:34]
TLBuffer_a28d64s6k1z3u_1 buffer ( // @[Buffer.scala:75:28]
.clock (auto_clock_in_clock),
.reset (auto_clock_in_reset),
.auto_in_a_ready (auto_xbar_anon_in_a_ready),
.auto_in_a_valid (auto_xbar_anon_in_a_valid),
.auto_in_a_bits_opcode (auto_xbar_anon_in_a_bits_opcode),
.auto_in_a_bits_param (auto_xbar_anon_in_a_bits_param),
.auto_in_a_bits_size (auto_xbar_anon_in_a_bits_size),
.auto_in_a_bits_source (auto_xbar_anon_in_a_bits_source),
.auto_in_a_bits_address (auto_xbar_anon_in_a_bits_address),
.auto_in_a_bits_mask (auto_xbar_anon_in_a_bits_mask),
.auto_in_a_bits_data (auto_xbar_anon_in_a_bits_data),
.auto_in_a_bits_corrupt (auto_xbar_anon_in_a_bits_corrupt),
.auto_in_d_ready (auto_xbar_anon_in_d_ready),
.auto_in_d_valid (auto_xbar_anon_in_d_valid),
.auto_in_d_bits_opcode (auto_xbar_anon_in_d_bits_opcode),
.auto_in_d_bits_param (auto_xbar_anon_in_d_bits_param),
.auto_in_d_bits_size (auto_xbar_anon_in_d_bits_size),
.auto_in_d_bits_source (auto_xbar_anon_in_d_bits_source),
.auto_in_d_bits_sink (auto_xbar_anon_in_d_bits_sink),
.auto_in_d_bits_denied (auto_xbar_anon_in_d_bits_denied),
.auto_in_d_bits_data (auto_xbar_anon_in_d_bits_data),
.auto_in_d_bits_corrupt (auto_xbar_anon_in_d_bits_corrupt),
.auto_out_a_ready (_fragmenter_auto_anon_in_a_ready), // @[Fragmenter.scala:345:34]
.auto_out_a_valid (_buffer_auto_out_a_valid),
.auto_out_a_bits_opcode (_buffer_auto_out_a_bits_opcode),
.auto_out_a_bits_param (_buffer_auto_out_a_bits_param),
.auto_out_a_bits_size (_buffer_auto_out_a_bits_size),
.auto_out_a_bits_source (_buffer_auto_out_a_bits_source),
.auto_out_a_bits_address (_buffer_auto_out_a_bits_address),
.auto_out_a_bits_mask (_buffer_auto_out_a_bits_mask),
.auto_out_a_bits_data (_buffer_auto_out_a_bits_data),
.auto_out_a_bits_corrupt (_buffer_auto_out_a_bits_corrupt),
.auto_out_d_ready (_buffer_auto_out_d_ready),
.auto_out_d_valid (_fragmenter_auto_anon_in_d_valid), // @[Fragmenter.scala:345:34]
.auto_out_d_bits_opcode (_fragmenter_auto_anon_in_d_bits_opcode), // @[Fragmenter.scala:345:34]
.auto_out_d_bits_size (_fragmenter_auto_anon_in_d_bits_size), // @[Fragmenter.scala:345:34]
.auto_out_d_bits_source (_fragmenter_auto_anon_in_d_bits_source), // @[Fragmenter.scala:345:34]
.auto_out_d_bits_data (_fragmenter_auto_anon_in_d_bits_data) // @[Fragmenter.scala:345:34]
); // @[Buffer.scala:75:28]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Decode.scala:
// See LICENSE.Berkeley for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util.BitPat
import chisel3.util.experimental.decode._
object DecodeLogic
{
// TODO This should be a method on BitPat
private def hasDontCare(bp: BitPat): Boolean = bp.mask.bitCount != bp.width
// Pads BitPats that are safe to pad (no don't cares), errors otherwise
private def padBP(bp: BitPat, width: Int): BitPat = {
if (bp.width == width) bp
else {
require(!hasDontCare(bp), s"Cannot pad '$bp' to '$width' bits because it has don't cares")
val diff = width - bp.width
require(diff > 0, s"Cannot pad '$bp' to '$width' because it is already '${bp.width}' bits wide!")
BitPat(0.U(diff.W)) ## bp
}
}
def apply(addr: UInt, default: BitPat, mapping: Iterable[(BitPat, BitPat)]): UInt =
chisel3.util.experimental.decode.decoder(QMCMinimizer, addr, TruthTable(mapping, default))
def apply(addr: UInt, default: Seq[BitPat], mappingIn: Iterable[(BitPat, Seq[BitPat])]): Seq[UInt] = {
val nElts = default.size
require(mappingIn.forall(_._2.size == nElts),
s"All Seq[BitPat] must be of the same length, got $nElts vs. ${mappingIn.find(_._2.size != nElts).get}"
)
val elementsGrouped = mappingIn.map(_._2).transpose
val elementWidths = elementsGrouped.zip(default).map { case (elts, default) =>
(default :: elts.toList).map(_.getWidth).max
}
val resultWidth = elementWidths.sum
val elementIndices = elementWidths.scan(resultWidth - 1) { case (l, r) => l - r }
// All BitPats that correspond to a given element in the result must have the same width in the
// chisel3 decoder. We will zero pad any BitPats that are too small so long as they dont have
// any don't cares. If there are don't cares, it is an error and the user needs to pad the
// BitPat themselves
val defaultsPadded = default.zip(elementWidths).map { case (bp, w) => padBP(bp, w) }
val mappingInPadded = mappingIn.map { case (in, elts) =>
in -> elts.zip(elementWidths).map { case (bp, w) => padBP(bp, w) }
}
val decoded = apply(addr, defaultsPadded.reduce(_ ## _), mappingInPadded.map { case (in, out) => (in, out.reduce(_ ## _)) })
elementIndices.zip(elementIndices.tail).map { case (msb, lsb) => decoded(msb, lsb + 1) }.toList
}
def apply(addr: UInt, default: Seq[BitPat], mappingIn: List[(UInt, Seq[BitPat])]): Seq[UInt] =
apply(addr, default, mappingIn.map(m => (BitPat(m._1), m._2)).asInstanceOf[Iterable[(BitPat, Seq[BitPat])]])
def apply(addr: UInt, trues: Iterable[UInt], falses: Iterable[UInt]): Bool =
apply(addr, BitPat.dontCare(1), trues.map(BitPat(_) -> BitPat("b1")) ++ falses.map(BitPat(_) -> BitPat("b0"))).asBool
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File decode.scala:
//******************************************************************************
// Copyright (c) 2015 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
package boom.v3.exu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.rocket.Instructions._
import freechips.rocketchip.rocket.Instructions32
import freechips.rocketchip.rocket.CustomInstructions._
import freechips.rocketchip.rocket.RVCExpander
import freechips.rocketchip.rocket.{CSR,Causes}
import freechips.rocketchip.util.{uintToBitPat,UIntIsOneOf}
import FUConstants._
import boom.v3.common._
import boom.v3.util._
// scalastyle:off
/**
* Abstract trait giving defaults and other relevant values to different Decode constants/
*/
abstract trait DecodeConstants
extends freechips.rocketchip.rocket.constants.ScalarOpConstants
with freechips.rocketchip.rocket.constants.MemoryOpConstants
{
val xpr64 = Y // TODO inform this from xLen
val DC2 = BitPat.dontCare(2) // Makes the listing below more readable
def decode_default: List[BitPat] =
// frs3_en wakeup_delay
// is val inst? | imm sel | bypassable (aka, known/fixed latency)
// | is fp inst? | | uses_ldq | | is_br
// | | is single-prec? rs1 regtype | | | uses_stq | | |
// | | | micro-code | rs2 type| | | | is_amo | | |
// | | | | iq-type func unit | | | | | | | is_fence | | |
// | | | | | | | | | | | | | | is_fencei | | | is breakpoint or ecall?
// | | | | | | dst | | | | | | | | | mem | | | | is unique? (clear pipeline for it)
// | | | | | | regtype | | | | | | | | | cmd | | | | | flush on commit
// | | | | | | | | | | | | | | | | | | | | | | | csr cmd
// | | | | | | | | | | | | | | | | | | | | | | | |
List(N, N, X, uopX , IQT_INT, FU_X , RT_X , DC2 ,DC2 ,X, IS_X, X, X, X, X, N, M_X, DC2, X, X, N, N, X, CSR.X)
val table: Array[(BitPat, List[BitPat])]
}
// scalastyle:on
/**
* Decoded control signals
*/
class CtrlSigs extends Bundle
{
val legal = Bool()
val fp_val = Bool()
val fp_single = Bool()
val uopc = UInt(UOPC_SZ.W)
val iq_type = UInt(IQT_SZ.W)
val fu_code = UInt(FUC_SZ.W)
val dst_type = UInt(2.W)
val rs1_type = UInt(2.W)
val rs2_type = UInt(2.W)
val frs3_en = Bool()
val imm_sel = UInt(IS_X.getWidth.W)
val uses_ldq = Bool()
val uses_stq = Bool()
val is_amo = Bool()
val is_fence = Bool()
val is_fencei = Bool()
val mem_cmd = UInt(freechips.rocketchip.rocket.M_SZ.W)
val wakeup_delay = UInt(2.W)
val bypassable = Bool()
val is_br = Bool()
val is_sys_pc2epc = Bool()
val inst_unique = Bool()
val flush_on_commit = Bool()
val csr_cmd = UInt(freechips.rocketchip.rocket.CSR.SZ.W)
val rocc = Bool()
def decode(inst: UInt, table: Iterable[(BitPat, List[BitPat])]) = {
val decoder = freechips.rocketchip.rocket.DecodeLogic(inst, XDecode.decode_default, table)
val sigs =
Seq(legal, fp_val, fp_single, uopc, iq_type, fu_code, dst_type, rs1_type,
rs2_type, frs3_en, imm_sel, uses_ldq, uses_stq, is_amo,
is_fence, is_fencei, mem_cmd, wakeup_delay, bypassable,
is_br, is_sys_pc2epc, inst_unique, flush_on_commit, csr_cmd)
sigs zip decoder map {case(s,d) => s := d}
rocc := false.B
this
}
}
// scalastyle:off
/**
* Decode constants for RV32
*/
object X32Decode extends DecodeConstants
{
// frs3_en wakeup_delay
// is val inst? | imm sel | bypassable (aka, known/fixed latency)
// | is fp inst? | | uses_ldq | | is_br
// | | is single-prec? rs1 regtype | | | uses_stq | | |
// | | | micro-code | rs2 type| | | | is_amo | | |
// | | | | iq-type func unit | | | | | | | is_fence | | |
// | | | | | | | | | | | | | | is_fencei | | | is breakpoint or ecall?
// | | | | | | dst | | | | | | | | | mem | | | | is unique? (clear pipeline for it)
// | | | | | | regtype | | | | | | | | | cmd | | | | | flush on commit
// | | | | | | | | | | | | | | | | | | | | | | | csr cmd
val table: Array[(BitPat, List[BitPat])] = Array(// | | | | | | | | | | | | | | | | | |
Instructions32.SLLI ->
List(Y, N, X, uopSLLI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),
Instructions32.SRLI ->
List(Y, N, X, uopSRLI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),
Instructions32.SRAI ->
List(Y, N, X, uopSRAI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N)
)
}
/**
* Decode constants for RV64
*/
object X64Decode extends DecodeConstants
{
// frs3_en wakeup_delay
// is val inst? | imm sel | bypassable (aka, known/fixed latency)
// | is fp inst? | | uses_ldq | | is_br
// | | is single-prec? rs1 regtype | | | uses_stq | | |
// | | | micro-code | rs2 type| | | | is_amo | | |
// | | | | iq-type func unit | | | | | | | is_fence | | |
// | | | | | | | | | | | | | | is_fencei | | | is breakpoint or ecall?
// | | | | | | dst | | | | | | | | | mem | | | | is unique? (clear pipeline for it)
// | | | | | | regtype | | | | | | | | | cmd | | | | | flush on commit
// | | | | | | | | | | | | | | | | | | | | | | | csr cmd
val table: Array[(BitPat, List[BitPat])] = Array(// | | | | | | | | | | | | | | | | | |
LD -> List(Y, N, X, uopLD , IQT_MEM, FU_MEM , RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, N, N, M_XRD, 3.U, N, N, N, N, N, CSR.N),
LWU -> List(Y, N, X, uopLD , IQT_MEM, FU_MEM , RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, N, N, M_XRD, 3.U, N, N, N, N, N, CSR.N),
SD -> List(Y, N, X, uopSTA , IQT_MEM, FU_MEM , RT_X , RT_FIX, RT_FIX, N, IS_S, N, Y, N, N, N, M_XWR, 0.U, N, N, N, N, N, CSR.N),
SLLI -> List(Y, N, X, uopSLLI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),
SRLI -> List(Y, N, X, uopSRLI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),
SRAI -> List(Y, N, X, uopSRAI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),
ADDIW -> List(Y, N, X, uopADDIW, IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),
SLLIW -> List(Y, N, X, uopSLLIW, IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),
SRAIW -> List(Y, N, X, uopSRAIW, IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),
SRLIW -> List(Y, N, X, uopSRLIW, IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),
ADDW -> List(Y, N, X, uopADDW , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),
SUBW -> List(Y, N, X, uopSUBW , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),
SLLW -> List(Y, N, X, uopSLLW , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),
SRAW -> List(Y, N, X, uopSRAW , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),
SRLW -> List(Y, N, X, uopSRLW , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N)
)
}
/**
* Overall Decode constants
*/
object XDecode extends DecodeConstants
{
// frs3_en wakeup_delay
// is val inst? | imm sel | bypassable (aka, known/fixed latency)
// | is fp inst? | | uses_ldq | | is_br
// | | is single-prec? rs1 regtype | | | uses_stq | | |
// | | | micro-code | rs2 type| | | | is_amo | | |
// | | | | iq-type func unit | | | | | | | is_fence | | |
// | | | | | | | | | | | | | | is_fencei | | | is breakpoint or ecall?
// | | | | | | dst | | | | | | | | | mem | | | | is unique? (clear pipeline for it)
// | | | | | | regtype | | | | | | | | | cmd | | | | | flush on commit
// | | | | | | | | | | | | | | | | | | | | | | | csr cmd
val table: Array[(BitPat, List[BitPat])] = Array(// | | | | | | | | | | | | | | | | | |
LW -> List(Y, N, X, uopLD , IQT_MEM, FU_MEM , RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, N, N, M_XRD, 3.U, N, N, N, N, N, CSR.N),
LH -> List(Y, N, X, uopLD , IQT_MEM, FU_MEM , RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, N, N, M_XRD, 3.U, N, N, N, N, N, CSR.N),
LHU -> List(Y, N, X, uopLD , IQT_MEM, FU_MEM , RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, N, N, M_XRD, 3.U, N, N, N, N, N, CSR.N),
LB -> List(Y, N, X, uopLD , IQT_MEM, FU_MEM , RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, N, N, M_XRD, 3.U, N, N, N, N, N, CSR.N),
LBU -> List(Y, N, X, uopLD , IQT_MEM, FU_MEM , RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, N, N, M_XRD, 3.U, N, N, N, N, N, CSR.N),
SW -> List(Y, N, X, uopSTA , IQT_MEM, FU_MEM , RT_X , RT_FIX, RT_FIX, N, IS_S, N, Y, N, N, N, M_XWR, 0.U, N, N, N, N, N, CSR.N),
SH -> List(Y, N, X, uopSTA , IQT_MEM, FU_MEM , RT_X , RT_FIX, RT_FIX, N, IS_S, N, Y, N, N, N, M_XWR, 0.U, N, N, N, N, N, CSR.N),
SB -> List(Y, N, X, uopSTA , IQT_MEM, FU_MEM , RT_X , RT_FIX, RT_FIX, N, IS_S, N, Y, N, N, N, M_XWR, 0.U, N, N, N, N, N, CSR.N),
LUI -> List(Y, N, X, uopLUI , IQT_INT, FU_ALU , RT_FIX, RT_X , RT_X , N, IS_U, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),
ADDI -> List(Y, N, X, uopADDI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),
ANDI -> List(Y, N, X, uopANDI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),
ORI -> List(Y, N, X, uopORI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),
XORI -> List(Y, N, X, uopXORI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),
SLTI -> List(Y, N, X, uopSLTI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),
SLTIU -> List(Y, N, X, uopSLTIU, IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),
SLL -> List(Y, N, X, uopSLL , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),
ADD -> List(Y, N, X, uopADD , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),
SUB -> List(Y, N, X, uopSUB , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),
SLT -> List(Y, N, X, uopSLT , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),
SLTU -> List(Y, N, X, uopSLTU , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),
AND -> List(Y, N, X, uopAND , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),
OR -> List(Y, N, X, uopOR , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),
XOR -> List(Y, N, X, uopXOR , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),
SRA -> List(Y, N, X, uopSRA , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),
SRL -> List(Y, N, X, uopSRL , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),
MUL -> List(Y, N, X, uopMUL , IQT_INT, FU_MUL , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
MULH -> List(Y, N, X, uopMULH , IQT_INT, FU_MUL , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
MULHU -> List(Y, N, X, uopMULHU, IQT_INT, FU_MUL , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
MULHSU -> List(Y, N, X, uopMULHSU,IQT_INT, FU_MUL , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
MULW -> List(Y, N, X, uopMULW , IQT_INT, FU_MUL , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
DIV -> List(Y, N, X, uopDIV , IQT_INT, FU_DIV , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
DIVU -> List(Y, N, X, uopDIVU , IQT_INT, FU_DIV , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
REM -> List(Y, N, X, uopREM , IQT_INT, FU_DIV , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
REMU -> List(Y, N, X, uopREMU , IQT_INT, FU_DIV , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
DIVW -> List(Y, N, X, uopDIVW , IQT_INT, FU_DIV , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
DIVUW -> List(Y, N, X, uopDIVUW, IQT_INT, FU_DIV , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
REMW -> List(Y, N, X, uopREMW , IQT_INT, FU_DIV , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
REMUW -> List(Y, N, X, uopREMUW, IQT_INT, FU_DIV , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
AUIPC -> List(Y, N, X, uopAUIPC, IQT_INT, FU_JMP , RT_FIX, RT_X , RT_X , N, IS_U, N, N, N, N, N, M_X , 1.U, N, N, N, N, N, CSR.N), // use BRU for the PC read
JAL -> List(Y, N, X, uopJAL , IQT_INT, FU_JMP , RT_FIX, RT_X , RT_X , N, IS_J, N, N, N, N, N, M_X , 1.U, N, N, N, N, N, CSR.N),
JALR -> List(Y, N, X, uopJALR , IQT_INT, FU_JMP , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, N, N, N, N, N, CSR.N),
BEQ -> List(Y, N, X, uopBEQ , IQT_INT, FU_ALU , RT_X , RT_FIX, RT_FIX, N, IS_B, N, N, N, N, N, M_X , 0.U, N, Y, N, N, N, CSR.N),
BNE -> List(Y, N, X, uopBNE , IQT_INT, FU_ALU , RT_X , RT_FIX, RT_FIX, N, IS_B, N, N, N, N, N, M_X , 0.U, N, Y, N, N, N, CSR.N),
BGE -> List(Y, N, X, uopBGE , IQT_INT, FU_ALU , RT_X , RT_FIX, RT_FIX, N, IS_B, N, N, N, N, N, M_X , 0.U, N, Y, N, N, N, CSR.N),
BGEU -> List(Y, N, X, uopBGEU , IQT_INT, FU_ALU , RT_X , RT_FIX, RT_FIX, N, IS_B, N, N, N, N, N, M_X , 0.U, N, Y, N, N, N, CSR.N),
BLT -> List(Y, N, X, uopBLT , IQT_INT, FU_ALU , RT_X , RT_FIX, RT_FIX, N, IS_B, N, N, N, N, N, M_X , 0.U, N, Y, N, N, N, CSR.N),
BLTU -> List(Y, N, X, uopBLTU , IQT_INT, FU_ALU , RT_X , RT_FIX, RT_FIX, N, IS_B, N, N, N, N, N, M_X , 0.U, N, Y, N, N, N, CSR.N),
// I-type, the immediate12 holds the CSR register.
CSRRW -> List(Y, N, X, uopCSRRW, IQT_INT, FU_CSR , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.W),
CSRRS -> List(Y, N, X, uopCSRRS, IQT_INT, FU_CSR , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.S),
CSRRC -> List(Y, N, X, uopCSRRC, IQT_INT, FU_CSR , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.C),
CSRRWI -> List(Y, N, X, uopCSRRWI,IQT_INT, FU_CSR , RT_FIX, RT_PAS, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.W),
CSRRSI -> List(Y, N, X, uopCSRRSI,IQT_INT, FU_CSR , RT_FIX, RT_PAS, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.S),
CSRRCI -> List(Y, N, X, uopCSRRCI,IQT_INT, FU_CSR , RT_FIX, RT_PAS, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.C),
SFENCE_VMA->List(Y,N, X, uopSFENCE,IQT_MEM, FU_MEM , RT_X , RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N,M_SFENCE,0.U,N, N, N, Y, Y, CSR.N),
ECALL -> List(Y, N, X, uopERET ,IQT_INT, FU_CSR , RT_X , RT_X , RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, Y, Y, Y, CSR.I),
EBREAK -> List(Y, N, X, uopERET ,IQT_INT, FU_CSR , RT_X , RT_X , RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, Y, Y, Y, CSR.I),
SRET -> List(Y, N, X, uopERET ,IQT_INT, FU_CSR , RT_X , RT_X , RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.I),
MRET -> List(Y, N, X, uopERET ,IQT_INT, FU_CSR , RT_X , RT_X , RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.I),
DRET -> List(Y, N, X, uopERET ,IQT_INT, FU_CSR , RT_X , RT_X , RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.I),
WFI -> List(Y, N, X, uopWFI ,IQT_INT, FU_CSR , RT_X , RT_X , RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.I),
FENCE_I -> List(Y, N, X, uopNOP , IQT_INT, FU_X , RT_X , RT_X , RT_X , N, IS_X, N, N, N, N, Y, M_X , 0.U, N, N, N, Y, Y, CSR.N),
FENCE -> List(Y, N, X, uopFENCE, IQT_INT, FU_MEM , RT_X , RT_X , RT_X , N, IS_X, N, Y, N, Y, N, M_X , 0.U, N, N, N, Y, Y, CSR.N), // TODO PERF make fence higher performance
// currently serializes pipeline
// frs3_en wakeup_delay
// is val inst? | imm sel | bypassable (aka, known/fixed latency)
// | is fp inst? | | uses_ldq | | is_br
// | | is single-prec? rs1 regtype | | | uses_stq | | |
// | | | micro-code | rs2 type| | | | is_amo | | |
// | | | | iq-type func unit | | | | | | | is_fence | | |
// | | | | | | | | | | | | | | is_fencei | | | is breakpoint or ecall?
// | | | | | | dst | | | | | | | | | mem | | | | is unique? (clear pipeline for it)
// | | | | | | regtype | | | | | | | | | cmd | | | | | flush on commit
// | | | | | | | | | | | | | | | | | | | | | | | csr cmd
// A-type | | | | | | | | | | | | | | | | | | | | | | | |
AMOADD_W-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_ADD, 0.U,N, N, N, Y, Y, CSR.N), // TODO make AMOs higherperformance
AMOXOR_W-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_XOR, 0.U,N, N, N, Y, Y, CSR.N),
AMOSWAP_W->List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_SWAP,0.U,N, N, N, Y, Y, CSR.N),
AMOAND_W-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_AND, 0.U,N, N, N, Y, Y, CSR.N),
AMOOR_W -> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_OR, 0.U,N, N, N, Y, Y, CSR.N),
AMOMIN_W-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_MIN, 0.U,N, N, N, Y, Y, CSR.N),
AMOMINU_W->List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_MINU,0.U,N, N, N, Y, Y, CSR.N),
AMOMAX_W-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_MAX, 0.U,N, N, N, Y, Y, CSR.N),
AMOMAXU_W->List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_MAXU,0.U,N, N, N, Y, Y, CSR.N),
AMOADD_D-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_ADD, 0.U,N, N, N, Y, Y, CSR.N),
AMOXOR_D-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_XOR, 0.U,N, N, N, Y, Y, CSR.N),
AMOSWAP_D->List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_SWAP,0.U,N, N, N, Y, Y, CSR.N),
AMOAND_D-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_AND, 0.U,N, N, N, Y, Y, CSR.N),
AMOOR_D -> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_OR, 0.U,N, N, N, Y, Y, CSR.N),
AMOMIN_D-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_MIN, 0.U,N, N, N, Y, Y, CSR.N),
AMOMINU_D->List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_MINU,0.U,N, N, N, Y, Y, CSR.N),
AMOMAX_D-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_MAX, 0.U,N, N, N, Y, Y, CSR.N),
AMOMAXU_D->List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_MAXU,0.U,N, N, N, Y, Y, CSR.N),
LR_W -> List(Y, N, X, uopLD , IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_X , N, IS_X, Y, N, N, N, N, M_XLR , 0.U,N, N, N, Y, Y, CSR.N),
LR_D -> List(Y, N, X, uopLD , IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_X , N, IS_X, Y, N, N, N, N, M_XLR , 0.U,N, N, N, Y, Y, CSR.N),
SC_W -> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XSC , 0.U,N, N, N, Y, Y, CSR.N),
SC_D -> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XSC , 0.U,N, N, N, Y, Y, CSR.N)
)
}
/**
* FP Decode constants
*/
object FDecode extends DecodeConstants
{
val table: Array[(BitPat, List[BitPat])] = Array(
// frs3_en wakeup_delay
// | imm sel | bypassable (aka, known/fixed latency)
// | | uses_ldq | | is_br
// is val inst? rs1 regtype | | | uses_stq | | |
// | is fp inst? | rs2 type| | | | is_amo | | |
// | | is dst single-prec? | | | | | | | is_fence | | |
// | | | micro-opcode | | | | | | | | is_fencei | | | is breakpoint or ecall
// | | | | iq_type func dst | | | | | | | | | mem | | | | is unique? (clear pipeline for it)
// | | | | | unit regtype | | | | | | | | | cmd | | | | | flush on commit
// | | | | | | | | | | | | | | | | | | | | | | | csr cmd
FLW -> List(Y, Y, Y, uopLD , IQT_MEM, FU_MEM, RT_FLT, RT_FIX, RT_X , N, IS_I, Y, N, N, N, N, M_XRD, 0.U, N, N, N, N, N, CSR.N),
FLD -> List(Y, Y, N, uopLD , IQT_MEM, FU_MEM, RT_FLT, RT_FIX, RT_X , N, IS_I, Y, N, N, N, N, M_XRD, 0.U, N, N, N, N, N, CSR.N),
FSW -> List(Y, Y, Y, uopSTA , IQT_MFP,FU_F2IMEM,RT_X , RT_FIX, RT_FLT, N, IS_S, N, Y, N, N, N, M_XWR, 0.U, N, N, N, N, N, CSR.N), // sort of a lie; broken into two micro-ops
FSD -> List(Y, Y, N, uopSTA , IQT_MFP,FU_F2IMEM,RT_X , RT_FIX, RT_FLT, N, IS_S, N, Y, N, N, N, M_XWR, 0.U, N, N, N, N, N, CSR.N),
FCLASS_S-> List(Y, Y, Y, uopFCLASS_S,IQT_FP , FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FCLASS_D-> List(Y, Y, N, uopFCLASS_D,IQT_FP , FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FMV_W_X -> List(Y, Y, Y, uopFMV_W_X, IQT_INT, FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FMV_D_X -> List(Y, Y, N, uopFMV_D_X, IQT_INT, FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FMV_X_W -> List(Y, Y, Y, uopFMV_X_W, IQT_FP , FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FMV_X_D -> List(Y, Y, N, uopFMV_X_D, IQT_FP , FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FSGNJ_S -> List(Y, Y, Y, uopFSGNJ_S, IQT_FP , FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FSGNJ_D -> List(Y, Y, N, uopFSGNJ_D, IQT_FP , FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FSGNJX_S-> List(Y, Y, Y, uopFSGNJ_S, IQT_FP , FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FSGNJX_D-> List(Y, Y, N, uopFSGNJ_D, IQT_FP , FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FSGNJN_S-> List(Y, Y, Y, uopFSGNJ_S, IQT_FP , FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FSGNJN_D-> List(Y, Y, N, uopFSGNJ_D, IQT_FP , FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
// FP to FP
FCVT_S_D-> List(Y, Y, Y, uopFCVT_S_D,IQT_FP , FU_FPU, RT_FLT, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FCVT_D_S-> List(Y, Y, N, uopFCVT_D_S,IQT_FP , FU_FPU, RT_FLT, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
// Int to FP
FCVT_S_W-> List(Y, Y, Y, uopFCVT_S_X, IQT_INT,FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FCVT_S_WU->List(Y, Y, Y, uopFCVT_S_X, IQT_INT,FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FCVT_S_L-> List(Y, Y, Y, uopFCVT_S_X, IQT_INT,FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FCVT_S_LU->List(Y, Y, Y, uopFCVT_S_X, IQT_INT,FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FCVT_D_W-> List(Y, Y, N, uopFCVT_D_X, IQT_INT,FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FCVT_D_WU->List(Y, Y, N, uopFCVT_D_X, IQT_INT,FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FCVT_D_L-> List(Y, Y, N, uopFCVT_D_X, IQT_INT,FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FCVT_D_LU->List(Y, Y, N, uopFCVT_D_X, IQT_INT,FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
// FP to Int
FCVT_W_S-> List(Y, Y, Y, uopFCVT_X_S, IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FCVT_WU_S->List(Y, Y, Y, uopFCVT_X_S, IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FCVT_L_S-> List(Y, Y, Y, uopFCVT_X_S, IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FCVT_LU_S->List(Y, Y, Y, uopFCVT_X_S, IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FCVT_W_D-> List(Y, Y, N, uopFCVT_X_D, IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FCVT_WU_D->List(Y, Y, N, uopFCVT_X_D, IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FCVT_L_D-> List(Y, Y, N, uopFCVT_X_D, IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FCVT_LU_D->List(Y, Y, N, uopFCVT_X_D, IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
// "fp_single" is used for wb_data formatting (and debugging)
FEQ_S ->List(Y, Y, Y, uopCMPR_S , IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FLT_S ->List(Y, Y, Y, uopCMPR_S , IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FLE_S ->List(Y, Y, Y, uopCMPR_S , IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FEQ_D ->List(Y, Y, N, uopCMPR_D , IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FLT_D ->List(Y, Y, N, uopCMPR_D , IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FLE_D ->List(Y, Y, N, uopCMPR_D , IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FMIN_S ->List(Y, Y, Y,uopFMINMAX_S,IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FMAX_S ->List(Y, Y, Y,uopFMINMAX_S,IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FMIN_D ->List(Y, Y, N,uopFMINMAX_D,IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FMAX_D ->List(Y, Y, N,uopFMINMAX_D,IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FADD_S ->List(Y, Y, Y, uopFADD_S , IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FSUB_S ->List(Y, Y, Y, uopFSUB_S , IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FMUL_S ->List(Y, Y, Y, uopFMUL_S , IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FADD_D ->List(Y, Y, N, uopFADD_D , IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FSUB_D ->List(Y, Y, N, uopFSUB_D , IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FMUL_D ->List(Y, Y, N, uopFMUL_D , IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FMADD_S ->List(Y, Y, Y, uopFMADD_S, IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, Y, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FMSUB_S ->List(Y, Y, Y, uopFMSUB_S, IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, Y, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FNMADD_S ->List(Y, Y, Y, uopFNMADD_S,IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, Y, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FNMSUB_S ->List(Y, Y, Y, uopFNMSUB_S,IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, Y, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FMADD_D ->List(Y, Y, N, uopFMADD_D, IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, Y, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FMSUB_D ->List(Y, Y, N, uopFMSUB_D, IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, Y, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FNMADD_D ->List(Y, Y, N, uopFNMADD_D,IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, Y, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FNMSUB_D ->List(Y, Y, N, uopFNMSUB_D,IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, Y, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N)
)
}
/**
* FP Divide SquareRoot Constants
*/
object FDivSqrtDecode extends DecodeConstants
{
val table: Array[(BitPat, List[BitPat])] = Array(
// frs3_en wakeup_delay
// | imm sel | bypassable (aka, known/fixed latency)
// | | uses_ldq | | is_br
// is val inst? rs1 regtype | | | uses_stq | | |
// | is fp inst? | rs2 type| | | | is_amo | | |
// | | is dst single-prec? | | | | | | | is_fence | | |
// | | | micro-opcode | | | | | | | | is_fencei | | | is breakpoint or ecall
// | | | | iq-type func dst | | | | | | | | | mem | | | | is unique? (clear pipeline for it)
// | | | | | unit regtype | | | | | | | | | cmd | | | | | flush on commit
// | | | | | | | | | | | | | | | | | | | | | | | csr cmd
FDIV_S ->List(Y, Y, Y, uopFDIV_S , IQT_FP, FU_FDV, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FDIV_D ->List(Y, Y, N, uopFDIV_D , IQT_FP, FU_FDV, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FSQRT_S ->List(Y, Y, Y, uopFSQRT_S, IQT_FP, FU_FDV, RT_FLT, RT_FLT, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FSQRT_D ->List(Y, Y, N, uopFSQRT_D, IQT_FP, FU_FDV, RT_FLT, RT_FLT, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N)
)
}
//scalastyle:on
/**
* RoCC initial decode
*/
object RoCCDecode extends DecodeConstants
{
// Note: We use FU_CSR since CSR instructions cannot co-execute with RoCC instructions
// frs3_en wakeup_delay
// is val inst? | imm sel | bypassable (aka, known/fixed latency)
// | is fp inst? | | uses_ldq | | is_br
// | | is single-prec rs1 regtype | | | uses_stq | | |
// | | | | rs2 type| | | | is_amo | | |
// | | | micro-code func unit | | | | | | | is_fence | | |
// | | | | iq-type | | | | | | | | | is_fencei | | | is breakpoint or ecall?
// | | | | | | dst | | | | | | | | | mem | | | | is unique? (clear pipeline for it)
// | | | | | | regtype | | | | | | | | | cmd | | | | | flush on commit
// | | | | | | | | | | | | | | | | | | | | | | | csr cmd
// | | | | | | | | | | | | | | | | | | | | | | | |
val table: Array[(BitPat, List[BitPat])] = Array(// | | | | | | | | | | | | | | | | | | |
CUSTOM0 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_X , RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
CUSTOM0_RS1 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_FIX, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
CUSTOM0_RS1_RS2 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
CUSTOM0_RD ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_X , RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
CUSTOM0_RD_RS1 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_FIX, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
CUSTOM0_RD_RS1_RS2 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
CUSTOM1 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_X , RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
CUSTOM1_RS1 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_FIX, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
CUSTOM1_RS1_RS2 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
CUSTOM1_RD ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_X , RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
CUSTOM1_RD_RS1 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_FIX, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
CUSTOM1_RD_RS1_RS2 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
CUSTOM2 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_X , RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
CUSTOM2_RS1 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_FIX, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
CUSTOM2_RS1_RS2 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
CUSTOM2_RD ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_X , RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
CUSTOM2_RD_RS1 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_FIX, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
CUSTOM2_RD_RS1_RS2 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
CUSTOM3 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_X , RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
CUSTOM3_RS1 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_FIX, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
CUSTOM3_RS1_RS2 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
CUSTOM3_RD ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_X , RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
CUSTOM3_RD_RS1 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_FIX, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
CUSTOM3_RD_RS1_RS2 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N)
)
}
/**
* IO bundle for the Decode unit
*/
class DecodeUnitIo(implicit p: Parameters) extends BoomBundle
{
val enq = new Bundle { val uop = Input(new MicroOp()) }
val deq = new Bundle { val uop = Output(new MicroOp()) }
// from CSRFile
val status = Input(new freechips.rocketchip.rocket.MStatus())
val csr_decode = Flipped(new freechips.rocketchip.rocket.CSRDecodeIO)
val interrupt = Input(Bool())
val interrupt_cause = Input(UInt(xLen.W))
}
/**
* Decode unit that takes in a single instruction and generates a MicroOp.
*/
class DecodeUnit(implicit p: Parameters) extends BoomModule
with freechips.rocketchip.rocket.constants.MemoryOpConstants
{
val io = IO(new DecodeUnitIo)
val uop = Wire(new MicroOp())
uop := io.enq.uop
var decode_table = XDecode.table
if (usingFPU) decode_table ++= FDecode.table
if (usingFPU && usingFDivSqrt) decode_table ++= FDivSqrtDecode.table
if (usingRoCC) decode_table ++= RoCCDecode.table
decode_table ++= (if (xLen == 64) X64Decode.table else X32Decode.table)
val inst = uop.inst
val cs = Wire(new CtrlSigs()).decode(inst, decode_table)
// Exception Handling
io.csr_decode.inst := inst
val csr_en = cs.csr_cmd.isOneOf(CSR.S, CSR.C, CSR.W)
val csr_ren = cs.csr_cmd.isOneOf(CSR.S, CSR.C) && uop.lrs1 === 0.U
val system_insn = cs.csr_cmd === CSR.I
val sfence = cs.uopc === uopSFENCE
val cs_legal = cs.legal
// dontTouch(cs_legal)
val id_illegal_insn = !cs_legal ||
cs.fp_val && io.csr_decode.fp_illegal || // TODO check for illegal rm mode: (io.fpu.illegal_rm)
cs.rocc && io.csr_decode.rocc_illegal ||
cs.is_amo && !io.status.isa('a'-'a') ||
(cs.fp_val && !cs.fp_single) && !io.status.isa('d'-'a') ||
csr_en && (io.csr_decode.read_illegal || !csr_ren && io.csr_decode.write_illegal) ||
((sfence || system_insn) && io.csr_decode.system_illegal)
// cs.div && !csr.io.status.isa('m'-'a') || TODO check for illegal div instructions
def checkExceptions(x: Seq[(Bool, UInt)]) =
(x.map(_._1).reduce(_||_), PriorityMux(x))
val (xcpt_valid, xcpt_cause) = checkExceptions(List(
(io.interrupt && !io.enq.uop.is_sfb, io.interrupt_cause), // Disallow interrupts while we are handling a SFB
(uop.bp_debug_if, (CSR.debugTriggerCause).U),
(uop.bp_xcpt_if, (Causes.breakpoint).U),
(uop.xcpt_pf_if, (Causes.fetch_page_fault).U),
(uop.xcpt_ae_if, (Causes.fetch_access).U),
(id_illegal_insn, (Causes.illegal_instruction).U)))
uop.exception := xcpt_valid
uop.exc_cause := xcpt_cause
//-------------------------------------------------------------
uop.uopc := cs.uopc
uop.iq_type := cs.iq_type
uop.fu_code := cs.fu_code
// x-registers placed in 0-31, f-registers placed in 32-63.
// This allows us to straight-up compare register specifiers and not need to
// verify the rtypes (e.g., bypassing in rename).
uop.ldst := inst(RD_MSB,RD_LSB)
uop.lrs1 := inst(RS1_MSB,RS1_LSB)
uop.lrs2 := inst(RS2_MSB,RS2_LSB)
uop.lrs3 := inst(RS3_MSB,RS3_LSB)
uop.ldst_val := cs.dst_type =/= RT_X && !(uop.ldst === 0.U && uop.dst_rtype === RT_FIX)
uop.dst_rtype := cs.dst_type
uop.lrs1_rtype := cs.rs1_type
uop.lrs2_rtype := cs.rs2_type
uop.frs3_en := cs.frs3_en
uop.ldst_is_rs1 := uop.is_sfb_shadow
// SFB optimization
when (uop.is_sfb_shadow && cs.rs2_type === RT_X) {
uop.lrs2_rtype := RT_FIX
uop.lrs2 := inst(RD_MSB,RD_LSB)
uop.ldst_is_rs1 := false.B
} .elsewhen (uop.is_sfb_shadow && cs.uopc === uopADD && inst(RS1_MSB,RS1_LSB) === 0.U) {
uop.uopc := uopMOV
uop.lrs1 := inst(RD_MSB, RD_LSB)
uop.ldst_is_rs1 := true.B
}
when (uop.is_sfb_br) {
uop.fu_code := FU_JMP
}
uop.fp_val := cs.fp_val
uop.fp_single := cs.fp_single // TODO use this signal instead of the FPU decode's table signal?
uop.mem_cmd := cs.mem_cmd
uop.mem_size := Mux(cs.mem_cmd.isOneOf(M_SFENCE, M_FLUSH_ALL), Cat(uop.lrs2 =/= 0.U, uop.lrs1 =/= 0.U), inst(13,12))
uop.mem_signed := !inst(14)
uop.uses_ldq := cs.uses_ldq
uop.uses_stq := cs.uses_stq
uop.is_amo := cs.is_amo
uop.is_fence := cs.is_fence
uop.is_fencei := cs.is_fencei
uop.is_sys_pc2epc := cs.is_sys_pc2epc
uop.is_unique := cs.inst_unique
uop.flush_on_commit := cs.flush_on_commit || (csr_en && !csr_ren && io.csr_decode.write_flush)
uop.bypassable := cs.bypassable
//-------------------------------------------------------------
// immediates
// repackage the immediate, and then pass the fewest number of bits around
val di24_20 = Mux(cs.imm_sel === IS_B || cs.imm_sel === IS_S, inst(11,7), inst(24,20))
uop.imm_packed := Cat(inst(31,25), di24_20, inst(19,12))
//-------------------------------------------------------------
uop.is_br := cs.is_br
uop.is_jal := (uop.uopc === uopJAL)
uop.is_jalr := (uop.uopc === uopJALR)
// uop.is_jump := cs.is_jal || (uop.uopc === uopJALR)
// uop.is_ret := (uop.uopc === uopJALR) &&
// (uop.ldst === X0) &&
// (uop.lrs1 === RA)
// uop.is_call := (uop.uopc === uopJALR || uop.uopc === uopJAL) &&
// (uop.ldst === RA)
//-------------------------------------------------------------
io.deq.uop := uop
}
/**
* Smaller Decode unit for the Frontend to decode different
* branches.
* Accepts EXPANDED RVC instructions
*/
class BranchDecodeSignals(implicit p: Parameters) extends BoomBundle
{
val is_ret = Bool()
val is_call = Bool()
val target = UInt(vaddrBitsExtended.W)
val cfi_type = UInt(CFI_SZ.W)
// Is this branch a short forwards jump?
val sfb_offset = Valid(UInt(log2Ceil(icBlockBytes).W))
// Is this instruction allowed to be inside a sfb?
val shadowable = Bool()
}
class BranchDecode(implicit p: Parameters) extends BoomModule
{
val io = IO(new Bundle {
val inst = Input(UInt(32.W))
val pc = Input(UInt(vaddrBitsExtended.W))
val out = Output(new BranchDecodeSignals)
})
val bpd_csignals =
freechips.rocketchip.rocket.DecodeLogic(io.inst,
List[BitPat](N, N, N, N, X),
//// is br?
//// | is jal?
//// | | is jalr?
//// | | |
//// | | | shadowable
//// | | | | has_rs2
//// | | | | |
Array[(BitPat, List[BitPat])](
JAL -> List(N, Y, N, N, X),
JALR -> List(N, N, Y, N, X),
BEQ -> List(Y, N, N, N, X),
BNE -> List(Y, N, N, N, X),
BGE -> List(Y, N, N, N, X),
BGEU -> List(Y, N, N, N, X),
BLT -> List(Y, N, N, N, X),
BLTU -> List(Y, N, N, N, X),
SLLI -> List(N, N, N, Y, N),
SRLI -> List(N, N, N, Y, N),
SRAI -> List(N, N, N, Y, N),
ADDIW -> List(N, N, N, Y, N),
SLLIW -> List(N, N, N, Y, N),
SRAIW -> List(N, N, N, Y, N),
SRLIW -> List(N, N, N, Y, N),
ADDW -> List(N, N, N, Y, Y),
SUBW -> List(N, N, N, Y, Y),
SLLW -> List(N, N, N, Y, Y),
SRAW -> List(N, N, N, Y, Y),
SRLW -> List(N, N, N, Y, Y),
LUI -> List(N, N, N, Y, N),
ADDI -> List(N, N, N, Y, N),
ANDI -> List(N, N, N, Y, N),
ORI -> List(N, N, N, Y, N),
XORI -> List(N, N, N, Y, N),
SLTI -> List(N, N, N, Y, N),
SLTIU -> List(N, N, N, Y, N),
SLL -> List(N, N, N, Y, Y),
ADD -> List(N, N, N, Y, Y),
SUB -> List(N, N, N, Y, Y),
SLT -> List(N, N, N, Y, Y),
SLTU -> List(N, N, N, Y, Y),
AND -> List(N, N, N, Y, Y),
OR -> List(N, N, N, Y, Y),
XOR -> List(N, N, N, Y, Y),
SRA -> List(N, N, N, Y, Y),
SRL -> List(N, N, N, Y, Y)
))
val cs_is_br = bpd_csignals(0)(0)
val cs_is_jal = bpd_csignals(1)(0)
val cs_is_jalr = bpd_csignals(2)(0)
val cs_is_shadowable = bpd_csignals(3)(0)
val cs_has_rs2 = bpd_csignals(4)(0)
io.out.is_call := (cs_is_jal || cs_is_jalr) && GetRd(io.inst) === RA
io.out.is_ret := cs_is_jalr && GetRs1(io.inst) === BitPat("b00?01") && GetRd(io.inst) === X0
io.out.target := Mux(cs_is_br, ComputeBranchTarget(io.pc, io.inst, xLen),
ComputeJALTarget(io.pc, io.inst, xLen))
io.out.cfi_type :=
Mux(cs_is_jalr,
CFI_JALR,
Mux(cs_is_jal,
CFI_JAL,
Mux(cs_is_br,
CFI_BR,
CFI_X)))
val br_offset = Cat(io.inst(7), io.inst(30,25), io.inst(11,8), 0.U(1.W))
// Is a sfb if it points forwards (offset is positive)
io.out.sfb_offset.valid := cs_is_br && !io.inst(31) && br_offset =/= 0.U && (br_offset >> log2Ceil(icBlockBytes)) === 0.U
io.out.sfb_offset.bits := br_offset
io.out.shadowable := cs_is_shadowable && (
!cs_has_rs2 ||
(GetRs1(io.inst) === GetRd(io.inst)) ||
(io.inst === ADD && GetRs1(io.inst) === X0)
)
}
/**
* Track the current "branch mask", and give out the branch mask to each micro-op in Decode
* (each micro-op in the machine has a branch mask which says which branches it
* is being speculated under).
*
* @param pl_width pipeline width for the processor
*/
class BranchMaskGenerationLogic(val pl_width: Int)(implicit p: Parameters) extends BoomModule
{
val io = IO(new Bundle {
// guess if the uop is a branch (we'll catch this later)
val is_branch = Input(Vec(pl_width, Bool()))
// lock in that it's actually a branch and will fire, so we update
// the branch_masks.
val will_fire = Input(Vec(pl_width, Bool()))
// give out tag immediately (needed in rename)
// mask can come later in the cycle
val br_tag = Output(Vec(pl_width, UInt(brTagSz.W)))
val br_mask = Output(Vec(pl_width, UInt(maxBrCount.W)))
// tell decoders the branch mask has filled up, but on the granularity
// of an individual micro-op (so some micro-ops can go through)
val is_full = Output(Vec(pl_width, Bool()))
val brupdate = Input(new BrUpdateInfo())
val flush_pipeline = Input(Bool())
val debug_branch_mask = Output(UInt(maxBrCount.W))
})
val branch_mask = RegInit(0.U(maxBrCount.W))
//-------------------------------------------------------------
// Give out the branch tag to each branch micro-op
var allocate_mask = branch_mask
val tag_masks = Wire(Vec(pl_width, UInt(maxBrCount.W)))
for (w <- 0 until pl_width) {
// TODO this is a loss of performance as we're blocking branches based on potentially fake branches
io.is_full(w) := (allocate_mask === ~(0.U(maxBrCount.W))) && io.is_branch(w)
// find br_tag and compute next br_mask
val new_br_tag = Wire(UInt(brTagSz.W))
new_br_tag := 0.U
tag_masks(w) := 0.U
for (i <- maxBrCount-1 to 0 by -1) {
when (~allocate_mask(i)) {
new_br_tag := i.U
tag_masks(w) := (1.U << i.U)
}
}
io.br_tag(w) := new_br_tag
allocate_mask = Mux(io.is_branch(w), tag_masks(w) | allocate_mask, allocate_mask)
}
//-------------------------------------------------------------
// Give out the branch mask to each micro-op
// (kill off the bits that corresponded to branches that aren't going to fire)
var curr_mask = branch_mask
for (w <- 0 until pl_width) {
io.br_mask(w) := GetNewBrMask(io.brupdate, curr_mask)
curr_mask = Mux(io.will_fire(w), tag_masks(w) | curr_mask, curr_mask)
}
//-------------------------------------------------------------
// Update the current branch_mask
when (io.flush_pipeline) {
branch_mask := 0.U
} .otherwise {
val mask = Mux(io.brupdate.b2.mispredict,
io.brupdate.b2.uop.br_mask,
~(0.U(maxBrCount.W)))
branch_mask := GetNewBrMask(io.brupdate, curr_mask) & mask
}
io.debug_branch_mask := branch_mask
}
File micro-op.scala:
//******************************************************************************
// Copyright (c) 2015 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// MicroOp
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v3.common
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import boom.v3.exu.FUConstants
/**
* Extension to BoomBundle to add a MicroOp
*/
abstract trait HasBoomUOP extends BoomBundle
{
val uop = new MicroOp()
}
/**
* MicroOp passing through the pipeline
*/
class MicroOp(implicit p: Parameters) extends BoomBundle
with freechips.rocketchip.rocket.constants.MemoryOpConstants
with freechips.rocketchip.rocket.constants.ScalarOpConstants
{
val uopc = UInt(UOPC_SZ.W) // micro-op code
val inst = UInt(32.W)
val debug_inst = UInt(32.W)
val is_rvc = Bool()
val debug_pc = UInt(coreMaxAddrBits.W)
val iq_type = UInt(IQT_SZ.W) // which issue unit do we use?
val fu_code = UInt(FUConstants.FUC_SZ.W) // which functional unit do we use?
val ctrl = new CtrlSignals
// What is the next state of this uop in the issue window? useful
// for the compacting queue.
val iw_state = UInt(2.W)
// Has operand 1 or 2 been waken speculatively by a load?
// Only integer operands are speculaively woken up,
// so we can ignore p3.
val iw_p1_poisoned = Bool()
val iw_p2_poisoned = Bool()
val is_br = Bool() // is this micro-op a (branch) vs a regular PC+4 inst?
val is_jalr = Bool() // is this a jump? (jal or jalr)
val is_jal = Bool() // is this a JAL (doesn't include JR)? used for branch unit
val is_sfb = Bool() // is this a sfb or in the shadow of a sfb
val br_mask = UInt(maxBrCount.W) // which branches are we being speculated under?
val br_tag = UInt(brTagSz.W)
// Index into FTQ to figure out our fetch PC.
val ftq_idx = UInt(log2Ceil(ftqSz).W)
// This inst straddles two fetch packets
val edge_inst = Bool()
// Low-order bits of our own PC. Combine with ftq[ftq_idx] to get PC.
// Aligned to a cache-line size, as that is the greater fetch granularity.
// TODO: Shouldn't this be aligned to fetch-width size?
val pc_lob = UInt(log2Ceil(icBlockBytes).W)
// Was this a branch that was predicted taken?
val taken = Bool()
val imm_packed = UInt(LONGEST_IMM_SZ.W) // densely pack the imm in decode...
// then translate and sign-extend in execute
val csr_addr = UInt(CSR_ADDR_SZ.W) // only used for critical path reasons in Exe
val rob_idx = UInt(robAddrSz.W)
val ldq_idx = UInt(ldqAddrSz.W)
val stq_idx = UInt(stqAddrSz.W)
val rxq_idx = UInt(log2Ceil(numRxqEntries).W)
val pdst = UInt(maxPregSz.W)
val prs1 = UInt(maxPregSz.W)
val prs2 = UInt(maxPregSz.W)
val prs3 = UInt(maxPregSz.W)
val ppred = UInt(log2Ceil(ftqSz).W)
val prs1_busy = Bool()
val prs2_busy = Bool()
val prs3_busy = Bool()
val ppred_busy = Bool()
val stale_pdst = UInt(maxPregSz.W)
val exception = Bool()
val exc_cause = UInt(xLen.W) // TODO compress this down, xlen is insanity
val bypassable = Bool() // can we bypass ALU results? (doesn't include loads, csr, etc...)
val mem_cmd = UInt(M_SZ.W) // sync primitives/cache flushes
val mem_size = UInt(2.W)
val mem_signed = Bool()
val is_fence = Bool()
val is_fencei = Bool()
val is_amo = Bool()
val uses_ldq = Bool()
val uses_stq = Bool()
val is_sys_pc2epc = Bool() // Is a ECall or Breakpoint -- both set EPC to PC.
val is_unique = Bool() // only allow this instruction in the pipeline, wait for STQ to
// drain, clear fetcha fter it (tell ROB to un-ready until empty)
val flush_on_commit = Bool() // some instructions need to flush the pipeline behind them
// Preditation
def is_sfb_br = is_br && is_sfb && enableSFBOpt.B // Does this write a predicate
def is_sfb_shadow = !is_br && is_sfb && enableSFBOpt.B // Is this predicated
val ldst_is_rs1 = Bool() // If this is set and we are predicated off, copy rs1 to dst,
// else copy rs2 to dst
// logical specifiers (only used in Decode->Rename), except rollback (ldst)
val ldst = UInt(lregSz.W)
val lrs1 = UInt(lregSz.W)
val lrs2 = UInt(lregSz.W)
val lrs3 = UInt(lregSz.W)
val ldst_val = Bool() // is there a destination? invalid for stores, rd==x0, etc.
val dst_rtype = UInt(2.W)
val lrs1_rtype = UInt(2.W)
val lrs2_rtype = UInt(2.W)
val frs3_en = Bool()
// floating point information
val fp_val = Bool() // is a floating-point instruction (F- or D-extension)?
// If it's non-ld/st it will write back exception bits to the fcsr.
val fp_single = Bool() // single-precision floating point instruction (F-extension)
// frontend exception information
val xcpt_pf_if = Bool() // I-TLB page fault.
val xcpt_ae_if = Bool() // I$ access exception.
val xcpt_ma_if = Bool() // Misaligned fetch (jal/brjumping to misaligned addr).
val bp_debug_if = Bool() // Breakpoint
val bp_xcpt_if = Bool() // Breakpoint
// What prediction structure provides the prediction FROM this op
val debug_fsrc = UInt(BSRC_SZ.W)
// What prediction structure provides the prediction TO this op
val debug_tsrc = UInt(BSRC_SZ.W)
// Do we allocate a branch tag for this?
// SFB branches don't get a mask, they get a predicate bit
def allocate_brtag = (is_br && !is_sfb) || is_jalr
// Does this register write-back
def rf_wen = dst_rtype =/= RT_X
// Is it possible for this uop to misspeculate, preventing the commit of subsequent uops?
def unsafe = uses_ldq || (uses_stq && !is_fence) || is_br || is_jalr
def fu_code_is(_fu: UInt) = (fu_code & _fu) =/= 0.U
}
/**
* Control signals within a MicroOp
*
* TODO REFACTOR this, as this should no longer be true, as bypass occurs in stage before branch resolution
*/
class CtrlSignals extends Bundle()
{
val br_type = UInt(BR_N.getWidth.W)
val op1_sel = UInt(OP1_X.getWidth.W)
val op2_sel = UInt(OP2_X.getWidth.W)
val imm_sel = UInt(IS_X.getWidth.W)
val op_fcn = UInt(freechips.rocketchip.rocket.ALU.SZ_ALU_FN.W)
val fcn_dw = Bool()
val csr_cmd = UInt(freechips.rocketchip.rocket.CSR.SZ.W)
val is_load = Bool() // will invoke TLB address lookup
val is_sta = Bool() // will invoke TLB address lookup
val is_std = Bool()
}
| module DecodeUnit_3( // @[decode.scala:474:7]
input clock, // @[decode.scala:474:7]
input reset, // @[decode.scala:474:7]
input [31:0] io_enq_uop_inst, // @[decode.scala:477:14]
input [31:0] io_enq_uop_debug_inst, // @[decode.scala:477:14]
input io_enq_uop_is_rvc, // @[decode.scala:477:14]
input [39:0] io_enq_uop_debug_pc, // @[decode.scala:477:14]
input io_enq_uop_is_sfb, // @[decode.scala:477:14]
input [4:0] io_enq_uop_ftq_idx, // @[decode.scala:477:14]
input io_enq_uop_edge_inst, // @[decode.scala:477:14]
input [5:0] io_enq_uop_pc_lob, // @[decode.scala:477:14]
input io_enq_uop_taken, // @[decode.scala:477:14]
input io_enq_uop_xcpt_pf_if, // @[decode.scala:477:14]
input io_enq_uop_xcpt_ae_if, // @[decode.scala:477:14]
input io_enq_uop_bp_debug_if, // @[decode.scala:477:14]
input io_enq_uop_bp_xcpt_if, // @[decode.scala:477:14]
input [1:0] io_enq_uop_debug_fsrc, // @[decode.scala:477:14]
output [6:0] io_deq_uop_uopc, // @[decode.scala:477:14]
output [31:0] io_deq_uop_inst, // @[decode.scala:477:14]
output [31:0] io_deq_uop_debug_inst, // @[decode.scala:477:14]
output io_deq_uop_is_rvc, // @[decode.scala:477:14]
output [39:0] io_deq_uop_debug_pc, // @[decode.scala:477:14]
output [2:0] io_deq_uop_iq_type, // @[decode.scala:477:14]
output [9:0] io_deq_uop_fu_code, // @[decode.scala:477:14]
output io_deq_uop_is_br, // @[decode.scala:477:14]
output io_deq_uop_is_jalr, // @[decode.scala:477:14]
output io_deq_uop_is_jal, // @[decode.scala:477:14]
output io_deq_uop_is_sfb, // @[decode.scala:477:14]
output [4:0] io_deq_uop_ftq_idx, // @[decode.scala:477:14]
output io_deq_uop_edge_inst, // @[decode.scala:477:14]
output [5:0] io_deq_uop_pc_lob, // @[decode.scala:477:14]
output io_deq_uop_taken, // @[decode.scala:477:14]
output [19:0] io_deq_uop_imm_packed, // @[decode.scala:477:14]
output io_deq_uop_exception, // @[decode.scala:477:14]
output [63:0] io_deq_uop_exc_cause, // @[decode.scala:477:14]
output io_deq_uop_bypassable, // @[decode.scala:477:14]
output [4:0] io_deq_uop_mem_cmd, // @[decode.scala:477:14]
output [1:0] io_deq_uop_mem_size, // @[decode.scala:477:14]
output io_deq_uop_mem_signed, // @[decode.scala:477:14]
output io_deq_uop_is_fence, // @[decode.scala:477:14]
output io_deq_uop_is_fencei, // @[decode.scala:477:14]
output io_deq_uop_is_amo, // @[decode.scala:477:14]
output io_deq_uop_uses_ldq, // @[decode.scala:477:14]
output io_deq_uop_uses_stq, // @[decode.scala:477:14]
output io_deq_uop_is_sys_pc2epc, // @[decode.scala:477:14]
output io_deq_uop_is_unique, // @[decode.scala:477:14]
output io_deq_uop_flush_on_commit, // @[decode.scala:477:14]
output [5:0] io_deq_uop_ldst, // @[decode.scala:477:14]
output [5:0] io_deq_uop_lrs1, // @[decode.scala:477:14]
output [5:0] io_deq_uop_lrs2, // @[decode.scala:477:14]
output [5:0] io_deq_uop_lrs3, // @[decode.scala:477:14]
output io_deq_uop_ldst_val, // @[decode.scala:477:14]
output [1:0] io_deq_uop_dst_rtype, // @[decode.scala:477:14]
output [1:0] io_deq_uop_lrs1_rtype, // @[decode.scala:477:14]
output [1:0] io_deq_uop_lrs2_rtype, // @[decode.scala:477:14]
output io_deq_uop_frs3_en, // @[decode.scala:477:14]
output io_deq_uop_fp_val, // @[decode.scala:477:14]
output io_deq_uop_fp_single, // @[decode.scala:477:14]
output io_deq_uop_xcpt_pf_if, // @[decode.scala:477:14]
output io_deq_uop_xcpt_ae_if, // @[decode.scala:477:14]
output io_deq_uop_bp_debug_if, // @[decode.scala:477:14]
output io_deq_uop_bp_xcpt_if, // @[decode.scala:477:14]
output [1:0] io_deq_uop_debug_fsrc, // @[decode.scala:477:14]
input io_status_debug, // @[decode.scala:477:14]
input io_status_cease, // @[decode.scala:477:14]
input io_status_wfi, // @[decode.scala:477:14]
input [1:0] io_status_dprv, // @[decode.scala:477:14]
input io_status_dv, // @[decode.scala:477:14]
input [1:0] io_status_prv, // @[decode.scala:477:14]
input io_status_v, // @[decode.scala:477:14]
input io_status_sd, // @[decode.scala:477:14]
input io_status_mpv, // @[decode.scala:477:14]
input io_status_gva, // @[decode.scala:477:14]
input io_status_tsr, // @[decode.scala:477:14]
input io_status_tw, // @[decode.scala:477:14]
input io_status_tvm, // @[decode.scala:477:14]
input io_status_mxr, // @[decode.scala:477:14]
input io_status_sum, // @[decode.scala:477:14]
input io_status_mprv, // @[decode.scala:477:14]
input [1:0] io_status_fs, // @[decode.scala:477:14]
input [1:0] io_status_mpp, // @[decode.scala:477:14]
input io_status_spp, // @[decode.scala:477:14]
input io_status_mpie, // @[decode.scala:477:14]
input io_status_spie, // @[decode.scala:477:14]
input io_status_mie, // @[decode.scala:477:14]
input io_status_sie, // @[decode.scala:477:14]
output [31:0] io_csr_decode_inst, // @[decode.scala:477:14]
input io_csr_decode_fp_illegal, // @[decode.scala:477:14]
input io_csr_decode_fp_csr, // @[decode.scala:477:14]
input io_csr_decode_read_illegal, // @[decode.scala:477:14]
input io_csr_decode_write_illegal, // @[decode.scala:477:14]
input io_csr_decode_write_flush, // @[decode.scala:477:14]
input io_csr_decode_system_illegal, // @[decode.scala:477:14]
input io_csr_decode_virtual_access_illegal, // @[decode.scala:477:14]
input io_csr_decode_virtual_system_illegal, // @[decode.scala:477:14]
input io_interrupt, // @[decode.scala:477:14]
input [63:0] io_interrupt_cause // @[decode.scala:477:14]
);
wire [31:0] io_enq_uop_inst_0 = io_enq_uop_inst; // @[decode.scala:474:7]
wire [31:0] io_enq_uop_debug_inst_0 = io_enq_uop_debug_inst; // @[decode.scala:474:7]
wire io_enq_uop_is_rvc_0 = io_enq_uop_is_rvc; // @[decode.scala:474:7]
wire [39:0] io_enq_uop_debug_pc_0 = io_enq_uop_debug_pc; // @[decode.scala:474:7]
wire io_enq_uop_is_sfb_0 = io_enq_uop_is_sfb; // @[decode.scala:474:7]
wire [4:0] io_enq_uop_ftq_idx_0 = io_enq_uop_ftq_idx; // @[decode.scala:474:7]
wire io_enq_uop_edge_inst_0 = io_enq_uop_edge_inst; // @[decode.scala:474:7]
wire [5:0] io_enq_uop_pc_lob_0 = io_enq_uop_pc_lob; // @[decode.scala:474:7]
wire io_enq_uop_taken_0 = io_enq_uop_taken; // @[decode.scala:474:7]
wire io_enq_uop_xcpt_pf_if_0 = io_enq_uop_xcpt_pf_if; // @[decode.scala:474:7]
wire io_enq_uop_xcpt_ae_if_0 = io_enq_uop_xcpt_ae_if; // @[decode.scala:474:7]
wire io_enq_uop_bp_debug_if_0 = io_enq_uop_bp_debug_if; // @[decode.scala:474:7]
wire io_enq_uop_bp_xcpt_if_0 = io_enq_uop_bp_xcpt_if; // @[decode.scala:474:7]
wire [1:0] io_enq_uop_debug_fsrc_0 = io_enq_uop_debug_fsrc; // @[decode.scala:474:7]
wire io_status_debug_0 = io_status_debug; // @[decode.scala:474:7]
wire io_status_cease_0 = io_status_cease; // @[decode.scala:474:7]
wire io_status_wfi_0 = io_status_wfi; // @[decode.scala:474:7]
wire [1:0] io_status_dprv_0 = io_status_dprv; // @[decode.scala:474:7]
wire io_status_dv_0 = io_status_dv; // @[decode.scala:474:7]
wire [1:0] io_status_prv_0 = io_status_prv; // @[decode.scala:474:7]
wire io_status_v_0 = io_status_v; // @[decode.scala:474:7]
wire io_status_sd_0 = io_status_sd; // @[decode.scala:474:7]
wire io_status_mpv_0 = io_status_mpv; // @[decode.scala:474:7]
wire io_status_gva_0 = io_status_gva; // @[decode.scala:474:7]
wire io_status_tsr_0 = io_status_tsr; // @[decode.scala:474:7]
wire io_status_tw_0 = io_status_tw; // @[decode.scala:474:7]
wire io_status_tvm_0 = io_status_tvm; // @[decode.scala:474:7]
wire io_status_mxr_0 = io_status_mxr; // @[decode.scala:474:7]
wire io_status_sum_0 = io_status_sum; // @[decode.scala:474:7]
wire io_status_mprv_0 = io_status_mprv; // @[decode.scala:474:7]
wire [1:0] io_status_fs_0 = io_status_fs; // @[decode.scala:474:7]
wire [1:0] io_status_mpp_0 = io_status_mpp; // @[decode.scala:474:7]
wire io_status_spp_0 = io_status_spp; // @[decode.scala:474:7]
wire io_status_mpie_0 = io_status_mpie; // @[decode.scala:474:7]
wire io_status_spie_0 = io_status_spie; // @[decode.scala:474:7]
wire io_status_mie_0 = io_status_mie; // @[decode.scala:474:7]
wire io_status_sie_0 = io_status_sie; // @[decode.scala:474:7]
wire io_csr_decode_fp_illegal_0 = io_csr_decode_fp_illegal; // @[decode.scala:474:7]
wire io_csr_decode_fp_csr_0 = io_csr_decode_fp_csr; // @[decode.scala:474:7]
wire io_csr_decode_read_illegal_0 = io_csr_decode_read_illegal; // @[decode.scala:474:7]
wire io_csr_decode_write_illegal_0 = io_csr_decode_write_illegal; // @[decode.scala:474:7]
wire io_csr_decode_write_flush_0 = io_csr_decode_write_flush; // @[decode.scala:474:7]
wire io_csr_decode_system_illegal_0 = io_csr_decode_system_illegal; // @[decode.scala:474:7]
wire io_csr_decode_virtual_access_illegal_0 = io_csr_decode_virtual_access_illegal; // @[decode.scala:474:7]
wire io_csr_decode_virtual_system_illegal_0 = io_csr_decode_virtual_system_illegal; // @[decode.scala:474:7]
wire io_interrupt_0 = io_interrupt; // @[decode.scala:474:7]
wire [63:0] io_interrupt_cause_0 = io_interrupt_cause; // @[decode.scala:474:7]
wire [1:0] io_status_sxl = 2'h2; // @[decode.scala:474:7]
wire [1:0] io_status_uxl = 2'h2; // @[decode.scala:474:7]
wire io_csr_decode_vector_illegal = 1'h1; // @[decode.scala:474:7, :477:14, :505:32, :506:51]
wire io_csr_decode_rocc_illegal = 1'h1; // @[decode.scala:474:7, :477:14, :505:32, :506:51]
wire _id_illegal_insn_T_5 = 1'h1; // @[decode.scala:474:7, :477:14, :505:32, :506:51]
wire _id_illegal_insn_T_11 = 1'h1; // @[decode.scala:474:7, :477:14, :505:32, :506:51]
wire [7:0] io_status_zero1 = 8'h0; // @[decode.scala:474:7, :477:14]
wire [22:0] io_status_zero2 = 23'h0; // @[decode.scala:474:7, :477:14]
wire [31:0] io_status_isa = 32'h14112D; // @[decode.scala:474:7, :477:14]
wire [5:0] io_enq_uop_ldst = 6'h0; // @[decode.scala:474:7, :477:14]
wire [5:0] io_enq_uop_lrs1 = 6'h0; // @[decode.scala:474:7, :477:14]
wire [5:0] io_enq_uop_lrs2 = 6'h0; // @[decode.scala:474:7, :477:14]
wire [5:0] io_enq_uop_lrs3 = 6'h0; // @[decode.scala:474:7, :477:14]
wire [63:0] io_enq_uop_exc_cause = 64'h0; // @[decode.scala:474:7, :477:14]
wire [11:0] io_enq_uop_csr_addr = 12'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [11:0] io_deq_uop_csr_addr = 12'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [11:0] uop_csr_addr = 12'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [19:0] io_enq_uop_imm_packed = 20'h0; // @[decode.scala:474:7, :477:14]
wire [15:0] io_enq_uop_br_mask = 16'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [15:0] io_deq_uop_br_mask = 16'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [15:0] uop_br_mask = 16'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire io_enq_uop_ctrl_fcn_dw = 1'h0; // @[decode.scala:474:7]
wire io_enq_uop_ctrl_is_load = 1'h0; // @[decode.scala:474:7]
wire io_enq_uop_ctrl_is_sta = 1'h0; // @[decode.scala:474:7]
wire io_enq_uop_ctrl_is_std = 1'h0; // @[decode.scala:474:7]
wire io_enq_uop_iw_p1_poisoned = 1'h0; // @[decode.scala:474:7]
wire io_enq_uop_iw_p2_poisoned = 1'h0; // @[decode.scala:474:7]
wire io_enq_uop_is_br = 1'h0; // @[decode.scala:474:7]
wire io_enq_uop_is_jalr = 1'h0; // @[decode.scala:474:7]
wire io_enq_uop_is_jal = 1'h0; // @[decode.scala:474:7]
wire io_enq_uop_prs1_busy = 1'h0; // @[decode.scala:474:7]
wire io_enq_uop_prs2_busy = 1'h0; // @[decode.scala:474:7]
wire io_enq_uop_prs3_busy = 1'h0; // @[decode.scala:474:7]
wire io_enq_uop_ppred_busy = 1'h0; // @[decode.scala:474:7]
wire io_enq_uop_exception = 1'h0; // @[decode.scala:474:7]
wire io_enq_uop_bypassable = 1'h0; // @[decode.scala:474:7]
wire io_enq_uop_mem_signed = 1'h0; // @[decode.scala:474:7]
wire io_enq_uop_is_fence = 1'h0; // @[decode.scala:474:7]
wire io_enq_uop_is_fencei = 1'h0; // @[decode.scala:474:7]
wire io_enq_uop_is_amo = 1'h0; // @[decode.scala:474:7]
wire io_enq_uop_uses_ldq = 1'h0; // @[decode.scala:474:7]
wire io_enq_uop_uses_stq = 1'h0; // @[decode.scala:474:7]
wire io_enq_uop_is_sys_pc2epc = 1'h0; // @[decode.scala:474:7]
wire io_enq_uop_is_unique = 1'h0; // @[decode.scala:474:7]
wire io_enq_uop_flush_on_commit = 1'h0; // @[decode.scala:474:7]
wire io_enq_uop_ldst_is_rs1 = 1'h0; // @[decode.scala:474:7]
wire io_enq_uop_ldst_val = 1'h0; // @[decode.scala:474:7]
wire io_enq_uop_frs3_en = 1'h0; // @[decode.scala:474:7]
wire io_enq_uop_fp_val = 1'h0; // @[decode.scala:474:7]
wire io_enq_uop_fp_single = 1'h0; // @[decode.scala:474:7]
wire io_enq_uop_xcpt_ma_if = 1'h0; // @[decode.scala:474:7]
wire io_deq_uop_ctrl_fcn_dw = 1'h0; // @[decode.scala:474:7]
wire io_deq_uop_ctrl_is_load = 1'h0; // @[decode.scala:474:7]
wire io_deq_uop_ctrl_is_sta = 1'h0; // @[decode.scala:474:7]
wire io_deq_uop_ctrl_is_std = 1'h0; // @[decode.scala:474:7]
wire io_deq_uop_iw_p1_poisoned = 1'h0; // @[decode.scala:474:7]
wire io_deq_uop_iw_p2_poisoned = 1'h0; // @[decode.scala:474:7]
wire io_deq_uop_prs1_busy = 1'h0; // @[decode.scala:474:7]
wire io_deq_uop_prs2_busy = 1'h0; // @[decode.scala:474:7]
wire io_deq_uop_prs3_busy = 1'h0; // @[decode.scala:474:7]
wire io_deq_uop_ppred_busy = 1'h0; // @[decode.scala:474:7]
wire io_deq_uop_ldst_is_rs1 = 1'h0; // @[decode.scala:474:7]
wire io_deq_uop_xcpt_ma_if = 1'h0; // @[decode.scala:474:7]
wire io_status_mbe = 1'h0; // @[decode.scala:474:7]
wire io_status_sbe = 1'h0; // @[decode.scala:474:7]
wire io_status_sd_rv32 = 1'h0; // @[decode.scala:474:7]
wire io_status_ube = 1'h0; // @[decode.scala:474:7]
wire io_status_upie = 1'h0; // @[decode.scala:474:7]
wire io_status_hie = 1'h0; // @[decode.scala:474:7]
wire io_status_uie = 1'h0; // @[decode.scala:474:7]
wire io_csr_decode_vector_csr = 1'h0; // @[decode.scala:474:7]
wire uop_ctrl_fcn_dw = 1'h0; // @[decode.scala:479:17]
wire uop_ctrl_is_load = 1'h0; // @[decode.scala:479:17]
wire uop_ctrl_is_sta = 1'h0; // @[decode.scala:479:17]
wire uop_ctrl_is_std = 1'h0; // @[decode.scala:479:17]
wire uop_iw_p1_poisoned = 1'h0; // @[decode.scala:479:17]
wire uop_iw_p2_poisoned = 1'h0; // @[decode.scala:479:17]
wire uop_prs1_busy = 1'h0; // @[decode.scala:479:17]
wire uop_prs2_busy = 1'h0; // @[decode.scala:479:17]
wire uop_prs3_busy = 1'h0; // @[decode.scala:479:17]
wire uop_ppred_busy = 1'h0; // @[decode.scala:479:17]
wire uop_ldst_is_rs1 = 1'h0; // @[decode.scala:479:17]
wire uop_xcpt_ma_if = 1'h0; // @[decode.scala:479:17]
wire cs_rocc = 1'h0; // @[decode.scala:490:16]
wire _id_illegal_insn_T_3 = 1'h0; // @[decode.scala:504:13]
wire _id_illegal_insn_T_6 = 1'h0; // @[decode.scala:505:18]
wire _id_illegal_insn_T_7 = 1'h0; // @[decode.scala:505:15]
wire _id_illegal_insn_T_12 = 1'h0; // @[decode.scala:506:37]
wire _id_illegal_insn_T_13 = 1'h0; // @[decode.scala:506:34]
wire _uop_ldst_is_rs1_T_2 = 1'h0; // @[micro-op.scala:110:43]
wire [4:0] io_enq_uop_ctrl_op_fcn = 5'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [4:0] io_enq_uop_ldq_idx = 5'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [4:0] io_enq_uop_stq_idx = 5'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [4:0] io_enq_uop_ppred = 5'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [4:0] io_enq_uop_mem_cmd = 5'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [4:0] io_deq_uop_ctrl_op_fcn = 5'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [4:0] io_deq_uop_ldq_idx = 5'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [4:0] io_deq_uop_stq_idx = 5'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [4:0] io_deq_uop_ppred = 5'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [4:0] uop_ctrl_op_fcn = 5'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [4:0] uop_ldq_idx = 5'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [4:0] uop_stq_idx = 5'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [4:0] uop_ppred = 5'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [1:0] io_enq_uop_ctrl_op1_sel = 2'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [1:0] io_enq_uop_iw_state = 2'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [1:0] io_enq_uop_rxq_idx = 2'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [1:0] io_enq_uop_mem_size = 2'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [1:0] io_enq_uop_dst_rtype = 2'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [1:0] io_enq_uop_lrs1_rtype = 2'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [1:0] io_enq_uop_lrs2_rtype = 2'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [1:0] io_enq_uop_debug_tsrc = 2'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [1:0] io_deq_uop_ctrl_op1_sel = 2'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [1:0] io_deq_uop_iw_state = 2'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [1:0] io_deq_uop_rxq_idx = 2'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [1:0] io_deq_uop_debug_tsrc = 2'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [1:0] io_status_xs = 2'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [1:0] io_status_vs = 2'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [1:0] uop_ctrl_op1_sel = 2'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [1:0] uop_iw_state = 2'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [1:0] uop_rxq_idx = 2'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [1:0] uop_debug_tsrc = 2'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [3:0] io_enq_uop_ctrl_br_type = 4'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [3:0] io_enq_uop_br_tag = 4'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [3:0] io_deq_uop_ctrl_br_type = 4'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [3:0] io_deq_uop_br_tag = 4'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [3:0] uop_ctrl_br_type = 4'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [3:0] uop_br_tag = 4'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [9:0] io_enq_uop_fu_code = 10'h0; // @[decode.scala:474:7, :477:14]
wire [2:0] io_enq_uop_iq_type = 3'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [2:0] io_enq_uop_ctrl_op2_sel = 3'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [2:0] io_enq_uop_ctrl_imm_sel = 3'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [2:0] io_enq_uop_ctrl_csr_cmd = 3'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [2:0] io_deq_uop_ctrl_op2_sel = 3'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [2:0] io_deq_uop_ctrl_imm_sel = 3'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [2:0] io_deq_uop_ctrl_csr_cmd = 3'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [2:0] uop_ctrl_op2_sel = 3'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [2:0] uop_ctrl_imm_sel = 3'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [2:0] uop_ctrl_csr_cmd = 3'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [6:0] io_enq_uop_uopc = 7'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [6:0] io_enq_uop_rob_idx = 7'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [6:0] io_enq_uop_pdst = 7'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [6:0] io_enq_uop_prs1 = 7'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [6:0] io_enq_uop_prs2 = 7'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [6:0] io_enq_uop_prs3 = 7'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [6:0] io_enq_uop_stale_pdst = 7'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [6:0] io_deq_uop_rob_idx = 7'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [6:0] io_deq_uop_pdst = 7'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [6:0] io_deq_uop_prs1 = 7'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [6:0] io_deq_uop_prs2 = 7'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [6:0] io_deq_uop_prs3 = 7'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [6:0] io_deq_uop_stale_pdst = 7'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [6:0] uop_rob_idx = 7'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [6:0] uop_pdst = 7'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [6:0] uop_prs1 = 7'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [6:0] uop_prs2 = 7'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [6:0] uop_prs3 = 7'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [6:0] uop_stale_pdst = 7'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [31:0] uop_inst = io_enq_uop_inst_0; // @[decode.scala:474:7, :479:17]
wire [31:0] uop_debug_inst = io_enq_uop_debug_inst_0; // @[decode.scala:474:7, :479:17]
wire uop_is_rvc = io_enq_uop_is_rvc_0; // @[decode.scala:474:7, :479:17]
wire [39:0] uop_debug_pc = io_enq_uop_debug_pc_0; // @[decode.scala:474:7, :479:17]
wire uop_is_sfb = io_enq_uop_is_sfb_0; // @[decode.scala:474:7, :479:17]
wire [4:0] uop_ftq_idx = io_enq_uop_ftq_idx_0; // @[decode.scala:474:7, :479:17]
wire uop_edge_inst = io_enq_uop_edge_inst_0; // @[decode.scala:474:7, :479:17]
wire [5:0] uop_pc_lob = io_enq_uop_pc_lob_0; // @[decode.scala:474:7, :479:17]
wire uop_taken = io_enq_uop_taken_0; // @[decode.scala:474:7, :479:17]
wire uop_xcpt_pf_if = io_enq_uop_xcpt_pf_if_0; // @[decode.scala:474:7, :479:17]
wire uop_xcpt_ae_if = io_enq_uop_xcpt_ae_if_0; // @[decode.scala:474:7, :479:17]
wire uop_bp_debug_if = io_enq_uop_bp_debug_if_0; // @[decode.scala:474:7, :479:17]
wire uop_bp_xcpt_if = io_enq_uop_bp_xcpt_if_0; // @[decode.scala:474:7, :479:17]
wire [1:0] uop_debug_fsrc = io_enq_uop_debug_fsrc_0; // @[decode.scala:474:7, :479:17]
wire [6:0] uop_uopc; // @[decode.scala:479:17]
wire [2:0] uop_iq_type; // @[decode.scala:479:17]
wire [9:0] uop_fu_code; // @[decode.scala:479:17]
wire uop_is_br; // @[decode.scala:479:17]
wire uop_is_jalr; // @[decode.scala:479:17]
wire uop_is_jal; // @[decode.scala:479:17]
wire [19:0] uop_imm_packed; // @[decode.scala:479:17]
wire uop_exception; // @[decode.scala:479:17]
wire [63:0] uop_exc_cause; // @[decode.scala:479:17]
wire uop_bypassable; // @[decode.scala:479:17]
wire [4:0] uop_mem_cmd; // @[decode.scala:479:17]
wire [1:0] uop_mem_size; // @[decode.scala:479:17]
wire uop_mem_signed; // @[decode.scala:479:17]
wire uop_is_fence; // @[decode.scala:479:17]
wire uop_is_fencei; // @[decode.scala:479:17]
wire uop_is_amo; // @[decode.scala:479:17]
wire uop_uses_ldq; // @[decode.scala:479:17]
wire uop_uses_stq; // @[decode.scala:479:17]
wire uop_is_sys_pc2epc; // @[decode.scala:479:17]
wire uop_is_unique; // @[decode.scala:479:17]
wire uop_flush_on_commit; // @[decode.scala:479:17]
wire [5:0] uop_ldst; // @[decode.scala:479:17]
wire [5:0] uop_lrs1; // @[decode.scala:479:17]
wire [5:0] uop_lrs2; // @[decode.scala:479:17]
wire [5:0] uop_lrs3; // @[decode.scala:479:17]
wire uop_ldst_val; // @[decode.scala:479:17]
wire [1:0] uop_dst_rtype; // @[decode.scala:479:17]
wire [1:0] uop_lrs1_rtype; // @[decode.scala:479:17]
wire [1:0] uop_lrs2_rtype; // @[decode.scala:479:17]
wire uop_frs3_en; // @[decode.scala:479:17]
wire uop_fp_val; // @[decode.scala:479:17]
wire uop_fp_single; // @[decode.scala:479:17]
wire [6:0] io_deq_uop_uopc_0; // @[decode.scala:474:7]
wire [31:0] io_deq_uop_inst_0; // @[decode.scala:474:7]
wire [31:0] io_deq_uop_debug_inst_0; // @[decode.scala:474:7]
wire io_deq_uop_is_rvc_0; // @[decode.scala:474:7]
wire [39:0] io_deq_uop_debug_pc_0; // @[decode.scala:474:7]
wire [2:0] io_deq_uop_iq_type_0; // @[decode.scala:474:7]
wire [9:0] io_deq_uop_fu_code_0; // @[decode.scala:474:7]
wire io_deq_uop_is_br_0; // @[decode.scala:474:7]
wire io_deq_uop_is_jalr_0; // @[decode.scala:474:7]
wire io_deq_uop_is_jal_0; // @[decode.scala:474:7]
wire io_deq_uop_is_sfb_0; // @[decode.scala:474:7]
wire [4:0] io_deq_uop_ftq_idx_0; // @[decode.scala:474:7]
wire io_deq_uop_edge_inst_0; // @[decode.scala:474:7]
wire [5:0] io_deq_uop_pc_lob_0; // @[decode.scala:474:7]
wire io_deq_uop_taken_0; // @[decode.scala:474:7]
wire [19:0] io_deq_uop_imm_packed_0; // @[decode.scala:474:7]
wire io_deq_uop_exception_0; // @[decode.scala:474:7]
wire [63:0] io_deq_uop_exc_cause_0; // @[decode.scala:474:7]
wire io_deq_uop_bypassable_0; // @[decode.scala:474:7]
wire [4:0] io_deq_uop_mem_cmd_0; // @[decode.scala:474:7]
wire [1:0] io_deq_uop_mem_size_0; // @[decode.scala:474:7]
wire io_deq_uop_mem_signed_0; // @[decode.scala:474:7]
wire io_deq_uop_is_fence_0; // @[decode.scala:474:7]
wire io_deq_uop_is_fencei_0; // @[decode.scala:474:7]
wire io_deq_uop_is_amo_0; // @[decode.scala:474:7]
wire io_deq_uop_uses_ldq_0; // @[decode.scala:474:7]
wire io_deq_uop_uses_stq_0; // @[decode.scala:474:7]
wire io_deq_uop_is_sys_pc2epc_0; // @[decode.scala:474:7]
wire io_deq_uop_is_unique_0; // @[decode.scala:474:7]
wire io_deq_uop_flush_on_commit_0; // @[decode.scala:474:7]
wire [5:0] io_deq_uop_ldst_0; // @[decode.scala:474:7]
wire [5:0] io_deq_uop_lrs1_0; // @[decode.scala:474:7]
wire [5:0] io_deq_uop_lrs2_0; // @[decode.scala:474:7]
wire [5:0] io_deq_uop_lrs3_0; // @[decode.scala:474:7]
wire io_deq_uop_ldst_val_0; // @[decode.scala:474:7]
wire [1:0] io_deq_uop_dst_rtype_0; // @[decode.scala:474:7]
wire [1:0] io_deq_uop_lrs1_rtype_0; // @[decode.scala:474:7]
wire [1:0] io_deq_uop_lrs2_rtype_0; // @[decode.scala:474:7]
wire io_deq_uop_frs3_en_0; // @[decode.scala:474:7]
wire io_deq_uop_fp_val_0; // @[decode.scala:474:7]
wire io_deq_uop_fp_single_0; // @[decode.scala:474:7]
wire io_deq_uop_xcpt_pf_if_0; // @[decode.scala:474:7]
wire io_deq_uop_xcpt_ae_if_0; // @[decode.scala:474:7]
wire io_deq_uop_bp_debug_if_0; // @[decode.scala:474:7]
wire io_deq_uop_bp_xcpt_if_0; // @[decode.scala:474:7]
wire [1:0] io_deq_uop_debug_fsrc_0; // @[decode.scala:474:7]
wire [31:0] io_csr_decode_inst_0; // @[decode.scala:474:7]
wire [6:0] cs_uopc; // @[decode.scala:490:16]
assign io_deq_uop_uopc_0 = uop_uopc; // @[decode.scala:474:7, :479:17]
assign io_deq_uop_inst_0 = uop_inst; // @[decode.scala:474:7, :479:17]
assign io_csr_decode_inst_0 = uop_inst; // @[decode.scala:474:7, :479:17]
wire [31:0] cs_decoder_decoded_plaInput = uop_inst; // @[pla.scala:77:22]
assign io_deq_uop_debug_inst_0 = uop_debug_inst; // @[decode.scala:474:7, :479:17]
assign io_deq_uop_is_rvc_0 = uop_is_rvc; // @[decode.scala:474:7, :479:17]
assign io_deq_uop_debug_pc_0 = uop_debug_pc; // @[decode.scala:474:7, :479:17]
wire [2:0] cs_iq_type; // @[decode.scala:490:16]
assign io_deq_uop_iq_type_0 = uop_iq_type; // @[decode.scala:474:7, :479:17]
wire [9:0] cs_fu_code; // @[decode.scala:490:16]
assign io_deq_uop_fu_code_0 = uop_fu_code; // @[decode.scala:474:7, :479:17]
wire cs_is_br; // @[decode.scala:490:16]
assign io_deq_uop_is_br_0 = uop_is_br; // @[decode.scala:474:7, :479:17]
wire _uop_is_jalr_T; // @[decode.scala:590:35]
assign io_deq_uop_is_jalr_0 = uop_is_jalr; // @[decode.scala:474:7, :479:17]
wire _uop_is_jal_T; // @[decode.scala:589:35]
assign io_deq_uop_is_jal_0 = uop_is_jal; // @[decode.scala:474:7, :479:17]
assign io_deq_uop_is_sfb_0 = uop_is_sfb; // @[decode.scala:474:7, :479:17]
assign io_deq_uop_ftq_idx_0 = uop_ftq_idx; // @[decode.scala:474:7, :479:17]
assign io_deq_uop_edge_inst_0 = uop_edge_inst; // @[decode.scala:474:7, :479:17]
assign io_deq_uop_pc_lob_0 = uop_pc_lob; // @[decode.scala:474:7, :479:17]
assign io_deq_uop_taken_0 = uop_taken; // @[decode.scala:474:7, :479:17]
wire [19:0] _uop_imm_packed_T_2; // @[decode.scala:584:24]
assign io_deq_uop_imm_packed_0 = uop_imm_packed; // @[decode.scala:474:7, :479:17]
wire xcpt_valid; // @[decode.scala:513:26]
assign io_deq_uop_exception_0 = uop_exception; // @[decode.scala:474:7, :479:17]
wire [63:0] xcpt_cause; // @[Mux.scala:50:70]
assign io_deq_uop_exc_cause_0 = uop_exc_cause; // @[decode.scala:474:7, :479:17]
wire cs_bypassable; // @[decode.scala:490:16]
assign io_deq_uop_bypassable_0 = uop_bypassable; // @[decode.scala:474:7, :479:17]
wire [4:0] cs_mem_cmd; // @[decode.scala:490:16]
assign io_deq_uop_mem_cmd_0 = uop_mem_cmd; // @[decode.scala:474:7, :479:17]
wire [1:0] _uop_mem_size_T_7; // @[decode.scala:566:24]
assign io_deq_uop_mem_size_0 = uop_mem_size; // @[decode.scala:474:7, :479:17]
wire _uop_mem_signed_T_1; // @[decode.scala:567:21]
assign io_deq_uop_mem_signed_0 = uop_mem_signed; // @[decode.scala:474:7, :479:17]
wire cs_is_fence; // @[decode.scala:490:16]
assign io_deq_uop_is_fence_0 = uop_is_fence; // @[decode.scala:474:7, :479:17]
wire cs_is_fencei; // @[decode.scala:490:16]
assign io_deq_uop_is_fencei_0 = uop_is_fencei; // @[decode.scala:474:7, :479:17]
wire cs_is_amo; // @[decode.scala:490:16]
assign io_deq_uop_is_amo_0 = uop_is_amo; // @[decode.scala:474:7, :479:17]
wire cs_uses_ldq; // @[decode.scala:490:16]
assign io_deq_uop_uses_ldq_0 = uop_uses_ldq; // @[decode.scala:474:7, :479:17]
wire cs_uses_stq; // @[decode.scala:490:16]
assign io_deq_uop_uses_stq_0 = uop_uses_stq; // @[decode.scala:474:7, :479:17]
wire cs_is_sys_pc2epc; // @[decode.scala:490:16]
assign io_deq_uop_is_sys_pc2epc_0 = uop_is_sys_pc2epc; // @[decode.scala:474:7, :479:17]
wire cs_inst_unique; // @[decode.scala:490:16]
assign io_deq_uop_is_unique_0 = uop_is_unique; // @[decode.scala:474:7, :479:17]
wire _uop_flush_on_commit_T_3; // @[decode.scala:575:45]
assign io_deq_uop_flush_on_commit_0 = uop_flush_on_commit; // @[decode.scala:474:7, :479:17]
assign io_deq_uop_ldst_0 = uop_ldst; // @[decode.scala:474:7, :479:17]
assign io_deq_uop_lrs1_0 = uop_lrs1; // @[decode.scala:474:7, :479:17]
assign io_deq_uop_lrs2_0 = uop_lrs2; // @[decode.scala:474:7, :479:17]
assign io_deq_uop_lrs3_0 = uop_lrs3; // @[decode.scala:474:7, :479:17]
wire _uop_ldst_val_T_5; // @[decode.scala:540:42]
assign io_deq_uop_ldst_val_0 = uop_ldst_val; // @[decode.scala:474:7, :479:17]
wire [1:0] cs_dst_type; // @[decode.scala:490:16]
assign io_deq_uop_dst_rtype_0 = uop_dst_rtype; // @[decode.scala:474:7, :479:17]
wire [1:0] cs_rs1_type; // @[decode.scala:490:16]
assign io_deq_uop_lrs1_rtype_0 = uop_lrs1_rtype; // @[decode.scala:474:7, :479:17]
wire [1:0] cs_rs2_type; // @[decode.scala:490:16]
assign io_deq_uop_lrs2_rtype_0 = uop_lrs2_rtype; // @[decode.scala:474:7, :479:17]
wire cs_frs3_en; // @[decode.scala:490:16]
assign io_deq_uop_frs3_en_0 = uop_frs3_en; // @[decode.scala:474:7, :479:17]
wire cs_fp_val; // @[decode.scala:490:16]
assign io_deq_uop_fp_val_0 = uop_fp_val; // @[decode.scala:474:7, :479:17]
wire cs_fp_single; // @[decode.scala:490:16]
assign io_deq_uop_fp_single_0 = uop_fp_single; // @[decode.scala:474:7, :479:17]
assign io_deq_uop_xcpt_pf_if_0 = uop_xcpt_pf_if; // @[decode.scala:474:7, :479:17]
assign io_deq_uop_xcpt_ae_if_0 = uop_xcpt_ae_if; // @[decode.scala:474:7, :479:17]
assign io_deq_uop_bp_debug_if_0 = uop_bp_debug_if; // @[decode.scala:474:7, :479:17]
assign io_deq_uop_bp_xcpt_if_0 = uop_bp_xcpt_if; // @[decode.scala:474:7, :479:17]
assign io_deq_uop_debug_fsrc_0 = uop_debug_fsrc; // @[decode.scala:474:7, :479:17]
wire cs_decoder_0; // @[Decode.scala:50:77]
wire cs_decoder_1; // @[Decode.scala:50:77]
assign uop_fp_val = cs_fp_val; // @[decode.scala:479:17, :490:16]
wire cs_decoder_2; // @[Decode.scala:50:77]
assign uop_fp_single = cs_fp_single; // @[decode.scala:479:17, :490:16]
wire [6:0] cs_decoder_3; // @[Decode.scala:50:77]
assign uop_uopc = cs_uopc; // @[decode.scala:479:17, :490:16]
wire [2:0] cs_decoder_4; // @[Decode.scala:50:77]
assign uop_iq_type = cs_iq_type; // @[decode.scala:479:17, :490:16]
wire [9:0] cs_decoder_5; // @[Decode.scala:50:77]
assign uop_fu_code = cs_fu_code; // @[decode.scala:479:17, :490:16]
wire [1:0] cs_decoder_6; // @[Decode.scala:50:77]
assign uop_dst_rtype = cs_dst_type; // @[decode.scala:479:17, :490:16]
wire [1:0] cs_decoder_7; // @[Decode.scala:50:77]
assign uop_lrs1_rtype = cs_rs1_type; // @[decode.scala:479:17, :490:16]
wire [1:0] cs_decoder_8; // @[Decode.scala:50:77]
assign uop_lrs2_rtype = cs_rs2_type; // @[decode.scala:479:17, :490:16]
wire cs_decoder_9; // @[Decode.scala:50:77]
assign uop_frs3_en = cs_frs3_en; // @[decode.scala:479:17, :490:16]
wire [2:0] cs_decoder_10; // @[Decode.scala:50:77]
wire cs_decoder_11; // @[Decode.scala:50:77]
assign uop_uses_ldq = cs_uses_ldq; // @[decode.scala:479:17, :490:16]
wire cs_decoder_12; // @[Decode.scala:50:77]
assign uop_uses_stq = cs_uses_stq; // @[decode.scala:479:17, :490:16]
wire cs_decoder_13; // @[Decode.scala:50:77]
assign uop_is_amo = cs_is_amo; // @[decode.scala:479:17, :490:16]
wire cs_decoder_14; // @[Decode.scala:50:77]
assign uop_is_fence = cs_is_fence; // @[decode.scala:479:17, :490:16]
wire cs_decoder_15; // @[Decode.scala:50:77]
assign uop_is_fencei = cs_is_fencei; // @[decode.scala:479:17, :490:16]
wire [4:0] cs_decoder_16; // @[Decode.scala:50:77]
assign uop_mem_cmd = cs_mem_cmd; // @[decode.scala:479:17, :490:16]
wire [1:0] cs_decoder_17; // @[Decode.scala:50:77]
wire cs_decoder_18; // @[Decode.scala:50:77]
assign uop_bypassable = cs_bypassable; // @[decode.scala:479:17, :490:16]
wire cs_decoder_19; // @[Decode.scala:50:77]
assign uop_is_br = cs_is_br; // @[decode.scala:479:17, :490:16]
wire cs_decoder_20; // @[Decode.scala:50:77]
assign uop_is_sys_pc2epc = cs_is_sys_pc2epc; // @[decode.scala:479:17, :490:16]
wire cs_decoder_21; // @[Decode.scala:50:77]
assign uop_is_unique = cs_inst_unique; // @[decode.scala:479:17, :490:16]
wire cs_decoder_22; // @[Decode.scala:50:77]
wire [2:0] cs_decoder_23; // @[Decode.scala:50:77]
wire cs_legal; // @[decode.scala:490:16]
wire [2:0] cs_imm_sel; // @[decode.scala:490:16]
wire [1:0] cs_wakeup_delay; // @[decode.scala:490:16]
wire cs_flush_on_commit; // @[decode.scala:490:16]
wire [2:0] cs_csr_cmd; // @[decode.scala:490:16]
wire [31:0] cs_decoder_decoded_invInputs = ~cs_decoder_decoded_plaInput; // @[pla.scala:77:22, :78:21]
wire [52:0] cs_decoder_decoded_invMatrixOutputs; // @[pla.scala:120:37]
wire [52:0] cs_decoder_decoded; // @[pla.scala:81:23]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_1 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_2 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_3 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_4 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_5 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_6 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_7 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_8 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_9 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_10 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_11 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_12 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_13 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_14 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_15 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_16 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_17 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_18 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_19 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_20 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_21 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_22 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_23 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_24 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_25 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_26 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_27 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_28 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_29 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_30 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_31 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_32 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_33 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_34 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_35 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_36 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_37 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_38 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_39 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_40 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_41 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_42 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_43 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_44 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_45 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_46 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_47 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_48 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_49 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_50 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_51 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_52 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_53 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_54 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_55 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_56 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_57 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_58 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_59 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_60 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_61 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_62 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_63 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_64 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_65 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_66 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_67 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_68 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_69 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_70 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_71 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_72 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_73 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_74 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_75 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_76 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_77 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_78 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_79 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_80 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_81 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_82 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_83 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_84 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_85 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_86 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_87 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_88 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_89 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_90 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_91 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_92 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_93 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_94 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_95 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_96 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_97 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_98 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_99 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_100 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_101 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_102 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_103 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_104 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_105 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_106 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_107 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_108 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_109 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_110 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_111 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_112 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_113 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_114 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_115 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_116 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_117 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_118 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_119 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_120 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_121 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_122 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_123 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_125 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_126 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_127 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_128 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_129 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_130 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_131 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_132 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_133 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_134 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_135 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_136 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_137 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_138 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_139 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_140 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_141 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_142 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_143 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_144 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_145 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_146 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_147 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_148 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_149 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_150 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_151 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_152 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_153 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_154 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_155 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_157 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_158 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_159 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_160 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_161 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_162 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_163 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_164 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_165 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_166 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_167 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_168 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_169 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_170 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_171 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_172 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_173 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_174 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_1 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_2 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_3 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_4 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_5 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_6 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_7 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_8 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_9 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_10 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_11 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_12 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_13 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_14 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_15 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_16 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_17 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_18 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_19 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_20 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_21 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_22 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_23 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_24 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_25 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_26 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_27 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_28 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_29 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_30 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_31 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_32 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_33 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_34 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_35 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_36 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_37 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_38 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_39 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_40 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_41 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_42 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_43 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_45 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_46 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_47 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_48 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_49 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_50 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_51 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_52 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_53 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_54 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_55 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_56 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_57 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_58 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_59 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_60 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_61 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_62 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_63 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_64 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_65 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_66 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_67 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_68 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_69 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_70 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_71 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_72 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_73 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_74 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_75 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_76 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_77 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_78 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_79 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_80 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_81 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_82 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_83 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_84 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_85 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_86 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_87 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_88 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_89 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_90 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_91 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_92 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_93 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_94 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_95 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_96 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_97 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_98 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_99 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_100 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_101 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_102 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_103 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_104 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_105 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_106 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_107 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_108 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_109 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_110 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_111 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_112 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_113 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_114 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_115 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_116 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_117 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_118 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_119 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_120 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_121 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_123 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_125 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_126 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_127 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_128 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_129 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_130 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_131 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_132 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_133 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_134 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_135 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_136 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_137 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_138 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_139 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_140 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_141 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_142 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_143 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_144 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_145 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_146 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_147 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_148 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_149 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_150 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_151 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_152 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_153 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_154 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_155 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_157 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_158 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_159 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_160 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_161 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_162 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_163 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_164 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_165 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_166 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_167 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_168 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_169 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_170 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_171 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_172 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_173 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_174 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_1 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_2 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_3 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_4 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_7 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_8 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_9 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_12 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_13 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_14 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_15 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_16 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_17 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_18 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_19 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_20 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_22 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_23 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_26 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_31 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_33 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_34 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_35 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_36 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_37 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_38 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_39 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_40 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_45 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_47 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_48 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_49 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_50 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_51 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_52 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_53 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_54 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_55 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_56 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_57 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_58 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_59 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_60 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_66 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_67 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_71 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_72 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_73 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_74 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_75 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_76 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_77 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_78 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_79 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_80 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_81 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_82 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_83 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_84 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_85 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_86 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_87 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_88 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_89 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_90 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_91 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_92 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_93 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_94 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_95 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_96 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_97 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_98 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_99 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_101 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_102 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_103 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_104 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_105 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_106 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_107 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_108 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_109 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_110 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_111 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_112 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_113 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_114 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_116 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_117 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_119 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_120 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_123 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_125 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_126 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_127 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_128 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_129 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_130 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_131 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_133 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_134 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_135 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_136 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_137 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_138 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_139 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_140 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_142 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_143 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_144 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_145 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_146 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_147 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_149 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_150 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_151 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_152 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_153 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_154 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_155 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_157 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_159 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_160 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_161 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_162 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_163 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_164 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_165 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_166 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_167 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_168 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_169 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_170 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_171 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_172 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_173 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_174 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_1 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_2 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_3 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_4 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_7 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_9 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_10 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_11 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_13 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_15 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_17 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_18 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_20 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_21 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_26 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_28 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_33 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_34 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_35 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_36 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_37 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_38 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_39 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_40 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_41 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_42 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_45 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_47 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_48 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_49 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_53 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_55 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_56 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_57 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_58 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_59 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_60 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_61 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_62 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_63 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_64 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_65 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_66 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_67 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_68 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_69 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_71 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_72 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_73 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_74 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_75 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_76 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_77 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_78 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_79 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_80 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_81 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_82 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_83 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_87 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_89 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_91 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_92 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_93 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_94 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_95 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_96 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_98 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_102 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_103 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_104 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_105 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_107 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_114 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_116 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_117 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_119 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_120 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_123 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_125 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_126 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_127 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_128 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_129 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_130 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_131 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_133 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_134 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_135 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_136 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_137 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_138 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_139 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_140 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_142 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_143 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_144 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_145 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_146 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_149 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_150 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_151 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_152 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_153 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_154 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_155 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_157 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_159 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_160 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_161 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_162 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_163 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_164 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_165 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_166 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_167 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_168 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_169 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_170 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_171 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_172 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_173 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_174 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_1 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_2 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_4 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_5 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_6 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_7 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_8 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_9 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_11 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_12 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_24 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_25 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_25 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_27 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_28 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_29 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_30 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_30 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_31 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_32 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_33 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_34 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_35 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_36 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_37 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_38 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_45 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_47 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_48 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_50 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_60 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_62 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_63 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_65 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_66 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_75 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_77 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_82 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_84 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_92 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_100 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_100 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_101 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_113 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_115 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_116 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_118 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_119 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_125 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_130 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_132 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_133 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_134 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_135 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_136 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_137 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_138 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_139 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_141 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_142 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_143 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_144 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_148 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_149 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_150 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_151 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_152 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_153 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_154 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_158 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_159 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_160 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_161 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_162 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_163 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_164 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_165 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_166 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_167 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_168 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_169 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_170 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_171 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_172 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_173 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_1 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_2 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_3 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_4 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_5 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_6 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_7 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_8 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_9 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_10 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_10 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_11 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_12 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_14 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_14 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_16 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_16 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_17 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_19 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_19 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_20 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_21 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_22 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_43 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_46 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_45 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_46 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_49 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_48 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_51 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_50 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_51 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_59 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_61 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_61 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_62 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_61 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_64 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_63 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_64 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_67 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_66 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_67 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_68 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_69 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_73 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_75 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_76 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_77 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_80 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_83 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_82 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_85 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_84 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_87 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_86 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_87 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_90 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_93 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_96 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_95 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_98 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_100 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_101 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_102 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_105 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_104 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_107 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_108 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_107 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_108 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_111 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_110 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_112 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_115 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_118 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_129 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_138 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_143 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_144 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_145 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_155 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_4 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_5 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_8 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_7 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_8 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_13 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_15 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_14 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_17 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_18 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_38 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_33 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_20 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_13 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_57 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_62 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_61 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_63 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_64 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_67 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_69 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_71 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_94 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_96 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_105 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_98 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_109 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_72 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_59 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_92 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_61 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_70 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_66 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_121 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_123 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_127 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_130 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_134 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_135 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_124 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_91 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_147 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_155 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_156 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_160 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_162 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo = {cs_decoder_decoded_andMatrixOutputs_lo_hi, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi = {cs_decoder_decoded_andMatrixOutputs_hi_hi, cs_decoder_decoded_andMatrixOutputs_hi_lo}; // @[pla.scala:98:53]
wire [6:0] _cs_decoder_decoded_andMatrixOutputs_T = {cs_decoder_decoded_andMatrixOutputs_hi, cs_decoder_decoded_andMatrixOutputs_lo}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_77_2 = &_cs_decoder_decoded_andMatrixOutputs_T; // @[pla.scala:98:{53,70}]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_1 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_2 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_3 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_4 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_5 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_6 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_13 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_24 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_25 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_26 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_27 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_28 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_29 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_30 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_31 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_32 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_40 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_41 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_42 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_43 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_46 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_57 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_61 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_62 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_63 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_64 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_65 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_68 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_69 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_70 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_81 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_82 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_91 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_94 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_100 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_101 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_115 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_118 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_121 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_132 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_141 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_148 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_158 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_1}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_1 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_lo_lo}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_1}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_1}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_1 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_hi_lo_1}; // @[pla.scala:98:53]
wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_1 = {cs_decoder_decoded_andMatrixOutputs_hi_1, cs_decoder_decoded_andMatrixOutputs_lo_1}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_84_2 = &_cs_decoder_decoded_andMatrixOutputs_T_1; // @[pla.scala:98:{53,70}]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_1 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_3 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_1 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_6 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_3 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_4 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_10 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_12 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_9 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_18 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_16 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_12 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_13 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_31 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_32 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_22 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_16 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_10 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_25 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_37 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_27 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_28 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_40 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_30 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_42 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_33 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_45 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_46 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_35 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_36 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_48 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_52 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_73 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_54 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_75 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_56 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_77 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_59 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_86 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_88 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_71 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_106 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_99 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_63 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_50 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_74 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_52 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_69 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_68 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_56 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_122 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_124 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_125 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_126 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_128 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_131 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_132 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_133 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_114 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_115 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_106 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_80 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_148 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_135 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_136 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_157 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_158 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_139 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_140 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_161 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_142 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_1}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_2}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_2 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_lo_lo_1}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_2}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_2}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_2 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_hi_lo_2}; // @[pla.scala:98:53]
wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_2 = {cs_decoder_decoded_andMatrixOutputs_hi_2, cs_decoder_decoded_andMatrixOutputs_lo_2}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_8_2 = &_cs_decoder_decoded_andMatrixOutputs_T_2; // @[pla.scala:98:{53,70}]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_3 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_2 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_2 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_1 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_2 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_9 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_5 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_7 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_15 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_11 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_10 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_11 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_21 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_19 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_15 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_8 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_22 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_25 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_31 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_34 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_31 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_32 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_58 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_51 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_52 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_37 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_38 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_39 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_57 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_40 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_41 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_35 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_36 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_87 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_68 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_53 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_72 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_83 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_89 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_61 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_42 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_65 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_44 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_67 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_65 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_48 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_100 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_101 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_102 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_103 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_104 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_105 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_106 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_107 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_108 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_109 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_110 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_111 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_112 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_113 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_96 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_97 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_116 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_97 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_68 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_126 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_127 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_128 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_117 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_118 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_137 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_138 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_121 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_122 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_141 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_124 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_3}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_3 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_3}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_3}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_3}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_3 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_3, cs_decoder_decoded_andMatrixOutputs_hi_lo_3}; // @[pla.scala:98:53]
wire [6:0] _cs_decoder_decoded_andMatrixOutputs_T_3 = {cs_decoder_decoded_andMatrixOutputs_hi_3, cs_decoder_decoded_andMatrixOutputs_lo_3}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_29_2 = &_cs_decoder_decoded_andMatrixOutputs_T_3; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_2}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_4}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_4 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_lo_lo_2}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_4}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_4}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_4 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_4, cs_decoder_decoded_andMatrixOutputs_hi_lo_4}; // @[pla.scala:98:53]
wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_4 = {cs_decoder_decoded_andMatrixOutputs_hi_4, cs_decoder_decoded_andMatrixOutputs_lo_4}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_124_2 = &_cs_decoder_decoded_andMatrixOutputs_T_4; // @[pla.scala:98:{53,70}]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_5 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_6 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_10 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_11 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_21 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_29 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_30 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_32 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_42 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_43 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_46 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_63 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_64 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_65 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_69 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_70 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_115 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_118 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_121 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_132 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_141 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_148 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_158 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_5 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_6 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_12 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_22 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_23 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_31 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_32 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_43 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_46 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_50 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_51 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_52 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_54 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_70 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_84 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_85 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_90 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_101 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_110 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_111 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_113 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_115 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_118 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_121 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_132 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_141 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_147 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_148 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_158 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_5}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_5 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_5, cs_decoder_decoded_andMatrixOutputs_lo_lo_3}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_5}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_5}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_5 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_5}; // @[pla.scala:90:45, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_5 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_5, cs_decoder_decoded_andMatrixOutputs_hi_lo_5}; // @[pla.scala:98:53]
wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_5 = {cs_decoder_decoded_andMatrixOutputs_hi_5, cs_decoder_decoded_andMatrixOutputs_lo_5}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_102_2 = &_cs_decoder_decoded_andMatrixOutputs_T_5; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_6}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_6 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_4}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_6 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_6, cs_decoder_decoded_andMatrixOutputs_lo_lo_4}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_6}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_6}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_6}; // @[pla.scala:90:45, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_6 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_hi_lo_6}; // @[pla.scala:98:53]
wire [9:0] _cs_decoder_decoded_andMatrixOutputs_T_6 = {cs_decoder_decoded_andMatrixOutputs_hi_6, cs_decoder_decoded_andMatrixOutputs_lo_6}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_85_2 = &_cs_decoder_decoded_andMatrixOutputs_T_6; // @[pla.scala:98:{53,70}]
wire _cs_decoder_decoded_orMatrixOutputs_T_26 = cs_decoder_decoded_andMatrixOutputs_85_2; // @[pla.scala:98:70, :114:36]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_7 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_8 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_9 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_10 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_11 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_12 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_14 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_15 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_16 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_17 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_18 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_19 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_20 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_21 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_22 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_23 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_33 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_34 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_35 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_36 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_37 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_38 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_39 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_44 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_45 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_47 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_48 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_49 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_50 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_51 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_52 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_53 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_54 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_58 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_59 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_66 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_67 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_71 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_72 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_73 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_74 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_75 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_76 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_77 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_78 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_79 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_80 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_83 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_84 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_85 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_86 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_87 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_88 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_89 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_90 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_92 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_93 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_95 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_96 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_97 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_98 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_99 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_102 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_103 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_104 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_105 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_106 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_107 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_108 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_109 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_110 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_111 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_112 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_113 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_114 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_116 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_117 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_119 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_120 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_122 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_123 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_124 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_125 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_126 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_127 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_128 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_129 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_130 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_131 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_133 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_134 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_135 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_136 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_137 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_138 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_139 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_140 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_142 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_143 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_144 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_145 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_146 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_147 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_149 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_150 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_151 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_152 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_153 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_154 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_155 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_156 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_157 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_159 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_160 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_161 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_162 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_163 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_164 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_165 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_166 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_167 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_168 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_169 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_170 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_171 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_172 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_173 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_174 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_5}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_7}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_7 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_7, cs_decoder_decoded_andMatrixOutputs_lo_lo_5}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_7}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_7}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_7 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_hi_lo_7}; // @[pla.scala:98:53]
wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_7 = {cs_decoder_decoded_andMatrixOutputs_hi_7, cs_decoder_decoded_andMatrixOutputs_lo_7}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_56_2 = &_cs_decoder_decoded_andMatrixOutputs_T_7; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_2}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_8}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_8 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_8, cs_decoder_decoded_andMatrixOutputs_lo_lo_6}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_8}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_8}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_8 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_8}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_8 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_8, cs_decoder_decoded_andMatrixOutputs_hi_lo_8}; // @[pla.scala:98:53]
wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_8 = {cs_decoder_decoded_andMatrixOutputs_hi_8, cs_decoder_decoded_andMatrixOutputs_lo_8}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_71_2 = &_cs_decoder_decoded_andMatrixOutputs_T_8; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_1}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_9}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_9 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_7}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_9 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_9, cs_decoder_decoded_andMatrixOutputs_lo_lo_7}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_9}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_9}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_9 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_9}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_9 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_9, cs_decoder_decoded_andMatrixOutputs_hi_lo_9}; // @[pla.scala:98:53]
wire [9:0] _cs_decoder_decoded_andMatrixOutputs_T_9 = {cs_decoder_decoded_andMatrixOutputs_hi_9, cs_decoder_decoded_andMatrixOutputs_lo_9}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_130_2 = &_cs_decoder_decoded_andMatrixOutputs_T_9; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_10}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_10 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_10}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_10}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_10 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_10}; // @[pla.scala:90:45, :98:53]
wire [5:0] _cs_decoder_decoded_andMatrixOutputs_T_10 = {cs_decoder_decoded_andMatrixOutputs_hi_10, cs_decoder_decoded_andMatrixOutputs_lo_10}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_34_2 = &_cs_decoder_decoded_andMatrixOutputs_T_10; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_11}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_11 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_10}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_11}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_11}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_11 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_11, cs_decoder_decoded_andMatrixOutputs_hi_lo_10}; // @[pla.scala:98:53]
wire [6:0] _cs_decoder_decoded_andMatrixOutputs_T_11 = {cs_decoder_decoded_andMatrixOutputs_hi_11, cs_decoder_decoded_andMatrixOutputs_lo_11}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_163_2 = &_cs_decoder_decoded_andMatrixOutputs_T_11; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_2}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_11}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_12 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_8}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_12 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_12, cs_decoder_decoded_andMatrixOutputs_lo_lo_8}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_12}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_12}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_12 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_12}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_12 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_12, cs_decoder_decoded_andMatrixOutputs_hi_lo_11}; // @[pla.scala:98:53]
wire [9:0] _cs_decoder_decoded_andMatrixOutputs_T_12 = {cs_decoder_decoded_andMatrixOutputs_hi_12, cs_decoder_decoded_andMatrixOutputs_lo_12}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_48_2 = &_cs_decoder_decoded_andMatrixOutputs_T_12; // @[pla.scala:98:{53,70}]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_13 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_14 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_15 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_16 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_17 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_18 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_19 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_20 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_21 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_22 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_23 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_39 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_41 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_41 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_42 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_44 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_44 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_52 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_53 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_55 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_56 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_56 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_57 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_58 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_68 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_68 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_69 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_70 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_71 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_72 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_73 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_74 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_76 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_78 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_79 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_80 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_81 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_86 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_86 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_88 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_88 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_89 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_90 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_91 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_93 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_94 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_95 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_97 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_97 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_99 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_102 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_103 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_104 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_106 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_106 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_108 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_109 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_109 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_110 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_112 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_112 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_114 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_117 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_120 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_122 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_122 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_124 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_124 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_126 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_127 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_128 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_129 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_131 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_140 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_145 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_146 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_147 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_156 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_156 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_157 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_9}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_13}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_13 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_13, cs_decoder_decoded_andMatrixOutputs_lo_lo_9}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_13}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_13}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_13 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_13, cs_decoder_decoded_andMatrixOutputs_hi_lo_12}; // @[pla.scala:98:53]
wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_13 = {cs_decoder_decoded_andMatrixOutputs_hi_13, cs_decoder_decoded_andMatrixOutputs_lo_13}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_110_2 = &_cs_decoder_decoded_andMatrixOutputs_T_13; // @[pla.scala:98:{53,70}]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_3 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_13 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_7 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_10 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_9 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_7 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_26 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_25 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_27 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_25 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_27 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_30 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_1 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_29 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_27 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_28 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_32 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_30 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_39 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_41 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_33 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_43 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_35 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_46 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_38 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_107 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_2 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_3 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_4 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_5 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_85 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_86 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_88 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_87 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_88 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_83 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_84 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_88 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_104 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_51 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_80 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_11 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_5 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_8 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_4 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_8 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_6 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_7 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_8 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_24 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_19 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_24 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_20 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_26 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_21 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_22 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_23 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_24 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_15 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_26 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_17 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_28 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_29 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_20 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_1 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_26 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_24 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_20 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_26 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_22 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_23 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_29 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_25 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_42 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_28 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_49 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_30 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_31 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_32 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_31 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_34 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_33 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_45 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_37 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_36 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_65 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_49 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_50 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_42 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_97 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_69 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_70 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_42 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_45 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_46 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_74 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_57 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_58 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_59 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_51 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_52 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_53 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_52 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_102 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_84 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_85 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_87 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_108 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_2 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_3 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_4 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_5 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_94 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_66 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_54 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_47 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_13 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_119 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_83 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_84 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_76 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_77 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_87 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_79 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_89 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_90 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_83 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_84 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_85 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_95 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_85 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_86 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_72 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_73 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_74 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_75 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_87 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_77 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_78 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_6 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_7 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_109 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_110 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_94 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_103 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_102 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_105 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_104 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_107 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_50 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_26 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_79 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_53 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_54 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_30 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_56 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_57 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_6 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_2 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_6 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_4 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_5 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_6 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_7 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_8 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_16 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_15 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_19 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_18 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_1 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_23 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_19 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_19 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_21 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_21 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_22 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_24 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_24 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_33 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_34 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_26 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_38 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_28 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_29 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_30 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_28 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_32 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_30 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_36 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_35 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_33 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_48 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_40 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_41 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_40 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_39 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_43 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_44 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_56 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_48 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_49 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_50 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_49 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_50 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_51 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_49 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_54 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_88 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_40 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_2 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_3 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_4 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_5 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_63 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_46 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_32 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_9 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_74 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_75 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_74 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_75 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_80 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_81 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_91 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_81 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_82 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_81 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_82 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_98 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_60 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_61 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_62 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_63 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_108 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_100 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_101 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_83 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_101 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_96 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_103 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_98 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_105 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_25 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_20 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_52 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_28 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_29 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_24 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_31 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_32 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_4 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_2 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_3 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_4 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_5 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_6 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_6 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_8 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_18 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_17 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_15 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_1 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_18 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_18 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_16 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_20 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_18 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_19 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_23 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_21 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_26 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_27 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_23 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_29 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_25 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_26 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_27 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_25 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_29 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_27 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_34 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_32 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_30 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_39 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_38 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_39 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_37 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_52 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_35 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_40 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_41 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_47 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_46 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_47 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_48 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_46 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_47 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_48 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_45 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_64 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_58 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_72 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_73 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_71 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_72 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_78 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_77 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_78 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_79 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_82 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_77 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_78 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_83 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_84 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_70 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_71 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_89 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_36 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_37 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_38 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_39 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_99 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_98 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_99 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_97 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_27 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_22 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_23 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_25 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_1 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_2 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_3 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_3 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_5 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_5 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_5 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_7 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_14 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_13 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_14 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_12 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_16 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_14 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_14 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_28 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_17 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_15 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_13 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_17 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_15 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_16 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_20 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_18 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_25 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_20 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_27 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_22 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_23 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_24 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_20 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_26 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_22 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_31 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_29 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_25 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_37 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_35 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_36 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_34 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_43 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_29 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_36 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_37 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_45 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_43 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_44 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_45 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_42 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_43 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_44 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_38 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_55 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_56 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_57 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_56 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_39 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_60 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_61 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_5 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_4 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_29_2 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_67 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_45 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_11 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_8 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_7 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_72 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_71 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_58 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_59 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_16 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_17 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_18 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_19 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_40 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_21 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_22 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_95 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_85 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_86 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_87 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_88 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_1 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_1 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_2 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_3 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_1 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_2 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_3 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_9 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_9 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_10 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_9 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_12 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_10 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_8 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_30 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_11 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_9 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_6 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_11 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_7 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_8 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_14 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_9 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_19 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_10 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_21 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_11 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_18 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_19 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_12 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_21 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_13 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_23 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_14 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_15 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_31 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_26 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_27 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_16 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_38 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_2 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_18 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_19 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_38 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_32 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_33 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_34 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_20 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_21 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_22 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_3 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_50 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_51 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_52 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_46 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_4 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_55 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_56 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_2 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_2 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_30_1 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_4 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_31 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_62 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_10 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_7 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_6 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_6 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_67 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_57 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_62 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_51 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_52 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_53 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_56 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_57 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_14 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_15 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_10 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_11 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_14 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_12 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_13 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_6 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_31_1 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_10 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_3}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_14 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_3, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_14 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_14, cs_decoder_decoded_andMatrixOutputs_lo_lo_10}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_10}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_14}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_13 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_14}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_14}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_14 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_5, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_14 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_14, cs_decoder_decoded_andMatrixOutputs_hi_lo_13}; // @[pla.scala:98:53]
wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_14 = {cs_decoder_decoded_andMatrixOutputs_hi_14, cs_decoder_decoded_andMatrixOutputs_lo_14}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_170_2 = &_cs_decoder_decoded_andMatrixOutputs_T_14; // @[pla.scala:98:{53,70}]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_1 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_1 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_3 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_2 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_4 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_4 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_6 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_12 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_10 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_11 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_11 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_13 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_13 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_11 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_29 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_14 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_12 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_10 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_14 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_12 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_13 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_17 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_15 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_22 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_16 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_24 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_17 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_28 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_24 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_34 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_32 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_33 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_28 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_41 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_17 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_30 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_31 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_42 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_39 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_40 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_41 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_35 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_36 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_37 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_23 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_53 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_54 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_55 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_53 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_24 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_58 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_59 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_2 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_2 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_29_1 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_4 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_30_2 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_65 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_30 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_7 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_8 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_6 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_70 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_68 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_58 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_59 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_49 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_50 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_73 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_63 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_64 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_65 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_54 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_55 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_68 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_69 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_81 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_82 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_1}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_11 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_1}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_6}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_15 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_4}; // @[pla.scala:91:29, :98:53]
wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_15 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_15, cs_decoder_decoded_andMatrixOutputs_lo_lo_11}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_15}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_14 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_14}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_15}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_15}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_15 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_1}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_15 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_15, cs_decoder_decoded_andMatrixOutputs_hi_lo_14}; // @[pla.scala:98:53]
wire [12:0] _cs_decoder_decoded_andMatrixOutputs_T_15 = {cs_decoder_decoded_andMatrixOutputs_hi_15, cs_decoder_decoded_andMatrixOutputs_lo_15}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_5_2 = &_cs_decoder_decoded_andMatrixOutputs_T_15; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_1}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_12 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_1}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_2}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_5}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_16 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_5, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_1}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_16 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_16, cs_decoder_decoded_andMatrixOutputs_lo_lo_12}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_12}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_16}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_15 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_1}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_16}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_16}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_16 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_2}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_16 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_16, cs_decoder_decoded_andMatrixOutputs_hi_lo_15}; // @[pla.scala:98:53]
wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_16 = {cs_decoder_decoded_andMatrixOutputs_hi_16, cs_decoder_decoded_andMatrixOutputs_lo_16}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_75_2 = &_cs_decoder_decoded_andMatrixOutputs_T_16; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_3}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_13 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_2}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_3}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_8}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_17 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_2}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_17 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_17, cs_decoder_decoded_andMatrixOutputs_lo_lo_13}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_17}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_16 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_16}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_17}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_17}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_17 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_8, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_3}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_17 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_17, cs_decoder_decoded_andMatrixOutputs_hi_lo_16}; // @[pla.scala:98:53]
wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_17 = {cs_decoder_decoded_andMatrixOutputs_hi_17, cs_decoder_decoded_andMatrixOutputs_lo_17}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_12_2 = &_cs_decoder_decoded_andMatrixOutputs_T_17; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_3}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_14 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_4}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_7}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_18 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_3}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_18 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_18, cs_decoder_decoded_andMatrixOutputs_lo_lo_14}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_14}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_18}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_17 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_2}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_18}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_18}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_18 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_9, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_4}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_18 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_18, cs_decoder_decoded_andMatrixOutputs_hi_lo_17}; // @[pla.scala:98:53]
wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_18 = {cs_decoder_decoded_andMatrixOutputs_hi_18, cs_decoder_decoded_andMatrixOutputs_lo_18}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_35_2 = &_cs_decoder_decoded_andMatrixOutputs_T_18; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_4}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_15 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_3}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_5}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_8}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_19 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_8, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_4}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_19 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_19, cs_decoder_decoded_andMatrixOutputs_lo_lo_15}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_15}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_19}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_18 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_5, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_3}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_19}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_19}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_19 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_10, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_5}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_19 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_19, cs_decoder_decoded_andMatrixOutputs_hi_lo_18}; // @[pla.scala:98:53]
wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_19 = {cs_decoder_decoded_andMatrixOutputs_hi_19, cs_decoder_decoded_andMatrixOutputs_lo_19}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_30_2 = &_cs_decoder_decoded_andMatrixOutputs_T_19; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_1}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_5}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_16 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_6, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_1}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_6}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_9}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_20 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_9, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_5}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_20 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_20, cs_decoder_decoded_andMatrixOutputs_lo_lo_16}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_16}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_20}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_19 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_6, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_4}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_20}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_20}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_20 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_11, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_6}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_20 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_20, cs_decoder_decoded_andMatrixOutputs_hi_lo_19}; // @[pla.scala:98:53]
wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_20 = {cs_decoder_decoded_andMatrixOutputs_hi_20, cs_decoder_decoded_andMatrixOutputs_lo_20}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_24_2 = &_cs_decoder_decoded_andMatrixOutputs_T_20; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_21}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_21 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_20}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_21}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_21}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_21 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_21, cs_decoder_decoded_andMatrixOutputs_hi_lo_20}; // @[pla.scala:98:53]
wire [6:0] _cs_decoder_decoded_andMatrixOutputs_T_21 = {cs_decoder_decoded_andMatrixOutputs_hi_21, cs_decoder_decoded_andMatrixOutputs_lo_21}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_144_2 = &_cs_decoder_decoded_andMatrixOutputs_T_21; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_2}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_6}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_17 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_7, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_2}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_7}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_10}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_22 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_10, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_6}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_22 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_22, cs_decoder_decoded_andMatrixOutputs_lo_lo_17}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_17}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_22}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_21 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_7, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_5}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_22}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_22}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_22 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_12, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_7}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_22 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_22, cs_decoder_decoded_andMatrixOutputs_hi_lo_21}; // @[pla.scala:98:53]
wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_22 = {cs_decoder_decoded_andMatrixOutputs_hi_22, cs_decoder_decoded_andMatrixOutputs_lo_22}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_28_2 = &_cs_decoder_decoded_andMatrixOutputs_T_22; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_3}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_7}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_18 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_8, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_3}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_8}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_11}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_23 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_11, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_7}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_23 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_23, cs_decoder_decoded_andMatrixOutputs_lo_lo_18}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_18}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_23}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_22 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_8, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_6}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_23}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_23}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_23 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_13, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_8}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_23 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_23, cs_decoder_decoded_andMatrixOutputs_hi_lo_22}; // @[pla.scala:98:53]
wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_23 = {cs_decoder_decoded_andMatrixOutputs_hi_23, cs_decoder_decoded_andMatrixOutputs_lo_23}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_126_2 = &_cs_decoder_decoded_andMatrixOutputs_T_23; // @[pla.scala:98:{53,70}]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_24 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_25 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_23 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_27 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_27 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_28 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_29 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_28 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_29 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_30 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_31 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_32 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_33 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_34 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_35 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_36 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_37 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_40 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_39 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_40 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_44 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_42 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_54 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_55 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_54 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_55 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_56 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_70 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_71 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_72 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_74 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_78 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_79 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_88 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_89 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_91 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_92 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_100 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_98 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_99 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_111 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_113 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_114 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_116 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_117 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_122 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_120 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_124 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_122 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_123 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_124 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_125 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_126 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_127 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_128 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_130 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_131 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_132 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_133 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_134 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_135 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_136 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_137 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_139 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_140 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_141 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_142 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_146 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_147 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_148 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_149 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_150 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_151 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_152 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_156 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_154 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_156 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_157 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_158 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_159 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_160 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_161 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_162 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_163 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_164 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_165 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_166 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_167 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_168 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_169 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_170 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_171 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_24}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_24}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_24 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_24}; // @[pla.scala:91:29, :98:53]
wire [4:0] _cs_decoder_decoded_andMatrixOutputs_T_24 = {cs_decoder_decoded_andMatrixOutputs_hi_24, cs_decoder_decoded_andMatrixOutputs_lo_24}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_162_2 = &_cs_decoder_decoded_andMatrixOutputs_T_24; // @[pla.scala:98:{53,70}]
wire _cs_decoder_decoded_orMatrixOutputs_T_38 = cs_decoder_decoded_andMatrixOutputs_162_2; // @[pla.scala:98:70, :114:36]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_25}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_25 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_24}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_25}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_25 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_25}; // @[pla.scala:91:29, :98:53]
wire [5:0] _cs_decoder_decoded_andMatrixOutputs_T_25 = {cs_decoder_decoded_andMatrixOutputs_hi_25, cs_decoder_decoded_andMatrixOutputs_lo_25}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_1_2 = &_cs_decoder_decoded_andMatrixOutputs_T_25; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_19}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_25}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_26 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_25, cs_decoder_decoded_andMatrixOutputs_lo_lo_19}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_26}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_26}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_26 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_26, cs_decoder_decoded_andMatrixOutputs_hi_lo_23}; // @[pla.scala:98:53]
wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_26 = {cs_decoder_decoded_andMatrixOutputs_hi_26, cs_decoder_decoded_andMatrixOutputs_lo_26}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_17_2 = &_cs_decoder_decoded_andMatrixOutputs_T_26; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_26}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_27 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_24}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_27}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_27}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_27 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_27, cs_decoder_decoded_andMatrixOutputs_hi_lo_24}; // @[pla.scala:98:53]
wire [6:0] _cs_decoder_decoded_andMatrixOutputs_T_27 = {cs_decoder_decoded_andMatrixOutputs_hi_27, cs_decoder_decoded_andMatrixOutputs_lo_27}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_98_2 = &_cs_decoder_decoded_andMatrixOutputs_T_27; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_20}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_27}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_28 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_27, cs_decoder_decoded_andMatrixOutputs_lo_lo_20}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_28}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_28}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_28 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_28, cs_decoder_decoded_andMatrixOutputs_hi_lo_25}; // @[pla.scala:98:53]
wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_28 = {cs_decoder_decoded_andMatrixOutputs_hi_28, cs_decoder_decoded_andMatrixOutputs_lo_28}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_27_2 = &_cs_decoder_decoded_andMatrixOutputs_T_28; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_28}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_29 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_26}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_29}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_29 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_29}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_29 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_29, cs_decoder_decoded_andMatrixOutputs_hi_lo_26}; // @[pla.scala:98:53]
wire [6:0] _cs_decoder_decoded_andMatrixOutputs_T_29 = {cs_decoder_decoded_andMatrixOutputs_hi_29, cs_decoder_decoded_andMatrixOutputs_lo_29}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_105_2 = &_cs_decoder_decoded_andMatrixOutputs_T_29; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_21}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_29 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_29}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_30 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_29, cs_decoder_decoded_andMatrixOutputs_lo_lo_21}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_30}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_30 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_30}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_30 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_30, cs_decoder_decoded_andMatrixOutputs_hi_lo_27}; // @[pla.scala:98:53]
wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_30 = {cs_decoder_decoded_andMatrixOutputs_hi_30, cs_decoder_decoded_andMatrixOutputs_lo_30}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_122_2 = &_cs_decoder_decoded_andMatrixOutputs_T_30; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_22}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_30 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_30}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_31 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_30, cs_decoder_decoded_andMatrixOutputs_lo_lo_22}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_31}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_31 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_31}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_31 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_31, cs_decoder_decoded_andMatrixOutputs_hi_lo_28}; // @[pla.scala:98:53]
wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_31 = {cs_decoder_decoded_andMatrixOutputs_hi_31, cs_decoder_decoded_andMatrixOutputs_lo_31}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_38_2 = &_cs_decoder_decoded_andMatrixOutputs_T_31; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_23}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_31 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_31}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_32 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_31, cs_decoder_decoded_andMatrixOutputs_lo_lo_23}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_29 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_32}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_32 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_32}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_32 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_32, cs_decoder_decoded_andMatrixOutputs_hi_lo_29}; // @[pla.scala:98:53]
wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_32 = {cs_decoder_decoded_andMatrixOutputs_hi_32, cs_decoder_decoded_andMatrixOutputs_lo_32}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_165_2 = &_cs_decoder_decoded_andMatrixOutputs_T_32; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_9}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_24}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_32 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_14}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_33 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_32, cs_decoder_decoded_andMatrixOutputs_lo_lo_24}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_33, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_33}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_30 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_32}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_33, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_33}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_33 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_33}; // @[pla.scala:91:29, :98:53]
wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_33 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_33, cs_decoder_decoded_andMatrixOutputs_hi_lo_30}; // @[pla.scala:98:53]
wire [10:0] _cs_decoder_decoded_andMatrixOutputs_T_33 = {cs_decoder_decoded_andMatrixOutputs_hi_33, cs_decoder_decoded_andMatrixOutputs_lo_33}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_19_2 = &_cs_decoder_decoded_andMatrixOutputs_T_33; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_10}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_25 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_9}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_25}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_33 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_15}; // @[pla.scala:91:29, :98:53]
wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_34 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_33, cs_decoder_decoded_andMatrixOutputs_lo_lo_25}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_34, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_34}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_31 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_33}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_34, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_34}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_34 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_34}; // @[pla.scala:91:29, :98:53]
wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_34 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_34, cs_decoder_decoded_andMatrixOutputs_hi_lo_31}; // @[pla.scala:98:53]
wire [11:0] _cs_decoder_decoded_andMatrixOutputs_T_34 = {cs_decoder_decoded_andMatrixOutputs_hi_34, cs_decoder_decoded_andMatrixOutputs_lo_34}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_118_2 = &_cs_decoder_decoded_andMatrixOutputs_T_34; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_11}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_26 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_10}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_26}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_34 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_16}; // @[pla.scala:91:29, :98:53]
wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_35 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_34, cs_decoder_decoded_andMatrixOutputs_lo_lo_26}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_35}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_32 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_34}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_16 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_35}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_35 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_35}; // @[pla.scala:91:29, :98:53]
wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_35 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_35, cs_decoder_decoded_andMatrixOutputs_hi_lo_32}; // @[pla.scala:98:53]
wire [11:0] _cs_decoder_decoded_andMatrixOutputs_T_35 = {cs_decoder_decoded_andMatrixOutputs_hi_35, cs_decoder_decoded_andMatrixOutputs_lo_35}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_153_2 = &_cs_decoder_decoded_andMatrixOutputs_T_35; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_11}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_27 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_9}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_17}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_35 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_15}; // @[pla.scala:91:29, :98:53]
wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_36 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_35, cs_decoder_decoded_andMatrixOutputs_lo_lo_27}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_35}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_33 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_33}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_36}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_36}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_36 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_17, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_9}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_36 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_36, cs_decoder_decoded_andMatrixOutputs_hi_lo_33}; // @[pla.scala:98:53]
wire [12:0] _cs_decoder_decoded_andMatrixOutputs_T_36 = {cs_decoder_decoded_andMatrixOutputs_hi_36, cs_decoder_decoded_andMatrixOutputs_lo_36}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_141_2 = &_cs_decoder_decoded_andMatrixOutputs_T_36; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_13}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_28 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_12}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_16 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_34, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_28}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_36 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_18}; // @[pla.scala:91:29, :98:53]
wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_37 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_36, cs_decoder_decoded_andMatrixOutputs_lo_lo_28}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_37}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_34 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_36}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_37}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_37 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_37}; // @[pla.scala:91:29, :98:53]
wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_37 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_37, cs_decoder_decoded_andMatrixOutputs_hi_lo_34}; // @[pla.scala:98:53]
wire [11:0] _cs_decoder_decoded_andMatrixOutputs_T_37 = {cs_decoder_decoded_andMatrixOutputs_hi_37, cs_decoder_decoded_andMatrixOutputs_lo_37}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_168_2 = &_cs_decoder_decoded_andMatrixOutputs_T_37; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_13}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_29 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_10}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_19}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_37 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_17}; // @[pla.scala:91:29, :98:53]
wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_38 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_37, cs_decoder_decoded_andMatrixOutputs_lo_lo_29}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_38, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_37}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_35 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_35}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_38, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_38}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_38, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_38}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_38 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_19, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_10}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_38 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_38, cs_decoder_decoded_andMatrixOutputs_hi_lo_35}; // @[pla.scala:98:53]
wire [12:0] _cs_decoder_decoded_andMatrixOutputs_T_38 = {cs_decoder_decoded_andMatrixOutputs_hi_38, cs_decoder_decoded_andMatrixOutputs_lo_38}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_73_2 = &_cs_decoder_decoded_andMatrixOutputs_T_38; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_11}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_30 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_8}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_15}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_20}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_38 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_18, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_8}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_39 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_38, cs_decoder_decoded_andMatrixOutputs_lo_lo_30}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_38}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_36 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_36}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_39}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_39}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_39 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_20, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_11}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_39 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_39, cs_decoder_decoded_andMatrixOutputs_hi_lo_36}; // @[pla.scala:98:53]
wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_39 = {cs_decoder_decoded_andMatrixOutputs_hi_39, cs_decoder_decoded_andMatrixOutputs_lo_39}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_25_2 = &_cs_decoder_decoded_andMatrixOutputs_T_39; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_31 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_31}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_39 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_40, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_39}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_40 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_39, cs_decoder_decoded_andMatrixOutputs_lo_lo_31}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_37 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_40, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_40}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_40 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_40, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_40}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_40 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_40, cs_decoder_decoded_andMatrixOutputs_hi_lo_37}; // @[pla.scala:98:53]
wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_40 = {cs_decoder_decoded_andMatrixOutputs_hi_40, cs_decoder_decoded_andMatrixOutputs_lo_40}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_79_2 = &_cs_decoder_decoded_andMatrixOutputs_T_40; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_32 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_21}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_40 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_40, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_38}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_41 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_40, cs_decoder_decoded_andMatrixOutputs_lo_lo_32}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_38 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_41}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_41}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_41 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_41}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_41 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_41, cs_decoder_decoded_andMatrixOutputs_hi_lo_38}; // @[pla.scala:98:53]
wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_41 = {cs_decoder_decoded_andMatrixOutputs_hi_41, cs_decoder_decoded_andMatrixOutputs_lo_41}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_114_2 = &_cs_decoder_decoded_andMatrixOutputs_T_41; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_33 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_19}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_39}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_41 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_33}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_42 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_41, cs_decoder_decoded_andMatrixOutputs_lo_lo_33}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_39 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_42, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_42}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_42, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_42}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_42 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_42}; // @[pla.scala:90:45, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_42 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_42, cs_decoder_decoded_andMatrixOutputs_hi_lo_39}; // @[pla.scala:98:53]
wire [9:0] _cs_decoder_decoded_andMatrixOutputs_T_42 = {cs_decoder_decoded_andMatrixOutputs_hi_42, cs_decoder_decoded_andMatrixOutputs_lo_42}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_174_2 = &_cs_decoder_decoded_andMatrixOutputs_T_42; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_42 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_43, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_42}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_43 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_42, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_40}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_40 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_43, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_43}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_43 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_43, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_43}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_43 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_43, cs_decoder_decoded_andMatrixOutputs_hi_lo_40}; // @[pla.scala:98:53]
wire [6:0] _cs_decoder_decoded_andMatrixOutputs_T_43 = {cs_decoder_decoded_andMatrixOutputs_hi_43, cs_decoder_decoded_andMatrixOutputs_lo_43}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_139_2 = &_cs_decoder_decoded_andMatrixOutputs_T_43; // @[pla.scala:98:{53,70}]
wire _cs_decoder_decoded_orMatrixOutputs_T_37 = cs_decoder_decoded_andMatrixOutputs_139_2; // @[pla.scala:98:70, :114:36]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_44 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_35 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_122 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_111 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_124 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_113 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_115 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_116 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_117 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_118 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_156 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_145 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_43 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_24 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_121 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_91 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_124 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_93 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_95 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_96 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_97 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_98 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_156 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_125 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_41 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_21 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_119 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_73 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_123 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_75 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_77 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_78 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_79 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_80 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_155 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_107 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_34 = cs_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_17 = cs_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_110 = cs_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_64 = cs_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_121 = cs_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_66 = cs_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_71 = cs_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_153 = cs_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_98 = cs_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_23 = cs_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_16 = cs_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_90 = cs_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_62 = cs_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_112 = cs_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_64 = cs_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_69 = cs_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_144 = cs_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_96 = cs_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_12 = cs_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_5 = cs_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_58 = cs_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_27 = cs_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_63 = cs_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_29 = cs_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_95 = cs_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_44 = cs_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_9 = cs_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_1 = cs_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_49 = cs_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_7 = cs_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_60 = cs_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_9 = cs_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_90 = cs_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_24 = cs_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_7 = cs_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_1 = cs_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_41 = cs_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_4 = cs_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_51 = cs_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_6 = cs_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_79 = cs_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_18 = cs_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_4 = cs_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_1 = cs_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_26 = cs_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_4 = cs_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_43 = cs_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_6 = cs_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_67 = cs_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_15 = cs_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16 = cs_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_1 = cs_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_6 = cs_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_3 = cs_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_28 = cs_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_5 = cs_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_43 = cs_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_9 = cs_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_1 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_86 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_62 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_5 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_5 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_117 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_118 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_119 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_120 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_121 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_122 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_123 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_129 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_106 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_107 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_110 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_111 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_110 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_111 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_114 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_113 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_1 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_68 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_60 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_2 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_3 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_99 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_100 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_101 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_102 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_103 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_104 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_105 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_14 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_7 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_111 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_150 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_151 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_152 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_153 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_154 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_100 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_101 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_108 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_109 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_104 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_105 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_112 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_107 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_1 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_59 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_57 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_2 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_3 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_4 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_5 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_90 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_91 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_92 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_93 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_94 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_95 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_96 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_8 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_7 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_102 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_130 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_131 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_132 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_133 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_134 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_89 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_90 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_102 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_103 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_93 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_94 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_106 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_96 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_1 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_57 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_48 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_2 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_3 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_4 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_5 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_88 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_89 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_90 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_91 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_92 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_93 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_94 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_100 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_112 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_113 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_114 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_115 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_116 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_77 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_78 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_91 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_92 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_81 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_82 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_95 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_84 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_4 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_15 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_34 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_15, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_4}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_9 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_4}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_20 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_43 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_20, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_9}; // @[pla.scala:98:53]
wire [13:0] cs_decoder_decoded_andMatrixOutputs_lo_44 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_43, cs_decoder_decoded_andMatrixOutputs_lo_lo_34}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_12}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_7 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_9}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_16}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_34, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_23}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_16 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_41 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_16, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_7}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_44, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_43}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_12 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_41}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_44, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_44}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_44, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_44}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_23 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_44 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_23, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_12}; // @[pla.scala:98:53]
wire [13:0] cs_decoder_decoded_andMatrixOutputs_hi_44 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_44, cs_decoder_decoded_andMatrixOutputs_hi_lo_41}; // @[pla.scala:98:53]
wire [27:0] _cs_decoder_decoded_andMatrixOutputs_T_44 = {cs_decoder_decoded_andMatrixOutputs_hi_44, cs_decoder_decoded_andMatrixOutputs_lo_44}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_43_2 = &_cs_decoder_decoded_andMatrixOutputs_T_44; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_29}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_5 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_30}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_1}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_1}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_16 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_1}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_35 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_16, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_5}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_1}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_1}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_10 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_1}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_1}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_21 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_1}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_44 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_21, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_10}; // @[pla.scala:98:53]
wire [14:0] cs_decoder_decoded_andMatrixOutputs_lo_45 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_44, cs_decoder_decoded_andMatrixOutputs_lo_lo_35}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_5}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_10}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_8 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_16}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_21}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_17 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_1}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_42 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_17, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_8}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_42, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_35}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_44}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_13 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_45}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_45}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_24 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_1}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_45 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_24, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_13}; // @[pla.scala:98:53]
wire [15:0] cs_decoder_decoded_andMatrixOutputs_hi_45 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_45, cs_decoder_decoded_andMatrixOutputs_hi_lo_42}; // @[pla.scala:98:53]
wire [30:0] _cs_decoder_decoded_andMatrixOutputs_T_45 = {cs_decoder_decoded_andMatrixOutputs_hi_45, cs_decoder_decoded_andMatrixOutputs_lo_45}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_67_2 = &_cs_decoder_decoded_andMatrixOutputs_T_45; // @[pla.scala:98:{53,70}]
wire _cs_decoder_decoded_orMatrixOutputs_T_8 = cs_decoder_decoded_andMatrixOutputs_67_2; // @[pla.scala:98:70, :114:36]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_36 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_44 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_38 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_39 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_47 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_41 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_49 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_43 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_44 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_52 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_53 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_47 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_48 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_49 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_65 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_66 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_72 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_81 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_74 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_83 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_76 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_85 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_78 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_79 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_80 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_81 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_91 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_93 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_101 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_159 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_36 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_22}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_43}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_45 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_36}; // @[pla.scala:90:45, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_46 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_45, cs_decoder_decoded_andMatrixOutputs_lo_lo_36}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_43 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_46, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_46}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_46, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_46}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_46 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_46}; // @[pla.scala:90:45, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_46 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_46, cs_decoder_decoded_andMatrixOutputs_hi_lo_43}; // @[pla.scala:98:53]
wire [9:0] _cs_decoder_decoded_andMatrixOutputs_T_46 = {cs_decoder_decoded_andMatrixOutputs_hi_46, cs_decoder_decoded_andMatrixOutputs_lo_46}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_18_2 = &_cs_decoder_decoded_andMatrixOutputs_T_46; // @[pla.scala:98:{53,70}]
wire _cs_decoder_decoded_orMatrixOutputs_T_25 = cs_decoder_decoded_andMatrixOutputs_18_2; // @[pla.scala:98:70, :114:36]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_14}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_37 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_11}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_18}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_26}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_46 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_23, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_11}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_47 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_46, cs_decoder_decoded_andMatrixOutputs_lo_lo_37}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_47, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_46}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_44 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_44}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_47, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_47}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_47, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_47}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_47 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_26, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_14}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_47 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_47, cs_decoder_decoded_andMatrixOutputs_hi_lo_44}; // @[pla.scala:98:53]
wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_47 = {cs_decoder_decoded_andMatrixOutputs_hi_47, cs_decoder_decoded_andMatrixOutputs_lo_47}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_108_2 = &_cs_decoder_decoded_andMatrixOutputs_T_47; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_12}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_38 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_9}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_18}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_24}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_47 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_24, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_12}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_48 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_47, cs_decoder_decoded_andMatrixOutputs_lo_lo_38}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_38}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_47}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_45 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_19, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_9}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_48}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_48}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_48 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_27, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_15}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_48 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_48, cs_decoder_decoded_andMatrixOutputs_hi_lo_45}; // @[pla.scala:98:53]
wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_48 = {cs_decoder_decoded_andMatrixOutputs_hi_48, cs_decoder_decoded_andMatrixOutputs_lo_48}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_46_2 = &_cs_decoder_decoded_andMatrixOutputs_T_48; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_6}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_13}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_39 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_19, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_6}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_19}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_25}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_48 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_25, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_13}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_49 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_48, cs_decoder_decoded_andMatrixOutputs_lo_lo_39}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_46, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_39}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_49, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_48}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_46 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_20, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_10}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_16 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_49, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_49}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_49, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_49}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_49 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_28, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_16}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_49 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_49, cs_decoder_decoded_andMatrixOutputs_hi_lo_46}; // @[pla.scala:98:53]
wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_49 = {cs_decoder_decoded_andMatrixOutputs_hi_49, cs_decoder_decoded_andMatrixOutputs_lo_49}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_10_2 = &_cs_decoder_decoded_andMatrixOutputs_T_49; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_14}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_40 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_11}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_20}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_26}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_49 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_26, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_14}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_50 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_49, cs_decoder_decoded_andMatrixOutputs_lo_lo_40}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_47, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_40}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_50, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_49}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_47 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_21, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_11}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_50, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_50}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_29 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_50, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_50}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_50 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_29, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_17}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_50 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_50, cs_decoder_decoded_andMatrixOutputs_hi_lo_47}; // @[pla.scala:98:53]
wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_50 = {cs_decoder_decoded_andMatrixOutputs_hi_50, cs_decoder_decoded_andMatrixOutputs_lo_50}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_82_2 = &_cs_decoder_decoded_andMatrixOutputs_T_50; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_7}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_15}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_41 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_21, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_7}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_21}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_27}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_50 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_27, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_15}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_51 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_50, cs_decoder_decoded_andMatrixOutputs_lo_lo_41}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_41}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_51, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_50}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_48 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_22, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_12}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_51, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_51}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_30 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_51, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_51}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_51 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_30, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_18}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_51 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_51, cs_decoder_decoded_andMatrixOutputs_hi_lo_48}; // @[pla.scala:98:53]
wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_51 = {cs_decoder_decoded_andMatrixOutputs_hi_51, cs_decoder_decoded_andMatrixOutputs_lo_51}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_26_2 = &_cs_decoder_decoded_andMatrixOutputs_T_51; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_8}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_16}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_42 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_22, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_8}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_16 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_22}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_28}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_51 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_28, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_16}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_52 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_51, cs_decoder_decoded_andMatrixOutputs_lo_lo_42}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_49, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_42}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_52, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_51}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_49 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_23, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_13}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_52, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_52}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_31 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_52, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_52}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_52 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_31, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_19}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_52 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_52, cs_decoder_decoded_andMatrixOutputs_hi_lo_49}; // @[pla.scala:98:53]
wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_52 = {cs_decoder_decoded_andMatrixOutputs_hi_52, cs_decoder_decoded_andMatrixOutputs_lo_52}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_42_2 = &_cs_decoder_decoded_andMatrixOutputs_T_52; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_17}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_43 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_14}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_23}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_29 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_29}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_52 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_29, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_17}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_53 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_52, cs_decoder_decoded_andMatrixOutputs_lo_lo_43}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_50, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_43}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_53, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_52}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_50 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_24, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_14}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_53, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_53}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_32 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_53, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_53}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_53 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_32, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_20}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_53 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_53, cs_decoder_decoded_andMatrixOutputs_hi_lo_50}; // @[pla.scala:98:53]
wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_53 = {cs_decoder_decoded_andMatrixOutputs_hi_53, cs_decoder_decoded_andMatrixOutputs_lo_53}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_41_2 = &_cs_decoder_decoded_andMatrixOutputs_T_53; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_9}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_18}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_44 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_24, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_9}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_24}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_30 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_33, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_30}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_53 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_30, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_18}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_54 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_53, cs_decoder_decoded_andMatrixOutputs_lo_lo_44}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_51, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_44}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_54, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_53}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_51 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_25, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_15}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_54, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_54}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_33 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_54, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_54}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_54 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_33, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_21}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_54 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_54, cs_decoder_decoded_andMatrixOutputs_hi_lo_51}; // @[pla.scala:98:53]
wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_54 = {cs_decoder_decoded_andMatrixOutputs_hi_54, cs_decoder_decoded_andMatrixOutputs_lo_54}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_93_2 = &_cs_decoder_decoded_andMatrixOutputs_T_54; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_45 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_52, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_45}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_54 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_54}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_55 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_54, cs_decoder_decoded_andMatrixOutputs_lo_lo_45}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_52 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_55}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_55 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_55}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_55 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_55, cs_decoder_decoded_andMatrixOutputs_hi_lo_52}; // @[pla.scala:98:53]
wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_55 = {cs_decoder_decoded_andMatrixOutputs_hi_55, cs_decoder_decoded_andMatrixOutputs_lo_55}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_70_2 = &_cs_decoder_decoded_andMatrixOutputs_T_55; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_46 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_46, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_34}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_55 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_53}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_56 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_55, cs_decoder_decoded_andMatrixOutputs_lo_lo_46}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_53 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_56}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_34 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_56}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_56 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_34, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_56}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_56 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_56, cs_decoder_decoded_andMatrixOutputs_hi_lo_53}; // @[pla.scala:98:53]
wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_56 = {cs_decoder_decoded_andMatrixOutputs_hi_56, cs_decoder_decoded_andMatrixOutputs_lo_56}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_11_2 = &_cs_decoder_decoded_andMatrixOutputs_T_56; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_47 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_31}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_31 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_54}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_56 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_47}; // @[pla.scala:90:45, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_57 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_56, cs_decoder_decoded_andMatrixOutputs_lo_lo_47}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_54 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_57, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_57}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_35 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_57, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_57}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_57 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_57}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_57 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_57, cs_decoder_decoded_andMatrixOutputs_hi_lo_54}; // @[pla.scala:98:53]
wire [9:0] _cs_decoder_decoded_andMatrixOutputs_T_57 = {cs_decoder_decoded_andMatrixOutputs_hi_57, cs_decoder_decoded_andMatrixOutputs_lo_57}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_76_2 = &_cs_decoder_decoded_andMatrixOutputs_T_57; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_48 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_48}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_57 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_58, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_57}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_58 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_57, cs_decoder_decoded_andMatrixOutputs_lo_lo_48}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_55 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_58, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_58}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_58 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_58, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_58}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_58 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_58, cs_decoder_decoded_andMatrixOutputs_hi_lo_55}; // @[pla.scala:98:53]
wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_58 = {cs_decoder_decoded_andMatrixOutputs_hi_58, cs_decoder_decoded_andMatrixOutputs_lo_58}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_167_2 = &_cs_decoder_decoded_andMatrixOutputs_T_58; // @[pla.scala:98:{53,70}]
wire _cs_decoder_decoded_orMatrixOutputs_T = cs_decoder_decoded_andMatrixOutputs_167_2; // @[pla.scala:98:70, :114:36]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_49 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_32}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_32 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_58, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_56}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_58 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_49}; // @[pla.scala:90:45, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_59 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_58, cs_decoder_decoded_andMatrixOutputs_lo_lo_49}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_56 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_59, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_59}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_36 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_59, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_59}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_59 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_59}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_59 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_59, cs_decoder_decoded_andMatrixOutputs_hi_lo_56}; // @[pla.scala:98:53]
wire [9:0] _cs_decoder_decoded_andMatrixOutputs_T_59 = {cs_decoder_decoded_andMatrixOutputs_hi_59, cs_decoder_decoded_andMatrixOutputs_lo_59}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_152_2 = &_cs_decoder_decoded_andMatrixOutputs_T_59; // @[pla.scala:98:{53,70}]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_50 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_60 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_59 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_60 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_53 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_54 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_55 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_56 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_65 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_58 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_59 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_60 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_43 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_62 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_44 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_45 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_46 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_47 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_82 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_83 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_84 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_92 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_73 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_100 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_81 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_103 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_109 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_120 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_129 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_136 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_146 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_50 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_57, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_50}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_59 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_59}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_60 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_59, cs_decoder_decoded_andMatrixOutputs_lo_lo_50}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_57 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_60}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_60 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_60}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_60 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_60, cs_decoder_decoded_andMatrixOutputs_hi_lo_57}; // @[pla.scala:98:53]
wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_60 = {cs_decoder_decoded_andMatrixOutputs_hi_60, cs_decoder_decoded_andMatrixOutputs_lo_60}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_96_2 = &_cs_decoder_decoded_andMatrixOutputs_T_60; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_60 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_61, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_60}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_61 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_58}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_58 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_61, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_61}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_61 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_61, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_61}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_61 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_61, cs_decoder_decoded_andMatrixOutputs_hi_lo_58}; // @[pla.scala:98:53]
wire [6:0] _cs_decoder_decoded_andMatrixOutputs_T_61 = {cs_decoder_decoded_andMatrixOutputs_hi_61, cs_decoder_decoded_andMatrixOutputs_lo_61}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_125_2 = &_cs_decoder_decoded_andMatrixOutputs_T_61; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_51 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_59, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_51}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_61 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_62, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_61}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_62 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_61, cs_decoder_decoded_andMatrixOutputs_lo_lo_51}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_59 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_62, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_62}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_62 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_62, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_62}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_62 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_62, cs_decoder_decoded_andMatrixOutputs_hi_lo_59}; // @[pla.scala:98:53]
wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_62 = {cs_decoder_decoded_andMatrixOutputs_hi_62, cs_decoder_decoded_andMatrixOutputs_lo_62}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_40_2 = &_cs_decoder_decoded_andMatrixOutputs_T_62; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_52 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_52}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_62 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_62}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_63 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_62, cs_decoder_decoded_andMatrixOutputs_lo_lo_52}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_60 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_63}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_63 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_63}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_63 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_63, cs_decoder_decoded_andMatrixOutputs_hi_lo_60}; // @[pla.scala:98:53]
wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_63 = {cs_decoder_decoded_andMatrixOutputs_hi_63, cs_decoder_decoded_andMatrixOutputs_lo_63}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_169_2 = &_cs_decoder_decoded_andMatrixOutputs_T_63; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_53 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_53, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_37}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_63 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_61}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_64 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_63, cs_decoder_decoded_andMatrixOutputs_lo_lo_53}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_61 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_64, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_64}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_37 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_64, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_64}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_64 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_64}; // @[pla.scala:90:45, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_64 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_64, cs_decoder_decoded_andMatrixOutputs_hi_lo_61}; // @[pla.scala:98:53]
wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_64 = {cs_decoder_decoded_andMatrixOutputs_hi_64, cs_decoder_decoded_andMatrixOutputs_lo_64}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_69_2 = &_cs_decoder_decoded_andMatrixOutputs_T_64; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_54 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_54, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_38}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_64 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_64, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_62}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_65 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_64, cs_decoder_decoded_andMatrixOutputs_lo_lo_54}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_62 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_65, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_65}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_38 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_65, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_65}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_65 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_38, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_65}; // @[pla.scala:90:45, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_65 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_65, cs_decoder_decoded_andMatrixOutputs_hi_lo_62}; // @[pla.scala:98:53]
wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_65 = {cs_decoder_decoded_andMatrixOutputs_hi_65, cs_decoder_decoded_andMatrixOutputs_lo_65}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_3_2 = &_cs_decoder_decoded_andMatrixOutputs_T_65; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_55 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_55}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_65 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_65}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_66 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_65, cs_decoder_decoded_andMatrixOutputs_lo_lo_55}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_63 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_66}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_66 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_66}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_66 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_66, cs_decoder_decoded_andMatrixOutputs_hi_lo_63}; // @[pla.scala:98:53]
wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_66 = {cs_decoder_decoded_andMatrixOutputs_hi_66, cs_decoder_decoded_andMatrixOutputs_lo_66}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_16_2 = &_cs_decoder_decoded_andMatrixOutputs_T_66; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_56 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_39}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_66 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_64}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_67 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_66, cs_decoder_decoded_andMatrixOutputs_lo_lo_56}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_64 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_67, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_67}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_39 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_67, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_67}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_67 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_67}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_67 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_67, cs_decoder_decoded_andMatrixOutputs_hi_lo_64}; // @[pla.scala:98:53]
wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_67 = {cs_decoder_decoded_andMatrixOutputs_hi_67, cs_decoder_decoded_andMatrixOutputs_lo_67}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_112_2 = &_cs_decoder_decoded_andMatrixOutputs_T_67; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_57 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_65, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_57}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_67 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_68, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_67}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_68 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_67, cs_decoder_decoded_andMatrixOutputs_lo_lo_57}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_65 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_68, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_68}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_68 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_68, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_68}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_68 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_68, cs_decoder_decoded_andMatrixOutputs_hi_lo_65}; // @[pla.scala:98:53]
wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_68 = {cs_decoder_decoded_andMatrixOutputs_hi_68, cs_decoder_decoded_andMatrixOutputs_lo_68}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_160_2 = &_cs_decoder_decoded_andMatrixOutputs_T_68; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_58 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_58, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_40}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_68 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_68, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_66}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_69 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_68, cs_decoder_decoded_andMatrixOutputs_lo_lo_58}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_66 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_69, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_69}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_40 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_69, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_69}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_69 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_40, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_69}; // @[pla.scala:90:45, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_69 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_69, cs_decoder_decoded_andMatrixOutputs_hi_lo_66}; // @[pla.scala:98:53]
wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_69 = {cs_decoder_decoded_andMatrixOutputs_hi_69, cs_decoder_decoded_andMatrixOutputs_lo_69}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_101_2 = &_cs_decoder_decoded_andMatrixOutputs_T_69; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_59 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_33, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_26}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_33 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_67, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_59}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_69 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_33, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_41}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_70 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_69, cs_decoder_decoded_andMatrixOutputs_lo_lo_59}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_70, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_70}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_67 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_69}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_41 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_70, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_70}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_70 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_70}; // @[pla.scala:90:45, :98:53]
wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_70 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_70, cs_decoder_decoded_andMatrixOutputs_hi_lo_67}; // @[pla.scala:98:53]
wire [10:0] _cs_decoder_decoded_andMatrixOutputs_T_70 = {cs_decoder_decoded_andMatrixOutputs_hi_70, cs_decoder_decoded_andMatrixOutputs_lo_70}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_15_2 = &_cs_decoder_decoded_andMatrixOutputs_T_70; // @[pla.scala:98:{53,70}]
wire _cs_decoder_decoded_orMatrixOutputs_T_23 = cs_decoder_decoded_andMatrixOutputs_15_2; // @[pla.scala:98:70, :114:36]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_22}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_60 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_19}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_34, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_27}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_34 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_42}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_70 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_34, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_19}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_71 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_70, cs_decoder_decoded_andMatrixOutputs_lo_lo_60}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_71, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_70}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_68 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_68}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_71, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_71}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_42 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_71, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_71}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_71 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_42, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_22}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_71 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_71, cs_decoder_decoded_andMatrixOutputs_hi_lo_68}; // @[pla.scala:98:53]
wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_71 = {cs_decoder_decoded_andMatrixOutputs_hi_71, cs_decoder_decoded_andMatrixOutputs_lo_71}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_23_2 = &_cs_decoder_decoded_andMatrixOutputs_T_71; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_10}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_20}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_61 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_26, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_10}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_26}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_35 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_43, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_35}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_71 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_35, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_20}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_72 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_71, cs_decoder_decoded_andMatrixOutputs_lo_lo_61}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_16 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_69, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_61}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_72, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_71}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_69 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_28, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_16}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_72, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_72}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_43 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_72, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_72}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_72 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_43, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_23}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_72 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_72, cs_decoder_decoded_andMatrixOutputs_hi_lo_69}; // @[pla.scala:98:53]
wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_72 = {cs_decoder_decoded_andMatrixOutputs_hi_72, cs_decoder_decoded_andMatrixOutputs_lo_72}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_173_2 = &_cs_decoder_decoded_andMatrixOutputs_T_72; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_62 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_70, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_62}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_72 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_73, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_72}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_73 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_72, cs_decoder_decoded_andMatrixOutputs_lo_lo_62}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_70 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_73, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_73}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_73 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_73, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_73}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_73 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_73, cs_decoder_decoded_andMatrixOutputs_hi_lo_70}; // @[pla.scala:98:53]
wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_73 = {cs_decoder_decoded_andMatrixOutputs_hi_73, cs_decoder_decoded_andMatrixOutputs_lo_73}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_137_2 = &_cs_decoder_decoded_andMatrixOutputs_T_73; // @[pla.scala:98:{53,70}]
wire _cs_decoder_decoded_orMatrixOutputs_T_1 = cs_decoder_decoded_andMatrixOutputs_137_2; // @[pla.scala:98:70, :114:36]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_63 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_44}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_73 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_73, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_71}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_74 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_73, cs_decoder_decoded_andMatrixOutputs_lo_lo_63}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_71 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_74, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_74}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_44 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_74, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_74}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_74 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_44, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_74}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_74 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_74, cs_decoder_decoded_andMatrixOutputs_hi_lo_71}; // @[pla.scala:98:53]
wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_74 = {cs_decoder_decoded_andMatrixOutputs_hi_74, cs_decoder_decoded_andMatrixOutputs_lo_74}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_20_2 = &_cs_decoder_decoded_andMatrixOutputs_T_74; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_64 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_36}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_36 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_74, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_72}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_74 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_64}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_75 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_74, cs_decoder_decoded_andMatrixOutputs_lo_lo_64}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_72 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_75, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_75}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_45 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_75, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_75}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_75 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_75}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_75 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_75, cs_decoder_decoded_andMatrixOutputs_hi_lo_72}; // @[pla.scala:98:53]
wire [9:0] _cs_decoder_decoded_andMatrixOutputs_T_75 = {cs_decoder_decoded_andMatrixOutputs_hi_75, cs_decoder_decoded_andMatrixOutputs_lo_75}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_54_2 = &_cs_decoder_decoded_andMatrixOutputs_T_75; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_65 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_65, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_46}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_75 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_75, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_73}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_76 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_75, cs_decoder_decoded_andMatrixOutputs_lo_lo_65}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_73 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_76}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_46 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_76}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_76 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_46, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_76}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_76 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_76, cs_decoder_decoded_andMatrixOutputs_hi_lo_73}; // @[pla.scala:98:53]
wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_76 = {cs_decoder_decoded_andMatrixOutputs_hi_76, cs_decoder_decoded_andMatrixOutputs_lo_76}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_97_2 = &_cs_decoder_decoded_andMatrixOutputs_T_76; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_66 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_47}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_76 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_74}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_77 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_76, cs_decoder_decoded_andMatrixOutputs_lo_lo_66}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_74 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_77, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_77}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_47 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_77, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_77}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_77 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_47, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_77}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_77 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_77, cs_decoder_decoded_andMatrixOutputs_hi_lo_74}; // @[pla.scala:98:53]
wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_77 = {cs_decoder_decoded_andMatrixOutputs_hi_77, cs_decoder_decoded_andMatrixOutputs_lo_77}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_157_2 = &_cs_decoder_decoded_andMatrixOutputs_T_77; // @[pla.scala:98:{53,70}]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_37 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_68 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_50 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_70 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_51 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_40 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_53 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_42 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_55 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_44 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_57 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_58 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_47 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_60 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_61 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_62 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_63 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_64 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_103 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_95 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_96 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_97 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_78 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_79 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_80 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_63 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_67 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_37}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_37 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_77, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_75}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_77 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_67}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_78 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_77, cs_decoder_decoded_andMatrixOutputs_lo_lo_67}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_75 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_78}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_48 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_78}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_78 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_78}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_78 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_78, cs_decoder_decoded_andMatrixOutputs_hi_lo_75}; // @[pla.scala:98:53]
wire [9:0] _cs_decoder_decoded_andMatrixOutputs_T_78 = {cs_decoder_decoded_andMatrixOutputs_hi_78, cs_decoder_decoded_andMatrixOutputs_lo_78}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_145_2 = &_cs_decoder_decoded_andMatrixOutputs_T_78; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_24}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_68 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_21}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_38, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_29}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_38 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_68, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_49}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_78 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_38, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_21}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_79 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_78, cs_decoder_decoded_andMatrixOutputs_lo_lo_68}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_29 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_79, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_78}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_76 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_76}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_79, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_79}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_49 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_79, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_79}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_79 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_49, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_24}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_79 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_79, cs_decoder_decoded_andMatrixOutputs_hi_lo_76}; // @[pla.scala:98:53]
wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_79 = {cs_decoder_decoded_andMatrixOutputs_hi_79, cs_decoder_decoded_andMatrixOutputs_lo_79}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_134_2 = &_cs_decoder_decoded_andMatrixOutputs_T_79; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_11}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_22}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_69 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_28, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_11}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_28}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_39 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_50, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_39}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_79 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_39, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_22}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_80 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_79, cs_decoder_decoded_andMatrixOutputs_lo_lo_69}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_77, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_69}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_30 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_79}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_77 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_30, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_17}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_80}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_50 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_80}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_80 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_50, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_25}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_80 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_80, cs_decoder_decoded_andMatrixOutputs_hi_lo_77}; // @[pla.scala:98:53]
wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_80 = {cs_decoder_decoded_andMatrixOutputs_hi_80, cs_decoder_decoded_andMatrixOutputs_lo_80}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_128_2 = &_cs_decoder_decoded_andMatrixOutputs_T_80; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_70 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_70}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_80 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_81, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_80}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_81 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_80, cs_decoder_decoded_andMatrixOutputs_lo_lo_70}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_78 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_81, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_81}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_81 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_81, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_81}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_81 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_81, cs_decoder_decoded_andMatrixOutputs_hi_lo_78}; // @[pla.scala:98:53]
wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_81 = {cs_decoder_decoded_andMatrixOutputs_hi_81, cs_decoder_decoded_andMatrixOutputs_lo_81}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_142_2 = &_cs_decoder_decoded_andMatrixOutputs_T_81; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_71 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_71, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_51}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_81 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_81, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_79}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_82 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_81, cs_decoder_decoded_andMatrixOutputs_lo_lo_71}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_79 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_82, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_82}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_51 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_82, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_82}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_82 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_51, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_82}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_82 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_82, cs_decoder_decoded_andMatrixOutputs_hi_lo_79}; // @[pla.scala:98:53]
wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_82 = {cs_decoder_decoded_andMatrixOutputs_hi_82, cs_decoder_decoded_andMatrixOutputs_lo_82}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_117_2 = &_cs_decoder_decoded_andMatrixOutputs_T_82; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_29 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_23}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_72 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_18}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_29}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_40 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_52, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_40}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_82 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_40, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_23}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_83 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_82, cs_decoder_decoded_andMatrixOutputs_lo_lo_72}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_72}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_31 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_83, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_82}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_80 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_31, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_18}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_83, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_83}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_52 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_83, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_83}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_83 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_52, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_26}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_83 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_83, cs_decoder_decoded_andMatrixOutputs_hi_lo_80}; // @[pla.scala:98:53]
wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_83 = {cs_decoder_decoded_andMatrixOutputs_hi_83, cs_decoder_decoded_andMatrixOutputs_lo_83}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_53_2 = &_cs_decoder_decoded_andMatrixOutputs_T_83; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_30 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_24}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_73 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_19}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_30}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_41 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_53, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_41}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_83 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_41, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_24}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_84 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_83, cs_decoder_decoded_andMatrixOutputs_lo_lo_73}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_81, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_73}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_32 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_84, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_83}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_81 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_32, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_19}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_84, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_84}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_53 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_84, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_84}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_84 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_53, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_27}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_84 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_84, cs_decoder_decoded_andMatrixOutputs_hi_lo_81}; // @[pla.scala:98:53]
wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_84 = {cs_decoder_decoded_andMatrixOutputs_hi_84, cs_decoder_decoded_andMatrixOutputs_lo_84}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_166_2 = &_cs_decoder_decoded_andMatrixOutputs_T_84; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_12}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_31 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_25}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_74 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_31, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_12}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_33, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_31}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_42 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_54, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_42}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_84 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_42, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_25}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_85 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_84, cs_decoder_decoded_andMatrixOutputs_lo_lo_74}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_82, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_74}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_33 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_85, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_84}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_82 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_33, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_20}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_85, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_85}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_54 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_85, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_85}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_85 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_54, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_28}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_85 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_85, cs_decoder_decoded_andMatrixOutputs_hi_lo_82}; // @[pla.scala:98:53]
wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_85 = {cs_decoder_decoded_andMatrixOutputs_hi_85, cs_decoder_decoded_andMatrixOutputs_lo_85}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_21_2 = &_cs_decoder_decoded_andMatrixOutputs_T_85; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_32 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_26}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_75 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_21}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_34, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_32}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_43 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_43}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_85 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_43, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_26}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_86 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_85, cs_decoder_decoded_andMatrixOutputs_lo_lo_75}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_83, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_75}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_34 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_86, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_85}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_83 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_34, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_21}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_29 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_86, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_86}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_55 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_86, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_86}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_86 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_55, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_29}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_86 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_86, cs_decoder_decoded_andMatrixOutputs_hi_lo_83}; // @[pla.scala:98:53]
wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_86 = {cs_decoder_decoded_andMatrixOutputs_hi_86, cs_decoder_decoded_andMatrixOutputs_lo_86}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_65_2 = &_cs_decoder_decoded_andMatrixOutputs_T_86; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_13}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_33 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_27}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_76 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_33, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_13}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_33}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_44 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_44}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_86 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_44, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_27}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_87 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_86, cs_decoder_decoded_andMatrixOutputs_lo_lo_76}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_84, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_76}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_35 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_87, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_86}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_84 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_35, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_22}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_30 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_87, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_87}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_56 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_87, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_87}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_87 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_56, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_30}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_87 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_87, cs_decoder_decoded_andMatrixOutputs_hi_lo_84}; // @[pla.scala:98:53]
wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_87 = {cs_decoder_decoded_andMatrixOutputs_hi_87, cs_decoder_decoded_andMatrixOutputs_lo_87}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_52_2 = &_cs_decoder_decoded_andMatrixOutputs_T_87; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_34 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_28}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_77 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_34, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_23}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_34}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_45 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_57, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_45}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_87 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_45, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_28}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_88 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_87, cs_decoder_decoded_andMatrixOutputs_lo_lo_77}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_85, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_77}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_36 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_88, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_87}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_85 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_36, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_23}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_31 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_88, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_88}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_57 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_88, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_88}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_88 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_57, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_31}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_88 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_88, cs_decoder_decoded_andMatrixOutputs_hi_lo_85}; // @[pla.scala:98:53]
wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_88 = {cs_decoder_decoded_andMatrixOutputs_hi_88, cs_decoder_decoded_andMatrixOutputs_lo_88}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_57_2 = &_cs_decoder_decoded_andMatrixOutputs_T_88; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_14}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_35 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_29}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_78 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_35, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_14}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_29 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_35}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_46 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_58, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_46}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_88 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_46, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_29}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_89 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_88, cs_decoder_decoded_andMatrixOutputs_lo_lo_78}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_86, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_78}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_37 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_89, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_88}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_86 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_37, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_24}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_32 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_89, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_89}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_58 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_89, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_89}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_89 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_58, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_32}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_89 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_89, cs_decoder_decoded_andMatrixOutputs_hi_lo_86}; // @[pla.scala:98:53]
wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_89 = {cs_decoder_decoded_andMatrixOutputs_hi_89, cs_decoder_decoded_andMatrixOutputs_lo_89}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_74_2 = &_cs_decoder_decoded_andMatrixOutputs_T_89; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_15}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_36 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_33, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_30}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_79 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_36, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_15}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_30 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_38, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_36}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_47 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_59, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_47}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_89 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_47, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_30}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_90 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_89, cs_decoder_decoded_andMatrixOutputs_lo_lo_79}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_87, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_79}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_38 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_90, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_89}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_87 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_38, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_25}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_33 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_90, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_90}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_59 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_90, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_90}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_90 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_59, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_33}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_90 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_90, cs_decoder_decoded_andMatrixOutputs_hi_lo_87}; // @[pla.scala:98:53]
wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_90 = {cs_decoder_decoded_andMatrixOutputs_hi_90, cs_decoder_decoded_andMatrixOutputs_lo_90}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_91_2 = &_cs_decoder_decoded_andMatrixOutputs_T_90; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_80 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_60}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_90 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_90, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_88}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_91 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_90, cs_decoder_decoded_andMatrixOutputs_lo_lo_80}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_88 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_91, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_91}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_60 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_91, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_91}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_91 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_91}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_91 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_91, cs_decoder_decoded_andMatrixOutputs_hi_lo_88}; // @[pla.scala:98:53]
wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_91 = {cs_decoder_decoded_andMatrixOutputs_hi_91, cs_decoder_decoded_andMatrixOutputs_lo_91}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_104_2 = &_cs_decoder_decoded_andMatrixOutputs_T_91; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_81 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_81, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_61}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_91 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_91, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_89}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_92 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_91, cs_decoder_decoded_andMatrixOutputs_lo_lo_81}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_89 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_92, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_92}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_61 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_92, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_92}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_92 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_61, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_92}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_92 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_92, cs_decoder_decoded_andMatrixOutputs_hi_lo_89}; // @[pla.scala:98:53]
wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_92 = {cs_decoder_decoded_andMatrixOutputs_hi_92, cs_decoder_decoded_andMatrixOutputs_lo_92}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_68_2 = &_cs_decoder_decoded_andMatrixOutputs_T_92; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_82 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_82, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_62}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_92 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_92, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_90}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_93 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_92, cs_decoder_decoded_andMatrixOutputs_lo_lo_82}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_90 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_93, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_93}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_62 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_93, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_93}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_93 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_62, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_93}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_93 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_93, cs_decoder_decoded_andMatrixOutputs_hi_lo_90}; // @[pla.scala:98:53]
wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_93 = {cs_decoder_decoded_andMatrixOutputs_hi_93, cs_decoder_decoded_andMatrixOutputs_lo_93}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_94_2 = &_cs_decoder_decoded_andMatrixOutputs_T_93; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_83 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_83, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_63}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_93 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_93, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_91}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_94 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_93, cs_decoder_decoded_andMatrixOutputs_lo_lo_83}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_91 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_94, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_94}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_63 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_94, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_94}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_94 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_94}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_94 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_94, cs_decoder_decoded_andMatrixOutputs_hi_lo_91}; // @[pla.scala:98:53]
wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_94 = {cs_decoder_decoded_andMatrixOutputs_hi_94, cs_decoder_decoded_andMatrixOutputs_lo_94}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_151_2 = &_cs_decoder_decoded_andMatrixOutputs_T_94; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_84 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_84, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_64}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_94 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_94, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_92}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_95 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_94, cs_decoder_decoded_andMatrixOutputs_lo_lo_84}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_92 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_95, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_95}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_64 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_95, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_95}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_95 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_64, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_95}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_95 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_95, cs_decoder_decoded_andMatrixOutputs_hi_lo_92}; // @[pla.scala:98:53]
wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_95 = {cs_decoder_decoded_andMatrixOutputs_hi_95, cs_decoder_decoded_andMatrixOutputs_lo_95}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_2_2 = &_cs_decoder_decoded_andMatrixOutputs_T_95; // @[pla.scala:98:{53,70}]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_85 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_66 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_67 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_51 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_99 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_89 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_90 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_44 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_54 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_55 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_94 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_75 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_76 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_77 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_60 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_61 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_62 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_54 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_104 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_105 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_114 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_68 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_64 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_55 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_33 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_92 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_93 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_94 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_85 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_86 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_89 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_7 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_7 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_106 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_55 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_83 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_37 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_34}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_85 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_31}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_31 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_39}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_48 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_85, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_65}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_95 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_48, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_31}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_96 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_95, cs_decoder_decoded_andMatrixOutputs_lo_lo_85}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_39 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_96, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_95}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_93 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_93}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_34 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_96, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_96}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_65 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_96, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_96}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_96 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_65, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_34}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_96 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_96, cs_decoder_decoded_andMatrixOutputs_hi_lo_93}; // @[pla.scala:98:53]
wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_96 = {cs_decoder_decoded_andMatrixOutputs_hi_96, cs_decoder_decoded_andMatrixOutputs_lo_96}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_156_2 = &_cs_decoder_decoded_andMatrixOutputs_T_96; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_38 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_32}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_86 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_38, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_26}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_32 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_40, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_38}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_49 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_49}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_96 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_49, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_32}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_97 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_96, cs_decoder_decoded_andMatrixOutputs_lo_lo_86}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_94, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_86}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_40 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_97, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_96}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_94 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_40, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_26}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_35 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_97, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_97}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_66 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_97, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_97}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_97 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_66, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_35}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_97 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_97, cs_decoder_decoded_andMatrixOutputs_hi_lo_94}; // @[pla.scala:98:53]
wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_97 = {cs_decoder_decoded_andMatrixOutputs_hi_97, cs_decoder_decoded_andMatrixOutputs_lo_97}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_154_2 = &_cs_decoder_decoded_andMatrixOutputs_T_97; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_39 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_33}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_87 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_27}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_33 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_39}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_50 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_67, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_50}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_97 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_50, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_33}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_98 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_97, cs_decoder_decoded_andMatrixOutputs_lo_lo_87}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_95, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_87}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_41 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_98, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_97}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_95 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_41, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_27}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_36 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_98, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_98}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_67 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_98, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_98}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_98 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_67, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_36}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_98 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_98, cs_decoder_decoded_andMatrixOutputs_hi_lo_95}; // @[pla.scala:98:53]
wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_98 = {cs_decoder_decoded_andMatrixOutputs_hi_98, cs_decoder_decoded_andMatrixOutputs_lo_98}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_148_2 = &_cs_decoder_decoded_andMatrixOutputs_T_98; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_16 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_16}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_40 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_34}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_88 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_40, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_16}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_34 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_42, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_40}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_51 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_68, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_51}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_98 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_51, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_34}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_99 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_98, cs_decoder_decoded_andMatrixOutputs_lo_lo_88}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_96, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_88}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_42 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_99, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_98}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_96 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_42, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_28}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_37 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_99, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_99}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_68 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_99, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_99}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_99 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_68, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_37}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_99 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_99, cs_decoder_decoded_andMatrixOutputs_hi_lo_96}; // @[pla.scala:98:53]
wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_99 = {cs_decoder_decoded_andMatrixOutputs_hi_99, cs_decoder_decoded_andMatrixOutputs_lo_99}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_89_2 = &_cs_decoder_decoded_andMatrixOutputs_T_99; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_99 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_100, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_99}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_100 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_99, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_97}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_97 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_100, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_100}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_100 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_100, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_100}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_100 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_100, cs_decoder_decoded_andMatrixOutputs_hi_lo_97}; // @[pla.scala:98:53]
wire [6:0] _cs_decoder_decoded_andMatrixOutputs_T_100 = {cs_decoder_decoded_andMatrixOutputs_hi_100, cs_decoder_decoded_andMatrixOutputs_lo_100}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_55_2 = &_cs_decoder_decoded_andMatrixOutputs_T_100; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_89 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_89, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_69}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_100 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_100, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_98}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_101 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_100, cs_decoder_decoded_andMatrixOutputs_lo_lo_89}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_98 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_101, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_101}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_69 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_101, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_101}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_101 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_69, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_101}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_101 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_101, cs_decoder_decoded_andMatrixOutputs_hi_lo_98}; // @[pla.scala:98:53]
wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_101 = {cs_decoder_decoded_andMatrixOutputs_hi_101, cs_decoder_decoded_andMatrixOutputs_lo_101}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_116_2 = &_cs_decoder_decoded_andMatrixOutputs_T_101; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_41 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_43, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_41}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_90 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_38}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_52 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_90, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_70}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_101 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_52, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_52}; // @[pla.scala:91:29, :98:53]
wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_102 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_101, cs_decoder_decoded_andMatrixOutputs_lo_lo_90}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_43 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_102, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_101}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_99 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_43, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_99}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_38 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_102, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_102}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_70 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_102, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_102}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_102 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_70, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_38}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_102 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_102, cs_decoder_decoded_andMatrixOutputs_hi_lo_99}; // @[pla.scala:98:53]
wire [12:0] _cs_decoder_decoded_andMatrixOutputs_T_102 = {cs_decoder_decoded_andMatrixOutputs_hi_102, cs_decoder_decoded_andMatrixOutputs_lo_102}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_131_2 = &_cs_decoder_decoded_andMatrixOutputs_T_102; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_2}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_42 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_29}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_91 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_42, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_17}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_35 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_42, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_39}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_53 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_53, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_44}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_102 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_53, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_35}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_103 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_102, cs_decoder_decoded_andMatrixOutputs_lo_lo_91}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_29 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_91, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_71}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_44 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_102, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_100}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_100 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_44, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_29}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_39 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_103, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_103}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_103, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_103}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_71 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_103}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_103 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_71, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_39}; // @[pla.scala:98:53]
wire [8:0] cs_decoder_decoded_andMatrixOutputs_hi_103 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_103, cs_decoder_decoded_andMatrixOutputs_hi_lo_100}; // @[pla.scala:98:53]
wire [16:0] _cs_decoder_decoded_andMatrixOutputs_T_103 = {cs_decoder_decoded_andMatrixOutputs_hi_103, cs_decoder_decoded_andMatrixOutputs_lo_103}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_172_2 = &_cs_decoder_decoded_andMatrixOutputs_T_103; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_18}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_43 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_40, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_36}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_92 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_43, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_18}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_36 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_43}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_54 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_72, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_54}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_103 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_54, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_36}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_104 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_103, cs_decoder_decoded_andMatrixOutputs_lo_lo_92}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_30 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_101, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_92}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_45 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_104, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_103}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_101 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_45, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_30}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_40 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_104, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_104}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_72 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_104, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_104}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_104 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_72, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_40}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_104 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_104, cs_decoder_decoded_andMatrixOutputs_hi_lo_101}; // @[pla.scala:98:53]
wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_104 = {cs_decoder_decoded_andMatrixOutputs_hi_104, cs_decoder_decoded_andMatrixOutputs_lo_104}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_72_2 = &_cs_decoder_decoded_andMatrixOutputs_T_104; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_19}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_44 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_37}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_93 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_44, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_19}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_37 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_46, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_44}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_55 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_73, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_55}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_104 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_55, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_37}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_105 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_104, cs_decoder_decoded_andMatrixOutputs_lo_lo_93}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_31 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_102, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_93}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_46 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_105, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_104}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_102 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_46, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_31}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_41 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_105, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_105}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_73 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_105, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_105}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_105 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_73, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_41}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_105 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_105, cs_decoder_decoded_andMatrixOutputs_hi_lo_102}; // @[pla.scala:98:53]
wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_105 = {cs_decoder_decoded_andMatrixOutputs_hi_105, cs_decoder_decoded_andMatrixOutputs_lo_105}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_81_2 = &_cs_decoder_decoded_andMatrixOutputs_T_105; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_45 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_42}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_94 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_38}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_38 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_47}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_56 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_94, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_74}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_105 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_56, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_38}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_106 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_105, cs_decoder_decoded_andMatrixOutputs_lo_lo_94}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_47 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_106, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_105}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_103 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_47, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_103}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_42 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_106, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_106}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_74 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_106, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_106}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_106 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_74, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_42}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_106 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_106, cs_decoder_decoded_andMatrixOutputs_hi_lo_103}; // @[pla.scala:98:53]
wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_106 = {cs_decoder_decoded_andMatrixOutputs_hi_106, cs_decoder_decoded_andMatrixOutputs_lo_106}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_6_2 = &_cs_decoder_decoded_andMatrixOutputs_T_106; // @[pla.scala:98:{53,70}]
wire _cs_decoder_decoded_orMatrixOutputs_T_59 = cs_decoder_decoded_andMatrixOutputs_6_2; // @[pla.scala:98:70, :114:36]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_46 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_43, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_39}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_95 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_46, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_32}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_39 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_46}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_57 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_75, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_57}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_106 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_57, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_39}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_107 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_106, cs_decoder_decoded_andMatrixOutputs_lo_lo_95}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_32 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_104, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_95}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_48 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_107, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_106}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_104 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_48, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_32}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_43 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_107, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_107}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_75 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_107, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_107}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_107 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_75, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_43}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_107 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_107, cs_decoder_decoded_andMatrixOutputs_hi_lo_104}; // @[pla.scala:98:53]
wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_107 = {cs_decoder_decoded_andMatrixOutputs_hi_107, cs_decoder_decoded_andMatrixOutputs_lo_107}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_143_2 = &_cs_decoder_decoded_andMatrixOutputs_T_107; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_47 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_44, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_40}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_96 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_47, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_33}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_40 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_49, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_47}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_58 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_58}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_107 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_58, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_40}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_108 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_107, cs_decoder_decoded_andMatrixOutputs_lo_lo_96}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_33 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_105, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_96}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_49 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_108, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_107}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_105 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_49, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_33}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_44 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_108, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_108}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_76 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_108, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_108}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_108 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_76, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_44}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_108 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_108, cs_decoder_decoded_andMatrixOutputs_hi_lo_105}; // @[pla.scala:98:53]
wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_108 = {cs_decoder_decoded_andMatrixOutputs_hi_108, cs_decoder_decoded_andMatrixOutputs_lo_108}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_66_2 = &_cs_decoder_decoded_andMatrixOutputs_T_108; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_48 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_41}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_97 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_34}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_41 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_50, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_48}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_59 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_77, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_59}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_108 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_59, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_41}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_109 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_108, cs_decoder_decoded_andMatrixOutputs_lo_lo_97}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_34 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_106, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_97}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_50 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_109, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_108}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_106 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_50, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_34}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_45 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_109, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_109}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_77 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_109, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_109}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_109 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_77, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_45}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_109 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_109, cs_decoder_decoded_andMatrixOutputs_hi_lo_106}; // @[pla.scala:98:53]
wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_109 = {cs_decoder_decoded_andMatrixOutputs_hi_109, cs_decoder_decoded_andMatrixOutputs_lo_109}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_63_2 = &_cs_decoder_decoded_andMatrixOutputs_T_109; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_20}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_49 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_46, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_42}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_98 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_49, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_20}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_42 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_51, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_49}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_60 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_60}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_109 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_60, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_42}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_110 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_109, cs_decoder_decoded_andMatrixOutputs_lo_lo_98}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_35 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_107, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_98}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_51 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_110, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_109}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_107 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_51, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_35}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_46 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_110, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_110}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_78 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_110, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_110}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_110 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_78, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_46}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_110 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_110, cs_decoder_decoded_andMatrixOutputs_hi_lo_107}; // @[pla.scala:98:53]
wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_110 = {cs_decoder_decoded_andMatrixOutputs_hi_110, cs_decoder_decoded_andMatrixOutputs_lo_110}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_161_2 = &_cs_decoder_decoded_andMatrixOutputs_T_110; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_21}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_50 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_47, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_43}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_99 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_50, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_21}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_43 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_52, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_50}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_61 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_79, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_61}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_110 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_61, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_43}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_111 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_110, cs_decoder_decoded_andMatrixOutputs_lo_lo_99}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_36 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_108, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_99}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_52 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_111, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_110}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_108 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_52, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_36}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_47 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_111, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_111}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_79 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_111, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_111}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_111 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_79, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_47}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_111 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_111, cs_decoder_decoded_andMatrixOutputs_hi_lo_108}; // @[pla.scala:98:53]
wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_111 = {cs_decoder_decoded_andMatrixOutputs_hi_111, cs_decoder_decoded_andMatrixOutputs_lo_111}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_132_2 = &_cs_decoder_decoded_andMatrixOutputs_T_111; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_22}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_51 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_44}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_100 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_51, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_22}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_44 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_53, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_51}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_62 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_62}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_111 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_62, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_44}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_112 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_111, cs_decoder_decoded_andMatrixOutputs_lo_lo_100}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_37 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_109, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_100}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_53 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_112, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_111}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_109 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_53, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_37}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_48 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_112, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_112}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_80 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_112, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_112}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_112 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_80, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_48}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_112 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_112, cs_decoder_decoded_andMatrixOutputs_hi_lo_109}; // @[pla.scala:98:53]
wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_112 = {cs_decoder_decoded_andMatrixOutputs_hi_112, cs_decoder_decoded_andMatrixOutputs_lo_112}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_133_2 = &_cs_decoder_decoded_andMatrixOutputs_T_112; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_3}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_52 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_38}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_101 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_52, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_23}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_45 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_52, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_49}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_63 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_54}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_112 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_63, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_45}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_113 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_112, cs_decoder_decoded_andMatrixOutputs_lo_lo_101}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_38 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_101, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_81}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_54 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_112, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_110}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_110 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_54, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_38}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_49 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_113, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_113}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_113, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_113}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_81 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_113}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_113 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_81, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_49}; // @[pla.scala:98:53]
wire [8:0] cs_decoder_decoded_andMatrixOutputs_hi_113 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_113, cs_decoder_decoded_andMatrixOutputs_hi_lo_110}; // @[pla.scala:98:53]
wire [16:0] _cs_decoder_decoded_andMatrixOutputs_T_113 = {cs_decoder_decoded_andMatrixOutputs_hi_113, cs_decoder_decoded_andMatrixOutputs_lo_113}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_147_2 = &_cs_decoder_decoded_andMatrixOutputs_T_113; // @[pla.scala:98:{53,70}]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_82 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_65 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_66 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_67 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_99 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_82 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_86 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_76 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_65 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_66 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_6 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_7 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_53 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_53}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_102 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_53, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_50}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_64 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_102, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_82}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_113 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_64, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_64}; // @[pla.scala:91:29, :98:53]
wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_114 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_113, cs_decoder_decoded_andMatrixOutputs_lo_lo_102}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_55 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_114, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_113}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_111 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_111}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_50 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_114, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_114}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_82 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_114, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_114}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_114 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_82, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_50}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_114 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_114, cs_decoder_decoded_andMatrixOutputs_hi_lo_111}; // @[pla.scala:98:53]
wire [12:0] _cs_decoder_decoded_andMatrixOutputs_T_114 = {cs_decoder_decoded_andMatrixOutputs_hi_114, cs_decoder_decoded_andMatrixOutputs_lo_114}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_129_2 = &_cs_decoder_decoded_andMatrixOutputs_T_114; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_54 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_54}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_103 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_54, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_51}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_65 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_103, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_83}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_114 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_65, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_65}; // @[pla.scala:90:45, :98:53]
wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_115 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_114, cs_decoder_decoded_andMatrixOutputs_lo_lo_103}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_56 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_115, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_114}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_112 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_112}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_51 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_115, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_115}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_83 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_115, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_115}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_115 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_83, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_51}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_115 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_115, cs_decoder_decoded_andMatrixOutputs_hi_lo_112}; // @[pla.scala:98:53]
wire [12:0] _cs_decoder_decoded_andMatrixOutputs_T_115 = {cs_decoder_decoded_andMatrixOutputs_hi_115, cs_decoder_decoded_andMatrixOutputs_lo_115}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_100_2 = &_cs_decoder_decoded_andMatrixOutputs_T_115; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_55 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_57, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_55}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_104 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_52}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_66 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_104, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_84}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_115 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_66}; // @[pla.scala:90:45, :98:53]
wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_116 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_115, cs_decoder_decoded_andMatrixOutputs_lo_lo_104}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_57 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_116, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_115}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_113 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_57, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_113}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_52 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_116, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_116}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_84 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_116, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_116}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_116 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_84, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_52}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_116 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_116, cs_decoder_decoded_andMatrixOutputs_hi_lo_113}; // @[pla.scala:98:53]
wire [12:0] _cs_decoder_decoded_andMatrixOutputs_T_116 = {cs_decoder_decoded_andMatrixOutputs_hi_116, cs_decoder_decoded_andMatrixOutputs_lo_116}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_119_2 = &_cs_decoder_decoded_andMatrixOutputs_T_116; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_56 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_53}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_105 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_46}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_46 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_67, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_58}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_67 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_105, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_85}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_116 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_67, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_46}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_117 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_116, cs_decoder_decoded_andMatrixOutputs_lo_lo_105}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_58 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_117, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_116}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_114 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_58, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_114}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_53 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_117, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_117}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_85 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_117, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_117}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_117 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_85, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_53}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_117 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_117, cs_decoder_decoded_andMatrixOutputs_hi_lo_114}; // @[pla.scala:98:53]
wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_117 = {cs_decoder_decoded_andMatrixOutputs_hi_117, cs_decoder_decoded_andMatrixOutputs_lo_117}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_150_2 = &_cs_decoder_decoded_andMatrixOutputs_T_117; // @[pla.scala:98:{53,70}]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_106 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_71 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_3 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_3 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_139 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_140 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_141 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_142 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_143 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_23 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_8 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_149 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_108 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_109 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_119 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_120 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_112 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_113 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_123 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_115 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_47 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_69 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_70 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_25 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_2 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_28_1 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_4 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_28_2 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_76 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_53 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_31 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_12 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_9 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_81 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_73 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_64 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_41 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_42 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_6 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_28_3 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_99 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_26 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_4}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_57 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_47, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_39}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_106 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_57, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_24}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_47 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_57, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_54}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_68 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_68, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_59}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_117 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_68, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_47}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_118 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_117, cs_decoder_decoded_andMatrixOutputs_lo_lo_106}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_39 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_106, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_86}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_59 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_117, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_115}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_115 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_59, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_39}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_54 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_118, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_118}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_118, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_118}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_86 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_118}; // @[pla.scala:90:45, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_118 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_86, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_54}; // @[pla.scala:98:53]
wire [8:0] cs_decoder_decoded_andMatrixOutputs_hi_118 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_118, cs_decoder_decoded_andMatrixOutputs_hi_lo_115}; // @[pla.scala:98:53]
wire [16:0] _cs_decoder_decoded_andMatrixOutputs_T_118 = {cs_decoder_decoded_andMatrixOutputs_hi_118, cs_decoder_decoded_andMatrixOutputs_lo_118}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_121_2 = &_cs_decoder_decoded_andMatrixOutputs_T_118; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_58 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_58}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_107 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_58, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_55}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_69 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_107, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_87}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_118 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_69, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_69}; // @[pla.scala:90:45, :98:53]
wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_119 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_118, cs_decoder_decoded_andMatrixOutputs_lo_lo_107}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_60 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_119, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_118}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_116 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_116}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_55 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_119, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_119}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_87 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_119, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_119}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_119 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_87, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_55}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_119 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_119, cs_decoder_decoded_andMatrixOutputs_hi_lo_116}; // @[pla.scala:98:53]
wire [12:0] _cs_decoder_decoded_andMatrixOutputs_T_119 = {cs_decoder_decoded_andMatrixOutputs_hi_119, cs_decoder_decoded_andMatrixOutputs_lo_119}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_158_2 = &_cs_decoder_decoded_andMatrixOutputs_T_119; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_59 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_61, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_59}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_108 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_59, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_56}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_70 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_108, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_88}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_119 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_70, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_70}; // @[pla.scala:90:45, :98:53]
wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_120 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_119, cs_decoder_decoded_andMatrixOutputs_lo_lo_108}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_61 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_120, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_119}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_117 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_61, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_117}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_56 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_120, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_120}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_88 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_120, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_120}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_120 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_88, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_56}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_120 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_120, cs_decoder_decoded_andMatrixOutputs_hi_lo_117}; // @[pla.scala:98:53]
wire [12:0] _cs_decoder_decoded_andMatrixOutputs_T_120 = {cs_decoder_decoded_andMatrixOutputs_hi_120, cs_decoder_decoded_andMatrixOutputs_lo_120}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_49_2 = &_cs_decoder_decoded_andMatrixOutputs_T_120; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_2}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_60 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_5}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_109 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_60, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_25}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_48 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_40}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_62, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_60}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_71 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_57}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_120 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_71, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_48}; // @[pla.scala:98:53]
wire [8:0] cs_decoder_decoded_andMatrixOutputs_lo_121 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_120, cs_decoder_decoded_andMatrixOutputs_lo_lo_109}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_40 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_89, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_71}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_120, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_118}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_62 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_109}; // @[pla.scala:90:45, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_118 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_62, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_40}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_57 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_121, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_121}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_121, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_121}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_89 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_121}; // @[pla.scala:90:45, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_121 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_89, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_57}; // @[pla.scala:98:53]
wire [9:0] cs_decoder_decoded_andMatrixOutputs_hi_121 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_121, cs_decoder_decoded_andMatrixOutputs_hi_lo_118}; // @[pla.scala:98:53]
wire [18:0] _cs_decoder_decoded_andMatrixOutputs_T_121 = {cs_decoder_decoded_andMatrixOutputs_hi_121, cs_decoder_decoded_andMatrixOutputs_lo_121}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_50_2 = &_cs_decoder_decoded_andMatrixOutputs_T_121; // @[pla.scala:98:{53,70}]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_3 = cs_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_3 = cs_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_17 = cs_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_8 = cs_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_2}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_26 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_2}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_2}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_2}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_61 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_2}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_110 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_61, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_26}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_2}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_49 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_2}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_3}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_26}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_72 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_3, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_2}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_121 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_72, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_49}; // @[pla.scala:98:53]
wire [13:0] cs_decoder_decoded_andMatrixOutputs_lo_122 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_121, cs_decoder_decoded_andMatrixOutputs_lo_lo_110}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_61, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_58}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_41 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_49}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_72, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_63}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_110, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_90}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_63 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_3, cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_2}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_119 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_63, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_41}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_122, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_121}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_58 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_119}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_122, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_122}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_122, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_122}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_90 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_2}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_122 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_90, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_58}; // @[pla.scala:98:53]
wire [13:0] cs_decoder_decoded_andMatrixOutputs_hi_122 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_122, cs_decoder_decoded_andMatrixOutputs_hi_lo_119}; // @[pla.scala:98:53]
wire [27:0] _cs_decoder_decoded_andMatrixOutputs_T_122 = {cs_decoder_decoded_andMatrixOutputs_hi_122, cs_decoder_decoded_andMatrixOutputs_lo_122}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_45_2 = &_cs_decoder_decoded_andMatrixOutputs_T_122; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_28_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_29_1}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_27 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_30_1}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_3}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_3}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_62 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_3, cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_3}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_111 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_62, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_27}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_3}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_3}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_50 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_3, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_1}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_3}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_4}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_73 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_4, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_3}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_122 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_73, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_50}; // @[pla.scala:98:53]
wire [14:0] cs_decoder_decoded_andMatrixOutputs_lo_123 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_122, cs_decoder_decoded_andMatrixOutputs_lo_lo_111}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_42, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_27}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_59, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_50}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_42 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_3, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_1}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_64, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_62}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_91, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_73}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_64 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_4, cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_3}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_120 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_64, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_42}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_120, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_111}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_123, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_122}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_59 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_3, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_1}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_123, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_123}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_123, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_123}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_91 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_3}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_123 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_91, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_59}; // @[pla.scala:98:53]
wire [15:0] cs_decoder_decoded_andMatrixOutputs_hi_123 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_123, cs_decoder_decoded_andMatrixOutputs_hi_lo_120}; // @[pla.scala:98:53]
wire [30:0] _cs_decoder_decoded_andMatrixOutputs_T_123 = {cs_decoder_decoded_andMatrixOutputs_hi_123, cs_decoder_decoded_andMatrixOutputs_lo_123}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_135_2 = &_cs_decoder_decoded_andMatrixOutputs_T_123; // @[pla.scala:98:{53,70}]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_8 = cs_decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_5 = cs_decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_137 = cs_decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_138 = cs_decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_5 = cs_decoder_decoded_plaInput[22]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_5 = cs_decoder_decoded_plaInput[22]; // @[pla.scala:77:22, :90:45]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_4}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_28 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_4}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_4}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_4}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_63 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_4, cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_4}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_112 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_63, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_28}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_4}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_51 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_4}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_5}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_43, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_28}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_74 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_5, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_4}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_123 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_74, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_51}; // @[pla.scala:98:53]
wire [13:0] cs_decoder_decoded_andMatrixOutputs_lo_124 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_123, cs_decoder_decoded_andMatrixOutputs_lo_lo_112}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_60}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_43 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_51}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_74, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_65}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_112, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_92}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_65 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_5, cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_4}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_121 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_65, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_43}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_124, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_123}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_60 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_121}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_124, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_124}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_124, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_124}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_92 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_8, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_4}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_124 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_92, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_60}; // @[pla.scala:98:53]
wire [13:0] cs_decoder_decoded_andMatrixOutputs_hi_124 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_124, cs_decoder_decoded_andMatrixOutputs_hi_lo_121}; // @[pla.scala:98:53]
wire [27:0] _cs_decoder_decoded_andMatrixOutputs_T_124 = {cs_decoder_decoded_andMatrixOutputs_hi_124, cs_decoder_decoded_andMatrixOutputs_lo_124}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_140_2 = &_cs_decoder_decoded_andMatrixOutputs_T_124; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_30_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_31}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_28_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_29_2}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_29 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_5, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_lo}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_5}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_5}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_64 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_5, cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_5}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_113 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_64, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_29}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_5}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_5}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_52 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_5, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_2}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_5}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_6}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_75 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_5}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_124 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_75, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_52}; // @[pla.scala:98:53]
wire [15:0] cs_decoder_decoded_andMatrixOutputs_lo_125 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_124, cs_decoder_decoded_andMatrixOutputs_lo_lo_113}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_44, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_29}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_61, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_52}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_44 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_5, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_2}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_64}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_93, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_75}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_66 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_5}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_122 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_66, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_44}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_122, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_113}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_125, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_124}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_61 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_5, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_2}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_125, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_125}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_125, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_125}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_93 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_9, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_5}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_125 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_93, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_61}; // @[pla.scala:98:53]
wire [15:0] cs_decoder_decoded_andMatrixOutputs_hi_125 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_125, cs_decoder_decoded_andMatrixOutputs_hi_lo_122}; // @[pla.scala:98:53]
wire [31:0] _cs_decoder_decoded_andMatrixOutputs_T_125 = {cs_decoder_decoded_andMatrixOutputs_hi_125, cs_decoder_decoded_andMatrixOutputs_lo_125}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_95_2 = &_cs_decoder_decoded_andMatrixOutputs_T_125; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_65 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_67, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_65}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_114 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_65, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_62}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_76 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_114, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_94}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_125 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_76}; // @[pla.scala:90:45, :98:53]
wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_126 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_125, cs_decoder_decoded_andMatrixOutputs_lo_lo_114}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_67 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_126, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_125}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_123 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_67, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_123}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_62 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_126, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_126}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_94 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_126, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_126}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_126 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_94, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_62}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_126 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_126, cs_decoder_decoded_andMatrixOutputs_hi_lo_123}; // @[pla.scala:98:53]
wire [12:0] _cs_decoder_decoded_andMatrixOutputs_T_126 = {cs_decoder_decoded_andMatrixOutputs_hi_126, cs_decoder_decoded_andMatrixOutputs_lo_126}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_115_2 = &_cs_decoder_decoded_andMatrixOutputs_T_126; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_30 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_10}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_66 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_53, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_45}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_115 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_66, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_30}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_53 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_63}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_77 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_77, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_68}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_126 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_77, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_53}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_127 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_126, cs_decoder_decoded_andMatrixOutputs_lo_lo_115}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_45 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_115, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_95}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_68 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_126, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_124}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_124 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_68, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_45}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_63 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_127, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_127}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_127, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_127}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_95 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_127}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_127 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_95, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_63}; // @[pla.scala:98:53]
wire [8:0] cs_decoder_decoded_andMatrixOutputs_hi_127 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_127, cs_decoder_decoded_andMatrixOutputs_hi_lo_124}; // @[pla.scala:98:53]
wire [16:0] _cs_decoder_decoded_andMatrixOutputs_T_127 = {cs_decoder_decoded_andMatrixOutputs_hi_127, cs_decoder_decoded_andMatrixOutputs_lo_127}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_60_2 = &_cs_decoder_decoded_andMatrixOutputs_T_127; // @[pla.scala:98:{53,70}]
wire _cs_decoder_decoded_orMatrixOutputs_T_24 = cs_decoder_decoded_andMatrixOutputs_60_2; // @[pla.scala:98:70, :114:36]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_31 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_7}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_67 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_11}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_116 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_67, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_31}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_54 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_54, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_46}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_69, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_67}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_78 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_64}; // @[pla.scala:90:45, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_127 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_78, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_54}; // @[pla.scala:98:53]
wire [8:0] cs_decoder_decoded_andMatrixOutputs_lo_128 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_127, cs_decoder_decoded_andMatrixOutputs_lo_lo_116}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_46 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_96, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_78}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_127, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_125}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_69 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_116}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_125 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_69, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_46}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_64 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_128, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_128}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_128, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_128}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_96 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_128}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_128 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_96, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_64}; // @[pla.scala:98:53]
wire [9:0] cs_decoder_decoded_andMatrixOutputs_hi_128 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_128, cs_decoder_decoded_andMatrixOutputs_hi_lo_125}; // @[pla.scala:98:53]
wire [18:0] _cs_decoder_decoded_andMatrixOutputs_T_128 = {cs_decoder_decoded_andMatrixOutputs_hi_128, cs_decoder_decoded_andMatrixOutputs_lo_128}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_7_2 = &_cs_decoder_decoded_andMatrixOutputs_T_128; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_32 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_6}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_12}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_68 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_8}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_117 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_68, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_32}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_55 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_47}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_70, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_68}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_79 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_65}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_128 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_79, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_55}; // @[pla.scala:98:53]
wire [9:0] cs_decoder_decoded_andMatrixOutputs_lo_129 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_128, cs_decoder_decoded_andMatrixOutputs_lo_lo_117}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_47 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_97, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_79}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_128, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_126}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_70 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_117}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_126 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_70, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_47}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_65 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_129, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_129}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_129, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_129}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_97 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_129}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_129 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_97, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_65}; // @[pla.scala:98:53]
wire [9:0] cs_decoder_decoded_andMatrixOutputs_hi_129 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_129, cs_decoder_decoded_andMatrixOutputs_hi_lo_126}; // @[pla.scala:98:53]
wire [19:0] _cs_decoder_decoded_andMatrixOutputs_T_129 = {cs_decoder_decoded_andMatrixOutputs_hi_129, cs_decoder_decoded_andMatrixOutputs_lo_129}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_14_2 = &_cs_decoder_decoded_andMatrixOutputs_T_129; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_33 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_6}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_9}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_69 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_7}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_118 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_69, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_33}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_33}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_56 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_13}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_69, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_66}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_80 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_56}; // @[pla.scala:91:29, :98:53]
wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_129 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_80, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_56}; // @[pla.scala:98:53]
wire [10:0] cs_decoder_decoded_andMatrixOutputs_lo_130 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_129, cs_decoder_decoded_andMatrixOutputs_lo_lo_118}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_48 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_71}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_127, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_118}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_71 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_98}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_127 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_71, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_48}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_130, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_130}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_66 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_129}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_130, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_130}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_98 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_130}; // @[pla.scala:91:29, :98:53]
wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_130 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_98, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_66}; // @[pla.scala:98:53]
wire [10:0] cs_decoder_decoded_andMatrixOutputs_hi_130 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_130, cs_decoder_decoded_andMatrixOutputs_hi_lo_127}; // @[pla.scala:98:53]
wire [21:0] _cs_decoder_decoded_andMatrixOutputs_T_130 = {cs_decoder_decoded_andMatrixOutputs_hi_130, cs_decoder_decoded_andMatrixOutputs_lo_130}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_92_2 = &_cs_decoder_decoded_andMatrixOutputs_T_130; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_70 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_72, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_70}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_119 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_70, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_67}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_81 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_119, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_99}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_130 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_81, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_81}; // @[pla.scala:90:45, :98:53]
wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_131 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_130, cs_decoder_decoded_andMatrixOutputs_lo_lo_119}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_72 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_131, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_130}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_128 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_72, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_128}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_67 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_131, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_131}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_99 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_131, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_131}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_131 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_99, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_67}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_131 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_131, cs_decoder_decoded_andMatrixOutputs_hi_lo_128}; // @[pla.scala:98:53]
wire [12:0] _cs_decoder_decoded_andMatrixOutputs_T_131 = {cs_decoder_decoded_andMatrixOutputs_hi_131, cs_decoder_decoded_andMatrixOutputs_lo_131}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_78_2 = &_cs_decoder_decoded_andMatrixOutputs_T_131; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_71 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_71, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_68}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_120 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_71, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_57}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_57 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_82, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_73}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_82 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_120, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_100}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_131 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_82, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_57}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_132 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_131, cs_decoder_decoded_andMatrixOutputs_lo_lo_120}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_73 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_132, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_131}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_129 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_73, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_129}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_68 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_132, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_132}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_100 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_132, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_132}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_132 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_100, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_68}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_132 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_132, cs_decoder_decoded_andMatrixOutputs_hi_lo_129}; // @[pla.scala:98:53]
wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_132 = {cs_decoder_decoded_andMatrixOutputs_hi_132, cs_decoder_decoded_andMatrixOutputs_lo_132}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_47_2 = &_cs_decoder_decoded_andMatrixOutputs_T_132; // @[pla.scala:98:{53,70}]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_69 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_70 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_60 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_61 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_76 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_74 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_75 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_76 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_80 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_66 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_67 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_79 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_80 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_6 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_29_3 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_92 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_93 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_19 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_17 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_21 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_19 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_20 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_21 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_22 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_23 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_72 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_72, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_69}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_121 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_72, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_58}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_58 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_83, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_74}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_83 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_121, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_101}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_132 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_83, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_58}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_133 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_132, cs_decoder_decoded_andMatrixOutputs_lo_lo_121}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_74 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_133, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_132}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_130 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_74, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_130}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_69 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_133, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_133}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_101 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_133, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_133}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_133 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_101, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_69}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_133 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_133, cs_decoder_decoded_andMatrixOutputs_hi_lo_130}; // @[pla.scala:98:53]
wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_133 = {cs_decoder_decoded_andMatrixOutputs_hi_133, cs_decoder_decoded_andMatrixOutputs_lo_133}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_4_2 = &_cs_decoder_decoded_andMatrixOutputs_T_133; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_73 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_73, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_70}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_122 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_73, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_59}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_59 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_84, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_75}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_84 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_122, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_102}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_133 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_84, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_59}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_134 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_133, cs_decoder_decoded_andMatrixOutputs_lo_lo_122}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_75 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_134, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_133}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_131 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_75, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_131}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_70 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_134, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_134}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_102 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_134, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_134}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_134 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_102, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_70}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_134 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_134, cs_decoder_decoded_andMatrixOutputs_hi_lo_131}; // @[pla.scala:98:53]
wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_134 = {cs_decoder_decoded_andMatrixOutputs_hi_134, cs_decoder_decoded_andMatrixOutputs_lo_134}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_123_2 = &_cs_decoder_decoded_andMatrixOutputs_T_134; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_74 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_71, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_60}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_123 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_74, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_49}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_60 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_74}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_85 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_103, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_85}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_134 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_85, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_60}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_135 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_134, cs_decoder_decoded_andMatrixOutputs_lo_lo_123}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_49 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_132, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_123}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_76 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_135, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_134}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_132 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_76, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_49}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_71 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_135, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_135}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_103 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_135, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_135}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_135 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_103, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_71}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_135 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_135, cs_decoder_decoded_andMatrixOutputs_hi_lo_132}; // @[pla.scala:98:53]
wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_135 = {cs_decoder_decoded_andMatrixOutputs_hi_135, cs_decoder_decoded_andMatrixOutputs_lo_135}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_107_2 = &_cs_decoder_decoded_andMatrixOutputs_T_135; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_75 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_72, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_61}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_124 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_75, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_50}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_61 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_77, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_75}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_86 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_104, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_86}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_135 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_86, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_61}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_136 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_135, cs_decoder_decoded_andMatrixOutputs_lo_lo_124}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_50 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_133, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_124}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_77 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_136, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_135}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_133 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_77, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_50}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_72 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_136, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_136}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_104 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_136, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_136}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_136 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_104, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_72}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_136 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_136, cs_decoder_decoded_andMatrixOutputs_hi_lo_133}; // @[pla.scala:98:53]
wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_136 = {cs_decoder_decoded_andMatrixOutputs_hi_136, cs_decoder_decoded_andMatrixOutputs_lo_136}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_33_2 = &_cs_decoder_decoded_andMatrixOutputs_T_136; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_76 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_73}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_125 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_62}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_62 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_87, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_78}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_87 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_125, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_105}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_136 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_87, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_62}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_137 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_136, cs_decoder_decoded_andMatrixOutputs_lo_lo_125}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_78 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_137, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_136}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_134 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_134}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_73 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_137, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_137}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_105 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_137, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_137}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_137 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_105, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_73}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_137 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_137, cs_decoder_decoded_andMatrixOutputs_hi_lo_134}; // @[pla.scala:98:53]
wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_137 = {cs_decoder_decoded_andMatrixOutputs_hi_137, cs_decoder_decoded_andMatrixOutputs_lo_137}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_88_2 = &_cs_decoder_decoded_andMatrixOutputs_T_137; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_77 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_74, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_63}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_126 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_77, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_51}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_63 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_79, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_77}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_88 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_106, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_88}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_137 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_88, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_63}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_138 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_137, cs_decoder_decoded_andMatrixOutputs_lo_lo_126}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_51 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_135, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_126}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_79 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_138, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_137}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_135 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_79, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_51}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_74 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_138, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_138}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_106 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_138, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_138}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_138 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_106, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_74}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_138 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_138, cs_decoder_decoded_andMatrixOutputs_hi_lo_135}; // @[pla.scala:98:53]
wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_138 = {cs_decoder_decoded_andMatrixOutputs_hi_138, cs_decoder_decoded_andMatrixOutputs_lo_138}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_87_2 = &_cs_decoder_decoded_andMatrixOutputs_T_138; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_78 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_75, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_64}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_127 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_52}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_64 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_78}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_89 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_107, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_89}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_138 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_89, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_64}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_139 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_138, cs_decoder_decoded_andMatrixOutputs_lo_lo_127}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_52 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_136, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_127}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_80 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_139, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_138}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_136 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_80, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_52}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_75 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_139, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_139}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_107 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_139, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_139}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_139 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_107, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_75}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_139 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_139, cs_decoder_decoded_andMatrixOutputs_hi_lo_136}; // @[pla.scala:98:53]
wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_139 = {cs_decoder_decoded_andMatrixOutputs_hi_139, cs_decoder_decoded_andMatrixOutputs_lo_139}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_37_2 = &_cs_decoder_decoded_andMatrixOutputs_T_139; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_79 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_65}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_128 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_79, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_53}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_65 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_81, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_79}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_90 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_108, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_90}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_139 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_90, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_65}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_140 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_139, cs_decoder_decoded_andMatrixOutputs_lo_lo_128}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_53 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_137, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_128}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_81 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_140, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_139}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_137 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_81, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_53}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_76 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_140, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_140}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_108 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_140, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_140}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_140 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_108, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_76}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_140 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_140, cs_decoder_decoded_andMatrixOutputs_hi_lo_137}; // @[pla.scala:98:53]
wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_140 = {cs_decoder_decoded_andMatrixOutputs_hi_140, cs_decoder_decoded_andMatrixOutputs_lo_140}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_22_2 = &_cs_decoder_decoded_andMatrixOutputs_T_140; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_80 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_91, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_82}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_129 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_80}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_91 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_138, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_129}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_140 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_91, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_109}; // @[pla.scala:91:29, :98:53]
wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_141 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_140, cs_decoder_decoded_andMatrixOutputs_lo_lo_129}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_82 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_141, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_141}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_138 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_82, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_140}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_109 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_141, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_141}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_141 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_109, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_141}; // @[pla.scala:90:45, :98:53]
wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_141 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_141, cs_decoder_decoded_andMatrixOutputs_hi_lo_138}; // @[pla.scala:98:53]
wire [11:0] _cs_decoder_decoded_andMatrixOutputs_T_141 = {cs_decoder_decoded_andMatrixOutputs_hi_141, cs_decoder_decoded_andMatrixOutputs_lo_141}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_58_2 = &_cs_decoder_decoded_andMatrixOutputs_T_141; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_81 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_77, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_66}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_130 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_81, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_54}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_66 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_83, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_81}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_92 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_110, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_92}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_141 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_92, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_66}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_142 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_141, cs_decoder_decoded_andMatrixOutputs_lo_lo_130}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_54 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_139, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_130}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_83 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_142, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_141}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_139 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_83, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_54}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_77 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_142, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_142}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_110 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_142, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_142}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_142 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_110, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_77}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_142 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_142, cs_decoder_decoded_andMatrixOutputs_hi_lo_139}; // @[pla.scala:98:53]
wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_142 = {cs_decoder_decoded_andMatrixOutputs_hi_142, cs_decoder_decoded_andMatrixOutputs_lo_142}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_62_2 = &_cs_decoder_decoded_andMatrixOutputs_T_142; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_82 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_67}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_131 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_82, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_55}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_67 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_84, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_82}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_93 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_111, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_93}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_142 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_93, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_67}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_143 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_142, cs_decoder_decoded_andMatrixOutputs_lo_lo_131}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_55 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_140, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_131}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_84 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_143, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_142}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_140 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_84, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_55}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_78 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_143, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_143}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_111 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_143, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_143}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_143 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_111, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_78}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_143 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_143, cs_decoder_decoded_andMatrixOutputs_hi_lo_140}; // @[pla.scala:98:53]
wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_143 = {cs_decoder_decoded_andMatrixOutputs_hi_143, cs_decoder_decoded_andMatrixOutputs_lo_143}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_9_2 = &_cs_decoder_decoded_andMatrixOutputs_T_143; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_83 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_79, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_68}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_132 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_83, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_56}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_68 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_85, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_83}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_94 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_112, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_94}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_143 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_94, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_68}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_144 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_143, cs_decoder_decoded_andMatrixOutputs_lo_lo_132}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_56 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_141, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_132}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_85 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_144, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_143}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_141 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_85, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_56}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_79 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_144, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_144}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_112 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_144, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_144}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_144 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_112, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_79}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_144 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_144, cs_decoder_decoded_andMatrixOutputs_hi_lo_141}; // @[pla.scala:98:53]
wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_144 = {cs_decoder_decoded_andMatrixOutputs_hi_144, cs_decoder_decoded_andMatrixOutputs_lo_144}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_64_2 = &_cs_decoder_decoded_andMatrixOutputs_T_144; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_84 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_69}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_133 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_84, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_57}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_69 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_86, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_84}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_95 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_113, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_95}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_144 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_95, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_69}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_145 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_144, cs_decoder_decoded_andMatrixOutputs_lo_lo_133}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_57 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_142, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_133}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_86 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_145, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_144}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_142 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_86, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_57}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_80 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_145, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_145}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_113 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_145, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_145}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_145 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_113, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_80}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_145 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_145, cs_decoder_decoded_andMatrixOutputs_hi_lo_142}; // @[pla.scala:98:53]
wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_145 = {cs_decoder_decoded_andMatrixOutputs_hi_145, cs_decoder_decoded_andMatrixOutputs_lo_145}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_146_2 = &_cs_decoder_decoded_andMatrixOutputs_T_145; // @[pla.scala:98:{53,70}]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_34 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_35 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_87 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_10 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_11 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_12 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_13 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_20 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_15 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_16 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_6 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_30_3 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_71 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_84 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_73 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_74 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_75 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_76 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_16 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_11 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_18 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_13 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_14 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_15 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_16 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_17 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_34 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_34, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_14}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_85 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_70, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_58}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_134 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_85, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_34}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_70 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_85, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_81}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_96 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_96, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_87}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_145 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_96, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_70}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_146 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_145, cs_decoder_decoded_andMatrixOutputs_lo_lo_134}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_58 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_134, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_114}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_87 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_145, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_143}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_143 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_87, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_58}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_81 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_146, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_146}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_146, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_146}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_114 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_146}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_146 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_114, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_81}; // @[pla.scala:98:53]
wire [8:0] cs_decoder_decoded_andMatrixOutputs_hi_146 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_146, cs_decoder_decoded_andMatrixOutputs_hi_lo_143}; // @[pla.scala:98:53]
wire [16:0] _cs_decoder_decoded_andMatrixOutputs_T_146 = {cs_decoder_decoded_andMatrixOutputs_hi_146, cs_decoder_decoded_andMatrixOutputs_lo_146}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_113_2 = &_cs_decoder_decoded_andMatrixOutputs_T_146; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_35 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_15}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_86 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_71, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_59}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_135 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_86, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_35}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_71 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_86, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_82}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_97 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_97, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_88}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_146 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_97, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_71}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_147 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_146, cs_decoder_decoded_andMatrixOutputs_lo_lo_135}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_59 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_135, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_115}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_88 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_146, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_144}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_144 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_88, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_59}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_82 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_147, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_147}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_147, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_147}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_115 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_147}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_147 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_115, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_82}; // @[pla.scala:98:53]
wire [8:0] cs_decoder_decoded_andMatrixOutputs_hi_147 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_147, cs_decoder_decoded_andMatrixOutputs_hi_lo_144}; // @[pla.scala:98:53]
wire [16:0] _cs_decoder_decoded_andMatrixOutputs_T_147 = {cs_decoder_decoded_andMatrixOutputs_hi_147, cs_decoder_decoded_andMatrixOutputs_lo_147}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_80_2 = &_cs_decoder_decoded_andMatrixOutputs_T_147; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_87 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_98, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_89}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_136 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_87, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_87}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_98 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_145, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_136}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_147 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_98, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_116}; // @[pla.scala:91:29, :98:53]
wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_148 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_147, cs_decoder_decoded_andMatrixOutputs_lo_lo_136}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_89 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_148, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_148}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_145 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_89, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_147}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_116 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_148, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_148}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_148 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_116, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_148}; // @[pla.scala:90:45, :98:53]
wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_148 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_148, cs_decoder_decoded_andMatrixOutputs_hi_lo_145}; // @[pla.scala:98:53]
wire [11:0] _cs_decoder_decoded_andMatrixOutputs_T_148 = {cs_decoder_decoded_andMatrixOutputs_hi_148, cs_decoder_decoded_andMatrixOutputs_lo_148}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_44_2 = &_cs_decoder_decoded_andMatrixOutputs_T_148; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_36 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_10}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_88 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_36}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_137 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_88, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_36}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_72 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_83, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_72}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_99, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_90}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_99 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_88}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_148 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_99, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_72}; // @[pla.scala:98:53]
wire [8:0] cs_decoder_decoded_andMatrixOutputs_lo_149 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_148, cs_decoder_decoded_andMatrixOutputs_lo_lo_137}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_60 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_137, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_117}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_90 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_148, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_146}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_146 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_90, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_60}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_83 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_149, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_149}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_16 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_149, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_149}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_117 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_149}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_149 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_117, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_83}; // @[pla.scala:98:53]
wire [8:0] cs_decoder_decoded_andMatrixOutputs_hi_149 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_149, cs_decoder_decoded_andMatrixOutputs_hi_lo_146}; // @[pla.scala:98:53]
wire [17:0] _cs_decoder_decoded_andMatrixOutputs_T_149 = {cs_decoder_decoded_andMatrixOutputs_hi_149, cs_decoder_decoded_andMatrixOutputs_lo_149}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_159_2 = &_cs_decoder_decoded_andMatrixOutputs_T_149; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_37 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_10}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_89 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_17}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_138 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_89, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_37}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_73 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_73, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_61}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_91, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_89}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_100 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_84}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_149 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_100, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_73}; // @[pla.scala:98:53]
wire [8:0] cs_decoder_decoded_andMatrixOutputs_lo_150 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_149, cs_decoder_decoded_andMatrixOutputs_lo_lo_138}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_61 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_118, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_100}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_149, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_147}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_91 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_138}; // @[pla.scala:90:45, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_147 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_91, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_61}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_84 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_150, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_150}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_150, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_150}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_118 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_150}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_150 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_118, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_84}; // @[pla.scala:98:53]
wire [9:0] cs_decoder_decoded_andMatrixOutputs_hi_150 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_150, cs_decoder_decoded_andMatrixOutputs_hi_lo_147}; // @[pla.scala:98:53]
wire [18:0] _cs_decoder_decoded_andMatrixOutputs_T_150 = {cs_decoder_decoded_andMatrixOutputs_hi_150, cs_decoder_decoded_andMatrixOutputs_lo_150}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_0_2 = &_cs_decoder_decoded_andMatrixOutputs_T_150; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_38 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_12}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_90 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_62, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_38}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_139 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_90, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_38}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_74 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_85, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_74}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_101, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_92}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_101 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_90}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_150 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_101, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_74}; // @[pla.scala:98:53]
wire [8:0] cs_decoder_decoded_andMatrixOutputs_lo_151 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_150, cs_decoder_decoded_andMatrixOutputs_lo_lo_139}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_62 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_139, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_119}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_92 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_150, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_148}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_148 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_92, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_62}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_85 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_151, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_151}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_151, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_151}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_119 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_151}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_151 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_119, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_85}; // @[pla.scala:98:53]
wire [8:0] cs_decoder_decoded_andMatrixOutputs_hi_151 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_151, cs_decoder_decoded_andMatrixOutputs_hi_lo_148}; // @[pla.scala:98:53]
wire [17:0] _cs_decoder_decoded_andMatrixOutputs_T_151 = {cs_decoder_decoded_andMatrixOutputs_hi_151, cs_decoder_decoded_andMatrixOutputs_lo_151}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_99_2 = &_cs_decoder_decoded_andMatrixOutputs_T_151; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_39 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_11}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_91 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_19}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_140 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_91, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_39}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_75 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_75, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_63}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_93, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_91}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_102 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_86}; // @[pla.scala:90:45, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_151 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_102, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_75}; // @[pla.scala:98:53]
wire [8:0] cs_decoder_decoded_andMatrixOutputs_lo_152 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_151, cs_decoder_decoded_andMatrixOutputs_lo_lo_140}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_63 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_120, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_102}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_151, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_149}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_93 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_140}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_149 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_93, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_63}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_86 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_152, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_152}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_152, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_152}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_120 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_152}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_152 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_120, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_86}; // @[pla.scala:98:53]
wire [9:0] cs_decoder_decoded_andMatrixOutputs_hi_152 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_152, cs_decoder_decoded_andMatrixOutputs_hi_lo_149}; // @[pla.scala:98:53]
wire [18:0] _cs_decoder_decoded_andMatrixOutputs_T_152 = {cs_decoder_decoded_andMatrixOutputs_hi_152, cs_decoder_decoded_andMatrixOutputs_lo_152}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_13_2 = &_cs_decoder_decoded_andMatrixOutputs_T_152; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_40 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_14}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_92 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_64, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_40}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_141 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_92, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_40}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_76 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_87, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_76}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_103, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_94}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_103 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_92}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_152 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_103, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_76}; // @[pla.scala:98:53]
wire [8:0] cs_decoder_decoded_andMatrixOutputs_lo_153 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_152, cs_decoder_decoded_andMatrixOutputs_lo_lo_141}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_64 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_141, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_121}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_94 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_152, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_150}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_150 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_94, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_64}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_87 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_153, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_153}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_153, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_153}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_121 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_153}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_153 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_121, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_87}; // @[pla.scala:98:53]
wire [8:0] cs_decoder_decoded_andMatrixOutputs_hi_153 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_153, cs_decoder_decoded_andMatrixOutputs_hi_lo_150}; // @[pla.scala:98:53]
wire [17:0] _cs_decoder_decoded_andMatrixOutputs_T_153 = {cs_decoder_decoded_andMatrixOutputs_hi_153, cs_decoder_decoded_andMatrixOutputs_lo_153}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_120_2 = &_cs_decoder_decoded_andMatrixOutputs_T_153; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_41 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_12}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_93 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_21}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_142 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_93, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_41}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_77 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_77, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_65}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_95, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_93}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_104 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_88}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_153 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_104, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_77}; // @[pla.scala:98:53]
wire [8:0] cs_decoder_decoded_andMatrixOutputs_lo_154 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_153, cs_decoder_decoded_andMatrixOutputs_lo_lo_142}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_65 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_122, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_104}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_153, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_151}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_95 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_142}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_151 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_95, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_65}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_88 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_154, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_154}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_154, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_154}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_122 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_154}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_154 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_122, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_88}; // @[pla.scala:98:53]
wire [9:0] cs_decoder_decoded_andMatrixOutputs_hi_154 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_154, cs_decoder_decoded_andMatrixOutputs_hi_lo_151}; // @[pla.scala:98:53]
wire [18:0] _cs_decoder_decoded_andMatrixOutputs_T_154 = {cs_decoder_decoded_andMatrixOutputs_hi_154, cs_decoder_decoded_andMatrixOutputs_lo_154}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_171_2 = &_cs_decoder_decoded_andMatrixOutputs_T_154; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_42 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_13}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_94 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_42, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_22}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_143 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_94, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_42}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_78 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_66}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_16 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_96, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_94}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_105 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_89}; // @[pla.scala:90:45, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_154 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_105, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_78}; // @[pla.scala:98:53]
wire [8:0] cs_decoder_decoded_andMatrixOutputs_lo_155 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_154, cs_decoder_decoded_andMatrixOutputs_lo_lo_143}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_66 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_123, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_105}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_154, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_152}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_96 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_143}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_152 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_96, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_66}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_89 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_155, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_155}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_155, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_155}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_123 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_155}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_155 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_123, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_89}; // @[pla.scala:98:53]
wire [9:0] cs_decoder_decoded_andMatrixOutputs_hi_155 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_155, cs_decoder_decoded_andMatrixOutputs_hi_lo_152}; // @[pla.scala:98:53]
wire [18:0] _cs_decoder_decoded_andMatrixOutputs_T_155 = {cs_decoder_decoded_andMatrixOutputs_hi_155, cs_decoder_decoded_andMatrixOutputs_lo_155}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_109_2 = &_cs_decoder_decoded_andMatrixOutputs_T_155; // @[pla.scala:98:{53,70}]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_7 = cs_decoder_decoded_plaInput[24]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_7 = cs_decoder_decoded_plaInput[24]; // @[pla.scala:77:22, :90:45]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_6}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_43 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_6}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_6}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_6}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_95 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_8, cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_6}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_144 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_95, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_43}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_8}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_79 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_7}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_17}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_67, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_43}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_106 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_17, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_6}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_155 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_106, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_79}; // @[pla.scala:98:53]
wire [13:0] cs_decoder_decoded_andMatrixOutputs_lo_156 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_155, cs_decoder_decoded_andMatrixOutputs_lo_lo_144}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_95, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_90}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_67 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_79}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_106, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_97}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_144, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_124}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_97 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_14, cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_6}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_153 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_97, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_67}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_156, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_155}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_90 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_153}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_156, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_156}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_156, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_156}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_124 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_23, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_6}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_156 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_124, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_90}; // @[pla.scala:98:53]
wire [13:0] cs_decoder_decoded_andMatrixOutputs_hi_156 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_156, cs_decoder_decoded_andMatrixOutputs_hi_lo_153}; // @[pla.scala:98:53]
wire [27:0] _cs_decoder_decoded_andMatrixOutputs_T_156 = {cs_decoder_decoded_andMatrixOutputs_hi_156, cs_decoder_decoded_andMatrixOutputs_lo_156}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_59_2 = &_cs_decoder_decoded_andMatrixOutputs_T_156; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_30_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_31_1}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_28_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_29_3}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_44 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_7, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_lo_1}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_7}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_7}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_96 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_9, cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_7}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_145 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_96, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_44}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_7}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_8}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_80 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_8, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_3}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_9}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_18}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_107 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_18, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_7}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_156 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_107, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_80}; // @[pla.scala:98:53]
wire [15:0] cs_decoder_decoded_andMatrixOutputs_lo_157 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_156, cs_decoder_decoded_andMatrixOutputs_lo_lo_145}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_68, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_44}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_91, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_80}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_68 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_7, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_3}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_98, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_96}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_125, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_107}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_98 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_15, cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_7}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_154 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_98, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_68}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_154, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_145}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_157, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_156}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_91 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_8, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_3}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_157, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_157}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_157, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_157}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_125 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_24, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_7}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_157 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_125, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_91}; // @[pla.scala:98:53]
wire [15:0] cs_decoder_decoded_andMatrixOutputs_hi_157 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_157, cs_decoder_decoded_andMatrixOutputs_hi_lo_154}; // @[pla.scala:98:53]
wire [31:0] _cs_decoder_decoded_andMatrixOutputs_T_157 = {cs_decoder_decoded_andMatrixOutputs_hi_157, cs_decoder_decoded_andMatrixOutputs_lo_157}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_106_2 = &_cs_decoder_decoded_andMatrixOutputs_T_157; // @[pla.scala:98:{53,70}]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_97 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_69 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_70 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_45 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_72 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_46 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_47 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_48 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_49 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_10 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_9 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_12 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_10 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_11 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_12 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_13 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_14 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_97 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_108, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_99}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_146 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_97, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_97}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_108 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_155, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_146}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_157 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_108, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_126}; // @[pla.scala:91:29, :98:53]
wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_158 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_157, cs_decoder_decoded_andMatrixOutputs_lo_lo_146}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_99 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_158, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_158}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_155 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_99, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_157}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_126 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_158, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_158}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_158 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_126, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_158}; // @[pla.scala:90:45, :98:53]
wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_158 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_158, cs_decoder_decoded_andMatrixOutputs_hi_lo_155}; // @[pla.scala:98:53]
wire [11:0] _cs_decoder_decoded_andMatrixOutputs_T_158 = {cs_decoder_decoded_andMatrixOutputs_hi_158, cs_decoder_decoded_andMatrixOutputs_lo_158}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_155_2 = &_cs_decoder_decoded_andMatrixOutputs_T_158; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_98 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_92, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_81}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_147 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_98, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_69}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_81 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_100, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_98}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_109 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_127, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_109}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_158 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_109, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_81}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_159 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_158, cs_decoder_decoded_andMatrixOutputs_lo_lo_147}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_69 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_156, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_147}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_100 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_159, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_158}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_156 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_100, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_69}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_92 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_159, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_159}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_127 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_159, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_159}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_159 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_127, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_92}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_159 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_159, cs_decoder_decoded_andMatrixOutputs_hi_lo_156}; // @[pla.scala:98:53]
wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_159 = {cs_decoder_decoded_andMatrixOutputs_hi_159, cs_decoder_decoded_andMatrixOutputs_lo_159}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_149_2 = &_cs_decoder_decoded_andMatrixOutputs_T_159; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_99 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_93, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_82}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_148 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_99, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_70}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_82 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_101, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_99}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_110 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_128, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_110}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_159 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_110, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_82}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_160 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_159, cs_decoder_decoded_andMatrixOutputs_lo_lo_148}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_70 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_157, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_148}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_101 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_160, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_159}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_157 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_101, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_70}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_93 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_160, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_160}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_128 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_160, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_160}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_160 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_128, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_93}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_160 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_160, cs_decoder_decoded_andMatrixOutputs_hi_lo_157}; // @[pla.scala:98:53]
wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_160 = {cs_decoder_decoded_andMatrixOutputs_hi_160, cs_decoder_decoded_andMatrixOutputs_lo_160}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_136_2 = &_cs_decoder_decoded_andMatrixOutputs_T_160; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_45 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_71, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_45}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_100 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_94, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_83}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_149 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_100, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_45}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_83 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_102, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_100}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_111 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_129, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_111}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_160 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_111, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_83}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_161 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_160, cs_decoder_decoded_andMatrixOutputs_lo_lo_149}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_71 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_158, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_149}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_102 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_161, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_160}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_158 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_102, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_71}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_94 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_161, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_161}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_129 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_161, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_161}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_161 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_129, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_94}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_161 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_161, cs_decoder_decoded_andMatrixOutputs_hi_lo_158}; // @[pla.scala:98:53]
wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_161 = {cs_decoder_decoded_andMatrixOutputs_hi_161, cs_decoder_decoded_andMatrixOutputs_lo_161}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_31_2 = &_cs_decoder_decoded_andMatrixOutputs_T_161; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_101 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_95, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_84}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_150 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_101, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_72}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_84 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_103, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_101}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_112 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_130, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_112}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_161 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_112, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_84}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_162 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_161, cs_decoder_decoded_andMatrixOutputs_lo_lo_150}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_72 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_159, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_150}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_103 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_162, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_161}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_159 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_103, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_72}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_95 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_162, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_162}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_130 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_162, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_162}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_162 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_130, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_95}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_162 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_162, cs_decoder_decoded_andMatrixOutputs_hi_lo_159}; // @[pla.scala:98:53]
wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_162 = {cs_decoder_decoded_andMatrixOutputs_hi_162, cs_decoder_decoded_andMatrixOutputs_lo_162}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_90_2 = &_cs_decoder_decoded_andMatrixOutputs_T_162; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_46 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_73, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_46}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_102 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_96, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_85}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_151 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_102, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_46}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_85 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_104, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_102}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_113 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_131, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_113}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_162 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_113, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_85}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_163 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_162, cs_decoder_decoded_andMatrixOutputs_lo_lo_151}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_73 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_160, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_151}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_104 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_163, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_162}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_160 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_104, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_73}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_96 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_163, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_163}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_131 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_163, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_163}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_163 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_131, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_96}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_163 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_163, cs_decoder_decoded_andMatrixOutputs_hi_lo_160}; // @[pla.scala:98:53]
wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_163 = {cs_decoder_decoded_andMatrixOutputs_hi_163, cs_decoder_decoded_andMatrixOutputs_lo_163}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_39_2 = &_cs_decoder_decoded_andMatrixOutputs_T_163; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_47 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_74, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_47}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_103 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_97, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_86}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_152 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_103, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_47}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_86 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_105, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_103}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_114 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_132, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_114}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_163 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_114, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_86}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_164 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_163, cs_decoder_decoded_andMatrixOutputs_lo_lo_152}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_74 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_161, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_152}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_105 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_164, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_163}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_161 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_105, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_74}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_97 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_164, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_164}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_132 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_164, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_164}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_164 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_132, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_97}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_164 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_164, cs_decoder_decoded_andMatrixOutputs_hi_lo_161}; // @[pla.scala:98:53]
wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_164 = {cs_decoder_decoded_andMatrixOutputs_hi_164, cs_decoder_decoded_andMatrixOutputs_lo_164}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_83_2 = &_cs_decoder_decoded_andMatrixOutputs_T_164; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_48 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_75, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_48}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_104 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_98, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_87}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_153 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_104, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_48}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_87 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_106, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_104}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_115 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_133, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_115}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_164 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_115, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_87}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_165 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_164, cs_decoder_decoded_andMatrixOutputs_lo_lo_153}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_75 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_162, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_153}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_106 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_165, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_164}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_162 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_106, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_75}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_98 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_165, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_165}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_133 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_165, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_165}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_165 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_133, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_98}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_165 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_165, cs_decoder_decoded_andMatrixOutputs_hi_lo_162}; // @[pla.scala:98:53]
wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_165 = {cs_decoder_decoded_andMatrixOutputs_hi_165, cs_decoder_decoded_andMatrixOutputs_lo_165}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_103_2 = &_cs_decoder_decoded_andMatrixOutputs_T_165; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_49 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_49}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_105 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_99, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_88}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_154 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_105, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_49}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_88 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_107, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_105}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_116 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_134, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_116}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_165 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_116, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_88}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_166 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_165, cs_decoder_decoded_andMatrixOutputs_lo_lo_154}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_76 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_163, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_154}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_107 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_166, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_165}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_163 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_107, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_76}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_99 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_166, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_166}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_134 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_166, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_166}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_166 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_134, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_99}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_166 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_166, cs_decoder_decoded_andMatrixOutputs_hi_lo_163}; // @[pla.scala:98:53]
wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_166 = {cs_decoder_decoded_andMatrixOutputs_hi_166, cs_decoder_decoded_andMatrixOutputs_lo_166}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_138_2 = &_cs_decoder_decoded_andMatrixOutputs_T_166; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_50 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_10}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_50, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_25}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_106 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_19}; // @[pla.scala:90:45, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_155 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_106, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_50}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_89 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_89, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_77}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_108, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_106}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_117 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_100}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_166 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_117, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_89}; // @[pla.scala:98:53]
wire [9:0] cs_decoder_decoded_andMatrixOutputs_lo_167 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_166, cs_decoder_decoded_andMatrixOutputs_lo_lo_155}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_77 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_135, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_117}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_16 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_166, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_164}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_108 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_155}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_164 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_108, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_77}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_100 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_167, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_167}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_167, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_167}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_135 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_167}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_167 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_135, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_100}; // @[pla.scala:98:53]
wire [9:0] cs_decoder_decoded_andMatrixOutputs_hi_167 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_167, cs_decoder_decoded_andMatrixOutputs_hi_lo_164}; // @[pla.scala:98:53]
wire [19:0] _cs_decoder_decoded_andMatrixOutputs_T_167 = {cs_decoder_decoded_andMatrixOutputs_hi_167, cs_decoder_decoded_andMatrixOutputs_lo_167}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_86_2 = &_cs_decoder_decoded_andMatrixOutputs_T_167; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_51 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_9}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_20}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_107 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_17}; // @[pla.scala:90:45, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_156 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_107, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_51}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_90 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_51}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_107, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_101}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_118 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_90}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_167 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_118, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_90}; // @[pla.scala:98:53]
wire [9:0] cs_decoder_decoded_andMatrixOutputs_lo_168 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_167, cs_decoder_decoded_andMatrixOutputs_lo_lo_156}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_78 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_118, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_109}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_165, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_156}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_109 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_136}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_165 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_109, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_78}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_168, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_168}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_101 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_167}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_168, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_168}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_136 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_168}; // @[pla.scala:91:29, :98:53]
wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_168 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_136, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_101}; // @[pla.scala:98:53]
wire [10:0] cs_decoder_decoded_andMatrixOutputs_hi_168 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_168, cs_decoder_decoded_andMatrixOutputs_hi_lo_165}; // @[pla.scala:98:53]
wire [20:0] _cs_decoder_decoded_andMatrixOutputs_T_168 = {cs_decoder_decoded_andMatrixOutputs_hi_168, cs_decoder_decoded_andMatrixOutputs_lo_168}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_111_2 = &_cs_decoder_decoded_andMatrixOutputs_T_168; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_52 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_12}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_52, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_27}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_108 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_21}; // @[pla.scala:90:45, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_157 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_108, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_52}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_91 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_91, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_79}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_110, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_108}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_119 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_102}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_168 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_119, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_91}; // @[pla.scala:98:53]
wire [9:0] cs_decoder_decoded_andMatrixOutputs_lo_169 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_168, cs_decoder_decoded_andMatrixOutputs_lo_lo_157}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_79 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_137, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_119}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_168, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_166}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_110 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_157}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_166 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_110, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_79}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_102 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_169, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_169}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_169, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_169}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_137 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_169}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_169 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_137, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_102}; // @[pla.scala:98:53]
wire [9:0] cs_decoder_decoded_andMatrixOutputs_hi_169 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_169, cs_decoder_decoded_andMatrixOutputs_hi_lo_166}; // @[pla.scala:98:53]
wire [19:0] _cs_decoder_decoded_andMatrixOutputs_T_169 = {cs_decoder_decoded_andMatrixOutputs_hi_169, cs_decoder_decoded_andMatrixOutputs_lo_169}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_32_2 = &_cs_decoder_decoded_andMatrixOutputs_T_169; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_53 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_10}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_22}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_109 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_19}; // @[pla.scala:90:45, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_158 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_109, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_53}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_92 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_53}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_109, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_103}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_120 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_92}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_169 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_120, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_92}; // @[pla.scala:98:53]
wire [9:0] cs_decoder_decoded_andMatrixOutputs_lo_170 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_169, cs_decoder_decoded_andMatrixOutputs_lo_lo_158}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_80 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_120, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_111}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_167, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_158}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_111 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_138}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_167 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_111, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_80}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_170, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_170}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_103 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_169}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_170, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_170}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_138 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_170}; // @[pla.scala:91:29, :98:53]
wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_170 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_138, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_103}; // @[pla.scala:98:53]
wire [10:0] cs_decoder_decoded_andMatrixOutputs_hi_170 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_170, cs_decoder_decoded_andMatrixOutputs_hi_lo_167}; // @[pla.scala:98:53]
wire [20:0] _cs_decoder_decoded_andMatrixOutputs_T_170 = {cs_decoder_decoded_andMatrixOutputs_hi_170, cs_decoder_decoded_andMatrixOutputs_lo_170}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_127_2 = &_cs_decoder_decoded_andMatrixOutputs_T_170; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_54 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_11}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_23}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_110 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_20}; // @[pla.scala:90:45, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_159 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_110, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_54}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_93 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_81, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_54}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_110, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_104}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_121 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_93}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_170 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_121, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_93}; // @[pla.scala:98:53]
wire [9:0] cs_decoder_decoded_andMatrixOutputs_lo_171 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_170, cs_decoder_decoded_andMatrixOutputs_lo_lo_159}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_81 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_121, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_112}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_168, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_159}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_112 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_139}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_168 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_112, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_81}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_171, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_171}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_104 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_170}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_29 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_171, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_171}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_139 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_171}; // @[pla.scala:91:29, :98:53]
wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_171 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_139, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_104}; // @[pla.scala:98:53]
wire [10:0] cs_decoder_decoded_andMatrixOutputs_hi_171 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_171, cs_decoder_decoded_andMatrixOutputs_hi_lo_168}; // @[pla.scala:98:53]
wire [20:0] _cs_decoder_decoded_andMatrixOutputs_T_171 = {cs_decoder_decoded_andMatrixOutputs_hi_171, cs_decoder_decoded_andMatrixOutputs_lo_171}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_164_2 = &_cs_decoder_decoded_andMatrixOutputs_T_171; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_55 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_12}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_24}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_111 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_21}; // @[pla.scala:90:45, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_160 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_111, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_55}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_94 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_82, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_55}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_111, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_105}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_122 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_94}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_171 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_122, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_94}; // @[pla.scala:98:53]
wire [9:0] cs_decoder_decoded_andMatrixOutputs_lo_172 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_171, cs_decoder_decoded_andMatrixOutputs_lo_lo_160}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_82 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_122, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_113}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_169, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_160}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_113 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_140}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_169 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_113, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_82}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_172, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_172}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_105 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_171}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_30 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_172, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_172}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_140 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_172}; // @[pla.scala:91:29, :98:53]
wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_172 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_140, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_105}; // @[pla.scala:98:53]
wire [10:0] cs_decoder_decoded_andMatrixOutputs_hi_172 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_172, cs_decoder_decoded_andMatrixOutputs_hi_lo_169}; // @[pla.scala:98:53]
wire [20:0] _cs_decoder_decoded_andMatrixOutputs_T_172 = {cs_decoder_decoded_andMatrixOutputs_hi_172, cs_decoder_decoded_andMatrixOutputs_lo_172}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_61_2 = &_cs_decoder_decoded_andMatrixOutputs_T_172; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_56 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_13}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_16 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_25}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_112 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_22}; // @[pla.scala:90:45, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_161 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_112, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_56}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_95 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_83, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_56}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_112, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_106}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_123 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_95}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_172 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_123, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_95}; // @[pla.scala:98:53]
wire [9:0] cs_decoder_decoded_andMatrixOutputs_lo_173 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_172, cs_decoder_decoded_andMatrixOutputs_lo_lo_161}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_83 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_123, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_114}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_170, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_161}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_114 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_141}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_170 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_114, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_83}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_173, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_173}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_106 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_172}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_31 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_173, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_173}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_141 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_173}; // @[pla.scala:91:29, :98:53]
wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_173 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_141, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_106}; // @[pla.scala:98:53]
wire [10:0] cs_decoder_decoded_andMatrixOutputs_hi_173 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_173, cs_decoder_decoded_andMatrixOutputs_hi_lo_170}; // @[pla.scala:98:53]
wire [20:0] _cs_decoder_decoded_andMatrixOutputs_T_173 = {cs_decoder_decoded_andMatrixOutputs_hi_173, cs_decoder_decoded_andMatrixOutputs_lo_173}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_36_2 = &_cs_decoder_decoded_andMatrixOutputs_T_173; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_57 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_14}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_26}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_113 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_23}; // @[pla.scala:90:45, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_162 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_113, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_57}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_96 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_84, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_57}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_113, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_107}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_124 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_96}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_173 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_124, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_96}; // @[pla.scala:98:53]
wire [9:0] cs_decoder_decoded_andMatrixOutputs_lo_174 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_173, cs_decoder_decoded_andMatrixOutputs_lo_lo_162}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_84 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_124, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_115}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_171, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_162}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_115 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_142}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_171 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_115, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_84}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_174, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_174}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_107 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_173}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_32 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_174, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_174}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_142 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_174}; // @[pla.scala:91:29, :98:53]
wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_174 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_142, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_107}; // @[pla.scala:98:53]
wire [10:0] cs_decoder_decoded_andMatrixOutputs_hi_174 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_174, cs_decoder_decoded_andMatrixOutputs_hi_lo_171}; // @[pla.scala:98:53]
wire [20:0] _cs_decoder_decoded_andMatrixOutputs_T_174 = {cs_decoder_decoded_andMatrixOutputs_hi_174, cs_decoder_decoded_andMatrixOutputs_lo_174}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_51_2 = &_cs_decoder_decoded_andMatrixOutputs_T_174; // @[pla.scala:98:{53,70}]
wire [1:0] _GEN = {cs_decoder_decoded_andMatrixOutputs_45_2, cs_decoder_decoded_andMatrixOutputs_140_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_lo_hi = _GEN; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_13; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_lo_hi_13 = _GEN; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_3; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_3 = _GEN; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_7; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_7 = _GEN; // @[pla.scala:114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo = {cs_decoder_decoded_orMatrixOutputs_lo_hi, cs_decoder_decoded_andMatrixOutputs_59_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] _GEN_0 = {cs_decoder_decoded_andMatrixOutputs_43_2, cs_decoder_decoded_andMatrixOutputs_167_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_hi_hi = _GEN_0; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_14; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_hi_hi_14 = _GEN_0; // @[pla.scala:114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi = {cs_decoder_decoded_orMatrixOutputs_hi_hi, cs_decoder_decoded_andMatrixOutputs_137_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] _cs_decoder_decoded_orMatrixOutputs_T_2 = {cs_decoder_decoded_orMatrixOutputs_hi, cs_decoder_decoded_orMatrixOutputs_lo}; // @[pla.scala:114:19]
wire _cs_decoder_decoded_orMatrixOutputs_T_3 = |_cs_decoder_decoded_orMatrixOutputs_T_2; // @[pla.scala:114:{19,36}]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo = {cs_decoder_decoded_andMatrixOutputs_60_2, cs_decoder_decoded_andMatrixOutputs_59_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] _GEN_1 = {cs_decoder_decoded_andMatrixOutputs_121_2, cs_decoder_decoded_andMatrixOutputs_45_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi = _GEN_1; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi = _GEN_1; // @[pla.scala:114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_1 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_140_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_1 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_1, cs_decoder_decoded_orMatrixOutputs_lo_lo}; // @[pla.scala:114:19]
wire [1:0] _GEN_2 = {cs_decoder_decoded_andMatrixOutputs_15_2, cs_decoder_decoded_andMatrixOutputs_137_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_hi_lo_hi = _GEN_2; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_1; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_1 = _GEN_2; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_4; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_4 = _GEN_2; // @[pla.scala:114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi, cs_decoder_decoded_andMatrixOutputs_100_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi = {cs_decoder_decoded_andMatrixOutputs_102_2, cs_decoder_decoded_andMatrixOutputs_43_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_1 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_167_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] cs_decoder_decoded_orMatrixOutputs_hi_1 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_1, cs_decoder_decoded_orMatrixOutputs_hi_lo}; // @[pla.scala:114:19]
wire [10:0] _cs_decoder_decoded_orMatrixOutputs_T_4 = {cs_decoder_decoded_orMatrixOutputs_hi_1, cs_decoder_decoded_orMatrixOutputs_lo_1}; // @[pla.scala:114:19]
wire _cs_decoder_decoded_orMatrixOutputs_T_5 = |_cs_decoder_decoded_orMatrixOutputs_T_4; // @[pla.scala:114:{19,36}]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_1 = {cs_decoder_decoded_andMatrixOutputs_92_2, cs_decoder_decoded_andMatrixOutputs_106_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_50_2, cs_decoder_decoded_andMatrixOutputs_135_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_2 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_95_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_2 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_2, cs_decoder_decoded_orMatrixOutputs_lo_lo_1}; // @[pla.scala:114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_1 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_100_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_102_2, cs_decoder_decoded_andMatrixOutputs_67_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_2 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_167_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] cs_decoder_decoded_orMatrixOutputs_hi_2 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_hi_lo_1}; // @[pla.scala:114:19]
wire [10:0] _cs_decoder_decoded_orMatrixOutputs_T_6 = {cs_decoder_decoded_orMatrixOutputs_hi_2, cs_decoder_decoded_orMatrixOutputs_lo_2}; // @[pla.scala:114:19]
wire _cs_decoder_decoded_orMatrixOutputs_T_7 = |_cs_decoder_decoded_orMatrixOutputs_T_6; // @[pla.scala:114:{19,36}]
wire [1:0] _cs_decoder_decoded_orMatrixOutputs_T_9 = {cs_decoder_decoded_andMatrixOutputs_79_2, cs_decoder_decoded_andMatrixOutputs_142_2}; // @[pla.scala:98:70, :114:19]
wire _cs_decoder_decoded_orMatrixOutputs_T_10 = |_cs_decoder_decoded_orMatrixOutputs_T_9; // @[pla.scala:114:{19,36}]
wire [1:0] _GEN_3 = {cs_decoder_decoded_andMatrixOutputs_166_2, cs_decoder_decoded_andMatrixOutputs_65_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_2; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_lo_lo_2 = _GEN_3; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo = _GEN_3; // @[pla.scala:114:19]
wire [1:0] _GEN_4 = {cs_decoder_decoded_andMatrixOutputs_82_2, cs_decoder_decoded_andMatrixOutputs_16_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_2; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_2 = _GEN_4; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_lo_hi_lo = _GEN_4; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_8; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_8 = _GEN_4; // @[pla.scala:114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_3 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_53_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_3 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_3, cs_decoder_decoded_orMatrixOutputs_lo_lo_2}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_2 = {cs_decoder_decoded_andMatrixOutputs_12_2, cs_decoder_decoded_andMatrixOutputs_144_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_2 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_46_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] _GEN_5 = {cs_decoder_decoded_andMatrixOutputs_56_2, cs_decoder_decoded_andMatrixOutputs_71_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_2; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_2 = _GEN_5; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_9; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_9 = _GEN_5; // @[pla.scala:114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_3 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_170_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] cs_decoder_decoded_orMatrixOutputs_hi_3 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_3, cs_decoder_decoded_orMatrixOutputs_hi_lo_2}; // @[pla.scala:114:19]
wire [10:0] _cs_decoder_decoded_orMatrixOutputs_T_11 = {cs_decoder_decoded_orMatrixOutputs_hi_3, cs_decoder_decoded_orMatrixOutputs_lo_3}; // @[pla.scala:114:19]
wire _cs_decoder_decoded_orMatrixOutputs_T_12 = |_cs_decoder_decoded_orMatrixOutputs_T_11; // @[pla.scala:114:{19,36}]
wire [1:0] _GEN_6 = {cs_decoder_decoded_andMatrixOutputs_53_2, cs_decoder_decoded_andMatrixOutputs_166_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_lo_lo_hi = _GEN_6; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_4; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_4 = _GEN_6; // @[pla.scala:114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_3 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi, cs_decoder_decoded_andMatrixOutputs_65_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_3 = {cs_decoder_decoded_andMatrixOutputs_139_2, cs_decoder_decoded_andMatrixOutputs_46_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_4 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_3, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo}; // @[pla.scala:114:19]
wire [6:0] cs_decoder_decoded_orMatrixOutputs_lo_4 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_4, cs_decoder_decoded_orMatrixOutputs_lo_lo_3}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo = {cs_decoder_decoded_andMatrixOutputs_12_2, cs_decoder_decoded_andMatrixOutputs_174_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] _GEN_7 = {cs_decoder_decoded_andMatrixOutputs_34_2, cs_decoder_decoded_andMatrixOutputs_170_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_3; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_3 = _GEN_7; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_1; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_1 = _GEN_7; // @[pla.scala:114:19]
wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_3 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_3, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo = {cs_decoder_decoded_andMatrixOutputs_124_2, cs_decoder_decoded_andMatrixOutputs_71_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] _GEN_8 = {cs_decoder_decoded_andMatrixOutputs_77_2, cs_decoder_decoded_andMatrixOutputs_8_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_3; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_3 = _GEN_8; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi = _GEN_8; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi = _GEN_8; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_4; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_4 = _GEN_8; // @[pla.scala:114:19]
wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_4 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_3, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo}; // @[pla.scala:114:19]
wire [7:0] cs_decoder_decoded_orMatrixOutputs_hi_4 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_4, cs_decoder_decoded_orMatrixOutputs_hi_lo_3}; // @[pla.scala:114:19]
wire [14:0] _cs_decoder_decoded_orMatrixOutputs_T_13 = {cs_decoder_decoded_orMatrixOutputs_hi_4, cs_decoder_decoded_orMatrixOutputs_lo_4}; // @[pla.scala:114:19]
wire _cs_decoder_decoded_orMatrixOutputs_T_14 = |_cs_decoder_decoded_orMatrixOutputs_T_13; // @[pla.scala:114:{19,36}]
wire [1:0] _GEN_9 = {cs_decoder_decoded_andMatrixOutputs_84_2, cs_decoder_decoded_andMatrixOutputs_8_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_5; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_hi_5 = _GEN_9; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_10; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_hi_10 = _GEN_9; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_10; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_10 = _GEN_9; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_2; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_2 = _GEN_9; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_18; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_hi_hi_18 = _GEN_9; // @[pla.scala:114:19]
wire [2:0] _cs_decoder_decoded_orMatrixOutputs_T_15 = {cs_decoder_decoded_orMatrixOutputs_hi_5, cs_decoder_decoded_andMatrixOutputs_124_2}; // @[pla.scala:98:70, :114:19]
wire _cs_decoder_decoded_orMatrixOutputs_T_16 = |_cs_decoder_decoded_orMatrixOutputs_T_15; // @[pla.scala:114:{19,36}]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_5 = {cs_decoder_decoded_andMatrixOutputs_47_2, cs_decoder_decoded_andMatrixOutputs_58_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_6 = {cs_decoder_decoded_andMatrixOutputs_110_2, cs_decoder_decoded_andMatrixOutputs_160_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] _cs_decoder_decoded_orMatrixOutputs_T_17 = {cs_decoder_decoded_orMatrixOutputs_hi_6, cs_decoder_decoded_orMatrixOutputs_lo_5}; // @[pla.scala:114:19]
wire _cs_decoder_decoded_orMatrixOutputs_T_18 = |_cs_decoder_decoded_orMatrixOutputs_T_17; // @[pla.scala:114:{19,36}]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_7 = {cs_decoder_decoded_andMatrixOutputs_121_2, cs_decoder_decoded_andMatrixOutputs_47_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] _cs_decoder_decoded_orMatrixOutputs_T_19 = {cs_decoder_decoded_orMatrixOutputs_hi_7, cs_decoder_decoded_andMatrixOutputs_44_2}; // @[pla.scala:98:70, :114:19]
wire _cs_decoder_decoded_orMatrixOutputs_T_20 = |_cs_decoder_decoded_orMatrixOutputs_T_19; // @[pla.scala:114:{19,36}]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_6 = {cs_decoder_decoded_andMatrixOutputs_60_2, cs_decoder_decoded_andMatrixOutputs_155_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_8 = {cs_decoder_decoded_andMatrixOutputs_100_2, cs_decoder_decoded_andMatrixOutputs_121_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] _cs_decoder_decoded_orMatrixOutputs_T_21 = {cs_decoder_decoded_orMatrixOutputs_hi_8, cs_decoder_decoded_orMatrixOutputs_lo_6}; // @[pla.scala:114:19]
wire _cs_decoder_decoded_orMatrixOutputs_T_22 = |_cs_decoder_decoded_orMatrixOutputs_T_21; // @[pla.scala:114:{19,36}]
wire [1:0] _GEN_10 = {cs_decoder_decoded_andMatrixOutputs_15_2, cs_decoder_decoded_andMatrixOutputs_100_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] _cs_decoder_decoded_orMatrixOutputs_T_27; // @[pla.scala:114:19]
assign _cs_decoder_decoded_orMatrixOutputs_T_27 = _GEN_10; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_7; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_lo_7 = _GEN_10; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_12; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_lo_hi_12 = _GEN_10; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_16; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_lo_hi_16 = _GEN_10; // @[pla.scala:114:19]
wire _cs_decoder_decoded_orMatrixOutputs_T_28 = |_cs_decoder_decoded_orMatrixOutputs_T_27; // @[pla.scala:114:{19,36}]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_5 = {cs_decoder_decoded_andMatrixOutputs_85_2, cs_decoder_decoded_andMatrixOutputs_110_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_9 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_5, cs_decoder_decoded_andMatrixOutputs_160_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] _cs_decoder_decoded_orMatrixOutputs_T_29 = {cs_decoder_decoded_orMatrixOutputs_hi_9, cs_decoder_decoded_orMatrixOutputs_lo_7}; // @[pla.scala:114:19]
wire _cs_decoder_decoded_orMatrixOutputs_T_30 = |_cs_decoder_decoded_orMatrixOutputs_T_29; // @[pla.scala:114:{19,36}]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_8 = {cs_decoder_decoded_andMatrixOutputs_40_2, cs_decoder_decoded_andMatrixOutputs_121_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] _cs_decoder_decoded_orMatrixOutputs_T_31 = {cs_decoder_decoded_orMatrixOutputs_hi_10, cs_decoder_decoded_orMatrixOutputs_lo_8}; // @[pla.scala:114:19]
wire _cs_decoder_decoded_orMatrixOutputs_T_32 = |_cs_decoder_decoded_orMatrixOutputs_T_31; // @[pla.scala:114:{19,36}]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_11 = {cs_decoder_decoded_andMatrixOutputs_34_2, cs_decoder_decoded_andMatrixOutputs_110_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] _cs_decoder_decoded_orMatrixOutputs_T_33 = {cs_decoder_decoded_orMatrixOutputs_hi_11, cs_decoder_decoded_andMatrixOutputs_160_2}; // @[pla.scala:98:70, :114:19]
wire _cs_decoder_decoded_orMatrixOutputs_T_34 = |_cs_decoder_decoded_orMatrixOutputs_T_33; // @[pla.scala:114:{19,36}]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_12 = {cs_decoder_decoded_andMatrixOutputs_34_2, cs_decoder_decoded_andMatrixOutputs_79_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] _cs_decoder_decoded_orMatrixOutputs_T_35 = {cs_decoder_decoded_orMatrixOutputs_hi_12, cs_decoder_decoded_andMatrixOutputs_142_2}; // @[pla.scala:98:70, :114:19]
wire _cs_decoder_decoded_orMatrixOutputs_T_36 = |_cs_decoder_decoded_orMatrixOutputs_T_35; // @[pla.scala:114:{19,36}]
wire [1:0] _GEN_11 = {cs_decoder_decoded_andMatrixOutputs_4_2, cs_decoder_decoded_andMatrixOutputs_123_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_5; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_lo_hi_5 = _GEN_11; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_9; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_9 = _GEN_11; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_9; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_9 = _GEN_11; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_18; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_18 = _GEN_11; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_1; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_1 = _GEN_11; // @[pla.scala:114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_9 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_5, cs_decoder_decoded_andMatrixOutputs_88_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] _GEN_12 = {cs_decoder_decoded_andMatrixOutputs_162_2, cs_decoder_decoded_andMatrixOutputs_19_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_6; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_hi_hi_6 = _GEN_12; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_5; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_5 = _GEN_12; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_9; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_9 = _GEN_12; // @[pla.scala:114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_13 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_101_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] _cs_decoder_decoded_orMatrixOutputs_T_39 = {cs_decoder_decoded_orMatrixOutputs_hi_13, cs_decoder_decoded_orMatrixOutputs_lo_9}; // @[pla.scala:114:19]
wire _cs_decoder_decoded_orMatrixOutputs_T_40 = |_cs_decoder_decoded_orMatrixOutputs_T_39; // @[pla.scala:114:{19,36}]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi = {cs_decoder_decoded_andMatrixOutputs_59_2, cs_decoder_decoded_andMatrixOutputs_31_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi, cs_decoder_decoded_andMatrixOutputs_90_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] _GEN_13 = {cs_decoder_decoded_andMatrixOutputs_159_2, cs_decoder_decoded_andMatrixOutputs_99_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi = _GEN_13; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo = _GEN_13; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_10; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_10 = _GEN_13; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_2; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_2 = _GEN_13; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_10; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_10 = _GEN_13; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_19; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_19 = _GEN_13; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_5; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_5 = _GEN_13; // @[pla.scala:114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_1 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_120_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_4 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_1, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo}; // @[pla.scala:114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_1 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi, cs_decoder_decoded_andMatrixOutputs_140_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] _GEN_14 = {cs_decoder_decoded_andMatrixOutputs_137_2, cs_decoder_decoded_andMatrixOutputs_53_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi = _GEN_14; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_1; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_1 = _GEN_14; // @[pla.scala:114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_4 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_21_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_6 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_4, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_1}; // @[pla.scala:114:19]
wire [11:0] cs_decoder_decoded_orMatrixOutputs_lo_10 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_6, cs_decoder_decoded_orMatrixOutputs_lo_lo_4}; // @[pla.scala:114:19]
wire [1:0] _GEN_15 = {cs_decoder_decoded_andMatrixOutputs_167_2, cs_decoder_decoded_andMatrixOutputs_40_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi = _GEN_15; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_1; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_1 = _GEN_15; // @[pla.scala:114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_1 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi, cs_decoder_decoded_andMatrixOutputs_16_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi = {cs_decoder_decoded_andMatrixOutputs_43_2, cs_decoder_decoded_andMatrixOutputs_46_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_4 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_26_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_4 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_4, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_1}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi = {cs_decoder_decoded_andMatrixOutputs_34_2, cs_decoder_decoded_andMatrixOutputs_174_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_1 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi, cs_decoder_decoded_andMatrixOutputs_139_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] _GEN_16 = {cs_decoder_decoded_andMatrixOutputs_102_2, cs_decoder_decoded_andMatrixOutputs_71_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo = _GEN_16; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi = _GEN_16; // @[pla.scala:114:19]
wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_4 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo}; // @[pla.scala:114:19]
wire [6:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_7 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_4, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_1}; // @[pla.scala:114:19]
wire [12:0] cs_decoder_decoded_orMatrixOutputs_hi_14 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_7, cs_decoder_decoded_orMatrixOutputs_hi_lo_4}; // @[pla.scala:114:19]
wire [24:0] _cs_decoder_decoded_orMatrixOutputs_T_41 = {cs_decoder_decoded_orMatrixOutputs_hi_14, cs_decoder_decoded_orMatrixOutputs_lo_10}; // @[pla.scala:114:19]
wire _cs_decoder_decoded_orMatrixOutputs_T_42 = |_cs_decoder_decoded_orMatrixOutputs_T_41; // @[pla.scala:114:{19,36}]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_2 = {cs_decoder_decoded_andMatrixOutputs_120_2, cs_decoder_decoded_andMatrixOutputs_83_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_5 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_32_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] _GEN_17 = {cs_decoder_decoded_andMatrixOutputs_88_2, cs_decoder_decoded_andMatrixOutputs_159_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_5; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_5 = _GEN_17; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_3; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_3 = _GEN_17; // @[pla.scala:114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_7 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_5, cs_decoder_decoded_andMatrixOutputs_99_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] cs_decoder_decoded_orMatrixOutputs_lo_11 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_7, cs_decoder_decoded_orMatrixOutputs_lo_lo_5}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_5 = {cs_decoder_decoded_andMatrixOutputs_2_2, cs_decoder_decoded_andMatrixOutputs_4_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_5 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_5, cs_decoder_decoded_andMatrixOutputs_123_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_8 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_5, cs_decoder_decoded_andMatrixOutputs_68_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] cs_decoder_decoded_orMatrixOutputs_hi_15 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_8, cs_decoder_decoded_orMatrixOutputs_hi_lo_5}; // @[pla.scala:114:19]
wire [11:0] _cs_decoder_decoded_orMatrixOutputs_T_43 = {cs_decoder_decoded_orMatrixOutputs_hi_15, cs_decoder_decoded_orMatrixOutputs_lo_11}; // @[pla.scala:114:19]
wire _cs_decoder_decoded_orMatrixOutputs_T_44 = |_cs_decoder_decoded_orMatrixOutputs_T_43; // @[pla.scala:114:{19,36}]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_6 = {cs_decoder_decoded_andMatrixOutputs_140_2, cs_decoder_decoded_andMatrixOutputs_59_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_8 = {cs_decoder_decoded_andMatrixOutputs_2_2, cs_decoder_decoded_andMatrixOutputs_45_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_12 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_8, cs_decoder_decoded_orMatrixOutputs_lo_lo_6}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_6 = {cs_decoder_decoded_andMatrixOutputs_43_2, cs_decoder_decoded_andMatrixOutputs_68_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_102_2, cs_decoder_decoded_andMatrixOutputs_34_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_9 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_139_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi_16 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_9, cs_decoder_decoded_orMatrixOutputs_hi_lo_6}; // @[pla.scala:114:19]
wire [8:0] _cs_decoder_decoded_orMatrixOutputs_T_45 = {cs_decoder_decoded_orMatrixOutputs_hi_16, cs_decoder_decoded_orMatrixOutputs_lo_12}; // @[pla.scala:114:19]
wire _cs_decoder_decoded_orMatrixOutputs_T_46 = |_cs_decoder_decoded_orMatrixOutputs_T_45; // @[pla.scala:114:{19,36}]
wire [1:0] _GEN_18 = {cs_decoder_decoded_andMatrixOutputs_138_2, cs_decoder_decoded_andMatrixOutputs_51_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_7; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_lo_lo_7 = _GEN_18; // @[pla.scala:114:19]
wire [1:0] _cs_decoder_decoded_orMatrixOutputs_T_66; // @[pla.scala:114:19]
assign _cs_decoder_decoded_orMatrixOutputs_T_66 = _GEN_18; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_0_2, cs_decoder_decoded_andMatrixOutputs_13_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_9 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_120_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_13 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_9, cs_decoder_decoded_orMatrixOutputs_lo_lo_7}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_7 = {cs_decoder_decoded_andMatrixOutputs_88_2, cs_decoder_decoded_andMatrixOutputs_37_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] _GEN_19 = {cs_decoder_decoded_andMatrixOutputs_1_2, cs_decoder_decoded_andMatrixOutputs_19_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_7; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_7 = _GEN_19; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo = _GEN_19; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_4; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_4 = _GEN_19; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_12; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_12 = _GEN_19; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_21; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_21 = _GEN_19; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_4; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_4 = _GEN_19; // @[pla.scala:114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_10 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_69_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi_17 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_10, cs_decoder_decoded_orMatrixOutputs_hi_lo_7}; // @[pla.scala:114:19]
wire [9:0] _cs_decoder_decoded_orMatrixOutputs_T_47 = {cs_decoder_decoded_orMatrixOutputs_hi_17, cs_decoder_decoded_orMatrixOutputs_lo_13}; // @[pla.scala:114:19]
wire _cs_decoder_decoded_orMatrixOutputs_T_48 = |_cs_decoder_decoded_orMatrixOutputs_T_47; // @[pla.scala:114:{19,36}]
wire [1:0] _GEN_20 = {cs_decoder_decoded_andMatrixOutputs_86_2, cs_decoder_decoded_andMatrixOutputs_32_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo = _GEN_20; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_4; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_4 = _GEN_20; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_1 = {cs_decoder_decoded_andMatrixOutputs_120_2, cs_decoder_decoded_andMatrixOutputs_90_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_1 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_1, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_123_2, cs_decoder_decoded_andMatrixOutputs_88_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_3 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_1, cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo}; // @[pla.scala:114:19]
wire [7:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_8 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_3, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_1}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo = {cs_decoder_decoded_andMatrixOutputs_50_2, cs_decoder_decoded_andMatrixOutputs_4_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_1 = {cs_decoder_decoded_andMatrixOutputs_6_2, cs_decoder_decoded_andMatrixOutputs_100_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_2 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_1, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo}; // @[pla.scala:114:19]
wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_7 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_1, cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo}; // @[pla.scala:114:19]
wire [7:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_10 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_7, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_2}; // @[pla.scala:114:19]
wire [15:0] cs_decoder_decoded_orMatrixOutputs_lo_14 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_10, cs_decoder_decoded_orMatrixOutputs_lo_lo_8}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo = {cs_decoder_decoded_andMatrixOutputs_16_2, cs_decoder_decoded_andMatrixOutputs_15_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_2 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_1, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo}; // @[pla.scala:114:19]
wire [1:0] _GEN_21 = {cs_decoder_decoded_andMatrixOutputs_108_2, cs_decoder_decoded_andMatrixOutputs_82_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo = _GEN_21; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_5; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_5 = _GEN_21; // @[pla.scala:114:19]
wire [1:0] _GEN_22 = {cs_decoder_decoded_andMatrixOutputs_174_2, cs_decoder_decoded_andMatrixOutputs_139_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_1; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_1 = _GEN_22; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_4; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_4 = _GEN_22; // @[pla.scala:114:19]
wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_6 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_1, cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo}; // @[pla.scala:114:19]
wire [7:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_8 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_6, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_2}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_1 = {cs_decoder_decoded_andMatrixOutputs_5_2, cs_decoder_decoded_andMatrixOutputs_75_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_2 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_1, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo}; // @[pla.scala:114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_1 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_71_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_8 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_1, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_1}; // @[pla.scala:114:19]
wire [8:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_11 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_8, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_2}; // @[pla.scala:114:19]
wire [16:0] cs_decoder_decoded_orMatrixOutputs_hi_18 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_11, cs_decoder_decoded_orMatrixOutputs_hi_lo_8}; // @[pla.scala:114:19]
wire [32:0] _cs_decoder_decoded_orMatrixOutputs_T_49 = {cs_decoder_decoded_orMatrixOutputs_hi_18, cs_decoder_decoded_orMatrixOutputs_lo_14}; // @[pla.scala:114:19]
wire _cs_decoder_decoded_orMatrixOutputs_T_50 = |_cs_decoder_decoded_orMatrixOutputs_T_49; // @[pla.scala:114:{19,36}]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_9 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_65_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_11 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_8, cs_decoder_decoded_andMatrixOutputs_142_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] cs_decoder_decoded_orMatrixOutputs_lo_15 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_11, cs_decoder_decoded_orMatrixOutputs_lo_lo_9}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_7 = {cs_decoder_decoded_andMatrixOutputs_144_2, cs_decoder_decoded_andMatrixOutputs_79_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_9 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_7, cs_decoder_decoded_andMatrixOutputs_46_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_3 = {cs_decoder_decoded_andMatrixOutputs_170_2, cs_decoder_decoded_andMatrixOutputs_12_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_12 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_9, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_3}; // @[pla.scala:114:19]
wire [6:0] cs_decoder_decoded_orMatrixOutputs_hi_19 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_12, cs_decoder_decoded_orMatrixOutputs_hi_lo_9}; // @[pla.scala:114:19]
wire [12:0] _cs_decoder_decoded_orMatrixOutputs_T_51 = {cs_decoder_decoded_orMatrixOutputs_hi_19, cs_decoder_decoded_orMatrixOutputs_lo_15}; // @[pla.scala:114:19]
wire _cs_decoder_decoded_orMatrixOutputs_T_52 = |_cs_decoder_decoded_orMatrixOutputs_T_51; // @[pla.scala:114:{19,36}]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_20 = {cs_decoder_decoded_andMatrixOutputs_163_2, cs_decoder_decoded_andMatrixOutputs_174_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] _cs_decoder_decoded_orMatrixOutputs_T_53 = {cs_decoder_decoded_orMatrixOutputs_hi_20, cs_decoder_decoded_andMatrixOutputs_139_2}; // @[pla.scala:98:70, :114:19]
wire _cs_decoder_decoded_orMatrixOutputs_T_54 = |_cs_decoder_decoded_orMatrixOutputs_T_53; // @[pla.scala:114:{19,36}]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_10 = {cs_decoder_decoded_andMatrixOutputs_121_2, cs_decoder_decoded_andMatrixOutputs_14_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_16 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_12, cs_decoder_decoded_orMatrixOutputs_lo_lo_10}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_10 = {cs_decoder_decoded_andMatrixOutputs_85_2, cs_decoder_decoded_andMatrixOutputs_125_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_13 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_10, cs_decoder_decoded_andMatrixOutputs_29_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi_21 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_13, cs_decoder_decoded_orMatrixOutputs_hi_lo_10}; // @[pla.scala:114:19]
wire [8:0] _cs_decoder_decoded_orMatrixOutputs_T_55 = {cs_decoder_decoded_orMatrixOutputs_hi_21, cs_decoder_decoded_orMatrixOutputs_lo_16}; // @[pla.scala:114:19]
wire _cs_decoder_decoded_orMatrixOutputs_T_56 = |_cs_decoder_decoded_orMatrixOutputs_T_55; // @[pla.scala:114:{19,36}]
wire [1:0] _cs_decoder_decoded_orMatrixOutputs_T_57 = {cs_decoder_decoded_andMatrixOutputs_148_2, cs_decoder_decoded_andMatrixOutputs_89_2}; // @[pla.scala:98:70, :114:19]
wire _cs_decoder_decoded_orMatrixOutputs_T_58 = |_cs_decoder_decoded_orMatrixOutputs_T_57; // @[pla.scala:114:{19,36}]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_17 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_13, cs_decoder_decoded_andMatrixOutputs_59_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_22 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_14, cs_decoder_decoded_andMatrixOutputs_137_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] _cs_decoder_decoded_orMatrixOutputs_T_60 = {cs_decoder_decoded_orMatrixOutputs_hi_22, cs_decoder_decoded_orMatrixOutputs_lo_17}; // @[pla.scala:114:19]
wire _cs_decoder_decoded_orMatrixOutputs_T_61 = |_cs_decoder_decoded_orMatrixOutputs_T_60; // @[pla.scala:114:{19,36}]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_14 = {cs_decoder_decoded_andMatrixOutputs_37_2, cs_decoder_decoded_andMatrixOutputs_0_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_18 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_14, cs_decoder_decoded_andMatrixOutputs_13_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_11 = {cs_decoder_decoded_andMatrixOutputs_168_2, cs_decoder_decoded_andMatrixOutputs_88_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_15 = {cs_decoder_decoded_andMatrixOutputs_162_2, cs_decoder_decoded_andMatrixOutputs_153_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_23 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_15, cs_decoder_decoded_orMatrixOutputs_hi_lo_11}; // @[pla.scala:114:19]
wire [6:0] _cs_decoder_decoded_orMatrixOutputs_T_62 = {cs_decoder_decoded_orMatrixOutputs_hi_23, cs_decoder_decoded_orMatrixOutputs_lo_18}; // @[pla.scala:114:19]
wire _cs_decoder_decoded_orMatrixOutputs_T_63 = |_cs_decoder_decoded_orMatrixOutputs_T_62; // @[pla.scala:114:{19,36}]
wire [1:0] _GEN_23 = {cs_decoder_decoded_andMatrixOutputs_78_2, cs_decoder_decoded_andMatrixOutputs_120_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] _cs_decoder_decoded_orMatrixOutputs_T_64; // @[pla.scala:114:19]
assign _cs_decoder_decoded_orMatrixOutputs_T_64 = _GEN_23; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_6; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_6 = _GEN_23; // @[pla.scala:114:19]
wire _cs_decoder_decoded_orMatrixOutputs_T_65 = |_cs_decoder_decoded_orMatrixOutputs_T_64; // @[pla.scala:114:{19,36}]
wire _cs_decoder_decoded_orMatrixOutputs_T_67 = |_cs_decoder_decoded_orMatrixOutputs_T_66; // @[pla.scala:114:{19,36}]
wire [1:0] _GEN_24 = {cs_decoder_decoded_andMatrixOutputs_83_2, cs_decoder_decoded_andMatrixOutputs_32_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_19; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_lo_19 = _GEN_24; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_2; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_2 = _GEN_24; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_13; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_lo_lo_13 = _GEN_24; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_2; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_2 = _GEN_24; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_16 = {cs_decoder_decoded_andMatrixOutputs_101_2, cs_decoder_decoded_andMatrixOutputs_149_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_24 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_16, cs_decoder_decoded_andMatrixOutputs_136_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] _cs_decoder_decoded_orMatrixOutputs_T_68 = {cs_decoder_decoded_orMatrixOutputs_hi_24, cs_decoder_decoded_orMatrixOutputs_lo_19}; // @[pla.scala:114:19]
wire _cs_decoder_decoded_orMatrixOutputs_T_69 = |_cs_decoder_decoded_orMatrixOutputs_T_68; // @[pla.scala:114:{19,36}]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_5 = {cs_decoder_decoded_andMatrixOutputs_99_2, cs_decoder_decoded_andMatrixOutputs_120_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_11 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_5, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_2}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_2 = {cs_decoder_decoded_andMatrixOutputs_92_2, cs_decoder_decoded_andMatrixOutputs_4_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_9 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_123_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_15 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_9, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_3}; // @[pla.scala:114:19]
wire [8:0] cs_decoder_decoded_orMatrixOutputs_lo_20 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_15, cs_decoder_decoded_orMatrixOutputs_lo_lo_11}; // @[pla.scala:114:19]
wire [1:0] _GEN_25 = {cs_decoder_decoded_andMatrixOutputs_100_2, cs_decoder_decoded_andMatrixOutputs_50_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_3; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_3 = _GEN_25; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi = _GEN_25; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_8 = {cs_decoder_decoded_andMatrixOutputs_125_2, cs_decoder_decoded_andMatrixOutputs_15_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_12 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_8, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_3}; // @[pla.scala:114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_11 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_29_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_17 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_11, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_4}; // @[pla.scala:114:19]
wire [8:0] cs_decoder_decoded_orMatrixOutputs_hi_25 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_17, cs_decoder_decoded_orMatrixOutputs_hi_lo_12}; // @[pla.scala:114:19]
wire [17:0] _cs_decoder_decoded_orMatrixOutputs_T_70 = {cs_decoder_decoded_orMatrixOutputs_hi_25, cs_decoder_decoded_orMatrixOutputs_lo_20}; // @[pla.scala:114:19]
wire _cs_decoder_decoded_orMatrixOutputs_T_71 = |_cs_decoder_decoded_orMatrixOutputs_T_70; // @[pla.scala:114:{19,36}]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_12 = {cs_decoder_decoded_andMatrixOutputs_50_2, cs_decoder_decoded_andMatrixOutputs_92_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_21 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_16, cs_decoder_decoded_orMatrixOutputs_lo_lo_12}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_13 = {cs_decoder_decoded_andMatrixOutputs_29_2, cs_decoder_decoded_andMatrixOutputs_125_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_26 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_18, cs_decoder_decoded_orMatrixOutputs_hi_lo_13}; // @[pla.scala:114:19]
wire [7:0] _cs_decoder_decoded_orMatrixOutputs_T_72 = {cs_decoder_decoded_orMatrixOutputs_hi_26, cs_decoder_decoded_orMatrixOutputs_lo_21}; // @[pla.scala:114:19]
wire _cs_decoder_decoded_orMatrixOutputs_T_73 = |_cs_decoder_decoded_orMatrixOutputs_T_72; // @[pla.scala:114:{19,36}]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_17 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_10, cs_decoder_decoded_andMatrixOutputs_120_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_22 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_17, cs_decoder_decoded_orMatrixOutputs_lo_lo_13}; // @[pla.scala:114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_14 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_9, cs_decoder_decoded_andMatrixOutputs_88_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_19 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_12, cs_decoder_decoded_andMatrixOutputs_101_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] cs_decoder_decoded_orMatrixOutputs_hi_27 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_19, cs_decoder_decoded_orMatrixOutputs_hi_lo_14}; // @[pla.scala:114:19]
wire [10:0] _cs_decoder_decoded_orMatrixOutputs_T_74 = {cs_decoder_decoded_orMatrixOutputs_hi_27, cs_decoder_decoded_orMatrixOutputs_lo_22}; // @[pla.scala:114:19]
wire _cs_decoder_decoded_orMatrixOutputs_T_75 = |_cs_decoder_decoded_orMatrixOutputs_T_74; // @[pla.scala:114:{19,36}]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_1 = {cs_decoder_decoded_andMatrixOutputs_61_2, cs_decoder_decoded_andMatrixOutputs_36_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_2 = {cs_decoder_decoded_andMatrixOutputs_171_2, cs_decoder_decoded_andMatrixOutputs_103_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_3 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_2, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_1}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_1 = {cs_decoder_decoded_andMatrixOutputs_80_2, cs_decoder_decoded_andMatrixOutputs_99_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi = {cs_decoder_decoded_andMatrixOutputs_62_2, cs_decoder_decoded_andMatrixOutputs_9_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_2 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_64_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_6 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_1}; // @[pla.scala:114:19]
wire [8:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_14 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_6, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_3}; // @[pla.scala:114:19]
wire [1:0] _GEN_26 = {cs_decoder_decoded_andMatrixOutputs_140_2, cs_decoder_decoded_andMatrixOutputs_14_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_1; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_1 = _GEN_26; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_10; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_10 = _GEN_26; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_2 = {cs_decoder_decoded_andMatrixOutputs_121_2, cs_decoder_decoded_andMatrixOutputs_158_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_4 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_2, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_1}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_1 = {cs_decoder_decoded_andMatrixOutputs_100_2, cs_decoder_decoded_andMatrixOutputs_150_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi = {cs_decoder_decoded_andMatrixOutputs_151_2, cs_decoder_decoded_andMatrixOutputs_172_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_3 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_66_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_11 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_3, cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_1}; // @[pla.scala:114:19]
wire [8:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_18 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_11, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_4}; // @[pla.scala:114:19]
wire [17:0] cs_decoder_decoded_orMatrixOutputs_lo_23 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_18, cs_decoder_decoded_orMatrixOutputs_lo_lo_14}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_1 = {cs_decoder_decoded_andMatrixOutputs_91_2, cs_decoder_decoded_andMatrixOutputs_68_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_2 = {cs_decoder_decoded_andMatrixOutputs_54_2, cs_decoder_decoded_andMatrixOutputs_74_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_4 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_2, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_1}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_1 = {cs_decoder_decoded_andMatrixOutputs_15_2, cs_decoder_decoded_andMatrixOutputs_173_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi = {cs_decoder_decoded_andMatrixOutputs_76_2, cs_decoder_decoded_andMatrixOutputs_96_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_2 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_40_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_10 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_1}; // @[pla.scala:114:19]
wire [8:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_15 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_10, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_4}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_1 = {cs_decoder_decoded_andMatrixOutputs_46_2, cs_decoder_decoded_andMatrixOutputs_93_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi = {cs_decoder_decoded_andMatrixOutputs_165_2, cs_decoder_decoded_andMatrixOutputs_141_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_2 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_139_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_5 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_2, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_1}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_2 = {cs_decoder_decoded_andMatrixOutputs_35_2, cs_decoder_decoded_andMatrixOutputs_17_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_8_2, cs_decoder_decoded_andMatrixOutputs_71_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_3 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_163_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_13 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_3, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_2}; // @[pla.scala:114:19]
wire [9:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_20 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_13, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_5}; // @[pla.scala:114:19]
wire [18:0] cs_decoder_decoded_orMatrixOutputs_hi_28 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_20, cs_decoder_decoded_orMatrixOutputs_hi_lo_15}; // @[pla.scala:114:19]
wire [36:0] _cs_decoder_decoded_orMatrixOutputs_T_76 = {cs_decoder_decoded_orMatrixOutputs_hi_28, cs_decoder_decoded_orMatrixOutputs_lo_23}; // @[pla.scala:114:19]
wire _cs_decoder_decoded_orMatrixOutputs_T_77 = |_cs_decoder_decoded_orMatrixOutputs_T_76; // @[pla.scala:114:{19,36}]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_3 = {cs_decoder_decoded_andMatrixOutputs_171_2, cs_decoder_decoded_andMatrixOutputs_59_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_4 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_3, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_2}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_3 = {cs_decoder_decoded_andMatrixOutputs_45_2, cs_decoder_decoded_andMatrixOutputs_7_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_7 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_3, cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_2}; // @[pla.scala:114:19]
wire [7:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_15 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_7, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_4}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_2 = {cs_decoder_decoded_andMatrixOutputs_100_2, cs_decoder_decoded_andMatrixOutputs_119_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_3 = {cs_decoder_decoded_andMatrixOutputs_72_2, cs_decoder_decoded_andMatrixOutputs_133_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_5 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_3, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_2}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_2 = {cs_decoder_decoded_andMatrixOutputs_94_2, cs_decoder_decoded_andMatrixOutputs_2_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_52_2, cs_decoder_decoded_andMatrixOutputs_57_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_4 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_104_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_12 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_4, cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_2}; // @[pla.scala:114:19]
wire [8:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_19 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_12, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_5}; // @[pla.scala:114:19]
wire [16:0] cs_decoder_decoded_orMatrixOutputs_lo_24 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_19, cs_decoder_decoded_orMatrixOutputs_lo_lo_15}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_2 = {cs_decoder_decoded_andMatrixOutputs_20_2, cs_decoder_decoded_andMatrixOutputs_97_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_3 = {cs_decoder_decoded_andMatrixOutputs_160_2, cs_decoder_decoded_andMatrixOutputs_15_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_5 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_3, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_2}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_2 = {cs_decoder_decoded_andMatrixOutputs_41_2, cs_decoder_decoded_andMatrixOutputs_152_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_3 = {cs_decoder_decoded_andMatrixOutputs_10_2, cs_decoder_decoded_andMatrixOutputs_82_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_11 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_3, cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_2}; // @[pla.scala:114:19]
wire [7:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_16 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_11, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_5}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_2 = {cs_decoder_decoded_andMatrixOutputs_174_2, cs_decoder_decoded_andMatrixOutputs_43_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_3 = {cs_decoder_decoded_andMatrixOutputs_105_2, cs_decoder_decoded_andMatrixOutputs_73_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_6 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_3, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_2}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_3 = {cs_decoder_decoded_andMatrixOutputs_110_2, cs_decoder_decoded_andMatrixOutputs_24_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] _GEN_27 = {cs_decoder_decoded_andMatrixOutputs_85_2, cs_decoder_decoded_andMatrixOutputs_163_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_2; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_2 = _GEN_27; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_8; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_8 = _GEN_27; // @[pla.scala:114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_4 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_48_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_14 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_4, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_3}; // @[pla.scala:114:19]
wire [8:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_21 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_14, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_6}; // @[pla.scala:114:19]
wire [16:0] cs_decoder_decoded_orMatrixOutputs_hi_29 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_21, cs_decoder_decoded_orMatrixOutputs_hi_lo_16}; // @[pla.scala:114:19]
wire [33:0] _cs_decoder_decoded_orMatrixOutputs_T_78 = {cs_decoder_decoded_orMatrixOutputs_hi_29, cs_decoder_decoded_orMatrixOutputs_lo_24}; // @[pla.scala:114:19]
wire _cs_decoder_decoded_orMatrixOutputs_T_79 = |_cs_decoder_decoded_orMatrixOutputs_T_78; // @[pla.scala:114:{19,36}]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_4 = {cs_decoder_decoded_andMatrixOutputs_171_2, cs_decoder_decoded_andMatrixOutputs_90_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_5 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_86_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_3 = {cs_decoder_decoded_andMatrixOutputs_78_2, cs_decoder_decoded_andMatrixOutputs_146_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_4 = {cs_decoder_decoded_andMatrixOutputs_132_2, cs_decoder_decoded_andMatrixOutputs_115_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_8 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_4, cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_3}; // @[pla.scala:114:19]
wire [6:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_16 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_8, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_5}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_4 = {cs_decoder_decoded_andMatrixOutputs_116_2, cs_decoder_decoded_andMatrixOutputs_81_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_6 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_161_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_3 = {cs_decoder_decoded_andMatrixOutputs_94_2, cs_decoder_decoded_andMatrixOutputs_148_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_5 = {cs_decoder_decoded_andMatrixOutputs_53_2, cs_decoder_decoded_andMatrixOutputs_52_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_13 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_5, cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_3}; // @[pla.scala:114:19]
wire [6:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_20 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_13, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_6}; // @[pla.scala:114:19]
wire [13:0] cs_decoder_decoded_orMatrixOutputs_lo_25 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_20, cs_decoder_decoded_orMatrixOutputs_lo_lo_16}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_4 = {cs_decoder_decoded_andMatrixOutputs_54_2, cs_decoder_decoded_andMatrixOutputs_128_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_6 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_117_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_3 = {cs_decoder_decoded_andMatrixOutputs_42_2, cs_decoder_decoded_andMatrixOutputs_152_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_12 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_4, cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_3}; // @[pla.scala:114:19]
wire [6:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_17 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_12, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_6}; // @[pla.scala:114:19]
wire [1:0] _GEN_28 = {cs_decoder_decoded_andMatrixOutputs_27_2, cs_decoder_decoded_andMatrixOutputs_122_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_4; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_4 = _GEN_28; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_5; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_5 = _GEN_28; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_7; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_7 = _GEN_28; // @[pla.scala:114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_7 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_25_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_4 = {cs_decoder_decoded_andMatrixOutputs_30_2, cs_decoder_decoded_andMatrixOutputs_28_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_5 = {cs_decoder_decoded_andMatrixOutputs_130_2, cs_decoder_decoded_andMatrixOutputs_34_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_15 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_5, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_4}; // @[pla.scala:114:19]
wire [6:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_22 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_15, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_7}; // @[pla.scala:114:19]
wire [13:0] cs_decoder_decoded_orMatrixOutputs_hi_30 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_22, cs_decoder_decoded_orMatrixOutputs_hi_lo_17}; // @[pla.scala:114:19]
wire [27:0] _cs_decoder_decoded_orMatrixOutputs_T_80 = {cs_decoder_decoded_orMatrixOutputs_hi_30, cs_decoder_decoded_orMatrixOutputs_lo_25}; // @[pla.scala:114:19]
wire _cs_decoder_decoded_orMatrixOutputs_T_81 = |_cs_decoder_decoded_orMatrixOutputs_T_80; // @[pla.scala:114:{19,36}]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_3 = {cs_decoder_decoded_andMatrixOutputs_59_2, cs_decoder_decoded_andMatrixOutputs_90_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_5 = {cs_decoder_decoded_andMatrixOutputs_99_2, cs_decoder_decoded_andMatrixOutputs_109_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_6 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_5, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_3}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_4 = {cs_decoder_decoded_andMatrixOutputs_22_2, cs_decoder_decoded_andMatrixOutputs_159_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_5 = {cs_decoder_decoded_andMatrixOutputs_7_2, cs_decoder_decoded_andMatrixOutputs_37_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_9 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_5, cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_4}; // @[pla.scala:114:19]
wire [7:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_17 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_9, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_6}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_5 = {cs_decoder_decoded_andMatrixOutputs_129_2, cs_decoder_decoded_andMatrixOutputs_49_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_7 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_5, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_3}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_4 = {cs_decoder_decoded_andMatrixOutputs_66_2, cs_decoder_decoded_andMatrixOutputs_63_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_131_2, cs_decoder_decoded_andMatrixOutputs_143_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_14 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_6, cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_4}; // @[pla.scala:114:19]
wire [7:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_21 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_14, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_7}; // @[pla.scala:114:19]
wire [15:0] cs_decoder_decoded_orMatrixOutputs_lo_26 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_21, cs_decoder_decoded_orMatrixOutputs_lo_lo_17}; // @[pla.scala:114:19]
wire [1:0] _GEN_29 = {cs_decoder_decoded_andMatrixOutputs_142_2, cs_decoder_decoded_andMatrixOutputs_53_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_3; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_3 = _GEN_29; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_2; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_2 = _GEN_29; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_5 = {cs_decoder_decoded_andMatrixOutputs_54_2, cs_decoder_decoded_andMatrixOutputs_145_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_7 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_5, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_3}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_4 = {cs_decoder_decoded_andMatrixOutputs_11_2, cs_decoder_decoded_andMatrixOutputs_112_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_5 = {cs_decoder_decoded_andMatrixOutputs_46_2, cs_decoder_decoded_andMatrixOutputs_42_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_13 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_5, cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_4}; // @[pla.scala:114:19]
wire [7:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_18 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_13, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_7}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_3 = {cs_decoder_decoded_andMatrixOutputs_79_2, cs_decoder_decoded_andMatrixOutputs_43_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_8 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_5, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_3}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_5 = {cs_decoder_decoded_andMatrixOutputs_28_2, cs_decoder_decoded_andMatrixOutputs_126_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_3 = {cs_decoder_decoded_andMatrixOutputs_85_2, cs_decoder_decoded_andMatrixOutputs_48_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_6 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_3, cs_decoder_decoded_andMatrixOutputs_30_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_16 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_6, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_5}; // @[pla.scala:114:19]
wire [8:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_23 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_16, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_8}; // @[pla.scala:114:19]
wire [16:0] cs_decoder_decoded_orMatrixOutputs_hi_31 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_23, cs_decoder_decoded_orMatrixOutputs_hi_lo_18}; // @[pla.scala:114:19]
wire [32:0] _cs_decoder_decoded_orMatrixOutputs_T_82 = {cs_decoder_decoded_orMatrixOutputs_hi_31, cs_decoder_decoded_orMatrixOutputs_lo_26}; // @[pla.scala:114:19]
wire _cs_decoder_decoded_orMatrixOutputs_T_83 = |_cs_decoder_decoded_orMatrixOutputs_T_82; // @[pla.scala:114:{19,36}]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_7 = {cs_decoder_decoded_andMatrixOutputs_136_2, cs_decoder_decoded_andMatrixOutputs_164_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_146_2, cs_decoder_decoded_andMatrixOutputs_113_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_10 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_149_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_18 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_10, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_7}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_8 = {cs_decoder_decoded_andMatrixOutputs_154_2, cs_decoder_decoded_andMatrixOutputs_66_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_7 = {cs_decoder_decoded_andMatrixOutputs_65_2, cs_decoder_decoded_andMatrixOutputs_57_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_15 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_156_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_22 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_15, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_8}; // @[pla.scala:114:19]
wire [9:0] cs_decoder_decoded_orMatrixOutputs_lo_27 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_22, cs_decoder_decoded_orMatrixOutputs_lo_lo_18}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_8 = {cs_decoder_decoded_andMatrixOutputs_142_2, cs_decoder_decoded_andMatrixOutputs_166_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_23_2, cs_decoder_decoded_andMatrixOutputs_54_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_14 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_134_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_19 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_14, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_8}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_6 = {cs_decoder_decoded_andMatrixOutputs_168_2, cs_decoder_decoded_andMatrixOutputs_79_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_9 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_6, cs_decoder_decoded_andMatrixOutputs_11_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_17 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_153_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_24 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_17, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_9}; // @[pla.scala:114:19]
wire [10:0] cs_decoder_decoded_orMatrixOutputs_hi_32 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_24, cs_decoder_decoded_orMatrixOutputs_hi_lo_19}; // @[pla.scala:114:19]
wire [20:0] _cs_decoder_decoded_orMatrixOutputs_T_84 = {cs_decoder_decoded_orMatrixOutputs_hi_32, cs_decoder_decoded_orMatrixOutputs_lo_27}; // @[pla.scala:114:19]
wire _cs_decoder_decoded_orMatrixOutputs_T_85 = |_cs_decoder_decoded_orMatrixOutputs_T_84; // @[pla.scala:114:{19,36}]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_8 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_6, cs_decoder_decoded_andMatrixOutputs_59_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_11 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_14_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_19 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_11, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_8}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_6 = {cs_decoder_decoded_andMatrixOutputs_55_2, cs_decoder_decoded_andMatrixOutputs_66_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_9 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_6, cs_decoder_decoded_andMatrixOutputs_63_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_8 = {cs_decoder_decoded_andMatrixOutputs_2_2, cs_decoder_decoded_andMatrixOutputs_156_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_16 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_8, cs_decoder_decoded_andMatrixOutputs_154_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_23 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_16, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_9}; // @[pla.scala:114:19]
wire [11:0] cs_decoder_decoded_orMatrixOutputs_lo_28 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_23, cs_decoder_decoded_orMatrixOutputs_lo_lo_19}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_6 = {cs_decoder_decoded_andMatrixOutputs_157_2, cs_decoder_decoded_andMatrixOutputs_166_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_9 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_6, cs_decoder_decoded_andMatrixOutputs_68_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_7 = {cs_decoder_decoded_andMatrixOutputs_139_2, cs_decoder_decoded_andMatrixOutputs_43_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_15 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_82_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_20 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_15, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_9}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_7 = {cs_decoder_decoded_andMatrixOutputs_28_2, cs_decoder_decoded_andMatrixOutputs_38_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_10 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_7, cs_decoder_decoded_andMatrixOutputs_174_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_18 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_8, cs_decoder_decoded_andMatrixOutputs_48_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_25 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_18, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_10}; // @[pla.scala:114:19]
wire [11:0] cs_decoder_decoded_orMatrixOutputs_hi_33 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_25, cs_decoder_decoded_orMatrixOutputs_hi_lo_20}; // @[pla.scala:114:19]
wire [23:0] _cs_decoder_decoded_orMatrixOutputs_T_86 = {cs_decoder_decoded_orMatrixOutputs_hi_33, cs_decoder_decoded_orMatrixOutputs_lo_28}; // @[pla.scala:114:19]
wire _cs_decoder_decoded_orMatrixOutputs_T_87 = |_cs_decoder_decoded_orMatrixOutputs_T_86; // @[pla.scala:114:{19,36}]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_9 = {cs_decoder_decoded_andMatrixOutputs_31_2, cs_decoder_decoded_andMatrixOutputs_90_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_12 = {cs_decoder_decoded_andMatrixOutputs_120_2, cs_decoder_decoded_andMatrixOutputs_59_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_20 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_12, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_9}; // @[pla.scala:114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_17 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_9, cs_decoder_decoded_andMatrixOutputs_88_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_24 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_17, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_10}; // @[pla.scala:114:19]
wire [8:0] cs_decoder_decoded_orMatrixOutputs_lo_29 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_24, cs_decoder_decoded_orMatrixOutputs_lo_lo_20}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_16 = {cs_decoder_decoded_andMatrixOutputs_100_2, cs_decoder_decoded_andMatrixOutputs_45_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_21 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_16, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_10}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_11 = {cs_decoder_decoded_andMatrixOutputs_15_2, cs_decoder_decoded_andMatrixOutputs_147_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_19 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_9, cs_decoder_decoded_andMatrixOutputs_43_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_26 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_19, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_11}; // @[pla.scala:114:19]
wire [8:0] cs_decoder_decoded_orMatrixOutputs_hi_34 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_26, cs_decoder_decoded_orMatrixOutputs_hi_lo_21}; // @[pla.scala:114:19]
wire [17:0] _cs_decoder_decoded_orMatrixOutputs_T_88 = {cs_decoder_decoded_orMatrixOutputs_hi_34, cs_decoder_decoded_orMatrixOutputs_lo_29}; // @[pla.scala:114:19]
wire _cs_decoder_decoded_orMatrixOutputs_T_89 = |_cs_decoder_decoded_orMatrixOutputs_T_88; // @[pla.scala:114:{19,36}]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_21 = {cs_decoder_decoded_andMatrixOutputs_111_2, cs_decoder_decoded_andMatrixOutputs_127_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_18 = {cs_decoder_decoded_andMatrixOutputs_159_2, cs_decoder_decoded_andMatrixOutputs_171_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_25 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_18, cs_decoder_decoded_andMatrixOutputs_39_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_30 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_25, cs_decoder_decoded_orMatrixOutputs_lo_lo_21}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_17 = {cs_decoder_decoded_andMatrixOutputs_107_2, cs_decoder_decoded_andMatrixOutputs_33_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_22 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_17, cs_decoder_decoded_andMatrixOutputs_87_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_20 = {cs_decoder_decoded_andMatrixOutputs_98_2, cs_decoder_decoded_andMatrixOutputs_118_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_27 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_20, cs_decoder_decoded_andMatrixOutputs_3_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] cs_decoder_decoded_orMatrixOutputs_hi_35 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_27, cs_decoder_decoded_orMatrixOutputs_hi_lo_22}; // @[pla.scala:114:19]
wire [10:0] _cs_decoder_decoded_orMatrixOutputs_T_90 = {cs_decoder_decoded_orMatrixOutputs_hi_35, cs_decoder_decoded_orMatrixOutputs_lo_30}; // @[pla.scala:114:19]
wire _cs_decoder_decoded_orMatrixOutputs_T_91 = |_cs_decoder_decoded_orMatrixOutputs_T_90; // @[pla.scala:114:{19,36}]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_13 = {cs_decoder_decoded_andMatrixOutputs_90_2, cs_decoder_decoded_andMatrixOutputs_86_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_22 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_13, cs_decoder_decoded_andMatrixOutputs_32_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_26 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_19, cs_decoder_decoded_andMatrixOutputs_120_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] cs_decoder_decoded_orMatrixOutputs_lo_31 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_26, cs_decoder_decoded_orMatrixOutputs_lo_lo_22}; // @[pla.scala:114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_23 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_18, cs_decoder_decoded_andMatrixOutputs_88_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_28 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_21, cs_decoder_decoded_andMatrixOutputs_169_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] cs_decoder_decoded_orMatrixOutputs_hi_36 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_28, cs_decoder_decoded_orMatrixOutputs_hi_lo_23}; // @[pla.scala:114:19]
wire [11:0] _cs_decoder_decoded_orMatrixOutputs_T_92 = {cs_decoder_decoded_orMatrixOutputs_hi_36, cs_decoder_decoded_orMatrixOutputs_lo_31}; // @[pla.scala:114:19]
wire _cs_decoder_decoded_orMatrixOutputs_T_93 = |_cs_decoder_decoded_orMatrixOutputs_T_92; // @[pla.scala:114:{19,36}]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi = {cs_decoder_decoded_andMatrixOutputs_120_2, cs_decoder_decoded_andMatrixOutputs_106_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_7 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_90_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_10 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_7, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_4}; // @[pla.scala:114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_8 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_88_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_14 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_8, cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_5}; // @[pla.scala:114:19]
wire [9:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_23 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_14, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_10}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_4 = {cs_decoder_decoded_andMatrixOutputs_95_2, cs_decoder_decoded_andMatrixOutputs_92_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_7 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_135_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_11 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_7, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_4}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_5 = {cs_decoder_decoded_andMatrixOutputs_65_2, cs_decoder_decoded_andMatrixOutputs_6_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_10 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_166_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_20 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_10, cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_5}; // @[pla.scala:114:19]
wire [9:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_27 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_20, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_11}; // @[pla.scala:114:19]
wire [19:0] cs_decoder_decoded_orMatrixOutputs_lo_32 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_27, cs_decoder_decoded_orMatrixOutputs_lo_lo_23}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi = {cs_decoder_decoded_andMatrixOutputs_70_2, cs_decoder_decoded_andMatrixOutputs_125_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_7 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_16_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_11 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_7, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_4}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_114_2, cs_decoder_decoded_andMatrixOutputs_139_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_8 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_67_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_19 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_8, cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_5}; // @[pla.scala:114:19]
wire [9:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_24 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_19, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_11}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_170_2, cs_decoder_decoded_andMatrixOutputs_5_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_8 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_75_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_12 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_8, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_4}; // @[pla.scala:114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_6 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi, cs_decoder_decoded_andMatrixOutputs_34_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_10 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_4, cs_decoder_decoded_andMatrixOutputs_29_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_22 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_10, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_6}; // @[pla.scala:114:19]
wire [10:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_29 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_22, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_12}; // @[pla.scala:114:19]
wire [20:0] cs_decoder_decoded_orMatrixOutputs_hi_37 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_29, cs_decoder_decoded_orMatrixOutputs_hi_lo_24}; // @[pla.scala:114:19]
wire [40:0] _cs_decoder_decoded_orMatrixOutputs_T_94 = {cs_decoder_decoded_orMatrixOutputs_hi_37, cs_decoder_decoded_orMatrixOutputs_lo_32}; // @[pla.scala:114:19]
wire _cs_decoder_decoded_orMatrixOutputs_T_95 = |_cs_decoder_decoded_orMatrixOutputs_T_94; // @[pla.scala:114:{19,36}]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_hi = {_cs_decoder_decoded_orMatrixOutputs_T_3, _cs_decoder_decoded_orMatrixOutputs_T_1}; // @[pla.scala:102:36, :114:36]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_5 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_hi, _cs_decoder_decoded_orMatrixOutputs_T}; // @[pla.scala:102:36, :114:36]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_1 = {_cs_decoder_decoded_orMatrixOutputs_T_8, _cs_decoder_decoded_orMatrixOutputs_T_7}; // @[pla.scala:102:36, :114:36]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_8 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_1, _cs_decoder_decoded_orMatrixOutputs_T_5}; // @[pla.scala:102:36, :114:36]
wire [5:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_11 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_8, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_5}; // @[pla.scala:102:36]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi = {_cs_decoder_decoded_orMatrixOutputs_T_14, _cs_decoder_decoded_orMatrixOutputs_T_12}; // @[pla.scala:102:36, :114:36]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_6 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi, _cs_decoder_decoded_orMatrixOutputs_T_10}; // @[pla.scala:102:36, :114:36]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_lo = {_cs_decoder_decoded_orMatrixOutputs_T_18, _cs_decoder_decoded_orMatrixOutputs_T_16}; // @[pla.scala:102:36, :114:36]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_2 = {_cs_decoder_decoded_orMatrixOutputs_T_22, _cs_decoder_decoded_orMatrixOutputs_T_20}; // @[pla.scala:102:36, :114:36]
wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_9 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_lo}; // @[pla.scala:102:36]
wire [6:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_15 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_9, cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_6}; // @[pla.scala:102:36]
wire [12:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_24 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_15, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_11}; // @[pla.scala:102:36]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi = {_cs_decoder_decoded_orMatrixOutputs_T_25, _cs_decoder_decoded_orMatrixOutputs_T_24}; // @[pla.scala:102:36, :114:36]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_5 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi, _cs_decoder_decoded_orMatrixOutputs_T_23}; // @[pla.scala:102:36, :114:36]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_1 = {_cs_decoder_decoded_orMatrixOutputs_T_30, _cs_decoder_decoded_orMatrixOutputs_T_28}; // @[pla.scala:102:36, :114:36]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_8 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_1, _cs_decoder_decoded_orMatrixOutputs_T_26}; // @[pla.scala:102:36, :114:36]
wire [5:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_12 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_8, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_5}; // @[pla.scala:102:36]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi = {_cs_decoder_decoded_orMatrixOutputs_T_36, _cs_decoder_decoded_orMatrixOutputs_T_34}; // @[pla.scala:102:36, :114:36]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_6 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi, _cs_decoder_decoded_orMatrixOutputs_T_32}; // @[pla.scala:102:36, :114:36]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_lo = {_cs_decoder_decoded_orMatrixOutputs_T_38, _cs_decoder_decoded_orMatrixOutputs_T_37}; // @[pla.scala:102:36, :114:36]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_3 = {_cs_decoder_decoded_orMatrixOutputs_T_42, _cs_decoder_decoded_orMatrixOutputs_T_40}; // @[pla.scala:102:36, :114:36]
wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_11 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_3, cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_lo}; // @[pla.scala:102:36]
wire [6:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_21 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_11, cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_6}; // @[pla.scala:102:36]
wire [12:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_28 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_21, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_12}; // @[pla.scala:102:36]
wire [25:0] cs_decoder_decoded_orMatrixOutputs_lo_33 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_28, cs_decoder_decoded_orMatrixOutputs_lo_lo_24}; // @[pla.scala:102:36]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_hi = {_cs_decoder_decoded_orMatrixOutputs_T_48, _cs_decoder_decoded_orMatrixOutputs_T_46}; // @[pla.scala:102:36, :114:36]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_5 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_hi, _cs_decoder_decoded_orMatrixOutputs_T_44}; // @[pla.scala:102:36, :114:36]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_1 = {_cs_decoder_decoded_orMatrixOutputs_T_54, _cs_decoder_decoded_orMatrixOutputs_T_52}; // @[pla.scala:102:36, :114:36]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_8 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_1, _cs_decoder_decoded_orMatrixOutputs_T_50}; // @[pla.scala:102:36, :114:36]
wire [5:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_12 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_8, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_5}; // @[pla.scala:102:36]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi = {_cs_decoder_decoded_orMatrixOutputs_T_59, _cs_decoder_decoded_orMatrixOutputs_T_58}; // @[pla.scala:102:36, :114:36]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_6 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi, _cs_decoder_decoded_orMatrixOutputs_T_56}; // @[pla.scala:102:36, :114:36]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_lo = {_cs_decoder_decoded_orMatrixOutputs_T_63, _cs_decoder_decoded_orMatrixOutputs_T_61}; // @[pla.scala:102:36, :114:36]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_2 = {_cs_decoder_decoded_orMatrixOutputs_T_67, _cs_decoder_decoded_orMatrixOutputs_T_65}; // @[pla.scala:102:36, :114:36]
wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_9 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_lo}; // @[pla.scala:102:36]
wire [6:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_20 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_9, cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_6}; // @[pla.scala:102:36]
wire [12:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_25 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_20, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_12}; // @[pla.scala:102:36]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi = {_cs_decoder_decoded_orMatrixOutputs_T_73, _cs_decoder_decoded_orMatrixOutputs_T_71}; // @[pla.scala:102:36, :114:36]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_5 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi, _cs_decoder_decoded_orMatrixOutputs_T_69}; // @[pla.scala:102:36, :114:36]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_lo = {_cs_decoder_decoded_orMatrixOutputs_T_77, _cs_decoder_decoded_orMatrixOutputs_T_75}; // @[pla.scala:102:36, :114:36]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_2 = {_cs_decoder_decoded_orMatrixOutputs_T_81, _cs_decoder_decoded_orMatrixOutputs_T_79}; // @[pla.scala:102:36, :114:36]
wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_9 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_lo}; // @[pla.scala:102:36]
wire [6:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_13 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_9, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_5}; // @[pla.scala:102:36]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_1 = {_cs_decoder_decoded_orMatrixOutputs_T_87, _cs_decoder_decoded_orMatrixOutputs_T_85}; // @[pla.scala:102:36, :114:36]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_7 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_1, _cs_decoder_decoded_orMatrixOutputs_T_83}; // @[pla.scala:102:36, :114:36]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_lo = {_cs_decoder_decoded_orMatrixOutputs_T_91, _cs_decoder_decoded_orMatrixOutputs_T_89}; // @[pla.scala:102:36, :114:36]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_5 = {_cs_decoder_decoded_orMatrixOutputs_T_95, _cs_decoder_decoded_orMatrixOutputs_T_93}; // @[pla.scala:102:36, :114:36]
wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_11 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_5, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_lo}; // @[pla.scala:102:36]
wire [6:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_23 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_11, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_7}; // @[pla.scala:102:36]
wire [13:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_30 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_23, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_13}; // @[pla.scala:102:36]
wire [26:0] cs_decoder_decoded_orMatrixOutputs_hi_38 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_30, cs_decoder_decoded_orMatrixOutputs_hi_lo_25}; // @[pla.scala:102:36]
wire [52:0] cs_decoder_decoded_orMatrixOutputs = {cs_decoder_decoded_orMatrixOutputs_hi_38, cs_decoder_decoded_orMatrixOutputs_lo_33}; // @[pla.scala:102:36]
wire _cs_decoder_decoded_invMatrixOutputs_T = cs_decoder_decoded_orMatrixOutputs[0]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_1 = cs_decoder_decoded_orMatrixOutputs[1]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_2 = cs_decoder_decoded_orMatrixOutputs[2]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_3 = cs_decoder_decoded_orMatrixOutputs[3]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_4 = cs_decoder_decoded_orMatrixOutputs[4]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_5 = cs_decoder_decoded_orMatrixOutputs[5]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_6 = cs_decoder_decoded_orMatrixOutputs[6]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_7 = cs_decoder_decoded_orMatrixOutputs[7]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_8 = cs_decoder_decoded_orMatrixOutputs[8]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_9 = cs_decoder_decoded_orMatrixOutputs[9]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_10 = cs_decoder_decoded_orMatrixOutputs[10]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_11 = cs_decoder_decoded_orMatrixOutputs[11]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_12 = cs_decoder_decoded_orMatrixOutputs[12]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_13 = cs_decoder_decoded_orMatrixOutputs[13]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_14 = cs_decoder_decoded_orMatrixOutputs[14]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_15 = cs_decoder_decoded_orMatrixOutputs[15]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_16 = cs_decoder_decoded_orMatrixOutputs[16]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_17 = cs_decoder_decoded_orMatrixOutputs[17]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_18 = cs_decoder_decoded_orMatrixOutputs[18]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_19 = cs_decoder_decoded_orMatrixOutputs[19]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_20 = cs_decoder_decoded_orMatrixOutputs[20]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_21 = cs_decoder_decoded_orMatrixOutputs[21]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_22 = cs_decoder_decoded_orMatrixOutputs[22]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_23 = cs_decoder_decoded_orMatrixOutputs[23]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_24 = cs_decoder_decoded_orMatrixOutputs[24]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_25 = cs_decoder_decoded_orMatrixOutputs[25]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_26 = cs_decoder_decoded_orMatrixOutputs[26]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_27 = cs_decoder_decoded_orMatrixOutputs[27]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_28 = cs_decoder_decoded_orMatrixOutputs[28]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_29 = cs_decoder_decoded_orMatrixOutputs[29]; // @[pla.scala:102:36, :123:56]
wire _cs_decoder_decoded_invMatrixOutputs_T_30 = ~_cs_decoder_decoded_invMatrixOutputs_T_29; // @[pla.scala:123:{40,56}]
wire _cs_decoder_decoded_invMatrixOutputs_T_31 = cs_decoder_decoded_orMatrixOutputs[30]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_32 = cs_decoder_decoded_orMatrixOutputs[31]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_33 = cs_decoder_decoded_orMatrixOutputs[32]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_34 = cs_decoder_decoded_orMatrixOutputs[33]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_35 = cs_decoder_decoded_orMatrixOutputs[34]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_36 = cs_decoder_decoded_orMatrixOutputs[35]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_37 = cs_decoder_decoded_orMatrixOutputs[36]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_38 = cs_decoder_decoded_orMatrixOutputs[37]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_39 = cs_decoder_decoded_orMatrixOutputs[38]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_40 = cs_decoder_decoded_orMatrixOutputs[39]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_41 = cs_decoder_decoded_orMatrixOutputs[40]; // @[pla.scala:102:36, :123:56]
wire _cs_decoder_decoded_invMatrixOutputs_T_42 = ~_cs_decoder_decoded_invMatrixOutputs_T_41; // @[pla.scala:123:{40,56}]
wire _cs_decoder_decoded_invMatrixOutputs_T_43 = cs_decoder_decoded_orMatrixOutputs[41]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_44 = cs_decoder_decoded_orMatrixOutputs[42]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_45 = cs_decoder_decoded_orMatrixOutputs[43]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_46 = cs_decoder_decoded_orMatrixOutputs[44]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_47 = cs_decoder_decoded_orMatrixOutputs[45]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_48 = cs_decoder_decoded_orMatrixOutputs[46]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_49 = cs_decoder_decoded_orMatrixOutputs[47]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_50 = cs_decoder_decoded_orMatrixOutputs[48]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_51 = cs_decoder_decoded_orMatrixOutputs[49]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_52 = cs_decoder_decoded_orMatrixOutputs[50]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_53 = cs_decoder_decoded_orMatrixOutputs[51]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_54 = cs_decoder_decoded_orMatrixOutputs[52]; // @[pla.scala:102:36, :124:31]
wire [1:0] cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_lo_hi = {_cs_decoder_decoded_invMatrixOutputs_T_2, _cs_decoder_decoded_invMatrixOutputs_T_1}; // @[pla.scala:120:37, :124:31]
wire [2:0] cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_lo = {cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_lo_hi, _cs_decoder_decoded_invMatrixOutputs_T}; // @[pla.scala:120:37, :124:31]
wire [1:0] cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi_hi = {_cs_decoder_decoded_invMatrixOutputs_T_5, _cs_decoder_decoded_invMatrixOutputs_T_4}; // @[pla.scala:120:37, :124:31]
wire [2:0] cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi = {cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi_hi, _cs_decoder_decoded_invMatrixOutputs_T_3}; // @[pla.scala:120:37, :124:31]
wire [5:0] cs_decoder_decoded_invMatrixOutputs_lo_lo_lo = {cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi, cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_lo}; // @[pla.scala:120:37]
wire [1:0] cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_lo_hi = {_cs_decoder_decoded_invMatrixOutputs_T_8, _cs_decoder_decoded_invMatrixOutputs_T_7}; // @[pla.scala:120:37, :124:31]
wire [2:0] cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_lo = {cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_lo_hi, _cs_decoder_decoded_invMatrixOutputs_T_6}; // @[pla.scala:120:37, :124:31]
wire [1:0] cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi_lo = {_cs_decoder_decoded_invMatrixOutputs_T_10, _cs_decoder_decoded_invMatrixOutputs_T_9}; // @[pla.scala:120:37, :124:31]
wire [1:0] cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi_hi = {_cs_decoder_decoded_invMatrixOutputs_T_12, _cs_decoder_decoded_invMatrixOutputs_T_11}; // @[pla.scala:120:37, :124:31]
wire [3:0] cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi = {cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi_hi, cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi_lo}; // @[pla.scala:120:37]
wire [6:0] cs_decoder_decoded_invMatrixOutputs_lo_lo_hi = {cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi, cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_lo}; // @[pla.scala:120:37]
wire [12:0] cs_decoder_decoded_invMatrixOutputs_lo_lo = {cs_decoder_decoded_invMatrixOutputs_lo_lo_hi, cs_decoder_decoded_invMatrixOutputs_lo_lo_lo}; // @[pla.scala:120:37]
wire [1:0] cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_lo_hi = {_cs_decoder_decoded_invMatrixOutputs_T_15, _cs_decoder_decoded_invMatrixOutputs_T_14}; // @[pla.scala:120:37, :124:31]
wire [2:0] cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_lo = {cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_lo_hi, _cs_decoder_decoded_invMatrixOutputs_T_13}; // @[pla.scala:120:37, :124:31]
wire [1:0] cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi_hi = {_cs_decoder_decoded_invMatrixOutputs_T_18, _cs_decoder_decoded_invMatrixOutputs_T_17}; // @[pla.scala:120:37, :124:31]
wire [2:0] cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi = {cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi_hi, _cs_decoder_decoded_invMatrixOutputs_T_16}; // @[pla.scala:120:37, :124:31]
wire [5:0] cs_decoder_decoded_invMatrixOutputs_lo_hi_lo = {cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi, cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_lo}; // @[pla.scala:120:37]
wire [1:0] cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_lo_hi = {_cs_decoder_decoded_invMatrixOutputs_T_21, _cs_decoder_decoded_invMatrixOutputs_T_20}; // @[pla.scala:120:37, :124:31]
wire [2:0] cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_lo = {cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_lo_hi, _cs_decoder_decoded_invMatrixOutputs_T_19}; // @[pla.scala:120:37, :124:31]
wire [1:0] cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi_lo = {_cs_decoder_decoded_invMatrixOutputs_T_23, _cs_decoder_decoded_invMatrixOutputs_T_22}; // @[pla.scala:120:37, :124:31]
wire [1:0] cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi_hi = {_cs_decoder_decoded_invMatrixOutputs_T_25, _cs_decoder_decoded_invMatrixOutputs_T_24}; // @[pla.scala:120:37, :124:31]
wire [3:0] cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi = {cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi_hi, cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi_lo}; // @[pla.scala:120:37]
wire [6:0] cs_decoder_decoded_invMatrixOutputs_lo_hi_hi = {cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi, cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_lo}; // @[pla.scala:120:37]
wire [12:0] cs_decoder_decoded_invMatrixOutputs_lo_hi = {cs_decoder_decoded_invMatrixOutputs_lo_hi_hi, cs_decoder_decoded_invMatrixOutputs_lo_hi_lo}; // @[pla.scala:120:37]
wire [25:0] cs_decoder_decoded_invMatrixOutputs_lo = {cs_decoder_decoded_invMatrixOutputs_lo_hi, cs_decoder_decoded_invMatrixOutputs_lo_lo}; // @[pla.scala:120:37]
wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_lo_hi = {_cs_decoder_decoded_invMatrixOutputs_T_28, _cs_decoder_decoded_invMatrixOutputs_T_27}; // @[pla.scala:120:37, :124:31]
wire [2:0] cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_lo = {cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_lo_hi, _cs_decoder_decoded_invMatrixOutputs_T_26}; // @[pla.scala:120:37, :124:31]
wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi_hi = {_cs_decoder_decoded_invMatrixOutputs_T_32, _cs_decoder_decoded_invMatrixOutputs_T_31}; // @[pla.scala:120:37, :124:31]
wire [2:0] cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi = {cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi_hi, _cs_decoder_decoded_invMatrixOutputs_T_30}; // @[pla.scala:120:37, :123:40]
wire [5:0] cs_decoder_decoded_invMatrixOutputs_hi_lo_lo = {cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi, cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_lo}; // @[pla.scala:120:37]
wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_lo_hi = {_cs_decoder_decoded_invMatrixOutputs_T_35, _cs_decoder_decoded_invMatrixOutputs_T_34}; // @[pla.scala:120:37, :124:31]
wire [2:0] cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_lo = {cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_lo_hi, _cs_decoder_decoded_invMatrixOutputs_T_33}; // @[pla.scala:120:37, :124:31]
wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi_lo = {_cs_decoder_decoded_invMatrixOutputs_T_37, _cs_decoder_decoded_invMatrixOutputs_T_36}; // @[pla.scala:120:37, :124:31]
wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi_hi = {_cs_decoder_decoded_invMatrixOutputs_T_39, _cs_decoder_decoded_invMatrixOutputs_T_38}; // @[pla.scala:120:37, :124:31]
wire [3:0] cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi = {cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi_hi, cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi_lo}; // @[pla.scala:120:37]
wire [6:0] cs_decoder_decoded_invMatrixOutputs_hi_lo_hi = {cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi, cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_lo}; // @[pla.scala:120:37]
wire [12:0] cs_decoder_decoded_invMatrixOutputs_hi_lo = {cs_decoder_decoded_invMatrixOutputs_hi_lo_hi, cs_decoder_decoded_invMatrixOutputs_hi_lo_lo}; // @[pla.scala:120:37]
wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_lo_hi = {_cs_decoder_decoded_invMatrixOutputs_T_43, _cs_decoder_decoded_invMatrixOutputs_T_42}; // @[pla.scala:120:37, :123:40, :124:31]
wire [2:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_lo = {cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_lo_hi, _cs_decoder_decoded_invMatrixOutputs_T_40}; // @[pla.scala:120:37, :124:31]
wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi_lo = {_cs_decoder_decoded_invMatrixOutputs_T_45, _cs_decoder_decoded_invMatrixOutputs_T_44}; // @[pla.scala:120:37, :124:31]
wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi_hi = {_cs_decoder_decoded_invMatrixOutputs_T_47, _cs_decoder_decoded_invMatrixOutputs_T_46}; // @[pla.scala:120:37, :124:31]
wire [3:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi = {cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi_hi, cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi_lo}; // @[pla.scala:120:37]
wire [6:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_lo = {cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi, cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_lo}; // @[pla.scala:120:37]
wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo_hi = {_cs_decoder_decoded_invMatrixOutputs_T_50, _cs_decoder_decoded_invMatrixOutputs_T_49}; // @[pla.scala:120:37, :124:31]
wire [2:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo = {cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo_hi, _cs_decoder_decoded_invMatrixOutputs_T_48}; // @[pla.scala:120:37, :124:31]
wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi_lo = {_cs_decoder_decoded_invMatrixOutputs_T_52, _cs_decoder_decoded_invMatrixOutputs_T_51}; // @[pla.scala:120:37, :124:31]
wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi_hi = {_cs_decoder_decoded_invMatrixOutputs_T_54, _cs_decoder_decoded_invMatrixOutputs_T_53}; // @[pla.scala:120:37, :124:31]
wire [3:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi = {cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi_hi, cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi_lo}; // @[pla.scala:120:37]
wire [6:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_hi = {cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi, cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo}; // @[pla.scala:120:37]
wire [13:0] cs_decoder_decoded_invMatrixOutputs_hi_hi = {cs_decoder_decoded_invMatrixOutputs_hi_hi_hi, cs_decoder_decoded_invMatrixOutputs_hi_hi_lo}; // @[pla.scala:120:37]
wire [26:0] cs_decoder_decoded_invMatrixOutputs_hi = {cs_decoder_decoded_invMatrixOutputs_hi_hi, cs_decoder_decoded_invMatrixOutputs_hi_lo}; // @[pla.scala:120:37]
assign cs_decoder_decoded_invMatrixOutputs = {cs_decoder_decoded_invMatrixOutputs_hi, cs_decoder_decoded_invMatrixOutputs_lo}; // @[pla.scala:120:37]
assign cs_decoder_decoded = cs_decoder_decoded_invMatrixOutputs; // @[pla.scala:81:23, :120:37]
assign cs_decoder_0 = cs_decoder_decoded[52]; // @[pla.scala:81:23]
assign cs_legal = cs_decoder_0; // @[Decode.scala:50:77]
assign cs_decoder_1 = cs_decoder_decoded[51]; // @[pla.scala:81:23]
assign cs_fp_val = cs_decoder_1; // @[Decode.scala:50:77]
assign cs_decoder_2 = cs_decoder_decoded[50]; // @[pla.scala:81:23]
assign cs_fp_single = cs_decoder_2; // @[Decode.scala:50:77]
assign cs_decoder_3 = cs_decoder_decoded[49:43]; // @[pla.scala:81:23]
assign cs_uopc = cs_decoder_3; // @[Decode.scala:50:77]
assign cs_decoder_4 = cs_decoder_decoded[42:40]; // @[pla.scala:81:23]
assign cs_iq_type = cs_decoder_4; // @[Decode.scala:50:77]
assign cs_decoder_5 = cs_decoder_decoded[39:30]; // @[pla.scala:81:23]
assign cs_fu_code = cs_decoder_5; // @[Decode.scala:50:77]
assign cs_decoder_6 = cs_decoder_decoded[29:28]; // @[pla.scala:81:23]
assign cs_dst_type = cs_decoder_6; // @[Decode.scala:50:77]
assign cs_decoder_7 = cs_decoder_decoded[27:26]; // @[pla.scala:81:23]
assign cs_rs1_type = cs_decoder_7; // @[Decode.scala:50:77]
assign cs_decoder_8 = cs_decoder_decoded[25:24]; // @[pla.scala:81:23]
assign cs_rs2_type = cs_decoder_8; // @[Decode.scala:50:77]
assign cs_decoder_9 = cs_decoder_decoded[23]; // @[pla.scala:81:23]
assign cs_frs3_en = cs_decoder_9; // @[Decode.scala:50:77]
assign cs_decoder_10 = cs_decoder_decoded[22:20]; // @[pla.scala:81:23]
assign cs_imm_sel = cs_decoder_10; // @[Decode.scala:50:77]
assign cs_decoder_11 = cs_decoder_decoded[19]; // @[pla.scala:81:23]
assign cs_uses_ldq = cs_decoder_11; // @[Decode.scala:50:77]
assign cs_decoder_12 = cs_decoder_decoded[18]; // @[pla.scala:81:23]
assign cs_uses_stq = cs_decoder_12; // @[Decode.scala:50:77]
assign cs_decoder_13 = cs_decoder_decoded[17]; // @[pla.scala:81:23]
assign cs_is_amo = cs_decoder_13; // @[Decode.scala:50:77]
assign cs_decoder_14 = cs_decoder_decoded[16]; // @[pla.scala:81:23]
assign cs_is_fence = cs_decoder_14; // @[Decode.scala:50:77]
assign cs_decoder_15 = cs_decoder_decoded[15]; // @[pla.scala:81:23]
assign cs_is_fencei = cs_decoder_15; // @[Decode.scala:50:77]
assign cs_decoder_16 = cs_decoder_decoded[14:10]; // @[pla.scala:81:23]
assign cs_mem_cmd = cs_decoder_16; // @[Decode.scala:50:77]
assign cs_decoder_17 = cs_decoder_decoded[9:8]; // @[pla.scala:81:23]
assign cs_wakeup_delay = cs_decoder_17; // @[Decode.scala:50:77]
assign cs_decoder_18 = cs_decoder_decoded[7]; // @[pla.scala:81:23]
assign cs_bypassable = cs_decoder_18; // @[Decode.scala:50:77]
assign cs_decoder_19 = cs_decoder_decoded[6]; // @[pla.scala:81:23]
assign cs_is_br = cs_decoder_19; // @[Decode.scala:50:77]
assign cs_decoder_20 = cs_decoder_decoded[5]; // @[pla.scala:81:23]
assign cs_is_sys_pc2epc = cs_decoder_20; // @[Decode.scala:50:77]
assign cs_decoder_21 = cs_decoder_decoded[4]; // @[pla.scala:81:23]
assign cs_inst_unique = cs_decoder_21; // @[Decode.scala:50:77]
assign cs_decoder_22 = cs_decoder_decoded[3]; // @[pla.scala:81:23]
assign cs_flush_on_commit = cs_decoder_22; // @[Decode.scala:50:77]
assign cs_decoder_23 = cs_decoder_decoded[2:0]; // @[pla.scala:81:23]
assign cs_csr_cmd = cs_decoder_23; // @[Decode.scala:50:77]
wire _GEN_30 = cs_csr_cmd == 3'h6; // @[package.scala:16:47]
wire _csr_en_T; // @[package.scala:16:47]
assign _csr_en_T = _GEN_30; // @[package.scala:16:47]
wire _csr_ren_T; // @[package.scala:16:47]
assign _csr_ren_T = _GEN_30; // @[package.scala:16:47]
wire _csr_en_T_1 = &cs_csr_cmd; // @[package.scala:16:47]
wire _csr_en_T_2 = cs_csr_cmd == 3'h5; // @[package.scala:16:47]
wire _csr_en_T_3 = _csr_en_T | _csr_en_T_1; // @[package.scala:16:47, :81:59]
wire csr_en = _csr_en_T_3 | _csr_en_T_2; // @[package.scala:16:47, :81:59]
wire _csr_ren_T_1 = &cs_csr_cmd; // @[package.scala:16:47]
wire _csr_ren_T_2 = _csr_ren_T | _csr_ren_T_1; // @[package.scala:16:47, :81:59]
wire _csr_ren_T_3 = ~(|uop_lrs1); // @[decode.scala:479:17, :495:62]
wire csr_ren = _csr_ren_T_2 & _csr_ren_T_3; // @[package.scala:81:59]
wire system_insn = cs_csr_cmd == 3'h4; // @[decode.scala:490:16, :496:32]
wire sfence = cs_uopc == 7'h6B; // @[decode.scala:490:16, :497:24]
wire _id_illegal_insn_T = ~cs_legal; // @[decode.scala:490:16, :502:25]
wire _id_illegal_insn_T_1 = cs_fp_val & io_csr_decode_fp_illegal_0; // @[decode.scala:474:7, :490:16, :503:15]
wire _id_illegal_insn_T_2 = _id_illegal_insn_T | _id_illegal_insn_T_1; // @[decode.scala:502:{25,35}, :503:15]
wire _id_illegal_insn_T_4 = _id_illegal_insn_T_2; // @[decode.scala:502:35, :503:43]
wire _id_illegal_insn_T_8 = _id_illegal_insn_T_4; // @[decode.scala:503:43, :504:43]
wire _id_illegal_insn_T_14 = _id_illegal_insn_T_8; // @[decode.scala:504:43, :505:43]
wire _id_illegal_insn_T_9 = ~cs_fp_single; // @[decode.scala:490:16, :506:19]
wire _id_illegal_insn_T_10 = cs_fp_val & _id_illegal_insn_T_9; // @[decode.scala:490:16, :506:{16,19}]
wire _id_illegal_insn_T_15 = ~csr_ren; // @[decode.scala:495:50, :507:46]
wire _id_illegal_insn_T_16 = _id_illegal_insn_T_15 & io_csr_decode_write_illegal_0; // @[decode.scala:474:7, :507:{46,55}]
wire _id_illegal_insn_T_17 = io_csr_decode_read_illegal_0 | _id_illegal_insn_T_16; // @[decode.scala:474:7, :507:{43,55}]
wire _id_illegal_insn_T_18 = csr_en & _id_illegal_insn_T_17; // @[package.scala:81:59]
wire _id_illegal_insn_T_19 = _id_illegal_insn_T_14 | _id_illegal_insn_T_18; // @[decode.scala:505:43, :506:61, :507:12]
wire _id_illegal_insn_T_20 = sfence | system_insn; // @[decode.scala:496:32, :497:24, :508:14]
wire _id_illegal_insn_T_21 = _id_illegal_insn_T_20 & io_csr_decode_system_illegal_0; // @[decode.scala:474:7, :508:{14,30}]
wire id_illegal_insn = _id_illegal_insn_T_19 | _id_illegal_insn_T_21; // @[decode.scala:506:61, :507:87, :508:30]
wire _T_1 = io_interrupt_0 & ~io_enq_uop_is_sfb_0; // @[decode.scala:474:7, :516:{19,22}]
assign xcpt_valid = _T_1 | uop_bp_debug_if | uop_bp_xcpt_if | uop_xcpt_pf_if | uop_xcpt_ae_if | id_illegal_insn; // @[decode.scala:479:17, :507:87, :513:26, :516:19]
assign uop_exception = xcpt_valid; // @[decode.scala:479:17, :513:26]
assign xcpt_cause = _T_1 ? io_interrupt_cause_0 : {60'h0, uop_bp_debug_if ? 4'hE : uop_bp_xcpt_if ? 4'h3 : uop_xcpt_pf_if ? 4'hC : {2'h0, uop_xcpt_ae_if ? 2'h1 : 2'h2}}; // @[Mux.scala:50:70]
assign uop_exc_cause = xcpt_cause; // @[Mux.scala:50:70]
wire [4:0] _uop_ldst_T = uop_inst[11:7]; // @[decode.scala:479:17, :535:25]
wire [4:0] _uop_lrs2_T_1 = uop_inst[11:7]; // @[decode.scala:479:17, :535:25, :550:28]
wire [4:0] _uop_lrs1_T_1 = uop_inst[11:7]; // @[decode.scala:479:17, :535:25, :554:28]
wire [4:0] _di24_20_T_3 = uop_inst[11:7]; // @[decode.scala:479:17, :535:25, :583:69]
assign uop_ldst = {1'h0, _uop_ldst_T}; // @[decode.scala:479:17, :535:{18,25}]
wire [4:0] _uop_lrs1_T = uop_inst[19:15]; // @[decode.scala:479:17, :536:25]
assign uop_lrs1 = {1'h0, _uop_lrs1_T}; // @[decode.scala:479:17, :536:{18,25}]
wire [4:0] _uop_lrs2_T = uop_inst[24:20]; // @[decode.scala:479:17, :537:25]
wire [4:0] _di24_20_T_4 = uop_inst[24:20]; // @[decode.scala:479:17, :537:25, :583:81]
assign uop_lrs2 = {1'h0, _uop_lrs2_T}; // @[decode.scala:479:17, :537:{18,25}]
wire [4:0] _uop_lrs3_T = uop_inst[31:27]; // @[decode.scala:479:17, :538:25]
assign uop_lrs3 = {1'h0, _uop_lrs3_T}; // @[decode.scala:479:17, :538:{18,25}]
wire _uop_ldst_val_T = cs_dst_type != 2'h2; // @[decode.scala:490:16, :540:33]
wire _uop_ldst_val_T_1 = uop_ldst == 6'h0; // @[decode.scala:474:7, :477:14, :479:17, :540:56]
wire _uop_ldst_val_T_2 = uop_dst_rtype == 2'h0; // @[decode.scala:474:7, :477:14, :479:17, :540:81]
wire _uop_ldst_val_T_3 = _uop_ldst_val_T_1 & _uop_ldst_val_T_2; // @[decode.scala:540:{56,64,81}]
wire _uop_ldst_val_T_4 = ~_uop_ldst_val_T_3; // @[decode.scala:540:{45,64}]
assign _uop_ldst_val_T_5 = _uop_ldst_val_T & _uop_ldst_val_T_4; // @[decode.scala:540:{33,42,45}]
assign uop_ldst_val = _uop_ldst_val_T_5; // @[decode.scala:479:17, :540:42]
wire _uop_ldst_is_rs1_T = ~uop_is_br; // @[decode.scala:479:17]
wire _uop_ldst_is_rs1_T_1 = _uop_ldst_is_rs1_T & uop_is_sfb; // @[decode.scala:479:17]
wire _uop_mem_size_T = cs_mem_cmd == 5'h14; // @[package.scala:16:47]
wire _uop_mem_size_T_1 = cs_mem_cmd == 5'h5; // @[package.scala:16:47]
wire _uop_mem_size_T_2 = _uop_mem_size_T | _uop_mem_size_T_1; // @[package.scala:16:47, :81:59]
wire _uop_mem_size_T_3 = |uop_lrs2; // @[decode.scala:479:17, :566:81]
wire _uop_mem_size_T_4 = |uop_lrs1; // @[decode.scala:479:17, :495:62, :566:99]
wire [1:0] _uop_mem_size_T_5 = {_uop_mem_size_T_3, _uop_mem_size_T_4}; // @[decode.scala:566:{71,81,99}]
wire [1:0] _uop_mem_size_T_6 = uop_inst[13:12]; // @[decode.scala:479:17, :566:113]
assign _uop_mem_size_T_7 = _uop_mem_size_T_2 ? _uop_mem_size_T_5 : _uop_mem_size_T_6; // @[package.scala:81:59]
assign uop_mem_size = _uop_mem_size_T_7; // @[decode.scala:479:17, :566:24]
wire _uop_mem_signed_T = uop_inst[14]; // @[decode.scala:479:17, :567:26]
assign _uop_mem_signed_T_1 = ~_uop_mem_signed_T; // @[decode.scala:567:{21,26}]
assign uop_mem_signed = _uop_mem_signed_T_1; // @[decode.scala:479:17, :567:21]
wire _uop_flush_on_commit_T = ~csr_ren; // @[decode.scala:495:50, :507:46, :575:59]
wire _uop_flush_on_commit_T_1 = csr_en & _uop_flush_on_commit_T; // @[package.scala:81:59]
wire _uop_flush_on_commit_T_2 = _uop_flush_on_commit_T_1 & io_csr_decode_write_flush_0; // @[decode.scala:474:7, :575:{56,68}]
assign _uop_flush_on_commit_T_3 = cs_flush_on_commit | _uop_flush_on_commit_T_2; // @[decode.scala:490:16, :575:{45,68}]
assign uop_flush_on_commit = _uop_flush_on_commit_T_3; // @[decode.scala:479:17, :575:45]
wire _di24_20_T = cs_imm_sel == 3'h2; // @[decode.scala:490:16, :583:32]
wire _di24_20_T_1 = cs_imm_sel == 3'h1; // @[decode.scala:490:16, :583:55]
wire _di24_20_T_2 = _di24_20_T | _di24_20_T_1; // @[decode.scala:583:{32,41,55}]
wire [4:0] di24_20 = _di24_20_T_2 ? _di24_20_T_3 : _di24_20_T_4; // @[decode.scala:583:{20,41,69,81}]
wire [6:0] _uop_imm_packed_T = uop_inst[31:25]; // @[decode.scala:479:17, :584:29]
wire [7:0] _uop_imm_packed_T_1 = uop_inst[19:12]; // @[decode.scala:479:17, :584:51]
wire [11:0] uop_imm_packed_hi = {_uop_imm_packed_T, di24_20}; // @[decode.scala:583:20, :584:{24,29}]
assign _uop_imm_packed_T_2 = {uop_imm_packed_hi, _uop_imm_packed_T_1}; // @[decode.scala:584:{24,51}]
assign uop_imm_packed = _uop_imm_packed_T_2; // @[decode.scala:479:17, :584:24]
assign _uop_is_jal_T = uop_uopc == 7'h25; // @[decode.scala:479:17, :589:35]
assign uop_is_jal = _uop_is_jal_T; // @[decode.scala:479:17, :589:35]
assign _uop_is_jalr_T = uop_uopc == 7'h26; // @[decode.scala:479:17, :590:35]
assign uop_is_jalr = _uop_is_jalr_T; // @[decode.scala:479:17, :590:35]
assign io_deq_uop_uopc = io_deq_uop_uopc_0; // @[decode.scala:474:7]
assign io_deq_uop_inst = io_deq_uop_inst_0; // @[decode.scala:474:7]
assign io_deq_uop_debug_inst = io_deq_uop_debug_inst_0; // @[decode.scala:474:7]
assign io_deq_uop_is_rvc = io_deq_uop_is_rvc_0; // @[decode.scala:474:7]
assign io_deq_uop_debug_pc = io_deq_uop_debug_pc_0; // @[decode.scala:474:7]
assign io_deq_uop_iq_type = io_deq_uop_iq_type_0; // @[decode.scala:474:7]
assign io_deq_uop_fu_code = io_deq_uop_fu_code_0; // @[decode.scala:474:7]
assign io_deq_uop_is_br = io_deq_uop_is_br_0; // @[decode.scala:474:7]
assign io_deq_uop_is_jalr = io_deq_uop_is_jalr_0; // @[decode.scala:474:7]
assign io_deq_uop_is_jal = io_deq_uop_is_jal_0; // @[decode.scala:474:7]
assign io_deq_uop_is_sfb = io_deq_uop_is_sfb_0; // @[decode.scala:474:7]
assign io_deq_uop_ftq_idx = io_deq_uop_ftq_idx_0; // @[decode.scala:474:7]
assign io_deq_uop_edge_inst = io_deq_uop_edge_inst_0; // @[decode.scala:474:7]
assign io_deq_uop_pc_lob = io_deq_uop_pc_lob_0; // @[decode.scala:474:7]
assign io_deq_uop_taken = io_deq_uop_taken_0; // @[decode.scala:474:7]
assign io_deq_uop_imm_packed = io_deq_uop_imm_packed_0; // @[decode.scala:474:7]
assign io_deq_uop_exception = io_deq_uop_exception_0; // @[decode.scala:474:7]
assign io_deq_uop_exc_cause = io_deq_uop_exc_cause_0; // @[decode.scala:474:7]
assign io_deq_uop_bypassable = io_deq_uop_bypassable_0; // @[decode.scala:474:7]
assign io_deq_uop_mem_cmd = io_deq_uop_mem_cmd_0; // @[decode.scala:474:7]
assign io_deq_uop_mem_size = io_deq_uop_mem_size_0; // @[decode.scala:474:7]
assign io_deq_uop_mem_signed = io_deq_uop_mem_signed_0; // @[decode.scala:474:7]
assign io_deq_uop_is_fence = io_deq_uop_is_fence_0; // @[decode.scala:474:7]
assign io_deq_uop_is_fencei = io_deq_uop_is_fencei_0; // @[decode.scala:474:7]
assign io_deq_uop_is_amo = io_deq_uop_is_amo_0; // @[decode.scala:474:7]
assign io_deq_uop_uses_ldq = io_deq_uop_uses_ldq_0; // @[decode.scala:474:7]
assign io_deq_uop_uses_stq = io_deq_uop_uses_stq_0; // @[decode.scala:474:7]
assign io_deq_uop_is_sys_pc2epc = io_deq_uop_is_sys_pc2epc_0; // @[decode.scala:474:7]
assign io_deq_uop_is_unique = io_deq_uop_is_unique_0; // @[decode.scala:474:7]
assign io_deq_uop_flush_on_commit = io_deq_uop_flush_on_commit_0; // @[decode.scala:474:7]
assign io_deq_uop_ldst = io_deq_uop_ldst_0; // @[decode.scala:474:7]
assign io_deq_uop_lrs1 = io_deq_uop_lrs1_0; // @[decode.scala:474:7]
assign io_deq_uop_lrs2 = io_deq_uop_lrs2_0; // @[decode.scala:474:7]
assign io_deq_uop_lrs3 = io_deq_uop_lrs3_0; // @[decode.scala:474:7]
assign io_deq_uop_ldst_val = io_deq_uop_ldst_val_0; // @[decode.scala:474:7]
assign io_deq_uop_dst_rtype = io_deq_uop_dst_rtype_0; // @[decode.scala:474:7]
assign io_deq_uop_lrs1_rtype = io_deq_uop_lrs1_rtype_0; // @[decode.scala:474:7]
assign io_deq_uop_lrs2_rtype = io_deq_uop_lrs2_rtype_0; // @[decode.scala:474:7]
assign io_deq_uop_frs3_en = io_deq_uop_frs3_en_0; // @[decode.scala:474:7]
assign io_deq_uop_fp_val = io_deq_uop_fp_val_0; // @[decode.scala:474:7]
assign io_deq_uop_fp_single = io_deq_uop_fp_single_0; // @[decode.scala:474:7]
assign io_deq_uop_xcpt_pf_if = io_deq_uop_xcpt_pf_if_0; // @[decode.scala:474:7]
assign io_deq_uop_xcpt_ae_if = io_deq_uop_xcpt_ae_if_0; // @[decode.scala:474:7]
assign io_deq_uop_bp_debug_if = io_deq_uop_bp_debug_if_0; // @[decode.scala:474:7]
assign io_deq_uop_bp_xcpt_if = io_deq_uop_bp_xcpt_if_0; // @[decode.scala:474:7]
assign io_deq_uop_debug_fsrc = io_deq_uop_debug_fsrc_0; // @[decode.scala:474:7]
assign io_csr_decode_inst = io_csr_decode_inst_0; // @[decode.scala:474:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File PE.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle {
val dataflow = UInt(1.W) // TODO make this an Enum
val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)?
val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats
}
class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module {
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(inputType)
val in_c = Input(cType)
val out_d = Output(dType)
})
io.out_d := io.in_c.mac(io.in_a, io.in_b)
}
// TODO update documentation
/**
* A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh.
* @param width Data width of operands
*/
class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int)
(implicit ev: Arithmetic[T]) extends Module { // Debugging variables
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(outputType)
val in_d = Input(outputType)
val out_a = Output(inputType)
val out_b = Output(outputType)
val out_c = Output(outputType)
val in_control = Input(new PEControl(accType))
val out_control = Output(new PEControl(accType))
val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W))
val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W))
val in_last = Input(Bool())
val out_last = Output(Bool())
val in_valid = Input(Bool())
val out_valid = Output(Bool())
val bad_dataflow = Output(Bool())
})
val cType = if (df == Dataflow.WS) inputType else accType
// When creating PEs that support multiple dataflows, the
// elaboration/synthesis tools often fail to consolidate and de-duplicate
// MAC units. To force mac circuitry to be re-used, we create a "mac_unit"
// module here which just performs a single MAC operation
val mac_unit = Module(new MacUnit(inputType,
if (df == Dataflow.WS) outputType else accType, outputType))
val a = io.in_a
val b = io.in_b
val d = io.in_d
val c1 = Reg(cType)
val c2 = Reg(cType)
val dataflow = io.in_control.dataflow
val prop = io.in_control.propagate
val shift = io.in_control.shift
val id = io.in_id
val last = io.in_last
val valid = io.in_valid
io.out_a := a
io.out_control.dataflow := dataflow
io.out_control.propagate := prop
io.out_control.shift := shift
io.out_id := id
io.out_last := last
io.out_valid := valid
mac_unit.io.in_a := a
val last_s = RegEnable(prop, valid)
val flip = last_s =/= prop
val shift_offset = Mux(flip, shift, 0.U)
// Which dataflow are we using?
val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W)
val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W)
// Is c1 being computed on, or propagated forward (in the output-stationary dataflow)?
val COMPUTE = 0.U(1.W)
val PROPAGATE = 1.U(1.W)
io.bad_dataflow := false.B
when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
c2 := mac_unit.io.out_d
c1 := d.withWidthOf(cType)
}.otherwise {
io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c1
c1 := mac_unit.io.out_d
c2 := d.withWidthOf(cType)
}
}.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := c1
mac_unit.io.in_b := c2.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c1 := d
}.otherwise {
io.out_c := c2
mac_unit.io.in_b := c1.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c2 := d
}
}.otherwise {
io.bad_dataflow := true.B
//assert(false.B, "unknown dataflow")
io.out_c := DontCare
io.out_b := DontCare
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
}
when (!valid) {
c1 := c1
c2 := c2
mac_unit.io.in_b := DontCare
mac_unit.io.in_c := DontCare
}
}
File Arithmetic.scala:
// A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own:
// implicit MyTypeArithmetic extends Arithmetic[MyType] { ... }
package gemmini
import chisel3._
import chisel3.util._
import hardfloat._
// Bundles that represent the raw bits of custom datatypes
case class Float(expWidth: Int, sigWidth: Int) extends Bundle {
val bits = UInt((expWidth + sigWidth).W)
val bias: Int = (1 << (expWidth-1)) - 1
}
case class DummySInt(w: Int) extends Bundle {
val bits = UInt(w.W)
def dontCare: DummySInt = {
val o = Wire(new DummySInt(w))
o.bits := 0.U
o
}
}
// The Arithmetic typeclass which implements various arithmetic operations on custom datatypes
abstract class Arithmetic[T <: Data] {
implicit def cast(t: T): ArithmeticOps[T]
}
abstract class ArithmeticOps[T <: Data](self: T) {
def *(t: T): T
def mac(m1: T, m2: T): T // Returns (m1 * m2 + self)
def +(t: T): T
def -(t: T): T
def >>(u: UInt): T // This is a rounding shift! Rounds away from 0
def >(t: T): Bool
def identity: T
def withWidthOf(t: T): T
def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates
def relu: T
def zero: T
def minimum: T
// Optional parameters, which only need to be defined if you want to enable various optimizations for transformers
def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None
def mult_with_reciprocal[U <: Data](reciprocal: U) = self
}
object Arithmetic {
implicit object UIntArithmetic extends Arithmetic[UInt] {
override implicit def cast(self: UInt) = new ArithmeticOps(self) {
override def *(t: UInt) = self * t
override def mac(m1: UInt, m2: UInt) = m1 * m2 + self
override def +(t: UInt) = self + t
override def -(t: UInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = point_five & (zeros | ones_digit)
(self >> u).asUInt + r
}
override def >(t: UInt): Bool = self > t
override def withWidthOf(t: UInt) = self.asTypeOf(t)
override def clippedToWidthOf(t: UInt) = {
val sat = ((1 << (t.getWidth-1))-1).U
Mux(self > sat, sat, self)(t.getWidth-1, 0)
}
override def relu: UInt = self
override def zero: UInt = 0.U
override def identity: UInt = 1.U
override def minimum: UInt = 0.U
}
}
implicit object SIntArithmetic extends Arithmetic[SInt] {
override implicit def cast(self: SInt) = new ArithmeticOps(self) {
override def *(t: SInt) = self * t
override def mac(m1: SInt, m2: SInt) = m1 * m2 + self
override def +(t: SInt) = self + t
override def -(t: SInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = (point_five & (zeros | ones_digit)).asBool
(self >> u).asSInt + Mux(r, 1.S, 0.S)
}
override def >(t: SInt): Bool = self > t
override def withWidthOf(t: SInt) = {
if (self.getWidth >= t.getWidth)
self(t.getWidth-1, 0).asSInt
else {
val sign_bits = t.getWidth - self.getWidth
val sign = self(self.getWidth-1)
Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t)
}
}
override def clippedToWidthOf(t: SInt): SInt = {
val maxsat = ((1 << (t.getWidth-1))-1).S
val minsat = (-(1 << (t.getWidth-1))).S
MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt
}
override def relu: SInt = Mux(self >= 0.S, self, 0.S)
override def zero: SInt = 0.S
override def identity: SInt = 1.S
override def minimum: SInt = (-(1 << (self.getWidth-1))).S
override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(denom_t.cloneType))
val output = Wire(Decoupled(self.cloneType))
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def sin_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def uin_to_float(x: UInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := x
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = sin_to_float(self)
val denom_rec = uin_to_float(input.bits)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := self_rec
divider.io.b := denom_rec
divider.io.roundingMode := consts.round_minMag
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := float_to_in(divider.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(self.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
// Instantiate the hardloat sqrt
val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0))
input.ready := sqrter.io.inReady
sqrter.io.inValid := input.valid
sqrter.io.sqrtOp := true.B
sqrter.io.a := self_rec
sqrter.io.b := DontCare
sqrter.io.roundingMode := consts.round_minMag
sqrter.io.detectTininess := consts.tininess_afterRounding
output.valid := sqrter.io.outValid_sqrt
output.bits := float_to_in(sqrter.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match {
case Float(expWidth, sigWidth) =>
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(u.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
val self_rec = in_to_float(self)
val one_rec = in_to_float(1.S)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := one_rec
divider.io.b := self_rec
divider.io.roundingMode := consts.round_near_even
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u)
assert(!output.valid || output.ready)
Some((input, output))
case _ => None
}
override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match {
case recip @ Float(expWidth, sigWidth) =>
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits)
// Instantiate the hardloat divider
val muladder = Module(new MulRecFN(expWidth, sigWidth))
muladder.io.roundingMode := consts.round_near_even
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := reciprocal_rec
float_to_in(muladder.io.out)
case _ => self
}
}
}
implicit object FloatArithmetic extends Arithmetic[Float] {
// TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array
override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) {
override def *(t: Float): Float = {
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := t_rec_resized
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def mac(m1: Float, m2: Float): Float = {
// Recode all operands
val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits)
val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize m1 to self's width
val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth))
m1_resizer.io.in := m1_rec
m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m1_resizer.io.detectTininess := consts.tininess_afterRounding
val m1_rec_resized = m1_resizer.io.out
// Resize m2 to self's width
val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth))
m2_resizer.io.in := m2_rec
m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m2_resizer.io.detectTininess := consts.tininess_afterRounding
val m2_rec_resized = m2_resizer.io.out
// Perform multiply-add
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := m1_rec_resized
muladder.io.b := m2_rec_resized
muladder.io.c := self_rec
// Convert result to standard format // TODO remove these intermediate recodings
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def +(t: Float): Float = {
require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Generate 1 as a float
val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := 1.U
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
val one_rec = in_to_rec_fn.io.out
// Resize t
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
// Perform addition
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := t_rec_resized
muladder.io.b := one_rec
muladder.io.c := self_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def -(t: Float): Float = {
val t_sgn = t.bits(t.getWidth-1)
val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t)
self + neg_t
}
override def >>(u: UInt): Float = {
// Recode self
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Get 2^(-u) as a recoded float
val shift_exp = Wire(UInt(self.expWidth.W))
shift_exp := self.bias.U - u
val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W))
val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn)
assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported")
// Multiply self and 2^(-u)
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := shift_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def >(t: Float): Bool = {
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize t to self's width
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth))
comparator.io.a := self_rec
comparator.io.b := t_rec_resized
comparator.io.signaling := false.B
comparator.io.gt
}
override def withWidthOf(t: Float): Float = {
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def clippedToWidthOf(t: Float): Float = {
// TODO check for overflow. Right now, we just assume that overflow doesn't happen
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def relu: Float = {
val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits)
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits)
result
}
override def zero: Float = 0.U.asTypeOf(self)
override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
}
}
implicit object DummySIntArithmetic extends Arithmetic[DummySInt] {
override implicit def cast(self: DummySInt) = new ArithmeticOps(self) {
override def *(t: DummySInt) = self.dontCare
override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare
override def +(t: DummySInt) = self.dontCare
override def -(t: DummySInt) = self.dontCare
override def >>(t: UInt) = self.dontCare
override def >(t: DummySInt): Bool = false.B
override def identity = self.dontCare
override def withWidthOf(t: DummySInt) = self.dontCare
override def clippedToWidthOf(t: DummySInt) = self.dontCare
override def relu = self.dontCare
override def zero = self.dontCare
override def minimum: DummySInt = self.dontCare
}
}
}
| module MacUnit_225( // @[PE.scala:14:7]
input clock, // @[PE.scala:14:7]
input reset, // @[PE.scala:14:7]
input [7:0] io_in_a, // @[PE.scala:16:14]
input [7:0] io_in_b, // @[PE.scala:16:14]
input [31:0] io_in_c, // @[PE.scala:16:14]
output [19:0] io_out_d // @[PE.scala:16:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7]
wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7]
wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7]
wire [19:0] io_out_d_0; // @[PE.scala:14:7]
wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7]
wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7]
wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54]
wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54]
assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12]
assign io_out_d = io_out_d_0; // @[PE.scala:14:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Consts.scala:
package shuttle.common
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util.Str
import freechips.rocketchip.rocket.RVCExpander
trait RISCVConstants
{
// abstract out instruction decode magic numbers
val RD_MSB = 11
val RD_LSB = 7
val RS1_MSB = 19
val RS1_LSB = 15
val RS2_MSB = 24
val RS2_LSB = 20
val RS3_MSB = 31
val RS3_LSB = 27
val CSR_ADDR_MSB = 31
val CSR_ADDR_LSB = 20
val CSR_ADDR_SZ = 12
// location of the fifth bit in the shamt (for checking for illegal ops for SRAIW,etc.)
val SHAMT_5_BIT = 25
val LONGEST_IMM_SZ = 20
val X0 = 0.U
val RA = 1.U // return address register
// memory consistency model
// The C/C++ atomics MCM requires that two loads to the same address maintain program order.
// The Cortex A9 does NOT enforce load/load ordering (which leads to buggy behavior).
val MCM_ORDER_DEPENDENT_LOADS = true
val jal_opc = (0x6f).U
val jalr_opc = (0x67).U
def ExpandRVC(inst: UInt)(implicit p: Parameters): UInt = {
val rvc_exp = Module(new RVCExpander)
rvc_exp.io.in := inst
Mux(rvc_exp.io.rvc, rvc_exp.io.out.bits, inst)
}
// Note: Accepts only EXPANDED rvc instructions
def ComputeBranchTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = {
val b_imm32 = Cat(Fill(20,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W))
((pc.asSInt + b_imm32.asSInt).asSInt & (-2).S).asUInt
}
// Note: Accepts only EXPANDED rvc instructions
def ComputeJALTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = {
val j_imm32 = Cat(Fill(12,inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W))
((pc.asSInt + j_imm32.asSInt).asSInt & (-2).S).asUInt
}
}
File Frontend.scala:
package shuttle.ifu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.rocket._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.tile._
import freechips.rocketchip.util._
import freechips.rocketchip.util.property._
import shuttle.common._
trait HasShuttleFrontendParameters extends HasL1ICacheParameters
{
def fetchAlign(addr: UInt) = ~(~addr | (fetchBytes-1).U)
def blockAlign(addr: UInt) = ~(~addr | (cacheParams.blockBytes-1).U)
def fetchIdx(addr: UInt) = addr >> log2Ceil(fetchBytes)
def nextFetch(addr: UInt) = fetchAlign(addr) + fetchBytes.U
def fetchMask(addr: UInt) = {
val idx = addr.extract(log2Ceil(fetchWidth)+log2Ceil(coreInstBytes)-1, log2Ceil(coreInstBytes))
((BigInt(1) << fetchWidth)-1).U << idx
}
}
class ShuttleFetchBundle(implicit val p: Parameters) extends Bundle
with HasShuttleFrontendParameters
with HasCoreParameters
{
val btbParams = tileParams.btb.get
val pc = Output(UInt(vaddrBitsExtended.W))
val next_pc = Output(Valid(UInt(vaddrBitsExtended.W)))
val edge_inst = Output(Bool()) // True if 1st instruction in this bundle is pc - 2
val insts = Output(Vec(fetchWidth, Bits(32.W)))
val exp_insts = Output(Vec(fetchWidth, Bits(32.W)))
val pcs = Output(Vec(fetchWidth, UInt(vaddrBitsExtended.W)))
val mask = Output(UInt(fetchWidth.W)) // mark which words are valid instructions
val btb_resp = Output(Valid(new BTBResp))
val ras_head = Output(UInt(log2Ceil(btbParams.nRAS).W))
val br_mask = Output(UInt(fetchWidth.W))
val xcpt_pf_if = Output(Bool()) // I-TLB miss (instruction fetch fault).
val xcpt_ae_if = Output(Bool()) // Access exception.
val end_half = Valid(UInt(16.W))
}
class ShuttleFrontend(val icacheParams: ICacheParams, staticIdForMetadataUseOnly: Int)(implicit p: Parameters) extends LazyModule
{
lazy val module = new ShuttleFrontendModule(this)
val icache = LazyModule(new ShuttleICache(icacheParams, staticIdForMetadataUseOnly))
val masterNode = icache.masterNode
val resetVectorSinkNode = BundleBridgeSink[UInt](Some(() =>
UInt(masterNode.edges.out.head.bundle.addressBits.W)))
}
class RASUpdate(implicit p: Parameters) extends CoreBundle()(p) {
val btbParams = tileParams.btb.get
val head = UInt(log2Ceil(btbParams.nRAS).W)
val addr = UInt(vaddrBitsExtended.W)
}
class ShuttleFrontendIO(implicit p: Parameters) extends CoreBundle()(p) {
val btbParams = tileParams.btb.get
val redirect_flush = Output(Bool())
val redirect_val = Output(Bool())
val redirect_pc = Output(UInt(vaddrBitsExtended.W))
val redirect_ras_head = Output(UInt(log2Ceil(btbParams.nRAS).W))
val sfence = Valid(new SFenceReq)
val flush_icache = Output(Bool())
val resp = Flipped(Vec(retireWidth, Decoupled(new ShuttleUOP)))
val peek = Flipped(Vec(retireWidth, Valid(new ShuttleUOP)))
val btb_update = Valid(new ShuttleBTBUpdate)
val bht_update = Valid(new BHTUpdate)
val ras_update = Valid(new RASUpdate)
}
class ShuttleFrontendBundle(val outer: ShuttleFrontend) extends CoreBundle()(outer.p)
{
val cpu = Flipped(new ShuttleFrontendIO)
val ptw = new TLBPTWIO()
}
class ShuttleFrontendModule(outer: ShuttleFrontend) extends LazyModuleImp(outer)
with HasShuttleFrontendParameters
with HasCoreParameters
with RISCVConstants
{
val io = IO(new ShuttleFrontendBundle(outer))
val io_reset_vector = outer.resetVectorSinkNode.bundle
implicit val edge = outer.masterNode.edges.out(0)
require(fetchWidth*coreInstBytes == outer.icacheParams.fetchBytes)
val btbParams = tileParams.btb.get
val icache = outer.icache.module
icache.io.invalidate := io.cpu.flush_icache
val tlb = Module(new TLB(true, log2Ceil(fetchBytes), TLBConfig(nTLBSets, nTLBWays)))
io.ptw <> tlb.io.ptw
val btb = Module(new ShuttleBTB)
val ras = Reg(Vec(btbParams.nRAS, UInt(vaddrBitsExtended.W)))
// TODO add RAS
btb.io.flush := false.B
btb.io.btb_update := io.cpu.btb_update
btb.io.bht_update := io.cpu.bht_update
// --------------------------------------------------------
// **** NextPC Select (F0) ****
// Send request to ICache
// -----------------------------
val s0_vpc = WireInit(0.U(vaddrBitsExtended.W))
val s0_valid = WireInit(false.B)
val s0_ras_head = WireInit(0.U(log2Ceil(btbParams.nRAS).W))
val s0_is_replay = WireInit(false.B)
val s0_replay_resp = Wire(new TLBResp)
val s0_replay_ppc = Wire(UInt(paddrBits.W))
icache.io.req.valid := s0_valid
icache.io.req.bits := s0_vpc
// --------------------------------------------------------
// **** ICache Access (F1) ****
// Translate VPC
// --------------------------------------------------------
val s1_vpc = RegNext(s0_vpc)
val s1_ras_head = WireInit(RegNext(s0_ras_head))
val s1_valid = RegNext(s0_valid, false.B)
val s1_is_replay = RegNext(s0_is_replay)
val f1_clear = WireInit(false.B)
tlb.io.req.valid := (s1_valid && !s1_is_replay && !f1_clear && !io.cpu.sfence.valid)
tlb.io.req.bits.cmd := DontCare
tlb.io.req.bits.vaddr := Mux(io.cpu.sfence.valid, io.cpu.sfence.bits.addr, s1_vpc)
tlb.io.req.bits.passthrough := false.B
tlb.io.req.bits.size := log2Ceil(coreInstBytes * fetchWidth).U
tlb.io.req.bits.v := io.ptw.status.v
tlb.io.req.bits.prv := io.ptw.status.prv
tlb.io.sfence := io.cpu.sfence
tlb.io.kill := false.B
btb.io.req.valid := s1_valid && !io.cpu.sfence.valid
btb.io.req.bits.addr := fetchAlign(s1_vpc)
val s1_tlb_miss = !s1_is_replay && (tlb.io.resp.miss || io.cpu.sfence.valid)
val s1_tlb_resp = Mux(s1_is_replay, RegNext(s0_replay_resp), tlb.io.resp)
val s1_ppc = Mux(s1_is_replay, RegNext(s0_replay_ppc), tlb.io.resp.paddr)
icache.io.s1_paddr := s1_ppc
icache.io.s1_kill := tlb.io.resp.miss || f1_clear
val f1_mask = fetchMask(s1_vpc)
val f1_next_fetch = nextFetch(s1_vpc)
val f1_do_redirect = btb.io.resp.valid && btb.io.resp.bits.taken
val f1_predicted_target = Mux(f1_do_redirect,
btb.io.resp.bits.target.sextTo(vaddrBitsExtended),
f1_next_fetch)
when (s1_valid) {
// Stop fetching on fault
s0_valid := true.B
s0_vpc := f1_predicted_target
s0_is_replay := false.B
s0_ras_head := s1_ras_head
}
btb.io.bht_advance.valid := s1_valid && btb.io.resp.valid
btb.io.bht_advance.bits := btb.io.resp.bits
// --------------------------------------------------------
// **** ICache Response (F2) ****
// --------------------------------------------------------
val s2_valid = RegNext(s1_valid && !f1_clear, false.B)
val s2_vpc = RegNext(s1_vpc)
val s2_ppc = RegNext(s1_ppc)
val s2_ras_head = RegNext(s1_ras_head)
val f2_clear = WireInit(false.B)
val s2_tlb_resp = RegNext(s1_tlb_resp)
val s2_tlb_miss = RegNext(s1_tlb_miss)
val s2_is_replay = RegNext(s1_is_replay) && s2_valid
val s2_xcpt = s2_valid && (s2_tlb_resp.ae.inst || s2_tlb_resp.pf.inst) && !s2_is_replay
val s2_btb_resp = RegNext(btb.io.resp)
val f3_ready = Wire(Bool())
icache.io.s2_kill := s2_xcpt
val f2_fetch_mask = fetchMask(s2_vpc)
val f2_next_fetch = RegNext(f1_next_fetch)
val f2_aligned_pc = fetchAlign(s2_vpc)
val f2_inst_mask = Wire(Vec(fetchWidth, Bool()))
val f2_call_mask = Wire(Vec(fetchWidth, Bool()))
val f2_ret_mask = Wire(Vec(fetchWidth, Bool()))
val f2_do_call = (f2_call_mask.asUInt & f2_inst_mask.asUInt) =/= 0.U
val f2_do_ret = (f2_ret_mask.asUInt & f2_inst_mask.asUInt) =/= 0.U
val f2_npc_plus4_mask = Wire(Vec(fetchWidth, Bool()))
val f2_do_redirect = WireInit(false.B)
val f2_redirect_bridx = WireInit(0.U(log2Ceil(fetchWidth).W))
val f2_predicted_target = Mux(f2_do_redirect,
Mux(f2_do_ret, ras(s2_ras_head), RegNext(f1_predicted_target)),
RegNext(f1_next_fetch))
val ras_write_val = WireInit(false.B)
val ras_write_idx = WireInit(0.U(log2Ceil(btbParams.nRAS).W))
val ras_write_addr = WireInit(0.U(vaddrBitsExtended.W))
val ras_next_head = Mux(f2_do_call, Mux(s2_ras_head === (btbParams.nRAS-1).U, 0.U, s2_ras_head + 1.U),
Mux(f2_do_ret, Mux(s2_ras_head === 0.U, (btbParams.nRAS-1).U, s2_ras_head - 1.U), s2_ras_head))
when ((f2_do_call || f2_do_ret) && s2_valid && f3_ready && icache.io.resp.valid) {
s0_ras_head := ras_next_head
s1_ras_head := ras_next_head
when (f2_do_call) {
ras_write_val := true.B
ras_write_idx := ras_next_head
ras_write_addr := f2_aligned_pc + (f2_redirect_bridx << 1) + Mux(f2_npc_plus4_mask(s2_btb_resp.bits.bridx), 4.U, 2.U)
}
}
when (io.cpu.ras_update.valid || (RegNext(ras_write_val && !io.cpu.redirect_val) && !io.cpu.redirect_val) ) {
val idx = Mux(io.cpu.ras_update.valid, io.cpu.ras_update.bits.head, RegNext(ras_write_idx))
val addr = Mux(io.cpu.ras_update.valid, io.cpu.ras_update.bits.addr, RegNext(ras_write_addr))
ras(idx) := addr
}
// Tracks trailing 16b of previous fetch packet
val f2_prev_half = Reg(UInt(16.W))
// Tracks if last fetchpacket contained a half-inst
val f2_prev_is_half = RegInit(false.B)
val f2_fetch_bundle = Wire(new ShuttleFetchBundle)
f2_fetch_bundle := DontCare
f2_fetch_bundle.pc := s2_vpc
f2_fetch_bundle.next_pc.valid := f2_do_redirect
f2_fetch_bundle.next_pc.bits := f2_predicted_target
f2_fetch_bundle.xcpt_pf_if := s2_tlb_resp.pf.inst
f2_fetch_bundle.xcpt_ae_if := s2_tlb_resp.ae.inst
f2_fetch_bundle.mask := f2_inst_mask.asUInt
f2_fetch_bundle.btb_resp := s2_btb_resp
f2_fetch_bundle.ras_head := s2_ras_head
def isRVC(inst: UInt) = (inst(1,0) =/= 3.U)
def isJALR(exp_inst: UInt) = exp_inst(6,0) === Instructions.JALR.value.asUInt(6,0)
def isJump(exp_inst: UInt) = exp_inst(6,0) === Instructions.JAL.value.asUInt(6,0)
def isCall(exp_inst: UInt) = (isJALR(exp_inst) || isJump(exp_inst)) && exp_inst(7)
def isRet(exp_inst: UInt) = isJALR(exp_inst) && !exp_inst(7) && BitPat("b00?01") === exp_inst(19,15)
def isBr(exp_inst: UInt) = exp_inst(6,0) === Instructions.BEQ.value.asUInt(6,0)
val icache_data = icache.io.resp.bits
var redir_found = false.B
for (i <- 0 until fetchWidth) {
val valid = Wire(Bool())
f2_inst_mask(i) := s2_valid && f2_fetch_mask(i) && valid && !redir_found
f2_fetch_bundle.pcs(i) := f2_aligned_pc + (i << 1).U - ((f2_fetch_bundle.edge_inst && (i == 0).B) << 1)
when (!valid && s2_btb_resp.valid && s2_btb_resp.bits.bridx === i.U) {
btb.io.flush := true.B
}
f2_call_mask(i) := isCall(f2_fetch_bundle.exp_insts(i))
f2_ret_mask(i) := isRet(f2_fetch_bundle.exp_insts(i))
f2_npc_plus4_mask(i) := !isRVC(f2_fetch_bundle.insts(i))
if (i == 0)
f2_npc_plus4_mask(i) := !isRVC(f2_fetch_bundle.insts(i)) && !f2_fetch_bundle.edge_inst
val redir_br = (isBr(f2_fetch_bundle.exp_insts(i)) &&
((s2_btb_resp.valid && s2_btb_resp.bits.bridx === i.U && s2_btb_resp.bits.taken && s2_btb_resp.bits.bht.taken)))
val redir = f2_inst_mask(i) && (isJALR(f2_fetch_bundle.exp_insts(i)) || isJump(f2_fetch_bundle.exp_insts(i)) || redir_br)
when (redir) {
f2_do_redirect := true.B
f2_redirect_bridx := i.U
}
redir_found = redir_found || redir
if (i == 0) {
valid := true.B
when (f2_prev_is_half) {
val expanded = ExpandRVC(Cat(icache_data(15,0), f2_prev_half))
f2_fetch_bundle.insts(i) := Cat(icache_data(15,0), f2_prev_half)
f2_fetch_bundle.exp_insts(i) := expanded
f2_fetch_bundle.edge_inst := true.B
} .otherwise {
val expanded = ExpandRVC(icache_data(31,0))
f2_fetch_bundle.insts(i) := icache_data(31,0)
f2_fetch_bundle.exp_insts(i) := expanded
f2_fetch_bundle.edge_inst := false.B
}
} else if (i == 1) {
// Need special case since 0th instruction may carry over the wrap around
val inst = icache_data(47,16)
val expanded = ExpandRVC(inst)
f2_fetch_bundle.insts(i) := inst
f2_fetch_bundle.exp_insts(i) := expanded
valid := f2_prev_is_half || !(f2_inst_mask(i-1) && !isRVC(f2_fetch_bundle.insts(i-1)))
} else if (i == fetchWidth - 1) {
val inst = Cat(0.U(16.W), icache_data(fetchWidth*16-1,(fetchWidth-1)*16))
val expanded = ExpandRVC(inst)
f2_fetch_bundle.insts(i) := inst
f2_fetch_bundle.exp_insts(i) := expanded
valid := !((f2_inst_mask(i-1) && !isRVC(f2_fetch_bundle.insts(i-1))) || !isRVC(inst))
} else {
val inst = icache_data(i*16+32-1,i*16)
val expanded = ExpandRVC(inst)
f2_fetch_bundle.insts(i) := inst
f2_fetch_bundle.exp_insts(i) := expanded
valid := !(f2_inst_mask(i-1) && !isRVC(f2_fetch_bundle.insts(i-1)))
}
}
val last_inst = f2_fetch_bundle.insts(fetchWidth-1)(15,0)
f2_fetch_bundle.end_half.valid := (!(f2_inst_mask(fetchWidth-2) && !isRVC(f2_fetch_bundle.insts(fetchWidth-2))) && !isRVC(last_inst))
f2_fetch_bundle.end_half.bits := last_inst
when ((s2_valid && !icache.io.resp.valid) ||
(s2_valid && icache.io.resp.valid && !f3_ready)) {
s0_valid := (!s2_tlb_resp.ae.inst && !s2_tlb_resp.pf.inst) || s2_is_replay || s2_tlb_miss || !f3_ready
s0_vpc := s2_vpc
s0_ras_head := s2_ras_head
s0_is_replay := s2_valid && icache.io.resp.valid
f1_clear := true.B
} .elsewhen (s2_valid && f3_ready) {
f2_prev_is_half := f2_fetch_bundle.end_half.valid && !f2_do_redirect
f2_prev_half := f2_fetch_bundle.end_half.bits
when ((s1_valid && (s1_vpc =/= f2_predicted_target)) || !s1_valid) {
f1_clear := true.B
s0_valid := !((s2_tlb_resp.ae.inst || s2_tlb_resp.pf.inst) && !s2_is_replay)
s0_vpc := f2_predicted_target
s0_ras_head := ras_next_head
s0_is_replay := false.B
}
}
s0_replay_resp := s2_tlb_resp
s0_replay_ppc := s2_ppc
val fb = Module(new ShuttleFetchBuffer)
fb.io.enq.valid := (s2_valid && !f2_clear &&
(icache.io.resp.valid || ((s2_tlb_resp.ae.inst || s2_tlb_resp.pf.inst) && !s2_tlb_miss))
)
fb.io.enq.bits := f2_fetch_bundle
f3_ready := fb.io.enq.ready
io.cpu.resp <> fb.io.deq
io.cpu.peek := fb.io.peek
fb.io.clear := false.B
when (io.cpu.redirect_flush) {
fb.io.clear := true.B
f2_clear := true.B
f2_prev_is_half := false.B
f1_clear := true.B
s0_valid := io.cpu.redirect_val
s0_vpc := io.cpu.redirect_pc
s0_ras_head := io.cpu.redirect_ras_head
s0_is_replay := false.B
}
val jump_to_reset = RegInit(true.B)
when (jump_to_reset) {
s0_valid := true.B
s0_vpc := io_reset_vector
s0_ras_head := (btbParams.nRAS-1).U
fb.io.clear := true.B
f2_clear := true.B
f2_prev_is_half := false.B
f1_clear := true.B
jump_to_reset := false.B
}
//dontTouch(io)
}
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
| module ShuttleFrontend( // @[Frontend.scala:93:7]
input clock, // @[Frontend.scala:93:7]
input reset, // @[Frontend.scala:93:7]
input auto_icache_master_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_icache_master_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_icache_master_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
input auto_icache_master_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_icache_master_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_icache_master_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_icache_master_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input auto_icache_master_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_icache_master_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_icache_master_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_icache_master_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_icache_master_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input io_cpu_redirect_flush, // @[Frontend.scala:98:14]
input io_cpu_redirect_val, // @[Frontend.scala:98:14]
input [39:0] io_cpu_redirect_pc, // @[Frontend.scala:98:14]
input [2:0] io_cpu_redirect_ras_head, // @[Frontend.scala:98:14]
input io_cpu_sfence_valid, // @[Frontend.scala:98:14]
input io_cpu_sfence_bits_rs1, // @[Frontend.scala:98:14]
input io_cpu_sfence_bits_rs2, // @[Frontend.scala:98:14]
input [38:0] io_cpu_sfence_bits_addr, // @[Frontend.scala:98:14]
input io_cpu_sfence_bits_asid, // @[Frontend.scala:98:14]
input io_cpu_sfence_bits_hv, // @[Frontend.scala:98:14]
input io_cpu_sfence_bits_hg, // @[Frontend.scala:98:14]
input io_cpu_flush_icache, // @[Frontend.scala:98:14]
input io_cpu_resp_0_ready, // @[Frontend.scala:98:14]
output io_cpu_resp_0_valid, // @[Frontend.scala:98:14]
output [31:0] io_cpu_resp_0_bits_inst, // @[Frontend.scala:98:14]
output [31:0] io_cpu_resp_0_bits_raw_inst, // @[Frontend.scala:98:14]
output [39:0] io_cpu_resp_0_bits_pc, // @[Frontend.scala:98:14]
output io_cpu_resp_0_bits_edge_inst, // @[Frontend.scala:98:14]
output io_cpu_resp_0_bits_rvc, // @[Frontend.scala:98:14]
output io_cpu_resp_0_bits_btb_resp_valid, // @[Frontend.scala:98:14]
output [1:0] io_cpu_resp_0_bits_btb_resp_bits_cfiType, // @[Frontend.scala:98:14]
output io_cpu_resp_0_bits_btb_resp_bits_taken, // @[Frontend.scala:98:14]
output [3:0] io_cpu_resp_0_bits_btb_resp_bits_mask, // @[Frontend.scala:98:14]
output [1:0] io_cpu_resp_0_bits_btb_resp_bits_bridx, // @[Frontend.scala:98:14]
output [38:0] io_cpu_resp_0_bits_btb_resp_bits_target, // @[Frontend.scala:98:14]
output [5:0] io_cpu_resp_0_bits_btb_resp_bits_entry, // @[Frontend.scala:98:14]
output [7:0] io_cpu_resp_0_bits_btb_resp_bits_bht_history, // @[Frontend.scala:98:14]
output [1:0] io_cpu_resp_0_bits_btb_resp_bits_bht_value, // @[Frontend.scala:98:14]
output io_cpu_resp_0_bits_sfb_br, // @[Frontend.scala:98:14]
output io_cpu_resp_0_bits_next_pc_valid, // @[Frontend.scala:98:14]
output [39:0] io_cpu_resp_0_bits_next_pc_bits, // @[Frontend.scala:98:14]
output [2:0] io_cpu_resp_0_bits_ras_head, // @[Frontend.scala:98:14]
output io_cpu_resp_0_bits_xcpt, // @[Frontend.scala:98:14]
output [63:0] io_cpu_resp_0_bits_xcpt_cause, // @[Frontend.scala:98:14]
output [1:0] io_cpu_resp_0_bits_mem_size, // @[Frontend.scala:98:14]
input io_cpu_resp_1_ready, // @[Frontend.scala:98:14]
output io_cpu_resp_1_valid, // @[Frontend.scala:98:14]
output [31:0] io_cpu_resp_1_bits_inst, // @[Frontend.scala:98:14]
output [31:0] io_cpu_resp_1_bits_raw_inst, // @[Frontend.scala:98:14]
output [39:0] io_cpu_resp_1_bits_pc, // @[Frontend.scala:98:14]
output io_cpu_resp_1_bits_edge_inst, // @[Frontend.scala:98:14]
output io_cpu_resp_1_bits_rvc, // @[Frontend.scala:98:14]
output io_cpu_resp_1_bits_btb_resp_valid, // @[Frontend.scala:98:14]
output [1:0] io_cpu_resp_1_bits_btb_resp_bits_cfiType, // @[Frontend.scala:98:14]
output io_cpu_resp_1_bits_btb_resp_bits_taken, // @[Frontend.scala:98:14]
output [3:0] io_cpu_resp_1_bits_btb_resp_bits_mask, // @[Frontend.scala:98:14]
output [1:0] io_cpu_resp_1_bits_btb_resp_bits_bridx, // @[Frontend.scala:98:14]
output [38:0] io_cpu_resp_1_bits_btb_resp_bits_target, // @[Frontend.scala:98:14]
output [5:0] io_cpu_resp_1_bits_btb_resp_bits_entry, // @[Frontend.scala:98:14]
output [7:0] io_cpu_resp_1_bits_btb_resp_bits_bht_history, // @[Frontend.scala:98:14]
output [1:0] io_cpu_resp_1_bits_btb_resp_bits_bht_value, // @[Frontend.scala:98:14]
output io_cpu_resp_1_bits_sfb_br, // @[Frontend.scala:98:14]
output io_cpu_resp_1_bits_next_pc_valid, // @[Frontend.scala:98:14]
output [39:0] io_cpu_resp_1_bits_next_pc_bits, // @[Frontend.scala:98:14]
output [2:0] io_cpu_resp_1_bits_ras_head, // @[Frontend.scala:98:14]
output io_cpu_resp_1_bits_xcpt, // @[Frontend.scala:98:14]
output [63:0] io_cpu_resp_1_bits_xcpt_cause, // @[Frontend.scala:98:14]
output [1:0] io_cpu_resp_1_bits_mem_size, // @[Frontend.scala:98:14]
output io_cpu_peek_0_valid, // @[Frontend.scala:98:14]
output [31:0] io_cpu_peek_0_bits_inst, // @[Frontend.scala:98:14]
output [31:0] io_cpu_peek_0_bits_raw_inst, // @[Frontend.scala:98:14]
output [39:0] io_cpu_peek_0_bits_pc, // @[Frontend.scala:98:14]
output io_cpu_peek_0_bits_edge_inst, // @[Frontend.scala:98:14]
output io_cpu_peek_0_bits_rvc, // @[Frontend.scala:98:14]
output io_cpu_peek_0_bits_btb_resp_valid, // @[Frontend.scala:98:14]
output [1:0] io_cpu_peek_0_bits_btb_resp_bits_cfiType, // @[Frontend.scala:98:14]
output io_cpu_peek_0_bits_btb_resp_bits_taken, // @[Frontend.scala:98:14]
output [3:0] io_cpu_peek_0_bits_btb_resp_bits_mask, // @[Frontend.scala:98:14]
output [1:0] io_cpu_peek_0_bits_btb_resp_bits_bridx, // @[Frontend.scala:98:14]
output [38:0] io_cpu_peek_0_bits_btb_resp_bits_target, // @[Frontend.scala:98:14]
output [5:0] io_cpu_peek_0_bits_btb_resp_bits_entry, // @[Frontend.scala:98:14]
output [7:0] io_cpu_peek_0_bits_btb_resp_bits_bht_history, // @[Frontend.scala:98:14]
output [1:0] io_cpu_peek_0_bits_btb_resp_bits_bht_value, // @[Frontend.scala:98:14]
output io_cpu_peek_0_bits_sfb_br, // @[Frontend.scala:98:14]
output io_cpu_peek_0_bits_next_pc_valid, // @[Frontend.scala:98:14]
output [39:0] io_cpu_peek_0_bits_next_pc_bits, // @[Frontend.scala:98:14]
output [2:0] io_cpu_peek_0_bits_ras_head, // @[Frontend.scala:98:14]
output io_cpu_peek_0_bits_xcpt, // @[Frontend.scala:98:14]
output [63:0] io_cpu_peek_0_bits_xcpt_cause, // @[Frontend.scala:98:14]
output [1:0] io_cpu_peek_0_bits_mem_size, // @[Frontend.scala:98:14]
output io_cpu_peek_1_valid, // @[Frontend.scala:98:14]
output [31:0] io_cpu_peek_1_bits_inst, // @[Frontend.scala:98:14]
output [31:0] io_cpu_peek_1_bits_raw_inst, // @[Frontend.scala:98:14]
output [39:0] io_cpu_peek_1_bits_pc, // @[Frontend.scala:98:14]
output io_cpu_peek_1_bits_edge_inst, // @[Frontend.scala:98:14]
output io_cpu_peek_1_bits_rvc, // @[Frontend.scala:98:14]
output io_cpu_peek_1_bits_btb_resp_valid, // @[Frontend.scala:98:14]
output [1:0] io_cpu_peek_1_bits_btb_resp_bits_cfiType, // @[Frontend.scala:98:14]
output io_cpu_peek_1_bits_btb_resp_bits_taken, // @[Frontend.scala:98:14]
output [3:0] io_cpu_peek_1_bits_btb_resp_bits_mask, // @[Frontend.scala:98:14]
output [1:0] io_cpu_peek_1_bits_btb_resp_bits_bridx, // @[Frontend.scala:98:14]
output [38:0] io_cpu_peek_1_bits_btb_resp_bits_target, // @[Frontend.scala:98:14]
output [5:0] io_cpu_peek_1_bits_btb_resp_bits_entry, // @[Frontend.scala:98:14]
output [7:0] io_cpu_peek_1_bits_btb_resp_bits_bht_history, // @[Frontend.scala:98:14]
output [1:0] io_cpu_peek_1_bits_btb_resp_bits_bht_value, // @[Frontend.scala:98:14]
output io_cpu_peek_1_bits_sfb_br, // @[Frontend.scala:98:14]
output io_cpu_peek_1_bits_next_pc_valid, // @[Frontend.scala:98:14]
output [39:0] io_cpu_peek_1_bits_next_pc_bits, // @[Frontend.scala:98:14]
output [2:0] io_cpu_peek_1_bits_ras_head, // @[Frontend.scala:98:14]
output io_cpu_peek_1_bits_xcpt, // @[Frontend.scala:98:14]
output [63:0] io_cpu_peek_1_bits_xcpt_cause, // @[Frontend.scala:98:14]
output [1:0] io_cpu_peek_1_bits_mem_size, // @[Frontend.scala:98:14]
input io_cpu_btb_update_valid, // @[Frontend.scala:98:14]
input [1:0] io_cpu_btb_update_bits_prediction_cfiType, // @[Frontend.scala:98:14]
input io_cpu_btb_update_bits_prediction_taken, // @[Frontend.scala:98:14]
input [3:0] io_cpu_btb_update_bits_prediction_mask, // @[Frontend.scala:98:14]
input [1:0] io_cpu_btb_update_bits_prediction_bridx, // @[Frontend.scala:98:14]
input [38:0] io_cpu_btb_update_bits_prediction_target, // @[Frontend.scala:98:14]
input [5:0] io_cpu_btb_update_bits_prediction_entry, // @[Frontend.scala:98:14]
input [7:0] io_cpu_btb_update_bits_prediction_bht_history, // @[Frontend.scala:98:14]
input [1:0] io_cpu_btb_update_bits_prediction_bht_value, // @[Frontend.scala:98:14]
input [38:0] io_cpu_btb_update_bits_pc, // @[Frontend.scala:98:14]
input [38:0] io_cpu_btb_update_bits_target, // @[Frontend.scala:98:14]
input io_cpu_btb_update_bits_isValid, // @[Frontend.scala:98:14]
input [38:0] io_cpu_btb_update_bits_br_pc, // @[Frontend.scala:98:14]
input [1:0] io_cpu_btb_update_bits_cfiType, // @[Frontend.scala:98:14]
input io_cpu_btb_update_bits_mispredict, // @[Frontend.scala:98:14]
input io_cpu_bht_update_valid, // @[Frontend.scala:98:14]
input [7:0] io_cpu_bht_update_bits_prediction_history, // @[Frontend.scala:98:14]
input [1:0] io_cpu_bht_update_bits_prediction_value, // @[Frontend.scala:98:14]
input [38:0] io_cpu_bht_update_bits_pc, // @[Frontend.scala:98:14]
input io_cpu_bht_update_bits_branch, // @[Frontend.scala:98:14]
input io_cpu_bht_update_bits_taken, // @[Frontend.scala:98:14]
input io_cpu_bht_update_bits_mispredict, // @[Frontend.scala:98:14]
input io_cpu_ras_update_valid, // @[Frontend.scala:98:14]
input [2:0] io_cpu_ras_update_bits_head, // @[Frontend.scala:98:14]
input [39:0] io_cpu_ras_update_bits_addr, // @[Frontend.scala:98:14]
input io_ptw_req_ready, // @[Frontend.scala:98:14]
output io_ptw_req_valid, // @[Frontend.scala:98:14]
output [26:0] io_ptw_req_bits_bits_addr, // @[Frontend.scala:98:14]
output io_ptw_req_bits_bits_need_gpa, // @[Frontend.scala:98:14]
input io_ptw_resp_valid, // @[Frontend.scala:98:14]
input io_ptw_resp_bits_ae_ptw, // @[Frontend.scala:98:14]
input io_ptw_resp_bits_ae_final, // @[Frontend.scala:98:14]
input io_ptw_resp_bits_pf, // @[Frontend.scala:98:14]
input io_ptw_resp_bits_gf, // @[Frontend.scala:98:14]
input io_ptw_resp_bits_hr, // @[Frontend.scala:98:14]
input io_ptw_resp_bits_hw, // @[Frontend.scala:98:14]
input io_ptw_resp_bits_hx, // @[Frontend.scala:98:14]
input [9:0] io_ptw_resp_bits_pte_reserved_for_future, // @[Frontend.scala:98:14]
input [43:0] io_ptw_resp_bits_pte_ppn, // @[Frontend.scala:98:14]
input [1:0] io_ptw_resp_bits_pte_reserved_for_software, // @[Frontend.scala:98:14]
input io_ptw_resp_bits_pte_d, // @[Frontend.scala:98:14]
input io_ptw_resp_bits_pte_a, // @[Frontend.scala:98:14]
input io_ptw_resp_bits_pte_g, // @[Frontend.scala:98:14]
input io_ptw_resp_bits_pte_u, // @[Frontend.scala:98:14]
input io_ptw_resp_bits_pte_x, // @[Frontend.scala:98:14]
input io_ptw_resp_bits_pte_w, // @[Frontend.scala:98:14]
input io_ptw_resp_bits_pte_r, // @[Frontend.scala:98:14]
input io_ptw_resp_bits_pte_v, // @[Frontend.scala:98:14]
input [1:0] io_ptw_resp_bits_level, // @[Frontend.scala:98:14]
input io_ptw_resp_bits_homogeneous, // @[Frontend.scala:98:14]
input io_ptw_resp_bits_gpa_valid, // @[Frontend.scala:98:14]
input [38:0] io_ptw_resp_bits_gpa_bits, // @[Frontend.scala:98:14]
input io_ptw_resp_bits_gpa_is_pte, // @[Frontend.scala:98:14]
input [3:0] io_ptw_ptbr_mode, // @[Frontend.scala:98:14]
input [43:0] io_ptw_ptbr_ppn, // @[Frontend.scala:98:14]
input io_ptw_status_debug, // @[Frontend.scala:98:14]
input io_ptw_status_cease, // @[Frontend.scala:98:14]
input io_ptw_status_wfi, // @[Frontend.scala:98:14]
input [1:0] io_ptw_status_dprv, // @[Frontend.scala:98:14]
input io_ptw_status_dv, // @[Frontend.scala:98:14]
input [1:0] io_ptw_status_prv, // @[Frontend.scala:98:14]
input io_ptw_status_v, // @[Frontend.scala:98:14]
input io_ptw_status_sd, // @[Frontend.scala:98:14]
input io_ptw_status_mpv, // @[Frontend.scala:98:14]
input io_ptw_status_gva, // @[Frontend.scala:98:14]
input io_ptw_status_tsr, // @[Frontend.scala:98:14]
input io_ptw_status_tw, // @[Frontend.scala:98:14]
input io_ptw_status_tvm, // @[Frontend.scala:98:14]
input io_ptw_status_mxr, // @[Frontend.scala:98:14]
input io_ptw_status_sum, // @[Frontend.scala:98:14]
input io_ptw_status_mprv, // @[Frontend.scala:98:14]
input [1:0] io_ptw_status_fs, // @[Frontend.scala:98:14]
input [1:0] io_ptw_status_mpp, // @[Frontend.scala:98:14]
input io_ptw_status_spp, // @[Frontend.scala:98:14]
input io_ptw_status_mpie, // @[Frontend.scala:98:14]
input io_ptw_status_spie, // @[Frontend.scala:98:14]
input io_ptw_status_mie, // @[Frontend.scala:98:14]
input io_ptw_status_sie, // @[Frontend.scala:98:14]
input io_ptw_hstatus_spvp, // @[Frontend.scala:98:14]
input io_ptw_hstatus_spv, // @[Frontend.scala:98:14]
input io_ptw_hstatus_gva, // @[Frontend.scala:98:14]
input io_ptw_gstatus_debug, // @[Frontend.scala:98:14]
input io_ptw_gstatus_cease, // @[Frontend.scala:98:14]
input io_ptw_gstatus_wfi, // @[Frontend.scala:98:14]
input [31:0] io_ptw_gstatus_isa, // @[Frontend.scala:98:14]
input [1:0] io_ptw_gstatus_dprv, // @[Frontend.scala:98:14]
input io_ptw_gstatus_dv, // @[Frontend.scala:98:14]
input [1:0] io_ptw_gstatus_prv, // @[Frontend.scala:98:14]
input io_ptw_gstatus_v, // @[Frontend.scala:98:14]
input [22:0] io_ptw_gstatus_zero2, // @[Frontend.scala:98:14]
input io_ptw_gstatus_mpv, // @[Frontend.scala:98:14]
input io_ptw_gstatus_gva, // @[Frontend.scala:98:14]
input io_ptw_gstatus_mbe, // @[Frontend.scala:98:14]
input io_ptw_gstatus_sbe, // @[Frontend.scala:98:14]
input [1:0] io_ptw_gstatus_sxl, // @[Frontend.scala:98:14]
input [7:0] io_ptw_gstatus_zero1, // @[Frontend.scala:98:14]
input io_ptw_gstatus_tsr, // @[Frontend.scala:98:14]
input io_ptw_gstatus_tw, // @[Frontend.scala:98:14]
input io_ptw_gstatus_tvm, // @[Frontend.scala:98:14]
input io_ptw_gstatus_mxr, // @[Frontend.scala:98:14]
input io_ptw_gstatus_sum, // @[Frontend.scala:98:14]
input io_ptw_gstatus_mprv, // @[Frontend.scala:98:14]
input [1:0] io_ptw_gstatus_mpp, // @[Frontend.scala:98:14]
input [1:0] io_ptw_gstatus_vs, // @[Frontend.scala:98:14]
input io_ptw_gstatus_spp, // @[Frontend.scala:98:14]
input io_ptw_gstatus_mpie, // @[Frontend.scala:98:14]
input io_ptw_gstatus_ube, // @[Frontend.scala:98:14]
input io_ptw_gstatus_spie, // @[Frontend.scala:98:14]
input io_ptw_gstatus_upie, // @[Frontend.scala:98:14]
input io_ptw_gstatus_mie, // @[Frontend.scala:98:14]
input io_ptw_gstatus_hie, // @[Frontend.scala:98:14]
input io_ptw_gstatus_sie, // @[Frontend.scala:98:14]
input io_ptw_gstatus_uie // @[Frontend.scala:98:14]
);
wire [31:0] _expanded_rvc_exp_4_io_out_bits; // @[Consts.scala:41:25]
wire _expanded_rvc_exp_4_io_rvc; // @[Consts.scala:41:25]
wire [31:0] _expanded_rvc_exp_3_io_out_bits; // @[Consts.scala:41:25]
wire _expanded_rvc_exp_3_io_rvc; // @[Consts.scala:41:25]
wire [31:0] _expanded_rvc_exp_2_io_out_bits; // @[Consts.scala:41:25]
wire _expanded_rvc_exp_2_io_rvc; // @[Consts.scala:41:25]
wire [31:0] _expanded_rvc_exp_1_io_out_bits; // @[Consts.scala:41:25]
wire _expanded_rvc_exp_1_io_rvc; // @[Consts.scala:41:25]
wire [31:0] _expanded_rvc_exp_io_out_bits; // @[Consts.scala:41:25]
wire _expanded_rvc_exp_io_rvc; // @[Consts.scala:41:25]
wire _btb_io_resp_valid; // @[Frontend.scala:109:19]
wire [1:0] _btb_io_resp_bits_cfiType; // @[Frontend.scala:109:19]
wire _btb_io_resp_bits_taken; // @[Frontend.scala:109:19]
wire [3:0] _btb_io_resp_bits_mask; // @[Frontend.scala:109:19]
wire [1:0] _btb_io_resp_bits_bridx; // @[Frontend.scala:109:19]
wire [38:0] _btb_io_resp_bits_target; // @[Frontend.scala:109:19]
wire [5:0] _btb_io_resp_bits_entry; // @[Frontend.scala:109:19]
wire [7:0] _btb_io_resp_bits_bht_history; // @[Frontend.scala:109:19]
wire [1:0] _btb_io_resp_bits_bht_value; // @[Frontend.scala:109:19]
wire _tlb_io_resp_miss; // @[Frontend.scala:107:19]
wire [31:0] _tlb_io_resp_paddr; // @[Frontend.scala:107:19]
wire [39:0] _tlb_io_resp_gpa; // @[Frontend.scala:107:19]
wire _tlb_io_resp_pf_ld; // @[Frontend.scala:107:19]
wire _tlb_io_resp_pf_inst; // @[Frontend.scala:107:19]
wire _tlb_io_resp_ae_ld; // @[Frontend.scala:107:19]
wire _tlb_io_resp_ae_inst; // @[Frontend.scala:107:19]
wire _tlb_io_resp_ma_ld; // @[Frontend.scala:107:19]
wire _tlb_io_resp_cacheable; // @[Frontend.scala:107:19]
wire _tlb_io_resp_prefetchable; // @[Frontend.scala:107:19]
wire _icache_io_resp_valid; // @[Frontend.scala:58:26]
wire [63:0] _icache_io_resp_bits; // @[Frontend.scala:58:26]
wire auto_icache_master_out_a_ready_0 = auto_icache_master_out_a_ready; // @[Frontend.scala:93:7]
wire auto_icache_master_out_d_valid_0 = auto_icache_master_out_d_valid; // @[Frontend.scala:93:7]
wire [2:0] auto_icache_master_out_d_bits_opcode_0 = auto_icache_master_out_d_bits_opcode; // @[Frontend.scala:93:7]
wire [1:0] auto_icache_master_out_d_bits_param_0 = auto_icache_master_out_d_bits_param; // @[Frontend.scala:93:7]
wire [3:0] auto_icache_master_out_d_bits_size_0 = auto_icache_master_out_d_bits_size; // @[Frontend.scala:93:7]
wire auto_icache_master_out_d_bits_source_0 = auto_icache_master_out_d_bits_source; // @[Frontend.scala:93:7]
wire [2:0] auto_icache_master_out_d_bits_sink_0 = auto_icache_master_out_d_bits_sink; // @[Frontend.scala:93:7]
wire auto_icache_master_out_d_bits_denied_0 = auto_icache_master_out_d_bits_denied; // @[Frontend.scala:93:7]
wire [63:0] auto_icache_master_out_d_bits_data_0 = auto_icache_master_out_d_bits_data; // @[Frontend.scala:93:7]
wire auto_icache_master_out_d_bits_corrupt_0 = auto_icache_master_out_d_bits_corrupt; // @[Frontend.scala:93:7]
wire io_cpu_redirect_flush_0 = io_cpu_redirect_flush; // @[Frontend.scala:93:7]
wire io_cpu_redirect_val_0 = io_cpu_redirect_val; // @[Frontend.scala:93:7]
wire [39:0] io_cpu_redirect_pc_0 = io_cpu_redirect_pc; // @[Frontend.scala:93:7]
wire [2:0] io_cpu_redirect_ras_head_0 = io_cpu_redirect_ras_head; // @[Frontend.scala:93:7]
wire io_cpu_sfence_valid_0 = io_cpu_sfence_valid; // @[Frontend.scala:93:7]
wire io_cpu_sfence_bits_rs1_0 = io_cpu_sfence_bits_rs1; // @[Frontend.scala:93:7]
wire io_cpu_sfence_bits_rs2_0 = io_cpu_sfence_bits_rs2; // @[Frontend.scala:93:7]
wire [38:0] io_cpu_sfence_bits_addr_0 = io_cpu_sfence_bits_addr; // @[Frontend.scala:93:7]
wire io_cpu_sfence_bits_asid_0 = io_cpu_sfence_bits_asid; // @[Frontend.scala:93:7]
wire io_cpu_sfence_bits_hv_0 = io_cpu_sfence_bits_hv; // @[Frontend.scala:93:7]
wire io_cpu_sfence_bits_hg_0 = io_cpu_sfence_bits_hg; // @[Frontend.scala:93:7]
wire io_cpu_flush_icache_0 = io_cpu_flush_icache; // @[Frontend.scala:93:7]
wire io_cpu_resp_0_ready_0 = io_cpu_resp_0_ready; // @[Frontend.scala:93:7]
wire io_cpu_resp_1_ready_0 = io_cpu_resp_1_ready; // @[Frontend.scala:93:7]
wire io_cpu_btb_update_valid_0 = io_cpu_btb_update_valid; // @[Frontend.scala:93:7]
wire [1:0] io_cpu_btb_update_bits_prediction_cfiType_0 = io_cpu_btb_update_bits_prediction_cfiType; // @[Frontend.scala:93:7]
wire io_cpu_btb_update_bits_prediction_taken_0 = io_cpu_btb_update_bits_prediction_taken; // @[Frontend.scala:93:7]
wire [3:0] io_cpu_btb_update_bits_prediction_mask_0 = io_cpu_btb_update_bits_prediction_mask; // @[Frontend.scala:93:7]
wire [1:0] io_cpu_btb_update_bits_prediction_bridx_0 = io_cpu_btb_update_bits_prediction_bridx; // @[Frontend.scala:93:7]
wire [38:0] io_cpu_btb_update_bits_prediction_target_0 = io_cpu_btb_update_bits_prediction_target; // @[Frontend.scala:93:7]
wire [5:0] io_cpu_btb_update_bits_prediction_entry_0 = io_cpu_btb_update_bits_prediction_entry; // @[Frontend.scala:93:7]
wire [7:0] io_cpu_btb_update_bits_prediction_bht_history_0 = io_cpu_btb_update_bits_prediction_bht_history; // @[Frontend.scala:93:7]
wire [1:0] io_cpu_btb_update_bits_prediction_bht_value_0 = io_cpu_btb_update_bits_prediction_bht_value; // @[Frontend.scala:93:7]
wire [38:0] io_cpu_btb_update_bits_pc_0 = io_cpu_btb_update_bits_pc; // @[Frontend.scala:93:7]
wire [38:0] io_cpu_btb_update_bits_target_0 = io_cpu_btb_update_bits_target; // @[Frontend.scala:93:7]
wire io_cpu_btb_update_bits_isValid_0 = io_cpu_btb_update_bits_isValid; // @[Frontend.scala:93:7]
wire [38:0] io_cpu_btb_update_bits_br_pc_0 = io_cpu_btb_update_bits_br_pc; // @[Frontend.scala:93:7]
wire [1:0] io_cpu_btb_update_bits_cfiType_0 = io_cpu_btb_update_bits_cfiType; // @[Frontend.scala:93:7]
wire io_cpu_btb_update_bits_mispredict_0 = io_cpu_btb_update_bits_mispredict; // @[Frontend.scala:93:7]
wire io_cpu_bht_update_valid_0 = io_cpu_bht_update_valid; // @[Frontend.scala:93:7]
wire [7:0] io_cpu_bht_update_bits_prediction_history_0 = io_cpu_bht_update_bits_prediction_history; // @[Frontend.scala:93:7]
wire [1:0] io_cpu_bht_update_bits_prediction_value_0 = io_cpu_bht_update_bits_prediction_value; // @[Frontend.scala:93:7]
wire [38:0] io_cpu_bht_update_bits_pc_0 = io_cpu_bht_update_bits_pc; // @[Frontend.scala:93:7]
wire io_cpu_bht_update_bits_branch_0 = io_cpu_bht_update_bits_branch; // @[Frontend.scala:93:7]
wire io_cpu_bht_update_bits_taken_0 = io_cpu_bht_update_bits_taken; // @[Frontend.scala:93:7]
wire io_cpu_bht_update_bits_mispredict_0 = io_cpu_bht_update_bits_mispredict; // @[Frontend.scala:93:7]
wire io_cpu_ras_update_valid_0 = io_cpu_ras_update_valid; // @[Frontend.scala:93:7]
wire [2:0] io_cpu_ras_update_bits_head_0 = io_cpu_ras_update_bits_head; // @[Frontend.scala:93:7]
wire [39:0] io_cpu_ras_update_bits_addr_0 = io_cpu_ras_update_bits_addr; // @[Frontend.scala:93:7]
wire io_ptw_req_ready_0 = io_ptw_req_ready; // @[Frontend.scala:93:7]
wire io_ptw_resp_valid_0 = io_ptw_resp_valid; // @[Frontend.scala:93:7]
wire io_ptw_resp_bits_ae_ptw_0 = io_ptw_resp_bits_ae_ptw; // @[Frontend.scala:93:7]
wire io_ptw_resp_bits_ae_final_0 = io_ptw_resp_bits_ae_final; // @[Frontend.scala:93:7]
wire io_ptw_resp_bits_pf_0 = io_ptw_resp_bits_pf; // @[Frontend.scala:93:7]
wire io_ptw_resp_bits_gf_0 = io_ptw_resp_bits_gf; // @[Frontend.scala:93:7]
wire io_ptw_resp_bits_hr_0 = io_ptw_resp_bits_hr; // @[Frontend.scala:93:7]
wire io_ptw_resp_bits_hw_0 = io_ptw_resp_bits_hw; // @[Frontend.scala:93:7]
wire io_ptw_resp_bits_hx_0 = io_ptw_resp_bits_hx; // @[Frontend.scala:93:7]
wire [9:0] io_ptw_resp_bits_pte_reserved_for_future_0 = io_ptw_resp_bits_pte_reserved_for_future; // @[Frontend.scala:93:7]
wire [43:0] io_ptw_resp_bits_pte_ppn_0 = io_ptw_resp_bits_pte_ppn; // @[Frontend.scala:93:7]
wire [1:0] io_ptw_resp_bits_pte_reserved_for_software_0 = io_ptw_resp_bits_pte_reserved_for_software; // @[Frontend.scala:93:7]
wire io_ptw_resp_bits_pte_d_0 = io_ptw_resp_bits_pte_d; // @[Frontend.scala:93:7]
wire io_ptw_resp_bits_pte_a_0 = io_ptw_resp_bits_pte_a; // @[Frontend.scala:93:7]
wire io_ptw_resp_bits_pte_g_0 = io_ptw_resp_bits_pte_g; // @[Frontend.scala:93:7]
wire io_ptw_resp_bits_pte_u_0 = io_ptw_resp_bits_pte_u; // @[Frontend.scala:93:7]
wire io_ptw_resp_bits_pte_x_0 = io_ptw_resp_bits_pte_x; // @[Frontend.scala:93:7]
wire io_ptw_resp_bits_pte_w_0 = io_ptw_resp_bits_pte_w; // @[Frontend.scala:93:7]
wire io_ptw_resp_bits_pte_r_0 = io_ptw_resp_bits_pte_r; // @[Frontend.scala:93:7]
wire io_ptw_resp_bits_pte_v_0 = io_ptw_resp_bits_pte_v; // @[Frontend.scala:93:7]
wire [1:0] io_ptw_resp_bits_level_0 = io_ptw_resp_bits_level; // @[Frontend.scala:93:7]
wire io_ptw_resp_bits_homogeneous_0 = io_ptw_resp_bits_homogeneous; // @[Frontend.scala:93:7]
wire io_ptw_resp_bits_gpa_valid_0 = io_ptw_resp_bits_gpa_valid; // @[Frontend.scala:93:7]
wire [38:0] io_ptw_resp_bits_gpa_bits_0 = io_ptw_resp_bits_gpa_bits; // @[Frontend.scala:93:7]
wire io_ptw_resp_bits_gpa_is_pte_0 = io_ptw_resp_bits_gpa_is_pte; // @[Frontend.scala:93:7]
wire [3:0] io_ptw_ptbr_mode_0 = io_ptw_ptbr_mode; // @[Frontend.scala:93:7]
wire [43:0] io_ptw_ptbr_ppn_0 = io_ptw_ptbr_ppn; // @[Frontend.scala:93:7]
wire io_ptw_status_debug_0 = io_ptw_status_debug; // @[Frontend.scala:93:7]
wire io_ptw_status_cease_0 = io_ptw_status_cease; // @[Frontend.scala:93:7]
wire io_ptw_status_wfi_0 = io_ptw_status_wfi; // @[Frontend.scala:93:7]
wire [1:0] io_ptw_status_dprv_0 = io_ptw_status_dprv; // @[Frontend.scala:93:7]
wire io_ptw_status_dv_0 = io_ptw_status_dv; // @[Frontend.scala:93:7]
wire [1:0] io_ptw_status_prv_0 = io_ptw_status_prv; // @[Frontend.scala:93:7]
wire io_ptw_status_v_0 = io_ptw_status_v; // @[Frontend.scala:93:7]
wire io_ptw_status_sd_0 = io_ptw_status_sd; // @[Frontend.scala:93:7]
wire io_ptw_status_mpv_0 = io_ptw_status_mpv; // @[Frontend.scala:93:7]
wire io_ptw_status_gva_0 = io_ptw_status_gva; // @[Frontend.scala:93:7]
wire io_ptw_status_tsr_0 = io_ptw_status_tsr; // @[Frontend.scala:93:7]
wire io_ptw_status_tw_0 = io_ptw_status_tw; // @[Frontend.scala:93:7]
wire io_ptw_status_tvm_0 = io_ptw_status_tvm; // @[Frontend.scala:93:7]
wire io_ptw_status_mxr_0 = io_ptw_status_mxr; // @[Frontend.scala:93:7]
wire io_ptw_status_sum_0 = io_ptw_status_sum; // @[Frontend.scala:93:7]
wire io_ptw_status_mprv_0 = io_ptw_status_mprv; // @[Frontend.scala:93:7]
wire [1:0] io_ptw_status_fs_0 = io_ptw_status_fs; // @[Frontend.scala:93:7]
wire [1:0] io_ptw_status_mpp_0 = io_ptw_status_mpp; // @[Frontend.scala:93:7]
wire io_ptw_status_spp_0 = io_ptw_status_spp; // @[Frontend.scala:93:7]
wire io_ptw_status_mpie_0 = io_ptw_status_mpie; // @[Frontend.scala:93:7]
wire io_ptw_status_spie_0 = io_ptw_status_spie; // @[Frontend.scala:93:7]
wire io_ptw_status_mie_0 = io_ptw_status_mie; // @[Frontend.scala:93:7]
wire io_ptw_status_sie_0 = io_ptw_status_sie; // @[Frontend.scala:93:7]
wire io_ptw_hstatus_spvp_0 = io_ptw_hstatus_spvp; // @[Frontend.scala:93:7]
wire io_ptw_hstatus_spv_0 = io_ptw_hstatus_spv; // @[Frontend.scala:93:7]
wire io_ptw_hstatus_gva_0 = io_ptw_hstatus_gva; // @[Frontend.scala:93:7]
wire io_ptw_gstatus_debug_0 = io_ptw_gstatus_debug; // @[Frontend.scala:93:7]
wire io_ptw_gstatus_cease_0 = io_ptw_gstatus_cease; // @[Frontend.scala:93:7]
wire io_ptw_gstatus_wfi_0 = io_ptw_gstatus_wfi; // @[Frontend.scala:93:7]
wire [31:0] io_ptw_gstatus_isa_0 = io_ptw_gstatus_isa; // @[Frontend.scala:93:7]
wire [1:0] io_ptw_gstatus_dprv_0 = io_ptw_gstatus_dprv; // @[Frontend.scala:93:7]
wire io_ptw_gstatus_dv_0 = io_ptw_gstatus_dv; // @[Frontend.scala:93:7]
wire [1:0] io_ptw_gstatus_prv_0 = io_ptw_gstatus_prv; // @[Frontend.scala:93:7]
wire io_ptw_gstatus_v_0 = io_ptw_gstatus_v; // @[Frontend.scala:93:7]
wire [22:0] io_ptw_gstatus_zero2_0 = io_ptw_gstatus_zero2; // @[Frontend.scala:93:7]
wire io_ptw_gstatus_mpv_0 = io_ptw_gstatus_mpv; // @[Frontend.scala:93:7]
wire io_ptw_gstatus_gva_0 = io_ptw_gstatus_gva; // @[Frontend.scala:93:7]
wire io_ptw_gstatus_mbe_0 = io_ptw_gstatus_mbe; // @[Frontend.scala:93:7]
wire io_ptw_gstatus_sbe_0 = io_ptw_gstatus_sbe; // @[Frontend.scala:93:7]
wire [1:0] io_ptw_gstatus_sxl_0 = io_ptw_gstatus_sxl; // @[Frontend.scala:93:7]
wire [7:0] io_ptw_gstatus_zero1_0 = io_ptw_gstatus_zero1; // @[Frontend.scala:93:7]
wire io_ptw_gstatus_tsr_0 = io_ptw_gstatus_tsr; // @[Frontend.scala:93:7]
wire io_ptw_gstatus_tw_0 = io_ptw_gstatus_tw; // @[Frontend.scala:93:7]
wire io_ptw_gstatus_tvm_0 = io_ptw_gstatus_tvm; // @[Frontend.scala:93:7]
wire io_ptw_gstatus_mxr_0 = io_ptw_gstatus_mxr; // @[Frontend.scala:93:7]
wire io_ptw_gstatus_sum_0 = io_ptw_gstatus_sum; // @[Frontend.scala:93:7]
wire io_ptw_gstatus_mprv_0 = io_ptw_gstatus_mprv; // @[Frontend.scala:93:7]
wire [1:0] io_ptw_gstatus_mpp_0 = io_ptw_gstatus_mpp; // @[Frontend.scala:93:7]
wire [1:0] io_ptw_gstatus_vs_0 = io_ptw_gstatus_vs; // @[Frontend.scala:93:7]
wire io_ptw_gstatus_spp_0 = io_ptw_gstatus_spp; // @[Frontend.scala:93:7]
wire io_ptw_gstatus_mpie_0 = io_ptw_gstatus_mpie; // @[Frontend.scala:93:7]
wire io_ptw_gstatus_ube_0 = io_ptw_gstatus_ube; // @[Frontend.scala:93:7]
wire io_ptw_gstatus_spie_0 = io_ptw_gstatus_spie; // @[Frontend.scala:93:7]
wire io_ptw_gstatus_upie_0 = io_ptw_gstatus_upie; // @[Frontend.scala:93:7]
wire io_ptw_gstatus_mie_0 = io_ptw_gstatus_mie; // @[Frontend.scala:93:7]
wire io_ptw_gstatus_hie_0 = io_ptw_gstatus_hie; // @[Frontend.scala:93:7]
wire io_ptw_gstatus_sie_0 = io_ptw_gstatus_sie; // @[Frontend.scala:93:7]
wire io_ptw_gstatus_uie_0 = io_ptw_gstatus_uie; // @[Frontend.scala:93:7]
wire [1:0] io_ptw_status_sxl = 2'h2; // @[Frontend.scala:93:7]
wire [1:0] io_ptw_status_uxl = 2'h2; // @[Frontend.scala:93:7]
wire [1:0] io_ptw_hstatus_vsxl = 2'h2; // @[Frontend.scala:93:7]
wire [1:0] io_ptw_gstatus_uxl = 2'h2; // @[Frontend.scala:93:7]
wire [31:0] auto_reset_vector_sink_in = 32'h10000; // @[Frontend.scala:93:7]
wire [31:0] resetVectorSinkNodeIn = 32'h10000; // @[Frontend.scala:93:7]
wire [7:0] auto_icache_master_out_a_bits_mask = 8'hFF; // @[Frontend.scala:58:26, :93:7]
wire [3:0] auto_icache_master_out_a_bits_size = 4'h6; // @[Frontend.scala:58:26, :93:7]
wire [2:0] auto_icache_master_out_a_bits_opcode = 3'h4; // @[Frontend.scala:93:7]
wire [1:0] io_ptw_gstatus_fs = 2'h3; // @[Frontend.scala:93:7]
wire auto_icache_master_out_d_ready = 1'h1; // @[Frontend.scala:93:7]
wire io_ptw_req_bits_valid = 1'h1; // @[Frontend.scala:93:7]
wire io_ptw_gstatus_sd = 1'h1; // @[Frontend.scala:93:7]
wire valid = 1'h1; // @[Frontend.scala:267:21]
wire _f2_inst_mask_0_T_3 = 1'h1; // @[Frontend.scala:268:65]
wire [5:0] io_ptw_hstatus_vgein = 6'h0; // @[Frontend.scala:93:7, :98:14, :107:19]
wire [8:0] io_ptw_hstatus_zero5 = 9'h0; // @[Frontend.scala:93:7, :98:14, :107:19]
wire [29:0] io_ptw_hstatus_zero6 = 30'h0; // @[Frontend.scala:93:7, :98:14, :107:19]
wire [7:0] io_ptw_status_zero1 = 8'h0; // @[Frontend.scala:93:7, :98:14, :107:19]
wire [22:0] io_ptw_status_zero2 = 23'h0; // @[Frontend.scala:93:7, :98:14, :107:19]
wire [31:0] io_ptw_status_isa = 32'h14112D; // @[Frontend.scala:93:7, :98:14, :107:19]
wire [43:0] io_ptw_hgatp_ppn = 44'h0; // @[Frontend.scala:93:7, :98:14, :107:19]
wire [43:0] io_ptw_vsatp_ppn = 44'h0; // @[Frontend.scala:93:7, :98:14, :107:19]
wire [3:0] io_ptw_hgatp_mode = 4'h0; // @[Frontend.scala:93:7]
wire [3:0] io_ptw_vsatp_mode = 4'h0; // @[Frontend.scala:93:7]
wire [3:0] f2_fetch_bundle_br_mask = 4'h0; // @[Frontend.scala:245:29]
wire [15:0] io_ptw_ptbr_asid = 16'h0; // @[Frontend.scala:93:7]
wire [15:0] io_ptw_hgatp_asid = 16'h0; // @[Frontend.scala:93:7]
wire [15:0] io_ptw_vsatp_asid = 16'h0; // @[Frontend.scala:93:7]
wire [64:0] io_cpu_resp_0_bits_fdivin_in1 = 65'h0; // @[Frontend.scala:93:7, :98:14, :347:18]
wire [64:0] io_cpu_resp_0_bits_fdivin_in2 = 65'h0; // @[Frontend.scala:93:7, :98:14, :347:18]
wire [64:0] io_cpu_resp_0_bits_fdivin_in3 = 65'h0; // @[Frontend.scala:93:7, :98:14, :347:18]
wire [64:0] io_cpu_resp_1_bits_fdivin_in1 = 65'h0; // @[Frontend.scala:93:7, :98:14, :347:18]
wire [64:0] io_cpu_resp_1_bits_fdivin_in2 = 65'h0; // @[Frontend.scala:93:7, :98:14, :347:18]
wire [64:0] io_cpu_resp_1_bits_fdivin_in3 = 65'h0; // @[Frontend.scala:93:7, :98:14, :347:18]
wire [64:0] io_cpu_peek_0_bits_fdivin_in1 = 65'h0; // @[Frontend.scala:93:7, :98:14, :347:18]
wire [64:0] io_cpu_peek_0_bits_fdivin_in2 = 65'h0; // @[Frontend.scala:93:7, :98:14, :347:18]
wire [64:0] io_cpu_peek_0_bits_fdivin_in3 = 65'h0; // @[Frontend.scala:93:7, :98:14, :347:18]
wire [64:0] io_cpu_peek_1_bits_fdivin_in1 = 65'h0; // @[Frontend.scala:93:7, :98:14, :347:18]
wire [64:0] io_cpu_peek_1_bits_fdivin_in2 = 65'h0; // @[Frontend.scala:93:7, :98:14, :347:18]
wire [64:0] io_cpu_peek_1_bits_fdivin_in3 = 65'h0; // @[Frontend.scala:93:7, :98:14, :347:18]
wire [63:0] auto_icache_master_out_a_bits_data = 64'h0; // @[Frontend.scala:93:7]
wire [63:0] io_cpu_resp_0_bits_rs1_data = 64'h0; // @[Frontend.scala:93:7]
wire [63:0] io_cpu_resp_0_bits_rs2_data = 64'h0; // @[Frontend.scala:93:7]
wire [63:0] io_cpu_resp_0_bits_rs3_data = 64'h0; // @[Frontend.scala:93:7]
wire [63:0] io_cpu_resp_0_bits_wdata_bits = 64'h0; // @[Frontend.scala:93:7]
wire [63:0] io_cpu_resp_1_bits_rs1_data = 64'h0; // @[Frontend.scala:93:7]
wire [63:0] io_cpu_resp_1_bits_rs2_data = 64'h0; // @[Frontend.scala:93:7]
wire [63:0] io_cpu_resp_1_bits_rs3_data = 64'h0; // @[Frontend.scala:93:7]
wire [63:0] io_cpu_resp_1_bits_wdata_bits = 64'h0; // @[Frontend.scala:93:7]
wire [63:0] io_cpu_peek_0_bits_rs1_data = 64'h0; // @[Frontend.scala:93:7]
wire [63:0] io_cpu_peek_0_bits_rs2_data = 64'h0; // @[Frontend.scala:93:7]
wire [63:0] io_cpu_peek_0_bits_rs3_data = 64'h0; // @[Frontend.scala:93:7]
wire [63:0] io_cpu_peek_0_bits_wdata_bits = 64'h0; // @[Frontend.scala:93:7]
wire [63:0] io_cpu_peek_1_bits_rs1_data = 64'h0; // @[Frontend.scala:93:7]
wire [63:0] io_cpu_peek_1_bits_rs2_data = 64'h0; // @[Frontend.scala:93:7]
wire [63:0] io_cpu_peek_1_bits_rs3_data = 64'h0; // @[Frontend.scala:93:7]
wire [63:0] io_cpu_peek_1_bits_wdata_bits = 64'h0; // @[Frontend.scala:93:7]
wire [4:0] io_cpu_resp_0_bits_ctrl_alu_fn = 5'h0; // @[Frontend.scala:93:7]
wire [4:0] io_cpu_resp_0_bits_ctrl_mem_cmd = 5'h0; // @[Frontend.scala:93:7]
wire [4:0] io_cpu_resp_0_bits_fra1 = 5'h0; // @[Frontend.scala:93:7]
wire [4:0] io_cpu_resp_0_bits_fra2 = 5'h0; // @[Frontend.scala:93:7]
wire [4:0] io_cpu_resp_0_bits_fra3 = 5'h0; // @[Frontend.scala:93:7]
wire [4:0] io_cpu_resp_0_bits_fexc = 5'h0; // @[Frontend.scala:93:7]
wire [4:0] io_cpu_resp_1_bits_ctrl_alu_fn = 5'h0; // @[Frontend.scala:93:7]
wire [4:0] io_cpu_resp_1_bits_ctrl_mem_cmd = 5'h0; // @[Frontend.scala:93:7]
wire [4:0] io_cpu_resp_1_bits_fra1 = 5'h0; // @[Frontend.scala:93:7]
wire [4:0] io_cpu_resp_1_bits_fra2 = 5'h0; // @[Frontend.scala:93:7]
wire [4:0] io_cpu_resp_1_bits_fra3 = 5'h0; // @[Frontend.scala:93:7]
wire [4:0] io_cpu_resp_1_bits_fexc = 5'h0; // @[Frontend.scala:93:7]
wire [4:0] io_cpu_peek_0_bits_ctrl_alu_fn = 5'h0; // @[Frontend.scala:93:7]
wire [4:0] io_cpu_peek_0_bits_ctrl_mem_cmd = 5'h0; // @[Frontend.scala:93:7]
wire [4:0] io_cpu_peek_0_bits_fra1 = 5'h0; // @[Frontend.scala:93:7]
wire [4:0] io_cpu_peek_0_bits_fra2 = 5'h0; // @[Frontend.scala:93:7]
wire [4:0] io_cpu_peek_0_bits_fra3 = 5'h0; // @[Frontend.scala:93:7]
wire [4:0] io_cpu_peek_0_bits_fexc = 5'h0; // @[Frontend.scala:93:7]
wire [4:0] io_cpu_peek_1_bits_ctrl_alu_fn = 5'h0; // @[Frontend.scala:93:7]
wire [4:0] io_cpu_peek_1_bits_ctrl_mem_cmd = 5'h0; // @[Frontend.scala:93:7]
wire [4:0] io_cpu_peek_1_bits_fra1 = 5'h0; // @[Frontend.scala:93:7]
wire [4:0] io_cpu_peek_1_bits_fra2 = 5'h0; // @[Frontend.scala:93:7]
wire [4:0] io_cpu_peek_1_bits_fra3 = 5'h0; // @[Frontend.scala:93:7]
wire [4:0] io_cpu_peek_1_bits_fexc = 5'h0; // @[Frontend.scala:93:7]
wire [4:0] io_ptw_hstatus_zero1 = 5'h0; // @[Frontend.scala:93:7]
wire [1:0] io_cpu_resp_0_bits_ctrl_sel_alu1 = 2'h0; // @[Frontend.scala:93:7]
wire [1:0] io_cpu_resp_0_bits_fp_ctrl_typeTagIn = 2'h0; // @[Frontend.scala:93:7]
wire [1:0] io_cpu_resp_0_bits_fp_ctrl_typeTagOut = 2'h0; // @[Frontend.scala:93:7]
wire [1:0] io_cpu_resp_0_bits_fdivin_typeTagIn = 2'h0; // @[Frontend.scala:93:7]
wire [1:0] io_cpu_resp_0_bits_fdivin_typeTagOut = 2'h0; // @[Frontend.scala:93:7]
wire [1:0] io_cpu_resp_0_bits_fdivin_fmaCmd = 2'h0; // @[Frontend.scala:93:7]
wire [1:0] io_cpu_resp_0_bits_fdivin_typ = 2'h0; // @[Frontend.scala:93:7]
wire [1:0] io_cpu_resp_0_bits_fdivin_fmt = 2'h0; // @[Frontend.scala:93:7]
wire [1:0] io_cpu_resp_1_bits_ctrl_sel_alu1 = 2'h0; // @[Frontend.scala:93:7]
wire [1:0] io_cpu_resp_1_bits_fp_ctrl_typeTagIn = 2'h0; // @[Frontend.scala:93:7]
wire [1:0] io_cpu_resp_1_bits_fp_ctrl_typeTagOut = 2'h0; // @[Frontend.scala:93:7]
wire [1:0] io_cpu_resp_1_bits_fdivin_typeTagIn = 2'h0; // @[Frontend.scala:93:7]
wire [1:0] io_cpu_resp_1_bits_fdivin_typeTagOut = 2'h0; // @[Frontend.scala:93:7]
wire [1:0] io_cpu_resp_1_bits_fdivin_fmaCmd = 2'h0; // @[Frontend.scala:93:7]
wire [1:0] io_cpu_resp_1_bits_fdivin_typ = 2'h0; // @[Frontend.scala:93:7]
wire [1:0] io_cpu_resp_1_bits_fdivin_fmt = 2'h0; // @[Frontend.scala:93:7]
wire [1:0] io_cpu_peek_0_bits_ctrl_sel_alu1 = 2'h0; // @[Frontend.scala:93:7]
wire [1:0] io_cpu_peek_0_bits_fp_ctrl_typeTagIn = 2'h0; // @[Frontend.scala:93:7]
wire [1:0] io_cpu_peek_0_bits_fp_ctrl_typeTagOut = 2'h0; // @[Frontend.scala:93:7]
wire [1:0] io_cpu_peek_0_bits_fdivin_typeTagIn = 2'h0; // @[Frontend.scala:93:7]
wire [1:0] io_cpu_peek_0_bits_fdivin_typeTagOut = 2'h0; // @[Frontend.scala:93:7]
wire [1:0] io_cpu_peek_0_bits_fdivin_fmaCmd = 2'h0; // @[Frontend.scala:93:7]
wire [1:0] io_cpu_peek_0_bits_fdivin_typ = 2'h0; // @[Frontend.scala:93:7]
wire [1:0] io_cpu_peek_0_bits_fdivin_fmt = 2'h0; // @[Frontend.scala:93:7]
wire [1:0] io_cpu_peek_1_bits_ctrl_sel_alu1 = 2'h0; // @[Frontend.scala:93:7]
wire [1:0] io_cpu_peek_1_bits_fp_ctrl_typeTagIn = 2'h0; // @[Frontend.scala:93:7]
wire [1:0] io_cpu_peek_1_bits_fp_ctrl_typeTagOut = 2'h0; // @[Frontend.scala:93:7]
wire [1:0] io_cpu_peek_1_bits_fdivin_typeTagIn = 2'h0; // @[Frontend.scala:93:7]
wire [1:0] io_cpu_peek_1_bits_fdivin_typeTagOut = 2'h0; // @[Frontend.scala:93:7]
wire [1:0] io_cpu_peek_1_bits_fdivin_fmaCmd = 2'h0; // @[Frontend.scala:93:7]
wire [1:0] io_cpu_peek_1_bits_fdivin_typ = 2'h0; // @[Frontend.scala:93:7]
wire [1:0] io_cpu_peek_1_bits_fdivin_fmt = 2'h0; // @[Frontend.scala:93:7]
wire [1:0] io_ptw_status_xs = 2'h0; // @[Frontend.scala:93:7]
wire [1:0] io_ptw_status_vs = 2'h0; // @[Frontend.scala:93:7]
wire [1:0] io_ptw_hstatus_zero3 = 2'h0; // @[Frontend.scala:93:7]
wire [1:0] io_ptw_hstatus_zero2 = 2'h0; // @[Frontend.scala:93:7]
wire [1:0] io_ptw_gstatus_xs = 2'h0; // @[Frontend.scala:93:7]
wire [1:0] _f2_fetch_bundle_pcs_1_T_3 = 2'h0; // @[Frontend.scala:269:103]
wire [1:0] _f2_fetch_bundle_pcs_2_T_3 = 2'h0; // @[Frontend.scala:269:103]
wire [1:0] _f2_fetch_bundle_pcs_3_T_3 = 2'h0; // @[Frontend.scala:269:103]
wire [2:0] auto_icache_master_out_a_bits_param = 3'h0; // @[Frontend.scala:93:7]
wire [2:0] io_cpu_resp_0_bits_ctrl_sel_alu2 = 3'h0; // @[Frontend.scala:93:7]
wire [2:0] io_cpu_resp_0_bits_ctrl_sel_imm = 3'h0; // @[Frontend.scala:93:7]
wire [2:0] io_cpu_resp_0_bits_ctrl_csr = 3'h0; // @[Frontend.scala:93:7]
wire [2:0] io_cpu_resp_0_bits_fdivin_rm = 3'h0; // @[Frontend.scala:93:7]
wire [2:0] io_cpu_resp_1_bits_ctrl_sel_alu2 = 3'h0; // @[Frontend.scala:93:7]
wire [2:0] io_cpu_resp_1_bits_ctrl_sel_imm = 3'h0; // @[Frontend.scala:93:7]
wire [2:0] io_cpu_resp_1_bits_ctrl_csr = 3'h0; // @[Frontend.scala:93:7]
wire [2:0] io_cpu_resp_1_bits_fdivin_rm = 3'h0; // @[Frontend.scala:93:7]
wire [2:0] io_cpu_peek_0_bits_ctrl_sel_alu2 = 3'h0; // @[Frontend.scala:93:7]
wire [2:0] io_cpu_peek_0_bits_ctrl_sel_imm = 3'h0; // @[Frontend.scala:93:7]
wire [2:0] io_cpu_peek_0_bits_ctrl_csr = 3'h0; // @[Frontend.scala:93:7]
wire [2:0] io_cpu_peek_0_bits_fdivin_rm = 3'h0; // @[Frontend.scala:93:7]
wire [2:0] io_cpu_peek_1_bits_ctrl_sel_alu2 = 3'h0; // @[Frontend.scala:93:7]
wire [2:0] io_cpu_peek_1_bits_ctrl_sel_imm = 3'h0; // @[Frontend.scala:93:7]
wire [2:0] io_cpu_peek_1_bits_ctrl_csr = 3'h0; // @[Frontend.scala:93:7]
wire [2:0] io_cpu_peek_1_bits_fdivin_rm = 3'h0; // @[Frontend.scala:93:7]
wire auto_icache_master_out_a_bits_source = 1'h0; // @[Frontend.scala:93:7]
wire auto_icache_master_out_a_bits_corrupt = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_0_bits_ctrl_legal = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_0_bits_ctrl_fp = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_0_bits_ctrl_rocc = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_0_bits_ctrl_branch = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_0_bits_ctrl_jal = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_0_bits_ctrl_jalr = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_0_bits_ctrl_rxs2 = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_0_bits_ctrl_rxs1 = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_0_bits_ctrl_alu_dw = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_0_bits_ctrl_mem = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_0_bits_ctrl_rfs1 = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_0_bits_ctrl_rfs2 = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_0_bits_ctrl_rfs3 = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_0_bits_ctrl_wfd = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_0_bits_ctrl_mul = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_0_bits_ctrl_div = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_0_bits_ctrl_wxd = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_0_bits_ctrl_fence_i = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_0_bits_ctrl_fence = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_0_bits_ctrl_amo = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_0_bits_ctrl_dp = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_0_bits_ctrl_vec = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_0_bits_fp_ctrl_ldst = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_0_bits_fp_ctrl_wen = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_0_bits_fp_ctrl_ren1 = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_0_bits_fp_ctrl_ren2 = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_0_bits_fp_ctrl_ren3 = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_0_bits_fp_ctrl_swap12 = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_0_bits_fp_ctrl_swap23 = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_0_bits_fp_ctrl_fromint = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_0_bits_fp_ctrl_toint = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_0_bits_fp_ctrl_fastpipe = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_0_bits_fp_ctrl_fma = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_0_bits_fp_ctrl_div = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_0_bits_fp_ctrl_sqrt = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_0_bits_fp_ctrl_wflags = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_0_bits_fp_ctrl_vec = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_0_bits_sets_vcfg = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_0_bits_sfb_shadow = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_0_bits_taken = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_0_bits_needs_replay = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_0_bits_uses_memalu = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_0_bits_uses_latealu = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_0_bits_wdata_valid = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_0_bits_fdivin_ldst = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_0_bits_fdivin_wen = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_0_bits_fdivin_ren1 = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_0_bits_fdivin_ren2 = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_0_bits_fdivin_ren3 = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_0_bits_fdivin_swap12 = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_0_bits_fdivin_swap23 = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_0_bits_fdivin_fromint = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_0_bits_fdivin_toint = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_0_bits_fdivin_fastpipe = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_0_bits_fdivin_fma = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_0_bits_fdivin_div = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_0_bits_fdivin_sqrt = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_0_bits_fdivin_wflags = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_0_bits_fdivin_vec = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_0_bits_flush_pipe = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_1_bits_ctrl_legal = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_1_bits_ctrl_fp = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_1_bits_ctrl_rocc = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_1_bits_ctrl_branch = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_1_bits_ctrl_jal = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_1_bits_ctrl_jalr = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_1_bits_ctrl_rxs2 = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_1_bits_ctrl_rxs1 = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_1_bits_ctrl_alu_dw = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_1_bits_ctrl_mem = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_1_bits_ctrl_rfs1 = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_1_bits_ctrl_rfs2 = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_1_bits_ctrl_rfs3 = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_1_bits_ctrl_wfd = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_1_bits_ctrl_mul = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_1_bits_ctrl_div = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_1_bits_ctrl_wxd = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_1_bits_ctrl_fence_i = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_1_bits_ctrl_fence = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_1_bits_ctrl_amo = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_1_bits_ctrl_dp = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_1_bits_ctrl_vec = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_1_bits_fp_ctrl_ldst = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_1_bits_fp_ctrl_wen = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_1_bits_fp_ctrl_ren1 = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_1_bits_fp_ctrl_ren2 = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_1_bits_fp_ctrl_ren3 = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_1_bits_fp_ctrl_swap12 = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_1_bits_fp_ctrl_swap23 = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_1_bits_fp_ctrl_fromint = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_1_bits_fp_ctrl_toint = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_1_bits_fp_ctrl_fastpipe = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_1_bits_fp_ctrl_fma = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_1_bits_fp_ctrl_div = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_1_bits_fp_ctrl_sqrt = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_1_bits_fp_ctrl_wflags = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_1_bits_fp_ctrl_vec = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_1_bits_sets_vcfg = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_1_bits_sfb_shadow = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_1_bits_taken = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_1_bits_needs_replay = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_1_bits_uses_memalu = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_1_bits_uses_latealu = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_1_bits_wdata_valid = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_1_bits_fdivin_ldst = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_1_bits_fdivin_wen = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_1_bits_fdivin_ren1 = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_1_bits_fdivin_ren2 = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_1_bits_fdivin_ren3 = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_1_bits_fdivin_swap12 = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_1_bits_fdivin_swap23 = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_1_bits_fdivin_fromint = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_1_bits_fdivin_toint = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_1_bits_fdivin_fastpipe = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_1_bits_fdivin_fma = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_1_bits_fdivin_div = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_1_bits_fdivin_sqrt = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_1_bits_fdivin_wflags = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_1_bits_fdivin_vec = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_resp_1_bits_flush_pipe = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_0_bits_ctrl_legal = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_0_bits_ctrl_fp = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_0_bits_ctrl_rocc = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_0_bits_ctrl_branch = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_0_bits_ctrl_jal = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_0_bits_ctrl_jalr = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_0_bits_ctrl_rxs2 = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_0_bits_ctrl_rxs1 = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_0_bits_ctrl_alu_dw = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_0_bits_ctrl_mem = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_0_bits_ctrl_rfs1 = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_0_bits_ctrl_rfs2 = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_0_bits_ctrl_rfs3 = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_0_bits_ctrl_wfd = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_0_bits_ctrl_mul = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_0_bits_ctrl_div = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_0_bits_ctrl_wxd = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_0_bits_ctrl_fence_i = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_0_bits_ctrl_fence = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_0_bits_ctrl_amo = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_0_bits_ctrl_dp = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_0_bits_ctrl_vec = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_0_bits_fp_ctrl_ldst = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_0_bits_fp_ctrl_wen = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_0_bits_fp_ctrl_ren1 = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_0_bits_fp_ctrl_ren2 = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_0_bits_fp_ctrl_ren3 = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_0_bits_fp_ctrl_swap12 = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_0_bits_fp_ctrl_swap23 = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_0_bits_fp_ctrl_fromint = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_0_bits_fp_ctrl_toint = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_0_bits_fp_ctrl_fastpipe = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_0_bits_fp_ctrl_fma = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_0_bits_fp_ctrl_div = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_0_bits_fp_ctrl_sqrt = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_0_bits_fp_ctrl_wflags = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_0_bits_fp_ctrl_vec = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_0_bits_sets_vcfg = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_0_bits_sfb_shadow = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_0_bits_taken = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_0_bits_needs_replay = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_0_bits_uses_memalu = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_0_bits_uses_latealu = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_0_bits_wdata_valid = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_0_bits_fdivin_ldst = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_0_bits_fdivin_wen = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_0_bits_fdivin_ren1 = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_0_bits_fdivin_ren2 = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_0_bits_fdivin_ren3 = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_0_bits_fdivin_swap12 = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_0_bits_fdivin_swap23 = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_0_bits_fdivin_fromint = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_0_bits_fdivin_toint = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_0_bits_fdivin_fastpipe = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_0_bits_fdivin_fma = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_0_bits_fdivin_div = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_0_bits_fdivin_sqrt = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_0_bits_fdivin_wflags = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_0_bits_fdivin_vec = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_0_bits_flush_pipe = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_1_bits_ctrl_legal = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_1_bits_ctrl_fp = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_1_bits_ctrl_rocc = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_1_bits_ctrl_branch = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_1_bits_ctrl_jal = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_1_bits_ctrl_jalr = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_1_bits_ctrl_rxs2 = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_1_bits_ctrl_rxs1 = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_1_bits_ctrl_alu_dw = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_1_bits_ctrl_mem = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_1_bits_ctrl_rfs1 = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_1_bits_ctrl_rfs2 = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_1_bits_ctrl_rfs3 = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_1_bits_ctrl_wfd = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_1_bits_ctrl_mul = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_1_bits_ctrl_div = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_1_bits_ctrl_wxd = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_1_bits_ctrl_fence_i = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_1_bits_ctrl_fence = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_1_bits_ctrl_amo = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_1_bits_ctrl_dp = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_1_bits_ctrl_vec = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_1_bits_fp_ctrl_ldst = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_1_bits_fp_ctrl_wen = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_1_bits_fp_ctrl_ren1 = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_1_bits_fp_ctrl_ren2 = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_1_bits_fp_ctrl_ren3 = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_1_bits_fp_ctrl_swap12 = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_1_bits_fp_ctrl_swap23 = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_1_bits_fp_ctrl_fromint = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_1_bits_fp_ctrl_toint = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_1_bits_fp_ctrl_fastpipe = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_1_bits_fp_ctrl_fma = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_1_bits_fp_ctrl_div = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_1_bits_fp_ctrl_sqrt = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_1_bits_fp_ctrl_wflags = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_1_bits_fp_ctrl_vec = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_1_bits_sets_vcfg = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_1_bits_sfb_shadow = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_1_bits_taken = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_1_bits_needs_replay = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_1_bits_uses_memalu = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_1_bits_uses_latealu = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_1_bits_wdata_valid = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_1_bits_fdivin_ldst = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_1_bits_fdivin_wen = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_1_bits_fdivin_ren1 = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_1_bits_fdivin_ren2 = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_1_bits_fdivin_ren3 = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_1_bits_fdivin_swap12 = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_1_bits_fdivin_swap23 = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_1_bits_fdivin_fromint = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_1_bits_fdivin_toint = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_1_bits_fdivin_fastpipe = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_1_bits_fdivin_fma = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_1_bits_fdivin_div = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_1_bits_fdivin_sqrt = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_1_bits_fdivin_wflags = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_1_bits_fdivin_vec = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_peek_1_bits_flush_pipe = 1'h0; // @[Frontend.scala:93:7]
wire io_cpu_btb_update_bits_taken = 1'h0; // @[Frontend.scala:93:7]
wire io_ptw_req_bits_bits_vstage1 = 1'h0; // @[Frontend.scala:93:7]
wire io_ptw_req_bits_bits_stage2 = 1'h0; // @[Frontend.scala:93:7]
wire io_ptw_resp_bits_fragmented_superpage = 1'h0; // @[Frontend.scala:93:7]
wire io_ptw_status_mbe = 1'h0; // @[Frontend.scala:93:7]
wire io_ptw_status_sbe = 1'h0; // @[Frontend.scala:93:7]
wire io_ptw_status_sd_rv32 = 1'h0; // @[Frontend.scala:93:7]
wire io_ptw_status_ube = 1'h0; // @[Frontend.scala:93:7]
wire io_ptw_status_upie = 1'h0; // @[Frontend.scala:93:7]
wire io_ptw_status_hie = 1'h0; // @[Frontend.scala:93:7]
wire io_ptw_status_uie = 1'h0; // @[Frontend.scala:93:7]
wire io_ptw_hstatus_vtsr = 1'h0; // @[Frontend.scala:93:7]
wire io_ptw_hstatus_vtw = 1'h0; // @[Frontend.scala:93:7]
wire io_ptw_hstatus_vtvm = 1'h0; // @[Frontend.scala:93:7]
wire io_ptw_hstatus_hu = 1'h0; // @[Frontend.scala:93:7]
wire io_ptw_hstatus_vsbe = 1'h0; // @[Frontend.scala:93:7]
wire io_ptw_gstatus_sd_rv32 = 1'h0; // @[Frontend.scala:93:7]
wire _f2_fetch_bundle_pcs_1_T_2 = 1'h0; // @[Frontend.scala:269:88]
wire _f2_fetch_bundle_pcs_2_T_2 = 1'h0; // @[Frontend.scala:269:88]
wire _f2_fetch_bundle_pcs_3_T_2 = 1'h0; // @[Frontend.scala:269:88]
wire [31:0] auto_icache_master_out_a_bits_address_0; // @[Frontend.scala:93:7]
wire auto_icache_master_out_a_valid_0; // @[Frontend.scala:93:7]
wire [7:0] io_cpu_resp_0_bits_btb_resp_bits_bht_history_0; // @[Frontend.scala:93:7]
wire [1:0] io_cpu_resp_0_bits_btb_resp_bits_bht_value_0; // @[Frontend.scala:93:7]
wire [1:0] io_cpu_resp_0_bits_btb_resp_bits_cfiType_0; // @[Frontend.scala:93:7]
wire io_cpu_resp_0_bits_btb_resp_bits_taken_0; // @[Frontend.scala:93:7]
wire [3:0] io_cpu_resp_0_bits_btb_resp_bits_mask_0; // @[Frontend.scala:93:7]
wire [1:0] io_cpu_resp_0_bits_btb_resp_bits_bridx_0; // @[Frontend.scala:93:7]
wire [38:0] io_cpu_resp_0_bits_btb_resp_bits_target_0; // @[Frontend.scala:93:7]
wire [5:0] io_cpu_resp_0_bits_btb_resp_bits_entry_0; // @[Frontend.scala:93:7]
wire io_cpu_resp_0_bits_btb_resp_valid_0; // @[Frontend.scala:93:7]
wire io_cpu_resp_0_bits_next_pc_valid_0; // @[Frontend.scala:93:7]
wire [39:0] io_cpu_resp_0_bits_next_pc_bits_0; // @[Frontend.scala:93:7]
wire [31:0] io_cpu_resp_0_bits_inst_0; // @[Frontend.scala:93:7]
wire [31:0] io_cpu_resp_0_bits_raw_inst_0; // @[Frontend.scala:93:7]
wire [39:0] io_cpu_resp_0_bits_pc_0; // @[Frontend.scala:93:7]
wire io_cpu_resp_0_bits_edge_inst_0; // @[Frontend.scala:93:7]
wire io_cpu_resp_0_bits_rvc_0; // @[Frontend.scala:93:7]
wire io_cpu_resp_0_bits_sfb_br_0; // @[Frontend.scala:93:7]
wire [2:0] io_cpu_resp_0_bits_ras_head_0; // @[Frontend.scala:93:7]
wire io_cpu_resp_0_bits_xcpt_0; // @[Frontend.scala:93:7]
wire [63:0] io_cpu_resp_0_bits_xcpt_cause_0; // @[Frontend.scala:93:7]
wire [1:0] io_cpu_resp_0_bits_mem_size_0; // @[Frontend.scala:93:7]
wire io_cpu_resp_0_valid_0; // @[Frontend.scala:93:7]
wire [7:0] io_cpu_resp_1_bits_btb_resp_bits_bht_history_0; // @[Frontend.scala:93:7]
wire [1:0] io_cpu_resp_1_bits_btb_resp_bits_bht_value_0; // @[Frontend.scala:93:7]
wire [1:0] io_cpu_resp_1_bits_btb_resp_bits_cfiType_0; // @[Frontend.scala:93:7]
wire io_cpu_resp_1_bits_btb_resp_bits_taken_0; // @[Frontend.scala:93:7]
wire [3:0] io_cpu_resp_1_bits_btb_resp_bits_mask_0; // @[Frontend.scala:93:7]
wire [1:0] io_cpu_resp_1_bits_btb_resp_bits_bridx_0; // @[Frontend.scala:93:7]
wire [38:0] io_cpu_resp_1_bits_btb_resp_bits_target_0; // @[Frontend.scala:93:7]
wire [5:0] io_cpu_resp_1_bits_btb_resp_bits_entry_0; // @[Frontend.scala:93:7]
wire io_cpu_resp_1_bits_btb_resp_valid_0; // @[Frontend.scala:93:7]
wire io_cpu_resp_1_bits_next_pc_valid_0; // @[Frontend.scala:93:7]
wire [39:0] io_cpu_resp_1_bits_next_pc_bits_0; // @[Frontend.scala:93:7]
wire [31:0] io_cpu_resp_1_bits_inst_0; // @[Frontend.scala:93:7]
wire [31:0] io_cpu_resp_1_bits_raw_inst_0; // @[Frontend.scala:93:7]
wire [39:0] io_cpu_resp_1_bits_pc_0; // @[Frontend.scala:93:7]
wire io_cpu_resp_1_bits_edge_inst_0; // @[Frontend.scala:93:7]
wire io_cpu_resp_1_bits_rvc_0; // @[Frontend.scala:93:7]
wire io_cpu_resp_1_bits_sfb_br_0; // @[Frontend.scala:93:7]
wire [2:0] io_cpu_resp_1_bits_ras_head_0; // @[Frontend.scala:93:7]
wire io_cpu_resp_1_bits_xcpt_0; // @[Frontend.scala:93:7]
wire [63:0] io_cpu_resp_1_bits_xcpt_cause_0; // @[Frontend.scala:93:7]
wire [1:0] io_cpu_resp_1_bits_mem_size_0; // @[Frontend.scala:93:7]
wire io_cpu_resp_1_valid_0; // @[Frontend.scala:93:7]
wire [7:0] io_cpu_peek_0_bits_btb_resp_bits_bht_history_0; // @[Frontend.scala:93:7]
wire [1:0] io_cpu_peek_0_bits_btb_resp_bits_bht_value_0; // @[Frontend.scala:93:7]
wire [1:0] io_cpu_peek_0_bits_btb_resp_bits_cfiType_0; // @[Frontend.scala:93:7]
wire io_cpu_peek_0_bits_btb_resp_bits_taken_0; // @[Frontend.scala:93:7]
wire [3:0] io_cpu_peek_0_bits_btb_resp_bits_mask_0; // @[Frontend.scala:93:7]
wire [1:0] io_cpu_peek_0_bits_btb_resp_bits_bridx_0; // @[Frontend.scala:93:7]
wire [38:0] io_cpu_peek_0_bits_btb_resp_bits_target_0; // @[Frontend.scala:93:7]
wire [5:0] io_cpu_peek_0_bits_btb_resp_bits_entry_0; // @[Frontend.scala:93:7]
wire io_cpu_peek_0_bits_btb_resp_valid_0; // @[Frontend.scala:93:7]
wire io_cpu_peek_0_bits_next_pc_valid_0; // @[Frontend.scala:93:7]
wire [39:0] io_cpu_peek_0_bits_next_pc_bits_0; // @[Frontend.scala:93:7]
wire [31:0] io_cpu_peek_0_bits_inst_0; // @[Frontend.scala:93:7]
wire [31:0] io_cpu_peek_0_bits_raw_inst_0; // @[Frontend.scala:93:7]
wire [39:0] io_cpu_peek_0_bits_pc_0; // @[Frontend.scala:93:7]
wire io_cpu_peek_0_bits_edge_inst_0; // @[Frontend.scala:93:7]
wire io_cpu_peek_0_bits_rvc_0; // @[Frontend.scala:93:7]
wire io_cpu_peek_0_bits_sfb_br_0; // @[Frontend.scala:93:7]
wire [2:0] io_cpu_peek_0_bits_ras_head_0; // @[Frontend.scala:93:7]
wire io_cpu_peek_0_bits_xcpt_0; // @[Frontend.scala:93:7]
wire [63:0] io_cpu_peek_0_bits_xcpt_cause_0; // @[Frontend.scala:93:7]
wire [1:0] io_cpu_peek_0_bits_mem_size_0; // @[Frontend.scala:93:7]
wire io_cpu_peek_0_valid_0; // @[Frontend.scala:93:7]
wire [7:0] io_cpu_peek_1_bits_btb_resp_bits_bht_history_0; // @[Frontend.scala:93:7]
wire [1:0] io_cpu_peek_1_bits_btb_resp_bits_bht_value_0; // @[Frontend.scala:93:7]
wire [1:0] io_cpu_peek_1_bits_btb_resp_bits_cfiType_0; // @[Frontend.scala:93:7]
wire io_cpu_peek_1_bits_btb_resp_bits_taken_0; // @[Frontend.scala:93:7]
wire [3:0] io_cpu_peek_1_bits_btb_resp_bits_mask_0; // @[Frontend.scala:93:7]
wire [1:0] io_cpu_peek_1_bits_btb_resp_bits_bridx_0; // @[Frontend.scala:93:7]
wire [38:0] io_cpu_peek_1_bits_btb_resp_bits_target_0; // @[Frontend.scala:93:7]
wire [5:0] io_cpu_peek_1_bits_btb_resp_bits_entry_0; // @[Frontend.scala:93:7]
wire io_cpu_peek_1_bits_btb_resp_valid_0; // @[Frontend.scala:93:7]
wire io_cpu_peek_1_bits_next_pc_valid_0; // @[Frontend.scala:93:7]
wire [39:0] io_cpu_peek_1_bits_next_pc_bits_0; // @[Frontend.scala:93:7]
wire [31:0] io_cpu_peek_1_bits_inst_0; // @[Frontend.scala:93:7]
wire [31:0] io_cpu_peek_1_bits_raw_inst_0; // @[Frontend.scala:93:7]
wire [39:0] io_cpu_peek_1_bits_pc_0; // @[Frontend.scala:93:7]
wire io_cpu_peek_1_bits_edge_inst_0; // @[Frontend.scala:93:7]
wire io_cpu_peek_1_bits_rvc_0; // @[Frontend.scala:93:7]
wire io_cpu_peek_1_bits_sfb_br_0; // @[Frontend.scala:93:7]
wire [2:0] io_cpu_peek_1_bits_ras_head_0; // @[Frontend.scala:93:7]
wire io_cpu_peek_1_bits_xcpt_0; // @[Frontend.scala:93:7]
wire [63:0] io_cpu_peek_1_bits_xcpt_cause_0; // @[Frontend.scala:93:7]
wire [1:0] io_cpu_peek_1_bits_mem_size_0; // @[Frontend.scala:93:7]
wire io_cpu_peek_1_valid_0; // @[Frontend.scala:93:7]
wire [26:0] io_ptw_req_bits_bits_addr_0; // @[Frontend.scala:93:7]
wire io_ptw_req_bits_bits_need_gpa_0; // @[Frontend.scala:93:7]
wire io_ptw_req_valid_0; // @[Frontend.scala:93:7]
reg [39:0] ras_0; // @[Frontend.scala:110:16]
reg [39:0] ras_1; // @[Frontend.scala:110:16]
reg [39:0] ras_2; // @[Frontend.scala:110:16]
reg [39:0] ras_3; // @[Frontend.scala:110:16]
reg [39:0] ras_4; // @[Frontend.scala:110:16]
reg [39:0] ras_5; // @[Frontend.scala:110:16]
wire [39:0] s0_vpc; // @[Frontend.scala:121:24]
wire s0_valid; // @[Frontend.scala:122:26]
wire [2:0] s0_ras_head; // @[Frontend.scala:123:29]
wire s0_is_replay; // @[Frontend.scala:124:30]
wire s0_replay_resp_pf_ld; // @[Frontend.scala:125:28]
wire s0_replay_resp_pf_st; // @[Frontend.scala:125:28]
wire s0_replay_resp_pf_inst; // @[Frontend.scala:125:28]
wire s0_replay_resp_gf_ld; // @[Frontend.scala:125:28]
wire s0_replay_resp_gf_st; // @[Frontend.scala:125:28]
wire s0_replay_resp_gf_inst; // @[Frontend.scala:125:28]
wire s0_replay_resp_ae_ld; // @[Frontend.scala:125:28]
wire s0_replay_resp_ae_st; // @[Frontend.scala:125:28]
wire s0_replay_resp_ae_inst; // @[Frontend.scala:125:28]
wire s0_replay_resp_ma_ld; // @[Frontend.scala:125:28]
wire s0_replay_resp_ma_st; // @[Frontend.scala:125:28]
wire s0_replay_resp_ma_inst; // @[Frontend.scala:125:28]
wire s0_replay_resp_miss; // @[Frontend.scala:125:28]
wire [31:0] s0_replay_resp_paddr; // @[Frontend.scala:125:28]
wire [39:0] s0_replay_resp_gpa; // @[Frontend.scala:125:28]
wire s0_replay_resp_gpa_is_pte; // @[Frontend.scala:125:28]
wire s0_replay_resp_cacheable; // @[Frontend.scala:125:28]
wire s0_replay_resp_must_alloc; // @[Frontend.scala:125:28]
wire s0_replay_resp_prefetchable; // @[Frontend.scala:125:28]
wire [1:0] s0_replay_resp_size; // @[Frontend.scala:125:28]
wire [4:0] s0_replay_resp_cmd; // @[Frontend.scala:125:28]
wire [31:0] s0_replay_ppc; // @[Frontend.scala:126:27]
reg [39:0] s1_vpc; // @[Frontend.scala:135:29]
reg [2:0] s1_ras_head_REG; // @[Frontend.scala:136:38]
wire [2:0] s1_ras_head; // @[Frontend.scala:136:30]
reg s1_valid; // @[Frontend.scala:137:29]
reg s1_is_replay; // @[Frontend.scala:138:29]
wire f1_clear; // @[Frontend.scala:139:30]
wire _tlb_io_req_valid_T = ~s1_is_replay; // @[Frontend.scala:138:29, :141:41]
wire _tlb_io_req_valid_T_1 = s1_valid & _tlb_io_req_valid_T; // @[Frontend.scala:137:29, :141:{38,41}]
wire _tlb_io_req_valid_T_2 = ~f1_clear; // @[Frontend.scala:139:30, :141:58]
wire _tlb_io_req_valid_T_3 = _tlb_io_req_valid_T_1 & _tlb_io_req_valid_T_2; // @[Frontend.scala:141:{38,55,58}]
wire _tlb_io_req_valid_T_4 = ~io_cpu_sfence_valid_0; // @[Frontend.scala:93:7, :141:71]
wire _tlb_io_req_valid_T_5 = _tlb_io_req_valid_T_3 & _tlb_io_req_valid_T_4; // @[Frontend.scala:141:{55,68,71}]
wire [39:0] _tlb_io_req_bits_vaddr_T = io_cpu_sfence_valid_0 ? {1'h0, io_cpu_sfence_bits_addr_0} : s1_vpc; // @[Frontend.scala:93:7, :135:29, :143:31]
wire _btb_io_req_valid_T = ~io_cpu_sfence_valid_0; // @[Frontend.scala:93:7, :141:71, :152:35]
wire _btb_io_req_valid_T_1 = s1_valid & _btb_io_req_valid_T; // @[Frontend.scala:137:29, :152:{32,35}]
wire [39:0] _btb_io_req_bits_addr_T = ~s1_vpc; // @[Frontend.scala:19:34, :135:29]
wire [39:0] _btb_io_req_bits_addr_T_1 = {_btb_io_req_bits_addr_T[39:3], 3'h7}; // @[Frontend.scala:19:{34,40}]
wire [39:0] _btb_io_req_bits_addr_T_2 = ~_btb_io_req_bits_addr_T_1; // @[Frontend.scala:19:{32,40}]
wire _s1_tlb_miss_T = ~s1_is_replay; // @[Frontend.scala:138:29, :141:41, :156:21]
wire _s1_tlb_miss_T_1 = _tlb_io_resp_miss | io_cpu_sfence_valid_0; // @[Frontend.scala:93:7, :107:19, :156:56]
wire s1_tlb_miss = _s1_tlb_miss_T & _s1_tlb_miss_T_1; // @[Frontend.scala:156:{21,35,56}]
reg s1_tlb_resp_REG_miss; // @[Frontend.scala:157:46]
reg [31:0] s1_tlb_resp_REG_paddr; // @[Frontend.scala:157:46]
reg [39:0] s1_tlb_resp_REG_gpa; // @[Frontend.scala:157:46]
reg s1_tlb_resp_REG_gpa_is_pte; // @[Frontend.scala:157:46]
reg s1_tlb_resp_REG_pf_ld; // @[Frontend.scala:157:46]
reg s1_tlb_resp_REG_pf_st; // @[Frontend.scala:157:46]
reg s1_tlb_resp_REG_pf_inst; // @[Frontend.scala:157:46]
reg s1_tlb_resp_REG_gf_ld; // @[Frontend.scala:157:46]
reg s1_tlb_resp_REG_gf_st; // @[Frontend.scala:157:46]
reg s1_tlb_resp_REG_gf_inst; // @[Frontend.scala:157:46]
reg s1_tlb_resp_REG_ae_ld; // @[Frontend.scala:157:46]
reg s1_tlb_resp_REG_ae_st; // @[Frontend.scala:157:46]
reg s1_tlb_resp_REG_ae_inst; // @[Frontend.scala:157:46]
reg s1_tlb_resp_REG_ma_ld; // @[Frontend.scala:157:46]
reg s1_tlb_resp_REG_ma_st; // @[Frontend.scala:157:46]
reg s1_tlb_resp_REG_ma_inst; // @[Frontend.scala:157:46]
reg s1_tlb_resp_REG_cacheable; // @[Frontend.scala:157:46]
reg s1_tlb_resp_REG_must_alloc; // @[Frontend.scala:157:46]
reg s1_tlb_resp_REG_prefetchable; // @[Frontend.scala:157:46]
reg [1:0] s1_tlb_resp_REG_size; // @[Frontend.scala:157:46]
reg [4:0] s1_tlb_resp_REG_cmd; // @[Frontend.scala:157:46]
wire s1_tlb_resp_miss = s1_is_replay ? s1_tlb_resp_REG_miss : _tlb_io_resp_miss; // @[Frontend.scala:107:19, :138:29, :157:{24,46}]
wire [31:0] s1_tlb_resp_paddr = s1_is_replay ? s1_tlb_resp_REG_paddr : _tlb_io_resp_paddr; // @[Frontend.scala:107:19, :138:29, :157:{24,46}]
wire [39:0] s1_tlb_resp_gpa = s1_is_replay ? s1_tlb_resp_REG_gpa : _tlb_io_resp_gpa; // @[Frontend.scala:107:19, :138:29, :157:{24,46}]
wire s1_tlb_resp_gpa_is_pte = s1_is_replay & s1_tlb_resp_REG_gpa_is_pte; // @[Frontend.scala:138:29, :157:{24,46}]
wire s1_tlb_resp_pf_ld = s1_is_replay ? s1_tlb_resp_REG_pf_ld : _tlb_io_resp_pf_ld; // @[Frontend.scala:107:19, :138:29, :157:{24,46}]
wire s1_tlb_resp_pf_st = s1_is_replay & s1_tlb_resp_REG_pf_st; // @[Frontend.scala:138:29, :157:{24,46}]
wire s1_tlb_resp_pf_inst = s1_is_replay ? s1_tlb_resp_REG_pf_inst : _tlb_io_resp_pf_inst; // @[Frontend.scala:107:19, :138:29, :157:{24,46}]
wire s1_tlb_resp_gf_ld = s1_is_replay & s1_tlb_resp_REG_gf_ld; // @[Frontend.scala:138:29, :157:{24,46}]
wire s1_tlb_resp_gf_st = s1_is_replay & s1_tlb_resp_REG_gf_st; // @[Frontend.scala:138:29, :157:{24,46}]
wire s1_tlb_resp_gf_inst = s1_is_replay & s1_tlb_resp_REG_gf_inst; // @[Frontend.scala:138:29, :157:{24,46}]
wire s1_tlb_resp_ae_ld = s1_is_replay ? s1_tlb_resp_REG_ae_ld : _tlb_io_resp_ae_ld; // @[Frontend.scala:107:19, :138:29, :157:{24,46}]
wire s1_tlb_resp_ae_st = s1_is_replay & s1_tlb_resp_REG_ae_st; // @[Frontend.scala:138:29, :157:{24,46}]
wire s1_tlb_resp_ae_inst = s1_is_replay ? s1_tlb_resp_REG_ae_inst : _tlb_io_resp_ae_inst; // @[Frontend.scala:107:19, :138:29, :157:{24,46}]
wire s1_tlb_resp_ma_ld = s1_is_replay ? s1_tlb_resp_REG_ma_ld : _tlb_io_resp_ma_ld; // @[Frontend.scala:107:19, :138:29, :157:{24,46}]
wire s1_tlb_resp_ma_st = s1_is_replay & s1_tlb_resp_REG_ma_st; // @[Frontend.scala:138:29, :157:{24,46}]
wire s1_tlb_resp_ma_inst = s1_is_replay & s1_tlb_resp_REG_ma_inst; // @[Frontend.scala:138:29, :157:{24,46}]
wire s1_tlb_resp_cacheable = s1_is_replay ? s1_tlb_resp_REG_cacheable : _tlb_io_resp_cacheable; // @[Frontend.scala:107:19, :138:29, :157:{24,46}]
wire s1_tlb_resp_must_alloc = s1_is_replay & s1_tlb_resp_REG_must_alloc; // @[Frontend.scala:138:29, :157:{24,46}]
wire s1_tlb_resp_prefetchable = s1_is_replay ? s1_tlb_resp_REG_prefetchable : _tlb_io_resp_prefetchable; // @[Frontend.scala:107:19, :138:29, :157:{24,46}]
wire [1:0] s1_tlb_resp_size = s1_is_replay ? s1_tlb_resp_REG_size : 2'h3; // @[Frontend.scala:138:29, :157:{24,46}]
wire [4:0] s1_tlb_resp_cmd = s1_is_replay ? s1_tlb_resp_REG_cmd : 5'h0; // @[Frontend.scala:138:29, :157:{24,46}]
reg [31:0] s1_ppc_REG; // @[Frontend.scala:158:42]
wire [31:0] s1_ppc = s1_is_replay ? s1_ppc_REG : _tlb_io_resp_paddr; // @[Frontend.scala:107:19, :138:29, :158:{20,42}]
wire _icache_io_s1_kill_T = _tlb_io_resp_miss | f1_clear; // @[Frontend.scala:107:19, :139:30, :161:42]
wire [1:0] f1_mask_idx = s1_vpc[2:1]; // @[Frontend.scala:135:29]
wire [6:0] f1_mask = 7'hF << f1_mask_idx; // @[Frontend.scala:25:37]
wire [39:0] _f1_next_fetch_T = ~s1_vpc; // @[Frontend.scala:19:34, :135:29]
wire [39:0] _f1_next_fetch_T_1 = {_f1_next_fetch_T[39:3], 3'h7}; // @[Frontend.scala:19:{34,40}]
wire [39:0] _f1_next_fetch_T_2 = ~_f1_next_fetch_T_1; // @[Frontend.scala:19:{32,40}]
wire [40:0] _f1_next_fetch_T_3 = {1'h0, _f1_next_fetch_T_2} + 41'h8; // @[Frontend.scala:19:32, :22:48]
wire [39:0] f1_next_fetch = _f1_next_fetch_T_3[39:0]; // @[Frontend.scala:22:48]
wire f1_do_redirect = _btb_io_resp_valid & _btb_io_resp_bits_taken; // @[Frontend.scala:109:19, :166:42]
wire _f1_predicted_target_T = _btb_io_resp_bits_target[38]; // @[Frontend.scala:109:19]
wire [39:0] _f1_predicted_target_T_1 = {_f1_predicted_target_T, _btb_io_resp_bits_target}; // @[Frontend.scala:109:19]
wire [39:0] f1_predicted_target = f1_do_redirect ? _f1_predicted_target_T_1 : f1_next_fetch; // @[Frontend.scala:22:48, :166:42, :167:32]
wire _btb_io_bht_advance_valid_T = s1_valid & _btb_io_resp_valid; // @[Frontend.scala:109:19, :137:29, :179:40]
wire _s2_valid_T = ~f1_clear; // @[Frontend.scala:139:30, :141:58, :186:38]
wire _s2_valid_T_1 = s1_valid & _s2_valid_T; // @[Frontend.scala:137:29, :186:{35,38}]
reg s2_valid; // @[Frontend.scala:186:25]
reg [39:0] s2_vpc; // @[Frontend.scala:187:25]
wire [39:0] f2_fetch_bundle_pc = s2_vpc; // @[Frontend.scala:187:25, :245:29]
reg [31:0] s2_ppc; // @[Frontend.scala:188:24]
assign s0_replay_ppc = s2_ppc; // @[Frontend.scala:126:27, :188:24]
reg [2:0] s2_ras_head; // @[Frontend.scala:189:28]
wire [2:0] _f2_predicted_target_T = s2_ras_head; // @[Frontend.scala:189:28]
wire [2:0] f2_fetch_bundle_ras_head = s2_ras_head; // @[Frontend.scala:189:28, :245:29]
wire f2_clear; // @[Frontend.scala:190:26]
reg s2_tlb_resp_miss; // @[Frontend.scala:191:28]
assign s0_replay_resp_miss = s2_tlb_resp_miss; // @[Frontend.scala:125:28, :191:28]
reg [31:0] s2_tlb_resp_paddr; // @[Frontend.scala:191:28]
assign s0_replay_resp_paddr = s2_tlb_resp_paddr; // @[Frontend.scala:125:28, :191:28]
reg [39:0] s2_tlb_resp_gpa; // @[Frontend.scala:191:28]
assign s0_replay_resp_gpa = s2_tlb_resp_gpa; // @[Frontend.scala:125:28, :191:28]
reg s2_tlb_resp_gpa_is_pte; // @[Frontend.scala:191:28]
assign s0_replay_resp_gpa_is_pte = s2_tlb_resp_gpa_is_pte; // @[Frontend.scala:125:28, :191:28]
reg s2_tlb_resp_pf_ld; // @[Frontend.scala:191:28]
assign s0_replay_resp_pf_ld = s2_tlb_resp_pf_ld; // @[Frontend.scala:125:28, :191:28]
reg s2_tlb_resp_pf_st; // @[Frontend.scala:191:28]
assign s0_replay_resp_pf_st = s2_tlb_resp_pf_st; // @[Frontend.scala:125:28, :191:28]
reg s2_tlb_resp_pf_inst; // @[Frontend.scala:191:28]
assign s0_replay_resp_pf_inst = s2_tlb_resp_pf_inst; // @[Frontend.scala:125:28, :191:28]
wire f2_fetch_bundle_xcpt_pf_if = s2_tlb_resp_pf_inst; // @[Frontend.scala:191:28, :245:29]
reg s2_tlb_resp_gf_ld; // @[Frontend.scala:191:28]
assign s0_replay_resp_gf_ld = s2_tlb_resp_gf_ld; // @[Frontend.scala:125:28, :191:28]
reg s2_tlb_resp_gf_st; // @[Frontend.scala:191:28]
assign s0_replay_resp_gf_st = s2_tlb_resp_gf_st; // @[Frontend.scala:125:28, :191:28]
reg s2_tlb_resp_gf_inst; // @[Frontend.scala:191:28]
assign s0_replay_resp_gf_inst = s2_tlb_resp_gf_inst; // @[Frontend.scala:125:28, :191:28]
reg s2_tlb_resp_ae_ld; // @[Frontend.scala:191:28]
assign s0_replay_resp_ae_ld = s2_tlb_resp_ae_ld; // @[Frontend.scala:125:28, :191:28]
reg s2_tlb_resp_ae_st; // @[Frontend.scala:191:28]
assign s0_replay_resp_ae_st = s2_tlb_resp_ae_st; // @[Frontend.scala:125:28, :191:28]
reg s2_tlb_resp_ae_inst; // @[Frontend.scala:191:28]
assign s0_replay_resp_ae_inst = s2_tlb_resp_ae_inst; // @[Frontend.scala:125:28, :191:28]
wire f2_fetch_bundle_xcpt_ae_if = s2_tlb_resp_ae_inst; // @[Frontend.scala:191:28, :245:29]
reg s2_tlb_resp_ma_ld; // @[Frontend.scala:191:28]
assign s0_replay_resp_ma_ld = s2_tlb_resp_ma_ld; // @[Frontend.scala:125:28, :191:28]
reg s2_tlb_resp_ma_st; // @[Frontend.scala:191:28]
assign s0_replay_resp_ma_st = s2_tlb_resp_ma_st; // @[Frontend.scala:125:28, :191:28]
reg s2_tlb_resp_ma_inst; // @[Frontend.scala:191:28]
assign s0_replay_resp_ma_inst = s2_tlb_resp_ma_inst; // @[Frontend.scala:125:28, :191:28]
reg s2_tlb_resp_cacheable; // @[Frontend.scala:191:28]
assign s0_replay_resp_cacheable = s2_tlb_resp_cacheable; // @[Frontend.scala:125:28, :191:28]
reg s2_tlb_resp_must_alloc; // @[Frontend.scala:191:28]
assign s0_replay_resp_must_alloc = s2_tlb_resp_must_alloc; // @[Frontend.scala:125:28, :191:28]
reg s2_tlb_resp_prefetchable; // @[Frontend.scala:191:28]
assign s0_replay_resp_prefetchable = s2_tlb_resp_prefetchable; // @[Frontend.scala:125:28, :191:28]
reg [1:0] s2_tlb_resp_size; // @[Frontend.scala:191:28]
assign s0_replay_resp_size = s2_tlb_resp_size; // @[Frontend.scala:125:28, :191:28]
reg [4:0] s2_tlb_resp_cmd; // @[Frontend.scala:191:28]
assign s0_replay_resp_cmd = s2_tlb_resp_cmd; // @[Frontend.scala:125:28, :191:28]
reg s2_tlb_miss; // @[Frontend.scala:192:28]
reg s2_is_replay_REG; // @[Frontend.scala:193:29]
wire s2_is_replay = s2_is_replay_REG & s2_valid; // @[Frontend.scala:186:25, :193:{29,44}]
wire _GEN = s2_tlb_resp_ae_inst | s2_tlb_resp_pf_inst; // @[Frontend.scala:191:28, :194:50]
wire _s2_xcpt_T; // @[Frontend.scala:194:50]
assign _s2_xcpt_T = _GEN; // @[Frontend.scala:194:50]
wire _s0_valid_T_7; // @[Frontend.scala:338:46]
assign _s0_valid_T_7 = _GEN; // @[Frontend.scala:194:50, :338:46]
wire _fb_io_enq_valid_T_2; // @[Frontend.scala:349:52]
assign _fb_io_enq_valid_T_2 = _GEN; // @[Frontend.scala:194:50, :349:52]
wire _s2_xcpt_T_1 = s2_valid & _s2_xcpt_T; // @[Frontend.scala:186:25, :194:{26,50}]
wire _s2_xcpt_T_2 = ~s2_is_replay; // @[Frontend.scala:193:44, :194:77]
wire s2_xcpt = _s2_xcpt_T_1 & _s2_xcpt_T_2; // @[Frontend.scala:194:{26,74,77}]
reg s2_btb_resp_valid; // @[Frontend.scala:195:28]
wire f2_fetch_bundle_btb_resp_valid = s2_btb_resp_valid; // @[Frontend.scala:195:28, :245:29]
reg [1:0] s2_btb_resp_bits_cfiType; // @[Frontend.scala:195:28]
wire [1:0] f2_fetch_bundle_btb_resp_bits_cfiType = s2_btb_resp_bits_cfiType; // @[Frontend.scala:195:28, :245:29]
reg s2_btb_resp_bits_taken; // @[Frontend.scala:195:28]
wire f2_fetch_bundle_btb_resp_bits_taken = s2_btb_resp_bits_taken; // @[Frontend.scala:195:28, :245:29]
reg [3:0] s2_btb_resp_bits_mask; // @[Frontend.scala:195:28]
wire [3:0] f2_fetch_bundle_btb_resp_bits_mask = s2_btb_resp_bits_mask; // @[Frontend.scala:195:28, :245:29]
reg [1:0] s2_btb_resp_bits_bridx; // @[Frontend.scala:195:28]
wire [1:0] f2_fetch_bundle_btb_resp_bits_bridx = s2_btb_resp_bits_bridx; // @[Frontend.scala:195:28, :245:29]
reg [38:0] s2_btb_resp_bits_target; // @[Frontend.scala:195:28]
wire [38:0] f2_fetch_bundle_btb_resp_bits_target = s2_btb_resp_bits_target; // @[Frontend.scala:195:28, :245:29]
reg [5:0] s2_btb_resp_bits_entry; // @[Frontend.scala:195:28]
wire [5:0] f2_fetch_bundle_btb_resp_bits_entry = s2_btb_resp_bits_entry; // @[Frontend.scala:195:28, :245:29]
reg [7:0] s2_btb_resp_bits_bht_history; // @[Frontend.scala:195:28]
wire [7:0] f2_fetch_bundle_btb_resp_bits_bht_history = s2_btb_resp_bits_bht_history; // @[Frontend.scala:195:28, :245:29]
reg [1:0] s2_btb_resp_bits_bht_value; // @[Frontend.scala:195:28]
wire [1:0] f2_fetch_bundle_btb_resp_bits_bht_value = s2_btb_resp_bits_bht_value; // @[Frontend.scala:195:28, :245:29]
wire f3_ready; // @[Frontend.scala:196:22]
wire [1:0] f2_fetch_mask_idx = s2_vpc[2:1]; // @[Frontend.scala:187:25]
wire [6:0] f2_fetch_mask = 7'hF << f2_fetch_mask_idx; // @[Frontend.scala:25:37]
reg [39:0] f2_next_fetch; // @[Frontend.scala:201:30]
wire [39:0] _f2_aligned_pc_T = ~s2_vpc; // @[Frontend.scala:19:34, :187:25]
wire [39:0] _f2_aligned_pc_T_1 = {_f2_aligned_pc_T[39:3], 3'h7}; // @[Frontend.scala:19:{34,40}]
wire [39:0] f2_aligned_pc = ~_f2_aligned_pc_T_1; // @[Frontend.scala:19:{32,40}]
wire _f2_inst_mask_0_T_4; // @[Frontend.scala:268:62]
wire _f2_inst_mask_1_T_4; // @[Frontend.scala:268:62]
wire _f2_inst_mask_2_T_4; // @[Frontend.scala:268:62]
wire _f2_inst_mask_3_T_4; // @[Frontend.scala:268:62]
wire f2_inst_mask_0; // @[Frontend.scala:205:27]
wire f2_inst_mask_1; // @[Frontend.scala:205:27]
wire f2_inst_mask_2; // @[Frontend.scala:205:27]
wire f2_inst_mask_3; // @[Frontend.scala:205:27]
wire _f2_call_mask_0_T_6; // @[Frontend.scala:260:71]
wire _f2_call_mask_1_T_6; // @[Frontend.scala:260:71]
wire _f2_call_mask_2_T_6; // @[Frontend.scala:260:71]
wire _f2_call_mask_3_T_6; // @[Frontend.scala:260:71]
wire f2_call_mask_0; // @[Frontend.scala:206:27]
wire f2_call_mask_1; // @[Frontend.scala:206:27]
wire f2_call_mask_2; // @[Frontend.scala:206:27]
wire f2_call_mask_3; // @[Frontend.scala:206:27]
wire _f2_ret_mask_0_T_8; // @[Frontend.scala:261:65]
wire _f2_ret_mask_1_T_8; // @[Frontend.scala:261:65]
wire _f2_ret_mask_2_T_8; // @[Frontend.scala:261:65]
wire _f2_ret_mask_3_T_8; // @[Frontend.scala:261:65]
wire f2_ret_mask_0; // @[Frontend.scala:207:27]
wire f2_ret_mask_1; // @[Frontend.scala:207:27]
wire f2_ret_mask_2; // @[Frontend.scala:207:27]
wire f2_ret_mask_3; // @[Frontend.scala:207:27]
wire [1:0] f2_do_call_lo = {f2_call_mask_1, f2_call_mask_0}; // @[Frontend.scala:206:27, :208:34]
wire [1:0] f2_do_call_hi = {f2_call_mask_3, f2_call_mask_2}; // @[Frontend.scala:206:27, :208:34]
wire [3:0] _f2_do_call_T = {f2_do_call_hi, f2_do_call_lo}; // @[Frontend.scala:208:34]
wire [1:0] _GEN_0 = {f2_inst_mask_1, f2_inst_mask_0}; // @[Frontend.scala:205:27, :208:56]
wire [1:0] f2_do_call_lo_1; // @[Frontend.scala:208:56]
assign f2_do_call_lo_1 = _GEN_0; // @[Frontend.scala:208:56]
wire [1:0] f2_do_ret_lo_1; // @[Frontend.scala:209:55]
assign f2_do_ret_lo_1 = _GEN_0; // @[Frontend.scala:208:56, :209:55]
wire [1:0] f2_fetch_bundle_mask_lo; // @[Frontend.scala:252:46]
assign f2_fetch_bundle_mask_lo = _GEN_0; // @[Frontend.scala:208:56, :252:46]
wire [1:0] _GEN_1 = {f2_inst_mask_3, f2_inst_mask_2}; // @[Frontend.scala:205:27, :208:56]
wire [1:0] f2_do_call_hi_1; // @[Frontend.scala:208:56]
assign f2_do_call_hi_1 = _GEN_1; // @[Frontend.scala:208:56]
wire [1:0] f2_do_ret_hi_1; // @[Frontend.scala:209:55]
assign f2_do_ret_hi_1 = _GEN_1; // @[Frontend.scala:208:56, :209:55]
wire [1:0] f2_fetch_bundle_mask_hi; // @[Frontend.scala:252:46]
assign f2_fetch_bundle_mask_hi = _GEN_1; // @[Frontend.scala:208:56, :252:46]
wire [3:0] _f2_do_call_T_1 = {f2_do_call_hi_1, f2_do_call_lo_1}; // @[Frontend.scala:208:56]
wire [3:0] _f2_do_call_T_2 = _f2_do_call_T & _f2_do_call_T_1; // @[Frontend.scala:208:{34,41,56}]
wire f2_do_call = |_f2_do_call_T_2; // @[Frontend.scala:208:{41,64}]
wire [1:0] f2_do_ret_lo = {f2_ret_mask_1, f2_ret_mask_0}; // @[Frontend.scala:207:27, :209:33]
wire [1:0] f2_do_ret_hi = {f2_ret_mask_3, f2_ret_mask_2}; // @[Frontend.scala:207:27, :209:33]
wire [3:0] _f2_do_ret_T = {f2_do_ret_hi, f2_do_ret_lo}; // @[Frontend.scala:209:33]
wire [3:0] _f2_do_ret_T_1 = {f2_do_ret_hi_1, f2_do_ret_lo_1}; // @[Frontend.scala:209:55]
wire [3:0] _f2_do_ret_T_2 = _f2_do_ret_T & _f2_do_ret_T_1; // @[Frontend.scala:209:{33,40,55}]
wire f2_do_ret = |_f2_do_ret_T_2; // @[Frontend.scala:209:{40,63}]
wire _f2_npc_plus4_mask_0_T_7; // @[Frontend.scala:277:64]
wire _f2_npc_plus4_mask_1_T_2; // @[Frontend.scala:275:29]
wire _f2_npc_plus4_mask_2_T_2; // @[Frontend.scala:275:29]
wire _f2_npc_plus4_mask_3_T_2; // @[Frontend.scala:275:29]
wire f2_npc_plus4_mask_0; // @[Frontend.scala:210:31]
wire f2_npc_plus4_mask_1; // @[Frontend.scala:210:31]
wire f2_npc_plus4_mask_2; // @[Frontend.scala:210:31]
wire f2_npc_plus4_mask_3; // @[Frontend.scala:210:31]
wire f2_do_redirect; // @[Frontend.scala:212:32]
wire f2_fetch_bundle_next_pc_valid = f2_do_redirect; // @[Frontend.scala:212:32, :245:29]
wire [1:0] f2_redirect_bridx; // @[Frontend.scala:213:35]
wire [2:0] _f2_predicted_target_T_1 = _f2_predicted_target_T;
reg [39:0] f2_predicted_target_REG; // @[Frontend.scala:215:45]
wire [7:0][39:0] _GEN_2 = {{ras_0}, {ras_0}, {ras_5}, {ras_4}, {ras_3}, {ras_2}, {ras_1}, {ras_0}}; // @[Frontend.scala:110:16, :215:8]
wire [39:0] _f2_predicted_target_T_2 = f2_do_ret ? _GEN_2[_f2_predicted_target_T_1] : f2_predicted_target_REG; // @[Frontend.scala:209:63, :215:{8,45}]
reg [39:0] f2_predicted_target_REG_1; // @[Frontend.scala:216:12]
wire [39:0] f2_predicted_target = f2_do_redirect ? _f2_predicted_target_T_2 : f2_predicted_target_REG_1; // @[Frontend.scala:212:32, :214:32, :215:8, :216:12]
wire [39:0] f2_fetch_bundle_next_pc_bits = f2_predicted_target; // @[Frontend.scala:214:32, :245:29]
wire ras_write_val; // @[Frontend.scala:219:31]
wire [2:0] ras_write_idx; // @[Frontend.scala:220:31]
wire [39:0] ras_write_addr; // @[Frontend.scala:221:32]
wire _ras_next_head_T = s2_ras_head == 3'h5; // @[Frontend.scala:189:28, :222:55]
wire [3:0] _GEN_3 = {1'h0, s2_ras_head}; // @[Frontend.scala:189:28, :222:98]
wire [3:0] _ras_next_head_T_1 = _GEN_3 + 4'h1; // @[Frontend.scala:222:98]
wire [2:0] _ras_next_head_T_2 = _ras_next_head_T_1[2:0]; // @[Frontend.scala:222:98]
wire [2:0] _ras_next_head_T_3 = _ras_next_head_T ? 3'h0 : _ras_next_head_T_2; // @[Frontend.scala:222:{42,55,98}]
wire _ras_next_head_T_4 = s2_ras_head == 3'h0; // @[Frontend.scala:189:28, :223:36]
wire [3:0] _ras_next_head_T_5 = _GEN_3 - 4'h1; // @[Frontend.scala:222:98, :223:79]
wire [2:0] _ras_next_head_T_6 = _ras_next_head_T_5[2:0]; // @[Frontend.scala:223:79]
wire [2:0] _ras_next_head_T_7 = _ras_next_head_T_4 ? 3'h5 : _ras_next_head_T_6; // @[Frontend.scala:223:{23,36,79}]
wire [2:0] _ras_next_head_T_8 = f2_do_ret ? _ras_next_head_T_7 : s2_ras_head; // @[Frontend.scala:189:28, :209:63, :223:{8,23}]
wire [2:0] ras_next_head = f2_do_call ? _ras_next_head_T_3 : _ras_next_head_T_8; // @[Frontend.scala:208:64, :222:{26,42}, :223:8]
wire _T_3 = (f2_do_call | f2_do_ret) & s2_valid & f3_ready & _icache_io_resp_valid; // @[Frontend.scala:58:26, :186:25, :196:22, :208:64, :209:63, :224:{21,35,47,59}]
assign s1_ras_head = _T_3 ? ras_next_head : s1_ras_head_REG; // @[Frontend.scala:136:{30,38}, :222:26, :224:{35,47,59,84}, :226:17]
assign ras_write_val = _T_3 & f2_do_call; // @[Frontend.scala:208:64, :219:31, :224:{35,47,59,84}, :227:23]
wire _GEN_4 = _T_3 & f2_do_call; // @[Frontend.scala:208:64, :220:31, :224:{35,47,59,84}, :227:23, :229:21]
assign ras_write_idx = _GEN_4 ? ras_next_head : 3'h0; // @[Frontend.scala:220:31, :222:26, :224:84, :227:23, :229:21]
wire [2:0] _ras_write_addr_T = {f2_redirect_bridx, 1'h0}; // @[Frontend.scala:213:35, :230:60]
wire [40:0] _f2_fetch_bundle_pcs_0_T = {1'h0, f2_aligned_pc}; // @[Frontend.scala:19:32, :230:39, :269:45]
wire [40:0] _ras_write_addr_T_1 = _f2_fetch_bundle_pcs_0_T + {38'h0, _ras_write_addr_T}; // @[Frontend.scala:230:{39,60}, :269:45]
wire [39:0] _ras_write_addr_T_2 = _ras_write_addr_T_1[39:0]; // @[Frontend.scala:230:39]
wire [3:0] _GEN_5 = {{f2_npc_plus4_mask_3}, {f2_npc_plus4_mask_2}, {f2_npc_plus4_mask_1}, {f2_npc_plus4_mask_0}}; // @[Frontend.scala:210:31, :230:71]
wire [2:0] _ras_write_addr_T_3 = _GEN_5[s2_btb_resp_bits_bridx] ? 3'h4 : 3'h2; // @[Frontend.scala:195:28, :230:71]
wire [40:0] _ras_write_addr_T_4 = {1'h0, _ras_write_addr_T_2} + {38'h0, _ras_write_addr_T_3}; // @[Frontend.scala:230:{39,66,71}]
wire [39:0] _ras_write_addr_T_5 = _ras_write_addr_T_4[39:0]; // @[Frontend.scala:230:66]
assign ras_write_addr = _GEN_4 ? _ras_write_addr_T_5 : 40'h0; // @[Frontend.scala:220:31, :221:32, :224:84, :227:23, :229:21, :230:{22,66}]
reg REG; // @[Frontend.scala:234:44]
reg [2:0] idx_REG; // @[Frontend.scala:235:80]
wire [2:0] idx = io_cpu_ras_update_valid_0 ? io_cpu_ras_update_bits_head_0 : idx_REG; // @[Frontend.scala:93:7, :235:{18,80}]
reg [39:0] addr_REG; // @[Frontend.scala:236:81]
wire [39:0] addr = io_cpu_ras_update_valid_0 ? io_cpu_ras_update_bits_addr_0 : addr_REG; // @[Frontend.scala:93:7, :236:{19,81}]
reg [15:0] f2_prev_half; // @[Frontend.scala:241:25]
reg f2_prev_is_half; // @[Frontend.scala:243:32]
wire f2_fetch_bundle_edge_inst = f2_prev_is_half; // @[Frontend.scala:243:32, :245:29]
wire _f2_fetch_bundle_pcs_0_T_2 = f2_fetch_bundle_edge_inst; // @[Frontend.scala:245:29, :269:88]
wire [31:0] inst; // @[Frontend.scala:301:29]
wire [31:0] inst_1; // @[Frontend.scala:313:29]
wire [31:0] inst_2; // @[Frontend.scala:307:21]
wire [31:0] expanded_2; // @[Consts.scala:43:8]
wire [31:0] expanded_3; // @[Consts.scala:43:8]
wire [31:0] expanded_4; // @[Consts.scala:43:8]
wire [39:0] _f2_fetch_bundle_pcs_0_T_5; // @[Frontend.scala:269:58]
wire [39:0] _f2_fetch_bundle_pcs_1_T_5; // @[Frontend.scala:269:58]
wire [39:0] _f2_fetch_bundle_pcs_2_T_5; // @[Frontend.scala:269:58]
wire [39:0] _f2_fetch_bundle_pcs_3_T_5; // @[Frontend.scala:269:58]
wire [3:0] _f2_fetch_bundle_mask_T; // @[Frontend.scala:252:46]
wire _f2_fetch_bundle_end_half_valid_T_8; // @[Frontend.scala:321:115]
wire [15:0] last_inst; // @[Frontend.scala:320:54]
wire [31:0] f2_fetch_bundle_insts_0; // @[Frontend.scala:245:29]
wire [31:0] f2_fetch_bundle_insts_1; // @[Frontend.scala:245:29]
wire [31:0] f2_fetch_bundle_insts_2; // @[Frontend.scala:245:29]
wire [31:0] f2_fetch_bundle_insts_3; // @[Frontend.scala:245:29]
wire [31:0] f2_fetch_bundle_exp_insts_0; // @[Frontend.scala:245:29]
wire [31:0] f2_fetch_bundle_exp_insts_1; // @[Frontend.scala:245:29]
wire [31:0] f2_fetch_bundle_exp_insts_2; // @[Frontend.scala:245:29]
wire [31:0] f2_fetch_bundle_exp_insts_3; // @[Frontend.scala:245:29]
wire [39:0] f2_fetch_bundle_pcs_0; // @[Frontend.scala:245:29]
wire [39:0] f2_fetch_bundle_pcs_1; // @[Frontend.scala:245:29]
wire [39:0] f2_fetch_bundle_pcs_2; // @[Frontend.scala:245:29]
wire [39:0] f2_fetch_bundle_pcs_3; // @[Frontend.scala:245:29]
wire f2_fetch_bundle_end_half_valid; // @[Frontend.scala:245:29]
wire [15:0] f2_fetch_bundle_end_half_bits; // @[Frontend.scala:245:29]
wire [3:0] f2_fetch_bundle_mask; // @[Frontend.scala:245:29]
assign _f2_fetch_bundle_mask_T = {f2_fetch_bundle_mask_hi, f2_fetch_bundle_mask_lo}; // @[Frontend.scala:252:46]
assign f2_fetch_bundle_mask = _f2_fetch_bundle_mask_T; // @[Frontend.scala:245:29, :252:46]
wire _f2_inst_mask_0_T = f2_fetch_mask[0]; // @[Frontend.scala:25:37, :268:49]
wire _f2_inst_mask_0_T_1 = s2_valid & _f2_inst_mask_0_T; // @[Frontend.scala:186:25, :268:{33,49}]
wire _f2_inst_mask_0_T_2 = _f2_inst_mask_0_T_1; // @[Frontend.scala:268:{33,53}]
assign _f2_inst_mask_0_T_4 = _f2_inst_mask_0_T_2; // @[Frontend.scala:268:{53,62}]
assign f2_inst_mask_0 = _f2_inst_mask_0_T_4; // @[Frontend.scala:205:27, :268:62]
wire [39:0] _f2_fetch_bundle_pcs_0_T_1 = _f2_fetch_bundle_pcs_0_T[39:0]; // @[Frontend.scala:269:45]
wire [1:0] _f2_fetch_bundle_pcs_0_T_3 = {_f2_fetch_bundle_pcs_0_T_2, 1'h0}; // @[Frontend.scala:269:{88,103}]
wire [40:0] _f2_fetch_bundle_pcs_0_T_4 = {1'h0, _f2_fetch_bundle_pcs_0_T_1} - {39'h0, _f2_fetch_bundle_pcs_0_T_3}; // @[Frontend.scala:269:{45,58,103}]
assign _f2_fetch_bundle_pcs_0_T_5 = _f2_fetch_bundle_pcs_0_T_4[39:0]; // @[Frontend.scala:269:58]
assign f2_fetch_bundle_pcs_0 = _f2_fetch_bundle_pcs_0_T_5; // @[Frontend.scala:245:29, :269:58]
wire _redir_br_T_2 = s2_btb_resp_bits_bridx == 2'h0; // @[Frontend.scala:195:28, :270:65, :279:53]
wire [6:0] _f2_call_mask_0_T = f2_fetch_bundle_exp_insts_0[6:0]; // @[Frontend.scala:245:29, :258:40]
wire [6:0] _f2_call_mask_0_T_2 = f2_fetch_bundle_exp_insts_0[6:0]; // @[Frontend.scala:245:29, :258:40, :259:40]
wire [6:0] _f2_ret_mask_0_T = f2_fetch_bundle_exp_insts_0[6:0]; // @[Frontend.scala:245:29, :258:40]
wire [6:0] _redir_br_T = f2_fetch_bundle_exp_insts_0[6:0]; // @[Frontend.scala:245:29, :258:40, :262:39]
wire [6:0] _redir_T = f2_fetch_bundle_exp_insts_0[6:0]; // @[Frontend.scala:245:29, :258:40]
wire [6:0] _redir_T_2 = f2_fetch_bundle_exp_insts_0[6:0]; // @[Frontend.scala:245:29, :258:40, :259:40]
wire _f2_call_mask_0_T_1 = _f2_call_mask_0_T == 7'h67; // @[Frontend.scala:258:{40,46}]
wire _f2_call_mask_0_T_3 = _f2_call_mask_0_T_2 == 7'h6F; // @[Frontend.scala:259:{40,46}]
wire _f2_call_mask_0_T_4 = _f2_call_mask_0_T_1 | _f2_call_mask_0_T_3; // @[Frontend.scala:258:46, :259:46, :260:50]
wire _f2_call_mask_0_T_5 = f2_fetch_bundle_exp_insts_0[7]; // @[Frontend.scala:245:29, :260:82]
wire _f2_ret_mask_0_T_2 = f2_fetch_bundle_exp_insts_0[7]; // @[Frontend.scala:245:29, :260:82, :261:61]
assign _f2_call_mask_0_T_6 = _f2_call_mask_0_T_4 & _f2_call_mask_0_T_5; // @[Frontend.scala:260:{50,71,82}]
assign f2_call_mask_0 = _f2_call_mask_0_T_6; // @[Frontend.scala:206:27, :260:71]
wire _f2_ret_mask_0_T_1 = _f2_ret_mask_0_T == 7'h67; // @[Frontend.scala:258:{40,46}]
wire _f2_ret_mask_0_T_3 = ~_f2_ret_mask_0_T_2; // @[Frontend.scala:261:{52,61}]
wire _f2_ret_mask_0_T_4 = _f2_ret_mask_0_T_1 & _f2_ret_mask_0_T_3; // @[Frontend.scala:258:46, :261:{49,52}]
wire [4:0] _f2_ret_mask_0_T_5 = f2_fetch_bundle_exp_insts_0[19:15]; // @[Frontend.scala:245:29, :261:97]
wire [4:0] _f2_ret_mask_0_T_6 = _f2_ret_mask_0_T_5 & 5'h1B; // @[Frontend.scala:261:{85,97}]
wire _f2_ret_mask_0_T_7 = _f2_ret_mask_0_T_6 == 5'h1; // @[Frontend.scala:261:85]
assign _f2_ret_mask_0_T_8 = _f2_ret_mask_0_T_4 & _f2_ret_mask_0_T_7; // @[Frontend.scala:261:{49,65,85}]
assign f2_ret_mask_0 = _f2_ret_mask_0_T_8; // @[Frontend.scala:207:27, :261:65]
wire [1:0] _f2_npc_plus4_mask_0_T = f2_fetch_bundle_insts_0[1:0]; // @[Frontend.scala:245:29, :256:32]
wire [1:0] _f2_npc_plus4_mask_0_T_3 = f2_fetch_bundle_insts_0[1:0]; // @[Frontend.scala:245:29, :256:32]
wire [1:0] _valid_T = f2_fetch_bundle_insts_0[1:0]; // @[Frontend.scala:245:29, :256:32]
wire _f2_npc_plus4_mask_0_T_1 = _f2_npc_plus4_mask_0_T != 2'h3; // @[Frontend.scala:256:{32,38}]
wire _f2_npc_plus4_mask_0_T_2 = ~_f2_npc_plus4_mask_0_T_1; // @[Frontend.scala:256:38, :275:29]
wire _f2_npc_plus4_mask_0_T_4 = _f2_npc_plus4_mask_0_T_3 != 2'h3; // @[Frontend.scala:256:{32,38}]
wire _f2_npc_plus4_mask_0_T_5 = ~_f2_npc_plus4_mask_0_T_4; // @[Frontend.scala:256:38, :277:31]
wire _f2_npc_plus4_mask_0_T_6 = ~f2_fetch_bundle_edge_inst; // @[Frontend.scala:245:29, :277:67]
assign _f2_npc_plus4_mask_0_T_7 = _f2_npc_plus4_mask_0_T_5 & _f2_npc_plus4_mask_0_T_6; // @[Frontend.scala:277:{31,64,67}]
assign f2_npc_plus4_mask_0 = _f2_npc_plus4_mask_0_T_7; // @[Frontend.scala:210:31, :277:64]
wire _redir_br_T_1 = _redir_br_T == 7'h63; // @[Frontend.scala:262:{39,45}]
wire _redir_br_T_3 = s2_btb_resp_valid & _redir_br_T_2; // @[Frontend.scala:195:28, :279:{27,53}]
wire _redir_br_T_4 = _redir_br_T_3 & s2_btb_resp_bits_taken; // @[Frontend.scala:195:28, :279:{27,61}]
wire _redir_br_T_5 = s2_btb_resp_bits_bht_value[0]; // @[Frontend.scala:195:28]
wire _redir_br_T_12 = s2_btb_resp_bits_bht_value[0]; // @[Frontend.scala:195:28]
wire _redir_br_T_19 = s2_btb_resp_bits_bht_value[0]; // @[Frontend.scala:195:28]
wire _redir_br_T_26 = s2_btb_resp_bits_bht_value[0]; // @[Frontend.scala:195:28]
wire _redir_br_T_6 = _redir_br_T_4 & _redir_br_T_5; // @[Frontend.scala:279:{61,87}]
wire redir_br = _redir_br_T_1 & _redir_br_T_6; // @[Frontend.scala:262:45, :278:56, :279:87]
wire _redir_T_1 = _redir_T == 7'h67; // @[Frontend.scala:258:{40,46}]
wire _redir_T_3 = _redir_T_2 == 7'h6F; // @[Frontend.scala:259:{40,46}]
wire _redir_T_4 = _redir_T_1 | _redir_T_3; // @[Frontend.scala:258:46, :259:46, :280:74]
wire _redir_T_5 = _redir_T_4 | redir_br; // @[Frontend.scala:278:56, :280:{74,114}]
wire redir = f2_inst_mask_0 & _redir_T_5; // @[Frontend.scala:205:27, :280:{33,114}]
wire [15:0] _expanded_T = _icache_io_resp_bits[15:0]; // @[Frontend.scala:58:26, :289:49]
wire [15:0] _f2_fetch_bundle_insts_0_T = _icache_io_resp_bits[15:0]; // @[Frontend.scala:58:26, :289:49, :290:56]
wire [31:0] _expanded_T_1 = {_expanded_T, f2_prev_half}; // @[Frontend.scala:241:25, :289:{37,49}]
wire [31:0] expanded = _expanded_rvc_exp_io_rvc ? _expanded_rvc_exp_io_out_bits : _expanded_T_1; // @[Frontend.scala:289:37]
wire [31:0] _f2_fetch_bundle_insts_0_T_1 = {_f2_fetch_bundle_insts_0_T, f2_prev_half}; // @[Frontend.scala:241:25, :290:{44,56}]
wire [31:0] _expanded_T_2 = _icache_io_resp_bits[31:0]; // @[Frontend.scala:58:26, :294:45]
wire [31:0] _f2_fetch_bundle_insts_0_T_2 = _icache_io_resp_bits[31:0]; // @[Frontend.scala:58:26, :294:45, :295:52]
wire [31:0] expanded_1 = _expanded_rvc_exp_1_io_rvc ? _expanded_rvc_exp_1_io_out_bits : _expanded_T_2; // @[Frontend.scala:294:45]
assign f2_fetch_bundle_insts_0 = f2_prev_is_half ? _f2_fetch_bundle_insts_0_T_1 : _f2_fetch_bundle_insts_0_T_2; // @[Frontend.scala:243:32, :245:29, :288:30, :290:{38,44}, :295:{38,52}]
assign f2_fetch_bundle_exp_insts_0 = f2_prev_is_half ? expanded : expanded_1; // @[Frontend.scala:243:32, :245:29, :288:30, :291:38, :296:38]
wire _valid_T_5; // @[Frontend.scala:305:32]
wire valid_1; // @[Frontend.scala:267:21]
wire _f2_inst_mask_1_T = f2_fetch_mask[1]; // @[Frontend.scala:25:37, :268:49]
wire _f2_inst_mask_1_T_1 = s2_valid & _f2_inst_mask_1_T; // @[Frontend.scala:186:25, :268:{33,49}]
wire _f2_inst_mask_1_T_2 = _f2_inst_mask_1_T_1 & valid_1; // @[Frontend.scala:267:21, :268:{33,53}]
wire _f2_inst_mask_1_T_3 = ~redir; // @[Frontend.scala:268:65, :280:33]
assign _f2_inst_mask_1_T_4 = _f2_inst_mask_1_T_2 & _f2_inst_mask_1_T_3; // @[Frontend.scala:268:{53,62,65}]
assign f2_inst_mask_1 = _f2_inst_mask_1_T_4; // @[Frontend.scala:205:27, :268:62]
wire [40:0] _f2_fetch_bundle_pcs_1_T = _f2_fetch_bundle_pcs_0_T + 41'h2; // @[Frontend.scala:269:45]
wire [39:0] _f2_fetch_bundle_pcs_1_T_1 = _f2_fetch_bundle_pcs_1_T[39:0]; // @[Frontend.scala:269:45]
wire [40:0] _f2_fetch_bundle_pcs_1_T_4 = {1'h0, _f2_fetch_bundle_pcs_1_T_1}; // @[Frontend.scala:269:{45,58}]
assign _f2_fetch_bundle_pcs_1_T_5 = _f2_fetch_bundle_pcs_1_T_4[39:0]; // @[Frontend.scala:269:58]
assign f2_fetch_bundle_pcs_1 = _f2_fetch_bundle_pcs_1_T_5; // @[Frontend.scala:245:29, :269:58]
wire _redir_br_T_9 = s2_btb_resp_bits_bridx == 2'h1; // @[Frontend.scala:195:28, :270:65, :279:53]
wire [6:0] _f2_call_mask_1_T = f2_fetch_bundle_exp_insts_1[6:0]; // @[Frontend.scala:245:29, :258:40]
wire [6:0] _f2_call_mask_1_T_2 = f2_fetch_bundle_exp_insts_1[6:0]; // @[Frontend.scala:245:29, :258:40, :259:40]
wire [6:0] _f2_ret_mask_1_T = f2_fetch_bundle_exp_insts_1[6:0]; // @[Frontend.scala:245:29, :258:40]
wire [6:0] _redir_br_T_7 = f2_fetch_bundle_exp_insts_1[6:0]; // @[Frontend.scala:245:29, :258:40, :262:39]
wire [6:0] _redir_T_6 = f2_fetch_bundle_exp_insts_1[6:0]; // @[Frontend.scala:245:29, :258:40]
wire [6:0] _redir_T_8 = f2_fetch_bundle_exp_insts_1[6:0]; // @[Frontend.scala:245:29, :258:40, :259:40]
wire _f2_call_mask_1_T_1 = _f2_call_mask_1_T == 7'h67; // @[Frontend.scala:258:{40,46}]
wire _f2_call_mask_1_T_3 = _f2_call_mask_1_T_2 == 7'h6F; // @[Frontend.scala:259:{40,46}]
wire _f2_call_mask_1_T_4 = _f2_call_mask_1_T_1 | _f2_call_mask_1_T_3; // @[Frontend.scala:258:46, :259:46, :260:50]
wire _f2_call_mask_1_T_5 = f2_fetch_bundle_exp_insts_1[7]; // @[Frontend.scala:245:29, :260:82]
wire _f2_ret_mask_1_T_2 = f2_fetch_bundle_exp_insts_1[7]; // @[Frontend.scala:245:29, :260:82, :261:61]
assign _f2_call_mask_1_T_6 = _f2_call_mask_1_T_4 & _f2_call_mask_1_T_5; // @[Frontend.scala:260:{50,71,82}]
assign f2_call_mask_1 = _f2_call_mask_1_T_6; // @[Frontend.scala:206:27, :260:71]
wire _f2_ret_mask_1_T_1 = _f2_ret_mask_1_T == 7'h67; // @[Frontend.scala:258:{40,46}]
wire _f2_ret_mask_1_T_3 = ~_f2_ret_mask_1_T_2; // @[Frontend.scala:261:{52,61}]
wire _f2_ret_mask_1_T_4 = _f2_ret_mask_1_T_1 & _f2_ret_mask_1_T_3; // @[Frontend.scala:258:46, :261:{49,52}]
wire [4:0] _f2_ret_mask_1_T_5 = f2_fetch_bundle_exp_insts_1[19:15]; // @[Frontend.scala:245:29, :261:97]
wire [4:0] _f2_ret_mask_1_T_6 = _f2_ret_mask_1_T_5 & 5'h1B; // @[Frontend.scala:261:{85,97}]
wire _f2_ret_mask_1_T_7 = _f2_ret_mask_1_T_6 == 5'h1; // @[Frontend.scala:261:85]
assign _f2_ret_mask_1_T_8 = _f2_ret_mask_1_T_4 & _f2_ret_mask_1_T_7; // @[Frontend.scala:261:{49,65,85}]
assign f2_ret_mask_1 = _f2_ret_mask_1_T_8; // @[Frontend.scala:207:27, :261:65]
wire [1:0] _f2_npc_plus4_mask_1_T = f2_fetch_bundle_insts_1[1:0]; // @[Frontend.scala:245:29, :256:32]
wire [1:0] _valid_T_6 = f2_fetch_bundle_insts_1[1:0]; // @[Frontend.scala:245:29, :256:32]
wire _f2_npc_plus4_mask_1_T_1 = _f2_npc_plus4_mask_1_T != 2'h3; // @[Frontend.scala:256:{32,38}]
assign _f2_npc_plus4_mask_1_T_2 = ~_f2_npc_plus4_mask_1_T_1; // @[Frontend.scala:256:38, :275:29]
assign f2_npc_plus4_mask_1 = _f2_npc_plus4_mask_1_T_2; // @[Frontend.scala:210:31, :275:29]
wire _redir_br_T_8 = _redir_br_T_7 == 7'h63; // @[Frontend.scala:262:{39,45}]
wire _redir_br_T_10 = s2_btb_resp_valid & _redir_br_T_9; // @[Frontend.scala:195:28, :279:{27,53}]
wire _redir_br_T_11 = _redir_br_T_10 & s2_btb_resp_bits_taken; // @[Frontend.scala:195:28, :279:{27,61}]
wire _redir_br_T_13 = _redir_br_T_11 & _redir_br_T_12; // @[Frontend.scala:279:{61,87}]
wire redir_br_1 = _redir_br_T_8 & _redir_br_T_13; // @[Frontend.scala:262:45, :278:56, :279:87]
wire _redir_T_7 = _redir_T_6 == 7'h67; // @[Frontend.scala:258:{40,46}]
wire _redir_T_9 = _redir_T_8 == 7'h6F; // @[Frontend.scala:259:{40,46}]
wire _redir_T_10 = _redir_T_7 | _redir_T_9; // @[Frontend.scala:258:46, :259:46, :280:74]
wire _redir_T_11 = _redir_T_10 | redir_br_1; // @[Frontend.scala:278:56, :280:{74,114}]
wire redir_1 = f2_inst_mask_1 & _redir_T_11; // @[Frontend.scala:205:27, :280:{33,114}]
wire _T_20 = redir | redir_1; // @[Frontend.scala:280:33, :285:31]
assign inst = _icache_io_resp_bits[47:16]; // @[Frontend.scala:58:26, :301:29]
assign f2_fetch_bundle_insts_1 = inst; // @[Frontend.scala:245:29, :301:29]
assign expanded_2 = _expanded_rvc_exp_2_io_rvc ? _expanded_rvc_exp_2_io_out_bits : inst; // @[Frontend.scala:301:29]
assign f2_fetch_bundle_exp_insts_1 = expanded_2; // @[Frontend.scala:245:29]
wire _valid_T_1 = _valid_T != 2'h3; // @[Frontend.scala:256:{32,38}]
wire _valid_T_2 = ~_valid_T_1; // @[Frontend.scala:256:38, :305:58]
wire _valid_T_3 = f2_inst_mask_0 & _valid_T_2; // @[Frontend.scala:205:27, :305:{55,58}]
wire _valid_T_4 = ~_valid_T_3; // @[Frontend.scala:305:{35,55}]
assign _valid_T_5 = f2_prev_is_half | _valid_T_4; // @[Frontend.scala:243:32, :305:{32,35}]
assign valid_1 = _valid_T_5; // @[Frontend.scala:267:21, :305:32]
wire _valid_T_10; // @[Frontend.scala:317:16]
wire valid_2; // @[Frontend.scala:267:21]
wire _f2_inst_mask_2_T = f2_fetch_mask[2]; // @[Frontend.scala:25:37, :268:49]
wire _f2_inst_mask_2_T_1 = s2_valid & _f2_inst_mask_2_T; // @[Frontend.scala:186:25, :268:{33,49}]
wire _f2_inst_mask_2_T_2 = _f2_inst_mask_2_T_1 & valid_2; // @[Frontend.scala:267:21, :268:{33,53}]
wire _f2_inst_mask_2_T_3 = ~_T_20; // @[Frontend.scala:268:65, :285:31]
assign _f2_inst_mask_2_T_4 = _f2_inst_mask_2_T_2 & _f2_inst_mask_2_T_3; // @[Frontend.scala:268:{53,62,65}]
assign f2_inst_mask_2 = _f2_inst_mask_2_T_4; // @[Frontend.scala:205:27, :268:62]
wire [40:0] _f2_fetch_bundle_pcs_2_T = _f2_fetch_bundle_pcs_0_T + 41'h4; // @[Frontend.scala:269:45]
wire [39:0] _f2_fetch_bundle_pcs_2_T_1 = _f2_fetch_bundle_pcs_2_T[39:0]; // @[Frontend.scala:269:45]
wire [40:0] _f2_fetch_bundle_pcs_2_T_4 = {1'h0, _f2_fetch_bundle_pcs_2_T_1}; // @[Frontend.scala:269:{45,58}]
assign _f2_fetch_bundle_pcs_2_T_5 = _f2_fetch_bundle_pcs_2_T_4[39:0]; // @[Frontend.scala:269:58]
assign f2_fetch_bundle_pcs_2 = _f2_fetch_bundle_pcs_2_T_5; // @[Frontend.scala:245:29, :269:58]
wire _redir_br_T_16 = s2_btb_resp_bits_bridx == 2'h2; // @[Frontend.scala:195:28, :270:65, :279:53]
wire [6:0] _f2_call_mask_2_T = f2_fetch_bundle_exp_insts_2[6:0]; // @[Frontend.scala:245:29, :258:40]
wire [6:0] _f2_call_mask_2_T_2 = f2_fetch_bundle_exp_insts_2[6:0]; // @[Frontend.scala:245:29, :258:40, :259:40]
wire [6:0] _f2_ret_mask_2_T = f2_fetch_bundle_exp_insts_2[6:0]; // @[Frontend.scala:245:29, :258:40]
wire [6:0] _redir_br_T_14 = f2_fetch_bundle_exp_insts_2[6:0]; // @[Frontend.scala:245:29, :258:40, :262:39]
wire [6:0] _redir_T_12 = f2_fetch_bundle_exp_insts_2[6:0]; // @[Frontend.scala:245:29, :258:40]
wire [6:0] _redir_T_14 = f2_fetch_bundle_exp_insts_2[6:0]; // @[Frontend.scala:245:29, :258:40, :259:40]
wire _f2_call_mask_2_T_1 = _f2_call_mask_2_T == 7'h67; // @[Frontend.scala:258:{40,46}]
wire _f2_call_mask_2_T_3 = _f2_call_mask_2_T_2 == 7'h6F; // @[Frontend.scala:259:{40,46}]
wire _f2_call_mask_2_T_4 = _f2_call_mask_2_T_1 | _f2_call_mask_2_T_3; // @[Frontend.scala:258:46, :259:46, :260:50]
wire _f2_call_mask_2_T_5 = f2_fetch_bundle_exp_insts_2[7]; // @[Frontend.scala:245:29, :260:82]
wire _f2_ret_mask_2_T_2 = f2_fetch_bundle_exp_insts_2[7]; // @[Frontend.scala:245:29, :260:82, :261:61]
assign _f2_call_mask_2_T_6 = _f2_call_mask_2_T_4 & _f2_call_mask_2_T_5; // @[Frontend.scala:260:{50,71,82}]
assign f2_call_mask_2 = _f2_call_mask_2_T_6; // @[Frontend.scala:206:27, :260:71]
wire _f2_ret_mask_2_T_1 = _f2_ret_mask_2_T == 7'h67; // @[Frontend.scala:258:{40,46}]
wire _f2_ret_mask_2_T_3 = ~_f2_ret_mask_2_T_2; // @[Frontend.scala:261:{52,61}]
wire _f2_ret_mask_2_T_4 = _f2_ret_mask_2_T_1 & _f2_ret_mask_2_T_3; // @[Frontend.scala:258:46, :261:{49,52}]
wire [4:0] _f2_ret_mask_2_T_5 = f2_fetch_bundle_exp_insts_2[19:15]; // @[Frontend.scala:245:29, :261:97]
wire [4:0] _f2_ret_mask_2_T_6 = _f2_ret_mask_2_T_5 & 5'h1B; // @[Frontend.scala:261:{85,97}]
wire _f2_ret_mask_2_T_7 = _f2_ret_mask_2_T_6 == 5'h1; // @[Frontend.scala:261:85]
assign _f2_ret_mask_2_T_8 = _f2_ret_mask_2_T_4 & _f2_ret_mask_2_T_7; // @[Frontend.scala:261:{49,65,85}]
assign f2_ret_mask_2 = _f2_ret_mask_2_T_8; // @[Frontend.scala:207:27, :261:65]
wire [1:0] _f2_npc_plus4_mask_2_T = f2_fetch_bundle_insts_2[1:0]; // @[Frontend.scala:245:29, :256:32]
wire [1:0] _valid_T_11 = f2_fetch_bundle_insts_2[1:0]; // @[Frontend.scala:245:29, :256:32]
wire [1:0] _f2_fetch_bundle_end_half_valid_T = f2_fetch_bundle_insts_2[1:0]; // @[Frontend.scala:245:29, :256:32]
wire _f2_npc_plus4_mask_2_T_1 = _f2_npc_plus4_mask_2_T != 2'h3; // @[Frontend.scala:256:{32,38}]
assign _f2_npc_plus4_mask_2_T_2 = ~_f2_npc_plus4_mask_2_T_1; // @[Frontend.scala:256:38, :275:29]
assign f2_npc_plus4_mask_2 = _f2_npc_plus4_mask_2_T_2; // @[Frontend.scala:210:31, :275:29]
wire _redir_br_T_15 = _redir_br_T_14 == 7'h63; // @[Frontend.scala:262:{39,45}]
wire _redir_br_T_17 = s2_btb_resp_valid & _redir_br_T_16; // @[Frontend.scala:195:28, :279:{27,53}]
wire _redir_br_T_18 = _redir_br_T_17 & s2_btb_resp_bits_taken; // @[Frontend.scala:195:28, :279:{27,61}]
wire _redir_br_T_20 = _redir_br_T_18 & _redir_br_T_19; // @[Frontend.scala:279:{61,87}]
wire redir_br_2 = _redir_br_T_15 & _redir_br_T_20; // @[Frontend.scala:262:45, :278:56, :279:87]
wire _redir_T_13 = _redir_T_12 == 7'h67; // @[Frontend.scala:258:{40,46}]
wire _redir_T_15 = _redir_T_14 == 7'h6F; // @[Frontend.scala:259:{40,46}]
wire _redir_T_16 = _redir_T_13 | _redir_T_15; // @[Frontend.scala:258:46, :259:46, :280:74]
wire _redir_T_17 = _redir_T_16 | redir_br_2; // @[Frontend.scala:278:56, :280:{74,114}]
wire redir_2 = f2_inst_mask_2 & _redir_T_17; // @[Frontend.scala:205:27, :280:{33,114}]
assign inst_1 = _icache_io_resp_bits[63:32]; // @[Frontend.scala:58:26, :313:29]
assign f2_fetch_bundle_insts_2 = inst_1; // @[Frontend.scala:245:29, :313:29]
assign expanded_3 = _expanded_rvc_exp_3_io_rvc ? _expanded_rvc_exp_3_io_out_bits : inst_1; // @[Frontend.scala:313:29]
assign f2_fetch_bundle_exp_insts_2 = expanded_3; // @[Frontend.scala:245:29]
wire _valid_T_7 = _valid_T_6 != 2'h3; // @[Frontend.scala:256:{32,38}]
wire _valid_T_8 = ~_valid_T_7; // @[Frontend.scala:256:38, :317:39]
wire _valid_T_9 = f2_inst_mask_1 & _valid_T_8; // @[Frontend.scala:205:27, :317:{36,39}]
assign _valid_T_10 = ~_valid_T_9; // @[Frontend.scala:317:{16,36}]
assign valid_2 = _valid_T_10; // @[Frontend.scala:267:21, :317:16]
wire _valid_T_19; // @[Frontend.scala:311:16]
wire valid_3; // @[Frontend.scala:267:21]
wire _f2_inst_mask_3_T = f2_fetch_mask[3]; // @[Frontend.scala:25:37, :268:49]
wire _f2_inst_mask_3_T_1 = s2_valid & _f2_inst_mask_3_T; // @[Frontend.scala:186:25, :268:{33,49}]
wire _f2_inst_mask_3_T_2 = _f2_inst_mask_3_T_1 & valid_3; // @[Frontend.scala:267:21, :268:{33,53}]
wire _f2_inst_mask_3_T_3 = ~(_T_20 | redir_2); // @[Frontend.scala:268:65, :280:33, :285:31]
assign _f2_inst_mask_3_T_4 = _f2_inst_mask_3_T_2 & _f2_inst_mask_3_T_3; // @[Frontend.scala:268:{53,62,65}]
assign f2_inst_mask_3 = _f2_inst_mask_3_T_4; // @[Frontend.scala:205:27, :268:62]
wire [40:0] _f2_fetch_bundle_pcs_3_T = _f2_fetch_bundle_pcs_0_T + 41'h6; // @[Frontend.scala:269:45]
wire [39:0] _f2_fetch_bundle_pcs_3_T_1 = _f2_fetch_bundle_pcs_3_T[39:0]; // @[Frontend.scala:269:45]
wire [40:0] _f2_fetch_bundle_pcs_3_T_4 = {1'h0, _f2_fetch_bundle_pcs_3_T_1}; // @[Frontend.scala:269:{45,58}]
assign _f2_fetch_bundle_pcs_3_T_5 = _f2_fetch_bundle_pcs_3_T_4[39:0]; // @[Frontend.scala:269:58]
assign f2_fetch_bundle_pcs_3 = _f2_fetch_bundle_pcs_3_T_5; // @[Frontend.scala:245:29, :269:58]
wire [6:0] _f2_call_mask_3_T = f2_fetch_bundle_exp_insts_3[6:0]; // @[Frontend.scala:245:29, :258:40]
wire [6:0] _f2_call_mask_3_T_2 = f2_fetch_bundle_exp_insts_3[6:0]; // @[Frontend.scala:245:29, :258:40, :259:40]
wire [6:0] _f2_ret_mask_3_T = f2_fetch_bundle_exp_insts_3[6:0]; // @[Frontend.scala:245:29, :258:40]
wire [6:0] _redir_br_T_21 = f2_fetch_bundle_exp_insts_3[6:0]; // @[Frontend.scala:245:29, :258:40, :262:39]
wire [6:0] _redir_T_18 = f2_fetch_bundle_exp_insts_3[6:0]; // @[Frontend.scala:245:29, :258:40]
wire [6:0] _redir_T_20 = f2_fetch_bundle_exp_insts_3[6:0]; // @[Frontend.scala:245:29, :258:40, :259:40]
wire _f2_call_mask_3_T_1 = _f2_call_mask_3_T == 7'h67; // @[Frontend.scala:258:{40,46}]
wire _f2_call_mask_3_T_3 = _f2_call_mask_3_T_2 == 7'h6F; // @[Frontend.scala:259:{40,46}]
wire _f2_call_mask_3_T_4 = _f2_call_mask_3_T_1 | _f2_call_mask_3_T_3; // @[Frontend.scala:258:46, :259:46, :260:50]
wire _f2_call_mask_3_T_5 = f2_fetch_bundle_exp_insts_3[7]; // @[Frontend.scala:245:29, :260:82]
wire _f2_ret_mask_3_T_2 = f2_fetch_bundle_exp_insts_3[7]; // @[Frontend.scala:245:29, :260:82, :261:61]
assign _f2_call_mask_3_T_6 = _f2_call_mask_3_T_4 & _f2_call_mask_3_T_5; // @[Frontend.scala:260:{50,71,82}]
assign f2_call_mask_3 = _f2_call_mask_3_T_6; // @[Frontend.scala:206:27, :260:71]
wire _f2_ret_mask_3_T_1 = _f2_ret_mask_3_T == 7'h67; // @[Frontend.scala:258:{40,46}]
wire _f2_ret_mask_3_T_3 = ~_f2_ret_mask_3_T_2; // @[Frontend.scala:261:{52,61}]
wire _f2_ret_mask_3_T_4 = _f2_ret_mask_3_T_1 & _f2_ret_mask_3_T_3; // @[Frontend.scala:258:46, :261:{49,52}]
wire [4:0] _f2_ret_mask_3_T_5 = f2_fetch_bundle_exp_insts_3[19:15]; // @[Frontend.scala:245:29, :261:97]
wire [4:0] _f2_ret_mask_3_T_6 = _f2_ret_mask_3_T_5 & 5'h1B; // @[Frontend.scala:261:{85,97}]
wire _f2_ret_mask_3_T_7 = _f2_ret_mask_3_T_6 == 5'h1; // @[Frontend.scala:261:85]
assign _f2_ret_mask_3_T_8 = _f2_ret_mask_3_T_4 & _f2_ret_mask_3_T_7; // @[Frontend.scala:261:{49,65,85}]
assign f2_ret_mask_3 = _f2_ret_mask_3_T_8; // @[Frontend.scala:207:27, :261:65]
wire [1:0] _f2_npc_plus4_mask_3_T = f2_fetch_bundle_insts_3[1:0]; // @[Frontend.scala:245:29, :256:32]
wire _f2_npc_plus4_mask_3_T_1 = _f2_npc_plus4_mask_3_T != 2'h3; // @[Frontend.scala:256:{32,38}]
assign _f2_npc_plus4_mask_3_T_2 = ~_f2_npc_plus4_mask_3_T_1; // @[Frontend.scala:256:38, :275:29]
assign f2_npc_plus4_mask_3 = _f2_npc_plus4_mask_3_T_2; // @[Frontend.scala:210:31, :275:29]
wire _redir_br_T_22 = _redir_br_T_21 == 7'h63; // @[Frontend.scala:262:{39,45}]
wire _redir_br_T_23 = &s2_btb_resp_bits_bridx; // @[Frontend.scala:195:28, :270:65, :279:53]
wire _redir_br_T_24 = s2_btb_resp_valid & _redir_br_T_23; // @[Frontend.scala:195:28, :279:{27,53}]
wire _redir_br_T_25 = _redir_br_T_24 & s2_btb_resp_bits_taken; // @[Frontend.scala:195:28, :279:{27,61}]
wire _redir_br_T_27 = _redir_br_T_25 & _redir_br_T_26; // @[Frontend.scala:279:{61,87}]
wire redir_br_3 = _redir_br_T_22 & _redir_br_T_27; // @[Frontend.scala:262:45, :278:56, :279:87]
wire _redir_T_19 = _redir_T_18 == 7'h67; // @[Frontend.scala:258:{40,46}]
wire _redir_T_21 = _redir_T_20 == 7'h6F; // @[Frontend.scala:259:{40,46}]
wire _redir_T_22 = _redir_T_19 | _redir_T_21; // @[Frontend.scala:258:46, :259:46, :280:74]
wire _redir_T_23 = _redir_T_22 | redir_br_3; // @[Frontend.scala:278:56, :280:{74,114}]
wire redir_3 = f2_inst_mask_3 & _redir_T_23; // @[Frontend.scala:205:27, :280:{33,114}]
assign f2_do_redirect = redir_3 | redir_2 | redir_1 | redir; // @[Frontend.scala:212:32, :280:33, :281:18, :282:22]
assign f2_redirect_bridx = redir_3 ? 2'h3 : redir_2 ? 2'h2 : {1'h0, redir_1}; // @[Frontend.scala:213:35, :280:33, :281:18, :283:25]
wire [15:0] _inst_T = _icache_io_resp_bits[63:48]; // @[Frontend.scala:58:26, :307:44]
assign inst_2 = {16'h0, _inst_T}; // @[Frontend.scala:307:{21,44}]
assign f2_fetch_bundle_insts_3 = inst_2; // @[Frontend.scala:245:29, :307:21]
assign expanded_4 = _expanded_rvc_exp_4_io_rvc ? _expanded_rvc_exp_4_io_out_bits : inst_2; // @[Frontend.scala:307:21]
assign f2_fetch_bundle_exp_insts_3 = expanded_4; // @[Frontend.scala:245:29]
wire _valid_T_12 = _valid_T_11 != 2'h3; // @[Frontend.scala:256:{32,38}]
wire _valid_T_13 = ~_valid_T_12; // @[Frontend.scala:256:38, :311:40]
wire _valid_T_14 = f2_inst_mask_2 & _valid_T_13; // @[Frontend.scala:205:27, :311:{37,40}]
wire [1:0] _valid_T_15 = inst_2[1:0]; // @[Frontend.scala:256:32, :307:21]
wire _valid_T_16 = _valid_T_15 != 2'h3; // @[Frontend.scala:256:{32,38}]
wire _valid_T_17 = ~_valid_T_16; // @[Frontend.scala:256:38, :311:79]
wire _valid_T_18 = _valid_T_14 | _valid_T_17; // @[Frontend.scala:311:{37,76,79}]
assign _valid_T_19 = ~_valid_T_18; // @[Frontend.scala:311:{16,76}]
assign valid_3 = _valid_T_19; // @[Frontend.scala:267:21, :311:16]
assign last_inst = f2_fetch_bundle_insts_3[15:0]; // @[Frontend.scala:245:29, :320:54]
assign f2_fetch_bundle_end_half_bits = last_inst; // @[Frontend.scala:245:29, :320:54]
wire _f2_fetch_bundle_end_half_valid_T_1 = _f2_fetch_bundle_end_half_valid_T != 2'h3; // @[Frontend.scala:256:{32,38}]
wire _f2_fetch_bundle_end_half_valid_T_2 = ~_f2_fetch_bundle_end_half_valid_T_1; // @[Frontend.scala:256:38, :321:70]
wire _f2_fetch_bundle_end_half_valid_T_3 = f2_inst_mask_2 & _f2_fetch_bundle_end_half_valid_T_2; // @[Frontend.scala:205:27, :321:{67,70}]
wire _f2_fetch_bundle_end_half_valid_T_4 = ~_f2_fetch_bundle_end_half_valid_T_3; // @[Frontend.scala:321:{38,67}]
wire [1:0] _f2_fetch_bundle_end_half_valid_T_5 = last_inst[1:0]; // @[Frontend.scala:256:32, :320:54]
wire _f2_fetch_bundle_end_half_valid_T_6 = _f2_fetch_bundle_end_half_valid_T_5 != 2'h3; // @[Frontend.scala:256:{32,38}]
wire _f2_fetch_bundle_end_half_valid_T_7 = ~_f2_fetch_bundle_end_half_valid_T_6; // @[Frontend.scala:256:38, :321:118]
assign _f2_fetch_bundle_end_half_valid_T_8 = _f2_fetch_bundle_end_half_valid_T_4 & _f2_fetch_bundle_end_half_valid_T_7; // @[Frontend.scala:321:{38,115,118}]
assign f2_fetch_bundle_end_half_valid = _f2_fetch_bundle_end_half_valid_T_8; // @[Frontend.scala:245:29, :321:115]
wire _s0_is_replay_T = s2_valid & _icache_io_resp_valid; // @[Frontend.scala:58:26, :186:25, :326:19, :330:30]
wire _T_36 = s2_valid & ~_icache_io_resp_valid | _s0_is_replay_T & ~f3_ready; // @[Frontend.scala:58:26, :186:25, :196:22, :325:{19,22,45}, :326:{43,46}, :330:30]
wire _s0_valid_T = ~s2_tlb_resp_ae_inst; // @[Frontend.scala:191:28, :327:18]
wire _s0_valid_T_1 = ~s2_tlb_resp_pf_inst; // @[Frontend.scala:191:28, :327:42]
wire _s0_valid_T_2 = _s0_valid_T & _s0_valid_T_1; // @[Frontend.scala:327:{18,39,42}]
wire _s0_valid_T_3 = _s0_valid_T_2 | s2_is_replay; // @[Frontend.scala:193:44, :327:{39,64}]
wire _s0_valid_T_4 = _s0_valid_T_3 | s2_tlb_miss; // @[Frontend.scala:192:28, :327:{64,80}]
wire _s0_valid_T_5 = ~f3_ready; // @[Frontend.scala:196:22, :326:46, :327:98]
wire _s0_valid_T_6 = _s0_valid_T_4 | _s0_valid_T_5; // @[Frontend.scala:327:{80,95,98}]
wire _T_37 = s2_valid & f3_ready; // @[Frontend.scala:186:25, :196:22, :332:25]
wire _f2_prev_is_half_T = ~f2_do_redirect; // @[Frontend.scala:212:32, :333:58]
wire _f2_prev_is_half_T_1 = f2_fetch_bundle_end_half_valid & _f2_prev_is_half_T; // @[Frontend.scala:245:29, :333:{55,58}]
wire _T_41 = s1_valid & s1_vpc != f2_predicted_target | ~s1_valid; // @[Frontend.scala:135:29, :137:29, :214:32, :335:{21,32,58,61}]
wire _GEN_6 = _T_37 & _T_41; // @[Frontend.scala:139:30, :332:{25,38}, :335:{58,72}]
wire _s0_valid_T_8 = ~s2_is_replay; // @[Frontend.scala:193:44, :194:77, :338:73]
wire _s0_valid_T_9 = _s0_valid_T_7 & _s0_valid_T_8; // @[Frontend.scala:338:{46,70,73}]
wire _s0_valid_T_10 = ~_s0_valid_T_9; // @[Frontend.scala:338:{23,70}]
wire _GEN_7 = _T_37 & _T_41; // @[Frontend.scala:171:19, :332:{25,38}, :335:{58,72}, :338:20]
wire _fb_io_enq_valid_T = ~f2_clear; // @[Frontend.scala:190:26, :348:35]
wire _fb_io_enq_valid_T_1 = s2_valid & _fb_io_enq_valid_T; // @[Frontend.scala:186:25, :348:{32,35}]
wire _fb_io_enq_valid_T_3 = ~s2_tlb_miss; // @[Frontend.scala:192:28, :349:79]
wire _fb_io_enq_valid_T_4 = _fb_io_enq_valid_T_2 & _fb_io_enq_valid_T_3; // @[Frontend.scala:349:{52,76,79}]
wire _fb_io_enq_valid_T_5 = _icache_io_resp_valid | _fb_io_enq_valid_T_4; // @[Frontend.scala:58:26, :349:{27,76}]
wire _fb_io_enq_valid_T_6 = _fb_io_enq_valid_T_1 & _fb_io_enq_valid_T_5; // @[Frontend.scala:348:{32,45}, :349:27]
assign s0_is_replay = ~io_cpu_redirect_flush_0 & _T_36 & _s0_is_replay_T; // @[Frontend.scala:93:7, :124:30, :325:45, :326:58, :330:{18,30}, :332:38, :357:32, :366:18]
reg jump_to_reset; // @[Frontend.scala:369:30]
assign s0_valid = jump_to_reset | (io_cpu_redirect_flush_0 ? io_cpu_redirect_val_0 : _T_36 ? _s0_valid_T_6 : _GEN_7 ? _s0_valid_T_10 : s1_valid); // @[Frontend.scala:93:7, :122:26, :137:29, :171:19, :325:45, :326:58, :327:{14,95}, :332:38, :335:72, :338:{20,23}, :357:32, :363:18, :369:30, :371:24, :372:14]
assign s0_vpc = jump_to_reset ? 40'h10000 : io_cpu_redirect_flush_0 ? io_cpu_redirect_pc_0 : _T_36 ? s2_vpc : _GEN_7 ? f2_predicted_target : s1_valid ? f1_predicted_target : 40'h0; // @[Frontend.scala:93:7, :121:24, :137:29, :167:32, :171:19, :174:18, :187:25, :214:32, :325:45, :326:58, :328:14, :332:38, :335:72, :338:20, :339:20, :357:32, :364:18, :369:30, :371:24, :373:14]
assign s0_ras_head = jump_to_reset ? 3'h5 : io_cpu_redirect_flush_0 ? io_cpu_redirect_ras_head_0 : _T_36 ? s2_ras_head : _GEN_6 | _T_3 ? ras_next_head : s1_valid ? s1_ras_head : 3'h0; // @[Frontend.scala:93:7, :123:29, :136:30, :137:29, :139:30, :171:19, :176:18, :189:28, :222:26, :224:{35,47,59,84}, :225:17, :325:45, :326:58, :329:17, :332:38, :335:72, :340:20, :357:32, :365:18, :369:30, :371:24, :374:17]
assign f2_clear = jump_to_reset | io_cpu_redirect_flush_0; // @[Frontend.scala:93:7, :190:26, :357:32, :369:30, :371:24, :375:17]
assign f1_clear = jump_to_reset | io_cpu_redirect_flush_0 | _T_36 | _GEN_6; // @[Frontend.scala:93:7, :139:30, :325:45, :326:58, :331:14, :332:38, :335:72, :357:32, :361:17, :369:30, :371:24, :378:17]
wire _T_8 = io_cpu_ras_update_valid_0 | REG & ~io_cpu_redirect_val_0; // @[Frontend.scala:93:7, :234:{33,44,62,84}]
wire _GEN_8 = _T_36 | ~_T_37; // @[Frontend.scala:243:32, :325:45, :326:58, :332:{25,38}]
always @(posedge clock) begin // @[Frontend.scala:93:7]
if (_T_8 & idx == 3'h0) // @[Frontend.scala:110:16, :234:{33,111}, :235:18, :237:14]
ras_0 <= addr; // @[Frontend.scala:110:16, :236:19]
if (_T_8 & idx == 3'h1) // @[Frontend.scala:110:16, :234:{33,111}, :235:18, :237:14]
ras_1 <= addr; // @[Frontend.scala:110:16, :236:19]
if (_T_8 & idx == 3'h2) // @[Frontend.scala:110:16, :234:{33,111}, :235:18, :237:14]
ras_2 <= addr; // @[Frontend.scala:110:16, :236:19]
if (_T_8 & idx == 3'h3) // @[Frontend.scala:110:16, :234:{33,111}, :235:18, :237:14]
ras_3 <= addr; // @[Frontend.scala:110:16, :236:19]
if (_T_8 & idx == 3'h4) // @[Frontend.scala:110:16, :234:{33,111}, :235:18, :237:14]
ras_4 <= addr; // @[Frontend.scala:110:16, :236:19]
if (_T_8 & idx == 3'h5) // @[Frontend.scala:110:16, :234:{33,111}, :235:18, :237:14]
ras_5 <= addr; // @[Frontend.scala:110:16, :236:19]
s1_vpc <= s0_vpc; // @[Frontend.scala:121:24, :135:29]
s1_ras_head_REG <= s0_ras_head; // @[Frontend.scala:123:29, :136:38]
s1_is_replay <= s0_is_replay; // @[Frontend.scala:124:30, :138:29]
s1_tlb_resp_REG_miss <= s0_replay_resp_miss; // @[Frontend.scala:125:28, :157:46]
s1_tlb_resp_REG_paddr <= s0_replay_resp_paddr; // @[Frontend.scala:125:28, :157:46]
s1_tlb_resp_REG_gpa <= s0_replay_resp_gpa; // @[Frontend.scala:125:28, :157:46]
s1_tlb_resp_REG_gpa_is_pte <= s0_replay_resp_gpa_is_pte; // @[Frontend.scala:125:28, :157:46]
s1_tlb_resp_REG_pf_ld <= s0_replay_resp_pf_ld; // @[Frontend.scala:125:28, :157:46]
s1_tlb_resp_REG_pf_st <= s0_replay_resp_pf_st; // @[Frontend.scala:125:28, :157:46]
s1_tlb_resp_REG_pf_inst <= s0_replay_resp_pf_inst; // @[Frontend.scala:125:28, :157:46]
s1_tlb_resp_REG_gf_ld <= s0_replay_resp_gf_ld; // @[Frontend.scala:125:28, :157:46]
s1_tlb_resp_REG_gf_st <= s0_replay_resp_gf_st; // @[Frontend.scala:125:28, :157:46]
s1_tlb_resp_REG_gf_inst <= s0_replay_resp_gf_inst; // @[Frontend.scala:125:28, :157:46]
s1_tlb_resp_REG_ae_ld <= s0_replay_resp_ae_ld; // @[Frontend.scala:125:28, :157:46]
s1_tlb_resp_REG_ae_st <= s0_replay_resp_ae_st; // @[Frontend.scala:125:28, :157:46]
s1_tlb_resp_REG_ae_inst <= s0_replay_resp_ae_inst; // @[Frontend.scala:125:28, :157:46]
s1_tlb_resp_REG_ma_ld <= s0_replay_resp_ma_ld; // @[Frontend.scala:125:28, :157:46]
s1_tlb_resp_REG_ma_st <= s0_replay_resp_ma_st; // @[Frontend.scala:125:28, :157:46]
s1_tlb_resp_REG_ma_inst <= s0_replay_resp_ma_inst; // @[Frontend.scala:125:28, :157:46]
s1_tlb_resp_REG_cacheable <= s0_replay_resp_cacheable; // @[Frontend.scala:125:28, :157:46]
s1_tlb_resp_REG_must_alloc <= s0_replay_resp_must_alloc; // @[Frontend.scala:125:28, :157:46]
s1_tlb_resp_REG_prefetchable <= s0_replay_resp_prefetchable; // @[Frontend.scala:125:28, :157:46]
s1_tlb_resp_REG_size <= s0_replay_resp_size; // @[Frontend.scala:125:28, :157:46]
s1_tlb_resp_REG_cmd <= s0_replay_resp_cmd; // @[Frontend.scala:125:28, :157:46]
s1_ppc_REG <= s0_replay_ppc; // @[Frontend.scala:126:27, :158:42]
s2_vpc <= s1_vpc; // @[Frontend.scala:135:29, :187:25]
s2_ppc <= s1_ppc; // @[Frontend.scala:158:20, :188:24]
s2_ras_head <= s1_ras_head; // @[Frontend.scala:136:30, :189:28]
s2_tlb_resp_miss <= s1_tlb_resp_miss; // @[Frontend.scala:157:24, :191:28]
s2_tlb_resp_paddr <= s1_tlb_resp_paddr; // @[Frontend.scala:157:24, :191:28]
s2_tlb_resp_gpa <= s1_tlb_resp_gpa; // @[Frontend.scala:157:24, :191:28]
s2_tlb_resp_gpa_is_pte <= s1_tlb_resp_gpa_is_pte; // @[Frontend.scala:157:24, :191:28]
s2_tlb_resp_pf_ld <= s1_tlb_resp_pf_ld; // @[Frontend.scala:157:24, :191:28]
s2_tlb_resp_pf_st <= s1_tlb_resp_pf_st; // @[Frontend.scala:157:24, :191:28]
s2_tlb_resp_pf_inst <= s1_tlb_resp_pf_inst; // @[Frontend.scala:157:24, :191:28]
s2_tlb_resp_gf_ld <= s1_tlb_resp_gf_ld; // @[Frontend.scala:157:24, :191:28]
s2_tlb_resp_gf_st <= s1_tlb_resp_gf_st; // @[Frontend.scala:157:24, :191:28]
s2_tlb_resp_gf_inst <= s1_tlb_resp_gf_inst; // @[Frontend.scala:157:24, :191:28]
s2_tlb_resp_ae_ld <= s1_tlb_resp_ae_ld; // @[Frontend.scala:157:24, :191:28]
s2_tlb_resp_ae_st <= s1_tlb_resp_ae_st; // @[Frontend.scala:157:24, :191:28]
s2_tlb_resp_ae_inst <= s1_tlb_resp_ae_inst; // @[Frontend.scala:157:24, :191:28]
s2_tlb_resp_ma_ld <= s1_tlb_resp_ma_ld; // @[Frontend.scala:157:24, :191:28]
s2_tlb_resp_ma_st <= s1_tlb_resp_ma_st; // @[Frontend.scala:157:24, :191:28]
s2_tlb_resp_ma_inst <= s1_tlb_resp_ma_inst; // @[Frontend.scala:157:24, :191:28]
s2_tlb_resp_cacheable <= s1_tlb_resp_cacheable; // @[Frontend.scala:157:24, :191:28]
s2_tlb_resp_must_alloc <= s1_tlb_resp_must_alloc; // @[Frontend.scala:157:24, :191:28]
s2_tlb_resp_prefetchable <= s1_tlb_resp_prefetchable; // @[Frontend.scala:157:24, :191:28]
s2_tlb_resp_size <= s1_tlb_resp_size; // @[Frontend.scala:157:24, :191:28]
s2_tlb_resp_cmd <= s1_tlb_resp_cmd; // @[Frontend.scala:157:24, :191:28]
s2_tlb_miss <= s1_tlb_miss; // @[Frontend.scala:156:35, :192:28]
s2_is_replay_REG <= s1_is_replay; // @[Frontend.scala:138:29, :193:29]
s2_btb_resp_valid <= _btb_io_resp_valid; // @[Frontend.scala:109:19, :195:28]
s2_btb_resp_bits_cfiType <= _btb_io_resp_bits_cfiType; // @[Frontend.scala:109:19, :195:28]
s2_btb_resp_bits_taken <= _btb_io_resp_bits_taken; // @[Frontend.scala:109:19, :195:28]
s2_btb_resp_bits_mask <= _btb_io_resp_bits_mask; // @[Frontend.scala:109:19, :195:28]
s2_btb_resp_bits_bridx <= _btb_io_resp_bits_bridx; // @[Frontend.scala:109:19, :195:28]
s2_btb_resp_bits_target <= _btb_io_resp_bits_target; // @[Frontend.scala:109:19, :195:28]
s2_btb_resp_bits_entry <= _btb_io_resp_bits_entry; // @[Frontend.scala:109:19, :195:28]
s2_btb_resp_bits_bht_history <= _btb_io_resp_bits_bht_history; // @[Frontend.scala:109:19, :195:28]
s2_btb_resp_bits_bht_value <= _btb_io_resp_bits_bht_value; // @[Frontend.scala:109:19, :195:28]
f2_next_fetch <= f1_next_fetch; // @[Frontend.scala:22:48, :201:30]
f2_predicted_target_REG <= f1_predicted_target; // @[Frontend.scala:167:32, :215:45]
f2_predicted_target_REG_1 <= f1_next_fetch; // @[Frontend.scala:22:48, :216:12]
REG <= ras_write_val & ~io_cpu_redirect_val_0; // @[Frontend.scala:93:7, :219:31, :234:{44,59,62}]
idx_REG <= ras_write_idx; // @[Frontend.scala:220:31, :235:80]
addr_REG <= ras_write_addr; // @[Frontend.scala:221:32, :236:81]
if (_GEN_8) begin // @[Frontend.scala:241:25, :243:32, :326:58, :332:38]
end
else // @[Frontend.scala:241:25, :326:58, :332:38]
f2_prev_half <= f2_fetch_bundle_end_half_bits; // @[Frontend.scala:241:25, :245:29]
if (reset) begin // @[Frontend.scala:93:7]
s1_valid <= 1'h0; // @[Frontend.scala:137:29]
s2_valid <= 1'h0; // @[Frontend.scala:186:25]
f2_prev_is_half <= 1'h0; // @[Frontend.scala:243:32]
jump_to_reset <= 1'h1; // @[Frontend.scala:369:30]
end
else begin // @[Frontend.scala:93:7]
s1_valid <= s0_valid; // @[Frontend.scala:122:26, :137:29]
s2_valid <= _s2_valid_T_1; // @[Frontend.scala:186:{25,35}]
f2_prev_is_half <= ~(jump_to_reset | io_cpu_redirect_flush_0) & (_GEN_8 ? f2_prev_is_half : _f2_prev_is_half_T_1); // @[Frontend.scala:93:7, :243:32, :326:58, :332:38, :333:55, :357:32, :360:21, :369:30, :371:24, :377:21]
jump_to_reset <= 1'h0; // @[Frontend.scala:369:30]
end
always @(posedge)
ShuttleICache icache ( // @[Frontend.scala:58:26]
.clock (clock),
.reset (reset),
.auto_master_out_a_ready (auto_icache_master_out_a_ready_0), // @[Frontend.scala:93:7]
.auto_master_out_a_valid (auto_icache_master_out_a_valid_0),
.auto_master_out_a_bits_address (auto_icache_master_out_a_bits_address_0),
.auto_master_out_d_valid (auto_icache_master_out_d_valid_0), // @[Frontend.scala:93:7]
.auto_master_out_d_bits_opcode (auto_icache_master_out_d_bits_opcode_0), // @[Frontend.scala:93:7]
.auto_master_out_d_bits_param (auto_icache_master_out_d_bits_param_0), // @[Frontend.scala:93:7]
.auto_master_out_d_bits_size (auto_icache_master_out_d_bits_size_0), // @[Frontend.scala:93:7]
.auto_master_out_d_bits_source (auto_icache_master_out_d_bits_source_0), // @[Frontend.scala:93:7]
.auto_master_out_d_bits_sink (auto_icache_master_out_d_bits_sink_0), // @[Frontend.scala:93:7]
.auto_master_out_d_bits_denied (auto_icache_master_out_d_bits_denied_0), // @[Frontend.scala:93:7]
.auto_master_out_d_bits_data (auto_icache_master_out_d_bits_data_0), // @[Frontend.scala:93:7]
.auto_master_out_d_bits_corrupt (auto_icache_master_out_d_bits_corrupt_0), // @[Frontend.scala:93:7]
.io_req_valid (s0_valid), // @[Frontend.scala:122:26]
.io_req_bits (s0_vpc[38:0]), // @[Frontend.scala:121:24, :129:22]
.io_s1_kill (_icache_io_s1_kill_T), // @[Frontend.scala:161:42]
.io_s2_kill (s2_xcpt), // @[Frontend.scala:194:74]
.io_s1_paddr (s1_ppc), // @[Frontend.scala:158:20]
.io_invalidate (io_cpu_flush_icache_0), // @[Frontend.scala:93:7]
.io_resp_valid (_icache_io_resp_valid),
.io_resp_bits (_icache_io_resp_bits)
); // @[Frontend.scala:58:26]
ITLB tlb ( // @[Frontend.scala:107:19]
.clock (clock),
.reset (reset),
.io_req_valid (_tlb_io_req_valid_T_5), // @[Frontend.scala:141:68]
.io_req_bits_vaddr (_tlb_io_req_bits_vaddr_T), // @[Frontend.scala:143:31]
.io_req_bits_prv (io_ptw_status_prv_0), // @[Frontend.scala:93:7]
.io_req_bits_v (io_ptw_status_v_0), // @[Frontend.scala:93:7]
.io_resp_miss (_tlb_io_resp_miss),
.io_resp_paddr (_tlb_io_resp_paddr),
.io_resp_gpa (_tlb_io_resp_gpa),
.io_resp_pf_ld (_tlb_io_resp_pf_ld),
.io_resp_pf_inst (_tlb_io_resp_pf_inst),
.io_resp_ae_ld (_tlb_io_resp_ae_ld),
.io_resp_ae_inst (_tlb_io_resp_ae_inst),
.io_resp_ma_ld (_tlb_io_resp_ma_ld),
.io_resp_cacheable (_tlb_io_resp_cacheable),
.io_resp_prefetchable (_tlb_io_resp_prefetchable),
.io_sfence_valid (io_cpu_sfence_valid_0), // @[Frontend.scala:93:7]
.io_sfence_bits_rs1 (io_cpu_sfence_bits_rs1_0), // @[Frontend.scala:93:7]
.io_sfence_bits_rs2 (io_cpu_sfence_bits_rs2_0), // @[Frontend.scala:93:7]
.io_sfence_bits_addr (io_cpu_sfence_bits_addr_0), // @[Frontend.scala:93:7]
.io_sfence_bits_asid (io_cpu_sfence_bits_asid_0), // @[Frontend.scala:93:7]
.io_sfence_bits_hv (io_cpu_sfence_bits_hv_0), // @[Frontend.scala:93:7]
.io_sfence_bits_hg (io_cpu_sfence_bits_hg_0), // @[Frontend.scala:93:7]
.io_ptw_req_ready (io_ptw_req_ready_0), // @[Frontend.scala:93:7]
.io_ptw_req_valid (io_ptw_req_valid_0),
.io_ptw_req_bits_bits_addr (io_ptw_req_bits_bits_addr_0),
.io_ptw_req_bits_bits_need_gpa (io_ptw_req_bits_bits_need_gpa_0),
.io_ptw_resp_valid (io_ptw_resp_valid_0), // @[Frontend.scala:93:7]
.io_ptw_resp_bits_ae_ptw (io_ptw_resp_bits_ae_ptw_0), // @[Frontend.scala:93:7]
.io_ptw_resp_bits_ae_final (io_ptw_resp_bits_ae_final_0), // @[Frontend.scala:93:7]
.io_ptw_resp_bits_pf (io_ptw_resp_bits_pf_0), // @[Frontend.scala:93:7]
.io_ptw_resp_bits_gf (io_ptw_resp_bits_gf_0), // @[Frontend.scala:93:7]
.io_ptw_resp_bits_hr (io_ptw_resp_bits_hr_0), // @[Frontend.scala:93:7]
.io_ptw_resp_bits_hw (io_ptw_resp_bits_hw_0), // @[Frontend.scala:93:7]
.io_ptw_resp_bits_hx (io_ptw_resp_bits_hx_0), // @[Frontend.scala:93:7]
.io_ptw_resp_bits_pte_reserved_for_future (io_ptw_resp_bits_pte_reserved_for_future_0), // @[Frontend.scala:93:7]
.io_ptw_resp_bits_pte_ppn (io_ptw_resp_bits_pte_ppn_0), // @[Frontend.scala:93:7]
.io_ptw_resp_bits_pte_reserved_for_software (io_ptw_resp_bits_pte_reserved_for_software_0), // @[Frontend.scala:93:7]
.io_ptw_resp_bits_pte_d (io_ptw_resp_bits_pte_d_0), // @[Frontend.scala:93:7]
.io_ptw_resp_bits_pte_a (io_ptw_resp_bits_pte_a_0), // @[Frontend.scala:93:7]
.io_ptw_resp_bits_pte_g (io_ptw_resp_bits_pte_g_0), // @[Frontend.scala:93:7]
.io_ptw_resp_bits_pte_u (io_ptw_resp_bits_pte_u_0), // @[Frontend.scala:93:7]
.io_ptw_resp_bits_pte_x (io_ptw_resp_bits_pte_x_0), // @[Frontend.scala:93:7]
.io_ptw_resp_bits_pte_w (io_ptw_resp_bits_pte_w_0), // @[Frontend.scala:93:7]
.io_ptw_resp_bits_pte_r (io_ptw_resp_bits_pte_r_0), // @[Frontend.scala:93:7]
.io_ptw_resp_bits_pte_v (io_ptw_resp_bits_pte_v_0), // @[Frontend.scala:93:7]
.io_ptw_resp_bits_level (io_ptw_resp_bits_level_0), // @[Frontend.scala:93:7]
.io_ptw_resp_bits_homogeneous (io_ptw_resp_bits_homogeneous_0), // @[Frontend.scala:93:7]
.io_ptw_resp_bits_gpa_valid (io_ptw_resp_bits_gpa_valid_0), // @[Frontend.scala:93:7]
.io_ptw_resp_bits_gpa_bits (io_ptw_resp_bits_gpa_bits_0), // @[Frontend.scala:93:7]
.io_ptw_resp_bits_gpa_is_pte (io_ptw_resp_bits_gpa_is_pte_0), // @[Frontend.scala:93:7]
.io_ptw_ptbr_mode (io_ptw_ptbr_mode_0), // @[Frontend.scala:93:7]
.io_ptw_ptbr_ppn (io_ptw_ptbr_ppn_0), // @[Frontend.scala:93:7]
.io_ptw_status_debug (io_ptw_status_debug_0), // @[Frontend.scala:93:7]
.io_ptw_status_cease (io_ptw_status_cease_0), // @[Frontend.scala:93:7]
.io_ptw_status_wfi (io_ptw_status_wfi_0), // @[Frontend.scala:93:7]
.io_ptw_status_dprv (io_ptw_status_dprv_0), // @[Frontend.scala:93:7]
.io_ptw_status_dv (io_ptw_status_dv_0), // @[Frontend.scala:93:7]
.io_ptw_status_prv (io_ptw_status_prv_0), // @[Frontend.scala:93:7]
.io_ptw_status_v (io_ptw_status_v_0), // @[Frontend.scala:93:7]
.io_ptw_status_sd (io_ptw_status_sd_0), // @[Frontend.scala:93:7]
.io_ptw_status_mpv (io_ptw_status_mpv_0), // @[Frontend.scala:93:7]
.io_ptw_status_gva (io_ptw_status_gva_0), // @[Frontend.scala:93:7]
.io_ptw_status_tsr (io_ptw_status_tsr_0), // @[Frontend.scala:93:7]
.io_ptw_status_tw (io_ptw_status_tw_0), // @[Frontend.scala:93:7]
.io_ptw_status_tvm (io_ptw_status_tvm_0), // @[Frontend.scala:93:7]
.io_ptw_status_mxr (io_ptw_status_mxr_0), // @[Frontend.scala:93:7]
.io_ptw_status_sum (io_ptw_status_sum_0), // @[Frontend.scala:93:7]
.io_ptw_status_mprv (io_ptw_status_mprv_0), // @[Frontend.scala:93:7]
.io_ptw_status_fs (io_ptw_status_fs_0), // @[Frontend.scala:93:7]
.io_ptw_status_mpp (io_ptw_status_mpp_0), // @[Frontend.scala:93:7]
.io_ptw_status_spp (io_ptw_status_spp_0), // @[Frontend.scala:93:7]
.io_ptw_status_mpie (io_ptw_status_mpie_0), // @[Frontend.scala:93:7]
.io_ptw_status_spie (io_ptw_status_spie_0), // @[Frontend.scala:93:7]
.io_ptw_status_mie (io_ptw_status_mie_0), // @[Frontend.scala:93:7]
.io_ptw_status_sie (io_ptw_status_sie_0), // @[Frontend.scala:93:7]
.io_ptw_hstatus_spvp (io_ptw_hstatus_spvp_0), // @[Frontend.scala:93:7]
.io_ptw_hstatus_spv (io_ptw_hstatus_spv_0), // @[Frontend.scala:93:7]
.io_ptw_hstatus_gva (io_ptw_hstatus_gva_0), // @[Frontend.scala:93:7]
.io_ptw_gstatus_debug (io_ptw_gstatus_debug_0), // @[Frontend.scala:93:7]
.io_ptw_gstatus_cease (io_ptw_gstatus_cease_0), // @[Frontend.scala:93:7]
.io_ptw_gstatus_wfi (io_ptw_gstatus_wfi_0), // @[Frontend.scala:93:7]
.io_ptw_gstatus_isa (io_ptw_gstatus_isa_0), // @[Frontend.scala:93:7]
.io_ptw_gstatus_dprv (io_ptw_gstatus_dprv_0), // @[Frontend.scala:93:7]
.io_ptw_gstatus_dv (io_ptw_gstatus_dv_0), // @[Frontend.scala:93:7]
.io_ptw_gstatus_prv (io_ptw_gstatus_prv_0), // @[Frontend.scala:93:7]
.io_ptw_gstatus_v (io_ptw_gstatus_v_0), // @[Frontend.scala:93:7]
.io_ptw_gstatus_zero2 (io_ptw_gstatus_zero2_0), // @[Frontend.scala:93:7]
.io_ptw_gstatus_mpv (io_ptw_gstatus_mpv_0), // @[Frontend.scala:93:7]
.io_ptw_gstatus_gva (io_ptw_gstatus_gva_0), // @[Frontend.scala:93:7]
.io_ptw_gstatus_mbe (io_ptw_gstatus_mbe_0), // @[Frontend.scala:93:7]
.io_ptw_gstatus_sbe (io_ptw_gstatus_sbe_0), // @[Frontend.scala:93:7]
.io_ptw_gstatus_sxl (io_ptw_gstatus_sxl_0), // @[Frontend.scala:93:7]
.io_ptw_gstatus_zero1 (io_ptw_gstatus_zero1_0), // @[Frontend.scala:93:7]
.io_ptw_gstatus_tsr (io_ptw_gstatus_tsr_0), // @[Frontend.scala:93:7]
.io_ptw_gstatus_tw (io_ptw_gstatus_tw_0), // @[Frontend.scala:93:7]
.io_ptw_gstatus_tvm (io_ptw_gstatus_tvm_0), // @[Frontend.scala:93:7]
.io_ptw_gstatus_mxr (io_ptw_gstatus_mxr_0), // @[Frontend.scala:93:7]
.io_ptw_gstatus_sum (io_ptw_gstatus_sum_0), // @[Frontend.scala:93:7]
.io_ptw_gstatus_mprv (io_ptw_gstatus_mprv_0), // @[Frontend.scala:93:7]
.io_ptw_gstatus_mpp (io_ptw_gstatus_mpp_0), // @[Frontend.scala:93:7]
.io_ptw_gstatus_vs (io_ptw_gstatus_vs_0), // @[Frontend.scala:93:7]
.io_ptw_gstatus_spp (io_ptw_gstatus_spp_0), // @[Frontend.scala:93:7]
.io_ptw_gstatus_mpie (io_ptw_gstatus_mpie_0), // @[Frontend.scala:93:7]
.io_ptw_gstatus_ube (io_ptw_gstatus_ube_0), // @[Frontend.scala:93:7]
.io_ptw_gstatus_spie (io_ptw_gstatus_spie_0), // @[Frontend.scala:93:7]
.io_ptw_gstatus_upie (io_ptw_gstatus_upie_0), // @[Frontend.scala:93:7]
.io_ptw_gstatus_mie (io_ptw_gstatus_mie_0), // @[Frontend.scala:93:7]
.io_ptw_gstatus_hie (io_ptw_gstatus_hie_0), // @[Frontend.scala:93:7]
.io_ptw_gstatus_sie (io_ptw_gstatus_sie_0), // @[Frontend.scala:93:7]
.io_ptw_gstatus_uie (io_ptw_gstatus_uie_0) // @[Frontend.scala:93:7]
); // @[Frontend.scala:107:19]
ShuttleBTB btb ( // @[Frontend.scala:109:19]
.clock (clock),
.reset (reset),
.io_req_valid (_btb_io_req_valid_T_1), // @[Frontend.scala:152:32]
.io_req_bits_addr (_btb_io_req_bits_addr_T_2[38:0]), // @[Frontend.scala:19:32, :153:24]
.io_resp_valid (_btb_io_resp_valid),
.io_resp_bits_cfiType (_btb_io_resp_bits_cfiType),
.io_resp_bits_taken (_btb_io_resp_bits_taken),
.io_resp_bits_mask (_btb_io_resp_bits_mask),
.io_resp_bits_bridx (_btb_io_resp_bits_bridx),
.io_resp_bits_target (_btb_io_resp_bits_target),
.io_resp_bits_entry (_btb_io_resp_bits_entry),
.io_resp_bits_bht_history (_btb_io_resp_bits_bht_history),
.io_resp_bits_bht_value (_btb_io_resp_bits_bht_value),
.io_btb_update_valid (io_cpu_btb_update_valid_0), // @[Frontend.scala:93:7]
.io_btb_update_bits_prediction_cfiType (io_cpu_btb_update_bits_prediction_cfiType_0), // @[Frontend.scala:93:7]
.io_btb_update_bits_prediction_taken (io_cpu_btb_update_bits_prediction_taken_0), // @[Frontend.scala:93:7]
.io_btb_update_bits_prediction_mask (io_cpu_btb_update_bits_prediction_mask_0), // @[Frontend.scala:93:7]
.io_btb_update_bits_prediction_bridx (io_cpu_btb_update_bits_prediction_bridx_0), // @[Frontend.scala:93:7]
.io_btb_update_bits_prediction_target (io_cpu_btb_update_bits_prediction_target_0), // @[Frontend.scala:93:7]
.io_btb_update_bits_prediction_entry (io_cpu_btb_update_bits_prediction_entry_0), // @[Frontend.scala:93:7]
.io_btb_update_bits_prediction_bht_history (io_cpu_btb_update_bits_prediction_bht_history_0), // @[Frontend.scala:93:7]
.io_btb_update_bits_prediction_bht_value (io_cpu_btb_update_bits_prediction_bht_value_0), // @[Frontend.scala:93:7]
.io_btb_update_bits_pc (io_cpu_btb_update_bits_pc_0), // @[Frontend.scala:93:7]
.io_btb_update_bits_target (io_cpu_btb_update_bits_target_0), // @[Frontend.scala:93:7]
.io_btb_update_bits_isValid (io_cpu_btb_update_bits_isValid_0), // @[Frontend.scala:93:7]
.io_btb_update_bits_br_pc (io_cpu_btb_update_bits_br_pc_0), // @[Frontend.scala:93:7]
.io_btb_update_bits_cfiType (io_cpu_btb_update_bits_cfiType_0), // @[Frontend.scala:93:7]
.io_btb_update_bits_mispredict (io_cpu_btb_update_bits_mispredict_0), // @[Frontend.scala:93:7]
.io_bht_update_valid (io_cpu_bht_update_valid_0), // @[Frontend.scala:93:7]
.io_bht_update_bits_prediction_history (io_cpu_bht_update_bits_prediction_history_0), // @[Frontend.scala:93:7]
.io_bht_update_bits_prediction_value (io_cpu_bht_update_bits_prediction_value_0), // @[Frontend.scala:93:7]
.io_bht_update_bits_pc (io_cpu_bht_update_bits_pc_0), // @[Frontend.scala:93:7]
.io_bht_update_bits_branch (io_cpu_bht_update_bits_branch_0), // @[Frontend.scala:93:7]
.io_bht_update_bits_taken (io_cpu_bht_update_bits_taken_0), // @[Frontend.scala:93:7]
.io_bht_update_bits_mispredict (io_cpu_bht_update_bits_mispredict_0), // @[Frontend.scala:93:7]
.io_bht_advance_valid (_btb_io_bht_advance_valid_T), // @[Frontend.scala:179:40]
.io_bht_advance_bits_cfiType (_btb_io_resp_bits_cfiType), // @[Frontend.scala:109:19]
.io_bht_advance_bits_taken (_btb_io_resp_bits_taken), // @[Frontend.scala:109:19]
.io_bht_advance_bits_mask (_btb_io_resp_bits_mask), // @[Frontend.scala:109:19]
.io_bht_advance_bits_bridx (_btb_io_resp_bits_bridx), // @[Frontend.scala:109:19]
.io_bht_advance_bits_target (_btb_io_resp_bits_target), // @[Frontend.scala:109:19]
.io_bht_advance_bits_entry (_btb_io_resp_bits_entry), // @[Frontend.scala:109:19]
.io_bht_advance_bits_bht_history (_btb_io_resp_bits_bht_history), // @[Frontend.scala:109:19]
.io_bht_advance_bits_bht_value (_btb_io_resp_bits_bht_value), // @[Frontend.scala:109:19]
.io_flush (~valid_3 & s2_btb_resp_valid & (&s2_btb_resp_bits_bridx) | ~valid_2 & s2_btb_resp_valid & _redir_br_T_16 | ~valid_1 & s2_btb_resp_valid & _redir_br_T_9) // @[Frontend.scala:195:28, :267:21, :270:{11,18,39,65,74}, :271:20, :279:53]
); // @[Frontend.scala:109:19]
RVCExpander expanded_rvc_exp ( // @[Consts.scala:41:25]
.clock (clock),
.reset (reset),
.io_in (_expanded_T_1), // @[Frontend.scala:289:37]
.io_out_bits (_expanded_rvc_exp_io_out_bits),
.io_rvc (_expanded_rvc_exp_io_rvc)
); // @[Consts.scala:41:25]
RVCExpander_1 expanded_rvc_exp_1 ( // @[Consts.scala:41:25]
.clock (clock),
.reset (reset),
.io_in (_expanded_T_2), // @[Frontend.scala:294:45]
.io_out_bits (_expanded_rvc_exp_1_io_out_bits),
.io_rvc (_expanded_rvc_exp_1_io_rvc)
); // @[Consts.scala:41:25]
RVCExpander_2 expanded_rvc_exp_2 ( // @[Consts.scala:41:25]
.clock (clock),
.reset (reset),
.io_in (inst), // @[Frontend.scala:301:29]
.io_out_bits (_expanded_rvc_exp_2_io_out_bits),
.io_rvc (_expanded_rvc_exp_2_io_rvc)
); // @[Consts.scala:41:25]
RVCExpander_3 expanded_rvc_exp_3 ( // @[Consts.scala:41:25]
.clock (clock),
.reset (reset),
.io_in (inst_1), // @[Frontend.scala:313:29]
.io_out_bits (_expanded_rvc_exp_3_io_out_bits),
.io_rvc (_expanded_rvc_exp_3_io_rvc)
); // @[Consts.scala:41:25]
RVCExpander_4 expanded_rvc_exp_4 ( // @[Consts.scala:41:25]
.clock (clock),
.reset (reset),
.io_in (inst_2), // @[Frontend.scala:307:21]
.io_out_bits (_expanded_rvc_exp_4_io_out_bits),
.io_rvc (_expanded_rvc_exp_4_io_rvc)
); // @[Consts.scala:41:25]
ShuttleFetchBuffer fb ( // @[Frontend.scala:347:18]
.clock (clock),
.reset (reset),
.io_enq_ready (f3_ready),
.io_enq_valid (_fb_io_enq_valid_T_6), // @[Frontend.scala:348:45]
.io_enq_bits_pc (f2_fetch_bundle_pc), // @[Frontend.scala:245:29]
.io_enq_bits_next_pc_valid (f2_fetch_bundle_next_pc_valid), // @[Frontend.scala:245:29]
.io_enq_bits_next_pc_bits (f2_fetch_bundle_next_pc_bits), // @[Frontend.scala:245:29]
.io_enq_bits_edge_inst (f2_fetch_bundle_edge_inst), // @[Frontend.scala:245:29]
.io_enq_bits_insts_0 (f2_fetch_bundle_insts_0), // @[Frontend.scala:245:29]
.io_enq_bits_insts_1 (f2_fetch_bundle_insts_1), // @[Frontend.scala:245:29]
.io_enq_bits_insts_2 (f2_fetch_bundle_insts_2), // @[Frontend.scala:245:29]
.io_enq_bits_insts_3 (f2_fetch_bundle_insts_3), // @[Frontend.scala:245:29]
.io_enq_bits_exp_insts_0 (f2_fetch_bundle_exp_insts_0), // @[Frontend.scala:245:29]
.io_enq_bits_exp_insts_1 (f2_fetch_bundle_exp_insts_1), // @[Frontend.scala:245:29]
.io_enq_bits_exp_insts_2 (f2_fetch_bundle_exp_insts_2), // @[Frontend.scala:245:29]
.io_enq_bits_exp_insts_3 (f2_fetch_bundle_exp_insts_3), // @[Frontend.scala:245:29]
.io_enq_bits_pcs_0 (f2_fetch_bundle_pcs_0), // @[Frontend.scala:245:29]
.io_enq_bits_pcs_1 (f2_fetch_bundle_pcs_1), // @[Frontend.scala:245:29]
.io_enq_bits_pcs_2 (f2_fetch_bundle_pcs_2), // @[Frontend.scala:245:29]
.io_enq_bits_pcs_3 (f2_fetch_bundle_pcs_3), // @[Frontend.scala:245:29]
.io_enq_bits_mask (f2_fetch_bundle_mask), // @[Frontend.scala:245:29]
.io_enq_bits_btb_resp_valid (f2_fetch_bundle_btb_resp_valid), // @[Frontend.scala:245:29]
.io_enq_bits_btb_resp_bits_cfiType (f2_fetch_bundle_btb_resp_bits_cfiType), // @[Frontend.scala:245:29]
.io_enq_bits_btb_resp_bits_taken (f2_fetch_bundle_btb_resp_bits_taken), // @[Frontend.scala:245:29]
.io_enq_bits_btb_resp_bits_mask (f2_fetch_bundle_btb_resp_bits_mask), // @[Frontend.scala:245:29]
.io_enq_bits_btb_resp_bits_bridx (f2_fetch_bundle_btb_resp_bits_bridx), // @[Frontend.scala:245:29]
.io_enq_bits_btb_resp_bits_target (f2_fetch_bundle_btb_resp_bits_target), // @[Frontend.scala:245:29]
.io_enq_bits_btb_resp_bits_entry (f2_fetch_bundle_btb_resp_bits_entry), // @[Frontend.scala:245:29]
.io_enq_bits_btb_resp_bits_bht_history (f2_fetch_bundle_btb_resp_bits_bht_history), // @[Frontend.scala:245:29]
.io_enq_bits_btb_resp_bits_bht_value (f2_fetch_bundle_btb_resp_bits_bht_value), // @[Frontend.scala:245:29]
.io_enq_bits_ras_head (f2_fetch_bundle_ras_head), // @[Frontend.scala:245:29]
.io_enq_bits_xcpt_pf_if (f2_fetch_bundle_xcpt_pf_if), // @[Frontend.scala:245:29]
.io_enq_bits_xcpt_ae_if (f2_fetch_bundle_xcpt_ae_if), // @[Frontend.scala:245:29]
.io_enq_bits_end_half_valid (f2_fetch_bundle_end_half_valid), // @[Frontend.scala:245:29]
.io_enq_bits_end_half_bits (f2_fetch_bundle_end_half_bits), // @[Frontend.scala:245:29]
.io_deq_0_ready (io_cpu_resp_0_ready_0), // @[Frontend.scala:93:7]
.io_deq_0_valid (io_cpu_resp_0_valid_0),
.io_deq_0_bits_inst (io_cpu_resp_0_bits_inst_0),
.io_deq_0_bits_raw_inst (io_cpu_resp_0_bits_raw_inst_0),
.io_deq_0_bits_pc (io_cpu_resp_0_bits_pc_0),
.io_deq_0_bits_edge_inst (io_cpu_resp_0_bits_edge_inst_0),
.io_deq_0_bits_rvc (io_cpu_resp_0_bits_rvc_0),
.io_deq_0_bits_btb_resp_valid (io_cpu_resp_0_bits_btb_resp_valid_0),
.io_deq_0_bits_btb_resp_bits_cfiType (io_cpu_resp_0_bits_btb_resp_bits_cfiType_0),
.io_deq_0_bits_btb_resp_bits_taken (io_cpu_resp_0_bits_btb_resp_bits_taken_0),
.io_deq_0_bits_btb_resp_bits_mask (io_cpu_resp_0_bits_btb_resp_bits_mask_0),
.io_deq_0_bits_btb_resp_bits_bridx (io_cpu_resp_0_bits_btb_resp_bits_bridx_0),
.io_deq_0_bits_btb_resp_bits_target (io_cpu_resp_0_bits_btb_resp_bits_target_0),
.io_deq_0_bits_btb_resp_bits_entry (io_cpu_resp_0_bits_btb_resp_bits_entry_0),
.io_deq_0_bits_btb_resp_bits_bht_history (io_cpu_resp_0_bits_btb_resp_bits_bht_history_0),
.io_deq_0_bits_btb_resp_bits_bht_value (io_cpu_resp_0_bits_btb_resp_bits_bht_value_0),
.io_deq_0_bits_sfb_br (io_cpu_resp_0_bits_sfb_br_0),
.io_deq_0_bits_next_pc_valid (io_cpu_resp_0_bits_next_pc_valid_0),
.io_deq_0_bits_next_pc_bits (io_cpu_resp_0_bits_next_pc_bits_0),
.io_deq_0_bits_ras_head (io_cpu_resp_0_bits_ras_head_0),
.io_deq_0_bits_xcpt (io_cpu_resp_0_bits_xcpt_0),
.io_deq_0_bits_xcpt_cause (io_cpu_resp_0_bits_xcpt_cause_0),
.io_deq_0_bits_mem_size (io_cpu_resp_0_bits_mem_size_0),
.io_deq_1_ready (io_cpu_resp_1_ready_0), // @[Frontend.scala:93:7]
.io_deq_1_valid (io_cpu_resp_1_valid_0),
.io_deq_1_bits_inst (io_cpu_resp_1_bits_inst_0),
.io_deq_1_bits_raw_inst (io_cpu_resp_1_bits_raw_inst_0),
.io_deq_1_bits_pc (io_cpu_resp_1_bits_pc_0),
.io_deq_1_bits_edge_inst (io_cpu_resp_1_bits_edge_inst_0),
.io_deq_1_bits_rvc (io_cpu_resp_1_bits_rvc_0),
.io_deq_1_bits_btb_resp_valid (io_cpu_resp_1_bits_btb_resp_valid_0),
.io_deq_1_bits_btb_resp_bits_cfiType (io_cpu_resp_1_bits_btb_resp_bits_cfiType_0),
.io_deq_1_bits_btb_resp_bits_taken (io_cpu_resp_1_bits_btb_resp_bits_taken_0),
.io_deq_1_bits_btb_resp_bits_mask (io_cpu_resp_1_bits_btb_resp_bits_mask_0),
.io_deq_1_bits_btb_resp_bits_bridx (io_cpu_resp_1_bits_btb_resp_bits_bridx_0),
.io_deq_1_bits_btb_resp_bits_target (io_cpu_resp_1_bits_btb_resp_bits_target_0),
.io_deq_1_bits_btb_resp_bits_entry (io_cpu_resp_1_bits_btb_resp_bits_entry_0),
.io_deq_1_bits_btb_resp_bits_bht_history (io_cpu_resp_1_bits_btb_resp_bits_bht_history_0),
.io_deq_1_bits_btb_resp_bits_bht_value (io_cpu_resp_1_bits_btb_resp_bits_bht_value_0),
.io_deq_1_bits_sfb_br (io_cpu_resp_1_bits_sfb_br_0),
.io_deq_1_bits_next_pc_valid (io_cpu_resp_1_bits_next_pc_valid_0),
.io_deq_1_bits_next_pc_bits (io_cpu_resp_1_bits_next_pc_bits_0),
.io_deq_1_bits_ras_head (io_cpu_resp_1_bits_ras_head_0),
.io_deq_1_bits_xcpt (io_cpu_resp_1_bits_xcpt_0),
.io_deq_1_bits_xcpt_cause (io_cpu_resp_1_bits_xcpt_cause_0),
.io_deq_1_bits_mem_size (io_cpu_resp_1_bits_mem_size_0),
.io_peek_0_valid (io_cpu_peek_0_valid_0),
.io_peek_0_bits_inst (io_cpu_peek_0_bits_inst_0),
.io_peek_0_bits_raw_inst (io_cpu_peek_0_bits_raw_inst_0),
.io_peek_0_bits_pc (io_cpu_peek_0_bits_pc_0),
.io_peek_0_bits_edge_inst (io_cpu_peek_0_bits_edge_inst_0),
.io_peek_0_bits_rvc (io_cpu_peek_0_bits_rvc_0),
.io_peek_0_bits_btb_resp_valid (io_cpu_peek_0_bits_btb_resp_valid_0),
.io_peek_0_bits_btb_resp_bits_cfiType (io_cpu_peek_0_bits_btb_resp_bits_cfiType_0),
.io_peek_0_bits_btb_resp_bits_taken (io_cpu_peek_0_bits_btb_resp_bits_taken_0),
.io_peek_0_bits_btb_resp_bits_mask (io_cpu_peek_0_bits_btb_resp_bits_mask_0),
.io_peek_0_bits_btb_resp_bits_bridx (io_cpu_peek_0_bits_btb_resp_bits_bridx_0),
.io_peek_0_bits_btb_resp_bits_target (io_cpu_peek_0_bits_btb_resp_bits_target_0),
.io_peek_0_bits_btb_resp_bits_entry (io_cpu_peek_0_bits_btb_resp_bits_entry_0),
.io_peek_0_bits_btb_resp_bits_bht_history (io_cpu_peek_0_bits_btb_resp_bits_bht_history_0),
.io_peek_0_bits_btb_resp_bits_bht_value (io_cpu_peek_0_bits_btb_resp_bits_bht_value_0),
.io_peek_0_bits_sfb_br (io_cpu_peek_0_bits_sfb_br_0),
.io_peek_0_bits_next_pc_valid (io_cpu_peek_0_bits_next_pc_valid_0),
.io_peek_0_bits_next_pc_bits (io_cpu_peek_0_bits_next_pc_bits_0),
.io_peek_0_bits_ras_head (io_cpu_peek_0_bits_ras_head_0),
.io_peek_0_bits_xcpt (io_cpu_peek_0_bits_xcpt_0),
.io_peek_0_bits_xcpt_cause (io_cpu_peek_0_bits_xcpt_cause_0),
.io_peek_0_bits_mem_size (io_cpu_peek_0_bits_mem_size_0),
.io_peek_1_valid (io_cpu_peek_1_valid_0),
.io_peek_1_bits_inst (io_cpu_peek_1_bits_inst_0),
.io_peek_1_bits_raw_inst (io_cpu_peek_1_bits_raw_inst_0),
.io_peek_1_bits_pc (io_cpu_peek_1_bits_pc_0),
.io_peek_1_bits_edge_inst (io_cpu_peek_1_bits_edge_inst_0),
.io_peek_1_bits_rvc (io_cpu_peek_1_bits_rvc_0),
.io_peek_1_bits_btb_resp_valid (io_cpu_peek_1_bits_btb_resp_valid_0),
.io_peek_1_bits_btb_resp_bits_cfiType (io_cpu_peek_1_bits_btb_resp_bits_cfiType_0),
.io_peek_1_bits_btb_resp_bits_taken (io_cpu_peek_1_bits_btb_resp_bits_taken_0),
.io_peek_1_bits_btb_resp_bits_mask (io_cpu_peek_1_bits_btb_resp_bits_mask_0),
.io_peek_1_bits_btb_resp_bits_bridx (io_cpu_peek_1_bits_btb_resp_bits_bridx_0),
.io_peek_1_bits_btb_resp_bits_target (io_cpu_peek_1_bits_btb_resp_bits_target_0),
.io_peek_1_bits_btb_resp_bits_entry (io_cpu_peek_1_bits_btb_resp_bits_entry_0),
.io_peek_1_bits_btb_resp_bits_bht_history (io_cpu_peek_1_bits_btb_resp_bits_bht_history_0),
.io_peek_1_bits_btb_resp_bits_bht_value (io_cpu_peek_1_bits_btb_resp_bits_bht_value_0),
.io_peek_1_bits_sfb_br (io_cpu_peek_1_bits_sfb_br_0),
.io_peek_1_bits_next_pc_valid (io_cpu_peek_1_bits_next_pc_valid_0),
.io_peek_1_bits_next_pc_bits (io_cpu_peek_1_bits_next_pc_bits_0),
.io_peek_1_bits_ras_head (io_cpu_peek_1_bits_ras_head_0),
.io_peek_1_bits_xcpt (io_cpu_peek_1_bits_xcpt_0),
.io_peek_1_bits_xcpt_cause (io_cpu_peek_1_bits_xcpt_cause_0),
.io_peek_1_bits_mem_size (io_cpu_peek_1_bits_mem_size_0),
.io_clear (f2_clear) // @[Frontend.scala:190:26]
); // @[Frontend.scala:347:18]
assign auto_icache_master_out_a_valid = auto_icache_master_out_a_valid_0; // @[Frontend.scala:93:7]
assign auto_icache_master_out_a_bits_address = auto_icache_master_out_a_bits_address_0; // @[Frontend.scala:93:7]
assign io_cpu_resp_0_valid = io_cpu_resp_0_valid_0; // @[Frontend.scala:93:7]
assign io_cpu_resp_0_bits_inst = io_cpu_resp_0_bits_inst_0; // @[Frontend.scala:93:7]
assign io_cpu_resp_0_bits_raw_inst = io_cpu_resp_0_bits_raw_inst_0; // @[Frontend.scala:93:7]
assign io_cpu_resp_0_bits_pc = io_cpu_resp_0_bits_pc_0; // @[Frontend.scala:93:7]
assign io_cpu_resp_0_bits_edge_inst = io_cpu_resp_0_bits_edge_inst_0; // @[Frontend.scala:93:7]
assign io_cpu_resp_0_bits_rvc = io_cpu_resp_0_bits_rvc_0; // @[Frontend.scala:93:7]
assign io_cpu_resp_0_bits_btb_resp_valid = io_cpu_resp_0_bits_btb_resp_valid_0; // @[Frontend.scala:93:7]
assign io_cpu_resp_0_bits_btb_resp_bits_cfiType = io_cpu_resp_0_bits_btb_resp_bits_cfiType_0; // @[Frontend.scala:93:7]
assign io_cpu_resp_0_bits_btb_resp_bits_taken = io_cpu_resp_0_bits_btb_resp_bits_taken_0; // @[Frontend.scala:93:7]
assign io_cpu_resp_0_bits_btb_resp_bits_mask = io_cpu_resp_0_bits_btb_resp_bits_mask_0; // @[Frontend.scala:93:7]
assign io_cpu_resp_0_bits_btb_resp_bits_bridx = io_cpu_resp_0_bits_btb_resp_bits_bridx_0; // @[Frontend.scala:93:7]
assign io_cpu_resp_0_bits_btb_resp_bits_target = io_cpu_resp_0_bits_btb_resp_bits_target_0; // @[Frontend.scala:93:7]
assign io_cpu_resp_0_bits_btb_resp_bits_entry = io_cpu_resp_0_bits_btb_resp_bits_entry_0; // @[Frontend.scala:93:7]
assign io_cpu_resp_0_bits_btb_resp_bits_bht_history = io_cpu_resp_0_bits_btb_resp_bits_bht_history_0; // @[Frontend.scala:93:7]
assign io_cpu_resp_0_bits_btb_resp_bits_bht_value = io_cpu_resp_0_bits_btb_resp_bits_bht_value_0; // @[Frontend.scala:93:7]
assign io_cpu_resp_0_bits_sfb_br = io_cpu_resp_0_bits_sfb_br_0; // @[Frontend.scala:93:7]
assign io_cpu_resp_0_bits_next_pc_valid = io_cpu_resp_0_bits_next_pc_valid_0; // @[Frontend.scala:93:7]
assign io_cpu_resp_0_bits_next_pc_bits = io_cpu_resp_0_bits_next_pc_bits_0; // @[Frontend.scala:93:7]
assign io_cpu_resp_0_bits_ras_head = io_cpu_resp_0_bits_ras_head_0; // @[Frontend.scala:93:7]
assign io_cpu_resp_0_bits_xcpt = io_cpu_resp_0_bits_xcpt_0; // @[Frontend.scala:93:7]
assign io_cpu_resp_0_bits_xcpt_cause = io_cpu_resp_0_bits_xcpt_cause_0; // @[Frontend.scala:93:7]
assign io_cpu_resp_0_bits_mem_size = io_cpu_resp_0_bits_mem_size_0; // @[Frontend.scala:93:7]
assign io_cpu_resp_1_valid = io_cpu_resp_1_valid_0; // @[Frontend.scala:93:7]
assign io_cpu_resp_1_bits_inst = io_cpu_resp_1_bits_inst_0; // @[Frontend.scala:93:7]
assign io_cpu_resp_1_bits_raw_inst = io_cpu_resp_1_bits_raw_inst_0; // @[Frontend.scala:93:7]
assign io_cpu_resp_1_bits_pc = io_cpu_resp_1_bits_pc_0; // @[Frontend.scala:93:7]
assign io_cpu_resp_1_bits_edge_inst = io_cpu_resp_1_bits_edge_inst_0; // @[Frontend.scala:93:7]
assign io_cpu_resp_1_bits_rvc = io_cpu_resp_1_bits_rvc_0; // @[Frontend.scala:93:7]
assign io_cpu_resp_1_bits_btb_resp_valid = io_cpu_resp_1_bits_btb_resp_valid_0; // @[Frontend.scala:93:7]
assign io_cpu_resp_1_bits_btb_resp_bits_cfiType = io_cpu_resp_1_bits_btb_resp_bits_cfiType_0; // @[Frontend.scala:93:7]
assign io_cpu_resp_1_bits_btb_resp_bits_taken = io_cpu_resp_1_bits_btb_resp_bits_taken_0; // @[Frontend.scala:93:7]
assign io_cpu_resp_1_bits_btb_resp_bits_mask = io_cpu_resp_1_bits_btb_resp_bits_mask_0; // @[Frontend.scala:93:7]
assign io_cpu_resp_1_bits_btb_resp_bits_bridx = io_cpu_resp_1_bits_btb_resp_bits_bridx_0; // @[Frontend.scala:93:7]
assign io_cpu_resp_1_bits_btb_resp_bits_target = io_cpu_resp_1_bits_btb_resp_bits_target_0; // @[Frontend.scala:93:7]
assign io_cpu_resp_1_bits_btb_resp_bits_entry = io_cpu_resp_1_bits_btb_resp_bits_entry_0; // @[Frontend.scala:93:7]
assign io_cpu_resp_1_bits_btb_resp_bits_bht_history = io_cpu_resp_1_bits_btb_resp_bits_bht_history_0; // @[Frontend.scala:93:7]
assign io_cpu_resp_1_bits_btb_resp_bits_bht_value = io_cpu_resp_1_bits_btb_resp_bits_bht_value_0; // @[Frontend.scala:93:7]
assign io_cpu_resp_1_bits_sfb_br = io_cpu_resp_1_bits_sfb_br_0; // @[Frontend.scala:93:7]
assign io_cpu_resp_1_bits_next_pc_valid = io_cpu_resp_1_bits_next_pc_valid_0; // @[Frontend.scala:93:7]
assign io_cpu_resp_1_bits_next_pc_bits = io_cpu_resp_1_bits_next_pc_bits_0; // @[Frontend.scala:93:7]
assign io_cpu_resp_1_bits_ras_head = io_cpu_resp_1_bits_ras_head_0; // @[Frontend.scala:93:7]
assign io_cpu_resp_1_bits_xcpt = io_cpu_resp_1_bits_xcpt_0; // @[Frontend.scala:93:7]
assign io_cpu_resp_1_bits_xcpt_cause = io_cpu_resp_1_bits_xcpt_cause_0; // @[Frontend.scala:93:7]
assign io_cpu_resp_1_bits_mem_size = io_cpu_resp_1_bits_mem_size_0; // @[Frontend.scala:93:7]
assign io_cpu_peek_0_valid = io_cpu_peek_0_valid_0; // @[Frontend.scala:93:7]
assign io_cpu_peek_0_bits_inst = io_cpu_peek_0_bits_inst_0; // @[Frontend.scala:93:7]
assign io_cpu_peek_0_bits_raw_inst = io_cpu_peek_0_bits_raw_inst_0; // @[Frontend.scala:93:7]
assign io_cpu_peek_0_bits_pc = io_cpu_peek_0_bits_pc_0; // @[Frontend.scala:93:7]
assign io_cpu_peek_0_bits_edge_inst = io_cpu_peek_0_bits_edge_inst_0; // @[Frontend.scala:93:7]
assign io_cpu_peek_0_bits_rvc = io_cpu_peek_0_bits_rvc_0; // @[Frontend.scala:93:7]
assign io_cpu_peek_0_bits_btb_resp_valid = io_cpu_peek_0_bits_btb_resp_valid_0; // @[Frontend.scala:93:7]
assign io_cpu_peek_0_bits_btb_resp_bits_cfiType = io_cpu_peek_0_bits_btb_resp_bits_cfiType_0; // @[Frontend.scala:93:7]
assign io_cpu_peek_0_bits_btb_resp_bits_taken = io_cpu_peek_0_bits_btb_resp_bits_taken_0; // @[Frontend.scala:93:7]
assign io_cpu_peek_0_bits_btb_resp_bits_mask = io_cpu_peek_0_bits_btb_resp_bits_mask_0; // @[Frontend.scala:93:7]
assign io_cpu_peek_0_bits_btb_resp_bits_bridx = io_cpu_peek_0_bits_btb_resp_bits_bridx_0; // @[Frontend.scala:93:7]
assign io_cpu_peek_0_bits_btb_resp_bits_target = io_cpu_peek_0_bits_btb_resp_bits_target_0; // @[Frontend.scala:93:7]
assign io_cpu_peek_0_bits_btb_resp_bits_entry = io_cpu_peek_0_bits_btb_resp_bits_entry_0; // @[Frontend.scala:93:7]
assign io_cpu_peek_0_bits_btb_resp_bits_bht_history = io_cpu_peek_0_bits_btb_resp_bits_bht_history_0; // @[Frontend.scala:93:7]
assign io_cpu_peek_0_bits_btb_resp_bits_bht_value = io_cpu_peek_0_bits_btb_resp_bits_bht_value_0; // @[Frontend.scala:93:7]
assign io_cpu_peek_0_bits_sfb_br = io_cpu_peek_0_bits_sfb_br_0; // @[Frontend.scala:93:7]
assign io_cpu_peek_0_bits_next_pc_valid = io_cpu_peek_0_bits_next_pc_valid_0; // @[Frontend.scala:93:7]
assign io_cpu_peek_0_bits_next_pc_bits = io_cpu_peek_0_bits_next_pc_bits_0; // @[Frontend.scala:93:7]
assign io_cpu_peek_0_bits_ras_head = io_cpu_peek_0_bits_ras_head_0; // @[Frontend.scala:93:7]
assign io_cpu_peek_0_bits_xcpt = io_cpu_peek_0_bits_xcpt_0; // @[Frontend.scala:93:7]
assign io_cpu_peek_0_bits_xcpt_cause = io_cpu_peek_0_bits_xcpt_cause_0; // @[Frontend.scala:93:7]
assign io_cpu_peek_0_bits_mem_size = io_cpu_peek_0_bits_mem_size_0; // @[Frontend.scala:93:7]
assign io_cpu_peek_1_valid = io_cpu_peek_1_valid_0; // @[Frontend.scala:93:7]
assign io_cpu_peek_1_bits_inst = io_cpu_peek_1_bits_inst_0; // @[Frontend.scala:93:7]
assign io_cpu_peek_1_bits_raw_inst = io_cpu_peek_1_bits_raw_inst_0; // @[Frontend.scala:93:7]
assign io_cpu_peek_1_bits_pc = io_cpu_peek_1_bits_pc_0; // @[Frontend.scala:93:7]
assign io_cpu_peek_1_bits_edge_inst = io_cpu_peek_1_bits_edge_inst_0; // @[Frontend.scala:93:7]
assign io_cpu_peek_1_bits_rvc = io_cpu_peek_1_bits_rvc_0; // @[Frontend.scala:93:7]
assign io_cpu_peek_1_bits_btb_resp_valid = io_cpu_peek_1_bits_btb_resp_valid_0; // @[Frontend.scala:93:7]
assign io_cpu_peek_1_bits_btb_resp_bits_cfiType = io_cpu_peek_1_bits_btb_resp_bits_cfiType_0; // @[Frontend.scala:93:7]
assign io_cpu_peek_1_bits_btb_resp_bits_taken = io_cpu_peek_1_bits_btb_resp_bits_taken_0; // @[Frontend.scala:93:7]
assign io_cpu_peek_1_bits_btb_resp_bits_mask = io_cpu_peek_1_bits_btb_resp_bits_mask_0; // @[Frontend.scala:93:7]
assign io_cpu_peek_1_bits_btb_resp_bits_bridx = io_cpu_peek_1_bits_btb_resp_bits_bridx_0; // @[Frontend.scala:93:7]
assign io_cpu_peek_1_bits_btb_resp_bits_target = io_cpu_peek_1_bits_btb_resp_bits_target_0; // @[Frontend.scala:93:7]
assign io_cpu_peek_1_bits_btb_resp_bits_entry = io_cpu_peek_1_bits_btb_resp_bits_entry_0; // @[Frontend.scala:93:7]
assign io_cpu_peek_1_bits_btb_resp_bits_bht_history = io_cpu_peek_1_bits_btb_resp_bits_bht_history_0; // @[Frontend.scala:93:7]
assign io_cpu_peek_1_bits_btb_resp_bits_bht_value = io_cpu_peek_1_bits_btb_resp_bits_bht_value_0; // @[Frontend.scala:93:7]
assign io_cpu_peek_1_bits_sfb_br = io_cpu_peek_1_bits_sfb_br_0; // @[Frontend.scala:93:7]
assign io_cpu_peek_1_bits_next_pc_valid = io_cpu_peek_1_bits_next_pc_valid_0; // @[Frontend.scala:93:7]
assign io_cpu_peek_1_bits_next_pc_bits = io_cpu_peek_1_bits_next_pc_bits_0; // @[Frontend.scala:93:7]
assign io_cpu_peek_1_bits_ras_head = io_cpu_peek_1_bits_ras_head_0; // @[Frontend.scala:93:7]
assign io_cpu_peek_1_bits_xcpt = io_cpu_peek_1_bits_xcpt_0; // @[Frontend.scala:93:7]
assign io_cpu_peek_1_bits_xcpt_cause = io_cpu_peek_1_bits_xcpt_cause_0; // @[Frontend.scala:93:7]
assign io_cpu_peek_1_bits_mem_size = io_cpu_peek_1_bits_mem_size_0; // @[Frontend.scala:93:7]
assign io_ptw_req_valid = io_ptw_req_valid_0; // @[Frontend.scala:93:7]
assign io_ptw_req_bits_bits_addr = io_ptw_req_bits_bits_addr_0; // @[Frontend.scala:93:7]
assign io_ptw_req_bits_bits_need_gpa = io_ptw_req_bits_bits_need_gpa_0; // @[Frontend.scala:93:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Tilelink.scala:
package constellation.protocol
import chisel3._
import chisel3.util._
import constellation.channel._
import constellation.noc._
import constellation.soc.{CanAttachToGlobalNoC}
import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.util._
import freechips.rocketchip.tilelink._
import scala.collection.immutable.{ListMap}
trait TLFieldHelper {
def getBodyFields(b: TLChannel): Seq[Data] = b match {
case b: TLBundleA => Seq(b.mask, b.data, b.corrupt)
case b: TLBundleB => Seq(b.mask, b.data, b.corrupt)
case b: TLBundleC => Seq( b.data, b.corrupt)
case b: TLBundleD => Seq( b.data, b.corrupt)
case b: TLBundleE => Seq()
}
def getConstFields(b: TLChannel): Seq[Data] = b match {
case b: TLBundleA => Seq(b.opcode, b.param, b.size, b.source, b.address, b.user, b.echo )
case b: TLBundleB => Seq(b.opcode, b.param, b.size, b.source, b.address )
case b: TLBundleC => Seq(b.opcode, b.param, b.size, b.source, b.address, b.user, b.echo )
case b: TLBundleD => Seq(b.opcode, b.param, b.size, b.source, b.user, b.echo, b.sink, b.denied)
case b: TLBundleE => Seq( b.sink )
}
def minTLPayloadWidth(b: TLChannel): Int = Seq(getBodyFields(b), getConstFields(b)).map(_.map(_.getWidth).sum).max
def minTLPayloadWidth(bs: Seq[TLChannel]): Int = bs.map(b => minTLPayloadWidth(b)).max
def minTLPayloadWidth(b: TLBundle): Int = minTLPayloadWidth(Seq(b.a, b.b, b.c, b.d, b.e).map(_.bits))
}
class TLMasterToNoC(
edgeIn: TLEdge, edgesOut: Seq[TLEdge],
sourceStart: Int, sourceSize: Int,
wideBundle: TLBundleParameters,
slaveToEgressOffset: Int => Int,
flitWidth: Int
)(implicit p: Parameters) extends Module {
val io = IO(new Bundle {
val tilelink = Flipped(new TLBundle(wideBundle))
val flits = new Bundle {
val a = Decoupled(new IngressFlit(flitWidth))
val b = Flipped(Decoupled(new EgressFlit(flitWidth)))
val c = Decoupled(new IngressFlit(flitWidth))
val d = Flipped(Decoupled(new EgressFlit(flitWidth)))
val e = Decoupled(new IngressFlit(flitWidth))
}
})
val a = Module(new TLAToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 0, sourceStart))
val b = Module(new TLBFromNoC(edgeIn, wideBundle, sourceSize))
val c = Module(new TLCToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 1, sourceStart))
val d = Module(new TLDFromNoC(edgeIn, wideBundle, sourceSize))
val e = Module(new TLEToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 2))
a.io.protocol <> io.tilelink.a
io.tilelink.b <> b.io.protocol
c.io.protocol <> io.tilelink.c
io.tilelink.d <> d.io.protocol
e.io.protocol <> io.tilelink.e
io.flits.a <> a.io.flit
b.io.flit <> io.flits.b
io.flits.c <> c.io.flit
d.io.flit <> io.flits.d
io.flits.e <> e.io.flit
}
class TLMasterACDToNoC(
edgeIn: TLEdge, edgesOut: Seq[TLEdge],
sourceStart: Int, sourceSize: Int,
wideBundle: TLBundleParameters,
slaveToEgressOffset: Int => Int,
flitWidth: Int
)(implicit p: Parameters) extends Module {
val io = IO(new Bundle {
val tilelink = Flipped(new TLBundle(wideBundle))
val flits = new Bundle {
val a = Decoupled(new IngressFlit(flitWidth))
val c = Decoupled(new IngressFlit(flitWidth))
val d = Flipped(Decoupled(new EgressFlit(flitWidth)))
}
})
io.tilelink := DontCare
val a = Module(new TLAToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 0, sourceStart))
val c = Module(new TLCToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 1, sourceStart))
val d = Module(new TLDFromNoC(edgeIn, wideBundle, sourceSize))
a.io.protocol <> io.tilelink.a
c.io.protocol <> io.tilelink.c
io.tilelink.d <> d.io.protocol
io.flits.a <> a.io.flit
io.flits.c <> c.io.flit
d.io.flit <> io.flits.d
}
class TLMasterBEToNoC(
edgeIn: TLEdge, edgesOut: Seq[TLEdge],
sourceStart: Int, sourceSize: Int,
wideBundle: TLBundleParameters,
slaveToEgressOffset: Int => Int,
flitWidth: Int
)(implicit p: Parameters) extends Module {
val io = IO(new Bundle {
val tilelink = Flipped(new TLBundle(wideBundle))
val flits = new Bundle {
val b = Flipped(Decoupled(new EgressFlit(flitWidth)))
val e = Decoupled(new IngressFlit(flitWidth))
}
})
io.tilelink := DontCare
val b = Module(new TLBFromNoC(edgeIn, wideBundle, sourceSize))
val e = Module(new TLEToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 0))
io.tilelink.b <> b.io.protocol
e.io.protocol <> io.tilelink.e
b.io.flit <> io.flits.b
io.flits.e <> e.io.flit
}
class TLSlaveToNoC(
edgeOut: TLEdge, edgesIn: Seq[TLEdge],
sourceStart: Int, sourceSize: Int,
wideBundle: TLBundleParameters,
masterToEgressOffset: Int => Int,
flitWidth: Int
)(implicit p: Parameters) extends Module {
val io = IO(new Bundle {
val tilelink = new TLBundle(wideBundle)
val flits = new Bundle {
val a = Flipped(Decoupled(new EgressFlit(flitWidth)))
val b = Decoupled(new IngressFlit(flitWidth))
val c = Flipped(Decoupled(new EgressFlit(flitWidth)))
val d = Decoupled(new IngressFlit(flitWidth))
val e = Flipped(Decoupled(new EgressFlit(flitWidth)))
}
})
val a = Module(new TLAFromNoC(edgeOut, wideBundle))
val b = Module(new TLBToNoC(edgeOut, edgesIn, wideBundle, (i) => masterToEgressOffset(i) + 0))
val c = Module(new TLCFromNoC(edgeOut, wideBundle))
val d = Module(new TLDToNoC(edgeOut, edgesIn, wideBundle, (i) => masterToEgressOffset(i) + 1, sourceStart))
val e = Module(new TLEFromNoC(edgeOut, wideBundle, sourceSize))
io.tilelink.a <> a.io.protocol
b.io.protocol <> io.tilelink.b
io.tilelink.c <> c.io.protocol
d.io.protocol <> io.tilelink.d
io.tilelink.e <> e.io.protocol
a.io.flit <> io.flits.a
io.flits.b <> b.io.flit
c.io.flit <> io.flits.c
io.flits.d <> d.io.flit
e.io.flit <> io.flits.e
}
class TLSlaveACDToNoC(
edgeOut: TLEdge, edgesIn: Seq[TLEdge],
sourceStart: Int, sourceSize: Int,
wideBundle: TLBundleParameters,
masterToEgressOffset: Int => Int,
flitWidth: Int
)(implicit p: Parameters) extends Module {
val io = IO(new Bundle {
val tilelink = new TLBundle(wideBundle)
val flits = new Bundle {
val a = Flipped(Decoupled(new EgressFlit(flitWidth)))
val c = Flipped(Decoupled(new EgressFlit(flitWidth)))
val d = Decoupled(new IngressFlit(flitWidth))
}
})
io.tilelink := DontCare
val a = Module(new TLAFromNoC(edgeOut, wideBundle))
val c = Module(new TLCFromNoC(edgeOut, wideBundle))
val d = Module(new TLDToNoC(edgeOut, edgesIn, wideBundle, (i) => masterToEgressOffset(i) + 0, sourceStart))
io.tilelink.a <> a.io.protocol
io.tilelink.c <> c.io.protocol
d.io.protocol <> io.tilelink.d
a.io.flit <> io.flits.a
c.io.flit <> io.flits.c
io.flits.d <> d.io.flit
}
class TLSlaveBEToNoC(
edgeOut: TLEdge, edgesIn: Seq[TLEdge],
sourceStart: Int, sourceSize: Int,
wideBundle: TLBundleParameters,
masterToEgressOffset: Int => Int,
flitWidth: Int
)(implicit p: Parameters) extends Module {
val io = IO(new Bundle {
val tilelink = new TLBundle(wideBundle)
val flits = new Bundle {
val b = Decoupled(new IngressFlit(flitWidth))
val e = Flipped(Decoupled(new EgressFlit(flitWidth)))
}
})
io.tilelink := DontCare
val b = Module(new TLBToNoC(edgeOut, edgesIn, wideBundle, (i) => masterToEgressOffset(i) + 0))
val e = Module(new TLEFromNoC(edgeOut, wideBundle, sourceSize))
b.io.protocol <> io.tilelink.b
io.tilelink.e <> e.io.protocol
io.flits.b <> b.io.flit
e.io.flit <> io.flits.e
}
class TileLinkInterconnectInterface(edgesIn: Seq[TLEdge], edgesOut: Seq[TLEdge])(implicit val p: Parameters) extends Bundle {
val in = MixedVec(edgesIn.map { e => Flipped(new TLBundle(e.bundle)) })
val out = MixedVec(edgesOut.map { e => new TLBundle(e.bundle) })
}
trait TileLinkProtocolParams extends ProtocolParams with TLFieldHelper {
def edgesIn: Seq[TLEdge]
def edgesOut: Seq[TLEdge]
def edgeInNodes: Seq[Int]
def edgeOutNodes: Seq[Int]
require(edgesIn.size == edgeInNodes.size && edgesOut.size == edgeOutNodes.size)
def wideBundle = TLBundleParameters.union(edgesIn.map(_.bundle) ++ edgesOut.map(_.bundle))
def genBundle = new TLBundle(wideBundle)
def inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client))
def outputIdRanges = TLXbar.mapOutputIds(edgesOut.map(_.manager))
val vNetBlocking = (blocker: Int, blockee: Int) => blocker < blockee
def genIO()(implicit p: Parameters): Data = new TileLinkInterconnectInterface(edgesIn, edgesOut)
}
object TLConnect {
def apply[T <: TLBundleBase](l: DecoupledIO[T], r: DecoupledIO[T]) = {
l.valid := r.valid
r.ready := l.ready
l.bits.squeezeAll.waiveAll :<>= r.bits.squeezeAll.waiveAll
}
}
// BEGIN: TileLinkProtocolParams
case class TileLinkABCDEProtocolParams(
edgesIn: Seq[TLEdge],
edgesOut: Seq[TLEdge],
edgeInNodes: Seq[Int],
edgeOutNodes: Seq[Int]
) extends TileLinkProtocolParams {
// END: TileLinkProtocolParams
val minPayloadWidth = minTLPayloadWidth(new TLBundle(wideBundle))
val ingressNodes = (edgeInNodes.map(u => Seq.fill(3) (u)) ++ edgeOutNodes.map(u => Seq.fill (2) {u})).flatten
val egressNodes = (edgeInNodes.map(u => Seq.fill(2) (u)) ++ edgeOutNodes.map(u => Seq.fill (3) {u})).flatten
val nVirtualNetworks = 5
val flows = edgesIn.zipWithIndex.map { case (edgeIn, ii) => edgesOut.zipWithIndex.map { case (edgeOut, oi) =>
val reachable = edgeIn.client.clients.exists { c => edgeOut.manager.managers.exists { m =>
c.visibility.exists { ca => m.address.exists { ma =>
ca.overlaps(ma)
}}
}}
val probe = edgeIn.client.anySupportProbe && edgeOut.manager.managers.exists(_.regionType >= RegionType.TRACKED)
val release = edgeIn.client.anySupportProbe && edgeOut.manager.anySupportAcquireB
( (if (reachable) Some(FlowParams(ii * 3 + 0 , oi * 3 + 0 + edgesIn.size * 2, 4)) else None) ++ // A
(if (probe ) Some(FlowParams(oi * 2 + 0 + edgesIn.size * 3, ii * 2 + 0 , 3)) else None) ++ // B
(if (release ) Some(FlowParams(ii * 3 + 1 , oi * 3 + 1 + edgesIn.size * 2, 2)) else None) ++ // C
(if (reachable) Some(FlowParams(oi * 2 + 1 + edgesIn.size * 3, ii * 2 + 1 , 1)) else None) ++ // D
(if (release ) Some(FlowParams(ii * 3 + 2 , oi * 3 + 2 + edgesIn.size * 2, 0)) else None)) // E
}}.flatten.flatten
def interface(terminals: NoCTerminalIO,
ingressOffset: Int, egressOffset: Int, protocol: Data)(implicit p: Parameters) = {
val ingresses = terminals.ingress
val egresses = terminals.egress
protocol match { case protocol: TileLinkInterconnectInterface => {
edgesIn.zipWithIndex.map { case (e,i) =>
val nif_master = Module(new TLMasterToNoC(
e, edgesOut, inputIdRanges(i).start, inputIdRanges(i).size,
wideBundle,
(s) => s * 3 + edgesIn.size * 2 + egressOffset,
minPayloadWidth
))
nif_master.io.tilelink := DontCare
nif_master.io.tilelink.a.valid := false.B
nif_master.io.tilelink.c.valid := false.B
nif_master.io.tilelink.e.valid := false.B
TLConnect(nif_master.io.tilelink.a, protocol.in(i).a)
TLConnect(protocol.in(i).d, nif_master.io.tilelink.d)
if (protocol.in(i).params.hasBCE) {
TLConnect(protocol.in(i).b, nif_master.io.tilelink.b)
TLConnect(nif_master.io.tilelink.c, protocol.in(i).c)
TLConnect(nif_master.io.tilelink.e, protocol.in(i).e)
}
ingresses(i * 3 + 0).flit <> nif_master.io.flits.a
ingresses(i * 3 + 1).flit <> nif_master.io.flits.c
ingresses(i * 3 + 2).flit <> nif_master.io.flits.e
nif_master.io.flits.b <> egresses(i * 2 + 0).flit
nif_master.io.flits.d <> egresses(i * 2 + 1).flit
}
edgesOut.zipWithIndex.map { case (e,i) =>
val nif_slave = Module(new TLSlaveToNoC(
e, edgesIn, outputIdRanges(i).start, outputIdRanges(i).size,
wideBundle,
(s) => s * 2 + egressOffset,
minPayloadWidth
))
nif_slave.io.tilelink := DontCare
nif_slave.io.tilelink.b.valid := false.B
nif_slave.io.tilelink.d.valid := false.B
TLConnect(protocol.out(i).a, nif_slave.io.tilelink.a)
TLConnect(nif_slave.io.tilelink.d, protocol.out(i).d)
if (protocol.out(i).params.hasBCE) {
TLConnect(nif_slave.io.tilelink.b, protocol.out(i).b)
TLConnect(protocol.out(i).c, nif_slave.io.tilelink.c)
TLConnect(protocol.out(i).e, nif_slave.io.tilelink.e)
}
ingresses(i * 2 + 0 + edgesIn.size * 3).flit <> nif_slave.io.flits.b
ingresses(i * 2 + 1 + edgesIn.size * 3).flit <> nif_slave.io.flits.d
nif_slave.io.flits.a <> egresses(i * 3 + 0 + edgesIn.size * 2).flit
nif_slave.io.flits.c <> egresses(i * 3 + 1 + edgesIn.size * 2).flit
nif_slave.io.flits.e <> egresses(i * 3 + 2 + edgesIn.size * 2).flit
}
} }
}
}
case class TileLinkACDProtocolParams(
edgesIn: Seq[TLEdge],
edgesOut: Seq[TLEdge],
edgeInNodes: Seq[Int],
edgeOutNodes: Seq[Int]) extends TileLinkProtocolParams {
val minPayloadWidth = minTLPayloadWidth(Seq(genBundle.a, genBundle.c, genBundle.d).map(_.bits))
val ingressNodes = (edgeInNodes.map(u => Seq.fill(2) (u)) ++ edgeOutNodes.map(u => Seq.fill (1) {u})).flatten
val egressNodes = (edgeInNodes.map(u => Seq.fill(1) (u)) ++ edgeOutNodes.map(u => Seq.fill (2) {u})).flatten
val nVirtualNetworks = 3
val flows = edgesIn.zipWithIndex.map { case (edgeIn, ii) => edgesOut.zipWithIndex.map { case (edgeOut, oi) =>
val reachable = edgeIn.client.clients.exists { c => edgeOut.manager.managers.exists { m =>
c.visibility.exists { ca => m.address.exists { ma =>
ca.overlaps(ma)
}}
}}
val release = edgeIn.client.anySupportProbe && edgeOut.manager.anySupportAcquireB
( (if (reachable) Some(FlowParams(ii * 2 + 0 , oi * 2 + 0 + edgesIn.size * 1, 2)) else None) ++ // A
(if (release ) Some(FlowParams(ii * 2 + 1 , oi * 2 + 1 + edgesIn.size * 1, 1)) else None) ++ // C
(if (reachable) Some(FlowParams(oi * 1 + 0 + edgesIn.size * 2, ii * 1 + 0 , 0)) else None)) // D
}}.flatten.flatten
def interface(terminals: NoCTerminalIO,
ingressOffset: Int, egressOffset: Int, protocol: Data)(implicit p: Parameters) = {
val ingresses = terminals.ingress
val egresses = terminals.egress
protocol match { case protocol: TileLinkInterconnectInterface => {
protocol := DontCare
edgesIn.zipWithIndex.map { case (e,i) =>
val nif_master_acd = Module(new TLMasterACDToNoC(
e, edgesOut, inputIdRanges(i).start, inputIdRanges(i).size,
wideBundle,
(s) => s * 2 + edgesIn.size * 1 + egressOffset,
minPayloadWidth
))
nif_master_acd.io.tilelink := DontCare
nif_master_acd.io.tilelink.a.valid := false.B
nif_master_acd.io.tilelink.c.valid := false.B
nif_master_acd.io.tilelink.e.valid := false.B
TLConnect(nif_master_acd.io.tilelink.a, protocol.in(i).a)
TLConnect(protocol.in(i).d, nif_master_acd.io.tilelink.d)
if (protocol.in(i).params.hasBCE) {
TLConnect(nif_master_acd.io.tilelink.c, protocol.in(i).c)
}
ingresses(i * 2 + 0).flit <> nif_master_acd.io.flits.a
ingresses(i * 2 + 1).flit <> nif_master_acd.io.flits.c
nif_master_acd.io.flits.d <> egresses(i * 1 + 0).flit
}
edgesOut.zipWithIndex.map { case (e,i) =>
val nif_slave_acd = Module(new TLSlaveACDToNoC(
e, edgesIn, outputIdRanges(i).start, outputIdRanges(i).size,
wideBundle,
(s) => s * 1 + egressOffset,
minPayloadWidth
))
nif_slave_acd.io.tilelink := DontCare
nif_slave_acd.io.tilelink.b.valid := false.B
nif_slave_acd.io.tilelink.d.valid := false.B
TLConnect(protocol.out(i).a, nif_slave_acd.io.tilelink.a)
TLConnect(nif_slave_acd.io.tilelink.d, protocol.out(i).d)
if (protocol.out(i).params.hasBCE) {
TLConnect(protocol.out(i).c, nif_slave_acd.io.tilelink.c)
}
ingresses(i * 1 + 0 + edgesIn.size * 2).flit <> nif_slave_acd.io.flits.d
nif_slave_acd.io.flits.a <> egresses(i * 2 + 0 + edgesIn.size * 1).flit
nif_slave_acd.io.flits.c <> egresses(i * 2 + 1 + edgesIn.size * 1).flit
}
}}
}
}
case class TileLinkBEProtocolParams(
edgesIn: Seq[TLEdge],
edgesOut: Seq[TLEdge],
edgeInNodes: Seq[Int],
edgeOutNodes: Seq[Int]) extends TileLinkProtocolParams {
val minPayloadWidth = minTLPayloadWidth(Seq(genBundle.b, genBundle.e).map(_.bits))
val ingressNodes = (edgeInNodes.map(u => Seq.fill(1) (u)) ++ edgeOutNodes.map(u => Seq.fill (1) {u})).flatten
val egressNodes = (edgeInNodes.map(u => Seq.fill(1) (u)) ++ edgeOutNodes.map(u => Seq.fill (1) {u})).flatten
val nVirtualNetworks = 2
val flows = edgesIn.zipWithIndex.map { case (edgeIn, ii) => edgesOut.zipWithIndex.map { case (edgeOut, oi) =>
val probe = edgeIn.client.anySupportProbe && edgeOut.manager.managers.exists(_.regionType >= RegionType.TRACKED)
val release = edgeIn.client.anySupportProbe && edgeOut.manager.anySupportAcquireB
( (if (probe ) Some(FlowParams(oi * 1 + 0 + edgesIn.size * 1, ii * 1 + 0 , 1)) else None) ++ // B
(if (release ) Some(FlowParams(ii * 1 + 0 , oi * 1 + 0 + edgesIn.size * 1, 0)) else None)) // E
}}.flatten.flatten
def interface(terminals: NoCTerminalIO,
ingressOffset: Int, egressOffset: Int, protocol: Data)(implicit p: Parameters) = {
val ingresses = terminals.ingress
val egresses = terminals.egress
protocol match { case protocol: TileLinkInterconnectInterface => {
protocol := DontCare
edgesIn.zipWithIndex.map { case (e,i) =>
val nif_master_be = Module(new TLMasterBEToNoC(
e, edgesOut, inputIdRanges(i).start, inputIdRanges(i).size,
wideBundle,
(s) => s * 1 + edgesIn.size * 1 + egressOffset,
minPayloadWidth
))
nif_master_be.io.tilelink := DontCare
nif_master_be.io.tilelink.a.valid := false.B
nif_master_be.io.tilelink.c.valid := false.B
nif_master_be.io.tilelink.e.valid := false.B
if (protocol.in(i).params.hasBCE) {
TLConnect(protocol.in(i).b, nif_master_be.io.tilelink.b)
TLConnect(nif_master_be.io.tilelink.e, protocol.in(i).e)
}
ingresses(i * 1 + 0).flit <> nif_master_be.io.flits.e
nif_master_be.io.flits.b <> egresses(i * 1 + 0).flit
}
edgesOut.zipWithIndex.map { case (e,i) =>
val nif_slave_be = Module(new TLSlaveBEToNoC(
e, edgesIn, outputIdRanges(i).start, outputIdRanges(i).size,
wideBundle,
(s) => s * 1 + egressOffset,
minPayloadWidth
))
nif_slave_be.io.tilelink := DontCare
nif_slave_be.io.tilelink.b.valid := false.B
nif_slave_be.io.tilelink.d.valid := false.B
if (protocol.out(i).params.hasBCE) {
TLConnect(protocol.out(i).e, nif_slave_be.io.tilelink.e)
TLConnect(nif_slave_be.io.tilelink.b, protocol.out(i).b)
}
ingresses(i * 1 + 0 + edgesIn.size * 1).flit <> nif_slave_be.io.flits.b
nif_slave_be.io.flits.e <> egresses(i * 1 + 0 + edgesIn.size * 1).flit
}
}}
}
}
abstract class TLNoCLike(implicit p: Parameters) extends LazyModule {
val node = new TLNexusNode(
clientFn = { seq =>
seq(0).v1copy(
echoFields = BundleField.union(seq.flatMap(_.echoFields)),
requestFields = BundleField.union(seq.flatMap(_.requestFields)),
responseKeys = seq.flatMap(_.responseKeys).distinct,
minLatency = seq.map(_.minLatency).min,
clients = (TLXbar.mapInputIds(seq) zip seq) flatMap { case (range, port) =>
port.clients map { client => client.v1copy(
sourceId = client.sourceId.shift(range.start)
)}
}
)
},
managerFn = { seq =>
val fifoIdFactory = TLXbar.relabeler()
seq(0).v1copy(
responseFields = BundleField.union(seq.flatMap(_.responseFields)),
requestKeys = seq.flatMap(_.requestKeys).distinct,
minLatency = seq.map(_.minLatency).min,
endSinkId = TLXbar.mapOutputIds(seq).map(_.end).max,
managers = seq.flatMap { port =>
require (port.beatBytes == seq(0).beatBytes,
s"TLNoC (data widths don't match: ${port.managers.map(_.name)} has ${port.beatBytes}B vs ${seq(0).managers.map(_.name)} has ${seq(0).beatBytes}B")
// TileLink NoC does not preserve FIFO-ness, masters to this NoC should instantiate FIFOFixers
port.managers map { manager => manager.v1copy(fifoId = None) }
}
)
}
)
}
abstract class TLNoCModuleImp(outer: LazyModule) extends LazyModuleImp(outer) {
val edgesIn: Seq[TLEdge]
val edgesOut: Seq[TLEdge]
val nodeMapping: DiplomaticNetworkNodeMapping
val nocName: String
lazy val inNames = nodeMapping.genUniqueName(edgesIn.map(_.master.masters.map(_.name)))
lazy val outNames = nodeMapping.genUniqueName(edgesOut.map(_.slave.slaves.map(_.name)))
lazy val edgeInNodes = nodeMapping.getNodesIn(inNames)
lazy val edgeOutNodes = nodeMapping.getNodesOut(outNames)
def printNodeMappings() {
println(s"Constellation: TLNoC $nocName inwards mapping:")
for ((n, i) <- inNames zip edgeInNodes) {
val node = i.map(_.toString).getOrElse("X")
println(s" $node <- $n")
}
println(s"Constellation: TLNoC $nocName outwards mapping:")
for ((n, i) <- outNames zip edgeOutNodes) {
val node = i.map(_.toString).getOrElse("X")
println(s" $node <- $n")
}
}
}
trait TLNoCParams
// Instantiates a private TLNoC. Replaces the TLXbar
// BEGIN: TLNoCParams
case class SimpleTLNoCParams(
nodeMappings: DiplomaticNetworkNodeMapping,
nocParams: NoCParams = NoCParams(),
) extends TLNoCParams
class TLNoC(params: SimpleTLNoCParams, name: String = "test", inlineNoC: Boolean = false)(implicit p: Parameters) extends TLNoCLike {
// END: TLNoCParams
override def shouldBeInlined = inlineNoC
lazy val module = new TLNoCModuleImp(this) {
val (io_in, edgesIn) = node.in.unzip
val (io_out, edgesOut) = node.out.unzip
val nodeMapping = params.nodeMappings
val nocName = name
printNodeMappings()
val protocolParams = TileLinkABCDEProtocolParams(
edgesIn = edgesIn,
edgesOut = edgesOut,
edgeInNodes = edgeInNodes.flatten,
edgeOutNodes = edgeOutNodes.flatten
)
val noc = Module(new ProtocolNoC(ProtocolNoCParams(
params.nocParams.copy(hasCtrl = false, nocName=name, inlineNoC = inlineNoC),
Seq(protocolParams),
inlineNoC = inlineNoC
)))
noc.io.protocol(0) match {
case protocol: TileLinkInterconnectInterface => {
(protocol.in zip io_in).foreach { case (l,r) => l <> r }
(io_out zip protocol.out).foreach { case (l,r) => l <> r }
}
}
}
}
case class SplitACDxBETLNoCParams(
nodeMappings: DiplomaticNetworkNodeMapping,
acdNoCParams: NoCParams = NoCParams(),
beNoCParams: NoCParams = NoCParams(),
beDivision: Int = 2
) extends TLNoCParams
class TLSplitACDxBENoC(params: SplitACDxBETLNoCParams, name: String = "test", inlineNoC: Boolean = false)(implicit p: Parameters) extends TLNoCLike {
override def shouldBeInlined = inlineNoC
lazy val module = new TLNoCModuleImp(this) {
val (io_in, edgesIn) = node.in.unzip
val (io_out, edgesOut) = node.out.unzip
val nodeMapping = params.nodeMappings
val nocName = name
printNodeMappings()
val acdProtocolParams = TileLinkACDProtocolParams(
edgesIn = edgesIn,
edgesOut = edgesOut,
edgeInNodes = edgeInNodes.flatten,
edgeOutNodes = edgeOutNodes.flatten
)
val beProtocolParams = TileLinkBEProtocolParams(
edgesIn = edgesIn,
edgesOut = edgesOut,
edgeInNodes = edgeInNodes.flatten,
edgeOutNodes = edgeOutNodes.flatten
)
val acd_noc = Module(new ProtocolNoC(ProtocolNoCParams(
params.acdNoCParams.copy(hasCtrl = false, nocName=s"${name}_acd", inlineNoC = inlineNoC),
Seq(acdProtocolParams),
inlineNoC = inlineNoC
)))
val be_noc = Module(new ProtocolNoC(ProtocolNoCParams(
params.beNoCParams.copy(hasCtrl = false, nocName=s"${name}_be", inlineNoC = inlineNoC),
Seq(beProtocolParams),
widthDivision = params.beDivision,
inlineNoC = inlineNoC
)))
acd_noc.io.protocol(0) match { case protocol: TileLinkInterconnectInterface => {
(protocol.in zip io_in).foreach { case (l,r) =>
l := DontCare
l.a <> r.a
l.c <> r.c
l.d <> r.d
}
(io_out zip protocol.out).foreach { case (l,r) =>
r := DontCare
l.a <> r.a
l.c <> r.c
l.d <> r.d
}
}}
be_noc.io.protocol(0) match { case protocol: TileLinkInterconnectInterface => {
(protocol.in zip io_in).foreach { case (l,r) =>
l := DontCare
l.b <> r.b
l.e <> r.e
}
(io_out zip protocol.out).foreach { case (l,r) =>
r := DontCare
l.b <> r.b
l.e <> r.e
}
}}
}
}
case class GlobalTLNoCParams(
nodeMappings: DiplomaticNetworkNodeMapping
) extends TLNoCParams
// Maps this interconnect onto a global NoC
class TLGlobalNoC(params: GlobalTLNoCParams, name: String = "test")(implicit p: Parameters) extends TLNoCLike {
lazy val module = new TLNoCModuleImp(this) with CanAttachToGlobalNoC {
val (io_in, edgesIn) = node.in.unzip
val (io_out, edgesOut) = node.out.unzip
val nodeMapping = params.nodeMappings
val nocName = name
val protocolParams = TileLinkABCDEProtocolParams(
edgesIn = edgesIn,
edgesOut = edgesOut,
edgeInNodes = edgeInNodes.flatten,
edgeOutNodes = edgeOutNodes.flatten
)
printNodeMappings()
val io_global = IO(Flipped(protocolParams.genIO()))
io_global match {
case protocol: TileLinkInterconnectInterface => {
(protocol.in zip io_in).foreach { case (l,r) => l <> r }
(io_out zip protocol.out).foreach { case (l,r) => l <> r }
}
}
}
}
| module TLMasterACDToNoC_5( // @[Tilelink.scala:72:7]
input clock, // @[Tilelink.scala:72:7]
input reset, // @[Tilelink.scala:72:7]
output io_tilelink_a_ready, // @[Tilelink.scala:79:14]
input io_tilelink_a_valid, // @[Tilelink.scala:79:14]
input [2:0] io_tilelink_a_bits_opcode, // @[Tilelink.scala:79:14]
input [2:0] io_tilelink_a_bits_param, // @[Tilelink.scala:79:14]
input [3:0] io_tilelink_a_bits_size, // @[Tilelink.scala:79:14]
input [6:0] io_tilelink_a_bits_source, // @[Tilelink.scala:79:14]
input [31:0] io_tilelink_a_bits_address, // @[Tilelink.scala:79:14]
input [15:0] io_tilelink_a_bits_mask, // @[Tilelink.scala:79:14]
input [127:0] io_tilelink_a_bits_data, // @[Tilelink.scala:79:14]
input io_tilelink_a_bits_corrupt, // @[Tilelink.scala:79:14]
output io_tilelink_c_ready, // @[Tilelink.scala:79:14]
input io_tilelink_c_valid, // @[Tilelink.scala:79:14]
input [2:0] io_tilelink_c_bits_opcode, // @[Tilelink.scala:79:14]
input [2:0] io_tilelink_c_bits_param, // @[Tilelink.scala:79:14]
input [3:0] io_tilelink_c_bits_size, // @[Tilelink.scala:79:14]
input [6:0] io_tilelink_c_bits_source, // @[Tilelink.scala:79:14]
input [31:0] io_tilelink_c_bits_address, // @[Tilelink.scala:79:14]
input [127:0] io_tilelink_c_bits_data, // @[Tilelink.scala:79:14]
input io_tilelink_c_bits_corrupt, // @[Tilelink.scala:79:14]
input io_tilelink_d_ready, // @[Tilelink.scala:79:14]
output io_tilelink_d_valid, // @[Tilelink.scala:79:14]
output [2:0] io_tilelink_d_bits_opcode, // @[Tilelink.scala:79:14]
output [1:0] io_tilelink_d_bits_param, // @[Tilelink.scala:79:14]
output [3:0] io_tilelink_d_bits_size, // @[Tilelink.scala:79:14]
output [6:0] io_tilelink_d_bits_source, // @[Tilelink.scala:79:14]
output [5:0] io_tilelink_d_bits_sink, // @[Tilelink.scala:79:14]
output io_tilelink_d_bits_denied, // @[Tilelink.scala:79:14]
output [127:0] io_tilelink_d_bits_data, // @[Tilelink.scala:79:14]
output io_tilelink_d_bits_corrupt, // @[Tilelink.scala:79:14]
input io_flits_a_ready, // @[Tilelink.scala:79:14]
output io_flits_a_valid, // @[Tilelink.scala:79:14]
output io_flits_a_bits_head, // @[Tilelink.scala:79:14]
output io_flits_a_bits_tail, // @[Tilelink.scala:79:14]
output [144:0] io_flits_a_bits_payload, // @[Tilelink.scala:79:14]
output [4:0] io_flits_a_bits_egress_id, // @[Tilelink.scala:79:14]
input io_flits_c_ready, // @[Tilelink.scala:79:14]
output io_flits_c_valid, // @[Tilelink.scala:79:14]
output io_flits_c_bits_head, // @[Tilelink.scala:79:14]
output io_flits_c_bits_tail, // @[Tilelink.scala:79:14]
output [144:0] io_flits_c_bits_payload, // @[Tilelink.scala:79:14]
output [4:0] io_flits_c_bits_egress_id, // @[Tilelink.scala:79:14]
output io_flits_d_ready, // @[Tilelink.scala:79:14]
input io_flits_d_valid, // @[Tilelink.scala:79:14]
input io_flits_d_bits_head, // @[Tilelink.scala:79:14]
input io_flits_d_bits_tail, // @[Tilelink.scala:79:14]
input [144:0] io_flits_d_bits_payload // @[Tilelink.scala:79:14]
);
wire [128:0] _c_io_flit_bits_payload; // @[Tilelink.scala:89:17]
TLAToNoC_5 a ( // @[Tilelink.scala:88:17]
.clock (clock),
.reset (reset),
.io_protocol_ready (io_tilelink_a_ready),
.io_protocol_valid (io_tilelink_a_valid),
.io_protocol_bits_opcode (io_tilelink_a_bits_opcode),
.io_protocol_bits_param (io_tilelink_a_bits_param),
.io_protocol_bits_size (io_tilelink_a_bits_size),
.io_protocol_bits_source (io_tilelink_a_bits_source),
.io_protocol_bits_address (io_tilelink_a_bits_address),
.io_protocol_bits_mask (io_tilelink_a_bits_mask),
.io_protocol_bits_data (io_tilelink_a_bits_data),
.io_protocol_bits_corrupt (io_tilelink_a_bits_corrupt),
.io_flit_ready (io_flits_a_ready),
.io_flit_valid (io_flits_a_valid),
.io_flit_bits_head (io_flits_a_bits_head),
.io_flit_bits_tail (io_flits_a_bits_tail),
.io_flit_bits_payload (io_flits_a_bits_payload),
.io_flit_bits_egress_id (io_flits_a_bits_egress_id)
); // @[Tilelink.scala:88:17]
TLCToNoC_5 c ( // @[Tilelink.scala:89:17]
.clock (clock),
.reset (reset),
.io_protocol_ready (io_tilelink_c_ready),
.io_protocol_valid (io_tilelink_c_valid),
.io_protocol_bits_opcode (io_tilelink_c_bits_opcode),
.io_protocol_bits_param (io_tilelink_c_bits_param),
.io_protocol_bits_size (io_tilelink_c_bits_size),
.io_protocol_bits_source (io_tilelink_c_bits_source),
.io_protocol_bits_address (io_tilelink_c_bits_address),
.io_protocol_bits_data (io_tilelink_c_bits_data),
.io_protocol_bits_corrupt (io_tilelink_c_bits_corrupt),
.io_flit_ready (io_flits_c_ready),
.io_flit_valid (io_flits_c_valid),
.io_flit_bits_head (io_flits_c_bits_head),
.io_flit_bits_tail (io_flits_c_bits_tail),
.io_flit_bits_payload (_c_io_flit_bits_payload),
.io_flit_bits_egress_id (io_flits_c_bits_egress_id)
); // @[Tilelink.scala:89:17]
TLDFromNoC_1 d ( // @[Tilelink.scala:90:17]
.clock (clock),
.reset (reset),
.io_protocol_ready (io_tilelink_d_ready),
.io_protocol_valid (io_tilelink_d_valid),
.io_protocol_bits_opcode (io_tilelink_d_bits_opcode),
.io_protocol_bits_param (io_tilelink_d_bits_param),
.io_protocol_bits_size (io_tilelink_d_bits_size),
.io_protocol_bits_source (io_tilelink_d_bits_source),
.io_protocol_bits_sink (io_tilelink_d_bits_sink),
.io_protocol_bits_denied (io_tilelink_d_bits_denied),
.io_protocol_bits_data (io_tilelink_d_bits_data),
.io_protocol_bits_corrupt (io_tilelink_d_bits_corrupt),
.io_flit_ready (io_flits_d_ready),
.io_flit_valid (io_flits_d_valid),
.io_flit_bits_head (io_flits_d_bits_head),
.io_flit_bits_tail (io_flits_d_bits_tail),
.io_flit_bits_payload (io_flits_d_bits_payload[128:0]) // @[Tilelink.scala:97:14]
); // @[Tilelink.scala:90:17]
assign io_flits_c_bits_payload = {16'h0, _c_io_flit_bits_payload}; // @[Tilelink.scala:72:7, :89:17, :96:14]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File InputUnit.scala:
package constellation.router
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.util._
import constellation.channel._
import constellation.routing.{FlowRoutingBundle}
import constellation.noc.{HasNoCParams}
class AbstractInputUnitIO(
val cParam: BaseChannelParams,
val outParams: Seq[ChannelParams],
val egressParams: Seq[EgressChannelParams],
)(implicit val p: Parameters) extends Bundle with HasRouterOutputParams {
val nodeId = cParam.destId
val router_req = Decoupled(new RouteComputerReq)
val router_resp = Input(new RouteComputerResp(outParams, egressParams))
val vcalloc_req = Decoupled(new VCAllocReq(cParam, outParams, egressParams))
val vcalloc_resp = Input(new VCAllocResp(outParams, egressParams))
val out_credit_available = Input(MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) }))
val salloc_req = Vec(cParam.destSpeedup, Decoupled(new SwitchAllocReq(outParams, egressParams)))
val out = Vec(cParam.destSpeedup, Valid(new SwitchBundle(outParams, egressParams)))
val debug = Output(new Bundle {
val va_stall = UInt(log2Ceil(cParam.nVirtualChannels).W)
val sa_stall = UInt(log2Ceil(cParam.nVirtualChannels).W)
})
val block = Input(Bool())
}
abstract class AbstractInputUnit(
val cParam: BaseChannelParams,
val outParams: Seq[ChannelParams],
val egressParams: Seq[EgressChannelParams]
)(implicit val p: Parameters) extends Module with HasRouterOutputParams with HasNoCParams {
val nodeId = cParam.destId
def io: AbstractInputUnitIO
}
class InputBuffer(cParam: ChannelParams)(implicit p: Parameters) extends Module {
val nVirtualChannels = cParam.nVirtualChannels
val io = IO(new Bundle {
val enq = Flipped(Vec(cParam.srcSpeedup, Valid(new Flit(cParam.payloadBits))))
val deq = Vec(cParam.nVirtualChannels, Decoupled(new BaseFlit(cParam.payloadBits)))
})
val useOutputQueues = cParam.useOutputQueues
val delims = if (useOutputQueues) {
cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize else 0).scanLeft(0)(_+_)
} else {
// If no queuing, have to add an additional slot since head == tail implies empty
// TODO this should be fixed, should use all slots available
cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize + 1 else 0).scanLeft(0)(_+_)
}
val starts = delims.dropRight(1).zipWithIndex.map { case (s,i) =>
if (cParam.virtualChannelParams(i).traversable) s else 0
}
val ends = delims.tail.zipWithIndex.map { case (s,i) =>
if (cParam.virtualChannelParams(i).traversable) s else 0
}
val fullSize = delims.last
// Ugly case. Use multiple queues
if ((cParam.srcSpeedup > 1 || cParam.destSpeedup > 1 || fullSize <= 1) || !cParam.unifiedBuffer) {
require(useOutputQueues)
val qs = cParam.virtualChannelParams.map(v => Module(new Queue(new BaseFlit(cParam.payloadBits), v.bufferSize)))
qs.zipWithIndex.foreach { case (q,i) =>
val sel = io.enq.map(f => f.valid && f.bits.virt_channel_id === i.U)
q.io.enq.valid := sel.orR
q.io.enq.bits.head := Mux1H(sel, io.enq.map(_.bits.head))
q.io.enq.bits.tail := Mux1H(sel, io.enq.map(_.bits.tail))
q.io.enq.bits.payload := Mux1H(sel, io.enq.map(_.bits.payload))
io.deq(i) <> q.io.deq
}
} else {
val mem = Mem(fullSize, new BaseFlit(cParam.payloadBits))
val heads = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W))))
val tails = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W))))
val empty = (heads zip tails).map(t => t._1 === t._2)
val qs = Seq.fill(nVirtualChannels) { Module(new Queue(new BaseFlit(cParam.payloadBits), 1, pipe=true)) }
qs.foreach(_.io.enq.valid := false.B)
qs.foreach(_.io.enq.bits := DontCare)
val vc_sel = UIntToOH(io.enq(0).bits.virt_channel_id)
val flit = Wire(new BaseFlit(cParam.payloadBits))
val direct_to_q = (Mux1H(vc_sel, qs.map(_.io.enq.ready)) && Mux1H(vc_sel, empty)) && useOutputQueues.B
flit.head := io.enq(0).bits.head
flit.tail := io.enq(0).bits.tail
flit.payload := io.enq(0).bits.payload
when (io.enq(0).valid && !direct_to_q) {
val tail = tails(io.enq(0).bits.virt_channel_id)
mem.write(tail, flit)
tails(io.enq(0).bits.virt_channel_id) := Mux(
tail === Mux1H(vc_sel, ends.map(_ - 1).map(_ max 0).map(_.U)),
Mux1H(vc_sel, starts.map(_.U)),
tail + 1.U)
} .elsewhen (io.enq(0).valid && direct_to_q) {
for (i <- 0 until nVirtualChannels) {
when (io.enq(0).bits.virt_channel_id === i.U) {
qs(i).io.enq.valid := true.B
qs(i).io.enq.bits := flit
}
}
}
if (useOutputQueues) {
val can_to_q = (0 until nVirtualChannels).map { i => !empty(i) && qs(i).io.enq.ready }
val to_q_oh = PriorityEncoderOH(can_to_q)
val to_q = OHToUInt(to_q_oh)
when (can_to_q.orR) {
val head = Mux1H(to_q_oh, heads)
heads(to_q) := Mux(
head === Mux1H(to_q_oh, ends.map(_ - 1).map(_ max 0).map(_.U)),
Mux1H(to_q_oh, starts.map(_.U)),
head + 1.U)
for (i <- 0 until nVirtualChannels) {
when (to_q_oh(i)) {
qs(i).io.enq.valid := true.B
qs(i).io.enq.bits := mem.read(head)
}
}
}
for (i <- 0 until nVirtualChannels) {
io.deq(i) <> qs(i).io.deq
}
} else {
qs.map(_.io.deq.ready := false.B)
val ready_sel = io.deq.map(_.ready)
val fire = io.deq.map(_.fire)
assert(PopCount(fire) <= 1.U)
val head = Mux1H(fire, heads)
when (fire.orR) {
val fire_idx = OHToUInt(fire)
heads(fire_idx) := Mux(
head === Mux1H(fire, ends.map(_ - 1).map(_ max 0).map(_.U)),
Mux1H(fire, starts.map(_.U)),
head + 1.U)
}
val read_flit = mem.read(head)
for (i <- 0 until nVirtualChannels) {
io.deq(i).valid := !empty(i)
io.deq(i).bits := read_flit
}
}
}
}
class InputUnit(cParam: ChannelParams, outParams: Seq[ChannelParams],
egressParams: Seq[EgressChannelParams],
combineRCVA: Boolean, combineSAST: Boolean
)
(implicit p: Parameters) extends AbstractInputUnit(cParam, outParams, egressParams)(p) {
val nVirtualChannels = cParam.nVirtualChannels
val virtualChannelParams = cParam.virtualChannelParams
class InputUnitIO extends AbstractInputUnitIO(cParam, outParams, egressParams) {
val in = Flipped(new Channel(cParam.asInstanceOf[ChannelParams]))
}
val io = IO(new InputUnitIO)
val g_i :: g_r :: g_v :: g_a :: g_c :: Nil = Enum(5)
class InputState extends Bundle {
val g = UInt(3.W)
val vc_sel = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) })
val flow = new FlowRoutingBundle
val fifo_deps = UInt(nVirtualChannels.W)
}
val input_buffer = Module(new InputBuffer(cParam))
for (i <- 0 until cParam.srcSpeedup) {
input_buffer.io.enq(i) := io.in.flit(i)
}
input_buffer.io.deq.foreach(_.ready := false.B)
val route_arbiter = Module(new Arbiter(
new RouteComputerReq, nVirtualChannels
))
io.router_req <> route_arbiter.io.out
val states = Reg(Vec(nVirtualChannels, new InputState))
val anyFifo = cParam.possibleFlows.map(_.fifo).reduce(_||_)
val allFifo = cParam.possibleFlows.map(_.fifo).reduce(_&&_)
if (anyFifo) {
val idle_mask = VecInit(states.map(_.g === g_i)).asUInt
for (s <- states)
for (i <- 0 until nVirtualChannels)
s.fifo_deps := s.fifo_deps & ~idle_mask
}
for (i <- 0 until cParam.srcSpeedup) {
when (io.in.flit(i).fire && io.in.flit(i).bits.head) {
val id = io.in.flit(i).bits.virt_channel_id
assert(id < nVirtualChannels.U)
assert(states(id).g === g_i)
val at_dest = io.in.flit(i).bits.flow.egress_node === nodeId.U
states(id).g := Mux(at_dest, g_v, g_r)
states(id).vc_sel.foreach(_.foreach(_ := false.B))
for (o <- 0 until nEgress) {
when (o.U === io.in.flit(i).bits.flow.egress_node_id) {
states(id).vc_sel(o+nOutputs)(0) := true.B
}
}
states(id).flow := io.in.flit(i).bits.flow
if (anyFifo) {
val fifo = cParam.possibleFlows.filter(_.fifo).map(_.isFlow(io.in.flit(i).bits.flow)).toSeq.orR
states(id).fifo_deps := VecInit(states.zipWithIndex.map { case (s, j) =>
s.g =/= g_i && s.flow.asUInt === io.in.flit(i).bits.flow.asUInt && j.U =/= id
}).asUInt
}
}
}
(route_arbiter.io.in zip states).zipWithIndex.map { case ((i,s),idx) =>
if (virtualChannelParams(idx).traversable) {
i.valid := s.g === g_r
i.bits.flow := s.flow
i.bits.src_virt_id := idx.U
when (i.fire) { s.g := g_v }
} else {
i.valid := false.B
i.bits := DontCare
}
}
when (io.router_req.fire) {
val id = io.router_req.bits.src_virt_id
assert(states(id).g === g_r)
states(id).g := g_v
for (i <- 0 until nVirtualChannels) {
when (i.U === id) {
states(i).vc_sel := io.router_resp.vc_sel
}
}
}
val mask = RegInit(0.U(nVirtualChannels.W))
val vcalloc_reqs = Wire(Vec(nVirtualChannels, new VCAllocReq(cParam, outParams, egressParams)))
val vcalloc_vals = Wire(Vec(nVirtualChannels, Bool()))
val vcalloc_filter = PriorityEncoderOH(Cat(vcalloc_vals.asUInt, vcalloc_vals.asUInt & ~mask))
val vcalloc_sel = vcalloc_filter(nVirtualChannels-1,0) | (vcalloc_filter >> nVirtualChannels)
// Prioritize incoming packetes
when (io.router_req.fire) {
mask := (1.U << io.router_req.bits.src_virt_id) - 1.U
} .elsewhen (vcalloc_vals.orR) {
mask := Mux1H(vcalloc_sel, (0 until nVirtualChannels).map { w => ~(0.U((w+1).W)) })
}
io.vcalloc_req.valid := vcalloc_vals.orR
io.vcalloc_req.bits := Mux1H(vcalloc_sel, vcalloc_reqs)
states.zipWithIndex.map { case (s,idx) =>
if (virtualChannelParams(idx).traversable) {
vcalloc_vals(idx) := s.g === g_v && s.fifo_deps === 0.U
vcalloc_reqs(idx).in_vc := idx.U
vcalloc_reqs(idx).vc_sel := s.vc_sel
vcalloc_reqs(idx).flow := s.flow
when (vcalloc_vals(idx) && vcalloc_sel(idx) && io.vcalloc_req.ready) { s.g := g_a }
if (combineRCVA) {
when (route_arbiter.io.in(idx).fire) {
vcalloc_vals(idx) := true.B
vcalloc_reqs(idx).vc_sel := io.router_resp.vc_sel
}
}
} else {
vcalloc_vals(idx) := false.B
vcalloc_reqs(idx) := DontCare
}
}
io.debug.va_stall := PopCount(vcalloc_vals) - io.vcalloc_req.ready
when (io.vcalloc_req.fire) {
for (i <- 0 until nVirtualChannels) {
when (vcalloc_sel(i)) {
states(i).vc_sel := io.vcalloc_resp.vc_sel
states(i).g := g_a
if (!combineRCVA) {
assert(states(i).g === g_v)
}
}
}
}
val salloc_arb = Module(new SwitchArbiter(
nVirtualChannels,
cParam.destSpeedup,
outParams, egressParams
))
(states zip salloc_arb.io.in).zipWithIndex.map { case ((s,r),i) =>
if (virtualChannelParams(i).traversable) {
val credit_available = (s.vc_sel.asUInt & io.out_credit_available.asUInt) =/= 0.U
r.valid := s.g === g_a && credit_available && input_buffer.io.deq(i).valid
r.bits.vc_sel := s.vc_sel
val deq_tail = input_buffer.io.deq(i).bits.tail
r.bits.tail := deq_tail
when (r.fire && deq_tail) {
s.g := g_i
}
input_buffer.io.deq(i).ready := r.ready
} else {
r.valid := false.B
r.bits := DontCare
}
}
io.debug.sa_stall := PopCount(salloc_arb.io.in.map(r => r.valid && !r.ready))
io.salloc_req <> salloc_arb.io.out
when (io.block) {
salloc_arb.io.out.foreach(_.ready := false.B)
io.salloc_req.foreach(_.valid := false.B)
}
class OutBundle extends Bundle {
val valid = Bool()
val vid = UInt(virtualChannelBits.W)
val out_vid = UInt(log2Up(allOutParams.map(_.nVirtualChannels).max).W)
val flit = new Flit(cParam.payloadBits)
}
val salloc_outs = if (combineSAST) {
Wire(Vec(cParam.destSpeedup, new OutBundle))
} else {
Reg(Vec(cParam.destSpeedup, new OutBundle))
}
io.in.credit_return := salloc_arb.io.out.zipWithIndex.map { case (o, i) =>
Mux(o.fire, salloc_arb.io.chosen_oh(i), 0.U)
}.reduce(_|_)
io.in.vc_free := salloc_arb.io.out.zipWithIndex.map { case (o, i) =>
Mux(o.fire && Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail)),
salloc_arb.io.chosen_oh(i), 0.U)
}.reduce(_|_)
for (i <- 0 until cParam.destSpeedup) {
val salloc_out = salloc_outs(i)
salloc_out.valid := salloc_arb.io.out(i).fire
salloc_out.vid := OHToUInt(salloc_arb.io.chosen_oh(i))
val vc_sel = Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.vc_sel))
val channel_oh = vc_sel.map(_.reduce(_||_)).toSeq
val virt_channel = Mux1H(channel_oh, vc_sel.map(v => OHToUInt(v)).toSeq)
when (salloc_arb.io.out(i).fire) {
salloc_out.out_vid := virt_channel
salloc_out.flit.payload := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.payload))
salloc_out.flit.head := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.head))
salloc_out.flit.tail := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail))
salloc_out.flit.flow := Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.flow))
} .otherwise {
salloc_out.out_vid := DontCare
salloc_out.flit := DontCare
}
salloc_out.flit.virt_channel_id := DontCare // this gets set in the switch
io.out(i).valid := salloc_out.valid
io.out(i).bits.flit := salloc_out.flit
io.out(i).bits.out_virt_channel := salloc_out.out_vid
}
def filterVCSel(sel: MixedVec[Vec[Bool]], srcV: Int) = {
if (virtualChannelParams(srcV).traversable) {
outParams.zipWithIndex.map { case (oP, oI) =>
(0 until oP.nVirtualChannels).map { oV =>
var allow = false
virtualChannelParams(srcV).possibleFlows.foreach { pI =>
allow = allow || routingRelation(
cParam.channelRoutingInfos(srcV),
oP.channelRoutingInfos(oV),
pI
)
}
if (!allow)
sel(oI)(oV) := false.B
}
}
}
}
(0 until nVirtualChannels).map { i =>
if (!virtualChannelParams(i).traversable) states(i) := DontCare
filterVCSel(states(i).vc_sel, i)
}
when (reset.asBool) {
states.foreach(_.g := g_i)
}
}
| module InputBuffer_6( // @[InputUnit.scala:49:7]
input clock, // @[InputUnit.scala:49:7]
input reset, // @[InputUnit.scala:49:7]
input io_enq_0_valid, // @[InputUnit.scala:51:14]
input io_enq_0_bits_head, // @[InputUnit.scala:51:14]
input io_enq_0_bits_tail, // @[InputUnit.scala:51:14]
input [72:0] io_enq_0_bits_payload, // @[InputUnit.scala:51:14]
input [3:0] io_enq_0_bits_virt_channel_id, // @[InputUnit.scala:51:14]
input io_deq_0_ready, // @[InputUnit.scala:51:14]
output io_deq_0_valid, // @[InputUnit.scala:51:14]
output io_deq_0_bits_head, // @[InputUnit.scala:51:14]
output io_deq_0_bits_tail, // @[InputUnit.scala:51:14]
output [72:0] io_deq_0_bits_payload, // @[InputUnit.scala:51:14]
input io_deq_1_ready, // @[InputUnit.scala:51:14]
output io_deq_1_valid, // @[InputUnit.scala:51:14]
output io_deq_1_bits_head, // @[InputUnit.scala:51:14]
output io_deq_1_bits_tail, // @[InputUnit.scala:51:14]
output [72:0] io_deq_1_bits_payload, // @[InputUnit.scala:51:14]
output io_deq_2_bits_head, // @[InputUnit.scala:51:14]
output io_deq_2_bits_tail, // @[InputUnit.scala:51:14]
output [72:0] io_deq_2_bits_payload, // @[InputUnit.scala:51:14]
input io_deq_3_ready, // @[InputUnit.scala:51:14]
output io_deq_3_valid, // @[InputUnit.scala:51:14]
output io_deq_3_bits_head, // @[InputUnit.scala:51:14]
output io_deq_3_bits_tail, // @[InputUnit.scala:51:14]
output [72:0] io_deq_3_bits_payload, // @[InputUnit.scala:51:14]
input io_deq_4_ready, // @[InputUnit.scala:51:14]
output io_deq_4_valid, // @[InputUnit.scala:51:14]
output io_deq_4_bits_head, // @[InputUnit.scala:51:14]
output io_deq_4_bits_tail, // @[InputUnit.scala:51:14]
output [72:0] io_deq_4_bits_payload, // @[InputUnit.scala:51:14]
input io_deq_5_ready, // @[InputUnit.scala:51:14]
output io_deq_5_valid, // @[InputUnit.scala:51:14]
output io_deq_5_bits_head, // @[InputUnit.scala:51:14]
output io_deq_5_bits_tail, // @[InputUnit.scala:51:14]
output [72:0] io_deq_5_bits_payload, // @[InputUnit.scala:51:14]
output io_deq_6_bits_head, // @[InputUnit.scala:51:14]
output io_deq_6_bits_tail, // @[InputUnit.scala:51:14]
output [72:0] io_deq_6_bits_payload, // @[InputUnit.scala:51:14]
input io_deq_7_ready, // @[InputUnit.scala:51:14]
output io_deq_7_valid, // @[InputUnit.scala:51:14]
output io_deq_7_bits_head, // @[InputUnit.scala:51:14]
output io_deq_7_bits_tail, // @[InputUnit.scala:51:14]
output [72:0] io_deq_7_bits_payload, // @[InputUnit.scala:51:14]
input io_deq_8_ready, // @[InputUnit.scala:51:14]
output io_deq_8_valid, // @[InputUnit.scala:51:14]
output io_deq_8_bits_head, // @[InputUnit.scala:51:14]
output io_deq_8_bits_tail, // @[InputUnit.scala:51:14]
output [72:0] io_deq_8_bits_payload, // @[InputUnit.scala:51:14]
input io_deq_9_ready, // @[InputUnit.scala:51:14]
output io_deq_9_valid, // @[InputUnit.scala:51:14]
output io_deq_9_bits_head, // @[InputUnit.scala:51:14]
output io_deq_9_bits_tail, // @[InputUnit.scala:51:14]
output [72:0] io_deq_9_bits_payload // @[InputUnit.scala:51:14]
);
wire _qs_9_io_enq_ready; // @[InputUnit.scala:90:49]
wire _qs_8_io_enq_ready; // @[InputUnit.scala:90:49]
wire _qs_7_io_enq_ready; // @[InputUnit.scala:90:49]
wire _qs_6_io_enq_ready; // @[InputUnit.scala:90:49]
wire _qs_5_io_enq_ready; // @[InputUnit.scala:90:49]
wire _qs_4_io_enq_ready; // @[InputUnit.scala:90:49]
wire _qs_3_io_enq_ready; // @[InputUnit.scala:90:49]
wire _qs_2_io_enq_ready; // @[InputUnit.scala:90:49]
wire _qs_1_io_enq_ready; // @[InputUnit.scala:90:49]
wire _qs_0_io_enq_ready; // @[InputUnit.scala:90:49]
wire [74:0] _mem_ext_R0_data; // @[InputUnit.scala:85:18]
wire [74:0] _mem_ext_R1_data; // @[InputUnit.scala:85:18]
wire [74:0] _mem_ext_R2_data; // @[InputUnit.scala:85:18]
wire [74:0] _mem_ext_R3_data; // @[InputUnit.scala:85:18]
wire [74:0] _mem_ext_R4_data; // @[InputUnit.scala:85:18]
wire [74:0] _mem_ext_R5_data; // @[InputUnit.scala:85:18]
wire [74:0] _mem_ext_R6_data; // @[InputUnit.scala:85:18]
wire [74:0] _mem_ext_R7_data; // @[InputUnit.scala:85:18]
wire [74:0] _mem_ext_R8_data; // @[InputUnit.scala:85:18]
wire [74:0] _mem_ext_R9_data; // @[InputUnit.scala:85:18]
reg [4:0] heads_0; // @[InputUnit.scala:86:24]
reg [4:0] heads_1; // @[InputUnit.scala:86:24]
reg [4:0] heads_2; // @[InputUnit.scala:86:24]
reg [4:0] heads_3; // @[InputUnit.scala:86:24]
reg [4:0] heads_4; // @[InputUnit.scala:86:24]
reg [4:0] heads_5; // @[InputUnit.scala:86:24]
reg [4:0] heads_6; // @[InputUnit.scala:86:24]
reg [4:0] heads_7; // @[InputUnit.scala:86:24]
reg [4:0] heads_8; // @[InputUnit.scala:86:24]
reg [4:0] heads_9; // @[InputUnit.scala:86:24]
reg [4:0] tails_0; // @[InputUnit.scala:87:24]
reg [4:0] tails_1; // @[InputUnit.scala:87:24]
reg [4:0] tails_2; // @[InputUnit.scala:87:24]
reg [4:0] tails_3; // @[InputUnit.scala:87:24]
reg [4:0] tails_4; // @[InputUnit.scala:87:24]
reg [4:0] tails_5; // @[InputUnit.scala:87:24]
reg [4:0] tails_6; // @[InputUnit.scala:87:24]
reg [4:0] tails_7; // @[InputUnit.scala:87:24]
reg [4:0] tails_8; // @[InputUnit.scala:87:24]
reg [4:0] tails_9; // @[InputUnit.scala:87:24]
wire _tails_T_30 = io_enq_0_bits_virt_channel_id == 4'h0; // @[Mux.scala:32:36]
wire _tails_T_31 = io_enq_0_bits_virt_channel_id == 4'h1; // @[Mux.scala:32:36]
wire _tails_T_32 = io_enq_0_bits_virt_channel_id == 4'h2; // @[Mux.scala:32:36]
wire _tails_T_33 = io_enq_0_bits_virt_channel_id == 4'h3; // @[Mux.scala:32:36]
wire _tails_T_34 = io_enq_0_bits_virt_channel_id == 4'h4; // @[Mux.scala:32:36]
wire _tails_T_35 = io_enq_0_bits_virt_channel_id == 4'h5; // @[Mux.scala:32:36]
wire _tails_T_36 = io_enq_0_bits_virt_channel_id == 4'h6; // @[Mux.scala:32:36]
wire _tails_T_37 = io_enq_0_bits_virt_channel_id == 4'h7; // @[Mux.scala:32:36]
wire _tails_T_38 = io_enq_0_bits_virt_channel_id == 4'h8; // @[Mux.scala:32:36]
wire _tails_T_39 = io_enq_0_bits_virt_channel_id == 4'h9; // @[Mux.scala:32:36]
wire direct_to_q = (_tails_T_30 & _qs_0_io_enq_ready | _tails_T_31 & _qs_1_io_enq_ready | _tails_T_32 & _qs_2_io_enq_ready | _tails_T_33 & _qs_3_io_enq_ready | _tails_T_34 & _qs_4_io_enq_ready | _tails_T_35 & _qs_5_io_enq_ready | _tails_T_36 & _qs_6_io_enq_ready | _tails_T_37 & _qs_7_io_enq_ready | _tails_T_38 & _qs_8_io_enq_ready | _tails_T_39 & _qs_9_io_enq_ready) & (_tails_T_30 & heads_0 == tails_0 | _tails_T_31 & heads_1 == tails_1 | _tails_T_32 & heads_2 == tails_2 | _tails_T_33 & heads_3 == tails_3 | _tails_T_34 & heads_4 == tails_4 | _tails_T_35 & heads_5 == tails_5 | _tails_T_36 & heads_6 == tails_6 | _tails_T_37 & heads_7 == tails_7 | _tails_T_38 & heads_8 == tails_8 | _tails_T_39 & heads_9 == tails_9); // @[Mux.scala:30:73, :32:36]
wire mem_MPORT_en = io_enq_0_valid & ~direct_to_q; // @[InputUnit.scala:96:62, :100:{27,30}]
wire [15:0][4:0] _GEN = {{tails_0}, {tails_0}, {tails_0}, {tails_0}, {tails_0}, {tails_0}, {tails_9}, {tails_8}, {tails_7}, {tails_6}, {tails_5}, {tails_4}, {tails_3}, {tails_2}, {tails_1}, {tails_0}}; // @[InputUnit.scala:87:24, :102:16]
wire _GEN_0 = io_enq_0_bits_virt_channel_id == 4'h0; // @[InputUnit.scala:103:45]
wire _GEN_1 = io_enq_0_bits_virt_channel_id == 4'h1; // @[InputUnit.scala:103:45]
wire _GEN_2 = io_enq_0_bits_virt_channel_id == 4'h2; // @[InputUnit.scala:103:45]
wire _GEN_3 = io_enq_0_bits_virt_channel_id == 4'h3; // @[InputUnit.scala:103:45]
wire _GEN_4 = io_enq_0_bits_virt_channel_id == 4'h4; // @[InputUnit.scala:103:45]
wire _GEN_5 = io_enq_0_bits_virt_channel_id == 4'h5; // @[InputUnit.scala:103:45]
wire _GEN_6 = io_enq_0_bits_virt_channel_id == 4'h6; // @[InputUnit.scala:103:45]
wire _GEN_7 = io_enq_0_bits_virt_channel_id == 4'h7; // @[InputUnit.scala:103:45]
wire _GEN_8 = io_enq_0_bits_virt_channel_id == 4'h8; // @[InputUnit.scala:103:45]
wire _GEN_9 = io_enq_0_bits_virt_channel_id == 4'h9; // @[InputUnit.scala:103:45]
wire _GEN_10 = io_enq_0_valid & direct_to_q; // @[InputUnit.scala:96:62, :107:34]
wire can_to_q_0 = heads_0 != tails_0 & _qs_0_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}]
wire can_to_q_1 = heads_1 != tails_1 & _qs_1_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}]
wire can_to_q_2 = heads_2 != tails_2 & _qs_2_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}]
wire can_to_q_3 = heads_3 != tails_3 & _qs_3_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}]
wire can_to_q_4 = heads_4 != tails_4 & _qs_4_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}]
wire can_to_q_5 = heads_5 != tails_5 & _qs_5_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}]
wire can_to_q_6 = heads_6 != tails_6 & _qs_6_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}]
wire can_to_q_7 = heads_7 != tails_7 & _qs_7_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}]
wire can_to_q_8 = heads_8 != tails_8 & _qs_8_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}]
wire can_to_q_9 = heads_9 != tails_9 & _qs_9_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}]
wire [9:0] to_q_oh_enc = can_to_q_0 ? 10'h1 : can_to_q_1 ? 10'h2 : can_to_q_2 ? 10'h4 : can_to_q_3 ? 10'h8 : can_to_q_4 ? 10'h10 : can_to_q_5 ? 10'h20 : can_to_q_6 ? 10'h40 : can_to_q_7 ? 10'h80 : can_to_q_8 ? 10'h100 : {can_to_q_9, 9'h0}; // @[Mux.scala:50:70]
wire _GEN_11 = can_to_q_0 | can_to_q_1 | can_to_q_2 | can_to_q_3 | can_to_q_4 | can_to_q_5 | can_to_q_6 | can_to_q_7 | can_to_q_8 | can_to_q_9; // @[package.scala:81:59]
wire [4:0] head = (to_q_oh_enc[0] ? heads_0 : 5'h0) | (to_q_oh_enc[1] ? heads_1 : 5'h0) | (to_q_oh_enc[2] ? heads_2 : 5'h0) | (to_q_oh_enc[3] ? heads_3 : 5'h0) | (to_q_oh_enc[4] ? heads_4 : 5'h0) | (to_q_oh_enc[5] ? heads_5 : 5'h0) | (to_q_oh_enc[6] ? heads_6 : 5'h0) | (to_q_oh_enc[7] ? heads_7 : 5'h0) | (to_q_oh_enc[8] ? heads_8 : 5'h0) | (to_q_oh_enc[9] ? heads_9 : 5'h0); // @[OneHot.scala:83:30]
wire _GEN_12 = _GEN_11 & to_q_oh_enc[0]; // @[OneHot.scala:83:30]
wire _GEN_13 = _GEN_11 & to_q_oh_enc[1]; // @[OneHot.scala:83:30]
wire _GEN_14 = _GEN_11 & to_q_oh_enc[2]; // @[OneHot.scala:83:30]
wire _GEN_15 = _GEN_11 & to_q_oh_enc[3]; // @[OneHot.scala:83:30]
wire _GEN_16 = _GEN_11 & to_q_oh_enc[4]; // @[OneHot.scala:83:30]
wire _GEN_17 = _GEN_11 & to_q_oh_enc[5]; // @[OneHot.scala:83:30]
wire _GEN_18 = _GEN_11 & to_q_oh_enc[6]; // @[OneHot.scala:83:30]
wire _GEN_19 = _GEN_11 & to_q_oh_enc[7]; // @[OneHot.scala:83:30]
wire _GEN_20 = _GEN_11 & to_q_oh_enc[8]; // @[OneHot.scala:83:30]
wire _GEN_21 = _GEN_11 & to_q_oh_enc[9]; // @[OneHot.scala:83:30]
wire [4:0] _tails_T_61 = _GEN[io_enq_0_bits_virt_channel_id] == ({1'h0, {1'h0, {1'h0, {2{_tails_T_30}}} | {3{_tails_T_31}}} | (_tails_T_33 ? 4'hB : 4'h0) | {4{_tails_T_34}}} | (_tails_T_35 ? 5'h13 : 5'h0) | (_tails_T_37 ? 5'h17 : 5'h0) | (_tails_T_38 ? 5'h1B : 5'h0) | {5{_tails_T_39}}) ? {_tails_T_35, {_tails_T_33, _tails_T_31, 2'h0} | (_tails_T_34 ? 4'hC : 4'h0)} | (_tails_T_37 ? 5'h14 : 5'h0) | (_tails_T_38 ? 5'h18 : 5'h0) | (_tails_T_39 ? 5'h1C : 5'h0) : _GEN[io_enq_0_bits_virt_channel_id] + 5'h1; // @[Mux.scala:30:73, :32:36]
wire [6:0] _to_q_T_2 = {6'h0, to_q_oh_enc[9]} | to_q_oh_enc[7:1]; // @[OneHot.scala:31:18, :32:28]
wire [2:0] _to_q_T_4 = _to_q_T_2[6:4] | _to_q_T_2[2:0]; // @[OneHot.scala:30:18, :31:18, :32:28]
wire _to_q_T_6 = _to_q_T_4[2] | _to_q_T_4[0]; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [3:0] to_q = {|(to_q_oh_enc[9:8]), |(_to_q_T_2[6:3]), |(_to_q_T_4[2:1]), _to_q_T_6}; // @[OneHot.scala:30:18, :32:{10,14,28}]
wire [4:0] _heads_T_41 = head == ({1'h0, {1'h0, {1'h0, {2{to_q_oh_enc[0]}}} | {3{to_q_oh_enc[1]}}} | (to_q_oh_enc[3] ? 4'hB : 4'h0) | {4{to_q_oh_enc[4]}}} | (to_q_oh_enc[5] ? 5'h13 : 5'h0) | (to_q_oh_enc[7] ? 5'h17 : 5'h0) | (to_q_oh_enc[8] ? 5'h1B : 5'h0) | {5{to_q_oh_enc[9]}}) ? {to_q_oh_enc[5], {to_q_oh_enc[3], to_q_oh_enc[1], 2'h0} | (to_q_oh_enc[4] ? 4'hC : 4'h0)} | (to_q_oh_enc[7] ? 5'h14 : 5'h0) | (to_q_oh_enc[8] ? 5'h18 : 5'h0) | (to_q_oh_enc[9] ? 5'h1C : 5'h0) : head + 5'h1; // @[OneHot.scala:83:30]
always @(posedge clock) begin // @[InputUnit.scala:49:7]
if (reset) begin // @[InputUnit.scala:49:7]
heads_0 <= 5'h0; // @[InputUnit.scala:86:24]
heads_1 <= 5'h4; // @[InputUnit.scala:86:24]
heads_2 <= 5'h0; // @[InputUnit.scala:86:24]
heads_3 <= 5'h8; // @[InputUnit.scala:86:24]
heads_4 <= 5'hC; // @[InputUnit.scala:86:24]
heads_5 <= 5'h10; // @[InputUnit.scala:86:24]
heads_6 <= 5'h0; // @[InputUnit.scala:86:24]
heads_7 <= 5'h14; // @[InputUnit.scala:86:24]
heads_8 <= 5'h18; // @[InputUnit.scala:86:24]
heads_9 <= 5'h1C; // @[InputUnit.scala:86:24]
tails_0 <= 5'h0; // @[InputUnit.scala:87:24]
tails_1 <= 5'h4; // @[InputUnit.scala:87:24]
tails_2 <= 5'h0; // @[InputUnit.scala:87:24]
tails_3 <= 5'h8; // @[InputUnit.scala:87:24]
tails_4 <= 5'hC; // @[InputUnit.scala:87:24]
tails_5 <= 5'h10; // @[InputUnit.scala:87:24]
tails_6 <= 5'h0; // @[InputUnit.scala:87:24]
tails_7 <= 5'h14; // @[InputUnit.scala:87:24]
tails_8 <= 5'h18; // @[InputUnit.scala:87:24]
tails_9 <= 5'h1C; // @[InputUnit.scala:87:24]
end
else begin // @[InputUnit.scala:49:7]
if (_GEN_11 & {to_q_oh_enc[9:8], |(_to_q_T_2[6:3]), |(_to_q_T_4[2:1]), _to_q_T_6} == 5'h0) // @[OneHot.scala:30:18, :32:{10,14,28}]
heads_0 <= _heads_T_41; // @[InputUnit.scala:86:24, :122:27]
if (_GEN_11 & to_q == 4'h1) // @[OneHot.scala:32:10]
heads_1 <= _heads_T_41; // @[InputUnit.scala:86:24, :122:27]
if (_GEN_11 & to_q == 4'h2) // @[OneHot.scala:32:10]
heads_2 <= _heads_T_41; // @[InputUnit.scala:86:24, :122:27]
if (_GEN_11 & to_q == 4'h3) // @[OneHot.scala:32:10]
heads_3 <= _heads_T_41; // @[InputUnit.scala:86:24, :122:27]
if (_GEN_11 & to_q == 4'h4) // @[OneHot.scala:32:10]
heads_4 <= _heads_T_41; // @[InputUnit.scala:86:24, :122:27]
if (_GEN_11 & to_q == 4'h5) // @[OneHot.scala:32:10]
heads_5 <= _heads_T_41; // @[InputUnit.scala:86:24, :122:27]
if (_GEN_11 & to_q == 4'h6) // @[OneHot.scala:32:10]
heads_6 <= _heads_T_41; // @[InputUnit.scala:86:24, :122:27]
if (_GEN_11 & to_q == 4'h7) // @[OneHot.scala:32:10]
heads_7 <= _heads_T_41; // @[InputUnit.scala:86:24, :122:27]
if (_GEN_11 & to_q == 4'h8) // @[OneHot.scala:32:10]
heads_8 <= _heads_T_41; // @[InputUnit.scala:86:24, :122:27]
if (_GEN_11 & to_q == 4'h9) // @[OneHot.scala:32:10]
heads_9 <= _heads_T_41; // @[InputUnit.scala:86:24, :122:27]
if (mem_MPORT_en & _GEN_0) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45]
tails_0 <= _tails_T_61; // @[InputUnit.scala:87:24, :103:51]
if (mem_MPORT_en & _GEN_1) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45]
tails_1 <= _tails_T_61; // @[InputUnit.scala:87:24, :103:51]
if (mem_MPORT_en & _GEN_2) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45]
tails_2 <= _tails_T_61; // @[InputUnit.scala:87:24, :103:51]
if (mem_MPORT_en & _GEN_3) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45]
tails_3 <= _tails_T_61; // @[InputUnit.scala:87:24, :103:51]
if (mem_MPORT_en & _GEN_4) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45]
tails_4 <= _tails_T_61; // @[InputUnit.scala:87:24, :103:51]
if (mem_MPORT_en & _GEN_5) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45]
tails_5 <= _tails_T_61; // @[InputUnit.scala:87:24, :103:51]
if (mem_MPORT_en & _GEN_6) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45]
tails_6 <= _tails_T_61; // @[InputUnit.scala:87:24, :103:51]
if (mem_MPORT_en & _GEN_7) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45]
tails_7 <= _tails_T_61; // @[InputUnit.scala:87:24, :103:51]
if (mem_MPORT_en & _GEN_8) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45]
tails_8 <= _tails_T_61; // @[InputUnit.scala:87:24, :103:51]
if (mem_MPORT_en & _GEN_9) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45]
tails_9 <= _tails_T_61; // @[InputUnit.scala:87:24, :103:51]
end
always @(posedge) |
Generate the Verilog code corresponding to the following Chisel files.
File IngressUnit.scala:
package constellation.router
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.util._
import constellation.channel._
class IngressUnit(
ingressNodeId: Int,
cParam: IngressChannelParams,
outParams: Seq[ChannelParams],
egressParams: Seq[EgressChannelParams],
combineRCVA: Boolean,
combineSAST: Boolean,
)
(implicit p: Parameters) extends AbstractInputUnit(cParam, outParams, egressParams)(p) {
class IngressUnitIO extends AbstractInputUnitIO(cParam, outParams, egressParams) {
val in = Flipped(Decoupled(new IngressFlit(cParam.payloadBits)))
}
val io = IO(new IngressUnitIO)
val route_buffer = Module(new Queue(new Flit(cParam.payloadBits), 2))
val route_q = Module(new Queue(new RouteComputerResp(outParams, egressParams), 2,
flow=combineRCVA))
assert(!(io.in.valid && !cParam.possibleFlows.toSeq.map(_.egressId.U === io.in.bits.egress_id).orR))
route_buffer.io.enq.bits.head := io.in.bits.head
route_buffer.io.enq.bits.tail := io.in.bits.tail
val flows = cParam.possibleFlows.toSeq
if (flows.size == 0) {
route_buffer.io.enq.bits.flow := DontCare
} else {
route_buffer.io.enq.bits.flow.ingress_node := cParam.destId.U
route_buffer.io.enq.bits.flow.ingress_node_id := ingressNodeId.U
route_buffer.io.enq.bits.flow.vnet_id := cParam.vNetId.U
route_buffer.io.enq.bits.flow.egress_node := Mux1H(
flows.map(_.egressId.U === io.in.bits.egress_id),
flows.map(_.egressNode.U)
)
route_buffer.io.enq.bits.flow.egress_node_id := Mux1H(
flows.map(_.egressId.U === io.in.bits.egress_id),
flows.map(_.egressNodeId.U)
)
}
route_buffer.io.enq.bits.payload := io.in.bits.payload
route_buffer.io.enq.bits.virt_channel_id := DontCare
io.router_req.bits.src_virt_id := 0.U
io.router_req.bits.flow := route_buffer.io.enq.bits.flow
val at_dest = route_buffer.io.enq.bits.flow.egress_node === nodeId.U
route_buffer.io.enq.valid := io.in.valid && (
io.router_req.ready || !io.in.bits.head || at_dest)
io.router_req.valid := io.in.valid && route_buffer.io.enq.ready && io.in.bits.head && !at_dest
io.in.ready := route_buffer.io.enq.ready && (
io.router_req.ready || !io.in.bits.head || at_dest)
route_q.io.enq.valid := io.router_req.fire
route_q.io.enq.bits := io.router_resp
when (io.in.fire && io.in.bits.head && at_dest) {
route_q.io.enq.valid := true.B
route_q.io.enq.bits.vc_sel.foreach(_.foreach(_ := false.B))
for (o <- 0 until nEgress) {
when (egressParams(o).egressId.U === io.in.bits.egress_id) {
route_q.io.enq.bits.vc_sel(o+nOutputs)(0) := true.B
}
}
}
assert(!(route_q.io.enq.valid && !route_q.io.enq.ready))
val vcalloc_buffer = Module(new Queue(new Flit(cParam.payloadBits), 2))
val vcalloc_q = Module(new Queue(new VCAllocResp(outParams, egressParams),
1, pipe=true))
vcalloc_buffer.io.enq.bits := route_buffer.io.deq.bits
io.vcalloc_req.bits.vc_sel := route_q.io.deq.bits.vc_sel
io.vcalloc_req.bits.flow := route_buffer.io.deq.bits.flow
io.vcalloc_req.bits.in_vc := 0.U
val head = route_buffer.io.deq.bits.head
val tail = route_buffer.io.deq.bits.tail
vcalloc_buffer.io.enq.valid := (route_buffer.io.deq.valid &&
(route_q.io.deq.valid || !head) &&
(io.vcalloc_req.ready || !head)
)
io.vcalloc_req.valid := (route_buffer.io.deq.valid && route_q.io.deq.valid &&
head && vcalloc_buffer.io.enq.ready && vcalloc_q.io.enq.ready)
route_buffer.io.deq.ready := (vcalloc_buffer.io.enq.ready &&
(route_q.io.deq.valid || !head) &&
(io.vcalloc_req.ready || !head) &&
(vcalloc_q.io.enq.ready || !head))
route_q.io.deq.ready := (route_buffer.io.deq.fire && tail)
vcalloc_q.io.enq.valid := io.vcalloc_req.fire
vcalloc_q.io.enq.bits := io.vcalloc_resp
assert(!(vcalloc_q.io.enq.valid && !vcalloc_q.io.enq.ready))
io.salloc_req(0).bits.vc_sel := vcalloc_q.io.deq.bits.vc_sel
io.salloc_req(0).bits.tail := vcalloc_buffer.io.deq.bits.tail
val c = (vcalloc_q.io.deq.bits.vc_sel.asUInt & io.out_credit_available.asUInt) =/= 0.U
val vcalloc_tail = vcalloc_buffer.io.deq.bits.tail
io.salloc_req(0).valid := vcalloc_buffer.io.deq.valid && vcalloc_q.io.deq.valid && c && !io.block
vcalloc_buffer.io.deq.ready := io.salloc_req(0).ready && vcalloc_q.io.deq.valid && c && !io.block
vcalloc_q.io.deq.ready := vcalloc_tail && vcalloc_buffer.io.deq.fire
val out_bundle = if (combineSAST) {
Wire(Valid(new SwitchBundle(outParams, egressParams)))
} else {
Reg(Valid(new SwitchBundle(outParams, egressParams)))
}
io.out(0) := out_bundle
out_bundle.valid := vcalloc_buffer.io.deq.fire
out_bundle.bits.flit := vcalloc_buffer.io.deq.bits
out_bundle.bits.flit.virt_channel_id := 0.U
val out_channel_oh = vcalloc_q.io.deq.bits.vc_sel.map(_.reduce(_||_)).toSeq
out_bundle.bits.out_virt_channel := Mux1H(out_channel_oh,
vcalloc_q.io.deq.bits.vc_sel.map(v => OHToUInt(v)).toSeq)
io.debug.va_stall := io.vcalloc_req.valid && !io.vcalloc_req.ready
io.debug.sa_stall := io.salloc_req(0).valid && !io.salloc_req(0).ready
// TODO: We should not generate input/ingress/output/egress units for untraversable channels
if (!cParam.traversable) {
io.in.ready := false.B
io.router_req.valid := false.B
io.router_req.bits := DontCare
io.vcalloc_req.valid := false.B
io.vcalloc_req.bits := DontCare
io.salloc_req.foreach(_.valid := false.B)
io.salloc_req.foreach(_.bits := DontCare)
io.out.foreach(_.valid := false.B)
io.out.foreach(_.bits := DontCare)
}
}
| module IngressUnit_70( // @[IngressUnit.scala:11:7]
input clock, // @[IngressUnit.scala:11:7]
input reset, // @[IngressUnit.scala:11:7]
output [3:0] io_router_req_bits_flow_egress_node, // @[IngressUnit.scala:24:14]
output [2:0] io_router_req_bits_flow_egress_node_id, // @[IngressUnit.scala:24:14]
input io_router_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14]
input io_router_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14]
input io_router_resp_vc_sel_0_2, // @[IngressUnit.scala:24:14]
input io_router_resp_vc_sel_0_3, // @[IngressUnit.scala:24:14]
input io_router_resp_vc_sel_0_4, // @[IngressUnit.scala:24:14]
input io_router_resp_vc_sel_0_5, // @[IngressUnit.scala:24:14]
input io_router_resp_vc_sel_0_6, // @[IngressUnit.scala:24:14]
input io_router_resp_vc_sel_0_7, // @[IngressUnit.scala:24:14]
input io_router_resp_vc_sel_0_8, // @[IngressUnit.scala:24:14]
input io_router_resp_vc_sel_0_9, // @[IngressUnit.scala:24:14]
input io_vcalloc_req_ready, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_valid, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_4, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_5, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_6, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_7, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_8, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_9, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_2_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_1_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_2, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_3, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_4, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_5, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_6, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_7, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_8, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_9, // @[IngressUnit.scala:24:14]
input io_out_credit_available_2_0, // @[IngressUnit.scala:24:14]
input io_out_credit_available_1_0, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_8, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_9, // @[IngressUnit.scala:24:14]
input io_salloc_req_0_ready, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_valid, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_4, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_5, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_6, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_7, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_8, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_9, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_tail, // @[IngressUnit.scala:24:14]
output io_out_0_valid, // @[IngressUnit.scala:24:14]
output io_out_0_bits_flit_head, // @[IngressUnit.scala:24:14]
output io_out_0_bits_flit_tail, // @[IngressUnit.scala:24:14]
output [72:0] io_out_0_bits_flit_payload, // @[IngressUnit.scala:24:14]
output [2:0] io_out_0_bits_flit_flow_vnet_id, // @[IngressUnit.scala:24:14]
output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[IngressUnit.scala:24:14]
output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[IngressUnit.scala:24:14]
output [3:0] io_out_0_bits_flit_flow_egress_node, // @[IngressUnit.scala:24:14]
output [2:0] io_out_0_bits_flit_flow_egress_node_id, // @[IngressUnit.scala:24:14]
output [3:0] io_out_0_bits_out_virt_channel, // @[IngressUnit.scala:24:14]
output io_in_ready, // @[IngressUnit.scala:24:14]
input io_in_valid, // @[IngressUnit.scala:24:14]
input io_in_bits_head, // @[IngressUnit.scala:24:14]
input io_in_bits_tail, // @[IngressUnit.scala:24:14]
input [72:0] io_in_bits_payload, // @[IngressUnit.scala:24:14]
input [4:0] io_in_bits_egress_id // @[IngressUnit.scala:24:14]
);
wire _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_valid; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_2_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_1_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_1; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_2; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_3; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_4; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_5; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_6; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_7; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_8; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_9; // @[IngressUnit.scala:76:25]
wire _vcalloc_buffer_io_enq_ready; // @[IngressUnit.scala:75:30]
wire _vcalloc_buffer_io_deq_valid; // @[IngressUnit.scala:75:30]
wire _vcalloc_buffer_io_deq_bits_head; // @[IngressUnit.scala:75:30]
wire _vcalloc_buffer_io_deq_bits_tail; // @[IngressUnit.scala:75:30]
wire [72:0] _vcalloc_buffer_io_deq_bits_payload; // @[IngressUnit.scala:75:30]
wire [2:0] _vcalloc_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:75:30]
wire [3:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:75:30]
wire [1:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:75:30]
wire [3:0] _vcalloc_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:75:30]
wire [2:0] _vcalloc_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:75:30]
wire _route_q_io_enq_ready; // @[IngressUnit.scala:27:23]
wire _route_q_io_deq_valid; // @[IngressUnit.scala:27:23]
wire _route_buffer_io_enq_ready; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_deq_valid; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_deq_bits_head; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_deq_bits_tail; // @[IngressUnit.scala:26:28]
wire [72:0] _route_buffer_io_deq_bits_payload; // @[IngressUnit.scala:26:28]
wire [2:0] _route_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:26:28]
wire [3:0] _route_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:26:28]
wire [1:0] _route_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:26:28]
wire [3:0] _route_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:26:28]
wire [2:0] _route_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:26:28]
wire [3:0] _route_buffer_io_deq_bits_virt_channel_id; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T = io_in_bits_egress_id == 5'hE; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = io_in_bits_egress_id == 5'h14; // @[IngressUnit.scala:30:72]
wire [3:0] route_buffer_io_enq_bits_flow_egress_node = {1'h0, _route_buffer_io_enq_bits_flow_egress_node_id_T, 2'h0}; // @[IngressUnit.scala:11:7, :30:72, :41:50]
wire [2:0] route_buffer_io_enq_bits_flow_egress_node_id = {1'h0, {2{_route_buffer_io_enq_bits_flow_egress_node_id_T_1}}}; // @[Mux.scala:30:73]
wire _io_router_req_valid_T_1 = io_in_valid & _route_buffer_io_enq_ready & io_in_bits_head; // @[IngressUnit.scala:26:28, :58:{38,67}]
wire io_vcalloc_req_valid_0 = _route_buffer_io_deq_valid & _route_q_io_deq_valid & _route_buffer_io_deq_bits_head & _vcalloc_buffer_io_enq_ready & _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :91:{54,78}, :92:{10,41}]
wire route_buffer_io_deq_ready = _vcalloc_buffer_io_enq_ready & (_route_q_io_deq_valid | ~_route_buffer_io_deq_bits_head) & (io_vcalloc_req_ready | ~_route_buffer_io_deq_bits_head) & (_vcalloc_q_io_enq_ready | ~_route_buffer_io_deq_bits_head); // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :88:30, :93:61, :94:{27,37}, :95:{27,37}, :96:29]
wire vcalloc_q_io_enq_valid = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35] |
Generate the Verilog code corresponding to the following Chisel files.
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Nodes.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection}
case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args))
object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
{
def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo)
def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo)
def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle)
def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle)
def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString)
override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = {
val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge)))
monitor.io.in := bundle
}
override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters =
pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })
override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters =
pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })
}
trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut]
case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode
case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode
case class TLAdapterNode(
clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s },
managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLJunctionNode(
clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters],
managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])(
implicit valName: ValName)
extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode
object TLNameNode {
def apply(name: ValName) = TLIdentityNode()(name)
def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLIdentityNode = apply(Some(name))
}
case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)()
object TLTempNode {
def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp"))
}
case class TLNexusNode(
clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters,
managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)(
implicit valName: ValName)
extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode
abstract class TLCustomNode(implicit valName: ValName)
extends CustomNode(TLImp) with TLFormatNode
// Asynchronous crossings
trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters]
object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle]
{
def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle)
def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString)
override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLAsyncAdapterNode(
clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s },
managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode
case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode
object TLAsyncNameNode {
def apply(name: ValName) = TLAsyncIdentityNode()(name)
def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLAsyncIdentityNode = apply(Some(name))
}
case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLAsyncImp)(
dFn = { p => TLAsyncClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain
case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName)
extends MixedAdapterNode(TLAsyncImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) },
uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut]
// Rationally related crossings
trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters]
object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle]
{
def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle)
def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */)
override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLRationalAdapterNode(
clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s },
managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode
case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode
object TLRationalNameNode {
def apply(name: ValName) = TLRationalIdentityNode()(name)
def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLRationalIdentityNode = apply(Some(name))
}
case class TLRationalSourceNode()(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLRationalImp)(
dFn = { p => TLRationalClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain
case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName)
extends MixedAdapterNode(TLRationalImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut]
// Credited version of TileLink channels
trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters]
object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle]
{
def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle)
def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString)
override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLCreditedAdapterNode(
clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s },
managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode
case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode
object TLCreditedNameNode {
def apply(name: ValName) = TLCreditedIdentityNode()(name)
def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLCreditedIdentityNode = apply(Some(name))
}
case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLCreditedImp)(
dFn = { p => TLCreditedClientPortParameters(delay, p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain
case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLCreditedImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut]
File Bundles.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import freechips.rocketchip.util._
import scala.collection.immutable.ListMap
import chisel3.util.Decoupled
import chisel3.util.DecoupledIO
import chisel3.reflect.DataMirror
abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle
// common combos in lazy policy:
// Put + Acquire
// Release + AccessAck
object TLMessages
{
// A B C D E
def PutFullData = 0.U // . . => AccessAck
def PutPartialData = 1.U // . . => AccessAck
def ArithmeticData = 2.U // . . => AccessAckData
def LogicalData = 3.U // . . => AccessAckData
def Get = 4.U // . . => AccessAckData
def Hint = 5.U // . . => HintAck
def AcquireBlock = 6.U // . => Grant[Data]
def AcquirePerm = 7.U // . => Grant[Data]
def Probe = 6.U // . => ProbeAck[Data]
def AccessAck = 0.U // . .
def AccessAckData = 1.U // . .
def HintAck = 2.U // . .
def ProbeAck = 4.U // .
def ProbeAckData = 5.U // .
def Release = 6.U // . => ReleaseAck
def ReleaseData = 7.U // . => ReleaseAck
def Grant = 4.U // . => GrantAck
def GrantData = 5.U // . => GrantAck
def ReleaseAck = 6.U // .
def GrantAck = 0.U // .
def isA(x: UInt) = x <= AcquirePerm
def isB(x: UInt) = x <= Probe
def isC(x: UInt) = x <= ReleaseData
def isD(x: UInt) = x <= ReleaseAck
def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant)
def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck)
def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("AcquireBlock",TLPermissions.PermMsgGrow),
("AcquirePerm",TLPermissions.PermMsgGrow))
def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("Probe",TLPermissions.PermMsgCap))
def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("ProbeAck",TLPermissions.PermMsgReport),
("ProbeAckData",TLPermissions.PermMsgReport),
("Release",TLPermissions.PermMsgReport),
("ReleaseData",TLPermissions.PermMsgReport))
def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("Grant",TLPermissions.PermMsgCap),
("GrantData",TLPermissions.PermMsgCap),
("ReleaseAck",TLPermissions.PermMsgReserved))
}
/**
* The three primary TileLink permissions are:
* (T)runk: the agent is (or is on inwards path to) the global point of serialization.
* (B)ranch: the agent is on an outwards path to
* (N)one:
* These permissions are permuted by transfer operations in various ways.
* Operations can cap permissions, request for them to be grown or shrunk,
* or for a report on their current status.
*/
object TLPermissions
{
val aWidth = 2
val bdWidth = 2
val cWidth = 3
// Cap types (Grant = new permissions, Probe = permisions <= target)
def toT = 0.U(bdWidth.W)
def toB = 1.U(bdWidth.W)
def toN = 2.U(bdWidth.W)
def isCap(x: UInt) = x <= toN
// Grow types (Acquire = permissions >= target)
def NtoB = 0.U(aWidth.W)
def NtoT = 1.U(aWidth.W)
def BtoT = 2.U(aWidth.W)
def isGrow(x: UInt) = x <= BtoT
// Shrink types (ProbeAck, Release)
def TtoB = 0.U(cWidth.W)
def TtoN = 1.U(cWidth.W)
def BtoN = 2.U(cWidth.W)
def isShrink(x: UInt) = x <= BtoN
// Report types (ProbeAck, Release)
def TtoT = 3.U(cWidth.W)
def BtoB = 4.U(cWidth.W)
def NtoN = 5.U(cWidth.W)
def isReport(x: UInt) = x <= NtoN
def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT")
def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN")
def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN")
def PermMsgReserved:Seq[String] = Seq("Reserved")
}
object TLAtomics
{
val width = 3
// Arithmetic types
def MIN = 0.U(width.W)
def MAX = 1.U(width.W)
def MINU = 2.U(width.W)
def MAXU = 3.U(width.W)
def ADD = 4.U(width.W)
def isArithmetic(x: UInt) = x <= ADD
// Logical types
def XOR = 0.U(width.W)
def OR = 1.U(width.W)
def AND = 2.U(width.W)
def SWAP = 3.U(width.W)
def isLogical(x: UInt) = x <= SWAP
def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD")
def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP")
}
object TLHints
{
val width = 1
def PREFETCH_READ = 0.U(width.W)
def PREFETCH_WRITE = 1.U(width.W)
def isHints(x: UInt) = x <= PREFETCH_WRITE
def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite")
}
sealed trait TLChannel extends TLBundleBase {
val channelName: String
}
sealed trait TLDataChannel extends TLChannel
sealed trait TLAddrChannel extends TLDataChannel
final class TLBundleA(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleA_${params.shortName}"
val channelName = "'A' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleB(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleB_${params.shortName}"
val channelName = "'B' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val address = UInt(params.addressBits.W) // from
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleC(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleC_${params.shortName}"
val channelName = "'C' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.cWidth.W) // shrink or report perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleD(params: TLBundleParameters)
extends TLBundleBase(params) with TLDataChannel
{
override def typeName = s"TLBundleD_${params.shortName}"
val channelName = "'D' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val sink = UInt(params.sinkBits.W) // from
val denied = Bool() // implies corrupt iff *Data
val user = BundleMap(params.responseFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleE(params: TLBundleParameters)
extends TLBundleBase(params) with TLChannel
{
override def typeName = s"TLBundleE_${params.shortName}"
val channelName = "'E' channel"
val sink = UInt(params.sinkBits.W) // to
}
class TLBundle(val params: TLBundleParameters) extends Record
{
// Emulate a Bundle with elements abcde or ad depending on params.hasBCE
private val optA = Some (Decoupled(new TLBundleA(params)))
private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params))))
private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params)))
private val optD = Some (Flipped(Decoupled(new TLBundleD(params))))
private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params)))
def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params)))))
def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params)))))
def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params)))))
def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params)))))
def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params)))))
val elements =
if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a)
else ListMap("d" -> d, "a" -> a)
def tieoff(): Unit = {
DataMirror.specifiedDirectionOf(a.ready) match {
case SpecifiedDirection.Input =>
a.ready := false.B
c.ready := false.B
e.ready := false.B
b.valid := false.B
d.valid := false.B
case SpecifiedDirection.Output =>
a.valid := false.B
c.valid := false.B
e.valid := false.B
b.ready := false.B
d.ready := false.B
case _ =>
}
}
}
object TLBundle
{
def apply(params: TLBundleParameters) = new TLBundle(params)
}
class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle
class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params)
{
val a = new AsyncBundle(new TLBundleA(params.base), params.async)
val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async))
val c = new AsyncBundle(new TLBundleC(params.base), params.async)
val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async))
val e = new AsyncBundle(new TLBundleE(params.base), params.async)
}
class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = RationalIO(new TLBundleA(params))
val b = Flipped(RationalIO(new TLBundleB(params)))
val c = RationalIO(new TLBundleC(params))
val d = Flipped(RationalIO(new TLBundleD(params)))
val e = RationalIO(new TLBundleE(params))
}
class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = CreditedIO(new TLBundleA(params))
val b = Flipped(CreditedIO(new TLBundleB(params)))
val c = CreditedIO(new TLBundleC(params))
val d = Flipped(CreditedIO(new TLBundleD(params)))
val e = CreditedIO(new TLBundleE(params))
}
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File TLSerdes.scala:
package testchipip.serdes
import chisel3._
import chisel3.util._
import freechips.rocketchip.diplomacy._
import org.chipsalliance.cde.config._
import freechips.rocketchip.util._
import freechips.rocketchip.tilelink._
object TLSerdesser {
// This should be the standard bundle type for TLSerdesser
val STANDARD_TLBUNDLE_PARAMS = TLBundleParameters(
addressBits=64, dataBits=64,
sourceBits=8, sinkBits=8, sizeBits=8,
echoFields=Nil, requestFields=Nil, responseFields=Nil,
hasBCE=true)
}
class SerdesDebugIO extends Bundle {
val ser_busy = Output(Bool())
val des_busy = Output(Bool())
}
class TLSerdesser(
val flitWidth: Int,
clientPortParams: Option[TLMasterPortParameters],
managerPortParams: Option[TLSlavePortParameters],
val bundleParams: TLBundleParameters = TLSerdesser.STANDARD_TLBUNDLE_PARAMS,
nameSuffix: Option[String] = None
)
(implicit p: Parameters) extends LazyModule {
require (clientPortParams.isDefined || managerPortParams.isDefined)
val clientNode = clientPortParams.map { c => TLClientNode(Seq(c)) }
val managerNode = managerPortParams.map { m => TLManagerNode(Seq(m)) }
override lazy val desiredName = (Seq("TLSerdesser") ++ nameSuffix).mkString("_")
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
val io = IO(new Bundle {
val ser = Vec(5, new DecoupledFlitIO(flitWidth))
val debug = new SerdesDebugIO
})
val client_tl = clientNode.map(_.out(0)._1).getOrElse(0.U.asTypeOf(new TLBundle(bundleParams)))
val client_edge = clientNode.map(_.out(0)._2)
val manager_tl = managerNode.map(_.in(0)._1).getOrElse(0.U.asTypeOf(new TLBundle(bundleParams)))
val manager_edge = managerNode.map(_.in(0)._2)
val clientParams = client_edge.map(_.bundle).getOrElse(bundleParams)
val managerParams = manager_edge.map(_.bundle).getOrElse(bundleParams)
val mergedParams = clientParams.union(managerParams).union(bundleParams)
require(mergedParams.echoFields.isEmpty, "TLSerdesser does not support TileLink with echo fields")
require(mergedParams.requestFields.isEmpty, "TLSerdesser does not support TileLink with request fields")
require(mergedParams.responseFields.isEmpty, "TLSerdesser does not support TileLink with response fields")
require(mergedParams == bundleParams, s"TLSerdesser is misconfigured, the combined inwards/outwards parameters cannot be serialized using the provided bundle params\n$mergedParams > $bundleParams")
val out_channels = Seq(
(manager_tl.e, manager_edge.map(e => Module(new TLEToBeat(e, mergedParams, nameSuffix)))),
(client_tl.d, client_edge.map (e => Module(new TLDToBeat(e, mergedParams, nameSuffix)))),
(manager_tl.c, manager_edge.map(e => Module(new TLCToBeat(e, mergedParams, nameSuffix)))),
(client_tl.b, client_edge.map (e => Module(new TLBToBeat(e, mergedParams, nameSuffix)))),
(manager_tl.a, manager_edge.map(e => Module(new TLAToBeat(e, mergedParams, nameSuffix))))
)
io.ser.map(_.out.valid := false.B)
io.ser.map(_.out.bits := DontCare)
val out_sers = out_channels.zipWithIndex.map { case ((c,b),i) => b.map { b =>
b.io.protocol <> c
val ser = Module(new GenericSerializer(b.io.beat.bits.cloneType, flitWidth)).suggestName(s"ser_$i")
ser.io.in <> b.io.beat
io.ser(i).out <> ser.io.out
ser
}}.flatten
io.debug.ser_busy := out_sers.map(_.io.busy).orR
val in_channels = Seq(
(client_tl.e, Module(new TLEFromBeat(mergedParams, nameSuffix))),
(manager_tl.d, Module(new TLDFromBeat(mergedParams, nameSuffix))),
(client_tl.c, Module(new TLCFromBeat(mergedParams, nameSuffix))),
(manager_tl.b, Module(new TLBFromBeat(mergedParams, nameSuffix))),
(client_tl.a, Module(new TLAFromBeat(mergedParams, nameSuffix)))
)
val in_desers = in_channels.zipWithIndex.map { case ((c,b),i) =>
c <> b.io.protocol
val des = Module(new GenericDeserializer(b.io.beat.bits.cloneType, flitWidth)).suggestName(s"des_$i")
des.io.in <> io.ser(i).in
b.io.beat <> des.io.out
des
}
io.debug.des_busy := in_desers.map(_.io.busy).orR
}
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
| module TLSerdesser_SerialRAM( // @[TLSerdes.scala:39:9]
input clock, // @[TLSerdes.scala:39:9]
input reset, // @[TLSerdes.scala:39:9]
output auto_manager_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_manager_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_manager_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_manager_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_manager_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input auto_manager_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_manager_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_manager_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_manager_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_manager_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_manager_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_manager_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_manager_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_manager_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_manager_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output auto_manager_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_manager_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_manager_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_manager_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_manager_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output io_ser_0_in_ready, // @[TLSerdes.scala:40:16]
input io_ser_0_in_valid, // @[TLSerdes.scala:40:16]
input [31:0] io_ser_0_in_bits_flit, // @[TLSerdes.scala:40:16]
input io_ser_0_out_ready, // @[TLSerdes.scala:40:16]
output [31:0] io_ser_0_out_bits_flit, // @[TLSerdes.scala:40:16]
output io_ser_1_in_ready, // @[TLSerdes.scala:40:16]
input io_ser_1_in_valid, // @[TLSerdes.scala:40:16]
input [31:0] io_ser_1_in_bits_flit, // @[TLSerdes.scala:40:16]
output io_ser_2_in_ready, // @[TLSerdes.scala:40:16]
input io_ser_2_in_valid, // @[TLSerdes.scala:40:16]
input [31:0] io_ser_2_in_bits_flit, // @[TLSerdes.scala:40:16]
input io_ser_2_out_ready, // @[TLSerdes.scala:40:16]
output io_ser_2_out_valid, // @[TLSerdes.scala:40:16]
output [31:0] io_ser_2_out_bits_flit, // @[TLSerdes.scala:40:16]
output io_ser_3_in_ready, // @[TLSerdes.scala:40:16]
input io_ser_3_in_valid, // @[TLSerdes.scala:40:16]
input [31:0] io_ser_3_in_bits_flit, // @[TLSerdes.scala:40:16]
output io_ser_4_in_ready, // @[TLSerdes.scala:40:16]
input io_ser_4_in_valid, // @[TLSerdes.scala:40:16]
input [31:0] io_ser_4_in_bits_flit, // @[TLSerdes.scala:40:16]
input io_ser_4_out_ready, // @[TLSerdes.scala:40:16]
output io_ser_4_out_valid, // @[TLSerdes.scala:40:16]
output [31:0] io_ser_4_out_bits_flit // @[TLSerdes.scala:40:16]
);
wire _des_4_io_out_valid; // @[TLSerdes.scala:86:23]
wire [85:0] _des_4_io_out_bits_payload; // @[TLSerdes.scala:86:23]
wire _des_4_io_out_bits_head; // @[TLSerdes.scala:86:23]
wire _des_4_io_out_bits_tail; // @[TLSerdes.scala:86:23]
wire _des_4_io_busy; // @[TLSerdes.scala:86:23]
wire _des_3_io_out_valid; // @[TLSerdes.scala:86:23]
wire [84:0] _des_3_io_out_bits_payload; // @[TLSerdes.scala:86:23]
wire _des_3_io_out_bits_head; // @[TLSerdes.scala:86:23]
wire _des_3_io_out_bits_tail; // @[TLSerdes.scala:86:23]
wire _des_3_io_busy; // @[TLSerdes.scala:86:23]
wire _des_2_io_out_valid; // @[TLSerdes.scala:86:23]
wire [85:0] _des_2_io_out_bits_payload; // @[TLSerdes.scala:86:23]
wire _des_2_io_out_bits_head; // @[TLSerdes.scala:86:23]
wire _des_2_io_out_bits_tail; // @[TLSerdes.scala:86:23]
wire _des_2_io_busy; // @[TLSerdes.scala:86:23]
wire _des_1_io_out_valid; // @[TLSerdes.scala:86:23]
wire [64:0] _des_1_io_out_bits_payload; // @[TLSerdes.scala:86:23]
wire _des_1_io_out_bits_head; // @[TLSerdes.scala:86:23]
wire _des_1_io_out_bits_tail; // @[TLSerdes.scala:86:23]
wire _des_0_io_out_valid; // @[TLSerdes.scala:86:23]
wire [7:0] _des_0_io_out_bits_payload; // @[TLSerdes.scala:86:23]
wire _des_0_io_out_bits_head; // @[TLSerdes.scala:86:23]
wire _des_0_io_out_bits_tail; // @[TLSerdes.scala:86:23]
wire _in_channels_4_2_io_beat_ready; // @[TLSerdes.scala:82:28]
wire [7:0] _in_channels_3_2_io_protocol_bits_size; // @[TLSerdes.scala:81:28]
wire [7:0] _in_channels_3_2_io_protocol_bits_source; // @[TLSerdes.scala:81:28]
wire [63:0] _in_channels_3_2_io_protocol_bits_address; // @[TLSerdes.scala:81:28]
wire _in_channels_3_2_io_beat_ready; // @[TLSerdes.scala:81:28]
wire _in_channels_2_2_io_beat_ready; // @[TLSerdes.scala:80:28]
wire [7:0] _in_channels_1_2_io_protocol_bits_size; // @[TLSerdes.scala:79:28]
wire [7:0] _in_channels_1_2_io_protocol_bits_source; // @[TLSerdes.scala:79:28]
wire [7:0] _in_channels_1_2_io_protocol_bits_sink; // @[TLSerdes.scala:79:28]
wire _in_channels_1_2_io_beat_ready; // @[TLSerdes.scala:79:28]
wire _in_channels_0_2_io_beat_ready; // @[TLSerdes.scala:78:28]
wire _ser_4_io_in_ready; // @[TLSerdes.scala:69:23]
wire _ser_4_io_busy; // @[TLSerdes.scala:69:23]
wire _ser_2_io_in_ready; // @[TLSerdes.scala:69:23]
wire _ser_0_io_in_ready; // @[TLSerdes.scala:69:23]
wire _out_channels_4_2_io_beat_valid; // @[TLSerdes.scala:63:50]
wire [85:0] _out_channels_4_2_io_beat_bits_payload; // @[TLSerdes.scala:63:50]
wire _out_channels_4_2_io_beat_bits_head; // @[TLSerdes.scala:63:50]
wire _out_channels_4_2_io_beat_bits_tail; // @[TLSerdes.scala:63:50]
wire _out_channels_2_2_io_beat_bits_head; // @[TLSerdes.scala:61:50]
wire _out_channels_0_2_io_beat_bits_head; // @[TLSerdes.scala:59:50]
wire auto_manager_in_a_valid_0 = auto_manager_in_a_valid; // @[TLSerdes.scala:39:9]
wire [2:0] auto_manager_in_a_bits_opcode_0 = auto_manager_in_a_bits_opcode; // @[TLSerdes.scala:39:9]
wire [2:0] auto_manager_in_a_bits_param_0 = auto_manager_in_a_bits_param; // @[TLSerdes.scala:39:9]
wire [3:0] auto_manager_in_a_bits_size_0 = auto_manager_in_a_bits_size; // @[TLSerdes.scala:39:9]
wire auto_manager_in_a_bits_source_0 = auto_manager_in_a_bits_source; // @[TLSerdes.scala:39:9]
wire [31:0] auto_manager_in_a_bits_address_0 = auto_manager_in_a_bits_address; // @[TLSerdes.scala:39:9]
wire [7:0] auto_manager_in_a_bits_mask_0 = auto_manager_in_a_bits_mask; // @[TLSerdes.scala:39:9]
wire [63:0] auto_manager_in_a_bits_data_0 = auto_manager_in_a_bits_data; // @[TLSerdes.scala:39:9]
wire auto_manager_in_a_bits_corrupt_0 = auto_manager_in_a_bits_corrupt; // @[TLSerdes.scala:39:9]
wire auto_manager_in_d_ready_0 = auto_manager_in_d_ready; // @[TLSerdes.scala:39:9]
wire io_ser_0_in_valid_0 = io_ser_0_in_valid; // @[TLSerdes.scala:39:9]
wire [31:0] io_ser_0_in_bits_flit_0 = io_ser_0_in_bits_flit; // @[TLSerdes.scala:39:9]
wire io_ser_0_out_ready_0 = io_ser_0_out_ready; // @[TLSerdes.scala:39:9]
wire io_ser_1_in_valid_0 = io_ser_1_in_valid; // @[TLSerdes.scala:39:9]
wire [31:0] io_ser_1_in_bits_flit_0 = io_ser_1_in_bits_flit; // @[TLSerdes.scala:39:9]
wire io_ser_2_in_valid_0 = io_ser_2_in_valid; // @[TLSerdes.scala:39:9]
wire [31:0] io_ser_2_in_bits_flit_0 = io_ser_2_in_bits_flit; // @[TLSerdes.scala:39:9]
wire io_ser_2_out_ready_0 = io_ser_2_out_ready; // @[TLSerdes.scala:39:9]
wire io_ser_3_in_valid_0 = io_ser_3_in_valid; // @[TLSerdes.scala:39:9]
wire [31:0] io_ser_3_in_bits_flit_0 = io_ser_3_in_bits_flit; // @[TLSerdes.scala:39:9]
wire io_ser_4_in_valid_0 = io_ser_4_in_valid; // @[TLSerdes.scala:39:9]
wire [31:0] io_ser_4_in_bits_flit_0 = io_ser_4_in_bits_flit; // @[TLSerdes.scala:39:9]
wire io_ser_4_out_ready_0 = io_ser_4_out_ready; // @[TLSerdes.scala:39:9]
wire [2:0] client_tl_b_bits_opcode = 3'h0; // @[TLSerdes.scala:45:71]
wire [2:0] client_tl_d_bits_opcode = 3'h0; // @[TLSerdes.scala:45:71]
wire [2:0] _out_channels_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _out_channels_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] out_channels_2_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] out_channels_2_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _in_channels_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [1:0] client_tl_b_bits_param = 2'h0; // @[TLSerdes.scala:45:71]
wire [1:0] client_tl_d_bits_param = 2'h0; // @[TLSerdes.scala:45:71]
wire [1:0] _in_channels_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [3:0] _out_channels_WIRE_bits_sink = 4'h0; // @[Bundles.scala:267:74]
wire [3:0] out_channels_0_1_bits_sink = 4'h0; // @[Bundles.scala:267:61]
wire [3:0] _out_channels_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] out_channels_2_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _in_channels_WIRE_bits_size = 4'h0; // @[Bundles.scala:264:74]
wire [7:0] client_tl_b_bits_size = 8'h0; // @[TLSerdes.scala:45:71]
wire [7:0] client_tl_b_bits_source = 8'h0; // @[TLSerdes.scala:45:71]
wire [7:0] client_tl_b_bits_mask = 8'h0; // @[TLSerdes.scala:45:71]
wire [7:0] client_tl_d_bits_size = 8'h0; // @[TLSerdes.scala:45:71]
wire [7:0] client_tl_d_bits_source = 8'h0; // @[TLSerdes.scala:45:71]
wire [7:0] client_tl_d_bits_sink = 8'h0; // @[TLSerdes.scala:45:71]
wire [7:0] _in_channels_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74]
wire [63:0] client_tl_b_bits_address = 64'h0; // @[TLSerdes.scala:45:71]
wire [63:0] client_tl_b_bits_data = 64'h0; // @[TLSerdes.scala:45:71]
wire [63:0] client_tl_d_bits_data = 64'h0; // @[TLSerdes.scala:45:71]
wire [63:0] _out_channels_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] out_channels_2_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _in_channels_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74]
wire [31:0] io_ser_1_out_bits_flit = 32'h0; // @[TLSerdes.scala:39:9]
wire [31:0] io_ser_3_out_bits_flit = 32'h0; // @[TLSerdes.scala:39:9]
wire [31:0] _out_channels_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] out_channels_2_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _in_channels_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74]
wire io_ser_1_out_ready = 1'h1; // @[TLSerdes.scala:39:9, :40:16, :59:50, :61:50]
wire io_ser_3_out_ready = 1'h1; // @[TLSerdes.scala:39:9, :40:16, :59:50, :61:50]
wire out_channels_0_1_ready = 1'h1; // @[TLSerdes.scala:39:9, :40:16, :59:50, :61:50]
wire out_channels_2_1_ready = 1'h1; // @[TLSerdes.scala:39:9, :40:16, :59:50, :61:50]
wire io_ser_0_out_valid = 1'h0; // @[TLSerdes.scala:39:9]
wire io_ser_1_out_valid = 1'h0; // @[TLSerdes.scala:39:9]
wire io_ser_3_out_valid = 1'h0; // @[TLSerdes.scala:39:9]
wire managerNodeIn_a_ready; // @[MixedNode.scala:551:17]
wire client_tl_a_ready = 1'h0; // @[TLSerdes.scala:45:71]
wire client_tl_b_ready = 1'h0; // @[TLSerdes.scala:45:71]
wire client_tl_b_valid = 1'h0; // @[TLSerdes.scala:45:71]
wire client_tl_b_bits_corrupt = 1'h0; // @[TLSerdes.scala:45:71]
wire client_tl_c_ready = 1'h0; // @[TLSerdes.scala:45:71]
wire client_tl_d_ready = 1'h0; // @[TLSerdes.scala:45:71]
wire client_tl_d_valid = 1'h0; // @[TLSerdes.scala:45:71]
wire client_tl_d_bits_denied = 1'h0; // @[TLSerdes.scala:45:71]
wire client_tl_d_bits_corrupt = 1'h0; // @[TLSerdes.scala:45:71]
wire client_tl_e_ready = 1'h0; // @[TLSerdes.scala:45:71]
wire _out_channels_WIRE_ready = 1'h0; // @[Bundles.scala:267:74]
wire _out_channels_WIRE_valid = 1'h0; // @[Bundles.scala:267:74]
wire out_channels_0_1_valid = 1'h0; // @[Bundles.scala:267:61]
wire _out_channels_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:74]
wire _out_channels_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:74]
wire _out_channels_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _out_channels_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire out_channels_2_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire out_channels_2_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire out_channels_2_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _in_channels_WIRE_ready = 1'h0; // @[Bundles.scala:264:74]
wire _in_channels_WIRE_valid = 1'h0; // @[Bundles.scala:264:74]
wire _in_channels_WIRE_bits_source = 1'h0; // @[Bundles.scala:264:74]
wire _in_channels_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire in_channels_3_1_ready = 1'h0; // @[Bundles.scala:264:61]
wire managerNodeIn_a_valid = auto_manager_in_a_valid_0; // @[TLSerdes.scala:39:9]
wire [2:0] managerNodeIn_a_bits_opcode = auto_manager_in_a_bits_opcode_0; // @[TLSerdes.scala:39:9]
wire [2:0] managerNodeIn_a_bits_param = auto_manager_in_a_bits_param_0; // @[TLSerdes.scala:39:9]
wire [3:0] managerNodeIn_a_bits_size = auto_manager_in_a_bits_size_0; // @[TLSerdes.scala:39:9]
wire managerNodeIn_a_bits_source = auto_manager_in_a_bits_source_0; // @[TLSerdes.scala:39:9]
wire [31:0] managerNodeIn_a_bits_address = auto_manager_in_a_bits_address_0; // @[TLSerdes.scala:39:9]
wire [7:0] managerNodeIn_a_bits_mask = auto_manager_in_a_bits_mask_0; // @[TLSerdes.scala:39:9]
wire [63:0] managerNodeIn_a_bits_data = auto_manager_in_a_bits_data_0; // @[TLSerdes.scala:39:9]
wire managerNodeIn_a_bits_corrupt = auto_manager_in_a_bits_corrupt_0; // @[TLSerdes.scala:39:9]
wire managerNodeIn_d_ready = auto_manager_in_d_ready_0; // @[TLSerdes.scala:39:9]
wire managerNodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] managerNodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] managerNodeIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] managerNodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire managerNodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [3:0] managerNodeIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire managerNodeIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] managerNodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire managerNodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire _io_debug_ser_busy_T_1; // @[package.scala:81:59]
wire _io_debug_des_busy_T_3; // @[package.scala:81:59]
wire auto_manager_in_a_ready_0; // @[TLSerdes.scala:39:9]
wire [2:0] auto_manager_in_d_bits_opcode_0; // @[TLSerdes.scala:39:9]
wire [1:0] auto_manager_in_d_bits_param_0; // @[TLSerdes.scala:39:9]
wire [3:0] auto_manager_in_d_bits_size_0; // @[TLSerdes.scala:39:9]
wire auto_manager_in_d_bits_source_0; // @[TLSerdes.scala:39:9]
wire [3:0] auto_manager_in_d_bits_sink_0; // @[TLSerdes.scala:39:9]
wire auto_manager_in_d_bits_denied_0; // @[TLSerdes.scala:39:9]
wire [63:0] auto_manager_in_d_bits_data_0; // @[TLSerdes.scala:39:9]
wire auto_manager_in_d_bits_corrupt_0; // @[TLSerdes.scala:39:9]
wire auto_manager_in_d_valid_0; // @[TLSerdes.scala:39:9]
wire io_ser_0_in_ready_0; // @[TLSerdes.scala:39:9]
wire [31:0] io_ser_0_out_bits_flit_0; // @[TLSerdes.scala:39:9]
wire io_ser_1_in_ready_0; // @[TLSerdes.scala:39:9]
wire io_ser_2_in_ready_0; // @[TLSerdes.scala:39:9]
wire [31:0] io_ser_2_out_bits_flit_0; // @[TLSerdes.scala:39:9]
wire io_ser_2_out_valid_0; // @[TLSerdes.scala:39:9]
wire io_ser_3_in_ready_0; // @[TLSerdes.scala:39:9]
wire io_ser_4_in_ready_0; // @[TLSerdes.scala:39:9]
wire [31:0] io_ser_4_out_bits_flit_0; // @[TLSerdes.scala:39:9]
wire io_ser_4_out_valid_0; // @[TLSerdes.scala:39:9]
wire io_debug_ser_busy; // @[TLSerdes.scala:39:9]
wire io_debug_des_busy; // @[TLSerdes.scala:39:9]
assign auto_manager_in_a_ready_0 = managerNodeIn_a_ready; // @[TLSerdes.scala:39:9]
assign auto_manager_in_d_valid_0 = managerNodeIn_d_valid; // @[TLSerdes.scala:39:9]
assign auto_manager_in_d_bits_opcode_0 = managerNodeIn_d_bits_opcode; // @[TLSerdes.scala:39:9]
assign auto_manager_in_d_bits_param_0 = managerNodeIn_d_bits_param; // @[TLSerdes.scala:39:9]
assign auto_manager_in_d_bits_size_0 = managerNodeIn_d_bits_size; // @[TLSerdes.scala:39:9]
assign auto_manager_in_d_bits_source_0 = managerNodeIn_d_bits_source; // @[TLSerdes.scala:39:9]
assign auto_manager_in_d_bits_sink_0 = managerNodeIn_d_bits_sink; // @[TLSerdes.scala:39:9]
assign auto_manager_in_d_bits_denied_0 = managerNodeIn_d_bits_denied; // @[TLSerdes.scala:39:9]
assign auto_manager_in_d_bits_data_0 = managerNodeIn_d_bits_data; // @[TLSerdes.scala:39:9]
assign auto_manager_in_d_bits_corrupt_0 = managerNodeIn_d_bits_corrupt; // @[TLSerdes.scala:39:9]
wire [2:0] client_tl_a_bits_opcode; // @[TLSerdes.scala:45:71]
wire [2:0] client_tl_a_bits_param; // @[TLSerdes.scala:45:71]
wire [7:0] client_tl_a_bits_size; // @[TLSerdes.scala:45:71]
wire [7:0] client_tl_a_bits_source; // @[TLSerdes.scala:45:71]
wire [63:0] client_tl_a_bits_address; // @[TLSerdes.scala:45:71]
wire [7:0] client_tl_a_bits_mask; // @[TLSerdes.scala:45:71]
wire [63:0] client_tl_a_bits_data; // @[TLSerdes.scala:45:71]
wire client_tl_a_bits_corrupt; // @[TLSerdes.scala:45:71]
wire client_tl_a_valid; // @[TLSerdes.scala:45:71]
wire [2:0] client_tl_c_bits_opcode; // @[TLSerdes.scala:45:71]
wire [2:0] client_tl_c_bits_param; // @[TLSerdes.scala:45:71]
wire [7:0] client_tl_c_bits_size; // @[TLSerdes.scala:45:71]
wire [7:0] client_tl_c_bits_source; // @[TLSerdes.scala:45:71]
wire [63:0] client_tl_c_bits_address; // @[TLSerdes.scala:45:71]
wire [63:0] client_tl_c_bits_data; // @[TLSerdes.scala:45:71]
wire client_tl_c_bits_corrupt; // @[TLSerdes.scala:45:71]
wire client_tl_c_valid; // @[TLSerdes.scala:45:71]
wire [7:0] client_tl_e_bits_sink; // @[TLSerdes.scala:45:71]
wire client_tl_e_valid; // @[TLSerdes.scala:45:71]
wire _io_debug_ser_busy_T; // @[package.scala:81:59]
assign _io_debug_ser_busy_T_1 = _io_debug_ser_busy_T | _ser_4_io_busy; // @[TLSerdes.scala:69:23]
assign io_debug_ser_busy = _io_debug_ser_busy_T_1; // @[TLSerdes.scala:39:9]
wire [2:0] in_channels_3_1_bits_opcode; // @[Bundles.scala:264:61]
wire [1:0] in_channels_3_1_bits_param; // @[Bundles.scala:264:61]
wire [3:0] in_channels_3_1_bits_size; // @[Bundles.scala:264:61]
wire in_channels_3_1_bits_source; // @[Bundles.scala:264:61]
wire [31:0] in_channels_3_1_bits_address; // @[Bundles.scala:264:61]
wire [7:0] in_channels_3_1_bits_mask; // @[Bundles.scala:264:61]
wire [63:0] in_channels_3_1_bits_data; // @[Bundles.scala:264:61]
wire in_channels_3_1_bits_corrupt; // @[Bundles.scala:264:61]
wire in_channels_3_1_valid; // @[Bundles.scala:264:61]
assign managerNodeIn_d_bits_size = _in_channels_1_2_io_protocol_bits_size[3:0]; // @[TLSerdes.scala:79:28, :85:9]
assign managerNodeIn_d_bits_source = _in_channels_1_2_io_protocol_bits_source[0]; // @[TLSerdes.scala:79:28, :85:9]
assign managerNodeIn_d_bits_sink = _in_channels_1_2_io_protocol_bits_sink[3:0]; // @[TLSerdes.scala:79:28, :85:9]
assign in_channels_3_1_bits_size = _in_channels_3_2_io_protocol_bits_size[3:0]; // @[TLSerdes.scala:81:28, :85:9]
assign in_channels_3_1_bits_source = _in_channels_3_2_io_protocol_bits_source[0]; // @[TLSerdes.scala:81:28, :85:9]
assign in_channels_3_1_bits_address = _in_channels_3_2_io_protocol_bits_address[31:0]; // @[TLSerdes.scala:81:28, :85:9]
wire _io_debug_des_busy_T; // @[package.scala:81:59]
wire _io_debug_des_busy_T_1 = _io_debug_des_busy_T | _des_2_io_busy; // @[TLSerdes.scala:86:23]
wire _io_debug_des_busy_T_2 = _io_debug_des_busy_T_1 | _des_3_io_busy; // @[TLSerdes.scala:86:23]
assign _io_debug_des_busy_T_3 = _io_debug_des_busy_T_2 | _des_4_io_busy; // @[TLSerdes.scala:86:23]
assign io_debug_des_busy = _io_debug_des_busy_T_3; // @[TLSerdes.scala:39:9]
TLMonitor_68 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (managerNodeIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (managerNodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (managerNodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (managerNodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (managerNodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (managerNodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (managerNodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (managerNodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (managerNodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_a_bits_corrupt (managerNodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_d_ready (managerNodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (managerNodeIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (managerNodeIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_param (managerNodeIn_d_bits_param), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (managerNodeIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (managerNodeIn_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_sink (managerNodeIn_d_bits_sink), // @[MixedNode.scala:551:17]
.io_in_d_bits_denied (managerNodeIn_d_bits_denied), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (managerNodeIn_d_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_bits_corrupt (managerNodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
TLEToBeat_SerialRAM_a64d64s8k8z8c out_channels_0_2 ( // @[TLSerdes.scala:59:50]
.clock (clock),
.reset (reset),
.io_beat_ready (_ser_0_io_in_ready), // @[TLSerdes.scala:69:23]
.io_beat_bits_head (_out_channels_0_2_io_beat_bits_head)
); // @[TLSerdes.scala:59:50]
TLCToBeat_SerialRAM_a64d64s8k8z8c out_channels_2_2 ( // @[TLSerdes.scala:61:50]
.clock (clock),
.reset (reset),
.io_beat_ready (_ser_2_io_in_ready), // @[TLSerdes.scala:69:23]
.io_beat_bits_head (_out_channels_2_2_io_beat_bits_head)
); // @[TLSerdes.scala:61:50]
TLAToBeat_SerialRAM_a64d64s8k8z8c out_channels_4_2 ( // @[TLSerdes.scala:63:50]
.clock (clock),
.reset (reset),
.io_protocol_ready (managerNodeIn_a_ready),
.io_protocol_valid (managerNodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_protocol_bits_opcode (managerNodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_protocol_bits_param (managerNodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_protocol_bits_size ({4'h0, managerNodeIn_a_bits_size}), // @[TLSerdes.scala:68:21]
.io_protocol_bits_source ({7'h0, managerNodeIn_a_bits_source}), // @[TLSerdes.scala:68:21]
.io_protocol_bits_address ({32'h0, managerNodeIn_a_bits_address}), // @[TLSerdes.scala:68:21]
.io_protocol_bits_mask (managerNodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_protocol_bits_data (managerNodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_protocol_bits_corrupt (managerNodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_beat_ready (_ser_4_io_in_ready), // @[TLSerdes.scala:69:23]
.io_beat_valid (_out_channels_4_2_io_beat_valid),
.io_beat_bits_payload (_out_channels_4_2_io_beat_bits_payload),
.io_beat_bits_head (_out_channels_4_2_io_beat_bits_head),
.io_beat_bits_tail (_out_channels_4_2_io_beat_bits_tail)
); // @[TLSerdes.scala:63:50]
GenericSerializer_TLBeatw10_f32 ser_0 ( // @[TLSerdes.scala:69:23]
.clock (clock),
.reset (reset),
.io_in_ready (_ser_0_io_in_ready),
.io_in_bits_head (_out_channels_0_2_io_beat_bits_head), // @[TLSerdes.scala:59:50]
.io_out_ready (io_ser_0_out_ready_0), // @[TLSerdes.scala:39:9]
.io_out_bits_flit (io_ser_0_out_bits_flit_0)
); // @[TLSerdes.scala:69:23]
GenericSerializer_TLBeatw88_f32 ser_2 ( // @[TLSerdes.scala:69:23]
.clock (clock),
.reset (reset),
.io_in_ready (_ser_2_io_in_ready),
.io_in_bits_head (_out_channels_2_2_io_beat_bits_head), // @[TLSerdes.scala:61:50]
.io_out_ready (io_ser_2_out_ready_0), // @[TLSerdes.scala:39:9]
.io_out_valid (io_ser_2_out_valid_0),
.io_out_bits_flit (io_ser_2_out_bits_flit_0),
.io_busy (_io_debug_ser_busy_T)
); // @[TLSerdes.scala:69:23]
GenericSerializer_TLBeatw88_f32_1 ser_4 ( // @[TLSerdes.scala:69:23]
.clock (clock),
.reset (reset),
.io_in_ready (_ser_4_io_in_ready),
.io_in_valid (_out_channels_4_2_io_beat_valid), // @[TLSerdes.scala:63:50]
.io_in_bits_payload (_out_channels_4_2_io_beat_bits_payload), // @[TLSerdes.scala:63:50]
.io_in_bits_head (_out_channels_4_2_io_beat_bits_head), // @[TLSerdes.scala:63:50]
.io_in_bits_tail (_out_channels_4_2_io_beat_bits_tail), // @[TLSerdes.scala:63:50]
.io_out_ready (io_ser_4_out_ready_0), // @[TLSerdes.scala:39:9]
.io_out_valid (io_ser_4_out_valid_0),
.io_out_bits_flit (io_ser_4_out_bits_flit_0),
.io_busy (_ser_4_io_busy)
); // @[TLSerdes.scala:69:23]
TLEFromBeat_SerialRAM_a64d64s8k8z8c in_channels_0_2 ( // @[TLSerdes.scala:78:28]
.clock (clock),
.reset (reset),
.io_protocol_valid (client_tl_e_valid),
.io_protocol_bits_sink (client_tl_e_bits_sink),
.io_beat_ready (_in_channels_0_2_io_beat_ready),
.io_beat_valid (_des_0_io_out_valid), // @[TLSerdes.scala:86:23]
.io_beat_bits_payload (_des_0_io_out_bits_payload), // @[TLSerdes.scala:86:23]
.io_beat_bits_head (_des_0_io_out_bits_head), // @[TLSerdes.scala:86:23]
.io_beat_bits_tail (_des_0_io_out_bits_tail) // @[TLSerdes.scala:86:23]
); // @[TLSerdes.scala:78:28]
TLDFromBeat_SerialRAM_a64d64s8k8z8c in_channels_1_2 ( // @[TLSerdes.scala:79:28]
.clock (clock),
.reset (reset),
.io_protocol_ready (managerNodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_protocol_valid (managerNodeIn_d_valid),
.io_protocol_bits_opcode (managerNodeIn_d_bits_opcode),
.io_protocol_bits_param (managerNodeIn_d_bits_param),
.io_protocol_bits_size (_in_channels_1_2_io_protocol_bits_size),
.io_protocol_bits_source (_in_channels_1_2_io_protocol_bits_source),
.io_protocol_bits_sink (_in_channels_1_2_io_protocol_bits_sink),
.io_protocol_bits_denied (managerNodeIn_d_bits_denied),
.io_protocol_bits_data (managerNodeIn_d_bits_data),
.io_protocol_bits_corrupt (managerNodeIn_d_bits_corrupt),
.io_beat_ready (_in_channels_1_2_io_beat_ready),
.io_beat_valid (_des_1_io_out_valid), // @[TLSerdes.scala:86:23]
.io_beat_bits_payload (_des_1_io_out_bits_payload), // @[TLSerdes.scala:86:23]
.io_beat_bits_head (_des_1_io_out_bits_head), // @[TLSerdes.scala:86:23]
.io_beat_bits_tail (_des_1_io_out_bits_tail) // @[TLSerdes.scala:86:23]
); // @[TLSerdes.scala:79:28]
TLCFromBeat_SerialRAM_a64d64s8k8z8c in_channels_2_2 ( // @[TLSerdes.scala:80:28]
.clock (clock),
.reset (reset),
.io_protocol_valid (client_tl_c_valid),
.io_protocol_bits_opcode (client_tl_c_bits_opcode),
.io_protocol_bits_param (client_tl_c_bits_param),
.io_protocol_bits_size (client_tl_c_bits_size),
.io_protocol_bits_source (client_tl_c_bits_source),
.io_protocol_bits_address (client_tl_c_bits_address),
.io_protocol_bits_data (client_tl_c_bits_data),
.io_protocol_bits_corrupt (client_tl_c_bits_corrupt),
.io_beat_ready (_in_channels_2_2_io_beat_ready),
.io_beat_valid (_des_2_io_out_valid), // @[TLSerdes.scala:86:23]
.io_beat_bits_payload (_des_2_io_out_bits_payload), // @[TLSerdes.scala:86:23]
.io_beat_bits_head (_des_2_io_out_bits_head), // @[TLSerdes.scala:86:23]
.io_beat_bits_tail (_des_2_io_out_bits_tail) // @[TLSerdes.scala:86:23]
); // @[TLSerdes.scala:80:28]
TLBFromBeat_SerialRAM_a64d64s8k8z8c in_channels_3_2 ( // @[TLSerdes.scala:81:28]
.clock (clock),
.reset (reset),
.io_protocol_valid (in_channels_3_1_valid),
.io_protocol_bits_opcode (in_channels_3_1_bits_opcode),
.io_protocol_bits_param (in_channels_3_1_bits_param),
.io_protocol_bits_size (_in_channels_3_2_io_protocol_bits_size),
.io_protocol_bits_source (_in_channels_3_2_io_protocol_bits_source),
.io_protocol_bits_address (_in_channels_3_2_io_protocol_bits_address),
.io_protocol_bits_mask (in_channels_3_1_bits_mask),
.io_protocol_bits_data (in_channels_3_1_bits_data),
.io_protocol_bits_corrupt (in_channels_3_1_bits_corrupt),
.io_beat_ready (_in_channels_3_2_io_beat_ready),
.io_beat_valid (_des_3_io_out_valid), // @[TLSerdes.scala:86:23]
.io_beat_bits_payload (_des_3_io_out_bits_payload), // @[TLSerdes.scala:86:23]
.io_beat_bits_head (_des_3_io_out_bits_head), // @[TLSerdes.scala:86:23]
.io_beat_bits_tail (_des_3_io_out_bits_tail) // @[TLSerdes.scala:86:23]
); // @[TLSerdes.scala:81:28]
TLAFromBeat_SerialRAM_a64d64s8k8z8c in_channels_4_2 ( // @[TLSerdes.scala:82:28]
.clock (clock),
.reset (reset),
.io_protocol_valid (client_tl_a_valid),
.io_protocol_bits_opcode (client_tl_a_bits_opcode),
.io_protocol_bits_param (client_tl_a_bits_param),
.io_protocol_bits_size (client_tl_a_bits_size),
.io_protocol_bits_source (client_tl_a_bits_source),
.io_protocol_bits_address (client_tl_a_bits_address),
.io_protocol_bits_mask (client_tl_a_bits_mask),
.io_protocol_bits_data (client_tl_a_bits_data),
.io_protocol_bits_corrupt (client_tl_a_bits_corrupt),
.io_beat_ready (_in_channels_4_2_io_beat_ready),
.io_beat_valid (_des_4_io_out_valid), // @[TLSerdes.scala:86:23]
.io_beat_bits_payload (_des_4_io_out_bits_payload), // @[TLSerdes.scala:86:23]
.io_beat_bits_head (_des_4_io_out_bits_head), // @[TLSerdes.scala:86:23]
.io_beat_bits_tail (_des_4_io_out_bits_tail) // @[TLSerdes.scala:86:23]
); // @[TLSerdes.scala:82:28]
GenericDeserializer_TLBeatw10_f32_1 des_0 ( // @[TLSerdes.scala:86:23]
.clock (clock),
.reset (reset),
.io_in_ready (io_ser_0_in_ready_0),
.io_in_valid (io_ser_0_in_valid_0), // @[TLSerdes.scala:39:9]
.io_in_bits_flit (io_ser_0_in_bits_flit_0), // @[TLSerdes.scala:39:9]
.io_out_ready (_in_channels_0_2_io_beat_ready), // @[TLSerdes.scala:78:28]
.io_out_valid (_des_0_io_out_valid),
.io_out_bits_payload (_des_0_io_out_bits_payload),
.io_out_bits_head (_des_0_io_out_bits_head),
.io_out_bits_tail (_des_0_io_out_bits_tail)
); // @[TLSerdes.scala:86:23]
GenericDeserializer_TLBeatw67_f32_1 des_1 ( // @[TLSerdes.scala:86:23]
.clock (clock),
.reset (reset),
.io_in_ready (io_ser_1_in_ready_0),
.io_in_valid (io_ser_1_in_valid_0), // @[TLSerdes.scala:39:9]
.io_in_bits_flit (io_ser_1_in_bits_flit_0), // @[TLSerdes.scala:39:9]
.io_out_ready (_in_channels_1_2_io_beat_ready), // @[TLSerdes.scala:79:28]
.io_out_valid (_des_1_io_out_valid),
.io_out_bits_payload (_des_1_io_out_bits_payload),
.io_out_bits_head (_des_1_io_out_bits_head),
.io_out_bits_tail (_des_1_io_out_bits_tail),
.io_busy (_io_debug_des_busy_T)
); // @[TLSerdes.scala:86:23]
GenericDeserializer_TLBeatw88_f32_2 des_2 ( // @[TLSerdes.scala:86:23]
.clock (clock),
.reset (reset),
.io_in_ready (io_ser_2_in_ready_0),
.io_in_valid (io_ser_2_in_valid_0), // @[TLSerdes.scala:39:9]
.io_in_bits_flit (io_ser_2_in_bits_flit_0), // @[TLSerdes.scala:39:9]
.io_out_ready (_in_channels_2_2_io_beat_ready), // @[TLSerdes.scala:80:28]
.io_out_valid (_des_2_io_out_valid),
.io_out_bits_payload (_des_2_io_out_bits_payload),
.io_out_bits_head (_des_2_io_out_bits_head),
.io_out_bits_tail (_des_2_io_out_bits_tail),
.io_busy (_des_2_io_busy)
); // @[TLSerdes.scala:86:23]
GenericDeserializer_TLBeatw87_f32_1 des_3 ( // @[TLSerdes.scala:86:23]
.clock (clock),
.reset (reset),
.io_in_ready (io_ser_3_in_ready_0),
.io_in_valid (io_ser_3_in_valid_0), // @[TLSerdes.scala:39:9]
.io_in_bits_flit (io_ser_3_in_bits_flit_0), // @[TLSerdes.scala:39:9]
.io_out_ready (_in_channels_3_2_io_beat_ready), // @[TLSerdes.scala:81:28]
.io_out_valid (_des_3_io_out_valid),
.io_out_bits_payload (_des_3_io_out_bits_payload),
.io_out_bits_head (_des_3_io_out_bits_head),
.io_out_bits_tail (_des_3_io_out_bits_tail),
.io_busy (_des_3_io_busy)
); // @[TLSerdes.scala:86:23]
GenericDeserializer_TLBeatw88_f32_3 des_4 ( // @[TLSerdes.scala:86:23]
.clock (clock),
.reset (reset),
.io_in_ready (io_ser_4_in_ready_0),
.io_in_valid (io_ser_4_in_valid_0), // @[TLSerdes.scala:39:9]
.io_in_bits_flit (io_ser_4_in_bits_flit_0), // @[TLSerdes.scala:39:9]
.io_out_ready (_in_channels_4_2_io_beat_ready), // @[TLSerdes.scala:82:28]
.io_out_valid (_des_4_io_out_valid),
.io_out_bits_payload (_des_4_io_out_bits_payload),
.io_out_bits_head (_des_4_io_out_bits_head),
.io_out_bits_tail (_des_4_io_out_bits_tail),
.io_busy (_des_4_io_busy)
); // @[TLSerdes.scala:86:23]
assign auto_manager_in_a_ready = auto_manager_in_a_ready_0; // @[TLSerdes.scala:39:9]
assign auto_manager_in_d_valid = auto_manager_in_d_valid_0; // @[TLSerdes.scala:39:9]
assign auto_manager_in_d_bits_opcode = auto_manager_in_d_bits_opcode_0; // @[TLSerdes.scala:39:9]
assign auto_manager_in_d_bits_param = auto_manager_in_d_bits_param_0; // @[TLSerdes.scala:39:9]
assign auto_manager_in_d_bits_size = auto_manager_in_d_bits_size_0; // @[TLSerdes.scala:39:9]
assign auto_manager_in_d_bits_source = auto_manager_in_d_bits_source_0; // @[TLSerdes.scala:39:9]
assign auto_manager_in_d_bits_sink = auto_manager_in_d_bits_sink_0; // @[TLSerdes.scala:39:9]
assign auto_manager_in_d_bits_denied = auto_manager_in_d_bits_denied_0; // @[TLSerdes.scala:39:9]
assign auto_manager_in_d_bits_data = auto_manager_in_d_bits_data_0; // @[TLSerdes.scala:39:9]
assign auto_manager_in_d_bits_corrupt = auto_manager_in_d_bits_corrupt_0; // @[TLSerdes.scala:39:9]
assign io_ser_0_in_ready = io_ser_0_in_ready_0; // @[TLSerdes.scala:39:9]
assign io_ser_0_out_bits_flit = io_ser_0_out_bits_flit_0; // @[TLSerdes.scala:39:9]
assign io_ser_1_in_ready = io_ser_1_in_ready_0; // @[TLSerdes.scala:39:9]
assign io_ser_2_in_ready = io_ser_2_in_ready_0; // @[TLSerdes.scala:39:9]
assign io_ser_2_out_valid = io_ser_2_out_valid_0; // @[TLSerdes.scala:39:9]
assign io_ser_2_out_bits_flit = io_ser_2_out_bits_flit_0; // @[TLSerdes.scala:39:9]
assign io_ser_3_in_ready = io_ser_3_in_ready_0; // @[TLSerdes.scala:39:9]
assign io_ser_4_in_ready = io_ser_4_in_ready_0; // @[TLSerdes.scala:39:9]
assign io_ser_4_out_valid = io_ser_4_out_valid_0; // @[TLSerdes.scala:39:9]
assign io_ser_4_out_bits_flit = io_ser_4_out_bits_flit_0; // @[TLSerdes.scala:39:9]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File TLSerdes.scala:
package testchipip.serdes
import chisel3._
import chisel3.util._
import freechips.rocketchip.diplomacy._
import org.chipsalliance.cde.config._
import freechips.rocketchip.util._
import freechips.rocketchip.tilelink._
object TLSerdesser {
// This should be the standard bundle type for TLSerdesser
val STANDARD_TLBUNDLE_PARAMS = TLBundleParameters(
addressBits=64, dataBits=64,
sourceBits=8, sinkBits=8, sizeBits=8,
echoFields=Nil, requestFields=Nil, responseFields=Nil,
hasBCE=true)
}
class SerdesDebugIO extends Bundle {
val ser_busy = Output(Bool())
val des_busy = Output(Bool())
}
class TLSerdesser(
val flitWidth: Int,
clientPortParams: Option[TLMasterPortParameters],
managerPortParams: Option[TLSlavePortParameters],
val bundleParams: TLBundleParameters = TLSerdesser.STANDARD_TLBUNDLE_PARAMS,
nameSuffix: Option[String] = None
)
(implicit p: Parameters) extends LazyModule {
require (clientPortParams.isDefined || managerPortParams.isDefined)
val clientNode = clientPortParams.map { c => TLClientNode(Seq(c)) }
val managerNode = managerPortParams.map { m => TLManagerNode(Seq(m)) }
override lazy val desiredName = (Seq("TLSerdesser") ++ nameSuffix).mkString("_")
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
val io = IO(new Bundle {
val ser = Vec(5, new DecoupledFlitIO(flitWidth))
val debug = new SerdesDebugIO
})
val client_tl = clientNode.map(_.out(0)._1).getOrElse(0.U.asTypeOf(new TLBundle(bundleParams)))
val client_edge = clientNode.map(_.out(0)._2)
val manager_tl = managerNode.map(_.in(0)._1).getOrElse(0.U.asTypeOf(new TLBundle(bundleParams)))
val manager_edge = managerNode.map(_.in(0)._2)
val clientParams = client_edge.map(_.bundle).getOrElse(bundleParams)
val managerParams = manager_edge.map(_.bundle).getOrElse(bundleParams)
val mergedParams = clientParams.union(managerParams).union(bundleParams)
require(mergedParams.echoFields.isEmpty, "TLSerdesser does not support TileLink with echo fields")
require(mergedParams.requestFields.isEmpty, "TLSerdesser does not support TileLink with request fields")
require(mergedParams.responseFields.isEmpty, "TLSerdesser does not support TileLink with response fields")
require(mergedParams == bundleParams, s"TLSerdesser is misconfigured, the combined inwards/outwards parameters cannot be serialized using the provided bundle params\n$mergedParams > $bundleParams")
val out_channels = Seq(
(manager_tl.e, manager_edge.map(e => Module(new TLEToBeat(e, mergedParams, nameSuffix)))),
(client_tl.d, client_edge.map (e => Module(new TLDToBeat(e, mergedParams, nameSuffix)))),
(manager_tl.c, manager_edge.map(e => Module(new TLCToBeat(e, mergedParams, nameSuffix)))),
(client_tl.b, client_edge.map (e => Module(new TLBToBeat(e, mergedParams, nameSuffix)))),
(manager_tl.a, manager_edge.map(e => Module(new TLAToBeat(e, mergedParams, nameSuffix))))
)
io.ser.map(_.out.valid := false.B)
io.ser.map(_.out.bits := DontCare)
val out_sers = out_channels.zipWithIndex.map { case ((c,b),i) => b.map { b =>
b.io.protocol <> c
val ser = Module(new GenericSerializer(b.io.beat.bits.cloneType, flitWidth)).suggestName(s"ser_$i")
ser.io.in <> b.io.beat
io.ser(i).out <> ser.io.out
ser
}}.flatten
io.debug.ser_busy := out_sers.map(_.io.busy).orR
val in_channels = Seq(
(client_tl.e, Module(new TLEFromBeat(mergedParams, nameSuffix))),
(manager_tl.d, Module(new TLDFromBeat(mergedParams, nameSuffix))),
(client_tl.c, Module(new TLCFromBeat(mergedParams, nameSuffix))),
(manager_tl.b, Module(new TLBFromBeat(mergedParams, nameSuffix))),
(client_tl.a, Module(new TLAFromBeat(mergedParams, nameSuffix)))
)
val in_desers = in_channels.zipWithIndex.map { case ((c,b),i) =>
c <> b.io.protocol
val des = Module(new GenericDeserializer(b.io.beat.bits.cloneType, flitWidth)).suggestName(s"des_$i")
des.io.in <> io.ser(i).in
b.io.beat <> des.io.out
des
}
io.debug.des_busy := in_desers.map(_.io.busy).orR
}
}
| module TLSerdesser_serial_tl_0( // @[TLSerdes.scala:39:9]
input clock, // @[TLSerdes.scala:39:9]
input reset, // @[TLSerdes.scala:39:9]
input auto_client_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_client_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_client_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_client_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_client_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_client_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_client_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_client_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_client_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_client_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_client_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_client_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_client_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_client_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_client_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_client_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_client_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_client_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_client_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_client_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output io_ser_0_in_ready, // @[TLSerdes.scala:40:16]
input io_ser_0_in_valid, // @[TLSerdes.scala:40:16]
input [31:0] io_ser_0_in_bits_flit, // @[TLSerdes.scala:40:16]
output io_ser_1_in_ready, // @[TLSerdes.scala:40:16]
input io_ser_1_in_valid, // @[TLSerdes.scala:40:16]
input [31:0] io_ser_1_in_bits_flit, // @[TLSerdes.scala:40:16]
input io_ser_1_out_ready, // @[TLSerdes.scala:40:16]
output io_ser_1_out_valid, // @[TLSerdes.scala:40:16]
output [31:0] io_ser_1_out_bits_flit, // @[TLSerdes.scala:40:16]
output io_ser_2_in_ready, // @[TLSerdes.scala:40:16]
input io_ser_2_in_valid, // @[TLSerdes.scala:40:16]
input [31:0] io_ser_2_in_bits_flit, // @[TLSerdes.scala:40:16]
output io_ser_3_in_ready, // @[TLSerdes.scala:40:16]
input io_ser_3_in_valid, // @[TLSerdes.scala:40:16]
input [31:0] io_ser_3_in_bits_flit, // @[TLSerdes.scala:40:16]
input io_ser_3_out_ready, // @[TLSerdes.scala:40:16]
output io_ser_3_out_valid, // @[TLSerdes.scala:40:16]
output [31:0] io_ser_3_out_bits_flit, // @[TLSerdes.scala:40:16]
output io_ser_4_in_ready, // @[TLSerdes.scala:40:16]
input io_ser_4_in_valid, // @[TLSerdes.scala:40:16]
input [31:0] io_ser_4_in_bits_flit // @[TLSerdes.scala:40:16]
);
wire _des_4_io_out_valid; // @[TLSerdes.scala:86:23]
wire [85:0] _des_4_io_out_bits_payload; // @[TLSerdes.scala:86:23]
wire _des_4_io_out_bits_head; // @[TLSerdes.scala:86:23]
wire _des_4_io_out_bits_tail; // @[TLSerdes.scala:86:23]
wire _des_3_io_out_valid; // @[TLSerdes.scala:86:23]
wire _des_3_io_out_bits_head; // @[TLSerdes.scala:86:23]
wire _des_3_io_out_bits_tail; // @[TLSerdes.scala:86:23]
wire _des_2_io_out_valid; // @[TLSerdes.scala:86:23]
wire _des_2_io_out_bits_head; // @[TLSerdes.scala:86:23]
wire _des_2_io_out_bits_tail; // @[TLSerdes.scala:86:23]
wire _des_1_io_out_valid; // @[TLSerdes.scala:86:23]
wire _des_1_io_out_bits_head; // @[TLSerdes.scala:86:23]
wire _des_1_io_out_bits_tail; // @[TLSerdes.scala:86:23]
wire _des_0_io_out_valid; // @[TLSerdes.scala:86:23]
wire _des_0_io_out_bits_head; // @[TLSerdes.scala:86:23]
wire _des_0_io_out_bits_tail; // @[TLSerdes.scala:86:23]
wire [7:0] _in_channels_4_2_io_protocol_bits_size; // @[TLSerdes.scala:82:28]
wire [7:0] _in_channels_4_2_io_protocol_bits_source; // @[TLSerdes.scala:82:28]
wire [63:0] _in_channels_4_2_io_protocol_bits_address; // @[TLSerdes.scala:82:28]
wire _in_channels_4_2_io_beat_ready; // @[TLSerdes.scala:82:28]
wire _in_channels_3_2_io_beat_ready; // @[TLSerdes.scala:81:28]
wire _in_channels_2_2_io_beat_ready; // @[TLSerdes.scala:80:28]
wire _in_channels_1_2_io_beat_ready; // @[TLSerdes.scala:79:28]
wire _in_channels_0_2_io_beat_ready; // @[TLSerdes.scala:78:28]
wire _ser_1_io_in_ready; // @[TLSerdes.scala:69:23]
wire _out_channels_3_2_io_beat_bits_head; // @[TLSerdes.scala:62:50]
wire _out_channels_3_2_io_beat_bits_tail; // @[TLSerdes.scala:62:50]
wire _out_channels_1_2_io_beat_valid; // @[TLSerdes.scala:60:50]
wire [64:0] _out_channels_1_2_io_beat_bits_payload; // @[TLSerdes.scala:60:50]
wire _out_channels_1_2_io_beat_bits_head; // @[TLSerdes.scala:60:50]
wire _out_channels_1_2_io_beat_bits_tail; // @[TLSerdes.scala:60:50]
TLDToBeat_serial_tl_0_a64d64s8k8z8c out_channels_1_2 ( // @[TLSerdes.scala:60:50]
.clock (clock),
.reset (reset),
.io_protocol_ready (auto_client_out_d_ready),
.io_protocol_valid (auto_client_out_d_valid),
.io_protocol_bits_opcode (auto_client_out_d_bits_opcode),
.io_protocol_bits_param (auto_client_out_d_bits_param),
.io_protocol_bits_size ({4'h0, auto_client_out_d_bits_size}), // @[TLSerdes.scala:68:21]
.io_protocol_bits_source ({4'h0, auto_client_out_d_bits_source}), // @[TLSerdes.scala:68:21]
.io_protocol_bits_sink ({3'h0, auto_client_out_d_bits_sink}), // @[TLSerdes.scala:68:21]
.io_protocol_bits_denied (auto_client_out_d_bits_denied),
.io_protocol_bits_data (auto_client_out_d_bits_data),
.io_protocol_bits_corrupt (auto_client_out_d_bits_corrupt),
.io_beat_ready (_ser_1_io_in_ready), // @[TLSerdes.scala:69:23]
.io_beat_valid (_out_channels_1_2_io_beat_valid),
.io_beat_bits_payload (_out_channels_1_2_io_beat_bits_payload),
.io_beat_bits_head (_out_channels_1_2_io_beat_bits_head),
.io_beat_bits_tail (_out_channels_1_2_io_beat_bits_tail)
); // @[TLSerdes.scala:60:50]
TLBToBeat_serial_tl_0_a64d64s8k8z8c out_channels_3_2 ( // @[TLSerdes.scala:62:50]
.clock (clock),
.reset (reset),
.io_beat_bits_head (_out_channels_3_2_io_beat_bits_head),
.io_beat_bits_tail (_out_channels_3_2_io_beat_bits_tail)
); // @[TLSerdes.scala:62:50]
GenericSerializer_TLBeatw67_f32 ser_1 ( // @[TLSerdes.scala:69:23]
.clock (clock),
.reset (reset),
.io_in_ready (_ser_1_io_in_ready),
.io_in_valid (_out_channels_1_2_io_beat_valid), // @[TLSerdes.scala:60:50]
.io_in_bits_payload (_out_channels_1_2_io_beat_bits_payload), // @[TLSerdes.scala:60:50]
.io_in_bits_head (_out_channels_1_2_io_beat_bits_head), // @[TLSerdes.scala:60:50]
.io_in_bits_tail (_out_channels_1_2_io_beat_bits_tail), // @[TLSerdes.scala:60:50]
.io_out_ready (io_ser_1_out_ready),
.io_out_valid (io_ser_1_out_valid),
.io_out_bits_flit (io_ser_1_out_bits_flit)
); // @[TLSerdes.scala:69:23]
GenericSerializer_TLBeatw87_f32 ser_3 ( // @[TLSerdes.scala:69:23]
.clock (clock),
.reset (reset),
.io_in_bits_head (_out_channels_3_2_io_beat_bits_head), // @[TLSerdes.scala:62:50]
.io_in_bits_tail (_out_channels_3_2_io_beat_bits_tail), // @[TLSerdes.scala:62:50]
.io_out_ready (io_ser_3_out_ready),
.io_out_valid (io_ser_3_out_valid),
.io_out_bits_flit (io_ser_3_out_bits_flit)
); // @[TLSerdes.scala:69:23]
TLEFromBeat_serial_tl_0_a64d64s8k8z8c in_channels_0_2 ( // @[TLSerdes.scala:78:28]
.clock (clock),
.reset (reset),
.io_beat_ready (_in_channels_0_2_io_beat_ready),
.io_beat_valid (_des_0_io_out_valid), // @[TLSerdes.scala:86:23]
.io_beat_bits_head (_des_0_io_out_bits_head), // @[TLSerdes.scala:86:23]
.io_beat_bits_tail (_des_0_io_out_bits_tail) // @[TLSerdes.scala:86:23]
); // @[TLSerdes.scala:78:28]
TLDFromBeat_serial_tl_0_a64d64s8k8z8c in_channels_1_2 ( // @[TLSerdes.scala:79:28]
.clock (clock),
.reset (reset),
.io_beat_ready (_in_channels_1_2_io_beat_ready),
.io_beat_valid (_des_1_io_out_valid), // @[TLSerdes.scala:86:23]
.io_beat_bits_head (_des_1_io_out_bits_head), // @[TLSerdes.scala:86:23]
.io_beat_bits_tail (_des_1_io_out_bits_tail) // @[TLSerdes.scala:86:23]
); // @[TLSerdes.scala:79:28]
TLCFromBeat_serial_tl_0_a64d64s8k8z8c in_channels_2_2 ( // @[TLSerdes.scala:80:28]
.clock (clock),
.reset (reset),
.io_beat_ready (_in_channels_2_2_io_beat_ready),
.io_beat_valid (_des_2_io_out_valid), // @[TLSerdes.scala:86:23]
.io_beat_bits_head (_des_2_io_out_bits_head), // @[TLSerdes.scala:86:23]
.io_beat_bits_tail (_des_2_io_out_bits_tail) // @[TLSerdes.scala:86:23]
); // @[TLSerdes.scala:80:28]
TLBFromBeat_serial_tl_0_a64d64s8k8z8c in_channels_3_2 ( // @[TLSerdes.scala:81:28]
.clock (clock),
.reset (reset),
.io_beat_ready (_in_channels_3_2_io_beat_ready),
.io_beat_valid (_des_3_io_out_valid), // @[TLSerdes.scala:86:23]
.io_beat_bits_head (_des_3_io_out_bits_head), // @[TLSerdes.scala:86:23]
.io_beat_bits_tail (_des_3_io_out_bits_tail) // @[TLSerdes.scala:86:23]
); // @[TLSerdes.scala:81:28]
TLAFromBeat_serial_tl_0_a64d64s8k8z8c in_channels_4_2 ( // @[TLSerdes.scala:82:28]
.clock (clock),
.reset (reset),
.io_protocol_ready (auto_client_out_a_ready),
.io_protocol_valid (auto_client_out_a_valid),
.io_protocol_bits_opcode (auto_client_out_a_bits_opcode),
.io_protocol_bits_param (auto_client_out_a_bits_param),
.io_protocol_bits_size (_in_channels_4_2_io_protocol_bits_size),
.io_protocol_bits_source (_in_channels_4_2_io_protocol_bits_source),
.io_protocol_bits_address (_in_channels_4_2_io_protocol_bits_address),
.io_protocol_bits_mask (auto_client_out_a_bits_mask),
.io_protocol_bits_data (auto_client_out_a_bits_data),
.io_protocol_bits_corrupt (auto_client_out_a_bits_corrupt),
.io_beat_ready (_in_channels_4_2_io_beat_ready),
.io_beat_valid (_des_4_io_out_valid), // @[TLSerdes.scala:86:23]
.io_beat_bits_payload (_des_4_io_out_bits_payload), // @[TLSerdes.scala:86:23]
.io_beat_bits_head (_des_4_io_out_bits_head), // @[TLSerdes.scala:86:23]
.io_beat_bits_tail (_des_4_io_out_bits_tail) // @[TLSerdes.scala:86:23]
); // @[TLSerdes.scala:82:28]
GenericDeserializer_TLBeatw10_f32 des_0 ( // @[TLSerdes.scala:86:23]
.io_in_ready (io_ser_0_in_ready),
.io_in_valid (io_ser_0_in_valid),
.io_in_bits_flit (io_ser_0_in_bits_flit),
.io_out_ready (_in_channels_0_2_io_beat_ready), // @[TLSerdes.scala:78:28]
.io_out_valid (_des_0_io_out_valid),
.io_out_bits_head (_des_0_io_out_bits_head),
.io_out_bits_tail (_des_0_io_out_bits_tail)
); // @[TLSerdes.scala:86:23]
GenericDeserializer_TLBeatw67_f32 des_1 ( // @[TLSerdes.scala:86:23]
.clock (clock),
.reset (reset),
.io_in_ready (io_ser_1_in_ready),
.io_in_valid (io_ser_1_in_valid),
.io_in_bits_flit (io_ser_1_in_bits_flit),
.io_out_ready (_in_channels_1_2_io_beat_ready), // @[TLSerdes.scala:79:28]
.io_out_valid (_des_1_io_out_valid),
.io_out_bits_payload (/* unused */),
.io_out_bits_head (_des_1_io_out_bits_head),
.io_out_bits_tail (_des_1_io_out_bits_tail)
); // @[TLSerdes.scala:86:23]
GenericDeserializer_TLBeatw88_f32 des_2 ( // @[TLSerdes.scala:86:23]
.clock (clock),
.reset (reset),
.io_in_ready (io_ser_2_in_ready),
.io_in_valid (io_ser_2_in_valid),
.io_in_bits_flit (io_ser_2_in_bits_flit),
.io_out_ready (_in_channels_2_2_io_beat_ready), // @[TLSerdes.scala:80:28]
.io_out_valid (_des_2_io_out_valid),
.io_out_bits_payload (/* unused */),
.io_out_bits_head (_des_2_io_out_bits_head),
.io_out_bits_tail (_des_2_io_out_bits_tail)
); // @[TLSerdes.scala:86:23]
GenericDeserializer_TLBeatw87_f32 des_3 ( // @[TLSerdes.scala:86:23]
.clock (clock),
.reset (reset),
.io_in_ready (io_ser_3_in_ready),
.io_in_valid (io_ser_3_in_valid),
.io_in_bits_flit (io_ser_3_in_bits_flit),
.io_out_ready (_in_channels_3_2_io_beat_ready), // @[TLSerdes.scala:81:28]
.io_out_valid (_des_3_io_out_valid),
.io_out_bits_head (_des_3_io_out_bits_head),
.io_out_bits_tail (_des_3_io_out_bits_tail)
); // @[TLSerdes.scala:86:23]
GenericDeserializer_TLBeatw88_f32 des_4 ( // @[TLSerdes.scala:86:23]
.clock (clock),
.reset (reset),
.io_in_ready (io_ser_4_in_ready),
.io_in_valid (io_ser_4_in_valid),
.io_in_bits_flit (io_ser_4_in_bits_flit),
.io_out_ready (_in_channels_4_2_io_beat_ready), // @[TLSerdes.scala:82:28]
.io_out_valid (_des_4_io_out_valid),
.io_out_bits_payload (_des_4_io_out_bits_payload),
.io_out_bits_head (_des_4_io_out_bits_head),
.io_out_bits_tail (_des_4_io_out_bits_tail)
); // @[TLSerdes.scala:86:23]
assign auto_client_out_a_bits_size = _in_channels_4_2_io_protocol_bits_size[3:0]; // @[TLSerdes.scala:39:9, :82:28, :85:9]
assign auto_client_out_a_bits_source = _in_channels_4_2_io_protocol_bits_source[3:0]; // @[TLSerdes.scala:39:9, :82:28, :85:9]
assign auto_client_out_a_bits_address = _in_channels_4_2_io_protocol_bits_address[31:0]; // @[TLSerdes.scala:39:9, :82:28, :85:9]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File MSHR.scala:
/*
* Copyright 2019 SiFive, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You should have received a copy of LICENSE.Apache2 along with
* this software. If not, you may obtain a copy at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package sifive.blocks.inclusivecache
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import freechips.rocketchip.tilelink._
import TLPermissions._
import TLMessages._
import MetaData._
import chisel3.PrintableHelper
import chisel3.experimental.dataview._
class ScheduleRequest(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params)
{
val a = Valid(new SourceARequest(params))
val b = Valid(new SourceBRequest(params))
val c = Valid(new SourceCRequest(params))
val d = Valid(new SourceDRequest(params))
val e = Valid(new SourceERequest(params))
val x = Valid(new SourceXRequest(params))
val dir = Valid(new DirectoryWrite(params))
val reload = Bool() // get next request via allocate (if any)
}
class MSHRStatus(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params)
{
val set = UInt(params.setBits.W)
val tag = UInt(params.tagBits.W)
val way = UInt(params.wayBits.W)
val blockB = Bool()
val nestB = Bool()
val blockC = Bool()
val nestC = Bool()
}
class NestedWriteback(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params)
{
val set = UInt(params.setBits.W)
val tag = UInt(params.tagBits.W)
val b_toN = Bool() // nested Probes may unhit us
val b_toB = Bool() // nested Probes may demote us
val b_clr_dirty = Bool() // nested Probes clear dirty
val c_set_dirty = Bool() // nested Releases MAY set dirty
}
sealed trait CacheState
{
val code = CacheState.index.U
CacheState.index = CacheState.index + 1
}
object CacheState
{
var index = 0
}
case object S_INVALID extends CacheState
case object S_BRANCH extends CacheState
case object S_BRANCH_C extends CacheState
case object S_TIP extends CacheState
case object S_TIP_C extends CacheState
case object S_TIP_CD extends CacheState
case object S_TIP_D extends CacheState
case object S_TRUNK_C extends CacheState
case object S_TRUNK_CD extends CacheState
class MSHR(params: InclusiveCacheParameters) extends Module
{
val io = IO(new Bundle {
val allocate = Flipped(Valid(new AllocateRequest(params))) // refills MSHR for next cycle
val directory = Flipped(Valid(new DirectoryResult(params))) // triggers schedule setup
val status = Valid(new MSHRStatus(params))
val schedule = Decoupled(new ScheduleRequest(params))
val sinkc = Flipped(Valid(new SinkCResponse(params)))
val sinkd = Flipped(Valid(new SinkDResponse(params)))
val sinke = Flipped(Valid(new SinkEResponse(params)))
val nestedwb = Flipped(new NestedWriteback(params))
})
val request_valid = RegInit(false.B)
val request = Reg(new FullRequest(params))
val meta_valid = RegInit(false.B)
val meta = Reg(new DirectoryResult(params))
// Define which states are valid
when (meta_valid) {
when (meta.state === INVALID) {
assert (!meta.clients.orR)
assert (!meta.dirty)
}
when (meta.state === BRANCH) {
assert (!meta.dirty)
}
when (meta.state === TRUNK) {
assert (meta.clients.orR)
assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one
}
when (meta.state === TIP) {
// noop
}
}
// Completed transitions (s_ = scheduled), (w_ = waiting)
val s_rprobe = RegInit(true.B) // B
val w_rprobeackfirst = RegInit(true.B)
val w_rprobeacklast = RegInit(true.B)
val s_release = RegInit(true.B) // CW w_rprobeackfirst
val w_releaseack = RegInit(true.B)
val s_pprobe = RegInit(true.B) // B
val s_acquire = RegInit(true.B) // A s_release, s_pprobe [1]
val s_flush = RegInit(true.B) // X w_releaseack
val w_grantfirst = RegInit(true.B)
val w_grantlast = RegInit(true.B)
val w_grant = RegInit(true.B) // first | last depending on wormhole
val w_pprobeackfirst = RegInit(true.B)
val w_pprobeacklast = RegInit(true.B)
val w_pprobeack = RegInit(true.B) // first | last depending on wormhole
val s_probeack = RegInit(true.B) // C w_pprobeackfirst (mutually exclusive with next two s_*)
val s_grantack = RegInit(true.B) // E w_grantfirst ... CAN require both outE&inD to service outD
val s_execute = RegInit(true.B) // D w_pprobeack, w_grant
val w_grantack = RegInit(true.B)
val s_writeback = RegInit(true.B) // W w_*
// [1]: We cannot issue outer Acquire while holding blockB (=> outA can stall)
// However, inB and outC are higher priority than outB, so s_release and s_pprobe
// may be safely issued while blockB. Thus we must NOT try to schedule the
// potentially stuck s_acquire with either of them (scheduler is all or none).
// Meta-data that we discover underway
val sink = Reg(UInt(params.outer.bundle.sinkBits.W))
val gotT = Reg(Bool())
val bad_grant = Reg(Bool())
val probes_done = Reg(UInt(params.clientBits.W))
val probes_toN = Reg(UInt(params.clientBits.W))
val probes_noT = Reg(Bool())
// When a nested transaction completes, update our meta data
when (meta_valid && meta.state =/= INVALID &&
io.nestedwb.set === request.set && io.nestedwb.tag === meta.tag) {
when (io.nestedwb.b_clr_dirty) { meta.dirty := false.B }
when (io.nestedwb.c_set_dirty) { meta.dirty := true.B }
when (io.nestedwb.b_toB) { meta.state := BRANCH }
when (io.nestedwb.b_toN) { meta.hit := false.B }
}
// Scheduler status
io.status.valid := request_valid
io.status.bits.set := request.set
io.status.bits.tag := request.tag
io.status.bits.way := meta.way
io.status.bits.blockB := !meta_valid || ((!w_releaseack || !w_rprobeacklast || !w_pprobeacklast) && !w_grantfirst)
io.status.bits.nestB := meta_valid && w_releaseack && w_rprobeacklast && w_pprobeacklast && !w_grantfirst
// The above rules ensure we will block and not nest an outer probe while still doing our
// own inner probes. Thus every probe wakes exactly one MSHR.
io.status.bits.blockC := !meta_valid
io.status.bits.nestC := meta_valid && (!w_rprobeackfirst || !w_pprobeackfirst || !w_grantfirst)
// The w_grantfirst in nestC is necessary to deal with:
// acquire waiting for grant, inner release gets queued, outer probe -> inner probe -> deadlock
// ... this is possible because the release+probe can be for same set, but different tag
// We can only demand: block, nest, or queue
assert (!io.status.bits.nestB || !io.status.bits.blockB)
assert (!io.status.bits.nestC || !io.status.bits.blockC)
// Scheduler requests
val no_wait = w_rprobeacklast && w_releaseack && w_grantlast && w_pprobeacklast && w_grantack
io.schedule.bits.a.valid := !s_acquire && s_release && s_pprobe
io.schedule.bits.b.valid := !s_rprobe || !s_pprobe
io.schedule.bits.c.valid := (!s_release && w_rprobeackfirst) || (!s_probeack && w_pprobeackfirst)
io.schedule.bits.d.valid := !s_execute && w_pprobeack && w_grant
io.schedule.bits.e.valid := !s_grantack && w_grantfirst
io.schedule.bits.x.valid := !s_flush && w_releaseack
io.schedule.bits.dir.valid := (!s_release && w_rprobeackfirst) || (!s_writeback && no_wait)
io.schedule.bits.reload := no_wait
io.schedule.valid := io.schedule.bits.a.valid || io.schedule.bits.b.valid || io.schedule.bits.c.valid ||
io.schedule.bits.d.valid || io.schedule.bits.e.valid || io.schedule.bits.x.valid ||
io.schedule.bits.dir.valid
// Schedule completions
when (io.schedule.ready) {
s_rprobe := true.B
when (w_rprobeackfirst) { s_release := true.B }
s_pprobe := true.B
when (s_release && s_pprobe) { s_acquire := true.B }
when (w_releaseack) { s_flush := true.B }
when (w_pprobeackfirst) { s_probeack := true.B }
when (w_grantfirst) { s_grantack := true.B }
when (w_pprobeack && w_grant) { s_execute := true.B }
when (no_wait) { s_writeback := true.B }
// Await the next operation
when (no_wait) {
request_valid := false.B
meta_valid := false.B
}
}
// Resulting meta-data
val final_meta_writeback = WireInit(meta)
val req_clientBit = params.clientBit(request.source)
val req_needT = needT(request.opcode, request.param)
val req_acquire = request.opcode === AcquireBlock || request.opcode === AcquirePerm
val meta_no_clients = !meta.clients.orR
val req_promoteT = req_acquire && Mux(meta.hit, meta_no_clients && meta.state === TIP, gotT)
when (request.prio(2) && (!params.firstLevel).B) { // always a hit
final_meta_writeback.dirty := meta.dirty || request.opcode(0)
final_meta_writeback.state := Mux(request.param =/= TtoT && meta.state === TRUNK, TIP, meta.state)
final_meta_writeback.clients := meta.clients & ~Mux(isToN(request.param), req_clientBit, 0.U)
final_meta_writeback.hit := true.B // chained requests are hits
} .elsewhen (request.control && params.control.B) { // request.prio(0)
when (meta.hit) {
final_meta_writeback.dirty := false.B
final_meta_writeback.state := INVALID
final_meta_writeback.clients := meta.clients & ~probes_toN
}
final_meta_writeback.hit := false.B
} .otherwise {
final_meta_writeback.dirty := (meta.hit && meta.dirty) || !request.opcode(2)
final_meta_writeback.state := Mux(req_needT,
Mux(req_acquire, TRUNK, TIP),
Mux(!meta.hit, Mux(gotT, Mux(req_acquire, TRUNK, TIP), BRANCH),
MuxLookup(meta.state, 0.U(2.W))(Seq(
INVALID -> BRANCH,
BRANCH -> BRANCH,
TRUNK -> TIP,
TIP -> Mux(meta_no_clients && req_acquire, TRUNK, TIP)))))
final_meta_writeback.clients := Mux(meta.hit, meta.clients & ~probes_toN, 0.U) |
Mux(req_acquire, req_clientBit, 0.U)
final_meta_writeback.tag := request.tag
final_meta_writeback.hit := true.B
}
when (bad_grant) {
when (meta.hit) {
// upgrade failed (B -> T)
assert (!meta_valid || meta.state === BRANCH)
final_meta_writeback.hit := true.B
final_meta_writeback.dirty := false.B
final_meta_writeback.state := BRANCH
final_meta_writeback.clients := meta.clients & ~probes_toN
} .otherwise {
// failed N -> (T or B)
final_meta_writeback.hit := false.B
final_meta_writeback.dirty := false.B
final_meta_writeback.state := INVALID
final_meta_writeback.clients := 0.U
}
}
val invalid = Wire(new DirectoryEntry(params))
invalid.dirty := false.B
invalid.state := INVALID
invalid.clients := 0.U
invalid.tag := 0.U
// Just because a client says BtoT, by the time we process the request he may be N.
// Therefore, we must consult our own meta-data state to confirm he owns the line still.
val honour_BtoT = meta.hit && (meta.clients & req_clientBit).orR
// The client asking us to act is proof they don't have permissions.
val excluded_client = Mux(meta.hit && request.prio(0) && skipProbeN(request.opcode, params.cache.hintsSkipProbe), req_clientBit, 0.U)
io.schedule.bits.a.bits.tag := request.tag
io.schedule.bits.a.bits.set := request.set
io.schedule.bits.a.bits.param := Mux(req_needT, Mux(meta.hit, BtoT, NtoT), NtoB)
io.schedule.bits.a.bits.block := request.size =/= log2Ceil(params.cache.blockBytes).U ||
!(request.opcode === PutFullData || request.opcode === AcquirePerm)
io.schedule.bits.a.bits.source := 0.U
io.schedule.bits.b.bits.param := Mux(!s_rprobe, toN, Mux(request.prio(1), request.param, Mux(req_needT, toN, toB)))
io.schedule.bits.b.bits.tag := Mux(!s_rprobe, meta.tag, request.tag)
io.schedule.bits.b.bits.set := request.set
io.schedule.bits.b.bits.clients := meta.clients & ~excluded_client
io.schedule.bits.c.bits.opcode := Mux(meta.dirty, ReleaseData, Release)
io.schedule.bits.c.bits.param := Mux(meta.state === BRANCH, BtoN, TtoN)
io.schedule.bits.c.bits.source := 0.U
io.schedule.bits.c.bits.tag := meta.tag
io.schedule.bits.c.bits.set := request.set
io.schedule.bits.c.bits.way := meta.way
io.schedule.bits.c.bits.dirty := meta.dirty
io.schedule.bits.d.bits.viewAsSupertype(chiselTypeOf(request)) := request
io.schedule.bits.d.bits.param := Mux(!req_acquire, request.param,
MuxLookup(request.param, request.param)(Seq(
NtoB -> Mux(req_promoteT, NtoT, NtoB),
BtoT -> Mux(honour_BtoT, BtoT, NtoT),
NtoT -> NtoT)))
io.schedule.bits.d.bits.sink := 0.U
io.schedule.bits.d.bits.way := meta.way
io.schedule.bits.d.bits.bad := bad_grant
io.schedule.bits.e.bits.sink := sink
io.schedule.bits.x.bits.fail := false.B
io.schedule.bits.dir.bits.set := request.set
io.schedule.bits.dir.bits.way := meta.way
io.schedule.bits.dir.bits.data := Mux(!s_release, invalid, WireInit(new DirectoryEntry(params), init = final_meta_writeback))
// Coverage of state transitions
def cacheState(entry: DirectoryEntry, hit: Bool) = {
val out = WireDefault(0.U)
val c = entry.clients.orR
val d = entry.dirty
switch (entry.state) {
is (BRANCH) { out := Mux(c, S_BRANCH_C.code, S_BRANCH.code) }
is (TRUNK) { out := Mux(d, S_TRUNK_CD.code, S_TRUNK_C.code) }
is (TIP) { out := Mux(c, Mux(d, S_TIP_CD.code, S_TIP_C.code), Mux(d, S_TIP_D.code, S_TIP.code)) }
is (INVALID) { out := S_INVALID.code }
}
when (!hit) { out := S_INVALID.code }
out
}
val p = !params.lastLevel // can be probed
val c = !params.firstLevel // can be acquired
val m = params.inner.client.clients.exists(!_.supports.probe) // can be written (or read)
val r = params.outer.manager.managers.exists(!_.alwaysGrantsT) // read-only devices exist
val f = params.control // flush control register exists
val cfg = (p, c, m, r, f)
val b = r || p // can reach branch state (via probe downgrade or read-only device)
// The cache must be used for something or we would not be here
require(c || m)
val evict = cacheState(meta, !meta.hit)
val before = cacheState(meta, meta.hit)
val after = cacheState(final_meta_writeback, true.B)
def eviction(from: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) {
if (cover) {
params.ccover(evict === from.code, s"MSHR_${from}_EVICT", s"State transition from ${from} to evicted ${cfg}")
} else {
assert(!(evict === from.code), cf"State transition from ${from} to evicted should be impossible ${cfg}")
}
if (cover && f) {
params.ccover(before === from.code, s"MSHR_${from}_FLUSH", s"State transition from ${from} to flushed ${cfg}")
} else {
assert(!(before === from.code), cf"State transition from ${from} to flushed should be impossible ${cfg}")
}
}
def transition(from: CacheState, to: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) {
if (cover) {
params.ccover(before === from.code && after === to.code, s"MSHR_${from}_${to}", s"State transition from ${from} to ${to} ${cfg}")
} else {
assert(!(before === from.code && after === to.code), cf"State transition from ${from} to ${to} should be impossible ${cfg}")
}
}
when ((!s_release && w_rprobeackfirst) && io.schedule.ready) {
eviction(S_BRANCH, b) // MMIO read to read-only device
eviction(S_BRANCH_C, b && c) // you need children to become C
eviction(S_TIP, true) // MMIO read || clean release can lead to this state
eviction(S_TIP_C, c) // needs two clients || client + mmio || downgrading client
eviction(S_TIP_CD, c) // needs two clients || client + mmio || downgrading client
eviction(S_TIP_D, true) // MMIO write || dirty release lead here
eviction(S_TRUNK_C, c) // acquire for write
eviction(S_TRUNK_CD, c) // dirty release then reacquire
}
when ((!s_writeback && no_wait) && io.schedule.ready) {
transition(S_INVALID, S_BRANCH, b && m) // only MMIO can bring us to BRANCH state
transition(S_INVALID, S_BRANCH_C, b && c) // C state is only possible if there are inner caches
transition(S_INVALID, S_TIP, m) // MMIO read
transition(S_INVALID, S_TIP_C, false) // we would go S_TRUNK_C instead
transition(S_INVALID, S_TIP_CD, false) // acquire does not cause dirty immediately
transition(S_INVALID, S_TIP_D, m) // MMIO write
transition(S_INVALID, S_TRUNK_C, c) // acquire
transition(S_INVALID, S_TRUNK_CD, false) // acquire does not cause dirty immediately
transition(S_BRANCH, S_INVALID, b && p) // probe can do this (flushes run as evictions)
transition(S_BRANCH, S_BRANCH_C, b && c) // acquire
transition(S_BRANCH, S_TIP, b && m) // prefetch write
transition(S_BRANCH, S_TIP_C, false) // we would go S_TRUNK_C instead
transition(S_BRANCH, S_TIP_CD, false) // acquire does not cause dirty immediately
transition(S_BRANCH, S_TIP_D, b && m) // MMIO write
transition(S_BRANCH, S_TRUNK_C, b && c) // acquire
transition(S_BRANCH, S_TRUNK_CD, false) // acquire does not cause dirty immediately
transition(S_BRANCH_C, S_INVALID, b && c && p)
transition(S_BRANCH_C, S_BRANCH, b && c) // clean release (optional)
transition(S_BRANCH_C, S_TIP, b && c && m) // prefetch write
transition(S_BRANCH_C, S_TIP_C, false) // we would go S_TRUNK_C instead
transition(S_BRANCH_C, S_TIP_D, b && c && m) // MMIO write
transition(S_BRANCH_C, S_TIP_CD, false) // going dirty means we must shoot down clients
transition(S_BRANCH_C, S_TRUNK_C, b && c) // acquire
transition(S_BRANCH_C, S_TRUNK_CD, false) // acquire does not cause dirty immediately
transition(S_TIP, S_INVALID, p)
transition(S_TIP, S_BRANCH, p) // losing TIP only possible via probe
transition(S_TIP, S_BRANCH_C, false) // we would go S_TRUNK_C instead
transition(S_TIP, S_TIP_C, false) // we would go S_TRUNK_C instead
transition(S_TIP, S_TIP_D, m) // direct dirty only via MMIO write
transition(S_TIP, S_TIP_CD, false) // acquire does not make us dirty immediately
transition(S_TIP, S_TRUNK_C, c) // acquire
transition(S_TIP, S_TRUNK_CD, false) // acquire does not make us dirty immediately
transition(S_TIP_C, S_INVALID, c && p)
transition(S_TIP_C, S_BRANCH, c && p) // losing TIP only possible via probe
transition(S_TIP_C, S_BRANCH_C, c && p) // losing TIP only possible via probe
transition(S_TIP_C, S_TIP, c) // probed while MMIO read || clean release (optional)
transition(S_TIP_C, S_TIP_D, c && m) // direct dirty only via MMIO write
transition(S_TIP_C, S_TIP_CD, false) // going dirty means we must shoot down clients
transition(S_TIP_C, S_TRUNK_C, c) // acquire
transition(S_TIP_C, S_TRUNK_CD, false) // acquire does not make us immediately dirty
transition(S_TIP_D, S_INVALID, p)
transition(S_TIP_D, S_BRANCH, p) // losing D is only possible via probe
transition(S_TIP_D, S_BRANCH_C, p && c) // probed while acquire shared
transition(S_TIP_D, S_TIP, p) // probed while MMIO read || outer probe.toT (optional)
transition(S_TIP_D, S_TIP_C, false) // we would go S_TRUNK_C instead
transition(S_TIP_D, S_TIP_CD, false) // we would go S_TRUNK_CD instead
transition(S_TIP_D, S_TRUNK_C, p && c) // probed while acquired
transition(S_TIP_D, S_TRUNK_CD, c) // acquire
transition(S_TIP_CD, S_INVALID, c && p)
transition(S_TIP_CD, S_BRANCH, c && p) // losing D is only possible via probe
transition(S_TIP_CD, S_BRANCH_C, c && p) // losing D is only possible via probe
transition(S_TIP_CD, S_TIP, c && p) // probed while MMIO read || outer probe.toT (optional)
transition(S_TIP_CD, S_TIP_C, false) // we would go S_TRUNK_C instead
transition(S_TIP_CD, S_TIP_D, c) // MMIO write || clean release (optional)
transition(S_TIP_CD, S_TRUNK_C, c && p) // probed while acquire
transition(S_TIP_CD, S_TRUNK_CD, c) // acquire
transition(S_TRUNK_C, S_INVALID, c && p)
transition(S_TRUNK_C, S_BRANCH, c && p) // losing TIP only possible via probe
transition(S_TRUNK_C, S_BRANCH_C, c && p) // losing TIP only possible via probe
transition(S_TRUNK_C, S_TIP, c) // MMIO read || clean release (optional)
transition(S_TRUNK_C, S_TIP_C, c) // bounce shared
transition(S_TRUNK_C, S_TIP_D, c) // dirty release
transition(S_TRUNK_C, S_TIP_CD, c) // dirty bounce shared
transition(S_TRUNK_C, S_TRUNK_CD, c) // dirty bounce
transition(S_TRUNK_CD, S_INVALID, c && p)
transition(S_TRUNK_CD, S_BRANCH, c && p) // losing D only possible via probe
transition(S_TRUNK_CD, S_BRANCH_C, c && p) // losing D only possible via probe
transition(S_TRUNK_CD, S_TIP, c && p) // probed while MMIO read || outer probe.toT (optional)
transition(S_TRUNK_CD, S_TIP_C, false) // we would go S_TRUNK_C instead
transition(S_TRUNK_CD, S_TIP_D, c) // dirty release
transition(S_TRUNK_CD, S_TIP_CD, c) // bounce shared
transition(S_TRUNK_CD, S_TRUNK_C, c && p) // probed while acquire
}
// Handle response messages
val probe_bit = params.clientBit(io.sinkc.bits.source)
val last_probe = (probes_done | probe_bit) === (meta.clients & ~excluded_client)
val probe_toN = isToN(io.sinkc.bits.param)
if (!params.firstLevel) when (io.sinkc.valid) {
params.ccover( probe_toN && io.schedule.bits.b.bits.param === toB, "MSHR_PROBE_FULL", "Client downgraded to N when asked only to do B")
params.ccover(!probe_toN && io.schedule.bits.b.bits.param === toB, "MSHR_PROBE_HALF", "Client downgraded to B when asked only to do B")
// Caution: the probe matches us only in set.
// We would never allow an outer probe to nest until both w_[rp]probeack complete, so
// it is safe to just unguardedly update the probe FSM.
probes_done := probes_done | probe_bit
probes_toN := probes_toN | Mux(probe_toN, probe_bit, 0.U)
probes_noT := probes_noT || io.sinkc.bits.param =/= TtoT
w_rprobeackfirst := w_rprobeackfirst || last_probe
w_rprobeacklast := w_rprobeacklast || (last_probe && io.sinkc.bits.last)
w_pprobeackfirst := w_pprobeackfirst || last_probe
w_pprobeacklast := w_pprobeacklast || (last_probe && io.sinkc.bits.last)
// Allow wormhole routing from sinkC if the first request beat has offset 0
val set_pprobeack = last_probe && (io.sinkc.bits.last || request.offset === 0.U)
w_pprobeack := w_pprobeack || set_pprobeack
params.ccover(!set_pprobeack && w_rprobeackfirst, "MSHR_PROBE_SERIAL", "Sequential routing of probe response data")
params.ccover( set_pprobeack && w_rprobeackfirst, "MSHR_PROBE_WORMHOLE", "Wormhole routing of probe response data")
// However, meta-data updates need to be done more cautiously
when (meta.state =/= INVALID && io.sinkc.bits.tag === meta.tag && io.sinkc.bits.data) { meta.dirty := true.B } // !!!
}
when (io.sinkd.valid) {
when (io.sinkd.bits.opcode === Grant || io.sinkd.bits.opcode === GrantData) {
sink := io.sinkd.bits.sink
w_grantfirst := true.B
w_grantlast := io.sinkd.bits.last
// Record if we need to prevent taking ownership
bad_grant := io.sinkd.bits.denied
// Allow wormhole routing for requests whose first beat has offset 0
w_grant := request.offset === 0.U || io.sinkd.bits.last
params.ccover(io.sinkd.bits.opcode === GrantData && request.offset === 0.U, "MSHR_GRANT_WORMHOLE", "Wormhole routing of grant response data")
params.ccover(io.sinkd.bits.opcode === GrantData && request.offset =/= 0.U, "MSHR_GRANT_SERIAL", "Sequential routing of grant response data")
gotT := io.sinkd.bits.param === toT
}
.elsewhen (io.sinkd.bits.opcode === ReleaseAck) {
w_releaseack := true.B
}
}
when (io.sinke.valid) {
w_grantack := true.B
}
// Bootstrap new requests
val allocate_as_full = WireInit(new FullRequest(params), init = io.allocate.bits)
val new_meta = Mux(io.allocate.valid && io.allocate.bits.repeat, final_meta_writeback, io.directory.bits)
val new_request = Mux(io.allocate.valid, allocate_as_full, request)
val new_needT = needT(new_request.opcode, new_request.param)
val new_clientBit = params.clientBit(new_request.source)
val new_skipProbe = Mux(skipProbeN(new_request.opcode, params.cache.hintsSkipProbe), new_clientBit, 0.U)
val prior = cacheState(final_meta_writeback, true.B)
def bypass(from: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) {
if (cover) {
params.ccover(prior === from.code, s"MSHR_${from}_BYPASS", s"State bypass transition from ${from} ${cfg}")
} else {
assert(!(prior === from.code), cf"State bypass from ${from} should be impossible ${cfg}")
}
}
when (io.allocate.valid && io.allocate.bits.repeat) {
bypass(S_INVALID, f || p) // Can lose permissions (probe/flush)
bypass(S_BRANCH, b) // MMIO read to read-only device
bypass(S_BRANCH_C, b && c) // you need children to become C
bypass(S_TIP, true) // MMIO read || clean release can lead to this state
bypass(S_TIP_C, c) // needs two clients || client + mmio || downgrading client
bypass(S_TIP_CD, c) // needs two clients || client + mmio || downgrading client
bypass(S_TIP_D, true) // MMIO write || dirty release lead here
bypass(S_TRUNK_C, c) // acquire for write
bypass(S_TRUNK_CD, c) // dirty release then reacquire
}
when (io.allocate.valid) {
assert (!request_valid || (no_wait && io.schedule.fire))
request_valid := true.B
request := io.allocate.bits
}
// Create execution plan
when (io.directory.valid || (io.allocate.valid && io.allocate.bits.repeat)) {
meta_valid := true.B
meta := new_meta
probes_done := 0.U
probes_toN := 0.U
probes_noT := false.B
gotT := false.B
bad_grant := false.B
// These should already be either true or turning true
// We clear them here explicitly to simplify the mux tree
s_rprobe := true.B
w_rprobeackfirst := true.B
w_rprobeacklast := true.B
s_release := true.B
w_releaseack := true.B
s_pprobe := true.B
s_acquire := true.B
s_flush := true.B
w_grantfirst := true.B
w_grantlast := true.B
w_grant := true.B
w_pprobeackfirst := true.B
w_pprobeacklast := true.B
w_pprobeack := true.B
s_probeack := true.B
s_grantack := true.B
s_execute := true.B
w_grantack := true.B
s_writeback := true.B
// For C channel requests (ie: Release[Data])
when (new_request.prio(2) && (!params.firstLevel).B) {
s_execute := false.B
// Do we need to go dirty?
when (new_request.opcode(0) && !new_meta.dirty) {
s_writeback := false.B
}
// Does our state change?
when (isToB(new_request.param) && new_meta.state === TRUNK) {
s_writeback := false.B
}
// Do our clients change?
when (isToN(new_request.param) && (new_meta.clients & new_clientBit) =/= 0.U) {
s_writeback := false.B
}
assert (new_meta.hit)
}
// For X channel requests (ie: flush)
.elsewhen (new_request.control && params.control.B) { // new_request.prio(0)
s_flush := false.B
// Do we need to actually do something?
when (new_meta.hit) {
s_release := false.B
w_releaseack := false.B
// Do we need to shoot-down inner caches?
when ((!params.firstLevel).B && (new_meta.clients =/= 0.U)) {
s_rprobe := false.B
w_rprobeackfirst := false.B
w_rprobeacklast := false.B
}
}
}
// For A channel requests
.otherwise { // new_request.prio(0) && !new_request.control
s_execute := false.B
// Do we need an eviction?
when (!new_meta.hit && new_meta.state =/= INVALID) {
s_release := false.B
w_releaseack := false.B
// Do we need to shoot-down inner caches?
when ((!params.firstLevel).B & (new_meta.clients =/= 0.U)) {
s_rprobe := false.B
w_rprobeackfirst := false.B
w_rprobeacklast := false.B
}
}
// Do we need an acquire?
when (!new_meta.hit || (new_meta.state === BRANCH && new_needT)) {
s_acquire := false.B
w_grantfirst := false.B
w_grantlast := false.B
w_grant := false.B
s_grantack := false.B
s_writeback := false.B
}
// Do we need a probe?
when ((!params.firstLevel).B && (new_meta.hit &&
(new_needT || new_meta.state === TRUNK) &&
(new_meta.clients & ~new_skipProbe) =/= 0.U)) {
s_pprobe := false.B
w_pprobeackfirst := false.B
w_pprobeacklast := false.B
w_pprobeack := false.B
s_writeback := false.B
}
// Do we need a grantack?
when (new_request.opcode === AcquireBlock || new_request.opcode === AcquirePerm) {
w_grantack := false.B
s_writeback := false.B
}
// Becomes dirty?
when (!new_request.opcode(2) && new_meta.hit && !new_meta.dirty) {
s_writeback := false.B
}
}
}
}
File Parameters.scala:
/*
* Copyright 2019 SiFive, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You should have received a copy of LICENSE.Apache2 along with
* this software. If not, you may obtain a copy at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package sifive.blocks.inclusivecache
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
import freechips.rocketchip.util.property.cover
import scala.math.{min,max}
case class CacheParameters(
level: Int,
ways: Int,
sets: Int,
blockBytes: Int,
beatBytes: Int, // inner
hintsSkipProbe: Boolean)
{
require (ways > 0)
require (sets > 0)
require (blockBytes > 0 && isPow2(blockBytes))
require (beatBytes > 0 && isPow2(beatBytes))
require (blockBytes >= beatBytes)
val blocks = ways * sets
val sizeBytes = blocks * blockBytes
val blockBeats = blockBytes/beatBytes
}
case class InclusiveCachePortParameters(
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)
{
def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new TLBuffer(a, b, c, d, e))
}
object InclusiveCachePortParameters
{
val none = InclusiveCachePortParameters(
a = BufferParams.none,
b = BufferParams.none,
c = BufferParams.none,
d = BufferParams.none,
e = BufferParams.none)
val full = InclusiveCachePortParameters(
a = BufferParams.default,
b = BufferParams.default,
c = BufferParams.default,
d = BufferParams.default,
e = BufferParams.default)
// This removes feed-through paths from C=>A and A=>C
val fullC = InclusiveCachePortParameters(
a = BufferParams.none,
b = BufferParams.none,
c = BufferParams.default,
d = BufferParams.none,
e = BufferParams.none)
val flowAD = InclusiveCachePortParameters(
a = BufferParams.flow,
b = BufferParams.none,
c = BufferParams.none,
d = BufferParams.flow,
e = BufferParams.none)
val flowAE = InclusiveCachePortParameters(
a = BufferParams.flow,
b = BufferParams.none,
c = BufferParams.none,
d = BufferParams.none,
e = BufferParams.flow)
// For innerBuf:
// SinkA: no restrictions, flows into scheduler+putbuffer
// SourceB: no restrictions, flows out of scheduler
// sinkC: no restrictions, flows into scheduler+putbuffer & buffered to bankedStore
// SourceD: no restrictions, flows out of bankedStore/regout
// SinkE: no restrictions, flows into scheduler
//
// ... so while none is possible, you probably want at least flowAC to cut ready
// from the scheduler delay and flowD to ease SourceD back-pressure
// For outerBufer:
// SourceA: must not be pipe, flows out of scheduler
// SinkB: no restrictions, flows into scheduler
// SourceC: pipe is useless, flows out of bankedStore/regout, parameter depth ignored
// SinkD: no restrictions, flows into scheduler & bankedStore
// SourceE: must not be pipe, flows out of scheduler
//
// ... AE take the channel ready into the scheduler, so you need at least flowAE
}
case class InclusiveCacheMicroParameters(
writeBytes: Int, // backing store update granularity
memCycles: Int = 40, // # of L2 clock cycles for a memory round-trip (50ns @ 800MHz)
portFactor: Int = 4, // numSubBanks = (widest TL port * portFactor) / writeBytes
dirReg: Boolean = false,
innerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.fullC, // or none
outerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.full) // or flowAE
{
require (writeBytes > 0 && isPow2(writeBytes))
require (memCycles > 0)
require (portFactor >= 2) // for inner RMW and concurrent outer Relase + Grant
}
case class InclusiveCacheControlParameters(
address: BigInt,
beatBytes: Int,
bankedControl: Boolean)
case class InclusiveCacheParameters(
cache: CacheParameters,
micro: InclusiveCacheMicroParameters,
control: Boolean,
inner: TLEdgeIn,
outer: TLEdgeOut)(implicit val p: Parameters)
{
require (cache.ways > 1)
require (cache.sets > 1 && isPow2(cache.sets))
require (micro.writeBytes <= inner.manager.beatBytes)
require (micro.writeBytes <= outer.manager.beatBytes)
require (inner.manager.beatBytes <= cache.blockBytes)
require (outer.manager.beatBytes <= cache.blockBytes)
// Require that all cached address ranges have contiguous blocks
outer.manager.managers.flatMap(_.address).foreach { a =>
require (a.alignment >= cache.blockBytes)
}
// If we are the first level cache, we do not need to support inner-BCE
val firstLevel = !inner.client.clients.exists(_.supports.probe)
// If we are the last level cache, we do not need to support outer-B
val lastLevel = !outer.manager.managers.exists(_.regionType > RegionType.UNCACHED)
require (lastLevel)
// Provision enough resources to achieve full throughput with missing single-beat accesses
val mshrs = InclusiveCacheParameters.all_mshrs(cache, micro)
val secondary = max(mshrs, micro.memCycles - mshrs)
val putLists = micro.memCycles // allow every request to be single beat
val putBeats = max(2*cache.blockBeats, micro.memCycles)
val relLists = 2
val relBeats = relLists*cache.blockBeats
val flatAddresses = AddressSet.unify(outer.manager.managers.flatMap(_.address))
val pickMask = AddressDecoder(flatAddresses.map(Seq(_)), flatAddresses.map(_.mask).reduce(_|_))
def bitOffsets(x: BigInt, offset: Int = 0, tail: List[Int] = List.empty[Int]): List[Int] =
if (x == 0) tail.reverse else bitOffsets(x >> 1, offset + 1, if ((x & 1) == 1) offset :: tail else tail)
val addressMapping = bitOffsets(pickMask)
val addressBits = addressMapping.size
// println(s"addresses: ${flatAddresses} => ${pickMask} => ${addressBits}")
val allClients = inner.client.clients.size
val clientBitsRaw = inner.client.clients.filter(_.supports.probe).size
val clientBits = max(1, clientBitsRaw)
val stateBits = 2
val wayBits = log2Ceil(cache.ways)
val setBits = log2Ceil(cache.sets)
val offsetBits = log2Ceil(cache.blockBytes)
val tagBits = addressBits - setBits - offsetBits
val putBits = log2Ceil(max(putLists, relLists))
require (tagBits > 0)
require (offsetBits > 0)
val innerBeatBits = (offsetBits - log2Ceil(inner.manager.beatBytes)) max 1
val outerBeatBits = (offsetBits - log2Ceil(outer.manager.beatBytes)) max 1
val innerMaskBits = inner.manager.beatBytes / micro.writeBytes
val outerMaskBits = outer.manager.beatBytes / micro.writeBytes
def clientBit(source: UInt): UInt = {
if (clientBitsRaw == 0) {
0.U
} else {
Cat(inner.client.clients.filter(_.supports.probe).map(_.sourceId.contains(source)).reverse)
}
}
def clientSource(bit: UInt): UInt = {
if (clientBitsRaw == 0) {
0.U
} else {
Mux1H(bit, inner.client.clients.filter(_.supports.probe).map(c => c.sourceId.start.U))
}
}
def parseAddress(x: UInt): (UInt, UInt, UInt) = {
val offset = Cat(addressMapping.map(o => x(o,o)).reverse)
val set = offset >> offsetBits
val tag = set >> setBits
(tag(tagBits-1, 0), set(setBits-1, 0), offset(offsetBits-1, 0))
}
def widen(x: UInt, width: Int): UInt = {
val y = x | 0.U(width.W)
assert (y >> width === 0.U)
y(width-1, 0)
}
def expandAddress(tag: UInt, set: UInt, offset: UInt): UInt = {
val base = Cat(widen(tag, tagBits), widen(set, setBits), widen(offset, offsetBits))
val bits = Array.fill(outer.bundle.addressBits) { 0.U(1.W) }
addressMapping.zipWithIndex.foreach { case (a, i) => bits(a) = base(i,i) }
Cat(bits.reverse)
}
def restoreAddress(expanded: UInt): UInt = {
val missingBits = flatAddresses
.map { a => (a.widen(pickMask).base, a.widen(~pickMask)) } // key is the bits to restore on match
.groupBy(_._1)
.view
.mapValues(_.map(_._2))
val muxMask = AddressDecoder(missingBits.values.toList)
val mux = missingBits.toList.map { case (bits, addrs) =>
val widen = addrs.map(_.widen(~muxMask))
val matches = AddressSet
.unify(widen.distinct)
.map(_.contains(expanded))
.reduce(_ || _)
(matches, bits.U)
}
expanded | Mux1H(mux)
}
def dirReg[T <: Data](x: T, en: Bool = true.B): T = {
if (micro.dirReg) RegEnable(x, en) else x
}
def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) =
cover(cond, "CCACHE_L" + cache.level + "_" + label, "MemorySystem;;" + desc)
}
object MetaData
{
val stateBits = 2
def INVALID: UInt = 0.U(stateBits.W) // way is empty
def BRANCH: UInt = 1.U(stateBits.W) // outer slave cache is trunk
def TRUNK: UInt = 2.U(stateBits.W) // unique inner master cache is trunk
def TIP: UInt = 3.U(stateBits.W) // we are trunk, inner masters are branch
// Does a request need trunk?
def needT(opcode: UInt, param: UInt): Bool = {
!opcode(2) ||
(opcode === TLMessages.Hint && param === TLHints.PREFETCH_WRITE) ||
((opcode === TLMessages.AcquireBlock || opcode === TLMessages.AcquirePerm) && param =/= TLPermissions.NtoB)
}
// Does a request prove the client need not be probed?
def skipProbeN(opcode: UInt, hintsSkipProbe: Boolean): Bool = {
// Acquire(toB) and Get => is N, so no probe
// Acquire(*toT) => is N or B, but need T, so no probe
// Hint => could be anything, so probe IS needed, if hintsSkipProbe is enabled, skip probe the same client
// Put* => is N or B, so probe IS needed
opcode === TLMessages.AcquireBlock || opcode === TLMessages.AcquirePerm || opcode === TLMessages.Get || (opcode === TLMessages.Hint && hintsSkipProbe.B)
}
def isToN(param: UInt): Bool = {
param === TLPermissions.TtoN || param === TLPermissions.BtoN || param === TLPermissions.NtoN
}
def isToB(param: UInt): Bool = {
param === TLPermissions.TtoB || param === TLPermissions.BtoB
}
}
object InclusiveCacheParameters
{
val lfsrBits = 10
val L2ControlAddress = 0x2010000
val L2ControlSize = 0x1000
def out_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = {
// We need 2-3 normal MSHRs to cover the Directory latency
// To fully exploit memory bandwidth-delay-product, we need memCyles/blockBeats MSHRs
max(if (micro.dirReg) 3 else 2, (micro.memCycles + cache.blockBeats - 1) / cache.blockBeats)
}
def all_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int =
// We need a dedicated MSHR for B+C each
2 + out_mshrs(cache, micro)
}
class InclusiveCacheBundle(params: InclusiveCacheParameters) extends Bundle
| module MSHR_2( // @[MSHR.scala:84:7]
input clock, // @[MSHR.scala:84:7]
input reset, // @[MSHR.scala:84:7]
input io_allocate_valid, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_0, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_1, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_2, // @[MSHR.scala:86:14]
input io_allocate_bits_control, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_source, // @[MSHR.scala:86:14]
input [12:0] io_allocate_bits_tag, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14]
input [9:0] io_allocate_bits_set, // @[MSHR.scala:86:14]
input io_allocate_bits_repeat, // @[MSHR.scala:86:14]
input io_directory_valid, // @[MSHR.scala:86:14]
input io_directory_bits_dirty, // @[MSHR.scala:86:14]
input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14]
input io_directory_bits_clients, // @[MSHR.scala:86:14]
input [12:0] io_directory_bits_tag, // @[MSHR.scala:86:14]
input io_directory_bits_hit, // @[MSHR.scala:86:14]
input [2:0] io_directory_bits_way, // @[MSHR.scala:86:14]
output io_status_valid, // @[MSHR.scala:86:14]
output [9:0] io_status_bits_set, // @[MSHR.scala:86:14]
output [12:0] io_status_bits_tag, // @[MSHR.scala:86:14]
output [2:0] io_status_bits_way, // @[MSHR.scala:86:14]
output io_status_bits_blockB, // @[MSHR.scala:86:14]
output io_status_bits_nestB, // @[MSHR.scala:86:14]
output io_status_bits_blockC, // @[MSHR.scala:86:14]
output io_status_bits_nestC, // @[MSHR.scala:86:14]
input io_schedule_ready, // @[MSHR.scala:86:14]
output io_schedule_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_a_valid, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14]
output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14]
output io_schedule_bits_b_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14]
output io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14]
output io_schedule_bits_c_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14]
output io_schedule_bits_d_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_0, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14]
output io_schedule_bits_e_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14]
output io_schedule_bits_x_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14]
output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14]
output io_schedule_bits_reload, // @[MSHR.scala:86:14]
input io_sinkc_valid, // @[MSHR.scala:86:14]
input io_sinkc_bits_last, // @[MSHR.scala:86:14]
input [9:0] io_sinkc_bits_set, // @[MSHR.scala:86:14]
input [12:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14]
input [5:0] io_sinkc_bits_source, // @[MSHR.scala:86:14]
input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14]
input io_sinkc_bits_data, // @[MSHR.scala:86:14]
input io_sinkd_valid, // @[MSHR.scala:86:14]
input io_sinkd_bits_last, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_source, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14]
input io_sinkd_bits_denied, // @[MSHR.scala:86:14]
input io_sinke_valid, // @[MSHR.scala:86:14]
input [2:0] io_sinke_bits_sink, // @[MSHR.scala:86:14]
input [9:0] io_nestedwb_set, // @[MSHR.scala:86:14]
input [12:0] io_nestedwb_tag, // @[MSHR.scala:86:14]
input io_nestedwb_b_toN, // @[MSHR.scala:86:14]
input io_nestedwb_b_toB, // @[MSHR.scala:86:14]
input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14]
input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14]
);
wire [12:0] final_meta_writeback_tag; // @[MSHR.scala:215:38]
wire final_meta_writeback_clients; // @[MSHR.scala:215:38]
wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38]
wire final_meta_writeback_dirty; // @[MSHR.scala:215:38]
wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_0_0 = io_allocate_bits_prio_0; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7]
wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7]
wire [12:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7]
wire [9:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7]
wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7]
wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7]
wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7]
wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7]
wire io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7]
wire [12:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7]
wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7]
wire [2:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7]
wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7]
wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7]
wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7]
wire [9:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7]
wire [12:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7]
wire [5:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7]
wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7]
wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7]
wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7]
wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7]
wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7]
wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7]
wire [2:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7]
wire [9:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7]
wire [12:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7]
wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7]
wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7]
wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7]
wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_a_bits_source = 3'h0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_source = 3'h0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_sink = 3'h0; // @[MSHR.scala:84:7]
wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7]
wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68]
wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80]
wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21]
wire invalid_clients = 1'h0; // @[MSHR.scala:268:21]
wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137]
wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11]
wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137]
wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11]
wire [12:0] invalid_tag = 13'h0; // @[MSHR.scala:268:21]
wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21]
wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70]
wire allocate_as_full_prio_0 = io_allocate_bits_prio_0_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34]
wire [12:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34]
wire [9:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34]
wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40]
wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93]
wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28]
wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39]
wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105]
wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55]
wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91]
wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41]
wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41]
wire [12:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41]
wire _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51]
wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64]
wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41]
wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41]
wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57]
wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41]
wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43]
wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40]
wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66]
wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41]
wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41]
wire _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41]
wire [12:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41]
wire no_wait; // @[MSHR.scala:183:83]
wire [9:0] io_status_bits_set_0; // @[MSHR.scala:84:7]
wire [12:0] io_status_bits_tag_0; // @[MSHR.scala:84:7]
wire [2:0] io_status_bits_way_0; // @[MSHR.scala:84:7]
wire io_status_bits_blockB_0; // @[MSHR.scala:84:7]
wire io_status_bits_nestB_0; // @[MSHR.scala:84:7]
wire io_status_bits_blockC_0; // @[MSHR.scala:84:7]
wire io_status_bits_nestC_0; // @[MSHR.scala:84:7]
wire io_status_valid_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_0_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7]
wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7]
wire io_schedule_valid_0; // @[MSHR.scala:84:7]
reg request_valid; // @[MSHR.scala:97:30]
assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30]
reg request_prio_0; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_0_0 = request_prio_0; // @[MSHR.scala:84:7, :98:20]
reg request_prio_1; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20]
reg request_prio_2; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20]
reg request_control; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20]
reg [2:0] request_opcode; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20]
reg [2:0] request_param; // @[MSHR.scala:98:20]
reg [2:0] request_size; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_source; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20]
reg [12:0] request_tag; // @[MSHR.scala:98:20]
assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_offset; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_put; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20]
reg [9:0] request_set; // @[MSHR.scala:98:20]
assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
reg meta_valid; // @[MSHR.scala:99:27]
reg meta_dirty; // @[MSHR.scala:100:17]
assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17]
reg [1:0] meta_state; // @[MSHR.scala:100:17]
reg meta_clients; // @[MSHR.scala:100:17]
wire _meta_no_clients_T = meta_clients; // @[MSHR.scala:100:17, :220:39]
wire evict_c = meta_clients; // @[MSHR.scala:100:17, :315:27]
wire before_c = meta_clients; // @[MSHR.scala:100:17, :315:27]
reg [12:0] meta_tag; // @[MSHR.scala:100:17]
assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17]
reg meta_hit; // @[MSHR.scala:100:17]
reg [2:0] meta_way; // @[MSHR.scala:100:17]
assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
wire [2:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38]
reg s_rprobe; // @[MSHR.scala:121:33]
reg w_rprobeackfirst; // @[MSHR.scala:122:33]
reg w_rprobeacklast; // @[MSHR.scala:123:33]
reg s_release; // @[MSHR.scala:124:33]
reg w_releaseack; // @[MSHR.scala:125:33]
reg s_pprobe; // @[MSHR.scala:126:33]
reg s_acquire; // @[MSHR.scala:127:33]
reg s_flush; // @[MSHR.scala:128:33]
reg w_grantfirst; // @[MSHR.scala:129:33]
reg w_grantlast; // @[MSHR.scala:130:33]
reg w_grant; // @[MSHR.scala:131:33]
reg w_pprobeackfirst; // @[MSHR.scala:132:33]
reg w_pprobeacklast; // @[MSHR.scala:133:33]
reg w_pprobeack; // @[MSHR.scala:134:33]
reg s_grantack; // @[MSHR.scala:136:33]
reg s_execute; // @[MSHR.scala:137:33]
reg w_grantack; // @[MSHR.scala:138:33]
reg s_writeback; // @[MSHR.scala:139:33]
reg [2:0] sink; // @[MSHR.scala:147:17]
assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17]
reg gotT; // @[MSHR.scala:148:17]
reg bad_grant; // @[MSHR.scala:149:22]
assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22]
reg probes_done; // @[MSHR.scala:150:24]
reg probes_toN; // @[MSHR.scala:151:23]
reg probes_noT; // @[MSHR.scala:152:23]
wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28]
wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45]
wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62]
wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 | _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}]
wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82]
wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 | _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}]
wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103]
wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}]
assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T | _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}]
assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40]
wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39]
wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}]
wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}]
wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96]
assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}]
assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93]
assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28]
assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28]
wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43]
wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64]
wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T | _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}]
wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85]
wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 | _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}]
assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}]
assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39]
wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33]
wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}]
wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}]
assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}]
assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83]
wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31]
wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}]
assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}]
assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55]
wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31]
wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44]
assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T | _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}]
assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41]
wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32]
wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}]
assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}]
assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64]
wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31]
wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}]
assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}]
assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57]
wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31]
assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}]
assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43]
wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31]
assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}]
assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40]
wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34]
wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}]
wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70]
wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}]
assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 | _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}]
assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66]
wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 | io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49]
wire _io_schedule_valid_T_1 = _io_schedule_valid_T | io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}]
wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 | io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}]
wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 | io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49]
wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 | io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}]
assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 | io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}]
assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105]
wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71]
wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71]
wire _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71]
wire after_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27]
wire prior_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27]
wire [12:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71]
wire final_meta_writeback_hit; // @[MSHR.scala:215:38]
wire req_clientBit = request_source == 6'h21; // @[Parameters.scala:46:9]
wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12]
wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12]
wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}]
wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13]
wire _req_needT_T_2; // @[Parameters.scala:270:13]
assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13]
wire _excluded_client_T_6; // @[Parameters.scala:279:117]
assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117]
wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42]
wire _req_needT_T_3; // @[Parameters.scala:270:42]
assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42]
wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11]
assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11]
wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42]
wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}]
wire _req_needT_T_5 = _req_needT_T_1 | _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33]
wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14]
wire _req_needT_T_6; // @[Parameters.scala:271:14]
assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14]
wire _req_acquire_T; // @[MSHR.scala:219:36]
assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14]
wire _excluded_client_T_1; // @[Parameters.scala:279:12]
assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12]
wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52]
wire _req_needT_T_8 = _req_needT_T_6 | _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}]
wire _req_needT_T_9 = |request_param; // @[Parameters.scala:271:89]
wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}]
wire req_needT = _req_needT_T_5 | _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80]
wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52]
wire req_acquire = _req_acquire_T | _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}]
wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}]
wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81]
wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}]
wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}]
wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}]
wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65]
wire _final_meta_writeback_dirty_T_1 = meta_dirty | _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}]
wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55]
wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78]
wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78]
assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78]
wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70]
assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70]
wire _evict_T_2; // @[MSHR.scala:317:26]
assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26]
wire _before_T_1; // @[MSHR.scala:317:26]
assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26]
wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}]
wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}]
wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43]
wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43]
assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43]
wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43]
wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T | _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}]
wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75]
wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 | _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}]
wire _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 & req_clientBit; // @[Parameters.scala:46:9]
wire _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}]
wire _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}]
wire _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54]
wire _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}]
wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45]
wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}]
wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 | _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}]
wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40]
wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40]
assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40]
wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65]
assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65]
wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41]
wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}]
wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72]
wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}]
wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70]
wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70]
assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70]
wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53]
assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53]
wire _evict_T_1; // @[MSHR.scala:317:26]
assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26]
wire _before_T; // @[MSHR.scala:317:26]
assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26]
wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70]
wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70]
wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55]
wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70]
wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70]
wire _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66]
wire _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}]
wire _final_meta_writeback_clients_T_12 = meta_hit & _final_meta_writeback_clients_T_11; // @[MSHR.scala:100:17, :245:{40,64}]
wire _final_meta_writeback_clients_T_13 = req_acquire & req_clientBit; // @[Parameters.scala:46:9]
wire _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 | _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40]
assign final_meta_writeback_tag = request_prio_2 | request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30]
wire _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54]
wire _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}]
assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 | ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21]
assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21]
assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36]
assign final_meta_writeback_clients = bad_grant ? meta_hit & _final_meta_writeback_clients_T_16 : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36]
wire _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:46:9]
wire _honour_BtoT_T_1 = _honour_BtoT_T; // @[MSHR.scala:276:{47,64}]
wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}]
wire _excluded_client_T = meta_hit & request_prio_0; // @[MSHR.scala:98:20, :100:17, :279:38]
wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50]
wire _excluded_client_T_3 = _excluded_client_T_1 | _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}]
wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87]
wire _excluded_client_T_5 = _excluded_client_T_3 | _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}]
wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}]
wire _excluded_client_T_9 = _excluded_client_T & _excluded_client_T_8; // @[Parameters.scala:279:106]
wire excluded_client = _excluded_client_T_9 & req_clientBit; // @[Parameters.scala:46:9]
wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56]
wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70]
assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}]
wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51]
wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55]
wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52]
wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 | _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}]
wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}]
assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T | _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38]
assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91]
wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42]
wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70]
wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}]
assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}]
assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41]
wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42]
assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}]
assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41]
wire _io_schedule_bits_b_bits_clients_T = ~excluded_client; // @[MSHR.scala:279:28, :289:53]
assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients & _io_schedule_bits_b_bits_clients_T; // @[MSHR.scala:100:17, :289:{51,53}]
assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51]
assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41]
assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41]
assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}]
assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41]
wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42]
wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53]
wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53]
wire _io_schedule_bits_d_bits_param_T_3 = ~(|request_param); // @[Parameters.scala:271:89]
wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53]
wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53]
wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79]
assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41]
wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42]
assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_clients = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 13'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}]
assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41]
wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32]
wire [3:0] evict; // @[MSHR.scala:314:26]
wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32]
wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32]
wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32]
assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32]
wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32]
assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32]
wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26]
wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39]
wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39]
assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39]
wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39]
assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39]
wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76]
wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76]
assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76]
wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76]
assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76]
wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _evict_T_4 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26]
wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32]
assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}]
wire [3:0] before_0; // @[MSHR.scala:314:26]
wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32]
wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26]
wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _before_T_3 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26]
wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11]
assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}]
wire [3:0] after; // @[MSHR.scala:314:26]
wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26]
wire _after_T; // @[MSHR.scala:317:26]
assign _after_T = _GEN_9; // @[MSHR.scala:317:26]
wire _prior_T; // @[MSHR.scala:317:26]
assign _prior_T = _GEN_9; // @[MSHR.scala:317:26]
wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32]
wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26]
wire _after_T_1; // @[MSHR.scala:317:26]
assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26]
wire _prior_T_1; // @[MSHR.scala:317:26]
assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26]
wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32]
wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32]
assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32]
wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32]
assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32]
wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26]
wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39]
wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39]
assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39]
wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39]
assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39]
wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76]
wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76]
assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76]
wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76]
assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76]
wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26]
wire _after_T_3; // @[MSHR.scala:317:26]
assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26]
wire _prior_T_3; // @[MSHR.scala:317:26]
assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26]
assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26]
wire probe_bit = io_sinkc_bits_source_0 == 6'h21; // @[Parameters.scala:46:9]
wire _GEN_15 = probes_done | probe_bit; // @[Parameters.scala:46:9]
wire _last_probe_T; // @[MSHR.scala:459:33]
assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33]
wire _probes_done_T; // @[MSHR.scala:467:32]
assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32]
wire _last_probe_T_1 = ~excluded_client; // @[MSHR.scala:279:28, :289:53, :459:66]
wire _last_probe_T_2 = meta_clients & _last_probe_T_1; // @[MSHR.scala:100:17, :459:{64,66}]
wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}]
wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11]
wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43]
wire _probe_toN_T_2 = _probe_toN_T | _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}]
wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75]
wire probe_toN = _probe_toN_T_2 | _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}]
wire _probes_toN_T = probe_toN & probe_bit; // @[Parameters.scala:46:9]
wire _probes_toN_T_1 = probes_toN | _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}]
wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53]
wire _probes_noT_T_1 = probes_noT | _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}]
wire _w_rprobeackfirst_T = w_rprobeackfirst | last_probe; // @[MSHR.scala:122:33, :459:46, :470:42]
wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55]
wire _w_rprobeacklast_T; // @[MSHR.scala:471:55]
assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55]
wire _w_pprobeacklast_T; // @[MSHR.scala:473:55]
assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55]
wire _w_rprobeacklast_T_1 = w_rprobeacklast | _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}]
wire _w_pprobeackfirst_T = w_pprobeackfirst | last_probe; // @[MSHR.scala:132:33, :459:46, :472:42]
wire _w_pprobeacklast_T_1 = w_pprobeacklast | _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}]
wire _set_pprobeack_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77]
wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 | _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}]
wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}]
wire _w_pprobeack_T = w_pprobeack | set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32]
wire _w_grant_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33]
wire _w_grant_T_1 = _w_grant_T | io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}]
wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35]
wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40]
wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [12:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [2:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_request_prio_0 = io_allocate_valid_0 ? allocate_as_full_prio_0 : request_prio_0; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [12:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [9:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12]
wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}]
wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13]
wire _new_needT_T_2; // @[Parameters.scala:270:13]
assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13]
wire _new_skipProbe_T_5; // @[Parameters.scala:279:117]
assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117]
wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42]
wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}]
wire _new_needT_T_5 = _new_needT_T_1 | _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33]
wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14]
wire _new_needT_T_6; // @[Parameters.scala:271:14]
assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14]
wire _new_skipProbe_T; // @[Parameters.scala:279:12]
assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12]
wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52]
wire _new_needT_T_8 = _new_needT_T_6 | _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}]
wire _new_needT_T_9 = |new_request_param; // @[Parameters.scala:271:89]
wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}]
wire new_needT = _new_needT_T_5 | _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80]
wire new_clientBit = new_request_source == 6'h21; // @[Parameters.scala:46:9]
wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50]
wire _new_skipProbe_T_2 = _new_skipProbe_T | _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}]
wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87]
wire _new_skipProbe_T_4 = _new_skipProbe_T_2 | _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}]
wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}]
wire new_skipProbe = _new_skipProbe_T_7 & new_clientBit; // @[Parameters.scala:46:9]
wire [3:0] prior; // @[MSHR.scala:314:26]
wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32]
wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26]
wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26]
wire _T_574 = io_directory_valid_0 | _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28] |
Generate the Verilog code corresponding to the following Chisel files.
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
| module OptimizationBarrier_TLBEntryData_8( // @[package.scala:267:30]
input clock, // @[package.scala:267:30]
input reset, // @[package.scala:267:30]
input [19:0] io_x_ppn, // @[package.scala:268:18]
input io_x_u, // @[package.scala:268:18]
input io_x_g, // @[package.scala:268:18]
input io_x_ae_ptw, // @[package.scala:268:18]
input io_x_ae_final, // @[package.scala:268:18]
input io_x_ae_stage2, // @[package.scala:268:18]
input io_x_pf, // @[package.scala:268:18]
input io_x_gf, // @[package.scala:268:18]
input io_x_sw, // @[package.scala:268:18]
input io_x_sx, // @[package.scala:268:18]
input io_x_sr, // @[package.scala:268:18]
input io_x_hw, // @[package.scala:268:18]
input io_x_hx, // @[package.scala:268:18]
input io_x_hr, // @[package.scala:268:18]
input io_x_pw, // @[package.scala:268:18]
input io_x_px, // @[package.scala:268:18]
input io_x_pr, // @[package.scala:268:18]
input io_x_ppp, // @[package.scala:268:18]
input io_x_pal, // @[package.scala:268:18]
input io_x_paa, // @[package.scala:268:18]
input io_x_eff, // @[package.scala:268:18]
input io_x_c, // @[package.scala:268:18]
input io_x_fragmented_superpage, // @[package.scala:268:18]
output io_y_u, // @[package.scala:268:18]
output io_y_ae_ptw, // @[package.scala:268:18]
output io_y_ae_final, // @[package.scala:268:18]
output io_y_ae_stage2, // @[package.scala:268:18]
output io_y_pf, // @[package.scala:268:18]
output io_y_gf, // @[package.scala:268:18]
output io_y_sw, // @[package.scala:268:18]
output io_y_sx, // @[package.scala:268:18]
output io_y_sr, // @[package.scala:268:18]
output io_y_hw, // @[package.scala:268:18]
output io_y_hx, // @[package.scala:268:18]
output io_y_hr, // @[package.scala:268:18]
output io_y_pw, // @[package.scala:268:18]
output io_y_px, // @[package.scala:268:18]
output io_y_pr, // @[package.scala:268:18]
output io_y_ppp, // @[package.scala:268:18]
output io_y_pal, // @[package.scala:268:18]
output io_y_paa, // @[package.scala:268:18]
output io_y_eff, // @[package.scala:268:18]
output io_y_c // @[package.scala:268:18]
);
wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30]
wire io_x_u_0 = io_x_u; // @[package.scala:267:30]
wire io_x_g_0 = io_x_g; // @[package.scala:267:30]
wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30]
wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30]
wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30]
wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30]
wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30]
wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30]
wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30]
wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30]
wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30]
wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30]
wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30]
wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30]
wire io_x_px_0 = io_x_px; // @[package.scala:267:30]
wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30]
wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30]
wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30]
wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30]
wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30]
wire io_x_c_0 = io_x_c; // @[package.scala:267:30]
wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30]
wire [19:0] io_y_ppn = io_x_ppn_0; // @[package.scala:267:30]
wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30]
wire io_y_g = io_x_g_0; // @[package.scala:267:30]
wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30]
wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30]
wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30]
wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30]
wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30]
wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30]
wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30]
wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30]
wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30]
wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30]
wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30]
wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30]
wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30]
wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30]
wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30]
wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30]
wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30]
wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30]
wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30]
wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30]
assign io_y_u = io_y_u_0; // @[package.scala:267:30]
assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30]
assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30]
assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30]
assign io_y_pf = io_y_pf_0; // @[package.scala:267:30]
assign io_y_gf = io_y_gf_0; // @[package.scala:267:30]
assign io_y_sw = io_y_sw_0; // @[package.scala:267:30]
assign io_y_sx = io_y_sx_0; // @[package.scala:267:30]
assign io_y_sr = io_y_sr_0; // @[package.scala:267:30]
assign io_y_hw = io_y_hw_0; // @[package.scala:267:30]
assign io_y_hx = io_y_hx_0; // @[package.scala:267:30]
assign io_y_hr = io_y_hr_0; // @[package.scala:267:30]
assign io_y_pw = io_y_pw_0; // @[package.scala:267:30]
assign io_y_px = io_y_px_0; // @[package.scala:267:30]
assign io_y_pr = io_y_pr_0; // @[package.scala:267:30]
assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30]
assign io_y_pal = io_y_pal_0; // @[package.scala:267:30]
assign io_y_paa = io_y_paa_0; // @[package.scala:267:30]
assign io_y_eff = io_y_eff_0; // @[package.scala:267:30]
assign io_y_c = io_y_c_0; // @[package.scala:267:30]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File InputUnit.scala:
package constellation.router
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.util._
import constellation.channel._
import constellation.routing.{FlowRoutingBundle}
import constellation.noc.{HasNoCParams}
class AbstractInputUnitIO(
val cParam: BaseChannelParams,
val outParams: Seq[ChannelParams],
val egressParams: Seq[EgressChannelParams],
)(implicit val p: Parameters) extends Bundle with HasRouterOutputParams {
val nodeId = cParam.destId
val router_req = Decoupled(new RouteComputerReq)
val router_resp = Input(new RouteComputerResp(outParams, egressParams))
val vcalloc_req = Decoupled(new VCAllocReq(cParam, outParams, egressParams))
val vcalloc_resp = Input(new VCAllocResp(outParams, egressParams))
val out_credit_available = Input(MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) }))
val salloc_req = Vec(cParam.destSpeedup, Decoupled(new SwitchAllocReq(outParams, egressParams)))
val out = Vec(cParam.destSpeedup, Valid(new SwitchBundle(outParams, egressParams)))
val debug = Output(new Bundle {
val va_stall = UInt(log2Ceil(cParam.nVirtualChannels).W)
val sa_stall = UInt(log2Ceil(cParam.nVirtualChannels).W)
})
val block = Input(Bool())
}
abstract class AbstractInputUnit(
val cParam: BaseChannelParams,
val outParams: Seq[ChannelParams],
val egressParams: Seq[EgressChannelParams]
)(implicit val p: Parameters) extends Module with HasRouterOutputParams with HasNoCParams {
val nodeId = cParam.destId
def io: AbstractInputUnitIO
}
class InputBuffer(cParam: ChannelParams)(implicit p: Parameters) extends Module {
val nVirtualChannels = cParam.nVirtualChannels
val io = IO(new Bundle {
val enq = Flipped(Vec(cParam.srcSpeedup, Valid(new Flit(cParam.payloadBits))))
val deq = Vec(cParam.nVirtualChannels, Decoupled(new BaseFlit(cParam.payloadBits)))
})
val useOutputQueues = cParam.useOutputQueues
val delims = if (useOutputQueues) {
cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize else 0).scanLeft(0)(_+_)
} else {
// If no queuing, have to add an additional slot since head == tail implies empty
// TODO this should be fixed, should use all slots available
cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize + 1 else 0).scanLeft(0)(_+_)
}
val starts = delims.dropRight(1).zipWithIndex.map { case (s,i) =>
if (cParam.virtualChannelParams(i).traversable) s else 0
}
val ends = delims.tail.zipWithIndex.map { case (s,i) =>
if (cParam.virtualChannelParams(i).traversable) s else 0
}
val fullSize = delims.last
// Ugly case. Use multiple queues
if ((cParam.srcSpeedup > 1 || cParam.destSpeedup > 1 || fullSize <= 1) || !cParam.unifiedBuffer) {
require(useOutputQueues)
val qs = cParam.virtualChannelParams.map(v => Module(new Queue(new BaseFlit(cParam.payloadBits), v.bufferSize)))
qs.zipWithIndex.foreach { case (q,i) =>
val sel = io.enq.map(f => f.valid && f.bits.virt_channel_id === i.U)
q.io.enq.valid := sel.orR
q.io.enq.bits.head := Mux1H(sel, io.enq.map(_.bits.head))
q.io.enq.bits.tail := Mux1H(sel, io.enq.map(_.bits.tail))
q.io.enq.bits.payload := Mux1H(sel, io.enq.map(_.bits.payload))
io.deq(i) <> q.io.deq
}
} else {
val mem = Mem(fullSize, new BaseFlit(cParam.payloadBits))
val heads = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W))))
val tails = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W))))
val empty = (heads zip tails).map(t => t._1 === t._2)
val qs = Seq.fill(nVirtualChannels) { Module(new Queue(new BaseFlit(cParam.payloadBits), 1, pipe=true)) }
qs.foreach(_.io.enq.valid := false.B)
qs.foreach(_.io.enq.bits := DontCare)
val vc_sel = UIntToOH(io.enq(0).bits.virt_channel_id)
val flit = Wire(new BaseFlit(cParam.payloadBits))
val direct_to_q = (Mux1H(vc_sel, qs.map(_.io.enq.ready)) && Mux1H(vc_sel, empty)) && useOutputQueues.B
flit.head := io.enq(0).bits.head
flit.tail := io.enq(0).bits.tail
flit.payload := io.enq(0).bits.payload
when (io.enq(0).valid && !direct_to_q) {
val tail = tails(io.enq(0).bits.virt_channel_id)
mem.write(tail, flit)
tails(io.enq(0).bits.virt_channel_id) := Mux(
tail === Mux1H(vc_sel, ends.map(_ - 1).map(_ max 0).map(_.U)),
Mux1H(vc_sel, starts.map(_.U)),
tail + 1.U)
} .elsewhen (io.enq(0).valid && direct_to_q) {
for (i <- 0 until nVirtualChannels) {
when (io.enq(0).bits.virt_channel_id === i.U) {
qs(i).io.enq.valid := true.B
qs(i).io.enq.bits := flit
}
}
}
if (useOutputQueues) {
val can_to_q = (0 until nVirtualChannels).map { i => !empty(i) && qs(i).io.enq.ready }
val to_q_oh = PriorityEncoderOH(can_to_q)
val to_q = OHToUInt(to_q_oh)
when (can_to_q.orR) {
val head = Mux1H(to_q_oh, heads)
heads(to_q) := Mux(
head === Mux1H(to_q_oh, ends.map(_ - 1).map(_ max 0).map(_.U)),
Mux1H(to_q_oh, starts.map(_.U)),
head + 1.U)
for (i <- 0 until nVirtualChannels) {
when (to_q_oh(i)) {
qs(i).io.enq.valid := true.B
qs(i).io.enq.bits := mem.read(head)
}
}
}
for (i <- 0 until nVirtualChannels) {
io.deq(i) <> qs(i).io.deq
}
} else {
qs.map(_.io.deq.ready := false.B)
val ready_sel = io.deq.map(_.ready)
val fire = io.deq.map(_.fire)
assert(PopCount(fire) <= 1.U)
val head = Mux1H(fire, heads)
when (fire.orR) {
val fire_idx = OHToUInt(fire)
heads(fire_idx) := Mux(
head === Mux1H(fire, ends.map(_ - 1).map(_ max 0).map(_.U)),
Mux1H(fire, starts.map(_.U)),
head + 1.U)
}
val read_flit = mem.read(head)
for (i <- 0 until nVirtualChannels) {
io.deq(i).valid := !empty(i)
io.deq(i).bits := read_flit
}
}
}
}
class InputUnit(cParam: ChannelParams, outParams: Seq[ChannelParams],
egressParams: Seq[EgressChannelParams],
combineRCVA: Boolean, combineSAST: Boolean
)
(implicit p: Parameters) extends AbstractInputUnit(cParam, outParams, egressParams)(p) {
val nVirtualChannels = cParam.nVirtualChannels
val virtualChannelParams = cParam.virtualChannelParams
class InputUnitIO extends AbstractInputUnitIO(cParam, outParams, egressParams) {
val in = Flipped(new Channel(cParam.asInstanceOf[ChannelParams]))
}
val io = IO(new InputUnitIO)
val g_i :: g_r :: g_v :: g_a :: g_c :: Nil = Enum(5)
class InputState extends Bundle {
val g = UInt(3.W)
val vc_sel = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) })
val flow = new FlowRoutingBundle
val fifo_deps = UInt(nVirtualChannels.W)
}
val input_buffer = Module(new InputBuffer(cParam))
for (i <- 0 until cParam.srcSpeedup) {
input_buffer.io.enq(i) := io.in.flit(i)
}
input_buffer.io.deq.foreach(_.ready := false.B)
val route_arbiter = Module(new Arbiter(
new RouteComputerReq, nVirtualChannels
))
io.router_req <> route_arbiter.io.out
val states = Reg(Vec(nVirtualChannels, new InputState))
val anyFifo = cParam.possibleFlows.map(_.fifo).reduce(_||_)
val allFifo = cParam.possibleFlows.map(_.fifo).reduce(_&&_)
if (anyFifo) {
val idle_mask = VecInit(states.map(_.g === g_i)).asUInt
for (s <- states)
for (i <- 0 until nVirtualChannels)
s.fifo_deps := s.fifo_deps & ~idle_mask
}
for (i <- 0 until cParam.srcSpeedup) {
when (io.in.flit(i).fire && io.in.flit(i).bits.head) {
val id = io.in.flit(i).bits.virt_channel_id
assert(id < nVirtualChannels.U)
assert(states(id).g === g_i)
val at_dest = io.in.flit(i).bits.flow.egress_node === nodeId.U
states(id).g := Mux(at_dest, g_v, g_r)
states(id).vc_sel.foreach(_.foreach(_ := false.B))
for (o <- 0 until nEgress) {
when (o.U === io.in.flit(i).bits.flow.egress_node_id) {
states(id).vc_sel(o+nOutputs)(0) := true.B
}
}
states(id).flow := io.in.flit(i).bits.flow
if (anyFifo) {
val fifo = cParam.possibleFlows.filter(_.fifo).map(_.isFlow(io.in.flit(i).bits.flow)).toSeq.orR
states(id).fifo_deps := VecInit(states.zipWithIndex.map { case (s, j) =>
s.g =/= g_i && s.flow.asUInt === io.in.flit(i).bits.flow.asUInt && j.U =/= id
}).asUInt
}
}
}
(route_arbiter.io.in zip states).zipWithIndex.map { case ((i,s),idx) =>
if (virtualChannelParams(idx).traversable) {
i.valid := s.g === g_r
i.bits.flow := s.flow
i.bits.src_virt_id := idx.U
when (i.fire) { s.g := g_v }
} else {
i.valid := false.B
i.bits := DontCare
}
}
when (io.router_req.fire) {
val id = io.router_req.bits.src_virt_id
assert(states(id).g === g_r)
states(id).g := g_v
for (i <- 0 until nVirtualChannels) {
when (i.U === id) {
states(i).vc_sel := io.router_resp.vc_sel
}
}
}
val mask = RegInit(0.U(nVirtualChannels.W))
val vcalloc_reqs = Wire(Vec(nVirtualChannels, new VCAllocReq(cParam, outParams, egressParams)))
val vcalloc_vals = Wire(Vec(nVirtualChannels, Bool()))
val vcalloc_filter = PriorityEncoderOH(Cat(vcalloc_vals.asUInt, vcalloc_vals.asUInt & ~mask))
val vcalloc_sel = vcalloc_filter(nVirtualChannels-1,0) | (vcalloc_filter >> nVirtualChannels)
// Prioritize incoming packetes
when (io.router_req.fire) {
mask := (1.U << io.router_req.bits.src_virt_id) - 1.U
} .elsewhen (vcalloc_vals.orR) {
mask := Mux1H(vcalloc_sel, (0 until nVirtualChannels).map { w => ~(0.U((w+1).W)) })
}
io.vcalloc_req.valid := vcalloc_vals.orR
io.vcalloc_req.bits := Mux1H(vcalloc_sel, vcalloc_reqs)
states.zipWithIndex.map { case (s,idx) =>
if (virtualChannelParams(idx).traversable) {
vcalloc_vals(idx) := s.g === g_v && s.fifo_deps === 0.U
vcalloc_reqs(idx).in_vc := idx.U
vcalloc_reqs(idx).vc_sel := s.vc_sel
vcalloc_reqs(idx).flow := s.flow
when (vcalloc_vals(idx) && vcalloc_sel(idx) && io.vcalloc_req.ready) { s.g := g_a }
if (combineRCVA) {
when (route_arbiter.io.in(idx).fire) {
vcalloc_vals(idx) := true.B
vcalloc_reqs(idx).vc_sel := io.router_resp.vc_sel
}
}
} else {
vcalloc_vals(idx) := false.B
vcalloc_reqs(idx) := DontCare
}
}
io.debug.va_stall := PopCount(vcalloc_vals) - io.vcalloc_req.ready
when (io.vcalloc_req.fire) {
for (i <- 0 until nVirtualChannels) {
when (vcalloc_sel(i)) {
states(i).vc_sel := io.vcalloc_resp.vc_sel
states(i).g := g_a
if (!combineRCVA) {
assert(states(i).g === g_v)
}
}
}
}
val salloc_arb = Module(new SwitchArbiter(
nVirtualChannels,
cParam.destSpeedup,
outParams, egressParams
))
(states zip salloc_arb.io.in).zipWithIndex.map { case ((s,r),i) =>
if (virtualChannelParams(i).traversable) {
val credit_available = (s.vc_sel.asUInt & io.out_credit_available.asUInt) =/= 0.U
r.valid := s.g === g_a && credit_available && input_buffer.io.deq(i).valid
r.bits.vc_sel := s.vc_sel
val deq_tail = input_buffer.io.deq(i).bits.tail
r.bits.tail := deq_tail
when (r.fire && deq_tail) {
s.g := g_i
}
input_buffer.io.deq(i).ready := r.ready
} else {
r.valid := false.B
r.bits := DontCare
}
}
io.debug.sa_stall := PopCount(salloc_arb.io.in.map(r => r.valid && !r.ready))
io.salloc_req <> salloc_arb.io.out
when (io.block) {
salloc_arb.io.out.foreach(_.ready := false.B)
io.salloc_req.foreach(_.valid := false.B)
}
class OutBundle extends Bundle {
val valid = Bool()
val vid = UInt(virtualChannelBits.W)
val out_vid = UInt(log2Up(allOutParams.map(_.nVirtualChannels).max).W)
val flit = new Flit(cParam.payloadBits)
}
val salloc_outs = if (combineSAST) {
Wire(Vec(cParam.destSpeedup, new OutBundle))
} else {
Reg(Vec(cParam.destSpeedup, new OutBundle))
}
io.in.credit_return := salloc_arb.io.out.zipWithIndex.map { case (o, i) =>
Mux(o.fire, salloc_arb.io.chosen_oh(i), 0.U)
}.reduce(_|_)
io.in.vc_free := salloc_arb.io.out.zipWithIndex.map { case (o, i) =>
Mux(o.fire && Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail)),
salloc_arb.io.chosen_oh(i), 0.U)
}.reduce(_|_)
for (i <- 0 until cParam.destSpeedup) {
val salloc_out = salloc_outs(i)
salloc_out.valid := salloc_arb.io.out(i).fire
salloc_out.vid := OHToUInt(salloc_arb.io.chosen_oh(i))
val vc_sel = Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.vc_sel))
val channel_oh = vc_sel.map(_.reduce(_||_)).toSeq
val virt_channel = Mux1H(channel_oh, vc_sel.map(v => OHToUInt(v)).toSeq)
when (salloc_arb.io.out(i).fire) {
salloc_out.out_vid := virt_channel
salloc_out.flit.payload := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.payload))
salloc_out.flit.head := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.head))
salloc_out.flit.tail := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail))
salloc_out.flit.flow := Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.flow))
} .otherwise {
salloc_out.out_vid := DontCare
salloc_out.flit := DontCare
}
salloc_out.flit.virt_channel_id := DontCare // this gets set in the switch
io.out(i).valid := salloc_out.valid
io.out(i).bits.flit := salloc_out.flit
io.out(i).bits.out_virt_channel := salloc_out.out_vid
}
def filterVCSel(sel: MixedVec[Vec[Bool]], srcV: Int) = {
if (virtualChannelParams(srcV).traversable) {
outParams.zipWithIndex.map { case (oP, oI) =>
(0 until oP.nVirtualChannels).map { oV =>
var allow = false
virtualChannelParams(srcV).possibleFlows.foreach { pI =>
allow = allow || routingRelation(
cParam.channelRoutingInfos(srcV),
oP.channelRoutingInfos(oV),
pI
)
}
if (!allow)
sel(oI)(oV) := false.B
}
}
}
}
(0 until nVirtualChannels).map { i =>
if (!virtualChannelParams(i).traversable) states(i) := DontCare
filterVCSel(states(i).vc_sel, i)
}
when (reset.asBool) {
states.foreach(_.g := g_i)
}
}
| module mem_28x75( // @[InputUnit.scala:85:18]
input [4:0] R0_addr,
input R0_en,
input R0_clk,
output [74:0] R0_data,
input [4:0] R1_addr,
input R1_en,
input R1_clk,
output [74:0] R1_data,
input [4:0] R2_addr,
input R2_en,
input R2_clk,
output [74:0] R2_data,
input [4:0] R3_addr,
input R3_en,
input R3_clk,
output [74:0] R3_data,
input [4:0] R4_addr,
input R4_en,
input R4_clk,
output [74:0] R4_data,
input [4:0] R5_addr,
input R5_en,
input R5_clk,
output [74:0] R5_data,
input [4:0] R6_addr,
input R6_en,
input R6_clk,
output [74:0] R6_data,
input [4:0] R7_addr,
input R7_en,
input R7_clk,
output [74:0] R7_data,
input [4:0] R8_addr,
input R8_en,
input R8_clk,
output [74:0] R8_data,
input [4:0] R9_addr,
input R9_en,
input R9_clk,
output [74:0] R9_data,
input [4:0] W0_addr,
input W0_en,
input W0_clk,
input [74:0] W0_data
);
reg [74:0] Memory[0:27]; // @[InputUnit.scala:85:18]
always @(posedge W0_clk) begin // @[InputUnit.scala:85:18]
if (W0_en & 1'h1) // @[InputUnit.scala:85:18]
Memory[W0_addr] <= W0_data; // @[InputUnit.scala:85:18]
always @(posedge) |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Bundles.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import freechips.rocketchip.util._
import scala.collection.immutable.ListMap
import chisel3.util.Decoupled
import chisel3.util.DecoupledIO
import chisel3.reflect.DataMirror
abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle
// common combos in lazy policy:
// Put + Acquire
// Release + AccessAck
object TLMessages
{
// A B C D E
def PutFullData = 0.U // . . => AccessAck
def PutPartialData = 1.U // . . => AccessAck
def ArithmeticData = 2.U // . . => AccessAckData
def LogicalData = 3.U // . . => AccessAckData
def Get = 4.U // . . => AccessAckData
def Hint = 5.U // . . => HintAck
def AcquireBlock = 6.U // . => Grant[Data]
def AcquirePerm = 7.U // . => Grant[Data]
def Probe = 6.U // . => ProbeAck[Data]
def AccessAck = 0.U // . .
def AccessAckData = 1.U // . .
def HintAck = 2.U // . .
def ProbeAck = 4.U // .
def ProbeAckData = 5.U // .
def Release = 6.U // . => ReleaseAck
def ReleaseData = 7.U // . => ReleaseAck
def Grant = 4.U // . => GrantAck
def GrantData = 5.U // . => GrantAck
def ReleaseAck = 6.U // .
def GrantAck = 0.U // .
def isA(x: UInt) = x <= AcquirePerm
def isB(x: UInt) = x <= Probe
def isC(x: UInt) = x <= ReleaseData
def isD(x: UInt) = x <= ReleaseAck
def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant)
def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck)
def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("AcquireBlock",TLPermissions.PermMsgGrow),
("AcquirePerm",TLPermissions.PermMsgGrow))
def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("Probe",TLPermissions.PermMsgCap))
def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("ProbeAck",TLPermissions.PermMsgReport),
("ProbeAckData",TLPermissions.PermMsgReport),
("Release",TLPermissions.PermMsgReport),
("ReleaseData",TLPermissions.PermMsgReport))
def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("Grant",TLPermissions.PermMsgCap),
("GrantData",TLPermissions.PermMsgCap),
("ReleaseAck",TLPermissions.PermMsgReserved))
}
/**
* The three primary TileLink permissions are:
* (T)runk: the agent is (or is on inwards path to) the global point of serialization.
* (B)ranch: the agent is on an outwards path to
* (N)one:
* These permissions are permuted by transfer operations in various ways.
* Operations can cap permissions, request for them to be grown or shrunk,
* or for a report on their current status.
*/
object TLPermissions
{
val aWidth = 2
val bdWidth = 2
val cWidth = 3
// Cap types (Grant = new permissions, Probe = permisions <= target)
def toT = 0.U(bdWidth.W)
def toB = 1.U(bdWidth.W)
def toN = 2.U(bdWidth.W)
def isCap(x: UInt) = x <= toN
// Grow types (Acquire = permissions >= target)
def NtoB = 0.U(aWidth.W)
def NtoT = 1.U(aWidth.W)
def BtoT = 2.U(aWidth.W)
def isGrow(x: UInt) = x <= BtoT
// Shrink types (ProbeAck, Release)
def TtoB = 0.U(cWidth.W)
def TtoN = 1.U(cWidth.W)
def BtoN = 2.U(cWidth.W)
def isShrink(x: UInt) = x <= BtoN
// Report types (ProbeAck, Release)
def TtoT = 3.U(cWidth.W)
def BtoB = 4.U(cWidth.W)
def NtoN = 5.U(cWidth.W)
def isReport(x: UInt) = x <= NtoN
def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT")
def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN")
def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN")
def PermMsgReserved:Seq[String] = Seq("Reserved")
}
object TLAtomics
{
val width = 3
// Arithmetic types
def MIN = 0.U(width.W)
def MAX = 1.U(width.W)
def MINU = 2.U(width.W)
def MAXU = 3.U(width.W)
def ADD = 4.U(width.W)
def isArithmetic(x: UInt) = x <= ADD
// Logical types
def XOR = 0.U(width.W)
def OR = 1.U(width.W)
def AND = 2.U(width.W)
def SWAP = 3.U(width.W)
def isLogical(x: UInt) = x <= SWAP
def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD")
def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP")
}
object TLHints
{
val width = 1
def PREFETCH_READ = 0.U(width.W)
def PREFETCH_WRITE = 1.U(width.W)
def isHints(x: UInt) = x <= PREFETCH_WRITE
def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite")
}
sealed trait TLChannel extends TLBundleBase {
val channelName: String
}
sealed trait TLDataChannel extends TLChannel
sealed trait TLAddrChannel extends TLDataChannel
final class TLBundleA(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleA_${params.shortName}"
val channelName = "'A' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleB(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleB_${params.shortName}"
val channelName = "'B' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val address = UInt(params.addressBits.W) // from
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleC(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleC_${params.shortName}"
val channelName = "'C' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.cWidth.W) // shrink or report perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleD(params: TLBundleParameters)
extends TLBundleBase(params) with TLDataChannel
{
override def typeName = s"TLBundleD_${params.shortName}"
val channelName = "'D' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val sink = UInt(params.sinkBits.W) // from
val denied = Bool() // implies corrupt iff *Data
val user = BundleMap(params.responseFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleE(params: TLBundleParameters)
extends TLBundleBase(params) with TLChannel
{
override def typeName = s"TLBundleE_${params.shortName}"
val channelName = "'E' channel"
val sink = UInt(params.sinkBits.W) // to
}
class TLBundle(val params: TLBundleParameters) extends Record
{
// Emulate a Bundle with elements abcde or ad depending on params.hasBCE
private val optA = Some (Decoupled(new TLBundleA(params)))
private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params))))
private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params)))
private val optD = Some (Flipped(Decoupled(new TLBundleD(params))))
private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params)))
def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params)))))
def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params)))))
def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params)))))
def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params)))))
def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params)))))
val elements =
if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a)
else ListMap("d" -> d, "a" -> a)
def tieoff(): Unit = {
DataMirror.specifiedDirectionOf(a.ready) match {
case SpecifiedDirection.Input =>
a.ready := false.B
c.ready := false.B
e.ready := false.B
b.valid := false.B
d.valid := false.B
case SpecifiedDirection.Output =>
a.valid := false.B
c.valid := false.B
e.valid := false.B
b.ready := false.B
d.ready := false.B
case _ =>
}
}
}
object TLBundle
{
def apply(params: TLBundleParameters) = new TLBundle(params)
}
class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle
class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params)
{
val a = new AsyncBundle(new TLBundleA(params.base), params.async)
val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async))
val c = new AsyncBundle(new TLBundleC(params.base), params.async)
val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async))
val e = new AsyncBundle(new TLBundleE(params.base), params.async)
}
class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = RationalIO(new TLBundleA(params))
val b = Flipped(RationalIO(new TLBundleB(params)))
val c = RationalIO(new TLBundleC(params))
val d = Flipped(RationalIO(new TLBundleD(params)))
val e = RationalIO(new TLBundleE(params))
}
class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = CreditedIO(new TLBundleA(params))
val b = Flipped(CreditedIO(new TLBundleB(params)))
val c = CreditedIO(new TLBundleC(params))
val d = Flipped(CreditedIO(new TLBundleD(params)))
val e = CreditedIO(new TLBundleE(params))
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor_21( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [7:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [7:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59]
wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27]
wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25]
wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_29 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_58 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_60 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_64 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_66 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_70 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_72 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_76 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_78 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_82 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_84 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_88 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_90 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_94 = 1'h1; // @[Parameters.scala:56:32]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28]
wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_first_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_first_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_first_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_first_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_set_wo_ready_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_set_wo_ready_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_opcodes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_opcodes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_sizes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_sizes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_opcodes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_opcodes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_sizes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_sizes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_probe_ack_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_probe_ack_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_probe_ack_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_probe_ack_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _same_cycle_resp_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _same_cycle_resp_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _same_cycle_resp_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _same_cycle_resp_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _same_cycle_resp_WIRE_4_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _same_cycle_resp_WIRE_5_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57]
wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57]
wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [2051:0] _c_sizes_set_T_1 = 2052'h0; // @[Monitor.scala:768:52]
wire [10:0] _c_opcodes_set_T = 11'h0; // @[Monitor.scala:767:79]
wire [10:0] _c_sizes_set_T = 11'h0; // @[Monitor.scala:768:77]
wire [2050:0] _c_opcodes_set_T_1 = 2051'h0; // @[Monitor.scala:767:54]
wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59]
wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40]
wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [255:0] _c_set_wo_ready_T = 256'h1; // @[OneHot.scala:58:35]
wire [255:0] _c_set_T = 256'h1; // @[OneHot.scala:58:35]
wire [1031:0] c_sizes_set = 1032'h0; // @[Monitor.scala:741:34]
wire [515:0] c_opcodes_set = 516'h0; // @[Monitor.scala:740:34]
wire [128:0] c_set = 129'h0; // @[Monitor.scala:738:34]
wire [128:0] c_set_wo_ready = 129'h0; // @[Monitor.scala:739:34]
wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117]
wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48]
wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119]
wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48]
wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [7:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_66 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_67 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_68 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_69 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_70 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_71 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_72 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_73 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_74 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_75 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_76 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_12 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_13 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 8'h20; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] _source_ok_T_1 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_7 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_13 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_19 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 6'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 6'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_14 = _source_ok_T_13 == 6'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 6'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_25 = io_in_a_bits_source_0[7:3]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_31 = io_in_a_bits_source_0[7:3]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_37 = io_in_a_bits_source_0[7:3]; // @[Monitor.scala:36:7]
wire _source_ok_T_26 = _source_ok_T_25 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_30 = _source_ok_T_28; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_32 = _source_ok_T_31 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_6 = _source_ok_T_36; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_38 = _source_ok_T_37 == 5'h8; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_41 = source_ok_uncommonBits_6 < 3'h5; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_42 = _source_ok_T_40 & _source_ok_T_41; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_7 = _source_ok_T_42; // @[Parameters.scala:1138:31]
wire _source_ok_T_43 = io_in_a_bits_source_0 == 8'h45; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_8 = _source_ok_T_43; // @[Parameters.scala:1138:31]
wire _source_ok_T_44 = io_in_a_bits_source_0 == 8'h48; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_9 = _source_ok_T_44; // @[Parameters.scala:1138:31]
wire _source_ok_T_45 = io_in_a_bits_source_0 == 8'h80; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_10 = _source_ok_T_45; // @[Parameters.scala:1138:31]
wire _source_ok_T_46 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_47 = _source_ok_T_46 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_48 = _source_ok_T_47 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_49 = _source_ok_T_48 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_50 = _source_ok_T_49 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_51 = _source_ok_T_50 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_52 = _source_ok_T_51 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_53 = _source_ok_T_52 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_54 = _source_ok_T_53 | _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_54 | _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46]
wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [28:0] _is_aligned_T = {17'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_4 = _uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_5 = _uncommonBits_T_5[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_6 = _uncommonBits_T_6[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_11 = _uncommonBits_T_11[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_12 = _uncommonBits_T_12[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_13 = _uncommonBits_T_13[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_18 = _uncommonBits_T_18[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_19 = _uncommonBits_T_19[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_20 = _uncommonBits_T_20[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_25 = _uncommonBits_T_25[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_26 = _uncommonBits_T_26[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_27 = _uncommonBits_T_27[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_32 = _uncommonBits_T_32[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_33 = _uncommonBits_T_33[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_34 = _uncommonBits_T_34[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_39 = _uncommonBits_T_39[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_40 = _uncommonBits_T_40[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_41 = _uncommonBits_T_41[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_46 = _uncommonBits_T_46[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_47 = _uncommonBits_T_47[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_48 = _uncommonBits_T_48[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_52 = _uncommonBits_T_52[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_53 = _uncommonBits_T_53[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_54 = _uncommonBits_T_54[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_55 = _uncommonBits_T_55[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_58 = _uncommonBits_T_58[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_59 = _uncommonBits_T_59[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_60 = _uncommonBits_T_60[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_61 = _uncommonBits_T_61[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_62 = _uncommonBits_T_62[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_63 = _uncommonBits_T_63[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_64 = _uncommonBits_T_64[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_65 = _uncommonBits_T_65[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_66 = _uncommonBits_T_66[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_67 = _uncommonBits_T_67[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_68 = _uncommonBits_T_68[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_69 = _uncommonBits_T_69[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_70 = _uncommonBits_T_70[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_71 = _uncommonBits_T_71[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_72 = _uncommonBits_T_72[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_73 = _uncommonBits_T_73[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_74 = _uncommonBits_T_74[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_75 = _uncommonBits_T_75[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_76 = _uncommonBits_T_76[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_55 = io_in_d_bits_source_0 == 8'h20; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_55; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] _source_ok_T_56 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_62 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_68 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_74 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_57 = _source_ok_T_56 == 6'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_59 = _source_ok_T_57; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_61 = _source_ok_T_59; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_61; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_63 = _source_ok_T_62 == 6'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_65 = _source_ok_T_63; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_67 = _source_ok_T_65; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_67; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_69 = _source_ok_T_68 == 6'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_71 = _source_ok_T_69; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_73 = _source_ok_T_71; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_73; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_75 = _source_ok_T_74 == 6'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_77 = _source_ok_T_75; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_79 = _source_ok_T_77; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_79; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[2:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_80 = io_in_d_bits_source_0[7:3]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_86 = io_in_d_bits_source_0[7:3]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_92 = io_in_d_bits_source_0[7:3]; // @[Monitor.scala:36:7]
wire _source_ok_T_81 = _source_ok_T_80 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_83 = _source_ok_T_81; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_85 = _source_ok_T_83; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_5 = _source_ok_T_85; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_12 = _source_ok_uncommonBits_T_12[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_87 = _source_ok_T_86 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_89 = _source_ok_T_87; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_91 = _source_ok_T_89; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_6 = _source_ok_T_91; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_13 = _source_ok_uncommonBits_T_13[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_93 = _source_ok_T_92 == 5'h8; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_95 = _source_ok_T_93; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_96 = source_ok_uncommonBits_13 < 3'h5; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_97 = _source_ok_T_95 & _source_ok_T_96; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_1_7 = _source_ok_T_97; // @[Parameters.scala:1138:31]
wire _source_ok_T_98 = io_in_d_bits_source_0 == 8'h45; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_8 = _source_ok_T_98; // @[Parameters.scala:1138:31]
wire _source_ok_T_99 = io_in_d_bits_source_0 == 8'h48; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_9 = _source_ok_T_99; // @[Parameters.scala:1138:31]
wire _source_ok_T_100 = io_in_d_bits_source_0 == 8'h80; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_10 = _source_ok_T_100; // @[Parameters.scala:1138:31]
wire _source_ok_T_101 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_102 = _source_ok_T_101 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_103 = _source_ok_T_102 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_104 = _source_ok_T_103 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_105 = _source_ok_T_104 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_106 = _source_ok_T_105 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_107 = _source_ok_T_106 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_108 = _source_ok_T_107 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_109 = _source_ok_T_108 | _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_109 | _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46]
wire _T_1835 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1835; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1835; // @[Decoupled.scala:51:35]
wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg [7:0] source; // @[Monitor.scala:390:22]
reg [28:0] address; // @[Monitor.scala:391:22]
wire _T_1903 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1903; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1903; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1903; // @[Decoupled.scala:51:35]
wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg [7:0] source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [128:0] inflight; // @[Monitor.scala:614:27]
reg [515:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [1031:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [128:0] a_set; // @[Monitor.scala:626:34]
wire [128:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [515:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [1031:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [10:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [10:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [10:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [10:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [10:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [515:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [515:0] _a_opcode_lookup_T_6 = {512'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [515:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[515:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [7:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [10:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65]
wire [10:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65]
wire [10:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99]
wire [10:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67]
wire [10:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99]
wire [1031:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [1031:0] _a_size_lookup_T_6 = {1024'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}]
wire [1031:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[1031:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [255:0] _GEN_3 = 256'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [255:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35]
wire [255:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire _T_1768 = _T_1835 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1768 ? _a_set_T[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1768 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1768 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [10:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [2050:0] _a_opcodes_set_T_1 = {2047'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1768 ? _a_opcodes_set_T_1[515:0] : 516'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [10:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77]
wire [2051:0] _a_sizes_set_T_1 = {2047'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1768 ? _a_sizes_set_T_1[1031:0] : 1032'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [128:0] d_clr; // @[Monitor.scala:664:34]
wire [128:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [515:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [1031:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_1814 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [255:0] _GEN_5 = 256'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1814 & ~d_release_ack ? _d_clr_wo_ready_T[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire _T_1783 = _T_1903 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1783 ? _d_clr_T[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire [2062:0] _d_opcodes_clr_T_5 = 2063'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1783 ? _d_opcodes_clr_T_5[515:0] : 516'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [2062:0] _d_sizes_clr_T_5 = 2063'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1783 ? _d_sizes_clr_T_5[1031:0] : 1032'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [128:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [128:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [128:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [515:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [515:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [515:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [1031:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [1031:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [1031:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [128:0] inflight_1; // @[Monitor.scala:726:35]
wire [128:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [515:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [515:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [1031:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [1031:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [7:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [515:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [515:0] _c_opcode_lookup_T_6 = {512'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [515:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[515:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [1031:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [1031:0] _c_size_lookup_T_6 = {1024'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}]
wire [1031:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[1031:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [128:0] d_clr_1; // @[Monitor.scala:774:34]
wire [128:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [515:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [1031:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1879 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1879 & d_release_ack_1 ? _d_clr_wo_ready_T_1[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire _T_1861 = _T_1903 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1861 ? _d_clr_T_1[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire [2062:0] _d_opcodes_clr_T_11 = 2063'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1861 ? _d_opcodes_clr_T_11[515:0] : 516'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [2062:0] _d_sizes_clr_T_11 = 2063'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1861 ? _d_sizes_clr_T_11[1031:0] : 1032'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 8'h0; // @[Monitor.scala:36:7, :795:113]
wire [128:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [128:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [515:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [515:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [1031:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [1031:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to the following Chisel files.
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
| module OptimizationBarrier_TLBEntryData_187( // @[package.scala:267:30]
input clock, // @[package.scala:267:30]
input reset, // @[package.scala:267:30]
input [19:0] io_x_ppn, // @[package.scala:268:18]
input io_x_u, // @[package.scala:268:18]
input io_x_g, // @[package.scala:268:18]
input io_x_ae_ptw, // @[package.scala:268:18]
input io_x_ae_final, // @[package.scala:268:18]
input io_x_ae_stage2, // @[package.scala:268:18]
input io_x_pf, // @[package.scala:268:18]
input io_x_gf, // @[package.scala:268:18]
input io_x_sw, // @[package.scala:268:18]
input io_x_sx, // @[package.scala:268:18]
input io_x_sr, // @[package.scala:268:18]
input io_x_hw, // @[package.scala:268:18]
input io_x_hx, // @[package.scala:268:18]
input io_x_hr, // @[package.scala:268:18]
input io_x_pw, // @[package.scala:268:18]
input io_x_px, // @[package.scala:268:18]
input io_x_pr, // @[package.scala:268:18]
input io_x_ppp, // @[package.scala:268:18]
input io_x_pal, // @[package.scala:268:18]
input io_x_paa, // @[package.scala:268:18]
input io_x_eff, // @[package.scala:268:18]
input io_x_c, // @[package.scala:268:18]
input io_x_fragmented_superpage, // @[package.scala:268:18]
output io_y_u, // @[package.scala:268:18]
output io_y_ae_ptw, // @[package.scala:268:18]
output io_y_ae_final, // @[package.scala:268:18]
output io_y_ae_stage2, // @[package.scala:268:18]
output io_y_pf, // @[package.scala:268:18]
output io_y_gf, // @[package.scala:268:18]
output io_y_sw, // @[package.scala:268:18]
output io_y_sx, // @[package.scala:268:18]
output io_y_sr, // @[package.scala:268:18]
output io_y_hw, // @[package.scala:268:18]
output io_y_hx, // @[package.scala:268:18]
output io_y_hr, // @[package.scala:268:18]
output io_y_pw, // @[package.scala:268:18]
output io_y_px, // @[package.scala:268:18]
output io_y_pr, // @[package.scala:268:18]
output io_y_ppp, // @[package.scala:268:18]
output io_y_pal, // @[package.scala:268:18]
output io_y_paa, // @[package.scala:268:18]
output io_y_eff, // @[package.scala:268:18]
output io_y_c // @[package.scala:268:18]
);
wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30]
wire io_x_u_0 = io_x_u; // @[package.scala:267:30]
wire io_x_g_0 = io_x_g; // @[package.scala:267:30]
wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30]
wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30]
wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30]
wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30]
wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30]
wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30]
wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30]
wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30]
wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30]
wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30]
wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30]
wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30]
wire io_x_px_0 = io_x_px; // @[package.scala:267:30]
wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30]
wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30]
wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30]
wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30]
wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30]
wire io_x_c_0 = io_x_c; // @[package.scala:267:30]
wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30]
wire [19:0] io_y_ppn = io_x_ppn_0; // @[package.scala:267:30]
wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30]
wire io_y_g = io_x_g_0; // @[package.scala:267:30]
wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30]
wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30]
wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30]
wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30]
wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30]
wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30]
wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30]
wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30]
wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30]
wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30]
wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30]
wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30]
wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30]
wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30]
wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30]
wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30]
wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30]
wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30]
wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30]
wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30]
assign io_y_u = io_y_u_0; // @[package.scala:267:30]
assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30]
assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30]
assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30]
assign io_y_pf = io_y_pf_0; // @[package.scala:267:30]
assign io_y_gf = io_y_gf_0; // @[package.scala:267:30]
assign io_y_sw = io_y_sw_0; // @[package.scala:267:30]
assign io_y_sx = io_y_sx_0; // @[package.scala:267:30]
assign io_y_sr = io_y_sr_0; // @[package.scala:267:30]
assign io_y_hw = io_y_hw_0; // @[package.scala:267:30]
assign io_y_hx = io_y_hx_0; // @[package.scala:267:30]
assign io_y_hr = io_y_hr_0; // @[package.scala:267:30]
assign io_y_pw = io_y_pw_0; // @[package.scala:267:30]
assign io_y_px = io_y_px_0; // @[package.scala:267:30]
assign io_y_pr = io_y_pr_0; // @[package.scala:267:30]
assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30]
assign io_y_pal = io_y_pal_0; // @[package.scala:267:30]
assign io_y_paa = io_y_paa_0; // @[package.scala:267:30]
assign io_y_eff = io_y_eff_0; // @[package.scala:267:30]
assign io_y_c = io_y_c_0; // @[package.scala:267:30]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File ListBuffer.scala:
/*
* Copyright 2019 SiFive, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You should have received a copy of LICENSE.Apache2 along with
* this software. If not, you may obtain a copy at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package sifive.blocks.inclusivecache
import chisel3._
import chisel3.util._
import freechips.rocketchip.util._
case class ListBufferParameters[T <: Data](gen: T, queues: Int, entries: Int, bypass: Boolean)
{
val queueBits = log2Up(queues)
val entryBits = log2Up(entries)
}
class ListBufferPush[T <: Data](params: ListBufferParameters[T]) extends Bundle
{
val index = UInt(params.queueBits.W)
val data = Output(params.gen)
}
class ListBuffer[T <: Data](params: ListBufferParameters[T]) extends Module
{
override def desiredName = s"ListBuffer_${params.gen.typeName}_q${params.queues}_e${params.entries}"
val io = IO(new Bundle {
// push is visible on the same cycle; flow queues
val push = Flipped(Decoupled(new ListBufferPush(params)))
val valid = UInt(params.queues.W)
val pop = Flipped(Valid(UInt(params.queueBits.W)))
val data = Output(params.gen)
})
val valid = RegInit(0.U(params.queues.W))
val head = Mem(params.queues, UInt(params.entryBits.W))
val tail = Mem(params.queues, UInt(params.entryBits.W))
val used = RegInit(0.U(params.entries.W))
val next = Mem(params.entries, UInt(params.entryBits.W))
val data = Mem(params.entries, params.gen)
val freeOH = ~(leftOR(~used) << 1) & ~used
val freeIdx = OHToUInt(freeOH)
val valid_set = WireDefault(0.U(params.queues.W))
val valid_clr = WireDefault(0.U(params.queues.W))
val used_set = WireDefault(0.U(params.entries.W))
val used_clr = WireDefault(0.U(params.entries.W))
val push_tail = tail.read(io.push.bits.index)
val push_valid = valid(io.push.bits.index)
io.push.ready := !used.andR
when (io.push.fire) {
valid_set := UIntToOH(io.push.bits.index, params.queues)
used_set := freeOH
data.write(freeIdx, io.push.bits.data)
when (push_valid) {
next.write(push_tail, freeIdx)
} .otherwise {
head.write(io.push.bits.index, freeIdx)
}
tail.write(io.push.bits.index, freeIdx)
}
val pop_head = head.read(io.pop.bits)
val pop_valid = valid(io.pop.bits)
// Bypass push data to the peek port
io.data := (if (!params.bypass) data.read(pop_head) else Mux(!pop_valid, io.push.bits.data, data.read(pop_head)))
io.valid := (if (!params.bypass) valid else (valid | valid_set))
// It is an error to pop something that is not valid
assert (!io.pop.fire || (io.valid)(io.pop.bits))
when (io.pop.fire) {
used_clr := UIntToOH(pop_head, params.entries)
when (pop_head === tail.read(io.pop.bits)) {
valid_clr := UIntToOH(io.pop.bits, params.queues)
}
head.write(io.pop.bits, Mux(io.push.fire && push_valid && push_tail === pop_head, freeIdx, next.read(pop_head)))
}
// Empty bypass changes no state
when ((!params.bypass).B || !io.pop.valid || pop_valid) {
used := (used & ~used_clr) | used_set
valid := (valid & ~valid_clr) | valid_set
}
}
| module ListBuffer_PutBufferCEntry_q2_e8_2( // @[ListBuffer.scala:36:7]
input clock, // @[ListBuffer.scala:36:7]
input reset, // @[ListBuffer.scala:36:7]
output io_push_ready, // @[ListBuffer.scala:39:14]
input io_push_valid, // @[ListBuffer.scala:39:14]
input io_push_bits_index, // @[ListBuffer.scala:39:14]
input [127:0] io_push_bits_data_data, // @[ListBuffer.scala:39:14]
input io_push_bits_data_corrupt, // @[ListBuffer.scala:39:14]
output [1:0] io_valid, // @[ListBuffer.scala:39:14]
input io_pop_valid, // @[ListBuffer.scala:39:14]
input io_pop_bits, // @[ListBuffer.scala:39:14]
output [127:0] io_data_data, // @[ListBuffer.scala:39:14]
output io_data_corrupt // @[ListBuffer.scala:39:14]
);
wire [128:0] _data_ext_R0_data; // @[ListBuffer.scala:52:18]
wire [2:0] _next_ext_R0_data; // @[ListBuffer.scala:51:18]
wire [2:0] _tail_ext_R0_data; // @[ListBuffer.scala:49:18]
wire [2:0] _tail_ext_R1_data; // @[ListBuffer.scala:49:18]
wire [2:0] _head_ext_R0_data; // @[ListBuffer.scala:48:18]
wire io_push_valid_0 = io_push_valid; // @[ListBuffer.scala:36:7]
wire io_push_bits_index_0 = io_push_bits_index; // @[ListBuffer.scala:36:7]
wire [127:0] io_push_bits_data_data_0 = io_push_bits_data_data; // @[ListBuffer.scala:36:7]
wire io_push_bits_data_corrupt_0 = io_push_bits_data_corrupt; // @[ListBuffer.scala:36:7]
wire io_pop_valid_0 = io_pop_valid; // @[ListBuffer.scala:36:7]
wire io_pop_bits_0 = io_pop_bits; // @[ListBuffer.scala:36:7]
wire _io_push_ready_T_1; // @[ListBuffer.scala:65:20]
wire valid_set_shiftAmount = io_push_bits_index_0; // @[OneHot.scala:64:49]
wire valid_clr_shiftAmount = io_pop_bits_0; // @[OneHot.scala:64:49]
wire io_push_ready_0; // @[ListBuffer.scala:36:7]
wire [127:0] io_data_data_0; // @[ListBuffer.scala:36:7]
wire io_data_corrupt_0; // @[ListBuffer.scala:36:7]
wire [1:0] io_valid_0; // @[ListBuffer.scala:36:7]
reg [1:0] valid; // @[ListBuffer.scala:47:22]
assign io_valid_0 = valid; // @[ListBuffer.scala:36:7, :47:22]
reg [7:0] used; // @[ListBuffer.scala:50:22]
assign io_data_data_0 = _data_ext_R0_data[127:0]; // @[ListBuffer.scala:36:7, :52:18]
assign io_data_corrupt_0 = _data_ext_R0_data[128]; // @[ListBuffer.scala:36:7, :52:18]
wire [7:0] _freeOH_T = ~used; // @[ListBuffer.scala:50:22, :54:25]
wire [8:0] _freeOH_T_1 = {_freeOH_T, 1'h0}; // @[package.scala:253:48]
wire [7:0] _freeOH_T_2 = _freeOH_T_1[7:0]; // @[package.scala:253:{48,53}]
wire [7:0] _freeOH_T_3 = _freeOH_T | _freeOH_T_2; // @[package.scala:253:{43,53}]
wire [9:0] _freeOH_T_4 = {_freeOH_T_3, 2'h0}; // @[package.scala:253:{43,48}]
wire [7:0] _freeOH_T_5 = _freeOH_T_4[7:0]; // @[package.scala:253:{48,53}]
wire [7:0] _freeOH_T_6 = _freeOH_T_3 | _freeOH_T_5; // @[package.scala:253:{43,53}]
wire [11:0] _freeOH_T_7 = {_freeOH_T_6, 4'h0}; // @[package.scala:253:{43,48}]
wire [7:0] _freeOH_T_8 = _freeOH_T_7[7:0]; // @[package.scala:253:{48,53}]
wire [7:0] _freeOH_T_9 = _freeOH_T_6 | _freeOH_T_8; // @[package.scala:253:{43,53}]
wire [7:0] _freeOH_T_10 = _freeOH_T_9; // @[package.scala:253:43, :254:17]
wire [8:0] _freeOH_T_11 = {_freeOH_T_10, 1'h0}; // @[package.scala:254:17]
wire [8:0] _freeOH_T_12 = ~_freeOH_T_11; // @[ListBuffer.scala:54:{16,32}]
wire [7:0] _freeOH_T_13 = ~used; // @[ListBuffer.scala:50:22, :54:{25,40}]
wire [8:0] freeOH = {1'h0, _freeOH_T_12[7:0] & _freeOH_T_13}; // @[ListBuffer.scala:54:{16,38,40}]
wire freeIdx_hi = freeOH[8]; // @[OneHot.scala:30:18]
wire _freeIdx_T = freeIdx_hi; // @[OneHot.scala:30:18, :32:14]
wire [7:0] freeIdx_lo = freeOH[7:0]; // @[OneHot.scala:31:18]
wire [7:0] _freeIdx_T_1 = {7'h0, freeIdx_hi} | freeIdx_lo; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [3:0] freeIdx_hi_1 = _freeIdx_T_1[7:4]; // @[OneHot.scala:30:18, :32:28]
wire [3:0] freeIdx_lo_1 = _freeIdx_T_1[3:0]; // @[OneHot.scala:31:18, :32:28]
wire _freeIdx_T_2 = |freeIdx_hi_1; // @[OneHot.scala:30:18, :32:14]
wire [3:0] _freeIdx_T_3 = freeIdx_hi_1 | freeIdx_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [1:0] freeIdx_hi_2 = _freeIdx_T_3[3:2]; // @[OneHot.scala:30:18, :32:28]
wire [1:0] freeIdx_lo_2 = _freeIdx_T_3[1:0]; // @[OneHot.scala:31:18, :32:28]
wire _freeIdx_T_4 = |freeIdx_hi_2; // @[OneHot.scala:30:18, :32:14]
wire [1:0] _freeIdx_T_5 = freeIdx_hi_2 | freeIdx_lo_2; // @[OneHot.scala:30:18, :31:18, :32:28]
wire _freeIdx_T_6 = _freeIdx_T_5[1]; // @[OneHot.scala:32:28]
wire [1:0] _freeIdx_T_7 = {_freeIdx_T_4, _freeIdx_T_6}; // @[OneHot.scala:32:{10,14}]
wire [2:0] _freeIdx_T_8 = {_freeIdx_T_2, _freeIdx_T_7}; // @[OneHot.scala:32:{10,14}]
wire [3:0] freeIdx = {_freeIdx_T, _freeIdx_T_8}; // @[OneHot.scala:32:{10,14}]
wire [1:0] valid_set; // @[ListBuffer.scala:57:30]
wire [1:0] valid_clr; // @[ListBuffer.scala:58:30]
wire [7:0] used_set; // @[ListBuffer.scala:59:30]
wire [7:0] used_clr; // @[ListBuffer.scala:60:30]
wire [1:0] _push_valid_T = valid >> io_push_bits_index_0; // @[ListBuffer.scala:36:7, :47:22, :63:25]
wire push_valid = _push_valid_T[0]; // @[ListBuffer.scala:63:25]
wire _io_push_ready_T = &used; // @[ListBuffer.scala:50:22, :65:26]
assign _io_push_ready_T_1 = ~_io_push_ready_T; // @[ListBuffer.scala:65:{20,26}]
assign io_push_ready_0 = _io_push_ready_T_1; // @[ListBuffer.scala:36:7, :65:20]
wire data_MPORT_en = io_push_ready_0 & io_push_valid_0; // @[Decoupled.scala:51:35]
wire [1:0] _valid_set_T = 2'h1 << valid_set_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [1:0] _valid_set_T_1 = _valid_set_T; // @[OneHot.scala:65:{12,27}]
assign valid_set = data_MPORT_en ? _valid_set_T_1 : 2'h0; // @[OneHot.scala:65:27]
assign used_set = data_MPORT_en ? freeIdx_lo : 8'h0; // @[OneHot.scala:31:18]
wire [1:0] _GEN = {1'h0, io_pop_bits_0}; // @[ListBuffer.scala:36:7, :79:24]
wire [1:0] _pop_valid_T = valid >> _GEN; // @[ListBuffer.scala:47:22, :79:24]
wire pop_valid = _pop_valid_T[0]; // @[ListBuffer.scala:79:24] |
Generate the Verilog code corresponding to the following Chisel files.
File PE.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle {
val dataflow = UInt(1.W) // TODO make this an Enum
val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)?
val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats
}
class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module {
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(inputType)
val in_c = Input(cType)
val out_d = Output(dType)
})
io.out_d := io.in_c.mac(io.in_a, io.in_b)
}
// TODO update documentation
/**
* A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh.
* @param width Data width of operands
*/
class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int)
(implicit ev: Arithmetic[T]) extends Module { // Debugging variables
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(outputType)
val in_d = Input(outputType)
val out_a = Output(inputType)
val out_b = Output(outputType)
val out_c = Output(outputType)
val in_control = Input(new PEControl(accType))
val out_control = Output(new PEControl(accType))
val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W))
val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W))
val in_last = Input(Bool())
val out_last = Output(Bool())
val in_valid = Input(Bool())
val out_valid = Output(Bool())
val bad_dataflow = Output(Bool())
})
val cType = if (df == Dataflow.WS) inputType else accType
// When creating PEs that support multiple dataflows, the
// elaboration/synthesis tools often fail to consolidate and de-duplicate
// MAC units. To force mac circuitry to be re-used, we create a "mac_unit"
// module here which just performs a single MAC operation
val mac_unit = Module(new MacUnit(inputType,
if (df == Dataflow.WS) outputType else accType, outputType))
val a = io.in_a
val b = io.in_b
val d = io.in_d
val c1 = Reg(cType)
val c2 = Reg(cType)
val dataflow = io.in_control.dataflow
val prop = io.in_control.propagate
val shift = io.in_control.shift
val id = io.in_id
val last = io.in_last
val valid = io.in_valid
io.out_a := a
io.out_control.dataflow := dataflow
io.out_control.propagate := prop
io.out_control.shift := shift
io.out_id := id
io.out_last := last
io.out_valid := valid
mac_unit.io.in_a := a
val last_s = RegEnable(prop, valid)
val flip = last_s =/= prop
val shift_offset = Mux(flip, shift, 0.U)
// Which dataflow are we using?
val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W)
val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W)
// Is c1 being computed on, or propagated forward (in the output-stationary dataflow)?
val COMPUTE = 0.U(1.W)
val PROPAGATE = 1.U(1.W)
io.bad_dataflow := false.B
when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
c2 := mac_unit.io.out_d
c1 := d.withWidthOf(cType)
}.otherwise {
io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c1
c1 := mac_unit.io.out_d
c2 := d.withWidthOf(cType)
}
}.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := c1
mac_unit.io.in_b := c2.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c1 := d
}.otherwise {
io.out_c := c2
mac_unit.io.in_b := c1.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c2 := d
}
}.otherwise {
io.bad_dataflow := true.B
//assert(false.B, "unknown dataflow")
io.out_c := DontCare
io.out_b := DontCare
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
}
when (!valid) {
c1 := c1
c2 := c2
mac_unit.io.in_b := DontCare
mac_unit.io.in_c := DontCare
}
}
File Arithmetic.scala:
// A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own:
// implicit MyTypeArithmetic extends Arithmetic[MyType] { ... }
package gemmini
import chisel3._
import chisel3.util._
import hardfloat._
// Bundles that represent the raw bits of custom datatypes
case class Float(expWidth: Int, sigWidth: Int) extends Bundle {
val bits = UInt((expWidth + sigWidth).W)
val bias: Int = (1 << (expWidth-1)) - 1
}
case class DummySInt(w: Int) extends Bundle {
val bits = UInt(w.W)
def dontCare: DummySInt = {
val o = Wire(new DummySInt(w))
o.bits := 0.U
o
}
}
// The Arithmetic typeclass which implements various arithmetic operations on custom datatypes
abstract class Arithmetic[T <: Data] {
implicit def cast(t: T): ArithmeticOps[T]
}
abstract class ArithmeticOps[T <: Data](self: T) {
def *(t: T): T
def mac(m1: T, m2: T): T // Returns (m1 * m2 + self)
def +(t: T): T
def -(t: T): T
def >>(u: UInt): T // This is a rounding shift! Rounds away from 0
def >(t: T): Bool
def identity: T
def withWidthOf(t: T): T
def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates
def relu: T
def zero: T
def minimum: T
// Optional parameters, which only need to be defined if you want to enable various optimizations for transformers
def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None
def mult_with_reciprocal[U <: Data](reciprocal: U) = self
}
object Arithmetic {
implicit object UIntArithmetic extends Arithmetic[UInt] {
override implicit def cast(self: UInt) = new ArithmeticOps(self) {
override def *(t: UInt) = self * t
override def mac(m1: UInt, m2: UInt) = m1 * m2 + self
override def +(t: UInt) = self + t
override def -(t: UInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = point_five & (zeros | ones_digit)
(self >> u).asUInt + r
}
override def >(t: UInt): Bool = self > t
override def withWidthOf(t: UInt) = self.asTypeOf(t)
override def clippedToWidthOf(t: UInt) = {
val sat = ((1 << (t.getWidth-1))-1).U
Mux(self > sat, sat, self)(t.getWidth-1, 0)
}
override def relu: UInt = self
override def zero: UInt = 0.U
override def identity: UInt = 1.U
override def minimum: UInt = 0.U
}
}
implicit object SIntArithmetic extends Arithmetic[SInt] {
override implicit def cast(self: SInt) = new ArithmeticOps(self) {
override def *(t: SInt) = self * t
override def mac(m1: SInt, m2: SInt) = m1 * m2 + self
override def +(t: SInt) = self + t
override def -(t: SInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = (point_five & (zeros | ones_digit)).asBool
(self >> u).asSInt + Mux(r, 1.S, 0.S)
}
override def >(t: SInt): Bool = self > t
override def withWidthOf(t: SInt) = {
if (self.getWidth >= t.getWidth)
self(t.getWidth-1, 0).asSInt
else {
val sign_bits = t.getWidth - self.getWidth
val sign = self(self.getWidth-1)
Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t)
}
}
override def clippedToWidthOf(t: SInt): SInt = {
val maxsat = ((1 << (t.getWidth-1))-1).S
val minsat = (-(1 << (t.getWidth-1))).S
MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt
}
override def relu: SInt = Mux(self >= 0.S, self, 0.S)
override def zero: SInt = 0.S
override def identity: SInt = 1.S
override def minimum: SInt = (-(1 << (self.getWidth-1))).S
override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(denom_t.cloneType))
val output = Wire(Decoupled(self.cloneType))
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def sin_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def uin_to_float(x: UInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := x
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = sin_to_float(self)
val denom_rec = uin_to_float(input.bits)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := self_rec
divider.io.b := denom_rec
divider.io.roundingMode := consts.round_minMag
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := float_to_in(divider.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(self.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
// Instantiate the hardloat sqrt
val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0))
input.ready := sqrter.io.inReady
sqrter.io.inValid := input.valid
sqrter.io.sqrtOp := true.B
sqrter.io.a := self_rec
sqrter.io.b := DontCare
sqrter.io.roundingMode := consts.round_minMag
sqrter.io.detectTininess := consts.tininess_afterRounding
output.valid := sqrter.io.outValid_sqrt
output.bits := float_to_in(sqrter.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match {
case Float(expWidth, sigWidth) =>
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(u.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
val self_rec = in_to_float(self)
val one_rec = in_to_float(1.S)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := one_rec
divider.io.b := self_rec
divider.io.roundingMode := consts.round_near_even
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u)
assert(!output.valid || output.ready)
Some((input, output))
case _ => None
}
override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match {
case recip @ Float(expWidth, sigWidth) =>
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits)
// Instantiate the hardloat divider
val muladder = Module(new MulRecFN(expWidth, sigWidth))
muladder.io.roundingMode := consts.round_near_even
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := reciprocal_rec
float_to_in(muladder.io.out)
case _ => self
}
}
}
implicit object FloatArithmetic extends Arithmetic[Float] {
// TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array
override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) {
override def *(t: Float): Float = {
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := t_rec_resized
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def mac(m1: Float, m2: Float): Float = {
// Recode all operands
val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits)
val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize m1 to self's width
val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth))
m1_resizer.io.in := m1_rec
m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m1_resizer.io.detectTininess := consts.tininess_afterRounding
val m1_rec_resized = m1_resizer.io.out
// Resize m2 to self's width
val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth))
m2_resizer.io.in := m2_rec
m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m2_resizer.io.detectTininess := consts.tininess_afterRounding
val m2_rec_resized = m2_resizer.io.out
// Perform multiply-add
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := m1_rec_resized
muladder.io.b := m2_rec_resized
muladder.io.c := self_rec
// Convert result to standard format // TODO remove these intermediate recodings
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def +(t: Float): Float = {
require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Generate 1 as a float
val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := 1.U
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
val one_rec = in_to_rec_fn.io.out
// Resize t
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
// Perform addition
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := t_rec_resized
muladder.io.b := one_rec
muladder.io.c := self_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def -(t: Float): Float = {
val t_sgn = t.bits(t.getWidth-1)
val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t)
self + neg_t
}
override def >>(u: UInt): Float = {
// Recode self
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Get 2^(-u) as a recoded float
val shift_exp = Wire(UInt(self.expWidth.W))
shift_exp := self.bias.U - u
val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W))
val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn)
assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported")
// Multiply self and 2^(-u)
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := shift_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def >(t: Float): Bool = {
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize t to self's width
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth))
comparator.io.a := self_rec
comparator.io.b := t_rec_resized
comparator.io.signaling := false.B
comparator.io.gt
}
override def withWidthOf(t: Float): Float = {
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def clippedToWidthOf(t: Float): Float = {
// TODO check for overflow. Right now, we just assume that overflow doesn't happen
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def relu: Float = {
val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits)
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits)
result
}
override def zero: Float = 0.U.asTypeOf(self)
override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
}
}
implicit object DummySIntArithmetic extends Arithmetic[DummySInt] {
override implicit def cast(self: DummySInt) = new ArithmeticOps(self) {
override def *(t: DummySInt) = self.dontCare
override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare
override def +(t: DummySInt) = self.dontCare
override def -(t: DummySInt) = self.dontCare
override def >>(t: UInt) = self.dontCare
override def >(t: DummySInt): Bool = false.B
override def identity = self.dontCare
override def withWidthOf(t: DummySInt) = self.dontCare
override def clippedToWidthOf(t: DummySInt) = self.dontCare
override def relu = self.dontCare
override def zero = self.dontCare
override def minimum: DummySInt = self.dontCare
}
}
}
| module MacUnit_255( // @[PE.scala:14:7]
input clock, // @[PE.scala:14:7]
input reset, // @[PE.scala:14:7]
input [7:0] io_in_a, // @[PE.scala:16:14]
input [7:0] io_in_b, // @[PE.scala:16:14]
input [19:0] io_in_c, // @[PE.scala:16:14]
output [19:0] io_out_d // @[PE.scala:16:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7]
wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7]
wire [19:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7]
wire [19:0] _io_out_d_T_3; // @[Arithmetic.scala:93:54]
wire [19:0] io_out_d_0; // @[PE.scala:14:7]
wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7]
wire [20:0] _io_out_d_T_1 = {{5{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[19], io_in_c_0}; // @[PE.scala:14:7]
wire [19:0] _io_out_d_T_2 = _io_out_d_T_1[19:0]; // @[Arithmetic.scala:93:54]
assign _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54]
assign io_out_d_0 = _io_out_d_T_3; // @[PE.scala:14:7]
assign io_out_d = io_out_d_0; // @[PE.scala:14:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Protocol.scala:
package rerocc.bus
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tile._
import freechips.rocketchip.rocket._
import freechips.rocketchip.util._
import rerocc.client.{ReRoCCClientParams}
import rerocc.manager.{ReRoCCManagerParams}
object ReRoCCProtocol {
val width = 3
val mAcquire = 0.U(width.W)
// beat0: data = inst
// beat1: data = mstatus[63:0]
// beat2: data = mstatus[127:64]
val mInst = 1.U(width.W)
// beat0: data = mstatus[63:0]
// beat1: data = mstatus[127:0]
val mUStatus = 2.U(width.W)
// beat0: data = ptbr
val mUPtbr = 3.U(width.W)
val mRelease = 4.U(width.W)
val mUnbusy = 5.U(width.W)
// data
// data = acquired
val sAcqResp = 0.U(width.W)
// data = 0
val sInstAck = 1.U(width.W)
// beat0: data = data
// beat1: data = rd
val sWrite = 2.U(width.W)
val sRelResp = 3.U(width.W)
val sUnbusyAck = 4.U(width.W)
val MAX_BEATS = 3
}
class ReRoCCMsgBundle(val params: ReRoCCBundleParams) extends Bundle {
val opcode = UInt(ReRoCCProtocol.width.W)
val client_id = UInt(params.clientIdBits.W)
val manager_id = UInt(params.managerIdBits.W)
val data = UInt(64.W)
}
object ReRoCCMsgFirstLast {
def apply(m: DecoupledIO[ReRoCCMsgBundle], isReq: Boolean): (Bool, Bool, UInt) = {
val beat = RegInit(0.U(log2Ceil(ReRoCCProtocol.MAX_BEATS).W))
val max_beat = RegInit(0.U(log2Ceil(ReRoCCProtocol.MAX_BEATS).W))
val first = beat === 0.U
val last = Wire(Bool())
val inst = m.bits.data.asTypeOf(new RoCCInstruction)
when (m.fire && first) {
max_beat := 0.U
if (isReq) {
when (m.bits.opcode === ReRoCCProtocol.mInst) {
max_beat := inst.xs1 +& inst.xs2
} .elsewhen (m.bits.opcode === ReRoCCProtocol.mUStatus) {
max_beat := 1.U
}
} else {
when (m.bits.opcode === ReRoCCProtocol.sWrite) {
max_beat := 1.U
}
}
}
last := true.B
if (isReq) {
when (m.bits.opcode === ReRoCCProtocol.mUStatus) {
last := beat === max_beat && !first
} .elsewhen (m.bits.opcode === ReRoCCProtocol.mInst) {
last := Mux(first, !inst.xs1 && !inst.xs2, beat === max_beat)
}
} else {
when (m.bits.opcode === ReRoCCProtocol.sWrite) {
last := beat === max_beat && !first
}
}
when (m.fire) { beat := beat + 1.U }
when (m.fire && last) {
max_beat := 0.U
beat := 0.U
}
(first, last, beat)
}
}
class ReRoCCBundle(val params: ReRoCCBundleParams) extends Bundle {
val req = Decoupled(new ReRoCCMsgBundle(params))
val resp = Flipped(Decoupled(new ReRoCCMsgBundle(params)))
}
case class EmptyParams()
object ReRoCCImp extends SimpleNodeImp[ReRoCCClientPortParams, ReRoCCManagerPortParams, ReRoCCEdgeParams, ReRoCCBundle] {
def edge(pd: ReRoCCClientPortParams, pu: ReRoCCManagerPortParams, p: Parameters, sourceInfo: SourceInfo) = {
ReRoCCEdgeParams(pu, pd)
}
def bundle(e: ReRoCCEdgeParams) = new ReRoCCBundle(e.bundle)
def render(ei: ReRoCCEdgeParams) = RenderedEdge(colour = "#000000" /* black */)
}
case class ReRoCCClientNode(clientParams: ReRoCCClientParams)(implicit valName: ValName) extends SourceNode(ReRoCCImp)(Seq(ReRoCCClientPortParams(Seq(clientParams))))
case class ReRoCCManagerNode(managerParams: ReRoCCManagerParams)(implicit valName: ValName) extends SinkNode(ReRoCCImp)(Seq(ReRoCCManagerPortParams(Seq(managerParams))))
class ReRoCCBuffer(b: BufferParams = BufferParams.default)(implicit p: Parameters) extends LazyModule {
val node = new AdapterNode(ReRoCCImp)({s => s}, {s => s})
lazy val module = new LazyModuleImp(this) {
(node.in zip node.out) foreach { case ((in, _), (out, _)) =>
out.req <> b(in.req)
in.resp <> b(out.resp)
}
}
}
object ReRoCCBuffer {
def apply(b: BufferParams = BufferParams.default)(implicit p: Parameters) = {
val rerocc_buffer = LazyModule(new ReRoCCBuffer(b)(p))
rerocc_buffer.node
}
}
case class ReRoCCIdentityNode()(implicit valName: ValName) extends IdentityNode(ReRoCCImp)()
File Arbiter.scala:
package rerocc.bus
import chisel3._
import chisel3.util._
import freechips.rocketchip.util.{HellaLockingArbiter}
class ReRoCCMsgArbiter(bundle: ReRoCCBundleParams, arbN: Int, isReq: Boolean) extends HellaLockingArbiter(new ReRoCCMsgBundle(bundle), arbN, false) {
when (io.out.fire) {
when (!locked) {
lockIdx := choice
locked := true.B
}
when (ReRoCCMsgFirstLast(io.out, isReq)._2) {
locked := false.B
}
}
}
File Arbiters.scala:
// See LICENSE.Berkeley for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
/** A generalized locking RR arbiter that addresses the limitations of the
* version in the Chisel standard library */
abstract class HellaLockingArbiter[T <: Data](typ: T, arbN: Int, rr: Boolean = false)
extends Module {
val io = IO(new Bundle {
val in = Flipped(Vec(arbN, Decoupled(typ.cloneType)))
val out = Decoupled(typ.cloneType)
})
def rotateLeft[T <: Data](norm: Vec[T], rot: UInt): Vec[T] = {
val n = norm.size
VecInit.tabulate(n) { i =>
Mux(rot < (n - i).U, norm(i.U + rot), norm(rot - (n - i).U))
}
}
val lockIdx = RegInit(0.U(log2Up(arbN).W))
val locked = RegInit(false.B)
val choice = if (rr) {
PriorityMux(
rotateLeft(VecInit(io.in.map(_.valid)), lockIdx + 1.U),
rotateLeft(VecInit((0 until arbN).map(_.U)), lockIdx + 1.U))
} else {
PriorityEncoder(io.in.map(_.valid))
}
val chosen = Mux(locked, lockIdx, choice)
for (i <- 0 until arbN) {
io.in(i).ready := io.out.ready && chosen === i.U
}
io.out.valid := io.in(chosen).valid
io.out.bits := io.in(chosen).bits
}
/** This locking arbiter determines when it is safe to unlock
* by peeking at the data */
class HellaPeekingArbiter[T <: Data](
typ: T, arbN: Int,
canUnlock: T => Bool,
needsLock: Option[T => Bool] = None,
rr: Boolean = false)
extends HellaLockingArbiter(typ, arbN, rr) {
def realNeedsLock(data: T): Bool =
needsLock.map(_(data)).getOrElse(true.B)
when (io.out.fire) {
when (!locked && realNeedsLock(io.out.bits)) {
lockIdx := choice
locked := true.B
}
// the unlock statement takes precedent
when (canUnlock(io.out.bits)) {
locked := false.B
}
}
}
/** This arbiter determines when it is safe to unlock by counting transactions */
class HellaCountingArbiter[T <: Data](
typ: T, arbN: Int, count: Int,
val needsLock: Option[T => Bool] = None,
rr: Boolean = false)
extends HellaLockingArbiter(typ, arbN, rr) {
def realNeedsLock(data: T): Bool =
needsLock.map(_(data)).getOrElse(true.B)
// if count is 1, you should use a non-locking arbiter
require(count > 1, "CountingArbiter cannot have count <= 1")
val lock_ctr = Counter(count)
when (io.out.fire) {
when (!locked && realNeedsLock(io.out.bits)) {
lockIdx := choice
locked := true.B
lock_ctr.inc()
}
when (locked) {
when (lock_ctr.inc()) { locked := false.B }
}
}
}
/** This arbiter preserves the order of responses */
class InOrderArbiter[T <: Data, U <: Data](reqTyp: T, respTyp: U, n: Int)
(implicit p: Parameters) extends Module {
val io = IO(new Bundle {
val in_req = Flipped(Vec(n, Decoupled(reqTyp)))
val in_resp = Vec(n, Decoupled(respTyp))
val out_req = Decoupled(reqTyp)
val out_resp = Flipped(Decoupled(respTyp))
})
if (n > 1) {
val route_q = Module(new Queue(UInt(log2Up(n).W), 2))
val req_arb = Module(new RRArbiter(reqTyp, n))
req_arb.io.in <> io.in_req
val req_helper = DecoupledHelper(
req_arb.io.out.valid,
route_q.io.enq.ready,
io.out_req.ready)
io.out_req.bits := req_arb.io.out.bits
io.out_req.valid := req_helper.fire(io.out_req.ready)
route_q.io.enq.bits := req_arb.io.chosen
route_q.io.enq.valid := req_helper.fire(route_q.io.enq.ready)
req_arb.io.out.ready := req_helper.fire(req_arb.io.out.valid)
val resp_sel = route_q.io.deq.bits
val resp_ready = io.in_resp(resp_sel).ready
val resp_helper = DecoupledHelper(
resp_ready,
route_q.io.deq.valid,
io.out_resp.valid)
val resp_valid = resp_helper.fire(resp_ready)
for (i <- 0 until n) {
io.in_resp(i).bits := io.out_resp.bits
io.in_resp(i).valid := resp_valid && resp_sel === i.U
}
route_q.io.deq.ready := resp_helper.fire(route_q.io.deq.valid)
io.out_resp.ready := resp_helper.fire(io.out_resp.valid)
} else {
io.out_req <> io.in_req.head
io.in_resp.head <> io.out_resp
}
}
| module ReRoCCMsgArbiter_8( // @[Arbiter.scala:7:7]
input clock, // @[Arbiter.scala:7:7]
input reset, // @[Arbiter.scala:7:7]
output io_in_0_ready, // @[Arbiters.scala:14:14]
input io_in_0_valid, // @[Arbiters.scala:14:14]
input [2:0] io_in_0_bits_opcode, // @[Arbiters.scala:14:14]
input [3:0] io_in_0_bits_client_id, // @[Arbiters.scala:14:14]
input [2:0] io_in_0_bits_manager_id, // @[Arbiters.scala:14:14]
input [63:0] io_in_0_bits_data, // @[Arbiters.scala:14:14]
input io_out_ready, // @[Arbiters.scala:14:14]
output io_out_valid, // @[Arbiters.scala:14:14]
output [2:0] io_out_bits_opcode, // @[Arbiters.scala:14:14]
output [3:0] io_out_bits_client_id, // @[Arbiters.scala:14:14]
output [2:0] io_out_bits_manager_id, // @[Arbiters.scala:14:14]
output [63:0] io_out_bits_data // @[Arbiters.scala:14:14]
);
wire io_in_0_valid_0 = io_in_0_valid; // @[Arbiter.scala:7:7]
wire [2:0] io_in_0_bits_opcode_0 = io_in_0_bits_opcode; // @[Arbiter.scala:7:7]
wire [3:0] io_in_0_bits_client_id_0 = io_in_0_bits_client_id; // @[Arbiter.scala:7:7]
wire [2:0] io_in_0_bits_manager_id_0 = io_in_0_bits_manager_id; // @[Arbiter.scala:7:7]
wire [63:0] io_in_0_bits_data_0 = io_in_0_bits_data; // @[Arbiter.scala:7:7]
wire io_out_ready_0 = io_out_ready; // @[Arbiter.scala:7:7]
wire _io_in_0_ready_T = 1'h1; // @[Arbiters.scala:40:46]
wire chosen = 1'h0; // @[Arbiters.scala:37:19]
wire _io_in_0_ready_T_1; // @[Arbiters.scala:40:36]
wire _io_out_valid_WIRE = 1'h0;
wire _io_out_bits_WIRE = 1'h0;
wire io_out_valid_0 = io_in_0_valid_0; // @[Arbiter.scala:7:7]
wire [2:0] io_out_bits_opcode_0 = io_in_0_bits_opcode_0; // @[Arbiter.scala:7:7]
wire [3:0] io_out_bits_client_id_0 = io_in_0_bits_client_id_0; // @[Arbiter.scala:7:7]
wire [2:0] io_out_bits_manager_id_0 = io_in_0_bits_manager_id_0; // @[Arbiter.scala:7:7]
wire [63:0] io_out_bits_data_0 = io_in_0_bits_data_0; // @[Arbiter.scala:7:7]
assign _io_in_0_ready_T_1 = io_out_ready_0; // @[Arbiters.scala:40:36]
wire io_in_0_ready_0; // @[Arbiter.scala:7:7]
reg locked; // @[Arbiters.scala:27:23]
assign io_in_0_ready_0 = _io_in_0_ready_T_1; // @[Arbiters.scala:40:36]
reg [1:0] beat; // @[Protocol.scala:54:23]
reg [1:0] max_beat; // @[Protocol.scala:55:27]
wire first = beat == 2'h0; // @[Protocol.scala:54:23, :56:22]
wire last; // @[Protocol.scala:57:20]
wire [6:0] _inst_T_7; // @[Protocol.scala:58:36]
wire [4:0] _inst_T_6; // @[Protocol.scala:58:36]
wire [4:0] _inst_T_5; // @[Protocol.scala:58:36]
wire _inst_T_4; // @[Protocol.scala:58:36]
wire _inst_T_3; // @[Protocol.scala:58:36]
wire _inst_T_2; // @[Protocol.scala:58:36]
wire [4:0] _inst_T_1; // @[Protocol.scala:58:36]
wire [6:0] _inst_T; // @[Protocol.scala:58:36]
wire [6:0] inst_funct; // @[Protocol.scala:58:36]
wire [4:0] inst_rs2; // @[Protocol.scala:58:36]
wire [4:0] inst_rs1; // @[Protocol.scala:58:36]
wire inst_xd; // @[Protocol.scala:58:36]
wire inst_xs1; // @[Protocol.scala:58:36]
wire inst_xs2; // @[Protocol.scala:58:36]
wire [4:0] inst_rd; // @[Protocol.scala:58:36]
wire [6:0] inst_opcode; // @[Protocol.scala:58:36]
wire [31:0] _inst_WIRE = io_out_bits_data_0[31:0]; // @[Protocol.scala:58:36]
assign _inst_T = _inst_WIRE[6:0]; // @[Protocol.scala:58:36]
assign inst_opcode = _inst_T; // @[Protocol.scala:58:36]
assign _inst_T_1 = _inst_WIRE[11:7]; // @[Protocol.scala:58:36]
assign inst_rd = _inst_T_1; // @[Protocol.scala:58:36]
assign _inst_T_2 = _inst_WIRE[12]; // @[Protocol.scala:58:36]
assign inst_xs2 = _inst_T_2; // @[Protocol.scala:58:36]
assign _inst_T_3 = _inst_WIRE[13]; // @[Protocol.scala:58:36]
assign inst_xs1 = _inst_T_3; // @[Protocol.scala:58:36]
assign _inst_T_4 = _inst_WIRE[14]; // @[Protocol.scala:58:36]
assign inst_xd = _inst_T_4; // @[Protocol.scala:58:36]
assign _inst_T_5 = _inst_WIRE[19:15]; // @[Protocol.scala:58:36]
assign inst_rs1 = _inst_T_5; // @[Protocol.scala:58:36]
assign _inst_T_6 = _inst_WIRE[24:20]; // @[Protocol.scala:58:36]
assign inst_rs2 = _inst_T_6; // @[Protocol.scala:58:36]
assign _inst_T_7 = _inst_WIRE[31:25]; // @[Protocol.scala:58:36]
assign inst_funct = _inst_T_7; // @[Protocol.scala:58:36]
wire [1:0] _max_beat_T = {1'h0, inst_xs1} + {1'h0, inst_xs2}; // @[Protocol.scala:58:36, :63:32]
wire _GEN = beat == max_beat; // @[Protocol.scala:54:23, :55:27, :77:22]
wire _last_T; // @[Protocol.scala:77:22]
assign _last_T = _GEN; // @[Protocol.scala:77:22]
wire _last_T_6; // @[Protocol.scala:79:57]
assign _last_T_6 = _GEN; // @[Protocol.scala:77:22, :79:57]
wire _last_T_1 = ~first; // @[Protocol.scala:56:22, :77:38]
wire _last_T_2 = _last_T & _last_T_1; // @[Protocol.scala:77:{22,35,38}]
wire _last_T_3 = ~inst_xs1; // @[Protocol.scala:58:36, :79:28]
wire _last_T_4 = ~inst_xs2; // @[Protocol.scala:58:36, :79:41]
wire _last_T_5 = _last_T_3 & _last_T_4; // @[Protocol.scala:79:{28,38,41}]
wire _last_T_7 = first ? _last_T_5 : _last_T_6; // @[Protocol.scala:56:22, :79:{20,38,57}]
assign last = io_out_bits_opcode_0 == 3'h2 ? _last_T_2 : io_out_bits_opcode_0 != 3'h1 | _last_T_7; // @[Protocol.scala:57:20, :74:10, :76:{27,56}, :77:{14,35}, :78:{34,60}, :79:{14,20}, :87:34]
wire [2:0] _beat_T = {1'h0, beat} + 3'h1; // @[Protocol.scala:54:23, :87:34]
wire [1:0] _beat_T_1 = _beat_T[1:0]; // @[Protocol.scala:87:34]
wire _T_9 = io_out_ready_0 & io_out_valid_0; // @[Decoupled.scala:51:35]
always @(posedge clock) begin // @[Arbiter.scala:7:7]
if (reset) begin // @[Arbiter.scala:7:7]
locked <= 1'h0; // @[Arbiters.scala:27:23]
beat <= 2'h0; // @[Protocol.scala:54:23]
max_beat <= 2'h0; // @[Protocol.scala:55:27]
end
else begin // @[Arbiter.scala:7:7]
if (_T_9) // @[Decoupled.scala:51:35]
locked <= ~last; // @[Arbiters.scala:27:23]
if (_T_9 & last) begin // @[Decoupled.scala:51:35]
beat <= 2'h0; // @[Protocol.scala:54:23]
max_beat <= 2'h0; // @[Protocol.scala:55:27]
end
else begin // @[Protocol.scala:88:18]
if (_T_9) // @[Decoupled.scala:51:35]
beat <= _beat_T_1; // @[Protocol.scala:54:23, :87:34]
if (_T_9 & first) // @[Decoupled.scala:51:35]
max_beat <= io_out_bits_opcode_0 == 3'h1 ? _max_beat_T : {1'h0, io_out_bits_opcode_0 == 3'h2}; // @[Protocol.scala:55:27, :60:16, :62:{29,55}, :63:{20,32}, :64:{36,65}, :65:20, :87:34]
end
end
always @(posedge)
assign io_in_0_ready = io_in_0_ready_0; // @[Arbiter.scala:7:7]
assign io_out_valid = io_out_valid_0; // @[Arbiter.scala:7:7]
assign io_out_bits_opcode = io_out_bits_opcode_0; // @[Arbiter.scala:7:7]
assign io_out_bits_client_id = io_out_bits_client_id_0; // @[Arbiter.scala:7:7]
assign io_out_bits_manager_id = io_out_bits_manager_id_0; // @[Arbiter.scala:7:7]
assign io_out_bits_data = io_out_bits_data_0; // @[Arbiter.scala:7:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Bundles.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import freechips.rocketchip.util._
import scala.collection.immutable.ListMap
import chisel3.util.Decoupled
import chisel3.util.DecoupledIO
import chisel3.reflect.DataMirror
abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle
// common combos in lazy policy:
// Put + Acquire
// Release + AccessAck
object TLMessages
{
// A B C D E
def PutFullData = 0.U // . . => AccessAck
def PutPartialData = 1.U // . . => AccessAck
def ArithmeticData = 2.U // . . => AccessAckData
def LogicalData = 3.U // . . => AccessAckData
def Get = 4.U // . . => AccessAckData
def Hint = 5.U // . . => HintAck
def AcquireBlock = 6.U // . => Grant[Data]
def AcquirePerm = 7.U // . => Grant[Data]
def Probe = 6.U // . => ProbeAck[Data]
def AccessAck = 0.U // . .
def AccessAckData = 1.U // . .
def HintAck = 2.U // . .
def ProbeAck = 4.U // .
def ProbeAckData = 5.U // .
def Release = 6.U // . => ReleaseAck
def ReleaseData = 7.U // . => ReleaseAck
def Grant = 4.U // . => GrantAck
def GrantData = 5.U // . => GrantAck
def ReleaseAck = 6.U // .
def GrantAck = 0.U // .
def isA(x: UInt) = x <= AcquirePerm
def isB(x: UInt) = x <= Probe
def isC(x: UInt) = x <= ReleaseData
def isD(x: UInt) = x <= ReleaseAck
def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant)
def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck)
def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("AcquireBlock",TLPermissions.PermMsgGrow),
("AcquirePerm",TLPermissions.PermMsgGrow))
def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("Probe",TLPermissions.PermMsgCap))
def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("ProbeAck",TLPermissions.PermMsgReport),
("ProbeAckData",TLPermissions.PermMsgReport),
("Release",TLPermissions.PermMsgReport),
("ReleaseData",TLPermissions.PermMsgReport))
def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("Grant",TLPermissions.PermMsgCap),
("GrantData",TLPermissions.PermMsgCap),
("ReleaseAck",TLPermissions.PermMsgReserved))
}
/**
* The three primary TileLink permissions are:
* (T)runk: the agent is (or is on inwards path to) the global point of serialization.
* (B)ranch: the agent is on an outwards path to
* (N)one:
* These permissions are permuted by transfer operations in various ways.
* Operations can cap permissions, request for them to be grown or shrunk,
* or for a report on their current status.
*/
object TLPermissions
{
val aWidth = 2
val bdWidth = 2
val cWidth = 3
// Cap types (Grant = new permissions, Probe = permisions <= target)
def toT = 0.U(bdWidth.W)
def toB = 1.U(bdWidth.W)
def toN = 2.U(bdWidth.W)
def isCap(x: UInt) = x <= toN
// Grow types (Acquire = permissions >= target)
def NtoB = 0.U(aWidth.W)
def NtoT = 1.U(aWidth.W)
def BtoT = 2.U(aWidth.W)
def isGrow(x: UInt) = x <= BtoT
// Shrink types (ProbeAck, Release)
def TtoB = 0.U(cWidth.W)
def TtoN = 1.U(cWidth.W)
def BtoN = 2.U(cWidth.W)
def isShrink(x: UInt) = x <= BtoN
// Report types (ProbeAck, Release)
def TtoT = 3.U(cWidth.W)
def BtoB = 4.U(cWidth.W)
def NtoN = 5.U(cWidth.W)
def isReport(x: UInt) = x <= NtoN
def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT")
def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN")
def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN")
def PermMsgReserved:Seq[String] = Seq("Reserved")
}
object TLAtomics
{
val width = 3
// Arithmetic types
def MIN = 0.U(width.W)
def MAX = 1.U(width.W)
def MINU = 2.U(width.W)
def MAXU = 3.U(width.W)
def ADD = 4.U(width.W)
def isArithmetic(x: UInt) = x <= ADD
// Logical types
def XOR = 0.U(width.W)
def OR = 1.U(width.W)
def AND = 2.U(width.W)
def SWAP = 3.U(width.W)
def isLogical(x: UInt) = x <= SWAP
def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD")
def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP")
}
object TLHints
{
val width = 1
def PREFETCH_READ = 0.U(width.W)
def PREFETCH_WRITE = 1.U(width.W)
def isHints(x: UInt) = x <= PREFETCH_WRITE
def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite")
}
sealed trait TLChannel extends TLBundleBase {
val channelName: String
}
sealed trait TLDataChannel extends TLChannel
sealed trait TLAddrChannel extends TLDataChannel
final class TLBundleA(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleA_${params.shortName}"
val channelName = "'A' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleB(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleB_${params.shortName}"
val channelName = "'B' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val address = UInt(params.addressBits.W) // from
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleC(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleC_${params.shortName}"
val channelName = "'C' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.cWidth.W) // shrink or report perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleD(params: TLBundleParameters)
extends TLBundleBase(params) with TLDataChannel
{
override def typeName = s"TLBundleD_${params.shortName}"
val channelName = "'D' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val sink = UInt(params.sinkBits.W) // from
val denied = Bool() // implies corrupt iff *Data
val user = BundleMap(params.responseFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleE(params: TLBundleParameters)
extends TLBundleBase(params) with TLChannel
{
override def typeName = s"TLBundleE_${params.shortName}"
val channelName = "'E' channel"
val sink = UInt(params.sinkBits.W) // to
}
class TLBundle(val params: TLBundleParameters) extends Record
{
// Emulate a Bundle with elements abcde or ad depending on params.hasBCE
private val optA = Some (Decoupled(new TLBundleA(params)))
private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params))))
private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params)))
private val optD = Some (Flipped(Decoupled(new TLBundleD(params))))
private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params)))
def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params)))))
def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params)))))
def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params)))))
def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params)))))
def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params)))))
val elements =
if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a)
else ListMap("d" -> d, "a" -> a)
def tieoff(): Unit = {
DataMirror.specifiedDirectionOf(a.ready) match {
case SpecifiedDirection.Input =>
a.ready := false.B
c.ready := false.B
e.ready := false.B
b.valid := false.B
d.valid := false.B
case SpecifiedDirection.Output =>
a.valid := false.B
c.valid := false.B
e.valid := false.B
b.ready := false.B
d.ready := false.B
case _ =>
}
}
}
object TLBundle
{
def apply(params: TLBundleParameters) = new TLBundle(params)
}
class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle
class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params)
{
val a = new AsyncBundle(new TLBundleA(params.base), params.async)
val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async))
val c = new AsyncBundle(new TLBundleC(params.base), params.async)
val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async))
val e = new AsyncBundle(new TLBundleE(params.base), params.async)
}
class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = RationalIO(new TLBundleA(params))
val b = Flipped(RationalIO(new TLBundleB(params)))
val c = RationalIO(new TLBundleC(params))
val d = Flipped(RationalIO(new TLBundleD(params)))
val e = RationalIO(new TLBundleE(params))
}
class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = CreditedIO(new TLBundleA(params))
val b = Flipped(CreditedIO(new TLBundleB(params)))
val c = CreditedIO(new TLBundleC(params))
val d = Flipped(CreditedIO(new TLBundleD(params)))
val e = CreditedIO(new TLBundleE(params))
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor_22( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [25:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [25:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59]
wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27]
wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25]
wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_28 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_30 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_44 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_46 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_50 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_52 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_56 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_58 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_62 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_64 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_69 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_71 = 1'h1; // @[Parameters.scala:57:20]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28]
wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_first_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_first_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_first_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_first_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_set_wo_ready_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_set_wo_ready_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_opcodes_set_interm_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_opcodes_set_interm_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_sizes_set_interm_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_sizes_set_interm_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_opcodes_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_opcodes_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_sizes_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_sizes_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_probe_ack_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_probe_ack_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_probe_ack_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_probe_ack_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _same_cycle_resp_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _same_cycle_resp_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _same_cycle_resp_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _same_cycle_resp_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _same_cycle_resp_WIRE_4_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _same_cycle_resp_WIRE_5_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54]
wire [1026:0] _c_sizes_set_T_1 = 1027'h0; // @[Monitor.scala:768:52]
wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79]
wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51]
wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35]
wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35]
wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34]
wire [259:0] c_sizes_set = 260'h0; // @[Monitor.scala:741:34]
wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34]
wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34]
wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46]
wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76]
wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_26 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire _source_ok_T_25 = io_in_a_bits_source_0 == 7'h28; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_27 = _source_ok_T_26 == 5'h8; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_29 = _source_ok_T_27; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_31 = _source_ok_T_29; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_6 = _source_ok_T_31; // @[Parameters.scala:1138:31]
wire _source_ok_T_32 = io_in_a_bits_source_0 == 7'h24; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_7 = _source_ok_T_32; // @[Parameters.scala:1138:31]
wire _source_ok_T_33 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_8 = _source_ok_T_33; // @[Parameters.scala:1138:31]
wire _source_ok_T_34 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_35 = _source_ok_T_34 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_36 = _source_ok_T_35 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_37 = _source_ok_T_36 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_38 = _source_ok_T_37 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_39 = _source_ok_T_38 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_40 = _source_ok_T_39 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_40 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46]
wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [25:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 26'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_46 = _uncommonBits_T_46[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_47 = _uncommonBits_T_47[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_52 = _uncommonBits_T_52[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_53 = _uncommonBits_T_53[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_54 = _uncommonBits_T_54[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_41 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_41; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_42 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_48 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_54 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_60 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_67 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_43 = _source_ok_T_42 == 5'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_45 = _source_ok_T_43; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_47 = _source_ok_T_45; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_47; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_49 = _source_ok_T_48 == 5'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_51 = _source_ok_T_49; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_53 = _source_ok_T_51; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_53; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_55 = _source_ok_T_54 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_57 = _source_ok_T_55; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_59 = _source_ok_T_57; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_59; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_61 = _source_ok_T_60 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_63 = _source_ok_T_61; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_65 = _source_ok_T_63; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_65; // @[Parameters.scala:1138:31]
wire _source_ok_T_66 = io_in_d_bits_source_0 == 7'h28; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_5 = _source_ok_T_66; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_68 = _source_ok_T_67 == 5'h8; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_70 = _source_ok_T_68; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_72 = _source_ok_T_70; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_6 = _source_ok_T_72; // @[Parameters.scala:1138:31]
wire _source_ok_T_73 = io_in_d_bits_source_0 == 7'h24; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_7 = _source_ok_T_73; // @[Parameters.scala:1138:31]
wire _source_ok_T_74 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_8 = _source_ok_T_74; // @[Parameters.scala:1138:31]
wire _source_ok_T_75 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_76 = _source_ok_T_75 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_77 = _source_ok_T_76 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_78 = _source_ok_T_77 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_79 = _source_ok_T_78 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_80 = _source_ok_T_79 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_81 = _source_ok_T_80 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_81 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46]
wire _T_1156 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1156; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1156; // @[Decoupled.scala:51:35]
wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [6:0] source; // @[Monitor.scala:390:22]
reg [25:0] address; // @[Monitor.scala:391:22]
wire _T_1229 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1229; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1229; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1229; // @[Decoupled.scala:51:35]
wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [6:0] source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [64:0] inflight; // @[Monitor.scala:614:27]
reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [259:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [64:0] a_set; // @[Monitor.scala:626:34]
wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [259:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [259:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [259:0] _a_size_lookup_T_6 = {256'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [259:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[259:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [127:0] _GEN_2 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [127:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1082 = _T_1156 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1082 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1082 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1082 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [9:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1082 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1082 ? _a_sizes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [64:0] d_clr; // @[Monitor.scala:664:34]
wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [259:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_1128 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1128 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1097 = _T_1229 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1097 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1097 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1097 ? _d_sizes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [64:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [259:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [259:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [259:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [259:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [64:0] inflight_1; // @[Monitor.scala:726:35]
wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [259:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [259:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [259:0] _c_size_lookup_T_6 = {256'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [259:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[259:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [64:0] d_clr_1; // @[Monitor.scala:774:34]
wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [259:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1200 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1200 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1182 = _T_1229 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1182 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1182 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1182 ? _d_sizes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113]
wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [259:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [259:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to the following Chisel files.
File Nodes.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection}
case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args))
object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
{
def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo)
def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo)
def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle)
def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle)
def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString)
override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = {
val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge)))
monitor.io.in := bundle
}
override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters =
pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })
override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters =
pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })
}
trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut]
case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode
case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode
case class TLAdapterNode(
clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s },
managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLJunctionNode(
clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters],
managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])(
implicit valName: ValName)
extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode
object TLNameNode {
def apply(name: ValName) = TLIdentityNode()(name)
def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLIdentityNode = apply(Some(name))
}
case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)()
object TLTempNode {
def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp"))
}
case class TLNexusNode(
clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters,
managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)(
implicit valName: ValName)
extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode
abstract class TLCustomNode(implicit valName: ValName)
extends CustomNode(TLImp) with TLFormatNode
// Asynchronous crossings
trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters]
object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle]
{
def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle)
def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString)
override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLAsyncAdapterNode(
clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s },
managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode
case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode
object TLAsyncNameNode {
def apply(name: ValName) = TLAsyncIdentityNode()(name)
def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLAsyncIdentityNode = apply(Some(name))
}
case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLAsyncImp)(
dFn = { p => TLAsyncClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain
case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName)
extends MixedAdapterNode(TLAsyncImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) },
uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut]
// Rationally related crossings
trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters]
object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle]
{
def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle)
def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */)
override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLRationalAdapterNode(
clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s },
managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode
case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode
object TLRationalNameNode {
def apply(name: ValName) = TLRationalIdentityNode()(name)
def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLRationalIdentityNode = apply(Some(name))
}
case class TLRationalSourceNode()(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLRationalImp)(
dFn = { p => TLRationalClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain
case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName)
extends MixedAdapterNode(TLRationalImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut]
// Credited version of TileLink channels
trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters]
object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle]
{
def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle)
def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString)
override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLCreditedAdapterNode(
clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s },
managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode
case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode
object TLCreditedNameNode {
def apply(name: ValName) = TLCreditedIdentityNode()(name)
def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLCreditedIdentityNode = apply(Some(name))
}
case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLCreditedImp)(
dFn = { p => TLCreditedClientPortParameters(delay, p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain
case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLCreditedImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut]
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
File BootROM.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.devices.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.bundlebridge._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.{AddressSet, RegionType, TransferSizes}
import freechips.rocketchip.resources.{Resource, SimpleDevice}
import freechips.rocketchip.subsystem._
import freechips.rocketchip.tilelink.{TLFragmenter, TLManagerNode, TLSlaveParameters, TLSlavePortParameters}
import java.nio.ByteBuffer
import java.nio.file.{Files, Paths}
/** Size, location and contents of the boot rom. */
case class BootROMParams(
address: BigInt = 0x10000,
size: Int = 0x10000,
hang: BigInt = 0x10040, // The hang parameter is used as the power-on reset vector
contentFileName: String)
class TLROM(val base: BigInt, val size: Int, contentsDelayed: => Seq[Byte], executable: Boolean = true, beatBytes: Int = 4,
resources: Seq[Resource] = new SimpleDevice("rom", Seq("sifive,rom0")).reg("mem"))(implicit p: Parameters) extends LazyModule
{
val node = TLManagerNode(Seq(TLSlavePortParameters.v1(
Seq(TLSlaveParameters.v1(
address = List(AddressSet(base, size-1)),
resources = resources,
regionType = RegionType.UNCACHED,
executable = executable,
supportsGet = TransferSizes(1, beatBytes),
fifoId = Some(0))),
beatBytes = beatBytes)))
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
val contents = contentsDelayed
val wrapSize = 1 << log2Ceil(contents.size)
require (wrapSize <= size)
val (in, edge) = node.in(0)
val words = (contents ++ Seq.fill(wrapSize-contents.size)(0.toByte)).grouped(beatBytes).toSeq
val bigs = words.map(_.foldRight(BigInt(0)){ case (x,y) => (x.toInt & 0xff) | y << 8})
val rom = VecInit(bigs.map(_.U((8*beatBytes).W)))
in.d.valid := in.a.valid
in.a.ready := in.d.ready
val index = in.a.bits.address(log2Ceil(wrapSize)-1,log2Ceil(beatBytes))
val high = if (wrapSize == size) 0.U else in.a.bits.address(log2Ceil(size)-1, log2Ceil(wrapSize))
in.d.bits := edge.AccessAck(in.a.bits, Mux(high.orR, 0.U, rom(index)))
// Tie off unused channels
in.b.valid := false.B
in.c.ready := true.B
in.e.ready := true.B
}
}
case class BootROMLocated(loc: HierarchicalLocation) extends Field[Option[BootROMParams]](None)
object BootROM {
/** BootROM.attach not only instantiates a TLROM and attaches it to the tilelink interconnect
* at a configurable location, but also drives the tiles' reset vectors to point
* at its 'hang' address parameter value.
*/
def attach(params: BootROMParams, subsystem: BaseSubsystem with HasHierarchicalElements with HasTileInputConstants, where: TLBusWrapperLocation)
(implicit p: Parameters): TLROM = {
val tlbus = subsystem.locateTLBusWrapper(where)
val bootROMDomainWrapper = tlbus.generateSynchronousDomain("BootROM").suggestName("bootrom_domain")
val bootROMResetVectorSourceNode = BundleBridgeSource[UInt]()
lazy val contents = {
val romdata = Files.readAllBytes(Paths.get(params.contentFileName))
val rom = ByteBuffer.wrap(romdata)
rom.array() ++ subsystem.dtb.contents
}
val bootrom = bootROMDomainWrapper {
LazyModule(new TLROM(params.address, params.size, contents, true, tlbus.beatBytes))
}
bootrom.node := tlbus.coupleTo("bootrom"){ TLFragmenter(tlbus, Some("BootROM")) := _ }
// Drive the `subsystem` reset vector to the `hang` address of this Boot ROM.
subsystem.tileResetVectorNexusNode := bootROMResetVectorSourceNode
InModuleBody {
val reset_vector_source = bootROMResetVectorSourceNode.bundle
require(reset_vector_source.getWidth >= params.hang.bitLength,
s"BootROM defined with a reset vector (${params.hang})too large for physical address space (${reset_vector_source.getWidth})")
bootROMResetVectorSourceNode.bundle := params.hang.U
}
bootrom
}
}
| module TLROM( // @[BootROM.scala:41:9]
input clock, // @[BootROM.scala:41:9]
input reset, // @[BootROM.scala:41:9]
output auto_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [10:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [16:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [10:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_d_bits_data // @[LazyModuleImp.scala:107:25]
);
wire auto_in_a_valid_0 = auto_in_a_valid; // @[BootROM.scala:41:9]
wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[BootROM.scala:41:9]
wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[BootROM.scala:41:9]
wire [1:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[BootROM.scala:41:9]
wire [10:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[BootROM.scala:41:9]
wire [16:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[BootROM.scala:41:9]
wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[BootROM.scala:41:9]
wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[BootROM.scala:41:9]
wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[BootROM.scala:41:9]
wire auto_in_d_ready_0 = auto_in_d_ready; // @[BootROM.scala:41:9]
wire [511:0][63:0] _GEN =
'{64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h73747075727265,
64'h746E6900746E6572,
64'h61702D7470757272,
64'h65746E6900736B63,
64'h6F6C63007665646E,
64'h2C76637369720079,
64'h7469726F6972702D,
64'h78616D2C76637369,
64'h7200686361747461,
64'h2D67756265640064,
64'h65646E657478652D,
64'h7374707572726574,
64'h6E690073656D616E,
64'h2D74757074756F2D,
64'h6B636F6C6300736C,
64'h6C65632D6B636F6C,
64'h632300746E756F63,
64'h2D7268736D2C6576,
64'h6966697300646569,
64'h66696E752D656863,
64'h6163006C6576656C,
64'h2D65686361630073,
64'h656D616E2D676572,
64'h7365676E617200,
64'h656C646E61687000,
64'h72656C6C6F72746E,
64'h6F632D7470757272,
64'h65746E6900736C6C,
64'h65632D7470757272,
64'h65746E6923007469,
64'h6C70732D626C7400,
64'h7375746174730073,
64'h6E6F69676572706D,
64'h702C766373697200,
64'h79746972616C756E,
64'h617267706D702C76,
64'h6373697200617369,
64'h2C76637369720067,
64'h6572006568636163,
64'h2D6C6576656C2D74,
64'h78656E0065707974,
64'h2D756D6D00657A69,
64'h732D626C742D6900,
64'h737465732D626C74,
64'h2D6900657A69732D,
64'h65686361632D6900,
64'h737465732D656863,
64'h61632D6900657A69,
64'h732D6B636F6C622D,
64'h65686361632D6900,
64'h746E756F632D746E,
64'h696F706B61657262,
64'h2D636578652D6572,
64'h6177647261680065,
64'h7079745F65636976,
64'h656400657A69732D,
64'h626C742D64007374,
64'h65732D626C742D64,
64'h657A69732D6568,
64'h6361632D64007374,
64'h65732D6568636163,
64'h2D6400657A69732D,
64'h6B636F6C622D6568,
64'h6361632D64007963,
64'h6E6575716572662D,
64'h6B636F6C63007963,
64'h6E6575716572662D,
64'h65736162656D6974,
64'h687461702D7475,
64'h6F64747300306C61,
64'h69726573006C6564,
64'h6F6D00656C626974,
64'h61706D6F6300736C,
64'h6C65632D657A6973,
64'h2300736C6C65632D,
64'h7373657264646123,
64'h900000002000000,
64'h200000002000000,
64'h6C6F72746E6F63,
64'hA801000008000000,
64'h300000000100000,
64'h11002E010000,
64'h800000003000000,
64'h30303030,
64'h3131407265747465,
64'h732D74657365722D,
64'h656C697401000000,
64'h2000000006C6F72,
64'h746E6F63A8010000,
64'h800000003000000,
64'h10000000000210,
64'h2E01000008000000,
64'h300000001000000,
64'h5502000004000000,
64'h300000006000000,
64'h4402000004000000,
64'h300000000000000,
64'h30747261752C6576,
64'h696669731B000000,
64'hD00000003000000,
64'h50000003D020000,
64'h400000003000000,
64'h30303030323030,
64'h31406C6169726573,
64'h100000002000000,
64'h6B636F6C632D64,
64'h657869661B000000,
64'hC00000003000000,
64'h6B636F6C635F,
64'h73756273EB010000,
64'hB00000003000000,
64'h65CD1D53000000,
64'h400000003000000,
64'hDE010000,
64'h400000003000000,
64'h6B636F6C635F,
64'h7375627301000000,
64'h2000000006D656D,
64'hA801000004000000,
64'h300000000000100,
64'h1002E010000,
64'h800000003000000,
64'h306D6F722C6576,
64'h696669731B000000,
64'hC00000003000000,
64'h3030303031,
64'h406D6F7201000000,
64'h200000005000000,
64'h9901000004000000,
64'h3000000006B636F,
64'h6C632D6465786966,
64'h1B0000000C000000,
64'h300000000006B63,
64'h6F6C635F73756270,
64'hEB0100000B000000,
64'h30000000065CD1D,
64'h5300000004000000,
64'h300000000000000,
64'hDE01000004000000,
64'h300000000006B63,
64'h6F6C635F73756270,
64'h100000002000000,
64'h6B636F6C632D64,
64'h657869661B000000,
64'hC00000003000000,
64'h6B636F6C635F,
64'h7375626DEB010000,
64'hB00000003000000,
64'h65CD1D53000000,
64'h400000003000000,
64'hDE010000,
64'h400000003000000,
64'h6B636F6C635F,
64'h7375626D01000000,
64'h200000006000000,
64'h9901000004000000,
64'h300000001000000,
64'h3202000004000000,
64'h300000001000000,
64'h1F02000004000000,
64'h3000000006C6F72,
64'h746E6F63A8010000,
64'h800000003000000,
64'h40000000C,
64'h2E01000008000000,
64'h300000009000000,
64'h40000000B000000,
64'h4000000FE010000,
64'h1000000003000000,
64'h8401000000000000,
64'h300000000306369,
64'h6C702C7663736972,
64'h1B0000000C000000,
64'h300000001000000,
64'h7301000004000000,
64'h300000000000000,
64'h3030303030306340,
64'h72656C6C6F72746E,
64'h6F632D7470757272,
64'h65746E6901000000,
64'h2000000006B636F,
64'h6C632D6465786966,
64'h1B0000000C000000,
64'h300000000006B63,
64'h6F6C635F73756266,
64'hEB0100000B000000,
64'h30000000065CD1D,
64'h5300000004000000,
64'h300000000000000,
64'hDE01000004000000,
64'h300000000006B63,
64'h6F6C635F73756266,
64'h100000002000000,
64'h10000000300000,
64'h2E01000008000000,
64'h300000000000030,
64'h726F7272652C6576,
64'h696669731B000000,
64'hE00000003000000,
64'h3030303340,
64'h6563697665642D72,
64'h6F72726501000000,
64'h2000000006C6F72,
64'h746E6F63A8010000,
64'h800000003000000,
64'h10000000000000,
64'h2E01000008000000,
64'h3000000FFFF0000,
64'h4000000FE010000,
64'h800000003000000,
64'h6761746A,
64'h1202000005000000,
64'h300000000000000,
64'h3331302D67756265,
64'h642C766373697200,
64'h3331302D67756265,
64'h642C657669666973,
64'h1B00000021000000,
64'h300000000003040,
64'h72656C6C6F72746E,
64'h6F632D6775626564,
64'h100000002000000,
64'h6C6F72746E6F63,
64'hA801000008000000,
64'h300000000100000,
64'h10002E010000,
64'h800000003000000,
64'h303030303031,
64'h4072657461672D6B,
64'h636F6C6301000000,
64'h2000000006C6F72,
64'h746E6F63A8010000,
64'h800000003000000,
64'h10000000002,
64'h2E01000008000000,
64'h300000007000000,
64'h400000003000000,
64'h4000000FE010000,
64'h1000000003000000,
64'h30746E69,
64'h6C632C7663736972,
64'h1B0000000D000000,
64'h300000000000030,
64'h3030303030324074,
64'h6E696C6301000000,
64'h2000000006B636F,
64'h6C632D6465786966,
64'h1B0000000C000000,
64'h300000000006B63,
64'h6F6C635F73756263,
64'hEB0100000B000000,
64'h30000000065CD1D,
64'h5300000004000000,
64'h300000000000000,
64'hDE01000004000000,
64'h300000000006B63,
64'h6F6C635F73756263,
64'h100000002000000,
64'h100000099010000,
64'h400000003000000,
64'h7000000CC010000,
64'h400000003000000,
64'h6C6F72746E6F63,
64'hA801000008000000,
64'h300000000100000,
64'h1022E010000,
64'h800000003000000,
64'h300000002000000,
64'h1D01000008000000,
64'h300000000000000,
64'h6568636163003065,
64'h6863616365766973,
64'h756C636E692C6576,
64'h696669731B000000,
64'h1D00000003000000,
64'hBE01000000000000,
64'h300000000000800,
64'h8500000004000000,
64'h300000000040000,
64'h7800000004000000,
64'h300000002000000,
64'hB201000004000000,
64'h300000040000000,
64'h6500000004000000,
64'h300000000000000,
64'h3030303031303240,
64'h72656C6C6F72746E,
64'h6F632D6568636163,
64'h100000002000000,
64'h6C6F72746E6F63,
64'hA801000008000000,
64'h300000000100000,
64'h1000002E010000,
64'h800000003000000,
64'h3030303140,
64'h6765722D73736572,
64'h6464612D746F6F62,
64'h1000000A1010000,
64'h3000000,
64'h7375622D656C70,
64'h6D697300636F732D,
64'h6472617970696863,
64'h2C7261622D626375,
64'h1B00000020000000,
64'h300000001000000,
64'hF00000004000000,
64'h300000001000000,
64'h4000000,
64'h300000000636F73,
64'h100000002000000,
64'h200000099010000,
64'h400000003000000,
64'h1000000080,
64'h2E01000008000000,
64'h300000000007972,
64'h6F6D656DA6000000,
64'h700000003000000,
64'h30303030303030,
64'h384079726F6D656D,
64'h100000002000000,
64'h300000099010000,
64'h400000003000000,
64'h64656C62,
64'h6173696462010000,
64'h900000003000000,
64'h10000000008,
64'h2E01000008000000,
64'h300000000007972,
64'h6F6D656DA6000000,
64'h700000003000000,
64'h303030303030,
64'h384079726F6D656D,
64'h100000002000000,
64'h3066697468,
64'h2C6263751B000000,
64'hA00000003000000,
64'h66697468,
64'h100000002000000,
64'h200000002000000,
64'h400000099010000,
64'h400000003000000,
64'h8401000000000000,
64'h300000000006374,
64'h6E692D7570632C76,
64'h637369721B000000,
64'hF00000003000000,
64'h100000073010000,
64'h400000003000000,
64'h72656C6C,
64'h6F72746E6F632D74,
64'h7075727265746E69,
64'h100000069010000,
64'h3000000,
64'h20A1070040000000,
64'h400000003000000,
64'h79616B6F,
64'h6201000005000000,
64'h300000008000000,
64'h5101000004000000,
64'h300000004000000,
64'h3C01000004000000,
64'h30000000074656B,
64'h636F72785F73627A,
64'h5F62627A5F61627A,
64'h5F68667A5F6D7068,
64'h697A5F6965636E65,
64'h66697A5F72736369,
64'h7A62636466616D69,
64'h3436767232010000,
64'h3800000003000000,
64'h2E010000,
64'h400000003000000,
64'h10000001D010000,
64'h400000003000000,
64'h393376732C76,
64'h6373697214010000,
64'hB00000003000000,
64'h2000000009010000,
64'h400000003000000,
64'h1000000FE000000,
64'h400000003000000,
64'h800000F1000000,
64'h400000003000000,
64'h40000000E4000000,
64'h400000003000000,
64'h40000000D1000000,
64'h400000003000000,
64'h1000000B2000000,
64'h400000003000000,
64'h757063A6000000,
64'h400000003000000,
64'h200000009B000000,
64'h400000003000000,
64'h100000090000000,
64'h400000003000000,
64'h80000083000000,
64'h400000003000000,
64'h4000000076000000,
64'h400000003000000,
64'h4000000063000000,
64'h400000003000000,
64'h76637369,
64'h72003074656B636F,
64'h722C657669666973,
64'h1B00000015000000,
64'h300000000000000,
64'h5300000004000000,
64'h300000000000030,
64'h4075706301000000,
64'h20A1070040000000,
64'h400000003000000,
64'hF000000,
64'h400000003000000,
64'h100000000000000,
64'h400000003000000,
64'h73757063,
64'h100000002000000,
64'h30303030,
64'h32303031406C6169,
64'h7265732F636F732F,
64'h3400000015000000,
64'h300000000006E65,
64'h736F686301000000,
64'h200000000000000,
64'h3030303032303031,
64'h406C61697265732F,
64'h636F732F2C000000,
64'h1500000003000000,
64'h73657361696C61,
64'h100000000000000,
64'h6472617970696863,
64'h2C7261622D626375,
64'h2600000011000000,
64'h300000000000000,
64'h7665642D64726179,
64'h706968632C726162,
64'h2D6263751B000000,
64'h1500000003000000,
64'h10000000F000000,
64'h400000003000000,
64'h100000000000000,
64'h400000003000000,
64'h1000000,
64'h0,
64'h0,
64'h780B000060020000,
64'h10000000,
64'h1100000028000000,
64'hB00B000038000000,
64'h100E0000EDFE0DD0,
64'h1330200073,
64'h3006307308000613,
64'h185859300000597,
64'hF140257334151073,
64'h5350300001537,
64'h5A02300B505B3,
64'h251513FE029EE3,
64'h5A283F81FF06F,
64'h0,
64'h0,
64'h2C0006F,
64'hFE069AE3FFC62683,
64'h46061300D62023,
64'h10069300458613,
64'h380006F00050463,
64'hF1402573020005B7,
64'hFFDFF06F,
64'h1050007330052073,
64'h3045107300800513,
64'h3445307322200513,
64'h3030107300028863,
64'h12F2934122D293,
64'h301022F330551073,
64'h405051300000517};
wire [63:0] rom_0 = 64'h405051300000517; // @[BootROM.scala:50:22]
wire [63:0] rom_1 = 64'h301022F330551073; // @[BootROM.scala:50:22]
wire [63:0] rom_2 = 64'h12F2934122D293; // @[BootROM.scala:50:22]
wire [63:0] rom_3 = 64'h3030107300028863; // @[BootROM.scala:50:22]
wire [63:0] rom_4 = 64'h3445307322200513; // @[BootROM.scala:50:22]
wire [63:0] rom_5 = 64'h3045107300800513; // @[BootROM.scala:50:22]
wire [63:0] rom_6 = 64'h1050007330052073; // @[BootROM.scala:50:22]
wire [63:0] rom_7 = 64'hFFDFF06F; // @[BootROM.scala:50:22]
wire [63:0] rom_8 = 64'hF1402573020005B7; // @[BootROM.scala:50:22]
wire [63:0] rom_9 = 64'h380006F00050463; // @[BootROM.scala:50:22]
wire [63:0] rom_10 = 64'h10069300458613; // @[BootROM.scala:50:22]
wire [63:0] rom_11 = 64'h46061300D62023; // @[BootROM.scala:50:22]
wire [63:0] rom_12 = 64'hFE069AE3FFC62683; // @[BootROM.scala:50:22]
wire [63:0] rom_13 = 64'h2C0006F; // @[BootROM.scala:50:22]
wire [63:0] rom_16 = 64'h5A283F81FF06F; // @[BootROM.scala:50:22]
wire [63:0] rom_17 = 64'h251513FE029EE3; // @[BootROM.scala:50:22]
wire [63:0] rom_18 = 64'h5A02300B505B3; // @[BootROM.scala:50:22]
wire [63:0] rom_19 = 64'h5350300001537; // @[BootROM.scala:50:22]
wire [63:0] rom_20 = 64'hF140257334151073; // @[BootROM.scala:50:22]
wire [63:0] rom_21 = 64'h185859300000597; // @[BootROM.scala:50:22]
wire [63:0] rom_22 = 64'h3006307308000613; // @[BootROM.scala:50:22]
wire [63:0] rom_23 = 64'h1330200073; // @[BootROM.scala:50:22]
wire [63:0] rom_24 = 64'h100E0000EDFE0DD0; // @[BootROM.scala:50:22]
wire [63:0] rom_25 = 64'hB00B000038000000; // @[BootROM.scala:50:22]
wire [63:0] rom_26 = 64'h1100000028000000; // @[BootROM.scala:50:22]
wire [63:0] rom_27 = 64'h10000000; // @[BootROM.scala:50:22]
wire [63:0] rom_28 = 64'h780B000060020000; // @[BootROM.scala:50:22]
wire [63:0] rom_31 = 64'h1000000; // @[BootROM.scala:50:22]
wire [63:0] rom_35 = 64'h10000000F000000; // @[BootROM.scala:50:22]
wire [63:0] rom_37 = 64'h2D6263751B000000; // @[BootROM.scala:50:22]
wire [63:0] rom_38 = 64'h706968632C726162; // @[BootROM.scala:50:22]
wire [63:0] rom_39 = 64'h7665642D64726179; // @[BootROM.scala:50:22]
wire [63:0] rom_41 = 64'h2600000011000000; // @[BootROM.scala:50:22]
wire [63:0] rom_45 = 64'h73657361696C61; // @[BootROM.scala:50:22]
wire [63:0] rom_36 = 64'h1500000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_46 = 64'h1500000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_47 = 64'h636F732F2C000000; // @[BootROM.scala:50:22]
wire [63:0] rom_48 = 64'h406C61697265732F; // @[BootROM.scala:50:22]
wire [63:0] rom_49 = 64'h3030303032303031; // @[BootROM.scala:50:22]
wire [63:0] rom_50 = 64'h200000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_51 = 64'h736F686301000000; // @[BootROM.scala:50:22]
wire [63:0] rom_52 = 64'h300000000006E65; // @[BootROM.scala:50:22]
wire [63:0] rom_53 = 64'h3400000015000000; // @[BootROM.scala:50:22]
wire [63:0] rom_54 = 64'h7265732F636F732F; // @[BootROM.scala:50:22]
wire [63:0] rom_55 = 64'h32303031406C6169; // @[BootROM.scala:50:22]
wire [63:0] rom_58 = 64'h73757063; // @[BootROM.scala:50:22]
wire [63:0] rom_33 = 64'h100000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_44 = 64'h100000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_60 = 64'h100000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_62 = 64'hF000000; // @[BootROM.scala:50:22]
wire [63:0] rom_65 = 64'h4075706301000000; // @[BootROM.scala:50:22]
wire [63:0] rom_69 = 64'h1B00000015000000; // @[BootROM.scala:50:22]
wire [63:0] rom_70 = 64'h722C657669666973; // @[BootROM.scala:50:22]
wire [63:0] rom_71 = 64'h72003074656B636F; // @[BootROM.scala:50:22]
wire [63:0] rom_72 = 64'h76637369; // @[BootROM.scala:50:22]
wire [63:0] rom_74 = 64'h4000000063000000; // @[BootROM.scala:50:22]
wire [63:0] rom_76 = 64'h4000000076000000; // @[BootROM.scala:50:22]
wire [63:0] rom_78 = 64'h80000083000000; // @[BootROM.scala:50:22]
wire [63:0] rom_80 = 64'h100000090000000; // @[BootROM.scala:50:22]
wire [63:0] rom_82 = 64'h200000009B000000; // @[BootROM.scala:50:22]
wire [63:0] rom_84 = 64'h757063A6000000; // @[BootROM.scala:50:22]
wire [63:0] rom_86 = 64'h1000000B2000000; // @[BootROM.scala:50:22]
wire [63:0] rom_88 = 64'h40000000D1000000; // @[BootROM.scala:50:22]
wire [63:0] rom_90 = 64'h40000000E4000000; // @[BootROM.scala:50:22]
wire [63:0] rom_92 = 64'h800000F1000000; // @[BootROM.scala:50:22]
wire [63:0] rom_94 = 64'h1000000FE000000; // @[BootROM.scala:50:22]
wire [63:0] rom_96 = 64'h2000000009010000; // @[BootROM.scala:50:22]
wire [63:0] rom_98 = 64'h6373697214010000; // @[BootROM.scala:50:22]
wire [63:0] rom_99 = 64'h393376732C76; // @[BootROM.scala:50:22]
wire [63:0] rom_101 = 64'h10000001D010000; // @[BootROM.scala:50:22]
wire [63:0] rom_103 = 64'h2E010000; // @[BootROM.scala:50:22]
wire [63:0] rom_104 = 64'h3800000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_105 = 64'h3436767232010000; // @[BootROM.scala:50:22]
wire [63:0] rom_106 = 64'h7A62636466616D69; // @[BootROM.scala:50:22]
wire [63:0] rom_107 = 64'h66697A5F72736369; // @[BootROM.scala:50:22]
wire [63:0] rom_108 = 64'h697A5F6965636E65; // @[BootROM.scala:50:22]
wire [63:0] rom_109 = 64'h5F68667A5F6D7068; // @[BootROM.scala:50:22]
wire [63:0] rom_110 = 64'h5F62627A5F61627A; // @[BootROM.scala:50:22]
wire [63:0] rom_111 = 64'h636F72785F73627A; // @[BootROM.scala:50:22]
wire [63:0] rom_112 = 64'h30000000074656B; // @[BootROM.scala:50:22]
wire [63:0] rom_113 = 64'h3C01000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_114 = 64'h300000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_115 = 64'h5101000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_116 = 64'h300000008000000; // @[BootROM.scala:50:22]
wire [63:0] rom_117 = 64'h6201000005000000; // @[BootROM.scala:50:22]
wire [63:0] rom_118 = 64'h79616B6F; // @[BootROM.scala:50:22]
wire [63:0] rom_64 = 64'h20A1070040000000; // @[BootROM.scala:50:22]
wire [63:0] rom_120 = 64'h20A1070040000000; // @[BootROM.scala:50:22]
wire [63:0] rom_122 = 64'h100000069010000; // @[BootROM.scala:50:22]
wire [63:0] rom_123 = 64'h7075727265746E69; // @[BootROM.scala:50:22]
wire [63:0] rom_124 = 64'h6F72746E6F632D74; // @[BootROM.scala:50:22]
wire [63:0] rom_125 = 64'h72656C6C; // @[BootROM.scala:50:22]
wire [63:0] rom_127 = 64'h100000073010000; // @[BootROM.scala:50:22]
wire [63:0] rom_128 = 64'hF00000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_129 = 64'h637369721B000000; // @[BootROM.scala:50:22]
wire [63:0] rom_130 = 64'h6E692D7570632C76; // @[BootROM.scala:50:22]
wire [63:0] rom_131 = 64'h300000000006374; // @[BootROM.scala:50:22]
wire [63:0] rom_134 = 64'h400000099010000; // @[BootROM.scala:50:22]
wire [63:0] rom_137 = 64'h66697468; // @[BootROM.scala:50:22]
wire [63:0] rom_138 = 64'hA00000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_139 = 64'h2C6263751B000000; // @[BootROM.scala:50:22]
wire [63:0] rom_140 = 64'h3066697468; // @[BootROM.scala:50:22]
wire [63:0] rom_143 = 64'h303030303030; // @[BootROM.scala:50:22]
wire [63:0] rom_148 = 64'h10000000008; // @[BootROM.scala:50:22]
wire [63:0] rom_149 = 64'h900000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_150 = 64'h6173696462010000; // @[BootROM.scala:50:22]
wire [63:0] rom_151 = 64'h64656C62; // @[BootROM.scala:50:22]
wire [63:0] rom_153 = 64'h300000099010000; // @[BootROM.scala:50:22]
wire [63:0] rom_142 = 64'h384079726F6D656D; // @[BootROM.scala:50:22]
wire [63:0] rom_155 = 64'h384079726F6D656D; // @[BootROM.scala:50:22]
wire [63:0] rom_156 = 64'h30303030303030; // @[BootROM.scala:50:22]
wire [63:0] rom_144 = 64'h700000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_157 = 64'h700000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_145 = 64'h6F6D656DA6000000; // @[BootROM.scala:50:22]
wire [63:0] rom_158 = 64'h6F6D656DA6000000; // @[BootROM.scala:50:22]
wire [63:0] rom_146 = 64'h300000000007972; // @[BootROM.scala:50:22]
wire [63:0] rom_159 = 64'h300000000007972; // @[BootROM.scala:50:22]
wire [63:0] rom_161 = 64'h1000000080; // @[BootROM.scala:50:22]
wire [63:0] rom_163 = 64'h200000099010000; // @[BootROM.scala:50:22]
wire [63:0] rom_165 = 64'h300000000636F73; // @[BootROM.scala:50:22]
wire [63:0] rom_166 = 64'h4000000; // @[BootROM.scala:50:22]
wire [63:0] rom_168 = 64'hF00000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_170 = 64'h1B00000020000000; // @[BootROM.scala:50:22]
wire [63:0] rom_42 = 64'h2C7261622D626375; // @[BootROM.scala:50:22]
wire [63:0] rom_171 = 64'h2C7261622D626375; // @[BootROM.scala:50:22]
wire [63:0] rom_43 = 64'h6472617970696863; // @[BootROM.scala:50:22]
wire [63:0] rom_172 = 64'h6472617970696863; // @[BootROM.scala:50:22]
wire [63:0] rom_173 = 64'h6D697300636F732D; // @[BootROM.scala:50:22]
wire [63:0] rom_174 = 64'h7375622D656C70; // @[BootROM.scala:50:22]
wire [63:0] rom_121 = 64'h3000000; // @[BootROM.scala:50:22]
wire [63:0] rom_175 = 64'h3000000; // @[BootROM.scala:50:22]
wire [63:0] rom_176 = 64'h1000000A1010000; // @[BootROM.scala:50:22]
wire [63:0] rom_177 = 64'h6464612D746F6F62; // @[BootROM.scala:50:22]
wire [63:0] rom_178 = 64'h6765722D73736572; // @[BootROM.scala:50:22]
wire [63:0] rom_179 = 64'h3030303140; // @[BootROM.scala:50:22]
wire [63:0] rom_181 = 64'h1000002E010000; // @[BootROM.scala:50:22]
wire [63:0] rom_186 = 64'h6F632D6568636163; // @[BootROM.scala:50:22]
wire [63:0] rom_188 = 64'h3030303031303240; // @[BootROM.scala:50:22]
wire [63:0] rom_190 = 64'h6500000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_191 = 64'h300000040000000; // @[BootROM.scala:50:22]
wire [63:0] rom_192 = 64'hB201000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_194 = 64'h7800000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_195 = 64'h300000000040000; // @[BootROM.scala:50:22]
wire [63:0] rom_196 = 64'h8500000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_197 = 64'h300000000000800; // @[BootROM.scala:50:22]
wire [63:0] rom_198 = 64'hBE01000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_199 = 64'h1D00000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_201 = 64'h756C636E692C6576; // @[BootROM.scala:50:22]
wire [63:0] rom_202 = 64'h6863616365766973; // @[BootROM.scala:50:22]
wire [63:0] rom_203 = 64'h6568636163003065; // @[BootROM.scala:50:22]
wire [63:0] rom_205 = 64'h1D01000008000000; // @[BootROM.scala:50:22]
wire [63:0] rom_193 = 64'h300000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_206 = 64'h300000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_208 = 64'h1022E010000; // @[BootROM.scala:50:22]
wire [63:0] rom_213 = 64'h7000000CC010000; // @[BootROM.scala:50:22]
wire [63:0] rom_215 = 64'h100000099010000; // @[BootROM.scala:50:22]
wire [63:0] rom_217 = 64'h6F6C635F73756263; // @[BootROM.scala:50:22]
wire [63:0] rom_224 = 64'h6F6C635F73756263; // @[BootROM.scala:50:22]
wire [63:0] rom_229 = 64'h6E696C6301000000; // @[BootROM.scala:50:22]
wire [63:0] rom_230 = 64'h3030303030324074; // @[BootROM.scala:50:22]
wire [63:0] rom_232 = 64'h1B0000000D000000; // @[BootROM.scala:50:22]
wire [63:0] rom_233 = 64'h6C632C7663736972; // @[BootROM.scala:50:22]
wire [63:0] rom_234 = 64'h30746E69; // @[BootROM.scala:50:22]
wire [63:0] rom_238 = 64'h300000007000000; // @[BootROM.scala:50:22]
wire [63:0] rom_240 = 64'h10000000002; // @[BootROM.scala:50:22]
wire [63:0] rom_244 = 64'h636F6C6301000000; // @[BootROM.scala:50:22]
wire [63:0] rom_245 = 64'h4072657461672D6B; // @[BootROM.scala:50:22]
wire [63:0] rom_246 = 64'h303030303031; // @[BootROM.scala:50:22]
wire [63:0] rom_248 = 64'h10002E010000; // @[BootROM.scala:50:22]
wire [63:0] rom_253 = 64'h6F632D6775626564; // @[BootROM.scala:50:22]
wire [63:0] rom_255 = 64'h300000000003040; // @[BootROM.scala:50:22]
wire [63:0] rom_256 = 64'h1B00000021000000; // @[BootROM.scala:50:22]
wire [63:0] rom_257 = 64'h642C657669666973; // @[BootROM.scala:50:22]
wire [63:0] rom_259 = 64'h642C766373697200; // @[BootROM.scala:50:22]
wire [63:0] rom_258 = 64'h3331302D67756265; // @[BootROM.scala:50:22]
wire [63:0] rom_260 = 64'h3331302D67756265; // @[BootROM.scala:50:22]
wire [63:0] rom_262 = 64'h1202000005000000; // @[BootROM.scala:50:22]
wire [63:0] rom_263 = 64'h6761746A; // @[BootROM.scala:50:22]
wire [63:0] rom_266 = 64'h3000000FFFF0000; // @[BootROM.scala:50:22]
wire [63:0] rom_268 = 64'h10000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_272 = 64'h6F72726501000000; // @[BootROM.scala:50:22]
wire [63:0] rom_273 = 64'h6563697665642D72; // @[BootROM.scala:50:22]
wire [63:0] rom_274 = 64'h3030303340; // @[BootROM.scala:50:22]
wire [63:0] rom_275 = 64'hE00000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_277 = 64'h726F7272652C6576; // @[BootROM.scala:50:22]
wire [63:0] rom_66 = 64'h300000000000030; // @[BootROM.scala:50:22]
wire [63:0] rom_231 = 64'h300000000000030; // @[BootROM.scala:50:22]
wire [63:0] rom_278 = 64'h300000000000030; // @[BootROM.scala:50:22]
wire [63:0] rom_280 = 64'h10000000300000; // @[BootROM.scala:50:22]
wire [63:0] rom_282 = 64'h6F6C635F73756266; // @[BootROM.scala:50:22]
wire [63:0] rom_289 = 64'h6F6C635F73756266; // @[BootROM.scala:50:22]
wire [63:0] rom_228 = 64'h2000000006B636F; // @[BootROM.scala:50:22]
wire [63:0] rom_293 = 64'h2000000006B636F; // @[BootROM.scala:50:22]
wire [63:0] rom_294 = 64'h65746E6901000000; // @[BootROM.scala:50:22]
wire [63:0] rom_297 = 64'h3030303030306340; // @[BootROM.scala:50:22]
wire [63:0] rom_299 = 64'h7301000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_302 = 64'h6C702C7663736972; // @[BootROM.scala:50:22]
wire [63:0] rom_303 = 64'h300000000306369; // @[BootROM.scala:50:22]
wire [63:0] rom_132 = 64'h8401000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_304 = 64'h8401000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_235 = 64'h1000000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_305 = 64'h1000000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_236 = 64'h4000000FE010000; // @[BootROM.scala:50:22]
wire [63:0] rom_265 = 64'h4000000FE010000; // @[BootROM.scala:50:22]
wire [63:0] rom_306 = 64'h4000000FE010000; // @[BootROM.scala:50:22]
wire [63:0] rom_307 = 64'h40000000B000000; // @[BootROM.scala:50:22]
wire [63:0] rom_308 = 64'h300000009000000; // @[BootROM.scala:50:22]
wire [63:0] rom_310 = 64'h40000000C; // @[BootROM.scala:50:22]
wire [63:0] rom_313 = 64'h3000000006C6F72; // @[BootROM.scala:50:22]
wire [63:0] rom_314 = 64'h1F02000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_316 = 64'h3202000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_319 = 64'h200000006000000; // @[BootROM.scala:50:22]
wire [63:0] rom_320 = 64'h7375626D01000000; // @[BootROM.scala:50:22]
wire [63:0] rom_327 = 64'h7375626DEB010000; // @[BootROM.scala:50:22]
wire [63:0] rom_219 = 64'hDE01000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_284 = 64'hDE01000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_335 = 64'hDE01000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_67 = 64'h5300000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_221 = 64'h5300000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_286 = 64'h5300000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_337 = 64'h5300000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_222 = 64'h30000000065CD1D; // @[BootROM.scala:50:22]
wire [63:0] rom_287 = 64'h30000000065CD1D; // @[BootROM.scala:50:22]
wire [63:0] rom_338 = 64'h30000000065CD1D; // @[BootROM.scala:50:22]
wire [63:0] rom_223 = 64'hEB0100000B000000; // @[BootROM.scala:50:22]
wire [63:0] rom_288 = 64'hEB0100000B000000; // @[BootROM.scala:50:22]
wire [63:0] rom_339 = 64'hEB0100000B000000; // @[BootROM.scala:50:22]
wire [63:0] rom_333 = 64'h6F6C635F73756270; // @[BootROM.scala:50:22]
wire [63:0] rom_340 = 64'h6F6C635F73756270; // @[BootROM.scala:50:22]
wire [63:0] rom_218 = 64'h300000000006B63; // @[BootROM.scala:50:22]
wire [63:0] rom_225 = 64'h300000000006B63; // @[BootROM.scala:50:22]
wire [63:0] rom_283 = 64'h300000000006B63; // @[BootROM.scala:50:22]
wire [63:0] rom_290 = 64'h300000000006B63; // @[BootROM.scala:50:22]
wire [63:0] rom_334 = 64'h300000000006B63; // @[BootROM.scala:50:22]
wire [63:0] rom_341 = 64'h300000000006B63; // @[BootROM.scala:50:22]
wire [63:0] rom_226 = 64'h1B0000000C000000; // @[BootROM.scala:50:22]
wire [63:0] rom_291 = 64'h1B0000000C000000; // @[BootROM.scala:50:22]
wire [63:0] rom_301 = 64'h1B0000000C000000; // @[BootROM.scala:50:22]
wire [63:0] rom_342 = 64'h1B0000000C000000; // @[BootROM.scala:50:22]
wire [63:0] rom_227 = 64'h6C632D6465786966; // @[BootROM.scala:50:22]
wire [63:0] rom_292 = 64'h6C632D6465786966; // @[BootROM.scala:50:22]
wire [63:0] rom_343 = 64'h6C632D6465786966; // @[BootROM.scala:50:22]
wire [63:0] rom_344 = 64'h3000000006B636F; // @[BootROM.scala:50:22]
wire [63:0] rom_318 = 64'h9901000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_345 = 64'h9901000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_346 = 64'h200000005000000; // @[BootROM.scala:50:22]
wire [63:0] rom_347 = 64'h406D6F7201000000; // @[BootROM.scala:50:22]
wire [63:0] rom_348 = 64'h3030303031; // @[BootROM.scala:50:22]
wire [63:0] rom_351 = 64'h306D6F722C6576; // @[BootROM.scala:50:22]
wire [63:0] rom_353 = 64'h1002E010000; // @[BootROM.scala:50:22]
wire [63:0] rom_354 = 64'h300000000000100; // @[BootROM.scala:50:22]
wire [63:0] rom_355 = 64'hA801000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_356 = 64'h2000000006D656D; // @[BootROM.scala:50:22]
wire [63:0] rom_357 = 64'h7375627301000000; // @[BootROM.scala:50:22]
wire [63:0] rom_323 = 64'hDE010000; // @[BootROM.scala:50:22]
wire [63:0] rom_360 = 64'hDE010000; // @[BootROM.scala:50:22]
wire [63:0] rom_325 = 64'h65CD1D53000000; // @[BootROM.scala:50:22]
wire [63:0] rom_362 = 64'h65CD1D53000000; // @[BootROM.scala:50:22]
wire [63:0] rom_97 = 64'hB00000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_326 = 64'hB00000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_363 = 64'hB00000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_364 = 64'h73756273EB010000; // @[BootROM.scala:50:22]
wire [63:0] rom_321 = 64'h6B636F6C635F; // @[BootROM.scala:50:22]
wire [63:0] rom_328 = 64'h6B636F6C635F; // @[BootROM.scala:50:22]
wire [63:0] rom_358 = 64'h6B636F6C635F; // @[BootROM.scala:50:22]
wire [63:0] rom_365 = 64'h6B636F6C635F; // @[BootROM.scala:50:22]
wire [63:0] rom_329 = 64'hC00000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_349 = 64'hC00000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_366 = 64'hC00000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_330 = 64'h657869661B000000; // @[BootROM.scala:50:22]
wire [63:0] rom_367 = 64'h657869661B000000; // @[BootROM.scala:50:22]
wire [63:0] rom_331 = 64'h6B636F6C632D64; // @[BootROM.scala:50:22]
wire [63:0] rom_368 = 64'h6B636F6C632D64; // @[BootROM.scala:50:22]
wire [63:0] rom_57 = 64'h100000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_136 = 64'h100000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_141 = 64'h100000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_154 = 64'h100000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_164 = 64'h100000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_185 = 64'h100000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_216 = 64'h100000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_252 = 64'h100000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_281 = 64'h100000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_332 = 64'h100000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_369 = 64'h100000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_370 = 64'h31406C6169726573; // @[BootROM.scala:50:22]
wire [63:0] rom_371 = 64'h30303030323030; // @[BootROM.scala:50:22]
wire [63:0] rom_32 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_34 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_59 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_61 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_63 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_73 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_75 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_77 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_79 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_81 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_83 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_85 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_87 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_89 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_91 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_93 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_95 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_100 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_102 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_119 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_126 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_133 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_152 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_162 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_212 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_214 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_237 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_322 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_324 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_359 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_361 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_372 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_373 = 64'h50000003D020000; // @[BootROM.scala:50:22]
wire [63:0] rom_374 = 64'hD00000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_200 = 64'h696669731B000000; // @[BootROM.scala:50:22]
wire [63:0] rom_276 = 64'h696669731B000000; // @[BootROM.scala:50:22]
wire [63:0] rom_350 = 64'h696669731B000000; // @[BootROM.scala:50:22]
wire [63:0] rom_375 = 64'h696669731B000000; // @[BootROM.scala:50:22]
wire [63:0] rom_376 = 64'h30747261752C6576; // @[BootROM.scala:50:22]
wire [63:0] rom_40 = 64'h300000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_68 = 64'h300000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_189 = 64'h300000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_204 = 64'h300000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_220 = 64'h300000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_261 = 64'h300000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_285 = 64'h300000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_298 = 64'h300000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_336 = 64'h300000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_377 = 64'h300000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_378 = 64'h4402000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_379 = 64'h300000006000000; // @[BootROM.scala:50:22]
wire [63:0] rom_380 = 64'h5502000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_167 = 64'h300000001000000; // @[BootROM.scala:50:22]
wire [63:0] rom_169 = 64'h300000001000000; // @[BootROM.scala:50:22]
wire [63:0] rom_300 = 64'h300000001000000; // @[BootROM.scala:50:22]
wire [63:0] rom_315 = 64'h300000001000000; // @[BootROM.scala:50:22]
wire [63:0] rom_317 = 64'h300000001000000; // @[BootROM.scala:50:22]
wire [63:0] rom_381 = 64'h300000001000000; // @[BootROM.scala:50:22]
wire [63:0] rom_147 = 64'h2E01000008000000; // @[BootROM.scala:50:22]
wire [63:0] rom_160 = 64'h2E01000008000000; // @[BootROM.scala:50:22]
wire [63:0] rom_239 = 64'h2E01000008000000; // @[BootROM.scala:50:22]
wire [63:0] rom_267 = 64'h2E01000008000000; // @[BootROM.scala:50:22]
wire [63:0] rom_279 = 64'h2E01000008000000; // @[BootROM.scala:50:22]
wire [63:0] rom_309 = 64'h2E01000008000000; // @[BootROM.scala:50:22]
wire [63:0] rom_382 = 64'h2E01000008000000; // @[BootROM.scala:50:22]
wire [63:0] rom_383 = 64'h10000000000210; // @[BootROM.scala:50:22]
wire [63:0] rom_242 = 64'h746E6F63A8010000; // @[BootROM.scala:50:22]
wire [63:0] rom_270 = 64'h746E6F63A8010000; // @[BootROM.scala:50:22]
wire [63:0] rom_312 = 64'h746E6F63A8010000; // @[BootROM.scala:50:22]
wire [63:0] rom_385 = 64'h746E6F63A8010000; // @[BootROM.scala:50:22]
wire [63:0] rom_243 = 64'h2000000006C6F72; // @[BootROM.scala:50:22]
wire [63:0] rom_271 = 64'h2000000006C6F72; // @[BootROM.scala:50:22]
wire [63:0] rom_386 = 64'h2000000006C6F72; // @[BootROM.scala:50:22]
wire [63:0] rom_387 = 64'h656C697401000000; // @[BootROM.scala:50:22]
wire [63:0] rom_388 = 64'h732D74657365722D; // @[BootROM.scala:50:22]
wire [63:0] rom_389 = 64'h3131407265747465; // @[BootROM.scala:50:22]
wire [63:0] rom_56 = 64'h30303030; // @[BootROM.scala:50:22]
wire [63:0] rom_390 = 64'h30303030; // @[BootROM.scala:50:22]
wire [63:0] rom_180 = 64'h800000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_207 = 64'h800000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_241 = 64'h800000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_247 = 64'h800000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_264 = 64'h800000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_269 = 64'h800000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_311 = 64'h800000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_352 = 64'h800000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_384 = 64'h800000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_391 = 64'h800000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_392 = 64'h11002E010000; // @[BootROM.scala:50:22]
wire [63:0] rom_182 = 64'h300000000100000; // @[BootROM.scala:50:22]
wire [63:0] rom_209 = 64'h300000000100000; // @[BootROM.scala:50:22]
wire [63:0] rom_249 = 64'h300000000100000; // @[BootROM.scala:50:22]
wire [63:0] rom_393 = 64'h300000000100000; // @[BootROM.scala:50:22]
wire [63:0] rom_183 = 64'hA801000008000000; // @[BootROM.scala:50:22]
wire [63:0] rom_210 = 64'hA801000008000000; // @[BootROM.scala:50:22]
wire [63:0] rom_250 = 64'hA801000008000000; // @[BootROM.scala:50:22]
wire [63:0] rom_394 = 64'hA801000008000000; // @[BootROM.scala:50:22]
wire [63:0] rom_184 = 64'h6C6F72746E6F63; // @[BootROM.scala:50:22]
wire [63:0] rom_211 = 64'h6C6F72746E6F63; // @[BootROM.scala:50:22]
wire [63:0] rom_251 = 64'h6C6F72746E6F63; // @[BootROM.scala:50:22]
wire [63:0] rom_395 = 64'h6C6F72746E6F63; // @[BootROM.scala:50:22]
wire [63:0] rom_135 = 64'h200000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_396 = 64'h200000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_397 = 64'h900000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_398 = 64'h7373657264646123; // @[BootROM.scala:50:22]
wire [63:0] rom_399 = 64'h2300736C6C65632D; // @[BootROM.scala:50:22]
wire [63:0] rom_400 = 64'h6C65632D657A6973; // @[BootROM.scala:50:22]
wire [63:0] rom_401 = 64'h61706D6F6300736C; // @[BootROM.scala:50:22]
wire [63:0] rom_402 = 64'h6F6D00656C626974; // @[BootROM.scala:50:22]
wire [63:0] rom_403 = 64'h69726573006C6564; // @[BootROM.scala:50:22]
wire [63:0] rom_404 = 64'h6F64747300306C61; // @[BootROM.scala:50:22]
wire [63:0] rom_405 = 64'h687461702D7475; // @[BootROM.scala:50:22]
wire [63:0] rom_406 = 64'h65736162656D6974; // @[BootROM.scala:50:22]
wire [63:0] rom_408 = 64'h6B636F6C63007963; // @[BootROM.scala:50:22]
wire [63:0] rom_407 = 64'h6E6575716572662D; // @[BootROM.scala:50:22]
wire [63:0] rom_409 = 64'h6E6575716572662D; // @[BootROM.scala:50:22]
wire [63:0] rom_410 = 64'h6361632D64007963; // @[BootROM.scala:50:22]
wire [63:0] rom_411 = 64'h6B636F6C622D6568; // @[BootROM.scala:50:22]
wire [63:0] rom_412 = 64'h2D6400657A69732D; // @[BootROM.scala:50:22]
wire [63:0] rom_413 = 64'h65732D6568636163; // @[BootROM.scala:50:22]
wire [63:0] rom_414 = 64'h6361632D64007374; // @[BootROM.scala:50:22]
wire [63:0] rom_415 = 64'h657A69732D6568; // @[BootROM.scala:50:22]
wire [63:0] rom_416 = 64'h65732D626C742D64; // @[BootROM.scala:50:22]
wire [63:0] rom_417 = 64'h626C742D64007374; // @[BootROM.scala:50:22]
wire [63:0] rom_418 = 64'h656400657A69732D; // @[BootROM.scala:50:22]
wire [63:0] rom_419 = 64'h7079745F65636976; // @[BootROM.scala:50:22]
wire [63:0] rom_420 = 64'h6177647261680065; // @[BootROM.scala:50:22]
wire [63:0] rom_421 = 64'h2D636578652D6572; // @[BootROM.scala:50:22]
wire [63:0] rom_422 = 64'h696F706B61657262; // @[BootROM.scala:50:22]
wire [63:0] rom_423 = 64'h746E756F632D746E; // @[BootROM.scala:50:22]
wire [63:0] rom_425 = 64'h732D6B636F6C622D; // @[BootROM.scala:50:22]
wire [63:0] rom_426 = 64'h61632D6900657A69; // @[BootROM.scala:50:22]
wire [63:0] rom_427 = 64'h737465732D656863; // @[BootROM.scala:50:22]
wire [63:0] rom_424 = 64'h65686361632D6900; // @[BootROM.scala:50:22]
wire [63:0] rom_428 = 64'h65686361632D6900; // @[BootROM.scala:50:22]
wire [63:0] rom_429 = 64'h2D6900657A69732D; // @[BootROM.scala:50:22]
wire [63:0] rom_430 = 64'h737465732D626C74; // @[BootROM.scala:50:22]
wire [63:0] rom_431 = 64'h732D626C742D6900; // @[BootROM.scala:50:22]
wire [63:0] rom_432 = 64'h2D756D6D00657A69; // @[BootROM.scala:50:22]
wire [63:0] rom_433 = 64'h78656E0065707974; // @[BootROM.scala:50:22]
wire [63:0] rom_434 = 64'h2D6C6576656C2D74; // @[BootROM.scala:50:22]
wire [63:0] rom_435 = 64'h6572006568636163; // @[BootROM.scala:50:22]
wire [63:0] rom_436 = 64'h2C76637369720067; // @[BootROM.scala:50:22]
wire [63:0] rom_437 = 64'h6373697200617369; // @[BootROM.scala:50:22]
wire [63:0] rom_438 = 64'h617267706D702C76; // @[BootROM.scala:50:22]
wire [63:0] rom_439 = 64'h79746972616C756E; // @[BootROM.scala:50:22]
wire [63:0] rom_440 = 64'h702C766373697200; // @[BootROM.scala:50:22]
wire [63:0] rom_441 = 64'h6E6F69676572706D; // @[BootROM.scala:50:22]
wire [63:0] rom_442 = 64'h7375746174730073; // @[BootROM.scala:50:22]
wire [63:0] rom_443 = 64'h6C70732D626C7400; // @[BootROM.scala:50:22]
wire [63:0] rom_444 = 64'h65746E6923007469; // @[BootROM.scala:50:22]
wire [63:0] rom_445 = 64'h65632D7470757272; // @[BootROM.scala:50:22]
wire [63:0] rom_446 = 64'h65746E6900736C6C; // @[BootROM.scala:50:22]
wire [63:0] rom_295 = 64'h6F632D7470757272; // @[BootROM.scala:50:22]
wire [63:0] rom_447 = 64'h6F632D7470757272; // @[BootROM.scala:50:22]
wire [63:0] rom_187 = 64'h72656C6C6F72746E; // @[BootROM.scala:50:22]
wire [63:0] rom_254 = 64'h72656C6C6F72746E; // @[BootROM.scala:50:22]
wire [63:0] rom_296 = 64'h72656C6C6F72746E; // @[BootROM.scala:50:22]
wire [63:0] rom_448 = 64'h72656C6C6F72746E; // @[BootROM.scala:50:22]
wire [63:0] rom_449 = 64'h656C646E61687000; // @[BootROM.scala:50:22]
wire [63:0] rom_450 = 64'h7365676E617200; // @[BootROM.scala:50:22]
wire [63:0] rom_451 = 64'h656D616E2D676572; // @[BootROM.scala:50:22]
wire [63:0] rom_452 = 64'h2D65686361630073; // @[BootROM.scala:50:22]
wire [63:0] rom_453 = 64'h6163006C6576656C; // @[BootROM.scala:50:22]
wire [63:0] rom_454 = 64'h66696E752D656863; // @[BootROM.scala:50:22]
wire [63:0] rom_455 = 64'h6966697300646569; // @[BootROM.scala:50:22]
wire [63:0] rom_456 = 64'h2D7268736D2C6576; // @[BootROM.scala:50:22]
wire [63:0] rom_457 = 64'h632300746E756F63; // @[BootROM.scala:50:22]
wire [63:0] rom_458 = 64'h6C65632D6B636F6C; // @[BootROM.scala:50:22]
wire [63:0] rom_459 = 64'h6B636F6C6300736C; // @[BootROM.scala:50:22]
wire [63:0] rom_460 = 64'h2D74757074756F2D; // @[BootROM.scala:50:22]
wire [63:0] rom_461 = 64'h6E690073656D616E; // @[BootROM.scala:50:22]
wire [63:0] rom_462 = 64'h7374707572726574; // @[BootROM.scala:50:22]
wire [63:0] rom_463 = 64'h65646E657478652D; // @[BootROM.scala:50:22]
wire [63:0] rom_464 = 64'h2D67756265640064; // @[BootROM.scala:50:22]
wire [63:0] rom_465 = 64'h7200686361747461; // @[BootROM.scala:50:22]
wire [63:0] rom_466 = 64'h78616D2C76637369; // @[BootROM.scala:50:22]
wire [63:0] rom_467 = 64'h7469726F6972702D; // @[BootROM.scala:50:22]
wire [63:0] rom_468 = 64'h2C76637369720079; // @[BootROM.scala:50:22]
wire [63:0] rom_469 = 64'h6F6C63007665646E; // @[BootROM.scala:50:22]
wire [63:0] rom_470 = 64'h65746E6900736B63; // @[BootROM.scala:50:22]
wire [63:0] rom_471 = 64'h61702D7470757272; // @[BootROM.scala:50:22]
wire [63:0] rom_472 = 64'h746E6900746E6572; // @[BootROM.scala:50:22]
wire [63:0] rom_473 = 64'h73747075727265; // @[BootROM.scala:50:22]
wire [63:0] rom_14 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_15 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_29 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_30 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_474 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_475 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_476 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_477 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_478 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_479 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_480 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_481 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_482 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_483 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_484 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_485 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_486 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_487 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_488 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_489 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_490 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_491 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_492 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_493 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_494 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_495 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_496 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_497 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_498 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_499 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_500 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_501 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_502 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_503 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_504 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_505 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_506 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_507 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_508 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_509 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_510 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_511 = 64'h0; // @[BootROM.scala:50:22]
wire auto_in_d_bits_sink = 1'h0; // @[BootROM.scala:41:9]
wire auto_in_d_bits_denied = 1'h0; // @[BootROM.scala:41:9]
wire auto_in_d_bits_corrupt = 1'h0; // @[BootROM.scala:41:9]
wire nodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:810:17]
wire nodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:810:17]
wire nodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:810:17]
wire [1:0] auto_in_d_bits_param = 2'h0; // @[BootROM.scala:41:9]
wire [1:0] nodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:810:17]
wire [2:0] auto_in_d_bits_opcode = 3'h1; // @[BootROM.scala:41:9]
wire nodeIn_a_ready; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_opcode = 3'h1; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_d_opcode = 3'h1; // @[Edges.scala:810:17]
wire nodeIn_a_valid = auto_in_a_valid_0; // @[BootROM.scala:41:9]
wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[BootROM.scala:41:9]
wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[BootROM.scala:41:9]
wire [1:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[BootROM.scala:41:9]
wire [10:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[BootROM.scala:41:9]
wire [16:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[BootROM.scala:41:9]
wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[BootROM.scala:41:9]
wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[BootROM.scala:41:9]
wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[BootROM.scala:41:9]
wire nodeIn_d_ready = auto_in_d_ready_0; // @[BootROM.scala:41:9]
wire nodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [10:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire auto_in_a_ready_0; // @[BootROM.scala:41:9]
wire [1:0] auto_in_d_bits_size_0; // @[BootROM.scala:41:9]
wire [10:0] auto_in_d_bits_source_0; // @[BootROM.scala:41:9]
wire [63:0] auto_in_d_bits_data_0; // @[BootROM.scala:41:9]
wire auto_in_d_valid_0; // @[BootROM.scala:41:9]
assign auto_in_a_ready_0 = nodeIn_a_ready; // @[BootROM.scala:41:9]
assign nodeIn_d_valid = nodeIn_a_valid; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_d_size = nodeIn_a_bits_size; // @[Edges.scala:810:17]
wire [10:0] nodeIn_d_bits_d_source = nodeIn_a_bits_source; // @[Edges.scala:810:17]
assign nodeIn_a_ready = nodeIn_d_ready; // @[MixedNode.scala:551:17]
assign auto_in_d_valid_0 = nodeIn_d_valid; // @[BootROM.scala:41:9]
assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[BootROM.scala:41:9]
assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[BootROM.scala:41:9]
wire [63:0] nodeIn_d_bits_d_data; // @[Edges.scala:810:17]
assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[BootROM.scala:41:9]
wire [8:0] index = nodeIn_a_bits_address[11:3]; // @[BootROM.scala:55:34]
wire [3:0] high = nodeIn_a_bits_address[15:12]; // @[BootROM.scala:56:64]
wire _nodeIn_d_bits_T = |high; // @[BootROM.scala:56:64, :57:53]
wire [63:0] _nodeIn_d_bits_T_1 = _nodeIn_d_bits_T ? 64'h0 : _GEN[index]; // @[BootROM.scala:55:34, :57:{47,53}]
assign nodeIn_d_bits_d_data = _nodeIn_d_bits_T_1; // @[Edges.scala:810:17]
assign nodeIn_d_bits_size = nodeIn_d_bits_d_size; // @[Edges.scala:810:17]
assign nodeIn_d_bits_source = nodeIn_d_bits_d_source; // @[Edges.scala:810:17]
assign nodeIn_d_bits_data = nodeIn_d_bits_d_data; // @[Edges.scala:810:17]
TLMonitor_51 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (nodeIn_d_bits_data) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
assign auto_in_a_ready = auto_in_a_ready_0; // @[BootROM.scala:41:9]
assign auto_in_d_valid = auto_in_d_valid_0; // @[BootROM.scala:41:9]
assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[BootROM.scala:41:9]
assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[BootROM.scala:41:9]
assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[BootROM.scala:41:9]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Nodes.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection}
case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args))
object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
{
def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo)
def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo)
def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle)
def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle)
def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString)
override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = {
val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge)))
monitor.io.in := bundle
}
override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters =
pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })
override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters =
pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })
}
trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut]
case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode
case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode
case class TLAdapterNode(
clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s },
managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLJunctionNode(
clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters],
managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])(
implicit valName: ValName)
extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode
object TLNameNode {
def apply(name: ValName) = TLIdentityNode()(name)
def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLIdentityNode = apply(Some(name))
}
case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)()
object TLTempNode {
def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp"))
}
case class TLNexusNode(
clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters,
managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)(
implicit valName: ValName)
extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode
abstract class TLCustomNode(implicit valName: ValName)
extends CustomNode(TLImp) with TLFormatNode
// Asynchronous crossings
trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters]
object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle]
{
def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle)
def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString)
override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLAsyncAdapterNode(
clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s },
managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode
case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode
object TLAsyncNameNode {
def apply(name: ValName) = TLAsyncIdentityNode()(name)
def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLAsyncIdentityNode = apply(Some(name))
}
case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLAsyncImp)(
dFn = { p => TLAsyncClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain
case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName)
extends MixedAdapterNode(TLAsyncImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) },
uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut]
// Rationally related crossings
trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters]
object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle]
{
def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle)
def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */)
override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLRationalAdapterNode(
clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s },
managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode
case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode
object TLRationalNameNode {
def apply(name: ValName) = TLRationalIdentityNode()(name)
def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLRationalIdentityNode = apply(Some(name))
}
case class TLRationalSourceNode()(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLRationalImp)(
dFn = { p => TLRationalClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain
case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName)
extends MixedAdapterNode(TLRationalImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut]
// Credited version of TileLink channels
trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters]
object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle]
{
def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle)
def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString)
override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLCreditedAdapterNode(
clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s },
managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode
case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode
object TLCreditedNameNode {
def apply(name: ValName) = TLCreditedIdentityNode()(name)
def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLCreditedIdentityNode = apply(Some(name))
}
case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLCreditedImp)(
dFn = { p => TLCreditedClientPortParameters(delay, p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain
case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLCreditedImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut]
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
File ProbePicker.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.{AddressSet, IdRange}
/* A ProbePicker is used to unify multiple cache banks into one logical cache */
class ProbePicker(implicit p: Parameters) extends LazyModule
{
val node = TLAdapterNode(
clientFn = { p =>
// The ProbePicker assembles multiple clients based on the assumption they are contiguous in the clients list
// This should be true for custers of xbar :=* BankBinder connections
def combine(next: TLMasterParameters, pair: (TLMasterParameters, Seq[TLMasterParameters])) = {
val (head, output) = pair
if (head.visibility.exists(x => next.visibility.exists(_.overlaps(x)))) {
(next, head +: output) // pair is not banked, push head without merging
} else {
def redact(x: TLMasterParameters) = x.v1copy(sourceId = IdRange(0,1), nodePath = Nil, visibility = Seq(AddressSet(0, ~0)))
require (redact(next) == redact(head), s"${redact(next)} != ${redact(head)}")
val merge = head.v1copy(
sourceId = IdRange(
head.sourceId.start min next.sourceId.start,
head.sourceId.end max next.sourceId.end),
visibility = AddressSet.unify(head.visibility ++ next.visibility))
(merge, output)
}
}
val myNil: Seq[TLMasterParameters] = Nil
val (head, output) = p.clients.init.foldRight((p.clients.last, myNil))(combine)
p.v1copy(clients = head +: output)
},
managerFn = { p => p })
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out <> in
// Based on address, adjust source to route to the correct bank
if (edgeIn.client.clients.size != edgeOut.client.clients.size) {
in.b.bits.source := Mux1H(
edgeOut.client.clients.map(_.sourceId contains out.b.bits.source),
edgeOut.client.clients.map { c =>
val banks = edgeIn.client.clients.filter(c.sourceId contains _.sourceId)
if (banks.size == 1) {
out.b.bits.source // allow sharing the value between single-bank cases
} else {
Mux1H(
banks.map(_.visibility.map(_ contains out.b.bits.address).reduce(_ || _)),
banks.map(_.sourceId.start.U))
}
}
)
}
}
}
}
object ProbePicker
{
def apply()(implicit p: Parameters): TLNode = {
val picker = LazyModule(new ProbePicker)
picker.node
}
}
| module ProbePicker( // @[ProbePicker.scala:42:9]
input clock, // @[ProbePicker.scala:42:9]
input reset, // @[ProbePicker.scala:42:9]
output auto_in_4_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_4_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_4_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_4_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_4_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_4_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [27:0] auto_in_4_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_4_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_4_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_4_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_4_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_4_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_4_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_4_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_4_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_in_4_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_in_4_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_4_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_4_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_4_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_in_3_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_3_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_3_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_3_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_3_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_3_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_3_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_3_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_3_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_3_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_3_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_3_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_3_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_3_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_in_3_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_in_3_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_3_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_3_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_in_2_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_2_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_2_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_2_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_2_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_2_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_2_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_2_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_2_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_2_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_2_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_2_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_2_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_2_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_in_2_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_in_2_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_2_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_2_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_in_1_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_1_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_1_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_1_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_1_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_1_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_1_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_1_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_1_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_1_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_1_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_in_1_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_in_1_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_1_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_in_0_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_0_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_0_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_0_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_0_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_0_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_0_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_0_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_0_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_0_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_0_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_in_0_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_in_0_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_0_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_4_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_4_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_4_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_4_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_4_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_4_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [27:0] auto_out_4_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_4_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_4_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_4_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_4_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_4_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_4_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_4_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_4_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_out_4_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_out_4_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_4_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_4_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_4_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_3_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_3_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_3_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_3_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_3_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_3_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_3_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_3_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_3_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_3_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_3_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_3_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_3_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_3_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_out_3_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_out_3_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_3_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_3_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_2_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_2_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_2_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_2_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_2_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_2_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_2_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_2_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_2_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_2_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_2_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_2_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_2_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_2_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_out_2_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_out_2_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_2_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_2_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_1_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_1_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_1_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_1_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_1_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_1_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_1_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_1_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_1_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_1_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_out_1_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_out_1_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_1_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_0_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_0_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_0_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_0_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_0_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_0_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_0_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_0_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_0_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_out_0_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_out_0_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_0_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_0_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
wire auto_in_4_a_valid_0 = auto_in_4_a_valid; // @[ProbePicker.scala:42:9]
wire [2:0] auto_in_4_a_bits_opcode_0 = auto_in_4_a_bits_opcode; // @[ProbePicker.scala:42:9]
wire [2:0] auto_in_4_a_bits_param_0 = auto_in_4_a_bits_param; // @[ProbePicker.scala:42:9]
wire [2:0] auto_in_4_a_bits_size_0 = auto_in_4_a_bits_size; // @[ProbePicker.scala:42:9]
wire [7:0] auto_in_4_a_bits_source_0 = auto_in_4_a_bits_source; // @[ProbePicker.scala:42:9]
wire [27:0] auto_in_4_a_bits_address_0 = auto_in_4_a_bits_address; // @[ProbePicker.scala:42:9]
wire [7:0] auto_in_4_a_bits_mask_0 = auto_in_4_a_bits_mask; // @[ProbePicker.scala:42:9]
wire [63:0] auto_in_4_a_bits_data_0 = auto_in_4_a_bits_data; // @[ProbePicker.scala:42:9]
wire auto_in_4_a_bits_corrupt_0 = auto_in_4_a_bits_corrupt; // @[ProbePicker.scala:42:9]
wire auto_in_4_d_ready_0 = auto_in_4_d_ready; // @[ProbePicker.scala:42:9]
wire auto_in_3_a_valid_0 = auto_in_3_a_valid; // @[ProbePicker.scala:42:9]
wire [2:0] auto_in_3_a_bits_opcode_0 = auto_in_3_a_bits_opcode; // @[ProbePicker.scala:42:9]
wire [2:0] auto_in_3_a_bits_param_0 = auto_in_3_a_bits_param; // @[ProbePicker.scala:42:9]
wire [2:0] auto_in_3_a_bits_size_0 = auto_in_3_a_bits_size; // @[ProbePicker.scala:42:9]
wire [7:0] auto_in_3_a_bits_source_0 = auto_in_3_a_bits_source; // @[ProbePicker.scala:42:9]
wire [31:0] auto_in_3_a_bits_address_0 = auto_in_3_a_bits_address; // @[ProbePicker.scala:42:9]
wire [7:0] auto_in_3_a_bits_mask_0 = auto_in_3_a_bits_mask; // @[ProbePicker.scala:42:9]
wire [63:0] auto_in_3_a_bits_data_0 = auto_in_3_a_bits_data; // @[ProbePicker.scala:42:9]
wire auto_in_3_a_bits_corrupt_0 = auto_in_3_a_bits_corrupt; // @[ProbePicker.scala:42:9]
wire auto_in_3_d_ready_0 = auto_in_3_d_ready; // @[ProbePicker.scala:42:9]
wire auto_in_2_a_valid_0 = auto_in_2_a_valid; // @[ProbePicker.scala:42:9]
wire [2:0] auto_in_2_a_bits_opcode_0 = auto_in_2_a_bits_opcode; // @[ProbePicker.scala:42:9]
wire [2:0] auto_in_2_a_bits_param_0 = auto_in_2_a_bits_param; // @[ProbePicker.scala:42:9]
wire [2:0] auto_in_2_a_bits_size_0 = auto_in_2_a_bits_size; // @[ProbePicker.scala:42:9]
wire [7:0] auto_in_2_a_bits_source_0 = auto_in_2_a_bits_source; // @[ProbePicker.scala:42:9]
wire [31:0] auto_in_2_a_bits_address_0 = auto_in_2_a_bits_address; // @[ProbePicker.scala:42:9]
wire [7:0] auto_in_2_a_bits_mask_0 = auto_in_2_a_bits_mask; // @[ProbePicker.scala:42:9]
wire [63:0] auto_in_2_a_bits_data_0 = auto_in_2_a_bits_data; // @[ProbePicker.scala:42:9]
wire auto_in_2_a_bits_corrupt_0 = auto_in_2_a_bits_corrupt; // @[ProbePicker.scala:42:9]
wire auto_in_2_d_ready_0 = auto_in_2_d_ready; // @[ProbePicker.scala:42:9]
wire auto_in_1_a_valid_0 = auto_in_1_a_valid; // @[ProbePicker.scala:42:9]
wire [2:0] auto_in_1_a_bits_opcode_0 = auto_in_1_a_bits_opcode; // @[ProbePicker.scala:42:9]
wire [2:0] auto_in_1_a_bits_param_0 = auto_in_1_a_bits_param; // @[ProbePicker.scala:42:9]
wire [2:0] auto_in_1_a_bits_size_0 = auto_in_1_a_bits_size; // @[ProbePicker.scala:42:9]
wire [7:0] auto_in_1_a_bits_source_0 = auto_in_1_a_bits_source; // @[ProbePicker.scala:42:9]
wire [31:0] auto_in_1_a_bits_address_0 = auto_in_1_a_bits_address; // @[ProbePicker.scala:42:9]
wire [7:0] auto_in_1_a_bits_mask_0 = auto_in_1_a_bits_mask; // @[ProbePicker.scala:42:9]
wire [63:0] auto_in_1_a_bits_data_0 = auto_in_1_a_bits_data; // @[ProbePicker.scala:42:9]
wire auto_in_1_a_bits_corrupt_0 = auto_in_1_a_bits_corrupt; // @[ProbePicker.scala:42:9]
wire auto_in_1_d_ready_0 = auto_in_1_d_ready; // @[ProbePicker.scala:42:9]
wire auto_in_0_a_valid_0 = auto_in_0_a_valid; // @[ProbePicker.scala:42:9]
wire [2:0] auto_in_0_a_bits_opcode_0 = auto_in_0_a_bits_opcode; // @[ProbePicker.scala:42:9]
wire [2:0] auto_in_0_a_bits_param_0 = auto_in_0_a_bits_param; // @[ProbePicker.scala:42:9]
wire [2:0] auto_in_0_a_bits_size_0 = auto_in_0_a_bits_size; // @[ProbePicker.scala:42:9]
wire [7:0] auto_in_0_a_bits_source_0 = auto_in_0_a_bits_source; // @[ProbePicker.scala:42:9]
wire [31:0] auto_in_0_a_bits_address_0 = auto_in_0_a_bits_address; // @[ProbePicker.scala:42:9]
wire [7:0] auto_in_0_a_bits_mask_0 = auto_in_0_a_bits_mask; // @[ProbePicker.scala:42:9]
wire [63:0] auto_in_0_a_bits_data_0 = auto_in_0_a_bits_data; // @[ProbePicker.scala:42:9]
wire auto_in_0_a_bits_corrupt_0 = auto_in_0_a_bits_corrupt; // @[ProbePicker.scala:42:9]
wire auto_in_0_d_ready_0 = auto_in_0_d_ready; // @[ProbePicker.scala:42:9]
wire auto_out_4_a_ready_0 = auto_out_4_a_ready; // @[ProbePicker.scala:42:9]
wire auto_out_4_d_valid_0 = auto_out_4_d_valid; // @[ProbePicker.scala:42:9]
wire [2:0] auto_out_4_d_bits_opcode_0 = auto_out_4_d_bits_opcode; // @[ProbePicker.scala:42:9]
wire [1:0] auto_out_4_d_bits_param_0 = auto_out_4_d_bits_param; // @[ProbePicker.scala:42:9]
wire [2:0] auto_out_4_d_bits_size_0 = auto_out_4_d_bits_size; // @[ProbePicker.scala:42:9]
wire [7:0] auto_out_4_d_bits_source_0 = auto_out_4_d_bits_source; // @[ProbePicker.scala:42:9]
wire auto_out_4_d_bits_sink_0 = auto_out_4_d_bits_sink; // @[ProbePicker.scala:42:9]
wire auto_out_4_d_bits_denied_0 = auto_out_4_d_bits_denied; // @[ProbePicker.scala:42:9]
wire [63:0] auto_out_4_d_bits_data_0 = auto_out_4_d_bits_data; // @[ProbePicker.scala:42:9]
wire auto_out_4_d_bits_corrupt_0 = auto_out_4_d_bits_corrupt; // @[ProbePicker.scala:42:9]
wire auto_out_3_a_ready_0 = auto_out_3_a_ready; // @[ProbePicker.scala:42:9]
wire auto_out_3_d_valid_0 = auto_out_3_d_valid; // @[ProbePicker.scala:42:9]
wire [2:0] auto_out_3_d_bits_opcode_0 = auto_out_3_d_bits_opcode; // @[ProbePicker.scala:42:9]
wire [2:0] auto_out_3_d_bits_size_0 = auto_out_3_d_bits_size; // @[ProbePicker.scala:42:9]
wire [7:0] auto_out_3_d_bits_source_0 = auto_out_3_d_bits_source; // @[ProbePicker.scala:42:9]
wire auto_out_3_d_bits_denied_0 = auto_out_3_d_bits_denied; // @[ProbePicker.scala:42:9]
wire [63:0] auto_out_3_d_bits_data_0 = auto_out_3_d_bits_data; // @[ProbePicker.scala:42:9]
wire auto_out_3_d_bits_corrupt_0 = auto_out_3_d_bits_corrupt; // @[ProbePicker.scala:42:9]
wire auto_out_2_a_ready_0 = auto_out_2_a_ready; // @[ProbePicker.scala:42:9]
wire auto_out_2_d_valid_0 = auto_out_2_d_valid; // @[ProbePicker.scala:42:9]
wire [2:0] auto_out_2_d_bits_opcode_0 = auto_out_2_d_bits_opcode; // @[ProbePicker.scala:42:9]
wire [2:0] auto_out_2_d_bits_size_0 = auto_out_2_d_bits_size; // @[ProbePicker.scala:42:9]
wire [7:0] auto_out_2_d_bits_source_0 = auto_out_2_d_bits_source; // @[ProbePicker.scala:42:9]
wire auto_out_2_d_bits_denied_0 = auto_out_2_d_bits_denied; // @[ProbePicker.scala:42:9]
wire [63:0] auto_out_2_d_bits_data_0 = auto_out_2_d_bits_data; // @[ProbePicker.scala:42:9]
wire auto_out_2_d_bits_corrupt_0 = auto_out_2_d_bits_corrupt; // @[ProbePicker.scala:42:9]
wire auto_out_1_a_ready_0 = auto_out_1_a_ready; // @[ProbePicker.scala:42:9]
wire auto_out_1_d_valid_0 = auto_out_1_d_valid; // @[ProbePicker.scala:42:9]
wire [2:0] auto_out_1_d_bits_opcode_0 = auto_out_1_d_bits_opcode; // @[ProbePicker.scala:42:9]
wire [2:0] auto_out_1_d_bits_size_0 = auto_out_1_d_bits_size; // @[ProbePicker.scala:42:9]
wire [7:0] auto_out_1_d_bits_source_0 = auto_out_1_d_bits_source; // @[ProbePicker.scala:42:9]
wire auto_out_1_d_bits_denied_0 = auto_out_1_d_bits_denied; // @[ProbePicker.scala:42:9]
wire [63:0] auto_out_1_d_bits_data_0 = auto_out_1_d_bits_data; // @[ProbePicker.scala:42:9]
wire auto_out_1_d_bits_corrupt_0 = auto_out_1_d_bits_corrupt; // @[ProbePicker.scala:42:9]
wire auto_out_0_a_ready_0 = auto_out_0_a_ready; // @[ProbePicker.scala:42:9]
wire auto_out_0_d_valid_0 = auto_out_0_d_valid; // @[ProbePicker.scala:42:9]
wire [2:0] auto_out_0_d_bits_opcode_0 = auto_out_0_d_bits_opcode; // @[ProbePicker.scala:42:9]
wire [2:0] auto_out_0_d_bits_size_0 = auto_out_0_d_bits_size; // @[ProbePicker.scala:42:9]
wire [7:0] auto_out_0_d_bits_source_0 = auto_out_0_d_bits_source; // @[ProbePicker.scala:42:9]
wire auto_out_0_d_bits_denied_0 = auto_out_0_d_bits_denied; // @[ProbePicker.scala:42:9]
wire [63:0] auto_out_0_d_bits_data_0 = auto_out_0_d_bits_data; // @[ProbePicker.scala:42:9]
wire auto_out_0_d_bits_corrupt_0 = auto_out_0_d_bits_corrupt; // @[ProbePicker.scala:42:9]
wire [7:0] _uncommonBits_T = 8'h0; // @[Parameters.scala:52:29]
wire [7:0] uncommonBits = 8'h0; // @[Parameters.scala:52:56]
wire [7:0] _uncommonBits_T_1 = 8'h0; // @[Parameters.scala:52:29]
wire [7:0] uncommonBits_1 = 8'h0; // @[Parameters.scala:52:56]
wire [7:0] _uncommonBits_T_2 = 8'h0; // @[Parameters.scala:52:29]
wire [7:0] uncommonBits_2 = 8'h0; // @[Parameters.scala:52:56]
wire [7:0] _uncommonBits_T_3 = 8'h0; // @[Parameters.scala:52:29]
wire [7:0] uncommonBits_3 = 8'h0; // @[Parameters.scala:52:56]
wire [7:0] _uncommonBits_T_4 = 8'h0; // @[Parameters.scala:52:29]
wire [7:0] uncommonBits_4 = 8'h0; // @[Parameters.scala:52:56]
wire auto_in_3_d_bits_sink = 1'h0; // @[ProbePicker.scala:42:9]
wire auto_in_2_d_bits_sink = 1'h0; // @[ProbePicker.scala:42:9]
wire auto_in_1_d_bits_sink = 1'h0; // @[ProbePicker.scala:42:9]
wire auto_in_0_d_bits_sink = 1'h0; // @[ProbePicker.scala:42:9]
wire auto_out_3_d_bits_sink = 1'h0; // @[ProbePicker.scala:42:9]
wire auto_out_2_d_bits_sink = 1'h0; // @[ProbePicker.scala:42:9]
wire auto_out_1_d_bits_sink = 1'h0; // @[ProbePicker.scala:42:9]
wire auto_out_0_d_bits_sink = 1'h0; // @[ProbePicker.scala:42:9]
wire nodeIn_d_bits_sink = 1'h0; // @[ProbePicker.scala:42:9]
wire nodeIn_1_d_bits_sink = 1'h0; // @[ProbePicker.scala:42:9]
wire nodeIn_2_d_bits_sink = 1'h0; // @[ProbePicker.scala:42:9]
wire nodeIn_3_d_bits_sink = 1'h0; // @[ProbePicker.scala:42:9]
wire nodeOut_d_bits_sink = 1'h0; // @[ProbePicker.scala:42:9]
wire x1_nodeOut_d_bits_sink = 1'h0; // @[ProbePicker.scala:42:9]
wire x1_nodeOut_1_d_bits_sink = 1'h0; // @[ProbePicker.scala:42:9]
wire x1_nodeOut_2_d_bits_sink = 1'h0; // @[ProbePicker.scala:42:9]
wire [1:0] auto_in_3_d_bits_param = 2'h0; // @[ProbePicker.scala:42:9]
wire [1:0] auto_in_2_d_bits_param = 2'h0; // @[ProbePicker.scala:42:9]
wire [1:0] auto_in_1_d_bits_param = 2'h0; // @[ProbePicker.scala:42:9]
wire [1:0] auto_in_0_d_bits_param = 2'h0; // @[ProbePicker.scala:42:9]
wire [1:0] auto_out_3_d_bits_param = 2'h0; // @[ProbePicker.scala:42:9]
wire [1:0] auto_out_2_d_bits_param = 2'h0; // @[ProbePicker.scala:42:9]
wire [1:0] auto_out_1_d_bits_param = 2'h0; // @[ProbePicker.scala:42:9]
wire [1:0] auto_out_0_d_bits_param = 2'h0; // @[ProbePicker.scala:42:9]
wire [1:0] nodeIn_d_bits_param = 2'h0; // @[ProbePicker.scala:42:9]
wire [1:0] nodeIn_1_d_bits_param = 2'h0; // @[ProbePicker.scala:42:9]
wire [1:0] nodeIn_2_d_bits_param = 2'h0; // @[ProbePicker.scala:42:9]
wire [1:0] nodeIn_3_d_bits_param = 2'h0; // @[ProbePicker.scala:42:9]
wire nodeIn_4_a_ready; // @[MixedNode.scala:551:17]
wire [1:0] nodeOut_d_bits_param = 2'h0; // @[ProbePicker.scala:42:9]
wire [1:0] x1_nodeOut_d_bits_param = 2'h0; // @[ProbePicker.scala:42:9]
wire [1:0] x1_nodeOut_1_d_bits_param = 2'h0; // @[ProbePicker.scala:42:9]
wire [1:0] x1_nodeOut_2_d_bits_param = 2'h0; // @[ProbePicker.scala:42:9]
wire nodeIn_4_a_valid = auto_in_4_a_valid_0; // @[ProbePicker.scala:42:9]
wire [2:0] nodeIn_4_a_bits_opcode = auto_in_4_a_bits_opcode_0; // @[ProbePicker.scala:42:9]
wire [2:0] nodeIn_4_a_bits_param = auto_in_4_a_bits_param_0; // @[ProbePicker.scala:42:9]
wire [2:0] nodeIn_4_a_bits_size = auto_in_4_a_bits_size_0; // @[ProbePicker.scala:42:9]
wire [7:0] nodeIn_4_a_bits_source = auto_in_4_a_bits_source_0; // @[ProbePicker.scala:42:9]
wire [27:0] nodeIn_4_a_bits_address = auto_in_4_a_bits_address_0; // @[ProbePicker.scala:42:9]
wire [7:0] nodeIn_4_a_bits_mask = auto_in_4_a_bits_mask_0; // @[ProbePicker.scala:42:9]
wire [63:0] nodeIn_4_a_bits_data = auto_in_4_a_bits_data_0; // @[ProbePicker.scala:42:9]
wire nodeIn_4_a_bits_corrupt = auto_in_4_a_bits_corrupt_0; // @[ProbePicker.scala:42:9]
wire nodeIn_4_d_ready = auto_in_4_d_ready_0; // @[ProbePicker.scala:42:9]
wire nodeIn_4_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_4_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_4_d_bits_param; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_4_d_bits_size; // @[MixedNode.scala:551:17]
wire [7:0] nodeIn_4_d_bits_source; // @[MixedNode.scala:551:17]
wire nodeIn_4_d_bits_sink; // @[MixedNode.scala:551:17]
wire nodeIn_4_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_4_d_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_4_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire nodeIn_3_a_ready; // @[MixedNode.scala:551:17]
wire nodeIn_3_a_valid = auto_in_3_a_valid_0; // @[ProbePicker.scala:42:9]
wire [2:0] nodeIn_3_a_bits_opcode = auto_in_3_a_bits_opcode_0; // @[ProbePicker.scala:42:9]
wire [2:0] nodeIn_3_a_bits_param = auto_in_3_a_bits_param_0; // @[ProbePicker.scala:42:9]
wire [2:0] nodeIn_3_a_bits_size = auto_in_3_a_bits_size_0; // @[ProbePicker.scala:42:9]
wire [7:0] nodeIn_3_a_bits_source = auto_in_3_a_bits_source_0; // @[ProbePicker.scala:42:9]
wire [31:0] nodeIn_3_a_bits_address = auto_in_3_a_bits_address_0; // @[ProbePicker.scala:42:9]
wire [7:0] nodeIn_3_a_bits_mask = auto_in_3_a_bits_mask_0; // @[ProbePicker.scala:42:9]
wire [63:0] nodeIn_3_a_bits_data = auto_in_3_a_bits_data_0; // @[ProbePicker.scala:42:9]
wire nodeIn_3_a_bits_corrupt = auto_in_3_a_bits_corrupt_0; // @[ProbePicker.scala:42:9]
wire nodeIn_3_d_ready = auto_in_3_d_ready_0; // @[ProbePicker.scala:42:9]
wire nodeIn_3_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_3_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_3_d_bits_size; // @[MixedNode.scala:551:17]
wire [7:0] nodeIn_3_d_bits_source; // @[MixedNode.scala:551:17]
wire nodeIn_3_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_3_d_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_3_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire nodeIn_2_a_ready; // @[MixedNode.scala:551:17]
wire nodeIn_2_a_valid = auto_in_2_a_valid_0; // @[ProbePicker.scala:42:9]
wire [2:0] nodeIn_2_a_bits_opcode = auto_in_2_a_bits_opcode_0; // @[ProbePicker.scala:42:9]
wire [2:0] nodeIn_2_a_bits_param = auto_in_2_a_bits_param_0; // @[ProbePicker.scala:42:9]
wire [2:0] nodeIn_2_a_bits_size = auto_in_2_a_bits_size_0; // @[ProbePicker.scala:42:9]
wire [7:0] nodeIn_2_a_bits_source = auto_in_2_a_bits_source_0; // @[ProbePicker.scala:42:9]
wire [31:0] nodeIn_2_a_bits_address = auto_in_2_a_bits_address_0; // @[ProbePicker.scala:42:9]
wire [7:0] nodeIn_2_a_bits_mask = auto_in_2_a_bits_mask_0; // @[ProbePicker.scala:42:9]
wire [63:0] nodeIn_2_a_bits_data = auto_in_2_a_bits_data_0; // @[ProbePicker.scala:42:9]
wire nodeIn_2_a_bits_corrupt = auto_in_2_a_bits_corrupt_0; // @[ProbePicker.scala:42:9]
wire nodeIn_2_d_ready = auto_in_2_d_ready_0; // @[ProbePicker.scala:42:9]
wire nodeIn_2_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_2_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_2_d_bits_size; // @[MixedNode.scala:551:17]
wire [7:0] nodeIn_2_d_bits_source; // @[MixedNode.scala:551:17]
wire nodeIn_2_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_2_d_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_2_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire nodeIn_1_a_ready; // @[MixedNode.scala:551:17]
wire nodeIn_1_a_valid = auto_in_1_a_valid_0; // @[ProbePicker.scala:42:9]
wire [2:0] nodeIn_1_a_bits_opcode = auto_in_1_a_bits_opcode_0; // @[ProbePicker.scala:42:9]
wire [2:0] nodeIn_1_a_bits_param = auto_in_1_a_bits_param_0; // @[ProbePicker.scala:42:9]
wire [2:0] nodeIn_1_a_bits_size = auto_in_1_a_bits_size_0; // @[ProbePicker.scala:42:9]
wire [7:0] nodeIn_1_a_bits_source = auto_in_1_a_bits_source_0; // @[ProbePicker.scala:42:9]
wire [31:0] nodeIn_1_a_bits_address = auto_in_1_a_bits_address_0; // @[ProbePicker.scala:42:9]
wire [7:0] nodeIn_1_a_bits_mask = auto_in_1_a_bits_mask_0; // @[ProbePicker.scala:42:9]
wire [63:0] nodeIn_1_a_bits_data = auto_in_1_a_bits_data_0; // @[ProbePicker.scala:42:9]
wire nodeIn_1_a_bits_corrupt = auto_in_1_a_bits_corrupt_0; // @[ProbePicker.scala:42:9]
wire nodeIn_1_d_ready = auto_in_1_d_ready_0; // @[ProbePicker.scala:42:9]
wire nodeIn_1_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_1_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_1_d_bits_size; // @[MixedNode.scala:551:17]
wire [7:0] nodeIn_1_d_bits_source; // @[MixedNode.scala:551:17]
wire nodeIn_1_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_1_d_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_1_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire nodeIn_a_ready; // @[MixedNode.scala:551:17]
wire nodeIn_a_valid = auto_in_0_a_valid_0; // @[ProbePicker.scala:42:9]
wire [2:0] nodeIn_a_bits_opcode = auto_in_0_a_bits_opcode_0; // @[ProbePicker.scala:42:9]
wire [2:0] nodeIn_a_bits_param = auto_in_0_a_bits_param_0; // @[ProbePicker.scala:42:9]
wire [2:0] nodeIn_a_bits_size = auto_in_0_a_bits_size_0; // @[ProbePicker.scala:42:9]
wire [7:0] nodeIn_a_bits_source = auto_in_0_a_bits_source_0; // @[ProbePicker.scala:42:9]
wire [31:0] nodeIn_a_bits_address = auto_in_0_a_bits_address_0; // @[ProbePicker.scala:42:9]
wire [7:0] nodeIn_a_bits_mask = auto_in_0_a_bits_mask_0; // @[ProbePicker.scala:42:9]
wire [63:0] nodeIn_a_bits_data = auto_in_0_a_bits_data_0; // @[ProbePicker.scala:42:9]
wire nodeIn_a_bits_corrupt = auto_in_0_a_bits_corrupt_0; // @[ProbePicker.scala:42:9]
wire nodeIn_d_ready = auto_in_0_d_ready_0; // @[ProbePicker.scala:42:9]
wire nodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [7:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire x1_nodeOut_3_a_ready = auto_out_4_a_ready_0; // @[ProbePicker.scala:42:9]
wire x1_nodeOut_3_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] x1_nodeOut_3_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] x1_nodeOut_3_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] x1_nodeOut_3_a_bits_size; // @[MixedNode.scala:542:17]
wire [7:0] x1_nodeOut_3_a_bits_source; // @[MixedNode.scala:542:17]
wire [27:0] x1_nodeOut_3_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] x1_nodeOut_3_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] x1_nodeOut_3_a_bits_data; // @[MixedNode.scala:542:17]
wire x1_nodeOut_3_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire x1_nodeOut_3_d_ready; // @[MixedNode.scala:542:17]
wire x1_nodeOut_3_d_valid = auto_out_4_d_valid_0; // @[ProbePicker.scala:42:9]
wire [2:0] x1_nodeOut_3_d_bits_opcode = auto_out_4_d_bits_opcode_0; // @[ProbePicker.scala:42:9]
wire [1:0] x1_nodeOut_3_d_bits_param = auto_out_4_d_bits_param_0; // @[ProbePicker.scala:42:9]
wire [2:0] x1_nodeOut_3_d_bits_size = auto_out_4_d_bits_size_0; // @[ProbePicker.scala:42:9]
wire [7:0] x1_nodeOut_3_d_bits_source = auto_out_4_d_bits_source_0; // @[ProbePicker.scala:42:9]
wire x1_nodeOut_3_d_bits_sink = auto_out_4_d_bits_sink_0; // @[ProbePicker.scala:42:9]
wire x1_nodeOut_3_d_bits_denied = auto_out_4_d_bits_denied_0; // @[ProbePicker.scala:42:9]
wire [63:0] x1_nodeOut_3_d_bits_data = auto_out_4_d_bits_data_0; // @[ProbePicker.scala:42:9]
wire x1_nodeOut_3_d_bits_corrupt = auto_out_4_d_bits_corrupt_0; // @[ProbePicker.scala:42:9]
wire x1_nodeOut_2_a_ready = auto_out_3_a_ready_0; // @[ProbePicker.scala:42:9]
wire x1_nodeOut_2_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] x1_nodeOut_2_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] x1_nodeOut_2_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] x1_nodeOut_2_a_bits_size; // @[MixedNode.scala:542:17]
wire [7:0] x1_nodeOut_2_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] x1_nodeOut_2_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] x1_nodeOut_2_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] x1_nodeOut_2_a_bits_data; // @[MixedNode.scala:542:17]
wire x1_nodeOut_2_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire x1_nodeOut_2_d_ready; // @[MixedNode.scala:542:17]
wire x1_nodeOut_2_d_valid = auto_out_3_d_valid_0; // @[ProbePicker.scala:42:9]
wire [2:0] x1_nodeOut_2_d_bits_opcode = auto_out_3_d_bits_opcode_0; // @[ProbePicker.scala:42:9]
wire [2:0] x1_nodeOut_2_d_bits_size = auto_out_3_d_bits_size_0; // @[ProbePicker.scala:42:9]
wire [7:0] x1_nodeOut_2_d_bits_source = auto_out_3_d_bits_source_0; // @[ProbePicker.scala:42:9]
wire x1_nodeOut_2_d_bits_denied = auto_out_3_d_bits_denied_0; // @[ProbePicker.scala:42:9]
wire [63:0] x1_nodeOut_2_d_bits_data = auto_out_3_d_bits_data_0; // @[ProbePicker.scala:42:9]
wire x1_nodeOut_2_d_bits_corrupt = auto_out_3_d_bits_corrupt_0; // @[ProbePicker.scala:42:9]
wire x1_nodeOut_1_a_ready = auto_out_2_a_ready_0; // @[ProbePicker.scala:42:9]
wire x1_nodeOut_1_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] x1_nodeOut_1_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] x1_nodeOut_1_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] x1_nodeOut_1_a_bits_size; // @[MixedNode.scala:542:17]
wire [7:0] x1_nodeOut_1_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] x1_nodeOut_1_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] x1_nodeOut_1_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] x1_nodeOut_1_a_bits_data; // @[MixedNode.scala:542:17]
wire x1_nodeOut_1_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire x1_nodeOut_1_d_ready; // @[MixedNode.scala:542:17]
wire x1_nodeOut_1_d_valid = auto_out_2_d_valid_0; // @[ProbePicker.scala:42:9]
wire [2:0] x1_nodeOut_1_d_bits_opcode = auto_out_2_d_bits_opcode_0; // @[ProbePicker.scala:42:9]
wire [2:0] x1_nodeOut_1_d_bits_size = auto_out_2_d_bits_size_0; // @[ProbePicker.scala:42:9]
wire [7:0] x1_nodeOut_1_d_bits_source = auto_out_2_d_bits_source_0; // @[ProbePicker.scala:42:9]
wire x1_nodeOut_1_d_bits_denied = auto_out_2_d_bits_denied_0; // @[ProbePicker.scala:42:9]
wire [63:0] x1_nodeOut_1_d_bits_data = auto_out_2_d_bits_data_0; // @[ProbePicker.scala:42:9]
wire x1_nodeOut_1_d_bits_corrupt = auto_out_2_d_bits_corrupt_0; // @[ProbePicker.scala:42:9]
wire x1_nodeOut_a_ready = auto_out_1_a_ready_0; // @[ProbePicker.scala:42:9]
wire x1_nodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] x1_nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] x1_nodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] x1_nodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [7:0] x1_nodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] x1_nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] x1_nodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] x1_nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire x1_nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire x1_nodeOut_d_ready; // @[MixedNode.scala:542:17]
wire x1_nodeOut_d_valid = auto_out_1_d_valid_0; // @[ProbePicker.scala:42:9]
wire [2:0] x1_nodeOut_d_bits_opcode = auto_out_1_d_bits_opcode_0; // @[ProbePicker.scala:42:9]
wire [2:0] x1_nodeOut_d_bits_size = auto_out_1_d_bits_size_0; // @[ProbePicker.scala:42:9]
wire [7:0] x1_nodeOut_d_bits_source = auto_out_1_d_bits_source_0; // @[ProbePicker.scala:42:9]
wire x1_nodeOut_d_bits_denied = auto_out_1_d_bits_denied_0; // @[ProbePicker.scala:42:9]
wire [63:0] x1_nodeOut_d_bits_data = auto_out_1_d_bits_data_0; // @[ProbePicker.scala:42:9]
wire x1_nodeOut_d_bits_corrupt = auto_out_1_d_bits_corrupt_0; // @[ProbePicker.scala:42:9]
wire nodeOut_a_ready = auto_out_0_a_ready_0; // @[ProbePicker.scala:42:9]
wire nodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire nodeOut_d_ready; // @[MixedNode.scala:542:17]
wire nodeOut_d_valid = auto_out_0_d_valid_0; // @[ProbePicker.scala:42:9]
wire [2:0] nodeOut_d_bits_opcode = auto_out_0_d_bits_opcode_0; // @[ProbePicker.scala:42:9]
wire [2:0] nodeOut_d_bits_size = auto_out_0_d_bits_size_0; // @[ProbePicker.scala:42:9]
wire [7:0] nodeOut_d_bits_source = auto_out_0_d_bits_source_0; // @[ProbePicker.scala:42:9]
wire nodeOut_d_bits_denied = auto_out_0_d_bits_denied_0; // @[ProbePicker.scala:42:9]
wire [63:0] nodeOut_d_bits_data = auto_out_0_d_bits_data_0; // @[ProbePicker.scala:42:9]
wire nodeOut_d_bits_corrupt = auto_out_0_d_bits_corrupt_0; // @[ProbePicker.scala:42:9]
wire auto_in_4_a_ready_0; // @[ProbePicker.scala:42:9]
wire [2:0] auto_in_4_d_bits_opcode_0; // @[ProbePicker.scala:42:9]
wire [1:0] auto_in_4_d_bits_param_0; // @[ProbePicker.scala:42:9]
wire [2:0] auto_in_4_d_bits_size_0; // @[ProbePicker.scala:42:9]
wire [7:0] auto_in_4_d_bits_source_0; // @[ProbePicker.scala:42:9]
wire auto_in_4_d_bits_sink_0; // @[ProbePicker.scala:42:9]
wire auto_in_4_d_bits_denied_0; // @[ProbePicker.scala:42:9]
wire [63:0] auto_in_4_d_bits_data_0; // @[ProbePicker.scala:42:9]
wire auto_in_4_d_bits_corrupt_0; // @[ProbePicker.scala:42:9]
wire auto_in_4_d_valid_0; // @[ProbePicker.scala:42:9]
wire auto_in_3_a_ready_0; // @[ProbePicker.scala:42:9]
wire [2:0] auto_in_3_d_bits_opcode_0; // @[ProbePicker.scala:42:9]
wire [2:0] auto_in_3_d_bits_size_0; // @[ProbePicker.scala:42:9]
wire [7:0] auto_in_3_d_bits_source_0; // @[ProbePicker.scala:42:9]
wire auto_in_3_d_bits_denied_0; // @[ProbePicker.scala:42:9]
wire [63:0] auto_in_3_d_bits_data_0; // @[ProbePicker.scala:42:9]
wire auto_in_3_d_bits_corrupt_0; // @[ProbePicker.scala:42:9]
wire auto_in_3_d_valid_0; // @[ProbePicker.scala:42:9]
wire auto_in_2_a_ready_0; // @[ProbePicker.scala:42:9]
wire [2:0] auto_in_2_d_bits_opcode_0; // @[ProbePicker.scala:42:9]
wire [2:0] auto_in_2_d_bits_size_0; // @[ProbePicker.scala:42:9]
wire [7:0] auto_in_2_d_bits_source_0; // @[ProbePicker.scala:42:9]
wire auto_in_2_d_bits_denied_0; // @[ProbePicker.scala:42:9]
wire [63:0] auto_in_2_d_bits_data_0; // @[ProbePicker.scala:42:9]
wire auto_in_2_d_bits_corrupt_0; // @[ProbePicker.scala:42:9]
wire auto_in_2_d_valid_0; // @[ProbePicker.scala:42:9]
wire auto_in_1_a_ready_0; // @[ProbePicker.scala:42:9]
wire [2:0] auto_in_1_d_bits_opcode_0; // @[ProbePicker.scala:42:9]
wire [2:0] auto_in_1_d_bits_size_0; // @[ProbePicker.scala:42:9]
wire [7:0] auto_in_1_d_bits_source_0; // @[ProbePicker.scala:42:9]
wire auto_in_1_d_bits_denied_0; // @[ProbePicker.scala:42:9]
wire [63:0] auto_in_1_d_bits_data_0; // @[ProbePicker.scala:42:9]
wire auto_in_1_d_bits_corrupt_0; // @[ProbePicker.scala:42:9]
wire auto_in_1_d_valid_0; // @[ProbePicker.scala:42:9]
wire auto_in_0_a_ready_0; // @[ProbePicker.scala:42:9]
wire [2:0] auto_in_0_d_bits_opcode_0; // @[ProbePicker.scala:42:9]
wire [2:0] auto_in_0_d_bits_size_0; // @[ProbePicker.scala:42:9]
wire [7:0] auto_in_0_d_bits_source_0; // @[ProbePicker.scala:42:9]
wire auto_in_0_d_bits_denied_0; // @[ProbePicker.scala:42:9]
wire [63:0] auto_in_0_d_bits_data_0; // @[ProbePicker.scala:42:9]
wire auto_in_0_d_bits_corrupt_0; // @[ProbePicker.scala:42:9]
wire auto_in_0_d_valid_0; // @[ProbePicker.scala:42:9]
wire [2:0] auto_out_4_a_bits_opcode_0; // @[ProbePicker.scala:42:9]
wire [2:0] auto_out_4_a_bits_param_0; // @[ProbePicker.scala:42:9]
wire [2:0] auto_out_4_a_bits_size_0; // @[ProbePicker.scala:42:9]
wire [7:0] auto_out_4_a_bits_source_0; // @[ProbePicker.scala:42:9]
wire [27:0] auto_out_4_a_bits_address_0; // @[ProbePicker.scala:42:9]
wire [7:0] auto_out_4_a_bits_mask_0; // @[ProbePicker.scala:42:9]
wire [63:0] auto_out_4_a_bits_data_0; // @[ProbePicker.scala:42:9]
wire auto_out_4_a_bits_corrupt_0; // @[ProbePicker.scala:42:9]
wire auto_out_4_a_valid_0; // @[ProbePicker.scala:42:9]
wire auto_out_4_d_ready_0; // @[ProbePicker.scala:42:9]
wire [2:0] auto_out_3_a_bits_opcode_0; // @[ProbePicker.scala:42:9]
wire [2:0] auto_out_3_a_bits_param_0; // @[ProbePicker.scala:42:9]
wire [2:0] auto_out_3_a_bits_size_0; // @[ProbePicker.scala:42:9]
wire [7:0] auto_out_3_a_bits_source_0; // @[ProbePicker.scala:42:9]
wire [31:0] auto_out_3_a_bits_address_0; // @[ProbePicker.scala:42:9]
wire [7:0] auto_out_3_a_bits_mask_0; // @[ProbePicker.scala:42:9]
wire [63:0] auto_out_3_a_bits_data_0; // @[ProbePicker.scala:42:9]
wire auto_out_3_a_bits_corrupt_0; // @[ProbePicker.scala:42:9]
wire auto_out_3_a_valid_0; // @[ProbePicker.scala:42:9]
wire auto_out_3_d_ready_0; // @[ProbePicker.scala:42:9]
wire [2:0] auto_out_2_a_bits_opcode_0; // @[ProbePicker.scala:42:9]
wire [2:0] auto_out_2_a_bits_param_0; // @[ProbePicker.scala:42:9]
wire [2:0] auto_out_2_a_bits_size_0; // @[ProbePicker.scala:42:9]
wire [7:0] auto_out_2_a_bits_source_0; // @[ProbePicker.scala:42:9]
wire [31:0] auto_out_2_a_bits_address_0; // @[ProbePicker.scala:42:9]
wire [7:0] auto_out_2_a_bits_mask_0; // @[ProbePicker.scala:42:9]
wire [63:0] auto_out_2_a_bits_data_0; // @[ProbePicker.scala:42:9]
wire auto_out_2_a_bits_corrupt_0; // @[ProbePicker.scala:42:9]
wire auto_out_2_a_valid_0; // @[ProbePicker.scala:42:9]
wire auto_out_2_d_ready_0; // @[ProbePicker.scala:42:9]
wire [2:0] auto_out_1_a_bits_opcode_0; // @[ProbePicker.scala:42:9]
wire [2:0] auto_out_1_a_bits_param_0; // @[ProbePicker.scala:42:9]
wire [2:0] auto_out_1_a_bits_size_0; // @[ProbePicker.scala:42:9]
wire [7:0] auto_out_1_a_bits_source_0; // @[ProbePicker.scala:42:9]
wire [31:0] auto_out_1_a_bits_address_0; // @[ProbePicker.scala:42:9]
wire [7:0] auto_out_1_a_bits_mask_0; // @[ProbePicker.scala:42:9]
wire [63:0] auto_out_1_a_bits_data_0; // @[ProbePicker.scala:42:9]
wire auto_out_1_a_bits_corrupt_0; // @[ProbePicker.scala:42:9]
wire auto_out_1_a_valid_0; // @[ProbePicker.scala:42:9]
wire auto_out_1_d_ready_0; // @[ProbePicker.scala:42:9]
wire [2:0] auto_out_0_a_bits_opcode_0; // @[ProbePicker.scala:42:9]
wire [2:0] auto_out_0_a_bits_param_0; // @[ProbePicker.scala:42:9]
wire [2:0] auto_out_0_a_bits_size_0; // @[ProbePicker.scala:42:9]
wire [7:0] auto_out_0_a_bits_source_0; // @[ProbePicker.scala:42:9]
wire [31:0] auto_out_0_a_bits_address_0; // @[ProbePicker.scala:42:9]
wire [7:0] auto_out_0_a_bits_mask_0; // @[ProbePicker.scala:42:9]
wire [63:0] auto_out_0_a_bits_data_0; // @[ProbePicker.scala:42:9]
wire auto_out_0_a_bits_corrupt_0; // @[ProbePicker.scala:42:9]
wire auto_out_0_a_valid_0; // @[ProbePicker.scala:42:9]
wire auto_out_0_d_ready_0; // @[ProbePicker.scala:42:9]
assign auto_in_0_a_ready_0 = nodeIn_a_ready; // @[ProbePicker.scala:42:9]
assign nodeOut_a_valid = nodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_a_bits_opcode = nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_a_bits_param = nodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_a_bits_size = nodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_a_bits_source = nodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_a_bits_address = nodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_a_bits_mask = nodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_a_bits_data = nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_a_bits_corrupt = nodeIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_d_ready = nodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign auto_in_0_d_valid_0 = nodeIn_d_valid; // @[ProbePicker.scala:42:9]
assign auto_in_0_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[ProbePicker.scala:42:9]
assign auto_in_0_d_bits_size_0 = nodeIn_d_bits_size; // @[ProbePicker.scala:42:9]
assign auto_in_0_d_bits_source_0 = nodeIn_d_bits_source; // @[ProbePicker.scala:42:9]
assign auto_in_0_d_bits_denied_0 = nodeIn_d_bits_denied; // @[ProbePicker.scala:42:9]
assign auto_in_0_d_bits_data_0 = nodeIn_d_bits_data; // @[ProbePicker.scala:42:9]
assign auto_in_0_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[ProbePicker.scala:42:9]
assign auto_in_1_a_ready_0 = nodeIn_1_a_ready; // @[ProbePicker.scala:42:9]
assign x1_nodeOut_a_valid = nodeIn_1_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign x1_nodeOut_a_bits_opcode = nodeIn_1_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign x1_nodeOut_a_bits_param = nodeIn_1_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign x1_nodeOut_a_bits_size = nodeIn_1_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign x1_nodeOut_a_bits_source = nodeIn_1_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign x1_nodeOut_a_bits_address = nodeIn_1_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign x1_nodeOut_a_bits_mask = nodeIn_1_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign x1_nodeOut_a_bits_data = nodeIn_1_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign x1_nodeOut_a_bits_corrupt = nodeIn_1_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign x1_nodeOut_d_ready = nodeIn_1_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign auto_in_1_d_valid_0 = nodeIn_1_d_valid; // @[ProbePicker.scala:42:9]
assign auto_in_1_d_bits_opcode_0 = nodeIn_1_d_bits_opcode; // @[ProbePicker.scala:42:9]
assign auto_in_1_d_bits_size_0 = nodeIn_1_d_bits_size; // @[ProbePicker.scala:42:9]
assign auto_in_1_d_bits_source_0 = nodeIn_1_d_bits_source; // @[ProbePicker.scala:42:9]
assign auto_in_1_d_bits_denied_0 = nodeIn_1_d_bits_denied; // @[ProbePicker.scala:42:9]
assign auto_in_1_d_bits_data_0 = nodeIn_1_d_bits_data; // @[ProbePicker.scala:42:9]
assign auto_in_1_d_bits_corrupt_0 = nodeIn_1_d_bits_corrupt; // @[ProbePicker.scala:42:9]
assign auto_in_2_a_ready_0 = nodeIn_2_a_ready; // @[ProbePicker.scala:42:9]
assign x1_nodeOut_1_a_valid = nodeIn_2_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign x1_nodeOut_1_a_bits_opcode = nodeIn_2_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign x1_nodeOut_1_a_bits_param = nodeIn_2_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign x1_nodeOut_1_a_bits_size = nodeIn_2_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign x1_nodeOut_1_a_bits_source = nodeIn_2_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign x1_nodeOut_1_a_bits_address = nodeIn_2_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign x1_nodeOut_1_a_bits_mask = nodeIn_2_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign x1_nodeOut_1_a_bits_data = nodeIn_2_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign x1_nodeOut_1_a_bits_corrupt = nodeIn_2_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign x1_nodeOut_1_d_ready = nodeIn_2_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign auto_in_2_d_valid_0 = nodeIn_2_d_valid; // @[ProbePicker.scala:42:9]
assign auto_in_2_d_bits_opcode_0 = nodeIn_2_d_bits_opcode; // @[ProbePicker.scala:42:9]
assign auto_in_2_d_bits_size_0 = nodeIn_2_d_bits_size; // @[ProbePicker.scala:42:9]
assign auto_in_2_d_bits_source_0 = nodeIn_2_d_bits_source; // @[ProbePicker.scala:42:9]
assign auto_in_2_d_bits_denied_0 = nodeIn_2_d_bits_denied; // @[ProbePicker.scala:42:9]
assign auto_in_2_d_bits_data_0 = nodeIn_2_d_bits_data; // @[ProbePicker.scala:42:9]
assign auto_in_2_d_bits_corrupt_0 = nodeIn_2_d_bits_corrupt; // @[ProbePicker.scala:42:9]
assign auto_in_3_a_ready_0 = nodeIn_3_a_ready; // @[ProbePicker.scala:42:9]
assign x1_nodeOut_2_a_valid = nodeIn_3_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign x1_nodeOut_2_a_bits_opcode = nodeIn_3_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign x1_nodeOut_2_a_bits_param = nodeIn_3_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign x1_nodeOut_2_a_bits_size = nodeIn_3_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign x1_nodeOut_2_a_bits_source = nodeIn_3_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign x1_nodeOut_2_a_bits_address = nodeIn_3_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign x1_nodeOut_2_a_bits_mask = nodeIn_3_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign x1_nodeOut_2_a_bits_data = nodeIn_3_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign x1_nodeOut_2_a_bits_corrupt = nodeIn_3_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign x1_nodeOut_2_d_ready = nodeIn_3_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign auto_in_3_d_valid_0 = nodeIn_3_d_valid; // @[ProbePicker.scala:42:9]
assign auto_in_3_d_bits_opcode_0 = nodeIn_3_d_bits_opcode; // @[ProbePicker.scala:42:9]
assign auto_in_3_d_bits_size_0 = nodeIn_3_d_bits_size; // @[ProbePicker.scala:42:9]
assign auto_in_3_d_bits_source_0 = nodeIn_3_d_bits_source; // @[ProbePicker.scala:42:9]
assign auto_in_3_d_bits_denied_0 = nodeIn_3_d_bits_denied; // @[ProbePicker.scala:42:9]
assign auto_in_3_d_bits_data_0 = nodeIn_3_d_bits_data; // @[ProbePicker.scala:42:9]
assign auto_in_3_d_bits_corrupt_0 = nodeIn_3_d_bits_corrupt; // @[ProbePicker.scala:42:9]
assign auto_in_4_a_ready_0 = nodeIn_4_a_ready; // @[ProbePicker.scala:42:9]
assign x1_nodeOut_3_a_valid = nodeIn_4_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign x1_nodeOut_3_a_bits_opcode = nodeIn_4_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign x1_nodeOut_3_a_bits_param = nodeIn_4_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign x1_nodeOut_3_a_bits_size = nodeIn_4_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign x1_nodeOut_3_a_bits_source = nodeIn_4_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign x1_nodeOut_3_a_bits_address = nodeIn_4_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign x1_nodeOut_3_a_bits_mask = nodeIn_4_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign x1_nodeOut_3_a_bits_data = nodeIn_4_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign x1_nodeOut_3_a_bits_corrupt = nodeIn_4_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign x1_nodeOut_3_d_ready = nodeIn_4_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign auto_in_4_d_valid_0 = nodeIn_4_d_valid; // @[ProbePicker.scala:42:9]
assign auto_in_4_d_bits_opcode_0 = nodeIn_4_d_bits_opcode; // @[ProbePicker.scala:42:9]
assign auto_in_4_d_bits_param_0 = nodeIn_4_d_bits_param; // @[ProbePicker.scala:42:9]
assign auto_in_4_d_bits_size_0 = nodeIn_4_d_bits_size; // @[ProbePicker.scala:42:9]
assign auto_in_4_d_bits_source_0 = nodeIn_4_d_bits_source; // @[ProbePicker.scala:42:9]
assign auto_in_4_d_bits_sink_0 = nodeIn_4_d_bits_sink; // @[ProbePicker.scala:42:9]
assign auto_in_4_d_bits_denied_0 = nodeIn_4_d_bits_denied; // @[ProbePicker.scala:42:9]
assign auto_in_4_d_bits_data_0 = nodeIn_4_d_bits_data; // @[ProbePicker.scala:42:9]
assign auto_in_4_d_bits_corrupt_0 = nodeIn_4_d_bits_corrupt; // @[ProbePicker.scala:42:9]
assign nodeIn_a_ready = nodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign auto_out_0_a_valid_0 = nodeOut_a_valid; // @[ProbePicker.scala:42:9]
assign auto_out_0_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[ProbePicker.scala:42:9]
assign auto_out_0_a_bits_param_0 = nodeOut_a_bits_param; // @[ProbePicker.scala:42:9]
assign auto_out_0_a_bits_size_0 = nodeOut_a_bits_size; // @[ProbePicker.scala:42:9]
assign auto_out_0_a_bits_source_0 = nodeOut_a_bits_source; // @[ProbePicker.scala:42:9]
assign auto_out_0_a_bits_address_0 = nodeOut_a_bits_address; // @[ProbePicker.scala:42:9]
assign auto_out_0_a_bits_mask_0 = nodeOut_a_bits_mask; // @[ProbePicker.scala:42:9]
assign auto_out_0_a_bits_data_0 = nodeOut_a_bits_data; // @[ProbePicker.scala:42:9]
assign auto_out_0_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[ProbePicker.scala:42:9]
assign auto_out_0_d_ready_0 = nodeOut_d_ready; // @[ProbePicker.scala:42:9]
assign nodeIn_d_valid = nodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_d_bits_opcode = nodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_d_bits_size = nodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_d_bits_source = nodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_d_bits_denied = nodeOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_d_bits_data = nodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_d_bits_corrupt = nodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_1_a_ready = x1_nodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign auto_out_1_a_valid_0 = x1_nodeOut_a_valid; // @[ProbePicker.scala:42:9]
assign auto_out_1_a_bits_opcode_0 = x1_nodeOut_a_bits_opcode; // @[ProbePicker.scala:42:9]
assign auto_out_1_a_bits_param_0 = x1_nodeOut_a_bits_param; // @[ProbePicker.scala:42:9]
assign auto_out_1_a_bits_size_0 = x1_nodeOut_a_bits_size; // @[ProbePicker.scala:42:9]
assign auto_out_1_a_bits_source_0 = x1_nodeOut_a_bits_source; // @[ProbePicker.scala:42:9]
assign auto_out_1_a_bits_address_0 = x1_nodeOut_a_bits_address; // @[ProbePicker.scala:42:9]
assign auto_out_1_a_bits_mask_0 = x1_nodeOut_a_bits_mask; // @[ProbePicker.scala:42:9]
assign auto_out_1_a_bits_data_0 = x1_nodeOut_a_bits_data; // @[ProbePicker.scala:42:9]
assign auto_out_1_a_bits_corrupt_0 = x1_nodeOut_a_bits_corrupt; // @[ProbePicker.scala:42:9]
assign auto_out_1_d_ready_0 = x1_nodeOut_d_ready; // @[ProbePicker.scala:42:9]
assign nodeIn_1_d_valid = x1_nodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_1_d_bits_opcode = x1_nodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_1_d_bits_size = x1_nodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_1_d_bits_source = x1_nodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_1_d_bits_denied = x1_nodeOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_1_d_bits_data = x1_nodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_1_d_bits_corrupt = x1_nodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_2_a_ready = x1_nodeOut_1_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign auto_out_2_a_valid_0 = x1_nodeOut_1_a_valid; // @[ProbePicker.scala:42:9]
assign auto_out_2_a_bits_opcode_0 = x1_nodeOut_1_a_bits_opcode; // @[ProbePicker.scala:42:9]
assign auto_out_2_a_bits_param_0 = x1_nodeOut_1_a_bits_param; // @[ProbePicker.scala:42:9]
assign auto_out_2_a_bits_size_0 = x1_nodeOut_1_a_bits_size; // @[ProbePicker.scala:42:9]
assign auto_out_2_a_bits_source_0 = x1_nodeOut_1_a_bits_source; // @[ProbePicker.scala:42:9]
assign auto_out_2_a_bits_address_0 = x1_nodeOut_1_a_bits_address; // @[ProbePicker.scala:42:9]
assign auto_out_2_a_bits_mask_0 = x1_nodeOut_1_a_bits_mask; // @[ProbePicker.scala:42:9]
assign auto_out_2_a_bits_data_0 = x1_nodeOut_1_a_bits_data; // @[ProbePicker.scala:42:9]
assign auto_out_2_a_bits_corrupt_0 = x1_nodeOut_1_a_bits_corrupt; // @[ProbePicker.scala:42:9]
assign auto_out_2_d_ready_0 = x1_nodeOut_1_d_ready; // @[ProbePicker.scala:42:9]
assign nodeIn_2_d_valid = x1_nodeOut_1_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_2_d_bits_opcode = x1_nodeOut_1_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_2_d_bits_size = x1_nodeOut_1_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_2_d_bits_source = x1_nodeOut_1_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_2_d_bits_denied = x1_nodeOut_1_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_2_d_bits_data = x1_nodeOut_1_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_2_d_bits_corrupt = x1_nodeOut_1_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_3_a_ready = x1_nodeOut_2_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign auto_out_3_a_valid_0 = x1_nodeOut_2_a_valid; // @[ProbePicker.scala:42:9]
assign auto_out_3_a_bits_opcode_0 = x1_nodeOut_2_a_bits_opcode; // @[ProbePicker.scala:42:9]
assign auto_out_3_a_bits_param_0 = x1_nodeOut_2_a_bits_param; // @[ProbePicker.scala:42:9]
assign auto_out_3_a_bits_size_0 = x1_nodeOut_2_a_bits_size; // @[ProbePicker.scala:42:9]
assign auto_out_3_a_bits_source_0 = x1_nodeOut_2_a_bits_source; // @[ProbePicker.scala:42:9]
assign auto_out_3_a_bits_address_0 = x1_nodeOut_2_a_bits_address; // @[ProbePicker.scala:42:9]
assign auto_out_3_a_bits_mask_0 = x1_nodeOut_2_a_bits_mask; // @[ProbePicker.scala:42:9]
assign auto_out_3_a_bits_data_0 = x1_nodeOut_2_a_bits_data; // @[ProbePicker.scala:42:9]
assign auto_out_3_a_bits_corrupt_0 = x1_nodeOut_2_a_bits_corrupt; // @[ProbePicker.scala:42:9]
assign auto_out_3_d_ready_0 = x1_nodeOut_2_d_ready; // @[ProbePicker.scala:42:9]
assign nodeIn_3_d_valid = x1_nodeOut_2_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_3_d_bits_opcode = x1_nodeOut_2_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_3_d_bits_size = x1_nodeOut_2_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_3_d_bits_source = x1_nodeOut_2_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_3_d_bits_denied = x1_nodeOut_2_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_3_d_bits_data = x1_nodeOut_2_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_3_d_bits_corrupt = x1_nodeOut_2_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_4_a_ready = x1_nodeOut_3_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign auto_out_4_a_valid_0 = x1_nodeOut_3_a_valid; // @[ProbePicker.scala:42:9]
assign auto_out_4_a_bits_opcode_0 = x1_nodeOut_3_a_bits_opcode; // @[ProbePicker.scala:42:9]
assign auto_out_4_a_bits_param_0 = x1_nodeOut_3_a_bits_param; // @[ProbePicker.scala:42:9]
assign auto_out_4_a_bits_size_0 = x1_nodeOut_3_a_bits_size; // @[ProbePicker.scala:42:9]
assign auto_out_4_a_bits_source_0 = x1_nodeOut_3_a_bits_source; // @[ProbePicker.scala:42:9]
assign auto_out_4_a_bits_address_0 = x1_nodeOut_3_a_bits_address; // @[ProbePicker.scala:42:9]
assign auto_out_4_a_bits_mask_0 = x1_nodeOut_3_a_bits_mask; // @[ProbePicker.scala:42:9]
assign auto_out_4_a_bits_data_0 = x1_nodeOut_3_a_bits_data; // @[ProbePicker.scala:42:9]
assign auto_out_4_a_bits_corrupt_0 = x1_nodeOut_3_a_bits_corrupt; // @[ProbePicker.scala:42:9]
assign auto_out_4_d_ready_0 = x1_nodeOut_3_d_ready; // @[ProbePicker.scala:42:9]
assign nodeIn_4_d_valid = x1_nodeOut_3_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_4_d_bits_opcode = x1_nodeOut_3_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_4_d_bits_param = x1_nodeOut_3_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_4_d_bits_size = x1_nodeOut_3_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_4_d_bits_source = x1_nodeOut_3_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_4_d_bits_sink = x1_nodeOut_3_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_4_d_bits_denied = x1_nodeOut_3_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_4_d_bits_data = x1_nodeOut_3_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_4_d_bits_corrupt = x1_nodeOut_3_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
TLMonitor_39 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
TLMonitor_40 monitor_1 ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (nodeIn_1_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (nodeIn_1_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (nodeIn_1_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (nodeIn_1_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (nodeIn_1_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (nodeIn_1_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (nodeIn_1_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (nodeIn_1_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (nodeIn_1_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_a_bits_corrupt (nodeIn_1_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_d_ready (nodeIn_1_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (nodeIn_1_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (nodeIn_1_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (nodeIn_1_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (nodeIn_1_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_denied (nodeIn_1_d_bits_denied), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (nodeIn_1_d_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_bits_corrupt (nodeIn_1_d_bits_corrupt) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
TLMonitor_41 monitor_2 ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (nodeIn_2_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (nodeIn_2_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (nodeIn_2_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (nodeIn_2_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (nodeIn_2_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (nodeIn_2_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (nodeIn_2_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (nodeIn_2_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (nodeIn_2_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_a_bits_corrupt (nodeIn_2_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_d_ready (nodeIn_2_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (nodeIn_2_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (nodeIn_2_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (nodeIn_2_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (nodeIn_2_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_denied (nodeIn_2_d_bits_denied), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (nodeIn_2_d_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_bits_corrupt (nodeIn_2_d_bits_corrupt) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
TLMonitor_42 monitor_3 ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (nodeIn_3_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (nodeIn_3_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (nodeIn_3_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (nodeIn_3_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (nodeIn_3_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (nodeIn_3_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (nodeIn_3_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (nodeIn_3_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (nodeIn_3_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_a_bits_corrupt (nodeIn_3_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_d_ready (nodeIn_3_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (nodeIn_3_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (nodeIn_3_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (nodeIn_3_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (nodeIn_3_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_denied (nodeIn_3_d_bits_denied), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (nodeIn_3_d_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_bits_corrupt (nodeIn_3_d_bits_corrupt) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
TLMonitor_43 monitor_4 ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (nodeIn_4_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (nodeIn_4_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (nodeIn_4_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (nodeIn_4_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (nodeIn_4_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (nodeIn_4_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (nodeIn_4_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (nodeIn_4_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (nodeIn_4_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_a_bits_corrupt (nodeIn_4_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_d_ready (nodeIn_4_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (nodeIn_4_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (nodeIn_4_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_param (nodeIn_4_d_bits_param), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (nodeIn_4_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (nodeIn_4_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_sink (nodeIn_4_d_bits_sink), // @[MixedNode.scala:551:17]
.io_in_d_bits_denied (nodeIn_4_d_bits_denied), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (nodeIn_4_d_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_bits_corrupt (nodeIn_4_d_bits_corrupt) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
assign auto_in_4_a_ready = auto_in_4_a_ready_0; // @[ProbePicker.scala:42:9]
assign auto_in_4_d_valid = auto_in_4_d_valid_0; // @[ProbePicker.scala:42:9]
assign auto_in_4_d_bits_opcode = auto_in_4_d_bits_opcode_0; // @[ProbePicker.scala:42:9]
assign auto_in_4_d_bits_param = auto_in_4_d_bits_param_0; // @[ProbePicker.scala:42:9]
assign auto_in_4_d_bits_size = auto_in_4_d_bits_size_0; // @[ProbePicker.scala:42:9]
assign auto_in_4_d_bits_source = auto_in_4_d_bits_source_0; // @[ProbePicker.scala:42:9]
assign auto_in_4_d_bits_sink = auto_in_4_d_bits_sink_0; // @[ProbePicker.scala:42:9]
assign auto_in_4_d_bits_denied = auto_in_4_d_bits_denied_0; // @[ProbePicker.scala:42:9]
assign auto_in_4_d_bits_data = auto_in_4_d_bits_data_0; // @[ProbePicker.scala:42:9]
assign auto_in_4_d_bits_corrupt = auto_in_4_d_bits_corrupt_0; // @[ProbePicker.scala:42:9]
assign auto_in_3_a_ready = auto_in_3_a_ready_0; // @[ProbePicker.scala:42:9]
assign auto_in_3_d_valid = auto_in_3_d_valid_0; // @[ProbePicker.scala:42:9]
assign auto_in_3_d_bits_opcode = auto_in_3_d_bits_opcode_0; // @[ProbePicker.scala:42:9]
assign auto_in_3_d_bits_size = auto_in_3_d_bits_size_0; // @[ProbePicker.scala:42:9]
assign auto_in_3_d_bits_source = auto_in_3_d_bits_source_0; // @[ProbePicker.scala:42:9]
assign auto_in_3_d_bits_denied = auto_in_3_d_bits_denied_0; // @[ProbePicker.scala:42:9]
assign auto_in_3_d_bits_data = auto_in_3_d_bits_data_0; // @[ProbePicker.scala:42:9]
assign auto_in_3_d_bits_corrupt = auto_in_3_d_bits_corrupt_0; // @[ProbePicker.scala:42:9]
assign auto_in_2_a_ready = auto_in_2_a_ready_0; // @[ProbePicker.scala:42:9]
assign auto_in_2_d_valid = auto_in_2_d_valid_0; // @[ProbePicker.scala:42:9]
assign auto_in_2_d_bits_opcode = auto_in_2_d_bits_opcode_0; // @[ProbePicker.scala:42:9]
assign auto_in_2_d_bits_size = auto_in_2_d_bits_size_0; // @[ProbePicker.scala:42:9]
assign auto_in_2_d_bits_source = auto_in_2_d_bits_source_0; // @[ProbePicker.scala:42:9]
assign auto_in_2_d_bits_denied = auto_in_2_d_bits_denied_0; // @[ProbePicker.scala:42:9]
assign auto_in_2_d_bits_data = auto_in_2_d_bits_data_0; // @[ProbePicker.scala:42:9]
assign auto_in_2_d_bits_corrupt = auto_in_2_d_bits_corrupt_0; // @[ProbePicker.scala:42:9]
assign auto_in_1_a_ready = auto_in_1_a_ready_0; // @[ProbePicker.scala:42:9]
assign auto_in_1_d_valid = auto_in_1_d_valid_0; // @[ProbePicker.scala:42:9]
assign auto_in_1_d_bits_opcode = auto_in_1_d_bits_opcode_0; // @[ProbePicker.scala:42:9]
assign auto_in_1_d_bits_size = auto_in_1_d_bits_size_0; // @[ProbePicker.scala:42:9]
assign auto_in_1_d_bits_source = auto_in_1_d_bits_source_0; // @[ProbePicker.scala:42:9]
assign auto_in_1_d_bits_denied = auto_in_1_d_bits_denied_0; // @[ProbePicker.scala:42:9]
assign auto_in_1_d_bits_data = auto_in_1_d_bits_data_0; // @[ProbePicker.scala:42:9]
assign auto_in_1_d_bits_corrupt = auto_in_1_d_bits_corrupt_0; // @[ProbePicker.scala:42:9]
assign auto_in_0_a_ready = auto_in_0_a_ready_0; // @[ProbePicker.scala:42:9]
assign auto_in_0_d_valid = auto_in_0_d_valid_0; // @[ProbePicker.scala:42:9]
assign auto_in_0_d_bits_opcode = auto_in_0_d_bits_opcode_0; // @[ProbePicker.scala:42:9]
assign auto_in_0_d_bits_size = auto_in_0_d_bits_size_0; // @[ProbePicker.scala:42:9]
assign auto_in_0_d_bits_source = auto_in_0_d_bits_source_0; // @[ProbePicker.scala:42:9]
assign auto_in_0_d_bits_denied = auto_in_0_d_bits_denied_0; // @[ProbePicker.scala:42:9]
assign auto_in_0_d_bits_data = auto_in_0_d_bits_data_0; // @[ProbePicker.scala:42:9]
assign auto_in_0_d_bits_corrupt = auto_in_0_d_bits_corrupt_0; // @[ProbePicker.scala:42:9]
assign auto_out_4_a_valid = auto_out_4_a_valid_0; // @[ProbePicker.scala:42:9]
assign auto_out_4_a_bits_opcode = auto_out_4_a_bits_opcode_0; // @[ProbePicker.scala:42:9]
assign auto_out_4_a_bits_param = auto_out_4_a_bits_param_0; // @[ProbePicker.scala:42:9]
assign auto_out_4_a_bits_size = auto_out_4_a_bits_size_0; // @[ProbePicker.scala:42:9]
assign auto_out_4_a_bits_source = auto_out_4_a_bits_source_0; // @[ProbePicker.scala:42:9]
assign auto_out_4_a_bits_address = auto_out_4_a_bits_address_0; // @[ProbePicker.scala:42:9]
assign auto_out_4_a_bits_mask = auto_out_4_a_bits_mask_0; // @[ProbePicker.scala:42:9]
assign auto_out_4_a_bits_data = auto_out_4_a_bits_data_0; // @[ProbePicker.scala:42:9]
assign auto_out_4_a_bits_corrupt = auto_out_4_a_bits_corrupt_0; // @[ProbePicker.scala:42:9]
assign auto_out_4_d_ready = auto_out_4_d_ready_0; // @[ProbePicker.scala:42:9]
assign auto_out_3_a_valid = auto_out_3_a_valid_0; // @[ProbePicker.scala:42:9]
assign auto_out_3_a_bits_opcode = auto_out_3_a_bits_opcode_0; // @[ProbePicker.scala:42:9]
assign auto_out_3_a_bits_param = auto_out_3_a_bits_param_0; // @[ProbePicker.scala:42:9]
assign auto_out_3_a_bits_size = auto_out_3_a_bits_size_0; // @[ProbePicker.scala:42:9]
assign auto_out_3_a_bits_source = auto_out_3_a_bits_source_0; // @[ProbePicker.scala:42:9]
assign auto_out_3_a_bits_address = auto_out_3_a_bits_address_0; // @[ProbePicker.scala:42:9]
assign auto_out_3_a_bits_mask = auto_out_3_a_bits_mask_0; // @[ProbePicker.scala:42:9]
assign auto_out_3_a_bits_data = auto_out_3_a_bits_data_0; // @[ProbePicker.scala:42:9]
assign auto_out_3_a_bits_corrupt = auto_out_3_a_bits_corrupt_0; // @[ProbePicker.scala:42:9]
assign auto_out_3_d_ready = auto_out_3_d_ready_0; // @[ProbePicker.scala:42:9]
assign auto_out_2_a_valid = auto_out_2_a_valid_0; // @[ProbePicker.scala:42:9]
assign auto_out_2_a_bits_opcode = auto_out_2_a_bits_opcode_0; // @[ProbePicker.scala:42:9]
assign auto_out_2_a_bits_param = auto_out_2_a_bits_param_0; // @[ProbePicker.scala:42:9]
assign auto_out_2_a_bits_size = auto_out_2_a_bits_size_0; // @[ProbePicker.scala:42:9]
assign auto_out_2_a_bits_source = auto_out_2_a_bits_source_0; // @[ProbePicker.scala:42:9]
assign auto_out_2_a_bits_address = auto_out_2_a_bits_address_0; // @[ProbePicker.scala:42:9]
assign auto_out_2_a_bits_mask = auto_out_2_a_bits_mask_0; // @[ProbePicker.scala:42:9]
assign auto_out_2_a_bits_data = auto_out_2_a_bits_data_0; // @[ProbePicker.scala:42:9]
assign auto_out_2_a_bits_corrupt = auto_out_2_a_bits_corrupt_0; // @[ProbePicker.scala:42:9]
assign auto_out_2_d_ready = auto_out_2_d_ready_0; // @[ProbePicker.scala:42:9]
assign auto_out_1_a_valid = auto_out_1_a_valid_0; // @[ProbePicker.scala:42:9]
assign auto_out_1_a_bits_opcode = auto_out_1_a_bits_opcode_0; // @[ProbePicker.scala:42:9]
assign auto_out_1_a_bits_param = auto_out_1_a_bits_param_0; // @[ProbePicker.scala:42:9]
assign auto_out_1_a_bits_size = auto_out_1_a_bits_size_0; // @[ProbePicker.scala:42:9]
assign auto_out_1_a_bits_source = auto_out_1_a_bits_source_0; // @[ProbePicker.scala:42:9]
assign auto_out_1_a_bits_address = auto_out_1_a_bits_address_0; // @[ProbePicker.scala:42:9]
assign auto_out_1_a_bits_mask = auto_out_1_a_bits_mask_0; // @[ProbePicker.scala:42:9]
assign auto_out_1_a_bits_data = auto_out_1_a_bits_data_0; // @[ProbePicker.scala:42:9]
assign auto_out_1_a_bits_corrupt = auto_out_1_a_bits_corrupt_0; // @[ProbePicker.scala:42:9]
assign auto_out_1_d_ready = auto_out_1_d_ready_0; // @[ProbePicker.scala:42:9]
assign auto_out_0_a_valid = auto_out_0_a_valid_0; // @[ProbePicker.scala:42:9]
assign auto_out_0_a_bits_opcode = auto_out_0_a_bits_opcode_0; // @[ProbePicker.scala:42:9]
assign auto_out_0_a_bits_param = auto_out_0_a_bits_param_0; // @[ProbePicker.scala:42:9]
assign auto_out_0_a_bits_size = auto_out_0_a_bits_size_0; // @[ProbePicker.scala:42:9]
assign auto_out_0_a_bits_source = auto_out_0_a_bits_source_0; // @[ProbePicker.scala:42:9]
assign auto_out_0_a_bits_address = auto_out_0_a_bits_address_0; // @[ProbePicker.scala:42:9]
assign auto_out_0_a_bits_mask = auto_out_0_a_bits_mask_0; // @[ProbePicker.scala:42:9]
assign auto_out_0_a_bits_data = auto_out_0_a_bits_data_0; // @[ProbePicker.scala:42:9]
assign auto_out_0_a_bits_corrupt = auto_out_0_a_bits_corrupt_0; // @[ProbePicker.scala:42:9]
assign auto_out_0_d_ready = auto_out_0_d_ready_0; // @[ProbePicker.scala:42:9]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftRegisterPriorityQueue.scala:
package compressacc
import chisel3._
import chisel3.util._
import chisel3.util._
// TODO : support enq & deq at the same cycle
class PriorityQueueStageIO(keyWidth: Int, value: ValueInfo) extends Bundle {
val output_prev = KeyValue(keyWidth, value)
val output_nxt = KeyValue(keyWidth, value)
val input_prev = Flipped(KeyValue(keyWidth, value))
val input_nxt = Flipped(KeyValue(keyWidth, value))
val cmd = Flipped(Valid(UInt(1.W)))
val insert_here = Input(Bool())
val cur_input_keyval = Flipped(KeyValue(keyWidth, value))
val cur_output_keyval = KeyValue(keyWidth, value)
}
class PriorityQueueStage(keyWidth: Int, value: ValueInfo) extends Module {
val io = IO(new PriorityQueueStageIO(keyWidth, value))
dontTouch(io)
val CMD_DEQ = 0.U
val CMD_ENQ = 1.U
val MAX_VALUE = (1 << keyWidth) - 1
val key_reg = RegInit(MAX_VALUE.U(keyWidth.W))
val value_reg = Reg(value)
io.output_prev.key := key_reg
io.output_prev.value := value_reg
io.output_nxt.key := key_reg
io.output_nxt.value := value_reg
io.cur_output_keyval.key := key_reg
io.cur_output_keyval.value := value_reg
when (io.cmd.valid) {
switch (io.cmd.bits) {
is (CMD_DEQ) {
key_reg := io.input_nxt.key
value_reg := io.input_nxt.value
}
is (CMD_ENQ) {
when (io.insert_here) {
key_reg := io.cur_input_keyval.key
value_reg := io.cur_input_keyval.value
} .elsewhen (key_reg >= io.cur_input_keyval.key) {
key_reg := io.input_prev.key
value_reg := io.input_prev.value
} .otherwise {
// do nothing
}
}
}
}
}
object PriorityQueueStage {
def apply(keyWidth: Int, v: ValueInfo): PriorityQueueStage = new PriorityQueueStage(keyWidth, v)
}
// TODO
// - This design is not scalable as the enqued_keyval is broadcasted to all the stages
// - Add pipeline registers later
class PriorityQueueIO(queSize: Int, keyWidth: Int, value: ValueInfo) extends Bundle {
val cnt_bits = log2Ceil(queSize+1)
val counter = Output(UInt(cnt_bits.W))
val enq = Flipped(Decoupled(KeyValue(keyWidth, value)))
val deq = Decoupled(KeyValue(keyWidth, value))
}
class PriorityQueue(queSize: Int, keyWidth: Int, value: ValueInfo) extends Module {
val keyWidthInternal = keyWidth + 1
val CMD_DEQ = 0.U
val CMD_ENQ = 1.U
val io = IO(new PriorityQueueIO(queSize, keyWidthInternal, value))
dontTouch(io)
val MAX_VALUE = ((1 << keyWidthInternal) - 1).U
val cnt_bits = log2Ceil(queSize+1)
// do not consider cases where we are inserting more entries then the queSize
val counter = RegInit(0.U(cnt_bits.W))
io.counter := counter
val full = (counter === queSize.U)
val empty = (counter === 0.U)
io.deq.valid := !empty
io.enq.ready := !full
when (io.enq.fire) {
counter := counter + 1.U
}
when (io.deq.fire) {
counter := counter - 1.U
}
val cmd_valid = io.enq.valid || io.deq.ready
val cmd = Mux(io.enq.valid, CMD_ENQ, CMD_DEQ)
assert(!(io.enq.valid && io.deq.ready))
val stages = Seq.fill(queSize)(Module(new PriorityQueueStage(keyWidthInternal, value)))
for (i <- 0 until (queSize - 1)) {
stages(i+1).io.input_prev <> stages(i).io.output_nxt
stages(i).io.input_nxt <> stages(i+1).io.output_prev
}
stages(queSize-1).io.input_nxt.key := MAX_VALUE
// stages(queSize-1).io.input_nxt.value :=
stages(queSize-1).io.input_nxt.value.symbol := 0.U
// stages(queSize-1).io.input_nxt.value.child(0) := 0.U
// stages(queSize-1).io.input_nxt.value.child(1) := 0.U
stages(0).io.input_prev.key := io.enq.bits.key
stages(0).io.input_prev.value <> io.enq.bits.value
for (i <- 0 until queSize) {
stages(i).io.cmd.valid := cmd_valid
stages(i).io.cmd.bits := cmd
stages(i).io.cur_input_keyval <> io.enq.bits
}
val is_large_or_equal = WireInit(VecInit(Seq.fill(queSize)(false.B)))
for (i <- 0 until queSize) {
is_large_or_equal(i) := (stages(i).io.cur_output_keyval.key >= io.enq.bits.key)
}
val is_large_or_equal_cat = Wire(UInt(queSize.W))
is_large_or_equal_cat := Cat(is_large_or_equal.reverse)
val insert_here_idx = PriorityEncoder(is_large_or_equal_cat)
for (i <- 0 until queSize) {
when (i.U === insert_here_idx) {
stages(i).io.insert_here := true.B
} .otherwise {
stages(i).io.insert_here := false.B
}
}
io.deq.bits <> stages(0).io.output_prev
}
| module PriorityQueueStage_8( // @[ShiftRegisterPriorityQueue.scala:21:7]
input clock, // @[ShiftRegisterPriorityQueue.scala:21:7]
input reset, // @[ShiftRegisterPriorityQueue.scala:21:7]
output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14]
);
wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24]
assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22]
assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30]
always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24]
else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30]
key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
end
else // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
end
if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7]
value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30]
value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
end
else // @[ShiftRegisterPriorityQueue.scala:21:7]
value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
end
always @(posedge)
assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
File Xbar.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.interrupts
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
class IntXbar()(implicit p: Parameters) extends LazyModule
{
val intnode = new IntNexusNode(
sinkFn = { _ => IntSinkPortParameters(Seq(IntSinkParameters())) },
sourceFn = { seq =>
IntSourcePortParameters((seq zip seq.map(_.num).scanLeft(0)(_+_).init).map {
case (s, o) => s.sources.map(z => z.copy(range = z.range.offset(o)))
}.flatten)
})
{
override def circuitIdentity = outputs == 1 && inputs == 1
}
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
override def desiredName = s"IntXbar_i${intnode.in.size}_o${intnode.out.size}"
val cat = intnode.in.map { case (i, e) => i.take(e.source.num) }.flatten
intnode.out.foreach { case (o, _) => o := cat }
}
}
class IntSyncXbar()(implicit p: Parameters) extends LazyModule
{
val intnode = new IntSyncNexusNode(
sinkFn = { _ => IntSinkPortParameters(Seq(IntSinkParameters())) },
sourceFn = { seq =>
IntSourcePortParameters((seq zip seq.map(_.num).scanLeft(0)(_+_).init).map {
case (s, o) => s.sources.map(z => z.copy(range = z.range.offset(o)))
}.flatten)
})
{
override def circuitIdentity = outputs == 1 && inputs == 1
}
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
override def desiredName = s"IntSyncXbar_i${intnode.in.size}_o${intnode.out.size}"
val cat = intnode.in.map { case (i, e) => i.sync.take(e.source.num) }.flatten
intnode.out.foreach { case (o, _) => o.sync := cat }
}
}
object IntXbar {
def apply()(implicit p: Parameters): IntNode = {
val xbar = LazyModule(new IntXbar)
xbar.intnode
}
}
object IntSyncXbar {
def apply()(implicit p: Parameters): IntSyncNode = {
val xbar = LazyModule(new IntSyncXbar)
xbar.intnode
}
}
| module IntXbar_i4_o1_4(); // @[Xbar.scala:22:9]
wire auto_anon_in_3_0 = 1'h0; // @[Xbar.scala:22:9]
wire auto_anon_in_2_0 = 1'h0; // @[Xbar.scala:22:9]
wire auto_anon_in_1_0 = 1'h0; // @[Xbar.scala:22:9]
wire auto_anon_in_0_0 = 1'h0; // @[Xbar.scala:22:9]
wire auto_anon_out_0 = 1'h0; // @[Xbar.scala:22:9]
wire auto_anon_out_1 = 1'h0; // @[Xbar.scala:22:9]
wire auto_anon_out_2 = 1'h0; // @[Xbar.scala:22:9]
wire auto_anon_out_3 = 1'h0; // @[Xbar.scala:22:9]
wire childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire anonIn_0 = 1'h0; // @[MixedNode.scala:551:17]
wire anonIn_1_0 = 1'h0; // @[MixedNode.scala:551:17]
wire anonIn_2_0 = 1'h0; // @[MixedNode.scala:551:17]
wire anonIn_3_0 = 1'h0; // @[MixedNode.scala:551:17]
wire anonOut_0 = 1'h0; // @[MixedNode.scala:542:17]
wire anonOut_1 = 1'h0; // @[MixedNode.scala:542:17]
wire anonOut_2 = 1'h0; // @[MixedNode.scala:542:17]
wire anonOut_3 = 1'h0; // @[MixedNode.scala:542:17]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Nodes.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection}
case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args))
object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
{
def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo)
def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo)
def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle)
def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle)
def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString)
override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = {
val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge)))
monitor.io.in := bundle
}
override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters =
pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })
override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters =
pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })
}
trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut]
case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode
case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode
case class TLAdapterNode(
clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s },
managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLJunctionNode(
clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters],
managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])(
implicit valName: ValName)
extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode
object TLNameNode {
def apply(name: ValName) = TLIdentityNode()(name)
def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLIdentityNode = apply(Some(name))
}
case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)()
object TLTempNode {
def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp"))
}
case class TLNexusNode(
clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters,
managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)(
implicit valName: ValName)
extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode
abstract class TLCustomNode(implicit valName: ValName)
extends CustomNode(TLImp) with TLFormatNode
// Asynchronous crossings
trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters]
object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle]
{
def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle)
def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString)
override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLAsyncAdapterNode(
clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s },
managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode
case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode
object TLAsyncNameNode {
def apply(name: ValName) = TLAsyncIdentityNode()(name)
def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLAsyncIdentityNode = apply(Some(name))
}
case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLAsyncImp)(
dFn = { p => TLAsyncClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain
case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName)
extends MixedAdapterNode(TLAsyncImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) },
uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut]
// Rationally related crossings
trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters]
object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle]
{
def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle)
def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */)
override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLRationalAdapterNode(
clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s },
managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode
case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode
object TLRationalNameNode {
def apply(name: ValName) = TLRationalIdentityNode()(name)
def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLRationalIdentityNode = apply(Some(name))
}
case class TLRationalSourceNode()(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLRationalImp)(
dFn = { p => TLRationalClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain
case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName)
extends MixedAdapterNode(TLRationalImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut]
// Credited version of TileLink channels
trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters]
object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle]
{
def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle)
def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString)
override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLCreditedAdapterNode(
clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s },
managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode
case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode
object TLCreditedNameNode {
def apply(name: ValName) = TLCreditedIdentityNode()(name)
def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLCreditedIdentityNode = apply(Some(name))
}
case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLCreditedImp)(
dFn = { p => TLCreditedClientPortParameters(delay, p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain
case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLCreditedImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut]
File RegisterRouter.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes}
import freechips.rocketchip.resources.{Device, Resource, ResourceBindings}
import freechips.rocketchip.prci.{NoCrossing}
import freechips.rocketchip.regmapper.{RegField, RegMapper, RegMapperParams, RegMapperInput, RegisterRouter}
import freechips.rocketchip.util.{BundleField, ControlKey, ElaborationArtefacts, GenRegDescsAnno}
import scala.math.min
class TLRegisterRouterExtraBundle(val sourceBits: Int, val sizeBits: Int) extends Bundle {
val source = UInt((sourceBits max 1).W)
val size = UInt((sizeBits max 1).W)
}
case object TLRegisterRouterExtra extends ControlKey[TLRegisterRouterExtraBundle]("tlrr_extra")
case class TLRegisterRouterExtraField(sourceBits: Int, sizeBits: Int) extends BundleField[TLRegisterRouterExtraBundle](TLRegisterRouterExtra, Output(new TLRegisterRouterExtraBundle(sourceBits, sizeBits)), x => {
x.size := 0.U
x.source := 0.U
})
/** TLRegisterNode is a specialized TL SinkNode that encapsulates MMIO registers.
* It provides functionality for describing and outputting metdata about the registers in several formats.
* It also provides a concrete implementation of a regmap function that will be used
* to wire a map of internal registers associated with this node to the node's interconnect port.
*/
case class TLRegisterNode(
address: Seq[AddressSet],
device: Device,
deviceKey: String = "reg/control",
concurrency: Int = 0,
beatBytes: Int = 4,
undefZero: Boolean = true,
executable: Boolean = false)(
implicit valName: ValName)
extends SinkNode(TLImp)(Seq(TLSlavePortParameters.v1(
Seq(TLSlaveParameters.v1(
address = address,
resources = Seq(Resource(device, deviceKey)),
executable = executable,
supportsGet = TransferSizes(1, beatBytes),
supportsPutPartial = TransferSizes(1, beatBytes),
supportsPutFull = TransferSizes(1, beatBytes),
fifoId = Some(0))), // requests are handled in order
beatBytes = beatBytes,
minLatency = min(concurrency, 1)))) with TLFormatNode // the Queue adds at most one cycle
{
val size = 1 << log2Ceil(1 + address.map(_.max).max - address.map(_.base).min)
require (size >= beatBytes)
address.foreach { case a =>
require (a.widen(size-1).base == address.head.widen(size-1).base,
s"TLRegisterNode addresses (${address}) must be aligned to its size ${size}")
}
// Calling this method causes the matching TL2 bundle to be
// configured to route all requests to the listed RegFields.
def regmap(mapping: RegField.Map*) = {
val (bundleIn, edge) = this.in(0)
val a = bundleIn.a
val d = bundleIn.d
val fields = TLRegisterRouterExtraField(edge.bundle.sourceBits, edge.bundle.sizeBits) +: a.bits.params.echoFields
val params = RegMapperParams(log2Up(size/beatBytes), beatBytes, fields)
val in = Wire(Decoupled(new RegMapperInput(params)))
in.bits.read := a.bits.opcode === TLMessages.Get
in.bits.index := edge.addr_hi(a.bits)
in.bits.data := a.bits.data
in.bits.mask := a.bits.mask
Connectable.waiveUnmatched(in.bits.extra, a.bits.echo) match {
case (lhs, rhs) => lhs :<= rhs
}
val a_extra = in.bits.extra(TLRegisterRouterExtra)
a_extra.source := a.bits.source
a_extra.size := a.bits.size
// Invoke the register map builder
val out = RegMapper(beatBytes, concurrency, undefZero, in, mapping:_*)
// No flow control needed
in.valid := a.valid
a.ready := in.ready
d.valid := out.valid
out.ready := d.ready
// We must restore the size to enable width adapters to work
val d_extra = out.bits.extra(TLRegisterRouterExtra)
d.bits := edge.AccessAck(toSource = d_extra.source, lgSize = d_extra.size)
// avoid a Mux on the data bus by manually overriding two fields
d.bits.data := out.bits.data
Connectable.waiveUnmatched(d.bits.echo, out.bits.extra) match {
case (lhs, rhs) => lhs :<= rhs
}
d.bits.opcode := Mux(out.bits.read, TLMessages.AccessAckData, TLMessages.AccessAck)
// Tie off unused channels
bundleIn.b.valid := false.B
bundleIn.c.ready := true.B
bundleIn.e.ready := true.B
genRegDescsJson(mapping:_*)
}
def genRegDescsJson(mapping: RegField.Map*): Unit = {
// Dump out the register map for documentation purposes.
val base = address.head.base
val baseHex = s"0x${base.toInt.toHexString}"
val name = s"${device.describe(ResourceBindings()).name}.At${baseHex}"
val json = GenRegDescsAnno.serialize(base, name, mapping:_*)
var suffix = 0
while( ElaborationArtefacts.contains(s"${baseHex}.${suffix}.regmap.json")) {
suffix = suffix + 1
}
ElaborationArtefacts.add(s"${baseHex}.${suffix}.regmap.json", json)
val module = Module.currentModule.get.asInstanceOf[RawModule]
GenRegDescsAnno.anno(
module,
base,
mapping:_*)
}
}
/** Mix HasTLControlRegMap into any subclass of RegisterRouter to gain helper functions for attaching a device control register map to TileLink.
* - The intended use case is that controlNode will diplomatically publish a SW-visible device's memory-mapped control registers.
* - Use the clock crossing helper controlXing to externally connect controlNode to a TileLink interconnect.
* - Use the mapping helper function regmap to internally fill out the space of device control registers.
*/
trait HasTLControlRegMap { this: RegisterRouter =>
protected val controlNode = TLRegisterNode(
address = address,
device = device,
deviceKey = "reg/control",
concurrency = concurrency,
beatBytes = beatBytes,
undefZero = undefZero,
executable = executable)
// Externally, this helper should be used to connect the register control port to a bus
val controlXing: TLInwardClockCrossingHelper = this.crossIn(controlNode)
// Backwards-compatibility default node accessor with no clock crossing
lazy val node: TLInwardNode = controlXing(NoCrossing)
// Internally, this function should be used to populate the control port with registers
protected def regmap(mapping: RegField.Map*): Unit = { controlNode.regmap(mapping:_*) }
}
File MuxLiteral.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.log2Ceil
import scala.reflect.ClassTag
/* MuxLiteral creates a lookup table from a key to a list of values.
* Unlike MuxLookup, the table keys must be exclusive literals.
*/
object MuxLiteral
{
def apply[T <: Data:ClassTag](index: UInt, default: T, first: (UInt, T), rest: (UInt, T)*): T =
apply(index, default, first :: rest.toList)
def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[(UInt, T)]): T =
MuxTable(index, default, cases.map { case (k, v) => (k.litValue, v) })
}
object MuxSeq
{
def apply[T <: Data:ClassTag](index: UInt, default: T, first: T, rest: T*): T =
apply(index, default, first :: rest.toList)
def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[T]): T =
MuxTable(index, default, cases.zipWithIndex.map { case (v, i) => (BigInt(i), v) })
}
object MuxTable
{
def apply[T <: Data:ClassTag](index: UInt, default: T, first: (BigInt, T), rest: (BigInt, T)*): T =
apply(index, default, first :: rest.toList)
def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[(BigInt, T)]): T = {
/* All keys must be >= 0 and distinct */
cases.foreach { case (k, _) => require (k >= 0) }
require (cases.map(_._1).distinct.size == cases.size)
/* Filter out any cases identical to the default */
val simple = cases.filter { case (k, v) => !default.isLit || !v.isLit || v.litValue != default.litValue }
val maxKey = (BigInt(0) +: simple.map(_._1)).max
val endIndex = BigInt(1) << log2Ceil(maxKey+1)
if (simple.isEmpty) {
default
} else if (endIndex <= 2*simple.size) {
/* The dense encoding case uses a Vec */
val table = Array.fill(endIndex.toInt) { default }
simple.foreach { case (k, v) => table(k.toInt) = v }
Mux(index >= endIndex.U, default, VecInit(table)(index))
} else {
/* The sparse encoding case uses switch */
val out = WireDefault(default)
simple.foldLeft(new chisel3.util.SwitchContext(index, None, Set.empty)) { case (acc, (k, v)) =>
acc.is (k.U) { out := v }
}
out
}
}
}
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File Debug.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.devices.debug
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.amba.apb.{APBFanout, APBToTL}
import freechips.rocketchip.devices.debug.systembusaccess.{SBToTL, SystemBusAccessModule}
import freechips.rocketchip.devices.tilelink.{DevNullParams, TLBusBypass, TLError}
import freechips.rocketchip.diplomacy.{AddressSet, BufferParams}
import freechips.rocketchip.resources.{Description, Device, Resource, ResourceBindings, ResourceString, SimpleDevice}
import freechips.rocketchip.interrupts.{IntNexusNode, IntSinkParameters, IntSinkPortParameters, IntSourceParameters, IntSourcePortParameters, IntSyncCrossingSource, IntSyncIdentityNode}
import freechips.rocketchip.regmapper.{RegField, RegFieldAccessType, RegFieldDesc, RegFieldGroup, RegFieldWrType, RegReadFn, RegWriteFn}
import freechips.rocketchip.rocket.{CSRs, Instructions}
import freechips.rocketchip.tile.MaxHartIdBits
import freechips.rocketchip.tilelink.{TLAsyncCrossingSink, TLAsyncCrossingSource, TLBuffer, TLRegisterNode, TLXbar}
import freechips.rocketchip.util.{Annotated, AsyncBundle, AsyncQueueParams, AsyncResetSynchronizerShiftReg, FromAsyncBundle, ParameterizedBundle, ResetSynchronizerShiftReg, ToAsyncBundle}
import freechips.rocketchip.util.SeqBoolBitwiseOps
import freechips.rocketchip.util.SeqToAugmentedSeq
import freechips.rocketchip.util.BooleanToAugmentedBoolean
object DsbBusConsts {
def sbAddrWidth = 12
def sbIdWidth = 10
}
object DsbRegAddrs{
// These are used by the ROM.
def HALTED = 0x100
def GOING = 0x104
def RESUMING = 0x108
def EXCEPTION = 0x10C
def WHERETO = 0x300
// This needs to be aligned for up to lq/sq
// This shows up in HartInfo, and needs to be aligned
// to enable up to LQ/SQ instructions.
def DATA = 0x380
// We want DATA to immediately follow PROGBUF so that we can
// use them interchangeably. Leave another slot if there is an
// implicit ebreak.
def PROGBUF(cfg:DebugModuleParams) = {
val tmp = DATA - (cfg.nProgramBufferWords * 4)
if (cfg.hasImplicitEbreak) (tmp - 4) else tmp
}
// This is unused if hasImpEbreak is false, and just points to the end of the PROGBUF.
def IMPEBREAK(cfg: DebugModuleParams) = { DATA - 4 }
// We want abstract to be immediately before PROGBUF
// because we auto-generate 2 (or 5) instructions.
def ABSTRACT(cfg:DebugModuleParams) = PROGBUF(cfg) - (cfg.nAbstractInstructions * 4)
def FLAGS = 0x400
def ROMBASE = 0x800
}
/** Enumerations used both in the hardware
* and in the configuration specification.
*/
object DebugModuleAccessType extends scala.Enumeration {
type DebugModuleAccessType = Value
val Access8Bit, Access16Bit, Access32Bit, Access64Bit, Access128Bit = Value
}
object DebugAbstractCommandError extends scala.Enumeration {
type DebugAbstractCommandError = Value
val Success, ErrBusy, ErrNotSupported, ErrException, ErrHaltResume = Value
}
object DebugAbstractCommandType extends scala.Enumeration {
type DebugAbstractCommandType = Value
val AccessRegister, QuickAccess = Value
}
/** Parameters exposed to the top-level design, set based on
* external requirements, etc.
*
* This object checks that the parameters conform to the
* full specification. The implementation which receives this
* object can perform more checks on what that implementation
* actually supports.
* @param nComponents Number of components to support debugging.
* @param baseAddress Base offest for debugEntry and debugException
* @param nDMIAddrSize Size of the Debug Bus Address
* @param nAbstractDataWords Number of 32-bit words for Abstract Commands
* @param nProgamBufferWords Number of 32-bit words for Program Buffer
* @param hasBusMaster Whether or not a bus master should be included
* @param clockGate Whether or not to use dmactive as the clockgate for debug module
* @param maxSupportedSBAccess Maximum transaction size supported by System Bus Access logic.
* @param supportQuickAccess Whether or not to support the quick access command.
* @param supportHartArray Whether or not to implement the hart array register (if >1 hart).
* @param nHaltGroups Number of halt groups
* @param nExtTriggers Number of external triggers
* @param hasHartResets Feature to reset all the currently selected harts
* @param hasImplicitEbreak There is an additional RO program buffer word containing an ebreak
* @param crossingHasSafeReset Include "safe" logic in Async Crossings so that only one side needs to be reset.
*/
case class DebugModuleParams (
baseAddress : BigInt = BigInt(0),
nDMIAddrSize : Int = 7,
nProgramBufferWords: Int = 16,
nAbstractDataWords : Int = 4,
nScratch : Int = 1,
hasBusMaster : Boolean = false,
clockGate : Boolean = true,
maxSupportedSBAccess : Int = 32,
supportQuickAccess : Boolean = false,
supportHartArray : Boolean = true,
nHaltGroups : Int = 1,
nExtTriggers : Int = 0,
hasHartResets : Boolean = false,
hasImplicitEbreak : Boolean = false,
hasAuthentication : Boolean = false,
crossingHasSafeReset : Boolean = true
) {
require ((nDMIAddrSize >= 7) && (nDMIAddrSize <= 32), s"Legal DMIAddrSize is 7-32, not ${nDMIAddrSize}")
require ((nAbstractDataWords > 0) && (nAbstractDataWords <= 16), s"Legal nAbstractDataWords is 0-16, not ${nAbstractDataWords}")
require ((nProgramBufferWords >= 0) && (nProgramBufferWords <= 16), s"Legal nProgramBufferWords is 0-16, not ${nProgramBufferWords}")
require (nHaltGroups < 32, s"Legal nHaltGroups is 0-31, not ${nHaltGroups}")
require (nExtTriggers <= 16, s"Legal nExtTriggers is 0-16, not ${nExtTriggers}")
if (supportQuickAccess) {
// TODO: Check that quick access requirements are met.
}
def address = AddressSet(baseAddress, 0xFFF)
/** the base address of DM */
def atzero = (baseAddress == 0)
/** The number of generated instructions
*
* When the base address is not zero, we need more instruction also,
* more dscratch registers) to load/store memory mapped data register
* because they may no longer be directly addressible with x0 + 12-bit imm
*/
def nAbstractInstructions = if (atzero) 2 else 5
def debugEntry: BigInt = baseAddress + 0x800
def debugException: BigInt = baseAddress + 0x808
def nDscratch: Int = if (atzero) 1 else 2
}
object DefaultDebugModuleParams {
def apply(xlen:Int /*TODO , val configStringAddr: Int*/): DebugModuleParams = {
new DebugModuleParams().copy(
nAbstractDataWords = (if (xlen == 32) 1 else if (xlen == 64) 2 else 4),
maxSupportedSBAccess = xlen
)
}
}
case object DebugModuleKey extends Field[Option[DebugModuleParams]](Some(DebugModuleParams()))
/** Functional parameters exposed to the design configuration.
*
* hartIdToHartSel: For systems where hart ids are not 1:1 with hartsel, provide the mapping.
* hartSelToHartId: Provide inverse mapping of the above
*/
case class DebugModuleHartSelFuncs (
hartIdToHartSel : (UInt) => UInt = (x:UInt) => x,
hartSelToHartId : (UInt) => UInt = (x:UInt) => x
)
case object DebugModuleHartSelKey extends Field(DebugModuleHartSelFuncs())
class DebugExtTriggerOut (val nExtTriggers: Int) extends Bundle {
val req = Output(UInt(nExtTriggers.W))
val ack = Input(UInt(nExtTriggers.W))
}
class DebugExtTriggerIn (val nExtTriggers: Int) extends Bundle {
val req = Input(UInt(nExtTriggers.W))
val ack = Output(UInt(nExtTriggers.W))
}
class DebugExtTriggerIO () (implicit val p: Parameters) extends ParameterizedBundle()(p) {
val out = new DebugExtTriggerOut(p(DebugModuleKey).get.nExtTriggers)
val in = new DebugExtTriggerIn (p(DebugModuleKey).get.nExtTriggers)
}
class DebugAuthenticationIO () (implicit val p: Parameters) extends ParameterizedBundle()(p) {
val dmactive = Output(Bool())
val dmAuthWrite = Output(Bool())
val dmAuthRead = Output(Bool())
val dmAuthWdata = Output(UInt(32.W))
val dmAuthBusy = Input(Bool())
val dmAuthRdata = Input(UInt(32.W))
val dmAuthenticated = Input(Bool())
}
// *****************************************
// Module Interfaces
//
// *****************************************
/** Control signals for Inner, generated in Outer
* {{{
* run control: resumreq, ackhavereset, halt-on-reset mask
* hart select: hasel, hartsel and the hart array mask
* }}}
*/
class DebugInternalBundle (val nComponents: Int)(implicit val p: Parameters) extends ParameterizedBundle()(p) {
/** resume request */
val resumereq = Bool()
/** hart select */
val hartsel = UInt(10.W)
/** reset acknowledge */
val ackhavereset = Bool()
/** hart array enable */
val hasel = Bool()
/** hart array mask */
val hamask = Vec(nComponents, Bool())
/** halt-on-reset mask */
val hrmask = Vec(nComponents, Bool())
}
/** structure for top-level Debug Module signals which aren't the bus interfaces. */
class DebugCtrlBundle (nComponents: Int)(implicit val p: Parameters) extends ParameterizedBundle()(p) {
/** debug availability status for all harts */
val debugUnavail = Input(Vec(nComponents, Bool()))
/** reset signal
*
* for every part of the hardware platform,
* including every hart, except for the DM and any
* logic required to access the DM
*/
val ndreset = Output(Bool())
/** reset signal for the DM itself */
val dmactive = Output(Bool())
/** dmactive acknowlege */
val dmactiveAck = Input(Bool())
}
// *****************************************
// Debug Module
//
// *****************************************
/** Parameterized version of the Debug Module defined in the
* RISC-V Debug Specification
*
* DebugModule is a slave to two asynchronous masters:
* The Debug Bus (DMI) -- This is driven by an external debugger
*
* The System Bus -- This services requests from the cores. Generally
* this interface should only be active at the request
* of the debugger, but the Debug Module may also
* provide the default MTVEC since it is mapped
* to address 0x0.
*
* DebugModule is responsible for control registers and RAM, and
* Debug ROM. It runs partially off of the dmiClk (e.g. TCK) and
* the TL clock. Therefore, it is divided into "Outer" portion (running
* off dmiClock and dmiReset) and "Inner" (running off tl_clock and tl_reset).
* This allows DMCONTROL.haltreq, hartsel, hasel, hawindowsel, hawindow, dmactive,
* and ndreset to be modified even while the Core is in reset or not being clocked.
* Not all reads from the Debugger to the Debug Module will actually complete
* in these scenarios either, they will just block until tl_clock and tl_reset
* allow them to complete. This is not strictly necessary for
* proper debugger functionality.
*/
// Local reg mapper function : Notify when written, but give the value as well.
object WNotifyWire {
def apply(n: Int, value: UInt, set: Bool, name: String, desc: String) : RegField = {
RegField(n, 0.U, RegWriteFn((valid, data) => {
set := valid
value := data
true.B
}), Some(RegFieldDesc(name = name, desc = desc,
access = RegFieldAccessType.W)))
}
}
// Local reg mapper function : Notify when accessed either as read or write.
object RWNotify {
def apply (n: Int, rVal: UInt, wVal: UInt, rNotify: Bool, wNotify: Bool, desc: Option[RegFieldDesc] = None): RegField = {
RegField(n,
RegReadFn ((ready) => {rNotify := ready ; (true.B, rVal)}),
RegWriteFn((valid, data) => {
wNotify := valid
when (valid) {wVal := data}
true.B
}
), desc)
}
}
// Local reg mapper function : Notify with value when written, take read input as presented.
// This allows checking or correcting the write value before storing it in the register field.
object WNotifyVal {
def apply(n: Int, rVal: UInt, wVal: UInt, wNotify: Bool, desc: RegFieldDesc): RegField = {
RegField(n, rVal, RegWriteFn((valid, data) => {
wNotify := valid
wVal := data
true.B
}
), desc)
}
}
class TLDebugModuleOuter(device: Device)(implicit p: Parameters) extends LazyModule {
// For Shorter Register Names
import DMI_RegAddrs._
val cfg = p(DebugModuleKey).get
val intnode = IntNexusNode(
sourceFn = { _ => IntSourcePortParameters(Seq(IntSourceParameters(1, Seq(Resource(device, "int"))))) },
sinkFn = { _ => IntSinkPortParameters(Seq(IntSinkParameters())) },
outputRequiresInput = false)
val dmiNode = TLRegisterNode (
address = AddressSet.misaligned(DMI_DMCONTROL << 2, 4) ++
AddressSet.misaligned(DMI_HARTINFO << 2, 4) ++
AddressSet.misaligned(DMI_HAWINDOWSEL << 2, 4) ++
AddressSet.misaligned(DMI_HAWINDOW << 2, 4),
device = device,
beatBytes = 4,
executable = false
)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
require (intnode.edges.in.size == 0, "Debug Module does not accept interrupts")
val nComponents = intnode.out.size
def getNComponents = () => nComponents
val supportHartArray = cfg.supportHartArray && (nComponents > 1) // no hart array if only one hart
val io = IO(new Bundle {
/** structure for top-level Debug Module signals which aren't the bus interfaces. */
val ctrl = (new DebugCtrlBundle(nComponents))
/** control signals for Inner, generated in Outer */
val innerCtrl = new DecoupledIO(new DebugInternalBundle(nComponents))
/** debug interruption from Inner to Outer
*
* contains 2 type of debug interruption causes:
* - halt group
* - halt-on-reset
*/
val hgDebugInt = Input(Vec(nComponents, Bool()))
/** hart reset request to core */
val hartResetReq = cfg.hasHartResets.option(Output(Vec(nComponents, Bool())))
/** authentication support */
val dmAuthenticated = cfg.hasAuthentication.option(Input(Bool()))
})
val omRegMap = withReset(reset.asAsyncReset) {
// FIXME: Instead of casting reset to ensure it is Async, assert/require reset.Type == AsyncReset (when this feature is available)
val dmAuthenticated = io.dmAuthenticated.map( dma =>
ResetSynchronizerShiftReg(in=dma, sync=3, name=Some("dmAuthenticated_sync"))).getOrElse(true.B)
//----DMCONTROL (The whole point of 'Outer' is to maintain this register on dmiClock (e.g. TCK) domain, so that it
// can be written even if 'Inner' is not being clocked or is in reset. This allows halting
// harts while the rest of the system is in reset. It doesn't really allow any other
// register accesses, which will keep returning 'busy' to the debugger interface.
val DMCONTROLReset = WireInit(0.U.asTypeOf(new DMCONTROLFields()))
val DMCONTROLNxt = WireInit(0.U.asTypeOf(new DMCONTROLFields()))
val DMCONTROLReg = RegNext(next=DMCONTROLNxt, init=0.U.asTypeOf(DMCONTROLNxt)).suggestName("DMCONTROLReg")
val hartsel_mask = if (nComponents > 1) ((1 << p(MaxHartIdBits)) - 1).U else 0.U
val DMCONTROLWrData = WireInit(0.U.asTypeOf(new DMCONTROLFields()))
val dmactiveWrEn = WireInit(false.B)
val ndmresetWrEn = WireInit(false.B)
val clrresethaltreqWrEn = WireInit(false.B)
val setresethaltreqWrEn = WireInit(false.B)
val hartselloWrEn = WireInit(false.B)
val haselWrEn = WireInit(false.B)
val ackhaveresetWrEn = WireInit(false.B)
val hartresetWrEn = WireInit(false.B)
val resumereqWrEn = WireInit(false.B)
val haltreqWrEn = WireInit(false.B)
val dmactive = DMCONTROLReg.dmactive
DMCONTROLNxt := DMCONTROLReg
when (~dmactive) {
DMCONTROLNxt := DMCONTROLReset
} .otherwise {
when (dmAuthenticated && ndmresetWrEn) { DMCONTROLNxt.ndmreset := DMCONTROLWrData.ndmreset }
when (dmAuthenticated && hartselloWrEn) { DMCONTROLNxt.hartsello := DMCONTROLWrData.hartsello & hartsel_mask}
when (dmAuthenticated && haselWrEn) { DMCONTROLNxt.hasel := DMCONTROLWrData.hasel }
when (dmAuthenticated && hartresetWrEn) { DMCONTROLNxt.hartreset := DMCONTROLWrData.hartreset }
when (dmAuthenticated && haltreqWrEn) { DMCONTROLNxt.haltreq := DMCONTROLWrData.haltreq }
}
// Put this last to override its own effects.
when (dmactiveWrEn) {
DMCONTROLNxt.dmactive := DMCONTROLWrData.dmactive
}
//----HARTINFO
// DATA registers are mapped to memory. The dataaddr field of HARTINFO has only
// 12 bits and assumes the DM base is 0. If not at 0, then HARTINFO reads as 0
// (implying nonexistence according to the Debug Spec).
val HARTINFORdData = WireInit(0.U.asTypeOf(new HARTINFOFields()))
if (cfg.atzero) when (dmAuthenticated) {
HARTINFORdData.dataaccess := true.B
HARTINFORdData.datasize := cfg.nAbstractDataWords.U
HARTINFORdData.dataaddr := DsbRegAddrs.DATA.U
HARTINFORdData.nscratch := cfg.nScratch.U
}
//--------------------------------------------------------------
// Hart array mask and window
// hamask is hart array mask(1 bit per component), which doesn't include the hart selected by dmcontrol.hartsello
// HAWINDOWSEL selects a 32-bit slice of HAMASK to be visible for read/write in HAWINDOW
//--------------------------------------------------------------
val hamask = WireInit(VecInit(Seq.fill(nComponents) {false.B} ))
def haWindowSize = 32
// The following need to be declared even if supportHartArray is false due to reference
// at compile time by dmiNode.regmap
val HAWINDOWSELWrData = WireInit(0.U.asTypeOf(new HAWINDOWSELFields()))
val HAWINDOWSELWrEn = WireInit(false.B)
val HAWINDOWRdData = WireInit(0.U.asTypeOf(new HAWINDOWFields()))
val HAWINDOWWrData = WireInit(0.U.asTypeOf(new HAWINDOWFields()))
val HAWINDOWWrEn = WireInit(false.B)
/** whether the hart is selected */
def hartSelected(hart: Int): Bool = {
((io.innerCtrl.bits.hartsel === hart.U) ||
(if (supportHartArray) io.innerCtrl.bits.hasel && io.innerCtrl.bits.hamask(hart) else false.B))
}
val HAWINDOWSELNxt = WireInit(0.U.asTypeOf(new HAWINDOWSELFields()))
val HAWINDOWSELReg = RegNext(next=HAWINDOWSELNxt, init=0.U.asTypeOf(HAWINDOWSELNxt))
if (supportHartArray) {
val HAWINDOWSELReset = WireInit(0.U.asTypeOf(new HAWINDOWSELFields()))
HAWINDOWSELNxt := HAWINDOWSELReg
when (~dmactive || ~dmAuthenticated) {
HAWINDOWSELNxt := HAWINDOWSELReset
} .otherwise {
when (HAWINDOWSELWrEn) {
// Unneeded upper bits of HAWINDOWSEL are tied to 0. Entire register is 0 if all harts fit in one window
if (nComponents > haWindowSize) {
HAWINDOWSELNxt.hawindowsel := HAWINDOWSELWrData.hawindowsel & ((1 << (log2Up(nComponents) - 5)) - 1).U
} else {
HAWINDOWSELNxt.hawindowsel := 0.U
}
}
}
val numHAMASKSlices = ((nComponents - 1)/haWindowSize)+1
HAWINDOWRdData.maskdata := 0.U // default, overridden below
// for each slice,use a hamaskReg to store the selection info
for (ii <- 0 until numHAMASKSlices) {
val sliceMask = if (nComponents > ((ii*haWindowSize) + haWindowSize-1)) (BigInt(1) << haWindowSize) - 1 // All harts in this slice exist
else (BigInt(1)<<(nComponents - (ii*haWindowSize))) - 1 // Partial last slice
val HAMASKRst = WireInit(0.U.asTypeOf(new HAWINDOWFields()))
val HAMASKNxt = WireInit(0.U.asTypeOf(new HAWINDOWFields()))
val HAMASKReg = RegNext(next=HAMASKNxt, init=0.U.asTypeOf(HAMASKNxt))
when (ii.U === HAWINDOWSELReg.hawindowsel) {
HAWINDOWRdData.maskdata := HAMASKReg.asUInt & sliceMask.U
}
HAMASKNxt.maskdata := HAMASKReg.asUInt
when (~dmactive || ~dmAuthenticated) {
HAMASKNxt := HAMASKRst
}.otherwise {
when (HAWINDOWWrEn && (ii.U === HAWINDOWSELReg.hawindowsel)) {
HAMASKNxt.maskdata := HAWINDOWWrData.maskdata
}
}
// drive each slice of hamask with stored HAMASKReg or with new value being written
for (jj <- 0 until haWindowSize) {
if (((ii*haWindowSize) + jj) < nComponents) {
val tempWrData = HAWINDOWWrData.maskdata.asBools
val tempMaskReg = HAMASKReg.asUInt.asBools
when (HAWINDOWWrEn && (ii.U === HAWINDOWSELReg.hawindowsel)) {
hamask(ii*haWindowSize + jj) := tempWrData(jj)
}.otherwise {
hamask(ii*haWindowSize + jj) := tempMaskReg(jj)
}
}
}
}
}
//--------------------------------------------------------------
// Halt-on-reset
// hrmaskReg is current set of harts that should halt-on-reset
// Reset state (dmactive=0) is all zeroes
// Bits are set by writing 1 to DMCONTROL.setresethaltreq
// Bits are cleared by writing 1 to DMCONTROL.clrresethaltreq
// Spec says if both are 1, then clrresethaltreq is executed
// hrmask is the halt-on-reset mask which will be sent to inner
//--------------------------------------------------------------
val hrmask = Wire(Vec(nComponents, Bool()))
val hrmaskNxt = Wire(Vec(nComponents, Bool()))
val hrmaskReg = RegNext(next=hrmaskNxt, init=0.U.asTypeOf(hrmaskNxt)).suggestName("hrmaskReg")
hrmaskNxt := hrmaskReg
for (component <- 0 until nComponents) {
when (~dmactive || ~dmAuthenticated) {
hrmaskNxt(component) := false.B
}.elsewhen (clrresethaltreqWrEn && DMCONTROLWrData.clrresethaltreq && hartSelected(component)) {
hrmaskNxt(component) := false.B
}.elsewhen (setresethaltreqWrEn && DMCONTROLWrData.setresethaltreq && hartSelected(component)) {
hrmaskNxt(component) := true.B
}
}
hrmask := hrmaskNxt
val dmControlRegFields = RegFieldGroup("dmcontrol", Some("debug module control register"), Seq(
WNotifyVal(1, DMCONTROLReg.dmactive & io.ctrl.dmactiveAck, DMCONTROLWrData.dmactive, dmactiveWrEn,
RegFieldDesc("dmactive", "debug module active", reset=Some(0))),
WNotifyVal(1, DMCONTROLReg.ndmreset, DMCONTROLWrData.ndmreset, ndmresetWrEn,
RegFieldDesc("ndmreset", "debug module reset output", reset=Some(0))),
WNotifyVal(1, 0.U, DMCONTROLWrData.clrresethaltreq, clrresethaltreqWrEn,
RegFieldDesc("clrresethaltreq", "clear reset halt request", reset=Some(0), access=RegFieldAccessType.W)),
WNotifyVal(1, 0.U, DMCONTROLWrData.setresethaltreq, setresethaltreqWrEn,
RegFieldDesc("setresethaltreq", "set reset halt request", reset=Some(0), access=RegFieldAccessType.W)),
RegField(12),
if (nComponents > 1) WNotifyVal(p(MaxHartIdBits),
DMCONTROLReg.hartsello, DMCONTROLWrData.hartsello, hartselloWrEn,
RegFieldDesc("hartsello", "hart select low", reset=Some(0)))
else RegField(1),
if (nComponents > 1) RegField(10-p(MaxHartIdBits))
else RegField(9),
if (supportHartArray)
WNotifyVal(1, DMCONTROLReg.hasel, DMCONTROLWrData.hasel, haselWrEn,
RegFieldDesc("hasel", "hart array select", reset=Some(0)))
else RegField(1),
RegField(1),
WNotifyVal(1, 0.U, DMCONTROLWrData.ackhavereset, ackhaveresetWrEn,
RegFieldDesc("ackhavereset", "acknowledge reset", reset=Some(0), access=RegFieldAccessType.W)),
if (cfg.hasHartResets)
WNotifyVal(1, DMCONTROLReg.hartreset, DMCONTROLWrData.hartreset, hartresetWrEn,
RegFieldDesc("hartreset", "hart reset request", reset=Some(0)))
else RegField(1),
WNotifyVal(1, 0.U, DMCONTROLWrData.resumereq, resumereqWrEn,
RegFieldDesc("resumereq", "resume request", reset=Some(0), access=RegFieldAccessType.W)),
WNotifyVal(1, DMCONTROLReg.haltreq, DMCONTROLWrData.haltreq, haltreqWrEn, // Spec says W, but maintaining previous behavior
RegFieldDesc("haltreq", "halt request", reset=Some(0)))
))
val hartinfoRegFields = RegFieldGroup("dmi_hartinfo", Some("hart information"), Seq(
RegField.r(12, HARTINFORdData.dataaddr, RegFieldDesc("dataaddr", "data address", reset=Some(if (cfg.atzero) DsbRegAddrs.DATA else 0))),
RegField.r(4, HARTINFORdData.datasize, RegFieldDesc("datasize", "number of DATA registers", reset=Some(if (cfg.atzero) cfg.nAbstractDataWords else 0))),
RegField.r(1, HARTINFORdData.dataaccess, RegFieldDesc("dataaccess", "data access type", reset=Some(if (cfg.atzero) 1 else 0))),
RegField(3),
RegField.r(4, HARTINFORdData.nscratch, RegFieldDesc("nscratch", "number of scratch registers", reset=Some(if (cfg.atzero) cfg.nScratch else 0)))
))
//--------------------------------------------------------------
// DMI register decoder for Outer
//--------------------------------------------------------------
// regmap addresses are byte offsets from lowest address
def DMI_DMCONTROL_OFFSET = 0
def DMI_HARTINFO_OFFSET = ((DMI_HARTINFO - DMI_DMCONTROL) << 2)
def DMI_HAWINDOWSEL_OFFSET = ((DMI_HAWINDOWSEL - DMI_DMCONTROL) << 2)
def DMI_HAWINDOW_OFFSET = ((DMI_HAWINDOW - DMI_DMCONTROL) << 2)
val omRegMap = dmiNode.regmap(
DMI_DMCONTROL_OFFSET -> dmControlRegFields,
DMI_HARTINFO_OFFSET -> hartinfoRegFields,
DMI_HAWINDOWSEL_OFFSET -> (if (supportHartArray && (nComponents > 32)) Seq(
WNotifyVal(log2Up(nComponents)-5, HAWINDOWSELReg.hawindowsel, HAWINDOWSELWrData.hawindowsel, HAWINDOWSELWrEn,
RegFieldDesc("hawindowsel", "hart array window select", reset=Some(0)))) else Nil),
DMI_HAWINDOW_OFFSET -> (if (supportHartArray) Seq(
WNotifyVal(if (nComponents > 31) 32 else nComponents, HAWINDOWRdData.maskdata, HAWINDOWWrData.maskdata, HAWINDOWWrEn,
RegFieldDesc("hawindow", "hart array window", reset=Some(0), volatile=(nComponents > 32)))) else Nil)
)
//--------------------------------------------------------------
// Interrupt Registers
//--------------------------------------------------------------
val debugIntNxt = WireInit(VecInit(Seq.fill(nComponents) {false.B} ))
val debugIntRegs = RegNext(next=debugIntNxt, init=0.U.asTypeOf(debugIntNxt)).suggestName("debugIntRegs")
debugIntNxt := debugIntRegs
val (intnode_out, _) = intnode.out.unzip
for (component <- 0 until nComponents) {
intnode_out(component)(0) := debugIntRegs(component) | io.hgDebugInt(component)
}
// sends debug interruption to Core when dmcs.haltreq is set,
for (component <- 0 until nComponents) {
when (~dmactive || ~dmAuthenticated) {
debugIntNxt(component) := false.B
}. otherwise {
when (haltreqWrEn && ((DMCONTROLWrData.hartsello === component.U)
|| (if (supportHartArray) DMCONTROLWrData.hasel && hamask(component) else false.B))) {
debugIntNxt(component) := DMCONTROLWrData.haltreq
}
}
}
// Halt request registers are set & cleared by writes to DMCONTROL.haltreq
// resumereq also causes the core to execute a 'dret',
// so resumereq is passed through to Inner.
// hartsel/hasel/hamask must also be used by the DebugModule state machine,
// so it is passed to Inner.
// These registers ensure that requests to dmInner are not lost if inner clock isn't running or requests occur too close together.
// If the innerCtrl async queue is not ready, the notification will be posted and held until ready is received.
// Additional notifications that occur while one is already waiting update the pending data so that the last value written is sent.
// Volatile events resumereq and ackhavereset are registered when they occur and remain pending until ready is received.
val innerCtrlValid = Wire(Bool())
val innerCtrlValidReg = RegInit(false.B).suggestName("innerCtrlValidReg")
val innerCtrlResumeReqReg = RegInit(false.B).suggestName("innerCtrlResumeReqReg")
val innerCtrlAckHaveResetReg = RegInit(false.B).suggestName("innerCtrlAckHaveResetReg")
innerCtrlValid := hartselloWrEn | resumereqWrEn | ackhaveresetWrEn | setresethaltreqWrEn | clrresethaltreqWrEn | haselWrEn |
(HAWINDOWWrEn & supportHartArray.B)
innerCtrlValidReg := io.innerCtrl.valid & ~io.innerCtrl.ready // Hold innerctrl request until the async queue accepts it
innerCtrlResumeReqReg := io.innerCtrl.bits.resumereq & ~io.innerCtrl.ready // Hold resumereq until accepted
innerCtrlAckHaveResetReg := io.innerCtrl.bits.ackhavereset & ~io.innerCtrl.ready // Hold ackhavereset until accepted
io.innerCtrl.valid := innerCtrlValid | innerCtrlValidReg
io.innerCtrl.bits.hartsel := Mux(hartselloWrEn, DMCONTROLWrData.hartsello, DMCONTROLReg.hartsello)
io.innerCtrl.bits.resumereq := (resumereqWrEn & DMCONTROLWrData.resumereq) | innerCtrlResumeReqReg
io.innerCtrl.bits.ackhavereset := (ackhaveresetWrEn & DMCONTROLWrData.ackhavereset) | innerCtrlAckHaveResetReg
io.innerCtrl.bits.hrmask := hrmask
if (supportHartArray) {
io.innerCtrl.bits.hasel := Mux(haselWrEn, DMCONTROLWrData.hasel, DMCONTROLReg.hasel)
io.innerCtrl.bits.hamask := hamask
} else {
io.innerCtrl.bits.hasel := DontCare
io.innerCtrl.bits.hamask := DontCare
}
io.ctrl.ndreset := DMCONTROLReg.ndmreset
io.ctrl.dmactive := DMCONTROLReg.dmactive
// hart reset mechanism implementation
if (cfg.hasHartResets) {
val hartResetNxt = Wire(Vec(nComponents, Bool()))
val hartResetReg = RegNext(next=hartResetNxt, init=0.U.asTypeOf(hartResetNxt))
for (component <- 0 until nComponents) {
hartResetNxt(component) := DMCONTROLReg.hartreset & hartSelected(component)
io.hartResetReq.get(component) := hartResetReg(component)
}
}
omRegMap // FIXME: Remove this when withReset is removed
}}
}
// wrap a Outer with a DMIToTL, derived by dmi clock & reset
class TLDebugModuleOuterAsync(device: Device)(implicit p: Parameters) extends LazyModule {
val cfg = p(DebugModuleKey).get
val dmiXbar = LazyModule (new TLXbar(nameSuffix = Some("dmixbar")))
val dmi2tlOpt = (!p(ExportDebug).apb).option({
val dmi2tl = LazyModule(new DMIToTL())
dmiXbar.node := dmi2tl.node
dmi2tl
})
val apbNodeOpt = p(ExportDebug).apb.option({
val apb2tl = LazyModule(new APBToTL())
val apb2tlBuffer = LazyModule(new TLBuffer(BufferParams.pipe))
val dmTopAddr = (1 << cfg.nDMIAddrSize) << 2
val tlErrorParams = DevNullParams(AddressSet.misaligned(dmTopAddr, APBDebugConsts.apbDebugRegBase-dmTopAddr), maxAtomic=0, maxTransfer=4)
val tlError = LazyModule(new TLError(tlErrorParams, buffer=false))
val apbXbar = LazyModule(new APBFanout())
val apbRegs = LazyModule(new APBDebugRegisters())
apbRegs.node := apbXbar.node
apb2tl.node := apbXbar.node
apb2tlBuffer.node := apb2tl.node
dmiXbar.node := apb2tlBuffer.node
tlError.node := dmiXbar.node
apbXbar.node
})
val dmOuter = LazyModule( new TLDebugModuleOuter(device))
val intnode = IntSyncIdentityNode()
intnode :*= IntSyncCrossingSource(alreadyRegistered = true) :*= dmOuter.intnode
val dmiBypass = LazyModule(new TLBusBypass(beatBytes=4, bufferError=false, maxAtomic=0, maxTransfer=4))
val dmiInnerNode = TLAsyncCrossingSource() := dmiBypass.node := dmiXbar.node
dmOuter.dmiNode := dmiXbar.node
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
val nComponents = dmOuter.intnode.edges.out.size
val io = IO(new Bundle {
val dmi_clock = Input(Clock())
val dmi_reset = Input(Reset())
/** Debug Module Interface bewteen DM and DTM
*
* The DTM provides access to one or more Debug Modules (DMs) using DMI
*/
val dmi = (!p(ExportDebug).apb).option(Flipped(new DMIIO()(p)))
// Optional APB Interface is fully diplomatic so is not listed here.
val ctrl = new DebugCtrlBundle(nComponents)
/** conrol signals for Inner, generated in Outer */
val innerCtrl = new AsyncBundle(new DebugInternalBundle(nComponents), AsyncQueueParams.singleton(safe=cfg.crossingHasSafeReset))
/** debug interruption generated in Inner */
val hgDebugInt = Input(Vec(nComponents, Bool()))
/** hart reset request to core */
val hartResetReq = p(DebugModuleKey).get.hasHartResets.option(Output(Vec(nComponents, Bool())))
/** Authentication signal from core */
val dmAuthenticated = p(DebugModuleKey).get.hasAuthentication.option(Input(Bool()))
})
val rf_reset = IO(Input(Reset())) // RF transform
childClock := io.dmi_clock
childReset := io.dmi_reset
override def provideImplicitClockToLazyChildren = true
withClockAndReset(childClock, childReset) {
dmi2tlOpt.foreach { _.module.io.dmi <> io.dmi.get }
val dmactiveAck = AsyncResetSynchronizerShiftReg(in=io.ctrl.dmactiveAck, sync=3, name=Some("dmactiveAckSync"))
dmiBypass.module.io.bypass := ~io.ctrl.dmactive | ~dmactiveAck
io.ctrl <> dmOuter.module.io.ctrl
dmOuter.module.io.ctrl.dmactiveAck := dmactiveAck // send synced version down to dmOuter
io.innerCtrl <> ToAsyncBundle(dmOuter.module.io.innerCtrl, AsyncQueueParams.singleton(safe=cfg.crossingHasSafeReset))
dmOuter.module.io.hgDebugInt := io.hgDebugInt
io.hartResetReq.foreach { x => dmOuter.module.io.hartResetReq.foreach {y => x := y}}
io.dmAuthenticated.foreach { x => dmOuter.module.io.dmAuthenticated.foreach { y => y := x}}
}
}
}
class TLDebugModuleInner(device: Device, getNComponents: () => Int, beatBytes: Int)(implicit p: Parameters) extends LazyModule
{
// For Shorter Register Names
import DMI_RegAddrs._
val cfg = p(DebugModuleKey).get
def getCfg = () => cfg
val dmTopAddr = (1 << cfg.nDMIAddrSize) << 2
/** dmiNode address set */
val dmiNode = TLRegisterNode(
// Address is range 0 to 0x1FF except DMCONTROL, HARTINFO, HAWINDOWSEL, HAWINDOW which are handled by Outer
address = AddressSet.misaligned(0, DMI_DMCONTROL << 2) ++
AddressSet.misaligned((DMI_DMCONTROL + 1) << 2, ((DMI_HARTINFO << 2) - ((DMI_DMCONTROL + 1) << 2))) ++
AddressSet.misaligned((DMI_HARTINFO + 1) << 2, ((DMI_HAWINDOWSEL << 2) - ((DMI_HARTINFO + 1) << 2))) ++
AddressSet.misaligned((DMI_HAWINDOW + 1) << 2, (dmTopAddr - ((DMI_HAWINDOW + 1) << 2))),
device = device,
beatBytes = 4,
executable = false
)
val tlNode = TLRegisterNode(
address=Seq(cfg.address),
device=device,
beatBytes=beatBytes,
executable=true
)
val sb2tlOpt = cfg.hasBusMaster.option(LazyModule(new SBToTL()))
// If we want to support custom registers read through Abstract Commands,
// provide a place to bring them into the debug module. What this connects
// to is up to the implementation.
val customNode = new DebugCustomSink()
lazy val module = new Impl
class Impl extends LazyModuleImp(this){
val nComponents = getNComponents()
Annotated.params(this, cfg)
val supportHartArray = cfg.supportHartArray & (nComponents > 1)
val nExtTriggers = cfg.nExtTriggers
val nHaltGroups = if ((nComponents > 1) | (nExtTriggers > 0)) cfg.nHaltGroups
else 0 // no halt groups possible if single hart with no external triggers
val hartSelFuncs = if (getNComponents() > 1) p(DebugModuleHartSelKey) else DebugModuleHartSelFuncs(
hartIdToHartSel = (x) => 0.U,
hartSelToHartId = (x) => x
)
val io = IO(new Bundle {
/** dm reset signal passed in from Outer */
val dmactive = Input(Bool())
/** conrol signals for Inner
*
* it's generated by Outer and comes in
*/
val innerCtrl = Flipped(new DecoupledIO(new DebugInternalBundle(nComponents)))
/** debug unavail signal passed in from Outer*/
val debugUnavail = Input(Vec(nComponents, Bool()))
/** debug interruption from Inner to Outer
*
* contain 2 type of debug interruption causes:
* - halt group
* - halt-on-reset
*/
val hgDebugInt = Output(Vec(nComponents, Bool()))
/** interface for trigger */
val extTrigger = (nExtTriggers > 0).option(new DebugExtTriggerIO())
/** vector to indicate which hart is in reset
*
* dm receives it from core and sends it to Inner
*/
val hartIsInReset = Input(Vec(nComponents, Bool()))
val tl_clock = Input(Clock())
val tl_reset = Input(Reset())
/** Debug Authentication signals from core */
val auth = cfg.hasAuthentication.option(new DebugAuthenticationIO())
})
sb2tlOpt.map { sb =>
sb.module.clock := io.tl_clock
sb.module.reset := io.tl_reset
sb.module.rf_reset := io.tl_reset
}
//--------------------------------------------------------------
// Import constants for shorter variable names
//--------------------------------------------------------------
import DMI_RegAddrs._
import DsbRegAddrs._
import DsbBusConsts._
//--------------------------------------------------------------
// Sanity Check Configuration For this implementation.
//--------------------------------------------------------------
require (cfg.supportQuickAccess == false, "No Quick Access support yet")
require ((nHaltGroups > 0) || (nExtTriggers == 0), "External triggers require at least 1 halt group")
//--------------------------------------------------------------
// Register & Wire Declarations (which need to be pre-declared)
//--------------------------------------------------------------
// run control regs: tracking all the harts
// implements: see implementation-specific bits part
/** all harts halted status */
val haltedBitRegs = Reg(UInt(nComponents.W))
/** all harts resume request status */
val resumeReqRegs = Reg(UInt(nComponents.W))
/** all harts have reset status */
val haveResetBitRegs = Reg(UInt(nComponents.W))
// default is 1,after resume, resumeAcks get 0
/** all harts resume ack status */
val resumeAcks = Wire(UInt(nComponents.W))
// --- regmapper outputs
// hart state Id and En
// in Hart Bus Access ROM
val hartHaltedWrEn = Wire(Bool())
val hartHaltedId = Wire(UInt(sbIdWidth.W))
val hartGoingWrEn = Wire(Bool())
val hartGoingId = Wire(UInt(sbIdWidth.W))
val hartResumingWrEn = Wire(Bool())
val hartResumingId = Wire(UInt(sbIdWidth.W))
val hartExceptionWrEn = Wire(Bool())
val hartExceptionId = Wire(UInt(sbIdWidth.W))
// progbuf and abstract data: byte-addressable control logic
// AccessLegal is set only when state = waiting
// RdEn and WrEnMaybe : contrl signal drived by DMI bus
val dmiProgramBufferRdEn = WireInit(VecInit(Seq.fill(cfg.nProgramBufferWords * 4) {false.B} ))
val dmiProgramBufferAccessLegal = WireInit(false.B)
val dmiProgramBufferWrEnMaybe = WireInit(VecInit(Seq.fill(cfg.nProgramBufferWords * 4) {false.B} ))
val dmiAbstractDataRdEn = WireInit(VecInit(Seq.fill(cfg.nAbstractDataWords * 4) {false.B} ))
val dmiAbstractDataAccessLegal = WireInit(false.B)
val dmiAbstractDataWrEnMaybe = WireInit(VecInit(Seq.fill(cfg.nAbstractDataWords * 4) {false.B} ))
//--------------------------------------------------------------
// Registers coming from 'CONTROL' in Outer
//--------------------------------------------------------------
val dmAuthenticated = io.auth.map(a => a.dmAuthenticated).getOrElse(true.B)
val selectedHartReg = Reg(UInt(p(MaxHartIdBits).W))
// hamaskFull is a vector of all selected harts including hartsel, whether or not supportHartArray is true
val hamaskFull = WireInit(VecInit(Seq.fill(nComponents) {false.B} ))
if (nComponents > 1) {
when (~io.dmactive) {
selectedHartReg := 0.U
}.elsewhen (io.innerCtrl.fire){
selectedHartReg := io.innerCtrl.bits.hartsel
}
}
if (supportHartArray) {
val hamaskZero = WireInit(VecInit(Seq.fill(nComponents) {false.B} ))
val hamaskReg = Reg(Vec(nComponents, Bool()))
when (~io.dmactive || ~dmAuthenticated) {
hamaskReg := hamaskZero
}.elsewhen (io.innerCtrl.fire){
hamaskReg := Mux(io.innerCtrl.bits.hasel, io.innerCtrl.bits.hamask, hamaskZero)
}
hamaskFull := hamaskReg
}
// Outer.hamask doesn't consider the hart selected by dmcontrol.hartsello,
// so append it here
when (selectedHartReg < nComponents.U) {
hamaskFull(if (nComponents == 1) 0.U(0.W) else selectedHartReg) := true.B
}
io.innerCtrl.ready := true.B
// Construct a Vec from io.innerCtrl fields indicating whether each hart is being selected in this write
// A hart may be selected by hartsel field or by hart array
val hamaskWrSel = WireInit(VecInit(Seq.fill(nComponents) {false.B} ))
for (component <- 0 until nComponents ) {
hamaskWrSel(component) := ((io.innerCtrl.bits.hartsel === component.U) ||
(if (supportHartArray) io.innerCtrl.bits.hasel && io.innerCtrl.bits.hamask(component) else false.B))
}
//-------------------------------------
// Halt-on-reset logic
// hrmask is set in dmOuter and passed in
// Debug interrupt is generated when a reset occurs whose corresponding hrmask bit is set
// Debug interrupt is maintained until the hart enters halted state
//-------------------------------------
val hrReset = WireInit(VecInit(Seq.fill(nComponents) { false.B } ))
val hrDebugInt = Wire(Vec(nComponents, Bool()))
val hrmaskReg = RegInit(hrReset)
val hartIsInResetSync = Wire(Vec(nComponents, Bool()))
for (component <- 0 until nComponents) {
hartIsInResetSync(component) := AsyncResetSynchronizerShiftReg(io.hartIsInReset(component), 3, Some(s"debug_hartReset_$component"))
}
when (~io.dmactive || ~dmAuthenticated) {
hrmaskReg := hrReset
}.elsewhen (io.innerCtrl.fire){
hrmaskReg := io.innerCtrl.bits.hrmask
}
withReset(reset.asAsyncReset) { // ensure interrupt requests are negated at first clock edge
val hrDebugIntReg = RegInit(VecInit(Seq.fill(nComponents) { false.B } ))
when (~io.dmactive || ~dmAuthenticated) {
hrDebugIntReg := hrReset
}.otherwise {
hrDebugIntReg := hrmaskReg &
(hartIsInResetSync | // set debugInt during reset
(hrDebugIntReg & ~(haltedBitRegs.asBools))) // maintain until core halts
}
hrDebugInt := hrDebugIntReg
}
//--------------------------------------------------------------
// DMI Registers
//--------------------------------------------------------------
//----DMSTATUS
val DMSTATUSRdData = WireInit(0.U.asTypeOf(new DMSTATUSFields()))
DMSTATUSRdData.authenticated := dmAuthenticated
DMSTATUSRdData.version := 2.U // Version 0.13
io.auth.map(a => DMSTATUSRdData.authbusy := a.dmAuthBusy)
val resumereq = io.innerCtrl.fire && io.innerCtrl.bits.resumereq
when (dmAuthenticated) {
DMSTATUSRdData.hasresethaltreq := true.B
DMSTATUSRdData.anynonexistent := (selectedHartReg >= nComponents.U) // only hartsel can be nonexistent
// all harts nonexistent if hartsel is out of range and there are no harts selected in the hart array
DMSTATUSRdData.allnonexistent := (selectedHartReg >= nComponents.U) & (~hamaskFull.reduce(_ | _))
when (~DMSTATUSRdData.allnonexistent) { // if no existent harts selected, all other status is false
DMSTATUSRdData.anyunavail := (io.debugUnavail & hamaskFull).reduce(_ | _)
DMSTATUSRdData.anyhalted := ((~io.debugUnavail & (haltedBitRegs.asBools)) & hamaskFull).reduce(_ | _)
DMSTATUSRdData.anyrunning := ((~io.debugUnavail & ~(haltedBitRegs.asBools)) & hamaskFull).reduce(_ | _)
DMSTATUSRdData.anyhavereset := (haveResetBitRegs.asBools & hamaskFull).reduce(_ | _)
DMSTATUSRdData.anyresumeack := (resumeAcks.asBools & hamaskFull).reduce(_ | _)
when (~DMSTATUSRdData.anynonexistent) { // if one hart is nonexistent, no 'all' status is set
DMSTATUSRdData.allunavail := (io.debugUnavail | ~hamaskFull).reduce(_ & _)
DMSTATUSRdData.allhalted := ((~io.debugUnavail & (haltedBitRegs.asBools)) | ~hamaskFull).reduce(_ & _)
DMSTATUSRdData.allrunning := ((~io.debugUnavail & ~(haltedBitRegs.asBools)) | ~hamaskFull).reduce(_ & _)
DMSTATUSRdData.allhavereset := (haveResetBitRegs.asBools | ~hamaskFull).reduce(_ & _)
DMSTATUSRdData.allresumeack := (resumeAcks.asBools | ~hamaskFull).reduce(_ & _)
}
}
//TODO
DMSTATUSRdData.confstrptrvalid := false.B
DMSTATUSRdData.impebreak := (cfg.hasImplicitEbreak).B
}
when(~io.dmactive || ~dmAuthenticated) {
haveResetBitRegs := 0.U
}.otherwise {
when (io.innerCtrl.fire && io.innerCtrl.bits.ackhavereset) {
haveResetBitRegs := (haveResetBitRegs & (~(hamaskWrSel.asUInt))) | hartIsInResetSync.asUInt
}.otherwise {
haveResetBitRegs := haveResetBitRegs | hartIsInResetSync.asUInt
}
}
//----DMCS2 (Halt Groups)
val DMCS2RdData = WireInit(0.U.asTypeOf(new DMCS2Fields()))
val DMCS2WrData = WireInit(0.U.asTypeOf(new DMCS2Fields()))
val hgselectWrEn = WireInit(false.B)
val hgwriteWrEn = WireInit(false.B)
val haltgroupWrEn = WireInit(false.B)
val exttriggerWrEn = WireInit(false.B)
val hgDebugInt = WireInit(VecInit(Seq.fill(nComponents) {false.B} ))
if (nHaltGroups > 0) withReset (reset.asAsyncReset) { // async reset ensures triggers don't falsely fire during startup
val hgBits = log2Up(nHaltGroups)
// hgParticipate: Each entry indicates which hg that entity belongs to (1 to nHartGroups). 0 means no hg assigned.
val hgParticipateHart = RegInit(VecInit(Seq.fill(nComponents)(0.U(hgBits.W))))
val hgParticipateTrig = if (nExtTriggers > 0) RegInit(VecInit(Seq.fill(nExtTriggers)(0.U(hgBits.W)))) else Nil
// assign group index to current seledcted harts
for (component <- 0 until nComponents) {
when (~io.dmactive || ~dmAuthenticated) {
hgParticipateHart(component) := 0.U
}.otherwise {
when (haltgroupWrEn & DMCS2WrData.hgwrite & ~DMCS2WrData.hgselect &
hamaskFull(component) & (DMCS2WrData.haltgroup <= nHaltGroups.U)) {
hgParticipateHart(component) := DMCS2WrData.haltgroup
}
}
}
DMCS2RdData.haltgroup := hgParticipateHart(if (nComponents == 1) 0.U(0.W) else selectedHartReg)
if (nExtTriggers > 0) {
val hgSelect = Reg(Bool())
when (~io.dmactive || ~dmAuthenticated) {
hgSelect := false.B
}.otherwise {
when (hgselectWrEn) {
hgSelect := DMCS2WrData.hgselect
}
}
// assign group index to trigger
for (trigger <- 0 until nExtTriggers) {
when (~io.dmactive || ~dmAuthenticated) {
hgParticipateTrig(trigger) := 0.U
}.otherwise {
when (haltgroupWrEn & DMCS2WrData.hgwrite & DMCS2WrData.hgselect &
(DMCS2WrData.exttrigger === trigger.U) & (DMCS2WrData.haltgroup <= nHaltGroups.U)) {
hgParticipateTrig(trigger) := DMCS2WrData.haltgroup
}
}
}
DMCS2RdData.hgselect := hgSelect
when (hgSelect) {
DMCS2RdData.haltgroup := hgParticipateTrig(0)
}
// If there is only 1 ext trigger, then the exttrigger field is fixed at 0
// Otherwise, instantiate a register with only the number of bits required
if (nExtTriggers > 1) {
val trigBits = log2Up(nExtTriggers-1)
val hgExtTrigger = Reg(UInt(trigBits.W))
when (~io.dmactive || ~dmAuthenticated) {
hgExtTrigger := 0.U
}.otherwise {
when (exttriggerWrEn & (DMCS2WrData.exttrigger < nExtTriggers.U)) {
hgExtTrigger := DMCS2WrData.exttrigger
}
}
DMCS2RdData.exttrigger := hgExtTrigger
when (hgSelect) {
DMCS2RdData.haltgroup := hgParticipateTrig(hgExtTrigger)
}
}
}
// Halt group state machine
// IDLE: Go to FIRED when any hart in this hg writes to HALTED while its HaltedBitRegs=0
// or when any trigin assigned to this hg occurs
// FIRED: Back to IDLE when all harts in this hg have set their haltedBitRegs
// and all trig out in this hg have been acknowledged
val hgFired = RegInit (VecInit(Seq.fill(nHaltGroups+1) {false.B} ))
val hgHartFiring = WireInit(VecInit(Seq.fill(nHaltGroups+1) {false.B} )) // which hg's are firing due to hart halting
val hgTrigFiring = WireInit(VecInit(Seq.fill(nHaltGroups+1) {false.B} )) // which hg's are firing due to trig in
val hgHartsAllHalted = WireInit(VecInit(Seq.fill(nHaltGroups+1) {false.B} )) // in which hg's have all harts halted
val hgTrigsAllAcked = WireInit(VecInit(Seq.fill(nHaltGroups+1) { true.B} )) // in which hg's have all trigouts been acked
io.extTrigger.foreach {extTrigger =>
val extTriggerInReq = Wire(Vec(nExtTriggers, Bool()))
val extTriggerOutAck = Wire(Vec(nExtTriggers, Bool()))
extTriggerInReq := extTrigger.in.req.asBools
extTriggerOutAck := extTrigger.out.ack.asBools
val trigInReq = ResetSynchronizerShiftReg(in=extTriggerInReq, sync=3, name=Some("dm_extTriggerInReqSync"))
val trigOutAck = ResetSynchronizerShiftReg(in=extTriggerOutAck, sync=3, name=Some("dm_extTriggerOutAckSync"))
for (hg <- 1 to nHaltGroups) {
hgTrigFiring(hg) := (trigInReq & ~RegNext(trigInReq) & hgParticipateTrig.map(_ === hg.U)).reduce(_ | _)
hgTrigsAllAcked(hg) := (trigOutAck | hgParticipateTrig.map(_ =/= hg.U)).reduce(_ & _)
}
extTrigger.in.ack := trigInReq.asUInt
}
for (hg <- 1 to nHaltGroups) {
hgHartFiring(hg) := hartHaltedWrEn & ~haltedBitRegs(hartHaltedId) & (hgParticipateHart(hartSelFuncs.hartIdToHartSel(hartHaltedId)) === hg.U)
hgHartsAllHalted(hg) := (haltedBitRegs.asBools | hgParticipateHart.map(_ =/= hg.U)).reduce(_ & _)
when (~io.dmactive || ~dmAuthenticated) {
hgFired(hg) := false.B
}.elsewhen (~hgFired(hg) & (hgHartFiring(hg) | hgTrigFiring(hg))) {
hgFired(hg) := true.B
}.elsewhen ( hgFired(hg) & hgHartsAllHalted(hg) & hgTrigsAllAcked(hg)) {
hgFired(hg) := false.B
}
}
// For each hg that has fired, assert debug interrupt to each hart in that hg
for (component <- 0 until nComponents) {
hgDebugInt(component) := hgFired(hgParticipateHart(component))
}
// For each hg that has fired, assert trigger out for all external triggers in that hg
io.extTrigger.foreach {extTrigger =>
val extTriggerOutReq = RegInit(VecInit(Seq.fill(cfg.nExtTriggers) {false.B} ))
for (trig <- 0 until nExtTriggers) {
extTriggerOutReq(trig) := hgFired(hgParticipateTrig(trig))
}
extTrigger.out.req := extTriggerOutReq.asUInt
}
}
io.hgDebugInt := hgDebugInt | hrDebugInt
//----HALTSUM*
val numHaltedStatus = ((nComponents - 1) / 32) + 1
val haltedStatus = Wire(Vec(numHaltedStatus, Bits(32.W)))
for (ii <- 0 until numHaltedStatus) {
when (dmAuthenticated) {
haltedStatus(ii) := haltedBitRegs >> (ii*32)
}.otherwise {
haltedStatus(ii) := 0.U
}
}
val haltedSummary = Cat(haltedStatus.map(_.orR).reverse)
val HALTSUM1RdData = haltedSummary.asTypeOf(new HALTSUM1Fields())
val selectedHaltedStatus = Mux((selectedHartReg >> 5) > numHaltedStatus.U, 0.U, haltedStatus(selectedHartReg >> 5))
val HALTSUM0RdData = selectedHaltedStatus.asTypeOf(new HALTSUM0Fields())
// Since we only support 1024 harts, we don't implement HALTSUM2 or HALTSUM3
//----ABSTRACTCS
val ABSTRACTCSReset = WireInit(0.U.asTypeOf(new ABSTRACTCSFields()))
ABSTRACTCSReset.datacount := cfg.nAbstractDataWords.U
ABSTRACTCSReset.progbufsize := cfg.nProgramBufferWords.U
val ABSTRACTCSReg = Reg(new ABSTRACTCSFields())
val ABSTRACTCSWrData = WireInit(0.U.asTypeOf(new ABSTRACTCSFields()))
val ABSTRACTCSRdData = WireInit(ABSTRACTCSReg)
val ABSTRACTCSRdEn = WireInit(false.B)
val ABSTRACTCSWrEnMaybe = WireInit(false.B)
val ABSTRACTCSWrEnLegal = WireInit(false.B)
val ABSTRACTCSWrEn = ABSTRACTCSWrEnMaybe && ABSTRACTCSWrEnLegal
// multiple error types
// find implement in the state machine part
val errorBusy = WireInit(false.B)
val errorException = WireInit(false.B)
val errorUnsupported = WireInit(false.B)
val errorHaltResume = WireInit(false.B)
when (~io.dmactive || ~dmAuthenticated) {
ABSTRACTCSReg := ABSTRACTCSReset
}.otherwise {
when (errorBusy){
ABSTRACTCSReg.cmderr := DebugAbstractCommandError.ErrBusy.id.U
}.elsewhen (errorException) {
ABSTRACTCSReg.cmderr := DebugAbstractCommandError.ErrException.id.U
}.elsewhen (errorUnsupported) {
ABSTRACTCSReg.cmderr := DebugAbstractCommandError.ErrNotSupported.id.U
}.elsewhen (errorHaltResume) {
ABSTRACTCSReg.cmderr := DebugAbstractCommandError.ErrHaltResume.id.U
}.otherwise {
//W1C
when (ABSTRACTCSWrEn){
ABSTRACTCSReg.cmderr := ABSTRACTCSReg.cmderr & ~(ABSTRACTCSWrData.cmderr);
}
}
}
// For busy, see below state machine.
val abstractCommandBusy = WireInit(true.B)
ABSTRACTCSRdData.busy := abstractCommandBusy
when (~dmAuthenticated) { // read value must be 0 when not authenticated
ABSTRACTCSRdData.datacount := 0.U
ABSTRACTCSRdData.progbufsize := 0.U
}
//---- ABSTRACTAUTO
// It is a mask indicating whether datai/probufi have the autoexcution permisson
// this part aims to produce 3 wires : autoexecData,autoexecProg,autoexec
// first two specify which reg supports autoexec
// autoexec is a control signal, meaning there is at least one enabled autoexec reg
// when autoexec is set, generate instructions using COMMAND register
val ABSTRACTAUTOReset = WireInit(0.U.asTypeOf(new ABSTRACTAUTOFields()))
val ABSTRACTAUTOReg = Reg(new ABSTRACTAUTOFields())
val ABSTRACTAUTOWrData = WireInit(0.U.asTypeOf(new ABSTRACTAUTOFields()))
val ABSTRACTAUTORdData = WireInit(ABSTRACTAUTOReg)
val ABSTRACTAUTORdEn = WireInit(false.B)
val autoexecdataWrEnMaybe = WireInit(false.B)
val autoexecprogbufWrEnMaybe = WireInit(false.B)
val ABSTRACTAUTOWrEnLegal = WireInit(false.B)
when (~io.dmactive || ~dmAuthenticated) {
ABSTRACTAUTOReg := ABSTRACTAUTOReset
}.otherwise {
when (autoexecprogbufWrEnMaybe && ABSTRACTAUTOWrEnLegal) {
ABSTRACTAUTOReg.autoexecprogbuf := ABSTRACTAUTOWrData.autoexecprogbuf & ( (1 << cfg.nProgramBufferWords) - 1).U
}
when (autoexecdataWrEnMaybe && ABSTRACTAUTOWrEnLegal) {
ABSTRACTAUTOReg.autoexecdata := ABSTRACTAUTOWrData.autoexecdata & ( (1 << cfg.nAbstractDataWords) - 1).U
}
}
// Abstract Data access vector(byte-addressable)
val dmiAbstractDataAccessVec = WireInit(VecInit(Seq.fill(cfg.nAbstractDataWords * 4) {false.B} ))
dmiAbstractDataAccessVec := (dmiAbstractDataWrEnMaybe zip dmiAbstractDataRdEn).map{ case (r,w) => r | w}
// Program Buffer access vector(byte-addressable)
val dmiProgramBufferAccessVec = WireInit(VecInit(Seq.fill(cfg.nProgramBufferWords * 4) {false.B} ))
dmiProgramBufferAccessVec := (dmiProgramBufferWrEnMaybe zip dmiProgramBufferRdEn).map{ case (r,w) => r | w}
// at least one word access
val dmiAbstractDataAccess = dmiAbstractDataAccessVec.reduce(_ || _ )
val dmiProgramBufferAccess = dmiProgramBufferAccessVec.reduce(_ || _)
// This will take the shorter of the lists, which is what we want.
val autoexecData = WireInit(VecInit(Seq.fill(cfg.nAbstractDataWords) {false.B} ))
val autoexecProg = WireInit(VecInit(Seq.fill(cfg.nProgramBufferWords) {false.B} ))
(autoexecData zip ABSTRACTAUTOReg.autoexecdata.asBools).zipWithIndex.foreach {case (t, i) => t._1 := dmiAbstractDataAccessVec(i * 4) && t._2 }
(autoexecProg zip ABSTRACTAUTOReg.autoexecprogbuf.asBools).zipWithIndex.foreach {case (t, i) => t._1 := dmiProgramBufferAccessVec(i * 4) && t._2}
val autoexec = autoexecData.reduce(_ || _) || autoexecProg.reduce(_ || _)
//---- COMMAND
val COMMANDReset = WireInit(0.U.asTypeOf(new COMMANDFields()))
val COMMANDReg = Reg(new COMMANDFields())
val COMMANDWrDataVal = WireInit(0.U(32.W))
val COMMANDWrData = WireInit(COMMANDWrDataVal.asTypeOf(new COMMANDFields()))
val COMMANDWrEnMaybe = WireInit(false.B)
val COMMANDWrEnLegal = WireInit(false.B)
val COMMANDRdEn = WireInit(false.B)
val COMMANDWrEn = COMMANDWrEnMaybe && COMMANDWrEnLegal
val COMMANDRdData = COMMANDReg
when (~io.dmactive || ~dmAuthenticated) {
COMMANDReg := COMMANDReset
}.otherwise {
when (COMMANDWrEn) {
COMMANDReg := COMMANDWrData
}
}
// --- Abstract Data
// These are byte addressible, s.t. the Processor can use
// byte-addressible instructions to store to them.
val abstractDataMem = Reg(Vec(cfg.nAbstractDataWords*4, UInt(8.W)))
val abstractDataNxt = WireInit(abstractDataMem)
// --- Program Buffer
// byte-addressible mem
val programBufferMem = Reg(Vec(cfg.nProgramBufferWords*4, UInt(8.W)))
val programBufferNxt = WireInit(programBufferMem)
//--------------------------------------------------------------
// These bits are implementation-specific bits set
// by harts executing code.
//--------------------------------------------------------------
// Run control logic
when (~io.dmactive || ~dmAuthenticated) {
haltedBitRegs := 0.U
resumeReqRegs := 0.U
}.otherwise {
//remove those harts in reset
resumeReqRegs := resumeReqRegs & ~(hartIsInResetSync.asUInt)
val hartHaltedIdIndex = UIntToOH(hartSelFuncs.hartIdToHartSel(hartHaltedId))
val hartResumingIdIndex = UIntToOH(hartSelFuncs.hartIdToHartSel(hartResumingId))
val hartselIndex = UIntToOH(io.innerCtrl.bits.hartsel)
when (hartHaltedWrEn) {
// add those harts halting and remove those in reset
haltedBitRegs := (haltedBitRegs | hartHaltedIdIndex) & ~(hartIsInResetSync.asUInt)
}.elsewhen (hartResumingWrEn) {
// remove those harts in reset and those in resume
haltedBitRegs := (haltedBitRegs & ~(hartResumingIdIndex)) & ~(hartIsInResetSync.asUInt)
}.otherwise {
// remove those harts in reset
haltedBitRegs := haltedBitRegs & ~(hartIsInResetSync.asUInt)
}
when (hartResumingWrEn) {
// remove those harts in resume and those in reset
resumeReqRegs := (resumeReqRegs & ~(hartResumingIdIndex)) & ~(hartIsInResetSync.asUInt)
}
when (resumereq) {
// set all sleceted harts to resumeReq, remove those in reset
resumeReqRegs := (resumeReqRegs | hamaskWrSel.asUInt) & ~(hartIsInResetSync.asUInt)
}
}
when (resumereq) {
// next cycle resumeAcls will be the negation of next cycle resumeReqRegs
resumeAcks := (~resumeReqRegs & ~(hamaskWrSel.asUInt))
}.otherwise {
resumeAcks := ~resumeReqRegs
}
//---- AUTHDATA
val authRdEnMaybe = WireInit(false.B)
val authWrEnMaybe = WireInit(false.B)
io.auth.map { a =>
a.dmactive := io.dmactive
a.dmAuthRead := authRdEnMaybe & ~a.dmAuthBusy
a.dmAuthWrite := authWrEnMaybe & ~a.dmAuthBusy
}
val dmstatusRegFields = RegFieldGroup("dmi_dmstatus", Some("debug module status register"), Seq(
RegField.r(4, DMSTATUSRdData.version, RegFieldDesc("version", "version", reset=Some(2))),
RegField.r(1, DMSTATUSRdData.confstrptrvalid, RegFieldDesc("confstrptrvalid", "confstrptrvalid", reset=Some(0))),
RegField.r(1, DMSTATUSRdData.hasresethaltreq, RegFieldDesc("hasresethaltreq", "hasresethaltreq", reset=Some(1))),
RegField.r(1, DMSTATUSRdData.authbusy, RegFieldDesc("authbusy", "authbusy", reset=Some(0))),
RegField.r(1, DMSTATUSRdData.authenticated, RegFieldDesc("authenticated", "authenticated", reset=Some(1))),
RegField.r(1, DMSTATUSRdData.anyhalted, RegFieldDesc("anyhalted", "anyhalted", reset=Some(0))),
RegField.r(1, DMSTATUSRdData.allhalted, RegFieldDesc("allhalted", "allhalted", reset=Some(0))),
RegField.r(1, DMSTATUSRdData.anyrunning, RegFieldDesc("anyrunning", "anyrunning", reset=Some(1))),
RegField.r(1, DMSTATUSRdData.allrunning, RegFieldDesc("allrunning", "allrunning", reset=Some(1))),
RegField.r(1, DMSTATUSRdData.anyunavail, RegFieldDesc("anyunavail", "anyunavail", reset=Some(0))),
RegField.r(1, DMSTATUSRdData.allunavail, RegFieldDesc("allunavail", "allunavail", reset=Some(0))),
RegField.r(1, DMSTATUSRdData.anynonexistent, RegFieldDesc("anynonexistent", "anynonexistent", reset=Some(0))),
RegField.r(1, DMSTATUSRdData.allnonexistent, RegFieldDesc("allnonexistent", "allnonexistent", reset=Some(0))),
RegField.r(1, DMSTATUSRdData.anyresumeack, RegFieldDesc("anyresumeack", "anyresumeack", reset=Some(1))),
RegField.r(1, DMSTATUSRdData.allresumeack, RegFieldDesc("allresumeack", "allresumeack", reset=Some(1))),
RegField.r(1, DMSTATUSRdData.anyhavereset, RegFieldDesc("anyhavereset", "anyhavereset", reset=Some(0))),
RegField.r(1, DMSTATUSRdData.allhavereset, RegFieldDesc("allhavereset", "allhavereset", reset=Some(0))),
RegField(2),
RegField.r(1, DMSTATUSRdData.impebreak, RegFieldDesc("impebreak", "impebreak", reset=Some(if (cfg.hasImplicitEbreak) 1 else 0)))
))
val dmcs2RegFields = RegFieldGroup("dmi_dmcs2", Some("debug module control/status register 2"), Seq(
WNotifyVal(1, DMCS2RdData.hgselect, DMCS2WrData.hgselect, hgselectWrEn,
RegFieldDesc("hgselect", "select halt groups or external triggers", reset=Some(0), volatile=true)),
WNotifyVal(1, 0.U, DMCS2WrData.hgwrite, hgwriteWrEn,
RegFieldDesc("hgwrite", "write 1 to change halt groups", reset=None, access=RegFieldAccessType.W)),
WNotifyVal(5, DMCS2RdData.haltgroup, DMCS2WrData.haltgroup, haltgroupWrEn,
RegFieldDesc("haltgroup", "halt group", reset=Some(0), volatile=true)),
if (nExtTriggers > 1)
WNotifyVal(4, DMCS2RdData.exttrigger, DMCS2WrData.exttrigger, exttriggerWrEn,
RegFieldDesc("exttrigger", "external trigger select", reset=Some(0), volatile=true))
else RegField(4)
))
val abstractcsRegFields = RegFieldGroup("dmi_abstractcs", Some("abstract command control/status"), Seq(
RegField.r(4, ABSTRACTCSRdData.datacount, RegFieldDesc("datacount", "number of DATA registers", reset=Some(cfg.nAbstractDataWords))),
RegField(4),
WNotifyVal(3, ABSTRACTCSRdData.cmderr, ABSTRACTCSWrData.cmderr, ABSTRACTCSWrEnMaybe,
RegFieldDesc("cmderr", "command error", reset=Some(0), wrType=Some(RegFieldWrType.ONE_TO_CLEAR))),
RegField(1),
RegField.r(1, ABSTRACTCSRdData.busy, RegFieldDesc("busy", "busy", reset=Some(0))),
RegField(11),
RegField.r(5, ABSTRACTCSRdData.progbufsize, RegFieldDesc("progbufsize", "number of PROGBUF registers", reset=Some(cfg.nProgramBufferWords)))
))
val (sbcsFields, sbAddrFields, sbDataFields):
(Seq[RegField], Seq[Seq[RegField]], Seq[Seq[RegField]]) = sb2tlOpt.map{ sb2tl =>
SystemBusAccessModule(sb2tl, io.dmactive, dmAuthenticated)(p)
}.getOrElse((Seq.empty[RegField], Seq.fill[Seq[RegField]](4)(Seq.empty[RegField]), Seq.fill[Seq[RegField]](4)(Seq.empty[RegField])))
//--------------------------------------------------------------
// Program Buffer Access (DMI ... System Bus can override)
//--------------------------------------------------------------
val omRegMap = dmiNode.regmap(
(DMI_DMSTATUS << 2) -> dmstatusRegFields,
//TODO (DMI_CFGSTRADDR0 << 2) -> cfgStrAddrFields,
(DMI_DMCS2 << 2) -> (if (nHaltGroups > 0) dmcs2RegFields else Nil),
(DMI_HALTSUM0 << 2) -> RegFieldGroup("dmi_haltsum0", Some("Halt Summary 0"),
Seq(RegField.r(32, HALTSUM0RdData.asUInt, RegFieldDesc("dmi_haltsum0", "halt summary 0")))),
(DMI_HALTSUM1 << 2) -> RegFieldGroup("dmi_haltsum1", Some("Halt Summary 1"),
Seq(RegField.r(32, HALTSUM1RdData.asUInt, RegFieldDesc("dmi_haltsum1", "halt summary 1")))),
(DMI_ABSTRACTCS << 2) -> abstractcsRegFields,
(DMI_ABSTRACTAUTO<< 2) -> RegFieldGroup("dmi_abstractauto", Some("abstract command autoexec"), Seq(
WNotifyVal(cfg.nAbstractDataWords, ABSTRACTAUTORdData.autoexecdata, ABSTRACTAUTOWrData.autoexecdata, autoexecdataWrEnMaybe,
RegFieldDesc("autoexecdata", "abstract command data autoexec", reset=Some(0))),
RegField(16-cfg.nAbstractDataWords),
WNotifyVal(cfg.nProgramBufferWords, ABSTRACTAUTORdData.autoexecprogbuf, ABSTRACTAUTOWrData.autoexecprogbuf, autoexecprogbufWrEnMaybe,
RegFieldDesc("autoexecprogbuf", "abstract command progbuf autoexec", reset=Some(0))))),
(DMI_COMMAND << 2) -> RegFieldGroup("dmi_command", Some("Abstract Command Register"),
Seq(RWNotify(32, COMMANDRdData.asUInt, COMMANDWrDataVal, COMMANDRdEn, COMMANDWrEnMaybe,
Some(RegFieldDesc("dmi_command", "abstract command register", reset=Some(0), volatile=true))))),
(DMI_DATA0 << 2) -> RegFieldGroup("dmi_data", Some("abstract command data registers"), abstractDataMem.zipWithIndex.map{case (x, i) =>
RWNotify(8, Mux(dmAuthenticated, x, 0.U), abstractDataNxt(i),
dmiAbstractDataRdEn(i),
dmiAbstractDataWrEnMaybe(i),
Some(RegFieldDesc(s"dmi_data_$i", s"abstract command data register $i", reset = Some(0), volatile=true)))}, false),
(DMI_PROGBUF0 << 2) -> RegFieldGroup("dmi_progbuf", Some("abstract command progbuf registers"), programBufferMem.zipWithIndex.map{case (x, i) =>
RWNotify(8, Mux(dmAuthenticated, x, 0.U), programBufferNxt(i),
dmiProgramBufferRdEn(i),
dmiProgramBufferWrEnMaybe(i),
Some(RegFieldDesc(s"dmi_progbuf_$i", s"abstract command progbuf register $i", reset = Some(0))))}, false),
(DMI_AUTHDATA << 2) -> (if (cfg.hasAuthentication) RegFieldGroup("dmi_authdata", Some("authentication data exchange register"),
Seq(RWNotify(32, io.auth.get.dmAuthRdata, io.auth.get.dmAuthWdata, authRdEnMaybe, authWrEnMaybe,
Some(RegFieldDesc("authdata", "authentication data exchange", volatile=true))))) else Nil),
(DMI_SBCS << 2) -> sbcsFields,
(DMI_SBDATA0 << 2) -> sbDataFields(0),
(DMI_SBDATA1 << 2) -> sbDataFields(1),
(DMI_SBDATA2 << 2) -> sbDataFields(2),
(DMI_SBDATA3 << 2) -> sbDataFields(3),
(DMI_SBADDRESS0 << 2) -> sbAddrFields(0),
(DMI_SBADDRESS1 << 2) -> sbAddrFields(1),
(DMI_SBADDRESS2 << 2) -> sbAddrFields(2),
(DMI_SBADDRESS3 << 2) -> sbAddrFields(3)
)
// Abstract data mem is written by both the tile link interface and DMI...
abstractDataMem.zipWithIndex.foreach { case (x, i) =>
when (dmAuthenticated && dmiAbstractDataWrEnMaybe(i) && dmiAbstractDataAccessLegal) {
x := abstractDataNxt(i)
}
}
// ... and also by custom register read (if implemented)
val (customs, customParams) = customNode.in.unzip
val needCustom = (customs.size > 0) && (customParams.head.addrs.size > 0)
def getNeedCustom = () => needCustom
if (needCustom) {
val (custom, customP) = customNode.in.head
require(customP.width % 8 == 0, s"Debug Custom width must be divisible by 8, not ${customP.width}")
val custom_data = custom.data.asBools
val custom_bytes = Seq.tabulate(customP.width/8){i => custom_data.slice(i*8, (i+1)*8).asUInt}
when (custom.ready && custom.valid) {
(abstractDataMem zip custom_bytes).zipWithIndex.foreach {case ((a, b), i) =>
a := b
}
}
}
programBufferMem.zipWithIndex.foreach { case (x, i) =>
when (dmAuthenticated && dmiProgramBufferWrEnMaybe(i) && dmiProgramBufferAccessLegal) {
x := programBufferNxt(i)
}
}
//--------------------------------------------------------------
// "Variable" ROM Generation
//--------------------------------------------------------------
val goReg = Reg(Bool())
val goAbstract = WireInit(false.B)
val goCustom = WireInit(false.B)
val jalAbstract = WireInit(Instructions.JAL.value.U.asTypeOf(new GeneratedUJ()))
jalAbstract.setImm(ABSTRACT(cfg) - WHERETO)
when (~io.dmactive){
goReg := false.B
}.otherwise {
when (goAbstract) {
goReg := true.B
}.elsewhen (hartGoingWrEn){
assert(hartGoingId === 0.U, "Unexpected 'GOING' hart.")//Chisel3 #540 %x, expected %x", hartGoingId, 0.U)
goReg := false.B
}
}
class flagBundle extends Bundle {
val reserved = UInt(6.W)
val resume = Bool()
val go = Bool()
}
val flags = WireInit(VecInit(Seq.fill(1 << selectedHartReg.getWidth) {0.U.asTypeOf(new flagBundle())} ))
assert ((hartSelFuncs.hartSelToHartId(selectedHartReg) < flags.size.U),
s"HartSel to HartId Mapping is illegal for this Debug Implementation, because HartID must be < ${flags.size} for it to work.")
flags(hartSelFuncs.hartSelToHartId(selectedHartReg)).go := goReg
for (component <- 0 until nComponents) {
val componentSel = WireInit(component.U)
flags(hartSelFuncs.hartSelToHartId(componentSel)).resume := resumeReqRegs(component)
}
//----------------------------
// Abstract Command Decoding & Generation
//----------------------------
val accessRegisterCommandWr = WireInit(COMMANDWrData.asUInt.asTypeOf(new ACCESS_REGISTERFields()))
/** real COMMAND*/
val accessRegisterCommandReg = WireInit(COMMANDReg.asUInt.asTypeOf(new ACCESS_REGISTERFields()))
// TODO: Quick Access
class GeneratedI extends Bundle {
val imm = UInt(12.W)
val rs1 = UInt(5.W)
val funct3 = UInt(3.W)
val rd = UInt(5.W)
val opcode = UInt(7.W)
}
class GeneratedS extends Bundle {
val immhi = UInt(7.W)
val rs2 = UInt(5.W)
val rs1 = UInt(5.W)
val funct3 = UInt(3.W)
val immlo = UInt(5.W)
val opcode = UInt(7.W)
}
class GeneratedCSR extends Bundle {
val imm = UInt(12.W)
val rs1 = UInt(5.W)
val funct3 = UInt(3.W)
val rd = UInt(5.W)
val opcode = UInt(7.W)
}
class GeneratedUJ extends Bundle {
val imm3 = UInt(1.W)
val imm0 = UInt(10.W)
val imm1 = UInt(1.W)
val imm2 = UInt(8.W)
val rd = UInt(5.W)
val opcode = UInt(7.W)
def setImm(imm: Int) : Unit = {
// TODO: Check bounds of imm.
require(imm % 2 == 0, "Immediate must be even for UJ encoding.")
val immWire = WireInit(imm.S(21.W))
val immBits = WireInit(VecInit(immWire.asBools))
imm0 := immBits.slice(1, 1 + 10).asUInt
imm1 := immBits.slice(11, 11 + 11).asUInt
imm2 := immBits.slice(12, 12 + 8).asUInt
imm3 := immBits.slice(20, 20 + 1).asUInt
}
}
require((cfg.atzero && cfg.nAbstractInstructions == 2) || (!cfg.atzero && cfg.nAbstractInstructions == 5),
"Mismatch between DebugModuleParams atzero and nAbstractInstructions")
val abstractGeneratedMem = Reg(Vec(cfg.nAbstractInstructions, (UInt(32.W))))
def abstractGeneratedI(cfg: DebugModuleParams): UInt = {
val inst = Wire(new GeneratedI())
val offset = if (cfg.atzero) DATA else (DATA-0x800) & 0xFFF
val base = if (cfg.atzero) 0.U else Mux(accessRegisterCommandReg.regno(0), 8.U, 9.U)
inst.opcode := (Instructions.LW.value.U.asTypeOf(new GeneratedI())).opcode
inst.rd := (accessRegisterCommandReg.regno & 0x1F.U)
inst.funct3 := accessRegisterCommandReg.size
inst.rs1 := base
inst.imm := offset.U
inst.asUInt
}
def abstractGeneratedS(cfg: DebugModuleParams): UInt = {
val inst = Wire(new GeneratedS())
val offset = if (cfg.atzero) DATA else (DATA-0x800) & 0xFFF
val base = if (cfg.atzero) 0.U else Mux(accessRegisterCommandReg.regno(0), 8.U, 9.U)
inst.opcode := (Instructions.SW.value.U.asTypeOf(new GeneratedS())).opcode
inst.immlo := (offset & 0x1F).U
inst.funct3 := accessRegisterCommandReg.size
inst.rs1 := base
inst.rs2 := (accessRegisterCommandReg.regno & 0x1F.U)
inst.immhi := (offset >> 5).U
inst.asUInt
}
def abstractGeneratedCSR: UInt = {
val inst = Wire(new GeneratedCSR())
val base = Mux(accessRegisterCommandReg.regno(0), 8.U, 9.U) // use s0 as base for odd regs, s1 as base for even regs
inst := (Instructions.CSRRW.value.U.asTypeOf(new GeneratedCSR()))
inst.imm := CSRs.dscratch1.U
inst.rs1 := base
inst.rd := base
inst.asUInt
}
val nop = Wire(new GeneratedI())
nop := Instructions.ADDI.value.U.asTypeOf(new GeneratedI())
nop.rd := 0.U
nop.rs1 := 0.U
nop.imm := 0.U
val isa = Wire(new GeneratedI())
isa := Instructions.ADDIW.value.U.asTypeOf(new GeneratedI())
isa.rd := 0.U
isa.rs1 := 0.U
isa.imm := 0.U
when (goAbstract) {
if (cfg.nAbstractInstructions == 2) {
// ABSTRACT(0): Transfer: LW or SW, else NOP
// ABSTRACT(1): Postexec: NOP else EBREAK
abstractGeneratedMem(0) := Mux(accessRegisterCommandReg.transfer,
Mux(accessRegisterCommandReg.write, abstractGeneratedI(cfg), abstractGeneratedS(cfg)),
nop.asUInt
)
abstractGeneratedMem(1) := Mux(accessRegisterCommandReg.postexec,
nop.asUInt,
Instructions.EBREAK.value.U)
} else {
// Entry: All regs in GPRs, dscratch1=offset 0x800 in DM
// ABSTRACT(0): CheckISA: ADDW or NOP (exception here if size=3 and not RV64)
// ABSTRACT(1): CSRRW s1,dscratch1,s1 or CSRRW s0,dscratch1,s0
// ABSTRACT(2): Transfer: LW, SW, LD, SD else NOP
// ABSTRACT(3): CSRRW s1,dscratch1,s1 or CSRRW s0,dscratch1,s0
// ABSTRACT(4): Postexec: NOP else EBREAK
abstractGeneratedMem(0) := Mux(accessRegisterCommandReg.transfer && accessRegisterCommandReg.size =/= 2.U, isa.asUInt, nop.asUInt)
abstractGeneratedMem(1) := abstractGeneratedCSR
abstractGeneratedMem(2) := Mux(accessRegisterCommandReg.transfer,
Mux(accessRegisterCommandReg.write, abstractGeneratedI(cfg), abstractGeneratedS(cfg)),
nop.asUInt
)
abstractGeneratedMem(3) := abstractGeneratedCSR
abstractGeneratedMem(4) := Mux(accessRegisterCommandReg.postexec,
nop.asUInt,
Instructions.EBREAK.value.U)
}
}
//--------------------------------------------------------------
// Drive Custom Access
//--------------------------------------------------------------
if (needCustom) {
val (custom, customP) = customNode.in.head
custom.addr := accessRegisterCommandReg.regno
custom.valid := goCustom
}
//--------------------------------------------------------------
// Hart Bus Access
//--------------------------------------------------------------
tlNode.regmap(
// This memory is writable.
HALTED -> Seq(WNotifyWire(sbIdWidth, hartHaltedId, hartHaltedWrEn,
"debug_hart_halted", "Debug ROM Causes hart to write its hartID here when it is in Debug Mode.")),
GOING -> Seq(WNotifyWire(sbIdWidth, hartGoingId, hartGoingWrEn,
"debug_hart_going", "Debug ROM causes hart to write 0 here when it begins executing Debug Mode instructions.")),
RESUMING -> Seq(WNotifyWire(sbIdWidth, hartResumingId, hartResumingWrEn,
"debug_hart_resuming", "Debug ROM causes hart to write its hartID here when it leaves Debug Mode.")),
EXCEPTION -> Seq(WNotifyWire(sbIdWidth, hartExceptionId, hartExceptionWrEn,
"debug_hart_exception", "Debug ROM causes hart to write 0 here if it gets an exception in Debug Mode.")),
DATA -> RegFieldGroup("debug_data", Some("Data used to communicate with Debug Module"),
abstractDataMem.zipWithIndex.map {case (x, i) => RegField(8, x, RegFieldDesc(s"debug_data_$i", ""))}),
PROGBUF(cfg)-> RegFieldGroup("debug_progbuf", Some("Program buffer used to communicate with Debug Module"),
programBufferMem.zipWithIndex.map {case (x, i) => RegField(8, x, RegFieldDesc(s"debug_progbuf_$i", ""))}),
// These sections are read-only.
IMPEBREAK(cfg)-> {if (cfg.hasImplicitEbreak) Seq(RegField.r(32, Instructions.EBREAK.value.U,
RegFieldDesc("debug_impebreak", "Debug Implicit EBREAK", reset=Some(Instructions.EBREAK.value)))) else Nil},
WHERETO -> Seq(RegField.r(32, jalAbstract.asUInt, RegFieldDesc("debug_whereto", "Instruction filled in by Debug Module to control hart in Debug Mode", volatile = true))),
ABSTRACT(cfg) -> RegFieldGroup("debug_abstract", Some("Instructions generated by Debug Module"),
abstractGeneratedMem.zipWithIndex.map{ case (x,i) => RegField.r(32, x, RegFieldDesc(s"debug_abstract_$i", "", volatile=true))}),
FLAGS -> RegFieldGroup("debug_flags", Some("Memory region used to control hart going/resuming in Debug Mode"),
if (nComponents == 1) {
Seq.tabulate(1024) { i => RegField.r(8, flags(0).asUInt, RegFieldDesc(s"debug_flags_$i", "", volatile=true)) }
} else {
flags.zipWithIndex.map{case(x, i) => RegField.r(8, x.asUInt, RegFieldDesc(s"debug_flags_$i", "", volatile=true))}
}),
ROMBASE -> RegFieldGroup("debug_rom", Some("Debug ROM"),
(if (cfg.atzero) DebugRomContents() else DebugRomNonzeroContents()).zipWithIndex.map{case (x, i) =>
RegField.r(8, (x & 0xFF).U(8.W), RegFieldDesc(s"debug_rom_$i", "", reset=Some(x)))})
)
// Override System Bus accesses with dmactive reset.
when (~io.dmactive){
abstractDataMem.foreach {x => x := 0.U}
programBufferMem.foreach {x => x := 0.U}
}
//--------------------------------------------------------------
// Abstract Command State Machine
//--------------------------------------------------------------
object CtrlState extends scala.Enumeration {
type CtrlState = Value
val Waiting, CheckGenerate, Exec, Custom = Value
def apply( t : Value) : UInt = {
t.id.U(log2Up(values.size).W)
}
}
import CtrlState._
// This is not an initialization!
val ctrlStateReg = Reg(chiselTypeOf(CtrlState(Waiting)))
val hartHalted = haltedBitRegs(if (nComponents == 1) 0.U(0.W) else selectedHartReg)
val ctrlStateNxt = WireInit(ctrlStateReg)
//------------------------
// DMI Register Control and Status
abstractCommandBusy := (ctrlStateReg =/= CtrlState(Waiting))
ABSTRACTCSWrEnLegal := (ctrlStateReg === CtrlState(Waiting))
COMMANDWrEnLegal := (ctrlStateReg === CtrlState(Waiting))
ABSTRACTAUTOWrEnLegal := (ctrlStateReg === CtrlState(Waiting))
dmiAbstractDataAccessLegal := (ctrlStateReg === CtrlState(Waiting))
dmiProgramBufferAccessLegal := (ctrlStateReg === CtrlState(Waiting))
errorBusy := (ABSTRACTCSWrEnMaybe && ~ABSTRACTCSWrEnLegal) ||
(autoexecdataWrEnMaybe && ~ABSTRACTAUTOWrEnLegal) ||
(autoexecprogbufWrEnMaybe && ~ABSTRACTAUTOWrEnLegal) ||
(COMMANDWrEnMaybe && ~COMMANDWrEnLegal) ||
(dmiAbstractDataAccess && ~dmiAbstractDataAccessLegal) ||
(dmiProgramBufferAccess && ~dmiProgramBufferAccessLegal)
// TODO: Maybe Quick Access
val commandWrIsAccessRegister = (COMMANDWrData.cmdtype === DebugAbstractCommandType.AccessRegister.id.U)
val commandRegIsAccessRegister = (COMMANDReg.cmdtype === DebugAbstractCommandType.AccessRegister.id.U)
val commandWrIsUnsupported = COMMANDWrEn && !commandWrIsAccessRegister
val commandRegIsUnsupported = WireInit(true.B)
val commandRegBadHaltResume = WireInit(false.B)
// We only support abstract commands for GPRs and any custom registers, if specified.
val accessRegIsLegalSize = (accessRegisterCommandReg.size === 2.U) || (accessRegisterCommandReg.size === 3.U)
val accessRegIsGPR = (accessRegisterCommandReg.regno >= 0x1000.U && accessRegisterCommandReg.regno <= 0x101F.U) && accessRegIsLegalSize
val accessRegIsCustom = if (needCustom) {
val (custom, customP) = customNode.in.head
customP.addrs.foldLeft(false.B){
(result, current) => result || (current.U === accessRegisterCommandReg.regno)}
} else false.B
when (commandRegIsAccessRegister) {
when (accessRegIsCustom && accessRegisterCommandReg.transfer && accessRegisterCommandReg.write === false.B) {
commandRegIsUnsupported := false.B
}.elsewhen (!accessRegisterCommandReg.transfer || accessRegIsGPR) {
commandRegIsUnsupported := false.B
commandRegBadHaltResume := ~hartHalted
}
}
val wrAccessRegisterCommand = COMMANDWrEn && commandWrIsAccessRegister && (ABSTRACTCSReg.cmderr === 0.U)
val regAccessRegisterCommand = autoexec && commandRegIsAccessRegister && (ABSTRACTCSReg.cmderr === 0.U)
//------------------------
// Variable ROM STATE MACHINE
// -----------------------
when (ctrlStateReg === CtrlState(Waiting)){
when (wrAccessRegisterCommand || regAccessRegisterCommand) {
ctrlStateNxt := CtrlState(CheckGenerate)
}.elsewhen (commandWrIsUnsupported) { // These checks are really on the command type.
errorUnsupported := true.B
}.elsewhen (autoexec && commandRegIsUnsupported) {
errorUnsupported := true.B
}
}.elsewhen (ctrlStateReg === CtrlState(CheckGenerate)){
// We use this state to ensure that the COMMAND has been
// registered by the time that we need to use it, to avoid
// generating it directly from the COMMANDWrData.
// This 'commandRegIsUnsupported' is really just checking the
// AccessRegisterCommand parameters (regno)
when (commandRegIsUnsupported) {
errorUnsupported := true.B
ctrlStateNxt := CtrlState(Waiting)
}.elsewhen (commandRegBadHaltResume){
errorHaltResume := true.B
ctrlStateNxt := CtrlState(Waiting)
}.otherwise {
when(accessRegIsCustom) {
ctrlStateNxt := CtrlState(Custom)
}.otherwise {
ctrlStateNxt := CtrlState(Exec)
goAbstract := true.B
}
}
}.elsewhen (ctrlStateReg === CtrlState(Exec)) {
// We can't just look at 'hartHalted' here, because
// hartHaltedWrEn is overloaded to mean 'got an ebreak'
// which may have happened when we were already halted.
when(goReg === false.B && hartHaltedWrEn && (hartSelFuncs.hartIdToHartSel(hartHaltedId) === selectedHartReg)){
ctrlStateNxt := CtrlState(Waiting)
}
when(hartExceptionWrEn) {
assert(hartExceptionId === 0.U, "Unexpected 'EXCEPTION' hart")//Chisel3 #540, %x, expected %x", hartExceptionId, 0.U)
ctrlStateNxt := CtrlState(Waiting)
errorException := true.B
}
}.elsewhen (ctrlStateReg === CtrlState(Custom)) {
assert(needCustom.B, "Should not be in custom state unless we need it.")
goCustom := true.B
val (custom, customP) = customNode.in.head
when (custom.ready && custom.valid) {
ctrlStateNxt := CtrlState(Waiting)
}
}
when (~io.dmactive || ~dmAuthenticated) {
ctrlStateReg := CtrlState(Waiting)
}.otherwise {
ctrlStateReg := ctrlStateNxt
}
assert ((!io.dmactive || !hartExceptionWrEn || ctrlStateReg === CtrlState(Exec)),
"Unexpected EXCEPTION write: should only get it in Debug Module EXEC state")
}
}
// Wrapper around TL Debug Module Inner and an Async DMI Sink interface.
// Handles the synchronization of dmactive, which is used as a synchronous reset
// inside the Inner block.
// Also is the Sink side of hartsel & resumereq fields of DMCONTROL.
class TLDebugModuleInnerAsync(device: Device, getNComponents: () => Int, beatBytes: Int)(implicit p: Parameters) extends LazyModule{
val cfg = p(DebugModuleKey).get
val dmInner = LazyModule(new TLDebugModuleInner(device, getNComponents, beatBytes))
val dmiXing = LazyModule(new TLAsyncCrossingSink(AsyncQueueParams.singleton(safe=cfg.crossingHasSafeReset)))
val dmiNode = dmiXing.node
val tlNode = dmInner.tlNode
dmInner.dmiNode := dmiXing.node
// Require that there are no registers in TL interface, so that spurious
// processor accesses to the DM don't need to enable the clock. We don't
// require this property of the SBA, because the debugger is responsible for
// raising dmactive (hence enabling the clock) during these transactions.
require(dmInner.tlNode.concurrency == 0)
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
// Clock/reset domains:
// debug_clock / debug_reset = Debug inner domain
// tl_clock / tl_reset = tilelink domain (External: clock / reset)
//
val io = IO(new Bundle {
val debug_clock = Input(Clock())
val debug_reset = Input(Reset())
val tl_clock = Input(Clock())
val tl_reset = Input(Reset())
// These are all asynchronous and come from Outer
/** reset signal for DM */
val dmactive = Input(Bool())
/** conrol signals for Inner
*
* generated in Outer
*/
val innerCtrl = Flipped(new AsyncBundle(new DebugInternalBundle(getNComponents()), AsyncQueueParams.singleton(safe=cfg.crossingHasSafeReset)))
// This comes from tlClk domain.
/** debug available status */
val debugUnavail = Input(Vec(getNComponents(), Bool()))
/** debug interruption*/
val hgDebugInt = Output(Vec(getNComponents(), Bool()))
val extTrigger = (p(DebugModuleKey).get.nExtTriggers > 0).option(new DebugExtTriggerIO())
/** vector to indicate which hart is in reset
*
* dm receives it from core and sends it to Inner
*/
val hartIsInReset = Input(Vec(getNComponents(), Bool()))
/** Debug Authentication signals from core */
val auth = p(DebugModuleKey).get.hasAuthentication.option(new DebugAuthenticationIO())
})
val rf_reset = IO(Input(Reset())) // RF transform
childClock := io.debug_clock
childReset := io.debug_reset
override def provideImplicitClockToLazyChildren = true
val dmactive_synced = withClockAndReset(childClock, childReset) {
val dmactive_synced = AsyncResetSynchronizerShiftReg(in=io.dmactive, sync=3, name=Some("dmactiveSync"))
dmInner.module.clock := io.debug_clock
dmInner.module.reset := io.debug_reset
dmInner.module.io.tl_clock := io.tl_clock
dmInner.module.io.tl_reset := io.tl_reset
dmInner.module.io.dmactive := dmactive_synced
dmInner.module.io.innerCtrl <> FromAsyncBundle(io.innerCtrl)
dmInner.module.io.debugUnavail := io.debugUnavail
io.hgDebugInt := dmInner.module.io.hgDebugInt
io.extTrigger.foreach { x => dmInner.module.io.extTrigger.foreach {y => x <> y}}
dmInner.module.io.hartIsInReset := io.hartIsInReset
io.auth.foreach { x => dmInner.module.io.auth.foreach {y => x <> y}}
dmactive_synced
}
}
}
/** Create a version of the TLDebugModule which includes a synchronization interface
* internally for the DMI. This is no longer optional outside of this module
* because the Clock must run when tl_clock isn't running or tl_reset is asserted.
*/
class TLDebugModule(beatBytes: Int)(implicit p: Parameters) extends LazyModule {
val device = new SimpleDevice("debug-controller", Seq("sifive,debug-013","riscv,debug-013")){
override val alwaysExtended = true
override def describe(resources: ResourceBindings): Description = {
val Description(name, mapping) = super.describe(resources)
val attach = Map(
"debug-attach" -> (
(if (p(ExportDebug).apb) Seq(ResourceString("apb")) else Seq()) ++
(if (p(ExportDebug).jtag) Seq(ResourceString("jtag")) else Seq()) ++
(if (p(ExportDebug).cjtag) Seq(ResourceString("cjtag")) else Seq()) ++
(if (p(ExportDebug).dmi) Seq(ResourceString("dmi")) else Seq())))
Description(name, mapping ++ attach)
}
}
val dmOuter : TLDebugModuleOuterAsync = LazyModule(new TLDebugModuleOuterAsync(device)(p))
val dmInner : TLDebugModuleInnerAsync = LazyModule(new TLDebugModuleInnerAsync(device, () => {dmOuter.dmOuter.intnode.edges.out.size}, beatBytes)(p))
val node = dmInner.tlNode
val intnode = dmOuter.intnode
val apbNodeOpt = dmOuter.apbNodeOpt
dmInner.dmiNode := dmOuter.dmiInnerNode
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
val nComponents = dmOuter.dmOuter.intnode.edges.out.size
// Clock/reset domains:
// tl_clock / tl_reset = tilelink domain
// debug_clock / debug_reset = Inner debug (synchronous to tl_clock)
// apb_clock / apb_reset = Outer debug with APB
// dmiClock / dmiReset = Outer debug without APB
//
val io = IO(new Bundle {
val debug_clock = Input(Clock())
val debug_reset = Input(Reset())
val tl_clock = Input(Clock())
val tl_reset = Input(Reset())
/** Debug control signals generated in Outer */
val ctrl = new DebugCtrlBundle(nComponents)
/** Debug Module Interface bewteen DM and DTM
*
* The DTM provides access to one or more Debug Modules (DMs) using DMI
*/
val dmi = (!p(ExportDebug).apb).option(Flipped(new ClockedDMIIO()))
val apb_clock = p(ExportDebug).apb.option(Input(Clock()))
val apb_reset = p(ExportDebug).apb.option(Input(Reset()))
val extTrigger = (p(DebugModuleKey).get.nExtTriggers > 0).option(new DebugExtTriggerIO())
/** vector to indicate which hart is in reset
*
* dm receives it from core and sends it to Inner
*/
val hartIsInReset = Input(Vec(nComponents, Bool()))
/** hart reset request generated by hartreset-logic in Outer */
val hartResetReq = p(DebugModuleKey).get.hasHartResets.option(Output(Vec(nComponents, Bool())))
/** Debug Authentication signals from core */
val auth = p(DebugModuleKey).get.hasAuthentication.option(new DebugAuthenticationIO())
})
childClock := io.tl_clock
childReset := io.tl_reset
override def provideImplicitClockToLazyChildren = true
dmOuter.module.io.dmi.foreach { dmOuterDMI =>
dmOuterDMI <> io.dmi.get.dmi
dmOuter.module.io.dmi_reset := io.dmi.get.dmiReset
dmOuter.module.io.dmi_clock := io.dmi.get.dmiClock
dmOuter.module.rf_reset := io.dmi.get.dmiReset
}
(io.apb_clock zip io.apb_reset) foreach { case (c, r) =>
dmOuter.module.io.dmi_reset := r
dmOuter.module.io.dmi_clock := c
dmOuter.module.rf_reset := r
}
dmInner.module.rf_reset := io.debug_reset
dmInner.module.io.debug_clock := io.debug_clock
dmInner.module.io.debug_reset := io.debug_reset
dmInner.module.io.tl_clock := io.tl_clock
dmInner.module.io.tl_reset := io.tl_reset
dmInner.module.io.innerCtrl <> dmOuter.module.io.innerCtrl
dmInner.module.io.dmactive := dmOuter.module.io.ctrl.dmactive
dmInner.module.io.debugUnavail := io.ctrl.debugUnavail
dmOuter.module.io.hgDebugInt := dmInner.module.io.hgDebugInt
io.ctrl <> dmOuter.module.io.ctrl
io.extTrigger.foreach { x => dmInner.module.io.extTrigger.foreach {y => x <> y}}
dmInner.module.io.hartIsInReset := io.hartIsInReset
io.hartResetReq.foreach { x => dmOuter.module.io.hartResetReq.foreach {y => x := y}}
io.auth.foreach { x => dmOuter.module.io.dmAuthenticated.get := x.dmAuthenticated }
io.auth.foreach { x => dmInner.module.io.auth.foreach {y => x <> y}}
}
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
File SBA.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.devices.debug.systembusaccess
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.amba.{AMBAProt, AMBAProtField}
import freechips.rocketchip.devices.debug.{DebugModuleKey, RWNotify, SBCSFields, WNotifyVal}
import freechips.rocketchip.diplomacy.TransferSizes
import freechips.rocketchip.regmapper.{RegField, RegFieldDesc, RegFieldGroup, RegFieldWrType}
import freechips.rocketchip.tilelink.{TLClientNode, TLMasterParameters, TLMasterPortParameters}
import freechips.rocketchip.util.property
object SystemBusAccessState extends scala.Enumeration {
type SystemBusAccessState = Value
val Idle, SBReadRequest, SBWriteRequest, SBReadResponse, SBWriteResponse = Value
}
object SBErrorCode extends scala.Enumeration {
type SBErrorCode = Value
val NoError = Value(0)
val Timeout = Value(1)
val BadAddr = Value(2)
val AlgnError = Value(3)
val BadAccess = Value(4)
val OtherError = Value(7)
}
object SystemBusAccessModule
{
def apply(sb2tl: SBToTL, dmactive: Bool, dmAuthenticated: Bool)(implicit p: Parameters):
(Seq[RegField], Seq[Seq[RegField]], Seq[Seq[RegField]]) =
{
import SBErrorCode._
val cfg = p(DebugModuleKey).get
val anyAddressWrEn = WireInit(false.B).suggestName("anyAddressWrEn")
val anyDataRdEn = WireInit(false.B).suggestName("anyDataRdEn")
val anyDataWrEn = WireInit(false.B).suggestName("anyDataWrEn")
// --- SBCS Status Register ---
val SBCSFieldsReg = Reg(new SBCSFields()).suggestName("SBCSFieldsReg")
val SBCSFieldsRegReset = WireInit(0.U.asTypeOf(new SBCSFields()))
SBCSFieldsRegReset.sbversion := 1.U(1.W) // This code implements a version of the spec after January 1, 2018
SBCSFieldsRegReset.sbbusy := (sb2tl.module.io.sbStateOut =/= SystemBusAccessState.Idle.id.U)
SBCSFieldsRegReset.sbaccess := 2.U
SBCSFieldsRegReset.sbasize := sb2tl.module.edge.bundle.addressBits.U
SBCSFieldsRegReset.sbaccess128 := (cfg.maxSupportedSBAccess == 128).B
SBCSFieldsRegReset.sbaccess64 := (cfg.maxSupportedSBAccess >= 64).B
SBCSFieldsRegReset.sbaccess32 := (cfg.maxSupportedSBAccess >= 32).B
SBCSFieldsRegReset.sbaccess16 := (cfg.maxSupportedSBAccess >= 16).B
SBCSFieldsRegReset.sbaccess8 := (cfg.maxSupportedSBAccess >= 8).B
val SBCSRdData = WireInit(0.U.asTypeOf(new SBCSFields())).suggestName("SBCSRdData")
val SBCSWrDataVal = WireInit(0.U(32.W))
val SBCSWrData = WireInit(SBCSWrDataVal.asTypeOf(new SBCSFields()))
val sberrorWrEn = WireInit(false.B)
val sbreadondataWrEn = WireInit(false.B)
val sbautoincrementWrEn= WireInit(false.B)
val sbaccessWrEn = WireInit(false.B)
val sbreadonaddrWrEn = WireInit(false.B)
val sbbusyerrorWrEn = WireInit(false.B)
val sbcsfields = RegFieldGroup("sbcs", Some("system bus access control and status"), Seq(
RegField.r(1, SBCSRdData.sbaccess8, RegFieldDesc("sbaccess8", "8-bit accesses supported", reset=Some(if (cfg.maxSupportedSBAccess >= 8) 1 else 0))),
RegField.r(1, SBCSRdData.sbaccess16, RegFieldDesc("sbaccess16", "16-bit accesses supported", reset=Some(if (cfg.maxSupportedSBAccess >= 16) 1 else 0))),
RegField.r(1, SBCSRdData.sbaccess32, RegFieldDesc("sbaccess32", "32-bit accesses supported", reset=Some(if (cfg.maxSupportedSBAccess >= 32) 1 else 0))),
RegField.r(1, SBCSRdData.sbaccess64, RegFieldDesc("sbaccess64", "64-bit accesses supported", reset=Some(if (cfg.maxSupportedSBAccess >= 64) 1 else 0))),
RegField.r(1, SBCSRdData.sbaccess128, RegFieldDesc("sbaccess128", "128-bit accesses supported", reset=Some(if (cfg.maxSupportedSBAccess == 128) 1 else 0))),
RegField.r(7, SBCSRdData.sbasize, RegFieldDesc("sbasize", "bits in address", reset=Some(sb2tl.module.edge.bundle.addressBits))),
WNotifyVal(3, SBCSRdData.sberror, SBCSWrData.sberror, sberrorWrEn,
RegFieldDesc("sberror", "system bus error", reset=Some(0), wrType=Some(RegFieldWrType.ONE_TO_CLEAR))),
WNotifyVal(1, SBCSRdData.sbreadondata, SBCSWrData.sbreadondata, sbreadondataWrEn,
RegFieldDesc("sbreadondata", "system bus read on data", reset=Some(0))),
WNotifyVal(1, SBCSRdData.sbautoincrement, SBCSWrData.sbautoincrement, sbautoincrementWrEn,
RegFieldDesc("sbautoincrement", "system bus auto-increment address", reset=Some(0))),
WNotifyVal(3, SBCSRdData.sbaccess, SBCSWrData.sbaccess, sbaccessWrEn,
RegFieldDesc("sbaccess", "system bus access size", reset=Some(2))),
WNotifyVal(1, SBCSRdData.sbreadonaddr, SBCSWrData.sbreadonaddr, sbreadonaddrWrEn,
RegFieldDesc("sbreadonaddr", "system bus read on data", reset=Some(0))),
RegField.r(1, SBCSRdData.sbbusy, RegFieldDesc("sbbusy", "system bus access is busy", reset=Some(0))),
WNotifyVal(1, SBCSRdData.sbbusyerror, SBCSWrData.sbbusyerror, sbbusyerrorWrEn,
RegFieldDesc("sbbusyerror", "system bus busy error", reset=Some(0), wrType=Some(RegFieldWrType.ONE_TO_CLEAR))),
RegField(6),
RegField.r(3, SBCSRdData.sbversion, RegFieldDesc("sbversion", "system bus access version", reset=Some(1))),
))
// --- System Bus Address Registers ---
// ADDR0 Register is required
// Instantiate ADDR1-3 registers as needed depending on system bus address width
val hasSBAddr1 = (sb2tl.module.edge.bundle.addressBits >= 33)
val hasSBAddr2 = (sb2tl.module.edge.bundle.addressBits >= 65)
val hasSBAddr3 = (sb2tl.module.edge.bundle.addressBits >= 97)
val hasAddr = Seq(true, hasSBAddr1, hasSBAddr2, hasSBAddr3)
val SBADDRESSFieldsReg = Reg(Vec(4, UInt(32.W)))
SBADDRESSFieldsReg.zipWithIndex.foreach { case(a,i) => a.suggestName("SBADDRESS"+i+"FieldsReg")}
val SBADDRESSWrData = WireInit(VecInit(Seq.fill(4) {0.U(32.W)} ))
val SBADDRESSRdEn = WireInit(VecInit(Seq.fill(4) {false.B} ))
val SBADDRESSWrEn = WireInit(VecInit(Seq.fill(4) {false.B} ))
val autoIncrementedAddr = WireInit(0.U(128.W))
autoIncrementedAddr := Cat(SBADDRESSFieldsReg.reverse) + (1.U << SBCSFieldsReg.sbaccess)
autoIncrementedAddr.suggestName("autoIncrementedAddr")
val sbaddrfields: Seq[Seq[RegField]] = SBADDRESSFieldsReg.zipWithIndex.map { case(a,i) =>
if(hasAddr(i)) {
when (~dmactive || ~dmAuthenticated) {
a := 0.U(32.W)
}.otherwise {
a := Mux(SBADDRESSWrEn(i) && !SBCSRdData.sberror && !SBCSFieldsReg.sbbusy && !SBCSFieldsReg.sbbusyerror, SBADDRESSWrData(i),
Mux((sb2tl.module.io.rdDone || sb2tl.module.io.wrDone) && SBCSFieldsReg.sbautoincrement, autoIncrementedAddr(32*i+31,32*i), a))
}
RegFieldGroup("dmi_sbaddr"+i, Some("SBA Address Register"), Seq(RWNotify(32, a, SBADDRESSWrData(i), SBADDRESSRdEn(i), SBADDRESSWrEn(i),
Some(RegFieldDesc("dmi_sbaddr"+i, "SBA address register", reset=Some(0), volatile=true)))))
} else {
a := DontCare
Seq.empty[RegField]
}
}
sb2tl.module.io.addrIn := Mux(SBADDRESSWrEn(0),
Cat(Cat(SBADDRESSFieldsReg.drop(1).reverse), SBADDRESSWrData(0)),
Cat(SBADDRESSFieldsReg.reverse))
anyAddressWrEn := SBADDRESSWrEn.reduce(_ || _)
// --- System Bus Data Registers ---
// DATA0 Register is required
// DATA1-3 Registers may not be needed depending on implementation
val hasSBData1 = (cfg.maxSupportedSBAccess > 32)
val hasSBData2And3 = (cfg.maxSupportedSBAccess == 128)
val hasData = Seq(true, hasSBData1, hasSBData2And3, hasSBData2And3)
val SBDATAFieldsReg = Reg(Vec(4, Vec(4, UInt(8.W))))
SBDATAFieldsReg.zipWithIndex.foreach { case(d,i) => d.zipWithIndex.foreach { case(d,j) => d.suggestName("SBDATA"+i+"BYTE"+j) }}
val SBDATARdData = WireInit(VecInit(Seq.fill(4) {0.U(32.W)} ))
SBDATARdData.zipWithIndex.foreach { case(d,i) => d.suggestName("SBDATARdData"+i) }
val SBDATAWrData = WireInit(VecInit(Seq.fill(4) {0.U(32.W)} ))
SBDATAWrData.zipWithIndex.foreach { case(d,i) => d.suggestName("SBDATAWrData"+i) }
val SBDATARdEn = WireInit(VecInit(Seq.fill(4) {false.B} ))
val SBDATAWrEn = WireInit(VecInit(Seq.fill(4) {false.B} ))
SBDATAWrEn.zipWithIndex.foreach { case(d,i) => d.suggestName("SBDATAWrEn"+i) }
val sbdatafields: Seq[Seq[RegField]] = SBDATAFieldsReg.zipWithIndex.map { case(d,i) =>
if(hasData(i)) {
// For data registers, load enable per-byte
for (j <- 0 to 3) {
when (~dmactive || ~dmAuthenticated) {
d(j) := 0.U(8.W)
}.otherwise {
d(j) := Mux(SBDATAWrEn(i) && !SBCSFieldsReg.sbbusy && !SBCSFieldsReg.sbbusyerror && !SBCSRdData.sberror, SBDATAWrData(i)(8*j+7,8*j),
Mux(sb2tl.module.io.rdLoad(4*i+j), sb2tl.module.io.dataOut, d(j)))
}
}
SBDATARdData(i) := Cat(d.reverse)
RegFieldGroup("dmi_sbdata"+i, Some("SBA Data Register"), Seq(RWNotify(32, SBDATARdData(i), SBDATAWrData(i), SBDATARdEn(i), SBDATAWrEn(i),
Some(RegFieldDesc("dmi_sbdata"+i, "SBA data register", reset=Some(0), volatile=true)))))
} else {
for (j <- 0 to 3) { d(j) := DontCare }
Seq.empty[RegField]
}
}
sb2tl.module.io.dataIn := Mux(sb2tl.module.io.wrEn,Cat(SBDATAWrData.reverse),Cat(SBDATAFieldsReg.flatten.reverse))
anyDataRdEn := SBDATARdEn.reduce(_ || _)
anyDataWrEn := SBDATAWrEn.reduce(_ || _)
val tryWrEn = SBDATAWrEn(0)
val tryRdEn = (SBADDRESSWrEn(0) && SBCSFieldsReg.sbreadonaddr) || (SBDATARdEn(0) && SBCSFieldsReg.sbreadondata)
val sbAccessError = (SBCSFieldsReg.sbaccess === 0.U) && (SBCSFieldsReg.sbaccess8 =/= 1.U) ||
(SBCSFieldsReg.sbaccess === 1.U) && (SBCSFieldsReg.sbaccess16 =/= 1.U) ||
(SBCSFieldsReg.sbaccess === 2.U) && (SBCSFieldsReg.sbaccess32 =/= 1.U) ||
(SBCSFieldsReg.sbaccess === 3.U) && (SBCSFieldsReg.sbaccess64 =/= 1.U) ||
(SBCSFieldsReg.sbaccess === 4.U) && (SBCSFieldsReg.sbaccess128 =/= 1.U) || (SBCSFieldsReg.sbaccess > 4.U)
val compareAddr = Wire(UInt(32.W)) // Need use written or latched address to detect error case depending on how transaction is initiated
compareAddr := Mux(SBADDRESSWrEn(0),SBADDRESSWrData(0),SBADDRESSFieldsReg(0))
val sbAlignmentError = (SBCSFieldsReg.sbaccess === 1.U) && (compareAddr(0) =/= 0.U) ||
(SBCSFieldsReg.sbaccess === 2.U) && (compareAddr(1,0) =/= 0.U) ||
(SBCSFieldsReg.sbaccess === 3.U) && (compareAddr(2,0) =/= 0.U) ||
(SBCSFieldsReg.sbaccess === 4.U) && (compareAddr(3,0) =/= 0.U)
sbAccessError.suggestName("sbAccessError")
sbAlignmentError.suggestName("sbAlignmentError")
sb2tl.module.io.wrEn := dmAuthenticated && tryWrEn && !SBCSFieldsReg.sbbusy && !SBCSFieldsReg.sbbusyerror && !SBCSRdData.sberror && !sbAccessError && !sbAlignmentError
sb2tl.module.io.rdEn := dmAuthenticated && tryRdEn && !SBCSFieldsReg.sbbusy && !SBCSFieldsReg.sbbusyerror && !SBCSRdData.sberror && !sbAccessError && !sbAlignmentError
sb2tl.module.io.sizeIn := SBCSFieldsReg.sbaccess
val sbBusy = (sb2tl.module.io.sbStateOut =/= SystemBusAccessState.Idle.id.U)
when (~dmactive || ~dmAuthenticated) {
SBCSFieldsReg := SBCSFieldsRegReset
}.otherwise {
SBCSFieldsReg.sbbusyerror := Mux(sbbusyerrorWrEn && SBCSWrData.sbbusyerror, false.B, // W1C
Mux(anyAddressWrEn && sbBusy, true.B, // Set if a write to SBADDRESS occurs while busy
Mux((anyDataRdEn || anyDataWrEn) && sbBusy, true.B, SBCSFieldsReg.sbbusyerror))) // Set if any access to SBDATA occurs while busy
SBCSFieldsReg.sbreadonaddr := Mux(sbreadonaddrWrEn, SBCSWrData.sbreadonaddr , SBCSFieldsReg.sbreadonaddr)
SBCSFieldsReg.sbautoincrement := Mux(sbautoincrementWrEn, SBCSWrData.sbautoincrement, SBCSFieldsReg.sbautoincrement)
SBCSFieldsReg.sbreadondata := Mux(sbreadondataWrEn, SBCSWrData.sbreadondata , SBCSFieldsReg.sbreadondata)
SBCSFieldsReg.sbaccess := Mux(sbaccessWrEn, SBCSWrData.sbaccess, SBCSFieldsReg.sbaccess)
SBCSFieldsReg.sbversion := 1.U(1.W) // This code implements a version of the spec after January 1, 2018
}
// sbErrorReg has a per-bit load enable since each bit can be individually cleared by writing a 1 to it
val sbErrorReg = Reg(Vec(4, UInt(1.W)))
when(~dmactive || ~dmAuthenticated) {
for (i <- 0 until 3)
sbErrorReg(i) := 0.U
}.otherwise {
for (i <- 0 until 3)
sbErrorReg(i) := Mux(sberrorWrEn && SBCSWrData.sberror(i) === 1.U, NoError.id.U.extract(i), // W1C
Mux((sb2tl.module.io.wrEn && !sb2tl.module.io.wrLegal) || (sb2tl.module.io.rdEn && !sb2tl.module.io.rdLegal), BadAddr.id.U.extract(i), // Bad address accessed
Mux((tryWrEn || tryRdEn) && sbAlignmentError, AlgnError.id.U.extract(i), // Address alignment error
Mux((tryWrEn || tryRdEn) && sbAccessError, BadAccess.id.U.extract(i), // Access size error
Mux((sb2tl.module.io.rdDone || sb2tl.module.io.wrDone) && sb2tl.module.io.respError, OtherError.id.U.extract(i), sbErrorReg(i)))))) // Response error from TL
}
SBCSRdData := SBCSFieldsReg
SBCSRdData.sbasize := sb2tl.module.edge.bundle.addressBits.U
SBCSRdData.sbaccess128 := (cfg.maxSupportedSBAccess == 128).B
SBCSRdData.sbaccess64 := (cfg.maxSupportedSBAccess >= 64).B
SBCSRdData.sbaccess32 := (cfg.maxSupportedSBAccess >= 32).B
SBCSRdData.sbaccess16 := (cfg.maxSupportedSBAccess >= 16).B
SBCSRdData.sbaccess8 := (cfg.maxSupportedSBAccess >= 8).B
SBCSRdData.sbbusy := sbBusy
SBCSRdData.sberror := sbErrorReg.asUInt
when (~dmAuthenticated) { // Read value must be 0 if not authenticated
SBCSRdData := 0.U.asTypeOf(new SBCSFields())
}
property.cover(SBCSFieldsReg.sbbusyerror, "SBCS Cover", "sberror set")
property.cover(SBCSFieldsReg.sbbusy === 3.U, "SBCS Cover", "sbbusyerror alignment error")
property.cover((sb2tl.module.io.wrEn || sb2tl.module.io.rdEn) && SBCSFieldsReg.sbaccess === 0.U && !sbAccessError && !sbAlignmentError, "SBCS Cover", "8-bit access")
property.cover((sb2tl.module.io.wrEn || sb2tl.module.io.rdEn) && SBCSFieldsReg.sbaccess === 1.U && !sbAccessError && !sbAlignmentError, "SBCS Cover", "16-bit access")
property.cover((sb2tl.module.io.wrEn || sb2tl.module.io.rdEn) && SBCSFieldsReg.sbaccess === 2.U && !sbAccessError && !sbAlignmentError, "SBCS Cover", "32-bit access")
property.cover((sb2tl.module.io.wrEn || sb2tl.module.io.rdEn) && SBCSFieldsReg.sbaccess === 3.U && !sbAccessError && !sbAlignmentError, "SBCS Cover", "64-bit access")
property.cover((sb2tl.module.io.wrEn || sb2tl.module.io.rdEn) && SBCSFieldsReg.sbaccess === 4.U && !sbAccessError && !sbAlignmentError, "SBCS Cover", "128-bit access")
property.cover(SBCSFieldsReg.sbautoincrement && SBCSFieldsReg.sbbusy, "SBCS Cover", "Access with autoincrement set")
property.cover(!SBCSFieldsReg.sbautoincrement && SBCSFieldsReg.sbbusy, "SBCS Cover", "Access without autoincrement set")
property.cover((sb2tl.module.io.wrEn || sb2tl.module.io.rdEn) && SBCSFieldsReg.sbaccess > 4.U, "SBCS Cover", "Invalid sbaccess value")
(sbcsfields, sbaddrfields, sbdatafields)
}
}
class SBToTL(implicit p: Parameters) extends LazyModule {
val cfg = p(DebugModuleKey).get
val node = TLClientNode(Seq(TLMasterPortParameters.v1(
clients = Seq(TLMasterParameters.v1("debug")),
requestFields = Seq(AMBAProtField()))))
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
val io = IO(new Bundle {
val rdEn = Input(Bool())
val wrEn = Input(Bool())
val addrIn = Input(UInt(128.W)) // TODO: Parameterize these widths
val dataIn = Input(UInt(128.W))
val sizeIn = Input(UInt(3.W))
val rdLegal = Output(Bool())
val wrLegal = Output(Bool())
val rdDone = Output(Bool())
val wrDone = Output(Bool())
val respError = Output(Bool())
val dataOut = Output(UInt(8.W))
val rdLoad = Output(Vec(cfg.maxSupportedSBAccess/8, Bool()))
val sbStateOut = Output(UInt(log2Ceil(SystemBusAccessState.maxId).W))
})
val rf_reset = IO(Input(Reset()))
import SystemBusAccessState._
val (tl, edge) = node.out(0)
val sbState = RegInit(0.U)
// --- Drive payloads on bus to TileLink ---
val d = Queue(tl.d, 2) // Add a small buffer since response could arrive on same cycle as request
d.ready := (sbState === SBReadResponse.id.U) || (sbState === SBWriteResponse.id.U)
val muxedData = WireInit(0.U(8.W))
val requestValid = tl.a.valid
val requestReady = tl.a.ready
val responseValid = d.valid
val responseReady = d.ready
val counter = RegInit(0.U((log2Ceil(cfg.maxSupportedSBAccess/8)+1).W))
val vecData = Wire(Vec(cfg.maxSupportedSBAccess/8, UInt(8.W)))
vecData.zipWithIndex.map { case (vd, i) => vd := io.dataIn(8*i+7,8*i) }
muxedData := vecData(counter(log2Ceil(vecData.size)-1,0))
// Need an additional check to determine if address is safe for Get/Put
val rdLegal_addr = edge.manager.supportsGetSafe(io.addrIn, io.sizeIn, Some(TransferSizes(1,cfg.maxSupportedSBAccess/8)))
val wrLegal_addr = edge.manager.supportsPutFullSafe(io.addrIn, io.sizeIn, Some(TransferSizes(1,cfg.maxSupportedSBAccess/8)))
val (_, gbits) = edge.Get(0.U, io.addrIn, io.sizeIn)
val (_, pfbits) = edge.Put(0.U, io.addrIn, io.sizeIn, muxedData)
io.rdLegal := rdLegal_addr
io.wrLegal := wrLegal_addr
io.sbStateOut := sbState
when(sbState === SBReadRequest.id.U) { tl.a.bits := gbits }
.otherwise { tl.a.bits := pfbits }
tl.a.bits.user.lift(AMBAProt).foreach { x =>
x.bufferable := false.B
x.modifiable := false.B
x.readalloc := false.B
x.writealloc := false.B
x.privileged := true.B
x.secure := true.B
x.fetch := false.B
}
val respError = d.bits.denied || d.bits.corrupt
io.respError := respError
val wrTxValid = sbState === SBWriteRequest.id.U && requestValid && requestReady
val rdTxValid = sbState === SBReadResponse.id.U && responseValid && responseReady
val txLast = counter === ((1.U << io.sizeIn) - 1.U)
counter := Mux((wrTxValid || rdTxValid) && txLast, 0.U,
Mux((wrTxValid || rdTxValid) , counter+1.U, counter))
for (i <- 0 until (cfg.maxSupportedSBAccess/8)) {
io.rdLoad(i) := rdTxValid && (counter === i.U)
}
// --- State Machine to interface with TileLink ---
when (sbState === Idle.id.U){
sbState := Mux(io.rdEn && io.rdLegal, SBReadRequest.id.U,
Mux(io.wrEn && io.wrLegal, SBWriteRequest.id.U, sbState))
}.elsewhen (sbState === SBReadRequest.id.U){
sbState := Mux(requestValid && requestReady, SBReadResponse.id.U, sbState)
}.elsewhen (sbState === SBWriteRequest.id.U){
sbState := Mux(wrTxValid && txLast, SBWriteResponse.id.U, sbState)
}.elsewhen (sbState === SBReadResponse.id.U){
sbState := Mux(rdTxValid && txLast, Idle.id.U, sbState)
}.elsewhen (sbState === SBWriteResponse.id.U){
sbState := Mux(responseValid && responseReady, Idle.id.U, sbState)
}
io.rdDone := rdTxValid && txLast
io.wrDone := (sbState === SBWriteResponse.id.U) && responseValid && responseReady
io.dataOut := d.bits.data
tl.a.valid := (sbState === SBReadRequest.id.U) || (sbState === SBWriteRequest.id.U)
// Tie off unused channels
tl.b.ready := false.B
tl.c.valid := false.B
tl.e.valid := false.B
assert (sbState === Idle.id.U ||
sbState === SBReadRequest.id.U ||
sbState === SBWriteRequest.id.U ||
sbState === SBReadResponse.id.U ||
sbState === SBWriteResponse.id.U, "SBA state machine in undefined state")
property.cover (sbState === Idle.id.U, "SBA State Cover", "SBA Access Idle")
property.cover (sbState === SBReadRequest.id.U, "SBA State Cover", "SBA Access Read Req")
property.cover (sbState === SBWriteRequest.id.U, "SBA State Cover", "SBA Access Write Req")
property.cover (sbState === SBReadResponse.id.U, "SBA State Cover", "SBA Access Read Resp")
property.cover (sbState === SBWriteResponse.id.U, "SBA State Cover", "SBA Access Write Resp")
property.cover (io.rdEn && !io.rdLegal, "SB Legality Cover", "SBA Rd Address Illegal")
property.cover (io.wrEn && !io.wrLegal, "SB Legality Cover", "SBA Wr Address Illegal")
}
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLDebugModuleInner( // @[Debug.scala:790:9]
input clock, // @[Debug.scala:790:9]
input reset, // @[Debug.scala:790:9]
input auto_sb2tlOpt_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_sb2tlOpt_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_sb2tlOpt_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_sb2tlOpt_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_sb2tlOpt_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_sb2tlOpt_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_sb2tlOpt_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_sb2tlOpt_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_sb2tlOpt_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_sb2tlOpt_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_sb2tlOpt_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_sb2tlOpt_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_sb2tlOpt_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_sb2tlOpt_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_sb2tlOpt_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_tl_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_tl_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_tl_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [10:0] auto_tl_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [11:0] auto_tl_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_tl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_tl_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_tl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_tl_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_tl_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_tl_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [10:0] auto_tl_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_tl_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_dmi_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_dmi_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_dmi_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_dmi_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_dmi_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input auto_dmi_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [8:0] auto_dmi_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_dmi_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_dmi_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_dmi_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_dmi_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_dmi_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_dmi_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_dmi_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output auto_dmi_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_dmi_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
input io_dmactive, // @[Debug.scala:803:16]
input io_innerCtrl_valid, // @[Debug.scala:803:16]
input io_innerCtrl_bits_resumereq, // @[Debug.scala:803:16]
input [9:0] io_innerCtrl_bits_hartsel, // @[Debug.scala:803:16]
input io_innerCtrl_bits_ackhavereset, // @[Debug.scala:803:16]
input io_innerCtrl_bits_hasel, // @[Debug.scala:803:16]
input io_innerCtrl_bits_hamask_0, // @[Debug.scala:803:16]
input io_innerCtrl_bits_hrmask_0, // @[Debug.scala:803:16]
output io_hgDebugInt_0, // @[Debug.scala:803:16]
input io_hartIsInReset_0, // @[Debug.scala:803:16]
input io_tl_clock, // @[Debug.scala:803:16]
input io_tl_reset // @[Debug.scala:803:16]
);
wire out_front_1_valid; // @[RegisterRouter.scala:87:24]
wire out_front_1_ready; // @[RegisterRouter.scala:87:24]
wire out_1_bits_read; // @[RegisterRouter.scala:87:24]
wire [10:0] out_1_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24]
wire [8:0] in_1_bits_index; // @[RegisterRouter.scala:73:18]
wire in_1_bits_read; // @[RegisterRouter.scala:73:18]
wire [7:0] _accessRegisterCommandReg_WIRE_cmdtype; // @[Debug.scala:1533:71]
wire _accessRegisterCommandReg_WIRE_reserved0; // @[Debug.scala:1533:71]
wire [2:0] _accessRegisterCommandReg_WIRE_size; // @[Debug.scala:1533:71]
wire _accessRegisterCommandReg_WIRE_reserved1; // @[Debug.scala:1533:71]
wire _accessRegisterCommandReg_WIRE_postexec; // @[Debug.scala:1533:71]
wire _accessRegisterCommandReg_WIRE_transfer; // @[Debug.scala:1533:71]
wire _accessRegisterCommandReg_WIRE_write; // @[Debug.scala:1533:71]
wire [15:0] _accessRegisterCommandReg_WIRE_regno; // @[Debug.scala:1533:71]
wire [7:0] _accessRegisterCommandWr_WIRE_cmdtype; // @[Debug.scala:1531:74]
wire _accessRegisterCommandWr_WIRE_reserved0; // @[Debug.scala:1531:74]
wire [2:0] _accessRegisterCommandWr_WIRE_size; // @[Debug.scala:1531:74]
wire _accessRegisterCommandWr_WIRE_reserved1; // @[Debug.scala:1531:74]
wire _accessRegisterCommandWr_WIRE_postexec; // @[Debug.scala:1531:74]
wire _accessRegisterCommandWr_WIRE_transfer; // @[Debug.scala:1531:74]
wire _accessRegisterCommandWr_WIRE_write; // @[Debug.scala:1531:74]
wire [15:0] _accessRegisterCommandWr_WIRE_regno; // @[Debug.scala:1531:74]
wire out_front_valid; // @[RegisterRouter.scala:87:24]
wire out_front_ready; // @[RegisterRouter.scala:87:24]
wire out_bits_read; // @[RegisterRouter.scala:87:24]
wire out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24]
wire [6:0] in_bits_index; // @[RegisterRouter.scala:73:18]
wire in_bits_read; // @[RegisterRouter.scala:73:18]
wire SBDATAWrEn_0; // @[SBA.scala:150:35]
wire [31:0] SBDATARdData_1; // @[SBA.scala:145:35]
wire [31:0] SBDATARdData_0; // @[SBA.scala:145:35]
wire SBADDRESSWrEn_0; // @[SBA.scala:108:38]
wire [7:0] _COMMANDWrData_WIRE_cmdtype; // @[Debug.scala:1280:65]
wire [23:0] _COMMANDWrData_WIRE_control; // @[Debug.scala:1280:65]
wire [15:0] ABSTRACTAUTOWrData_autoexecprogbuf; // @[Debug.scala:1236:41]
wire [31:0] _HALTSUM1RdData_WIRE; // @[Debug.scala:1170:48]
wire _sb2tlOpt_io_rdLegal; // @[Debug.scala:782:52]
wire _sb2tlOpt_io_wrLegal; // @[Debug.scala:782:52]
wire _sb2tlOpt_io_rdDone; // @[Debug.scala:782:52]
wire _sb2tlOpt_io_wrDone; // @[Debug.scala:782:52]
wire _sb2tlOpt_io_respError; // @[Debug.scala:782:52]
wire [7:0] _sb2tlOpt_io_dataOut; // @[Debug.scala:782:52]
wire _sb2tlOpt_io_rdLoad_0; // @[Debug.scala:782:52]
wire _sb2tlOpt_io_rdLoad_1; // @[Debug.scala:782:52]
wire _sb2tlOpt_io_rdLoad_2; // @[Debug.scala:782:52]
wire _sb2tlOpt_io_rdLoad_3; // @[Debug.scala:782:52]
wire _sb2tlOpt_io_rdLoad_4; // @[Debug.scala:782:52]
wire _sb2tlOpt_io_rdLoad_5; // @[Debug.scala:782:52]
wire _sb2tlOpt_io_rdLoad_6; // @[Debug.scala:782:52]
wire _sb2tlOpt_io_rdLoad_7; // @[Debug.scala:782:52]
wire [2:0] _sb2tlOpt_io_sbStateOut; // @[Debug.scala:782:52]
wire auto_sb2tlOpt_out_a_ready_0 = auto_sb2tlOpt_out_a_ready; // @[Debug.scala:790:9]
wire auto_sb2tlOpt_out_d_valid_0 = auto_sb2tlOpt_out_d_valid; // @[Debug.scala:790:9]
wire [2:0] auto_sb2tlOpt_out_d_bits_opcode_0 = auto_sb2tlOpt_out_d_bits_opcode; // @[Debug.scala:790:9]
wire [1:0] auto_sb2tlOpt_out_d_bits_param_0 = auto_sb2tlOpt_out_d_bits_param; // @[Debug.scala:790:9]
wire [3:0] auto_sb2tlOpt_out_d_bits_size_0 = auto_sb2tlOpt_out_d_bits_size; // @[Debug.scala:790:9]
wire [6:0] auto_sb2tlOpt_out_d_bits_sink_0 = auto_sb2tlOpt_out_d_bits_sink; // @[Debug.scala:790:9]
wire auto_sb2tlOpt_out_d_bits_denied_0 = auto_sb2tlOpt_out_d_bits_denied; // @[Debug.scala:790:9]
wire [7:0] auto_sb2tlOpt_out_d_bits_data_0 = auto_sb2tlOpt_out_d_bits_data; // @[Debug.scala:790:9]
wire auto_sb2tlOpt_out_d_bits_corrupt_0 = auto_sb2tlOpt_out_d_bits_corrupt; // @[Debug.scala:790:9]
wire auto_tl_in_a_valid_0 = auto_tl_in_a_valid; // @[Debug.scala:790:9]
wire [2:0] auto_tl_in_a_bits_opcode_0 = auto_tl_in_a_bits_opcode; // @[Debug.scala:790:9]
wire [2:0] auto_tl_in_a_bits_param_0 = auto_tl_in_a_bits_param; // @[Debug.scala:790:9]
wire [1:0] auto_tl_in_a_bits_size_0 = auto_tl_in_a_bits_size; // @[Debug.scala:790:9]
wire [10:0] auto_tl_in_a_bits_source_0 = auto_tl_in_a_bits_source; // @[Debug.scala:790:9]
wire [11:0] auto_tl_in_a_bits_address_0 = auto_tl_in_a_bits_address; // @[Debug.scala:790:9]
wire [7:0] auto_tl_in_a_bits_mask_0 = auto_tl_in_a_bits_mask; // @[Debug.scala:790:9]
wire [63:0] auto_tl_in_a_bits_data_0 = auto_tl_in_a_bits_data; // @[Debug.scala:790:9]
wire auto_tl_in_a_bits_corrupt_0 = auto_tl_in_a_bits_corrupt; // @[Debug.scala:790:9]
wire auto_tl_in_d_ready_0 = auto_tl_in_d_ready; // @[Debug.scala:790:9]
wire auto_dmi_in_a_valid_0 = auto_dmi_in_a_valid; // @[Debug.scala:790:9]
wire [2:0] auto_dmi_in_a_bits_opcode_0 = auto_dmi_in_a_bits_opcode; // @[Debug.scala:790:9]
wire [2:0] auto_dmi_in_a_bits_param_0 = auto_dmi_in_a_bits_param; // @[Debug.scala:790:9]
wire [1:0] auto_dmi_in_a_bits_size_0 = auto_dmi_in_a_bits_size; // @[Debug.scala:790:9]
wire auto_dmi_in_a_bits_source_0 = auto_dmi_in_a_bits_source; // @[Debug.scala:790:9]
wire [8:0] auto_dmi_in_a_bits_address_0 = auto_dmi_in_a_bits_address; // @[Debug.scala:790:9]
wire [3:0] auto_dmi_in_a_bits_mask_0 = auto_dmi_in_a_bits_mask; // @[Debug.scala:790:9]
wire [31:0] auto_dmi_in_a_bits_data_0 = auto_dmi_in_a_bits_data; // @[Debug.scala:790:9]
wire auto_dmi_in_a_bits_corrupt_0 = auto_dmi_in_a_bits_corrupt; // @[Debug.scala:790:9]
wire auto_dmi_in_d_ready_0 = auto_dmi_in_d_ready; // @[Debug.scala:790:9]
wire io_dmactive_0 = io_dmactive; // @[Debug.scala:790:9]
wire io_innerCtrl_valid_0 = io_innerCtrl_valid; // @[Debug.scala:790:9]
wire io_innerCtrl_bits_resumereq_0 = io_innerCtrl_bits_resumereq; // @[Debug.scala:790:9]
wire [9:0] io_innerCtrl_bits_hartsel_0 = io_innerCtrl_bits_hartsel; // @[Debug.scala:790:9]
wire io_innerCtrl_bits_ackhavereset_0 = io_innerCtrl_bits_ackhavereset; // @[Debug.scala:790:9]
wire io_innerCtrl_bits_hasel_0 = io_innerCtrl_bits_hasel; // @[Debug.scala:790:9]
wire io_innerCtrl_bits_hamask_0_0 = io_innerCtrl_bits_hamask_0; // @[Debug.scala:790:9]
wire io_innerCtrl_bits_hrmask_0_0 = io_innerCtrl_bits_hrmask_0; // @[Debug.scala:790:9]
wire io_hartIsInReset_0_0 = io_hartIsInReset_0; // @[Debug.scala:790:9]
wire io_tl_clock_0 = io_tl_clock; // @[Debug.scala:790:9]
wire io_tl_reset_0 = io_tl_reset; // @[Debug.scala:790:9]
wire auto_sb2tlOpt_out_a_bits_source = 1'h0; // @[Debug.scala:790:9]
wire auto_sb2tlOpt_out_a_bits_corrupt = 1'h0; // @[Debug.scala:790:9]
wire auto_sb2tlOpt_out_d_bits_source = 1'h0; // @[Debug.scala:790:9]
wire auto_custom_in_addr = 1'h0; // @[Debug.scala:790:9]
wire auto_custom_in_ready = 1'h0; // @[Debug.scala:790:9]
wire auto_custom_in_valid = 1'h0; // @[Debug.scala:790:9]
wire auto_tl_in_d_bits_sink = 1'h0; // @[Debug.scala:790:9]
wire auto_tl_in_d_bits_denied = 1'h0; // @[Debug.scala:790:9]
wire auto_tl_in_d_bits_corrupt = 1'h0; // @[Debug.scala:790:9]
wire auto_dmi_in_d_bits_sink = 1'h0; // @[Debug.scala:790:9]
wire auto_dmi_in_d_bits_denied = 1'h0; // @[Debug.scala:790:9]
wire auto_dmi_in_d_bits_corrupt = 1'h0; // @[Debug.scala:790:9]
wire io_debugUnavail_0 = 1'h0; // @[Debug.scala:790:9]
wire dmiNodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17]
wire dmiNodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17]
wire dmiNodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire tlNodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17]
wire tlNodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17]
wire tlNodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire customNodeIn_addr = 1'h0; // @[MixedNode.scala:551:17]
wire customNodeIn_ready = 1'h0; // @[MixedNode.scala:551:17]
wire customNodeIn_valid = 1'h0; // @[MixedNode.scala:551:17]
wire _dmiProgramBufferRdEn_WIRE_0 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_1 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_2 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_3 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_4 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_5 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_6 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_7 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_8 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_9 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_10 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_11 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_12 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_13 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_14 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_15 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_16 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_17 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_18 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_19 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_20 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_21 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_22 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_23 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_24 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_25 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_26 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_27 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_28 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_29 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_30 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_31 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_32 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_33 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_34 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_35 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_36 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_37 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_38 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_39 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_40 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_41 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_42 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_43 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_44 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_45 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_46 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_47 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_48 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_49 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_50 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_51 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_52 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_53 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_54 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_55 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_56 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_57 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_58 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_59 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_60 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_61 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_62 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_63 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferWrEnMaybe_WIRE_0 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_1 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_2 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_3 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_4 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_5 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_6 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_7 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_8 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_9 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_10 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_11 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_12 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_13 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_14 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_15 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_16 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_17 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_18 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_19 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_20 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_21 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_22 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_23 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_24 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_25 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_26 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_27 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_28 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_29 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_30 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_31 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_32 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_33 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_34 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_35 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_36 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_37 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_38 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_39 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_40 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_41 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_42 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_43 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_44 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_45 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_46 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_47 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_48 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_49 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_50 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_51 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_52 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_53 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_54 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_55 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_56 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_57 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_58 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_59 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_60 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_61 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_62 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_63 = 1'h0; // @[Debug.scala:889:53]
wire _dmiAbstractDataRdEn_WIRE_0 = 1'h0; // @[Debug.scala:891:47]
wire _dmiAbstractDataRdEn_WIRE_1 = 1'h0; // @[Debug.scala:891:47]
wire _dmiAbstractDataRdEn_WIRE_2 = 1'h0; // @[Debug.scala:891:47]
wire _dmiAbstractDataRdEn_WIRE_3 = 1'h0; // @[Debug.scala:891:47]
wire _dmiAbstractDataRdEn_WIRE_4 = 1'h0; // @[Debug.scala:891:47]
wire _dmiAbstractDataRdEn_WIRE_5 = 1'h0; // @[Debug.scala:891:47]
wire _dmiAbstractDataRdEn_WIRE_6 = 1'h0; // @[Debug.scala:891:47]
wire _dmiAbstractDataRdEn_WIRE_7 = 1'h0; // @[Debug.scala:891:47]
wire _dmiAbstractDataRdEn_WIRE_8 = 1'h0; // @[Debug.scala:891:47]
wire _dmiAbstractDataRdEn_WIRE_9 = 1'h0; // @[Debug.scala:891:47]
wire _dmiAbstractDataRdEn_WIRE_10 = 1'h0; // @[Debug.scala:891:47]
wire _dmiAbstractDataRdEn_WIRE_11 = 1'h0; // @[Debug.scala:891:47]
wire _dmiAbstractDataRdEn_WIRE_12 = 1'h0; // @[Debug.scala:891:47]
wire _dmiAbstractDataRdEn_WIRE_13 = 1'h0; // @[Debug.scala:891:47]
wire _dmiAbstractDataRdEn_WIRE_14 = 1'h0; // @[Debug.scala:891:47]
wire _dmiAbstractDataRdEn_WIRE_15 = 1'h0; // @[Debug.scala:891:47]
wire _dmiAbstractDataRdEn_WIRE_16 = 1'h0; // @[Debug.scala:891:47]
wire _dmiAbstractDataRdEn_WIRE_17 = 1'h0; // @[Debug.scala:891:47]
wire _dmiAbstractDataRdEn_WIRE_18 = 1'h0; // @[Debug.scala:891:47]
wire _dmiAbstractDataRdEn_WIRE_19 = 1'h0; // @[Debug.scala:891:47]
wire _dmiAbstractDataRdEn_WIRE_20 = 1'h0; // @[Debug.scala:891:47]
wire _dmiAbstractDataRdEn_WIRE_21 = 1'h0; // @[Debug.scala:891:47]
wire _dmiAbstractDataRdEn_WIRE_22 = 1'h0; // @[Debug.scala:891:47]
wire _dmiAbstractDataRdEn_WIRE_23 = 1'h0; // @[Debug.scala:891:47]
wire _dmiAbstractDataRdEn_WIRE_24 = 1'h0; // @[Debug.scala:891:47]
wire _dmiAbstractDataRdEn_WIRE_25 = 1'h0; // @[Debug.scala:891:47]
wire _dmiAbstractDataRdEn_WIRE_26 = 1'h0; // @[Debug.scala:891:47]
wire _dmiAbstractDataRdEn_WIRE_27 = 1'h0; // @[Debug.scala:891:47]
wire _dmiAbstractDataRdEn_WIRE_28 = 1'h0; // @[Debug.scala:891:47]
wire _dmiAbstractDataRdEn_WIRE_29 = 1'h0; // @[Debug.scala:891:47]
wire _dmiAbstractDataRdEn_WIRE_30 = 1'h0; // @[Debug.scala:891:47]
wire _dmiAbstractDataRdEn_WIRE_31 = 1'h0; // @[Debug.scala:891:47]
wire _dmiAbstractDataWrEnMaybe_WIRE_0 = 1'h0; // @[Debug.scala:893:52]
wire _dmiAbstractDataWrEnMaybe_WIRE_1 = 1'h0; // @[Debug.scala:893:52]
wire _dmiAbstractDataWrEnMaybe_WIRE_2 = 1'h0; // @[Debug.scala:893:52]
wire _dmiAbstractDataWrEnMaybe_WIRE_3 = 1'h0; // @[Debug.scala:893:52]
wire _dmiAbstractDataWrEnMaybe_WIRE_4 = 1'h0; // @[Debug.scala:893:52]
wire _dmiAbstractDataWrEnMaybe_WIRE_5 = 1'h0; // @[Debug.scala:893:52]
wire _dmiAbstractDataWrEnMaybe_WIRE_6 = 1'h0; // @[Debug.scala:893:52]
wire _dmiAbstractDataWrEnMaybe_WIRE_7 = 1'h0; // @[Debug.scala:893:52]
wire _dmiAbstractDataWrEnMaybe_WIRE_8 = 1'h0; // @[Debug.scala:893:52]
wire _dmiAbstractDataWrEnMaybe_WIRE_9 = 1'h0; // @[Debug.scala:893:52]
wire _dmiAbstractDataWrEnMaybe_WIRE_10 = 1'h0; // @[Debug.scala:893:52]
wire _dmiAbstractDataWrEnMaybe_WIRE_11 = 1'h0; // @[Debug.scala:893:52]
wire _dmiAbstractDataWrEnMaybe_WIRE_12 = 1'h0; // @[Debug.scala:893:52]
wire _dmiAbstractDataWrEnMaybe_WIRE_13 = 1'h0; // @[Debug.scala:893:52]
wire _dmiAbstractDataWrEnMaybe_WIRE_14 = 1'h0; // @[Debug.scala:893:52]
wire _dmiAbstractDataWrEnMaybe_WIRE_15 = 1'h0; // @[Debug.scala:893:52]
wire _dmiAbstractDataWrEnMaybe_WIRE_16 = 1'h0; // @[Debug.scala:893:52]
wire _dmiAbstractDataWrEnMaybe_WIRE_17 = 1'h0; // @[Debug.scala:893:52]
wire _dmiAbstractDataWrEnMaybe_WIRE_18 = 1'h0; // @[Debug.scala:893:52]
wire _dmiAbstractDataWrEnMaybe_WIRE_19 = 1'h0; // @[Debug.scala:893:52]
wire _dmiAbstractDataWrEnMaybe_WIRE_20 = 1'h0; // @[Debug.scala:893:52]
wire _dmiAbstractDataWrEnMaybe_WIRE_21 = 1'h0; // @[Debug.scala:893:52]
wire _dmiAbstractDataWrEnMaybe_WIRE_22 = 1'h0; // @[Debug.scala:893:52]
wire _dmiAbstractDataWrEnMaybe_WIRE_23 = 1'h0; // @[Debug.scala:893:52]
wire _dmiAbstractDataWrEnMaybe_WIRE_24 = 1'h0; // @[Debug.scala:893:52]
wire _dmiAbstractDataWrEnMaybe_WIRE_25 = 1'h0; // @[Debug.scala:893:52]
wire _dmiAbstractDataWrEnMaybe_WIRE_26 = 1'h0; // @[Debug.scala:893:52]
wire _dmiAbstractDataWrEnMaybe_WIRE_27 = 1'h0; // @[Debug.scala:893:52]
wire _dmiAbstractDataWrEnMaybe_WIRE_28 = 1'h0; // @[Debug.scala:893:52]
wire _dmiAbstractDataWrEnMaybe_WIRE_29 = 1'h0; // @[Debug.scala:893:52]
wire _dmiAbstractDataWrEnMaybe_WIRE_30 = 1'h0; // @[Debug.scala:893:52]
wire _dmiAbstractDataWrEnMaybe_WIRE_31 = 1'h0; // @[Debug.scala:893:52]
wire _hamaskFull_WIRE_0 = 1'h0; // @[Debug.scala:903:38]
wire _hamaskWrSel_WIRE_0 = 1'h0; // @[Debug.scala:933:39]
wire _hrReset_WIRE_0 = 1'h0; // @[Debug.scala:945:38]
wire hrReset_0 = 1'h0; // @[Debug.scala:945:30]
wire _hrDebugIntReg_WIRE_0 = 1'h0; // @[Debug.scala:961:42]
wire _DMSTATUSRdData_WIRE_impebreak = 1'h0; // @[Debug.scala:978:47]
wire _DMSTATUSRdData_WIRE_allhavereset = 1'h0; // @[Debug.scala:978:47]
wire _DMSTATUSRdData_WIRE_anyhavereset = 1'h0; // @[Debug.scala:978:47]
wire _DMSTATUSRdData_WIRE_allresumeack = 1'h0; // @[Debug.scala:978:47]
wire _DMSTATUSRdData_WIRE_anyresumeack = 1'h0; // @[Debug.scala:978:47]
wire _DMSTATUSRdData_WIRE_allnonexistent = 1'h0; // @[Debug.scala:978:47]
wire _DMSTATUSRdData_WIRE_anynonexistent = 1'h0; // @[Debug.scala:978:47]
wire _DMSTATUSRdData_WIRE_allunavail = 1'h0; // @[Debug.scala:978:47]
wire _DMSTATUSRdData_WIRE_anyunavail = 1'h0; // @[Debug.scala:978:47]
wire _DMSTATUSRdData_WIRE_allrunning = 1'h0; // @[Debug.scala:978:47]
wire _DMSTATUSRdData_WIRE_anyrunning = 1'h0; // @[Debug.scala:978:47]
wire _DMSTATUSRdData_WIRE_allhalted = 1'h0; // @[Debug.scala:978:47]
wire _DMSTATUSRdData_WIRE_anyhalted = 1'h0; // @[Debug.scala:978:47]
wire _DMSTATUSRdData_WIRE_authenticated = 1'h0; // @[Debug.scala:978:47]
wire _DMSTATUSRdData_WIRE_authbusy = 1'h0; // @[Debug.scala:978:47]
wire _DMSTATUSRdData_WIRE_hasresethaltreq = 1'h0; // @[Debug.scala:978:47]
wire _DMSTATUSRdData_WIRE_confstrptrvalid = 1'h0; // @[Debug.scala:978:47]
wire DMSTATUSRdData_impebreak = 1'h0; // @[Debug.scala:978:34]
wire DMSTATUSRdData_anyunavail = 1'h0; // @[Debug.scala:978:34]
wire DMSTATUSRdData_authbusy = 1'h0; // @[Debug.scala:978:34]
wire DMSTATUSRdData_confstrptrvalid = 1'h0; // @[Debug.scala:978:34]
wire _DMSTATUSRdData_anynonexistent_T = 1'h0; // @[Debug.scala:988:57]
wire _DMSTATUSRdData_allnonexistent_T = 1'h0; // @[Debug.scala:991:57]
wire _DMSTATUSRdData_anyunavail_T = 1'h0; // @[package.scala:74:72]
wire _DMCS2RdData_WIRE_hgwrite = 1'h0; // @[Debug.scala:1025:47]
wire _DMCS2RdData_WIRE_hgselect = 1'h0; // @[Debug.scala:1025:47]
wire DMCS2RdData_hgwrite = 1'h0; // @[Debug.scala:1025:34]
wire DMCS2RdData_hgselect = 1'h0; // @[Debug.scala:1025:34]
wire _DMCS2WrData_WIRE_hgwrite = 1'h0; // @[Debug.scala:1026:47]
wire _DMCS2WrData_WIRE_hgselect = 1'h0; // @[Debug.scala:1026:47]
wire DMCS2WrData_hgwrite = 1'h0; // @[Debug.scala:1026:34]
wire DMCS2WrData_hgselect = 1'h0; // @[Debug.scala:1026:34]
wire hgselectWrEn = 1'h0; // @[Debug.scala:1027:34]
wire hgwriteWrEn = 1'h0; // @[Debug.scala:1028:34]
wire haltgroupWrEn = 1'h0; // @[Debug.scala:1029:34]
wire exttriggerWrEn = 1'h0; // @[Debug.scala:1030:34]
wire _hgDebugInt_WIRE_0 = 1'h0; // @[Debug.scala:1031:42]
wire hgDebugInt_0 = 1'h0; // @[Debug.scala:1031:34]
wire _selectedHaltedStatus_T = 1'h0; // @[Debug.scala:1172:53]
wire _selectedHaltedStatus_T_1 = 1'h0; // @[Debug.scala:1172:59]
wire _selectedHaltedStatus_T_2 = 1'h0; // @[Debug.scala:1172:114]
wire _selectedHaltedStatus_WIRE = 1'h0;
wire _ABSTRACTCSReset_WIRE_busy = 1'h0; // @[Debug.scala:1179:48]
wire _ABSTRACTCSReset_WIRE_reserved2 = 1'h0; // @[Debug.scala:1179:48]
wire ABSTRACTCSReset_busy = 1'h0; // @[Debug.scala:1179:35]
wire ABSTRACTCSReset_reserved2 = 1'h0; // @[Debug.scala:1179:35]
wire _ABSTRACTCSWrData_WIRE_busy = 1'h0; // @[Debug.scala:1184:52]
wire _ABSTRACTCSWrData_WIRE_reserved2 = 1'h0; // @[Debug.scala:1184:52]
wire ABSTRACTCSWrData_busy = 1'h0; // @[Debug.scala:1184:39]
wire ABSTRACTCSWrData_reserved2 = 1'h0; // @[Debug.scala:1184:39]
wire ABSTRACTCSRdData_reserved2 = 1'h0; // @[Debug.scala:1185:39]
wire ABSTRACTCSRdEn = 1'h0; // @[Debug.scala:1187:34]
wire ABSTRACTAUTORdEn = 1'h0; // @[Debug.scala:1239:36]
wire _dmiAbstractDataAccessVec_WIRE_0 = 1'h0; // @[Debug.scala:1257:53]
wire _dmiAbstractDataAccessVec_WIRE_1 = 1'h0; // @[Debug.scala:1257:53]
wire _dmiAbstractDataAccessVec_WIRE_2 = 1'h0; // @[Debug.scala:1257:53]
wire _dmiAbstractDataAccessVec_WIRE_3 = 1'h0; // @[Debug.scala:1257:53]
wire _dmiAbstractDataAccessVec_WIRE_4 = 1'h0; // @[Debug.scala:1257:53]
wire _dmiAbstractDataAccessVec_WIRE_5 = 1'h0; // @[Debug.scala:1257:53]
wire _dmiAbstractDataAccessVec_WIRE_6 = 1'h0; // @[Debug.scala:1257:53]
wire _dmiAbstractDataAccessVec_WIRE_7 = 1'h0; // @[Debug.scala:1257:53]
wire _dmiAbstractDataAccessVec_WIRE_8 = 1'h0; // @[Debug.scala:1257:53]
wire _dmiAbstractDataAccessVec_WIRE_9 = 1'h0; // @[Debug.scala:1257:53]
wire _dmiAbstractDataAccessVec_WIRE_10 = 1'h0; // @[Debug.scala:1257:53]
wire _dmiAbstractDataAccessVec_WIRE_11 = 1'h0; // @[Debug.scala:1257:53]
wire _dmiAbstractDataAccessVec_WIRE_12 = 1'h0; // @[Debug.scala:1257:53]
wire _dmiAbstractDataAccessVec_WIRE_13 = 1'h0; // @[Debug.scala:1257:53]
wire _dmiAbstractDataAccessVec_WIRE_14 = 1'h0; // @[Debug.scala:1257:53]
wire _dmiAbstractDataAccessVec_WIRE_15 = 1'h0; // @[Debug.scala:1257:53]
wire _dmiAbstractDataAccessVec_WIRE_16 = 1'h0; // @[Debug.scala:1257:53]
wire _dmiAbstractDataAccessVec_WIRE_17 = 1'h0; // @[Debug.scala:1257:53]
wire _dmiAbstractDataAccessVec_WIRE_18 = 1'h0; // @[Debug.scala:1257:53]
wire _dmiAbstractDataAccessVec_WIRE_19 = 1'h0; // @[Debug.scala:1257:53]
wire _dmiAbstractDataAccessVec_WIRE_20 = 1'h0; // @[Debug.scala:1257:53]
wire _dmiAbstractDataAccessVec_WIRE_21 = 1'h0; // @[Debug.scala:1257:53]
wire _dmiAbstractDataAccessVec_WIRE_22 = 1'h0; // @[Debug.scala:1257:53]
wire _dmiAbstractDataAccessVec_WIRE_23 = 1'h0; // @[Debug.scala:1257:53]
wire _dmiAbstractDataAccessVec_WIRE_24 = 1'h0; // @[Debug.scala:1257:53]
wire _dmiAbstractDataAccessVec_WIRE_25 = 1'h0; // @[Debug.scala:1257:53]
wire _dmiAbstractDataAccessVec_WIRE_26 = 1'h0; // @[Debug.scala:1257:53]
wire _dmiAbstractDataAccessVec_WIRE_27 = 1'h0; // @[Debug.scala:1257:53]
wire _dmiAbstractDataAccessVec_WIRE_28 = 1'h0; // @[Debug.scala:1257:53]
wire _dmiAbstractDataAccessVec_WIRE_29 = 1'h0; // @[Debug.scala:1257:53]
wire _dmiAbstractDataAccessVec_WIRE_30 = 1'h0; // @[Debug.scala:1257:53]
wire _dmiAbstractDataAccessVec_WIRE_31 = 1'h0; // @[Debug.scala:1257:53]
wire _dmiProgramBufferAccessVec_WIRE_0 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_1 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_2 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_3 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_4 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_5 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_6 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_7 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_8 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_9 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_10 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_11 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_12 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_13 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_14 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_15 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_16 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_17 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_18 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_19 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_20 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_21 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_22 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_23 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_24 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_25 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_26 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_27 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_28 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_29 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_30 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_31 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_32 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_33 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_34 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_35 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_36 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_37 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_38 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_39 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_40 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_41 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_42 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_43 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_44 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_45 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_46 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_47 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_48 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_49 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_50 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_51 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_52 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_53 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_54 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_55 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_56 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_57 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_58 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_59 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_60 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_61 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_62 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_63 = 1'h0; // @[Debug.scala:1260:54]
wire _autoexecData_WIRE_0 = 1'h0; // @[Debug.scala:1267:41]
wire _autoexecData_WIRE_1 = 1'h0; // @[Debug.scala:1267:41]
wire _autoexecData_WIRE_2 = 1'h0; // @[Debug.scala:1267:41]
wire _autoexecData_WIRE_3 = 1'h0; // @[Debug.scala:1267:41]
wire _autoexecData_WIRE_4 = 1'h0; // @[Debug.scala:1267:41]
wire _autoexecData_WIRE_5 = 1'h0; // @[Debug.scala:1267:41]
wire _autoexecData_WIRE_6 = 1'h0; // @[Debug.scala:1267:41]
wire _autoexecData_WIRE_7 = 1'h0; // @[Debug.scala:1267:41]
wire _autoexecProg_WIRE_0 = 1'h0; // @[Debug.scala:1268:41]
wire _autoexecProg_WIRE_1 = 1'h0; // @[Debug.scala:1268:41]
wire _autoexecProg_WIRE_2 = 1'h0; // @[Debug.scala:1268:41]
wire _autoexecProg_WIRE_3 = 1'h0; // @[Debug.scala:1268:41]
wire _autoexecProg_WIRE_4 = 1'h0; // @[Debug.scala:1268:41]
wire _autoexecProg_WIRE_5 = 1'h0; // @[Debug.scala:1268:41]
wire _autoexecProg_WIRE_6 = 1'h0; // @[Debug.scala:1268:41]
wire _autoexecProg_WIRE_7 = 1'h0; // @[Debug.scala:1268:41]
wire _autoexecProg_WIRE_8 = 1'h0; // @[Debug.scala:1268:41]
wire _autoexecProg_WIRE_9 = 1'h0; // @[Debug.scala:1268:41]
wire _autoexecProg_WIRE_10 = 1'h0; // @[Debug.scala:1268:41]
wire _autoexecProg_WIRE_11 = 1'h0; // @[Debug.scala:1268:41]
wire _autoexecProg_WIRE_12 = 1'h0; // @[Debug.scala:1268:41]
wire _autoexecProg_WIRE_13 = 1'h0; // @[Debug.scala:1268:41]
wire _autoexecProg_WIRE_14 = 1'h0; // @[Debug.scala:1268:41]
wire _autoexecProg_WIRE_15 = 1'h0; // @[Debug.scala:1268:41]
wire authRdEnMaybe = 1'h0; // @[Debug.scala:1356:33]
wire authWrEnMaybe = 1'h0; // @[Debug.scala:1357:33]
wire _SBCSFieldsRegReset_WIRE_sbbusyerror = 1'h0; // @[SBA.scala:49:51]
wire _SBCSFieldsRegReset_WIRE_sbbusy = 1'h0; // @[SBA.scala:49:51]
wire _SBCSFieldsRegReset_WIRE_sbreadonaddr = 1'h0; // @[SBA.scala:49:51]
wire _SBCSFieldsRegReset_WIRE_sbautoincrement = 1'h0; // @[SBA.scala:49:51]
wire _SBCSFieldsRegReset_WIRE_sbreadondata = 1'h0; // @[SBA.scala:49:51]
wire _SBCSFieldsRegReset_WIRE_sbaccess128 = 1'h0; // @[SBA.scala:49:51]
wire _SBCSFieldsRegReset_WIRE_sbaccess64 = 1'h0; // @[SBA.scala:49:51]
wire _SBCSFieldsRegReset_WIRE_sbaccess32 = 1'h0; // @[SBA.scala:49:51]
wire _SBCSFieldsRegReset_WIRE_sbaccess16 = 1'h0; // @[SBA.scala:49:51]
wire _SBCSFieldsRegReset_WIRE_sbaccess8 = 1'h0; // @[SBA.scala:49:51]
wire SBCSFieldsRegReset_sbbusyerror = 1'h0; // @[SBA.scala:49:38]
wire SBCSFieldsRegReset_sbreadonaddr = 1'h0; // @[SBA.scala:49:38]
wire SBCSFieldsRegReset_sbautoincrement = 1'h0; // @[SBA.scala:49:38]
wire SBCSFieldsRegReset_sbreadondata = 1'h0; // @[SBA.scala:49:38]
wire SBCSFieldsRegReset_sbaccess128 = 1'h0; // @[SBA.scala:49:38]
wire _SBCSRdData_WIRE_sbbusyerror = 1'h0; // @[SBA.scala:60:51]
wire _SBCSRdData_WIRE_sbbusy = 1'h0; // @[SBA.scala:60:51]
wire _SBCSRdData_WIRE_sbreadonaddr = 1'h0; // @[SBA.scala:60:51]
wire _SBCSRdData_WIRE_sbautoincrement = 1'h0; // @[SBA.scala:60:51]
wire _SBCSRdData_WIRE_sbreadondata = 1'h0; // @[SBA.scala:60:51]
wire _SBCSRdData_WIRE_sbaccess128 = 1'h0; // @[SBA.scala:60:51]
wire _SBCSRdData_WIRE_sbaccess64 = 1'h0; // @[SBA.scala:60:51]
wire _SBCSRdData_WIRE_sbaccess32 = 1'h0; // @[SBA.scala:60:51]
wire _SBCSRdData_WIRE_sbaccess16 = 1'h0; // @[SBA.scala:60:51]
wire _SBCSRdData_WIRE_sbaccess8 = 1'h0; // @[SBA.scala:60:51]
wire SBCSRdData_sbaccess128 = 1'h0; // @[SBA.scala:60:38]
wire _SBCSWrData_WIRE_sbbusyerror = 1'h0; // @[SBA.scala:63:61]
wire _SBCSWrData_WIRE_sbbusy = 1'h0; // @[SBA.scala:63:61]
wire _SBCSWrData_WIRE_sbreadonaddr = 1'h0; // @[SBA.scala:63:61]
wire _SBCSWrData_WIRE_sbautoincrement = 1'h0; // @[SBA.scala:63:61]
wire _SBCSWrData_WIRE_sbreadondata = 1'h0; // @[SBA.scala:63:61]
wire _SBCSWrData_WIRE_sbaccess128 = 1'h0; // @[SBA.scala:63:61]
wire _SBCSWrData_WIRE_sbaccess64 = 1'h0; // @[SBA.scala:63:61]
wire _SBCSWrData_WIRE_sbaccess32 = 1'h0; // @[SBA.scala:63:61]
wire _SBCSWrData_WIRE_sbaccess16 = 1'h0; // @[SBA.scala:63:61]
wire _SBCSWrData_WIRE_sbaccess8 = 1'h0; // @[SBA.scala:63:61]
wire _SBCSWrData_T = 1'h0; // @[SBA.scala:63:61]
wire _SBCSWrData_T_1 = 1'h0; // @[SBA.scala:63:61]
wire _SBCSWrData_T_2 = 1'h0; // @[SBA.scala:63:61]
wire _SBCSWrData_T_3 = 1'h0; // @[SBA.scala:63:61]
wire _SBCSWrData_T_4 = 1'h0; // @[SBA.scala:63:61]
wire _SBCSWrData_T_7 = 1'h0; // @[SBA.scala:63:61]
wire _SBCSWrData_T_8 = 1'h0; // @[SBA.scala:63:61]
wire _SBCSWrData_T_10 = 1'h0; // @[SBA.scala:63:61]
wire _SBCSWrData_T_11 = 1'h0; // @[SBA.scala:63:61]
wire _SBCSWrData_T_12 = 1'h0; // @[SBA.scala:63:61]
wire SBCSWrData_sbbusy = 1'h0; // @[SBA.scala:63:38]
wire SBCSWrData_sbaccess128 = 1'h0; // @[SBA.scala:63:38]
wire SBCSWrData_sbaccess64 = 1'h0; // @[SBA.scala:63:38]
wire SBCSWrData_sbaccess32 = 1'h0; // @[SBA.scala:63:38]
wire SBCSWrData_sbaccess16 = 1'h0; // @[SBA.scala:63:38]
wire SBCSWrData_sbaccess8 = 1'h0; // @[SBA.scala:63:38]
wire _SBADDRESSRdEn_WIRE_0 = 1'h0; // @[SBA.scala:107:46]
wire _SBADDRESSRdEn_WIRE_1 = 1'h0; // @[SBA.scala:107:46]
wire _SBADDRESSRdEn_WIRE_2 = 1'h0; // @[SBA.scala:107:46]
wire _SBADDRESSRdEn_WIRE_3 = 1'h0; // @[SBA.scala:107:46]
wire SBADDRESSRdEn_1 = 1'h0; // @[SBA.scala:107:38]
wire SBADDRESSRdEn_2 = 1'h0; // @[SBA.scala:107:38]
wire SBADDRESSRdEn_3 = 1'h0; // @[SBA.scala:107:38]
wire _SBADDRESSWrEn_WIRE_0 = 1'h0; // @[SBA.scala:108:46]
wire _SBADDRESSWrEn_WIRE_1 = 1'h0; // @[SBA.scala:108:46]
wire _SBADDRESSWrEn_WIRE_2 = 1'h0; // @[SBA.scala:108:46]
wire _SBADDRESSWrEn_WIRE_3 = 1'h0; // @[SBA.scala:108:46]
wire SBADDRESSWrEn_1 = 1'h0; // @[SBA.scala:108:38]
wire SBADDRESSWrEn_2 = 1'h0; // @[SBA.scala:108:38]
wire SBADDRESSWrEn_3 = 1'h0; // @[SBA.scala:108:38]
wire _SBDATARdEn_WIRE_0 = 1'h0; // @[SBA.scala:149:43]
wire _SBDATARdEn_WIRE_1 = 1'h0; // @[SBA.scala:149:43]
wire _SBDATARdEn_WIRE_2 = 1'h0; // @[SBA.scala:149:43]
wire _SBDATARdEn_WIRE_3 = 1'h0; // @[SBA.scala:149:43]
wire SBDATARdEn_2 = 1'h0; // @[SBA.scala:149:35]
wire SBDATARdEn_3 = 1'h0; // @[SBA.scala:149:35]
wire _SBDATAWrEn_WIRE_0 = 1'h0; // @[SBA.scala:150:43]
wire _SBDATAWrEn_WIRE_1 = 1'h0; // @[SBA.scala:150:43]
wire _SBDATAWrEn_WIRE_2 = 1'h0; // @[SBA.scala:150:43]
wire _SBDATAWrEn_WIRE_3 = 1'h0; // @[SBA.scala:150:43]
wire SBDATAWrEn_2 = 1'h0; // @[SBA.scala:150:35]
wire SBDATAWrEn_3 = 1'h0; // @[SBA.scala:150:35]
wire _sbAccessError_T_1 = 1'h0; // @[SBA.scala:182:88]
wire _sbAccessError_T_2 = 1'h0; // @[SBA.scala:182:58]
wire _sbAccessError_T_4 = 1'h0; // @[SBA.scala:183:88]
wire _sbAccessError_T_5 = 1'h0; // @[SBA.scala:183:58]
wire _sbAccessError_T_6 = 1'h0; // @[SBA.scala:182:97]
wire _sbAccessError_T_8 = 1'h0; // @[SBA.scala:184:88]
wire _sbAccessError_T_9 = 1'h0; // @[SBA.scala:184:58]
wire _sbAccessError_T_10 = 1'h0; // @[SBA.scala:183:97]
wire _sbAccessError_T_12 = 1'h0; // @[SBA.scala:185:88]
wire _sbAccessError_T_13 = 1'h0; // @[SBA.scala:185:58]
wire _sbAccessError_T_14 = 1'h0; // @[SBA.scala:184:97]
wire _SBCSRdData_WIRE_1_sbbusyerror = 1'h0; // @[SBA.scala:243:33]
wire _SBCSRdData_WIRE_1_sbbusy = 1'h0; // @[SBA.scala:243:33]
wire _SBCSRdData_WIRE_1_sbreadonaddr = 1'h0; // @[SBA.scala:243:33]
wire _SBCSRdData_WIRE_1_sbautoincrement = 1'h0; // @[SBA.scala:243:33]
wire _SBCSRdData_WIRE_1_sbreadondata = 1'h0; // @[SBA.scala:243:33]
wire _SBCSRdData_WIRE_1_sbaccess128 = 1'h0; // @[SBA.scala:243:33]
wire _SBCSRdData_WIRE_1_sbaccess64 = 1'h0; // @[SBA.scala:243:33]
wire _SBCSRdData_WIRE_1_sbaccess32 = 1'h0; // @[SBA.scala:243:33]
wire _SBCSRdData_WIRE_1_sbaccess16 = 1'h0; // @[SBA.scala:243:33]
wire _SBCSRdData_WIRE_1_sbaccess8 = 1'h0; // @[SBA.scala:243:33]
wire _out_rifireMux_T_8 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_12 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_16 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_52 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_56 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_60 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_64 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_68 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_76 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_84 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_88 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_104 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_108 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_112 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_116 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_120 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_124 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_128 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_196 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_200 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_204 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_208 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_212 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_216 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_220 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_224 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_236 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_240 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_252 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_256 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_258 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_wifireMux_T_9 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_13 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_17 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_53 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_57 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_61 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_65 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_69 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_77 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_85 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_89 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_105 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_109 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_113 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_117 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_121 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_125 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_129 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_197 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_201 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_205 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_209 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_213 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_217 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_221 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_225 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_237 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_241 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_253 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_257 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_259 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_rofireMux_T_8 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_12 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_16 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_52 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_56 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_60 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_64 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_68 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_76 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_84 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_88 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_104 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_108 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_112 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_116 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_120 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_124 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_128 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_196 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_200 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_204 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_208 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_212 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_216 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_220 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_224 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_236 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_240 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_252 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_256 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_258 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_wofireMux_T_9 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_13 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_17 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_53 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_57 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_61 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_65 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_69 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_77 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_85 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_89 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_105 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_109 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_113 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_117 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_121 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_125 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_129 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_197 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_201 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_205 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_209 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_213 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_217 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_221 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_225 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_237 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_241 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_253 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_257 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_259 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_out_bits_data_T = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_out_bits_data_T_2 = 1'h0; // @[MuxLiteral.scala:49:17]
wire dmiNodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:792:17]
wire dmiNodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:792:17]
wire dmiNodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:792:17]
wire _jalAbstract_WIRE_imm3 = 1'h0; // @[Debug.scala:1497:66]
wire _jalAbstract_WIRE_imm1 = 1'h0; // @[Debug.scala:1497:66]
wire jalAbstract_imm3 = 1'h0; // @[Debug.scala:1497:32]
wire jalAbstract_imm1 = 1'h0; // @[Debug.scala:1497:32]
wire _immBits_T = 1'h0; // @[Debug.scala:1575:48]
wire _immBits_T_1 = 1'h0; // @[Debug.scala:1575:48]
wire _immBits_T_2 = 1'h0; // @[Debug.scala:1575:48]
wire _immBits_T_6 = 1'h0; // @[Debug.scala:1575:48]
wire _immBits_T_7 = 1'h0; // @[Debug.scala:1575:48]
wire _immBits_T_8 = 1'h0; // @[Debug.scala:1575:48]
wire _immBits_T_9 = 1'h0; // @[Debug.scala:1575:48]
wire _immBits_T_10 = 1'h0; // @[Debug.scala:1575:48]
wire _immBits_T_11 = 1'h0; // @[Debug.scala:1575:48]
wire _immBits_T_12 = 1'h0; // @[Debug.scala:1575:48]
wire _immBits_T_13 = 1'h0; // @[Debug.scala:1575:48]
wire _immBits_T_14 = 1'h0; // @[Debug.scala:1575:48]
wire _immBits_T_15 = 1'h0; // @[Debug.scala:1575:48]
wire _immBits_T_16 = 1'h0; // @[Debug.scala:1575:48]
wire _immBits_T_17 = 1'h0; // @[Debug.scala:1575:48]
wire _immBits_T_18 = 1'h0; // @[Debug.scala:1575:48]
wire _immBits_T_19 = 1'h0; // @[Debug.scala:1575:48]
wire _immBits_T_20 = 1'h0; // @[Debug.scala:1575:48]
wire _immBits_WIRE_0 = 1'h0; // @[Debug.scala:1575:39]
wire _immBits_WIRE_1 = 1'h0; // @[Debug.scala:1575:39]
wire _immBits_WIRE_2 = 1'h0; // @[Debug.scala:1575:39]
wire _immBits_WIRE_6 = 1'h0; // @[Debug.scala:1575:39]
wire _immBits_WIRE_7 = 1'h0; // @[Debug.scala:1575:39]
wire _immBits_WIRE_8 = 1'h0; // @[Debug.scala:1575:39]
wire _immBits_WIRE_9 = 1'h0; // @[Debug.scala:1575:39]
wire _immBits_WIRE_10 = 1'h0; // @[Debug.scala:1575:39]
wire _immBits_WIRE_11 = 1'h0; // @[Debug.scala:1575:39]
wire _immBits_WIRE_12 = 1'h0; // @[Debug.scala:1575:39]
wire _immBits_WIRE_13 = 1'h0; // @[Debug.scala:1575:39]
wire _immBits_WIRE_14 = 1'h0; // @[Debug.scala:1575:39]
wire _immBits_WIRE_15 = 1'h0; // @[Debug.scala:1575:39]
wire _immBits_WIRE_16 = 1'h0; // @[Debug.scala:1575:39]
wire _immBits_WIRE_17 = 1'h0; // @[Debug.scala:1575:39]
wire _immBits_WIRE_18 = 1'h0; // @[Debug.scala:1575:39]
wire _immBits_WIRE_19 = 1'h0; // @[Debug.scala:1575:39]
wire _immBits_WIRE_20 = 1'h0; // @[Debug.scala:1575:39]
wire immBits_0 = 1'h0; // @[Debug.scala:1575:31]
wire immBits_1 = 1'h0; // @[Debug.scala:1575:31]
wire immBits_2 = 1'h0; // @[Debug.scala:1575:31]
wire immBits_6 = 1'h0; // @[Debug.scala:1575:31]
wire immBits_7 = 1'h0; // @[Debug.scala:1575:31]
wire immBits_8 = 1'h0; // @[Debug.scala:1575:31]
wire immBits_9 = 1'h0; // @[Debug.scala:1575:31]
wire immBits_10 = 1'h0; // @[Debug.scala:1575:31]
wire immBits_11 = 1'h0; // @[Debug.scala:1575:31]
wire immBits_12 = 1'h0; // @[Debug.scala:1575:31]
wire immBits_13 = 1'h0; // @[Debug.scala:1575:31]
wire immBits_14 = 1'h0; // @[Debug.scala:1575:31]
wire immBits_15 = 1'h0; // @[Debug.scala:1575:31]
wire immBits_16 = 1'h0; // @[Debug.scala:1575:31]
wire immBits_17 = 1'h0; // @[Debug.scala:1575:31]
wire immBits_18 = 1'h0; // @[Debug.scala:1575:31]
wire immBits_19 = 1'h0; // @[Debug.scala:1575:31]
wire immBits_20 = 1'h0; // @[Debug.scala:1575:31]
wire _flags_WIRE_resume = 1'h0; // @[Debug.scala:1517:87]
wire _flags_WIRE_go = 1'h0; // @[Debug.scala:1517:87]
wire _flags_WIRE_1_resume = 1'h0; // @[Debug.scala:1517:87]
wire _flags_WIRE_1_go = 1'h0; // @[Debug.scala:1517:87]
wire _flags_WIRE_2_0_resume = 1'h0; // @[Debug.scala:1517:33]
wire _flags_WIRE_2_0_go = 1'h0; // @[Debug.scala:1517:33]
wire _flags_WIRE_2_1_resume = 1'h0; // @[Debug.scala:1517:33]
wire _flags_WIRE_2_1_go = 1'h0; // @[Debug.scala:1517:33]
wire flags_1_resume = 1'h0; // @[Debug.scala:1517:25]
wire flags_1_go = 1'h0; // @[Debug.scala:1517:25]
wire componentSel = 1'h0; // @[Debug.scala:1523:34]
wire _out_rifireMux_T_307 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_311 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_315 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_319 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_323 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_327 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_331 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_335 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_339 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_343 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_347 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_351 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_355 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_359 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_363 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_367 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_371 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_375 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_379 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_383 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_387 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_399 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_403 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_407 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_411 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_415 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_419 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_423 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_427 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_431 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_435 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_439 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_443 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_447 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_451 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_455 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_459 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_463 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_467 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_471 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_475 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_479 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_483 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_487 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_491 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_495 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_499 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_503 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_507 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_511 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_515 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_519 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_523 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_527 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_531 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_535 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_539 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_543 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_547 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_551 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_555 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_559 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_563 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_567 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_571 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_575 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_579 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_583 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_587 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_591 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_595 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_599 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_603 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_607 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_611 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_615 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_619 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_623 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_627 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_631 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_635 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_639 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_643 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_651 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_655 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_659 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_663 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_667 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_671 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_727 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_731 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_735 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_739 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_743 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_747 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_751 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_755 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_759 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_763 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_767 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_771 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1285 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_wifireMux_T_309 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_313 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_317 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_321 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_325 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_329 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_333 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_337 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_341 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_345 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_349 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_353 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_357 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_361 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_365 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_369 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_373 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_377 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_381 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_385 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_389 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_401 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_405 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_409 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_413 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_417 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_421 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_425 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_429 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_433 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_437 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_441 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_445 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_449 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_453 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_457 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_461 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_465 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_469 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_473 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_477 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_481 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_485 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_489 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_493 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_497 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_501 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_505 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_509 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_513 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_517 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_521 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_525 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_529 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_533 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_537 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_541 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_545 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_549 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_553 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_557 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_561 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_565 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_569 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_573 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_577 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_581 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_585 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_589 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_593 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_597 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_601 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_605 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_609 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_613 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_617 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_621 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_625 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_629 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_633 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_637 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_641 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_645 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_653 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_657 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_661 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_665 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_669 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_673 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_729 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_733 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_737 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_741 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_745 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_749 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_753 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_757 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_761 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_765 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_769 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_773 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1287 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_rofireMux_T_307 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_311 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_315 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_319 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_323 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_327 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_331 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_335 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_339 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_343 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_347 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_351 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_355 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_359 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_363 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_367 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_371 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_375 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_379 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_383 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_387 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_399 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_403 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_407 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_411 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_415 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_419 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_423 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_427 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_431 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_435 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_439 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_443 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_447 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_451 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_455 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_459 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_463 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_467 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_471 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_475 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_479 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_483 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_487 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_491 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_495 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_499 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_503 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_507 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_511 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_515 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_519 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_523 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_527 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_531 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_535 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_539 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_543 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_547 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_551 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_555 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_559 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_563 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_567 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_571 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_575 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_579 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_583 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_587 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_591 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_595 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_599 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_603 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_607 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_611 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_615 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_619 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_623 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_627 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_631 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_635 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_639 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_643 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_651 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_655 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_659 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_663 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_667 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_671 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_727 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_731 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_735 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_739 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_743 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_747 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_751 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_755 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_759 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_763 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_767 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_771 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1285 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_wofireMux_T_309 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_313 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_317 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_321 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_325 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_329 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_333 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_337 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_341 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_345 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_349 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_353 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_357 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_361 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_365 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_369 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_373 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_377 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_381 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_385 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_389 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_401 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_405 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_409 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_413 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_417 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_421 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_425 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_429 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_433 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_437 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_441 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_445 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_449 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_453 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_457 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_461 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_465 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_469 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_473 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_477 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_481 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_485 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_489 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_493 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_497 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_501 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_505 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_509 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_513 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_517 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_521 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_525 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_529 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_533 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_537 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_541 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_545 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_549 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_553 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_557 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_561 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_565 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_569 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_573 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_577 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_581 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_585 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_589 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_593 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_597 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_601 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_605 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_609 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_613 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_617 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_621 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_625 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_629 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_633 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_637 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_641 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_645 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_653 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_657 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_661 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_665 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_669 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_673 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_729 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_733 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_737 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_741 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_745 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_749 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_753 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_757 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_761 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_765 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_769 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_773 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1287 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_out_bits_data_T_5 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_out_bits_data_T_7 = 1'h0; // @[MuxLiteral.scala:49:17]
wire tlNodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:792:17]
wire tlNodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:792:17]
wire tlNodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:792:17]
wire [63:0] autoIncrementedAddr_hi = 64'h0; // @[SBA.scala:111:31]
wire [63:0] sb2tlOpt_io_addrIn_hi = 64'h0; // @[SBA.scala:132:14]
wire [63:0] sb2tlOpt_io_addrIn_hi_1 = 64'h0; // @[SBA.scala:133:10]
wire [63:0] sb2tlOpt_io_dataIn_hi = 64'h0; // @[SBA.scala:175:59]
wire [63:0] sb2tlOpt_io_dataIn_hi_1 = 64'h0; // @[SBA.scala:175:85]
wire [63:0] _out_out_bits_data_WIRE_3_11 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_12 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_13 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_14 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_15 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_16 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_17 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_18 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_19 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_20 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_21 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_22 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_23 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_24 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_25 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_26 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_27 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_28 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_29 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_30 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_31 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_32 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_33 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_34 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_35 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_36 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_37 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_38 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_39 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_40 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_41 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_42 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_43 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_44 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_45 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_46 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_47 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_48 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_49 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_50 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_51 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_52 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_53 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_54 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_55 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_56 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_57 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_58 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_59 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_60 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_61 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_62 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_63 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_64 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_65 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_66 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_67 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_68 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_69 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_70 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_71 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_72 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_73 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_74 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_75 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_76 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_77 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_78 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_79 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_80 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_81 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_82 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_83 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_84 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_85 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_86 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_87 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_88 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_89 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_90 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_91 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_92 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_93 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_94 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_95 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_97 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_98 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_99 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_100 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_101 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_102 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_116 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_117 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_118 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_119 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_120 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_121 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_122 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_123 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_124 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_125 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_126 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_127 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] tlNodeIn_d_bits_d_data = 64'h0; // @[Edges.scala:792:17]
wire [2:0] auto_sb2tlOpt_out_a_bits_param = 3'h0; // @[Debug.scala:790:9]
wire [2:0] _ABSTRACTCSReset_WIRE_reserved0 = 3'h0; // @[Debug.scala:1179:48]
wire [2:0] _ABSTRACTCSReset_WIRE_cmderr = 3'h0; // @[Debug.scala:1179:48]
wire [2:0] ABSTRACTCSReset_reserved0 = 3'h0; // @[Debug.scala:1179:35]
wire [2:0] ABSTRACTCSReset_cmderr = 3'h0; // @[Debug.scala:1179:35]
wire [2:0] _ABSTRACTCSWrData_WIRE_reserved0 = 3'h0; // @[Debug.scala:1184:52]
wire [2:0] _ABSTRACTCSWrData_WIRE_cmderr = 3'h0; // @[Debug.scala:1184:52]
wire [2:0] ABSTRACTCSWrData_reserved0 = 3'h0; // @[Debug.scala:1184:39]
wire [2:0] ABSTRACTCSRdData_reserved0 = 3'h0; // @[Debug.scala:1185:39]
wire [2:0] _SBCSFieldsRegReset_WIRE_sbversion = 3'h0; // @[SBA.scala:49:51]
wire [2:0] _SBCSFieldsRegReset_WIRE_sbaccess = 3'h0; // @[SBA.scala:49:51]
wire [2:0] _SBCSFieldsRegReset_WIRE_sberror = 3'h0; // @[SBA.scala:49:51]
wire [2:0] SBCSFieldsRegReset_sberror = 3'h0; // @[SBA.scala:49:38]
wire [2:0] _SBCSRdData_WIRE_sbversion = 3'h0; // @[SBA.scala:60:51]
wire [2:0] _SBCSRdData_WIRE_sbaccess = 3'h0; // @[SBA.scala:60:51]
wire [2:0] _SBCSRdData_WIRE_sberror = 3'h0; // @[SBA.scala:60:51]
wire [2:0] _SBCSWrData_WIRE_sbversion = 3'h0; // @[SBA.scala:63:61]
wire [2:0] _SBCSWrData_WIRE_sbaccess = 3'h0; // @[SBA.scala:63:61]
wire [2:0] _SBCSWrData_WIRE_sberror = 3'h0; // @[SBA.scala:63:61]
wire [2:0] _SBCSWrData_T_6 = 3'h0; // @[SBA.scala:63:61]
wire [2:0] _SBCSWrData_T_9 = 3'h0; // @[SBA.scala:63:61]
wire [2:0] _SBCSWrData_T_14 = 3'h0; // @[SBA.scala:63:61]
wire [2:0] SBCSWrData_sbversion = 3'h0; // @[SBA.scala:63:38]
wire [2:0] _SBCSRdData_WIRE_1_sbversion = 3'h0; // @[SBA.scala:243:33]
wire [2:0] _SBCSRdData_WIRE_1_sbaccess = 3'h0; // @[SBA.scala:243:33]
wire [2:0] _SBCSRdData_WIRE_1_sberror = 3'h0; // @[SBA.scala:243:33]
wire [2:0] dmiNodeIn_d_bits_d_opcode = 3'h0; // @[Edges.scala:792:17]
wire [2:0] jalAbstract_imm0_hi_hi = 3'h0; // @[package.scala:45:27]
wire [2:0] jalAbstract_imm1_lo_hi = 3'h0; // @[package.scala:45:27]
wire [2:0] jalAbstract_imm1_hi_hi = 3'h0; // @[package.scala:45:27]
wire [2:0] nop_funct3 = 3'h0; // @[Debug.scala:1623:19]
wire [2:0] _nop_WIRE_funct3 = 3'h0; // @[Debug.scala:1624:46]
wire [2:0] isa_funct3 = 3'h0; // @[Debug.scala:1629:19]
wire [2:0] _isa_WIRE_funct3 = 3'h0; // @[Debug.scala:1630:47]
wire [2:0] tlNodeIn_d_bits_d_opcode = 3'h0; // @[Edges.scala:792:17]
wire auto_sb2tlOpt_out_a_bits_mask = 1'h1; // @[Debug.scala:790:9]
wire io_innerCtrl_ready = 1'h1; // @[Debug.scala:790:9]
wire hamaskFull_0 = 1'h1; // @[Debug.scala:903:30]
wire DMSTATUSRdData_authenticated = 1'h1; // @[Debug.scala:978:34]
wire DMSTATUSRdData_hasresethaltreq = 1'h1; // @[Debug.scala:978:34]
wire _DMSTATUSRdData_anyhalted_T = 1'h1; // @[package.scala:79:37]
wire _DMSTATUSRdData_anyrunning_T = 1'h1; // @[package.scala:79:37]
wire _DMSTATUSRdData_allhalted_T = 1'h1; // @[package.scala:79:37]
wire _DMSTATUSRdData_allrunning_T = 1'h1; // @[package.scala:79:37]
wire SBCSFieldsRegReset_sbaccess64 = 1'h1; // @[SBA.scala:49:38]
wire SBCSFieldsRegReset_sbaccess32 = 1'h1; // @[SBA.scala:49:38]
wire SBCSFieldsRegReset_sbaccess16 = 1'h1; // @[SBA.scala:49:38]
wire SBCSFieldsRegReset_sbaccess8 = 1'h1; // @[SBA.scala:49:38]
wire SBCSRdData_sbaccess64 = 1'h1; // @[SBA.scala:60:38]
wire SBCSRdData_sbaccess32 = 1'h1; // @[SBA.scala:60:38]
wire SBCSRdData_sbaccess16 = 1'h1; // @[SBA.scala:60:38]
wire SBCSRdData_sbaccess8 = 1'h1; // @[SBA.scala:60:38]
wire _sbAccessError_T_16 = 1'h1; // @[SBA.scala:186:88]
wire _out_T_438 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_T_439 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_prepend_T_24 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_4 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_21 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_5 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_25 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_6 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_29 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_7 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_33 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_8 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_37 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_9 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_41 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_10 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_45 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_11 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_49 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_12 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_53 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_13 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_57 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_14 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_61 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_15 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_65 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_16 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_69 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_17 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_73 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_18 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_77 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_19 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_81 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_20 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_85 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_21 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_89 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_22 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_93 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_23 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_97 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_24 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_101 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_25 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_105 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_26 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_109 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_27 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_113 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_28 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_117 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_29 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_121 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_30 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_125 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_31 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_129 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_32 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_133 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_33 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_137 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_34 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_141 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_35 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_145 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_36 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_149 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_37 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_153 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_38 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_157 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_39 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_161 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_40 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_165 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_41 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_169 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_42 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_173 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_43 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_177 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_44 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_181 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_45 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_185 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_46 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_189 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_47 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_193 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_48 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_197 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_49 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_201 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_50 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_205 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_51 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_209 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_52 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_213 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_53 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_217 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_54 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_221 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_55 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_225 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_56 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_229 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_57 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_233 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_58 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_237 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_59 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_241 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_60 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_245 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_61 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_249 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_62 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_253 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_63 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_257 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_4 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_5 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_6 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_7 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_8 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_9 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_10 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_11 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_12 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_13 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_14 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_15 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_16 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_17 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_18 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_19 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_20 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_21 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_22 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_23 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_24 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_25 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_26 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_27 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_28 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_29 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_30 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_31 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_32 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_33 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_34 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_35 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_36 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_37 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_38 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_39 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_40 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_41 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_42 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_43 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_44 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_45 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_46 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_47 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_48 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_49 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_50 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_51 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_52 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_53 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_54 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_55 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_56 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_57 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_58 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_59 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_60 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_61 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_62 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_63 = 1'h1; // @[MuxLiteral.scala:49:48]
wire out_rifireMux = 1'h1; // @[MuxLiteral.scala:49:10]
wire out_wifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_14 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_18 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_4 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_22 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_5 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_26 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_6 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_30 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_7 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_34 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_8 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_38 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_9 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_42 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_10 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_46 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_11 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_50 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_12 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_54 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_13 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_58 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_14 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_62 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_15 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_66 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_16 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_70 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_17 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_74 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_18 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_78 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_19 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_82 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_20 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_86 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_21 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_90 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_22 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_94 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_23 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_98 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_24 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_102 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_25 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_106 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_26 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_110 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_27 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_114 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_28 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_118 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_29 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_122 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_30 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_126 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_31 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_130 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_32 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_134 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_33 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_138 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_34 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_142 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_35 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_146 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_36 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_150 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_37 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_154 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_38 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_158 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_39 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_162 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_40 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_166 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_41 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_170 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_42 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_174 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_43 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_178 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_44 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_182 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_45 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_186 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_46 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_190 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_47 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_194 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_48 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_198 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_49 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_202 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_50 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_206 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_51 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_210 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_52 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_214 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_53 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_218 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_54 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_222 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_55 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_226 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_56 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_230 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_57 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_234 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_58 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_238 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_59 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_242 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_60 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_246 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_61 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_250 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_62 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_254 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_63 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_258 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_4 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_5 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_6 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_7 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_8 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_9 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_10 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_11 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_12 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_13 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_14 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_15 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_16 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_17 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_18 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_19 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_20 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_21 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_22 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_23 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_24 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_25 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_26 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_27 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_28 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_29 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_30 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_31 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_32 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_33 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_34 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_35 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_36 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_37 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_38 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_39 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_40 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_41 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_42 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_43 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_44 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_45 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_46 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_47 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_48 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_49 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_50 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_51 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_52 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_53 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_54 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_55 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_56 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_57 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_58 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_59 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_60 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_61 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_62 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_63 = 1'h1; // @[MuxLiteral.scala:49:48]
wire out_wifireMux = 1'h1; // @[MuxLiteral.scala:49:10]
wire out_rofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_4 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_21 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_5 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_25 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_6 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_29 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_7 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_33 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_8 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_37 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_9 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_41 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_10 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_45 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_11 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_49 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_12 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_53 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_13 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_57 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_14 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_61 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_15 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_65 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_16 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_69 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_17 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_73 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_18 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_77 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_19 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_81 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_20 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_85 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_21 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_89 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_22 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_93 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_23 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_97 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_24 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_101 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_25 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_105 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_26 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_109 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_27 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_113 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_28 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_117 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_29 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_121 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_30 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_125 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_31 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_129 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_32 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_133 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_33 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_137 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_34 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_141 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_35 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_145 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_36 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_149 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_37 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_153 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_38 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_157 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_39 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_161 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_40 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_165 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_41 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_169 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_42 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_173 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_43 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_177 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_44 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_181 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_45 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_185 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_46 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_189 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_47 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_193 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_48 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_197 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_49 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_201 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_50 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_205 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_51 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_209 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_52 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_213 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_53 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_217 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_54 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_221 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_55 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_225 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_56 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_229 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_57 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_233 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_58 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_237 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_59 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_241 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_60 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_245 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_61 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_249 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_62 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_253 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_63 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_257 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_4 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_5 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_6 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_7 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_8 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_9 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_10 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_11 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_12 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_13 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_14 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_15 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_16 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_17 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_18 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_19 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_20 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_21 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_22 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_23 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_24 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_25 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_26 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_27 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_28 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_29 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_30 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_31 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_32 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_33 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_34 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_35 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_36 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_37 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_38 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_39 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_40 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_41 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_42 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_43 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_44 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_45 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_46 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_47 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_48 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_49 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_50 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_51 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_52 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_53 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_54 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_55 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_56 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_57 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_58 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_59 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_60 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_61 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_62 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_63 = 1'h1; // @[MuxLiteral.scala:49:48]
wire out_rofireMux = 1'h1; // @[MuxLiteral.scala:49:10]
wire out_wofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_14 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_18 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_4 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_22 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_5 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_26 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_6 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_30 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_7 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_34 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_8 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_38 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_9 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_42 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_10 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_46 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_11 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_50 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_12 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_54 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_13 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_58 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_14 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_62 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_15 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_66 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_16 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_70 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_17 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_74 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_18 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_78 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_19 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_82 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_20 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_86 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_21 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_90 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_22 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_94 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_23 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_98 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_24 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_102 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_25 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_106 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_26 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_110 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_27 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_114 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_28 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_118 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_29 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_122 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_30 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_126 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_31 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_130 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_32 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_134 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_33 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_138 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_34 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_142 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_35 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_146 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_36 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_150 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_37 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_154 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_38 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_158 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_39 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_162 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_40 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_166 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_41 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_170 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_42 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_174 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_43 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_178 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_44 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_182 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_45 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_186 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_46 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_190 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_47 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_194 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_48 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_198 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_49 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_202 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_50 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_206 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_51 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_210 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_52 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_214 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_53 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_218 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_54 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_222 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_55 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_226 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_56 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_230 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_57 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_234 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_58 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_238 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_59 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_242 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_60 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_246 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_61 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_250 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_62 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_254 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_63 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_258 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_4 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_5 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_6 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_7 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_8 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_9 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_10 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_11 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_12 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_13 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_14 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_15 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_16 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_17 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_18 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_19 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_20 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_21 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_22 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_23 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_24 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_25 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_26 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_27 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_28 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_29 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_30 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_31 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_32 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_33 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_34 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_35 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_36 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_37 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_38 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_39 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_40 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_41 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_42 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_43 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_44 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_45 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_46 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_47 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_48 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_49 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_50 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_51 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_52 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_53 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_54 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_55 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_56 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_57 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_58 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_59 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_60 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_61 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_62 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_63 = 1'h1; // @[MuxLiteral.scala:49:48]
wire out_wofireMux = 1'h1; // @[MuxLiteral.scala:49:10]
wire out_iready = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_oready = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_out_bits_data_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_12 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_13 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_14 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_15 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_16 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_18 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_20 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_21 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_25 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_26 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_27 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_28 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_29 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_30 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_31 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_48 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_49 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_50 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_51 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_52 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_53 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_54 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_55 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_58 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_59 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_62 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_63 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _immBits_T_3 = 1'h1; // @[Debug.scala:1575:48]
wire _immBits_T_4 = 1'h1; // @[Debug.scala:1575:48]
wire _immBits_T_5 = 1'h1; // @[Debug.scala:1575:48]
wire _immBits_WIRE_3 = 1'h1; // @[Debug.scala:1575:39]
wire _immBits_WIRE_4 = 1'h1; // @[Debug.scala:1575:39]
wire _immBits_WIRE_5 = 1'h1; // @[Debug.scala:1575:39]
wire immBits_3 = 1'h1; // @[Debug.scala:1575:31]
wire immBits_4 = 1'h1; // @[Debug.scala:1575:31]
wire immBits_5 = 1'h1; // @[Debug.scala:1575:31]
wire out_rifireMux_out_64 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_264 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_65 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_268 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_66 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_272 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_67 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_276 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_68 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_280 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_69 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_284 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_70 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_288 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_71 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_292 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_72 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_296 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_73 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_300 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_74 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_304 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_75 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_308 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_76 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_312 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_77 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_316 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_78 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_320 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_79 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_324 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_80 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_328 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_81 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_332 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_82 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_336 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_83 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_340 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_84 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_344 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_85 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_348 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_86 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_352 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_87 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_356 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_88 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_360 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_89 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_364 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_90 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_368 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_91 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_372 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_92 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_376 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_93 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_380 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_94 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_384 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_95 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_388 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_96 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_392 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_97 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_396 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_98 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_400 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_99 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_404 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_100 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_408 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_101 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_412 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_102 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_416 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_103 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_420 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_104 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_424 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_105 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_428 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_106 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_432 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_107 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_436 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_108 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_440 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_109 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_444 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_110 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_448 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_111 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_452 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_112 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_456 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_113 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_460 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_114 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_464 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_115 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_468 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_116 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_472 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_117 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_476 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_118 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_480 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_119 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_484 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_120 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_488 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_121 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_492 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_122 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_496 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_123 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_500 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_124 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_504 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_125 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_508 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_126 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_512 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_127 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_516 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_128 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_520 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_129 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_524 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_130 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_528 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_131 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_532 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_132 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_536 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_133 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_540 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_134 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_544 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_135 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_548 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_136 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_552 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_137 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_556 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_138 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_560 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_139 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_564 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_140 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_568 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_141 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_572 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_142 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_576 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_143 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_580 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_144 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_584 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_145 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_588 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_146 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_592 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_147 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_596 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_148 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_600 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_149 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_604 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_150 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_608 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_151 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_612 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_152 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_616 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_153 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_620 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_154 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_624 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_155 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_628 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_156 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_632 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_157 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_636 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_158 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_640 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_159 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_644 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_160 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_648 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_161 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_652 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_162 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_656 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_163 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_660 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_164 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_664 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_165 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_668 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_166 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_672 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_167 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_676 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_168 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_680 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_169 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_684 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_170 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_688 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_171 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_692 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_172 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_696 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_173 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_700 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_174 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_704 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_175 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_708 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_176 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_712 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_177 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_716 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_178 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_720 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_179 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_724 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_180 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_728 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_181 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_732 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_182 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_736 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_183 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_740 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_184 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_744 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_185 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_748 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_186 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_752 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_187 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_756 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_188 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_760 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_189 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_764 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_190 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_768 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_191 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_772 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_192 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_776 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_193 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_780 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_194 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_784 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_195 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_788 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_196 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_792 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_197 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_796 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_198 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_800 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_199 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_804 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_200 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_808 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_201 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_812 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_202 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_816 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_203 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_820 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_204 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_824 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_205 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_828 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_206 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_832 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_207 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_836 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_208 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_840 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_209 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_844 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_210 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_848 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_211 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_852 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_212 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_856 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_213 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_860 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_214 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_864 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_215 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_868 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_216 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_872 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_217 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_876 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_218 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_880 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_219 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_884 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_220 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_888 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_221 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_892 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_222 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_896 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_223 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_900 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_224 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_904 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_225 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_908 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_226 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_912 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_227 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_916 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_228 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_920 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_229 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_924 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_230 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_928 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_231 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_932 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_232 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_936 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_233 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_940 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_234 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_944 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_235 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_948 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_236 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_952 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_237 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_956 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_238 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_960 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_239 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_964 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_240 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_968 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_241 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_972 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_242 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_976 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_243 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_980 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_244 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_984 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_245 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_988 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_246 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_992 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_247 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_996 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_248 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1000 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_249 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1004 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_250 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1008 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_251 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1012 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_252 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1016 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_253 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1020 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_254 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1024 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_255 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1028 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_256 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1032 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_257 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1036 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_258 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1040 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_259 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1044 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_260 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1048 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_261 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1052 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_262 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1056 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_263 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1060 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_264 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1064 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_265 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1068 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_266 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1072 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_267 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1076 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_268 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1080 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_269 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1084 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_270 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1088 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_271 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1092 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_272 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1096 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_273 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1100 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_274 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1104 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_275 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1108 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_276 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1112 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_277 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1116 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_278 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1120 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_279 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1124 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_280 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1128 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_281 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1132 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_282 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1136 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_283 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1140 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_284 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1144 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_285 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1148 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_286 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1152 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_287 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1156 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_288 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1160 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_289 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1164 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_290 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1168 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_291 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1172 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_292 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1176 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_293 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1180 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_294 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1184 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_295 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1188 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_296 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1192 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_297 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1196 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_298 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1200 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_299 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1204 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_300 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1208 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_301 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1212 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_302 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1216 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_303 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1220 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_304 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1224 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_305 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1228 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_306 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1232 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_307 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1236 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_308 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1240 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_309 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1244 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_310 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1248 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_311 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1252 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_312 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1256 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_313 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1260 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_314 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1264 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_315 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1268 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_316 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1272 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_317 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1276 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_318 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1280 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_319 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1284 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_WIRE_1_0 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_1 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_2 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_3 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_4 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_5 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_6 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_7 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_8 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_9 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_10 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_11 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_12 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_13 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_14 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_15 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_16 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_17 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_18 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_19 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_20 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_21 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_22 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_23 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_24 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_25 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_26 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_27 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_28 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_29 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_30 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_31 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_32 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_33 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_34 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_35 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_36 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_37 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_38 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_39 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_40 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_41 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_42 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_43 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_44 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_45 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_46 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_47 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_48 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_49 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_50 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_51 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_52 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_53 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_54 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_55 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_56 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_57 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_58 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_59 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_60 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_61 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_62 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_63 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_64 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_65 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_66 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_67 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_68 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_69 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_70 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_71 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_72 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_73 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_74 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_75 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_76 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_77 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_78 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_79 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_80 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_81 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_82 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_83 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_84 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_85 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_86 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_87 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_88 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_89 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_90 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_91 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_92 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_93 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_94 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_95 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_96 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_97 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_98 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_99 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_100 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_101 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_102 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_103 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_104 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_105 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_106 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_107 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_108 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_109 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_110 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_111 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_112 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_113 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_114 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_115 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_116 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_117 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_118 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_119 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_120 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_121 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_122 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_123 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_124 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_125 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_126 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_127 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_128 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_129 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_130 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_131 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_132 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_133 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_134 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_135 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_136 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_137 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_138 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_139 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_140 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_141 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_142 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_143 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_144 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_145 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_146 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_147 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_148 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_149 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_150 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_151 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_152 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_153 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_154 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_155 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_156 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_157 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_158 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_159 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_160 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_161 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_162 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_163 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_164 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_165 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_166 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_167 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_168 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_169 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_170 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_171 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_172 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_173 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_174 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_175 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_176 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_177 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_178 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_179 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_180 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_181 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_182 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_183 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_184 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_185 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_186 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_187 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_188 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_189 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_190 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_191 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_192 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_193 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_194 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_195 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_196 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_197 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_198 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_199 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_200 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_201 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_202 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_203 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_204 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_205 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_206 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_207 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_208 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_209 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_210 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_211 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_212 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_213 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_214 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_215 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_216 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_217 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_218 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_219 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_220 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_221 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_222 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_223 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_224 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_225 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_226 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_227 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_228 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_229 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_230 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_231 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_232 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_233 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_234 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_235 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_236 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_237 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_238 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_239 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_240 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_241 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_242 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_243 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_244 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_245 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_246 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_247 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_248 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_249 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_250 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_251 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_252 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_253 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_254 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_255 = 1'h1; // @[MuxLiteral.scala:49:48]
wire out_rifireMux_1 = 1'h1; // @[MuxLiteral.scala:49:10]
wire out_wifireMux_out_64 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_266 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_65 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_270 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_66 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_274 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_67 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_278 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_68 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_282 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_69 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_286 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_70 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_290 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_71 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_294 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_72 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_298 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_73 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_302 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_74 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_306 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_75 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_310 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_76 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_314 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_77 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_318 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_78 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_322 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_79 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_326 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_80 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_330 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_81 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_334 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_82 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_338 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_83 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_342 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_84 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_346 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_85 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_350 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_86 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_354 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_87 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_358 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_88 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_362 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_89 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_366 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_90 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_370 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_91 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_374 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_92 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_378 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_93 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_382 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_94 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_386 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_95 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_390 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_96 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_394 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_97 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_398 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_98 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_402 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_99 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_406 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_100 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_410 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_101 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_414 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_102 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_418 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_103 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_422 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_104 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_426 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_105 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_430 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_106 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_434 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_107 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_438 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_108 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_442 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_109 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_446 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_110 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_450 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_111 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_454 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_112 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_458 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_113 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_462 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_114 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_466 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_115 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_470 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_116 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_474 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_117 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_478 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_118 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_482 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_119 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_486 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_120 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_490 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_121 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_494 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_122 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_498 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_123 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_502 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_124 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_506 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_125 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_510 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_126 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_514 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_127 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_518 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_128 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_522 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_129 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_526 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_130 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_530 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_131 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_534 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_132 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_538 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_133 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_542 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_134 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_546 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_135 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_550 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_136 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_554 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_137 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_558 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_138 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_562 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_139 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_566 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_140 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_570 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_141 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_574 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_142 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_578 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_143 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_582 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_144 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_586 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_145 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_590 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_146 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_594 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_147 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_598 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_148 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_602 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_149 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_606 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_150 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_610 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_151 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_614 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_152 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_618 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_153 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_622 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_154 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_626 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_155 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_630 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_156 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_634 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_157 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_638 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_158 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_642 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_159 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_646 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_160 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_650 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_161 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_654 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_162 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_658 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_163 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_662 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_164 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_666 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_165 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_670 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_166 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_674 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_167 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_678 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_168 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_682 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_169 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_686 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_170 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_690 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_171 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_694 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_172 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_698 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_173 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_702 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_174 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_706 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_175 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_710 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_176 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_714 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_177 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_718 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_178 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_722 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_179 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_726 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_180 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_730 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_181 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_734 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_182 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_738 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_183 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_742 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_184 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_746 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_185 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_750 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_186 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_754 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_187 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_758 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_188 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_762 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_189 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_766 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_190 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_770 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_191 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_774 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_192 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_778 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_193 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_782 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_194 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_786 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_195 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_790 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_196 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_794 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_197 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_798 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_198 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_802 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_199 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_806 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_200 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_810 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_201 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_814 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_202 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_818 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_203 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_822 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_204 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_826 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_205 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_830 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_206 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_834 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_207 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_838 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_208 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_842 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_209 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_846 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_210 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_850 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_211 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_854 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_212 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_858 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_213 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_862 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_214 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_866 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_215 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_870 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_216 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_874 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_217 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_878 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_218 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_882 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_219 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_886 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_220 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_890 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_221 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_894 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_222 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_898 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_223 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_902 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_224 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_906 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_225 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_910 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_226 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_914 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_227 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_918 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_228 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_922 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_229 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_926 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_230 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_930 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_231 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_934 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_232 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_938 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_233 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_942 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_234 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_946 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_235 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_950 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_236 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_954 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_237 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_958 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_238 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_962 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_239 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_966 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_240 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_970 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_241 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_974 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_242 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_978 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_243 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_982 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_244 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_986 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_245 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_990 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_246 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_994 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_247 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_998 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_248 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1002 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_249 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1006 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_250 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1010 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_251 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1014 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_252 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1018 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_253 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1022 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_254 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1026 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_255 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1030 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_256 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1034 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_257 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1038 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_258 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1042 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_259 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1046 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_260 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1050 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_261 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1054 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_262 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1058 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_263 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1062 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_264 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1066 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_265 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1070 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_266 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1074 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_267 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1078 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_268 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1082 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_269 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1086 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_270 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1090 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_271 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1094 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_272 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1098 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_273 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1102 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_274 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1106 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_275 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1110 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_276 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1114 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_277 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1118 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_278 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1122 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_279 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1126 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_280 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1130 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_281 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1134 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_282 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1138 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_283 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1142 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_284 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1146 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_285 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1150 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_286 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1154 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_287 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1158 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_288 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1162 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_289 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1166 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_290 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1170 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_291 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1174 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_292 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1178 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_293 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1182 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_294 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1186 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_295 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1190 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_296 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1194 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_297 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1198 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_298 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1202 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_299 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1206 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_300 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1210 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_301 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1214 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_302 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1218 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_303 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1222 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_304 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1226 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_305 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1230 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_306 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1234 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_307 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1238 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_308 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1242 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_309 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1246 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_310 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1250 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_311 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1254 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_312 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1258 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_313 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1262 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_314 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1266 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_315 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1270 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_316 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1274 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_317 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1278 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_318 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1282 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_319 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1286 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_WIRE_1_0 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_1 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_2 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_3 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_4 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_5 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_6 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_7 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_8 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_9 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_10 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_11 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_12 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_13 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_14 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_15 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_16 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_17 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_18 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_19 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_20 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_21 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_22 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_23 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_24 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_25 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_26 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_27 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_28 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_29 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_30 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_31 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_32 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_33 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_34 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_35 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_36 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_37 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_38 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_39 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_40 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_41 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_42 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_43 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_44 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_45 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_46 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_47 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_48 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_49 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_50 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_51 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_52 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_53 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_54 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_55 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_56 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_57 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_58 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_59 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_60 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_61 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_62 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_63 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_64 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_65 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_66 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_67 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_68 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_69 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_70 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_71 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_72 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_73 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_74 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_75 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_76 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_77 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_78 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_79 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_80 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_81 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_82 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_83 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_84 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_85 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_86 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_87 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_88 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_89 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_90 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_91 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_92 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_93 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_94 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_95 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_96 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_97 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_98 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_99 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_100 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_101 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_102 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_103 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_104 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_105 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_106 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_107 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_108 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_109 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_110 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_111 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_112 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_113 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_114 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_115 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_116 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_117 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_118 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_119 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_120 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_121 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_122 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_123 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_124 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_125 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_126 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_127 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_128 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_129 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_130 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_131 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_132 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_133 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_134 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_135 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_136 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_137 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_138 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_139 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_140 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_141 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_142 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_143 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_144 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_145 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_146 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_147 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_148 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_149 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_150 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_151 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_152 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_153 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_154 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_155 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_156 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_157 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_158 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_159 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_160 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_161 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_162 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_163 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_164 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_165 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_166 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_167 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_168 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_169 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_170 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_171 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_172 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_173 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_174 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_175 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_176 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_177 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_178 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_179 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_180 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_181 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_182 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_183 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_184 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_185 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_186 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_187 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_188 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_189 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_190 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_191 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_192 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_193 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_194 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_195 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_196 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_197 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_198 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_199 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_200 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_201 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_202 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_203 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_204 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_205 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_206 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_207 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_208 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_209 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_210 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_211 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_212 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_213 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_214 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_215 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_216 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_217 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_218 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_219 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_220 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_221 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_222 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_223 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_224 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_225 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_226 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_227 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_228 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_229 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_230 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_231 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_232 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_233 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_234 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_235 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_236 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_237 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_238 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_239 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_240 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_241 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_242 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_243 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_244 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_245 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_246 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_247 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_248 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_249 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_250 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_251 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_252 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_253 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_254 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_255 = 1'h1; // @[MuxLiteral.scala:49:48]
wire out_wifireMux_1 = 1'h1; // @[MuxLiteral.scala:49:10]
wire out_rofireMux_out_64 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_264 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_65 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_268 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_66 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_272 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_67 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_276 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_68 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_280 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_69 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_284 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_70 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_288 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_71 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_292 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_72 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_296 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_73 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_300 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_74 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_304 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_75 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_308 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_76 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_312 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_77 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_316 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_78 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_320 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_79 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_324 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_80 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_328 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_81 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_332 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_82 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_336 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_83 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_340 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_84 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_344 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_85 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_348 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_86 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_352 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_87 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_356 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_88 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_360 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_89 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_364 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_90 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_368 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_91 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_372 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_92 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_376 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_93 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_380 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_94 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_384 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_95 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_388 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_96 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_392 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_97 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_396 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_98 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_400 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_99 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_404 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_100 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_408 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_101 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_412 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_102 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_416 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_103 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_420 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_104 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_424 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_105 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_428 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_106 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_432 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_107 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_436 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_108 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_440 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_109 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_444 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_110 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_448 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_111 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_452 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_112 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_456 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_113 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_460 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_114 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_464 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_115 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_468 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_116 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_472 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_117 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_476 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_118 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_480 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_119 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_484 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_120 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_488 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_121 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_492 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_122 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_496 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_123 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_500 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_124 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_504 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_125 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_508 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_126 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_512 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_127 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_516 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_128 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_520 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_129 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_524 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_130 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_528 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_131 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_532 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_132 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_536 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_133 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_540 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_134 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_544 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_135 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_548 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_136 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_552 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_137 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_556 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_138 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_560 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_139 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_564 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_140 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_568 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_141 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_572 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_142 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_576 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_143 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_580 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_144 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_584 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_145 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_588 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_146 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_592 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_147 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_596 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_148 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_600 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_149 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_604 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_150 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_608 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_151 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_612 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_152 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_616 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_153 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_620 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_154 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_624 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_155 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_628 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_156 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_632 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_157 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_636 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_158 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_640 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_159 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_644 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_160 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_648 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_161 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_652 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_162 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_656 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_163 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_660 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_164 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_664 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_165 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_668 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_166 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_672 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_167 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_676 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_168 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_680 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_169 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_684 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_170 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_688 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_171 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_692 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_172 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_696 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_173 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_700 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_174 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_704 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_175 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_708 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_176 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_712 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_177 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_716 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_178 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_720 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_179 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_724 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_180 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_728 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_181 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_732 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_182 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_736 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_183 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_740 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_184 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_744 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_185 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_748 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_186 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_752 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_187 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_756 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_188 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_760 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_189 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_764 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_190 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_768 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_191 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_772 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_192 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_776 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_193 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_780 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_194 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_784 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_195 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_788 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_196 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_792 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_197 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_796 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_198 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_800 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_199 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_804 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_200 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_808 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_201 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_812 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_202 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_816 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_203 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_820 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_204 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_824 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_205 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_828 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_206 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_832 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_207 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_836 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_208 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_840 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_209 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_844 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_210 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_848 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_211 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_852 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_212 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_856 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_213 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_860 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_214 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_864 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_215 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_868 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_216 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_872 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_217 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_876 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_218 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_880 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_219 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_884 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_220 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_888 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_221 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_892 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_222 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_896 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_223 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_900 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_224 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_904 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_225 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_908 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_226 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_912 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_227 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_916 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_228 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_920 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_229 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_924 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_230 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_928 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_231 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_932 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_232 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_936 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_233 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_940 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_234 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_944 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_235 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_948 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_236 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_952 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_237 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_956 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_238 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_960 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_239 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_964 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_240 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_968 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_241 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_972 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_242 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_976 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_243 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_980 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_244 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_984 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_245 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_988 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_246 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_992 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_247 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_996 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_248 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1000 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_249 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1004 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_250 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1008 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_251 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1012 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_252 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1016 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_253 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1020 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_254 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1024 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_255 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1028 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_256 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1032 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_257 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1036 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_258 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1040 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_259 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1044 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_260 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1048 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_261 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1052 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_262 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1056 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_263 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1060 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_264 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1064 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_265 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1068 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_266 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1072 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_267 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1076 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_268 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1080 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_269 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1084 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_270 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1088 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_271 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1092 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_272 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1096 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_273 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1100 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_274 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1104 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_275 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1108 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_276 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1112 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_277 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1116 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_278 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1120 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_279 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1124 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_280 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1128 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_281 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1132 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_282 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1136 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_283 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1140 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_284 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1144 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_285 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1148 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_286 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1152 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_287 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1156 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_288 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1160 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_289 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1164 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_290 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1168 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_291 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1172 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_292 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1176 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_293 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1180 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_294 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1184 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_295 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1188 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_296 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1192 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_297 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1196 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_298 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1200 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_299 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1204 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_300 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1208 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_301 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1212 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_302 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1216 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_303 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1220 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_304 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1224 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_305 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1228 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_306 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1232 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_307 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1236 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_308 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1240 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_309 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1244 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_310 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1248 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_311 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1252 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_312 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1256 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_313 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1260 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_314 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1264 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_315 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1268 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_316 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1272 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_317 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1276 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_318 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1280 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_319 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1284 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_WIRE_1_0 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_1 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_2 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_3 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_4 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_5 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_6 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_7 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_8 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_9 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_10 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_11 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_12 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_13 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_14 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_15 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_16 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_17 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_18 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_19 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_20 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_21 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_22 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_23 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_24 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_25 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_26 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_27 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_28 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_29 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_30 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_31 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_32 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_33 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_34 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_35 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_36 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_37 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_38 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_39 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_40 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_41 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_42 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_43 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_44 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_45 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_46 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_47 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_48 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_49 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_50 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_51 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_52 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_53 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_54 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_55 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_56 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_57 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_58 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_59 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_60 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_61 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_62 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_63 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_64 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_65 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_66 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_67 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_68 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_69 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_70 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_71 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_72 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_73 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_74 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_75 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_76 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_77 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_78 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_79 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_80 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_81 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_82 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_83 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_84 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_85 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_86 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_87 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_88 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_89 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_90 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_91 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_92 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_93 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_94 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_95 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_96 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_97 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_98 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_99 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_100 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_101 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_102 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_103 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_104 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_105 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_106 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_107 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_108 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_109 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_110 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_111 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_112 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_113 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_114 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_115 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_116 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_117 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_118 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_119 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_120 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_121 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_122 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_123 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_124 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_125 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_126 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_127 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_128 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_129 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_130 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_131 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_132 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_133 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_134 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_135 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_136 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_137 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_138 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_139 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_140 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_141 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_142 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_143 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_144 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_145 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_146 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_147 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_148 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_149 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_150 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_151 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_152 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_153 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_154 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_155 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_156 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_157 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_158 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_159 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_160 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_161 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_162 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_163 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_164 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_165 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_166 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_167 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_168 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_169 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_170 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_171 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_172 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_173 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_174 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_175 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_176 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_177 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_178 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_179 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_180 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_181 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_182 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_183 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_184 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_185 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_186 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_187 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_188 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_189 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_190 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_191 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_192 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_193 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_194 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_195 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_196 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_197 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_198 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_199 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_200 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_201 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_202 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_203 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_204 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_205 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_206 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_207 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_208 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_209 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_210 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_211 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_212 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_213 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_214 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_215 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_216 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_217 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_218 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_219 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_220 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_221 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_222 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_223 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_224 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_225 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_226 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_227 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_228 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_229 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_230 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_231 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_232 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_233 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_234 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_235 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_236 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_237 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_238 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_239 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_240 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_241 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_242 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_243 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_244 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_245 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_246 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_247 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_248 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_249 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_250 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_251 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_252 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_253 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_254 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_255 = 1'h1; // @[MuxLiteral.scala:49:48]
wire out_rofireMux_1 = 1'h1; // @[MuxLiteral.scala:49:10]
wire out_wofireMux_out_64 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_266 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_65 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_270 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_66 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_274 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_67 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_278 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_68 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_282 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_69 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_286 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_70 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_290 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_71 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_294 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_72 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_298 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_73 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_302 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_74 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_306 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_75 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_310 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_76 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_314 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_77 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_318 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_78 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_322 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_79 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_326 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_80 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_330 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_81 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_334 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_82 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_338 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_83 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_342 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_84 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_346 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_85 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_350 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_86 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_354 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_87 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_358 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_88 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_362 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_89 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_366 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_90 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_370 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_91 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_374 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_92 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_378 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_93 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_382 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_94 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_386 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_95 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_390 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_96 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_394 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_97 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_398 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_98 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_402 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_99 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_406 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_100 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_410 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_101 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_414 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_102 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_418 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_103 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_422 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_104 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_426 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_105 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_430 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_106 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_434 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_107 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_438 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_108 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_442 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_109 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_446 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_110 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_450 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_111 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_454 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_112 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_458 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_113 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_462 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_114 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_466 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_115 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_470 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_116 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_474 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_117 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_478 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_118 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_482 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_119 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_486 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_120 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_490 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_121 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_494 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_122 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_498 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_123 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_502 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_124 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_506 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_125 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_510 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_126 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_514 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_127 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_518 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_128 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_522 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_129 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_526 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_130 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_530 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_131 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_534 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_132 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_538 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_133 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_542 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_134 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_546 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_135 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_550 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_136 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_554 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_137 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_558 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_138 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_562 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_139 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_566 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_140 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_570 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_141 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_574 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_142 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_578 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_143 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_582 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_144 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_586 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_145 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_590 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_146 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_594 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_147 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_598 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_148 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_602 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_149 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_606 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_150 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_610 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_151 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_614 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_152 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_618 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_153 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_622 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_154 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_626 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_155 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_630 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_156 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_634 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_157 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_638 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_158 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_642 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_159 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_646 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_160 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_650 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_161 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_654 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_162 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_658 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_163 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_662 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_164 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_666 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_165 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_670 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_166 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_674 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_167 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_678 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_168 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_682 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_169 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_686 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_170 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_690 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_171 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_694 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_172 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_698 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_173 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_702 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_174 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_706 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_175 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_710 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_176 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_714 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_177 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_718 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_178 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_722 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_179 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_726 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_180 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_730 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_181 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_734 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_182 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_738 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_183 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_742 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_184 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_746 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_185 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_750 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_186 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_754 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_187 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_758 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_188 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_762 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_189 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_766 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_190 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_770 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_191 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_774 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_192 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_778 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_193 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_782 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_194 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_786 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_195 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_790 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_196 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_794 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_197 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_798 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_198 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_802 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_199 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_806 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_200 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_810 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_201 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_814 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_202 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_818 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_203 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_822 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_204 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_826 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_205 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_830 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_206 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_834 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_207 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_838 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_208 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_842 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_209 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_846 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_210 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_850 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_211 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_854 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_212 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_858 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_213 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_862 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_214 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_866 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_215 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_870 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_216 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_874 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_217 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_878 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_218 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_882 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_219 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_886 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_220 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_890 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_221 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_894 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_222 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_898 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_223 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_902 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_224 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_906 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_225 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_910 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_226 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_914 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_227 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_918 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_228 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_922 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_229 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_926 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_230 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_930 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_231 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_934 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_232 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_938 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_233 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_942 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_234 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_946 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_235 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_950 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_236 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_954 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_237 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_958 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_238 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_962 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_239 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_966 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_240 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_970 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_241 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_974 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_242 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_978 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_243 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_982 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_244 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_986 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_245 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_990 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_246 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_994 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_247 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_998 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_248 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1002 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_249 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1006 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_250 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1010 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_251 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1014 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_252 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1018 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_253 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1022 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_254 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1026 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_255 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1030 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_256 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1034 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_257 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1038 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_258 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1042 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_259 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1046 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_260 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1050 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_261 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1054 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_262 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1058 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_263 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1062 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_264 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1066 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_265 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1070 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_266 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1074 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_267 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1078 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_268 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1082 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_269 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1086 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_270 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1090 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_271 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1094 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_272 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1098 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_273 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1102 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_274 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1106 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_275 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1110 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_276 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1114 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_277 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1118 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_278 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1122 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_279 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1126 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_280 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1130 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_281 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1134 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_282 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1138 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_283 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1142 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_284 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1146 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_285 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1150 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_286 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1154 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_287 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1158 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_288 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1162 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_289 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1166 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_290 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1170 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_291 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1174 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_292 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1178 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_293 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1182 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_294 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1186 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_295 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1190 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_296 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1194 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_297 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1198 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_298 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1202 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_299 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1206 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_300 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1210 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_301 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1214 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_302 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1218 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_303 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1222 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_304 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1226 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_305 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1230 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_306 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1234 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_307 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1238 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_308 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1242 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_309 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1246 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_310 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1250 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_311 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1254 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_312 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1258 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_313 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1262 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_314 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1266 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_315 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1270 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_316 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1274 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_317 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1278 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_318 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1282 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_319 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1286 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_WIRE_1_0 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_1 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_2 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_3 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_4 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_5 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_6 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_7 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_8 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_9 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_10 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_11 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_12 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_13 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_14 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_15 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_16 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_17 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_18 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_19 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_20 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_21 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_22 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_23 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_24 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_25 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_26 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_27 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_28 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_29 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_30 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_31 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_32 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_33 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_34 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_35 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_36 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_37 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_38 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_39 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_40 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_41 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_42 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_43 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_44 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_45 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_46 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_47 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_48 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_49 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_50 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_51 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_52 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_53 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_54 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_55 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_56 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_57 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_58 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_59 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_60 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_61 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_62 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_63 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_64 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_65 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_66 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_67 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_68 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_69 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_70 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_71 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_72 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_73 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_74 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_75 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_76 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_77 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_78 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_79 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_80 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_81 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_82 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_83 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_84 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_85 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_86 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_87 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_88 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_89 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_90 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_91 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_92 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_93 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_94 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_95 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_96 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_97 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_98 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_99 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_100 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_101 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_102 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_103 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_104 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_105 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_106 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_107 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_108 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_109 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_110 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_111 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_112 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_113 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_114 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_115 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_116 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_117 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_118 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_119 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_120 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_121 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_122 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_123 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_124 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_125 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_126 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_127 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_128 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_129 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_130 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_131 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_132 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_133 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_134 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_135 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_136 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_137 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_138 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_139 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_140 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_141 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_142 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_143 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_144 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_145 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_146 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_147 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_148 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_149 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_150 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_151 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_152 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_153 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_154 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_155 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_156 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_157 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_158 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_159 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_160 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_161 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_162 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_163 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_164 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_165 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_166 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_167 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_168 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_169 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_170 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_171 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_172 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_173 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_174 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_175 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_176 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_177 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_178 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_179 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_180 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_181 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_182 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_183 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_184 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_185 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_186 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_187 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_188 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_189 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_190 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_191 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_192 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_193 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_194 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_195 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_196 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_197 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_198 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_199 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_200 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_201 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_202 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_203 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_204 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_205 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_206 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_207 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_208 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_209 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_210 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_211 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_212 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_213 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_214 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_215 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_216 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_217 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_218 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_219 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_220 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_221 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_222 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_223 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_224 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_225 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_226 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_227 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_228 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_229 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_230 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_231 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_232 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_233 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_234 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_235 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_236 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_237 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_238 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_239 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_240 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_241 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_242 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_243 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_244 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_245 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_246 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_247 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_248 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_249 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_250 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_251 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_252 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_253 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_254 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_255 = 1'h1; // @[MuxLiteral.scala:49:48]
wire out_wofireMux_1 = 1'h1; // @[MuxLiteral.scala:49:10]
wire out_iready_1 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_oready_1 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_out_bits_data_WIRE_2_11 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_12 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_13 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_14 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_15 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_16 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_17 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_18 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_19 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_20 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_21 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_22 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_23 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_24 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_25 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_26 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_27 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_28 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_29 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_30 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_31 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_34 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_35 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_36 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_37 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_38 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_39 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_40 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_41 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_42 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_43 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_44 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_45 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_46 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_47 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_48 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_49 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_50 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_51 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_52 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_53 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_54 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_55 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_56 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_57 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_58 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_59 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_60 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_61 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_62 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_63 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_64 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_65 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_66 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_67 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_68 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_69 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_70 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_71 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_72 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_73 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_74 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_75 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_76 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_77 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_78 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_79 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_80 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_81 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_82 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_83 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_84 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_85 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_86 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_87 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_88 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_89 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_90 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_91 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_92 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_93 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_94 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_95 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_97 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_98 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_99 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_100 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_101 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_102 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_116 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_117 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_118 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_119 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_120 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_121 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_122 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_123 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_124 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_125 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_126 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_127 = 1'h1; // @[MuxLiteral.scala:49:48]
wire [31:0] SBCSWrDataVal = 32'h0; // @[SBA.scala:62:38]
wire [31:0] _SBCSWrData_WIRE_1 = 32'h0; // @[SBA.scala:63:61]
wire [31:0] _SBADDRESSWrData_WIRE_0 = 32'h0; // @[SBA.scala:106:46]
wire [31:0] _SBADDRESSWrData_WIRE_1 = 32'h0; // @[SBA.scala:106:46]
wire [31:0] _SBADDRESSWrData_WIRE_2 = 32'h0; // @[SBA.scala:106:46]
wire [31:0] _SBADDRESSWrData_WIRE_3 = 32'h0; // @[SBA.scala:106:46]
wire [31:0] SBADDRESSWrData_1 = 32'h0; // @[SBA.scala:106:38]
wire [31:0] SBADDRESSWrData_2 = 32'h0; // @[SBA.scala:106:38]
wire [31:0] SBADDRESSWrData_3 = 32'h0; // @[SBA.scala:106:38]
wire [31:0] _SBDATARdData_WIRE_0 = 32'h0; // @[SBA.scala:145:43]
wire [31:0] _SBDATARdData_WIRE_1 = 32'h0; // @[SBA.scala:145:43]
wire [31:0] _SBDATARdData_WIRE_2 = 32'h0; // @[SBA.scala:145:43]
wire [31:0] _SBDATARdData_WIRE_3 = 32'h0; // @[SBA.scala:145:43]
wire [31:0] SBDATARdData_2 = 32'h0; // @[SBA.scala:145:35]
wire [31:0] SBDATARdData_3 = 32'h0; // @[SBA.scala:145:35]
wire [31:0] _SBDATAWrData_WIRE_0 = 32'h0; // @[SBA.scala:147:43]
wire [31:0] _SBDATAWrData_WIRE_1 = 32'h0; // @[SBA.scala:147:43]
wire [31:0] _SBDATAWrData_WIRE_2 = 32'h0; // @[SBA.scala:147:43]
wire [31:0] _SBDATAWrData_WIRE_3 = 32'h0; // @[SBA.scala:147:43]
wire [31:0] SBDATAWrData_2 = 32'h0; // @[SBA.scala:147:35]
wire [31:0] SBDATAWrData_3 = 32'h0; // @[SBA.scala:147:35]
wire [31:0] sb2tlOpt_io_dataIn_hi_lo = 32'h0; // @[SBA.scala:175:85]
wire [31:0] sb2tlOpt_io_dataIn_hi_hi = 32'h0; // @[SBA.scala:175:85]
wire [31:0] _out_out_bits_data_WIRE_1_1 = 32'h0; // @[MuxLiteral.scala:49:48]
wire [31:0] _out_out_bits_data_WIRE_1_2 = 32'h0; // @[MuxLiteral.scala:49:48]
wire [31:0] _out_out_bits_data_WIRE_1_3 = 32'h0; // @[MuxLiteral.scala:49:48]
wire [31:0] _out_out_bits_data_WIRE_1_12 = 32'h0; // @[MuxLiteral.scala:49:48]
wire [31:0] _out_out_bits_data_WIRE_1_13 = 32'h0; // @[MuxLiteral.scala:49:48]
wire [31:0] _out_out_bits_data_WIRE_1_14 = 32'h0; // @[MuxLiteral.scala:49:48]
wire [31:0] _out_out_bits_data_WIRE_1_15 = 32'h0; // @[MuxLiteral.scala:49:48]
wire [31:0] _out_out_bits_data_WIRE_1_16 = 32'h0; // @[MuxLiteral.scala:49:48]
wire [31:0] _out_out_bits_data_WIRE_1_18 = 32'h0; // @[MuxLiteral.scala:49:48]
wire [31:0] _out_out_bits_data_WIRE_1_20 = 32'h0; // @[MuxLiteral.scala:49:48]
wire [31:0] _out_out_bits_data_WIRE_1_21 = 32'h0; // @[MuxLiteral.scala:49:48]
wire [31:0] _out_out_bits_data_WIRE_1_25 = 32'h0; // @[MuxLiteral.scala:49:48]
wire [31:0] _out_out_bits_data_WIRE_1_26 = 32'h0; // @[MuxLiteral.scala:49:48]
wire [31:0] _out_out_bits_data_WIRE_1_27 = 32'h0; // @[MuxLiteral.scala:49:48]
wire [31:0] _out_out_bits_data_WIRE_1_28 = 32'h0; // @[MuxLiteral.scala:49:48]
wire [31:0] _out_out_bits_data_WIRE_1_29 = 32'h0; // @[MuxLiteral.scala:49:48]
wire [31:0] _out_out_bits_data_WIRE_1_30 = 32'h0; // @[MuxLiteral.scala:49:48]
wire [31:0] _out_out_bits_data_WIRE_1_31 = 32'h0; // @[MuxLiteral.scala:49:48]
wire [31:0] _out_out_bits_data_WIRE_1_48 = 32'h0; // @[MuxLiteral.scala:49:48]
wire [31:0] _out_out_bits_data_WIRE_1_49 = 32'h0; // @[MuxLiteral.scala:49:48]
wire [31:0] _out_out_bits_data_WIRE_1_50 = 32'h0; // @[MuxLiteral.scala:49:48]
wire [31:0] _out_out_bits_data_WIRE_1_51 = 32'h0; // @[MuxLiteral.scala:49:48]
wire [31:0] _out_out_bits_data_WIRE_1_52 = 32'h0; // @[MuxLiteral.scala:49:48]
wire [31:0] _out_out_bits_data_WIRE_1_53 = 32'h0; // @[MuxLiteral.scala:49:48]
wire [31:0] _out_out_bits_data_WIRE_1_54 = 32'h0; // @[MuxLiteral.scala:49:48]
wire [31:0] _out_out_bits_data_WIRE_1_55 = 32'h0; // @[MuxLiteral.scala:49:48]
wire [31:0] _out_out_bits_data_WIRE_1_58 = 32'h0; // @[MuxLiteral.scala:49:48]
wire [31:0] _out_out_bits_data_WIRE_1_59 = 32'h0; // @[MuxLiteral.scala:49:48]
wire [31:0] _out_out_bits_data_WIRE_1_62 = 32'h0; // @[MuxLiteral.scala:49:48]
wire [31:0] _out_out_bits_data_WIRE_1_63 = 32'h0; // @[MuxLiteral.scala:49:48]
wire [31:0] dmiNodeIn_d_bits_d_data = 32'h0; // @[Edges.scala:792:17]
wire [31:0] _out_prepend_T_420 = 32'h0; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_578 = 32'h0; // @[RegisterRouter.scala:87:24]
wire [5:0] _SBCSFieldsRegReset_WIRE_reserved0 = 6'h0; // @[SBA.scala:49:51]
wire [5:0] SBCSFieldsRegReset_reserved0 = 6'h0; // @[SBA.scala:49:38]
wire [5:0] _SBCSRdData_WIRE_reserved0 = 6'h0; // @[SBA.scala:60:51]
wire [5:0] SBCSRdData_reserved0 = 6'h0; // @[SBA.scala:60:38]
wire [5:0] _SBCSWrData_WIRE_reserved0 = 6'h0; // @[SBA.scala:63:61]
wire [5:0] _SBCSWrData_T_13 = 6'h0; // @[SBA.scala:63:61]
wire [5:0] SBCSWrData_reserved0 = 6'h0; // @[SBA.scala:63:38]
wire [5:0] _SBCSRdData_WIRE_1_reserved0 = 6'h0; // @[SBA.scala:243:33]
wire [5:0] _flags_WIRE_reserved = 6'h0; // @[Debug.scala:1517:87]
wire [5:0] _flags_WIRE_1_reserved = 6'h0; // @[Debug.scala:1517:87]
wire [5:0] _flags_WIRE_2_0_reserved = 6'h0; // @[Debug.scala:1517:33]
wire [5:0] _flags_WIRE_2_1_reserved = 6'h0; // @[Debug.scala:1517:33]
wire [5:0] flags_0_reserved = 6'h0; // @[Debug.scala:1517:25]
wire [5:0] flags_1_reserved = 6'h0; // @[Debug.scala:1517:25]
wire [3:0] _DMSTATUSRdData_WIRE_version = 4'h0; // @[Debug.scala:978:47]
wire [3:0] _DMCS2RdData_WIRE_exttrigger = 4'h0; // @[Debug.scala:1025:47]
wire [3:0] DMCS2RdData_exttrigger = 4'h0; // @[Debug.scala:1025:34]
wire [3:0] _DMCS2WrData_WIRE_exttrigger = 4'h0; // @[Debug.scala:1026:47]
wire [3:0] DMCS2WrData_exttrigger = 4'h0; // @[Debug.scala:1026:34]
wire [3:0] _ABSTRACTCSReset_WIRE_reserved3 = 4'h0; // @[Debug.scala:1179:48]
wire [3:0] _ABSTRACTCSReset_WIRE_datacount = 4'h0; // @[Debug.scala:1179:48]
wire [3:0] ABSTRACTCSReset_reserved3 = 4'h0; // @[Debug.scala:1179:35]
wire [3:0] _ABSTRACTCSWrData_WIRE_reserved3 = 4'h0; // @[Debug.scala:1184:52]
wire [3:0] _ABSTRACTCSWrData_WIRE_datacount = 4'h0; // @[Debug.scala:1184:52]
wire [3:0] ABSTRACTCSWrData_reserved3 = 4'h0; // @[Debug.scala:1184:39]
wire [3:0] ABSTRACTCSWrData_datacount = 4'h0; // @[Debug.scala:1184:39]
wire [3:0] ABSTRACTCSRdData_reserved3 = 4'h0; // @[Debug.scala:1185:39]
wire [3:0] _ABSTRACTAUTOReset_WIRE_reserved0 = 4'h0; // @[Debug.scala:1234:54]
wire [3:0] ABSTRACTAUTOReset_reserved0 = 4'h0; // @[Debug.scala:1234:41]
wire [3:0] _ABSTRACTAUTOWrData_WIRE_reserved0 = 4'h0; // @[Debug.scala:1236:54]
wire [3:0] ABSTRACTAUTOWrData_reserved0 = 4'h0; // @[Debug.scala:1236:41]
wire [3:0] ABSTRACTAUTORdData_reserved0 = 4'h0; // @[Debug.scala:1237:41]
wire [3:0] jalAbstract_imm2_lo = 4'h0; // @[package.scala:45:27]
wire [3:0] jalAbstract_imm2_hi = 4'h0; // @[package.scala:45:27]
wire [7:0] _out_T_1223 = 8'h8; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1224 = 8'h8; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_86 = 8'h8; // @[RegisterRouter.scala:87:24]
wire [4:0] out_prepend_85 = 5'h8; // @[RegisterRouter.scala:87:24]
wire [3:0] ABSTRACTCSReset_datacount = 4'h8; // @[Debug.scala:1179:35]
wire [3:0] ABSTRACTCSRdData_datacount = 4'h8; // @[Debug.scala:1185:39]
wire [3:0] _out_T_1214 = 4'h8; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_T_1215 = 4'h8; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_prepend_T_85 = 4'h8; // @[RegisterRouter.scala:87:24]
wire [15:0] _ABSTRACTAUTOReset_WIRE_autoexecprogbuf = 16'h0; // @[Debug.scala:1234:54]
wire [15:0] ABSTRACTAUTOReset_autoexecprogbuf = 16'h0; // @[Debug.scala:1234:41]
wire [15:0] _ABSTRACTAUTOWrData_WIRE_autoexecprogbuf = 16'h0; // @[Debug.scala:1236:54]
wire [15:0] sb2tlOpt_io_dataIn_hi_lo_lo = 16'h0; // @[SBA.scala:175:85]
wire [15:0] sb2tlOpt_io_dataIn_hi_lo_hi = 16'h0; // @[SBA.scala:175:85]
wire [15:0] sb2tlOpt_io_dataIn_hi_hi_lo = 16'h0; // @[SBA.scala:175:85]
wire [15:0] sb2tlOpt_io_dataIn_hi_hi_hi = 16'h0; // @[SBA.scala:175:85]
wire [95:0] _sb2tlOpt_io_addrIn_T = 96'h0; // @[SBA.scala:132:14]
wire [2:0] SBCSFieldsRegReset_sbversion = 3'h1; // @[SBA.scala:49:38]
wire [2:0] SBCSRdData_sbversion = 3'h1; // @[SBA.scala:60:38]
wire [10:0] _ABSTRACTCSReset_WIRE_reserved1 = 11'h0; // @[Debug.scala:1179:48]
wire [10:0] ABSTRACTCSReset_reserved1 = 11'h0; // @[Debug.scala:1179:35]
wire [10:0] _ABSTRACTCSWrData_WIRE_reserved1 = 11'h0; // @[Debug.scala:1184:52]
wire [10:0] ABSTRACTCSWrData_reserved1 = 11'h0; // @[Debug.scala:1184:39]
wire [10:0] ABSTRACTCSRdData_reserved1 = 11'h0; // @[Debug.scala:1185:39]
wire [4:0] ABSTRACTCSReset_progbufsize = 5'h10; // @[Debug.scala:1179:35]
wire [4:0] ABSTRACTCSRdData_progbufsize = 5'h10; // @[Debug.scala:1185:39]
wire [7:0] _COMMANDReset_WIRE_cmdtype = 8'h0; // @[Debug.scala:1276:45]
wire [7:0] COMMANDReset_cmdtype = 8'h0; // @[Debug.scala:1276:32]
wire [7:0] _jalAbstract_WIRE_imm2 = 8'h0; // @[Debug.scala:1497:66]
wire [7:0] jalAbstract_imm2 = 8'h0; // @[Debug.scala:1497:32]
wire [7:0] _jalAbstract_imm2_T = 8'h0; // @[package.scala:45:27]
wire [6:0] SBCSFieldsRegReset_sbasize = 7'h20; // @[SBA.scala:49:38]
wire [6:0] SBCSRdData_sbasize = 7'h20; // @[SBA.scala:60:38]
wire [1:0] auto_tl_in_d_bits_param = 2'h0; // @[Debug.scala:790:9]
wire [1:0] auto_dmi_in_d_bits_param = 2'h0; // @[Debug.scala:790:9]
wire [1:0] dmiNodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17]
wire [1:0] tlNodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17]
wire [1:0] _DMSTATUSRdData_WIRE_reserved1 = 2'h0; // @[Debug.scala:978:47]
wire [1:0] DMSTATUSRdData_reserved1 = 2'h0; // @[Debug.scala:978:34]
wire [1:0] _haltedBitRegs_T_4 = 2'h0; // @[Debug.scala:1330:43]
wire [1:0] _haltedBitRegs_T_6 = 2'h0; // @[Debug.scala:1330:69]
wire [1:0] _resumeReqRegs_T_3 = 2'h0; // @[Debug.scala:1338:43]
wire [1:0] _resumeReqRegs_T_5 = 2'h0; // @[Debug.scala:1338:69]
wire [1:0] dmiNodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:792:17]
wire [1:0] jalAbstract_imm0_lo_lo = 2'h0; // @[package.scala:45:27]
wire [1:0] jalAbstract_imm0_hi_lo = 2'h0; // @[package.scala:45:27]
wire [1:0] jalAbstract_imm0_hi_hi_hi = 2'h0; // @[package.scala:45:27]
wire [1:0] jalAbstract_imm1_lo_lo = 2'h0; // @[package.scala:45:27]
wire [1:0] jalAbstract_imm1_lo_hi_hi = 2'h0; // @[package.scala:45:27]
wire [1:0] jalAbstract_imm1_hi_lo = 2'h0; // @[package.scala:45:27]
wire [1:0] jalAbstract_imm1_hi_hi_hi = 2'h0; // @[package.scala:45:27]
wire [1:0] jalAbstract_imm2_lo_lo = 2'h0; // @[package.scala:45:27]
wire [1:0] jalAbstract_imm2_lo_hi = 2'h0; // @[package.scala:45:27]
wire [1:0] jalAbstract_imm2_hi_lo = 2'h0; // @[package.scala:45:27]
wire [1:0] jalAbstract_imm2_hi_hi = 2'h0; // @[package.scala:45:27]
wire [1:0] tlNodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:792:17]
wire [63:0] _out_out_bits_data_WIRE_3_96 = 64'h380006F; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_3_10 = 64'h100073; // @[MuxLiteral.scala:49:48]
wire [63:0] out_prepend_349 = 64'h100026237B200073; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_4404 = 64'h100026237B200073; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_4405 = 64'h100026237B200073; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_9 = 64'h100026237B200073; // @[MuxLiteral.scala:49:48]
wire [63:0] out_prepend_592 = 64'h7B20247310802423; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_6965 = 64'h7B20247310802423; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_6966 = 64'h7B20247310802423; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_8 = 64'h7B20247310802423; // @[MuxLiteral.scala:49:48]
wire [63:0] out_prepend_866 = 64'hF140247330000067; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_9839 = 64'hF140247330000067; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_9840 = 64'hF140247330000067; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_7 = 64'hF140247330000067; // @[MuxLiteral.scala:49:48]
wire [63:0] out_prepend_1055 = 64'h100022237B202473; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_11815 = 64'h100022237B202473; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_11816 = 64'h100022237B202473; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_6 = 64'h100022237B202473; // @[MuxLiteral.scala:49:48]
wire [63:0] out_prepend_258 = 64'h4086300147413; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_3452 = 64'h4086300147413; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_3453 = 64'h4086300147413; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_5 = 64'h4086300147413; // @[MuxLiteral.scala:49:48]
wire [63:0] out_prepend_391 = 64'hFE0408E300347413; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_4836 = 64'hFE0408E300347413; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_4837 = 64'hFE0408E300347413; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_4 = 64'hFE0408E300347413; // @[MuxLiteral.scala:49:48]
wire [63:0] out_prepend_641 = 64'h4004440310802023; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_7469 = 64'h4004440310802023; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_7470 = 64'h4004440310802023; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_3 = 64'h4004440310802023; // @[MuxLiteral.scala:49:48]
wire [63:0] out_prepend_950 = 64'hF14024737B241073; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_10719 = 64'hF14024737B241073; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_10720 = 64'hF14024737B241073; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_2 = 64'hF14024737B241073; // @[MuxLiteral.scala:49:48]
wire [63:0] out_prepend_202 = 64'hFF0000F0440006F; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_2860 = 64'hFF0000F0440006F; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_2861 = 64'hFF0000F0440006F; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_1 = 64'hFF0000F0440006F; // @[MuxLiteral.scala:49:48]
wire [63:0] out_prepend_511 = 64'h380006F00C0006F; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_6103 = 64'h380006F00C0006F; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_6104 = 64'h380006F00C0006F; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_0 = 64'h380006F00C0006F; // @[MuxLiteral.scala:49:48]
wire [55:0] out_prepend_1054 = 56'h22237B202473; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_11806 = 56'h22237B202473; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_11807 = 56'h22237B202473; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_1055 = 56'h22237B202473; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_1053 = 48'h22237B202473; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_11797 = 48'h22237B202473; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_11798 = 48'h22237B202473; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_1054 = 48'h22237B202473; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_1052 = 40'h237B202473; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_11788 = 40'h237B202473; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_11789 = 40'h237B202473; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_1053 = 40'h237B202473; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_1051 = 32'h7B202473; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_11779 = 32'h7B202473; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_11780 = 32'h7B202473; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_1052 = 32'h7B202473; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_1050 = 24'h202473; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_11770 = 24'h202473; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_11771 = 24'h202473; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_1051 = 24'h202473; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_1049 = 16'h2473; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_11761 = 16'h2473; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_11762 = 16'h2473; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_1050 = 16'h2473; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4341 = 8'h73; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4342 = 8'h73; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_343 = 8'h73; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6328 = 8'h73; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6329 = 8'h73; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_533 = 8'h73; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10656 = 8'h73; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10657 = 8'h73; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_944 = 8'h73; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11752 = 8'h73; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11753 = 8'h73; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_1049 = 8'h73; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_949 = 56'h4024737B241073; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_10710 = 56'h4024737B241073; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_10711 = 56'h4024737B241073; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_950 = 56'h4024737B241073; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_948 = 48'h24737B241073; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_10701 = 48'h24737B241073; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_10702 = 48'h24737B241073; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_949 = 48'h24737B241073; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_947 = 40'h737B241073; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_10692 = 40'h737B241073; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_10693 = 40'h737B241073; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_948 = 40'h737B241073; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_946 = 32'h7B241073; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_10683 = 32'h7B241073; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_10684 = 32'h7B241073; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_947 = 32'h7B241073; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_945 = 24'h241073; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_10674 = 24'h241073; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_10675 = 24'h241073; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_946 = 24'h241073; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_944 = 16'h1073; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_10665 = 16'h1073; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_10666 = 16'h1073; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_945 = 16'h1073; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_865 = 56'h40247330000067; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_9830 = 56'h40247330000067; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_9831 = 56'h40247330000067; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_866 = 56'h40247330000067; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_864 = 48'h247330000067; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_9821 = 48'h247330000067; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_9822 = 48'h247330000067; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_865 = 48'h247330000067; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_863 = 40'h7330000067; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_9812 = 40'h7330000067; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_9813 = 40'h7330000067; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_864 = 40'h7330000067; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_862 = 32'h30000067; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_9803 = 32'h30000067; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_9804 = 32'h30000067; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_863 = 32'h30000067; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_861 = 24'h67; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_9794 = 24'h67; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_9795 = 24'h67; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_862 = 24'h67; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_860 = 16'h67; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_9785 = 16'h67; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_9786 = 16'h67; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_861 = 16'h67; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9776 = 8'h67; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9777 = 8'h67; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_860 = 8'h67; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_640 = 56'h4440310802023; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_7460 = 56'h4440310802023; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_7461 = 56'h4440310802023; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_641 = 56'h4440310802023; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_639 = 48'h440310802023; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_7451 = 48'h440310802023; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_7452 = 48'h440310802023; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_640 = 48'h440310802023; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_638 = 40'h310802023; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_7442 = 40'h310802023; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_7443 = 40'h310802023; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_639 = 40'h310802023; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_637 = 32'h10802023; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_7433 = 32'h10802023; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_7434 = 32'h10802023; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_638 = 32'h10802023; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_636 = 24'h802023; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_7424 = 24'h802023; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_7425 = 24'h802023; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_637 = 24'h802023; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_635 = 16'h2023; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_7415 = 16'h2023; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_7416 = 16'h2023; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_636 = 16'h2023; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6902 = 8'h23; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6903 = 8'h23; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_586 = 8'h23; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7406 = 8'h23; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7407 = 8'h23; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_635 = 8'h23; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_591 = 56'h20247310802423; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_6956 = 56'h20247310802423; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_6957 = 56'h20247310802423; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_592 = 56'h20247310802423; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_590 = 48'h247310802423; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_6947 = 48'h247310802423; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_6948 = 48'h247310802423; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_591 = 48'h247310802423; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_589 = 40'h7310802423; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_6938 = 40'h7310802423; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_6939 = 40'h7310802423; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_590 = 40'h7310802423; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_588 = 32'h10802423; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_6929 = 32'h10802423; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_6930 = 32'h10802423; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_589 = 32'h10802423; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_587 = 24'h802423; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_6920 = 24'h802423; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_6921 = 24'h802423; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_588 = 24'h802423; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_586 = 16'h2423; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_6911 = 16'h2423; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_6912 = 16'h2423; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_587 = 16'h2423; // @[RegisterRouter.scala:87:24]
wire [41:0] _out_T_5142 = 42'h0; // @[RegisterRouter.scala:87:24]
wire [41:0] _out_T_5143 = 42'h0; // @[RegisterRouter.scala:87:24]
wire [41:0] _out_T_6821 = 42'h0; // @[RegisterRouter.scala:87:24]
wire [41:0] _out_T_6822 = 42'h0; // @[RegisterRouter.scala:87:24]
wire [32:0] out_prepend_420 = 33'h0; // @[RegisterRouter.scala:87:24]
wire [32:0] out_prepend_578 = 33'h0; // @[RegisterRouter.scala:87:24]
wire [9:0] _jalAbstract_WIRE_imm0 = 10'h0; // @[Debug.scala:1497:66]
wire [9:0] _jalAbstract_imm1_T = 10'h0; // @[package.scala:45:27]
wire [9:0] _out_T_5133 = 10'h0; // @[RegisterRouter.scala:87:24]
wire [9:0] _out_T_5134 = 10'h0; // @[RegisterRouter.scala:87:24]
wire [9:0] _out_T_6812 = 10'h0; // @[RegisterRouter.scala:87:24]
wire [9:0] _out_T_6813 = 10'h0; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_535 = 32'h100073; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_6355 = 32'h100073; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_6356 = 32'h100073; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_534 = 24'h100073; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_6346 = 24'h100073; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_6347 = 24'h100073; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_535 = 24'h100073; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_343 = 16'h73; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_4350 = 16'h73; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_4351 = 16'h73; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_344 = 16'h73; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_533 = 16'h73; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_6337 = 16'h73; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_6338 = 16'h73; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_534 = 16'h73; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_510 = 56'h80006F00C0006F; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_6094 = 56'h80006F00C0006F; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_6095 = 56'h80006F00C0006F; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_511 = 56'h80006F00C0006F; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_509 = 48'h6F00C0006F; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_6085 = 48'h6F00C0006F; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_6086 = 48'h6F00C0006F; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_510 = 48'h6F00C0006F; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_508 = 40'h6F00C0006F; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_6076 = 40'h6F00C0006F; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_6077 = 40'h6F00C0006F; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_509 = 40'h6F00C0006F; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_507 = 32'hC0006F; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_6067 = 32'hC0006F; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_6068 = 32'hC0006F; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_508 = 32'hC0006F; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_506 = 24'hC0006F; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_6058 = 24'hC0006F; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_6059 = 24'hC0006F; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_507 = 24'hC0006F; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_196 = 16'h6F; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_2806 = 16'h6F; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_2807 = 16'h6F; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_197 = 16'h6F; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_505 = 16'h6F; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_6049 = 16'h6F; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_6050 = 16'h6F; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_506 = 16'h6F; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2797 = 8'h6F; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2798 = 8'h6F; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_196 = 8'h6F; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6040 = 8'h6F; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6041 = 8'h6F; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_505 = 8'h6F; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_5943 = 32'h380006F; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_5944 = 32'h380006F; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_390 = 56'h408E300347413; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_4827 = 56'h408E300347413; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_4828 = 56'h408E300347413; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_391 = 56'h408E300347413; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_389 = 48'h8E300347413; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_4818 = 48'h8E300347413; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_4819 = 48'h8E300347413; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_390 = 48'h8E300347413; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_388 = 40'hE300347413; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_4809 = 40'hE300347413; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_4810 = 40'hE300347413; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_389 = 40'hE300347413; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_387 = 32'h347413; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_4800 = 32'h347413; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_4801 = 32'h347413; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_388 = 32'h347413; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_386 = 24'h347413; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_4791 = 24'h347413; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_4792 = 24'h347413; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_387 = 24'h347413; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_252 = 16'h7413; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_3398 = 16'h7413; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_3399 = 16'h7413; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_253 = 16'h7413; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_385 = 16'h7413; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_4782 = 16'h7413; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_4783 = 16'h7413; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_386 = 16'h7413; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3389 = 8'h13; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3390 = 8'h13; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_252 = 8'h13; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4773 = 8'h13; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4774 = 8'h13; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_385 = 8'h13; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_348 = 56'h26237B200073; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_4395 = 56'h26237B200073; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_4396 = 56'h26237B200073; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_349 = 56'h26237B200073; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_347 = 48'h26237B200073; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_4386 = 48'h26237B200073; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_4387 = 48'h26237B200073; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_348 = 48'h26237B200073; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_346 = 40'h237B200073; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_4377 = 40'h237B200073; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_4378 = 40'h237B200073; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_347 = 40'h237B200073; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_345 = 32'h7B200073; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_4368 = 32'h7B200073; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_4369 = 32'h7B200073; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_346 = 32'h7B200073; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_344 = 24'h200073; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_4359 = 24'h200073; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_4360 = 24'h200073; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_345 = 24'h200073; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_257 = 56'h4086300147413; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_3443 = 56'h4086300147413; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_3444 = 56'h4086300147413; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_258 = 56'h4086300147413; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_256 = 48'h86300147413; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_3434 = 48'h86300147413; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_3435 = 48'h86300147413; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_257 = 48'h86300147413; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_255 = 40'h6300147413; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_3425 = 40'h6300147413; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_3426 = 40'h6300147413; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_256 = 40'h6300147413; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_254 = 32'h147413; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_3416 = 32'h147413; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_3417 = 32'h147413; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_255 = 32'h147413; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_253 = 24'h147413; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_3407 = 24'h147413; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_3408 = 24'h147413; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_254 = 24'h147413; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_201 = 56'hF0000F0440006F; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_2851 = 56'hF0000F0440006F; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_2852 = 56'hF0000F0440006F; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_202 = 56'hF0000F0440006F; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_200 = 48'hF0440006F; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_2842 = 48'hF0440006F; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_2843 = 48'hF0440006F; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_201 = 48'hF0440006F; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_199 = 40'hF0440006F; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_2833 = 40'hF0440006F; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_2834 = 40'hF0440006F; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_200 = 40'hF0440006F; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_198 = 32'h440006F; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_2824 = 32'h440006F; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_2825 = 32'h440006F; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_199 = 32'h440006F; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_197 = 24'h40006F; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_2815 = 24'h40006F; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_2816 = 24'h40006F; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_198 = 24'h40006F; // @[RegisterRouter.scala:87:24]
wire [8:0] out_maskMatch_1 = 9'h100; // @[RegisterRouter.scala:87:24]
wire [11:0] hi = 12'h38; // @[Debug.scala:1697:55]
wire [10:0] hi_hi = 11'h1C; // @[Debug.scala:1697:55]
wire [19:0] lo = 20'h6F; // @[Debug.scala:1697:55]
wire [12:0] lo_hi = 13'h0; // @[Debug.scala:1697:55]
wire [31:0] _abstractGeneratedMem_0_T_3 = 32'h13; // @[Debug.scala:1642:15]
wire [31:0] _abstractGeneratedMem_1_T = 32'h13; // @[Debug.scala:1645:15]
wire [19:0] abstractGeneratedMem_0_hi_2 = 20'h0; // @[Debug.scala:1642:15]
wire [19:0] abstractGeneratedMem_1_hi = 20'h0; // @[Debug.scala:1645:15]
wire [16:0] abstractGeneratedMem_0_hi_hi_2 = 17'h0; // @[Debug.scala:1642:15]
wire [16:0] abstractGeneratedMem_1_hi_hi = 17'h0; // @[Debug.scala:1645:15]
wire [11:0] abstractGeneratedMem_0_lo_2 = 12'h13; // @[Debug.scala:1642:15]
wire [11:0] abstractGeneratedMem_1_lo = 12'h13; // @[Debug.scala:1645:15]
wire [6:0] abstractGeneratedMem_0_inst_1_opcode = 7'h23; // @[Debug.scala:1601:22]
wire [6:0] _abstractGeneratedMem_0_inst_opcode_WIRE_1_opcode = 7'h23; // @[Debug.scala:1604:55]
wire [4:0] _DMCS2RdData_WIRE_haltgroup = 5'h0; // @[Debug.scala:1025:47]
wire [4:0] DMCS2RdData_haltgroup = 5'h0; // @[Debug.scala:1025:34]
wire [4:0] _DMCS2WrData_WIRE_haltgroup = 5'h0; // @[Debug.scala:1026:47]
wire [4:0] DMCS2WrData_haltgroup = 5'h0; // @[Debug.scala:1026:34]
wire [4:0] _ABSTRACTCSReset_WIRE_progbufsize = 5'h0; // @[Debug.scala:1179:48]
wire [4:0] _ABSTRACTCSWrData_WIRE_progbufsize = 5'h0; // @[Debug.scala:1184:52]
wire [4:0] ABSTRACTCSWrData_progbufsize = 5'h0; // @[Debug.scala:1184:39]
wire [4:0] _jalAbstract_WIRE_rd = 5'h0; // @[Debug.scala:1497:66]
wire [4:0] jalAbstract_rd = 5'h0; // @[Debug.scala:1497:32]
wire [4:0] jalAbstract_imm0_hi = 5'h0; // @[package.scala:45:27]
wire [4:0] jalAbstract_imm1_lo = 5'h0; // @[package.scala:45:27]
wire [4:0] jalAbstract_imm1_hi = 5'h0; // @[package.scala:45:27]
wire [4:0] nop_rs1 = 5'h0; // @[Debug.scala:1623:19]
wire [4:0] nop_rd = 5'h0; // @[Debug.scala:1623:19]
wire [4:0] _nop_WIRE_rs1 = 5'h0; // @[Debug.scala:1624:46]
wire [4:0] _nop_WIRE_rd = 5'h0; // @[Debug.scala:1624:46]
wire [4:0] isa_rs1 = 5'h0; // @[Debug.scala:1629:19]
wire [4:0] isa_rd = 5'h0; // @[Debug.scala:1629:19]
wire [4:0] _isa_WIRE_rs1 = 5'h0; // @[Debug.scala:1630:47]
wire [4:0] _isa_WIRE_rd = 5'h0; // @[Debug.scala:1630:47]
wire [4:0] abstractGeneratedMem_0_inst_rs1 = 5'h0; // @[Debug.scala:1589:22]
wire [4:0] _abstractGeneratedMem_0_inst_opcode_WIRE_rs1 = 5'h0; // @[Debug.scala:1592:55]
wire [4:0] _abstractGeneratedMem_0_inst_opcode_WIRE_rd = 5'h0; // @[Debug.scala:1592:55]
wire [4:0] abstractGeneratedMem_0_inst_1_rs1 = 5'h0; // @[Debug.scala:1601:22]
wire [4:0] abstractGeneratedMem_0_inst_1_immlo = 5'h0; // @[Debug.scala:1601:22]
wire [4:0] _abstractGeneratedMem_0_inst_opcode_WIRE_1_rs2 = 5'h0; // @[Debug.scala:1604:55]
wire [4:0] _abstractGeneratedMem_0_inst_opcode_WIRE_1_rs1 = 5'h0; // @[Debug.scala:1604:55]
wire [4:0] _abstractGeneratedMem_0_inst_opcode_WIRE_1_immlo = 5'h0; // @[Debug.scala:1604:55]
wire [2:0] SBCSFieldsRegReset_sbaccess = 3'h2; // @[SBA.scala:49:38]
wire [2:0] _abstractGeneratedMem_0_inst_opcode_WIRE_funct3 = 3'h2; // @[Debug.scala:1592:55]
wire [2:0] _abstractGeneratedMem_0_inst_opcode_WIRE_1_funct3 = 3'h2; // @[Debug.scala:1604:55]
wire [6:0] _SBCSFieldsRegReset_WIRE_sbasize = 7'h0; // @[SBA.scala:49:51]
wire [6:0] _SBCSRdData_WIRE_sbasize = 7'h0; // @[SBA.scala:60:51]
wire [6:0] _SBCSWrData_WIRE_sbasize = 7'h0; // @[SBA.scala:63:61]
wire [6:0] _SBCSWrData_T_5 = 7'h0; // @[SBA.scala:63:61]
wire [6:0] SBCSWrData_sbasize = 7'h0; // @[SBA.scala:63:38]
wire [6:0] _SBCSRdData_WIRE_1_sbasize = 7'h0; // @[SBA.scala:243:33]
wire [6:0] _abstractGeneratedMem_0_inst_opcode_WIRE_1_immhi = 7'h0; // @[Debug.scala:1604:55]
wire [6:0] abstractGeneratedMem_0_inst_1_immhi = 7'h1C; // @[Debug.scala:1601:22]
wire [16:0] abstractGeneratedMem_0_hi_hi = 17'h7000; // @[Debug.scala:1597:12]
wire [6:0] abstractGeneratedMem_0_inst_opcode = 7'h3; // @[Debug.scala:1589:22]
wire [6:0] _abstractGeneratedMem_0_inst_opcode_WIRE_opcode = 7'h3; // @[Debug.scala:1592:55]
wire [11:0] _ABSTRACTAUTOReset_WIRE_autoexecdata = 12'h0; // @[Debug.scala:1234:54]
wire [11:0] ABSTRACTAUTOReset_autoexecdata = 12'h0; // @[Debug.scala:1234:41]
wire [11:0] _ABSTRACTAUTOWrData_WIRE_autoexecdata = 12'h0; // @[Debug.scala:1236:54]
wire [11:0] nop_imm = 12'h0; // @[Debug.scala:1623:19]
wire [11:0] _nop_WIRE_imm = 12'h0; // @[Debug.scala:1624:46]
wire [11:0] isa_imm = 12'h0; // @[Debug.scala:1629:19]
wire [11:0] _isa_WIRE_imm = 12'h0; // @[Debug.scala:1630:47]
wire [11:0] _abstractGeneratedMem_0_inst_opcode_WIRE_imm = 12'h0; // @[Debug.scala:1592:55]
wire [11:0] abstractGeneratedMem_0_inst_imm = 12'h380; // @[Debug.scala:1589:22]
wire [6:0] isa_opcode = 7'h1B; // @[Debug.scala:1629:19]
wire [6:0] _isa_WIRE_opcode = 7'h1B; // @[Debug.scala:1630:47]
wire [6:0] nop_opcode = 7'h13; // @[Debug.scala:1623:19]
wire [6:0] _nop_WIRE_opcode = 7'h13; // @[Debug.scala:1624:46]
wire [9:0] jalAbstract_imm0 = 10'h1C; // @[Debug.scala:1497:32]
wire [9:0] _jalAbstract_imm0_T = 10'h1C; // @[package.scala:45:27]
wire [4:0] jalAbstract_imm0_lo = 5'h1C; // @[package.scala:45:27]
wire [2:0] out_prepend_25 = 3'h7; // @[RegisterRouter.scala:87:24]
wire [2:0] _out_T_456 = 3'h7; // @[RegisterRouter.scala:87:24]
wire [2:0] _out_T_457 = 3'h7; // @[RegisterRouter.scala:87:24]
wire [2:0] _out_prepend_T_26 = 3'h7; // @[RegisterRouter.scala:87:24]
wire [2:0] jalAbstract_imm0_lo_hi = 3'h7; // @[package.scala:45:27]
wire [1:0] out_prepend_24 = 2'h3; // @[RegisterRouter.scala:87:24]
wire [1:0] _out_T_447 = 2'h3; // @[RegisterRouter.scala:87:24]
wire [1:0] _out_T_448 = 2'h3; // @[RegisterRouter.scala:87:24]
wire [1:0] _out_prepend_T_25 = 2'h3; // @[RegisterRouter.scala:87:24]
wire [1:0] jalAbstract_imm0_lo_hi_hi = 2'h3; // @[package.scala:45:27]
wire [20:0] immWire = 21'h38; // @[Debug.scala:1574:31]
wire [6:0] _jalAbstract_WIRE_opcode = 7'h6F; // @[Debug.scala:1497:66]
wire [6:0] jalAbstract_opcode = 7'h6F; // @[Debug.scala:1497:32]
wire [7:0] out_prepend_64 = 8'hA2; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_991 = 8'hA2; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_992 = 8'hA2; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_65 = 8'hA2; // @[RegisterRouter.scala:87:24]
wire [6:0] out_prepend_63 = 7'h22; // @[RegisterRouter.scala:87:24]
wire [6:0] _out_T_982 = 7'h22; // @[RegisterRouter.scala:87:24]
wire [6:0] _out_T_983 = 7'h22; // @[RegisterRouter.scala:87:24]
wire [6:0] _out_prepend_T_64 = 7'h22; // @[RegisterRouter.scala:87:24]
wire [5:0] out_prepend_62 = 6'h22; // @[RegisterRouter.scala:87:24]
wire [5:0] _out_T_973 = 6'h22; // @[RegisterRouter.scala:87:24]
wire [5:0] _out_T_974 = 6'h22; // @[RegisterRouter.scala:87:24]
wire [5:0] _out_prepend_T_63 = 6'h22; // @[RegisterRouter.scala:87:24]
wire [4:0] out_prepend_61 = 5'h2; // @[RegisterRouter.scala:87:24]
wire [4:0] _out_T_964 = 5'h2; // @[RegisterRouter.scala:87:24]
wire [4:0] _out_T_965 = 5'h2; // @[RegisterRouter.scala:87:24]
wire [4:0] _out_prepend_T_62 = 5'h2; // @[RegisterRouter.scala:87:24]
wire [3:0] DMSTATUSRdData_version = 4'h2; // @[Debug.scala:978:34]
wire [3:0] _out_T_955 = 4'h2; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_T_956 = 4'h2; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_prepend_T_61 = 4'h2; // @[RegisterRouter.scala:87:24]
wire [11:0] out_prepend_28 = 12'h40F; // @[RegisterRouter.scala:87:24]
wire [11:0] _out_T_483 = 12'h40F; // @[RegisterRouter.scala:87:24]
wire [11:0] _out_T_484 = 12'h40F; // @[RegisterRouter.scala:87:24]
wire [11:0] _out_prepend_T_29 = 12'h40F; // @[RegisterRouter.scala:87:24]
wire [4:0] out_prepend_27 = 5'hF; // @[RegisterRouter.scala:87:24]
wire [4:0] _out_T_474 = 5'hF; // @[RegisterRouter.scala:87:24]
wire [4:0] _out_T_475 = 5'hF; // @[RegisterRouter.scala:87:24]
wire [4:0] _out_prepend_T_28 = 5'hF; // @[RegisterRouter.scala:87:24]
wire [3:0] out_prepend_26 = 4'hF; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_T_465 = 4'hF; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_T_466 = 4'hF; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_prepend_T_27 = 4'hF; // @[RegisterRouter.scala:87:24]
wire [6:0] out_maskMatch = 7'h40; // @[RegisterRouter.scala:87:24]
wire [1:0] _haltedBitRegs_T_3 = 2'h2; // @[Debug.scala:1330:45]
wire [1:0] _resumeReqRegs_T_2 = 2'h2; // @[Debug.scala:1338:45]
wire [1:0] hartHaltedIdIndex = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] hartResumingIdIndex = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _haltedBitRegs_T = 2'h1; // @[Debug.scala:1327:43]
wire [23:0] _COMMANDReset_WIRE_control = 24'h0; // @[Debug.scala:1276:45]
wire [23:0] COMMANDReset_control = 24'h0; // @[Debug.scala:1276:32]
wire [20:0] _DMCS2RdData_WIRE_reserved0 = 21'h0; // @[Debug.scala:1025:47]
wire [20:0] DMCS2RdData_reserved0 = 21'h0; // @[Debug.scala:1025:34]
wire [20:0] _DMCS2WrData_WIRE_reserved0 = 21'h0; // @[Debug.scala:1026:47]
wire [20:0] DMCS2WrData_reserved0 = 21'h0; // @[Debug.scala:1026:34]
wire [8:0] _DMSTATUSRdData_WIRE_reserved0 = 9'h0; // @[Debug.scala:978:47]
wire [8:0] DMSTATUSRdData_reserved0 = 9'h0; // @[Debug.scala:978:34]
wire tlNodeIn_a_ready; // @[MixedNode.scala:551:17]
wire tlNodeIn_a_valid = auto_tl_in_a_valid_0; // @[Debug.scala:790:9]
wire [2:0] tlNodeIn_a_bits_opcode = auto_tl_in_a_bits_opcode_0; // @[Debug.scala:790:9]
wire [2:0] tlNodeIn_a_bits_param = auto_tl_in_a_bits_param_0; // @[Debug.scala:790:9]
wire [1:0] tlNodeIn_a_bits_size = auto_tl_in_a_bits_size_0; // @[Debug.scala:790:9]
wire [10:0] tlNodeIn_a_bits_source = auto_tl_in_a_bits_source_0; // @[Debug.scala:790:9]
wire [11:0] tlNodeIn_a_bits_address = auto_tl_in_a_bits_address_0; // @[Debug.scala:790:9]
wire [7:0] tlNodeIn_a_bits_mask = auto_tl_in_a_bits_mask_0; // @[Debug.scala:790:9]
wire [63:0] tlNodeIn_a_bits_data = auto_tl_in_a_bits_data_0; // @[Debug.scala:790:9]
wire tlNodeIn_a_bits_corrupt = auto_tl_in_a_bits_corrupt_0; // @[Debug.scala:790:9]
wire tlNodeIn_d_ready = auto_tl_in_d_ready_0; // @[Debug.scala:790:9]
wire tlNodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] tlNodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] tlNodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [10:0] tlNodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [63:0] tlNodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire dmiNodeIn_a_ready; // @[MixedNode.scala:551:17]
wire dmiNodeIn_a_valid = auto_dmi_in_a_valid_0; // @[Debug.scala:790:9]
wire [2:0] dmiNodeIn_a_bits_opcode = auto_dmi_in_a_bits_opcode_0; // @[Debug.scala:790:9]
wire [2:0] dmiNodeIn_a_bits_param = auto_dmi_in_a_bits_param_0; // @[Debug.scala:790:9]
wire [1:0] dmiNodeIn_a_bits_size = auto_dmi_in_a_bits_size_0; // @[Debug.scala:790:9]
wire dmiNodeIn_a_bits_source = auto_dmi_in_a_bits_source_0; // @[Debug.scala:790:9]
wire [8:0] dmiNodeIn_a_bits_address = auto_dmi_in_a_bits_address_0; // @[Debug.scala:790:9]
wire [3:0] dmiNodeIn_a_bits_mask = auto_dmi_in_a_bits_mask_0; // @[Debug.scala:790:9]
wire [31:0] dmiNodeIn_a_bits_data = auto_dmi_in_a_bits_data_0; // @[Debug.scala:790:9]
wire dmiNodeIn_a_bits_corrupt = auto_dmi_in_a_bits_corrupt_0; // @[Debug.scala:790:9]
wire dmiNodeIn_d_ready = auto_dmi_in_d_ready_0; // @[Debug.scala:790:9]
wire dmiNodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] dmiNodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] dmiNodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire dmiNodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [31:0] dmiNodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire _resumereq_T = io_innerCtrl_valid_0; // @[Decoupled.scala:51:35]
wire hrDebugInt_0; // @[Debug.scala:946:26]
wire [2:0] auto_sb2tlOpt_out_a_bits_opcode_0; // @[Debug.scala:790:9]
wire [3:0] auto_sb2tlOpt_out_a_bits_size_0; // @[Debug.scala:790:9]
wire [31:0] auto_sb2tlOpt_out_a_bits_address_0; // @[Debug.scala:790:9]
wire [7:0] auto_sb2tlOpt_out_a_bits_data_0; // @[Debug.scala:790:9]
wire auto_sb2tlOpt_out_a_valid_0; // @[Debug.scala:790:9]
wire auto_sb2tlOpt_out_d_ready_0; // @[Debug.scala:790:9]
wire auto_tl_in_a_ready_0; // @[Debug.scala:790:9]
wire [2:0] auto_tl_in_d_bits_opcode_0; // @[Debug.scala:790:9]
wire [1:0] auto_tl_in_d_bits_size_0; // @[Debug.scala:790:9]
wire [10:0] auto_tl_in_d_bits_source_0; // @[Debug.scala:790:9]
wire [63:0] auto_tl_in_d_bits_data_0; // @[Debug.scala:790:9]
wire auto_tl_in_d_valid_0; // @[Debug.scala:790:9]
wire auto_dmi_in_a_ready_0; // @[Debug.scala:790:9]
wire [2:0] auto_dmi_in_d_bits_opcode_0; // @[Debug.scala:790:9]
wire [1:0] auto_dmi_in_d_bits_size_0; // @[Debug.scala:790:9]
wire auto_dmi_in_d_bits_source_0; // @[Debug.scala:790:9]
wire [31:0] auto_dmi_in_d_bits_data_0; // @[Debug.scala:790:9]
wire auto_dmi_in_d_valid_0; // @[Debug.scala:790:9]
wire io_hgDebugInt_0_0; // @[Debug.scala:790:9]
wire in_ready; // @[RegisterRouter.scala:73:18]
assign auto_dmi_in_a_ready_0 = dmiNodeIn_a_ready; // @[Debug.scala:790:9]
wire in_valid = dmiNodeIn_a_valid; // @[RegisterRouter.scala:73:18]
wire [1:0] in_bits_extra_tlrr_extra_size = dmiNodeIn_a_bits_size; // @[RegisterRouter.scala:73:18]
wire in_bits_extra_tlrr_extra_source = dmiNodeIn_a_bits_source; // @[RegisterRouter.scala:73:18]
wire [3:0] in_bits_mask = dmiNodeIn_a_bits_mask; // @[RegisterRouter.scala:73:18]
wire [31:0] in_bits_data = dmiNodeIn_a_bits_data; // @[RegisterRouter.scala:73:18]
wire out_ready = dmiNodeIn_d_ready; // @[RegisterRouter.scala:87:24]
wire out_valid; // @[RegisterRouter.scala:87:24]
assign auto_dmi_in_d_valid_0 = dmiNodeIn_d_valid; // @[Debug.scala:790:9]
assign auto_dmi_in_d_bits_opcode_0 = dmiNodeIn_d_bits_opcode; // @[Debug.scala:790:9]
wire [1:0] dmiNodeIn_d_bits_d_size; // @[Edges.scala:792:17]
assign auto_dmi_in_d_bits_size_0 = dmiNodeIn_d_bits_size; // @[Debug.scala:790:9]
wire dmiNodeIn_d_bits_d_source; // @[Edges.scala:792:17]
assign auto_dmi_in_d_bits_source_0 = dmiNodeIn_d_bits_source; // @[Debug.scala:790:9]
wire [31:0] out_bits_data; // @[RegisterRouter.scala:87:24]
assign auto_dmi_in_d_bits_data_0 = dmiNodeIn_d_bits_data; // @[Debug.scala:790:9]
wire in_1_ready; // @[RegisterRouter.scala:73:18]
assign auto_tl_in_a_ready_0 = tlNodeIn_a_ready; // @[Debug.scala:790:9]
wire in_1_valid = tlNodeIn_a_valid; // @[RegisterRouter.scala:73:18]
wire [1:0] in_1_bits_extra_tlrr_extra_size = tlNodeIn_a_bits_size; // @[RegisterRouter.scala:73:18]
wire [10:0] in_1_bits_extra_tlrr_extra_source = tlNodeIn_a_bits_source; // @[RegisterRouter.scala:73:18]
wire [7:0] in_1_bits_mask = tlNodeIn_a_bits_mask; // @[RegisterRouter.scala:73:18]
wire [63:0] in_1_bits_data = tlNodeIn_a_bits_data; // @[RegisterRouter.scala:73:18]
wire out_1_ready = tlNodeIn_d_ready; // @[RegisterRouter.scala:87:24]
wire out_1_valid; // @[RegisterRouter.scala:87:24]
assign auto_tl_in_d_valid_0 = tlNodeIn_d_valid; // @[Debug.scala:790:9]
assign auto_tl_in_d_bits_opcode_0 = tlNodeIn_d_bits_opcode; // @[Debug.scala:790:9]
wire [1:0] tlNodeIn_d_bits_d_size; // @[Edges.scala:792:17]
assign auto_tl_in_d_bits_size_0 = tlNodeIn_d_bits_size; // @[Debug.scala:790:9]
wire [10:0] tlNodeIn_d_bits_d_source; // @[Edges.scala:792:17]
assign auto_tl_in_d_bits_source_0 = tlNodeIn_d_bits_source; // @[Debug.scala:790:9]
wire [63:0] out_1_bits_data; // @[RegisterRouter.scala:87:24]
assign auto_tl_in_d_bits_data_0 = tlNodeIn_d_bits_data; // @[Debug.scala:790:9]
reg haltedBitRegs; // @[Debug.scala:861:31]
wire _DMSTATUSRdData_anyhalted_T_1 = haltedBitRegs; // @[Debug.scala:861:31, :995:77]
wire _DMSTATUSRdData_anyrunning_T_1 = haltedBitRegs; // @[Debug.scala:861:31, :996:77]
wire _DMSTATUSRdData_allhalted_T_1 = haltedBitRegs; // @[Debug.scala:861:31, :1001:79]
wire _DMSTATUSRdData_allrunning_T_1 = haltedBitRegs; // @[Debug.scala:861:31, :1002:79]
wire _haltedStatus_0_T = haltedBitRegs; // @[Debug.scala:861:31, :1163:43]
wire _hartHalted_T = haltedBitRegs; // @[Debug.scala:861:31, :1734:37]
reg resumeReqRegs; // @[Debug.scala:863:31]
wire _flags_resume_T = resumeReqRegs; // @[Debug.scala:863:31, :1524:80]
reg haveResetBitRegs; // @[Debug.scala:865:31]
wire _DMSTATUSRdData_anyhavereset_T = haveResetBitRegs; // @[Debug.scala:865:31, :997:58]
wire _DMSTATUSRdData_allhavereset_T = haveResetBitRegs; // @[Debug.scala:865:31, :1003:60]
wire resumeAcks; // @[Debug.scala:869:32]
wire _DMSTATUSRdData_anyresumeack_T = resumeAcks; // @[Debug.scala:869:32, :998:52]
wire _DMSTATUSRdData_allresumeack_T = resumeAcks; // @[Debug.scala:869:32, :1004:54]
wire out_f_woready_681; // @[RegisterRouter.scala:87:24]
wire hartHaltedWrEn; // @[Debug.scala:875:36]
wire [9:0] _out_T_6805; // @[RegisterRouter.scala:87:24]
wire [9:0] hartHaltedId; // @[Debug.scala:876:36]
wire out_f_woready_682; // @[RegisterRouter.scala:87:24]
wire hartGoingWrEn; // @[Debug.scala:877:36]
wire [9:0] _out_T_6814; // @[RegisterRouter.scala:87:24]
wire [9:0] hartGoingId; // @[Debug.scala:878:36]
wire out_f_woready_498; // @[RegisterRouter.scala:87:24]
wire hartResumingWrEn; // @[Debug.scala:879:36]
wire [9:0] _out_T_5126; // @[RegisterRouter.scala:87:24]
wire [9:0] hartResumingId; // @[Debug.scala:880:36]
wire out_f_woready_499; // @[RegisterRouter.scala:87:24]
wire hartExceptionWrEn; // @[Debug.scala:881:36]
wire [9:0] _out_T_5135; // @[RegisterRouter.scala:87:24]
wire [9:0] hartExceptionId; // @[Debug.scala:882:36]
wire out_f_roready_101; // @[RegisterRouter.scala:87:24]
wire out_f_roready_102; // @[RegisterRouter.scala:87:24]
wire out_f_roready_103; // @[RegisterRouter.scala:87:24]
wire out_f_roready_104; // @[RegisterRouter.scala:87:24]
wire out_f_roready_73; // @[RegisterRouter.scala:87:24]
wire out_f_roready_74; // @[RegisterRouter.scala:87:24]
wire out_f_roready_75; // @[RegisterRouter.scala:87:24]
wire out_f_roready_76; // @[RegisterRouter.scala:87:24]
wire out_f_roready_105; // @[RegisterRouter.scala:87:24]
wire out_f_roready_106; // @[RegisterRouter.scala:87:24]
wire out_f_roready_107; // @[RegisterRouter.scala:87:24]
wire out_f_roready_108; // @[RegisterRouter.scala:87:24]
wire out_f_roready_13; // @[RegisterRouter.scala:87:24]
wire out_f_roready_14; // @[RegisterRouter.scala:87:24]
wire out_f_roready_15; // @[RegisterRouter.scala:87:24]
wire out_f_roready_16; // @[RegisterRouter.scala:87:24]
wire out_f_roready_141; // @[RegisterRouter.scala:87:24]
wire out_f_roready_142; // @[RegisterRouter.scala:87:24]
wire out_f_roready_143; // @[RegisterRouter.scala:87:24]
wire out_f_roready_144; // @[RegisterRouter.scala:87:24]
wire out_f_roready_55; // @[RegisterRouter.scala:87:24]
wire out_f_roready_56; // @[RegisterRouter.scala:87:24]
wire out_f_roready_57; // @[RegisterRouter.scala:87:24]
wire out_f_roready_58; // @[RegisterRouter.scala:87:24]
wire out_f_roready_69; // @[RegisterRouter.scala:87:24]
wire out_f_roready_70; // @[RegisterRouter.scala:87:24]
wire out_f_roready_71; // @[RegisterRouter.scala:87:24]
wire out_f_roready_72; // @[RegisterRouter.scala:87:24]
wire out_f_roready_124; // @[RegisterRouter.scala:87:24]
wire out_f_roready_125; // @[RegisterRouter.scala:87:24]
wire out_f_roready_126; // @[RegisterRouter.scala:87:24]
wire out_f_roready_127; // @[RegisterRouter.scala:87:24]
wire out_f_roready_136; // @[RegisterRouter.scala:87:24]
wire out_f_roready_137; // @[RegisterRouter.scala:87:24]
wire out_f_roready_138; // @[RegisterRouter.scala:87:24]
wire out_f_roready_139; // @[RegisterRouter.scala:87:24]
wire out_f_roready_9; // @[RegisterRouter.scala:87:24]
wire out_f_roready_10; // @[RegisterRouter.scala:87:24]
wire out_f_roready_11; // @[RegisterRouter.scala:87:24]
wire out_f_roready_12; // @[RegisterRouter.scala:87:24]
wire out_f_roready_48; // @[RegisterRouter.scala:87:24]
wire out_f_roready_49; // @[RegisterRouter.scala:87:24]
wire out_f_roready_50; // @[RegisterRouter.scala:87:24]
wire out_f_roready_51; // @[RegisterRouter.scala:87:24]
wire out_f_roready_132; // @[RegisterRouter.scala:87:24]
wire out_f_roready_133; // @[RegisterRouter.scala:87:24]
wire out_f_roready_134; // @[RegisterRouter.scala:87:24]
wire out_f_roready_135; // @[RegisterRouter.scala:87:24]
wire out_f_roready_116; // @[RegisterRouter.scala:87:24]
wire out_f_roready_117; // @[RegisterRouter.scala:87:24]
wire out_f_roready_118; // @[RegisterRouter.scala:87:24]
wire out_f_roready_119; // @[RegisterRouter.scala:87:24]
wire out_f_roready_77; // @[RegisterRouter.scala:87:24]
wire out_f_roready_78; // @[RegisterRouter.scala:87:24]
wire out_f_roready_79; // @[RegisterRouter.scala:87:24]
wire out_f_roready_80; // @[RegisterRouter.scala:87:24]
wire out_f_roready_59; // @[RegisterRouter.scala:87:24]
wire out_f_roready_60; // @[RegisterRouter.scala:87:24]
wire out_f_roready_61; // @[RegisterRouter.scala:87:24]
wire out_f_roready_62; // @[RegisterRouter.scala:87:24]
wire out_f_roready_25; // @[RegisterRouter.scala:87:24]
wire out_f_roready_26; // @[RegisterRouter.scala:87:24]
wire out_f_roready_27; // @[RegisterRouter.scala:87:24]
wire out_f_roready_28; // @[RegisterRouter.scala:87:24]
wire dmiProgramBufferRdEn_0; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_1; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_2; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_3; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_4; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_5; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_6; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_7; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_8; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_9; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_10; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_11; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_12; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_13; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_14; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_15; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_16; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_17; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_18; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_19; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_20; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_21; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_22; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_23; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_24; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_25; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_26; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_27; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_28; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_29; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_30; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_31; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_32; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_33; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_34; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_35; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_36; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_37; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_38; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_39; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_40; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_41; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_42; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_43; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_44; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_45; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_46; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_47; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_48; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_49; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_50; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_51; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_52; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_53; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_54; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_55; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_56; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_57; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_58; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_59; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_60; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_61; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_62; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_63; // @[Debug.scala:887:40]
wire _dmiProgramBufferAccessLegal_T; // @[Debug.scala:1746:50]
wire dmiProgramBufferAccessLegal; // @[Debug.scala:888:47]
wire out_f_woready_101; // @[RegisterRouter.scala:87:24]
wire out_f_woready_102; // @[RegisterRouter.scala:87:24]
wire out_f_woready_103; // @[RegisterRouter.scala:87:24]
wire out_f_woready_104; // @[RegisterRouter.scala:87:24]
wire out_f_woready_73; // @[RegisterRouter.scala:87:24]
wire out_f_woready_74; // @[RegisterRouter.scala:87:24]
wire out_f_woready_75; // @[RegisterRouter.scala:87:24]
wire out_f_woready_76; // @[RegisterRouter.scala:87:24]
wire out_f_woready_105; // @[RegisterRouter.scala:87:24]
wire out_f_woready_106; // @[RegisterRouter.scala:87:24]
wire out_f_woready_107; // @[RegisterRouter.scala:87:24]
wire out_f_woready_108; // @[RegisterRouter.scala:87:24]
wire out_f_woready_13; // @[RegisterRouter.scala:87:24]
wire out_f_woready_14; // @[RegisterRouter.scala:87:24]
wire out_f_woready_15; // @[RegisterRouter.scala:87:24]
wire out_f_woready_16; // @[RegisterRouter.scala:87:24]
wire out_f_woready_141; // @[RegisterRouter.scala:87:24]
wire out_f_woready_142; // @[RegisterRouter.scala:87:24]
wire out_f_woready_143; // @[RegisterRouter.scala:87:24]
wire out_f_woready_144; // @[RegisterRouter.scala:87:24]
wire out_f_woready_55; // @[RegisterRouter.scala:87:24]
wire out_f_woready_56; // @[RegisterRouter.scala:87:24]
wire out_f_woready_57; // @[RegisterRouter.scala:87:24]
wire out_f_woready_58; // @[RegisterRouter.scala:87:24]
wire out_f_woready_69; // @[RegisterRouter.scala:87:24]
wire out_f_woready_70; // @[RegisterRouter.scala:87:24]
wire out_f_woready_71; // @[RegisterRouter.scala:87:24]
wire out_f_woready_72; // @[RegisterRouter.scala:87:24]
wire out_f_woready_124; // @[RegisterRouter.scala:87:24]
wire out_f_woready_125; // @[RegisterRouter.scala:87:24]
wire out_f_woready_126; // @[RegisterRouter.scala:87:24]
wire out_f_woready_127; // @[RegisterRouter.scala:87:24]
wire out_f_woready_136; // @[RegisterRouter.scala:87:24]
wire out_f_woready_137; // @[RegisterRouter.scala:87:24]
wire out_f_woready_138; // @[RegisterRouter.scala:87:24]
wire out_f_woready_139; // @[RegisterRouter.scala:87:24]
wire out_f_woready_9; // @[RegisterRouter.scala:87:24]
wire out_f_woready_10; // @[RegisterRouter.scala:87:24]
wire out_f_woready_11; // @[RegisterRouter.scala:87:24]
wire out_f_woready_12; // @[RegisterRouter.scala:87:24]
wire out_f_woready_48; // @[RegisterRouter.scala:87:24]
wire out_f_woready_49; // @[RegisterRouter.scala:87:24]
wire out_f_woready_50; // @[RegisterRouter.scala:87:24]
wire out_f_woready_51; // @[RegisterRouter.scala:87:24]
wire out_f_woready_132; // @[RegisterRouter.scala:87:24]
wire out_f_woready_133; // @[RegisterRouter.scala:87:24]
wire out_f_woready_134; // @[RegisterRouter.scala:87:24]
wire out_f_woready_135; // @[RegisterRouter.scala:87:24]
wire out_f_woready_116; // @[RegisterRouter.scala:87:24]
wire out_f_woready_117; // @[RegisterRouter.scala:87:24]
wire out_f_woready_118; // @[RegisterRouter.scala:87:24]
wire out_f_woready_119; // @[RegisterRouter.scala:87:24]
wire out_f_woready_77; // @[RegisterRouter.scala:87:24]
wire out_f_woready_78; // @[RegisterRouter.scala:87:24]
wire out_f_woready_79; // @[RegisterRouter.scala:87:24]
wire out_f_woready_80; // @[RegisterRouter.scala:87:24]
wire out_f_woready_59; // @[RegisterRouter.scala:87:24]
wire out_f_woready_60; // @[RegisterRouter.scala:87:24]
wire out_f_woready_61; // @[RegisterRouter.scala:87:24]
wire out_f_woready_62; // @[RegisterRouter.scala:87:24]
wire out_f_woready_25; // @[RegisterRouter.scala:87:24]
wire out_f_woready_26; // @[RegisterRouter.scala:87:24]
wire out_f_woready_27; // @[RegisterRouter.scala:87:24]
wire out_f_woready_28; // @[RegisterRouter.scala:87:24]
wire dmiProgramBufferWrEnMaybe_0; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_1; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_2; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_3; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_4; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_5; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_6; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_7; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_8; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_9; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_10; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_11; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_12; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_13; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_14; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_15; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_16; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_17; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_18; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_19; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_20; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_21; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_22; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_23; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_24; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_25; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_26; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_27; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_28; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_29; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_30; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_31; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_32; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_33; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_34; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_35; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_36; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_37; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_38; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_39; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_40; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_41; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_42; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_43; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_44; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_45; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_46; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_47; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_48; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_49; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_50; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_51; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_52; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_53; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_54; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_55; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_56; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_57; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_58; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_59; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_60; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_61; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_62; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_63; // @[Debug.scala:889:45]
wire out_f_roready_21; // @[RegisterRouter.scala:87:24]
wire out_f_roready_22; // @[RegisterRouter.scala:87:24]
wire out_f_roready_23; // @[RegisterRouter.scala:87:24]
wire out_f_roready_24; // @[RegisterRouter.scala:87:24]
wire out_f_roready; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1; // @[RegisterRouter.scala:87:24]
wire out_f_roready_2; // @[RegisterRouter.scala:87:24]
wire out_f_roready_3; // @[RegisterRouter.scala:87:24]
wire out_f_roready_64; // @[RegisterRouter.scala:87:24]
wire out_f_roready_65; // @[RegisterRouter.scala:87:24]
wire out_f_roready_66; // @[RegisterRouter.scala:87:24]
wire out_f_roready_67; // @[RegisterRouter.scala:87:24]
wire out_f_roready_120; // @[RegisterRouter.scala:87:24]
wire out_f_roready_121; // @[RegisterRouter.scala:87:24]
wire out_f_roready_122; // @[RegisterRouter.scala:87:24]
wire out_f_roready_123; // @[RegisterRouter.scala:87:24]
wire out_f_roready_17; // @[RegisterRouter.scala:87:24]
wire out_f_roready_18; // @[RegisterRouter.scala:87:24]
wire out_f_roready_19; // @[RegisterRouter.scala:87:24]
wire out_f_roready_20; // @[RegisterRouter.scala:87:24]
wire out_f_roready_5; // @[RegisterRouter.scala:87:24]
wire out_f_roready_6; // @[RegisterRouter.scala:87:24]
wire out_f_roready_7; // @[RegisterRouter.scala:87:24]
wire out_f_roready_8; // @[RegisterRouter.scala:87:24]
wire out_f_roready_29; // @[RegisterRouter.scala:87:24]
wire out_f_roready_30; // @[RegisterRouter.scala:87:24]
wire out_f_roready_31; // @[RegisterRouter.scala:87:24]
wire out_f_roready_32; // @[RegisterRouter.scala:87:24]
wire out_f_roready_128; // @[RegisterRouter.scala:87:24]
wire out_f_roready_129; // @[RegisterRouter.scala:87:24]
wire out_f_roready_130; // @[RegisterRouter.scala:87:24]
wire out_f_roready_131; // @[RegisterRouter.scala:87:24]
wire dmiAbstractDataRdEn_0; // @[Debug.scala:891:39]
wire dmiAbstractDataRdEn_1; // @[Debug.scala:891:39]
wire dmiAbstractDataRdEn_2; // @[Debug.scala:891:39]
wire dmiAbstractDataRdEn_3; // @[Debug.scala:891:39]
wire dmiAbstractDataRdEn_4; // @[Debug.scala:891:39]
wire dmiAbstractDataRdEn_5; // @[Debug.scala:891:39]
wire dmiAbstractDataRdEn_6; // @[Debug.scala:891:39]
wire dmiAbstractDataRdEn_7; // @[Debug.scala:891:39]
wire dmiAbstractDataRdEn_8; // @[Debug.scala:891:39]
wire dmiAbstractDataRdEn_9; // @[Debug.scala:891:39]
wire dmiAbstractDataRdEn_10; // @[Debug.scala:891:39]
wire dmiAbstractDataRdEn_11; // @[Debug.scala:891:39]
wire dmiAbstractDataRdEn_12; // @[Debug.scala:891:39]
wire dmiAbstractDataRdEn_13; // @[Debug.scala:891:39]
wire dmiAbstractDataRdEn_14; // @[Debug.scala:891:39]
wire dmiAbstractDataRdEn_15; // @[Debug.scala:891:39]
wire dmiAbstractDataRdEn_16; // @[Debug.scala:891:39]
wire dmiAbstractDataRdEn_17; // @[Debug.scala:891:39]
wire dmiAbstractDataRdEn_18; // @[Debug.scala:891:39]
wire dmiAbstractDataRdEn_19; // @[Debug.scala:891:39]
wire dmiAbstractDataRdEn_20; // @[Debug.scala:891:39]
wire dmiAbstractDataRdEn_21; // @[Debug.scala:891:39]
wire dmiAbstractDataRdEn_22; // @[Debug.scala:891:39]
wire dmiAbstractDataRdEn_23; // @[Debug.scala:891:39]
wire dmiAbstractDataRdEn_24; // @[Debug.scala:891:39]
wire dmiAbstractDataRdEn_25; // @[Debug.scala:891:39]
wire dmiAbstractDataRdEn_26; // @[Debug.scala:891:39]
wire dmiAbstractDataRdEn_27; // @[Debug.scala:891:39]
wire dmiAbstractDataRdEn_28; // @[Debug.scala:891:39]
wire dmiAbstractDataRdEn_29; // @[Debug.scala:891:39]
wire dmiAbstractDataRdEn_30; // @[Debug.scala:891:39]
wire dmiAbstractDataRdEn_31; // @[Debug.scala:891:39]
wire _dmiAbstractDataAccessLegal_T; // @[Debug.scala:1745:50]
wire dmiAbstractDataAccessLegal; // @[Debug.scala:892:46]
wire out_f_woready_21; // @[RegisterRouter.scala:87:24]
wire out_f_woready_22; // @[RegisterRouter.scala:87:24]
wire out_f_woready_23; // @[RegisterRouter.scala:87:24]
wire out_f_woready_24; // @[RegisterRouter.scala:87:24]
wire out_f_woready; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1; // @[RegisterRouter.scala:87:24]
wire out_f_woready_2; // @[RegisterRouter.scala:87:24]
wire out_f_woready_3; // @[RegisterRouter.scala:87:24]
wire out_f_woready_64; // @[RegisterRouter.scala:87:24]
wire out_f_woready_65; // @[RegisterRouter.scala:87:24]
wire out_f_woready_66; // @[RegisterRouter.scala:87:24]
wire out_f_woready_67; // @[RegisterRouter.scala:87:24]
wire out_f_woready_120; // @[RegisterRouter.scala:87:24]
wire out_f_woready_121; // @[RegisterRouter.scala:87:24]
wire out_f_woready_122; // @[RegisterRouter.scala:87:24]
wire out_f_woready_123; // @[RegisterRouter.scala:87:24]
wire out_f_woready_17; // @[RegisterRouter.scala:87:24]
wire out_f_woready_18; // @[RegisterRouter.scala:87:24]
wire out_f_woready_19; // @[RegisterRouter.scala:87:24]
wire out_f_woready_20; // @[RegisterRouter.scala:87:24]
wire out_f_woready_5; // @[RegisterRouter.scala:87:24]
wire out_f_woready_6; // @[RegisterRouter.scala:87:24]
wire out_f_woready_7; // @[RegisterRouter.scala:87:24]
wire out_f_woready_8; // @[RegisterRouter.scala:87:24]
wire out_f_woready_29; // @[RegisterRouter.scala:87:24]
wire out_f_woready_30; // @[RegisterRouter.scala:87:24]
wire out_f_woready_31; // @[RegisterRouter.scala:87:24]
wire out_f_woready_32; // @[RegisterRouter.scala:87:24]
wire out_f_woready_128; // @[RegisterRouter.scala:87:24]
wire out_f_woready_129; // @[RegisterRouter.scala:87:24]
wire out_f_woready_130; // @[RegisterRouter.scala:87:24]
wire out_f_woready_131; // @[RegisterRouter.scala:87:24]
wire dmiAbstractDataWrEnMaybe_0; // @[Debug.scala:893:44]
wire dmiAbstractDataWrEnMaybe_1; // @[Debug.scala:893:44]
wire dmiAbstractDataWrEnMaybe_2; // @[Debug.scala:893:44]
wire dmiAbstractDataWrEnMaybe_3; // @[Debug.scala:893:44]
wire dmiAbstractDataWrEnMaybe_4; // @[Debug.scala:893:44]
wire dmiAbstractDataWrEnMaybe_5; // @[Debug.scala:893:44]
wire dmiAbstractDataWrEnMaybe_6; // @[Debug.scala:893:44]
wire dmiAbstractDataWrEnMaybe_7; // @[Debug.scala:893:44]
wire dmiAbstractDataWrEnMaybe_8; // @[Debug.scala:893:44]
wire dmiAbstractDataWrEnMaybe_9; // @[Debug.scala:893:44]
wire dmiAbstractDataWrEnMaybe_10; // @[Debug.scala:893:44]
wire dmiAbstractDataWrEnMaybe_11; // @[Debug.scala:893:44]
wire dmiAbstractDataWrEnMaybe_12; // @[Debug.scala:893:44]
wire dmiAbstractDataWrEnMaybe_13; // @[Debug.scala:893:44]
wire dmiAbstractDataWrEnMaybe_14; // @[Debug.scala:893:44]
wire dmiAbstractDataWrEnMaybe_15; // @[Debug.scala:893:44]
wire dmiAbstractDataWrEnMaybe_16; // @[Debug.scala:893:44]
wire dmiAbstractDataWrEnMaybe_17; // @[Debug.scala:893:44]
wire dmiAbstractDataWrEnMaybe_18; // @[Debug.scala:893:44]
wire dmiAbstractDataWrEnMaybe_19; // @[Debug.scala:893:44]
wire dmiAbstractDataWrEnMaybe_20; // @[Debug.scala:893:44]
wire dmiAbstractDataWrEnMaybe_21; // @[Debug.scala:893:44]
wire dmiAbstractDataWrEnMaybe_22; // @[Debug.scala:893:44]
wire dmiAbstractDataWrEnMaybe_23; // @[Debug.scala:893:44]
wire dmiAbstractDataWrEnMaybe_24; // @[Debug.scala:893:44]
wire dmiAbstractDataWrEnMaybe_25; // @[Debug.scala:893:44]
wire dmiAbstractDataWrEnMaybe_26; // @[Debug.scala:893:44]
wire dmiAbstractDataWrEnMaybe_27; // @[Debug.scala:893:44]
wire dmiAbstractDataWrEnMaybe_28; // @[Debug.scala:893:44]
wire dmiAbstractDataWrEnMaybe_29; // @[Debug.scala:893:44]
wire dmiAbstractDataWrEnMaybe_30; // @[Debug.scala:893:44]
wire dmiAbstractDataWrEnMaybe_31; // @[Debug.scala:893:44]
wire _hamaskWrSel_0_T_1; // @[Debug.scala:935:78]
wire hamaskWrSel_0; // @[Debug.scala:933:31]
wire _hamaskWrSel_0_T = io_innerCtrl_bits_hartsel_0 == 10'h0; // @[Debug.scala:790:9, :935:61]
assign _hamaskWrSel_0_T_1 = _hamaskWrSel_0_T; // @[Debug.scala:935:{61,78}]
assign hamaskWrSel_0 = _hamaskWrSel_0_T_1; // @[Debug.scala:933:31, :935:78]
assign io_hgDebugInt_0_0 = hrDebugInt_0; // @[Debug.scala:790:9, :946:26]
reg hrmaskReg_0; // @[Debug.scala:947:29]
wire _hartIsInResetSync_0_WIRE; // @[ShiftReg.scala:48:24]
wire hartIsInResetSync_0; // @[Debug.scala:948:33]
assign hartIsInResetSync_0 = _hartIsInResetSync_0_WIRE; // @[ShiftReg.scala:48:24]
reg hrDebugIntReg_0; // @[Debug.scala:961:34]
assign hrDebugInt_0 = hrDebugIntReg_0; // @[Debug.scala:946:26, :961:34]
wire _DMSTATUSRdData_allnonexistent_T_2; // @[Debug.scala:991:75]
wire DMSTATUSRdData_allhavereset; // @[Debug.scala:978:34]
wire DMSTATUSRdData_anyhavereset; // @[Debug.scala:978:34]
wire DMSTATUSRdData_allresumeack; // @[Debug.scala:978:34]
wire DMSTATUSRdData_anyresumeack; // @[Debug.scala:978:34]
wire DMSTATUSRdData_allnonexistent; // @[Debug.scala:978:34]
wire DMSTATUSRdData_anynonexistent; // @[Debug.scala:978:34]
wire DMSTATUSRdData_allunavail; // @[Debug.scala:978:34]
wire DMSTATUSRdData_allrunning; // @[Debug.scala:978:34]
wire DMSTATUSRdData_anyrunning; // @[Debug.scala:978:34]
wire DMSTATUSRdData_allhalted; // @[Debug.scala:978:34]
wire DMSTATUSRdData_anyhalted; // @[Debug.scala:978:34]
wire resumereq = _resumereq_T & io_innerCtrl_bits_resumereq_0; // @[Decoupled.scala:51:35]
assign DMSTATUSRdData_anynonexistent = _DMSTATUSRdData_anynonexistent_T; // @[Debug.scala:978:34, :988:57]
wire _DMSTATUSRdData_allnonexistent_T_1 = ~hamaskFull_0; // @[Debug.scala:903:30, :991:78]
assign _DMSTATUSRdData_allnonexistent_T_2 = _DMSTATUSRdData_allnonexistent_T & _DMSTATUSRdData_allnonexistent_T_1; // @[Debug.scala:991:{57,75,78}]
assign DMSTATUSRdData_allnonexistent = _DMSTATUSRdData_allnonexistent_T_2; // @[Debug.scala:978:34, :991:75]
wire _DMSTATUSRdData_anyhalted_T_2 = _DMSTATUSRdData_anyhalted_T_1; // @[package.scala:74:72]
wire _DMSTATUSRdData_anyhalted_T_3 = _DMSTATUSRdData_anyhalted_T_2 & hamaskFull_0; // @[package.scala:74:72]
assign DMSTATUSRdData_anyhalted = ~DMSTATUSRdData_allnonexistent & _DMSTATUSRdData_anyhalted_T_3; // @[package.scala:74:72]
wire _DMSTATUSRdData_anyrunning_T_2 = ~_DMSTATUSRdData_anyrunning_T_1; // @[package.scala:79:37]
wire _DMSTATUSRdData_anyrunning_T_3 = _DMSTATUSRdData_anyrunning_T_2; // @[package.scala:74:72, :79:37]
wire _DMSTATUSRdData_anyrunning_T_4 = _DMSTATUSRdData_anyrunning_T_3 & hamaskFull_0; // @[package.scala:74:72]
assign DMSTATUSRdData_anyrunning = ~DMSTATUSRdData_allnonexistent & _DMSTATUSRdData_anyrunning_T_4; // @[package.scala:74:72]
wire _DMSTATUSRdData_anyhavereset_T_1 = _DMSTATUSRdData_anyhavereset_T & hamaskFull_0; // @[package.scala:74:72]
assign DMSTATUSRdData_anyhavereset = ~DMSTATUSRdData_allnonexistent & _DMSTATUSRdData_anyhavereset_T_1; // @[package.scala:74:72]
wire _DMSTATUSRdData_anyresumeack_T_1 = _DMSTATUSRdData_anyresumeack_T & hamaskFull_0; // @[package.scala:74:72]
assign DMSTATUSRdData_anyresumeack = ~DMSTATUSRdData_allnonexistent & _DMSTATUSRdData_anyresumeack_T_1; // @[package.scala:74:72]
wire _DMSTATUSRdData_allunavail_T = ~hamaskFull_0; // @[package.scala:79:37]
wire _DMSTATUSRdData_allunavail_T_1 = _DMSTATUSRdData_allunavail_T; // @[package.scala:75:75, :79:37]
wire _GEN = ~DMSTATUSRdData_allnonexistent & ~DMSTATUSRdData_anynonexistent; // @[Debug.scala:978:34, :993:{13,45}, :999:{15,47}, :1000:39]
assign DMSTATUSRdData_allunavail = _GEN & _DMSTATUSRdData_allunavail_T_1; // @[package.scala:75:75]
wire _DMSTATUSRdData_allhalted_T_2 = _DMSTATUSRdData_allhalted_T_1; // @[package.scala:74:72]
wire _DMSTATUSRdData_allhalted_T_3 = ~hamaskFull_0; // @[package.scala:79:37]
wire _DMSTATUSRdData_allhalted_T_4 = _DMSTATUSRdData_allhalted_T_2 | _DMSTATUSRdData_allhalted_T_3; // @[package.scala:74:72, :75:75, :79:37]
assign DMSTATUSRdData_allhalted = _GEN & _DMSTATUSRdData_allhalted_T_4; // @[package.scala:75:75]
wire _DMSTATUSRdData_allrunning_T_2 = ~_DMSTATUSRdData_allrunning_T_1; // @[package.scala:79:37]
wire _DMSTATUSRdData_allrunning_T_3 = _DMSTATUSRdData_allrunning_T_2; // @[package.scala:74:72, :79:37]
wire _DMSTATUSRdData_allrunning_T_4 = ~hamaskFull_0; // @[package.scala:79:37]
wire _DMSTATUSRdData_allrunning_T_5 = _DMSTATUSRdData_allrunning_T_3 | _DMSTATUSRdData_allrunning_T_4; // @[package.scala:74:72, :75:75, :79:37]
assign DMSTATUSRdData_allrunning = _GEN & _DMSTATUSRdData_allrunning_T_5; // @[package.scala:75:75]
wire _DMSTATUSRdData_allhavereset_T_1 = ~hamaskFull_0; // @[package.scala:79:37]
wire _DMSTATUSRdData_allhavereset_T_2 = _DMSTATUSRdData_allhavereset_T | _DMSTATUSRdData_allhavereset_T_1; // @[package.scala:75:75, :79:37]
assign DMSTATUSRdData_allhavereset = _GEN & _DMSTATUSRdData_allhavereset_T_2; // @[package.scala:75:75]
wire _DMSTATUSRdData_allresumeack_T_1 = ~hamaskFull_0; // @[package.scala:79:37]
wire _DMSTATUSRdData_allresumeack_T_2 = _DMSTATUSRdData_allresumeack_T | _DMSTATUSRdData_allresumeack_T_1; // @[package.scala:75:75, :79:37]
assign DMSTATUSRdData_allresumeack = _GEN & _DMSTATUSRdData_allresumeack_T_2; // @[package.scala:75:75]
wire _haveResetBitRegs_T = ~hamaskWrSel_0; // @[Debug.scala:933:31, :1017:50]
wire _haveResetBitRegs_T_1 = haveResetBitRegs & _haveResetBitRegs_T; // @[Debug.scala:865:31, :1017:{47,50}]
wire _haveResetBitRegs_T_2 = _haveResetBitRegs_T_1 | hartIsInResetSync_0; // @[Debug.scala:948:33, :1017:{47,74}]
wire _haveResetBitRegs_T_3 = haveResetBitRegs | hartIsInResetSync_0; // @[Debug.scala:865:31, :948:33, :1019:46]
wire [31:0] haltedStatus_0; // @[Debug.scala:1159:30]
wire [31:0] selectedHaltedStatus = haltedStatus_0; // @[Debug.scala:1159:30, :1172:35]
assign haltedStatus_0 = {31'h0, _haltedStatus_0_T}; // @[Debug.scala:1159:30, :1163:{26,43}]
wire haltedSummary = |haltedStatus_0; // @[Debug.scala:1159:30, :1169:48]
wire [31:0] _HALTSUM1RdData_T; // @[Debug.scala:1170:48]
wire [31:0] HALTSUM1RdData_haltsum1; // @[Debug.scala:1170:48]
wire [31:0] _out_T_1598 = HALTSUM1RdData_haltsum1; // @[RegisterRouter.scala:87:24]
assign _HALTSUM1RdData_T = _HALTSUM1RdData_WIRE; // @[Debug.scala:1170:48]
assign _HALTSUM1RdData_WIRE = {31'h0, haltedSummary}; // @[Debug.scala:1169:48, :1170:48]
assign HALTSUM1RdData_haltsum1 = _HALTSUM1RdData_T; // @[Debug.scala:1170:48]
wire [31:0] _HALTSUM0RdData_WIRE = selectedHaltedStatus; // @[Debug.scala:1172:35, :1173:55]
wire [31:0] _HALTSUM0RdData_T; // @[Debug.scala:1173:55]
wire [31:0] HALTSUM0RdData_haltsum0; // @[Debug.scala:1173:55]
wire [31:0] _out_T_946 = HALTSUM0RdData_haltsum0; // @[RegisterRouter.scala:87:24]
assign _HALTSUM0RdData_T = _HALTSUM0RdData_WIRE; // @[Debug.scala:1173:55]
assign HALTSUM0RdData_haltsum0 = _HALTSUM0RdData_T; // @[Debug.scala:1173:55]
reg [2:0] ABSTRACTCSReg_cmderr; // @[Debug.scala:1183:34]
wire [2:0] ABSTRACTCSRdData_cmderr = ABSTRACTCSReg_cmderr; // @[Debug.scala:1183:34, :1185:39]
wire [2:0] _out_T_1225; // @[RegisterRouter.scala:87:24]
wire [2:0] ABSTRACTCSWrData_cmderr; // @[Debug.scala:1184:39]
wire abstractCommandBusy; // @[Debug.scala:1220:39]
wire ABSTRACTCSRdData_busy; // @[Debug.scala:1185:39]
wire out_f_woready_111; // @[RegisterRouter.scala:87:24]
wire ABSTRACTCSWrEnMaybe; // @[Debug.scala:1188:39]
wire _ABSTRACTCSWrEnLegal_T; // @[Debug.scala:1742:44]
wire ABSTRACTCSWrEnLegal; // @[Debug.scala:1190:39]
wire ABSTRACTCSWrEn = ABSTRACTCSWrEnMaybe & ABSTRACTCSWrEnLegal; // @[Debug.scala:1188:39, :1190:39, :1191:51]
wire _errorBusy_T_16; // @[Debug.scala:1752:74]
wire errorBusy; // @[Debug.scala:1195:36]
wire errorException; // @[Debug.scala:1196:36]
wire errorUnsupported; // @[Debug.scala:1197:36]
wire errorHaltResume; // @[Debug.scala:1198:36]
wire [2:0] _ABSTRACTCSReg_cmderr_T = ~ABSTRACTCSWrData_cmderr; // @[Debug.scala:1184:39, :1214:58]
wire [2:0] _ABSTRACTCSReg_cmderr_T_1 = ABSTRACTCSReg_cmderr & _ABSTRACTCSReg_cmderr_T; // @[Debug.scala:1183:34, :1214:{56,58}]
wire _abstractCommandBusy_T; // @[Debug.scala:1740:42]
assign ABSTRACTCSRdData_busy = abstractCommandBusy; // @[Debug.scala:1185:39, :1220:39]
reg [15:0] ABSTRACTAUTOReg_autoexecprogbuf; // @[Debug.scala:1235:36]
wire [15:0] ABSTRACTAUTORdData_autoexecprogbuf = ABSTRACTAUTOReg_autoexecprogbuf; // @[Debug.scala:1235:36, :1237:41]
reg [11:0] ABSTRACTAUTOReg_autoexecdata; // @[Debug.scala:1235:36]
wire [11:0] ABSTRACTAUTORdData_autoexecdata = ABSTRACTAUTOReg_autoexecdata; // @[Debug.scala:1235:36, :1237:41]
wire [15:0] _out_T_642; // @[RegisterRouter.scala:87:24]
wire [15:0] _ABSTRACTAUTOReg_autoexecprogbuf_T = ABSTRACTAUTOWrData_autoexecprogbuf; // @[Debug.scala:1236:41, :1249:79]
wire [11:0] ABSTRACTAUTOWrData_autoexecdata; // @[Debug.scala:1236:41]
wire [11:0] _out_T_631 = ABSTRACTAUTORdData_autoexecdata; // @[RegisterRouter.scala:87:24]
wire out_f_woready_52; // @[RegisterRouter.scala:87:24]
wire autoexecdataWrEnMaybe; // @[Debug.scala:1240:41]
wire out_f_woready_54; // @[RegisterRouter.scala:87:24]
wire autoexecprogbufWrEnMaybe; // @[Debug.scala:1241:44]
wire _ABSTRACTAUTOWrEnLegal_T; // @[Debug.scala:1744:44]
wire ABSTRACTAUTOWrEnLegal; // @[Debug.scala:1243:41]
wire [11:0] _ABSTRACTAUTOReg_autoexecdata_T = {4'h0, ABSTRACTAUTOWrData_autoexecdata[7:0]}; // @[Debug.scala:1236:41, :1252:73]
wire dmiAbstractDataAccessVec_0; // @[Debug.scala:1257:45]
wire dmiAbstractDataAccessVec_1; // @[Debug.scala:1257:45]
wire dmiAbstractDataAccessVec_2; // @[Debug.scala:1257:45]
wire dmiAbstractDataAccessVec_3; // @[Debug.scala:1257:45]
wire dmiAbstractDataAccessVec_4; // @[Debug.scala:1257:45]
wire dmiAbstractDataAccessVec_5; // @[Debug.scala:1257:45]
wire dmiAbstractDataAccessVec_6; // @[Debug.scala:1257:45]
wire dmiAbstractDataAccessVec_7; // @[Debug.scala:1257:45]
wire dmiAbstractDataAccessVec_8; // @[Debug.scala:1257:45]
wire dmiAbstractDataAccessVec_9; // @[Debug.scala:1257:45]
wire dmiAbstractDataAccessVec_10; // @[Debug.scala:1257:45]
wire dmiAbstractDataAccessVec_11; // @[Debug.scala:1257:45]
wire dmiAbstractDataAccessVec_12; // @[Debug.scala:1257:45]
wire dmiAbstractDataAccessVec_13; // @[Debug.scala:1257:45]
wire dmiAbstractDataAccessVec_14; // @[Debug.scala:1257:45]
wire dmiAbstractDataAccessVec_15; // @[Debug.scala:1257:45]
wire dmiAbstractDataAccessVec_16; // @[Debug.scala:1257:45]
wire dmiAbstractDataAccessVec_17; // @[Debug.scala:1257:45]
wire dmiAbstractDataAccessVec_18; // @[Debug.scala:1257:45]
wire dmiAbstractDataAccessVec_19; // @[Debug.scala:1257:45]
wire dmiAbstractDataAccessVec_20; // @[Debug.scala:1257:45]
wire dmiAbstractDataAccessVec_21; // @[Debug.scala:1257:45]
wire dmiAbstractDataAccessVec_22; // @[Debug.scala:1257:45]
wire dmiAbstractDataAccessVec_23; // @[Debug.scala:1257:45]
wire dmiAbstractDataAccessVec_24; // @[Debug.scala:1257:45]
wire dmiAbstractDataAccessVec_25; // @[Debug.scala:1257:45]
wire dmiAbstractDataAccessVec_26; // @[Debug.scala:1257:45]
wire dmiAbstractDataAccessVec_27; // @[Debug.scala:1257:45]
wire dmiAbstractDataAccessVec_28; // @[Debug.scala:1257:45]
wire dmiAbstractDataAccessVec_29; // @[Debug.scala:1257:45]
wire dmiAbstractDataAccessVec_30; // @[Debug.scala:1257:45]
wire dmiAbstractDataAccessVec_31; // @[Debug.scala:1257:45]
assign dmiAbstractDataAccessVec_0 = dmiAbstractDataWrEnMaybe_0 | dmiAbstractDataRdEn_0; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105]
assign dmiAbstractDataAccessVec_1 = dmiAbstractDataWrEnMaybe_1 | dmiAbstractDataRdEn_1; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105]
assign dmiAbstractDataAccessVec_2 = dmiAbstractDataWrEnMaybe_2 | dmiAbstractDataRdEn_2; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105]
assign dmiAbstractDataAccessVec_3 = dmiAbstractDataWrEnMaybe_3 | dmiAbstractDataRdEn_3; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105]
assign dmiAbstractDataAccessVec_4 = dmiAbstractDataWrEnMaybe_4 | dmiAbstractDataRdEn_4; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105]
assign dmiAbstractDataAccessVec_5 = dmiAbstractDataWrEnMaybe_5 | dmiAbstractDataRdEn_5; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105]
assign dmiAbstractDataAccessVec_6 = dmiAbstractDataWrEnMaybe_6 | dmiAbstractDataRdEn_6; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105]
assign dmiAbstractDataAccessVec_7 = dmiAbstractDataWrEnMaybe_7 | dmiAbstractDataRdEn_7; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105]
assign dmiAbstractDataAccessVec_8 = dmiAbstractDataWrEnMaybe_8 | dmiAbstractDataRdEn_8; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105]
assign dmiAbstractDataAccessVec_9 = dmiAbstractDataWrEnMaybe_9 | dmiAbstractDataRdEn_9; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105]
assign dmiAbstractDataAccessVec_10 = dmiAbstractDataWrEnMaybe_10 | dmiAbstractDataRdEn_10; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105]
assign dmiAbstractDataAccessVec_11 = dmiAbstractDataWrEnMaybe_11 | dmiAbstractDataRdEn_11; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105]
assign dmiAbstractDataAccessVec_12 = dmiAbstractDataWrEnMaybe_12 | dmiAbstractDataRdEn_12; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105]
assign dmiAbstractDataAccessVec_13 = dmiAbstractDataWrEnMaybe_13 | dmiAbstractDataRdEn_13; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105]
assign dmiAbstractDataAccessVec_14 = dmiAbstractDataWrEnMaybe_14 | dmiAbstractDataRdEn_14; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105]
assign dmiAbstractDataAccessVec_15 = dmiAbstractDataWrEnMaybe_15 | dmiAbstractDataRdEn_15; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105]
assign dmiAbstractDataAccessVec_16 = dmiAbstractDataWrEnMaybe_16 | dmiAbstractDataRdEn_16; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105]
assign dmiAbstractDataAccessVec_17 = dmiAbstractDataWrEnMaybe_17 | dmiAbstractDataRdEn_17; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105]
assign dmiAbstractDataAccessVec_18 = dmiAbstractDataWrEnMaybe_18 | dmiAbstractDataRdEn_18; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105]
assign dmiAbstractDataAccessVec_19 = dmiAbstractDataWrEnMaybe_19 | dmiAbstractDataRdEn_19; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105]
assign dmiAbstractDataAccessVec_20 = dmiAbstractDataWrEnMaybe_20 | dmiAbstractDataRdEn_20; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105]
assign dmiAbstractDataAccessVec_21 = dmiAbstractDataWrEnMaybe_21 | dmiAbstractDataRdEn_21; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105]
assign dmiAbstractDataAccessVec_22 = dmiAbstractDataWrEnMaybe_22 | dmiAbstractDataRdEn_22; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105]
assign dmiAbstractDataAccessVec_23 = dmiAbstractDataWrEnMaybe_23 | dmiAbstractDataRdEn_23; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105]
assign dmiAbstractDataAccessVec_24 = dmiAbstractDataWrEnMaybe_24 | dmiAbstractDataRdEn_24; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105]
assign dmiAbstractDataAccessVec_25 = dmiAbstractDataWrEnMaybe_25 | dmiAbstractDataRdEn_25; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105]
assign dmiAbstractDataAccessVec_26 = dmiAbstractDataWrEnMaybe_26 | dmiAbstractDataRdEn_26; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105]
assign dmiAbstractDataAccessVec_27 = dmiAbstractDataWrEnMaybe_27 | dmiAbstractDataRdEn_27; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105]
assign dmiAbstractDataAccessVec_28 = dmiAbstractDataWrEnMaybe_28 | dmiAbstractDataRdEn_28; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105]
assign dmiAbstractDataAccessVec_29 = dmiAbstractDataWrEnMaybe_29 | dmiAbstractDataRdEn_29; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105]
assign dmiAbstractDataAccessVec_30 = dmiAbstractDataWrEnMaybe_30 | dmiAbstractDataRdEn_30; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105]
assign dmiAbstractDataAccessVec_31 = dmiAbstractDataWrEnMaybe_31 | dmiAbstractDataRdEn_31; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105]
wire dmiProgramBufferAccessVec_0; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_1; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_2; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_3; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_4; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_5; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_6; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_7; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_8; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_9; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_10; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_11; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_12; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_13; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_14; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_15; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_16; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_17; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_18; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_19; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_20; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_21; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_22; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_23; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_24; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_25; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_26; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_27; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_28; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_29; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_30; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_31; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_32; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_33; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_34; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_35; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_36; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_37; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_38; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_39; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_40; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_41; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_42; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_43; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_44; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_45; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_46; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_47; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_48; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_49; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_50; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_51; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_52; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_53; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_54; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_55; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_56; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_57; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_58; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_59; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_60; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_61; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_62; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_63; // @[Debug.scala:1260:46]
assign dmiProgramBufferAccessVec_0 = dmiProgramBufferWrEnMaybe_0 | dmiProgramBufferRdEn_0; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_1 = dmiProgramBufferWrEnMaybe_1 | dmiProgramBufferRdEn_1; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_2 = dmiProgramBufferWrEnMaybe_2 | dmiProgramBufferRdEn_2; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_3 = dmiProgramBufferWrEnMaybe_3 | dmiProgramBufferRdEn_3; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_4 = dmiProgramBufferWrEnMaybe_4 | dmiProgramBufferRdEn_4; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_5 = dmiProgramBufferWrEnMaybe_5 | dmiProgramBufferRdEn_5; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_6 = dmiProgramBufferWrEnMaybe_6 | dmiProgramBufferRdEn_6; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_7 = dmiProgramBufferWrEnMaybe_7 | dmiProgramBufferRdEn_7; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_8 = dmiProgramBufferWrEnMaybe_8 | dmiProgramBufferRdEn_8; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_9 = dmiProgramBufferWrEnMaybe_9 | dmiProgramBufferRdEn_9; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_10 = dmiProgramBufferWrEnMaybe_10 | dmiProgramBufferRdEn_10; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_11 = dmiProgramBufferWrEnMaybe_11 | dmiProgramBufferRdEn_11; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_12 = dmiProgramBufferWrEnMaybe_12 | dmiProgramBufferRdEn_12; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_13 = dmiProgramBufferWrEnMaybe_13 | dmiProgramBufferRdEn_13; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_14 = dmiProgramBufferWrEnMaybe_14 | dmiProgramBufferRdEn_14; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_15 = dmiProgramBufferWrEnMaybe_15 | dmiProgramBufferRdEn_15; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_16 = dmiProgramBufferWrEnMaybe_16 | dmiProgramBufferRdEn_16; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_17 = dmiProgramBufferWrEnMaybe_17 | dmiProgramBufferRdEn_17; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_18 = dmiProgramBufferWrEnMaybe_18 | dmiProgramBufferRdEn_18; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_19 = dmiProgramBufferWrEnMaybe_19 | dmiProgramBufferRdEn_19; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_20 = dmiProgramBufferWrEnMaybe_20 | dmiProgramBufferRdEn_20; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_21 = dmiProgramBufferWrEnMaybe_21 | dmiProgramBufferRdEn_21; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_22 = dmiProgramBufferWrEnMaybe_22 | dmiProgramBufferRdEn_22; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_23 = dmiProgramBufferWrEnMaybe_23 | dmiProgramBufferRdEn_23; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_24 = dmiProgramBufferWrEnMaybe_24 | dmiProgramBufferRdEn_24; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_25 = dmiProgramBufferWrEnMaybe_25 | dmiProgramBufferRdEn_25; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_26 = dmiProgramBufferWrEnMaybe_26 | dmiProgramBufferRdEn_26; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_27 = dmiProgramBufferWrEnMaybe_27 | dmiProgramBufferRdEn_27; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_28 = dmiProgramBufferWrEnMaybe_28 | dmiProgramBufferRdEn_28; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_29 = dmiProgramBufferWrEnMaybe_29 | dmiProgramBufferRdEn_29; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_30 = dmiProgramBufferWrEnMaybe_30 | dmiProgramBufferRdEn_30; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_31 = dmiProgramBufferWrEnMaybe_31 | dmiProgramBufferRdEn_31; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_32 = dmiProgramBufferWrEnMaybe_32 | dmiProgramBufferRdEn_32; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_33 = dmiProgramBufferWrEnMaybe_33 | dmiProgramBufferRdEn_33; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_34 = dmiProgramBufferWrEnMaybe_34 | dmiProgramBufferRdEn_34; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_35 = dmiProgramBufferWrEnMaybe_35 | dmiProgramBufferRdEn_35; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_36 = dmiProgramBufferWrEnMaybe_36 | dmiProgramBufferRdEn_36; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_37 = dmiProgramBufferWrEnMaybe_37 | dmiProgramBufferRdEn_37; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_38 = dmiProgramBufferWrEnMaybe_38 | dmiProgramBufferRdEn_38; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_39 = dmiProgramBufferWrEnMaybe_39 | dmiProgramBufferRdEn_39; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_40 = dmiProgramBufferWrEnMaybe_40 | dmiProgramBufferRdEn_40; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_41 = dmiProgramBufferWrEnMaybe_41 | dmiProgramBufferRdEn_41; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_42 = dmiProgramBufferWrEnMaybe_42 | dmiProgramBufferRdEn_42; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_43 = dmiProgramBufferWrEnMaybe_43 | dmiProgramBufferRdEn_43; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_44 = dmiProgramBufferWrEnMaybe_44 | dmiProgramBufferRdEn_44; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_45 = dmiProgramBufferWrEnMaybe_45 | dmiProgramBufferRdEn_45; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_46 = dmiProgramBufferWrEnMaybe_46 | dmiProgramBufferRdEn_46; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_47 = dmiProgramBufferWrEnMaybe_47 | dmiProgramBufferRdEn_47; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_48 = dmiProgramBufferWrEnMaybe_48 | dmiProgramBufferRdEn_48; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_49 = dmiProgramBufferWrEnMaybe_49 | dmiProgramBufferRdEn_49; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_50 = dmiProgramBufferWrEnMaybe_50 | dmiProgramBufferRdEn_50; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_51 = dmiProgramBufferWrEnMaybe_51 | dmiProgramBufferRdEn_51; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_52 = dmiProgramBufferWrEnMaybe_52 | dmiProgramBufferRdEn_52; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_53 = dmiProgramBufferWrEnMaybe_53 | dmiProgramBufferRdEn_53; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_54 = dmiProgramBufferWrEnMaybe_54 | dmiProgramBufferRdEn_54; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_55 = dmiProgramBufferWrEnMaybe_55 | dmiProgramBufferRdEn_55; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_56 = dmiProgramBufferWrEnMaybe_56 | dmiProgramBufferRdEn_56; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_57 = dmiProgramBufferWrEnMaybe_57 | dmiProgramBufferRdEn_57; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_58 = dmiProgramBufferWrEnMaybe_58 | dmiProgramBufferRdEn_58; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_59 = dmiProgramBufferWrEnMaybe_59 | dmiProgramBufferRdEn_59; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_60 = dmiProgramBufferWrEnMaybe_60 | dmiProgramBufferRdEn_60; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_61 = dmiProgramBufferWrEnMaybe_61 | dmiProgramBufferRdEn_61; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_62 = dmiProgramBufferWrEnMaybe_62 | dmiProgramBufferRdEn_62; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_63 = dmiProgramBufferWrEnMaybe_63 | dmiProgramBufferRdEn_63; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
wire _dmiAbstractDataAccess_T = dmiAbstractDataAccessVec_0 | dmiAbstractDataAccessVec_1; // @[Debug.scala:1257:45, :1263:68]
wire _dmiAbstractDataAccess_T_1 = _dmiAbstractDataAccess_T | dmiAbstractDataAccessVec_2; // @[Debug.scala:1257:45, :1263:68]
wire _dmiAbstractDataAccess_T_2 = _dmiAbstractDataAccess_T_1 | dmiAbstractDataAccessVec_3; // @[Debug.scala:1257:45, :1263:68]
wire _dmiAbstractDataAccess_T_3 = _dmiAbstractDataAccess_T_2 | dmiAbstractDataAccessVec_4; // @[Debug.scala:1257:45, :1263:68]
wire _dmiAbstractDataAccess_T_4 = _dmiAbstractDataAccess_T_3 | dmiAbstractDataAccessVec_5; // @[Debug.scala:1257:45, :1263:68]
wire _dmiAbstractDataAccess_T_5 = _dmiAbstractDataAccess_T_4 | dmiAbstractDataAccessVec_6; // @[Debug.scala:1257:45, :1263:68]
wire _dmiAbstractDataAccess_T_6 = _dmiAbstractDataAccess_T_5 | dmiAbstractDataAccessVec_7; // @[Debug.scala:1257:45, :1263:68]
wire _dmiAbstractDataAccess_T_7 = _dmiAbstractDataAccess_T_6 | dmiAbstractDataAccessVec_8; // @[Debug.scala:1257:45, :1263:68]
wire _dmiAbstractDataAccess_T_8 = _dmiAbstractDataAccess_T_7 | dmiAbstractDataAccessVec_9; // @[Debug.scala:1257:45, :1263:68]
wire _dmiAbstractDataAccess_T_9 = _dmiAbstractDataAccess_T_8 | dmiAbstractDataAccessVec_10; // @[Debug.scala:1257:45, :1263:68]
wire _dmiAbstractDataAccess_T_10 = _dmiAbstractDataAccess_T_9 | dmiAbstractDataAccessVec_11; // @[Debug.scala:1257:45, :1263:68]
wire _dmiAbstractDataAccess_T_11 = _dmiAbstractDataAccess_T_10 | dmiAbstractDataAccessVec_12; // @[Debug.scala:1257:45, :1263:68]
wire _dmiAbstractDataAccess_T_12 = _dmiAbstractDataAccess_T_11 | dmiAbstractDataAccessVec_13; // @[Debug.scala:1257:45, :1263:68]
wire _dmiAbstractDataAccess_T_13 = _dmiAbstractDataAccess_T_12 | dmiAbstractDataAccessVec_14; // @[Debug.scala:1257:45, :1263:68]
wire _dmiAbstractDataAccess_T_14 = _dmiAbstractDataAccess_T_13 | dmiAbstractDataAccessVec_15; // @[Debug.scala:1257:45, :1263:68]
wire _dmiAbstractDataAccess_T_15 = _dmiAbstractDataAccess_T_14 | dmiAbstractDataAccessVec_16; // @[Debug.scala:1257:45, :1263:68]
wire _dmiAbstractDataAccess_T_16 = _dmiAbstractDataAccess_T_15 | dmiAbstractDataAccessVec_17; // @[Debug.scala:1257:45, :1263:68]
wire _dmiAbstractDataAccess_T_17 = _dmiAbstractDataAccess_T_16 | dmiAbstractDataAccessVec_18; // @[Debug.scala:1257:45, :1263:68]
wire _dmiAbstractDataAccess_T_18 = _dmiAbstractDataAccess_T_17 | dmiAbstractDataAccessVec_19; // @[Debug.scala:1257:45, :1263:68]
wire _dmiAbstractDataAccess_T_19 = _dmiAbstractDataAccess_T_18 | dmiAbstractDataAccessVec_20; // @[Debug.scala:1257:45, :1263:68]
wire _dmiAbstractDataAccess_T_20 = _dmiAbstractDataAccess_T_19 | dmiAbstractDataAccessVec_21; // @[Debug.scala:1257:45, :1263:68]
wire _dmiAbstractDataAccess_T_21 = _dmiAbstractDataAccess_T_20 | dmiAbstractDataAccessVec_22; // @[Debug.scala:1257:45, :1263:68]
wire _dmiAbstractDataAccess_T_22 = _dmiAbstractDataAccess_T_21 | dmiAbstractDataAccessVec_23; // @[Debug.scala:1257:45, :1263:68]
wire _dmiAbstractDataAccess_T_23 = _dmiAbstractDataAccess_T_22 | dmiAbstractDataAccessVec_24; // @[Debug.scala:1257:45, :1263:68]
wire _dmiAbstractDataAccess_T_24 = _dmiAbstractDataAccess_T_23 | dmiAbstractDataAccessVec_25; // @[Debug.scala:1257:45, :1263:68]
wire _dmiAbstractDataAccess_T_25 = _dmiAbstractDataAccess_T_24 | dmiAbstractDataAccessVec_26; // @[Debug.scala:1257:45, :1263:68]
wire _dmiAbstractDataAccess_T_26 = _dmiAbstractDataAccess_T_25 | dmiAbstractDataAccessVec_27; // @[Debug.scala:1257:45, :1263:68]
wire _dmiAbstractDataAccess_T_27 = _dmiAbstractDataAccess_T_26 | dmiAbstractDataAccessVec_28; // @[Debug.scala:1257:45, :1263:68]
wire _dmiAbstractDataAccess_T_28 = _dmiAbstractDataAccess_T_27 | dmiAbstractDataAccessVec_29; // @[Debug.scala:1257:45, :1263:68]
wire _dmiAbstractDataAccess_T_29 = _dmiAbstractDataAccess_T_28 | dmiAbstractDataAccessVec_30; // @[Debug.scala:1257:45, :1263:68]
wire dmiAbstractDataAccess = _dmiAbstractDataAccess_T_29 | dmiAbstractDataAccessVec_31; // @[Debug.scala:1257:45, :1263:68]
wire _dmiProgramBufferAccess_T = dmiProgramBufferAccessVec_0 | dmiProgramBufferAccessVec_1; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_1 = _dmiProgramBufferAccess_T | dmiProgramBufferAccessVec_2; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_2 = _dmiProgramBufferAccess_T_1 | dmiProgramBufferAccessVec_3; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_3 = _dmiProgramBufferAccess_T_2 | dmiProgramBufferAccessVec_4; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_4 = _dmiProgramBufferAccess_T_3 | dmiProgramBufferAccessVec_5; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_5 = _dmiProgramBufferAccess_T_4 | dmiProgramBufferAccessVec_6; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_6 = _dmiProgramBufferAccess_T_5 | dmiProgramBufferAccessVec_7; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_7 = _dmiProgramBufferAccess_T_6 | dmiProgramBufferAccessVec_8; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_8 = _dmiProgramBufferAccess_T_7 | dmiProgramBufferAccessVec_9; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_9 = _dmiProgramBufferAccess_T_8 | dmiProgramBufferAccessVec_10; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_10 = _dmiProgramBufferAccess_T_9 | dmiProgramBufferAccessVec_11; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_11 = _dmiProgramBufferAccess_T_10 | dmiProgramBufferAccessVec_12; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_12 = _dmiProgramBufferAccess_T_11 | dmiProgramBufferAccessVec_13; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_13 = _dmiProgramBufferAccess_T_12 | dmiProgramBufferAccessVec_14; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_14 = _dmiProgramBufferAccess_T_13 | dmiProgramBufferAccessVec_15; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_15 = _dmiProgramBufferAccess_T_14 | dmiProgramBufferAccessVec_16; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_16 = _dmiProgramBufferAccess_T_15 | dmiProgramBufferAccessVec_17; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_17 = _dmiProgramBufferAccess_T_16 | dmiProgramBufferAccessVec_18; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_18 = _dmiProgramBufferAccess_T_17 | dmiProgramBufferAccessVec_19; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_19 = _dmiProgramBufferAccess_T_18 | dmiProgramBufferAccessVec_20; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_20 = _dmiProgramBufferAccess_T_19 | dmiProgramBufferAccessVec_21; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_21 = _dmiProgramBufferAccess_T_20 | dmiProgramBufferAccessVec_22; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_22 = _dmiProgramBufferAccess_T_21 | dmiProgramBufferAccessVec_23; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_23 = _dmiProgramBufferAccess_T_22 | dmiProgramBufferAccessVec_24; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_24 = _dmiProgramBufferAccess_T_23 | dmiProgramBufferAccessVec_25; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_25 = _dmiProgramBufferAccess_T_24 | dmiProgramBufferAccessVec_26; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_26 = _dmiProgramBufferAccess_T_25 | dmiProgramBufferAccessVec_27; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_27 = _dmiProgramBufferAccess_T_26 | dmiProgramBufferAccessVec_28; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_28 = _dmiProgramBufferAccess_T_27 | dmiProgramBufferAccessVec_29; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_29 = _dmiProgramBufferAccess_T_28 | dmiProgramBufferAccessVec_30; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_30 = _dmiProgramBufferAccess_T_29 | dmiProgramBufferAccessVec_31; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_31 = _dmiProgramBufferAccess_T_30 | dmiProgramBufferAccessVec_32; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_32 = _dmiProgramBufferAccess_T_31 | dmiProgramBufferAccessVec_33; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_33 = _dmiProgramBufferAccess_T_32 | dmiProgramBufferAccessVec_34; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_34 = _dmiProgramBufferAccess_T_33 | dmiProgramBufferAccessVec_35; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_35 = _dmiProgramBufferAccess_T_34 | dmiProgramBufferAccessVec_36; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_36 = _dmiProgramBufferAccess_T_35 | dmiProgramBufferAccessVec_37; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_37 = _dmiProgramBufferAccess_T_36 | dmiProgramBufferAccessVec_38; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_38 = _dmiProgramBufferAccess_T_37 | dmiProgramBufferAccessVec_39; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_39 = _dmiProgramBufferAccess_T_38 | dmiProgramBufferAccessVec_40; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_40 = _dmiProgramBufferAccess_T_39 | dmiProgramBufferAccessVec_41; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_41 = _dmiProgramBufferAccess_T_40 | dmiProgramBufferAccessVec_42; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_42 = _dmiProgramBufferAccess_T_41 | dmiProgramBufferAccessVec_43; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_43 = _dmiProgramBufferAccess_T_42 | dmiProgramBufferAccessVec_44; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_44 = _dmiProgramBufferAccess_T_43 | dmiProgramBufferAccessVec_45; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_45 = _dmiProgramBufferAccess_T_44 | dmiProgramBufferAccessVec_46; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_46 = _dmiProgramBufferAccess_T_45 | dmiProgramBufferAccessVec_47; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_47 = _dmiProgramBufferAccess_T_46 | dmiProgramBufferAccessVec_48; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_48 = _dmiProgramBufferAccess_T_47 | dmiProgramBufferAccessVec_49; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_49 = _dmiProgramBufferAccess_T_48 | dmiProgramBufferAccessVec_50; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_50 = _dmiProgramBufferAccess_T_49 | dmiProgramBufferAccessVec_51; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_51 = _dmiProgramBufferAccess_T_50 | dmiProgramBufferAccessVec_52; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_52 = _dmiProgramBufferAccess_T_51 | dmiProgramBufferAccessVec_53; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_53 = _dmiProgramBufferAccess_T_52 | dmiProgramBufferAccessVec_54; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_54 = _dmiProgramBufferAccess_T_53 | dmiProgramBufferAccessVec_55; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_55 = _dmiProgramBufferAccess_T_54 | dmiProgramBufferAccessVec_56; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_56 = _dmiProgramBufferAccess_T_55 | dmiProgramBufferAccessVec_57; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_57 = _dmiProgramBufferAccess_T_56 | dmiProgramBufferAccessVec_58; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_58 = _dmiProgramBufferAccess_T_57 | dmiProgramBufferAccessVec_59; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_59 = _dmiProgramBufferAccess_T_58 | dmiProgramBufferAccessVec_60; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_60 = _dmiProgramBufferAccess_T_59 | dmiProgramBufferAccessVec_61; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_61 = _dmiProgramBufferAccess_T_60 | dmiProgramBufferAccessVec_62; // @[Debug.scala:1260:46, :1264:69]
wire dmiProgramBufferAccess = _dmiProgramBufferAccess_T_61 | dmiProgramBufferAccessVec_63; // @[Debug.scala:1260:46, :1264:69]
wire _autoexecData_0_T; // @[Debug.scala:1269:140]
wire _autoexecData_1_T; // @[Debug.scala:1269:140]
wire _autoexecData_2_T; // @[Debug.scala:1269:140]
wire _autoexecData_3_T; // @[Debug.scala:1269:140]
wire _autoexecData_4_T; // @[Debug.scala:1269:140]
wire _autoexecData_5_T; // @[Debug.scala:1269:140]
wire _autoexecData_6_T; // @[Debug.scala:1269:140]
wire _autoexecData_7_T; // @[Debug.scala:1269:140]
wire autoexecData_0; // @[Debug.scala:1267:33]
wire autoexecData_1; // @[Debug.scala:1267:33]
wire autoexecData_2; // @[Debug.scala:1267:33]
wire autoexecData_3; // @[Debug.scala:1267:33]
wire autoexecData_4; // @[Debug.scala:1267:33]
wire autoexecData_5; // @[Debug.scala:1267:33]
wire autoexecData_6; // @[Debug.scala:1267:33]
wire autoexecData_7; // @[Debug.scala:1267:33]
wire _autoexecProg_0_T; // @[Debug.scala:1270:144]
wire _autoexecProg_1_T; // @[Debug.scala:1270:144]
wire _autoexecProg_2_T; // @[Debug.scala:1270:144]
wire _autoexecProg_3_T; // @[Debug.scala:1270:144]
wire _autoexecProg_4_T; // @[Debug.scala:1270:144]
wire _autoexecProg_5_T; // @[Debug.scala:1270:144]
wire _autoexecProg_6_T; // @[Debug.scala:1270:144]
wire _autoexecProg_7_T; // @[Debug.scala:1270:144]
wire _autoexecProg_8_T; // @[Debug.scala:1270:144]
wire _autoexecProg_9_T; // @[Debug.scala:1270:144]
wire _autoexecProg_10_T; // @[Debug.scala:1270:144]
wire _autoexecProg_11_T; // @[Debug.scala:1270:144]
wire _autoexecProg_12_T; // @[Debug.scala:1270:144]
wire _autoexecProg_13_T; // @[Debug.scala:1270:144]
wire _autoexecProg_14_T; // @[Debug.scala:1270:144]
wire _autoexecProg_15_T; // @[Debug.scala:1270:144]
wire autoexecProg_0; // @[Debug.scala:1268:33]
wire autoexecProg_1; // @[Debug.scala:1268:33]
wire autoexecProg_2; // @[Debug.scala:1268:33]
wire autoexecProg_3; // @[Debug.scala:1268:33]
wire autoexecProg_4; // @[Debug.scala:1268:33]
wire autoexecProg_5; // @[Debug.scala:1268:33]
wire autoexecProg_6; // @[Debug.scala:1268:33]
wire autoexecProg_7; // @[Debug.scala:1268:33]
wire autoexecProg_8; // @[Debug.scala:1268:33]
wire autoexecProg_9; // @[Debug.scala:1268:33]
wire autoexecProg_10; // @[Debug.scala:1268:33]
wire autoexecProg_11; // @[Debug.scala:1268:33]
wire autoexecProg_12; // @[Debug.scala:1268:33]
wire autoexecProg_13; // @[Debug.scala:1268:33]
wire autoexecProg_14; // @[Debug.scala:1268:33]
wire autoexecProg_15; // @[Debug.scala:1268:33]
assign _autoexecData_0_T = dmiAbstractDataAccessVec_0 & ABSTRACTAUTOReg_autoexecdata[0]; // @[Debug.scala:1235:36, :1257:45, :1269:{54,140}]
assign autoexecData_0 = _autoexecData_0_T; // @[Debug.scala:1267:33, :1269:140]
assign _autoexecData_1_T = dmiAbstractDataAccessVec_4 & ABSTRACTAUTOReg_autoexecdata[1]; // @[Debug.scala:1235:36, :1257:45, :1269:{54,140}]
assign autoexecData_1 = _autoexecData_1_T; // @[Debug.scala:1267:33, :1269:140]
assign _autoexecData_2_T = dmiAbstractDataAccessVec_8 & ABSTRACTAUTOReg_autoexecdata[2]; // @[Debug.scala:1235:36, :1257:45, :1269:{54,140}]
assign autoexecData_2 = _autoexecData_2_T; // @[Debug.scala:1267:33, :1269:140]
assign _autoexecData_3_T = dmiAbstractDataAccessVec_12 & ABSTRACTAUTOReg_autoexecdata[3]; // @[Debug.scala:1235:36, :1257:45, :1269:{54,140}]
assign autoexecData_3 = _autoexecData_3_T; // @[Debug.scala:1267:33, :1269:140]
assign _autoexecData_4_T = dmiAbstractDataAccessVec_16 & ABSTRACTAUTOReg_autoexecdata[4]; // @[Debug.scala:1235:36, :1257:45, :1269:{54,140}]
assign autoexecData_4 = _autoexecData_4_T; // @[Debug.scala:1267:33, :1269:140]
assign _autoexecData_5_T = dmiAbstractDataAccessVec_20 & ABSTRACTAUTOReg_autoexecdata[5]; // @[Debug.scala:1235:36, :1257:45, :1269:{54,140}]
assign autoexecData_5 = _autoexecData_5_T; // @[Debug.scala:1267:33, :1269:140]
assign _autoexecData_6_T = dmiAbstractDataAccessVec_24 & ABSTRACTAUTOReg_autoexecdata[6]; // @[Debug.scala:1235:36, :1257:45, :1269:{54,140}]
assign autoexecData_6 = _autoexecData_6_T; // @[Debug.scala:1267:33, :1269:140]
assign _autoexecData_7_T = dmiAbstractDataAccessVec_28 & ABSTRACTAUTOReg_autoexecdata[7]; // @[Debug.scala:1235:36, :1257:45, :1269:{54,140}]
assign autoexecData_7 = _autoexecData_7_T; // @[Debug.scala:1267:33, :1269:140]
assign _autoexecProg_0_T = dmiProgramBufferAccessVec_0 & ABSTRACTAUTOReg_autoexecprogbuf[0]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}]
assign autoexecProg_0 = _autoexecProg_0_T; // @[Debug.scala:1268:33, :1270:144]
assign _autoexecProg_1_T = dmiProgramBufferAccessVec_4 & ABSTRACTAUTOReg_autoexecprogbuf[1]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}]
assign autoexecProg_1 = _autoexecProg_1_T; // @[Debug.scala:1268:33, :1270:144]
assign _autoexecProg_2_T = dmiProgramBufferAccessVec_8 & ABSTRACTAUTOReg_autoexecprogbuf[2]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}]
assign autoexecProg_2 = _autoexecProg_2_T; // @[Debug.scala:1268:33, :1270:144]
assign _autoexecProg_3_T = dmiProgramBufferAccessVec_12 & ABSTRACTAUTOReg_autoexecprogbuf[3]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}]
assign autoexecProg_3 = _autoexecProg_3_T; // @[Debug.scala:1268:33, :1270:144]
assign _autoexecProg_4_T = dmiProgramBufferAccessVec_16 & ABSTRACTAUTOReg_autoexecprogbuf[4]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}]
assign autoexecProg_4 = _autoexecProg_4_T; // @[Debug.scala:1268:33, :1270:144]
assign _autoexecProg_5_T = dmiProgramBufferAccessVec_20 & ABSTRACTAUTOReg_autoexecprogbuf[5]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}]
assign autoexecProg_5 = _autoexecProg_5_T; // @[Debug.scala:1268:33, :1270:144]
assign _autoexecProg_6_T = dmiProgramBufferAccessVec_24 & ABSTRACTAUTOReg_autoexecprogbuf[6]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}]
assign autoexecProg_6 = _autoexecProg_6_T; // @[Debug.scala:1268:33, :1270:144]
assign _autoexecProg_7_T = dmiProgramBufferAccessVec_28 & ABSTRACTAUTOReg_autoexecprogbuf[7]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}]
assign autoexecProg_7 = _autoexecProg_7_T; // @[Debug.scala:1268:33, :1270:144]
assign _autoexecProg_8_T = dmiProgramBufferAccessVec_32 & ABSTRACTAUTOReg_autoexecprogbuf[8]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}]
assign autoexecProg_8 = _autoexecProg_8_T; // @[Debug.scala:1268:33, :1270:144]
assign _autoexecProg_9_T = dmiProgramBufferAccessVec_36 & ABSTRACTAUTOReg_autoexecprogbuf[9]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}]
assign autoexecProg_9 = _autoexecProg_9_T; // @[Debug.scala:1268:33, :1270:144]
assign _autoexecProg_10_T = dmiProgramBufferAccessVec_40 & ABSTRACTAUTOReg_autoexecprogbuf[10]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}]
assign autoexecProg_10 = _autoexecProg_10_T; // @[Debug.scala:1268:33, :1270:144]
assign _autoexecProg_11_T = dmiProgramBufferAccessVec_44 & ABSTRACTAUTOReg_autoexecprogbuf[11]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}]
assign autoexecProg_11 = _autoexecProg_11_T; // @[Debug.scala:1268:33, :1270:144]
assign _autoexecProg_12_T = dmiProgramBufferAccessVec_48 & ABSTRACTAUTOReg_autoexecprogbuf[12]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}]
assign autoexecProg_12 = _autoexecProg_12_T; // @[Debug.scala:1268:33, :1270:144]
assign _autoexecProg_13_T = dmiProgramBufferAccessVec_52 & ABSTRACTAUTOReg_autoexecprogbuf[13]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}]
assign autoexecProg_13 = _autoexecProg_13_T; // @[Debug.scala:1268:33, :1270:144]
assign _autoexecProg_14_T = dmiProgramBufferAccessVec_56 & ABSTRACTAUTOReg_autoexecprogbuf[14]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}]
assign autoexecProg_14 = _autoexecProg_14_T; // @[Debug.scala:1268:33, :1270:144]
assign _autoexecProg_15_T = dmiProgramBufferAccessVec_60 & ABSTRACTAUTOReg_autoexecprogbuf[15]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}]
assign autoexecProg_15 = _autoexecProg_15_T; // @[Debug.scala:1268:33, :1270:144]
wire _autoexec_T = autoexecData_0 | autoexecData_1; // @[Debug.scala:1267:33, :1272:42]
wire _autoexec_T_1 = _autoexec_T | autoexecData_2; // @[Debug.scala:1267:33, :1272:42]
wire _autoexec_T_2 = _autoexec_T_1 | autoexecData_3; // @[Debug.scala:1267:33, :1272:42]
wire _autoexec_T_3 = _autoexec_T_2 | autoexecData_4; // @[Debug.scala:1267:33, :1272:42]
wire _autoexec_T_4 = _autoexec_T_3 | autoexecData_5; // @[Debug.scala:1267:33, :1272:42]
wire _autoexec_T_5 = _autoexec_T_4 | autoexecData_6; // @[Debug.scala:1267:33, :1272:42]
wire _autoexec_T_6 = _autoexec_T_5 | autoexecData_7; // @[Debug.scala:1267:33, :1272:42]
wire _autoexec_T_7 = autoexecProg_0 | autoexecProg_1; // @[Debug.scala:1268:33, :1272:73]
wire _autoexec_T_8 = _autoexec_T_7 | autoexecProg_2; // @[Debug.scala:1268:33, :1272:73]
wire _autoexec_T_9 = _autoexec_T_8 | autoexecProg_3; // @[Debug.scala:1268:33, :1272:73]
wire _autoexec_T_10 = _autoexec_T_9 | autoexecProg_4; // @[Debug.scala:1268:33, :1272:73]
wire _autoexec_T_11 = _autoexec_T_10 | autoexecProg_5; // @[Debug.scala:1268:33, :1272:73]
wire _autoexec_T_12 = _autoexec_T_11 | autoexecProg_6; // @[Debug.scala:1268:33, :1272:73]
wire _autoexec_T_13 = _autoexec_T_12 | autoexecProg_7; // @[Debug.scala:1268:33, :1272:73]
wire _autoexec_T_14 = _autoexec_T_13 | autoexecProg_8; // @[Debug.scala:1268:33, :1272:73]
wire _autoexec_T_15 = _autoexec_T_14 | autoexecProg_9; // @[Debug.scala:1268:33, :1272:73]
wire _autoexec_T_16 = _autoexec_T_15 | autoexecProg_10; // @[Debug.scala:1268:33, :1272:73]
wire _autoexec_T_17 = _autoexec_T_16 | autoexecProg_11; // @[Debug.scala:1268:33, :1272:73]
wire _autoexec_T_18 = _autoexec_T_17 | autoexecProg_12; // @[Debug.scala:1268:33, :1272:73]
wire _autoexec_T_19 = _autoexec_T_18 | autoexecProg_13; // @[Debug.scala:1268:33, :1272:73]
wire _autoexec_T_20 = _autoexec_T_19 | autoexecProg_14; // @[Debug.scala:1268:33, :1272:73]
wire _autoexec_T_21 = _autoexec_T_20 | autoexecProg_15; // @[Debug.scala:1268:33, :1272:73]
wire autoexec = _autoexec_T_6 | _autoexec_T_21; // @[Debug.scala:1272:{42,48,73}]
reg [7:0] COMMANDReg_cmdtype; // @[Debug.scala:1277:25]
reg [23:0] COMMANDReg_control; // @[Debug.scala:1277:25]
wire [31:0] COMMANDWrDataVal; // @[Debug.scala:1279:39]
wire [31:0] _COMMANDWrData_WIRE_1 = COMMANDWrDataVal; // @[Debug.scala:1279:39, :1280:65]
wire [7:0] _COMMANDWrData_T_1; // @[Debug.scala:1280:65]
wire [23:0] _COMMANDWrData_T; // @[Debug.scala:1280:65]
wire [7:0] COMMANDWrData_cmdtype = _COMMANDWrData_WIRE_cmdtype; // @[Debug.scala:1280:{39,65}]
wire [23:0] COMMANDWrData_control = _COMMANDWrData_WIRE_control; // @[Debug.scala:1280:{39,65}]
assign _COMMANDWrData_T = _COMMANDWrData_WIRE_1[23:0]; // @[Debug.scala:1280:65]
assign _COMMANDWrData_WIRE_control = _COMMANDWrData_T; // @[Debug.scala:1280:65]
assign _COMMANDWrData_T_1 = _COMMANDWrData_WIRE_1[31:24]; // @[Debug.scala:1280:65]
assign _COMMANDWrData_WIRE_cmdtype = _COMMANDWrData_T_1; // @[Debug.scala:1280:65]
wire out_f_woready_140; // @[RegisterRouter.scala:87:24]
wire COMMANDWrEnMaybe; // @[Debug.scala:1281:39]
wire _COMMANDWrEnLegal_T; // @[Debug.scala:1743:44]
wire COMMANDWrEnLegal; // @[Debug.scala:1282:39]
wire out_f_roready_140; // @[RegisterRouter.scala:87:24]
wire COMMANDRdEn; // @[Debug.scala:1283:32]
wire COMMANDWrEn = COMMANDWrEnMaybe & COMMANDWrEnLegal; // @[Debug.scala:1281:39, :1282:39, :1285:40]
reg [7:0] abstractDataMem_0; // @[Debug.scala:1300:36]
wire [7:0] _out_T_308 = abstractDataMem_0; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9474 = abstractDataMem_0; // @[RegisterRouter.scala:87:24]
reg [7:0] abstractDataMem_1; // @[Debug.scala:1300:36]
reg [7:0] abstractDataMem_2; // @[Debug.scala:1300:36]
reg [7:0] abstractDataMem_3; // @[Debug.scala:1300:36]
reg [7:0] abstractDataMem_4; // @[Debug.scala:1300:36]
wire [7:0] _out_T_77 = abstractDataMem_4; // @[RegisterRouter.scala:87:24]
reg [7:0] abstractDataMem_5; // @[Debug.scala:1300:36]
reg [7:0] abstractDataMem_6; // @[Debug.scala:1300:36]
reg [7:0] abstractDataMem_7; // @[Debug.scala:1300:36]
reg [7:0] abstractDataMem_8; // @[Debug.scala:1300:36]
wire [7:0] _out_T_761 = abstractDataMem_8; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7912 = abstractDataMem_8; // @[RegisterRouter.scala:87:24]
reg [7:0] abstractDataMem_9; // @[Debug.scala:1300:36]
reg [7:0] abstractDataMem_10; // @[Debug.scala:1300:36]
reg [7:0] abstractDataMem_11; // @[Debug.scala:1300:36]
reg [7:0] abstractDataMem_12; // @[Debug.scala:1300:36]
wire [7:0] _out_T_1325 = abstractDataMem_12; // @[RegisterRouter.scala:87:24]
reg [7:0] abstractDataMem_13; // @[Debug.scala:1300:36]
reg [7:0] abstractDataMem_14; // @[Debug.scala:1300:36]
reg [7:0] abstractDataMem_15; // @[Debug.scala:1300:36]
reg [7:0] abstractDataMem_16; // @[Debug.scala:1300:36]
wire [7:0] _out_T_264 = abstractDataMem_16; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10874 = abstractDataMem_16; // @[RegisterRouter.scala:87:24]
reg [7:0] abstractDataMem_17; // @[Debug.scala:1300:36]
reg [7:0] abstractDataMem_18; // @[Debug.scala:1300:36]
reg [7:0] abstractDataMem_19; // @[Debug.scala:1300:36]
reg [7:0] abstractDataMem_20; // @[Debug.scala:1300:36]
wire [7:0] _out_T_132 = abstractDataMem_20; // @[RegisterRouter.scala:87:24]
reg [7:0] abstractDataMem_21; // @[Debug.scala:1300:36]
reg [7:0] abstractDataMem_22; // @[Debug.scala:1300:36]
reg [7:0] abstractDataMem_23; // @[Debug.scala:1300:36]
reg [7:0] abstractDataMem_24; // @[Debug.scala:1300:36]
wire [7:0] _out_T_396 = abstractDataMem_24; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2207 = abstractDataMem_24; // @[RegisterRouter.scala:87:24]
reg [7:0] abstractDataMem_25; // @[Debug.scala:1300:36]
reg [7:0] abstractDataMem_26; // @[Debug.scala:1300:36]
reg [7:0] abstractDataMem_27; // @[Debug.scala:1300:36]
reg [7:0] abstractDataMem_28; // @[Debug.scala:1300:36]
wire [7:0] _out_T_1413 = abstractDataMem_28; // @[RegisterRouter.scala:87:24]
reg [7:0] abstractDataMem_29; // @[Debug.scala:1300:36]
reg [7:0] abstractDataMem_30; // @[Debug.scala:1300:36]
reg [7:0] abstractDataMem_31; // @[Debug.scala:1300:36]
wire [7:0] abstractDataNxt_0; // @[Debug.scala:1301:41]
wire [7:0] abstractDataNxt_1; // @[Debug.scala:1301:41]
wire [7:0] abstractDataNxt_2; // @[Debug.scala:1301:41]
wire [7:0] abstractDataNxt_3; // @[Debug.scala:1301:41]
wire [7:0] abstractDataNxt_4; // @[Debug.scala:1301:41]
wire [7:0] abstractDataNxt_5; // @[Debug.scala:1301:41]
wire [7:0] abstractDataNxt_6; // @[Debug.scala:1301:41]
wire [7:0] abstractDataNxt_7; // @[Debug.scala:1301:41]
wire [7:0] abstractDataNxt_8; // @[Debug.scala:1301:41]
wire [7:0] abstractDataNxt_9; // @[Debug.scala:1301:41]
wire [7:0] abstractDataNxt_10; // @[Debug.scala:1301:41]
wire [7:0] abstractDataNxt_11; // @[Debug.scala:1301:41]
wire [7:0] abstractDataNxt_12; // @[Debug.scala:1301:41]
wire [7:0] abstractDataNxt_13; // @[Debug.scala:1301:41]
wire [7:0] abstractDataNxt_14; // @[Debug.scala:1301:41]
wire [7:0] abstractDataNxt_15; // @[Debug.scala:1301:41]
wire [7:0] abstractDataNxt_16; // @[Debug.scala:1301:41]
wire [7:0] abstractDataNxt_17; // @[Debug.scala:1301:41]
wire [7:0] abstractDataNxt_18; // @[Debug.scala:1301:41]
wire [7:0] abstractDataNxt_19; // @[Debug.scala:1301:41]
wire [7:0] abstractDataNxt_20; // @[Debug.scala:1301:41]
wire [7:0] abstractDataNxt_21; // @[Debug.scala:1301:41]
wire [7:0] abstractDataNxt_22; // @[Debug.scala:1301:41]
wire [7:0] abstractDataNxt_23; // @[Debug.scala:1301:41]
wire [7:0] abstractDataNxt_24; // @[Debug.scala:1301:41]
wire [7:0] abstractDataNxt_25; // @[Debug.scala:1301:41]
wire [7:0] abstractDataNxt_26; // @[Debug.scala:1301:41]
wire [7:0] abstractDataNxt_27; // @[Debug.scala:1301:41]
wire [7:0] abstractDataNxt_28; // @[Debug.scala:1301:41]
wire [7:0] abstractDataNxt_29; // @[Debug.scala:1301:41]
wire [7:0] abstractDataNxt_30; // @[Debug.scala:1301:41]
wire [7:0] abstractDataNxt_31; // @[Debug.scala:1301:41]
reg [7:0] programBufferMem_0; // @[Debug.scala:1306:34]
wire [7:0] _out_T_1128 = programBufferMem_0; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10426 = programBufferMem_0; // @[RegisterRouter.scala:87:24]
reg [7:0] programBufferMem_1; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_2; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_3; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_4; // @[Debug.scala:1306:34]
wire [7:0] _out_T_860 = programBufferMem_4; // @[RegisterRouter.scala:87:24]
reg [7:0] programBufferMem_5; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_6; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_7; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_8; // @[Debug.scala:1306:34]
wire [7:0] _out_T_1172 = programBufferMem_8; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6582 = programBufferMem_8; // @[RegisterRouter.scala:87:24]
reg [7:0] programBufferMem_9; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_10; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_11; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_12; // @[Debug.scala:1306:34]
wire [7:0] _out_T_220 = programBufferMem_12; // @[RegisterRouter.scala:87:24]
reg [7:0] programBufferMem_13; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_14; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_15; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_16; // @[Debug.scala:1306:34]
wire [7:0] _out_T_1556 = programBufferMem_16; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3679 = programBufferMem_16; // @[RegisterRouter.scala:87:24]
reg [7:0] programBufferMem_17; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_18; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_19; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_20; // @[Debug.scala:1306:34]
wire [7:0] _out_T_662 = programBufferMem_20; // @[RegisterRouter.scala:87:24]
reg [7:0] programBufferMem_21; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_22; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_23; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_24; // @[Debug.scala:1306:34]
wire [7:0] _out_T_816 = programBufferMem_24; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11898 = programBufferMem_24; // @[RegisterRouter.scala:87:24]
reg [7:0] programBufferMem_25; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_26; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_27; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_28; // @[Debug.scala:1306:34]
wire [7:0] _out_T_1369 = programBufferMem_28; // @[RegisterRouter.scala:87:24]
reg [7:0] programBufferMem_29; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_30; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_31; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_32; // @[Debug.scala:1306:34]
wire [7:0] _out_T_1501 = programBufferMem_32; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8594 = programBufferMem_32; // @[RegisterRouter.scala:87:24]
reg [7:0] programBufferMem_33; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_34; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_35; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_36; // @[Debug.scala:1306:34]
wire [7:0] _out_T_176 = programBufferMem_36; // @[RegisterRouter.scala:87:24]
reg [7:0] programBufferMem_37; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_38; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_39; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_40; // @[Debug.scala:1306:34]
wire [7:0] _out_T_587 = programBufferMem_40; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5954 = programBufferMem_40; // @[RegisterRouter.scala:87:24]
reg [7:0] programBufferMem_41; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_42; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_43; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_44; // @[Debug.scala:1306:34]
wire [7:0] _out_T_1457 = programBufferMem_44; // @[RegisterRouter.scala:87:24]
reg [7:0] programBufferMem_45; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_46; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_47; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_48; // @[Debug.scala:1306:34]
wire [7:0] _out_T_1281 = programBufferMem_48; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2943 = programBufferMem_48; // @[RegisterRouter.scala:87:24]
reg [7:0] programBufferMem_49; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_50; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_51; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_52; // @[Debug.scala:1306:34]
wire [7:0] _out_T_904 = programBufferMem_52; // @[RegisterRouter.scala:87:24]
reg [7:0] programBufferMem_53; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_54; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_55; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_56; // @[Debug.scala:1306:34]
wire [7:0] _out_T_706 = programBufferMem_56; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12562 = programBufferMem_56; // @[RegisterRouter.scala:87:24]
reg [7:0] programBufferMem_57; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_58; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_59; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_60; // @[Debug.scala:1306:34]
wire [7:0] _out_T_352 = programBufferMem_60; // @[RegisterRouter.scala:87:24]
reg [7:0] programBufferMem_61; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_62; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_63; // @[Debug.scala:1306:34]
wire [7:0] programBufferNxt_0; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_1; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_2; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_3; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_4; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_5; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_6; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_7; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_8; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_9; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_10; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_11; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_12; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_13; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_14; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_15; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_16; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_17; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_18; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_19; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_20; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_21; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_22; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_23; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_24; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_25; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_26; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_27; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_28; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_29; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_30; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_31; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_32; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_33; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_34; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_35; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_36; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_37; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_38; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_39; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_40; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_41; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_42; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_43; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_44; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_45; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_46; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_47; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_48; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_49; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_50; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_51; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_52; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_53; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_54; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_55; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_56; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_57; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_58; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_59; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_60; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_61; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_62; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_63; // @[Debug.scala:1307:39]
wire _resumeReqRegs_T = ~hartIsInResetSync_0; // @[Debug.scala:948:33, :1320:42]
wire _resumeReqRegs_T_1 = resumeReqRegs & _resumeReqRegs_T; // @[Debug.scala:863:31, :1320:{40,42}]
wire [1023:0] hartselIndex = 1024'h1 << io_innerCtrl_bits_hartsel_0; // @[OneHot.scala:58:35]
wire _haltedBitRegs_T_1 = ~hartIsInResetSync_0; // @[Debug.scala:948:33, :1320:42, :1327:66]
wire [1:0] _haltedBitRegs_T_2 = {1'h0, _haltedBitRegs_T[0] & _haltedBitRegs_T_1}; // @[Debug.scala:1327:{43,64,66}]
wire _haltedBitRegs_T_5 = ~hartIsInResetSync_0; // @[Debug.scala:948:33, :1320:42, :1330:71]
wire _haltedBitRegs_T_7 = ~hartIsInResetSync_0; // @[Debug.scala:948:33, :1320:42, :1333:44]
wire _haltedBitRegs_T_8 = haltedBitRegs & _haltedBitRegs_T_7; // @[Debug.scala:861:31, :1333:{42,44}]
wire _resumeReqRegs_T_4 = ~hartIsInResetSync_0; // @[Debug.scala:948:33, :1320:42, :1338:71]
wire _resumeReqRegs_T_6 = resumeReqRegs | hamaskWrSel_0; // @[Debug.scala:863:31, :933:31, :1342:43]
wire _resumeReqRegs_T_7 = ~hartIsInResetSync_0; // @[Debug.scala:948:33, :1320:42, :1342:67]
wire _resumeReqRegs_T_8 = _resumeReqRegs_T_6 & _resumeReqRegs_T_7; // @[Debug.scala:1342:{43,65,67}]
wire _resumeAcks_T = ~resumeReqRegs; // @[Debug.scala:863:31, :1349:24]
wire _resumeAcks_T_1 = ~hamaskWrSel_0; // @[Debug.scala:933:31, :1017:50, :1349:41]
wire _resumeAcks_T_2 = _resumeAcks_T & _resumeAcks_T_1; // @[Debug.scala:1349:{24,39,41}]
wire _resumeAcks_T_3 = ~resumeReqRegs; // @[Debug.scala:863:31, :1349:24, :1351:23]
assign resumeAcks = resumereq ? _resumeAcks_T_2 : _resumeAcks_T_3; // @[Debug.scala:869:32, :983:39, :1347:24, :1349:{20,39}, :1351:{20,23}]
wire _anyAddressWrEn_T_2; // @[SBA.scala:134:54]
wire anyAddressWrEn; // @[SBA.scala:42:34]
wire _anyDataRdEn_T_2; // @[SBA.scala:176:51]
wire anyDataRdEn; // @[SBA.scala:43:34]
wire _anyDataWrEn_T_2; // @[SBA.scala:177:51]
wire anyDataWrEn; // @[SBA.scala:44:34]
reg SBCSFieldsReg_sbbusyerror; // @[SBA.scala:47:28]
wire SBCSRdData_sbbusyerror = SBCSFieldsReg_sbbusyerror; // @[SBA.scala:47:28, :60:38]
reg SBCSFieldsReg_sbbusy; // @[SBA.scala:47:28]
reg SBCSFieldsReg_sbreadonaddr; // @[SBA.scala:47:28]
wire SBCSRdData_sbreadonaddr = SBCSFieldsReg_sbreadonaddr; // @[SBA.scala:47:28, :60:38]
reg [2:0] SBCSFieldsReg_sbaccess; // @[SBA.scala:47:28]
wire [2:0] SBCSRdData_sbaccess = SBCSFieldsReg_sbaccess; // @[SBA.scala:47:28, :60:38]
reg SBCSFieldsReg_sbautoincrement; // @[SBA.scala:47:28]
wire SBCSRdData_sbautoincrement = SBCSFieldsReg_sbautoincrement; // @[SBA.scala:47:28, :60:38]
reg SBCSFieldsReg_sbreadondata; // @[SBA.scala:47:28]
wire SBCSRdData_sbreadondata = SBCSFieldsReg_sbreadondata; // @[SBA.scala:47:28, :60:38]
wire _SBCSFieldsRegReset_sbbusy_T; // @[SBA.scala:51:67]
wire SBCSFieldsRegReset_sbbusy; // @[SBA.scala:49:38]
assign _SBCSFieldsRegReset_sbbusy_T = |_sb2tlOpt_io_sbStateOut; // @[SBA.scala:51:67]
assign SBCSFieldsRegReset_sbbusy = _SBCSFieldsRegReset_sbbusy_T; // @[SBA.scala:49:38, :51:67]
wire sbBusy; // @[SBA.scala:203:46]
wire SBCSRdData_sbbusy; // @[SBA.scala:60:38]
wire [2:0] SBCSRdData_sberror; // @[SBA.scala:60:38]
wire _out_T_549; // @[RegisterRouter.scala:87:24]
wire _out_T_529; // @[RegisterRouter.scala:87:24]
wire [2:0] _out_T_518; // @[RegisterRouter.scala:87:24]
wire _out_T_507; // @[RegisterRouter.scala:87:24]
wire _out_T_496; // @[RegisterRouter.scala:87:24]
wire [2:0] _out_T_485; // @[RegisterRouter.scala:87:24]
wire SBCSWrData_sbbusyerror; // @[SBA.scala:63:38]
wire SBCSWrData_sbreadonaddr; // @[SBA.scala:63:38]
wire [2:0] SBCSWrData_sbaccess; // @[SBA.scala:63:38]
wire SBCSWrData_sbautoincrement; // @[SBA.scala:63:38]
wire SBCSWrData_sbreadondata; // @[SBA.scala:63:38]
wire [2:0] SBCSWrData_sberror; // @[SBA.scala:63:38]
wire out_f_woready_39; // @[RegisterRouter.scala:87:24]
wire sberrorWrEn; // @[SBA.scala:65:38]
wire out_f_woready_40; // @[RegisterRouter.scala:87:24]
wire sbreadondataWrEn; // @[SBA.scala:66:38]
wire out_f_woready_41; // @[RegisterRouter.scala:87:24]
wire sbautoincrementWrEn; // @[SBA.scala:67:38]
wire out_f_woready_42; // @[RegisterRouter.scala:87:24]
wire sbaccessWrEn; // @[SBA.scala:68:38]
wire out_f_woready_43; // @[RegisterRouter.scala:87:24]
wire sbreadonaddrWrEn; // @[SBA.scala:69:38]
wire out_f_woready_45; // @[RegisterRouter.scala:87:24]
wire sbbusyerrorWrEn; // @[SBA.scala:70:38]
reg [31:0] SBADDRESSFieldsReg_0; // @[SBA.scala:104:33]
wire [31:0] _out_T_750 = SBADDRESSFieldsReg_0; // @[RegisterRouter.scala:87:24]
wire [31:0] SBADDRESSWrData_0; // @[SBA.scala:106:38]
wire out_f_roready_63; // @[RegisterRouter.scala:87:24]
wire SBADDRESSRdEn_0; // @[SBA.scala:107:38]
wire out_f_woready_63; // @[RegisterRouter.scala:87:24]
wire _anyAddressWrEn_T = SBADDRESSWrEn_0; // @[SBA.scala:108:38, :134:54]
wire [127:0] _autoIncrementedAddr_T_3; // @[SBA.scala:111:60]
wire [127:0] autoIncrementedAddr; // @[SBA.scala:110:39]
wire [63:0] _GEN_0 = {32'h0, SBADDRESSFieldsReg_0}; // @[SBA.scala:104:33, :111:31]
wire [63:0] autoIncrementedAddr_lo; // @[SBA.scala:111:31]
assign autoIncrementedAddr_lo = _GEN_0; // @[SBA.scala:111:31]
wire [63:0] sb2tlOpt_io_addrIn_lo; // @[SBA.scala:133:10]
assign sb2tlOpt_io_addrIn_lo = _GEN_0; // @[SBA.scala:111:31, :133:10]
wire [127:0] _autoIncrementedAddr_T = {64'h0, autoIncrementedAddr_lo}; // @[SBA.scala:111:31]
wire [7:0] _autoIncrementedAddr_T_1 = 8'h1 << SBCSFieldsReg_sbaccess; // @[SBA.scala:47:28, :111:67]
wire [128:0] _autoIncrementedAddr_T_2 = {1'h0, _autoIncrementedAddr_T} + {121'h0, _autoIncrementedAddr_T_1}; // @[SBA.scala:111:{31,60,67}]
assign _autoIncrementedAddr_T_3 = _autoIncrementedAddr_T_2[127:0]; // @[SBA.scala:111:60]
assign autoIncrementedAddr = _autoIncrementedAddr_T_3; // @[SBA.scala:110:39, :111:60]
wire _GEN_1 = SBCSRdData_sberror == 3'h0; // @[SBA.scala:60:38, :119:40]
wire _SBADDRESSFieldsReg_0_T; // @[SBA.scala:119:40]
assign _SBADDRESSFieldsReg_0_T = _GEN_1; // @[SBA.scala:119:40]
wire _SBDATAFieldsReg_0_0_T_4; // @[SBA.scala:160:97]
assign _SBDATAFieldsReg_0_0_T_4 = _GEN_1; // @[SBA.scala:119:40, :160:97]
wire _SBDATAFieldsReg_0_1_T_4; // @[SBA.scala:160:97]
assign _SBDATAFieldsReg_0_1_T_4 = _GEN_1; // @[SBA.scala:119:40, :160:97]
wire _SBDATAFieldsReg_0_2_T_4; // @[SBA.scala:160:97]
assign _SBDATAFieldsReg_0_2_T_4 = _GEN_1; // @[SBA.scala:119:40, :160:97]
wire _SBDATAFieldsReg_0_3_T_4; // @[SBA.scala:160:97]
assign _SBDATAFieldsReg_0_3_T_4 = _GEN_1; // @[SBA.scala:119:40, :160:97]
wire _SBDATAFieldsReg_1_0_T_4; // @[SBA.scala:160:97]
assign _SBDATAFieldsReg_1_0_T_4 = _GEN_1; // @[SBA.scala:119:40, :160:97]
wire _SBDATAFieldsReg_1_1_T_4; // @[SBA.scala:160:97]
assign _SBDATAFieldsReg_1_1_T_4 = _GEN_1; // @[SBA.scala:119:40, :160:97]
wire _SBDATAFieldsReg_1_2_T_4; // @[SBA.scala:160:97]
assign _SBDATAFieldsReg_1_2_T_4 = _GEN_1; // @[SBA.scala:119:40, :160:97]
wire _SBDATAFieldsReg_1_3_T_4; // @[SBA.scala:160:97]
assign _SBDATAFieldsReg_1_3_T_4 = _GEN_1; // @[SBA.scala:119:40, :160:97]
wire _sb2tlOpt_io_wrEn_T_5; // @[SBA.scala:199:118]
assign _sb2tlOpt_io_wrEn_T_5 = _GEN_1; // @[SBA.scala:119:40, :199:118]
wire _sb2tlOpt_io_rdEn_T_5; // @[SBA.scala:200:118]
assign _sb2tlOpt_io_rdEn_T_5 = _GEN_1; // @[SBA.scala:119:40, :200:118]
wire _SBADDRESSFieldsReg_0_T_1 = SBADDRESSWrEn_0 & _SBADDRESSFieldsReg_0_T; // @[SBA.scala:108:38, :119:{37,40}]
wire _SBADDRESSFieldsReg_0_T_2 = ~SBCSFieldsReg_sbbusy; // @[SBA.scala:47:28, :119:63]
wire _SBADDRESSFieldsReg_0_T_3 = _SBADDRESSFieldsReg_0_T_1 & _SBADDRESSFieldsReg_0_T_2; // @[SBA.scala:119:{37,60,63}]
wire _SBADDRESSFieldsReg_0_T_4 = ~SBCSFieldsReg_sbbusyerror; // @[SBA.scala:47:28, :119:88]
wire _SBADDRESSFieldsReg_0_T_5 = _SBADDRESSFieldsReg_0_T_3 & _SBADDRESSFieldsReg_0_T_4; // @[SBA.scala:119:{60,85,88}]
wire _GEN_2 = _sb2tlOpt_io_rdDone | _sb2tlOpt_io_wrDone; // @[SBA.scala:120:44]
wire _SBADDRESSFieldsReg_0_T_6; // @[SBA.scala:120:44]
assign _SBADDRESSFieldsReg_0_T_6 = _GEN_2; // @[SBA.scala:120:44]
wire _sbErrorReg_0_T_12; // @[SBA.scala:229:54]
assign _sbErrorReg_0_T_12 = _GEN_2; // @[SBA.scala:120:44, :229:54]
wire _sbErrorReg_1_T_12; // @[SBA.scala:229:54]
assign _sbErrorReg_1_T_12 = _GEN_2; // @[SBA.scala:120:44, :229:54]
wire _sbErrorReg_2_T_12; // @[SBA.scala:229:54]
assign _sbErrorReg_2_T_12 = _GEN_2; // @[SBA.scala:120:44, :229:54]
wire _SBADDRESSFieldsReg_0_T_7 = _SBADDRESSFieldsReg_0_T_6 & SBCSFieldsReg_sbautoincrement; // @[SBA.scala:47:28, :120:{44,71}]
wire [31:0] _SBADDRESSFieldsReg_0_T_8 = autoIncrementedAddr[31:0]; // @[SBA.scala:110:39, :120:124]
wire [31:0] _SBADDRESSFieldsReg_0_T_9 = _SBADDRESSFieldsReg_0_T_7 ? _SBADDRESSFieldsReg_0_T_8 : SBADDRESSFieldsReg_0; // @[SBA.scala:104:33, :120:{19,71,124}]
wire [31:0] _SBADDRESSFieldsReg_0_T_10 = _SBADDRESSFieldsReg_0_T_5 ? SBADDRESSWrData_0 : _SBADDRESSFieldsReg_0_T_9; // @[SBA.scala:106:38, :119:{19,85}, :120:19]
wire [127:0] _sb2tlOpt_io_addrIn_T_1 = {96'h0, SBADDRESSWrData_0}; // @[SBA.scala:106:38, :132:10]
wire [127:0] _sb2tlOpt_io_addrIn_T_2 = {64'h0, sb2tlOpt_io_addrIn_lo}; // @[SBA.scala:133:10]
wire [127:0] _sb2tlOpt_io_addrIn_T_3 = SBADDRESSWrEn_0 ? _sb2tlOpt_io_addrIn_T_1 : _sb2tlOpt_io_addrIn_T_2; // @[SBA.scala:108:38, :131:34, :132:10, :133:10]
wire _anyAddressWrEn_T_1 = _anyAddressWrEn_T; // @[SBA.scala:134:54]
assign _anyAddressWrEn_T_2 = _anyAddressWrEn_T_1; // @[SBA.scala:134:54]
assign anyAddressWrEn = _anyAddressWrEn_T_2; // @[SBA.scala:42:34, :134:54]
reg [7:0] SBDATAFieldsReg_0_0; // @[SBA.scala:143:30]
reg [7:0] SBDATAFieldsReg_0_1; // @[SBA.scala:143:30]
reg [7:0] SBDATAFieldsReg_0_2; // @[SBA.scala:143:30]
reg [7:0] SBDATAFieldsReg_0_3; // @[SBA.scala:143:30]
reg [7:0] SBDATAFieldsReg_1_0; // @[SBA.scala:143:30]
reg [7:0] SBDATAFieldsReg_1_1; // @[SBA.scala:143:30]
reg [7:0] SBDATAFieldsReg_1_2; // @[SBA.scala:143:30]
reg [7:0] SBDATAFieldsReg_1_3; // @[SBA.scala:143:30]
wire [31:0] _SBDATARdData_0_T; // @[SBA.scala:165:31]
wire [31:0] _SBDATARdData_1_T; // @[SBA.scala:165:31]
wire [31:0] _out_T_805 = SBDATARdData_0; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_121 = SBDATARdData_1; // @[RegisterRouter.scala:87:24]
wire [31:0] SBDATAWrData_0; // @[SBA.scala:147:35]
wire [31:0] SBDATAWrData_1; // @[SBA.scala:147:35]
wire out_f_roready_68; // @[RegisterRouter.scala:87:24]
wire out_f_roready_4; // @[RegisterRouter.scala:87:24]
wire SBDATARdEn_0; // @[SBA.scala:149:35]
wire SBDATARdEn_1; // @[SBA.scala:149:35]
wire out_f_woready_68; // @[RegisterRouter.scala:87:24]
wire _sb2tlOpt_io_wrEn_T = SBDATAWrEn_0; // @[SBA.scala:150:35, :199:49]
wire out_f_woready_4; // @[RegisterRouter.scala:87:24]
wire SBDATAWrEn_1; // @[SBA.scala:150:35]
wire _SBDATAFieldsReg_0_0_T = ~SBCSFieldsReg_sbbusy; // @[SBA.scala:47:28, :119:63, :160:42]
wire _SBDATAFieldsReg_0_0_T_1 = SBDATAWrEn_0 & _SBDATAFieldsReg_0_0_T; // @[SBA.scala:150:35, :160:{39,42}]
wire _SBDATAFieldsReg_0_0_T_2 = ~SBCSFieldsReg_sbbusyerror; // @[SBA.scala:47:28, :119:88, :160:67]
wire _SBDATAFieldsReg_0_0_T_3 = _SBDATAFieldsReg_0_0_T_1 & _SBDATAFieldsReg_0_0_T_2; // @[SBA.scala:160:{39,64,67}]
wire _SBDATAFieldsReg_0_0_T_5 = _SBDATAFieldsReg_0_0_T_3 & _SBDATAFieldsReg_0_0_T_4; // @[SBA.scala:160:{64,94,97}]
wire [7:0] _SBDATAFieldsReg_0_0_T_6 = SBDATAWrData_0[7:0]; // @[SBA.scala:147:35, :160:133]
wire [7:0] _SBDATAFieldsReg_0_0_T_7 = _sb2tlOpt_io_rdLoad_0 ? _sb2tlOpt_io_dataOut : SBDATAFieldsReg_0_0; // @[SBA.scala:143:30, :161:24]
wire [7:0] _SBDATAFieldsReg_0_0_T_8 = _SBDATAFieldsReg_0_0_T_5 ? _SBDATAFieldsReg_0_0_T_6 : _SBDATAFieldsReg_0_0_T_7; // @[SBA.scala:160:{24,94,133}, :161:24]
wire _SBDATAFieldsReg_0_1_T = ~SBCSFieldsReg_sbbusy; // @[SBA.scala:47:28, :119:63, :160:42]
wire _SBDATAFieldsReg_0_1_T_1 = SBDATAWrEn_0 & _SBDATAFieldsReg_0_1_T; // @[SBA.scala:150:35, :160:{39,42}]
wire _SBDATAFieldsReg_0_1_T_2 = ~SBCSFieldsReg_sbbusyerror; // @[SBA.scala:47:28, :119:88, :160:67]
wire _SBDATAFieldsReg_0_1_T_3 = _SBDATAFieldsReg_0_1_T_1 & _SBDATAFieldsReg_0_1_T_2; // @[SBA.scala:160:{39,64,67}]
wire _SBDATAFieldsReg_0_1_T_5 = _SBDATAFieldsReg_0_1_T_3 & _SBDATAFieldsReg_0_1_T_4; // @[SBA.scala:160:{64,94,97}]
wire [7:0] _SBDATAFieldsReg_0_1_T_6 = SBDATAWrData_0[15:8]; // @[SBA.scala:147:35, :160:133]
wire [7:0] _SBDATAFieldsReg_0_1_T_7 = _sb2tlOpt_io_rdLoad_1 ? _sb2tlOpt_io_dataOut : SBDATAFieldsReg_0_1; // @[SBA.scala:143:30, :161:24]
wire [7:0] _SBDATAFieldsReg_0_1_T_8 = _SBDATAFieldsReg_0_1_T_5 ? _SBDATAFieldsReg_0_1_T_6 : _SBDATAFieldsReg_0_1_T_7; // @[SBA.scala:160:{24,94,133}, :161:24]
wire _SBDATAFieldsReg_0_2_T = ~SBCSFieldsReg_sbbusy; // @[SBA.scala:47:28, :119:63, :160:42]
wire _SBDATAFieldsReg_0_2_T_1 = SBDATAWrEn_0 & _SBDATAFieldsReg_0_2_T; // @[SBA.scala:150:35, :160:{39,42}]
wire _SBDATAFieldsReg_0_2_T_2 = ~SBCSFieldsReg_sbbusyerror; // @[SBA.scala:47:28, :119:88, :160:67]
wire _SBDATAFieldsReg_0_2_T_3 = _SBDATAFieldsReg_0_2_T_1 & _SBDATAFieldsReg_0_2_T_2; // @[SBA.scala:160:{39,64,67}]
wire _SBDATAFieldsReg_0_2_T_5 = _SBDATAFieldsReg_0_2_T_3 & _SBDATAFieldsReg_0_2_T_4; // @[SBA.scala:160:{64,94,97}]
wire [7:0] _SBDATAFieldsReg_0_2_T_6 = SBDATAWrData_0[23:16]; // @[SBA.scala:147:35, :160:133]
wire [7:0] _SBDATAFieldsReg_0_2_T_7 = _sb2tlOpt_io_rdLoad_2 ? _sb2tlOpt_io_dataOut : SBDATAFieldsReg_0_2; // @[SBA.scala:143:30, :161:24]
wire [7:0] _SBDATAFieldsReg_0_2_T_8 = _SBDATAFieldsReg_0_2_T_5 ? _SBDATAFieldsReg_0_2_T_6 : _SBDATAFieldsReg_0_2_T_7; // @[SBA.scala:160:{24,94,133}, :161:24]
wire _SBDATAFieldsReg_0_3_T = ~SBCSFieldsReg_sbbusy; // @[SBA.scala:47:28, :119:63, :160:42]
wire _SBDATAFieldsReg_0_3_T_1 = SBDATAWrEn_0 & _SBDATAFieldsReg_0_3_T; // @[SBA.scala:150:35, :160:{39,42}]
wire _SBDATAFieldsReg_0_3_T_2 = ~SBCSFieldsReg_sbbusyerror; // @[SBA.scala:47:28, :119:88, :160:67]
wire _SBDATAFieldsReg_0_3_T_3 = _SBDATAFieldsReg_0_3_T_1 & _SBDATAFieldsReg_0_3_T_2; // @[SBA.scala:160:{39,64,67}]
wire _SBDATAFieldsReg_0_3_T_5 = _SBDATAFieldsReg_0_3_T_3 & _SBDATAFieldsReg_0_3_T_4; // @[SBA.scala:160:{64,94,97}]
wire [7:0] _SBDATAFieldsReg_0_3_T_6 = SBDATAWrData_0[31:24]; // @[SBA.scala:147:35, :160:133]
wire [7:0] _SBDATAFieldsReg_0_3_T_7 = _sb2tlOpt_io_rdLoad_3 ? _sb2tlOpt_io_dataOut : SBDATAFieldsReg_0_3; // @[SBA.scala:143:30, :161:24]
wire [7:0] _SBDATAFieldsReg_0_3_T_8 = _SBDATAFieldsReg_0_3_T_5 ? _SBDATAFieldsReg_0_3_T_6 : _SBDATAFieldsReg_0_3_T_7; // @[SBA.scala:160:{24,94,133}, :161:24]
wire [15:0] _GEN_3 = {SBDATAFieldsReg_0_1, SBDATAFieldsReg_0_0}; // @[SBA.scala:143:30, :165:31]
wire [15:0] SBDATARdData_0_lo; // @[SBA.scala:165:31]
assign SBDATARdData_0_lo = _GEN_3; // @[SBA.scala:165:31]
wire [15:0] sb2tlOpt_io_dataIn_lo_lo_lo; // @[SBA.scala:175:85]
assign sb2tlOpt_io_dataIn_lo_lo_lo = _GEN_3; // @[SBA.scala:165:31, :175:85]
wire [15:0] _GEN_4 = {SBDATAFieldsReg_0_3, SBDATAFieldsReg_0_2}; // @[SBA.scala:143:30, :165:31]
wire [15:0] SBDATARdData_0_hi; // @[SBA.scala:165:31]
assign SBDATARdData_0_hi = _GEN_4; // @[SBA.scala:165:31]
wire [15:0] sb2tlOpt_io_dataIn_lo_lo_hi; // @[SBA.scala:175:85]
assign sb2tlOpt_io_dataIn_lo_lo_hi = _GEN_4; // @[SBA.scala:165:31, :175:85]
assign _SBDATARdData_0_T = {SBDATARdData_0_hi, SBDATARdData_0_lo}; // @[SBA.scala:165:31]
assign SBDATARdData_0 = _SBDATARdData_0_T; // @[SBA.scala:145:35, :165:31]
wire _SBDATAFieldsReg_1_0_T = ~SBCSFieldsReg_sbbusy; // @[SBA.scala:47:28, :119:63, :160:42]
wire _SBDATAFieldsReg_1_0_T_1 = SBDATAWrEn_1 & _SBDATAFieldsReg_1_0_T; // @[SBA.scala:150:35, :160:{39,42}]
wire _SBDATAFieldsReg_1_0_T_2 = ~SBCSFieldsReg_sbbusyerror; // @[SBA.scala:47:28, :119:88, :160:67]
wire _SBDATAFieldsReg_1_0_T_3 = _SBDATAFieldsReg_1_0_T_1 & _SBDATAFieldsReg_1_0_T_2; // @[SBA.scala:160:{39,64,67}]
wire _SBDATAFieldsReg_1_0_T_5 = _SBDATAFieldsReg_1_0_T_3 & _SBDATAFieldsReg_1_0_T_4; // @[SBA.scala:160:{64,94,97}]
wire [7:0] _SBDATAFieldsReg_1_0_T_6 = SBDATAWrData_1[7:0]; // @[SBA.scala:147:35, :160:133]
wire [7:0] _SBDATAFieldsReg_1_0_T_7 = _sb2tlOpt_io_rdLoad_4 ? _sb2tlOpt_io_dataOut : SBDATAFieldsReg_1_0; // @[SBA.scala:143:30, :161:24]
wire [7:0] _SBDATAFieldsReg_1_0_T_8 = _SBDATAFieldsReg_1_0_T_5 ? _SBDATAFieldsReg_1_0_T_6 : _SBDATAFieldsReg_1_0_T_7; // @[SBA.scala:160:{24,94,133}, :161:24]
wire _SBDATAFieldsReg_1_1_T = ~SBCSFieldsReg_sbbusy; // @[SBA.scala:47:28, :119:63, :160:42]
wire _SBDATAFieldsReg_1_1_T_1 = SBDATAWrEn_1 & _SBDATAFieldsReg_1_1_T; // @[SBA.scala:150:35, :160:{39,42}]
wire _SBDATAFieldsReg_1_1_T_2 = ~SBCSFieldsReg_sbbusyerror; // @[SBA.scala:47:28, :119:88, :160:67]
wire _SBDATAFieldsReg_1_1_T_3 = _SBDATAFieldsReg_1_1_T_1 & _SBDATAFieldsReg_1_1_T_2; // @[SBA.scala:160:{39,64,67}]
wire _SBDATAFieldsReg_1_1_T_5 = _SBDATAFieldsReg_1_1_T_3 & _SBDATAFieldsReg_1_1_T_4; // @[SBA.scala:160:{64,94,97}]
wire [7:0] _SBDATAFieldsReg_1_1_T_6 = SBDATAWrData_1[15:8]; // @[SBA.scala:147:35, :160:133]
wire [7:0] _SBDATAFieldsReg_1_1_T_7 = _sb2tlOpt_io_rdLoad_5 ? _sb2tlOpt_io_dataOut : SBDATAFieldsReg_1_1; // @[SBA.scala:143:30, :161:24]
wire [7:0] _SBDATAFieldsReg_1_1_T_8 = _SBDATAFieldsReg_1_1_T_5 ? _SBDATAFieldsReg_1_1_T_6 : _SBDATAFieldsReg_1_1_T_7; // @[SBA.scala:160:{24,94,133}, :161:24]
wire _SBDATAFieldsReg_1_2_T = ~SBCSFieldsReg_sbbusy; // @[SBA.scala:47:28, :119:63, :160:42]
wire _SBDATAFieldsReg_1_2_T_1 = SBDATAWrEn_1 & _SBDATAFieldsReg_1_2_T; // @[SBA.scala:150:35, :160:{39,42}]
wire _SBDATAFieldsReg_1_2_T_2 = ~SBCSFieldsReg_sbbusyerror; // @[SBA.scala:47:28, :119:88, :160:67]
wire _SBDATAFieldsReg_1_2_T_3 = _SBDATAFieldsReg_1_2_T_1 & _SBDATAFieldsReg_1_2_T_2; // @[SBA.scala:160:{39,64,67}]
wire _SBDATAFieldsReg_1_2_T_5 = _SBDATAFieldsReg_1_2_T_3 & _SBDATAFieldsReg_1_2_T_4; // @[SBA.scala:160:{64,94,97}]
wire [7:0] _SBDATAFieldsReg_1_2_T_6 = SBDATAWrData_1[23:16]; // @[SBA.scala:147:35, :160:133]
wire [7:0] _SBDATAFieldsReg_1_2_T_7 = _sb2tlOpt_io_rdLoad_6 ? _sb2tlOpt_io_dataOut : SBDATAFieldsReg_1_2; // @[SBA.scala:143:30, :161:24]
wire [7:0] _SBDATAFieldsReg_1_2_T_8 = _SBDATAFieldsReg_1_2_T_5 ? _SBDATAFieldsReg_1_2_T_6 : _SBDATAFieldsReg_1_2_T_7; // @[SBA.scala:160:{24,94,133}, :161:24]
wire _SBDATAFieldsReg_1_3_T = ~SBCSFieldsReg_sbbusy; // @[SBA.scala:47:28, :119:63, :160:42]
wire _SBDATAFieldsReg_1_3_T_1 = SBDATAWrEn_1 & _SBDATAFieldsReg_1_3_T; // @[SBA.scala:150:35, :160:{39,42}]
wire _SBDATAFieldsReg_1_3_T_2 = ~SBCSFieldsReg_sbbusyerror; // @[SBA.scala:47:28, :119:88, :160:67]
wire _SBDATAFieldsReg_1_3_T_3 = _SBDATAFieldsReg_1_3_T_1 & _SBDATAFieldsReg_1_3_T_2; // @[SBA.scala:160:{39,64,67}]
wire _SBDATAFieldsReg_1_3_T_5 = _SBDATAFieldsReg_1_3_T_3 & _SBDATAFieldsReg_1_3_T_4; // @[SBA.scala:160:{64,94,97}]
wire [7:0] _SBDATAFieldsReg_1_3_T_6 = SBDATAWrData_1[31:24]; // @[SBA.scala:147:35, :160:133]
wire [7:0] _SBDATAFieldsReg_1_3_T_7 = _sb2tlOpt_io_rdLoad_7 ? _sb2tlOpt_io_dataOut : SBDATAFieldsReg_1_3; // @[SBA.scala:143:30, :161:24]
wire [7:0] _SBDATAFieldsReg_1_3_T_8 = _SBDATAFieldsReg_1_3_T_5 ? _SBDATAFieldsReg_1_3_T_6 : _SBDATAFieldsReg_1_3_T_7; // @[SBA.scala:160:{24,94,133}, :161:24]
wire [15:0] _GEN_5 = {SBDATAFieldsReg_1_1, SBDATAFieldsReg_1_0}; // @[SBA.scala:143:30, :165:31]
wire [15:0] SBDATARdData_1_lo; // @[SBA.scala:165:31]
assign SBDATARdData_1_lo = _GEN_5; // @[SBA.scala:165:31]
wire [15:0] sb2tlOpt_io_dataIn_lo_hi_lo; // @[SBA.scala:175:85]
assign sb2tlOpt_io_dataIn_lo_hi_lo = _GEN_5; // @[SBA.scala:165:31, :175:85]
wire [15:0] _GEN_6 = {SBDATAFieldsReg_1_3, SBDATAFieldsReg_1_2}; // @[SBA.scala:143:30, :165:31]
wire [15:0] SBDATARdData_1_hi; // @[SBA.scala:165:31]
assign SBDATARdData_1_hi = _GEN_6; // @[SBA.scala:165:31]
wire [15:0] sb2tlOpt_io_dataIn_lo_hi_hi; // @[SBA.scala:175:85]
assign sb2tlOpt_io_dataIn_lo_hi_hi = _GEN_6; // @[SBA.scala:165:31, :175:85]
assign _SBDATARdData_1_T = {SBDATARdData_1_hi, SBDATARdData_1_lo}; // @[SBA.scala:165:31]
assign SBDATARdData_1 = _SBDATARdData_1_T; // @[SBA.scala:145:35, :165:31]
wire [63:0] sb2tlOpt_io_dataIn_lo = {SBDATAWrData_1, SBDATAWrData_0}; // @[SBA.scala:147:35, :175:59]
wire [127:0] _sb2tlOpt_io_dataIn_T = {64'h0, sb2tlOpt_io_dataIn_lo}; // @[SBA.scala:175:59]
wire [31:0] sb2tlOpt_io_dataIn_lo_lo = {sb2tlOpt_io_dataIn_lo_lo_hi, sb2tlOpt_io_dataIn_lo_lo_lo}; // @[SBA.scala:175:85]
wire [31:0] sb2tlOpt_io_dataIn_lo_hi = {sb2tlOpt_io_dataIn_lo_hi_hi, sb2tlOpt_io_dataIn_lo_hi_lo}; // @[SBA.scala:175:85]
wire [63:0] sb2tlOpt_io_dataIn_lo_1 = {sb2tlOpt_io_dataIn_lo_hi, sb2tlOpt_io_dataIn_lo_lo}; // @[SBA.scala:175:85]
wire [127:0] _sb2tlOpt_io_dataIn_T_1 = {64'h0, sb2tlOpt_io_dataIn_lo_1}; // @[SBA.scala:175:85]
wire _sb2tlOpt_io_wrEn_T_10; // @[SBA.scala:199:156]
wire [127:0] _sb2tlOpt_io_dataIn_T_2 = _sb2tlOpt_io_wrEn_T_10 ? _sb2tlOpt_io_dataIn_T : _sb2tlOpt_io_dataIn_T_1; // @[SBA.scala:175:{34,59,85}, :199:156]
wire _anyDataRdEn_T = SBDATARdEn_0 | SBDATARdEn_1; // @[SBA.scala:149:35, :176:51]
wire _anyDataRdEn_T_1 = _anyDataRdEn_T; // @[SBA.scala:176:51]
assign _anyDataRdEn_T_2 = _anyDataRdEn_T_1; // @[SBA.scala:176:51]
assign anyDataRdEn = _anyDataRdEn_T_2; // @[SBA.scala:43:34, :176:51]
wire _anyDataWrEn_T = SBDATAWrEn_0 | SBDATAWrEn_1; // @[SBA.scala:150:35, :177:51]
wire _anyDataWrEn_T_1 = _anyDataWrEn_T; // @[SBA.scala:177:51]
assign _anyDataWrEn_T_2 = _anyDataWrEn_T_1; // @[SBA.scala:177:51]
assign anyDataWrEn = _anyDataWrEn_T_2; // @[SBA.scala:44:34, :177:51]
wire _tryRdEn_T = SBADDRESSWrEn_0 & SBCSFieldsReg_sbreadonaddr; // @[SBA.scala:47:28, :108:38, :180:37]
wire _tryRdEn_T_1 = SBDATARdEn_0 & SBCSFieldsReg_sbreadondata; // @[SBA.scala:47:28, :149:35, :180:86]
wire tryRdEn = _tryRdEn_T | _tryRdEn_T_1; // @[SBA.scala:180:{37,68,86}]
wire _sb2tlOpt_io_rdEn_T = tryRdEn; // @[SBA.scala:180:68, :200:49]
wire _sbAccessError_T = SBCSFieldsReg_sbaccess == 3'h0; // @[SBA.scala:47:28, :182:49]
wire _T_204 = SBCSFieldsReg_sbaccess == 3'h1; // @[SBA.scala:47:28, :183:49]
wire _sbAccessError_T_3; // @[SBA.scala:183:49]
assign _sbAccessError_T_3 = _T_204; // @[SBA.scala:183:49]
wire _sbAlignmentError_T; // @[SBA.scala:191:52]
assign _sbAlignmentError_T = _T_204; // @[SBA.scala:183:49, :191:52]
wire _T_211 = SBCSFieldsReg_sbaccess == 3'h2; // @[SBA.scala:47:28, :184:49]
wire _sbAccessError_T_7; // @[SBA.scala:184:49]
assign _sbAccessError_T_7 = _T_211; // @[SBA.scala:184:49]
wire _sbAlignmentError_T_4; // @[SBA.scala:192:52]
assign _sbAlignmentError_T_4 = _T_211; // @[SBA.scala:184:49, :192:52]
wire _T_218 = SBCSFieldsReg_sbaccess == 3'h3; // @[SBA.scala:47:28, :185:49]
wire _sbAccessError_T_11; // @[SBA.scala:185:49]
assign _sbAccessError_T_11 = _T_218; // @[SBA.scala:185:49]
wire _sbAlignmentError_T_9; // @[SBA.scala:193:52]
assign _sbAlignmentError_T_9 = _T_218; // @[SBA.scala:185:49, :193:52]
wire _T_225 = SBCSFieldsReg_sbaccess == 3'h4; // @[SBA.scala:47:28, :186:49]
wire _sbAccessError_T_15; // @[SBA.scala:186:49]
assign _sbAccessError_T_15 = _T_225; // @[SBA.scala:186:49]
wire _sbAlignmentError_T_14; // @[SBA.scala:194:52]
assign _sbAlignmentError_T_14 = _T_225; // @[SBA.scala:186:49, :194:52]
wire _sbAccessError_T_17 = _sbAccessError_T_15; // @[SBA.scala:186:{49,58}]
wire _sbAccessError_T_18 = _sbAccessError_T_17; // @[SBA.scala:185:97, :186:58]
wire _sbAccessError_T_19 = SBCSFieldsReg_sbaccess > 3'h4; // @[SBA.scala:47:28, :186:124]
wire sbAccessError = _sbAccessError_T_18 | _sbAccessError_T_19; // @[SBA.scala:185:97, :186:{97,124}]
wire [31:0] _compareAddr_T; // @[SBA.scala:189:23]
wire [31:0] compareAddr; // @[SBA.scala:188:27]
assign _compareAddr_T = SBADDRESSWrEn_0 ? SBADDRESSWrData_0 : SBADDRESSFieldsReg_0; // @[SBA.scala:104:33, :106:38, :108:38, :189:23]
assign compareAddr = _compareAddr_T; // @[SBA.scala:188:27, :189:23]
wire _sbAlignmentError_T_1 = compareAddr[0]; // @[SBA.scala:188:27, :191:76]
wire _sbAlignmentError_T_2 = _sbAlignmentError_T_1; // @[SBA.scala:191:{76,82}]
wire _sbAlignmentError_T_3 = _sbAlignmentError_T & _sbAlignmentError_T_2; // @[SBA.scala:191:{52,61,82}]
wire [1:0] _sbAlignmentError_T_5 = compareAddr[1:0]; // @[SBA.scala:188:27, :192:76]
wire _sbAlignmentError_T_6 = |_sbAlignmentError_T_5; // @[SBA.scala:192:{76,82}]
wire _sbAlignmentError_T_7 = _sbAlignmentError_T_4 & _sbAlignmentError_T_6; // @[SBA.scala:192:{52,61,82}]
wire _sbAlignmentError_T_8 = _sbAlignmentError_T_3 | _sbAlignmentError_T_7; // @[SBA.scala:191:{61,91}, :192:61]
wire [2:0] _sbAlignmentError_T_10 = compareAddr[2:0]; // @[SBA.scala:188:27, :193:76]
wire _sbAlignmentError_T_11 = |_sbAlignmentError_T_10; // @[SBA.scala:193:{76,82}]
wire _sbAlignmentError_T_12 = _sbAlignmentError_T_9 & _sbAlignmentError_T_11; // @[SBA.scala:193:{52,61,82}]
wire _sbAlignmentError_T_13 = _sbAlignmentError_T_8 | _sbAlignmentError_T_12; // @[SBA.scala:191:91, :192:91, :193:61]
wire [3:0] _sbAlignmentError_T_15 = compareAddr[3:0]; // @[SBA.scala:188:27, :194:76]
wire _sbAlignmentError_T_16 = |_sbAlignmentError_T_15; // @[SBA.scala:194:{76,82}]
wire _sbAlignmentError_T_17 = _sbAlignmentError_T_14 & _sbAlignmentError_T_16; // @[SBA.scala:194:{52,61,82}]
wire sbAlignmentError = _sbAlignmentError_T_13 | _sbAlignmentError_T_17; // @[SBA.scala:192:91, :193:91, :194:61]
wire _sb2tlOpt_io_wrEn_T_1 = ~SBCSFieldsReg_sbbusy; // @[SBA.scala:47:28, :119:63, :199:63]
wire _sb2tlOpt_io_wrEn_T_2 = _sb2tlOpt_io_wrEn_T & _sb2tlOpt_io_wrEn_T_1; // @[SBA.scala:199:{49,60,63}]
wire _sb2tlOpt_io_wrEn_T_3 = ~SBCSFieldsReg_sbbusyerror; // @[SBA.scala:47:28, :119:88, :199:88]
wire _sb2tlOpt_io_wrEn_T_4 = _sb2tlOpt_io_wrEn_T_2 & _sb2tlOpt_io_wrEn_T_3; // @[SBA.scala:199:{60,85,88}]
wire _sb2tlOpt_io_wrEn_T_6 = _sb2tlOpt_io_wrEn_T_4 & _sb2tlOpt_io_wrEn_T_5; // @[SBA.scala:199:{85,115,118}]
wire _sb2tlOpt_io_wrEn_T_7 = ~sbAccessError; // @[SBA.scala:186:97, :199:141]
wire _sb2tlOpt_io_wrEn_T_8 = _sb2tlOpt_io_wrEn_T_6 & _sb2tlOpt_io_wrEn_T_7; // @[SBA.scala:199:{115,138,141}]
wire _sb2tlOpt_io_wrEn_T_9 = ~sbAlignmentError; // @[SBA.scala:193:91, :199:159]
assign _sb2tlOpt_io_wrEn_T_10 = _sb2tlOpt_io_wrEn_T_8 & _sb2tlOpt_io_wrEn_T_9; // @[SBA.scala:199:{138,156,159}]
wire _sb2tlOpt_io_rdEn_T_1 = ~SBCSFieldsReg_sbbusy; // @[SBA.scala:47:28, :119:63, :200:63]
wire _sb2tlOpt_io_rdEn_T_2 = _sb2tlOpt_io_rdEn_T & _sb2tlOpt_io_rdEn_T_1; // @[SBA.scala:200:{49,60,63}]
wire _sb2tlOpt_io_rdEn_T_3 = ~SBCSFieldsReg_sbbusyerror; // @[SBA.scala:47:28, :119:88, :200:88]
wire _sb2tlOpt_io_rdEn_T_4 = _sb2tlOpt_io_rdEn_T_2 & _sb2tlOpt_io_rdEn_T_3; // @[SBA.scala:200:{60,85,88}]
wire _sb2tlOpt_io_rdEn_T_6 = _sb2tlOpt_io_rdEn_T_4 & _sb2tlOpt_io_rdEn_T_5; // @[SBA.scala:200:{85,115,118}]
wire _sb2tlOpt_io_rdEn_T_7 = ~sbAccessError; // @[SBA.scala:186:97, :199:141, :200:141]
wire _sb2tlOpt_io_rdEn_T_8 = _sb2tlOpt_io_rdEn_T_6 & _sb2tlOpt_io_rdEn_T_7; // @[SBA.scala:200:{115,138,141}]
wire _sb2tlOpt_io_rdEn_T_9 = ~sbAlignmentError; // @[SBA.scala:193:91, :199:159, :200:159]
wire _sb2tlOpt_io_rdEn_T_10 = _sb2tlOpt_io_rdEn_T_8 & _sb2tlOpt_io_rdEn_T_9; // @[SBA.scala:200:{138,156,159}]
assign sbBusy = |_sb2tlOpt_io_sbStateOut; // @[SBA.scala:51:67, :203:46]
assign SBCSRdData_sbbusy = sbBusy; // @[SBA.scala:60:38, :203:46]
wire _SBCSFieldsReg_sbbusyerror_T = sbbusyerrorWrEn & SBCSWrData_sbbusyerror; // @[SBA.scala:63:38, :70:38, :208:60]
wire _SBCSFieldsReg_sbbusyerror_T_1 = anyAddressWrEn & sbBusy; // @[SBA.scala:42:34, :203:46, :209:59]
wire _SBCSFieldsReg_sbbusyerror_T_2 = anyDataRdEn | anyDataWrEn; // @[SBA.scala:43:34, :44:34, :210:57]
wire _SBCSFieldsReg_sbbusyerror_T_3 = _SBCSFieldsReg_sbbusyerror_T_2 & sbBusy; // @[SBA.scala:203:46, :210:{57,73}]
wire _SBCSFieldsReg_sbbusyerror_T_4 = _SBCSFieldsReg_sbbusyerror_T_3 | SBCSFieldsReg_sbbusyerror; // @[SBA.scala:47:28, :210:{43,73}]
wire _SBCSFieldsReg_sbbusyerror_T_5 = _SBCSFieldsReg_sbbusyerror_T_1 | _SBCSFieldsReg_sbbusyerror_T_4; // @[SBA.scala:209:{43,59}, :210:43]
wire _SBCSFieldsReg_sbbusyerror_T_6 = ~_SBCSFieldsReg_sbbusyerror_T & _SBCSFieldsReg_sbbusyerror_T_5; // @[SBA.scala:208:{43,60}, :209:43]
wire _SBCSFieldsReg_sbreadonaddr_T = sbreadonaddrWrEn ? SBCSWrData_sbreadonaddr : SBCSFieldsReg_sbreadonaddr; // @[SBA.scala:47:28, :63:38, :69:38, :211:43]
wire _SBCSFieldsReg_sbautoincrement_T = sbautoincrementWrEn ? SBCSWrData_sbautoincrement : SBCSFieldsReg_sbautoincrement; // @[SBA.scala:47:28, :63:38, :67:38, :212:43]
wire _SBCSFieldsReg_sbreadondata_T = sbreadondataWrEn ? SBCSWrData_sbreadondata : SBCSFieldsReg_sbreadondata; // @[SBA.scala:47:28, :63:38, :66:38, :213:43]
wire [2:0] _SBCSFieldsReg_sbaccess_T = sbaccessWrEn ? SBCSWrData_sbaccess : SBCSFieldsReg_sbaccess; // @[SBA.scala:47:28, :63:38, :68:38, :214:43]
reg sbErrorReg_0; // @[SBA.scala:219:25]
reg sbErrorReg_1; // @[SBA.scala:219:25]
reg sbErrorReg_2; // @[SBA.scala:219:25]
wire _sbErrorReg_0_T = SBCSWrData_sberror[0]; // @[SBA.scala:63:38, :225:63]
wire _sbErrorReg_0_T_1 = _sbErrorReg_0_T; // @[SBA.scala:225:{63,67}]
wire _sbErrorReg_0_T_2 = sberrorWrEn & _sbErrorReg_0_T_1; // @[SBA.scala:65:38, :225:{42,67}]
wire _sbErrorReg_0_T_3 = ~_sb2tlOpt_io_wrLegal; // @[SBA.scala:226:55]
wire _sbErrorReg_0_T_4 = _sb2tlOpt_io_wrEn_T_10 & _sbErrorReg_0_T_3; // @[SBA.scala:199:156, :226:{52,55}]
wire _sbErrorReg_0_T_5 = ~_sb2tlOpt_io_rdLegal; // @[SBA.scala:226:109]
wire _sbErrorReg_0_T_6 = _sb2tlOpt_io_rdEn_T_10 & _sbErrorReg_0_T_5; // @[SBA.scala:200:156, :226:{106,109}]
wire _sbErrorReg_0_T_7 = _sbErrorReg_0_T_4 | _sbErrorReg_0_T_6; // @[SBA.scala:226:{52,81,106}]
wire _GEN_7 = SBDATAWrEn_0 | tryRdEn; // @[SBA.scala:150:35, :180:68, :227:39]
wire _sbErrorReg_0_T_8; // @[SBA.scala:227:39]
assign _sbErrorReg_0_T_8 = _GEN_7; // @[SBA.scala:227:39]
wire _sbErrorReg_0_T_10; // @[SBA.scala:228:39]
assign _sbErrorReg_0_T_10 = _GEN_7; // @[SBA.scala:227:39, :228:39]
wire _sbErrorReg_1_T_8; // @[SBA.scala:227:39]
assign _sbErrorReg_1_T_8 = _GEN_7; // @[SBA.scala:227:39]
wire _sbErrorReg_1_T_10; // @[SBA.scala:228:39]
assign _sbErrorReg_1_T_10 = _GEN_7; // @[SBA.scala:227:39, :228:39]
wire _sbErrorReg_2_T_8; // @[SBA.scala:227:39]
assign _sbErrorReg_2_T_8 = _GEN_7; // @[SBA.scala:227:39]
wire _sbErrorReg_2_T_10; // @[SBA.scala:228:39]
assign _sbErrorReg_2_T_10 = _GEN_7; // @[SBA.scala:227:39, :228:39]
wire _sbErrorReg_0_T_9 = _sbErrorReg_0_T_8 & sbAlignmentError; // @[SBA.scala:193:91, :227:{39,51}]
wire _sbErrorReg_0_T_11 = _sbErrorReg_0_T_10 & sbAccessError; // @[SBA.scala:186:97, :228:{39,51}]
wire _sbErrorReg_0_T_13 = _sbErrorReg_0_T_12 & _sb2tlOpt_io_respError; // @[SBA.scala:229:{54,81}]
wire _sbErrorReg_0_T_14 = _sbErrorReg_0_T_13 | sbErrorReg_0; // @[SBA.scala:219:25, :229:{29,81}]
wire _sbErrorReg_0_T_15 = ~_sbErrorReg_0_T_11 & _sbErrorReg_0_T_14; // @[SBA.scala:228:{29,51}, :229:29]
wire _sbErrorReg_0_T_16 = _sbErrorReg_0_T_9 | _sbErrorReg_0_T_15; // @[SBA.scala:227:{29,51}, :228:29]
wire _sbErrorReg_0_T_17 = ~_sbErrorReg_0_T_7 & _sbErrorReg_0_T_16; // @[SBA.scala:226:{29,81}, :227:29]
wire _sbErrorReg_0_T_18 = ~_sbErrorReg_0_T_2 & _sbErrorReg_0_T_17; // @[SBA.scala:225:{29,42}, :226:29]
wire _sbErrorReg_1_T = SBCSWrData_sberror[1]; // @[SBA.scala:63:38, :225:63]
wire _sbErrorReg_1_T_1 = _sbErrorReg_1_T; // @[SBA.scala:225:{63,67}]
wire _sbErrorReg_1_T_2 = sberrorWrEn & _sbErrorReg_1_T_1; // @[SBA.scala:65:38, :225:{42,67}]
wire _sbErrorReg_1_T_3 = ~_sb2tlOpt_io_wrLegal; // @[SBA.scala:226:55]
wire _sbErrorReg_1_T_4 = _sb2tlOpt_io_wrEn_T_10 & _sbErrorReg_1_T_3; // @[SBA.scala:199:156, :226:{52,55}]
wire _sbErrorReg_1_T_5 = ~_sb2tlOpt_io_rdLegal; // @[SBA.scala:226:109]
wire _sbErrorReg_1_T_6 = _sb2tlOpt_io_rdEn_T_10 & _sbErrorReg_1_T_5; // @[SBA.scala:200:156, :226:{106,109}]
wire _sbErrorReg_1_T_7 = _sbErrorReg_1_T_4 | _sbErrorReg_1_T_6; // @[SBA.scala:226:{52,81,106}]
wire _sbErrorReg_1_T_9 = _sbErrorReg_1_T_8 & sbAlignmentError; // @[SBA.scala:193:91, :227:{39,51}]
wire _sbErrorReg_1_T_11 = _sbErrorReg_1_T_10 & sbAccessError; // @[SBA.scala:186:97, :228:{39,51}]
wire _sbErrorReg_1_T_13 = _sbErrorReg_1_T_12 & _sb2tlOpt_io_respError; // @[SBA.scala:229:{54,81}]
wire _sbErrorReg_1_T_14 = _sbErrorReg_1_T_13 | sbErrorReg_1; // @[SBA.scala:219:25, :229:{29,81}]
wire _sbErrorReg_1_T_15 = ~_sbErrorReg_1_T_11 & _sbErrorReg_1_T_14; // @[SBA.scala:228:{29,51}, :229:29]
wire _sbErrorReg_1_T_16 = _sbErrorReg_1_T_9 | _sbErrorReg_1_T_15; // @[SBA.scala:227:{29,51}, :228:29]
wire _sbErrorReg_1_T_17 = _sbErrorReg_1_T_7 | _sbErrorReg_1_T_16; // @[SBA.scala:226:{29,81}, :227:29]
wire _sbErrorReg_1_T_18 = ~_sbErrorReg_1_T_2 & _sbErrorReg_1_T_17; // @[SBA.scala:225:{29,42}, :226:29]
wire _sbErrorReg_2_T = SBCSWrData_sberror[2]; // @[SBA.scala:63:38, :225:63]
wire _sbErrorReg_2_T_1 = _sbErrorReg_2_T; // @[SBA.scala:225:{63,67}]
wire _sbErrorReg_2_T_2 = sberrorWrEn & _sbErrorReg_2_T_1; // @[SBA.scala:65:38, :225:{42,67}]
wire _sbErrorReg_2_T_3 = ~_sb2tlOpt_io_wrLegal; // @[SBA.scala:226:55]
wire _sbErrorReg_2_T_4 = _sb2tlOpt_io_wrEn_T_10 & _sbErrorReg_2_T_3; // @[SBA.scala:199:156, :226:{52,55}]
wire _sbErrorReg_2_T_5 = ~_sb2tlOpt_io_rdLegal; // @[SBA.scala:226:109]
wire _sbErrorReg_2_T_6 = _sb2tlOpt_io_rdEn_T_10 & _sbErrorReg_2_T_5; // @[SBA.scala:200:156, :226:{106,109}]
wire _sbErrorReg_2_T_7 = _sbErrorReg_2_T_4 | _sbErrorReg_2_T_6; // @[SBA.scala:226:{52,81,106}]
wire _sbErrorReg_2_T_9 = _sbErrorReg_2_T_8 & sbAlignmentError; // @[SBA.scala:193:91, :227:{39,51}]
wire _sbErrorReg_2_T_11 = _sbErrorReg_2_T_10 & sbAccessError; // @[SBA.scala:186:97, :228:{39,51}]
wire _sbErrorReg_2_T_13 = _sbErrorReg_2_T_12 & _sb2tlOpt_io_respError; // @[SBA.scala:229:{54,81}]
wire _sbErrorReg_2_T_14 = _sbErrorReg_2_T_13 | sbErrorReg_2; // @[SBA.scala:219:25, :229:{29,81}]
wire _sbErrorReg_2_T_15 = _sbErrorReg_2_T_11 | _sbErrorReg_2_T_14; // @[SBA.scala:228:{29,51}, :229:29]
wire _sbErrorReg_2_T_16 = ~_sbErrorReg_2_T_9 & _sbErrorReg_2_T_15; // @[SBA.scala:227:{29,51}, :228:29]
wire _sbErrorReg_2_T_17 = ~_sbErrorReg_2_T_7 & _sbErrorReg_2_T_16; // @[SBA.scala:226:{29,81}, :227:29]
wire _sbErrorReg_2_T_18 = ~_sbErrorReg_2_T_2 & _sbErrorReg_2_T_17; // @[SBA.scala:225:{29,42}, :226:29]
wire [1:0] SBCSRdData_sberror_lo = {sbErrorReg_1, sbErrorReg_0}; // @[SBA.scala:219:25, :240:42]
wire [1:0] SBCSRdData_sberror_hi = {1'h0, sbErrorReg_2}; // @[SBA.scala:219:25, :240:42]
wire [3:0] _SBCSRdData_sberror_T = {SBCSRdData_sberror_hi, SBCSRdData_sberror_lo}; // @[SBA.scala:240:42]
assign SBCSRdData_sberror = _SBCSRdData_sberror_T[2:0]; // @[SBA.scala:60:38, :240:{28,42}]
wire [31:0] _T_237 = {COMMANDReg_cmdtype, COMMANDReg_control}; // @[Debug.scala:1277:25, :1435:40]
wire [31:0] _out_T_1545; // @[RegisterRouter.scala:87:24]
assign _out_T_1545 = _T_237; // @[RegisterRouter.scala:87:24]
wire _out_in_ready_T; // @[RegisterRouter.scala:87:24]
wire [31:0] _accessRegisterCommandReg_T; // @[Debug.scala:1533:56]
assign _accessRegisterCommandReg_T = _T_237; // @[Debug.scala:1435:40, :1533:56]
assign dmiNodeIn_a_ready = in_ready; // @[RegisterRouter.scala:73:18]
wire _in_bits_read_T; // @[RegisterRouter.scala:74:36]
wire _out_front_valid_T = in_valid; // @[RegisterRouter.scala:73:18, :87:24]
wire [6:0] _in_bits_index_T; // @[Edges.scala:192:34]
wire out_front_bits_read = in_bits_read; // @[RegisterRouter.scala:73:18, :87:24]
wire [6:0] out_front_bits_index = in_bits_index; // @[RegisterRouter.scala:73:18, :87:24]
wire [31:0] out_front_bits_data = in_bits_data; // @[RegisterRouter.scala:73:18, :87:24]
wire [3:0] out_front_bits_mask = in_bits_mask; // @[RegisterRouter.scala:73:18, :87:24]
wire out_front_bits_extra_tlrr_extra_source = in_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:73:18, :87:24]
wire [1:0] out_front_bits_extra_tlrr_extra_size = in_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:73:18, :87:24]
assign _in_bits_read_T = dmiNodeIn_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36]
assign in_bits_read = _in_bits_read_T; // @[RegisterRouter.scala:73:18, :74:36]
assign _in_bits_index_T = dmiNodeIn_a_bits_address[8:2]; // @[Edges.scala:192:34]
assign in_bits_index = _in_bits_index_T; // @[RegisterRouter.scala:73:18]
wire _out_front_ready_T = out_ready; // @[RegisterRouter.scala:87:24]
wire _out_out_valid_T; // @[RegisterRouter.scala:87:24]
assign dmiNodeIn_d_valid = out_valid; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24]
wire _dmiNodeIn_d_bits_opcode_T = out_bits_read; // @[RegisterRouter.scala:87:24, :105:25]
assign dmiNodeIn_d_bits_data = out_bits_data; // @[RegisterRouter.scala:87:24]
assign dmiNodeIn_d_bits_d_source = out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24]
wire [1:0] out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24]
assign dmiNodeIn_d_bits_d_size = out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24]
assign _out_in_ready_T = out_front_ready; // @[RegisterRouter.scala:87:24]
assign _out_out_valid_T = out_front_valid; // @[RegisterRouter.scala:87:24]
assign out_bits_read = out_front_bits_read; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_112 = out_front_bits_data; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_741 = out_front_bits_data; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_796 = out_front_bits_data; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_939 = out_front_bits_data; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_1536 = out_front_bits_data; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_1591 = out_front_bits_data; // @[RegisterRouter.scala:87:24]
assign out_bits_extra_tlrr_extra_source = out_front_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24]
assign out_bits_extra_tlrr_extra_size = out_front_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24]
wire [6:0] _GEN_8 = out_front_bits_index & 7'h40; // @[RegisterRouter.scala:87:24]
wire [6:0] out_findex; // @[RegisterRouter.scala:87:24]
assign out_findex = _GEN_8; // @[RegisterRouter.scala:87:24]
wire [6:0] out_bindex; // @[RegisterRouter.scala:87:24]
assign out_bindex = _GEN_8; // @[RegisterRouter.scala:87:24]
wire _GEN_9 = out_findex == 7'h0; // @[RegisterRouter.scala:87:24]
wire _out_T; // @[RegisterRouter.scala:87:24]
assign _out_T = _GEN_9; // @[RegisterRouter.scala:87:24]
wire _out_T_2; // @[RegisterRouter.scala:87:24]
assign _out_T_2 = _GEN_9; // @[RegisterRouter.scala:87:24]
wire _out_T_4; // @[RegisterRouter.scala:87:24]
assign _out_T_4 = _GEN_9; // @[RegisterRouter.scala:87:24]
wire _out_T_6; // @[RegisterRouter.scala:87:24]
assign _out_T_6 = _GEN_9; // @[RegisterRouter.scala:87:24]
wire _out_T_8; // @[RegisterRouter.scala:87:24]
assign _out_T_8 = _GEN_9; // @[RegisterRouter.scala:87:24]
wire _out_T_10; // @[RegisterRouter.scala:87:24]
assign _out_T_10 = _GEN_9; // @[RegisterRouter.scala:87:24]
wire _out_T_12; // @[RegisterRouter.scala:87:24]
assign _out_T_12 = _GEN_9; // @[RegisterRouter.scala:87:24]
wire _out_T_14; // @[RegisterRouter.scala:87:24]
assign _out_T_14 = _GEN_9; // @[RegisterRouter.scala:87:24]
wire _out_T_16; // @[RegisterRouter.scala:87:24]
assign _out_T_16 = _GEN_9; // @[RegisterRouter.scala:87:24]
wire _out_T_18; // @[RegisterRouter.scala:87:24]
assign _out_T_18 = _GEN_9; // @[RegisterRouter.scala:87:24]
wire _out_T_20; // @[RegisterRouter.scala:87:24]
assign _out_T_20 = _GEN_9; // @[RegisterRouter.scala:87:24]
wire _out_T_22; // @[RegisterRouter.scala:87:24]
assign _out_T_22 = _GEN_9; // @[RegisterRouter.scala:87:24]
wire _out_T_24; // @[RegisterRouter.scala:87:24]
assign _out_T_24 = _GEN_9; // @[RegisterRouter.scala:87:24]
wire _out_T_26; // @[RegisterRouter.scala:87:24]
assign _out_T_26 = _GEN_9; // @[RegisterRouter.scala:87:24]
wire _out_T_28; // @[RegisterRouter.scala:87:24]
assign _out_T_28 = _GEN_9; // @[RegisterRouter.scala:87:24]
wire _out_T_30; // @[RegisterRouter.scala:87:24]
assign _out_T_30 = _GEN_9; // @[RegisterRouter.scala:87:24]
wire _out_T_32; // @[RegisterRouter.scala:87:24]
assign _out_T_32 = _GEN_9; // @[RegisterRouter.scala:87:24]
wire _out_T_34; // @[RegisterRouter.scala:87:24]
assign _out_T_34 = _GEN_9; // @[RegisterRouter.scala:87:24]
wire _out_T_36; // @[RegisterRouter.scala:87:24]
assign _out_T_36 = _GEN_9; // @[RegisterRouter.scala:87:24]
wire _out_T_38; // @[RegisterRouter.scala:87:24]
assign _out_T_38 = _GEN_9; // @[RegisterRouter.scala:87:24]
wire _out_T_42; // @[RegisterRouter.scala:87:24]
assign _out_T_42 = _GEN_9; // @[RegisterRouter.scala:87:24]
wire _out_T_44; // @[RegisterRouter.scala:87:24]
assign _out_T_44 = _GEN_9; // @[RegisterRouter.scala:87:24]
wire _out_T_46; // @[RegisterRouter.scala:87:24]
assign _out_T_46 = _GEN_9; // @[RegisterRouter.scala:87:24]
wire _out_T_48; // @[RegisterRouter.scala:87:24]
assign _out_T_48 = _GEN_9; // @[RegisterRouter.scala:87:24]
wire _out_T_50; // @[RegisterRouter.scala:87:24]
assign _out_T_50 = _GEN_9; // @[RegisterRouter.scala:87:24]
wire _out_T_52; // @[RegisterRouter.scala:87:24]
assign _out_T_52 = _GEN_9; // @[RegisterRouter.scala:87:24]
wire _out_T_54; // @[RegisterRouter.scala:87:24]
assign _out_T_54 = _GEN_9; // @[RegisterRouter.scala:87:24]
wire _out_T_56; // @[RegisterRouter.scala:87:24]
assign _out_T_56 = _GEN_9; // @[RegisterRouter.scala:87:24]
wire _out_T_58; // @[RegisterRouter.scala:87:24]
assign _out_T_58 = _GEN_9; // @[RegisterRouter.scala:87:24]
wire _out_T_60; // @[RegisterRouter.scala:87:24]
assign _out_T_60 = _GEN_9; // @[RegisterRouter.scala:87:24]
wire _out_T_62; // @[RegisterRouter.scala:87:24]
assign _out_T_62 = _GEN_9; // @[RegisterRouter.scala:87:24]
wire _out_T_64; // @[RegisterRouter.scala:87:24]
assign _out_T_64 = _GEN_9; // @[RegisterRouter.scala:87:24]
wire _out_T_66; // @[RegisterRouter.scala:87:24]
assign _out_T_66 = _GEN_9; // @[RegisterRouter.scala:87:24]
wire _GEN_10 = out_bindex == 7'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_1; // @[RegisterRouter.scala:87:24]
assign _out_T_1 = _GEN_10; // @[RegisterRouter.scala:87:24]
wire _out_T_3; // @[RegisterRouter.scala:87:24]
assign _out_T_3 = _GEN_10; // @[RegisterRouter.scala:87:24]
wire _out_T_5; // @[RegisterRouter.scala:87:24]
assign _out_T_5 = _GEN_10; // @[RegisterRouter.scala:87:24]
wire _out_T_7; // @[RegisterRouter.scala:87:24]
assign _out_T_7 = _GEN_10; // @[RegisterRouter.scala:87:24]
wire _out_T_9; // @[RegisterRouter.scala:87:24]
assign _out_T_9 = _GEN_10; // @[RegisterRouter.scala:87:24]
wire _out_T_11; // @[RegisterRouter.scala:87:24]
assign _out_T_11 = _GEN_10; // @[RegisterRouter.scala:87:24]
wire _out_T_13; // @[RegisterRouter.scala:87:24]
assign _out_T_13 = _GEN_10; // @[RegisterRouter.scala:87:24]
wire _out_T_15; // @[RegisterRouter.scala:87:24]
assign _out_T_15 = _GEN_10; // @[RegisterRouter.scala:87:24]
wire _out_T_17; // @[RegisterRouter.scala:87:24]
assign _out_T_17 = _GEN_10; // @[RegisterRouter.scala:87:24]
wire _out_T_19; // @[RegisterRouter.scala:87:24]
assign _out_T_19 = _GEN_10; // @[RegisterRouter.scala:87:24]
wire _out_T_21; // @[RegisterRouter.scala:87:24]
assign _out_T_21 = _GEN_10; // @[RegisterRouter.scala:87:24]
wire _out_T_23; // @[RegisterRouter.scala:87:24]
assign _out_T_23 = _GEN_10; // @[RegisterRouter.scala:87:24]
wire _out_T_25; // @[RegisterRouter.scala:87:24]
assign _out_T_25 = _GEN_10; // @[RegisterRouter.scala:87:24]
wire _out_T_27; // @[RegisterRouter.scala:87:24]
assign _out_T_27 = _GEN_10; // @[RegisterRouter.scala:87:24]
wire _out_T_29; // @[RegisterRouter.scala:87:24]
assign _out_T_29 = _GEN_10; // @[RegisterRouter.scala:87:24]
wire _out_T_31; // @[RegisterRouter.scala:87:24]
assign _out_T_31 = _GEN_10; // @[RegisterRouter.scala:87:24]
wire _out_T_33; // @[RegisterRouter.scala:87:24]
assign _out_T_33 = _GEN_10; // @[RegisterRouter.scala:87:24]
wire _out_T_35; // @[RegisterRouter.scala:87:24]
assign _out_T_35 = _GEN_10; // @[RegisterRouter.scala:87:24]
wire _out_T_37; // @[RegisterRouter.scala:87:24]
assign _out_T_37 = _GEN_10; // @[RegisterRouter.scala:87:24]
wire _out_T_39; // @[RegisterRouter.scala:87:24]
assign _out_T_39 = _GEN_10; // @[RegisterRouter.scala:87:24]
wire _out_T_43; // @[RegisterRouter.scala:87:24]
assign _out_T_43 = _GEN_10; // @[RegisterRouter.scala:87:24]
wire _out_T_45; // @[RegisterRouter.scala:87:24]
assign _out_T_45 = _GEN_10; // @[RegisterRouter.scala:87:24]
wire _out_T_47; // @[RegisterRouter.scala:87:24]
assign _out_T_47 = _GEN_10; // @[RegisterRouter.scala:87:24]
wire _out_T_49; // @[RegisterRouter.scala:87:24]
assign _out_T_49 = _GEN_10; // @[RegisterRouter.scala:87:24]
wire _out_T_51; // @[RegisterRouter.scala:87:24]
assign _out_T_51 = _GEN_10; // @[RegisterRouter.scala:87:24]
wire _out_T_53; // @[RegisterRouter.scala:87:24]
assign _out_T_53 = _GEN_10; // @[RegisterRouter.scala:87:24]
wire _out_T_55; // @[RegisterRouter.scala:87:24]
assign _out_T_55 = _GEN_10; // @[RegisterRouter.scala:87:24]
wire _out_T_57; // @[RegisterRouter.scala:87:24]
assign _out_T_57 = _GEN_10; // @[RegisterRouter.scala:87:24]
wire _out_T_59; // @[RegisterRouter.scala:87:24]
assign _out_T_59 = _GEN_10; // @[RegisterRouter.scala:87:24]
wire _out_T_61; // @[RegisterRouter.scala:87:24]
assign _out_T_61 = _GEN_10; // @[RegisterRouter.scala:87:24]
wire _out_T_63; // @[RegisterRouter.scala:87:24]
assign _out_T_63 = _GEN_10; // @[RegisterRouter.scala:87:24]
wire _out_T_65; // @[RegisterRouter.scala:87:24]
assign _out_T_65 = _GEN_10; // @[RegisterRouter.scala:87:24]
wire _out_T_67; // @[RegisterRouter.scala:87:24]
assign _out_T_67 = _GEN_10; // @[RegisterRouter.scala:87:24]
wire _out_out_bits_data_WIRE_5 = _out_T_1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_61 = _out_T_3; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_9 = _out_T_5; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_41 = _out_T_7; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_35 = _out_T_9; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_8 = _out_T_11; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_4 = _out_T_13; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_47 = _out_T_15; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_10 = _out_T_17; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_56 = _out_T_19; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_42 = _out_T_21; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_24 = _out_T_23; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_37 = _out_T_25; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_46 = _out_T_27; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_57 = _out_T_29; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_6 = _out_T_31; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_60 = _out_T_33; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_38 = _out_T_35; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_33 = _out_T_37; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_45 = _out_T_39; // @[MuxLiteral.scala:49:48]
wire _out_T_40 = out_findex == 7'h40; // @[RegisterRouter.scala:87:24]
wire _out_T_41 = out_bindex == 7'h40; // @[RegisterRouter.scala:87:24]
wire _out_out_bits_data_WIRE_0 = _out_T_41; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_17 = _out_T_43; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_32 = _out_T_45; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_34 = _out_T_47; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_22 = _out_T_49; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_44 = _out_T_51; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_7 = _out_T_53; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_39 = _out_T_55; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_11 = _out_T_57; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_43 = _out_T_59; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_40 = _out_T_61; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_23 = _out_T_63; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_36 = _out_T_65; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_T_23; // @[RegisterRouter.scala:87:24]
wire _out_out_bits_data_WIRE_19 = _out_T_67; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_T_247; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_39; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_167; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_143; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_35; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_19; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_191; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_43; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_171; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_99; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_151; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_187; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_231; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_27; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_243; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_155; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_135; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_183; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_131; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_139; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_91; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_179; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_31; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_159; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_47; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_175; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_163; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_95; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_147; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_79; // @[RegisterRouter.scala:87:24]
wire out_rivalid_0; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1; // @[RegisterRouter.scala:87:24]
wire out_rivalid_2; // @[RegisterRouter.scala:87:24]
wire out_rivalid_3; // @[RegisterRouter.scala:87:24]
wire out_rivalid_4; // @[RegisterRouter.scala:87:24]
wire out_rivalid_5; // @[RegisterRouter.scala:87:24]
wire out_rivalid_6; // @[RegisterRouter.scala:87:24]
wire out_rivalid_7; // @[RegisterRouter.scala:87:24]
wire out_rivalid_8; // @[RegisterRouter.scala:87:24]
wire out_rivalid_9; // @[RegisterRouter.scala:87:24]
wire out_rivalid_10; // @[RegisterRouter.scala:87:24]
wire out_rivalid_11; // @[RegisterRouter.scala:87:24]
wire out_rivalid_12; // @[RegisterRouter.scala:87:24]
wire out_rivalid_13; // @[RegisterRouter.scala:87:24]
wire out_rivalid_14; // @[RegisterRouter.scala:87:24]
wire out_rivalid_15; // @[RegisterRouter.scala:87:24]
wire out_rivalid_16; // @[RegisterRouter.scala:87:24]
wire out_rivalid_17; // @[RegisterRouter.scala:87:24]
wire out_rivalid_18; // @[RegisterRouter.scala:87:24]
wire out_rivalid_19; // @[RegisterRouter.scala:87:24]
wire out_rivalid_20; // @[RegisterRouter.scala:87:24]
wire out_rivalid_21; // @[RegisterRouter.scala:87:24]
wire out_rivalid_22; // @[RegisterRouter.scala:87:24]
wire out_rivalid_23; // @[RegisterRouter.scala:87:24]
wire out_rivalid_24; // @[RegisterRouter.scala:87:24]
wire out_rivalid_25; // @[RegisterRouter.scala:87:24]
wire out_rivalid_26; // @[RegisterRouter.scala:87:24]
wire out_rivalid_27; // @[RegisterRouter.scala:87:24]
wire out_rivalid_28; // @[RegisterRouter.scala:87:24]
wire out_rivalid_29; // @[RegisterRouter.scala:87:24]
wire out_rivalid_30; // @[RegisterRouter.scala:87:24]
wire out_rivalid_31; // @[RegisterRouter.scala:87:24]
wire out_rivalid_32; // @[RegisterRouter.scala:87:24]
wire out_rivalid_33; // @[RegisterRouter.scala:87:24]
wire out_rivalid_34; // @[RegisterRouter.scala:87:24]
wire out_rivalid_35; // @[RegisterRouter.scala:87:24]
wire out_rivalid_36; // @[RegisterRouter.scala:87:24]
wire out_rivalid_37; // @[RegisterRouter.scala:87:24]
wire out_rivalid_38; // @[RegisterRouter.scala:87:24]
wire out_rivalid_39; // @[RegisterRouter.scala:87:24]
wire out_rivalid_40; // @[RegisterRouter.scala:87:24]
wire out_rivalid_41; // @[RegisterRouter.scala:87:24]
wire out_rivalid_42; // @[RegisterRouter.scala:87:24]
wire out_rivalid_43; // @[RegisterRouter.scala:87:24]
wire out_rivalid_44; // @[RegisterRouter.scala:87:24]
wire out_rivalid_45; // @[RegisterRouter.scala:87:24]
wire out_rivalid_46; // @[RegisterRouter.scala:87:24]
wire out_rivalid_47; // @[RegisterRouter.scala:87:24]
wire out_rivalid_48; // @[RegisterRouter.scala:87:24]
wire out_rivalid_49; // @[RegisterRouter.scala:87:24]
wire out_rivalid_50; // @[RegisterRouter.scala:87:24]
wire out_rivalid_51; // @[RegisterRouter.scala:87:24]
wire out_rivalid_52; // @[RegisterRouter.scala:87:24]
wire out_rivalid_53; // @[RegisterRouter.scala:87:24]
wire out_rivalid_54; // @[RegisterRouter.scala:87:24]
wire out_rivalid_55; // @[RegisterRouter.scala:87:24]
wire out_rivalid_56; // @[RegisterRouter.scala:87:24]
wire out_rivalid_57; // @[RegisterRouter.scala:87:24]
wire out_rivalid_58; // @[RegisterRouter.scala:87:24]
wire out_rivalid_59; // @[RegisterRouter.scala:87:24]
wire out_rivalid_60; // @[RegisterRouter.scala:87:24]
wire out_rivalid_61; // @[RegisterRouter.scala:87:24]
wire out_rivalid_62; // @[RegisterRouter.scala:87:24]
wire out_rivalid_63; // @[RegisterRouter.scala:87:24]
wire out_rivalid_64; // @[RegisterRouter.scala:87:24]
wire out_rivalid_65; // @[RegisterRouter.scala:87:24]
wire out_rivalid_66; // @[RegisterRouter.scala:87:24]
wire out_rivalid_67; // @[RegisterRouter.scala:87:24]
wire out_rivalid_68; // @[RegisterRouter.scala:87:24]
wire out_rivalid_69; // @[RegisterRouter.scala:87:24]
wire out_rivalid_70; // @[RegisterRouter.scala:87:24]
wire out_rivalid_71; // @[RegisterRouter.scala:87:24]
wire out_rivalid_72; // @[RegisterRouter.scala:87:24]
wire out_rivalid_73; // @[RegisterRouter.scala:87:24]
wire out_rivalid_74; // @[RegisterRouter.scala:87:24]
wire out_rivalid_75; // @[RegisterRouter.scala:87:24]
wire out_rivalid_76; // @[RegisterRouter.scala:87:24]
wire out_rivalid_77; // @[RegisterRouter.scala:87:24]
wire out_rivalid_78; // @[RegisterRouter.scala:87:24]
wire out_rivalid_79; // @[RegisterRouter.scala:87:24]
wire out_rivalid_80; // @[RegisterRouter.scala:87:24]
wire out_rivalid_81; // @[RegisterRouter.scala:87:24]
wire out_rivalid_82; // @[RegisterRouter.scala:87:24]
wire out_rivalid_83; // @[RegisterRouter.scala:87:24]
wire out_rivalid_84; // @[RegisterRouter.scala:87:24]
wire out_rivalid_85; // @[RegisterRouter.scala:87:24]
wire out_rivalid_86; // @[RegisterRouter.scala:87:24]
wire out_rivalid_87; // @[RegisterRouter.scala:87:24]
wire out_rivalid_88; // @[RegisterRouter.scala:87:24]
wire out_rivalid_89; // @[RegisterRouter.scala:87:24]
wire out_rivalid_90; // @[RegisterRouter.scala:87:24]
wire out_rivalid_91; // @[RegisterRouter.scala:87:24]
wire out_rivalid_92; // @[RegisterRouter.scala:87:24]
wire out_rivalid_93; // @[RegisterRouter.scala:87:24]
wire out_rivalid_94; // @[RegisterRouter.scala:87:24]
wire out_rivalid_95; // @[RegisterRouter.scala:87:24]
wire out_rivalid_96; // @[RegisterRouter.scala:87:24]
wire out_rivalid_97; // @[RegisterRouter.scala:87:24]
wire out_rivalid_98; // @[RegisterRouter.scala:87:24]
wire out_rivalid_99; // @[RegisterRouter.scala:87:24]
wire out_rivalid_100; // @[RegisterRouter.scala:87:24]
wire out_rivalid_101; // @[RegisterRouter.scala:87:24]
wire out_rivalid_102; // @[RegisterRouter.scala:87:24]
wire out_rivalid_103; // @[RegisterRouter.scala:87:24]
wire out_rivalid_104; // @[RegisterRouter.scala:87:24]
wire out_rivalid_105; // @[RegisterRouter.scala:87:24]
wire out_rivalid_106; // @[RegisterRouter.scala:87:24]
wire out_rivalid_107; // @[RegisterRouter.scala:87:24]
wire out_rivalid_108; // @[RegisterRouter.scala:87:24]
wire out_rivalid_109; // @[RegisterRouter.scala:87:24]
wire out_rivalid_110; // @[RegisterRouter.scala:87:24]
wire out_rivalid_111; // @[RegisterRouter.scala:87:24]
wire out_rivalid_112; // @[RegisterRouter.scala:87:24]
wire out_rivalid_113; // @[RegisterRouter.scala:87:24]
wire out_rivalid_114; // @[RegisterRouter.scala:87:24]
wire out_rivalid_115; // @[RegisterRouter.scala:87:24]
wire out_rivalid_116; // @[RegisterRouter.scala:87:24]
wire out_rivalid_117; // @[RegisterRouter.scala:87:24]
wire out_rivalid_118; // @[RegisterRouter.scala:87:24]
wire out_rivalid_119; // @[RegisterRouter.scala:87:24]
wire out_rivalid_120; // @[RegisterRouter.scala:87:24]
wire out_rivalid_121; // @[RegisterRouter.scala:87:24]
wire out_rivalid_122; // @[RegisterRouter.scala:87:24]
wire out_rivalid_123; // @[RegisterRouter.scala:87:24]
wire out_rivalid_124; // @[RegisterRouter.scala:87:24]
wire out_rivalid_125; // @[RegisterRouter.scala:87:24]
wire out_rivalid_126; // @[RegisterRouter.scala:87:24]
wire out_rivalid_127; // @[RegisterRouter.scala:87:24]
wire out_rivalid_128; // @[RegisterRouter.scala:87:24]
wire out_rivalid_129; // @[RegisterRouter.scala:87:24]
wire out_rivalid_130; // @[RegisterRouter.scala:87:24]
wire out_rivalid_131; // @[RegisterRouter.scala:87:24]
wire out_rivalid_132; // @[RegisterRouter.scala:87:24]
wire out_rivalid_133; // @[RegisterRouter.scala:87:24]
wire out_rivalid_134; // @[RegisterRouter.scala:87:24]
wire out_rivalid_135; // @[RegisterRouter.scala:87:24]
wire out_rivalid_136; // @[RegisterRouter.scala:87:24]
wire out_rivalid_137; // @[RegisterRouter.scala:87:24]
wire out_rivalid_138; // @[RegisterRouter.scala:87:24]
wire out_rivalid_139; // @[RegisterRouter.scala:87:24]
wire out_rivalid_140; // @[RegisterRouter.scala:87:24]
wire out_rivalid_141; // @[RegisterRouter.scala:87:24]
wire out_rivalid_142; // @[RegisterRouter.scala:87:24]
wire out_rivalid_143; // @[RegisterRouter.scala:87:24]
wire out_rivalid_144; // @[RegisterRouter.scala:87:24]
wire out_rivalid_145; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_24; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_248; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_40; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_168; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_144; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_36; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_20; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_192; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_44; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_172; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_100; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_152; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_188; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_232; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_28; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_244; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_156; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_136; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_184; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_132; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_140; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_92; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_180; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_32; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_160; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_48; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_176; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_164; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_96; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_148; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_80; // @[RegisterRouter.scala:87:24]
wire out_wivalid_0; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1; // @[RegisterRouter.scala:87:24]
wire out_wivalid_2; // @[RegisterRouter.scala:87:24]
wire out_wivalid_3; // @[RegisterRouter.scala:87:24]
wire out_wivalid_4; // @[RegisterRouter.scala:87:24]
wire out_wivalid_5; // @[RegisterRouter.scala:87:24]
wire out_wivalid_6; // @[RegisterRouter.scala:87:24]
wire out_wivalid_7; // @[RegisterRouter.scala:87:24]
wire out_wivalid_8; // @[RegisterRouter.scala:87:24]
wire out_wivalid_9; // @[RegisterRouter.scala:87:24]
wire out_wivalid_10; // @[RegisterRouter.scala:87:24]
wire out_wivalid_11; // @[RegisterRouter.scala:87:24]
wire out_wivalid_12; // @[RegisterRouter.scala:87:24]
wire out_wivalid_13; // @[RegisterRouter.scala:87:24]
wire out_wivalid_14; // @[RegisterRouter.scala:87:24]
wire out_wivalid_15; // @[RegisterRouter.scala:87:24]
wire out_wivalid_16; // @[RegisterRouter.scala:87:24]
wire out_wivalid_17; // @[RegisterRouter.scala:87:24]
wire out_wivalid_18; // @[RegisterRouter.scala:87:24]
wire out_wivalid_19; // @[RegisterRouter.scala:87:24]
wire out_wivalid_20; // @[RegisterRouter.scala:87:24]
wire out_wivalid_21; // @[RegisterRouter.scala:87:24]
wire out_wivalid_22; // @[RegisterRouter.scala:87:24]
wire out_wivalid_23; // @[RegisterRouter.scala:87:24]
wire out_wivalid_24; // @[RegisterRouter.scala:87:24]
wire out_wivalid_25; // @[RegisterRouter.scala:87:24]
wire out_wivalid_26; // @[RegisterRouter.scala:87:24]
wire out_wivalid_27; // @[RegisterRouter.scala:87:24]
wire out_wivalid_28; // @[RegisterRouter.scala:87:24]
wire out_wivalid_29; // @[RegisterRouter.scala:87:24]
wire out_wivalid_30; // @[RegisterRouter.scala:87:24]
wire out_wivalid_31; // @[RegisterRouter.scala:87:24]
wire out_wivalid_32; // @[RegisterRouter.scala:87:24]
wire out_wivalid_33; // @[RegisterRouter.scala:87:24]
wire out_wivalid_34; // @[RegisterRouter.scala:87:24]
wire out_wivalid_35; // @[RegisterRouter.scala:87:24]
wire out_wivalid_36; // @[RegisterRouter.scala:87:24]
wire out_wivalid_37; // @[RegisterRouter.scala:87:24]
wire out_wivalid_38; // @[RegisterRouter.scala:87:24]
wire out_wivalid_39; // @[RegisterRouter.scala:87:24]
wire out_wivalid_40; // @[RegisterRouter.scala:87:24]
wire out_wivalid_41; // @[RegisterRouter.scala:87:24]
wire out_wivalid_42; // @[RegisterRouter.scala:87:24]
wire out_wivalid_43; // @[RegisterRouter.scala:87:24]
wire out_wivalid_44; // @[RegisterRouter.scala:87:24]
wire out_wivalid_45; // @[RegisterRouter.scala:87:24]
wire out_wivalid_46; // @[RegisterRouter.scala:87:24]
wire out_wivalid_47; // @[RegisterRouter.scala:87:24]
wire out_wivalid_48; // @[RegisterRouter.scala:87:24]
wire out_wivalid_49; // @[RegisterRouter.scala:87:24]
wire out_wivalid_50; // @[RegisterRouter.scala:87:24]
wire out_wivalid_51; // @[RegisterRouter.scala:87:24]
wire out_wivalid_52; // @[RegisterRouter.scala:87:24]
wire out_wivalid_53; // @[RegisterRouter.scala:87:24]
wire out_wivalid_54; // @[RegisterRouter.scala:87:24]
wire out_wivalid_55; // @[RegisterRouter.scala:87:24]
wire out_wivalid_56; // @[RegisterRouter.scala:87:24]
wire out_wivalid_57; // @[RegisterRouter.scala:87:24]
wire out_wivalid_58; // @[RegisterRouter.scala:87:24]
wire out_wivalid_59; // @[RegisterRouter.scala:87:24]
wire out_wivalid_60; // @[RegisterRouter.scala:87:24]
wire out_wivalid_61; // @[RegisterRouter.scala:87:24]
wire out_wivalid_62; // @[RegisterRouter.scala:87:24]
wire out_wivalid_63; // @[RegisterRouter.scala:87:24]
wire out_wivalid_64; // @[RegisterRouter.scala:87:24]
wire out_wivalid_65; // @[RegisterRouter.scala:87:24]
wire out_wivalid_66; // @[RegisterRouter.scala:87:24]
wire out_wivalid_67; // @[RegisterRouter.scala:87:24]
wire out_wivalid_68; // @[RegisterRouter.scala:87:24]
wire out_wivalid_69; // @[RegisterRouter.scala:87:24]
wire out_wivalid_70; // @[RegisterRouter.scala:87:24]
wire out_wivalid_71; // @[RegisterRouter.scala:87:24]
wire out_wivalid_72; // @[RegisterRouter.scala:87:24]
wire out_wivalid_73; // @[RegisterRouter.scala:87:24]
wire out_wivalid_74; // @[RegisterRouter.scala:87:24]
wire out_wivalid_75; // @[RegisterRouter.scala:87:24]
wire out_wivalid_76; // @[RegisterRouter.scala:87:24]
wire out_wivalid_77; // @[RegisterRouter.scala:87:24]
wire out_wivalid_78; // @[RegisterRouter.scala:87:24]
wire out_wivalid_79; // @[RegisterRouter.scala:87:24]
wire out_wivalid_80; // @[RegisterRouter.scala:87:24]
wire out_wivalid_81; // @[RegisterRouter.scala:87:24]
wire out_wivalid_82; // @[RegisterRouter.scala:87:24]
wire out_wivalid_83; // @[RegisterRouter.scala:87:24]
wire out_wivalid_84; // @[RegisterRouter.scala:87:24]
wire out_wivalid_85; // @[RegisterRouter.scala:87:24]
wire out_wivalid_86; // @[RegisterRouter.scala:87:24]
wire out_wivalid_87; // @[RegisterRouter.scala:87:24]
wire out_wivalid_88; // @[RegisterRouter.scala:87:24]
wire out_wivalid_89; // @[RegisterRouter.scala:87:24]
wire out_wivalid_90; // @[RegisterRouter.scala:87:24]
wire out_wivalid_91; // @[RegisterRouter.scala:87:24]
wire out_wivalid_92; // @[RegisterRouter.scala:87:24]
wire out_wivalid_93; // @[RegisterRouter.scala:87:24]
wire out_wivalid_94; // @[RegisterRouter.scala:87:24]
wire out_wivalid_95; // @[RegisterRouter.scala:87:24]
wire out_wivalid_96; // @[RegisterRouter.scala:87:24]
wire out_wivalid_97; // @[RegisterRouter.scala:87:24]
wire out_wivalid_98; // @[RegisterRouter.scala:87:24]
wire out_wivalid_99; // @[RegisterRouter.scala:87:24]
wire out_wivalid_100; // @[RegisterRouter.scala:87:24]
wire out_wivalid_101; // @[RegisterRouter.scala:87:24]
wire out_wivalid_102; // @[RegisterRouter.scala:87:24]
wire out_wivalid_103; // @[RegisterRouter.scala:87:24]
wire out_wivalid_104; // @[RegisterRouter.scala:87:24]
wire out_wivalid_105; // @[RegisterRouter.scala:87:24]
wire out_wivalid_106; // @[RegisterRouter.scala:87:24]
wire out_wivalid_107; // @[RegisterRouter.scala:87:24]
wire out_wivalid_108; // @[RegisterRouter.scala:87:24]
wire out_wivalid_109; // @[RegisterRouter.scala:87:24]
wire out_wivalid_110; // @[RegisterRouter.scala:87:24]
wire out_wivalid_111; // @[RegisterRouter.scala:87:24]
wire out_wivalid_112; // @[RegisterRouter.scala:87:24]
wire out_wivalid_113; // @[RegisterRouter.scala:87:24]
wire out_wivalid_114; // @[RegisterRouter.scala:87:24]
wire out_wivalid_115; // @[RegisterRouter.scala:87:24]
wire out_wivalid_116; // @[RegisterRouter.scala:87:24]
wire out_wivalid_117; // @[RegisterRouter.scala:87:24]
wire out_wivalid_118; // @[RegisterRouter.scala:87:24]
wire out_wivalid_119; // @[RegisterRouter.scala:87:24]
wire out_wivalid_120; // @[RegisterRouter.scala:87:24]
wire out_wivalid_121; // @[RegisterRouter.scala:87:24]
wire out_wivalid_122; // @[RegisterRouter.scala:87:24]
wire out_wivalid_123; // @[RegisterRouter.scala:87:24]
wire out_wivalid_124; // @[RegisterRouter.scala:87:24]
wire out_wivalid_125; // @[RegisterRouter.scala:87:24]
wire out_wivalid_126; // @[RegisterRouter.scala:87:24]
wire out_wivalid_127; // @[RegisterRouter.scala:87:24]
wire out_wivalid_128; // @[RegisterRouter.scala:87:24]
wire out_wivalid_129; // @[RegisterRouter.scala:87:24]
wire out_wivalid_130; // @[RegisterRouter.scala:87:24]
wire out_wivalid_131; // @[RegisterRouter.scala:87:24]
wire out_wivalid_132; // @[RegisterRouter.scala:87:24]
wire out_wivalid_133; // @[RegisterRouter.scala:87:24]
wire out_wivalid_134; // @[RegisterRouter.scala:87:24]
wire out_wivalid_135; // @[RegisterRouter.scala:87:24]
wire out_wivalid_136; // @[RegisterRouter.scala:87:24]
wire out_wivalid_137; // @[RegisterRouter.scala:87:24]
wire out_wivalid_138; // @[RegisterRouter.scala:87:24]
wire out_wivalid_139; // @[RegisterRouter.scala:87:24]
wire out_wivalid_140; // @[RegisterRouter.scala:87:24]
wire out_wivalid_141; // @[RegisterRouter.scala:87:24]
wire out_wivalid_142; // @[RegisterRouter.scala:87:24]
wire out_wivalid_143; // @[RegisterRouter.scala:87:24]
wire out_wivalid_144; // @[RegisterRouter.scala:87:24]
wire out_wivalid_145; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_23; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_247; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_39; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_167; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_143; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_35; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_19; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_191; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_43; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_171; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_99; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_151; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_187; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_231; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_27; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_243; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_155; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_135; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_183; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_131; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_139; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_91; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_179; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_31; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_159; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_47; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_175; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_163; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_95; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_147; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_79; // @[RegisterRouter.scala:87:24]
wire out_roready_0; // @[RegisterRouter.scala:87:24]
wire out_roready_1; // @[RegisterRouter.scala:87:24]
wire out_roready_2; // @[RegisterRouter.scala:87:24]
wire out_roready_3; // @[RegisterRouter.scala:87:24]
wire out_roready_4; // @[RegisterRouter.scala:87:24]
wire out_roready_5; // @[RegisterRouter.scala:87:24]
wire out_roready_6; // @[RegisterRouter.scala:87:24]
wire out_roready_7; // @[RegisterRouter.scala:87:24]
wire out_roready_8; // @[RegisterRouter.scala:87:24]
wire out_roready_9; // @[RegisterRouter.scala:87:24]
wire out_roready_10; // @[RegisterRouter.scala:87:24]
wire out_roready_11; // @[RegisterRouter.scala:87:24]
wire out_roready_12; // @[RegisterRouter.scala:87:24]
wire out_roready_13; // @[RegisterRouter.scala:87:24]
wire out_roready_14; // @[RegisterRouter.scala:87:24]
wire out_roready_15; // @[RegisterRouter.scala:87:24]
wire out_roready_16; // @[RegisterRouter.scala:87:24]
wire out_roready_17; // @[RegisterRouter.scala:87:24]
wire out_roready_18; // @[RegisterRouter.scala:87:24]
wire out_roready_19; // @[RegisterRouter.scala:87:24]
wire out_roready_20; // @[RegisterRouter.scala:87:24]
wire out_roready_21; // @[RegisterRouter.scala:87:24]
wire out_roready_22; // @[RegisterRouter.scala:87:24]
wire out_roready_23; // @[RegisterRouter.scala:87:24]
wire out_roready_24; // @[RegisterRouter.scala:87:24]
wire out_roready_25; // @[RegisterRouter.scala:87:24]
wire out_roready_26; // @[RegisterRouter.scala:87:24]
wire out_roready_27; // @[RegisterRouter.scala:87:24]
wire out_roready_28; // @[RegisterRouter.scala:87:24]
wire out_roready_29; // @[RegisterRouter.scala:87:24]
wire out_roready_30; // @[RegisterRouter.scala:87:24]
wire out_roready_31; // @[RegisterRouter.scala:87:24]
wire out_roready_32; // @[RegisterRouter.scala:87:24]
wire out_roready_33; // @[RegisterRouter.scala:87:24]
wire out_roready_34; // @[RegisterRouter.scala:87:24]
wire out_roready_35; // @[RegisterRouter.scala:87:24]
wire out_roready_36; // @[RegisterRouter.scala:87:24]
wire out_roready_37; // @[RegisterRouter.scala:87:24]
wire out_roready_38; // @[RegisterRouter.scala:87:24]
wire out_roready_39; // @[RegisterRouter.scala:87:24]
wire out_roready_40; // @[RegisterRouter.scala:87:24]
wire out_roready_41; // @[RegisterRouter.scala:87:24]
wire out_roready_42; // @[RegisterRouter.scala:87:24]
wire out_roready_43; // @[RegisterRouter.scala:87:24]
wire out_roready_44; // @[RegisterRouter.scala:87:24]
wire out_roready_45; // @[RegisterRouter.scala:87:24]
wire out_roready_46; // @[RegisterRouter.scala:87:24]
wire out_roready_47; // @[RegisterRouter.scala:87:24]
wire out_roready_48; // @[RegisterRouter.scala:87:24]
wire out_roready_49; // @[RegisterRouter.scala:87:24]
wire out_roready_50; // @[RegisterRouter.scala:87:24]
wire out_roready_51; // @[RegisterRouter.scala:87:24]
wire out_roready_52; // @[RegisterRouter.scala:87:24]
wire out_roready_53; // @[RegisterRouter.scala:87:24]
wire out_roready_54; // @[RegisterRouter.scala:87:24]
wire out_roready_55; // @[RegisterRouter.scala:87:24]
wire out_roready_56; // @[RegisterRouter.scala:87:24]
wire out_roready_57; // @[RegisterRouter.scala:87:24]
wire out_roready_58; // @[RegisterRouter.scala:87:24]
wire out_roready_59; // @[RegisterRouter.scala:87:24]
wire out_roready_60; // @[RegisterRouter.scala:87:24]
wire out_roready_61; // @[RegisterRouter.scala:87:24]
wire out_roready_62; // @[RegisterRouter.scala:87:24]
wire out_roready_63; // @[RegisterRouter.scala:87:24]
wire out_roready_64; // @[RegisterRouter.scala:87:24]
wire out_roready_65; // @[RegisterRouter.scala:87:24]
wire out_roready_66; // @[RegisterRouter.scala:87:24]
wire out_roready_67; // @[RegisterRouter.scala:87:24]
wire out_roready_68; // @[RegisterRouter.scala:87:24]
wire out_roready_69; // @[RegisterRouter.scala:87:24]
wire out_roready_70; // @[RegisterRouter.scala:87:24]
wire out_roready_71; // @[RegisterRouter.scala:87:24]
wire out_roready_72; // @[RegisterRouter.scala:87:24]
wire out_roready_73; // @[RegisterRouter.scala:87:24]
wire out_roready_74; // @[RegisterRouter.scala:87:24]
wire out_roready_75; // @[RegisterRouter.scala:87:24]
wire out_roready_76; // @[RegisterRouter.scala:87:24]
wire out_roready_77; // @[RegisterRouter.scala:87:24]
wire out_roready_78; // @[RegisterRouter.scala:87:24]
wire out_roready_79; // @[RegisterRouter.scala:87:24]
wire out_roready_80; // @[RegisterRouter.scala:87:24]
wire out_roready_81; // @[RegisterRouter.scala:87:24]
wire out_roready_82; // @[RegisterRouter.scala:87:24]
wire out_roready_83; // @[RegisterRouter.scala:87:24]
wire out_roready_84; // @[RegisterRouter.scala:87:24]
wire out_roready_85; // @[RegisterRouter.scala:87:24]
wire out_roready_86; // @[RegisterRouter.scala:87:24]
wire out_roready_87; // @[RegisterRouter.scala:87:24]
wire out_roready_88; // @[RegisterRouter.scala:87:24]
wire out_roready_89; // @[RegisterRouter.scala:87:24]
wire out_roready_90; // @[RegisterRouter.scala:87:24]
wire out_roready_91; // @[RegisterRouter.scala:87:24]
wire out_roready_92; // @[RegisterRouter.scala:87:24]
wire out_roready_93; // @[RegisterRouter.scala:87:24]
wire out_roready_94; // @[RegisterRouter.scala:87:24]
wire out_roready_95; // @[RegisterRouter.scala:87:24]
wire out_roready_96; // @[RegisterRouter.scala:87:24]
wire out_roready_97; // @[RegisterRouter.scala:87:24]
wire out_roready_98; // @[RegisterRouter.scala:87:24]
wire out_roready_99; // @[RegisterRouter.scala:87:24]
wire out_roready_100; // @[RegisterRouter.scala:87:24]
wire out_roready_101; // @[RegisterRouter.scala:87:24]
wire out_roready_102; // @[RegisterRouter.scala:87:24]
wire out_roready_103; // @[RegisterRouter.scala:87:24]
wire out_roready_104; // @[RegisterRouter.scala:87:24]
wire out_roready_105; // @[RegisterRouter.scala:87:24]
wire out_roready_106; // @[RegisterRouter.scala:87:24]
wire out_roready_107; // @[RegisterRouter.scala:87:24]
wire out_roready_108; // @[RegisterRouter.scala:87:24]
wire out_roready_109; // @[RegisterRouter.scala:87:24]
wire out_roready_110; // @[RegisterRouter.scala:87:24]
wire out_roready_111; // @[RegisterRouter.scala:87:24]
wire out_roready_112; // @[RegisterRouter.scala:87:24]
wire out_roready_113; // @[RegisterRouter.scala:87:24]
wire out_roready_114; // @[RegisterRouter.scala:87:24]
wire out_roready_115; // @[RegisterRouter.scala:87:24]
wire out_roready_116; // @[RegisterRouter.scala:87:24]
wire out_roready_117; // @[RegisterRouter.scala:87:24]
wire out_roready_118; // @[RegisterRouter.scala:87:24]
wire out_roready_119; // @[RegisterRouter.scala:87:24]
wire out_roready_120; // @[RegisterRouter.scala:87:24]
wire out_roready_121; // @[RegisterRouter.scala:87:24]
wire out_roready_122; // @[RegisterRouter.scala:87:24]
wire out_roready_123; // @[RegisterRouter.scala:87:24]
wire out_roready_124; // @[RegisterRouter.scala:87:24]
wire out_roready_125; // @[RegisterRouter.scala:87:24]
wire out_roready_126; // @[RegisterRouter.scala:87:24]
wire out_roready_127; // @[RegisterRouter.scala:87:24]
wire out_roready_128; // @[RegisterRouter.scala:87:24]
wire out_roready_129; // @[RegisterRouter.scala:87:24]
wire out_roready_130; // @[RegisterRouter.scala:87:24]
wire out_roready_131; // @[RegisterRouter.scala:87:24]
wire out_roready_132; // @[RegisterRouter.scala:87:24]
wire out_roready_133; // @[RegisterRouter.scala:87:24]
wire out_roready_134; // @[RegisterRouter.scala:87:24]
wire out_roready_135; // @[RegisterRouter.scala:87:24]
wire out_roready_136; // @[RegisterRouter.scala:87:24]
wire out_roready_137; // @[RegisterRouter.scala:87:24]
wire out_roready_138; // @[RegisterRouter.scala:87:24]
wire out_roready_139; // @[RegisterRouter.scala:87:24]
wire out_roready_140; // @[RegisterRouter.scala:87:24]
wire out_roready_141; // @[RegisterRouter.scala:87:24]
wire out_roready_142; // @[RegisterRouter.scala:87:24]
wire out_roready_143; // @[RegisterRouter.scala:87:24]
wire out_roready_144; // @[RegisterRouter.scala:87:24]
wire out_roready_145; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_24; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_248; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_40; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_168; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_144; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_36; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_20; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_192; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_44; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_172; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_100; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_152; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_188; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_232; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_28; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_244; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_156; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_136; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_184; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_132; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_140; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_92; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_180; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_32; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_160; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_48; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_176; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_164; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_96; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_148; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_80; // @[RegisterRouter.scala:87:24]
wire out_woready_0; // @[RegisterRouter.scala:87:24]
wire out_woready_1; // @[RegisterRouter.scala:87:24]
wire out_woready_2; // @[RegisterRouter.scala:87:24]
wire out_woready_3; // @[RegisterRouter.scala:87:24]
wire out_woready_4; // @[RegisterRouter.scala:87:24]
wire out_woready_5; // @[RegisterRouter.scala:87:24]
wire out_woready_6; // @[RegisterRouter.scala:87:24]
wire out_woready_7; // @[RegisterRouter.scala:87:24]
wire out_woready_8; // @[RegisterRouter.scala:87:24]
wire out_woready_9; // @[RegisterRouter.scala:87:24]
wire out_woready_10; // @[RegisterRouter.scala:87:24]
wire out_woready_11; // @[RegisterRouter.scala:87:24]
wire out_woready_12; // @[RegisterRouter.scala:87:24]
wire out_woready_13; // @[RegisterRouter.scala:87:24]
wire out_woready_14; // @[RegisterRouter.scala:87:24]
wire out_woready_15; // @[RegisterRouter.scala:87:24]
wire out_woready_16; // @[RegisterRouter.scala:87:24]
wire out_woready_17; // @[RegisterRouter.scala:87:24]
wire out_woready_18; // @[RegisterRouter.scala:87:24]
wire out_woready_19; // @[RegisterRouter.scala:87:24]
wire out_woready_20; // @[RegisterRouter.scala:87:24]
wire out_woready_21; // @[RegisterRouter.scala:87:24]
wire out_woready_22; // @[RegisterRouter.scala:87:24]
wire out_woready_23; // @[RegisterRouter.scala:87:24]
wire out_woready_24; // @[RegisterRouter.scala:87:24]
wire out_woready_25; // @[RegisterRouter.scala:87:24]
wire out_woready_26; // @[RegisterRouter.scala:87:24]
wire out_woready_27; // @[RegisterRouter.scala:87:24]
wire out_woready_28; // @[RegisterRouter.scala:87:24]
wire out_woready_29; // @[RegisterRouter.scala:87:24]
wire out_woready_30; // @[RegisterRouter.scala:87:24]
wire out_woready_31; // @[RegisterRouter.scala:87:24]
wire out_woready_32; // @[RegisterRouter.scala:87:24]
wire out_woready_33; // @[RegisterRouter.scala:87:24]
wire out_woready_34; // @[RegisterRouter.scala:87:24]
wire out_woready_35; // @[RegisterRouter.scala:87:24]
wire out_woready_36; // @[RegisterRouter.scala:87:24]
wire out_woready_37; // @[RegisterRouter.scala:87:24]
wire out_woready_38; // @[RegisterRouter.scala:87:24]
wire out_woready_39; // @[RegisterRouter.scala:87:24]
wire out_woready_40; // @[RegisterRouter.scala:87:24]
wire out_woready_41; // @[RegisterRouter.scala:87:24]
wire out_woready_42; // @[RegisterRouter.scala:87:24]
wire out_woready_43; // @[RegisterRouter.scala:87:24]
wire out_woready_44; // @[RegisterRouter.scala:87:24]
wire out_woready_45; // @[RegisterRouter.scala:87:24]
wire out_woready_46; // @[RegisterRouter.scala:87:24]
wire out_woready_47; // @[RegisterRouter.scala:87:24]
wire out_woready_48; // @[RegisterRouter.scala:87:24]
wire out_woready_49; // @[RegisterRouter.scala:87:24]
wire out_woready_50; // @[RegisterRouter.scala:87:24]
wire out_woready_51; // @[RegisterRouter.scala:87:24]
wire out_woready_52; // @[RegisterRouter.scala:87:24]
wire out_woready_53; // @[RegisterRouter.scala:87:24]
wire out_woready_54; // @[RegisterRouter.scala:87:24]
wire out_woready_55; // @[RegisterRouter.scala:87:24]
wire out_woready_56; // @[RegisterRouter.scala:87:24]
wire out_woready_57; // @[RegisterRouter.scala:87:24]
wire out_woready_58; // @[RegisterRouter.scala:87:24]
wire out_woready_59; // @[RegisterRouter.scala:87:24]
wire out_woready_60; // @[RegisterRouter.scala:87:24]
wire out_woready_61; // @[RegisterRouter.scala:87:24]
wire out_woready_62; // @[RegisterRouter.scala:87:24]
wire out_woready_63; // @[RegisterRouter.scala:87:24]
wire out_woready_64; // @[RegisterRouter.scala:87:24]
wire out_woready_65; // @[RegisterRouter.scala:87:24]
wire out_woready_66; // @[RegisterRouter.scala:87:24]
wire out_woready_67; // @[RegisterRouter.scala:87:24]
wire out_woready_68; // @[RegisterRouter.scala:87:24]
wire out_woready_69; // @[RegisterRouter.scala:87:24]
wire out_woready_70; // @[RegisterRouter.scala:87:24]
wire out_woready_71; // @[RegisterRouter.scala:87:24]
wire out_woready_72; // @[RegisterRouter.scala:87:24]
wire out_woready_73; // @[RegisterRouter.scala:87:24]
wire out_woready_74; // @[RegisterRouter.scala:87:24]
wire out_woready_75; // @[RegisterRouter.scala:87:24]
wire out_woready_76; // @[RegisterRouter.scala:87:24]
wire out_woready_77; // @[RegisterRouter.scala:87:24]
wire out_woready_78; // @[RegisterRouter.scala:87:24]
wire out_woready_79; // @[RegisterRouter.scala:87:24]
wire out_woready_80; // @[RegisterRouter.scala:87:24]
wire out_woready_81; // @[RegisterRouter.scala:87:24]
wire out_woready_82; // @[RegisterRouter.scala:87:24]
wire out_woready_83; // @[RegisterRouter.scala:87:24]
wire out_woready_84; // @[RegisterRouter.scala:87:24]
wire out_woready_85; // @[RegisterRouter.scala:87:24]
wire out_woready_86; // @[RegisterRouter.scala:87:24]
wire out_woready_87; // @[RegisterRouter.scala:87:24]
wire out_woready_88; // @[RegisterRouter.scala:87:24]
wire out_woready_89; // @[RegisterRouter.scala:87:24]
wire out_woready_90; // @[RegisterRouter.scala:87:24]
wire out_woready_91; // @[RegisterRouter.scala:87:24]
wire out_woready_92; // @[RegisterRouter.scala:87:24]
wire out_woready_93; // @[RegisterRouter.scala:87:24]
wire out_woready_94; // @[RegisterRouter.scala:87:24]
wire out_woready_95; // @[RegisterRouter.scala:87:24]
wire out_woready_96; // @[RegisterRouter.scala:87:24]
wire out_woready_97; // @[RegisterRouter.scala:87:24]
wire out_woready_98; // @[RegisterRouter.scala:87:24]
wire out_woready_99; // @[RegisterRouter.scala:87:24]
wire out_woready_100; // @[RegisterRouter.scala:87:24]
wire out_woready_101; // @[RegisterRouter.scala:87:24]
wire out_woready_102; // @[RegisterRouter.scala:87:24]
wire out_woready_103; // @[RegisterRouter.scala:87:24]
wire out_woready_104; // @[RegisterRouter.scala:87:24]
wire out_woready_105; // @[RegisterRouter.scala:87:24]
wire out_woready_106; // @[RegisterRouter.scala:87:24]
wire out_woready_107; // @[RegisterRouter.scala:87:24]
wire out_woready_108; // @[RegisterRouter.scala:87:24]
wire out_woready_109; // @[RegisterRouter.scala:87:24]
wire out_woready_110; // @[RegisterRouter.scala:87:24]
wire out_woready_111; // @[RegisterRouter.scala:87:24]
wire out_woready_112; // @[RegisterRouter.scala:87:24]
wire out_woready_113; // @[RegisterRouter.scala:87:24]
wire out_woready_114; // @[RegisterRouter.scala:87:24]
wire out_woready_115; // @[RegisterRouter.scala:87:24]
wire out_woready_116; // @[RegisterRouter.scala:87:24]
wire out_woready_117; // @[RegisterRouter.scala:87:24]
wire out_woready_118; // @[RegisterRouter.scala:87:24]
wire out_woready_119; // @[RegisterRouter.scala:87:24]
wire out_woready_120; // @[RegisterRouter.scala:87:24]
wire out_woready_121; // @[RegisterRouter.scala:87:24]
wire out_woready_122; // @[RegisterRouter.scala:87:24]
wire out_woready_123; // @[RegisterRouter.scala:87:24]
wire out_woready_124; // @[RegisterRouter.scala:87:24]
wire out_woready_125; // @[RegisterRouter.scala:87:24]
wire out_woready_126; // @[RegisterRouter.scala:87:24]
wire out_woready_127; // @[RegisterRouter.scala:87:24]
wire out_woready_128; // @[RegisterRouter.scala:87:24]
wire out_woready_129; // @[RegisterRouter.scala:87:24]
wire out_woready_130; // @[RegisterRouter.scala:87:24]
wire out_woready_131; // @[RegisterRouter.scala:87:24]
wire out_woready_132; // @[RegisterRouter.scala:87:24]
wire out_woready_133; // @[RegisterRouter.scala:87:24]
wire out_woready_134; // @[RegisterRouter.scala:87:24]
wire out_woready_135; // @[RegisterRouter.scala:87:24]
wire out_woready_136; // @[RegisterRouter.scala:87:24]
wire out_woready_137; // @[RegisterRouter.scala:87:24]
wire out_woready_138; // @[RegisterRouter.scala:87:24]
wire out_woready_139; // @[RegisterRouter.scala:87:24]
wire out_woready_140; // @[RegisterRouter.scala:87:24]
wire out_woready_141; // @[RegisterRouter.scala:87:24]
wire out_woready_142; // @[RegisterRouter.scala:87:24]
wire out_woready_143; // @[RegisterRouter.scala:87:24]
wire out_woready_144; // @[RegisterRouter.scala:87:24]
wire out_woready_145; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_4 = {8{_out_frontMask_T}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_5 = {8{_out_frontMask_T_1}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_6 = {8{_out_frontMask_T_2}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_7 = {8{_out_frontMask_T_3}}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_frontMask_lo = {_out_frontMask_T_5, _out_frontMask_T_4}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_frontMask_hi = {_out_frontMask_T_7, _out_frontMask_T_6}; // @[RegisterRouter.scala:87:24]
wire [31:0] out_frontMask = {out_frontMask_hi, out_frontMask_lo}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_rimask_T_4 = out_frontMask; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_wimask_T_4 = out_frontMask; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_rimask_T_63 = out_frontMask; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_wimask_T_63 = out_frontMask; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_rimask_T_68 = out_frontMask; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_wimask_T_68 = out_frontMask; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_rimask_T_81 = out_frontMask; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_wimask_T_81 = out_frontMask; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_rimask_T_140 = out_frontMask; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_wimask_T_140 = out_frontMask; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_rimask_T_145 = out_frontMask; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_wimask_T_145 = out_frontMask; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_4 = {8{_out_backMask_T}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_5 = {8{_out_backMask_T_1}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_6 = {8{_out_backMask_T_2}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_7 = {8{_out_backMask_T_3}}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_backMask_lo = {_out_backMask_T_5, _out_backMask_T_4}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_backMask_hi = {_out_backMask_T_7, _out_backMask_T_6}; // @[RegisterRouter.scala:87:24]
wire [31:0] out_backMask = {out_backMask_hi, out_backMask_lo}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_romask_T_4 = out_backMask; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_womask_T_4 = out_backMask; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_romask_T_63 = out_backMask; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_womask_T_63 = out_backMask; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_romask_T_68 = out_backMask; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_womask_T_68 = out_backMask; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_romask_T_81 = out_backMask; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_womask_T_81 = out_backMask; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_romask_T_140 = out_backMask; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_womask_T_140 = out_backMask; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_romask_T_145 = out_backMask; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_womask_T_145 = out_backMask; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_5 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_5 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_9 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_9 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_13 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_13 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_17 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_17 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_21 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_21 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_25 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_25 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_29 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_29 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_48 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_48 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_52 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_52 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_55 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_55 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_59 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_59 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_64 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_64 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_69 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_69 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_73 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_73 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_77 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_77 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_101 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_101 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_105 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_105 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_116 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_116 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_120 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_120 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_124 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_124 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_128 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_128 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_132 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_132 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_136 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_136 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_141 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_141 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire out_rimask = |_out_rimask_T; // @[RegisterRouter.scala:87:24]
wire out_wimask = &_out_wimask_T; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_5 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_5 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_9 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_9 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_13 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_13 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_17 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_17 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_21 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_21 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_25 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_25 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_29 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_29 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_48 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_48 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_52 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_52 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_55 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_55 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_59 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_59 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_64 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_64 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_69 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_69 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_73 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_73 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_77 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_77 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_101 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_101 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_105 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_105 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_116 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_116 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_120 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_120 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_124 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_124 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_128 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_128 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_132 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_132 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_136 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_136 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_141 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_141 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire out_romask = |_out_romask_T; // @[RegisterRouter.scala:87:24]
wire out_womask = &_out_womask_T; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid = out_rivalid_0 & out_rimask; // @[RegisterRouter.scala:87:24]
wire _out_T_69 = out_f_rivalid; // @[RegisterRouter.scala:87:24]
assign out_f_roready = out_roready_0 & out_romask; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataRdEn_4 = out_f_roready; // @[RegisterRouter.scala:87:24]
wire _out_T_70 = out_f_roready; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala:87:24]
wire _out_T_71 = out_f_wivalid; // @[RegisterRouter.scala:87:24]
assign out_f_woready = out_woready_0 & out_womask; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataWrEnMaybe_4 = out_f_woready; // @[RegisterRouter.scala:87:24]
wire _out_T_72 = out_f_woready; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_68 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_123 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_167 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_211 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_255 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_299 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_343 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_387 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_578 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_622 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_653 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_697 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_752 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_807 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_851 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_895 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1119 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1163 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1272 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1316 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1360 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1404 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1448 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1492 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1547 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
assign abstractDataNxt_4 = out_f_woready ? _out_T_68 : abstractDataMem_4; // @[RegisterRouter.scala:87:24]
wire _out_T_73 = ~out_rimask; // @[RegisterRouter.scala:87:24]
wire _out_T_74 = ~out_wimask; // @[RegisterRouter.scala:87:24]
wire _out_T_75 = ~out_romask; // @[RegisterRouter.scala:87:24]
wire _out_T_76 = ~out_womask; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_78 = _out_T_77; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T = _out_T_78; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_6 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_6 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_10 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_10 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_14 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_14 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_18 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_18 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_22 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_22 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_26 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_26 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_30 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_30 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_49 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_49 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_53 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_53 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_56 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_56 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_60 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_60 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_65 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_65 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_70 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_70 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_74 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_74 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_78 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_78 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_102 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_102 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_106 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_106 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_117 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_117 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_121 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_121 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_125 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_125 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_129 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_129 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_133 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_133 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_137 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_137 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_142 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_142 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire out_rimask_1 = |_out_rimask_T_1; // @[RegisterRouter.scala:87:24]
wire out_wimask_1 = &_out_wimask_T_1; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_6 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_6 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_10 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_10 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_14 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_14 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_18 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_18 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_22 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_22 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_26 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_26 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_30 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_30 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_49 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_49 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_53 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_53 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_56 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_56 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_60 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_60 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_65 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_65 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_70 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_70 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_74 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_74 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_78 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_78 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_102 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_102 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_106 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_106 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_117 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_117 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_121 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_121 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_125 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_125 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_129 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_129 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_133 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_133 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_137 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_137 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_142 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_142 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire out_romask_1 = |_out_romask_T_1; // @[RegisterRouter.scala:87:24]
wire out_womask_1 = &_out_womask_T_1; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1 = out_rivalid_1 & out_rimask_1; // @[RegisterRouter.scala:87:24]
wire _out_T_80 = out_f_rivalid_1; // @[RegisterRouter.scala:87:24]
assign out_f_roready_1 = out_roready_1 & out_romask_1; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataRdEn_5 = out_f_roready_1; // @[RegisterRouter.scala:87:24]
wire _out_T_81 = out_f_roready_1; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1 = out_wivalid_1 & out_wimask_1; // @[RegisterRouter.scala:87:24]
wire _out_T_82 = out_f_wivalid_1; // @[RegisterRouter.scala:87:24]
assign out_f_woready_1 = out_woready_1 & out_womask_1; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataWrEnMaybe_5 = out_f_woready_1; // @[RegisterRouter.scala:87:24]
wire _out_T_83 = out_f_woready_1; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_79 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_134 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_178 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_222 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_266 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_310 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_354 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_398 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_589 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_633 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_664 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_708 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_763 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_818 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_862 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_906 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1130 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1174 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1283 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1327 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1371 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1415 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1459 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1503 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1558 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
assign abstractDataNxt_5 = out_f_woready_1 ? _out_T_79 : abstractDataMem_5; // @[RegisterRouter.scala:87:24]
wire _out_T_84 = ~out_rimask_1; // @[RegisterRouter.scala:87:24]
wire _out_T_85 = ~out_wimask_1; // @[RegisterRouter.scala:87:24]
wire _out_T_86 = ~out_romask_1; // @[RegisterRouter.scala:87:24]
wire _out_T_87 = ~out_womask_1; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend = {abstractDataMem_5, _out_prepend_T}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_88 = out_prepend; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_89 = _out_T_88; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_1 = _out_T_89; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_2 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_2 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_7 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_7 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_11 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_11 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_15 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_15 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_19 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_19 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_23 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_23 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_27 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_27 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_31 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_31 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_50 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_50 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_57 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_57 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_61 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_61 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_66 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_66 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_71 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_71 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_75 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_75 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_79 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_79 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_103 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_103 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_107 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_107 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_118 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_118 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_122 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_122 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_126 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_126 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_130 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_130 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_134 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_134 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_138 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_138 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_143 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_143 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire out_rimask_2 = |_out_rimask_T_2; // @[RegisterRouter.scala:87:24]
wire out_wimask_2 = &_out_wimask_T_2; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_2 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_2 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_7 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_7 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_11 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_11 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_15 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_15 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_19 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_19 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_23 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_23 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_27 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_27 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_31 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_31 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_50 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_50 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_57 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_57 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_61 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_61 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_66 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_66 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_71 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_71 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_75 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_75 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_79 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_79 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_103 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_103 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_107 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_107 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_118 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_118 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_122 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_122 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_126 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_126 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_130 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_130 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_134 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_134 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_138 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_138 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_143 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_143 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire out_romask_2 = |_out_romask_T_2; // @[RegisterRouter.scala:87:24]
wire out_womask_2 = &_out_womask_T_2; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_2 = out_rivalid_2 & out_rimask_2; // @[RegisterRouter.scala:87:24]
wire _out_T_91 = out_f_rivalid_2; // @[RegisterRouter.scala:87:24]
assign out_f_roready_2 = out_roready_2 & out_romask_2; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataRdEn_6 = out_f_roready_2; // @[RegisterRouter.scala:87:24]
wire _out_T_92 = out_f_roready_2; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_2 = out_wivalid_2 & out_wimask_2; // @[RegisterRouter.scala:87:24]
wire _out_T_93 = out_f_wivalid_2; // @[RegisterRouter.scala:87:24]
assign out_f_woready_2 = out_woready_2 & out_womask_2; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataWrEnMaybe_6 = out_f_woready_2; // @[RegisterRouter.scala:87:24]
wire _out_T_94 = out_f_woready_2; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_90 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_145 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_189 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_233 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_277 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_321 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_365 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_409 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_600 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_675 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_719 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_774 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_829 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_873 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_917 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1141 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1185 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1294 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1338 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1382 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1426 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1470 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1514 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1569 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
assign abstractDataNxt_6 = out_f_woready_2 ? _out_T_90 : abstractDataMem_6; // @[RegisterRouter.scala:87:24]
wire _out_T_95 = ~out_rimask_2; // @[RegisterRouter.scala:87:24]
wire _out_T_96 = ~out_wimask_2; // @[RegisterRouter.scala:87:24]
wire _out_T_97 = ~out_romask_2; // @[RegisterRouter.scala:87:24]
wire _out_T_98 = ~out_womask_2; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_1 = {abstractDataMem_6, _out_prepend_T_1}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_99 = out_prepend_1; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_100 = _out_T_99; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_2 = _out_T_100; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_3 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_3 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_8 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_8 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_12 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_12 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_16 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_16 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_20 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_20 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_24 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_24 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_28 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_28 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_32 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_32 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_51 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_51 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_58 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_58 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_62 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_62 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_67 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_67 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_72 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_72 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_76 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_76 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_80 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_80 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_104 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_104 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_108 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_108 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_119 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_119 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_123 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_123 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_127 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_127 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_131 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_131 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_135 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_135 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_139 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_139 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_144 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_144 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire out_rimask_3 = |_out_rimask_T_3; // @[RegisterRouter.scala:87:24]
wire out_wimask_3 = &_out_wimask_T_3; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_3 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_3 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_8 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_8 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_12 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_12 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_16 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_16 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_20 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_20 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_24 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_24 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_28 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_28 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_32 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_32 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_51 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_51 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_58 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_58 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_62 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_62 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_67 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_67 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_72 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_72 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_76 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_76 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_80 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_80 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_104 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_104 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_108 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_108 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_119 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_119 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_123 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_123 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_127 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_127 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_131 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_131 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_135 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_135 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_139 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_139 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_144 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_144 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire out_romask_3 = |_out_romask_T_3; // @[RegisterRouter.scala:87:24]
wire out_womask_3 = &_out_womask_T_3; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_3 = out_rivalid_3 & out_rimask_3; // @[RegisterRouter.scala:87:24]
wire _out_T_102 = out_f_rivalid_3; // @[RegisterRouter.scala:87:24]
assign out_f_roready_3 = out_roready_3 & out_romask_3; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataRdEn_7 = out_f_roready_3; // @[RegisterRouter.scala:87:24]
wire _out_T_103 = out_f_roready_3; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_3 = out_wivalid_3 & out_wimask_3; // @[RegisterRouter.scala:87:24]
wire _out_T_104 = out_f_wivalid_3; // @[RegisterRouter.scala:87:24]
assign out_f_woready_3 = out_woready_3 & out_womask_3; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataWrEnMaybe_7 = out_f_woready_3; // @[RegisterRouter.scala:87:24]
wire _out_T_105 = out_f_woready_3; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_101 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_156 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_200 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_244 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_288 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_332 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_376 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_420 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_611 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_686 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_730 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_785 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_840 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_884 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_928 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1152 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1196 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1305 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1349 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1393 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1437 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1481 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1525 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1580 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
assign abstractDataNxt_7 = out_f_woready_3 ? _out_T_101 : abstractDataMem_7; // @[RegisterRouter.scala:87:24]
wire _out_T_106 = ~out_rimask_3; // @[RegisterRouter.scala:87:24]
wire _out_T_107 = ~out_wimask_3; // @[RegisterRouter.scala:87:24]
wire _out_T_108 = ~out_romask_3; // @[RegisterRouter.scala:87:24]
wire _out_T_109 = ~out_womask_3; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_2 = {abstractDataMem_7, _out_prepend_T_2}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_110 = out_prepend_2; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_111 = _out_T_110; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_out_bits_data_WIRE_1_5 = _out_T_111; // @[MuxLiteral.scala:49:48]
wire out_rimask_4 = |_out_rimask_T_4; // @[RegisterRouter.scala:87:24]
wire out_wimask_4 = &_out_wimask_T_4; // @[RegisterRouter.scala:87:24]
wire out_romask_4 = |_out_romask_T_4; // @[RegisterRouter.scala:87:24]
wire out_womask_4 = &_out_womask_T_4; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_4 = out_rivalid_4 & out_rimask_4; // @[RegisterRouter.scala:87:24]
wire _out_T_113 = out_f_rivalid_4; // @[RegisterRouter.scala:87:24]
assign out_f_roready_4 = out_roready_4 & out_romask_4; // @[RegisterRouter.scala:87:24]
assign SBDATARdEn_1 = out_f_roready_4; // @[RegisterRouter.scala:87:24]
wire _out_T_114 = out_f_roready_4; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_4 = out_wivalid_4 & out_wimask_4; // @[RegisterRouter.scala:87:24]
wire _out_T_115 = out_f_wivalid_4; // @[RegisterRouter.scala:87:24]
assign out_f_woready_4 = out_woready_4 & out_womask_4; // @[RegisterRouter.scala:87:24]
assign SBDATAWrEn_1 = out_f_woready_4; // @[RegisterRouter.scala:87:24]
wire _out_T_116 = out_f_woready_4; // @[RegisterRouter.scala:87:24]
assign SBDATAWrData_1 = out_f_woready_4 ? _out_T_112 : 32'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_117 = ~out_rimask_4; // @[RegisterRouter.scala:87:24]
wire _out_T_118 = ~out_wimask_4; // @[RegisterRouter.scala:87:24]
wire _out_T_119 = ~out_romask_4; // @[RegisterRouter.scala:87:24]
wire _out_T_120 = ~out_womask_4; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_122 = _out_T_121; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_out_bits_data_WIRE_1_61 = _out_T_122; // @[MuxLiteral.scala:49:48]
wire out_rimask_5 = |_out_rimask_T_5; // @[RegisterRouter.scala:87:24]
wire out_wimask_5 = &_out_wimask_T_5; // @[RegisterRouter.scala:87:24]
wire out_romask_5 = |_out_romask_T_5; // @[RegisterRouter.scala:87:24]
wire out_womask_5 = &_out_womask_T_5; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_5 = out_rivalid_5 & out_rimask_5; // @[RegisterRouter.scala:87:24]
wire _out_T_124 = out_f_rivalid_5; // @[RegisterRouter.scala:87:24]
assign out_f_roready_5 = out_roready_5 & out_romask_5; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataRdEn_20 = out_f_roready_5; // @[RegisterRouter.scala:87:24]
wire _out_T_125 = out_f_roready_5; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_5 = out_wivalid_5 & out_wimask_5; // @[RegisterRouter.scala:87:24]
wire _out_T_126 = out_f_wivalid_5; // @[RegisterRouter.scala:87:24]
assign out_f_woready_5 = out_woready_5 & out_womask_5; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataWrEnMaybe_20 = out_f_woready_5; // @[RegisterRouter.scala:87:24]
wire _out_T_127 = out_f_woready_5; // @[RegisterRouter.scala:87:24]
assign abstractDataNxt_20 = out_f_woready_5 ? _out_T_123 : abstractDataMem_20; // @[RegisterRouter.scala:87:24]
wire _out_T_128 = ~out_rimask_5; // @[RegisterRouter.scala:87:24]
wire _out_T_129 = ~out_wimask_5; // @[RegisterRouter.scala:87:24]
wire _out_T_130 = ~out_romask_5; // @[RegisterRouter.scala:87:24]
wire _out_T_131 = ~out_womask_5; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_133 = _out_T_132; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_3 = _out_T_133; // @[RegisterRouter.scala:87:24]
wire out_rimask_6 = |_out_rimask_T_6; // @[RegisterRouter.scala:87:24]
wire out_wimask_6 = &_out_wimask_T_6; // @[RegisterRouter.scala:87:24]
wire out_romask_6 = |_out_romask_T_6; // @[RegisterRouter.scala:87:24]
wire out_womask_6 = &_out_womask_T_6; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_6 = out_rivalid_6 & out_rimask_6; // @[RegisterRouter.scala:87:24]
wire _out_T_135 = out_f_rivalid_6; // @[RegisterRouter.scala:87:24]
assign out_f_roready_6 = out_roready_6 & out_romask_6; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataRdEn_21 = out_f_roready_6; // @[RegisterRouter.scala:87:24]
wire _out_T_136 = out_f_roready_6; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_6 = out_wivalid_6 & out_wimask_6; // @[RegisterRouter.scala:87:24]
wire _out_T_137 = out_f_wivalid_6; // @[RegisterRouter.scala:87:24]
assign out_f_woready_6 = out_woready_6 & out_womask_6; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataWrEnMaybe_21 = out_f_woready_6; // @[RegisterRouter.scala:87:24]
wire _out_T_138 = out_f_woready_6; // @[RegisterRouter.scala:87:24]
assign abstractDataNxt_21 = out_f_woready_6 ? _out_T_134 : abstractDataMem_21; // @[RegisterRouter.scala:87:24]
wire _out_T_139 = ~out_rimask_6; // @[RegisterRouter.scala:87:24]
wire _out_T_140 = ~out_wimask_6; // @[RegisterRouter.scala:87:24]
wire _out_T_141 = ~out_romask_6; // @[RegisterRouter.scala:87:24]
wire _out_T_142 = ~out_womask_6; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_3 = {abstractDataMem_21, _out_prepend_T_3}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_143 = out_prepend_3; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_144 = _out_T_143; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_4 = _out_T_144; // @[RegisterRouter.scala:87:24]
wire out_rimask_7 = |_out_rimask_T_7; // @[RegisterRouter.scala:87:24]
wire out_wimask_7 = &_out_wimask_T_7; // @[RegisterRouter.scala:87:24]
wire out_romask_7 = |_out_romask_T_7; // @[RegisterRouter.scala:87:24]
wire out_womask_7 = &_out_womask_T_7; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_7 = out_rivalid_7 & out_rimask_7; // @[RegisterRouter.scala:87:24]
wire _out_T_146 = out_f_rivalid_7; // @[RegisterRouter.scala:87:24]
assign out_f_roready_7 = out_roready_7 & out_romask_7; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataRdEn_22 = out_f_roready_7; // @[RegisterRouter.scala:87:24]
wire _out_T_147 = out_f_roready_7; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_7 = out_wivalid_7 & out_wimask_7; // @[RegisterRouter.scala:87:24]
wire _out_T_148 = out_f_wivalid_7; // @[RegisterRouter.scala:87:24]
assign out_f_woready_7 = out_woready_7 & out_womask_7; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataWrEnMaybe_22 = out_f_woready_7; // @[RegisterRouter.scala:87:24]
wire _out_T_149 = out_f_woready_7; // @[RegisterRouter.scala:87:24]
assign abstractDataNxt_22 = out_f_woready_7 ? _out_T_145 : abstractDataMem_22; // @[RegisterRouter.scala:87:24]
wire _out_T_150 = ~out_rimask_7; // @[RegisterRouter.scala:87:24]
wire _out_T_151 = ~out_wimask_7; // @[RegisterRouter.scala:87:24]
wire _out_T_152 = ~out_romask_7; // @[RegisterRouter.scala:87:24]
wire _out_T_153 = ~out_womask_7; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_4 = {abstractDataMem_22, _out_prepend_T_4}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_154 = out_prepend_4; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_155 = _out_T_154; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_5 = _out_T_155; // @[RegisterRouter.scala:87:24]
wire out_rimask_8 = |_out_rimask_T_8; // @[RegisterRouter.scala:87:24]
wire out_wimask_8 = &_out_wimask_T_8; // @[RegisterRouter.scala:87:24]
wire out_romask_8 = |_out_romask_T_8; // @[RegisterRouter.scala:87:24]
wire out_womask_8 = &_out_womask_T_8; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_8 = out_rivalid_8 & out_rimask_8; // @[RegisterRouter.scala:87:24]
wire _out_T_157 = out_f_rivalid_8; // @[RegisterRouter.scala:87:24]
assign out_f_roready_8 = out_roready_8 & out_romask_8; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataRdEn_23 = out_f_roready_8; // @[RegisterRouter.scala:87:24]
wire _out_T_158 = out_f_roready_8; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_8 = out_wivalid_8 & out_wimask_8; // @[RegisterRouter.scala:87:24]
wire _out_T_159 = out_f_wivalid_8; // @[RegisterRouter.scala:87:24]
assign out_f_woready_8 = out_woready_8 & out_womask_8; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataWrEnMaybe_23 = out_f_woready_8; // @[RegisterRouter.scala:87:24]
wire _out_T_160 = out_f_woready_8; // @[RegisterRouter.scala:87:24]
assign abstractDataNxt_23 = out_f_woready_8 ? _out_T_156 : abstractDataMem_23; // @[RegisterRouter.scala:87:24]
wire _out_T_161 = ~out_rimask_8; // @[RegisterRouter.scala:87:24]
wire _out_T_162 = ~out_wimask_8; // @[RegisterRouter.scala:87:24]
wire _out_T_163 = ~out_romask_8; // @[RegisterRouter.scala:87:24]
wire _out_T_164 = ~out_womask_8; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_5 = {abstractDataMem_23, _out_prepend_T_5}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_165 = out_prepend_5; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_166 = _out_T_165; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_out_bits_data_WIRE_1_9 = _out_T_166; // @[MuxLiteral.scala:49:48]
wire out_rimask_9 = |_out_rimask_T_9; // @[RegisterRouter.scala:87:24]
wire out_wimask_9 = &_out_wimask_T_9; // @[RegisterRouter.scala:87:24]
wire out_romask_9 = |_out_romask_T_9; // @[RegisterRouter.scala:87:24]
wire out_womask_9 = &_out_womask_T_9; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_9 = out_rivalid_9 & out_rimask_9; // @[RegisterRouter.scala:87:24]
wire _out_T_168 = out_f_rivalid_9; // @[RegisterRouter.scala:87:24]
assign out_f_roready_9 = out_roready_9 & out_romask_9; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_36 = out_f_roready_9; // @[RegisterRouter.scala:87:24]
wire _out_T_169 = out_f_roready_9; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_9 = out_wivalid_9 & out_wimask_9; // @[RegisterRouter.scala:87:24]
wire _out_T_170 = out_f_wivalid_9; // @[RegisterRouter.scala:87:24]
assign out_f_woready_9 = out_woready_9 & out_womask_9; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_36 = out_f_woready_9; // @[RegisterRouter.scala:87:24]
wire _out_T_171 = out_f_woready_9; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_36 = out_f_woready_9 ? _out_T_167 : programBufferMem_36; // @[RegisterRouter.scala:87:24]
wire _out_T_172 = ~out_rimask_9; // @[RegisterRouter.scala:87:24]
wire _out_T_173 = ~out_wimask_9; // @[RegisterRouter.scala:87:24]
wire _out_T_174 = ~out_romask_9; // @[RegisterRouter.scala:87:24]
wire _out_T_175 = ~out_womask_9; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_177 = _out_T_176; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_6 = _out_T_177; // @[RegisterRouter.scala:87:24]
wire out_rimask_10 = |_out_rimask_T_10; // @[RegisterRouter.scala:87:24]
wire out_wimask_10 = &_out_wimask_T_10; // @[RegisterRouter.scala:87:24]
wire out_romask_10 = |_out_romask_T_10; // @[RegisterRouter.scala:87:24]
wire out_womask_10 = &_out_womask_T_10; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_10 = out_rivalid_10 & out_rimask_10; // @[RegisterRouter.scala:87:24]
wire _out_T_179 = out_f_rivalid_10; // @[RegisterRouter.scala:87:24]
assign out_f_roready_10 = out_roready_10 & out_romask_10; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_37 = out_f_roready_10; // @[RegisterRouter.scala:87:24]
wire _out_T_180 = out_f_roready_10; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_10 = out_wivalid_10 & out_wimask_10; // @[RegisterRouter.scala:87:24]
wire _out_T_181 = out_f_wivalid_10; // @[RegisterRouter.scala:87:24]
assign out_f_woready_10 = out_woready_10 & out_womask_10; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_37 = out_f_woready_10; // @[RegisterRouter.scala:87:24]
wire _out_T_182 = out_f_woready_10; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_37 = out_f_woready_10 ? _out_T_178 : programBufferMem_37; // @[RegisterRouter.scala:87:24]
wire _out_T_183 = ~out_rimask_10; // @[RegisterRouter.scala:87:24]
wire _out_T_184 = ~out_wimask_10; // @[RegisterRouter.scala:87:24]
wire _out_T_185 = ~out_romask_10; // @[RegisterRouter.scala:87:24]
wire _out_T_186 = ~out_womask_10; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_6 = {programBufferMem_37, _out_prepend_T_6}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_187 = out_prepend_6; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_188 = _out_T_187; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_7 = _out_T_188; // @[RegisterRouter.scala:87:24]
wire out_rimask_11 = |_out_rimask_T_11; // @[RegisterRouter.scala:87:24]
wire out_wimask_11 = &_out_wimask_T_11; // @[RegisterRouter.scala:87:24]
wire out_romask_11 = |_out_romask_T_11; // @[RegisterRouter.scala:87:24]
wire out_womask_11 = &_out_womask_T_11; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_11 = out_rivalid_11 & out_rimask_11; // @[RegisterRouter.scala:87:24]
wire _out_T_190 = out_f_rivalid_11; // @[RegisterRouter.scala:87:24]
assign out_f_roready_11 = out_roready_11 & out_romask_11; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_38 = out_f_roready_11; // @[RegisterRouter.scala:87:24]
wire _out_T_191 = out_f_roready_11; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_11 = out_wivalid_11 & out_wimask_11; // @[RegisterRouter.scala:87:24]
wire _out_T_192 = out_f_wivalid_11; // @[RegisterRouter.scala:87:24]
assign out_f_woready_11 = out_woready_11 & out_womask_11; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_38 = out_f_woready_11; // @[RegisterRouter.scala:87:24]
wire _out_T_193 = out_f_woready_11; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_38 = out_f_woready_11 ? _out_T_189 : programBufferMem_38; // @[RegisterRouter.scala:87:24]
wire _out_T_194 = ~out_rimask_11; // @[RegisterRouter.scala:87:24]
wire _out_T_195 = ~out_wimask_11; // @[RegisterRouter.scala:87:24]
wire _out_T_196 = ~out_romask_11; // @[RegisterRouter.scala:87:24]
wire _out_T_197 = ~out_womask_11; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_7 = {programBufferMem_38, _out_prepend_T_7}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_198 = out_prepend_7; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_199 = _out_T_198; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_8 = _out_T_199; // @[RegisterRouter.scala:87:24]
wire out_rimask_12 = |_out_rimask_T_12; // @[RegisterRouter.scala:87:24]
wire out_wimask_12 = &_out_wimask_T_12; // @[RegisterRouter.scala:87:24]
wire out_romask_12 = |_out_romask_T_12; // @[RegisterRouter.scala:87:24]
wire out_womask_12 = &_out_womask_T_12; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_12 = out_rivalid_12 & out_rimask_12; // @[RegisterRouter.scala:87:24]
wire _out_T_201 = out_f_rivalid_12; // @[RegisterRouter.scala:87:24]
assign out_f_roready_12 = out_roready_12 & out_romask_12; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_39 = out_f_roready_12; // @[RegisterRouter.scala:87:24]
wire _out_T_202 = out_f_roready_12; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_12 = out_wivalid_12 & out_wimask_12; // @[RegisterRouter.scala:87:24]
wire _out_T_203 = out_f_wivalid_12; // @[RegisterRouter.scala:87:24]
assign out_f_woready_12 = out_woready_12 & out_womask_12; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_39 = out_f_woready_12; // @[RegisterRouter.scala:87:24]
wire _out_T_204 = out_f_woready_12; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_39 = out_f_woready_12 ? _out_T_200 : programBufferMem_39; // @[RegisterRouter.scala:87:24]
wire _out_T_205 = ~out_rimask_12; // @[RegisterRouter.scala:87:24]
wire _out_T_206 = ~out_wimask_12; // @[RegisterRouter.scala:87:24]
wire _out_T_207 = ~out_romask_12; // @[RegisterRouter.scala:87:24]
wire _out_T_208 = ~out_womask_12; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_8 = {programBufferMem_39, _out_prepend_T_8}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_209 = out_prepend_8; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_210 = _out_T_209; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_out_bits_data_WIRE_1_41 = _out_T_210; // @[MuxLiteral.scala:49:48]
wire out_rimask_13 = |_out_rimask_T_13; // @[RegisterRouter.scala:87:24]
wire out_wimask_13 = &_out_wimask_T_13; // @[RegisterRouter.scala:87:24]
wire out_romask_13 = |_out_romask_T_13; // @[RegisterRouter.scala:87:24]
wire out_womask_13 = &_out_womask_T_13; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_13 = out_rivalid_13 & out_rimask_13; // @[RegisterRouter.scala:87:24]
wire _out_T_212 = out_f_rivalid_13; // @[RegisterRouter.scala:87:24]
assign out_f_roready_13 = out_roready_13 & out_romask_13; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_12 = out_f_roready_13; // @[RegisterRouter.scala:87:24]
wire _out_T_213 = out_f_roready_13; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_13 = out_wivalid_13 & out_wimask_13; // @[RegisterRouter.scala:87:24]
wire _out_T_214 = out_f_wivalid_13; // @[RegisterRouter.scala:87:24]
assign out_f_woready_13 = out_woready_13 & out_womask_13; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_12 = out_f_woready_13; // @[RegisterRouter.scala:87:24]
wire _out_T_215 = out_f_woready_13; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_12 = out_f_woready_13 ? _out_T_211 : programBufferMem_12; // @[RegisterRouter.scala:87:24]
wire _out_T_216 = ~out_rimask_13; // @[RegisterRouter.scala:87:24]
wire _out_T_217 = ~out_wimask_13; // @[RegisterRouter.scala:87:24]
wire _out_T_218 = ~out_romask_13; // @[RegisterRouter.scala:87:24]
wire _out_T_219 = ~out_womask_13; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_221 = _out_T_220; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_9 = _out_T_221; // @[RegisterRouter.scala:87:24]
wire out_rimask_14 = |_out_rimask_T_14; // @[RegisterRouter.scala:87:24]
wire out_wimask_14 = &_out_wimask_T_14; // @[RegisterRouter.scala:87:24]
wire out_romask_14 = |_out_romask_T_14; // @[RegisterRouter.scala:87:24]
wire out_womask_14 = &_out_womask_T_14; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_14 = out_rivalid_14 & out_rimask_14; // @[RegisterRouter.scala:87:24]
wire _out_T_223 = out_f_rivalid_14; // @[RegisterRouter.scala:87:24]
assign out_f_roready_14 = out_roready_14 & out_romask_14; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_13 = out_f_roready_14; // @[RegisterRouter.scala:87:24]
wire _out_T_224 = out_f_roready_14; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_14 = out_wivalid_14 & out_wimask_14; // @[RegisterRouter.scala:87:24]
wire _out_T_225 = out_f_wivalid_14; // @[RegisterRouter.scala:87:24]
assign out_f_woready_14 = out_woready_14 & out_womask_14; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_13 = out_f_woready_14; // @[RegisterRouter.scala:87:24]
wire _out_T_226 = out_f_woready_14; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_13 = out_f_woready_14 ? _out_T_222 : programBufferMem_13; // @[RegisterRouter.scala:87:24]
wire _out_T_227 = ~out_rimask_14; // @[RegisterRouter.scala:87:24]
wire _out_T_228 = ~out_wimask_14; // @[RegisterRouter.scala:87:24]
wire _out_T_229 = ~out_romask_14; // @[RegisterRouter.scala:87:24]
wire _out_T_230 = ~out_womask_14; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_9 = {programBufferMem_13, _out_prepend_T_9}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_231 = out_prepend_9; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_232 = _out_T_231; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_10 = _out_T_232; // @[RegisterRouter.scala:87:24]
wire out_rimask_15 = |_out_rimask_T_15; // @[RegisterRouter.scala:87:24]
wire out_wimask_15 = &_out_wimask_T_15; // @[RegisterRouter.scala:87:24]
wire out_romask_15 = |_out_romask_T_15; // @[RegisterRouter.scala:87:24]
wire out_womask_15 = &_out_womask_T_15; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_15 = out_rivalid_15 & out_rimask_15; // @[RegisterRouter.scala:87:24]
wire _out_T_234 = out_f_rivalid_15; // @[RegisterRouter.scala:87:24]
assign out_f_roready_15 = out_roready_15 & out_romask_15; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_14 = out_f_roready_15; // @[RegisterRouter.scala:87:24]
wire _out_T_235 = out_f_roready_15; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_15 = out_wivalid_15 & out_wimask_15; // @[RegisterRouter.scala:87:24]
wire _out_T_236 = out_f_wivalid_15; // @[RegisterRouter.scala:87:24]
assign out_f_woready_15 = out_woready_15 & out_womask_15; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_14 = out_f_woready_15; // @[RegisterRouter.scala:87:24]
wire _out_T_237 = out_f_woready_15; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_14 = out_f_woready_15 ? _out_T_233 : programBufferMem_14; // @[RegisterRouter.scala:87:24]
wire _out_T_238 = ~out_rimask_15; // @[RegisterRouter.scala:87:24]
wire _out_T_239 = ~out_wimask_15; // @[RegisterRouter.scala:87:24]
wire _out_T_240 = ~out_romask_15; // @[RegisterRouter.scala:87:24]
wire _out_T_241 = ~out_womask_15; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_10 = {programBufferMem_14, _out_prepend_T_10}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_242 = out_prepend_10; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_243 = _out_T_242; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_11 = _out_T_243; // @[RegisterRouter.scala:87:24]
wire out_rimask_16 = |_out_rimask_T_16; // @[RegisterRouter.scala:87:24]
wire out_wimask_16 = &_out_wimask_T_16; // @[RegisterRouter.scala:87:24]
wire out_romask_16 = |_out_romask_T_16; // @[RegisterRouter.scala:87:24]
wire out_womask_16 = &_out_womask_T_16; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_16 = out_rivalid_16 & out_rimask_16; // @[RegisterRouter.scala:87:24]
wire _out_T_245 = out_f_rivalid_16; // @[RegisterRouter.scala:87:24]
assign out_f_roready_16 = out_roready_16 & out_romask_16; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_15 = out_f_roready_16; // @[RegisterRouter.scala:87:24]
wire _out_T_246 = out_f_roready_16; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_16 = out_wivalid_16 & out_wimask_16; // @[RegisterRouter.scala:87:24]
wire _out_T_247 = out_f_wivalid_16; // @[RegisterRouter.scala:87:24]
assign out_f_woready_16 = out_woready_16 & out_womask_16; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_15 = out_f_woready_16; // @[RegisterRouter.scala:87:24]
wire _out_T_248 = out_f_woready_16; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_15 = out_f_woready_16 ? _out_T_244 : programBufferMem_15; // @[RegisterRouter.scala:87:24]
wire _out_T_249 = ~out_rimask_16; // @[RegisterRouter.scala:87:24]
wire _out_T_250 = ~out_wimask_16; // @[RegisterRouter.scala:87:24]
wire _out_T_251 = ~out_romask_16; // @[RegisterRouter.scala:87:24]
wire _out_T_252 = ~out_womask_16; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_11 = {programBufferMem_15, _out_prepend_T_11}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_253 = out_prepend_11; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_254 = _out_T_253; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_out_bits_data_WIRE_1_35 = _out_T_254; // @[MuxLiteral.scala:49:48]
wire out_rimask_17 = |_out_rimask_T_17; // @[RegisterRouter.scala:87:24]
wire out_wimask_17 = &_out_wimask_T_17; // @[RegisterRouter.scala:87:24]
wire out_romask_17 = |_out_romask_T_17; // @[RegisterRouter.scala:87:24]
wire out_womask_17 = &_out_womask_T_17; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_17 = out_rivalid_17 & out_rimask_17; // @[RegisterRouter.scala:87:24]
wire _out_T_256 = out_f_rivalid_17; // @[RegisterRouter.scala:87:24]
assign out_f_roready_17 = out_roready_17 & out_romask_17; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataRdEn_16 = out_f_roready_17; // @[RegisterRouter.scala:87:24]
wire _out_T_257 = out_f_roready_17; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_17 = out_wivalid_17 & out_wimask_17; // @[RegisterRouter.scala:87:24]
wire _out_T_258 = out_f_wivalid_17; // @[RegisterRouter.scala:87:24]
assign out_f_woready_17 = out_woready_17 & out_womask_17; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataWrEnMaybe_16 = out_f_woready_17; // @[RegisterRouter.scala:87:24]
wire _out_T_259 = out_f_woready_17; // @[RegisterRouter.scala:87:24]
assign abstractDataNxt_16 = out_f_woready_17 ? _out_T_255 : abstractDataMem_16; // @[RegisterRouter.scala:87:24]
wire _out_T_260 = ~out_rimask_17; // @[RegisterRouter.scala:87:24]
wire _out_T_261 = ~out_wimask_17; // @[RegisterRouter.scala:87:24]
wire _out_T_262 = ~out_romask_17; // @[RegisterRouter.scala:87:24]
wire _out_T_263 = ~out_womask_17; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_265 = _out_T_264; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_12 = _out_T_265; // @[RegisterRouter.scala:87:24]
wire out_rimask_18 = |_out_rimask_T_18; // @[RegisterRouter.scala:87:24]
wire out_wimask_18 = &_out_wimask_T_18; // @[RegisterRouter.scala:87:24]
wire out_romask_18 = |_out_romask_T_18; // @[RegisterRouter.scala:87:24]
wire out_womask_18 = &_out_womask_T_18; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_18 = out_rivalid_18 & out_rimask_18; // @[RegisterRouter.scala:87:24]
wire _out_T_267 = out_f_rivalid_18; // @[RegisterRouter.scala:87:24]
assign out_f_roready_18 = out_roready_18 & out_romask_18; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataRdEn_17 = out_f_roready_18; // @[RegisterRouter.scala:87:24]
wire _out_T_268 = out_f_roready_18; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_18 = out_wivalid_18 & out_wimask_18; // @[RegisterRouter.scala:87:24]
wire _out_T_269 = out_f_wivalid_18; // @[RegisterRouter.scala:87:24]
assign out_f_woready_18 = out_woready_18 & out_womask_18; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataWrEnMaybe_17 = out_f_woready_18; // @[RegisterRouter.scala:87:24]
wire _out_T_270 = out_f_woready_18; // @[RegisterRouter.scala:87:24]
assign abstractDataNxt_17 = out_f_woready_18 ? _out_T_266 : abstractDataMem_17; // @[RegisterRouter.scala:87:24]
wire _out_T_271 = ~out_rimask_18; // @[RegisterRouter.scala:87:24]
wire _out_T_272 = ~out_wimask_18; // @[RegisterRouter.scala:87:24]
wire _out_T_273 = ~out_romask_18; // @[RegisterRouter.scala:87:24]
wire _out_T_274 = ~out_womask_18; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_12 = {abstractDataMem_17, _out_prepend_T_12}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_275 = out_prepend_12; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_276 = _out_T_275; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_13 = _out_T_276; // @[RegisterRouter.scala:87:24]
wire out_rimask_19 = |_out_rimask_T_19; // @[RegisterRouter.scala:87:24]
wire out_wimask_19 = &_out_wimask_T_19; // @[RegisterRouter.scala:87:24]
wire out_romask_19 = |_out_romask_T_19; // @[RegisterRouter.scala:87:24]
wire out_womask_19 = &_out_womask_T_19; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_19 = out_rivalid_19 & out_rimask_19; // @[RegisterRouter.scala:87:24]
wire _out_T_278 = out_f_rivalid_19; // @[RegisterRouter.scala:87:24]
assign out_f_roready_19 = out_roready_19 & out_romask_19; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataRdEn_18 = out_f_roready_19; // @[RegisterRouter.scala:87:24]
wire _out_T_279 = out_f_roready_19; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_19 = out_wivalid_19 & out_wimask_19; // @[RegisterRouter.scala:87:24]
wire _out_T_280 = out_f_wivalid_19; // @[RegisterRouter.scala:87:24]
assign out_f_woready_19 = out_woready_19 & out_womask_19; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataWrEnMaybe_18 = out_f_woready_19; // @[RegisterRouter.scala:87:24]
wire _out_T_281 = out_f_woready_19; // @[RegisterRouter.scala:87:24]
assign abstractDataNxt_18 = out_f_woready_19 ? _out_T_277 : abstractDataMem_18; // @[RegisterRouter.scala:87:24]
wire _out_T_282 = ~out_rimask_19; // @[RegisterRouter.scala:87:24]
wire _out_T_283 = ~out_wimask_19; // @[RegisterRouter.scala:87:24]
wire _out_T_284 = ~out_romask_19; // @[RegisterRouter.scala:87:24]
wire _out_T_285 = ~out_womask_19; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_13 = {abstractDataMem_18, _out_prepend_T_13}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_286 = out_prepend_13; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_287 = _out_T_286; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_14 = _out_T_287; // @[RegisterRouter.scala:87:24]
wire out_rimask_20 = |_out_rimask_T_20; // @[RegisterRouter.scala:87:24]
wire out_wimask_20 = &_out_wimask_T_20; // @[RegisterRouter.scala:87:24]
wire out_romask_20 = |_out_romask_T_20; // @[RegisterRouter.scala:87:24]
wire out_womask_20 = &_out_womask_T_20; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_20 = out_rivalid_20 & out_rimask_20; // @[RegisterRouter.scala:87:24]
wire _out_T_289 = out_f_rivalid_20; // @[RegisterRouter.scala:87:24]
assign out_f_roready_20 = out_roready_20 & out_romask_20; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataRdEn_19 = out_f_roready_20; // @[RegisterRouter.scala:87:24]
wire _out_T_290 = out_f_roready_20; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_20 = out_wivalid_20 & out_wimask_20; // @[RegisterRouter.scala:87:24]
wire _out_T_291 = out_f_wivalid_20; // @[RegisterRouter.scala:87:24]
assign out_f_woready_20 = out_woready_20 & out_womask_20; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataWrEnMaybe_19 = out_f_woready_20; // @[RegisterRouter.scala:87:24]
wire _out_T_292 = out_f_woready_20; // @[RegisterRouter.scala:87:24]
assign abstractDataNxt_19 = out_f_woready_20 ? _out_T_288 : abstractDataMem_19; // @[RegisterRouter.scala:87:24]
wire _out_T_293 = ~out_rimask_20; // @[RegisterRouter.scala:87:24]
wire _out_T_294 = ~out_wimask_20; // @[RegisterRouter.scala:87:24]
wire _out_T_295 = ~out_romask_20; // @[RegisterRouter.scala:87:24]
wire _out_T_296 = ~out_womask_20; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_14 = {abstractDataMem_19, _out_prepend_T_14}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_297 = out_prepend_14; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_298 = _out_T_297; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_out_bits_data_WIRE_1_8 = _out_T_298; // @[MuxLiteral.scala:49:48]
wire out_rimask_21 = |_out_rimask_T_21; // @[RegisterRouter.scala:87:24]
wire out_wimask_21 = &_out_wimask_T_21; // @[RegisterRouter.scala:87:24]
wire out_romask_21 = |_out_romask_T_21; // @[RegisterRouter.scala:87:24]
wire out_womask_21 = &_out_womask_T_21; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_21 = out_rivalid_21 & out_rimask_21; // @[RegisterRouter.scala:87:24]
wire _out_T_300 = out_f_rivalid_21; // @[RegisterRouter.scala:87:24]
assign out_f_roready_21 = out_roready_21 & out_romask_21; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataRdEn_0 = out_f_roready_21; // @[RegisterRouter.scala:87:24]
wire _out_T_301 = out_f_roready_21; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_21 = out_wivalid_21 & out_wimask_21; // @[RegisterRouter.scala:87:24]
wire _out_T_302 = out_f_wivalid_21; // @[RegisterRouter.scala:87:24]
assign out_f_woready_21 = out_woready_21 & out_womask_21; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataWrEnMaybe_0 = out_f_woready_21; // @[RegisterRouter.scala:87:24]
wire _out_T_303 = out_f_woready_21; // @[RegisterRouter.scala:87:24]
assign abstractDataNxt_0 = out_f_woready_21 ? _out_T_299 : abstractDataMem_0; // @[RegisterRouter.scala:87:24]
wire _out_T_304 = ~out_rimask_21; // @[RegisterRouter.scala:87:24]
wire _out_T_305 = ~out_wimask_21; // @[RegisterRouter.scala:87:24]
wire _out_T_306 = ~out_romask_21; // @[RegisterRouter.scala:87:24]
wire _out_T_307 = ~out_womask_21; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_309 = _out_T_308; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_15 = _out_T_309; // @[RegisterRouter.scala:87:24]
wire out_rimask_22 = |_out_rimask_T_22; // @[RegisterRouter.scala:87:24]
wire out_wimask_22 = &_out_wimask_T_22; // @[RegisterRouter.scala:87:24]
wire out_romask_22 = |_out_romask_T_22; // @[RegisterRouter.scala:87:24]
wire out_womask_22 = &_out_womask_T_22; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_22 = out_rivalid_22 & out_rimask_22; // @[RegisterRouter.scala:87:24]
wire _out_T_311 = out_f_rivalid_22; // @[RegisterRouter.scala:87:24]
assign out_f_roready_22 = out_roready_22 & out_romask_22; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataRdEn_1 = out_f_roready_22; // @[RegisterRouter.scala:87:24]
wire _out_T_312 = out_f_roready_22; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_22 = out_wivalid_22 & out_wimask_22; // @[RegisterRouter.scala:87:24]
wire _out_T_313 = out_f_wivalid_22; // @[RegisterRouter.scala:87:24]
assign out_f_woready_22 = out_woready_22 & out_womask_22; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataWrEnMaybe_1 = out_f_woready_22; // @[RegisterRouter.scala:87:24]
wire _out_T_314 = out_f_woready_22; // @[RegisterRouter.scala:87:24]
assign abstractDataNxt_1 = out_f_woready_22 ? _out_T_310 : abstractDataMem_1; // @[RegisterRouter.scala:87:24]
wire _out_T_315 = ~out_rimask_22; // @[RegisterRouter.scala:87:24]
wire _out_T_316 = ~out_wimask_22; // @[RegisterRouter.scala:87:24]
wire _out_T_317 = ~out_romask_22; // @[RegisterRouter.scala:87:24]
wire _out_T_318 = ~out_womask_22; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_15 = {abstractDataMem_1, _out_prepend_T_15}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_319 = out_prepend_15; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_320 = _out_T_319; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_16 = _out_T_320; // @[RegisterRouter.scala:87:24]
wire out_rimask_23 = |_out_rimask_T_23; // @[RegisterRouter.scala:87:24]
wire out_wimask_23 = &_out_wimask_T_23; // @[RegisterRouter.scala:87:24]
wire out_romask_23 = |_out_romask_T_23; // @[RegisterRouter.scala:87:24]
wire out_womask_23 = &_out_womask_T_23; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_23 = out_rivalid_23 & out_rimask_23; // @[RegisterRouter.scala:87:24]
wire _out_T_322 = out_f_rivalid_23; // @[RegisterRouter.scala:87:24]
assign out_f_roready_23 = out_roready_23 & out_romask_23; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataRdEn_2 = out_f_roready_23; // @[RegisterRouter.scala:87:24]
wire _out_T_323 = out_f_roready_23; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_23 = out_wivalid_23 & out_wimask_23; // @[RegisterRouter.scala:87:24]
wire _out_T_324 = out_f_wivalid_23; // @[RegisterRouter.scala:87:24]
assign out_f_woready_23 = out_woready_23 & out_womask_23; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataWrEnMaybe_2 = out_f_woready_23; // @[RegisterRouter.scala:87:24]
wire _out_T_325 = out_f_woready_23; // @[RegisterRouter.scala:87:24]
assign abstractDataNxt_2 = out_f_woready_23 ? _out_T_321 : abstractDataMem_2; // @[RegisterRouter.scala:87:24]
wire _out_T_326 = ~out_rimask_23; // @[RegisterRouter.scala:87:24]
wire _out_T_327 = ~out_wimask_23; // @[RegisterRouter.scala:87:24]
wire _out_T_328 = ~out_romask_23; // @[RegisterRouter.scala:87:24]
wire _out_T_329 = ~out_womask_23; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_16 = {abstractDataMem_2, _out_prepend_T_16}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_330 = out_prepend_16; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_331 = _out_T_330; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_17 = _out_T_331; // @[RegisterRouter.scala:87:24]
wire out_rimask_24 = |_out_rimask_T_24; // @[RegisterRouter.scala:87:24]
wire out_wimask_24 = &_out_wimask_T_24; // @[RegisterRouter.scala:87:24]
wire out_romask_24 = |_out_romask_T_24; // @[RegisterRouter.scala:87:24]
wire out_womask_24 = &_out_womask_T_24; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_24 = out_rivalid_24 & out_rimask_24; // @[RegisterRouter.scala:87:24]
wire _out_T_333 = out_f_rivalid_24; // @[RegisterRouter.scala:87:24]
assign out_f_roready_24 = out_roready_24 & out_romask_24; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataRdEn_3 = out_f_roready_24; // @[RegisterRouter.scala:87:24]
wire _out_T_334 = out_f_roready_24; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_24 = out_wivalid_24 & out_wimask_24; // @[RegisterRouter.scala:87:24]
wire _out_T_335 = out_f_wivalid_24; // @[RegisterRouter.scala:87:24]
assign out_f_woready_24 = out_woready_24 & out_womask_24; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataWrEnMaybe_3 = out_f_woready_24; // @[RegisterRouter.scala:87:24]
wire _out_T_336 = out_f_woready_24; // @[RegisterRouter.scala:87:24]
assign abstractDataNxt_3 = out_f_woready_24 ? _out_T_332 : abstractDataMem_3; // @[RegisterRouter.scala:87:24]
wire _out_T_337 = ~out_rimask_24; // @[RegisterRouter.scala:87:24]
wire _out_T_338 = ~out_wimask_24; // @[RegisterRouter.scala:87:24]
wire _out_T_339 = ~out_romask_24; // @[RegisterRouter.scala:87:24]
wire _out_T_340 = ~out_womask_24; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_17 = {abstractDataMem_3, _out_prepend_T_17}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_341 = out_prepend_17; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_342 = _out_T_341; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_out_bits_data_WIRE_1_4 = _out_T_342; // @[MuxLiteral.scala:49:48]
wire out_rimask_25 = |_out_rimask_T_25; // @[RegisterRouter.scala:87:24]
wire out_wimask_25 = &_out_wimask_T_25; // @[RegisterRouter.scala:87:24]
wire out_romask_25 = |_out_romask_T_25; // @[RegisterRouter.scala:87:24]
wire out_womask_25 = &_out_womask_T_25; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_25 = out_rivalid_25 & out_rimask_25; // @[RegisterRouter.scala:87:24]
wire _out_T_344 = out_f_rivalid_25; // @[RegisterRouter.scala:87:24]
assign out_f_roready_25 = out_roready_25 & out_romask_25; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_60 = out_f_roready_25; // @[RegisterRouter.scala:87:24]
wire _out_T_345 = out_f_roready_25; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_25 = out_wivalid_25 & out_wimask_25; // @[RegisterRouter.scala:87:24]
wire _out_T_346 = out_f_wivalid_25; // @[RegisterRouter.scala:87:24]
assign out_f_woready_25 = out_woready_25 & out_womask_25; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_60 = out_f_woready_25; // @[RegisterRouter.scala:87:24]
wire _out_T_347 = out_f_woready_25; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_60 = out_f_woready_25 ? _out_T_343 : programBufferMem_60; // @[RegisterRouter.scala:87:24]
wire _out_T_348 = ~out_rimask_25; // @[RegisterRouter.scala:87:24]
wire _out_T_349 = ~out_wimask_25; // @[RegisterRouter.scala:87:24]
wire _out_T_350 = ~out_romask_25; // @[RegisterRouter.scala:87:24]
wire _out_T_351 = ~out_womask_25; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_353 = _out_T_352; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_18 = _out_T_353; // @[RegisterRouter.scala:87:24]
wire out_rimask_26 = |_out_rimask_T_26; // @[RegisterRouter.scala:87:24]
wire out_wimask_26 = &_out_wimask_T_26; // @[RegisterRouter.scala:87:24]
wire out_romask_26 = |_out_romask_T_26; // @[RegisterRouter.scala:87:24]
wire out_womask_26 = &_out_womask_T_26; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_26 = out_rivalid_26 & out_rimask_26; // @[RegisterRouter.scala:87:24]
wire _out_T_355 = out_f_rivalid_26; // @[RegisterRouter.scala:87:24]
assign out_f_roready_26 = out_roready_26 & out_romask_26; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_61 = out_f_roready_26; // @[RegisterRouter.scala:87:24]
wire _out_T_356 = out_f_roready_26; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_26 = out_wivalid_26 & out_wimask_26; // @[RegisterRouter.scala:87:24]
wire _out_T_357 = out_f_wivalid_26; // @[RegisterRouter.scala:87:24]
assign out_f_woready_26 = out_woready_26 & out_womask_26; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_61 = out_f_woready_26; // @[RegisterRouter.scala:87:24]
wire _out_T_358 = out_f_woready_26; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_61 = out_f_woready_26 ? _out_T_354 : programBufferMem_61; // @[RegisterRouter.scala:87:24]
wire _out_T_359 = ~out_rimask_26; // @[RegisterRouter.scala:87:24]
wire _out_T_360 = ~out_wimask_26; // @[RegisterRouter.scala:87:24]
wire _out_T_361 = ~out_romask_26; // @[RegisterRouter.scala:87:24]
wire _out_T_362 = ~out_womask_26; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_18 = {programBufferMem_61, _out_prepend_T_18}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_363 = out_prepend_18; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_364 = _out_T_363; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_19 = _out_T_364; // @[RegisterRouter.scala:87:24]
wire out_rimask_27 = |_out_rimask_T_27; // @[RegisterRouter.scala:87:24]
wire out_wimask_27 = &_out_wimask_T_27; // @[RegisterRouter.scala:87:24]
wire out_romask_27 = |_out_romask_T_27; // @[RegisterRouter.scala:87:24]
wire out_womask_27 = &_out_womask_T_27; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_27 = out_rivalid_27 & out_rimask_27; // @[RegisterRouter.scala:87:24]
wire _out_T_366 = out_f_rivalid_27; // @[RegisterRouter.scala:87:24]
assign out_f_roready_27 = out_roready_27 & out_romask_27; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_62 = out_f_roready_27; // @[RegisterRouter.scala:87:24]
wire _out_T_367 = out_f_roready_27; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_27 = out_wivalid_27 & out_wimask_27; // @[RegisterRouter.scala:87:24]
wire _out_T_368 = out_f_wivalid_27; // @[RegisterRouter.scala:87:24]
assign out_f_woready_27 = out_woready_27 & out_womask_27; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_62 = out_f_woready_27; // @[RegisterRouter.scala:87:24]
wire _out_T_369 = out_f_woready_27; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_62 = out_f_woready_27 ? _out_T_365 : programBufferMem_62; // @[RegisterRouter.scala:87:24]
wire _out_T_370 = ~out_rimask_27; // @[RegisterRouter.scala:87:24]
wire _out_T_371 = ~out_wimask_27; // @[RegisterRouter.scala:87:24]
wire _out_T_372 = ~out_romask_27; // @[RegisterRouter.scala:87:24]
wire _out_T_373 = ~out_womask_27; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_19 = {programBufferMem_62, _out_prepend_T_19}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_374 = out_prepend_19; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_375 = _out_T_374; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_20 = _out_T_375; // @[RegisterRouter.scala:87:24]
wire out_rimask_28 = |_out_rimask_T_28; // @[RegisterRouter.scala:87:24]
wire out_wimask_28 = &_out_wimask_T_28; // @[RegisterRouter.scala:87:24]
wire out_romask_28 = |_out_romask_T_28; // @[RegisterRouter.scala:87:24]
wire out_womask_28 = &_out_womask_T_28; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_28 = out_rivalid_28 & out_rimask_28; // @[RegisterRouter.scala:87:24]
wire _out_T_377 = out_f_rivalid_28; // @[RegisterRouter.scala:87:24]
assign out_f_roready_28 = out_roready_28 & out_romask_28; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_63 = out_f_roready_28; // @[RegisterRouter.scala:87:24]
wire _out_T_378 = out_f_roready_28; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_28 = out_wivalid_28 & out_wimask_28; // @[RegisterRouter.scala:87:24]
wire _out_T_379 = out_f_wivalid_28; // @[RegisterRouter.scala:87:24]
assign out_f_woready_28 = out_woready_28 & out_womask_28; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_63 = out_f_woready_28; // @[RegisterRouter.scala:87:24]
wire _out_T_380 = out_f_woready_28; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_63 = out_f_woready_28 ? _out_T_376 : programBufferMem_63; // @[RegisterRouter.scala:87:24]
wire _out_T_381 = ~out_rimask_28; // @[RegisterRouter.scala:87:24]
wire _out_T_382 = ~out_wimask_28; // @[RegisterRouter.scala:87:24]
wire _out_T_383 = ~out_romask_28; // @[RegisterRouter.scala:87:24]
wire _out_T_384 = ~out_womask_28; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_20 = {programBufferMem_63, _out_prepend_T_20}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_385 = out_prepend_20; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_386 = _out_T_385; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_out_bits_data_WIRE_1_47 = _out_T_386; // @[MuxLiteral.scala:49:48]
wire out_rimask_29 = |_out_rimask_T_29; // @[RegisterRouter.scala:87:24]
wire out_wimask_29 = &_out_wimask_T_29; // @[RegisterRouter.scala:87:24]
wire out_romask_29 = |_out_romask_T_29; // @[RegisterRouter.scala:87:24]
wire out_womask_29 = &_out_womask_T_29; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_29 = out_rivalid_29 & out_rimask_29; // @[RegisterRouter.scala:87:24]
wire _out_T_388 = out_f_rivalid_29; // @[RegisterRouter.scala:87:24]
assign out_f_roready_29 = out_roready_29 & out_romask_29; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataRdEn_24 = out_f_roready_29; // @[RegisterRouter.scala:87:24]
wire _out_T_389 = out_f_roready_29; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_29 = out_wivalid_29 & out_wimask_29; // @[RegisterRouter.scala:87:24]
wire _out_T_390 = out_f_wivalid_29; // @[RegisterRouter.scala:87:24]
assign out_f_woready_29 = out_woready_29 & out_womask_29; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataWrEnMaybe_24 = out_f_woready_29; // @[RegisterRouter.scala:87:24]
wire _out_T_391 = out_f_woready_29; // @[RegisterRouter.scala:87:24]
assign abstractDataNxt_24 = out_f_woready_29 ? _out_T_387 : abstractDataMem_24; // @[RegisterRouter.scala:87:24]
wire _out_T_392 = ~out_rimask_29; // @[RegisterRouter.scala:87:24]
wire _out_T_393 = ~out_wimask_29; // @[RegisterRouter.scala:87:24]
wire _out_T_394 = ~out_romask_29; // @[RegisterRouter.scala:87:24]
wire _out_T_395 = ~out_womask_29; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_397 = _out_T_396; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_21 = _out_T_397; // @[RegisterRouter.scala:87:24]
wire out_rimask_30 = |_out_rimask_T_30; // @[RegisterRouter.scala:87:24]
wire out_wimask_30 = &_out_wimask_T_30; // @[RegisterRouter.scala:87:24]
wire out_romask_30 = |_out_romask_T_30; // @[RegisterRouter.scala:87:24]
wire out_womask_30 = &_out_womask_T_30; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_30 = out_rivalid_30 & out_rimask_30; // @[RegisterRouter.scala:87:24]
wire _out_T_399 = out_f_rivalid_30; // @[RegisterRouter.scala:87:24]
assign out_f_roready_30 = out_roready_30 & out_romask_30; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataRdEn_25 = out_f_roready_30; // @[RegisterRouter.scala:87:24]
wire _out_T_400 = out_f_roready_30; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_30 = out_wivalid_30 & out_wimask_30; // @[RegisterRouter.scala:87:24]
wire _out_T_401 = out_f_wivalid_30; // @[RegisterRouter.scala:87:24]
assign out_f_woready_30 = out_woready_30 & out_womask_30; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataWrEnMaybe_25 = out_f_woready_30; // @[RegisterRouter.scala:87:24]
wire _out_T_402 = out_f_woready_30; // @[RegisterRouter.scala:87:24]
assign abstractDataNxt_25 = out_f_woready_30 ? _out_T_398 : abstractDataMem_25; // @[RegisterRouter.scala:87:24]
wire _out_T_403 = ~out_rimask_30; // @[RegisterRouter.scala:87:24]
wire _out_T_404 = ~out_wimask_30; // @[RegisterRouter.scala:87:24]
wire _out_T_405 = ~out_romask_30; // @[RegisterRouter.scala:87:24]
wire _out_T_406 = ~out_womask_30; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_21 = {abstractDataMem_25, _out_prepend_T_21}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_407 = out_prepend_21; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_408 = _out_T_407; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_22 = _out_T_408; // @[RegisterRouter.scala:87:24]
wire out_rimask_31 = |_out_rimask_T_31; // @[RegisterRouter.scala:87:24]
wire out_wimask_31 = &_out_wimask_T_31; // @[RegisterRouter.scala:87:24]
wire out_romask_31 = |_out_romask_T_31; // @[RegisterRouter.scala:87:24]
wire out_womask_31 = &_out_womask_T_31; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_31 = out_rivalid_31 & out_rimask_31; // @[RegisterRouter.scala:87:24]
wire _out_T_410 = out_f_rivalid_31; // @[RegisterRouter.scala:87:24]
assign out_f_roready_31 = out_roready_31 & out_romask_31; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataRdEn_26 = out_f_roready_31; // @[RegisterRouter.scala:87:24]
wire _out_T_411 = out_f_roready_31; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_31 = out_wivalid_31 & out_wimask_31; // @[RegisterRouter.scala:87:24]
wire _out_T_412 = out_f_wivalid_31; // @[RegisterRouter.scala:87:24]
assign out_f_woready_31 = out_woready_31 & out_womask_31; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataWrEnMaybe_26 = out_f_woready_31; // @[RegisterRouter.scala:87:24]
wire _out_T_413 = out_f_woready_31; // @[RegisterRouter.scala:87:24]
assign abstractDataNxt_26 = out_f_woready_31 ? _out_T_409 : abstractDataMem_26; // @[RegisterRouter.scala:87:24]
wire _out_T_414 = ~out_rimask_31; // @[RegisterRouter.scala:87:24]
wire _out_T_415 = ~out_wimask_31; // @[RegisterRouter.scala:87:24]
wire _out_T_416 = ~out_romask_31; // @[RegisterRouter.scala:87:24]
wire _out_T_417 = ~out_womask_31; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_22 = {abstractDataMem_26, _out_prepend_T_22}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_418 = out_prepend_22; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_419 = _out_T_418; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_23 = _out_T_419; // @[RegisterRouter.scala:87:24]
wire out_rimask_32 = |_out_rimask_T_32; // @[RegisterRouter.scala:87:24]
wire out_wimask_32 = &_out_wimask_T_32; // @[RegisterRouter.scala:87:24]
wire out_romask_32 = |_out_romask_T_32; // @[RegisterRouter.scala:87:24]
wire out_womask_32 = &_out_womask_T_32; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_32 = out_rivalid_32 & out_rimask_32; // @[RegisterRouter.scala:87:24]
wire _out_T_421 = out_f_rivalid_32; // @[RegisterRouter.scala:87:24]
assign out_f_roready_32 = out_roready_32 & out_romask_32; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataRdEn_27 = out_f_roready_32; // @[RegisterRouter.scala:87:24]
wire _out_T_422 = out_f_roready_32; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_32 = out_wivalid_32 & out_wimask_32; // @[RegisterRouter.scala:87:24]
wire _out_T_423 = out_f_wivalid_32; // @[RegisterRouter.scala:87:24]
assign out_f_woready_32 = out_woready_32 & out_womask_32; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataWrEnMaybe_27 = out_f_woready_32; // @[RegisterRouter.scala:87:24]
wire _out_T_424 = out_f_woready_32; // @[RegisterRouter.scala:87:24]
assign abstractDataNxt_27 = out_f_woready_32 ? _out_T_420 : abstractDataMem_27; // @[RegisterRouter.scala:87:24]
wire _out_T_425 = ~out_rimask_32; // @[RegisterRouter.scala:87:24]
wire _out_T_426 = ~out_wimask_32; // @[RegisterRouter.scala:87:24]
wire _out_T_427 = ~out_romask_32; // @[RegisterRouter.scala:87:24]
wire _out_T_428 = ~out_womask_32; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_23 = {abstractDataMem_27, _out_prepend_T_23}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_429 = out_prepend_23; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_430 = _out_T_429; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_out_bits_data_WIRE_1_10 = _out_T_430; // @[MuxLiteral.scala:49:48]
wire _out_rimask_T_33 = out_frontMask[0]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_33 = out_frontMask[0]; // @[RegisterRouter.scala:87:24]
wire out_rimask_33 = _out_rimask_T_33; // @[RegisterRouter.scala:87:24]
wire out_wimask_33 = _out_wimask_T_33; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_33 = out_backMask[0]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_33 = out_backMask[0]; // @[RegisterRouter.scala:87:24]
wire out_romask_33 = _out_romask_T_33; // @[RegisterRouter.scala:87:24]
wire out_womask_33 = _out_womask_T_33; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_33 = out_rivalid_33 & out_rimask_33; // @[RegisterRouter.scala:87:24]
wire _out_T_432 = out_f_rivalid_33; // @[RegisterRouter.scala:87:24]
wire out_f_roready_33 = out_roready_33 & out_romask_33; // @[RegisterRouter.scala:87:24]
wire _out_T_433 = out_f_roready_33; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_33 = out_wivalid_33 & out_wimask_33; // @[RegisterRouter.scala:87:24]
wire out_f_woready_33 = out_woready_33 & out_womask_33; // @[RegisterRouter.scala:87:24]
wire _out_T_431 = out_front_bits_data[0]; // @[RegisterRouter.scala:87:24]
wire _out_T_434 = ~out_rimask_33; // @[RegisterRouter.scala:87:24]
wire _out_T_435 = ~out_wimask_33; // @[RegisterRouter.scala:87:24]
wire _out_T_436 = ~out_romask_33; // @[RegisterRouter.scala:87:24]
wire _out_T_437 = ~out_womask_33; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_34 = out_frontMask[1]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_34 = out_frontMask[1]; // @[RegisterRouter.scala:87:24]
wire out_rimask_34 = _out_rimask_T_34; // @[RegisterRouter.scala:87:24]
wire out_wimask_34 = _out_wimask_T_34; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_34 = out_backMask[1]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_34 = out_backMask[1]; // @[RegisterRouter.scala:87:24]
wire out_romask_34 = _out_romask_T_34; // @[RegisterRouter.scala:87:24]
wire out_womask_34 = _out_womask_T_34; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_34 = out_rivalid_34 & out_rimask_34; // @[RegisterRouter.scala:87:24]
wire _out_T_441 = out_f_rivalid_34; // @[RegisterRouter.scala:87:24]
wire out_f_roready_34 = out_roready_34 & out_romask_34; // @[RegisterRouter.scala:87:24]
wire _out_T_442 = out_f_roready_34; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_34 = out_wivalid_34 & out_wimask_34; // @[RegisterRouter.scala:87:24]
wire out_f_woready_34 = out_woready_34 & out_womask_34; // @[RegisterRouter.scala:87:24]
wire _out_T_440 = out_front_bits_data[1]; // @[RegisterRouter.scala:87:24]
wire _out_T_443 = ~out_rimask_34; // @[RegisterRouter.scala:87:24]
wire _out_T_444 = ~out_wimask_34; // @[RegisterRouter.scala:87:24]
wire _out_T_445 = ~out_romask_34; // @[RegisterRouter.scala:87:24]
wire _out_T_446 = ~out_womask_34; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_35 = out_frontMask[2]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_35 = out_frontMask[2]; // @[RegisterRouter.scala:87:24]
wire out_rimask_35 = _out_rimask_T_35; // @[RegisterRouter.scala:87:24]
wire out_wimask_35 = _out_wimask_T_35; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_35 = out_backMask[2]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_35 = out_backMask[2]; // @[RegisterRouter.scala:87:24]
wire out_romask_35 = _out_romask_T_35; // @[RegisterRouter.scala:87:24]
wire out_womask_35 = _out_womask_T_35; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_35 = out_rivalid_35 & out_rimask_35; // @[RegisterRouter.scala:87:24]
wire _out_T_450 = out_f_rivalid_35; // @[RegisterRouter.scala:87:24]
wire out_f_roready_35 = out_roready_35 & out_romask_35; // @[RegisterRouter.scala:87:24]
wire _out_T_451 = out_f_roready_35; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_35 = out_wivalid_35 & out_wimask_35; // @[RegisterRouter.scala:87:24]
wire out_f_woready_35 = out_woready_35 & out_womask_35; // @[RegisterRouter.scala:87:24]
wire _out_T_449 = out_front_bits_data[2]; // @[RegisterRouter.scala:87:24]
wire _out_T_452 = ~out_rimask_35; // @[RegisterRouter.scala:87:24]
wire _out_T_453 = ~out_wimask_35; // @[RegisterRouter.scala:87:24]
wire _out_T_454 = ~out_romask_35; // @[RegisterRouter.scala:87:24]
wire _out_T_455 = ~out_womask_35; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_36 = out_frontMask[3]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_36 = out_frontMask[3]; // @[RegisterRouter.scala:87:24]
wire out_rimask_36 = _out_rimask_T_36; // @[RegisterRouter.scala:87:24]
wire out_wimask_36 = _out_wimask_T_36; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_36 = out_backMask[3]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_36 = out_backMask[3]; // @[RegisterRouter.scala:87:24]
wire out_romask_36 = _out_romask_T_36; // @[RegisterRouter.scala:87:24]
wire out_womask_36 = _out_womask_T_36; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_36 = out_rivalid_36 & out_rimask_36; // @[RegisterRouter.scala:87:24]
wire _out_T_459 = out_f_rivalid_36; // @[RegisterRouter.scala:87:24]
wire out_f_roready_36 = out_roready_36 & out_romask_36; // @[RegisterRouter.scala:87:24]
wire _out_T_460 = out_f_roready_36; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_36 = out_wivalid_36 & out_wimask_36; // @[RegisterRouter.scala:87:24]
wire out_f_woready_36 = out_woready_36 & out_womask_36; // @[RegisterRouter.scala:87:24]
wire _out_T_458 = out_front_bits_data[3]; // @[RegisterRouter.scala:87:24]
wire _out_T_461 = ~out_rimask_36; // @[RegisterRouter.scala:87:24]
wire _out_T_462 = ~out_wimask_36; // @[RegisterRouter.scala:87:24]
wire _out_T_463 = ~out_romask_36; // @[RegisterRouter.scala:87:24]
wire _out_T_464 = ~out_womask_36; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_37 = out_frontMask[4]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_37 = out_frontMask[4]; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_83 = out_frontMask[4]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_83 = out_frontMask[4]; // @[RegisterRouter.scala:87:24]
wire out_rimask_37 = _out_rimask_T_37; // @[RegisterRouter.scala:87:24]
wire out_wimask_37 = _out_wimask_T_37; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_37 = out_backMask[4]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_37 = out_backMask[4]; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_83 = out_backMask[4]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_83 = out_backMask[4]; // @[RegisterRouter.scala:87:24]
wire out_romask_37 = _out_romask_T_37; // @[RegisterRouter.scala:87:24]
wire out_womask_37 = _out_womask_T_37; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_37 = out_rivalid_37 & out_rimask_37; // @[RegisterRouter.scala:87:24]
wire _out_T_468 = out_f_rivalid_37; // @[RegisterRouter.scala:87:24]
wire out_f_roready_37 = out_roready_37 & out_romask_37; // @[RegisterRouter.scala:87:24]
wire _out_T_469 = out_f_roready_37; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_37 = out_wivalid_37 & out_wimask_37; // @[RegisterRouter.scala:87:24]
wire out_f_woready_37 = out_woready_37 & out_womask_37; // @[RegisterRouter.scala:87:24]
wire _out_T_467 = out_front_bits_data[4]; // @[RegisterRouter.scala:87:24]
wire _out_T_957 = out_front_bits_data[4]; // @[RegisterRouter.scala:87:24]
wire _out_T_470 = ~out_rimask_37; // @[RegisterRouter.scala:87:24]
wire _out_T_471 = ~out_wimask_37; // @[RegisterRouter.scala:87:24]
wire _out_T_472 = ~out_romask_37; // @[RegisterRouter.scala:87:24]
wire _out_T_473 = ~out_womask_37; // @[RegisterRouter.scala:87:24]
wire [6:0] _out_rimask_T_38 = out_frontMask[11:5]; // @[RegisterRouter.scala:87:24]
wire [6:0] _out_wimask_T_38 = out_frontMask[11:5]; // @[RegisterRouter.scala:87:24]
wire out_rimask_38 = |_out_rimask_T_38; // @[RegisterRouter.scala:87:24]
wire out_wimask_38 = &_out_wimask_T_38; // @[RegisterRouter.scala:87:24]
wire [6:0] _out_romask_T_38 = out_backMask[11:5]; // @[RegisterRouter.scala:87:24]
wire [6:0] _out_womask_T_38 = out_backMask[11:5]; // @[RegisterRouter.scala:87:24]
wire out_romask_38 = |_out_romask_T_38; // @[RegisterRouter.scala:87:24]
wire out_womask_38 = &_out_womask_T_38; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_38 = out_rivalid_38 & out_rimask_38; // @[RegisterRouter.scala:87:24]
wire _out_T_477 = out_f_rivalid_38; // @[RegisterRouter.scala:87:24]
wire out_f_roready_38 = out_roready_38 & out_romask_38; // @[RegisterRouter.scala:87:24]
wire _out_T_478 = out_f_roready_38; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_38 = out_wivalid_38 & out_wimask_38; // @[RegisterRouter.scala:87:24]
wire out_f_woready_38 = out_woready_38 & out_womask_38; // @[RegisterRouter.scala:87:24]
wire [6:0] _out_T_476 = out_front_bits_data[11:5]; // @[RegisterRouter.scala:87:24]
wire _out_T_479 = ~out_rimask_38; // @[RegisterRouter.scala:87:24]
wire _out_T_480 = ~out_wimask_38; // @[RegisterRouter.scala:87:24]
wire _out_T_481 = ~out_romask_38; // @[RegisterRouter.scala:87:24]
wire _out_T_482 = ~out_womask_38; // @[RegisterRouter.scala:87:24]
wire [2:0] _out_rimask_T_39 = out_frontMask[14:12]; // @[RegisterRouter.scala:87:24]
wire [2:0] _out_wimask_T_39 = out_frontMask[14:12]; // @[RegisterRouter.scala:87:24]
wire out_rimask_39 = |_out_rimask_T_39; // @[RegisterRouter.scala:87:24]
wire out_wimask_39 = &_out_wimask_T_39; // @[RegisterRouter.scala:87:24]
wire [2:0] _out_romask_T_39 = out_backMask[14:12]; // @[RegisterRouter.scala:87:24]
wire [2:0] _out_womask_T_39 = out_backMask[14:12]; // @[RegisterRouter.scala:87:24]
wire out_romask_39 = |_out_romask_T_39; // @[RegisterRouter.scala:87:24]
wire out_womask_39 = &_out_womask_T_39; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_39 = out_rivalid_39 & out_rimask_39; // @[RegisterRouter.scala:87:24]
wire _out_T_486 = out_f_rivalid_39; // @[RegisterRouter.scala:87:24]
wire out_f_roready_39 = out_roready_39 & out_romask_39; // @[RegisterRouter.scala:87:24]
wire _out_T_487 = out_f_roready_39; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_39 = out_wivalid_39 & out_wimask_39; // @[RegisterRouter.scala:87:24]
wire _out_T_488 = out_f_wivalid_39; // @[RegisterRouter.scala:87:24]
assign out_f_woready_39 = out_woready_39 & out_womask_39; // @[RegisterRouter.scala:87:24]
assign sberrorWrEn = out_f_woready_39; // @[RegisterRouter.scala:87:24]
wire _out_T_489 = out_f_woready_39; // @[RegisterRouter.scala:87:24]
assign _out_T_485 = out_front_bits_data[14:12]; // @[RegisterRouter.scala:87:24]
assign SBCSWrData_sberror = _out_T_485; // @[RegisterRouter.scala:87:24]
wire _out_T_490 = ~out_rimask_39; // @[RegisterRouter.scala:87:24]
wire _out_T_491 = ~out_wimask_39; // @[RegisterRouter.scala:87:24]
wire _out_T_492 = ~out_romask_39; // @[RegisterRouter.scala:87:24]
wire _out_T_493 = ~out_womask_39; // @[RegisterRouter.scala:87:24]
wire [14:0] out_prepend_29 = {SBCSRdData_sberror, 12'h40F}; // @[RegisterRouter.scala:87:24]
wire [14:0] _out_T_494 = out_prepend_29; // @[RegisterRouter.scala:87:24]
wire [14:0] _out_T_495 = _out_T_494; // @[RegisterRouter.scala:87:24]
wire [14:0] _out_prepend_T_30 = _out_T_495; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_40 = out_frontMask[15]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_40 = out_frontMask[15]; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_94 = out_frontMask[15]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_94 = out_frontMask[15]; // @[RegisterRouter.scala:87:24]
wire out_rimask_40 = _out_rimask_T_40; // @[RegisterRouter.scala:87:24]
wire out_wimask_40 = _out_wimask_T_40; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_40 = out_backMask[15]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_40 = out_backMask[15]; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_94 = out_backMask[15]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_94 = out_backMask[15]; // @[RegisterRouter.scala:87:24]
wire out_romask_40 = _out_romask_T_40; // @[RegisterRouter.scala:87:24]
wire out_womask_40 = _out_womask_T_40; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_40 = out_rivalid_40 & out_rimask_40; // @[RegisterRouter.scala:87:24]
wire _out_T_497 = out_f_rivalid_40; // @[RegisterRouter.scala:87:24]
wire out_f_roready_40 = out_roready_40 & out_romask_40; // @[RegisterRouter.scala:87:24]
wire _out_T_498 = out_f_roready_40; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_40 = out_wivalid_40 & out_wimask_40; // @[RegisterRouter.scala:87:24]
wire _out_T_499 = out_f_wivalid_40; // @[RegisterRouter.scala:87:24]
assign out_f_woready_40 = out_woready_40 & out_womask_40; // @[RegisterRouter.scala:87:24]
assign sbreadondataWrEn = out_f_woready_40; // @[RegisterRouter.scala:87:24]
wire _out_T_500 = out_f_woready_40; // @[RegisterRouter.scala:87:24]
assign _out_T_496 = out_front_bits_data[15]; // @[RegisterRouter.scala:87:24]
wire _out_T_1056 = out_front_bits_data[15]; // @[RegisterRouter.scala:87:24]
assign SBCSWrData_sbreadondata = _out_T_496; // @[RegisterRouter.scala:87:24]
wire _out_T_501 = ~out_rimask_40; // @[RegisterRouter.scala:87:24]
wire _out_T_502 = ~out_wimask_40; // @[RegisterRouter.scala:87:24]
wire _out_T_503 = ~out_romask_40; // @[RegisterRouter.scala:87:24]
wire _out_T_504 = ~out_womask_40; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_30 = {SBCSRdData_sbreadondata, _out_prepend_T_30}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_505 = out_prepend_30; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_506 = _out_T_505; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_31 = _out_T_506; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_41 = out_frontMask[16]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_41 = out_frontMask[16]; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_95 = out_frontMask[16]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_95 = out_frontMask[16]; // @[RegisterRouter.scala:87:24]
wire out_rimask_41 = _out_rimask_T_41; // @[RegisterRouter.scala:87:24]
wire out_wimask_41 = _out_wimask_T_41; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_41 = out_backMask[16]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_41 = out_backMask[16]; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_95 = out_backMask[16]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_95 = out_backMask[16]; // @[RegisterRouter.scala:87:24]
wire out_romask_41 = _out_romask_T_41; // @[RegisterRouter.scala:87:24]
wire out_womask_41 = _out_womask_T_41; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_41 = out_rivalid_41 & out_rimask_41; // @[RegisterRouter.scala:87:24]
wire _out_T_508 = out_f_rivalid_41; // @[RegisterRouter.scala:87:24]
wire out_f_roready_41 = out_roready_41 & out_romask_41; // @[RegisterRouter.scala:87:24]
wire _out_T_509 = out_f_roready_41; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_41 = out_wivalid_41 & out_wimask_41; // @[RegisterRouter.scala:87:24]
wire _out_T_510 = out_f_wivalid_41; // @[RegisterRouter.scala:87:24]
assign out_f_woready_41 = out_woready_41 & out_womask_41; // @[RegisterRouter.scala:87:24]
assign sbautoincrementWrEn = out_f_woready_41; // @[RegisterRouter.scala:87:24]
wire _out_T_511 = out_f_woready_41; // @[RegisterRouter.scala:87:24]
assign _out_T_507 = out_front_bits_data[16]; // @[RegisterRouter.scala:87:24]
wire _out_T_1065 = out_front_bits_data[16]; // @[RegisterRouter.scala:87:24]
assign SBCSWrData_sbautoincrement = _out_T_507; // @[RegisterRouter.scala:87:24]
wire _out_T_512 = ~out_rimask_41; // @[RegisterRouter.scala:87:24]
wire _out_T_513 = ~out_wimask_41; // @[RegisterRouter.scala:87:24]
wire _out_T_514 = ~out_romask_41; // @[RegisterRouter.scala:87:24]
wire _out_T_515 = ~out_womask_41; // @[RegisterRouter.scala:87:24]
wire [16:0] out_prepend_31 = {SBCSRdData_sbautoincrement, _out_prepend_T_31}; // @[RegisterRouter.scala:87:24]
wire [16:0] _out_T_516 = out_prepend_31; // @[RegisterRouter.scala:87:24]
wire [16:0] _out_T_517 = _out_T_516; // @[RegisterRouter.scala:87:24]
wire [16:0] _out_prepend_T_32 = _out_T_517; // @[RegisterRouter.scala:87:24]
wire [2:0] _out_rimask_T_42 = out_frontMask[19:17]; // @[RegisterRouter.scala:87:24]
wire [2:0] _out_wimask_T_42 = out_frontMask[19:17]; // @[RegisterRouter.scala:87:24]
wire out_rimask_42 = |_out_rimask_T_42; // @[RegisterRouter.scala:87:24]
wire out_wimask_42 = &_out_wimask_T_42; // @[RegisterRouter.scala:87:24]
wire [2:0] _out_romask_T_42 = out_backMask[19:17]; // @[RegisterRouter.scala:87:24]
wire [2:0] _out_womask_T_42 = out_backMask[19:17]; // @[RegisterRouter.scala:87:24]
wire out_romask_42 = |_out_romask_T_42; // @[RegisterRouter.scala:87:24]
wire out_womask_42 = &_out_womask_T_42; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_42 = out_rivalid_42 & out_rimask_42; // @[RegisterRouter.scala:87:24]
wire _out_T_519 = out_f_rivalid_42; // @[RegisterRouter.scala:87:24]
wire out_f_roready_42 = out_roready_42 & out_romask_42; // @[RegisterRouter.scala:87:24]
wire _out_T_520 = out_f_roready_42; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_42 = out_wivalid_42 & out_wimask_42; // @[RegisterRouter.scala:87:24]
wire _out_T_521 = out_f_wivalid_42; // @[RegisterRouter.scala:87:24]
assign out_f_woready_42 = out_woready_42 & out_womask_42; // @[RegisterRouter.scala:87:24]
assign sbaccessWrEn = out_f_woready_42; // @[RegisterRouter.scala:87:24]
wire _out_T_522 = out_f_woready_42; // @[RegisterRouter.scala:87:24]
assign _out_T_518 = out_front_bits_data[19:17]; // @[RegisterRouter.scala:87:24]
assign SBCSWrData_sbaccess = _out_T_518; // @[RegisterRouter.scala:87:24]
wire _out_T_523 = ~out_rimask_42; // @[RegisterRouter.scala:87:24]
wire _out_T_524 = ~out_wimask_42; // @[RegisterRouter.scala:87:24]
wire _out_T_525 = ~out_romask_42; // @[RegisterRouter.scala:87:24]
wire _out_T_526 = ~out_womask_42; // @[RegisterRouter.scala:87:24]
wire [19:0] out_prepend_32 = {SBCSRdData_sbaccess, _out_prepend_T_32}; // @[RegisterRouter.scala:87:24]
wire [19:0] _out_T_527 = out_prepend_32; // @[RegisterRouter.scala:87:24]
wire [19:0] _out_T_528 = _out_T_527; // @[RegisterRouter.scala:87:24]
wire [19:0] _out_prepend_T_33 = _out_T_528; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_43 = out_frontMask[20]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_43 = out_frontMask[20]; // @[RegisterRouter.scala:87:24]
wire out_rimask_43 = _out_rimask_T_43; // @[RegisterRouter.scala:87:24]
wire out_wimask_43 = _out_wimask_T_43; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_43 = out_backMask[20]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_43 = out_backMask[20]; // @[RegisterRouter.scala:87:24]
wire out_romask_43 = _out_romask_T_43; // @[RegisterRouter.scala:87:24]
wire out_womask_43 = _out_womask_T_43; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_43 = out_rivalid_43 & out_rimask_43; // @[RegisterRouter.scala:87:24]
wire _out_T_530 = out_f_rivalid_43; // @[RegisterRouter.scala:87:24]
wire out_f_roready_43 = out_roready_43 & out_romask_43; // @[RegisterRouter.scala:87:24]
wire _out_T_531 = out_f_roready_43; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_43 = out_wivalid_43 & out_wimask_43; // @[RegisterRouter.scala:87:24]
wire _out_T_532 = out_f_wivalid_43; // @[RegisterRouter.scala:87:24]
assign out_f_woready_43 = out_woready_43 & out_womask_43; // @[RegisterRouter.scala:87:24]
assign sbreadonaddrWrEn = out_f_woready_43; // @[RegisterRouter.scala:87:24]
wire _out_T_533 = out_f_woready_43; // @[RegisterRouter.scala:87:24]
assign _out_T_529 = out_front_bits_data[20]; // @[RegisterRouter.scala:87:24]
assign SBCSWrData_sbreadonaddr = _out_T_529; // @[RegisterRouter.scala:87:24]
wire _out_T_534 = ~out_rimask_43; // @[RegisterRouter.scala:87:24]
wire _out_T_535 = ~out_wimask_43; // @[RegisterRouter.scala:87:24]
wire _out_T_536 = ~out_romask_43; // @[RegisterRouter.scala:87:24]
wire _out_T_537 = ~out_womask_43; // @[RegisterRouter.scala:87:24]
wire [20:0] out_prepend_33 = {SBCSRdData_sbreadonaddr, _out_prepend_T_33}; // @[RegisterRouter.scala:87:24]
wire [20:0] _out_T_538 = out_prepend_33; // @[RegisterRouter.scala:87:24]
wire [20:0] _out_T_539 = _out_T_538; // @[RegisterRouter.scala:87:24]
wire [20:0] _out_prepend_T_34 = _out_T_539; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_44 = out_frontMask[21]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_44 = out_frontMask[21]; // @[RegisterRouter.scala:87:24]
wire out_rimask_44 = _out_rimask_T_44; // @[RegisterRouter.scala:87:24]
wire out_wimask_44 = _out_wimask_T_44; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_44 = out_backMask[21]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_44 = out_backMask[21]; // @[RegisterRouter.scala:87:24]
wire out_romask_44 = _out_romask_T_44; // @[RegisterRouter.scala:87:24]
wire out_womask_44 = _out_womask_T_44; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_44 = out_rivalid_44 & out_rimask_44; // @[RegisterRouter.scala:87:24]
wire _out_T_541 = out_f_rivalid_44; // @[RegisterRouter.scala:87:24]
wire out_f_roready_44 = out_roready_44 & out_romask_44; // @[RegisterRouter.scala:87:24]
wire _out_T_542 = out_f_roready_44; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_44 = out_wivalid_44 & out_wimask_44; // @[RegisterRouter.scala:87:24]
wire out_f_woready_44 = out_woready_44 & out_womask_44; // @[RegisterRouter.scala:87:24]
wire _out_T_540 = out_front_bits_data[21]; // @[RegisterRouter.scala:87:24]
wire _out_T_543 = ~out_rimask_44; // @[RegisterRouter.scala:87:24]
wire _out_T_544 = ~out_wimask_44; // @[RegisterRouter.scala:87:24]
wire _out_T_545 = ~out_romask_44; // @[RegisterRouter.scala:87:24]
wire _out_T_546 = ~out_womask_44; // @[RegisterRouter.scala:87:24]
wire [21:0] out_prepend_34 = {SBCSRdData_sbbusy, _out_prepend_T_34}; // @[RegisterRouter.scala:87:24]
wire [21:0] _out_T_547 = out_prepend_34; // @[RegisterRouter.scala:87:24]
wire [21:0] _out_T_548 = _out_T_547; // @[RegisterRouter.scala:87:24]
wire [21:0] _out_prepend_T_35 = _out_T_548; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_45 = out_frontMask[22]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_45 = out_frontMask[22]; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_100 = out_frontMask[22]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_100 = out_frontMask[22]; // @[RegisterRouter.scala:87:24]
wire out_rimask_45 = _out_rimask_T_45; // @[RegisterRouter.scala:87:24]
wire out_wimask_45 = _out_wimask_T_45; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_45 = out_backMask[22]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_45 = out_backMask[22]; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_100 = out_backMask[22]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_100 = out_backMask[22]; // @[RegisterRouter.scala:87:24]
wire out_romask_45 = _out_romask_T_45; // @[RegisterRouter.scala:87:24]
wire out_womask_45 = _out_womask_T_45; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_45 = out_rivalid_45 & out_rimask_45; // @[RegisterRouter.scala:87:24]
wire _out_T_550 = out_f_rivalid_45; // @[RegisterRouter.scala:87:24]
wire out_f_roready_45 = out_roready_45 & out_romask_45; // @[RegisterRouter.scala:87:24]
wire _out_T_551 = out_f_roready_45; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_45 = out_wivalid_45 & out_wimask_45; // @[RegisterRouter.scala:87:24]
wire _out_T_552 = out_f_wivalid_45; // @[RegisterRouter.scala:87:24]
assign out_f_woready_45 = out_woready_45 & out_womask_45; // @[RegisterRouter.scala:87:24]
assign sbbusyerrorWrEn = out_f_woready_45; // @[RegisterRouter.scala:87:24]
wire _out_T_553 = out_f_woready_45; // @[RegisterRouter.scala:87:24]
assign _out_T_549 = out_front_bits_data[22]; // @[RegisterRouter.scala:87:24]
wire _out_T_1110 = out_front_bits_data[22]; // @[RegisterRouter.scala:87:24]
assign SBCSWrData_sbbusyerror = _out_T_549; // @[RegisterRouter.scala:87:24]
wire _out_T_554 = ~out_rimask_45; // @[RegisterRouter.scala:87:24]
wire _out_T_555 = ~out_wimask_45; // @[RegisterRouter.scala:87:24]
wire _out_T_556 = ~out_romask_45; // @[RegisterRouter.scala:87:24]
wire _out_T_557 = ~out_womask_45; // @[RegisterRouter.scala:87:24]
wire [22:0] out_prepend_35 = {SBCSRdData_sbbusyerror, _out_prepend_T_35}; // @[RegisterRouter.scala:87:24]
wire [22:0] _out_T_558 = out_prepend_35; // @[RegisterRouter.scala:87:24]
wire [22:0] _out_T_559 = _out_T_558; // @[RegisterRouter.scala:87:24]
wire [22:0] _out_prepend_T_36 = _out_T_559; // @[RegisterRouter.scala:87:24]
wire [5:0] _out_rimask_T_46 = out_frontMask[28:23]; // @[RegisterRouter.scala:87:24]
wire [5:0] _out_wimask_T_46 = out_frontMask[28:23]; // @[RegisterRouter.scala:87:24]
wire out_rimask_46 = |_out_rimask_T_46; // @[RegisterRouter.scala:87:24]
wire out_wimask_46 = &_out_wimask_T_46; // @[RegisterRouter.scala:87:24]
wire [5:0] _out_romask_T_46 = out_backMask[28:23]; // @[RegisterRouter.scala:87:24]
wire [5:0] _out_womask_T_46 = out_backMask[28:23]; // @[RegisterRouter.scala:87:24]
wire out_romask_46 = |_out_romask_T_46; // @[RegisterRouter.scala:87:24]
wire out_womask_46 = &_out_womask_T_46; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_46 = out_rivalid_46 & out_rimask_46; // @[RegisterRouter.scala:87:24]
wire _out_T_561 = out_f_rivalid_46; // @[RegisterRouter.scala:87:24]
wire out_f_roready_46 = out_roready_46 & out_romask_46; // @[RegisterRouter.scala:87:24]
wire _out_T_562 = out_f_roready_46; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_46 = out_wivalid_46 & out_wimask_46; // @[RegisterRouter.scala:87:24]
wire out_f_woready_46 = out_woready_46 & out_womask_46; // @[RegisterRouter.scala:87:24]
wire [5:0] _out_T_560 = out_front_bits_data[28:23]; // @[RegisterRouter.scala:87:24]
wire _out_T_563 = ~out_rimask_46; // @[RegisterRouter.scala:87:24]
wire _out_T_564 = ~out_wimask_46; // @[RegisterRouter.scala:87:24]
wire _out_T_565 = ~out_romask_46; // @[RegisterRouter.scala:87:24]
wire _out_T_566 = ~out_womask_46; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_36 = {1'h0, _out_prepend_T_36}; // @[RegisterRouter.scala:87:24]
wire [28:0] _out_T_567 = {5'h0, out_prepend_36}; // @[RegisterRouter.scala:87:24]
wire [28:0] _out_T_568 = _out_T_567; // @[RegisterRouter.scala:87:24]
wire [28:0] _out_prepend_T_37 = _out_T_568; // @[RegisterRouter.scala:87:24]
wire [2:0] _out_rimask_T_47 = out_frontMask[31:29]; // @[RegisterRouter.scala:87:24]
wire [2:0] _out_wimask_T_47 = out_frontMask[31:29]; // @[RegisterRouter.scala:87:24]
wire out_rimask_47 = |_out_rimask_T_47; // @[RegisterRouter.scala:87:24]
wire out_wimask_47 = &_out_wimask_T_47; // @[RegisterRouter.scala:87:24]
wire [2:0] _out_romask_T_47 = out_backMask[31:29]; // @[RegisterRouter.scala:87:24]
wire [2:0] _out_womask_T_47 = out_backMask[31:29]; // @[RegisterRouter.scala:87:24]
wire out_romask_47 = |_out_romask_T_47; // @[RegisterRouter.scala:87:24]
wire out_womask_47 = &_out_womask_T_47; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_47 = out_rivalid_47 & out_rimask_47; // @[RegisterRouter.scala:87:24]
wire _out_T_570 = out_f_rivalid_47; // @[RegisterRouter.scala:87:24]
wire out_f_roready_47 = out_roready_47 & out_romask_47; // @[RegisterRouter.scala:87:24]
wire _out_T_571 = out_f_roready_47; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_47 = out_wivalid_47 & out_wimask_47; // @[RegisterRouter.scala:87:24]
wire out_f_woready_47 = out_woready_47 & out_womask_47; // @[RegisterRouter.scala:87:24]
wire [2:0] _out_T_569 = out_front_bits_data[31:29]; // @[RegisterRouter.scala:87:24]
wire _out_T_572 = ~out_rimask_47; // @[RegisterRouter.scala:87:24]
wire _out_T_573 = ~out_wimask_47; // @[RegisterRouter.scala:87:24]
wire _out_T_574 = ~out_romask_47; // @[RegisterRouter.scala:87:24]
wire _out_T_575 = ~out_womask_47; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_37 = {3'h1, _out_prepend_T_37}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_576 = out_prepend_37; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_577 = _out_T_576; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_out_bits_data_WIRE_1_56 = _out_T_577; // @[MuxLiteral.scala:49:48]
wire out_rimask_48 = |_out_rimask_T_48; // @[RegisterRouter.scala:87:24]
wire out_wimask_48 = &_out_wimask_T_48; // @[RegisterRouter.scala:87:24]
wire out_romask_48 = |_out_romask_T_48; // @[RegisterRouter.scala:87:24]
wire out_womask_48 = &_out_womask_T_48; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_48 = out_rivalid_48 & out_rimask_48; // @[RegisterRouter.scala:87:24]
wire _out_T_579 = out_f_rivalid_48; // @[RegisterRouter.scala:87:24]
assign out_f_roready_48 = out_roready_48 & out_romask_48; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_40 = out_f_roready_48; // @[RegisterRouter.scala:87:24]
wire _out_T_580 = out_f_roready_48; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_48 = out_wivalid_48 & out_wimask_48; // @[RegisterRouter.scala:87:24]
wire _out_T_581 = out_f_wivalid_48; // @[RegisterRouter.scala:87:24]
assign out_f_woready_48 = out_woready_48 & out_womask_48; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_40 = out_f_woready_48; // @[RegisterRouter.scala:87:24]
wire _out_T_582 = out_f_woready_48; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_40 = out_f_woready_48 ? _out_T_578 : programBufferMem_40; // @[RegisterRouter.scala:87:24]
wire _out_T_583 = ~out_rimask_48; // @[RegisterRouter.scala:87:24]
wire _out_T_584 = ~out_wimask_48; // @[RegisterRouter.scala:87:24]
wire _out_T_585 = ~out_romask_48; // @[RegisterRouter.scala:87:24]
wire _out_T_586 = ~out_womask_48; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_588 = _out_T_587; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_38 = _out_T_588; // @[RegisterRouter.scala:87:24]
wire out_rimask_49 = |_out_rimask_T_49; // @[RegisterRouter.scala:87:24]
wire out_wimask_49 = &_out_wimask_T_49; // @[RegisterRouter.scala:87:24]
wire out_romask_49 = |_out_romask_T_49; // @[RegisterRouter.scala:87:24]
wire out_womask_49 = &_out_womask_T_49; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_49 = out_rivalid_49 & out_rimask_49; // @[RegisterRouter.scala:87:24]
wire _out_T_590 = out_f_rivalid_49; // @[RegisterRouter.scala:87:24]
assign out_f_roready_49 = out_roready_49 & out_romask_49; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_41 = out_f_roready_49; // @[RegisterRouter.scala:87:24]
wire _out_T_591 = out_f_roready_49; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_49 = out_wivalid_49 & out_wimask_49; // @[RegisterRouter.scala:87:24]
wire _out_T_592 = out_f_wivalid_49; // @[RegisterRouter.scala:87:24]
assign out_f_woready_49 = out_woready_49 & out_womask_49; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_41 = out_f_woready_49; // @[RegisterRouter.scala:87:24]
wire _out_T_593 = out_f_woready_49; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_41 = out_f_woready_49 ? _out_T_589 : programBufferMem_41; // @[RegisterRouter.scala:87:24]
wire _out_T_594 = ~out_rimask_49; // @[RegisterRouter.scala:87:24]
wire _out_T_595 = ~out_wimask_49; // @[RegisterRouter.scala:87:24]
wire _out_T_596 = ~out_romask_49; // @[RegisterRouter.scala:87:24]
wire _out_T_597 = ~out_womask_49; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_38 = {programBufferMem_41, _out_prepend_T_38}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_598 = out_prepend_38; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_599 = _out_T_598; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_39 = _out_T_599; // @[RegisterRouter.scala:87:24]
wire out_rimask_50 = |_out_rimask_T_50; // @[RegisterRouter.scala:87:24]
wire out_wimask_50 = &_out_wimask_T_50; // @[RegisterRouter.scala:87:24]
wire out_romask_50 = |_out_romask_T_50; // @[RegisterRouter.scala:87:24]
wire out_womask_50 = &_out_womask_T_50; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_50 = out_rivalid_50 & out_rimask_50; // @[RegisterRouter.scala:87:24]
wire _out_T_601 = out_f_rivalid_50; // @[RegisterRouter.scala:87:24]
assign out_f_roready_50 = out_roready_50 & out_romask_50; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_42 = out_f_roready_50; // @[RegisterRouter.scala:87:24]
wire _out_T_602 = out_f_roready_50; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_50 = out_wivalid_50 & out_wimask_50; // @[RegisterRouter.scala:87:24]
wire _out_T_603 = out_f_wivalid_50; // @[RegisterRouter.scala:87:24]
assign out_f_woready_50 = out_woready_50 & out_womask_50; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_42 = out_f_woready_50; // @[RegisterRouter.scala:87:24]
wire _out_T_604 = out_f_woready_50; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_42 = out_f_woready_50 ? _out_T_600 : programBufferMem_42; // @[RegisterRouter.scala:87:24]
wire _out_T_605 = ~out_rimask_50; // @[RegisterRouter.scala:87:24]
wire _out_T_606 = ~out_wimask_50; // @[RegisterRouter.scala:87:24]
wire _out_T_607 = ~out_romask_50; // @[RegisterRouter.scala:87:24]
wire _out_T_608 = ~out_womask_50; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_39 = {programBufferMem_42, _out_prepend_T_39}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_609 = out_prepend_39; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_610 = _out_T_609; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_40 = _out_T_610; // @[RegisterRouter.scala:87:24]
wire out_rimask_51 = |_out_rimask_T_51; // @[RegisterRouter.scala:87:24]
wire out_wimask_51 = &_out_wimask_T_51; // @[RegisterRouter.scala:87:24]
wire out_romask_51 = |_out_romask_T_51; // @[RegisterRouter.scala:87:24]
wire out_womask_51 = &_out_womask_T_51; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_51 = out_rivalid_51 & out_rimask_51; // @[RegisterRouter.scala:87:24]
wire _out_T_612 = out_f_rivalid_51; // @[RegisterRouter.scala:87:24]
assign out_f_roready_51 = out_roready_51 & out_romask_51; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_43 = out_f_roready_51; // @[RegisterRouter.scala:87:24]
wire _out_T_613 = out_f_roready_51; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_51 = out_wivalid_51 & out_wimask_51; // @[RegisterRouter.scala:87:24]
wire _out_T_614 = out_f_wivalid_51; // @[RegisterRouter.scala:87:24]
assign out_f_woready_51 = out_woready_51 & out_womask_51; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_43 = out_f_woready_51; // @[RegisterRouter.scala:87:24]
wire _out_T_615 = out_f_woready_51; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_43 = out_f_woready_51 ? _out_T_611 : programBufferMem_43; // @[RegisterRouter.scala:87:24]
wire _out_T_616 = ~out_rimask_51; // @[RegisterRouter.scala:87:24]
wire _out_T_617 = ~out_wimask_51; // @[RegisterRouter.scala:87:24]
wire _out_T_618 = ~out_romask_51; // @[RegisterRouter.scala:87:24]
wire _out_T_619 = ~out_womask_51; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_40 = {programBufferMem_43, _out_prepend_T_40}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_620 = out_prepend_40; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_621 = _out_T_620; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_out_bits_data_WIRE_1_42 = _out_T_621; // @[MuxLiteral.scala:49:48]
wire out_rimask_52 = |_out_rimask_T_52; // @[RegisterRouter.scala:87:24]
wire out_wimask_52 = &_out_wimask_T_52; // @[RegisterRouter.scala:87:24]
wire out_romask_52 = |_out_romask_T_52; // @[RegisterRouter.scala:87:24]
wire out_womask_52 = &_out_womask_T_52; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_52 = out_rivalid_52 & out_rimask_52; // @[RegisterRouter.scala:87:24]
wire _out_T_623 = out_f_rivalid_52; // @[RegisterRouter.scala:87:24]
wire out_f_roready_52 = out_roready_52 & out_romask_52; // @[RegisterRouter.scala:87:24]
wire _out_T_624 = out_f_roready_52; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_52 = out_wivalid_52 & out_wimask_52; // @[RegisterRouter.scala:87:24]
wire _out_T_625 = out_f_wivalid_52; // @[RegisterRouter.scala:87:24]
assign out_f_woready_52 = out_woready_52 & out_womask_52; // @[RegisterRouter.scala:87:24]
assign autoexecdataWrEnMaybe = out_f_woready_52; // @[RegisterRouter.scala:87:24]
wire _out_T_626 = out_f_woready_52; // @[RegisterRouter.scala:87:24]
assign ABSTRACTAUTOWrData_autoexecdata = {4'h0, _out_T_622}; // @[RegisterRouter.scala:87:24]
wire _out_T_627 = ~out_rimask_52; // @[RegisterRouter.scala:87:24]
wire _out_T_628 = ~out_wimask_52; // @[RegisterRouter.scala:87:24]
wire _out_T_629 = ~out_romask_52; // @[RegisterRouter.scala:87:24]
wire _out_T_630 = ~out_womask_52; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_632 = _out_T_631[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_41 = _out_T_632; // @[RegisterRouter.scala:87:24]
wire out_rimask_53 = |_out_rimask_T_53; // @[RegisterRouter.scala:87:24]
wire out_wimask_53 = &_out_wimask_T_53; // @[RegisterRouter.scala:87:24]
wire out_romask_53 = |_out_romask_T_53; // @[RegisterRouter.scala:87:24]
wire out_womask_53 = &_out_womask_T_53; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_53 = out_rivalid_53 & out_rimask_53; // @[RegisterRouter.scala:87:24]
wire _out_T_634 = out_f_rivalid_53; // @[RegisterRouter.scala:87:24]
wire out_f_roready_53 = out_roready_53 & out_romask_53; // @[RegisterRouter.scala:87:24]
wire _out_T_635 = out_f_roready_53; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_53 = out_wivalid_53 & out_wimask_53; // @[RegisterRouter.scala:87:24]
wire out_f_woready_53 = out_woready_53 & out_womask_53; // @[RegisterRouter.scala:87:24]
wire _out_T_636 = ~out_rimask_53; // @[RegisterRouter.scala:87:24]
wire _out_T_637 = ~out_wimask_53; // @[RegisterRouter.scala:87:24]
wire _out_T_638 = ~out_romask_53; // @[RegisterRouter.scala:87:24]
wire _out_T_639 = ~out_womask_53; // @[RegisterRouter.scala:87:24]
wire [8:0] out_prepend_41 = {1'h0, _out_prepend_T_41}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_640 = {7'h0, out_prepend_41}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_641 = _out_T_640; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_42 = _out_T_641; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_rimask_T_54 = out_frontMask[31:16]; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_wimask_T_54 = out_frontMask[31:16]; // @[RegisterRouter.scala:87:24]
wire out_rimask_54 = |_out_rimask_T_54; // @[RegisterRouter.scala:87:24]
wire out_wimask_54 = &_out_wimask_T_54; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_romask_T_54 = out_backMask[31:16]; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_womask_T_54 = out_backMask[31:16]; // @[RegisterRouter.scala:87:24]
wire out_romask_54 = |_out_romask_T_54; // @[RegisterRouter.scala:87:24]
wire out_womask_54 = &_out_womask_T_54; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_54 = out_rivalid_54 & out_rimask_54; // @[RegisterRouter.scala:87:24]
wire _out_T_643 = out_f_rivalid_54; // @[RegisterRouter.scala:87:24]
wire out_f_roready_54 = out_roready_54 & out_romask_54; // @[RegisterRouter.scala:87:24]
wire _out_T_644 = out_f_roready_54; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_54 = out_wivalid_54 & out_wimask_54; // @[RegisterRouter.scala:87:24]
wire _out_T_645 = out_f_wivalid_54; // @[RegisterRouter.scala:87:24]
assign out_f_woready_54 = out_woready_54 & out_womask_54; // @[RegisterRouter.scala:87:24]
assign autoexecprogbufWrEnMaybe = out_f_woready_54; // @[RegisterRouter.scala:87:24]
wire _out_T_646 = out_f_woready_54; // @[RegisterRouter.scala:87:24]
assign _out_T_642 = out_front_bits_data[31:16]; // @[RegisterRouter.scala:87:24]
assign ABSTRACTAUTOWrData_autoexecprogbuf = _out_T_642; // @[RegisterRouter.scala:87:24]
wire _out_T_647 = ~out_rimask_54; // @[RegisterRouter.scala:87:24]
wire _out_T_648 = ~out_wimask_54; // @[RegisterRouter.scala:87:24]
wire _out_T_649 = ~out_romask_54; // @[RegisterRouter.scala:87:24]
wire _out_T_650 = ~out_womask_54; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_42 = {ABSTRACTAUTORdData_autoexecprogbuf, _out_prepend_T_42}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_651 = out_prepend_42; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_652 = _out_T_651; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_out_bits_data_WIRE_1_24 = _out_T_652; // @[MuxLiteral.scala:49:48]
wire out_rimask_55 = |_out_rimask_T_55; // @[RegisterRouter.scala:87:24]
wire out_wimask_55 = &_out_wimask_T_55; // @[RegisterRouter.scala:87:24]
wire out_romask_55 = |_out_romask_T_55; // @[RegisterRouter.scala:87:24]
wire out_womask_55 = &_out_womask_T_55; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_55 = out_rivalid_55 & out_rimask_55; // @[RegisterRouter.scala:87:24]
wire _out_T_654 = out_f_rivalid_55; // @[RegisterRouter.scala:87:24]
assign out_f_roready_55 = out_roready_55 & out_romask_55; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_20 = out_f_roready_55; // @[RegisterRouter.scala:87:24]
wire _out_T_655 = out_f_roready_55; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_55 = out_wivalid_55 & out_wimask_55; // @[RegisterRouter.scala:87:24]
wire _out_T_656 = out_f_wivalid_55; // @[RegisterRouter.scala:87:24]
assign out_f_woready_55 = out_woready_55 & out_womask_55; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_20 = out_f_woready_55; // @[RegisterRouter.scala:87:24]
wire _out_T_657 = out_f_woready_55; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_20 = out_f_woready_55 ? _out_T_653 : programBufferMem_20; // @[RegisterRouter.scala:87:24]
wire _out_T_658 = ~out_rimask_55; // @[RegisterRouter.scala:87:24]
wire _out_T_659 = ~out_wimask_55; // @[RegisterRouter.scala:87:24]
wire _out_T_660 = ~out_romask_55; // @[RegisterRouter.scala:87:24]
wire _out_T_661 = ~out_womask_55; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_663 = _out_T_662; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_43 = _out_T_663; // @[RegisterRouter.scala:87:24]
wire out_rimask_56 = |_out_rimask_T_56; // @[RegisterRouter.scala:87:24]
wire out_wimask_56 = &_out_wimask_T_56; // @[RegisterRouter.scala:87:24]
wire out_romask_56 = |_out_romask_T_56; // @[RegisterRouter.scala:87:24]
wire out_womask_56 = &_out_womask_T_56; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_56 = out_rivalid_56 & out_rimask_56; // @[RegisterRouter.scala:87:24]
wire _out_T_665 = out_f_rivalid_56; // @[RegisterRouter.scala:87:24]
assign out_f_roready_56 = out_roready_56 & out_romask_56; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_21 = out_f_roready_56; // @[RegisterRouter.scala:87:24]
wire _out_T_666 = out_f_roready_56; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_56 = out_wivalid_56 & out_wimask_56; // @[RegisterRouter.scala:87:24]
wire _out_T_667 = out_f_wivalid_56; // @[RegisterRouter.scala:87:24]
assign out_f_woready_56 = out_woready_56 & out_womask_56; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_21 = out_f_woready_56; // @[RegisterRouter.scala:87:24]
wire _out_T_668 = out_f_woready_56; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_21 = out_f_woready_56 ? _out_T_664 : programBufferMem_21; // @[RegisterRouter.scala:87:24]
wire _out_T_669 = ~out_rimask_56; // @[RegisterRouter.scala:87:24]
wire _out_T_670 = ~out_wimask_56; // @[RegisterRouter.scala:87:24]
wire _out_T_671 = ~out_romask_56; // @[RegisterRouter.scala:87:24]
wire _out_T_672 = ~out_womask_56; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_43 = {programBufferMem_21, _out_prepend_T_43}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_673 = out_prepend_43; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_674 = _out_T_673; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_44 = _out_T_674; // @[RegisterRouter.scala:87:24]
wire out_rimask_57 = |_out_rimask_T_57; // @[RegisterRouter.scala:87:24]
wire out_wimask_57 = &_out_wimask_T_57; // @[RegisterRouter.scala:87:24]
wire out_romask_57 = |_out_romask_T_57; // @[RegisterRouter.scala:87:24]
wire out_womask_57 = &_out_womask_T_57; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_57 = out_rivalid_57 & out_rimask_57; // @[RegisterRouter.scala:87:24]
wire _out_T_676 = out_f_rivalid_57; // @[RegisterRouter.scala:87:24]
assign out_f_roready_57 = out_roready_57 & out_romask_57; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_22 = out_f_roready_57; // @[RegisterRouter.scala:87:24]
wire _out_T_677 = out_f_roready_57; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_57 = out_wivalid_57 & out_wimask_57; // @[RegisterRouter.scala:87:24]
wire _out_T_678 = out_f_wivalid_57; // @[RegisterRouter.scala:87:24]
assign out_f_woready_57 = out_woready_57 & out_womask_57; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_22 = out_f_woready_57; // @[RegisterRouter.scala:87:24]
wire _out_T_679 = out_f_woready_57; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_22 = out_f_woready_57 ? _out_T_675 : programBufferMem_22; // @[RegisterRouter.scala:87:24]
wire _out_T_680 = ~out_rimask_57; // @[RegisterRouter.scala:87:24]
wire _out_T_681 = ~out_wimask_57; // @[RegisterRouter.scala:87:24]
wire _out_T_682 = ~out_romask_57; // @[RegisterRouter.scala:87:24]
wire _out_T_683 = ~out_womask_57; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_44 = {programBufferMem_22, _out_prepend_T_44}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_684 = out_prepend_44; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_685 = _out_T_684; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_45 = _out_T_685; // @[RegisterRouter.scala:87:24]
wire out_rimask_58 = |_out_rimask_T_58; // @[RegisterRouter.scala:87:24]
wire out_wimask_58 = &_out_wimask_T_58; // @[RegisterRouter.scala:87:24]
wire out_romask_58 = |_out_romask_T_58; // @[RegisterRouter.scala:87:24]
wire out_womask_58 = &_out_womask_T_58; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_58 = out_rivalid_58 & out_rimask_58; // @[RegisterRouter.scala:87:24]
wire _out_T_687 = out_f_rivalid_58; // @[RegisterRouter.scala:87:24]
assign out_f_roready_58 = out_roready_58 & out_romask_58; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_23 = out_f_roready_58; // @[RegisterRouter.scala:87:24]
wire _out_T_688 = out_f_roready_58; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_58 = out_wivalid_58 & out_wimask_58; // @[RegisterRouter.scala:87:24]
wire _out_T_689 = out_f_wivalid_58; // @[RegisterRouter.scala:87:24]
assign out_f_woready_58 = out_woready_58 & out_womask_58; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_23 = out_f_woready_58; // @[RegisterRouter.scala:87:24]
wire _out_T_690 = out_f_woready_58; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_23 = out_f_woready_58 ? _out_T_686 : programBufferMem_23; // @[RegisterRouter.scala:87:24]
wire _out_T_691 = ~out_rimask_58; // @[RegisterRouter.scala:87:24]
wire _out_T_692 = ~out_wimask_58; // @[RegisterRouter.scala:87:24]
wire _out_T_693 = ~out_romask_58; // @[RegisterRouter.scala:87:24]
wire _out_T_694 = ~out_womask_58; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_45 = {programBufferMem_23, _out_prepend_T_45}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_695 = out_prepend_45; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_696 = _out_T_695; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_out_bits_data_WIRE_1_37 = _out_T_696; // @[MuxLiteral.scala:49:48]
wire out_rimask_59 = |_out_rimask_T_59; // @[RegisterRouter.scala:87:24]
wire out_wimask_59 = &_out_wimask_T_59; // @[RegisterRouter.scala:87:24]
wire out_romask_59 = |_out_romask_T_59; // @[RegisterRouter.scala:87:24]
wire out_womask_59 = &_out_womask_T_59; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_59 = out_rivalid_59 & out_rimask_59; // @[RegisterRouter.scala:87:24]
wire _out_T_698 = out_f_rivalid_59; // @[RegisterRouter.scala:87:24]
assign out_f_roready_59 = out_roready_59 & out_romask_59; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_56 = out_f_roready_59; // @[RegisterRouter.scala:87:24]
wire _out_T_699 = out_f_roready_59; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_59 = out_wivalid_59 & out_wimask_59; // @[RegisterRouter.scala:87:24]
wire _out_T_700 = out_f_wivalid_59; // @[RegisterRouter.scala:87:24]
assign out_f_woready_59 = out_woready_59 & out_womask_59; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_56 = out_f_woready_59; // @[RegisterRouter.scala:87:24]
wire _out_T_701 = out_f_woready_59; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_56 = out_f_woready_59 ? _out_T_697 : programBufferMem_56; // @[RegisterRouter.scala:87:24]
wire _out_T_702 = ~out_rimask_59; // @[RegisterRouter.scala:87:24]
wire _out_T_703 = ~out_wimask_59; // @[RegisterRouter.scala:87:24]
wire _out_T_704 = ~out_romask_59; // @[RegisterRouter.scala:87:24]
wire _out_T_705 = ~out_womask_59; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_707 = _out_T_706; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_46 = _out_T_707; // @[RegisterRouter.scala:87:24]
wire out_rimask_60 = |_out_rimask_T_60; // @[RegisterRouter.scala:87:24]
wire out_wimask_60 = &_out_wimask_T_60; // @[RegisterRouter.scala:87:24]
wire out_romask_60 = |_out_romask_T_60; // @[RegisterRouter.scala:87:24]
wire out_womask_60 = &_out_womask_T_60; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_60 = out_rivalid_60 & out_rimask_60; // @[RegisterRouter.scala:87:24]
wire _out_T_709 = out_f_rivalid_60; // @[RegisterRouter.scala:87:24]
assign out_f_roready_60 = out_roready_60 & out_romask_60; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_57 = out_f_roready_60; // @[RegisterRouter.scala:87:24]
wire _out_T_710 = out_f_roready_60; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_60 = out_wivalid_60 & out_wimask_60; // @[RegisterRouter.scala:87:24]
wire _out_T_711 = out_f_wivalid_60; // @[RegisterRouter.scala:87:24]
assign out_f_woready_60 = out_woready_60 & out_womask_60; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_57 = out_f_woready_60; // @[RegisterRouter.scala:87:24]
wire _out_T_712 = out_f_woready_60; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_57 = out_f_woready_60 ? _out_T_708 : programBufferMem_57; // @[RegisterRouter.scala:87:24]
wire _out_T_713 = ~out_rimask_60; // @[RegisterRouter.scala:87:24]
wire _out_T_714 = ~out_wimask_60; // @[RegisterRouter.scala:87:24]
wire _out_T_715 = ~out_romask_60; // @[RegisterRouter.scala:87:24]
wire _out_T_716 = ~out_womask_60; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_46 = {programBufferMem_57, _out_prepend_T_46}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_717 = out_prepend_46; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_718 = _out_T_717; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_47 = _out_T_718; // @[RegisterRouter.scala:87:24]
wire out_rimask_61 = |_out_rimask_T_61; // @[RegisterRouter.scala:87:24]
wire out_wimask_61 = &_out_wimask_T_61; // @[RegisterRouter.scala:87:24]
wire out_romask_61 = |_out_romask_T_61; // @[RegisterRouter.scala:87:24]
wire out_womask_61 = &_out_womask_T_61; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_61 = out_rivalid_61 & out_rimask_61; // @[RegisterRouter.scala:87:24]
wire _out_T_720 = out_f_rivalid_61; // @[RegisterRouter.scala:87:24]
assign out_f_roready_61 = out_roready_61 & out_romask_61; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_58 = out_f_roready_61; // @[RegisterRouter.scala:87:24]
wire _out_T_721 = out_f_roready_61; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_61 = out_wivalid_61 & out_wimask_61; // @[RegisterRouter.scala:87:24]
wire _out_T_722 = out_f_wivalid_61; // @[RegisterRouter.scala:87:24]
assign out_f_woready_61 = out_woready_61 & out_womask_61; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_58 = out_f_woready_61; // @[RegisterRouter.scala:87:24]
wire _out_T_723 = out_f_woready_61; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_58 = out_f_woready_61 ? _out_T_719 : programBufferMem_58; // @[RegisterRouter.scala:87:24]
wire _out_T_724 = ~out_rimask_61; // @[RegisterRouter.scala:87:24]
wire _out_T_725 = ~out_wimask_61; // @[RegisterRouter.scala:87:24]
wire _out_T_726 = ~out_romask_61; // @[RegisterRouter.scala:87:24]
wire _out_T_727 = ~out_womask_61; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_47 = {programBufferMem_58, _out_prepend_T_47}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_728 = out_prepend_47; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_729 = _out_T_728; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_48 = _out_T_729; // @[RegisterRouter.scala:87:24]
wire out_rimask_62 = |_out_rimask_T_62; // @[RegisterRouter.scala:87:24]
wire out_wimask_62 = &_out_wimask_T_62; // @[RegisterRouter.scala:87:24]
wire out_romask_62 = |_out_romask_T_62; // @[RegisterRouter.scala:87:24]
wire out_womask_62 = &_out_womask_T_62; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_62 = out_rivalid_62 & out_rimask_62; // @[RegisterRouter.scala:87:24]
wire _out_T_731 = out_f_rivalid_62; // @[RegisterRouter.scala:87:24]
assign out_f_roready_62 = out_roready_62 & out_romask_62; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_59 = out_f_roready_62; // @[RegisterRouter.scala:87:24]
wire _out_T_732 = out_f_roready_62; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_62 = out_wivalid_62 & out_wimask_62; // @[RegisterRouter.scala:87:24]
wire _out_T_733 = out_f_wivalid_62; // @[RegisterRouter.scala:87:24]
assign out_f_woready_62 = out_woready_62 & out_womask_62; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_59 = out_f_woready_62; // @[RegisterRouter.scala:87:24]
wire _out_T_734 = out_f_woready_62; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_59 = out_f_woready_62 ? _out_T_730 : programBufferMem_59; // @[RegisterRouter.scala:87:24]
wire _out_T_735 = ~out_rimask_62; // @[RegisterRouter.scala:87:24]
wire _out_T_736 = ~out_wimask_62; // @[RegisterRouter.scala:87:24]
wire _out_T_737 = ~out_romask_62; // @[RegisterRouter.scala:87:24]
wire _out_T_738 = ~out_womask_62; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_48 = {programBufferMem_59, _out_prepend_T_48}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_739 = out_prepend_48; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_740 = _out_T_739; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_out_bits_data_WIRE_1_46 = _out_T_740; // @[MuxLiteral.scala:49:48]
wire out_rimask_63 = |_out_rimask_T_63; // @[RegisterRouter.scala:87:24]
wire out_wimask_63 = &_out_wimask_T_63; // @[RegisterRouter.scala:87:24]
wire out_romask_63 = |_out_romask_T_63; // @[RegisterRouter.scala:87:24]
wire out_womask_63 = &_out_womask_T_63; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_63 = out_rivalid_63 & out_rimask_63; // @[RegisterRouter.scala:87:24]
wire _out_T_742 = out_f_rivalid_63; // @[RegisterRouter.scala:87:24]
assign out_f_roready_63 = out_roready_63 & out_romask_63; // @[RegisterRouter.scala:87:24]
assign SBADDRESSRdEn_0 = out_f_roready_63; // @[RegisterRouter.scala:87:24]
wire _out_T_743 = out_f_roready_63; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_63 = out_wivalid_63 & out_wimask_63; // @[RegisterRouter.scala:87:24]
wire _out_T_744 = out_f_wivalid_63; // @[RegisterRouter.scala:87:24]
assign out_f_woready_63 = out_woready_63 & out_womask_63; // @[RegisterRouter.scala:87:24]
assign SBADDRESSWrEn_0 = out_f_woready_63; // @[RegisterRouter.scala:87:24]
wire _out_T_745 = out_f_woready_63; // @[RegisterRouter.scala:87:24]
assign SBADDRESSWrData_0 = out_f_woready_63 ? _out_T_741 : 32'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_746 = ~out_rimask_63; // @[RegisterRouter.scala:87:24]
wire _out_T_747 = ~out_wimask_63; // @[RegisterRouter.scala:87:24]
wire _out_T_748 = ~out_romask_63; // @[RegisterRouter.scala:87:24]
wire _out_T_749 = ~out_womask_63; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_751 = _out_T_750; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_out_bits_data_WIRE_1_57 = _out_T_751; // @[MuxLiteral.scala:49:48]
wire out_rimask_64 = |_out_rimask_T_64; // @[RegisterRouter.scala:87:24]
wire out_wimask_64 = &_out_wimask_T_64; // @[RegisterRouter.scala:87:24]
wire out_romask_64 = |_out_romask_T_64; // @[RegisterRouter.scala:87:24]
wire out_womask_64 = &_out_womask_T_64; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_64 = out_rivalid_64 & out_rimask_64; // @[RegisterRouter.scala:87:24]
wire _out_T_753 = out_f_rivalid_64; // @[RegisterRouter.scala:87:24]
assign out_f_roready_64 = out_roready_64 & out_romask_64; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataRdEn_8 = out_f_roready_64; // @[RegisterRouter.scala:87:24]
wire _out_T_754 = out_f_roready_64; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_64 = out_wivalid_64 & out_wimask_64; // @[RegisterRouter.scala:87:24]
wire _out_T_755 = out_f_wivalid_64; // @[RegisterRouter.scala:87:24]
assign out_f_woready_64 = out_woready_64 & out_womask_64; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataWrEnMaybe_8 = out_f_woready_64; // @[RegisterRouter.scala:87:24]
wire _out_T_756 = out_f_woready_64; // @[RegisterRouter.scala:87:24]
assign abstractDataNxt_8 = out_f_woready_64 ? _out_T_752 : abstractDataMem_8; // @[RegisterRouter.scala:87:24]
wire _out_T_757 = ~out_rimask_64; // @[RegisterRouter.scala:87:24]
wire _out_T_758 = ~out_wimask_64; // @[RegisterRouter.scala:87:24]
wire _out_T_759 = ~out_romask_64; // @[RegisterRouter.scala:87:24]
wire _out_T_760 = ~out_womask_64; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_762 = _out_T_761; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_49 = _out_T_762; // @[RegisterRouter.scala:87:24]
wire out_rimask_65 = |_out_rimask_T_65; // @[RegisterRouter.scala:87:24]
wire out_wimask_65 = &_out_wimask_T_65; // @[RegisterRouter.scala:87:24]
wire out_romask_65 = |_out_romask_T_65; // @[RegisterRouter.scala:87:24]
wire out_womask_65 = &_out_womask_T_65; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_65 = out_rivalid_65 & out_rimask_65; // @[RegisterRouter.scala:87:24]
wire _out_T_764 = out_f_rivalid_65; // @[RegisterRouter.scala:87:24]
assign out_f_roready_65 = out_roready_65 & out_romask_65; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataRdEn_9 = out_f_roready_65; // @[RegisterRouter.scala:87:24]
wire _out_T_765 = out_f_roready_65; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_65 = out_wivalid_65 & out_wimask_65; // @[RegisterRouter.scala:87:24]
wire _out_T_766 = out_f_wivalid_65; // @[RegisterRouter.scala:87:24]
assign out_f_woready_65 = out_woready_65 & out_womask_65; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataWrEnMaybe_9 = out_f_woready_65; // @[RegisterRouter.scala:87:24]
wire _out_T_767 = out_f_woready_65; // @[RegisterRouter.scala:87:24]
assign abstractDataNxt_9 = out_f_woready_65 ? _out_T_763 : abstractDataMem_9; // @[RegisterRouter.scala:87:24]
wire _out_T_768 = ~out_rimask_65; // @[RegisterRouter.scala:87:24]
wire _out_T_769 = ~out_wimask_65; // @[RegisterRouter.scala:87:24]
wire _out_T_770 = ~out_romask_65; // @[RegisterRouter.scala:87:24]
wire _out_T_771 = ~out_womask_65; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_49 = {abstractDataMem_9, _out_prepend_T_49}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_772 = out_prepend_49; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_773 = _out_T_772; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_50 = _out_T_773; // @[RegisterRouter.scala:87:24]
wire out_rimask_66 = |_out_rimask_T_66; // @[RegisterRouter.scala:87:24]
wire out_wimask_66 = &_out_wimask_T_66; // @[RegisterRouter.scala:87:24]
wire out_romask_66 = |_out_romask_T_66; // @[RegisterRouter.scala:87:24]
wire out_womask_66 = &_out_womask_T_66; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_66 = out_rivalid_66 & out_rimask_66; // @[RegisterRouter.scala:87:24]
wire _out_T_775 = out_f_rivalid_66; // @[RegisterRouter.scala:87:24]
assign out_f_roready_66 = out_roready_66 & out_romask_66; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataRdEn_10 = out_f_roready_66; // @[RegisterRouter.scala:87:24]
wire _out_T_776 = out_f_roready_66; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_66 = out_wivalid_66 & out_wimask_66; // @[RegisterRouter.scala:87:24]
wire _out_T_777 = out_f_wivalid_66; // @[RegisterRouter.scala:87:24]
assign out_f_woready_66 = out_woready_66 & out_womask_66; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataWrEnMaybe_10 = out_f_woready_66; // @[RegisterRouter.scala:87:24]
wire _out_T_778 = out_f_woready_66; // @[RegisterRouter.scala:87:24]
assign abstractDataNxt_10 = out_f_woready_66 ? _out_T_774 : abstractDataMem_10; // @[RegisterRouter.scala:87:24]
wire _out_T_779 = ~out_rimask_66; // @[RegisterRouter.scala:87:24]
wire _out_T_780 = ~out_wimask_66; // @[RegisterRouter.scala:87:24]
wire _out_T_781 = ~out_romask_66; // @[RegisterRouter.scala:87:24]
wire _out_T_782 = ~out_womask_66; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_50 = {abstractDataMem_10, _out_prepend_T_50}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_783 = out_prepend_50; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_784 = _out_T_783; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_51 = _out_T_784; // @[RegisterRouter.scala:87:24]
wire out_rimask_67 = |_out_rimask_T_67; // @[RegisterRouter.scala:87:24]
wire out_wimask_67 = &_out_wimask_T_67; // @[RegisterRouter.scala:87:24]
wire out_romask_67 = |_out_romask_T_67; // @[RegisterRouter.scala:87:24]
wire out_womask_67 = &_out_womask_T_67; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_67 = out_rivalid_67 & out_rimask_67; // @[RegisterRouter.scala:87:24]
wire _out_T_786 = out_f_rivalid_67; // @[RegisterRouter.scala:87:24]
assign out_f_roready_67 = out_roready_67 & out_romask_67; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataRdEn_11 = out_f_roready_67; // @[RegisterRouter.scala:87:24]
wire _out_T_787 = out_f_roready_67; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_67 = out_wivalid_67 & out_wimask_67; // @[RegisterRouter.scala:87:24]
wire _out_T_788 = out_f_wivalid_67; // @[RegisterRouter.scala:87:24]
assign out_f_woready_67 = out_woready_67 & out_womask_67; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataWrEnMaybe_11 = out_f_woready_67; // @[RegisterRouter.scala:87:24]
wire _out_T_789 = out_f_woready_67; // @[RegisterRouter.scala:87:24]
assign abstractDataNxt_11 = out_f_woready_67 ? _out_T_785 : abstractDataMem_11; // @[RegisterRouter.scala:87:24]
wire _out_T_790 = ~out_rimask_67; // @[RegisterRouter.scala:87:24]
wire _out_T_791 = ~out_wimask_67; // @[RegisterRouter.scala:87:24]
wire _out_T_792 = ~out_romask_67; // @[RegisterRouter.scala:87:24]
wire _out_T_793 = ~out_womask_67; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_51 = {abstractDataMem_11, _out_prepend_T_51}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_794 = out_prepend_51; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_795 = _out_T_794; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_out_bits_data_WIRE_1_6 = _out_T_795; // @[MuxLiteral.scala:49:48]
wire out_rimask_68 = |_out_rimask_T_68; // @[RegisterRouter.scala:87:24]
wire out_wimask_68 = &_out_wimask_T_68; // @[RegisterRouter.scala:87:24]
wire out_romask_68 = |_out_romask_T_68; // @[RegisterRouter.scala:87:24]
wire out_womask_68 = &_out_womask_T_68; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_68 = out_rivalid_68 & out_rimask_68; // @[RegisterRouter.scala:87:24]
wire _out_T_797 = out_f_rivalid_68; // @[RegisterRouter.scala:87:24]
assign out_f_roready_68 = out_roready_68 & out_romask_68; // @[RegisterRouter.scala:87:24]
assign SBDATARdEn_0 = out_f_roready_68; // @[RegisterRouter.scala:87:24]
wire _out_T_798 = out_f_roready_68; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_68 = out_wivalid_68 & out_wimask_68; // @[RegisterRouter.scala:87:24]
wire _out_T_799 = out_f_wivalid_68; // @[RegisterRouter.scala:87:24]
assign out_f_woready_68 = out_woready_68 & out_womask_68; // @[RegisterRouter.scala:87:24]
assign SBDATAWrEn_0 = out_f_woready_68; // @[RegisterRouter.scala:87:24]
wire _out_T_800 = out_f_woready_68; // @[RegisterRouter.scala:87:24]
assign SBDATAWrData_0 = out_f_woready_68 ? _out_T_796 : 32'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_801 = ~out_rimask_68; // @[RegisterRouter.scala:87:24]
wire _out_T_802 = ~out_wimask_68; // @[RegisterRouter.scala:87:24]
wire _out_T_803 = ~out_romask_68; // @[RegisterRouter.scala:87:24]
wire _out_T_804 = ~out_womask_68; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_806 = _out_T_805; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_out_bits_data_WIRE_1_60 = _out_T_806; // @[MuxLiteral.scala:49:48]
wire out_rimask_69 = |_out_rimask_T_69; // @[RegisterRouter.scala:87:24]
wire out_wimask_69 = &_out_wimask_T_69; // @[RegisterRouter.scala:87:24]
wire out_romask_69 = |_out_romask_T_69; // @[RegisterRouter.scala:87:24]
wire out_womask_69 = &_out_womask_T_69; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_69 = out_rivalid_69 & out_rimask_69; // @[RegisterRouter.scala:87:24]
wire _out_T_808 = out_f_rivalid_69; // @[RegisterRouter.scala:87:24]
assign out_f_roready_69 = out_roready_69 & out_romask_69; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_24 = out_f_roready_69; // @[RegisterRouter.scala:87:24]
wire _out_T_809 = out_f_roready_69; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_69 = out_wivalid_69 & out_wimask_69; // @[RegisterRouter.scala:87:24]
wire _out_T_810 = out_f_wivalid_69; // @[RegisterRouter.scala:87:24]
assign out_f_woready_69 = out_woready_69 & out_womask_69; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_24 = out_f_woready_69; // @[RegisterRouter.scala:87:24]
wire _out_T_811 = out_f_woready_69; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_24 = out_f_woready_69 ? _out_T_807 : programBufferMem_24; // @[RegisterRouter.scala:87:24]
wire _out_T_812 = ~out_rimask_69; // @[RegisterRouter.scala:87:24]
wire _out_T_813 = ~out_wimask_69; // @[RegisterRouter.scala:87:24]
wire _out_T_814 = ~out_romask_69; // @[RegisterRouter.scala:87:24]
wire _out_T_815 = ~out_womask_69; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_817 = _out_T_816; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_52 = _out_T_817; // @[RegisterRouter.scala:87:24]
wire out_rimask_70 = |_out_rimask_T_70; // @[RegisterRouter.scala:87:24]
wire out_wimask_70 = &_out_wimask_T_70; // @[RegisterRouter.scala:87:24]
wire out_romask_70 = |_out_romask_T_70; // @[RegisterRouter.scala:87:24]
wire out_womask_70 = &_out_womask_T_70; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_70 = out_rivalid_70 & out_rimask_70; // @[RegisterRouter.scala:87:24]
wire _out_T_819 = out_f_rivalid_70; // @[RegisterRouter.scala:87:24]
assign out_f_roready_70 = out_roready_70 & out_romask_70; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_25 = out_f_roready_70; // @[RegisterRouter.scala:87:24]
wire _out_T_820 = out_f_roready_70; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_70 = out_wivalid_70 & out_wimask_70; // @[RegisterRouter.scala:87:24]
wire _out_T_821 = out_f_wivalid_70; // @[RegisterRouter.scala:87:24]
assign out_f_woready_70 = out_woready_70 & out_womask_70; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_25 = out_f_woready_70; // @[RegisterRouter.scala:87:24]
wire _out_T_822 = out_f_woready_70; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_25 = out_f_woready_70 ? _out_T_818 : programBufferMem_25; // @[RegisterRouter.scala:87:24]
wire _out_T_823 = ~out_rimask_70; // @[RegisterRouter.scala:87:24]
wire _out_T_824 = ~out_wimask_70; // @[RegisterRouter.scala:87:24]
wire _out_T_825 = ~out_romask_70; // @[RegisterRouter.scala:87:24]
wire _out_T_826 = ~out_womask_70; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_52 = {programBufferMem_25, _out_prepend_T_52}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_827 = out_prepend_52; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_828 = _out_T_827; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_53 = _out_T_828; // @[RegisterRouter.scala:87:24]
wire out_rimask_71 = |_out_rimask_T_71; // @[RegisterRouter.scala:87:24]
wire out_wimask_71 = &_out_wimask_T_71; // @[RegisterRouter.scala:87:24]
wire out_romask_71 = |_out_romask_T_71; // @[RegisterRouter.scala:87:24]
wire out_womask_71 = &_out_womask_T_71; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_71 = out_rivalid_71 & out_rimask_71; // @[RegisterRouter.scala:87:24]
wire _out_T_830 = out_f_rivalid_71; // @[RegisterRouter.scala:87:24]
assign out_f_roready_71 = out_roready_71 & out_romask_71; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_26 = out_f_roready_71; // @[RegisterRouter.scala:87:24]
wire _out_T_831 = out_f_roready_71; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_71 = out_wivalid_71 & out_wimask_71; // @[RegisterRouter.scala:87:24]
wire _out_T_832 = out_f_wivalid_71; // @[RegisterRouter.scala:87:24]
assign out_f_woready_71 = out_woready_71 & out_womask_71; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_26 = out_f_woready_71; // @[RegisterRouter.scala:87:24]
wire _out_T_833 = out_f_woready_71; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_26 = out_f_woready_71 ? _out_T_829 : programBufferMem_26; // @[RegisterRouter.scala:87:24]
wire _out_T_834 = ~out_rimask_71; // @[RegisterRouter.scala:87:24]
wire _out_T_835 = ~out_wimask_71; // @[RegisterRouter.scala:87:24]
wire _out_T_836 = ~out_romask_71; // @[RegisterRouter.scala:87:24]
wire _out_T_837 = ~out_womask_71; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_53 = {programBufferMem_26, _out_prepend_T_53}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_838 = out_prepend_53; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_839 = _out_T_838; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_54 = _out_T_839; // @[RegisterRouter.scala:87:24]
wire out_rimask_72 = |_out_rimask_T_72; // @[RegisterRouter.scala:87:24]
wire out_wimask_72 = &_out_wimask_T_72; // @[RegisterRouter.scala:87:24]
wire out_romask_72 = |_out_romask_T_72; // @[RegisterRouter.scala:87:24]
wire out_womask_72 = &_out_womask_T_72; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_72 = out_rivalid_72 & out_rimask_72; // @[RegisterRouter.scala:87:24]
wire _out_T_841 = out_f_rivalid_72; // @[RegisterRouter.scala:87:24]
assign out_f_roready_72 = out_roready_72 & out_romask_72; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_27 = out_f_roready_72; // @[RegisterRouter.scala:87:24]
wire _out_T_842 = out_f_roready_72; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_72 = out_wivalid_72 & out_wimask_72; // @[RegisterRouter.scala:87:24]
wire _out_T_843 = out_f_wivalid_72; // @[RegisterRouter.scala:87:24]
assign out_f_woready_72 = out_woready_72 & out_womask_72; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_27 = out_f_woready_72; // @[RegisterRouter.scala:87:24]
wire _out_T_844 = out_f_woready_72; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_27 = out_f_woready_72 ? _out_T_840 : programBufferMem_27; // @[RegisterRouter.scala:87:24]
wire _out_T_845 = ~out_rimask_72; // @[RegisterRouter.scala:87:24]
wire _out_T_846 = ~out_wimask_72; // @[RegisterRouter.scala:87:24]
wire _out_T_847 = ~out_romask_72; // @[RegisterRouter.scala:87:24]
wire _out_T_848 = ~out_womask_72; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_54 = {programBufferMem_27, _out_prepend_T_54}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_849 = out_prepend_54; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_850 = _out_T_849; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_out_bits_data_WIRE_1_38 = _out_T_850; // @[MuxLiteral.scala:49:48]
wire out_rimask_73 = |_out_rimask_T_73; // @[RegisterRouter.scala:87:24]
wire out_wimask_73 = &_out_wimask_T_73; // @[RegisterRouter.scala:87:24]
wire out_romask_73 = |_out_romask_T_73; // @[RegisterRouter.scala:87:24]
wire out_womask_73 = &_out_womask_T_73; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_73 = out_rivalid_73 & out_rimask_73; // @[RegisterRouter.scala:87:24]
wire _out_T_852 = out_f_rivalid_73; // @[RegisterRouter.scala:87:24]
assign out_f_roready_73 = out_roready_73 & out_romask_73; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_4 = out_f_roready_73; // @[RegisterRouter.scala:87:24]
wire _out_T_853 = out_f_roready_73; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_73 = out_wivalid_73 & out_wimask_73; // @[RegisterRouter.scala:87:24]
wire _out_T_854 = out_f_wivalid_73; // @[RegisterRouter.scala:87:24]
assign out_f_woready_73 = out_woready_73 & out_womask_73; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_4 = out_f_woready_73; // @[RegisterRouter.scala:87:24]
wire _out_T_855 = out_f_woready_73; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_4 = out_f_woready_73 ? _out_T_851 : programBufferMem_4; // @[RegisterRouter.scala:87:24]
wire _out_T_856 = ~out_rimask_73; // @[RegisterRouter.scala:87:24]
wire _out_T_857 = ~out_wimask_73; // @[RegisterRouter.scala:87:24]
wire _out_T_858 = ~out_romask_73; // @[RegisterRouter.scala:87:24]
wire _out_T_859 = ~out_womask_73; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_861 = _out_T_860; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_55 = _out_T_861; // @[RegisterRouter.scala:87:24]
wire out_rimask_74 = |_out_rimask_T_74; // @[RegisterRouter.scala:87:24]
wire out_wimask_74 = &_out_wimask_T_74; // @[RegisterRouter.scala:87:24]
wire out_romask_74 = |_out_romask_T_74; // @[RegisterRouter.scala:87:24]
wire out_womask_74 = &_out_womask_T_74; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_74 = out_rivalid_74 & out_rimask_74; // @[RegisterRouter.scala:87:24]
wire _out_T_863 = out_f_rivalid_74; // @[RegisterRouter.scala:87:24]
assign out_f_roready_74 = out_roready_74 & out_romask_74; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_5 = out_f_roready_74; // @[RegisterRouter.scala:87:24]
wire _out_T_864 = out_f_roready_74; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_74 = out_wivalid_74 & out_wimask_74; // @[RegisterRouter.scala:87:24]
wire _out_T_865 = out_f_wivalid_74; // @[RegisterRouter.scala:87:24]
assign out_f_woready_74 = out_woready_74 & out_womask_74; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_5 = out_f_woready_74; // @[RegisterRouter.scala:87:24]
wire _out_T_866 = out_f_woready_74; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_5 = out_f_woready_74 ? _out_T_862 : programBufferMem_5; // @[RegisterRouter.scala:87:24]
wire _out_T_867 = ~out_rimask_74; // @[RegisterRouter.scala:87:24]
wire _out_T_868 = ~out_wimask_74; // @[RegisterRouter.scala:87:24]
wire _out_T_869 = ~out_romask_74; // @[RegisterRouter.scala:87:24]
wire _out_T_870 = ~out_womask_74; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_55 = {programBufferMem_5, _out_prepend_T_55}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_871 = out_prepend_55; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_872 = _out_T_871; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_56 = _out_T_872; // @[RegisterRouter.scala:87:24]
wire out_rimask_75 = |_out_rimask_T_75; // @[RegisterRouter.scala:87:24]
wire out_wimask_75 = &_out_wimask_T_75; // @[RegisterRouter.scala:87:24]
wire out_romask_75 = |_out_romask_T_75; // @[RegisterRouter.scala:87:24]
wire out_womask_75 = &_out_womask_T_75; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_75 = out_rivalid_75 & out_rimask_75; // @[RegisterRouter.scala:87:24]
wire _out_T_874 = out_f_rivalid_75; // @[RegisterRouter.scala:87:24]
assign out_f_roready_75 = out_roready_75 & out_romask_75; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_6 = out_f_roready_75; // @[RegisterRouter.scala:87:24]
wire _out_T_875 = out_f_roready_75; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_75 = out_wivalid_75 & out_wimask_75; // @[RegisterRouter.scala:87:24]
wire _out_T_876 = out_f_wivalid_75; // @[RegisterRouter.scala:87:24]
assign out_f_woready_75 = out_woready_75 & out_womask_75; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_6 = out_f_woready_75; // @[RegisterRouter.scala:87:24]
wire _out_T_877 = out_f_woready_75; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_6 = out_f_woready_75 ? _out_T_873 : programBufferMem_6; // @[RegisterRouter.scala:87:24]
wire _out_T_878 = ~out_rimask_75; // @[RegisterRouter.scala:87:24]
wire _out_T_879 = ~out_wimask_75; // @[RegisterRouter.scala:87:24]
wire _out_T_880 = ~out_romask_75; // @[RegisterRouter.scala:87:24]
wire _out_T_881 = ~out_womask_75; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_56 = {programBufferMem_6, _out_prepend_T_56}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_882 = out_prepend_56; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_883 = _out_T_882; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_57 = _out_T_883; // @[RegisterRouter.scala:87:24]
wire out_rimask_76 = |_out_rimask_T_76; // @[RegisterRouter.scala:87:24]
wire out_wimask_76 = &_out_wimask_T_76; // @[RegisterRouter.scala:87:24]
wire out_romask_76 = |_out_romask_T_76; // @[RegisterRouter.scala:87:24]
wire out_womask_76 = &_out_womask_T_76; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_76 = out_rivalid_76 & out_rimask_76; // @[RegisterRouter.scala:87:24]
wire _out_T_885 = out_f_rivalid_76; // @[RegisterRouter.scala:87:24]
assign out_f_roready_76 = out_roready_76 & out_romask_76; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_7 = out_f_roready_76; // @[RegisterRouter.scala:87:24]
wire _out_T_886 = out_f_roready_76; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_76 = out_wivalid_76 & out_wimask_76; // @[RegisterRouter.scala:87:24]
wire _out_T_887 = out_f_wivalid_76; // @[RegisterRouter.scala:87:24]
assign out_f_woready_76 = out_woready_76 & out_womask_76; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_7 = out_f_woready_76; // @[RegisterRouter.scala:87:24]
wire _out_T_888 = out_f_woready_76; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_7 = out_f_woready_76 ? _out_T_884 : programBufferMem_7; // @[RegisterRouter.scala:87:24]
wire _out_T_889 = ~out_rimask_76; // @[RegisterRouter.scala:87:24]
wire _out_T_890 = ~out_wimask_76; // @[RegisterRouter.scala:87:24]
wire _out_T_891 = ~out_romask_76; // @[RegisterRouter.scala:87:24]
wire _out_T_892 = ~out_womask_76; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_57 = {programBufferMem_7, _out_prepend_T_57}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_893 = out_prepend_57; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_894 = _out_T_893; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_out_bits_data_WIRE_1_33 = _out_T_894; // @[MuxLiteral.scala:49:48]
wire out_rimask_77 = |_out_rimask_T_77; // @[RegisterRouter.scala:87:24]
wire out_wimask_77 = &_out_wimask_T_77; // @[RegisterRouter.scala:87:24]
wire out_romask_77 = |_out_romask_T_77; // @[RegisterRouter.scala:87:24]
wire out_womask_77 = &_out_womask_T_77; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_77 = out_rivalid_77 & out_rimask_77; // @[RegisterRouter.scala:87:24]
wire _out_T_896 = out_f_rivalid_77; // @[RegisterRouter.scala:87:24]
assign out_f_roready_77 = out_roready_77 & out_romask_77; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_52 = out_f_roready_77; // @[RegisterRouter.scala:87:24]
wire _out_T_897 = out_f_roready_77; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_77 = out_wivalid_77 & out_wimask_77; // @[RegisterRouter.scala:87:24]
wire _out_T_898 = out_f_wivalid_77; // @[RegisterRouter.scala:87:24]
assign out_f_woready_77 = out_woready_77 & out_womask_77; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_52 = out_f_woready_77; // @[RegisterRouter.scala:87:24]
wire _out_T_899 = out_f_woready_77; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_52 = out_f_woready_77 ? _out_T_895 : programBufferMem_52; // @[RegisterRouter.scala:87:24]
wire _out_T_900 = ~out_rimask_77; // @[RegisterRouter.scala:87:24]
wire _out_T_901 = ~out_wimask_77; // @[RegisterRouter.scala:87:24]
wire _out_T_902 = ~out_romask_77; // @[RegisterRouter.scala:87:24]
wire _out_T_903 = ~out_womask_77; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_905 = _out_T_904; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_58 = _out_T_905; // @[RegisterRouter.scala:87:24]
wire out_rimask_78 = |_out_rimask_T_78; // @[RegisterRouter.scala:87:24]
wire out_wimask_78 = &_out_wimask_T_78; // @[RegisterRouter.scala:87:24]
wire out_romask_78 = |_out_romask_T_78; // @[RegisterRouter.scala:87:24]
wire out_womask_78 = &_out_womask_T_78; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_78 = out_rivalid_78 & out_rimask_78; // @[RegisterRouter.scala:87:24]
wire _out_T_907 = out_f_rivalid_78; // @[RegisterRouter.scala:87:24]
assign out_f_roready_78 = out_roready_78 & out_romask_78; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_53 = out_f_roready_78; // @[RegisterRouter.scala:87:24]
wire _out_T_908 = out_f_roready_78; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_78 = out_wivalid_78 & out_wimask_78; // @[RegisterRouter.scala:87:24]
wire _out_T_909 = out_f_wivalid_78; // @[RegisterRouter.scala:87:24]
assign out_f_woready_78 = out_woready_78 & out_womask_78; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_53 = out_f_woready_78; // @[RegisterRouter.scala:87:24]
wire _out_T_910 = out_f_woready_78; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_53 = out_f_woready_78 ? _out_T_906 : programBufferMem_53; // @[RegisterRouter.scala:87:24]
wire _out_T_911 = ~out_rimask_78; // @[RegisterRouter.scala:87:24]
wire _out_T_912 = ~out_wimask_78; // @[RegisterRouter.scala:87:24]
wire _out_T_913 = ~out_romask_78; // @[RegisterRouter.scala:87:24]
wire _out_T_914 = ~out_womask_78; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_58 = {programBufferMem_53, _out_prepend_T_58}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_915 = out_prepend_58; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_916 = _out_T_915; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_59 = _out_T_916; // @[RegisterRouter.scala:87:24]
wire out_rimask_79 = |_out_rimask_T_79; // @[RegisterRouter.scala:87:24]
wire out_wimask_79 = &_out_wimask_T_79; // @[RegisterRouter.scala:87:24]
wire out_romask_79 = |_out_romask_T_79; // @[RegisterRouter.scala:87:24]
wire out_womask_79 = &_out_womask_T_79; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_79 = out_rivalid_79 & out_rimask_79; // @[RegisterRouter.scala:87:24]
wire _out_T_918 = out_f_rivalid_79; // @[RegisterRouter.scala:87:24]
assign out_f_roready_79 = out_roready_79 & out_romask_79; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_54 = out_f_roready_79; // @[RegisterRouter.scala:87:24]
wire _out_T_919 = out_f_roready_79; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_79 = out_wivalid_79 & out_wimask_79; // @[RegisterRouter.scala:87:24]
wire _out_T_920 = out_f_wivalid_79; // @[RegisterRouter.scala:87:24]
assign out_f_woready_79 = out_woready_79 & out_womask_79; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_54 = out_f_woready_79; // @[RegisterRouter.scala:87:24]
wire _out_T_921 = out_f_woready_79; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_54 = out_f_woready_79 ? _out_T_917 : programBufferMem_54; // @[RegisterRouter.scala:87:24]
wire _out_T_922 = ~out_rimask_79; // @[RegisterRouter.scala:87:24]
wire _out_T_923 = ~out_wimask_79; // @[RegisterRouter.scala:87:24]
wire _out_T_924 = ~out_romask_79; // @[RegisterRouter.scala:87:24]
wire _out_T_925 = ~out_womask_79; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_59 = {programBufferMem_54, _out_prepend_T_59}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_926 = out_prepend_59; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_927 = _out_T_926; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_60 = _out_T_927; // @[RegisterRouter.scala:87:24]
wire out_rimask_80 = |_out_rimask_T_80; // @[RegisterRouter.scala:87:24]
wire out_wimask_80 = &_out_wimask_T_80; // @[RegisterRouter.scala:87:24]
wire out_romask_80 = |_out_romask_T_80; // @[RegisterRouter.scala:87:24]
wire out_womask_80 = &_out_womask_T_80; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_80 = out_rivalid_80 & out_rimask_80; // @[RegisterRouter.scala:87:24]
wire _out_T_929 = out_f_rivalid_80; // @[RegisterRouter.scala:87:24]
assign out_f_roready_80 = out_roready_80 & out_romask_80; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_55 = out_f_roready_80; // @[RegisterRouter.scala:87:24]
wire _out_T_930 = out_f_roready_80; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_80 = out_wivalid_80 & out_wimask_80; // @[RegisterRouter.scala:87:24]
wire _out_T_931 = out_f_wivalid_80; // @[RegisterRouter.scala:87:24]
assign out_f_woready_80 = out_woready_80 & out_womask_80; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_55 = out_f_woready_80; // @[RegisterRouter.scala:87:24]
wire _out_T_932 = out_f_woready_80; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_55 = out_f_woready_80 ? _out_T_928 : programBufferMem_55; // @[RegisterRouter.scala:87:24]
wire _out_T_933 = ~out_rimask_80; // @[RegisterRouter.scala:87:24]
wire _out_T_934 = ~out_wimask_80; // @[RegisterRouter.scala:87:24]
wire _out_T_935 = ~out_romask_80; // @[RegisterRouter.scala:87:24]
wire _out_T_936 = ~out_womask_80; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_60 = {programBufferMem_55, _out_prepend_T_60}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_937 = out_prepend_60; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_938 = _out_T_937; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_out_bits_data_WIRE_1_45 = _out_T_938; // @[MuxLiteral.scala:49:48]
wire out_rimask_81 = |_out_rimask_T_81; // @[RegisterRouter.scala:87:24]
wire out_wimask_81 = &_out_wimask_T_81; // @[RegisterRouter.scala:87:24]
wire out_romask_81 = |_out_romask_T_81; // @[RegisterRouter.scala:87:24]
wire out_womask_81 = &_out_womask_T_81; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_81 = out_rivalid_81 & out_rimask_81; // @[RegisterRouter.scala:87:24]
wire _out_T_940 = out_f_rivalid_81; // @[RegisterRouter.scala:87:24]
wire out_f_roready_81 = out_roready_81 & out_romask_81; // @[RegisterRouter.scala:87:24]
wire _out_T_941 = out_f_roready_81; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_81 = out_wivalid_81 & out_wimask_81; // @[RegisterRouter.scala:87:24]
wire out_f_woready_81 = out_woready_81 & out_womask_81; // @[RegisterRouter.scala:87:24]
wire _out_T_942 = ~out_rimask_81; // @[RegisterRouter.scala:87:24]
wire _out_T_943 = ~out_wimask_81; // @[RegisterRouter.scala:87:24]
wire _out_T_944 = ~out_romask_81; // @[RegisterRouter.scala:87:24]
wire _out_T_945 = ~out_womask_81; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_947 = _out_T_946; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_out_bits_data_WIRE_1_0 = _out_T_947; // @[MuxLiteral.scala:49:48]
wire [3:0] _out_rimask_T_82 = out_frontMask[3:0]; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_wimask_T_82 = out_frontMask[3:0]; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_rimask_T_109 = out_frontMask[3:0]; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_wimask_T_109 = out_frontMask[3:0]; // @[RegisterRouter.scala:87:24]
wire out_rimask_82 = |_out_rimask_T_82; // @[RegisterRouter.scala:87:24]
wire out_wimask_82 = &_out_wimask_T_82; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_romask_T_82 = out_backMask[3:0]; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_womask_T_82 = out_backMask[3:0]; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_romask_T_109 = out_backMask[3:0]; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_womask_T_109 = out_backMask[3:0]; // @[RegisterRouter.scala:87:24]
wire out_romask_82 = |_out_romask_T_82; // @[RegisterRouter.scala:87:24]
wire out_womask_82 = &_out_womask_T_82; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_82 = out_rivalid_82 & out_rimask_82; // @[RegisterRouter.scala:87:24]
wire _out_T_949 = out_f_rivalid_82; // @[RegisterRouter.scala:87:24]
wire out_f_roready_82 = out_roready_82 & out_romask_82; // @[RegisterRouter.scala:87:24]
wire _out_T_950 = out_f_roready_82; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_82 = out_wivalid_82 & out_wimask_82; // @[RegisterRouter.scala:87:24]
wire out_f_woready_82 = out_woready_82 & out_womask_82; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_T_948 = out_front_bits_data[3:0]; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_T_1207 = out_front_bits_data[3:0]; // @[RegisterRouter.scala:87:24]
wire _out_T_951 = ~out_rimask_82; // @[RegisterRouter.scala:87:24]
wire _out_T_952 = ~out_wimask_82; // @[RegisterRouter.scala:87:24]
wire _out_T_953 = ~out_romask_82; // @[RegisterRouter.scala:87:24]
wire _out_T_954 = ~out_womask_82; // @[RegisterRouter.scala:87:24]
wire out_rimask_83 = _out_rimask_T_83; // @[RegisterRouter.scala:87:24]
wire out_wimask_83 = _out_wimask_T_83; // @[RegisterRouter.scala:87:24]
wire out_romask_83 = _out_romask_T_83; // @[RegisterRouter.scala:87:24]
wire out_womask_83 = _out_womask_T_83; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_83 = out_rivalid_83 & out_rimask_83; // @[RegisterRouter.scala:87:24]
wire _out_T_958 = out_f_rivalid_83; // @[RegisterRouter.scala:87:24]
wire out_f_roready_83 = out_roready_83 & out_romask_83; // @[RegisterRouter.scala:87:24]
wire _out_T_959 = out_f_roready_83; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_83 = out_wivalid_83 & out_wimask_83; // @[RegisterRouter.scala:87:24]
wire out_f_woready_83 = out_woready_83 & out_womask_83; // @[RegisterRouter.scala:87:24]
wire _out_T_960 = ~out_rimask_83; // @[RegisterRouter.scala:87:24]
wire _out_T_961 = ~out_wimask_83; // @[RegisterRouter.scala:87:24]
wire _out_T_962 = ~out_romask_83; // @[RegisterRouter.scala:87:24]
wire _out_T_963 = ~out_womask_83; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_84 = out_frontMask[5]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_84 = out_frontMask[5]; // @[RegisterRouter.scala:87:24]
wire out_rimask_84 = _out_rimask_T_84; // @[RegisterRouter.scala:87:24]
wire out_wimask_84 = _out_wimask_T_84; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_84 = out_backMask[5]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_84 = out_backMask[5]; // @[RegisterRouter.scala:87:24]
wire out_romask_84 = _out_romask_T_84; // @[RegisterRouter.scala:87:24]
wire out_womask_84 = _out_womask_T_84; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_84 = out_rivalid_84 & out_rimask_84; // @[RegisterRouter.scala:87:24]
wire _out_T_967 = out_f_rivalid_84; // @[RegisterRouter.scala:87:24]
wire out_f_roready_84 = out_roready_84 & out_romask_84; // @[RegisterRouter.scala:87:24]
wire _out_T_968 = out_f_roready_84; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_84 = out_wivalid_84 & out_wimask_84; // @[RegisterRouter.scala:87:24]
wire out_f_woready_84 = out_woready_84 & out_womask_84; // @[RegisterRouter.scala:87:24]
wire _out_T_966 = out_front_bits_data[5]; // @[RegisterRouter.scala:87:24]
wire _out_T_969 = ~out_rimask_84; // @[RegisterRouter.scala:87:24]
wire _out_T_970 = ~out_wimask_84; // @[RegisterRouter.scala:87:24]
wire _out_T_971 = ~out_romask_84; // @[RegisterRouter.scala:87:24]
wire _out_T_972 = ~out_womask_84; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_85 = out_frontMask[6]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_85 = out_frontMask[6]; // @[RegisterRouter.scala:87:24]
wire out_rimask_85 = _out_rimask_T_85; // @[RegisterRouter.scala:87:24]
wire out_wimask_85 = _out_wimask_T_85; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_85 = out_backMask[6]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_85 = out_backMask[6]; // @[RegisterRouter.scala:87:24]
wire out_romask_85 = _out_romask_T_85; // @[RegisterRouter.scala:87:24]
wire out_womask_85 = _out_womask_T_85; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_85 = out_rivalid_85 & out_rimask_85; // @[RegisterRouter.scala:87:24]
wire _out_T_976 = out_f_rivalid_85; // @[RegisterRouter.scala:87:24]
wire out_f_roready_85 = out_roready_85 & out_romask_85; // @[RegisterRouter.scala:87:24]
wire _out_T_977 = out_f_roready_85; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_85 = out_wivalid_85 & out_wimask_85; // @[RegisterRouter.scala:87:24]
wire out_f_woready_85 = out_woready_85 & out_womask_85; // @[RegisterRouter.scala:87:24]
wire _out_T_975 = out_front_bits_data[6]; // @[RegisterRouter.scala:87:24]
wire _out_T_978 = ~out_rimask_85; // @[RegisterRouter.scala:87:24]
wire _out_T_979 = ~out_wimask_85; // @[RegisterRouter.scala:87:24]
wire _out_T_980 = ~out_romask_85; // @[RegisterRouter.scala:87:24]
wire _out_T_981 = ~out_womask_85; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_86 = out_frontMask[7]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_86 = out_frontMask[7]; // @[RegisterRouter.scala:87:24]
wire out_rimask_86 = _out_rimask_T_86; // @[RegisterRouter.scala:87:24]
wire out_wimask_86 = _out_wimask_T_86; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_86 = out_backMask[7]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_86 = out_backMask[7]; // @[RegisterRouter.scala:87:24]
wire out_romask_86 = _out_romask_T_86; // @[RegisterRouter.scala:87:24]
wire out_womask_86 = _out_womask_T_86; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_86 = out_rivalid_86 & out_rimask_86; // @[RegisterRouter.scala:87:24]
wire _out_T_985 = out_f_rivalid_86; // @[RegisterRouter.scala:87:24]
wire out_f_roready_86 = out_roready_86 & out_romask_86; // @[RegisterRouter.scala:87:24]
wire _out_T_986 = out_f_roready_86; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_86 = out_wivalid_86 & out_wimask_86; // @[RegisterRouter.scala:87:24]
wire out_f_woready_86 = out_woready_86 & out_womask_86; // @[RegisterRouter.scala:87:24]
wire _out_T_984 = out_front_bits_data[7]; // @[RegisterRouter.scala:87:24]
wire _out_T_987 = ~out_rimask_86; // @[RegisterRouter.scala:87:24]
wire _out_T_988 = ~out_wimask_86; // @[RegisterRouter.scala:87:24]
wire _out_T_989 = ~out_romask_86; // @[RegisterRouter.scala:87:24]
wire _out_T_990 = ~out_womask_86; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_87 = out_frontMask[8]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_87 = out_frontMask[8]; // @[RegisterRouter.scala:87:24]
wire out_rimask_87 = _out_rimask_T_87; // @[RegisterRouter.scala:87:24]
wire out_wimask_87 = _out_wimask_T_87; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_87 = out_backMask[8]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_87 = out_backMask[8]; // @[RegisterRouter.scala:87:24]
wire out_romask_87 = _out_romask_T_87; // @[RegisterRouter.scala:87:24]
wire out_womask_87 = _out_womask_T_87; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_87 = out_rivalid_87 & out_rimask_87; // @[RegisterRouter.scala:87:24]
wire _out_T_994 = out_f_rivalid_87; // @[RegisterRouter.scala:87:24]
wire out_f_roready_87 = out_roready_87 & out_romask_87; // @[RegisterRouter.scala:87:24]
wire _out_T_995 = out_f_roready_87; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_87 = out_wivalid_87 & out_wimask_87; // @[RegisterRouter.scala:87:24]
wire out_f_woready_87 = out_woready_87 & out_womask_87; // @[RegisterRouter.scala:87:24]
wire _out_T_993 = out_front_bits_data[8]; // @[RegisterRouter.scala:87:24]
wire _out_T_996 = ~out_rimask_87; // @[RegisterRouter.scala:87:24]
wire _out_T_997 = ~out_wimask_87; // @[RegisterRouter.scala:87:24]
wire _out_T_998 = ~out_romask_87; // @[RegisterRouter.scala:87:24]
wire _out_T_999 = ~out_womask_87; // @[RegisterRouter.scala:87:24]
wire [8:0] out_prepend_65 = {DMSTATUSRdData_anyhalted, 8'hA2}; // @[RegisterRouter.scala:87:24]
wire [8:0] _out_T_1000 = out_prepend_65; // @[RegisterRouter.scala:87:24]
wire [8:0] _out_T_1001 = _out_T_1000; // @[RegisterRouter.scala:87:24]
wire [8:0] _out_prepend_T_66 = _out_T_1001; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_88 = out_frontMask[9]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_88 = out_frontMask[9]; // @[RegisterRouter.scala:87:24]
wire out_rimask_88 = _out_rimask_T_88; // @[RegisterRouter.scala:87:24]
wire out_wimask_88 = _out_wimask_T_88; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_88 = out_backMask[9]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_88 = out_backMask[9]; // @[RegisterRouter.scala:87:24]
wire out_romask_88 = _out_romask_T_88; // @[RegisterRouter.scala:87:24]
wire out_womask_88 = _out_womask_T_88; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_88 = out_rivalid_88 & out_rimask_88; // @[RegisterRouter.scala:87:24]
wire _out_T_1003 = out_f_rivalid_88; // @[RegisterRouter.scala:87:24]
wire out_f_roready_88 = out_roready_88 & out_romask_88; // @[RegisterRouter.scala:87:24]
wire _out_T_1004 = out_f_roready_88; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_88 = out_wivalid_88 & out_wimask_88; // @[RegisterRouter.scala:87:24]
wire out_f_woready_88 = out_woready_88 & out_womask_88; // @[RegisterRouter.scala:87:24]
wire _out_T_1002 = out_front_bits_data[9]; // @[RegisterRouter.scala:87:24]
wire _out_T_1005 = ~out_rimask_88; // @[RegisterRouter.scala:87:24]
wire _out_T_1006 = ~out_wimask_88; // @[RegisterRouter.scala:87:24]
wire _out_T_1007 = ~out_romask_88; // @[RegisterRouter.scala:87:24]
wire _out_T_1008 = ~out_womask_88; // @[RegisterRouter.scala:87:24]
wire [9:0] out_prepend_66 = {DMSTATUSRdData_allhalted, _out_prepend_T_66}; // @[RegisterRouter.scala:87:24]
wire [9:0] _out_T_1009 = out_prepend_66; // @[RegisterRouter.scala:87:24]
wire [9:0] _out_T_1010 = _out_T_1009; // @[RegisterRouter.scala:87:24]
wire [9:0] _out_prepend_T_67 = _out_T_1010; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_89 = out_frontMask[10]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_89 = out_frontMask[10]; // @[RegisterRouter.scala:87:24]
wire out_rimask_89 = _out_rimask_T_89; // @[RegisterRouter.scala:87:24]
wire out_wimask_89 = _out_wimask_T_89; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_89 = out_backMask[10]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_89 = out_backMask[10]; // @[RegisterRouter.scala:87:24]
wire out_romask_89 = _out_romask_T_89; // @[RegisterRouter.scala:87:24]
wire out_womask_89 = _out_womask_T_89; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_89 = out_rivalid_89 & out_rimask_89; // @[RegisterRouter.scala:87:24]
wire _out_T_1012 = out_f_rivalid_89; // @[RegisterRouter.scala:87:24]
wire out_f_roready_89 = out_roready_89 & out_romask_89; // @[RegisterRouter.scala:87:24]
wire _out_T_1013 = out_f_roready_89; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_89 = out_wivalid_89 & out_wimask_89; // @[RegisterRouter.scala:87:24]
wire out_f_woready_89 = out_woready_89 & out_womask_89; // @[RegisterRouter.scala:87:24]
wire _out_T_1011 = out_front_bits_data[10]; // @[RegisterRouter.scala:87:24]
wire _out_T_1014 = ~out_rimask_89; // @[RegisterRouter.scala:87:24]
wire _out_T_1015 = ~out_wimask_89; // @[RegisterRouter.scala:87:24]
wire _out_T_1016 = ~out_romask_89; // @[RegisterRouter.scala:87:24]
wire _out_T_1017 = ~out_womask_89; // @[RegisterRouter.scala:87:24]
wire [10:0] out_prepend_67 = {DMSTATUSRdData_anyrunning, _out_prepend_T_67}; // @[RegisterRouter.scala:87:24]
wire [10:0] _out_T_1018 = out_prepend_67; // @[RegisterRouter.scala:87:24]
wire [10:0] _out_T_1019 = _out_T_1018; // @[RegisterRouter.scala:87:24]
wire [10:0] _out_prepend_T_68 = _out_T_1019; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_90 = out_frontMask[11]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_90 = out_frontMask[11]; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_112 = out_frontMask[11]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_112 = out_frontMask[11]; // @[RegisterRouter.scala:87:24]
wire out_rimask_90 = _out_rimask_T_90; // @[RegisterRouter.scala:87:24]
wire out_wimask_90 = _out_wimask_T_90; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_90 = out_backMask[11]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_90 = out_backMask[11]; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_112 = out_backMask[11]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_112 = out_backMask[11]; // @[RegisterRouter.scala:87:24]
wire out_romask_90 = _out_romask_T_90; // @[RegisterRouter.scala:87:24]
wire out_womask_90 = _out_womask_T_90; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_90 = out_rivalid_90 & out_rimask_90; // @[RegisterRouter.scala:87:24]
wire _out_T_1021 = out_f_rivalid_90; // @[RegisterRouter.scala:87:24]
wire out_f_roready_90 = out_roready_90 & out_romask_90; // @[RegisterRouter.scala:87:24]
wire _out_T_1022 = out_f_roready_90; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_90 = out_wivalid_90 & out_wimask_90; // @[RegisterRouter.scala:87:24]
wire out_f_woready_90 = out_woready_90 & out_womask_90; // @[RegisterRouter.scala:87:24]
wire _out_T_1020 = out_front_bits_data[11]; // @[RegisterRouter.scala:87:24]
wire _out_T_1236 = out_front_bits_data[11]; // @[RegisterRouter.scala:87:24]
wire _out_T_1023 = ~out_rimask_90; // @[RegisterRouter.scala:87:24]
wire _out_T_1024 = ~out_wimask_90; // @[RegisterRouter.scala:87:24]
wire _out_T_1025 = ~out_romask_90; // @[RegisterRouter.scala:87:24]
wire _out_T_1026 = ~out_womask_90; // @[RegisterRouter.scala:87:24]
wire [11:0] out_prepend_68 = {DMSTATUSRdData_allrunning, _out_prepend_T_68}; // @[RegisterRouter.scala:87:24]
wire [11:0] _out_T_1027 = out_prepend_68; // @[RegisterRouter.scala:87:24]
wire [11:0] _out_T_1028 = _out_T_1027; // @[RegisterRouter.scala:87:24]
wire [11:0] _out_prepend_T_69 = _out_T_1028; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_91 = out_frontMask[12]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_91 = out_frontMask[12]; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_113 = out_frontMask[12]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_113 = out_frontMask[12]; // @[RegisterRouter.scala:87:24]
wire out_rimask_91 = _out_rimask_T_91; // @[RegisterRouter.scala:87:24]
wire out_wimask_91 = _out_wimask_T_91; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_91 = out_backMask[12]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_91 = out_backMask[12]; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_113 = out_backMask[12]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_113 = out_backMask[12]; // @[RegisterRouter.scala:87:24]
wire out_romask_91 = _out_romask_T_91; // @[RegisterRouter.scala:87:24]
wire out_womask_91 = _out_womask_T_91; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_91 = out_rivalid_91 & out_rimask_91; // @[RegisterRouter.scala:87:24]
wire _out_T_1030 = out_f_rivalid_91; // @[RegisterRouter.scala:87:24]
wire out_f_roready_91 = out_roready_91 & out_romask_91; // @[RegisterRouter.scala:87:24]
wire _out_T_1031 = out_f_roready_91; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_91 = out_wivalid_91 & out_wimask_91; // @[RegisterRouter.scala:87:24]
wire out_f_woready_91 = out_woready_91 & out_womask_91; // @[RegisterRouter.scala:87:24]
wire _out_T_1029 = out_front_bits_data[12]; // @[RegisterRouter.scala:87:24]
wire _out_T_1245 = out_front_bits_data[12]; // @[RegisterRouter.scala:87:24]
wire _out_T_1032 = ~out_rimask_91; // @[RegisterRouter.scala:87:24]
wire _out_T_1033 = ~out_wimask_91; // @[RegisterRouter.scala:87:24]
wire _out_T_1034 = ~out_romask_91; // @[RegisterRouter.scala:87:24]
wire _out_T_1035 = ~out_womask_91; // @[RegisterRouter.scala:87:24]
wire [12:0] out_prepend_69 = {1'h0, _out_prepend_T_69}; // @[RegisterRouter.scala:87:24]
wire [12:0] _out_T_1036 = out_prepend_69; // @[RegisterRouter.scala:87:24]
wire [12:0] _out_T_1037 = _out_T_1036; // @[RegisterRouter.scala:87:24]
wire [12:0] _out_prepend_T_70 = _out_T_1037; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_92 = out_frontMask[13]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_92 = out_frontMask[13]; // @[RegisterRouter.scala:87:24]
wire out_rimask_92 = _out_rimask_T_92; // @[RegisterRouter.scala:87:24]
wire out_wimask_92 = _out_wimask_T_92; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_92 = out_backMask[13]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_92 = out_backMask[13]; // @[RegisterRouter.scala:87:24]
wire out_romask_92 = _out_romask_T_92; // @[RegisterRouter.scala:87:24]
wire out_womask_92 = _out_womask_T_92; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_92 = out_rivalid_92 & out_rimask_92; // @[RegisterRouter.scala:87:24]
wire _out_T_1039 = out_f_rivalid_92; // @[RegisterRouter.scala:87:24]
wire out_f_roready_92 = out_roready_92 & out_romask_92; // @[RegisterRouter.scala:87:24]
wire _out_T_1040 = out_f_roready_92; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_92 = out_wivalid_92 & out_wimask_92; // @[RegisterRouter.scala:87:24]
wire out_f_woready_92 = out_woready_92 & out_womask_92; // @[RegisterRouter.scala:87:24]
wire _out_T_1038 = out_front_bits_data[13]; // @[RegisterRouter.scala:87:24]
wire _out_T_1041 = ~out_rimask_92; // @[RegisterRouter.scala:87:24]
wire _out_T_1042 = ~out_wimask_92; // @[RegisterRouter.scala:87:24]
wire _out_T_1043 = ~out_romask_92; // @[RegisterRouter.scala:87:24]
wire _out_T_1044 = ~out_womask_92; // @[RegisterRouter.scala:87:24]
wire [13:0] out_prepend_70 = {DMSTATUSRdData_allunavail, _out_prepend_T_70}; // @[RegisterRouter.scala:87:24]
wire [13:0] _out_T_1045 = out_prepend_70; // @[RegisterRouter.scala:87:24]
wire [13:0] _out_T_1046 = _out_T_1045; // @[RegisterRouter.scala:87:24]
wire [13:0] _out_prepend_T_71 = _out_T_1046; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_93 = out_frontMask[14]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_93 = out_frontMask[14]; // @[RegisterRouter.scala:87:24]
wire out_rimask_93 = _out_rimask_T_93; // @[RegisterRouter.scala:87:24]
wire out_wimask_93 = _out_wimask_T_93; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_93 = out_backMask[14]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_93 = out_backMask[14]; // @[RegisterRouter.scala:87:24]
wire out_romask_93 = _out_romask_T_93; // @[RegisterRouter.scala:87:24]
wire out_womask_93 = _out_womask_T_93; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_93 = out_rivalid_93 & out_rimask_93; // @[RegisterRouter.scala:87:24]
wire _out_T_1048 = out_f_rivalid_93; // @[RegisterRouter.scala:87:24]
wire out_f_roready_93 = out_roready_93 & out_romask_93; // @[RegisterRouter.scala:87:24]
wire _out_T_1049 = out_f_roready_93; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_93 = out_wivalid_93 & out_wimask_93; // @[RegisterRouter.scala:87:24]
wire out_f_woready_93 = out_woready_93 & out_womask_93; // @[RegisterRouter.scala:87:24]
wire _out_T_1047 = out_front_bits_data[14]; // @[RegisterRouter.scala:87:24]
wire _out_T_1050 = ~out_rimask_93; // @[RegisterRouter.scala:87:24]
wire _out_T_1051 = ~out_wimask_93; // @[RegisterRouter.scala:87:24]
wire _out_T_1052 = ~out_romask_93; // @[RegisterRouter.scala:87:24]
wire _out_T_1053 = ~out_womask_93; // @[RegisterRouter.scala:87:24]
wire [14:0] out_prepend_71 = {DMSTATUSRdData_anynonexistent, _out_prepend_T_71}; // @[RegisterRouter.scala:87:24]
wire [14:0] _out_T_1054 = out_prepend_71; // @[RegisterRouter.scala:87:24]
wire [14:0] _out_T_1055 = _out_T_1054; // @[RegisterRouter.scala:87:24]
wire [14:0] _out_prepend_T_72 = _out_T_1055; // @[RegisterRouter.scala:87:24]
wire out_rimask_94 = _out_rimask_T_94; // @[RegisterRouter.scala:87:24]
wire out_wimask_94 = _out_wimask_T_94; // @[RegisterRouter.scala:87:24]
wire out_romask_94 = _out_romask_T_94; // @[RegisterRouter.scala:87:24]
wire out_womask_94 = _out_womask_T_94; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_94 = out_rivalid_94 & out_rimask_94; // @[RegisterRouter.scala:87:24]
wire _out_T_1057 = out_f_rivalid_94; // @[RegisterRouter.scala:87:24]
wire out_f_roready_94 = out_roready_94 & out_romask_94; // @[RegisterRouter.scala:87:24]
wire _out_T_1058 = out_f_roready_94; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_94 = out_wivalid_94 & out_wimask_94; // @[RegisterRouter.scala:87:24]
wire out_f_woready_94 = out_woready_94 & out_womask_94; // @[RegisterRouter.scala:87:24]
wire _out_T_1059 = ~out_rimask_94; // @[RegisterRouter.scala:87:24]
wire _out_T_1060 = ~out_wimask_94; // @[RegisterRouter.scala:87:24]
wire _out_T_1061 = ~out_romask_94; // @[RegisterRouter.scala:87:24]
wire _out_T_1062 = ~out_womask_94; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_72 = {DMSTATUSRdData_allnonexistent, _out_prepend_T_72}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_1063 = out_prepend_72; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_1064 = _out_T_1063; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_73 = _out_T_1064; // @[RegisterRouter.scala:87:24]
wire out_rimask_95 = _out_rimask_T_95; // @[RegisterRouter.scala:87:24]
wire out_wimask_95 = _out_wimask_T_95; // @[RegisterRouter.scala:87:24]
wire out_romask_95 = _out_romask_T_95; // @[RegisterRouter.scala:87:24]
wire out_womask_95 = _out_womask_T_95; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_95 = out_rivalid_95 & out_rimask_95; // @[RegisterRouter.scala:87:24]
wire _out_T_1066 = out_f_rivalid_95; // @[RegisterRouter.scala:87:24]
wire out_f_roready_95 = out_roready_95 & out_romask_95; // @[RegisterRouter.scala:87:24]
wire _out_T_1067 = out_f_roready_95; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_95 = out_wivalid_95 & out_wimask_95; // @[RegisterRouter.scala:87:24]
wire out_f_woready_95 = out_woready_95 & out_womask_95; // @[RegisterRouter.scala:87:24]
wire _out_T_1068 = ~out_rimask_95; // @[RegisterRouter.scala:87:24]
wire _out_T_1069 = ~out_wimask_95; // @[RegisterRouter.scala:87:24]
wire _out_T_1070 = ~out_romask_95; // @[RegisterRouter.scala:87:24]
wire _out_T_1071 = ~out_womask_95; // @[RegisterRouter.scala:87:24]
wire [16:0] out_prepend_73 = {DMSTATUSRdData_anyresumeack, _out_prepend_T_73}; // @[RegisterRouter.scala:87:24]
wire [16:0] _out_T_1072 = out_prepend_73; // @[RegisterRouter.scala:87:24]
wire [16:0] _out_T_1073 = _out_T_1072; // @[RegisterRouter.scala:87:24]
wire [16:0] _out_prepend_T_74 = _out_T_1073; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_96 = out_frontMask[17]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_96 = out_frontMask[17]; // @[RegisterRouter.scala:87:24]
wire out_rimask_96 = _out_rimask_T_96; // @[RegisterRouter.scala:87:24]
wire out_wimask_96 = _out_wimask_T_96; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_96 = out_backMask[17]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_96 = out_backMask[17]; // @[RegisterRouter.scala:87:24]
wire out_romask_96 = _out_romask_T_96; // @[RegisterRouter.scala:87:24]
wire out_womask_96 = _out_womask_T_96; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_96 = out_rivalid_96 & out_rimask_96; // @[RegisterRouter.scala:87:24]
wire _out_T_1075 = out_f_rivalid_96; // @[RegisterRouter.scala:87:24]
wire out_f_roready_96 = out_roready_96 & out_romask_96; // @[RegisterRouter.scala:87:24]
wire _out_T_1076 = out_f_roready_96; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_96 = out_wivalid_96 & out_wimask_96; // @[RegisterRouter.scala:87:24]
wire out_f_woready_96 = out_woready_96 & out_womask_96; // @[RegisterRouter.scala:87:24]
wire _out_T_1074 = out_front_bits_data[17]; // @[RegisterRouter.scala:87:24]
wire _out_T_1077 = ~out_rimask_96; // @[RegisterRouter.scala:87:24]
wire _out_T_1078 = ~out_wimask_96; // @[RegisterRouter.scala:87:24]
wire _out_T_1079 = ~out_romask_96; // @[RegisterRouter.scala:87:24]
wire _out_T_1080 = ~out_womask_96; // @[RegisterRouter.scala:87:24]
wire [17:0] out_prepend_74 = {DMSTATUSRdData_allresumeack, _out_prepend_T_74}; // @[RegisterRouter.scala:87:24]
wire [17:0] _out_T_1081 = out_prepend_74; // @[RegisterRouter.scala:87:24]
wire [17:0] _out_T_1082 = _out_T_1081; // @[RegisterRouter.scala:87:24]
wire [17:0] _out_prepend_T_75 = _out_T_1082; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_97 = out_frontMask[18]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_97 = out_frontMask[18]; // @[RegisterRouter.scala:87:24]
wire out_rimask_97 = _out_rimask_T_97; // @[RegisterRouter.scala:87:24]
wire out_wimask_97 = _out_wimask_T_97; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_97 = out_backMask[18]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_97 = out_backMask[18]; // @[RegisterRouter.scala:87:24]
wire out_romask_97 = _out_romask_T_97; // @[RegisterRouter.scala:87:24]
wire out_womask_97 = _out_womask_T_97; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_97 = out_rivalid_97 & out_rimask_97; // @[RegisterRouter.scala:87:24]
wire _out_T_1084 = out_f_rivalid_97; // @[RegisterRouter.scala:87:24]
wire out_f_roready_97 = out_roready_97 & out_romask_97; // @[RegisterRouter.scala:87:24]
wire _out_T_1085 = out_f_roready_97; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_97 = out_wivalid_97 & out_wimask_97; // @[RegisterRouter.scala:87:24]
wire out_f_woready_97 = out_woready_97 & out_womask_97; // @[RegisterRouter.scala:87:24]
wire _out_T_1083 = out_front_bits_data[18]; // @[RegisterRouter.scala:87:24]
wire _out_T_1086 = ~out_rimask_97; // @[RegisterRouter.scala:87:24]
wire _out_T_1087 = ~out_wimask_97; // @[RegisterRouter.scala:87:24]
wire _out_T_1088 = ~out_romask_97; // @[RegisterRouter.scala:87:24]
wire _out_T_1089 = ~out_womask_97; // @[RegisterRouter.scala:87:24]
wire [18:0] out_prepend_75 = {DMSTATUSRdData_anyhavereset, _out_prepend_T_75}; // @[RegisterRouter.scala:87:24]
wire [18:0] _out_T_1090 = out_prepend_75; // @[RegisterRouter.scala:87:24]
wire [18:0] _out_T_1091 = _out_T_1090; // @[RegisterRouter.scala:87:24]
wire [18:0] _out_prepend_T_76 = _out_T_1091; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_98 = out_frontMask[19]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_98 = out_frontMask[19]; // @[RegisterRouter.scala:87:24]
wire out_rimask_98 = _out_rimask_T_98; // @[RegisterRouter.scala:87:24]
wire out_wimask_98 = _out_wimask_T_98; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_98 = out_backMask[19]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_98 = out_backMask[19]; // @[RegisterRouter.scala:87:24]
wire out_romask_98 = _out_romask_T_98; // @[RegisterRouter.scala:87:24]
wire out_womask_98 = _out_womask_T_98; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_98 = out_rivalid_98 & out_rimask_98; // @[RegisterRouter.scala:87:24]
wire _out_T_1093 = out_f_rivalid_98; // @[RegisterRouter.scala:87:24]
wire out_f_roready_98 = out_roready_98 & out_romask_98; // @[RegisterRouter.scala:87:24]
wire _out_T_1094 = out_f_roready_98; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_98 = out_wivalid_98 & out_wimask_98; // @[RegisterRouter.scala:87:24]
wire out_f_woready_98 = out_woready_98 & out_womask_98; // @[RegisterRouter.scala:87:24]
wire _out_T_1092 = out_front_bits_data[19]; // @[RegisterRouter.scala:87:24]
wire _out_T_1095 = ~out_rimask_98; // @[RegisterRouter.scala:87:24]
wire _out_T_1096 = ~out_wimask_98; // @[RegisterRouter.scala:87:24]
wire _out_T_1097 = ~out_romask_98; // @[RegisterRouter.scala:87:24]
wire _out_T_1098 = ~out_womask_98; // @[RegisterRouter.scala:87:24]
wire [19:0] out_prepend_76 = {DMSTATUSRdData_allhavereset, _out_prepend_T_76}; // @[RegisterRouter.scala:87:24]
wire [19:0] _out_T_1099 = out_prepend_76; // @[RegisterRouter.scala:87:24]
wire [19:0] _out_T_1100 = _out_T_1099; // @[RegisterRouter.scala:87:24]
wire [19:0] _out_prepend_T_77 = _out_T_1100; // @[RegisterRouter.scala:87:24]
wire [1:0] _out_rimask_T_99 = out_frontMask[21:20]; // @[RegisterRouter.scala:87:24]
wire [1:0] _out_wimask_T_99 = out_frontMask[21:20]; // @[RegisterRouter.scala:87:24]
wire out_rimask_99 = |_out_rimask_T_99; // @[RegisterRouter.scala:87:24]
wire out_wimask_99 = &_out_wimask_T_99; // @[RegisterRouter.scala:87:24]
wire [1:0] _out_romask_T_99 = out_backMask[21:20]; // @[RegisterRouter.scala:87:24]
wire [1:0] _out_womask_T_99 = out_backMask[21:20]; // @[RegisterRouter.scala:87:24]
wire out_romask_99 = |_out_romask_T_99; // @[RegisterRouter.scala:87:24]
wire out_womask_99 = &_out_womask_T_99; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_99 = out_rivalid_99 & out_rimask_99; // @[RegisterRouter.scala:87:24]
wire _out_T_1102 = out_f_rivalid_99; // @[RegisterRouter.scala:87:24]
wire out_f_roready_99 = out_roready_99 & out_romask_99; // @[RegisterRouter.scala:87:24]
wire _out_T_1103 = out_f_roready_99; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_99 = out_wivalid_99 & out_wimask_99; // @[RegisterRouter.scala:87:24]
wire out_f_woready_99 = out_woready_99 & out_womask_99; // @[RegisterRouter.scala:87:24]
wire [1:0] _out_T_1101 = out_front_bits_data[21:20]; // @[RegisterRouter.scala:87:24]
wire _out_T_1104 = ~out_rimask_99; // @[RegisterRouter.scala:87:24]
wire _out_T_1105 = ~out_wimask_99; // @[RegisterRouter.scala:87:24]
wire _out_T_1106 = ~out_romask_99; // @[RegisterRouter.scala:87:24]
wire _out_T_1107 = ~out_womask_99; // @[RegisterRouter.scala:87:24]
wire [20:0] out_prepend_77 = {1'h0, _out_prepend_T_77}; // @[RegisterRouter.scala:87:24]
wire [21:0] _out_T_1108 = {1'h0, out_prepend_77}; // @[RegisterRouter.scala:87:24]
wire [21:0] _out_T_1109 = _out_T_1108; // @[RegisterRouter.scala:87:24]
wire [21:0] _out_prepend_T_78 = _out_T_1109; // @[RegisterRouter.scala:87:24]
wire out_rimask_100 = _out_rimask_T_100; // @[RegisterRouter.scala:87:24]
wire out_wimask_100 = _out_wimask_T_100; // @[RegisterRouter.scala:87:24]
wire out_romask_100 = _out_romask_T_100; // @[RegisterRouter.scala:87:24]
wire out_womask_100 = _out_womask_T_100; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_100 = out_rivalid_100 & out_rimask_100; // @[RegisterRouter.scala:87:24]
wire _out_T_1111 = out_f_rivalid_100; // @[RegisterRouter.scala:87:24]
wire out_f_roready_100 = out_roready_100 & out_romask_100; // @[RegisterRouter.scala:87:24]
wire _out_T_1112 = out_f_roready_100; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_100 = out_wivalid_100 & out_wimask_100; // @[RegisterRouter.scala:87:24]
wire out_f_woready_100 = out_woready_100 & out_womask_100; // @[RegisterRouter.scala:87:24]
wire _out_T_1113 = ~out_rimask_100; // @[RegisterRouter.scala:87:24]
wire _out_T_1114 = ~out_wimask_100; // @[RegisterRouter.scala:87:24]
wire _out_T_1115 = ~out_romask_100; // @[RegisterRouter.scala:87:24]
wire _out_T_1116 = ~out_womask_100; // @[RegisterRouter.scala:87:24]
wire [22:0] out_prepend_78 = {1'h0, _out_prepend_T_78}; // @[RegisterRouter.scala:87:24]
wire [22:0] _out_T_1117 = out_prepend_78; // @[RegisterRouter.scala:87:24]
wire [22:0] _out_T_1118 = _out_T_1117; // @[RegisterRouter.scala:87:24]
wire out_rimask_101 = |_out_rimask_T_101; // @[RegisterRouter.scala:87:24]
wire out_wimask_101 = &_out_wimask_T_101; // @[RegisterRouter.scala:87:24]
wire out_romask_101 = |_out_romask_T_101; // @[RegisterRouter.scala:87:24]
wire out_womask_101 = &_out_womask_T_101; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_101 = out_rivalid_101 & out_rimask_101; // @[RegisterRouter.scala:87:24]
wire _out_T_1120 = out_f_rivalid_101; // @[RegisterRouter.scala:87:24]
assign out_f_roready_101 = out_roready_101 & out_romask_101; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_0 = out_f_roready_101; // @[RegisterRouter.scala:87:24]
wire _out_T_1121 = out_f_roready_101; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_101 = out_wivalid_101 & out_wimask_101; // @[RegisterRouter.scala:87:24]
wire _out_T_1122 = out_f_wivalid_101; // @[RegisterRouter.scala:87:24]
assign out_f_woready_101 = out_woready_101 & out_womask_101; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_0 = out_f_woready_101; // @[RegisterRouter.scala:87:24]
wire _out_T_1123 = out_f_woready_101; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_0 = out_f_woready_101 ? _out_T_1119 : programBufferMem_0; // @[RegisterRouter.scala:87:24]
wire _out_T_1124 = ~out_rimask_101; // @[RegisterRouter.scala:87:24]
wire _out_T_1125 = ~out_wimask_101; // @[RegisterRouter.scala:87:24]
wire _out_T_1126 = ~out_romask_101; // @[RegisterRouter.scala:87:24]
wire _out_T_1127 = ~out_womask_101; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1129 = _out_T_1128; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_79 = _out_T_1129; // @[RegisterRouter.scala:87:24]
wire out_rimask_102 = |_out_rimask_T_102; // @[RegisterRouter.scala:87:24]
wire out_wimask_102 = &_out_wimask_T_102; // @[RegisterRouter.scala:87:24]
wire out_romask_102 = |_out_romask_T_102; // @[RegisterRouter.scala:87:24]
wire out_womask_102 = &_out_womask_T_102; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_102 = out_rivalid_102 & out_rimask_102; // @[RegisterRouter.scala:87:24]
wire _out_T_1131 = out_f_rivalid_102; // @[RegisterRouter.scala:87:24]
assign out_f_roready_102 = out_roready_102 & out_romask_102; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_1 = out_f_roready_102; // @[RegisterRouter.scala:87:24]
wire _out_T_1132 = out_f_roready_102; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_102 = out_wivalid_102 & out_wimask_102; // @[RegisterRouter.scala:87:24]
wire _out_T_1133 = out_f_wivalid_102; // @[RegisterRouter.scala:87:24]
assign out_f_woready_102 = out_woready_102 & out_womask_102; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_1 = out_f_woready_102; // @[RegisterRouter.scala:87:24]
wire _out_T_1134 = out_f_woready_102; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_1 = out_f_woready_102 ? _out_T_1130 : programBufferMem_1; // @[RegisterRouter.scala:87:24]
wire _out_T_1135 = ~out_rimask_102; // @[RegisterRouter.scala:87:24]
wire _out_T_1136 = ~out_wimask_102; // @[RegisterRouter.scala:87:24]
wire _out_T_1137 = ~out_romask_102; // @[RegisterRouter.scala:87:24]
wire _out_T_1138 = ~out_womask_102; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_79 = {programBufferMem_1, _out_prepend_T_79}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_1139 = out_prepend_79; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_1140 = _out_T_1139; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_80 = _out_T_1140; // @[RegisterRouter.scala:87:24]
wire out_rimask_103 = |_out_rimask_T_103; // @[RegisterRouter.scala:87:24]
wire out_wimask_103 = &_out_wimask_T_103; // @[RegisterRouter.scala:87:24]
wire out_romask_103 = |_out_romask_T_103; // @[RegisterRouter.scala:87:24]
wire out_womask_103 = &_out_womask_T_103; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_103 = out_rivalid_103 & out_rimask_103; // @[RegisterRouter.scala:87:24]
wire _out_T_1142 = out_f_rivalid_103; // @[RegisterRouter.scala:87:24]
assign out_f_roready_103 = out_roready_103 & out_romask_103; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_2 = out_f_roready_103; // @[RegisterRouter.scala:87:24]
wire _out_T_1143 = out_f_roready_103; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_103 = out_wivalid_103 & out_wimask_103; // @[RegisterRouter.scala:87:24]
wire _out_T_1144 = out_f_wivalid_103; // @[RegisterRouter.scala:87:24]
assign out_f_woready_103 = out_woready_103 & out_womask_103; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_2 = out_f_woready_103; // @[RegisterRouter.scala:87:24]
wire _out_T_1145 = out_f_woready_103; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_2 = out_f_woready_103 ? _out_T_1141 : programBufferMem_2; // @[RegisterRouter.scala:87:24]
wire _out_T_1146 = ~out_rimask_103; // @[RegisterRouter.scala:87:24]
wire _out_T_1147 = ~out_wimask_103; // @[RegisterRouter.scala:87:24]
wire _out_T_1148 = ~out_romask_103; // @[RegisterRouter.scala:87:24]
wire _out_T_1149 = ~out_womask_103; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_80 = {programBufferMem_2, _out_prepend_T_80}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_1150 = out_prepend_80; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_1151 = _out_T_1150; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_81 = _out_T_1151; // @[RegisterRouter.scala:87:24]
wire out_rimask_104 = |_out_rimask_T_104; // @[RegisterRouter.scala:87:24]
wire out_wimask_104 = &_out_wimask_T_104; // @[RegisterRouter.scala:87:24]
wire out_romask_104 = |_out_romask_T_104; // @[RegisterRouter.scala:87:24]
wire out_womask_104 = &_out_womask_T_104; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_104 = out_rivalid_104 & out_rimask_104; // @[RegisterRouter.scala:87:24]
wire _out_T_1153 = out_f_rivalid_104; // @[RegisterRouter.scala:87:24]
assign out_f_roready_104 = out_roready_104 & out_romask_104; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_3 = out_f_roready_104; // @[RegisterRouter.scala:87:24]
wire _out_T_1154 = out_f_roready_104; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_104 = out_wivalid_104 & out_wimask_104; // @[RegisterRouter.scala:87:24]
wire _out_T_1155 = out_f_wivalid_104; // @[RegisterRouter.scala:87:24]
assign out_f_woready_104 = out_woready_104 & out_womask_104; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_3 = out_f_woready_104; // @[RegisterRouter.scala:87:24]
wire _out_T_1156 = out_f_woready_104; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_3 = out_f_woready_104 ? _out_T_1152 : programBufferMem_3; // @[RegisterRouter.scala:87:24]
wire _out_T_1157 = ~out_rimask_104; // @[RegisterRouter.scala:87:24]
wire _out_T_1158 = ~out_wimask_104; // @[RegisterRouter.scala:87:24]
wire _out_T_1159 = ~out_romask_104; // @[RegisterRouter.scala:87:24]
wire _out_T_1160 = ~out_womask_104; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_81 = {programBufferMem_3, _out_prepend_T_81}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_1161 = out_prepend_81; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_1162 = _out_T_1161; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_out_bits_data_WIRE_1_32 = _out_T_1162; // @[MuxLiteral.scala:49:48]
wire out_rimask_105 = |_out_rimask_T_105; // @[RegisterRouter.scala:87:24]
wire out_wimask_105 = &_out_wimask_T_105; // @[RegisterRouter.scala:87:24]
wire out_romask_105 = |_out_romask_T_105; // @[RegisterRouter.scala:87:24]
wire out_womask_105 = &_out_womask_T_105; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_105 = out_rivalid_105 & out_rimask_105; // @[RegisterRouter.scala:87:24]
wire _out_T_1164 = out_f_rivalid_105; // @[RegisterRouter.scala:87:24]
assign out_f_roready_105 = out_roready_105 & out_romask_105; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_8 = out_f_roready_105; // @[RegisterRouter.scala:87:24]
wire _out_T_1165 = out_f_roready_105; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_105 = out_wivalid_105 & out_wimask_105; // @[RegisterRouter.scala:87:24]
wire _out_T_1166 = out_f_wivalid_105; // @[RegisterRouter.scala:87:24]
assign out_f_woready_105 = out_woready_105 & out_womask_105; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_8 = out_f_woready_105; // @[RegisterRouter.scala:87:24]
wire _out_T_1167 = out_f_woready_105; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_8 = out_f_woready_105 ? _out_T_1163 : programBufferMem_8; // @[RegisterRouter.scala:87:24]
wire _out_T_1168 = ~out_rimask_105; // @[RegisterRouter.scala:87:24]
wire _out_T_1169 = ~out_wimask_105; // @[RegisterRouter.scala:87:24]
wire _out_T_1170 = ~out_romask_105; // @[RegisterRouter.scala:87:24]
wire _out_T_1171 = ~out_womask_105; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1173 = _out_T_1172; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_82 = _out_T_1173; // @[RegisterRouter.scala:87:24]
wire out_rimask_106 = |_out_rimask_T_106; // @[RegisterRouter.scala:87:24]
wire out_wimask_106 = &_out_wimask_T_106; // @[RegisterRouter.scala:87:24]
wire out_romask_106 = |_out_romask_T_106; // @[RegisterRouter.scala:87:24]
wire out_womask_106 = &_out_womask_T_106; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_106 = out_rivalid_106 & out_rimask_106; // @[RegisterRouter.scala:87:24]
wire _out_T_1175 = out_f_rivalid_106; // @[RegisterRouter.scala:87:24]
assign out_f_roready_106 = out_roready_106 & out_romask_106; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_9 = out_f_roready_106; // @[RegisterRouter.scala:87:24]
wire _out_T_1176 = out_f_roready_106; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_106 = out_wivalid_106 & out_wimask_106; // @[RegisterRouter.scala:87:24]
wire _out_T_1177 = out_f_wivalid_106; // @[RegisterRouter.scala:87:24]
assign out_f_woready_106 = out_woready_106 & out_womask_106; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_9 = out_f_woready_106; // @[RegisterRouter.scala:87:24]
wire _out_T_1178 = out_f_woready_106; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_9 = out_f_woready_106 ? _out_T_1174 : programBufferMem_9; // @[RegisterRouter.scala:87:24]
wire _out_T_1179 = ~out_rimask_106; // @[RegisterRouter.scala:87:24]
wire _out_T_1180 = ~out_wimask_106; // @[RegisterRouter.scala:87:24]
wire _out_T_1181 = ~out_romask_106; // @[RegisterRouter.scala:87:24]
wire _out_T_1182 = ~out_womask_106; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_82 = {programBufferMem_9, _out_prepend_T_82}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_1183 = out_prepend_82; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_1184 = _out_T_1183; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_83 = _out_T_1184; // @[RegisterRouter.scala:87:24]
wire out_rimask_107 = |_out_rimask_T_107; // @[RegisterRouter.scala:87:24]
wire out_wimask_107 = &_out_wimask_T_107; // @[RegisterRouter.scala:87:24]
wire out_romask_107 = |_out_romask_T_107; // @[RegisterRouter.scala:87:24]
wire out_womask_107 = &_out_womask_T_107; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_107 = out_rivalid_107 & out_rimask_107; // @[RegisterRouter.scala:87:24]
wire _out_T_1186 = out_f_rivalid_107; // @[RegisterRouter.scala:87:24]
assign out_f_roready_107 = out_roready_107 & out_romask_107; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_10 = out_f_roready_107; // @[RegisterRouter.scala:87:24]
wire _out_T_1187 = out_f_roready_107; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_107 = out_wivalid_107 & out_wimask_107; // @[RegisterRouter.scala:87:24]
wire _out_T_1188 = out_f_wivalid_107; // @[RegisterRouter.scala:87:24]
assign out_f_woready_107 = out_woready_107 & out_womask_107; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_10 = out_f_woready_107; // @[RegisterRouter.scala:87:24]
wire _out_T_1189 = out_f_woready_107; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_10 = out_f_woready_107 ? _out_T_1185 : programBufferMem_10; // @[RegisterRouter.scala:87:24]
wire _out_T_1190 = ~out_rimask_107; // @[RegisterRouter.scala:87:24]
wire _out_T_1191 = ~out_wimask_107; // @[RegisterRouter.scala:87:24]
wire _out_T_1192 = ~out_romask_107; // @[RegisterRouter.scala:87:24]
wire _out_T_1193 = ~out_womask_107; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_83 = {programBufferMem_10, _out_prepend_T_83}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_1194 = out_prepend_83; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_1195 = _out_T_1194; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_84 = _out_T_1195; // @[RegisterRouter.scala:87:24]
wire out_rimask_108 = |_out_rimask_T_108; // @[RegisterRouter.scala:87:24]
wire out_wimask_108 = &_out_wimask_T_108; // @[RegisterRouter.scala:87:24]
wire out_romask_108 = |_out_romask_T_108; // @[RegisterRouter.scala:87:24]
wire out_womask_108 = &_out_womask_T_108; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_108 = out_rivalid_108 & out_rimask_108; // @[RegisterRouter.scala:87:24]
wire _out_T_1197 = out_f_rivalid_108; // @[RegisterRouter.scala:87:24]
assign out_f_roready_108 = out_roready_108 & out_romask_108; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_11 = out_f_roready_108; // @[RegisterRouter.scala:87:24]
wire _out_T_1198 = out_f_roready_108; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_108 = out_wivalid_108 & out_wimask_108; // @[RegisterRouter.scala:87:24]
wire _out_T_1199 = out_f_wivalid_108; // @[RegisterRouter.scala:87:24]
assign out_f_woready_108 = out_woready_108 & out_womask_108; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_11 = out_f_woready_108; // @[RegisterRouter.scala:87:24]
wire _out_T_1200 = out_f_woready_108; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_11 = out_f_woready_108 ? _out_T_1196 : programBufferMem_11; // @[RegisterRouter.scala:87:24]
wire _out_T_1201 = ~out_rimask_108; // @[RegisterRouter.scala:87:24]
wire _out_T_1202 = ~out_wimask_108; // @[RegisterRouter.scala:87:24]
wire _out_T_1203 = ~out_romask_108; // @[RegisterRouter.scala:87:24]
wire _out_T_1204 = ~out_womask_108; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_84 = {programBufferMem_11, _out_prepend_T_84}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_1205 = out_prepend_84; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_1206 = _out_T_1205; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_out_bits_data_WIRE_1_34 = _out_T_1206; // @[MuxLiteral.scala:49:48]
wire out_rimask_109 = |_out_rimask_T_109; // @[RegisterRouter.scala:87:24]
wire out_wimask_109 = &_out_wimask_T_109; // @[RegisterRouter.scala:87:24]
wire out_romask_109 = |_out_romask_T_109; // @[RegisterRouter.scala:87:24]
wire out_womask_109 = &_out_womask_T_109; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_109 = out_rivalid_109 & out_rimask_109; // @[RegisterRouter.scala:87:24]
wire _out_T_1208 = out_f_rivalid_109; // @[RegisterRouter.scala:87:24]
wire out_f_roready_109 = out_roready_109 & out_romask_109; // @[RegisterRouter.scala:87:24]
wire _out_T_1209 = out_f_roready_109; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_109 = out_wivalid_109 & out_wimask_109; // @[RegisterRouter.scala:87:24]
wire out_f_woready_109 = out_woready_109 & out_womask_109; // @[RegisterRouter.scala:87:24]
wire _out_T_1210 = ~out_rimask_109; // @[RegisterRouter.scala:87:24]
wire _out_T_1211 = ~out_wimask_109; // @[RegisterRouter.scala:87:24]
wire _out_T_1212 = ~out_romask_109; // @[RegisterRouter.scala:87:24]
wire _out_T_1213 = ~out_womask_109; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_rimask_T_110 = out_frontMask[7:4]; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_wimask_T_110 = out_frontMask[7:4]; // @[RegisterRouter.scala:87:24]
wire out_rimask_110 = |_out_rimask_T_110; // @[RegisterRouter.scala:87:24]
wire out_wimask_110 = &_out_wimask_T_110; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_romask_T_110 = out_backMask[7:4]; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_womask_T_110 = out_backMask[7:4]; // @[RegisterRouter.scala:87:24]
wire out_romask_110 = |_out_romask_T_110; // @[RegisterRouter.scala:87:24]
wire out_womask_110 = &_out_womask_T_110; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_110 = out_rivalid_110 & out_rimask_110; // @[RegisterRouter.scala:87:24]
wire _out_T_1217 = out_f_rivalid_110; // @[RegisterRouter.scala:87:24]
wire out_f_roready_110 = out_roready_110 & out_romask_110; // @[RegisterRouter.scala:87:24]
wire _out_T_1218 = out_f_roready_110; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_110 = out_wivalid_110 & out_wimask_110; // @[RegisterRouter.scala:87:24]
wire out_f_woready_110 = out_woready_110 & out_womask_110; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_T_1216 = out_front_bits_data[7:4]; // @[RegisterRouter.scala:87:24]
wire _out_T_1219 = ~out_rimask_110; // @[RegisterRouter.scala:87:24]
wire _out_T_1220 = ~out_wimask_110; // @[RegisterRouter.scala:87:24]
wire _out_T_1221 = ~out_romask_110; // @[RegisterRouter.scala:87:24]
wire _out_T_1222 = ~out_womask_110; // @[RegisterRouter.scala:87:24]
wire [2:0] _out_rimask_T_111 = out_frontMask[10:8]; // @[RegisterRouter.scala:87:24]
wire [2:0] _out_wimask_T_111 = out_frontMask[10:8]; // @[RegisterRouter.scala:87:24]
wire out_rimask_111 = |_out_rimask_T_111; // @[RegisterRouter.scala:87:24]
wire out_wimask_111 = &_out_wimask_T_111; // @[RegisterRouter.scala:87:24]
wire [2:0] _out_romask_T_111 = out_backMask[10:8]; // @[RegisterRouter.scala:87:24]
wire [2:0] _out_womask_T_111 = out_backMask[10:8]; // @[RegisterRouter.scala:87:24]
wire out_romask_111 = |_out_romask_T_111; // @[RegisterRouter.scala:87:24]
wire out_womask_111 = &_out_womask_T_111; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_111 = out_rivalid_111 & out_rimask_111; // @[RegisterRouter.scala:87:24]
wire _out_T_1226 = out_f_rivalid_111; // @[RegisterRouter.scala:87:24]
wire out_f_roready_111 = out_roready_111 & out_romask_111; // @[RegisterRouter.scala:87:24]
wire _out_T_1227 = out_f_roready_111; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_111 = out_wivalid_111 & out_wimask_111; // @[RegisterRouter.scala:87:24]
wire _out_T_1228 = out_f_wivalid_111; // @[RegisterRouter.scala:87:24]
assign out_f_woready_111 = out_woready_111 & out_womask_111; // @[RegisterRouter.scala:87:24]
assign ABSTRACTCSWrEnMaybe = out_f_woready_111; // @[RegisterRouter.scala:87:24]
wire _out_T_1229 = out_f_woready_111; // @[RegisterRouter.scala:87:24]
assign _out_T_1225 = out_front_bits_data[10:8]; // @[RegisterRouter.scala:87:24]
assign ABSTRACTCSWrData_cmderr = _out_T_1225; // @[RegisterRouter.scala:87:24]
wire _out_T_1230 = ~out_rimask_111; // @[RegisterRouter.scala:87:24]
wire _out_T_1231 = ~out_wimask_111; // @[RegisterRouter.scala:87:24]
wire _out_T_1232 = ~out_romask_111; // @[RegisterRouter.scala:87:24]
wire _out_T_1233 = ~out_womask_111; // @[RegisterRouter.scala:87:24]
wire [10:0] out_prepend_86 = {ABSTRACTCSRdData_cmderr, 8'h8}; // @[RegisterRouter.scala:87:24]
wire [10:0] _out_T_1234 = out_prepend_86; // @[RegisterRouter.scala:87:24]
wire [10:0] _out_T_1235 = _out_T_1234; // @[RegisterRouter.scala:87:24]
wire [10:0] _out_prepend_T_87 = _out_T_1235; // @[RegisterRouter.scala:87:24]
wire out_rimask_112 = _out_rimask_T_112; // @[RegisterRouter.scala:87:24]
wire out_wimask_112 = _out_wimask_T_112; // @[RegisterRouter.scala:87:24]
wire out_romask_112 = _out_romask_T_112; // @[RegisterRouter.scala:87:24]
wire out_womask_112 = _out_womask_T_112; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_112 = out_rivalid_112 & out_rimask_112; // @[RegisterRouter.scala:87:24]
wire _out_T_1237 = out_f_rivalid_112; // @[RegisterRouter.scala:87:24]
wire out_f_roready_112 = out_roready_112 & out_romask_112; // @[RegisterRouter.scala:87:24]
wire _out_T_1238 = out_f_roready_112; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_112 = out_wivalid_112 & out_wimask_112; // @[RegisterRouter.scala:87:24]
wire out_f_woready_112 = out_woready_112 & out_womask_112; // @[RegisterRouter.scala:87:24]
wire _out_T_1239 = ~out_rimask_112; // @[RegisterRouter.scala:87:24]
wire _out_T_1240 = ~out_wimask_112; // @[RegisterRouter.scala:87:24]
wire _out_T_1241 = ~out_romask_112; // @[RegisterRouter.scala:87:24]
wire _out_T_1242 = ~out_womask_112; // @[RegisterRouter.scala:87:24]
wire [11:0] out_prepend_87 = {1'h0, _out_prepend_T_87}; // @[RegisterRouter.scala:87:24]
wire [11:0] _out_T_1243 = out_prepend_87; // @[RegisterRouter.scala:87:24]
wire [11:0] _out_T_1244 = _out_T_1243; // @[RegisterRouter.scala:87:24]
wire [11:0] _out_prepend_T_88 = _out_T_1244; // @[RegisterRouter.scala:87:24]
wire out_rimask_113 = _out_rimask_T_113; // @[RegisterRouter.scala:87:24]
wire out_wimask_113 = _out_wimask_T_113; // @[RegisterRouter.scala:87:24]
wire out_romask_113 = _out_romask_T_113; // @[RegisterRouter.scala:87:24]
wire out_womask_113 = _out_womask_T_113; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_113 = out_rivalid_113 & out_rimask_113; // @[RegisterRouter.scala:87:24]
wire _out_T_1246 = out_f_rivalid_113; // @[RegisterRouter.scala:87:24]
wire out_f_roready_113 = out_roready_113 & out_romask_113; // @[RegisterRouter.scala:87:24]
wire _out_T_1247 = out_f_roready_113; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_113 = out_wivalid_113 & out_wimask_113; // @[RegisterRouter.scala:87:24]
wire out_f_woready_113 = out_woready_113 & out_womask_113; // @[RegisterRouter.scala:87:24]
wire _out_T_1248 = ~out_rimask_113; // @[RegisterRouter.scala:87:24]
wire _out_T_1249 = ~out_wimask_113; // @[RegisterRouter.scala:87:24]
wire _out_T_1250 = ~out_romask_113; // @[RegisterRouter.scala:87:24]
wire _out_T_1251 = ~out_womask_113; // @[RegisterRouter.scala:87:24]
wire [12:0] out_prepend_88 = {ABSTRACTCSRdData_busy, _out_prepend_T_88}; // @[RegisterRouter.scala:87:24]
wire [12:0] _out_T_1252 = out_prepend_88; // @[RegisterRouter.scala:87:24]
wire [12:0] _out_T_1253 = _out_T_1252; // @[RegisterRouter.scala:87:24]
wire [12:0] _out_prepend_T_89 = _out_T_1253; // @[RegisterRouter.scala:87:24]
wire [10:0] _out_rimask_T_114 = out_frontMask[23:13]; // @[RegisterRouter.scala:87:24]
wire [10:0] _out_wimask_T_114 = out_frontMask[23:13]; // @[RegisterRouter.scala:87:24]
wire out_rimask_114 = |_out_rimask_T_114; // @[RegisterRouter.scala:87:24]
wire out_wimask_114 = &_out_wimask_T_114; // @[RegisterRouter.scala:87:24]
wire [10:0] _out_romask_T_114 = out_backMask[23:13]; // @[RegisterRouter.scala:87:24]
wire [10:0] _out_womask_T_114 = out_backMask[23:13]; // @[RegisterRouter.scala:87:24]
wire out_romask_114 = |_out_romask_T_114; // @[RegisterRouter.scala:87:24]
wire out_womask_114 = &_out_womask_T_114; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_114 = out_rivalid_114 & out_rimask_114; // @[RegisterRouter.scala:87:24]
wire _out_T_1255 = out_f_rivalid_114; // @[RegisterRouter.scala:87:24]
wire out_f_roready_114 = out_roready_114 & out_romask_114; // @[RegisterRouter.scala:87:24]
wire _out_T_1256 = out_f_roready_114; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_114 = out_wivalid_114 & out_wimask_114; // @[RegisterRouter.scala:87:24]
wire out_f_woready_114 = out_woready_114 & out_womask_114; // @[RegisterRouter.scala:87:24]
wire [10:0] _out_T_1254 = out_front_bits_data[23:13]; // @[RegisterRouter.scala:87:24]
wire _out_T_1257 = ~out_rimask_114; // @[RegisterRouter.scala:87:24]
wire _out_T_1258 = ~out_wimask_114; // @[RegisterRouter.scala:87:24]
wire _out_T_1259 = ~out_romask_114; // @[RegisterRouter.scala:87:24]
wire _out_T_1260 = ~out_womask_114; // @[RegisterRouter.scala:87:24]
wire [13:0] out_prepend_89 = {1'h0, _out_prepend_T_89}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_1261 = {10'h0, out_prepend_89}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_1262 = _out_T_1261; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_90 = _out_T_1262; // @[RegisterRouter.scala:87:24]
wire [4:0] _out_rimask_T_115 = out_frontMask[28:24]; // @[RegisterRouter.scala:87:24]
wire [4:0] _out_wimask_T_115 = out_frontMask[28:24]; // @[RegisterRouter.scala:87:24]
wire out_rimask_115 = |_out_rimask_T_115; // @[RegisterRouter.scala:87:24]
wire out_wimask_115 = &_out_wimask_T_115; // @[RegisterRouter.scala:87:24]
wire [4:0] _out_romask_T_115 = out_backMask[28:24]; // @[RegisterRouter.scala:87:24]
wire [4:0] _out_womask_T_115 = out_backMask[28:24]; // @[RegisterRouter.scala:87:24]
wire out_romask_115 = |_out_romask_T_115; // @[RegisterRouter.scala:87:24]
wire out_womask_115 = &_out_womask_T_115; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_115 = out_rivalid_115 & out_rimask_115; // @[RegisterRouter.scala:87:24]
wire _out_T_1264 = out_f_rivalid_115; // @[RegisterRouter.scala:87:24]
wire out_f_roready_115 = out_roready_115 & out_romask_115; // @[RegisterRouter.scala:87:24]
wire _out_T_1265 = out_f_roready_115; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_115 = out_wivalid_115 & out_wimask_115; // @[RegisterRouter.scala:87:24]
wire out_f_woready_115 = out_woready_115 & out_womask_115; // @[RegisterRouter.scala:87:24]
wire [4:0] _out_T_1263 = out_front_bits_data[28:24]; // @[RegisterRouter.scala:87:24]
wire _out_T_1266 = ~out_rimask_115; // @[RegisterRouter.scala:87:24]
wire _out_T_1267 = ~out_wimask_115; // @[RegisterRouter.scala:87:24]
wire _out_T_1268 = ~out_romask_115; // @[RegisterRouter.scala:87:24]
wire _out_T_1269 = ~out_womask_115; // @[RegisterRouter.scala:87:24]
wire [28:0] out_prepend_90 = {5'h10, _out_prepend_T_90}; // @[RegisterRouter.scala:87:24]
wire [28:0] _out_T_1270 = out_prepend_90; // @[RegisterRouter.scala:87:24]
wire [28:0] _out_T_1271 = _out_T_1270; // @[RegisterRouter.scala:87:24]
wire out_rimask_116 = |_out_rimask_T_116; // @[RegisterRouter.scala:87:24]
wire out_wimask_116 = &_out_wimask_T_116; // @[RegisterRouter.scala:87:24]
wire out_romask_116 = |_out_romask_T_116; // @[RegisterRouter.scala:87:24]
wire out_womask_116 = &_out_womask_T_116; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_116 = out_rivalid_116 & out_rimask_116; // @[RegisterRouter.scala:87:24]
wire _out_T_1273 = out_f_rivalid_116; // @[RegisterRouter.scala:87:24]
assign out_f_roready_116 = out_roready_116 & out_romask_116; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_48 = out_f_roready_116; // @[RegisterRouter.scala:87:24]
wire _out_T_1274 = out_f_roready_116; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_116 = out_wivalid_116 & out_wimask_116; // @[RegisterRouter.scala:87:24]
wire _out_T_1275 = out_f_wivalid_116; // @[RegisterRouter.scala:87:24]
assign out_f_woready_116 = out_woready_116 & out_womask_116; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_48 = out_f_woready_116; // @[RegisterRouter.scala:87:24]
wire _out_T_1276 = out_f_woready_116; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_48 = out_f_woready_116 ? _out_T_1272 : programBufferMem_48; // @[RegisterRouter.scala:87:24]
wire _out_T_1277 = ~out_rimask_116; // @[RegisterRouter.scala:87:24]
wire _out_T_1278 = ~out_wimask_116; // @[RegisterRouter.scala:87:24]
wire _out_T_1279 = ~out_romask_116; // @[RegisterRouter.scala:87:24]
wire _out_T_1280 = ~out_womask_116; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1282 = _out_T_1281; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_91 = _out_T_1282; // @[RegisterRouter.scala:87:24]
wire out_rimask_117 = |_out_rimask_T_117; // @[RegisterRouter.scala:87:24]
wire out_wimask_117 = &_out_wimask_T_117; // @[RegisterRouter.scala:87:24]
wire out_romask_117 = |_out_romask_T_117; // @[RegisterRouter.scala:87:24]
wire out_womask_117 = &_out_womask_T_117; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_117 = out_rivalid_117 & out_rimask_117; // @[RegisterRouter.scala:87:24]
wire _out_T_1284 = out_f_rivalid_117; // @[RegisterRouter.scala:87:24]
assign out_f_roready_117 = out_roready_117 & out_romask_117; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_49 = out_f_roready_117; // @[RegisterRouter.scala:87:24]
wire _out_T_1285 = out_f_roready_117; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_117 = out_wivalid_117 & out_wimask_117; // @[RegisterRouter.scala:87:24]
wire _out_T_1286 = out_f_wivalid_117; // @[RegisterRouter.scala:87:24]
assign out_f_woready_117 = out_woready_117 & out_womask_117; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_49 = out_f_woready_117; // @[RegisterRouter.scala:87:24]
wire _out_T_1287 = out_f_woready_117; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_49 = out_f_woready_117 ? _out_T_1283 : programBufferMem_49; // @[RegisterRouter.scala:87:24]
wire _out_T_1288 = ~out_rimask_117; // @[RegisterRouter.scala:87:24]
wire _out_T_1289 = ~out_wimask_117; // @[RegisterRouter.scala:87:24]
wire _out_T_1290 = ~out_romask_117; // @[RegisterRouter.scala:87:24]
wire _out_T_1291 = ~out_womask_117; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_91 = {programBufferMem_49, _out_prepend_T_91}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_1292 = out_prepend_91; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_1293 = _out_T_1292; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_92 = _out_T_1293; // @[RegisterRouter.scala:87:24]
wire out_rimask_118 = |_out_rimask_T_118; // @[RegisterRouter.scala:87:24]
wire out_wimask_118 = &_out_wimask_T_118; // @[RegisterRouter.scala:87:24]
wire out_romask_118 = |_out_romask_T_118; // @[RegisterRouter.scala:87:24]
wire out_womask_118 = &_out_womask_T_118; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_118 = out_rivalid_118 & out_rimask_118; // @[RegisterRouter.scala:87:24]
wire _out_T_1295 = out_f_rivalid_118; // @[RegisterRouter.scala:87:24]
assign out_f_roready_118 = out_roready_118 & out_romask_118; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_50 = out_f_roready_118; // @[RegisterRouter.scala:87:24]
wire _out_T_1296 = out_f_roready_118; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_118 = out_wivalid_118 & out_wimask_118; // @[RegisterRouter.scala:87:24]
wire _out_T_1297 = out_f_wivalid_118; // @[RegisterRouter.scala:87:24]
assign out_f_woready_118 = out_woready_118 & out_womask_118; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_50 = out_f_woready_118; // @[RegisterRouter.scala:87:24]
wire _out_T_1298 = out_f_woready_118; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_50 = out_f_woready_118 ? _out_T_1294 : programBufferMem_50; // @[RegisterRouter.scala:87:24]
wire _out_T_1299 = ~out_rimask_118; // @[RegisterRouter.scala:87:24]
wire _out_T_1300 = ~out_wimask_118; // @[RegisterRouter.scala:87:24]
wire _out_T_1301 = ~out_romask_118; // @[RegisterRouter.scala:87:24]
wire _out_T_1302 = ~out_womask_118; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_92 = {programBufferMem_50, _out_prepend_T_92}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_1303 = out_prepend_92; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_1304 = _out_T_1303; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_93 = _out_T_1304; // @[RegisterRouter.scala:87:24]
wire out_rimask_119 = |_out_rimask_T_119; // @[RegisterRouter.scala:87:24]
wire out_wimask_119 = &_out_wimask_T_119; // @[RegisterRouter.scala:87:24]
wire out_romask_119 = |_out_romask_T_119; // @[RegisterRouter.scala:87:24]
wire out_womask_119 = &_out_womask_T_119; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_119 = out_rivalid_119 & out_rimask_119; // @[RegisterRouter.scala:87:24]
wire _out_T_1306 = out_f_rivalid_119; // @[RegisterRouter.scala:87:24]
assign out_f_roready_119 = out_roready_119 & out_romask_119; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_51 = out_f_roready_119; // @[RegisterRouter.scala:87:24]
wire _out_T_1307 = out_f_roready_119; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_119 = out_wivalid_119 & out_wimask_119; // @[RegisterRouter.scala:87:24]
wire _out_T_1308 = out_f_wivalid_119; // @[RegisterRouter.scala:87:24]
assign out_f_woready_119 = out_woready_119 & out_womask_119; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_51 = out_f_woready_119; // @[RegisterRouter.scala:87:24]
wire _out_T_1309 = out_f_woready_119; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_51 = out_f_woready_119 ? _out_T_1305 : programBufferMem_51; // @[RegisterRouter.scala:87:24]
wire _out_T_1310 = ~out_rimask_119; // @[RegisterRouter.scala:87:24]
wire _out_T_1311 = ~out_wimask_119; // @[RegisterRouter.scala:87:24]
wire _out_T_1312 = ~out_romask_119; // @[RegisterRouter.scala:87:24]
wire _out_T_1313 = ~out_womask_119; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_93 = {programBufferMem_51, _out_prepend_T_93}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_1314 = out_prepend_93; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_1315 = _out_T_1314; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_out_bits_data_WIRE_1_44 = _out_T_1315; // @[MuxLiteral.scala:49:48]
wire out_rimask_120 = |_out_rimask_T_120; // @[RegisterRouter.scala:87:24]
wire out_wimask_120 = &_out_wimask_T_120; // @[RegisterRouter.scala:87:24]
wire out_romask_120 = |_out_romask_T_120; // @[RegisterRouter.scala:87:24]
wire out_womask_120 = &_out_womask_T_120; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_120 = out_rivalid_120 & out_rimask_120; // @[RegisterRouter.scala:87:24]
wire _out_T_1317 = out_f_rivalid_120; // @[RegisterRouter.scala:87:24]
assign out_f_roready_120 = out_roready_120 & out_romask_120; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataRdEn_12 = out_f_roready_120; // @[RegisterRouter.scala:87:24]
wire _out_T_1318 = out_f_roready_120; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_120 = out_wivalid_120 & out_wimask_120; // @[RegisterRouter.scala:87:24]
wire _out_T_1319 = out_f_wivalid_120; // @[RegisterRouter.scala:87:24]
assign out_f_woready_120 = out_woready_120 & out_womask_120; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataWrEnMaybe_12 = out_f_woready_120; // @[RegisterRouter.scala:87:24]
wire _out_T_1320 = out_f_woready_120; // @[RegisterRouter.scala:87:24]
assign abstractDataNxt_12 = out_f_woready_120 ? _out_T_1316 : abstractDataMem_12; // @[RegisterRouter.scala:87:24]
wire _out_T_1321 = ~out_rimask_120; // @[RegisterRouter.scala:87:24]
wire _out_T_1322 = ~out_wimask_120; // @[RegisterRouter.scala:87:24]
wire _out_T_1323 = ~out_romask_120; // @[RegisterRouter.scala:87:24]
wire _out_T_1324 = ~out_womask_120; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1326 = _out_T_1325; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_94 = _out_T_1326; // @[RegisterRouter.scala:87:24]
wire out_rimask_121 = |_out_rimask_T_121; // @[RegisterRouter.scala:87:24]
wire out_wimask_121 = &_out_wimask_T_121; // @[RegisterRouter.scala:87:24]
wire out_romask_121 = |_out_romask_T_121; // @[RegisterRouter.scala:87:24]
wire out_womask_121 = &_out_womask_T_121; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_121 = out_rivalid_121 & out_rimask_121; // @[RegisterRouter.scala:87:24]
wire _out_T_1328 = out_f_rivalid_121; // @[RegisterRouter.scala:87:24]
assign out_f_roready_121 = out_roready_121 & out_romask_121; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataRdEn_13 = out_f_roready_121; // @[RegisterRouter.scala:87:24]
wire _out_T_1329 = out_f_roready_121; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_121 = out_wivalid_121 & out_wimask_121; // @[RegisterRouter.scala:87:24]
wire _out_T_1330 = out_f_wivalid_121; // @[RegisterRouter.scala:87:24]
assign out_f_woready_121 = out_woready_121 & out_womask_121; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataWrEnMaybe_13 = out_f_woready_121; // @[RegisterRouter.scala:87:24]
wire _out_T_1331 = out_f_woready_121; // @[RegisterRouter.scala:87:24]
assign abstractDataNxt_13 = out_f_woready_121 ? _out_T_1327 : abstractDataMem_13; // @[RegisterRouter.scala:87:24]
wire _out_T_1332 = ~out_rimask_121; // @[RegisterRouter.scala:87:24]
wire _out_T_1333 = ~out_wimask_121; // @[RegisterRouter.scala:87:24]
wire _out_T_1334 = ~out_romask_121; // @[RegisterRouter.scala:87:24]
wire _out_T_1335 = ~out_womask_121; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_94 = {abstractDataMem_13, _out_prepend_T_94}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_1336 = out_prepend_94; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_1337 = _out_T_1336; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_95 = _out_T_1337; // @[RegisterRouter.scala:87:24]
wire out_rimask_122 = |_out_rimask_T_122; // @[RegisterRouter.scala:87:24]
wire out_wimask_122 = &_out_wimask_T_122; // @[RegisterRouter.scala:87:24]
wire out_romask_122 = |_out_romask_T_122; // @[RegisterRouter.scala:87:24]
wire out_womask_122 = &_out_womask_T_122; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_122 = out_rivalid_122 & out_rimask_122; // @[RegisterRouter.scala:87:24]
wire _out_T_1339 = out_f_rivalid_122; // @[RegisterRouter.scala:87:24]
assign out_f_roready_122 = out_roready_122 & out_romask_122; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataRdEn_14 = out_f_roready_122; // @[RegisterRouter.scala:87:24]
wire _out_T_1340 = out_f_roready_122; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_122 = out_wivalid_122 & out_wimask_122; // @[RegisterRouter.scala:87:24]
wire _out_T_1341 = out_f_wivalid_122; // @[RegisterRouter.scala:87:24]
assign out_f_woready_122 = out_woready_122 & out_womask_122; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataWrEnMaybe_14 = out_f_woready_122; // @[RegisterRouter.scala:87:24]
wire _out_T_1342 = out_f_woready_122; // @[RegisterRouter.scala:87:24]
assign abstractDataNxt_14 = out_f_woready_122 ? _out_T_1338 : abstractDataMem_14; // @[RegisterRouter.scala:87:24]
wire _out_T_1343 = ~out_rimask_122; // @[RegisterRouter.scala:87:24]
wire _out_T_1344 = ~out_wimask_122; // @[RegisterRouter.scala:87:24]
wire _out_T_1345 = ~out_romask_122; // @[RegisterRouter.scala:87:24]
wire _out_T_1346 = ~out_womask_122; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_95 = {abstractDataMem_14, _out_prepend_T_95}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_1347 = out_prepend_95; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_1348 = _out_T_1347; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_96 = _out_T_1348; // @[RegisterRouter.scala:87:24]
wire out_rimask_123 = |_out_rimask_T_123; // @[RegisterRouter.scala:87:24]
wire out_wimask_123 = &_out_wimask_T_123; // @[RegisterRouter.scala:87:24]
wire out_romask_123 = |_out_romask_T_123; // @[RegisterRouter.scala:87:24]
wire out_womask_123 = &_out_womask_T_123; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_123 = out_rivalid_123 & out_rimask_123; // @[RegisterRouter.scala:87:24]
wire _out_T_1350 = out_f_rivalid_123; // @[RegisterRouter.scala:87:24]
assign out_f_roready_123 = out_roready_123 & out_romask_123; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataRdEn_15 = out_f_roready_123; // @[RegisterRouter.scala:87:24]
wire _out_T_1351 = out_f_roready_123; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_123 = out_wivalid_123 & out_wimask_123; // @[RegisterRouter.scala:87:24]
wire _out_T_1352 = out_f_wivalid_123; // @[RegisterRouter.scala:87:24]
assign out_f_woready_123 = out_woready_123 & out_womask_123; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataWrEnMaybe_15 = out_f_woready_123; // @[RegisterRouter.scala:87:24]
wire _out_T_1353 = out_f_woready_123; // @[RegisterRouter.scala:87:24]
assign abstractDataNxt_15 = out_f_woready_123 ? _out_T_1349 : abstractDataMem_15; // @[RegisterRouter.scala:87:24]
wire _out_T_1354 = ~out_rimask_123; // @[RegisterRouter.scala:87:24]
wire _out_T_1355 = ~out_wimask_123; // @[RegisterRouter.scala:87:24]
wire _out_T_1356 = ~out_romask_123; // @[RegisterRouter.scala:87:24]
wire _out_T_1357 = ~out_womask_123; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_96 = {abstractDataMem_15, _out_prepend_T_96}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_1358 = out_prepend_96; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_1359 = _out_T_1358; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_out_bits_data_WIRE_1_7 = _out_T_1359; // @[MuxLiteral.scala:49:48]
wire out_rimask_124 = |_out_rimask_T_124; // @[RegisterRouter.scala:87:24]
wire out_wimask_124 = &_out_wimask_T_124; // @[RegisterRouter.scala:87:24]
wire out_romask_124 = |_out_romask_T_124; // @[RegisterRouter.scala:87:24]
wire out_womask_124 = &_out_womask_T_124; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_124 = out_rivalid_124 & out_rimask_124; // @[RegisterRouter.scala:87:24]
wire _out_T_1361 = out_f_rivalid_124; // @[RegisterRouter.scala:87:24]
assign out_f_roready_124 = out_roready_124 & out_romask_124; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_28 = out_f_roready_124; // @[RegisterRouter.scala:87:24]
wire _out_T_1362 = out_f_roready_124; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_124 = out_wivalid_124 & out_wimask_124; // @[RegisterRouter.scala:87:24]
wire _out_T_1363 = out_f_wivalid_124; // @[RegisterRouter.scala:87:24]
assign out_f_woready_124 = out_woready_124 & out_womask_124; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_28 = out_f_woready_124; // @[RegisterRouter.scala:87:24]
wire _out_T_1364 = out_f_woready_124; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_28 = out_f_woready_124 ? _out_T_1360 : programBufferMem_28; // @[RegisterRouter.scala:87:24]
wire _out_T_1365 = ~out_rimask_124; // @[RegisterRouter.scala:87:24]
wire _out_T_1366 = ~out_wimask_124; // @[RegisterRouter.scala:87:24]
wire _out_T_1367 = ~out_romask_124; // @[RegisterRouter.scala:87:24]
wire _out_T_1368 = ~out_womask_124; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1370 = _out_T_1369; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_97 = _out_T_1370; // @[RegisterRouter.scala:87:24]
wire out_rimask_125 = |_out_rimask_T_125; // @[RegisterRouter.scala:87:24]
wire out_wimask_125 = &_out_wimask_T_125; // @[RegisterRouter.scala:87:24]
wire out_romask_125 = |_out_romask_T_125; // @[RegisterRouter.scala:87:24]
wire out_womask_125 = &_out_womask_T_125; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_125 = out_rivalid_125 & out_rimask_125; // @[RegisterRouter.scala:87:24]
wire _out_T_1372 = out_f_rivalid_125; // @[RegisterRouter.scala:87:24]
assign out_f_roready_125 = out_roready_125 & out_romask_125; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_29 = out_f_roready_125; // @[RegisterRouter.scala:87:24]
wire _out_T_1373 = out_f_roready_125; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_125 = out_wivalid_125 & out_wimask_125; // @[RegisterRouter.scala:87:24]
wire _out_T_1374 = out_f_wivalid_125; // @[RegisterRouter.scala:87:24]
assign out_f_woready_125 = out_woready_125 & out_womask_125; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_29 = out_f_woready_125; // @[RegisterRouter.scala:87:24]
wire _out_T_1375 = out_f_woready_125; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_29 = out_f_woready_125 ? _out_T_1371 : programBufferMem_29; // @[RegisterRouter.scala:87:24]
wire _out_T_1376 = ~out_rimask_125; // @[RegisterRouter.scala:87:24]
wire _out_T_1377 = ~out_wimask_125; // @[RegisterRouter.scala:87:24]
wire _out_T_1378 = ~out_romask_125; // @[RegisterRouter.scala:87:24]
wire _out_T_1379 = ~out_womask_125; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_97 = {programBufferMem_29, _out_prepend_T_97}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_1380 = out_prepend_97; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_1381 = _out_T_1380; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_98 = _out_T_1381; // @[RegisterRouter.scala:87:24]
wire out_rimask_126 = |_out_rimask_T_126; // @[RegisterRouter.scala:87:24]
wire out_wimask_126 = &_out_wimask_T_126; // @[RegisterRouter.scala:87:24]
wire out_romask_126 = |_out_romask_T_126; // @[RegisterRouter.scala:87:24]
wire out_womask_126 = &_out_womask_T_126; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_126 = out_rivalid_126 & out_rimask_126; // @[RegisterRouter.scala:87:24]
wire _out_T_1383 = out_f_rivalid_126; // @[RegisterRouter.scala:87:24]
assign out_f_roready_126 = out_roready_126 & out_romask_126; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_30 = out_f_roready_126; // @[RegisterRouter.scala:87:24]
wire _out_T_1384 = out_f_roready_126; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_126 = out_wivalid_126 & out_wimask_126; // @[RegisterRouter.scala:87:24]
wire _out_T_1385 = out_f_wivalid_126; // @[RegisterRouter.scala:87:24]
assign out_f_woready_126 = out_woready_126 & out_womask_126; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_30 = out_f_woready_126; // @[RegisterRouter.scala:87:24]
wire _out_T_1386 = out_f_woready_126; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_30 = out_f_woready_126 ? _out_T_1382 : programBufferMem_30; // @[RegisterRouter.scala:87:24]
wire _out_T_1387 = ~out_rimask_126; // @[RegisterRouter.scala:87:24]
wire _out_T_1388 = ~out_wimask_126; // @[RegisterRouter.scala:87:24]
wire _out_T_1389 = ~out_romask_126; // @[RegisterRouter.scala:87:24]
wire _out_T_1390 = ~out_womask_126; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_98 = {programBufferMem_30, _out_prepend_T_98}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_1391 = out_prepend_98; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_1392 = _out_T_1391; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_99 = _out_T_1392; // @[RegisterRouter.scala:87:24]
wire out_rimask_127 = |_out_rimask_T_127; // @[RegisterRouter.scala:87:24]
wire out_wimask_127 = &_out_wimask_T_127; // @[RegisterRouter.scala:87:24]
wire out_romask_127 = |_out_romask_T_127; // @[RegisterRouter.scala:87:24]
wire out_womask_127 = &_out_womask_T_127; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_127 = out_rivalid_127 & out_rimask_127; // @[RegisterRouter.scala:87:24]
wire _out_T_1394 = out_f_rivalid_127; // @[RegisterRouter.scala:87:24]
assign out_f_roready_127 = out_roready_127 & out_romask_127; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_31 = out_f_roready_127; // @[RegisterRouter.scala:87:24]
wire _out_T_1395 = out_f_roready_127; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_127 = out_wivalid_127 & out_wimask_127; // @[RegisterRouter.scala:87:24]
wire _out_T_1396 = out_f_wivalid_127; // @[RegisterRouter.scala:87:24]
assign out_f_woready_127 = out_woready_127 & out_womask_127; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_31 = out_f_woready_127; // @[RegisterRouter.scala:87:24]
wire _out_T_1397 = out_f_woready_127; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_31 = out_f_woready_127 ? _out_T_1393 : programBufferMem_31; // @[RegisterRouter.scala:87:24]
wire _out_T_1398 = ~out_rimask_127; // @[RegisterRouter.scala:87:24]
wire _out_T_1399 = ~out_wimask_127; // @[RegisterRouter.scala:87:24]
wire _out_T_1400 = ~out_romask_127; // @[RegisterRouter.scala:87:24]
wire _out_T_1401 = ~out_womask_127; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_99 = {programBufferMem_31, _out_prepend_T_99}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_1402 = out_prepend_99; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_1403 = _out_T_1402; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_out_bits_data_WIRE_1_39 = _out_T_1403; // @[MuxLiteral.scala:49:48]
wire out_rimask_128 = |_out_rimask_T_128; // @[RegisterRouter.scala:87:24]
wire out_wimask_128 = &_out_wimask_T_128; // @[RegisterRouter.scala:87:24]
wire out_romask_128 = |_out_romask_T_128; // @[RegisterRouter.scala:87:24]
wire out_womask_128 = &_out_womask_T_128; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_128 = out_rivalid_128 & out_rimask_128; // @[RegisterRouter.scala:87:24]
wire _out_T_1405 = out_f_rivalid_128; // @[RegisterRouter.scala:87:24]
assign out_f_roready_128 = out_roready_128 & out_romask_128; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataRdEn_28 = out_f_roready_128; // @[RegisterRouter.scala:87:24]
wire _out_T_1406 = out_f_roready_128; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_128 = out_wivalid_128 & out_wimask_128; // @[RegisterRouter.scala:87:24]
wire _out_T_1407 = out_f_wivalid_128; // @[RegisterRouter.scala:87:24]
assign out_f_woready_128 = out_woready_128 & out_womask_128; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataWrEnMaybe_28 = out_f_woready_128; // @[RegisterRouter.scala:87:24]
wire _out_T_1408 = out_f_woready_128; // @[RegisterRouter.scala:87:24]
assign abstractDataNxt_28 = out_f_woready_128 ? _out_T_1404 : abstractDataMem_28; // @[RegisterRouter.scala:87:24]
wire _out_T_1409 = ~out_rimask_128; // @[RegisterRouter.scala:87:24]
wire _out_T_1410 = ~out_wimask_128; // @[RegisterRouter.scala:87:24]
wire _out_T_1411 = ~out_romask_128; // @[RegisterRouter.scala:87:24]
wire _out_T_1412 = ~out_womask_128; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1414 = _out_T_1413; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_100 = _out_T_1414; // @[RegisterRouter.scala:87:24]
wire out_rimask_129 = |_out_rimask_T_129; // @[RegisterRouter.scala:87:24]
wire out_wimask_129 = &_out_wimask_T_129; // @[RegisterRouter.scala:87:24]
wire out_romask_129 = |_out_romask_T_129; // @[RegisterRouter.scala:87:24]
wire out_womask_129 = &_out_womask_T_129; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_129 = out_rivalid_129 & out_rimask_129; // @[RegisterRouter.scala:87:24]
wire _out_T_1416 = out_f_rivalid_129; // @[RegisterRouter.scala:87:24]
assign out_f_roready_129 = out_roready_129 & out_romask_129; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataRdEn_29 = out_f_roready_129; // @[RegisterRouter.scala:87:24]
wire _out_T_1417 = out_f_roready_129; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_129 = out_wivalid_129 & out_wimask_129; // @[RegisterRouter.scala:87:24]
wire _out_T_1418 = out_f_wivalid_129; // @[RegisterRouter.scala:87:24]
assign out_f_woready_129 = out_woready_129 & out_womask_129; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataWrEnMaybe_29 = out_f_woready_129; // @[RegisterRouter.scala:87:24]
wire _out_T_1419 = out_f_woready_129; // @[RegisterRouter.scala:87:24]
assign abstractDataNxt_29 = out_f_woready_129 ? _out_T_1415 : abstractDataMem_29; // @[RegisterRouter.scala:87:24]
wire _out_T_1420 = ~out_rimask_129; // @[RegisterRouter.scala:87:24]
wire _out_T_1421 = ~out_wimask_129; // @[RegisterRouter.scala:87:24]
wire _out_T_1422 = ~out_romask_129; // @[RegisterRouter.scala:87:24]
wire _out_T_1423 = ~out_womask_129; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_100 = {abstractDataMem_29, _out_prepend_T_100}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_1424 = out_prepend_100; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_1425 = _out_T_1424; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_101 = _out_T_1425; // @[RegisterRouter.scala:87:24]
wire out_rimask_130 = |_out_rimask_T_130; // @[RegisterRouter.scala:87:24]
wire out_wimask_130 = &_out_wimask_T_130; // @[RegisterRouter.scala:87:24]
wire out_romask_130 = |_out_romask_T_130; // @[RegisterRouter.scala:87:24]
wire out_womask_130 = &_out_womask_T_130; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_130 = out_rivalid_130 & out_rimask_130; // @[RegisterRouter.scala:87:24]
wire _out_T_1427 = out_f_rivalid_130; // @[RegisterRouter.scala:87:24]
assign out_f_roready_130 = out_roready_130 & out_romask_130; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataRdEn_30 = out_f_roready_130; // @[RegisterRouter.scala:87:24]
wire _out_T_1428 = out_f_roready_130; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_130 = out_wivalid_130 & out_wimask_130; // @[RegisterRouter.scala:87:24]
wire _out_T_1429 = out_f_wivalid_130; // @[RegisterRouter.scala:87:24]
assign out_f_woready_130 = out_woready_130 & out_womask_130; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataWrEnMaybe_30 = out_f_woready_130; // @[RegisterRouter.scala:87:24]
wire _out_T_1430 = out_f_woready_130; // @[RegisterRouter.scala:87:24]
assign abstractDataNxt_30 = out_f_woready_130 ? _out_T_1426 : abstractDataMem_30; // @[RegisterRouter.scala:87:24]
wire _out_T_1431 = ~out_rimask_130; // @[RegisterRouter.scala:87:24]
wire _out_T_1432 = ~out_wimask_130; // @[RegisterRouter.scala:87:24]
wire _out_T_1433 = ~out_romask_130; // @[RegisterRouter.scala:87:24]
wire _out_T_1434 = ~out_womask_130; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_101 = {abstractDataMem_30, _out_prepend_T_101}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_1435 = out_prepend_101; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_1436 = _out_T_1435; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_102 = _out_T_1436; // @[RegisterRouter.scala:87:24]
wire out_rimask_131 = |_out_rimask_T_131; // @[RegisterRouter.scala:87:24]
wire out_wimask_131 = &_out_wimask_T_131; // @[RegisterRouter.scala:87:24]
wire out_romask_131 = |_out_romask_T_131; // @[RegisterRouter.scala:87:24]
wire out_womask_131 = &_out_womask_T_131; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_131 = out_rivalid_131 & out_rimask_131; // @[RegisterRouter.scala:87:24]
wire _out_T_1438 = out_f_rivalid_131; // @[RegisterRouter.scala:87:24]
assign out_f_roready_131 = out_roready_131 & out_romask_131; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataRdEn_31 = out_f_roready_131; // @[RegisterRouter.scala:87:24]
wire _out_T_1439 = out_f_roready_131; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_131 = out_wivalid_131 & out_wimask_131; // @[RegisterRouter.scala:87:24]
wire _out_T_1440 = out_f_wivalid_131; // @[RegisterRouter.scala:87:24]
assign out_f_woready_131 = out_woready_131 & out_womask_131; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataWrEnMaybe_31 = out_f_woready_131; // @[RegisterRouter.scala:87:24]
wire _out_T_1441 = out_f_woready_131; // @[RegisterRouter.scala:87:24]
assign abstractDataNxt_31 = out_f_woready_131 ? _out_T_1437 : abstractDataMem_31; // @[RegisterRouter.scala:87:24]
wire _out_T_1442 = ~out_rimask_131; // @[RegisterRouter.scala:87:24]
wire _out_T_1443 = ~out_wimask_131; // @[RegisterRouter.scala:87:24]
wire _out_T_1444 = ~out_romask_131; // @[RegisterRouter.scala:87:24]
wire _out_T_1445 = ~out_womask_131; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_102 = {abstractDataMem_31, _out_prepend_T_102}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_1446 = out_prepend_102; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_1447 = _out_T_1446; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_out_bits_data_WIRE_1_11 = _out_T_1447; // @[MuxLiteral.scala:49:48]
wire out_rimask_132 = |_out_rimask_T_132; // @[RegisterRouter.scala:87:24]
wire out_wimask_132 = &_out_wimask_T_132; // @[RegisterRouter.scala:87:24]
wire out_romask_132 = |_out_romask_T_132; // @[RegisterRouter.scala:87:24]
wire out_womask_132 = &_out_womask_T_132; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_132 = out_rivalid_132 & out_rimask_132; // @[RegisterRouter.scala:87:24]
wire _out_T_1449 = out_f_rivalid_132; // @[RegisterRouter.scala:87:24]
assign out_f_roready_132 = out_roready_132 & out_romask_132; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_44 = out_f_roready_132; // @[RegisterRouter.scala:87:24]
wire _out_T_1450 = out_f_roready_132; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_132 = out_wivalid_132 & out_wimask_132; // @[RegisterRouter.scala:87:24]
wire _out_T_1451 = out_f_wivalid_132; // @[RegisterRouter.scala:87:24]
assign out_f_woready_132 = out_woready_132 & out_womask_132; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_44 = out_f_woready_132; // @[RegisterRouter.scala:87:24]
wire _out_T_1452 = out_f_woready_132; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_44 = out_f_woready_132 ? _out_T_1448 : programBufferMem_44; // @[RegisterRouter.scala:87:24]
wire _out_T_1453 = ~out_rimask_132; // @[RegisterRouter.scala:87:24]
wire _out_T_1454 = ~out_wimask_132; // @[RegisterRouter.scala:87:24]
wire _out_T_1455 = ~out_romask_132; // @[RegisterRouter.scala:87:24]
wire _out_T_1456 = ~out_womask_132; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1458 = _out_T_1457; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_103 = _out_T_1458; // @[RegisterRouter.scala:87:24]
wire out_rimask_133 = |_out_rimask_T_133; // @[RegisterRouter.scala:87:24]
wire out_wimask_133 = &_out_wimask_T_133; // @[RegisterRouter.scala:87:24]
wire out_romask_133 = |_out_romask_T_133; // @[RegisterRouter.scala:87:24]
wire out_womask_133 = &_out_womask_T_133; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_133 = out_rivalid_133 & out_rimask_133; // @[RegisterRouter.scala:87:24]
wire _out_T_1460 = out_f_rivalid_133; // @[RegisterRouter.scala:87:24]
assign out_f_roready_133 = out_roready_133 & out_romask_133; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_45 = out_f_roready_133; // @[RegisterRouter.scala:87:24]
wire _out_T_1461 = out_f_roready_133; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_133 = out_wivalid_133 & out_wimask_133; // @[RegisterRouter.scala:87:24]
wire _out_T_1462 = out_f_wivalid_133; // @[RegisterRouter.scala:87:24]
assign out_f_woready_133 = out_woready_133 & out_womask_133; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_45 = out_f_woready_133; // @[RegisterRouter.scala:87:24]
wire _out_T_1463 = out_f_woready_133; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_45 = out_f_woready_133 ? _out_T_1459 : programBufferMem_45; // @[RegisterRouter.scala:87:24]
wire _out_T_1464 = ~out_rimask_133; // @[RegisterRouter.scala:87:24]
wire _out_T_1465 = ~out_wimask_133; // @[RegisterRouter.scala:87:24]
wire _out_T_1466 = ~out_romask_133; // @[RegisterRouter.scala:87:24]
wire _out_T_1467 = ~out_womask_133; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_103 = {programBufferMem_45, _out_prepend_T_103}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_1468 = out_prepend_103; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_1469 = _out_T_1468; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_104 = _out_T_1469; // @[RegisterRouter.scala:87:24]
wire out_rimask_134 = |_out_rimask_T_134; // @[RegisterRouter.scala:87:24]
wire out_wimask_134 = &_out_wimask_T_134; // @[RegisterRouter.scala:87:24]
wire out_romask_134 = |_out_romask_T_134; // @[RegisterRouter.scala:87:24]
wire out_womask_134 = &_out_womask_T_134; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_134 = out_rivalid_134 & out_rimask_134; // @[RegisterRouter.scala:87:24]
wire _out_T_1471 = out_f_rivalid_134; // @[RegisterRouter.scala:87:24]
assign out_f_roready_134 = out_roready_134 & out_romask_134; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_46 = out_f_roready_134; // @[RegisterRouter.scala:87:24]
wire _out_T_1472 = out_f_roready_134; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_134 = out_wivalid_134 & out_wimask_134; // @[RegisterRouter.scala:87:24]
wire _out_T_1473 = out_f_wivalid_134; // @[RegisterRouter.scala:87:24]
assign out_f_woready_134 = out_woready_134 & out_womask_134; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_46 = out_f_woready_134; // @[RegisterRouter.scala:87:24]
wire _out_T_1474 = out_f_woready_134; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_46 = out_f_woready_134 ? _out_T_1470 : programBufferMem_46; // @[RegisterRouter.scala:87:24]
wire _out_T_1475 = ~out_rimask_134; // @[RegisterRouter.scala:87:24]
wire _out_T_1476 = ~out_wimask_134; // @[RegisterRouter.scala:87:24]
wire _out_T_1477 = ~out_romask_134; // @[RegisterRouter.scala:87:24]
wire _out_T_1478 = ~out_womask_134; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_104 = {programBufferMem_46, _out_prepend_T_104}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_1479 = out_prepend_104; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_1480 = _out_T_1479; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_105 = _out_T_1480; // @[RegisterRouter.scala:87:24]
wire out_rimask_135 = |_out_rimask_T_135; // @[RegisterRouter.scala:87:24]
wire out_wimask_135 = &_out_wimask_T_135; // @[RegisterRouter.scala:87:24]
wire out_romask_135 = |_out_romask_T_135; // @[RegisterRouter.scala:87:24]
wire out_womask_135 = &_out_womask_T_135; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_135 = out_rivalid_135 & out_rimask_135; // @[RegisterRouter.scala:87:24]
wire _out_T_1482 = out_f_rivalid_135; // @[RegisterRouter.scala:87:24]
assign out_f_roready_135 = out_roready_135 & out_romask_135; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_47 = out_f_roready_135; // @[RegisterRouter.scala:87:24]
wire _out_T_1483 = out_f_roready_135; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_135 = out_wivalid_135 & out_wimask_135; // @[RegisterRouter.scala:87:24]
wire _out_T_1484 = out_f_wivalid_135; // @[RegisterRouter.scala:87:24]
assign out_f_woready_135 = out_woready_135 & out_womask_135; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_47 = out_f_woready_135; // @[RegisterRouter.scala:87:24]
wire _out_T_1485 = out_f_woready_135; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_47 = out_f_woready_135 ? _out_T_1481 : programBufferMem_47; // @[RegisterRouter.scala:87:24]
wire _out_T_1486 = ~out_rimask_135; // @[RegisterRouter.scala:87:24]
wire _out_T_1487 = ~out_wimask_135; // @[RegisterRouter.scala:87:24]
wire _out_T_1488 = ~out_romask_135; // @[RegisterRouter.scala:87:24]
wire _out_T_1489 = ~out_womask_135; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_105 = {programBufferMem_47, _out_prepend_T_105}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_1490 = out_prepend_105; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_1491 = _out_T_1490; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_out_bits_data_WIRE_1_43 = _out_T_1491; // @[MuxLiteral.scala:49:48]
wire out_rimask_136 = |_out_rimask_T_136; // @[RegisterRouter.scala:87:24]
wire out_wimask_136 = &_out_wimask_T_136; // @[RegisterRouter.scala:87:24]
wire out_romask_136 = |_out_romask_T_136; // @[RegisterRouter.scala:87:24]
wire out_womask_136 = &_out_womask_T_136; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_136 = out_rivalid_136 & out_rimask_136; // @[RegisterRouter.scala:87:24]
wire _out_T_1493 = out_f_rivalid_136; // @[RegisterRouter.scala:87:24]
assign out_f_roready_136 = out_roready_136 & out_romask_136; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_32 = out_f_roready_136; // @[RegisterRouter.scala:87:24]
wire _out_T_1494 = out_f_roready_136; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_136 = out_wivalid_136 & out_wimask_136; // @[RegisterRouter.scala:87:24]
wire _out_T_1495 = out_f_wivalid_136; // @[RegisterRouter.scala:87:24]
assign out_f_woready_136 = out_woready_136 & out_womask_136; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_32 = out_f_woready_136; // @[RegisterRouter.scala:87:24]
wire _out_T_1496 = out_f_woready_136; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_32 = out_f_woready_136 ? _out_T_1492 : programBufferMem_32; // @[RegisterRouter.scala:87:24]
wire _out_T_1497 = ~out_rimask_136; // @[RegisterRouter.scala:87:24]
wire _out_T_1498 = ~out_wimask_136; // @[RegisterRouter.scala:87:24]
wire _out_T_1499 = ~out_romask_136; // @[RegisterRouter.scala:87:24]
wire _out_T_1500 = ~out_womask_136; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1502 = _out_T_1501; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_106 = _out_T_1502; // @[RegisterRouter.scala:87:24]
wire out_rimask_137 = |_out_rimask_T_137; // @[RegisterRouter.scala:87:24]
wire out_wimask_137 = &_out_wimask_T_137; // @[RegisterRouter.scala:87:24]
wire out_romask_137 = |_out_romask_T_137; // @[RegisterRouter.scala:87:24]
wire out_womask_137 = &_out_womask_T_137; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_137 = out_rivalid_137 & out_rimask_137; // @[RegisterRouter.scala:87:24]
wire _out_T_1504 = out_f_rivalid_137; // @[RegisterRouter.scala:87:24]
assign out_f_roready_137 = out_roready_137 & out_romask_137; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_33 = out_f_roready_137; // @[RegisterRouter.scala:87:24]
wire _out_T_1505 = out_f_roready_137; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_137 = out_wivalid_137 & out_wimask_137; // @[RegisterRouter.scala:87:24]
wire _out_T_1506 = out_f_wivalid_137; // @[RegisterRouter.scala:87:24]
assign out_f_woready_137 = out_woready_137 & out_womask_137; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_33 = out_f_woready_137; // @[RegisterRouter.scala:87:24]
wire _out_T_1507 = out_f_woready_137; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_33 = out_f_woready_137 ? _out_T_1503 : programBufferMem_33; // @[RegisterRouter.scala:87:24]
wire _out_T_1508 = ~out_rimask_137; // @[RegisterRouter.scala:87:24]
wire _out_T_1509 = ~out_wimask_137; // @[RegisterRouter.scala:87:24]
wire _out_T_1510 = ~out_romask_137; // @[RegisterRouter.scala:87:24]
wire _out_T_1511 = ~out_womask_137; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_106 = {programBufferMem_33, _out_prepend_T_106}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_1512 = out_prepend_106; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_1513 = _out_T_1512; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_107 = _out_T_1513; // @[RegisterRouter.scala:87:24]
wire out_rimask_138 = |_out_rimask_T_138; // @[RegisterRouter.scala:87:24]
wire out_wimask_138 = &_out_wimask_T_138; // @[RegisterRouter.scala:87:24]
wire out_romask_138 = |_out_romask_T_138; // @[RegisterRouter.scala:87:24]
wire out_womask_138 = &_out_womask_T_138; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_138 = out_rivalid_138 & out_rimask_138; // @[RegisterRouter.scala:87:24]
wire _out_T_1515 = out_f_rivalid_138; // @[RegisterRouter.scala:87:24]
assign out_f_roready_138 = out_roready_138 & out_romask_138; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_34 = out_f_roready_138; // @[RegisterRouter.scala:87:24]
wire _out_T_1516 = out_f_roready_138; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_138 = out_wivalid_138 & out_wimask_138; // @[RegisterRouter.scala:87:24]
wire _out_T_1517 = out_f_wivalid_138; // @[RegisterRouter.scala:87:24]
assign out_f_woready_138 = out_woready_138 & out_womask_138; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_34 = out_f_woready_138; // @[RegisterRouter.scala:87:24]
wire _out_T_1518 = out_f_woready_138; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_34 = out_f_woready_138 ? _out_T_1514 : programBufferMem_34; // @[RegisterRouter.scala:87:24]
wire _out_T_1519 = ~out_rimask_138; // @[RegisterRouter.scala:87:24]
wire _out_T_1520 = ~out_wimask_138; // @[RegisterRouter.scala:87:24]
wire _out_T_1521 = ~out_romask_138; // @[RegisterRouter.scala:87:24]
wire _out_T_1522 = ~out_womask_138; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_107 = {programBufferMem_34, _out_prepend_T_107}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_1523 = out_prepend_107; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_1524 = _out_T_1523; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_108 = _out_T_1524; // @[RegisterRouter.scala:87:24]
wire out_rimask_139 = |_out_rimask_T_139; // @[RegisterRouter.scala:87:24]
wire out_wimask_139 = &_out_wimask_T_139; // @[RegisterRouter.scala:87:24]
wire out_romask_139 = |_out_romask_T_139; // @[RegisterRouter.scala:87:24]
wire out_womask_139 = &_out_womask_T_139; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_139 = out_rivalid_139 & out_rimask_139; // @[RegisterRouter.scala:87:24]
wire _out_T_1526 = out_f_rivalid_139; // @[RegisterRouter.scala:87:24]
assign out_f_roready_139 = out_roready_139 & out_romask_139; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_35 = out_f_roready_139; // @[RegisterRouter.scala:87:24]
wire _out_T_1527 = out_f_roready_139; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_139 = out_wivalid_139 & out_wimask_139; // @[RegisterRouter.scala:87:24]
wire _out_T_1528 = out_f_wivalid_139; // @[RegisterRouter.scala:87:24]
assign out_f_woready_139 = out_woready_139 & out_womask_139; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_35 = out_f_woready_139; // @[RegisterRouter.scala:87:24]
wire _out_T_1529 = out_f_woready_139; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_35 = out_f_woready_139 ? _out_T_1525 : programBufferMem_35; // @[RegisterRouter.scala:87:24]
wire _out_T_1530 = ~out_rimask_139; // @[RegisterRouter.scala:87:24]
wire _out_T_1531 = ~out_wimask_139; // @[RegisterRouter.scala:87:24]
wire _out_T_1532 = ~out_romask_139; // @[RegisterRouter.scala:87:24]
wire _out_T_1533 = ~out_womask_139; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_108 = {programBufferMem_35, _out_prepend_T_108}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_1534 = out_prepend_108; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_1535 = _out_T_1534; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_out_bits_data_WIRE_1_40 = _out_T_1535; // @[MuxLiteral.scala:49:48]
wire out_rimask_140 = |_out_rimask_T_140; // @[RegisterRouter.scala:87:24]
wire out_wimask_140 = &_out_wimask_T_140; // @[RegisterRouter.scala:87:24]
wire out_romask_140 = |_out_romask_T_140; // @[RegisterRouter.scala:87:24]
wire out_womask_140 = &_out_womask_T_140; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_140 = out_rivalid_140 & out_rimask_140; // @[RegisterRouter.scala:87:24]
wire _out_T_1537 = out_f_rivalid_140; // @[RegisterRouter.scala:87:24]
assign out_f_roready_140 = out_roready_140 & out_romask_140; // @[RegisterRouter.scala:87:24]
assign COMMANDRdEn = out_f_roready_140; // @[RegisterRouter.scala:87:24]
wire _out_T_1538 = out_f_roready_140; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_140 = out_wivalid_140 & out_wimask_140; // @[RegisterRouter.scala:87:24]
wire _out_T_1539 = out_f_wivalid_140; // @[RegisterRouter.scala:87:24]
assign out_f_woready_140 = out_woready_140 & out_womask_140; // @[RegisterRouter.scala:87:24]
assign COMMANDWrEnMaybe = out_f_woready_140; // @[RegisterRouter.scala:87:24]
wire _out_T_1540 = out_f_woready_140; // @[RegisterRouter.scala:87:24]
assign COMMANDWrDataVal = out_f_woready_140 ? _out_T_1536 : 32'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_1541 = ~out_rimask_140; // @[RegisterRouter.scala:87:24]
wire _out_T_1542 = ~out_wimask_140; // @[RegisterRouter.scala:87:24]
wire _out_T_1543 = ~out_romask_140; // @[RegisterRouter.scala:87:24]
wire _out_T_1544 = ~out_womask_140; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_1546 = _out_T_1545; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_out_bits_data_WIRE_1_23 = _out_T_1546; // @[MuxLiteral.scala:49:48]
wire out_rimask_141 = |_out_rimask_T_141; // @[RegisterRouter.scala:87:24]
wire out_wimask_141 = &_out_wimask_T_141; // @[RegisterRouter.scala:87:24]
wire out_romask_141 = |_out_romask_T_141; // @[RegisterRouter.scala:87:24]
wire out_womask_141 = &_out_womask_T_141; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_141 = out_rivalid_141 & out_rimask_141; // @[RegisterRouter.scala:87:24]
wire _out_T_1548 = out_f_rivalid_141; // @[RegisterRouter.scala:87:24]
assign out_f_roready_141 = out_roready_141 & out_romask_141; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_16 = out_f_roready_141; // @[RegisterRouter.scala:87:24]
wire _out_T_1549 = out_f_roready_141; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_141 = out_wivalid_141 & out_wimask_141; // @[RegisterRouter.scala:87:24]
wire _out_T_1550 = out_f_wivalid_141; // @[RegisterRouter.scala:87:24]
assign out_f_woready_141 = out_woready_141 & out_womask_141; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_16 = out_f_woready_141; // @[RegisterRouter.scala:87:24]
wire _out_T_1551 = out_f_woready_141; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_16 = out_f_woready_141 ? _out_T_1547 : programBufferMem_16; // @[RegisterRouter.scala:87:24]
wire _out_T_1552 = ~out_rimask_141; // @[RegisterRouter.scala:87:24]
wire _out_T_1553 = ~out_wimask_141; // @[RegisterRouter.scala:87:24]
wire _out_T_1554 = ~out_romask_141; // @[RegisterRouter.scala:87:24]
wire _out_T_1555 = ~out_womask_141; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1557 = _out_T_1556; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_109 = _out_T_1557; // @[RegisterRouter.scala:87:24]
wire out_rimask_142 = |_out_rimask_T_142; // @[RegisterRouter.scala:87:24]
wire out_wimask_142 = &_out_wimask_T_142; // @[RegisterRouter.scala:87:24]
wire out_romask_142 = |_out_romask_T_142; // @[RegisterRouter.scala:87:24]
wire out_womask_142 = &_out_womask_T_142; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_142 = out_rivalid_142 & out_rimask_142; // @[RegisterRouter.scala:87:24]
wire _out_T_1559 = out_f_rivalid_142; // @[RegisterRouter.scala:87:24]
assign out_f_roready_142 = out_roready_142 & out_romask_142; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_17 = out_f_roready_142; // @[RegisterRouter.scala:87:24]
wire _out_T_1560 = out_f_roready_142; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_142 = out_wivalid_142 & out_wimask_142; // @[RegisterRouter.scala:87:24]
wire _out_T_1561 = out_f_wivalid_142; // @[RegisterRouter.scala:87:24]
assign out_f_woready_142 = out_woready_142 & out_womask_142; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_17 = out_f_woready_142; // @[RegisterRouter.scala:87:24]
wire _out_T_1562 = out_f_woready_142; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_17 = out_f_woready_142 ? _out_T_1558 : programBufferMem_17; // @[RegisterRouter.scala:87:24]
wire _out_T_1563 = ~out_rimask_142; // @[RegisterRouter.scala:87:24]
wire _out_T_1564 = ~out_wimask_142; // @[RegisterRouter.scala:87:24]
wire _out_T_1565 = ~out_romask_142; // @[RegisterRouter.scala:87:24]
wire _out_T_1566 = ~out_womask_142; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_109 = {programBufferMem_17, _out_prepend_T_109}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_1567 = out_prepend_109; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_1568 = _out_T_1567; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_110 = _out_T_1568; // @[RegisterRouter.scala:87:24]
wire out_rimask_143 = |_out_rimask_T_143; // @[RegisterRouter.scala:87:24]
wire out_wimask_143 = &_out_wimask_T_143; // @[RegisterRouter.scala:87:24]
wire out_romask_143 = |_out_romask_T_143; // @[RegisterRouter.scala:87:24]
wire out_womask_143 = &_out_womask_T_143; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_143 = out_rivalid_143 & out_rimask_143; // @[RegisterRouter.scala:87:24]
wire _out_T_1570 = out_f_rivalid_143; // @[RegisterRouter.scala:87:24]
assign out_f_roready_143 = out_roready_143 & out_romask_143; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_18 = out_f_roready_143; // @[RegisterRouter.scala:87:24]
wire _out_T_1571 = out_f_roready_143; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_143 = out_wivalid_143 & out_wimask_143; // @[RegisterRouter.scala:87:24]
wire _out_T_1572 = out_f_wivalid_143; // @[RegisterRouter.scala:87:24]
assign out_f_woready_143 = out_woready_143 & out_womask_143; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_18 = out_f_woready_143; // @[RegisterRouter.scala:87:24]
wire _out_T_1573 = out_f_woready_143; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_18 = out_f_woready_143 ? _out_T_1569 : programBufferMem_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1574 = ~out_rimask_143; // @[RegisterRouter.scala:87:24]
wire _out_T_1575 = ~out_wimask_143; // @[RegisterRouter.scala:87:24]
wire _out_T_1576 = ~out_romask_143; // @[RegisterRouter.scala:87:24]
wire _out_T_1577 = ~out_womask_143; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_110 = {programBufferMem_18, _out_prepend_T_110}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_1578 = out_prepend_110; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_1579 = _out_T_1578; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_111 = _out_T_1579; // @[RegisterRouter.scala:87:24]
wire out_rimask_144 = |_out_rimask_T_144; // @[RegisterRouter.scala:87:24]
wire out_wimask_144 = &_out_wimask_T_144; // @[RegisterRouter.scala:87:24]
wire out_romask_144 = |_out_romask_T_144; // @[RegisterRouter.scala:87:24]
wire out_womask_144 = &_out_womask_T_144; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_144 = out_rivalid_144 & out_rimask_144; // @[RegisterRouter.scala:87:24]
wire _out_T_1581 = out_f_rivalid_144; // @[RegisterRouter.scala:87:24]
assign out_f_roready_144 = out_roready_144 & out_romask_144; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_19 = out_f_roready_144; // @[RegisterRouter.scala:87:24]
wire _out_T_1582 = out_f_roready_144; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_144 = out_wivalid_144 & out_wimask_144; // @[RegisterRouter.scala:87:24]
wire _out_T_1583 = out_f_wivalid_144; // @[RegisterRouter.scala:87:24]
assign out_f_woready_144 = out_woready_144 & out_womask_144; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_19 = out_f_woready_144; // @[RegisterRouter.scala:87:24]
wire _out_T_1584 = out_f_woready_144; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_19 = out_f_woready_144 ? _out_T_1580 : programBufferMem_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1585 = ~out_rimask_144; // @[RegisterRouter.scala:87:24]
wire _out_T_1586 = ~out_wimask_144; // @[RegisterRouter.scala:87:24]
wire _out_T_1587 = ~out_romask_144; // @[RegisterRouter.scala:87:24]
wire _out_T_1588 = ~out_womask_144; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_111 = {programBufferMem_19, _out_prepend_T_111}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_1589 = out_prepend_111; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_1590 = _out_T_1589; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_out_bits_data_WIRE_1_36 = _out_T_1590; // @[MuxLiteral.scala:49:48]
wire out_rimask_145 = |_out_rimask_T_145; // @[RegisterRouter.scala:87:24]
wire out_wimask_145 = &_out_wimask_T_145; // @[RegisterRouter.scala:87:24]
wire out_romask_145 = |_out_romask_T_145; // @[RegisterRouter.scala:87:24]
wire out_womask_145 = &_out_womask_T_145; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_145 = out_rivalid_145 & out_rimask_145; // @[RegisterRouter.scala:87:24]
wire _out_T_1592 = out_f_rivalid_145; // @[RegisterRouter.scala:87:24]
wire out_f_roready_145 = out_roready_145 & out_romask_145; // @[RegisterRouter.scala:87:24]
wire _out_T_1593 = out_f_roready_145; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_145 = out_wivalid_145 & out_wimask_145; // @[RegisterRouter.scala:87:24]
wire out_f_woready_145 = out_woready_145 & out_womask_145; // @[RegisterRouter.scala:87:24]
wire _out_T_1594 = ~out_rimask_145; // @[RegisterRouter.scala:87:24]
wire _out_T_1595 = ~out_wimask_145; // @[RegisterRouter.scala:87:24]
wire _out_T_1596 = ~out_romask_145; // @[RegisterRouter.scala:87:24]
wire _out_T_1597 = ~out_womask_145; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_1599 = _out_T_1598; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_out_bits_data_WIRE_1_19 = _out_T_1599; // @[MuxLiteral.scala:49:48]
wire _out_iindex_T = out_front_bits_index[0]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T = out_front_bits_index[0]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_1 = out_front_bits_index[1]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_1 = out_front_bits_index[1]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_2 = out_front_bits_index[2]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_2 = out_front_bits_index[2]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_3 = out_front_bits_index[3]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_3 = out_front_bits_index[3]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_4 = out_front_bits_index[4]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_4 = out_front_bits_index[4]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_5 = out_front_bits_index[5]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_5 = out_front_bits_index[5]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_6 = out_front_bits_index[6]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_6 = out_front_bits_index[6]; // @[RegisterRouter.scala:87:24]
wire [1:0] out_iindex_lo_hi = {_out_iindex_T_2, _out_iindex_T_1}; // @[RegisterRouter.scala:87:24]
wire [2:0] out_iindex_lo = {out_iindex_lo_hi, _out_iindex_T}; // @[RegisterRouter.scala:87:24]
wire [1:0] out_iindex_hi_hi = {_out_iindex_T_5, _out_iindex_T_4}; // @[RegisterRouter.scala:87:24]
wire [2:0] out_iindex_hi = {out_iindex_hi_hi, _out_iindex_T_3}; // @[RegisterRouter.scala:87:24]
wire [5:0] out_iindex = {out_iindex_hi, out_iindex_lo}; // @[RegisterRouter.scala:87:24]
wire [1:0] out_oindex_lo_hi = {_out_oindex_T_2, _out_oindex_T_1}; // @[RegisterRouter.scala:87:24]
wire [2:0] out_oindex_lo = {out_oindex_lo_hi, _out_oindex_T}; // @[RegisterRouter.scala:87:24]
wire [1:0] out_oindex_hi_hi = {_out_oindex_T_5, _out_oindex_T_4}; // @[RegisterRouter.scala:87:24]
wire [2:0] out_oindex_hi = {out_oindex_hi_hi, _out_oindex_T_3}; // @[RegisterRouter.scala:87:24]
wire [5:0] out_oindex = {out_oindex_hi, out_oindex_lo}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_frontSel_T = 64'h1 << out_iindex; // @[OneHot.scala:58:35]
wire out_frontSel_0 = _out_frontSel_T[0]; // @[OneHot.scala:58:35]
wire out_frontSel_1 = _out_frontSel_T[1]; // @[OneHot.scala:58:35]
wire out_frontSel_2 = _out_frontSel_T[2]; // @[OneHot.scala:58:35]
wire out_frontSel_3 = _out_frontSel_T[3]; // @[OneHot.scala:58:35]
wire out_frontSel_4 = _out_frontSel_T[4]; // @[OneHot.scala:58:35]
wire out_frontSel_5 = _out_frontSel_T[5]; // @[OneHot.scala:58:35]
wire out_frontSel_6 = _out_frontSel_T[6]; // @[OneHot.scala:58:35]
wire out_frontSel_7 = _out_frontSel_T[7]; // @[OneHot.scala:58:35]
wire out_frontSel_8 = _out_frontSel_T[8]; // @[OneHot.scala:58:35]
wire out_frontSel_9 = _out_frontSel_T[9]; // @[OneHot.scala:58:35]
wire out_frontSel_10 = _out_frontSel_T[10]; // @[OneHot.scala:58:35]
wire out_frontSel_11 = _out_frontSel_T[11]; // @[OneHot.scala:58:35]
wire out_frontSel_12 = _out_frontSel_T[12]; // @[OneHot.scala:58:35]
wire out_frontSel_13 = _out_frontSel_T[13]; // @[OneHot.scala:58:35]
wire out_frontSel_14 = _out_frontSel_T[14]; // @[OneHot.scala:58:35]
wire out_frontSel_15 = _out_frontSel_T[15]; // @[OneHot.scala:58:35]
wire out_frontSel_16 = _out_frontSel_T[16]; // @[OneHot.scala:58:35]
wire out_frontSel_17 = _out_frontSel_T[17]; // @[OneHot.scala:58:35]
wire out_frontSel_18 = _out_frontSel_T[18]; // @[OneHot.scala:58:35]
wire out_frontSel_19 = _out_frontSel_T[19]; // @[OneHot.scala:58:35]
wire out_frontSel_20 = _out_frontSel_T[20]; // @[OneHot.scala:58:35]
wire out_frontSel_21 = _out_frontSel_T[21]; // @[OneHot.scala:58:35]
wire out_frontSel_22 = _out_frontSel_T[22]; // @[OneHot.scala:58:35]
wire out_frontSel_23 = _out_frontSel_T[23]; // @[OneHot.scala:58:35]
wire out_frontSel_24 = _out_frontSel_T[24]; // @[OneHot.scala:58:35]
wire out_frontSel_25 = _out_frontSel_T[25]; // @[OneHot.scala:58:35]
wire out_frontSel_26 = _out_frontSel_T[26]; // @[OneHot.scala:58:35]
wire out_frontSel_27 = _out_frontSel_T[27]; // @[OneHot.scala:58:35]
wire out_frontSel_28 = _out_frontSel_T[28]; // @[OneHot.scala:58:35]
wire out_frontSel_29 = _out_frontSel_T[29]; // @[OneHot.scala:58:35]
wire out_frontSel_30 = _out_frontSel_T[30]; // @[OneHot.scala:58:35]
wire out_frontSel_31 = _out_frontSel_T[31]; // @[OneHot.scala:58:35]
wire out_frontSel_32 = _out_frontSel_T[32]; // @[OneHot.scala:58:35]
wire out_frontSel_33 = _out_frontSel_T[33]; // @[OneHot.scala:58:35]
wire out_frontSel_34 = _out_frontSel_T[34]; // @[OneHot.scala:58:35]
wire out_frontSel_35 = _out_frontSel_T[35]; // @[OneHot.scala:58:35]
wire out_frontSel_36 = _out_frontSel_T[36]; // @[OneHot.scala:58:35]
wire out_frontSel_37 = _out_frontSel_T[37]; // @[OneHot.scala:58:35]
wire out_frontSel_38 = _out_frontSel_T[38]; // @[OneHot.scala:58:35]
wire out_frontSel_39 = _out_frontSel_T[39]; // @[OneHot.scala:58:35]
wire out_frontSel_40 = _out_frontSel_T[40]; // @[OneHot.scala:58:35]
wire out_frontSel_41 = _out_frontSel_T[41]; // @[OneHot.scala:58:35]
wire out_frontSel_42 = _out_frontSel_T[42]; // @[OneHot.scala:58:35]
wire out_frontSel_43 = _out_frontSel_T[43]; // @[OneHot.scala:58:35]
wire out_frontSel_44 = _out_frontSel_T[44]; // @[OneHot.scala:58:35]
wire out_frontSel_45 = _out_frontSel_T[45]; // @[OneHot.scala:58:35]
wire out_frontSel_46 = _out_frontSel_T[46]; // @[OneHot.scala:58:35]
wire out_frontSel_47 = _out_frontSel_T[47]; // @[OneHot.scala:58:35]
wire out_frontSel_48 = _out_frontSel_T[48]; // @[OneHot.scala:58:35]
wire out_frontSel_49 = _out_frontSel_T[49]; // @[OneHot.scala:58:35]
wire out_frontSel_50 = _out_frontSel_T[50]; // @[OneHot.scala:58:35]
wire out_frontSel_51 = _out_frontSel_T[51]; // @[OneHot.scala:58:35]
wire out_frontSel_52 = _out_frontSel_T[52]; // @[OneHot.scala:58:35]
wire out_frontSel_53 = _out_frontSel_T[53]; // @[OneHot.scala:58:35]
wire out_frontSel_54 = _out_frontSel_T[54]; // @[OneHot.scala:58:35]
wire out_frontSel_55 = _out_frontSel_T[55]; // @[OneHot.scala:58:35]
wire out_frontSel_56 = _out_frontSel_T[56]; // @[OneHot.scala:58:35]
wire out_frontSel_57 = _out_frontSel_T[57]; // @[OneHot.scala:58:35]
wire out_frontSel_58 = _out_frontSel_T[58]; // @[OneHot.scala:58:35]
wire out_frontSel_59 = _out_frontSel_T[59]; // @[OneHot.scala:58:35]
wire out_frontSel_60 = _out_frontSel_T[60]; // @[OneHot.scala:58:35]
wire out_frontSel_61 = _out_frontSel_T[61]; // @[OneHot.scala:58:35]
wire out_frontSel_62 = _out_frontSel_T[62]; // @[OneHot.scala:58:35]
wire out_frontSel_63 = _out_frontSel_T[63]; // @[OneHot.scala:58:35]
wire [63:0] _out_backSel_T = 64'h1 << out_oindex; // @[OneHot.scala:58:35]
wire out_backSel_0 = _out_backSel_T[0]; // @[OneHot.scala:58:35]
wire out_backSel_1 = _out_backSel_T[1]; // @[OneHot.scala:58:35]
wire out_backSel_2 = _out_backSel_T[2]; // @[OneHot.scala:58:35]
wire out_backSel_3 = _out_backSel_T[3]; // @[OneHot.scala:58:35]
wire out_backSel_4 = _out_backSel_T[4]; // @[OneHot.scala:58:35]
wire out_backSel_5 = _out_backSel_T[5]; // @[OneHot.scala:58:35]
wire out_backSel_6 = _out_backSel_T[6]; // @[OneHot.scala:58:35]
wire out_backSel_7 = _out_backSel_T[7]; // @[OneHot.scala:58:35]
wire out_backSel_8 = _out_backSel_T[8]; // @[OneHot.scala:58:35]
wire out_backSel_9 = _out_backSel_T[9]; // @[OneHot.scala:58:35]
wire out_backSel_10 = _out_backSel_T[10]; // @[OneHot.scala:58:35]
wire out_backSel_11 = _out_backSel_T[11]; // @[OneHot.scala:58:35]
wire out_backSel_12 = _out_backSel_T[12]; // @[OneHot.scala:58:35]
wire out_backSel_13 = _out_backSel_T[13]; // @[OneHot.scala:58:35]
wire out_backSel_14 = _out_backSel_T[14]; // @[OneHot.scala:58:35]
wire out_backSel_15 = _out_backSel_T[15]; // @[OneHot.scala:58:35]
wire out_backSel_16 = _out_backSel_T[16]; // @[OneHot.scala:58:35]
wire out_backSel_17 = _out_backSel_T[17]; // @[OneHot.scala:58:35]
wire out_backSel_18 = _out_backSel_T[18]; // @[OneHot.scala:58:35]
wire out_backSel_19 = _out_backSel_T[19]; // @[OneHot.scala:58:35]
wire out_backSel_20 = _out_backSel_T[20]; // @[OneHot.scala:58:35]
wire out_backSel_21 = _out_backSel_T[21]; // @[OneHot.scala:58:35]
wire out_backSel_22 = _out_backSel_T[22]; // @[OneHot.scala:58:35]
wire out_backSel_23 = _out_backSel_T[23]; // @[OneHot.scala:58:35]
wire out_backSel_24 = _out_backSel_T[24]; // @[OneHot.scala:58:35]
wire out_backSel_25 = _out_backSel_T[25]; // @[OneHot.scala:58:35]
wire out_backSel_26 = _out_backSel_T[26]; // @[OneHot.scala:58:35]
wire out_backSel_27 = _out_backSel_T[27]; // @[OneHot.scala:58:35]
wire out_backSel_28 = _out_backSel_T[28]; // @[OneHot.scala:58:35]
wire out_backSel_29 = _out_backSel_T[29]; // @[OneHot.scala:58:35]
wire out_backSel_30 = _out_backSel_T[30]; // @[OneHot.scala:58:35]
wire out_backSel_31 = _out_backSel_T[31]; // @[OneHot.scala:58:35]
wire out_backSel_32 = _out_backSel_T[32]; // @[OneHot.scala:58:35]
wire out_backSel_33 = _out_backSel_T[33]; // @[OneHot.scala:58:35]
wire out_backSel_34 = _out_backSel_T[34]; // @[OneHot.scala:58:35]
wire out_backSel_35 = _out_backSel_T[35]; // @[OneHot.scala:58:35]
wire out_backSel_36 = _out_backSel_T[36]; // @[OneHot.scala:58:35]
wire out_backSel_37 = _out_backSel_T[37]; // @[OneHot.scala:58:35]
wire out_backSel_38 = _out_backSel_T[38]; // @[OneHot.scala:58:35]
wire out_backSel_39 = _out_backSel_T[39]; // @[OneHot.scala:58:35]
wire out_backSel_40 = _out_backSel_T[40]; // @[OneHot.scala:58:35]
wire out_backSel_41 = _out_backSel_T[41]; // @[OneHot.scala:58:35]
wire out_backSel_42 = _out_backSel_T[42]; // @[OneHot.scala:58:35]
wire out_backSel_43 = _out_backSel_T[43]; // @[OneHot.scala:58:35]
wire out_backSel_44 = _out_backSel_T[44]; // @[OneHot.scala:58:35]
wire out_backSel_45 = _out_backSel_T[45]; // @[OneHot.scala:58:35]
wire out_backSel_46 = _out_backSel_T[46]; // @[OneHot.scala:58:35]
wire out_backSel_47 = _out_backSel_T[47]; // @[OneHot.scala:58:35]
wire out_backSel_48 = _out_backSel_T[48]; // @[OneHot.scala:58:35]
wire out_backSel_49 = _out_backSel_T[49]; // @[OneHot.scala:58:35]
wire out_backSel_50 = _out_backSel_T[50]; // @[OneHot.scala:58:35]
wire out_backSel_51 = _out_backSel_T[51]; // @[OneHot.scala:58:35]
wire out_backSel_52 = _out_backSel_T[52]; // @[OneHot.scala:58:35]
wire out_backSel_53 = _out_backSel_T[53]; // @[OneHot.scala:58:35]
wire out_backSel_54 = _out_backSel_T[54]; // @[OneHot.scala:58:35]
wire out_backSel_55 = _out_backSel_T[55]; // @[OneHot.scala:58:35]
wire out_backSel_56 = _out_backSel_T[56]; // @[OneHot.scala:58:35]
wire out_backSel_57 = _out_backSel_T[57]; // @[OneHot.scala:58:35]
wire out_backSel_58 = _out_backSel_T[58]; // @[OneHot.scala:58:35]
wire out_backSel_59 = _out_backSel_T[59]; // @[OneHot.scala:58:35]
wire out_backSel_60 = _out_backSel_T[60]; // @[OneHot.scala:58:35]
wire out_backSel_61 = _out_backSel_T[61]; // @[OneHot.scala:58:35]
wire out_backSel_62 = _out_backSel_T[62]; // @[OneHot.scala:58:35]
wire out_backSel_63 = _out_backSel_T[63]; // @[OneHot.scala:58:35]
wire _GEN_11 = in_valid & out_front_ready; // @[RegisterRouter.scala:73:18, :87:24]
wire _out_rifireMux_T; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T = _GEN_11; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T = _GEN_11; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1 = _out_rifireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_2 = _out_rifireMux_T_1 & out_frontSel_0; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_3 = _out_rifireMux_T_2 & _out_T_40; // @[RegisterRouter.scala:87:24]
assign out_rivalid_81 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_4 = ~_out_T_40; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_6 = _out_rifireMux_T_1 & out_frontSel_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_7 = _out_rifireMux_T_6; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_10 = _out_rifireMux_T_1 & out_frontSel_2; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_11 = _out_rifireMux_T_10; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_14 = _out_rifireMux_T_1 & out_frontSel_3; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_15 = _out_rifireMux_T_14; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_18 = _out_rifireMux_T_1 & out_frontSel_4; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_19 = _out_rifireMux_T_18 & _out_T_12; // @[RegisterRouter.scala:87:24]
assign out_rivalid_21 = _out_rifireMux_T_19; // @[RegisterRouter.scala:87:24]
assign out_rivalid_22 = _out_rifireMux_T_19; // @[RegisterRouter.scala:87:24]
assign out_rivalid_23 = _out_rifireMux_T_19; // @[RegisterRouter.scala:87:24]
assign out_rivalid_24 = _out_rifireMux_T_19; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_20 = ~_out_T_12; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_22 = _out_rifireMux_T_1 & out_frontSel_5; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_23 = _out_rifireMux_T_22 & _out_T; // @[RegisterRouter.scala:87:24]
assign out_rivalid_0 = _out_rifireMux_T_23; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1 = _out_rifireMux_T_23; // @[RegisterRouter.scala:87:24]
assign out_rivalid_2 = _out_rifireMux_T_23; // @[RegisterRouter.scala:87:24]
assign out_rivalid_3 = _out_rifireMux_T_23; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_24 = ~_out_T; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_26 = _out_rifireMux_T_1 & out_frontSel_6; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_27 = _out_rifireMux_T_26 & _out_T_30; // @[RegisterRouter.scala:87:24]
assign out_rivalid_64 = _out_rifireMux_T_27; // @[RegisterRouter.scala:87:24]
assign out_rivalid_65 = _out_rifireMux_T_27; // @[RegisterRouter.scala:87:24]
assign out_rivalid_66 = _out_rifireMux_T_27; // @[RegisterRouter.scala:87:24]
assign out_rivalid_67 = _out_rifireMux_T_27; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_28 = ~_out_T_30; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_30 = _out_rifireMux_T_1 & out_frontSel_7; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_31 = _out_rifireMux_T_30 & _out_T_52; // @[RegisterRouter.scala:87:24]
assign out_rivalid_120 = _out_rifireMux_T_31; // @[RegisterRouter.scala:87:24]
assign out_rivalid_121 = _out_rifireMux_T_31; // @[RegisterRouter.scala:87:24]
assign out_rivalid_122 = _out_rifireMux_T_31; // @[RegisterRouter.scala:87:24]
assign out_rivalid_123 = _out_rifireMux_T_31; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_32 = ~_out_T_52; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_34 = _out_rifireMux_T_1 & out_frontSel_8; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_35 = _out_rifireMux_T_34 & _out_T_10; // @[RegisterRouter.scala:87:24]
assign out_rivalid_17 = _out_rifireMux_T_35; // @[RegisterRouter.scala:87:24]
assign out_rivalid_18 = _out_rifireMux_T_35; // @[RegisterRouter.scala:87:24]
assign out_rivalid_19 = _out_rifireMux_T_35; // @[RegisterRouter.scala:87:24]
assign out_rivalid_20 = _out_rifireMux_T_35; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_36 = ~_out_T_10; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_38 = _out_rifireMux_T_1 & out_frontSel_9; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_39 = _out_rifireMux_T_38 & _out_T_4; // @[RegisterRouter.scala:87:24]
assign out_rivalid_5 = _out_rifireMux_T_39; // @[RegisterRouter.scala:87:24]
assign out_rivalid_6 = _out_rifireMux_T_39; // @[RegisterRouter.scala:87:24]
assign out_rivalid_7 = _out_rifireMux_T_39; // @[RegisterRouter.scala:87:24]
assign out_rivalid_8 = _out_rifireMux_T_39; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_40 = ~_out_T_4; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_42 = _out_rifireMux_T_1 & out_frontSel_10; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_43 = _out_rifireMux_T_42 & _out_T_16; // @[RegisterRouter.scala:87:24]
assign out_rivalid_29 = _out_rifireMux_T_43; // @[RegisterRouter.scala:87:24]
assign out_rivalid_30 = _out_rifireMux_T_43; // @[RegisterRouter.scala:87:24]
assign out_rivalid_31 = _out_rifireMux_T_43; // @[RegisterRouter.scala:87:24]
assign out_rivalid_32 = _out_rifireMux_T_43; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_44 = ~_out_T_16; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_46 = _out_rifireMux_T_1 & out_frontSel_11; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_47 = _out_rifireMux_T_46 & _out_T_56; // @[RegisterRouter.scala:87:24]
assign out_rivalid_128 = _out_rifireMux_T_47; // @[RegisterRouter.scala:87:24]
assign out_rivalid_129 = _out_rifireMux_T_47; // @[RegisterRouter.scala:87:24]
assign out_rivalid_130 = _out_rifireMux_T_47; // @[RegisterRouter.scala:87:24]
assign out_rivalid_131 = _out_rifireMux_T_47; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_48 = ~_out_T_56; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_50 = _out_rifireMux_T_1 & out_frontSel_12; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_51 = _out_rifireMux_T_50; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_54 = _out_rifireMux_T_1 & out_frontSel_13; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_55 = _out_rifireMux_T_54; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_58 = _out_rifireMux_T_1 & out_frontSel_14; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_59 = _out_rifireMux_T_58; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_62 = _out_rifireMux_T_1 & out_frontSel_15; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_63 = _out_rifireMux_T_62; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_66 = _out_rifireMux_T_1 & out_frontSel_16; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_67 = _out_rifireMux_T_66; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_70 = _out_rifireMux_T_1 & out_frontSel_17; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_71 = _out_rifireMux_T_70 & _out_T_42; // @[RegisterRouter.scala:87:24]
assign out_rivalid_82 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24]
assign out_rivalid_83 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24]
assign out_rivalid_84 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24]
assign out_rivalid_85 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24]
assign out_rivalid_86 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24]
assign out_rivalid_87 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24]
assign out_rivalid_88 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24]
assign out_rivalid_89 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24]
assign out_rivalid_90 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24]
assign out_rivalid_91 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24]
assign out_rivalid_92 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24]
assign out_rivalid_93 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24]
assign out_rivalid_94 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24]
assign out_rivalid_95 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24]
assign out_rivalid_96 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24]
assign out_rivalid_97 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24]
assign out_rivalid_98 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24]
assign out_rivalid_99 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24]
assign out_rivalid_100 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_72 = ~_out_T_42; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_74 = _out_rifireMux_T_1 & out_frontSel_18; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_75 = _out_rifireMux_T_74; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_78 = _out_rifireMux_T_1 & out_frontSel_19; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_79 = _out_rifireMux_T_78 & _out_T_66; // @[RegisterRouter.scala:87:24]
assign out_rivalid_145 = _out_rifireMux_T_79; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_80 = ~_out_T_66; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_82 = _out_rifireMux_T_1 & out_frontSel_20; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_83 = _out_rifireMux_T_82; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_86 = _out_rifireMux_T_1 & out_frontSel_21; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_87 = _out_rifireMux_T_86; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_90 = _out_rifireMux_T_1 & out_frontSel_22; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_91 = _out_rifireMux_T_90 & _out_T_48; // @[RegisterRouter.scala:87:24]
assign out_rivalid_109 = _out_rifireMux_T_91; // @[RegisterRouter.scala:87:24]
assign out_rivalid_110 = _out_rifireMux_T_91; // @[RegisterRouter.scala:87:24]
assign out_rivalid_111 = _out_rifireMux_T_91; // @[RegisterRouter.scala:87:24]
assign out_rivalid_112 = _out_rifireMux_T_91; // @[RegisterRouter.scala:87:24]
assign out_rivalid_113 = _out_rifireMux_T_91; // @[RegisterRouter.scala:87:24]
assign out_rivalid_114 = _out_rifireMux_T_91; // @[RegisterRouter.scala:87:24]
assign out_rivalid_115 = _out_rifireMux_T_91; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_92 = ~_out_T_48; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_94 = _out_rifireMux_T_1 & out_frontSel_23; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_95 = _out_rifireMux_T_94 & _out_T_62; // @[RegisterRouter.scala:87:24]
assign out_rivalid_140 = _out_rifireMux_T_95; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_96 = ~_out_T_62; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_98 = _out_rifireMux_T_1 & out_frontSel_24; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_99 = _out_rifireMux_T_98 & _out_T_22; // @[RegisterRouter.scala:87:24]
assign out_rivalid_52 = _out_rifireMux_T_99; // @[RegisterRouter.scala:87:24]
assign out_rivalid_53 = _out_rifireMux_T_99; // @[RegisterRouter.scala:87:24]
assign out_rivalid_54 = _out_rifireMux_T_99; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_100 = ~_out_T_22; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_102 = _out_rifireMux_T_1 & out_frontSel_25; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_103 = _out_rifireMux_T_102; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_106 = _out_rifireMux_T_1 & out_frontSel_26; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_107 = _out_rifireMux_T_106; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_110 = _out_rifireMux_T_1 & out_frontSel_27; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_111 = _out_rifireMux_T_110; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_114 = _out_rifireMux_T_1 & out_frontSel_28; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_115 = _out_rifireMux_T_114; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_118 = _out_rifireMux_T_1 & out_frontSel_29; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_119 = _out_rifireMux_T_118; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_122 = _out_rifireMux_T_1 & out_frontSel_30; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_123 = _out_rifireMux_T_122; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_126 = _out_rifireMux_T_1 & out_frontSel_31; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_127 = _out_rifireMux_T_126; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_130 = _out_rifireMux_T_1 & out_frontSel_32; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_131 = _out_rifireMux_T_130 & _out_T_44; // @[RegisterRouter.scala:87:24]
assign out_rivalid_101 = _out_rifireMux_T_131; // @[RegisterRouter.scala:87:24]
assign out_rivalid_102 = _out_rifireMux_T_131; // @[RegisterRouter.scala:87:24]
assign out_rivalid_103 = _out_rifireMux_T_131; // @[RegisterRouter.scala:87:24]
assign out_rivalid_104 = _out_rifireMux_T_131; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_132 = ~_out_T_44; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_134 = _out_rifireMux_T_1 & out_frontSel_33; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_135 = _out_rifireMux_T_134 & _out_T_36; // @[RegisterRouter.scala:87:24]
assign out_rivalid_73 = _out_rifireMux_T_135; // @[RegisterRouter.scala:87:24]
assign out_rivalid_74 = _out_rifireMux_T_135; // @[RegisterRouter.scala:87:24]
assign out_rivalid_75 = _out_rifireMux_T_135; // @[RegisterRouter.scala:87:24]
assign out_rivalid_76 = _out_rifireMux_T_135; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_136 = ~_out_T_36; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_138 = _out_rifireMux_T_1 & out_frontSel_34; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_139 = _out_rifireMux_T_138 & _out_T_46; // @[RegisterRouter.scala:87:24]
assign out_rivalid_105 = _out_rifireMux_T_139; // @[RegisterRouter.scala:87:24]
assign out_rivalid_106 = _out_rifireMux_T_139; // @[RegisterRouter.scala:87:24]
assign out_rivalid_107 = _out_rifireMux_T_139; // @[RegisterRouter.scala:87:24]
assign out_rivalid_108 = _out_rifireMux_T_139; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_140 = ~_out_T_46; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_142 = _out_rifireMux_T_1 & out_frontSel_35; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_143 = _out_rifireMux_T_142 & _out_T_8; // @[RegisterRouter.scala:87:24]
assign out_rivalid_13 = _out_rifireMux_T_143; // @[RegisterRouter.scala:87:24]
assign out_rivalid_14 = _out_rifireMux_T_143; // @[RegisterRouter.scala:87:24]
assign out_rivalid_15 = _out_rifireMux_T_143; // @[RegisterRouter.scala:87:24]
assign out_rivalid_16 = _out_rifireMux_T_143; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_144 = ~_out_T_8; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_146 = _out_rifireMux_T_1 & out_frontSel_36; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_147 = _out_rifireMux_T_146 & _out_T_64; // @[RegisterRouter.scala:87:24]
assign out_rivalid_141 = _out_rifireMux_T_147; // @[RegisterRouter.scala:87:24]
assign out_rivalid_142 = _out_rifireMux_T_147; // @[RegisterRouter.scala:87:24]
assign out_rivalid_143 = _out_rifireMux_T_147; // @[RegisterRouter.scala:87:24]
assign out_rivalid_144 = _out_rifireMux_T_147; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_148 = ~_out_T_64; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_150 = _out_rifireMux_T_1 & out_frontSel_37; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_151 = _out_rifireMux_T_150 & _out_T_24; // @[RegisterRouter.scala:87:24]
assign out_rivalid_55 = _out_rifireMux_T_151; // @[RegisterRouter.scala:87:24]
assign out_rivalid_56 = _out_rifireMux_T_151; // @[RegisterRouter.scala:87:24]
assign out_rivalid_57 = _out_rifireMux_T_151; // @[RegisterRouter.scala:87:24]
assign out_rivalid_58 = _out_rifireMux_T_151; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_152 = ~_out_T_24; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_154 = _out_rifireMux_T_1 & out_frontSel_38; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_155 = _out_rifireMux_T_154 & _out_T_34; // @[RegisterRouter.scala:87:24]
assign out_rivalid_69 = _out_rifireMux_T_155; // @[RegisterRouter.scala:87:24]
assign out_rivalid_70 = _out_rifireMux_T_155; // @[RegisterRouter.scala:87:24]
assign out_rivalid_71 = _out_rifireMux_T_155; // @[RegisterRouter.scala:87:24]
assign out_rivalid_72 = _out_rifireMux_T_155; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_156 = ~_out_T_34; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_158 = _out_rifireMux_T_1 & out_frontSel_39; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_159 = _out_rifireMux_T_158 & _out_T_54; // @[RegisterRouter.scala:87:24]
assign out_rivalid_124 = _out_rifireMux_T_159; // @[RegisterRouter.scala:87:24]
assign out_rivalid_125 = _out_rifireMux_T_159; // @[RegisterRouter.scala:87:24]
assign out_rivalid_126 = _out_rifireMux_T_159; // @[RegisterRouter.scala:87:24]
assign out_rivalid_127 = _out_rifireMux_T_159; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_160 = ~_out_T_54; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_162 = _out_rifireMux_T_1 & out_frontSel_40; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_163 = _out_rifireMux_T_162 & _out_T_60; // @[RegisterRouter.scala:87:24]
assign out_rivalid_136 = _out_rifireMux_T_163; // @[RegisterRouter.scala:87:24]
assign out_rivalid_137 = _out_rifireMux_T_163; // @[RegisterRouter.scala:87:24]
assign out_rivalid_138 = _out_rifireMux_T_163; // @[RegisterRouter.scala:87:24]
assign out_rivalid_139 = _out_rifireMux_T_163; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_164 = ~_out_T_60; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_166 = _out_rifireMux_T_1 & out_frontSel_41; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_167 = _out_rifireMux_T_166 & _out_T_6; // @[RegisterRouter.scala:87:24]
assign out_rivalid_9 = _out_rifireMux_T_167; // @[RegisterRouter.scala:87:24]
assign out_rivalid_10 = _out_rifireMux_T_167; // @[RegisterRouter.scala:87:24]
assign out_rivalid_11 = _out_rifireMux_T_167; // @[RegisterRouter.scala:87:24]
assign out_rivalid_12 = _out_rifireMux_T_167; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_168 = ~_out_T_6; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_170 = _out_rifireMux_T_1 & out_frontSel_42; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_171 = _out_rifireMux_T_170 & _out_T_20; // @[RegisterRouter.scala:87:24]
assign out_rivalid_48 = _out_rifireMux_T_171; // @[RegisterRouter.scala:87:24]
assign out_rivalid_49 = _out_rifireMux_T_171; // @[RegisterRouter.scala:87:24]
assign out_rivalid_50 = _out_rifireMux_T_171; // @[RegisterRouter.scala:87:24]
assign out_rivalid_51 = _out_rifireMux_T_171; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_172 = ~_out_T_20; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_174 = _out_rifireMux_T_1 & out_frontSel_43; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_175 = _out_rifireMux_T_174 & _out_T_58; // @[RegisterRouter.scala:87:24]
assign out_rivalid_132 = _out_rifireMux_T_175; // @[RegisterRouter.scala:87:24]
assign out_rivalid_133 = _out_rifireMux_T_175; // @[RegisterRouter.scala:87:24]
assign out_rivalid_134 = _out_rifireMux_T_175; // @[RegisterRouter.scala:87:24]
assign out_rivalid_135 = _out_rifireMux_T_175; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_176 = ~_out_T_58; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_178 = _out_rifireMux_T_1 & out_frontSel_44; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_179 = _out_rifireMux_T_178 & _out_T_50; // @[RegisterRouter.scala:87:24]
assign out_rivalid_116 = _out_rifireMux_T_179; // @[RegisterRouter.scala:87:24]
assign out_rivalid_117 = _out_rifireMux_T_179; // @[RegisterRouter.scala:87:24]
assign out_rivalid_118 = _out_rifireMux_T_179; // @[RegisterRouter.scala:87:24]
assign out_rivalid_119 = _out_rifireMux_T_179; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_180 = ~_out_T_50; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_182 = _out_rifireMux_T_1 & out_frontSel_45; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_183 = _out_rifireMux_T_182 & _out_T_38; // @[RegisterRouter.scala:87:24]
assign out_rivalid_77 = _out_rifireMux_T_183; // @[RegisterRouter.scala:87:24]
assign out_rivalid_78 = _out_rifireMux_T_183; // @[RegisterRouter.scala:87:24]
assign out_rivalid_79 = _out_rifireMux_T_183; // @[RegisterRouter.scala:87:24]
assign out_rivalid_80 = _out_rifireMux_T_183; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_184 = ~_out_T_38; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_186 = _out_rifireMux_T_1 & out_frontSel_46; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_187 = _out_rifireMux_T_186 & _out_T_26; // @[RegisterRouter.scala:87:24]
assign out_rivalid_59 = _out_rifireMux_T_187; // @[RegisterRouter.scala:87:24]
assign out_rivalid_60 = _out_rifireMux_T_187; // @[RegisterRouter.scala:87:24]
assign out_rivalid_61 = _out_rifireMux_T_187; // @[RegisterRouter.scala:87:24]
assign out_rivalid_62 = _out_rifireMux_T_187; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_188 = ~_out_T_26; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_190 = _out_rifireMux_T_1 & out_frontSel_47; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_191 = _out_rifireMux_T_190 & _out_T_14; // @[RegisterRouter.scala:87:24]
assign out_rivalid_25 = _out_rifireMux_T_191; // @[RegisterRouter.scala:87:24]
assign out_rivalid_26 = _out_rifireMux_T_191; // @[RegisterRouter.scala:87:24]
assign out_rivalid_27 = _out_rifireMux_T_191; // @[RegisterRouter.scala:87:24]
assign out_rivalid_28 = _out_rifireMux_T_191; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_192 = ~_out_T_14; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_194 = _out_rifireMux_T_1 & out_frontSel_48; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_195 = _out_rifireMux_T_194; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_198 = _out_rifireMux_T_1 & out_frontSel_49; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_199 = _out_rifireMux_T_198; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_202 = _out_rifireMux_T_1 & out_frontSel_50; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_203 = _out_rifireMux_T_202; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_206 = _out_rifireMux_T_1 & out_frontSel_51; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_207 = _out_rifireMux_T_206; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_210 = _out_rifireMux_T_1 & out_frontSel_52; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_211 = _out_rifireMux_T_210; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_214 = _out_rifireMux_T_1 & out_frontSel_53; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_215 = _out_rifireMux_T_214; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_218 = _out_rifireMux_T_1 & out_frontSel_54; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_219 = _out_rifireMux_T_218; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_222 = _out_rifireMux_T_1 & out_frontSel_55; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_223 = _out_rifireMux_T_222; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_226 = _out_rifireMux_T_1 & out_frontSel_56; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_227 = _out_rifireMux_T_226 & _out_T_18; // @[RegisterRouter.scala:87:24]
assign out_rivalid_33 = _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24]
assign out_rivalid_34 = _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24]
assign out_rivalid_35 = _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24]
assign out_rivalid_36 = _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24]
assign out_rivalid_37 = _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24]
assign out_rivalid_38 = _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24]
assign out_rivalid_39 = _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24]
assign out_rivalid_40 = _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24]
assign out_rivalid_41 = _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24]
assign out_rivalid_42 = _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24]
assign out_rivalid_43 = _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24]
assign out_rivalid_44 = _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24]
assign out_rivalid_45 = _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24]
assign out_rivalid_46 = _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24]
assign out_rivalid_47 = _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_228 = ~_out_T_18; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_230 = _out_rifireMux_T_1 & out_frontSel_57; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_231 = _out_rifireMux_T_230 & _out_T_28; // @[RegisterRouter.scala:87:24]
assign out_rivalid_63 = _out_rifireMux_T_231; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_232 = ~_out_T_28; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_234 = _out_rifireMux_T_1 & out_frontSel_58; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_235 = _out_rifireMux_T_234; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_238 = _out_rifireMux_T_1 & out_frontSel_59; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_239 = _out_rifireMux_T_238; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_242 = _out_rifireMux_T_1 & out_frontSel_60; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_243 = _out_rifireMux_T_242 & _out_T_32; // @[RegisterRouter.scala:87:24]
assign out_rivalid_68 = _out_rifireMux_T_243; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_244 = ~_out_T_32; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_246 = _out_rifireMux_T_1 & out_frontSel_61; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_247 = _out_rifireMux_T_246 & _out_T_2; // @[RegisterRouter.scala:87:24]
assign out_rivalid_4 = _out_rifireMux_T_247; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_248 = ~_out_T_2; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_250 = _out_rifireMux_T_1 & out_frontSel_62; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_251 = _out_rifireMux_T_250; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_254 = _out_rifireMux_T_1 & out_frontSel_63; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_255 = _out_rifireMux_T_254; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_2 = _out_wifireMux_T & _out_wifireMux_T_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_3 = _out_wifireMux_T_2 & out_frontSel_0; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_4 = _out_wifireMux_T_3 & _out_T_40; // @[RegisterRouter.scala:87:24]
assign out_wivalid_81 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_5 = ~_out_T_40; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_7 = _out_wifireMux_T_2 & out_frontSel_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_8 = _out_wifireMux_T_7; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_11 = _out_wifireMux_T_2 & out_frontSel_2; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_12 = _out_wifireMux_T_11; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_15 = _out_wifireMux_T_2 & out_frontSel_3; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_16 = _out_wifireMux_T_15; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_19 = _out_wifireMux_T_2 & out_frontSel_4; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_20 = _out_wifireMux_T_19 & _out_T_12; // @[RegisterRouter.scala:87:24]
assign out_wivalid_21 = _out_wifireMux_T_20; // @[RegisterRouter.scala:87:24]
assign out_wivalid_22 = _out_wifireMux_T_20; // @[RegisterRouter.scala:87:24]
assign out_wivalid_23 = _out_wifireMux_T_20; // @[RegisterRouter.scala:87:24]
assign out_wivalid_24 = _out_wifireMux_T_20; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_21 = ~_out_T_12; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_23 = _out_wifireMux_T_2 & out_frontSel_5; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_24 = _out_wifireMux_T_23 & _out_T; // @[RegisterRouter.scala:87:24]
assign out_wivalid_0 = _out_wifireMux_T_24; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1 = _out_wifireMux_T_24; // @[RegisterRouter.scala:87:24]
assign out_wivalid_2 = _out_wifireMux_T_24; // @[RegisterRouter.scala:87:24]
assign out_wivalid_3 = _out_wifireMux_T_24; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_25 = ~_out_T; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_27 = _out_wifireMux_T_2 & out_frontSel_6; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_28 = _out_wifireMux_T_27 & _out_T_30; // @[RegisterRouter.scala:87:24]
assign out_wivalid_64 = _out_wifireMux_T_28; // @[RegisterRouter.scala:87:24]
assign out_wivalid_65 = _out_wifireMux_T_28; // @[RegisterRouter.scala:87:24]
assign out_wivalid_66 = _out_wifireMux_T_28; // @[RegisterRouter.scala:87:24]
assign out_wivalid_67 = _out_wifireMux_T_28; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_29 = ~_out_T_30; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_31 = _out_wifireMux_T_2 & out_frontSel_7; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_32 = _out_wifireMux_T_31 & _out_T_52; // @[RegisterRouter.scala:87:24]
assign out_wivalid_120 = _out_wifireMux_T_32; // @[RegisterRouter.scala:87:24]
assign out_wivalid_121 = _out_wifireMux_T_32; // @[RegisterRouter.scala:87:24]
assign out_wivalid_122 = _out_wifireMux_T_32; // @[RegisterRouter.scala:87:24]
assign out_wivalid_123 = _out_wifireMux_T_32; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_33 = ~_out_T_52; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_35 = _out_wifireMux_T_2 & out_frontSel_8; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_36 = _out_wifireMux_T_35 & _out_T_10; // @[RegisterRouter.scala:87:24]
assign out_wivalid_17 = _out_wifireMux_T_36; // @[RegisterRouter.scala:87:24]
assign out_wivalid_18 = _out_wifireMux_T_36; // @[RegisterRouter.scala:87:24]
assign out_wivalid_19 = _out_wifireMux_T_36; // @[RegisterRouter.scala:87:24]
assign out_wivalid_20 = _out_wifireMux_T_36; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_37 = ~_out_T_10; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_39 = _out_wifireMux_T_2 & out_frontSel_9; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_40 = _out_wifireMux_T_39 & _out_T_4; // @[RegisterRouter.scala:87:24]
assign out_wivalid_5 = _out_wifireMux_T_40; // @[RegisterRouter.scala:87:24]
assign out_wivalid_6 = _out_wifireMux_T_40; // @[RegisterRouter.scala:87:24]
assign out_wivalid_7 = _out_wifireMux_T_40; // @[RegisterRouter.scala:87:24]
assign out_wivalid_8 = _out_wifireMux_T_40; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_41 = ~_out_T_4; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_43 = _out_wifireMux_T_2 & out_frontSel_10; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_44 = _out_wifireMux_T_43 & _out_T_16; // @[RegisterRouter.scala:87:24]
assign out_wivalid_29 = _out_wifireMux_T_44; // @[RegisterRouter.scala:87:24]
assign out_wivalid_30 = _out_wifireMux_T_44; // @[RegisterRouter.scala:87:24]
assign out_wivalid_31 = _out_wifireMux_T_44; // @[RegisterRouter.scala:87:24]
assign out_wivalid_32 = _out_wifireMux_T_44; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_45 = ~_out_T_16; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_47 = _out_wifireMux_T_2 & out_frontSel_11; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_48 = _out_wifireMux_T_47 & _out_T_56; // @[RegisterRouter.scala:87:24]
assign out_wivalid_128 = _out_wifireMux_T_48; // @[RegisterRouter.scala:87:24]
assign out_wivalid_129 = _out_wifireMux_T_48; // @[RegisterRouter.scala:87:24]
assign out_wivalid_130 = _out_wifireMux_T_48; // @[RegisterRouter.scala:87:24]
assign out_wivalid_131 = _out_wifireMux_T_48; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_49 = ~_out_T_56; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_51 = _out_wifireMux_T_2 & out_frontSel_12; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_52 = _out_wifireMux_T_51; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_55 = _out_wifireMux_T_2 & out_frontSel_13; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_56 = _out_wifireMux_T_55; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_59 = _out_wifireMux_T_2 & out_frontSel_14; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_60 = _out_wifireMux_T_59; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_63 = _out_wifireMux_T_2 & out_frontSel_15; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_64 = _out_wifireMux_T_63; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_67 = _out_wifireMux_T_2 & out_frontSel_16; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_68 = _out_wifireMux_T_67; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_71 = _out_wifireMux_T_2 & out_frontSel_17; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_72 = _out_wifireMux_T_71 & _out_T_42; // @[RegisterRouter.scala:87:24]
assign out_wivalid_82 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24]
assign out_wivalid_83 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24]
assign out_wivalid_84 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24]
assign out_wivalid_85 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24]
assign out_wivalid_86 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24]
assign out_wivalid_87 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24]
assign out_wivalid_88 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24]
assign out_wivalid_89 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24]
assign out_wivalid_90 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24]
assign out_wivalid_91 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24]
assign out_wivalid_92 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24]
assign out_wivalid_93 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24]
assign out_wivalid_94 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24]
assign out_wivalid_95 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24]
assign out_wivalid_96 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24]
assign out_wivalid_97 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24]
assign out_wivalid_98 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24]
assign out_wivalid_99 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24]
assign out_wivalid_100 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_73 = ~_out_T_42; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_75 = _out_wifireMux_T_2 & out_frontSel_18; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_76 = _out_wifireMux_T_75; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_79 = _out_wifireMux_T_2 & out_frontSel_19; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_80 = _out_wifireMux_T_79 & _out_T_66; // @[RegisterRouter.scala:87:24]
assign out_wivalid_145 = _out_wifireMux_T_80; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_81 = ~_out_T_66; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_83 = _out_wifireMux_T_2 & out_frontSel_20; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_84 = _out_wifireMux_T_83; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_87 = _out_wifireMux_T_2 & out_frontSel_21; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_88 = _out_wifireMux_T_87; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_91 = _out_wifireMux_T_2 & out_frontSel_22; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_92 = _out_wifireMux_T_91 & _out_T_48; // @[RegisterRouter.scala:87:24]
assign out_wivalid_109 = _out_wifireMux_T_92; // @[RegisterRouter.scala:87:24]
assign out_wivalid_110 = _out_wifireMux_T_92; // @[RegisterRouter.scala:87:24]
assign out_wivalid_111 = _out_wifireMux_T_92; // @[RegisterRouter.scala:87:24]
assign out_wivalid_112 = _out_wifireMux_T_92; // @[RegisterRouter.scala:87:24]
assign out_wivalid_113 = _out_wifireMux_T_92; // @[RegisterRouter.scala:87:24]
assign out_wivalid_114 = _out_wifireMux_T_92; // @[RegisterRouter.scala:87:24]
assign out_wivalid_115 = _out_wifireMux_T_92; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_93 = ~_out_T_48; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_95 = _out_wifireMux_T_2 & out_frontSel_23; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_96 = _out_wifireMux_T_95 & _out_T_62; // @[RegisterRouter.scala:87:24]
assign out_wivalid_140 = _out_wifireMux_T_96; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_97 = ~_out_T_62; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_99 = _out_wifireMux_T_2 & out_frontSel_24; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_100 = _out_wifireMux_T_99 & _out_T_22; // @[RegisterRouter.scala:87:24]
assign out_wivalid_52 = _out_wifireMux_T_100; // @[RegisterRouter.scala:87:24]
assign out_wivalid_53 = _out_wifireMux_T_100; // @[RegisterRouter.scala:87:24]
assign out_wivalid_54 = _out_wifireMux_T_100; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_101 = ~_out_T_22; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_103 = _out_wifireMux_T_2 & out_frontSel_25; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_104 = _out_wifireMux_T_103; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_107 = _out_wifireMux_T_2 & out_frontSel_26; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_108 = _out_wifireMux_T_107; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_111 = _out_wifireMux_T_2 & out_frontSel_27; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_112 = _out_wifireMux_T_111; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_115 = _out_wifireMux_T_2 & out_frontSel_28; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_116 = _out_wifireMux_T_115; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_119 = _out_wifireMux_T_2 & out_frontSel_29; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_120 = _out_wifireMux_T_119; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_123 = _out_wifireMux_T_2 & out_frontSel_30; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_124 = _out_wifireMux_T_123; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_127 = _out_wifireMux_T_2 & out_frontSel_31; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_128 = _out_wifireMux_T_127; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_131 = _out_wifireMux_T_2 & out_frontSel_32; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_132 = _out_wifireMux_T_131 & _out_T_44; // @[RegisterRouter.scala:87:24]
assign out_wivalid_101 = _out_wifireMux_T_132; // @[RegisterRouter.scala:87:24]
assign out_wivalid_102 = _out_wifireMux_T_132; // @[RegisterRouter.scala:87:24]
assign out_wivalid_103 = _out_wifireMux_T_132; // @[RegisterRouter.scala:87:24]
assign out_wivalid_104 = _out_wifireMux_T_132; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_133 = ~_out_T_44; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_135 = _out_wifireMux_T_2 & out_frontSel_33; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_136 = _out_wifireMux_T_135 & _out_T_36; // @[RegisterRouter.scala:87:24]
assign out_wivalid_73 = _out_wifireMux_T_136; // @[RegisterRouter.scala:87:24]
assign out_wivalid_74 = _out_wifireMux_T_136; // @[RegisterRouter.scala:87:24]
assign out_wivalid_75 = _out_wifireMux_T_136; // @[RegisterRouter.scala:87:24]
assign out_wivalid_76 = _out_wifireMux_T_136; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_137 = ~_out_T_36; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_139 = _out_wifireMux_T_2 & out_frontSel_34; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_140 = _out_wifireMux_T_139 & _out_T_46; // @[RegisterRouter.scala:87:24]
assign out_wivalid_105 = _out_wifireMux_T_140; // @[RegisterRouter.scala:87:24]
assign out_wivalid_106 = _out_wifireMux_T_140; // @[RegisterRouter.scala:87:24]
assign out_wivalid_107 = _out_wifireMux_T_140; // @[RegisterRouter.scala:87:24]
assign out_wivalid_108 = _out_wifireMux_T_140; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_141 = ~_out_T_46; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_143 = _out_wifireMux_T_2 & out_frontSel_35; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_144 = _out_wifireMux_T_143 & _out_T_8; // @[RegisterRouter.scala:87:24]
assign out_wivalid_13 = _out_wifireMux_T_144; // @[RegisterRouter.scala:87:24]
assign out_wivalid_14 = _out_wifireMux_T_144; // @[RegisterRouter.scala:87:24]
assign out_wivalid_15 = _out_wifireMux_T_144; // @[RegisterRouter.scala:87:24]
assign out_wivalid_16 = _out_wifireMux_T_144; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_145 = ~_out_T_8; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_147 = _out_wifireMux_T_2 & out_frontSel_36; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_148 = _out_wifireMux_T_147 & _out_T_64; // @[RegisterRouter.scala:87:24]
assign out_wivalid_141 = _out_wifireMux_T_148; // @[RegisterRouter.scala:87:24]
assign out_wivalid_142 = _out_wifireMux_T_148; // @[RegisterRouter.scala:87:24]
assign out_wivalid_143 = _out_wifireMux_T_148; // @[RegisterRouter.scala:87:24]
assign out_wivalid_144 = _out_wifireMux_T_148; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_149 = ~_out_T_64; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_151 = _out_wifireMux_T_2 & out_frontSel_37; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_152 = _out_wifireMux_T_151 & _out_T_24; // @[RegisterRouter.scala:87:24]
assign out_wivalid_55 = _out_wifireMux_T_152; // @[RegisterRouter.scala:87:24]
assign out_wivalid_56 = _out_wifireMux_T_152; // @[RegisterRouter.scala:87:24]
assign out_wivalid_57 = _out_wifireMux_T_152; // @[RegisterRouter.scala:87:24]
assign out_wivalid_58 = _out_wifireMux_T_152; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_153 = ~_out_T_24; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_155 = _out_wifireMux_T_2 & out_frontSel_38; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_156 = _out_wifireMux_T_155 & _out_T_34; // @[RegisterRouter.scala:87:24]
assign out_wivalid_69 = _out_wifireMux_T_156; // @[RegisterRouter.scala:87:24]
assign out_wivalid_70 = _out_wifireMux_T_156; // @[RegisterRouter.scala:87:24]
assign out_wivalid_71 = _out_wifireMux_T_156; // @[RegisterRouter.scala:87:24]
assign out_wivalid_72 = _out_wifireMux_T_156; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_157 = ~_out_T_34; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_159 = _out_wifireMux_T_2 & out_frontSel_39; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_160 = _out_wifireMux_T_159 & _out_T_54; // @[RegisterRouter.scala:87:24]
assign out_wivalid_124 = _out_wifireMux_T_160; // @[RegisterRouter.scala:87:24]
assign out_wivalid_125 = _out_wifireMux_T_160; // @[RegisterRouter.scala:87:24]
assign out_wivalid_126 = _out_wifireMux_T_160; // @[RegisterRouter.scala:87:24]
assign out_wivalid_127 = _out_wifireMux_T_160; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_161 = ~_out_T_54; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_163 = _out_wifireMux_T_2 & out_frontSel_40; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_164 = _out_wifireMux_T_163 & _out_T_60; // @[RegisterRouter.scala:87:24]
assign out_wivalid_136 = _out_wifireMux_T_164; // @[RegisterRouter.scala:87:24]
assign out_wivalid_137 = _out_wifireMux_T_164; // @[RegisterRouter.scala:87:24]
assign out_wivalid_138 = _out_wifireMux_T_164; // @[RegisterRouter.scala:87:24]
assign out_wivalid_139 = _out_wifireMux_T_164; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_165 = ~_out_T_60; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_167 = _out_wifireMux_T_2 & out_frontSel_41; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_168 = _out_wifireMux_T_167 & _out_T_6; // @[RegisterRouter.scala:87:24]
assign out_wivalid_9 = _out_wifireMux_T_168; // @[RegisterRouter.scala:87:24]
assign out_wivalid_10 = _out_wifireMux_T_168; // @[RegisterRouter.scala:87:24]
assign out_wivalid_11 = _out_wifireMux_T_168; // @[RegisterRouter.scala:87:24]
assign out_wivalid_12 = _out_wifireMux_T_168; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_169 = ~_out_T_6; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_171 = _out_wifireMux_T_2 & out_frontSel_42; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_172 = _out_wifireMux_T_171 & _out_T_20; // @[RegisterRouter.scala:87:24]
assign out_wivalid_48 = _out_wifireMux_T_172; // @[RegisterRouter.scala:87:24]
assign out_wivalid_49 = _out_wifireMux_T_172; // @[RegisterRouter.scala:87:24]
assign out_wivalid_50 = _out_wifireMux_T_172; // @[RegisterRouter.scala:87:24]
assign out_wivalid_51 = _out_wifireMux_T_172; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_173 = ~_out_T_20; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_175 = _out_wifireMux_T_2 & out_frontSel_43; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_176 = _out_wifireMux_T_175 & _out_T_58; // @[RegisterRouter.scala:87:24]
assign out_wivalid_132 = _out_wifireMux_T_176; // @[RegisterRouter.scala:87:24]
assign out_wivalid_133 = _out_wifireMux_T_176; // @[RegisterRouter.scala:87:24]
assign out_wivalid_134 = _out_wifireMux_T_176; // @[RegisterRouter.scala:87:24]
assign out_wivalid_135 = _out_wifireMux_T_176; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_177 = ~_out_T_58; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_179 = _out_wifireMux_T_2 & out_frontSel_44; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_180 = _out_wifireMux_T_179 & _out_T_50; // @[RegisterRouter.scala:87:24]
assign out_wivalid_116 = _out_wifireMux_T_180; // @[RegisterRouter.scala:87:24]
assign out_wivalid_117 = _out_wifireMux_T_180; // @[RegisterRouter.scala:87:24]
assign out_wivalid_118 = _out_wifireMux_T_180; // @[RegisterRouter.scala:87:24]
assign out_wivalid_119 = _out_wifireMux_T_180; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_181 = ~_out_T_50; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_183 = _out_wifireMux_T_2 & out_frontSel_45; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_184 = _out_wifireMux_T_183 & _out_T_38; // @[RegisterRouter.scala:87:24]
assign out_wivalid_77 = _out_wifireMux_T_184; // @[RegisterRouter.scala:87:24]
assign out_wivalid_78 = _out_wifireMux_T_184; // @[RegisterRouter.scala:87:24]
assign out_wivalid_79 = _out_wifireMux_T_184; // @[RegisterRouter.scala:87:24]
assign out_wivalid_80 = _out_wifireMux_T_184; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_185 = ~_out_T_38; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_187 = _out_wifireMux_T_2 & out_frontSel_46; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_188 = _out_wifireMux_T_187 & _out_T_26; // @[RegisterRouter.scala:87:24]
assign out_wivalid_59 = _out_wifireMux_T_188; // @[RegisterRouter.scala:87:24]
assign out_wivalid_60 = _out_wifireMux_T_188; // @[RegisterRouter.scala:87:24]
assign out_wivalid_61 = _out_wifireMux_T_188; // @[RegisterRouter.scala:87:24]
assign out_wivalid_62 = _out_wifireMux_T_188; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_189 = ~_out_T_26; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_191 = _out_wifireMux_T_2 & out_frontSel_47; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_192 = _out_wifireMux_T_191 & _out_T_14; // @[RegisterRouter.scala:87:24]
assign out_wivalid_25 = _out_wifireMux_T_192; // @[RegisterRouter.scala:87:24]
assign out_wivalid_26 = _out_wifireMux_T_192; // @[RegisterRouter.scala:87:24]
assign out_wivalid_27 = _out_wifireMux_T_192; // @[RegisterRouter.scala:87:24]
assign out_wivalid_28 = _out_wifireMux_T_192; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_193 = ~_out_T_14; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_195 = _out_wifireMux_T_2 & out_frontSel_48; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_196 = _out_wifireMux_T_195; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_199 = _out_wifireMux_T_2 & out_frontSel_49; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_200 = _out_wifireMux_T_199; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_203 = _out_wifireMux_T_2 & out_frontSel_50; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_204 = _out_wifireMux_T_203; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_207 = _out_wifireMux_T_2 & out_frontSel_51; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_208 = _out_wifireMux_T_207; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_211 = _out_wifireMux_T_2 & out_frontSel_52; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_212 = _out_wifireMux_T_211; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_215 = _out_wifireMux_T_2 & out_frontSel_53; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_216 = _out_wifireMux_T_215; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_219 = _out_wifireMux_T_2 & out_frontSel_54; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_220 = _out_wifireMux_T_219; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_223 = _out_wifireMux_T_2 & out_frontSel_55; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_224 = _out_wifireMux_T_223; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_227 = _out_wifireMux_T_2 & out_frontSel_56; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_228 = _out_wifireMux_T_227 & _out_T_18; // @[RegisterRouter.scala:87:24]
assign out_wivalid_33 = _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24]
assign out_wivalid_34 = _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24]
assign out_wivalid_35 = _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24]
assign out_wivalid_36 = _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24]
assign out_wivalid_37 = _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24]
assign out_wivalid_38 = _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24]
assign out_wivalid_39 = _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24]
assign out_wivalid_40 = _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24]
assign out_wivalid_41 = _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24]
assign out_wivalid_42 = _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24]
assign out_wivalid_43 = _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24]
assign out_wivalid_44 = _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24]
assign out_wivalid_45 = _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24]
assign out_wivalid_46 = _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24]
assign out_wivalid_47 = _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_229 = ~_out_T_18; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_231 = _out_wifireMux_T_2 & out_frontSel_57; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_232 = _out_wifireMux_T_231 & _out_T_28; // @[RegisterRouter.scala:87:24]
assign out_wivalid_63 = _out_wifireMux_T_232; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_233 = ~_out_T_28; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_235 = _out_wifireMux_T_2 & out_frontSel_58; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_236 = _out_wifireMux_T_235; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_239 = _out_wifireMux_T_2 & out_frontSel_59; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_240 = _out_wifireMux_T_239; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_243 = _out_wifireMux_T_2 & out_frontSel_60; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_244 = _out_wifireMux_T_243 & _out_T_32; // @[RegisterRouter.scala:87:24]
assign out_wivalid_68 = _out_wifireMux_T_244; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_245 = ~_out_T_32; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_247 = _out_wifireMux_T_2 & out_frontSel_61; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_248 = _out_wifireMux_T_247 & _out_T_2; // @[RegisterRouter.scala:87:24]
assign out_wivalid_4 = _out_wifireMux_T_248; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_249 = ~_out_T_2; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_251 = _out_wifireMux_T_2 & out_frontSel_62; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_252 = _out_wifireMux_T_251; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_255 = _out_wifireMux_T_2 & out_frontSel_63; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_256 = _out_wifireMux_T_255; // @[RegisterRouter.scala:87:24]
wire _GEN_12 = out_front_valid & out_ready; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T = _GEN_12; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T = _GEN_12; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1 = _out_rofireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_2 = _out_rofireMux_T_1 & out_backSel_0; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_3 = _out_rofireMux_T_2 & _out_T_41; // @[RegisterRouter.scala:87:24]
assign out_roready_81 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_4 = ~_out_T_41; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_6 = _out_rofireMux_T_1 & out_backSel_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_7 = _out_rofireMux_T_6; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_10 = _out_rofireMux_T_1 & out_backSel_2; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_11 = _out_rofireMux_T_10; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_14 = _out_rofireMux_T_1 & out_backSel_3; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_15 = _out_rofireMux_T_14; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_18 = _out_rofireMux_T_1 & out_backSel_4; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_19 = _out_rofireMux_T_18 & _out_T_13; // @[RegisterRouter.scala:87:24]
assign out_roready_21 = _out_rofireMux_T_19; // @[RegisterRouter.scala:87:24]
assign out_roready_22 = _out_rofireMux_T_19; // @[RegisterRouter.scala:87:24]
assign out_roready_23 = _out_rofireMux_T_19; // @[RegisterRouter.scala:87:24]
assign out_roready_24 = _out_rofireMux_T_19; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_20 = ~_out_T_13; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_22 = _out_rofireMux_T_1 & out_backSel_5; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_23 = _out_rofireMux_T_22 & _out_T_1; // @[RegisterRouter.scala:87:24]
assign out_roready_0 = _out_rofireMux_T_23; // @[RegisterRouter.scala:87:24]
assign out_roready_1 = _out_rofireMux_T_23; // @[RegisterRouter.scala:87:24]
assign out_roready_2 = _out_rofireMux_T_23; // @[RegisterRouter.scala:87:24]
assign out_roready_3 = _out_rofireMux_T_23; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_24 = ~_out_T_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_26 = _out_rofireMux_T_1 & out_backSel_6; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_27 = _out_rofireMux_T_26 & _out_T_31; // @[RegisterRouter.scala:87:24]
assign out_roready_64 = _out_rofireMux_T_27; // @[RegisterRouter.scala:87:24]
assign out_roready_65 = _out_rofireMux_T_27; // @[RegisterRouter.scala:87:24]
assign out_roready_66 = _out_rofireMux_T_27; // @[RegisterRouter.scala:87:24]
assign out_roready_67 = _out_rofireMux_T_27; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_28 = ~_out_T_31; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_30 = _out_rofireMux_T_1 & out_backSel_7; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_31 = _out_rofireMux_T_30 & _out_T_53; // @[RegisterRouter.scala:87:24]
assign out_roready_120 = _out_rofireMux_T_31; // @[RegisterRouter.scala:87:24]
assign out_roready_121 = _out_rofireMux_T_31; // @[RegisterRouter.scala:87:24]
assign out_roready_122 = _out_rofireMux_T_31; // @[RegisterRouter.scala:87:24]
assign out_roready_123 = _out_rofireMux_T_31; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_32 = ~_out_T_53; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_34 = _out_rofireMux_T_1 & out_backSel_8; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_35 = _out_rofireMux_T_34 & _out_T_11; // @[RegisterRouter.scala:87:24]
assign out_roready_17 = _out_rofireMux_T_35; // @[RegisterRouter.scala:87:24]
assign out_roready_18 = _out_rofireMux_T_35; // @[RegisterRouter.scala:87:24]
assign out_roready_19 = _out_rofireMux_T_35; // @[RegisterRouter.scala:87:24]
assign out_roready_20 = _out_rofireMux_T_35; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_36 = ~_out_T_11; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_38 = _out_rofireMux_T_1 & out_backSel_9; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_39 = _out_rofireMux_T_38 & _out_T_5; // @[RegisterRouter.scala:87:24]
assign out_roready_5 = _out_rofireMux_T_39; // @[RegisterRouter.scala:87:24]
assign out_roready_6 = _out_rofireMux_T_39; // @[RegisterRouter.scala:87:24]
assign out_roready_7 = _out_rofireMux_T_39; // @[RegisterRouter.scala:87:24]
assign out_roready_8 = _out_rofireMux_T_39; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_40 = ~_out_T_5; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_42 = _out_rofireMux_T_1 & out_backSel_10; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_43 = _out_rofireMux_T_42 & _out_T_17; // @[RegisterRouter.scala:87:24]
assign out_roready_29 = _out_rofireMux_T_43; // @[RegisterRouter.scala:87:24]
assign out_roready_30 = _out_rofireMux_T_43; // @[RegisterRouter.scala:87:24]
assign out_roready_31 = _out_rofireMux_T_43; // @[RegisterRouter.scala:87:24]
assign out_roready_32 = _out_rofireMux_T_43; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_44 = ~_out_T_17; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_46 = _out_rofireMux_T_1 & out_backSel_11; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_47 = _out_rofireMux_T_46 & _out_T_57; // @[RegisterRouter.scala:87:24]
assign out_roready_128 = _out_rofireMux_T_47; // @[RegisterRouter.scala:87:24]
assign out_roready_129 = _out_rofireMux_T_47; // @[RegisterRouter.scala:87:24]
assign out_roready_130 = _out_rofireMux_T_47; // @[RegisterRouter.scala:87:24]
assign out_roready_131 = _out_rofireMux_T_47; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_48 = ~_out_T_57; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_50 = _out_rofireMux_T_1 & out_backSel_12; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_51 = _out_rofireMux_T_50; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_54 = _out_rofireMux_T_1 & out_backSel_13; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_55 = _out_rofireMux_T_54; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_58 = _out_rofireMux_T_1 & out_backSel_14; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_59 = _out_rofireMux_T_58; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_62 = _out_rofireMux_T_1 & out_backSel_15; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_63 = _out_rofireMux_T_62; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_66 = _out_rofireMux_T_1 & out_backSel_16; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_67 = _out_rofireMux_T_66; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_70 = _out_rofireMux_T_1 & out_backSel_17; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_71 = _out_rofireMux_T_70 & _out_T_43; // @[RegisterRouter.scala:87:24]
assign out_roready_82 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24]
assign out_roready_83 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24]
assign out_roready_84 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24]
assign out_roready_85 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24]
assign out_roready_86 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24]
assign out_roready_87 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24]
assign out_roready_88 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24]
assign out_roready_89 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24]
assign out_roready_90 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24]
assign out_roready_91 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24]
assign out_roready_92 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24]
assign out_roready_93 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24]
assign out_roready_94 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24]
assign out_roready_95 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24]
assign out_roready_96 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24]
assign out_roready_97 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24]
assign out_roready_98 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24]
assign out_roready_99 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24]
assign out_roready_100 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_72 = ~_out_T_43; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_74 = _out_rofireMux_T_1 & out_backSel_18; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_75 = _out_rofireMux_T_74; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_78 = _out_rofireMux_T_1 & out_backSel_19; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_79 = _out_rofireMux_T_78 & _out_T_67; // @[RegisterRouter.scala:87:24]
assign out_roready_145 = _out_rofireMux_T_79; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_80 = ~_out_T_67; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_82 = _out_rofireMux_T_1 & out_backSel_20; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_83 = _out_rofireMux_T_82; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_86 = _out_rofireMux_T_1 & out_backSel_21; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_87 = _out_rofireMux_T_86; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_90 = _out_rofireMux_T_1 & out_backSel_22; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_91 = _out_rofireMux_T_90 & _out_T_49; // @[RegisterRouter.scala:87:24]
assign out_roready_109 = _out_rofireMux_T_91; // @[RegisterRouter.scala:87:24]
assign out_roready_110 = _out_rofireMux_T_91; // @[RegisterRouter.scala:87:24]
assign out_roready_111 = _out_rofireMux_T_91; // @[RegisterRouter.scala:87:24]
assign out_roready_112 = _out_rofireMux_T_91; // @[RegisterRouter.scala:87:24]
assign out_roready_113 = _out_rofireMux_T_91; // @[RegisterRouter.scala:87:24]
assign out_roready_114 = _out_rofireMux_T_91; // @[RegisterRouter.scala:87:24]
assign out_roready_115 = _out_rofireMux_T_91; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_92 = ~_out_T_49; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_94 = _out_rofireMux_T_1 & out_backSel_23; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_95 = _out_rofireMux_T_94 & _out_T_63; // @[RegisterRouter.scala:87:24]
assign out_roready_140 = _out_rofireMux_T_95; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_96 = ~_out_T_63; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_98 = _out_rofireMux_T_1 & out_backSel_24; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_99 = _out_rofireMux_T_98 & _out_T_23; // @[RegisterRouter.scala:87:24]
assign out_roready_52 = _out_rofireMux_T_99; // @[RegisterRouter.scala:87:24]
assign out_roready_53 = _out_rofireMux_T_99; // @[RegisterRouter.scala:87:24]
assign out_roready_54 = _out_rofireMux_T_99; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_100 = ~_out_T_23; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_102 = _out_rofireMux_T_1 & out_backSel_25; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_103 = _out_rofireMux_T_102; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_106 = _out_rofireMux_T_1 & out_backSel_26; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_107 = _out_rofireMux_T_106; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_110 = _out_rofireMux_T_1 & out_backSel_27; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_111 = _out_rofireMux_T_110; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_114 = _out_rofireMux_T_1 & out_backSel_28; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_115 = _out_rofireMux_T_114; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_118 = _out_rofireMux_T_1 & out_backSel_29; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_119 = _out_rofireMux_T_118; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_122 = _out_rofireMux_T_1 & out_backSel_30; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_123 = _out_rofireMux_T_122; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_126 = _out_rofireMux_T_1 & out_backSel_31; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_127 = _out_rofireMux_T_126; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_130 = _out_rofireMux_T_1 & out_backSel_32; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_131 = _out_rofireMux_T_130 & _out_T_45; // @[RegisterRouter.scala:87:24]
assign out_roready_101 = _out_rofireMux_T_131; // @[RegisterRouter.scala:87:24]
assign out_roready_102 = _out_rofireMux_T_131; // @[RegisterRouter.scala:87:24]
assign out_roready_103 = _out_rofireMux_T_131; // @[RegisterRouter.scala:87:24]
assign out_roready_104 = _out_rofireMux_T_131; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_132 = ~_out_T_45; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_134 = _out_rofireMux_T_1 & out_backSel_33; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_135 = _out_rofireMux_T_134 & _out_T_37; // @[RegisterRouter.scala:87:24]
assign out_roready_73 = _out_rofireMux_T_135; // @[RegisterRouter.scala:87:24]
assign out_roready_74 = _out_rofireMux_T_135; // @[RegisterRouter.scala:87:24]
assign out_roready_75 = _out_rofireMux_T_135; // @[RegisterRouter.scala:87:24]
assign out_roready_76 = _out_rofireMux_T_135; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_136 = ~_out_T_37; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_138 = _out_rofireMux_T_1 & out_backSel_34; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_139 = _out_rofireMux_T_138 & _out_T_47; // @[RegisterRouter.scala:87:24]
assign out_roready_105 = _out_rofireMux_T_139; // @[RegisterRouter.scala:87:24]
assign out_roready_106 = _out_rofireMux_T_139; // @[RegisterRouter.scala:87:24]
assign out_roready_107 = _out_rofireMux_T_139; // @[RegisterRouter.scala:87:24]
assign out_roready_108 = _out_rofireMux_T_139; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_140 = ~_out_T_47; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_142 = _out_rofireMux_T_1 & out_backSel_35; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_143 = _out_rofireMux_T_142 & _out_T_9; // @[RegisterRouter.scala:87:24]
assign out_roready_13 = _out_rofireMux_T_143; // @[RegisterRouter.scala:87:24]
assign out_roready_14 = _out_rofireMux_T_143; // @[RegisterRouter.scala:87:24]
assign out_roready_15 = _out_rofireMux_T_143; // @[RegisterRouter.scala:87:24]
assign out_roready_16 = _out_rofireMux_T_143; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_144 = ~_out_T_9; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_146 = _out_rofireMux_T_1 & out_backSel_36; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_147 = _out_rofireMux_T_146 & _out_T_65; // @[RegisterRouter.scala:87:24]
assign out_roready_141 = _out_rofireMux_T_147; // @[RegisterRouter.scala:87:24]
assign out_roready_142 = _out_rofireMux_T_147; // @[RegisterRouter.scala:87:24]
assign out_roready_143 = _out_rofireMux_T_147; // @[RegisterRouter.scala:87:24]
assign out_roready_144 = _out_rofireMux_T_147; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_148 = ~_out_T_65; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_150 = _out_rofireMux_T_1 & out_backSel_37; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_151 = _out_rofireMux_T_150 & _out_T_25; // @[RegisterRouter.scala:87:24]
assign out_roready_55 = _out_rofireMux_T_151; // @[RegisterRouter.scala:87:24]
assign out_roready_56 = _out_rofireMux_T_151; // @[RegisterRouter.scala:87:24]
assign out_roready_57 = _out_rofireMux_T_151; // @[RegisterRouter.scala:87:24]
assign out_roready_58 = _out_rofireMux_T_151; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_152 = ~_out_T_25; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_154 = _out_rofireMux_T_1 & out_backSel_38; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_155 = _out_rofireMux_T_154 & _out_T_35; // @[RegisterRouter.scala:87:24]
assign out_roready_69 = _out_rofireMux_T_155; // @[RegisterRouter.scala:87:24]
assign out_roready_70 = _out_rofireMux_T_155; // @[RegisterRouter.scala:87:24]
assign out_roready_71 = _out_rofireMux_T_155; // @[RegisterRouter.scala:87:24]
assign out_roready_72 = _out_rofireMux_T_155; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_156 = ~_out_T_35; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_158 = _out_rofireMux_T_1 & out_backSel_39; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_159 = _out_rofireMux_T_158 & _out_T_55; // @[RegisterRouter.scala:87:24]
assign out_roready_124 = _out_rofireMux_T_159; // @[RegisterRouter.scala:87:24]
assign out_roready_125 = _out_rofireMux_T_159; // @[RegisterRouter.scala:87:24]
assign out_roready_126 = _out_rofireMux_T_159; // @[RegisterRouter.scala:87:24]
assign out_roready_127 = _out_rofireMux_T_159; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_160 = ~_out_T_55; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_162 = _out_rofireMux_T_1 & out_backSel_40; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_163 = _out_rofireMux_T_162 & _out_T_61; // @[RegisterRouter.scala:87:24]
assign out_roready_136 = _out_rofireMux_T_163; // @[RegisterRouter.scala:87:24]
assign out_roready_137 = _out_rofireMux_T_163; // @[RegisterRouter.scala:87:24]
assign out_roready_138 = _out_rofireMux_T_163; // @[RegisterRouter.scala:87:24]
assign out_roready_139 = _out_rofireMux_T_163; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_164 = ~_out_T_61; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_166 = _out_rofireMux_T_1 & out_backSel_41; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_167 = _out_rofireMux_T_166 & _out_T_7; // @[RegisterRouter.scala:87:24]
assign out_roready_9 = _out_rofireMux_T_167; // @[RegisterRouter.scala:87:24]
assign out_roready_10 = _out_rofireMux_T_167; // @[RegisterRouter.scala:87:24]
assign out_roready_11 = _out_rofireMux_T_167; // @[RegisterRouter.scala:87:24]
assign out_roready_12 = _out_rofireMux_T_167; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_168 = ~_out_T_7; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_170 = _out_rofireMux_T_1 & out_backSel_42; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_171 = _out_rofireMux_T_170 & _out_T_21; // @[RegisterRouter.scala:87:24]
assign out_roready_48 = _out_rofireMux_T_171; // @[RegisterRouter.scala:87:24]
assign out_roready_49 = _out_rofireMux_T_171; // @[RegisterRouter.scala:87:24]
assign out_roready_50 = _out_rofireMux_T_171; // @[RegisterRouter.scala:87:24]
assign out_roready_51 = _out_rofireMux_T_171; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_172 = ~_out_T_21; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_174 = _out_rofireMux_T_1 & out_backSel_43; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_175 = _out_rofireMux_T_174 & _out_T_59; // @[RegisterRouter.scala:87:24]
assign out_roready_132 = _out_rofireMux_T_175; // @[RegisterRouter.scala:87:24]
assign out_roready_133 = _out_rofireMux_T_175; // @[RegisterRouter.scala:87:24]
assign out_roready_134 = _out_rofireMux_T_175; // @[RegisterRouter.scala:87:24]
assign out_roready_135 = _out_rofireMux_T_175; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_176 = ~_out_T_59; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_178 = _out_rofireMux_T_1 & out_backSel_44; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_179 = _out_rofireMux_T_178 & _out_T_51; // @[RegisterRouter.scala:87:24]
assign out_roready_116 = _out_rofireMux_T_179; // @[RegisterRouter.scala:87:24]
assign out_roready_117 = _out_rofireMux_T_179; // @[RegisterRouter.scala:87:24]
assign out_roready_118 = _out_rofireMux_T_179; // @[RegisterRouter.scala:87:24]
assign out_roready_119 = _out_rofireMux_T_179; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_180 = ~_out_T_51; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_182 = _out_rofireMux_T_1 & out_backSel_45; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_183 = _out_rofireMux_T_182 & _out_T_39; // @[RegisterRouter.scala:87:24]
assign out_roready_77 = _out_rofireMux_T_183; // @[RegisterRouter.scala:87:24]
assign out_roready_78 = _out_rofireMux_T_183; // @[RegisterRouter.scala:87:24]
assign out_roready_79 = _out_rofireMux_T_183; // @[RegisterRouter.scala:87:24]
assign out_roready_80 = _out_rofireMux_T_183; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_184 = ~_out_T_39; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_186 = _out_rofireMux_T_1 & out_backSel_46; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_187 = _out_rofireMux_T_186 & _out_T_27; // @[RegisterRouter.scala:87:24]
assign out_roready_59 = _out_rofireMux_T_187; // @[RegisterRouter.scala:87:24]
assign out_roready_60 = _out_rofireMux_T_187; // @[RegisterRouter.scala:87:24]
assign out_roready_61 = _out_rofireMux_T_187; // @[RegisterRouter.scala:87:24]
assign out_roready_62 = _out_rofireMux_T_187; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_188 = ~_out_T_27; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_190 = _out_rofireMux_T_1 & out_backSel_47; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_191 = _out_rofireMux_T_190 & _out_T_15; // @[RegisterRouter.scala:87:24]
assign out_roready_25 = _out_rofireMux_T_191; // @[RegisterRouter.scala:87:24]
assign out_roready_26 = _out_rofireMux_T_191; // @[RegisterRouter.scala:87:24]
assign out_roready_27 = _out_rofireMux_T_191; // @[RegisterRouter.scala:87:24]
assign out_roready_28 = _out_rofireMux_T_191; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_192 = ~_out_T_15; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_194 = _out_rofireMux_T_1 & out_backSel_48; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_195 = _out_rofireMux_T_194; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_198 = _out_rofireMux_T_1 & out_backSel_49; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_199 = _out_rofireMux_T_198; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_202 = _out_rofireMux_T_1 & out_backSel_50; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_203 = _out_rofireMux_T_202; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_206 = _out_rofireMux_T_1 & out_backSel_51; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_207 = _out_rofireMux_T_206; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_210 = _out_rofireMux_T_1 & out_backSel_52; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_211 = _out_rofireMux_T_210; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_214 = _out_rofireMux_T_1 & out_backSel_53; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_215 = _out_rofireMux_T_214; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_218 = _out_rofireMux_T_1 & out_backSel_54; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_219 = _out_rofireMux_T_218; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_222 = _out_rofireMux_T_1 & out_backSel_55; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_223 = _out_rofireMux_T_222; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_226 = _out_rofireMux_T_1 & out_backSel_56; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_227 = _out_rofireMux_T_226 & _out_T_19; // @[RegisterRouter.scala:87:24]
assign out_roready_33 = _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24]
assign out_roready_34 = _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24]
assign out_roready_35 = _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24]
assign out_roready_36 = _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24]
assign out_roready_37 = _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24]
assign out_roready_38 = _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24]
assign out_roready_39 = _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24]
assign out_roready_40 = _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24]
assign out_roready_41 = _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24]
assign out_roready_42 = _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24]
assign out_roready_43 = _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24]
assign out_roready_44 = _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24]
assign out_roready_45 = _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24]
assign out_roready_46 = _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24]
assign out_roready_47 = _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_228 = ~_out_T_19; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_230 = _out_rofireMux_T_1 & out_backSel_57; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_231 = _out_rofireMux_T_230 & _out_T_29; // @[RegisterRouter.scala:87:24]
assign out_roready_63 = _out_rofireMux_T_231; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_232 = ~_out_T_29; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_234 = _out_rofireMux_T_1 & out_backSel_58; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_235 = _out_rofireMux_T_234; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_238 = _out_rofireMux_T_1 & out_backSel_59; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_239 = _out_rofireMux_T_238; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_242 = _out_rofireMux_T_1 & out_backSel_60; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_243 = _out_rofireMux_T_242 & _out_T_33; // @[RegisterRouter.scala:87:24]
assign out_roready_68 = _out_rofireMux_T_243; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_244 = ~_out_T_33; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_246 = _out_rofireMux_T_1 & out_backSel_61; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_247 = _out_rofireMux_T_246 & _out_T_3; // @[RegisterRouter.scala:87:24]
assign out_roready_4 = _out_rofireMux_T_247; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_248 = ~_out_T_3; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_250 = _out_rofireMux_T_1 & out_backSel_62; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_251 = _out_rofireMux_T_250; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_254 = _out_rofireMux_T_1 & out_backSel_63; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_255 = _out_rofireMux_T_254; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_2 = _out_wofireMux_T & _out_wofireMux_T_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_3 = _out_wofireMux_T_2 & out_backSel_0; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_4 = _out_wofireMux_T_3 & _out_T_41; // @[RegisterRouter.scala:87:24]
assign out_woready_81 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_5 = ~_out_T_41; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_7 = _out_wofireMux_T_2 & out_backSel_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_8 = _out_wofireMux_T_7; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_11 = _out_wofireMux_T_2 & out_backSel_2; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_12 = _out_wofireMux_T_11; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_15 = _out_wofireMux_T_2 & out_backSel_3; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_16 = _out_wofireMux_T_15; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_19 = _out_wofireMux_T_2 & out_backSel_4; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_20 = _out_wofireMux_T_19 & _out_T_13; // @[RegisterRouter.scala:87:24]
assign out_woready_21 = _out_wofireMux_T_20; // @[RegisterRouter.scala:87:24]
assign out_woready_22 = _out_wofireMux_T_20; // @[RegisterRouter.scala:87:24]
assign out_woready_23 = _out_wofireMux_T_20; // @[RegisterRouter.scala:87:24]
assign out_woready_24 = _out_wofireMux_T_20; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_21 = ~_out_T_13; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_23 = _out_wofireMux_T_2 & out_backSel_5; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_24 = _out_wofireMux_T_23 & _out_T_1; // @[RegisterRouter.scala:87:24]
assign out_woready_0 = _out_wofireMux_T_24; // @[RegisterRouter.scala:87:24]
assign out_woready_1 = _out_wofireMux_T_24; // @[RegisterRouter.scala:87:24]
assign out_woready_2 = _out_wofireMux_T_24; // @[RegisterRouter.scala:87:24]
assign out_woready_3 = _out_wofireMux_T_24; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_25 = ~_out_T_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_27 = _out_wofireMux_T_2 & out_backSel_6; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_28 = _out_wofireMux_T_27 & _out_T_31; // @[RegisterRouter.scala:87:24]
assign out_woready_64 = _out_wofireMux_T_28; // @[RegisterRouter.scala:87:24]
assign out_woready_65 = _out_wofireMux_T_28; // @[RegisterRouter.scala:87:24]
assign out_woready_66 = _out_wofireMux_T_28; // @[RegisterRouter.scala:87:24]
assign out_woready_67 = _out_wofireMux_T_28; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_29 = ~_out_T_31; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_31 = _out_wofireMux_T_2 & out_backSel_7; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_32 = _out_wofireMux_T_31 & _out_T_53; // @[RegisterRouter.scala:87:24]
assign out_woready_120 = _out_wofireMux_T_32; // @[RegisterRouter.scala:87:24]
assign out_woready_121 = _out_wofireMux_T_32; // @[RegisterRouter.scala:87:24]
assign out_woready_122 = _out_wofireMux_T_32; // @[RegisterRouter.scala:87:24]
assign out_woready_123 = _out_wofireMux_T_32; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_33 = ~_out_T_53; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_35 = _out_wofireMux_T_2 & out_backSel_8; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_36 = _out_wofireMux_T_35 & _out_T_11; // @[RegisterRouter.scala:87:24]
assign out_woready_17 = _out_wofireMux_T_36; // @[RegisterRouter.scala:87:24]
assign out_woready_18 = _out_wofireMux_T_36; // @[RegisterRouter.scala:87:24]
assign out_woready_19 = _out_wofireMux_T_36; // @[RegisterRouter.scala:87:24]
assign out_woready_20 = _out_wofireMux_T_36; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_37 = ~_out_T_11; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_39 = _out_wofireMux_T_2 & out_backSel_9; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_40 = _out_wofireMux_T_39 & _out_T_5; // @[RegisterRouter.scala:87:24]
assign out_woready_5 = _out_wofireMux_T_40; // @[RegisterRouter.scala:87:24]
assign out_woready_6 = _out_wofireMux_T_40; // @[RegisterRouter.scala:87:24]
assign out_woready_7 = _out_wofireMux_T_40; // @[RegisterRouter.scala:87:24]
assign out_woready_8 = _out_wofireMux_T_40; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_41 = ~_out_T_5; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_43 = _out_wofireMux_T_2 & out_backSel_10; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_44 = _out_wofireMux_T_43 & _out_T_17; // @[RegisterRouter.scala:87:24]
assign out_woready_29 = _out_wofireMux_T_44; // @[RegisterRouter.scala:87:24]
assign out_woready_30 = _out_wofireMux_T_44; // @[RegisterRouter.scala:87:24]
assign out_woready_31 = _out_wofireMux_T_44; // @[RegisterRouter.scala:87:24]
assign out_woready_32 = _out_wofireMux_T_44; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_45 = ~_out_T_17; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_47 = _out_wofireMux_T_2 & out_backSel_11; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_48 = _out_wofireMux_T_47 & _out_T_57; // @[RegisterRouter.scala:87:24]
assign out_woready_128 = _out_wofireMux_T_48; // @[RegisterRouter.scala:87:24]
assign out_woready_129 = _out_wofireMux_T_48; // @[RegisterRouter.scala:87:24]
assign out_woready_130 = _out_wofireMux_T_48; // @[RegisterRouter.scala:87:24]
assign out_woready_131 = _out_wofireMux_T_48; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_49 = ~_out_T_57; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_51 = _out_wofireMux_T_2 & out_backSel_12; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_52 = _out_wofireMux_T_51; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_55 = _out_wofireMux_T_2 & out_backSel_13; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_56 = _out_wofireMux_T_55; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_59 = _out_wofireMux_T_2 & out_backSel_14; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_60 = _out_wofireMux_T_59; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_63 = _out_wofireMux_T_2 & out_backSel_15; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_64 = _out_wofireMux_T_63; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_67 = _out_wofireMux_T_2 & out_backSel_16; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_68 = _out_wofireMux_T_67; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_71 = _out_wofireMux_T_2 & out_backSel_17; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_72 = _out_wofireMux_T_71 & _out_T_43; // @[RegisterRouter.scala:87:24]
assign out_woready_82 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24]
assign out_woready_83 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24]
assign out_woready_84 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24]
assign out_woready_85 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24]
assign out_woready_86 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24]
assign out_woready_87 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24]
assign out_woready_88 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24]
assign out_woready_89 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24]
assign out_woready_90 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24]
assign out_woready_91 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24]
assign out_woready_92 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24]
assign out_woready_93 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24]
assign out_woready_94 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24]
assign out_woready_95 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24]
assign out_woready_96 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24]
assign out_woready_97 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24]
assign out_woready_98 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24]
assign out_woready_99 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24]
assign out_woready_100 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_73 = ~_out_T_43; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_75 = _out_wofireMux_T_2 & out_backSel_18; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_76 = _out_wofireMux_T_75; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_79 = _out_wofireMux_T_2 & out_backSel_19; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_80 = _out_wofireMux_T_79 & _out_T_67; // @[RegisterRouter.scala:87:24]
assign out_woready_145 = _out_wofireMux_T_80; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_81 = ~_out_T_67; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_83 = _out_wofireMux_T_2 & out_backSel_20; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_84 = _out_wofireMux_T_83; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_87 = _out_wofireMux_T_2 & out_backSel_21; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_88 = _out_wofireMux_T_87; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_91 = _out_wofireMux_T_2 & out_backSel_22; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_92 = _out_wofireMux_T_91 & _out_T_49; // @[RegisterRouter.scala:87:24]
assign out_woready_109 = _out_wofireMux_T_92; // @[RegisterRouter.scala:87:24]
assign out_woready_110 = _out_wofireMux_T_92; // @[RegisterRouter.scala:87:24]
assign out_woready_111 = _out_wofireMux_T_92; // @[RegisterRouter.scala:87:24]
assign out_woready_112 = _out_wofireMux_T_92; // @[RegisterRouter.scala:87:24]
assign out_woready_113 = _out_wofireMux_T_92; // @[RegisterRouter.scala:87:24]
assign out_woready_114 = _out_wofireMux_T_92; // @[RegisterRouter.scala:87:24]
assign out_woready_115 = _out_wofireMux_T_92; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_93 = ~_out_T_49; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_95 = _out_wofireMux_T_2 & out_backSel_23; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_96 = _out_wofireMux_T_95 & _out_T_63; // @[RegisterRouter.scala:87:24]
assign out_woready_140 = _out_wofireMux_T_96; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_97 = ~_out_T_63; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_99 = _out_wofireMux_T_2 & out_backSel_24; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_100 = _out_wofireMux_T_99 & _out_T_23; // @[RegisterRouter.scala:87:24]
assign out_woready_52 = _out_wofireMux_T_100; // @[RegisterRouter.scala:87:24]
assign out_woready_53 = _out_wofireMux_T_100; // @[RegisterRouter.scala:87:24]
assign out_woready_54 = _out_wofireMux_T_100; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_101 = ~_out_T_23; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_103 = _out_wofireMux_T_2 & out_backSel_25; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_104 = _out_wofireMux_T_103; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_107 = _out_wofireMux_T_2 & out_backSel_26; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_108 = _out_wofireMux_T_107; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_111 = _out_wofireMux_T_2 & out_backSel_27; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_112 = _out_wofireMux_T_111; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_115 = _out_wofireMux_T_2 & out_backSel_28; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_116 = _out_wofireMux_T_115; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_119 = _out_wofireMux_T_2 & out_backSel_29; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_120 = _out_wofireMux_T_119; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_123 = _out_wofireMux_T_2 & out_backSel_30; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_124 = _out_wofireMux_T_123; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_127 = _out_wofireMux_T_2 & out_backSel_31; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_128 = _out_wofireMux_T_127; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_131 = _out_wofireMux_T_2 & out_backSel_32; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_132 = _out_wofireMux_T_131 & _out_T_45; // @[RegisterRouter.scala:87:24]
assign out_woready_101 = _out_wofireMux_T_132; // @[RegisterRouter.scala:87:24]
assign out_woready_102 = _out_wofireMux_T_132; // @[RegisterRouter.scala:87:24]
assign out_woready_103 = _out_wofireMux_T_132; // @[RegisterRouter.scala:87:24]
assign out_woready_104 = _out_wofireMux_T_132; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_133 = ~_out_T_45; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_135 = _out_wofireMux_T_2 & out_backSel_33; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_136 = _out_wofireMux_T_135 & _out_T_37; // @[RegisterRouter.scala:87:24]
assign out_woready_73 = _out_wofireMux_T_136; // @[RegisterRouter.scala:87:24]
assign out_woready_74 = _out_wofireMux_T_136; // @[RegisterRouter.scala:87:24]
assign out_woready_75 = _out_wofireMux_T_136; // @[RegisterRouter.scala:87:24]
assign out_woready_76 = _out_wofireMux_T_136; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_137 = ~_out_T_37; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_139 = _out_wofireMux_T_2 & out_backSel_34; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_140 = _out_wofireMux_T_139 & _out_T_47; // @[RegisterRouter.scala:87:24]
assign out_woready_105 = _out_wofireMux_T_140; // @[RegisterRouter.scala:87:24]
assign out_woready_106 = _out_wofireMux_T_140; // @[RegisterRouter.scala:87:24]
assign out_woready_107 = _out_wofireMux_T_140; // @[RegisterRouter.scala:87:24]
assign out_woready_108 = _out_wofireMux_T_140; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_141 = ~_out_T_47; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_143 = _out_wofireMux_T_2 & out_backSel_35; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_144 = _out_wofireMux_T_143 & _out_T_9; // @[RegisterRouter.scala:87:24]
assign out_woready_13 = _out_wofireMux_T_144; // @[RegisterRouter.scala:87:24]
assign out_woready_14 = _out_wofireMux_T_144; // @[RegisterRouter.scala:87:24]
assign out_woready_15 = _out_wofireMux_T_144; // @[RegisterRouter.scala:87:24]
assign out_woready_16 = _out_wofireMux_T_144; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_145 = ~_out_T_9; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_147 = _out_wofireMux_T_2 & out_backSel_36; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_148 = _out_wofireMux_T_147 & _out_T_65; // @[RegisterRouter.scala:87:24]
assign out_woready_141 = _out_wofireMux_T_148; // @[RegisterRouter.scala:87:24]
assign out_woready_142 = _out_wofireMux_T_148; // @[RegisterRouter.scala:87:24]
assign out_woready_143 = _out_wofireMux_T_148; // @[RegisterRouter.scala:87:24]
assign out_woready_144 = _out_wofireMux_T_148; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_149 = ~_out_T_65; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_151 = _out_wofireMux_T_2 & out_backSel_37; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_152 = _out_wofireMux_T_151 & _out_T_25; // @[RegisterRouter.scala:87:24]
assign out_woready_55 = _out_wofireMux_T_152; // @[RegisterRouter.scala:87:24]
assign out_woready_56 = _out_wofireMux_T_152; // @[RegisterRouter.scala:87:24]
assign out_woready_57 = _out_wofireMux_T_152; // @[RegisterRouter.scala:87:24]
assign out_woready_58 = _out_wofireMux_T_152; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_153 = ~_out_T_25; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_155 = _out_wofireMux_T_2 & out_backSel_38; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_156 = _out_wofireMux_T_155 & _out_T_35; // @[RegisterRouter.scala:87:24]
assign out_woready_69 = _out_wofireMux_T_156; // @[RegisterRouter.scala:87:24]
assign out_woready_70 = _out_wofireMux_T_156; // @[RegisterRouter.scala:87:24]
assign out_woready_71 = _out_wofireMux_T_156; // @[RegisterRouter.scala:87:24]
assign out_woready_72 = _out_wofireMux_T_156; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_157 = ~_out_T_35; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_159 = _out_wofireMux_T_2 & out_backSel_39; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_160 = _out_wofireMux_T_159 & _out_T_55; // @[RegisterRouter.scala:87:24]
assign out_woready_124 = _out_wofireMux_T_160; // @[RegisterRouter.scala:87:24]
assign out_woready_125 = _out_wofireMux_T_160; // @[RegisterRouter.scala:87:24]
assign out_woready_126 = _out_wofireMux_T_160; // @[RegisterRouter.scala:87:24]
assign out_woready_127 = _out_wofireMux_T_160; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_161 = ~_out_T_55; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_163 = _out_wofireMux_T_2 & out_backSel_40; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_164 = _out_wofireMux_T_163 & _out_T_61; // @[RegisterRouter.scala:87:24]
assign out_woready_136 = _out_wofireMux_T_164; // @[RegisterRouter.scala:87:24]
assign out_woready_137 = _out_wofireMux_T_164; // @[RegisterRouter.scala:87:24]
assign out_woready_138 = _out_wofireMux_T_164; // @[RegisterRouter.scala:87:24]
assign out_woready_139 = _out_wofireMux_T_164; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_165 = ~_out_T_61; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_167 = _out_wofireMux_T_2 & out_backSel_41; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_168 = _out_wofireMux_T_167 & _out_T_7; // @[RegisterRouter.scala:87:24]
assign out_woready_9 = _out_wofireMux_T_168; // @[RegisterRouter.scala:87:24]
assign out_woready_10 = _out_wofireMux_T_168; // @[RegisterRouter.scala:87:24]
assign out_woready_11 = _out_wofireMux_T_168; // @[RegisterRouter.scala:87:24]
assign out_woready_12 = _out_wofireMux_T_168; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_169 = ~_out_T_7; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_171 = _out_wofireMux_T_2 & out_backSel_42; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_172 = _out_wofireMux_T_171 & _out_T_21; // @[RegisterRouter.scala:87:24]
assign out_woready_48 = _out_wofireMux_T_172; // @[RegisterRouter.scala:87:24]
assign out_woready_49 = _out_wofireMux_T_172; // @[RegisterRouter.scala:87:24]
assign out_woready_50 = _out_wofireMux_T_172; // @[RegisterRouter.scala:87:24]
assign out_woready_51 = _out_wofireMux_T_172; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_173 = ~_out_T_21; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_175 = _out_wofireMux_T_2 & out_backSel_43; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_176 = _out_wofireMux_T_175 & _out_T_59; // @[RegisterRouter.scala:87:24]
assign out_woready_132 = _out_wofireMux_T_176; // @[RegisterRouter.scala:87:24]
assign out_woready_133 = _out_wofireMux_T_176; // @[RegisterRouter.scala:87:24]
assign out_woready_134 = _out_wofireMux_T_176; // @[RegisterRouter.scala:87:24]
assign out_woready_135 = _out_wofireMux_T_176; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_177 = ~_out_T_59; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_179 = _out_wofireMux_T_2 & out_backSel_44; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_180 = _out_wofireMux_T_179 & _out_T_51; // @[RegisterRouter.scala:87:24]
assign out_woready_116 = _out_wofireMux_T_180; // @[RegisterRouter.scala:87:24]
assign out_woready_117 = _out_wofireMux_T_180; // @[RegisterRouter.scala:87:24]
assign out_woready_118 = _out_wofireMux_T_180; // @[RegisterRouter.scala:87:24]
assign out_woready_119 = _out_wofireMux_T_180; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_181 = ~_out_T_51; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_183 = _out_wofireMux_T_2 & out_backSel_45; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_184 = _out_wofireMux_T_183 & _out_T_39; // @[RegisterRouter.scala:87:24]
assign out_woready_77 = _out_wofireMux_T_184; // @[RegisterRouter.scala:87:24]
assign out_woready_78 = _out_wofireMux_T_184; // @[RegisterRouter.scala:87:24]
assign out_woready_79 = _out_wofireMux_T_184; // @[RegisterRouter.scala:87:24]
assign out_woready_80 = _out_wofireMux_T_184; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_185 = ~_out_T_39; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_187 = _out_wofireMux_T_2 & out_backSel_46; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_188 = _out_wofireMux_T_187 & _out_T_27; // @[RegisterRouter.scala:87:24]
assign out_woready_59 = _out_wofireMux_T_188; // @[RegisterRouter.scala:87:24]
assign out_woready_60 = _out_wofireMux_T_188; // @[RegisterRouter.scala:87:24]
assign out_woready_61 = _out_wofireMux_T_188; // @[RegisterRouter.scala:87:24]
assign out_woready_62 = _out_wofireMux_T_188; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_189 = ~_out_T_27; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_191 = _out_wofireMux_T_2 & out_backSel_47; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_192 = _out_wofireMux_T_191 & _out_T_15; // @[RegisterRouter.scala:87:24]
assign out_woready_25 = _out_wofireMux_T_192; // @[RegisterRouter.scala:87:24]
assign out_woready_26 = _out_wofireMux_T_192; // @[RegisterRouter.scala:87:24]
assign out_woready_27 = _out_wofireMux_T_192; // @[RegisterRouter.scala:87:24]
assign out_woready_28 = _out_wofireMux_T_192; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_193 = ~_out_T_15; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_195 = _out_wofireMux_T_2 & out_backSel_48; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_196 = _out_wofireMux_T_195; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_199 = _out_wofireMux_T_2 & out_backSel_49; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_200 = _out_wofireMux_T_199; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_203 = _out_wofireMux_T_2 & out_backSel_50; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_204 = _out_wofireMux_T_203; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_207 = _out_wofireMux_T_2 & out_backSel_51; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_208 = _out_wofireMux_T_207; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_211 = _out_wofireMux_T_2 & out_backSel_52; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_212 = _out_wofireMux_T_211; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_215 = _out_wofireMux_T_2 & out_backSel_53; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_216 = _out_wofireMux_T_215; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_219 = _out_wofireMux_T_2 & out_backSel_54; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_220 = _out_wofireMux_T_219; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_223 = _out_wofireMux_T_2 & out_backSel_55; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_224 = _out_wofireMux_T_223; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_227 = _out_wofireMux_T_2 & out_backSel_56; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_228 = _out_wofireMux_T_227 & _out_T_19; // @[RegisterRouter.scala:87:24]
assign out_woready_33 = _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24]
assign out_woready_34 = _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24]
assign out_woready_35 = _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24]
assign out_woready_36 = _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24]
assign out_woready_37 = _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24]
assign out_woready_38 = _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24]
assign out_woready_39 = _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24]
assign out_woready_40 = _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24]
assign out_woready_41 = _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24]
assign out_woready_42 = _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24]
assign out_woready_43 = _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24]
assign out_woready_44 = _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24]
assign out_woready_45 = _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24]
assign out_woready_46 = _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24]
assign out_woready_47 = _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_229 = ~_out_T_19; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_231 = _out_wofireMux_T_2 & out_backSel_57; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_232 = _out_wofireMux_T_231 & _out_T_29; // @[RegisterRouter.scala:87:24]
assign out_woready_63 = _out_wofireMux_T_232; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_233 = ~_out_T_29; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_235 = _out_wofireMux_T_2 & out_backSel_58; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_236 = _out_wofireMux_T_235; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_239 = _out_wofireMux_T_2 & out_backSel_59; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_240 = _out_wofireMux_T_239; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_243 = _out_wofireMux_T_2 & out_backSel_60; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_244 = _out_wofireMux_T_243 & _out_T_33; // @[RegisterRouter.scala:87:24]
assign out_woready_68 = _out_wofireMux_T_244; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_245 = ~_out_T_33; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_247 = _out_wofireMux_T_2 & out_backSel_61; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_248 = _out_wofireMux_T_247 & _out_T_3; // @[RegisterRouter.scala:87:24]
assign out_woready_4 = _out_wofireMux_T_248; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_249 = ~_out_T_3; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_251 = _out_wofireMux_T_2 & out_backSel_62; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_252 = _out_wofireMux_T_251; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_255 = _out_wofireMux_T_2 & out_backSel_63; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_256 = _out_wofireMux_T_255; // @[RegisterRouter.scala:87:24]
assign in_ready = _out_in_ready_T; // @[RegisterRouter.scala:73:18, :87:24]
assign out_front_valid = _out_front_valid_T; // @[RegisterRouter.scala:87:24]
assign out_front_ready = _out_front_ready_T; // @[RegisterRouter.scala:87:24]
assign out_valid = _out_out_valid_T; // @[RegisterRouter.scala:87:24]
wire [63:0] _GEN_13 = {{1'h1}, {1'h1}, {_out_out_bits_data_WIRE_61}, {_out_out_bits_data_WIRE_60}, {1'h1}, {1'h1}, {_out_out_bits_data_WIRE_57}, {_out_out_bits_data_WIRE_56}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {_out_out_bits_data_WIRE_47}, {_out_out_bits_data_WIRE_46}, {_out_out_bits_data_WIRE_45}, {_out_out_bits_data_WIRE_44}, {_out_out_bits_data_WIRE_43}, {_out_out_bits_data_WIRE_42}, {_out_out_bits_data_WIRE_41}, {_out_out_bits_data_WIRE_40}, {_out_out_bits_data_WIRE_39}, {_out_out_bits_data_WIRE_38}, {_out_out_bits_data_WIRE_37}, {_out_out_bits_data_WIRE_36}, {_out_out_bits_data_WIRE_35}, {_out_out_bits_data_WIRE_34}, {_out_out_bits_data_WIRE_33}, {_out_out_bits_data_WIRE_32}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {_out_out_bits_data_WIRE_24}, {_out_out_bits_data_WIRE_23}, {_out_out_bits_data_WIRE_22}, {1'h1}, {1'h1}, {_out_out_bits_data_WIRE_19}, {1'h1}, {_out_out_bits_data_WIRE_17}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {_out_out_bits_data_WIRE_11}, {_out_out_bits_data_WIRE_10}, {_out_out_bits_data_WIRE_9}, {_out_out_bits_data_WIRE_8}, {_out_out_bits_data_WIRE_7}, {_out_out_bits_data_WIRE_6}, {_out_out_bits_data_WIRE_5}, {_out_out_bits_data_WIRE_4}, {1'h1}, {1'h1}, {1'h1}, {_out_out_bits_data_WIRE_0}}; // @[MuxLiteral.scala:49:{10,48}]
wire _out_out_bits_data_T_1 = _GEN_13[out_oindex]; // @[MuxLiteral.scala:49:10]
wire [31:0] _out_out_bits_data_WIRE_1_17 = {9'h0, _out_T_1118}; // @[MuxLiteral.scala:49:48]
wire [31:0] _out_out_bits_data_WIRE_1_22 = {3'h0, _out_T_1271}; // @[MuxLiteral.scala:49:48]
wire [63:0][31:0] _GEN_14 = {{32'h0}, {32'h0}, {_out_out_bits_data_WIRE_1_61}, {_out_out_bits_data_WIRE_1_60}, {32'h0}, {32'h0}, {_out_out_bits_data_WIRE_1_57}, {_out_out_bits_data_WIRE_1_56}, {32'h0}, {32'h0}, {32'h0}, {32'h0}, {32'h0}, {32'h0}, {32'h0}, {32'h0}, {_out_out_bits_data_WIRE_1_47}, {_out_out_bits_data_WIRE_1_46}, {_out_out_bits_data_WIRE_1_45}, {_out_out_bits_data_WIRE_1_44}, {_out_out_bits_data_WIRE_1_43}, {_out_out_bits_data_WIRE_1_42}, {_out_out_bits_data_WIRE_1_41}, {_out_out_bits_data_WIRE_1_40}, {_out_out_bits_data_WIRE_1_39}, {_out_out_bits_data_WIRE_1_38}, {_out_out_bits_data_WIRE_1_37}, {_out_out_bits_data_WIRE_1_36}, {_out_out_bits_data_WIRE_1_35}, {_out_out_bits_data_WIRE_1_34}, {_out_out_bits_data_WIRE_1_33}, {_out_out_bits_data_WIRE_1_32}, {32'h0}, {32'h0}, {32'h0}, {32'h0}, {32'h0}, {32'h0}, {32'h0}, {_out_out_bits_data_WIRE_1_24}, {_out_out_bits_data_WIRE_1_23}, {_out_out_bits_data_WIRE_1_22}, {32'h0}, {32'h0}, {_out_out_bits_data_WIRE_1_19}, {32'h0}, {_out_out_bits_data_WIRE_1_17}, {32'h0}, {32'h0}, {32'h0}, {32'h0}, {32'h0}, {_out_out_bits_data_WIRE_1_11}, {_out_out_bits_data_WIRE_1_10}, {_out_out_bits_data_WIRE_1_9}, {_out_out_bits_data_WIRE_1_8}, {_out_out_bits_data_WIRE_1_7}, {_out_out_bits_data_WIRE_1_6}, {_out_out_bits_data_WIRE_1_5}, {_out_out_bits_data_WIRE_1_4}, {32'h0}, {32'h0}, {32'h0}, {_out_out_bits_data_WIRE_1_0}}; // @[MuxLiteral.scala:49:{10,48}]
wire [31:0] _out_out_bits_data_T_3 = _GEN_14[out_oindex]; // @[MuxLiteral.scala:49:10]
assign _out_out_bits_data_T_4 = _out_out_bits_data_T_1 ? _out_out_bits_data_T_3 : 32'h0; // @[MuxLiteral.scala:49:10]
assign out_bits_data = _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24]
assign dmiNodeIn_d_bits_size = dmiNodeIn_d_bits_d_size; // @[Edges.scala:792:17]
assign dmiNodeIn_d_bits_source = dmiNodeIn_d_bits_d_source; // @[Edges.scala:792:17]
assign dmiNodeIn_d_bits_opcode = {2'h0, _dmiNodeIn_d_bits_opcode_T}; // @[RegisterRouter.scala:105:{19,25}]
reg goReg; // @[Debug.scala:1494:27]
wire flags_0_go = goReg; // @[Debug.scala:1494:27, :1517:25]
wire goAbstract; // @[Debug.scala:1495:32]
wire goCustom; // @[Debug.scala:1496:32]
wire flags_0_resume; // @[Debug.scala:1517:25]
assign flags_0_resume = _flags_resume_T; // @[Debug.scala:1517:25, :1524:80]
wire [31:0] _accessRegisterCommandWr_T = {COMMANDWrData_cmdtype, COMMANDWrData_control}; // @[Debug.scala:1280:39, :1531:59]
wire [31:0] _accessRegisterCommandWr_WIRE_1 = _accessRegisterCommandWr_T; // @[Debug.scala:1531:{59,74}]
wire [7:0] _accessRegisterCommandWr_T_8; // @[Debug.scala:1531:74]
wire _accessRegisterCommandWr_T_7; // @[Debug.scala:1531:74]
wire [7:0] accessRegisterCommandWr_cmdtype = _accessRegisterCommandWr_WIRE_cmdtype; // @[Debug.scala:1531:{44,74}]
wire [2:0] _accessRegisterCommandWr_T_6; // @[Debug.scala:1531:74]
wire accessRegisterCommandWr_reserved0 = _accessRegisterCommandWr_WIRE_reserved0; // @[Debug.scala:1531:{44,74}]
wire _accessRegisterCommandWr_T_5; // @[Debug.scala:1531:74]
wire [2:0] accessRegisterCommandWr_size = _accessRegisterCommandWr_WIRE_size; // @[Debug.scala:1531:{44,74}]
wire _accessRegisterCommandWr_T_4; // @[Debug.scala:1531:74]
wire accessRegisterCommandWr_reserved1 = _accessRegisterCommandWr_WIRE_reserved1; // @[Debug.scala:1531:{44,74}]
wire _accessRegisterCommandWr_T_3; // @[Debug.scala:1531:74]
wire accessRegisterCommandWr_postexec = _accessRegisterCommandWr_WIRE_postexec; // @[Debug.scala:1531:{44,74}]
wire _accessRegisterCommandWr_T_2; // @[Debug.scala:1531:74]
wire accessRegisterCommandWr_transfer = _accessRegisterCommandWr_WIRE_transfer; // @[Debug.scala:1531:{44,74}]
wire [15:0] _accessRegisterCommandWr_T_1; // @[Debug.scala:1531:74]
wire accessRegisterCommandWr_write = _accessRegisterCommandWr_WIRE_write; // @[Debug.scala:1531:{44,74}]
wire [15:0] accessRegisterCommandWr_regno = _accessRegisterCommandWr_WIRE_regno; // @[Debug.scala:1531:{44,74}]
assign _accessRegisterCommandWr_T_1 = _accessRegisterCommandWr_WIRE_1[15:0]; // @[Debug.scala:1531:74]
assign _accessRegisterCommandWr_WIRE_regno = _accessRegisterCommandWr_T_1; // @[Debug.scala:1531:74]
assign _accessRegisterCommandWr_T_2 = _accessRegisterCommandWr_WIRE_1[16]; // @[Debug.scala:1531:74]
assign _accessRegisterCommandWr_WIRE_write = _accessRegisterCommandWr_T_2; // @[Debug.scala:1531:74]
assign _accessRegisterCommandWr_T_3 = _accessRegisterCommandWr_WIRE_1[17]; // @[Debug.scala:1531:74]
assign _accessRegisterCommandWr_WIRE_transfer = _accessRegisterCommandWr_T_3; // @[Debug.scala:1531:74]
assign _accessRegisterCommandWr_T_4 = _accessRegisterCommandWr_WIRE_1[18]; // @[Debug.scala:1531:74]
assign _accessRegisterCommandWr_WIRE_postexec = _accessRegisterCommandWr_T_4; // @[Debug.scala:1531:74]
assign _accessRegisterCommandWr_T_5 = _accessRegisterCommandWr_WIRE_1[19]; // @[Debug.scala:1531:74]
assign _accessRegisterCommandWr_WIRE_reserved1 = _accessRegisterCommandWr_T_5; // @[Debug.scala:1531:74]
assign _accessRegisterCommandWr_T_6 = _accessRegisterCommandWr_WIRE_1[22:20]; // @[Debug.scala:1531:74]
assign _accessRegisterCommandWr_WIRE_size = _accessRegisterCommandWr_T_6; // @[Debug.scala:1531:74]
assign _accessRegisterCommandWr_T_7 = _accessRegisterCommandWr_WIRE_1[23]; // @[Debug.scala:1531:74]
assign _accessRegisterCommandWr_WIRE_reserved0 = _accessRegisterCommandWr_T_7; // @[Debug.scala:1531:74]
assign _accessRegisterCommandWr_T_8 = _accessRegisterCommandWr_WIRE_1[31:24]; // @[Debug.scala:1531:74]
assign _accessRegisterCommandWr_WIRE_cmdtype = _accessRegisterCommandWr_T_8; // @[Debug.scala:1531:74]
wire [31:0] _accessRegisterCommandReg_WIRE_1 = _accessRegisterCommandReg_T; // @[Debug.scala:1533:{56,71}]
wire [7:0] _accessRegisterCommandReg_T_8; // @[Debug.scala:1533:71]
wire _accessRegisterCommandReg_T_7; // @[Debug.scala:1533:71]
wire [7:0] accessRegisterCommandReg_cmdtype = _accessRegisterCommandReg_WIRE_cmdtype; // @[Debug.scala:1533:{44,71}]
wire [2:0] _accessRegisterCommandReg_T_6; // @[Debug.scala:1533:71]
wire accessRegisterCommandReg_reserved0 = _accessRegisterCommandReg_WIRE_reserved0; // @[Debug.scala:1533:{44,71}]
wire _accessRegisterCommandReg_T_5; // @[Debug.scala:1533:71]
wire [2:0] accessRegisterCommandReg_size = _accessRegisterCommandReg_WIRE_size; // @[Debug.scala:1533:{44,71}]
wire _accessRegisterCommandReg_T_4; // @[Debug.scala:1533:71]
wire accessRegisterCommandReg_reserved1 = _accessRegisterCommandReg_WIRE_reserved1; // @[Debug.scala:1533:{44,71}]
wire _accessRegisterCommandReg_T_3; // @[Debug.scala:1533:71]
wire accessRegisterCommandReg_postexec = _accessRegisterCommandReg_WIRE_postexec; // @[Debug.scala:1533:{44,71}]
wire _accessRegisterCommandReg_T_2; // @[Debug.scala:1533:71]
wire accessRegisterCommandReg_transfer = _accessRegisterCommandReg_WIRE_transfer; // @[Debug.scala:1533:{44,71}]
wire [15:0] _accessRegisterCommandReg_T_1; // @[Debug.scala:1533:71]
wire accessRegisterCommandReg_write = _accessRegisterCommandReg_WIRE_write; // @[Debug.scala:1533:{44,71}]
wire [15:0] accessRegisterCommandReg_regno = _accessRegisterCommandReg_WIRE_regno; // @[Debug.scala:1533:{44,71}]
assign _accessRegisterCommandReg_T_1 = _accessRegisterCommandReg_WIRE_1[15:0]; // @[Debug.scala:1533:71]
assign _accessRegisterCommandReg_WIRE_regno = _accessRegisterCommandReg_T_1; // @[Debug.scala:1533:71]
assign _accessRegisterCommandReg_T_2 = _accessRegisterCommandReg_WIRE_1[16]; // @[Debug.scala:1533:71]
assign _accessRegisterCommandReg_WIRE_write = _accessRegisterCommandReg_T_2; // @[Debug.scala:1533:71]
assign _accessRegisterCommandReg_T_3 = _accessRegisterCommandReg_WIRE_1[17]; // @[Debug.scala:1533:71]
assign _accessRegisterCommandReg_WIRE_transfer = _accessRegisterCommandReg_T_3; // @[Debug.scala:1533:71]
assign _accessRegisterCommandReg_T_4 = _accessRegisterCommandReg_WIRE_1[18]; // @[Debug.scala:1533:71]
assign _accessRegisterCommandReg_WIRE_postexec = _accessRegisterCommandReg_T_4; // @[Debug.scala:1533:71]
assign _accessRegisterCommandReg_T_5 = _accessRegisterCommandReg_WIRE_1[19]; // @[Debug.scala:1533:71]
assign _accessRegisterCommandReg_WIRE_reserved1 = _accessRegisterCommandReg_T_5; // @[Debug.scala:1533:71]
assign _accessRegisterCommandReg_T_6 = _accessRegisterCommandReg_WIRE_1[22:20]; // @[Debug.scala:1533:71]
assign _accessRegisterCommandReg_WIRE_size = _accessRegisterCommandReg_T_6; // @[Debug.scala:1533:71]
assign _accessRegisterCommandReg_T_7 = _accessRegisterCommandReg_WIRE_1[23]; // @[Debug.scala:1533:71]
assign _accessRegisterCommandReg_WIRE_reserved0 = _accessRegisterCommandReg_T_7; // @[Debug.scala:1533:71]
assign _accessRegisterCommandReg_T_8 = _accessRegisterCommandReg_WIRE_1[31:24]; // @[Debug.scala:1533:71]
assign _accessRegisterCommandReg_WIRE_cmdtype = _accessRegisterCommandReg_T_8; // @[Debug.scala:1533:71]
wire [2:0] abstractGeneratedMem_0_inst_funct3 = accessRegisterCommandReg_size; // @[Debug.scala:1533:44, :1589:22]
wire [2:0] abstractGeneratedMem_0_inst_1_funct3 = accessRegisterCommandReg_size; // @[Debug.scala:1533:44, :1601:22]
reg [31:0] abstractGeneratedMem_0; // @[Debug.scala:1586:35]
wire [31:0] _out_T_8286 = abstractGeneratedMem_0; // @[RegisterRouter.scala:87:24]
reg [31:0] abstractGeneratedMem_1; // @[Debug.scala:1586:35]
wire [4:0] abstractGeneratedMem_0_inst_rd; // @[Debug.scala:1589:22]
wire [15:0] _GEN_15 = {11'h0, accessRegisterCommandReg_regno[4:0]}; // @[Debug.scala:1533:44, :1593:54]
wire [15:0] _abstractGeneratedMem_0_inst_rd_T; // @[Debug.scala:1593:54]
assign _abstractGeneratedMem_0_inst_rd_T = _GEN_15; // @[Debug.scala:1593:54]
wire [15:0] _abstractGeneratedMem_0_inst_rs2_T; // @[Debug.scala:1608:54]
assign _abstractGeneratedMem_0_inst_rs2_T = _GEN_15; // @[Debug.scala:1593:54, :1608:54]
assign abstractGeneratedMem_0_inst_rd = _abstractGeneratedMem_0_inst_rd_T[4:0]; // @[Debug.scala:1589:22, :1593:{19,54}]
wire [11:0] abstractGeneratedMem_0_lo = {abstractGeneratedMem_0_inst_rd, 7'h3}; // @[Debug.scala:1589:22, :1597:12]
wire [19:0] abstractGeneratedMem_0_hi = {17'h7000, abstractGeneratedMem_0_inst_funct3}; // @[Debug.scala:1589:22, :1597:12]
wire [31:0] _abstractGeneratedMem_0_T = {abstractGeneratedMem_0_hi, abstractGeneratedMem_0_lo}; // @[Debug.scala:1597:12]
wire [4:0] abstractGeneratedMem_0_inst_1_rs2; // @[Debug.scala:1601:22]
assign abstractGeneratedMem_0_inst_1_rs2 = _abstractGeneratedMem_0_inst_rs2_T[4:0]; // @[Debug.scala:1601:22, :1608:{19,54}]
wire [7:0] abstractGeneratedMem_0_lo_hi = {abstractGeneratedMem_0_inst_1_funct3, 5'h0}; // @[Debug.scala:1601:22, :1610:12]
wire [14:0] abstractGeneratedMem_0_lo_1 = {abstractGeneratedMem_0_lo_hi, 7'h23}; // @[Debug.scala:1610:12]
wire [11:0] abstractGeneratedMem_0_hi_hi_1 = {7'h1C, abstractGeneratedMem_0_inst_1_rs2}; // @[Debug.scala:1601:22, :1610:12]
wire [16:0] abstractGeneratedMem_0_hi_1 = {abstractGeneratedMem_0_hi_hi_1, 5'h0}; // @[Debug.scala:1610:12]
wire [31:0] _abstractGeneratedMem_0_T_1 = {abstractGeneratedMem_0_hi_1, abstractGeneratedMem_0_lo_1}; // @[Debug.scala:1610:12]
wire [31:0] _abstractGeneratedMem_0_T_2 = accessRegisterCommandReg_write ? _abstractGeneratedMem_0_T : _abstractGeneratedMem_0_T_1; // @[Debug.scala:1533:44, :1597:12, :1610:12, :1641:14]
wire [31:0] _abstractGeneratedMem_0_T_4 = accessRegisterCommandReg_transfer ? _abstractGeneratedMem_0_T_2 : 32'h13; // @[Debug.scala:1533:44, :1640:39, :1641:14]
wire [31:0] _abstractGeneratedMem_1_T_1 = accessRegisterCommandReg_postexec ? 32'h13 : 32'h100073; // @[Debug.scala:1533:44, :1644:39]
wire [6:0] _GEN_16 = {6'h0, flags_0_resume}; // @[Debug.scala:1517:25, :1702:60]
wire [6:0] hi_1; // @[Debug.scala:1702:60]
assign hi_1 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_2; // @[Debug.scala:1702:60]
assign hi_2 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_3; // @[Debug.scala:1702:60]
assign hi_3 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_4; // @[Debug.scala:1702:60]
assign hi_4 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_5; // @[Debug.scala:1702:60]
assign hi_5 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_6; // @[Debug.scala:1702:60]
assign hi_6 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_7; // @[Debug.scala:1702:60]
assign hi_7 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_8; // @[Debug.scala:1702:60]
assign hi_8 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_9; // @[Debug.scala:1702:60]
assign hi_9 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_10; // @[Debug.scala:1702:60]
assign hi_10 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_11; // @[Debug.scala:1702:60]
assign hi_11 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_12; // @[Debug.scala:1702:60]
assign hi_12 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_13; // @[Debug.scala:1702:60]
assign hi_13 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_14; // @[Debug.scala:1702:60]
assign hi_14 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_15; // @[Debug.scala:1702:60]
assign hi_15 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_16; // @[Debug.scala:1702:60]
assign hi_16 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_17; // @[Debug.scala:1702:60]
assign hi_17 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_18; // @[Debug.scala:1702:60]
assign hi_18 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_19; // @[Debug.scala:1702:60]
assign hi_19 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_20; // @[Debug.scala:1702:60]
assign hi_20 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_21; // @[Debug.scala:1702:60]
assign hi_21 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_22; // @[Debug.scala:1702:60]
assign hi_22 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_23; // @[Debug.scala:1702:60]
assign hi_23 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_24; // @[Debug.scala:1702:60]
assign hi_24 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_25; // @[Debug.scala:1702:60]
assign hi_25 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_26; // @[Debug.scala:1702:60]
assign hi_26 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_27; // @[Debug.scala:1702:60]
assign hi_27 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_28; // @[Debug.scala:1702:60]
assign hi_28 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_29; // @[Debug.scala:1702:60]
assign hi_29 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_30; // @[Debug.scala:1702:60]
assign hi_30 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_31; // @[Debug.scala:1702:60]
assign hi_31 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_32; // @[Debug.scala:1702:60]
assign hi_32 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_33; // @[Debug.scala:1702:60]
assign hi_33 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_34; // @[Debug.scala:1702:60]
assign hi_34 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_35; // @[Debug.scala:1702:60]
assign hi_35 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_36; // @[Debug.scala:1702:60]
assign hi_36 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_37; // @[Debug.scala:1702:60]
assign hi_37 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_38; // @[Debug.scala:1702:60]
assign hi_38 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_39; // @[Debug.scala:1702:60]
assign hi_39 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_40; // @[Debug.scala:1702:60]
assign hi_40 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_41; // @[Debug.scala:1702:60]
assign hi_41 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_42; // @[Debug.scala:1702:60]
assign hi_42 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_43; // @[Debug.scala:1702:60]
assign hi_43 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_44; // @[Debug.scala:1702:60]
assign hi_44 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_45; // @[Debug.scala:1702:60]
assign hi_45 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_46; // @[Debug.scala:1702:60]
assign hi_46 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_47; // @[Debug.scala:1702:60]
assign hi_47 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_48; // @[Debug.scala:1702:60]
assign hi_48 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_49; // @[Debug.scala:1702:60]
assign hi_49 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_50; // @[Debug.scala:1702:60]
assign hi_50 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_51; // @[Debug.scala:1702:60]
assign hi_51 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_52; // @[Debug.scala:1702:60]
assign hi_52 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_53; // @[Debug.scala:1702:60]
assign hi_53 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_54; // @[Debug.scala:1702:60]
assign hi_54 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_55; // @[Debug.scala:1702:60]
assign hi_55 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_56; // @[Debug.scala:1702:60]
assign hi_56 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_57; // @[Debug.scala:1702:60]
assign hi_57 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_58; // @[Debug.scala:1702:60]
assign hi_58 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_59; // @[Debug.scala:1702:60]
assign hi_59 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_60; // @[Debug.scala:1702:60]
assign hi_60 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_61; // @[Debug.scala:1702:60]
assign hi_61 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_62; // @[Debug.scala:1702:60]
assign hi_62 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_63; // @[Debug.scala:1702:60]
assign hi_63 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_64; // @[Debug.scala:1702:60]
assign hi_64 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_65; // @[Debug.scala:1702:60]
assign hi_65 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_66; // @[Debug.scala:1702:60]
assign hi_66 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_67; // @[Debug.scala:1702:60]
assign hi_67 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_68; // @[Debug.scala:1702:60]
assign hi_68 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_69; // @[Debug.scala:1702:60]
assign hi_69 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_70; // @[Debug.scala:1702:60]
assign hi_70 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_71; // @[Debug.scala:1702:60]
assign hi_71 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_72; // @[Debug.scala:1702:60]
assign hi_72 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_73; // @[Debug.scala:1702:60]
assign hi_73 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_74; // @[Debug.scala:1702:60]
assign hi_74 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_75; // @[Debug.scala:1702:60]
assign hi_75 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_76; // @[Debug.scala:1702:60]
assign hi_76 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_77; // @[Debug.scala:1702:60]
assign hi_77 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_78; // @[Debug.scala:1702:60]
assign hi_78 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_79; // @[Debug.scala:1702:60]
assign hi_79 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_80; // @[Debug.scala:1702:60]
assign hi_80 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_81; // @[Debug.scala:1702:60]
assign hi_81 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_82; // @[Debug.scala:1702:60]
assign hi_82 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_83; // @[Debug.scala:1702:60]
assign hi_83 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_84; // @[Debug.scala:1702:60]
assign hi_84 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_85; // @[Debug.scala:1702:60]
assign hi_85 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_86; // @[Debug.scala:1702:60]
assign hi_86 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_87; // @[Debug.scala:1702:60]
assign hi_87 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_88; // @[Debug.scala:1702:60]
assign hi_88 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_89; // @[Debug.scala:1702:60]
assign hi_89 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_90; // @[Debug.scala:1702:60]
assign hi_90 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_91; // @[Debug.scala:1702:60]
assign hi_91 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_92; // @[Debug.scala:1702:60]
assign hi_92 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_93; // @[Debug.scala:1702:60]
assign hi_93 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_94; // @[Debug.scala:1702:60]
assign hi_94 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_95; // @[Debug.scala:1702:60]
assign hi_95 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_96; // @[Debug.scala:1702:60]
assign hi_96 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_97; // @[Debug.scala:1702:60]
assign hi_97 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_98; // @[Debug.scala:1702:60]
assign hi_98 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_99; // @[Debug.scala:1702:60]
assign hi_99 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_100; // @[Debug.scala:1702:60]
assign hi_100 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_101; // @[Debug.scala:1702:60]
assign hi_101 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_102; // @[Debug.scala:1702:60]
assign hi_102 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_103; // @[Debug.scala:1702:60]
assign hi_103 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_104; // @[Debug.scala:1702:60]
assign hi_104 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_105; // @[Debug.scala:1702:60]
assign hi_105 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_106; // @[Debug.scala:1702:60]
assign hi_106 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_107; // @[Debug.scala:1702:60]
assign hi_107 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_108; // @[Debug.scala:1702:60]
assign hi_108 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_109; // @[Debug.scala:1702:60]
assign hi_109 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_110; // @[Debug.scala:1702:60]
assign hi_110 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_111; // @[Debug.scala:1702:60]
assign hi_111 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_112; // @[Debug.scala:1702:60]
assign hi_112 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_113; // @[Debug.scala:1702:60]
assign hi_113 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_114; // @[Debug.scala:1702:60]
assign hi_114 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_115; // @[Debug.scala:1702:60]
assign hi_115 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_116; // @[Debug.scala:1702:60]
assign hi_116 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_117; // @[Debug.scala:1702:60]
assign hi_117 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_118; // @[Debug.scala:1702:60]
assign hi_118 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_119; // @[Debug.scala:1702:60]
assign hi_119 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_120; // @[Debug.scala:1702:60]
assign hi_120 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_121; // @[Debug.scala:1702:60]
assign hi_121 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_122; // @[Debug.scala:1702:60]
assign hi_122 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_123; // @[Debug.scala:1702:60]
assign hi_123 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_124; // @[Debug.scala:1702:60]
assign hi_124 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_125; // @[Debug.scala:1702:60]
assign hi_125 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_126; // @[Debug.scala:1702:60]
assign hi_126 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_127; // @[Debug.scala:1702:60]
assign hi_127 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_128; // @[Debug.scala:1702:60]
assign hi_128 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_129; // @[Debug.scala:1702:60]
assign hi_129 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_130; // @[Debug.scala:1702:60]
assign hi_130 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_131; // @[Debug.scala:1702:60]
assign hi_131 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_132; // @[Debug.scala:1702:60]
assign hi_132 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_133; // @[Debug.scala:1702:60]
assign hi_133 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_134; // @[Debug.scala:1702:60]
assign hi_134 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_135; // @[Debug.scala:1702:60]
assign hi_135 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_136; // @[Debug.scala:1702:60]
assign hi_136 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_137; // @[Debug.scala:1702:60]
assign hi_137 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_138; // @[Debug.scala:1702:60]
assign hi_138 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_139; // @[Debug.scala:1702:60]
assign hi_139 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_140; // @[Debug.scala:1702:60]
assign hi_140 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_141; // @[Debug.scala:1702:60]
assign hi_141 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_142; // @[Debug.scala:1702:60]
assign hi_142 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_143; // @[Debug.scala:1702:60]
assign hi_143 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_144; // @[Debug.scala:1702:60]
assign hi_144 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_145; // @[Debug.scala:1702:60]
assign hi_145 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_146; // @[Debug.scala:1702:60]
assign hi_146 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_147; // @[Debug.scala:1702:60]
assign hi_147 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_148; // @[Debug.scala:1702:60]
assign hi_148 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_149; // @[Debug.scala:1702:60]
assign hi_149 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_150; // @[Debug.scala:1702:60]
assign hi_150 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_151; // @[Debug.scala:1702:60]
assign hi_151 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_152; // @[Debug.scala:1702:60]
assign hi_152 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_153; // @[Debug.scala:1702:60]
assign hi_153 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_154; // @[Debug.scala:1702:60]
assign hi_154 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_155; // @[Debug.scala:1702:60]
assign hi_155 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_156; // @[Debug.scala:1702:60]
assign hi_156 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_157; // @[Debug.scala:1702:60]
assign hi_157 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_158; // @[Debug.scala:1702:60]
assign hi_158 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_159; // @[Debug.scala:1702:60]
assign hi_159 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_160; // @[Debug.scala:1702:60]
assign hi_160 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_161; // @[Debug.scala:1702:60]
assign hi_161 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_162; // @[Debug.scala:1702:60]
assign hi_162 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_163; // @[Debug.scala:1702:60]
assign hi_163 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_164; // @[Debug.scala:1702:60]
assign hi_164 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_165; // @[Debug.scala:1702:60]
assign hi_165 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_166; // @[Debug.scala:1702:60]
assign hi_166 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_167; // @[Debug.scala:1702:60]
assign hi_167 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_168; // @[Debug.scala:1702:60]
assign hi_168 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_169; // @[Debug.scala:1702:60]
assign hi_169 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_170; // @[Debug.scala:1702:60]
assign hi_170 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_171; // @[Debug.scala:1702:60]
assign hi_171 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_172; // @[Debug.scala:1702:60]
assign hi_172 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_173; // @[Debug.scala:1702:60]
assign hi_173 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_174; // @[Debug.scala:1702:60]
assign hi_174 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_175; // @[Debug.scala:1702:60]
assign hi_175 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_176; // @[Debug.scala:1702:60]
assign hi_176 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_177; // @[Debug.scala:1702:60]
assign hi_177 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_178; // @[Debug.scala:1702:60]
assign hi_178 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_179; // @[Debug.scala:1702:60]
assign hi_179 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_180; // @[Debug.scala:1702:60]
assign hi_180 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_181; // @[Debug.scala:1702:60]
assign hi_181 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_182; // @[Debug.scala:1702:60]
assign hi_182 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_183; // @[Debug.scala:1702:60]
assign hi_183 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_184; // @[Debug.scala:1702:60]
assign hi_184 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_185; // @[Debug.scala:1702:60]
assign hi_185 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_186; // @[Debug.scala:1702:60]
assign hi_186 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_187; // @[Debug.scala:1702:60]
assign hi_187 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_188; // @[Debug.scala:1702:60]
assign hi_188 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_189; // @[Debug.scala:1702:60]
assign hi_189 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_190; // @[Debug.scala:1702:60]
assign hi_190 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_191; // @[Debug.scala:1702:60]
assign hi_191 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_192; // @[Debug.scala:1702:60]
assign hi_192 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_193; // @[Debug.scala:1702:60]
assign hi_193 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_194; // @[Debug.scala:1702:60]
assign hi_194 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_195; // @[Debug.scala:1702:60]
assign hi_195 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_196; // @[Debug.scala:1702:60]
assign hi_196 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_197; // @[Debug.scala:1702:60]
assign hi_197 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_198; // @[Debug.scala:1702:60]
assign hi_198 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_199; // @[Debug.scala:1702:60]
assign hi_199 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_200; // @[Debug.scala:1702:60]
assign hi_200 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_201; // @[Debug.scala:1702:60]
assign hi_201 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_202; // @[Debug.scala:1702:60]
assign hi_202 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_203; // @[Debug.scala:1702:60]
assign hi_203 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_204; // @[Debug.scala:1702:60]
assign hi_204 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_205; // @[Debug.scala:1702:60]
assign hi_205 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_206; // @[Debug.scala:1702:60]
assign hi_206 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_207; // @[Debug.scala:1702:60]
assign hi_207 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_208; // @[Debug.scala:1702:60]
assign hi_208 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_209; // @[Debug.scala:1702:60]
assign hi_209 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_210; // @[Debug.scala:1702:60]
assign hi_210 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_211; // @[Debug.scala:1702:60]
assign hi_211 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_212; // @[Debug.scala:1702:60]
assign hi_212 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_213; // @[Debug.scala:1702:60]
assign hi_213 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_214; // @[Debug.scala:1702:60]
assign hi_214 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_215; // @[Debug.scala:1702:60]
assign hi_215 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_216; // @[Debug.scala:1702:60]
assign hi_216 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_217; // @[Debug.scala:1702:60]
assign hi_217 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_218; // @[Debug.scala:1702:60]
assign hi_218 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_219; // @[Debug.scala:1702:60]
assign hi_219 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_220; // @[Debug.scala:1702:60]
assign hi_220 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_221; // @[Debug.scala:1702:60]
assign hi_221 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_222; // @[Debug.scala:1702:60]
assign hi_222 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_223; // @[Debug.scala:1702:60]
assign hi_223 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_224; // @[Debug.scala:1702:60]
assign hi_224 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_225; // @[Debug.scala:1702:60]
assign hi_225 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_226; // @[Debug.scala:1702:60]
assign hi_226 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_227; // @[Debug.scala:1702:60]
assign hi_227 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_228; // @[Debug.scala:1702:60]
assign hi_228 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_229; // @[Debug.scala:1702:60]
assign hi_229 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_230; // @[Debug.scala:1702:60]
assign hi_230 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_231; // @[Debug.scala:1702:60]
assign hi_231 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_232; // @[Debug.scala:1702:60]
assign hi_232 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_233; // @[Debug.scala:1702:60]
assign hi_233 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_234; // @[Debug.scala:1702:60]
assign hi_234 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_235; // @[Debug.scala:1702:60]
assign hi_235 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_236; // @[Debug.scala:1702:60]
assign hi_236 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_237; // @[Debug.scala:1702:60]
assign hi_237 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_238; // @[Debug.scala:1702:60]
assign hi_238 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_239; // @[Debug.scala:1702:60]
assign hi_239 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_240; // @[Debug.scala:1702:60]
assign hi_240 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_241; // @[Debug.scala:1702:60]
assign hi_241 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_242; // @[Debug.scala:1702:60]
assign hi_242 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_243; // @[Debug.scala:1702:60]
assign hi_243 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_244; // @[Debug.scala:1702:60]
assign hi_244 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_245; // @[Debug.scala:1702:60]
assign hi_245 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_246; // @[Debug.scala:1702:60]
assign hi_246 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_247; // @[Debug.scala:1702:60]
assign hi_247 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_248; // @[Debug.scala:1702:60]
assign hi_248 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_249; // @[Debug.scala:1702:60]
assign hi_249 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_250; // @[Debug.scala:1702:60]
assign hi_250 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_251; // @[Debug.scala:1702:60]
assign hi_251 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_252; // @[Debug.scala:1702:60]
assign hi_252 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_253; // @[Debug.scala:1702:60]
assign hi_253 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_254; // @[Debug.scala:1702:60]
assign hi_254 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_255; // @[Debug.scala:1702:60]
assign hi_255 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_256; // @[Debug.scala:1702:60]
assign hi_256 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_257; // @[Debug.scala:1702:60]
assign hi_257 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_258; // @[Debug.scala:1702:60]
assign hi_258 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_259; // @[Debug.scala:1702:60]
assign hi_259 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_260; // @[Debug.scala:1702:60]
assign hi_260 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_261; // @[Debug.scala:1702:60]
assign hi_261 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_262; // @[Debug.scala:1702:60]
assign hi_262 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_263; // @[Debug.scala:1702:60]
assign hi_263 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_264; // @[Debug.scala:1702:60]
assign hi_264 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_265; // @[Debug.scala:1702:60]
assign hi_265 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_266; // @[Debug.scala:1702:60]
assign hi_266 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_267; // @[Debug.scala:1702:60]
assign hi_267 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_268; // @[Debug.scala:1702:60]
assign hi_268 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_269; // @[Debug.scala:1702:60]
assign hi_269 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_270; // @[Debug.scala:1702:60]
assign hi_270 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_271; // @[Debug.scala:1702:60]
assign hi_271 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_272; // @[Debug.scala:1702:60]
assign hi_272 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_273; // @[Debug.scala:1702:60]
assign hi_273 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_274; // @[Debug.scala:1702:60]
assign hi_274 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_275; // @[Debug.scala:1702:60]
assign hi_275 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_276; // @[Debug.scala:1702:60]
assign hi_276 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_277; // @[Debug.scala:1702:60]
assign hi_277 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_278; // @[Debug.scala:1702:60]
assign hi_278 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_279; // @[Debug.scala:1702:60]
assign hi_279 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_280; // @[Debug.scala:1702:60]
assign hi_280 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_281; // @[Debug.scala:1702:60]
assign hi_281 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_282; // @[Debug.scala:1702:60]
assign hi_282 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_283; // @[Debug.scala:1702:60]
assign hi_283 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_284; // @[Debug.scala:1702:60]
assign hi_284 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_285; // @[Debug.scala:1702:60]
assign hi_285 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_286; // @[Debug.scala:1702:60]
assign hi_286 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_287; // @[Debug.scala:1702:60]
assign hi_287 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_288; // @[Debug.scala:1702:60]
assign hi_288 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_289; // @[Debug.scala:1702:60]
assign hi_289 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_290; // @[Debug.scala:1702:60]
assign hi_290 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_291; // @[Debug.scala:1702:60]
assign hi_291 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_292; // @[Debug.scala:1702:60]
assign hi_292 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_293; // @[Debug.scala:1702:60]
assign hi_293 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_294; // @[Debug.scala:1702:60]
assign hi_294 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_295; // @[Debug.scala:1702:60]
assign hi_295 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_296; // @[Debug.scala:1702:60]
assign hi_296 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_297; // @[Debug.scala:1702:60]
assign hi_297 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_298; // @[Debug.scala:1702:60]
assign hi_298 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_299; // @[Debug.scala:1702:60]
assign hi_299 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_300; // @[Debug.scala:1702:60]
assign hi_300 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_301; // @[Debug.scala:1702:60]
assign hi_301 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_302; // @[Debug.scala:1702:60]
assign hi_302 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_303; // @[Debug.scala:1702:60]
assign hi_303 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_304; // @[Debug.scala:1702:60]
assign hi_304 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_305; // @[Debug.scala:1702:60]
assign hi_305 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_306; // @[Debug.scala:1702:60]
assign hi_306 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_307; // @[Debug.scala:1702:60]
assign hi_307 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_308; // @[Debug.scala:1702:60]
assign hi_308 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_309; // @[Debug.scala:1702:60]
assign hi_309 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_310; // @[Debug.scala:1702:60]
assign hi_310 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_311; // @[Debug.scala:1702:60]
assign hi_311 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_312; // @[Debug.scala:1702:60]
assign hi_312 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_313; // @[Debug.scala:1702:60]
assign hi_313 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_314; // @[Debug.scala:1702:60]
assign hi_314 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_315; // @[Debug.scala:1702:60]
assign hi_315 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_316; // @[Debug.scala:1702:60]
assign hi_316 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_317; // @[Debug.scala:1702:60]
assign hi_317 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_318; // @[Debug.scala:1702:60]
assign hi_318 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_319; // @[Debug.scala:1702:60]
assign hi_319 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_320; // @[Debug.scala:1702:60]
assign hi_320 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_321; // @[Debug.scala:1702:60]
assign hi_321 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_322; // @[Debug.scala:1702:60]
assign hi_322 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_323; // @[Debug.scala:1702:60]
assign hi_323 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_324; // @[Debug.scala:1702:60]
assign hi_324 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_325; // @[Debug.scala:1702:60]
assign hi_325 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_326; // @[Debug.scala:1702:60]
assign hi_326 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_327; // @[Debug.scala:1702:60]
assign hi_327 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_328; // @[Debug.scala:1702:60]
assign hi_328 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_329; // @[Debug.scala:1702:60]
assign hi_329 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_330; // @[Debug.scala:1702:60]
assign hi_330 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_331; // @[Debug.scala:1702:60]
assign hi_331 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_332; // @[Debug.scala:1702:60]
assign hi_332 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_333; // @[Debug.scala:1702:60]
assign hi_333 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_334; // @[Debug.scala:1702:60]
assign hi_334 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_335; // @[Debug.scala:1702:60]
assign hi_335 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_336; // @[Debug.scala:1702:60]
assign hi_336 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_337; // @[Debug.scala:1702:60]
assign hi_337 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_338; // @[Debug.scala:1702:60]
assign hi_338 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_339; // @[Debug.scala:1702:60]
assign hi_339 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_340; // @[Debug.scala:1702:60]
assign hi_340 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_341; // @[Debug.scala:1702:60]
assign hi_341 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_342; // @[Debug.scala:1702:60]
assign hi_342 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_343; // @[Debug.scala:1702:60]
assign hi_343 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_344; // @[Debug.scala:1702:60]
assign hi_344 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_345; // @[Debug.scala:1702:60]
assign hi_345 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_346; // @[Debug.scala:1702:60]
assign hi_346 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_347; // @[Debug.scala:1702:60]
assign hi_347 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_348; // @[Debug.scala:1702:60]
assign hi_348 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_349; // @[Debug.scala:1702:60]
assign hi_349 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_350; // @[Debug.scala:1702:60]
assign hi_350 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_351; // @[Debug.scala:1702:60]
assign hi_351 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_352; // @[Debug.scala:1702:60]
assign hi_352 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_353; // @[Debug.scala:1702:60]
assign hi_353 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_354; // @[Debug.scala:1702:60]
assign hi_354 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_355; // @[Debug.scala:1702:60]
assign hi_355 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_356; // @[Debug.scala:1702:60]
assign hi_356 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_357; // @[Debug.scala:1702:60]
assign hi_357 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_358; // @[Debug.scala:1702:60]
assign hi_358 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_359; // @[Debug.scala:1702:60]
assign hi_359 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_360; // @[Debug.scala:1702:60]
assign hi_360 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_361; // @[Debug.scala:1702:60]
assign hi_361 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_362; // @[Debug.scala:1702:60]
assign hi_362 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_363; // @[Debug.scala:1702:60]
assign hi_363 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_364; // @[Debug.scala:1702:60]
assign hi_364 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_365; // @[Debug.scala:1702:60]
assign hi_365 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_366; // @[Debug.scala:1702:60]
assign hi_366 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_367; // @[Debug.scala:1702:60]
assign hi_367 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_368; // @[Debug.scala:1702:60]
assign hi_368 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_369; // @[Debug.scala:1702:60]
assign hi_369 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_370; // @[Debug.scala:1702:60]
assign hi_370 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_371; // @[Debug.scala:1702:60]
assign hi_371 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_372; // @[Debug.scala:1702:60]
assign hi_372 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_373; // @[Debug.scala:1702:60]
assign hi_373 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_374; // @[Debug.scala:1702:60]
assign hi_374 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_375; // @[Debug.scala:1702:60]
assign hi_375 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_376; // @[Debug.scala:1702:60]
assign hi_376 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_377; // @[Debug.scala:1702:60]
assign hi_377 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_378; // @[Debug.scala:1702:60]
assign hi_378 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_379; // @[Debug.scala:1702:60]
assign hi_379 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_380; // @[Debug.scala:1702:60]
assign hi_380 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_381; // @[Debug.scala:1702:60]
assign hi_381 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_382; // @[Debug.scala:1702:60]
assign hi_382 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_383; // @[Debug.scala:1702:60]
assign hi_383 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_384; // @[Debug.scala:1702:60]
assign hi_384 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_385; // @[Debug.scala:1702:60]
assign hi_385 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_386; // @[Debug.scala:1702:60]
assign hi_386 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_387; // @[Debug.scala:1702:60]
assign hi_387 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_388; // @[Debug.scala:1702:60]
assign hi_388 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_389; // @[Debug.scala:1702:60]
assign hi_389 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_390; // @[Debug.scala:1702:60]
assign hi_390 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_391; // @[Debug.scala:1702:60]
assign hi_391 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_392; // @[Debug.scala:1702:60]
assign hi_392 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_393; // @[Debug.scala:1702:60]
assign hi_393 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_394; // @[Debug.scala:1702:60]
assign hi_394 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_395; // @[Debug.scala:1702:60]
assign hi_395 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_396; // @[Debug.scala:1702:60]
assign hi_396 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_397; // @[Debug.scala:1702:60]
assign hi_397 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_398; // @[Debug.scala:1702:60]
assign hi_398 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_399; // @[Debug.scala:1702:60]
assign hi_399 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_400; // @[Debug.scala:1702:60]
assign hi_400 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_401; // @[Debug.scala:1702:60]
assign hi_401 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_402; // @[Debug.scala:1702:60]
assign hi_402 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_403; // @[Debug.scala:1702:60]
assign hi_403 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_404; // @[Debug.scala:1702:60]
assign hi_404 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_405; // @[Debug.scala:1702:60]
assign hi_405 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_406; // @[Debug.scala:1702:60]
assign hi_406 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_407; // @[Debug.scala:1702:60]
assign hi_407 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_408; // @[Debug.scala:1702:60]
assign hi_408 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_409; // @[Debug.scala:1702:60]
assign hi_409 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_410; // @[Debug.scala:1702:60]
assign hi_410 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_411; // @[Debug.scala:1702:60]
assign hi_411 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_412; // @[Debug.scala:1702:60]
assign hi_412 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_413; // @[Debug.scala:1702:60]
assign hi_413 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_414; // @[Debug.scala:1702:60]
assign hi_414 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_415; // @[Debug.scala:1702:60]
assign hi_415 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_416; // @[Debug.scala:1702:60]
assign hi_416 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_417; // @[Debug.scala:1702:60]
assign hi_417 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_418; // @[Debug.scala:1702:60]
assign hi_418 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_419; // @[Debug.scala:1702:60]
assign hi_419 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_420; // @[Debug.scala:1702:60]
assign hi_420 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_421; // @[Debug.scala:1702:60]
assign hi_421 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_422; // @[Debug.scala:1702:60]
assign hi_422 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_423; // @[Debug.scala:1702:60]
assign hi_423 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_424; // @[Debug.scala:1702:60]
assign hi_424 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_425; // @[Debug.scala:1702:60]
assign hi_425 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_426; // @[Debug.scala:1702:60]
assign hi_426 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_427; // @[Debug.scala:1702:60]
assign hi_427 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_428; // @[Debug.scala:1702:60]
assign hi_428 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_429; // @[Debug.scala:1702:60]
assign hi_429 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_430; // @[Debug.scala:1702:60]
assign hi_430 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_431; // @[Debug.scala:1702:60]
assign hi_431 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_432; // @[Debug.scala:1702:60]
assign hi_432 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_433; // @[Debug.scala:1702:60]
assign hi_433 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_434; // @[Debug.scala:1702:60]
assign hi_434 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_435; // @[Debug.scala:1702:60]
assign hi_435 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_436; // @[Debug.scala:1702:60]
assign hi_436 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_437; // @[Debug.scala:1702:60]
assign hi_437 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_438; // @[Debug.scala:1702:60]
assign hi_438 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_439; // @[Debug.scala:1702:60]
assign hi_439 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_440; // @[Debug.scala:1702:60]
assign hi_440 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_441; // @[Debug.scala:1702:60]
assign hi_441 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_442; // @[Debug.scala:1702:60]
assign hi_442 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_443; // @[Debug.scala:1702:60]
assign hi_443 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_444; // @[Debug.scala:1702:60]
assign hi_444 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_445; // @[Debug.scala:1702:60]
assign hi_445 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_446; // @[Debug.scala:1702:60]
assign hi_446 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_447; // @[Debug.scala:1702:60]
assign hi_447 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_448; // @[Debug.scala:1702:60]
assign hi_448 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_449; // @[Debug.scala:1702:60]
assign hi_449 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_450; // @[Debug.scala:1702:60]
assign hi_450 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_451; // @[Debug.scala:1702:60]
assign hi_451 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_452; // @[Debug.scala:1702:60]
assign hi_452 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_453; // @[Debug.scala:1702:60]
assign hi_453 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_454; // @[Debug.scala:1702:60]
assign hi_454 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_455; // @[Debug.scala:1702:60]
assign hi_455 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_456; // @[Debug.scala:1702:60]
assign hi_456 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_457; // @[Debug.scala:1702:60]
assign hi_457 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_458; // @[Debug.scala:1702:60]
assign hi_458 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_459; // @[Debug.scala:1702:60]
assign hi_459 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_460; // @[Debug.scala:1702:60]
assign hi_460 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_461; // @[Debug.scala:1702:60]
assign hi_461 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_462; // @[Debug.scala:1702:60]
assign hi_462 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_463; // @[Debug.scala:1702:60]
assign hi_463 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_464; // @[Debug.scala:1702:60]
assign hi_464 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_465; // @[Debug.scala:1702:60]
assign hi_465 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_466; // @[Debug.scala:1702:60]
assign hi_466 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_467; // @[Debug.scala:1702:60]
assign hi_467 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_468; // @[Debug.scala:1702:60]
assign hi_468 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_469; // @[Debug.scala:1702:60]
assign hi_469 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_470; // @[Debug.scala:1702:60]
assign hi_470 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_471; // @[Debug.scala:1702:60]
assign hi_471 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_472; // @[Debug.scala:1702:60]
assign hi_472 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_473; // @[Debug.scala:1702:60]
assign hi_473 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_474; // @[Debug.scala:1702:60]
assign hi_474 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_475; // @[Debug.scala:1702:60]
assign hi_475 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_476; // @[Debug.scala:1702:60]
assign hi_476 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_477; // @[Debug.scala:1702:60]
assign hi_477 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_478; // @[Debug.scala:1702:60]
assign hi_478 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_479; // @[Debug.scala:1702:60]
assign hi_479 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_480; // @[Debug.scala:1702:60]
assign hi_480 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_481; // @[Debug.scala:1702:60]
assign hi_481 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_482; // @[Debug.scala:1702:60]
assign hi_482 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_483; // @[Debug.scala:1702:60]
assign hi_483 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_484; // @[Debug.scala:1702:60]
assign hi_484 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_485; // @[Debug.scala:1702:60]
assign hi_485 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_486; // @[Debug.scala:1702:60]
assign hi_486 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_487; // @[Debug.scala:1702:60]
assign hi_487 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_488; // @[Debug.scala:1702:60]
assign hi_488 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_489; // @[Debug.scala:1702:60]
assign hi_489 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_490; // @[Debug.scala:1702:60]
assign hi_490 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_491; // @[Debug.scala:1702:60]
assign hi_491 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_492; // @[Debug.scala:1702:60]
assign hi_492 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_493; // @[Debug.scala:1702:60]
assign hi_493 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_494; // @[Debug.scala:1702:60]
assign hi_494 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_495; // @[Debug.scala:1702:60]
assign hi_495 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_496; // @[Debug.scala:1702:60]
assign hi_496 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_497; // @[Debug.scala:1702:60]
assign hi_497 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_498; // @[Debug.scala:1702:60]
assign hi_498 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_499; // @[Debug.scala:1702:60]
assign hi_499 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_500; // @[Debug.scala:1702:60]
assign hi_500 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_501; // @[Debug.scala:1702:60]
assign hi_501 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_502; // @[Debug.scala:1702:60]
assign hi_502 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_503; // @[Debug.scala:1702:60]
assign hi_503 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_504; // @[Debug.scala:1702:60]
assign hi_504 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_505; // @[Debug.scala:1702:60]
assign hi_505 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_506; // @[Debug.scala:1702:60]
assign hi_506 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_507; // @[Debug.scala:1702:60]
assign hi_507 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_508; // @[Debug.scala:1702:60]
assign hi_508 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_509; // @[Debug.scala:1702:60]
assign hi_509 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_510; // @[Debug.scala:1702:60]
assign hi_510 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_511; // @[Debug.scala:1702:60]
assign hi_511 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_512; // @[Debug.scala:1702:60]
assign hi_512 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_513; // @[Debug.scala:1702:60]
assign hi_513 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_514; // @[Debug.scala:1702:60]
assign hi_514 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_515; // @[Debug.scala:1702:60]
assign hi_515 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_516; // @[Debug.scala:1702:60]
assign hi_516 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_517; // @[Debug.scala:1702:60]
assign hi_517 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_518; // @[Debug.scala:1702:60]
assign hi_518 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_519; // @[Debug.scala:1702:60]
assign hi_519 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_520; // @[Debug.scala:1702:60]
assign hi_520 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_521; // @[Debug.scala:1702:60]
assign hi_521 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_522; // @[Debug.scala:1702:60]
assign hi_522 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_523; // @[Debug.scala:1702:60]
assign hi_523 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_524; // @[Debug.scala:1702:60]
assign hi_524 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_525; // @[Debug.scala:1702:60]
assign hi_525 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_526; // @[Debug.scala:1702:60]
assign hi_526 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_527; // @[Debug.scala:1702:60]
assign hi_527 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_528; // @[Debug.scala:1702:60]
assign hi_528 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_529; // @[Debug.scala:1702:60]
assign hi_529 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_530; // @[Debug.scala:1702:60]
assign hi_530 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_531; // @[Debug.scala:1702:60]
assign hi_531 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_532; // @[Debug.scala:1702:60]
assign hi_532 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_533; // @[Debug.scala:1702:60]
assign hi_533 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_534; // @[Debug.scala:1702:60]
assign hi_534 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_535; // @[Debug.scala:1702:60]
assign hi_535 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_536; // @[Debug.scala:1702:60]
assign hi_536 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_537; // @[Debug.scala:1702:60]
assign hi_537 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_538; // @[Debug.scala:1702:60]
assign hi_538 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_539; // @[Debug.scala:1702:60]
assign hi_539 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_540; // @[Debug.scala:1702:60]
assign hi_540 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_541; // @[Debug.scala:1702:60]
assign hi_541 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_542; // @[Debug.scala:1702:60]
assign hi_542 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_543; // @[Debug.scala:1702:60]
assign hi_543 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_544; // @[Debug.scala:1702:60]
assign hi_544 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_545; // @[Debug.scala:1702:60]
assign hi_545 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_546; // @[Debug.scala:1702:60]
assign hi_546 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_547; // @[Debug.scala:1702:60]
assign hi_547 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_548; // @[Debug.scala:1702:60]
assign hi_548 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_549; // @[Debug.scala:1702:60]
assign hi_549 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_550; // @[Debug.scala:1702:60]
assign hi_550 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_551; // @[Debug.scala:1702:60]
assign hi_551 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_552; // @[Debug.scala:1702:60]
assign hi_552 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_553; // @[Debug.scala:1702:60]
assign hi_553 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_554; // @[Debug.scala:1702:60]
assign hi_554 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_555; // @[Debug.scala:1702:60]
assign hi_555 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_556; // @[Debug.scala:1702:60]
assign hi_556 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_557; // @[Debug.scala:1702:60]
assign hi_557 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_558; // @[Debug.scala:1702:60]
assign hi_558 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_559; // @[Debug.scala:1702:60]
assign hi_559 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_560; // @[Debug.scala:1702:60]
assign hi_560 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_561; // @[Debug.scala:1702:60]
assign hi_561 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_562; // @[Debug.scala:1702:60]
assign hi_562 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_563; // @[Debug.scala:1702:60]
assign hi_563 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_564; // @[Debug.scala:1702:60]
assign hi_564 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_565; // @[Debug.scala:1702:60]
assign hi_565 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_566; // @[Debug.scala:1702:60]
assign hi_566 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_567; // @[Debug.scala:1702:60]
assign hi_567 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_568; // @[Debug.scala:1702:60]
assign hi_568 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_569; // @[Debug.scala:1702:60]
assign hi_569 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_570; // @[Debug.scala:1702:60]
assign hi_570 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_571; // @[Debug.scala:1702:60]
assign hi_571 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_572; // @[Debug.scala:1702:60]
assign hi_572 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_573; // @[Debug.scala:1702:60]
assign hi_573 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_574; // @[Debug.scala:1702:60]
assign hi_574 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_575; // @[Debug.scala:1702:60]
assign hi_575 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_576; // @[Debug.scala:1702:60]
assign hi_576 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_577; // @[Debug.scala:1702:60]
assign hi_577 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_578; // @[Debug.scala:1702:60]
assign hi_578 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_579; // @[Debug.scala:1702:60]
assign hi_579 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_580; // @[Debug.scala:1702:60]
assign hi_580 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_581; // @[Debug.scala:1702:60]
assign hi_581 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_582; // @[Debug.scala:1702:60]
assign hi_582 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_583; // @[Debug.scala:1702:60]
assign hi_583 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_584; // @[Debug.scala:1702:60]
assign hi_584 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_585; // @[Debug.scala:1702:60]
assign hi_585 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_586; // @[Debug.scala:1702:60]
assign hi_586 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_587; // @[Debug.scala:1702:60]
assign hi_587 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_588; // @[Debug.scala:1702:60]
assign hi_588 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_589; // @[Debug.scala:1702:60]
assign hi_589 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_590; // @[Debug.scala:1702:60]
assign hi_590 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_591; // @[Debug.scala:1702:60]
assign hi_591 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_592; // @[Debug.scala:1702:60]
assign hi_592 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_593; // @[Debug.scala:1702:60]
assign hi_593 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_594; // @[Debug.scala:1702:60]
assign hi_594 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_595; // @[Debug.scala:1702:60]
assign hi_595 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_596; // @[Debug.scala:1702:60]
assign hi_596 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_597; // @[Debug.scala:1702:60]
assign hi_597 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_598; // @[Debug.scala:1702:60]
assign hi_598 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_599; // @[Debug.scala:1702:60]
assign hi_599 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_600; // @[Debug.scala:1702:60]
assign hi_600 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_601; // @[Debug.scala:1702:60]
assign hi_601 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_602; // @[Debug.scala:1702:60]
assign hi_602 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_603; // @[Debug.scala:1702:60]
assign hi_603 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_604; // @[Debug.scala:1702:60]
assign hi_604 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_605; // @[Debug.scala:1702:60]
assign hi_605 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_606; // @[Debug.scala:1702:60]
assign hi_606 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_607; // @[Debug.scala:1702:60]
assign hi_607 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_608; // @[Debug.scala:1702:60]
assign hi_608 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_609; // @[Debug.scala:1702:60]
assign hi_609 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_610; // @[Debug.scala:1702:60]
assign hi_610 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_611; // @[Debug.scala:1702:60]
assign hi_611 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_612; // @[Debug.scala:1702:60]
assign hi_612 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_613; // @[Debug.scala:1702:60]
assign hi_613 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_614; // @[Debug.scala:1702:60]
assign hi_614 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_615; // @[Debug.scala:1702:60]
assign hi_615 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_616; // @[Debug.scala:1702:60]
assign hi_616 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_617; // @[Debug.scala:1702:60]
assign hi_617 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_618; // @[Debug.scala:1702:60]
assign hi_618 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_619; // @[Debug.scala:1702:60]
assign hi_619 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_620; // @[Debug.scala:1702:60]
assign hi_620 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_621; // @[Debug.scala:1702:60]
assign hi_621 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_622; // @[Debug.scala:1702:60]
assign hi_622 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_623; // @[Debug.scala:1702:60]
assign hi_623 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_624; // @[Debug.scala:1702:60]
assign hi_624 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_625; // @[Debug.scala:1702:60]
assign hi_625 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_626; // @[Debug.scala:1702:60]
assign hi_626 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_627; // @[Debug.scala:1702:60]
assign hi_627 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_628; // @[Debug.scala:1702:60]
assign hi_628 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_629; // @[Debug.scala:1702:60]
assign hi_629 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_630; // @[Debug.scala:1702:60]
assign hi_630 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_631; // @[Debug.scala:1702:60]
assign hi_631 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_632; // @[Debug.scala:1702:60]
assign hi_632 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_633; // @[Debug.scala:1702:60]
assign hi_633 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_634; // @[Debug.scala:1702:60]
assign hi_634 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_635; // @[Debug.scala:1702:60]
assign hi_635 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_636; // @[Debug.scala:1702:60]
assign hi_636 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_637; // @[Debug.scala:1702:60]
assign hi_637 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_638; // @[Debug.scala:1702:60]
assign hi_638 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_639; // @[Debug.scala:1702:60]
assign hi_639 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_640; // @[Debug.scala:1702:60]
assign hi_640 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_641; // @[Debug.scala:1702:60]
assign hi_641 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_642; // @[Debug.scala:1702:60]
assign hi_642 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_643; // @[Debug.scala:1702:60]
assign hi_643 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_644; // @[Debug.scala:1702:60]
assign hi_644 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_645; // @[Debug.scala:1702:60]
assign hi_645 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_646; // @[Debug.scala:1702:60]
assign hi_646 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_647; // @[Debug.scala:1702:60]
assign hi_647 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_648; // @[Debug.scala:1702:60]
assign hi_648 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_649; // @[Debug.scala:1702:60]
assign hi_649 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_650; // @[Debug.scala:1702:60]
assign hi_650 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_651; // @[Debug.scala:1702:60]
assign hi_651 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_652; // @[Debug.scala:1702:60]
assign hi_652 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_653; // @[Debug.scala:1702:60]
assign hi_653 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_654; // @[Debug.scala:1702:60]
assign hi_654 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_655; // @[Debug.scala:1702:60]
assign hi_655 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_656; // @[Debug.scala:1702:60]
assign hi_656 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_657; // @[Debug.scala:1702:60]
assign hi_657 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_658; // @[Debug.scala:1702:60]
assign hi_658 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_659; // @[Debug.scala:1702:60]
assign hi_659 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_660; // @[Debug.scala:1702:60]
assign hi_660 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_661; // @[Debug.scala:1702:60]
assign hi_661 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_662; // @[Debug.scala:1702:60]
assign hi_662 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_663; // @[Debug.scala:1702:60]
assign hi_663 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_664; // @[Debug.scala:1702:60]
assign hi_664 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_665; // @[Debug.scala:1702:60]
assign hi_665 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_666; // @[Debug.scala:1702:60]
assign hi_666 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_667; // @[Debug.scala:1702:60]
assign hi_667 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_668; // @[Debug.scala:1702:60]
assign hi_668 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_669; // @[Debug.scala:1702:60]
assign hi_669 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_670; // @[Debug.scala:1702:60]
assign hi_670 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_671; // @[Debug.scala:1702:60]
assign hi_671 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_672; // @[Debug.scala:1702:60]
assign hi_672 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_673; // @[Debug.scala:1702:60]
assign hi_673 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_674; // @[Debug.scala:1702:60]
assign hi_674 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_675; // @[Debug.scala:1702:60]
assign hi_675 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_676; // @[Debug.scala:1702:60]
assign hi_676 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_677; // @[Debug.scala:1702:60]
assign hi_677 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_678; // @[Debug.scala:1702:60]
assign hi_678 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_679; // @[Debug.scala:1702:60]
assign hi_679 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_680; // @[Debug.scala:1702:60]
assign hi_680 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_681; // @[Debug.scala:1702:60]
assign hi_681 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_682; // @[Debug.scala:1702:60]
assign hi_682 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_683; // @[Debug.scala:1702:60]
assign hi_683 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_684; // @[Debug.scala:1702:60]
assign hi_684 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_685; // @[Debug.scala:1702:60]
assign hi_685 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_686; // @[Debug.scala:1702:60]
assign hi_686 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_687; // @[Debug.scala:1702:60]
assign hi_687 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_688; // @[Debug.scala:1702:60]
assign hi_688 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_689; // @[Debug.scala:1702:60]
assign hi_689 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_690; // @[Debug.scala:1702:60]
assign hi_690 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_691; // @[Debug.scala:1702:60]
assign hi_691 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_692; // @[Debug.scala:1702:60]
assign hi_692 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_693; // @[Debug.scala:1702:60]
assign hi_693 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_694; // @[Debug.scala:1702:60]
assign hi_694 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_695; // @[Debug.scala:1702:60]
assign hi_695 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_696; // @[Debug.scala:1702:60]
assign hi_696 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_697; // @[Debug.scala:1702:60]
assign hi_697 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_698; // @[Debug.scala:1702:60]
assign hi_698 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_699; // @[Debug.scala:1702:60]
assign hi_699 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_700; // @[Debug.scala:1702:60]
assign hi_700 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_701; // @[Debug.scala:1702:60]
assign hi_701 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_702; // @[Debug.scala:1702:60]
assign hi_702 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_703; // @[Debug.scala:1702:60]
assign hi_703 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_704; // @[Debug.scala:1702:60]
assign hi_704 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_705; // @[Debug.scala:1702:60]
assign hi_705 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_706; // @[Debug.scala:1702:60]
assign hi_706 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_707; // @[Debug.scala:1702:60]
assign hi_707 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_708; // @[Debug.scala:1702:60]
assign hi_708 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_709; // @[Debug.scala:1702:60]
assign hi_709 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_710; // @[Debug.scala:1702:60]
assign hi_710 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_711; // @[Debug.scala:1702:60]
assign hi_711 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_712; // @[Debug.scala:1702:60]
assign hi_712 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_713; // @[Debug.scala:1702:60]
assign hi_713 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_714; // @[Debug.scala:1702:60]
assign hi_714 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_715; // @[Debug.scala:1702:60]
assign hi_715 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_716; // @[Debug.scala:1702:60]
assign hi_716 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_717; // @[Debug.scala:1702:60]
assign hi_717 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_718; // @[Debug.scala:1702:60]
assign hi_718 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_719; // @[Debug.scala:1702:60]
assign hi_719 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_720; // @[Debug.scala:1702:60]
assign hi_720 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_721; // @[Debug.scala:1702:60]
assign hi_721 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_722; // @[Debug.scala:1702:60]
assign hi_722 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_723; // @[Debug.scala:1702:60]
assign hi_723 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_724; // @[Debug.scala:1702:60]
assign hi_724 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_725; // @[Debug.scala:1702:60]
assign hi_725 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_726; // @[Debug.scala:1702:60]
assign hi_726 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_727; // @[Debug.scala:1702:60]
assign hi_727 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_728; // @[Debug.scala:1702:60]
assign hi_728 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_729; // @[Debug.scala:1702:60]
assign hi_729 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_730; // @[Debug.scala:1702:60]
assign hi_730 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_731; // @[Debug.scala:1702:60]
assign hi_731 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_732; // @[Debug.scala:1702:60]
assign hi_732 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_733; // @[Debug.scala:1702:60]
assign hi_733 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_734; // @[Debug.scala:1702:60]
assign hi_734 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_735; // @[Debug.scala:1702:60]
assign hi_735 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_736; // @[Debug.scala:1702:60]
assign hi_736 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_737; // @[Debug.scala:1702:60]
assign hi_737 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_738; // @[Debug.scala:1702:60]
assign hi_738 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_739; // @[Debug.scala:1702:60]
assign hi_739 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_740; // @[Debug.scala:1702:60]
assign hi_740 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_741; // @[Debug.scala:1702:60]
assign hi_741 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_742; // @[Debug.scala:1702:60]
assign hi_742 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_743; // @[Debug.scala:1702:60]
assign hi_743 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_744; // @[Debug.scala:1702:60]
assign hi_744 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_745; // @[Debug.scala:1702:60]
assign hi_745 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_746; // @[Debug.scala:1702:60]
assign hi_746 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_747; // @[Debug.scala:1702:60]
assign hi_747 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_748; // @[Debug.scala:1702:60]
assign hi_748 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_749; // @[Debug.scala:1702:60]
assign hi_749 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_750; // @[Debug.scala:1702:60]
assign hi_750 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_751; // @[Debug.scala:1702:60]
assign hi_751 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_752; // @[Debug.scala:1702:60]
assign hi_752 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_753; // @[Debug.scala:1702:60]
assign hi_753 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_754; // @[Debug.scala:1702:60]
assign hi_754 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_755; // @[Debug.scala:1702:60]
assign hi_755 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_756; // @[Debug.scala:1702:60]
assign hi_756 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_757; // @[Debug.scala:1702:60]
assign hi_757 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_758; // @[Debug.scala:1702:60]
assign hi_758 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_759; // @[Debug.scala:1702:60]
assign hi_759 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_760; // @[Debug.scala:1702:60]
assign hi_760 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_761; // @[Debug.scala:1702:60]
assign hi_761 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_762; // @[Debug.scala:1702:60]
assign hi_762 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_763; // @[Debug.scala:1702:60]
assign hi_763 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_764; // @[Debug.scala:1702:60]
assign hi_764 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_765; // @[Debug.scala:1702:60]
assign hi_765 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_766; // @[Debug.scala:1702:60]
assign hi_766 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_767; // @[Debug.scala:1702:60]
assign hi_767 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_768; // @[Debug.scala:1702:60]
assign hi_768 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_769; // @[Debug.scala:1702:60]
assign hi_769 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_770; // @[Debug.scala:1702:60]
assign hi_770 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_771; // @[Debug.scala:1702:60]
assign hi_771 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_772; // @[Debug.scala:1702:60]
assign hi_772 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_773; // @[Debug.scala:1702:60]
assign hi_773 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_774; // @[Debug.scala:1702:60]
assign hi_774 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_775; // @[Debug.scala:1702:60]
assign hi_775 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_776; // @[Debug.scala:1702:60]
assign hi_776 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_777; // @[Debug.scala:1702:60]
assign hi_777 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_778; // @[Debug.scala:1702:60]
assign hi_778 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_779; // @[Debug.scala:1702:60]
assign hi_779 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_780; // @[Debug.scala:1702:60]
assign hi_780 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_781; // @[Debug.scala:1702:60]
assign hi_781 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_782; // @[Debug.scala:1702:60]
assign hi_782 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_783; // @[Debug.scala:1702:60]
assign hi_783 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_784; // @[Debug.scala:1702:60]
assign hi_784 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_785; // @[Debug.scala:1702:60]
assign hi_785 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_786; // @[Debug.scala:1702:60]
assign hi_786 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_787; // @[Debug.scala:1702:60]
assign hi_787 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_788; // @[Debug.scala:1702:60]
assign hi_788 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_789; // @[Debug.scala:1702:60]
assign hi_789 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_790; // @[Debug.scala:1702:60]
assign hi_790 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_791; // @[Debug.scala:1702:60]
assign hi_791 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_792; // @[Debug.scala:1702:60]
assign hi_792 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_793; // @[Debug.scala:1702:60]
assign hi_793 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_794; // @[Debug.scala:1702:60]
assign hi_794 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_795; // @[Debug.scala:1702:60]
assign hi_795 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_796; // @[Debug.scala:1702:60]
assign hi_796 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_797; // @[Debug.scala:1702:60]
assign hi_797 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_798; // @[Debug.scala:1702:60]
assign hi_798 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_799; // @[Debug.scala:1702:60]
assign hi_799 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_800; // @[Debug.scala:1702:60]
assign hi_800 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_801; // @[Debug.scala:1702:60]
assign hi_801 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_802; // @[Debug.scala:1702:60]
assign hi_802 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_803; // @[Debug.scala:1702:60]
assign hi_803 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_804; // @[Debug.scala:1702:60]
assign hi_804 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_805; // @[Debug.scala:1702:60]
assign hi_805 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_806; // @[Debug.scala:1702:60]
assign hi_806 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_807; // @[Debug.scala:1702:60]
assign hi_807 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_808; // @[Debug.scala:1702:60]
assign hi_808 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_809; // @[Debug.scala:1702:60]
assign hi_809 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_810; // @[Debug.scala:1702:60]
assign hi_810 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_811; // @[Debug.scala:1702:60]
assign hi_811 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_812; // @[Debug.scala:1702:60]
assign hi_812 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_813; // @[Debug.scala:1702:60]
assign hi_813 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_814; // @[Debug.scala:1702:60]
assign hi_814 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_815; // @[Debug.scala:1702:60]
assign hi_815 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_816; // @[Debug.scala:1702:60]
assign hi_816 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_817; // @[Debug.scala:1702:60]
assign hi_817 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_818; // @[Debug.scala:1702:60]
assign hi_818 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_819; // @[Debug.scala:1702:60]
assign hi_819 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_820; // @[Debug.scala:1702:60]
assign hi_820 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_821; // @[Debug.scala:1702:60]
assign hi_821 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_822; // @[Debug.scala:1702:60]
assign hi_822 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_823; // @[Debug.scala:1702:60]
assign hi_823 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_824; // @[Debug.scala:1702:60]
assign hi_824 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_825; // @[Debug.scala:1702:60]
assign hi_825 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_826; // @[Debug.scala:1702:60]
assign hi_826 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_827; // @[Debug.scala:1702:60]
assign hi_827 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_828; // @[Debug.scala:1702:60]
assign hi_828 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_829; // @[Debug.scala:1702:60]
assign hi_829 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_830; // @[Debug.scala:1702:60]
assign hi_830 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_831; // @[Debug.scala:1702:60]
assign hi_831 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_832; // @[Debug.scala:1702:60]
assign hi_832 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_833; // @[Debug.scala:1702:60]
assign hi_833 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_834; // @[Debug.scala:1702:60]
assign hi_834 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_835; // @[Debug.scala:1702:60]
assign hi_835 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_836; // @[Debug.scala:1702:60]
assign hi_836 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_837; // @[Debug.scala:1702:60]
assign hi_837 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_838; // @[Debug.scala:1702:60]
assign hi_838 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_839; // @[Debug.scala:1702:60]
assign hi_839 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_840; // @[Debug.scala:1702:60]
assign hi_840 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_841; // @[Debug.scala:1702:60]
assign hi_841 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_842; // @[Debug.scala:1702:60]
assign hi_842 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_843; // @[Debug.scala:1702:60]
assign hi_843 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_844; // @[Debug.scala:1702:60]
assign hi_844 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_845; // @[Debug.scala:1702:60]
assign hi_845 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_846; // @[Debug.scala:1702:60]
assign hi_846 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_847; // @[Debug.scala:1702:60]
assign hi_847 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_848; // @[Debug.scala:1702:60]
assign hi_848 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_849; // @[Debug.scala:1702:60]
assign hi_849 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_850; // @[Debug.scala:1702:60]
assign hi_850 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_851; // @[Debug.scala:1702:60]
assign hi_851 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_852; // @[Debug.scala:1702:60]
assign hi_852 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_853; // @[Debug.scala:1702:60]
assign hi_853 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_854; // @[Debug.scala:1702:60]
assign hi_854 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_855; // @[Debug.scala:1702:60]
assign hi_855 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_856; // @[Debug.scala:1702:60]
assign hi_856 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_857; // @[Debug.scala:1702:60]
assign hi_857 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_858; // @[Debug.scala:1702:60]
assign hi_858 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_859; // @[Debug.scala:1702:60]
assign hi_859 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_860; // @[Debug.scala:1702:60]
assign hi_860 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_861; // @[Debug.scala:1702:60]
assign hi_861 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_862; // @[Debug.scala:1702:60]
assign hi_862 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_863; // @[Debug.scala:1702:60]
assign hi_863 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_864; // @[Debug.scala:1702:60]
assign hi_864 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_865; // @[Debug.scala:1702:60]
assign hi_865 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_866; // @[Debug.scala:1702:60]
assign hi_866 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_867; // @[Debug.scala:1702:60]
assign hi_867 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_868; // @[Debug.scala:1702:60]
assign hi_868 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_869; // @[Debug.scala:1702:60]
assign hi_869 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_870; // @[Debug.scala:1702:60]
assign hi_870 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_871; // @[Debug.scala:1702:60]
assign hi_871 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_872; // @[Debug.scala:1702:60]
assign hi_872 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_873; // @[Debug.scala:1702:60]
assign hi_873 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_874; // @[Debug.scala:1702:60]
assign hi_874 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_875; // @[Debug.scala:1702:60]
assign hi_875 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_876; // @[Debug.scala:1702:60]
assign hi_876 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_877; // @[Debug.scala:1702:60]
assign hi_877 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_878; // @[Debug.scala:1702:60]
assign hi_878 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_879; // @[Debug.scala:1702:60]
assign hi_879 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_880; // @[Debug.scala:1702:60]
assign hi_880 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_881; // @[Debug.scala:1702:60]
assign hi_881 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_882; // @[Debug.scala:1702:60]
assign hi_882 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_883; // @[Debug.scala:1702:60]
assign hi_883 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_884; // @[Debug.scala:1702:60]
assign hi_884 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_885; // @[Debug.scala:1702:60]
assign hi_885 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_886; // @[Debug.scala:1702:60]
assign hi_886 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_887; // @[Debug.scala:1702:60]
assign hi_887 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_888; // @[Debug.scala:1702:60]
assign hi_888 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_889; // @[Debug.scala:1702:60]
assign hi_889 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_890; // @[Debug.scala:1702:60]
assign hi_890 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_891; // @[Debug.scala:1702:60]
assign hi_891 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_892; // @[Debug.scala:1702:60]
assign hi_892 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_893; // @[Debug.scala:1702:60]
assign hi_893 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_894; // @[Debug.scala:1702:60]
assign hi_894 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_895; // @[Debug.scala:1702:60]
assign hi_895 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_896; // @[Debug.scala:1702:60]
assign hi_896 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_897; // @[Debug.scala:1702:60]
assign hi_897 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_898; // @[Debug.scala:1702:60]
assign hi_898 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_899; // @[Debug.scala:1702:60]
assign hi_899 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_900; // @[Debug.scala:1702:60]
assign hi_900 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_901; // @[Debug.scala:1702:60]
assign hi_901 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_902; // @[Debug.scala:1702:60]
assign hi_902 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_903; // @[Debug.scala:1702:60]
assign hi_903 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_904; // @[Debug.scala:1702:60]
assign hi_904 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_905; // @[Debug.scala:1702:60]
assign hi_905 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_906; // @[Debug.scala:1702:60]
assign hi_906 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_907; // @[Debug.scala:1702:60]
assign hi_907 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_908; // @[Debug.scala:1702:60]
assign hi_908 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_909; // @[Debug.scala:1702:60]
assign hi_909 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_910; // @[Debug.scala:1702:60]
assign hi_910 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_911; // @[Debug.scala:1702:60]
assign hi_911 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_912; // @[Debug.scala:1702:60]
assign hi_912 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_913; // @[Debug.scala:1702:60]
assign hi_913 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_914; // @[Debug.scala:1702:60]
assign hi_914 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_915; // @[Debug.scala:1702:60]
assign hi_915 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_916; // @[Debug.scala:1702:60]
assign hi_916 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_917; // @[Debug.scala:1702:60]
assign hi_917 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_918; // @[Debug.scala:1702:60]
assign hi_918 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_919; // @[Debug.scala:1702:60]
assign hi_919 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_920; // @[Debug.scala:1702:60]
assign hi_920 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_921; // @[Debug.scala:1702:60]
assign hi_921 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_922; // @[Debug.scala:1702:60]
assign hi_922 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_923; // @[Debug.scala:1702:60]
assign hi_923 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_924; // @[Debug.scala:1702:60]
assign hi_924 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_925; // @[Debug.scala:1702:60]
assign hi_925 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_926; // @[Debug.scala:1702:60]
assign hi_926 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_927; // @[Debug.scala:1702:60]
assign hi_927 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_928; // @[Debug.scala:1702:60]
assign hi_928 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_929; // @[Debug.scala:1702:60]
assign hi_929 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_930; // @[Debug.scala:1702:60]
assign hi_930 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_931; // @[Debug.scala:1702:60]
assign hi_931 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_932; // @[Debug.scala:1702:60]
assign hi_932 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_933; // @[Debug.scala:1702:60]
assign hi_933 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_934; // @[Debug.scala:1702:60]
assign hi_934 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_935; // @[Debug.scala:1702:60]
assign hi_935 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_936; // @[Debug.scala:1702:60]
assign hi_936 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_937; // @[Debug.scala:1702:60]
assign hi_937 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_938; // @[Debug.scala:1702:60]
assign hi_938 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_939; // @[Debug.scala:1702:60]
assign hi_939 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_940; // @[Debug.scala:1702:60]
assign hi_940 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_941; // @[Debug.scala:1702:60]
assign hi_941 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_942; // @[Debug.scala:1702:60]
assign hi_942 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_943; // @[Debug.scala:1702:60]
assign hi_943 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_944; // @[Debug.scala:1702:60]
assign hi_944 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_945; // @[Debug.scala:1702:60]
assign hi_945 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_946; // @[Debug.scala:1702:60]
assign hi_946 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_947; // @[Debug.scala:1702:60]
assign hi_947 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_948; // @[Debug.scala:1702:60]
assign hi_948 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_949; // @[Debug.scala:1702:60]
assign hi_949 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_950; // @[Debug.scala:1702:60]
assign hi_950 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_951; // @[Debug.scala:1702:60]
assign hi_951 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_952; // @[Debug.scala:1702:60]
assign hi_952 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_953; // @[Debug.scala:1702:60]
assign hi_953 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_954; // @[Debug.scala:1702:60]
assign hi_954 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_955; // @[Debug.scala:1702:60]
assign hi_955 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_956; // @[Debug.scala:1702:60]
assign hi_956 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_957; // @[Debug.scala:1702:60]
assign hi_957 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_958; // @[Debug.scala:1702:60]
assign hi_958 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_959; // @[Debug.scala:1702:60]
assign hi_959 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_960; // @[Debug.scala:1702:60]
assign hi_960 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_961; // @[Debug.scala:1702:60]
assign hi_961 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_962; // @[Debug.scala:1702:60]
assign hi_962 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_963; // @[Debug.scala:1702:60]
assign hi_963 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_964; // @[Debug.scala:1702:60]
assign hi_964 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_965; // @[Debug.scala:1702:60]
assign hi_965 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_966; // @[Debug.scala:1702:60]
assign hi_966 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_967; // @[Debug.scala:1702:60]
assign hi_967 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_968; // @[Debug.scala:1702:60]
assign hi_968 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_969; // @[Debug.scala:1702:60]
assign hi_969 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_970; // @[Debug.scala:1702:60]
assign hi_970 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_971; // @[Debug.scala:1702:60]
assign hi_971 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_972; // @[Debug.scala:1702:60]
assign hi_972 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_973; // @[Debug.scala:1702:60]
assign hi_973 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_974; // @[Debug.scala:1702:60]
assign hi_974 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_975; // @[Debug.scala:1702:60]
assign hi_975 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_976; // @[Debug.scala:1702:60]
assign hi_976 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_977; // @[Debug.scala:1702:60]
assign hi_977 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_978; // @[Debug.scala:1702:60]
assign hi_978 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_979; // @[Debug.scala:1702:60]
assign hi_979 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_980; // @[Debug.scala:1702:60]
assign hi_980 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_981; // @[Debug.scala:1702:60]
assign hi_981 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_982; // @[Debug.scala:1702:60]
assign hi_982 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_983; // @[Debug.scala:1702:60]
assign hi_983 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_984; // @[Debug.scala:1702:60]
assign hi_984 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_985; // @[Debug.scala:1702:60]
assign hi_985 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_986; // @[Debug.scala:1702:60]
assign hi_986 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_987; // @[Debug.scala:1702:60]
assign hi_987 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_988; // @[Debug.scala:1702:60]
assign hi_988 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_989; // @[Debug.scala:1702:60]
assign hi_989 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_990; // @[Debug.scala:1702:60]
assign hi_990 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_991; // @[Debug.scala:1702:60]
assign hi_991 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_992; // @[Debug.scala:1702:60]
assign hi_992 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_993; // @[Debug.scala:1702:60]
assign hi_993 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_994; // @[Debug.scala:1702:60]
assign hi_994 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_995; // @[Debug.scala:1702:60]
assign hi_995 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_996; // @[Debug.scala:1702:60]
assign hi_996 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_997; // @[Debug.scala:1702:60]
assign hi_997 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_998; // @[Debug.scala:1702:60]
assign hi_998 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_999; // @[Debug.scala:1702:60]
assign hi_999 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_1000; // @[Debug.scala:1702:60]
assign hi_1000 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_1001; // @[Debug.scala:1702:60]
assign hi_1001 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_1002; // @[Debug.scala:1702:60]
assign hi_1002 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_1003; // @[Debug.scala:1702:60]
assign hi_1003 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_1004; // @[Debug.scala:1702:60]
assign hi_1004 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_1005; // @[Debug.scala:1702:60]
assign hi_1005 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_1006; // @[Debug.scala:1702:60]
assign hi_1006 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_1007; // @[Debug.scala:1702:60]
assign hi_1007 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_1008; // @[Debug.scala:1702:60]
assign hi_1008 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_1009; // @[Debug.scala:1702:60]
assign hi_1009 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_1010; // @[Debug.scala:1702:60]
assign hi_1010 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_1011; // @[Debug.scala:1702:60]
assign hi_1011 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_1012; // @[Debug.scala:1702:60]
assign hi_1012 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_1013; // @[Debug.scala:1702:60]
assign hi_1013 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_1014; // @[Debug.scala:1702:60]
assign hi_1014 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_1015; // @[Debug.scala:1702:60]
assign hi_1015 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_1016; // @[Debug.scala:1702:60]
assign hi_1016 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_1017; // @[Debug.scala:1702:60]
assign hi_1017 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_1018; // @[Debug.scala:1702:60]
assign hi_1018 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_1019; // @[Debug.scala:1702:60]
assign hi_1019 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_1020; // @[Debug.scala:1702:60]
assign hi_1020 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_1021; // @[Debug.scala:1702:60]
assign hi_1021 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_1022; // @[Debug.scala:1702:60]
assign hi_1022 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_1023; // @[Debug.scala:1702:60]
assign hi_1023 = _GEN_16; // @[Debug.scala:1702:60]
wire [6:0] hi_1024; // @[Debug.scala:1702:60]
assign hi_1024 = _GEN_16; // @[Debug.scala:1702:60]
wire [7:0] _out_T_6436 = {hi_1, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6184 = {hi_9, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8824 = {hi_17, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12272 = {hi_25, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4125 = {hi_33, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4197 = {hi_41, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6256 = {hi_49, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8968 = {hi_57, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11984 = {hi_65, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4989 = {hi_73, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1917 = {hi_81, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11032 = {hi_89, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8304 = {hi_97, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5655 = {hi_105, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2509 = {hi_113, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10208 = {hi_121, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7478 = {hi_129, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9632 = {hi_137, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11464 = {hi_145, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3981 = {hi_153, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6830 = {hi_161, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7118 = {hi_169, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9704 = {hi_177, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11392 = {hi_185, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3245 = {hi_193, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2581 = {hi_201, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10064 = {hi_209, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8448 = {hi_217, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5439 = {hi_225, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3101 = {hi_233, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10728 = {hi_241, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7694 = {hi_249, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4845 = {hi_257, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6974 = {hi_265, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9256 = {hi_273, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12416 = {hi_281, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3533 = {hi_289, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5061 = {hi_297, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6740 = {hi_305, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9184 = {hi_313, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11680 = {hi_321, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5583 = {hi_329, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2133 = {hi_337, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10960 = {hi_345, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7838 = {hi_353, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6112 = {hi_361, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2653 = {hi_369, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10136 = {hi_377, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7190 = {hi_385, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9920 = {hi_393, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12344 = {hi_401, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3605 = {hi_409, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7046 = {hi_417, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7622 = {hi_425, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9992 = {hi_433, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11608 = {hi_441, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2869 = {hi_449, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2725 = {hi_457, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10800 = {hi_465, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7766 = {hi_473, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5511 = {hi_481, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3173 = {hi_489, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11536 = {hi_497, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7262 = {hi_505, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4917 = {hi_513, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5799 = {hi_521, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9560 = {hi_529, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12056 = {hi_537, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3029 = {hi_545, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5295 = {hi_553, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8520 = {hi_561, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9848 = {hi_569, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12488 = {hi_577, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4629 = {hi_585, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2437 = {hi_593, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10280 = {hi_601, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7334 = {hi_609, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6364 = {hi_617, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4413 = {hi_625, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11104 = {hi_633, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8214 = {hi_641, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9400 = {hi_649, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11824 = {hi_657, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3837 = {hi_665, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5871 = {hi_673, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8376 = {hi_681, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11176 = {hi_689, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12648 = {hi_697, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3461 = {hi_705, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2293 = {hi_713, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10352 = {hi_721, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7998 = {hi_729, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4701 = {hi_737, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4053 = {hi_745, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12720 = {hi_753, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8896 = {hi_761, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5367 = {hi_769, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5727 = {hi_777, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9040 = {hi_785, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12936 = {hi_793, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3317 = {hi_801, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5151 = {hi_809, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8070 = {hi_817, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10584 = {hi_825, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12792 = {hi_833, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4485 = {hi_841, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2061 = {hi_849, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11248 = {hi_857, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7550 = {hi_865, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6508 = {hi_873, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3765 = {hi_881, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12128 = {hi_889, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8680 = {hi_897, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9112 = {hi_905, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12200 = {hi_913, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4269 = {hi_921, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6668 = {hi_929, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8142 = {hi_937, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11320 = {hi_945, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2365 = {hi_953, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4557 = {hi_961, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1989 = {hi_969, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10512 = {hi_977, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8752 = {hi_985, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5223 = {hi_993, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3909 = {hi_1001, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12864 = {hi_1009, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9328 = {hi_1017, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire _out_in_ready_T_1; // @[RegisterRouter.scala:87:24]
assign tlNodeIn_a_ready = in_1_ready; // @[RegisterRouter.scala:73:18]
wire _in_bits_read_T_1; // @[RegisterRouter.scala:74:36]
wire _out_front_valid_T_1 = in_1_valid; // @[RegisterRouter.scala:73:18, :87:24]
wire [8:0] _in_bits_index_T_1; // @[Edges.scala:192:34]
wire out_front_1_bits_read = in_1_bits_read; // @[RegisterRouter.scala:73:18, :87:24]
wire [8:0] out_front_1_bits_index = in_1_bits_index; // @[RegisterRouter.scala:73:18, :87:24]
wire [63:0] out_front_1_bits_data = in_1_bits_data; // @[RegisterRouter.scala:73:18, :87:24]
wire [7:0] out_front_1_bits_mask = in_1_bits_mask; // @[RegisterRouter.scala:73:18, :87:24]
wire [10:0] out_front_1_bits_extra_tlrr_extra_source = in_1_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:73:18, :87:24]
wire [1:0] out_front_1_bits_extra_tlrr_extra_size = in_1_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:73:18, :87:24]
assign _in_bits_read_T_1 = tlNodeIn_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36]
assign in_1_bits_read = _in_bits_read_T_1; // @[RegisterRouter.scala:73:18, :74:36]
assign _in_bits_index_T_1 = tlNodeIn_a_bits_address[11:3]; // @[Edges.scala:192:34]
assign in_1_bits_index = _in_bits_index_T_1; // @[RegisterRouter.scala:73:18]
wire _out_front_ready_T_1 = out_1_ready; // @[RegisterRouter.scala:87:24]
wire _out_out_valid_T_1; // @[RegisterRouter.scala:87:24]
assign tlNodeIn_d_valid = out_1_valid; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_T_9; // @[RegisterRouter.scala:87:24]
wire _tlNodeIn_d_bits_opcode_T = out_1_bits_read; // @[RegisterRouter.scala:87:24, :105:25]
assign tlNodeIn_d_bits_data = out_1_bits_data; // @[RegisterRouter.scala:87:24]
assign tlNodeIn_d_bits_d_source = out_1_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24]
wire [1:0] out_1_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24]
assign tlNodeIn_d_bits_d_size = out_1_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24]
assign _out_in_ready_T_1 = out_front_1_ready; // @[RegisterRouter.scala:87:24]
assign _out_out_valid_T_1 = out_front_1_valid; // @[RegisterRouter.scala:87:24]
assign out_1_bits_read = out_front_1_bits_read; // @[RegisterRouter.scala:87:24]
assign out_1_bits_extra_tlrr_extra_source = out_front_1_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24]
assign out_1_bits_extra_tlrr_extra_size = out_front_1_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24]
wire [8:0] _GEN_17 = out_front_1_bits_index & 9'h100; // @[RegisterRouter.scala:87:24]
wire [8:0] out_findex_1; // @[RegisterRouter.scala:87:24]
assign out_findex_1 = _GEN_17; // @[RegisterRouter.scala:87:24]
wire [8:0] out_bindex_1; // @[RegisterRouter.scala:87:24]
assign out_bindex_1 = _GEN_17; // @[RegisterRouter.scala:87:24]
wire _GEN_18 = out_findex_1 == 9'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_1600; // @[RegisterRouter.scala:87:24]
assign _out_T_1600 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1602; // @[RegisterRouter.scala:87:24]
assign _out_T_1602 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1604; // @[RegisterRouter.scala:87:24]
assign _out_T_1604 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1606; // @[RegisterRouter.scala:87:24]
assign _out_T_1606 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1608; // @[RegisterRouter.scala:87:24]
assign _out_T_1608 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1610; // @[RegisterRouter.scala:87:24]
assign _out_T_1610 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1612; // @[RegisterRouter.scala:87:24]
assign _out_T_1612 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1614; // @[RegisterRouter.scala:87:24]
assign _out_T_1614 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1616; // @[RegisterRouter.scala:87:24]
assign _out_T_1616 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1618; // @[RegisterRouter.scala:87:24]
assign _out_T_1618 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1620; // @[RegisterRouter.scala:87:24]
assign _out_T_1620 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1622; // @[RegisterRouter.scala:87:24]
assign _out_T_1622 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1626; // @[RegisterRouter.scala:87:24]
assign _out_T_1626 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1628; // @[RegisterRouter.scala:87:24]
assign _out_T_1628 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1630; // @[RegisterRouter.scala:87:24]
assign _out_T_1630 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1632; // @[RegisterRouter.scala:87:24]
assign _out_T_1632 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1634; // @[RegisterRouter.scala:87:24]
assign _out_T_1634 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1636; // @[RegisterRouter.scala:87:24]
assign _out_T_1636 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1638; // @[RegisterRouter.scala:87:24]
assign _out_T_1638 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1642; // @[RegisterRouter.scala:87:24]
assign _out_T_1642 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1644; // @[RegisterRouter.scala:87:24]
assign _out_T_1644 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1646; // @[RegisterRouter.scala:87:24]
assign _out_T_1646 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1648; // @[RegisterRouter.scala:87:24]
assign _out_T_1648 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1650; // @[RegisterRouter.scala:87:24]
assign _out_T_1650 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1652; // @[RegisterRouter.scala:87:24]
assign _out_T_1652 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1654; // @[RegisterRouter.scala:87:24]
assign _out_T_1654 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1656; // @[RegisterRouter.scala:87:24]
assign _out_T_1656 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1658; // @[RegisterRouter.scala:87:24]
assign _out_T_1658 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1660; // @[RegisterRouter.scala:87:24]
assign _out_T_1660 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1662; // @[RegisterRouter.scala:87:24]
assign _out_T_1662 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1664; // @[RegisterRouter.scala:87:24]
assign _out_T_1664 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1668; // @[RegisterRouter.scala:87:24]
assign _out_T_1668 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1670; // @[RegisterRouter.scala:87:24]
assign _out_T_1670 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1672; // @[RegisterRouter.scala:87:24]
assign _out_T_1672 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1674; // @[RegisterRouter.scala:87:24]
assign _out_T_1674 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1676; // @[RegisterRouter.scala:87:24]
assign _out_T_1676 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1680; // @[RegisterRouter.scala:87:24]
assign _out_T_1680 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1682; // @[RegisterRouter.scala:87:24]
assign _out_T_1682 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1684; // @[RegisterRouter.scala:87:24]
assign _out_T_1684 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1686; // @[RegisterRouter.scala:87:24]
assign _out_T_1686 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1688; // @[RegisterRouter.scala:87:24]
assign _out_T_1688 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1690; // @[RegisterRouter.scala:87:24]
assign _out_T_1690 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1692; // @[RegisterRouter.scala:87:24]
assign _out_T_1692 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1694; // @[RegisterRouter.scala:87:24]
assign _out_T_1694 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1696; // @[RegisterRouter.scala:87:24]
assign _out_T_1696 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1698; // @[RegisterRouter.scala:87:24]
assign _out_T_1698 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1700; // @[RegisterRouter.scala:87:24]
assign _out_T_1700 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1702; // @[RegisterRouter.scala:87:24]
assign _out_T_1702 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1704; // @[RegisterRouter.scala:87:24]
assign _out_T_1704 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1706; // @[RegisterRouter.scala:87:24]
assign _out_T_1706 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1708; // @[RegisterRouter.scala:87:24]
assign _out_T_1708 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1710; // @[RegisterRouter.scala:87:24]
assign _out_T_1710 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1712; // @[RegisterRouter.scala:87:24]
assign _out_T_1712 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1714; // @[RegisterRouter.scala:87:24]
assign _out_T_1714 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1718; // @[RegisterRouter.scala:87:24]
assign _out_T_1718 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1720; // @[RegisterRouter.scala:87:24]
assign _out_T_1720 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1722; // @[RegisterRouter.scala:87:24]
assign _out_T_1722 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1726; // @[RegisterRouter.scala:87:24]
assign _out_T_1726 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1728; // @[RegisterRouter.scala:87:24]
assign _out_T_1728 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1730; // @[RegisterRouter.scala:87:24]
assign _out_T_1730 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1732; // @[RegisterRouter.scala:87:24]
assign _out_T_1732 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1734; // @[RegisterRouter.scala:87:24]
assign _out_T_1734 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1736; // @[RegisterRouter.scala:87:24]
assign _out_T_1736 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1738; // @[RegisterRouter.scala:87:24]
assign _out_T_1738 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1740; // @[RegisterRouter.scala:87:24]
assign _out_T_1740 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1744; // @[RegisterRouter.scala:87:24]
assign _out_T_1744 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1746; // @[RegisterRouter.scala:87:24]
assign _out_T_1746 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1748; // @[RegisterRouter.scala:87:24]
assign _out_T_1748 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1750; // @[RegisterRouter.scala:87:24]
assign _out_T_1750 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1752; // @[RegisterRouter.scala:87:24]
assign _out_T_1752 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1754; // @[RegisterRouter.scala:87:24]
assign _out_T_1754 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1758; // @[RegisterRouter.scala:87:24]
assign _out_T_1758 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1760; // @[RegisterRouter.scala:87:24]
assign _out_T_1760 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1762; // @[RegisterRouter.scala:87:24]
assign _out_T_1762 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1764; // @[RegisterRouter.scala:87:24]
assign _out_T_1764 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1766; // @[RegisterRouter.scala:87:24]
assign _out_T_1766 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1768; // @[RegisterRouter.scala:87:24]
assign _out_T_1768 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1770; // @[RegisterRouter.scala:87:24]
assign _out_T_1770 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1772; // @[RegisterRouter.scala:87:24]
assign _out_T_1772 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1774; // @[RegisterRouter.scala:87:24]
assign _out_T_1774 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1776; // @[RegisterRouter.scala:87:24]
assign _out_T_1776 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1778; // @[RegisterRouter.scala:87:24]
assign _out_T_1778 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1780; // @[RegisterRouter.scala:87:24]
assign _out_T_1780 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1782; // @[RegisterRouter.scala:87:24]
assign _out_T_1782 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1784; // @[RegisterRouter.scala:87:24]
assign _out_T_1784 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1786; // @[RegisterRouter.scala:87:24]
assign _out_T_1786 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1788; // @[RegisterRouter.scala:87:24]
assign _out_T_1788 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1790; // @[RegisterRouter.scala:87:24]
assign _out_T_1790 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1792; // @[RegisterRouter.scala:87:24]
assign _out_T_1792 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1794; // @[RegisterRouter.scala:87:24]
assign _out_T_1794 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1796; // @[RegisterRouter.scala:87:24]
assign _out_T_1796 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1798; // @[RegisterRouter.scala:87:24]
assign _out_T_1798 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1800; // @[RegisterRouter.scala:87:24]
assign _out_T_1800 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1802; // @[RegisterRouter.scala:87:24]
assign _out_T_1802 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1804; // @[RegisterRouter.scala:87:24]
assign _out_T_1804 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1806; // @[RegisterRouter.scala:87:24]
assign _out_T_1806 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1808; // @[RegisterRouter.scala:87:24]
assign _out_T_1808 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1810; // @[RegisterRouter.scala:87:24]
assign _out_T_1810 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1812; // @[RegisterRouter.scala:87:24]
assign _out_T_1812 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1814; // @[RegisterRouter.scala:87:24]
assign _out_T_1814 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1816; // @[RegisterRouter.scala:87:24]
assign _out_T_1816 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1818; // @[RegisterRouter.scala:87:24]
assign _out_T_1818 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1820; // @[RegisterRouter.scala:87:24]
assign _out_T_1820 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1824; // @[RegisterRouter.scala:87:24]
assign _out_T_1824 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1826; // @[RegisterRouter.scala:87:24]
assign _out_T_1826 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1828; // @[RegisterRouter.scala:87:24]
assign _out_T_1828 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1830; // @[RegisterRouter.scala:87:24]
assign _out_T_1830 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1832; // @[RegisterRouter.scala:87:24]
assign _out_T_1832 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1834; // @[RegisterRouter.scala:87:24]
assign _out_T_1834 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1836; // @[RegisterRouter.scala:87:24]
assign _out_T_1836 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1838; // @[RegisterRouter.scala:87:24]
assign _out_T_1838 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1840; // @[RegisterRouter.scala:87:24]
assign _out_T_1840 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1842; // @[RegisterRouter.scala:87:24]
assign _out_T_1842 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1844; // @[RegisterRouter.scala:87:24]
assign _out_T_1844 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1848; // @[RegisterRouter.scala:87:24]
assign _out_T_1848 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1850; // @[RegisterRouter.scala:87:24]
assign _out_T_1850 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1852; // @[RegisterRouter.scala:87:24]
assign _out_T_1852 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1854; // @[RegisterRouter.scala:87:24]
assign _out_T_1854 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1856; // @[RegisterRouter.scala:87:24]
assign _out_T_1856 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1858; // @[RegisterRouter.scala:87:24]
assign _out_T_1858 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1860; // @[RegisterRouter.scala:87:24]
assign _out_T_1860 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1862; // @[RegisterRouter.scala:87:24]
assign _out_T_1862 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1864; // @[RegisterRouter.scala:87:24]
assign _out_T_1864 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1866; // @[RegisterRouter.scala:87:24]
assign _out_T_1866 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1868; // @[RegisterRouter.scala:87:24]
assign _out_T_1868 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1870; // @[RegisterRouter.scala:87:24]
assign _out_T_1870 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1872; // @[RegisterRouter.scala:87:24]
assign _out_T_1872 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1874; // @[RegisterRouter.scala:87:24]
assign _out_T_1874 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1878; // @[RegisterRouter.scala:87:24]
assign _out_T_1878 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1880; // @[RegisterRouter.scala:87:24]
assign _out_T_1880 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1882; // @[RegisterRouter.scala:87:24]
assign _out_T_1882 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1884; // @[RegisterRouter.scala:87:24]
assign _out_T_1884 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1886; // @[RegisterRouter.scala:87:24]
assign _out_T_1886 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1888; // @[RegisterRouter.scala:87:24]
assign _out_T_1888 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1890; // @[RegisterRouter.scala:87:24]
assign _out_T_1890 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1892; // @[RegisterRouter.scala:87:24]
assign _out_T_1892 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1894; // @[RegisterRouter.scala:87:24]
assign _out_T_1894 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1896; // @[RegisterRouter.scala:87:24]
assign _out_T_1896 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1898; // @[RegisterRouter.scala:87:24]
assign _out_T_1898 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1900; // @[RegisterRouter.scala:87:24]
assign _out_T_1900 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1902; // @[RegisterRouter.scala:87:24]
assign _out_T_1902 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1904; // @[RegisterRouter.scala:87:24]
assign _out_T_1904 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1906; // @[RegisterRouter.scala:87:24]
assign _out_T_1906 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1908; // @[RegisterRouter.scala:87:24]
assign _out_T_1908 = _GEN_18; // @[RegisterRouter.scala:87:24]
wire _GEN_19 = out_bindex_1 == 9'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_1601; // @[RegisterRouter.scala:87:24]
assign _out_T_1601 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1603; // @[RegisterRouter.scala:87:24]
assign _out_T_1603 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1605; // @[RegisterRouter.scala:87:24]
assign _out_T_1605 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1607; // @[RegisterRouter.scala:87:24]
assign _out_T_1607 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1609; // @[RegisterRouter.scala:87:24]
assign _out_T_1609 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1611; // @[RegisterRouter.scala:87:24]
assign _out_T_1611 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1613; // @[RegisterRouter.scala:87:24]
assign _out_T_1613 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1615; // @[RegisterRouter.scala:87:24]
assign _out_T_1615 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1617; // @[RegisterRouter.scala:87:24]
assign _out_T_1617 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1619; // @[RegisterRouter.scala:87:24]
assign _out_T_1619 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1621; // @[RegisterRouter.scala:87:24]
assign _out_T_1621 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1623; // @[RegisterRouter.scala:87:24]
assign _out_T_1623 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1627; // @[RegisterRouter.scala:87:24]
assign _out_T_1627 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1629; // @[RegisterRouter.scala:87:24]
assign _out_T_1629 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1631; // @[RegisterRouter.scala:87:24]
assign _out_T_1631 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1633; // @[RegisterRouter.scala:87:24]
assign _out_T_1633 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1635; // @[RegisterRouter.scala:87:24]
assign _out_T_1635 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1637; // @[RegisterRouter.scala:87:24]
assign _out_T_1637 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1639; // @[RegisterRouter.scala:87:24]
assign _out_T_1639 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1643; // @[RegisterRouter.scala:87:24]
assign _out_T_1643 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1645; // @[RegisterRouter.scala:87:24]
assign _out_T_1645 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1647; // @[RegisterRouter.scala:87:24]
assign _out_T_1647 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1649; // @[RegisterRouter.scala:87:24]
assign _out_T_1649 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1651; // @[RegisterRouter.scala:87:24]
assign _out_T_1651 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1653; // @[RegisterRouter.scala:87:24]
assign _out_T_1653 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1655; // @[RegisterRouter.scala:87:24]
assign _out_T_1655 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1657; // @[RegisterRouter.scala:87:24]
assign _out_T_1657 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1659; // @[RegisterRouter.scala:87:24]
assign _out_T_1659 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1661; // @[RegisterRouter.scala:87:24]
assign _out_T_1661 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1663; // @[RegisterRouter.scala:87:24]
assign _out_T_1663 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1665; // @[RegisterRouter.scala:87:24]
assign _out_T_1665 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1669; // @[RegisterRouter.scala:87:24]
assign _out_T_1669 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1671; // @[RegisterRouter.scala:87:24]
assign _out_T_1671 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1673; // @[RegisterRouter.scala:87:24]
assign _out_T_1673 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1675; // @[RegisterRouter.scala:87:24]
assign _out_T_1675 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1677; // @[RegisterRouter.scala:87:24]
assign _out_T_1677 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1681; // @[RegisterRouter.scala:87:24]
assign _out_T_1681 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1683; // @[RegisterRouter.scala:87:24]
assign _out_T_1683 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1685; // @[RegisterRouter.scala:87:24]
assign _out_T_1685 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1687; // @[RegisterRouter.scala:87:24]
assign _out_T_1687 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1689; // @[RegisterRouter.scala:87:24]
assign _out_T_1689 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1691; // @[RegisterRouter.scala:87:24]
assign _out_T_1691 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1693; // @[RegisterRouter.scala:87:24]
assign _out_T_1693 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1695; // @[RegisterRouter.scala:87:24]
assign _out_T_1695 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1697; // @[RegisterRouter.scala:87:24]
assign _out_T_1697 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1699; // @[RegisterRouter.scala:87:24]
assign _out_T_1699 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1701; // @[RegisterRouter.scala:87:24]
assign _out_T_1701 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1703; // @[RegisterRouter.scala:87:24]
assign _out_T_1703 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1705; // @[RegisterRouter.scala:87:24]
assign _out_T_1705 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1707; // @[RegisterRouter.scala:87:24]
assign _out_T_1707 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1709; // @[RegisterRouter.scala:87:24]
assign _out_T_1709 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1711; // @[RegisterRouter.scala:87:24]
assign _out_T_1711 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1713; // @[RegisterRouter.scala:87:24]
assign _out_T_1713 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1715; // @[RegisterRouter.scala:87:24]
assign _out_T_1715 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1719; // @[RegisterRouter.scala:87:24]
assign _out_T_1719 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1721; // @[RegisterRouter.scala:87:24]
assign _out_T_1721 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1723; // @[RegisterRouter.scala:87:24]
assign _out_T_1723 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1727; // @[RegisterRouter.scala:87:24]
assign _out_T_1727 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1729; // @[RegisterRouter.scala:87:24]
assign _out_T_1729 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1731; // @[RegisterRouter.scala:87:24]
assign _out_T_1731 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1733; // @[RegisterRouter.scala:87:24]
assign _out_T_1733 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1735; // @[RegisterRouter.scala:87:24]
assign _out_T_1735 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1737; // @[RegisterRouter.scala:87:24]
assign _out_T_1737 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1739; // @[RegisterRouter.scala:87:24]
assign _out_T_1739 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1741; // @[RegisterRouter.scala:87:24]
assign _out_T_1741 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1745; // @[RegisterRouter.scala:87:24]
assign _out_T_1745 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1747; // @[RegisterRouter.scala:87:24]
assign _out_T_1747 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1749; // @[RegisterRouter.scala:87:24]
assign _out_T_1749 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1751; // @[RegisterRouter.scala:87:24]
assign _out_T_1751 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1753; // @[RegisterRouter.scala:87:24]
assign _out_T_1753 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1755; // @[RegisterRouter.scala:87:24]
assign _out_T_1755 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1759; // @[RegisterRouter.scala:87:24]
assign _out_T_1759 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1761; // @[RegisterRouter.scala:87:24]
assign _out_T_1761 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1763; // @[RegisterRouter.scala:87:24]
assign _out_T_1763 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1765; // @[RegisterRouter.scala:87:24]
assign _out_T_1765 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1767; // @[RegisterRouter.scala:87:24]
assign _out_T_1767 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1769; // @[RegisterRouter.scala:87:24]
assign _out_T_1769 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1771; // @[RegisterRouter.scala:87:24]
assign _out_T_1771 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1773; // @[RegisterRouter.scala:87:24]
assign _out_T_1773 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1775; // @[RegisterRouter.scala:87:24]
assign _out_T_1775 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1777; // @[RegisterRouter.scala:87:24]
assign _out_T_1777 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1779; // @[RegisterRouter.scala:87:24]
assign _out_T_1779 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1781; // @[RegisterRouter.scala:87:24]
assign _out_T_1781 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1783; // @[RegisterRouter.scala:87:24]
assign _out_T_1783 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1785; // @[RegisterRouter.scala:87:24]
assign _out_T_1785 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1787; // @[RegisterRouter.scala:87:24]
assign _out_T_1787 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1789; // @[RegisterRouter.scala:87:24]
assign _out_T_1789 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1791; // @[RegisterRouter.scala:87:24]
assign _out_T_1791 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1793; // @[RegisterRouter.scala:87:24]
assign _out_T_1793 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1795; // @[RegisterRouter.scala:87:24]
assign _out_T_1795 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1797; // @[RegisterRouter.scala:87:24]
assign _out_T_1797 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1799; // @[RegisterRouter.scala:87:24]
assign _out_T_1799 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1801; // @[RegisterRouter.scala:87:24]
assign _out_T_1801 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1803; // @[RegisterRouter.scala:87:24]
assign _out_T_1803 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1805; // @[RegisterRouter.scala:87:24]
assign _out_T_1805 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1807; // @[RegisterRouter.scala:87:24]
assign _out_T_1807 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1809; // @[RegisterRouter.scala:87:24]
assign _out_T_1809 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1811; // @[RegisterRouter.scala:87:24]
assign _out_T_1811 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1813; // @[RegisterRouter.scala:87:24]
assign _out_T_1813 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1815; // @[RegisterRouter.scala:87:24]
assign _out_T_1815 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1817; // @[RegisterRouter.scala:87:24]
assign _out_T_1817 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1819; // @[RegisterRouter.scala:87:24]
assign _out_T_1819 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1821; // @[RegisterRouter.scala:87:24]
assign _out_T_1821 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1825; // @[RegisterRouter.scala:87:24]
assign _out_T_1825 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1827; // @[RegisterRouter.scala:87:24]
assign _out_T_1827 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1829; // @[RegisterRouter.scala:87:24]
assign _out_T_1829 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1831; // @[RegisterRouter.scala:87:24]
assign _out_T_1831 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1833; // @[RegisterRouter.scala:87:24]
assign _out_T_1833 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1835; // @[RegisterRouter.scala:87:24]
assign _out_T_1835 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1837; // @[RegisterRouter.scala:87:24]
assign _out_T_1837 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1839; // @[RegisterRouter.scala:87:24]
assign _out_T_1839 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1841; // @[RegisterRouter.scala:87:24]
assign _out_T_1841 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1843; // @[RegisterRouter.scala:87:24]
assign _out_T_1843 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1845; // @[RegisterRouter.scala:87:24]
assign _out_T_1845 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1849; // @[RegisterRouter.scala:87:24]
assign _out_T_1849 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1851; // @[RegisterRouter.scala:87:24]
assign _out_T_1851 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1853; // @[RegisterRouter.scala:87:24]
assign _out_T_1853 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1855; // @[RegisterRouter.scala:87:24]
assign _out_T_1855 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1857; // @[RegisterRouter.scala:87:24]
assign _out_T_1857 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1859; // @[RegisterRouter.scala:87:24]
assign _out_T_1859 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1861; // @[RegisterRouter.scala:87:24]
assign _out_T_1861 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1863; // @[RegisterRouter.scala:87:24]
assign _out_T_1863 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1865; // @[RegisterRouter.scala:87:24]
assign _out_T_1865 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1867; // @[RegisterRouter.scala:87:24]
assign _out_T_1867 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1869; // @[RegisterRouter.scala:87:24]
assign _out_T_1869 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1871; // @[RegisterRouter.scala:87:24]
assign _out_T_1871 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1873; // @[RegisterRouter.scala:87:24]
assign _out_T_1873 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1875; // @[RegisterRouter.scala:87:24]
assign _out_T_1875 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1879; // @[RegisterRouter.scala:87:24]
assign _out_T_1879 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1881; // @[RegisterRouter.scala:87:24]
assign _out_T_1881 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1883; // @[RegisterRouter.scala:87:24]
assign _out_T_1883 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1885; // @[RegisterRouter.scala:87:24]
assign _out_T_1885 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1887; // @[RegisterRouter.scala:87:24]
assign _out_T_1887 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1889; // @[RegisterRouter.scala:87:24]
assign _out_T_1889 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1891; // @[RegisterRouter.scala:87:24]
assign _out_T_1891 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1893; // @[RegisterRouter.scala:87:24]
assign _out_T_1893 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1895; // @[RegisterRouter.scala:87:24]
assign _out_T_1895 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1897; // @[RegisterRouter.scala:87:24]
assign _out_T_1897 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1899; // @[RegisterRouter.scala:87:24]
assign _out_T_1899 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1901; // @[RegisterRouter.scala:87:24]
assign _out_T_1901 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1903; // @[RegisterRouter.scala:87:24]
assign _out_T_1903 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1905; // @[RegisterRouter.scala:87:24]
assign _out_T_1905 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1907; // @[RegisterRouter.scala:87:24]
assign _out_T_1907 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1909; // @[RegisterRouter.scala:87:24]
assign _out_T_1909 = _GEN_19; // @[RegisterRouter.scala:87:24]
wire _out_out_bits_data_WIRE_2_138 = _out_T_1601; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_249 = _out_T_1603; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_234 = _out_T_1605; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_170 = _out_T_1607; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_115 = _out_T_1609; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_217 = _out_T_1611; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_247 = _out_T_1613; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_202 = _out_T_1615; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_142 = _out_T_1617; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_153 = _out_T_1619; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_174 = _out_T_1621; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_185 = _out_T_1623; // @[MuxLiteral.scala:49:48]
wire _GEN_20 = out_findex_1 == 9'h100; // @[RegisterRouter.scala:87:24]
wire _out_T_1624; // @[RegisterRouter.scala:87:24]
assign _out_T_1624 = _GEN_20; // @[RegisterRouter.scala:87:24]
wire _out_T_1640; // @[RegisterRouter.scala:87:24]
assign _out_T_1640 = _GEN_20; // @[RegisterRouter.scala:87:24]
wire _out_T_1666; // @[RegisterRouter.scala:87:24]
assign _out_T_1666 = _GEN_20; // @[RegisterRouter.scala:87:24]
wire _out_T_1678; // @[RegisterRouter.scala:87:24]
assign _out_T_1678 = _GEN_20; // @[RegisterRouter.scala:87:24]
wire _out_T_1716; // @[RegisterRouter.scala:87:24]
assign _out_T_1716 = _GEN_20; // @[RegisterRouter.scala:87:24]
wire _out_T_1724; // @[RegisterRouter.scala:87:24]
assign _out_T_1724 = _GEN_20; // @[RegisterRouter.scala:87:24]
wire _out_T_1742; // @[RegisterRouter.scala:87:24]
assign _out_T_1742 = _GEN_20; // @[RegisterRouter.scala:87:24]
wire _out_T_1756; // @[RegisterRouter.scala:87:24]
assign _out_T_1756 = _GEN_20; // @[RegisterRouter.scala:87:24]
wire _out_T_1822; // @[RegisterRouter.scala:87:24]
assign _out_T_1822 = _GEN_20; // @[RegisterRouter.scala:87:24]
wire _out_T_1846; // @[RegisterRouter.scala:87:24]
assign _out_T_1846 = _GEN_20; // @[RegisterRouter.scala:87:24]
wire _out_T_1876; // @[RegisterRouter.scala:87:24]
assign _out_T_1876 = _GEN_20; // @[RegisterRouter.scala:87:24]
wire _GEN_21 = out_bindex_1 == 9'h100; // @[RegisterRouter.scala:87:24]
wire _out_T_1625; // @[RegisterRouter.scala:87:24]
assign _out_T_1625 = _GEN_21; // @[RegisterRouter.scala:87:24]
wire _out_T_1641; // @[RegisterRouter.scala:87:24]
assign _out_T_1641 = _GEN_21; // @[RegisterRouter.scala:87:24]
wire _out_T_1667; // @[RegisterRouter.scala:87:24]
assign _out_T_1667 = _GEN_21; // @[RegisterRouter.scala:87:24]
wire _out_T_1679; // @[RegisterRouter.scala:87:24]
assign _out_T_1679 = _GEN_21; // @[RegisterRouter.scala:87:24]
wire _out_T_1717; // @[RegisterRouter.scala:87:24]
assign _out_T_1717 = _GEN_21; // @[RegisterRouter.scala:87:24]
wire _out_T_1725; // @[RegisterRouter.scala:87:24]
assign _out_T_1725 = _GEN_21; // @[RegisterRouter.scala:87:24]
wire _out_T_1743; // @[RegisterRouter.scala:87:24]
assign _out_T_1743 = _GEN_21; // @[RegisterRouter.scala:87:24]
wire _out_T_1757; // @[RegisterRouter.scala:87:24]
assign _out_T_1757 = _GEN_21; // @[RegisterRouter.scala:87:24]
wire _out_T_1823; // @[RegisterRouter.scala:87:24]
assign _out_T_1823 = _GEN_21; // @[RegisterRouter.scala:87:24]
wire _out_T_1847; // @[RegisterRouter.scala:87:24]
assign _out_T_1847 = _GEN_21; // @[RegisterRouter.scala:87:24]
wire _out_T_1877; // @[RegisterRouter.scala:87:24]
assign _out_T_1877 = _GEN_21; // @[RegisterRouter.scala:87:24]
wire _out_out_bits_data_WIRE_2_1 = _out_T_1625; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_184 = _out_T_1627; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_110 = _out_T_1629; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_196 = _out_T_1631; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_157 = _out_T_1633; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_189 = _out_T_1635; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_152 = _out_T_1637; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_228 = _out_T_1639; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_5 = _out_T_1641; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_216 = _out_T_1643; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_164 = _out_T_1645; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_179 = _out_T_1647; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_106 = _out_T_1649; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_238 = _out_T_1651; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_211 = _out_T_1653; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_253 = _out_T_1655; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_147 = _out_T_1657; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_221 = _out_T_1659; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_132 = _out_T_1661; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_133 = _out_T_1663; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_243 = _out_T_1665; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_9 = _out_T_1667; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_206 = _out_T_1669; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_233 = _out_T_1671; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_248 = _out_T_1673; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_201 = _out_T_1675; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_220 = _out_T_1677; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_4 = _out_T_1679; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_160 = _out_T_1681; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_192 = _out_T_1683; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_137 = _out_T_1685; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_165 = _out_T_1687; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_33 = _out_T_1689; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_229 = _out_T_1691; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_252 = _out_T_1693; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_197 = _out_T_1695; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_224 = _out_T_1697; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_156 = _out_T_1699; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_188 = _out_T_1701; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_169 = _out_T_1703; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_141 = _out_T_1705; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_225 = _out_T_1707; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_193 = _out_T_1709; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_212 = _out_T_1711; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_96 = _out_T_1713; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_109 = _out_T_1715; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_0 = _out_T_1717; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_173 = _out_T_1719; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_129 = _out_T_1721; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_134 = _out_T_1723; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_10 = _out_T_1725; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_205 = _out_T_1727; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_128 = _out_T_1729; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_237 = _out_T_1731; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_105 = _out_T_1733; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_244 = _out_T_1735; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_166 = _out_T_1737; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_32 = _out_T_1739; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_148 = _out_T_1741; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_8 = _out_T_1743; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_161 = _out_T_1745; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_180 = _out_T_1747; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_149 = _out_T_1749; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_176 = _out_T_1751; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_191 = _out_T_1753; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_204 = _out_T_1755; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_3 = _out_T_1757; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_144 = _out_T_1759; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_236 = _out_T_1761; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_181 = _out_T_1763; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_159 = _out_T_1765; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_187 = _out_T_1767; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_172 = _out_T_1769; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_113 = _out_T_1771; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_219 = _out_T_1773; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_230 = _out_T_1775; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_245 = _out_T_1777; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_208 = _out_T_1779; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_103 = _out_T_1781; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_140 = _out_T_1783; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_213 = _out_T_1785; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_155 = _out_T_1787; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_198 = _out_T_1789; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_108 = _out_T_1791; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_240 = _out_T_1793; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_251 = _out_T_1795; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_130 = _out_T_1797; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_223 = _out_T_1799; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_135 = _out_T_1801; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_226 = _out_T_1803; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_241 = _out_T_1805; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_167 = _out_T_1807; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_162 = _out_T_1809; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_255 = _out_T_1811; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_209 = _out_T_1813; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_112 = _out_T_1815; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_194 = _out_T_1817; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_145 = _out_T_1819; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_150 = _out_T_1821; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_7 = _out_T_1823; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_199 = _out_T_1825; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_177 = _out_T_1827; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_182 = _out_T_1829; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_154 = _out_T_1831; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_175 = _out_T_1833; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_143 = _out_T_1835; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_203 = _out_T_1837; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_218 = _out_T_1839; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_104 = _out_T_1841; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_250 = _out_T_1843; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_231 = _out_T_1845; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_2 = _out_T_1847; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_158 = _out_T_1849; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_186 = _out_T_1851; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_114 = _out_T_1853; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_171 = _out_T_1855; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_139 = _out_T_1857; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_207 = _out_T_1859; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_214 = _out_T_1861; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_235 = _out_T_1863; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_246 = _out_T_1865; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_151 = _out_T_1867; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_146 = _out_T_1869; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_190 = _out_T_1871; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_183 = _out_T_1873; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_168 = _out_T_1875; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_6 = _out_T_1877; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_210 = _out_T_1879; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_107 = _out_T_1881; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_136 = _out_T_1883; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_195 = _out_T_1885; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_239 = _out_T_1887; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_242 = _out_T_1889; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_131 = _out_T_1891; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_178 = _out_T_1893; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_163 = _out_T_1895; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_200 = _out_T_1897; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_111 = _out_T_1899; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_215 = _out_T_1901; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_222 = _out_T_1903; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_232 = _out_T_1905; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2_254 = _out_T_1907; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_T_814; // @[RegisterRouter.scala:87:24]
wire _out_out_bits_data_WIRE_2_227 = _out_T_1909; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_T_1258; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1198; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_942; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_722; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1130; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1250; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1070; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_830; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_874; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_958; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1002; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_266; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_998; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_702; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1046; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_890; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1018; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_870; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1174; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_282; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1126; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_918; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_978; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_686; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1214; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1106; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1274; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_850; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1146; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_790; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_794; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1234; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_298; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1086; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1194; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1254; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1066; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1142; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_278; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_902; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1030; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_810; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_922; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_394; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1178; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1270; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1050; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1158; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_886; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1014; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_938; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_826; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1162; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1034; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1110; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_646; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_698; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_262; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_954; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_778; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_798; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_302; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1082; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_774; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1210; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_682; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1238; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_926; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_390; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_854; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_294; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_906; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_982; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_858; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_966; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1026; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1078; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_274; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_838; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1206; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_986; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_898; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1010; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_950; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_714; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1138; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1182; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1242; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1094; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_674; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_822; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1114; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_882; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1054; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_694; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1222; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1266; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_782; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1154; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_802; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1166; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1226; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_930; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_910; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1282; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1098; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_710; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1038; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_842; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_862; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_290; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1058; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_970; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_990; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_878; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_962; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_834; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1074; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1134; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_678; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1262; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1186; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_270; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_894; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1006; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_718; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_946; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_818; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1090; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1118; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1202; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1246; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_866; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_846; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1022; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_994; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_934; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_286; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1102; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_690; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_806; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1042; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1218; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1230; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_786; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_974; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_914; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1062; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_706; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1122; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1150; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1190; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1278; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1170; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_0; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_2; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_3; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_4; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_5; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_6; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_7; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_8; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_9; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_10; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_11; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_12; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_13; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_14; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_15; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_16; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_17; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_18; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_19; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_20; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_21; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_22; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_23; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_24; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_25; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_26; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_27; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_28; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_29; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_30; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_31; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_32; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_33; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_34; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_35; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_36; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_37; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_38; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_39; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_40; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_41; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_42; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_43; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_44; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_45; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_46; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_47; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_48; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_49; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_50; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_51; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_52; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_53; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_54; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_55; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_56; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_57; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_58; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_59; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_60; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_61; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_62; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_63; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_64; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_65; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_66; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_67; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_68; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_69; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_70; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_71; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_72; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_73; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_74; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_75; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_76; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_77; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_78; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_79; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_80; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_81; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_82; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_83; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_84; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_85; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_86; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_87; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_88; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_89; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_90; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_91; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_92; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_93; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_94; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_95; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_96; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_97; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_98; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_99; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_100; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_101; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_102; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_103; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_104; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_105; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_106; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_107; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_108; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_109; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_110; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_111; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_112; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_113; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_114; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_115; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_116; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_117; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_118; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_119; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_120; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_121; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_122; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_123; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_124; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_125; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_126; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_127; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_128; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_129; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_130; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_131; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_132; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_133; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_134; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_135; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_136; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_137; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_138; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_139; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_140; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_141; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_142; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_143; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_144; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_145; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_146; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_147; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_148; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_149; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_150; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_151; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_152; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_153; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_154; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_155; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_156; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_157; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_158; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_159; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_160; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_161; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_162; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_163; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_164; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_165; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_166; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_167; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_168; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_169; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_170; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_171; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_172; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_173; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_174; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_175; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_176; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_177; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_178; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_179; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_180; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_181; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_182; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_183; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_184; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_185; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_186; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_187; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_188; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_189; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_190; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_191; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_192; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_193; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_194; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_195; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_196; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_197; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_198; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_199; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_200; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_201; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_202; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_203; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_204; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_205; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_206; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_207; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_208; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_209; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_210; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_211; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_212; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_213; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_214; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_215; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_216; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_217; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_218; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_219; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_220; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_221; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_222; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_223; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_224; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_225; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_226; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_227; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_228; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_229; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_230; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_231; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_232; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_233; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_234; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_235; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_236; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_237; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_238; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_239; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_240; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_241; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_242; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_243; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_244; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_245; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_246; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_247; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_248; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_249; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_250; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_251; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_252; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_253; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_254; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_255; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_256; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_257; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_258; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_259; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_260; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_261; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_262; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_263; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_264; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_265; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_266; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_267; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_268; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_269; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_270; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_271; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_272; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_273; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_274; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_275; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_276; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_277; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_278; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_279; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_280; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_281; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_282; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_283; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_284; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_285; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_286; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_287; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_288; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_289; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_290; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_291; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_292; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_293; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_294; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_295; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_296; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_297; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_298; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_299; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_300; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_301; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_302; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_303; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_304; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_305; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_306; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_307; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_308; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_309; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_310; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_311; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_312; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_313; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_314; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_315; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_316; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_317; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_318; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_319; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_320; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_321; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_322; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_323; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_324; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_325; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_326; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_327; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_328; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_329; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_330; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_331; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_332; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_333; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_334; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_335; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_336; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_337; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_338; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_339; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_340; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_341; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_342; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_343; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_344; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_345; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_346; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_347; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_348; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_349; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_350; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_351; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_352; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_353; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_354; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_355; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_356; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_357; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_358; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_359; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_360; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_361; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_362; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_363; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_364; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_365; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_366; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_367; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_368; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_369; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_370; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_371; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_372; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_373; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_374; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_375; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_376; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_377; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_378; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_379; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_380; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_381; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_382; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_383; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_384; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_385; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_386; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_387; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_388; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_389; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_390; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_391; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_392; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_393; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_394; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_395; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_396; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_397; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_398; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_399; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_400; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_401; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_402; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_403; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_404; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_405; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_406; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_407; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_408; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_409; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_410; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_411; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_412; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_413; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_414; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_415; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_416; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_417; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_418; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_419; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_420; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_421; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_422; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_423; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_424; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_425; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_426; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_427; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_428; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_429; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_430; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_431; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_432; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_433; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_434; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_435; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_436; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_437; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_438; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_439; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_440; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_441; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_442; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_443; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_444; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_445; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_446; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_447; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_448; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_449; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_450; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_451; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_452; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_453; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_454; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_455; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_456; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_457; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_458; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_459; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_460; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_461; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_462; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_463; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_464; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_465; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_466; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_467; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_468; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_469; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_470; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_471; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_472; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_473; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_474; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_475; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_476; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_477; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_478; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_479; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_480; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_481; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_482; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_483; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_484; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_485; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_486; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_487; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_488; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_489; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_490; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_491; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_492; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_493; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_494; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_495; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_496; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_497; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_498; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_499; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_500; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_501; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_502; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_503; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_504; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_505; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_506; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_507; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_508; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_509; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_510; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_511; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_512; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_513; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_514; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_515; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_516; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_517; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_518; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_519; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_520; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_521; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_522; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_523; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_524; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_525; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_526; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_527; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_528; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_529; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_530; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_531; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_532; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_533; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_534; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_535; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_536; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_537; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_538; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_539; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_540; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_541; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_542; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_543; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_544; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_545; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_546; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_547; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_548; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_549; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_550; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_551; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_552; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_553; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_554; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_555; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_556; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_557; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_558; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_559; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_560; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_561; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_562; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_563; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_564; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_565; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_566; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_567; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_568; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_569; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_570; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_571; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_572; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_573; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_574; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_575; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_576; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_577; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_578; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_579; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_580; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_581; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_582; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_583; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_584; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_585; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_586; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_587; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_588; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_589; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_590; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_591; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_592; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_593; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_594; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_595; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_596; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_597; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_598; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_599; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_600; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_601; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_602; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_603; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_604; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_605; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_606; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_607; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_608; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_609; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_610; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_611; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_612; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_613; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_614; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_615; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_616; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_617; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_618; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_619; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_620; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_621; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_622; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_623; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_624; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_625; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_626; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_627; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_628; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_629; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_630; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_631; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_632; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_633; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_634; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_635; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_636; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_637; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_638; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_639; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_640; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_641; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_642; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_643; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_644; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_645; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_646; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_647; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_648; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_649; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_650; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_651; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_652; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_653; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_654; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_655; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_656; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_657; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_658; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_659; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_660; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_661; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_662; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_663; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_664; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_665; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_666; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_667; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_668; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_669; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_670; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_671; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_672; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_673; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_674; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_675; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_676; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_677; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_678; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_679; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_680; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_681; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_682; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_683; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_684; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_685; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_686; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_687; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_688; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_689; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_690; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_691; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_692; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_693; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_694; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_695; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_696; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_697; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_698; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_699; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_700; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_701; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_702; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_703; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_704; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_705; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_706; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_707; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_708; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_709; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_710; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_711; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_712; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_713; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_714; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_715; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_716; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_717; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_718; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_719; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_720; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_721; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_722; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_723; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_724; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_725; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_726; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_727; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_728; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_729; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_730; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_731; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_732; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_733; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_734; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_735; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_736; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_737; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_738; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_739; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_740; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_741; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_742; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_743; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_744; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_745; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_746; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_747; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_748; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_749; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_750; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_751; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_752; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_753; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_754; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_755; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_756; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_757; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_758; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_759; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_760; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_761; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_762; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_763; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_764; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_765; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_766; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_767; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_768; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_769; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_770; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_771; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_772; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_773; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_774; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_775; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_776; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_777; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_778; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_779; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_780; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_781; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_782; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_783; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_784; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_785; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_786; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_787; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_788; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_789; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_790; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_791; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_792; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_793; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_794; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_795; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_796; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_797; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_798; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_799; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_800; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_801; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_802; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_803; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_804; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_805; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_806; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_807; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_808; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_809; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_810; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_811; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_812; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_813; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_814; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_815; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_816; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_817; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_818; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_819; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_820; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_821; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_822; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_823; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_824; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_825; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_826; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_827; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_828; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_829; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_830; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_831; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_832; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_833; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_834; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_835; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_836; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_837; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_838; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_839; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_840; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_841; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_842; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_843; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_844; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_845; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_846; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_847; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_848; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_849; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_850; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_851; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_852; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_853; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_854; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_855; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_856; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_857; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_858; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_859; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_860; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_861; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_862; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_863; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_864; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_865; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_866; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_867; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_868; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_869; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_870; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_871; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_872; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_873; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_874; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_875; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_876; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_877; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_878; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_879; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_880; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_881; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_882; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_883; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_884; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_885; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_886; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_887; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_888; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_889; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_890; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_891; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_892; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_893; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_894; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_895; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_896; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_897; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_898; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_899; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_900; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_901; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_902; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_903; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_904; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_905; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_906; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_907; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_908; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_909; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_910; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_911; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_912; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_913; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_914; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_915; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_916; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_917; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_918; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_919; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_920; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_921; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_922; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_923; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_924; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_925; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_926; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_927; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_928; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_929; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_930; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_931; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_932; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_933; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_934; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_935; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_936; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_937; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_938; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_939; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_940; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_941; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_942; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_943; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_944; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_945; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_946; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_947; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_948; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_949; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_950; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_951; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_952; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_953; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_954; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_955; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_956; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_957; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_958; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_959; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_960; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_961; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_962; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_963; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_964; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_965; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_966; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_967; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_968; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_969; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_970; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_971; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_972; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_973; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_974; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_975; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_976; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_977; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_978; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_979; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_980; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_981; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_982; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_983; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_984; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_985; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_986; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_987; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_988; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_989; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_990; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_991; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_992; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_993; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_994; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_995; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_996; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_997; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_998; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_999; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1000; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1001; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1002; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1003; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1004; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1005; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1006; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1007; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1008; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1009; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1010; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1011; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1012; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1013; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1014; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1015; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1016; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1017; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1018; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1019; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1020; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1021; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1022; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1023; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1024; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1025; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1026; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1027; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1028; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1029; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1030; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1031; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1032; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1033; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1034; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1035; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1036; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1037; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1038; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1039; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1040; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1041; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1042; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1043; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1044; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1045; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1046; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1047; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1048; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1049; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1050; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1051; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1052; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1053; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1054; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1055; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1056; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1057; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1058; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1059; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1060; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1061; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1062; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1063; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1064; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1065; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1066; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1067; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1068; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1069; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1070; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1071; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1072; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1073; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1074; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1075; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1076; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1077; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1078; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1079; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1080; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1081; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1082; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1083; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1084; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1085; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1086; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1087; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1088; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1089; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1090; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1091; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1092; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1093; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1094; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1095; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1096; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1097; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1098; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1099; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1100; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1101; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1102; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1103; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1104; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1105; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1106; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1107; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1108; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1109; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1110; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1111; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1112; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1113; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1114; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1115; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1116; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1117; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1118; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1119; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1120; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1121; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1122; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1123; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1124; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1125; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1126; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1127; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1128; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1129; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1130; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1131; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1132; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1133; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1134; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1135; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1136; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1137; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1138; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1139; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1140; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1141; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1142; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1143; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1144; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1145; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1146; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1147; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1148; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1149; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1150; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1151; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1152; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1153; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1154; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1155; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1156; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1157; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1158; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1159; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1160; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1161; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1162; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1163; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1164; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1165; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1166; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1167; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1168; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1169; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1170; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1171; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1172; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1173; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1174; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1175; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1176; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1177; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1178; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1179; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1180; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1181; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1182; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1183; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1184; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1185; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1186; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1187; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1188; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1189; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1190; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1191; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1192; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1193; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1194; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1195; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1196; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1197; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1198; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1199; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1200; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1201; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1202; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1203; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1204; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1205; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1206; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1207; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1208; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1209; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1210; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_816; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1260; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1200; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_944; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_724; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1132; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1252; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1072; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_832; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_876; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_960; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1004; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_268; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1000; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_704; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1048; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_892; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1020; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_872; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1176; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_284; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1128; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_920; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_980; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_688; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1216; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1108; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1276; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_852; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1148; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_792; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_796; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1236; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_300; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1088; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1196; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1256; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1068; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1144; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_280; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_904; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1032; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_812; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_924; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_396; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1180; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1272; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1052; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1160; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_888; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1016; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_940; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_828; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1164; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1036; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1112; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_648; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_700; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_264; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_956; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_780; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_800; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_304; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1084; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_776; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1212; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_684; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1240; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_928; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_392; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_856; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_296; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_908; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_984; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_860; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_968; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1028; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1080; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_276; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_840; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1208; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_988; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_900; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1012; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_952; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_716; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1140; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1184; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1244; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1096; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_676; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_824; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1116; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_884; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1056; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_696; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1224; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1268; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_784; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1156; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_804; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1168; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1228; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_932; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_912; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1284; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1100; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_712; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1040; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_844; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_864; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_292; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1060; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_972; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_992; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_880; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_964; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_836; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1076; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1136; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_680; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1264; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1188; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_272; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_896; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1008; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_720; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_948; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_820; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1092; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1120; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1204; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1248; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_868; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_848; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1024; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_996; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_936; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_288; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1104; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_692; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_808; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1044; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1220; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1232; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_788; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_976; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_916; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1064; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_708; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1124; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1152; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1192; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1280; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1172; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_0; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_2; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_3; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_4; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_5; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_6; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_7; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_8; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_9; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_10; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_11; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_12; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_13; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_14; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_15; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_16; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_17; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_18; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_19; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_20; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_21; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_22; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_23; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_24; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_25; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_26; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_27; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_28; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_29; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_30; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_31; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_32; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_33; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_34; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_35; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_36; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_37; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_38; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_39; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_40; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_41; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_42; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_43; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_44; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_45; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_46; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_47; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_48; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_49; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_50; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_51; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_52; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_53; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_54; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_55; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_56; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_57; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_58; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_59; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_60; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_61; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_62; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_63; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_64; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_65; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_66; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_67; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_68; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_69; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_70; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_71; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_72; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_73; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_74; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_75; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_76; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_77; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_78; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_79; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_80; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_81; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_82; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_83; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_84; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_85; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_86; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_87; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_88; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_89; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_90; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_91; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_92; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_93; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_94; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_95; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_96; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_97; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_98; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_99; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_100; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_101; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_102; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_103; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_104; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_105; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_106; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_107; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_108; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_109; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_110; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_111; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_112; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_113; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_114; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_115; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_116; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_117; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_118; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_119; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_120; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_121; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_122; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_123; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_124; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_125; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_126; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_127; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_128; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_129; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_130; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_131; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_132; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_133; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_134; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_135; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_136; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_137; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_138; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_139; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_140; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_141; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_142; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_143; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_144; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_145; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_146; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_147; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_148; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_149; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_150; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_151; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_152; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_153; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_154; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_155; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_156; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_157; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_158; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_159; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_160; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_161; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_162; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_163; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_164; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_165; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_166; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_167; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_168; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_169; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_170; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_171; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_172; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_173; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_174; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_175; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_176; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_177; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_178; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_179; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_180; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_181; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_182; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_183; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_184; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_185; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_186; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_187; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_188; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_189; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_190; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_191; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_192; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_193; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_194; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_195; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_196; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_197; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_198; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_199; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_200; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_201; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_202; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_203; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_204; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_205; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_206; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_207; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_208; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_209; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_210; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_211; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_212; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_213; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_214; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_215; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_216; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_217; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_218; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_219; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_220; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_221; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_222; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_223; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_224; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_225; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_226; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_227; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_228; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_229; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_230; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_231; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_232; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_233; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_234; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_235; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_236; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_237; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_238; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_239; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_240; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_241; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_242; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_243; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_244; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_245; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_246; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_247; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_248; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_249; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_250; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_251; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_252; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_253; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_254; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_255; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_256; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_257; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_258; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_259; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_260; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_261; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_262; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_263; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_264; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_265; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_266; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_267; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_268; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_269; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_270; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_271; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_272; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_273; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_274; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_275; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_276; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_277; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_278; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_279; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_280; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_281; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_282; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_283; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_284; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_285; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_286; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_287; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_288; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_289; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_290; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_291; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_292; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_293; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_294; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_295; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_296; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_297; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_298; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_299; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_300; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_301; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_302; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_303; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_304; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_305; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_306; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_307; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_308; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_309; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_310; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_311; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_312; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_313; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_314; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_315; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_316; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_317; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_318; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_319; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_320; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_321; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_322; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_323; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_324; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_325; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_326; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_327; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_328; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_329; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_330; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_331; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_332; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_333; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_334; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_335; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_336; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_337; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_338; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_339; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_340; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_341; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_342; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_343; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_344; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_345; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_346; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_347; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_348; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_349; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_350; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_351; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_352; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_353; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_354; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_355; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_356; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_357; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_358; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_359; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_360; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_361; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_362; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_363; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_364; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_365; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_366; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_367; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_368; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_369; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_370; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_371; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_372; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_373; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_374; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_375; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_376; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_377; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_378; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_379; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_380; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_381; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_382; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_383; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_384; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_385; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_386; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_387; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_388; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_389; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_390; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_391; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_392; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_393; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_394; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_395; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_396; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_397; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_398; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_399; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_400; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_401; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_402; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_403; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_404; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_405; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_406; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_407; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_408; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_409; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_410; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_411; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_412; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_413; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_414; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_415; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_416; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_417; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_418; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_419; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_420; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_421; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_422; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_423; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_424; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_425; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_426; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_427; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_428; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_429; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_430; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_431; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_432; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_433; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_434; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_435; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_436; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_437; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_438; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_439; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_440; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_441; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_442; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_443; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_444; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_445; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_446; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_447; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_448; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_449; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_450; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_451; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_452; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_453; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_454; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_455; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_456; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_457; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_458; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_459; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_460; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_461; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_462; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_463; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_464; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_465; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_466; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_467; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_468; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_469; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_470; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_471; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_472; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_473; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_474; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_475; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_476; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_477; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_478; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_479; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_480; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_481; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_482; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_483; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_484; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_485; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_486; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_487; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_488; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_489; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_490; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_491; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_492; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_493; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_494; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_495; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_496; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_497; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_498; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_499; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_500; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_501; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_502; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_503; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_504; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_505; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_506; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_507; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_508; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_509; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_510; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_511; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_512; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_513; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_514; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_515; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_516; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_517; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_518; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_519; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_520; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_521; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_522; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_523; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_524; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_525; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_526; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_527; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_528; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_529; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_530; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_531; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_532; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_533; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_534; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_535; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_536; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_537; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_538; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_539; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_540; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_541; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_542; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_543; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_544; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_545; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_546; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_547; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_548; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_549; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_550; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_551; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_552; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_553; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_554; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_555; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_556; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_557; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_558; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_559; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_560; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_561; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_562; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_563; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_564; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_565; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_566; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_567; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_568; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_569; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_570; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_571; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_572; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_573; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_574; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_575; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_576; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_577; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_578; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_579; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_580; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_581; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_582; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_583; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_584; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_585; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_586; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_587; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_588; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_589; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_590; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_591; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_592; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_593; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_594; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_595; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_596; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_597; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_598; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_599; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_600; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_601; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_602; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_603; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_604; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_605; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_606; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_607; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_608; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_609; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_610; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_611; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_612; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_613; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_614; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_615; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_616; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_617; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_618; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_619; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_620; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_621; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_622; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_623; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_624; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_625; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_626; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_627; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_628; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_629; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_630; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_631; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_632; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_633; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_634; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_635; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_636; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_637; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_638; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_639; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_640; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_641; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_642; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_643; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_644; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_645; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_646; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_647; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_648; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_649; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_650; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_651; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_652; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_653; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_654; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_655; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_656; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_657; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_658; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_659; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_660; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_661; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_662; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_663; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_664; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_665; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_666; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_667; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_668; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_669; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_670; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_671; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_672; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_673; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_674; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_675; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_676; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_677; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_678; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_679; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_680; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_681; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_682; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_683; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_684; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_685; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_686; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_687; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_688; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_689; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_690; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_691; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_692; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_693; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_694; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_695; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_696; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_697; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_698; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_699; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_700; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_701; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_702; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_703; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_704; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_705; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_706; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_707; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_708; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_709; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_710; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_711; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_712; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_713; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_714; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_715; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_716; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_717; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_718; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_719; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_720; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_721; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_722; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_723; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_724; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_725; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_726; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_727; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_728; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_729; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_730; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_731; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_732; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_733; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_734; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_735; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_736; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_737; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_738; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_739; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_740; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_741; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_742; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_743; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_744; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_745; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_746; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_747; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_748; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_749; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_750; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_751; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_752; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_753; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_754; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_755; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_756; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_757; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_758; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_759; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_760; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_761; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_762; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_763; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_764; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_765; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_766; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_767; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_768; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_769; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_770; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_771; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_772; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_773; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_774; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_775; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_776; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_777; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_778; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_779; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_780; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_781; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_782; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_783; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_784; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_785; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_786; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_787; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_788; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_789; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_790; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_791; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_792; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_793; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_794; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_795; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_796; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_797; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_798; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_799; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_800; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_801; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_802; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_803; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_804; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_805; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_806; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_807; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_808; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_809; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_810; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_811; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_812; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_813; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_814; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_815; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_816; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_817; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_818; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_819; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_820; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_821; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_822; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_823; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_824; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_825; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_826; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_827; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_828; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_829; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_830; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_831; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_832; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_833; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_834; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_835; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_836; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_837; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_838; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_839; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_840; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_841; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_842; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_843; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_844; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_845; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_846; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_847; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_848; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_849; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_850; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_851; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_852; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_853; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_854; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_855; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_856; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_857; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_858; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_859; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_860; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_861; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_862; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_863; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_864; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_865; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_866; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_867; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_868; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_869; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_870; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_871; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_872; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_873; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_874; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_875; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_876; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_877; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_878; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_879; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_880; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_881; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_882; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_883; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_884; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_885; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_886; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_887; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_888; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_889; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_890; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_891; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_892; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_893; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_894; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_895; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_896; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_897; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_898; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_899; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_900; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_901; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_902; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_903; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_904; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_905; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_906; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_907; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_908; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_909; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_910; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_911; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_912; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_913; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_914; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_915; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_916; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_917; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_918; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_919; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_920; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_921; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_922; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_923; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_924; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_925; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_926; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_927; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_928; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_929; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_930; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_931; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_932; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_933; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_934; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_935; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_936; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_937; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_938; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_939; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_940; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_941; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_942; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_943; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_944; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_945; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_946; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_947; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_948; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_949; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_950; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_951; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_952; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_953; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_954; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_955; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_956; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_957; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_958; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_959; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_960; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_961; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_962; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_963; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_964; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_965; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_966; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_967; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_968; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_969; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_970; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_971; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_972; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_973; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_974; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_975; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_976; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_977; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_978; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_979; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_980; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_981; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_982; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_983; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_984; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_985; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_986; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_987; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_988; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_989; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_990; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_991; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_992; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_993; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_994; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_995; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_996; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_997; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_998; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_999; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1000; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1001; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1002; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1003; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1004; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1005; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1006; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1007; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1008; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1009; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1010; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1011; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1012; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1013; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1014; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1015; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1016; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1017; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1018; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1019; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1020; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1021; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1022; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1023; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1024; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1025; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1026; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1027; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1028; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1029; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1030; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1031; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1032; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1033; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1034; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1035; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1036; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1037; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1038; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1039; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1040; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1041; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1042; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1043; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1044; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1045; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1046; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1047; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1048; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1049; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1050; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1051; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1052; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1053; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1054; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1055; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1056; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1057; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1058; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1059; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1060; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1061; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1062; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1063; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1064; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1065; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1066; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1067; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1068; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1069; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1070; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1071; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1072; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1073; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1074; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1075; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1076; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1077; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1078; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1079; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1080; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1081; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1082; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1083; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1084; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1085; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1086; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1087; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1088; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1089; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1090; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1091; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1092; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1093; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1094; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1095; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1096; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1097; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1098; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1099; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1100; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1101; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1102; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1103; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1104; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1105; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1106; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1107; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1108; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1109; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1110; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1111; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1112; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1113; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1114; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1115; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1116; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1117; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1118; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1119; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1120; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1121; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1122; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1123; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1124; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1125; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1126; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1127; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1128; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1129; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1130; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1131; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1132; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1133; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1134; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1135; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1136; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1137; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1138; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1139; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1140; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1141; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1142; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1143; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1144; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1145; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1146; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1147; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1148; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1149; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1150; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1151; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1152; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1153; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1154; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1155; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1156; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1157; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1158; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1159; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1160; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1161; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1162; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1163; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1164; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1165; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1166; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1167; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1168; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1169; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1170; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1171; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1172; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1173; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1174; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1175; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1176; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1177; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1178; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1179; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1180; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1181; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1182; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1183; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1184; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1185; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1186; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1187; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1188; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1189; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1190; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1191; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1192; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1193; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1194; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1195; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1196; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1197; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1198; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1199; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1200; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1201; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1202; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1203; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1204; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1205; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1206; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1207; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1208; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1209; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1210; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_814; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1258; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1198; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_942; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_722; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1130; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1250; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1070; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_830; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_874; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_958; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1002; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_266; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_998; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_702; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1046; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_890; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1018; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_870; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1174; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_282; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1126; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_918; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_978; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_686; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1214; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1106; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1274; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_850; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1146; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_790; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_794; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1234; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_298; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1086; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1194; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1254; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1066; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1142; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_278; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_902; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1030; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_810; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_922; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_394; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1178; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1270; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1050; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1158; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_886; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1014; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_938; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_826; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1162; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1034; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1110; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_646; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_698; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_262; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_954; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_778; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_798; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_302; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1082; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_774; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1210; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_682; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1238; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_926; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_390; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_854; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_294; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_906; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_982; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_858; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_966; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1026; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1078; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_274; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_838; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1206; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_986; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_898; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1010; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_950; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_714; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1138; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1182; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1242; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1094; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_674; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_822; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1114; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_882; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1054; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_694; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1222; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1266; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_782; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1154; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_802; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1166; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1226; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_930; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_910; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1282; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1098; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_710; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1038; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_842; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_862; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_290; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1058; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_970; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_990; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_878; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_962; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_834; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1074; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1134; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_678; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1262; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1186; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_270; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_894; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1006; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_718; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_946; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_818; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1090; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1118; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1202; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1246; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_866; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_846; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1022; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_994; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_934; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_286; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1102; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_690; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_806; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1042; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1218; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1230; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_786; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_974; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_914; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1062; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_706; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1122; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1150; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1190; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1278; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1170; // @[RegisterRouter.scala:87:24]
wire out_roready_1_0; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1; // @[RegisterRouter.scala:87:24]
wire out_roready_1_2; // @[RegisterRouter.scala:87:24]
wire out_roready_1_3; // @[RegisterRouter.scala:87:24]
wire out_roready_1_4; // @[RegisterRouter.scala:87:24]
wire out_roready_1_5; // @[RegisterRouter.scala:87:24]
wire out_roready_1_6; // @[RegisterRouter.scala:87:24]
wire out_roready_1_7; // @[RegisterRouter.scala:87:24]
wire out_roready_1_8; // @[RegisterRouter.scala:87:24]
wire out_roready_1_9; // @[RegisterRouter.scala:87:24]
wire out_roready_1_10; // @[RegisterRouter.scala:87:24]
wire out_roready_1_11; // @[RegisterRouter.scala:87:24]
wire out_roready_1_12; // @[RegisterRouter.scala:87:24]
wire out_roready_1_13; // @[RegisterRouter.scala:87:24]
wire out_roready_1_14; // @[RegisterRouter.scala:87:24]
wire out_roready_1_15; // @[RegisterRouter.scala:87:24]
wire out_roready_1_16; // @[RegisterRouter.scala:87:24]
wire out_roready_1_17; // @[RegisterRouter.scala:87:24]
wire out_roready_1_18; // @[RegisterRouter.scala:87:24]
wire out_roready_1_19; // @[RegisterRouter.scala:87:24]
wire out_roready_1_20; // @[RegisterRouter.scala:87:24]
wire out_roready_1_21; // @[RegisterRouter.scala:87:24]
wire out_roready_1_22; // @[RegisterRouter.scala:87:24]
wire out_roready_1_23; // @[RegisterRouter.scala:87:24]
wire out_roready_1_24; // @[RegisterRouter.scala:87:24]
wire out_roready_1_25; // @[RegisterRouter.scala:87:24]
wire out_roready_1_26; // @[RegisterRouter.scala:87:24]
wire out_roready_1_27; // @[RegisterRouter.scala:87:24]
wire out_roready_1_28; // @[RegisterRouter.scala:87:24]
wire out_roready_1_29; // @[RegisterRouter.scala:87:24]
wire out_roready_1_30; // @[RegisterRouter.scala:87:24]
wire out_roready_1_31; // @[RegisterRouter.scala:87:24]
wire out_roready_1_32; // @[RegisterRouter.scala:87:24]
wire out_roready_1_33; // @[RegisterRouter.scala:87:24]
wire out_roready_1_34; // @[RegisterRouter.scala:87:24]
wire out_roready_1_35; // @[RegisterRouter.scala:87:24]
wire out_roready_1_36; // @[RegisterRouter.scala:87:24]
wire out_roready_1_37; // @[RegisterRouter.scala:87:24]
wire out_roready_1_38; // @[RegisterRouter.scala:87:24]
wire out_roready_1_39; // @[RegisterRouter.scala:87:24]
wire out_roready_1_40; // @[RegisterRouter.scala:87:24]
wire out_roready_1_41; // @[RegisterRouter.scala:87:24]
wire out_roready_1_42; // @[RegisterRouter.scala:87:24]
wire out_roready_1_43; // @[RegisterRouter.scala:87:24]
wire out_roready_1_44; // @[RegisterRouter.scala:87:24]
wire out_roready_1_45; // @[RegisterRouter.scala:87:24]
wire out_roready_1_46; // @[RegisterRouter.scala:87:24]
wire out_roready_1_47; // @[RegisterRouter.scala:87:24]
wire out_roready_1_48; // @[RegisterRouter.scala:87:24]
wire out_roready_1_49; // @[RegisterRouter.scala:87:24]
wire out_roready_1_50; // @[RegisterRouter.scala:87:24]
wire out_roready_1_51; // @[RegisterRouter.scala:87:24]
wire out_roready_1_52; // @[RegisterRouter.scala:87:24]
wire out_roready_1_53; // @[RegisterRouter.scala:87:24]
wire out_roready_1_54; // @[RegisterRouter.scala:87:24]
wire out_roready_1_55; // @[RegisterRouter.scala:87:24]
wire out_roready_1_56; // @[RegisterRouter.scala:87:24]
wire out_roready_1_57; // @[RegisterRouter.scala:87:24]
wire out_roready_1_58; // @[RegisterRouter.scala:87:24]
wire out_roready_1_59; // @[RegisterRouter.scala:87:24]
wire out_roready_1_60; // @[RegisterRouter.scala:87:24]
wire out_roready_1_61; // @[RegisterRouter.scala:87:24]
wire out_roready_1_62; // @[RegisterRouter.scala:87:24]
wire out_roready_1_63; // @[RegisterRouter.scala:87:24]
wire out_roready_1_64; // @[RegisterRouter.scala:87:24]
wire out_roready_1_65; // @[RegisterRouter.scala:87:24]
wire out_roready_1_66; // @[RegisterRouter.scala:87:24]
wire out_roready_1_67; // @[RegisterRouter.scala:87:24]
wire out_roready_1_68; // @[RegisterRouter.scala:87:24]
wire out_roready_1_69; // @[RegisterRouter.scala:87:24]
wire out_roready_1_70; // @[RegisterRouter.scala:87:24]
wire out_roready_1_71; // @[RegisterRouter.scala:87:24]
wire out_roready_1_72; // @[RegisterRouter.scala:87:24]
wire out_roready_1_73; // @[RegisterRouter.scala:87:24]
wire out_roready_1_74; // @[RegisterRouter.scala:87:24]
wire out_roready_1_75; // @[RegisterRouter.scala:87:24]
wire out_roready_1_76; // @[RegisterRouter.scala:87:24]
wire out_roready_1_77; // @[RegisterRouter.scala:87:24]
wire out_roready_1_78; // @[RegisterRouter.scala:87:24]
wire out_roready_1_79; // @[RegisterRouter.scala:87:24]
wire out_roready_1_80; // @[RegisterRouter.scala:87:24]
wire out_roready_1_81; // @[RegisterRouter.scala:87:24]
wire out_roready_1_82; // @[RegisterRouter.scala:87:24]
wire out_roready_1_83; // @[RegisterRouter.scala:87:24]
wire out_roready_1_84; // @[RegisterRouter.scala:87:24]
wire out_roready_1_85; // @[RegisterRouter.scala:87:24]
wire out_roready_1_86; // @[RegisterRouter.scala:87:24]
wire out_roready_1_87; // @[RegisterRouter.scala:87:24]
wire out_roready_1_88; // @[RegisterRouter.scala:87:24]
wire out_roready_1_89; // @[RegisterRouter.scala:87:24]
wire out_roready_1_90; // @[RegisterRouter.scala:87:24]
wire out_roready_1_91; // @[RegisterRouter.scala:87:24]
wire out_roready_1_92; // @[RegisterRouter.scala:87:24]
wire out_roready_1_93; // @[RegisterRouter.scala:87:24]
wire out_roready_1_94; // @[RegisterRouter.scala:87:24]
wire out_roready_1_95; // @[RegisterRouter.scala:87:24]
wire out_roready_1_96; // @[RegisterRouter.scala:87:24]
wire out_roready_1_97; // @[RegisterRouter.scala:87:24]
wire out_roready_1_98; // @[RegisterRouter.scala:87:24]
wire out_roready_1_99; // @[RegisterRouter.scala:87:24]
wire out_roready_1_100; // @[RegisterRouter.scala:87:24]
wire out_roready_1_101; // @[RegisterRouter.scala:87:24]
wire out_roready_1_102; // @[RegisterRouter.scala:87:24]
wire out_roready_1_103; // @[RegisterRouter.scala:87:24]
wire out_roready_1_104; // @[RegisterRouter.scala:87:24]
wire out_roready_1_105; // @[RegisterRouter.scala:87:24]
wire out_roready_1_106; // @[RegisterRouter.scala:87:24]
wire out_roready_1_107; // @[RegisterRouter.scala:87:24]
wire out_roready_1_108; // @[RegisterRouter.scala:87:24]
wire out_roready_1_109; // @[RegisterRouter.scala:87:24]
wire out_roready_1_110; // @[RegisterRouter.scala:87:24]
wire out_roready_1_111; // @[RegisterRouter.scala:87:24]
wire out_roready_1_112; // @[RegisterRouter.scala:87:24]
wire out_roready_1_113; // @[RegisterRouter.scala:87:24]
wire out_roready_1_114; // @[RegisterRouter.scala:87:24]
wire out_roready_1_115; // @[RegisterRouter.scala:87:24]
wire out_roready_1_116; // @[RegisterRouter.scala:87:24]
wire out_roready_1_117; // @[RegisterRouter.scala:87:24]
wire out_roready_1_118; // @[RegisterRouter.scala:87:24]
wire out_roready_1_119; // @[RegisterRouter.scala:87:24]
wire out_roready_1_120; // @[RegisterRouter.scala:87:24]
wire out_roready_1_121; // @[RegisterRouter.scala:87:24]
wire out_roready_1_122; // @[RegisterRouter.scala:87:24]
wire out_roready_1_123; // @[RegisterRouter.scala:87:24]
wire out_roready_1_124; // @[RegisterRouter.scala:87:24]
wire out_roready_1_125; // @[RegisterRouter.scala:87:24]
wire out_roready_1_126; // @[RegisterRouter.scala:87:24]
wire out_roready_1_127; // @[RegisterRouter.scala:87:24]
wire out_roready_1_128; // @[RegisterRouter.scala:87:24]
wire out_roready_1_129; // @[RegisterRouter.scala:87:24]
wire out_roready_1_130; // @[RegisterRouter.scala:87:24]
wire out_roready_1_131; // @[RegisterRouter.scala:87:24]
wire out_roready_1_132; // @[RegisterRouter.scala:87:24]
wire out_roready_1_133; // @[RegisterRouter.scala:87:24]
wire out_roready_1_134; // @[RegisterRouter.scala:87:24]
wire out_roready_1_135; // @[RegisterRouter.scala:87:24]
wire out_roready_1_136; // @[RegisterRouter.scala:87:24]
wire out_roready_1_137; // @[RegisterRouter.scala:87:24]
wire out_roready_1_138; // @[RegisterRouter.scala:87:24]
wire out_roready_1_139; // @[RegisterRouter.scala:87:24]
wire out_roready_1_140; // @[RegisterRouter.scala:87:24]
wire out_roready_1_141; // @[RegisterRouter.scala:87:24]
wire out_roready_1_142; // @[RegisterRouter.scala:87:24]
wire out_roready_1_143; // @[RegisterRouter.scala:87:24]
wire out_roready_1_144; // @[RegisterRouter.scala:87:24]
wire out_roready_1_145; // @[RegisterRouter.scala:87:24]
wire out_roready_1_146; // @[RegisterRouter.scala:87:24]
wire out_roready_1_147; // @[RegisterRouter.scala:87:24]
wire out_roready_1_148; // @[RegisterRouter.scala:87:24]
wire out_roready_1_149; // @[RegisterRouter.scala:87:24]
wire out_roready_1_150; // @[RegisterRouter.scala:87:24]
wire out_roready_1_151; // @[RegisterRouter.scala:87:24]
wire out_roready_1_152; // @[RegisterRouter.scala:87:24]
wire out_roready_1_153; // @[RegisterRouter.scala:87:24]
wire out_roready_1_154; // @[RegisterRouter.scala:87:24]
wire out_roready_1_155; // @[RegisterRouter.scala:87:24]
wire out_roready_1_156; // @[RegisterRouter.scala:87:24]
wire out_roready_1_157; // @[RegisterRouter.scala:87:24]
wire out_roready_1_158; // @[RegisterRouter.scala:87:24]
wire out_roready_1_159; // @[RegisterRouter.scala:87:24]
wire out_roready_1_160; // @[RegisterRouter.scala:87:24]
wire out_roready_1_161; // @[RegisterRouter.scala:87:24]
wire out_roready_1_162; // @[RegisterRouter.scala:87:24]
wire out_roready_1_163; // @[RegisterRouter.scala:87:24]
wire out_roready_1_164; // @[RegisterRouter.scala:87:24]
wire out_roready_1_165; // @[RegisterRouter.scala:87:24]
wire out_roready_1_166; // @[RegisterRouter.scala:87:24]
wire out_roready_1_167; // @[RegisterRouter.scala:87:24]
wire out_roready_1_168; // @[RegisterRouter.scala:87:24]
wire out_roready_1_169; // @[RegisterRouter.scala:87:24]
wire out_roready_1_170; // @[RegisterRouter.scala:87:24]
wire out_roready_1_171; // @[RegisterRouter.scala:87:24]
wire out_roready_1_172; // @[RegisterRouter.scala:87:24]
wire out_roready_1_173; // @[RegisterRouter.scala:87:24]
wire out_roready_1_174; // @[RegisterRouter.scala:87:24]
wire out_roready_1_175; // @[RegisterRouter.scala:87:24]
wire out_roready_1_176; // @[RegisterRouter.scala:87:24]
wire out_roready_1_177; // @[RegisterRouter.scala:87:24]
wire out_roready_1_178; // @[RegisterRouter.scala:87:24]
wire out_roready_1_179; // @[RegisterRouter.scala:87:24]
wire out_roready_1_180; // @[RegisterRouter.scala:87:24]
wire out_roready_1_181; // @[RegisterRouter.scala:87:24]
wire out_roready_1_182; // @[RegisterRouter.scala:87:24]
wire out_roready_1_183; // @[RegisterRouter.scala:87:24]
wire out_roready_1_184; // @[RegisterRouter.scala:87:24]
wire out_roready_1_185; // @[RegisterRouter.scala:87:24]
wire out_roready_1_186; // @[RegisterRouter.scala:87:24]
wire out_roready_1_187; // @[RegisterRouter.scala:87:24]
wire out_roready_1_188; // @[RegisterRouter.scala:87:24]
wire out_roready_1_189; // @[RegisterRouter.scala:87:24]
wire out_roready_1_190; // @[RegisterRouter.scala:87:24]
wire out_roready_1_191; // @[RegisterRouter.scala:87:24]
wire out_roready_1_192; // @[RegisterRouter.scala:87:24]
wire out_roready_1_193; // @[RegisterRouter.scala:87:24]
wire out_roready_1_194; // @[RegisterRouter.scala:87:24]
wire out_roready_1_195; // @[RegisterRouter.scala:87:24]
wire out_roready_1_196; // @[RegisterRouter.scala:87:24]
wire out_roready_1_197; // @[RegisterRouter.scala:87:24]
wire out_roready_1_198; // @[RegisterRouter.scala:87:24]
wire out_roready_1_199; // @[RegisterRouter.scala:87:24]
wire out_roready_1_200; // @[RegisterRouter.scala:87:24]
wire out_roready_1_201; // @[RegisterRouter.scala:87:24]
wire out_roready_1_202; // @[RegisterRouter.scala:87:24]
wire out_roready_1_203; // @[RegisterRouter.scala:87:24]
wire out_roready_1_204; // @[RegisterRouter.scala:87:24]
wire out_roready_1_205; // @[RegisterRouter.scala:87:24]
wire out_roready_1_206; // @[RegisterRouter.scala:87:24]
wire out_roready_1_207; // @[RegisterRouter.scala:87:24]
wire out_roready_1_208; // @[RegisterRouter.scala:87:24]
wire out_roready_1_209; // @[RegisterRouter.scala:87:24]
wire out_roready_1_210; // @[RegisterRouter.scala:87:24]
wire out_roready_1_211; // @[RegisterRouter.scala:87:24]
wire out_roready_1_212; // @[RegisterRouter.scala:87:24]
wire out_roready_1_213; // @[RegisterRouter.scala:87:24]
wire out_roready_1_214; // @[RegisterRouter.scala:87:24]
wire out_roready_1_215; // @[RegisterRouter.scala:87:24]
wire out_roready_1_216; // @[RegisterRouter.scala:87:24]
wire out_roready_1_217; // @[RegisterRouter.scala:87:24]
wire out_roready_1_218; // @[RegisterRouter.scala:87:24]
wire out_roready_1_219; // @[RegisterRouter.scala:87:24]
wire out_roready_1_220; // @[RegisterRouter.scala:87:24]
wire out_roready_1_221; // @[RegisterRouter.scala:87:24]
wire out_roready_1_222; // @[RegisterRouter.scala:87:24]
wire out_roready_1_223; // @[RegisterRouter.scala:87:24]
wire out_roready_1_224; // @[RegisterRouter.scala:87:24]
wire out_roready_1_225; // @[RegisterRouter.scala:87:24]
wire out_roready_1_226; // @[RegisterRouter.scala:87:24]
wire out_roready_1_227; // @[RegisterRouter.scala:87:24]
wire out_roready_1_228; // @[RegisterRouter.scala:87:24]
wire out_roready_1_229; // @[RegisterRouter.scala:87:24]
wire out_roready_1_230; // @[RegisterRouter.scala:87:24]
wire out_roready_1_231; // @[RegisterRouter.scala:87:24]
wire out_roready_1_232; // @[RegisterRouter.scala:87:24]
wire out_roready_1_233; // @[RegisterRouter.scala:87:24]
wire out_roready_1_234; // @[RegisterRouter.scala:87:24]
wire out_roready_1_235; // @[RegisterRouter.scala:87:24]
wire out_roready_1_236; // @[RegisterRouter.scala:87:24]
wire out_roready_1_237; // @[RegisterRouter.scala:87:24]
wire out_roready_1_238; // @[RegisterRouter.scala:87:24]
wire out_roready_1_239; // @[RegisterRouter.scala:87:24]
wire out_roready_1_240; // @[RegisterRouter.scala:87:24]
wire out_roready_1_241; // @[RegisterRouter.scala:87:24]
wire out_roready_1_242; // @[RegisterRouter.scala:87:24]
wire out_roready_1_243; // @[RegisterRouter.scala:87:24]
wire out_roready_1_244; // @[RegisterRouter.scala:87:24]
wire out_roready_1_245; // @[RegisterRouter.scala:87:24]
wire out_roready_1_246; // @[RegisterRouter.scala:87:24]
wire out_roready_1_247; // @[RegisterRouter.scala:87:24]
wire out_roready_1_248; // @[RegisterRouter.scala:87:24]
wire out_roready_1_249; // @[RegisterRouter.scala:87:24]
wire out_roready_1_250; // @[RegisterRouter.scala:87:24]
wire out_roready_1_251; // @[RegisterRouter.scala:87:24]
wire out_roready_1_252; // @[RegisterRouter.scala:87:24]
wire out_roready_1_253; // @[RegisterRouter.scala:87:24]
wire out_roready_1_254; // @[RegisterRouter.scala:87:24]
wire out_roready_1_255; // @[RegisterRouter.scala:87:24]
wire out_roready_1_256; // @[RegisterRouter.scala:87:24]
wire out_roready_1_257; // @[RegisterRouter.scala:87:24]
wire out_roready_1_258; // @[RegisterRouter.scala:87:24]
wire out_roready_1_259; // @[RegisterRouter.scala:87:24]
wire out_roready_1_260; // @[RegisterRouter.scala:87:24]
wire out_roready_1_261; // @[RegisterRouter.scala:87:24]
wire out_roready_1_262; // @[RegisterRouter.scala:87:24]
wire out_roready_1_263; // @[RegisterRouter.scala:87:24]
wire out_roready_1_264; // @[RegisterRouter.scala:87:24]
wire out_roready_1_265; // @[RegisterRouter.scala:87:24]
wire out_roready_1_266; // @[RegisterRouter.scala:87:24]
wire out_roready_1_267; // @[RegisterRouter.scala:87:24]
wire out_roready_1_268; // @[RegisterRouter.scala:87:24]
wire out_roready_1_269; // @[RegisterRouter.scala:87:24]
wire out_roready_1_270; // @[RegisterRouter.scala:87:24]
wire out_roready_1_271; // @[RegisterRouter.scala:87:24]
wire out_roready_1_272; // @[RegisterRouter.scala:87:24]
wire out_roready_1_273; // @[RegisterRouter.scala:87:24]
wire out_roready_1_274; // @[RegisterRouter.scala:87:24]
wire out_roready_1_275; // @[RegisterRouter.scala:87:24]
wire out_roready_1_276; // @[RegisterRouter.scala:87:24]
wire out_roready_1_277; // @[RegisterRouter.scala:87:24]
wire out_roready_1_278; // @[RegisterRouter.scala:87:24]
wire out_roready_1_279; // @[RegisterRouter.scala:87:24]
wire out_roready_1_280; // @[RegisterRouter.scala:87:24]
wire out_roready_1_281; // @[RegisterRouter.scala:87:24]
wire out_roready_1_282; // @[RegisterRouter.scala:87:24]
wire out_roready_1_283; // @[RegisterRouter.scala:87:24]
wire out_roready_1_284; // @[RegisterRouter.scala:87:24]
wire out_roready_1_285; // @[RegisterRouter.scala:87:24]
wire out_roready_1_286; // @[RegisterRouter.scala:87:24]
wire out_roready_1_287; // @[RegisterRouter.scala:87:24]
wire out_roready_1_288; // @[RegisterRouter.scala:87:24]
wire out_roready_1_289; // @[RegisterRouter.scala:87:24]
wire out_roready_1_290; // @[RegisterRouter.scala:87:24]
wire out_roready_1_291; // @[RegisterRouter.scala:87:24]
wire out_roready_1_292; // @[RegisterRouter.scala:87:24]
wire out_roready_1_293; // @[RegisterRouter.scala:87:24]
wire out_roready_1_294; // @[RegisterRouter.scala:87:24]
wire out_roready_1_295; // @[RegisterRouter.scala:87:24]
wire out_roready_1_296; // @[RegisterRouter.scala:87:24]
wire out_roready_1_297; // @[RegisterRouter.scala:87:24]
wire out_roready_1_298; // @[RegisterRouter.scala:87:24]
wire out_roready_1_299; // @[RegisterRouter.scala:87:24]
wire out_roready_1_300; // @[RegisterRouter.scala:87:24]
wire out_roready_1_301; // @[RegisterRouter.scala:87:24]
wire out_roready_1_302; // @[RegisterRouter.scala:87:24]
wire out_roready_1_303; // @[RegisterRouter.scala:87:24]
wire out_roready_1_304; // @[RegisterRouter.scala:87:24]
wire out_roready_1_305; // @[RegisterRouter.scala:87:24]
wire out_roready_1_306; // @[RegisterRouter.scala:87:24]
wire out_roready_1_307; // @[RegisterRouter.scala:87:24]
wire out_roready_1_308; // @[RegisterRouter.scala:87:24]
wire out_roready_1_309; // @[RegisterRouter.scala:87:24]
wire out_roready_1_310; // @[RegisterRouter.scala:87:24]
wire out_roready_1_311; // @[RegisterRouter.scala:87:24]
wire out_roready_1_312; // @[RegisterRouter.scala:87:24]
wire out_roready_1_313; // @[RegisterRouter.scala:87:24]
wire out_roready_1_314; // @[RegisterRouter.scala:87:24]
wire out_roready_1_315; // @[RegisterRouter.scala:87:24]
wire out_roready_1_316; // @[RegisterRouter.scala:87:24]
wire out_roready_1_317; // @[RegisterRouter.scala:87:24]
wire out_roready_1_318; // @[RegisterRouter.scala:87:24]
wire out_roready_1_319; // @[RegisterRouter.scala:87:24]
wire out_roready_1_320; // @[RegisterRouter.scala:87:24]
wire out_roready_1_321; // @[RegisterRouter.scala:87:24]
wire out_roready_1_322; // @[RegisterRouter.scala:87:24]
wire out_roready_1_323; // @[RegisterRouter.scala:87:24]
wire out_roready_1_324; // @[RegisterRouter.scala:87:24]
wire out_roready_1_325; // @[RegisterRouter.scala:87:24]
wire out_roready_1_326; // @[RegisterRouter.scala:87:24]
wire out_roready_1_327; // @[RegisterRouter.scala:87:24]
wire out_roready_1_328; // @[RegisterRouter.scala:87:24]
wire out_roready_1_329; // @[RegisterRouter.scala:87:24]
wire out_roready_1_330; // @[RegisterRouter.scala:87:24]
wire out_roready_1_331; // @[RegisterRouter.scala:87:24]
wire out_roready_1_332; // @[RegisterRouter.scala:87:24]
wire out_roready_1_333; // @[RegisterRouter.scala:87:24]
wire out_roready_1_334; // @[RegisterRouter.scala:87:24]
wire out_roready_1_335; // @[RegisterRouter.scala:87:24]
wire out_roready_1_336; // @[RegisterRouter.scala:87:24]
wire out_roready_1_337; // @[RegisterRouter.scala:87:24]
wire out_roready_1_338; // @[RegisterRouter.scala:87:24]
wire out_roready_1_339; // @[RegisterRouter.scala:87:24]
wire out_roready_1_340; // @[RegisterRouter.scala:87:24]
wire out_roready_1_341; // @[RegisterRouter.scala:87:24]
wire out_roready_1_342; // @[RegisterRouter.scala:87:24]
wire out_roready_1_343; // @[RegisterRouter.scala:87:24]
wire out_roready_1_344; // @[RegisterRouter.scala:87:24]
wire out_roready_1_345; // @[RegisterRouter.scala:87:24]
wire out_roready_1_346; // @[RegisterRouter.scala:87:24]
wire out_roready_1_347; // @[RegisterRouter.scala:87:24]
wire out_roready_1_348; // @[RegisterRouter.scala:87:24]
wire out_roready_1_349; // @[RegisterRouter.scala:87:24]
wire out_roready_1_350; // @[RegisterRouter.scala:87:24]
wire out_roready_1_351; // @[RegisterRouter.scala:87:24]
wire out_roready_1_352; // @[RegisterRouter.scala:87:24]
wire out_roready_1_353; // @[RegisterRouter.scala:87:24]
wire out_roready_1_354; // @[RegisterRouter.scala:87:24]
wire out_roready_1_355; // @[RegisterRouter.scala:87:24]
wire out_roready_1_356; // @[RegisterRouter.scala:87:24]
wire out_roready_1_357; // @[RegisterRouter.scala:87:24]
wire out_roready_1_358; // @[RegisterRouter.scala:87:24]
wire out_roready_1_359; // @[RegisterRouter.scala:87:24]
wire out_roready_1_360; // @[RegisterRouter.scala:87:24]
wire out_roready_1_361; // @[RegisterRouter.scala:87:24]
wire out_roready_1_362; // @[RegisterRouter.scala:87:24]
wire out_roready_1_363; // @[RegisterRouter.scala:87:24]
wire out_roready_1_364; // @[RegisterRouter.scala:87:24]
wire out_roready_1_365; // @[RegisterRouter.scala:87:24]
wire out_roready_1_366; // @[RegisterRouter.scala:87:24]
wire out_roready_1_367; // @[RegisterRouter.scala:87:24]
wire out_roready_1_368; // @[RegisterRouter.scala:87:24]
wire out_roready_1_369; // @[RegisterRouter.scala:87:24]
wire out_roready_1_370; // @[RegisterRouter.scala:87:24]
wire out_roready_1_371; // @[RegisterRouter.scala:87:24]
wire out_roready_1_372; // @[RegisterRouter.scala:87:24]
wire out_roready_1_373; // @[RegisterRouter.scala:87:24]
wire out_roready_1_374; // @[RegisterRouter.scala:87:24]
wire out_roready_1_375; // @[RegisterRouter.scala:87:24]
wire out_roready_1_376; // @[RegisterRouter.scala:87:24]
wire out_roready_1_377; // @[RegisterRouter.scala:87:24]
wire out_roready_1_378; // @[RegisterRouter.scala:87:24]
wire out_roready_1_379; // @[RegisterRouter.scala:87:24]
wire out_roready_1_380; // @[RegisterRouter.scala:87:24]
wire out_roready_1_381; // @[RegisterRouter.scala:87:24]
wire out_roready_1_382; // @[RegisterRouter.scala:87:24]
wire out_roready_1_383; // @[RegisterRouter.scala:87:24]
wire out_roready_1_384; // @[RegisterRouter.scala:87:24]
wire out_roready_1_385; // @[RegisterRouter.scala:87:24]
wire out_roready_1_386; // @[RegisterRouter.scala:87:24]
wire out_roready_1_387; // @[RegisterRouter.scala:87:24]
wire out_roready_1_388; // @[RegisterRouter.scala:87:24]
wire out_roready_1_389; // @[RegisterRouter.scala:87:24]
wire out_roready_1_390; // @[RegisterRouter.scala:87:24]
wire out_roready_1_391; // @[RegisterRouter.scala:87:24]
wire out_roready_1_392; // @[RegisterRouter.scala:87:24]
wire out_roready_1_393; // @[RegisterRouter.scala:87:24]
wire out_roready_1_394; // @[RegisterRouter.scala:87:24]
wire out_roready_1_395; // @[RegisterRouter.scala:87:24]
wire out_roready_1_396; // @[RegisterRouter.scala:87:24]
wire out_roready_1_397; // @[RegisterRouter.scala:87:24]
wire out_roready_1_398; // @[RegisterRouter.scala:87:24]
wire out_roready_1_399; // @[RegisterRouter.scala:87:24]
wire out_roready_1_400; // @[RegisterRouter.scala:87:24]
wire out_roready_1_401; // @[RegisterRouter.scala:87:24]
wire out_roready_1_402; // @[RegisterRouter.scala:87:24]
wire out_roready_1_403; // @[RegisterRouter.scala:87:24]
wire out_roready_1_404; // @[RegisterRouter.scala:87:24]
wire out_roready_1_405; // @[RegisterRouter.scala:87:24]
wire out_roready_1_406; // @[RegisterRouter.scala:87:24]
wire out_roready_1_407; // @[RegisterRouter.scala:87:24]
wire out_roready_1_408; // @[RegisterRouter.scala:87:24]
wire out_roready_1_409; // @[RegisterRouter.scala:87:24]
wire out_roready_1_410; // @[RegisterRouter.scala:87:24]
wire out_roready_1_411; // @[RegisterRouter.scala:87:24]
wire out_roready_1_412; // @[RegisterRouter.scala:87:24]
wire out_roready_1_413; // @[RegisterRouter.scala:87:24]
wire out_roready_1_414; // @[RegisterRouter.scala:87:24]
wire out_roready_1_415; // @[RegisterRouter.scala:87:24]
wire out_roready_1_416; // @[RegisterRouter.scala:87:24]
wire out_roready_1_417; // @[RegisterRouter.scala:87:24]
wire out_roready_1_418; // @[RegisterRouter.scala:87:24]
wire out_roready_1_419; // @[RegisterRouter.scala:87:24]
wire out_roready_1_420; // @[RegisterRouter.scala:87:24]
wire out_roready_1_421; // @[RegisterRouter.scala:87:24]
wire out_roready_1_422; // @[RegisterRouter.scala:87:24]
wire out_roready_1_423; // @[RegisterRouter.scala:87:24]
wire out_roready_1_424; // @[RegisterRouter.scala:87:24]
wire out_roready_1_425; // @[RegisterRouter.scala:87:24]
wire out_roready_1_426; // @[RegisterRouter.scala:87:24]
wire out_roready_1_427; // @[RegisterRouter.scala:87:24]
wire out_roready_1_428; // @[RegisterRouter.scala:87:24]
wire out_roready_1_429; // @[RegisterRouter.scala:87:24]
wire out_roready_1_430; // @[RegisterRouter.scala:87:24]
wire out_roready_1_431; // @[RegisterRouter.scala:87:24]
wire out_roready_1_432; // @[RegisterRouter.scala:87:24]
wire out_roready_1_433; // @[RegisterRouter.scala:87:24]
wire out_roready_1_434; // @[RegisterRouter.scala:87:24]
wire out_roready_1_435; // @[RegisterRouter.scala:87:24]
wire out_roready_1_436; // @[RegisterRouter.scala:87:24]
wire out_roready_1_437; // @[RegisterRouter.scala:87:24]
wire out_roready_1_438; // @[RegisterRouter.scala:87:24]
wire out_roready_1_439; // @[RegisterRouter.scala:87:24]
wire out_roready_1_440; // @[RegisterRouter.scala:87:24]
wire out_roready_1_441; // @[RegisterRouter.scala:87:24]
wire out_roready_1_442; // @[RegisterRouter.scala:87:24]
wire out_roready_1_443; // @[RegisterRouter.scala:87:24]
wire out_roready_1_444; // @[RegisterRouter.scala:87:24]
wire out_roready_1_445; // @[RegisterRouter.scala:87:24]
wire out_roready_1_446; // @[RegisterRouter.scala:87:24]
wire out_roready_1_447; // @[RegisterRouter.scala:87:24]
wire out_roready_1_448; // @[RegisterRouter.scala:87:24]
wire out_roready_1_449; // @[RegisterRouter.scala:87:24]
wire out_roready_1_450; // @[RegisterRouter.scala:87:24]
wire out_roready_1_451; // @[RegisterRouter.scala:87:24]
wire out_roready_1_452; // @[RegisterRouter.scala:87:24]
wire out_roready_1_453; // @[RegisterRouter.scala:87:24]
wire out_roready_1_454; // @[RegisterRouter.scala:87:24]
wire out_roready_1_455; // @[RegisterRouter.scala:87:24]
wire out_roready_1_456; // @[RegisterRouter.scala:87:24]
wire out_roready_1_457; // @[RegisterRouter.scala:87:24]
wire out_roready_1_458; // @[RegisterRouter.scala:87:24]
wire out_roready_1_459; // @[RegisterRouter.scala:87:24]
wire out_roready_1_460; // @[RegisterRouter.scala:87:24]
wire out_roready_1_461; // @[RegisterRouter.scala:87:24]
wire out_roready_1_462; // @[RegisterRouter.scala:87:24]
wire out_roready_1_463; // @[RegisterRouter.scala:87:24]
wire out_roready_1_464; // @[RegisterRouter.scala:87:24]
wire out_roready_1_465; // @[RegisterRouter.scala:87:24]
wire out_roready_1_466; // @[RegisterRouter.scala:87:24]
wire out_roready_1_467; // @[RegisterRouter.scala:87:24]
wire out_roready_1_468; // @[RegisterRouter.scala:87:24]
wire out_roready_1_469; // @[RegisterRouter.scala:87:24]
wire out_roready_1_470; // @[RegisterRouter.scala:87:24]
wire out_roready_1_471; // @[RegisterRouter.scala:87:24]
wire out_roready_1_472; // @[RegisterRouter.scala:87:24]
wire out_roready_1_473; // @[RegisterRouter.scala:87:24]
wire out_roready_1_474; // @[RegisterRouter.scala:87:24]
wire out_roready_1_475; // @[RegisterRouter.scala:87:24]
wire out_roready_1_476; // @[RegisterRouter.scala:87:24]
wire out_roready_1_477; // @[RegisterRouter.scala:87:24]
wire out_roready_1_478; // @[RegisterRouter.scala:87:24]
wire out_roready_1_479; // @[RegisterRouter.scala:87:24]
wire out_roready_1_480; // @[RegisterRouter.scala:87:24]
wire out_roready_1_481; // @[RegisterRouter.scala:87:24]
wire out_roready_1_482; // @[RegisterRouter.scala:87:24]
wire out_roready_1_483; // @[RegisterRouter.scala:87:24]
wire out_roready_1_484; // @[RegisterRouter.scala:87:24]
wire out_roready_1_485; // @[RegisterRouter.scala:87:24]
wire out_roready_1_486; // @[RegisterRouter.scala:87:24]
wire out_roready_1_487; // @[RegisterRouter.scala:87:24]
wire out_roready_1_488; // @[RegisterRouter.scala:87:24]
wire out_roready_1_489; // @[RegisterRouter.scala:87:24]
wire out_roready_1_490; // @[RegisterRouter.scala:87:24]
wire out_roready_1_491; // @[RegisterRouter.scala:87:24]
wire out_roready_1_492; // @[RegisterRouter.scala:87:24]
wire out_roready_1_493; // @[RegisterRouter.scala:87:24]
wire out_roready_1_494; // @[RegisterRouter.scala:87:24]
wire out_roready_1_495; // @[RegisterRouter.scala:87:24]
wire out_roready_1_496; // @[RegisterRouter.scala:87:24]
wire out_roready_1_497; // @[RegisterRouter.scala:87:24]
wire out_roready_1_498; // @[RegisterRouter.scala:87:24]
wire out_roready_1_499; // @[RegisterRouter.scala:87:24]
wire out_roready_1_500; // @[RegisterRouter.scala:87:24]
wire out_roready_1_501; // @[RegisterRouter.scala:87:24]
wire out_roready_1_502; // @[RegisterRouter.scala:87:24]
wire out_roready_1_503; // @[RegisterRouter.scala:87:24]
wire out_roready_1_504; // @[RegisterRouter.scala:87:24]
wire out_roready_1_505; // @[RegisterRouter.scala:87:24]
wire out_roready_1_506; // @[RegisterRouter.scala:87:24]
wire out_roready_1_507; // @[RegisterRouter.scala:87:24]
wire out_roready_1_508; // @[RegisterRouter.scala:87:24]
wire out_roready_1_509; // @[RegisterRouter.scala:87:24]
wire out_roready_1_510; // @[RegisterRouter.scala:87:24]
wire out_roready_1_511; // @[RegisterRouter.scala:87:24]
wire out_roready_1_512; // @[RegisterRouter.scala:87:24]
wire out_roready_1_513; // @[RegisterRouter.scala:87:24]
wire out_roready_1_514; // @[RegisterRouter.scala:87:24]
wire out_roready_1_515; // @[RegisterRouter.scala:87:24]
wire out_roready_1_516; // @[RegisterRouter.scala:87:24]
wire out_roready_1_517; // @[RegisterRouter.scala:87:24]
wire out_roready_1_518; // @[RegisterRouter.scala:87:24]
wire out_roready_1_519; // @[RegisterRouter.scala:87:24]
wire out_roready_1_520; // @[RegisterRouter.scala:87:24]
wire out_roready_1_521; // @[RegisterRouter.scala:87:24]
wire out_roready_1_522; // @[RegisterRouter.scala:87:24]
wire out_roready_1_523; // @[RegisterRouter.scala:87:24]
wire out_roready_1_524; // @[RegisterRouter.scala:87:24]
wire out_roready_1_525; // @[RegisterRouter.scala:87:24]
wire out_roready_1_526; // @[RegisterRouter.scala:87:24]
wire out_roready_1_527; // @[RegisterRouter.scala:87:24]
wire out_roready_1_528; // @[RegisterRouter.scala:87:24]
wire out_roready_1_529; // @[RegisterRouter.scala:87:24]
wire out_roready_1_530; // @[RegisterRouter.scala:87:24]
wire out_roready_1_531; // @[RegisterRouter.scala:87:24]
wire out_roready_1_532; // @[RegisterRouter.scala:87:24]
wire out_roready_1_533; // @[RegisterRouter.scala:87:24]
wire out_roready_1_534; // @[RegisterRouter.scala:87:24]
wire out_roready_1_535; // @[RegisterRouter.scala:87:24]
wire out_roready_1_536; // @[RegisterRouter.scala:87:24]
wire out_roready_1_537; // @[RegisterRouter.scala:87:24]
wire out_roready_1_538; // @[RegisterRouter.scala:87:24]
wire out_roready_1_539; // @[RegisterRouter.scala:87:24]
wire out_roready_1_540; // @[RegisterRouter.scala:87:24]
wire out_roready_1_541; // @[RegisterRouter.scala:87:24]
wire out_roready_1_542; // @[RegisterRouter.scala:87:24]
wire out_roready_1_543; // @[RegisterRouter.scala:87:24]
wire out_roready_1_544; // @[RegisterRouter.scala:87:24]
wire out_roready_1_545; // @[RegisterRouter.scala:87:24]
wire out_roready_1_546; // @[RegisterRouter.scala:87:24]
wire out_roready_1_547; // @[RegisterRouter.scala:87:24]
wire out_roready_1_548; // @[RegisterRouter.scala:87:24]
wire out_roready_1_549; // @[RegisterRouter.scala:87:24]
wire out_roready_1_550; // @[RegisterRouter.scala:87:24]
wire out_roready_1_551; // @[RegisterRouter.scala:87:24]
wire out_roready_1_552; // @[RegisterRouter.scala:87:24]
wire out_roready_1_553; // @[RegisterRouter.scala:87:24]
wire out_roready_1_554; // @[RegisterRouter.scala:87:24]
wire out_roready_1_555; // @[RegisterRouter.scala:87:24]
wire out_roready_1_556; // @[RegisterRouter.scala:87:24]
wire out_roready_1_557; // @[RegisterRouter.scala:87:24]
wire out_roready_1_558; // @[RegisterRouter.scala:87:24]
wire out_roready_1_559; // @[RegisterRouter.scala:87:24]
wire out_roready_1_560; // @[RegisterRouter.scala:87:24]
wire out_roready_1_561; // @[RegisterRouter.scala:87:24]
wire out_roready_1_562; // @[RegisterRouter.scala:87:24]
wire out_roready_1_563; // @[RegisterRouter.scala:87:24]
wire out_roready_1_564; // @[RegisterRouter.scala:87:24]
wire out_roready_1_565; // @[RegisterRouter.scala:87:24]
wire out_roready_1_566; // @[RegisterRouter.scala:87:24]
wire out_roready_1_567; // @[RegisterRouter.scala:87:24]
wire out_roready_1_568; // @[RegisterRouter.scala:87:24]
wire out_roready_1_569; // @[RegisterRouter.scala:87:24]
wire out_roready_1_570; // @[RegisterRouter.scala:87:24]
wire out_roready_1_571; // @[RegisterRouter.scala:87:24]
wire out_roready_1_572; // @[RegisterRouter.scala:87:24]
wire out_roready_1_573; // @[RegisterRouter.scala:87:24]
wire out_roready_1_574; // @[RegisterRouter.scala:87:24]
wire out_roready_1_575; // @[RegisterRouter.scala:87:24]
wire out_roready_1_576; // @[RegisterRouter.scala:87:24]
wire out_roready_1_577; // @[RegisterRouter.scala:87:24]
wire out_roready_1_578; // @[RegisterRouter.scala:87:24]
wire out_roready_1_579; // @[RegisterRouter.scala:87:24]
wire out_roready_1_580; // @[RegisterRouter.scala:87:24]
wire out_roready_1_581; // @[RegisterRouter.scala:87:24]
wire out_roready_1_582; // @[RegisterRouter.scala:87:24]
wire out_roready_1_583; // @[RegisterRouter.scala:87:24]
wire out_roready_1_584; // @[RegisterRouter.scala:87:24]
wire out_roready_1_585; // @[RegisterRouter.scala:87:24]
wire out_roready_1_586; // @[RegisterRouter.scala:87:24]
wire out_roready_1_587; // @[RegisterRouter.scala:87:24]
wire out_roready_1_588; // @[RegisterRouter.scala:87:24]
wire out_roready_1_589; // @[RegisterRouter.scala:87:24]
wire out_roready_1_590; // @[RegisterRouter.scala:87:24]
wire out_roready_1_591; // @[RegisterRouter.scala:87:24]
wire out_roready_1_592; // @[RegisterRouter.scala:87:24]
wire out_roready_1_593; // @[RegisterRouter.scala:87:24]
wire out_roready_1_594; // @[RegisterRouter.scala:87:24]
wire out_roready_1_595; // @[RegisterRouter.scala:87:24]
wire out_roready_1_596; // @[RegisterRouter.scala:87:24]
wire out_roready_1_597; // @[RegisterRouter.scala:87:24]
wire out_roready_1_598; // @[RegisterRouter.scala:87:24]
wire out_roready_1_599; // @[RegisterRouter.scala:87:24]
wire out_roready_1_600; // @[RegisterRouter.scala:87:24]
wire out_roready_1_601; // @[RegisterRouter.scala:87:24]
wire out_roready_1_602; // @[RegisterRouter.scala:87:24]
wire out_roready_1_603; // @[RegisterRouter.scala:87:24]
wire out_roready_1_604; // @[RegisterRouter.scala:87:24]
wire out_roready_1_605; // @[RegisterRouter.scala:87:24]
wire out_roready_1_606; // @[RegisterRouter.scala:87:24]
wire out_roready_1_607; // @[RegisterRouter.scala:87:24]
wire out_roready_1_608; // @[RegisterRouter.scala:87:24]
wire out_roready_1_609; // @[RegisterRouter.scala:87:24]
wire out_roready_1_610; // @[RegisterRouter.scala:87:24]
wire out_roready_1_611; // @[RegisterRouter.scala:87:24]
wire out_roready_1_612; // @[RegisterRouter.scala:87:24]
wire out_roready_1_613; // @[RegisterRouter.scala:87:24]
wire out_roready_1_614; // @[RegisterRouter.scala:87:24]
wire out_roready_1_615; // @[RegisterRouter.scala:87:24]
wire out_roready_1_616; // @[RegisterRouter.scala:87:24]
wire out_roready_1_617; // @[RegisterRouter.scala:87:24]
wire out_roready_1_618; // @[RegisterRouter.scala:87:24]
wire out_roready_1_619; // @[RegisterRouter.scala:87:24]
wire out_roready_1_620; // @[RegisterRouter.scala:87:24]
wire out_roready_1_621; // @[RegisterRouter.scala:87:24]
wire out_roready_1_622; // @[RegisterRouter.scala:87:24]
wire out_roready_1_623; // @[RegisterRouter.scala:87:24]
wire out_roready_1_624; // @[RegisterRouter.scala:87:24]
wire out_roready_1_625; // @[RegisterRouter.scala:87:24]
wire out_roready_1_626; // @[RegisterRouter.scala:87:24]
wire out_roready_1_627; // @[RegisterRouter.scala:87:24]
wire out_roready_1_628; // @[RegisterRouter.scala:87:24]
wire out_roready_1_629; // @[RegisterRouter.scala:87:24]
wire out_roready_1_630; // @[RegisterRouter.scala:87:24]
wire out_roready_1_631; // @[RegisterRouter.scala:87:24]
wire out_roready_1_632; // @[RegisterRouter.scala:87:24]
wire out_roready_1_633; // @[RegisterRouter.scala:87:24]
wire out_roready_1_634; // @[RegisterRouter.scala:87:24]
wire out_roready_1_635; // @[RegisterRouter.scala:87:24]
wire out_roready_1_636; // @[RegisterRouter.scala:87:24]
wire out_roready_1_637; // @[RegisterRouter.scala:87:24]
wire out_roready_1_638; // @[RegisterRouter.scala:87:24]
wire out_roready_1_639; // @[RegisterRouter.scala:87:24]
wire out_roready_1_640; // @[RegisterRouter.scala:87:24]
wire out_roready_1_641; // @[RegisterRouter.scala:87:24]
wire out_roready_1_642; // @[RegisterRouter.scala:87:24]
wire out_roready_1_643; // @[RegisterRouter.scala:87:24]
wire out_roready_1_644; // @[RegisterRouter.scala:87:24]
wire out_roready_1_645; // @[RegisterRouter.scala:87:24]
wire out_roready_1_646; // @[RegisterRouter.scala:87:24]
wire out_roready_1_647; // @[RegisterRouter.scala:87:24]
wire out_roready_1_648; // @[RegisterRouter.scala:87:24]
wire out_roready_1_649; // @[RegisterRouter.scala:87:24]
wire out_roready_1_650; // @[RegisterRouter.scala:87:24]
wire out_roready_1_651; // @[RegisterRouter.scala:87:24]
wire out_roready_1_652; // @[RegisterRouter.scala:87:24]
wire out_roready_1_653; // @[RegisterRouter.scala:87:24]
wire out_roready_1_654; // @[RegisterRouter.scala:87:24]
wire out_roready_1_655; // @[RegisterRouter.scala:87:24]
wire out_roready_1_656; // @[RegisterRouter.scala:87:24]
wire out_roready_1_657; // @[RegisterRouter.scala:87:24]
wire out_roready_1_658; // @[RegisterRouter.scala:87:24]
wire out_roready_1_659; // @[RegisterRouter.scala:87:24]
wire out_roready_1_660; // @[RegisterRouter.scala:87:24]
wire out_roready_1_661; // @[RegisterRouter.scala:87:24]
wire out_roready_1_662; // @[RegisterRouter.scala:87:24]
wire out_roready_1_663; // @[RegisterRouter.scala:87:24]
wire out_roready_1_664; // @[RegisterRouter.scala:87:24]
wire out_roready_1_665; // @[RegisterRouter.scala:87:24]
wire out_roready_1_666; // @[RegisterRouter.scala:87:24]
wire out_roready_1_667; // @[RegisterRouter.scala:87:24]
wire out_roready_1_668; // @[RegisterRouter.scala:87:24]
wire out_roready_1_669; // @[RegisterRouter.scala:87:24]
wire out_roready_1_670; // @[RegisterRouter.scala:87:24]
wire out_roready_1_671; // @[RegisterRouter.scala:87:24]
wire out_roready_1_672; // @[RegisterRouter.scala:87:24]
wire out_roready_1_673; // @[RegisterRouter.scala:87:24]
wire out_roready_1_674; // @[RegisterRouter.scala:87:24]
wire out_roready_1_675; // @[RegisterRouter.scala:87:24]
wire out_roready_1_676; // @[RegisterRouter.scala:87:24]
wire out_roready_1_677; // @[RegisterRouter.scala:87:24]
wire out_roready_1_678; // @[RegisterRouter.scala:87:24]
wire out_roready_1_679; // @[RegisterRouter.scala:87:24]
wire out_roready_1_680; // @[RegisterRouter.scala:87:24]
wire out_roready_1_681; // @[RegisterRouter.scala:87:24]
wire out_roready_1_682; // @[RegisterRouter.scala:87:24]
wire out_roready_1_683; // @[RegisterRouter.scala:87:24]
wire out_roready_1_684; // @[RegisterRouter.scala:87:24]
wire out_roready_1_685; // @[RegisterRouter.scala:87:24]
wire out_roready_1_686; // @[RegisterRouter.scala:87:24]
wire out_roready_1_687; // @[RegisterRouter.scala:87:24]
wire out_roready_1_688; // @[RegisterRouter.scala:87:24]
wire out_roready_1_689; // @[RegisterRouter.scala:87:24]
wire out_roready_1_690; // @[RegisterRouter.scala:87:24]
wire out_roready_1_691; // @[RegisterRouter.scala:87:24]
wire out_roready_1_692; // @[RegisterRouter.scala:87:24]
wire out_roready_1_693; // @[RegisterRouter.scala:87:24]
wire out_roready_1_694; // @[RegisterRouter.scala:87:24]
wire out_roready_1_695; // @[RegisterRouter.scala:87:24]
wire out_roready_1_696; // @[RegisterRouter.scala:87:24]
wire out_roready_1_697; // @[RegisterRouter.scala:87:24]
wire out_roready_1_698; // @[RegisterRouter.scala:87:24]
wire out_roready_1_699; // @[RegisterRouter.scala:87:24]
wire out_roready_1_700; // @[RegisterRouter.scala:87:24]
wire out_roready_1_701; // @[RegisterRouter.scala:87:24]
wire out_roready_1_702; // @[RegisterRouter.scala:87:24]
wire out_roready_1_703; // @[RegisterRouter.scala:87:24]
wire out_roready_1_704; // @[RegisterRouter.scala:87:24]
wire out_roready_1_705; // @[RegisterRouter.scala:87:24]
wire out_roready_1_706; // @[RegisterRouter.scala:87:24]
wire out_roready_1_707; // @[RegisterRouter.scala:87:24]
wire out_roready_1_708; // @[RegisterRouter.scala:87:24]
wire out_roready_1_709; // @[RegisterRouter.scala:87:24]
wire out_roready_1_710; // @[RegisterRouter.scala:87:24]
wire out_roready_1_711; // @[RegisterRouter.scala:87:24]
wire out_roready_1_712; // @[RegisterRouter.scala:87:24]
wire out_roready_1_713; // @[RegisterRouter.scala:87:24]
wire out_roready_1_714; // @[RegisterRouter.scala:87:24]
wire out_roready_1_715; // @[RegisterRouter.scala:87:24]
wire out_roready_1_716; // @[RegisterRouter.scala:87:24]
wire out_roready_1_717; // @[RegisterRouter.scala:87:24]
wire out_roready_1_718; // @[RegisterRouter.scala:87:24]
wire out_roready_1_719; // @[RegisterRouter.scala:87:24]
wire out_roready_1_720; // @[RegisterRouter.scala:87:24]
wire out_roready_1_721; // @[RegisterRouter.scala:87:24]
wire out_roready_1_722; // @[RegisterRouter.scala:87:24]
wire out_roready_1_723; // @[RegisterRouter.scala:87:24]
wire out_roready_1_724; // @[RegisterRouter.scala:87:24]
wire out_roready_1_725; // @[RegisterRouter.scala:87:24]
wire out_roready_1_726; // @[RegisterRouter.scala:87:24]
wire out_roready_1_727; // @[RegisterRouter.scala:87:24]
wire out_roready_1_728; // @[RegisterRouter.scala:87:24]
wire out_roready_1_729; // @[RegisterRouter.scala:87:24]
wire out_roready_1_730; // @[RegisterRouter.scala:87:24]
wire out_roready_1_731; // @[RegisterRouter.scala:87:24]
wire out_roready_1_732; // @[RegisterRouter.scala:87:24]
wire out_roready_1_733; // @[RegisterRouter.scala:87:24]
wire out_roready_1_734; // @[RegisterRouter.scala:87:24]
wire out_roready_1_735; // @[RegisterRouter.scala:87:24]
wire out_roready_1_736; // @[RegisterRouter.scala:87:24]
wire out_roready_1_737; // @[RegisterRouter.scala:87:24]
wire out_roready_1_738; // @[RegisterRouter.scala:87:24]
wire out_roready_1_739; // @[RegisterRouter.scala:87:24]
wire out_roready_1_740; // @[RegisterRouter.scala:87:24]
wire out_roready_1_741; // @[RegisterRouter.scala:87:24]
wire out_roready_1_742; // @[RegisterRouter.scala:87:24]
wire out_roready_1_743; // @[RegisterRouter.scala:87:24]
wire out_roready_1_744; // @[RegisterRouter.scala:87:24]
wire out_roready_1_745; // @[RegisterRouter.scala:87:24]
wire out_roready_1_746; // @[RegisterRouter.scala:87:24]
wire out_roready_1_747; // @[RegisterRouter.scala:87:24]
wire out_roready_1_748; // @[RegisterRouter.scala:87:24]
wire out_roready_1_749; // @[RegisterRouter.scala:87:24]
wire out_roready_1_750; // @[RegisterRouter.scala:87:24]
wire out_roready_1_751; // @[RegisterRouter.scala:87:24]
wire out_roready_1_752; // @[RegisterRouter.scala:87:24]
wire out_roready_1_753; // @[RegisterRouter.scala:87:24]
wire out_roready_1_754; // @[RegisterRouter.scala:87:24]
wire out_roready_1_755; // @[RegisterRouter.scala:87:24]
wire out_roready_1_756; // @[RegisterRouter.scala:87:24]
wire out_roready_1_757; // @[RegisterRouter.scala:87:24]
wire out_roready_1_758; // @[RegisterRouter.scala:87:24]
wire out_roready_1_759; // @[RegisterRouter.scala:87:24]
wire out_roready_1_760; // @[RegisterRouter.scala:87:24]
wire out_roready_1_761; // @[RegisterRouter.scala:87:24]
wire out_roready_1_762; // @[RegisterRouter.scala:87:24]
wire out_roready_1_763; // @[RegisterRouter.scala:87:24]
wire out_roready_1_764; // @[RegisterRouter.scala:87:24]
wire out_roready_1_765; // @[RegisterRouter.scala:87:24]
wire out_roready_1_766; // @[RegisterRouter.scala:87:24]
wire out_roready_1_767; // @[RegisterRouter.scala:87:24]
wire out_roready_1_768; // @[RegisterRouter.scala:87:24]
wire out_roready_1_769; // @[RegisterRouter.scala:87:24]
wire out_roready_1_770; // @[RegisterRouter.scala:87:24]
wire out_roready_1_771; // @[RegisterRouter.scala:87:24]
wire out_roready_1_772; // @[RegisterRouter.scala:87:24]
wire out_roready_1_773; // @[RegisterRouter.scala:87:24]
wire out_roready_1_774; // @[RegisterRouter.scala:87:24]
wire out_roready_1_775; // @[RegisterRouter.scala:87:24]
wire out_roready_1_776; // @[RegisterRouter.scala:87:24]
wire out_roready_1_777; // @[RegisterRouter.scala:87:24]
wire out_roready_1_778; // @[RegisterRouter.scala:87:24]
wire out_roready_1_779; // @[RegisterRouter.scala:87:24]
wire out_roready_1_780; // @[RegisterRouter.scala:87:24]
wire out_roready_1_781; // @[RegisterRouter.scala:87:24]
wire out_roready_1_782; // @[RegisterRouter.scala:87:24]
wire out_roready_1_783; // @[RegisterRouter.scala:87:24]
wire out_roready_1_784; // @[RegisterRouter.scala:87:24]
wire out_roready_1_785; // @[RegisterRouter.scala:87:24]
wire out_roready_1_786; // @[RegisterRouter.scala:87:24]
wire out_roready_1_787; // @[RegisterRouter.scala:87:24]
wire out_roready_1_788; // @[RegisterRouter.scala:87:24]
wire out_roready_1_789; // @[RegisterRouter.scala:87:24]
wire out_roready_1_790; // @[RegisterRouter.scala:87:24]
wire out_roready_1_791; // @[RegisterRouter.scala:87:24]
wire out_roready_1_792; // @[RegisterRouter.scala:87:24]
wire out_roready_1_793; // @[RegisterRouter.scala:87:24]
wire out_roready_1_794; // @[RegisterRouter.scala:87:24]
wire out_roready_1_795; // @[RegisterRouter.scala:87:24]
wire out_roready_1_796; // @[RegisterRouter.scala:87:24]
wire out_roready_1_797; // @[RegisterRouter.scala:87:24]
wire out_roready_1_798; // @[RegisterRouter.scala:87:24]
wire out_roready_1_799; // @[RegisterRouter.scala:87:24]
wire out_roready_1_800; // @[RegisterRouter.scala:87:24]
wire out_roready_1_801; // @[RegisterRouter.scala:87:24]
wire out_roready_1_802; // @[RegisterRouter.scala:87:24]
wire out_roready_1_803; // @[RegisterRouter.scala:87:24]
wire out_roready_1_804; // @[RegisterRouter.scala:87:24]
wire out_roready_1_805; // @[RegisterRouter.scala:87:24]
wire out_roready_1_806; // @[RegisterRouter.scala:87:24]
wire out_roready_1_807; // @[RegisterRouter.scala:87:24]
wire out_roready_1_808; // @[RegisterRouter.scala:87:24]
wire out_roready_1_809; // @[RegisterRouter.scala:87:24]
wire out_roready_1_810; // @[RegisterRouter.scala:87:24]
wire out_roready_1_811; // @[RegisterRouter.scala:87:24]
wire out_roready_1_812; // @[RegisterRouter.scala:87:24]
wire out_roready_1_813; // @[RegisterRouter.scala:87:24]
wire out_roready_1_814; // @[RegisterRouter.scala:87:24]
wire out_roready_1_815; // @[RegisterRouter.scala:87:24]
wire out_roready_1_816; // @[RegisterRouter.scala:87:24]
wire out_roready_1_817; // @[RegisterRouter.scala:87:24]
wire out_roready_1_818; // @[RegisterRouter.scala:87:24]
wire out_roready_1_819; // @[RegisterRouter.scala:87:24]
wire out_roready_1_820; // @[RegisterRouter.scala:87:24]
wire out_roready_1_821; // @[RegisterRouter.scala:87:24]
wire out_roready_1_822; // @[RegisterRouter.scala:87:24]
wire out_roready_1_823; // @[RegisterRouter.scala:87:24]
wire out_roready_1_824; // @[RegisterRouter.scala:87:24]
wire out_roready_1_825; // @[RegisterRouter.scala:87:24]
wire out_roready_1_826; // @[RegisterRouter.scala:87:24]
wire out_roready_1_827; // @[RegisterRouter.scala:87:24]
wire out_roready_1_828; // @[RegisterRouter.scala:87:24]
wire out_roready_1_829; // @[RegisterRouter.scala:87:24]
wire out_roready_1_830; // @[RegisterRouter.scala:87:24]
wire out_roready_1_831; // @[RegisterRouter.scala:87:24]
wire out_roready_1_832; // @[RegisterRouter.scala:87:24]
wire out_roready_1_833; // @[RegisterRouter.scala:87:24]
wire out_roready_1_834; // @[RegisterRouter.scala:87:24]
wire out_roready_1_835; // @[RegisterRouter.scala:87:24]
wire out_roready_1_836; // @[RegisterRouter.scala:87:24]
wire out_roready_1_837; // @[RegisterRouter.scala:87:24]
wire out_roready_1_838; // @[RegisterRouter.scala:87:24]
wire out_roready_1_839; // @[RegisterRouter.scala:87:24]
wire out_roready_1_840; // @[RegisterRouter.scala:87:24]
wire out_roready_1_841; // @[RegisterRouter.scala:87:24]
wire out_roready_1_842; // @[RegisterRouter.scala:87:24]
wire out_roready_1_843; // @[RegisterRouter.scala:87:24]
wire out_roready_1_844; // @[RegisterRouter.scala:87:24]
wire out_roready_1_845; // @[RegisterRouter.scala:87:24]
wire out_roready_1_846; // @[RegisterRouter.scala:87:24]
wire out_roready_1_847; // @[RegisterRouter.scala:87:24]
wire out_roready_1_848; // @[RegisterRouter.scala:87:24]
wire out_roready_1_849; // @[RegisterRouter.scala:87:24]
wire out_roready_1_850; // @[RegisterRouter.scala:87:24]
wire out_roready_1_851; // @[RegisterRouter.scala:87:24]
wire out_roready_1_852; // @[RegisterRouter.scala:87:24]
wire out_roready_1_853; // @[RegisterRouter.scala:87:24]
wire out_roready_1_854; // @[RegisterRouter.scala:87:24]
wire out_roready_1_855; // @[RegisterRouter.scala:87:24]
wire out_roready_1_856; // @[RegisterRouter.scala:87:24]
wire out_roready_1_857; // @[RegisterRouter.scala:87:24]
wire out_roready_1_858; // @[RegisterRouter.scala:87:24]
wire out_roready_1_859; // @[RegisterRouter.scala:87:24]
wire out_roready_1_860; // @[RegisterRouter.scala:87:24]
wire out_roready_1_861; // @[RegisterRouter.scala:87:24]
wire out_roready_1_862; // @[RegisterRouter.scala:87:24]
wire out_roready_1_863; // @[RegisterRouter.scala:87:24]
wire out_roready_1_864; // @[RegisterRouter.scala:87:24]
wire out_roready_1_865; // @[RegisterRouter.scala:87:24]
wire out_roready_1_866; // @[RegisterRouter.scala:87:24]
wire out_roready_1_867; // @[RegisterRouter.scala:87:24]
wire out_roready_1_868; // @[RegisterRouter.scala:87:24]
wire out_roready_1_869; // @[RegisterRouter.scala:87:24]
wire out_roready_1_870; // @[RegisterRouter.scala:87:24]
wire out_roready_1_871; // @[RegisterRouter.scala:87:24]
wire out_roready_1_872; // @[RegisterRouter.scala:87:24]
wire out_roready_1_873; // @[RegisterRouter.scala:87:24]
wire out_roready_1_874; // @[RegisterRouter.scala:87:24]
wire out_roready_1_875; // @[RegisterRouter.scala:87:24]
wire out_roready_1_876; // @[RegisterRouter.scala:87:24]
wire out_roready_1_877; // @[RegisterRouter.scala:87:24]
wire out_roready_1_878; // @[RegisterRouter.scala:87:24]
wire out_roready_1_879; // @[RegisterRouter.scala:87:24]
wire out_roready_1_880; // @[RegisterRouter.scala:87:24]
wire out_roready_1_881; // @[RegisterRouter.scala:87:24]
wire out_roready_1_882; // @[RegisterRouter.scala:87:24]
wire out_roready_1_883; // @[RegisterRouter.scala:87:24]
wire out_roready_1_884; // @[RegisterRouter.scala:87:24]
wire out_roready_1_885; // @[RegisterRouter.scala:87:24]
wire out_roready_1_886; // @[RegisterRouter.scala:87:24]
wire out_roready_1_887; // @[RegisterRouter.scala:87:24]
wire out_roready_1_888; // @[RegisterRouter.scala:87:24]
wire out_roready_1_889; // @[RegisterRouter.scala:87:24]
wire out_roready_1_890; // @[RegisterRouter.scala:87:24]
wire out_roready_1_891; // @[RegisterRouter.scala:87:24]
wire out_roready_1_892; // @[RegisterRouter.scala:87:24]
wire out_roready_1_893; // @[RegisterRouter.scala:87:24]
wire out_roready_1_894; // @[RegisterRouter.scala:87:24]
wire out_roready_1_895; // @[RegisterRouter.scala:87:24]
wire out_roready_1_896; // @[RegisterRouter.scala:87:24]
wire out_roready_1_897; // @[RegisterRouter.scala:87:24]
wire out_roready_1_898; // @[RegisterRouter.scala:87:24]
wire out_roready_1_899; // @[RegisterRouter.scala:87:24]
wire out_roready_1_900; // @[RegisterRouter.scala:87:24]
wire out_roready_1_901; // @[RegisterRouter.scala:87:24]
wire out_roready_1_902; // @[RegisterRouter.scala:87:24]
wire out_roready_1_903; // @[RegisterRouter.scala:87:24]
wire out_roready_1_904; // @[RegisterRouter.scala:87:24]
wire out_roready_1_905; // @[RegisterRouter.scala:87:24]
wire out_roready_1_906; // @[RegisterRouter.scala:87:24]
wire out_roready_1_907; // @[RegisterRouter.scala:87:24]
wire out_roready_1_908; // @[RegisterRouter.scala:87:24]
wire out_roready_1_909; // @[RegisterRouter.scala:87:24]
wire out_roready_1_910; // @[RegisterRouter.scala:87:24]
wire out_roready_1_911; // @[RegisterRouter.scala:87:24]
wire out_roready_1_912; // @[RegisterRouter.scala:87:24]
wire out_roready_1_913; // @[RegisterRouter.scala:87:24]
wire out_roready_1_914; // @[RegisterRouter.scala:87:24]
wire out_roready_1_915; // @[RegisterRouter.scala:87:24]
wire out_roready_1_916; // @[RegisterRouter.scala:87:24]
wire out_roready_1_917; // @[RegisterRouter.scala:87:24]
wire out_roready_1_918; // @[RegisterRouter.scala:87:24]
wire out_roready_1_919; // @[RegisterRouter.scala:87:24]
wire out_roready_1_920; // @[RegisterRouter.scala:87:24]
wire out_roready_1_921; // @[RegisterRouter.scala:87:24]
wire out_roready_1_922; // @[RegisterRouter.scala:87:24]
wire out_roready_1_923; // @[RegisterRouter.scala:87:24]
wire out_roready_1_924; // @[RegisterRouter.scala:87:24]
wire out_roready_1_925; // @[RegisterRouter.scala:87:24]
wire out_roready_1_926; // @[RegisterRouter.scala:87:24]
wire out_roready_1_927; // @[RegisterRouter.scala:87:24]
wire out_roready_1_928; // @[RegisterRouter.scala:87:24]
wire out_roready_1_929; // @[RegisterRouter.scala:87:24]
wire out_roready_1_930; // @[RegisterRouter.scala:87:24]
wire out_roready_1_931; // @[RegisterRouter.scala:87:24]
wire out_roready_1_932; // @[RegisterRouter.scala:87:24]
wire out_roready_1_933; // @[RegisterRouter.scala:87:24]
wire out_roready_1_934; // @[RegisterRouter.scala:87:24]
wire out_roready_1_935; // @[RegisterRouter.scala:87:24]
wire out_roready_1_936; // @[RegisterRouter.scala:87:24]
wire out_roready_1_937; // @[RegisterRouter.scala:87:24]
wire out_roready_1_938; // @[RegisterRouter.scala:87:24]
wire out_roready_1_939; // @[RegisterRouter.scala:87:24]
wire out_roready_1_940; // @[RegisterRouter.scala:87:24]
wire out_roready_1_941; // @[RegisterRouter.scala:87:24]
wire out_roready_1_942; // @[RegisterRouter.scala:87:24]
wire out_roready_1_943; // @[RegisterRouter.scala:87:24]
wire out_roready_1_944; // @[RegisterRouter.scala:87:24]
wire out_roready_1_945; // @[RegisterRouter.scala:87:24]
wire out_roready_1_946; // @[RegisterRouter.scala:87:24]
wire out_roready_1_947; // @[RegisterRouter.scala:87:24]
wire out_roready_1_948; // @[RegisterRouter.scala:87:24]
wire out_roready_1_949; // @[RegisterRouter.scala:87:24]
wire out_roready_1_950; // @[RegisterRouter.scala:87:24]
wire out_roready_1_951; // @[RegisterRouter.scala:87:24]
wire out_roready_1_952; // @[RegisterRouter.scala:87:24]
wire out_roready_1_953; // @[RegisterRouter.scala:87:24]
wire out_roready_1_954; // @[RegisterRouter.scala:87:24]
wire out_roready_1_955; // @[RegisterRouter.scala:87:24]
wire out_roready_1_956; // @[RegisterRouter.scala:87:24]
wire out_roready_1_957; // @[RegisterRouter.scala:87:24]
wire out_roready_1_958; // @[RegisterRouter.scala:87:24]
wire out_roready_1_959; // @[RegisterRouter.scala:87:24]
wire out_roready_1_960; // @[RegisterRouter.scala:87:24]
wire out_roready_1_961; // @[RegisterRouter.scala:87:24]
wire out_roready_1_962; // @[RegisterRouter.scala:87:24]
wire out_roready_1_963; // @[RegisterRouter.scala:87:24]
wire out_roready_1_964; // @[RegisterRouter.scala:87:24]
wire out_roready_1_965; // @[RegisterRouter.scala:87:24]
wire out_roready_1_966; // @[RegisterRouter.scala:87:24]
wire out_roready_1_967; // @[RegisterRouter.scala:87:24]
wire out_roready_1_968; // @[RegisterRouter.scala:87:24]
wire out_roready_1_969; // @[RegisterRouter.scala:87:24]
wire out_roready_1_970; // @[RegisterRouter.scala:87:24]
wire out_roready_1_971; // @[RegisterRouter.scala:87:24]
wire out_roready_1_972; // @[RegisterRouter.scala:87:24]
wire out_roready_1_973; // @[RegisterRouter.scala:87:24]
wire out_roready_1_974; // @[RegisterRouter.scala:87:24]
wire out_roready_1_975; // @[RegisterRouter.scala:87:24]
wire out_roready_1_976; // @[RegisterRouter.scala:87:24]
wire out_roready_1_977; // @[RegisterRouter.scala:87:24]
wire out_roready_1_978; // @[RegisterRouter.scala:87:24]
wire out_roready_1_979; // @[RegisterRouter.scala:87:24]
wire out_roready_1_980; // @[RegisterRouter.scala:87:24]
wire out_roready_1_981; // @[RegisterRouter.scala:87:24]
wire out_roready_1_982; // @[RegisterRouter.scala:87:24]
wire out_roready_1_983; // @[RegisterRouter.scala:87:24]
wire out_roready_1_984; // @[RegisterRouter.scala:87:24]
wire out_roready_1_985; // @[RegisterRouter.scala:87:24]
wire out_roready_1_986; // @[RegisterRouter.scala:87:24]
wire out_roready_1_987; // @[RegisterRouter.scala:87:24]
wire out_roready_1_988; // @[RegisterRouter.scala:87:24]
wire out_roready_1_989; // @[RegisterRouter.scala:87:24]
wire out_roready_1_990; // @[RegisterRouter.scala:87:24]
wire out_roready_1_991; // @[RegisterRouter.scala:87:24]
wire out_roready_1_992; // @[RegisterRouter.scala:87:24]
wire out_roready_1_993; // @[RegisterRouter.scala:87:24]
wire out_roready_1_994; // @[RegisterRouter.scala:87:24]
wire out_roready_1_995; // @[RegisterRouter.scala:87:24]
wire out_roready_1_996; // @[RegisterRouter.scala:87:24]
wire out_roready_1_997; // @[RegisterRouter.scala:87:24]
wire out_roready_1_998; // @[RegisterRouter.scala:87:24]
wire out_roready_1_999; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1000; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1001; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1002; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1003; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1004; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1005; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1006; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1007; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1008; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1009; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1010; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1011; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1012; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1013; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1014; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1015; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1016; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1017; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1018; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1019; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1020; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1021; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1022; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1023; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1024; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1025; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1026; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1027; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1028; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1029; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1030; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1031; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1032; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1033; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1034; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1035; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1036; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1037; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1038; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1039; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1040; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1041; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1042; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1043; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1044; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1045; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1046; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1047; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1048; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1049; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1050; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1051; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1052; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1053; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1054; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1055; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1056; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1057; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1058; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1059; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1060; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1061; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1062; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1063; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1064; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1065; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1066; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1067; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1068; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1069; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1070; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1071; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1072; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1073; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1074; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1075; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1076; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1077; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1078; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1079; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1080; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1081; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1082; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1083; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1084; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1085; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1086; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1087; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1088; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1089; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1090; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1091; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1092; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1093; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1094; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1095; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1096; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1097; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1098; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1099; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1100; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1101; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1102; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1103; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1104; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1105; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1106; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1107; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1108; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1109; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1110; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1111; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1112; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1113; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1114; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1115; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1116; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1117; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1118; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1119; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1120; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1121; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1122; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1123; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1124; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1125; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1126; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1127; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1128; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1129; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1130; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1131; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1132; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1133; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1134; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1135; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1136; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1137; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1138; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1139; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1140; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1141; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1142; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1143; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1144; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1145; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1146; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1147; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1148; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1149; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1150; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1151; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1152; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1153; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1154; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1155; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1156; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1157; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1158; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1159; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1160; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1161; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1162; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1163; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1164; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1165; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1166; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1167; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1168; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1169; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1170; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1171; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1172; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1173; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1174; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1175; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1176; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1177; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1178; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1179; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1180; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1181; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1182; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1183; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1184; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1185; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1186; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1187; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1188; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1189; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1190; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1191; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1192; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1193; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1194; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1195; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1196; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1197; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1198; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1199; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1200; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1201; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1202; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1203; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1204; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1205; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1206; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1207; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1208; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1209; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1210; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_816; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1260; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1200; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_944; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_724; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1132; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1252; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1072; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_832; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_876; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_960; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1004; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_268; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1000; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_704; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1048; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_892; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1020; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_872; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1176; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_284; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1128; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_920; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_980; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_688; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1216; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1108; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1276; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_852; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1148; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_792; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_796; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1236; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_300; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1088; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1196; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1256; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1068; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1144; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_280; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_904; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1032; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_812; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_924; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_396; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1180; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1272; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1052; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1160; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_888; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1016; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_940; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_828; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1164; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1036; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1112; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_648; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_700; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_264; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_956; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_780; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_800; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_304; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1084; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_776; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1212; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_684; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1240; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_928; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_392; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_856; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_296; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_908; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_984; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_860; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_968; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1028; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1080; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_276; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_840; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1208; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_988; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_900; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1012; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_952; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_716; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1140; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1184; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1244; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1096; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_676; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_824; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1116; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_884; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1056; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_696; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1224; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1268; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_784; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1156; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_804; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1168; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1228; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_932; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_912; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1284; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1100; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_712; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1040; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_844; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_864; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_292; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1060; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_972; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_992; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_880; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_964; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_836; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1076; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1136; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_680; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1264; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1188; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_272; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_896; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1008; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_720; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_948; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_820; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1092; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1120; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1204; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1248; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_868; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_848; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1024; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_996; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_936; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_288; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1104; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_692; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_808; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1044; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1220; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1232; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_788; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_976; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_916; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1064; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_708; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1124; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1152; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1192; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1280; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1172; // @[RegisterRouter.scala:87:24]
wire out_woready_1_0; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1; // @[RegisterRouter.scala:87:24]
wire out_woready_1_2; // @[RegisterRouter.scala:87:24]
wire out_woready_1_3; // @[RegisterRouter.scala:87:24]
wire out_woready_1_4; // @[RegisterRouter.scala:87:24]
wire out_woready_1_5; // @[RegisterRouter.scala:87:24]
wire out_woready_1_6; // @[RegisterRouter.scala:87:24]
wire out_woready_1_7; // @[RegisterRouter.scala:87:24]
wire out_woready_1_8; // @[RegisterRouter.scala:87:24]
wire out_woready_1_9; // @[RegisterRouter.scala:87:24]
wire out_woready_1_10; // @[RegisterRouter.scala:87:24]
wire out_woready_1_11; // @[RegisterRouter.scala:87:24]
wire out_woready_1_12; // @[RegisterRouter.scala:87:24]
wire out_woready_1_13; // @[RegisterRouter.scala:87:24]
wire out_woready_1_14; // @[RegisterRouter.scala:87:24]
wire out_woready_1_15; // @[RegisterRouter.scala:87:24]
wire out_woready_1_16; // @[RegisterRouter.scala:87:24]
wire out_woready_1_17; // @[RegisterRouter.scala:87:24]
wire out_woready_1_18; // @[RegisterRouter.scala:87:24]
wire out_woready_1_19; // @[RegisterRouter.scala:87:24]
wire out_woready_1_20; // @[RegisterRouter.scala:87:24]
wire out_woready_1_21; // @[RegisterRouter.scala:87:24]
wire out_woready_1_22; // @[RegisterRouter.scala:87:24]
wire out_woready_1_23; // @[RegisterRouter.scala:87:24]
wire out_woready_1_24; // @[RegisterRouter.scala:87:24]
wire out_woready_1_25; // @[RegisterRouter.scala:87:24]
wire out_woready_1_26; // @[RegisterRouter.scala:87:24]
wire out_woready_1_27; // @[RegisterRouter.scala:87:24]
wire out_woready_1_28; // @[RegisterRouter.scala:87:24]
wire out_woready_1_29; // @[RegisterRouter.scala:87:24]
wire out_woready_1_30; // @[RegisterRouter.scala:87:24]
wire out_woready_1_31; // @[RegisterRouter.scala:87:24]
wire out_woready_1_32; // @[RegisterRouter.scala:87:24]
wire out_woready_1_33; // @[RegisterRouter.scala:87:24]
wire out_woready_1_34; // @[RegisterRouter.scala:87:24]
wire out_woready_1_35; // @[RegisterRouter.scala:87:24]
wire out_woready_1_36; // @[RegisterRouter.scala:87:24]
wire out_woready_1_37; // @[RegisterRouter.scala:87:24]
wire out_woready_1_38; // @[RegisterRouter.scala:87:24]
wire out_woready_1_39; // @[RegisterRouter.scala:87:24]
wire out_woready_1_40; // @[RegisterRouter.scala:87:24]
wire out_woready_1_41; // @[RegisterRouter.scala:87:24]
wire out_woready_1_42; // @[RegisterRouter.scala:87:24]
wire out_woready_1_43; // @[RegisterRouter.scala:87:24]
wire out_woready_1_44; // @[RegisterRouter.scala:87:24]
wire out_woready_1_45; // @[RegisterRouter.scala:87:24]
wire out_woready_1_46; // @[RegisterRouter.scala:87:24]
wire out_woready_1_47; // @[RegisterRouter.scala:87:24]
wire out_woready_1_48; // @[RegisterRouter.scala:87:24]
wire out_woready_1_49; // @[RegisterRouter.scala:87:24]
wire out_woready_1_50; // @[RegisterRouter.scala:87:24]
wire out_woready_1_51; // @[RegisterRouter.scala:87:24]
wire out_woready_1_52; // @[RegisterRouter.scala:87:24]
wire out_woready_1_53; // @[RegisterRouter.scala:87:24]
wire out_woready_1_54; // @[RegisterRouter.scala:87:24]
wire out_woready_1_55; // @[RegisterRouter.scala:87:24]
wire out_woready_1_56; // @[RegisterRouter.scala:87:24]
wire out_woready_1_57; // @[RegisterRouter.scala:87:24]
wire out_woready_1_58; // @[RegisterRouter.scala:87:24]
wire out_woready_1_59; // @[RegisterRouter.scala:87:24]
wire out_woready_1_60; // @[RegisterRouter.scala:87:24]
wire out_woready_1_61; // @[RegisterRouter.scala:87:24]
wire out_woready_1_62; // @[RegisterRouter.scala:87:24]
wire out_woready_1_63; // @[RegisterRouter.scala:87:24]
wire out_woready_1_64; // @[RegisterRouter.scala:87:24]
wire out_woready_1_65; // @[RegisterRouter.scala:87:24]
wire out_woready_1_66; // @[RegisterRouter.scala:87:24]
wire out_woready_1_67; // @[RegisterRouter.scala:87:24]
wire out_woready_1_68; // @[RegisterRouter.scala:87:24]
wire out_woready_1_69; // @[RegisterRouter.scala:87:24]
wire out_woready_1_70; // @[RegisterRouter.scala:87:24]
wire out_woready_1_71; // @[RegisterRouter.scala:87:24]
wire out_woready_1_72; // @[RegisterRouter.scala:87:24]
wire out_woready_1_73; // @[RegisterRouter.scala:87:24]
wire out_woready_1_74; // @[RegisterRouter.scala:87:24]
wire out_woready_1_75; // @[RegisterRouter.scala:87:24]
wire out_woready_1_76; // @[RegisterRouter.scala:87:24]
wire out_woready_1_77; // @[RegisterRouter.scala:87:24]
wire out_woready_1_78; // @[RegisterRouter.scala:87:24]
wire out_woready_1_79; // @[RegisterRouter.scala:87:24]
wire out_woready_1_80; // @[RegisterRouter.scala:87:24]
wire out_woready_1_81; // @[RegisterRouter.scala:87:24]
wire out_woready_1_82; // @[RegisterRouter.scala:87:24]
wire out_woready_1_83; // @[RegisterRouter.scala:87:24]
wire out_woready_1_84; // @[RegisterRouter.scala:87:24]
wire out_woready_1_85; // @[RegisterRouter.scala:87:24]
wire out_woready_1_86; // @[RegisterRouter.scala:87:24]
wire out_woready_1_87; // @[RegisterRouter.scala:87:24]
wire out_woready_1_88; // @[RegisterRouter.scala:87:24]
wire out_woready_1_89; // @[RegisterRouter.scala:87:24]
wire out_woready_1_90; // @[RegisterRouter.scala:87:24]
wire out_woready_1_91; // @[RegisterRouter.scala:87:24]
wire out_woready_1_92; // @[RegisterRouter.scala:87:24]
wire out_woready_1_93; // @[RegisterRouter.scala:87:24]
wire out_woready_1_94; // @[RegisterRouter.scala:87:24]
wire out_woready_1_95; // @[RegisterRouter.scala:87:24]
wire out_woready_1_96; // @[RegisterRouter.scala:87:24]
wire out_woready_1_97; // @[RegisterRouter.scala:87:24]
wire out_woready_1_98; // @[RegisterRouter.scala:87:24]
wire out_woready_1_99; // @[RegisterRouter.scala:87:24]
wire out_woready_1_100; // @[RegisterRouter.scala:87:24]
wire out_woready_1_101; // @[RegisterRouter.scala:87:24]
wire out_woready_1_102; // @[RegisterRouter.scala:87:24]
wire out_woready_1_103; // @[RegisterRouter.scala:87:24]
wire out_woready_1_104; // @[RegisterRouter.scala:87:24]
wire out_woready_1_105; // @[RegisterRouter.scala:87:24]
wire out_woready_1_106; // @[RegisterRouter.scala:87:24]
wire out_woready_1_107; // @[RegisterRouter.scala:87:24]
wire out_woready_1_108; // @[RegisterRouter.scala:87:24]
wire out_woready_1_109; // @[RegisterRouter.scala:87:24]
wire out_woready_1_110; // @[RegisterRouter.scala:87:24]
wire out_woready_1_111; // @[RegisterRouter.scala:87:24]
wire out_woready_1_112; // @[RegisterRouter.scala:87:24]
wire out_woready_1_113; // @[RegisterRouter.scala:87:24]
wire out_woready_1_114; // @[RegisterRouter.scala:87:24]
wire out_woready_1_115; // @[RegisterRouter.scala:87:24]
wire out_woready_1_116; // @[RegisterRouter.scala:87:24]
wire out_woready_1_117; // @[RegisterRouter.scala:87:24]
wire out_woready_1_118; // @[RegisterRouter.scala:87:24]
wire out_woready_1_119; // @[RegisterRouter.scala:87:24]
wire out_woready_1_120; // @[RegisterRouter.scala:87:24]
wire out_woready_1_121; // @[RegisterRouter.scala:87:24]
wire out_woready_1_122; // @[RegisterRouter.scala:87:24]
wire out_woready_1_123; // @[RegisterRouter.scala:87:24]
wire out_woready_1_124; // @[RegisterRouter.scala:87:24]
wire out_woready_1_125; // @[RegisterRouter.scala:87:24]
wire out_woready_1_126; // @[RegisterRouter.scala:87:24]
wire out_woready_1_127; // @[RegisterRouter.scala:87:24]
wire out_woready_1_128; // @[RegisterRouter.scala:87:24]
wire out_woready_1_129; // @[RegisterRouter.scala:87:24]
wire out_woready_1_130; // @[RegisterRouter.scala:87:24]
wire out_woready_1_131; // @[RegisterRouter.scala:87:24]
wire out_woready_1_132; // @[RegisterRouter.scala:87:24]
wire out_woready_1_133; // @[RegisterRouter.scala:87:24]
wire out_woready_1_134; // @[RegisterRouter.scala:87:24]
wire out_woready_1_135; // @[RegisterRouter.scala:87:24]
wire out_woready_1_136; // @[RegisterRouter.scala:87:24]
wire out_woready_1_137; // @[RegisterRouter.scala:87:24]
wire out_woready_1_138; // @[RegisterRouter.scala:87:24]
wire out_woready_1_139; // @[RegisterRouter.scala:87:24]
wire out_woready_1_140; // @[RegisterRouter.scala:87:24]
wire out_woready_1_141; // @[RegisterRouter.scala:87:24]
wire out_woready_1_142; // @[RegisterRouter.scala:87:24]
wire out_woready_1_143; // @[RegisterRouter.scala:87:24]
wire out_woready_1_144; // @[RegisterRouter.scala:87:24]
wire out_woready_1_145; // @[RegisterRouter.scala:87:24]
wire out_woready_1_146; // @[RegisterRouter.scala:87:24]
wire out_woready_1_147; // @[RegisterRouter.scala:87:24]
wire out_woready_1_148; // @[RegisterRouter.scala:87:24]
wire out_woready_1_149; // @[RegisterRouter.scala:87:24]
wire out_woready_1_150; // @[RegisterRouter.scala:87:24]
wire out_woready_1_151; // @[RegisterRouter.scala:87:24]
wire out_woready_1_152; // @[RegisterRouter.scala:87:24]
wire out_woready_1_153; // @[RegisterRouter.scala:87:24]
wire out_woready_1_154; // @[RegisterRouter.scala:87:24]
wire out_woready_1_155; // @[RegisterRouter.scala:87:24]
wire out_woready_1_156; // @[RegisterRouter.scala:87:24]
wire out_woready_1_157; // @[RegisterRouter.scala:87:24]
wire out_woready_1_158; // @[RegisterRouter.scala:87:24]
wire out_woready_1_159; // @[RegisterRouter.scala:87:24]
wire out_woready_1_160; // @[RegisterRouter.scala:87:24]
wire out_woready_1_161; // @[RegisterRouter.scala:87:24]
wire out_woready_1_162; // @[RegisterRouter.scala:87:24]
wire out_woready_1_163; // @[RegisterRouter.scala:87:24]
wire out_woready_1_164; // @[RegisterRouter.scala:87:24]
wire out_woready_1_165; // @[RegisterRouter.scala:87:24]
wire out_woready_1_166; // @[RegisterRouter.scala:87:24]
wire out_woready_1_167; // @[RegisterRouter.scala:87:24]
wire out_woready_1_168; // @[RegisterRouter.scala:87:24]
wire out_woready_1_169; // @[RegisterRouter.scala:87:24]
wire out_woready_1_170; // @[RegisterRouter.scala:87:24]
wire out_woready_1_171; // @[RegisterRouter.scala:87:24]
wire out_woready_1_172; // @[RegisterRouter.scala:87:24]
wire out_woready_1_173; // @[RegisterRouter.scala:87:24]
wire out_woready_1_174; // @[RegisterRouter.scala:87:24]
wire out_woready_1_175; // @[RegisterRouter.scala:87:24]
wire out_woready_1_176; // @[RegisterRouter.scala:87:24]
wire out_woready_1_177; // @[RegisterRouter.scala:87:24]
wire out_woready_1_178; // @[RegisterRouter.scala:87:24]
wire out_woready_1_179; // @[RegisterRouter.scala:87:24]
wire out_woready_1_180; // @[RegisterRouter.scala:87:24]
wire out_woready_1_181; // @[RegisterRouter.scala:87:24]
wire out_woready_1_182; // @[RegisterRouter.scala:87:24]
wire out_woready_1_183; // @[RegisterRouter.scala:87:24]
wire out_woready_1_184; // @[RegisterRouter.scala:87:24]
wire out_woready_1_185; // @[RegisterRouter.scala:87:24]
wire out_woready_1_186; // @[RegisterRouter.scala:87:24]
wire out_woready_1_187; // @[RegisterRouter.scala:87:24]
wire out_woready_1_188; // @[RegisterRouter.scala:87:24]
wire out_woready_1_189; // @[RegisterRouter.scala:87:24]
wire out_woready_1_190; // @[RegisterRouter.scala:87:24]
wire out_woready_1_191; // @[RegisterRouter.scala:87:24]
wire out_woready_1_192; // @[RegisterRouter.scala:87:24]
wire out_woready_1_193; // @[RegisterRouter.scala:87:24]
wire out_woready_1_194; // @[RegisterRouter.scala:87:24]
wire out_woready_1_195; // @[RegisterRouter.scala:87:24]
wire out_woready_1_196; // @[RegisterRouter.scala:87:24]
wire out_woready_1_197; // @[RegisterRouter.scala:87:24]
wire out_woready_1_198; // @[RegisterRouter.scala:87:24]
wire out_woready_1_199; // @[RegisterRouter.scala:87:24]
wire out_woready_1_200; // @[RegisterRouter.scala:87:24]
wire out_woready_1_201; // @[RegisterRouter.scala:87:24]
wire out_woready_1_202; // @[RegisterRouter.scala:87:24]
wire out_woready_1_203; // @[RegisterRouter.scala:87:24]
wire out_woready_1_204; // @[RegisterRouter.scala:87:24]
wire out_woready_1_205; // @[RegisterRouter.scala:87:24]
wire out_woready_1_206; // @[RegisterRouter.scala:87:24]
wire out_woready_1_207; // @[RegisterRouter.scala:87:24]
wire out_woready_1_208; // @[RegisterRouter.scala:87:24]
wire out_woready_1_209; // @[RegisterRouter.scala:87:24]
wire out_woready_1_210; // @[RegisterRouter.scala:87:24]
wire out_woready_1_211; // @[RegisterRouter.scala:87:24]
wire out_woready_1_212; // @[RegisterRouter.scala:87:24]
wire out_woready_1_213; // @[RegisterRouter.scala:87:24]
wire out_woready_1_214; // @[RegisterRouter.scala:87:24]
wire out_woready_1_215; // @[RegisterRouter.scala:87:24]
wire out_woready_1_216; // @[RegisterRouter.scala:87:24]
wire out_woready_1_217; // @[RegisterRouter.scala:87:24]
wire out_woready_1_218; // @[RegisterRouter.scala:87:24]
wire out_woready_1_219; // @[RegisterRouter.scala:87:24]
wire out_woready_1_220; // @[RegisterRouter.scala:87:24]
wire out_woready_1_221; // @[RegisterRouter.scala:87:24]
wire out_woready_1_222; // @[RegisterRouter.scala:87:24]
wire out_woready_1_223; // @[RegisterRouter.scala:87:24]
wire out_woready_1_224; // @[RegisterRouter.scala:87:24]
wire out_woready_1_225; // @[RegisterRouter.scala:87:24]
wire out_woready_1_226; // @[RegisterRouter.scala:87:24]
wire out_woready_1_227; // @[RegisterRouter.scala:87:24]
wire out_woready_1_228; // @[RegisterRouter.scala:87:24]
wire out_woready_1_229; // @[RegisterRouter.scala:87:24]
wire out_woready_1_230; // @[RegisterRouter.scala:87:24]
wire out_woready_1_231; // @[RegisterRouter.scala:87:24]
wire out_woready_1_232; // @[RegisterRouter.scala:87:24]
wire out_woready_1_233; // @[RegisterRouter.scala:87:24]
wire out_woready_1_234; // @[RegisterRouter.scala:87:24]
wire out_woready_1_235; // @[RegisterRouter.scala:87:24]
wire out_woready_1_236; // @[RegisterRouter.scala:87:24]
wire out_woready_1_237; // @[RegisterRouter.scala:87:24]
wire out_woready_1_238; // @[RegisterRouter.scala:87:24]
wire out_woready_1_239; // @[RegisterRouter.scala:87:24]
wire out_woready_1_240; // @[RegisterRouter.scala:87:24]
wire out_woready_1_241; // @[RegisterRouter.scala:87:24]
wire out_woready_1_242; // @[RegisterRouter.scala:87:24]
wire out_woready_1_243; // @[RegisterRouter.scala:87:24]
wire out_woready_1_244; // @[RegisterRouter.scala:87:24]
wire out_woready_1_245; // @[RegisterRouter.scala:87:24]
wire out_woready_1_246; // @[RegisterRouter.scala:87:24]
wire out_woready_1_247; // @[RegisterRouter.scala:87:24]
wire out_woready_1_248; // @[RegisterRouter.scala:87:24]
wire out_woready_1_249; // @[RegisterRouter.scala:87:24]
wire out_woready_1_250; // @[RegisterRouter.scala:87:24]
wire out_woready_1_251; // @[RegisterRouter.scala:87:24]
wire out_woready_1_252; // @[RegisterRouter.scala:87:24]
wire out_woready_1_253; // @[RegisterRouter.scala:87:24]
wire out_woready_1_254; // @[RegisterRouter.scala:87:24]
wire out_woready_1_255; // @[RegisterRouter.scala:87:24]
wire out_woready_1_256; // @[RegisterRouter.scala:87:24]
wire out_woready_1_257; // @[RegisterRouter.scala:87:24]
wire out_woready_1_258; // @[RegisterRouter.scala:87:24]
wire out_woready_1_259; // @[RegisterRouter.scala:87:24]
wire out_woready_1_260; // @[RegisterRouter.scala:87:24]
wire out_woready_1_261; // @[RegisterRouter.scala:87:24]
wire out_woready_1_262; // @[RegisterRouter.scala:87:24]
wire out_woready_1_263; // @[RegisterRouter.scala:87:24]
wire out_woready_1_264; // @[RegisterRouter.scala:87:24]
wire out_woready_1_265; // @[RegisterRouter.scala:87:24]
wire out_woready_1_266; // @[RegisterRouter.scala:87:24]
wire out_woready_1_267; // @[RegisterRouter.scala:87:24]
wire out_woready_1_268; // @[RegisterRouter.scala:87:24]
wire out_woready_1_269; // @[RegisterRouter.scala:87:24]
wire out_woready_1_270; // @[RegisterRouter.scala:87:24]
wire out_woready_1_271; // @[RegisterRouter.scala:87:24]
wire out_woready_1_272; // @[RegisterRouter.scala:87:24]
wire out_woready_1_273; // @[RegisterRouter.scala:87:24]
wire out_woready_1_274; // @[RegisterRouter.scala:87:24]
wire out_woready_1_275; // @[RegisterRouter.scala:87:24]
wire out_woready_1_276; // @[RegisterRouter.scala:87:24]
wire out_woready_1_277; // @[RegisterRouter.scala:87:24]
wire out_woready_1_278; // @[RegisterRouter.scala:87:24]
wire out_woready_1_279; // @[RegisterRouter.scala:87:24]
wire out_woready_1_280; // @[RegisterRouter.scala:87:24]
wire out_woready_1_281; // @[RegisterRouter.scala:87:24]
wire out_woready_1_282; // @[RegisterRouter.scala:87:24]
wire out_woready_1_283; // @[RegisterRouter.scala:87:24]
wire out_woready_1_284; // @[RegisterRouter.scala:87:24]
wire out_woready_1_285; // @[RegisterRouter.scala:87:24]
wire out_woready_1_286; // @[RegisterRouter.scala:87:24]
wire out_woready_1_287; // @[RegisterRouter.scala:87:24]
wire out_woready_1_288; // @[RegisterRouter.scala:87:24]
wire out_woready_1_289; // @[RegisterRouter.scala:87:24]
wire out_woready_1_290; // @[RegisterRouter.scala:87:24]
wire out_woready_1_291; // @[RegisterRouter.scala:87:24]
wire out_woready_1_292; // @[RegisterRouter.scala:87:24]
wire out_woready_1_293; // @[RegisterRouter.scala:87:24]
wire out_woready_1_294; // @[RegisterRouter.scala:87:24]
wire out_woready_1_295; // @[RegisterRouter.scala:87:24]
wire out_woready_1_296; // @[RegisterRouter.scala:87:24]
wire out_woready_1_297; // @[RegisterRouter.scala:87:24]
wire out_woready_1_298; // @[RegisterRouter.scala:87:24]
wire out_woready_1_299; // @[RegisterRouter.scala:87:24]
wire out_woready_1_300; // @[RegisterRouter.scala:87:24]
wire out_woready_1_301; // @[RegisterRouter.scala:87:24]
wire out_woready_1_302; // @[RegisterRouter.scala:87:24]
wire out_woready_1_303; // @[RegisterRouter.scala:87:24]
wire out_woready_1_304; // @[RegisterRouter.scala:87:24]
wire out_woready_1_305; // @[RegisterRouter.scala:87:24]
wire out_woready_1_306; // @[RegisterRouter.scala:87:24]
wire out_woready_1_307; // @[RegisterRouter.scala:87:24]
wire out_woready_1_308; // @[RegisterRouter.scala:87:24]
wire out_woready_1_309; // @[RegisterRouter.scala:87:24]
wire out_woready_1_310; // @[RegisterRouter.scala:87:24]
wire out_woready_1_311; // @[RegisterRouter.scala:87:24]
wire out_woready_1_312; // @[RegisterRouter.scala:87:24]
wire out_woready_1_313; // @[RegisterRouter.scala:87:24]
wire out_woready_1_314; // @[RegisterRouter.scala:87:24]
wire out_woready_1_315; // @[RegisterRouter.scala:87:24]
wire out_woready_1_316; // @[RegisterRouter.scala:87:24]
wire out_woready_1_317; // @[RegisterRouter.scala:87:24]
wire out_woready_1_318; // @[RegisterRouter.scala:87:24]
wire out_woready_1_319; // @[RegisterRouter.scala:87:24]
wire out_woready_1_320; // @[RegisterRouter.scala:87:24]
wire out_woready_1_321; // @[RegisterRouter.scala:87:24]
wire out_woready_1_322; // @[RegisterRouter.scala:87:24]
wire out_woready_1_323; // @[RegisterRouter.scala:87:24]
wire out_woready_1_324; // @[RegisterRouter.scala:87:24]
wire out_woready_1_325; // @[RegisterRouter.scala:87:24]
wire out_woready_1_326; // @[RegisterRouter.scala:87:24]
wire out_woready_1_327; // @[RegisterRouter.scala:87:24]
wire out_woready_1_328; // @[RegisterRouter.scala:87:24]
wire out_woready_1_329; // @[RegisterRouter.scala:87:24]
wire out_woready_1_330; // @[RegisterRouter.scala:87:24]
wire out_woready_1_331; // @[RegisterRouter.scala:87:24]
wire out_woready_1_332; // @[RegisterRouter.scala:87:24]
wire out_woready_1_333; // @[RegisterRouter.scala:87:24]
wire out_woready_1_334; // @[RegisterRouter.scala:87:24]
wire out_woready_1_335; // @[RegisterRouter.scala:87:24]
wire out_woready_1_336; // @[RegisterRouter.scala:87:24]
wire out_woready_1_337; // @[RegisterRouter.scala:87:24]
wire out_woready_1_338; // @[RegisterRouter.scala:87:24]
wire out_woready_1_339; // @[RegisterRouter.scala:87:24]
wire out_woready_1_340; // @[RegisterRouter.scala:87:24]
wire out_woready_1_341; // @[RegisterRouter.scala:87:24]
wire out_woready_1_342; // @[RegisterRouter.scala:87:24]
wire out_woready_1_343; // @[RegisterRouter.scala:87:24]
wire out_woready_1_344; // @[RegisterRouter.scala:87:24]
wire out_woready_1_345; // @[RegisterRouter.scala:87:24]
wire out_woready_1_346; // @[RegisterRouter.scala:87:24]
wire out_woready_1_347; // @[RegisterRouter.scala:87:24]
wire out_woready_1_348; // @[RegisterRouter.scala:87:24]
wire out_woready_1_349; // @[RegisterRouter.scala:87:24]
wire out_woready_1_350; // @[RegisterRouter.scala:87:24]
wire out_woready_1_351; // @[RegisterRouter.scala:87:24]
wire out_woready_1_352; // @[RegisterRouter.scala:87:24]
wire out_woready_1_353; // @[RegisterRouter.scala:87:24]
wire out_woready_1_354; // @[RegisterRouter.scala:87:24]
wire out_woready_1_355; // @[RegisterRouter.scala:87:24]
wire out_woready_1_356; // @[RegisterRouter.scala:87:24]
wire out_woready_1_357; // @[RegisterRouter.scala:87:24]
wire out_woready_1_358; // @[RegisterRouter.scala:87:24]
wire out_woready_1_359; // @[RegisterRouter.scala:87:24]
wire out_woready_1_360; // @[RegisterRouter.scala:87:24]
wire out_woready_1_361; // @[RegisterRouter.scala:87:24]
wire out_woready_1_362; // @[RegisterRouter.scala:87:24]
wire out_woready_1_363; // @[RegisterRouter.scala:87:24]
wire out_woready_1_364; // @[RegisterRouter.scala:87:24]
wire out_woready_1_365; // @[RegisterRouter.scala:87:24]
wire out_woready_1_366; // @[RegisterRouter.scala:87:24]
wire out_woready_1_367; // @[RegisterRouter.scala:87:24]
wire out_woready_1_368; // @[RegisterRouter.scala:87:24]
wire out_woready_1_369; // @[RegisterRouter.scala:87:24]
wire out_woready_1_370; // @[RegisterRouter.scala:87:24]
wire out_woready_1_371; // @[RegisterRouter.scala:87:24]
wire out_woready_1_372; // @[RegisterRouter.scala:87:24]
wire out_woready_1_373; // @[RegisterRouter.scala:87:24]
wire out_woready_1_374; // @[RegisterRouter.scala:87:24]
wire out_woready_1_375; // @[RegisterRouter.scala:87:24]
wire out_woready_1_376; // @[RegisterRouter.scala:87:24]
wire out_woready_1_377; // @[RegisterRouter.scala:87:24]
wire out_woready_1_378; // @[RegisterRouter.scala:87:24]
wire out_woready_1_379; // @[RegisterRouter.scala:87:24]
wire out_woready_1_380; // @[RegisterRouter.scala:87:24]
wire out_woready_1_381; // @[RegisterRouter.scala:87:24]
wire out_woready_1_382; // @[RegisterRouter.scala:87:24]
wire out_woready_1_383; // @[RegisterRouter.scala:87:24]
wire out_woready_1_384; // @[RegisterRouter.scala:87:24]
wire out_woready_1_385; // @[RegisterRouter.scala:87:24]
wire out_woready_1_386; // @[RegisterRouter.scala:87:24]
wire out_woready_1_387; // @[RegisterRouter.scala:87:24]
wire out_woready_1_388; // @[RegisterRouter.scala:87:24]
wire out_woready_1_389; // @[RegisterRouter.scala:87:24]
wire out_woready_1_390; // @[RegisterRouter.scala:87:24]
wire out_woready_1_391; // @[RegisterRouter.scala:87:24]
wire out_woready_1_392; // @[RegisterRouter.scala:87:24]
wire out_woready_1_393; // @[RegisterRouter.scala:87:24]
wire out_woready_1_394; // @[RegisterRouter.scala:87:24]
wire out_woready_1_395; // @[RegisterRouter.scala:87:24]
wire out_woready_1_396; // @[RegisterRouter.scala:87:24]
wire out_woready_1_397; // @[RegisterRouter.scala:87:24]
wire out_woready_1_398; // @[RegisterRouter.scala:87:24]
wire out_woready_1_399; // @[RegisterRouter.scala:87:24]
wire out_woready_1_400; // @[RegisterRouter.scala:87:24]
wire out_woready_1_401; // @[RegisterRouter.scala:87:24]
wire out_woready_1_402; // @[RegisterRouter.scala:87:24]
wire out_woready_1_403; // @[RegisterRouter.scala:87:24]
wire out_woready_1_404; // @[RegisterRouter.scala:87:24]
wire out_woready_1_405; // @[RegisterRouter.scala:87:24]
wire out_woready_1_406; // @[RegisterRouter.scala:87:24]
wire out_woready_1_407; // @[RegisterRouter.scala:87:24]
wire out_woready_1_408; // @[RegisterRouter.scala:87:24]
wire out_woready_1_409; // @[RegisterRouter.scala:87:24]
wire out_woready_1_410; // @[RegisterRouter.scala:87:24]
wire out_woready_1_411; // @[RegisterRouter.scala:87:24]
wire out_woready_1_412; // @[RegisterRouter.scala:87:24]
wire out_woready_1_413; // @[RegisterRouter.scala:87:24]
wire out_woready_1_414; // @[RegisterRouter.scala:87:24]
wire out_woready_1_415; // @[RegisterRouter.scala:87:24]
wire out_woready_1_416; // @[RegisterRouter.scala:87:24]
wire out_woready_1_417; // @[RegisterRouter.scala:87:24]
wire out_woready_1_418; // @[RegisterRouter.scala:87:24]
wire out_woready_1_419; // @[RegisterRouter.scala:87:24]
wire out_woready_1_420; // @[RegisterRouter.scala:87:24]
wire out_woready_1_421; // @[RegisterRouter.scala:87:24]
wire out_woready_1_422; // @[RegisterRouter.scala:87:24]
wire out_woready_1_423; // @[RegisterRouter.scala:87:24]
wire out_woready_1_424; // @[RegisterRouter.scala:87:24]
wire out_woready_1_425; // @[RegisterRouter.scala:87:24]
wire out_woready_1_426; // @[RegisterRouter.scala:87:24]
wire out_woready_1_427; // @[RegisterRouter.scala:87:24]
wire out_woready_1_428; // @[RegisterRouter.scala:87:24]
wire out_woready_1_429; // @[RegisterRouter.scala:87:24]
wire out_woready_1_430; // @[RegisterRouter.scala:87:24]
wire out_woready_1_431; // @[RegisterRouter.scala:87:24]
wire out_woready_1_432; // @[RegisterRouter.scala:87:24]
wire out_woready_1_433; // @[RegisterRouter.scala:87:24]
wire out_woready_1_434; // @[RegisterRouter.scala:87:24]
wire out_woready_1_435; // @[RegisterRouter.scala:87:24]
wire out_woready_1_436; // @[RegisterRouter.scala:87:24]
wire out_woready_1_437; // @[RegisterRouter.scala:87:24]
wire out_woready_1_438; // @[RegisterRouter.scala:87:24]
wire out_woready_1_439; // @[RegisterRouter.scala:87:24]
wire out_woready_1_440; // @[RegisterRouter.scala:87:24]
wire out_woready_1_441; // @[RegisterRouter.scala:87:24]
wire out_woready_1_442; // @[RegisterRouter.scala:87:24]
wire out_woready_1_443; // @[RegisterRouter.scala:87:24]
wire out_woready_1_444; // @[RegisterRouter.scala:87:24]
wire out_woready_1_445; // @[RegisterRouter.scala:87:24]
wire out_woready_1_446; // @[RegisterRouter.scala:87:24]
wire out_woready_1_447; // @[RegisterRouter.scala:87:24]
wire out_woready_1_448; // @[RegisterRouter.scala:87:24]
wire out_woready_1_449; // @[RegisterRouter.scala:87:24]
wire out_woready_1_450; // @[RegisterRouter.scala:87:24]
wire out_woready_1_451; // @[RegisterRouter.scala:87:24]
wire out_woready_1_452; // @[RegisterRouter.scala:87:24]
wire out_woready_1_453; // @[RegisterRouter.scala:87:24]
wire out_woready_1_454; // @[RegisterRouter.scala:87:24]
wire out_woready_1_455; // @[RegisterRouter.scala:87:24]
wire out_woready_1_456; // @[RegisterRouter.scala:87:24]
wire out_woready_1_457; // @[RegisterRouter.scala:87:24]
wire out_woready_1_458; // @[RegisterRouter.scala:87:24]
wire out_woready_1_459; // @[RegisterRouter.scala:87:24]
wire out_woready_1_460; // @[RegisterRouter.scala:87:24]
wire out_woready_1_461; // @[RegisterRouter.scala:87:24]
wire out_woready_1_462; // @[RegisterRouter.scala:87:24]
wire out_woready_1_463; // @[RegisterRouter.scala:87:24]
wire out_woready_1_464; // @[RegisterRouter.scala:87:24]
wire out_woready_1_465; // @[RegisterRouter.scala:87:24]
wire out_woready_1_466; // @[RegisterRouter.scala:87:24]
wire out_woready_1_467; // @[RegisterRouter.scala:87:24]
wire out_woready_1_468; // @[RegisterRouter.scala:87:24]
wire out_woready_1_469; // @[RegisterRouter.scala:87:24]
wire out_woready_1_470; // @[RegisterRouter.scala:87:24]
wire out_woready_1_471; // @[RegisterRouter.scala:87:24]
wire out_woready_1_472; // @[RegisterRouter.scala:87:24]
wire out_woready_1_473; // @[RegisterRouter.scala:87:24]
wire out_woready_1_474; // @[RegisterRouter.scala:87:24]
wire out_woready_1_475; // @[RegisterRouter.scala:87:24]
wire out_woready_1_476; // @[RegisterRouter.scala:87:24]
wire out_woready_1_477; // @[RegisterRouter.scala:87:24]
wire out_woready_1_478; // @[RegisterRouter.scala:87:24]
wire out_woready_1_479; // @[RegisterRouter.scala:87:24]
wire out_woready_1_480; // @[RegisterRouter.scala:87:24]
wire out_woready_1_481; // @[RegisterRouter.scala:87:24]
wire out_woready_1_482; // @[RegisterRouter.scala:87:24]
wire out_woready_1_483; // @[RegisterRouter.scala:87:24]
wire out_woready_1_484; // @[RegisterRouter.scala:87:24]
wire out_woready_1_485; // @[RegisterRouter.scala:87:24]
wire out_woready_1_486; // @[RegisterRouter.scala:87:24]
wire out_woready_1_487; // @[RegisterRouter.scala:87:24]
wire out_woready_1_488; // @[RegisterRouter.scala:87:24]
wire out_woready_1_489; // @[RegisterRouter.scala:87:24]
wire out_woready_1_490; // @[RegisterRouter.scala:87:24]
wire out_woready_1_491; // @[RegisterRouter.scala:87:24]
wire out_woready_1_492; // @[RegisterRouter.scala:87:24]
wire out_woready_1_493; // @[RegisterRouter.scala:87:24]
wire out_woready_1_494; // @[RegisterRouter.scala:87:24]
wire out_woready_1_495; // @[RegisterRouter.scala:87:24]
wire out_woready_1_496; // @[RegisterRouter.scala:87:24]
wire out_woready_1_497; // @[RegisterRouter.scala:87:24]
wire out_woready_1_498; // @[RegisterRouter.scala:87:24]
wire out_woready_1_499; // @[RegisterRouter.scala:87:24]
wire out_woready_1_500; // @[RegisterRouter.scala:87:24]
wire out_woready_1_501; // @[RegisterRouter.scala:87:24]
wire out_woready_1_502; // @[RegisterRouter.scala:87:24]
wire out_woready_1_503; // @[RegisterRouter.scala:87:24]
wire out_woready_1_504; // @[RegisterRouter.scala:87:24]
wire out_woready_1_505; // @[RegisterRouter.scala:87:24]
wire out_woready_1_506; // @[RegisterRouter.scala:87:24]
wire out_woready_1_507; // @[RegisterRouter.scala:87:24]
wire out_woready_1_508; // @[RegisterRouter.scala:87:24]
wire out_woready_1_509; // @[RegisterRouter.scala:87:24]
wire out_woready_1_510; // @[RegisterRouter.scala:87:24]
wire out_woready_1_511; // @[RegisterRouter.scala:87:24]
wire out_woready_1_512; // @[RegisterRouter.scala:87:24]
wire out_woready_1_513; // @[RegisterRouter.scala:87:24]
wire out_woready_1_514; // @[RegisterRouter.scala:87:24]
wire out_woready_1_515; // @[RegisterRouter.scala:87:24]
wire out_woready_1_516; // @[RegisterRouter.scala:87:24]
wire out_woready_1_517; // @[RegisterRouter.scala:87:24]
wire out_woready_1_518; // @[RegisterRouter.scala:87:24]
wire out_woready_1_519; // @[RegisterRouter.scala:87:24]
wire out_woready_1_520; // @[RegisterRouter.scala:87:24]
wire out_woready_1_521; // @[RegisterRouter.scala:87:24]
wire out_woready_1_522; // @[RegisterRouter.scala:87:24]
wire out_woready_1_523; // @[RegisterRouter.scala:87:24]
wire out_woready_1_524; // @[RegisterRouter.scala:87:24]
wire out_woready_1_525; // @[RegisterRouter.scala:87:24]
wire out_woready_1_526; // @[RegisterRouter.scala:87:24]
wire out_woready_1_527; // @[RegisterRouter.scala:87:24]
wire out_woready_1_528; // @[RegisterRouter.scala:87:24]
wire out_woready_1_529; // @[RegisterRouter.scala:87:24]
wire out_woready_1_530; // @[RegisterRouter.scala:87:24]
wire out_woready_1_531; // @[RegisterRouter.scala:87:24]
wire out_woready_1_532; // @[RegisterRouter.scala:87:24]
wire out_woready_1_533; // @[RegisterRouter.scala:87:24]
wire out_woready_1_534; // @[RegisterRouter.scala:87:24]
wire out_woready_1_535; // @[RegisterRouter.scala:87:24]
wire out_woready_1_536; // @[RegisterRouter.scala:87:24]
wire out_woready_1_537; // @[RegisterRouter.scala:87:24]
wire out_woready_1_538; // @[RegisterRouter.scala:87:24]
wire out_woready_1_539; // @[RegisterRouter.scala:87:24]
wire out_woready_1_540; // @[RegisterRouter.scala:87:24]
wire out_woready_1_541; // @[RegisterRouter.scala:87:24]
wire out_woready_1_542; // @[RegisterRouter.scala:87:24]
wire out_woready_1_543; // @[RegisterRouter.scala:87:24]
wire out_woready_1_544; // @[RegisterRouter.scala:87:24]
wire out_woready_1_545; // @[RegisterRouter.scala:87:24]
wire out_woready_1_546; // @[RegisterRouter.scala:87:24]
wire out_woready_1_547; // @[RegisterRouter.scala:87:24]
wire out_woready_1_548; // @[RegisterRouter.scala:87:24]
wire out_woready_1_549; // @[RegisterRouter.scala:87:24]
wire out_woready_1_550; // @[RegisterRouter.scala:87:24]
wire out_woready_1_551; // @[RegisterRouter.scala:87:24]
wire out_woready_1_552; // @[RegisterRouter.scala:87:24]
wire out_woready_1_553; // @[RegisterRouter.scala:87:24]
wire out_woready_1_554; // @[RegisterRouter.scala:87:24]
wire out_woready_1_555; // @[RegisterRouter.scala:87:24]
wire out_woready_1_556; // @[RegisterRouter.scala:87:24]
wire out_woready_1_557; // @[RegisterRouter.scala:87:24]
wire out_woready_1_558; // @[RegisterRouter.scala:87:24]
wire out_woready_1_559; // @[RegisterRouter.scala:87:24]
wire out_woready_1_560; // @[RegisterRouter.scala:87:24]
wire out_woready_1_561; // @[RegisterRouter.scala:87:24]
wire out_woready_1_562; // @[RegisterRouter.scala:87:24]
wire out_woready_1_563; // @[RegisterRouter.scala:87:24]
wire out_woready_1_564; // @[RegisterRouter.scala:87:24]
wire out_woready_1_565; // @[RegisterRouter.scala:87:24]
wire out_woready_1_566; // @[RegisterRouter.scala:87:24]
wire out_woready_1_567; // @[RegisterRouter.scala:87:24]
wire out_woready_1_568; // @[RegisterRouter.scala:87:24]
wire out_woready_1_569; // @[RegisterRouter.scala:87:24]
wire out_woready_1_570; // @[RegisterRouter.scala:87:24]
wire out_woready_1_571; // @[RegisterRouter.scala:87:24]
wire out_woready_1_572; // @[RegisterRouter.scala:87:24]
wire out_woready_1_573; // @[RegisterRouter.scala:87:24]
wire out_woready_1_574; // @[RegisterRouter.scala:87:24]
wire out_woready_1_575; // @[RegisterRouter.scala:87:24]
wire out_woready_1_576; // @[RegisterRouter.scala:87:24]
wire out_woready_1_577; // @[RegisterRouter.scala:87:24]
wire out_woready_1_578; // @[RegisterRouter.scala:87:24]
wire out_woready_1_579; // @[RegisterRouter.scala:87:24]
wire out_woready_1_580; // @[RegisterRouter.scala:87:24]
wire out_woready_1_581; // @[RegisterRouter.scala:87:24]
wire out_woready_1_582; // @[RegisterRouter.scala:87:24]
wire out_woready_1_583; // @[RegisterRouter.scala:87:24]
wire out_woready_1_584; // @[RegisterRouter.scala:87:24]
wire out_woready_1_585; // @[RegisterRouter.scala:87:24]
wire out_woready_1_586; // @[RegisterRouter.scala:87:24]
wire out_woready_1_587; // @[RegisterRouter.scala:87:24]
wire out_woready_1_588; // @[RegisterRouter.scala:87:24]
wire out_woready_1_589; // @[RegisterRouter.scala:87:24]
wire out_woready_1_590; // @[RegisterRouter.scala:87:24]
wire out_woready_1_591; // @[RegisterRouter.scala:87:24]
wire out_woready_1_592; // @[RegisterRouter.scala:87:24]
wire out_woready_1_593; // @[RegisterRouter.scala:87:24]
wire out_woready_1_594; // @[RegisterRouter.scala:87:24]
wire out_woready_1_595; // @[RegisterRouter.scala:87:24]
wire out_woready_1_596; // @[RegisterRouter.scala:87:24]
wire out_woready_1_597; // @[RegisterRouter.scala:87:24]
wire out_woready_1_598; // @[RegisterRouter.scala:87:24]
wire out_woready_1_599; // @[RegisterRouter.scala:87:24]
wire out_woready_1_600; // @[RegisterRouter.scala:87:24]
wire out_woready_1_601; // @[RegisterRouter.scala:87:24]
wire out_woready_1_602; // @[RegisterRouter.scala:87:24]
wire out_woready_1_603; // @[RegisterRouter.scala:87:24]
wire out_woready_1_604; // @[RegisterRouter.scala:87:24]
wire out_woready_1_605; // @[RegisterRouter.scala:87:24]
wire out_woready_1_606; // @[RegisterRouter.scala:87:24]
wire out_woready_1_607; // @[RegisterRouter.scala:87:24]
wire out_woready_1_608; // @[RegisterRouter.scala:87:24]
wire out_woready_1_609; // @[RegisterRouter.scala:87:24]
wire out_woready_1_610; // @[RegisterRouter.scala:87:24]
wire out_woready_1_611; // @[RegisterRouter.scala:87:24]
wire out_woready_1_612; // @[RegisterRouter.scala:87:24]
wire out_woready_1_613; // @[RegisterRouter.scala:87:24]
wire out_woready_1_614; // @[RegisterRouter.scala:87:24]
wire out_woready_1_615; // @[RegisterRouter.scala:87:24]
wire out_woready_1_616; // @[RegisterRouter.scala:87:24]
wire out_woready_1_617; // @[RegisterRouter.scala:87:24]
wire out_woready_1_618; // @[RegisterRouter.scala:87:24]
wire out_woready_1_619; // @[RegisterRouter.scala:87:24]
wire out_woready_1_620; // @[RegisterRouter.scala:87:24]
wire out_woready_1_621; // @[RegisterRouter.scala:87:24]
wire out_woready_1_622; // @[RegisterRouter.scala:87:24]
wire out_woready_1_623; // @[RegisterRouter.scala:87:24]
wire out_woready_1_624; // @[RegisterRouter.scala:87:24]
wire out_woready_1_625; // @[RegisterRouter.scala:87:24]
wire out_woready_1_626; // @[RegisterRouter.scala:87:24]
wire out_woready_1_627; // @[RegisterRouter.scala:87:24]
wire out_woready_1_628; // @[RegisterRouter.scala:87:24]
wire out_woready_1_629; // @[RegisterRouter.scala:87:24]
wire out_woready_1_630; // @[RegisterRouter.scala:87:24]
wire out_woready_1_631; // @[RegisterRouter.scala:87:24]
wire out_woready_1_632; // @[RegisterRouter.scala:87:24]
wire out_woready_1_633; // @[RegisterRouter.scala:87:24]
wire out_woready_1_634; // @[RegisterRouter.scala:87:24]
wire out_woready_1_635; // @[RegisterRouter.scala:87:24]
wire out_woready_1_636; // @[RegisterRouter.scala:87:24]
wire out_woready_1_637; // @[RegisterRouter.scala:87:24]
wire out_woready_1_638; // @[RegisterRouter.scala:87:24]
wire out_woready_1_639; // @[RegisterRouter.scala:87:24]
wire out_woready_1_640; // @[RegisterRouter.scala:87:24]
wire out_woready_1_641; // @[RegisterRouter.scala:87:24]
wire out_woready_1_642; // @[RegisterRouter.scala:87:24]
wire out_woready_1_643; // @[RegisterRouter.scala:87:24]
wire out_woready_1_644; // @[RegisterRouter.scala:87:24]
wire out_woready_1_645; // @[RegisterRouter.scala:87:24]
wire out_woready_1_646; // @[RegisterRouter.scala:87:24]
wire out_woready_1_647; // @[RegisterRouter.scala:87:24]
wire out_woready_1_648; // @[RegisterRouter.scala:87:24]
wire out_woready_1_649; // @[RegisterRouter.scala:87:24]
wire out_woready_1_650; // @[RegisterRouter.scala:87:24]
wire out_woready_1_651; // @[RegisterRouter.scala:87:24]
wire out_woready_1_652; // @[RegisterRouter.scala:87:24]
wire out_woready_1_653; // @[RegisterRouter.scala:87:24]
wire out_woready_1_654; // @[RegisterRouter.scala:87:24]
wire out_woready_1_655; // @[RegisterRouter.scala:87:24]
wire out_woready_1_656; // @[RegisterRouter.scala:87:24]
wire out_woready_1_657; // @[RegisterRouter.scala:87:24]
wire out_woready_1_658; // @[RegisterRouter.scala:87:24]
wire out_woready_1_659; // @[RegisterRouter.scala:87:24]
wire out_woready_1_660; // @[RegisterRouter.scala:87:24]
wire out_woready_1_661; // @[RegisterRouter.scala:87:24]
wire out_woready_1_662; // @[RegisterRouter.scala:87:24]
wire out_woready_1_663; // @[RegisterRouter.scala:87:24]
wire out_woready_1_664; // @[RegisterRouter.scala:87:24]
wire out_woready_1_665; // @[RegisterRouter.scala:87:24]
wire out_woready_1_666; // @[RegisterRouter.scala:87:24]
wire out_woready_1_667; // @[RegisterRouter.scala:87:24]
wire out_woready_1_668; // @[RegisterRouter.scala:87:24]
wire out_woready_1_669; // @[RegisterRouter.scala:87:24]
wire out_woready_1_670; // @[RegisterRouter.scala:87:24]
wire out_woready_1_671; // @[RegisterRouter.scala:87:24]
wire out_woready_1_672; // @[RegisterRouter.scala:87:24]
wire out_woready_1_673; // @[RegisterRouter.scala:87:24]
wire out_woready_1_674; // @[RegisterRouter.scala:87:24]
wire out_woready_1_675; // @[RegisterRouter.scala:87:24]
wire out_woready_1_676; // @[RegisterRouter.scala:87:24]
wire out_woready_1_677; // @[RegisterRouter.scala:87:24]
wire out_woready_1_678; // @[RegisterRouter.scala:87:24]
wire out_woready_1_679; // @[RegisterRouter.scala:87:24]
wire out_woready_1_680; // @[RegisterRouter.scala:87:24]
wire out_woready_1_681; // @[RegisterRouter.scala:87:24]
wire out_woready_1_682; // @[RegisterRouter.scala:87:24]
wire out_woready_1_683; // @[RegisterRouter.scala:87:24]
wire out_woready_1_684; // @[RegisterRouter.scala:87:24]
wire out_woready_1_685; // @[RegisterRouter.scala:87:24]
wire out_woready_1_686; // @[RegisterRouter.scala:87:24]
wire out_woready_1_687; // @[RegisterRouter.scala:87:24]
wire out_woready_1_688; // @[RegisterRouter.scala:87:24]
wire out_woready_1_689; // @[RegisterRouter.scala:87:24]
wire out_woready_1_690; // @[RegisterRouter.scala:87:24]
wire out_woready_1_691; // @[RegisterRouter.scala:87:24]
wire out_woready_1_692; // @[RegisterRouter.scala:87:24]
wire out_woready_1_693; // @[RegisterRouter.scala:87:24]
wire out_woready_1_694; // @[RegisterRouter.scala:87:24]
wire out_woready_1_695; // @[RegisterRouter.scala:87:24]
wire out_woready_1_696; // @[RegisterRouter.scala:87:24]
wire out_woready_1_697; // @[RegisterRouter.scala:87:24]
wire out_woready_1_698; // @[RegisterRouter.scala:87:24]
wire out_woready_1_699; // @[RegisterRouter.scala:87:24]
wire out_woready_1_700; // @[RegisterRouter.scala:87:24]
wire out_woready_1_701; // @[RegisterRouter.scala:87:24]
wire out_woready_1_702; // @[RegisterRouter.scala:87:24]
wire out_woready_1_703; // @[RegisterRouter.scala:87:24]
wire out_woready_1_704; // @[RegisterRouter.scala:87:24]
wire out_woready_1_705; // @[RegisterRouter.scala:87:24]
wire out_woready_1_706; // @[RegisterRouter.scala:87:24]
wire out_woready_1_707; // @[RegisterRouter.scala:87:24]
wire out_woready_1_708; // @[RegisterRouter.scala:87:24]
wire out_woready_1_709; // @[RegisterRouter.scala:87:24]
wire out_woready_1_710; // @[RegisterRouter.scala:87:24]
wire out_woready_1_711; // @[RegisterRouter.scala:87:24]
wire out_woready_1_712; // @[RegisterRouter.scala:87:24]
wire out_woready_1_713; // @[RegisterRouter.scala:87:24]
wire out_woready_1_714; // @[RegisterRouter.scala:87:24]
wire out_woready_1_715; // @[RegisterRouter.scala:87:24]
wire out_woready_1_716; // @[RegisterRouter.scala:87:24]
wire out_woready_1_717; // @[RegisterRouter.scala:87:24]
wire out_woready_1_718; // @[RegisterRouter.scala:87:24]
wire out_woready_1_719; // @[RegisterRouter.scala:87:24]
wire out_woready_1_720; // @[RegisterRouter.scala:87:24]
wire out_woready_1_721; // @[RegisterRouter.scala:87:24]
wire out_woready_1_722; // @[RegisterRouter.scala:87:24]
wire out_woready_1_723; // @[RegisterRouter.scala:87:24]
wire out_woready_1_724; // @[RegisterRouter.scala:87:24]
wire out_woready_1_725; // @[RegisterRouter.scala:87:24]
wire out_woready_1_726; // @[RegisterRouter.scala:87:24]
wire out_woready_1_727; // @[RegisterRouter.scala:87:24]
wire out_woready_1_728; // @[RegisterRouter.scala:87:24]
wire out_woready_1_729; // @[RegisterRouter.scala:87:24]
wire out_woready_1_730; // @[RegisterRouter.scala:87:24]
wire out_woready_1_731; // @[RegisterRouter.scala:87:24]
wire out_woready_1_732; // @[RegisterRouter.scala:87:24]
wire out_woready_1_733; // @[RegisterRouter.scala:87:24]
wire out_woready_1_734; // @[RegisterRouter.scala:87:24]
wire out_woready_1_735; // @[RegisterRouter.scala:87:24]
wire out_woready_1_736; // @[RegisterRouter.scala:87:24]
wire out_woready_1_737; // @[RegisterRouter.scala:87:24]
wire out_woready_1_738; // @[RegisterRouter.scala:87:24]
wire out_woready_1_739; // @[RegisterRouter.scala:87:24]
wire out_woready_1_740; // @[RegisterRouter.scala:87:24]
wire out_woready_1_741; // @[RegisterRouter.scala:87:24]
wire out_woready_1_742; // @[RegisterRouter.scala:87:24]
wire out_woready_1_743; // @[RegisterRouter.scala:87:24]
wire out_woready_1_744; // @[RegisterRouter.scala:87:24]
wire out_woready_1_745; // @[RegisterRouter.scala:87:24]
wire out_woready_1_746; // @[RegisterRouter.scala:87:24]
wire out_woready_1_747; // @[RegisterRouter.scala:87:24]
wire out_woready_1_748; // @[RegisterRouter.scala:87:24]
wire out_woready_1_749; // @[RegisterRouter.scala:87:24]
wire out_woready_1_750; // @[RegisterRouter.scala:87:24]
wire out_woready_1_751; // @[RegisterRouter.scala:87:24]
wire out_woready_1_752; // @[RegisterRouter.scala:87:24]
wire out_woready_1_753; // @[RegisterRouter.scala:87:24]
wire out_woready_1_754; // @[RegisterRouter.scala:87:24]
wire out_woready_1_755; // @[RegisterRouter.scala:87:24]
wire out_woready_1_756; // @[RegisterRouter.scala:87:24]
wire out_woready_1_757; // @[RegisterRouter.scala:87:24]
wire out_woready_1_758; // @[RegisterRouter.scala:87:24]
wire out_woready_1_759; // @[RegisterRouter.scala:87:24]
wire out_woready_1_760; // @[RegisterRouter.scala:87:24]
wire out_woready_1_761; // @[RegisterRouter.scala:87:24]
wire out_woready_1_762; // @[RegisterRouter.scala:87:24]
wire out_woready_1_763; // @[RegisterRouter.scala:87:24]
wire out_woready_1_764; // @[RegisterRouter.scala:87:24]
wire out_woready_1_765; // @[RegisterRouter.scala:87:24]
wire out_woready_1_766; // @[RegisterRouter.scala:87:24]
wire out_woready_1_767; // @[RegisterRouter.scala:87:24]
wire out_woready_1_768; // @[RegisterRouter.scala:87:24]
wire out_woready_1_769; // @[RegisterRouter.scala:87:24]
wire out_woready_1_770; // @[RegisterRouter.scala:87:24]
wire out_woready_1_771; // @[RegisterRouter.scala:87:24]
wire out_woready_1_772; // @[RegisterRouter.scala:87:24]
wire out_woready_1_773; // @[RegisterRouter.scala:87:24]
wire out_woready_1_774; // @[RegisterRouter.scala:87:24]
wire out_woready_1_775; // @[RegisterRouter.scala:87:24]
wire out_woready_1_776; // @[RegisterRouter.scala:87:24]
wire out_woready_1_777; // @[RegisterRouter.scala:87:24]
wire out_woready_1_778; // @[RegisterRouter.scala:87:24]
wire out_woready_1_779; // @[RegisterRouter.scala:87:24]
wire out_woready_1_780; // @[RegisterRouter.scala:87:24]
wire out_woready_1_781; // @[RegisterRouter.scala:87:24]
wire out_woready_1_782; // @[RegisterRouter.scala:87:24]
wire out_woready_1_783; // @[RegisterRouter.scala:87:24]
wire out_woready_1_784; // @[RegisterRouter.scala:87:24]
wire out_woready_1_785; // @[RegisterRouter.scala:87:24]
wire out_woready_1_786; // @[RegisterRouter.scala:87:24]
wire out_woready_1_787; // @[RegisterRouter.scala:87:24]
wire out_woready_1_788; // @[RegisterRouter.scala:87:24]
wire out_woready_1_789; // @[RegisterRouter.scala:87:24]
wire out_woready_1_790; // @[RegisterRouter.scala:87:24]
wire out_woready_1_791; // @[RegisterRouter.scala:87:24]
wire out_woready_1_792; // @[RegisterRouter.scala:87:24]
wire out_woready_1_793; // @[RegisterRouter.scala:87:24]
wire out_woready_1_794; // @[RegisterRouter.scala:87:24]
wire out_woready_1_795; // @[RegisterRouter.scala:87:24]
wire out_woready_1_796; // @[RegisterRouter.scala:87:24]
wire out_woready_1_797; // @[RegisterRouter.scala:87:24]
wire out_woready_1_798; // @[RegisterRouter.scala:87:24]
wire out_woready_1_799; // @[RegisterRouter.scala:87:24]
wire out_woready_1_800; // @[RegisterRouter.scala:87:24]
wire out_woready_1_801; // @[RegisterRouter.scala:87:24]
wire out_woready_1_802; // @[RegisterRouter.scala:87:24]
wire out_woready_1_803; // @[RegisterRouter.scala:87:24]
wire out_woready_1_804; // @[RegisterRouter.scala:87:24]
wire out_woready_1_805; // @[RegisterRouter.scala:87:24]
wire out_woready_1_806; // @[RegisterRouter.scala:87:24]
wire out_woready_1_807; // @[RegisterRouter.scala:87:24]
wire out_woready_1_808; // @[RegisterRouter.scala:87:24]
wire out_woready_1_809; // @[RegisterRouter.scala:87:24]
wire out_woready_1_810; // @[RegisterRouter.scala:87:24]
wire out_woready_1_811; // @[RegisterRouter.scala:87:24]
wire out_woready_1_812; // @[RegisterRouter.scala:87:24]
wire out_woready_1_813; // @[RegisterRouter.scala:87:24]
wire out_woready_1_814; // @[RegisterRouter.scala:87:24]
wire out_woready_1_815; // @[RegisterRouter.scala:87:24]
wire out_woready_1_816; // @[RegisterRouter.scala:87:24]
wire out_woready_1_817; // @[RegisterRouter.scala:87:24]
wire out_woready_1_818; // @[RegisterRouter.scala:87:24]
wire out_woready_1_819; // @[RegisterRouter.scala:87:24]
wire out_woready_1_820; // @[RegisterRouter.scala:87:24]
wire out_woready_1_821; // @[RegisterRouter.scala:87:24]
wire out_woready_1_822; // @[RegisterRouter.scala:87:24]
wire out_woready_1_823; // @[RegisterRouter.scala:87:24]
wire out_woready_1_824; // @[RegisterRouter.scala:87:24]
wire out_woready_1_825; // @[RegisterRouter.scala:87:24]
wire out_woready_1_826; // @[RegisterRouter.scala:87:24]
wire out_woready_1_827; // @[RegisterRouter.scala:87:24]
wire out_woready_1_828; // @[RegisterRouter.scala:87:24]
wire out_woready_1_829; // @[RegisterRouter.scala:87:24]
wire out_woready_1_830; // @[RegisterRouter.scala:87:24]
wire out_woready_1_831; // @[RegisterRouter.scala:87:24]
wire out_woready_1_832; // @[RegisterRouter.scala:87:24]
wire out_woready_1_833; // @[RegisterRouter.scala:87:24]
wire out_woready_1_834; // @[RegisterRouter.scala:87:24]
wire out_woready_1_835; // @[RegisterRouter.scala:87:24]
wire out_woready_1_836; // @[RegisterRouter.scala:87:24]
wire out_woready_1_837; // @[RegisterRouter.scala:87:24]
wire out_woready_1_838; // @[RegisterRouter.scala:87:24]
wire out_woready_1_839; // @[RegisterRouter.scala:87:24]
wire out_woready_1_840; // @[RegisterRouter.scala:87:24]
wire out_woready_1_841; // @[RegisterRouter.scala:87:24]
wire out_woready_1_842; // @[RegisterRouter.scala:87:24]
wire out_woready_1_843; // @[RegisterRouter.scala:87:24]
wire out_woready_1_844; // @[RegisterRouter.scala:87:24]
wire out_woready_1_845; // @[RegisterRouter.scala:87:24]
wire out_woready_1_846; // @[RegisterRouter.scala:87:24]
wire out_woready_1_847; // @[RegisterRouter.scala:87:24]
wire out_woready_1_848; // @[RegisterRouter.scala:87:24]
wire out_woready_1_849; // @[RegisterRouter.scala:87:24]
wire out_woready_1_850; // @[RegisterRouter.scala:87:24]
wire out_woready_1_851; // @[RegisterRouter.scala:87:24]
wire out_woready_1_852; // @[RegisterRouter.scala:87:24]
wire out_woready_1_853; // @[RegisterRouter.scala:87:24]
wire out_woready_1_854; // @[RegisterRouter.scala:87:24]
wire out_woready_1_855; // @[RegisterRouter.scala:87:24]
wire out_woready_1_856; // @[RegisterRouter.scala:87:24]
wire out_woready_1_857; // @[RegisterRouter.scala:87:24]
wire out_woready_1_858; // @[RegisterRouter.scala:87:24]
wire out_woready_1_859; // @[RegisterRouter.scala:87:24]
wire out_woready_1_860; // @[RegisterRouter.scala:87:24]
wire out_woready_1_861; // @[RegisterRouter.scala:87:24]
wire out_woready_1_862; // @[RegisterRouter.scala:87:24]
wire out_woready_1_863; // @[RegisterRouter.scala:87:24]
wire out_woready_1_864; // @[RegisterRouter.scala:87:24]
wire out_woready_1_865; // @[RegisterRouter.scala:87:24]
wire out_woready_1_866; // @[RegisterRouter.scala:87:24]
wire out_woready_1_867; // @[RegisterRouter.scala:87:24]
wire out_woready_1_868; // @[RegisterRouter.scala:87:24]
wire out_woready_1_869; // @[RegisterRouter.scala:87:24]
wire out_woready_1_870; // @[RegisterRouter.scala:87:24]
wire out_woready_1_871; // @[RegisterRouter.scala:87:24]
wire out_woready_1_872; // @[RegisterRouter.scala:87:24]
wire out_woready_1_873; // @[RegisterRouter.scala:87:24]
wire out_woready_1_874; // @[RegisterRouter.scala:87:24]
wire out_woready_1_875; // @[RegisterRouter.scala:87:24]
wire out_woready_1_876; // @[RegisterRouter.scala:87:24]
wire out_woready_1_877; // @[RegisterRouter.scala:87:24]
wire out_woready_1_878; // @[RegisterRouter.scala:87:24]
wire out_woready_1_879; // @[RegisterRouter.scala:87:24]
wire out_woready_1_880; // @[RegisterRouter.scala:87:24]
wire out_woready_1_881; // @[RegisterRouter.scala:87:24]
wire out_woready_1_882; // @[RegisterRouter.scala:87:24]
wire out_woready_1_883; // @[RegisterRouter.scala:87:24]
wire out_woready_1_884; // @[RegisterRouter.scala:87:24]
wire out_woready_1_885; // @[RegisterRouter.scala:87:24]
wire out_woready_1_886; // @[RegisterRouter.scala:87:24]
wire out_woready_1_887; // @[RegisterRouter.scala:87:24]
wire out_woready_1_888; // @[RegisterRouter.scala:87:24]
wire out_woready_1_889; // @[RegisterRouter.scala:87:24]
wire out_woready_1_890; // @[RegisterRouter.scala:87:24]
wire out_woready_1_891; // @[RegisterRouter.scala:87:24]
wire out_woready_1_892; // @[RegisterRouter.scala:87:24]
wire out_woready_1_893; // @[RegisterRouter.scala:87:24]
wire out_woready_1_894; // @[RegisterRouter.scala:87:24]
wire out_woready_1_895; // @[RegisterRouter.scala:87:24]
wire out_woready_1_896; // @[RegisterRouter.scala:87:24]
wire out_woready_1_897; // @[RegisterRouter.scala:87:24]
wire out_woready_1_898; // @[RegisterRouter.scala:87:24]
wire out_woready_1_899; // @[RegisterRouter.scala:87:24]
wire out_woready_1_900; // @[RegisterRouter.scala:87:24]
wire out_woready_1_901; // @[RegisterRouter.scala:87:24]
wire out_woready_1_902; // @[RegisterRouter.scala:87:24]
wire out_woready_1_903; // @[RegisterRouter.scala:87:24]
wire out_woready_1_904; // @[RegisterRouter.scala:87:24]
wire out_woready_1_905; // @[RegisterRouter.scala:87:24]
wire out_woready_1_906; // @[RegisterRouter.scala:87:24]
wire out_woready_1_907; // @[RegisterRouter.scala:87:24]
wire out_woready_1_908; // @[RegisterRouter.scala:87:24]
wire out_woready_1_909; // @[RegisterRouter.scala:87:24]
wire out_woready_1_910; // @[RegisterRouter.scala:87:24]
wire out_woready_1_911; // @[RegisterRouter.scala:87:24]
wire out_woready_1_912; // @[RegisterRouter.scala:87:24]
wire out_woready_1_913; // @[RegisterRouter.scala:87:24]
wire out_woready_1_914; // @[RegisterRouter.scala:87:24]
wire out_woready_1_915; // @[RegisterRouter.scala:87:24]
wire out_woready_1_916; // @[RegisterRouter.scala:87:24]
wire out_woready_1_917; // @[RegisterRouter.scala:87:24]
wire out_woready_1_918; // @[RegisterRouter.scala:87:24]
wire out_woready_1_919; // @[RegisterRouter.scala:87:24]
wire out_woready_1_920; // @[RegisterRouter.scala:87:24]
wire out_woready_1_921; // @[RegisterRouter.scala:87:24]
wire out_woready_1_922; // @[RegisterRouter.scala:87:24]
wire out_woready_1_923; // @[RegisterRouter.scala:87:24]
wire out_woready_1_924; // @[RegisterRouter.scala:87:24]
wire out_woready_1_925; // @[RegisterRouter.scala:87:24]
wire out_woready_1_926; // @[RegisterRouter.scala:87:24]
wire out_woready_1_927; // @[RegisterRouter.scala:87:24]
wire out_woready_1_928; // @[RegisterRouter.scala:87:24]
wire out_woready_1_929; // @[RegisterRouter.scala:87:24]
wire out_woready_1_930; // @[RegisterRouter.scala:87:24]
wire out_woready_1_931; // @[RegisterRouter.scala:87:24]
wire out_woready_1_932; // @[RegisterRouter.scala:87:24]
wire out_woready_1_933; // @[RegisterRouter.scala:87:24]
wire out_woready_1_934; // @[RegisterRouter.scala:87:24]
wire out_woready_1_935; // @[RegisterRouter.scala:87:24]
wire out_woready_1_936; // @[RegisterRouter.scala:87:24]
wire out_woready_1_937; // @[RegisterRouter.scala:87:24]
wire out_woready_1_938; // @[RegisterRouter.scala:87:24]
wire out_woready_1_939; // @[RegisterRouter.scala:87:24]
wire out_woready_1_940; // @[RegisterRouter.scala:87:24]
wire out_woready_1_941; // @[RegisterRouter.scala:87:24]
wire out_woready_1_942; // @[RegisterRouter.scala:87:24]
wire out_woready_1_943; // @[RegisterRouter.scala:87:24]
wire out_woready_1_944; // @[RegisterRouter.scala:87:24]
wire out_woready_1_945; // @[RegisterRouter.scala:87:24]
wire out_woready_1_946; // @[RegisterRouter.scala:87:24]
wire out_woready_1_947; // @[RegisterRouter.scala:87:24]
wire out_woready_1_948; // @[RegisterRouter.scala:87:24]
wire out_woready_1_949; // @[RegisterRouter.scala:87:24]
wire out_woready_1_950; // @[RegisterRouter.scala:87:24]
wire out_woready_1_951; // @[RegisterRouter.scala:87:24]
wire out_woready_1_952; // @[RegisterRouter.scala:87:24]
wire out_woready_1_953; // @[RegisterRouter.scala:87:24]
wire out_woready_1_954; // @[RegisterRouter.scala:87:24]
wire out_woready_1_955; // @[RegisterRouter.scala:87:24]
wire out_woready_1_956; // @[RegisterRouter.scala:87:24]
wire out_woready_1_957; // @[RegisterRouter.scala:87:24]
wire out_woready_1_958; // @[RegisterRouter.scala:87:24]
wire out_woready_1_959; // @[RegisterRouter.scala:87:24]
wire out_woready_1_960; // @[RegisterRouter.scala:87:24]
wire out_woready_1_961; // @[RegisterRouter.scala:87:24]
wire out_woready_1_962; // @[RegisterRouter.scala:87:24]
wire out_woready_1_963; // @[RegisterRouter.scala:87:24]
wire out_woready_1_964; // @[RegisterRouter.scala:87:24]
wire out_woready_1_965; // @[RegisterRouter.scala:87:24]
wire out_woready_1_966; // @[RegisterRouter.scala:87:24]
wire out_woready_1_967; // @[RegisterRouter.scala:87:24]
wire out_woready_1_968; // @[RegisterRouter.scala:87:24]
wire out_woready_1_969; // @[RegisterRouter.scala:87:24]
wire out_woready_1_970; // @[RegisterRouter.scala:87:24]
wire out_woready_1_971; // @[RegisterRouter.scala:87:24]
wire out_woready_1_972; // @[RegisterRouter.scala:87:24]
wire out_woready_1_973; // @[RegisterRouter.scala:87:24]
wire out_woready_1_974; // @[RegisterRouter.scala:87:24]
wire out_woready_1_975; // @[RegisterRouter.scala:87:24]
wire out_woready_1_976; // @[RegisterRouter.scala:87:24]
wire out_woready_1_977; // @[RegisterRouter.scala:87:24]
wire out_woready_1_978; // @[RegisterRouter.scala:87:24]
wire out_woready_1_979; // @[RegisterRouter.scala:87:24]
wire out_woready_1_980; // @[RegisterRouter.scala:87:24]
wire out_woready_1_981; // @[RegisterRouter.scala:87:24]
wire out_woready_1_982; // @[RegisterRouter.scala:87:24]
wire out_woready_1_983; // @[RegisterRouter.scala:87:24]
wire out_woready_1_984; // @[RegisterRouter.scala:87:24]
wire out_woready_1_985; // @[RegisterRouter.scala:87:24]
wire out_woready_1_986; // @[RegisterRouter.scala:87:24]
wire out_woready_1_987; // @[RegisterRouter.scala:87:24]
wire out_woready_1_988; // @[RegisterRouter.scala:87:24]
wire out_woready_1_989; // @[RegisterRouter.scala:87:24]
wire out_woready_1_990; // @[RegisterRouter.scala:87:24]
wire out_woready_1_991; // @[RegisterRouter.scala:87:24]
wire out_woready_1_992; // @[RegisterRouter.scala:87:24]
wire out_woready_1_993; // @[RegisterRouter.scala:87:24]
wire out_woready_1_994; // @[RegisterRouter.scala:87:24]
wire out_woready_1_995; // @[RegisterRouter.scala:87:24]
wire out_woready_1_996; // @[RegisterRouter.scala:87:24]
wire out_woready_1_997; // @[RegisterRouter.scala:87:24]
wire out_woready_1_998; // @[RegisterRouter.scala:87:24]
wire out_woready_1_999; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1000; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1001; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1002; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1003; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1004; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1005; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1006; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1007; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1008; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1009; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1010; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1011; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1012; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1013; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1014; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1015; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1016; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1017; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1018; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1019; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1020; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1021; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1022; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1023; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1024; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1025; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1026; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1027; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1028; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1029; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1030; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1031; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1032; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1033; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1034; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1035; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1036; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1037; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1038; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1039; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1040; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1041; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1042; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1043; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1044; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1045; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1046; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1047; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1048; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1049; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1050; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1051; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1052; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1053; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1054; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1055; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1056; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1057; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1058; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1059; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1060; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1061; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1062; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1063; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1064; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1065; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1066; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1067; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1068; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1069; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1070; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1071; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1072; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1073; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1074; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1075; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1076; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1077; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1078; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1079; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1080; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1081; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1082; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1083; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1084; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1085; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1086; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1087; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1088; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1089; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1090; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1091; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1092; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1093; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1094; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1095; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1096; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1097; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1098; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1099; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1100; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1101; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1102; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1103; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1104; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1105; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1106; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1107; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1108; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1109; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1110; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1111; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1112; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1113; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1114; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1115; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1116; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1117; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1118; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1119; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1120; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1121; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1122; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1123; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1124; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1125; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1126; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1127; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1128; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1129; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1130; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1131; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1132; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1133; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1134; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1135; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1136; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1137; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1138; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1139; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1140; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1141; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1142; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1143; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1144; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1145; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1146; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1147; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1148; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1149; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1150; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1151; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1152; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1153; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1154; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1155; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1156; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1157; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1158; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1159; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1160; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1161; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1162; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1163; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1164; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1165; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1166; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1167; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1168; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1169; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1170; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1171; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1172; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1173; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1174; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1175; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1176; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1177; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1178; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1179; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1180; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1181; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1182; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1183; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1184; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1185; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1186; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1187; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1188; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1189; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1190; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1191; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1192; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1193; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1194; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1195; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1196; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1197; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1198; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1199; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1200; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1201; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1202; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1203; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1204; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1205; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1206; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1207; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1208; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1209; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1210; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_8 = out_front_1_bits_mask[0]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_8 = out_front_1_bits_mask[0]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_9 = out_front_1_bits_mask[1]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_9 = out_front_1_bits_mask[1]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_10 = out_front_1_bits_mask[2]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_10 = out_front_1_bits_mask[2]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_11 = out_front_1_bits_mask[3]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_11 = out_front_1_bits_mask[3]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_12 = out_front_1_bits_mask[4]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_12 = out_front_1_bits_mask[4]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_13 = out_front_1_bits_mask[5]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_13 = out_front_1_bits_mask[5]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_14 = out_front_1_bits_mask[6]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_14 = out_front_1_bits_mask[6]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_15 = out_front_1_bits_mask[7]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_15 = out_front_1_bits_mask[7]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_16 = {8{_out_frontMask_T_8}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_17 = {8{_out_frontMask_T_9}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_18 = {8{_out_frontMask_T_10}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_19 = {8{_out_frontMask_T_11}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_20 = {8{_out_frontMask_T_12}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_21 = {8{_out_frontMask_T_13}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_22 = {8{_out_frontMask_T_14}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_23 = {8{_out_frontMask_T_15}}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_frontMask_lo_lo = {_out_frontMask_T_17, _out_frontMask_T_16}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_frontMask_lo_hi = {_out_frontMask_T_19, _out_frontMask_T_18}; // @[RegisterRouter.scala:87:24]
wire [31:0] out_frontMask_lo_1 = {out_frontMask_lo_hi, out_frontMask_lo_lo}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_frontMask_hi_lo = {_out_frontMask_T_21, _out_frontMask_T_20}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_frontMask_hi_hi = {_out_frontMask_T_23, _out_frontMask_T_22}; // @[RegisterRouter.scala:87:24]
wire [31:0] out_frontMask_hi_1 = {out_frontMask_hi_hi, out_frontMask_hi_lo}; // @[RegisterRouter.scala:87:24]
wire [63:0] out_frontMask_1 = {out_frontMask_hi_1, out_frontMask_lo_1}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_16 = {8{_out_backMask_T_8}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_17 = {8{_out_backMask_T_9}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_18 = {8{_out_backMask_T_10}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_19 = {8{_out_backMask_T_11}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_20 = {8{_out_backMask_T_12}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_21 = {8{_out_backMask_T_13}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_22 = {8{_out_backMask_T_14}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_23 = {8{_out_backMask_T_15}}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_backMask_lo_lo = {_out_backMask_T_17, _out_backMask_T_16}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_backMask_lo_hi = {_out_backMask_T_19, _out_backMask_T_18}; // @[RegisterRouter.scala:87:24]
wire [31:0] out_backMask_lo_1 = {out_backMask_lo_hi, out_backMask_lo_lo}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_backMask_hi_lo = {_out_backMask_T_21, _out_backMask_T_20}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_backMask_hi_hi = {_out_backMask_T_23, _out_backMask_T_22}; // @[RegisterRouter.scala:87:24]
wire [31:0] out_backMask_hi_1 = {out_backMask_hi_hi, out_backMask_hi_lo}; // @[RegisterRouter.scala:87:24]
wire [63:0] out_backMask_1 = {out_backMask_hi_1, out_backMask_lo_1}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_146 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_146 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_154 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_154 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_162 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_162 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_170 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_170 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_178 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_178 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_186 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_186 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_194 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_194 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_202 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_202 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_210 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_210 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_218 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_218 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_226 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_226 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_234 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_234 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_242 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_242 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_250 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_250 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_258 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_258 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_266 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_266 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_274 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_274 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_282 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_282 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_290 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_290 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_298 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_298 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_306 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_306 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_314 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_314 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_322 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_322 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_330 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_330 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_338 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_338 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_346 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_346 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_354 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_354 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_362 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_362 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_370 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_370 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_378 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_378 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_386 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_386 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_394 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_394 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_402 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_402 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_410 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_410 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_418 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_418 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_426 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_426 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_434 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_434 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_442 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_442 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_450 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_450 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_458 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_458 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_466 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_466 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_474 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_474 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_482 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_482 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_490 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_490 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_500 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_500 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_508 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_508 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_516 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_516 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_524 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_524 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_532 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_532 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_540 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_540 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_548 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_548 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_556 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_556 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_564 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_564 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_572 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_572 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_580 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_580 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_589 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_589 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_597 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_597 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_605 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_605 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_613 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_613 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_621 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_621 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_629 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_629 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_633 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_633 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_641 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_641 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_649 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_649 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_657 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_657 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_665 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_665 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_673 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_673 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_683 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_683 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_691 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_691 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_699 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_699 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_707 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_707 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_715 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_715 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_723 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_723 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_731 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_731 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_739 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_739 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_747 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_747 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_755 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_755 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_763 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_763 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_771 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_771 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_779 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_779 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_787 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_787 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_795 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_795 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_803 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_803 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_811 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_811 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_819 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_819 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_827 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_827 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_835 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_835 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_845 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_845 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_853 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_853 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_861 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_861 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_869 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_869 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_877 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_877 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_885 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_885 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_893 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_893 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_901 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_901 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_909 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_909 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_917 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_917 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_925 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_925 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_933 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_933 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_941 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_941 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_949 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_949 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_957 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_957 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_965 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_965 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_973 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_973 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_981 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_981 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_989 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_989 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_997 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_997 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1005 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1005 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1013 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1013 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1021 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1021 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1029 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1029 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1037 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1037 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1045 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1045 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1053 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1053 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1061 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1061 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1069 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1069 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1077 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1077 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1085 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1085 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1093 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1093 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1101 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1101 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1109 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1109 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1117 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1117 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1125 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1125 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1133 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1133 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1141 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1141 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1149 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1149 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1157 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1157 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1165 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1165 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1173 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1173 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1181 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1181 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1189 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1189 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1197 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1197 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1205 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1205 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1213 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1213 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1221 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1221 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1229 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1229 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1237 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1237 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1245 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1245 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1253 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1253 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1261 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1261 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1269 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1269 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1277 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1277 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1285 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1285 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1293 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1293 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1301 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1301 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1309 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1309 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1317 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1317 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1325 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1325 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1333 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1333 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1341 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1341 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1349 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1349 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire out_rimask_146 = |_out_rimask_T_146; // @[RegisterRouter.scala:87:24]
wire out_wimask_146 = &_out_wimask_T_146; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_146 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_146 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_154 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_154 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_162 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_162 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_170 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_170 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_178 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_178 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_186 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_186 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_194 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_194 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_202 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_202 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_210 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_210 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_218 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_218 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_226 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_226 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_234 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_234 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_242 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_242 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_250 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_250 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_258 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_258 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_266 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_266 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_274 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_274 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_282 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_282 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_290 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_290 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_298 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_298 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_306 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_306 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_314 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_314 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_322 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_322 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_330 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_330 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_338 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_338 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_346 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_346 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_354 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_354 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_362 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_362 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_370 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_370 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_378 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_378 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_386 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_386 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_394 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_394 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_402 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_402 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_410 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_410 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_418 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_418 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_426 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_426 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_434 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_434 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_442 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_442 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_450 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_450 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_458 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_458 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_466 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_466 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_474 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_474 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_482 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_482 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_490 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_490 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_500 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_500 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_508 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_508 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_516 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_516 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_524 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_524 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_532 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_532 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_540 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_540 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_548 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_548 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_556 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_556 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_564 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_564 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_572 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_572 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_580 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_580 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_589 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_589 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_597 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_597 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_605 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_605 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_613 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_613 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_621 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_621 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_629 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_629 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_633 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_633 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_641 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_641 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_649 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_649 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_657 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_657 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_665 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_665 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_673 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_673 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_683 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_683 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_691 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_691 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_699 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_699 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_707 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_707 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_715 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_715 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_723 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_723 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_731 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_731 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_739 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_739 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_747 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_747 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_755 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_755 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_763 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_763 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_771 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_771 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_779 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_779 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_787 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_787 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_795 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_795 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_803 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_803 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_811 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_811 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_819 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_819 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_827 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_827 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_835 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_835 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_845 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_845 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_853 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_853 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_861 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_861 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_869 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_869 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_877 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_877 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_885 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_885 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_893 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_893 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_901 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_901 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_909 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_909 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_917 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_917 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_925 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_925 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_933 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_933 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_941 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_941 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_949 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_949 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_957 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_957 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_965 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_965 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_973 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_973 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_981 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_981 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_989 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_989 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_997 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_997 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1005 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1005 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1013 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1013 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1021 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1021 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1029 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1029 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1037 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1037 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1045 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1045 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1053 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1053 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1061 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1061 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1069 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1069 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1077 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1077 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1085 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1085 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1093 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1093 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1101 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1101 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1109 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1109 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1117 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1117 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1125 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1125 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1133 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1133 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1141 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1141 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1149 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1149 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1157 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1157 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1165 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1165 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1173 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1173 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1181 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1181 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1189 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1189 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1197 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1197 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1205 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1205 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1213 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1213 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1221 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1221 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1229 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1229 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1237 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1237 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1245 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1245 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1253 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1253 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1261 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1261 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1269 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1269 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1277 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1277 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1285 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1285 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1293 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1293 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1301 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1301 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1309 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1309 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1317 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1317 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1325 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1325 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1333 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1333 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1341 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1341 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1349 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1349 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire out_romask_146 = |_out_romask_T_146; // @[RegisterRouter.scala:87:24]
wire out_womask_146 = &_out_womask_T_146; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_146 = out_rivalid_1_0 & out_rimask_146; // @[RegisterRouter.scala:87:24]
wire _out_T_1911 = out_f_rivalid_146; // @[RegisterRouter.scala:87:24]
wire out_f_roready_146 = out_roready_1_0 & out_romask_146; // @[RegisterRouter.scala:87:24]
wire _out_T_1912 = out_f_roready_146; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_146 = out_wivalid_1_0 & out_wimask_146; // @[RegisterRouter.scala:87:24]
wire out_f_woready_146 = out_woready_1_0 & out_womask_146; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1910 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1982 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2054 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2126 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2198 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2286 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2358 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2430 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2502 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2574 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2646 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2718 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2790 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2862 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2934 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3022 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3094 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3166 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3238 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3310 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3382 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3454 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3526 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3598 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3670 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3758 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3830 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3902 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3974 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4046 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4118 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4190 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4262 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4334 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4406 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4478 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4550 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4622 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4694 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4766 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4838 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4910 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4982 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5054 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5144 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5216 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5288 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5360 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5432 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5504 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5576 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5648 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5720 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5792 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5864 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5945 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6033 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6105 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6177 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6249 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6321 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6357 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6429 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6501 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6573 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6661 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6733 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6823 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6895 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6967 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7039 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7111 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7183 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7255 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7327 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7399 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7471 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7543 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7615 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7687 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7759 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7831 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7903 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7991 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8063 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8135 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8207 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8297 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8369 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8441 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8513 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8585 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8673 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8745 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8817 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8889 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8961 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9033 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9105 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9177 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9249 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9321 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9393 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9465 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9553 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9625 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9697 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9769 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9841 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9913 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9985 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10057 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10129 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10201 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10273 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10345 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10417 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10505 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10577 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10649 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10721 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10793 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10865 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10953 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11025 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11097 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11169 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11241 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11313 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11385 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11457 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11529 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11601 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11673 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11745 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11817 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11889 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11977 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12049 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12121 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12193 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12265 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12337 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12409 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12481 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12553 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12641 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12713 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12785 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12857 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12929 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire _out_T_1913 = ~out_rimask_146; // @[RegisterRouter.scala:87:24]
wire _out_T_1914 = ~out_wimask_146; // @[RegisterRouter.scala:87:24]
wire _out_T_1915 = ~out_romask_146; // @[RegisterRouter.scala:87:24]
wire _out_T_1916 = ~out_womask_146; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1918 = _out_T_1917; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_112 = _out_T_1918; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_147 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_147 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_155 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_155 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_163 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_163 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_171 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_171 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_179 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_179 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_187 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_187 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_195 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_195 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_203 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_203 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_211 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_211 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_219 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_219 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_227 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_227 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_235 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_235 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_243 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_243 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_251 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_251 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_259 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_259 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_267 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_267 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_275 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_275 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_283 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_283 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_291 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_291 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_299 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_299 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_307 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_307 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_315 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_315 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_323 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_323 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_331 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_331 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_339 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_339 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_347 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_347 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_355 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_355 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_363 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_363 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_371 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_371 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_379 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_379 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_387 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_387 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_395 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_395 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_403 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_403 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_411 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_411 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_419 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_419 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_427 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_427 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_435 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_435 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_443 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_443 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_451 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_451 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_459 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_459 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_467 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_467 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_475 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_475 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_483 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_483 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_491 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_491 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_501 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_501 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_509 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_509 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_517 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_517 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_525 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_525 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_533 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_533 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_541 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_541 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_549 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_549 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_557 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_557 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_565 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_565 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_573 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_573 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_581 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_581 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_590 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_590 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_598 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_598 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_606 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_606 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_614 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_614 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_622 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_622 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_630 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_630 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_634 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_634 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_642 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_642 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_650 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_650 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_658 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_658 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_666 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_666 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_674 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_674 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_684 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_684 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_692 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_692 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_700 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_700 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_708 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_708 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_716 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_716 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_724 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_724 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_732 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_732 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_740 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_740 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_748 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_748 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_756 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_756 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_764 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_764 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_772 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_772 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_780 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_780 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_788 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_788 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_796 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_796 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_804 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_804 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_812 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_812 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_820 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_820 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_828 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_828 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_836 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_836 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_846 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_846 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_854 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_854 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_862 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_862 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_870 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_870 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_878 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_878 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_886 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_886 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_894 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_894 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_902 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_902 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_910 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_910 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_918 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_918 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_926 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_926 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_934 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_934 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_942 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_942 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_950 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_950 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_958 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_958 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_966 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_966 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_974 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_974 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_982 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_982 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_990 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_990 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_998 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_998 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1006 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1006 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1014 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1014 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1022 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1022 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1030 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1030 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1038 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1038 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1046 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1046 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1054 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1054 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1062 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1062 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1070 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1070 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1078 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1078 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1086 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1086 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1094 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1094 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1102 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1102 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1110 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1110 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1118 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1118 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1126 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1126 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1134 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1134 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1142 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1142 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1150 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1150 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1158 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1158 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1166 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1166 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1174 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1174 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1182 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1182 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1190 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1190 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1198 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1198 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1206 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1206 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1214 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1214 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1222 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1222 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1230 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1230 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1238 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1238 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1246 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1246 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1254 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1254 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1262 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1262 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1270 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1270 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1278 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1278 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1286 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1286 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1294 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1294 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1302 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1302 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1310 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1310 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1318 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1318 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1326 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1326 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1334 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1334 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1342 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1342 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1350 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1350 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire out_rimask_147 = |_out_rimask_T_147; // @[RegisterRouter.scala:87:24]
wire out_wimask_147 = &_out_wimask_T_147; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_147 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_147 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_155 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_155 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_163 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_163 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_171 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_171 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_179 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_179 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_187 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_187 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_195 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_195 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_203 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_203 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_211 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_211 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_219 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_219 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_227 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_227 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_235 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_235 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_243 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_243 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_251 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_251 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_259 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_259 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_267 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_267 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_275 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_275 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_283 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_283 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_291 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_291 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_299 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_299 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_307 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_307 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_315 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_315 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_323 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_323 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_331 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_331 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_339 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_339 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_347 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_347 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_355 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_355 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_363 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_363 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_371 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_371 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_379 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_379 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_387 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_387 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_395 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_395 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_403 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_403 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_411 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_411 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_419 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_419 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_427 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_427 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_435 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_435 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_443 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_443 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_451 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_451 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_459 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_459 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_467 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_467 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_475 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_475 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_483 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_483 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_491 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_491 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_501 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_501 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_509 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_509 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_517 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_517 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_525 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_525 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_533 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_533 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_541 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_541 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_549 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_549 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_557 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_557 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_565 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_565 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_573 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_573 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_581 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_581 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_590 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_590 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_598 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_598 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_606 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_606 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_614 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_614 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_622 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_622 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_630 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_630 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_634 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_634 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_642 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_642 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_650 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_650 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_658 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_658 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_666 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_666 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_674 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_674 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_684 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_684 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_692 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_692 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_700 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_700 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_708 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_708 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_716 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_716 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_724 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_724 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_732 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_732 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_740 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_740 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_748 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_748 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_756 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_756 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_764 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_764 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_772 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_772 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_780 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_780 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_788 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_788 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_796 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_796 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_804 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_804 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_812 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_812 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_820 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_820 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_828 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_828 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_836 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_836 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_846 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_846 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_854 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_854 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_862 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_862 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_870 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_870 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_878 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_878 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_886 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_886 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_894 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_894 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_902 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_902 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_910 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_910 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_918 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_918 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_926 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_926 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_934 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_934 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_942 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_942 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_950 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_950 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_958 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_958 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_966 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_966 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_974 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_974 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_982 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_982 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_990 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_990 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_998 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_998 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1006 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1006 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1014 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1014 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1022 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1022 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1030 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1030 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1038 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1038 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1046 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1046 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1054 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1054 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1062 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1062 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1070 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1070 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1078 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1078 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1086 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1086 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1094 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1094 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1102 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1102 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1110 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1110 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1118 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1118 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1126 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1126 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1134 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1134 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1142 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1142 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1150 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1150 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1158 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1158 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1166 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1166 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1174 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1174 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1182 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1182 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1190 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1190 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1198 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1198 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1206 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1206 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1214 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1214 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1222 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1222 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1230 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1230 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1238 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1238 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1246 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1246 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1254 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1254 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1262 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1262 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1270 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1270 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1278 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1278 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1286 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1286 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1294 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1294 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1302 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1302 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1310 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1310 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1318 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1318 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1326 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1326 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1334 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1334 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1342 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1342 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1350 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1350 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire out_romask_147 = |_out_romask_T_147; // @[RegisterRouter.scala:87:24]
wire out_womask_147 = &_out_womask_T_147; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_147 = out_rivalid_1_1 & out_rimask_147; // @[RegisterRouter.scala:87:24]
wire _out_T_1920 = out_f_rivalid_147; // @[RegisterRouter.scala:87:24]
wire out_f_roready_147 = out_roready_1_1 & out_romask_147; // @[RegisterRouter.scala:87:24]
wire _out_T_1921 = out_f_roready_147; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_147 = out_wivalid_1_1 & out_wimask_147; // @[RegisterRouter.scala:87:24]
wire out_f_woready_147 = out_woready_1_1 & out_womask_147; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1919 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1991 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2063 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2135 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2209 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2295 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2367 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2439 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2511 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2583 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2655 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2727 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2799 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2871 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2945 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3031 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3103 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3175 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3247 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3319 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3391 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3463 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3535 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3607 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3681 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3767 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3839 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3911 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3983 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4055 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4127 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4199 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4271 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4343 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4415 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4487 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4559 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4631 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4703 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4775 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4847 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4919 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4991 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5063 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5153 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5225 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5297 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5369 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5441 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5513 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5585 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5657 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5729 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5801 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5873 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5956 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6042 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6114 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6186 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6258 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6330 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6366 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6438 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6510 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6584 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6670 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6742 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6832 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6904 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6976 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7048 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7120 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7192 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7264 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7336 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7408 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7480 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7552 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7624 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7696 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7768 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7840 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7914 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8000 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8072 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8144 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8216 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8306 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8378 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8450 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8522 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8596 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8682 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8754 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8826 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8898 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8970 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9042 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9114 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9186 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9258 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9330 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9402 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9476 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9562 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9634 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9706 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9778 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9850 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9922 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9994 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10066 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10138 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10210 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10282 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10354 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10428 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10514 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10586 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10658 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10730 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10802 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10876 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10962 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11034 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11106 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11178 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11250 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11322 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11394 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11466 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11538 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11610 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11682 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11754 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11826 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11900 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11986 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12058 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12130 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12202 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12274 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12346 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12418 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12490 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12564 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12650 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12722 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12794 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12866 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12938 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire _out_T_1922 = ~out_rimask_147; // @[RegisterRouter.scala:87:24]
wire _out_T_1923 = ~out_wimask_147; // @[RegisterRouter.scala:87:24]
wire _out_T_1924 = ~out_romask_147; // @[RegisterRouter.scala:87:24]
wire _out_T_1925 = ~out_womask_147; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_112 = {hi_82, flags_0_go, _out_prepend_T_112}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_1926 = out_prepend_112; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_1927 = _out_T_1926; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_113 = _out_T_1927; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_148 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_148 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_156 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_156 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_164 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_164 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_172 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_172 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_180 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_180 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_188 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_188 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_196 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_196 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_204 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_204 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_212 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_212 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_220 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_220 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_228 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_228 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_236 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_236 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_244 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_244 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_252 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_252 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_260 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_260 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_268 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_268 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_276 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_276 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_284 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_284 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_292 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_292 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_300 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_300 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_308 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_308 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_316 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_316 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_324 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_324 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_332 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_332 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_340 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_340 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_348 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_348 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_356 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_356 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_364 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_364 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_372 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_372 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_380 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_380 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_388 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_388 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_396 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_396 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_404 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_404 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_412 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_412 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_420 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_420 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_428 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_428 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_436 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_436 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_444 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_444 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_452 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_452 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_460 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_460 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_468 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_468 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_476 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_476 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_484 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_484 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_492 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_492 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_502 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_502 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_510 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_510 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_518 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_518 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_526 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_526 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_534 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_534 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_542 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_542 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_550 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_550 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_558 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_558 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_566 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_566 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_574 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_574 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_582 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_582 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_591 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_591 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_599 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_599 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_607 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_607 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_615 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_615 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_623 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_623 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_631 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_631 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_635 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_635 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_643 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_643 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_651 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_651 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_659 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_659 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_667 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_667 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_675 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_675 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_685 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_685 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_693 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_693 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_701 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_701 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_709 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_709 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_717 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_717 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_725 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_725 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_733 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_733 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_741 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_741 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_749 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_749 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_757 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_757 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_765 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_765 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_773 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_773 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_781 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_781 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_789 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_789 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_797 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_797 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_805 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_805 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_813 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_813 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_821 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_821 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_829 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_829 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_837 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_837 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_847 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_847 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_855 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_855 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_863 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_863 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_871 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_871 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_879 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_879 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_887 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_887 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_895 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_895 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_903 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_903 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_911 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_911 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_919 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_919 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_927 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_927 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_935 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_935 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_943 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_943 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_951 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_951 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_959 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_959 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_967 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_967 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_975 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_975 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_983 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_983 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_991 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_991 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_999 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_999 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1007 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1007 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1015 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1015 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1023 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1023 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1031 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1031 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1039 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1039 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1047 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1047 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1055 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1055 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1063 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1063 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1071 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1071 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1079 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1079 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1087 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1087 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1095 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1095 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1103 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1103 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1111 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1111 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1119 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1119 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1127 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1127 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1135 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1135 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1143 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1143 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1151 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1151 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1159 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1159 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1167 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1167 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1175 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1175 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1183 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1183 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1191 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1191 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1199 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1199 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1207 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1207 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1215 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1215 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1223 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1223 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1231 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1231 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1239 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1239 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1247 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1247 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1255 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1255 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1263 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1263 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1271 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1271 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1279 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1279 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1287 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1287 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1295 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1295 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1303 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1303 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1311 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1311 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1319 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1319 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1327 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1327 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1335 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1335 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1343 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1343 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1351 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1351 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire out_rimask_148 = |_out_rimask_T_148; // @[RegisterRouter.scala:87:24]
wire out_wimask_148 = &_out_wimask_T_148; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_148 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_148 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_156 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_156 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_164 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_164 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_172 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_172 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_180 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_180 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_188 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_188 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_196 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_196 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_204 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_204 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_212 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_212 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_220 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_220 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_228 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_228 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_236 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_236 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_244 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_244 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_252 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_252 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_260 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_260 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_268 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_268 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_276 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_276 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_284 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_284 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_292 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_292 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_300 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_300 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_308 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_308 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_316 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_316 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_324 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_324 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_332 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_332 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_340 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_340 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_348 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_348 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_356 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_356 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_364 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_364 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_372 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_372 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_380 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_380 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_388 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_388 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_396 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_396 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_404 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_404 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_412 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_412 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_420 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_420 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_428 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_428 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_436 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_436 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_444 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_444 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_452 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_452 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_460 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_460 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_468 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_468 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_476 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_476 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_484 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_484 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_492 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_492 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_502 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_502 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_510 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_510 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_518 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_518 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_526 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_526 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_534 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_534 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_542 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_542 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_550 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_550 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_558 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_558 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_566 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_566 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_574 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_574 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_582 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_582 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_591 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_591 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_599 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_599 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_607 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_607 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_615 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_615 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_623 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_623 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_631 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_631 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_635 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_635 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_643 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_643 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_651 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_651 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_659 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_659 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_667 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_667 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_675 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_675 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_685 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_685 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_693 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_693 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_701 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_701 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_709 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_709 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_717 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_717 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_725 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_725 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_733 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_733 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_741 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_741 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_749 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_749 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_757 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_757 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_765 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_765 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_773 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_773 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_781 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_781 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_789 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_789 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_797 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_797 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_805 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_805 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_813 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_813 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_821 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_821 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_829 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_829 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_837 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_837 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_847 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_847 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_855 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_855 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_863 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_863 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_871 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_871 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_879 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_879 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_887 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_887 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_895 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_895 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_903 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_903 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_911 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_911 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_919 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_919 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_927 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_927 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_935 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_935 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_943 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_943 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_951 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_951 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_959 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_959 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_967 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_967 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_975 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_975 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_983 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_983 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_991 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_991 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_999 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_999 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1007 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1007 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1015 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1015 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1023 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1023 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1031 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1031 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1039 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1039 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1047 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1047 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1055 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1055 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1063 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1063 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1071 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1071 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1079 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1079 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1087 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1087 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1095 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1095 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1103 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1103 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1111 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1111 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1119 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1119 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1127 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1127 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1135 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1135 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1143 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1143 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1151 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1151 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1159 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1159 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1167 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1167 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1175 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1175 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1183 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1183 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1191 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1191 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1199 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1199 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1207 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1207 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1215 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1215 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1223 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1223 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1231 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1231 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1239 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1239 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1247 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1247 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1255 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1255 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1263 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1263 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1271 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1271 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1279 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1279 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1287 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1287 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1295 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1295 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1303 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1303 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1311 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1311 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1319 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1319 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1327 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1327 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1335 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1335 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1343 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1343 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1351 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1351 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire out_romask_148 = |_out_romask_T_148; // @[RegisterRouter.scala:87:24]
wire out_womask_148 = &_out_womask_T_148; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_148 = out_rivalid_1_2 & out_rimask_148; // @[RegisterRouter.scala:87:24]
wire _out_T_1929 = out_f_rivalid_148; // @[RegisterRouter.scala:87:24]
wire out_f_roready_148 = out_roready_1_2 & out_romask_148; // @[RegisterRouter.scala:87:24]
wire _out_T_1930 = out_f_roready_148; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_148 = out_wivalid_1_2 & out_wimask_148; // @[RegisterRouter.scala:87:24]
wire out_f_woready_148 = out_woready_1_2 & out_womask_148; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1928 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2000 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2072 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2144 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2220 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2304 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2376 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2448 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2520 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2592 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2664 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2736 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2808 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2880 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2956 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3040 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3112 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3184 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3256 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3328 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3400 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3472 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3544 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3616 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3692 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3776 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3848 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3920 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3992 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4064 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4136 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4208 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4280 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4352 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4424 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4496 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4568 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4640 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4712 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4784 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4856 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4928 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5000 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5072 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5162 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5234 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5306 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5378 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5450 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5522 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5594 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5666 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5738 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5810 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5882 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5967 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6051 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6123 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6195 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6267 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6339 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6375 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6447 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6519 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6595 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6679 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6751 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6841 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6913 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6985 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7057 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7129 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7201 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7273 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7345 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7417 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7489 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7561 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7633 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7705 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7777 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7849 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7925 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8009 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8081 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8153 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8225 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8315 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8387 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8459 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8531 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8607 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8691 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8763 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8835 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8907 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8979 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9051 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9123 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9195 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9267 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9339 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9411 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9487 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9571 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9643 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9715 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9787 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9859 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9931 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10003 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10075 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10147 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10219 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10291 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10363 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10439 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10523 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10595 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10667 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10739 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10811 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10887 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10971 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11043 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11115 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11187 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11259 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11331 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11403 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11475 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11547 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11619 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11691 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11763 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11835 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11911 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11995 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12067 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12139 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12211 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12283 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12355 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12427 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12499 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12575 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12659 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12731 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12803 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12875 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12947 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire _out_T_1931 = ~out_rimask_148; // @[RegisterRouter.scala:87:24]
wire _out_T_1932 = ~out_wimask_148; // @[RegisterRouter.scala:87:24]
wire _out_T_1933 = ~out_romask_148; // @[RegisterRouter.scala:87:24]
wire _out_T_1934 = ~out_womask_148; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_113 = {hi_83, flags_0_go, _out_prepend_T_113}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_1935 = out_prepend_113; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_1936 = _out_T_1935; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_114 = _out_T_1936; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_149 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_149 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_157 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_157 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_165 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_165 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_173 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_173 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_181 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_181 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_189 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_189 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_197 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_197 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_205 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_205 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_213 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_213 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_221 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_221 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_229 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_229 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_237 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_237 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_245 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_245 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_253 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_253 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_261 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_261 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_269 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_269 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_277 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_277 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_285 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_285 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_293 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_293 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_301 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_301 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_309 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_309 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_317 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_317 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_325 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_325 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_333 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_333 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_341 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_341 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_349 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_349 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_357 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_357 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_365 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_365 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_373 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_373 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_381 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_381 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_389 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_389 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_397 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_397 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_405 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_405 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_413 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_413 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_421 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_421 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_429 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_429 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_437 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_437 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_445 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_445 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_453 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_453 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_461 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_461 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_469 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_469 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_477 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_477 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_485 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_485 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_493 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_493 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_503 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_503 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_511 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_511 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_519 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_519 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_527 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_527 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_535 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_535 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_543 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_543 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_551 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_551 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_559 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_559 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_567 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_567 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_575 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_575 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_583 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_583 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_592 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_592 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_600 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_600 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_608 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_608 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_616 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_616 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_624 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_624 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_632 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_632 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_636 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_636 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_644 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_644 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_652 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_652 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_660 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_660 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_668 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_668 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_676 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_676 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_686 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_686 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_694 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_694 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_702 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_702 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_710 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_710 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_718 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_718 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_726 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_726 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_734 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_734 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_742 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_742 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_750 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_750 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_758 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_758 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_766 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_766 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_774 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_774 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_782 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_782 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_790 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_790 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_798 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_798 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_806 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_806 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_814 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_814 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_822 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_822 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_830 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_830 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_838 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_838 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_848 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_848 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_856 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_856 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_864 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_864 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_872 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_872 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_880 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_880 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_888 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_888 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_896 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_896 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_904 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_904 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_912 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_912 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_920 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_920 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_928 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_928 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_936 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_936 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_944 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_944 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_952 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_952 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_960 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_960 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_968 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_968 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_976 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_976 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_984 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_984 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_992 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_992 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1000 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1000 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1008 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1008 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1016 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1016 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1024 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1024 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1032 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1032 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1040 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1040 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1048 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1048 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1056 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1056 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1064 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1064 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1072 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1072 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1080 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1080 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1088 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1088 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1096 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1096 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1104 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1104 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1112 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1112 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1120 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1120 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1128 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1128 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1136 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1136 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1144 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1144 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1152 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1152 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1160 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1160 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1168 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1168 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1176 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1176 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1184 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1184 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1192 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1192 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1200 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1200 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1208 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1208 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1216 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1216 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1224 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1224 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1232 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1232 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1240 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1240 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1248 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1248 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1256 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1256 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1264 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1264 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1272 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1272 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1280 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1280 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1288 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1288 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1296 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1296 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1304 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1304 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1312 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1312 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1320 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1320 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1328 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1328 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1336 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1336 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1344 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1344 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1352 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1352 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire out_rimask_149 = |_out_rimask_T_149; // @[RegisterRouter.scala:87:24]
wire out_wimask_149 = &_out_wimask_T_149; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_149 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_149 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_157 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_157 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_165 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_165 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_173 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_173 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_181 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_181 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_189 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_189 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_197 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_197 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_205 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_205 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_213 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_213 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_221 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_221 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_229 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_229 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_237 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_237 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_245 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_245 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_253 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_253 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_261 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_261 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_269 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_269 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_277 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_277 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_285 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_285 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_293 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_293 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_301 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_301 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_309 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_309 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_317 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_317 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_325 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_325 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_333 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_333 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_341 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_341 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_349 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_349 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_357 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_357 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_365 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_365 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_373 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_373 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_381 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_381 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_389 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_389 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_397 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_397 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_405 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_405 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_413 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_413 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_421 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_421 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_429 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_429 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_437 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_437 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_445 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_445 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_453 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_453 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_461 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_461 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_469 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_469 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_477 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_477 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_485 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_485 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_493 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_493 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_503 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_503 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_511 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_511 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_519 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_519 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_527 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_527 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_535 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_535 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_543 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_543 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_551 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_551 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_559 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_559 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_567 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_567 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_575 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_575 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_583 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_583 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_592 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_592 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_600 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_600 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_608 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_608 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_616 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_616 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_624 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_624 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_632 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_632 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_636 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_636 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_644 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_644 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_652 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_652 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_660 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_660 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_668 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_668 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_676 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_676 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_686 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_686 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_694 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_694 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_702 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_702 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_710 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_710 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_718 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_718 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_726 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_726 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_734 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_734 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_742 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_742 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_750 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_750 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_758 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_758 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_766 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_766 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_774 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_774 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_782 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_782 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_790 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_790 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_798 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_798 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_806 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_806 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_814 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_814 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_822 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_822 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_830 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_830 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_838 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_838 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_848 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_848 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_856 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_856 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_864 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_864 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_872 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_872 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_880 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_880 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_888 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_888 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_896 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_896 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_904 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_904 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_912 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_912 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_920 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_920 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_928 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_928 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_936 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_936 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_944 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_944 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_952 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_952 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_960 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_960 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_968 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_968 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_976 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_976 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_984 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_984 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_992 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_992 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1000 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1000 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1008 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1008 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1016 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1016 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1024 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1024 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1032 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1032 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1040 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1040 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1048 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1048 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1056 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1056 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1064 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1064 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1072 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1072 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1080 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1080 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1088 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1088 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1096 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1096 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1104 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1104 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1112 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1112 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1120 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1120 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1128 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1128 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1136 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1136 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1144 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1144 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1152 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1152 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1160 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1160 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1168 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1168 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1176 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1176 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1184 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1184 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1192 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1192 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1200 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1200 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1208 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1208 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1216 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1216 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1224 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1224 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1232 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1232 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1240 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1240 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1248 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1248 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1256 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1256 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1264 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1264 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1272 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1272 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1280 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1280 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1288 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1288 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1296 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1296 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1304 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1304 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1312 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1312 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1320 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1320 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1328 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1328 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1336 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1336 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1344 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1344 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1352 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1352 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire out_romask_149 = |_out_romask_T_149; // @[RegisterRouter.scala:87:24]
wire out_womask_149 = &_out_womask_T_149; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_149 = out_rivalid_1_3 & out_rimask_149; // @[RegisterRouter.scala:87:24]
wire _out_T_1938 = out_f_rivalid_149; // @[RegisterRouter.scala:87:24]
wire out_f_roready_149 = out_roready_1_3 & out_romask_149; // @[RegisterRouter.scala:87:24]
wire _out_T_1939 = out_f_roready_149; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_149 = out_wivalid_1_3 & out_wimask_149; // @[RegisterRouter.scala:87:24]
wire out_f_woready_149 = out_woready_1_3 & out_womask_149; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1937 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2009 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2081 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2153 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2231 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2313 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2385 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2457 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2529 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2601 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2673 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2745 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2817 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2889 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2967 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3049 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3121 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3193 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3265 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3337 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3409 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3481 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3553 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3625 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3703 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3785 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3857 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3929 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4001 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4073 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4145 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4217 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4289 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4361 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4433 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4505 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4577 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4649 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4721 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4793 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4865 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4937 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5009 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5081 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5171 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5243 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5315 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5387 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5459 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5531 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5603 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5675 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5747 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5819 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5891 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5978 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6060 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6132 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6204 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6276 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6348 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6384 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6456 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6528 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6606 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6688 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6760 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6850 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6922 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6994 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7066 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7138 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7210 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7282 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7354 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7426 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7498 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7570 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7642 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7714 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7786 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7858 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7936 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8018 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8090 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8162 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8234 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8324 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8396 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8468 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8540 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8618 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8700 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8772 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8844 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8916 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8988 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9060 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9132 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9204 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9276 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9348 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9420 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9498 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9580 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9652 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9724 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9796 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9868 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9940 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10012 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10084 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10156 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10228 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10300 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10372 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10450 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10532 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10604 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10676 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10748 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10820 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10898 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10980 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11052 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11124 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11196 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11268 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11340 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11412 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11484 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11556 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11628 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11700 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11772 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11844 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11922 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12004 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12076 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12148 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12220 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12292 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12364 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12436 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12508 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12586 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12668 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12740 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12812 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12884 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12956 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire _out_T_1940 = ~out_rimask_149; // @[RegisterRouter.scala:87:24]
wire _out_T_1941 = ~out_wimask_149; // @[RegisterRouter.scala:87:24]
wire _out_T_1942 = ~out_romask_149; // @[RegisterRouter.scala:87:24]
wire _out_T_1943 = ~out_womask_149; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_114 = {hi_84, flags_0_go, _out_prepend_T_114}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_1944 = out_prepend_114; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_1945 = _out_T_1944; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_115 = _out_T_1945; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_150 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_150 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_158 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_158 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_166 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_166 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_174 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_174 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_182 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_182 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_190 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_190 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_198 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_198 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_206 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_206 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_214 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_214 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_222 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_222 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_230 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_230 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_238 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_238 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_246 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_246 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_254 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_254 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_262 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_262 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_270 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_270 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_278 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_278 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_286 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_286 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_294 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_294 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_302 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_302 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_310 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_310 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_318 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_318 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_326 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_326 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_334 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_334 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_342 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_342 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_350 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_350 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_358 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_358 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_366 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_366 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_374 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_374 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_382 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_382 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_390 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_390 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_398 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_398 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_406 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_406 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_414 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_414 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_422 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_422 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_430 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_430 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_438 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_438 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_446 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_446 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_454 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_454 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_462 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_462 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_470 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_470 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_478 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_478 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_486 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_486 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_494 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_494 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_504 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_504 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_512 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_512 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_520 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_520 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_528 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_528 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_536 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_536 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_544 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_544 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_552 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_552 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_560 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_560 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_568 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_568 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_576 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_576 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_584 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_584 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_593 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_593 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_601 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_601 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_609 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_609 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_617 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_617 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_625 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_625 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_637 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_637 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_645 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_645 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_653 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_653 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_661 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_661 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_669 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_669 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_677 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_677 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_687 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_687 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_695 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_695 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_703 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_703 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_711 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_711 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_719 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_719 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_727 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_727 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_735 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_735 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_743 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_743 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_751 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_751 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_759 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_759 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_767 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_767 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_775 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_775 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_783 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_783 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_791 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_791 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_799 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_799 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_807 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_807 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_815 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_815 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_823 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_823 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_831 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_831 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_839 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_839 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_849 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_849 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_857 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_857 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_865 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_865 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_873 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_873 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_881 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_881 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_889 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_889 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_897 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_897 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_905 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_905 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_913 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_913 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_921 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_921 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_929 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_929 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_937 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_937 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_945 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_945 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_953 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_953 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_961 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_961 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_969 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_969 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_977 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_977 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_985 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_985 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_993 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_993 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1001 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1001 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1009 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1009 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1017 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1017 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1025 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1025 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1033 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1033 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1041 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1041 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1049 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1049 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1057 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1057 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1065 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1065 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1073 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1073 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1081 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1081 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1089 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1089 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1097 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1097 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1105 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1105 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1113 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1113 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1121 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1121 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1129 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1129 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1137 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1137 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1145 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1145 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1153 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1153 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1161 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1161 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1169 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1169 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1177 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1177 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1185 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1185 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1193 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1193 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1201 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1201 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1209 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1209 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1217 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1217 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1225 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1225 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1233 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1233 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1241 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1241 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1249 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1249 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1257 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1257 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1265 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1265 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1273 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1273 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1281 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1281 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1289 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1289 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1297 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1297 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1305 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1305 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1313 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1313 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1321 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1321 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1329 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1329 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1337 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1337 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1345 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1345 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1353 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1353 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire out_rimask_150 = |_out_rimask_T_150; // @[RegisterRouter.scala:87:24]
wire out_wimask_150 = &_out_wimask_T_150; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_150 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_150 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_158 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_158 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_166 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_166 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_174 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_174 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_182 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_182 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_190 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_190 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_198 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_198 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_206 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_206 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_214 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_214 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_222 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_222 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_230 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_230 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_238 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_238 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_246 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_246 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_254 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_254 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_262 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_262 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_270 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_270 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_278 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_278 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_286 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_286 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_294 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_294 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_302 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_302 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_310 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_310 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_318 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_318 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_326 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_326 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_334 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_334 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_342 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_342 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_350 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_350 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_358 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_358 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_366 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_366 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_374 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_374 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_382 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_382 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_390 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_390 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_398 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_398 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_406 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_406 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_414 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_414 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_422 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_422 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_430 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_430 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_438 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_438 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_446 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_446 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_454 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_454 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_462 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_462 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_470 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_470 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_478 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_478 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_486 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_486 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_494 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_494 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_504 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_504 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_512 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_512 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_520 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_520 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_528 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_528 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_536 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_536 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_544 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_544 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_552 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_552 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_560 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_560 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_568 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_568 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_576 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_576 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_584 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_584 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_593 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_593 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_601 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_601 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_609 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_609 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_617 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_617 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_625 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_625 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_637 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_637 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_645 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_645 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_653 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_653 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_661 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_661 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_669 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_669 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_677 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_677 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_687 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_687 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_695 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_695 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_703 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_703 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_711 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_711 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_719 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_719 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_727 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_727 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_735 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_735 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_743 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_743 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_751 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_751 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_759 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_759 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_767 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_767 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_775 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_775 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_783 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_783 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_791 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_791 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_799 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_799 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_807 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_807 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_815 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_815 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_823 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_823 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_831 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_831 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_839 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_839 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_849 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_849 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_857 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_857 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_865 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_865 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_873 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_873 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_881 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_881 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_889 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_889 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_897 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_897 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_905 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_905 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_913 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_913 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_921 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_921 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_929 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_929 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_937 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_937 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_945 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_945 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_953 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_953 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_961 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_961 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_969 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_969 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_977 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_977 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_985 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_985 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_993 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_993 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1001 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1001 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1009 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1009 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1017 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1017 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1025 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1025 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1033 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1033 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1041 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1041 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1049 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1049 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1057 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1057 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1065 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1065 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1073 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1073 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1081 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1081 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1089 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1089 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1097 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1097 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1105 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1105 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1113 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1113 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1121 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1121 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1129 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1129 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1137 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1137 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1145 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1145 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1153 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1153 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1161 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1161 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1169 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1169 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1177 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1177 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1185 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1185 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1193 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1193 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1201 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1201 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1209 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1209 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1217 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1217 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1225 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1225 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1233 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1233 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1241 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1241 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1249 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1249 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1257 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1257 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1265 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1265 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1273 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1273 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1281 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1281 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1289 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1289 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1297 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1297 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1305 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1305 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1313 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1313 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1321 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1321 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1329 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1329 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1337 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1337 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1345 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1345 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1353 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1353 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire out_romask_150 = |_out_romask_T_150; // @[RegisterRouter.scala:87:24]
wire out_womask_150 = &_out_womask_T_150; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_150 = out_rivalid_1_4 & out_rimask_150; // @[RegisterRouter.scala:87:24]
wire _out_T_1947 = out_f_rivalid_150; // @[RegisterRouter.scala:87:24]
wire out_f_roready_150 = out_roready_1_4 & out_romask_150; // @[RegisterRouter.scala:87:24]
wire _out_T_1948 = out_f_roready_150; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_150 = out_wivalid_1_4 & out_wimask_150; // @[RegisterRouter.scala:87:24]
wire out_f_woready_150 = out_woready_1_4 & out_womask_150; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1946 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2018 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2090 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2162 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2242 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2322 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2394 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2466 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2538 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2610 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2682 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2754 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2826 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2898 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2978 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3058 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3130 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3202 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3274 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3346 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3418 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3490 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3562 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3634 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3714 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3794 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3866 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3938 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4010 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4082 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4154 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4226 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4298 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4370 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4442 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4514 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4586 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4658 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4730 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4802 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4874 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4946 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5018 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5090 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5180 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5252 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5324 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5396 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5468 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5540 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5612 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5684 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5756 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5828 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5900 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5989 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6069 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6141 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6213 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6285 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6393 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6465 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6537 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6617 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6697 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6769 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6859 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6931 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7003 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7075 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7147 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7219 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7291 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7363 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7435 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7507 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7579 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7651 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7723 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7795 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7867 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7947 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8027 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8099 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8171 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8243 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8333 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8405 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8477 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8549 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8629 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8709 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8781 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8853 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8925 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8997 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9069 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9141 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9213 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9285 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9357 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9429 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9509 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9589 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9661 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9733 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9805 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9877 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9949 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10021 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10093 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10165 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10237 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10309 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10381 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10461 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10541 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10613 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10685 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10757 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10829 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10909 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10989 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11061 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11133 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11205 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11277 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11349 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11421 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11493 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11565 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11637 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11709 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11781 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11853 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11933 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12013 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12085 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12157 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12229 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12301 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12373 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12445 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12517 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12597 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12677 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12749 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12821 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12893 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12965 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire _out_T_1949 = ~out_rimask_150; // @[RegisterRouter.scala:87:24]
wire _out_T_1950 = ~out_wimask_150; // @[RegisterRouter.scala:87:24]
wire _out_T_1951 = ~out_romask_150; // @[RegisterRouter.scala:87:24]
wire _out_T_1952 = ~out_womask_150; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_115 = {hi_85, flags_0_go, _out_prepend_T_115}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_1953 = out_prepend_115; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_1954 = _out_T_1953; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_116 = _out_T_1954; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_151 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_151 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_159 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_159 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_167 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_167 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_175 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_175 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_183 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_183 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_191 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_191 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_199 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_199 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_207 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_207 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_215 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_215 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_223 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_223 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_231 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_231 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_239 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_239 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_247 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_247 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_255 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_255 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_263 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_263 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_271 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_271 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_279 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_279 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_287 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_287 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_295 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_295 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_303 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_303 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_311 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_311 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_319 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_319 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_327 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_327 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_335 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_335 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_343 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_343 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_351 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_351 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_359 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_359 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_367 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_367 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_375 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_375 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_383 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_383 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_391 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_391 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_399 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_399 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_407 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_407 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_415 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_415 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_423 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_423 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_431 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_431 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_439 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_439 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_447 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_447 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_455 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_455 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_463 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_463 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_471 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_471 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_479 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_479 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_487 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_487 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_495 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_495 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_505 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_505 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_513 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_513 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_521 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_521 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_529 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_529 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_537 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_537 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_545 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_545 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_553 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_553 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_561 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_561 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_569 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_569 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_577 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_577 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_585 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_585 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_594 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_594 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_602 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_602 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_610 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_610 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_618 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_618 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_626 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_626 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_638 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_638 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_646 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_646 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_654 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_654 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_662 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_662 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_670 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_670 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_678 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_678 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_688 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_688 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_696 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_696 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_704 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_704 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_712 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_712 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_720 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_720 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_728 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_728 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_736 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_736 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_744 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_744 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_752 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_752 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_760 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_760 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_768 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_768 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_776 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_776 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_784 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_784 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_792 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_792 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_800 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_800 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_808 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_808 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_816 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_816 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_824 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_824 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_832 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_832 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_840 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_840 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_850 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_850 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_858 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_858 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_866 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_866 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_874 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_874 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_882 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_882 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_890 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_890 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_898 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_898 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_906 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_906 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_914 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_914 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_922 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_922 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_930 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_930 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_938 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_938 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_946 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_946 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_954 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_954 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_962 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_962 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_970 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_970 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_978 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_978 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_986 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_986 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_994 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_994 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1002 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1002 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1010 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1010 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1018 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1018 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1026 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1026 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1034 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1034 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1042 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1042 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1050 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1050 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1058 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1058 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1066 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1066 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1074 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1074 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1082 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1082 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1090 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1090 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1098 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1098 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1106 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1106 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1114 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1114 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1122 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1122 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1130 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1130 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1138 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1138 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1146 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1146 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1154 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1154 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1162 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1162 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1170 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1170 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1178 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1178 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1186 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1186 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1194 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1194 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1202 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1202 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1210 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1210 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1218 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1218 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1226 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1226 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1234 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1234 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1242 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1242 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1250 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1250 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1258 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1258 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1266 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1266 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1274 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1274 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1282 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1282 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1290 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1290 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1298 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1298 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1306 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1306 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1314 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1314 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1322 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1322 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1330 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1330 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1338 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1338 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1346 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1346 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1354 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1354 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire out_rimask_151 = |_out_rimask_T_151; // @[RegisterRouter.scala:87:24]
wire out_wimask_151 = &_out_wimask_T_151; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_151 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_151 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_159 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_159 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_167 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_167 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_175 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_175 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_183 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_183 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_191 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_191 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_199 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_199 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_207 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_207 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_215 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_215 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_223 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_223 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_231 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_231 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_239 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_239 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_247 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_247 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_255 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_255 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_263 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_263 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_271 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_271 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_279 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_279 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_287 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_287 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_295 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_295 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_303 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_303 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_311 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_311 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_319 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_319 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_327 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_327 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_335 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_335 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_343 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_343 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_351 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_351 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_359 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_359 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_367 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_367 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_375 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_375 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_383 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_383 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_391 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_391 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_399 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_399 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_407 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_407 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_415 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_415 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_423 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_423 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_431 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_431 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_439 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_439 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_447 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_447 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_455 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_455 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_463 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_463 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_471 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_471 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_479 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_479 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_487 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_487 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_495 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_495 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_505 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_505 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_513 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_513 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_521 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_521 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_529 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_529 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_537 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_537 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_545 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_545 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_553 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_553 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_561 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_561 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_569 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_569 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_577 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_577 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_585 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_585 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_594 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_594 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_602 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_602 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_610 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_610 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_618 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_618 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_626 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_626 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_638 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_638 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_646 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_646 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_654 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_654 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_662 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_662 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_670 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_670 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_678 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_678 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_688 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_688 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_696 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_696 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_704 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_704 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_712 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_712 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_720 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_720 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_728 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_728 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_736 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_736 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_744 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_744 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_752 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_752 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_760 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_760 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_768 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_768 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_776 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_776 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_784 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_784 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_792 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_792 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_800 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_800 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_808 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_808 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_816 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_816 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_824 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_824 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_832 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_832 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_840 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_840 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_850 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_850 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_858 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_858 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_866 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_866 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_874 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_874 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_882 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_882 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_890 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_890 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_898 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_898 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_906 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_906 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_914 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_914 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_922 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_922 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_930 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_930 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_938 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_938 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_946 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_946 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_954 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_954 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_962 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_962 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_970 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_970 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_978 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_978 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_986 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_986 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_994 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_994 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1002 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1002 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1010 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1010 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1018 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1018 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1026 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1026 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1034 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1034 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1042 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1042 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1050 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1050 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1058 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1058 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1066 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1066 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1074 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1074 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1082 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1082 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1090 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1090 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1098 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1098 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1106 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1106 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1114 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1114 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1122 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1122 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1130 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1130 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1138 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1138 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1146 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1146 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1154 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1154 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1162 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1162 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1170 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1170 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1178 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1178 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1186 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1186 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1194 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1194 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1202 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1202 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1210 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1210 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1218 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1218 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1226 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1226 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1234 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1234 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1242 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1242 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1250 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1250 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1258 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1258 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1266 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1266 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1274 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1274 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1282 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1282 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1290 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1290 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1298 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1298 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1306 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1306 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1314 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1314 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1322 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1322 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1330 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1330 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1338 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1338 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1346 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1346 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1354 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1354 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire out_romask_151 = |_out_romask_T_151; // @[RegisterRouter.scala:87:24]
wire out_womask_151 = &_out_womask_T_151; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_151 = out_rivalid_1_5 & out_rimask_151; // @[RegisterRouter.scala:87:24]
wire _out_T_1956 = out_f_rivalid_151; // @[RegisterRouter.scala:87:24]
wire out_f_roready_151 = out_roready_1_5 & out_romask_151; // @[RegisterRouter.scala:87:24]
wire _out_T_1957 = out_f_roready_151; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_151 = out_wivalid_1_5 & out_wimask_151; // @[RegisterRouter.scala:87:24]
wire out_f_woready_151 = out_woready_1_5 & out_womask_151; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1955 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2027 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2099 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2171 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2253 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2331 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2403 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2475 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2547 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2619 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2691 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2763 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2835 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2907 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2989 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3067 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3139 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3211 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3283 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3355 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3427 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3499 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3571 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3643 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3725 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3803 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3875 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3947 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4019 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4091 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4163 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4235 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4307 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4379 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4451 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4523 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4595 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4667 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4739 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4811 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4883 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4955 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5027 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5099 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5189 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5261 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5333 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5405 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5477 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5549 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5621 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5693 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5765 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5837 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5909 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6000 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6078 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6150 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6222 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6294 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6402 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6474 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6546 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6628 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6706 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6778 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6868 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6940 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7012 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7084 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7156 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7228 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7300 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7372 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7444 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7516 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7588 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7660 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7732 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7804 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7876 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7958 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8036 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8108 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8180 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8252 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8342 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8414 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8486 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8558 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8640 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8718 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8790 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8862 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8934 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9006 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9078 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9150 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9222 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9294 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9366 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9438 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9520 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9598 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9670 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9742 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9814 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9886 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9958 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10030 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10102 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10174 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10246 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10318 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10390 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10472 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10550 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10622 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10694 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10766 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10838 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10920 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10998 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11070 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11142 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11214 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11286 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11358 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11430 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11502 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11574 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11646 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11718 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11790 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11862 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11944 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12022 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12094 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12166 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12238 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12310 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12382 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12454 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12526 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12608 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12686 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12758 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12830 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12902 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12974 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire _out_T_1958 = ~out_rimask_151; // @[RegisterRouter.scala:87:24]
wire _out_T_1959 = ~out_wimask_151; // @[RegisterRouter.scala:87:24]
wire _out_T_1960 = ~out_romask_151; // @[RegisterRouter.scala:87:24]
wire _out_T_1961 = ~out_womask_151; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_116 = {hi_86, flags_0_go, _out_prepend_T_116}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_1962 = out_prepend_116; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_1963 = _out_T_1962; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_117 = _out_T_1963; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_152 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_152 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_160 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_160 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_168 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_168 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_176 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_176 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_184 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_184 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_192 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_192 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_200 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_200 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_208 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_208 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_216 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_216 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_224 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_224 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_232 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_232 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_240 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_240 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_248 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_248 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_256 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_256 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_264 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_264 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_272 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_272 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_280 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_280 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_288 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_288 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_296 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_296 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_304 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_304 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_312 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_312 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_320 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_320 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_328 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_328 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_336 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_336 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_344 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_344 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_352 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_352 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_360 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_360 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_368 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_368 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_376 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_376 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_384 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_384 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_392 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_392 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_400 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_400 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_408 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_408 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_416 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_416 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_424 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_424 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_432 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_432 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_440 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_440 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_448 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_448 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_456 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_456 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_464 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_464 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_472 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_472 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_480 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_480 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_488 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_488 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_496 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_496 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_506 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_506 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_514 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_514 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_522 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_522 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_530 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_530 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_538 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_538 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_546 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_546 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_554 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_554 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_562 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_562 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_570 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_570 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_578 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_578 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_586 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_586 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_595 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_595 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_603 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_603 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_611 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_611 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_619 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_619 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_627 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_627 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_639 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_639 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_647 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_647 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_655 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_655 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_663 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_663 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_671 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_671 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_679 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_679 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_689 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_689 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_697 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_697 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_705 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_705 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_713 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_713 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_721 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_721 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_729 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_729 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_737 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_737 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_745 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_745 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_753 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_753 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_761 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_761 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_769 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_769 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_777 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_777 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_785 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_785 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_793 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_793 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_801 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_801 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_809 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_809 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_817 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_817 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_825 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_825 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_833 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_833 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_841 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_841 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_851 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_851 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_859 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_859 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_867 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_867 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_875 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_875 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_883 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_883 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_891 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_891 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_899 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_899 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_907 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_907 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_915 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_915 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_923 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_923 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_931 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_931 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_939 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_939 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_947 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_947 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_955 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_955 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_963 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_963 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_971 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_971 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_979 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_979 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_987 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_987 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_995 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_995 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1003 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1003 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1011 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1011 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1019 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1019 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1027 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1027 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1035 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1035 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1043 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1043 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1051 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1051 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1059 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1059 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1067 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1067 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1075 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1075 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1083 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1083 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1091 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1091 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1099 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1099 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1107 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1107 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1115 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1115 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1123 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1123 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1131 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1131 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1139 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1139 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1147 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1147 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1155 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1155 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1163 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1163 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1171 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1171 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1179 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1179 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1187 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1187 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1195 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1195 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1203 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1203 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1211 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1211 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1219 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1219 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1227 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1227 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1235 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1235 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1243 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1243 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1251 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1251 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1259 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1259 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1267 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1267 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1275 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1275 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1283 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1283 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1291 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1291 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1299 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1299 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1307 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1307 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1315 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1315 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1323 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1323 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1331 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1331 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1339 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1339 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1347 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1347 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1355 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1355 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire out_rimask_152 = |_out_rimask_T_152; // @[RegisterRouter.scala:87:24]
wire out_wimask_152 = &_out_wimask_T_152; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_152 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_152 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_160 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_160 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_168 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_168 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_176 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_176 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_184 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_184 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_192 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_192 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_200 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_200 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_208 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_208 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_216 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_216 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_224 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_224 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_232 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_232 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_240 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_240 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_248 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_248 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_256 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_256 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_264 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_264 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_272 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_272 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_280 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_280 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_288 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_288 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_296 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_296 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_304 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_304 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_312 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_312 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_320 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_320 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_328 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_328 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_336 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_336 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_344 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_344 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_352 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_352 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_360 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_360 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_368 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_368 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_376 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_376 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_384 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_384 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_392 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_392 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_400 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_400 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_408 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_408 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_416 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_416 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_424 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_424 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_432 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_432 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_440 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_440 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_448 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_448 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_456 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_456 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_464 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_464 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_472 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_472 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_480 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_480 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_488 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_488 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_496 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_496 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_506 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_506 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_514 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_514 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_522 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_522 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_530 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_530 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_538 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_538 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_546 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_546 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_554 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_554 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_562 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_562 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_570 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_570 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_578 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_578 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_586 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_586 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_595 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_595 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_603 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_603 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_611 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_611 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_619 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_619 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_627 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_627 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_639 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_639 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_647 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_647 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_655 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_655 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_663 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_663 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_671 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_671 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_679 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_679 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_689 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_689 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_697 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_697 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_705 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_705 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_713 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_713 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_721 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_721 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_729 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_729 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_737 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_737 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_745 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_745 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_753 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_753 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_761 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_761 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_769 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_769 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_777 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_777 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_785 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_785 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_793 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_793 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_801 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_801 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_809 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_809 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_817 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_817 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_825 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_825 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_833 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_833 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_841 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_841 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_851 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_851 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_859 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_859 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_867 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_867 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_875 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_875 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_883 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_883 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_891 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_891 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_899 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_899 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_907 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_907 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_915 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_915 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_923 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_923 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_931 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_931 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_939 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_939 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_947 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_947 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_955 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_955 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_963 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_963 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_971 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_971 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_979 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_979 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_987 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_987 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_995 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_995 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1003 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1003 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1011 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1011 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1019 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1019 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1027 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1027 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1035 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1035 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1043 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1043 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1051 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1051 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1059 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1059 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1067 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1067 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1075 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1075 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1083 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1083 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1091 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1091 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1099 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1099 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1107 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1107 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1115 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1115 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1123 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1123 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1131 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1131 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1139 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1139 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1147 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1147 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1155 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1155 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1163 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1163 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1171 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1171 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1179 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1179 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1187 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1187 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1195 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1195 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1203 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1203 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1211 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1211 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1219 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1219 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1227 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1227 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1235 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1235 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1243 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1243 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1251 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1251 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1259 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1259 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1267 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1267 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1275 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1275 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1283 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1283 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1291 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1291 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1299 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1299 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1307 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1307 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1315 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1315 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1323 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1323 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1331 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1331 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1339 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1339 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1347 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1347 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1355 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1355 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire out_romask_152 = |_out_romask_T_152; // @[RegisterRouter.scala:87:24]
wire out_womask_152 = &_out_womask_T_152; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_152 = out_rivalid_1_6 & out_rimask_152; // @[RegisterRouter.scala:87:24]
wire _out_T_1965 = out_f_rivalid_152; // @[RegisterRouter.scala:87:24]
wire out_f_roready_152 = out_roready_1_6 & out_romask_152; // @[RegisterRouter.scala:87:24]
wire _out_T_1966 = out_f_roready_152; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_152 = out_wivalid_1_6 & out_wimask_152; // @[RegisterRouter.scala:87:24]
wire out_f_woready_152 = out_woready_1_6 & out_womask_152; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1964 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2036 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2108 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2180 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2264 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2340 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2412 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2484 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2556 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2628 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2700 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2772 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2844 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2916 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3000 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3076 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3148 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3220 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3292 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3364 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3436 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3508 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3580 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3652 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3736 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3812 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3884 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3956 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4028 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4100 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4172 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4244 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4316 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4388 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4460 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4532 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4604 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4676 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4748 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4820 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4892 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4964 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5036 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5108 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5198 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5270 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5342 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5414 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5486 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5558 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5630 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5702 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5774 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5846 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5918 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6011 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6087 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6159 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6231 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6303 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6411 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6483 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6555 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6639 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6715 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6787 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6877 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6949 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7021 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7093 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7165 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7237 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7309 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7381 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7453 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7525 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7597 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7669 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7741 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7813 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7885 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7969 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8045 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8117 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8189 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8261 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8351 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8423 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8495 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8567 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8651 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8727 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8799 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8871 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8943 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9015 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9087 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9159 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9231 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9303 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9375 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9447 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9531 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9607 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9679 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9751 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9823 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9895 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9967 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10039 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10111 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10183 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10255 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10327 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10399 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10483 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10559 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10631 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10703 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10775 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10847 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10931 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11007 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11079 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11151 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11223 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11295 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11367 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11439 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11511 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11583 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11655 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11727 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11799 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11871 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11955 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12031 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12103 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12175 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12247 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12319 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12391 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12463 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12535 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12619 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12695 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12767 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12839 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12911 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12983 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire _out_T_1967 = ~out_rimask_152; // @[RegisterRouter.scala:87:24]
wire _out_T_1968 = ~out_wimask_152; // @[RegisterRouter.scala:87:24]
wire _out_T_1969 = ~out_romask_152; // @[RegisterRouter.scala:87:24]
wire _out_T_1970 = ~out_womask_152; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_117 = {hi_87, flags_0_go, _out_prepend_T_117}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_1971 = out_prepend_117; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_1972 = _out_T_1971; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_118 = _out_T_1972; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_153 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_153 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_161 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_161 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_169 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_169 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_177 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_177 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_185 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_185 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_193 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_193 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_201 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_201 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_209 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_209 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_217 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_217 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_225 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_225 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_233 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_233 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_241 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_241 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_249 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_249 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_257 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_257 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_265 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_265 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_273 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_273 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_281 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_281 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_289 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_289 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_297 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_297 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_305 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_305 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_313 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_313 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_321 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_321 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_329 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_329 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_337 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_337 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_345 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_345 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_353 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_353 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_361 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_361 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_369 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_369 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_377 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_377 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_385 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_385 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_393 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_393 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_401 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_401 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_409 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_409 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_417 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_417 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_425 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_425 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_433 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_433 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_441 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_441 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_449 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_449 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_457 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_457 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_465 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_465 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_473 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_473 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_481 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_481 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_489 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_489 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_497 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_497 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_507 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_507 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_515 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_515 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_523 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_523 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_531 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_531 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_539 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_539 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_547 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_547 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_555 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_555 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_563 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_563 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_571 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_571 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_579 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_579 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_587 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_587 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_596 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_596 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_604 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_604 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_612 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_612 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_620 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_620 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_628 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_628 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_640 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_640 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_648 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_648 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_656 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_656 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_664 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_664 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_672 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_672 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_680 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_680 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_690 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_690 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_698 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_698 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_706 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_706 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_714 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_714 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_722 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_722 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_730 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_730 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_738 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_738 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_746 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_746 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_754 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_754 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_762 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_762 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_770 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_770 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_778 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_778 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_786 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_786 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_794 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_794 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_802 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_802 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_810 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_810 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_818 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_818 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_826 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_826 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_834 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_834 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_842 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_842 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_852 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_852 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_860 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_860 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_868 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_868 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_876 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_876 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_884 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_884 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_892 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_892 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_900 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_900 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_908 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_908 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_916 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_916 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_924 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_924 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_932 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_932 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_940 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_940 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_948 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_948 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_956 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_956 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_964 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_964 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_972 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_972 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_980 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_980 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_988 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_988 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_996 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_996 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1004 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1004 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1012 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1012 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1020 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1020 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1028 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1028 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1036 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1036 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1044 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1044 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1052 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1052 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1060 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1060 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1068 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1068 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1076 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1076 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1084 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1084 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1092 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1092 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1100 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1100 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1108 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1108 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1116 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1116 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1124 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1124 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1132 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1132 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1140 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1140 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1148 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1148 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1156 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1156 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1164 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1164 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1172 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1172 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1180 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1180 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1188 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1188 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1196 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1196 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1204 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1204 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1212 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1212 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1220 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1220 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1228 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1228 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1236 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1236 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1244 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1244 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1252 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1252 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1260 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1260 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1268 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1268 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1276 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1276 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1284 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1284 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1292 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1292 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1300 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1300 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1308 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1308 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1316 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1316 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1324 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1324 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1332 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1332 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1340 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1340 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1348 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1348 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1356 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1356 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire out_rimask_153 = |_out_rimask_T_153; // @[RegisterRouter.scala:87:24]
wire out_wimask_153 = &_out_wimask_T_153; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_153 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_153 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_161 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_161 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_169 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_169 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_177 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_177 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_185 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_185 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_193 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_193 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_201 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_201 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_209 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_209 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_217 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_217 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_225 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_225 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_233 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_233 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_241 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_241 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_249 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_249 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_257 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_257 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_265 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_265 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_273 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_273 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_281 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_281 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_289 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_289 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_297 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_297 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_305 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_305 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_313 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_313 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_321 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_321 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_329 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_329 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_337 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_337 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_345 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_345 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_353 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_353 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_361 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_361 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_369 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_369 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_377 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_377 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_385 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_385 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_393 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_393 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_401 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_401 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_409 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_409 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_417 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_417 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_425 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_425 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_433 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_433 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_441 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_441 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_449 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_449 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_457 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_457 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_465 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_465 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_473 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_473 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_481 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_481 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_489 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_489 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_497 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_497 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_507 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_507 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_515 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_515 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_523 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_523 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_531 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_531 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_539 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_539 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_547 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_547 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_555 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_555 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_563 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_563 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_571 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_571 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_579 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_579 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_587 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_587 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_596 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_596 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_604 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_604 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_612 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_612 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_620 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_620 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_628 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_628 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_640 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_640 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_648 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_648 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_656 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_656 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_664 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_664 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_672 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_672 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_680 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_680 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_690 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_690 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_698 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_698 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_706 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_706 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_714 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_714 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_722 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_722 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_730 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_730 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_738 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_738 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_746 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_746 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_754 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_754 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_762 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_762 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_770 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_770 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_778 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_778 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_786 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_786 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_794 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_794 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_802 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_802 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_810 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_810 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_818 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_818 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_826 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_826 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_834 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_834 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_842 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_842 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_852 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_852 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_860 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_860 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_868 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_868 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_876 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_876 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_884 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_884 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_892 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_892 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_900 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_900 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_908 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_908 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_916 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_916 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_924 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_924 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_932 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_932 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_940 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_940 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_948 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_948 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_956 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_956 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_964 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_964 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_972 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_972 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_980 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_980 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_988 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_988 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_996 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_996 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1004 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1004 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1012 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1012 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1020 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1020 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1028 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1028 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1036 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1036 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1044 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1044 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1052 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1052 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1060 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1060 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1068 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1068 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1076 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1076 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1084 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1084 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1092 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1092 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1100 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1100 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1108 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1108 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1116 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1116 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1124 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1124 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1132 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1132 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1140 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1140 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1148 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1148 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1156 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1156 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1164 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1164 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1172 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1172 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1180 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1180 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1188 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1188 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1196 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1196 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1204 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1204 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1212 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1212 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1220 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1220 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1228 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1228 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1236 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1236 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1244 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1244 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1252 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1252 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1260 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1260 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1268 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1268 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1276 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1276 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1284 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1284 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1292 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1292 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1300 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1300 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1308 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1308 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1316 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1316 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1324 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1324 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1332 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1332 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1340 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1340 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1348 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1348 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1356 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1356 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire out_romask_153 = |_out_romask_T_153; // @[RegisterRouter.scala:87:24]
wire out_womask_153 = &_out_womask_T_153; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_153 = out_rivalid_1_7 & out_rimask_153; // @[RegisterRouter.scala:87:24]
wire _out_T_1974 = out_f_rivalid_153; // @[RegisterRouter.scala:87:24]
wire out_f_roready_153 = out_roready_1_7 & out_romask_153; // @[RegisterRouter.scala:87:24]
wire _out_T_1975 = out_f_roready_153; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_153 = out_wivalid_1_7 & out_wimask_153; // @[RegisterRouter.scala:87:24]
wire out_f_woready_153 = out_woready_1_7 & out_womask_153; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1973 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2045 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2117 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2189 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2275 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2349 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2421 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2493 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2565 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2637 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2709 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2781 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2853 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2925 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3011 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3085 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3157 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3229 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3301 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3373 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3445 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3517 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3589 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3661 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3747 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3821 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3893 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3965 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4037 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4109 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4181 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4253 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4325 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4397 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4469 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4541 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4613 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4685 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4757 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4829 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4901 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4973 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5045 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5117 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5207 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5279 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5351 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5423 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5495 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5567 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5639 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5711 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5783 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5855 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5927 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6022 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6096 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6168 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6240 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6312 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6420 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6492 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6564 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6650 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6724 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6796 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6886 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6958 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7030 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7102 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7174 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7246 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7318 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7390 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7462 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7534 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7606 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7678 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7750 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7822 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7894 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7980 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8054 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8126 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8198 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8270 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8360 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8432 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8504 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8576 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8662 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8736 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8808 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8880 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8952 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9024 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9096 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9168 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9240 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9312 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9384 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9456 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9542 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9616 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9688 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9760 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9832 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9904 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9976 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10048 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10120 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10192 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10264 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10336 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10408 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10494 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10568 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10640 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10712 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10784 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10856 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10942 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11016 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11088 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11160 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11232 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11304 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11376 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11448 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11520 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11592 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11664 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11736 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11808 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11880 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11966 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12040 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12112 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12184 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12256 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12328 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12400 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12472 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12544 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12630 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12704 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12776 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12848 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12920 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12992 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire _out_T_1976 = ~out_rimask_153; // @[RegisterRouter.scala:87:24]
wire _out_T_1977 = ~out_wimask_153; // @[RegisterRouter.scala:87:24]
wire _out_T_1978 = ~out_romask_153; // @[RegisterRouter.scala:87:24]
wire _out_T_1979 = ~out_womask_153; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_118 = {hi_88, flags_0_go, _out_prepend_T_118}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_1980 = out_prepend_118; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_1981 = _out_T_1980; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_138 = _out_T_1981; // @[MuxLiteral.scala:49:48]
wire out_rimask_154 = |_out_rimask_T_154; // @[RegisterRouter.scala:87:24]
wire out_wimask_154 = &_out_wimask_T_154; // @[RegisterRouter.scala:87:24]
wire out_romask_154 = |_out_romask_T_154; // @[RegisterRouter.scala:87:24]
wire out_womask_154 = &_out_womask_T_154; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_154 = out_rivalid_1_8 & out_rimask_154; // @[RegisterRouter.scala:87:24]
wire _out_T_1983 = out_f_rivalid_154; // @[RegisterRouter.scala:87:24]
wire out_f_roready_154 = out_roready_1_8 & out_romask_154; // @[RegisterRouter.scala:87:24]
wire _out_T_1984 = out_f_roready_154; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_154 = out_wivalid_1_8 & out_wimask_154; // @[RegisterRouter.scala:87:24]
wire out_f_woready_154 = out_woready_1_8 & out_womask_154; // @[RegisterRouter.scala:87:24]
wire _out_T_1985 = ~out_rimask_154; // @[RegisterRouter.scala:87:24]
wire _out_T_1986 = ~out_wimask_154; // @[RegisterRouter.scala:87:24]
wire _out_T_1987 = ~out_romask_154; // @[RegisterRouter.scala:87:24]
wire _out_T_1988 = ~out_womask_154; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1990 = _out_T_1989; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_119 = _out_T_1990; // @[RegisterRouter.scala:87:24]
wire out_rimask_155 = |_out_rimask_T_155; // @[RegisterRouter.scala:87:24]
wire out_wimask_155 = &_out_wimask_T_155; // @[RegisterRouter.scala:87:24]
wire out_romask_155 = |_out_romask_T_155; // @[RegisterRouter.scala:87:24]
wire out_womask_155 = &_out_womask_T_155; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_155 = out_rivalid_1_9 & out_rimask_155; // @[RegisterRouter.scala:87:24]
wire _out_T_1992 = out_f_rivalid_155; // @[RegisterRouter.scala:87:24]
wire out_f_roready_155 = out_roready_1_9 & out_romask_155; // @[RegisterRouter.scala:87:24]
wire _out_T_1993 = out_f_roready_155; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_155 = out_wivalid_1_9 & out_wimask_155; // @[RegisterRouter.scala:87:24]
wire out_f_woready_155 = out_woready_1_9 & out_womask_155; // @[RegisterRouter.scala:87:24]
wire _out_T_1994 = ~out_rimask_155; // @[RegisterRouter.scala:87:24]
wire _out_T_1995 = ~out_wimask_155; // @[RegisterRouter.scala:87:24]
wire _out_T_1996 = ~out_romask_155; // @[RegisterRouter.scala:87:24]
wire _out_T_1997 = ~out_womask_155; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_119 = {hi_970, flags_0_go, _out_prepend_T_119}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_1998 = out_prepend_119; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_1999 = _out_T_1998; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_120 = _out_T_1999; // @[RegisterRouter.scala:87:24]
wire out_rimask_156 = |_out_rimask_T_156; // @[RegisterRouter.scala:87:24]
wire out_wimask_156 = &_out_wimask_T_156; // @[RegisterRouter.scala:87:24]
wire out_romask_156 = |_out_romask_T_156; // @[RegisterRouter.scala:87:24]
wire out_womask_156 = &_out_womask_T_156; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_156 = out_rivalid_1_10 & out_rimask_156; // @[RegisterRouter.scala:87:24]
wire _out_T_2001 = out_f_rivalid_156; // @[RegisterRouter.scala:87:24]
wire out_f_roready_156 = out_roready_1_10 & out_romask_156; // @[RegisterRouter.scala:87:24]
wire _out_T_2002 = out_f_roready_156; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_156 = out_wivalid_1_10 & out_wimask_156; // @[RegisterRouter.scala:87:24]
wire out_f_woready_156 = out_woready_1_10 & out_womask_156; // @[RegisterRouter.scala:87:24]
wire _out_T_2003 = ~out_rimask_156; // @[RegisterRouter.scala:87:24]
wire _out_T_2004 = ~out_wimask_156; // @[RegisterRouter.scala:87:24]
wire _out_T_2005 = ~out_romask_156; // @[RegisterRouter.scala:87:24]
wire _out_T_2006 = ~out_womask_156; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_120 = {hi_971, flags_0_go, _out_prepend_T_120}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_2007 = out_prepend_120; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_2008 = _out_T_2007; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_121 = _out_T_2008; // @[RegisterRouter.scala:87:24]
wire out_rimask_157 = |_out_rimask_T_157; // @[RegisterRouter.scala:87:24]
wire out_wimask_157 = &_out_wimask_T_157; // @[RegisterRouter.scala:87:24]
wire out_romask_157 = |_out_romask_T_157; // @[RegisterRouter.scala:87:24]
wire out_womask_157 = &_out_womask_T_157; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_157 = out_rivalid_1_11 & out_rimask_157; // @[RegisterRouter.scala:87:24]
wire _out_T_2010 = out_f_rivalid_157; // @[RegisterRouter.scala:87:24]
wire out_f_roready_157 = out_roready_1_11 & out_romask_157; // @[RegisterRouter.scala:87:24]
wire _out_T_2011 = out_f_roready_157; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_157 = out_wivalid_1_11 & out_wimask_157; // @[RegisterRouter.scala:87:24]
wire out_f_woready_157 = out_woready_1_11 & out_womask_157; // @[RegisterRouter.scala:87:24]
wire _out_T_2012 = ~out_rimask_157; // @[RegisterRouter.scala:87:24]
wire _out_T_2013 = ~out_wimask_157; // @[RegisterRouter.scala:87:24]
wire _out_T_2014 = ~out_romask_157; // @[RegisterRouter.scala:87:24]
wire _out_T_2015 = ~out_womask_157; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_121 = {hi_972, flags_0_go, _out_prepend_T_121}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_2016 = out_prepend_121; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_2017 = _out_T_2016; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_122 = _out_T_2017; // @[RegisterRouter.scala:87:24]
wire out_rimask_158 = |_out_rimask_T_158; // @[RegisterRouter.scala:87:24]
wire out_wimask_158 = &_out_wimask_T_158; // @[RegisterRouter.scala:87:24]
wire out_romask_158 = |_out_romask_T_158; // @[RegisterRouter.scala:87:24]
wire out_womask_158 = &_out_womask_T_158; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_158 = out_rivalid_1_12 & out_rimask_158; // @[RegisterRouter.scala:87:24]
wire _out_T_2019 = out_f_rivalid_158; // @[RegisterRouter.scala:87:24]
wire out_f_roready_158 = out_roready_1_12 & out_romask_158; // @[RegisterRouter.scala:87:24]
wire _out_T_2020 = out_f_roready_158; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_158 = out_wivalid_1_12 & out_wimask_158; // @[RegisterRouter.scala:87:24]
wire out_f_woready_158 = out_woready_1_12 & out_womask_158; // @[RegisterRouter.scala:87:24]
wire _out_T_2021 = ~out_rimask_158; // @[RegisterRouter.scala:87:24]
wire _out_T_2022 = ~out_wimask_158; // @[RegisterRouter.scala:87:24]
wire _out_T_2023 = ~out_romask_158; // @[RegisterRouter.scala:87:24]
wire _out_T_2024 = ~out_womask_158; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_122 = {hi_973, flags_0_go, _out_prepend_T_122}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_2025 = out_prepend_122; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_2026 = _out_T_2025; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_123 = _out_T_2026; // @[RegisterRouter.scala:87:24]
wire out_rimask_159 = |_out_rimask_T_159; // @[RegisterRouter.scala:87:24]
wire out_wimask_159 = &_out_wimask_T_159; // @[RegisterRouter.scala:87:24]
wire out_romask_159 = |_out_romask_T_159; // @[RegisterRouter.scala:87:24]
wire out_womask_159 = &_out_womask_T_159; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_159 = out_rivalid_1_13 & out_rimask_159; // @[RegisterRouter.scala:87:24]
wire _out_T_2028 = out_f_rivalid_159; // @[RegisterRouter.scala:87:24]
wire out_f_roready_159 = out_roready_1_13 & out_romask_159; // @[RegisterRouter.scala:87:24]
wire _out_T_2029 = out_f_roready_159; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_159 = out_wivalid_1_13 & out_wimask_159; // @[RegisterRouter.scala:87:24]
wire out_f_woready_159 = out_woready_1_13 & out_womask_159; // @[RegisterRouter.scala:87:24]
wire _out_T_2030 = ~out_rimask_159; // @[RegisterRouter.scala:87:24]
wire _out_T_2031 = ~out_wimask_159; // @[RegisterRouter.scala:87:24]
wire _out_T_2032 = ~out_romask_159; // @[RegisterRouter.scala:87:24]
wire _out_T_2033 = ~out_womask_159; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_123 = {hi_974, flags_0_go, _out_prepend_T_123}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_2034 = out_prepend_123; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_2035 = _out_T_2034; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_124 = _out_T_2035; // @[RegisterRouter.scala:87:24]
wire out_rimask_160 = |_out_rimask_T_160; // @[RegisterRouter.scala:87:24]
wire out_wimask_160 = &_out_wimask_T_160; // @[RegisterRouter.scala:87:24]
wire out_romask_160 = |_out_romask_T_160; // @[RegisterRouter.scala:87:24]
wire out_womask_160 = &_out_womask_T_160; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_160 = out_rivalid_1_14 & out_rimask_160; // @[RegisterRouter.scala:87:24]
wire _out_T_2037 = out_f_rivalid_160; // @[RegisterRouter.scala:87:24]
wire out_f_roready_160 = out_roready_1_14 & out_romask_160; // @[RegisterRouter.scala:87:24]
wire _out_T_2038 = out_f_roready_160; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_160 = out_wivalid_1_14 & out_wimask_160; // @[RegisterRouter.scala:87:24]
wire out_f_woready_160 = out_woready_1_14 & out_womask_160; // @[RegisterRouter.scala:87:24]
wire _out_T_2039 = ~out_rimask_160; // @[RegisterRouter.scala:87:24]
wire _out_T_2040 = ~out_wimask_160; // @[RegisterRouter.scala:87:24]
wire _out_T_2041 = ~out_romask_160; // @[RegisterRouter.scala:87:24]
wire _out_T_2042 = ~out_womask_160; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_124 = {hi_975, flags_0_go, _out_prepend_T_124}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_2043 = out_prepend_124; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_2044 = _out_T_2043; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_125 = _out_T_2044; // @[RegisterRouter.scala:87:24]
wire out_rimask_161 = |_out_rimask_T_161; // @[RegisterRouter.scala:87:24]
wire out_wimask_161 = &_out_wimask_T_161; // @[RegisterRouter.scala:87:24]
wire out_romask_161 = |_out_romask_T_161; // @[RegisterRouter.scala:87:24]
wire out_womask_161 = &_out_womask_T_161; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_161 = out_rivalid_1_15 & out_rimask_161; // @[RegisterRouter.scala:87:24]
wire _out_T_2046 = out_f_rivalid_161; // @[RegisterRouter.scala:87:24]
wire out_f_roready_161 = out_roready_1_15 & out_romask_161; // @[RegisterRouter.scala:87:24]
wire _out_T_2047 = out_f_roready_161; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_161 = out_wivalid_1_15 & out_wimask_161; // @[RegisterRouter.scala:87:24]
wire out_f_woready_161 = out_woready_1_15 & out_womask_161; // @[RegisterRouter.scala:87:24]
wire _out_T_2048 = ~out_rimask_161; // @[RegisterRouter.scala:87:24]
wire _out_T_2049 = ~out_wimask_161; // @[RegisterRouter.scala:87:24]
wire _out_T_2050 = ~out_romask_161; // @[RegisterRouter.scala:87:24]
wire _out_T_2051 = ~out_womask_161; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_125 = {hi_976, flags_0_go, _out_prepend_T_125}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_2052 = out_prepend_125; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_2053 = _out_T_2052; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_249 = _out_T_2053; // @[MuxLiteral.scala:49:48]
wire out_rimask_162 = |_out_rimask_T_162; // @[RegisterRouter.scala:87:24]
wire out_wimask_162 = &_out_wimask_T_162; // @[RegisterRouter.scala:87:24]
wire out_romask_162 = |_out_romask_T_162; // @[RegisterRouter.scala:87:24]
wire out_womask_162 = &_out_womask_T_162; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_162 = out_rivalid_1_16 & out_rimask_162; // @[RegisterRouter.scala:87:24]
wire _out_T_2055 = out_f_rivalid_162; // @[RegisterRouter.scala:87:24]
wire out_f_roready_162 = out_roready_1_16 & out_romask_162; // @[RegisterRouter.scala:87:24]
wire _out_T_2056 = out_f_roready_162; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_162 = out_wivalid_1_16 & out_wimask_162; // @[RegisterRouter.scala:87:24]
wire out_f_woready_162 = out_woready_1_16 & out_womask_162; // @[RegisterRouter.scala:87:24]
wire _out_T_2057 = ~out_rimask_162; // @[RegisterRouter.scala:87:24]
wire _out_T_2058 = ~out_wimask_162; // @[RegisterRouter.scala:87:24]
wire _out_T_2059 = ~out_romask_162; // @[RegisterRouter.scala:87:24]
wire _out_T_2060 = ~out_womask_162; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2062 = _out_T_2061; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_126 = _out_T_2062; // @[RegisterRouter.scala:87:24]
wire out_rimask_163 = |_out_rimask_T_163; // @[RegisterRouter.scala:87:24]
wire out_wimask_163 = &_out_wimask_T_163; // @[RegisterRouter.scala:87:24]
wire out_romask_163 = |_out_romask_T_163; // @[RegisterRouter.scala:87:24]
wire out_womask_163 = &_out_womask_T_163; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_163 = out_rivalid_1_17 & out_rimask_163; // @[RegisterRouter.scala:87:24]
wire _out_T_2064 = out_f_rivalid_163; // @[RegisterRouter.scala:87:24]
wire out_f_roready_163 = out_roready_1_17 & out_romask_163; // @[RegisterRouter.scala:87:24]
wire _out_T_2065 = out_f_roready_163; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_163 = out_wivalid_1_17 & out_wimask_163; // @[RegisterRouter.scala:87:24]
wire out_f_woready_163 = out_woready_1_17 & out_womask_163; // @[RegisterRouter.scala:87:24]
wire _out_T_2066 = ~out_rimask_163; // @[RegisterRouter.scala:87:24]
wire _out_T_2067 = ~out_wimask_163; // @[RegisterRouter.scala:87:24]
wire _out_T_2068 = ~out_romask_163; // @[RegisterRouter.scala:87:24]
wire _out_T_2069 = ~out_womask_163; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_126 = {hi_850, flags_0_go, _out_prepend_T_126}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_2070 = out_prepend_126; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_2071 = _out_T_2070; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_127 = _out_T_2071; // @[RegisterRouter.scala:87:24]
wire out_rimask_164 = |_out_rimask_T_164; // @[RegisterRouter.scala:87:24]
wire out_wimask_164 = &_out_wimask_T_164; // @[RegisterRouter.scala:87:24]
wire out_romask_164 = |_out_romask_T_164; // @[RegisterRouter.scala:87:24]
wire out_womask_164 = &_out_womask_T_164; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_164 = out_rivalid_1_18 & out_rimask_164; // @[RegisterRouter.scala:87:24]
wire _out_T_2073 = out_f_rivalid_164; // @[RegisterRouter.scala:87:24]
wire out_f_roready_164 = out_roready_1_18 & out_romask_164; // @[RegisterRouter.scala:87:24]
wire _out_T_2074 = out_f_roready_164; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_164 = out_wivalid_1_18 & out_wimask_164; // @[RegisterRouter.scala:87:24]
wire out_f_woready_164 = out_woready_1_18 & out_womask_164; // @[RegisterRouter.scala:87:24]
wire _out_T_2075 = ~out_rimask_164; // @[RegisterRouter.scala:87:24]
wire _out_T_2076 = ~out_wimask_164; // @[RegisterRouter.scala:87:24]
wire _out_T_2077 = ~out_romask_164; // @[RegisterRouter.scala:87:24]
wire _out_T_2078 = ~out_womask_164; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_127 = {hi_851, flags_0_go, _out_prepend_T_127}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_2079 = out_prepend_127; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_2080 = _out_T_2079; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_128 = _out_T_2080; // @[RegisterRouter.scala:87:24]
wire out_rimask_165 = |_out_rimask_T_165; // @[RegisterRouter.scala:87:24]
wire out_wimask_165 = &_out_wimask_T_165; // @[RegisterRouter.scala:87:24]
wire out_romask_165 = |_out_romask_T_165; // @[RegisterRouter.scala:87:24]
wire out_womask_165 = &_out_womask_T_165; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_165 = out_rivalid_1_19 & out_rimask_165; // @[RegisterRouter.scala:87:24]
wire _out_T_2082 = out_f_rivalid_165; // @[RegisterRouter.scala:87:24]
wire out_f_roready_165 = out_roready_1_19 & out_romask_165; // @[RegisterRouter.scala:87:24]
wire _out_T_2083 = out_f_roready_165; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_165 = out_wivalid_1_19 & out_wimask_165; // @[RegisterRouter.scala:87:24]
wire out_f_woready_165 = out_woready_1_19 & out_womask_165; // @[RegisterRouter.scala:87:24]
wire _out_T_2084 = ~out_rimask_165; // @[RegisterRouter.scala:87:24]
wire _out_T_2085 = ~out_wimask_165; // @[RegisterRouter.scala:87:24]
wire _out_T_2086 = ~out_romask_165; // @[RegisterRouter.scala:87:24]
wire _out_T_2087 = ~out_womask_165; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_128 = {hi_852, flags_0_go, _out_prepend_T_128}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_2088 = out_prepend_128; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_2089 = _out_T_2088; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_129 = _out_T_2089; // @[RegisterRouter.scala:87:24]
wire out_rimask_166 = |_out_rimask_T_166; // @[RegisterRouter.scala:87:24]
wire out_wimask_166 = &_out_wimask_T_166; // @[RegisterRouter.scala:87:24]
wire out_romask_166 = |_out_romask_T_166; // @[RegisterRouter.scala:87:24]
wire out_womask_166 = &_out_womask_T_166; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_166 = out_rivalid_1_20 & out_rimask_166; // @[RegisterRouter.scala:87:24]
wire _out_T_2091 = out_f_rivalid_166; // @[RegisterRouter.scala:87:24]
wire out_f_roready_166 = out_roready_1_20 & out_romask_166; // @[RegisterRouter.scala:87:24]
wire _out_T_2092 = out_f_roready_166; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_166 = out_wivalid_1_20 & out_wimask_166; // @[RegisterRouter.scala:87:24]
wire out_f_woready_166 = out_woready_1_20 & out_womask_166; // @[RegisterRouter.scala:87:24]
wire _out_T_2093 = ~out_rimask_166; // @[RegisterRouter.scala:87:24]
wire _out_T_2094 = ~out_wimask_166; // @[RegisterRouter.scala:87:24]
wire _out_T_2095 = ~out_romask_166; // @[RegisterRouter.scala:87:24]
wire _out_T_2096 = ~out_womask_166; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_129 = {hi_853, flags_0_go, _out_prepend_T_129}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_2097 = out_prepend_129; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_2098 = _out_T_2097; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_130 = _out_T_2098; // @[RegisterRouter.scala:87:24]
wire out_rimask_167 = |_out_rimask_T_167; // @[RegisterRouter.scala:87:24]
wire out_wimask_167 = &_out_wimask_T_167; // @[RegisterRouter.scala:87:24]
wire out_romask_167 = |_out_romask_T_167; // @[RegisterRouter.scala:87:24]
wire out_womask_167 = &_out_womask_T_167; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_167 = out_rivalid_1_21 & out_rimask_167; // @[RegisterRouter.scala:87:24]
wire _out_T_2100 = out_f_rivalid_167; // @[RegisterRouter.scala:87:24]
wire out_f_roready_167 = out_roready_1_21 & out_romask_167; // @[RegisterRouter.scala:87:24]
wire _out_T_2101 = out_f_roready_167; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_167 = out_wivalid_1_21 & out_wimask_167; // @[RegisterRouter.scala:87:24]
wire out_f_woready_167 = out_woready_1_21 & out_womask_167; // @[RegisterRouter.scala:87:24]
wire _out_T_2102 = ~out_rimask_167; // @[RegisterRouter.scala:87:24]
wire _out_T_2103 = ~out_wimask_167; // @[RegisterRouter.scala:87:24]
wire _out_T_2104 = ~out_romask_167; // @[RegisterRouter.scala:87:24]
wire _out_T_2105 = ~out_womask_167; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_130 = {hi_854, flags_0_go, _out_prepend_T_130}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_2106 = out_prepend_130; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_2107 = _out_T_2106; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_131 = _out_T_2107; // @[RegisterRouter.scala:87:24]
wire out_rimask_168 = |_out_rimask_T_168; // @[RegisterRouter.scala:87:24]
wire out_wimask_168 = &_out_wimask_T_168; // @[RegisterRouter.scala:87:24]
wire out_romask_168 = |_out_romask_T_168; // @[RegisterRouter.scala:87:24]
wire out_womask_168 = &_out_womask_T_168; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_168 = out_rivalid_1_22 & out_rimask_168; // @[RegisterRouter.scala:87:24]
wire _out_T_2109 = out_f_rivalid_168; // @[RegisterRouter.scala:87:24]
wire out_f_roready_168 = out_roready_1_22 & out_romask_168; // @[RegisterRouter.scala:87:24]
wire _out_T_2110 = out_f_roready_168; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_168 = out_wivalid_1_22 & out_wimask_168; // @[RegisterRouter.scala:87:24]
wire out_f_woready_168 = out_woready_1_22 & out_womask_168; // @[RegisterRouter.scala:87:24]
wire _out_T_2111 = ~out_rimask_168; // @[RegisterRouter.scala:87:24]
wire _out_T_2112 = ~out_wimask_168; // @[RegisterRouter.scala:87:24]
wire _out_T_2113 = ~out_romask_168; // @[RegisterRouter.scala:87:24]
wire _out_T_2114 = ~out_womask_168; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_131 = {hi_855, flags_0_go, _out_prepend_T_131}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_2115 = out_prepend_131; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_2116 = _out_T_2115; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_132 = _out_T_2116; // @[RegisterRouter.scala:87:24]
wire out_rimask_169 = |_out_rimask_T_169; // @[RegisterRouter.scala:87:24]
wire out_wimask_169 = &_out_wimask_T_169; // @[RegisterRouter.scala:87:24]
wire out_romask_169 = |_out_romask_T_169; // @[RegisterRouter.scala:87:24]
wire out_womask_169 = &_out_womask_T_169; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_169 = out_rivalid_1_23 & out_rimask_169; // @[RegisterRouter.scala:87:24]
wire _out_T_2118 = out_f_rivalid_169; // @[RegisterRouter.scala:87:24]
wire out_f_roready_169 = out_roready_1_23 & out_romask_169; // @[RegisterRouter.scala:87:24]
wire _out_T_2119 = out_f_roready_169; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_169 = out_wivalid_1_23 & out_wimask_169; // @[RegisterRouter.scala:87:24]
wire out_f_woready_169 = out_woready_1_23 & out_womask_169; // @[RegisterRouter.scala:87:24]
wire _out_T_2120 = ~out_rimask_169; // @[RegisterRouter.scala:87:24]
wire _out_T_2121 = ~out_wimask_169; // @[RegisterRouter.scala:87:24]
wire _out_T_2122 = ~out_romask_169; // @[RegisterRouter.scala:87:24]
wire _out_T_2123 = ~out_womask_169; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_132 = {hi_856, flags_0_go, _out_prepend_T_132}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_2124 = out_prepend_132; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_2125 = _out_T_2124; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_234 = _out_T_2125; // @[MuxLiteral.scala:49:48]
wire out_rimask_170 = |_out_rimask_T_170; // @[RegisterRouter.scala:87:24]
wire out_wimask_170 = &_out_wimask_T_170; // @[RegisterRouter.scala:87:24]
wire out_romask_170 = |_out_romask_T_170; // @[RegisterRouter.scala:87:24]
wire out_womask_170 = &_out_womask_T_170; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_170 = out_rivalid_1_24 & out_rimask_170; // @[RegisterRouter.scala:87:24]
wire _out_T_2127 = out_f_rivalid_170; // @[RegisterRouter.scala:87:24]
wire out_f_roready_170 = out_roready_1_24 & out_romask_170; // @[RegisterRouter.scala:87:24]
wire _out_T_2128 = out_f_roready_170; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_170 = out_wivalid_1_24 & out_wimask_170; // @[RegisterRouter.scala:87:24]
wire out_f_woready_170 = out_woready_1_24 & out_womask_170; // @[RegisterRouter.scala:87:24]
wire _out_T_2129 = ~out_rimask_170; // @[RegisterRouter.scala:87:24]
wire _out_T_2130 = ~out_wimask_170; // @[RegisterRouter.scala:87:24]
wire _out_T_2131 = ~out_romask_170; // @[RegisterRouter.scala:87:24]
wire _out_T_2132 = ~out_womask_170; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2134 = _out_T_2133; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_133 = _out_T_2134; // @[RegisterRouter.scala:87:24]
wire out_rimask_171 = |_out_rimask_T_171; // @[RegisterRouter.scala:87:24]
wire out_wimask_171 = &_out_wimask_T_171; // @[RegisterRouter.scala:87:24]
wire out_romask_171 = |_out_romask_T_171; // @[RegisterRouter.scala:87:24]
wire out_womask_171 = &_out_womask_T_171; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_171 = out_rivalid_1_25 & out_rimask_171; // @[RegisterRouter.scala:87:24]
wire _out_T_2136 = out_f_rivalid_171; // @[RegisterRouter.scala:87:24]
wire out_f_roready_171 = out_roready_1_25 & out_romask_171; // @[RegisterRouter.scala:87:24]
wire _out_T_2137 = out_f_roready_171; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_171 = out_wivalid_1_25 & out_wimask_171; // @[RegisterRouter.scala:87:24]
wire out_f_woready_171 = out_woready_1_25 & out_womask_171; // @[RegisterRouter.scala:87:24]
wire _out_T_2138 = ~out_rimask_171; // @[RegisterRouter.scala:87:24]
wire _out_T_2139 = ~out_wimask_171; // @[RegisterRouter.scala:87:24]
wire _out_T_2140 = ~out_romask_171; // @[RegisterRouter.scala:87:24]
wire _out_T_2141 = ~out_womask_171; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_133 = {hi_338, flags_0_go, _out_prepend_T_133}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_2142 = out_prepend_133; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_2143 = _out_T_2142; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_134 = _out_T_2143; // @[RegisterRouter.scala:87:24]
wire out_rimask_172 = |_out_rimask_T_172; // @[RegisterRouter.scala:87:24]
wire out_wimask_172 = &_out_wimask_T_172; // @[RegisterRouter.scala:87:24]
wire out_romask_172 = |_out_romask_T_172; // @[RegisterRouter.scala:87:24]
wire out_womask_172 = &_out_womask_T_172; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_172 = out_rivalid_1_26 & out_rimask_172; // @[RegisterRouter.scala:87:24]
wire _out_T_2145 = out_f_rivalid_172; // @[RegisterRouter.scala:87:24]
wire out_f_roready_172 = out_roready_1_26 & out_romask_172; // @[RegisterRouter.scala:87:24]
wire _out_T_2146 = out_f_roready_172; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_172 = out_wivalid_1_26 & out_wimask_172; // @[RegisterRouter.scala:87:24]
wire out_f_woready_172 = out_woready_1_26 & out_womask_172; // @[RegisterRouter.scala:87:24]
wire _out_T_2147 = ~out_rimask_172; // @[RegisterRouter.scala:87:24]
wire _out_T_2148 = ~out_wimask_172; // @[RegisterRouter.scala:87:24]
wire _out_T_2149 = ~out_romask_172; // @[RegisterRouter.scala:87:24]
wire _out_T_2150 = ~out_womask_172; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_134 = {hi_339, flags_0_go, _out_prepend_T_134}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_2151 = out_prepend_134; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_2152 = _out_T_2151; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_135 = _out_T_2152; // @[RegisterRouter.scala:87:24]
wire out_rimask_173 = |_out_rimask_T_173; // @[RegisterRouter.scala:87:24]
wire out_wimask_173 = &_out_wimask_T_173; // @[RegisterRouter.scala:87:24]
wire out_romask_173 = |_out_romask_T_173; // @[RegisterRouter.scala:87:24]
wire out_womask_173 = &_out_womask_T_173; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_173 = out_rivalid_1_27 & out_rimask_173; // @[RegisterRouter.scala:87:24]
wire _out_T_2154 = out_f_rivalid_173; // @[RegisterRouter.scala:87:24]
wire out_f_roready_173 = out_roready_1_27 & out_romask_173; // @[RegisterRouter.scala:87:24]
wire _out_T_2155 = out_f_roready_173; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_173 = out_wivalid_1_27 & out_wimask_173; // @[RegisterRouter.scala:87:24]
wire out_f_woready_173 = out_woready_1_27 & out_womask_173; // @[RegisterRouter.scala:87:24]
wire _out_T_2156 = ~out_rimask_173; // @[RegisterRouter.scala:87:24]
wire _out_T_2157 = ~out_wimask_173; // @[RegisterRouter.scala:87:24]
wire _out_T_2158 = ~out_romask_173; // @[RegisterRouter.scala:87:24]
wire _out_T_2159 = ~out_womask_173; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_135 = {hi_340, flags_0_go, _out_prepend_T_135}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_2160 = out_prepend_135; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_2161 = _out_T_2160; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_136 = _out_T_2161; // @[RegisterRouter.scala:87:24]
wire out_rimask_174 = |_out_rimask_T_174; // @[RegisterRouter.scala:87:24]
wire out_wimask_174 = &_out_wimask_T_174; // @[RegisterRouter.scala:87:24]
wire out_romask_174 = |_out_romask_T_174; // @[RegisterRouter.scala:87:24]
wire out_womask_174 = &_out_womask_T_174; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_174 = out_rivalid_1_28 & out_rimask_174; // @[RegisterRouter.scala:87:24]
wire _out_T_2163 = out_f_rivalid_174; // @[RegisterRouter.scala:87:24]
wire out_f_roready_174 = out_roready_1_28 & out_romask_174; // @[RegisterRouter.scala:87:24]
wire _out_T_2164 = out_f_roready_174; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_174 = out_wivalid_1_28 & out_wimask_174; // @[RegisterRouter.scala:87:24]
wire out_f_woready_174 = out_woready_1_28 & out_womask_174; // @[RegisterRouter.scala:87:24]
wire _out_T_2165 = ~out_rimask_174; // @[RegisterRouter.scala:87:24]
wire _out_T_2166 = ~out_wimask_174; // @[RegisterRouter.scala:87:24]
wire _out_T_2167 = ~out_romask_174; // @[RegisterRouter.scala:87:24]
wire _out_T_2168 = ~out_womask_174; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_136 = {hi_341, flags_0_go, _out_prepend_T_136}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_2169 = out_prepend_136; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_2170 = _out_T_2169; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_137 = _out_T_2170; // @[RegisterRouter.scala:87:24]
wire out_rimask_175 = |_out_rimask_T_175; // @[RegisterRouter.scala:87:24]
wire out_wimask_175 = &_out_wimask_T_175; // @[RegisterRouter.scala:87:24]
wire out_romask_175 = |_out_romask_T_175; // @[RegisterRouter.scala:87:24]
wire out_womask_175 = &_out_womask_T_175; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_175 = out_rivalid_1_29 & out_rimask_175; // @[RegisterRouter.scala:87:24]
wire _out_T_2172 = out_f_rivalid_175; // @[RegisterRouter.scala:87:24]
wire out_f_roready_175 = out_roready_1_29 & out_romask_175; // @[RegisterRouter.scala:87:24]
wire _out_T_2173 = out_f_roready_175; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_175 = out_wivalid_1_29 & out_wimask_175; // @[RegisterRouter.scala:87:24]
wire out_f_woready_175 = out_woready_1_29 & out_womask_175; // @[RegisterRouter.scala:87:24]
wire _out_T_2174 = ~out_rimask_175; // @[RegisterRouter.scala:87:24]
wire _out_T_2175 = ~out_wimask_175; // @[RegisterRouter.scala:87:24]
wire _out_T_2176 = ~out_romask_175; // @[RegisterRouter.scala:87:24]
wire _out_T_2177 = ~out_womask_175; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_137 = {hi_342, flags_0_go, _out_prepend_T_137}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_2178 = out_prepend_137; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_2179 = _out_T_2178; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_138 = _out_T_2179; // @[RegisterRouter.scala:87:24]
wire out_rimask_176 = |_out_rimask_T_176; // @[RegisterRouter.scala:87:24]
wire out_wimask_176 = &_out_wimask_T_176; // @[RegisterRouter.scala:87:24]
wire out_romask_176 = |_out_romask_T_176; // @[RegisterRouter.scala:87:24]
wire out_womask_176 = &_out_womask_T_176; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_176 = out_rivalid_1_30 & out_rimask_176; // @[RegisterRouter.scala:87:24]
wire _out_T_2181 = out_f_rivalid_176; // @[RegisterRouter.scala:87:24]
wire out_f_roready_176 = out_roready_1_30 & out_romask_176; // @[RegisterRouter.scala:87:24]
wire _out_T_2182 = out_f_roready_176; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_176 = out_wivalid_1_30 & out_wimask_176; // @[RegisterRouter.scala:87:24]
wire out_f_woready_176 = out_woready_1_30 & out_womask_176; // @[RegisterRouter.scala:87:24]
wire _out_T_2183 = ~out_rimask_176; // @[RegisterRouter.scala:87:24]
wire _out_T_2184 = ~out_wimask_176; // @[RegisterRouter.scala:87:24]
wire _out_T_2185 = ~out_romask_176; // @[RegisterRouter.scala:87:24]
wire _out_T_2186 = ~out_womask_176; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_138 = {hi_343, flags_0_go, _out_prepend_T_138}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_2187 = out_prepend_138; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_2188 = _out_T_2187; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_139 = _out_T_2188; // @[RegisterRouter.scala:87:24]
wire out_rimask_177 = |_out_rimask_T_177; // @[RegisterRouter.scala:87:24]
wire out_wimask_177 = &_out_wimask_T_177; // @[RegisterRouter.scala:87:24]
wire out_romask_177 = |_out_romask_T_177; // @[RegisterRouter.scala:87:24]
wire out_womask_177 = &_out_womask_T_177; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_177 = out_rivalid_1_31 & out_rimask_177; // @[RegisterRouter.scala:87:24]
wire _out_T_2190 = out_f_rivalid_177; // @[RegisterRouter.scala:87:24]
wire out_f_roready_177 = out_roready_1_31 & out_romask_177; // @[RegisterRouter.scala:87:24]
wire _out_T_2191 = out_f_roready_177; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_177 = out_wivalid_1_31 & out_wimask_177; // @[RegisterRouter.scala:87:24]
wire out_f_woready_177 = out_woready_1_31 & out_womask_177; // @[RegisterRouter.scala:87:24]
wire _out_T_2192 = ~out_rimask_177; // @[RegisterRouter.scala:87:24]
wire _out_T_2193 = ~out_wimask_177; // @[RegisterRouter.scala:87:24]
wire _out_T_2194 = ~out_romask_177; // @[RegisterRouter.scala:87:24]
wire _out_T_2195 = ~out_womask_177; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_139 = {hi_344, flags_0_go, _out_prepend_T_139}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_2196 = out_prepend_139; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_2197 = _out_T_2196; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_170 = _out_T_2197; // @[MuxLiteral.scala:49:48]
wire out_rimask_178 = |_out_rimask_T_178; // @[RegisterRouter.scala:87:24]
wire out_wimask_178 = &_out_wimask_T_178; // @[RegisterRouter.scala:87:24]
wire out_romask_178 = |_out_romask_T_178; // @[RegisterRouter.scala:87:24]
wire out_womask_178 = &_out_womask_T_178; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_178 = out_rivalid_1_32 & out_rimask_178; // @[RegisterRouter.scala:87:24]
wire _out_T_2199 = out_f_rivalid_178; // @[RegisterRouter.scala:87:24]
wire out_f_roready_178 = out_roready_1_32 & out_romask_178; // @[RegisterRouter.scala:87:24]
wire _out_T_2200 = out_f_roready_178; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_178 = out_wivalid_1_32 & out_wimask_178; // @[RegisterRouter.scala:87:24]
wire _out_T_2201 = out_f_wivalid_178; // @[RegisterRouter.scala:87:24]
wire out_f_woready_178 = out_woready_1_32 & out_womask_178; // @[RegisterRouter.scala:87:24]
wire _out_T_2202 = out_f_woready_178; // @[RegisterRouter.scala:87:24]
wire _out_T_2203 = ~out_rimask_178; // @[RegisterRouter.scala:87:24]
wire _out_T_2204 = ~out_wimask_178; // @[RegisterRouter.scala:87:24]
wire _out_T_2205 = ~out_romask_178; // @[RegisterRouter.scala:87:24]
wire _out_T_2206 = ~out_womask_178; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2208 = _out_T_2207; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_140 = _out_T_2208; // @[RegisterRouter.scala:87:24]
wire out_rimask_179 = |_out_rimask_T_179; // @[RegisterRouter.scala:87:24]
wire out_wimask_179 = &_out_wimask_T_179; // @[RegisterRouter.scala:87:24]
wire out_romask_179 = |_out_romask_T_179; // @[RegisterRouter.scala:87:24]
wire out_womask_179 = &_out_womask_T_179; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_179 = out_rivalid_1_33 & out_rimask_179; // @[RegisterRouter.scala:87:24]
wire _out_T_2210 = out_f_rivalid_179; // @[RegisterRouter.scala:87:24]
wire out_f_roready_179 = out_roready_1_33 & out_romask_179; // @[RegisterRouter.scala:87:24]
wire _out_T_2211 = out_f_roready_179; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_179 = out_wivalid_1_33 & out_wimask_179; // @[RegisterRouter.scala:87:24]
wire _out_T_2212 = out_f_wivalid_179; // @[RegisterRouter.scala:87:24]
wire out_f_woready_179 = out_woready_1_33 & out_womask_179; // @[RegisterRouter.scala:87:24]
wire _out_T_2213 = out_f_woready_179; // @[RegisterRouter.scala:87:24]
wire _out_T_2214 = ~out_rimask_179; // @[RegisterRouter.scala:87:24]
wire _out_T_2215 = ~out_wimask_179; // @[RegisterRouter.scala:87:24]
wire _out_T_2216 = ~out_romask_179; // @[RegisterRouter.scala:87:24]
wire _out_T_2217 = ~out_womask_179; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_140 = {abstractDataMem_25, _out_prepend_T_140}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_2218 = out_prepend_140; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_2219 = _out_T_2218; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_141 = _out_T_2219; // @[RegisterRouter.scala:87:24]
wire out_rimask_180 = |_out_rimask_T_180; // @[RegisterRouter.scala:87:24]
wire out_wimask_180 = &_out_wimask_T_180; // @[RegisterRouter.scala:87:24]
wire out_romask_180 = |_out_romask_T_180; // @[RegisterRouter.scala:87:24]
wire out_womask_180 = &_out_womask_T_180; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_180 = out_rivalid_1_34 & out_rimask_180; // @[RegisterRouter.scala:87:24]
wire _out_T_2221 = out_f_rivalid_180; // @[RegisterRouter.scala:87:24]
wire out_f_roready_180 = out_roready_1_34 & out_romask_180; // @[RegisterRouter.scala:87:24]
wire _out_T_2222 = out_f_roready_180; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_180 = out_wivalid_1_34 & out_wimask_180; // @[RegisterRouter.scala:87:24]
wire _out_T_2223 = out_f_wivalid_180; // @[RegisterRouter.scala:87:24]
wire out_f_woready_180 = out_woready_1_34 & out_womask_180; // @[RegisterRouter.scala:87:24]
wire _out_T_2224 = out_f_woready_180; // @[RegisterRouter.scala:87:24]
wire _out_T_2225 = ~out_rimask_180; // @[RegisterRouter.scala:87:24]
wire _out_T_2226 = ~out_wimask_180; // @[RegisterRouter.scala:87:24]
wire _out_T_2227 = ~out_romask_180; // @[RegisterRouter.scala:87:24]
wire _out_T_2228 = ~out_womask_180; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_141 = {abstractDataMem_26, _out_prepend_T_141}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_2229 = out_prepend_141; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_2230 = _out_T_2229; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_142 = _out_T_2230; // @[RegisterRouter.scala:87:24]
wire out_rimask_181 = |_out_rimask_T_181; // @[RegisterRouter.scala:87:24]
wire out_wimask_181 = &_out_wimask_T_181; // @[RegisterRouter.scala:87:24]
wire out_romask_181 = |_out_romask_T_181; // @[RegisterRouter.scala:87:24]
wire out_womask_181 = &_out_womask_T_181; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_181 = out_rivalid_1_35 & out_rimask_181; // @[RegisterRouter.scala:87:24]
wire _out_T_2232 = out_f_rivalid_181; // @[RegisterRouter.scala:87:24]
wire out_f_roready_181 = out_roready_1_35 & out_romask_181; // @[RegisterRouter.scala:87:24]
wire _out_T_2233 = out_f_roready_181; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_181 = out_wivalid_1_35 & out_wimask_181; // @[RegisterRouter.scala:87:24]
wire _out_T_2234 = out_f_wivalid_181; // @[RegisterRouter.scala:87:24]
wire out_f_woready_181 = out_woready_1_35 & out_womask_181; // @[RegisterRouter.scala:87:24]
wire _out_T_2235 = out_f_woready_181; // @[RegisterRouter.scala:87:24]
wire _out_T_2236 = ~out_rimask_181; // @[RegisterRouter.scala:87:24]
wire _out_T_2237 = ~out_wimask_181; // @[RegisterRouter.scala:87:24]
wire _out_T_2238 = ~out_romask_181; // @[RegisterRouter.scala:87:24]
wire _out_T_2239 = ~out_womask_181; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_142 = {abstractDataMem_27, _out_prepend_T_142}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_2240 = out_prepend_142; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_2241 = _out_T_2240; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_143 = _out_T_2241; // @[RegisterRouter.scala:87:24]
wire out_rimask_182 = |_out_rimask_T_182; // @[RegisterRouter.scala:87:24]
wire out_wimask_182 = &_out_wimask_T_182; // @[RegisterRouter.scala:87:24]
wire out_romask_182 = |_out_romask_T_182; // @[RegisterRouter.scala:87:24]
wire out_womask_182 = &_out_womask_T_182; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_182 = out_rivalid_1_36 & out_rimask_182; // @[RegisterRouter.scala:87:24]
wire _out_T_2243 = out_f_rivalid_182; // @[RegisterRouter.scala:87:24]
wire out_f_roready_182 = out_roready_1_36 & out_romask_182; // @[RegisterRouter.scala:87:24]
wire _out_T_2244 = out_f_roready_182; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_182 = out_wivalid_1_36 & out_wimask_182; // @[RegisterRouter.scala:87:24]
wire _out_T_2245 = out_f_wivalid_182; // @[RegisterRouter.scala:87:24]
wire out_f_woready_182 = out_woready_1_36 & out_womask_182; // @[RegisterRouter.scala:87:24]
wire _out_T_2246 = out_f_woready_182; // @[RegisterRouter.scala:87:24]
wire _out_T_2247 = ~out_rimask_182; // @[RegisterRouter.scala:87:24]
wire _out_T_2248 = ~out_wimask_182; // @[RegisterRouter.scala:87:24]
wire _out_T_2249 = ~out_romask_182; // @[RegisterRouter.scala:87:24]
wire _out_T_2250 = ~out_womask_182; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_143 = {abstractDataMem_28, _out_prepend_T_143}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_2251 = out_prepend_143; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_2252 = _out_T_2251; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_144 = _out_T_2252; // @[RegisterRouter.scala:87:24]
wire out_rimask_183 = |_out_rimask_T_183; // @[RegisterRouter.scala:87:24]
wire out_wimask_183 = &_out_wimask_T_183; // @[RegisterRouter.scala:87:24]
wire out_romask_183 = |_out_romask_T_183; // @[RegisterRouter.scala:87:24]
wire out_womask_183 = &_out_womask_T_183; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_183 = out_rivalid_1_37 & out_rimask_183; // @[RegisterRouter.scala:87:24]
wire _out_T_2254 = out_f_rivalid_183; // @[RegisterRouter.scala:87:24]
wire out_f_roready_183 = out_roready_1_37 & out_romask_183; // @[RegisterRouter.scala:87:24]
wire _out_T_2255 = out_f_roready_183; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_183 = out_wivalid_1_37 & out_wimask_183; // @[RegisterRouter.scala:87:24]
wire _out_T_2256 = out_f_wivalid_183; // @[RegisterRouter.scala:87:24]
wire out_f_woready_183 = out_woready_1_37 & out_womask_183; // @[RegisterRouter.scala:87:24]
wire _out_T_2257 = out_f_woready_183; // @[RegisterRouter.scala:87:24]
wire _out_T_2258 = ~out_rimask_183; // @[RegisterRouter.scala:87:24]
wire _out_T_2259 = ~out_wimask_183; // @[RegisterRouter.scala:87:24]
wire _out_T_2260 = ~out_romask_183; // @[RegisterRouter.scala:87:24]
wire _out_T_2261 = ~out_womask_183; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_144 = {abstractDataMem_29, _out_prepend_T_144}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_2262 = out_prepend_144; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_2263 = _out_T_2262; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_145 = _out_T_2263; // @[RegisterRouter.scala:87:24]
wire out_rimask_184 = |_out_rimask_T_184; // @[RegisterRouter.scala:87:24]
wire out_wimask_184 = &_out_wimask_T_184; // @[RegisterRouter.scala:87:24]
wire out_romask_184 = |_out_romask_T_184; // @[RegisterRouter.scala:87:24]
wire out_womask_184 = &_out_womask_T_184; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_184 = out_rivalid_1_38 & out_rimask_184; // @[RegisterRouter.scala:87:24]
wire _out_T_2265 = out_f_rivalid_184; // @[RegisterRouter.scala:87:24]
wire out_f_roready_184 = out_roready_1_38 & out_romask_184; // @[RegisterRouter.scala:87:24]
wire _out_T_2266 = out_f_roready_184; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_184 = out_wivalid_1_38 & out_wimask_184; // @[RegisterRouter.scala:87:24]
wire _out_T_2267 = out_f_wivalid_184; // @[RegisterRouter.scala:87:24]
wire out_f_woready_184 = out_woready_1_38 & out_womask_184; // @[RegisterRouter.scala:87:24]
wire _out_T_2268 = out_f_woready_184; // @[RegisterRouter.scala:87:24]
wire _out_T_2269 = ~out_rimask_184; // @[RegisterRouter.scala:87:24]
wire _out_T_2270 = ~out_wimask_184; // @[RegisterRouter.scala:87:24]
wire _out_T_2271 = ~out_romask_184; // @[RegisterRouter.scala:87:24]
wire _out_T_2272 = ~out_womask_184; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_145 = {abstractDataMem_30, _out_prepend_T_145}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_2273 = out_prepend_145; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_2274 = _out_T_2273; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_146 = _out_T_2274; // @[RegisterRouter.scala:87:24]
wire out_rimask_185 = |_out_rimask_T_185; // @[RegisterRouter.scala:87:24]
wire out_wimask_185 = &_out_wimask_T_185; // @[RegisterRouter.scala:87:24]
wire out_romask_185 = |_out_romask_T_185; // @[RegisterRouter.scala:87:24]
wire out_womask_185 = &_out_womask_T_185; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_185 = out_rivalid_1_39 & out_rimask_185; // @[RegisterRouter.scala:87:24]
wire _out_T_2276 = out_f_rivalid_185; // @[RegisterRouter.scala:87:24]
wire out_f_roready_185 = out_roready_1_39 & out_romask_185; // @[RegisterRouter.scala:87:24]
wire _out_T_2277 = out_f_roready_185; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_185 = out_wivalid_1_39 & out_wimask_185; // @[RegisterRouter.scala:87:24]
wire _out_T_2278 = out_f_wivalid_185; // @[RegisterRouter.scala:87:24]
wire out_f_woready_185 = out_woready_1_39 & out_womask_185; // @[RegisterRouter.scala:87:24]
wire _out_T_2279 = out_f_woready_185; // @[RegisterRouter.scala:87:24]
wire _out_T_2280 = ~out_rimask_185; // @[RegisterRouter.scala:87:24]
wire _out_T_2281 = ~out_wimask_185; // @[RegisterRouter.scala:87:24]
wire _out_T_2282 = ~out_romask_185; // @[RegisterRouter.scala:87:24]
wire _out_T_2283 = ~out_womask_185; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_146 = {abstractDataMem_31, _out_prepend_T_146}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_2284 = out_prepend_146; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_2285 = _out_T_2284; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_115 = _out_T_2285; // @[MuxLiteral.scala:49:48]
wire out_rimask_186 = |_out_rimask_T_186; // @[RegisterRouter.scala:87:24]
wire out_wimask_186 = &_out_wimask_T_186; // @[RegisterRouter.scala:87:24]
wire out_romask_186 = |_out_romask_T_186; // @[RegisterRouter.scala:87:24]
wire out_womask_186 = &_out_womask_T_186; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_186 = out_rivalid_1_40 & out_rimask_186; // @[RegisterRouter.scala:87:24]
wire _out_T_2287 = out_f_rivalid_186; // @[RegisterRouter.scala:87:24]
wire out_f_roready_186 = out_roready_1_40 & out_romask_186; // @[RegisterRouter.scala:87:24]
wire _out_T_2288 = out_f_roready_186; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_186 = out_wivalid_1_40 & out_wimask_186; // @[RegisterRouter.scala:87:24]
wire out_f_woready_186 = out_woready_1_40 & out_womask_186; // @[RegisterRouter.scala:87:24]
wire _out_T_2289 = ~out_rimask_186; // @[RegisterRouter.scala:87:24]
wire _out_T_2290 = ~out_wimask_186; // @[RegisterRouter.scala:87:24]
wire _out_T_2291 = ~out_romask_186; // @[RegisterRouter.scala:87:24]
wire _out_T_2292 = ~out_womask_186; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2294 = _out_T_2293; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_147 = _out_T_2294; // @[RegisterRouter.scala:87:24]
wire out_rimask_187 = |_out_rimask_T_187; // @[RegisterRouter.scala:87:24]
wire out_wimask_187 = &_out_wimask_T_187; // @[RegisterRouter.scala:87:24]
wire out_romask_187 = |_out_romask_T_187; // @[RegisterRouter.scala:87:24]
wire out_womask_187 = &_out_womask_T_187; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_187 = out_rivalid_1_41 & out_rimask_187; // @[RegisterRouter.scala:87:24]
wire _out_T_2296 = out_f_rivalid_187; // @[RegisterRouter.scala:87:24]
wire out_f_roready_187 = out_roready_1_41 & out_romask_187; // @[RegisterRouter.scala:87:24]
wire _out_T_2297 = out_f_roready_187; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_187 = out_wivalid_1_41 & out_wimask_187; // @[RegisterRouter.scala:87:24]
wire out_f_woready_187 = out_woready_1_41 & out_womask_187; // @[RegisterRouter.scala:87:24]
wire _out_T_2298 = ~out_rimask_187; // @[RegisterRouter.scala:87:24]
wire _out_T_2299 = ~out_wimask_187; // @[RegisterRouter.scala:87:24]
wire _out_T_2300 = ~out_romask_187; // @[RegisterRouter.scala:87:24]
wire _out_T_2301 = ~out_womask_187; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_147 = {hi_714, flags_0_go, _out_prepend_T_147}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_2302 = out_prepend_147; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_2303 = _out_T_2302; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_148 = _out_T_2303; // @[RegisterRouter.scala:87:24]
wire out_rimask_188 = |_out_rimask_T_188; // @[RegisterRouter.scala:87:24]
wire out_wimask_188 = &_out_wimask_T_188; // @[RegisterRouter.scala:87:24]
wire out_romask_188 = |_out_romask_T_188; // @[RegisterRouter.scala:87:24]
wire out_womask_188 = &_out_womask_T_188; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_188 = out_rivalid_1_42 & out_rimask_188; // @[RegisterRouter.scala:87:24]
wire _out_T_2305 = out_f_rivalid_188; // @[RegisterRouter.scala:87:24]
wire out_f_roready_188 = out_roready_1_42 & out_romask_188; // @[RegisterRouter.scala:87:24]
wire _out_T_2306 = out_f_roready_188; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_188 = out_wivalid_1_42 & out_wimask_188; // @[RegisterRouter.scala:87:24]
wire out_f_woready_188 = out_woready_1_42 & out_womask_188; // @[RegisterRouter.scala:87:24]
wire _out_T_2307 = ~out_rimask_188; // @[RegisterRouter.scala:87:24]
wire _out_T_2308 = ~out_wimask_188; // @[RegisterRouter.scala:87:24]
wire _out_T_2309 = ~out_romask_188; // @[RegisterRouter.scala:87:24]
wire _out_T_2310 = ~out_womask_188; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_148 = {hi_715, flags_0_go, _out_prepend_T_148}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_2311 = out_prepend_148; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_2312 = _out_T_2311; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_149 = _out_T_2312; // @[RegisterRouter.scala:87:24]
wire out_rimask_189 = |_out_rimask_T_189; // @[RegisterRouter.scala:87:24]
wire out_wimask_189 = &_out_wimask_T_189; // @[RegisterRouter.scala:87:24]
wire out_romask_189 = |_out_romask_T_189; // @[RegisterRouter.scala:87:24]
wire out_womask_189 = &_out_womask_T_189; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_189 = out_rivalid_1_43 & out_rimask_189; // @[RegisterRouter.scala:87:24]
wire _out_T_2314 = out_f_rivalid_189; // @[RegisterRouter.scala:87:24]
wire out_f_roready_189 = out_roready_1_43 & out_romask_189; // @[RegisterRouter.scala:87:24]
wire _out_T_2315 = out_f_roready_189; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_189 = out_wivalid_1_43 & out_wimask_189; // @[RegisterRouter.scala:87:24]
wire out_f_woready_189 = out_woready_1_43 & out_womask_189; // @[RegisterRouter.scala:87:24]
wire _out_T_2316 = ~out_rimask_189; // @[RegisterRouter.scala:87:24]
wire _out_T_2317 = ~out_wimask_189; // @[RegisterRouter.scala:87:24]
wire _out_T_2318 = ~out_romask_189; // @[RegisterRouter.scala:87:24]
wire _out_T_2319 = ~out_womask_189; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_149 = {hi_716, flags_0_go, _out_prepend_T_149}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_2320 = out_prepend_149; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_2321 = _out_T_2320; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_150 = _out_T_2321; // @[RegisterRouter.scala:87:24]
wire out_rimask_190 = |_out_rimask_T_190; // @[RegisterRouter.scala:87:24]
wire out_wimask_190 = &_out_wimask_T_190; // @[RegisterRouter.scala:87:24]
wire out_romask_190 = |_out_romask_T_190; // @[RegisterRouter.scala:87:24]
wire out_womask_190 = &_out_womask_T_190; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_190 = out_rivalid_1_44 & out_rimask_190; // @[RegisterRouter.scala:87:24]
wire _out_T_2323 = out_f_rivalid_190; // @[RegisterRouter.scala:87:24]
wire out_f_roready_190 = out_roready_1_44 & out_romask_190; // @[RegisterRouter.scala:87:24]
wire _out_T_2324 = out_f_roready_190; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_190 = out_wivalid_1_44 & out_wimask_190; // @[RegisterRouter.scala:87:24]
wire out_f_woready_190 = out_woready_1_44 & out_womask_190; // @[RegisterRouter.scala:87:24]
wire _out_T_2325 = ~out_rimask_190; // @[RegisterRouter.scala:87:24]
wire _out_T_2326 = ~out_wimask_190; // @[RegisterRouter.scala:87:24]
wire _out_T_2327 = ~out_romask_190; // @[RegisterRouter.scala:87:24]
wire _out_T_2328 = ~out_womask_190; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_150 = {hi_717, flags_0_go, _out_prepend_T_150}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_2329 = out_prepend_150; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_2330 = _out_T_2329; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_151 = _out_T_2330; // @[RegisterRouter.scala:87:24]
wire out_rimask_191 = |_out_rimask_T_191; // @[RegisterRouter.scala:87:24]
wire out_wimask_191 = &_out_wimask_T_191; // @[RegisterRouter.scala:87:24]
wire out_romask_191 = |_out_romask_T_191; // @[RegisterRouter.scala:87:24]
wire out_womask_191 = &_out_womask_T_191; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_191 = out_rivalid_1_45 & out_rimask_191; // @[RegisterRouter.scala:87:24]
wire _out_T_2332 = out_f_rivalid_191; // @[RegisterRouter.scala:87:24]
wire out_f_roready_191 = out_roready_1_45 & out_romask_191; // @[RegisterRouter.scala:87:24]
wire _out_T_2333 = out_f_roready_191; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_191 = out_wivalid_1_45 & out_wimask_191; // @[RegisterRouter.scala:87:24]
wire out_f_woready_191 = out_woready_1_45 & out_womask_191; // @[RegisterRouter.scala:87:24]
wire _out_T_2334 = ~out_rimask_191; // @[RegisterRouter.scala:87:24]
wire _out_T_2335 = ~out_wimask_191; // @[RegisterRouter.scala:87:24]
wire _out_T_2336 = ~out_romask_191; // @[RegisterRouter.scala:87:24]
wire _out_T_2337 = ~out_womask_191; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_151 = {hi_718, flags_0_go, _out_prepend_T_151}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_2338 = out_prepend_151; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_2339 = _out_T_2338; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_152 = _out_T_2339; // @[RegisterRouter.scala:87:24]
wire out_rimask_192 = |_out_rimask_T_192; // @[RegisterRouter.scala:87:24]
wire out_wimask_192 = &_out_wimask_T_192; // @[RegisterRouter.scala:87:24]
wire out_romask_192 = |_out_romask_T_192; // @[RegisterRouter.scala:87:24]
wire out_womask_192 = &_out_womask_T_192; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_192 = out_rivalid_1_46 & out_rimask_192; // @[RegisterRouter.scala:87:24]
wire _out_T_2341 = out_f_rivalid_192; // @[RegisterRouter.scala:87:24]
wire out_f_roready_192 = out_roready_1_46 & out_romask_192; // @[RegisterRouter.scala:87:24]
wire _out_T_2342 = out_f_roready_192; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_192 = out_wivalid_1_46 & out_wimask_192; // @[RegisterRouter.scala:87:24]
wire out_f_woready_192 = out_woready_1_46 & out_womask_192; // @[RegisterRouter.scala:87:24]
wire _out_T_2343 = ~out_rimask_192; // @[RegisterRouter.scala:87:24]
wire _out_T_2344 = ~out_wimask_192; // @[RegisterRouter.scala:87:24]
wire _out_T_2345 = ~out_romask_192; // @[RegisterRouter.scala:87:24]
wire _out_T_2346 = ~out_womask_192; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_152 = {hi_719, flags_0_go, _out_prepend_T_152}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_2347 = out_prepend_152; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_2348 = _out_T_2347; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_153 = _out_T_2348; // @[RegisterRouter.scala:87:24]
wire out_rimask_193 = |_out_rimask_T_193; // @[RegisterRouter.scala:87:24]
wire out_wimask_193 = &_out_wimask_T_193; // @[RegisterRouter.scala:87:24]
wire out_romask_193 = |_out_romask_T_193; // @[RegisterRouter.scala:87:24]
wire out_womask_193 = &_out_womask_T_193; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_193 = out_rivalid_1_47 & out_rimask_193; // @[RegisterRouter.scala:87:24]
wire _out_T_2350 = out_f_rivalid_193; // @[RegisterRouter.scala:87:24]
wire out_f_roready_193 = out_roready_1_47 & out_romask_193; // @[RegisterRouter.scala:87:24]
wire _out_T_2351 = out_f_roready_193; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_193 = out_wivalid_1_47 & out_wimask_193; // @[RegisterRouter.scala:87:24]
wire out_f_woready_193 = out_woready_1_47 & out_womask_193; // @[RegisterRouter.scala:87:24]
wire _out_T_2352 = ~out_rimask_193; // @[RegisterRouter.scala:87:24]
wire _out_T_2353 = ~out_wimask_193; // @[RegisterRouter.scala:87:24]
wire _out_T_2354 = ~out_romask_193; // @[RegisterRouter.scala:87:24]
wire _out_T_2355 = ~out_womask_193; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_153 = {hi_720, flags_0_go, _out_prepend_T_153}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_2356 = out_prepend_153; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_2357 = _out_T_2356; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_217 = _out_T_2357; // @[MuxLiteral.scala:49:48]
wire out_rimask_194 = |_out_rimask_T_194; // @[RegisterRouter.scala:87:24]
wire out_wimask_194 = &_out_wimask_T_194; // @[RegisterRouter.scala:87:24]
wire out_romask_194 = |_out_romask_T_194; // @[RegisterRouter.scala:87:24]
wire out_womask_194 = &_out_womask_T_194; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_194 = out_rivalid_1_48 & out_rimask_194; // @[RegisterRouter.scala:87:24]
wire _out_T_2359 = out_f_rivalid_194; // @[RegisterRouter.scala:87:24]
wire out_f_roready_194 = out_roready_1_48 & out_romask_194; // @[RegisterRouter.scala:87:24]
wire _out_T_2360 = out_f_roready_194; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_194 = out_wivalid_1_48 & out_wimask_194; // @[RegisterRouter.scala:87:24]
wire out_f_woready_194 = out_woready_1_48 & out_womask_194; // @[RegisterRouter.scala:87:24]
wire _out_T_2361 = ~out_rimask_194; // @[RegisterRouter.scala:87:24]
wire _out_T_2362 = ~out_wimask_194; // @[RegisterRouter.scala:87:24]
wire _out_T_2363 = ~out_romask_194; // @[RegisterRouter.scala:87:24]
wire _out_T_2364 = ~out_womask_194; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2366 = _out_T_2365; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_154 = _out_T_2366; // @[RegisterRouter.scala:87:24]
wire out_rimask_195 = |_out_rimask_T_195; // @[RegisterRouter.scala:87:24]
wire out_wimask_195 = &_out_wimask_T_195; // @[RegisterRouter.scala:87:24]
wire out_romask_195 = |_out_romask_T_195; // @[RegisterRouter.scala:87:24]
wire out_womask_195 = &_out_womask_T_195; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_195 = out_rivalid_1_49 & out_rimask_195; // @[RegisterRouter.scala:87:24]
wire _out_T_2368 = out_f_rivalid_195; // @[RegisterRouter.scala:87:24]
wire out_f_roready_195 = out_roready_1_49 & out_romask_195; // @[RegisterRouter.scala:87:24]
wire _out_T_2369 = out_f_roready_195; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_195 = out_wivalid_1_49 & out_wimask_195; // @[RegisterRouter.scala:87:24]
wire out_f_woready_195 = out_woready_1_49 & out_womask_195; // @[RegisterRouter.scala:87:24]
wire _out_T_2370 = ~out_rimask_195; // @[RegisterRouter.scala:87:24]
wire _out_T_2371 = ~out_wimask_195; // @[RegisterRouter.scala:87:24]
wire _out_T_2372 = ~out_romask_195; // @[RegisterRouter.scala:87:24]
wire _out_T_2373 = ~out_womask_195; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_154 = {hi_954, flags_0_go, _out_prepend_T_154}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_2374 = out_prepend_154; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_2375 = _out_T_2374; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_155 = _out_T_2375; // @[RegisterRouter.scala:87:24]
wire out_rimask_196 = |_out_rimask_T_196; // @[RegisterRouter.scala:87:24]
wire out_wimask_196 = &_out_wimask_T_196; // @[RegisterRouter.scala:87:24]
wire out_romask_196 = |_out_romask_T_196; // @[RegisterRouter.scala:87:24]
wire out_womask_196 = &_out_womask_T_196; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_196 = out_rivalid_1_50 & out_rimask_196; // @[RegisterRouter.scala:87:24]
wire _out_T_2377 = out_f_rivalid_196; // @[RegisterRouter.scala:87:24]
wire out_f_roready_196 = out_roready_1_50 & out_romask_196; // @[RegisterRouter.scala:87:24]
wire _out_T_2378 = out_f_roready_196; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_196 = out_wivalid_1_50 & out_wimask_196; // @[RegisterRouter.scala:87:24]
wire out_f_woready_196 = out_woready_1_50 & out_womask_196; // @[RegisterRouter.scala:87:24]
wire _out_T_2379 = ~out_rimask_196; // @[RegisterRouter.scala:87:24]
wire _out_T_2380 = ~out_wimask_196; // @[RegisterRouter.scala:87:24]
wire _out_T_2381 = ~out_romask_196; // @[RegisterRouter.scala:87:24]
wire _out_T_2382 = ~out_womask_196; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_155 = {hi_955, flags_0_go, _out_prepend_T_155}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_2383 = out_prepend_155; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_2384 = _out_T_2383; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_156 = _out_T_2384; // @[RegisterRouter.scala:87:24]
wire out_rimask_197 = |_out_rimask_T_197; // @[RegisterRouter.scala:87:24]
wire out_wimask_197 = &_out_wimask_T_197; // @[RegisterRouter.scala:87:24]
wire out_romask_197 = |_out_romask_T_197; // @[RegisterRouter.scala:87:24]
wire out_womask_197 = &_out_womask_T_197; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_197 = out_rivalid_1_51 & out_rimask_197; // @[RegisterRouter.scala:87:24]
wire _out_T_2386 = out_f_rivalid_197; // @[RegisterRouter.scala:87:24]
wire out_f_roready_197 = out_roready_1_51 & out_romask_197; // @[RegisterRouter.scala:87:24]
wire _out_T_2387 = out_f_roready_197; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_197 = out_wivalid_1_51 & out_wimask_197; // @[RegisterRouter.scala:87:24]
wire out_f_woready_197 = out_woready_1_51 & out_womask_197; // @[RegisterRouter.scala:87:24]
wire _out_T_2388 = ~out_rimask_197; // @[RegisterRouter.scala:87:24]
wire _out_T_2389 = ~out_wimask_197; // @[RegisterRouter.scala:87:24]
wire _out_T_2390 = ~out_romask_197; // @[RegisterRouter.scala:87:24]
wire _out_T_2391 = ~out_womask_197; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_156 = {hi_956, flags_0_go, _out_prepend_T_156}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_2392 = out_prepend_156; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_2393 = _out_T_2392; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_157 = _out_T_2393; // @[RegisterRouter.scala:87:24]
wire out_rimask_198 = |_out_rimask_T_198; // @[RegisterRouter.scala:87:24]
wire out_wimask_198 = &_out_wimask_T_198; // @[RegisterRouter.scala:87:24]
wire out_romask_198 = |_out_romask_T_198; // @[RegisterRouter.scala:87:24]
wire out_womask_198 = &_out_womask_T_198; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_198 = out_rivalid_1_52 & out_rimask_198; // @[RegisterRouter.scala:87:24]
wire _out_T_2395 = out_f_rivalid_198; // @[RegisterRouter.scala:87:24]
wire out_f_roready_198 = out_roready_1_52 & out_romask_198; // @[RegisterRouter.scala:87:24]
wire _out_T_2396 = out_f_roready_198; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_198 = out_wivalid_1_52 & out_wimask_198; // @[RegisterRouter.scala:87:24]
wire out_f_woready_198 = out_woready_1_52 & out_womask_198; // @[RegisterRouter.scala:87:24]
wire _out_T_2397 = ~out_rimask_198; // @[RegisterRouter.scala:87:24]
wire _out_T_2398 = ~out_wimask_198; // @[RegisterRouter.scala:87:24]
wire _out_T_2399 = ~out_romask_198; // @[RegisterRouter.scala:87:24]
wire _out_T_2400 = ~out_womask_198; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_157 = {hi_957, flags_0_go, _out_prepend_T_157}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_2401 = out_prepend_157; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_2402 = _out_T_2401; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_158 = _out_T_2402; // @[RegisterRouter.scala:87:24]
wire out_rimask_199 = |_out_rimask_T_199; // @[RegisterRouter.scala:87:24]
wire out_wimask_199 = &_out_wimask_T_199; // @[RegisterRouter.scala:87:24]
wire out_romask_199 = |_out_romask_T_199; // @[RegisterRouter.scala:87:24]
wire out_womask_199 = &_out_womask_T_199; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_199 = out_rivalid_1_53 & out_rimask_199; // @[RegisterRouter.scala:87:24]
wire _out_T_2404 = out_f_rivalid_199; // @[RegisterRouter.scala:87:24]
wire out_f_roready_199 = out_roready_1_53 & out_romask_199; // @[RegisterRouter.scala:87:24]
wire _out_T_2405 = out_f_roready_199; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_199 = out_wivalid_1_53 & out_wimask_199; // @[RegisterRouter.scala:87:24]
wire out_f_woready_199 = out_woready_1_53 & out_womask_199; // @[RegisterRouter.scala:87:24]
wire _out_T_2406 = ~out_rimask_199; // @[RegisterRouter.scala:87:24]
wire _out_T_2407 = ~out_wimask_199; // @[RegisterRouter.scala:87:24]
wire _out_T_2408 = ~out_romask_199; // @[RegisterRouter.scala:87:24]
wire _out_T_2409 = ~out_womask_199; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_158 = {hi_958, flags_0_go, _out_prepend_T_158}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_2410 = out_prepend_158; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_2411 = _out_T_2410; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_159 = _out_T_2411; // @[RegisterRouter.scala:87:24]
wire out_rimask_200 = |_out_rimask_T_200; // @[RegisterRouter.scala:87:24]
wire out_wimask_200 = &_out_wimask_T_200; // @[RegisterRouter.scala:87:24]
wire out_romask_200 = |_out_romask_T_200; // @[RegisterRouter.scala:87:24]
wire out_womask_200 = &_out_womask_T_200; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_200 = out_rivalid_1_54 & out_rimask_200; // @[RegisterRouter.scala:87:24]
wire _out_T_2413 = out_f_rivalid_200; // @[RegisterRouter.scala:87:24]
wire out_f_roready_200 = out_roready_1_54 & out_romask_200; // @[RegisterRouter.scala:87:24]
wire _out_T_2414 = out_f_roready_200; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_200 = out_wivalid_1_54 & out_wimask_200; // @[RegisterRouter.scala:87:24]
wire out_f_woready_200 = out_woready_1_54 & out_womask_200; // @[RegisterRouter.scala:87:24]
wire _out_T_2415 = ~out_rimask_200; // @[RegisterRouter.scala:87:24]
wire _out_T_2416 = ~out_wimask_200; // @[RegisterRouter.scala:87:24]
wire _out_T_2417 = ~out_romask_200; // @[RegisterRouter.scala:87:24]
wire _out_T_2418 = ~out_womask_200; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_159 = {hi_959, flags_0_go, _out_prepend_T_159}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_2419 = out_prepend_159; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_2420 = _out_T_2419; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_160 = _out_T_2420; // @[RegisterRouter.scala:87:24]
wire out_rimask_201 = |_out_rimask_T_201; // @[RegisterRouter.scala:87:24]
wire out_wimask_201 = &_out_wimask_T_201; // @[RegisterRouter.scala:87:24]
wire out_romask_201 = |_out_romask_T_201; // @[RegisterRouter.scala:87:24]
wire out_womask_201 = &_out_womask_T_201; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_201 = out_rivalid_1_55 & out_rimask_201; // @[RegisterRouter.scala:87:24]
wire _out_T_2422 = out_f_rivalid_201; // @[RegisterRouter.scala:87:24]
wire out_f_roready_201 = out_roready_1_55 & out_romask_201; // @[RegisterRouter.scala:87:24]
wire _out_T_2423 = out_f_roready_201; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_201 = out_wivalid_1_55 & out_wimask_201; // @[RegisterRouter.scala:87:24]
wire out_f_woready_201 = out_woready_1_55 & out_womask_201; // @[RegisterRouter.scala:87:24]
wire _out_T_2424 = ~out_rimask_201; // @[RegisterRouter.scala:87:24]
wire _out_T_2425 = ~out_wimask_201; // @[RegisterRouter.scala:87:24]
wire _out_T_2426 = ~out_romask_201; // @[RegisterRouter.scala:87:24]
wire _out_T_2427 = ~out_womask_201; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_160 = {hi_960, flags_0_go, _out_prepend_T_160}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_2428 = out_prepend_160; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_2429 = _out_T_2428; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_247 = _out_T_2429; // @[MuxLiteral.scala:49:48]
wire out_rimask_202 = |_out_rimask_T_202; // @[RegisterRouter.scala:87:24]
wire out_wimask_202 = &_out_wimask_T_202; // @[RegisterRouter.scala:87:24]
wire out_romask_202 = |_out_romask_T_202; // @[RegisterRouter.scala:87:24]
wire out_womask_202 = &_out_womask_T_202; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_202 = out_rivalid_1_56 & out_rimask_202; // @[RegisterRouter.scala:87:24]
wire _out_T_2431 = out_f_rivalid_202; // @[RegisterRouter.scala:87:24]
wire out_f_roready_202 = out_roready_1_56 & out_romask_202; // @[RegisterRouter.scala:87:24]
wire _out_T_2432 = out_f_roready_202; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_202 = out_wivalid_1_56 & out_wimask_202; // @[RegisterRouter.scala:87:24]
wire out_f_woready_202 = out_woready_1_56 & out_womask_202; // @[RegisterRouter.scala:87:24]
wire _out_T_2433 = ~out_rimask_202; // @[RegisterRouter.scala:87:24]
wire _out_T_2434 = ~out_wimask_202; // @[RegisterRouter.scala:87:24]
wire _out_T_2435 = ~out_romask_202; // @[RegisterRouter.scala:87:24]
wire _out_T_2436 = ~out_womask_202; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2438 = _out_T_2437; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_161 = _out_T_2438; // @[RegisterRouter.scala:87:24]
wire out_rimask_203 = |_out_rimask_T_203; // @[RegisterRouter.scala:87:24]
wire out_wimask_203 = &_out_wimask_T_203; // @[RegisterRouter.scala:87:24]
wire out_romask_203 = |_out_romask_T_203; // @[RegisterRouter.scala:87:24]
wire out_womask_203 = &_out_womask_T_203; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_203 = out_rivalid_1_57 & out_rimask_203; // @[RegisterRouter.scala:87:24]
wire _out_T_2440 = out_f_rivalid_203; // @[RegisterRouter.scala:87:24]
wire out_f_roready_203 = out_roready_1_57 & out_romask_203; // @[RegisterRouter.scala:87:24]
wire _out_T_2441 = out_f_roready_203; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_203 = out_wivalid_1_57 & out_wimask_203; // @[RegisterRouter.scala:87:24]
wire out_f_woready_203 = out_woready_1_57 & out_womask_203; // @[RegisterRouter.scala:87:24]
wire _out_T_2442 = ~out_rimask_203; // @[RegisterRouter.scala:87:24]
wire _out_T_2443 = ~out_wimask_203; // @[RegisterRouter.scala:87:24]
wire _out_T_2444 = ~out_romask_203; // @[RegisterRouter.scala:87:24]
wire _out_T_2445 = ~out_womask_203; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_161 = {hi_594, flags_0_go, _out_prepend_T_161}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_2446 = out_prepend_161; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_2447 = _out_T_2446; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_162 = _out_T_2447; // @[RegisterRouter.scala:87:24]
wire out_rimask_204 = |_out_rimask_T_204; // @[RegisterRouter.scala:87:24]
wire out_wimask_204 = &_out_wimask_T_204; // @[RegisterRouter.scala:87:24]
wire out_romask_204 = |_out_romask_T_204; // @[RegisterRouter.scala:87:24]
wire out_womask_204 = &_out_womask_T_204; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_204 = out_rivalid_1_58 & out_rimask_204; // @[RegisterRouter.scala:87:24]
wire _out_T_2449 = out_f_rivalid_204; // @[RegisterRouter.scala:87:24]
wire out_f_roready_204 = out_roready_1_58 & out_romask_204; // @[RegisterRouter.scala:87:24]
wire _out_T_2450 = out_f_roready_204; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_204 = out_wivalid_1_58 & out_wimask_204; // @[RegisterRouter.scala:87:24]
wire out_f_woready_204 = out_woready_1_58 & out_womask_204; // @[RegisterRouter.scala:87:24]
wire _out_T_2451 = ~out_rimask_204; // @[RegisterRouter.scala:87:24]
wire _out_T_2452 = ~out_wimask_204; // @[RegisterRouter.scala:87:24]
wire _out_T_2453 = ~out_romask_204; // @[RegisterRouter.scala:87:24]
wire _out_T_2454 = ~out_womask_204; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_162 = {hi_595, flags_0_go, _out_prepend_T_162}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_2455 = out_prepend_162; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_2456 = _out_T_2455; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_163 = _out_T_2456; // @[RegisterRouter.scala:87:24]
wire out_rimask_205 = |_out_rimask_T_205; // @[RegisterRouter.scala:87:24]
wire out_wimask_205 = &_out_wimask_T_205; // @[RegisterRouter.scala:87:24]
wire out_romask_205 = |_out_romask_T_205; // @[RegisterRouter.scala:87:24]
wire out_womask_205 = &_out_womask_T_205; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_205 = out_rivalid_1_59 & out_rimask_205; // @[RegisterRouter.scala:87:24]
wire _out_T_2458 = out_f_rivalid_205; // @[RegisterRouter.scala:87:24]
wire out_f_roready_205 = out_roready_1_59 & out_romask_205; // @[RegisterRouter.scala:87:24]
wire _out_T_2459 = out_f_roready_205; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_205 = out_wivalid_1_59 & out_wimask_205; // @[RegisterRouter.scala:87:24]
wire out_f_woready_205 = out_woready_1_59 & out_womask_205; // @[RegisterRouter.scala:87:24]
wire _out_T_2460 = ~out_rimask_205; // @[RegisterRouter.scala:87:24]
wire _out_T_2461 = ~out_wimask_205; // @[RegisterRouter.scala:87:24]
wire _out_T_2462 = ~out_romask_205; // @[RegisterRouter.scala:87:24]
wire _out_T_2463 = ~out_womask_205; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_163 = {hi_596, flags_0_go, _out_prepend_T_163}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_2464 = out_prepend_163; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_2465 = _out_T_2464; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_164 = _out_T_2465; // @[RegisterRouter.scala:87:24]
wire out_rimask_206 = |_out_rimask_T_206; // @[RegisterRouter.scala:87:24]
wire out_wimask_206 = &_out_wimask_T_206; // @[RegisterRouter.scala:87:24]
wire out_romask_206 = |_out_romask_T_206; // @[RegisterRouter.scala:87:24]
wire out_womask_206 = &_out_womask_T_206; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_206 = out_rivalid_1_60 & out_rimask_206; // @[RegisterRouter.scala:87:24]
wire _out_T_2467 = out_f_rivalid_206; // @[RegisterRouter.scala:87:24]
wire out_f_roready_206 = out_roready_1_60 & out_romask_206; // @[RegisterRouter.scala:87:24]
wire _out_T_2468 = out_f_roready_206; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_206 = out_wivalid_1_60 & out_wimask_206; // @[RegisterRouter.scala:87:24]
wire out_f_woready_206 = out_woready_1_60 & out_womask_206; // @[RegisterRouter.scala:87:24]
wire _out_T_2469 = ~out_rimask_206; // @[RegisterRouter.scala:87:24]
wire _out_T_2470 = ~out_wimask_206; // @[RegisterRouter.scala:87:24]
wire _out_T_2471 = ~out_romask_206; // @[RegisterRouter.scala:87:24]
wire _out_T_2472 = ~out_womask_206; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_164 = {hi_597, flags_0_go, _out_prepend_T_164}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_2473 = out_prepend_164; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_2474 = _out_T_2473; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_165 = _out_T_2474; // @[RegisterRouter.scala:87:24]
wire out_rimask_207 = |_out_rimask_T_207; // @[RegisterRouter.scala:87:24]
wire out_wimask_207 = &_out_wimask_T_207; // @[RegisterRouter.scala:87:24]
wire out_romask_207 = |_out_romask_T_207; // @[RegisterRouter.scala:87:24]
wire out_womask_207 = &_out_womask_T_207; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_207 = out_rivalid_1_61 & out_rimask_207; // @[RegisterRouter.scala:87:24]
wire _out_T_2476 = out_f_rivalid_207; // @[RegisterRouter.scala:87:24]
wire out_f_roready_207 = out_roready_1_61 & out_romask_207; // @[RegisterRouter.scala:87:24]
wire _out_T_2477 = out_f_roready_207; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_207 = out_wivalid_1_61 & out_wimask_207; // @[RegisterRouter.scala:87:24]
wire out_f_woready_207 = out_woready_1_61 & out_womask_207; // @[RegisterRouter.scala:87:24]
wire _out_T_2478 = ~out_rimask_207; // @[RegisterRouter.scala:87:24]
wire _out_T_2479 = ~out_wimask_207; // @[RegisterRouter.scala:87:24]
wire _out_T_2480 = ~out_romask_207; // @[RegisterRouter.scala:87:24]
wire _out_T_2481 = ~out_womask_207; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_165 = {hi_598, flags_0_go, _out_prepend_T_165}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_2482 = out_prepend_165; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_2483 = _out_T_2482; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_166 = _out_T_2483; // @[RegisterRouter.scala:87:24]
wire out_rimask_208 = |_out_rimask_T_208; // @[RegisterRouter.scala:87:24]
wire out_wimask_208 = &_out_wimask_T_208; // @[RegisterRouter.scala:87:24]
wire out_romask_208 = |_out_romask_T_208; // @[RegisterRouter.scala:87:24]
wire out_womask_208 = &_out_womask_T_208; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_208 = out_rivalid_1_62 & out_rimask_208; // @[RegisterRouter.scala:87:24]
wire _out_T_2485 = out_f_rivalid_208; // @[RegisterRouter.scala:87:24]
wire out_f_roready_208 = out_roready_1_62 & out_romask_208; // @[RegisterRouter.scala:87:24]
wire _out_T_2486 = out_f_roready_208; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_208 = out_wivalid_1_62 & out_wimask_208; // @[RegisterRouter.scala:87:24]
wire out_f_woready_208 = out_woready_1_62 & out_womask_208; // @[RegisterRouter.scala:87:24]
wire _out_T_2487 = ~out_rimask_208; // @[RegisterRouter.scala:87:24]
wire _out_T_2488 = ~out_wimask_208; // @[RegisterRouter.scala:87:24]
wire _out_T_2489 = ~out_romask_208; // @[RegisterRouter.scala:87:24]
wire _out_T_2490 = ~out_womask_208; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_166 = {hi_599, flags_0_go, _out_prepend_T_166}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_2491 = out_prepend_166; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_2492 = _out_T_2491; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_167 = _out_T_2492; // @[RegisterRouter.scala:87:24]
wire out_rimask_209 = |_out_rimask_T_209; // @[RegisterRouter.scala:87:24]
wire out_wimask_209 = &_out_wimask_T_209; // @[RegisterRouter.scala:87:24]
wire out_romask_209 = |_out_romask_T_209; // @[RegisterRouter.scala:87:24]
wire out_womask_209 = &_out_womask_T_209; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_209 = out_rivalid_1_63 & out_rimask_209; // @[RegisterRouter.scala:87:24]
wire _out_T_2494 = out_f_rivalid_209; // @[RegisterRouter.scala:87:24]
wire out_f_roready_209 = out_roready_1_63 & out_romask_209; // @[RegisterRouter.scala:87:24]
wire _out_T_2495 = out_f_roready_209; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_209 = out_wivalid_1_63 & out_wimask_209; // @[RegisterRouter.scala:87:24]
wire out_f_woready_209 = out_woready_1_63 & out_womask_209; // @[RegisterRouter.scala:87:24]
wire _out_T_2496 = ~out_rimask_209; // @[RegisterRouter.scala:87:24]
wire _out_T_2497 = ~out_wimask_209; // @[RegisterRouter.scala:87:24]
wire _out_T_2498 = ~out_romask_209; // @[RegisterRouter.scala:87:24]
wire _out_T_2499 = ~out_womask_209; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_167 = {hi_600, flags_0_go, _out_prepend_T_167}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_2500 = out_prepend_167; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_2501 = _out_T_2500; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_202 = _out_T_2501; // @[MuxLiteral.scala:49:48]
wire out_rimask_210 = |_out_rimask_T_210; // @[RegisterRouter.scala:87:24]
wire out_wimask_210 = &_out_wimask_T_210; // @[RegisterRouter.scala:87:24]
wire out_romask_210 = |_out_romask_T_210; // @[RegisterRouter.scala:87:24]
wire out_womask_210 = &_out_womask_T_210; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_210 = out_rivalid_1_64 & out_rimask_210; // @[RegisterRouter.scala:87:24]
wire _out_T_2503 = out_f_rivalid_210; // @[RegisterRouter.scala:87:24]
wire out_f_roready_210 = out_roready_1_64 & out_romask_210; // @[RegisterRouter.scala:87:24]
wire _out_T_2504 = out_f_roready_210; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_210 = out_wivalid_1_64 & out_wimask_210; // @[RegisterRouter.scala:87:24]
wire out_f_woready_210 = out_woready_1_64 & out_womask_210; // @[RegisterRouter.scala:87:24]
wire _out_T_2505 = ~out_rimask_210; // @[RegisterRouter.scala:87:24]
wire _out_T_2506 = ~out_wimask_210; // @[RegisterRouter.scala:87:24]
wire _out_T_2507 = ~out_romask_210; // @[RegisterRouter.scala:87:24]
wire _out_T_2508 = ~out_womask_210; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2510 = _out_T_2509; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_168 = _out_T_2510; // @[RegisterRouter.scala:87:24]
wire out_rimask_211 = |_out_rimask_T_211; // @[RegisterRouter.scala:87:24]
wire out_wimask_211 = &_out_wimask_T_211; // @[RegisterRouter.scala:87:24]
wire out_romask_211 = |_out_romask_T_211; // @[RegisterRouter.scala:87:24]
wire out_womask_211 = &_out_womask_T_211; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_211 = out_rivalid_1_65 & out_rimask_211; // @[RegisterRouter.scala:87:24]
wire _out_T_2512 = out_f_rivalid_211; // @[RegisterRouter.scala:87:24]
wire out_f_roready_211 = out_roready_1_65 & out_romask_211; // @[RegisterRouter.scala:87:24]
wire _out_T_2513 = out_f_roready_211; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_211 = out_wivalid_1_65 & out_wimask_211; // @[RegisterRouter.scala:87:24]
wire out_f_woready_211 = out_woready_1_65 & out_womask_211; // @[RegisterRouter.scala:87:24]
wire _out_T_2514 = ~out_rimask_211; // @[RegisterRouter.scala:87:24]
wire _out_T_2515 = ~out_wimask_211; // @[RegisterRouter.scala:87:24]
wire _out_T_2516 = ~out_romask_211; // @[RegisterRouter.scala:87:24]
wire _out_T_2517 = ~out_womask_211; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_168 = {hi_114, flags_0_go, _out_prepend_T_168}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_2518 = out_prepend_168; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_2519 = _out_T_2518; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_169 = _out_T_2519; // @[RegisterRouter.scala:87:24]
wire out_rimask_212 = |_out_rimask_T_212; // @[RegisterRouter.scala:87:24]
wire out_wimask_212 = &_out_wimask_T_212; // @[RegisterRouter.scala:87:24]
wire out_romask_212 = |_out_romask_T_212; // @[RegisterRouter.scala:87:24]
wire out_womask_212 = &_out_womask_T_212; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_212 = out_rivalid_1_66 & out_rimask_212; // @[RegisterRouter.scala:87:24]
wire _out_T_2521 = out_f_rivalid_212; // @[RegisterRouter.scala:87:24]
wire out_f_roready_212 = out_roready_1_66 & out_romask_212; // @[RegisterRouter.scala:87:24]
wire _out_T_2522 = out_f_roready_212; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_212 = out_wivalid_1_66 & out_wimask_212; // @[RegisterRouter.scala:87:24]
wire out_f_woready_212 = out_woready_1_66 & out_womask_212; // @[RegisterRouter.scala:87:24]
wire _out_T_2523 = ~out_rimask_212; // @[RegisterRouter.scala:87:24]
wire _out_T_2524 = ~out_wimask_212; // @[RegisterRouter.scala:87:24]
wire _out_T_2525 = ~out_romask_212; // @[RegisterRouter.scala:87:24]
wire _out_T_2526 = ~out_womask_212; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_169 = {hi_115, flags_0_go, _out_prepend_T_169}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_2527 = out_prepend_169; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_2528 = _out_T_2527; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_170 = _out_T_2528; // @[RegisterRouter.scala:87:24]
wire out_rimask_213 = |_out_rimask_T_213; // @[RegisterRouter.scala:87:24]
wire out_wimask_213 = &_out_wimask_T_213; // @[RegisterRouter.scala:87:24]
wire out_romask_213 = |_out_romask_T_213; // @[RegisterRouter.scala:87:24]
wire out_womask_213 = &_out_womask_T_213; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_213 = out_rivalid_1_67 & out_rimask_213; // @[RegisterRouter.scala:87:24]
wire _out_T_2530 = out_f_rivalid_213; // @[RegisterRouter.scala:87:24]
wire out_f_roready_213 = out_roready_1_67 & out_romask_213; // @[RegisterRouter.scala:87:24]
wire _out_T_2531 = out_f_roready_213; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_213 = out_wivalid_1_67 & out_wimask_213; // @[RegisterRouter.scala:87:24]
wire out_f_woready_213 = out_woready_1_67 & out_womask_213; // @[RegisterRouter.scala:87:24]
wire _out_T_2532 = ~out_rimask_213; // @[RegisterRouter.scala:87:24]
wire _out_T_2533 = ~out_wimask_213; // @[RegisterRouter.scala:87:24]
wire _out_T_2534 = ~out_romask_213; // @[RegisterRouter.scala:87:24]
wire _out_T_2535 = ~out_womask_213; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_170 = {hi_116, flags_0_go, _out_prepend_T_170}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_2536 = out_prepend_170; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_2537 = _out_T_2536; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_171 = _out_T_2537; // @[RegisterRouter.scala:87:24]
wire out_rimask_214 = |_out_rimask_T_214; // @[RegisterRouter.scala:87:24]
wire out_wimask_214 = &_out_wimask_T_214; // @[RegisterRouter.scala:87:24]
wire out_romask_214 = |_out_romask_T_214; // @[RegisterRouter.scala:87:24]
wire out_womask_214 = &_out_womask_T_214; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_214 = out_rivalid_1_68 & out_rimask_214; // @[RegisterRouter.scala:87:24]
wire _out_T_2539 = out_f_rivalid_214; // @[RegisterRouter.scala:87:24]
wire out_f_roready_214 = out_roready_1_68 & out_romask_214; // @[RegisterRouter.scala:87:24]
wire _out_T_2540 = out_f_roready_214; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_214 = out_wivalid_1_68 & out_wimask_214; // @[RegisterRouter.scala:87:24]
wire out_f_woready_214 = out_woready_1_68 & out_womask_214; // @[RegisterRouter.scala:87:24]
wire _out_T_2541 = ~out_rimask_214; // @[RegisterRouter.scala:87:24]
wire _out_T_2542 = ~out_wimask_214; // @[RegisterRouter.scala:87:24]
wire _out_T_2543 = ~out_romask_214; // @[RegisterRouter.scala:87:24]
wire _out_T_2544 = ~out_womask_214; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_171 = {hi_117, flags_0_go, _out_prepend_T_171}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_2545 = out_prepend_171; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_2546 = _out_T_2545; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_172 = _out_T_2546; // @[RegisterRouter.scala:87:24]
wire out_rimask_215 = |_out_rimask_T_215; // @[RegisterRouter.scala:87:24]
wire out_wimask_215 = &_out_wimask_T_215; // @[RegisterRouter.scala:87:24]
wire out_romask_215 = |_out_romask_T_215; // @[RegisterRouter.scala:87:24]
wire out_womask_215 = &_out_womask_T_215; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_215 = out_rivalid_1_69 & out_rimask_215; // @[RegisterRouter.scala:87:24]
wire _out_T_2548 = out_f_rivalid_215; // @[RegisterRouter.scala:87:24]
wire out_f_roready_215 = out_roready_1_69 & out_romask_215; // @[RegisterRouter.scala:87:24]
wire _out_T_2549 = out_f_roready_215; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_215 = out_wivalid_1_69 & out_wimask_215; // @[RegisterRouter.scala:87:24]
wire out_f_woready_215 = out_woready_1_69 & out_womask_215; // @[RegisterRouter.scala:87:24]
wire _out_T_2550 = ~out_rimask_215; // @[RegisterRouter.scala:87:24]
wire _out_T_2551 = ~out_wimask_215; // @[RegisterRouter.scala:87:24]
wire _out_T_2552 = ~out_romask_215; // @[RegisterRouter.scala:87:24]
wire _out_T_2553 = ~out_womask_215; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_172 = {hi_118, flags_0_go, _out_prepend_T_172}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_2554 = out_prepend_172; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_2555 = _out_T_2554; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_173 = _out_T_2555; // @[RegisterRouter.scala:87:24]
wire out_rimask_216 = |_out_rimask_T_216; // @[RegisterRouter.scala:87:24]
wire out_wimask_216 = &_out_wimask_T_216; // @[RegisterRouter.scala:87:24]
wire out_romask_216 = |_out_romask_T_216; // @[RegisterRouter.scala:87:24]
wire out_womask_216 = &_out_womask_T_216; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_216 = out_rivalid_1_70 & out_rimask_216; // @[RegisterRouter.scala:87:24]
wire _out_T_2557 = out_f_rivalid_216; // @[RegisterRouter.scala:87:24]
wire out_f_roready_216 = out_roready_1_70 & out_romask_216; // @[RegisterRouter.scala:87:24]
wire _out_T_2558 = out_f_roready_216; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_216 = out_wivalid_1_70 & out_wimask_216; // @[RegisterRouter.scala:87:24]
wire out_f_woready_216 = out_woready_1_70 & out_womask_216; // @[RegisterRouter.scala:87:24]
wire _out_T_2559 = ~out_rimask_216; // @[RegisterRouter.scala:87:24]
wire _out_T_2560 = ~out_wimask_216; // @[RegisterRouter.scala:87:24]
wire _out_T_2561 = ~out_romask_216; // @[RegisterRouter.scala:87:24]
wire _out_T_2562 = ~out_womask_216; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_173 = {hi_119, flags_0_go, _out_prepend_T_173}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_2563 = out_prepend_173; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_2564 = _out_T_2563; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_174 = _out_T_2564; // @[RegisterRouter.scala:87:24]
wire out_rimask_217 = |_out_rimask_T_217; // @[RegisterRouter.scala:87:24]
wire out_wimask_217 = &_out_wimask_T_217; // @[RegisterRouter.scala:87:24]
wire out_romask_217 = |_out_romask_T_217; // @[RegisterRouter.scala:87:24]
wire out_womask_217 = &_out_womask_T_217; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_217 = out_rivalid_1_71 & out_rimask_217; // @[RegisterRouter.scala:87:24]
wire _out_T_2566 = out_f_rivalid_217; // @[RegisterRouter.scala:87:24]
wire out_f_roready_217 = out_roready_1_71 & out_romask_217; // @[RegisterRouter.scala:87:24]
wire _out_T_2567 = out_f_roready_217; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_217 = out_wivalid_1_71 & out_wimask_217; // @[RegisterRouter.scala:87:24]
wire out_f_woready_217 = out_woready_1_71 & out_womask_217; // @[RegisterRouter.scala:87:24]
wire _out_T_2568 = ~out_rimask_217; // @[RegisterRouter.scala:87:24]
wire _out_T_2569 = ~out_wimask_217; // @[RegisterRouter.scala:87:24]
wire _out_T_2570 = ~out_romask_217; // @[RegisterRouter.scala:87:24]
wire _out_T_2571 = ~out_womask_217; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_174 = {hi_120, flags_0_go, _out_prepend_T_174}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_2572 = out_prepend_174; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_2573 = _out_T_2572; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_142 = _out_T_2573; // @[MuxLiteral.scala:49:48]
wire out_rimask_218 = |_out_rimask_T_218; // @[RegisterRouter.scala:87:24]
wire out_wimask_218 = &_out_wimask_T_218; // @[RegisterRouter.scala:87:24]
wire out_romask_218 = |_out_romask_T_218; // @[RegisterRouter.scala:87:24]
wire out_womask_218 = &_out_womask_T_218; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_218 = out_rivalid_1_72 & out_rimask_218; // @[RegisterRouter.scala:87:24]
wire _out_T_2575 = out_f_rivalid_218; // @[RegisterRouter.scala:87:24]
wire out_f_roready_218 = out_roready_1_72 & out_romask_218; // @[RegisterRouter.scala:87:24]
wire _out_T_2576 = out_f_roready_218; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_218 = out_wivalid_1_72 & out_wimask_218; // @[RegisterRouter.scala:87:24]
wire out_f_woready_218 = out_woready_1_72 & out_womask_218; // @[RegisterRouter.scala:87:24]
wire _out_T_2577 = ~out_rimask_218; // @[RegisterRouter.scala:87:24]
wire _out_T_2578 = ~out_wimask_218; // @[RegisterRouter.scala:87:24]
wire _out_T_2579 = ~out_romask_218; // @[RegisterRouter.scala:87:24]
wire _out_T_2580 = ~out_womask_218; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2582 = _out_T_2581; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_175 = _out_T_2582; // @[RegisterRouter.scala:87:24]
wire out_rimask_219 = |_out_rimask_T_219; // @[RegisterRouter.scala:87:24]
wire out_wimask_219 = &_out_wimask_T_219; // @[RegisterRouter.scala:87:24]
wire out_romask_219 = |_out_romask_T_219; // @[RegisterRouter.scala:87:24]
wire out_womask_219 = &_out_womask_T_219; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_219 = out_rivalid_1_73 & out_rimask_219; // @[RegisterRouter.scala:87:24]
wire _out_T_2584 = out_f_rivalid_219; // @[RegisterRouter.scala:87:24]
wire out_f_roready_219 = out_roready_1_73 & out_romask_219; // @[RegisterRouter.scala:87:24]
wire _out_T_2585 = out_f_roready_219; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_219 = out_wivalid_1_73 & out_wimask_219; // @[RegisterRouter.scala:87:24]
wire out_f_woready_219 = out_woready_1_73 & out_womask_219; // @[RegisterRouter.scala:87:24]
wire _out_T_2586 = ~out_rimask_219; // @[RegisterRouter.scala:87:24]
wire _out_T_2587 = ~out_wimask_219; // @[RegisterRouter.scala:87:24]
wire _out_T_2588 = ~out_romask_219; // @[RegisterRouter.scala:87:24]
wire _out_T_2589 = ~out_womask_219; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_175 = {hi_202, flags_0_go, _out_prepend_T_175}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_2590 = out_prepend_175; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_2591 = _out_T_2590; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_176 = _out_T_2591; // @[RegisterRouter.scala:87:24]
wire out_rimask_220 = |_out_rimask_T_220; // @[RegisterRouter.scala:87:24]
wire out_wimask_220 = &_out_wimask_T_220; // @[RegisterRouter.scala:87:24]
wire out_romask_220 = |_out_romask_T_220; // @[RegisterRouter.scala:87:24]
wire out_womask_220 = &_out_womask_T_220; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_220 = out_rivalid_1_74 & out_rimask_220; // @[RegisterRouter.scala:87:24]
wire _out_T_2593 = out_f_rivalid_220; // @[RegisterRouter.scala:87:24]
wire out_f_roready_220 = out_roready_1_74 & out_romask_220; // @[RegisterRouter.scala:87:24]
wire _out_T_2594 = out_f_roready_220; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_220 = out_wivalid_1_74 & out_wimask_220; // @[RegisterRouter.scala:87:24]
wire out_f_woready_220 = out_woready_1_74 & out_womask_220; // @[RegisterRouter.scala:87:24]
wire _out_T_2595 = ~out_rimask_220; // @[RegisterRouter.scala:87:24]
wire _out_T_2596 = ~out_wimask_220; // @[RegisterRouter.scala:87:24]
wire _out_T_2597 = ~out_romask_220; // @[RegisterRouter.scala:87:24]
wire _out_T_2598 = ~out_womask_220; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_176 = {hi_203, flags_0_go, _out_prepend_T_176}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_2599 = out_prepend_176; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_2600 = _out_T_2599; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_177 = _out_T_2600; // @[RegisterRouter.scala:87:24]
wire out_rimask_221 = |_out_rimask_T_221; // @[RegisterRouter.scala:87:24]
wire out_wimask_221 = &_out_wimask_T_221; // @[RegisterRouter.scala:87:24]
wire out_romask_221 = |_out_romask_T_221; // @[RegisterRouter.scala:87:24]
wire out_womask_221 = &_out_womask_T_221; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_221 = out_rivalid_1_75 & out_rimask_221; // @[RegisterRouter.scala:87:24]
wire _out_T_2602 = out_f_rivalid_221; // @[RegisterRouter.scala:87:24]
wire out_f_roready_221 = out_roready_1_75 & out_romask_221; // @[RegisterRouter.scala:87:24]
wire _out_T_2603 = out_f_roready_221; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_221 = out_wivalid_1_75 & out_wimask_221; // @[RegisterRouter.scala:87:24]
wire out_f_woready_221 = out_woready_1_75 & out_womask_221; // @[RegisterRouter.scala:87:24]
wire _out_T_2604 = ~out_rimask_221; // @[RegisterRouter.scala:87:24]
wire _out_T_2605 = ~out_wimask_221; // @[RegisterRouter.scala:87:24]
wire _out_T_2606 = ~out_romask_221; // @[RegisterRouter.scala:87:24]
wire _out_T_2607 = ~out_womask_221; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_177 = {hi_204, flags_0_go, _out_prepend_T_177}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_2608 = out_prepend_177; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_2609 = _out_T_2608; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_178 = _out_T_2609; // @[RegisterRouter.scala:87:24]
wire out_rimask_222 = |_out_rimask_T_222; // @[RegisterRouter.scala:87:24]
wire out_wimask_222 = &_out_wimask_T_222; // @[RegisterRouter.scala:87:24]
wire out_romask_222 = |_out_romask_T_222; // @[RegisterRouter.scala:87:24]
wire out_womask_222 = &_out_womask_T_222; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_222 = out_rivalid_1_76 & out_rimask_222; // @[RegisterRouter.scala:87:24]
wire _out_T_2611 = out_f_rivalid_222; // @[RegisterRouter.scala:87:24]
wire out_f_roready_222 = out_roready_1_76 & out_romask_222; // @[RegisterRouter.scala:87:24]
wire _out_T_2612 = out_f_roready_222; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_222 = out_wivalid_1_76 & out_wimask_222; // @[RegisterRouter.scala:87:24]
wire out_f_woready_222 = out_woready_1_76 & out_womask_222; // @[RegisterRouter.scala:87:24]
wire _out_T_2613 = ~out_rimask_222; // @[RegisterRouter.scala:87:24]
wire _out_T_2614 = ~out_wimask_222; // @[RegisterRouter.scala:87:24]
wire _out_T_2615 = ~out_romask_222; // @[RegisterRouter.scala:87:24]
wire _out_T_2616 = ~out_womask_222; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_178 = {hi_205, flags_0_go, _out_prepend_T_178}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_2617 = out_prepend_178; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_2618 = _out_T_2617; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_179 = _out_T_2618; // @[RegisterRouter.scala:87:24]
wire out_rimask_223 = |_out_rimask_T_223; // @[RegisterRouter.scala:87:24]
wire out_wimask_223 = &_out_wimask_T_223; // @[RegisterRouter.scala:87:24]
wire out_romask_223 = |_out_romask_T_223; // @[RegisterRouter.scala:87:24]
wire out_womask_223 = &_out_womask_T_223; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_223 = out_rivalid_1_77 & out_rimask_223; // @[RegisterRouter.scala:87:24]
wire _out_T_2620 = out_f_rivalid_223; // @[RegisterRouter.scala:87:24]
wire out_f_roready_223 = out_roready_1_77 & out_romask_223; // @[RegisterRouter.scala:87:24]
wire _out_T_2621 = out_f_roready_223; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_223 = out_wivalid_1_77 & out_wimask_223; // @[RegisterRouter.scala:87:24]
wire out_f_woready_223 = out_woready_1_77 & out_womask_223; // @[RegisterRouter.scala:87:24]
wire _out_T_2622 = ~out_rimask_223; // @[RegisterRouter.scala:87:24]
wire _out_T_2623 = ~out_wimask_223; // @[RegisterRouter.scala:87:24]
wire _out_T_2624 = ~out_romask_223; // @[RegisterRouter.scala:87:24]
wire _out_T_2625 = ~out_womask_223; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_179 = {hi_206, flags_0_go, _out_prepend_T_179}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_2626 = out_prepend_179; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_2627 = _out_T_2626; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_180 = _out_T_2627; // @[RegisterRouter.scala:87:24]
wire out_rimask_224 = |_out_rimask_T_224; // @[RegisterRouter.scala:87:24]
wire out_wimask_224 = &_out_wimask_T_224; // @[RegisterRouter.scala:87:24]
wire out_romask_224 = |_out_romask_T_224; // @[RegisterRouter.scala:87:24]
wire out_womask_224 = &_out_womask_T_224; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_224 = out_rivalid_1_78 & out_rimask_224; // @[RegisterRouter.scala:87:24]
wire _out_T_2629 = out_f_rivalid_224; // @[RegisterRouter.scala:87:24]
wire out_f_roready_224 = out_roready_1_78 & out_romask_224; // @[RegisterRouter.scala:87:24]
wire _out_T_2630 = out_f_roready_224; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_224 = out_wivalid_1_78 & out_wimask_224; // @[RegisterRouter.scala:87:24]
wire out_f_woready_224 = out_woready_1_78 & out_womask_224; // @[RegisterRouter.scala:87:24]
wire _out_T_2631 = ~out_rimask_224; // @[RegisterRouter.scala:87:24]
wire _out_T_2632 = ~out_wimask_224; // @[RegisterRouter.scala:87:24]
wire _out_T_2633 = ~out_romask_224; // @[RegisterRouter.scala:87:24]
wire _out_T_2634 = ~out_womask_224; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_180 = {hi_207, flags_0_go, _out_prepend_T_180}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_2635 = out_prepend_180; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_2636 = _out_T_2635; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_181 = _out_T_2636; // @[RegisterRouter.scala:87:24]
wire out_rimask_225 = |_out_rimask_T_225; // @[RegisterRouter.scala:87:24]
wire out_wimask_225 = &_out_wimask_T_225; // @[RegisterRouter.scala:87:24]
wire out_romask_225 = |_out_romask_T_225; // @[RegisterRouter.scala:87:24]
wire out_womask_225 = &_out_womask_T_225; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_225 = out_rivalid_1_79 & out_rimask_225; // @[RegisterRouter.scala:87:24]
wire _out_T_2638 = out_f_rivalid_225; // @[RegisterRouter.scala:87:24]
wire out_f_roready_225 = out_roready_1_79 & out_romask_225; // @[RegisterRouter.scala:87:24]
wire _out_T_2639 = out_f_roready_225; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_225 = out_wivalid_1_79 & out_wimask_225; // @[RegisterRouter.scala:87:24]
wire out_f_woready_225 = out_woready_1_79 & out_womask_225; // @[RegisterRouter.scala:87:24]
wire _out_T_2640 = ~out_rimask_225; // @[RegisterRouter.scala:87:24]
wire _out_T_2641 = ~out_wimask_225; // @[RegisterRouter.scala:87:24]
wire _out_T_2642 = ~out_romask_225; // @[RegisterRouter.scala:87:24]
wire _out_T_2643 = ~out_womask_225; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_181 = {hi_208, flags_0_go, _out_prepend_T_181}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_2644 = out_prepend_181; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_2645 = _out_T_2644; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_153 = _out_T_2645; // @[MuxLiteral.scala:49:48]
wire out_rimask_226 = |_out_rimask_T_226; // @[RegisterRouter.scala:87:24]
wire out_wimask_226 = &_out_wimask_T_226; // @[RegisterRouter.scala:87:24]
wire out_romask_226 = |_out_romask_T_226; // @[RegisterRouter.scala:87:24]
wire out_womask_226 = &_out_womask_T_226; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_226 = out_rivalid_1_80 & out_rimask_226; // @[RegisterRouter.scala:87:24]
wire _out_T_2647 = out_f_rivalid_226; // @[RegisterRouter.scala:87:24]
wire out_f_roready_226 = out_roready_1_80 & out_romask_226; // @[RegisterRouter.scala:87:24]
wire _out_T_2648 = out_f_roready_226; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_226 = out_wivalid_1_80 & out_wimask_226; // @[RegisterRouter.scala:87:24]
wire out_f_woready_226 = out_woready_1_80 & out_womask_226; // @[RegisterRouter.scala:87:24]
wire _out_T_2649 = ~out_rimask_226; // @[RegisterRouter.scala:87:24]
wire _out_T_2650 = ~out_wimask_226; // @[RegisterRouter.scala:87:24]
wire _out_T_2651 = ~out_romask_226; // @[RegisterRouter.scala:87:24]
wire _out_T_2652 = ~out_womask_226; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2654 = _out_T_2653; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_182 = _out_T_2654; // @[RegisterRouter.scala:87:24]
wire out_rimask_227 = |_out_rimask_T_227; // @[RegisterRouter.scala:87:24]
wire out_wimask_227 = &_out_wimask_T_227; // @[RegisterRouter.scala:87:24]
wire out_romask_227 = |_out_romask_T_227; // @[RegisterRouter.scala:87:24]
wire out_womask_227 = &_out_womask_T_227; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_227 = out_rivalid_1_81 & out_rimask_227; // @[RegisterRouter.scala:87:24]
wire _out_T_2656 = out_f_rivalid_227; // @[RegisterRouter.scala:87:24]
wire out_f_roready_227 = out_roready_1_81 & out_romask_227; // @[RegisterRouter.scala:87:24]
wire _out_T_2657 = out_f_roready_227; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_227 = out_wivalid_1_81 & out_wimask_227; // @[RegisterRouter.scala:87:24]
wire out_f_woready_227 = out_woready_1_81 & out_womask_227; // @[RegisterRouter.scala:87:24]
wire _out_T_2658 = ~out_rimask_227; // @[RegisterRouter.scala:87:24]
wire _out_T_2659 = ~out_wimask_227; // @[RegisterRouter.scala:87:24]
wire _out_T_2660 = ~out_romask_227; // @[RegisterRouter.scala:87:24]
wire _out_T_2661 = ~out_womask_227; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_182 = {hi_370, flags_0_go, _out_prepend_T_182}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_2662 = out_prepend_182; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_2663 = _out_T_2662; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_183 = _out_T_2663; // @[RegisterRouter.scala:87:24]
wire out_rimask_228 = |_out_rimask_T_228; // @[RegisterRouter.scala:87:24]
wire out_wimask_228 = &_out_wimask_T_228; // @[RegisterRouter.scala:87:24]
wire out_romask_228 = |_out_romask_T_228; // @[RegisterRouter.scala:87:24]
wire out_womask_228 = &_out_womask_T_228; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_228 = out_rivalid_1_82 & out_rimask_228; // @[RegisterRouter.scala:87:24]
wire _out_T_2665 = out_f_rivalid_228; // @[RegisterRouter.scala:87:24]
wire out_f_roready_228 = out_roready_1_82 & out_romask_228; // @[RegisterRouter.scala:87:24]
wire _out_T_2666 = out_f_roready_228; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_228 = out_wivalid_1_82 & out_wimask_228; // @[RegisterRouter.scala:87:24]
wire out_f_woready_228 = out_woready_1_82 & out_womask_228; // @[RegisterRouter.scala:87:24]
wire _out_T_2667 = ~out_rimask_228; // @[RegisterRouter.scala:87:24]
wire _out_T_2668 = ~out_wimask_228; // @[RegisterRouter.scala:87:24]
wire _out_T_2669 = ~out_romask_228; // @[RegisterRouter.scala:87:24]
wire _out_T_2670 = ~out_womask_228; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_183 = {hi_371, flags_0_go, _out_prepend_T_183}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_2671 = out_prepend_183; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_2672 = _out_T_2671; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_184 = _out_T_2672; // @[RegisterRouter.scala:87:24]
wire out_rimask_229 = |_out_rimask_T_229; // @[RegisterRouter.scala:87:24]
wire out_wimask_229 = &_out_wimask_T_229; // @[RegisterRouter.scala:87:24]
wire out_romask_229 = |_out_romask_T_229; // @[RegisterRouter.scala:87:24]
wire out_womask_229 = &_out_womask_T_229; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_229 = out_rivalid_1_83 & out_rimask_229; // @[RegisterRouter.scala:87:24]
wire _out_T_2674 = out_f_rivalid_229; // @[RegisterRouter.scala:87:24]
wire out_f_roready_229 = out_roready_1_83 & out_romask_229; // @[RegisterRouter.scala:87:24]
wire _out_T_2675 = out_f_roready_229; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_229 = out_wivalid_1_83 & out_wimask_229; // @[RegisterRouter.scala:87:24]
wire out_f_woready_229 = out_woready_1_83 & out_womask_229; // @[RegisterRouter.scala:87:24]
wire _out_T_2676 = ~out_rimask_229; // @[RegisterRouter.scala:87:24]
wire _out_T_2677 = ~out_wimask_229; // @[RegisterRouter.scala:87:24]
wire _out_T_2678 = ~out_romask_229; // @[RegisterRouter.scala:87:24]
wire _out_T_2679 = ~out_womask_229; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_184 = {hi_372, flags_0_go, _out_prepend_T_184}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_2680 = out_prepend_184; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_2681 = _out_T_2680; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_185 = _out_T_2681; // @[RegisterRouter.scala:87:24]
wire out_rimask_230 = |_out_rimask_T_230; // @[RegisterRouter.scala:87:24]
wire out_wimask_230 = &_out_wimask_T_230; // @[RegisterRouter.scala:87:24]
wire out_romask_230 = |_out_romask_T_230; // @[RegisterRouter.scala:87:24]
wire out_womask_230 = &_out_womask_T_230; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_230 = out_rivalid_1_84 & out_rimask_230; // @[RegisterRouter.scala:87:24]
wire _out_T_2683 = out_f_rivalid_230; // @[RegisterRouter.scala:87:24]
wire out_f_roready_230 = out_roready_1_84 & out_romask_230; // @[RegisterRouter.scala:87:24]
wire _out_T_2684 = out_f_roready_230; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_230 = out_wivalid_1_84 & out_wimask_230; // @[RegisterRouter.scala:87:24]
wire out_f_woready_230 = out_woready_1_84 & out_womask_230; // @[RegisterRouter.scala:87:24]
wire _out_T_2685 = ~out_rimask_230; // @[RegisterRouter.scala:87:24]
wire _out_T_2686 = ~out_wimask_230; // @[RegisterRouter.scala:87:24]
wire _out_T_2687 = ~out_romask_230; // @[RegisterRouter.scala:87:24]
wire _out_T_2688 = ~out_womask_230; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_185 = {hi_373, flags_0_go, _out_prepend_T_185}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_2689 = out_prepend_185; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_2690 = _out_T_2689; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_186 = _out_T_2690; // @[RegisterRouter.scala:87:24]
wire out_rimask_231 = |_out_rimask_T_231; // @[RegisterRouter.scala:87:24]
wire out_wimask_231 = &_out_wimask_T_231; // @[RegisterRouter.scala:87:24]
wire out_romask_231 = |_out_romask_T_231; // @[RegisterRouter.scala:87:24]
wire out_womask_231 = &_out_womask_T_231; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_231 = out_rivalid_1_85 & out_rimask_231; // @[RegisterRouter.scala:87:24]
wire _out_T_2692 = out_f_rivalid_231; // @[RegisterRouter.scala:87:24]
wire out_f_roready_231 = out_roready_1_85 & out_romask_231; // @[RegisterRouter.scala:87:24]
wire _out_T_2693 = out_f_roready_231; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_231 = out_wivalid_1_85 & out_wimask_231; // @[RegisterRouter.scala:87:24]
wire out_f_woready_231 = out_woready_1_85 & out_womask_231; // @[RegisterRouter.scala:87:24]
wire _out_T_2694 = ~out_rimask_231; // @[RegisterRouter.scala:87:24]
wire _out_T_2695 = ~out_wimask_231; // @[RegisterRouter.scala:87:24]
wire _out_T_2696 = ~out_romask_231; // @[RegisterRouter.scala:87:24]
wire _out_T_2697 = ~out_womask_231; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_186 = {hi_374, flags_0_go, _out_prepend_T_186}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_2698 = out_prepend_186; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_2699 = _out_T_2698; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_187 = _out_T_2699; // @[RegisterRouter.scala:87:24]
wire out_rimask_232 = |_out_rimask_T_232; // @[RegisterRouter.scala:87:24]
wire out_wimask_232 = &_out_wimask_T_232; // @[RegisterRouter.scala:87:24]
wire out_romask_232 = |_out_romask_T_232; // @[RegisterRouter.scala:87:24]
wire out_womask_232 = &_out_womask_T_232; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_232 = out_rivalid_1_86 & out_rimask_232; // @[RegisterRouter.scala:87:24]
wire _out_T_2701 = out_f_rivalid_232; // @[RegisterRouter.scala:87:24]
wire out_f_roready_232 = out_roready_1_86 & out_romask_232; // @[RegisterRouter.scala:87:24]
wire _out_T_2702 = out_f_roready_232; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_232 = out_wivalid_1_86 & out_wimask_232; // @[RegisterRouter.scala:87:24]
wire out_f_woready_232 = out_woready_1_86 & out_womask_232; // @[RegisterRouter.scala:87:24]
wire _out_T_2703 = ~out_rimask_232; // @[RegisterRouter.scala:87:24]
wire _out_T_2704 = ~out_wimask_232; // @[RegisterRouter.scala:87:24]
wire _out_T_2705 = ~out_romask_232; // @[RegisterRouter.scala:87:24]
wire _out_T_2706 = ~out_womask_232; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_187 = {hi_375, flags_0_go, _out_prepend_T_187}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_2707 = out_prepend_187; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_2708 = _out_T_2707; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_188 = _out_T_2708; // @[RegisterRouter.scala:87:24]
wire out_rimask_233 = |_out_rimask_T_233; // @[RegisterRouter.scala:87:24]
wire out_wimask_233 = &_out_wimask_T_233; // @[RegisterRouter.scala:87:24]
wire out_romask_233 = |_out_romask_T_233; // @[RegisterRouter.scala:87:24]
wire out_womask_233 = &_out_womask_T_233; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_233 = out_rivalid_1_87 & out_rimask_233; // @[RegisterRouter.scala:87:24]
wire _out_T_2710 = out_f_rivalid_233; // @[RegisterRouter.scala:87:24]
wire out_f_roready_233 = out_roready_1_87 & out_romask_233; // @[RegisterRouter.scala:87:24]
wire _out_T_2711 = out_f_roready_233; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_233 = out_wivalid_1_87 & out_wimask_233; // @[RegisterRouter.scala:87:24]
wire out_f_woready_233 = out_woready_1_87 & out_womask_233; // @[RegisterRouter.scala:87:24]
wire _out_T_2712 = ~out_rimask_233; // @[RegisterRouter.scala:87:24]
wire _out_T_2713 = ~out_wimask_233; // @[RegisterRouter.scala:87:24]
wire _out_T_2714 = ~out_romask_233; // @[RegisterRouter.scala:87:24]
wire _out_T_2715 = ~out_womask_233; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_188 = {hi_376, flags_0_go, _out_prepend_T_188}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_2716 = out_prepend_188; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_2717 = _out_T_2716; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_174 = _out_T_2717; // @[MuxLiteral.scala:49:48]
wire out_rimask_234 = |_out_rimask_T_234; // @[RegisterRouter.scala:87:24]
wire out_wimask_234 = &_out_wimask_T_234; // @[RegisterRouter.scala:87:24]
wire out_romask_234 = |_out_romask_T_234; // @[RegisterRouter.scala:87:24]
wire out_womask_234 = &_out_womask_T_234; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_234 = out_rivalid_1_88 & out_rimask_234; // @[RegisterRouter.scala:87:24]
wire _out_T_2719 = out_f_rivalid_234; // @[RegisterRouter.scala:87:24]
wire out_f_roready_234 = out_roready_1_88 & out_romask_234; // @[RegisterRouter.scala:87:24]
wire _out_T_2720 = out_f_roready_234; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_234 = out_wivalid_1_88 & out_wimask_234; // @[RegisterRouter.scala:87:24]
wire out_f_woready_234 = out_woready_1_88 & out_womask_234; // @[RegisterRouter.scala:87:24]
wire _out_T_2721 = ~out_rimask_234; // @[RegisterRouter.scala:87:24]
wire _out_T_2722 = ~out_wimask_234; // @[RegisterRouter.scala:87:24]
wire _out_T_2723 = ~out_romask_234; // @[RegisterRouter.scala:87:24]
wire _out_T_2724 = ~out_womask_234; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2726 = _out_T_2725; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_189 = _out_T_2726; // @[RegisterRouter.scala:87:24]
wire out_rimask_235 = |_out_rimask_T_235; // @[RegisterRouter.scala:87:24]
wire out_wimask_235 = &_out_wimask_T_235; // @[RegisterRouter.scala:87:24]
wire out_romask_235 = |_out_romask_T_235; // @[RegisterRouter.scala:87:24]
wire out_womask_235 = &_out_womask_T_235; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_235 = out_rivalid_1_89 & out_rimask_235; // @[RegisterRouter.scala:87:24]
wire _out_T_2728 = out_f_rivalid_235; // @[RegisterRouter.scala:87:24]
wire out_f_roready_235 = out_roready_1_89 & out_romask_235; // @[RegisterRouter.scala:87:24]
wire _out_T_2729 = out_f_roready_235; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_235 = out_wivalid_1_89 & out_wimask_235; // @[RegisterRouter.scala:87:24]
wire out_f_woready_235 = out_woready_1_89 & out_womask_235; // @[RegisterRouter.scala:87:24]
wire _out_T_2730 = ~out_rimask_235; // @[RegisterRouter.scala:87:24]
wire _out_T_2731 = ~out_wimask_235; // @[RegisterRouter.scala:87:24]
wire _out_T_2732 = ~out_romask_235; // @[RegisterRouter.scala:87:24]
wire _out_T_2733 = ~out_womask_235; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_189 = {hi_458, flags_0_go, _out_prepend_T_189}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_2734 = out_prepend_189; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_2735 = _out_T_2734; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_190 = _out_T_2735; // @[RegisterRouter.scala:87:24]
wire out_rimask_236 = |_out_rimask_T_236; // @[RegisterRouter.scala:87:24]
wire out_wimask_236 = &_out_wimask_T_236; // @[RegisterRouter.scala:87:24]
wire out_romask_236 = |_out_romask_T_236; // @[RegisterRouter.scala:87:24]
wire out_womask_236 = &_out_womask_T_236; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_236 = out_rivalid_1_90 & out_rimask_236; // @[RegisterRouter.scala:87:24]
wire _out_T_2737 = out_f_rivalid_236; // @[RegisterRouter.scala:87:24]
wire out_f_roready_236 = out_roready_1_90 & out_romask_236; // @[RegisterRouter.scala:87:24]
wire _out_T_2738 = out_f_roready_236; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_236 = out_wivalid_1_90 & out_wimask_236; // @[RegisterRouter.scala:87:24]
wire out_f_woready_236 = out_woready_1_90 & out_womask_236; // @[RegisterRouter.scala:87:24]
wire _out_T_2739 = ~out_rimask_236; // @[RegisterRouter.scala:87:24]
wire _out_T_2740 = ~out_wimask_236; // @[RegisterRouter.scala:87:24]
wire _out_T_2741 = ~out_romask_236; // @[RegisterRouter.scala:87:24]
wire _out_T_2742 = ~out_womask_236; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_190 = {hi_459, flags_0_go, _out_prepend_T_190}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_2743 = out_prepend_190; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_2744 = _out_T_2743; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_191 = _out_T_2744; // @[RegisterRouter.scala:87:24]
wire out_rimask_237 = |_out_rimask_T_237; // @[RegisterRouter.scala:87:24]
wire out_wimask_237 = &_out_wimask_T_237; // @[RegisterRouter.scala:87:24]
wire out_romask_237 = |_out_romask_T_237; // @[RegisterRouter.scala:87:24]
wire out_womask_237 = &_out_womask_T_237; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_237 = out_rivalid_1_91 & out_rimask_237; // @[RegisterRouter.scala:87:24]
wire _out_T_2746 = out_f_rivalid_237; // @[RegisterRouter.scala:87:24]
wire out_f_roready_237 = out_roready_1_91 & out_romask_237; // @[RegisterRouter.scala:87:24]
wire _out_T_2747 = out_f_roready_237; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_237 = out_wivalid_1_91 & out_wimask_237; // @[RegisterRouter.scala:87:24]
wire out_f_woready_237 = out_woready_1_91 & out_womask_237; // @[RegisterRouter.scala:87:24]
wire _out_T_2748 = ~out_rimask_237; // @[RegisterRouter.scala:87:24]
wire _out_T_2749 = ~out_wimask_237; // @[RegisterRouter.scala:87:24]
wire _out_T_2750 = ~out_romask_237; // @[RegisterRouter.scala:87:24]
wire _out_T_2751 = ~out_womask_237; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_191 = {hi_460, flags_0_go, _out_prepend_T_191}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_2752 = out_prepend_191; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_2753 = _out_T_2752; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_192 = _out_T_2753; // @[RegisterRouter.scala:87:24]
wire out_rimask_238 = |_out_rimask_T_238; // @[RegisterRouter.scala:87:24]
wire out_wimask_238 = &_out_wimask_T_238; // @[RegisterRouter.scala:87:24]
wire out_romask_238 = |_out_romask_T_238; // @[RegisterRouter.scala:87:24]
wire out_womask_238 = &_out_womask_T_238; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_238 = out_rivalid_1_92 & out_rimask_238; // @[RegisterRouter.scala:87:24]
wire _out_T_2755 = out_f_rivalid_238; // @[RegisterRouter.scala:87:24]
wire out_f_roready_238 = out_roready_1_92 & out_romask_238; // @[RegisterRouter.scala:87:24]
wire _out_T_2756 = out_f_roready_238; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_238 = out_wivalid_1_92 & out_wimask_238; // @[RegisterRouter.scala:87:24]
wire out_f_woready_238 = out_woready_1_92 & out_womask_238; // @[RegisterRouter.scala:87:24]
wire _out_T_2757 = ~out_rimask_238; // @[RegisterRouter.scala:87:24]
wire _out_T_2758 = ~out_wimask_238; // @[RegisterRouter.scala:87:24]
wire _out_T_2759 = ~out_romask_238; // @[RegisterRouter.scala:87:24]
wire _out_T_2760 = ~out_womask_238; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_192 = {hi_461, flags_0_go, _out_prepend_T_192}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_2761 = out_prepend_192; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_2762 = _out_T_2761; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_193 = _out_T_2762; // @[RegisterRouter.scala:87:24]
wire out_rimask_239 = |_out_rimask_T_239; // @[RegisterRouter.scala:87:24]
wire out_wimask_239 = &_out_wimask_T_239; // @[RegisterRouter.scala:87:24]
wire out_romask_239 = |_out_romask_T_239; // @[RegisterRouter.scala:87:24]
wire out_womask_239 = &_out_womask_T_239; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_239 = out_rivalid_1_93 & out_rimask_239; // @[RegisterRouter.scala:87:24]
wire _out_T_2764 = out_f_rivalid_239; // @[RegisterRouter.scala:87:24]
wire out_f_roready_239 = out_roready_1_93 & out_romask_239; // @[RegisterRouter.scala:87:24]
wire _out_T_2765 = out_f_roready_239; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_239 = out_wivalid_1_93 & out_wimask_239; // @[RegisterRouter.scala:87:24]
wire out_f_woready_239 = out_woready_1_93 & out_womask_239; // @[RegisterRouter.scala:87:24]
wire _out_T_2766 = ~out_rimask_239; // @[RegisterRouter.scala:87:24]
wire _out_T_2767 = ~out_wimask_239; // @[RegisterRouter.scala:87:24]
wire _out_T_2768 = ~out_romask_239; // @[RegisterRouter.scala:87:24]
wire _out_T_2769 = ~out_womask_239; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_193 = {hi_462, flags_0_go, _out_prepend_T_193}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_2770 = out_prepend_193; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_2771 = _out_T_2770; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_194 = _out_T_2771; // @[RegisterRouter.scala:87:24]
wire out_rimask_240 = |_out_rimask_T_240; // @[RegisterRouter.scala:87:24]
wire out_wimask_240 = &_out_wimask_T_240; // @[RegisterRouter.scala:87:24]
wire out_romask_240 = |_out_romask_T_240; // @[RegisterRouter.scala:87:24]
wire out_womask_240 = &_out_womask_T_240; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_240 = out_rivalid_1_94 & out_rimask_240; // @[RegisterRouter.scala:87:24]
wire _out_T_2773 = out_f_rivalid_240; // @[RegisterRouter.scala:87:24]
wire out_f_roready_240 = out_roready_1_94 & out_romask_240; // @[RegisterRouter.scala:87:24]
wire _out_T_2774 = out_f_roready_240; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_240 = out_wivalid_1_94 & out_wimask_240; // @[RegisterRouter.scala:87:24]
wire out_f_woready_240 = out_woready_1_94 & out_womask_240; // @[RegisterRouter.scala:87:24]
wire _out_T_2775 = ~out_rimask_240; // @[RegisterRouter.scala:87:24]
wire _out_T_2776 = ~out_wimask_240; // @[RegisterRouter.scala:87:24]
wire _out_T_2777 = ~out_romask_240; // @[RegisterRouter.scala:87:24]
wire _out_T_2778 = ~out_womask_240; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_194 = {hi_463, flags_0_go, _out_prepend_T_194}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_2779 = out_prepend_194; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_2780 = _out_T_2779; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_195 = _out_T_2780; // @[RegisterRouter.scala:87:24]
wire out_rimask_241 = |_out_rimask_T_241; // @[RegisterRouter.scala:87:24]
wire out_wimask_241 = &_out_wimask_T_241; // @[RegisterRouter.scala:87:24]
wire out_romask_241 = |_out_romask_T_241; // @[RegisterRouter.scala:87:24]
wire out_womask_241 = &_out_womask_T_241; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_241 = out_rivalid_1_95 & out_rimask_241; // @[RegisterRouter.scala:87:24]
wire _out_T_2782 = out_f_rivalid_241; // @[RegisterRouter.scala:87:24]
wire out_f_roready_241 = out_roready_1_95 & out_romask_241; // @[RegisterRouter.scala:87:24]
wire _out_T_2783 = out_f_roready_241; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_241 = out_wivalid_1_95 & out_wimask_241; // @[RegisterRouter.scala:87:24]
wire out_f_woready_241 = out_woready_1_95 & out_womask_241; // @[RegisterRouter.scala:87:24]
wire _out_T_2784 = ~out_rimask_241; // @[RegisterRouter.scala:87:24]
wire _out_T_2785 = ~out_wimask_241; // @[RegisterRouter.scala:87:24]
wire _out_T_2786 = ~out_romask_241; // @[RegisterRouter.scala:87:24]
wire _out_T_2787 = ~out_womask_241; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_195 = {hi_464, flags_0_go, _out_prepend_T_195}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_2788 = out_prepend_195; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_2789 = _out_T_2788; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_185 = _out_T_2789; // @[MuxLiteral.scala:49:48]
wire out_rimask_242 = |_out_rimask_T_242; // @[RegisterRouter.scala:87:24]
wire out_wimask_242 = &_out_wimask_T_242; // @[RegisterRouter.scala:87:24]
wire out_romask_242 = |_out_romask_T_242; // @[RegisterRouter.scala:87:24]
wire out_womask_242 = &_out_womask_T_242; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_242 = out_rivalid_1_96 & out_rimask_242; // @[RegisterRouter.scala:87:24]
wire _out_T_2791 = out_f_rivalid_242; // @[RegisterRouter.scala:87:24]
wire out_f_roready_242 = out_roready_1_96 & out_romask_242; // @[RegisterRouter.scala:87:24]
wire _out_T_2792 = out_f_roready_242; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_242 = out_wivalid_1_96 & out_wimask_242; // @[RegisterRouter.scala:87:24]
wire out_f_woready_242 = out_woready_1_96 & out_womask_242; // @[RegisterRouter.scala:87:24]
wire _out_T_2793 = ~out_rimask_242; // @[RegisterRouter.scala:87:24]
wire _out_T_2794 = ~out_wimask_242; // @[RegisterRouter.scala:87:24]
wire _out_T_2795 = ~out_romask_242; // @[RegisterRouter.scala:87:24]
wire _out_T_2796 = ~out_womask_242; // @[RegisterRouter.scala:87:24]
wire out_rimask_243 = |_out_rimask_T_243; // @[RegisterRouter.scala:87:24]
wire out_wimask_243 = &_out_wimask_T_243; // @[RegisterRouter.scala:87:24]
wire out_romask_243 = |_out_romask_T_243; // @[RegisterRouter.scala:87:24]
wire out_womask_243 = &_out_womask_T_243; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_243 = out_rivalid_1_97 & out_rimask_243; // @[RegisterRouter.scala:87:24]
wire _out_T_2800 = out_f_rivalid_243; // @[RegisterRouter.scala:87:24]
wire out_f_roready_243 = out_roready_1_97 & out_romask_243; // @[RegisterRouter.scala:87:24]
wire _out_T_2801 = out_f_roready_243; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_243 = out_wivalid_1_97 & out_wimask_243; // @[RegisterRouter.scala:87:24]
wire out_f_woready_243 = out_woready_1_97 & out_womask_243; // @[RegisterRouter.scala:87:24]
wire _out_T_2802 = ~out_rimask_243; // @[RegisterRouter.scala:87:24]
wire _out_T_2803 = ~out_wimask_243; // @[RegisterRouter.scala:87:24]
wire _out_T_2804 = ~out_romask_243; // @[RegisterRouter.scala:87:24]
wire _out_T_2805 = ~out_womask_243; // @[RegisterRouter.scala:87:24]
wire out_rimask_244 = |_out_rimask_T_244; // @[RegisterRouter.scala:87:24]
wire out_wimask_244 = &_out_wimask_T_244; // @[RegisterRouter.scala:87:24]
wire out_romask_244 = |_out_romask_T_244; // @[RegisterRouter.scala:87:24]
wire out_womask_244 = &_out_womask_T_244; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_244 = out_rivalid_1_98 & out_rimask_244; // @[RegisterRouter.scala:87:24]
wire _out_T_2809 = out_f_rivalid_244; // @[RegisterRouter.scala:87:24]
wire out_f_roready_244 = out_roready_1_98 & out_romask_244; // @[RegisterRouter.scala:87:24]
wire _out_T_2810 = out_f_roready_244; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_244 = out_wivalid_1_98 & out_wimask_244; // @[RegisterRouter.scala:87:24]
wire out_f_woready_244 = out_woready_1_98 & out_womask_244; // @[RegisterRouter.scala:87:24]
wire _out_T_2811 = ~out_rimask_244; // @[RegisterRouter.scala:87:24]
wire _out_T_2812 = ~out_wimask_244; // @[RegisterRouter.scala:87:24]
wire _out_T_2813 = ~out_romask_244; // @[RegisterRouter.scala:87:24]
wire _out_T_2814 = ~out_womask_244; // @[RegisterRouter.scala:87:24]
wire out_rimask_245 = |_out_rimask_T_245; // @[RegisterRouter.scala:87:24]
wire out_wimask_245 = &_out_wimask_T_245; // @[RegisterRouter.scala:87:24]
wire out_romask_245 = |_out_romask_T_245; // @[RegisterRouter.scala:87:24]
wire out_womask_245 = &_out_womask_T_245; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_245 = out_rivalid_1_99 & out_rimask_245; // @[RegisterRouter.scala:87:24]
wire _out_T_2818 = out_f_rivalid_245; // @[RegisterRouter.scala:87:24]
wire out_f_roready_245 = out_roready_1_99 & out_romask_245; // @[RegisterRouter.scala:87:24]
wire _out_T_2819 = out_f_roready_245; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_245 = out_wivalid_1_99 & out_wimask_245; // @[RegisterRouter.scala:87:24]
wire out_f_woready_245 = out_woready_1_99 & out_womask_245; // @[RegisterRouter.scala:87:24]
wire _out_T_2820 = ~out_rimask_245; // @[RegisterRouter.scala:87:24]
wire _out_T_2821 = ~out_wimask_245; // @[RegisterRouter.scala:87:24]
wire _out_T_2822 = ~out_romask_245; // @[RegisterRouter.scala:87:24]
wire _out_T_2823 = ~out_womask_245; // @[RegisterRouter.scala:87:24]
wire out_rimask_246 = |_out_rimask_T_246; // @[RegisterRouter.scala:87:24]
wire out_wimask_246 = &_out_wimask_T_246; // @[RegisterRouter.scala:87:24]
wire out_romask_246 = |_out_romask_T_246; // @[RegisterRouter.scala:87:24]
wire out_womask_246 = &_out_womask_T_246; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_246 = out_rivalid_1_100 & out_rimask_246; // @[RegisterRouter.scala:87:24]
wire _out_T_2827 = out_f_rivalid_246; // @[RegisterRouter.scala:87:24]
wire out_f_roready_246 = out_roready_1_100 & out_romask_246; // @[RegisterRouter.scala:87:24]
wire _out_T_2828 = out_f_roready_246; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_246 = out_wivalid_1_100 & out_wimask_246; // @[RegisterRouter.scala:87:24]
wire out_f_woready_246 = out_woready_1_100 & out_womask_246; // @[RegisterRouter.scala:87:24]
wire _out_T_2829 = ~out_rimask_246; // @[RegisterRouter.scala:87:24]
wire _out_T_2830 = ~out_wimask_246; // @[RegisterRouter.scala:87:24]
wire _out_T_2831 = ~out_romask_246; // @[RegisterRouter.scala:87:24]
wire _out_T_2832 = ~out_womask_246; // @[RegisterRouter.scala:87:24]
wire out_rimask_247 = |_out_rimask_T_247; // @[RegisterRouter.scala:87:24]
wire out_wimask_247 = &_out_wimask_T_247; // @[RegisterRouter.scala:87:24]
wire out_romask_247 = |_out_romask_T_247; // @[RegisterRouter.scala:87:24]
wire out_womask_247 = &_out_womask_T_247; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_247 = out_rivalid_1_101 & out_rimask_247; // @[RegisterRouter.scala:87:24]
wire _out_T_2836 = out_f_rivalid_247; // @[RegisterRouter.scala:87:24]
wire out_f_roready_247 = out_roready_1_101 & out_romask_247; // @[RegisterRouter.scala:87:24]
wire _out_T_2837 = out_f_roready_247; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_247 = out_wivalid_1_101 & out_wimask_247; // @[RegisterRouter.scala:87:24]
wire out_f_woready_247 = out_woready_1_101 & out_womask_247; // @[RegisterRouter.scala:87:24]
wire _out_T_2838 = ~out_rimask_247; // @[RegisterRouter.scala:87:24]
wire _out_T_2839 = ~out_wimask_247; // @[RegisterRouter.scala:87:24]
wire _out_T_2840 = ~out_romask_247; // @[RegisterRouter.scala:87:24]
wire _out_T_2841 = ~out_womask_247; // @[RegisterRouter.scala:87:24]
wire out_rimask_248 = |_out_rimask_T_248; // @[RegisterRouter.scala:87:24]
wire out_wimask_248 = &_out_wimask_T_248; // @[RegisterRouter.scala:87:24]
wire out_romask_248 = |_out_romask_T_248; // @[RegisterRouter.scala:87:24]
wire out_womask_248 = &_out_womask_T_248; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_248 = out_rivalid_1_102 & out_rimask_248; // @[RegisterRouter.scala:87:24]
wire _out_T_2845 = out_f_rivalid_248; // @[RegisterRouter.scala:87:24]
wire out_f_roready_248 = out_roready_1_102 & out_romask_248; // @[RegisterRouter.scala:87:24]
wire _out_T_2846 = out_f_roready_248; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_248 = out_wivalid_1_102 & out_wimask_248; // @[RegisterRouter.scala:87:24]
wire out_f_woready_248 = out_woready_1_102 & out_womask_248; // @[RegisterRouter.scala:87:24]
wire _out_T_2847 = ~out_rimask_248; // @[RegisterRouter.scala:87:24]
wire _out_T_2848 = ~out_wimask_248; // @[RegisterRouter.scala:87:24]
wire _out_T_2849 = ~out_romask_248; // @[RegisterRouter.scala:87:24]
wire _out_T_2850 = ~out_womask_248; // @[RegisterRouter.scala:87:24]
wire out_rimask_249 = |_out_rimask_T_249; // @[RegisterRouter.scala:87:24]
wire out_wimask_249 = &_out_wimask_T_249; // @[RegisterRouter.scala:87:24]
wire out_romask_249 = |_out_romask_T_249; // @[RegisterRouter.scala:87:24]
wire out_womask_249 = &_out_womask_T_249; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_249 = out_rivalid_1_103 & out_rimask_249; // @[RegisterRouter.scala:87:24]
wire _out_T_2854 = out_f_rivalid_249; // @[RegisterRouter.scala:87:24]
wire out_f_roready_249 = out_roready_1_103 & out_romask_249; // @[RegisterRouter.scala:87:24]
wire _out_T_2855 = out_f_roready_249; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_249 = out_wivalid_1_103 & out_wimask_249; // @[RegisterRouter.scala:87:24]
wire out_f_woready_249 = out_woready_1_103 & out_womask_249; // @[RegisterRouter.scala:87:24]
wire _out_T_2856 = ~out_rimask_249; // @[RegisterRouter.scala:87:24]
wire _out_T_2857 = ~out_wimask_249; // @[RegisterRouter.scala:87:24]
wire _out_T_2858 = ~out_romask_249; // @[RegisterRouter.scala:87:24]
wire _out_T_2859 = ~out_womask_249; // @[RegisterRouter.scala:87:24]
wire out_rimask_250 = |_out_rimask_T_250; // @[RegisterRouter.scala:87:24]
wire out_wimask_250 = &_out_wimask_T_250; // @[RegisterRouter.scala:87:24]
wire out_romask_250 = |_out_romask_T_250; // @[RegisterRouter.scala:87:24]
wire out_womask_250 = &_out_womask_T_250; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_250 = out_rivalid_1_104 & out_rimask_250; // @[RegisterRouter.scala:87:24]
wire _out_T_2863 = out_f_rivalid_250; // @[RegisterRouter.scala:87:24]
wire out_f_roready_250 = out_roready_1_104 & out_romask_250; // @[RegisterRouter.scala:87:24]
wire _out_T_2864 = out_f_roready_250; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_250 = out_wivalid_1_104 & out_wimask_250; // @[RegisterRouter.scala:87:24]
wire out_f_woready_250 = out_woready_1_104 & out_womask_250; // @[RegisterRouter.scala:87:24]
wire _out_T_2865 = ~out_rimask_250; // @[RegisterRouter.scala:87:24]
wire _out_T_2866 = ~out_wimask_250; // @[RegisterRouter.scala:87:24]
wire _out_T_2867 = ~out_romask_250; // @[RegisterRouter.scala:87:24]
wire _out_T_2868 = ~out_womask_250; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2870 = _out_T_2869; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_203 = _out_T_2870; // @[RegisterRouter.scala:87:24]
wire out_rimask_251 = |_out_rimask_T_251; // @[RegisterRouter.scala:87:24]
wire out_wimask_251 = &_out_wimask_T_251; // @[RegisterRouter.scala:87:24]
wire out_romask_251 = |_out_romask_T_251; // @[RegisterRouter.scala:87:24]
wire out_womask_251 = &_out_womask_T_251; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_251 = out_rivalid_1_105 & out_rimask_251; // @[RegisterRouter.scala:87:24]
wire _out_T_2872 = out_f_rivalid_251; // @[RegisterRouter.scala:87:24]
wire out_f_roready_251 = out_roready_1_105 & out_romask_251; // @[RegisterRouter.scala:87:24]
wire _out_T_2873 = out_f_roready_251; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_251 = out_wivalid_1_105 & out_wimask_251; // @[RegisterRouter.scala:87:24]
wire out_f_woready_251 = out_woready_1_105 & out_womask_251; // @[RegisterRouter.scala:87:24]
wire _out_T_2874 = ~out_rimask_251; // @[RegisterRouter.scala:87:24]
wire _out_T_2875 = ~out_wimask_251; // @[RegisterRouter.scala:87:24]
wire _out_T_2876 = ~out_romask_251; // @[RegisterRouter.scala:87:24]
wire _out_T_2877 = ~out_womask_251; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_203 = {hi_450, flags_0_go, _out_prepend_T_203}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_2878 = out_prepend_203; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_2879 = _out_T_2878; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_204 = _out_T_2879; // @[RegisterRouter.scala:87:24]
wire out_rimask_252 = |_out_rimask_T_252; // @[RegisterRouter.scala:87:24]
wire out_wimask_252 = &_out_wimask_T_252; // @[RegisterRouter.scala:87:24]
wire out_romask_252 = |_out_romask_T_252; // @[RegisterRouter.scala:87:24]
wire out_womask_252 = &_out_womask_T_252; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_252 = out_rivalid_1_106 & out_rimask_252; // @[RegisterRouter.scala:87:24]
wire _out_T_2881 = out_f_rivalid_252; // @[RegisterRouter.scala:87:24]
wire out_f_roready_252 = out_roready_1_106 & out_romask_252; // @[RegisterRouter.scala:87:24]
wire _out_T_2882 = out_f_roready_252; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_252 = out_wivalid_1_106 & out_wimask_252; // @[RegisterRouter.scala:87:24]
wire out_f_woready_252 = out_woready_1_106 & out_womask_252; // @[RegisterRouter.scala:87:24]
wire _out_T_2883 = ~out_rimask_252; // @[RegisterRouter.scala:87:24]
wire _out_T_2884 = ~out_wimask_252; // @[RegisterRouter.scala:87:24]
wire _out_T_2885 = ~out_romask_252; // @[RegisterRouter.scala:87:24]
wire _out_T_2886 = ~out_womask_252; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_204 = {hi_451, flags_0_go, _out_prepend_T_204}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_2887 = out_prepend_204; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_2888 = _out_T_2887; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_205 = _out_T_2888; // @[RegisterRouter.scala:87:24]
wire out_rimask_253 = |_out_rimask_T_253; // @[RegisterRouter.scala:87:24]
wire out_wimask_253 = &_out_wimask_T_253; // @[RegisterRouter.scala:87:24]
wire out_romask_253 = |_out_romask_T_253; // @[RegisterRouter.scala:87:24]
wire out_womask_253 = &_out_womask_T_253; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_253 = out_rivalid_1_107 & out_rimask_253; // @[RegisterRouter.scala:87:24]
wire _out_T_2890 = out_f_rivalid_253; // @[RegisterRouter.scala:87:24]
wire out_f_roready_253 = out_roready_1_107 & out_romask_253; // @[RegisterRouter.scala:87:24]
wire _out_T_2891 = out_f_roready_253; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_253 = out_wivalid_1_107 & out_wimask_253; // @[RegisterRouter.scala:87:24]
wire out_f_woready_253 = out_woready_1_107 & out_womask_253; // @[RegisterRouter.scala:87:24]
wire _out_T_2892 = ~out_rimask_253; // @[RegisterRouter.scala:87:24]
wire _out_T_2893 = ~out_wimask_253; // @[RegisterRouter.scala:87:24]
wire _out_T_2894 = ~out_romask_253; // @[RegisterRouter.scala:87:24]
wire _out_T_2895 = ~out_womask_253; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_205 = {hi_452, flags_0_go, _out_prepend_T_205}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_2896 = out_prepend_205; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_2897 = _out_T_2896; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_206 = _out_T_2897; // @[RegisterRouter.scala:87:24]
wire out_rimask_254 = |_out_rimask_T_254; // @[RegisterRouter.scala:87:24]
wire out_wimask_254 = &_out_wimask_T_254; // @[RegisterRouter.scala:87:24]
wire out_romask_254 = |_out_romask_T_254; // @[RegisterRouter.scala:87:24]
wire out_womask_254 = &_out_womask_T_254; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_254 = out_rivalid_1_108 & out_rimask_254; // @[RegisterRouter.scala:87:24]
wire _out_T_2899 = out_f_rivalid_254; // @[RegisterRouter.scala:87:24]
wire out_f_roready_254 = out_roready_1_108 & out_romask_254; // @[RegisterRouter.scala:87:24]
wire _out_T_2900 = out_f_roready_254; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_254 = out_wivalid_1_108 & out_wimask_254; // @[RegisterRouter.scala:87:24]
wire out_f_woready_254 = out_woready_1_108 & out_womask_254; // @[RegisterRouter.scala:87:24]
wire _out_T_2901 = ~out_rimask_254; // @[RegisterRouter.scala:87:24]
wire _out_T_2902 = ~out_wimask_254; // @[RegisterRouter.scala:87:24]
wire _out_T_2903 = ~out_romask_254; // @[RegisterRouter.scala:87:24]
wire _out_T_2904 = ~out_womask_254; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_206 = {hi_453, flags_0_go, _out_prepend_T_206}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_2905 = out_prepend_206; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_2906 = _out_T_2905; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_207 = _out_T_2906; // @[RegisterRouter.scala:87:24]
wire out_rimask_255 = |_out_rimask_T_255; // @[RegisterRouter.scala:87:24]
wire out_wimask_255 = &_out_wimask_T_255; // @[RegisterRouter.scala:87:24]
wire out_romask_255 = |_out_romask_T_255; // @[RegisterRouter.scala:87:24]
wire out_womask_255 = &_out_womask_T_255; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_255 = out_rivalid_1_109 & out_rimask_255; // @[RegisterRouter.scala:87:24]
wire _out_T_2908 = out_f_rivalid_255; // @[RegisterRouter.scala:87:24]
wire out_f_roready_255 = out_roready_1_109 & out_romask_255; // @[RegisterRouter.scala:87:24]
wire _out_T_2909 = out_f_roready_255; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_255 = out_wivalid_1_109 & out_wimask_255; // @[RegisterRouter.scala:87:24]
wire out_f_woready_255 = out_woready_1_109 & out_womask_255; // @[RegisterRouter.scala:87:24]
wire _out_T_2910 = ~out_rimask_255; // @[RegisterRouter.scala:87:24]
wire _out_T_2911 = ~out_wimask_255; // @[RegisterRouter.scala:87:24]
wire _out_T_2912 = ~out_romask_255; // @[RegisterRouter.scala:87:24]
wire _out_T_2913 = ~out_womask_255; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_207 = {hi_454, flags_0_go, _out_prepend_T_207}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_2914 = out_prepend_207; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_2915 = _out_T_2914; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_208 = _out_T_2915; // @[RegisterRouter.scala:87:24]
wire out_rimask_256 = |_out_rimask_T_256; // @[RegisterRouter.scala:87:24]
wire out_wimask_256 = &_out_wimask_T_256; // @[RegisterRouter.scala:87:24]
wire out_romask_256 = |_out_romask_T_256; // @[RegisterRouter.scala:87:24]
wire out_womask_256 = &_out_womask_T_256; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_256 = out_rivalid_1_110 & out_rimask_256; // @[RegisterRouter.scala:87:24]
wire _out_T_2917 = out_f_rivalid_256; // @[RegisterRouter.scala:87:24]
wire out_f_roready_256 = out_roready_1_110 & out_romask_256; // @[RegisterRouter.scala:87:24]
wire _out_T_2918 = out_f_roready_256; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_256 = out_wivalid_1_110 & out_wimask_256; // @[RegisterRouter.scala:87:24]
wire out_f_woready_256 = out_woready_1_110 & out_womask_256; // @[RegisterRouter.scala:87:24]
wire _out_T_2919 = ~out_rimask_256; // @[RegisterRouter.scala:87:24]
wire _out_T_2920 = ~out_wimask_256; // @[RegisterRouter.scala:87:24]
wire _out_T_2921 = ~out_romask_256; // @[RegisterRouter.scala:87:24]
wire _out_T_2922 = ~out_womask_256; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_208 = {hi_455, flags_0_go, _out_prepend_T_208}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_2923 = out_prepend_208; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_2924 = _out_T_2923; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_209 = _out_T_2924; // @[RegisterRouter.scala:87:24]
wire out_rimask_257 = |_out_rimask_T_257; // @[RegisterRouter.scala:87:24]
wire out_wimask_257 = &_out_wimask_T_257; // @[RegisterRouter.scala:87:24]
wire out_romask_257 = |_out_romask_T_257; // @[RegisterRouter.scala:87:24]
wire out_womask_257 = &_out_womask_T_257; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_257 = out_rivalid_1_111 & out_rimask_257; // @[RegisterRouter.scala:87:24]
wire _out_T_2926 = out_f_rivalid_257; // @[RegisterRouter.scala:87:24]
wire out_f_roready_257 = out_roready_1_111 & out_romask_257; // @[RegisterRouter.scala:87:24]
wire _out_T_2927 = out_f_roready_257; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_257 = out_wivalid_1_111 & out_wimask_257; // @[RegisterRouter.scala:87:24]
wire out_f_woready_257 = out_woready_1_111 & out_womask_257; // @[RegisterRouter.scala:87:24]
wire _out_T_2928 = ~out_rimask_257; // @[RegisterRouter.scala:87:24]
wire _out_T_2929 = ~out_wimask_257; // @[RegisterRouter.scala:87:24]
wire _out_T_2930 = ~out_romask_257; // @[RegisterRouter.scala:87:24]
wire _out_T_2931 = ~out_womask_257; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_209 = {hi_456, flags_0_go, _out_prepend_T_209}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_2932 = out_prepend_209; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_2933 = _out_T_2932; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_184 = _out_T_2933; // @[MuxLiteral.scala:49:48]
wire out_rimask_258 = |_out_rimask_T_258; // @[RegisterRouter.scala:87:24]
wire out_wimask_258 = &_out_wimask_T_258; // @[RegisterRouter.scala:87:24]
wire out_romask_258 = |_out_romask_T_258; // @[RegisterRouter.scala:87:24]
wire out_womask_258 = &_out_womask_T_258; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_258 = out_rivalid_1_112 & out_rimask_258; // @[RegisterRouter.scala:87:24]
wire _out_T_2935 = out_f_rivalid_258; // @[RegisterRouter.scala:87:24]
wire out_f_roready_258 = out_roready_1_112 & out_romask_258; // @[RegisterRouter.scala:87:24]
wire _out_T_2936 = out_f_roready_258; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_258 = out_wivalid_1_112 & out_wimask_258; // @[RegisterRouter.scala:87:24]
wire _out_T_2937 = out_f_wivalid_258; // @[RegisterRouter.scala:87:24]
wire out_f_woready_258 = out_woready_1_112 & out_womask_258; // @[RegisterRouter.scala:87:24]
wire _out_T_2938 = out_f_woready_258; // @[RegisterRouter.scala:87:24]
wire _out_T_2939 = ~out_rimask_258; // @[RegisterRouter.scala:87:24]
wire _out_T_2940 = ~out_wimask_258; // @[RegisterRouter.scala:87:24]
wire _out_T_2941 = ~out_romask_258; // @[RegisterRouter.scala:87:24]
wire _out_T_2942 = ~out_womask_258; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2944 = _out_T_2943; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_210 = _out_T_2944; // @[RegisterRouter.scala:87:24]
wire out_rimask_259 = |_out_rimask_T_259; // @[RegisterRouter.scala:87:24]
wire out_wimask_259 = &_out_wimask_T_259; // @[RegisterRouter.scala:87:24]
wire out_romask_259 = |_out_romask_T_259; // @[RegisterRouter.scala:87:24]
wire out_womask_259 = &_out_womask_T_259; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_259 = out_rivalid_1_113 & out_rimask_259; // @[RegisterRouter.scala:87:24]
wire _out_T_2946 = out_f_rivalid_259; // @[RegisterRouter.scala:87:24]
wire out_f_roready_259 = out_roready_1_113 & out_romask_259; // @[RegisterRouter.scala:87:24]
wire _out_T_2947 = out_f_roready_259; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_259 = out_wivalid_1_113 & out_wimask_259; // @[RegisterRouter.scala:87:24]
wire _out_T_2948 = out_f_wivalid_259; // @[RegisterRouter.scala:87:24]
wire out_f_woready_259 = out_woready_1_113 & out_womask_259; // @[RegisterRouter.scala:87:24]
wire _out_T_2949 = out_f_woready_259; // @[RegisterRouter.scala:87:24]
wire _out_T_2950 = ~out_rimask_259; // @[RegisterRouter.scala:87:24]
wire _out_T_2951 = ~out_wimask_259; // @[RegisterRouter.scala:87:24]
wire _out_T_2952 = ~out_romask_259; // @[RegisterRouter.scala:87:24]
wire _out_T_2953 = ~out_womask_259; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_210 = {programBufferMem_49, _out_prepend_T_210}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_2954 = out_prepend_210; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_2955 = _out_T_2954; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_211 = _out_T_2955; // @[RegisterRouter.scala:87:24]
wire out_rimask_260 = |_out_rimask_T_260; // @[RegisterRouter.scala:87:24]
wire out_wimask_260 = &_out_wimask_T_260; // @[RegisterRouter.scala:87:24]
wire out_romask_260 = |_out_romask_T_260; // @[RegisterRouter.scala:87:24]
wire out_womask_260 = &_out_womask_T_260; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_260 = out_rivalid_1_114 & out_rimask_260; // @[RegisterRouter.scala:87:24]
wire _out_T_2957 = out_f_rivalid_260; // @[RegisterRouter.scala:87:24]
wire out_f_roready_260 = out_roready_1_114 & out_romask_260; // @[RegisterRouter.scala:87:24]
wire _out_T_2958 = out_f_roready_260; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_260 = out_wivalid_1_114 & out_wimask_260; // @[RegisterRouter.scala:87:24]
wire _out_T_2959 = out_f_wivalid_260; // @[RegisterRouter.scala:87:24]
wire out_f_woready_260 = out_woready_1_114 & out_womask_260; // @[RegisterRouter.scala:87:24]
wire _out_T_2960 = out_f_woready_260; // @[RegisterRouter.scala:87:24]
wire _out_T_2961 = ~out_rimask_260; // @[RegisterRouter.scala:87:24]
wire _out_T_2962 = ~out_wimask_260; // @[RegisterRouter.scala:87:24]
wire _out_T_2963 = ~out_romask_260; // @[RegisterRouter.scala:87:24]
wire _out_T_2964 = ~out_womask_260; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_211 = {programBufferMem_50, _out_prepend_T_211}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_2965 = out_prepend_211; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_2966 = _out_T_2965; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_212 = _out_T_2966; // @[RegisterRouter.scala:87:24]
wire out_rimask_261 = |_out_rimask_T_261; // @[RegisterRouter.scala:87:24]
wire out_wimask_261 = &_out_wimask_T_261; // @[RegisterRouter.scala:87:24]
wire out_romask_261 = |_out_romask_T_261; // @[RegisterRouter.scala:87:24]
wire out_womask_261 = &_out_womask_T_261; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_261 = out_rivalid_1_115 & out_rimask_261; // @[RegisterRouter.scala:87:24]
wire _out_T_2968 = out_f_rivalid_261; // @[RegisterRouter.scala:87:24]
wire out_f_roready_261 = out_roready_1_115 & out_romask_261; // @[RegisterRouter.scala:87:24]
wire _out_T_2969 = out_f_roready_261; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_261 = out_wivalid_1_115 & out_wimask_261; // @[RegisterRouter.scala:87:24]
wire _out_T_2970 = out_f_wivalid_261; // @[RegisterRouter.scala:87:24]
wire out_f_woready_261 = out_woready_1_115 & out_womask_261; // @[RegisterRouter.scala:87:24]
wire _out_T_2971 = out_f_woready_261; // @[RegisterRouter.scala:87:24]
wire _out_T_2972 = ~out_rimask_261; // @[RegisterRouter.scala:87:24]
wire _out_T_2973 = ~out_wimask_261; // @[RegisterRouter.scala:87:24]
wire _out_T_2974 = ~out_romask_261; // @[RegisterRouter.scala:87:24]
wire _out_T_2975 = ~out_womask_261; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_212 = {programBufferMem_51, _out_prepend_T_212}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_2976 = out_prepend_212; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_2977 = _out_T_2976; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_213 = _out_T_2977; // @[RegisterRouter.scala:87:24]
wire out_rimask_262 = |_out_rimask_T_262; // @[RegisterRouter.scala:87:24]
wire out_wimask_262 = &_out_wimask_T_262; // @[RegisterRouter.scala:87:24]
wire out_romask_262 = |_out_romask_T_262; // @[RegisterRouter.scala:87:24]
wire out_womask_262 = &_out_womask_T_262; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_262 = out_rivalid_1_116 & out_rimask_262; // @[RegisterRouter.scala:87:24]
wire _out_T_2979 = out_f_rivalid_262; // @[RegisterRouter.scala:87:24]
wire out_f_roready_262 = out_roready_1_116 & out_romask_262; // @[RegisterRouter.scala:87:24]
wire _out_T_2980 = out_f_roready_262; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_262 = out_wivalid_1_116 & out_wimask_262; // @[RegisterRouter.scala:87:24]
wire _out_T_2981 = out_f_wivalid_262; // @[RegisterRouter.scala:87:24]
wire out_f_woready_262 = out_woready_1_116 & out_womask_262; // @[RegisterRouter.scala:87:24]
wire _out_T_2982 = out_f_woready_262; // @[RegisterRouter.scala:87:24]
wire _out_T_2983 = ~out_rimask_262; // @[RegisterRouter.scala:87:24]
wire _out_T_2984 = ~out_wimask_262; // @[RegisterRouter.scala:87:24]
wire _out_T_2985 = ~out_romask_262; // @[RegisterRouter.scala:87:24]
wire _out_T_2986 = ~out_womask_262; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_213 = {programBufferMem_52, _out_prepend_T_213}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_2987 = out_prepend_213; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_2988 = _out_T_2987; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_214 = _out_T_2988; // @[RegisterRouter.scala:87:24]
wire out_rimask_263 = |_out_rimask_T_263; // @[RegisterRouter.scala:87:24]
wire out_wimask_263 = &_out_wimask_T_263; // @[RegisterRouter.scala:87:24]
wire out_romask_263 = |_out_romask_T_263; // @[RegisterRouter.scala:87:24]
wire out_womask_263 = &_out_womask_T_263; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_263 = out_rivalid_1_117 & out_rimask_263; // @[RegisterRouter.scala:87:24]
wire _out_T_2990 = out_f_rivalid_263; // @[RegisterRouter.scala:87:24]
wire out_f_roready_263 = out_roready_1_117 & out_romask_263; // @[RegisterRouter.scala:87:24]
wire _out_T_2991 = out_f_roready_263; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_263 = out_wivalid_1_117 & out_wimask_263; // @[RegisterRouter.scala:87:24]
wire _out_T_2992 = out_f_wivalid_263; // @[RegisterRouter.scala:87:24]
wire out_f_woready_263 = out_woready_1_117 & out_womask_263; // @[RegisterRouter.scala:87:24]
wire _out_T_2993 = out_f_woready_263; // @[RegisterRouter.scala:87:24]
wire _out_T_2994 = ~out_rimask_263; // @[RegisterRouter.scala:87:24]
wire _out_T_2995 = ~out_wimask_263; // @[RegisterRouter.scala:87:24]
wire _out_T_2996 = ~out_romask_263; // @[RegisterRouter.scala:87:24]
wire _out_T_2997 = ~out_womask_263; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_214 = {programBufferMem_53, _out_prepend_T_214}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_2998 = out_prepend_214; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_2999 = _out_T_2998; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_215 = _out_T_2999; // @[RegisterRouter.scala:87:24]
wire out_rimask_264 = |_out_rimask_T_264; // @[RegisterRouter.scala:87:24]
wire out_wimask_264 = &_out_wimask_T_264; // @[RegisterRouter.scala:87:24]
wire out_romask_264 = |_out_romask_T_264; // @[RegisterRouter.scala:87:24]
wire out_womask_264 = &_out_womask_T_264; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_264 = out_rivalid_1_118 & out_rimask_264; // @[RegisterRouter.scala:87:24]
wire _out_T_3001 = out_f_rivalid_264; // @[RegisterRouter.scala:87:24]
wire out_f_roready_264 = out_roready_1_118 & out_romask_264; // @[RegisterRouter.scala:87:24]
wire _out_T_3002 = out_f_roready_264; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_264 = out_wivalid_1_118 & out_wimask_264; // @[RegisterRouter.scala:87:24]
wire _out_T_3003 = out_f_wivalid_264; // @[RegisterRouter.scala:87:24]
wire out_f_woready_264 = out_woready_1_118 & out_womask_264; // @[RegisterRouter.scala:87:24]
wire _out_T_3004 = out_f_woready_264; // @[RegisterRouter.scala:87:24]
wire _out_T_3005 = ~out_rimask_264; // @[RegisterRouter.scala:87:24]
wire _out_T_3006 = ~out_wimask_264; // @[RegisterRouter.scala:87:24]
wire _out_T_3007 = ~out_romask_264; // @[RegisterRouter.scala:87:24]
wire _out_T_3008 = ~out_womask_264; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_215 = {programBufferMem_54, _out_prepend_T_215}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_3009 = out_prepend_215; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_3010 = _out_T_3009; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_216 = _out_T_3010; // @[RegisterRouter.scala:87:24]
wire out_rimask_265 = |_out_rimask_T_265; // @[RegisterRouter.scala:87:24]
wire out_wimask_265 = &_out_wimask_T_265; // @[RegisterRouter.scala:87:24]
wire out_romask_265 = |_out_romask_T_265; // @[RegisterRouter.scala:87:24]
wire out_womask_265 = &_out_womask_T_265; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_265 = out_rivalid_1_119 & out_rimask_265; // @[RegisterRouter.scala:87:24]
wire _out_T_3012 = out_f_rivalid_265; // @[RegisterRouter.scala:87:24]
wire out_f_roready_265 = out_roready_1_119 & out_romask_265; // @[RegisterRouter.scala:87:24]
wire _out_T_3013 = out_f_roready_265; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_265 = out_wivalid_1_119 & out_wimask_265; // @[RegisterRouter.scala:87:24]
wire _out_T_3014 = out_f_wivalid_265; // @[RegisterRouter.scala:87:24]
wire out_f_woready_265 = out_woready_1_119 & out_womask_265; // @[RegisterRouter.scala:87:24]
wire _out_T_3015 = out_f_woready_265; // @[RegisterRouter.scala:87:24]
wire _out_T_3016 = ~out_rimask_265; // @[RegisterRouter.scala:87:24]
wire _out_T_3017 = ~out_wimask_265; // @[RegisterRouter.scala:87:24]
wire _out_T_3018 = ~out_romask_265; // @[RegisterRouter.scala:87:24]
wire _out_T_3019 = ~out_womask_265; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_216 = {programBufferMem_55, _out_prepend_T_216}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_3020 = out_prepend_216; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_3021 = _out_T_3020; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_110 = _out_T_3021; // @[MuxLiteral.scala:49:48]
wire out_rimask_266 = |_out_rimask_T_266; // @[RegisterRouter.scala:87:24]
wire out_wimask_266 = &_out_wimask_T_266; // @[RegisterRouter.scala:87:24]
wire out_romask_266 = |_out_romask_T_266; // @[RegisterRouter.scala:87:24]
wire out_womask_266 = &_out_womask_T_266; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_266 = out_rivalid_1_120 & out_rimask_266; // @[RegisterRouter.scala:87:24]
wire _out_T_3023 = out_f_rivalid_266; // @[RegisterRouter.scala:87:24]
wire out_f_roready_266 = out_roready_1_120 & out_romask_266; // @[RegisterRouter.scala:87:24]
wire _out_T_3024 = out_f_roready_266; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_266 = out_wivalid_1_120 & out_wimask_266; // @[RegisterRouter.scala:87:24]
wire out_f_woready_266 = out_woready_1_120 & out_womask_266; // @[RegisterRouter.scala:87:24]
wire _out_T_3025 = ~out_rimask_266; // @[RegisterRouter.scala:87:24]
wire _out_T_3026 = ~out_wimask_266; // @[RegisterRouter.scala:87:24]
wire _out_T_3027 = ~out_romask_266; // @[RegisterRouter.scala:87:24]
wire _out_T_3028 = ~out_womask_266; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3030 = _out_T_3029; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_217 = _out_T_3030; // @[RegisterRouter.scala:87:24]
wire out_rimask_267 = |_out_rimask_T_267; // @[RegisterRouter.scala:87:24]
wire out_wimask_267 = &_out_wimask_T_267; // @[RegisterRouter.scala:87:24]
wire out_romask_267 = |_out_romask_T_267; // @[RegisterRouter.scala:87:24]
wire out_womask_267 = &_out_womask_T_267; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_267 = out_rivalid_1_121 & out_rimask_267; // @[RegisterRouter.scala:87:24]
wire _out_T_3032 = out_f_rivalid_267; // @[RegisterRouter.scala:87:24]
wire out_f_roready_267 = out_roready_1_121 & out_romask_267; // @[RegisterRouter.scala:87:24]
wire _out_T_3033 = out_f_roready_267; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_267 = out_wivalid_1_121 & out_wimask_267; // @[RegisterRouter.scala:87:24]
wire out_f_woready_267 = out_woready_1_121 & out_womask_267; // @[RegisterRouter.scala:87:24]
wire _out_T_3034 = ~out_rimask_267; // @[RegisterRouter.scala:87:24]
wire _out_T_3035 = ~out_wimask_267; // @[RegisterRouter.scala:87:24]
wire _out_T_3036 = ~out_romask_267; // @[RegisterRouter.scala:87:24]
wire _out_T_3037 = ~out_womask_267; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_217 = {hi_546, flags_0_go, _out_prepend_T_217}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_3038 = out_prepend_217; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_3039 = _out_T_3038; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_218 = _out_T_3039; // @[RegisterRouter.scala:87:24]
wire out_rimask_268 = |_out_rimask_T_268; // @[RegisterRouter.scala:87:24]
wire out_wimask_268 = &_out_wimask_T_268; // @[RegisterRouter.scala:87:24]
wire out_romask_268 = |_out_romask_T_268; // @[RegisterRouter.scala:87:24]
wire out_womask_268 = &_out_womask_T_268; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_268 = out_rivalid_1_122 & out_rimask_268; // @[RegisterRouter.scala:87:24]
wire _out_T_3041 = out_f_rivalid_268; // @[RegisterRouter.scala:87:24]
wire out_f_roready_268 = out_roready_1_122 & out_romask_268; // @[RegisterRouter.scala:87:24]
wire _out_T_3042 = out_f_roready_268; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_268 = out_wivalid_1_122 & out_wimask_268; // @[RegisterRouter.scala:87:24]
wire out_f_woready_268 = out_woready_1_122 & out_womask_268; // @[RegisterRouter.scala:87:24]
wire _out_T_3043 = ~out_rimask_268; // @[RegisterRouter.scala:87:24]
wire _out_T_3044 = ~out_wimask_268; // @[RegisterRouter.scala:87:24]
wire _out_T_3045 = ~out_romask_268; // @[RegisterRouter.scala:87:24]
wire _out_T_3046 = ~out_womask_268; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_218 = {hi_547, flags_0_go, _out_prepend_T_218}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_3047 = out_prepend_218; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_3048 = _out_T_3047; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_219 = _out_T_3048; // @[RegisterRouter.scala:87:24]
wire out_rimask_269 = |_out_rimask_T_269; // @[RegisterRouter.scala:87:24]
wire out_wimask_269 = &_out_wimask_T_269; // @[RegisterRouter.scala:87:24]
wire out_romask_269 = |_out_romask_T_269; // @[RegisterRouter.scala:87:24]
wire out_womask_269 = &_out_womask_T_269; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_269 = out_rivalid_1_123 & out_rimask_269; // @[RegisterRouter.scala:87:24]
wire _out_T_3050 = out_f_rivalid_269; // @[RegisterRouter.scala:87:24]
wire out_f_roready_269 = out_roready_1_123 & out_romask_269; // @[RegisterRouter.scala:87:24]
wire _out_T_3051 = out_f_roready_269; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_269 = out_wivalid_1_123 & out_wimask_269; // @[RegisterRouter.scala:87:24]
wire out_f_woready_269 = out_woready_1_123 & out_womask_269; // @[RegisterRouter.scala:87:24]
wire _out_T_3052 = ~out_rimask_269; // @[RegisterRouter.scala:87:24]
wire _out_T_3053 = ~out_wimask_269; // @[RegisterRouter.scala:87:24]
wire _out_T_3054 = ~out_romask_269; // @[RegisterRouter.scala:87:24]
wire _out_T_3055 = ~out_womask_269; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_219 = {hi_548, flags_0_go, _out_prepend_T_219}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_3056 = out_prepend_219; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_3057 = _out_T_3056; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_220 = _out_T_3057; // @[RegisterRouter.scala:87:24]
wire out_rimask_270 = |_out_rimask_T_270; // @[RegisterRouter.scala:87:24]
wire out_wimask_270 = &_out_wimask_T_270; // @[RegisterRouter.scala:87:24]
wire out_romask_270 = |_out_romask_T_270; // @[RegisterRouter.scala:87:24]
wire out_womask_270 = &_out_womask_T_270; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_270 = out_rivalid_1_124 & out_rimask_270; // @[RegisterRouter.scala:87:24]
wire _out_T_3059 = out_f_rivalid_270; // @[RegisterRouter.scala:87:24]
wire out_f_roready_270 = out_roready_1_124 & out_romask_270; // @[RegisterRouter.scala:87:24]
wire _out_T_3060 = out_f_roready_270; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_270 = out_wivalid_1_124 & out_wimask_270; // @[RegisterRouter.scala:87:24]
wire out_f_woready_270 = out_woready_1_124 & out_womask_270; // @[RegisterRouter.scala:87:24]
wire _out_T_3061 = ~out_rimask_270; // @[RegisterRouter.scala:87:24]
wire _out_T_3062 = ~out_wimask_270; // @[RegisterRouter.scala:87:24]
wire _out_T_3063 = ~out_romask_270; // @[RegisterRouter.scala:87:24]
wire _out_T_3064 = ~out_womask_270; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_220 = {hi_549, flags_0_go, _out_prepend_T_220}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_3065 = out_prepend_220; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_3066 = _out_T_3065; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_221 = _out_T_3066; // @[RegisterRouter.scala:87:24]
wire out_rimask_271 = |_out_rimask_T_271; // @[RegisterRouter.scala:87:24]
wire out_wimask_271 = &_out_wimask_T_271; // @[RegisterRouter.scala:87:24]
wire out_romask_271 = |_out_romask_T_271; // @[RegisterRouter.scala:87:24]
wire out_womask_271 = &_out_womask_T_271; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_271 = out_rivalid_1_125 & out_rimask_271; // @[RegisterRouter.scala:87:24]
wire _out_T_3068 = out_f_rivalid_271; // @[RegisterRouter.scala:87:24]
wire out_f_roready_271 = out_roready_1_125 & out_romask_271; // @[RegisterRouter.scala:87:24]
wire _out_T_3069 = out_f_roready_271; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_271 = out_wivalid_1_125 & out_wimask_271; // @[RegisterRouter.scala:87:24]
wire out_f_woready_271 = out_woready_1_125 & out_womask_271; // @[RegisterRouter.scala:87:24]
wire _out_T_3070 = ~out_rimask_271; // @[RegisterRouter.scala:87:24]
wire _out_T_3071 = ~out_wimask_271; // @[RegisterRouter.scala:87:24]
wire _out_T_3072 = ~out_romask_271; // @[RegisterRouter.scala:87:24]
wire _out_T_3073 = ~out_womask_271; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_221 = {hi_550, flags_0_go, _out_prepend_T_221}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_3074 = out_prepend_221; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_3075 = _out_T_3074; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_222 = _out_T_3075; // @[RegisterRouter.scala:87:24]
wire out_rimask_272 = |_out_rimask_T_272; // @[RegisterRouter.scala:87:24]
wire out_wimask_272 = &_out_wimask_T_272; // @[RegisterRouter.scala:87:24]
wire out_romask_272 = |_out_romask_T_272; // @[RegisterRouter.scala:87:24]
wire out_womask_272 = &_out_womask_T_272; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_272 = out_rivalid_1_126 & out_rimask_272; // @[RegisterRouter.scala:87:24]
wire _out_T_3077 = out_f_rivalid_272; // @[RegisterRouter.scala:87:24]
wire out_f_roready_272 = out_roready_1_126 & out_romask_272; // @[RegisterRouter.scala:87:24]
wire _out_T_3078 = out_f_roready_272; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_272 = out_wivalid_1_126 & out_wimask_272; // @[RegisterRouter.scala:87:24]
wire out_f_woready_272 = out_woready_1_126 & out_womask_272; // @[RegisterRouter.scala:87:24]
wire _out_T_3079 = ~out_rimask_272; // @[RegisterRouter.scala:87:24]
wire _out_T_3080 = ~out_wimask_272; // @[RegisterRouter.scala:87:24]
wire _out_T_3081 = ~out_romask_272; // @[RegisterRouter.scala:87:24]
wire _out_T_3082 = ~out_womask_272; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_222 = {hi_551, flags_0_go, _out_prepend_T_222}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_3083 = out_prepend_222; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_3084 = _out_T_3083; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_223 = _out_T_3084; // @[RegisterRouter.scala:87:24]
wire out_rimask_273 = |_out_rimask_T_273; // @[RegisterRouter.scala:87:24]
wire out_wimask_273 = &_out_wimask_T_273; // @[RegisterRouter.scala:87:24]
wire out_romask_273 = |_out_romask_T_273; // @[RegisterRouter.scala:87:24]
wire out_womask_273 = &_out_womask_T_273; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_273 = out_rivalid_1_127 & out_rimask_273; // @[RegisterRouter.scala:87:24]
wire _out_T_3086 = out_f_rivalid_273; // @[RegisterRouter.scala:87:24]
wire out_f_roready_273 = out_roready_1_127 & out_romask_273; // @[RegisterRouter.scala:87:24]
wire _out_T_3087 = out_f_roready_273; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_273 = out_wivalid_1_127 & out_wimask_273; // @[RegisterRouter.scala:87:24]
wire out_f_woready_273 = out_woready_1_127 & out_womask_273; // @[RegisterRouter.scala:87:24]
wire _out_T_3088 = ~out_rimask_273; // @[RegisterRouter.scala:87:24]
wire _out_T_3089 = ~out_wimask_273; // @[RegisterRouter.scala:87:24]
wire _out_T_3090 = ~out_romask_273; // @[RegisterRouter.scala:87:24]
wire _out_T_3091 = ~out_womask_273; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_223 = {hi_552, flags_0_go, _out_prepend_T_223}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_3092 = out_prepend_223; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_3093 = _out_T_3092; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_196 = _out_T_3093; // @[MuxLiteral.scala:49:48]
wire out_rimask_274 = |_out_rimask_T_274; // @[RegisterRouter.scala:87:24]
wire out_wimask_274 = &_out_wimask_T_274; // @[RegisterRouter.scala:87:24]
wire out_romask_274 = |_out_romask_T_274; // @[RegisterRouter.scala:87:24]
wire out_womask_274 = &_out_womask_T_274; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_274 = out_rivalid_1_128 & out_rimask_274; // @[RegisterRouter.scala:87:24]
wire _out_T_3095 = out_f_rivalid_274; // @[RegisterRouter.scala:87:24]
wire out_f_roready_274 = out_roready_1_128 & out_romask_274; // @[RegisterRouter.scala:87:24]
wire _out_T_3096 = out_f_roready_274; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_274 = out_wivalid_1_128 & out_wimask_274; // @[RegisterRouter.scala:87:24]
wire out_f_woready_274 = out_woready_1_128 & out_womask_274; // @[RegisterRouter.scala:87:24]
wire _out_T_3097 = ~out_rimask_274; // @[RegisterRouter.scala:87:24]
wire _out_T_3098 = ~out_wimask_274; // @[RegisterRouter.scala:87:24]
wire _out_T_3099 = ~out_romask_274; // @[RegisterRouter.scala:87:24]
wire _out_T_3100 = ~out_womask_274; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3102 = _out_T_3101; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_224 = _out_T_3102; // @[RegisterRouter.scala:87:24]
wire out_rimask_275 = |_out_rimask_T_275; // @[RegisterRouter.scala:87:24]
wire out_wimask_275 = &_out_wimask_T_275; // @[RegisterRouter.scala:87:24]
wire out_romask_275 = |_out_romask_T_275; // @[RegisterRouter.scala:87:24]
wire out_womask_275 = &_out_womask_T_275; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_275 = out_rivalid_1_129 & out_rimask_275; // @[RegisterRouter.scala:87:24]
wire _out_T_3104 = out_f_rivalid_275; // @[RegisterRouter.scala:87:24]
wire out_f_roready_275 = out_roready_1_129 & out_romask_275; // @[RegisterRouter.scala:87:24]
wire _out_T_3105 = out_f_roready_275; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_275 = out_wivalid_1_129 & out_wimask_275; // @[RegisterRouter.scala:87:24]
wire out_f_woready_275 = out_woready_1_129 & out_womask_275; // @[RegisterRouter.scala:87:24]
wire _out_T_3106 = ~out_rimask_275; // @[RegisterRouter.scala:87:24]
wire _out_T_3107 = ~out_wimask_275; // @[RegisterRouter.scala:87:24]
wire _out_T_3108 = ~out_romask_275; // @[RegisterRouter.scala:87:24]
wire _out_T_3109 = ~out_womask_275; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_224 = {hi_234, flags_0_go, _out_prepend_T_224}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_3110 = out_prepend_224; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_3111 = _out_T_3110; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_225 = _out_T_3111; // @[RegisterRouter.scala:87:24]
wire out_rimask_276 = |_out_rimask_T_276; // @[RegisterRouter.scala:87:24]
wire out_wimask_276 = &_out_wimask_T_276; // @[RegisterRouter.scala:87:24]
wire out_romask_276 = |_out_romask_T_276; // @[RegisterRouter.scala:87:24]
wire out_womask_276 = &_out_womask_T_276; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_276 = out_rivalid_1_130 & out_rimask_276; // @[RegisterRouter.scala:87:24]
wire _out_T_3113 = out_f_rivalid_276; // @[RegisterRouter.scala:87:24]
wire out_f_roready_276 = out_roready_1_130 & out_romask_276; // @[RegisterRouter.scala:87:24]
wire _out_T_3114 = out_f_roready_276; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_276 = out_wivalid_1_130 & out_wimask_276; // @[RegisterRouter.scala:87:24]
wire out_f_woready_276 = out_woready_1_130 & out_womask_276; // @[RegisterRouter.scala:87:24]
wire _out_T_3115 = ~out_rimask_276; // @[RegisterRouter.scala:87:24]
wire _out_T_3116 = ~out_wimask_276; // @[RegisterRouter.scala:87:24]
wire _out_T_3117 = ~out_romask_276; // @[RegisterRouter.scala:87:24]
wire _out_T_3118 = ~out_womask_276; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_225 = {hi_235, flags_0_go, _out_prepend_T_225}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_3119 = out_prepend_225; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_3120 = _out_T_3119; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_226 = _out_T_3120; // @[RegisterRouter.scala:87:24]
wire out_rimask_277 = |_out_rimask_T_277; // @[RegisterRouter.scala:87:24]
wire out_wimask_277 = &_out_wimask_T_277; // @[RegisterRouter.scala:87:24]
wire out_romask_277 = |_out_romask_T_277; // @[RegisterRouter.scala:87:24]
wire out_womask_277 = &_out_womask_T_277; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_277 = out_rivalid_1_131 & out_rimask_277; // @[RegisterRouter.scala:87:24]
wire _out_T_3122 = out_f_rivalid_277; // @[RegisterRouter.scala:87:24]
wire out_f_roready_277 = out_roready_1_131 & out_romask_277; // @[RegisterRouter.scala:87:24]
wire _out_T_3123 = out_f_roready_277; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_277 = out_wivalid_1_131 & out_wimask_277; // @[RegisterRouter.scala:87:24]
wire out_f_woready_277 = out_woready_1_131 & out_womask_277; // @[RegisterRouter.scala:87:24]
wire _out_T_3124 = ~out_rimask_277; // @[RegisterRouter.scala:87:24]
wire _out_T_3125 = ~out_wimask_277; // @[RegisterRouter.scala:87:24]
wire _out_T_3126 = ~out_romask_277; // @[RegisterRouter.scala:87:24]
wire _out_T_3127 = ~out_womask_277; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_226 = {hi_236, flags_0_go, _out_prepend_T_226}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_3128 = out_prepend_226; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_3129 = _out_T_3128; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_227 = _out_T_3129; // @[RegisterRouter.scala:87:24]
wire out_rimask_278 = |_out_rimask_T_278; // @[RegisterRouter.scala:87:24]
wire out_wimask_278 = &_out_wimask_T_278; // @[RegisterRouter.scala:87:24]
wire out_romask_278 = |_out_romask_T_278; // @[RegisterRouter.scala:87:24]
wire out_womask_278 = &_out_womask_T_278; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_278 = out_rivalid_1_132 & out_rimask_278; // @[RegisterRouter.scala:87:24]
wire _out_T_3131 = out_f_rivalid_278; // @[RegisterRouter.scala:87:24]
wire out_f_roready_278 = out_roready_1_132 & out_romask_278; // @[RegisterRouter.scala:87:24]
wire _out_T_3132 = out_f_roready_278; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_278 = out_wivalid_1_132 & out_wimask_278; // @[RegisterRouter.scala:87:24]
wire out_f_woready_278 = out_woready_1_132 & out_womask_278; // @[RegisterRouter.scala:87:24]
wire _out_T_3133 = ~out_rimask_278; // @[RegisterRouter.scala:87:24]
wire _out_T_3134 = ~out_wimask_278; // @[RegisterRouter.scala:87:24]
wire _out_T_3135 = ~out_romask_278; // @[RegisterRouter.scala:87:24]
wire _out_T_3136 = ~out_womask_278; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_227 = {hi_237, flags_0_go, _out_prepend_T_227}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_3137 = out_prepend_227; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_3138 = _out_T_3137; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_228 = _out_T_3138; // @[RegisterRouter.scala:87:24]
wire out_rimask_279 = |_out_rimask_T_279; // @[RegisterRouter.scala:87:24]
wire out_wimask_279 = &_out_wimask_T_279; // @[RegisterRouter.scala:87:24]
wire out_romask_279 = |_out_romask_T_279; // @[RegisterRouter.scala:87:24]
wire out_womask_279 = &_out_womask_T_279; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_279 = out_rivalid_1_133 & out_rimask_279; // @[RegisterRouter.scala:87:24]
wire _out_T_3140 = out_f_rivalid_279; // @[RegisterRouter.scala:87:24]
wire out_f_roready_279 = out_roready_1_133 & out_romask_279; // @[RegisterRouter.scala:87:24]
wire _out_T_3141 = out_f_roready_279; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_279 = out_wivalid_1_133 & out_wimask_279; // @[RegisterRouter.scala:87:24]
wire out_f_woready_279 = out_woready_1_133 & out_womask_279; // @[RegisterRouter.scala:87:24]
wire _out_T_3142 = ~out_rimask_279; // @[RegisterRouter.scala:87:24]
wire _out_T_3143 = ~out_wimask_279; // @[RegisterRouter.scala:87:24]
wire _out_T_3144 = ~out_romask_279; // @[RegisterRouter.scala:87:24]
wire _out_T_3145 = ~out_womask_279; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_228 = {hi_238, flags_0_go, _out_prepend_T_228}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_3146 = out_prepend_228; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_3147 = _out_T_3146; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_229 = _out_T_3147; // @[RegisterRouter.scala:87:24]
wire out_rimask_280 = |_out_rimask_T_280; // @[RegisterRouter.scala:87:24]
wire out_wimask_280 = &_out_wimask_T_280; // @[RegisterRouter.scala:87:24]
wire out_romask_280 = |_out_romask_T_280; // @[RegisterRouter.scala:87:24]
wire out_womask_280 = &_out_womask_T_280; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_280 = out_rivalid_1_134 & out_rimask_280; // @[RegisterRouter.scala:87:24]
wire _out_T_3149 = out_f_rivalid_280; // @[RegisterRouter.scala:87:24]
wire out_f_roready_280 = out_roready_1_134 & out_romask_280; // @[RegisterRouter.scala:87:24]
wire _out_T_3150 = out_f_roready_280; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_280 = out_wivalid_1_134 & out_wimask_280; // @[RegisterRouter.scala:87:24]
wire out_f_woready_280 = out_woready_1_134 & out_womask_280; // @[RegisterRouter.scala:87:24]
wire _out_T_3151 = ~out_rimask_280; // @[RegisterRouter.scala:87:24]
wire _out_T_3152 = ~out_wimask_280; // @[RegisterRouter.scala:87:24]
wire _out_T_3153 = ~out_romask_280; // @[RegisterRouter.scala:87:24]
wire _out_T_3154 = ~out_womask_280; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_229 = {hi_239, flags_0_go, _out_prepend_T_229}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_3155 = out_prepend_229; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_3156 = _out_T_3155; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_230 = _out_T_3156; // @[RegisterRouter.scala:87:24]
wire out_rimask_281 = |_out_rimask_T_281; // @[RegisterRouter.scala:87:24]
wire out_wimask_281 = &_out_wimask_T_281; // @[RegisterRouter.scala:87:24]
wire out_romask_281 = |_out_romask_T_281; // @[RegisterRouter.scala:87:24]
wire out_womask_281 = &_out_womask_T_281; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_281 = out_rivalid_1_135 & out_rimask_281; // @[RegisterRouter.scala:87:24]
wire _out_T_3158 = out_f_rivalid_281; // @[RegisterRouter.scala:87:24]
wire out_f_roready_281 = out_roready_1_135 & out_romask_281; // @[RegisterRouter.scala:87:24]
wire _out_T_3159 = out_f_roready_281; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_281 = out_wivalid_1_135 & out_wimask_281; // @[RegisterRouter.scala:87:24]
wire out_f_woready_281 = out_woready_1_135 & out_womask_281; // @[RegisterRouter.scala:87:24]
wire _out_T_3160 = ~out_rimask_281; // @[RegisterRouter.scala:87:24]
wire _out_T_3161 = ~out_wimask_281; // @[RegisterRouter.scala:87:24]
wire _out_T_3162 = ~out_romask_281; // @[RegisterRouter.scala:87:24]
wire _out_T_3163 = ~out_womask_281; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_230 = {hi_240, flags_0_go, _out_prepend_T_230}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_3164 = out_prepend_230; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_3165 = _out_T_3164; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_157 = _out_T_3165; // @[MuxLiteral.scala:49:48]
wire out_rimask_282 = |_out_rimask_T_282; // @[RegisterRouter.scala:87:24]
wire out_wimask_282 = &_out_wimask_T_282; // @[RegisterRouter.scala:87:24]
wire out_romask_282 = |_out_romask_T_282; // @[RegisterRouter.scala:87:24]
wire out_womask_282 = &_out_womask_T_282; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_282 = out_rivalid_1_136 & out_rimask_282; // @[RegisterRouter.scala:87:24]
wire _out_T_3167 = out_f_rivalid_282; // @[RegisterRouter.scala:87:24]
wire out_f_roready_282 = out_roready_1_136 & out_romask_282; // @[RegisterRouter.scala:87:24]
wire _out_T_3168 = out_f_roready_282; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_282 = out_wivalid_1_136 & out_wimask_282; // @[RegisterRouter.scala:87:24]
wire out_f_woready_282 = out_woready_1_136 & out_womask_282; // @[RegisterRouter.scala:87:24]
wire _out_T_3169 = ~out_rimask_282; // @[RegisterRouter.scala:87:24]
wire _out_T_3170 = ~out_wimask_282; // @[RegisterRouter.scala:87:24]
wire _out_T_3171 = ~out_romask_282; // @[RegisterRouter.scala:87:24]
wire _out_T_3172 = ~out_womask_282; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3174 = _out_T_3173; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_231 = _out_T_3174; // @[RegisterRouter.scala:87:24]
wire out_rimask_283 = |_out_rimask_T_283; // @[RegisterRouter.scala:87:24]
wire out_wimask_283 = &_out_wimask_T_283; // @[RegisterRouter.scala:87:24]
wire out_romask_283 = |_out_romask_T_283; // @[RegisterRouter.scala:87:24]
wire out_womask_283 = &_out_womask_T_283; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_283 = out_rivalid_1_137 & out_rimask_283; // @[RegisterRouter.scala:87:24]
wire _out_T_3176 = out_f_rivalid_283; // @[RegisterRouter.scala:87:24]
wire out_f_roready_283 = out_roready_1_137 & out_romask_283; // @[RegisterRouter.scala:87:24]
wire _out_T_3177 = out_f_roready_283; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_283 = out_wivalid_1_137 & out_wimask_283; // @[RegisterRouter.scala:87:24]
wire out_f_woready_283 = out_woready_1_137 & out_womask_283; // @[RegisterRouter.scala:87:24]
wire _out_T_3178 = ~out_rimask_283; // @[RegisterRouter.scala:87:24]
wire _out_T_3179 = ~out_wimask_283; // @[RegisterRouter.scala:87:24]
wire _out_T_3180 = ~out_romask_283; // @[RegisterRouter.scala:87:24]
wire _out_T_3181 = ~out_womask_283; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_231 = {hi_490, flags_0_go, _out_prepend_T_231}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_3182 = out_prepend_231; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_3183 = _out_T_3182; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_232 = _out_T_3183; // @[RegisterRouter.scala:87:24]
wire out_rimask_284 = |_out_rimask_T_284; // @[RegisterRouter.scala:87:24]
wire out_wimask_284 = &_out_wimask_T_284; // @[RegisterRouter.scala:87:24]
wire out_romask_284 = |_out_romask_T_284; // @[RegisterRouter.scala:87:24]
wire out_womask_284 = &_out_womask_T_284; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_284 = out_rivalid_1_138 & out_rimask_284; // @[RegisterRouter.scala:87:24]
wire _out_T_3185 = out_f_rivalid_284; // @[RegisterRouter.scala:87:24]
wire out_f_roready_284 = out_roready_1_138 & out_romask_284; // @[RegisterRouter.scala:87:24]
wire _out_T_3186 = out_f_roready_284; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_284 = out_wivalid_1_138 & out_wimask_284; // @[RegisterRouter.scala:87:24]
wire out_f_woready_284 = out_woready_1_138 & out_womask_284; // @[RegisterRouter.scala:87:24]
wire _out_T_3187 = ~out_rimask_284; // @[RegisterRouter.scala:87:24]
wire _out_T_3188 = ~out_wimask_284; // @[RegisterRouter.scala:87:24]
wire _out_T_3189 = ~out_romask_284; // @[RegisterRouter.scala:87:24]
wire _out_T_3190 = ~out_womask_284; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_232 = {hi_491, flags_0_go, _out_prepend_T_232}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_3191 = out_prepend_232; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_3192 = _out_T_3191; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_233 = _out_T_3192; // @[RegisterRouter.scala:87:24]
wire out_rimask_285 = |_out_rimask_T_285; // @[RegisterRouter.scala:87:24]
wire out_wimask_285 = &_out_wimask_T_285; // @[RegisterRouter.scala:87:24]
wire out_romask_285 = |_out_romask_T_285; // @[RegisterRouter.scala:87:24]
wire out_womask_285 = &_out_womask_T_285; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_285 = out_rivalid_1_139 & out_rimask_285; // @[RegisterRouter.scala:87:24]
wire _out_T_3194 = out_f_rivalid_285; // @[RegisterRouter.scala:87:24]
wire out_f_roready_285 = out_roready_1_139 & out_romask_285; // @[RegisterRouter.scala:87:24]
wire _out_T_3195 = out_f_roready_285; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_285 = out_wivalid_1_139 & out_wimask_285; // @[RegisterRouter.scala:87:24]
wire out_f_woready_285 = out_woready_1_139 & out_womask_285; // @[RegisterRouter.scala:87:24]
wire _out_T_3196 = ~out_rimask_285; // @[RegisterRouter.scala:87:24]
wire _out_T_3197 = ~out_wimask_285; // @[RegisterRouter.scala:87:24]
wire _out_T_3198 = ~out_romask_285; // @[RegisterRouter.scala:87:24]
wire _out_T_3199 = ~out_womask_285; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_233 = {hi_492, flags_0_go, _out_prepend_T_233}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_3200 = out_prepend_233; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_3201 = _out_T_3200; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_234 = _out_T_3201; // @[RegisterRouter.scala:87:24]
wire out_rimask_286 = |_out_rimask_T_286; // @[RegisterRouter.scala:87:24]
wire out_wimask_286 = &_out_wimask_T_286; // @[RegisterRouter.scala:87:24]
wire out_romask_286 = |_out_romask_T_286; // @[RegisterRouter.scala:87:24]
wire out_womask_286 = &_out_womask_T_286; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_286 = out_rivalid_1_140 & out_rimask_286; // @[RegisterRouter.scala:87:24]
wire _out_T_3203 = out_f_rivalid_286; // @[RegisterRouter.scala:87:24]
wire out_f_roready_286 = out_roready_1_140 & out_romask_286; // @[RegisterRouter.scala:87:24]
wire _out_T_3204 = out_f_roready_286; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_286 = out_wivalid_1_140 & out_wimask_286; // @[RegisterRouter.scala:87:24]
wire out_f_woready_286 = out_woready_1_140 & out_womask_286; // @[RegisterRouter.scala:87:24]
wire _out_T_3205 = ~out_rimask_286; // @[RegisterRouter.scala:87:24]
wire _out_T_3206 = ~out_wimask_286; // @[RegisterRouter.scala:87:24]
wire _out_T_3207 = ~out_romask_286; // @[RegisterRouter.scala:87:24]
wire _out_T_3208 = ~out_womask_286; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_234 = {hi_493, flags_0_go, _out_prepend_T_234}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_3209 = out_prepend_234; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_3210 = _out_T_3209; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_235 = _out_T_3210; // @[RegisterRouter.scala:87:24]
wire out_rimask_287 = |_out_rimask_T_287; // @[RegisterRouter.scala:87:24]
wire out_wimask_287 = &_out_wimask_T_287; // @[RegisterRouter.scala:87:24]
wire out_romask_287 = |_out_romask_T_287; // @[RegisterRouter.scala:87:24]
wire out_womask_287 = &_out_womask_T_287; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_287 = out_rivalid_1_141 & out_rimask_287; // @[RegisterRouter.scala:87:24]
wire _out_T_3212 = out_f_rivalid_287; // @[RegisterRouter.scala:87:24]
wire out_f_roready_287 = out_roready_1_141 & out_romask_287; // @[RegisterRouter.scala:87:24]
wire _out_T_3213 = out_f_roready_287; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_287 = out_wivalid_1_141 & out_wimask_287; // @[RegisterRouter.scala:87:24]
wire out_f_woready_287 = out_woready_1_141 & out_womask_287; // @[RegisterRouter.scala:87:24]
wire _out_T_3214 = ~out_rimask_287; // @[RegisterRouter.scala:87:24]
wire _out_T_3215 = ~out_wimask_287; // @[RegisterRouter.scala:87:24]
wire _out_T_3216 = ~out_romask_287; // @[RegisterRouter.scala:87:24]
wire _out_T_3217 = ~out_womask_287; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_235 = {hi_494, flags_0_go, _out_prepend_T_235}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_3218 = out_prepend_235; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_3219 = _out_T_3218; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_236 = _out_T_3219; // @[RegisterRouter.scala:87:24]
wire out_rimask_288 = |_out_rimask_T_288; // @[RegisterRouter.scala:87:24]
wire out_wimask_288 = &_out_wimask_T_288; // @[RegisterRouter.scala:87:24]
wire out_romask_288 = |_out_romask_T_288; // @[RegisterRouter.scala:87:24]
wire out_womask_288 = &_out_womask_T_288; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_288 = out_rivalid_1_142 & out_rimask_288; // @[RegisterRouter.scala:87:24]
wire _out_T_3221 = out_f_rivalid_288; // @[RegisterRouter.scala:87:24]
wire out_f_roready_288 = out_roready_1_142 & out_romask_288; // @[RegisterRouter.scala:87:24]
wire _out_T_3222 = out_f_roready_288; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_288 = out_wivalid_1_142 & out_wimask_288; // @[RegisterRouter.scala:87:24]
wire out_f_woready_288 = out_woready_1_142 & out_womask_288; // @[RegisterRouter.scala:87:24]
wire _out_T_3223 = ~out_rimask_288; // @[RegisterRouter.scala:87:24]
wire _out_T_3224 = ~out_wimask_288; // @[RegisterRouter.scala:87:24]
wire _out_T_3225 = ~out_romask_288; // @[RegisterRouter.scala:87:24]
wire _out_T_3226 = ~out_womask_288; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_236 = {hi_495, flags_0_go, _out_prepend_T_236}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_3227 = out_prepend_236; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_3228 = _out_T_3227; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_237 = _out_T_3228; // @[RegisterRouter.scala:87:24]
wire out_rimask_289 = |_out_rimask_T_289; // @[RegisterRouter.scala:87:24]
wire out_wimask_289 = &_out_wimask_T_289; // @[RegisterRouter.scala:87:24]
wire out_romask_289 = |_out_romask_T_289; // @[RegisterRouter.scala:87:24]
wire out_womask_289 = &_out_womask_T_289; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_289 = out_rivalid_1_143 & out_rimask_289; // @[RegisterRouter.scala:87:24]
wire _out_T_3230 = out_f_rivalid_289; // @[RegisterRouter.scala:87:24]
wire out_f_roready_289 = out_roready_1_143 & out_romask_289; // @[RegisterRouter.scala:87:24]
wire _out_T_3231 = out_f_roready_289; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_289 = out_wivalid_1_143 & out_wimask_289; // @[RegisterRouter.scala:87:24]
wire out_f_woready_289 = out_woready_1_143 & out_womask_289; // @[RegisterRouter.scala:87:24]
wire _out_T_3232 = ~out_rimask_289; // @[RegisterRouter.scala:87:24]
wire _out_T_3233 = ~out_wimask_289; // @[RegisterRouter.scala:87:24]
wire _out_T_3234 = ~out_romask_289; // @[RegisterRouter.scala:87:24]
wire _out_T_3235 = ~out_womask_289; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_237 = {hi_496, flags_0_go, _out_prepend_T_237}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_3236 = out_prepend_237; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_3237 = _out_T_3236; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_189 = _out_T_3237; // @[MuxLiteral.scala:49:48]
wire out_rimask_290 = |_out_rimask_T_290; // @[RegisterRouter.scala:87:24]
wire out_wimask_290 = &_out_wimask_T_290; // @[RegisterRouter.scala:87:24]
wire out_romask_290 = |_out_romask_T_290; // @[RegisterRouter.scala:87:24]
wire out_womask_290 = &_out_womask_T_290; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_290 = out_rivalid_1_144 & out_rimask_290; // @[RegisterRouter.scala:87:24]
wire _out_T_3239 = out_f_rivalid_290; // @[RegisterRouter.scala:87:24]
wire out_f_roready_290 = out_roready_1_144 & out_romask_290; // @[RegisterRouter.scala:87:24]
wire _out_T_3240 = out_f_roready_290; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_290 = out_wivalid_1_144 & out_wimask_290; // @[RegisterRouter.scala:87:24]
wire out_f_woready_290 = out_woready_1_144 & out_womask_290; // @[RegisterRouter.scala:87:24]
wire _out_T_3241 = ~out_rimask_290; // @[RegisterRouter.scala:87:24]
wire _out_T_3242 = ~out_wimask_290; // @[RegisterRouter.scala:87:24]
wire _out_T_3243 = ~out_romask_290; // @[RegisterRouter.scala:87:24]
wire _out_T_3244 = ~out_womask_290; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3246 = _out_T_3245; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_238 = _out_T_3246; // @[RegisterRouter.scala:87:24]
wire out_rimask_291 = |_out_rimask_T_291; // @[RegisterRouter.scala:87:24]
wire out_wimask_291 = &_out_wimask_T_291; // @[RegisterRouter.scala:87:24]
wire out_romask_291 = |_out_romask_T_291; // @[RegisterRouter.scala:87:24]
wire out_womask_291 = &_out_womask_T_291; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_291 = out_rivalid_1_145 & out_rimask_291; // @[RegisterRouter.scala:87:24]
wire _out_T_3248 = out_f_rivalid_291; // @[RegisterRouter.scala:87:24]
wire out_f_roready_291 = out_roready_1_145 & out_romask_291; // @[RegisterRouter.scala:87:24]
wire _out_T_3249 = out_f_roready_291; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_291 = out_wivalid_1_145 & out_wimask_291; // @[RegisterRouter.scala:87:24]
wire out_f_woready_291 = out_woready_1_145 & out_womask_291; // @[RegisterRouter.scala:87:24]
wire _out_T_3250 = ~out_rimask_291; // @[RegisterRouter.scala:87:24]
wire _out_T_3251 = ~out_wimask_291; // @[RegisterRouter.scala:87:24]
wire _out_T_3252 = ~out_romask_291; // @[RegisterRouter.scala:87:24]
wire _out_T_3253 = ~out_womask_291; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_238 = {hi_194, flags_0_go, _out_prepend_T_238}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_3254 = out_prepend_238; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_3255 = _out_T_3254; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_239 = _out_T_3255; // @[RegisterRouter.scala:87:24]
wire out_rimask_292 = |_out_rimask_T_292; // @[RegisterRouter.scala:87:24]
wire out_wimask_292 = &_out_wimask_T_292; // @[RegisterRouter.scala:87:24]
wire out_romask_292 = |_out_romask_T_292; // @[RegisterRouter.scala:87:24]
wire out_womask_292 = &_out_womask_T_292; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_292 = out_rivalid_1_146 & out_rimask_292; // @[RegisterRouter.scala:87:24]
wire _out_T_3257 = out_f_rivalid_292; // @[RegisterRouter.scala:87:24]
wire out_f_roready_292 = out_roready_1_146 & out_romask_292; // @[RegisterRouter.scala:87:24]
wire _out_T_3258 = out_f_roready_292; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_292 = out_wivalid_1_146 & out_wimask_292; // @[RegisterRouter.scala:87:24]
wire out_f_woready_292 = out_woready_1_146 & out_womask_292; // @[RegisterRouter.scala:87:24]
wire _out_T_3259 = ~out_rimask_292; // @[RegisterRouter.scala:87:24]
wire _out_T_3260 = ~out_wimask_292; // @[RegisterRouter.scala:87:24]
wire _out_T_3261 = ~out_romask_292; // @[RegisterRouter.scala:87:24]
wire _out_T_3262 = ~out_womask_292; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_239 = {hi_195, flags_0_go, _out_prepend_T_239}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_3263 = out_prepend_239; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_3264 = _out_T_3263; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_240 = _out_T_3264; // @[RegisterRouter.scala:87:24]
wire out_rimask_293 = |_out_rimask_T_293; // @[RegisterRouter.scala:87:24]
wire out_wimask_293 = &_out_wimask_T_293; // @[RegisterRouter.scala:87:24]
wire out_romask_293 = |_out_romask_T_293; // @[RegisterRouter.scala:87:24]
wire out_womask_293 = &_out_womask_T_293; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_293 = out_rivalid_1_147 & out_rimask_293; // @[RegisterRouter.scala:87:24]
wire _out_T_3266 = out_f_rivalid_293; // @[RegisterRouter.scala:87:24]
wire out_f_roready_293 = out_roready_1_147 & out_romask_293; // @[RegisterRouter.scala:87:24]
wire _out_T_3267 = out_f_roready_293; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_293 = out_wivalid_1_147 & out_wimask_293; // @[RegisterRouter.scala:87:24]
wire out_f_woready_293 = out_woready_1_147 & out_womask_293; // @[RegisterRouter.scala:87:24]
wire _out_T_3268 = ~out_rimask_293; // @[RegisterRouter.scala:87:24]
wire _out_T_3269 = ~out_wimask_293; // @[RegisterRouter.scala:87:24]
wire _out_T_3270 = ~out_romask_293; // @[RegisterRouter.scala:87:24]
wire _out_T_3271 = ~out_womask_293; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_240 = {hi_196, flags_0_go, _out_prepend_T_240}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_3272 = out_prepend_240; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_3273 = _out_T_3272; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_241 = _out_T_3273; // @[RegisterRouter.scala:87:24]
wire out_rimask_294 = |_out_rimask_T_294; // @[RegisterRouter.scala:87:24]
wire out_wimask_294 = &_out_wimask_T_294; // @[RegisterRouter.scala:87:24]
wire out_romask_294 = |_out_romask_T_294; // @[RegisterRouter.scala:87:24]
wire out_womask_294 = &_out_womask_T_294; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_294 = out_rivalid_1_148 & out_rimask_294; // @[RegisterRouter.scala:87:24]
wire _out_T_3275 = out_f_rivalid_294; // @[RegisterRouter.scala:87:24]
wire out_f_roready_294 = out_roready_1_148 & out_romask_294; // @[RegisterRouter.scala:87:24]
wire _out_T_3276 = out_f_roready_294; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_294 = out_wivalid_1_148 & out_wimask_294; // @[RegisterRouter.scala:87:24]
wire out_f_woready_294 = out_woready_1_148 & out_womask_294; // @[RegisterRouter.scala:87:24]
wire _out_T_3277 = ~out_rimask_294; // @[RegisterRouter.scala:87:24]
wire _out_T_3278 = ~out_wimask_294; // @[RegisterRouter.scala:87:24]
wire _out_T_3279 = ~out_romask_294; // @[RegisterRouter.scala:87:24]
wire _out_T_3280 = ~out_womask_294; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_241 = {hi_197, flags_0_go, _out_prepend_T_241}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_3281 = out_prepend_241; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_3282 = _out_T_3281; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_242 = _out_T_3282; // @[RegisterRouter.scala:87:24]
wire out_rimask_295 = |_out_rimask_T_295; // @[RegisterRouter.scala:87:24]
wire out_wimask_295 = &_out_wimask_T_295; // @[RegisterRouter.scala:87:24]
wire out_romask_295 = |_out_romask_T_295; // @[RegisterRouter.scala:87:24]
wire out_womask_295 = &_out_womask_T_295; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_295 = out_rivalid_1_149 & out_rimask_295; // @[RegisterRouter.scala:87:24]
wire _out_T_3284 = out_f_rivalid_295; // @[RegisterRouter.scala:87:24]
wire out_f_roready_295 = out_roready_1_149 & out_romask_295; // @[RegisterRouter.scala:87:24]
wire _out_T_3285 = out_f_roready_295; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_295 = out_wivalid_1_149 & out_wimask_295; // @[RegisterRouter.scala:87:24]
wire out_f_woready_295 = out_woready_1_149 & out_womask_295; // @[RegisterRouter.scala:87:24]
wire _out_T_3286 = ~out_rimask_295; // @[RegisterRouter.scala:87:24]
wire _out_T_3287 = ~out_wimask_295; // @[RegisterRouter.scala:87:24]
wire _out_T_3288 = ~out_romask_295; // @[RegisterRouter.scala:87:24]
wire _out_T_3289 = ~out_womask_295; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_242 = {hi_198, flags_0_go, _out_prepend_T_242}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_3290 = out_prepend_242; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_3291 = _out_T_3290; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_243 = _out_T_3291; // @[RegisterRouter.scala:87:24]
wire out_rimask_296 = |_out_rimask_T_296; // @[RegisterRouter.scala:87:24]
wire out_wimask_296 = &_out_wimask_T_296; // @[RegisterRouter.scala:87:24]
wire out_romask_296 = |_out_romask_T_296; // @[RegisterRouter.scala:87:24]
wire out_womask_296 = &_out_womask_T_296; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_296 = out_rivalid_1_150 & out_rimask_296; // @[RegisterRouter.scala:87:24]
wire _out_T_3293 = out_f_rivalid_296; // @[RegisterRouter.scala:87:24]
wire out_f_roready_296 = out_roready_1_150 & out_romask_296; // @[RegisterRouter.scala:87:24]
wire _out_T_3294 = out_f_roready_296; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_296 = out_wivalid_1_150 & out_wimask_296; // @[RegisterRouter.scala:87:24]
wire out_f_woready_296 = out_woready_1_150 & out_womask_296; // @[RegisterRouter.scala:87:24]
wire _out_T_3295 = ~out_rimask_296; // @[RegisterRouter.scala:87:24]
wire _out_T_3296 = ~out_wimask_296; // @[RegisterRouter.scala:87:24]
wire _out_T_3297 = ~out_romask_296; // @[RegisterRouter.scala:87:24]
wire _out_T_3298 = ~out_womask_296; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_243 = {hi_199, flags_0_go, _out_prepend_T_243}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_3299 = out_prepend_243; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_3300 = _out_T_3299; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_244 = _out_T_3300; // @[RegisterRouter.scala:87:24]
wire out_rimask_297 = |_out_rimask_T_297; // @[RegisterRouter.scala:87:24]
wire out_wimask_297 = &_out_wimask_T_297; // @[RegisterRouter.scala:87:24]
wire out_romask_297 = |_out_romask_T_297; // @[RegisterRouter.scala:87:24]
wire out_womask_297 = &_out_womask_T_297; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_297 = out_rivalid_1_151 & out_rimask_297; // @[RegisterRouter.scala:87:24]
wire _out_T_3302 = out_f_rivalid_297; // @[RegisterRouter.scala:87:24]
wire out_f_roready_297 = out_roready_1_151 & out_romask_297; // @[RegisterRouter.scala:87:24]
wire _out_T_3303 = out_f_roready_297; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_297 = out_wivalid_1_151 & out_wimask_297; // @[RegisterRouter.scala:87:24]
wire out_f_woready_297 = out_woready_1_151 & out_womask_297; // @[RegisterRouter.scala:87:24]
wire _out_T_3304 = ~out_rimask_297; // @[RegisterRouter.scala:87:24]
wire _out_T_3305 = ~out_wimask_297; // @[RegisterRouter.scala:87:24]
wire _out_T_3306 = ~out_romask_297; // @[RegisterRouter.scala:87:24]
wire _out_T_3307 = ~out_womask_297; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_244 = {hi_200, flags_0_go, _out_prepend_T_244}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_3308 = out_prepend_244; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_3309 = _out_T_3308; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_152 = _out_T_3309; // @[MuxLiteral.scala:49:48]
wire out_rimask_298 = |_out_rimask_T_298; // @[RegisterRouter.scala:87:24]
wire out_wimask_298 = &_out_wimask_T_298; // @[RegisterRouter.scala:87:24]
wire out_romask_298 = |_out_romask_T_298; // @[RegisterRouter.scala:87:24]
wire out_womask_298 = &_out_womask_T_298; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_298 = out_rivalid_1_152 & out_rimask_298; // @[RegisterRouter.scala:87:24]
wire _out_T_3311 = out_f_rivalid_298; // @[RegisterRouter.scala:87:24]
wire out_f_roready_298 = out_roready_1_152 & out_romask_298; // @[RegisterRouter.scala:87:24]
wire _out_T_3312 = out_f_roready_298; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_298 = out_wivalid_1_152 & out_wimask_298; // @[RegisterRouter.scala:87:24]
wire out_f_woready_298 = out_woready_1_152 & out_womask_298; // @[RegisterRouter.scala:87:24]
wire _out_T_3313 = ~out_rimask_298; // @[RegisterRouter.scala:87:24]
wire _out_T_3314 = ~out_wimask_298; // @[RegisterRouter.scala:87:24]
wire _out_T_3315 = ~out_romask_298; // @[RegisterRouter.scala:87:24]
wire _out_T_3316 = ~out_womask_298; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3318 = _out_T_3317; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_245 = _out_T_3318; // @[RegisterRouter.scala:87:24]
wire out_rimask_299 = |_out_rimask_T_299; // @[RegisterRouter.scala:87:24]
wire out_wimask_299 = &_out_wimask_T_299; // @[RegisterRouter.scala:87:24]
wire out_romask_299 = |_out_romask_T_299; // @[RegisterRouter.scala:87:24]
wire out_womask_299 = &_out_womask_T_299; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_299 = out_rivalid_1_153 & out_rimask_299; // @[RegisterRouter.scala:87:24]
wire _out_T_3320 = out_f_rivalid_299; // @[RegisterRouter.scala:87:24]
wire out_f_roready_299 = out_roready_1_153 & out_romask_299; // @[RegisterRouter.scala:87:24]
wire _out_T_3321 = out_f_roready_299; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_299 = out_wivalid_1_153 & out_wimask_299; // @[RegisterRouter.scala:87:24]
wire out_f_woready_299 = out_woready_1_153 & out_womask_299; // @[RegisterRouter.scala:87:24]
wire _out_T_3322 = ~out_rimask_299; // @[RegisterRouter.scala:87:24]
wire _out_T_3323 = ~out_wimask_299; // @[RegisterRouter.scala:87:24]
wire _out_T_3324 = ~out_romask_299; // @[RegisterRouter.scala:87:24]
wire _out_T_3325 = ~out_womask_299; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_245 = {hi_802, flags_0_go, _out_prepend_T_245}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_3326 = out_prepend_245; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_3327 = _out_T_3326; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_246 = _out_T_3327; // @[RegisterRouter.scala:87:24]
wire out_rimask_300 = |_out_rimask_T_300; // @[RegisterRouter.scala:87:24]
wire out_wimask_300 = &_out_wimask_T_300; // @[RegisterRouter.scala:87:24]
wire out_romask_300 = |_out_romask_T_300; // @[RegisterRouter.scala:87:24]
wire out_womask_300 = &_out_womask_T_300; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_300 = out_rivalid_1_154 & out_rimask_300; // @[RegisterRouter.scala:87:24]
wire _out_T_3329 = out_f_rivalid_300; // @[RegisterRouter.scala:87:24]
wire out_f_roready_300 = out_roready_1_154 & out_romask_300; // @[RegisterRouter.scala:87:24]
wire _out_T_3330 = out_f_roready_300; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_300 = out_wivalid_1_154 & out_wimask_300; // @[RegisterRouter.scala:87:24]
wire out_f_woready_300 = out_woready_1_154 & out_womask_300; // @[RegisterRouter.scala:87:24]
wire _out_T_3331 = ~out_rimask_300; // @[RegisterRouter.scala:87:24]
wire _out_T_3332 = ~out_wimask_300; // @[RegisterRouter.scala:87:24]
wire _out_T_3333 = ~out_romask_300; // @[RegisterRouter.scala:87:24]
wire _out_T_3334 = ~out_womask_300; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_246 = {hi_803, flags_0_go, _out_prepend_T_246}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_3335 = out_prepend_246; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_3336 = _out_T_3335; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_247 = _out_T_3336; // @[RegisterRouter.scala:87:24]
wire out_rimask_301 = |_out_rimask_T_301; // @[RegisterRouter.scala:87:24]
wire out_wimask_301 = &_out_wimask_T_301; // @[RegisterRouter.scala:87:24]
wire out_romask_301 = |_out_romask_T_301; // @[RegisterRouter.scala:87:24]
wire out_womask_301 = &_out_womask_T_301; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_301 = out_rivalid_1_155 & out_rimask_301; // @[RegisterRouter.scala:87:24]
wire _out_T_3338 = out_f_rivalid_301; // @[RegisterRouter.scala:87:24]
wire out_f_roready_301 = out_roready_1_155 & out_romask_301; // @[RegisterRouter.scala:87:24]
wire _out_T_3339 = out_f_roready_301; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_301 = out_wivalid_1_155 & out_wimask_301; // @[RegisterRouter.scala:87:24]
wire out_f_woready_301 = out_woready_1_155 & out_womask_301; // @[RegisterRouter.scala:87:24]
wire _out_T_3340 = ~out_rimask_301; // @[RegisterRouter.scala:87:24]
wire _out_T_3341 = ~out_wimask_301; // @[RegisterRouter.scala:87:24]
wire _out_T_3342 = ~out_romask_301; // @[RegisterRouter.scala:87:24]
wire _out_T_3343 = ~out_womask_301; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_247 = {hi_804, flags_0_go, _out_prepend_T_247}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_3344 = out_prepend_247; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_3345 = _out_T_3344; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_248 = _out_T_3345; // @[RegisterRouter.scala:87:24]
wire out_rimask_302 = |_out_rimask_T_302; // @[RegisterRouter.scala:87:24]
wire out_wimask_302 = &_out_wimask_T_302; // @[RegisterRouter.scala:87:24]
wire out_romask_302 = |_out_romask_T_302; // @[RegisterRouter.scala:87:24]
wire out_womask_302 = &_out_womask_T_302; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_302 = out_rivalid_1_156 & out_rimask_302; // @[RegisterRouter.scala:87:24]
wire _out_T_3347 = out_f_rivalid_302; // @[RegisterRouter.scala:87:24]
wire out_f_roready_302 = out_roready_1_156 & out_romask_302; // @[RegisterRouter.scala:87:24]
wire _out_T_3348 = out_f_roready_302; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_302 = out_wivalid_1_156 & out_wimask_302; // @[RegisterRouter.scala:87:24]
wire out_f_woready_302 = out_woready_1_156 & out_womask_302; // @[RegisterRouter.scala:87:24]
wire _out_T_3349 = ~out_rimask_302; // @[RegisterRouter.scala:87:24]
wire _out_T_3350 = ~out_wimask_302; // @[RegisterRouter.scala:87:24]
wire _out_T_3351 = ~out_romask_302; // @[RegisterRouter.scala:87:24]
wire _out_T_3352 = ~out_womask_302; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_248 = {hi_805, flags_0_go, _out_prepend_T_248}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_3353 = out_prepend_248; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_3354 = _out_T_3353; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_249 = _out_T_3354; // @[RegisterRouter.scala:87:24]
wire out_rimask_303 = |_out_rimask_T_303; // @[RegisterRouter.scala:87:24]
wire out_wimask_303 = &_out_wimask_T_303; // @[RegisterRouter.scala:87:24]
wire out_romask_303 = |_out_romask_T_303; // @[RegisterRouter.scala:87:24]
wire out_womask_303 = &_out_womask_T_303; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_303 = out_rivalid_1_157 & out_rimask_303; // @[RegisterRouter.scala:87:24]
wire _out_T_3356 = out_f_rivalid_303; // @[RegisterRouter.scala:87:24]
wire out_f_roready_303 = out_roready_1_157 & out_romask_303; // @[RegisterRouter.scala:87:24]
wire _out_T_3357 = out_f_roready_303; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_303 = out_wivalid_1_157 & out_wimask_303; // @[RegisterRouter.scala:87:24]
wire out_f_woready_303 = out_woready_1_157 & out_womask_303; // @[RegisterRouter.scala:87:24]
wire _out_T_3358 = ~out_rimask_303; // @[RegisterRouter.scala:87:24]
wire _out_T_3359 = ~out_wimask_303; // @[RegisterRouter.scala:87:24]
wire _out_T_3360 = ~out_romask_303; // @[RegisterRouter.scala:87:24]
wire _out_T_3361 = ~out_womask_303; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_249 = {hi_806, flags_0_go, _out_prepend_T_249}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_3362 = out_prepend_249; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_3363 = _out_T_3362; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_250 = _out_T_3363; // @[RegisterRouter.scala:87:24]
wire out_rimask_304 = |_out_rimask_T_304; // @[RegisterRouter.scala:87:24]
wire out_wimask_304 = &_out_wimask_T_304; // @[RegisterRouter.scala:87:24]
wire out_romask_304 = |_out_romask_T_304; // @[RegisterRouter.scala:87:24]
wire out_womask_304 = &_out_womask_T_304; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_304 = out_rivalid_1_158 & out_rimask_304; // @[RegisterRouter.scala:87:24]
wire _out_T_3365 = out_f_rivalid_304; // @[RegisterRouter.scala:87:24]
wire out_f_roready_304 = out_roready_1_158 & out_romask_304; // @[RegisterRouter.scala:87:24]
wire _out_T_3366 = out_f_roready_304; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_304 = out_wivalid_1_158 & out_wimask_304; // @[RegisterRouter.scala:87:24]
wire out_f_woready_304 = out_woready_1_158 & out_womask_304; // @[RegisterRouter.scala:87:24]
wire _out_T_3367 = ~out_rimask_304; // @[RegisterRouter.scala:87:24]
wire _out_T_3368 = ~out_wimask_304; // @[RegisterRouter.scala:87:24]
wire _out_T_3369 = ~out_romask_304; // @[RegisterRouter.scala:87:24]
wire _out_T_3370 = ~out_womask_304; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_250 = {hi_807, flags_0_go, _out_prepend_T_250}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_3371 = out_prepend_250; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_3372 = _out_T_3371; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_251 = _out_T_3372; // @[RegisterRouter.scala:87:24]
wire out_rimask_305 = |_out_rimask_T_305; // @[RegisterRouter.scala:87:24]
wire out_wimask_305 = &_out_wimask_T_305; // @[RegisterRouter.scala:87:24]
wire out_romask_305 = |_out_romask_T_305; // @[RegisterRouter.scala:87:24]
wire out_womask_305 = &_out_womask_T_305; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_305 = out_rivalid_1_159 & out_rimask_305; // @[RegisterRouter.scala:87:24]
wire _out_T_3374 = out_f_rivalid_305; // @[RegisterRouter.scala:87:24]
wire out_f_roready_305 = out_roready_1_159 & out_romask_305; // @[RegisterRouter.scala:87:24]
wire _out_T_3375 = out_f_roready_305; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_305 = out_wivalid_1_159 & out_wimask_305; // @[RegisterRouter.scala:87:24]
wire out_f_woready_305 = out_woready_1_159 & out_womask_305; // @[RegisterRouter.scala:87:24]
wire _out_T_3376 = ~out_rimask_305; // @[RegisterRouter.scala:87:24]
wire _out_T_3377 = ~out_wimask_305; // @[RegisterRouter.scala:87:24]
wire _out_T_3378 = ~out_romask_305; // @[RegisterRouter.scala:87:24]
wire _out_T_3379 = ~out_womask_305; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_251 = {hi_808, flags_0_go, _out_prepend_T_251}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_3380 = out_prepend_251; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_3381 = _out_T_3380; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_228 = _out_T_3381; // @[MuxLiteral.scala:49:48]
wire out_rimask_306 = |_out_rimask_T_306; // @[RegisterRouter.scala:87:24]
wire out_wimask_306 = &_out_wimask_T_306; // @[RegisterRouter.scala:87:24]
wire out_romask_306 = |_out_romask_T_306; // @[RegisterRouter.scala:87:24]
wire out_womask_306 = &_out_womask_T_306; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_306 = out_rivalid_1_160 & out_rimask_306; // @[RegisterRouter.scala:87:24]
wire _out_T_3383 = out_f_rivalid_306; // @[RegisterRouter.scala:87:24]
wire out_f_roready_306 = out_roready_1_160 & out_romask_306; // @[RegisterRouter.scala:87:24]
wire _out_T_3384 = out_f_roready_306; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_306 = out_wivalid_1_160 & out_wimask_306; // @[RegisterRouter.scala:87:24]
wire out_f_woready_306 = out_woready_1_160 & out_womask_306; // @[RegisterRouter.scala:87:24]
wire _out_T_3385 = ~out_rimask_306; // @[RegisterRouter.scala:87:24]
wire _out_T_3386 = ~out_wimask_306; // @[RegisterRouter.scala:87:24]
wire _out_T_3387 = ~out_romask_306; // @[RegisterRouter.scala:87:24]
wire _out_T_3388 = ~out_womask_306; // @[RegisterRouter.scala:87:24]
wire out_rimask_307 = |_out_rimask_T_307; // @[RegisterRouter.scala:87:24]
wire out_wimask_307 = &_out_wimask_T_307; // @[RegisterRouter.scala:87:24]
wire out_romask_307 = |_out_romask_T_307; // @[RegisterRouter.scala:87:24]
wire out_womask_307 = &_out_womask_T_307; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_307 = out_rivalid_1_161 & out_rimask_307; // @[RegisterRouter.scala:87:24]
wire _out_T_3392 = out_f_rivalid_307; // @[RegisterRouter.scala:87:24]
wire out_f_roready_307 = out_roready_1_161 & out_romask_307; // @[RegisterRouter.scala:87:24]
wire _out_T_3393 = out_f_roready_307; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_307 = out_wivalid_1_161 & out_wimask_307; // @[RegisterRouter.scala:87:24]
wire out_f_woready_307 = out_woready_1_161 & out_womask_307; // @[RegisterRouter.scala:87:24]
wire _out_T_3394 = ~out_rimask_307; // @[RegisterRouter.scala:87:24]
wire _out_T_3395 = ~out_wimask_307; // @[RegisterRouter.scala:87:24]
wire _out_T_3396 = ~out_romask_307; // @[RegisterRouter.scala:87:24]
wire _out_T_3397 = ~out_womask_307; // @[RegisterRouter.scala:87:24]
wire out_rimask_308 = |_out_rimask_T_308; // @[RegisterRouter.scala:87:24]
wire out_wimask_308 = &_out_wimask_T_308; // @[RegisterRouter.scala:87:24]
wire out_romask_308 = |_out_romask_T_308; // @[RegisterRouter.scala:87:24]
wire out_womask_308 = &_out_womask_T_308; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_308 = out_rivalid_1_162 & out_rimask_308; // @[RegisterRouter.scala:87:24]
wire _out_T_3401 = out_f_rivalid_308; // @[RegisterRouter.scala:87:24]
wire out_f_roready_308 = out_roready_1_162 & out_romask_308; // @[RegisterRouter.scala:87:24]
wire _out_T_3402 = out_f_roready_308; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_308 = out_wivalid_1_162 & out_wimask_308; // @[RegisterRouter.scala:87:24]
wire out_f_woready_308 = out_woready_1_162 & out_womask_308; // @[RegisterRouter.scala:87:24]
wire _out_T_3403 = ~out_rimask_308; // @[RegisterRouter.scala:87:24]
wire _out_T_3404 = ~out_wimask_308; // @[RegisterRouter.scala:87:24]
wire _out_T_3405 = ~out_romask_308; // @[RegisterRouter.scala:87:24]
wire _out_T_3406 = ~out_womask_308; // @[RegisterRouter.scala:87:24]
wire out_rimask_309 = |_out_rimask_T_309; // @[RegisterRouter.scala:87:24]
wire out_wimask_309 = &_out_wimask_T_309; // @[RegisterRouter.scala:87:24]
wire out_romask_309 = |_out_romask_T_309; // @[RegisterRouter.scala:87:24]
wire out_womask_309 = &_out_womask_T_309; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_309 = out_rivalid_1_163 & out_rimask_309; // @[RegisterRouter.scala:87:24]
wire _out_T_3410 = out_f_rivalid_309; // @[RegisterRouter.scala:87:24]
wire out_f_roready_309 = out_roready_1_163 & out_romask_309; // @[RegisterRouter.scala:87:24]
wire _out_T_3411 = out_f_roready_309; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_309 = out_wivalid_1_163 & out_wimask_309; // @[RegisterRouter.scala:87:24]
wire out_f_woready_309 = out_woready_1_163 & out_womask_309; // @[RegisterRouter.scala:87:24]
wire _out_T_3412 = ~out_rimask_309; // @[RegisterRouter.scala:87:24]
wire _out_T_3413 = ~out_wimask_309; // @[RegisterRouter.scala:87:24]
wire _out_T_3414 = ~out_romask_309; // @[RegisterRouter.scala:87:24]
wire _out_T_3415 = ~out_womask_309; // @[RegisterRouter.scala:87:24]
wire out_rimask_310 = |_out_rimask_T_310; // @[RegisterRouter.scala:87:24]
wire out_wimask_310 = &_out_wimask_T_310; // @[RegisterRouter.scala:87:24]
wire out_romask_310 = |_out_romask_T_310; // @[RegisterRouter.scala:87:24]
wire out_womask_310 = &_out_womask_T_310; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_310 = out_rivalid_1_164 & out_rimask_310; // @[RegisterRouter.scala:87:24]
wire _out_T_3419 = out_f_rivalid_310; // @[RegisterRouter.scala:87:24]
wire out_f_roready_310 = out_roready_1_164 & out_romask_310; // @[RegisterRouter.scala:87:24]
wire _out_T_3420 = out_f_roready_310; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_310 = out_wivalid_1_164 & out_wimask_310; // @[RegisterRouter.scala:87:24]
wire out_f_woready_310 = out_woready_1_164 & out_womask_310; // @[RegisterRouter.scala:87:24]
wire _out_T_3421 = ~out_rimask_310; // @[RegisterRouter.scala:87:24]
wire _out_T_3422 = ~out_wimask_310; // @[RegisterRouter.scala:87:24]
wire _out_T_3423 = ~out_romask_310; // @[RegisterRouter.scala:87:24]
wire _out_T_3424 = ~out_womask_310; // @[RegisterRouter.scala:87:24]
wire out_rimask_311 = |_out_rimask_T_311; // @[RegisterRouter.scala:87:24]
wire out_wimask_311 = &_out_wimask_T_311; // @[RegisterRouter.scala:87:24]
wire out_romask_311 = |_out_romask_T_311; // @[RegisterRouter.scala:87:24]
wire out_womask_311 = &_out_womask_T_311; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_311 = out_rivalid_1_165 & out_rimask_311; // @[RegisterRouter.scala:87:24]
wire _out_T_3428 = out_f_rivalid_311; // @[RegisterRouter.scala:87:24]
wire out_f_roready_311 = out_roready_1_165 & out_romask_311; // @[RegisterRouter.scala:87:24]
wire _out_T_3429 = out_f_roready_311; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_311 = out_wivalid_1_165 & out_wimask_311; // @[RegisterRouter.scala:87:24]
wire out_f_woready_311 = out_woready_1_165 & out_womask_311; // @[RegisterRouter.scala:87:24]
wire _out_T_3430 = ~out_rimask_311; // @[RegisterRouter.scala:87:24]
wire _out_T_3431 = ~out_wimask_311; // @[RegisterRouter.scala:87:24]
wire _out_T_3432 = ~out_romask_311; // @[RegisterRouter.scala:87:24]
wire _out_T_3433 = ~out_womask_311; // @[RegisterRouter.scala:87:24]
wire out_rimask_312 = |_out_rimask_T_312; // @[RegisterRouter.scala:87:24]
wire out_wimask_312 = &_out_wimask_T_312; // @[RegisterRouter.scala:87:24]
wire out_romask_312 = |_out_romask_T_312; // @[RegisterRouter.scala:87:24]
wire out_womask_312 = &_out_womask_T_312; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_312 = out_rivalid_1_166 & out_rimask_312; // @[RegisterRouter.scala:87:24]
wire _out_T_3437 = out_f_rivalid_312; // @[RegisterRouter.scala:87:24]
wire out_f_roready_312 = out_roready_1_166 & out_romask_312; // @[RegisterRouter.scala:87:24]
wire _out_T_3438 = out_f_roready_312; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_312 = out_wivalid_1_166 & out_wimask_312; // @[RegisterRouter.scala:87:24]
wire out_f_woready_312 = out_woready_1_166 & out_womask_312; // @[RegisterRouter.scala:87:24]
wire _out_T_3439 = ~out_rimask_312; // @[RegisterRouter.scala:87:24]
wire _out_T_3440 = ~out_wimask_312; // @[RegisterRouter.scala:87:24]
wire _out_T_3441 = ~out_romask_312; // @[RegisterRouter.scala:87:24]
wire _out_T_3442 = ~out_womask_312; // @[RegisterRouter.scala:87:24]
wire out_rimask_313 = |_out_rimask_T_313; // @[RegisterRouter.scala:87:24]
wire out_wimask_313 = &_out_wimask_T_313; // @[RegisterRouter.scala:87:24]
wire out_romask_313 = |_out_romask_T_313; // @[RegisterRouter.scala:87:24]
wire out_womask_313 = &_out_womask_T_313; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_313 = out_rivalid_1_167 & out_rimask_313; // @[RegisterRouter.scala:87:24]
wire _out_T_3446 = out_f_rivalid_313; // @[RegisterRouter.scala:87:24]
wire out_f_roready_313 = out_roready_1_167 & out_romask_313; // @[RegisterRouter.scala:87:24]
wire _out_T_3447 = out_f_roready_313; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_313 = out_wivalid_1_167 & out_wimask_313; // @[RegisterRouter.scala:87:24]
wire out_f_woready_313 = out_woready_1_167 & out_womask_313; // @[RegisterRouter.scala:87:24]
wire _out_T_3448 = ~out_rimask_313; // @[RegisterRouter.scala:87:24]
wire _out_T_3449 = ~out_wimask_313; // @[RegisterRouter.scala:87:24]
wire _out_T_3450 = ~out_romask_313; // @[RegisterRouter.scala:87:24]
wire _out_T_3451 = ~out_womask_313; // @[RegisterRouter.scala:87:24]
wire out_rimask_314 = |_out_rimask_T_314; // @[RegisterRouter.scala:87:24]
wire out_wimask_314 = &_out_wimask_T_314; // @[RegisterRouter.scala:87:24]
wire out_romask_314 = |_out_romask_T_314; // @[RegisterRouter.scala:87:24]
wire out_womask_314 = &_out_womask_T_314; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_314 = out_rivalid_1_168 & out_rimask_314; // @[RegisterRouter.scala:87:24]
wire _out_T_3455 = out_f_rivalid_314; // @[RegisterRouter.scala:87:24]
wire out_f_roready_314 = out_roready_1_168 & out_romask_314; // @[RegisterRouter.scala:87:24]
wire _out_T_3456 = out_f_roready_314; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_314 = out_wivalid_1_168 & out_wimask_314; // @[RegisterRouter.scala:87:24]
wire out_f_woready_314 = out_woready_1_168 & out_womask_314; // @[RegisterRouter.scala:87:24]
wire _out_T_3457 = ~out_rimask_314; // @[RegisterRouter.scala:87:24]
wire _out_T_3458 = ~out_wimask_314; // @[RegisterRouter.scala:87:24]
wire _out_T_3459 = ~out_romask_314; // @[RegisterRouter.scala:87:24]
wire _out_T_3460 = ~out_womask_314; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3462 = _out_T_3461; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_259 = _out_T_3462; // @[RegisterRouter.scala:87:24]
wire out_rimask_315 = |_out_rimask_T_315; // @[RegisterRouter.scala:87:24]
wire out_wimask_315 = &_out_wimask_T_315; // @[RegisterRouter.scala:87:24]
wire out_romask_315 = |_out_romask_T_315; // @[RegisterRouter.scala:87:24]
wire out_womask_315 = &_out_womask_T_315; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_315 = out_rivalid_1_169 & out_rimask_315; // @[RegisterRouter.scala:87:24]
wire _out_T_3464 = out_f_rivalid_315; // @[RegisterRouter.scala:87:24]
wire out_f_roready_315 = out_roready_1_169 & out_romask_315; // @[RegisterRouter.scala:87:24]
wire _out_T_3465 = out_f_roready_315; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_315 = out_wivalid_1_169 & out_wimask_315; // @[RegisterRouter.scala:87:24]
wire out_f_woready_315 = out_woready_1_169 & out_womask_315; // @[RegisterRouter.scala:87:24]
wire _out_T_3466 = ~out_rimask_315; // @[RegisterRouter.scala:87:24]
wire _out_T_3467 = ~out_wimask_315; // @[RegisterRouter.scala:87:24]
wire _out_T_3468 = ~out_romask_315; // @[RegisterRouter.scala:87:24]
wire _out_T_3469 = ~out_womask_315; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_259 = {hi_706, flags_0_go, _out_prepend_T_259}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_3470 = out_prepend_259; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_3471 = _out_T_3470; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_260 = _out_T_3471; // @[RegisterRouter.scala:87:24]
wire out_rimask_316 = |_out_rimask_T_316; // @[RegisterRouter.scala:87:24]
wire out_wimask_316 = &_out_wimask_T_316; // @[RegisterRouter.scala:87:24]
wire out_romask_316 = |_out_romask_T_316; // @[RegisterRouter.scala:87:24]
wire out_womask_316 = &_out_womask_T_316; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_316 = out_rivalid_1_170 & out_rimask_316; // @[RegisterRouter.scala:87:24]
wire _out_T_3473 = out_f_rivalid_316; // @[RegisterRouter.scala:87:24]
wire out_f_roready_316 = out_roready_1_170 & out_romask_316; // @[RegisterRouter.scala:87:24]
wire _out_T_3474 = out_f_roready_316; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_316 = out_wivalid_1_170 & out_wimask_316; // @[RegisterRouter.scala:87:24]
wire out_f_woready_316 = out_woready_1_170 & out_womask_316; // @[RegisterRouter.scala:87:24]
wire _out_T_3475 = ~out_rimask_316; // @[RegisterRouter.scala:87:24]
wire _out_T_3476 = ~out_wimask_316; // @[RegisterRouter.scala:87:24]
wire _out_T_3477 = ~out_romask_316; // @[RegisterRouter.scala:87:24]
wire _out_T_3478 = ~out_womask_316; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_260 = {hi_707, flags_0_go, _out_prepend_T_260}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_3479 = out_prepend_260; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_3480 = _out_T_3479; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_261 = _out_T_3480; // @[RegisterRouter.scala:87:24]
wire out_rimask_317 = |_out_rimask_T_317; // @[RegisterRouter.scala:87:24]
wire out_wimask_317 = &_out_wimask_T_317; // @[RegisterRouter.scala:87:24]
wire out_romask_317 = |_out_romask_T_317; // @[RegisterRouter.scala:87:24]
wire out_womask_317 = &_out_womask_T_317; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_317 = out_rivalid_1_171 & out_rimask_317; // @[RegisterRouter.scala:87:24]
wire _out_T_3482 = out_f_rivalid_317; // @[RegisterRouter.scala:87:24]
wire out_f_roready_317 = out_roready_1_171 & out_romask_317; // @[RegisterRouter.scala:87:24]
wire _out_T_3483 = out_f_roready_317; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_317 = out_wivalid_1_171 & out_wimask_317; // @[RegisterRouter.scala:87:24]
wire out_f_woready_317 = out_woready_1_171 & out_womask_317; // @[RegisterRouter.scala:87:24]
wire _out_T_3484 = ~out_rimask_317; // @[RegisterRouter.scala:87:24]
wire _out_T_3485 = ~out_wimask_317; // @[RegisterRouter.scala:87:24]
wire _out_T_3486 = ~out_romask_317; // @[RegisterRouter.scala:87:24]
wire _out_T_3487 = ~out_womask_317; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_261 = {hi_708, flags_0_go, _out_prepend_T_261}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_3488 = out_prepend_261; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_3489 = _out_T_3488; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_262 = _out_T_3489; // @[RegisterRouter.scala:87:24]
wire out_rimask_318 = |_out_rimask_T_318; // @[RegisterRouter.scala:87:24]
wire out_wimask_318 = &_out_wimask_T_318; // @[RegisterRouter.scala:87:24]
wire out_romask_318 = |_out_romask_T_318; // @[RegisterRouter.scala:87:24]
wire out_womask_318 = &_out_womask_T_318; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_318 = out_rivalid_1_172 & out_rimask_318; // @[RegisterRouter.scala:87:24]
wire _out_T_3491 = out_f_rivalid_318; // @[RegisterRouter.scala:87:24]
wire out_f_roready_318 = out_roready_1_172 & out_romask_318; // @[RegisterRouter.scala:87:24]
wire _out_T_3492 = out_f_roready_318; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_318 = out_wivalid_1_172 & out_wimask_318; // @[RegisterRouter.scala:87:24]
wire out_f_woready_318 = out_woready_1_172 & out_womask_318; // @[RegisterRouter.scala:87:24]
wire _out_T_3493 = ~out_rimask_318; // @[RegisterRouter.scala:87:24]
wire _out_T_3494 = ~out_wimask_318; // @[RegisterRouter.scala:87:24]
wire _out_T_3495 = ~out_romask_318; // @[RegisterRouter.scala:87:24]
wire _out_T_3496 = ~out_womask_318; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_262 = {hi_709, flags_0_go, _out_prepend_T_262}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_3497 = out_prepend_262; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_3498 = _out_T_3497; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_263 = _out_T_3498; // @[RegisterRouter.scala:87:24]
wire out_rimask_319 = |_out_rimask_T_319; // @[RegisterRouter.scala:87:24]
wire out_wimask_319 = &_out_wimask_T_319; // @[RegisterRouter.scala:87:24]
wire out_romask_319 = |_out_romask_T_319; // @[RegisterRouter.scala:87:24]
wire out_womask_319 = &_out_womask_T_319; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_319 = out_rivalid_1_173 & out_rimask_319; // @[RegisterRouter.scala:87:24]
wire _out_T_3500 = out_f_rivalid_319; // @[RegisterRouter.scala:87:24]
wire out_f_roready_319 = out_roready_1_173 & out_romask_319; // @[RegisterRouter.scala:87:24]
wire _out_T_3501 = out_f_roready_319; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_319 = out_wivalid_1_173 & out_wimask_319; // @[RegisterRouter.scala:87:24]
wire out_f_woready_319 = out_woready_1_173 & out_womask_319; // @[RegisterRouter.scala:87:24]
wire _out_T_3502 = ~out_rimask_319; // @[RegisterRouter.scala:87:24]
wire _out_T_3503 = ~out_wimask_319; // @[RegisterRouter.scala:87:24]
wire _out_T_3504 = ~out_romask_319; // @[RegisterRouter.scala:87:24]
wire _out_T_3505 = ~out_womask_319; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_263 = {hi_710, flags_0_go, _out_prepend_T_263}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_3506 = out_prepend_263; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_3507 = _out_T_3506; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_264 = _out_T_3507; // @[RegisterRouter.scala:87:24]
wire out_rimask_320 = |_out_rimask_T_320; // @[RegisterRouter.scala:87:24]
wire out_wimask_320 = &_out_wimask_T_320; // @[RegisterRouter.scala:87:24]
wire out_romask_320 = |_out_romask_T_320; // @[RegisterRouter.scala:87:24]
wire out_womask_320 = &_out_womask_T_320; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_320 = out_rivalid_1_174 & out_rimask_320; // @[RegisterRouter.scala:87:24]
wire _out_T_3509 = out_f_rivalid_320; // @[RegisterRouter.scala:87:24]
wire out_f_roready_320 = out_roready_1_174 & out_romask_320; // @[RegisterRouter.scala:87:24]
wire _out_T_3510 = out_f_roready_320; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_320 = out_wivalid_1_174 & out_wimask_320; // @[RegisterRouter.scala:87:24]
wire out_f_woready_320 = out_woready_1_174 & out_womask_320; // @[RegisterRouter.scala:87:24]
wire _out_T_3511 = ~out_rimask_320; // @[RegisterRouter.scala:87:24]
wire _out_T_3512 = ~out_wimask_320; // @[RegisterRouter.scala:87:24]
wire _out_T_3513 = ~out_romask_320; // @[RegisterRouter.scala:87:24]
wire _out_T_3514 = ~out_womask_320; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_264 = {hi_711, flags_0_go, _out_prepend_T_264}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_3515 = out_prepend_264; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_3516 = _out_T_3515; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_265 = _out_T_3516; // @[RegisterRouter.scala:87:24]
wire out_rimask_321 = |_out_rimask_T_321; // @[RegisterRouter.scala:87:24]
wire out_wimask_321 = &_out_wimask_T_321; // @[RegisterRouter.scala:87:24]
wire out_romask_321 = |_out_romask_T_321; // @[RegisterRouter.scala:87:24]
wire out_womask_321 = &_out_womask_T_321; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_321 = out_rivalid_1_175 & out_rimask_321; // @[RegisterRouter.scala:87:24]
wire _out_T_3518 = out_f_rivalid_321; // @[RegisterRouter.scala:87:24]
wire out_f_roready_321 = out_roready_1_175 & out_romask_321; // @[RegisterRouter.scala:87:24]
wire _out_T_3519 = out_f_roready_321; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_321 = out_wivalid_1_175 & out_wimask_321; // @[RegisterRouter.scala:87:24]
wire out_f_woready_321 = out_woready_1_175 & out_womask_321; // @[RegisterRouter.scala:87:24]
wire _out_T_3520 = ~out_rimask_321; // @[RegisterRouter.scala:87:24]
wire _out_T_3521 = ~out_wimask_321; // @[RegisterRouter.scala:87:24]
wire _out_T_3522 = ~out_romask_321; // @[RegisterRouter.scala:87:24]
wire _out_T_3523 = ~out_womask_321; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_265 = {hi_712, flags_0_go, _out_prepend_T_265}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_3524 = out_prepend_265; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_3525 = _out_T_3524; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_216 = _out_T_3525; // @[MuxLiteral.scala:49:48]
wire out_rimask_322 = |_out_rimask_T_322; // @[RegisterRouter.scala:87:24]
wire out_wimask_322 = &_out_wimask_T_322; // @[RegisterRouter.scala:87:24]
wire out_romask_322 = |_out_romask_T_322; // @[RegisterRouter.scala:87:24]
wire out_womask_322 = &_out_womask_T_322; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_322 = out_rivalid_1_176 & out_rimask_322; // @[RegisterRouter.scala:87:24]
wire _out_T_3527 = out_f_rivalid_322; // @[RegisterRouter.scala:87:24]
wire out_f_roready_322 = out_roready_1_176 & out_romask_322; // @[RegisterRouter.scala:87:24]
wire _out_T_3528 = out_f_roready_322; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_322 = out_wivalid_1_176 & out_wimask_322; // @[RegisterRouter.scala:87:24]
wire out_f_woready_322 = out_woready_1_176 & out_womask_322; // @[RegisterRouter.scala:87:24]
wire _out_T_3529 = ~out_rimask_322; // @[RegisterRouter.scala:87:24]
wire _out_T_3530 = ~out_wimask_322; // @[RegisterRouter.scala:87:24]
wire _out_T_3531 = ~out_romask_322; // @[RegisterRouter.scala:87:24]
wire _out_T_3532 = ~out_womask_322; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3534 = _out_T_3533; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_266 = _out_T_3534; // @[RegisterRouter.scala:87:24]
wire out_rimask_323 = |_out_rimask_T_323; // @[RegisterRouter.scala:87:24]
wire out_wimask_323 = &_out_wimask_T_323; // @[RegisterRouter.scala:87:24]
wire out_romask_323 = |_out_romask_T_323; // @[RegisterRouter.scala:87:24]
wire out_womask_323 = &_out_womask_T_323; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_323 = out_rivalid_1_177 & out_rimask_323; // @[RegisterRouter.scala:87:24]
wire _out_T_3536 = out_f_rivalid_323; // @[RegisterRouter.scala:87:24]
wire out_f_roready_323 = out_roready_1_177 & out_romask_323; // @[RegisterRouter.scala:87:24]
wire _out_T_3537 = out_f_roready_323; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_323 = out_wivalid_1_177 & out_wimask_323; // @[RegisterRouter.scala:87:24]
wire out_f_woready_323 = out_woready_1_177 & out_womask_323; // @[RegisterRouter.scala:87:24]
wire _out_T_3538 = ~out_rimask_323; // @[RegisterRouter.scala:87:24]
wire _out_T_3539 = ~out_wimask_323; // @[RegisterRouter.scala:87:24]
wire _out_T_3540 = ~out_romask_323; // @[RegisterRouter.scala:87:24]
wire _out_T_3541 = ~out_womask_323; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_266 = {hi_290, flags_0_go, _out_prepend_T_266}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_3542 = out_prepend_266; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_3543 = _out_T_3542; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_267 = _out_T_3543; // @[RegisterRouter.scala:87:24]
wire out_rimask_324 = |_out_rimask_T_324; // @[RegisterRouter.scala:87:24]
wire out_wimask_324 = &_out_wimask_T_324; // @[RegisterRouter.scala:87:24]
wire out_romask_324 = |_out_romask_T_324; // @[RegisterRouter.scala:87:24]
wire out_womask_324 = &_out_womask_T_324; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_324 = out_rivalid_1_178 & out_rimask_324; // @[RegisterRouter.scala:87:24]
wire _out_T_3545 = out_f_rivalid_324; // @[RegisterRouter.scala:87:24]
wire out_f_roready_324 = out_roready_1_178 & out_romask_324; // @[RegisterRouter.scala:87:24]
wire _out_T_3546 = out_f_roready_324; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_324 = out_wivalid_1_178 & out_wimask_324; // @[RegisterRouter.scala:87:24]
wire out_f_woready_324 = out_woready_1_178 & out_womask_324; // @[RegisterRouter.scala:87:24]
wire _out_T_3547 = ~out_rimask_324; // @[RegisterRouter.scala:87:24]
wire _out_T_3548 = ~out_wimask_324; // @[RegisterRouter.scala:87:24]
wire _out_T_3549 = ~out_romask_324; // @[RegisterRouter.scala:87:24]
wire _out_T_3550 = ~out_womask_324; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_267 = {hi_291, flags_0_go, _out_prepend_T_267}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_3551 = out_prepend_267; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_3552 = _out_T_3551; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_268 = _out_T_3552; // @[RegisterRouter.scala:87:24]
wire out_rimask_325 = |_out_rimask_T_325; // @[RegisterRouter.scala:87:24]
wire out_wimask_325 = &_out_wimask_T_325; // @[RegisterRouter.scala:87:24]
wire out_romask_325 = |_out_romask_T_325; // @[RegisterRouter.scala:87:24]
wire out_womask_325 = &_out_womask_T_325; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_325 = out_rivalid_1_179 & out_rimask_325; // @[RegisterRouter.scala:87:24]
wire _out_T_3554 = out_f_rivalid_325; // @[RegisterRouter.scala:87:24]
wire out_f_roready_325 = out_roready_1_179 & out_romask_325; // @[RegisterRouter.scala:87:24]
wire _out_T_3555 = out_f_roready_325; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_325 = out_wivalid_1_179 & out_wimask_325; // @[RegisterRouter.scala:87:24]
wire out_f_woready_325 = out_woready_1_179 & out_womask_325; // @[RegisterRouter.scala:87:24]
wire _out_T_3556 = ~out_rimask_325; // @[RegisterRouter.scala:87:24]
wire _out_T_3557 = ~out_wimask_325; // @[RegisterRouter.scala:87:24]
wire _out_T_3558 = ~out_romask_325; // @[RegisterRouter.scala:87:24]
wire _out_T_3559 = ~out_womask_325; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_268 = {hi_292, flags_0_go, _out_prepend_T_268}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_3560 = out_prepend_268; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_3561 = _out_T_3560; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_269 = _out_T_3561; // @[RegisterRouter.scala:87:24]
wire out_rimask_326 = |_out_rimask_T_326; // @[RegisterRouter.scala:87:24]
wire out_wimask_326 = &_out_wimask_T_326; // @[RegisterRouter.scala:87:24]
wire out_romask_326 = |_out_romask_T_326; // @[RegisterRouter.scala:87:24]
wire out_womask_326 = &_out_womask_T_326; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_326 = out_rivalid_1_180 & out_rimask_326; // @[RegisterRouter.scala:87:24]
wire _out_T_3563 = out_f_rivalid_326; // @[RegisterRouter.scala:87:24]
wire out_f_roready_326 = out_roready_1_180 & out_romask_326; // @[RegisterRouter.scala:87:24]
wire _out_T_3564 = out_f_roready_326; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_326 = out_wivalid_1_180 & out_wimask_326; // @[RegisterRouter.scala:87:24]
wire out_f_woready_326 = out_woready_1_180 & out_womask_326; // @[RegisterRouter.scala:87:24]
wire _out_T_3565 = ~out_rimask_326; // @[RegisterRouter.scala:87:24]
wire _out_T_3566 = ~out_wimask_326; // @[RegisterRouter.scala:87:24]
wire _out_T_3567 = ~out_romask_326; // @[RegisterRouter.scala:87:24]
wire _out_T_3568 = ~out_womask_326; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_269 = {hi_293, flags_0_go, _out_prepend_T_269}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_3569 = out_prepend_269; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_3570 = _out_T_3569; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_270 = _out_T_3570; // @[RegisterRouter.scala:87:24]
wire out_rimask_327 = |_out_rimask_T_327; // @[RegisterRouter.scala:87:24]
wire out_wimask_327 = &_out_wimask_T_327; // @[RegisterRouter.scala:87:24]
wire out_romask_327 = |_out_romask_T_327; // @[RegisterRouter.scala:87:24]
wire out_womask_327 = &_out_womask_T_327; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_327 = out_rivalid_1_181 & out_rimask_327; // @[RegisterRouter.scala:87:24]
wire _out_T_3572 = out_f_rivalid_327; // @[RegisterRouter.scala:87:24]
wire out_f_roready_327 = out_roready_1_181 & out_romask_327; // @[RegisterRouter.scala:87:24]
wire _out_T_3573 = out_f_roready_327; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_327 = out_wivalid_1_181 & out_wimask_327; // @[RegisterRouter.scala:87:24]
wire out_f_woready_327 = out_woready_1_181 & out_womask_327; // @[RegisterRouter.scala:87:24]
wire _out_T_3574 = ~out_rimask_327; // @[RegisterRouter.scala:87:24]
wire _out_T_3575 = ~out_wimask_327; // @[RegisterRouter.scala:87:24]
wire _out_T_3576 = ~out_romask_327; // @[RegisterRouter.scala:87:24]
wire _out_T_3577 = ~out_womask_327; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_270 = {hi_294, flags_0_go, _out_prepend_T_270}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_3578 = out_prepend_270; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_3579 = _out_T_3578; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_271 = _out_T_3579; // @[RegisterRouter.scala:87:24]
wire out_rimask_328 = |_out_rimask_T_328; // @[RegisterRouter.scala:87:24]
wire out_wimask_328 = &_out_wimask_T_328; // @[RegisterRouter.scala:87:24]
wire out_romask_328 = |_out_romask_T_328; // @[RegisterRouter.scala:87:24]
wire out_womask_328 = &_out_womask_T_328; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_328 = out_rivalid_1_182 & out_rimask_328; // @[RegisterRouter.scala:87:24]
wire _out_T_3581 = out_f_rivalid_328; // @[RegisterRouter.scala:87:24]
wire out_f_roready_328 = out_roready_1_182 & out_romask_328; // @[RegisterRouter.scala:87:24]
wire _out_T_3582 = out_f_roready_328; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_328 = out_wivalid_1_182 & out_wimask_328; // @[RegisterRouter.scala:87:24]
wire out_f_woready_328 = out_woready_1_182 & out_womask_328; // @[RegisterRouter.scala:87:24]
wire _out_T_3583 = ~out_rimask_328; // @[RegisterRouter.scala:87:24]
wire _out_T_3584 = ~out_wimask_328; // @[RegisterRouter.scala:87:24]
wire _out_T_3585 = ~out_romask_328; // @[RegisterRouter.scala:87:24]
wire _out_T_3586 = ~out_womask_328; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_271 = {hi_295, flags_0_go, _out_prepend_T_271}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_3587 = out_prepend_271; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_3588 = _out_T_3587; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_272 = _out_T_3588; // @[RegisterRouter.scala:87:24]
wire out_rimask_329 = |_out_rimask_T_329; // @[RegisterRouter.scala:87:24]
wire out_wimask_329 = &_out_wimask_T_329; // @[RegisterRouter.scala:87:24]
wire out_romask_329 = |_out_romask_T_329; // @[RegisterRouter.scala:87:24]
wire out_womask_329 = &_out_womask_T_329; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_329 = out_rivalid_1_183 & out_rimask_329; // @[RegisterRouter.scala:87:24]
wire _out_T_3590 = out_f_rivalid_329; // @[RegisterRouter.scala:87:24]
wire out_f_roready_329 = out_roready_1_183 & out_romask_329; // @[RegisterRouter.scala:87:24]
wire _out_T_3591 = out_f_roready_329; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_329 = out_wivalid_1_183 & out_wimask_329; // @[RegisterRouter.scala:87:24]
wire out_f_woready_329 = out_woready_1_183 & out_womask_329; // @[RegisterRouter.scala:87:24]
wire _out_T_3592 = ~out_rimask_329; // @[RegisterRouter.scala:87:24]
wire _out_T_3593 = ~out_wimask_329; // @[RegisterRouter.scala:87:24]
wire _out_T_3594 = ~out_romask_329; // @[RegisterRouter.scala:87:24]
wire _out_T_3595 = ~out_womask_329; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_272 = {hi_296, flags_0_go, _out_prepend_T_272}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_3596 = out_prepend_272; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_3597 = _out_T_3596; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_164 = _out_T_3597; // @[MuxLiteral.scala:49:48]
wire out_rimask_330 = |_out_rimask_T_330; // @[RegisterRouter.scala:87:24]
wire out_wimask_330 = &_out_wimask_T_330; // @[RegisterRouter.scala:87:24]
wire out_romask_330 = |_out_romask_T_330; // @[RegisterRouter.scala:87:24]
wire out_womask_330 = &_out_womask_T_330; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_330 = out_rivalid_1_184 & out_rimask_330; // @[RegisterRouter.scala:87:24]
wire _out_T_3599 = out_f_rivalid_330; // @[RegisterRouter.scala:87:24]
wire out_f_roready_330 = out_roready_1_184 & out_romask_330; // @[RegisterRouter.scala:87:24]
wire _out_T_3600 = out_f_roready_330; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_330 = out_wivalid_1_184 & out_wimask_330; // @[RegisterRouter.scala:87:24]
wire out_f_woready_330 = out_woready_1_184 & out_womask_330; // @[RegisterRouter.scala:87:24]
wire _out_T_3601 = ~out_rimask_330; // @[RegisterRouter.scala:87:24]
wire _out_T_3602 = ~out_wimask_330; // @[RegisterRouter.scala:87:24]
wire _out_T_3603 = ~out_romask_330; // @[RegisterRouter.scala:87:24]
wire _out_T_3604 = ~out_womask_330; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3606 = _out_T_3605; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_273 = _out_T_3606; // @[RegisterRouter.scala:87:24]
wire out_rimask_331 = |_out_rimask_T_331; // @[RegisterRouter.scala:87:24]
wire out_wimask_331 = &_out_wimask_T_331; // @[RegisterRouter.scala:87:24]
wire out_romask_331 = |_out_romask_T_331; // @[RegisterRouter.scala:87:24]
wire out_womask_331 = &_out_womask_T_331; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_331 = out_rivalid_1_185 & out_rimask_331; // @[RegisterRouter.scala:87:24]
wire _out_T_3608 = out_f_rivalid_331; // @[RegisterRouter.scala:87:24]
wire out_f_roready_331 = out_roready_1_185 & out_romask_331; // @[RegisterRouter.scala:87:24]
wire _out_T_3609 = out_f_roready_331; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_331 = out_wivalid_1_185 & out_wimask_331; // @[RegisterRouter.scala:87:24]
wire out_f_woready_331 = out_woready_1_185 & out_womask_331; // @[RegisterRouter.scala:87:24]
wire _out_T_3610 = ~out_rimask_331; // @[RegisterRouter.scala:87:24]
wire _out_T_3611 = ~out_wimask_331; // @[RegisterRouter.scala:87:24]
wire _out_T_3612 = ~out_romask_331; // @[RegisterRouter.scala:87:24]
wire _out_T_3613 = ~out_womask_331; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_273 = {hi_410, flags_0_go, _out_prepend_T_273}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_3614 = out_prepend_273; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_3615 = _out_T_3614; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_274 = _out_T_3615; // @[RegisterRouter.scala:87:24]
wire out_rimask_332 = |_out_rimask_T_332; // @[RegisterRouter.scala:87:24]
wire out_wimask_332 = &_out_wimask_T_332; // @[RegisterRouter.scala:87:24]
wire out_romask_332 = |_out_romask_T_332; // @[RegisterRouter.scala:87:24]
wire out_womask_332 = &_out_womask_T_332; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_332 = out_rivalid_1_186 & out_rimask_332; // @[RegisterRouter.scala:87:24]
wire _out_T_3617 = out_f_rivalid_332; // @[RegisterRouter.scala:87:24]
wire out_f_roready_332 = out_roready_1_186 & out_romask_332; // @[RegisterRouter.scala:87:24]
wire _out_T_3618 = out_f_roready_332; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_332 = out_wivalid_1_186 & out_wimask_332; // @[RegisterRouter.scala:87:24]
wire out_f_woready_332 = out_woready_1_186 & out_womask_332; // @[RegisterRouter.scala:87:24]
wire _out_T_3619 = ~out_rimask_332; // @[RegisterRouter.scala:87:24]
wire _out_T_3620 = ~out_wimask_332; // @[RegisterRouter.scala:87:24]
wire _out_T_3621 = ~out_romask_332; // @[RegisterRouter.scala:87:24]
wire _out_T_3622 = ~out_womask_332; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_274 = {hi_411, flags_0_go, _out_prepend_T_274}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_3623 = out_prepend_274; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_3624 = _out_T_3623; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_275 = _out_T_3624; // @[RegisterRouter.scala:87:24]
wire out_rimask_333 = |_out_rimask_T_333; // @[RegisterRouter.scala:87:24]
wire out_wimask_333 = &_out_wimask_T_333; // @[RegisterRouter.scala:87:24]
wire out_romask_333 = |_out_romask_T_333; // @[RegisterRouter.scala:87:24]
wire out_womask_333 = &_out_womask_T_333; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_333 = out_rivalid_1_187 & out_rimask_333; // @[RegisterRouter.scala:87:24]
wire _out_T_3626 = out_f_rivalid_333; // @[RegisterRouter.scala:87:24]
wire out_f_roready_333 = out_roready_1_187 & out_romask_333; // @[RegisterRouter.scala:87:24]
wire _out_T_3627 = out_f_roready_333; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_333 = out_wivalid_1_187 & out_wimask_333; // @[RegisterRouter.scala:87:24]
wire out_f_woready_333 = out_woready_1_187 & out_womask_333; // @[RegisterRouter.scala:87:24]
wire _out_T_3628 = ~out_rimask_333; // @[RegisterRouter.scala:87:24]
wire _out_T_3629 = ~out_wimask_333; // @[RegisterRouter.scala:87:24]
wire _out_T_3630 = ~out_romask_333; // @[RegisterRouter.scala:87:24]
wire _out_T_3631 = ~out_womask_333; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_275 = {hi_412, flags_0_go, _out_prepend_T_275}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_3632 = out_prepend_275; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_3633 = _out_T_3632; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_276 = _out_T_3633; // @[RegisterRouter.scala:87:24]
wire out_rimask_334 = |_out_rimask_T_334; // @[RegisterRouter.scala:87:24]
wire out_wimask_334 = &_out_wimask_T_334; // @[RegisterRouter.scala:87:24]
wire out_romask_334 = |_out_romask_T_334; // @[RegisterRouter.scala:87:24]
wire out_womask_334 = &_out_womask_T_334; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_334 = out_rivalid_1_188 & out_rimask_334; // @[RegisterRouter.scala:87:24]
wire _out_T_3635 = out_f_rivalid_334; // @[RegisterRouter.scala:87:24]
wire out_f_roready_334 = out_roready_1_188 & out_romask_334; // @[RegisterRouter.scala:87:24]
wire _out_T_3636 = out_f_roready_334; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_334 = out_wivalid_1_188 & out_wimask_334; // @[RegisterRouter.scala:87:24]
wire out_f_woready_334 = out_woready_1_188 & out_womask_334; // @[RegisterRouter.scala:87:24]
wire _out_T_3637 = ~out_rimask_334; // @[RegisterRouter.scala:87:24]
wire _out_T_3638 = ~out_wimask_334; // @[RegisterRouter.scala:87:24]
wire _out_T_3639 = ~out_romask_334; // @[RegisterRouter.scala:87:24]
wire _out_T_3640 = ~out_womask_334; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_276 = {hi_413, flags_0_go, _out_prepend_T_276}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_3641 = out_prepend_276; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_3642 = _out_T_3641; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_277 = _out_T_3642; // @[RegisterRouter.scala:87:24]
wire out_rimask_335 = |_out_rimask_T_335; // @[RegisterRouter.scala:87:24]
wire out_wimask_335 = &_out_wimask_T_335; // @[RegisterRouter.scala:87:24]
wire out_romask_335 = |_out_romask_T_335; // @[RegisterRouter.scala:87:24]
wire out_womask_335 = &_out_womask_T_335; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_335 = out_rivalid_1_189 & out_rimask_335; // @[RegisterRouter.scala:87:24]
wire _out_T_3644 = out_f_rivalid_335; // @[RegisterRouter.scala:87:24]
wire out_f_roready_335 = out_roready_1_189 & out_romask_335; // @[RegisterRouter.scala:87:24]
wire _out_T_3645 = out_f_roready_335; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_335 = out_wivalid_1_189 & out_wimask_335; // @[RegisterRouter.scala:87:24]
wire out_f_woready_335 = out_woready_1_189 & out_womask_335; // @[RegisterRouter.scala:87:24]
wire _out_T_3646 = ~out_rimask_335; // @[RegisterRouter.scala:87:24]
wire _out_T_3647 = ~out_wimask_335; // @[RegisterRouter.scala:87:24]
wire _out_T_3648 = ~out_romask_335; // @[RegisterRouter.scala:87:24]
wire _out_T_3649 = ~out_womask_335; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_277 = {hi_414, flags_0_go, _out_prepend_T_277}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_3650 = out_prepend_277; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_3651 = _out_T_3650; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_278 = _out_T_3651; // @[RegisterRouter.scala:87:24]
wire out_rimask_336 = |_out_rimask_T_336; // @[RegisterRouter.scala:87:24]
wire out_wimask_336 = &_out_wimask_T_336; // @[RegisterRouter.scala:87:24]
wire out_romask_336 = |_out_romask_T_336; // @[RegisterRouter.scala:87:24]
wire out_womask_336 = &_out_womask_T_336; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_336 = out_rivalid_1_190 & out_rimask_336; // @[RegisterRouter.scala:87:24]
wire _out_T_3653 = out_f_rivalid_336; // @[RegisterRouter.scala:87:24]
wire out_f_roready_336 = out_roready_1_190 & out_romask_336; // @[RegisterRouter.scala:87:24]
wire _out_T_3654 = out_f_roready_336; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_336 = out_wivalid_1_190 & out_wimask_336; // @[RegisterRouter.scala:87:24]
wire out_f_woready_336 = out_woready_1_190 & out_womask_336; // @[RegisterRouter.scala:87:24]
wire _out_T_3655 = ~out_rimask_336; // @[RegisterRouter.scala:87:24]
wire _out_T_3656 = ~out_wimask_336; // @[RegisterRouter.scala:87:24]
wire _out_T_3657 = ~out_romask_336; // @[RegisterRouter.scala:87:24]
wire _out_T_3658 = ~out_womask_336; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_278 = {hi_415, flags_0_go, _out_prepend_T_278}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_3659 = out_prepend_278; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_3660 = _out_T_3659; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_279 = _out_T_3660; // @[RegisterRouter.scala:87:24]
wire out_rimask_337 = |_out_rimask_T_337; // @[RegisterRouter.scala:87:24]
wire out_wimask_337 = &_out_wimask_T_337; // @[RegisterRouter.scala:87:24]
wire out_romask_337 = |_out_romask_T_337; // @[RegisterRouter.scala:87:24]
wire out_womask_337 = &_out_womask_T_337; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_337 = out_rivalid_1_191 & out_rimask_337; // @[RegisterRouter.scala:87:24]
wire _out_T_3662 = out_f_rivalid_337; // @[RegisterRouter.scala:87:24]
wire out_f_roready_337 = out_roready_1_191 & out_romask_337; // @[RegisterRouter.scala:87:24]
wire _out_T_3663 = out_f_roready_337; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_337 = out_wivalid_1_191 & out_wimask_337; // @[RegisterRouter.scala:87:24]
wire out_f_woready_337 = out_woready_1_191 & out_womask_337; // @[RegisterRouter.scala:87:24]
wire _out_T_3664 = ~out_rimask_337; // @[RegisterRouter.scala:87:24]
wire _out_T_3665 = ~out_wimask_337; // @[RegisterRouter.scala:87:24]
wire _out_T_3666 = ~out_romask_337; // @[RegisterRouter.scala:87:24]
wire _out_T_3667 = ~out_womask_337; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_279 = {hi_416, flags_0_go, _out_prepend_T_279}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_3668 = out_prepend_279; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_3669 = _out_T_3668; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_179 = _out_T_3669; // @[MuxLiteral.scala:49:48]
wire out_rimask_338 = |_out_rimask_T_338; // @[RegisterRouter.scala:87:24]
wire out_wimask_338 = &_out_wimask_T_338; // @[RegisterRouter.scala:87:24]
wire out_romask_338 = |_out_romask_T_338; // @[RegisterRouter.scala:87:24]
wire out_womask_338 = &_out_womask_T_338; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_338 = out_rivalid_1_192 & out_rimask_338; // @[RegisterRouter.scala:87:24]
wire _out_T_3671 = out_f_rivalid_338; // @[RegisterRouter.scala:87:24]
wire out_f_roready_338 = out_roready_1_192 & out_romask_338; // @[RegisterRouter.scala:87:24]
wire _out_T_3672 = out_f_roready_338; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_338 = out_wivalid_1_192 & out_wimask_338; // @[RegisterRouter.scala:87:24]
wire _out_T_3673 = out_f_wivalid_338; // @[RegisterRouter.scala:87:24]
wire out_f_woready_338 = out_woready_1_192 & out_womask_338; // @[RegisterRouter.scala:87:24]
wire _out_T_3674 = out_f_woready_338; // @[RegisterRouter.scala:87:24]
wire _out_T_3675 = ~out_rimask_338; // @[RegisterRouter.scala:87:24]
wire _out_T_3676 = ~out_wimask_338; // @[RegisterRouter.scala:87:24]
wire _out_T_3677 = ~out_romask_338; // @[RegisterRouter.scala:87:24]
wire _out_T_3678 = ~out_womask_338; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3680 = _out_T_3679; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_280 = _out_T_3680; // @[RegisterRouter.scala:87:24]
wire out_rimask_339 = |_out_rimask_T_339; // @[RegisterRouter.scala:87:24]
wire out_wimask_339 = &_out_wimask_T_339; // @[RegisterRouter.scala:87:24]
wire out_romask_339 = |_out_romask_T_339; // @[RegisterRouter.scala:87:24]
wire out_womask_339 = &_out_womask_T_339; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_339 = out_rivalid_1_193 & out_rimask_339; // @[RegisterRouter.scala:87:24]
wire _out_T_3682 = out_f_rivalid_339; // @[RegisterRouter.scala:87:24]
wire out_f_roready_339 = out_roready_1_193 & out_romask_339; // @[RegisterRouter.scala:87:24]
wire _out_T_3683 = out_f_roready_339; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_339 = out_wivalid_1_193 & out_wimask_339; // @[RegisterRouter.scala:87:24]
wire _out_T_3684 = out_f_wivalid_339; // @[RegisterRouter.scala:87:24]
wire out_f_woready_339 = out_woready_1_193 & out_womask_339; // @[RegisterRouter.scala:87:24]
wire _out_T_3685 = out_f_woready_339; // @[RegisterRouter.scala:87:24]
wire _out_T_3686 = ~out_rimask_339; // @[RegisterRouter.scala:87:24]
wire _out_T_3687 = ~out_wimask_339; // @[RegisterRouter.scala:87:24]
wire _out_T_3688 = ~out_romask_339; // @[RegisterRouter.scala:87:24]
wire _out_T_3689 = ~out_womask_339; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_280 = {programBufferMem_17, _out_prepend_T_280}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_3690 = out_prepend_280; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_3691 = _out_T_3690; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_281 = _out_T_3691; // @[RegisterRouter.scala:87:24]
wire out_rimask_340 = |_out_rimask_T_340; // @[RegisterRouter.scala:87:24]
wire out_wimask_340 = &_out_wimask_T_340; // @[RegisterRouter.scala:87:24]
wire out_romask_340 = |_out_romask_T_340; // @[RegisterRouter.scala:87:24]
wire out_womask_340 = &_out_womask_T_340; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_340 = out_rivalid_1_194 & out_rimask_340; // @[RegisterRouter.scala:87:24]
wire _out_T_3693 = out_f_rivalid_340; // @[RegisterRouter.scala:87:24]
wire out_f_roready_340 = out_roready_1_194 & out_romask_340; // @[RegisterRouter.scala:87:24]
wire _out_T_3694 = out_f_roready_340; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_340 = out_wivalid_1_194 & out_wimask_340; // @[RegisterRouter.scala:87:24]
wire _out_T_3695 = out_f_wivalid_340; // @[RegisterRouter.scala:87:24]
wire out_f_woready_340 = out_woready_1_194 & out_womask_340; // @[RegisterRouter.scala:87:24]
wire _out_T_3696 = out_f_woready_340; // @[RegisterRouter.scala:87:24]
wire _out_T_3697 = ~out_rimask_340; // @[RegisterRouter.scala:87:24]
wire _out_T_3698 = ~out_wimask_340; // @[RegisterRouter.scala:87:24]
wire _out_T_3699 = ~out_romask_340; // @[RegisterRouter.scala:87:24]
wire _out_T_3700 = ~out_womask_340; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_281 = {programBufferMem_18, _out_prepend_T_281}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_3701 = out_prepend_281; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_3702 = _out_T_3701; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_282 = _out_T_3702; // @[RegisterRouter.scala:87:24]
wire out_rimask_341 = |_out_rimask_T_341; // @[RegisterRouter.scala:87:24]
wire out_wimask_341 = &_out_wimask_T_341; // @[RegisterRouter.scala:87:24]
wire out_romask_341 = |_out_romask_T_341; // @[RegisterRouter.scala:87:24]
wire out_womask_341 = &_out_womask_T_341; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_341 = out_rivalid_1_195 & out_rimask_341; // @[RegisterRouter.scala:87:24]
wire _out_T_3704 = out_f_rivalid_341; // @[RegisterRouter.scala:87:24]
wire out_f_roready_341 = out_roready_1_195 & out_romask_341; // @[RegisterRouter.scala:87:24]
wire _out_T_3705 = out_f_roready_341; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_341 = out_wivalid_1_195 & out_wimask_341; // @[RegisterRouter.scala:87:24]
wire _out_T_3706 = out_f_wivalid_341; // @[RegisterRouter.scala:87:24]
wire out_f_woready_341 = out_woready_1_195 & out_womask_341; // @[RegisterRouter.scala:87:24]
wire _out_T_3707 = out_f_woready_341; // @[RegisterRouter.scala:87:24]
wire _out_T_3708 = ~out_rimask_341; // @[RegisterRouter.scala:87:24]
wire _out_T_3709 = ~out_wimask_341; // @[RegisterRouter.scala:87:24]
wire _out_T_3710 = ~out_romask_341; // @[RegisterRouter.scala:87:24]
wire _out_T_3711 = ~out_womask_341; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_282 = {programBufferMem_19, _out_prepend_T_282}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_3712 = out_prepend_282; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_3713 = _out_T_3712; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_283 = _out_T_3713; // @[RegisterRouter.scala:87:24]
wire out_rimask_342 = |_out_rimask_T_342; // @[RegisterRouter.scala:87:24]
wire out_wimask_342 = &_out_wimask_T_342; // @[RegisterRouter.scala:87:24]
wire out_romask_342 = |_out_romask_T_342; // @[RegisterRouter.scala:87:24]
wire out_womask_342 = &_out_womask_T_342; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_342 = out_rivalid_1_196 & out_rimask_342; // @[RegisterRouter.scala:87:24]
wire _out_T_3715 = out_f_rivalid_342; // @[RegisterRouter.scala:87:24]
wire out_f_roready_342 = out_roready_1_196 & out_romask_342; // @[RegisterRouter.scala:87:24]
wire _out_T_3716 = out_f_roready_342; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_342 = out_wivalid_1_196 & out_wimask_342; // @[RegisterRouter.scala:87:24]
wire _out_T_3717 = out_f_wivalid_342; // @[RegisterRouter.scala:87:24]
wire out_f_woready_342 = out_woready_1_196 & out_womask_342; // @[RegisterRouter.scala:87:24]
wire _out_T_3718 = out_f_woready_342; // @[RegisterRouter.scala:87:24]
wire _out_T_3719 = ~out_rimask_342; // @[RegisterRouter.scala:87:24]
wire _out_T_3720 = ~out_wimask_342; // @[RegisterRouter.scala:87:24]
wire _out_T_3721 = ~out_romask_342; // @[RegisterRouter.scala:87:24]
wire _out_T_3722 = ~out_womask_342; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_283 = {programBufferMem_20, _out_prepend_T_283}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_3723 = out_prepend_283; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_3724 = _out_T_3723; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_284 = _out_T_3724; // @[RegisterRouter.scala:87:24]
wire out_rimask_343 = |_out_rimask_T_343; // @[RegisterRouter.scala:87:24]
wire out_wimask_343 = &_out_wimask_T_343; // @[RegisterRouter.scala:87:24]
wire out_romask_343 = |_out_romask_T_343; // @[RegisterRouter.scala:87:24]
wire out_womask_343 = &_out_womask_T_343; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_343 = out_rivalid_1_197 & out_rimask_343; // @[RegisterRouter.scala:87:24]
wire _out_T_3726 = out_f_rivalid_343; // @[RegisterRouter.scala:87:24]
wire out_f_roready_343 = out_roready_1_197 & out_romask_343; // @[RegisterRouter.scala:87:24]
wire _out_T_3727 = out_f_roready_343; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_343 = out_wivalid_1_197 & out_wimask_343; // @[RegisterRouter.scala:87:24]
wire _out_T_3728 = out_f_wivalid_343; // @[RegisterRouter.scala:87:24]
wire out_f_woready_343 = out_woready_1_197 & out_womask_343; // @[RegisterRouter.scala:87:24]
wire _out_T_3729 = out_f_woready_343; // @[RegisterRouter.scala:87:24]
wire _out_T_3730 = ~out_rimask_343; // @[RegisterRouter.scala:87:24]
wire _out_T_3731 = ~out_wimask_343; // @[RegisterRouter.scala:87:24]
wire _out_T_3732 = ~out_romask_343; // @[RegisterRouter.scala:87:24]
wire _out_T_3733 = ~out_womask_343; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_284 = {programBufferMem_21, _out_prepend_T_284}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_3734 = out_prepend_284; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_3735 = _out_T_3734; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_285 = _out_T_3735; // @[RegisterRouter.scala:87:24]
wire out_rimask_344 = |_out_rimask_T_344; // @[RegisterRouter.scala:87:24]
wire out_wimask_344 = &_out_wimask_T_344; // @[RegisterRouter.scala:87:24]
wire out_romask_344 = |_out_romask_T_344; // @[RegisterRouter.scala:87:24]
wire out_womask_344 = &_out_womask_T_344; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_344 = out_rivalid_1_198 & out_rimask_344; // @[RegisterRouter.scala:87:24]
wire _out_T_3737 = out_f_rivalid_344; // @[RegisterRouter.scala:87:24]
wire out_f_roready_344 = out_roready_1_198 & out_romask_344; // @[RegisterRouter.scala:87:24]
wire _out_T_3738 = out_f_roready_344; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_344 = out_wivalid_1_198 & out_wimask_344; // @[RegisterRouter.scala:87:24]
wire _out_T_3739 = out_f_wivalid_344; // @[RegisterRouter.scala:87:24]
wire out_f_woready_344 = out_woready_1_198 & out_womask_344; // @[RegisterRouter.scala:87:24]
wire _out_T_3740 = out_f_woready_344; // @[RegisterRouter.scala:87:24]
wire _out_T_3741 = ~out_rimask_344; // @[RegisterRouter.scala:87:24]
wire _out_T_3742 = ~out_wimask_344; // @[RegisterRouter.scala:87:24]
wire _out_T_3743 = ~out_romask_344; // @[RegisterRouter.scala:87:24]
wire _out_T_3744 = ~out_womask_344; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_285 = {programBufferMem_22, _out_prepend_T_285}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_3745 = out_prepend_285; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_3746 = _out_T_3745; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_286 = _out_T_3746; // @[RegisterRouter.scala:87:24]
wire out_rimask_345 = |_out_rimask_T_345; // @[RegisterRouter.scala:87:24]
wire out_wimask_345 = &_out_wimask_T_345; // @[RegisterRouter.scala:87:24]
wire out_romask_345 = |_out_romask_T_345; // @[RegisterRouter.scala:87:24]
wire out_womask_345 = &_out_womask_T_345; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_345 = out_rivalid_1_199 & out_rimask_345; // @[RegisterRouter.scala:87:24]
wire _out_T_3748 = out_f_rivalid_345; // @[RegisterRouter.scala:87:24]
wire out_f_roready_345 = out_roready_1_199 & out_romask_345; // @[RegisterRouter.scala:87:24]
wire _out_T_3749 = out_f_roready_345; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_345 = out_wivalid_1_199 & out_wimask_345; // @[RegisterRouter.scala:87:24]
wire _out_T_3750 = out_f_wivalid_345; // @[RegisterRouter.scala:87:24]
wire out_f_woready_345 = out_woready_1_199 & out_womask_345; // @[RegisterRouter.scala:87:24]
wire _out_T_3751 = out_f_woready_345; // @[RegisterRouter.scala:87:24]
wire _out_T_3752 = ~out_rimask_345; // @[RegisterRouter.scala:87:24]
wire _out_T_3753 = ~out_wimask_345; // @[RegisterRouter.scala:87:24]
wire _out_T_3754 = ~out_romask_345; // @[RegisterRouter.scala:87:24]
wire _out_T_3755 = ~out_womask_345; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_286 = {programBufferMem_23, _out_prepend_T_286}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_3756 = out_prepend_286; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_3757 = _out_T_3756; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_106 = _out_T_3757; // @[MuxLiteral.scala:49:48]
wire out_rimask_346 = |_out_rimask_T_346; // @[RegisterRouter.scala:87:24]
wire out_wimask_346 = &_out_wimask_T_346; // @[RegisterRouter.scala:87:24]
wire out_romask_346 = |_out_romask_T_346; // @[RegisterRouter.scala:87:24]
wire out_womask_346 = &_out_womask_T_346; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_346 = out_rivalid_1_200 & out_rimask_346; // @[RegisterRouter.scala:87:24]
wire _out_T_3759 = out_f_rivalid_346; // @[RegisterRouter.scala:87:24]
wire out_f_roready_346 = out_roready_1_200 & out_romask_346; // @[RegisterRouter.scala:87:24]
wire _out_T_3760 = out_f_roready_346; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_346 = out_wivalid_1_200 & out_wimask_346; // @[RegisterRouter.scala:87:24]
wire out_f_woready_346 = out_woready_1_200 & out_womask_346; // @[RegisterRouter.scala:87:24]
wire _out_T_3761 = ~out_rimask_346; // @[RegisterRouter.scala:87:24]
wire _out_T_3762 = ~out_wimask_346; // @[RegisterRouter.scala:87:24]
wire _out_T_3763 = ~out_romask_346; // @[RegisterRouter.scala:87:24]
wire _out_T_3764 = ~out_womask_346; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3766 = _out_T_3765; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_287 = _out_T_3766; // @[RegisterRouter.scala:87:24]
wire out_rimask_347 = |_out_rimask_T_347; // @[RegisterRouter.scala:87:24]
wire out_wimask_347 = &_out_wimask_T_347; // @[RegisterRouter.scala:87:24]
wire out_romask_347 = |_out_romask_T_347; // @[RegisterRouter.scala:87:24]
wire out_womask_347 = &_out_womask_T_347; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_347 = out_rivalid_1_201 & out_rimask_347; // @[RegisterRouter.scala:87:24]
wire _out_T_3768 = out_f_rivalid_347; // @[RegisterRouter.scala:87:24]
wire out_f_roready_347 = out_roready_1_201 & out_romask_347; // @[RegisterRouter.scala:87:24]
wire _out_T_3769 = out_f_roready_347; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_347 = out_wivalid_1_201 & out_wimask_347; // @[RegisterRouter.scala:87:24]
wire out_f_woready_347 = out_woready_1_201 & out_womask_347; // @[RegisterRouter.scala:87:24]
wire _out_T_3770 = ~out_rimask_347; // @[RegisterRouter.scala:87:24]
wire _out_T_3771 = ~out_wimask_347; // @[RegisterRouter.scala:87:24]
wire _out_T_3772 = ~out_romask_347; // @[RegisterRouter.scala:87:24]
wire _out_T_3773 = ~out_womask_347; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_287 = {hi_882, flags_0_go, _out_prepend_T_287}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_3774 = out_prepend_287; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_3775 = _out_T_3774; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_288 = _out_T_3775; // @[RegisterRouter.scala:87:24]
wire out_rimask_348 = |_out_rimask_T_348; // @[RegisterRouter.scala:87:24]
wire out_wimask_348 = &_out_wimask_T_348; // @[RegisterRouter.scala:87:24]
wire out_romask_348 = |_out_romask_T_348; // @[RegisterRouter.scala:87:24]
wire out_womask_348 = &_out_womask_T_348; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_348 = out_rivalid_1_202 & out_rimask_348; // @[RegisterRouter.scala:87:24]
wire _out_T_3777 = out_f_rivalid_348; // @[RegisterRouter.scala:87:24]
wire out_f_roready_348 = out_roready_1_202 & out_romask_348; // @[RegisterRouter.scala:87:24]
wire _out_T_3778 = out_f_roready_348; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_348 = out_wivalid_1_202 & out_wimask_348; // @[RegisterRouter.scala:87:24]
wire out_f_woready_348 = out_woready_1_202 & out_womask_348; // @[RegisterRouter.scala:87:24]
wire _out_T_3779 = ~out_rimask_348; // @[RegisterRouter.scala:87:24]
wire _out_T_3780 = ~out_wimask_348; // @[RegisterRouter.scala:87:24]
wire _out_T_3781 = ~out_romask_348; // @[RegisterRouter.scala:87:24]
wire _out_T_3782 = ~out_womask_348; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_288 = {hi_883, flags_0_go, _out_prepend_T_288}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_3783 = out_prepend_288; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_3784 = _out_T_3783; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_289 = _out_T_3784; // @[RegisterRouter.scala:87:24]
wire out_rimask_349 = |_out_rimask_T_349; // @[RegisterRouter.scala:87:24]
wire out_wimask_349 = &_out_wimask_T_349; // @[RegisterRouter.scala:87:24]
wire out_romask_349 = |_out_romask_T_349; // @[RegisterRouter.scala:87:24]
wire out_womask_349 = &_out_womask_T_349; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_349 = out_rivalid_1_203 & out_rimask_349; // @[RegisterRouter.scala:87:24]
wire _out_T_3786 = out_f_rivalid_349; // @[RegisterRouter.scala:87:24]
wire out_f_roready_349 = out_roready_1_203 & out_romask_349; // @[RegisterRouter.scala:87:24]
wire _out_T_3787 = out_f_roready_349; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_349 = out_wivalid_1_203 & out_wimask_349; // @[RegisterRouter.scala:87:24]
wire out_f_woready_349 = out_woready_1_203 & out_womask_349; // @[RegisterRouter.scala:87:24]
wire _out_T_3788 = ~out_rimask_349; // @[RegisterRouter.scala:87:24]
wire _out_T_3789 = ~out_wimask_349; // @[RegisterRouter.scala:87:24]
wire _out_T_3790 = ~out_romask_349; // @[RegisterRouter.scala:87:24]
wire _out_T_3791 = ~out_womask_349; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_289 = {hi_884, flags_0_go, _out_prepend_T_289}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_3792 = out_prepend_289; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_3793 = _out_T_3792; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_290 = _out_T_3793; // @[RegisterRouter.scala:87:24]
wire out_rimask_350 = |_out_rimask_T_350; // @[RegisterRouter.scala:87:24]
wire out_wimask_350 = &_out_wimask_T_350; // @[RegisterRouter.scala:87:24]
wire out_romask_350 = |_out_romask_T_350; // @[RegisterRouter.scala:87:24]
wire out_womask_350 = &_out_womask_T_350; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_350 = out_rivalid_1_204 & out_rimask_350; // @[RegisterRouter.scala:87:24]
wire _out_T_3795 = out_f_rivalid_350; // @[RegisterRouter.scala:87:24]
wire out_f_roready_350 = out_roready_1_204 & out_romask_350; // @[RegisterRouter.scala:87:24]
wire _out_T_3796 = out_f_roready_350; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_350 = out_wivalid_1_204 & out_wimask_350; // @[RegisterRouter.scala:87:24]
wire out_f_woready_350 = out_woready_1_204 & out_womask_350; // @[RegisterRouter.scala:87:24]
wire _out_T_3797 = ~out_rimask_350; // @[RegisterRouter.scala:87:24]
wire _out_T_3798 = ~out_wimask_350; // @[RegisterRouter.scala:87:24]
wire _out_T_3799 = ~out_romask_350; // @[RegisterRouter.scala:87:24]
wire _out_T_3800 = ~out_womask_350; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_290 = {hi_885, flags_0_go, _out_prepend_T_290}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_3801 = out_prepend_290; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_3802 = _out_T_3801; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_291 = _out_T_3802; // @[RegisterRouter.scala:87:24]
wire out_rimask_351 = |_out_rimask_T_351; // @[RegisterRouter.scala:87:24]
wire out_wimask_351 = &_out_wimask_T_351; // @[RegisterRouter.scala:87:24]
wire out_romask_351 = |_out_romask_T_351; // @[RegisterRouter.scala:87:24]
wire out_womask_351 = &_out_womask_T_351; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_351 = out_rivalid_1_205 & out_rimask_351; // @[RegisterRouter.scala:87:24]
wire _out_T_3804 = out_f_rivalid_351; // @[RegisterRouter.scala:87:24]
wire out_f_roready_351 = out_roready_1_205 & out_romask_351; // @[RegisterRouter.scala:87:24]
wire _out_T_3805 = out_f_roready_351; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_351 = out_wivalid_1_205 & out_wimask_351; // @[RegisterRouter.scala:87:24]
wire out_f_woready_351 = out_woready_1_205 & out_womask_351; // @[RegisterRouter.scala:87:24]
wire _out_T_3806 = ~out_rimask_351; // @[RegisterRouter.scala:87:24]
wire _out_T_3807 = ~out_wimask_351; // @[RegisterRouter.scala:87:24]
wire _out_T_3808 = ~out_romask_351; // @[RegisterRouter.scala:87:24]
wire _out_T_3809 = ~out_womask_351; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_291 = {hi_886, flags_0_go, _out_prepend_T_291}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_3810 = out_prepend_291; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_3811 = _out_T_3810; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_292 = _out_T_3811; // @[RegisterRouter.scala:87:24]
wire out_rimask_352 = |_out_rimask_T_352; // @[RegisterRouter.scala:87:24]
wire out_wimask_352 = &_out_wimask_T_352; // @[RegisterRouter.scala:87:24]
wire out_romask_352 = |_out_romask_T_352; // @[RegisterRouter.scala:87:24]
wire out_womask_352 = &_out_womask_T_352; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_352 = out_rivalid_1_206 & out_rimask_352; // @[RegisterRouter.scala:87:24]
wire _out_T_3813 = out_f_rivalid_352; // @[RegisterRouter.scala:87:24]
wire out_f_roready_352 = out_roready_1_206 & out_romask_352; // @[RegisterRouter.scala:87:24]
wire _out_T_3814 = out_f_roready_352; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_352 = out_wivalid_1_206 & out_wimask_352; // @[RegisterRouter.scala:87:24]
wire out_f_woready_352 = out_woready_1_206 & out_womask_352; // @[RegisterRouter.scala:87:24]
wire _out_T_3815 = ~out_rimask_352; // @[RegisterRouter.scala:87:24]
wire _out_T_3816 = ~out_wimask_352; // @[RegisterRouter.scala:87:24]
wire _out_T_3817 = ~out_romask_352; // @[RegisterRouter.scala:87:24]
wire _out_T_3818 = ~out_womask_352; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_292 = {hi_887, flags_0_go, _out_prepend_T_292}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_3819 = out_prepend_292; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_3820 = _out_T_3819; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_293 = _out_T_3820; // @[RegisterRouter.scala:87:24]
wire out_rimask_353 = |_out_rimask_T_353; // @[RegisterRouter.scala:87:24]
wire out_wimask_353 = &_out_wimask_T_353; // @[RegisterRouter.scala:87:24]
wire out_romask_353 = |_out_romask_T_353; // @[RegisterRouter.scala:87:24]
wire out_womask_353 = &_out_womask_T_353; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_353 = out_rivalid_1_207 & out_rimask_353; // @[RegisterRouter.scala:87:24]
wire _out_T_3822 = out_f_rivalid_353; // @[RegisterRouter.scala:87:24]
wire out_f_roready_353 = out_roready_1_207 & out_romask_353; // @[RegisterRouter.scala:87:24]
wire _out_T_3823 = out_f_roready_353; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_353 = out_wivalid_1_207 & out_wimask_353; // @[RegisterRouter.scala:87:24]
wire out_f_woready_353 = out_woready_1_207 & out_womask_353; // @[RegisterRouter.scala:87:24]
wire _out_T_3824 = ~out_rimask_353; // @[RegisterRouter.scala:87:24]
wire _out_T_3825 = ~out_wimask_353; // @[RegisterRouter.scala:87:24]
wire _out_T_3826 = ~out_romask_353; // @[RegisterRouter.scala:87:24]
wire _out_T_3827 = ~out_womask_353; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_293 = {hi_888, flags_0_go, _out_prepend_T_293}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_3828 = out_prepend_293; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_3829 = _out_T_3828; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_238 = _out_T_3829; // @[MuxLiteral.scala:49:48]
wire out_rimask_354 = |_out_rimask_T_354; // @[RegisterRouter.scala:87:24]
wire out_wimask_354 = &_out_wimask_T_354; // @[RegisterRouter.scala:87:24]
wire out_romask_354 = |_out_romask_T_354; // @[RegisterRouter.scala:87:24]
wire out_womask_354 = &_out_womask_T_354; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_354 = out_rivalid_1_208 & out_rimask_354; // @[RegisterRouter.scala:87:24]
wire _out_T_3831 = out_f_rivalid_354; // @[RegisterRouter.scala:87:24]
wire out_f_roready_354 = out_roready_1_208 & out_romask_354; // @[RegisterRouter.scala:87:24]
wire _out_T_3832 = out_f_roready_354; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_354 = out_wivalid_1_208 & out_wimask_354; // @[RegisterRouter.scala:87:24]
wire out_f_woready_354 = out_woready_1_208 & out_womask_354; // @[RegisterRouter.scala:87:24]
wire _out_T_3833 = ~out_rimask_354; // @[RegisterRouter.scala:87:24]
wire _out_T_3834 = ~out_wimask_354; // @[RegisterRouter.scala:87:24]
wire _out_T_3835 = ~out_romask_354; // @[RegisterRouter.scala:87:24]
wire _out_T_3836 = ~out_womask_354; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3838 = _out_T_3837; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_294 = _out_T_3838; // @[RegisterRouter.scala:87:24]
wire out_rimask_355 = |_out_rimask_T_355; // @[RegisterRouter.scala:87:24]
wire out_wimask_355 = &_out_wimask_T_355; // @[RegisterRouter.scala:87:24]
wire out_romask_355 = |_out_romask_T_355; // @[RegisterRouter.scala:87:24]
wire out_womask_355 = &_out_womask_T_355; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_355 = out_rivalid_1_209 & out_rimask_355; // @[RegisterRouter.scala:87:24]
wire _out_T_3840 = out_f_rivalid_355; // @[RegisterRouter.scala:87:24]
wire out_f_roready_355 = out_roready_1_209 & out_romask_355; // @[RegisterRouter.scala:87:24]
wire _out_T_3841 = out_f_roready_355; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_355 = out_wivalid_1_209 & out_wimask_355; // @[RegisterRouter.scala:87:24]
wire out_f_woready_355 = out_woready_1_209 & out_womask_355; // @[RegisterRouter.scala:87:24]
wire _out_T_3842 = ~out_rimask_355; // @[RegisterRouter.scala:87:24]
wire _out_T_3843 = ~out_wimask_355; // @[RegisterRouter.scala:87:24]
wire _out_T_3844 = ~out_romask_355; // @[RegisterRouter.scala:87:24]
wire _out_T_3845 = ~out_womask_355; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_294 = {hi_666, flags_0_go, _out_prepend_T_294}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_3846 = out_prepend_294; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_3847 = _out_T_3846; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_295 = _out_T_3847; // @[RegisterRouter.scala:87:24]
wire out_rimask_356 = |_out_rimask_T_356; // @[RegisterRouter.scala:87:24]
wire out_wimask_356 = &_out_wimask_T_356; // @[RegisterRouter.scala:87:24]
wire out_romask_356 = |_out_romask_T_356; // @[RegisterRouter.scala:87:24]
wire out_womask_356 = &_out_womask_T_356; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_356 = out_rivalid_1_210 & out_rimask_356; // @[RegisterRouter.scala:87:24]
wire _out_T_3849 = out_f_rivalid_356; // @[RegisterRouter.scala:87:24]
wire out_f_roready_356 = out_roready_1_210 & out_romask_356; // @[RegisterRouter.scala:87:24]
wire _out_T_3850 = out_f_roready_356; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_356 = out_wivalid_1_210 & out_wimask_356; // @[RegisterRouter.scala:87:24]
wire out_f_woready_356 = out_woready_1_210 & out_womask_356; // @[RegisterRouter.scala:87:24]
wire _out_T_3851 = ~out_rimask_356; // @[RegisterRouter.scala:87:24]
wire _out_T_3852 = ~out_wimask_356; // @[RegisterRouter.scala:87:24]
wire _out_T_3853 = ~out_romask_356; // @[RegisterRouter.scala:87:24]
wire _out_T_3854 = ~out_womask_356; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_295 = {hi_667, flags_0_go, _out_prepend_T_295}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_3855 = out_prepend_295; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_3856 = _out_T_3855; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_296 = _out_T_3856; // @[RegisterRouter.scala:87:24]
wire out_rimask_357 = |_out_rimask_T_357; // @[RegisterRouter.scala:87:24]
wire out_wimask_357 = &_out_wimask_T_357; // @[RegisterRouter.scala:87:24]
wire out_romask_357 = |_out_romask_T_357; // @[RegisterRouter.scala:87:24]
wire out_womask_357 = &_out_womask_T_357; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_357 = out_rivalid_1_211 & out_rimask_357; // @[RegisterRouter.scala:87:24]
wire _out_T_3858 = out_f_rivalid_357; // @[RegisterRouter.scala:87:24]
wire out_f_roready_357 = out_roready_1_211 & out_romask_357; // @[RegisterRouter.scala:87:24]
wire _out_T_3859 = out_f_roready_357; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_357 = out_wivalid_1_211 & out_wimask_357; // @[RegisterRouter.scala:87:24]
wire out_f_woready_357 = out_woready_1_211 & out_womask_357; // @[RegisterRouter.scala:87:24]
wire _out_T_3860 = ~out_rimask_357; // @[RegisterRouter.scala:87:24]
wire _out_T_3861 = ~out_wimask_357; // @[RegisterRouter.scala:87:24]
wire _out_T_3862 = ~out_romask_357; // @[RegisterRouter.scala:87:24]
wire _out_T_3863 = ~out_womask_357; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_296 = {hi_668, flags_0_go, _out_prepend_T_296}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_3864 = out_prepend_296; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_3865 = _out_T_3864; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_297 = _out_T_3865; // @[RegisterRouter.scala:87:24]
wire out_rimask_358 = |_out_rimask_T_358; // @[RegisterRouter.scala:87:24]
wire out_wimask_358 = &_out_wimask_T_358; // @[RegisterRouter.scala:87:24]
wire out_romask_358 = |_out_romask_T_358; // @[RegisterRouter.scala:87:24]
wire out_womask_358 = &_out_womask_T_358; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_358 = out_rivalid_1_212 & out_rimask_358; // @[RegisterRouter.scala:87:24]
wire _out_T_3867 = out_f_rivalid_358; // @[RegisterRouter.scala:87:24]
wire out_f_roready_358 = out_roready_1_212 & out_romask_358; // @[RegisterRouter.scala:87:24]
wire _out_T_3868 = out_f_roready_358; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_358 = out_wivalid_1_212 & out_wimask_358; // @[RegisterRouter.scala:87:24]
wire out_f_woready_358 = out_woready_1_212 & out_womask_358; // @[RegisterRouter.scala:87:24]
wire _out_T_3869 = ~out_rimask_358; // @[RegisterRouter.scala:87:24]
wire _out_T_3870 = ~out_wimask_358; // @[RegisterRouter.scala:87:24]
wire _out_T_3871 = ~out_romask_358; // @[RegisterRouter.scala:87:24]
wire _out_T_3872 = ~out_womask_358; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_297 = {hi_669, flags_0_go, _out_prepend_T_297}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_3873 = out_prepend_297; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_3874 = _out_T_3873; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_298 = _out_T_3874; // @[RegisterRouter.scala:87:24]
wire out_rimask_359 = |_out_rimask_T_359; // @[RegisterRouter.scala:87:24]
wire out_wimask_359 = &_out_wimask_T_359; // @[RegisterRouter.scala:87:24]
wire out_romask_359 = |_out_romask_T_359; // @[RegisterRouter.scala:87:24]
wire out_womask_359 = &_out_womask_T_359; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_359 = out_rivalid_1_213 & out_rimask_359; // @[RegisterRouter.scala:87:24]
wire _out_T_3876 = out_f_rivalid_359; // @[RegisterRouter.scala:87:24]
wire out_f_roready_359 = out_roready_1_213 & out_romask_359; // @[RegisterRouter.scala:87:24]
wire _out_T_3877 = out_f_roready_359; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_359 = out_wivalid_1_213 & out_wimask_359; // @[RegisterRouter.scala:87:24]
wire out_f_woready_359 = out_woready_1_213 & out_womask_359; // @[RegisterRouter.scala:87:24]
wire _out_T_3878 = ~out_rimask_359; // @[RegisterRouter.scala:87:24]
wire _out_T_3879 = ~out_wimask_359; // @[RegisterRouter.scala:87:24]
wire _out_T_3880 = ~out_romask_359; // @[RegisterRouter.scala:87:24]
wire _out_T_3881 = ~out_womask_359; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_298 = {hi_670, flags_0_go, _out_prepend_T_298}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_3882 = out_prepend_298; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_3883 = _out_T_3882; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_299 = _out_T_3883; // @[RegisterRouter.scala:87:24]
wire out_rimask_360 = |_out_rimask_T_360; // @[RegisterRouter.scala:87:24]
wire out_wimask_360 = &_out_wimask_T_360; // @[RegisterRouter.scala:87:24]
wire out_romask_360 = |_out_romask_T_360; // @[RegisterRouter.scala:87:24]
wire out_womask_360 = &_out_womask_T_360; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_360 = out_rivalid_1_214 & out_rimask_360; // @[RegisterRouter.scala:87:24]
wire _out_T_3885 = out_f_rivalid_360; // @[RegisterRouter.scala:87:24]
wire out_f_roready_360 = out_roready_1_214 & out_romask_360; // @[RegisterRouter.scala:87:24]
wire _out_T_3886 = out_f_roready_360; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_360 = out_wivalid_1_214 & out_wimask_360; // @[RegisterRouter.scala:87:24]
wire out_f_woready_360 = out_woready_1_214 & out_womask_360; // @[RegisterRouter.scala:87:24]
wire _out_T_3887 = ~out_rimask_360; // @[RegisterRouter.scala:87:24]
wire _out_T_3888 = ~out_wimask_360; // @[RegisterRouter.scala:87:24]
wire _out_T_3889 = ~out_romask_360; // @[RegisterRouter.scala:87:24]
wire _out_T_3890 = ~out_womask_360; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_299 = {hi_671, flags_0_go, _out_prepend_T_299}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_3891 = out_prepend_299; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_3892 = _out_T_3891; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_300 = _out_T_3892; // @[RegisterRouter.scala:87:24]
wire out_rimask_361 = |_out_rimask_T_361; // @[RegisterRouter.scala:87:24]
wire out_wimask_361 = &_out_wimask_T_361; // @[RegisterRouter.scala:87:24]
wire out_romask_361 = |_out_romask_T_361; // @[RegisterRouter.scala:87:24]
wire out_womask_361 = &_out_womask_T_361; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_361 = out_rivalid_1_215 & out_rimask_361; // @[RegisterRouter.scala:87:24]
wire _out_T_3894 = out_f_rivalid_361; // @[RegisterRouter.scala:87:24]
wire out_f_roready_361 = out_roready_1_215 & out_romask_361; // @[RegisterRouter.scala:87:24]
wire _out_T_3895 = out_f_roready_361; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_361 = out_wivalid_1_215 & out_wimask_361; // @[RegisterRouter.scala:87:24]
wire out_f_woready_361 = out_woready_1_215 & out_womask_361; // @[RegisterRouter.scala:87:24]
wire _out_T_3896 = ~out_rimask_361; // @[RegisterRouter.scala:87:24]
wire _out_T_3897 = ~out_wimask_361; // @[RegisterRouter.scala:87:24]
wire _out_T_3898 = ~out_romask_361; // @[RegisterRouter.scala:87:24]
wire _out_T_3899 = ~out_womask_361; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_300 = {hi_672, flags_0_go, _out_prepend_T_300}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_3900 = out_prepend_300; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_3901 = _out_T_3900; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_211 = _out_T_3901; // @[MuxLiteral.scala:49:48]
wire out_rimask_362 = |_out_rimask_T_362; // @[RegisterRouter.scala:87:24]
wire out_wimask_362 = &_out_wimask_T_362; // @[RegisterRouter.scala:87:24]
wire out_romask_362 = |_out_romask_T_362; // @[RegisterRouter.scala:87:24]
wire out_womask_362 = &_out_womask_T_362; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_362 = out_rivalid_1_216 & out_rimask_362; // @[RegisterRouter.scala:87:24]
wire _out_T_3903 = out_f_rivalid_362; // @[RegisterRouter.scala:87:24]
wire out_f_roready_362 = out_roready_1_216 & out_romask_362; // @[RegisterRouter.scala:87:24]
wire _out_T_3904 = out_f_roready_362; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_362 = out_wivalid_1_216 & out_wimask_362; // @[RegisterRouter.scala:87:24]
wire out_f_woready_362 = out_woready_1_216 & out_womask_362; // @[RegisterRouter.scala:87:24]
wire _out_T_3905 = ~out_rimask_362; // @[RegisterRouter.scala:87:24]
wire _out_T_3906 = ~out_wimask_362; // @[RegisterRouter.scala:87:24]
wire _out_T_3907 = ~out_romask_362; // @[RegisterRouter.scala:87:24]
wire _out_T_3908 = ~out_womask_362; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3910 = _out_T_3909; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_301 = _out_T_3910; // @[RegisterRouter.scala:87:24]
wire out_rimask_363 = |_out_rimask_T_363; // @[RegisterRouter.scala:87:24]
wire out_wimask_363 = &_out_wimask_T_363; // @[RegisterRouter.scala:87:24]
wire out_romask_363 = |_out_romask_T_363; // @[RegisterRouter.scala:87:24]
wire out_womask_363 = &_out_womask_T_363; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_363 = out_rivalid_1_217 & out_rimask_363; // @[RegisterRouter.scala:87:24]
wire _out_T_3912 = out_f_rivalid_363; // @[RegisterRouter.scala:87:24]
wire out_f_roready_363 = out_roready_1_217 & out_romask_363; // @[RegisterRouter.scala:87:24]
wire _out_T_3913 = out_f_roready_363; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_363 = out_wivalid_1_217 & out_wimask_363; // @[RegisterRouter.scala:87:24]
wire out_f_woready_363 = out_woready_1_217 & out_womask_363; // @[RegisterRouter.scala:87:24]
wire _out_T_3914 = ~out_rimask_363; // @[RegisterRouter.scala:87:24]
wire _out_T_3915 = ~out_wimask_363; // @[RegisterRouter.scala:87:24]
wire _out_T_3916 = ~out_romask_363; // @[RegisterRouter.scala:87:24]
wire _out_T_3917 = ~out_womask_363; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_301 = {hi_1002, flags_0_go, _out_prepend_T_301}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_3918 = out_prepend_301; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_3919 = _out_T_3918; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_302 = _out_T_3919; // @[RegisterRouter.scala:87:24]
wire out_rimask_364 = |_out_rimask_T_364; // @[RegisterRouter.scala:87:24]
wire out_wimask_364 = &_out_wimask_T_364; // @[RegisterRouter.scala:87:24]
wire out_romask_364 = |_out_romask_T_364; // @[RegisterRouter.scala:87:24]
wire out_womask_364 = &_out_womask_T_364; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_364 = out_rivalid_1_218 & out_rimask_364; // @[RegisterRouter.scala:87:24]
wire _out_T_3921 = out_f_rivalid_364; // @[RegisterRouter.scala:87:24]
wire out_f_roready_364 = out_roready_1_218 & out_romask_364; // @[RegisterRouter.scala:87:24]
wire _out_T_3922 = out_f_roready_364; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_364 = out_wivalid_1_218 & out_wimask_364; // @[RegisterRouter.scala:87:24]
wire out_f_woready_364 = out_woready_1_218 & out_womask_364; // @[RegisterRouter.scala:87:24]
wire _out_T_3923 = ~out_rimask_364; // @[RegisterRouter.scala:87:24]
wire _out_T_3924 = ~out_wimask_364; // @[RegisterRouter.scala:87:24]
wire _out_T_3925 = ~out_romask_364; // @[RegisterRouter.scala:87:24]
wire _out_T_3926 = ~out_womask_364; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_302 = {hi_1003, flags_0_go, _out_prepend_T_302}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_3927 = out_prepend_302; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_3928 = _out_T_3927; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_303 = _out_T_3928; // @[RegisterRouter.scala:87:24]
wire out_rimask_365 = |_out_rimask_T_365; // @[RegisterRouter.scala:87:24]
wire out_wimask_365 = &_out_wimask_T_365; // @[RegisterRouter.scala:87:24]
wire out_romask_365 = |_out_romask_T_365; // @[RegisterRouter.scala:87:24]
wire out_womask_365 = &_out_womask_T_365; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_365 = out_rivalid_1_219 & out_rimask_365; // @[RegisterRouter.scala:87:24]
wire _out_T_3930 = out_f_rivalid_365; // @[RegisterRouter.scala:87:24]
wire out_f_roready_365 = out_roready_1_219 & out_romask_365; // @[RegisterRouter.scala:87:24]
wire _out_T_3931 = out_f_roready_365; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_365 = out_wivalid_1_219 & out_wimask_365; // @[RegisterRouter.scala:87:24]
wire out_f_woready_365 = out_woready_1_219 & out_womask_365; // @[RegisterRouter.scala:87:24]
wire _out_T_3932 = ~out_rimask_365; // @[RegisterRouter.scala:87:24]
wire _out_T_3933 = ~out_wimask_365; // @[RegisterRouter.scala:87:24]
wire _out_T_3934 = ~out_romask_365; // @[RegisterRouter.scala:87:24]
wire _out_T_3935 = ~out_womask_365; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_303 = {hi_1004, flags_0_go, _out_prepend_T_303}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_3936 = out_prepend_303; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_3937 = _out_T_3936; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_304 = _out_T_3937; // @[RegisterRouter.scala:87:24]
wire out_rimask_366 = |_out_rimask_T_366; // @[RegisterRouter.scala:87:24]
wire out_wimask_366 = &_out_wimask_T_366; // @[RegisterRouter.scala:87:24]
wire out_romask_366 = |_out_romask_T_366; // @[RegisterRouter.scala:87:24]
wire out_womask_366 = &_out_womask_T_366; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_366 = out_rivalid_1_220 & out_rimask_366; // @[RegisterRouter.scala:87:24]
wire _out_T_3939 = out_f_rivalid_366; // @[RegisterRouter.scala:87:24]
wire out_f_roready_366 = out_roready_1_220 & out_romask_366; // @[RegisterRouter.scala:87:24]
wire _out_T_3940 = out_f_roready_366; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_366 = out_wivalid_1_220 & out_wimask_366; // @[RegisterRouter.scala:87:24]
wire out_f_woready_366 = out_woready_1_220 & out_womask_366; // @[RegisterRouter.scala:87:24]
wire _out_T_3941 = ~out_rimask_366; // @[RegisterRouter.scala:87:24]
wire _out_T_3942 = ~out_wimask_366; // @[RegisterRouter.scala:87:24]
wire _out_T_3943 = ~out_romask_366; // @[RegisterRouter.scala:87:24]
wire _out_T_3944 = ~out_womask_366; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_304 = {hi_1005, flags_0_go, _out_prepend_T_304}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_3945 = out_prepend_304; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_3946 = _out_T_3945; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_305 = _out_T_3946; // @[RegisterRouter.scala:87:24]
wire out_rimask_367 = |_out_rimask_T_367; // @[RegisterRouter.scala:87:24]
wire out_wimask_367 = &_out_wimask_T_367; // @[RegisterRouter.scala:87:24]
wire out_romask_367 = |_out_romask_T_367; // @[RegisterRouter.scala:87:24]
wire out_womask_367 = &_out_womask_T_367; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_367 = out_rivalid_1_221 & out_rimask_367; // @[RegisterRouter.scala:87:24]
wire _out_T_3948 = out_f_rivalid_367; // @[RegisterRouter.scala:87:24]
wire out_f_roready_367 = out_roready_1_221 & out_romask_367; // @[RegisterRouter.scala:87:24]
wire _out_T_3949 = out_f_roready_367; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_367 = out_wivalid_1_221 & out_wimask_367; // @[RegisterRouter.scala:87:24]
wire out_f_woready_367 = out_woready_1_221 & out_womask_367; // @[RegisterRouter.scala:87:24]
wire _out_T_3950 = ~out_rimask_367; // @[RegisterRouter.scala:87:24]
wire _out_T_3951 = ~out_wimask_367; // @[RegisterRouter.scala:87:24]
wire _out_T_3952 = ~out_romask_367; // @[RegisterRouter.scala:87:24]
wire _out_T_3953 = ~out_womask_367; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_305 = {hi_1006, flags_0_go, _out_prepend_T_305}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_3954 = out_prepend_305; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_3955 = _out_T_3954; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_306 = _out_T_3955; // @[RegisterRouter.scala:87:24]
wire out_rimask_368 = |_out_rimask_T_368; // @[RegisterRouter.scala:87:24]
wire out_wimask_368 = &_out_wimask_T_368; // @[RegisterRouter.scala:87:24]
wire out_romask_368 = |_out_romask_T_368; // @[RegisterRouter.scala:87:24]
wire out_womask_368 = &_out_womask_T_368; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_368 = out_rivalid_1_222 & out_rimask_368; // @[RegisterRouter.scala:87:24]
wire _out_T_3957 = out_f_rivalid_368; // @[RegisterRouter.scala:87:24]
wire out_f_roready_368 = out_roready_1_222 & out_romask_368; // @[RegisterRouter.scala:87:24]
wire _out_T_3958 = out_f_roready_368; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_368 = out_wivalid_1_222 & out_wimask_368; // @[RegisterRouter.scala:87:24]
wire out_f_woready_368 = out_woready_1_222 & out_womask_368; // @[RegisterRouter.scala:87:24]
wire _out_T_3959 = ~out_rimask_368; // @[RegisterRouter.scala:87:24]
wire _out_T_3960 = ~out_wimask_368; // @[RegisterRouter.scala:87:24]
wire _out_T_3961 = ~out_romask_368; // @[RegisterRouter.scala:87:24]
wire _out_T_3962 = ~out_womask_368; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_306 = {hi_1007, flags_0_go, _out_prepend_T_306}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_3963 = out_prepend_306; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_3964 = _out_T_3963; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_307 = _out_T_3964; // @[RegisterRouter.scala:87:24]
wire out_rimask_369 = |_out_rimask_T_369; // @[RegisterRouter.scala:87:24]
wire out_wimask_369 = &_out_wimask_T_369; // @[RegisterRouter.scala:87:24]
wire out_romask_369 = |_out_romask_T_369; // @[RegisterRouter.scala:87:24]
wire out_womask_369 = &_out_womask_T_369; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_369 = out_rivalid_1_223 & out_rimask_369; // @[RegisterRouter.scala:87:24]
wire _out_T_3966 = out_f_rivalid_369; // @[RegisterRouter.scala:87:24]
wire out_f_roready_369 = out_roready_1_223 & out_romask_369; // @[RegisterRouter.scala:87:24]
wire _out_T_3967 = out_f_roready_369; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_369 = out_wivalid_1_223 & out_wimask_369; // @[RegisterRouter.scala:87:24]
wire out_f_woready_369 = out_woready_1_223 & out_womask_369; // @[RegisterRouter.scala:87:24]
wire _out_T_3968 = ~out_rimask_369; // @[RegisterRouter.scala:87:24]
wire _out_T_3969 = ~out_wimask_369; // @[RegisterRouter.scala:87:24]
wire _out_T_3970 = ~out_romask_369; // @[RegisterRouter.scala:87:24]
wire _out_T_3971 = ~out_womask_369; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_307 = {hi_1008, flags_0_go, _out_prepend_T_307}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_3972 = out_prepend_307; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_3973 = _out_T_3972; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_253 = _out_T_3973; // @[MuxLiteral.scala:49:48]
wire out_rimask_370 = |_out_rimask_T_370; // @[RegisterRouter.scala:87:24]
wire out_wimask_370 = &_out_wimask_T_370; // @[RegisterRouter.scala:87:24]
wire out_romask_370 = |_out_romask_T_370; // @[RegisterRouter.scala:87:24]
wire out_womask_370 = &_out_womask_T_370; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_370 = out_rivalid_1_224 & out_rimask_370; // @[RegisterRouter.scala:87:24]
wire _out_T_3975 = out_f_rivalid_370; // @[RegisterRouter.scala:87:24]
wire out_f_roready_370 = out_roready_1_224 & out_romask_370; // @[RegisterRouter.scala:87:24]
wire _out_T_3976 = out_f_roready_370; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_370 = out_wivalid_1_224 & out_wimask_370; // @[RegisterRouter.scala:87:24]
wire out_f_woready_370 = out_woready_1_224 & out_womask_370; // @[RegisterRouter.scala:87:24]
wire _out_T_3977 = ~out_rimask_370; // @[RegisterRouter.scala:87:24]
wire _out_T_3978 = ~out_wimask_370; // @[RegisterRouter.scala:87:24]
wire _out_T_3979 = ~out_romask_370; // @[RegisterRouter.scala:87:24]
wire _out_T_3980 = ~out_womask_370; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3982 = _out_T_3981; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_308 = _out_T_3982; // @[RegisterRouter.scala:87:24]
wire out_rimask_371 = |_out_rimask_T_371; // @[RegisterRouter.scala:87:24]
wire out_wimask_371 = &_out_wimask_T_371; // @[RegisterRouter.scala:87:24]
wire out_romask_371 = |_out_romask_T_371; // @[RegisterRouter.scala:87:24]
wire out_womask_371 = &_out_womask_T_371; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_371 = out_rivalid_1_225 & out_rimask_371; // @[RegisterRouter.scala:87:24]
wire _out_T_3984 = out_f_rivalid_371; // @[RegisterRouter.scala:87:24]
wire out_f_roready_371 = out_roready_1_225 & out_romask_371; // @[RegisterRouter.scala:87:24]
wire _out_T_3985 = out_f_roready_371; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_371 = out_wivalid_1_225 & out_wimask_371; // @[RegisterRouter.scala:87:24]
wire out_f_woready_371 = out_woready_1_225 & out_womask_371; // @[RegisterRouter.scala:87:24]
wire _out_T_3986 = ~out_rimask_371; // @[RegisterRouter.scala:87:24]
wire _out_T_3987 = ~out_wimask_371; // @[RegisterRouter.scala:87:24]
wire _out_T_3988 = ~out_romask_371; // @[RegisterRouter.scala:87:24]
wire _out_T_3989 = ~out_womask_371; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_308 = {hi_154, flags_0_go, _out_prepend_T_308}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_3990 = out_prepend_308; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_3991 = _out_T_3990; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_309 = _out_T_3991; // @[RegisterRouter.scala:87:24]
wire out_rimask_372 = |_out_rimask_T_372; // @[RegisterRouter.scala:87:24]
wire out_wimask_372 = &_out_wimask_T_372; // @[RegisterRouter.scala:87:24]
wire out_romask_372 = |_out_romask_T_372; // @[RegisterRouter.scala:87:24]
wire out_womask_372 = &_out_womask_T_372; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_372 = out_rivalid_1_226 & out_rimask_372; // @[RegisterRouter.scala:87:24]
wire _out_T_3993 = out_f_rivalid_372; // @[RegisterRouter.scala:87:24]
wire out_f_roready_372 = out_roready_1_226 & out_romask_372; // @[RegisterRouter.scala:87:24]
wire _out_T_3994 = out_f_roready_372; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_372 = out_wivalid_1_226 & out_wimask_372; // @[RegisterRouter.scala:87:24]
wire out_f_woready_372 = out_woready_1_226 & out_womask_372; // @[RegisterRouter.scala:87:24]
wire _out_T_3995 = ~out_rimask_372; // @[RegisterRouter.scala:87:24]
wire _out_T_3996 = ~out_wimask_372; // @[RegisterRouter.scala:87:24]
wire _out_T_3997 = ~out_romask_372; // @[RegisterRouter.scala:87:24]
wire _out_T_3998 = ~out_womask_372; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_309 = {hi_155, flags_0_go, _out_prepend_T_309}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_3999 = out_prepend_309; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_4000 = _out_T_3999; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_310 = _out_T_4000; // @[RegisterRouter.scala:87:24]
wire out_rimask_373 = |_out_rimask_T_373; // @[RegisterRouter.scala:87:24]
wire out_wimask_373 = &_out_wimask_T_373; // @[RegisterRouter.scala:87:24]
wire out_romask_373 = |_out_romask_T_373; // @[RegisterRouter.scala:87:24]
wire out_womask_373 = &_out_womask_T_373; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_373 = out_rivalid_1_227 & out_rimask_373; // @[RegisterRouter.scala:87:24]
wire _out_T_4002 = out_f_rivalid_373; // @[RegisterRouter.scala:87:24]
wire out_f_roready_373 = out_roready_1_227 & out_romask_373; // @[RegisterRouter.scala:87:24]
wire _out_T_4003 = out_f_roready_373; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_373 = out_wivalid_1_227 & out_wimask_373; // @[RegisterRouter.scala:87:24]
wire out_f_woready_373 = out_woready_1_227 & out_womask_373; // @[RegisterRouter.scala:87:24]
wire _out_T_4004 = ~out_rimask_373; // @[RegisterRouter.scala:87:24]
wire _out_T_4005 = ~out_wimask_373; // @[RegisterRouter.scala:87:24]
wire _out_T_4006 = ~out_romask_373; // @[RegisterRouter.scala:87:24]
wire _out_T_4007 = ~out_womask_373; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_310 = {hi_156, flags_0_go, _out_prepend_T_310}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_4008 = out_prepend_310; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_4009 = _out_T_4008; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_311 = _out_T_4009; // @[RegisterRouter.scala:87:24]
wire out_rimask_374 = |_out_rimask_T_374; // @[RegisterRouter.scala:87:24]
wire out_wimask_374 = &_out_wimask_T_374; // @[RegisterRouter.scala:87:24]
wire out_romask_374 = |_out_romask_T_374; // @[RegisterRouter.scala:87:24]
wire out_womask_374 = &_out_womask_T_374; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_374 = out_rivalid_1_228 & out_rimask_374; // @[RegisterRouter.scala:87:24]
wire _out_T_4011 = out_f_rivalid_374; // @[RegisterRouter.scala:87:24]
wire out_f_roready_374 = out_roready_1_228 & out_romask_374; // @[RegisterRouter.scala:87:24]
wire _out_T_4012 = out_f_roready_374; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_374 = out_wivalid_1_228 & out_wimask_374; // @[RegisterRouter.scala:87:24]
wire out_f_woready_374 = out_woready_1_228 & out_womask_374; // @[RegisterRouter.scala:87:24]
wire _out_T_4013 = ~out_rimask_374; // @[RegisterRouter.scala:87:24]
wire _out_T_4014 = ~out_wimask_374; // @[RegisterRouter.scala:87:24]
wire _out_T_4015 = ~out_romask_374; // @[RegisterRouter.scala:87:24]
wire _out_T_4016 = ~out_womask_374; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_311 = {hi_157, flags_0_go, _out_prepend_T_311}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_4017 = out_prepend_311; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_4018 = _out_T_4017; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_312 = _out_T_4018; // @[RegisterRouter.scala:87:24]
wire out_rimask_375 = |_out_rimask_T_375; // @[RegisterRouter.scala:87:24]
wire out_wimask_375 = &_out_wimask_T_375; // @[RegisterRouter.scala:87:24]
wire out_romask_375 = |_out_romask_T_375; // @[RegisterRouter.scala:87:24]
wire out_womask_375 = &_out_womask_T_375; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_375 = out_rivalid_1_229 & out_rimask_375; // @[RegisterRouter.scala:87:24]
wire _out_T_4020 = out_f_rivalid_375; // @[RegisterRouter.scala:87:24]
wire out_f_roready_375 = out_roready_1_229 & out_romask_375; // @[RegisterRouter.scala:87:24]
wire _out_T_4021 = out_f_roready_375; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_375 = out_wivalid_1_229 & out_wimask_375; // @[RegisterRouter.scala:87:24]
wire out_f_woready_375 = out_woready_1_229 & out_womask_375; // @[RegisterRouter.scala:87:24]
wire _out_T_4022 = ~out_rimask_375; // @[RegisterRouter.scala:87:24]
wire _out_T_4023 = ~out_wimask_375; // @[RegisterRouter.scala:87:24]
wire _out_T_4024 = ~out_romask_375; // @[RegisterRouter.scala:87:24]
wire _out_T_4025 = ~out_womask_375; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_312 = {hi_158, flags_0_go, _out_prepend_T_312}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_4026 = out_prepend_312; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_4027 = _out_T_4026; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_313 = _out_T_4027; // @[RegisterRouter.scala:87:24]
wire out_rimask_376 = |_out_rimask_T_376; // @[RegisterRouter.scala:87:24]
wire out_wimask_376 = &_out_wimask_T_376; // @[RegisterRouter.scala:87:24]
wire out_romask_376 = |_out_romask_T_376; // @[RegisterRouter.scala:87:24]
wire out_womask_376 = &_out_womask_T_376; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_376 = out_rivalid_1_230 & out_rimask_376; // @[RegisterRouter.scala:87:24]
wire _out_T_4029 = out_f_rivalid_376; // @[RegisterRouter.scala:87:24]
wire out_f_roready_376 = out_roready_1_230 & out_romask_376; // @[RegisterRouter.scala:87:24]
wire _out_T_4030 = out_f_roready_376; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_376 = out_wivalid_1_230 & out_wimask_376; // @[RegisterRouter.scala:87:24]
wire out_f_woready_376 = out_woready_1_230 & out_womask_376; // @[RegisterRouter.scala:87:24]
wire _out_T_4031 = ~out_rimask_376; // @[RegisterRouter.scala:87:24]
wire _out_T_4032 = ~out_wimask_376; // @[RegisterRouter.scala:87:24]
wire _out_T_4033 = ~out_romask_376; // @[RegisterRouter.scala:87:24]
wire _out_T_4034 = ~out_womask_376; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_313 = {hi_159, flags_0_go, _out_prepend_T_313}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_4035 = out_prepend_313; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_4036 = _out_T_4035; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_314 = _out_T_4036; // @[RegisterRouter.scala:87:24]
wire out_rimask_377 = |_out_rimask_T_377; // @[RegisterRouter.scala:87:24]
wire out_wimask_377 = &_out_wimask_T_377; // @[RegisterRouter.scala:87:24]
wire out_romask_377 = |_out_romask_T_377; // @[RegisterRouter.scala:87:24]
wire out_womask_377 = &_out_womask_T_377; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_377 = out_rivalid_1_231 & out_rimask_377; // @[RegisterRouter.scala:87:24]
wire _out_T_4038 = out_f_rivalid_377; // @[RegisterRouter.scala:87:24]
wire out_f_roready_377 = out_roready_1_231 & out_romask_377; // @[RegisterRouter.scala:87:24]
wire _out_T_4039 = out_f_roready_377; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_377 = out_wivalid_1_231 & out_wimask_377; // @[RegisterRouter.scala:87:24]
wire out_f_woready_377 = out_woready_1_231 & out_womask_377; // @[RegisterRouter.scala:87:24]
wire _out_T_4040 = ~out_rimask_377; // @[RegisterRouter.scala:87:24]
wire _out_T_4041 = ~out_wimask_377; // @[RegisterRouter.scala:87:24]
wire _out_T_4042 = ~out_romask_377; // @[RegisterRouter.scala:87:24]
wire _out_T_4043 = ~out_womask_377; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_314 = {hi_160, flags_0_go, _out_prepend_T_314}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_4044 = out_prepend_314; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_4045 = _out_T_4044; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_147 = _out_T_4045; // @[MuxLiteral.scala:49:48]
wire out_rimask_378 = |_out_rimask_T_378; // @[RegisterRouter.scala:87:24]
wire out_wimask_378 = &_out_wimask_T_378; // @[RegisterRouter.scala:87:24]
wire out_romask_378 = |_out_romask_T_378; // @[RegisterRouter.scala:87:24]
wire out_womask_378 = &_out_womask_T_378; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_378 = out_rivalid_1_232 & out_rimask_378; // @[RegisterRouter.scala:87:24]
wire _out_T_4047 = out_f_rivalid_378; // @[RegisterRouter.scala:87:24]
wire out_f_roready_378 = out_roready_1_232 & out_romask_378; // @[RegisterRouter.scala:87:24]
wire _out_T_4048 = out_f_roready_378; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_378 = out_wivalid_1_232 & out_wimask_378; // @[RegisterRouter.scala:87:24]
wire out_f_woready_378 = out_woready_1_232 & out_womask_378; // @[RegisterRouter.scala:87:24]
wire _out_T_4049 = ~out_rimask_378; // @[RegisterRouter.scala:87:24]
wire _out_T_4050 = ~out_wimask_378; // @[RegisterRouter.scala:87:24]
wire _out_T_4051 = ~out_romask_378; // @[RegisterRouter.scala:87:24]
wire _out_T_4052 = ~out_womask_378; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4054 = _out_T_4053; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_315 = _out_T_4054; // @[RegisterRouter.scala:87:24]
wire out_rimask_379 = |_out_rimask_T_379; // @[RegisterRouter.scala:87:24]
wire out_wimask_379 = &_out_wimask_T_379; // @[RegisterRouter.scala:87:24]
wire out_romask_379 = |_out_romask_T_379; // @[RegisterRouter.scala:87:24]
wire out_womask_379 = &_out_womask_T_379; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_379 = out_rivalid_1_233 & out_rimask_379; // @[RegisterRouter.scala:87:24]
wire _out_T_4056 = out_f_rivalid_379; // @[RegisterRouter.scala:87:24]
wire out_f_roready_379 = out_roready_1_233 & out_romask_379; // @[RegisterRouter.scala:87:24]
wire _out_T_4057 = out_f_roready_379; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_379 = out_wivalid_1_233 & out_wimask_379; // @[RegisterRouter.scala:87:24]
wire out_f_woready_379 = out_woready_1_233 & out_womask_379; // @[RegisterRouter.scala:87:24]
wire _out_T_4058 = ~out_rimask_379; // @[RegisterRouter.scala:87:24]
wire _out_T_4059 = ~out_wimask_379; // @[RegisterRouter.scala:87:24]
wire _out_T_4060 = ~out_romask_379; // @[RegisterRouter.scala:87:24]
wire _out_T_4061 = ~out_womask_379; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_315 = {hi_746, flags_0_go, _out_prepend_T_315}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_4062 = out_prepend_315; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_4063 = _out_T_4062; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_316 = _out_T_4063; // @[RegisterRouter.scala:87:24]
wire out_rimask_380 = |_out_rimask_T_380; // @[RegisterRouter.scala:87:24]
wire out_wimask_380 = &_out_wimask_T_380; // @[RegisterRouter.scala:87:24]
wire out_romask_380 = |_out_romask_T_380; // @[RegisterRouter.scala:87:24]
wire out_womask_380 = &_out_womask_T_380; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_380 = out_rivalid_1_234 & out_rimask_380; // @[RegisterRouter.scala:87:24]
wire _out_T_4065 = out_f_rivalid_380; // @[RegisterRouter.scala:87:24]
wire out_f_roready_380 = out_roready_1_234 & out_romask_380; // @[RegisterRouter.scala:87:24]
wire _out_T_4066 = out_f_roready_380; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_380 = out_wivalid_1_234 & out_wimask_380; // @[RegisterRouter.scala:87:24]
wire out_f_woready_380 = out_woready_1_234 & out_womask_380; // @[RegisterRouter.scala:87:24]
wire _out_T_4067 = ~out_rimask_380; // @[RegisterRouter.scala:87:24]
wire _out_T_4068 = ~out_wimask_380; // @[RegisterRouter.scala:87:24]
wire _out_T_4069 = ~out_romask_380; // @[RegisterRouter.scala:87:24]
wire _out_T_4070 = ~out_womask_380; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_316 = {hi_747, flags_0_go, _out_prepend_T_316}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_4071 = out_prepend_316; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_4072 = _out_T_4071; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_317 = _out_T_4072; // @[RegisterRouter.scala:87:24]
wire out_rimask_381 = |_out_rimask_T_381; // @[RegisterRouter.scala:87:24]
wire out_wimask_381 = &_out_wimask_T_381; // @[RegisterRouter.scala:87:24]
wire out_romask_381 = |_out_romask_T_381; // @[RegisterRouter.scala:87:24]
wire out_womask_381 = &_out_womask_T_381; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_381 = out_rivalid_1_235 & out_rimask_381; // @[RegisterRouter.scala:87:24]
wire _out_T_4074 = out_f_rivalid_381; // @[RegisterRouter.scala:87:24]
wire out_f_roready_381 = out_roready_1_235 & out_romask_381; // @[RegisterRouter.scala:87:24]
wire _out_T_4075 = out_f_roready_381; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_381 = out_wivalid_1_235 & out_wimask_381; // @[RegisterRouter.scala:87:24]
wire out_f_woready_381 = out_woready_1_235 & out_womask_381; // @[RegisterRouter.scala:87:24]
wire _out_T_4076 = ~out_rimask_381; // @[RegisterRouter.scala:87:24]
wire _out_T_4077 = ~out_wimask_381; // @[RegisterRouter.scala:87:24]
wire _out_T_4078 = ~out_romask_381; // @[RegisterRouter.scala:87:24]
wire _out_T_4079 = ~out_womask_381; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_317 = {hi_748, flags_0_go, _out_prepend_T_317}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_4080 = out_prepend_317; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_4081 = _out_T_4080; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_318 = _out_T_4081; // @[RegisterRouter.scala:87:24]
wire out_rimask_382 = |_out_rimask_T_382; // @[RegisterRouter.scala:87:24]
wire out_wimask_382 = &_out_wimask_T_382; // @[RegisterRouter.scala:87:24]
wire out_romask_382 = |_out_romask_T_382; // @[RegisterRouter.scala:87:24]
wire out_womask_382 = &_out_womask_T_382; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_382 = out_rivalid_1_236 & out_rimask_382; // @[RegisterRouter.scala:87:24]
wire _out_T_4083 = out_f_rivalid_382; // @[RegisterRouter.scala:87:24]
wire out_f_roready_382 = out_roready_1_236 & out_romask_382; // @[RegisterRouter.scala:87:24]
wire _out_T_4084 = out_f_roready_382; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_382 = out_wivalid_1_236 & out_wimask_382; // @[RegisterRouter.scala:87:24]
wire out_f_woready_382 = out_woready_1_236 & out_womask_382; // @[RegisterRouter.scala:87:24]
wire _out_T_4085 = ~out_rimask_382; // @[RegisterRouter.scala:87:24]
wire _out_T_4086 = ~out_wimask_382; // @[RegisterRouter.scala:87:24]
wire _out_T_4087 = ~out_romask_382; // @[RegisterRouter.scala:87:24]
wire _out_T_4088 = ~out_womask_382; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_318 = {hi_749, flags_0_go, _out_prepend_T_318}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_4089 = out_prepend_318; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_4090 = _out_T_4089; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_319 = _out_T_4090; // @[RegisterRouter.scala:87:24]
wire out_rimask_383 = |_out_rimask_T_383; // @[RegisterRouter.scala:87:24]
wire out_wimask_383 = &_out_wimask_T_383; // @[RegisterRouter.scala:87:24]
wire out_romask_383 = |_out_romask_T_383; // @[RegisterRouter.scala:87:24]
wire out_womask_383 = &_out_womask_T_383; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_383 = out_rivalid_1_237 & out_rimask_383; // @[RegisterRouter.scala:87:24]
wire _out_T_4092 = out_f_rivalid_383; // @[RegisterRouter.scala:87:24]
wire out_f_roready_383 = out_roready_1_237 & out_romask_383; // @[RegisterRouter.scala:87:24]
wire _out_T_4093 = out_f_roready_383; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_383 = out_wivalid_1_237 & out_wimask_383; // @[RegisterRouter.scala:87:24]
wire out_f_woready_383 = out_woready_1_237 & out_womask_383; // @[RegisterRouter.scala:87:24]
wire _out_T_4094 = ~out_rimask_383; // @[RegisterRouter.scala:87:24]
wire _out_T_4095 = ~out_wimask_383; // @[RegisterRouter.scala:87:24]
wire _out_T_4096 = ~out_romask_383; // @[RegisterRouter.scala:87:24]
wire _out_T_4097 = ~out_womask_383; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_319 = {hi_750, flags_0_go, _out_prepend_T_319}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_4098 = out_prepend_319; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_4099 = _out_T_4098; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_320 = _out_T_4099; // @[RegisterRouter.scala:87:24]
wire out_rimask_384 = |_out_rimask_T_384; // @[RegisterRouter.scala:87:24]
wire out_wimask_384 = &_out_wimask_T_384; // @[RegisterRouter.scala:87:24]
wire out_romask_384 = |_out_romask_T_384; // @[RegisterRouter.scala:87:24]
wire out_womask_384 = &_out_womask_T_384; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_384 = out_rivalid_1_238 & out_rimask_384; // @[RegisterRouter.scala:87:24]
wire _out_T_4101 = out_f_rivalid_384; // @[RegisterRouter.scala:87:24]
wire out_f_roready_384 = out_roready_1_238 & out_romask_384; // @[RegisterRouter.scala:87:24]
wire _out_T_4102 = out_f_roready_384; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_384 = out_wivalid_1_238 & out_wimask_384; // @[RegisterRouter.scala:87:24]
wire out_f_woready_384 = out_woready_1_238 & out_womask_384; // @[RegisterRouter.scala:87:24]
wire _out_T_4103 = ~out_rimask_384; // @[RegisterRouter.scala:87:24]
wire _out_T_4104 = ~out_wimask_384; // @[RegisterRouter.scala:87:24]
wire _out_T_4105 = ~out_romask_384; // @[RegisterRouter.scala:87:24]
wire _out_T_4106 = ~out_womask_384; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_320 = {hi_751, flags_0_go, _out_prepend_T_320}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_4107 = out_prepend_320; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_4108 = _out_T_4107; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_321 = _out_T_4108; // @[RegisterRouter.scala:87:24]
wire out_rimask_385 = |_out_rimask_T_385; // @[RegisterRouter.scala:87:24]
wire out_wimask_385 = &_out_wimask_T_385; // @[RegisterRouter.scala:87:24]
wire out_romask_385 = |_out_romask_T_385; // @[RegisterRouter.scala:87:24]
wire out_womask_385 = &_out_womask_T_385; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_385 = out_rivalid_1_239 & out_rimask_385; // @[RegisterRouter.scala:87:24]
wire _out_T_4110 = out_f_rivalid_385; // @[RegisterRouter.scala:87:24]
wire out_f_roready_385 = out_roready_1_239 & out_romask_385; // @[RegisterRouter.scala:87:24]
wire _out_T_4111 = out_f_roready_385; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_385 = out_wivalid_1_239 & out_wimask_385; // @[RegisterRouter.scala:87:24]
wire out_f_woready_385 = out_woready_1_239 & out_womask_385; // @[RegisterRouter.scala:87:24]
wire _out_T_4112 = ~out_rimask_385; // @[RegisterRouter.scala:87:24]
wire _out_T_4113 = ~out_wimask_385; // @[RegisterRouter.scala:87:24]
wire _out_T_4114 = ~out_romask_385; // @[RegisterRouter.scala:87:24]
wire _out_T_4115 = ~out_womask_385; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_321 = {hi_752, flags_0_go, _out_prepend_T_321}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_4116 = out_prepend_321; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_4117 = _out_T_4116; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_221 = _out_T_4117; // @[MuxLiteral.scala:49:48]
wire out_rimask_386 = |_out_rimask_T_386; // @[RegisterRouter.scala:87:24]
wire out_wimask_386 = &_out_wimask_T_386; // @[RegisterRouter.scala:87:24]
wire out_romask_386 = |_out_romask_T_386; // @[RegisterRouter.scala:87:24]
wire out_womask_386 = &_out_womask_T_386; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_386 = out_rivalid_1_240 & out_rimask_386; // @[RegisterRouter.scala:87:24]
wire _out_T_4119 = out_f_rivalid_386; // @[RegisterRouter.scala:87:24]
wire out_f_roready_386 = out_roready_1_240 & out_romask_386; // @[RegisterRouter.scala:87:24]
wire _out_T_4120 = out_f_roready_386; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_386 = out_wivalid_1_240 & out_wimask_386; // @[RegisterRouter.scala:87:24]
wire out_f_woready_386 = out_woready_1_240 & out_womask_386; // @[RegisterRouter.scala:87:24]
wire _out_T_4121 = ~out_rimask_386; // @[RegisterRouter.scala:87:24]
wire _out_T_4122 = ~out_wimask_386; // @[RegisterRouter.scala:87:24]
wire _out_T_4123 = ~out_romask_386; // @[RegisterRouter.scala:87:24]
wire _out_T_4124 = ~out_womask_386; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4126 = _out_T_4125; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_322 = _out_T_4126; // @[RegisterRouter.scala:87:24]
wire out_rimask_387 = |_out_rimask_T_387; // @[RegisterRouter.scala:87:24]
wire out_wimask_387 = &_out_wimask_T_387; // @[RegisterRouter.scala:87:24]
wire out_romask_387 = |_out_romask_T_387; // @[RegisterRouter.scala:87:24]
wire out_womask_387 = &_out_womask_T_387; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_387 = out_rivalid_1_241 & out_rimask_387; // @[RegisterRouter.scala:87:24]
wire _out_T_4128 = out_f_rivalid_387; // @[RegisterRouter.scala:87:24]
wire out_f_roready_387 = out_roready_1_241 & out_romask_387; // @[RegisterRouter.scala:87:24]
wire _out_T_4129 = out_f_roready_387; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_387 = out_wivalid_1_241 & out_wimask_387; // @[RegisterRouter.scala:87:24]
wire out_f_woready_387 = out_woready_1_241 & out_womask_387; // @[RegisterRouter.scala:87:24]
wire _out_T_4130 = ~out_rimask_387; // @[RegisterRouter.scala:87:24]
wire _out_T_4131 = ~out_wimask_387; // @[RegisterRouter.scala:87:24]
wire _out_T_4132 = ~out_romask_387; // @[RegisterRouter.scala:87:24]
wire _out_T_4133 = ~out_womask_387; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_322 = {hi_34, flags_0_go, _out_prepend_T_322}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_4134 = out_prepend_322; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_4135 = _out_T_4134; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_323 = _out_T_4135; // @[RegisterRouter.scala:87:24]
wire out_rimask_388 = |_out_rimask_T_388; // @[RegisterRouter.scala:87:24]
wire out_wimask_388 = &_out_wimask_T_388; // @[RegisterRouter.scala:87:24]
wire out_romask_388 = |_out_romask_T_388; // @[RegisterRouter.scala:87:24]
wire out_womask_388 = &_out_womask_T_388; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_388 = out_rivalid_1_242 & out_rimask_388; // @[RegisterRouter.scala:87:24]
wire _out_T_4137 = out_f_rivalid_388; // @[RegisterRouter.scala:87:24]
wire out_f_roready_388 = out_roready_1_242 & out_romask_388; // @[RegisterRouter.scala:87:24]
wire _out_T_4138 = out_f_roready_388; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_388 = out_wivalid_1_242 & out_wimask_388; // @[RegisterRouter.scala:87:24]
wire out_f_woready_388 = out_woready_1_242 & out_womask_388; // @[RegisterRouter.scala:87:24]
wire _out_T_4139 = ~out_rimask_388; // @[RegisterRouter.scala:87:24]
wire _out_T_4140 = ~out_wimask_388; // @[RegisterRouter.scala:87:24]
wire _out_T_4141 = ~out_romask_388; // @[RegisterRouter.scala:87:24]
wire _out_T_4142 = ~out_womask_388; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_323 = {hi_35, flags_0_go, _out_prepend_T_323}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_4143 = out_prepend_323; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_4144 = _out_T_4143; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_324 = _out_T_4144; // @[RegisterRouter.scala:87:24]
wire out_rimask_389 = |_out_rimask_T_389; // @[RegisterRouter.scala:87:24]
wire out_wimask_389 = &_out_wimask_T_389; // @[RegisterRouter.scala:87:24]
wire out_romask_389 = |_out_romask_T_389; // @[RegisterRouter.scala:87:24]
wire out_womask_389 = &_out_womask_T_389; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_389 = out_rivalid_1_243 & out_rimask_389; // @[RegisterRouter.scala:87:24]
wire _out_T_4146 = out_f_rivalid_389; // @[RegisterRouter.scala:87:24]
wire out_f_roready_389 = out_roready_1_243 & out_romask_389; // @[RegisterRouter.scala:87:24]
wire _out_T_4147 = out_f_roready_389; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_389 = out_wivalid_1_243 & out_wimask_389; // @[RegisterRouter.scala:87:24]
wire out_f_woready_389 = out_woready_1_243 & out_womask_389; // @[RegisterRouter.scala:87:24]
wire _out_T_4148 = ~out_rimask_389; // @[RegisterRouter.scala:87:24]
wire _out_T_4149 = ~out_wimask_389; // @[RegisterRouter.scala:87:24]
wire _out_T_4150 = ~out_romask_389; // @[RegisterRouter.scala:87:24]
wire _out_T_4151 = ~out_womask_389; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_324 = {hi_36, flags_0_go, _out_prepend_T_324}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_4152 = out_prepend_324; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_4153 = _out_T_4152; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_325 = _out_T_4153; // @[RegisterRouter.scala:87:24]
wire out_rimask_390 = |_out_rimask_T_390; // @[RegisterRouter.scala:87:24]
wire out_wimask_390 = &_out_wimask_T_390; // @[RegisterRouter.scala:87:24]
wire out_romask_390 = |_out_romask_T_390; // @[RegisterRouter.scala:87:24]
wire out_womask_390 = &_out_womask_T_390; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_390 = out_rivalid_1_244 & out_rimask_390; // @[RegisterRouter.scala:87:24]
wire _out_T_4155 = out_f_rivalid_390; // @[RegisterRouter.scala:87:24]
wire out_f_roready_390 = out_roready_1_244 & out_romask_390; // @[RegisterRouter.scala:87:24]
wire _out_T_4156 = out_f_roready_390; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_390 = out_wivalid_1_244 & out_wimask_390; // @[RegisterRouter.scala:87:24]
wire out_f_woready_390 = out_woready_1_244 & out_womask_390; // @[RegisterRouter.scala:87:24]
wire _out_T_4157 = ~out_rimask_390; // @[RegisterRouter.scala:87:24]
wire _out_T_4158 = ~out_wimask_390; // @[RegisterRouter.scala:87:24]
wire _out_T_4159 = ~out_romask_390; // @[RegisterRouter.scala:87:24]
wire _out_T_4160 = ~out_womask_390; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_325 = {hi_37, flags_0_go, _out_prepend_T_325}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_4161 = out_prepend_325; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_4162 = _out_T_4161; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_326 = _out_T_4162; // @[RegisterRouter.scala:87:24]
wire out_rimask_391 = |_out_rimask_T_391; // @[RegisterRouter.scala:87:24]
wire out_wimask_391 = &_out_wimask_T_391; // @[RegisterRouter.scala:87:24]
wire out_romask_391 = |_out_romask_T_391; // @[RegisterRouter.scala:87:24]
wire out_womask_391 = &_out_womask_T_391; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_391 = out_rivalid_1_245 & out_rimask_391; // @[RegisterRouter.scala:87:24]
wire _out_T_4164 = out_f_rivalid_391; // @[RegisterRouter.scala:87:24]
wire out_f_roready_391 = out_roready_1_245 & out_romask_391; // @[RegisterRouter.scala:87:24]
wire _out_T_4165 = out_f_roready_391; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_391 = out_wivalid_1_245 & out_wimask_391; // @[RegisterRouter.scala:87:24]
wire out_f_woready_391 = out_woready_1_245 & out_womask_391; // @[RegisterRouter.scala:87:24]
wire _out_T_4166 = ~out_rimask_391; // @[RegisterRouter.scala:87:24]
wire _out_T_4167 = ~out_wimask_391; // @[RegisterRouter.scala:87:24]
wire _out_T_4168 = ~out_romask_391; // @[RegisterRouter.scala:87:24]
wire _out_T_4169 = ~out_womask_391; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_326 = {hi_38, flags_0_go, _out_prepend_T_326}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_4170 = out_prepend_326; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_4171 = _out_T_4170; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_327 = _out_T_4171; // @[RegisterRouter.scala:87:24]
wire out_rimask_392 = |_out_rimask_T_392; // @[RegisterRouter.scala:87:24]
wire out_wimask_392 = &_out_wimask_T_392; // @[RegisterRouter.scala:87:24]
wire out_romask_392 = |_out_romask_T_392; // @[RegisterRouter.scala:87:24]
wire out_womask_392 = &_out_womask_T_392; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_392 = out_rivalid_1_246 & out_rimask_392; // @[RegisterRouter.scala:87:24]
wire _out_T_4173 = out_f_rivalid_392; // @[RegisterRouter.scala:87:24]
wire out_f_roready_392 = out_roready_1_246 & out_romask_392; // @[RegisterRouter.scala:87:24]
wire _out_T_4174 = out_f_roready_392; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_392 = out_wivalid_1_246 & out_wimask_392; // @[RegisterRouter.scala:87:24]
wire out_f_woready_392 = out_woready_1_246 & out_womask_392; // @[RegisterRouter.scala:87:24]
wire _out_T_4175 = ~out_rimask_392; // @[RegisterRouter.scala:87:24]
wire _out_T_4176 = ~out_wimask_392; // @[RegisterRouter.scala:87:24]
wire _out_T_4177 = ~out_romask_392; // @[RegisterRouter.scala:87:24]
wire _out_T_4178 = ~out_womask_392; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_327 = {hi_39, flags_0_go, _out_prepend_T_327}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_4179 = out_prepend_327; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_4180 = _out_T_4179; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_328 = _out_T_4180; // @[RegisterRouter.scala:87:24]
wire out_rimask_393 = |_out_rimask_T_393; // @[RegisterRouter.scala:87:24]
wire out_wimask_393 = &_out_wimask_T_393; // @[RegisterRouter.scala:87:24]
wire out_romask_393 = |_out_romask_T_393; // @[RegisterRouter.scala:87:24]
wire out_womask_393 = &_out_womask_T_393; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_393 = out_rivalid_1_247 & out_rimask_393; // @[RegisterRouter.scala:87:24]
wire _out_T_4182 = out_f_rivalid_393; // @[RegisterRouter.scala:87:24]
wire out_f_roready_393 = out_roready_1_247 & out_romask_393; // @[RegisterRouter.scala:87:24]
wire _out_T_4183 = out_f_roready_393; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_393 = out_wivalid_1_247 & out_wimask_393; // @[RegisterRouter.scala:87:24]
wire out_f_woready_393 = out_woready_1_247 & out_womask_393; // @[RegisterRouter.scala:87:24]
wire _out_T_4184 = ~out_rimask_393; // @[RegisterRouter.scala:87:24]
wire _out_T_4185 = ~out_wimask_393; // @[RegisterRouter.scala:87:24]
wire _out_T_4186 = ~out_romask_393; // @[RegisterRouter.scala:87:24]
wire _out_T_4187 = ~out_womask_393; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_328 = {hi_40, flags_0_go, _out_prepend_T_328}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_4188 = out_prepend_328; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_4189 = _out_T_4188; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_132 = _out_T_4189; // @[MuxLiteral.scala:49:48]
wire out_rimask_394 = |_out_rimask_T_394; // @[RegisterRouter.scala:87:24]
wire out_wimask_394 = &_out_wimask_T_394; // @[RegisterRouter.scala:87:24]
wire out_romask_394 = |_out_romask_T_394; // @[RegisterRouter.scala:87:24]
wire out_womask_394 = &_out_womask_T_394; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_394 = out_rivalid_1_248 & out_rimask_394; // @[RegisterRouter.scala:87:24]
wire _out_T_4191 = out_f_rivalid_394; // @[RegisterRouter.scala:87:24]
wire out_f_roready_394 = out_roready_1_248 & out_romask_394; // @[RegisterRouter.scala:87:24]
wire _out_T_4192 = out_f_roready_394; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_394 = out_wivalid_1_248 & out_wimask_394; // @[RegisterRouter.scala:87:24]
wire out_f_woready_394 = out_woready_1_248 & out_womask_394; // @[RegisterRouter.scala:87:24]
wire _out_T_4193 = ~out_rimask_394; // @[RegisterRouter.scala:87:24]
wire _out_T_4194 = ~out_wimask_394; // @[RegisterRouter.scala:87:24]
wire _out_T_4195 = ~out_romask_394; // @[RegisterRouter.scala:87:24]
wire _out_T_4196 = ~out_womask_394; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4198 = _out_T_4197; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_329 = _out_T_4198; // @[RegisterRouter.scala:87:24]
wire out_rimask_395 = |_out_rimask_T_395; // @[RegisterRouter.scala:87:24]
wire out_wimask_395 = &_out_wimask_T_395; // @[RegisterRouter.scala:87:24]
wire out_romask_395 = |_out_romask_T_395; // @[RegisterRouter.scala:87:24]
wire out_womask_395 = &_out_womask_T_395; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_395 = out_rivalid_1_249 & out_rimask_395; // @[RegisterRouter.scala:87:24]
wire _out_T_4200 = out_f_rivalid_395; // @[RegisterRouter.scala:87:24]
wire out_f_roready_395 = out_roready_1_249 & out_romask_395; // @[RegisterRouter.scala:87:24]
wire _out_T_4201 = out_f_roready_395; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_395 = out_wivalid_1_249 & out_wimask_395; // @[RegisterRouter.scala:87:24]
wire out_f_woready_395 = out_woready_1_249 & out_womask_395; // @[RegisterRouter.scala:87:24]
wire _out_T_4202 = ~out_rimask_395; // @[RegisterRouter.scala:87:24]
wire _out_T_4203 = ~out_wimask_395; // @[RegisterRouter.scala:87:24]
wire _out_T_4204 = ~out_romask_395; // @[RegisterRouter.scala:87:24]
wire _out_T_4205 = ~out_womask_395; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_329 = {hi_42, flags_0_go, _out_prepend_T_329}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_4206 = out_prepend_329; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_4207 = _out_T_4206; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_330 = _out_T_4207; // @[RegisterRouter.scala:87:24]
wire out_rimask_396 = |_out_rimask_T_396; // @[RegisterRouter.scala:87:24]
wire out_wimask_396 = &_out_wimask_T_396; // @[RegisterRouter.scala:87:24]
wire out_romask_396 = |_out_romask_T_396; // @[RegisterRouter.scala:87:24]
wire out_womask_396 = &_out_womask_T_396; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_396 = out_rivalid_1_250 & out_rimask_396; // @[RegisterRouter.scala:87:24]
wire _out_T_4209 = out_f_rivalid_396; // @[RegisterRouter.scala:87:24]
wire out_f_roready_396 = out_roready_1_250 & out_romask_396; // @[RegisterRouter.scala:87:24]
wire _out_T_4210 = out_f_roready_396; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_396 = out_wivalid_1_250 & out_wimask_396; // @[RegisterRouter.scala:87:24]
wire out_f_woready_396 = out_woready_1_250 & out_womask_396; // @[RegisterRouter.scala:87:24]
wire _out_T_4211 = ~out_rimask_396; // @[RegisterRouter.scala:87:24]
wire _out_T_4212 = ~out_wimask_396; // @[RegisterRouter.scala:87:24]
wire _out_T_4213 = ~out_romask_396; // @[RegisterRouter.scala:87:24]
wire _out_T_4214 = ~out_womask_396; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_330 = {hi_43, flags_0_go, _out_prepend_T_330}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_4215 = out_prepend_330; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_4216 = _out_T_4215; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_331 = _out_T_4216; // @[RegisterRouter.scala:87:24]
wire out_rimask_397 = |_out_rimask_T_397; // @[RegisterRouter.scala:87:24]
wire out_wimask_397 = &_out_wimask_T_397; // @[RegisterRouter.scala:87:24]
wire out_romask_397 = |_out_romask_T_397; // @[RegisterRouter.scala:87:24]
wire out_womask_397 = &_out_womask_T_397; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_397 = out_rivalid_1_251 & out_rimask_397; // @[RegisterRouter.scala:87:24]
wire _out_T_4218 = out_f_rivalid_397; // @[RegisterRouter.scala:87:24]
wire out_f_roready_397 = out_roready_1_251 & out_romask_397; // @[RegisterRouter.scala:87:24]
wire _out_T_4219 = out_f_roready_397; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_397 = out_wivalid_1_251 & out_wimask_397; // @[RegisterRouter.scala:87:24]
wire out_f_woready_397 = out_woready_1_251 & out_womask_397; // @[RegisterRouter.scala:87:24]
wire _out_T_4220 = ~out_rimask_397; // @[RegisterRouter.scala:87:24]
wire _out_T_4221 = ~out_wimask_397; // @[RegisterRouter.scala:87:24]
wire _out_T_4222 = ~out_romask_397; // @[RegisterRouter.scala:87:24]
wire _out_T_4223 = ~out_womask_397; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_331 = {hi_44, flags_0_go, _out_prepend_T_331}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_4224 = out_prepend_331; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_4225 = _out_T_4224; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_332 = _out_T_4225; // @[RegisterRouter.scala:87:24]
wire out_rimask_398 = |_out_rimask_T_398; // @[RegisterRouter.scala:87:24]
wire out_wimask_398 = &_out_wimask_T_398; // @[RegisterRouter.scala:87:24]
wire out_romask_398 = |_out_romask_T_398; // @[RegisterRouter.scala:87:24]
wire out_womask_398 = &_out_womask_T_398; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_398 = out_rivalid_1_252 & out_rimask_398; // @[RegisterRouter.scala:87:24]
wire _out_T_4227 = out_f_rivalid_398; // @[RegisterRouter.scala:87:24]
wire out_f_roready_398 = out_roready_1_252 & out_romask_398; // @[RegisterRouter.scala:87:24]
wire _out_T_4228 = out_f_roready_398; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_398 = out_wivalid_1_252 & out_wimask_398; // @[RegisterRouter.scala:87:24]
wire out_f_woready_398 = out_woready_1_252 & out_womask_398; // @[RegisterRouter.scala:87:24]
wire _out_T_4229 = ~out_rimask_398; // @[RegisterRouter.scala:87:24]
wire _out_T_4230 = ~out_wimask_398; // @[RegisterRouter.scala:87:24]
wire _out_T_4231 = ~out_romask_398; // @[RegisterRouter.scala:87:24]
wire _out_T_4232 = ~out_womask_398; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_332 = {hi_45, flags_0_go, _out_prepend_T_332}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_4233 = out_prepend_332; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_4234 = _out_T_4233; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_333 = _out_T_4234; // @[RegisterRouter.scala:87:24]
wire out_rimask_399 = |_out_rimask_T_399; // @[RegisterRouter.scala:87:24]
wire out_wimask_399 = &_out_wimask_T_399; // @[RegisterRouter.scala:87:24]
wire out_romask_399 = |_out_romask_T_399; // @[RegisterRouter.scala:87:24]
wire out_womask_399 = &_out_womask_T_399; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_399 = out_rivalid_1_253 & out_rimask_399; // @[RegisterRouter.scala:87:24]
wire _out_T_4236 = out_f_rivalid_399; // @[RegisterRouter.scala:87:24]
wire out_f_roready_399 = out_roready_1_253 & out_romask_399; // @[RegisterRouter.scala:87:24]
wire _out_T_4237 = out_f_roready_399; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_399 = out_wivalid_1_253 & out_wimask_399; // @[RegisterRouter.scala:87:24]
wire out_f_woready_399 = out_woready_1_253 & out_womask_399; // @[RegisterRouter.scala:87:24]
wire _out_T_4238 = ~out_rimask_399; // @[RegisterRouter.scala:87:24]
wire _out_T_4239 = ~out_wimask_399; // @[RegisterRouter.scala:87:24]
wire _out_T_4240 = ~out_romask_399; // @[RegisterRouter.scala:87:24]
wire _out_T_4241 = ~out_womask_399; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_333 = {hi_46, flags_0_go, _out_prepend_T_333}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_4242 = out_prepend_333; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_4243 = _out_T_4242; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_334 = _out_T_4243; // @[RegisterRouter.scala:87:24]
wire out_rimask_400 = |_out_rimask_T_400; // @[RegisterRouter.scala:87:24]
wire out_wimask_400 = &_out_wimask_T_400; // @[RegisterRouter.scala:87:24]
wire out_romask_400 = |_out_romask_T_400; // @[RegisterRouter.scala:87:24]
wire out_womask_400 = &_out_womask_T_400; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_400 = out_rivalid_1_254 & out_rimask_400; // @[RegisterRouter.scala:87:24]
wire _out_T_4245 = out_f_rivalid_400; // @[RegisterRouter.scala:87:24]
wire out_f_roready_400 = out_roready_1_254 & out_romask_400; // @[RegisterRouter.scala:87:24]
wire _out_T_4246 = out_f_roready_400; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_400 = out_wivalid_1_254 & out_wimask_400; // @[RegisterRouter.scala:87:24]
wire out_f_woready_400 = out_woready_1_254 & out_womask_400; // @[RegisterRouter.scala:87:24]
wire _out_T_4247 = ~out_rimask_400; // @[RegisterRouter.scala:87:24]
wire _out_T_4248 = ~out_wimask_400; // @[RegisterRouter.scala:87:24]
wire _out_T_4249 = ~out_romask_400; // @[RegisterRouter.scala:87:24]
wire _out_T_4250 = ~out_womask_400; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_334 = {hi_47, flags_0_go, _out_prepend_T_334}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_4251 = out_prepend_334; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_4252 = _out_T_4251; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_335 = _out_T_4252; // @[RegisterRouter.scala:87:24]
wire out_rimask_401 = |_out_rimask_T_401; // @[RegisterRouter.scala:87:24]
wire out_wimask_401 = &_out_wimask_T_401; // @[RegisterRouter.scala:87:24]
wire out_romask_401 = |_out_romask_T_401; // @[RegisterRouter.scala:87:24]
wire out_womask_401 = &_out_womask_T_401; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_401 = out_rivalid_1_255 & out_rimask_401; // @[RegisterRouter.scala:87:24]
wire _out_T_4254 = out_f_rivalid_401; // @[RegisterRouter.scala:87:24]
wire out_f_roready_401 = out_roready_1_255 & out_romask_401; // @[RegisterRouter.scala:87:24]
wire _out_T_4255 = out_f_roready_401; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_401 = out_wivalid_1_255 & out_wimask_401; // @[RegisterRouter.scala:87:24]
wire out_f_woready_401 = out_woready_1_255 & out_womask_401; // @[RegisterRouter.scala:87:24]
wire _out_T_4256 = ~out_rimask_401; // @[RegisterRouter.scala:87:24]
wire _out_T_4257 = ~out_wimask_401; // @[RegisterRouter.scala:87:24]
wire _out_T_4258 = ~out_romask_401; // @[RegisterRouter.scala:87:24]
wire _out_T_4259 = ~out_womask_401; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_335 = {hi_48, flags_0_go, _out_prepend_T_335}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_4260 = out_prepend_335; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_4261 = _out_T_4260; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_133 = _out_T_4261; // @[MuxLiteral.scala:49:48]
wire out_rimask_402 = |_out_rimask_T_402; // @[RegisterRouter.scala:87:24]
wire out_wimask_402 = &_out_wimask_T_402; // @[RegisterRouter.scala:87:24]
wire out_romask_402 = |_out_romask_T_402; // @[RegisterRouter.scala:87:24]
wire out_womask_402 = &_out_womask_T_402; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_402 = out_rivalid_1_256 & out_rimask_402; // @[RegisterRouter.scala:87:24]
wire _out_T_4263 = out_f_rivalid_402; // @[RegisterRouter.scala:87:24]
wire out_f_roready_402 = out_roready_1_256 & out_romask_402; // @[RegisterRouter.scala:87:24]
wire _out_T_4264 = out_f_roready_402; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_402 = out_wivalid_1_256 & out_wimask_402; // @[RegisterRouter.scala:87:24]
wire out_f_woready_402 = out_woready_1_256 & out_womask_402; // @[RegisterRouter.scala:87:24]
wire _out_T_4265 = ~out_rimask_402; // @[RegisterRouter.scala:87:24]
wire _out_T_4266 = ~out_wimask_402; // @[RegisterRouter.scala:87:24]
wire _out_T_4267 = ~out_romask_402; // @[RegisterRouter.scala:87:24]
wire _out_T_4268 = ~out_womask_402; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4270 = _out_T_4269; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_336 = _out_T_4270; // @[RegisterRouter.scala:87:24]
wire out_rimask_403 = |_out_rimask_T_403; // @[RegisterRouter.scala:87:24]
wire out_wimask_403 = &_out_wimask_T_403; // @[RegisterRouter.scala:87:24]
wire out_romask_403 = |_out_romask_T_403; // @[RegisterRouter.scala:87:24]
wire out_womask_403 = &_out_womask_T_403; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_403 = out_rivalid_1_257 & out_rimask_403; // @[RegisterRouter.scala:87:24]
wire _out_T_4272 = out_f_rivalid_403; // @[RegisterRouter.scala:87:24]
wire out_f_roready_403 = out_roready_1_257 & out_romask_403; // @[RegisterRouter.scala:87:24]
wire _out_T_4273 = out_f_roready_403; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_403 = out_wivalid_1_257 & out_wimask_403; // @[RegisterRouter.scala:87:24]
wire out_f_woready_403 = out_woready_1_257 & out_womask_403; // @[RegisterRouter.scala:87:24]
wire _out_T_4274 = ~out_rimask_403; // @[RegisterRouter.scala:87:24]
wire _out_T_4275 = ~out_wimask_403; // @[RegisterRouter.scala:87:24]
wire _out_T_4276 = ~out_romask_403; // @[RegisterRouter.scala:87:24]
wire _out_T_4277 = ~out_womask_403; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_336 = {hi_922, flags_0_go, _out_prepend_T_336}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_4278 = out_prepend_336; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_4279 = _out_T_4278; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_337 = _out_T_4279; // @[RegisterRouter.scala:87:24]
wire out_rimask_404 = |_out_rimask_T_404; // @[RegisterRouter.scala:87:24]
wire out_wimask_404 = &_out_wimask_T_404; // @[RegisterRouter.scala:87:24]
wire out_romask_404 = |_out_romask_T_404; // @[RegisterRouter.scala:87:24]
wire out_womask_404 = &_out_womask_T_404; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_404 = out_rivalid_1_258 & out_rimask_404; // @[RegisterRouter.scala:87:24]
wire _out_T_4281 = out_f_rivalid_404; // @[RegisterRouter.scala:87:24]
wire out_f_roready_404 = out_roready_1_258 & out_romask_404; // @[RegisterRouter.scala:87:24]
wire _out_T_4282 = out_f_roready_404; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_404 = out_wivalid_1_258 & out_wimask_404; // @[RegisterRouter.scala:87:24]
wire out_f_woready_404 = out_woready_1_258 & out_womask_404; // @[RegisterRouter.scala:87:24]
wire _out_T_4283 = ~out_rimask_404; // @[RegisterRouter.scala:87:24]
wire _out_T_4284 = ~out_wimask_404; // @[RegisterRouter.scala:87:24]
wire _out_T_4285 = ~out_romask_404; // @[RegisterRouter.scala:87:24]
wire _out_T_4286 = ~out_womask_404; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_337 = {hi_923, flags_0_go, _out_prepend_T_337}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_4287 = out_prepend_337; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_4288 = _out_T_4287; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_338 = _out_T_4288; // @[RegisterRouter.scala:87:24]
wire out_rimask_405 = |_out_rimask_T_405; // @[RegisterRouter.scala:87:24]
wire out_wimask_405 = &_out_wimask_T_405; // @[RegisterRouter.scala:87:24]
wire out_romask_405 = |_out_romask_T_405; // @[RegisterRouter.scala:87:24]
wire out_womask_405 = &_out_womask_T_405; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_405 = out_rivalid_1_259 & out_rimask_405; // @[RegisterRouter.scala:87:24]
wire _out_T_4290 = out_f_rivalid_405; // @[RegisterRouter.scala:87:24]
wire out_f_roready_405 = out_roready_1_259 & out_romask_405; // @[RegisterRouter.scala:87:24]
wire _out_T_4291 = out_f_roready_405; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_405 = out_wivalid_1_259 & out_wimask_405; // @[RegisterRouter.scala:87:24]
wire out_f_woready_405 = out_woready_1_259 & out_womask_405; // @[RegisterRouter.scala:87:24]
wire _out_T_4292 = ~out_rimask_405; // @[RegisterRouter.scala:87:24]
wire _out_T_4293 = ~out_wimask_405; // @[RegisterRouter.scala:87:24]
wire _out_T_4294 = ~out_romask_405; // @[RegisterRouter.scala:87:24]
wire _out_T_4295 = ~out_womask_405; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_338 = {hi_924, flags_0_go, _out_prepend_T_338}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_4296 = out_prepend_338; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_4297 = _out_T_4296; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_339 = _out_T_4297; // @[RegisterRouter.scala:87:24]
wire out_rimask_406 = |_out_rimask_T_406; // @[RegisterRouter.scala:87:24]
wire out_wimask_406 = &_out_wimask_T_406; // @[RegisterRouter.scala:87:24]
wire out_romask_406 = |_out_romask_T_406; // @[RegisterRouter.scala:87:24]
wire out_womask_406 = &_out_womask_T_406; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_406 = out_rivalid_1_260 & out_rimask_406; // @[RegisterRouter.scala:87:24]
wire _out_T_4299 = out_f_rivalid_406; // @[RegisterRouter.scala:87:24]
wire out_f_roready_406 = out_roready_1_260 & out_romask_406; // @[RegisterRouter.scala:87:24]
wire _out_T_4300 = out_f_roready_406; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_406 = out_wivalid_1_260 & out_wimask_406; // @[RegisterRouter.scala:87:24]
wire out_f_woready_406 = out_woready_1_260 & out_womask_406; // @[RegisterRouter.scala:87:24]
wire _out_T_4301 = ~out_rimask_406; // @[RegisterRouter.scala:87:24]
wire _out_T_4302 = ~out_wimask_406; // @[RegisterRouter.scala:87:24]
wire _out_T_4303 = ~out_romask_406; // @[RegisterRouter.scala:87:24]
wire _out_T_4304 = ~out_womask_406; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_339 = {hi_925, flags_0_go, _out_prepend_T_339}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_4305 = out_prepend_339; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_4306 = _out_T_4305; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_340 = _out_T_4306; // @[RegisterRouter.scala:87:24]
wire out_rimask_407 = |_out_rimask_T_407; // @[RegisterRouter.scala:87:24]
wire out_wimask_407 = &_out_wimask_T_407; // @[RegisterRouter.scala:87:24]
wire out_romask_407 = |_out_romask_T_407; // @[RegisterRouter.scala:87:24]
wire out_womask_407 = &_out_womask_T_407; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_407 = out_rivalid_1_261 & out_rimask_407; // @[RegisterRouter.scala:87:24]
wire _out_T_4308 = out_f_rivalid_407; // @[RegisterRouter.scala:87:24]
wire out_f_roready_407 = out_roready_1_261 & out_romask_407; // @[RegisterRouter.scala:87:24]
wire _out_T_4309 = out_f_roready_407; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_407 = out_wivalid_1_261 & out_wimask_407; // @[RegisterRouter.scala:87:24]
wire out_f_woready_407 = out_woready_1_261 & out_womask_407; // @[RegisterRouter.scala:87:24]
wire _out_T_4310 = ~out_rimask_407; // @[RegisterRouter.scala:87:24]
wire _out_T_4311 = ~out_wimask_407; // @[RegisterRouter.scala:87:24]
wire _out_T_4312 = ~out_romask_407; // @[RegisterRouter.scala:87:24]
wire _out_T_4313 = ~out_womask_407; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_340 = {hi_926, flags_0_go, _out_prepend_T_340}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_4314 = out_prepend_340; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_4315 = _out_T_4314; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_341 = _out_T_4315; // @[RegisterRouter.scala:87:24]
wire out_rimask_408 = |_out_rimask_T_408; // @[RegisterRouter.scala:87:24]
wire out_wimask_408 = &_out_wimask_T_408; // @[RegisterRouter.scala:87:24]
wire out_romask_408 = |_out_romask_T_408; // @[RegisterRouter.scala:87:24]
wire out_womask_408 = &_out_womask_T_408; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_408 = out_rivalid_1_262 & out_rimask_408; // @[RegisterRouter.scala:87:24]
wire _out_T_4317 = out_f_rivalid_408; // @[RegisterRouter.scala:87:24]
wire out_f_roready_408 = out_roready_1_262 & out_romask_408; // @[RegisterRouter.scala:87:24]
wire _out_T_4318 = out_f_roready_408; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_408 = out_wivalid_1_262 & out_wimask_408; // @[RegisterRouter.scala:87:24]
wire out_f_woready_408 = out_woready_1_262 & out_womask_408; // @[RegisterRouter.scala:87:24]
wire _out_T_4319 = ~out_rimask_408; // @[RegisterRouter.scala:87:24]
wire _out_T_4320 = ~out_wimask_408; // @[RegisterRouter.scala:87:24]
wire _out_T_4321 = ~out_romask_408; // @[RegisterRouter.scala:87:24]
wire _out_T_4322 = ~out_womask_408; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_341 = {hi_927, flags_0_go, _out_prepend_T_341}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_4323 = out_prepend_341; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_4324 = _out_T_4323; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_342 = _out_T_4324; // @[RegisterRouter.scala:87:24]
wire out_rimask_409 = |_out_rimask_T_409; // @[RegisterRouter.scala:87:24]
wire out_wimask_409 = &_out_wimask_T_409; // @[RegisterRouter.scala:87:24]
wire out_romask_409 = |_out_romask_T_409; // @[RegisterRouter.scala:87:24]
wire out_womask_409 = &_out_womask_T_409; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_409 = out_rivalid_1_263 & out_rimask_409; // @[RegisterRouter.scala:87:24]
wire _out_T_4326 = out_f_rivalid_409; // @[RegisterRouter.scala:87:24]
wire out_f_roready_409 = out_roready_1_263 & out_romask_409; // @[RegisterRouter.scala:87:24]
wire _out_T_4327 = out_f_roready_409; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_409 = out_wivalid_1_263 & out_wimask_409; // @[RegisterRouter.scala:87:24]
wire out_f_woready_409 = out_woready_1_263 & out_womask_409; // @[RegisterRouter.scala:87:24]
wire _out_T_4328 = ~out_rimask_409; // @[RegisterRouter.scala:87:24]
wire _out_T_4329 = ~out_wimask_409; // @[RegisterRouter.scala:87:24]
wire _out_T_4330 = ~out_romask_409; // @[RegisterRouter.scala:87:24]
wire _out_T_4331 = ~out_womask_409; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_342 = {hi_928, flags_0_go, _out_prepend_T_342}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_4332 = out_prepend_342; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_4333 = _out_T_4332; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_243 = _out_T_4333; // @[MuxLiteral.scala:49:48]
wire out_rimask_410 = |_out_rimask_T_410; // @[RegisterRouter.scala:87:24]
wire out_wimask_410 = &_out_wimask_T_410; // @[RegisterRouter.scala:87:24]
wire out_romask_410 = |_out_romask_T_410; // @[RegisterRouter.scala:87:24]
wire out_womask_410 = &_out_womask_T_410; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_410 = out_rivalid_1_264 & out_rimask_410; // @[RegisterRouter.scala:87:24]
wire _out_T_4335 = out_f_rivalid_410; // @[RegisterRouter.scala:87:24]
wire out_f_roready_410 = out_roready_1_264 & out_romask_410; // @[RegisterRouter.scala:87:24]
wire _out_T_4336 = out_f_roready_410; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_410 = out_wivalid_1_264 & out_wimask_410; // @[RegisterRouter.scala:87:24]
wire out_f_woready_410 = out_woready_1_264 & out_womask_410; // @[RegisterRouter.scala:87:24]
wire _out_T_4337 = ~out_rimask_410; // @[RegisterRouter.scala:87:24]
wire _out_T_4338 = ~out_wimask_410; // @[RegisterRouter.scala:87:24]
wire _out_T_4339 = ~out_romask_410; // @[RegisterRouter.scala:87:24]
wire _out_T_4340 = ~out_womask_410; // @[RegisterRouter.scala:87:24]
wire out_rimask_411 = |_out_rimask_T_411; // @[RegisterRouter.scala:87:24]
wire out_wimask_411 = &_out_wimask_T_411; // @[RegisterRouter.scala:87:24]
wire out_romask_411 = |_out_romask_T_411; // @[RegisterRouter.scala:87:24]
wire out_womask_411 = &_out_womask_T_411; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_411 = out_rivalid_1_265 & out_rimask_411; // @[RegisterRouter.scala:87:24]
wire _out_T_4344 = out_f_rivalid_411; // @[RegisterRouter.scala:87:24]
wire out_f_roready_411 = out_roready_1_265 & out_romask_411; // @[RegisterRouter.scala:87:24]
wire _out_T_4345 = out_f_roready_411; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_411 = out_wivalid_1_265 & out_wimask_411; // @[RegisterRouter.scala:87:24]
wire out_f_woready_411 = out_woready_1_265 & out_womask_411; // @[RegisterRouter.scala:87:24]
wire _out_T_4346 = ~out_rimask_411; // @[RegisterRouter.scala:87:24]
wire _out_T_4347 = ~out_wimask_411; // @[RegisterRouter.scala:87:24]
wire _out_T_4348 = ~out_romask_411; // @[RegisterRouter.scala:87:24]
wire _out_T_4349 = ~out_womask_411; // @[RegisterRouter.scala:87:24]
wire out_rimask_412 = |_out_rimask_T_412; // @[RegisterRouter.scala:87:24]
wire out_wimask_412 = &_out_wimask_T_412; // @[RegisterRouter.scala:87:24]
wire out_romask_412 = |_out_romask_T_412; // @[RegisterRouter.scala:87:24]
wire out_womask_412 = &_out_womask_T_412; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_412 = out_rivalid_1_266 & out_rimask_412; // @[RegisterRouter.scala:87:24]
wire _out_T_4353 = out_f_rivalid_412; // @[RegisterRouter.scala:87:24]
wire out_f_roready_412 = out_roready_1_266 & out_romask_412; // @[RegisterRouter.scala:87:24]
wire _out_T_4354 = out_f_roready_412; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_412 = out_wivalid_1_266 & out_wimask_412; // @[RegisterRouter.scala:87:24]
wire out_f_woready_412 = out_woready_1_266 & out_womask_412; // @[RegisterRouter.scala:87:24]
wire _out_T_4355 = ~out_rimask_412; // @[RegisterRouter.scala:87:24]
wire _out_T_4356 = ~out_wimask_412; // @[RegisterRouter.scala:87:24]
wire _out_T_4357 = ~out_romask_412; // @[RegisterRouter.scala:87:24]
wire _out_T_4358 = ~out_womask_412; // @[RegisterRouter.scala:87:24]
wire out_rimask_413 = |_out_rimask_T_413; // @[RegisterRouter.scala:87:24]
wire out_wimask_413 = &_out_wimask_T_413; // @[RegisterRouter.scala:87:24]
wire out_romask_413 = |_out_romask_T_413; // @[RegisterRouter.scala:87:24]
wire out_womask_413 = &_out_womask_T_413; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_413 = out_rivalid_1_267 & out_rimask_413; // @[RegisterRouter.scala:87:24]
wire _out_T_4362 = out_f_rivalid_413; // @[RegisterRouter.scala:87:24]
wire out_f_roready_413 = out_roready_1_267 & out_romask_413; // @[RegisterRouter.scala:87:24]
wire _out_T_4363 = out_f_roready_413; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_413 = out_wivalid_1_267 & out_wimask_413; // @[RegisterRouter.scala:87:24]
wire out_f_woready_413 = out_woready_1_267 & out_womask_413; // @[RegisterRouter.scala:87:24]
wire _out_T_4364 = ~out_rimask_413; // @[RegisterRouter.scala:87:24]
wire _out_T_4365 = ~out_wimask_413; // @[RegisterRouter.scala:87:24]
wire _out_T_4366 = ~out_romask_413; // @[RegisterRouter.scala:87:24]
wire _out_T_4367 = ~out_womask_413; // @[RegisterRouter.scala:87:24]
wire out_rimask_414 = |_out_rimask_T_414; // @[RegisterRouter.scala:87:24]
wire out_wimask_414 = &_out_wimask_T_414; // @[RegisterRouter.scala:87:24]
wire out_romask_414 = |_out_romask_T_414; // @[RegisterRouter.scala:87:24]
wire out_womask_414 = &_out_womask_T_414; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_414 = out_rivalid_1_268 & out_rimask_414; // @[RegisterRouter.scala:87:24]
wire _out_T_4371 = out_f_rivalid_414; // @[RegisterRouter.scala:87:24]
wire out_f_roready_414 = out_roready_1_268 & out_romask_414; // @[RegisterRouter.scala:87:24]
wire _out_T_4372 = out_f_roready_414; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_414 = out_wivalid_1_268 & out_wimask_414; // @[RegisterRouter.scala:87:24]
wire out_f_woready_414 = out_woready_1_268 & out_womask_414; // @[RegisterRouter.scala:87:24]
wire _out_T_4373 = ~out_rimask_414; // @[RegisterRouter.scala:87:24]
wire _out_T_4374 = ~out_wimask_414; // @[RegisterRouter.scala:87:24]
wire _out_T_4375 = ~out_romask_414; // @[RegisterRouter.scala:87:24]
wire _out_T_4376 = ~out_womask_414; // @[RegisterRouter.scala:87:24]
wire out_rimask_415 = |_out_rimask_T_415; // @[RegisterRouter.scala:87:24]
wire out_wimask_415 = &_out_wimask_T_415; // @[RegisterRouter.scala:87:24]
wire out_romask_415 = |_out_romask_T_415; // @[RegisterRouter.scala:87:24]
wire out_womask_415 = &_out_womask_T_415; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_415 = out_rivalid_1_269 & out_rimask_415; // @[RegisterRouter.scala:87:24]
wire _out_T_4380 = out_f_rivalid_415; // @[RegisterRouter.scala:87:24]
wire out_f_roready_415 = out_roready_1_269 & out_romask_415; // @[RegisterRouter.scala:87:24]
wire _out_T_4381 = out_f_roready_415; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_415 = out_wivalid_1_269 & out_wimask_415; // @[RegisterRouter.scala:87:24]
wire out_f_woready_415 = out_woready_1_269 & out_womask_415; // @[RegisterRouter.scala:87:24]
wire _out_T_4382 = ~out_rimask_415; // @[RegisterRouter.scala:87:24]
wire _out_T_4383 = ~out_wimask_415; // @[RegisterRouter.scala:87:24]
wire _out_T_4384 = ~out_romask_415; // @[RegisterRouter.scala:87:24]
wire _out_T_4385 = ~out_womask_415; // @[RegisterRouter.scala:87:24]
wire out_rimask_416 = |_out_rimask_T_416; // @[RegisterRouter.scala:87:24]
wire out_wimask_416 = &_out_wimask_T_416; // @[RegisterRouter.scala:87:24]
wire out_romask_416 = |_out_romask_T_416; // @[RegisterRouter.scala:87:24]
wire out_womask_416 = &_out_womask_T_416; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_416 = out_rivalid_1_270 & out_rimask_416; // @[RegisterRouter.scala:87:24]
wire _out_T_4389 = out_f_rivalid_416; // @[RegisterRouter.scala:87:24]
wire out_f_roready_416 = out_roready_1_270 & out_romask_416; // @[RegisterRouter.scala:87:24]
wire _out_T_4390 = out_f_roready_416; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_416 = out_wivalid_1_270 & out_wimask_416; // @[RegisterRouter.scala:87:24]
wire out_f_woready_416 = out_woready_1_270 & out_womask_416; // @[RegisterRouter.scala:87:24]
wire _out_T_4391 = ~out_rimask_416; // @[RegisterRouter.scala:87:24]
wire _out_T_4392 = ~out_wimask_416; // @[RegisterRouter.scala:87:24]
wire _out_T_4393 = ~out_romask_416; // @[RegisterRouter.scala:87:24]
wire _out_T_4394 = ~out_womask_416; // @[RegisterRouter.scala:87:24]
wire out_rimask_417 = |_out_rimask_T_417; // @[RegisterRouter.scala:87:24]
wire out_wimask_417 = &_out_wimask_T_417; // @[RegisterRouter.scala:87:24]
wire out_romask_417 = |_out_romask_T_417; // @[RegisterRouter.scala:87:24]
wire out_womask_417 = &_out_womask_T_417; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_417 = out_rivalid_1_271 & out_rimask_417; // @[RegisterRouter.scala:87:24]
wire _out_T_4398 = out_f_rivalid_417; // @[RegisterRouter.scala:87:24]
wire out_f_roready_417 = out_roready_1_271 & out_romask_417; // @[RegisterRouter.scala:87:24]
wire _out_T_4399 = out_f_roready_417; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_417 = out_wivalid_1_271 & out_wimask_417; // @[RegisterRouter.scala:87:24]
wire out_f_woready_417 = out_woready_1_271 & out_womask_417; // @[RegisterRouter.scala:87:24]
wire _out_T_4400 = ~out_rimask_417; // @[RegisterRouter.scala:87:24]
wire _out_T_4401 = ~out_wimask_417; // @[RegisterRouter.scala:87:24]
wire _out_T_4402 = ~out_romask_417; // @[RegisterRouter.scala:87:24]
wire _out_T_4403 = ~out_womask_417; // @[RegisterRouter.scala:87:24]
wire out_rimask_418 = |_out_rimask_T_418; // @[RegisterRouter.scala:87:24]
wire out_wimask_418 = &_out_wimask_T_418; // @[RegisterRouter.scala:87:24]
wire out_romask_418 = |_out_romask_T_418; // @[RegisterRouter.scala:87:24]
wire out_womask_418 = &_out_womask_T_418; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_418 = out_rivalid_1_272 & out_rimask_418; // @[RegisterRouter.scala:87:24]
wire _out_T_4407 = out_f_rivalid_418; // @[RegisterRouter.scala:87:24]
wire out_f_roready_418 = out_roready_1_272 & out_romask_418; // @[RegisterRouter.scala:87:24]
wire _out_T_4408 = out_f_roready_418; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_418 = out_wivalid_1_272 & out_wimask_418; // @[RegisterRouter.scala:87:24]
wire out_f_woready_418 = out_woready_1_272 & out_womask_418; // @[RegisterRouter.scala:87:24]
wire _out_T_4409 = ~out_rimask_418; // @[RegisterRouter.scala:87:24]
wire _out_T_4410 = ~out_wimask_418; // @[RegisterRouter.scala:87:24]
wire _out_T_4411 = ~out_romask_418; // @[RegisterRouter.scala:87:24]
wire _out_T_4412 = ~out_womask_418; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4414 = _out_T_4413; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_350 = _out_T_4414; // @[RegisterRouter.scala:87:24]
wire out_rimask_419 = |_out_rimask_T_419; // @[RegisterRouter.scala:87:24]
wire out_wimask_419 = &_out_wimask_T_419; // @[RegisterRouter.scala:87:24]
wire out_romask_419 = |_out_romask_T_419; // @[RegisterRouter.scala:87:24]
wire out_womask_419 = &_out_womask_T_419; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_419 = out_rivalid_1_273 & out_rimask_419; // @[RegisterRouter.scala:87:24]
wire _out_T_4416 = out_f_rivalid_419; // @[RegisterRouter.scala:87:24]
wire out_f_roready_419 = out_roready_1_273 & out_romask_419; // @[RegisterRouter.scala:87:24]
wire _out_T_4417 = out_f_roready_419; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_419 = out_wivalid_1_273 & out_wimask_419; // @[RegisterRouter.scala:87:24]
wire out_f_woready_419 = out_woready_1_273 & out_womask_419; // @[RegisterRouter.scala:87:24]
wire _out_T_4418 = ~out_rimask_419; // @[RegisterRouter.scala:87:24]
wire _out_T_4419 = ~out_wimask_419; // @[RegisterRouter.scala:87:24]
wire _out_T_4420 = ~out_romask_419; // @[RegisterRouter.scala:87:24]
wire _out_T_4421 = ~out_womask_419; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_350 = {hi_626, flags_0_go, _out_prepend_T_350}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_4422 = out_prepend_350; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_4423 = _out_T_4422; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_351 = _out_T_4423; // @[RegisterRouter.scala:87:24]
wire out_rimask_420 = |_out_rimask_T_420; // @[RegisterRouter.scala:87:24]
wire out_wimask_420 = &_out_wimask_T_420; // @[RegisterRouter.scala:87:24]
wire out_romask_420 = |_out_romask_T_420; // @[RegisterRouter.scala:87:24]
wire out_womask_420 = &_out_womask_T_420; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_420 = out_rivalid_1_274 & out_rimask_420; // @[RegisterRouter.scala:87:24]
wire _out_T_4425 = out_f_rivalid_420; // @[RegisterRouter.scala:87:24]
wire out_f_roready_420 = out_roready_1_274 & out_romask_420; // @[RegisterRouter.scala:87:24]
wire _out_T_4426 = out_f_roready_420; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_420 = out_wivalid_1_274 & out_wimask_420; // @[RegisterRouter.scala:87:24]
wire out_f_woready_420 = out_woready_1_274 & out_womask_420; // @[RegisterRouter.scala:87:24]
wire _out_T_4427 = ~out_rimask_420; // @[RegisterRouter.scala:87:24]
wire _out_T_4428 = ~out_wimask_420; // @[RegisterRouter.scala:87:24]
wire _out_T_4429 = ~out_romask_420; // @[RegisterRouter.scala:87:24]
wire _out_T_4430 = ~out_womask_420; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_351 = {hi_627, flags_0_go, _out_prepend_T_351}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_4431 = out_prepend_351; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_4432 = _out_T_4431; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_352 = _out_T_4432; // @[RegisterRouter.scala:87:24]
wire out_rimask_421 = |_out_rimask_T_421; // @[RegisterRouter.scala:87:24]
wire out_wimask_421 = &_out_wimask_T_421; // @[RegisterRouter.scala:87:24]
wire out_romask_421 = |_out_romask_T_421; // @[RegisterRouter.scala:87:24]
wire out_womask_421 = &_out_womask_T_421; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_421 = out_rivalid_1_275 & out_rimask_421; // @[RegisterRouter.scala:87:24]
wire _out_T_4434 = out_f_rivalid_421; // @[RegisterRouter.scala:87:24]
wire out_f_roready_421 = out_roready_1_275 & out_romask_421; // @[RegisterRouter.scala:87:24]
wire _out_T_4435 = out_f_roready_421; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_421 = out_wivalid_1_275 & out_wimask_421; // @[RegisterRouter.scala:87:24]
wire out_f_woready_421 = out_woready_1_275 & out_womask_421; // @[RegisterRouter.scala:87:24]
wire _out_T_4436 = ~out_rimask_421; // @[RegisterRouter.scala:87:24]
wire _out_T_4437 = ~out_wimask_421; // @[RegisterRouter.scala:87:24]
wire _out_T_4438 = ~out_romask_421; // @[RegisterRouter.scala:87:24]
wire _out_T_4439 = ~out_womask_421; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_352 = {hi_628, flags_0_go, _out_prepend_T_352}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_4440 = out_prepend_352; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_4441 = _out_T_4440; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_353 = _out_T_4441; // @[RegisterRouter.scala:87:24]
wire out_rimask_422 = |_out_rimask_T_422; // @[RegisterRouter.scala:87:24]
wire out_wimask_422 = &_out_wimask_T_422; // @[RegisterRouter.scala:87:24]
wire out_romask_422 = |_out_romask_T_422; // @[RegisterRouter.scala:87:24]
wire out_womask_422 = &_out_womask_T_422; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_422 = out_rivalid_1_276 & out_rimask_422; // @[RegisterRouter.scala:87:24]
wire _out_T_4443 = out_f_rivalid_422; // @[RegisterRouter.scala:87:24]
wire out_f_roready_422 = out_roready_1_276 & out_romask_422; // @[RegisterRouter.scala:87:24]
wire _out_T_4444 = out_f_roready_422; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_422 = out_wivalid_1_276 & out_wimask_422; // @[RegisterRouter.scala:87:24]
wire out_f_woready_422 = out_woready_1_276 & out_womask_422; // @[RegisterRouter.scala:87:24]
wire _out_T_4445 = ~out_rimask_422; // @[RegisterRouter.scala:87:24]
wire _out_T_4446 = ~out_wimask_422; // @[RegisterRouter.scala:87:24]
wire _out_T_4447 = ~out_romask_422; // @[RegisterRouter.scala:87:24]
wire _out_T_4448 = ~out_womask_422; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_353 = {hi_629, flags_0_go, _out_prepend_T_353}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_4449 = out_prepend_353; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_4450 = _out_T_4449; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_354 = _out_T_4450; // @[RegisterRouter.scala:87:24]
wire out_rimask_423 = |_out_rimask_T_423; // @[RegisterRouter.scala:87:24]
wire out_wimask_423 = &_out_wimask_T_423; // @[RegisterRouter.scala:87:24]
wire out_romask_423 = |_out_romask_T_423; // @[RegisterRouter.scala:87:24]
wire out_womask_423 = &_out_womask_T_423; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_423 = out_rivalid_1_277 & out_rimask_423; // @[RegisterRouter.scala:87:24]
wire _out_T_4452 = out_f_rivalid_423; // @[RegisterRouter.scala:87:24]
wire out_f_roready_423 = out_roready_1_277 & out_romask_423; // @[RegisterRouter.scala:87:24]
wire _out_T_4453 = out_f_roready_423; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_423 = out_wivalid_1_277 & out_wimask_423; // @[RegisterRouter.scala:87:24]
wire out_f_woready_423 = out_woready_1_277 & out_womask_423; // @[RegisterRouter.scala:87:24]
wire _out_T_4454 = ~out_rimask_423; // @[RegisterRouter.scala:87:24]
wire _out_T_4455 = ~out_wimask_423; // @[RegisterRouter.scala:87:24]
wire _out_T_4456 = ~out_romask_423; // @[RegisterRouter.scala:87:24]
wire _out_T_4457 = ~out_womask_423; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_354 = {hi_630, flags_0_go, _out_prepend_T_354}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_4458 = out_prepend_354; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_4459 = _out_T_4458; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_355 = _out_T_4459; // @[RegisterRouter.scala:87:24]
wire out_rimask_424 = |_out_rimask_T_424; // @[RegisterRouter.scala:87:24]
wire out_wimask_424 = &_out_wimask_T_424; // @[RegisterRouter.scala:87:24]
wire out_romask_424 = |_out_romask_T_424; // @[RegisterRouter.scala:87:24]
wire out_womask_424 = &_out_womask_T_424; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_424 = out_rivalid_1_278 & out_rimask_424; // @[RegisterRouter.scala:87:24]
wire _out_T_4461 = out_f_rivalid_424; // @[RegisterRouter.scala:87:24]
wire out_f_roready_424 = out_roready_1_278 & out_romask_424; // @[RegisterRouter.scala:87:24]
wire _out_T_4462 = out_f_roready_424; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_424 = out_wivalid_1_278 & out_wimask_424; // @[RegisterRouter.scala:87:24]
wire out_f_woready_424 = out_woready_1_278 & out_womask_424; // @[RegisterRouter.scala:87:24]
wire _out_T_4463 = ~out_rimask_424; // @[RegisterRouter.scala:87:24]
wire _out_T_4464 = ~out_wimask_424; // @[RegisterRouter.scala:87:24]
wire _out_T_4465 = ~out_romask_424; // @[RegisterRouter.scala:87:24]
wire _out_T_4466 = ~out_womask_424; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_355 = {hi_631, flags_0_go, _out_prepend_T_355}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_4467 = out_prepend_355; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_4468 = _out_T_4467; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_356 = _out_T_4468; // @[RegisterRouter.scala:87:24]
wire out_rimask_425 = |_out_rimask_T_425; // @[RegisterRouter.scala:87:24]
wire out_wimask_425 = &_out_wimask_T_425; // @[RegisterRouter.scala:87:24]
wire out_romask_425 = |_out_romask_T_425; // @[RegisterRouter.scala:87:24]
wire out_womask_425 = &_out_womask_T_425; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_425 = out_rivalid_1_279 & out_rimask_425; // @[RegisterRouter.scala:87:24]
wire _out_T_4470 = out_f_rivalid_425; // @[RegisterRouter.scala:87:24]
wire out_f_roready_425 = out_roready_1_279 & out_romask_425; // @[RegisterRouter.scala:87:24]
wire _out_T_4471 = out_f_roready_425; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_425 = out_wivalid_1_279 & out_wimask_425; // @[RegisterRouter.scala:87:24]
wire out_f_woready_425 = out_woready_1_279 & out_womask_425; // @[RegisterRouter.scala:87:24]
wire _out_T_4472 = ~out_rimask_425; // @[RegisterRouter.scala:87:24]
wire _out_T_4473 = ~out_wimask_425; // @[RegisterRouter.scala:87:24]
wire _out_T_4474 = ~out_romask_425; // @[RegisterRouter.scala:87:24]
wire _out_T_4475 = ~out_womask_425; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_356 = {hi_632, flags_0_go, _out_prepend_T_356}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_4476 = out_prepend_356; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_4477 = _out_T_4476; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_206 = _out_T_4477; // @[MuxLiteral.scala:49:48]
wire out_rimask_426 = |_out_rimask_T_426; // @[RegisterRouter.scala:87:24]
wire out_wimask_426 = &_out_wimask_T_426; // @[RegisterRouter.scala:87:24]
wire out_romask_426 = |_out_romask_T_426; // @[RegisterRouter.scala:87:24]
wire out_womask_426 = &_out_womask_T_426; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_426 = out_rivalid_1_280 & out_rimask_426; // @[RegisterRouter.scala:87:24]
wire _out_T_4479 = out_f_rivalid_426; // @[RegisterRouter.scala:87:24]
wire out_f_roready_426 = out_roready_1_280 & out_romask_426; // @[RegisterRouter.scala:87:24]
wire _out_T_4480 = out_f_roready_426; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_426 = out_wivalid_1_280 & out_wimask_426; // @[RegisterRouter.scala:87:24]
wire out_f_woready_426 = out_woready_1_280 & out_womask_426; // @[RegisterRouter.scala:87:24]
wire _out_T_4481 = ~out_rimask_426; // @[RegisterRouter.scala:87:24]
wire _out_T_4482 = ~out_wimask_426; // @[RegisterRouter.scala:87:24]
wire _out_T_4483 = ~out_romask_426; // @[RegisterRouter.scala:87:24]
wire _out_T_4484 = ~out_womask_426; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4486 = _out_T_4485; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_357 = _out_T_4486; // @[RegisterRouter.scala:87:24]
wire out_rimask_427 = |_out_rimask_T_427; // @[RegisterRouter.scala:87:24]
wire out_wimask_427 = &_out_wimask_T_427; // @[RegisterRouter.scala:87:24]
wire out_romask_427 = |_out_romask_T_427; // @[RegisterRouter.scala:87:24]
wire out_womask_427 = &_out_womask_T_427; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_427 = out_rivalid_1_281 & out_rimask_427; // @[RegisterRouter.scala:87:24]
wire _out_T_4488 = out_f_rivalid_427; // @[RegisterRouter.scala:87:24]
wire out_f_roready_427 = out_roready_1_281 & out_romask_427; // @[RegisterRouter.scala:87:24]
wire _out_T_4489 = out_f_roready_427; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_427 = out_wivalid_1_281 & out_wimask_427; // @[RegisterRouter.scala:87:24]
wire out_f_woready_427 = out_woready_1_281 & out_womask_427; // @[RegisterRouter.scala:87:24]
wire _out_T_4490 = ~out_rimask_427; // @[RegisterRouter.scala:87:24]
wire _out_T_4491 = ~out_wimask_427; // @[RegisterRouter.scala:87:24]
wire _out_T_4492 = ~out_romask_427; // @[RegisterRouter.scala:87:24]
wire _out_T_4493 = ~out_womask_427; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_357 = {hi_842, flags_0_go, _out_prepend_T_357}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_4494 = out_prepend_357; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_4495 = _out_T_4494; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_358 = _out_T_4495; // @[RegisterRouter.scala:87:24]
wire out_rimask_428 = |_out_rimask_T_428; // @[RegisterRouter.scala:87:24]
wire out_wimask_428 = &_out_wimask_T_428; // @[RegisterRouter.scala:87:24]
wire out_romask_428 = |_out_romask_T_428; // @[RegisterRouter.scala:87:24]
wire out_womask_428 = &_out_womask_T_428; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_428 = out_rivalid_1_282 & out_rimask_428; // @[RegisterRouter.scala:87:24]
wire _out_T_4497 = out_f_rivalid_428; // @[RegisterRouter.scala:87:24]
wire out_f_roready_428 = out_roready_1_282 & out_romask_428; // @[RegisterRouter.scala:87:24]
wire _out_T_4498 = out_f_roready_428; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_428 = out_wivalid_1_282 & out_wimask_428; // @[RegisterRouter.scala:87:24]
wire out_f_woready_428 = out_woready_1_282 & out_womask_428; // @[RegisterRouter.scala:87:24]
wire _out_T_4499 = ~out_rimask_428; // @[RegisterRouter.scala:87:24]
wire _out_T_4500 = ~out_wimask_428; // @[RegisterRouter.scala:87:24]
wire _out_T_4501 = ~out_romask_428; // @[RegisterRouter.scala:87:24]
wire _out_T_4502 = ~out_womask_428; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_358 = {hi_843, flags_0_go, _out_prepend_T_358}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_4503 = out_prepend_358; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_4504 = _out_T_4503; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_359 = _out_T_4504; // @[RegisterRouter.scala:87:24]
wire out_rimask_429 = |_out_rimask_T_429; // @[RegisterRouter.scala:87:24]
wire out_wimask_429 = &_out_wimask_T_429; // @[RegisterRouter.scala:87:24]
wire out_romask_429 = |_out_romask_T_429; // @[RegisterRouter.scala:87:24]
wire out_womask_429 = &_out_womask_T_429; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_429 = out_rivalid_1_283 & out_rimask_429; // @[RegisterRouter.scala:87:24]
wire _out_T_4506 = out_f_rivalid_429; // @[RegisterRouter.scala:87:24]
wire out_f_roready_429 = out_roready_1_283 & out_romask_429; // @[RegisterRouter.scala:87:24]
wire _out_T_4507 = out_f_roready_429; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_429 = out_wivalid_1_283 & out_wimask_429; // @[RegisterRouter.scala:87:24]
wire out_f_woready_429 = out_woready_1_283 & out_womask_429; // @[RegisterRouter.scala:87:24]
wire _out_T_4508 = ~out_rimask_429; // @[RegisterRouter.scala:87:24]
wire _out_T_4509 = ~out_wimask_429; // @[RegisterRouter.scala:87:24]
wire _out_T_4510 = ~out_romask_429; // @[RegisterRouter.scala:87:24]
wire _out_T_4511 = ~out_womask_429; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_359 = {hi_844, flags_0_go, _out_prepend_T_359}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_4512 = out_prepend_359; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_4513 = _out_T_4512; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_360 = _out_T_4513; // @[RegisterRouter.scala:87:24]
wire out_rimask_430 = |_out_rimask_T_430; // @[RegisterRouter.scala:87:24]
wire out_wimask_430 = &_out_wimask_T_430; // @[RegisterRouter.scala:87:24]
wire out_romask_430 = |_out_romask_T_430; // @[RegisterRouter.scala:87:24]
wire out_womask_430 = &_out_womask_T_430; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_430 = out_rivalid_1_284 & out_rimask_430; // @[RegisterRouter.scala:87:24]
wire _out_T_4515 = out_f_rivalid_430; // @[RegisterRouter.scala:87:24]
wire out_f_roready_430 = out_roready_1_284 & out_romask_430; // @[RegisterRouter.scala:87:24]
wire _out_T_4516 = out_f_roready_430; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_430 = out_wivalid_1_284 & out_wimask_430; // @[RegisterRouter.scala:87:24]
wire out_f_woready_430 = out_woready_1_284 & out_womask_430; // @[RegisterRouter.scala:87:24]
wire _out_T_4517 = ~out_rimask_430; // @[RegisterRouter.scala:87:24]
wire _out_T_4518 = ~out_wimask_430; // @[RegisterRouter.scala:87:24]
wire _out_T_4519 = ~out_romask_430; // @[RegisterRouter.scala:87:24]
wire _out_T_4520 = ~out_womask_430; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_360 = {hi_845, flags_0_go, _out_prepend_T_360}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_4521 = out_prepend_360; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_4522 = _out_T_4521; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_361 = _out_T_4522; // @[RegisterRouter.scala:87:24]
wire out_rimask_431 = |_out_rimask_T_431; // @[RegisterRouter.scala:87:24]
wire out_wimask_431 = &_out_wimask_T_431; // @[RegisterRouter.scala:87:24]
wire out_romask_431 = |_out_romask_T_431; // @[RegisterRouter.scala:87:24]
wire out_womask_431 = &_out_womask_T_431; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_431 = out_rivalid_1_285 & out_rimask_431; // @[RegisterRouter.scala:87:24]
wire _out_T_4524 = out_f_rivalid_431; // @[RegisterRouter.scala:87:24]
wire out_f_roready_431 = out_roready_1_285 & out_romask_431; // @[RegisterRouter.scala:87:24]
wire _out_T_4525 = out_f_roready_431; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_431 = out_wivalid_1_285 & out_wimask_431; // @[RegisterRouter.scala:87:24]
wire out_f_woready_431 = out_woready_1_285 & out_womask_431; // @[RegisterRouter.scala:87:24]
wire _out_T_4526 = ~out_rimask_431; // @[RegisterRouter.scala:87:24]
wire _out_T_4527 = ~out_wimask_431; // @[RegisterRouter.scala:87:24]
wire _out_T_4528 = ~out_romask_431; // @[RegisterRouter.scala:87:24]
wire _out_T_4529 = ~out_womask_431; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_361 = {hi_846, flags_0_go, _out_prepend_T_361}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_4530 = out_prepend_361; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_4531 = _out_T_4530; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_362 = _out_T_4531; // @[RegisterRouter.scala:87:24]
wire out_rimask_432 = |_out_rimask_T_432; // @[RegisterRouter.scala:87:24]
wire out_wimask_432 = &_out_wimask_T_432; // @[RegisterRouter.scala:87:24]
wire out_romask_432 = |_out_romask_T_432; // @[RegisterRouter.scala:87:24]
wire out_womask_432 = &_out_womask_T_432; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_432 = out_rivalid_1_286 & out_rimask_432; // @[RegisterRouter.scala:87:24]
wire _out_T_4533 = out_f_rivalid_432; // @[RegisterRouter.scala:87:24]
wire out_f_roready_432 = out_roready_1_286 & out_romask_432; // @[RegisterRouter.scala:87:24]
wire _out_T_4534 = out_f_roready_432; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_432 = out_wivalid_1_286 & out_wimask_432; // @[RegisterRouter.scala:87:24]
wire out_f_woready_432 = out_woready_1_286 & out_womask_432; // @[RegisterRouter.scala:87:24]
wire _out_T_4535 = ~out_rimask_432; // @[RegisterRouter.scala:87:24]
wire _out_T_4536 = ~out_wimask_432; // @[RegisterRouter.scala:87:24]
wire _out_T_4537 = ~out_romask_432; // @[RegisterRouter.scala:87:24]
wire _out_T_4538 = ~out_womask_432; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_362 = {hi_847, flags_0_go, _out_prepend_T_362}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_4539 = out_prepend_362; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_4540 = _out_T_4539; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_363 = _out_T_4540; // @[RegisterRouter.scala:87:24]
wire out_rimask_433 = |_out_rimask_T_433; // @[RegisterRouter.scala:87:24]
wire out_wimask_433 = &_out_wimask_T_433; // @[RegisterRouter.scala:87:24]
wire out_romask_433 = |_out_romask_T_433; // @[RegisterRouter.scala:87:24]
wire out_womask_433 = &_out_womask_T_433; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_433 = out_rivalid_1_287 & out_rimask_433; // @[RegisterRouter.scala:87:24]
wire _out_T_4542 = out_f_rivalid_433; // @[RegisterRouter.scala:87:24]
wire out_f_roready_433 = out_roready_1_287 & out_romask_433; // @[RegisterRouter.scala:87:24]
wire _out_T_4543 = out_f_roready_433; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_433 = out_wivalid_1_287 & out_wimask_433; // @[RegisterRouter.scala:87:24]
wire out_f_woready_433 = out_woready_1_287 & out_womask_433; // @[RegisterRouter.scala:87:24]
wire _out_T_4544 = ~out_rimask_433; // @[RegisterRouter.scala:87:24]
wire _out_T_4545 = ~out_wimask_433; // @[RegisterRouter.scala:87:24]
wire _out_T_4546 = ~out_romask_433; // @[RegisterRouter.scala:87:24]
wire _out_T_4547 = ~out_womask_433; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_363 = {hi_848, flags_0_go, _out_prepend_T_363}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_4548 = out_prepend_363; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_4549 = _out_T_4548; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_233 = _out_T_4549; // @[MuxLiteral.scala:49:48]
wire out_rimask_434 = |_out_rimask_T_434; // @[RegisterRouter.scala:87:24]
wire out_wimask_434 = &_out_wimask_T_434; // @[RegisterRouter.scala:87:24]
wire out_romask_434 = |_out_romask_T_434; // @[RegisterRouter.scala:87:24]
wire out_womask_434 = &_out_womask_T_434; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_434 = out_rivalid_1_288 & out_rimask_434; // @[RegisterRouter.scala:87:24]
wire _out_T_4551 = out_f_rivalid_434; // @[RegisterRouter.scala:87:24]
wire out_f_roready_434 = out_roready_1_288 & out_romask_434; // @[RegisterRouter.scala:87:24]
wire _out_T_4552 = out_f_roready_434; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_434 = out_wivalid_1_288 & out_wimask_434; // @[RegisterRouter.scala:87:24]
wire out_f_woready_434 = out_woready_1_288 & out_womask_434; // @[RegisterRouter.scala:87:24]
wire _out_T_4553 = ~out_rimask_434; // @[RegisterRouter.scala:87:24]
wire _out_T_4554 = ~out_wimask_434; // @[RegisterRouter.scala:87:24]
wire _out_T_4555 = ~out_romask_434; // @[RegisterRouter.scala:87:24]
wire _out_T_4556 = ~out_womask_434; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4558 = _out_T_4557; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_364 = _out_T_4558; // @[RegisterRouter.scala:87:24]
wire out_rimask_435 = |_out_rimask_T_435; // @[RegisterRouter.scala:87:24]
wire out_wimask_435 = &_out_wimask_T_435; // @[RegisterRouter.scala:87:24]
wire out_romask_435 = |_out_romask_T_435; // @[RegisterRouter.scala:87:24]
wire out_womask_435 = &_out_womask_T_435; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_435 = out_rivalid_1_289 & out_rimask_435; // @[RegisterRouter.scala:87:24]
wire _out_T_4560 = out_f_rivalid_435; // @[RegisterRouter.scala:87:24]
wire out_f_roready_435 = out_roready_1_289 & out_romask_435; // @[RegisterRouter.scala:87:24]
wire _out_T_4561 = out_f_roready_435; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_435 = out_wivalid_1_289 & out_wimask_435; // @[RegisterRouter.scala:87:24]
wire out_f_woready_435 = out_woready_1_289 & out_womask_435; // @[RegisterRouter.scala:87:24]
wire _out_T_4562 = ~out_rimask_435; // @[RegisterRouter.scala:87:24]
wire _out_T_4563 = ~out_wimask_435; // @[RegisterRouter.scala:87:24]
wire _out_T_4564 = ~out_romask_435; // @[RegisterRouter.scala:87:24]
wire _out_T_4565 = ~out_womask_435; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_364 = {hi_962, flags_0_go, _out_prepend_T_364}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_4566 = out_prepend_364; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_4567 = _out_T_4566; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_365 = _out_T_4567; // @[RegisterRouter.scala:87:24]
wire out_rimask_436 = |_out_rimask_T_436; // @[RegisterRouter.scala:87:24]
wire out_wimask_436 = &_out_wimask_T_436; // @[RegisterRouter.scala:87:24]
wire out_romask_436 = |_out_romask_T_436; // @[RegisterRouter.scala:87:24]
wire out_womask_436 = &_out_womask_T_436; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_436 = out_rivalid_1_290 & out_rimask_436; // @[RegisterRouter.scala:87:24]
wire _out_T_4569 = out_f_rivalid_436; // @[RegisterRouter.scala:87:24]
wire out_f_roready_436 = out_roready_1_290 & out_romask_436; // @[RegisterRouter.scala:87:24]
wire _out_T_4570 = out_f_roready_436; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_436 = out_wivalid_1_290 & out_wimask_436; // @[RegisterRouter.scala:87:24]
wire out_f_woready_436 = out_woready_1_290 & out_womask_436; // @[RegisterRouter.scala:87:24]
wire _out_T_4571 = ~out_rimask_436; // @[RegisterRouter.scala:87:24]
wire _out_T_4572 = ~out_wimask_436; // @[RegisterRouter.scala:87:24]
wire _out_T_4573 = ~out_romask_436; // @[RegisterRouter.scala:87:24]
wire _out_T_4574 = ~out_womask_436; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_365 = {hi_963, flags_0_go, _out_prepend_T_365}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_4575 = out_prepend_365; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_4576 = _out_T_4575; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_366 = _out_T_4576; // @[RegisterRouter.scala:87:24]
wire out_rimask_437 = |_out_rimask_T_437; // @[RegisterRouter.scala:87:24]
wire out_wimask_437 = &_out_wimask_T_437; // @[RegisterRouter.scala:87:24]
wire out_romask_437 = |_out_romask_T_437; // @[RegisterRouter.scala:87:24]
wire out_womask_437 = &_out_womask_T_437; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_437 = out_rivalid_1_291 & out_rimask_437; // @[RegisterRouter.scala:87:24]
wire _out_T_4578 = out_f_rivalid_437; // @[RegisterRouter.scala:87:24]
wire out_f_roready_437 = out_roready_1_291 & out_romask_437; // @[RegisterRouter.scala:87:24]
wire _out_T_4579 = out_f_roready_437; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_437 = out_wivalid_1_291 & out_wimask_437; // @[RegisterRouter.scala:87:24]
wire out_f_woready_437 = out_woready_1_291 & out_womask_437; // @[RegisterRouter.scala:87:24]
wire _out_T_4580 = ~out_rimask_437; // @[RegisterRouter.scala:87:24]
wire _out_T_4581 = ~out_wimask_437; // @[RegisterRouter.scala:87:24]
wire _out_T_4582 = ~out_romask_437; // @[RegisterRouter.scala:87:24]
wire _out_T_4583 = ~out_womask_437; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_366 = {hi_964, flags_0_go, _out_prepend_T_366}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_4584 = out_prepend_366; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_4585 = _out_T_4584; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_367 = _out_T_4585; // @[RegisterRouter.scala:87:24]
wire out_rimask_438 = |_out_rimask_T_438; // @[RegisterRouter.scala:87:24]
wire out_wimask_438 = &_out_wimask_T_438; // @[RegisterRouter.scala:87:24]
wire out_romask_438 = |_out_romask_T_438; // @[RegisterRouter.scala:87:24]
wire out_womask_438 = &_out_womask_T_438; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_438 = out_rivalid_1_292 & out_rimask_438; // @[RegisterRouter.scala:87:24]
wire _out_T_4587 = out_f_rivalid_438; // @[RegisterRouter.scala:87:24]
wire out_f_roready_438 = out_roready_1_292 & out_romask_438; // @[RegisterRouter.scala:87:24]
wire _out_T_4588 = out_f_roready_438; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_438 = out_wivalid_1_292 & out_wimask_438; // @[RegisterRouter.scala:87:24]
wire out_f_woready_438 = out_woready_1_292 & out_womask_438; // @[RegisterRouter.scala:87:24]
wire _out_T_4589 = ~out_rimask_438; // @[RegisterRouter.scala:87:24]
wire _out_T_4590 = ~out_wimask_438; // @[RegisterRouter.scala:87:24]
wire _out_T_4591 = ~out_romask_438; // @[RegisterRouter.scala:87:24]
wire _out_T_4592 = ~out_womask_438; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_367 = {hi_965, flags_0_go, _out_prepend_T_367}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_4593 = out_prepend_367; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_4594 = _out_T_4593; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_368 = _out_T_4594; // @[RegisterRouter.scala:87:24]
wire out_rimask_439 = |_out_rimask_T_439; // @[RegisterRouter.scala:87:24]
wire out_wimask_439 = &_out_wimask_T_439; // @[RegisterRouter.scala:87:24]
wire out_romask_439 = |_out_romask_T_439; // @[RegisterRouter.scala:87:24]
wire out_womask_439 = &_out_womask_T_439; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_439 = out_rivalid_1_293 & out_rimask_439; // @[RegisterRouter.scala:87:24]
wire _out_T_4596 = out_f_rivalid_439; // @[RegisterRouter.scala:87:24]
wire out_f_roready_439 = out_roready_1_293 & out_romask_439; // @[RegisterRouter.scala:87:24]
wire _out_T_4597 = out_f_roready_439; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_439 = out_wivalid_1_293 & out_wimask_439; // @[RegisterRouter.scala:87:24]
wire out_f_woready_439 = out_woready_1_293 & out_womask_439; // @[RegisterRouter.scala:87:24]
wire _out_T_4598 = ~out_rimask_439; // @[RegisterRouter.scala:87:24]
wire _out_T_4599 = ~out_wimask_439; // @[RegisterRouter.scala:87:24]
wire _out_T_4600 = ~out_romask_439; // @[RegisterRouter.scala:87:24]
wire _out_T_4601 = ~out_womask_439; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_368 = {hi_966, flags_0_go, _out_prepend_T_368}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_4602 = out_prepend_368; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_4603 = _out_T_4602; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_369 = _out_T_4603; // @[RegisterRouter.scala:87:24]
wire out_rimask_440 = |_out_rimask_T_440; // @[RegisterRouter.scala:87:24]
wire out_wimask_440 = &_out_wimask_T_440; // @[RegisterRouter.scala:87:24]
wire out_romask_440 = |_out_romask_T_440; // @[RegisterRouter.scala:87:24]
wire out_womask_440 = &_out_womask_T_440; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_440 = out_rivalid_1_294 & out_rimask_440; // @[RegisterRouter.scala:87:24]
wire _out_T_4605 = out_f_rivalid_440; // @[RegisterRouter.scala:87:24]
wire out_f_roready_440 = out_roready_1_294 & out_romask_440; // @[RegisterRouter.scala:87:24]
wire _out_T_4606 = out_f_roready_440; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_440 = out_wivalid_1_294 & out_wimask_440; // @[RegisterRouter.scala:87:24]
wire out_f_woready_440 = out_woready_1_294 & out_womask_440; // @[RegisterRouter.scala:87:24]
wire _out_T_4607 = ~out_rimask_440; // @[RegisterRouter.scala:87:24]
wire _out_T_4608 = ~out_wimask_440; // @[RegisterRouter.scala:87:24]
wire _out_T_4609 = ~out_romask_440; // @[RegisterRouter.scala:87:24]
wire _out_T_4610 = ~out_womask_440; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_369 = {hi_967, flags_0_go, _out_prepend_T_369}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_4611 = out_prepend_369; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_4612 = _out_T_4611; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_370 = _out_T_4612; // @[RegisterRouter.scala:87:24]
wire out_rimask_441 = |_out_rimask_T_441; // @[RegisterRouter.scala:87:24]
wire out_wimask_441 = &_out_wimask_T_441; // @[RegisterRouter.scala:87:24]
wire out_romask_441 = |_out_romask_T_441; // @[RegisterRouter.scala:87:24]
wire out_womask_441 = &_out_womask_T_441; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_441 = out_rivalid_1_295 & out_rimask_441; // @[RegisterRouter.scala:87:24]
wire _out_T_4614 = out_f_rivalid_441; // @[RegisterRouter.scala:87:24]
wire out_f_roready_441 = out_roready_1_295 & out_romask_441; // @[RegisterRouter.scala:87:24]
wire _out_T_4615 = out_f_roready_441; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_441 = out_wivalid_1_295 & out_wimask_441; // @[RegisterRouter.scala:87:24]
wire out_f_woready_441 = out_woready_1_295 & out_womask_441; // @[RegisterRouter.scala:87:24]
wire _out_T_4616 = ~out_rimask_441; // @[RegisterRouter.scala:87:24]
wire _out_T_4617 = ~out_wimask_441; // @[RegisterRouter.scala:87:24]
wire _out_T_4618 = ~out_romask_441; // @[RegisterRouter.scala:87:24]
wire _out_T_4619 = ~out_womask_441; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_370 = {hi_968, flags_0_go, _out_prepend_T_370}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_4620 = out_prepend_370; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_4621 = _out_T_4620; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_248 = _out_T_4621; // @[MuxLiteral.scala:49:48]
wire out_rimask_442 = |_out_rimask_T_442; // @[RegisterRouter.scala:87:24]
wire out_wimask_442 = &_out_wimask_T_442; // @[RegisterRouter.scala:87:24]
wire out_romask_442 = |_out_romask_T_442; // @[RegisterRouter.scala:87:24]
wire out_womask_442 = &_out_womask_T_442; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_442 = out_rivalid_1_296 & out_rimask_442; // @[RegisterRouter.scala:87:24]
wire _out_T_4623 = out_f_rivalid_442; // @[RegisterRouter.scala:87:24]
wire out_f_roready_442 = out_roready_1_296 & out_romask_442; // @[RegisterRouter.scala:87:24]
wire _out_T_4624 = out_f_roready_442; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_442 = out_wivalid_1_296 & out_wimask_442; // @[RegisterRouter.scala:87:24]
wire out_f_woready_442 = out_woready_1_296 & out_womask_442; // @[RegisterRouter.scala:87:24]
wire _out_T_4625 = ~out_rimask_442; // @[RegisterRouter.scala:87:24]
wire _out_T_4626 = ~out_wimask_442; // @[RegisterRouter.scala:87:24]
wire _out_T_4627 = ~out_romask_442; // @[RegisterRouter.scala:87:24]
wire _out_T_4628 = ~out_womask_442; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4630 = _out_T_4629; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_371 = _out_T_4630; // @[RegisterRouter.scala:87:24]
wire out_rimask_443 = |_out_rimask_T_443; // @[RegisterRouter.scala:87:24]
wire out_wimask_443 = &_out_wimask_T_443; // @[RegisterRouter.scala:87:24]
wire out_romask_443 = |_out_romask_T_443; // @[RegisterRouter.scala:87:24]
wire out_womask_443 = &_out_womask_T_443; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_443 = out_rivalid_1_297 & out_rimask_443; // @[RegisterRouter.scala:87:24]
wire _out_T_4632 = out_f_rivalid_443; // @[RegisterRouter.scala:87:24]
wire out_f_roready_443 = out_roready_1_297 & out_romask_443; // @[RegisterRouter.scala:87:24]
wire _out_T_4633 = out_f_roready_443; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_443 = out_wivalid_1_297 & out_wimask_443; // @[RegisterRouter.scala:87:24]
wire out_f_woready_443 = out_woready_1_297 & out_womask_443; // @[RegisterRouter.scala:87:24]
wire _out_T_4634 = ~out_rimask_443; // @[RegisterRouter.scala:87:24]
wire _out_T_4635 = ~out_wimask_443; // @[RegisterRouter.scala:87:24]
wire _out_T_4636 = ~out_romask_443; // @[RegisterRouter.scala:87:24]
wire _out_T_4637 = ~out_womask_443; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_371 = {hi_586, flags_0_go, _out_prepend_T_371}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_4638 = out_prepend_371; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_4639 = _out_T_4638; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_372 = _out_T_4639; // @[RegisterRouter.scala:87:24]
wire out_rimask_444 = |_out_rimask_T_444; // @[RegisterRouter.scala:87:24]
wire out_wimask_444 = &_out_wimask_T_444; // @[RegisterRouter.scala:87:24]
wire out_romask_444 = |_out_romask_T_444; // @[RegisterRouter.scala:87:24]
wire out_womask_444 = &_out_womask_T_444; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_444 = out_rivalid_1_298 & out_rimask_444; // @[RegisterRouter.scala:87:24]
wire _out_T_4641 = out_f_rivalid_444; // @[RegisterRouter.scala:87:24]
wire out_f_roready_444 = out_roready_1_298 & out_romask_444; // @[RegisterRouter.scala:87:24]
wire _out_T_4642 = out_f_roready_444; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_444 = out_wivalid_1_298 & out_wimask_444; // @[RegisterRouter.scala:87:24]
wire out_f_woready_444 = out_woready_1_298 & out_womask_444; // @[RegisterRouter.scala:87:24]
wire _out_T_4643 = ~out_rimask_444; // @[RegisterRouter.scala:87:24]
wire _out_T_4644 = ~out_wimask_444; // @[RegisterRouter.scala:87:24]
wire _out_T_4645 = ~out_romask_444; // @[RegisterRouter.scala:87:24]
wire _out_T_4646 = ~out_womask_444; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_372 = {hi_587, flags_0_go, _out_prepend_T_372}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_4647 = out_prepend_372; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_4648 = _out_T_4647; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_373 = _out_T_4648; // @[RegisterRouter.scala:87:24]
wire out_rimask_445 = |_out_rimask_T_445; // @[RegisterRouter.scala:87:24]
wire out_wimask_445 = &_out_wimask_T_445; // @[RegisterRouter.scala:87:24]
wire out_romask_445 = |_out_romask_T_445; // @[RegisterRouter.scala:87:24]
wire out_womask_445 = &_out_womask_T_445; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_445 = out_rivalid_1_299 & out_rimask_445; // @[RegisterRouter.scala:87:24]
wire _out_T_4650 = out_f_rivalid_445; // @[RegisterRouter.scala:87:24]
wire out_f_roready_445 = out_roready_1_299 & out_romask_445; // @[RegisterRouter.scala:87:24]
wire _out_T_4651 = out_f_roready_445; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_445 = out_wivalid_1_299 & out_wimask_445; // @[RegisterRouter.scala:87:24]
wire out_f_woready_445 = out_woready_1_299 & out_womask_445; // @[RegisterRouter.scala:87:24]
wire _out_T_4652 = ~out_rimask_445; // @[RegisterRouter.scala:87:24]
wire _out_T_4653 = ~out_wimask_445; // @[RegisterRouter.scala:87:24]
wire _out_T_4654 = ~out_romask_445; // @[RegisterRouter.scala:87:24]
wire _out_T_4655 = ~out_womask_445; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_373 = {hi_588, flags_0_go, _out_prepend_T_373}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_4656 = out_prepend_373; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_4657 = _out_T_4656; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_374 = _out_T_4657; // @[RegisterRouter.scala:87:24]
wire out_rimask_446 = |_out_rimask_T_446; // @[RegisterRouter.scala:87:24]
wire out_wimask_446 = &_out_wimask_T_446; // @[RegisterRouter.scala:87:24]
wire out_romask_446 = |_out_romask_T_446; // @[RegisterRouter.scala:87:24]
wire out_womask_446 = &_out_womask_T_446; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_446 = out_rivalid_1_300 & out_rimask_446; // @[RegisterRouter.scala:87:24]
wire _out_T_4659 = out_f_rivalid_446; // @[RegisterRouter.scala:87:24]
wire out_f_roready_446 = out_roready_1_300 & out_romask_446; // @[RegisterRouter.scala:87:24]
wire _out_T_4660 = out_f_roready_446; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_446 = out_wivalid_1_300 & out_wimask_446; // @[RegisterRouter.scala:87:24]
wire out_f_woready_446 = out_woready_1_300 & out_womask_446; // @[RegisterRouter.scala:87:24]
wire _out_T_4661 = ~out_rimask_446; // @[RegisterRouter.scala:87:24]
wire _out_T_4662 = ~out_wimask_446; // @[RegisterRouter.scala:87:24]
wire _out_T_4663 = ~out_romask_446; // @[RegisterRouter.scala:87:24]
wire _out_T_4664 = ~out_womask_446; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_374 = {hi_589, flags_0_go, _out_prepend_T_374}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_4665 = out_prepend_374; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_4666 = _out_T_4665; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_375 = _out_T_4666; // @[RegisterRouter.scala:87:24]
wire out_rimask_447 = |_out_rimask_T_447; // @[RegisterRouter.scala:87:24]
wire out_wimask_447 = &_out_wimask_T_447; // @[RegisterRouter.scala:87:24]
wire out_romask_447 = |_out_romask_T_447; // @[RegisterRouter.scala:87:24]
wire out_womask_447 = &_out_womask_T_447; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_447 = out_rivalid_1_301 & out_rimask_447; // @[RegisterRouter.scala:87:24]
wire _out_T_4668 = out_f_rivalid_447; // @[RegisterRouter.scala:87:24]
wire out_f_roready_447 = out_roready_1_301 & out_romask_447; // @[RegisterRouter.scala:87:24]
wire _out_T_4669 = out_f_roready_447; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_447 = out_wivalid_1_301 & out_wimask_447; // @[RegisterRouter.scala:87:24]
wire out_f_woready_447 = out_woready_1_301 & out_womask_447; // @[RegisterRouter.scala:87:24]
wire _out_T_4670 = ~out_rimask_447; // @[RegisterRouter.scala:87:24]
wire _out_T_4671 = ~out_wimask_447; // @[RegisterRouter.scala:87:24]
wire _out_T_4672 = ~out_romask_447; // @[RegisterRouter.scala:87:24]
wire _out_T_4673 = ~out_womask_447; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_375 = {hi_590, flags_0_go, _out_prepend_T_375}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_4674 = out_prepend_375; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_4675 = _out_T_4674; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_376 = _out_T_4675; // @[RegisterRouter.scala:87:24]
wire out_rimask_448 = |_out_rimask_T_448; // @[RegisterRouter.scala:87:24]
wire out_wimask_448 = &_out_wimask_T_448; // @[RegisterRouter.scala:87:24]
wire out_romask_448 = |_out_romask_T_448; // @[RegisterRouter.scala:87:24]
wire out_womask_448 = &_out_womask_T_448; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_448 = out_rivalid_1_302 & out_rimask_448; // @[RegisterRouter.scala:87:24]
wire _out_T_4677 = out_f_rivalid_448; // @[RegisterRouter.scala:87:24]
wire out_f_roready_448 = out_roready_1_302 & out_romask_448; // @[RegisterRouter.scala:87:24]
wire _out_T_4678 = out_f_roready_448; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_448 = out_wivalid_1_302 & out_wimask_448; // @[RegisterRouter.scala:87:24]
wire out_f_woready_448 = out_woready_1_302 & out_womask_448; // @[RegisterRouter.scala:87:24]
wire _out_T_4679 = ~out_rimask_448; // @[RegisterRouter.scala:87:24]
wire _out_T_4680 = ~out_wimask_448; // @[RegisterRouter.scala:87:24]
wire _out_T_4681 = ~out_romask_448; // @[RegisterRouter.scala:87:24]
wire _out_T_4682 = ~out_womask_448; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_376 = {hi_591, flags_0_go, _out_prepend_T_376}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_4683 = out_prepend_376; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_4684 = _out_T_4683; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_377 = _out_T_4684; // @[RegisterRouter.scala:87:24]
wire out_rimask_449 = |_out_rimask_T_449; // @[RegisterRouter.scala:87:24]
wire out_wimask_449 = &_out_wimask_T_449; // @[RegisterRouter.scala:87:24]
wire out_romask_449 = |_out_romask_T_449; // @[RegisterRouter.scala:87:24]
wire out_womask_449 = &_out_womask_T_449; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_449 = out_rivalid_1_303 & out_rimask_449; // @[RegisterRouter.scala:87:24]
wire _out_T_4686 = out_f_rivalid_449; // @[RegisterRouter.scala:87:24]
wire out_f_roready_449 = out_roready_1_303 & out_romask_449; // @[RegisterRouter.scala:87:24]
wire _out_T_4687 = out_f_roready_449; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_449 = out_wivalid_1_303 & out_wimask_449; // @[RegisterRouter.scala:87:24]
wire out_f_woready_449 = out_woready_1_303 & out_womask_449; // @[RegisterRouter.scala:87:24]
wire _out_T_4688 = ~out_rimask_449; // @[RegisterRouter.scala:87:24]
wire _out_T_4689 = ~out_wimask_449; // @[RegisterRouter.scala:87:24]
wire _out_T_4690 = ~out_romask_449; // @[RegisterRouter.scala:87:24]
wire _out_T_4691 = ~out_womask_449; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_377 = {hi_592, flags_0_go, _out_prepend_T_377}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_4692 = out_prepend_377; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_4693 = _out_T_4692; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_201 = _out_T_4693; // @[MuxLiteral.scala:49:48]
wire out_rimask_450 = |_out_rimask_T_450; // @[RegisterRouter.scala:87:24]
wire out_wimask_450 = &_out_wimask_T_450; // @[RegisterRouter.scala:87:24]
wire out_romask_450 = |_out_romask_T_450; // @[RegisterRouter.scala:87:24]
wire out_womask_450 = &_out_womask_T_450; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_450 = out_rivalid_1_304 & out_rimask_450; // @[RegisterRouter.scala:87:24]
wire _out_T_4695 = out_f_rivalid_450; // @[RegisterRouter.scala:87:24]
wire out_f_roready_450 = out_roready_1_304 & out_romask_450; // @[RegisterRouter.scala:87:24]
wire _out_T_4696 = out_f_roready_450; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_450 = out_wivalid_1_304 & out_wimask_450; // @[RegisterRouter.scala:87:24]
wire out_f_woready_450 = out_woready_1_304 & out_womask_450; // @[RegisterRouter.scala:87:24]
wire _out_T_4697 = ~out_rimask_450; // @[RegisterRouter.scala:87:24]
wire _out_T_4698 = ~out_wimask_450; // @[RegisterRouter.scala:87:24]
wire _out_T_4699 = ~out_romask_450; // @[RegisterRouter.scala:87:24]
wire _out_T_4700 = ~out_womask_450; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4702 = _out_T_4701; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_378 = _out_T_4702; // @[RegisterRouter.scala:87:24]
wire out_rimask_451 = |_out_rimask_T_451; // @[RegisterRouter.scala:87:24]
wire out_wimask_451 = &_out_wimask_T_451; // @[RegisterRouter.scala:87:24]
wire out_romask_451 = |_out_romask_T_451; // @[RegisterRouter.scala:87:24]
wire out_womask_451 = &_out_womask_T_451; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_451 = out_rivalid_1_305 & out_rimask_451; // @[RegisterRouter.scala:87:24]
wire _out_T_4704 = out_f_rivalid_451; // @[RegisterRouter.scala:87:24]
wire out_f_roready_451 = out_roready_1_305 & out_romask_451; // @[RegisterRouter.scala:87:24]
wire _out_T_4705 = out_f_roready_451; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_451 = out_wivalid_1_305 & out_wimask_451; // @[RegisterRouter.scala:87:24]
wire out_f_woready_451 = out_woready_1_305 & out_womask_451; // @[RegisterRouter.scala:87:24]
wire _out_T_4706 = ~out_rimask_451; // @[RegisterRouter.scala:87:24]
wire _out_T_4707 = ~out_wimask_451; // @[RegisterRouter.scala:87:24]
wire _out_T_4708 = ~out_romask_451; // @[RegisterRouter.scala:87:24]
wire _out_T_4709 = ~out_womask_451; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_378 = {hi_738, flags_0_go, _out_prepend_T_378}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_4710 = out_prepend_378; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_4711 = _out_T_4710; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_379 = _out_T_4711; // @[RegisterRouter.scala:87:24]
wire out_rimask_452 = |_out_rimask_T_452; // @[RegisterRouter.scala:87:24]
wire out_wimask_452 = &_out_wimask_T_452; // @[RegisterRouter.scala:87:24]
wire out_romask_452 = |_out_romask_T_452; // @[RegisterRouter.scala:87:24]
wire out_womask_452 = &_out_womask_T_452; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_452 = out_rivalid_1_306 & out_rimask_452; // @[RegisterRouter.scala:87:24]
wire _out_T_4713 = out_f_rivalid_452; // @[RegisterRouter.scala:87:24]
wire out_f_roready_452 = out_roready_1_306 & out_romask_452; // @[RegisterRouter.scala:87:24]
wire _out_T_4714 = out_f_roready_452; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_452 = out_wivalid_1_306 & out_wimask_452; // @[RegisterRouter.scala:87:24]
wire out_f_woready_452 = out_woready_1_306 & out_womask_452; // @[RegisterRouter.scala:87:24]
wire _out_T_4715 = ~out_rimask_452; // @[RegisterRouter.scala:87:24]
wire _out_T_4716 = ~out_wimask_452; // @[RegisterRouter.scala:87:24]
wire _out_T_4717 = ~out_romask_452; // @[RegisterRouter.scala:87:24]
wire _out_T_4718 = ~out_womask_452; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_379 = {hi_739, flags_0_go, _out_prepend_T_379}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_4719 = out_prepend_379; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_4720 = _out_T_4719; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_380 = _out_T_4720; // @[RegisterRouter.scala:87:24]
wire out_rimask_453 = |_out_rimask_T_453; // @[RegisterRouter.scala:87:24]
wire out_wimask_453 = &_out_wimask_T_453; // @[RegisterRouter.scala:87:24]
wire out_romask_453 = |_out_romask_T_453; // @[RegisterRouter.scala:87:24]
wire out_womask_453 = &_out_womask_T_453; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_453 = out_rivalid_1_307 & out_rimask_453; // @[RegisterRouter.scala:87:24]
wire _out_T_4722 = out_f_rivalid_453; // @[RegisterRouter.scala:87:24]
wire out_f_roready_453 = out_roready_1_307 & out_romask_453; // @[RegisterRouter.scala:87:24]
wire _out_T_4723 = out_f_roready_453; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_453 = out_wivalid_1_307 & out_wimask_453; // @[RegisterRouter.scala:87:24]
wire out_f_woready_453 = out_woready_1_307 & out_womask_453; // @[RegisterRouter.scala:87:24]
wire _out_T_4724 = ~out_rimask_453; // @[RegisterRouter.scala:87:24]
wire _out_T_4725 = ~out_wimask_453; // @[RegisterRouter.scala:87:24]
wire _out_T_4726 = ~out_romask_453; // @[RegisterRouter.scala:87:24]
wire _out_T_4727 = ~out_womask_453; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_380 = {hi_740, flags_0_go, _out_prepend_T_380}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_4728 = out_prepend_380; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_4729 = _out_T_4728; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_381 = _out_T_4729; // @[RegisterRouter.scala:87:24]
wire out_rimask_454 = |_out_rimask_T_454; // @[RegisterRouter.scala:87:24]
wire out_wimask_454 = &_out_wimask_T_454; // @[RegisterRouter.scala:87:24]
wire out_romask_454 = |_out_romask_T_454; // @[RegisterRouter.scala:87:24]
wire out_womask_454 = &_out_womask_T_454; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_454 = out_rivalid_1_308 & out_rimask_454; // @[RegisterRouter.scala:87:24]
wire _out_T_4731 = out_f_rivalid_454; // @[RegisterRouter.scala:87:24]
wire out_f_roready_454 = out_roready_1_308 & out_romask_454; // @[RegisterRouter.scala:87:24]
wire _out_T_4732 = out_f_roready_454; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_454 = out_wivalid_1_308 & out_wimask_454; // @[RegisterRouter.scala:87:24]
wire out_f_woready_454 = out_woready_1_308 & out_womask_454; // @[RegisterRouter.scala:87:24]
wire _out_T_4733 = ~out_rimask_454; // @[RegisterRouter.scala:87:24]
wire _out_T_4734 = ~out_wimask_454; // @[RegisterRouter.scala:87:24]
wire _out_T_4735 = ~out_romask_454; // @[RegisterRouter.scala:87:24]
wire _out_T_4736 = ~out_womask_454; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_381 = {hi_741, flags_0_go, _out_prepend_T_381}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_4737 = out_prepend_381; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_4738 = _out_T_4737; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_382 = _out_T_4738; // @[RegisterRouter.scala:87:24]
wire out_rimask_455 = |_out_rimask_T_455; // @[RegisterRouter.scala:87:24]
wire out_wimask_455 = &_out_wimask_T_455; // @[RegisterRouter.scala:87:24]
wire out_romask_455 = |_out_romask_T_455; // @[RegisterRouter.scala:87:24]
wire out_womask_455 = &_out_womask_T_455; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_455 = out_rivalid_1_309 & out_rimask_455; // @[RegisterRouter.scala:87:24]
wire _out_T_4740 = out_f_rivalid_455; // @[RegisterRouter.scala:87:24]
wire out_f_roready_455 = out_roready_1_309 & out_romask_455; // @[RegisterRouter.scala:87:24]
wire _out_T_4741 = out_f_roready_455; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_455 = out_wivalid_1_309 & out_wimask_455; // @[RegisterRouter.scala:87:24]
wire out_f_woready_455 = out_woready_1_309 & out_womask_455; // @[RegisterRouter.scala:87:24]
wire _out_T_4742 = ~out_rimask_455; // @[RegisterRouter.scala:87:24]
wire _out_T_4743 = ~out_wimask_455; // @[RegisterRouter.scala:87:24]
wire _out_T_4744 = ~out_romask_455; // @[RegisterRouter.scala:87:24]
wire _out_T_4745 = ~out_womask_455; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_382 = {hi_742, flags_0_go, _out_prepend_T_382}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_4746 = out_prepend_382; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_4747 = _out_T_4746; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_383 = _out_T_4747; // @[RegisterRouter.scala:87:24]
wire out_rimask_456 = |_out_rimask_T_456; // @[RegisterRouter.scala:87:24]
wire out_wimask_456 = &_out_wimask_T_456; // @[RegisterRouter.scala:87:24]
wire out_romask_456 = |_out_romask_T_456; // @[RegisterRouter.scala:87:24]
wire out_womask_456 = &_out_womask_T_456; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_456 = out_rivalid_1_310 & out_rimask_456; // @[RegisterRouter.scala:87:24]
wire _out_T_4749 = out_f_rivalid_456; // @[RegisterRouter.scala:87:24]
wire out_f_roready_456 = out_roready_1_310 & out_romask_456; // @[RegisterRouter.scala:87:24]
wire _out_T_4750 = out_f_roready_456; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_456 = out_wivalid_1_310 & out_wimask_456; // @[RegisterRouter.scala:87:24]
wire out_f_woready_456 = out_woready_1_310 & out_womask_456; // @[RegisterRouter.scala:87:24]
wire _out_T_4751 = ~out_rimask_456; // @[RegisterRouter.scala:87:24]
wire _out_T_4752 = ~out_wimask_456; // @[RegisterRouter.scala:87:24]
wire _out_T_4753 = ~out_romask_456; // @[RegisterRouter.scala:87:24]
wire _out_T_4754 = ~out_womask_456; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_383 = {hi_743, flags_0_go, _out_prepend_T_383}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_4755 = out_prepend_383; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_4756 = _out_T_4755; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_384 = _out_T_4756; // @[RegisterRouter.scala:87:24]
wire out_rimask_457 = |_out_rimask_T_457; // @[RegisterRouter.scala:87:24]
wire out_wimask_457 = &_out_wimask_T_457; // @[RegisterRouter.scala:87:24]
wire out_romask_457 = |_out_romask_T_457; // @[RegisterRouter.scala:87:24]
wire out_womask_457 = &_out_womask_T_457; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_457 = out_rivalid_1_311 & out_rimask_457; // @[RegisterRouter.scala:87:24]
wire _out_T_4758 = out_f_rivalid_457; // @[RegisterRouter.scala:87:24]
wire out_f_roready_457 = out_roready_1_311 & out_romask_457; // @[RegisterRouter.scala:87:24]
wire _out_T_4759 = out_f_roready_457; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_457 = out_wivalid_1_311 & out_wimask_457; // @[RegisterRouter.scala:87:24]
wire out_f_woready_457 = out_woready_1_311 & out_womask_457; // @[RegisterRouter.scala:87:24]
wire _out_T_4760 = ~out_rimask_457; // @[RegisterRouter.scala:87:24]
wire _out_T_4761 = ~out_wimask_457; // @[RegisterRouter.scala:87:24]
wire _out_T_4762 = ~out_romask_457; // @[RegisterRouter.scala:87:24]
wire _out_T_4763 = ~out_womask_457; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_384 = {hi_744, flags_0_go, _out_prepend_T_384}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_4764 = out_prepend_384; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_4765 = _out_T_4764; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_220 = _out_T_4765; // @[MuxLiteral.scala:49:48]
wire out_rimask_458 = |_out_rimask_T_458; // @[RegisterRouter.scala:87:24]
wire out_wimask_458 = &_out_wimask_T_458; // @[RegisterRouter.scala:87:24]
wire out_romask_458 = |_out_romask_T_458; // @[RegisterRouter.scala:87:24]
wire out_womask_458 = &_out_womask_T_458; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_458 = out_rivalid_1_312 & out_rimask_458; // @[RegisterRouter.scala:87:24]
wire _out_T_4767 = out_f_rivalid_458; // @[RegisterRouter.scala:87:24]
wire out_f_roready_458 = out_roready_1_312 & out_romask_458; // @[RegisterRouter.scala:87:24]
wire _out_T_4768 = out_f_roready_458; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_458 = out_wivalid_1_312 & out_wimask_458; // @[RegisterRouter.scala:87:24]
wire out_f_woready_458 = out_woready_1_312 & out_womask_458; // @[RegisterRouter.scala:87:24]
wire _out_T_4769 = ~out_rimask_458; // @[RegisterRouter.scala:87:24]
wire _out_T_4770 = ~out_wimask_458; // @[RegisterRouter.scala:87:24]
wire _out_T_4771 = ~out_romask_458; // @[RegisterRouter.scala:87:24]
wire _out_T_4772 = ~out_womask_458; // @[RegisterRouter.scala:87:24]
wire out_rimask_459 = |_out_rimask_T_459; // @[RegisterRouter.scala:87:24]
wire out_wimask_459 = &_out_wimask_T_459; // @[RegisterRouter.scala:87:24]
wire out_romask_459 = |_out_romask_T_459; // @[RegisterRouter.scala:87:24]
wire out_womask_459 = &_out_womask_T_459; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_459 = out_rivalid_1_313 & out_rimask_459; // @[RegisterRouter.scala:87:24]
wire _out_T_4776 = out_f_rivalid_459; // @[RegisterRouter.scala:87:24]
wire out_f_roready_459 = out_roready_1_313 & out_romask_459; // @[RegisterRouter.scala:87:24]
wire _out_T_4777 = out_f_roready_459; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_459 = out_wivalid_1_313 & out_wimask_459; // @[RegisterRouter.scala:87:24]
wire out_f_woready_459 = out_woready_1_313 & out_womask_459; // @[RegisterRouter.scala:87:24]
wire _out_T_4778 = ~out_rimask_459; // @[RegisterRouter.scala:87:24]
wire _out_T_4779 = ~out_wimask_459; // @[RegisterRouter.scala:87:24]
wire _out_T_4780 = ~out_romask_459; // @[RegisterRouter.scala:87:24]
wire _out_T_4781 = ~out_womask_459; // @[RegisterRouter.scala:87:24]
wire out_rimask_460 = |_out_rimask_T_460; // @[RegisterRouter.scala:87:24]
wire out_wimask_460 = &_out_wimask_T_460; // @[RegisterRouter.scala:87:24]
wire out_romask_460 = |_out_romask_T_460; // @[RegisterRouter.scala:87:24]
wire out_womask_460 = &_out_womask_T_460; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_460 = out_rivalid_1_314 & out_rimask_460; // @[RegisterRouter.scala:87:24]
wire _out_T_4785 = out_f_rivalid_460; // @[RegisterRouter.scala:87:24]
wire out_f_roready_460 = out_roready_1_314 & out_romask_460; // @[RegisterRouter.scala:87:24]
wire _out_T_4786 = out_f_roready_460; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_460 = out_wivalid_1_314 & out_wimask_460; // @[RegisterRouter.scala:87:24]
wire out_f_woready_460 = out_woready_1_314 & out_womask_460; // @[RegisterRouter.scala:87:24]
wire _out_T_4787 = ~out_rimask_460; // @[RegisterRouter.scala:87:24]
wire _out_T_4788 = ~out_wimask_460; // @[RegisterRouter.scala:87:24]
wire _out_T_4789 = ~out_romask_460; // @[RegisterRouter.scala:87:24]
wire _out_T_4790 = ~out_womask_460; // @[RegisterRouter.scala:87:24]
wire out_rimask_461 = |_out_rimask_T_461; // @[RegisterRouter.scala:87:24]
wire out_wimask_461 = &_out_wimask_T_461; // @[RegisterRouter.scala:87:24]
wire out_romask_461 = |_out_romask_T_461; // @[RegisterRouter.scala:87:24]
wire out_womask_461 = &_out_womask_T_461; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_461 = out_rivalid_1_315 & out_rimask_461; // @[RegisterRouter.scala:87:24]
wire _out_T_4794 = out_f_rivalid_461; // @[RegisterRouter.scala:87:24]
wire out_f_roready_461 = out_roready_1_315 & out_romask_461; // @[RegisterRouter.scala:87:24]
wire _out_T_4795 = out_f_roready_461; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_461 = out_wivalid_1_315 & out_wimask_461; // @[RegisterRouter.scala:87:24]
wire out_f_woready_461 = out_woready_1_315 & out_womask_461; // @[RegisterRouter.scala:87:24]
wire _out_T_4796 = ~out_rimask_461; // @[RegisterRouter.scala:87:24]
wire _out_T_4797 = ~out_wimask_461; // @[RegisterRouter.scala:87:24]
wire _out_T_4798 = ~out_romask_461; // @[RegisterRouter.scala:87:24]
wire _out_T_4799 = ~out_womask_461; // @[RegisterRouter.scala:87:24]
wire out_rimask_462 = |_out_rimask_T_462; // @[RegisterRouter.scala:87:24]
wire out_wimask_462 = &_out_wimask_T_462; // @[RegisterRouter.scala:87:24]
wire out_romask_462 = |_out_romask_T_462; // @[RegisterRouter.scala:87:24]
wire out_womask_462 = &_out_womask_T_462; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_462 = out_rivalid_1_316 & out_rimask_462; // @[RegisterRouter.scala:87:24]
wire _out_T_4803 = out_f_rivalid_462; // @[RegisterRouter.scala:87:24]
wire out_f_roready_462 = out_roready_1_316 & out_romask_462; // @[RegisterRouter.scala:87:24]
wire _out_T_4804 = out_f_roready_462; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_462 = out_wivalid_1_316 & out_wimask_462; // @[RegisterRouter.scala:87:24]
wire out_f_woready_462 = out_woready_1_316 & out_womask_462; // @[RegisterRouter.scala:87:24]
wire _out_T_4805 = ~out_rimask_462; // @[RegisterRouter.scala:87:24]
wire _out_T_4806 = ~out_wimask_462; // @[RegisterRouter.scala:87:24]
wire _out_T_4807 = ~out_romask_462; // @[RegisterRouter.scala:87:24]
wire _out_T_4808 = ~out_womask_462; // @[RegisterRouter.scala:87:24]
wire out_rimask_463 = |_out_rimask_T_463; // @[RegisterRouter.scala:87:24]
wire out_wimask_463 = &_out_wimask_T_463; // @[RegisterRouter.scala:87:24]
wire out_romask_463 = |_out_romask_T_463; // @[RegisterRouter.scala:87:24]
wire out_womask_463 = &_out_womask_T_463; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_463 = out_rivalid_1_317 & out_rimask_463; // @[RegisterRouter.scala:87:24]
wire _out_T_4812 = out_f_rivalid_463; // @[RegisterRouter.scala:87:24]
wire out_f_roready_463 = out_roready_1_317 & out_romask_463; // @[RegisterRouter.scala:87:24]
wire _out_T_4813 = out_f_roready_463; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_463 = out_wivalid_1_317 & out_wimask_463; // @[RegisterRouter.scala:87:24]
wire out_f_woready_463 = out_woready_1_317 & out_womask_463; // @[RegisterRouter.scala:87:24]
wire _out_T_4814 = ~out_rimask_463; // @[RegisterRouter.scala:87:24]
wire _out_T_4815 = ~out_wimask_463; // @[RegisterRouter.scala:87:24]
wire _out_T_4816 = ~out_romask_463; // @[RegisterRouter.scala:87:24]
wire _out_T_4817 = ~out_womask_463; // @[RegisterRouter.scala:87:24]
wire out_rimask_464 = |_out_rimask_T_464; // @[RegisterRouter.scala:87:24]
wire out_wimask_464 = &_out_wimask_T_464; // @[RegisterRouter.scala:87:24]
wire out_romask_464 = |_out_romask_T_464; // @[RegisterRouter.scala:87:24]
wire out_womask_464 = &_out_womask_T_464; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_464 = out_rivalid_1_318 & out_rimask_464; // @[RegisterRouter.scala:87:24]
wire _out_T_4821 = out_f_rivalid_464; // @[RegisterRouter.scala:87:24]
wire out_f_roready_464 = out_roready_1_318 & out_romask_464; // @[RegisterRouter.scala:87:24]
wire _out_T_4822 = out_f_roready_464; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_464 = out_wivalid_1_318 & out_wimask_464; // @[RegisterRouter.scala:87:24]
wire out_f_woready_464 = out_woready_1_318 & out_womask_464; // @[RegisterRouter.scala:87:24]
wire _out_T_4823 = ~out_rimask_464; // @[RegisterRouter.scala:87:24]
wire _out_T_4824 = ~out_wimask_464; // @[RegisterRouter.scala:87:24]
wire _out_T_4825 = ~out_romask_464; // @[RegisterRouter.scala:87:24]
wire _out_T_4826 = ~out_womask_464; // @[RegisterRouter.scala:87:24]
wire out_rimask_465 = |_out_rimask_T_465; // @[RegisterRouter.scala:87:24]
wire out_wimask_465 = &_out_wimask_T_465; // @[RegisterRouter.scala:87:24]
wire out_romask_465 = |_out_romask_T_465; // @[RegisterRouter.scala:87:24]
wire out_womask_465 = &_out_womask_T_465; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_465 = out_rivalid_1_319 & out_rimask_465; // @[RegisterRouter.scala:87:24]
wire _out_T_4830 = out_f_rivalid_465; // @[RegisterRouter.scala:87:24]
wire out_f_roready_465 = out_roready_1_319 & out_romask_465; // @[RegisterRouter.scala:87:24]
wire _out_T_4831 = out_f_roready_465; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_465 = out_wivalid_1_319 & out_wimask_465; // @[RegisterRouter.scala:87:24]
wire out_f_woready_465 = out_woready_1_319 & out_womask_465; // @[RegisterRouter.scala:87:24]
wire _out_T_4832 = ~out_rimask_465; // @[RegisterRouter.scala:87:24]
wire _out_T_4833 = ~out_wimask_465; // @[RegisterRouter.scala:87:24]
wire _out_T_4834 = ~out_romask_465; // @[RegisterRouter.scala:87:24]
wire _out_T_4835 = ~out_womask_465; // @[RegisterRouter.scala:87:24]
wire out_rimask_466 = |_out_rimask_T_466; // @[RegisterRouter.scala:87:24]
wire out_wimask_466 = &_out_wimask_T_466; // @[RegisterRouter.scala:87:24]
wire out_romask_466 = |_out_romask_T_466; // @[RegisterRouter.scala:87:24]
wire out_womask_466 = &_out_womask_T_466; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_466 = out_rivalid_1_320 & out_rimask_466; // @[RegisterRouter.scala:87:24]
wire _out_T_4839 = out_f_rivalid_466; // @[RegisterRouter.scala:87:24]
wire out_f_roready_466 = out_roready_1_320 & out_romask_466; // @[RegisterRouter.scala:87:24]
wire _out_T_4840 = out_f_roready_466; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_466 = out_wivalid_1_320 & out_wimask_466; // @[RegisterRouter.scala:87:24]
wire out_f_woready_466 = out_woready_1_320 & out_womask_466; // @[RegisterRouter.scala:87:24]
wire _out_T_4841 = ~out_rimask_466; // @[RegisterRouter.scala:87:24]
wire _out_T_4842 = ~out_wimask_466; // @[RegisterRouter.scala:87:24]
wire _out_T_4843 = ~out_romask_466; // @[RegisterRouter.scala:87:24]
wire _out_T_4844 = ~out_womask_466; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4846 = _out_T_4845; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_392 = _out_T_4846; // @[RegisterRouter.scala:87:24]
wire out_rimask_467 = |_out_rimask_T_467; // @[RegisterRouter.scala:87:24]
wire out_wimask_467 = &_out_wimask_T_467; // @[RegisterRouter.scala:87:24]
wire out_romask_467 = |_out_romask_T_467; // @[RegisterRouter.scala:87:24]
wire out_womask_467 = &_out_womask_T_467; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_467 = out_rivalid_1_321 & out_rimask_467; // @[RegisterRouter.scala:87:24]
wire _out_T_4848 = out_f_rivalid_467; // @[RegisterRouter.scala:87:24]
wire out_f_roready_467 = out_roready_1_321 & out_romask_467; // @[RegisterRouter.scala:87:24]
wire _out_T_4849 = out_f_roready_467; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_467 = out_wivalid_1_321 & out_wimask_467; // @[RegisterRouter.scala:87:24]
wire out_f_woready_467 = out_woready_1_321 & out_womask_467; // @[RegisterRouter.scala:87:24]
wire _out_T_4850 = ~out_rimask_467; // @[RegisterRouter.scala:87:24]
wire _out_T_4851 = ~out_wimask_467; // @[RegisterRouter.scala:87:24]
wire _out_T_4852 = ~out_romask_467; // @[RegisterRouter.scala:87:24]
wire _out_T_4853 = ~out_womask_467; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_392 = {hi_258, flags_0_go, _out_prepend_T_392}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_4854 = out_prepend_392; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_4855 = _out_T_4854; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_393 = _out_T_4855; // @[RegisterRouter.scala:87:24]
wire out_rimask_468 = |_out_rimask_T_468; // @[RegisterRouter.scala:87:24]
wire out_wimask_468 = &_out_wimask_T_468; // @[RegisterRouter.scala:87:24]
wire out_romask_468 = |_out_romask_T_468; // @[RegisterRouter.scala:87:24]
wire out_womask_468 = &_out_womask_T_468; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_468 = out_rivalid_1_322 & out_rimask_468; // @[RegisterRouter.scala:87:24]
wire _out_T_4857 = out_f_rivalid_468; // @[RegisterRouter.scala:87:24]
wire out_f_roready_468 = out_roready_1_322 & out_romask_468; // @[RegisterRouter.scala:87:24]
wire _out_T_4858 = out_f_roready_468; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_468 = out_wivalid_1_322 & out_wimask_468; // @[RegisterRouter.scala:87:24]
wire out_f_woready_468 = out_woready_1_322 & out_womask_468; // @[RegisterRouter.scala:87:24]
wire _out_T_4859 = ~out_rimask_468; // @[RegisterRouter.scala:87:24]
wire _out_T_4860 = ~out_wimask_468; // @[RegisterRouter.scala:87:24]
wire _out_T_4861 = ~out_romask_468; // @[RegisterRouter.scala:87:24]
wire _out_T_4862 = ~out_womask_468; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_393 = {hi_259, flags_0_go, _out_prepend_T_393}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_4863 = out_prepend_393; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_4864 = _out_T_4863; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_394 = _out_T_4864; // @[RegisterRouter.scala:87:24]
wire out_rimask_469 = |_out_rimask_T_469; // @[RegisterRouter.scala:87:24]
wire out_wimask_469 = &_out_wimask_T_469; // @[RegisterRouter.scala:87:24]
wire out_romask_469 = |_out_romask_T_469; // @[RegisterRouter.scala:87:24]
wire out_womask_469 = &_out_womask_T_469; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_469 = out_rivalid_1_323 & out_rimask_469; // @[RegisterRouter.scala:87:24]
wire _out_T_4866 = out_f_rivalid_469; // @[RegisterRouter.scala:87:24]
wire out_f_roready_469 = out_roready_1_323 & out_romask_469; // @[RegisterRouter.scala:87:24]
wire _out_T_4867 = out_f_roready_469; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_469 = out_wivalid_1_323 & out_wimask_469; // @[RegisterRouter.scala:87:24]
wire out_f_woready_469 = out_woready_1_323 & out_womask_469; // @[RegisterRouter.scala:87:24]
wire _out_T_4868 = ~out_rimask_469; // @[RegisterRouter.scala:87:24]
wire _out_T_4869 = ~out_wimask_469; // @[RegisterRouter.scala:87:24]
wire _out_T_4870 = ~out_romask_469; // @[RegisterRouter.scala:87:24]
wire _out_T_4871 = ~out_womask_469; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_394 = {hi_260, flags_0_go, _out_prepend_T_394}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_4872 = out_prepend_394; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_4873 = _out_T_4872; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_395 = _out_T_4873; // @[RegisterRouter.scala:87:24]
wire out_rimask_470 = |_out_rimask_T_470; // @[RegisterRouter.scala:87:24]
wire out_wimask_470 = &_out_wimask_T_470; // @[RegisterRouter.scala:87:24]
wire out_romask_470 = |_out_romask_T_470; // @[RegisterRouter.scala:87:24]
wire out_womask_470 = &_out_womask_T_470; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_470 = out_rivalid_1_324 & out_rimask_470; // @[RegisterRouter.scala:87:24]
wire _out_T_4875 = out_f_rivalid_470; // @[RegisterRouter.scala:87:24]
wire out_f_roready_470 = out_roready_1_324 & out_romask_470; // @[RegisterRouter.scala:87:24]
wire _out_T_4876 = out_f_roready_470; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_470 = out_wivalid_1_324 & out_wimask_470; // @[RegisterRouter.scala:87:24]
wire out_f_woready_470 = out_woready_1_324 & out_womask_470; // @[RegisterRouter.scala:87:24]
wire _out_T_4877 = ~out_rimask_470; // @[RegisterRouter.scala:87:24]
wire _out_T_4878 = ~out_wimask_470; // @[RegisterRouter.scala:87:24]
wire _out_T_4879 = ~out_romask_470; // @[RegisterRouter.scala:87:24]
wire _out_T_4880 = ~out_womask_470; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_395 = {hi_261, flags_0_go, _out_prepend_T_395}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_4881 = out_prepend_395; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_4882 = _out_T_4881; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_396 = _out_T_4882; // @[RegisterRouter.scala:87:24]
wire out_rimask_471 = |_out_rimask_T_471; // @[RegisterRouter.scala:87:24]
wire out_wimask_471 = &_out_wimask_T_471; // @[RegisterRouter.scala:87:24]
wire out_romask_471 = |_out_romask_T_471; // @[RegisterRouter.scala:87:24]
wire out_womask_471 = &_out_womask_T_471; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_471 = out_rivalid_1_325 & out_rimask_471; // @[RegisterRouter.scala:87:24]
wire _out_T_4884 = out_f_rivalid_471; // @[RegisterRouter.scala:87:24]
wire out_f_roready_471 = out_roready_1_325 & out_romask_471; // @[RegisterRouter.scala:87:24]
wire _out_T_4885 = out_f_roready_471; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_471 = out_wivalid_1_325 & out_wimask_471; // @[RegisterRouter.scala:87:24]
wire out_f_woready_471 = out_woready_1_325 & out_womask_471; // @[RegisterRouter.scala:87:24]
wire _out_T_4886 = ~out_rimask_471; // @[RegisterRouter.scala:87:24]
wire _out_T_4887 = ~out_wimask_471; // @[RegisterRouter.scala:87:24]
wire _out_T_4888 = ~out_romask_471; // @[RegisterRouter.scala:87:24]
wire _out_T_4889 = ~out_womask_471; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_396 = {hi_262, flags_0_go, _out_prepend_T_396}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_4890 = out_prepend_396; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_4891 = _out_T_4890; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_397 = _out_T_4891; // @[RegisterRouter.scala:87:24]
wire out_rimask_472 = |_out_rimask_T_472; // @[RegisterRouter.scala:87:24]
wire out_wimask_472 = &_out_wimask_T_472; // @[RegisterRouter.scala:87:24]
wire out_romask_472 = |_out_romask_T_472; // @[RegisterRouter.scala:87:24]
wire out_womask_472 = &_out_womask_T_472; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_472 = out_rivalid_1_326 & out_rimask_472; // @[RegisterRouter.scala:87:24]
wire _out_T_4893 = out_f_rivalid_472; // @[RegisterRouter.scala:87:24]
wire out_f_roready_472 = out_roready_1_326 & out_romask_472; // @[RegisterRouter.scala:87:24]
wire _out_T_4894 = out_f_roready_472; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_472 = out_wivalid_1_326 & out_wimask_472; // @[RegisterRouter.scala:87:24]
wire out_f_woready_472 = out_woready_1_326 & out_womask_472; // @[RegisterRouter.scala:87:24]
wire _out_T_4895 = ~out_rimask_472; // @[RegisterRouter.scala:87:24]
wire _out_T_4896 = ~out_wimask_472; // @[RegisterRouter.scala:87:24]
wire _out_T_4897 = ~out_romask_472; // @[RegisterRouter.scala:87:24]
wire _out_T_4898 = ~out_womask_472; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_397 = {hi_263, flags_0_go, _out_prepend_T_397}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_4899 = out_prepend_397; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_4900 = _out_T_4899; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_398 = _out_T_4900; // @[RegisterRouter.scala:87:24]
wire out_rimask_473 = |_out_rimask_T_473; // @[RegisterRouter.scala:87:24]
wire out_wimask_473 = &_out_wimask_T_473; // @[RegisterRouter.scala:87:24]
wire out_romask_473 = |_out_romask_T_473; // @[RegisterRouter.scala:87:24]
wire out_womask_473 = &_out_womask_T_473; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_473 = out_rivalid_1_327 & out_rimask_473; // @[RegisterRouter.scala:87:24]
wire _out_T_4902 = out_f_rivalid_473; // @[RegisterRouter.scala:87:24]
wire out_f_roready_473 = out_roready_1_327 & out_romask_473; // @[RegisterRouter.scala:87:24]
wire _out_T_4903 = out_f_roready_473; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_473 = out_wivalid_1_327 & out_wimask_473; // @[RegisterRouter.scala:87:24]
wire out_f_woready_473 = out_woready_1_327 & out_womask_473; // @[RegisterRouter.scala:87:24]
wire _out_T_4904 = ~out_rimask_473; // @[RegisterRouter.scala:87:24]
wire _out_T_4905 = ~out_wimask_473; // @[RegisterRouter.scala:87:24]
wire _out_T_4906 = ~out_romask_473; // @[RegisterRouter.scala:87:24]
wire _out_T_4907 = ~out_womask_473; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_398 = {hi_264, flags_0_go, _out_prepend_T_398}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_4908 = out_prepend_398; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_4909 = _out_T_4908; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_160 = _out_T_4909; // @[MuxLiteral.scala:49:48]
wire out_rimask_474 = |_out_rimask_T_474; // @[RegisterRouter.scala:87:24]
wire out_wimask_474 = &_out_wimask_T_474; // @[RegisterRouter.scala:87:24]
wire out_romask_474 = |_out_romask_T_474; // @[RegisterRouter.scala:87:24]
wire out_womask_474 = &_out_womask_T_474; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_474 = out_rivalid_1_328 & out_rimask_474; // @[RegisterRouter.scala:87:24]
wire _out_T_4911 = out_f_rivalid_474; // @[RegisterRouter.scala:87:24]
wire out_f_roready_474 = out_roready_1_328 & out_romask_474; // @[RegisterRouter.scala:87:24]
wire _out_T_4912 = out_f_roready_474; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_474 = out_wivalid_1_328 & out_wimask_474; // @[RegisterRouter.scala:87:24]
wire out_f_woready_474 = out_woready_1_328 & out_womask_474; // @[RegisterRouter.scala:87:24]
wire _out_T_4913 = ~out_rimask_474; // @[RegisterRouter.scala:87:24]
wire _out_T_4914 = ~out_wimask_474; // @[RegisterRouter.scala:87:24]
wire _out_T_4915 = ~out_romask_474; // @[RegisterRouter.scala:87:24]
wire _out_T_4916 = ~out_womask_474; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4918 = _out_T_4917; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_399 = _out_T_4918; // @[RegisterRouter.scala:87:24]
wire out_rimask_475 = |_out_rimask_T_475; // @[RegisterRouter.scala:87:24]
wire out_wimask_475 = &_out_wimask_T_475; // @[RegisterRouter.scala:87:24]
wire out_romask_475 = |_out_romask_T_475; // @[RegisterRouter.scala:87:24]
wire out_womask_475 = &_out_womask_T_475; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_475 = out_rivalid_1_329 & out_rimask_475; // @[RegisterRouter.scala:87:24]
wire _out_T_4920 = out_f_rivalid_475; // @[RegisterRouter.scala:87:24]
wire out_f_roready_475 = out_roready_1_329 & out_romask_475; // @[RegisterRouter.scala:87:24]
wire _out_T_4921 = out_f_roready_475; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_475 = out_wivalid_1_329 & out_wimask_475; // @[RegisterRouter.scala:87:24]
wire out_f_woready_475 = out_woready_1_329 & out_womask_475; // @[RegisterRouter.scala:87:24]
wire _out_T_4922 = ~out_rimask_475; // @[RegisterRouter.scala:87:24]
wire _out_T_4923 = ~out_wimask_475; // @[RegisterRouter.scala:87:24]
wire _out_T_4924 = ~out_romask_475; // @[RegisterRouter.scala:87:24]
wire _out_T_4925 = ~out_womask_475; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_399 = {hi_514, flags_0_go, _out_prepend_T_399}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_4926 = out_prepend_399; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_4927 = _out_T_4926; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_400 = _out_T_4927; // @[RegisterRouter.scala:87:24]
wire out_rimask_476 = |_out_rimask_T_476; // @[RegisterRouter.scala:87:24]
wire out_wimask_476 = &_out_wimask_T_476; // @[RegisterRouter.scala:87:24]
wire out_romask_476 = |_out_romask_T_476; // @[RegisterRouter.scala:87:24]
wire out_womask_476 = &_out_womask_T_476; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_476 = out_rivalid_1_330 & out_rimask_476; // @[RegisterRouter.scala:87:24]
wire _out_T_4929 = out_f_rivalid_476; // @[RegisterRouter.scala:87:24]
wire out_f_roready_476 = out_roready_1_330 & out_romask_476; // @[RegisterRouter.scala:87:24]
wire _out_T_4930 = out_f_roready_476; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_476 = out_wivalid_1_330 & out_wimask_476; // @[RegisterRouter.scala:87:24]
wire out_f_woready_476 = out_woready_1_330 & out_womask_476; // @[RegisterRouter.scala:87:24]
wire _out_T_4931 = ~out_rimask_476; // @[RegisterRouter.scala:87:24]
wire _out_T_4932 = ~out_wimask_476; // @[RegisterRouter.scala:87:24]
wire _out_T_4933 = ~out_romask_476; // @[RegisterRouter.scala:87:24]
wire _out_T_4934 = ~out_womask_476; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_400 = {hi_515, flags_0_go, _out_prepend_T_400}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_4935 = out_prepend_400; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_4936 = _out_T_4935; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_401 = _out_T_4936; // @[RegisterRouter.scala:87:24]
wire out_rimask_477 = |_out_rimask_T_477; // @[RegisterRouter.scala:87:24]
wire out_wimask_477 = &_out_wimask_T_477; // @[RegisterRouter.scala:87:24]
wire out_romask_477 = |_out_romask_T_477; // @[RegisterRouter.scala:87:24]
wire out_womask_477 = &_out_womask_T_477; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_477 = out_rivalid_1_331 & out_rimask_477; // @[RegisterRouter.scala:87:24]
wire _out_T_4938 = out_f_rivalid_477; // @[RegisterRouter.scala:87:24]
wire out_f_roready_477 = out_roready_1_331 & out_romask_477; // @[RegisterRouter.scala:87:24]
wire _out_T_4939 = out_f_roready_477; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_477 = out_wivalid_1_331 & out_wimask_477; // @[RegisterRouter.scala:87:24]
wire out_f_woready_477 = out_woready_1_331 & out_womask_477; // @[RegisterRouter.scala:87:24]
wire _out_T_4940 = ~out_rimask_477; // @[RegisterRouter.scala:87:24]
wire _out_T_4941 = ~out_wimask_477; // @[RegisterRouter.scala:87:24]
wire _out_T_4942 = ~out_romask_477; // @[RegisterRouter.scala:87:24]
wire _out_T_4943 = ~out_womask_477; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_401 = {hi_516, flags_0_go, _out_prepend_T_401}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_4944 = out_prepend_401; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_4945 = _out_T_4944; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_402 = _out_T_4945; // @[RegisterRouter.scala:87:24]
wire out_rimask_478 = |_out_rimask_T_478; // @[RegisterRouter.scala:87:24]
wire out_wimask_478 = &_out_wimask_T_478; // @[RegisterRouter.scala:87:24]
wire out_romask_478 = |_out_romask_T_478; // @[RegisterRouter.scala:87:24]
wire out_womask_478 = &_out_womask_T_478; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_478 = out_rivalid_1_332 & out_rimask_478; // @[RegisterRouter.scala:87:24]
wire _out_T_4947 = out_f_rivalid_478; // @[RegisterRouter.scala:87:24]
wire out_f_roready_478 = out_roready_1_332 & out_romask_478; // @[RegisterRouter.scala:87:24]
wire _out_T_4948 = out_f_roready_478; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_478 = out_wivalid_1_332 & out_wimask_478; // @[RegisterRouter.scala:87:24]
wire out_f_woready_478 = out_woready_1_332 & out_womask_478; // @[RegisterRouter.scala:87:24]
wire _out_T_4949 = ~out_rimask_478; // @[RegisterRouter.scala:87:24]
wire _out_T_4950 = ~out_wimask_478; // @[RegisterRouter.scala:87:24]
wire _out_T_4951 = ~out_romask_478; // @[RegisterRouter.scala:87:24]
wire _out_T_4952 = ~out_womask_478; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_402 = {hi_517, flags_0_go, _out_prepend_T_402}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_4953 = out_prepend_402; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_4954 = _out_T_4953; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_403 = _out_T_4954; // @[RegisterRouter.scala:87:24]
wire out_rimask_479 = |_out_rimask_T_479; // @[RegisterRouter.scala:87:24]
wire out_wimask_479 = &_out_wimask_T_479; // @[RegisterRouter.scala:87:24]
wire out_romask_479 = |_out_romask_T_479; // @[RegisterRouter.scala:87:24]
wire out_womask_479 = &_out_womask_T_479; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_479 = out_rivalid_1_333 & out_rimask_479; // @[RegisterRouter.scala:87:24]
wire _out_T_4956 = out_f_rivalid_479; // @[RegisterRouter.scala:87:24]
wire out_f_roready_479 = out_roready_1_333 & out_romask_479; // @[RegisterRouter.scala:87:24]
wire _out_T_4957 = out_f_roready_479; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_479 = out_wivalid_1_333 & out_wimask_479; // @[RegisterRouter.scala:87:24]
wire out_f_woready_479 = out_woready_1_333 & out_womask_479; // @[RegisterRouter.scala:87:24]
wire _out_T_4958 = ~out_rimask_479; // @[RegisterRouter.scala:87:24]
wire _out_T_4959 = ~out_wimask_479; // @[RegisterRouter.scala:87:24]
wire _out_T_4960 = ~out_romask_479; // @[RegisterRouter.scala:87:24]
wire _out_T_4961 = ~out_womask_479; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_403 = {hi_518, flags_0_go, _out_prepend_T_403}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_4962 = out_prepend_403; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_4963 = _out_T_4962; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_404 = _out_T_4963; // @[RegisterRouter.scala:87:24]
wire out_rimask_480 = |_out_rimask_T_480; // @[RegisterRouter.scala:87:24]
wire out_wimask_480 = &_out_wimask_T_480; // @[RegisterRouter.scala:87:24]
wire out_romask_480 = |_out_romask_T_480; // @[RegisterRouter.scala:87:24]
wire out_womask_480 = &_out_womask_T_480; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_480 = out_rivalid_1_334 & out_rimask_480; // @[RegisterRouter.scala:87:24]
wire _out_T_4965 = out_f_rivalid_480; // @[RegisterRouter.scala:87:24]
wire out_f_roready_480 = out_roready_1_334 & out_romask_480; // @[RegisterRouter.scala:87:24]
wire _out_T_4966 = out_f_roready_480; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_480 = out_wivalid_1_334 & out_wimask_480; // @[RegisterRouter.scala:87:24]
wire out_f_woready_480 = out_woready_1_334 & out_womask_480; // @[RegisterRouter.scala:87:24]
wire _out_T_4967 = ~out_rimask_480; // @[RegisterRouter.scala:87:24]
wire _out_T_4968 = ~out_wimask_480; // @[RegisterRouter.scala:87:24]
wire _out_T_4969 = ~out_romask_480; // @[RegisterRouter.scala:87:24]
wire _out_T_4970 = ~out_womask_480; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_404 = {hi_519, flags_0_go, _out_prepend_T_404}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_4971 = out_prepend_404; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_4972 = _out_T_4971; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_405 = _out_T_4972; // @[RegisterRouter.scala:87:24]
wire out_rimask_481 = |_out_rimask_T_481; // @[RegisterRouter.scala:87:24]
wire out_wimask_481 = &_out_wimask_T_481; // @[RegisterRouter.scala:87:24]
wire out_romask_481 = |_out_romask_T_481; // @[RegisterRouter.scala:87:24]
wire out_womask_481 = &_out_womask_T_481; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_481 = out_rivalid_1_335 & out_rimask_481; // @[RegisterRouter.scala:87:24]
wire _out_T_4974 = out_f_rivalid_481; // @[RegisterRouter.scala:87:24]
wire out_f_roready_481 = out_roready_1_335 & out_romask_481; // @[RegisterRouter.scala:87:24]
wire _out_T_4975 = out_f_roready_481; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_481 = out_wivalid_1_335 & out_wimask_481; // @[RegisterRouter.scala:87:24]
wire out_f_woready_481 = out_woready_1_335 & out_womask_481; // @[RegisterRouter.scala:87:24]
wire _out_T_4976 = ~out_rimask_481; // @[RegisterRouter.scala:87:24]
wire _out_T_4977 = ~out_wimask_481; // @[RegisterRouter.scala:87:24]
wire _out_T_4978 = ~out_romask_481; // @[RegisterRouter.scala:87:24]
wire _out_T_4979 = ~out_womask_481; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_405 = {hi_520, flags_0_go, _out_prepend_T_405}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_4980 = out_prepend_405; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_4981 = _out_T_4980; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_192 = _out_T_4981; // @[MuxLiteral.scala:49:48]
wire out_rimask_482 = |_out_rimask_T_482; // @[RegisterRouter.scala:87:24]
wire out_wimask_482 = &_out_wimask_T_482; // @[RegisterRouter.scala:87:24]
wire out_romask_482 = |_out_romask_T_482; // @[RegisterRouter.scala:87:24]
wire out_womask_482 = &_out_womask_T_482; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_482 = out_rivalid_1_336 & out_rimask_482; // @[RegisterRouter.scala:87:24]
wire _out_T_4983 = out_f_rivalid_482; // @[RegisterRouter.scala:87:24]
wire out_f_roready_482 = out_roready_1_336 & out_romask_482; // @[RegisterRouter.scala:87:24]
wire _out_T_4984 = out_f_roready_482; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_482 = out_wivalid_1_336 & out_wimask_482; // @[RegisterRouter.scala:87:24]
wire out_f_woready_482 = out_woready_1_336 & out_womask_482; // @[RegisterRouter.scala:87:24]
wire _out_T_4985 = ~out_rimask_482; // @[RegisterRouter.scala:87:24]
wire _out_T_4986 = ~out_wimask_482; // @[RegisterRouter.scala:87:24]
wire _out_T_4987 = ~out_romask_482; // @[RegisterRouter.scala:87:24]
wire _out_T_4988 = ~out_womask_482; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_4990 = _out_T_4989; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_406 = _out_T_4990; // @[RegisterRouter.scala:87:24]
wire out_rimask_483 = |_out_rimask_T_483; // @[RegisterRouter.scala:87:24]
wire out_wimask_483 = &_out_wimask_T_483; // @[RegisterRouter.scala:87:24]
wire out_romask_483 = |_out_romask_T_483; // @[RegisterRouter.scala:87:24]
wire out_womask_483 = &_out_womask_T_483; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_483 = out_rivalid_1_337 & out_rimask_483; // @[RegisterRouter.scala:87:24]
wire _out_T_4992 = out_f_rivalid_483; // @[RegisterRouter.scala:87:24]
wire out_f_roready_483 = out_roready_1_337 & out_romask_483; // @[RegisterRouter.scala:87:24]
wire _out_T_4993 = out_f_roready_483; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_483 = out_wivalid_1_337 & out_wimask_483; // @[RegisterRouter.scala:87:24]
wire out_f_woready_483 = out_woready_1_337 & out_womask_483; // @[RegisterRouter.scala:87:24]
wire _out_T_4994 = ~out_rimask_483; // @[RegisterRouter.scala:87:24]
wire _out_T_4995 = ~out_wimask_483; // @[RegisterRouter.scala:87:24]
wire _out_T_4996 = ~out_romask_483; // @[RegisterRouter.scala:87:24]
wire _out_T_4997 = ~out_womask_483; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_406 = {hi_74, flags_0_go, _out_prepend_T_406}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_4998 = out_prepend_406; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_4999 = _out_T_4998; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_407 = _out_T_4999; // @[RegisterRouter.scala:87:24]
wire out_rimask_484 = |_out_rimask_T_484; // @[RegisterRouter.scala:87:24]
wire out_wimask_484 = &_out_wimask_T_484; // @[RegisterRouter.scala:87:24]
wire out_romask_484 = |_out_romask_T_484; // @[RegisterRouter.scala:87:24]
wire out_womask_484 = &_out_womask_T_484; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_484 = out_rivalid_1_338 & out_rimask_484; // @[RegisterRouter.scala:87:24]
wire _out_T_5001 = out_f_rivalid_484; // @[RegisterRouter.scala:87:24]
wire out_f_roready_484 = out_roready_1_338 & out_romask_484; // @[RegisterRouter.scala:87:24]
wire _out_T_5002 = out_f_roready_484; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_484 = out_wivalid_1_338 & out_wimask_484; // @[RegisterRouter.scala:87:24]
wire out_f_woready_484 = out_woready_1_338 & out_womask_484; // @[RegisterRouter.scala:87:24]
wire _out_T_5003 = ~out_rimask_484; // @[RegisterRouter.scala:87:24]
wire _out_T_5004 = ~out_wimask_484; // @[RegisterRouter.scala:87:24]
wire _out_T_5005 = ~out_romask_484; // @[RegisterRouter.scala:87:24]
wire _out_T_5006 = ~out_womask_484; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_407 = {hi_75, flags_0_go, _out_prepend_T_407}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_5007 = out_prepend_407; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_5008 = _out_T_5007; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_408 = _out_T_5008; // @[RegisterRouter.scala:87:24]
wire out_rimask_485 = |_out_rimask_T_485; // @[RegisterRouter.scala:87:24]
wire out_wimask_485 = &_out_wimask_T_485; // @[RegisterRouter.scala:87:24]
wire out_romask_485 = |_out_romask_T_485; // @[RegisterRouter.scala:87:24]
wire out_womask_485 = &_out_womask_T_485; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_485 = out_rivalid_1_339 & out_rimask_485; // @[RegisterRouter.scala:87:24]
wire _out_T_5010 = out_f_rivalid_485; // @[RegisterRouter.scala:87:24]
wire out_f_roready_485 = out_roready_1_339 & out_romask_485; // @[RegisterRouter.scala:87:24]
wire _out_T_5011 = out_f_roready_485; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_485 = out_wivalid_1_339 & out_wimask_485; // @[RegisterRouter.scala:87:24]
wire out_f_woready_485 = out_woready_1_339 & out_womask_485; // @[RegisterRouter.scala:87:24]
wire _out_T_5012 = ~out_rimask_485; // @[RegisterRouter.scala:87:24]
wire _out_T_5013 = ~out_wimask_485; // @[RegisterRouter.scala:87:24]
wire _out_T_5014 = ~out_romask_485; // @[RegisterRouter.scala:87:24]
wire _out_T_5015 = ~out_womask_485; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_408 = {hi_76, flags_0_go, _out_prepend_T_408}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_5016 = out_prepend_408; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_5017 = _out_T_5016; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_409 = _out_T_5017; // @[RegisterRouter.scala:87:24]
wire out_rimask_486 = |_out_rimask_T_486; // @[RegisterRouter.scala:87:24]
wire out_wimask_486 = &_out_wimask_T_486; // @[RegisterRouter.scala:87:24]
wire out_romask_486 = |_out_romask_T_486; // @[RegisterRouter.scala:87:24]
wire out_womask_486 = &_out_womask_T_486; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_486 = out_rivalid_1_340 & out_rimask_486; // @[RegisterRouter.scala:87:24]
wire _out_T_5019 = out_f_rivalid_486; // @[RegisterRouter.scala:87:24]
wire out_f_roready_486 = out_roready_1_340 & out_romask_486; // @[RegisterRouter.scala:87:24]
wire _out_T_5020 = out_f_roready_486; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_486 = out_wivalid_1_340 & out_wimask_486; // @[RegisterRouter.scala:87:24]
wire out_f_woready_486 = out_woready_1_340 & out_womask_486; // @[RegisterRouter.scala:87:24]
wire _out_T_5021 = ~out_rimask_486; // @[RegisterRouter.scala:87:24]
wire _out_T_5022 = ~out_wimask_486; // @[RegisterRouter.scala:87:24]
wire _out_T_5023 = ~out_romask_486; // @[RegisterRouter.scala:87:24]
wire _out_T_5024 = ~out_womask_486; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_409 = {hi_77, flags_0_go, _out_prepend_T_409}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_5025 = out_prepend_409; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_5026 = _out_T_5025; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_410 = _out_T_5026; // @[RegisterRouter.scala:87:24]
wire out_rimask_487 = |_out_rimask_T_487; // @[RegisterRouter.scala:87:24]
wire out_wimask_487 = &_out_wimask_T_487; // @[RegisterRouter.scala:87:24]
wire out_romask_487 = |_out_romask_T_487; // @[RegisterRouter.scala:87:24]
wire out_womask_487 = &_out_womask_T_487; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_487 = out_rivalid_1_341 & out_rimask_487; // @[RegisterRouter.scala:87:24]
wire _out_T_5028 = out_f_rivalid_487; // @[RegisterRouter.scala:87:24]
wire out_f_roready_487 = out_roready_1_341 & out_romask_487; // @[RegisterRouter.scala:87:24]
wire _out_T_5029 = out_f_roready_487; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_487 = out_wivalid_1_341 & out_wimask_487; // @[RegisterRouter.scala:87:24]
wire out_f_woready_487 = out_woready_1_341 & out_womask_487; // @[RegisterRouter.scala:87:24]
wire _out_T_5030 = ~out_rimask_487; // @[RegisterRouter.scala:87:24]
wire _out_T_5031 = ~out_wimask_487; // @[RegisterRouter.scala:87:24]
wire _out_T_5032 = ~out_romask_487; // @[RegisterRouter.scala:87:24]
wire _out_T_5033 = ~out_womask_487; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_410 = {hi_78, flags_0_go, _out_prepend_T_410}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_5034 = out_prepend_410; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_5035 = _out_T_5034; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_411 = _out_T_5035; // @[RegisterRouter.scala:87:24]
wire out_rimask_488 = |_out_rimask_T_488; // @[RegisterRouter.scala:87:24]
wire out_wimask_488 = &_out_wimask_T_488; // @[RegisterRouter.scala:87:24]
wire out_romask_488 = |_out_romask_T_488; // @[RegisterRouter.scala:87:24]
wire out_womask_488 = &_out_womask_T_488; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_488 = out_rivalid_1_342 & out_rimask_488; // @[RegisterRouter.scala:87:24]
wire _out_T_5037 = out_f_rivalid_488; // @[RegisterRouter.scala:87:24]
wire out_f_roready_488 = out_roready_1_342 & out_romask_488; // @[RegisterRouter.scala:87:24]
wire _out_T_5038 = out_f_roready_488; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_488 = out_wivalid_1_342 & out_wimask_488; // @[RegisterRouter.scala:87:24]
wire out_f_woready_488 = out_woready_1_342 & out_womask_488; // @[RegisterRouter.scala:87:24]
wire _out_T_5039 = ~out_rimask_488; // @[RegisterRouter.scala:87:24]
wire _out_T_5040 = ~out_wimask_488; // @[RegisterRouter.scala:87:24]
wire _out_T_5041 = ~out_romask_488; // @[RegisterRouter.scala:87:24]
wire _out_T_5042 = ~out_womask_488; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_411 = {hi_79, flags_0_go, _out_prepend_T_411}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_5043 = out_prepend_411; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_5044 = _out_T_5043; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_412 = _out_T_5044; // @[RegisterRouter.scala:87:24]
wire out_rimask_489 = |_out_rimask_T_489; // @[RegisterRouter.scala:87:24]
wire out_wimask_489 = &_out_wimask_T_489; // @[RegisterRouter.scala:87:24]
wire out_romask_489 = |_out_romask_T_489; // @[RegisterRouter.scala:87:24]
wire out_womask_489 = &_out_womask_T_489; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_489 = out_rivalid_1_343 & out_rimask_489; // @[RegisterRouter.scala:87:24]
wire _out_T_5046 = out_f_rivalid_489; // @[RegisterRouter.scala:87:24]
wire out_f_roready_489 = out_roready_1_343 & out_romask_489; // @[RegisterRouter.scala:87:24]
wire _out_T_5047 = out_f_roready_489; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_489 = out_wivalid_1_343 & out_wimask_489; // @[RegisterRouter.scala:87:24]
wire out_f_woready_489 = out_woready_1_343 & out_womask_489; // @[RegisterRouter.scala:87:24]
wire _out_T_5048 = ~out_rimask_489; // @[RegisterRouter.scala:87:24]
wire _out_T_5049 = ~out_wimask_489; // @[RegisterRouter.scala:87:24]
wire _out_T_5050 = ~out_romask_489; // @[RegisterRouter.scala:87:24]
wire _out_T_5051 = ~out_womask_489; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_412 = {hi_80, flags_0_go, _out_prepend_T_412}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_5052 = out_prepend_412; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_5053 = _out_T_5052; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_137 = _out_T_5053; // @[MuxLiteral.scala:49:48]
wire out_rimask_490 = |_out_rimask_T_490; // @[RegisterRouter.scala:87:24]
wire out_wimask_490 = &_out_wimask_T_490; // @[RegisterRouter.scala:87:24]
wire out_romask_490 = |_out_romask_T_490; // @[RegisterRouter.scala:87:24]
wire out_womask_490 = &_out_womask_T_490; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_490 = out_rivalid_1_344 & out_rimask_490; // @[RegisterRouter.scala:87:24]
wire _out_T_5055 = out_f_rivalid_490; // @[RegisterRouter.scala:87:24]
wire out_f_roready_490 = out_roready_1_344 & out_romask_490; // @[RegisterRouter.scala:87:24]
wire _out_T_5056 = out_f_roready_490; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_490 = out_wivalid_1_344 & out_wimask_490; // @[RegisterRouter.scala:87:24]
wire out_f_woready_490 = out_woready_1_344 & out_womask_490; // @[RegisterRouter.scala:87:24]
wire _out_T_5057 = ~out_rimask_490; // @[RegisterRouter.scala:87:24]
wire _out_T_5058 = ~out_wimask_490; // @[RegisterRouter.scala:87:24]
wire _out_T_5059 = ~out_romask_490; // @[RegisterRouter.scala:87:24]
wire _out_T_5060 = ~out_womask_490; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5062 = _out_T_5061; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_413 = _out_T_5062; // @[RegisterRouter.scala:87:24]
wire out_rimask_491 = |_out_rimask_T_491; // @[RegisterRouter.scala:87:24]
wire out_wimask_491 = &_out_wimask_T_491; // @[RegisterRouter.scala:87:24]
wire out_romask_491 = |_out_romask_T_491; // @[RegisterRouter.scala:87:24]
wire out_womask_491 = &_out_womask_T_491; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_491 = out_rivalid_1_345 & out_rimask_491; // @[RegisterRouter.scala:87:24]
wire _out_T_5064 = out_f_rivalid_491; // @[RegisterRouter.scala:87:24]
wire out_f_roready_491 = out_roready_1_345 & out_romask_491; // @[RegisterRouter.scala:87:24]
wire _out_T_5065 = out_f_roready_491; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_491 = out_wivalid_1_345 & out_wimask_491; // @[RegisterRouter.scala:87:24]
wire out_f_woready_491 = out_woready_1_345 & out_womask_491; // @[RegisterRouter.scala:87:24]
wire _out_T_5066 = ~out_rimask_491; // @[RegisterRouter.scala:87:24]
wire _out_T_5067 = ~out_wimask_491; // @[RegisterRouter.scala:87:24]
wire _out_T_5068 = ~out_romask_491; // @[RegisterRouter.scala:87:24]
wire _out_T_5069 = ~out_womask_491; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_413 = {hi_298, flags_0_go, _out_prepend_T_413}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_5070 = out_prepend_413; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_5071 = _out_T_5070; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_414 = _out_T_5071; // @[RegisterRouter.scala:87:24]
wire out_rimask_492 = |_out_rimask_T_492; // @[RegisterRouter.scala:87:24]
wire out_wimask_492 = &_out_wimask_T_492; // @[RegisterRouter.scala:87:24]
wire out_romask_492 = |_out_romask_T_492; // @[RegisterRouter.scala:87:24]
wire out_womask_492 = &_out_womask_T_492; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_492 = out_rivalid_1_346 & out_rimask_492; // @[RegisterRouter.scala:87:24]
wire _out_T_5073 = out_f_rivalid_492; // @[RegisterRouter.scala:87:24]
wire out_f_roready_492 = out_roready_1_346 & out_romask_492; // @[RegisterRouter.scala:87:24]
wire _out_T_5074 = out_f_roready_492; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_492 = out_wivalid_1_346 & out_wimask_492; // @[RegisterRouter.scala:87:24]
wire out_f_woready_492 = out_woready_1_346 & out_womask_492; // @[RegisterRouter.scala:87:24]
wire _out_T_5075 = ~out_rimask_492; // @[RegisterRouter.scala:87:24]
wire _out_T_5076 = ~out_wimask_492; // @[RegisterRouter.scala:87:24]
wire _out_T_5077 = ~out_romask_492; // @[RegisterRouter.scala:87:24]
wire _out_T_5078 = ~out_womask_492; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_414 = {hi_299, flags_0_go, _out_prepend_T_414}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_5079 = out_prepend_414; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_5080 = _out_T_5079; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_415 = _out_T_5080; // @[RegisterRouter.scala:87:24]
wire out_rimask_493 = |_out_rimask_T_493; // @[RegisterRouter.scala:87:24]
wire out_wimask_493 = &_out_wimask_T_493; // @[RegisterRouter.scala:87:24]
wire out_romask_493 = |_out_romask_T_493; // @[RegisterRouter.scala:87:24]
wire out_womask_493 = &_out_womask_T_493; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_493 = out_rivalid_1_347 & out_rimask_493; // @[RegisterRouter.scala:87:24]
wire _out_T_5082 = out_f_rivalid_493; // @[RegisterRouter.scala:87:24]
wire out_f_roready_493 = out_roready_1_347 & out_romask_493; // @[RegisterRouter.scala:87:24]
wire _out_T_5083 = out_f_roready_493; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_493 = out_wivalid_1_347 & out_wimask_493; // @[RegisterRouter.scala:87:24]
wire out_f_woready_493 = out_woready_1_347 & out_womask_493; // @[RegisterRouter.scala:87:24]
wire _out_T_5084 = ~out_rimask_493; // @[RegisterRouter.scala:87:24]
wire _out_T_5085 = ~out_wimask_493; // @[RegisterRouter.scala:87:24]
wire _out_T_5086 = ~out_romask_493; // @[RegisterRouter.scala:87:24]
wire _out_T_5087 = ~out_womask_493; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_415 = {hi_300, flags_0_go, _out_prepend_T_415}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_5088 = out_prepend_415; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_5089 = _out_T_5088; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_416 = _out_T_5089; // @[RegisterRouter.scala:87:24]
wire out_rimask_494 = |_out_rimask_T_494; // @[RegisterRouter.scala:87:24]
wire out_wimask_494 = &_out_wimask_T_494; // @[RegisterRouter.scala:87:24]
wire out_romask_494 = |_out_romask_T_494; // @[RegisterRouter.scala:87:24]
wire out_womask_494 = &_out_womask_T_494; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_494 = out_rivalid_1_348 & out_rimask_494; // @[RegisterRouter.scala:87:24]
wire _out_T_5091 = out_f_rivalid_494; // @[RegisterRouter.scala:87:24]
wire out_f_roready_494 = out_roready_1_348 & out_romask_494; // @[RegisterRouter.scala:87:24]
wire _out_T_5092 = out_f_roready_494; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_494 = out_wivalid_1_348 & out_wimask_494; // @[RegisterRouter.scala:87:24]
wire out_f_woready_494 = out_woready_1_348 & out_womask_494; // @[RegisterRouter.scala:87:24]
wire _out_T_5093 = ~out_rimask_494; // @[RegisterRouter.scala:87:24]
wire _out_T_5094 = ~out_wimask_494; // @[RegisterRouter.scala:87:24]
wire _out_T_5095 = ~out_romask_494; // @[RegisterRouter.scala:87:24]
wire _out_T_5096 = ~out_womask_494; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_416 = {hi_301, flags_0_go, _out_prepend_T_416}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_5097 = out_prepend_416; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_5098 = _out_T_5097; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_417 = _out_T_5098; // @[RegisterRouter.scala:87:24]
wire out_rimask_495 = |_out_rimask_T_495; // @[RegisterRouter.scala:87:24]
wire out_wimask_495 = &_out_wimask_T_495; // @[RegisterRouter.scala:87:24]
wire out_romask_495 = |_out_romask_T_495; // @[RegisterRouter.scala:87:24]
wire out_womask_495 = &_out_womask_T_495; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_495 = out_rivalid_1_349 & out_rimask_495; // @[RegisterRouter.scala:87:24]
wire _out_T_5100 = out_f_rivalid_495; // @[RegisterRouter.scala:87:24]
wire out_f_roready_495 = out_roready_1_349 & out_romask_495; // @[RegisterRouter.scala:87:24]
wire _out_T_5101 = out_f_roready_495; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_495 = out_wivalid_1_349 & out_wimask_495; // @[RegisterRouter.scala:87:24]
wire out_f_woready_495 = out_woready_1_349 & out_womask_495; // @[RegisterRouter.scala:87:24]
wire _out_T_5102 = ~out_rimask_495; // @[RegisterRouter.scala:87:24]
wire _out_T_5103 = ~out_wimask_495; // @[RegisterRouter.scala:87:24]
wire _out_T_5104 = ~out_romask_495; // @[RegisterRouter.scala:87:24]
wire _out_T_5105 = ~out_womask_495; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_417 = {hi_302, flags_0_go, _out_prepend_T_417}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_5106 = out_prepend_417; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_5107 = _out_T_5106; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_418 = _out_T_5107; // @[RegisterRouter.scala:87:24]
wire out_rimask_496 = |_out_rimask_T_496; // @[RegisterRouter.scala:87:24]
wire out_wimask_496 = &_out_wimask_T_496; // @[RegisterRouter.scala:87:24]
wire out_romask_496 = |_out_romask_T_496; // @[RegisterRouter.scala:87:24]
wire out_womask_496 = &_out_womask_T_496; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_496 = out_rivalid_1_350 & out_rimask_496; // @[RegisterRouter.scala:87:24]
wire _out_T_5109 = out_f_rivalid_496; // @[RegisterRouter.scala:87:24]
wire out_f_roready_496 = out_roready_1_350 & out_romask_496; // @[RegisterRouter.scala:87:24]
wire _out_T_5110 = out_f_roready_496; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_496 = out_wivalid_1_350 & out_wimask_496; // @[RegisterRouter.scala:87:24]
wire out_f_woready_496 = out_woready_1_350 & out_womask_496; // @[RegisterRouter.scala:87:24]
wire _out_T_5111 = ~out_rimask_496; // @[RegisterRouter.scala:87:24]
wire _out_T_5112 = ~out_wimask_496; // @[RegisterRouter.scala:87:24]
wire _out_T_5113 = ~out_romask_496; // @[RegisterRouter.scala:87:24]
wire _out_T_5114 = ~out_womask_496; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_418 = {hi_303, flags_0_go, _out_prepend_T_418}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_5115 = out_prepend_418; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_5116 = _out_T_5115; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_419 = _out_T_5116; // @[RegisterRouter.scala:87:24]
wire out_rimask_497 = |_out_rimask_T_497; // @[RegisterRouter.scala:87:24]
wire out_wimask_497 = &_out_wimask_T_497; // @[RegisterRouter.scala:87:24]
wire out_romask_497 = |_out_romask_T_497; // @[RegisterRouter.scala:87:24]
wire out_womask_497 = &_out_womask_T_497; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_497 = out_rivalid_1_351 & out_rimask_497; // @[RegisterRouter.scala:87:24]
wire _out_T_5118 = out_f_rivalid_497; // @[RegisterRouter.scala:87:24]
wire out_f_roready_497 = out_roready_1_351 & out_romask_497; // @[RegisterRouter.scala:87:24]
wire _out_T_5119 = out_f_roready_497; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_497 = out_wivalid_1_351 & out_wimask_497; // @[RegisterRouter.scala:87:24]
wire out_f_woready_497 = out_woready_1_351 & out_womask_497; // @[RegisterRouter.scala:87:24]
wire _out_T_5120 = ~out_rimask_497; // @[RegisterRouter.scala:87:24]
wire _out_T_5121 = ~out_wimask_497; // @[RegisterRouter.scala:87:24]
wire _out_T_5122 = ~out_romask_497; // @[RegisterRouter.scala:87:24]
wire _out_T_5123 = ~out_womask_497; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_419 = {hi_304, flags_0_go, _out_prepend_T_419}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_5124 = out_prepend_419; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_5125 = _out_T_5124; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_165 = _out_T_5125; // @[MuxLiteral.scala:49:48]
wire [9:0] _out_rimask_T_498 = out_frontMask_1[9:0]; // @[RegisterRouter.scala:87:24]
wire [9:0] _out_wimask_T_498 = out_frontMask_1[9:0]; // @[RegisterRouter.scala:87:24]
wire [9:0] _out_rimask_T_681 = out_frontMask_1[9:0]; // @[RegisterRouter.scala:87:24]
wire [9:0] _out_wimask_T_681 = out_frontMask_1[9:0]; // @[RegisterRouter.scala:87:24]
wire out_rimask_498 = |_out_rimask_T_498; // @[RegisterRouter.scala:87:24]
wire out_wimask_498 = &_out_wimask_T_498; // @[RegisterRouter.scala:87:24]
wire [9:0] _out_romask_T_498 = out_backMask_1[9:0]; // @[RegisterRouter.scala:87:24]
wire [9:0] _out_womask_T_498 = out_backMask_1[9:0]; // @[RegisterRouter.scala:87:24]
wire [9:0] _out_romask_T_681 = out_backMask_1[9:0]; // @[RegisterRouter.scala:87:24]
wire [9:0] _out_womask_T_681 = out_backMask_1[9:0]; // @[RegisterRouter.scala:87:24]
wire out_romask_498 = |_out_romask_T_498; // @[RegisterRouter.scala:87:24]
wire out_womask_498 = &_out_womask_T_498; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_498 = out_rivalid_1_352 & out_rimask_498; // @[RegisterRouter.scala:87:24]
wire out_f_roready_498 = out_roready_1_352 & out_romask_498; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_498 = out_wivalid_1_352 & out_wimask_498; // @[RegisterRouter.scala:87:24]
wire _out_T_5127 = out_f_wivalid_498; // @[RegisterRouter.scala:87:24]
assign out_f_woready_498 = out_woready_1_352 & out_womask_498; // @[RegisterRouter.scala:87:24]
assign hartResumingWrEn = out_f_woready_498; // @[RegisterRouter.scala:87:24]
wire _out_T_5128 = out_f_woready_498; // @[RegisterRouter.scala:87:24]
assign _out_T_5126 = out_front_1_bits_data[9:0]; // @[RegisterRouter.scala:87:24]
assign _out_T_6805 = out_front_1_bits_data[9:0]; // @[RegisterRouter.scala:87:24]
assign hartResumingId = _out_T_5126; // @[RegisterRouter.scala:87:24]
wire _out_T_5129 = ~out_rimask_498; // @[RegisterRouter.scala:87:24]
wire _out_T_5130 = ~out_wimask_498; // @[RegisterRouter.scala:87:24]
wire _out_T_5131 = ~out_romask_498; // @[RegisterRouter.scala:87:24]
wire _out_T_5132 = ~out_womask_498; // @[RegisterRouter.scala:87:24]
wire [9:0] _out_rimask_T_499 = out_frontMask_1[41:32]; // @[RegisterRouter.scala:87:24]
wire [9:0] _out_wimask_T_499 = out_frontMask_1[41:32]; // @[RegisterRouter.scala:87:24]
wire [9:0] _out_rimask_T_682 = out_frontMask_1[41:32]; // @[RegisterRouter.scala:87:24]
wire [9:0] _out_wimask_T_682 = out_frontMask_1[41:32]; // @[RegisterRouter.scala:87:24]
wire out_rimask_499 = |_out_rimask_T_499; // @[RegisterRouter.scala:87:24]
wire out_wimask_499 = &_out_wimask_T_499; // @[RegisterRouter.scala:87:24]
wire [9:0] _out_romask_T_499 = out_backMask_1[41:32]; // @[RegisterRouter.scala:87:24]
wire [9:0] _out_womask_T_499 = out_backMask_1[41:32]; // @[RegisterRouter.scala:87:24]
wire [9:0] _out_romask_T_682 = out_backMask_1[41:32]; // @[RegisterRouter.scala:87:24]
wire [9:0] _out_womask_T_682 = out_backMask_1[41:32]; // @[RegisterRouter.scala:87:24]
wire out_romask_499 = |_out_romask_T_499; // @[RegisterRouter.scala:87:24]
wire out_womask_499 = &_out_womask_T_499; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_499 = out_rivalid_1_353 & out_rimask_499; // @[RegisterRouter.scala:87:24]
wire out_f_roready_499 = out_roready_1_353 & out_romask_499; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_499 = out_wivalid_1_353 & out_wimask_499; // @[RegisterRouter.scala:87:24]
wire _out_T_5136 = out_f_wivalid_499; // @[RegisterRouter.scala:87:24]
assign out_f_woready_499 = out_woready_1_353 & out_womask_499; // @[RegisterRouter.scala:87:24]
assign hartExceptionWrEn = out_f_woready_499; // @[RegisterRouter.scala:87:24]
wire _out_T_5137 = out_f_woready_499; // @[RegisterRouter.scala:87:24]
assign _out_T_5135 = out_front_1_bits_data[41:32]; // @[RegisterRouter.scala:87:24]
assign _out_T_6814 = out_front_1_bits_data[41:32]; // @[RegisterRouter.scala:87:24]
assign hartExceptionId = _out_T_5135; // @[RegisterRouter.scala:87:24]
wire _out_T_5138 = ~out_rimask_499; // @[RegisterRouter.scala:87:24]
wire _out_T_5139 = ~out_wimask_499; // @[RegisterRouter.scala:87:24]
wire _out_T_5140 = ~out_romask_499; // @[RegisterRouter.scala:87:24]
wire _out_T_5141 = ~out_womask_499; // @[RegisterRouter.scala:87:24]
wire out_rimask_500 = |_out_rimask_T_500; // @[RegisterRouter.scala:87:24]
wire out_wimask_500 = &_out_wimask_T_500; // @[RegisterRouter.scala:87:24]
wire out_romask_500 = |_out_romask_T_500; // @[RegisterRouter.scala:87:24]
wire out_womask_500 = &_out_womask_T_500; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_500 = out_rivalid_1_354 & out_rimask_500; // @[RegisterRouter.scala:87:24]
wire _out_T_5145 = out_f_rivalid_500; // @[RegisterRouter.scala:87:24]
wire out_f_roready_500 = out_roready_1_354 & out_romask_500; // @[RegisterRouter.scala:87:24]
wire _out_T_5146 = out_f_roready_500; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_500 = out_wivalid_1_354 & out_wimask_500; // @[RegisterRouter.scala:87:24]
wire out_f_woready_500 = out_woready_1_354 & out_womask_500; // @[RegisterRouter.scala:87:24]
wire _out_T_5147 = ~out_rimask_500; // @[RegisterRouter.scala:87:24]
wire _out_T_5148 = ~out_wimask_500; // @[RegisterRouter.scala:87:24]
wire _out_T_5149 = ~out_romask_500; // @[RegisterRouter.scala:87:24]
wire _out_T_5150 = ~out_womask_500; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5152 = _out_T_5151; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_421 = _out_T_5152; // @[RegisterRouter.scala:87:24]
wire out_rimask_501 = |_out_rimask_T_501; // @[RegisterRouter.scala:87:24]
wire out_wimask_501 = &_out_wimask_T_501; // @[RegisterRouter.scala:87:24]
wire out_romask_501 = |_out_romask_T_501; // @[RegisterRouter.scala:87:24]
wire out_womask_501 = &_out_womask_T_501; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_501 = out_rivalid_1_355 & out_rimask_501; // @[RegisterRouter.scala:87:24]
wire _out_T_5154 = out_f_rivalid_501; // @[RegisterRouter.scala:87:24]
wire out_f_roready_501 = out_roready_1_355 & out_romask_501; // @[RegisterRouter.scala:87:24]
wire _out_T_5155 = out_f_roready_501; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_501 = out_wivalid_1_355 & out_wimask_501; // @[RegisterRouter.scala:87:24]
wire out_f_woready_501 = out_woready_1_355 & out_womask_501; // @[RegisterRouter.scala:87:24]
wire _out_T_5156 = ~out_rimask_501; // @[RegisterRouter.scala:87:24]
wire _out_T_5157 = ~out_wimask_501; // @[RegisterRouter.scala:87:24]
wire _out_T_5158 = ~out_romask_501; // @[RegisterRouter.scala:87:24]
wire _out_T_5159 = ~out_womask_501; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_421 = {hi_810, flags_0_go, _out_prepend_T_421}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_5160 = out_prepend_421; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_5161 = _out_T_5160; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_422 = _out_T_5161; // @[RegisterRouter.scala:87:24]
wire out_rimask_502 = |_out_rimask_T_502; // @[RegisterRouter.scala:87:24]
wire out_wimask_502 = &_out_wimask_T_502; // @[RegisterRouter.scala:87:24]
wire out_romask_502 = |_out_romask_T_502; // @[RegisterRouter.scala:87:24]
wire out_womask_502 = &_out_womask_T_502; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_502 = out_rivalid_1_356 & out_rimask_502; // @[RegisterRouter.scala:87:24]
wire _out_T_5163 = out_f_rivalid_502; // @[RegisterRouter.scala:87:24]
wire out_f_roready_502 = out_roready_1_356 & out_romask_502; // @[RegisterRouter.scala:87:24]
wire _out_T_5164 = out_f_roready_502; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_502 = out_wivalid_1_356 & out_wimask_502; // @[RegisterRouter.scala:87:24]
wire out_f_woready_502 = out_woready_1_356 & out_womask_502; // @[RegisterRouter.scala:87:24]
wire _out_T_5165 = ~out_rimask_502; // @[RegisterRouter.scala:87:24]
wire _out_T_5166 = ~out_wimask_502; // @[RegisterRouter.scala:87:24]
wire _out_T_5167 = ~out_romask_502; // @[RegisterRouter.scala:87:24]
wire _out_T_5168 = ~out_womask_502; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_422 = {hi_811, flags_0_go, _out_prepend_T_422}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_5169 = out_prepend_422; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_5170 = _out_T_5169; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_423 = _out_T_5170; // @[RegisterRouter.scala:87:24]
wire out_rimask_503 = |_out_rimask_T_503; // @[RegisterRouter.scala:87:24]
wire out_wimask_503 = &_out_wimask_T_503; // @[RegisterRouter.scala:87:24]
wire out_romask_503 = |_out_romask_T_503; // @[RegisterRouter.scala:87:24]
wire out_womask_503 = &_out_womask_T_503; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_503 = out_rivalid_1_357 & out_rimask_503; // @[RegisterRouter.scala:87:24]
wire _out_T_5172 = out_f_rivalid_503; // @[RegisterRouter.scala:87:24]
wire out_f_roready_503 = out_roready_1_357 & out_romask_503; // @[RegisterRouter.scala:87:24]
wire _out_T_5173 = out_f_roready_503; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_503 = out_wivalid_1_357 & out_wimask_503; // @[RegisterRouter.scala:87:24]
wire out_f_woready_503 = out_woready_1_357 & out_womask_503; // @[RegisterRouter.scala:87:24]
wire _out_T_5174 = ~out_rimask_503; // @[RegisterRouter.scala:87:24]
wire _out_T_5175 = ~out_wimask_503; // @[RegisterRouter.scala:87:24]
wire _out_T_5176 = ~out_romask_503; // @[RegisterRouter.scala:87:24]
wire _out_T_5177 = ~out_womask_503; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_423 = {hi_812, flags_0_go, _out_prepend_T_423}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_5178 = out_prepend_423; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_5179 = _out_T_5178; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_424 = _out_T_5179; // @[RegisterRouter.scala:87:24]
wire out_rimask_504 = |_out_rimask_T_504; // @[RegisterRouter.scala:87:24]
wire out_wimask_504 = &_out_wimask_T_504; // @[RegisterRouter.scala:87:24]
wire out_romask_504 = |_out_romask_T_504; // @[RegisterRouter.scala:87:24]
wire out_womask_504 = &_out_womask_T_504; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_504 = out_rivalid_1_358 & out_rimask_504; // @[RegisterRouter.scala:87:24]
wire _out_T_5181 = out_f_rivalid_504; // @[RegisterRouter.scala:87:24]
wire out_f_roready_504 = out_roready_1_358 & out_romask_504; // @[RegisterRouter.scala:87:24]
wire _out_T_5182 = out_f_roready_504; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_504 = out_wivalid_1_358 & out_wimask_504; // @[RegisterRouter.scala:87:24]
wire out_f_woready_504 = out_woready_1_358 & out_womask_504; // @[RegisterRouter.scala:87:24]
wire _out_T_5183 = ~out_rimask_504; // @[RegisterRouter.scala:87:24]
wire _out_T_5184 = ~out_wimask_504; // @[RegisterRouter.scala:87:24]
wire _out_T_5185 = ~out_romask_504; // @[RegisterRouter.scala:87:24]
wire _out_T_5186 = ~out_womask_504; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_424 = {hi_813, flags_0_go, _out_prepend_T_424}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_5187 = out_prepend_424; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_5188 = _out_T_5187; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_425 = _out_T_5188; // @[RegisterRouter.scala:87:24]
wire out_rimask_505 = |_out_rimask_T_505; // @[RegisterRouter.scala:87:24]
wire out_wimask_505 = &_out_wimask_T_505; // @[RegisterRouter.scala:87:24]
wire out_romask_505 = |_out_romask_T_505; // @[RegisterRouter.scala:87:24]
wire out_womask_505 = &_out_womask_T_505; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_505 = out_rivalid_1_359 & out_rimask_505; // @[RegisterRouter.scala:87:24]
wire _out_T_5190 = out_f_rivalid_505; // @[RegisterRouter.scala:87:24]
wire out_f_roready_505 = out_roready_1_359 & out_romask_505; // @[RegisterRouter.scala:87:24]
wire _out_T_5191 = out_f_roready_505; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_505 = out_wivalid_1_359 & out_wimask_505; // @[RegisterRouter.scala:87:24]
wire out_f_woready_505 = out_woready_1_359 & out_womask_505; // @[RegisterRouter.scala:87:24]
wire _out_T_5192 = ~out_rimask_505; // @[RegisterRouter.scala:87:24]
wire _out_T_5193 = ~out_wimask_505; // @[RegisterRouter.scala:87:24]
wire _out_T_5194 = ~out_romask_505; // @[RegisterRouter.scala:87:24]
wire _out_T_5195 = ~out_womask_505; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_425 = {hi_814, flags_0_go, _out_prepend_T_425}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_5196 = out_prepend_425; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_5197 = _out_T_5196; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_426 = _out_T_5197; // @[RegisterRouter.scala:87:24]
wire out_rimask_506 = |_out_rimask_T_506; // @[RegisterRouter.scala:87:24]
wire out_wimask_506 = &_out_wimask_T_506; // @[RegisterRouter.scala:87:24]
wire out_romask_506 = |_out_romask_T_506; // @[RegisterRouter.scala:87:24]
wire out_womask_506 = &_out_womask_T_506; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_506 = out_rivalid_1_360 & out_rimask_506; // @[RegisterRouter.scala:87:24]
wire _out_T_5199 = out_f_rivalid_506; // @[RegisterRouter.scala:87:24]
wire out_f_roready_506 = out_roready_1_360 & out_romask_506; // @[RegisterRouter.scala:87:24]
wire _out_T_5200 = out_f_roready_506; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_506 = out_wivalid_1_360 & out_wimask_506; // @[RegisterRouter.scala:87:24]
wire out_f_woready_506 = out_woready_1_360 & out_womask_506; // @[RegisterRouter.scala:87:24]
wire _out_T_5201 = ~out_rimask_506; // @[RegisterRouter.scala:87:24]
wire _out_T_5202 = ~out_wimask_506; // @[RegisterRouter.scala:87:24]
wire _out_T_5203 = ~out_romask_506; // @[RegisterRouter.scala:87:24]
wire _out_T_5204 = ~out_womask_506; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_426 = {hi_815, flags_0_go, _out_prepend_T_426}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_5205 = out_prepend_426; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_5206 = _out_T_5205; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_427 = _out_T_5206; // @[RegisterRouter.scala:87:24]
wire out_rimask_507 = |_out_rimask_T_507; // @[RegisterRouter.scala:87:24]
wire out_wimask_507 = &_out_wimask_T_507; // @[RegisterRouter.scala:87:24]
wire out_romask_507 = |_out_romask_T_507; // @[RegisterRouter.scala:87:24]
wire out_womask_507 = &_out_womask_T_507; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_507 = out_rivalid_1_361 & out_rimask_507; // @[RegisterRouter.scala:87:24]
wire _out_T_5208 = out_f_rivalid_507; // @[RegisterRouter.scala:87:24]
wire out_f_roready_507 = out_roready_1_361 & out_romask_507; // @[RegisterRouter.scala:87:24]
wire _out_T_5209 = out_f_roready_507; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_507 = out_wivalid_1_361 & out_wimask_507; // @[RegisterRouter.scala:87:24]
wire out_f_woready_507 = out_woready_1_361 & out_womask_507; // @[RegisterRouter.scala:87:24]
wire _out_T_5210 = ~out_rimask_507; // @[RegisterRouter.scala:87:24]
wire _out_T_5211 = ~out_wimask_507; // @[RegisterRouter.scala:87:24]
wire _out_T_5212 = ~out_romask_507; // @[RegisterRouter.scala:87:24]
wire _out_T_5213 = ~out_womask_507; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_427 = {hi_816, flags_0_go, _out_prepend_T_427}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_5214 = out_prepend_427; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_5215 = _out_T_5214; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_229 = _out_T_5215; // @[MuxLiteral.scala:49:48]
wire out_rimask_508 = |_out_rimask_T_508; // @[RegisterRouter.scala:87:24]
wire out_wimask_508 = &_out_wimask_T_508; // @[RegisterRouter.scala:87:24]
wire out_romask_508 = |_out_romask_T_508; // @[RegisterRouter.scala:87:24]
wire out_womask_508 = &_out_womask_T_508; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_508 = out_rivalid_1_362 & out_rimask_508; // @[RegisterRouter.scala:87:24]
wire _out_T_5217 = out_f_rivalid_508; // @[RegisterRouter.scala:87:24]
wire out_f_roready_508 = out_roready_1_362 & out_romask_508; // @[RegisterRouter.scala:87:24]
wire _out_T_5218 = out_f_roready_508; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_508 = out_wivalid_1_362 & out_wimask_508; // @[RegisterRouter.scala:87:24]
wire out_f_woready_508 = out_woready_1_362 & out_womask_508; // @[RegisterRouter.scala:87:24]
wire _out_T_5219 = ~out_rimask_508; // @[RegisterRouter.scala:87:24]
wire _out_T_5220 = ~out_wimask_508; // @[RegisterRouter.scala:87:24]
wire _out_T_5221 = ~out_romask_508; // @[RegisterRouter.scala:87:24]
wire _out_T_5222 = ~out_womask_508; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5224 = _out_T_5223; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_428 = _out_T_5224; // @[RegisterRouter.scala:87:24]
wire out_rimask_509 = |_out_rimask_T_509; // @[RegisterRouter.scala:87:24]
wire out_wimask_509 = &_out_wimask_T_509; // @[RegisterRouter.scala:87:24]
wire out_romask_509 = |_out_romask_T_509; // @[RegisterRouter.scala:87:24]
wire out_womask_509 = &_out_womask_T_509; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_509 = out_rivalid_1_363 & out_rimask_509; // @[RegisterRouter.scala:87:24]
wire _out_T_5226 = out_f_rivalid_509; // @[RegisterRouter.scala:87:24]
wire out_f_roready_509 = out_roready_1_363 & out_romask_509; // @[RegisterRouter.scala:87:24]
wire _out_T_5227 = out_f_roready_509; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_509 = out_wivalid_1_363 & out_wimask_509; // @[RegisterRouter.scala:87:24]
wire out_f_woready_509 = out_woready_1_363 & out_womask_509; // @[RegisterRouter.scala:87:24]
wire _out_T_5228 = ~out_rimask_509; // @[RegisterRouter.scala:87:24]
wire _out_T_5229 = ~out_wimask_509; // @[RegisterRouter.scala:87:24]
wire _out_T_5230 = ~out_romask_509; // @[RegisterRouter.scala:87:24]
wire _out_T_5231 = ~out_womask_509; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_428 = {hi_994, flags_0_go, _out_prepend_T_428}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_5232 = out_prepend_428; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_5233 = _out_T_5232; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_429 = _out_T_5233; // @[RegisterRouter.scala:87:24]
wire out_rimask_510 = |_out_rimask_T_510; // @[RegisterRouter.scala:87:24]
wire out_wimask_510 = &_out_wimask_T_510; // @[RegisterRouter.scala:87:24]
wire out_romask_510 = |_out_romask_T_510; // @[RegisterRouter.scala:87:24]
wire out_womask_510 = &_out_womask_T_510; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_510 = out_rivalid_1_364 & out_rimask_510; // @[RegisterRouter.scala:87:24]
wire _out_T_5235 = out_f_rivalid_510; // @[RegisterRouter.scala:87:24]
wire out_f_roready_510 = out_roready_1_364 & out_romask_510; // @[RegisterRouter.scala:87:24]
wire _out_T_5236 = out_f_roready_510; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_510 = out_wivalid_1_364 & out_wimask_510; // @[RegisterRouter.scala:87:24]
wire out_f_woready_510 = out_woready_1_364 & out_womask_510; // @[RegisterRouter.scala:87:24]
wire _out_T_5237 = ~out_rimask_510; // @[RegisterRouter.scala:87:24]
wire _out_T_5238 = ~out_wimask_510; // @[RegisterRouter.scala:87:24]
wire _out_T_5239 = ~out_romask_510; // @[RegisterRouter.scala:87:24]
wire _out_T_5240 = ~out_womask_510; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_429 = {hi_995, flags_0_go, _out_prepend_T_429}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_5241 = out_prepend_429; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_5242 = _out_T_5241; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_430 = _out_T_5242; // @[RegisterRouter.scala:87:24]
wire out_rimask_511 = |_out_rimask_T_511; // @[RegisterRouter.scala:87:24]
wire out_wimask_511 = &_out_wimask_T_511; // @[RegisterRouter.scala:87:24]
wire out_romask_511 = |_out_romask_T_511; // @[RegisterRouter.scala:87:24]
wire out_womask_511 = &_out_womask_T_511; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_511 = out_rivalid_1_365 & out_rimask_511; // @[RegisterRouter.scala:87:24]
wire _out_T_5244 = out_f_rivalid_511; // @[RegisterRouter.scala:87:24]
wire out_f_roready_511 = out_roready_1_365 & out_romask_511; // @[RegisterRouter.scala:87:24]
wire _out_T_5245 = out_f_roready_511; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_511 = out_wivalid_1_365 & out_wimask_511; // @[RegisterRouter.scala:87:24]
wire out_f_woready_511 = out_woready_1_365 & out_womask_511; // @[RegisterRouter.scala:87:24]
wire _out_T_5246 = ~out_rimask_511; // @[RegisterRouter.scala:87:24]
wire _out_T_5247 = ~out_wimask_511; // @[RegisterRouter.scala:87:24]
wire _out_T_5248 = ~out_romask_511; // @[RegisterRouter.scala:87:24]
wire _out_T_5249 = ~out_womask_511; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_430 = {hi_996, flags_0_go, _out_prepend_T_430}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_5250 = out_prepend_430; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_5251 = _out_T_5250; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_431 = _out_T_5251; // @[RegisterRouter.scala:87:24]
wire out_rimask_512 = |_out_rimask_T_512; // @[RegisterRouter.scala:87:24]
wire out_wimask_512 = &_out_wimask_T_512; // @[RegisterRouter.scala:87:24]
wire out_romask_512 = |_out_romask_T_512; // @[RegisterRouter.scala:87:24]
wire out_womask_512 = &_out_womask_T_512; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_512 = out_rivalid_1_366 & out_rimask_512; // @[RegisterRouter.scala:87:24]
wire _out_T_5253 = out_f_rivalid_512; // @[RegisterRouter.scala:87:24]
wire out_f_roready_512 = out_roready_1_366 & out_romask_512; // @[RegisterRouter.scala:87:24]
wire _out_T_5254 = out_f_roready_512; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_512 = out_wivalid_1_366 & out_wimask_512; // @[RegisterRouter.scala:87:24]
wire out_f_woready_512 = out_woready_1_366 & out_womask_512; // @[RegisterRouter.scala:87:24]
wire _out_T_5255 = ~out_rimask_512; // @[RegisterRouter.scala:87:24]
wire _out_T_5256 = ~out_wimask_512; // @[RegisterRouter.scala:87:24]
wire _out_T_5257 = ~out_romask_512; // @[RegisterRouter.scala:87:24]
wire _out_T_5258 = ~out_womask_512; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_431 = {hi_997, flags_0_go, _out_prepend_T_431}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_5259 = out_prepend_431; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_5260 = _out_T_5259; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_432 = _out_T_5260; // @[RegisterRouter.scala:87:24]
wire out_rimask_513 = |_out_rimask_T_513; // @[RegisterRouter.scala:87:24]
wire out_wimask_513 = &_out_wimask_T_513; // @[RegisterRouter.scala:87:24]
wire out_romask_513 = |_out_romask_T_513; // @[RegisterRouter.scala:87:24]
wire out_womask_513 = &_out_womask_T_513; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_513 = out_rivalid_1_367 & out_rimask_513; // @[RegisterRouter.scala:87:24]
wire _out_T_5262 = out_f_rivalid_513; // @[RegisterRouter.scala:87:24]
wire out_f_roready_513 = out_roready_1_367 & out_romask_513; // @[RegisterRouter.scala:87:24]
wire _out_T_5263 = out_f_roready_513; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_513 = out_wivalid_1_367 & out_wimask_513; // @[RegisterRouter.scala:87:24]
wire out_f_woready_513 = out_woready_1_367 & out_womask_513; // @[RegisterRouter.scala:87:24]
wire _out_T_5264 = ~out_rimask_513; // @[RegisterRouter.scala:87:24]
wire _out_T_5265 = ~out_wimask_513; // @[RegisterRouter.scala:87:24]
wire _out_T_5266 = ~out_romask_513; // @[RegisterRouter.scala:87:24]
wire _out_T_5267 = ~out_womask_513; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_432 = {hi_998, flags_0_go, _out_prepend_T_432}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_5268 = out_prepend_432; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_5269 = _out_T_5268; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_433 = _out_T_5269; // @[RegisterRouter.scala:87:24]
wire out_rimask_514 = |_out_rimask_T_514; // @[RegisterRouter.scala:87:24]
wire out_wimask_514 = &_out_wimask_T_514; // @[RegisterRouter.scala:87:24]
wire out_romask_514 = |_out_romask_T_514; // @[RegisterRouter.scala:87:24]
wire out_womask_514 = &_out_womask_T_514; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_514 = out_rivalid_1_368 & out_rimask_514; // @[RegisterRouter.scala:87:24]
wire _out_T_5271 = out_f_rivalid_514; // @[RegisterRouter.scala:87:24]
wire out_f_roready_514 = out_roready_1_368 & out_romask_514; // @[RegisterRouter.scala:87:24]
wire _out_T_5272 = out_f_roready_514; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_514 = out_wivalid_1_368 & out_wimask_514; // @[RegisterRouter.scala:87:24]
wire out_f_woready_514 = out_woready_1_368 & out_womask_514; // @[RegisterRouter.scala:87:24]
wire _out_T_5273 = ~out_rimask_514; // @[RegisterRouter.scala:87:24]
wire _out_T_5274 = ~out_wimask_514; // @[RegisterRouter.scala:87:24]
wire _out_T_5275 = ~out_romask_514; // @[RegisterRouter.scala:87:24]
wire _out_T_5276 = ~out_womask_514; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_433 = {hi_999, flags_0_go, _out_prepend_T_433}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_5277 = out_prepend_433; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_5278 = _out_T_5277; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_434 = _out_T_5278; // @[RegisterRouter.scala:87:24]
wire out_rimask_515 = |_out_rimask_T_515; // @[RegisterRouter.scala:87:24]
wire out_wimask_515 = &_out_wimask_T_515; // @[RegisterRouter.scala:87:24]
wire out_romask_515 = |_out_romask_T_515; // @[RegisterRouter.scala:87:24]
wire out_womask_515 = &_out_womask_T_515; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_515 = out_rivalid_1_369 & out_rimask_515; // @[RegisterRouter.scala:87:24]
wire _out_T_5280 = out_f_rivalid_515; // @[RegisterRouter.scala:87:24]
wire out_f_roready_515 = out_roready_1_369 & out_romask_515; // @[RegisterRouter.scala:87:24]
wire _out_T_5281 = out_f_roready_515; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_515 = out_wivalid_1_369 & out_wimask_515; // @[RegisterRouter.scala:87:24]
wire out_f_woready_515 = out_woready_1_369 & out_womask_515; // @[RegisterRouter.scala:87:24]
wire _out_T_5282 = ~out_rimask_515; // @[RegisterRouter.scala:87:24]
wire _out_T_5283 = ~out_wimask_515; // @[RegisterRouter.scala:87:24]
wire _out_T_5284 = ~out_romask_515; // @[RegisterRouter.scala:87:24]
wire _out_T_5285 = ~out_womask_515; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_434 = {hi_1000, flags_0_go, _out_prepend_T_434}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_5286 = out_prepend_434; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_5287 = _out_T_5286; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_252 = _out_T_5287; // @[MuxLiteral.scala:49:48]
wire out_rimask_516 = |_out_rimask_T_516; // @[RegisterRouter.scala:87:24]
wire out_wimask_516 = &_out_wimask_T_516; // @[RegisterRouter.scala:87:24]
wire out_romask_516 = |_out_romask_T_516; // @[RegisterRouter.scala:87:24]
wire out_womask_516 = &_out_womask_T_516; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_516 = out_rivalid_1_370 & out_rimask_516; // @[RegisterRouter.scala:87:24]
wire _out_T_5289 = out_f_rivalid_516; // @[RegisterRouter.scala:87:24]
wire out_f_roready_516 = out_roready_1_370 & out_romask_516; // @[RegisterRouter.scala:87:24]
wire _out_T_5290 = out_f_roready_516; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_516 = out_wivalid_1_370 & out_wimask_516; // @[RegisterRouter.scala:87:24]
wire out_f_woready_516 = out_woready_1_370 & out_womask_516; // @[RegisterRouter.scala:87:24]
wire _out_T_5291 = ~out_rimask_516; // @[RegisterRouter.scala:87:24]
wire _out_T_5292 = ~out_wimask_516; // @[RegisterRouter.scala:87:24]
wire _out_T_5293 = ~out_romask_516; // @[RegisterRouter.scala:87:24]
wire _out_T_5294 = ~out_womask_516; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5296 = _out_T_5295; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_435 = _out_T_5296; // @[RegisterRouter.scala:87:24]
wire out_rimask_517 = |_out_rimask_T_517; // @[RegisterRouter.scala:87:24]
wire out_wimask_517 = &_out_wimask_T_517; // @[RegisterRouter.scala:87:24]
wire out_romask_517 = |_out_romask_T_517; // @[RegisterRouter.scala:87:24]
wire out_womask_517 = &_out_womask_T_517; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_517 = out_rivalid_1_371 & out_rimask_517; // @[RegisterRouter.scala:87:24]
wire _out_T_5298 = out_f_rivalid_517; // @[RegisterRouter.scala:87:24]
wire out_f_roready_517 = out_roready_1_371 & out_romask_517; // @[RegisterRouter.scala:87:24]
wire _out_T_5299 = out_f_roready_517; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_517 = out_wivalid_1_371 & out_wimask_517; // @[RegisterRouter.scala:87:24]
wire out_f_woready_517 = out_woready_1_371 & out_womask_517; // @[RegisterRouter.scala:87:24]
wire _out_T_5300 = ~out_rimask_517; // @[RegisterRouter.scala:87:24]
wire _out_T_5301 = ~out_wimask_517; // @[RegisterRouter.scala:87:24]
wire _out_T_5302 = ~out_romask_517; // @[RegisterRouter.scala:87:24]
wire _out_T_5303 = ~out_womask_517; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_435 = {hi_554, flags_0_go, _out_prepend_T_435}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_5304 = out_prepend_435; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_5305 = _out_T_5304; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_436 = _out_T_5305; // @[RegisterRouter.scala:87:24]
wire out_rimask_518 = |_out_rimask_T_518; // @[RegisterRouter.scala:87:24]
wire out_wimask_518 = &_out_wimask_T_518; // @[RegisterRouter.scala:87:24]
wire out_romask_518 = |_out_romask_T_518; // @[RegisterRouter.scala:87:24]
wire out_womask_518 = &_out_womask_T_518; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_518 = out_rivalid_1_372 & out_rimask_518; // @[RegisterRouter.scala:87:24]
wire _out_T_5307 = out_f_rivalid_518; // @[RegisterRouter.scala:87:24]
wire out_f_roready_518 = out_roready_1_372 & out_romask_518; // @[RegisterRouter.scala:87:24]
wire _out_T_5308 = out_f_roready_518; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_518 = out_wivalid_1_372 & out_wimask_518; // @[RegisterRouter.scala:87:24]
wire out_f_woready_518 = out_woready_1_372 & out_womask_518; // @[RegisterRouter.scala:87:24]
wire _out_T_5309 = ~out_rimask_518; // @[RegisterRouter.scala:87:24]
wire _out_T_5310 = ~out_wimask_518; // @[RegisterRouter.scala:87:24]
wire _out_T_5311 = ~out_romask_518; // @[RegisterRouter.scala:87:24]
wire _out_T_5312 = ~out_womask_518; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_436 = {hi_555, flags_0_go, _out_prepend_T_436}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_5313 = out_prepend_436; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_5314 = _out_T_5313; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_437 = _out_T_5314; // @[RegisterRouter.scala:87:24]
wire out_rimask_519 = |_out_rimask_T_519; // @[RegisterRouter.scala:87:24]
wire out_wimask_519 = &_out_wimask_T_519; // @[RegisterRouter.scala:87:24]
wire out_romask_519 = |_out_romask_T_519; // @[RegisterRouter.scala:87:24]
wire out_womask_519 = &_out_womask_T_519; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_519 = out_rivalid_1_373 & out_rimask_519; // @[RegisterRouter.scala:87:24]
wire _out_T_5316 = out_f_rivalid_519; // @[RegisterRouter.scala:87:24]
wire out_f_roready_519 = out_roready_1_373 & out_romask_519; // @[RegisterRouter.scala:87:24]
wire _out_T_5317 = out_f_roready_519; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_519 = out_wivalid_1_373 & out_wimask_519; // @[RegisterRouter.scala:87:24]
wire out_f_woready_519 = out_woready_1_373 & out_womask_519; // @[RegisterRouter.scala:87:24]
wire _out_T_5318 = ~out_rimask_519; // @[RegisterRouter.scala:87:24]
wire _out_T_5319 = ~out_wimask_519; // @[RegisterRouter.scala:87:24]
wire _out_T_5320 = ~out_romask_519; // @[RegisterRouter.scala:87:24]
wire _out_T_5321 = ~out_womask_519; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_437 = {hi_556, flags_0_go, _out_prepend_T_437}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_5322 = out_prepend_437; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_5323 = _out_T_5322; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_438 = _out_T_5323; // @[RegisterRouter.scala:87:24]
wire out_rimask_520 = |_out_rimask_T_520; // @[RegisterRouter.scala:87:24]
wire out_wimask_520 = &_out_wimask_T_520; // @[RegisterRouter.scala:87:24]
wire out_romask_520 = |_out_romask_T_520; // @[RegisterRouter.scala:87:24]
wire out_womask_520 = &_out_womask_T_520; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_520 = out_rivalid_1_374 & out_rimask_520; // @[RegisterRouter.scala:87:24]
wire _out_T_5325 = out_f_rivalid_520; // @[RegisterRouter.scala:87:24]
wire out_f_roready_520 = out_roready_1_374 & out_romask_520; // @[RegisterRouter.scala:87:24]
wire _out_T_5326 = out_f_roready_520; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_520 = out_wivalid_1_374 & out_wimask_520; // @[RegisterRouter.scala:87:24]
wire out_f_woready_520 = out_woready_1_374 & out_womask_520; // @[RegisterRouter.scala:87:24]
wire _out_T_5327 = ~out_rimask_520; // @[RegisterRouter.scala:87:24]
wire _out_T_5328 = ~out_wimask_520; // @[RegisterRouter.scala:87:24]
wire _out_T_5329 = ~out_romask_520; // @[RegisterRouter.scala:87:24]
wire _out_T_5330 = ~out_womask_520; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_438 = {hi_557, flags_0_go, _out_prepend_T_438}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_5331 = out_prepend_438; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_5332 = _out_T_5331; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_439 = _out_T_5332; // @[RegisterRouter.scala:87:24]
wire out_rimask_521 = |_out_rimask_T_521; // @[RegisterRouter.scala:87:24]
wire out_wimask_521 = &_out_wimask_T_521; // @[RegisterRouter.scala:87:24]
wire out_romask_521 = |_out_romask_T_521; // @[RegisterRouter.scala:87:24]
wire out_womask_521 = &_out_womask_T_521; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_521 = out_rivalid_1_375 & out_rimask_521; // @[RegisterRouter.scala:87:24]
wire _out_T_5334 = out_f_rivalid_521; // @[RegisterRouter.scala:87:24]
wire out_f_roready_521 = out_roready_1_375 & out_romask_521; // @[RegisterRouter.scala:87:24]
wire _out_T_5335 = out_f_roready_521; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_521 = out_wivalid_1_375 & out_wimask_521; // @[RegisterRouter.scala:87:24]
wire out_f_woready_521 = out_woready_1_375 & out_womask_521; // @[RegisterRouter.scala:87:24]
wire _out_T_5336 = ~out_rimask_521; // @[RegisterRouter.scala:87:24]
wire _out_T_5337 = ~out_wimask_521; // @[RegisterRouter.scala:87:24]
wire _out_T_5338 = ~out_romask_521; // @[RegisterRouter.scala:87:24]
wire _out_T_5339 = ~out_womask_521; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_439 = {hi_558, flags_0_go, _out_prepend_T_439}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_5340 = out_prepend_439; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_5341 = _out_T_5340; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_440 = _out_T_5341; // @[RegisterRouter.scala:87:24]
wire out_rimask_522 = |_out_rimask_T_522; // @[RegisterRouter.scala:87:24]
wire out_wimask_522 = &_out_wimask_T_522; // @[RegisterRouter.scala:87:24]
wire out_romask_522 = |_out_romask_T_522; // @[RegisterRouter.scala:87:24]
wire out_womask_522 = &_out_womask_T_522; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_522 = out_rivalid_1_376 & out_rimask_522; // @[RegisterRouter.scala:87:24]
wire _out_T_5343 = out_f_rivalid_522; // @[RegisterRouter.scala:87:24]
wire out_f_roready_522 = out_roready_1_376 & out_romask_522; // @[RegisterRouter.scala:87:24]
wire _out_T_5344 = out_f_roready_522; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_522 = out_wivalid_1_376 & out_wimask_522; // @[RegisterRouter.scala:87:24]
wire out_f_woready_522 = out_woready_1_376 & out_womask_522; // @[RegisterRouter.scala:87:24]
wire _out_T_5345 = ~out_rimask_522; // @[RegisterRouter.scala:87:24]
wire _out_T_5346 = ~out_wimask_522; // @[RegisterRouter.scala:87:24]
wire _out_T_5347 = ~out_romask_522; // @[RegisterRouter.scala:87:24]
wire _out_T_5348 = ~out_womask_522; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_440 = {hi_559, flags_0_go, _out_prepend_T_440}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_5349 = out_prepend_440; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_5350 = _out_T_5349; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_441 = _out_T_5350; // @[RegisterRouter.scala:87:24]
wire out_rimask_523 = |_out_rimask_T_523; // @[RegisterRouter.scala:87:24]
wire out_wimask_523 = &_out_wimask_T_523; // @[RegisterRouter.scala:87:24]
wire out_romask_523 = |_out_romask_T_523; // @[RegisterRouter.scala:87:24]
wire out_womask_523 = &_out_womask_T_523; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_523 = out_rivalid_1_377 & out_rimask_523; // @[RegisterRouter.scala:87:24]
wire _out_T_5352 = out_f_rivalid_523; // @[RegisterRouter.scala:87:24]
wire out_f_roready_523 = out_roready_1_377 & out_romask_523; // @[RegisterRouter.scala:87:24]
wire _out_T_5353 = out_f_roready_523; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_523 = out_wivalid_1_377 & out_wimask_523; // @[RegisterRouter.scala:87:24]
wire out_f_woready_523 = out_woready_1_377 & out_womask_523; // @[RegisterRouter.scala:87:24]
wire _out_T_5354 = ~out_rimask_523; // @[RegisterRouter.scala:87:24]
wire _out_T_5355 = ~out_wimask_523; // @[RegisterRouter.scala:87:24]
wire _out_T_5356 = ~out_romask_523; // @[RegisterRouter.scala:87:24]
wire _out_T_5357 = ~out_womask_523; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_441 = {hi_560, flags_0_go, _out_prepend_T_441}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_5358 = out_prepend_441; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_5359 = _out_T_5358; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_197 = _out_T_5359; // @[MuxLiteral.scala:49:48]
wire out_rimask_524 = |_out_rimask_T_524; // @[RegisterRouter.scala:87:24]
wire out_wimask_524 = &_out_wimask_T_524; // @[RegisterRouter.scala:87:24]
wire out_romask_524 = |_out_romask_T_524; // @[RegisterRouter.scala:87:24]
wire out_womask_524 = &_out_womask_T_524; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_524 = out_rivalid_1_378 & out_rimask_524; // @[RegisterRouter.scala:87:24]
wire _out_T_5361 = out_f_rivalid_524; // @[RegisterRouter.scala:87:24]
wire out_f_roready_524 = out_roready_1_378 & out_romask_524; // @[RegisterRouter.scala:87:24]
wire _out_T_5362 = out_f_roready_524; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_524 = out_wivalid_1_378 & out_wimask_524; // @[RegisterRouter.scala:87:24]
wire out_f_woready_524 = out_woready_1_378 & out_womask_524; // @[RegisterRouter.scala:87:24]
wire _out_T_5363 = ~out_rimask_524; // @[RegisterRouter.scala:87:24]
wire _out_T_5364 = ~out_wimask_524; // @[RegisterRouter.scala:87:24]
wire _out_T_5365 = ~out_romask_524; // @[RegisterRouter.scala:87:24]
wire _out_T_5366 = ~out_womask_524; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5368 = _out_T_5367; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_442 = _out_T_5368; // @[RegisterRouter.scala:87:24]
wire out_rimask_525 = |_out_rimask_T_525; // @[RegisterRouter.scala:87:24]
wire out_wimask_525 = &_out_wimask_T_525; // @[RegisterRouter.scala:87:24]
wire out_romask_525 = |_out_romask_T_525; // @[RegisterRouter.scala:87:24]
wire out_womask_525 = &_out_womask_T_525; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_525 = out_rivalid_1_379 & out_rimask_525; // @[RegisterRouter.scala:87:24]
wire _out_T_5370 = out_f_rivalid_525; // @[RegisterRouter.scala:87:24]
wire out_f_roready_525 = out_roready_1_379 & out_romask_525; // @[RegisterRouter.scala:87:24]
wire _out_T_5371 = out_f_roready_525; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_525 = out_wivalid_1_379 & out_wimask_525; // @[RegisterRouter.scala:87:24]
wire out_f_woready_525 = out_woready_1_379 & out_womask_525; // @[RegisterRouter.scala:87:24]
wire _out_T_5372 = ~out_rimask_525; // @[RegisterRouter.scala:87:24]
wire _out_T_5373 = ~out_wimask_525; // @[RegisterRouter.scala:87:24]
wire _out_T_5374 = ~out_romask_525; // @[RegisterRouter.scala:87:24]
wire _out_T_5375 = ~out_womask_525; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_442 = {hi_770, flags_0_go, _out_prepend_T_442}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_5376 = out_prepend_442; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_5377 = _out_T_5376; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_443 = _out_T_5377; // @[RegisterRouter.scala:87:24]
wire out_rimask_526 = |_out_rimask_T_526; // @[RegisterRouter.scala:87:24]
wire out_wimask_526 = &_out_wimask_T_526; // @[RegisterRouter.scala:87:24]
wire out_romask_526 = |_out_romask_T_526; // @[RegisterRouter.scala:87:24]
wire out_womask_526 = &_out_womask_T_526; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_526 = out_rivalid_1_380 & out_rimask_526; // @[RegisterRouter.scala:87:24]
wire _out_T_5379 = out_f_rivalid_526; // @[RegisterRouter.scala:87:24]
wire out_f_roready_526 = out_roready_1_380 & out_romask_526; // @[RegisterRouter.scala:87:24]
wire _out_T_5380 = out_f_roready_526; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_526 = out_wivalid_1_380 & out_wimask_526; // @[RegisterRouter.scala:87:24]
wire out_f_woready_526 = out_woready_1_380 & out_womask_526; // @[RegisterRouter.scala:87:24]
wire _out_T_5381 = ~out_rimask_526; // @[RegisterRouter.scala:87:24]
wire _out_T_5382 = ~out_wimask_526; // @[RegisterRouter.scala:87:24]
wire _out_T_5383 = ~out_romask_526; // @[RegisterRouter.scala:87:24]
wire _out_T_5384 = ~out_womask_526; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_443 = {hi_771, flags_0_go, _out_prepend_T_443}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_5385 = out_prepend_443; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_5386 = _out_T_5385; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_444 = _out_T_5386; // @[RegisterRouter.scala:87:24]
wire out_rimask_527 = |_out_rimask_T_527; // @[RegisterRouter.scala:87:24]
wire out_wimask_527 = &_out_wimask_T_527; // @[RegisterRouter.scala:87:24]
wire out_romask_527 = |_out_romask_T_527; // @[RegisterRouter.scala:87:24]
wire out_womask_527 = &_out_womask_T_527; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_527 = out_rivalid_1_381 & out_rimask_527; // @[RegisterRouter.scala:87:24]
wire _out_T_5388 = out_f_rivalid_527; // @[RegisterRouter.scala:87:24]
wire out_f_roready_527 = out_roready_1_381 & out_romask_527; // @[RegisterRouter.scala:87:24]
wire _out_T_5389 = out_f_roready_527; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_527 = out_wivalid_1_381 & out_wimask_527; // @[RegisterRouter.scala:87:24]
wire out_f_woready_527 = out_woready_1_381 & out_womask_527; // @[RegisterRouter.scala:87:24]
wire _out_T_5390 = ~out_rimask_527; // @[RegisterRouter.scala:87:24]
wire _out_T_5391 = ~out_wimask_527; // @[RegisterRouter.scala:87:24]
wire _out_T_5392 = ~out_romask_527; // @[RegisterRouter.scala:87:24]
wire _out_T_5393 = ~out_womask_527; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_444 = {hi_772, flags_0_go, _out_prepend_T_444}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_5394 = out_prepend_444; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_5395 = _out_T_5394; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_445 = _out_T_5395; // @[RegisterRouter.scala:87:24]
wire out_rimask_528 = |_out_rimask_T_528; // @[RegisterRouter.scala:87:24]
wire out_wimask_528 = &_out_wimask_T_528; // @[RegisterRouter.scala:87:24]
wire out_romask_528 = |_out_romask_T_528; // @[RegisterRouter.scala:87:24]
wire out_womask_528 = &_out_womask_T_528; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_528 = out_rivalid_1_382 & out_rimask_528; // @[RegisterRouter.scala:87:24]
wire _out_T_5397 = out_f_rivalid_528; // @[RegisterRouter.scala:87:24]
wire out_f_roready_528 = out_roready_1_382 & out_romask_528; // @[RegisterRouter.scala:87:24]
wire _out_T_5398 = out_f_roready_528; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_528 = out_wivalid_1_382 & out_wimask_528; // @[RegisterRouter.scala:87:24]
wire out_f_woready_528 = out_woready_1_382 & out_womask_528; // @[RegisterRouter.scala:87:24]
wire _out_T_5399 = ~out_rimask_528; // @[RegisterRouter.scala:87:24]
wire _out_T_5400 = ~out_wimask_528; // @[RegisterRouter.scala:87:24]
wire _out_T_5401 = ~out_romask_528; // @[RegisterRouter.scala:87:24]
wire _out_T_5402 = ~out_womask_528; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_445 = {hi_773, flags_0_go, _out_prepend_T_445}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_5403 = out_prepend_445; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_5404 = _out_T_5403; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_446 = _out_T_5404; // @[RegisterRouter.scala:87:24]
wire out_rimask_529 = |_out_rimask_T_529; // @[RegisterRouter.scala:87:24]
wire out_wimask_529 = &_out_wimask_T_529; // @[RegisterRouter.scala:87:24]
wire out_romask_529 = |_out_romask_T_529; // @[RegisterRouter.scala:87:24]
wire out_womask_529 = &_out_womask_T_529; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_529 = out_rivalid_1_383 & out_rimask_529; // @[RegisterRouter.scala:87:24]
wire _out_T_5406 = out_f_rivalid_529; // @[RegisterRouter.scala:87:24]
wire out_f_roready_529 = out_roready_1_383 & out_romask_529; // @[RegisterRouter.scala:87:24]
wire _out_T_5407 = out_f_roready_529; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_529 = out_wivalid_1_383 & out_wimask_529; // @[RegisterRouter.scala:87:24]
wire out_f_woready_529 = out_woready_1_383 & out_womask_529; // @[RegisterRouter.scala:87:24]
wire _out_T_5408 = ~out_rimask_529; // @[RegisterRouter.scala:87:24]
wire _out_T_5409 = ~out_wimask_529; // @[RegisterRouter.scala:87:24]
wire _out_T_5410 = ~out_romask_529; // @[RegisterRouter.scala:87:24]
wire _out_T_5411 = ~out_womask_529; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_446 = {hi_774, flags_0_go, _out_prepend_T_446}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_5412 = out_prepend_446; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_5413 = _out_T_5412; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_447 = _out_T_5413; // @[RegisterRouter.scala:87:24]
wire out_rimask_530 = |_out_rimask_T_530; // @[RegisterRouter.scala:87:24]
wire out_wimask_530 = &_out_wimask_T_530; // @[RegisterRouter.scala:87:24]
wire out_romask_530 = |_out_romask_T_530; // @[RegisterRouter.scala:87:24]
wire out_womask_530 = &_out_womask_T_530; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_530 = out_rivalid_1_384 & out_rimask_530; // @[RegisterRouter.scala:87:24]
wire _out_T_5415 = out_f_rivalid_530; // @[RegisterRouter.scala:87:24]
wire out_f_roready_530 = out_roready_1_384 & out_romask_530; // @[RegisterRouter.scala:87:24]
wire _out_T_5416 = out_f_roready_530; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_530 = out_wivalid_1_384 & out_wimask_530; // @[RegisterRouter.scala:87:24]
wire out_f_woready_530 = out_woready_1_384 & out_womask_530; // @[RegisterRouter.scala:87:24]
wire _out_T_5417 = ~out_rimask_530; // @[RegisterRouter.scala:87:24]
wire _out_T_5418 = ~out_wimask_530; // @[RegisterRouter.scala:87:24]
wire _out_T_5419 = ~out_romask_530; // @[RegisterRouter.scala:87:24]
wire _out_T_5420 = ~out_womask_530; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_447 = {hi_775, flags_0_go, _out_prepend_T_447}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_5421 = out_prepend_447; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_5422 = _out_T_5421; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_448 = _out_T_5422; // @[RegisterRouter.scala:87:24]
wire out_rimask_531 = |_out_rimask_T_531; // @[RegisterRouter.scala:87:24]
wire out_wimask_531 = &_out_wimask_T_531; // @[RegisterRouter.scala:87:24]
wire out_romask_531 = |_out_romask_T_531; // @[RegisterRouter.scala:87:24]
wire out_womask_531 = &_out_womask_T_531; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_531 = out_rivalid_1_385 & out_rimask_531; // @[RegisterRouter.scala:87:24]
wire _out_T_5424 = out_f_rivalid_531; // @[RegisterRouter.scala:87:24]
wire out_f_roready_531 = out_roready_1_385 & out_romask_531; // @[RegisterRouter.scala:87:24]
wire _out_T_5425 = out_f_roready_531; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_531 = out_wivalid_1_385 & out_wimask_531; // @[RegisterRouter.scala:87:24]
wire out_f_woready_531 = out_woready_1_385 & out_womask_531; // @[RegisterRouter.scala:87:24]
wire _out_T_5426 = ~out_rimask_531; // @[RegisterRouter.scala:87:24]
wire _out_T_5427 = ~out_wimask_531; // @[RegisterRouter.scala:87:24]
wire _out_T_5428 = ~out_romask_531; // @[RegisterRouter.scala:87:24]
wire _out_T_5429 = ~out_womask_531; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_448 = {hi_776, flags_0_go, _out_prepend_T_448}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_5430 = out_prepend_448; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_5431 = _out_T_5430; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_224 = _out_T_5431; // @[MuxLiteral.scala:49:48]
wire out_rimask_532 = |_out_rimask_T_532; // @[RegisterRouter.scala:87:24]
wire out_wimask_532 = &_out_wimask_T_532; // @[RegisterRouter.scala:87:24]
wire out_romask_532 = |_out_romask_T_532; // @[RegisterRouter.scala:87:24]
wire out_womask_532 = &_out_womask_T_532; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_532 = out_rivalid_1_386 & out_rimask_532; // @[RegisterRouter.scala:87:24]
wire _out_T_5433 = out_f_rivalid_532; // @[RegisterRouter.scala:87:24]
wire out_f_roready_532 = out_roready_1_386 & out_romask_532; // @[RegisterRouter.scala:87:24]
wire _out_T_5434 = out_f_roready_532; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_532 = out_wivalid_1_386 & out_wimask_532; // @[RegisterRouter.scala:87:24]
wire out_f_woready_532 = out_woready_1_386 & out_womask_532; // @[RegisterRouter.scala:87:24]
wire _out_T_5435 = ~out_rimask_532; // @[RegisterRouter.scala:87:24]
wire _out_T_5436 = ~out_wimask_532; // @[RegisterRouter.scala:87:24]
wire _out_T_5437 = ~out_romask_532; // @[RegisterRouter.scala:87:24]
wire _out_T_5438 = ~out_womask_532; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5440 = _out_T_5439; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_449 = _out_T_5440; // @[RegisterRouter.scala:87:24]
wire out_rimask_533 = |_out_rimask_T_533; // @[RegisterRouter.scala:87:24]
wire out_wimask_533 = &_out_wimask_T_533; // @[RegisterRouter.scala:87:24]
wire out_romask_533 = |_out_romask_T_533; // @[RegisterRouter.scala:87:24]
wire out_womask_533 = &_out_womask_T_533; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_533 = out_rivalid_1_387 & out_rimask_533; // @[RegisterRouter.scala:87:24]
wire _out_T_5442 = out_f_rivalid_533; // @[RegisterRouter.scala:87:24]
wire out_f_roready_533 = out_roready_1_387 & out_romask_533; // @[RegisterRouter.scala:87:24]
wire _out_T_5443 = out_f_roready_533; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_533 = out_wivalid_1_387 & out_wimask_533; // @[RegisterRouter.scala:87:24]
wire out_f_woready_533 = out_woready_1_387 & out_womask_533; // @[RegisterRouter.scala:87:24]
wire _out_T_5444 = ~out_rimask_533; // @[RegisterRouter.scala:87:24]
wire _out_T_5445 = ~out_wimask_533; // @[RegisterRouter.scala:87:24]
wire _out_T_5446 = ~out_romask_533; // @[RegisterRouter.scala:87:24]
wire _out_T_5447 = ~out_womask_533; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_449 = {hi_226, flags_0_go, _out_prepend_T_449}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_5448 = out_prepend_449; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_5449 = _out_T_5448; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_450 = _out_T_5449; // @[RegisterRouter.scala:87:24]
wire out_rimask_534 = |_out_rimask_T_534; // @[RegisterRouter.scala:87:24]
wire out_wimask_534 = &_out_wimask_T_534; // @[RegisterRouter.scala:87:24]
wire out_romask_534 = |_out_romask_T_534; // @[RegisterRouter.scala:87:24]
wire out_womask_534 = &_out_womask_T_534; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_534 = out_rivalid_1_388 & out_rimask_534; // @[RegisterRouter.scala:87:24]
wire _out_T_5451 = out_f_rivalid_534; // @[RegisterRouter.scala:87:24]
wire out_f_roready_534 = out_roready_1_388 & out_romask_534; // @[RegisterRouter.scala:87:24]
wire _out_T_5452 = out_f_roready_534; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_534 = out_wivalid_1_388 & out_wimask_534; // @[RegisterRouter.scala:87:24]
wire out_f_woready_534 = out_woready_1_388 & out_womask_534; // @[RegisterRouter.scala:87:24]
wire _out_T_5453 = ~out_rimask_534; // @[RegisterRouter.scala:87:24]
wire _out_T_5454 = ~out_wimask_534; // @[RegisterRouter.scala:87:24]
wire _out_T_5455 = ~out_romask_534; // @[RegisterRouter.scala:87:24]
wire _out_T_5456 = ~out_womask_534; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_450 = {hi_227, flags_0_go, _out_prepend_T_450}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_5457 = out_prepend_450; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_5458 = _out_T_5457; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_451 = _out_T_5458; // @[RegisterRouter.scala:87:24]
wire out_rimask_535 = |_out_rimask_T_535; // @[RegisterRouter.scala:87:24]
wire out_wimask_535 = &_out_wimask_T_535; // @[RegisterRouter.scala:87:24]
wire out_romask_535 = |_out_romask_T_535; // @[RegisterRouter.scala:87:24]
wire out_womask_535 = &_out_womask_T_535; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_535 = out_rivalid_1_389 & out_rimask_535; // @[RegisterRouter.scala:87:24]
wire _out_T_5460 = out_f_rivalid_535; // @[RegisterRouter.scala:87:24]
wire out_f_roready_535 = out_roready_1_389 & out_romask_535; // @[RegisterRouter.scala:87:24]
wire _out_T_5461 = out_f_roready_535; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_535 = out_wivalid_1_389 & out_wimask_535; // @[RegisterRouter.scala:87:24]
wire out_f_woready_535 = out_woready_1_389 & out_womask_535; // @[RegisterRouter.scala:87:24]
wire _out_T_5462 = ~out_rimask_535; // @[RegisterRouter.scala:87:24]
wire _out_T_5463 = ~out_wimask_535; // @[RegisterRouter.scala:87:24]
wire _out_T_5464 = ~out_romask_535; // @[RegisterRouter.scala:87:24]
wire _out_T_5465 = ~out_womask_535; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_451 = {hi_228, flags_0_go, _out_prepend_T_451}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_5466 = out_prepend_451; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_5467 = _out_T_5466; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_452 = _out_T_5467; // @[RegisterRouter.scala:87:24]
wire out_rimask_536 = |_out_rimask_T_536; // @[RegisterRouter.scala:87:24]
wire out_wimask_536 = &_out_wimask_T_536; // @[RegisterRouter.scala:87:24]
wire out_romask_536 = |_out_romask_T_536; // @[RegisterRouter.scala:87:24]
wire out_womask_536 = &_out_womask_T_536; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_536 = out_rivalid_1_390 & out_rimask_536; // @[RegisterRouter.scala:87:24]
wire _out_T_5469 = out_f_rivalid_536; // @[RegisterRouter.scala:87:24]
wire out_f_roready_536 = out_roready_1_390 & out_romask_536; // @[RegisterRouter.scala:87:24]
wire _out_T_5470 = out_f_roready_536; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_536 = out_wivalid_1_390 & out_wimask_536; // @[RegisterRouter.scala:87:24]
wire out_f_woready_536 = out_woready_1_390 & out_womask_536; // @[RegisterRouter.scala:87:24]
wire _out_T_5471 = ~out_rimask_536; // @[RegisterRouter.scala:87:24]
wire _out_T_5472 = ~out_wimask_536; // @[RegisterRouter.scala:87:24]
wire _out_T_5473 = ~out_romask_536; // @[RegisterRouter.scala:87:24]
wire _out_T_5474 = ~out_womask_536; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_452 = {hi_229, flags_0_go, _out_prepend_T_452}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_5475 = out_prepend_452; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_5476 = _out_T_5475; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_453 = _out_T_5476; // @[RegisterRouter.scala:87:24]
wire out_rimask_537 = |_out_rimask_T_537; // @[RegisterRouter.scala:87:24]
wire out_wimask_537 = &_out_wimask_T_537; // @[RegisterRouter.scala:87:24]
wire out_romask_537 = |_out_romask_T_537; // @[RegisterRouter.scala:87:24]
wire out_womask_537 = &_out_womask_T_537; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_537 = out_rivalid_1_391 & out_rimask_537; // @[RegisterRouter.scala:87:24]
wire _out_T_5478 = out_f_rivalid_537; // @[RegisterRouter.scala:87:24]
wire out_f_roready_537 = out_roready_1_391 & out_romask_537; // @[RegisterRouter.scala:87:24]
wire _out_T_5479 = out_f_roready_537; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_537 = out_wivalid_1_391 & out_wimask_537; // @[RegisterRouter.scala:87:24]
wire out_f_woready_537 = out_woready_1_391 & out_womask_537; // @[RegisterRouter.scala:87:24]
wire _out_T_5480 = ~out_rimask_537; // @[RegisterRouter.scala:87:24]
wire _out_T_5481 = ~out_wimask_537; // @[RegisterRouter.scala:87:24]
wire _out_T_5482 = ~out_romask_537; // @[RegisterRouter.scala:87:24]
wire _out_T_5483 = ~out_womask_537; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_453 = {hi_230, flags_0_go, _out_prepend_T_453}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_5484 = out_prepend_453; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_5485 = _out_T_5484; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_454 = _out_T_5485; // @[RegisterRouter.scala:87:24]
wire out_rimask_538 = |_out_rimask_T_538; // @[RegisterRouter.scala:87:24]
wire out_wimask_538 = &_out_wimask_T_538; // @[RegisterRouter.scala:87:24]
wire out_romask_538 = |_out_romask_T_538; // @[RegisterRouter.scala:87:24]
wire out_womask_538 = &_out_womask_T_538; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_538 = out_rivalid_1_392 & out_rimask_538; // @[RegisterRouter.scala:87:24]
wire _out_T_5487 = out_f_rivalid_538; // @[RegisterRouter.scala:87:24]
wire out_f_roready_538 = out_roready_1_392 & out_romask_538; // @[RegisterRouter.scala:87:24]
wire _out_T_5488 = out_f_roready_538; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_538 = out_wivalid_1_392 & out_wimask_538; // @[RegisterRouter.scala:87:24]
wire out_f_woready_538 = out_woready_1_392 & out_womask_538; // @[RegisterRouter.scala:87:24]
wire _out_T_5489 = ~out_rimask_538; // @[RegisterRouter.scala:87:24]
wire _out_T_5490 = ~out_wimask_538; // @[RegisterRouter.scala:87:24]
wire _out_T_5491 = ~out_romask_538; // @[RegisterRouter.scala:87:24]
wire _out_T_5492 = ~out_womask_538; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_454 = {hi_231, flags_0_go, _out_prepend_T_454}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_5493 = out_prepend_454; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_5494 = _out_T_5493; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_455 = _out_T_5494; // @[RegisterRouter.scala:87:24]
wire out_rimask_539 = |_out_rimask_T_539; // @[RegisterRouter.scala:87:24]
wire out_wimask_539 = &_out_wimask_T_539; // @[RegisterRouter.scala:87:24]
wire out_romask_539 = |_out_romask_T_539; // @[RegisterRouter.scala:87:24]
wire out_womask_539 = &_out_womask_T_539; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_539 = out_rivalid_1_393 & out_rimask_539; // @[RegisterRouter.scala:87:24]
wire _out_T_5496 = out_f_rivalid_539; // @[RegisterRouter.scala:87:24]
wire out_f_roready_539 = out_roready_1_393 & out_romask_539; // @[RegisterRouter.scala:87:24]
wire _out_T_5497 = out_f_roready_539; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_539 = out_wivalid_1_393 & out_wimask_539; // @[RegisterRouter.scala:87:24]
wire out_f_woready_539 = out_woready_1_393 & out_womask_539; // @[RegisterRouter.scala:87:24]
wire _out_T_5498 = ~out_rimask_539; // @[RegisterRouter.scala:87:24]
wire _out_T_5499 = ~out_wimask_539; // @[RegisterRouter.scala:87:24]
wire _out_T_5500 = ~out_romask_539; // @[RegisterRouter.scala:87:24]
wire _out_T_5501 = ~out_womask_539; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_455 = {hi_232, flags_0_go, _out_prepend_T_455}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_5502 = out_prepend_455; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_5503 = _out_T_5502; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_156 = _out_T_5503; // @[MuxLiteral.scala:49:48]
wire out_rimask_540 = |_out_rimask_T_540; // @[RegisterRouter.scala:87:24]
wire out_wimask_540 = &_out_wimask_T_540; // @[RegisterRouter.scala:87:24]
wire out_romask_540 = |_out_romask_T_540; // @[RegisterRouter.scala:87:24]
wire out_womask_540 = &_out_womask_T_540; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_540 = out_rivalid_1_394 & out_rimask_540; // @[RegisterRouter.scala:87:24]
wire _out_T_5505 = out_f_rivalid_540; // @[RegisterRouter.scala:87:24]
wire out_f_roready_540 = out_roready_1_394 & out_romask_540; // @[RegisterRouter.scala:87:24]
wire _out_T_5506 = out_f_roready_540; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_540 = out_wivalid_1_394 & out_wimask_540; // @[RegisterRouter.scala:87:24]
wire out_f_woready_540 = out_woready_1_394 & out_womask_540; // @[RegisterRouter.scala:87:24]
wire _out_T_5507 = ~out_rimask_540; // @[RegisterRouter.scala:87:24]
wire _out_T_5508 = ~out_wimask_540; // @[RegisterRouter.scala:87:24]
wire _out_T_5509 = ~out_romask_540; // @[RegisterRouter.scala:87:24]
wire _out_T_5510 = ~out_womask_540; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5512 = _out_T_5511; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_456 = _out_T_5512; // @[RegisterRouter.scala:87:24]
wire out_rimask_541 = |_out_rimask_T_541; // @[RegisterRouter.scala:87:24]
wire out_wimask_541 = &_out_wimask_T_541; // @[RegisterRouter.scala:87:24]
wire out_romask_541 = |_out_romask_T_541; // @[RegisterRouter.scala:87:24]
wire out_womask_541 = &_out_womask_T_541; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_541 = out_rivalid_1_395 & out_rimask_541; // @[RegisterRouter.scala:87:24]
wire _out_T_5514 = out_f_rivalid_541; // @[RegisterRouter.scala:87:24]
wire out_f_roready_541 = out_roready_1_395 & out_romask_541; // @[RegisterRouter.scala:87:24]
wire _out_T_5515 = out_f_roready_541; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_541 = out_wivalid_1_395 & out_wimask_541; // @[RegisterRouter.scala:87:24]
wire out_f_woready_541 = out_woready_1_395 & out_womask_541; // @[RegisterRouter.scala:87:24]
wire _out_T_5516 = ~out_rimask_541; // @[RegisterRouter.scala:87:24]
wire _out_T_5517 = ~out_wimask_541; // @[RegisterRouter.scala:87:24]
wire _out_T_5518 = ~out_romask_541; // @[RegisterRouter.scala:87:24]
wire _out_T_5519 = ~out_womask_541; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_456 = {hi_482, flags_0_go, _out_prepend_T_456}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_5520 = out_prepend_456; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_5521 = _out_T_5520; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_457 = _out_T_5521; // @[RegisterRouter.scala:87:24]
wire out_rimask_542 = |_out_rimask_T_542; // @[RegisterRouter.scala:87:24]
wire out_wimask_542 = &_out_wimask_T_542; // @[RegisterRouter.scala:87:24]
wire out_romask_542 = |_out_romask_T_542; // @[RegisterRouter.scala:87:24]
wire out_womask_542 = &_out_womask_T_542; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_542 = out_rivalid_1_396 & out_rimask_542; // @[RegisterRouter.scala:87:24]
wire _out_T_5523 = out_f_rivalid_542; // @[RegisterRouter.scala:87:24]
wire out_f_roready_542 = out_roready_1_396 & out_romask_542; // @[RegisterRouter.scala:87:24]
wire _out_T_5524 = out_f_roready_542; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_542 = out_wivalid_1_396 & out_wimask_542; // @[RegisterRouter.scala:87:24]
wire out_f_woready_542 = out_woready_1_396 & out_womask_542; // @[RegisterRouter.scala:87:24]
wire _out_T_5525 = ~out_rimask_542; // @[RegisterRouter.scala:87:24]
wire _out_T_5526 = ~out_wimask_542; // @[RegisterRouter.scala:87:24]
wire _out_T_5527 = ~out_romask_542; // @[RegisterRouter.scala:87:24]
wire _out_T_5528 = ~out_womask_542; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_457 = {hi_483, flags_0_go, _out_prepend_T_457}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_5529 = out_prepend_457; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_5530 = _out_T_5529; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_458 = _out_T_5530; // @[RegisterRouter.scala:87:24]
wire out_rimask_543 = |_out_rimask_T_543; // @[RegisterRouter.scala:87:24]
wire out_wimask_543 = &_out_wimask_T_543; // @[RegisterRouter.scala:87:24]
wire out_romask_543 = |_out_romask_T_543; // @[RegisterRouter.scala:87:24]
wire out_womask_543 = &_out_womask_T_543; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_543 = out_rivalid_1_397 & out_rimask_543; // @[RegisterRouter.scala:87:24]
wire _out_T_5532 = out_f_rivalid_543; // @[RegisterRouter.scala:87:24]
wire out_f_roready_543 = out_roready_1_397 & out_romask_543; // @[RegisterRouter.scala:87:24]
wire _out_T_5533 = out_f_roready_543; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_543 = out_wivalid_1_397 & out_wimask_543; // @[RegisterRouter.scala:87:24]
wire out_f_woready_543 = out_woready_1_397 & out_womask_543; // @[RegisterRouter.scala:87:24]
wire _out_T_5534 = ~out_rimask_543; // @[RegisterRouter.scala:87:24]
wire _out_T_5535 = ~out_wimask_543; // @[RegisterRouter.scala:87:24]
wire _out_T_5536 = ~out_romask_543; // @[RegisterRouter.scala:87:24]
wire _out_T_5537 = ~out_womask_543; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_458 = {hi_484, flags_0_go, _out_prepend_T_458}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_5538 = out_prepend_458; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_5539 = _out_T_5538; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_459 = _out_T_5539; // @[RegisterRouter.scala:87:24]
wire out_rimask_544 = |_out_rimask_T_544; // @[RegisterRouter.scala:87:24]
wire out_wimask_544 = &_out_wimask_T_544; // @[RegisterRouter.scala:87:24]
wire out_romask_544 = |_out_romask_T_544; // @[RegisterRouter.scala:87:24]
wire out_womask_544 = &_out_womask_T_544; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_544 = out_rivalid_1_398 & out_rimask_544; // @[RegisterRouter.scala:87:24]
wire _out_T_5541 = out_f_rivalid_544; // @[RegisterRouter.scala:87:24]
wire out_f_roready_544 = out_roready_1_398 & out_romask_544; // @[RegisterRouter.scala:87:24]
wire _out_T_5542 = out_f_roready_544; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_544 = out_wivalid_1_398 & out_wimask_544; // @[RegisterRouter.scala:87:24]
wire out_f_woready_544 = out_woready_1_398 & out_womask_544; // @[RegisterRouter.scala:87:24]
wire _out_T_5543 = ~out_rimask_544; // @[RegisterRouter.scala:87:24]
wire _out_T_5544 = ~out_wimask_544; // @[RegisterRouter.scala:87:24]
wire _out_T_5545 = ~out_romask_544; // @[RegisterRouter.scala:87:24]
wire _out_T_5546 = ~out_womask_544; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_459 = {hi_485, flags_0_go, _out_prepend_T_459}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_5547 = out_prepend_459; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_5548 = _out_T_5547; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_460 = _out_T_5548; // @[RegisterRouter.scala:87:24]
wire out_rimask_545 = |_out_rimask_T_545; // @[RegisterRouter.scala:87:24]
wire out_wimask_545 = &_out_wimask_T_545; // @[RegisterRouter.scala:87:24]
wire out_romask_545 = |_out_romask_T_545; // @[RegisterRouter.scala:87:24]
wire out_womask_545 = &_out_womask_T_545; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_545 = out_rivalid_1_399 & out_rimask_545; // @[RegisterRouter.scala:87:24]
wire _out_T_5550 = out_f_rivalid_545; // @[RegisterRouter.scala:87:24]
wire out_f_roready_545 = out_roready_1_399 & out_romask_545; // @[RegisterRouter.scala:87:24]
wire _out_T_5551 = out_f_roready_545; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_545 = out_wivalid_1_399 & out_wimask_545; // @[RegisterRouter.scala:87:24]
wire out_f_woready_545 = out_woready_1_399 & out_womask_545; // @[RegisterRouter.scala:87:24]
wire _out_T_5552 = ~out_rimask_545; // @[RegisterRouter.scala:87:24]
wire _out_T_5553 = ~out_wimask_545; // @[RegisterRouter.scala:87:24]
wire _out_T_5554 = ~out_romask_545; // @[RegisterRouter.scala:87:24]
wire _out_T_5555 = ~out_womask_545; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_460 = {hi_486, flags_0_go, _out_prepend_T_460}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_5556 = out_prepend_460; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_5557 = _out_T_5556; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_461 = _out_T_5557; // @[RegisterRouter.scala:87:24]
wire out_rimask_546 = |_out_rimask_T_546; // @[RegisterRouter.scala:87:24]
wire out_wimask_546 = &_out_wimask_T_546; // @[RegisterRouter.scala:87:24]
wire out_romask_546 = |_out_romask_T_546; // @[RegisterRouter.scala:87:24]
wire out_womask_546 = &_out_womask_T_546; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_546 = out_rivalid_1_400 & out_rimask_546; // @[RegisterRouter.scala:87:24]
wire _out_T_5559 = out_f_rivalid_546; // @[RegisterRouter.scala:87:24]
wire out_f_roready_546 = out_roready_1_400 & out_romask_546; // @[RegisterRouter.scala:87:24]
wire _out_T_5560 = out_f_roready_546; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_546 = out_wivalid_1_400 & out_wimask_546; // @[RegisterRouter.scala:87:24]
wire out_f_woready_546 = out_woready_1_400 & out_womask_546; // @[RegisterRouter.scala:87:24]
wire _out_T_5561 = ~out_rimask_546; // @[RegisterRouter.scala:87:24]
wire _out_T_5562 = ~out_wimask_546; // @[RegisterRouter.scala:87:24]
wire _out_T_5563 = ~out_romask_546; // @[RegisterRouter.scala:87:24]
wire _out_T_5564 = ~out_womask_546; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_461 = {hi_487, flags_0_go, _out_prepend_T_461}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_5565 = out_prepend_461; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_5566 = _out_T_5565; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_462 = _out_T_5566; // @[RegisterRouter.scala:87:24]
wire out_rimask_547 = |_out_rimask_T_547; // @[RegisterRouter.scala:87:24]
wire out_wimask_547 = &_out_wimask_T_547; // @[RegisterRouter.scala:87:24]
wire out_romask_547 = |_out_romask_T_547; // @[RegisterRouter.scala:87:24]
wire out_womask_547 = &_out_womask_T_547; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_547 = out_rivalid_1_401 & out_rimask_547; // @[RegisterRouter.scala:87:24]
wire _out_T_5568 = out_f_rivalid_547; // @[RegisterRouter.scala:87:24]
wire out_f_roready_547 = out_roready_1_401 & out_romask_547; // @[RegisterRouter.scala:87:24]
wire _out_T_5569 = out_f_roready_547; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_547 = out_wivalid_1_401 & out_wimask_547; // @[RegisterRouter.scala:87:24]
wire out_f_woready_547 = out_woready_1_401 & out_womask_547; // @[RegisterRouter.scala:87:24]
wire _out_T_5570 = ~out_rimask_547; // @[RegisterRouter.scala:87:24]
wire _out_T_5571 = ~out_wimask_547; // @[RegisterRouter.scala:87:24]
wire _out_T_5572 = ~out_romask_547; // @[RegisterRouter.scala:87:24]
wire _out_T_5573 = ~out_womask_547; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_462 = {hi_488, flags_0_go, _out_prepend_T_462}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_5574 = out_prepend_462; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_5575 = _out_T_5574; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_188 = _out_T_5575; // @[MuxLiteral.scala:49:48]
wire out_rimask_548 = |_out_rimask_T_548; // @[RegisterRouter.scala:87:24]
wire out_wimask_548 = &_out_wimask_T_548; // @[RegisterRouter.scala:87:24]
wire out_romask_548 = |_out_romask_T_548; // @[RegisterRouter.scala:87:24]
wire out_womask_548 = &_out_womask_T_548; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_548 = out_rivalid_1_402 & out_rimask_548; // @[RegisterRouter.scala:87:24]
wire _out_T_5577 = out_f_rivalid_548; // @[RegisterRouter.scala:87:24]
wire out_f_roready_548 = out_roready_1_402 & out_romask_548; // @[RegisterRouter.scala:87:24]
wire _out_T_5578 = out_f_roready_548; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_548 = out_wivalid_1_402 & out_wimask_548; // @[RegisterRouter.scala:87:24]
wire out_f_woready_548 = out_woready_1_402 & out_womask_548; // @[RegisterRouter.scala:87:24]
wire _out_T_5579 = ~out_rimask_548; // @[RegisterRouter.scala:87:24]
wire _out_T_5580 = ~out_wimask_548; // @[RegisterRouter.scala:87:24]
wire _out_T_5581 = ~out_romask_548; // @[RegisterRouter.scala:87:24]
wire _out_T_5582 = ~out_womask_548; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5584 = _out_T_5583; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_463 = _out_T_5584; // @[RegisterRouter.scala:87:24]
wire out_rimask_549 = |_out_rimask_T_549; // @[RegisterRouter.scala:87:24]
wire out_wimask_549 = &_out_wimask_T_549; // @[RegisterRouter.scala:87:24]
wire out_romask_549 = |_out_romask_T_549; // @[RegisterRouter.scala:87:24]
wire out_womask_549 = &_out_womask_T_549; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_549 = out_rivalid_1_403 & out_rimask_549; // @[RegisterRouter.scala:87:24]
wire _out_T_5586 = out_f_rivalid_549; // @[RegisterRouter.scala:87:24]
wire out_f_roready_549 = out_roready_1_403 & out_romask_549; // @[RegisterRouter.scala:87:24]
wire _out_T_5587 = out_f_roready_549; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_549 = out_wivalid_1_403 & out_wimask_549; // @[RegisterRouter.scala:87:24]
wire out_f_woready_549 = out_woready_1_403 & out_womask_549; // @[RegisterRouter.scala:87:24]
wire _out_T_5588 = ~out_rimask_549; // @[RegisterRouter.scala:87:24]
wire _out_T_5589 = ~out_wimask_549; // @[RegisterRouter.scala:87:24]
wire _out_T_5590 = ~out_romask_549; // @[RegisterRouter.scala:87:24]
wire _out_T_5591 = ~out_womask_549; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_463 = {hi_330, flags_0_go, _out_prepend_T_463}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_5592 = out_prepend_463; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_5593 = _out_T_5592; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_464 = _out_T_5593; // @[RegisterRouter.scala:87:24]
wire out_rimask_550 = |_out_rimask_T_550; // @[RegisterRouter.scala:87:24]
wire out_wimask_550 = &_out_wimask_T_550; // @[RegisterRouter.scala:87:24]
wire out_romask_550 = |_out_romask_T_550; // @[RegisterRouter.scala:87:24]
wire out_womask_550 = &_out_womask_T_550; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_550 = out_rivalid_1_404 & out_rimask_550; // @[RegisterRouter.scala:87:24]
wire _out_T_5595 = out_f_rivalid_550; // @[RegisterRouter.scala:87:24]
wire out_f_roready_550 = out_roready_1_404 & out_romask_550; // @[RegisterRouter.scala:87:24]
wire _out_T_5596 = out_f_roready_550; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_550 = out_wivalid_1_404 & out_wimask_550; // @[RegisterRouter.scala:87:24]
wire out_f_woready_550 = out_woready_1_404 & out_womask_550; // @[RegisterRouter.scala:87:24]
wire _out_T_5597 = ~out_rimask_550; // @[RegisterRouter.scala:87:24]
wire _out_T_5598 = ~out_wimask_550; // @[RegisterRouter.scala:87:24]
wire _out_T_5599 = ~out_romask_550; // @[RegisterRouter.scala:87:24]
wire _out_T_5600 = ~out_womask_550; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_464 = {hi_331, flags_0_go, _out_prepend_T_464}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_5601 = out_prepend_464; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_5602 = _out_T_5601; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_465 = _out_T_5602; // @[RegisterRouter.scala:87:24]
wire out_rimask_551 = |_out_rimask_T_551; // @[RegisterRouter.scala:87:24]
wire out_wimask_551 = &_out_wimask_T_551; // @[RegisterRouter.scala:87:24]
wire out_romask_551 = |_out_romask_T_551; // @[RegisterRouter.scala:87:24]
wire out_womask_551 = &_out_womask_T_551; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_551 = out_rivalid_1_405 & out_rimask_551; // @[RegisterRouter.scala:87:24]
wire _out_T_5604 = out_f_rivalid_551; // @[RegisterRouter.scala:87:24]
wire out_f_roready_551 = out_roready_1_405 & out_romask_551; // @[RegisterRouter.scala:87:24]
wire _out_T_5605 = out_f_roready_551; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_551 = out_wivalid_1_405 & out_wimask_551; // @[RegisterRouter.scala:87:24]
wire out_f_woready_551 = out_woready_1_405 & out_womask_551; // @[RegisterRouter.scala:87:24]
wire _out_T_5606 = ~out_rimask_551; // @[RegisterRouter.scala:87:24]
wire _out_T_5607 = ~out_wimask_551; // @[RegisterRouter.scala:87:24]
wire _out_T_5608 = ~out_romask_551; // @[RegisterRouter.scala:87:24]
wire _out_T_5609 = ~out_womask_551; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_465 = {hi_332, flags_0_go, _out_prepend_T_465}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_5610 = out_prepend_465; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_5611 = _out_T_5610; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_466 = _out_T_5611; // @[RegisterRouter.scala:87:24]
wire out_rimask_552 = |_out_rimask_T_552; // @[RegisterRouter.scala:87:24]
wire out_wimask_552 = &_out_wimask_T_552; // @[RegisterRouter.scala:87:24]
wire out_romask_552 = |_out_romask_T_552; // @[RegisterRouter.scala:87:24]
wire out_womask_552 = &_out_womask_T_552; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_552 = out_rivalid_1_406 & out_rimask_552; // @[RegisterRouter.scala:87:24]
wire _out_T_5613 = out_f_rivalid_552; // @[RegisterRouter.scala:87:24]
wire out_f_roready_552 = out_roready_1_406 & out_romask_552; // @[RegisterRouter.scala:87:24]
wire _out_T_5614 = out_f_roready_552; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_552 = out_wivalid_1_406 & out_wimask_552; // @[RegisterRouter.scala:87:24]
wire out_f_woready_552 = out_woready_1_406 & out_womask_552; // @[RegisterRouter.scala:87:24]
wire _out_T_5615 = ~out_rimask_552; // @[RegisterRouter.scala:87:24]
wire _out_T_5616 = ~out_wimask_552; // @[RegisterRouter.scala:87:24]
wire _out_T_5617 = ~out_romask_552; // @[RegisterRouter.scala:87:24]
wire _out_T_5618 = ~out_womask_552; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_466 = {hi_333, flags_0_go, _out_prepend_T_466}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_5619 = out_prepend_466; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_5620 = _out_T_5619; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_467 = _out_T_5620; // @[RegisterRouter.scala:87:24]
wire out_rimask_553 = |_out_rimask_T_553; // @[RegisterRouter.scala:87:24]
wire out_wimask_553 = &_out_wimask_T_553; // @[RegisterRouter.scala:87:24]
wire out_romask_553 = |_out_romask_T_553; // @[RegisterRouter.scala:87:24]
wire out_womask_553 = &_out_womask_T_553; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_553 = out_rivalid_1_407 & out_rimask_553; // @[RegisterRouter.scala:87:24]
wire _out_T_5622 = out_f_rivalid_553; // @[RegisterRouter.scala:87:24]
wire out_f_roready_553 = out_roready_1_407 & out_romask_553; // @[RegisterRouter.scala:87:24]
wire _out_T_5623 = out_f_roready_553; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_553 = out_wivalid_1_407 & out_wimask_553; // @[RegisterRouter.scala:87:24]
wire out_f_woready_553 = out_woready_1_407 & out_womask_553; // @[RegisterRouter.scala:87:24]
wire _out_T_5624 = ~out_rimask_553; // @[RegisterRouter.scala:87:24]
wire _out_T_5625 = ~out_wimask_553; // @[RegisterRouter.scala:87:24]
wire _out_T_5626 = ~out_romask_553; // @[RegisterRouter.scala:87:24]
wire _out_T_5627 = ~out_womask_553; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_467 = {hi_334, flags_0_go, _out_prepend_T_467}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_5628 = out_prepend_467; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_5629 = _out_T_5628; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_468 = _out_T_5629; // @[RegisterRouter.scala:87:24]
wire out_rimask_554 = |_out_rimask_T_554; // @[RegisterRouter.scala:87:24]
wire out_wimask_554 = &_out_wimask_T_554; // @[RegisterRouter.scala:87:24]
wire out_romask_554 = |_out_romask_T_554; // @[RegisterRouter.scala:87:24]
wire out_womask_554 = &_out_womask_T_554; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_554 = out_rivalid_1_408 & out_rimask_554; // @[RegisterRouter.scala:87:24]
wire _out_T_5631 = out_f_rivalid_554; // @[RegisterRouter.scala:87:24]
wire out_f_roready_554 = out_roready_1_408 & out_romask_554; // @[RegisterRouter.scala:87:24]
wire _out_T_5632 = out_f_roready_554; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_554 = out_wivalid_1_408 & out_wimask_554; // @[RegisterRouter.scala:87:24]
wire out_f_woready_554 = out_woready_1_408 & out_womask_554; // @[RegisterRouter.scala:87:24]
wire _out_T_5633 = ~out_rimask_554; // @[RegisterRouter.scala:87:24]
wire _out_T_5634 = ~out_wimask_554; // @[RegisterRouter.scala:87:24]
wire _out_T_5635 = ~out_romask_554; // @[RegisterRouter.scala:87:24]
wire _out_T_5636 = ~out_womask_554; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_468 = {hi_335, flags_0_go, _out_prepend_T_468}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_5637 = out_prepend_468; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_5638 = _out_T_5637; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_469 = _out_T_5638; // @[RegisterRouter.scala:87:24]
wire out_rimask_555 = |_out_rimask_T_555; // @[RegisterRouter.scala:87:24]
wire out_wimask_555 = &_out_wimask_T_555; // @[RegisterRouter.scala:87:24]
wire out_romask_555 = |_out_romask_T_555; // @[RegisterRouter.scala:87:24]
wire out_womask_555 = &_out_womask_T_555; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_555 = out_rivalid_1_409 & out_rimask_555; // @[RegisterRouter.scala:87:24]
wire _out_T_5640 = out_f_rivalid_555; // @[RegisterRouter.scala:87:24]
wire out_f_roready_555 = out_roready_1_409 & out_romask_555; // @[RegisterRouter.scala:87:24]
wire _out_T_5641 = out_f_roready_555; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_555 = out_wivalid_1_409 & out_wimask_555; // @[RegisterRouter.scala:87:24]
wire out_f_woready_555 = out_woready_1_409 & out_womask_555; // @[RegisterRouter.scala:87:24]
wire _out_T_5642 = ~out_rimask_555; // @[RegisterRouter.scala:87:24]
wire _out_T_5643 = ~out_wimask_555; // @[RegisterRouter.scala:87:24]
wire _out_T_5644 = ~out_romask_555; // @[RegisterRouter.scala:87:24]
wire _out_T_5645 = ~out_womask_555; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_469 = {hi_336, flags_0_go, _out_prepend_T_469}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_5646 = out_prepend_469; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_5647 = _out_T_5646; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_169 = _out_T_5647; // @[MuxLiteral.scala:49:48]
wire out_rimask_556 = |_out_rimask_T_556; // @[RegisterRouter.scala:87:24]
wire out_wimask_556 = &_out_wimask_T_556; // @[RegisterRouter.scala:87:24]
wire out_romask_556 = |_out_romask_T_556; // @[RegisterRouter.scala:87:24]
wire out_womask_556 = &_out_womask_T_556; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_556 = out_rivalid_1_410 & out_rimask_556; // @[RegisterRouter.scala:87:24]
wire _out_T_5649 = out_f_rivalid_556; // @[RegisterRouter.scala:87:24]
wire out_f_roready_556 = out_roready_1_410 & out_romask_556; // @[RegisterRouter.scala:87:24]
wire _out_T_5650 = out_f_roready_556; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_556 = out_wivalid_1_410 & out_wimask_556; // @[RegisterRouter.scala:87:24]
wire out_f_woready_556 = out_woready_1_410 & out_womask_556; // @[RegisterRouter.scala:87:24]
wire _out_T_5651 = ~out_rimask_556; // @[RegisterRouter.scala:87:24]
wire _out_T_5652 = ~out_wimask_556; // @[RegisterRouter.scala:87:24]
wire _out_T_5653 = ~out_romask_556; // @[RegisterRouter.scala:87:24]
wire _out_T_5654 = ~out_womask_556; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5656 = _out_T_5655; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_470 = _out_T_5656; // @[RegisterRouter.scala:87:24]
wire out_rimask_557 = |_out_rimask_T_557; // @[RegisterRouter.scala:87:24]
wire out_wimask_557 = &_out_wimask_T_557; // @[RegisterRouter.scala:87:24]
wire out_romask_557 = |_out_romask_T_557; // @[RegisterRouter.scala:87:24]
wire out_womask_557 = &_out_womask_T_557; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_557 = out_rivalid_1_411 & out_rimask_557; // @[RegisterRouter.scala:87:24]
wire _out_T_5658 = out_f_rivalid_557; // @[RegisterRouter.scala:87:24]
wire out_f_roready_557 = out_roready_1_411 & out_romask_557; // @[RegisterRouter.scala:87:24]
wire _out_T_5659 = out_f_roready_557; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_557 = out_wivalid_1_411 & out_wimask_557; // @[RegisterRouter.scala:87:24]
wire out_f_woready_557 = out_woready_1_411 & out_womask_557; // @[RegisterRouter.scala:87:24]
wire _out_T_5660 = ~out_rimask_557; // @[RegisterRouter.scala:87:24]
wire _out_T_5661 = ~out_wimask_557; // @[RegisterRouter.scala:87:24]
wire _out_T_5662 = ~out_romask_557; // @[RegisterRouter.scala:87:24]
wire _out_T_5663 = ~out_womask_557; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_470 = {hi_106, flags_0_go, _out_prepend_T_470}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_5664 = out_prepend_470; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_5665 = _out_T_5664; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_471 = _out_T_5665; // @[RegisterRouter.scala:87:24]
wire out_rimask_558 = |_out_rimask_T_558; // @[RegisterRouter.scala:87:24]
wire out_wimask_558 = &_out_wimask_T_558; // @[RegisterRouter.scala:87:24]
wire out_romask_558 = |_out_romask_T_558; // @[RegisterRouter.scala:87:24]
wire out_womask_558 = &_out_womask_T_558; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_558 = out_rivalid_1_412 & out_rimask_558; // @[RegisterRouter.scala:87:24]
wire _out_T_5667 = out_f_rivalid_558; // @[RegisterRouter.scala:87:24]
wire out_f_roready_558 = out_roready_1_412 & out_romask_558; // @[RegisterRouter.scala:87:24]
wire _out_T_5668 = out_f_roready_558; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_558 = out_wivalid_1_412 & out_wimask_558; // @[RegisterRouter.scala:87:24]
wire out_f_woready_558 = out_woready_1_412 & out_womask_558; // @[RegisterRouter.scala:87:24]
wire _out_T_5669 = ~out_rimask_558; // @[RegisterRouter.scala:87:24]
wire _out_T_5670 = ~out_wimask_558; // @[RegisterRouter.scala:87:24]
wire _out_T_5671 = ~out_romask_558; // @[RegisterRouter.scala:87:24]
wire _out_T_5672 = ~out_womask_558; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_471 = {hi_107, flags_0_go, _out_prepend_T_471}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_5673 = out_prepend_471; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_5674 = _out_T_5673; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_472 = _out_T_5674; // @[RegisterRouter.scala:87:24]
wire out_rimask_559 = |_out_rimask_T_559; // @[RegisterRouter.scala:87:24]
wire out_wimask_559 = &_out_wimask_T_559; // @[RegisterRouter.scala:87:24]
wire out_romask_559 = |_out_romask_T_559; // @[RegisterRouter.scala:87:24]
wire out_womask_559 = &_out_womask_T_559; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_559 = out_rivalid_1_413 & out_rimask_559; // @[RegisterRouter.scala:87:24]
wire _out_T_5676 = out_f_rivalid_559; // @[RegisterRouter.scala:87:24]
wire out_f_roready_559 = out_roready_1_413 & out_romask_559; // @[RegisterRouter.scala:87:24]
wire _out_T_5677 = out_f_roready_559; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_559 = out_wivalid_1_413 & out_wimask_559; // @[RegisterRouter.scala:87:24]
wire out_f_woready_559 = out_woready_1_413 & out_womask_559; // @[RegisterRouter.scala:87:24]
wire _out_T_5678 = ~out_rimask_559; // @[RegisterRouter.scala:87:24]
wire _out_T_5679 = ~out_wimask_559; // @[RegisterRouter.scala:87:24]
wire _out_T_5680 = ~out_romask_559; // @[RegisterRouter.scala:87:24]
wire _out_T_5681 = ~out_womask_559; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_472 = {hi_108, flags_0_go, _out_prepend_T_472}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_5682 = out_prepend_472; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_5683 = _out_T_5682; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_473 = _out_T_5683; // @[RegisterRouter.scala:87:24]
wire out_rimask_560 = |_out_rimask_T_560; // @[RegisterRouter.scala:87:24]
wire out_wimask_560 = &_out_wimask_T_560; // @[RegisterRouter.scala:87:24]
wire out_romask_560 = |_out_romask_T_560; // @[RegisterRouter.scala:87:24]
wire out_womask_560 = &_out_womask_T_560; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_560 = out_rivalid_1_414 & out_rimask_560; // @[RegisterRouter.scala:87:24]
wire _out_T_5685 = out_f_rivalid_560; // @[RegisterRouter.scala:87:24]
wire out_f_roready_560 = out_roready_1_414 & out_romask_560; // @[RegisterRouter.scala:87:24]
wire _out_T_5686 = out_f_roready_560; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_560 = out_wivalid_1_414 & out_wimask_560; // @[RegisterRouter.scala:87:24]
wire out_f_woready_560 = out_woready_1_414 & out_womask_560; // @[RegisterRouter.scala:87:24]
wire _out_T_5687 = ~out_rimask_560; // @[RegisterRouter.scala:87:24]
wire _out_T_5688 = ~out_wimask_560; // @[RegisterRouter.scala:87:24]
wire _out_T_5689 = ~out_romask_560; // @[RegisterRouter.scala:87:24]
wire _out_T_5690 = ~out_womask_560; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_473 = {hi_109, flags_0_go, _out_prepend_T_473}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_5691 = out_prepend_473; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_5692 = _out_T_5691; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_474 = _out_T_5692; // @[RegisterRouter.scala:87:24]
wire out_rimask_561 = |_out_rimask_T_561; // @[RegisterRouter.scala:87:24]
wire out_wimask_561 = &_out_wimask_T_561; // @[RegisterRouter.scala:87:24]
wire out_romask_561 = |_out_romask_T_561; // @[RegisterRouter.scala:87:24]
wire out_womask_561 = &_out_womask_T_561; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_561 = out_rivalid_1_415 & out_rimask_561; // @[RegisterRouter.scala:87:24]
wire _out_T_5694 = out_f_rivalid_561; // @[RegisterRouter.scala:87:24]
wire out_f_roready_561 = out_roready_1_415 & out_romask_561; // @[RegisterRouter.scala:87:24]
wire _out_T_5695 = out_f_roready_561; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_561 = out_wivalid_1_415 & out_wimask_561; // @[RegisterRouter.scala:87:24]
wire out_f_woready_561 = out_woready_1_415 & out_womask_561; // @[RegisterRouter.scala:87:24]
wire _out_T_5696 = ~out_rimask_561; // @[RegisterRouter.scala:87:24]
wire _out_T_5697 = ~out_wimask_561; // @[RegisterRouter.scala:87:24]
wire _out_T_5698 = ~out_romask_561; // @[RegisterRouter.scala:87:24]
wire _out_T_5699 = ~out_womask_561; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_474 = {hi_110, flags_0_go, _out_prepend_T_474}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_5700 = out_prepend_474; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_5701 = _out_T_5700; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_475 = _out_T_5701; // @[RegisterRouter.scala:87:24]
wire out_rimask_562 = |_out_rimask_T_562; // @[RegisterRouter.scala:87:24]
wire out_wimask_562 = &_out_wimask_T_562; // @[RegisterRouter.scala:87:24]
wire out_romask_562 = |_out_romask_T_562; // @[RegisterRouter.scala:87:24]
wire out_womask_562 = &_out_womask_T_562; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_562 = out_rivalid_1_416 & out_rimask_562; // @[RegisterRouter.scala:87:24]
wire _out_T_5703 = out_f_rivalid_562; // @[RegisterRouter.scala:87:24]
wire out_f_roready_562 = out_roready_1_416 & out_romask_562; // @[RegisterRouter.scala:87:24]
wire _out_T_5704 = out_f_roready_562; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_562 = out_wivalid_1_416 & out_wimask_562; // @[RegisterRouter.scala:87:24]
wire out_f_woready_562 = out_woready_1_416 & out_womask_562; // @[RegisterRouter.scala:87:24]
wire _out_T_5705 = ~out_rimask_562; // @[RegisterRouter.scala:87:24]
wire _out_T_5706 = ~out_wimask_562; // @[RegisterRouter.scala:87:24]
wire _out_T_5707 = ~out_romask_562; // @[RegisterRouter.scala:87:24]
wire _out_T_5708 = ~out_womask_562; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_475 = {hi_111, flags_0_go, _out_prepend_T_475}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_5709 = out_prepend_475; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_5710 = _out_T_5709; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_476 = _out_T_5710; // @[RegisterRouter.scala:87:24]
wire out_rimask_563 = |_out_rimask_T_563; // @[RegisterRouter.scala:87:24]
wire out_wimask_563 = &_out_wimask_T_563; // @[RegisterRouter.scala:87:24]
wire out_romask_563 = |_out_romask_T_563; // @[RegisterRouter.scala:87:24]
wire out_womask_563 = &_out_womask_T_563; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_563 = out_rivalid_1_417 & out_rimask_563; // @[RegisterRouter.scala:87:24]
wire _out_T_5712 = out_f_rivalid_563; // @[RegisterRouter.scala:87:24]
wire out_f_roready_563 = out_roready_1_417 & out_romask_563; // @[RegisterRouter.scala:87:24]
wire _out_T_5713 = out_f_roready_563; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_563 = out_wivalid_1_417 & out_wimask_563; // @[RegisterRouter.scala:87:24]
wire out_f_woready_563 = out_woready_1_417 & out_womask_563; // @[RegisterRouter.scala:87:24]
wire _out_T_5714 = ~out_rimask_563; // @[RegisterRouter.scala:87:24]
wire _out_T_5715 = ~out_wimask_563; // @[RegisterRouter.scala:87:24]
wire _out_T_5716 = ~out_romask_563; // @[RegisterRouter.scala:87:24]
wire _out_T_5717 = ~out_womask_563; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_476 = {hi_112, flags_0_go, _out_prepend_T_476}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_5718 = out_prepend_476; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_5719 = _out_T_5718; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_141 = _out_T_5719; // @[MuxLiteral.scala:49:48]
wire out_rimask_564 = |_out_rimask_T_564; // @[RegisterRouter.scala:87:24]
wire out_wimask_564 = &_out_wimask_T_564; // @[RegisterRouter.scala:87:24]
wire out_romask_564 = |_out_romask_T_564; // @[RegisterRouter.scala:87:24]
wire out_womask_564 = &_out_womask_T_564; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_564 = out_rivalid_1_418 & out_rimask_564; // @[RegisterRouter.scala:87:24]
wire _out_T_5721 = out_f_rivalid_564; // @[RegisterRouter.scala:87:24]
wire out_f_roready_564 = out_roready_1_418 & out_romask_564; // @[RegisterRouter.scala:87:24]
wire _out_T_5722 = out_f_roready_564; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_564 = out_wivalid_1_418 & out_wimask_564; // @[RegisterRouter.scala:87:24]
wire out_f_woready_564 = out_woready_1_418 & out_womask_564; // @[RegisterRouter.scala:87:24]
wire _out_T_5723 = ~out_rimask_564; // @[RegisterRouter.scala:87:24]
wire _out_T_5724 = ~out_wimask_564; // @[RegisterRouter.scala:87:24]
wire _out_T_5725 = ~out_romask_564; // @[RegisterRouter.scala:87:24]
wire _out_T_5726 = ~out_womask_564; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5728 = _out_T_5727; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_477 = _out_T_5728; // @[RegisterRouter.scala:87:24]
wire out_rimask_565 = |_out_rimask_T_565; // @[RegisterRouter.scala:87:24]
wire out_wimask_565 = &_out_wimask_T_565; // @[RegisterRouter.scala:87:24]
wire out_romask_565 = |_out_romask_T_565; // @[RegisterRouter.scala:87:24]
wire out_womask_565 = &_out_womask_T_565; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_565 = out_rivalid_1_419 & out_rimask_565; // @[RegisterRouter.scala:87:24]
wire _out_T_5730 = out_f_rivalid_565; // @[RegisterRouter.scala:87:24]
wire out_f_roready_565 = out_roready_1_419 & out_romask_565; // @[RegisterRouter.scala:87:24]
wire _out_T_5731 = out_f_roready_565; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_565 = out_wivalid_1_419 & out_wimask_565; // @[RegisterRouter.scala:87:24]
wire out_f_woready_565 = out_woready_1_419 & out_womask_565; // @[RegisterRouter.scala:87:24]
wire _out_T_5732 = ~out_rimask_565; // @[RegisterRouter.scala:87:24]
wire _out_T_5733 = ~out_wimask_565; // @[RegisterRouter.scala:87:24]
wire _out_T_5734 = ~out_romask_565; // @[RegisterRouter.scala:87:24]
wire _out_T_5735 = ~out_womask_565; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_477 = {hi_778, flags_0_go, _out_prepend_T_477}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_5736 = out_prepend_477; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_5737 = _out_T_5736; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_478 = _out_T_5737; // @[RegisterRouter.scala:87:24]
wire out_rimask_566 = |_out_rimask_T_566; // @[RegisterRouter.scala:87:24]
wire out_wimask_566 = &_out_wimask_T_566; // @[RegisterRouter.scala:87:24]
wire out_romask_566 = |_out_romask_T_566; // @[RegisterRouter.scala:87:24]
wire out_womask_566 = &_out_womask_T_566; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_566 = out_rivalid_1_420 & out_rimask_566; // @[RegisterRouter.scala:87:24]
wire _out_T_5739 = out_f_rivalid_566; // @[RegisterRouter.scala:87:24]
wire out_f_roready_566 = out_roready_1_420 & out_romask_566; // @[RegisterRouter.scala:87:24]
wire _out_T_5740 = out_f_roready_566; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_566 = out_wivalid_1_420 & out_wimask_566; // @[RegisterRouter.scala:87:24]
wire out_f_woready_566 = out_woready_1_420 & out_womask_566; // @[RegisterRouter.scala:87:24]
wire _out_T_5741 = ~out_rimask_566; // @[RegisterRouter.scala:87:24]
wire _out_T_5742 = ~out_wimask_566; // @[RegisterRouter.scala:87:24]
wire _out_T_5743 = ~out_romask_566; // @[RegisterRouter.scala:87:24]
wire _out_T_5744 = ~out_womask_566; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_478 = {hi_779, flags_0_go, _out_prepend_T_478}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_5745 = out_prepend_478; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_5746 = _out_T_5745; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_479 = _out_T_5746; // @[RegisterRouter.scala:87:24]
wire out_rimask_567 = |_out_rimask_T_567; // @[RegisterRouter.scala:87:24]
wire out_wimask_567 = &_out_wimask_T_567; // @[RegisterRouter.scala:87:24]
wire out_romask_567 = |_out_romask_T_567; // @[RegisterRouter.scala:87:24]
wire out_womask_567 = &_out_womask_T_567; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_567 = out_rivalid_1_421 & out_rimask_567; // @[RegisterRouter.scala:87:24]
wire _out_T_5748 = out_f_rivalid_567; // @[RegisterRouter.scala:87:24]
wire out_f_roready_567 = out_roready_1_421 & out_romask_567; // @[RegisterRouter.scala:87:24]
wire _out_T_5749 = out_f_roready_567; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_567 = out_wivalid_1_421 & out_wimask_567; // @[RegisterRouter.scala:87:24]
wire out_f_woready_567 = out_woready_1_421 & out_womask_567; // @[RegisterRouter.scala:87:24]
wire _out_T_5750 = ~out_rimask_567; // @[RegisterRouter.scala:87:24]
wire _out_T_5751 = ~out_wimask_567; // @[RegisterRouter.scala:87:24]
wire _out_T_5752 = ~out_romask_567; // @[RegisterRouter.scala:87:24]
wire _out_T_5753 = ~out_womask_567; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_479 = {hi_780, flags_0_go, _out_prepend_T_479}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_5754 = out_prepend_479; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_5755 = _out_T_5754; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_480 = _out_T_5755; // @[RegisterRouter.scala:87:24]
wire out_rimask_568 = |_out_rimask_T_568; // @[RegisterRouter.scala:87:24]
wire out_wimask_568 = &_out_wimask_T_568; // @[RegisterRouter.scala:87:24]
wire out_romask_568 = |_out_romask_T_568; // @[RegisterRouter.scala:87:24]
wire out_womask_568 = &_out_womask_T_568; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_568 = out_rivalid_1_422 & out_rimask_568; // @[RegisterRouter.scala:87:24]
wire _out_T_5757 = out_f_rivalid_568; // @[RegisterRouter.scala:87:24]
wire out_f_roready_568 = out_roready_1_422 & out_romask_568; // @[RegisterRouter.scala:87:24]
wire _out_T_5758 = out_f_roready_568; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_568 = out_wivalid_1_422 & out_wimask_568; // @[RegisterRouter.scala:87:24]
wire out_f_woready_568 = out_woready_1_422 & out_womask_568; // @[RegisterRouter.scala:87:24]
wire _out_T_5759 = ~out_rimask_568; // @[RegisterRouter.scala:87:24]
wire _out_T_5760 = ~out_wimask_568; // @[RegisterRouter.scala:87:24]
wire _out_T_5761 = ~out_romask_568; // @[RegisterRouter.scala:87:24]
wire _out_T_5762 = ~out_womask_568; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_480 = {hi_781, flags_0_go, _out_prepend_T_480}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_5763 = out_prepend_480; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_5764 = _out_T_5763; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_481 = _out_T_5764; // @[RegisterRouter.scala:87:24]
wire out_rimask_569 = |_out_rimask_T_569; // @[RegisterRouter.scala:87:24]
wire out_wimask_569 = &_out_wimask_T_569; // @[RegisterRouter.scala:87:24]
wire out_romask_569 = |_out_romask_T_569; // @[RegisterRouter.scala:87:24]
wire out_womask_569 = &_out_womask_T_569; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_569 = out_rivalid_1_423 & out_rimask_569; // @[RegisterRouter.scala:87:24]
wire _out_T_5766 = out_f_rivalid_569; // @[RegisterRouter.scala:87:24]
wire out_f_roready_569 = out_roready_1_423 & out_romask_569; // @[RegisterRouter.scala:87:24]
wire _out_T_5767 = out_f_roready_569; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_569 = out_wivalid_1_423 & out_wimask_569; // @[RegisterRouter.scala:87:24]
wire out_f_woready_569 = out_woready_1_423 & out_womask_569; // @[RegisterRouter.scala:87:24]
wire _out_T_5768 = ~out_rimask_569; // @[RegisterRouter.scala:87:24]
wire _out_T_5769 = ~out_wimask_569; // @[RegisterRouter.scala:87:24]
wire _out_T_5770 = ~out_romask_569; // @[RegisterRouter.scala:87:24]
wire _out_T_5771 = ~out_womask_569; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_481 = {hi_782, flags_0_go, _out_prepend_T_481}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_5772 = out_prepend_481; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_5773 = _out_T_5772; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_482 = _out_T_5773; // @[RegisterRouter.scala:87:24]
wire out_rimask_570 = |_out_rimask_T_570; // @[RegisterRouter.scala:87:24]
wire out_wimask_570 = &_out_wimask_T_570; // @[RegisterRouter.scala:87:24]
wire out_romask_570 = |_out_romask_T_570; // @[RegisterRouter.scala:87:24]
wire out_womask_570 = &_out_womask_T_570; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_570 = out_rivalid_1_424 & out_rimask_570; // @[RegisterRouter.scala:87:24]
wire _out_T_5775 = out_f_rivalid_570; // @[RegisterRouter.scala:87:24]
wire out_f_roready_570 = out_roready_1_424 & out_romask_570; // @[RegisterRouter.scala:87:24]
wire _out_T_5776 = out_f_roready_570; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_570 = out_wivalid_1_424 & out_wimask_570; // @[RegisterRouter.scala:87:24]
wire out_f_woready_570 = out_woready_1_424 & out_womask_570; // @[RegisterRouter.scala:87:24]
wire _out_T_5777 = ~out_rimask_570; // @[RegisterRouter.scala:87:24]
wire _out_T_5778 = ~out_wimask_570; // @[RegisterRouter.scala:87:24]
wire _out_T_5779 = ~out_romask_570; // @[RegisterRouter.scala:87:24]
wire _out_T_5780 = ~out_womask_570; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_482 = {hi_783, flags_0_go, _out_prepend_T_482}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_5781 = out_prepend_482; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_5782 = _out_T_5781; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_483 = _out_T_5782; // @[RegisterRouter.scala:87:24]
wire out_rimask_571 = |_out_rimask_T_571; // @[RegisterRouter.scala:87:24]
wire out_wimask_571 = &_out_wimask_T_571; // @[RegisterRouter.scala:87:24]
wire out_romask_571 = |_out_romask_T_571; // @[RegisterRouter.scala:87:24]
wire out_womask_571 = &_out_womask_T_571; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_571 = out_rivalid_1_425 & out_rimask_571; // @[RegisterRouter.scala:87:24]
wire _out_T_5784 = out_f_rivalid_571; // @[RegisterRouter.scala:87:24]
wire out_f_roready_571 = out_roready_1_425 & out_romask_571; // @[RegisterRouter.scala:87:24]
wire _out_T_5785 = out_f_roready_571; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_571 = out_wivalid_1_425 & out_wimask_571; // @[RegisterRouter.scala:87:24]
wire out_f_woready_571 = out_woready_1_425 & out_womask_571; // @[RegisterRouter.scala:87:24]
wire _out_T_5786 = ~out_rimask_571; // @[RegisterRouter.scala:87:24]
wire _out_T_5787 = ~out_wimask_571; // @[RegisterRouter.scala:87:24]
wire _out_T_5788 = ~out_romask_571; // @[RegisterRouter.scala:87:24]
wire _out_T_5789 = ~out_womask_571; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_483 = {hi_784, flags_0_go, _out_prepend_T_483}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_5790 = out_prepend_483; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_5791 = _out_T_5790; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_225 = _out_T_5791; // @[MuxLiteral.scala:49:48]
wire out_rimask_572 = |_out_rimask_T_572; // @[RegisterRouter.scala:87:24]
wire out_wimask_572 = &_out_wimask_T_572; // @[RegisterRouter.scala:87:24]
wire out_romask_572 = |_out_romask_T_572; // @[RegisterRouter.scala:87:24]
wire out_womask_572 = &_out_womask_T_572; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_572 = out_rivalid_1_426 & out_rimask_572; // @[RegisterRouter.scala:87:24]
wire _out_T_5793 = out_f_rivalid_572; // @[RegisterRouter.scala:87:24]
wire out_f_roready_572 = out_roready_1_426 & out_romask_572; // @[RegisterRouter.scala:87:24]
wire _out_T_5794 = out_f_roready_572; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_572 = out_wivalid_1_426 & out_wimask_572; // @[RegisterRouter.scala:87:24]
wire out_f_woready_572 = out_woready_1_426 & out_womask_572; // @[RegisterRouter.scala:87:24]
wire _out_T_5795 = ~out_rimask_572; // @[RegisterRouter.scala:87:24]
wire _out_T_5796 = ~out_wimask_572; // @[RegisterRouter.scala:87:24]
wire _out_T_5797 = ~out_romask_572; // @[RegisterRouter.scala:87:24]
wire _out_T_5798 = ~out_womask_572; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5800 = _out_T_5799; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_484 = _out_T_5800; // @[RegisterRouter.scala:87:24]
wire out_rimask_573 = |_out_rimask_T_573; // @[RegisterRouter.scala:87:24]
wire out_wimask_573 = &_out_wimask_T_573; // @[RegisterRouter.scala:87:24]
wire out_romask_573 = |_out_romask_T_573; // @[RegisterRouter.scala:87:24]
wire out_womask_573 = &_out_womask_T_573; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_573 = out_rivalid_1_427 & out_rimask_573; // @[RegisterRouter.scala:87:24]
wire _out_T_5802 = out_f_rivalid_573; // @[RegisterRouter.scala:87:24]
wire out_f_roready_573 = out_roready_1_427 & out_romask_573; // @[RegisterRouter.scala:87:24]
wire _out_T_5803 = out_f_roready_573; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_573 = out_wivalid_1_427 & out_wimask_573; // @[RegisterRouter.scala:87:24]
wire out_f_woready_573 = out_woready_1_427 & out_womask_573; // @[RegisterRouter.scala:87:24]
wire _out_T_5804 = ~out_rimask_573; // @[RegisterRouter.scala:87:24]
wire _out_T_5805 = ~out_wimask_573; // @[RegisterRouter.scala:87:24]
wire _out_T_5806 = ~out_romask_573; // @[RegisterRouter.scala:87:24]
wire _out_T_5807 = ~out_womask_573; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_484 = {hi_522, flags_0_go, _out_prepend_T_484}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_5808 = out_prepend_484; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_5809 = _out_T_5808; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_485 = _out_T_5809; // @[RegisterRouter.scala:87:24]
wire out_rimask_574 = |_out_rimask_T_574; // @[RegisterRouter.scala:87:24]
wire out_wimask_574 = &_out_wimask_T_574; // @[RegisterRouter.scala:87:24]
wire out_romask_574 = |_out_romask_T_574; // @[RegisterRouter.scala:87:24]
wire out_womask_574 = &_out_womask_T_574; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_574 = out_rivalid_1_428 & out_rimask_574; // @[RegisterRouter.scala:87:24]
wire _out_T_5811 = out_f_rivalid_574; // @[RegisterRouter.scala:87:24]
wire out_f_roready_574 = out_roready_1_428 & out_romask_574; // @[RegisterRouter.scala:87:24]
wire _out_T_5812 = out_f_roready_574; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_574 = out_wivalid_1_428 & out_wimask_574; // @[RegisterRouter.scala:87:24]
wire out_f_woready_574 = out_woready_1_428 & out_womask_574; // @[RegisterRouter.scala:87:24]
wire _out_T_5813 = ~out_rimask_574; // @[RegisterRouter.scala:87:24]
wire _out_T_5814 = ~out_wimask_574; // @[RegisterRouter.scala:87:24]
wire _out_T_5815 = ~out_romask_574; // @[RegisterRouter.scala:87:24]
wire _out_T_5816 = ~out_womask_574; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_485 = {hi_523, flags_0_go, _out_prepend_T_485}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_5817 = out_prepend_485; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_5818 = _out_T_5817; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_486 = _out_T_5818; // @[RegisterRouter.scala:87:24]
wire out_rimask_575 = |_out_rimask_T_575; // @[RegisterRouter.scala:87:24]
wire out_wimask_575 = &_out_wimask_T_575; // @[RegisterRouter.scala:87:24]
wire out_romask_575 = |_out_romask_T_575; // @[RegisterRouter.scala:87:24]
wire out_womask_575 = &_out_womask_T_575; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_575 = out_rivalid_1_429 & out_rimask_575; // @[RegisterRouter.scala:87:24]
wire _out_T_5820 = out_f_rivalid_575; // @[RegisterRouter.scala:87:24]
wire out_f_roready_575 = out_roready_1_429 & out_romask_575; // @[RegisterRouter.scala:87:24]
wire _out_T_5821 = out_f_roready_575; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_575 = out_wivalid_1_429 & out_wimask_575; // @[RegisterRouter.scala:87:24]
wire out_f_woready_575 = out_woready_1_429 & out_womask_575; // @[RegisterRouter.scala:87:24]
wire _out_T_5822 = ~out_rimask_575; // @[RegisterRouter.scala:87:24]
wire _out_T_5823 = ~out_wimask_575; // @[RegisterRouter.scala:87:24]
wire _out_T_5824 = ~out_romask_575; // @[RegisterRouter.scala:87:24]
wire _out_T_5825 = ~out_womask_575; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_486 = {hi_524, flags_0_go, _out_prepend_T_486}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_5826 = out_prepend_486; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_5827 = _out_T_5826; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_487 = _out_T_5827; // @[RegisterRouter.scala:87:24]
wire out_rimask_576 = |_out_rimask_T_576; // @[RegisterRouter.scala:87:24]
wire out_wimask_576 = &_out_wimask_T_576; // @[RegisterRouter.scala:87:24]
wire out_romask_576 = |_out_romask_T_576; // @[RegisterRouter.scala:87:24]
wire out_womask_576 = &_out_womask_T_576; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_576 = out_rivalid_1_430 & out_rimask_576; // @[RegisterRouter.scala:87:24]
wire _out_T_5829 = out_f_rivalid_576; // @[RegisterRouter.scala:87:24]
wire out_f_roready_576 = out_roready_1_430 & out_romask_576; // @[RegisterRouter.scala:87:24]
wire _out_T_5830 = out_f_roready_576; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_576 = out_wivalid_1_430 & out_wimask_576; // @[RegisterRouter.scala:87:24]
wire out_f_woready_576 = out_woready_1_430 & out_womask_576; // @[RegisterRouter.scala:87:24]
wire _out_T_5831 = ~out_rimask_576; // @[RegisterRouter.scala:87:24]
wire _out_T_5832 = ~out_wimask_576; // @[RegisterRouter.scala:87:24]
wire _out_T_5833 = ~out_romask_576; // @[RegisterRouter.scala:87:24]
wire _out_T_5834 = ~out_womask_576; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_487 = {hi_525, flags_0_go, _out_prepend_T_487}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_5835 = out_prepend_487; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_5836 = _out_T_5835; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_488 = _out_T_5836; // @[RegisterRouter.scala:87:24]
wire out_rimask_577 = |_out_rimask_T_577; // @[RegisterRouter.scala:87:24]
wire out_wimask_577 = &_out_wimask_T_577; // @[RegisterRouter.scala:87:24]
wire out_romask_577 = |_out_romask_T_577; // @[RegisterRouter.scala:87:24]
wire out_womask_577 = &_out_womask_T_577; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_577 = out_rivalid_1_431 & out_rimask_577; // @[RegisterRouter.scala:87:24]
wire _out_T_5838 = out_f_rivalid_577; // @[RegisterRouter.scala:87:24]
wire out_f_roready_577 = out_roready_1_431 & out_romask_577; // @[RegisterRouter.scala:87:24]
wire _out_T_5839 = out_f_roready_577; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_577 = out_wivalid_1_431 & out_wimask_577; // @[RegisterRouter.scala:87:24]
wire out_f_woready_577 = out_woready_1_431 & out_womask_577; // @[RegisterRouter.scala:87:24]
wire _out_T_5840 = ~out_rimask_577; // @[RegisterRouter.scala:87:24]
wire _out_T_5841 = ~out_wimask_577; // @[RegisterRouter.scala:87:24]
wire _out_T_5842 = ~out_romask_577; // @[RegisterRouter.scala:87:24]
wire _out_T_5843 = ~out_womask_577; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_488 = {hi_526, flags_0_go, _out_prepend_T_488}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_5844 = out_prepend_488; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_5845 = _out_T_5844; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_489 = _out_T_5845; // @[RegisterRouter.scala:87:24]
wire out_rimask_578 = |_out_rimask_T_578; // @[RegisterRouter.scala:87:24]
wire out_wimask_578 = &_out_wimask_T_578; // @[RegisterRouter.scala:87:24]
wire out_romask_578 = |_out_romask_T_578; // @[RegisterRouter.scala:87:24]
wire out_womask_578 = &_out_womask_T_578; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_578 = out_rivalid_1_432 & out_rimask_578; // @[RegisterRouter.scala:87:24]
wire _out_T_5847 = out_f_rivalid_578; // @[RegisterRouter.scala:87:24]
wire out_f_roready_578 = out_roready_1_432 & out_romask_578; // @[RegisterRouter.scala:87:24]
wire _out_T_5848 = out_f_roready_578; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_578 = out_wivalid_1_432 & out_wimask_578; // @[RegisterRouter.scala:87:24]
wire out_f_woready_578 = out_woready_1_432 & out_womask_578; // @[RegisterRouter.scala:87:24]
wire _out_T_5849 = ~out_rimask_578; // @[RegisterRouter.scala:87:24]
wire _out_T_5850 = ~out_wimask_578; // @[RegisterRouter.scala:87:24]
wire _out_T_5851 = ~out_romask_578; // @[RegisterRouter.scala:87:24]
wire _out_T_5852 = ~out_womask_578; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_489 = {hi_527, flags_0_go, _out_prepend_T_489}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_5853 = out_prepend_489; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_5854 = _out_T_5853; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_490 = _out_T_5854; // @[RegisterRouter.scala:87:24]
wire out_rimask_579 = |_out_rimask_T_579; // @[RegisterRouter.scala:87:24]
wire out_wimask_579 = &_out_wimask_T_579; // @[RegisterRouter.scala:87:24]
wire out_romask_579 = |_out_romask_T_579; // @[RegisterRouter.scala:87:24]
wire out_womask_579 = &_out_womask_T_579; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_579 = out_rivalid_1_433 & out_rimask_579; // @[RegisterRouter.scala:87:24]
wire _out_T_5856 = out_f_rivalid_579; // @[RegisterRouter.scala:87:24]
wire out_f_roready_579 = out_roready_1_433 & out_romask_579; // @[RegisterRouter.scala:87:24]
wire _out_T_5857 = out_f_roready_579; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_579 = out_wivalid_1_433 & out_wimask_579; // @[RegisterRouter.scala:87:24]
wire out_f_woready_579 = out_woready_1_433 & out_womask_579; // @[RegisterRouter.scala:87:24]
wire _out_T_5858 = ~out_rimask_579; // @[RegisterRouter.scala:87:24]
wire _out_T_5859 = ~out_wimask_579; // @[RegisterRouter.scala:87:24]
wire _out_T_5860 = ~out_romask_579; // @[RegisterRouter.scala:87:24]
wire _out_T_5861 = ~out_womask_579; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_490 = {hi_528, flags_0_go, _out_prepend_T_490}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_5862 = out_prepend_490; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_5863 = _out_T_5862; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_193 = _out_T_5863; // @[MuxLiteral.scala:49:48]
wire out_rimask_580 = |_out_rimask_T_580; // @[RegisterRouter.scala:87:24]
wire out_wimask_580 = &_out_wimask_T_580; // @[RegisterRouter.scala:87:24]
wire out_romask_580 = |_out_romask_T_580; // @[RegisterRouter.scala:87:24]
wire out_womask_580 = &_out_womask_T_580; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_580 = out_rivalid_1_434 & out_rimask_580; // @[RegisterRouter.scala:87:24]
wire _out_T_5865 = out_f_rivalid_580; // @[RegisterRouter.scala:87:24]
wire out_f_roready_580 = out_roready_1_434 & out_romask_580; // @[RegisterRouter.scala:87:24]
wire _out_T_5866 = out_f_roready_580; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_580 = out_wivalid_1_434 & out_wimask_580; // @[RegisterRouter.scala:87:24]
wire out_f_woready_580 = out_woready_1_434 & out_womask_580; // @[RegisterRouter.scala:87:24]
wire _out_T_5867 = ~out_rimask_580; // @[RegisterRouter.scala:87:24]
wire _out_T_5868 = ~out_wimask_580; // @[RegisterRouter.scala:87:24]
wire _out_T_5869 = ~out_romask_580; // @[RegisterRouter.scala:87:24]
wire _out_T_5870 = ~out_womask_580; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5872 = _out_T_5871; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_491 = _out_T_5872; // @[RegisterRouter.scala:87:24]
wire out_rimask_581 = |_out_rimask_T_581; // @[RegisterRouter.scala:87:24]
wire out_wimask_581 = &_out_wimask_T_581; // @[RegisterRouter.scala:87:24]
wire out_romask_581 = |_out_romask_T_581; // @[RegisterRouter.scala:87:24]
wire out_womask_581 = &_out_womask_T_581; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_581 = out_rivalid_1_435 & out_rimask_581; // @[RegisterRouter.scala:87:24]
wire _out_T_5874 = out_f_rivalid_581; // @[RegisterRouter.scala:87:24]
wire out_f_roready_581 = out_roready_1_435 & out_romask_581; // @[RegisterRouter.scala:87:24]
wire _out_T_5875 = out_f_roready_581; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_581 = out_wivalid_1_435 & out_wimask_581; // @[RegisterRouter.scala:87:24]
wire out_f_woready_581 = out_woready_1_435 & out_womask_581; // @[RegisterRouter.scala:87:24]
wire _out_T_5876 = ~out_rimask_581; // @[RegisterRouter.scala:87:24]
wire _out_T_5877 = ~out_wimask_581; // @[RegisterRouter.scala:87:24]
wire _out_T_5878 = ~out_romask_581; // @[RegisterRouter.scala:87:24]
wire _out_T_5879 = ~out_womask_581; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_491 = {hi_674, flags_0_go, _out_prepend_T_491}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_5880 = out_prepend_491; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_5881 = _out_T_5880; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_492 = _out_T_5881; // @[RegisterRouter.scala:87:24]
wire out_rimask_582 = |_out_rimask_T_582; // @[RegisterRouter.scala:87:24]
wire out_wimask_582 = &_out_wimask_T_582; // @[RegisterRouter.scala:87:24]
wire out_romask_582 = |_out_romask_T_582; // @[RegisterRouter.scala:87:24]
wire out_womask_582 = &_out_womask_T_582; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_582 = out_rivalid_1_436 & out_rimask_582; // @[RegisterRouter.scala:87:24]
wire _out_T_5883 = out_f_rivalid_582; // @[RegisterRouter.scala:87:24]
wire out_f_roready_582 = out_roready_1_436 & out_romask_582; // @[RegisterRouter.scala:87:24]
wire _out_T_5884 = out_f_roready_582; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_582 = out_wivalid_1_436 & out_wimask_582; // @[RegisterRouter.scala:87:24]
wire out_f_woready_582 = out_woready_1_436 & out_womask_582; // @[RegisterRouter.scala:87:24]
wire _out_T_5885 = ~out_rimask_582; // @[RegisterRouter.scala:87:24]
wire _out_T_5886 = ~out_wimask_582; // @[RegisterRouter.scala:87:24]
wire _out_T_5887 = ~out_romask_582; // @[RegisterRouter.scala:87:24]
wire _out_T_5888 = ~out_womask_582; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_492 = {hi_675, flags_0_go, _out_prepend_T_492}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_5889 = out_prepend_492; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_5890 = _out_T_5889; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_493 = _out_T_5890; // @[RegisterRouter.scala:87:24]
wire out_rimask_583 = |_out_rimask_T_583; // @[RegisterRouter.scala:87:24]
wire out_wimask_583 = &_out_wimask_T_583; // @[RegisterRouter.scala:87:24]
wire out_romask_583 = |_out_romask_T_583; // @[RegisterRouter.scala:87:24]
wire out_womask_583 = &_out_womask_T_583; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_583 = out_rivalid_1_437 & out_rimask_583; // @[RegisterRouter.scala:87:24]
wire _out_T_5892 = out_f_rivalid_583; // @[RegisterRouter.scala:87:24]
wire out_f_roready_583 = out_roready_1_437 & out_romask_583; // @[RegisterRouter.scala:87:24]
wire _out_T_5893 = out_f_roready_583; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_583 = out_wivalid_1_437 & out_wimask_583; // @[RegisterRouter.scala:87:24]
wire out_f_woready_583 = out_woready_1_437 & out_womask_583; // @[RegisterRouter.scala:87:24]
wire _out_T_5894 = ~out_rimask_583; // @[RegisterRouter.scala:87:24]
wire _out_T_5895 = ~out_wimask_583; // @[RegisterRouter.scala:87:24]
wire _out_T_5896 = ~out_romask_583; // @[RegisterRouter.scala:87:24]
wire _out_T_5897 = ~out_womask_583; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_493 = {hi_676, flags_0_go, _out_prepend_T_493}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_5898 = out_prepend_493; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_5899 = _out_T_5898; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_494 = _out_T_5899; // @[RegisterRouter.scala:87:24]
wire out_rimask_584 = |_out_rimask_T_584; // @[RegisterRouter.scala:87:24]
wire out_wimask_584 = &_out_wimask_T_584; // @[RegisterRouter.scala:87:24]
wire out_romask_584 = |_out_romask_T_584; // @[RegisterRouter.scala:87:24]
wire out_womask_584 = &_out_womask_T_584; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_584 = out_rivalid_1_438 & out_rimask_584; // @[RegisterRouter.scala:87:24]
wire _out_T_5901 = out_f_rivalid_584; // @[RegisterRouter.scala:87:24]
wire out_f_roready_584 = out_roready_1_438 & out_romask_584; // @[RegisterRouter.scala:87:24]
wire _out_T_5902 = out_f_roready_584; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_584 = out_wivalid_1_438 & out_wimask_584; // @[RegisterRouter.scala:87:24]
wire out_f_woready_584 = out_woready_1_438 & out_womask_584; // @[RegisterRouter.scala:87:24]
wire _out_T_5903 = ~out_rimask_584; // @[RegisterRouter.scala:87:24]
wire _out_T_5904 = ~out_wimask_584; // @[RegisterRouter.scala:87:24]
wire _out_T_5905 = ~out_romask_584; // @[RegisterRouter.scala:87:24]
wire _out_T_5906 = ~out_womask_584; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_494 = {hi_677, flags_0_go, _out_prepend_T_494}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_5907 = out_prepend_494; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_5908 = _out_T_5907; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_495 = _out_T_5908; // @[RegisterRouter.scala:87:24]
wire out_rimask_585 = |_out_rimask_T_585; // @[RegisterRouter.scala:87:24]
wire out_wimask_585 = &_out_wimask_T_585; // @[RegisterRouter.scala:87:24]
wire out_romask_585 = |_out_romask_T_585; // @[RegisterRouter.scala:87:24]
wire out_womask_585 = &_out_womask_T_585; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_585 = out_rivalid_1_439 & out_rimask_585; // @[RegisterRouter.scala:87:24]
wire _out_T_5910 = out_f_rivalid_585; // @[RegisterRouter.scala:87:24]
wire out_f_roready_585 = out_roready_1_439 & out_romask_585; // @[RegisterRouter.scala:87:24]
wire _out_T_5911 = out_f_roready_585; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_585 = out_wivalid_1_439 & out_wimask_585; // @[RegisterRouter.scala:87:24]
wire out_f_woready_585 = out_woready_1_439 & out_womask_585; // @[RegisterRouter.scala:87:24]
wire _out_T_5912 = ~out_rimask_585; // @[RegisterRouter.scala:87:24]
wire _out_T_5913 = ~out_wimask_585; // @[RegisterRouter.scala:87:24]
wire _out_T_5914 = ~out_romask_585; // @[RegisterRouter.scala:87:24]
wire _out_T_5915 = ~out_womask_585; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_495 = {hi_678, flags_0_go, _out_prepend_T_495}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_5916 = out_prepend_495; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_5917 = _out_T_5916; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_496 = _out_T_5917; // @[RegisterRouter.scala:87:24]
wire out_rimask_586 = |_out_rimask_T_586; // @[RegisterRouter.scala:87:24]
wire out_wimask_586 = &_out_wimask_T_586; // @[RegisterRouter.scala:87:24]
wire out_romask_586 = |_out_romask_T_586; // @[RegisterRouter.scala:87:24]
wire out_womask_586 = &_out_womask_T_586; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_586 = out_rivalid_1_440 & out_rimask_586; // @[RegisterRouter.scala:87:24]
wire _out_T_5919 = out_f_rivalid_586; // @[RegisterRouter.scala:87:24]
wire out_f_roready_586 = out_roready_1_440 & out_romask_586; // @[RegisterRouter.scala:87:24]
wire _out_T_5920 = out_f_roready_586; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_586 = out_wivalid_1_440 & out_wimask_586; // @[RegisterRouter.scala:87:24]
wire out_f_woready_586 = out_woready_1_440 & out_womask_586; // @[RegisterRouter.scala:87:24]
wire _out_T_5921 = ~out_rimask_586; // @[RegisterRouter.scala:87:24]
wire _out_T_5922 = ~out_wimask_586; // @[RegisterRouter.scala:87:24]
wire _out_T_5923 = ~out_romask_586; // @[RegisterRouter.scala:87:24]
wire _out_T_5924 = ~out_womask_586; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_496 = {hi_679, flags_0_go, _out_prepend_T_496}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_5925 = out_prepend_496; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_5926 = _out_T_5925; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_497 = _out_T_5926; // @[RegisterRouter.scala:87:24]
wire out_rimask_587 = |_out_rimask_T_587; // @[RegisterRouter.scala:87:24]
wire out_wimask_587 = &_out_wimask_T_587; // @[RegisterRouter.scala:87:24]
wire out_romask_587 = |_out_romask_T_587; // @[RegisterRouter.scala:87:24]
wire out_womask_587 = &_out_womask_T_587; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_587 = out_rivalid_1_441 & out_rimask_587; // @[RegisterRouter.scala:87:24]
wire _out_T_5928 = out_f_rivalid_587; // @[RegisterRouter.scala:87:24]
wire out_f_roready_587 = out_roready_1_441 & out_romask_587; // @[RegisterRouter.scala:87:24]
wire _out_T_5929 = out_f_roready_587; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_587 = out_wivalid_1_441 & out_wimask_587; // @[RegisterRouter.scala:87:24]
wire out_f_woready_587 = out_woready_1_441 & out_womask_587; // @[RegisterRouter.scala:87:24]
wire _out_T_5930 = ~out_rimask_587; // @[RegisterRouter.scala:87:24]
wire _out_T_5931 = ~out_wimask_587; // @[RegisterRouter.scala:87:24]
wire _out_T_5932 = ~out_romask_587; // @[RegisterRouter.scala:87:24]
wire _out_T_5933 = ~out_womask_587; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_497 = {hi_680, flags_0_go, _out_prepend_T_497}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_5934 = out_prepend_497; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_5935 = _out_T_5934; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_212 = _out_T_5935; // @[MuxLiteral.scala:49:48]
wire [31:0] _out_rimask_T_588 = out_frontMask_1[31:0]; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_wimask_T_588 = out_frontMask_1[31:0]; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_rimask_T_843 = out_frontMask_1[31:0]; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_wimask_T_843 = out_frontMask_1[31:0]; // @[RegisterRouter.scala:87:24]
wire out_rimask_588 = |_out_rimask_T_588; // @[RegisterRouter.scala:87:24]
wire out_wimask_588 = &_out_wimask_T_588; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_romask_T_588 = out_backMask_1[31:0]; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_womask_T_588 = out_backMask_1[31:0]; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_romask_T_843 = out_backMask_1[31:0]; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_womask_T_843 = out_backMask_1[31:0]; // @[RegisterRouter.scala:87:24]
wire out_romask_588 = |_out_romask_T_588; // @[RegisterRouter.scala:87:24]
wire out_womask_588 = &_out_womask_T_588; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_588 = out_rivalid_1_442 & out_rimask_588; // @[RegisterRouter.scala:87:24]
wire _out_T_5937 = out_f_rivalid_588; // @[RegisterRouter.scala:87:24]
wire out_f_roready_588 = out_roready_1_442 & out_romask_588; // @[RegisterRouter.scala:87:24]
wire _out_T_5938 = out_f_roready_588; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_588 = out_wivalid_1_442 & out_wimask_588; // @[RegisterRouter.scala:87:24]
wire out_f_woready_588 = out_woready_1_442 & out_womask_588; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_5936 = out_front_1_bits_data[31:0]; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_8279 = out_front_1_bits_data[31:0]; // @[RegisterRouter.scala:87:24]
wire _out_T_5939 = ~out_rimask_588; // @[RegisterRouter.scala:87:24]
wire _out_T_5940 = ~out_wimask_588; // @[RegisterRouter.scala:87:24]
wire _out_T_5941 = ~out_romask_588; // @[RegisterRouter.scala:87:24]
wire _out_T_5942 = ~out_womask_588; // @[RegisterRouter.scala:87:24]
wire out_rimask_589 = |_out_rimask_T_589; // @[RegisterRouter.scala:87:24]
wire out_wimask_589 = &_out_wimask_T_589; // @[RegisterRouter.scala:87:24]
wire out_romask_589 = |_out_romask_T_589; // @[RegisterRouter.scala:87:24]
wire out_womask_589 = &_out_womask_T_589; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_589 = out_rivalid_1_443 & out_rimask_589; // @[RegisterRouter.scala:87:24]
wire _out_T_5946 = out_f_rivalid_589; // @[RegisterRouter.scala:87:24]
wire out_f_roready_589 = out_roready_1_443 & out_romask_589; // @[RegisterRouter.scala:87:24]
wire _out_T_5947 = out_f_roready_589; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_589 = out_wivalid_1_443 & out_wimask_589; // @[RegisterRouter.scala:87:24]
wire _out_T_5948 = out_f_wivalid_589; // @[RegisterRouter.scala:87:24]
wire out_f_woready_589 = out_woready_1_443 & out_womask_589; // @[RegisterRouter.scala:87:24]
wire _out_T_5949 = out_f_woready_589; // @[RegisterRouter.scala:87:24]
wire _out_T_5950 = ~out_rimask_589; // @[RegisterRouter.scala:87:24]
wire _out_T_5951 = ~out_wimask_589; // @[RegisterRouter.scala:87:24]
wire _out_T_5952 = ~out_romask_589; // @[RegisterRouter.scala:87:24]
wire _out_T_5953 = ~out_womask_589; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_5955 = _out_T_5954; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_498 = _out_T_5955; // @[RegisterRouter.scala:87:24]
wire out_rimask_590 = |_out_rimask_T_590; // @[RegisterRouter.scala:87:24]
wire out_wimask_590 = &_out_wimask_T_590; // @[RegisterRouter.scala:87:24]
wire out_romask_590 = |_out_romask_T_590; // @[RegisterRouter.scala:87:24]
wire out_womask_590 = &_out_womask_T_590; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_590 = out_rivalid_1_444 & out_rimask_590; // @[RegisterRouter.scala:87:24]
wire _out_T_5957 = out_f_rivalid_590; // @[RegisterRouter.scala:87:24]
wire out_f_roready_590 = out_roready_1_444 & out_romask_590; // @[RegisterRouter.scala:87:24]
wire _out_T_5958 = out_f_roready_590; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_590 = out_wivalid_1_444 & out_wimask_590; // @[RegisterRouter.scala:87:24]
wire _out_T_5959 = out_f_wivalid_590; // @[RegisterRouter.scala:87:24]
wire out_f_woready_590 = out_woready_1_444 & out_womask_590; // @[RegisterRouter.scala:87:24]
wire _out_T_5960 = out_f_woready_590; // @[RegisterRouter.scala:87:24]
wire _out_T_5961 = ~out_rimask_590; // @[RegisterRouter.scala:87:24]
wire _out_T_5962 = ~out_wimask_590; // @[RegisterRouter.scala:87:24]
wire _out_T_5963 = ~out_romask_590; // @[RegisterRouter.scala:87:24]
wire _out_T_5964 = ~out_womask_590; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_498 = {programBufferMem_41, _out_prepend_T_498}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_5965 = out_prepend_498; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_5966 = _out_T_5965; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_499 = _out_T_5966; // @[RegisterRouter.scala:87:24]
wire out_rimask_591 = |_out_rimask_T_591; // @[RegisterRouter.scala:87:24]
wire out_wimask_591 = &_out_wimask_T_591; // @[RegisterRouter.scala:87:24]
wire out_romask_591 = |_out_romask_T_591; // @[RegisterRouter.scala:87:24]
wire out_womask_591 = &_out_womask_T_591; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_591 = out_rivalid_1_445 & out_rimask_591; // @[RegisterRouter.scala:87:24]
wire _out_T_5968 = out_f_rivalid_591; // @[RegisterRouter.scala:87:24]
wire out_f_roready_591 = out_roready_1_445 & out_romask_591; // @[RegisterRouter.scala:87:24]
wire _out_T_5969 = out_f_roready_591; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_591 = out_wivalid_1_445 & out_wimask_591; // @[RegisterRouter.scala:87:24]
wire _out_T_5970 = out_f_wivalid_591; // @[RegisterRouter.scala:87:24]
wire out_f_woready_591 = out_woready_1_445 & out_womask_591; // @[RegisterRouter.scala:87:24]
wire _out_T_5971 = out_f_woready_591; // @[RegisterRouter.scala:87:24]
wire _out_T_5972 = ~out_rimask_591; // @[RegisterRouter.scala:87:24]
wire _out_T_5973 = ~out_wimask_591; // @[RegisterRouter.scala:87:24]
wire _out_T_5974 = ~out_romask_591; // @[RegisterRouter.scala:87:24]
wire _out_T_5975 = ~out_womask_591; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_499 = {programBufferMem_42, _out_prepend_T_499}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_5976 = out_prepend_499; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_5977 = _out_T_5976; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_500 = _out_T_5977; // @[RegisterRouter.scala:87:24]
wire out_rimask_592 = |_out_rimask_T_592; // @[RegisterRouter.scala:87:24]
wire out_wimask_592 = &_out_wimask_T_592; // @[RegisterRouter.scala:87:24]
wire out_romask_592 = |_out_romask_T_592; // @[RegisterRouter.scala:87:24]
wire out_womask_592 = &_out_womask_T_592; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_592 = out_rivalid_1_446 & out_rimask_592; // @[RegisterRouter.scala:87:24]
wire _out_T_5979 = out_f_rivalid_592; // @[RegisterRouter.scala:87:24]
wire out_f_roready_592 = out_roready_1_446 & out_romask_592; // @[RegisterRouter.scala:87:24]
wire _out_T_5980 = out_f_roready_592; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_592 = out_wivalid_1_446 & out_wimask_592; // @[RegisterRouter.scala:87:24]
wire _out_T_5981 = out_f_wivalid_592; // @[RegisterRouter.scala:87:24]
wire out_f_woready_592 = out_woready_1_446 & out_womask_592; // @[RegisterRouter.scala:87:24]
wire _out_T_5982 = out_f_woready_592; // @[RegisterRouter.scala:87:24]
wire _out_T_5983 = ~out_rimask_592; // @[RegisterRouter.scala:87:24]
wire _out_T_5984 = ~out_wimask_592; // @[RegisterRouter.scala:87:24]
wire _out_T_5985 = ~out_romask_592; // @[RegisterRouter.scala:87:24]
wire _out_T_5986 = ~out_womask_592; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_500 = {programBufferMem_43, _out_prepend_T_500}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_5987 = out_prepend_500; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_5988 = _out_T_5987; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_501 = _out_T_5988; // @[RegisterRouter.scala:87:24]
wire out_rimask_593 = |_out_rimask_T_593; // @[RegisterRouter.scala:87:24]
wire out_wimask_593 = &_out_wimask_T_593; // @[RegisterRouter.scala:87:24]
wire out_romask_593 = |_out_romask_T_593; // @[RegisterRouter.scala:87:24]
wire out_womask_593 = &_out_womask_T_593; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_593 = out_rivalid_1_447 & out_rimask_593; // @[RegisterRouter.scala:87:24]
wire _out_T_5990 = out_f_rivalid_593; // @[RegisterRouter.scala:87:24]
wire out_f_roready_593 = out_roready_1_447 & out_romask_593; // @[RegisterRouter.scala:87:24]
wire _out_T_5991 = out_f_roready_593; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_593 = out_wivalid_1_447 & out_wimask_593; // @[RegisterRouter.scala:87:24]
wire _out_T_5992 = out_f_wivalid_593; // @[RegisterRouter.scala:87:24]
wire out_f_woready_593 = out_woready_1_447 & out_womask_593; // @[RegisterRouter.scala:87:24]
wire _out_T_5993 = out_f_woready_593; // @[RegisterRouter.scala:87:24]
wire _out_T_5994 = ~out_rimask_593; // @[RegisterRouter.scala:87:24]
wire _out_T_5995 = ~out_wimask_593; // @[RegisterRouter.scala:87:24]
wire _out_T_5996 = ~out_romask_593; // @[RegisterRouter.scala:87:24]
wire _out_T_5997 = ~out_womask_593; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_501 = {programBufferMem_44, _out_prepend_T_501}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_5998 = out_prepend_501; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_5999 = _out_T_5998; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_502 = _out_T_5999; // @[RegisterRouter.scala:87:24]
wire out_rimask_594 = |_out_rimask_T_594; // @[RegisterRouter.scala:87:24]
wire out_wimask_594 = &_out_wimask_T_594; // @[RegisterRouter.scala:87:24]
wire out_romask_594 = |_out_romask_T_594; // @[RegisterRouter.scala:87:24]
wire out_womask_594 = &_out_womask_T_594; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_594 = out_rivalid_1_448 & out_rimask_594; // @[RegisterRouter.scala:87:24]
wire _out_T_6001 = out_f_rivalid_594; // @[RegisterRouter.scala:87:24]
wire out_f_roready_594 = out_roready_1_448 & out_romask_594; // @[RegisterRouter.scala:87:24]
wire _out_T_6002 = out_f_roready_594; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_594 = out_wivalid_1_448 & out_wimask_594; // @[RegisterRouter.scala:87:24]
wire _out_T_6003 = out_f_wivalid_594; // @[RegisterRouter.scala:87:24]
wire out_f_woready_594 = out_woready_1_448 & out_womask_594; // @[RegisterRouter.scala:87:24]
wire _out_T_6004 = out_f_woready_594; // @[RegisterRouter.scala:87:24]
wire _out_T_6005 = ~out_rimask_594; // @[RegisterRouter.scala:87:24]
wire _out_T_6006 = ~out_wimask_594; // @[RegisterRouter.scala:87:24]
wire _out_T_6007 = ~out_romask_594; // @[RegisterRouter.scala:87:24]
wire _out_T_6008 = ~out_womask_594; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_502 = {programBufferMem_45, _out_prepend_T_502}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_6009 = out_prepend_502; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_6010 = _out_T_6009; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_503 = _out_T_6010; // @[RegisterRouter.scala:87:24]
wire out_rimask_595 = |_out_rimask_T_595; // @[RegisterRouter.scala:87:24]
wire out_wimask_595 = &_out_wimask_T_595; // @[RegisterRouter.scala:87:24]
wire out_romask_595 = |_out_romask_T_595; // @[RegisterRouter.scala:87:24]
wire out_womask_595 = &_out_womask_T_595; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_595 = out_rivalid_1_449 & out_rimask_595; // @[RegisterRouter.scala:87:24]
wire _out_T_6012 = out_f_rivalid_595; // @[RegisterRouter.scala:87:24]
wire out_f_roready_595 = out_roready_1_449 & out_romask_595; // @[RegisterRouter.scala:87:24]
wire _out_T_6013 = out_f_roready_595; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_595 = out_wivalid_1_449 & out_wimask_595; // @[RegisterRouter.scala:87:24]
wire _out_T_6014 = out_f_wivalid_595; // @[RegisterRouter.scala:87:24]
wire out_f_woready_595 = out_woready_1_449 & out_womask_595; // @[RegisterRouter.scala:87:24]
wire _out_T_6015 = out_f_woready_595; // @[RegisterRouter.scala:87:24]
wire _out_T_6016 = ~out_rimask_595; // @[RegisterRouter.scala:87:24]
wire _out_T_6017 = ~out_wimask_595; // @[RegisterRouter.scala:87:24]
wire _out_T_6018 = ~out_romask_595; // @[RegisterRouter.scala:87:24]
wire _out_T_6019 = ~out_womask_595; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_503 = {programBufferMem_46, _out_prepend_T_503}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_6020 = out_prepend_503; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_6021 = _out_T_6020; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_504 = _out_T_6021; // @[RegisterRouter.scala:87:24]
wire out_rimask_596 = |_out_rimask_T_596; // @[RegisterRouter.scala:87:24]
wire out_wimask_596 = &_out_wimask_T_596; // @[RegisterRouter.scala:87:24]
wire out_romask_596 = |_out_romask_T_596; // @[RegisterRouter.scala:87:24]
wire out_womask_596 = &_out_womask_T_596; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_596 = out_rivalid_1_450 & out_rimask_596; // @[RegisterRouter.scala:87:24]
wire _out_T_6023 = out_f_rivalid_596; // @[RegisterRouter.scala:87:24]
wire out_f_roready_596 = out_roready_1_450 & out_romask_596; // @[RegisterRouter.scala:87:24]
wire _out_T_6024 = out_f_roready_596; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_596 = out_wivalid_1_450 & out_wimask_596; // @[RegisterRouter.scala:87:24]
wire _out_T_6025 = out_f_wivalid_596; // @[RegisterRouter.scala:87:24]
wire out_f_woready_596 = out_woready_1_450 & out_womask_596; // @[RegisterRouter.scala:87:24]
wire _out_T_6026 = out_f_woready_596; // @[RegisterRouter.scala:87:24]
wire _out_T_6027 = ~out_rimask_596; // @[RegisterRouter.scala:87:24]
wire _out_T_6028 = ~out_wimask_596; // @[RegisterRouter.scala:87:24]
wire _out_T_6029 = ~out_romask_596; // @[RegisterRouter.scala:87:24]
wire _out_T_6030 = ~out_womask_596; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_504 = {programBufferMem_47, _out_prepend_T_504}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_6031 = out_prepend_504; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_6032 = _out_T_6031; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_109 = _out_T_6032; // @[MuxLiteral.scala:49:48]
wire out_rimask_597 = |_out_rimask_T_597; // @[RegisterRouter.scala:87:24]
wire out_wimask_597 = &_out_wimask_T_597; // @[RegisterRouter.scala:87:24]
wire out_romask_597 = |_out_romask_T_597; // @[RegisterRouter.scala:87:24]
wire out_womask_597 = &_out_womask_T_597; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_597 = out_rivalid_1_451 & out_rimask_597; // @[RegisterRouter.scala:87:24]
wire _out_T_6034 = out_f_rivalid_597; // @[RegisterRouter.scala:87:24]
wire out_f_roready_597 = out_roready_1_451 & out_romask_597; // @[RegisterRouter.scala:87:24]
wire _out_T_6035 = out_f_roready_597; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_597 = out_wivalid_1_451 & out_wimask_597; // @[RegisterRouter.scala:87:24]
wire out_f_woready_597 = out_woready_1_451 & out_womask_597; // @[RegisterRouter.scala:87:24]
wire _out_T_6036 = ~out_rimask_597; // @[RegisterRouter.scala:87:24]
wire _out_T_6037 = ~out_wimask_597; // @[RegisterRouter.scala:87:24]
wire _out_T_6038 = ~out_romask_597; // @[RegisterRouter.scala:87:24]
wire _out_T_6039 = ~out_womask_597; // @[RegisterRouter.scala:87:24]
wire out_rimask_598 = |_out_rimask_T_598; // @[RegisterRouter.scala:87:24]
wire out_wimask_598 = &_out_wimask_T_598; // @[RegisterRouter.scala:87:24]
wire out_romask_598 = |_out_romask_T_598; // @[RegisterRouter.scala:87:24]
wire out_womask_598 = &_out_womask_T_598; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_598 = out_rivalid_1_452 & out_rimask_598; // @[RegisterRouter.scala:87:24]
wire _out_T_6043 = out_f_rivalid_598; // @[RegisterRouter.scala:87:24]
wire out_f_roready_598 = out_roready_1_452 & out_romask_598; // @[RegisterRouter.scala:87:24]
wire _out_T_6044 = out_f_roready_598; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_598 = out_wivalid_1_452 & out_wimask_598; // @[RegisterRouter.scala:87:24]
wire out_f_woready_598 = out_woready_1_452 & out_womask_598; // @[RegisterRouter.scala:87:24]
wire _out_T_6045 = ~out_rimask_598; // @[RegisterRouter.scala:87:24]
wire _out_T_6046 = ~out_wimask_598; // @[RegisterRouter.scala:87:24]
wire _out_T_6047 = ~out_romask_598; // @[RegisterRouter.scala:87:24]
wire _out_T_6048 = ~out_womask_598; // @[RegisterRouter.scala:87:24]
wire out_rimask_599 = |_out_rimask_T_599; // @[RegisterRouter.scala:87:24]
wire out_wimask_599 = &_out_wimask_T_599; // @[RegisterRouter.scala:87:24]
wire out_romask_599 = |_out_romask_T_599; // @[RegisterRouter.scala:87:24]
wire out_womask_599 = &_out_womask_T_599; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_599 = out_rivalid_1_453 & out_rimask_599; // @[RegisterRouter.scala:87:24]
wire _out_T_6052 = out_f_rivalid_599; // @[RegisterRouter.scala:87:24]
wire out_f_roready_599 = out_roready_1_453 & out_romask_599; // @[RegisterRouter.scala:87:24]
wire _out_T_6053 = out_f_roready_599; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_599 = out_wivalid_1_453 & out_wimask_599; // @[RegisterRouter.scala:87:24]
wire out_f_woready_599 = out_woready_1_453 & out_womask_599; // @[RegisterRouter.scala:87:24]
wire _out_T_6054 = ~out_rimask_599; // @[RegisterRouter.scala:87:24]
wire _out_T_6055 = ~out_wimask_599; // @[RegisterRouter.scala:87:24]
wire _out_T_6056 = ~out_romask_599; // @[RegisterRouter.scala:87:24]
wire _out_T_6057 = ~out_womask_599; // @[RegisterRouter.scala:87:24]
wire out_rimask_600 = |_out_rimask_T_600; // @[RegisterRouter.scala:87:24]
wire out_wimask_600 = &_out_wimask_T_600; // @[RegisterRouter.scala:87:24]
wire out_romask_600 = |_out_romask_T_600; // @[RegisterRouter.scala:87:24]
wire out_womask_600 = &_out_womask_T_600; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_600 = out_rivalid_1_454 & out_rimask_600; // @[RegisterRouter.scala:87:24]
wire _out_T_6061 = out_f_rivalid_600; // @[RegisterRouter.scala:87:24]
wire out_f_roready_600 = out_roready_1_454 & out_romask_600; // @[RegisterRouter.scala:87:24]
wire _out_T_6062 = out_f_roready_600; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_600 = out_wivalid_1_454 & out_wimask_600; // @[RegisterRouter.scala:87:24]
wire out_f_woready_600 = out_woready_1_454 & out_womask_600; // @[RegisterRouter.scala:87:24]
wire _out_T_6063 = ~out_rimask_600; // @[RegisterRouter.scala:87:24]
wire _out_T_6064 = ~out_wimask_600; // @[RegisterRouter.scala:87:24]
wire _out_T_6065 = ~out_romask_600; // @[RegisterRouter.scala:87:24]
wire _out_T_6066 = ~out_womask_600; // @[RegisterRouter.scala:87:24]
wire out_rimask_601 = |_out_rimask_T_601; // @[RegisterRouter.scala:87:24]
wire out_wimask_601 = &_out_wimask_T_601; // @[RegisterRouter.scala:87:24]
wire out_romask_601 = |_out_romask_T_601; // @[RegisterRouter.scala:87:24]
wire out_womask_601 = &_out_womask_T_601; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_601 = out_rivalid_1_455 & out_rimask_601; // @[RegisterRouter.scala:87:24]
wire _out_T_6070 = out_f_rivalid_601; // @[RegisterRouter.scala:87:24]
wire out_f_roready_601 = out_roready_1_455 & out_romask_601; // @[RegisterRouter.scala:87:24]
wire _out_T_6071 = out_f_roready_601; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_601 = out_wivalid_1_455 & out_wimask_601; // @[RegisterRouter.scala:87:24]
wire out_f_woready_601 = out_woready_1_455 & out_womask_601; // @[RegisterRouter.scala:87:24]
wire _out_T_6072 = ~out_rimask_601; // @[RegisterRouter.scala:87:24]
wire _out_T_6073 = ~out_wimask_601; // @[RegisterRouter.scala:87:24]
wire _out_T_6074 = ~out_romask_601; // @[RegisterRouter.scala:87:24]
wire _out_T_6075 = ~out_womask_601; // @[RegisterRouter.scala:87:24]
wire out_rimask_602 = |_out_rimask_T_602; // @[RegisterRouter.scala:87:24]
wire out_wimask_602 = &_out_wimask_T_602; // @[RegisterRouter.scala:87:24]
wire out_romask_602 = |_out_romask_T_602; // @[RegisterRouter.scala:87:24]
wire out_womask_602 = &_out_womask_T_602; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_602 = out_rivalid_1_456 & out_rimask_602; // @[RegisterRouter.scala:87:24]
wire _out_T_6079 = out_f_rivalid_602; // @[RegisterRouter.scala:87:24]
wire out_f_roready_602 = out_roready_1_456 & out_romask_602; // @[RegisterRouter.scala:87:24]
wire _out_T_6080 = out_f_roready_602; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_602 = out_wivalid_1_456 & out_wimask_602; // @[RegisterRouter.scala:87:24]
wire out_f_woready_602 = out_woready_1_456 & out_womask_602; // @[RegisterRouter.scala:87:24]
wire _out_T_6081 = ~out_rimask_602; // @[RegisterRouter.scala:87:24]
wire _out_T_6082 = ~out_wimask_602; // @[RegisterRouter.scala:87:24]
wire _out_T_6083 = ~out_romask_602; // @[RegisterRouter.scala:87:24]
wire _out_T_6084 = ~out_womask_602; // @[RegisterRouter.scala:87:24]
wire out_rimask_603 = |_out_rimask_T_603; // @[RegisterRouter.scala:87:24]
wire out_wimask_603 = &_out_wimask_T_603; // @[RegisterRouter.scala:87:24]
wire out_romask_603 = |_out_romask_T_603; // @[RegisterRouter.scala:87:24]
wire out_womask_603 = &_out_womask_T_603; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_603 = out_rivalid_1_457 & out_rimask_603; // @[RegisterRouter.scala:87:24]
wire _out_T_6088 = out_f_rivalid_603; // @[RegisterRouter.scala:87:24]
wire out_f_roready_603 = out_roready_1_457 & out_romask_603; // @[RegisterRouter.scala:87:24]
wire _out_T_6089 = out_f_roready_603; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_603 = out_wivalid_1_457 & out_wimask_603; // @[RegisterRouter.scala:87:24]
wire out_f_woready_603 = out_woready_1_457 & out_womask_603; // @[RegisterRouter.scala:87:24]
wire _out_T_6090 = ~out_rimask_603; // @[RegisterRouter.scala:87:24]
wire _out_T_6091 = ~out_wimask_603; // @[RegisterRouter.scala:87:24]
wire _out_T_6092 = ~out_romask_603; // @[RegisterRouter.scala:87:24]
wire _out_T_6093 = ~out_womask_603; // @[RegisterRouter.scala:87:24]
wire out_rimask_604 = |_out_rimask_T_604; // @[RegisterRouter.scala:87:24]
wire out_wimask_604 = &_out_wimask_T_604; // @[RegisterRouter.scala:87:24]
wire out_romask_604 = |_out_romask_T_604; // @[RegisterRouter.scala:87:24]
wire out_womask_604 = &_out_womask_T_604; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_604 = out_rivalid_1_458 & out_rimask_604; // @[RegisterRouter.scala:87:24]
wire _out_T_6097 = out_f_rivalid_604; // @[RegisterRouter.scala:87:24]
wire out_f_roready_604 = out_roready_1_458 & out_romask_604; // @[RegisterRouter.scala:87:24]
wire _out_T_6098 = out_f_roready_604; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_604 = out_wivalid_1_458 & out_wimask_604; // @[RegisterRouter.scala:87:24]
wire out_f_woready_604 = out_woready_1_458 & out_womask_604; // @[RegisterRouter.scala:87:24]
wire _out_T_6099 = ~out_rimask_604; // @[RegisterRouter.scala:87:24]
wire _out_T_6100 = ~out_wimask_604; // @[RegisterRouter.scala:87:24]
wire _out_T_6101 = ~out_romask_604; // @[RegisterRouter.scala:87:24]
wire _out_T_6102 = ~out_womask_604; // @[RegisterRouter.scala:87:24]
wire out_rimask_605 = |_out_rimask_T_605; // @[RegisterRouter.scala:87:24]
wire out_wimask_605 = &_out_wimask_T_605; // @[RegisterRouter.scala:87:24]
wire out_romask_605 = |_out_romask_T_605; // @[RegisterRouter.scala:87:24]
wire out_womask_605 = &_out_womask_T_605; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_605 = out_rivalid_1_459 & out_rimask_605; // @[RegisterRouter.scala:87:24]
wire _out_T_6106 = out_f_rivalid_605; // @[RegisterRouter.scala:87:24]
wire out_f_roready_605 = out_roready_1_459 & out_romask_605; // @[RegisterRouter.scala:87:24]
wire _out_T_6107 = out_f_roready_605; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_605 = out_wivalid_1_459 & out_wimask_605; // @[RegisterRouter.scala:87:24]
wire out_f_woready_605 = out_woready_1_459 & out_womask_605; // @[RegisterRouter.scala:87:24]
wire _out_T_6108 = ~out_rimask_605; // @[RegisterRouter.scala:87:24]
wire _out_T_6109 = ~out_wimask_605; // @[RegisterRouter.scala:87:24]
wire _out_T_6110 = ~out_romask_605; // @[RegisterRouter.scala:87:24]
wire _out_T_6111 = ~out_womask_605; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6113 = _out_T_6112; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_512 = _out_T_6113; // @[RegisterRouter.scala:87:24]
wire out_rimask_606 = |_out_rimask_T_606; // @[RegisterRouter.scala:87:24]
wire out_wimask_606 = &_out_wimask_T_606; // @[RegisterRouter.scala:87:24]
wire out_romask_606 = |_out_romask_T_606; // @[RegisterRouter.scala:87:24]
wire out_womask_606 = &_out_womask_T_606; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_606 = out_rivalid_1_460 & out_rimask_606; // @[RegisterRouter.scala:87:24]
wire _out_T_6115 = out_f_rivalid_606; // @[RegisterRouter.scala:87:24]
wire out_f_roready_606 = out_roready_1_460 & out_romask_606; // @[RegisterRouter.scala:87:24]
wire _out_T_6116 = out_f_roready_606; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_606 = out_wivalid_1_460 & out_wimask_606; // @[RegisterRouter.scala:87:24]
wire out_f_woready_606 = out_woready_1_460 & out_womask_606; // @[RegisterRouter.scala:87:24]
wire _out_T_6117 = ~out_rimask_606; // @[RegisterRouter.scala:87:24]
wire _out_T_6118 = ~out_wimask_606; // @[RegisterRouter.scala:87:24]
wire _out_T_6119 = ~out_romask_606; // @[RegisterRouter.scala:87:24]
wire _out_T_6120 = ~out_womask_606; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_512 = {hi_362, flags_0_go, _out_prepend_T_512}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_6121 = out_prepend_512; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_6122 = _out_T_6121; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_513 = _out_T_6122; // @[RegisterRouter.scala:87:24]
wire out_rimask_607 = |_out_rimask_T_607; // @[RegisterRouter.scala:87:24]
wire out_wimask_607 = &_out_wimask_T_607; // @[RegisterRouter.scala:87:24]
wire out_romask_607 = |_out_romask_T_607; // @[RegisterRouter.scala:87:24]
wire out_womask_607 = &_out_womask_T_607; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_607 = out_rivalid_1_461 & out_rimask_607; // @[RegisterRouter.scala:87:24]
wire _out_T_6124 = out_f_rivalid_607; // @[RegisterRouter.scala:87:24]
wire out_f_roready_607 = out_roready_1_461 & out_romask_607; // @[RegisterRouter.scala:87:24]
wire _out_T_6125 = out_f_roready_607; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_607 = out_wivalid_1_461 & out_wimask_607; // @[RegisterRouter.scala:87:24]
wire out_f_woready_607 = out_woready_1_461 & out_womask_607; // @[RegisterRouter.scala:87:24]
wire _out_T_6126 = ~out_rimask_607; // @[RegisterRouter.scala:87:24]
wire _out_T_6127 = ~out_wimask_607; // @[RegisterRouter.scala:87:24]
wire _out_T_6128 = ~out_romask_607; // @[RegisterRouter.scala:87:24]
wire _out_T_6129 = ~out_womask_607; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_513 = {hi_363, flags_0_go, _out_prepend_T_513}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_6130 = out_prepend_513; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_6131 = _out_T_6130; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_514 = _out_T_6131; // @[RegisterRouter.scala:87:24]
wire out_rimask_608 = |_out_rimask_T_608; // @[RegisterRouter.scala:87:24]
wire out_wimask_608 = &_out_wimask_T_608; // @[RegisterRouter.scala:87:24]
wire out_romask_608 = |_out_romask_T_608; // @[RegisterRouter.scala:87:24]
wire out_womask_608 = &_out_womask_T_608; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_608 = out_rivalid_1_462 & out_rimask_608; // @[RegisterRouter.scala:87:24]
wire _out_T_6133 = out_f_rivalid_608; // @[RegisterRouter.scala:87:24]
wire out_f_roready_608 = out_roready_1_462 & out_romask_608; // @[RegisterRouter.scala:87:24]
wire _out_T_6134 = out_f_roready_608; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_608 = out_wivalid_1_462 & out_wimask_608; // @[RegisterRouter.scala:87:24]
wire out_f_woready_608 = out_woready_1_462 & out_womask_608; // @[RegisterRouter.scala:87:24]
wire _out_T_6135 = ~out_rimask_608; // @[RegisterRouter.scala:87:24]
wire _out_T_6136 = ~out_wimask_608; // @[RegisterRouter.scala:87:24]
wire _out_T_6137 = ~out_romask_608; // @[RegisterRouter.scala:87:24]
wire _out_T_6138 = ~out_womask_608; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_514 = {hi_364, flags_0_go, _out_prepend_T_514}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_6139 = out_prepend_514; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_6140 = _out_T_6139; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_515 = _out_T_6140; // @[RegisterRouter.scala:87:24]
wire out_rimask_609 = |_out_rimask_T_609; // @[RegisterRouter.scala:87:24]
wire out_wimask_609 = &_out_wimask_T_609; // @[RegisterRouter.scala:87:24]
wire out_romask_609 = |_out_romask_T_609; // @[RegisterRouter.scala:87:24]
wire out_womask_609 = &_out_womask_T_609; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_609 = out_rivalid_1_463 & out_rimask_609; // @[RegisterRouter.scala:87:24]
wire _out_T_6142 = out_f_rivalid_609; // @[RegisterRouter.scala:87:24]
wire out_f_roready_609 = out_roready_1_463 & out_romask_609; // @[RegisterRouter.scala:87:24]
wire _out_T_6143 = out_f_roready_609; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_609 = out_wivalid_1_463 & out_wimask_609; // @[RegisterRouter.scala:87:24]
wire out_f_woready_609 = out_woready_1_463 & out_womask_609; // @[RegisterRouter.scala:87:24]
wire _out_T_6144 = ~out_rimask_609; // @[RegisterRouter.scala:87:24]
wire _out_T_6145 = ~out_wimask_609; // @[RegisterRouter.scala:87:24]
wire _out_T_6146 = ~out_romask_609; // @[RegisterRouter.scala:87:24]
wire _out_T_6147 = ~out_womask_609; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_515 = {hi_365, flags_0_go, _out_prepend_T_515}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_6148 = out_prepend_515; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_6149 = _out_T_6148; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_516 = _out_T_6149; // @[RegisterRouter.scala:87:24]
wire out_rimask_610 = |_out_rimask_T_610; // @[RegisterRouter.scala:87:24]
wire out_wimask_610 = &_out_wimask_T_610; // @[RegisterRouter.scala:87:24]
wire out_romask_610 = |_out_romask_T_610; // @[RegisterRouter.scala:87:24]
wire out_womask_610 = &_out_womask_T_610; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_610 = out_rivalid_1_464 & out_rimask_610; // @[RegisterRouter.scala:87:24]
wire _out_T_6151 = out_f_rivalid_610; // @[RegisterRouter.scala:87:24]
wire out_f_roready_610 = out_roready_1_464 & out_romask_610; // @[RegisterRouter.scala:87:24]
wire _out_T_6152 = out_f_roready_610; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_610 = out_wivalid_1_464 & out_wimask_610; // @[RegisterRouter.scala:87:24]
wire out_f_woready_610 = out_woready_1_464 & out_womask_610; // @[RegisterRouter.scala:87:24]
wire _out_T_6153 = ~out_rimask_610; // @[RegisterRouter.scala:87:24]
wire _out_T_6154 = ~out_wimask_610; // @[RegisterRouter.scala:87:24]
wire _out_T_6155 = ~out_romask_610; // @[RegisterRouter.scala:87:24]
wire _out_T_6156 = ~out_womask_610; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_516 = {hi_366, flags_0_go, _out_prepend_T_516}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_6157 = out_prepend_516; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_6158 = _out_T_6157; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_517 = _out_T_6158; // @[RegisterRouter.scala:87:24]
wire out_rimask_611 = |_out_rimask_T_611; // @[RegisterRouter.scala:87:24]
wire out_wimask_611 = &_out_wimask_T_611; // @[RegisterRouter.scala:87:24]
wire out_romask_611 = |_out_romask_T_611; // @[RegisterRouter.scala:87:24]
wire out_womask_611 = &_out_womask_T_611; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_611 = out_rivalid_1_465 & out_rimask_611; // @[RegisterRouter.scala:87:24]
wire _out_T_6160 = out_f_rivalid_611; // @[RegisterRouter.scala:87:24]
wire out_f_roready_611 = out_roready_1_465 & out_romask_611; // @[RegisterRouter.scala:87:24]
wire _out_T_6161 = out_f_roready_611; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_611 = out_wivalid_1_465 & out_wimask_611; // @[RegisterRouter.scala:87:24]
wire out_f_woready_611 = out_woready_1_465 & out_womask_611; // @[RegisterRouter.scala:87:24]
wire _out_T_6162 = ~out_rimask_611; // @[RegisterRouter.scala:87:24]
wire _out_T_6163 = ~out_wimask_611; // @[RegisterRouter.scala:87:24]
wire _out_T_6164 = ~out_romask_611; // @[RegisterRouter.scala:87:24]
wire _out_T_6165 = ~out_womask_611; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_517 = {hi_367, flags_0_go, _out_prepend_T_517}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_6166 = out_prepend_517; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_6167 = _out_T_6166; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_518 = _out_T_6167; // @[RegisterRouter.scala:87:24]
wire out_rimask_612 = |_out_rimask_T_612; // @[RegisterRouter.scala:87:24]
wire out_wimask_612 = &_out_wimask_T_612; // @[RegisterRouter.scala:87:24]
wire out_romask_612 = |_out_romask_T_612; // @[RegisterRouter.scala:87:24]
wire out_womask_612 = &_out_womask_T_612; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_612 = out_rivalid_1_466 & out_rimask_612; // @[RegisterRouter.scala:87:24]
wire _out_T_6169 = out_f_rivalid_612; // @[RegisterRouter.scala:87:24]
wire out_f_roready_612 = out_roready_1_466 & out_romask_612; // @[RegisterRouter.scala:87:24]
wire _out_T_6170 = out_f_roready_612; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_612 = out_wivalid_1_466 & out_wimask_612; // @[RegisterRouter.scala:87:24]
wire out_f_woready_612 = out_woready_1_466 & out_womask_612; // @[RegisterRouter.scala:87:24]
wire _out_T_6171 = ~out_rimask_612; // @[RegisterRouter.scala:87:24]
wire _out_T_6172 = ~out_wimask_612; // @[RegisterRouter.scala:87:24]
wire _out_T_6173 = ~out_romask_612; // @[RegisterRouter.scala:87:24]
wire _out_T_6174 = ~out_womask_612; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_518 = {hi_368, flags_0_go, _out_prepend_T_518}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_6175 = out_prepend_518; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_6176 = _out_T_6175; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_173 = _out_T_6176; // @[MuxLiteral.scala:49:48]
wire out_rimask_613 = |_out_rimask_T_613; // @[RegisterRouter.scala:87:24]
wire out_wimask_613 = &_out_wimask_T_613; // @[RegisterRouter.scala:87:24]
wire out_romask_613 = |_out_romask_T_613; // @[RegisterRouter.scala:87:24]
wire out_womask_613 = &_out_womask_T_613; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_613 = out_rivalid_1_467 & out_rimask_613; // @[RegisterRouter.scala:87:24]
wire _out_T_6178 = out_f_rivalid_613; // @[RegisterRouter.scala:87:24]
wire out_f_roready_613 = out_roready_1_467 & out_romask_613; // @[RegisterRouter.scala:87:24]
wire _out_T_6179 = out_f_roready_613; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_613 = out_wivalid_1_467 & out_wimask_613; // @[RegisterRouter.scala:87:24]
wire out_f_woready_613 = out_woready_1_467 & out_womask_613; // @[RegisterRouter.scala:87:24]
wire _out_T_6180 = ~out_rimask_613; // @[RegisterRouter.scala:87:24]
wire _out_T_6181 = ~out_wimask_613; // @[RegisterRouter.scala:87:24]
wire _out_T_6182 = ~out_romask_613; // @[RegisterRouter.scala:87:24]
wire _out_T_6183 = ~out_womask_613; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6185 = _out_T_6184; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_519 = _out_T_6185; // @[RegisterRouter.scala:87:24]
wire out_rimask_614 = |_out_rimask_T_614; // @[RegisterRouter.scala:87:24]
wire out_wimask_614 = &_out_wimask_T_614; // @[RegisterRouter.scala:87:24]
wire out_romask_614 = |_out_romask_T_614; // @[RegisterRouter.scala:87:24]
wire out_womask_614 = &_out_womask_T_614; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_614 = out_rivalid_1_468 & out_rimask_614; // @[RegisterRouter.scala:87:24]
wire _out_T_6187 = out_f_rivalid_614; // @[RegisterRouter.scala:87:24]
wire out_f_roready_614 = out_roready_1_468 & out_romask_614; // @[RegisterRouter.scala:87:24]
wire _out_T_6188 = out_f_roready_614; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_614 = out_wivalid_1_468 & out_wimask_614; // @[RegisterRouter.scala:87:24]
wire out_f_woready_614 = out_woready_1_468 & out_womask_614; // @[RegisterRouter.scala:87:24]
wire _out_T_6189 = ~out_rimask_614; // @[RegisterRouter.scala:87:24]
wire _out_T_6190 = ~out_wimask_614; // @[RegisterRouter.scala:87:24]
wire _out_T_6191 = ~out_romask_614; // @[RegisterRouter.scala:87:24]
wire _out_T_6192 = ~out_womask_614; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_519 = {hi_10, flags_0_go, _out_prepend_T_519}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_6193 = out_prepend_519; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_6194 = _out_T_6193; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_520 = _out_T_6194; // @[RegisterRouter.scala:87:24]
wire out_rimask_615 = |_out_rimask_T_615; // @[RegisterRouter.scala:87:24]
wire out_wimask_615 = &_out_wimask_T_615; // @[RegisterRouter.scala:87:24]
wire out_romask_615 = |_out_romask_T_615; // @[RegisterRouter.scala:87:24]
wire out_womask_615 = &_out_womask_T_615; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_615 = out_rivalid_1_469 & out_rimask_615; // @[RegisterRouter.scala:87:24]
wire _out_T_6196 = out_f_rivalid_615; // @[RegisterRouter.scala:87:24]
wire out_f_roready_615 = out_roready_1_469 & out_romask_615; // @[RegisterRouter.scala:87:24]
wire _out_T_6197 = out_f_roready_615; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_615 = out_wivalid_1_469 & out_wimask_615; // @[RegisterRouter.scala:87:24]
wire out_f_woready_615 = out_woready_1_469 & out_womask_615; // @[RegisterRouter.scala:87:24]
wire _out_T_6198 = ~out_rimask_615; // @[RegisterRouter.scala:87:24]
wire _out_T_6199 = ~out_wimask_615; // @[RegisterRouter.scala:87:24]
wire _out_T_6200 = ~out_romask_615; // @[RegisterRouter.scala:87:24]
wire _out_T_6201 = ~out_womask_615; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_520 = {hi_11, flags_0_go, _out_prepend_T_520}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_6202 = out_prepend_520; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_6203 = _out_T_6202; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_521 = _out_T_6203; // @[RegisterRouter.scala:87:24]
wire out_rimask_616 = |_out_rimask_T_616; // @[RegisterRouter.scala:87:24]
wire out_wimask_616 = &_out_wimask_T_616; // @[RegisterRouter.scala:87:24]
wire out_romask_616 = |_out_romask_T_616; // @[RegisterRouter.scala:87:24]
wire out_womask_616 = &_out_womask_T_616; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_616 = out_rivalid_1_470 & out_rimask_616; // @[RegisterRouter.scala:87:24]
wire _out_T_6205 = out_f_rivalid_616; // @[RegisterRouter.scala:87:24]
wire out_f_roready_616 = out_roready_1_470 & out_romask_616; // @[RegisterRouter.scala:87:24]
wire _out_T_6206 = out_f_roready_616; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_616 = out_wivalid_1_470 & out_wimask_616; // @[RegisterRouter.scala:87:24]
wire out_f_woready_616 = out_woready_1_470 & out_womask_616; // @[RegisterRouter.scala:87:24]
wire _out_T_6207 = ~out_rimask_616; // @[RegisterRouter.scala:87:24]
wire _out_T_6208 = ~out_wimask_616; // @[RegisterRouter.scala:87:24]
wire _out_T_6209 = ~out_romask_616; // @[RegisterRouter.scala:87:24]
wire _out_T_6210 = ~out_womask_616; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_521 = {hi_12, flags_0_go, _out_prepend_T_521}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_6211 = out_prepend_521; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_6212 = _out_T_6211; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_522 = _out_T_6212; // @[RegisterRouter.scala:87:24]
wire out_rimask_617 = |_out_rimask_T_617; // @[RegisterRouter.scala:87:24]
wire out_wimask_617 = &_out_wimask_T_617; // @[RegisterRouter.scala:87:24]
wire out_romask_617 = |_out_romask_T_617; // @[RegisterRouter.scala:87:24]
wire out_womask_617 = &_out_womask_T_617; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_617 = out_rivalid_1_471 & out_rimask_617; // @[RegisterRouter.scala:87:24]
wire _out_T_6214 = out_f_rivalid_617; // @[RegisterRouter.scala:87:24]
wire out_f_roready_617 = out_roready_1_471 & out_romask_617; // @[RegisterRouter.scala:87:24]
wire _out_T_6215 = out_f_roready_617; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_617 = out_wivalid_1_471 & out_wimask_617; // @[RegisterRouter.scala:87:24]
wire out_f_woready_617 = out_woready_1_471 & out_womask_617; // @[RegisterRouter.scala:87:24]
wire _out_T_6216 = ~out_rimask_617; // @[RegisterRouter.scala:87:24]
wire _out_T_6217 = ~out_wimask_617; // @[RegisterRouter.scala:87:24]
wire _out_T_6218 = ~out_romask_617; // @[RegisterRouter.scala:87:24]
wire _out_T_6219 = ~out_womask_617; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_522 = {hi_13, flags_0_go, _out_prepend_T_522}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_6220 = out_prepend_522; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_6221 = _out_T_6220; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_523 = _out_T_6221; // @[RegisterRouter.scala:87:24]
wire out_rimask_618 = |_out_rimask_T_618; // @[RegisterRouter.scala:87:24]
wire out_wimask_618 = &_out_wimask_T_618; // @[RegisterRouter.scala:87:24]
wire out_romask_618 = |_out_romask_T_618; // @[RegisterRouter.scala:87:24]
wire out_womask_618 = &_out_womask_T_618; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_618 = out_rivalid_1_472 & out_rimask_618; // @[RegisterRouter.scala:87:24]
wire _out_T_6223 = out_f_rivalid_618; // @[RegisterRouter.scala:87:24]
wire out_f_roready_618 = out_roready_1_472 & out_romask_618; // @[RegisterRouter.scala:87:24]
wire _out_T_6224 = out_f_roready_618; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_618 = out_wivalid_1_472 & out_wimask_618; // @[RegisterRouter.scala:87:24]
wire out_f_woready_618 = out_woready_1_472 & out_womask_618; // @[RegisterRouter.scala:87:24]
wire _out_T_6225 = ~out_rimask_618; // @[RegisterRouter.scala:87:24]
wire _out_T_6226 = ~out_wimask_618; // @[RegisterRouter.scala:87:24]
wire _out_T_6227 = ~out_romask_618; // @[RegisterRouter.scala:87:24]
wire _out_T_6228 = ~out_womask_618; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_523 = {hi_14, flags_0_go, _out_prepend_T_523}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_6229 = out_prepend_523; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_6230 = _out_T_6229; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_524 = _out_T_6230; // @[RegisterRouter.scala:87:24]
wire out_rimask_619 = |_out_rimask_T_619; // @[RegisterRouter.scala:87:24]
wire out_wimask_619 = &_out_wimask_T_619; // @[RegisterRouter.scala:87:24]
wire out_romask_619 = |_out_romask_T_619; // @[RegisterRouter.scala:87:24]
wire out_womask_619 = &_out_womask_T_619; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_619 = out_rivalid_1_473 & out_rimask_619; // @[RegisterRouter.scala:87:24]
wire _out_T_6232 = out_f_rivalid_619; // @[RegisterRouter.scala:87:24]
wire out_f_roready_619 = out_roready_1_473 & out_romask_619; // @[RegisterRouter.scala:87:24]
wire _out_T_6233 = out_f_roready_619; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_619 = out_wivalid_1_473 & out_wimask_619; // @[RegisterRouter.scala:87:24]
wire out_f_woready_619 = out_woready_1_473 & out_womask_619; // @[RegisterRouter.scala:87:24]
wire _out_T_6234 = ~out_rimask_619; // @[RegisterRouter.scala:87:24]
wire _out_T_6235 = ~out_wimask_619; // @[RegisterRouter.scala:87:24]
wire _out_T_6236 = ~out_romask_619; // @[RegisterRouter.scala:87:24]
wire _out_T_6237 = ~out_womask_619; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_524 = {hi_15, flags_0_go, _out_prepend_T_524}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_6238 = out_prepend_524; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_6239 = _out_T_6238; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_525 = _out_T_6239; // @[RegisterRouter.scala:87:24]
wire out_rimask_620 = |_out_rimask_T_620; // @[RegisterRouter.scala:87:24]
wire out_wimask_620 = &_out_wimask_T_620; // @[RegisterRouter.scala:87:24]
wire out_romask_620 = |_out_romask_T_620; // @[RegisterRouter.scala:87:24]
wire out_womask_620 = &_out_womask_T_620; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_620 = out_rivalid_1_474 & out_rimask_620; // @[RegisterRouter.scala:87:24]
wire _out_T_6241 = out_f_rivalid_620; // @[RegisterRouter.scala:87:24]
wire out_f_roready_620 = out_roready_1_474 & out_romask_620; // @[RegisterRouter.scala:87:24]
wire _out_T_6242 = out_f_roready_620; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_620 = out_wivalid_1_474 & out_wimask_620; // @[RegisterRouter.scala:87:24]
wire out_f_woready_620 = out_woready_1_474 & out_womask_620; // @[RegisterRouter.scala:87:24]
wire _out_T_6243 = ~out_rimask_620; // @[RegisterRouter.scala:87:24]
wire _out_T_6244 = ~out_wimask_620; // @[RegisterRouter.scala:87:24]
wire _out_T_6245 = ~out_romask_620; // @[RegisterRouter.scala:87:24]
wire _out_T_6246 = ~out_womask_620; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_525 = {hi_16, flags_0_go, _out_prepend_T_525}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_6247 = out_prepend_525; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_6248 = _out_T_6247; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_129 = _out_T_6248; // @[MuxLiteral.scala:49:48]
wire out_rimask_621 = |_out_rimask_T_621; // @[RegisterRouter.scala:87:24]
wire out_wimask_621 = &_out_wimask_T_621; // @[RegisterRouter.scala:87:24]
wire out_romask_621 = |_out_romask_T_621; // @[RegisterRouter.scala:87:24]
wire out_womask_621 = &_out_womask_T_621; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_621 = out_rivalid_1_475 & out_rimask_621; // @[RegisterRouter.scala:87:24]
wire _out_T_6250 = out_f_rivalid_621; // @[RegisterRouter.scala:87:24]
wire out_f_roready_621 = out_roready_1_475 & out_romask_621; // @[RegisterRouter.scala:87:24]
wire _out_T_6251 = out_f_roready_621; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_621 = out_wivalid_1_475 & out_wimask_621; // @[RegisterRouter.scala:87:24]
wire out_f_woready_621 = out_woready_1_475 & out_womask_621; // @[RegisterRouter.scala:87:24]
wire _out_T_6252 = ~out_rimask_621; // @[RegisterRouter.scala:87:24]
wire _out_T_6253 = ~out_wimask_621; // @[RegisterRouter.scala:87:24]
wire _out_T_6254 = ~out_romask_621; // @[RegisterRouter.scala:87:24]
wire _out_T_6255 = ~out_womask_621; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6257 = _out_T_6256; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_526 = _out_T_6257; // @[RegisterRouter.scala:87:24]
wire out_rimask_622 = |_out_rimask_T_622; // @[RegisterRouter.scala:87:24]
wire out_wimask_622 = &_out_wimask_T_622; // @[RegisterRouter.scala:87:24]
wire out_romask_622 = |_out_romask_T_622; // @[RegisterRouter.scala:87:24]
wire out_womask_622 = &_out_womask_T_622; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_622 = out_rivalid_1_476 & out_rimask_622; // @[RegisterRouter.scala:87:24]
wire _out_T_6259 = out_f_rivalid_622; // @[RegisterRouter.scala:87:24]
wire out_f_roready_622 = out_roready_1_476 & out_romask_622; // @[RegisterRouter.scala:87:24]
wire _out_T_6260 = out_f_roready_622; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_622 = out_wivalid_1_476 & out_wimask_622; // @[RegisterRouter.scala:87:24]
wire out_f_woready_622 = out_woready_1_476 & out_womask_622; // @[RegisterRouter.scala:87:24]
wire _out_T_6261 = ~out_rimask_622; // @[RegisterRouter.scala:87:24]
wire _out_T_6262 = ~out_wimask_622; // @[RegisterRouter.scala:87:24]
wire _out_T_6263 = ~out_romask_622; // @[RegisterRouter.scala:87:24]
wire _out_T_6264 = ~out_womask_622; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_526 = {hi_50, flags_0_go, _out_prepend_T_526}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_6265 = out_prepend_526; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_6266 = _out_T_6265; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_527 = _out_T_6266; // @[RegisterRouter.scala:87:24]
wire out_rimask_623 = |_out_rimask_T_623; // @[RegisterRouter.scala:87:24]
wire out_wimask_623 = &_out_wimask_T_623; // @[RegisterRouter.scala:87:24]
wire out_romask_623 = |_out_romask_T_623; // @[RegisterRouter.scala:87:24]
wire out_womask_623 = &_out_womask_T_623; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_623 = out_rivalid_1_477 & out_rimask_623; // @[RegisterRouter.scala:87:24]
wire _out_T_6268 = out_f_rivalid_623; // @[RegisterRouter.scala:87:24]
wire out_f_roready_623 = out_roready_1_477 & out_romask_623; // @[RegisterRouter.scala:87:24]
wire _out_T_6269 = out_f_roready_623; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_623 = out_wivalid_1_477 & out_wimask_623; // @[RegisterRouter.scala:87:24]
wire out_f_woready_623 = out_woready_1_477 & out_womask_623; // @[RegisterRouter.scala:87:24]
wire _out_T_6270 = ~out_rimask_623; // @[RegisterRouter.scala:87:24]
wire _out_T_6271 = ~out_wimask_623; // @[RegisterRouter.scala:87:24]
wire _out_T_6272 = ~out_romask_623; // @[RegisterRouter.scala:87:24]
wire _out_T_6273 = ~out_womask_623; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_527 = {hi_51, flags_0_go, _out_prepend_T_527}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_6274 = out_prepend_527; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_6275 = _out_T_6274; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_528 = _out_T_6275; // @[RegisterRouter.scala:87:24]
wire out_rimask_624 = |_out_rimask_T_624; // @[RegisterRouter.scala:87:24]
wire out_wimask_624 = &_out_wimask_T_624; // @[RegisterRouter.scala:87:24]
wire out_romask_624 = |_out_romask_T_624; // @[RegisterRouter.scala:87:24]
wire out_womask_624 = &_out_womask_T_624; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_624 = out_rivalid_1_478 & out_rimask_624; // @[RegisterRouter.scala:87:24]
wire _out_T_6277 = out_f_rivalid_624; // @[RegisterRouter.scala:87:24]
wire out_f_roready_624 = out_roready_1_478 & out_romask_624; // @[RegisterRouter.scala:87:24]
wire _out_T_6278 = out_f_roready_624; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_624 = out_wivalid_1_478 & out_wimask_624; // @[RegisterRouter.scala:87:24]
wire out_f_woready_624 = out_woready_1_478 & out_womask_624; // @[RegisterRouter.scala:87:24]
wire _out_T_6279 = ~out_rimask_624; // @[RegisterRouter.scala:87:24]
wire _out_T_6280 = ~out_wimask_624; // @[RegisterRouter.scala:87:24]
wire _out_T_6281 = ~out_romask_624; // @[RegisterRouter.scala:87:24]
wire _out_T_6282 = ~out_womask_624; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_528 = {hi_52, flags_0_go, _out_prepend_T_528}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_6283 = out_prepend_528; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_6284 = _out_T_6283; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_529 = _out_T_6284; // @[RegisterRouter.scala:87:24]
wire out_rimask_625 = |_out_rimask_T_625; // @[RegisterRouter.scala:87:24]
wire out_wimask_625 = &_out_wimask_T_625; // @[RegisterRouter.scala:87:24]
wire out_romask_625 = |_out_romask_T_625; // @[RegisterRouter.scala:87:24]
wire out_womask_625 = &_out_womask_T_625; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_625 = out_rivalid_1_479 & out_rimask_625; // @[RegisterRouter.scala:87:24]
wire _out_T_6286 = out_f_rivalid_625; // @[RegisterRouter.scala:87:24]
wire out_f_roready_625 = out_roready_1_479 & out_romask_625; // @[RegisterRouter.scala:87:24]
wire _out_T_6287 = out_f_roready_625; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_625 = out_wivalid_1_479 & out_wimask_625; // @[RegisterRouter.scala:87:24]
wire out_f_woready_625 = out_woready_1_479 & out_womask_625; // @[RegisterRouter.scala:87:24]
wire _out_T_6288 = ~out_rimask_625; // @[RegisterRouter.scala:87:24]
wire _out_T_6289 = ~out_wimask_625; // @[RegisterRouter.scala:87:24]
wire _out_T_6290 = ~out_romask_625; // @[RegisterRouter.scala:87:24]
wire _out_T_6291 = ~out_womask_625; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_529 = {hi_53, flags_0_go, _out_prepend_T_529}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_6292 = out_prepend_529; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_6293 = _out_T_6292; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_530 = _out_T_6293; // @[RegisterRouter.scala:87:24]
wire out_rimask_626 = |_out_rimask_T_626; // @[RegisterRouter.scala:87:24]
wire out_wimask_626 = &_out_wimask_T_626; // @[RegisterRouter.scala:87:24]
wire out_romask_626 = |_out_romask_T_626; // @[RegisterRouter.scala:87:24]
wire out_womask_626 = &_out_womask_T_626; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_626 = out_rivalid_1_480 & out_rimask_626; // @[RegisterRouter.scala:87:24]
wire _out_T_6295 = out_f_rivalid_626; // @[RegisterRouter.scala:87:24]
wire out_f_roready_626 = out_roready_1_480 & out_romask_626; // @[RegisterRouter.scala:87:24]
wire _out_T_6296 = out_f_roready_626; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_626 = out_wivalid_1_480 & out_wimask_626; // @[RegisterRouter.scala:87:24]
wire out_f_woready_626 = out_woready_1_480 & out_womask_626; // @[RegisterRouter.scala:87:24]
wire _out_T_6297 = ~out_rimask_626; // @[RegisterRouter.scala:87:24]
wire _out_T_6298 = ~out_wimask_626; // @[RegisterRouter.scala:87:24]
wire _out_T_6299 = ~out_romask_626; // @[RegisterRouter.scala:87:24]
wire _out_T_6300 = ~out_womask_626; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_530 = {hi_54, flags_0_go, _out_prepend_T_530}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_6301 = out_prepend_530; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_6302 = _out_T_6301; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_531 = _out_T_6302; // @[RegisterRouter.scala:87:24]
wire out_rimask_627 = |_out_rimask_T_627; // @[RegisterRouter.scala:87:24]
wire out_wimask_627 = &_out_wimask_T_627; // @[RegisterRouter.scala:87:24]
wire out_romask_627 = |_out_romask_T_627; // @[RegisterRouter.scala:87:24]
wire out_womask_627 = &_out_womask_T_627; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_627 = out_rivalid_1_481 & out_rimask_627; // @[RegisterRouter.scala:87:24]
wire _out_T_6304 = out_f_rivalid_627; // @[RegisterRouter.scala:87:24]
wire out_f_roready_627 = out_roready_1_481 & out_romask_627; // @[RegisterRouter.scala:87:24]
wire _out_T_6305 = out_f_roready_627; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_627 = out_wivalid_1_481 & out_wimask_627; // @[RegisterRouter.scala:87:24]
wire out_f_woready_627 = out_woready_1_481 & out_womask_627; // @[RegisterRouter.scala:87:24]
wire _out_T_6306 = ~out_rimask_627; // @[RegisterRouter.scala:87:24]
wire _out_T_6307 = ~out_wimask_627; // @[RegisterRouter.scala:87:24]
wire _out_T_6308 = ~out_romask_627; // @[RegisterRouter.scala:87:24]
wire _out_T_6309 = ~out_womask_627; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_531 = {hi_55, flags_0_go, _out_prepend_T_531}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_6310 = out_prepend_531; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_6311 = _out_T_6310; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_532 = _out_T_6311; // @[RegisterRouter.scala:87:24]
wire out_rimask_628 = |_out_rimask_T_628; // @[RegisterRouter.scala:87:24]
wire out_wimask_628 = &_out_wimask_T_628; // @[RegisterRouter.scala:87:24]
wire out_romask_628 = |_out_romask_T_628; // @[RegisterRouter.scala:87:24]
wire out_womask_628 = &_out_womask_T_628; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_628 = out_rivalid_1_482 & out_rimask_628; // @[RegisterRouter.scala:87:24]
wire _out_T_6313 = out_f_rivalid_628; // @[RegisterRouter.scala:87:24]
wire out_f_roready_628 = out_roready_1_482 & out_romask_628; // @[RegisterRouter.scala:87:24]
wire _out_T_6314 = out_f_roready_628; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_628 = out_wivalid_1_482 & out_wimask_628; // @[RegisterRouter.scala:87:24]
wire out_f_woready_628 = out_woready_1_482 & out_womask_628; // @[RegisterRouter.scala:87:24]
wire _out_T_6315 = ~out_rimask_628; // @[RegisterRouter.scala:87:24]
wire _out_T_6316 = ~out_wimask_628; // @[RegisterRouter.scala:87:24]
wire _out_T_6317 = ~out_romask_628; // @[RegisterRouter.scala:87:24]
wire _out_T_6318 = ~out_womask_628; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_532 = {hi_56, flags_0_go, _out_prepend_T_532}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_6319 = out_prepend_532; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_6320 = _out_T_6319; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_134 = _out_T_6320; // @[MuxLiteral.scala:49:48]
wire out_rimask_629 = |_out_rimask_T_629; // @[RegisterRouter.scala:87:24]
wire out_wimask_629 = &_out_wimask_T_629; // @[RegisterRouter.scala:87:24]
wire out_romask_629 = |_out_romask_T_629; // @[RegisterRouter.scala:87:24]
wire out_womask_629 = &_out_womask_T_629; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_629 = out_rivalid_1_483 & out_rimask_629; // @[RegisterRouter.scala:87:24]
wire _out_T_6322 = out_f_rivalid_629; // @[RegisterRouter.scala:87:24]
wire out_f_roready_629 = out_roready_1_483 & out_romask_629; // @[RegisterRouter.scala:87:24]
wire _out_T_6323 = out_f_roready_629; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_629 = out_wivalid_1_483 & out_wimask_629; // @[RegisterRouter.scala:87:24]
wire out_f_woready_629 = out_woready_1_483 & out_womask_629; // @[RegisterRouter.scala:87:24]
wire _out_T_6324 = ~out_rimask_629; // @[RegisterRouter.scala:87:24]
wire _out_T_6325 = ~out_wimask_629; // @[RegisterRouter.scala:87:24]
wire _out_T_6326 = ~out_romask_629; // @[RegisterRouter.scala:87:24]
wire _out_T_6327 = ~out_womask_629; // @[RegisterRouter.scala:87:24]
wire out_rimask_630 = |_out_rimask_T_630; // @[RegisterRouter.scala:87:24]
wire out_wimask_630 = &_out_wimask_T_630; // @[RegisterRouter.scala:87:24]
wire out_romask_630 = |_out_romask_T_630; // @[RegisterRouter.scala:87:24]
wire out_womask_630 = &_out_womask_T_630; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_630 = out_rivalid_1_484 & out_rimask_630; // @[RegisterRouter.scala:87:24]
wire _out_T_6331 = out_f_rivalid_630; // @[RegisterRouter.scala:87:24]
wire out_f_roready_630 = out_roready_1_484 & out_romask_630; // @[RegisterRouter.scala:87:24]
wire _out_T_6332 = out_f_roready_630; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_630 = out_wivalid_1_484 & out_wimask_630; // @[RegisterRouter.scala:87:24]
wire out_f_woready_630 = out_woready_1_484 & out_womask_630; // @[RegisterRouter.scala:87:24]
wire _out_T_6333 = ~out_rimask_630; // @[RegisterRouter.scala:87:24]
wire _out_T_6334 = ~out_wimask_630; // @[RegisterRouter.scala:87:24]
wire _out_T_6335 = ~out_romask_630; // @[RegisterRouter.scala:87:24]
wire _out_T_6336 = ~out_womask_630; // @[RegisterRouter.scala:87:24]
wire out_rimask_631 = |_out_rimask_T_631; // @[RegisterRouter.scala:87:24]
wire out_wimask_631 = &_out_wimask_T_631; // @[RegisterRouter.scala:87:24]
wire out_romask_631 = |_out_romask_T_631; // @[RegisterRouter.scala:87:24]
wire out_womask_631 = &_out_womask_T_631; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_631 = out_rivalid_1_485 & out_rimask_631; // @[RegisterRouter.scala:87:24]
wire _out_T_6340 = out_f_rivalid_631; // @[RegisterRouter.scala:87:24]
wire out_f_roready_631 = out_roready_1_485 & out_romask_631; // @[RegisterRouter.scala:87:24]
wire _out_T_6341 = out_f_roready_631; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_631 = out_wivalid_1_485 & out_wimask_631; // @[RegisterRouter.scala:87:24]
wire out_f_woready_631 = out_woready_1_485 & out_womask_631; // @[RegisterRouter.scala:87:24]
wire _out_T_6342 = ~out_rimask_631; // @[RegisterRouter.scala:87:24]
wire _out_T_6343 = ~out_wimask_631; // @[RegisterRouter.scala:87:24]
wire _out_T_6344 = ~out_romask_631; // @[RegisterRouter.scala:87:24]
wire _out_T_6345 = ~out_womask_631; // @[RegisterRouter.scala:87:24]
wire out_rimask_632 = |_out_rimask_T_632; // @[RegisterRouter.scala:87:24]
wire out_wimask_632 = &_out_wimask_T_632; // @[RegisterRouter.scala:87:24]
wire out_romask_632 = |_out_romask_T_632; // @[RegisterRouter.scala:87:24]
wire out_womask_632 = &_out_womask_T_632; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_632 = out_rivalid_1_486 & out_rimask_632; // @[RegisterRouter.scala:87:24]
wire _out_T_6349 = out_f_rivalid_632; // @[RegisterRouter.scala:87:24]
wire out_f_roready_632 = out_roready_1_486 & out_romask_632; // @[RegisterRouter.scala:87:24]
wire _out_T_6350 = out_f_roready_632; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_632 = out_wivalid_1_486 & out_wimask_632; // @[RegisterRouter.scala:87:24]
wire out_f_woready_632 = out_woready_1_486 & out_womask_632; // @[RegisterRouter.scala:87:24]
wire _out_T_6351 = ~out_rimask_632; // @[RegisterRouter.scala:87:24]
wire _out_T_6352 = ~out_wimask_632; // @[RegisterRouter.scala:87:24]
wire _out_T_6353 = ~out_romask_632; // @[RegisterRouter.scala:87:24]
wire _out_T_6354 = ~out_womask_632; // @[RegisterRouter.scala:87:24]
wire out_rimask_633 = |_out_rimask_T_633; // @[RegisterRouter.scala:87:24]
wire out_wimask_633 = &_out_wimask_T_633; // @[RegisterRouter.scala:87:24]
wire out_romask_633 = |_out_romask_T_633; // @[RegisterRouter.scala:87:24]
wire out_womask_633 = &_out_womask_T_633; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_633 = out_rivalid_1_487 & out_rimask_633; // @[RegisterRouter.scala:87:24]
wire _out_T_6358 = out_f_rivalid_633; // @[RegisterRouter.scala:87:24]
wire out_f_roready_633 = out_roready_1_487 & out_romask_633; // @[RegisterRouter.scala:87:24]
wire _out_T_6359 = out_f_roready_633; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_633 = out_wivalid_1_487 & out_wimask_633; // @[RegisterRouter.scala:87:24]
wire out_f_woready_633 = out_woready_1_487 & out_womask_633; // @[RegisterRouter.scala:87:24]
wire _out_T_6360 = ~out_rimask_633; // @[RegisterRouter.scala:87:24]
wire _out_T_6361 = ~out_wimask_633; // @[RegisterRouter.scala:87:24]
wire _out_T_6362 = ~out_romask_633; // @[RegisterRouter.scala:87:24]
wire _out_T_6363 = ~out_womask_633; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6365 = _out_T_6364; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_536 = _out_T_6365; // @[RegisterRouter.scala:87:24]
wire out_rimask_634 = |_out_rimask_T_634; // @[RegisterRouter.scala:87:24]
wire out_wimask_634 = &_out_wimask_T_634; // @[RegisterRouter.scala:87:24]
wire out_romask_634 = |_out_romask_T_634; // @[RegisterRouter.scala:87:24]
wire out_womask_634 = &_out_womask_T_634; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_634 = out_rivalid_1_488 & out_rimask_634; // @[RegisterRouter.scala:87:24]
wire _out_T_6367 = out_f_rivalid_634; // @[RegisterRouter.scala:87:24]
wire out_f_roready_634 = out_roready_1_488 & out_romask_634; // @[RegisterRouter.scala:87:24]
wire _out_T_6368 = out_f_roready_634; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_634 = out_wivalid_1_488 & out_wimask_634; // @[RegisterRouter.scala:87:24]
wire out_f_woready_634 = out_woready_1_488 & out_womask_634; // @[RegisterRouter.scala:87:24]
wire _out_T_6369 = ~out_rimask_634; // @[RegisterRouter.scala:87:24]
wire _out_T_6370 = ~out_wimask_634; // @[RegisterRouter.scala:87:24]
wire _out_T_6371 = ~out_romask_634; // @[RegisterRouter.scala:87:24]
wire _out_T_6372 = ~out_womask_634; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_536 = {hi_618, flags_0_go, _out_prepend_T_536}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_6373 = out_prepend_536; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_6374 = _out_T_6373; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_537 = _out_T_6374; // @[RegisterRouter.scala:87:24]
wire out_rimask_635 = |_out_rimask_T_635; // @[RegisterRouter.scala:87:24]
wire out_wimask_635 = &_out_wimask_T_635; // @[RegisterRouter.scala:87:24]
wire out_romask_635 = |_out_romask_T_635; // @[RegisterRouter.scala:87:24]
wire out_womask_635 = &_out_womask_T_635; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_635 = out_rivalid_1_489 & out_rimask_635; // @[RegisterRouter.scala:87:24]
wire _out_T_6376 = out_f_rivalid_635; // @[RegisterRouter.scala:87:24]
wire out_f_roready_635 = out_roready_1_489 & out_romask_635; // @[RegisterRouter.scala:87:24]
wire _out_T_6377 = out_f_roready_635; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_635 = out_wivalid_1_489 & out_wimask_635; // @[RegisterRouter.scala:87:24]
wire out_f_woready_635 = out_woready_1_489 & out_womask_635; // @[RegisterRouter.scala:87:24]
wire _out_T_6378 = ~out_rimask_635; // @[RegisterRouter.scala:87:24]
wire _out_T_6379 = ~out_wimask_635; // @[RegisterRouter.scala:87:24]
wire _out_T_6380 = ~out_romask_635; // @[RegisterRouter.scala:87:24]
wire _out_T_6381 = ~out_womask_635; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_537 = {hi_619, flags_0_go, _out_prepend_T_537}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_6382 = out_prepend_537; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_6383 = _out_T_6382; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_538 = _out_T_6383; // @[RegisterRouter.scala:87:24]
wire out_rimask_636 = |_out_rimask_T_636; // @[RegisterRouter.scala:87:24]
wire out_wimask_636 = &_out_wimask_T_636; // @[RegisterRouter.scala:87:24]
wire out_romask_636 = |_out_romask_T_636; // @[RegisterRouter.scala:87:24]
wire out_womask_636 = &_out_womask_T_636; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_636 = out_rivalid_1_490 & out_rimask_636; // @[RegisterRouter.scala:87:24]
wire _out_T_6385 = out_f_rivalid_636; // @[RegisterRouter.scala:87:24]
wire out_f_roready_636 = out_roready_1_490 & out_romask_636; // @[RegisterRouter.scala:87:24]
wire _out_T_6386 = out_f_roready_636; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_636 = out_wivalid_1_490 & out_wimask_636; // @[RegisterRouter.scala:87:24]
wire out_f_woready_636 = out_woready_1_490 & out_womask_636; // @[RegisterRouter.scala:87:24]
wire _out_T_6387 = ~out_rimask_636; // @[RegisterRouter.scala:87:24]
wire _out_T_6388 = ~out_wimask_636; // @[RegisterRouter.scala:87:24]
wire _out_T_6389 = ~out_romask_636; // @[RegisterRouter.scala:87:24]
wire _out_T_6390 = ~out_womask_636; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_538 = {hi_620, flags_0_go, _out_prepend_T_538}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_6391 = out_prepend_538; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_6392 = _out_T_6391; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_539 = _out_T_6392; // @[RegisterRouter.scala:87:24]
wire out_rimask_637 = |_out_rimask_T_637; // @[RegisterRouter.scala:87:24]
wire out_wimask_637 = &_out_wimask_T_637; // @[RegisterRouter.scala:87:24]
wire out_romask_637 = |_out_romask_T_637; // @[RegisterRouter.scala:87:24]
wire out_womask_637 = &_out_womask_T_637; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_637 = out_rivalid_1_491 & out_rimask_637; // @[RegisterRouter.scala:87:24]
wire _out_T_6394 = out_f_rivalid_637; // @[RegisterRouter.scala:87:24]
wire out_f_roready_637 = out_roready_1_491 & out_romask_637; // @[RegisterRouter.scala:87:24]
wire _out_T_6395 = out_f_roready_637; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_637 = out_wivalid_1_491 & out_wimask_637; // @[RegisterRouter.scala:87:24]
wire out_f_woready_637 = out_woready_1_491 & out_womask_637; // @[RegisterRouter.scala:87:24]
wire _out_T_6396 = ~out_rimask_637; // @[RegisterRouter.scala:87:24]
wire _out_T_6397 = ~out_wimask_637; // @[RegisterRouter.scala:87:24]
wire _out_T_6398 = ~out_romask_637; // @[RegisterRouter.scala:87:24]
wire _out_T_6399 = ~out_womask_637; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_539 = {hi_621, flags_0_go, _out_prepend_T_539}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_6400 = out_prepend_539; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_6401 = _out_T_6400; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_540 = _out_T_6401; // @[RegisterRouter.scala:87:24]
wire out_rimask_638 = |_out_rimask_T_638; // @[RegisterRouter.scala:87:24]
wire out_wimask_638 = &_out_wimask_T_638; // @[RegisterRouter.scala:87:24]
wire out_romask_638 = |_out_romask_T_638; // @[RegisterRouter.scala:87:24]
wire out_womask_638 = &_out_womask_T_638; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_638 = out_rivalid_1_492 & out_rimask_638; // @[RegisterRouter.scala:87:24]
wire _out_T_6403 = out_f_rivalid_638; // @[RegisterRouter.scala:87:24]
wire out_f_roready_638 = out_roready_1_492 & out_romask_638; // @[RegisterRouter.scala:87:24]
wire _out_T_6404 = out_f_roready_638; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_638 = out_wivalid_1_492 & out_wimask_638; // @[RegisterRouter.scala:87:24]
wire out_f_woready_638 = out_woready_1_492 & out_womask_638; // @[RegisterRouter.scala:87:24]
wire _out_T_6405 = ~out_rimask_638; // @[RegisterRouter.scala:87:24]
wire _out_T_6406 = ~out_wimask_638; // @[RegisterRouter.scala:87:24]
wire _out_T_6407 = ~out_romask_638; // @[RegisterRouter.scala:87:24]
wire _out_T_6408 = ~out_womask_638; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_540 = {hi_622, flags_0_go, _out_prepend_T_540}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_6409 = out_prepend_540; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_6410 = _out_T_6409; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_541 = _out_T_6410; // @[RegisterRouter.scala:87:24]
wire out_rimask_639 = |_out_rimask_T_639; // @[RegisterRouter.scala:87:24]
wire out_wimask_639 = &_out_wimask_T_639; // @[RegisterRouter.scala:87:24]
wire out_romask_639 = |_out_romask_T_639; // @[RegisterRouter.scala:87:24]
wire out_womask_639 = &_out_womask_T_639; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_639 = out_rivalid_1_493 & out_rimask_639; // @[RegisterRouter.scala:87:24]
wire _out_T_6412 = out_f_rivalid_639; // @[RegisterRouter.scala:87:24]
wire out_f_roready_639 = out_roready_1_493 & out_romask_639; // @[RegisterRouter.scala:87:24]
wire _out_T_6413 = out_f_roready_639; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_639 = out_wivalid_1_493 & out_wimask_639; // @[RegisterRouter.scala:87:24]
wire out_f_woready_639 = out_woready_1_493 & out_womask_639; // @[RegisterRouter.scala:87:24]
wire _out_T_6414 = ~out_rimask_639; // @[RegisterRouter.scala:87:24]
wire _out_T_6415 = ~out_wimask_639; // @[RegisterRouter.scala:87:24]
wire _out_T_6416 = ~out_romask_639; // @[RegisterRouter.scala:87:24]
wire _out_T_6417 = ~out_womask_639; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_541 = {hi_623, flags_0_go, _out_prepend_T_541}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_6418 = out_prepend_541; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_6419 = _out_T_6418; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_542 = _out_T_6419; // @[RegisterRouter.scala:87:24]
wire out_rimask_640 = |_out_rimask_T_640; // @[RegisterRouter.scala:87:24]
wire out_wimask_640 = &_out_wimask_T_640; // @[RegisterRouter.scala:87:24]
wire out_romask_640 = |_out_romask_T_640; // @[RegisterRouter.scala:87:24]
wire out_womask_640 = &_out_womask_T_640; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_640 = out_rivalid_1_494 & out_rimask_640; // @[RegisterRouter.scala:87:24]
wire _out_T_6421 = out_f_rivalid_640; // @[RegisterRouter.scala:87:24]
wire out_f_roready_640 = out_roready_1_494 & out_romask_640; // @[RegisterRouter.scala:87:24]
wire _out_T_6422 = out_f_roready_640; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_640 = out_wivalid_1_494 & out_wimask_640; // @[RegisterRouter.scala:87:24]
wire out_f_woready_640 = out_woready_1_494 & out_womask_640; // @[RegisterRouter.scala:87:24]
wire _out_T_6423 = ~out_rimask_640; // @[RegisterRouter.scala:87:24]
wire _out_T_6424 = ~out_wimask_640; // @[RegisterRouter.scala:87:24]
wire _out_T_6425 = ~out_romask_640; // @[RegisterRouter.scala:87:24]
wire _out_T_6426 = ~out_womask_640; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_542 = {hi_624, flags_0_go, _out_prepend_T_542}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_6427 = out_prepend_542; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_6428 = _out_T_6427; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_205 = _out_T_6428; // @[MuxLiteral.scala:49:48]
wire out_rimask_641 = |_out_rimask_T_641; // @[RegisterRouter.scala:87:24]
wire out_wimask_641 = &_out_wimask_T_641; // @[RegisterRouter.scala:87:24]
wire out_romask_641 = |_out_romask_T_641; // @[RegisterRouter.scala:87:24]
wire out_womask_641 = &_out_womask_T_641; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_641 = out_rivalid_1_495 & out_rimask_641; // @[RegisterRouter.scala:87:24]
wire _out_T_6430 = out_f_rivalid_641; // @[RegisterRouter.scala:87:24]
wire out_f_roready_641 = out_roready_1_495 & out_romask_641; // @[RegisterRouter.scala:87:24]
wire _out_T_6431 = out_f_roready_641; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_641 = out_wivalid_1_495 & out_wimask_641; // @[RegisterRouter.scala:87:24]
wire out_f_woready_641 = out_woready_1_495 & out_womask_641; // @[RegisterRouter.scala:87:24]
wire _out_T_6432 = ~out_rimask_641; // @[RegisterRouter.scala:87:24]
wire _out_T_6433 = ~out_wimask_641; // @[RegisterRouter.scala:87:24]
wire _out_T_6434 = ~out_romask_641; // @[RegisterRouter.scala:87:24]
wire _out_T_6435 = ~out_womask_641; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6437 = _out_T_6436; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_543 = _out_T_6437; // @[RegisterRouter.scala:87:24]
wire out_rimask_642 = |_out_rimask_T_642; // @[RegisterRouter.scala:87:24]
wire out_wimask_642 = &_out_wimask_T_642; // @[RegisterRouter.scala:87:24]
wire out_romask_642 = |_out_romask_T_642; // @[RegisterRouter.scala:87:24]
wire out_womask_642 = &_out_womask_T_642; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_642 = out_rivalid_1_496 & out_rimask_642; // @[RegisterRouter.scala:87:24]
wire _out_T_6439 = out_f_rivalid_642; // @[RegisterRouter.scala:87:24]
wire out_f_roready_642 = out_roready_1_496 & out_romask_642; // @[RegisterRouter.scala:87:24]
wire _out_T_6440 = out_f_roready_642; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_642 = out_wivalid_1_496 & out_wimask_642; // @[RegisterRouter.scala:87:24]
wire out_f_woready_642 = out_woready_1_496 & out_womask_642; // @[RegisterRouter.scala:87:24]
wire _out_T_6441 = ~out_rimask_642; // @[RegisterRouter.scala:87:24]
wire _out_T_6442 = ~out_wimask_642; // @[RegisterRouter.scala:87:24]
wire _out_T_6443 = ~out_romask_642; // @[RegisterRouter.scala:87:24]
wire _out_T_6444 = ~out_womask_642; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_543 = {hi_2, flags_0_go, _out_prepend_T_543}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_6445 = out_prepend_543; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_6446 = _out_T_6445; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_544 = _out_T_6446; // @[RegisterRouter.scala:87:24]
wire out_rimask_643 = |_out_rimask_T_643; // @[RegisterRouter.scala:87:24]
wire out_wimask_643 = &_out_wimask_T_643; // @[RegisterRouter.scala:87:24]
wire out_romask_643 = |_out_romask_T_643; // @[RegisterRouter.scala:87:24]
wire out_womask_643 = &_out_womask_T_643; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_643 = out_rivalid_1_497 & out_rimask_643; // @[RegisterRouter.scala:87:24]
wire _out_T_6448 = out_f_rivalid_643; // @[RegisterRouter.scala:87:24]
wire out_f_roready_643 = out_roready_1_497 & out_romask_643; // @[RegisterRouter.scala:87:24]
wire _out_T_6449 = out_f_roready_643; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_643 = out_wivalid_1_497 & out_wimask_643; // @[RegisterRouter.scala:87:24]
wire out_f_woready_643 = out_woready_1_497 & out_womask_643; // @[RegisterRouter.scala:87:24]
wire _out_T_6450 = ~out_rimask_643; // @[RegisterRouter.scala:87:24]
wire _out_T_6451 = ~out_wimask_643; // @[RegisterRouter.scala:87:24]
wire _out_T_6452 = ~out_romask_643; // @[RegisterRouter.scala:87:24]
wire _out_T_6453 = ~out_womask_643; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_544 = {hi_3, flags_0_go, _out_prepend_T_544}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_6454 = out_prepend_544; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_6455 = _out_T_6454; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_545 = _out_T_6455; // @[RegisterRouter.scala:87:24]
wire out_rimask_644 = |_out_rimask_T_644; // @[RegisterRouter.scala:87:24]
wire out_wimask_644 = &_out_wimask_T_644; // @[RegisterRouter.scala:87:24]
wire out_romask_644 = |_out_romask_T_644; // @[RegisterRouter.scala:87:24]
wire out_womask_644 = &_out_womask_T_644; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_644 = out_rivalid_1_498 & out_rimask_644; // @[RegisterRouter.scala:87:24]
wire _out_T_6457 = out_f_rivalid_644; // @[RegisterRouter.scala:87:24]
wire out_f_roready_644 = out_roready_1_498 & out_romask_644; // @[RegisterRouter.scala:87:24]
wire _out_T_6458 = out_f_roready_644; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_644 = out_wivalid_1_498 & out_wimask_644; // @[RegisterRouter.scala:87:24]
wire out_f_woready_644 = out_woready_1_498 & out_womask_644; // @[RegisterRouter.scala:87:24]
wire _out_T_6459 = ~out_rimask_644; // @[RegisterRouter.scala:87:24]
wire _out_T_6460 = ~out_wimask_644; // @[RegisterRouter.scala:87:24]
wire _out_T_6461 = ~out_romask_644; // @[RegisterRouter.scala:87:24]
wire _out_T_6462 = ~out_womask_644; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_545 = {hi_4, flags_0_go, _out_prepend_T_545}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_6463 = out_prepend_545; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_6464 = _out_T_6463; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_546 = _out_T_6464; // @[RegisterRouter.scala:87:24]
wire out_rimask_645 = |_out_rimask_T_645; // @[RegisterRouter.scala:87:24]
wire out_wimask_645 = &_out_wimask_T_645; // @[RegisterRouter.scala:87:24]
wire out_romask_645 = |_out_romask_T_645; // @[RegisterRouter.scala:87:24]
wire out_womask_645 = &_out_womask_T_645; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_645 = out_rivalid_1_499 & out_rimask_645; // @[RegisterRouter.scala:87:24]
wire _out_T_6466 = out_f_rivalid_645; // @[RegisterRouter.scala:87:24]
wire out_f_roready_645 = out_roready_1_499 & out_romask_645; // @[RegisterRouter.scala:87:24]
wire _out_T_6467 = out_f_roready_645; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_645 = out_wivalid_1_499 & out_wimask_645; // @[RegisterRouter.scala:87:24]
wire out_f_woready_645 = out_woready_1_499 & out_womask_645; // @[RegisterRouter.scala:87:24]
wire _out_T_6468 = ~out_rimask_645; // @[RegisterRouter.scala:87:24]
wire _out_T_6469 = ~out_wimask_645; // @[RegisterRouter.scala:87:24]
wire _out_T_6470 = ~out_romask_645; // @[RegisterRouter.scala:87:24]
wire _out_T_6471 = ~out_womask_645; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_546 = {hi_5, flags_0_go, _out_prepend_T_546}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_6472 = out_prepend_546; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_6473 = _out_T_6472; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_547 = _out_T_6473; // @[RegisterRouter.scala:87:24]
wire out_rimask_646 = |_out_rimask_T_646; // @[RegisterRouter.scala:87:24]
wire out_wimask_646 = &_out_wimask_T_646; // @[RegisterRouter.scala:87:24]
wire out_romask_646 = |_out_romask_T_646; // @[RegisterRouter.scala:87:24]
wire out_womask_646 = &_out_womask_T_646; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_646 = out_rivalid_1_500 & out_rimask_646; // @[RegisterRouter.scala:87:24]
wire _out_T_6475 = out_f_rivalid_646; // @[RegisterRouter.scala:87:24]
wire out_f_roready_646 = out_roready_1_500 & out_romask_646; // @[RegisterRouter.scala:87:24]
wire _out_T_6476 = out_f_roready_646; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_646 = out_wivalid_1_500 & out_wimask_646; // @[RegisterRouter.scala:87:24]
wire out_f_woready_646 = out_woready_1_500 & out_womask_646; // @[RegisterRouter.scala:87:24]
wire _out_T_6477 = ~out_rimask_646; // @[RegisterRouter.scala:87:24]
wire _out_T_6478 = ~out_wimask_646; // @[RegisterRouter.scala:87:24]
wire _out_T_6479 = ~out_romask_646; // @[RegisterRouter.scala:87:24]
wire _out_T_6480 = ~out_womask_646; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_547 = {hi_6, flags_0_go, _out_prepend_T_547}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_6481 = out_prepend_547; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_6482 = _out_T_6481; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_548 = _out_T_6482; // @[RegisterRouter.scala:87:24]
wire out_rimask_647 = |_out_rimask_T_647; // @[RegisterRouter.scala:87:24]
wire out_wimask_647 = &_out_wimask_T_647; // @[RegisterRouter.scala:87:24]
wire out_romask_647 = |_out_romask_T_647; // @[RegisterRouter.scala:87:24]
wire out_womask_647 = &_out_womask_T_647; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_647 = out_rivalid_1_501 & out_rimask_647; // @[RegisterRouter.scala:87:24]
wire _out_T_6484 = out_f_rivalid_647; // @[RegisterRouter.scala:87:24]
wire out_f_roready_647 = out_roready_1_501 & out_romask_647; // @[RegisterRouter.scala:87:24]
wire _out_T_6485 = out_f_roready_647; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_647 = out_wivalid_1_501 & out_wimask_647; // @[RegisterRouter.scala:87:24]
wire out_f_woready_647 = out_woready_1_501 & out_womask_647; // @[RegisterRouter.scala:87:24]
wire _out_T_6486 = ~out_rimask_647; // @[RegisterRouter.scala:87:24]
wire _out_T_6487 = ~out_wimask_647; // @[RegisterRouter.scala:87:24]
wire _out_T_6488 = ~out_romask_647; // @[RegisterRouter.scala:87:24]
wire _out_T_6489 = ~out_womask_647; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_548 = {hi_7, flags_0_go, _out_prepend_T_548}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_6490 = out_prepend_548; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_6491 = _out_T_6490; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_549 = _out_T_6491; // @[RegisterRouter.scala:87:24]
wire out_rimask_648 = |_out_rimask_T_648; // @[RegisterRouter.scala:87:24]
wire out_wimask_648 = &_out_wimask_T_648; // @[RegisterRouter.scala:87:24]
wire out_romask_648 = |_out_romask_T_648; // @[RegisterRouter.scala:87:24]
wire out_womask_648 = &_out_womask_T_648; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_648 = out_rivalid_1_502 & out_rimask_648; // @[RegisterRouter.scala:87:24]
wire _out_T_6493 = out_f_rivalid_648; // @[RegisterRouter.scala:87:24]
wire out_f_roready_648 = out_roready_1_502 & out_romask_648; // @[RegisterRouter.scala:87:24]
wire _out_T_6494 = out_f_roready_648; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_648 = out_wivalid_1_502 & out_wimask_648; // @[RegisterRouter.scala:87:24]
wire out_f_woready_648 = out_woready_1_502 & out_womask_648; // @[RegisterRouter.scala:87:24]
wire _out_T_6495 = ~out_rimask_648; // @[RegisterRouter.scala:87:24]
wire _out_T_6496 = ~out_wimask_648; // @[RegisterRouter.scala:87:24]
wire _out_T_6497 = ~out_romask_648; // @[RegisterRouter.scala:87:24]
wire _out_T_6498 = ~out_womask_648; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_549 = {hi_8, flags_0_go, _out_prepend_T_549}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_6499 = out_prepend_549; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_6500 = _out_T_6499; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_128 = _out_T_6500; // @[MuxLiteral.scala:49:48]
wire out_rimask_649 = |_out_rimask_T_649; // @[RegisterRouter.scala:87:24]
wire out_wimask_649 = &_out_wimask_T_649; // @[RegisterRouter.scala:87:24]
wire out_romask_649 = |_out_romask_T_649; // @[RegisterRouter.scala:87:24]
wire out_womask_649 = &_out_womask_T_649; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_649 = out_rivalid_1_503 & out_rimask_649; // @[RegisterRouter.scala:87:24]
wire _out_T_6502 = out_f_rivalid_649; // @[RegisterRouter.scala:87:24]
wire out_f_roready_649 = out_roready_1_503 & out_romask_649; // @[RegisterRouter.scala:87:24]
wire _out_T_6503 = out_f_roready_649; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_649 = out_wivalid_1_503 & out_wimask_649; // @[RegisterRouter.scala:87:24]
wire out_f_woready_649 = out_woready_1_503 & out_womask_649; // @[RegisterRouter.scala:87:24]
wire _out_T_6504 = ~out_rimask_649; // @[RegisterRouter.scala:87:24]
wire _out_T_6505 = ~out_wimask_649; // @[RegisterRouter.scala:87:24]
wire _out_T_6506 = ~out_romask_649; // @[RegisterRouter.scala:87:24]
wire _out_T_6507 = ~out_womask_649; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6509 = _out_T_6508; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_550 = _out_T_6509; // @[RegisterRouter.scala:87:24]
wire out_rimask_650 = |_out_rimask_T_650; // @[RegisterRouter.scala:87:24]
wire out_wimask_650 = &_out_wimask_T_650; // @[RegisterRouter.scala:87:24]
wire out_romask_650 = |_out_romask_T_650; // @[RegisterRouter.scala:87:24]
wire out_womask_650 = &_out_womask_T_650; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_650 = out_rivalid_1_504 & out_rimask_650; // @[RegisterRouter.scala:87:24]
wire _out_T_6511 = out_f_rivalid_650; // @[RegisterRouter.scala:87:24]
wire out_f_roready_650 = out_roready_1_504 & out_romask_650; // @[RegisterRouter.scala:87:24]
wire _out_T_6512 = out_f_roready_650; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_650 = out_wivalid_1_504 & out_wimask_650; // @[RegisterRouter.scala:87:24]
wire out_f_woready_650 = out_woready_1_504 & out_womask_650; // @[RegisterRouter.scala:87:24]
wire _out_T_6513 = ~out_rimask_650; // @[RegisterRouter.scala:87:24]
wire _out_T_6514 = ~out_wimask_650; // @[RegisterRouter.scala:87:24]
wire _out_T_6515 = ~out_romask_650; // @[RegisterRouter.scala:87:24]
wire _out_T_6516 = ~out_womask_650; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_550 = {hi_874, flags_0_go, _out_prepend_T_550}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_6517 = out_prepend_550; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_6518 = _out_T_6517; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_551 = _out_T_6518; // @[RegisterRouter.scala:87:24]
wire out_rimask_651 = |_out_rimask_T_651; // @[RegisterRouter.scala:87:24]
wire out_wimask_651 = &_out_wimask_T_651; // @[RegisterRouter.scala:87:24]
wire out_romask_651 = |_out_romask_T_651; // @[RegisterRouter.scala:87:24]
wire out_womask_651 = &_out_womask_T_651; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_651 = out_rivalid_1_505 & out_rimask_651; // @[RegisterRouter.scala:87:24]
wire _out_T_6520 = out_f_rivalid_651; // @[RegisterRouter.scala:87:24]
wire out_f_roready_651 = out_roready_1_505 & out_romask_651; // @[RegisterRouter.scala:87:24]
wire _out_T_6521 = out_f_roready_651; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_651 = out_wivalid_1_505 & out_wimask_651; // @[RegisterRouter.scala:87:24]
wire out_f_woready_651 = out_woready_1_505 & out_womask_651; // @[RegisterRouter.scala:87:24]
wire _out_T_6522 = ~out_rimask_651; // @[RegisterRouter.scala:87:24]
wire _out_T_6523 = ~out_wimask_651; // @[RegisterRouter.scala:87:24]
wire _out_T_6524 = ~out_romask_651; // @[RegisterRouter.scala:87:24]
wire _out_T_6525 = ~out_womask_651; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_551 = {hi_875, flags_0_go, _out_prepend_T_551}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_6526 = out_prepend_551; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_6527 = _out_T_6526; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_552 = _out_T_6527; // @[RegisterRouter.scala:87:24]
wire out_rimask_652 = |_out_rimask_T_652; // @[RegisterRouter.scala:87:24]
wire out_wimask_652 = &_out_wimask_T_652; // @[RegisterRouter.scala:87:24]
wire out_romask_652 = |_out_romask_T_652; // @[RegisterRouter.scala:87:24]
wire out_womask_652 = &_out_womask_T_652; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_652 = out_rivalid_1_506 & out_rimask_652; // @[RegisterRouter.scala:87:24]
wire _out_T_6529 = out_f_rivalid_652; // @[RegisterRouter.scala:87:24]
wire out_f_roready_652 = out_roready_1_506 & out_romask_652; // @[RegisterRouter.scala:87:24]
wire _out_T_6530 = out_f_roready_652; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_652 = out_wivalid_1_506 & out_wimask_652; // @[RegisterRouter.scala:87:24]
wire out_f_woready_652 = out_woready_1_506 & out_womask_652; // @[RegisterRouter.scala:87:24]
wire _out_T_6531 = ~out_rimask_652; // @[RegisterRouter.scala:87:24]
wire _out_T_6532 = ~out_wimask_652; // @[RegisterRouter.scala:87:24]
wire _out_T_6533 = ~out_romask_652; // @[RegisterRouter.scala:87:24]
wire _out_T_6534 = ~out_womask_652; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_552 = {hi_876, flags_0_go, _out_prepend_T_552}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_6535 = out_prepend_552; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_6536 = _out_T_6535; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_553 = _out_T_6536; // @[RegisterRouter.scala:87:24]
wire out_rimask_653 = |_out_rimask_T_653; // @[RegisterRouter.scala:87:24]
wire out_wimask_653 = &_out_wimask_T_653; // @[RegisterRouter.scala:87:24]
wire out_romask_653 = |_out_romask_T_653; // @[RegisterRouter.scala:87:24]
wire out_womask_653 = &_out_womask_T_653; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_653 = out_rivalid_1_507 & out_rimask_653; // @[RegisterRouter.scala:87:24]
wire _out_T_6538 = out_f_rivalid_653; // @[RegisterRouter.scala:87:24]
wire out_f_roready_653 = out_roready_1_507 & out_romask_653; // @[RegisterRouter.scala:87:24]
wire _out_T_6539 = out_f_roready_653; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_653 = out_wivalid_1_507 & out_wimask_653; // @[RegisterRouter.scala:87:24]
wire out_f_woready_653 = out_woready_1_507 & out_womask_653; // @[RegisterRouter.scala:87:24]
wire _out_T_6540 = ~out_rimask_653; // @[RegisterRouter.scala:87:24]
wire _out_T_6541 = ~out_wimask_653; // @[RegisterRouter.scala:87:24]
wire _out_T_6542 = ~out_romask_653; // @[RegisterRouter.scala:87:24]
wire _out_T_6543 = ~out_womask_653; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_553 = {hi_877, flags_0_go, _out_prepend_T_553}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_6544 = out_prepend_553; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_6545 = _out_T_6544; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_554 = _out_T_6545; // @[RegisterRouter.scala:87:24]
wire out_rimask_654 = |_out_rimask_T_654; // @[RegisterRouter.scala:87:24]
wire out_wimask_654 = &_out_wimask_T_654; // @[RegisterRouter.scala:87:24]
wire out_romask_654 = |_out_romask_T_654; // @[RegisterRouter.scala:87:24]
wire out_womask_654 = &_out_womask_T_654; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_654 = out_rivalid_1_508 & out_rimask_654; // @[RegisterRouter.scala:87:24]
wire _out_T_6547 = out_f_rivalid_654; // @[RegisterRouter.scala:87:24]
wire out_f_roready_654 = out_roready_1_508 & out_romask_654; // @[RegisterRouter.scala:87:24]
wire _out_T_6548 = out_f_roready_654; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_654 = out_wivalid_1_508 & out_wimask_654; // @[RegisterRouter.scala:87:24]
wire out_f_woready_654 = out_woready_1_508 & out_womask_654; // @[RegisterRouter.scala:87:24]
wire _out_T_6549 = ~out_rimask_654; // @[RegisterRouter.scala:87:24]
wire _out_T_6550 = ~out_wimask_654; // @[RegisterRouter.scala:87:24]
wire _out_T_6551 = ~out_romask_654; // @[RegisterRouter.scala:87:24]
wire _out_T_6552 = ~out_womask_654; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_554 = {hi_878, flags_0_go, _out_prepend_T_554}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_6553 = out_prepend_554; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_6554 = _out_T_6553; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_555 = _out_T_6554; // @[RegisterRouter.scala:87:24]
wire out_rimask_655 = |_out_rimask_T_655; // @[RegisterRouter.scala:87:24]
wire out_wimask_655 = &_out_wimask_T_655; // @[RegisterRouter.scala:87:24]
wire out_romask_655 = |_out_romask_T_655; // @[RegisterRouter.scala:87:24]
wire out_womask_655 = &_out_womask_T_655; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_655 = out_rivalid_1_509 & out_rimask_655; // @[RegisterRouter.scala:87:24]
wire _out_T_6556 = out_f_rivalid_655; // @[RegisterRouter.scala:87:24]
wire out_f_roready_655 = out_roready_1_509 & out_romask_655; // @[RegisterRouter.scala:87:24]
wire _out_T_6557 = out_f_roready_655; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_655 = out_wivalid_1_509 & out_wimask_655; // @[RegisterRouter.scala:87:24]
wire out_f_woready_655 = out_woready_1_509 & out_womask_655; // @[RegisterRouter.scala:87:24]
wire _out_T_6558 = ~out_rimask_655; // @[RegisterRouter.scala:87:24]
wire _out_T_6559 = ~out_wimask_655; // @[RegisterRouter.scala:87:24]
wire _out_T_6560 = ~out_romask_655; // @[RegisterRouter.scala:87:24]
wire _out_T_6561 = ~out_womask_655; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_555 = {hi_879, flags_0_go, _out_prepend_T_555}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_6562 = out_prepend_555; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_6563 = _out_T_6562; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_556 = _out_T_6563; // @[RegisterRouter.scala:87:24]
wire out_rimask_656 = |_out_rimask_T_656; // @[RegisterRouter.scala:87:24]
wire out_wimask_656 = &_out_wimask_T_656; // @[RegisterRouter.scala:87:24]
wire out_romask_656 = |_out_romask_T_656; // @[RegisterRouter.scala:87:24]
wire out_womask_656 = &_out_womask_T_656; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_656 = out_rivalid_1_510 & out_rimask_656; // @[RegisterRouter.scala:87:24]
wire _out_T_6565 = out_f_rivalid_656; // @[RegisterRouter.scala:87:24]
wire out_f_roready_656 = out_roready_1_510 & out_romask_656; // @[RegisterRouter.scala:87:24]
wire _out_T_6566 = out_f_roready_656; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_656 = out_wivalid_1_510 & out_wimask_656; // @[RegisterRouter.scala:87:24]
wire out_f_woready_656 = out_woready_1_510 & out_womask_656; // @[RegisterRouter.scala:87:24]
wire _out_T_6567 = ~out_rimask_656; // @[RegisterRouter.scala:87:24]
wire _out_T_6568 = ~out_wimask_656; // @[RegisterRouter.scala:87:24]
wire _out_T_6569 = ~out_romask_656; // @[RegisterRouter.scala:87:24]
wire _out_T_6570 = ~out_womask_656; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_556 = {hi_880, flags_0_go, _out_prepend_T_556}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_6571 = out_prepend_556; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_6572 = _out_T_6571; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_237 = _out_T_6572; // @[MuxLiteral.scala:49:48]
wire out_rimask_657 = |_out_rimask_T_657; // @[RegisterRouter.scala:87:24]
wire out_wimask_657 = &_out_wimask_T_657; // @[RegisterRouter.scala:87:24]
wire out_romask_657 = |_out_romask_T_657; // @[RegisterRouter.scala:87:24]
wire out_womask_657 = &_out_womask_T_657; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_657 = out_rivalid_1_511 & out_rimask_657; // @[RegisterRouter.scala:87:24]
wire _out_T_6574 = out_f_rivalid_657; // @[RegisterRouter.scala:87:24]
wire out_f_roready_657 = out_roready_1_511 & out_romask_657; // @[RegisterRouter.scala:87:24]
wire _out_T_6575 = out_f_roready_657; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_657 = out_wivalid_1_511 & out_wimask_657; // @[RegisterRouter.scala:87:24]
wire _out_T_6576 = out_f_wivalid_657; // @[RegisterRouter.scala:87:24]
wire out_f_woready_657 = out_woready_1_511 & out_womask_657; // @[RegisterRouter.scala:87:24]
wire _out_T_6577 = out_f_woready_657; // @[RegisterRouter.scala:87:24]
wire _out_T_6578 = ~out_rimask_657; // @[RegisterRouter.scala:87:24]
wire _out_T_6579 = ~out_wimask_657; // @[RegisterRouter.scala:87:24]
wire _out_T_6580 = ~out_romask_657; // @[RegisterRouter.scala:87:24]
wire _out_T_6581 = ~out_womask_657; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6583 = _out_T_6582; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_557 = _out_T_6583; // @[RegisterRouter.scala:87:24]
wire out_rimask_658 = |_out_rimask_T_658; // @[RegisterRouter.scala:87:24]
wire out_wimask_658 = &_out_wimask_T_658; // @[RegisterRouter.scala:87:24]
wire out_romask_658 = |_out_romask_T_658; // @[RegisterRouter.scala:87:24]
wire out_womask_658 = &_out_womask_T_658; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_658 = out_rivalid_1_512 & out_rimask_658; // @[RegisterRouter.scala:87:24]
wire _out_T_6585 = out_f_rivalid_658; // @[RegisterRouter.scala:87:24]
wire out_f_roready_658 = out_roready_1_512 & out_romask_658; // @[RegisterRouter.scala:87:24]
wire _out_T_6586 = out_f_roready_658; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_658 = out_wivalid_1_512 & out_wimask_658; // @[RegisterRouter.scala:87:24]
wire _out_T_6587 = out_f_wivalid_658; // @[RegisterRouter.scala:87:24]
wire out_f_woready_658 = out_woready_1_512 & out_womask_658; // @[RegisterRouter.scala:87:24]
wire _out_T_6588 = out_f_woready_658; // @[RegisterRouter.scala:87:24]
wire _out_T_6589 = ~out_rimask_658; // @[RegisterRouter.scala:87:24]
wire _out_T_6590 = ~out_wimask_658; // @[RegisterRouter.scala:87:24]
wire _out_T_6591 = ~out_romask_658; // @[RegisterRouter.scala:87:24]
wire _out_T_6592 = ~out_womask_658; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_557 = {programBufferMem_9, _out_prepend_T_557}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_6593 = out_prepend_557; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_6594 = _out_T_6593; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_558 = _out_T_6594; // @[RegisterRouter.scala:87:24]
wire out_rimask_659 = |_out_rimask_T_659; // @[RegisterRouter.scala:87:24]
wire out_wimask_659 = &_out_wimask_T_659; // @[RegisterRouter.scala:87:24]
wire out_romask_659 = |_out_romask_T_659; // @[RegisterRouter.scala:87:24]
wire out_womask_659 = &_out_womask_T_659; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_659 = out_rivalid_1_513 & out_rimask_659; // @[RegisterRouter.scala:87:24]
wire _out_T_6596 = out_f_rivalid_659; // @[RegisterRouter.scala:87:24]
wire out_f_roready_659 = out_roready_1_513 & out_romask_659; // @[RegisterRouter.scala:87:24]
wire _out_T_6597 = out_f_roready_659; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_659 = out_wivalid_1_513 & out_wimask_659; // @[RegisterRouter.scala:87:24]
wire _out_T_6598 = out_f_wivalid_659; // @[RegisterRouter.scala:87:24]
wire out_f_woready_659 = out_woready_1_513 & out_womask_659; // @[RegisterRouter.scala:87:24]
wire _out_T_6599 = out_f_woready_659; // @[RegisterRouter.scala:87:24]
wire _out_T_6600 = ~out_rimask_659; // @[RegisterRouter.scala:87:24]
wire _out_T_6601 = ~out_wimask_659; // @[RegisterRouter.scala:87:24]
wire _out_T_6602 = ~out_romask_659; // @[RegisterRouter.scala:87:24]
wire _out_T_6603 = ~out_womask_659; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_558 = {programBufferMem_10, _out_prepend_T_558}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_6604 = out_prepend_558; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_6605 = _out_T_6604; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_559 = _out_T_6605; // @[RegisterRouter.scala:87:24]
wire out_rimask_660 = |_out_rimask_T_660; // @[RegisterRouter.scala:87:24]
wire out_wimask_660 = &_out_wimask_T_660; // @[RegisterRouter.scala:87:24]
wire out_romask_660 = |_out_romask_T_660; // @[RegisterRouter.scala:87:24]
wire out_womask_660 = &_out_womask_T_660; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_660 = out_rivalid_1_514 & out_rimask_660; // @[RegisterRouter.scala:87:24]
wire _out_T_6607 = out_f_rivalid_660; // @[RegisterRouter.scala:87:24]
wire out_f_roready_660 = out_roready_1_514 & out_romask_660; // @[RegisterRouter.scala:87:24]
wire _out_T_6608 = out_f_roready_660; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_660 = out_wivalid_1_514 & out_wimask_660; // @[RegisterRouter.scala:87:24]
wire _out_T_6609 = out_f_wivalid_660; // @[RegisterRouter.scala:87:24]
wire out_f_woready_660 = out_woready_1_514 & out_womask_660; // @[RegisterRouter.scala:87:24]
wire _out_T_6610 = out_f_woready_660; // @[RegisterRouter.scala:87:24]
wire _out_T_6611 = ~out_rimask_660; // @[RegisterRouter.scala:87:24]
wire _out_T_6612 = ~out_wimask_660; // @[RegisterRouter.scala:87:24]
wire _out_T_6613 = ~out_romask_660; // @[RegisterRouter.scala:87:24]
wire _out_T_6614 = ~out_womask_660; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_559 = {programBufferMem_11, _out_prepend_T_559}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_6615 = out_prepend_559; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_6616 = _out_T_6615; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_560 = _out_T_6616; // @[RegisterRouter.scala:87:24]
wire out_rimask_661 = |_out_rimask_T_661; // @[RegisterRouter.scala:87:24]
wire out_wimask_661 = &_out_wimask_T_661; // @[RegisterRouter.scala:87:24]
wire out_romask_661 = |_out_romask_T_661; // @[RegisterRouter.scala:87:24]
wire out_womask_661 = &_out_womask_T_661; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_661 = out_rivalid_1_515 & out_rimask_661; // @[RegisterRouter.scala:87:24]
wire _out_T_6618 = out_f_rivalid_661; // @[RegisterRouter.scala:87:24]
wire out_f_roready_661 = out_roready_1_515 & out_romask_661; // @[RegisterRouter.scala:87:24]
wire _out_T_6619 = out_f_roready_661; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_661 = out_wivalid_1_515 & out_wimask_661; // @[RegisterRouter.scala:87:24]
wire _out_T_6620 = out_f_wivalid_661; // @[RegisterRouter.scala:87:24]
wire out_f_woready_661 = out_woready_1_515 & out_womask_661; // @[RegisterRouter.scala:87:24]
wire _out_T_6621 = out_f_woready_661; // @[RegisterRouter.scala:87:24]
wire _out_T_6622 = ~out_rimask_661; // @[RegisterRouter.scala:87:24]
wire _out_T_6623 = ~out_wimask_661; // @[RegisterRouter.scala:87:24]
wire _out_T_6624 = ~out_romask_661; // @[RegisterRouter.scala:87:24]
wire _out_T_6625 = ~out_womask_661; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_560 = {programBufferMem_12, _out_prepend_T_560}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_6626 = out_prepend_560; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_6627 = _out_T_6626; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_561 = _out_T_6627; // @[RegisterRouter.scala:87:24]
wire out_rimask_662 = |_out_rimask_T_662; // @[RegisterRouter.scala:87:24]
wire out_wimask_662 = &_out_wimask_T_662; // @[RegisterRouter.scala:87:24]
wire out_romask_662 = |_out_romask_T_662; // @[RegisterRouter.scala:87:24]
wire out_womask_662 = &_out_womask_T_662; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_662 = out_rivalid_1_516 & out_rimask_662; // @[RegisterRouter.scala:87:24]
wire _out_T_6629 = out_f_rivalid_662; // @[RegisterRouter.scala:87:24]
wire out_f_roready_662 = out_roready_1_516 & out_romask_662; // @[RegisterRouter.scala:87:24]
wire _out_T_6630 = out_f_roready_662; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_662 = out_wivalid_1_516 & out_wimask_662; // @[RegisterRouter.scala:87:24]
wire _out_T_6631 = out_f_wivalid_662; // @[RegisterRouter.scala:87:24]
wire out_f_woready_662 = out_woready_1_516 & out_womask_662; // @[RegisterRouter.scala:87:24]
wire _out_T_6632 = out_f_woready_662; // @[RegisterRouter.scala:87:24]
wire _out_T_6633 = ~out_rimask_662; // @[RegisterRouter.scala:87:24]
wire _out_T_6634 = ~out_wimask_662; // @[RegisterRouter.scala:87:24]
wire _out_T_6635 = ~out_romask_662; // @[RegisterRouter.scala:87:24]
wire _out_T_6636 = ~out_womask_662; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_561 = {programBufferMem_13, _out_prepend_T_561}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_6637 = out_prepend_561; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_6638 = _out_T_6637; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_562 = _out_T_6638; // @[RegisterRouter.scala:87:24]
wire out_rimask_663 = |_out_rimask_T_663; // @[RegisterRouter.scala:87:24]
wire out_wimask_663 = &_out_wimask_T_663; // @[RegisterRouter.scala:87:24]
wire out_romask_663 = |_out_romask_T_663; // @[RegisterRouter.scala:87:24]
wire out_womask_663 = &_out_womask_T_663; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_663 = out_rivalid_1_517 & out_rimask_663; // @[RegisterRouter.scala:87:24]
wire _out_T_6640 = out_f_rivalid_663; // @[RegisterRouter.scala:87:24]
wire out_f_roready_663 = out_roready_1_517 & out_romask_663; // @[RegisterRouter.scala:87:24]
wire _out_T_6641 = out_f_roready_663; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_663 = out_wivalid_1_517 & out_wimask_663; // @[RegisterRouter.scala:87:24]
wire _out_T_6642 = out_f_wivalid_663; // @[RegisterRouter.scala:87:24]
wire out_f_woready_663 = out_woready_1_517 & out_womask_663; // @[RegisterRouter.scala:87:24]
wire _out_T_6643 = out_f_woready_663; // @[RegisterRouter.scala:87:24]
wire _out_T_6644 = ~out_rimask_663; // @[RegisterRouter.scala:87:24]
wire _out_T_6645 = ~out_wimask_663; // @[RegisterRouter.scala:87:24]
wire _out_T_6646 = ~out_romask_663; // @[RegisterRouter.scala:87:24]
wire _out_T_6647 = ~out_womask_663; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_562 = {programBufferMem_14, _out_prepend_T_562}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_6648 = out_prepend_562; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_6649 = _out_T_6648; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_563 = _out_T_6649; // @[RegisterRouter.scala:87:24]
wire out_rimask_664 = |_out_rimask_T_664; // @[RegisterRouter.scala:87:24]
wire out_wimask_664 = &_out_wimask_T_664; // @[RegisterRouter.scala:87:24]
wire out_romask_664 = |_out_romask_T_664; // @[RegisterRouter.scala:87:24]
wire out_womask_664 = &_out_womask_T_664; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_664 = out_rivalid_1_518 & out_rimask_664; // @[RegisterRouter.scala:87:24]
wire _out_T_6651 = out_f_rivalid_664; // @[RegisterRouter.scala:87:24]
wire out_f_roready_664 = out_roready_1_518 & out_romask_664; // @[RegisterRouter.scala:87:24]
wire _out_T_6652 = out_f_roready_664; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_664 = out_wivalid_1_518 & out_wimask_664; // @[RegisterRouter.scala:87:24]
wire _out_T_6653 = out_f_wivalid_664; // @[RegisterRouter.scala:87:24]
wire out_f_woready_664 = out_woready_1_518 & out_womask_664; // @[RegisterRouter.scala:87:24]
wire _out_T_6654 = out_f_woready_664; // @[RegisterRouter.scala:87:24]
wire _out_T_6655 = ~out_rimask_664; // @[RegisterRouter.scala:87:24]
wire _out_T_6656 = ~out_wimask_664; // @[RegisterRouter.scala:87:24]
wire _out_T_6657 = ~out_romask_664; // @[RegisterRouter.scala:87:24]
wire _out_T_6658 = ~out_womask_664; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_563 = {programBufferMem_15, _out_prepend_T_563}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_6659 = out_prepend_563; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_6660 = _out_T_6659; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_105 = _out_T_6660; // @[MuxLiteral.scala:49:48]
wire out_rimask_665 = |_out_rimask_T_665; // @[RegisterRouter.scala:87:24]
wire out_wimask_665 = &_out_wimask_T_665; // @[RegisterRouter.scala:87:24]
wire out_romask_665 = |_out_romask_T_665; // @[RegisterRouter.scala:87:24]
wire out_womask_665 = &_out_womask_T_665; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_665 = out_rivalid_1_519 & out_rimask_665; // @[RegisterRouter.scala:87:24]
wire _out_T_6662 = out_f_rivalid_665; // @[RegisterRouter.scala:87:24]
wire out_f_roready_665 = out_roready_1_519 & out_romask_665; // @[RegisterRouter.scala:87:24]
wire _out_T_6663 = out_f_roready_665; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_665 = out_wivalid_1_519 & out_wimask_665; // @[RegisterRouter.scala:87:24]
wire out_f_woready_665 = out_woready_1_519 & out_womask_665; // @[RegisterRouter.scala:87:24]
wire _out_T_6664 = ~out_rimask_665; // @[RegisterRouter.scala:87:24]
wire _out_T_6665 = ~out_wimask_665; // @[RegisterRouter.scala:87:24]
wire _out_T_6666 = ~out_romask_665; // @[RegisterRouter.scala:87:24]
wire _out_T_6667 = ~out_womask_665; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6669 = _out_T_6668; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_564 = _out_T_6669; // @[RegisterRouter.scala:87:24]
wire out_rimask_666 = |_out_rimask_T_666; // @[RegisterRouter.scala:87:24]
wire out_wimask_666 = &_out_wimask_T_666; // @[RegisterRouter.scala:87:24]
wire out_romask_666 = |_out_romask_T_666; // @[RegisterRouter.scala:87:24]
wire out_womask_666 = &_out_womask_T_666; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_666 = out_rivalid_1_520 & out_rimask_666; // @[RegisterRouter.scala:87:24]
wire _out_T_6671 = out_f_rivalid_666; // @[RegisterRouter.scala:87:24]
wire out_f_roready_666 = out_roready_1_520 & out_romask_666; // @[RegisterRouter.scala:87:24]
wire _out_T_6672 = out_f_roready_666; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_666 = out_wivalid_1_520 & out_wimask_666; // @[RegisterRouter.scala:87:24]
wire out_f_woready_666 = out_woready_1_520 & out_womask_666; // @[RegisterRouter.scala:87:24]
wire _out_T_6673 = ~out_rimask_666; // @[RegisterRouter.scala:87:24]
wire _out_T_6674 = ~out_wimask_666; // @[RegisterRouter.scala:87:24]
wire _out_T_6675 = ~out_romask_666; // @[RegisterRouter.scala:87:24]
wire _out_T_6676 = ~out_womask_666; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_564 = {hi_930, flags_0_go, _out_prepend_T_564}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_6677 = out_prepend_564; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_6678 = _out_T_6677; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_565 = _out_T_6678; // @[RegisterRouter.scala:87:24]
wire out_rimask_667 = |_out_rimask_T_667; // @[RegisterRouter.scala:87:24]
wire out_wimask_667 = &_out_wimask_T_667; // @[RegisterRouter.scala:87:24]
wire out_romask_667 = |_out_romask_T_667; // @[RegisterRouter.scala:87:24]
wire out_womask_667 = &_out_womask_T_667; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_667 = out_rivalid_1_521 & out_rimask_667; // @[RegisterRouter.scala:87:24]
wire _out_T_6680 = out_f_rivalid_667; // @[RegisterRouter.scala:87:24]
wire out_f_roready_667 = out_roready_1_521 & out_romask_667; // @[RegisterRouter.scala:87:24]
wire _out_T_6681 = out_f_roready_667; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_667 = out_wivalid_1_521 & out_wimask_667; // @[RegisterRouter.scala:87:24]
wire out_f_woready_667 = out_woready_1_521 & out_womask_667; // @[RegisterRouter.scala:87:24]
wire _out_T_6682 = ~out_rimask_667; // @[RegisterRouter.scala:87:24]
wire _out_T_6683 = ~out_wimask_667; // @[RegisterRouter.scala:87:24]
wire _out_T_6684 = ~out_romask_667; // @[RegisterRouter.scala:87:24]
wire _out_T_6685 = ~out_womask_667; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_565 = {hi_931, flags_0_go, _out_prepend_T_565}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_6686 = out_prepend_565; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_6687 = _out_T_6686; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_566 = _out_T_6687; // @[RegisterRouter.scala:87:24]
wire out_rimask_668 = |_out_rimask_T_668; // @[RegisterRouter.scala:87:24]
wire out_wimask_668 = &_out_wimask_T_668; // @[RegisterRouter.scala:87:24]
wire out_romask_668 = |_out_romask_T_668; // @[RegisterRouter.scala:87:24]
wire out_womask_668 = &_out_womask_T_668; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_668 = out_rivalid_1_522 & out_rimask_668; // @[RegisterRouter.scala:87:24]
wire _out_T_6689 = out_f_rivalid_668; // @[RegisterRouter.scala:87:24]
wire out_f_roready_668 = out_roready_1_522 & out_romask_668; // @[RegisterRouter.scala:87:24]
wire _out_T_6690 = out_f_roready_668; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_668 = out_wivalid_1_522 & out_wimask_668; // @[RegisterRouter.scala:87:24]
wire out_f_woready_668 = out_woready_1_522 & out_womask_668; // @[RegisterRouter.scala:87:24]
wire _out_T_6691 = ~out_rimask_668; // @[RegisterRouter.scala:87:24]
wire _out_T_6692 = ~out_wimask_668; // @[RegisterRouter.scala:87:24]
wire _out_T_6693 = ~out_romask_668; // @[RegisterRouter.scala:87:24]
wire _out_T_6694 = ~out_womask_668; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_566 = {hi_932, flags_0_go, _out_prepend_T_566}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_6695 = out_prepend_566; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_6696 = _out_T_6695; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_567 = _out_T_6696; // @[RegisterRouter.scala:87:24]
wire out_rimask_669 = |_out_rimask_T_669; // @[RegisterRouter.scala:87:24]
wire out_wimask_669 = &_out_wimask_T_669; // @[RegisterRouter.scala:87:24]
wire out_romask_669 = |_out_romask_T_669; // @[RegisterRouter.scala:87:24]
wire out_womask_669 = &_out_womask_T_669; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_669 = out_rivalid_1_523 & out_rimask_669; // @[RegisterRouter.scala:87:24]
wire _out_T_6698 = out_f_rivalid_669; // @[RegisterRouter.scala:87:24]
wire out_f_roready_669 = out_roready_1_523 & out_romask_669; // @[RegisterRouter.scala:87:24]
wire _out_T_6699 = out_f_roready_669; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_669 = out_wivalid_1_523 & out_wimask_669; // @[RegisterRouter.scala:87:24]
wire out_f_woready_669 = out_woready_1_523 & out_womask_669; // @[RegisterRouter.scala:87:24]
wire _out_T_6700 = ~out_rimask_669; // @[RegisterRouter.scala:87:24]
wire _out_T_6701 = ~out_wimask_669; // @[RegisterRouter.scala:87:24]
wire _out_T_6702 = ~out_romask_669; // @[RegisterRouter.scala:87:24]
wire _out_T_6703 = ~out_womask_669; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_567 = {hi_933, flags_0_go, _out_prepend_T_567}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_6704 = out_prepend_567; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_6705 = _out_T_6704; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_568 = _out_T_6705; // @[RegisterRouter.scala:87:24]
wire out_rimask_670 = |_out_rimask_T_670; // @[RegisterRouter.scala:87:24]
wire out_wimask_670 = &_out_wimask_T_670; // @[RegisterRouter.scala:87:24]
wire out_romask_670 = |_out_romask_T_670; // @[RegisterRouter.scala:87:24]
wire out_womask_670 = &_out_womask_T_670; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_670 = out_rivalid_1_524 & out_rimask_670; // @[RegisterRouter.scala:87:24]
wire _out_T_6707 = out_f_rivalid_670; // @[RegisterRouter.scala:87:24]
wire out_f_roready_670 = out_roready_1_524 & out_romask_670; // @[RegisterRouter.scala:87:24]
wire _out_T_6708 = out_f_roready_670; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_670 = out_wivalid_1_524 & out_wimask_670; // @[RegisterRouter.scala:87:24]
wire out_f_woready_670 = out_woready_1_524 & out_womask_670; // @[RegisterRouter.scala:87:24]
wire _out_T_6709 = ~out_rimask_670; // @[RegisterRouter.scala:87:24]
wire _out_T_6710 = ~out_wimask_670; // @[RegisterRouter.scala:87:24]
wire _out_T_6711 = ~out_romask_670; // @[RegisterRouter.scala:87:24]
wire _out_T_6712 = ~out_womask_670; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_568 = {hi_934, flags_0_go, _out_prepend_T_568}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_6713 = out_prepend_568; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_6714 = _out_T_6713; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_569 = _out_T_6714; // @[RegisterRouter.scala:87:24]
wire out_rimask_671 = |_out_rimask_T_671; // @[RegisterRouter.scala:87:24]
wire out_wimask_671 = &_out_wimask_T_671; // @[RegisterRouter.scala:87:24]
wire out_romask_671 = |_out_romask_T_671; // @[RegisterRouter.scala:87:24]
wire out_womask_671 = &_out_womask_T_671; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_671 = out_rivalid_1_525 & out_rimask_671; // @[RegisterRouter.scala:87:24]
wire _out_T_6716 = out_f_rivalid_671; // @[RegisterRouter.scala:87:24]
wire out_f_roready_671 = out_roready_1_525 & out_romask_671; // @[RegisterRouter.scala:87:24]
wire _out_T_6717 = out_f_roready_671; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_671 = out_wivalid_1_525 & out_wimask_671; // @[RegisterRouter.scala:87:24]
wire out_f_woready_671 = out_woready_1_525 & out_womask_671; // @[RegisterRouter.scala:87:24]
wire _out_T_6718 = ~out_rimask_671; // @[RegisterRouter.scala:87:24]
wire _out_T_6719 = ~out_wimask_671; // @[RegisterRouter.scala:87:24]
wire _out_T_6720 = ~out_romask_671; // @[RegisterRouter.scala:87:24]
wire _out_T_6721 = ~out_womask_671; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_569 = {hi_935, flags_0_go, _out_prepend_T_569}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_6722 = out_prepend_569; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_6723 = _out_T_6722; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_570 = _out_T_6723; // @[RegisterRouter.scala:87:24]
wire out_rimask_672 = |_out_rimask_T_672; // @[RegisterRouter.scala:87:24]
wire out_wimask_672 = &_out_wimask_T_672; // @[RegisterRouter.scala:87:24]
wire out_romask_672 = |_out_romask_T_672; // @[RegisterRouter.scala:87:24]
wire out_womask_672 = &_out_womask_T_672; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_672 = out_rivalid_1_526 & out_rimask_672; // @[RegisterRouter.scala:87:24]
wire _out_T_6725 = out_f_rivalid_672; // @[RegisterRouter.scala:87:24]
wire out_f_roready_672 = out_roready_1_526 & out_romask_672; // @[RegisterRouter.scala:87:24]
wire _out_T_6726 = out_f_roready_672; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_672 = out_wivalid_1_526 & out_wimask_672; // @[RegisterRouter.scala:87:24]
wire out_f_woready_672 = out_woready_1_526 & out_womask_672; // @[RegisterRouter.scala:87:24]
wire _out_T_6727 = ~out_rimask_672; // @[RegisterRouter.scala:87:24]
wire _out_T_6728 = ~out_wimask_672; // @[RegisterRouter.scala:87:24]
wire _out_T_6729 = ~out_romask_672; // @[RegisterRouter.scala:87:24]
wire _out_T_6730 = ~out_womask_672; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_570 = {hi_936, flags_0_go, _out_prepend_T_570}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_6731 = out_prepend_570; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_6732 = _out_T_6731; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_244 = _out_T_6732; // @[MuxLiteral.scala:49:48]
wire out_rimask_673 = |_out_rimask_T_673; // @[RegisterRouter.scala:87:24]
wire out_wimask_673 = &_out_wimask_T_673; // @[RegisterRouter.scala:87:24]
wire out_romask_673 = |_out_romask_T_673; // @[RegisterRouter.scala:87:24]
wire out_womask_673 = &_out_womask_T_673; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_673 = out_rivalid_1_527 & out_rimask_673; // @[RegisterRouter.scala:87:24]
wire _out_T_6734 = out_f_rivalid_673; // @[RegisterRouter.scala:87:24]
wire out_f_roready_673 = out_roready_1_527 & out_romask_673; // @[RegisterRouter.scala:87:24]
wire _out_T_6735 = out_f_roready_673; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_673 = out_wivalid_1_527 & out_wimask_673; // @[RegisterRouter.scala:87:24]
wire out_f_woready_673 = out_woready_1_527 & out_womask_673; // @[RegisterRouter.scala:87:24]
wire _out_T_6736 = ~out_rimask_673; // @[RegisterRouter.scala:87:24]
wire _out_T_6737 = ~out_wimask_673; // @[RegisterRouter.scala:87:24]
wire _out_T_6738 = ~out_romask_673; // @[RegisterRouter.scala:87:24]
wire _out_T_6739 = ~out_womask_673; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6741 = _out_T_6740; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_571 = _out_T_6741; // @[RegisterRouter.scala:87:24]
wire out_rimask_674 = |_out_rimask_T_674; // @[RegisterRouter.scala:87:24]
wire out_wimask_674 = &_out_wimask_T_674; // @[RegisterRouter.scala:87:24]
wire out_romask_674 = |_out_romask_T_674; // @[RegisterRouter.scala:87:24]
wire out_womask_674 = &_out_womask_T_674; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_674 = out_rivalid_1_528 & out_rimask_674; // @[RegisterRouter.scala:87:24]
wire _out_T_6743 = out_f_rivalid_674; // @[RegisterRouter.scala:87:24]
wire out_f_roready_674 = out_roready_1_528 & out_romask_674; // @[RegisterRouter.scala:87:24]
wire _out_T_6744 = out_f_roready_674; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_674 = out_wivalid_1_528 & out_wimask_674; // @[RegisterRouter.scala:87:24]
wire out_f_woready_674 = out_woready_1_528 & out_womask_674; // @[RegisterRouter.scala:87:24]
wire _out_T_6745 = ~out_rimask_674; // @[RegisterRouter.scala:87:24]
wire _out_T_6746 = ~out_wimask_674; // @[RegisterRouter.scala:87:24]
wire _out_T_6747 = ~out_romask_674; // @[RegisterRouter.scala:87:24]
wire _out_T_6748 = ~out_womask_674; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_571 = {hi_306, flags_0_go, _out_prepend_T_571}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_6749 = out_prepend_571; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_6750 = _out_T_6749; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_572 = _out_T_6750; // @[RegisterRouter.scala:87:24]
wire out_rimask_675 = |_out_rimask_T_675; // @[RegisterRouter.scala:87:24]
wire out_wimask_675 = &_out_wimask_T_675; // @[RegisterRouter.scala:87:24]
wire out_romask_675 = |_out_romask_T_675; // @[RegisterRouter.scala:87:24]
wire out_womask_675 = &_out_womask_T_675; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_675 = out_rivalid_1_529 & out_rimask_675; // @[RegisterRouter.scala:87:24]
wire _out_T_6752 = out_f_rivalid_675; // @[RegisterRouter.scala:87:24]
wire out_f_roready_675 = out_roready_1_529 & out_romask_675; // @[RegisterRouter.scala:87:24]
wire _out_T_6753 = out_f_roready_675; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_675 = out_wivalid_1_529 & out_wimask_675; // @[RegisterRouter.scala:87:24]
wire out_f_woready_675 = out_woready_1_529 & out_womask_675; // @[RegisterRouter.scala:87:24]
wire _out_T_6754 = ~out_rimask_675; // @[RegisterRouter.scala:87:24]
wire _out_T_6755 = ~out_wimask_675; // @[RegisterRouter.scala:87:24]
wire _out_T_6756 = ~out_romask_675; // @[RegisterRouter.scala:87:24]
wire _out_T_6757 = ~out_womask_675; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_572 = {hi_307, flags_0_go, _out_prepend_T_572}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_6758 = out_prepend_572; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_6759 = _out_T_6758; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_573 = _out_T_6759; // @[RegisterRouter.scala:87:24]
wire out_rimask_676 = |_out_rimask_T_676; // @[RegisterRouter.scala:87:24]
wire out_wimask_676 = &_out_wimask_T_676; // @[RegisterRouter.scala:87:24]
wire out_romask_676 = |_out_romask_T_676; // @[RegisterRouter.scala:87:24]
wire out_womask_676 = &_out_womask_T_676; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_676 = out_rivalid_1_530 & out_rimask_676; // @[RegisterRouter.scala:87:24]
wire _out_T_6761 = out_f_rivalid_676; // @[RegisterRouter.scala:87:24]
wire out_f_roready_676 = out_roready_1_530 & out_romask_676; // @[RegisterRouter.scala:87:24]
wire _out_T_6762 = out_f_roready_676; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_676 = out_wivalid_1_530 & out_wimask_676; // @[RegisterRouter.scala:87:24]
wire out_f_woready_676 = out_woready_1_530 & out_womask_676; // @[RegisterRouter.scala:87:24]
wire _out_T_6763 = ~out_rimask_676; // @[RegisterRouter.scala:87:24]
wire _out_T_6764 = ~out_wimask_676; // @[RegisterRouter.scala:87:24]
wire _out_T_6765 = ~out_romask_676; // @[RegisterRouter.scala:87:24]
wire _out_T_6766 = ~out_womask_676; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_573 = {hi_308, flags_0_go, _out_prepend_T_573}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_6767 = out_prepend_573; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_6768 = _out_T_6767; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_574 = _out_T_6768; // @[RegisterRouter.scala:87:24]
wire out_rimask_677 = |_out_rimask_T_677; // @[RegisterRouter.scala:87:24]
wire out_wimask_677 = &_out_wimask_T_677; // @[RegisterRouter.scala:87:24]
wire out_romask_677 = |_out_romask_T_677; // @[RegisterRouter.scala:87:24]
wire out_womask_677 = &_out_womask_T_677; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_677 = out_rivalid_1_531 & out_rimask_677; // @[RegisterRouter.scala:87:24]
wire _out_T_6770 = out_f_rivalid_677; // @[RegisterRouter.scala:87:24]
wire out_f_roready_677 = out_roready_1_531 & out_romask_677; // @[RegisterRouter.scala:87:24]
wire _out_T_6771 = out_f_roready_677; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_677 = out_wivalid_1_531 & out_wimask_677; // @[RegisterRouter.scala:87:24]
wire out_f_woready_677 = out_woready_1_531 & out_womask_677; // @[RegisterRouter.scala:87:24]
wire _out_T_6772 = ~out_rimask_677; // @[RegisterRouter.scala:87:24]
wire _out_T_6773 = ~out_wimask_677; // @[RegisterRouter.scala:87:24]
wire _out_T_6774 = ~out_romask_677; // @[RegisterRouter.scala:87:24]
wire _out_T_6775 = ~out_womask_677; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_574 = {hi_309, flags_0_go, _out_prepend_T_574}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_6776 = out_prepend_574; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_6777 = _out_T_6776; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_575 = _out_T_6777; // @[RegisterRouter.scala:87:24]
wire out_rimask_678 = |_out_rimask_T_678; // @[RegisterRouter.scala:87:24]
wire out_wimask_678 = &_out_wimask_T_678; // @[RegisterRouter.scala:87:24]
wire out_romask_678 = |_out_romask_T_678; // @[RegisterRouter.scala:87:24]
wire out_womask_678 = &_out_womask_T_678; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_678 = out_rivalid_1_532 & out_rimask_678; // @[RegisterRouter.scala:87:24]
wire _out_T_6779 = out_f_rivalid_678; // @[RegisterRouter.scala:87:24]
wire out_f_roready_678 = out_roready_1_532 & out_romask_678; // @[RegisterRouter.scala:87:24]
wire _out_T_6780 = out_f_roready_678; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_678 = out_wivalid_1_532 & out_wimask_678; // @[RegisterRouter.scala:87:24]
wire out_f_woready_678 = out_woready_1_532 & out_womask_678; // @[RegisterRouter.scala:87:24]
wire _out_T_6781 = ~out_rimask_678; // @[RegisterRouter.scala:87:24]
wire _out_T_6782 = ~out_wimask_678; // @[RegisterRouter.scala:87:24]
wire _out_T_6783 = ~out_romask_678; // @[RegisterRouter.scala:87:24]
wire _out_T_6784 = ~out_womask_678; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_575 = {hi_310, flags_0_go, _out_prepend_T_575}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_6785 = out_prepend_575; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_6786 = _out_T_6785; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_576 = _out_T_6786; // @[RegisterRouter.scala:87:24]
wire out_rimask_679 = |_out_rimask_T_679; // @[RegisterRouter.scala:87:24]
wire out_wimask_679 = &_out_wimask_T_679; // @[RegisterRouter.scala:87:24]
wire out_romask_679 = |_out_romask_T_679; // @[RegisterRouter.scala:87:24]
wire out_womask_679 = &_out_womask_T_679; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_679 = out_rivalid_1_533 & out_rimask_679; // @[RegisterRouter.scala:87:24]
wire _out_T_6788 = out_f_rivalid_679; // @[RegisterRouter.scala:87:24]
wire out_f_roready_679 = out_roready_1_533 & out_romask_679; // @[RegisterRouter.scala:87:24]
wire _out_T_6789 = out_f_roready_679; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_679 = out_wivalid_1_533 & out_wimask_679; // @[RegisterRouter.scala:87:24]
wire out_f_woready_679 = out_woready_1_533 & out_womask_679; // @[RegisterRouter.scala:87:24]
wire _out_T_6790 = ~out_rimask_679; // @[RegisterRouter.scala:87:24]
wire _out_T_6791 = ~out_wimask_679; // @[RegisterRouter.scala:87:24]
wire _out_T_6792 = ~out_romask_679; // @[RegisterRouter.scala:87:24]
wire _out_T_6793 = ~out_womask_679; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_576 = {hi_311, flags_0_go, _out_prepend_T_576}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_6794 = out_prepend_576; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_6795 = _out_T_6794; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_577 = _out_T_6795; // @[RegisterRouter.scala:87:24]
wire out_rimask_680 = |_out_rimask_T_680; // @[RegisterRouter.scala:87:24]
wire out_wimask_680 = &_out_wimask_T_680; // @[RegisterRouter.scala:87:24]
wire out_romask_680 = |_out_romask_T_680; // @[RegisterRouter.scala:87:24]
wire out_womask_680 = &_out_womask_T_680; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_680 = out_rivalid_1_534 & out_rimask_680; // @[RegisterRouter.scala:87:24]
wire _out_T_6797 = out_f_rivalid_680; // @[RegisterRouter.scala:87:24]
wire out_f_roready_680 = out_roready_1_534 & out_romask_680; // @[RegisterRouter.scala:87:24]
wire _out_T_6798 = out_f_roready_680; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_680 = out_wivalid_1_534 & out_wimask_680; // @[RegisterRouter.scala:87:24]
wire out_f_woready_680 = out_woready_1_534 & out_womask_680; // @[RegisterRouter.scala:87:24]
wire _out_T_6799 = ~out_rimask_680; // @[RegisterRouter.scala:87:24]
wire _out_T_6800 = ~out_wimask_680; // @[RegisterRouter.scala:87:24]
wire _out_T_6801 = ~out_romask_680; // @[RegisterRouter.scala:87:24]
wire _out_T_6802 = ~out_womask_680; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_577 = {hi_312, flags_0_go, _out_prepend_T_577}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_6803 = out_prepend_577; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_6804 = _out_T_6803; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_166 = _out_T_6804; // @[MuxLiteral.scala:49:48]
wire out_rimask_681 = |_out_rimask_T_681; // @[RegisterRouter.scala:87:24]
wire out_wimask_681 = &_out_wimask_T_681; // @[RegisterRouter.scala:87:24]
wire out_romask_681 = |_out_romask_T_681; // @[RegisterRouter.scala:87:24]
wire out_womask_681 = &_out_womask_T_681; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_681 = out_rivalid_1_535 & out_rimask_681; // @[RegisterRouter.scala:87:24]
wire out_f_roready_681 = out_roready_1_535 & out_romask_681; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_681 = out_wivalid_1_535 & out_wimask_681; // @[RegisterRouter.scala:87:24]
wire _out_T_6806 = out_f_wivalid_681; // @[RegisterRouter.scala:87:24]
assign out_f_woready_681 = out_woready_1_535 & out_womask_681; // @[RegisterRouter.scala:87:24]
assign hartHaltedWrEn = out_f_woready_681; // @[RegisterRouter.scala:87:24]
wire _out_T_6807 = out_f_woready_681; // @[RegisterRouter.scala:87:24]
assign hartHaltedId = _out_T_6805; // @[RegisterRouter.scala:87:24]
wire _out_T_6808 = ~out_rimask_681; // @[RegisterRouter.scala:87:24]
wire _out_T_6809 = ~out_wimask_681; // @[RegisterRouter.scala:87:24]
wire _out_T_6810 = ~out_romask_681; // @[RegisterRouter.scala:87:24]
wire _out_T_6811 = ~out_womask_681; // @[RegisterRouter.scala:87:24]
wire out_rimask_682 = |_out_rimask_T_682; // @[RegisterRouter.scala:87:24]
wire out_wimask_682 = &_out_wimask_T_682; // @[RegisterRouter.scala:87:24]
wire out_romask_682 = |_out_romask_T_682; // @[RegisterRouter.scala:87:24]
wire out_womask_682 = &_out_womask_T_682; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_682 = out_rivalid_1_536 & out_rimask_682; // @[RegisterRouter.scala:87:24]
wire out_f_roready_682 = out_roready_1_536 & out_romask_682; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_682 = out_wivalid_1_536 & out_wimask_682; // @[RegisterRouter.scala:87:24]
wire _out_T_6815 = out_f_wivalid_682; // @[RegisterRouter.scala:87:24]
assign out_f_woready_682 = out_woready_1_536 & out_womask_682; // @[RegisterRouter.scala:87:24]
assign hartGoingWrEn = out_f_woready_682; // @[RegisterRouter.scala:87:24]
wire _out_T_6816 = out_f_woready_682; // @[RegisterRouter.scala:87:24]
assign hartGoingId = _out_T_6814; // @[RegisterRouter.scala:87:24]
wire _out_T_6817 = ~out_rimask_682; // @[RegisterRouter.scala:87:24]
wire _out_T_6818 = ~out_wimask_682; // @[RegisterRouter.scala:87:24]
wire _out_T_6819 = ~out_romask_682; // @[RegisterRouter.scala:87:24]
wire _out_T_6820 = ~out_womask_682; // @[RegisterRouter.scala:87:24]
wire out_rimask_683 = |_out_rimask_T_683; // @[RegisterRouter.scala:87:24]
wire out_wimask_683 = &_out_wimask_T_683; // @[RegisterRouter.scala:87:24]
wire out_romask_683 = |_out_romask_T_683; // @[RegisterRouter.scala:87:24]
wire out_womask_683 = &_out_womask_T_683; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_683 = out_rivalid_1_537 & out_rimask_683; // @[RegisterRouter.scala:87:24]
wire _out_T_6824 = out_f_rivalid_683; // @[RegisterRouter.scala:87:24]
wire out_f_roready_683 = out_roready_1_537 & out_romask_683; // @[RegisterRouter.scala:87:24]
wire _out_T_6825 = out_f_roready_683; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_683 = out_wivalid_1_537 & out_wimask_683; // @[RegisterRouter.scala:87:24]
wire out_f_woready_683 = out_woready_1_537 & out_womask_683; // @[RegisterRouter.scala:87:24]
wire _out_T_6826 = ~out_rimask_683; // @[RegisterRouter.scala:87:24]
wire _out_T_6827 = ~out_wimask_683; // @[RegisterRouter.scala:87:24]
wire _out_T_6828 = ~out_romask_683; // @[RegisterRouter.scala:87:24]
wire _out_T_6829 = ~out_womask_683; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6831 = _out_T_6830; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_579 = _out_T_6831; // @[RegisterRouter.scala:87:24]
wire out_rimask_684 = |_out_rimask_T_684; // @[RegisterRouter.scala:87:24]
wire out_wimask_684 = &_out_wimask_T_684; // @[RegisterRouter.scala:87:24]
wire out_romask_684 = |_out_romask_T_684; // @[RegisterRouter.scala:87:24]
wire out_womask_684 = &_out_womask_T_684; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_684 = out_rivalid_1_538 & out_rimask_684; // @[RegisterRouter.scala:87:24]
wire _out_T_6833 = out_f_rivalid_684; // @[RegisterRouter.scala:87:24]
wire out_f_roready_684 = out_roready_1_538 & out_romask_684; // @[RegisterRouter.scala:87:24]
wire _out_T_6834 = out_f_roready_684; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_684 = out_wivalid_1_538 & out_wimask_684; // @[RegisterRouter.scala:87:24]
wire out_f_woready_684 = out_woready_1_538 & out_womask_684; // @[RegisterRouter.scala:87:24]
wire _out_T_6835 = ~out_rimask_684; // @[RegisterRouter.scala:87:24]
wire _out_T_6836 = ~out_wimask_684; // @[RegisterRouter.scala:87:24]
wire _out_T_6837 = ~out_romask_684; // @[RegisterRouter.scala:87:24]
wire _out_T_6838 = ~out_womask_684; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_579 = {hi_162, flags_0_go, _out_prepend_T_579}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_6839 = out_prepend_579; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_6840 = _out_T_6839; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_580 = _out_T_6840; // @[RegisterRouter.scala:87:24]
wire out_rimask_685 = |_out_rimask_T_685; // @[RegisterRouter.scala:87:24]
wire out_wimask_685 = &_out_wimask_T_685; // @[RegisterRouter.scala:87:24]
wire out_romask_685 = |_out_romask_T_685; // @[RegisterRouter.scala:87:24]
wire out_womask_685 = &_out_womask_T_685; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_685 = out_rivalid_1_539 & out_rimask_685; // @[RegisterRouter.scala:87:24]
wire _out_T_6842 = out_f_rivalid_685; // @[RegisterRouter.scala:87:24]
wire out_f_roready_685 = out_roready_1_539 & out_romask_685; // @[RegisterRouter.scala:87:24]
wire _out_T_6843 = out_f_roready_685; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_685 = out_wivalid_1_539 & out_wimask_685; // @[RegisterRouter.scala:87:24]
wire out_f_woready_685 = out_woready_1_539 & out_womask_685; // @[RegisterRouter.scala:87:24]
wire _out_T_6844 = ~out_rimask_685; // @[RegisterRouter.scala:87:24]
wire _out_T_6845 = ~out_wimask_685; // @[RegisterRouter.scala:87:24]
wire _out_T_6846 = ~out_romask_685; // @[RegisterRouter.scala:87:24]
wire _out_T_6847 = ~out_womask_685; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_580 = {hi_163, flags_0_go, _out_prepend_T_580}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_6848 = out_prepend_580; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_6849 = _out_T_6848; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_581 = _out_T_6849; // @[RegisterRouter.scala:87:24]
wire out_rimask_686 = |_out_rimask_T_686; // @[RegisterRouter.scala:87:24]
wire out_wimask_686 = &_out_wimask_T_686; // @[RegisterRouter.scala:87:24]
wire out_romask_686 = |_out_romask_T_686; // @[RegisterRouter.scala:87:24]
wire out_womask_686 = &_out_womask_T_686; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_686 = out_rivalid_1_540 & out_rimask_686; // @[RegisterRouter.scala:87:24]
wire _out_T_6851 = out_f_rivalid_686; // @[RegisterRouter.scala:87:24]
wire out_f_roready_686 = out_roready_1_540 & out_romask_686; // @[RegisterRouter.scala:87:24]
wire _out_T_6852 = out_f_roready_686; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_686 = out_wivalid_1_540 & out_wimask_686; // @[RegisterRouter.scala:87:24]
wire out_f_woready_686 = out_woready_1_540 & out_womask_686; // @[RegisterRouter.scala:87:24]
wire _out_T_6853 = ~out_rimask_686; // @[RegisterRouter.scala:87:24]
wire _out_T_6854 = ~out_wimask_686; // @[RegisterRouter.scala:87:24]
wire _out_T_6855 = ~out_romask_686; // @[RegisterRouter.scala:87:24]
wire _out_T_6856 = ~out_womask_686; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_581 = {hi_164, flags_0_go, _out_prepend_T_581}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_6857 = out_prepend_581; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_6858 = _out_T_6857; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_582 = _out_T_6858; // @[RegisterRouter.scala:87:24]
wire out_rimask_687 = |_out_rimask_T_687; // @[RegisterRouter.scala:87:24]
wire out_wimask_687 = &_out_wimask_T_687; // @[RegisterRouter.scala:87:24]
wire out_romask_687 = |_out_romask_T_687; // @[RegisterRouter.scala:87:24]
wire out_womask_687 = &_out_womask_T_687; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_687 = out_rivalid_1_541 & out_rimask_687; // @[RegisterRouter.scala:87:24]
wire _out_T_6860 = out_f_rivalid_687; // @[RegisterRouter.scala:87:24]
wire out_f_roready_687 = out_roready_1_541 & out_romask_687; // @[RegisterRouter.scala:87:24]
wire _out_T_6861 = out_f_roready_687; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_687 = out_wivalid_1_541 & out_wimask_687; // @[RegisterRouter.scala:87:24]
wire out_f_woready_687 = out_woready_1_541 & out_womask_687; // @[RegisterRouter.scala:87:24]
wire _out_T_6862 = ~out_rimask_687; // @[RegisterRouter.scala:87:24]
wire _out_T_6863 = ~out_wimask_687; // @[RegisterRouter.scala:87:24]
wire _out_T_6864 = ~out_romask_687; // @[RegisterRouter.scala:87:24]
wire _out_T_6865 = ~out_womask_687; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_582 = {hi_165, flags_0_go, _out_prepend_T_582}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_6866 = out_prepend_582; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_6867 = _out_T_6866; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_583 = _out_T_6867; // @[RegisterRouter.scala:87:24]
wire out_rimask_688 = |_out_rimask_T_688; // @[RegisterRouter.scala:87:24]
wire out_wimask_688 = &_out_wimask_T_688; // @[RegisterRouter.scala:87:24]
wire out_romask_688 = |_out_romask_T_688; // @[RegisterRouter.scala:87:24]
wire out_womask_688 = &_out_womask_T_688; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_688 = out_rivalid_1_542 & out_rimask_688; // @[RegisterRouter.scala:87:24]
wire _out_T_6869 = out_f_rivalid_688; // @[RegisterRouter.scala:87:24]
wire out_f_roready_688 = out_roready_1_542 & out_romask_688; // @[RegisterRouter.scala:87:24]
wire _out_T_6870 = out_f_roready_688; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_688 = out_wivalid_1_542 & out_wimask_688; // @[RegisterRouter.scala:87:24]
wire out_f_woready_688 = out_woready_1_542 & out_womask_688; // @[RegisterRouter.scala:87:24]
wire _out_T_6871 = ~out_rimask_688; // @[RegisterRouter.scala:87:24]
wire _out_T_6872 = ~out_wimask_688; // @[RegisterRouter.scala:87:24]
wire _out_T_6873 = ~out_romask_688; // @[RegisterRouter.scala:87:24]
wire _out_T_6874 = ~out_womask_688; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_583 = {hi_166, flags_0_go, _out_prepend_T_583}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_6875 = out_prepend_583; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_6876 = _out_T_6875; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_584 = _out_T_6876; // @[RegisterRouter.scala:87:24]
wire out_rimask_689 = |_out_rimask_T_689; // @[RegisterRouter.scala:87:24]
wire out_wimask_689 = &_out_wimask_T_689; // @[RegisterRouter.scala:87:24]
wire out_romask_689 = |_out_romask_T_689; // @[RegisterRouter.scala:87:24]
wire out_womask_689 = &_out_womask_T_689; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_689 = out_rivalid_1_543 & out_rimask_689; // @[RegisterRouter.scala:87:24]
wire _out_T_6878 = out_f_rivalid_689; // @[RegisterRouter.scala:87:24]
wire out_f_roready_689 = out_roready_1_543 & out_romask_689; // @[RegisterRouter.scala:87:24]
wire _out_T_6879 = out_f_roready_689; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_689 = out_wivalid_1_543 & out_wimask_689; // @[RegisterRouter.scala:87:24]
wire out_f_woready_689 = out_woready_1_543 & out_womask_689; // @[RegisterRouter.scala:87:24]
wire _out_T_6880 = ~out_rimask_689; // @[RegisterRouter.scala:87:24]
wire _out_T_6881 = ~out_wimask_689; // @[RegisterRouter.scala:87:24]
wire _out_T_6882 = ~out_romask_689; // @[RegisterRouter.scala:87:24]
wire _out_T_6883 = ~out_womask_689; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_584 = {hi_167, flags_0_go, _out_prepend_T_584}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_6884 = out_prepend_584; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_6885 = _out_T_6884; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_585 = _out_T_6885; // @[RegisterRouter.scala:87:24]
wire out_rimask_690 = |_out_rimask_T_690; // @[RegisterRouter.scala:87:24]
wire out_wimask_690 = &_out_wimask_T_690; // @[RegisterRouter.scala:87:24]
wire out_romask_690 = |_out_romask_T_690; // @[RegisterRouter.scala:87:24]
wire out_womask_690 = &_out_womask_T_690; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_690 = out_rivalid_1_544 & out_rimask_690; // @[RegisterRouter.scala:87:24]
wire _out_T_6887 = out_f_rivalid_690; // @[RegisterRouter.scala:87:24]
wire out_f_roready_690 = out_roready_1_544 & out_romask_690; // @[RegisterRouter.scala:87:24]
wire _out_T_6888 = out_f_roready_690; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_690 = out_wivalid_1_544 & out_wimask_690; // @[RegisterRouter.scala:87:24]
wire out_f_woready_690 = out_woready_1_544 & out_womask_690; // @[RegisterRouter.scala:87:24]
wire _out_T_6889 = ~out_rimask_690; // @[RegisterRouter.scala:87:24]
wire _out_T_6890 = ~out_wimask_690; // @[RegisterRouter.scala:87:24]
wire _out_T_6891 = ~out_romask_690; // @[RegisterRouter.scala:87:24]
wire _out_T_6892 = ~out_womask_690; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_585 = {hi_168, flags_0_go, _out_prepend_T_585}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_6893 = out_prepend_585; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_6894 = _out_T_6893; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_148 = _out_T_6894; // @[MuxLiteral.scala:49:48]
wire out_rimask_691 = |_out_rimask_T_691; // @[RegisterRouter.scala:87:24]
wire out_wimask_691 = &_out_wimask_T_691; // @[RegisterRouter.scala:87:24]
wire out_romask_691 = |_out_romask_T_691; // @[RegisterRouter.scala:87:24]
wire out_womask_691 = &_out_womask_T_691; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_691 = out_rivalid_1_545 & out_rimask_691; // @[RegisterRouter.scala:87:24]
wire _out_T_6896 = out_f_rivalid_691; // @[RegisterRouter.scala:87:24]
wire out_f_roready_691 = out_roready_1_545 & out_romask_691; // @[RegisterRouter.scala:87:24]
wire _out_T_6897 = out_f_roready_691; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_691 = out_wivalid_1_545 & out_wimask_691; // @[RegisterRouter.scala:87:24]
wire out_f_woready_691 = out_woready_1_545 & out_womask_691; // @[RegisterRouter.scala:87:24]
wire _out_T_6898 = ~out_rimask_691; // @[RegisterRouter.scala:87:24]
wire _out_T_6899 = ~out_wimask_691; // @[RegisterRouter.scala:87:24]
wire _out_T_6900 = ~out_romask_691; // @[RegisterRouter.scala:87:24]
wire _out_T_6901 = ~out_womask_691; // @[RegisterRouter.scala:87:24]
wire out_rimask_692 = |_out_rimask_T_692; // @[RegisterRouter.scala:87:24]
wire out_wimask_692 = &_out_wimask_T_692; // @[RegisterRouter.scala:87:24]
wire out_romask_692 = |_out_romask_T_692; // @[RegisterRouter.scala:87:24]
wire out_womask_692 = &_out_womask_T_692; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_692 = out_rivalid_1_546 & out_rimask_692; // @[RegisterRouter.scala:87:24]
wire _out_T_6905 = out_f_rivalid_692; // @[RegisterRouter.scala:87:24]
wire out_f_roready_692 = out_roready_1_546 & out_romask_692; // @[RegisterRouter.scala:87:24]
wire _out_T_6906 = out_f_roready_692; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_692 = out_wivalid_1_546 & out_wimask_692; // @[RegisterRouter.scala:87:24]
wire out_f_woready_692 = out_woready_1_546 & out_womask_692; // @[RegisterRouter.scala:87:24]
wire _out_T_6907 = ~out_rimask_692; // @[RegisterRouter.scala:87:24]
wire _out_T_6908 = ~out_wimask_692; // @[RegisterRouter.scala:87:24]
wire _out_T_6909 = ~out_romask_692; // @[RegisterRouter.scala:87:24]
wire _out_T_6910 = ~out_womask_692; // @[RegisterRouter.scala:87:24]
wire out_rimask_693 = |_out_rimask_T_693; // @[RegisterRouter.scala:87:24]
wire out_wimask_693 = &_out_wimask_T_693; // @[RegisterRouter.scala:87:24]
wire out_romask_693 = |_out_romask_T_693; // @[RegisterRouter.scala:87:24]
wire out_womask_693 = &_out_womask_T_693; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_693 = out_rivalid_1_547 & out_rimask_693; // @[RegisterRouter.scala:87:24]
wire _out_T_6914 = out_f_rivalid_693; // @[RegisterRouter.scala:87:24]
wire out_f_roready_693 = out_roready_1_547 & out_romask_693; // @[RegisterRouter.scala:87:24]
wire _out_T_6915 = out_f_roready_693; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_693 = out_wivalid_1_547 & out_wimask_693; // @[RegisterRouter.scala:87:24]
wire out_f_woready_693 = out_woready_1_547 & out_womask_693; // @[RegisterRouter.scala:87:24]
wire _out_T_6916 = ~out_rimask_693; // @[RegisterRouter.scala:87:24]
wire _out_T_6917 = ~out_wimask_693; // @[RegisterRouter.scala:87:24]
wire _out_T_6918 = ~out_romask_693; // @[RegisterRouter.scala:87:24]
wire _out_T_6919 = ~out_womask_693; // @[RegisterRouter.scala:87:24]
wire out_rimask_694 = |_out_rimask_T_694; // @[RegisterRouter.scala:87:24]
wire out_wimask_694 = &_out_wimask_T_694; // @[RegisterRouter.scala:87:24]
wire out_romask_694 = |_out_romask_T_694; // @[RegisterRouter.scala:87:24]
wire out_womask_694 = &_out_womask_T_694; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_694 = out_rivalid_1_548 & out_rimask_694; // @[RegisterRouter.scala:87:24]
wire _out_T_6923 = out_f_rivalid_694; // @[RegisterRouter.scala:87:24]
wire out_f_roready_694 = out_roready_1_548 & out_romask_694; // @[RegisterRouter.scala:87:24]
wire _out_T_6924 = out_f_roready_694; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_694 = out_wivalid_1_548 & out_wimask_694; // @[RegisterRouter.scala:87:24]
wire out_f_woready_694 = out_woready_1_548 & out_womask_694; // @[RegisterRouter.scala:87:24]
wire _out_T_6925 = ~out_rimask_694; // @[RegisterRouter.scala:87:24]
wire _out_T_6926 = ~out_wimask_694; // @[RegisterRouter.scala:87:24]
wire _out_T_6927 = ~out_romask_694; // @[RegisterRouter.scala:87:24]
wire _out_T_6928 = ~out_womask_694; // @[RegisterRouter.scala:87:24]
wire out_rimask_695 = |_out_rimask_T_695; // @[RegisterRouter.scala:87:24]
wire out_wimask_695 = &_out_wimask_T_695; // @[RegisterRouter.scala:87:24]
wire out_romask_695 = |_out_romask_T_695; // @[RegisterRouter.scala:87:24]
wire out_womask_695 = &_out_womask_T_695; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_695 = out_rivalid_1_549 & out_rimask_695; // @[RegisterRouter.scala:87:24]
wire _out_T_6932 = out_f_rivalid_695; // @[RegisterRouter.scala:87:24]
wire out_f_roready_695 = out_roready_1_549 & out_romask_695; // @[RegisterRouter.scala:87:24]
wire _out_T_6933 = out_f_roready_695; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_695 = out_wivalid_1_549 & out_wimask_695; // @[RegisterRouter.scala:87:24]
wire out_f_woready_695 = out_woready_1_549 & out_womask_695; // @[RegisterRouter.scala:87:24]
wire _out_T_6934 = ~out_rimask_695; // @[RegisterRouter.scala:87:24]
wire _out_T_6935 = ~out_wimask_695; // @[RegisterRouter.scala:87:24]
wire _out_T_6936 = ~out_romask_695; // @[RegisterRouter.scala:87:24]
wire _out_T_6937 = ~out_womask_695; // @[RegisterRouter.scala:87:24]
wire out_rimask_696 = |_out_rimask_T_696; // @[RegisterRouter.scala:87:24]
wire out_wimask_696 = &_out_wimask_T_696; // @[RegisterRouter.scala:87:24]
wire out_romask_696 = |_out_romask_T_696; // @[RegisterRouter.scala:87:24]
wire out_womask_696 = &_out_womask_T_696; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_696 = out_rivalid_1_550 & out_rimask_696; // @[RegisterRouter.scala:87:24]
wire _out_T_6941 = out_f_rivalid_696; // @[RegisterRouter.scala:87:24]
wire out_f_roready_696 = out_roready_1_550 & out_romask_696; // @[RegisterRouter.scala:87:24]
wire _out_T_6942 = out_f_roready_696; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_696 = out_wivalid_1_550 & out_wimask_696; // @[RegisterRouter.scala:87:24]
wire out_f_woready_696 = out_woready_1_550 & out_womask_696; // @[RegisterRouter.scala:87:24]
wire _out_T_6943 = ~out_rimask_696; // @[RegisterRouter.scala:87:24]
wire _out_T_6944 = ~out_wimask_696; // @[RegisterRouter.scala:87:24]
wire _out_T_6945 = ~out_romask_696; // @[RegisterRouter.scala:87:24]
wire _out_T_6946 = ~out_womask_696; // @[RegisterRouter.scala:87:24]
wire out_rimask_697 = |_out_rimask_T_697; // @[RegisterRouter.scala:87:24]
wire out_wimask_697 = &_out_wimask_T_697; // @[RegisterRouter.scala:87:24]
wire out_romask_697 = |_out_romask_T_697; // @[RegisterRouter.scala:87:24]
wire out_womask_697 = &_out_womask_T_697; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_697 = out_rivalid_1_551 & out_rimask_697; // @[RegisterRouter.scala:87:24]
wire _out_T_6950 = out_f_rivalid_697; // @[RegisterRouter.scala:87:24]
wire out_f_roready_697 = out_roready_1_551 & out_romask_697; // @[RegisterRouter.scala:87:24]
wire _out_T_6951 = out_f_roready_697; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_697 = out_wivalid_1_551 & out_wimask_697; // @[RegisterRouter.scala:87:24]
wire out_f_woready_697 = out_woready_1_551 & out_womask_697; // @[RegisterRouter.scala:87:24]
wire _out_T_6952 = ~out_rimask_697; // @[RegisterRouter.scala:87:24]
wire _out_T_6953 = ~out_wimask_697; // @[RegisterRouter.scala:87:24]
wire _out_T_6954 = ~out_romask_697; // @[RegisterRouter.scala:87:24]
wire _out_T_6955 = ~out_womask_697; // @[RegisterRouter.scala:87:24]
wire out_rimask_698 = |_out_rimask_T_698; // @[RegisterRouter.scala:87:24]
wire out_wimask_698 = &_out_wimask_T_698; // @[RegisterRouter.scala:87:24]
wire out_romask_698 = |_out_romask_T_698; // @[RegisterRouter.scala:87:24]
wire out_womask_698 = &_out_womask_T_698; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_698 = out_rivalid_1_552 & out_rimask_698; // @[RegisterRouter.scala:87:24]
wire _out_T_6959 = out_f_rivalid_698; // @[RegisterRouter.scala:87:24]
wire out_f_roready_698 = out_roready_1_552 & out_romask_698; // @[RegisterRouter.scala:87:24]
wire _out_T_6960 = out_f_roready_698; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_698 = out_wivalid_1_552 & out_wimask_698; // @[RegisterRouter.scala:87:24]
wire out_f_woready_698 = out_woready_1_552 & out_womask_698; // @[RegisterRouter.scala:87:24]
wire _out_T_6961 = ~out_rimask_698; // @[RegisterRouter.scala:87:24]
wire _out_T_6962 = ~out_wimask_698; // @[RegisterRouter.scala:87:24]
wire _out_T_6963 = ~out_romask_698; // @[RegisterRouter.scala:87:24]
wire _out_T_6964 = ~out_womask_698; // @[RegisterRouter.scala:87:24]
wire out_rimask_699 = |_out_rimask_T_699; // @[RegisterRouter.scala:87:24]
wire out_wimask_699 = &_out_wimask_T_699; // @[RegisterRouter.scala:87:24]
wire out_romask_699 = |_out_romask_T_699; // @[RegisterRouter.scala:87:24]
wire out_womask_699 = &_out_womask_T_699; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_699 = out_rivalid_1_553 & out_rimask_699; // @[RegisterRouter.scala:87:24]
wire _out_T_6968 = out_f_rivalid_699; // @[RegisterRouter.scala:87:24]
wire out_f_roready_699 = out_roready_1_553 & out_romask_699; // @[RegisterRouter.scala:87:24]
wire _out_T_6969 = out_f_roready_699; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_699 = out_wivalid_1_553 & out_wimask_699; // @[RegisterRouter.scala:87:24]
wire out_f_woready_699 = out_woready_1_553 & out_womask_699; // @[RegisterRouter.scala:87:24]
wire _out_T_6970 = ~out_rimask_699; // @[RegisterRouter.scala:87:24]
wire _out_T_6971 = ~out_wimask_699; // @[RegisterRouter.scala:87:24]
wire _out_T_6972 = ~out_romask_699; // @[RegisterRouter.scala:87:24]
wire _out_T_6973 = ~out_womask_699; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6975 = _out_T_6974; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_593 = _out_T_6975; // @[RegisterRouter.scala:87:24]
wire out_rimask_700 = |_out_rimask_T_700; // @[RegisterRouter.scala:87:24]
wire out_wimask_700 = &_out_wimask_T_700; // @[RegisterRouter.scala:87:24]
wire out_romask_700 = |_out_romask_T_700; // @[RegisterRouter.scala:87:24]
wire out_womask_700 = &_out_womask_T_700; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_700 = out_rivalid_1_554 & out_rimask_700; // @[RegisterRouter.scala:87:24]
wire _out_T_6977 = out_f_rivalid_700; // @[RegisterRouter.scala:87:24]
wire out_f_roready_700 = out_roready_1_554 & out_romask_700; // @[RegisterRouter.scala:87:24]
wire _out_T_6978 = out_f_roready_700; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_700 = out_wivalid_1_554 & out_wimask_700; // @[RegisterRouter.scala:87:24]
wire out_f_woready_700 = out_woready_1_554 & out_womask_700; // @[RegisterRouter.scala:87:24]
wire _out_T_6979 = ~out_rimask_700; // @[RegisterRouter.scala:87:24]
wire _out_T_6980 = ~out_wimask_700; // @[RegisterRouter.scala:87:24]
wire _out_T_6981 = ~out_romask_700; // @[RegisterRouter.scala:87:24]
wire _out_T_6982 = ~out_womask_700; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_593 = {hi_266, flags_0_go, _out_prepend_T_593}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_6983 = out_prepend_593; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_6984 = _out_T_6983; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_594 = _out_T_6984; // @[RegisterRouter.scala:87:24]
wire out_rimask_701 = |_out_rimask_T_701; // @[RegisterRouter.scala:87:24]
wire out_wimask_701 = &_out_wimask_T_701; // @[RegisterRouter.scala:87:24]
wire out_romask_701 = |_out_romask_T_701; // @[RegisterRouter.scala:87:24]
wire out_womask_701 = &_out_womask_T_701; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_701 = out_rivalid_1_555 & out_rimask_701; // @[RegisterRouter.scala:87:24]
wire _out_T_6986 = out_f_rivalid_701; // @[RegisterRouter.scala:87:24]
wire out_f_roready_701 = out_roready_1_555 & out_romask_701; // @[RegisterRouter.scala:87:24]
wire _out_T_6987 = out_f_roready_701; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_701 = out_wivalid_1_555 & out_wimask_701; // @[RegisterRouter.scala:87:24]
wire out_f_woready_701 = out_woready_1_555 & out_womask_701; // @[RegisterRouter.scala:87:24]
wire _out_T_6988 = ~out_rimask_701; // @[RegisterRouter.scala:87:24]
wire _out_T_6989 = ~out_wimask_701; // @[RegisterRouter.scala:87:24]
wire _out_T_6990 = ~out_romask_701; // @[RegisterRouter.scala:87:24]
wire _out_T_6991 = ~out_womask_701; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_594 = {hi_267, flags_0_go, _out_prepend_T_594}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_6992 = out_prepend_594; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_6993 = _out_T_6992; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_595 = _out_T_6993; // @[RegisterRouter.scala:87:24]
wire out_rimask_702 = |_out_rimask_T_702; // @[RegisterRouter.scala:87:24]
wire out_wimask_702 = &_out_wimask_T_702; // @[RegisterRouter.scala:87:24]
wire out_romask_702 = |_out_romask_T_702; // @[RegisterRouter.scala:87:24]
wire out_womask_702 = &_out_womask_T_702; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_702 = out_rivalid_1_556 & out_rimask_702; // @[RegisterRouter.scala:87:24]
wire _out_T_6995 = out_f_rivalid_702; // @[RegisterRouter.scala:87:24]
wire out_f_roready_702 = out_roready_1_556 & out_romask_702; // @[RegisterRouter.scala:87:24]
wire _out_T_6996 = out_f_roready_702; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_702 = out_wivalid_1_556 & out_wimask_702; // @[RegisterRouter.scala:87:24]
wire out_f_woready_702 = out_woready_1_556 & out_womask_702; // @[RegisterRouter.scala:87:24]
wire _out_T_6997 = ~out_rimask_702; // @[RegisterRouter.scala:87:24]
wire _out_T_6998 = ~out_wimask_702; // @[RegisterRouter.scala:87:24]
wire _out_T_6999 = ~out_romask_702; // @[RegisterRouter.scala:87:24]
wire _out_T_7000 = ~out_womask_702; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_595 = {hi_268, flags_0_go, _out_prepend_T_595}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_7001 = out_prepend_595; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_7002 = _out_T_7001; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_596 = _out_T_7002; // @[RegisterRouter.scala:87:24]
wire out_rimask_703 = |_out_rimask_T_703; // @[RegisterRouter.scala:87:24]
wire out_wimask_703 = &_out_wimask_T_703; // @[RegisterRouter.scala:87:24]
wire out_romask_703 = |_out_romask_T_703; // @[RegisterRouter.scala:87:24]
wire out_womask_703 = &_out_womask_T_703; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_703 = out_rivalid_1_557 & out_rimask_703; // @[RegisterRouter.scala:87:24]
wire _out_T_7004 = out_f_rivalid_703; // @[RegisterRouter.scala:87:24]
wire out_f_roready_703 = out_roready_1_557 & out_romask_703; // @[RegisterRouter.scala:87:24]
wire _out_T_7005 = out_f_roready_703; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_703 = out_wivalid_1_557 & out_wimask_703; // @[RegisterRouter.scala:87:24]
wire out_f_woready_703 = out_woready_1_557 & out_womask_703; // @[RegisterRouter.scala:87:24]
wire _out_T_7006 = ~out_rimask_703; // @[RegisterRouter.scala:87:24]
wire _out_T_7007 = ~out_wimask_703; // @[RegisterRouter.scala:87:24]
wire _out_T_7008 = ~out_romask_703; // @[RegisterRouter.scala:87:24]
wire _out_T_7009 = ~out_womask_703; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_596 = {hi_269, flags_0_go, _out_prepend_T_596}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_7010 = out_prepend_596; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_7011 = _out_T_7010; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_597 = _out_T_7011; // @[RegisterRouter.scala:87:24]
wire out_rimask_704 = |_out_rimask_T_704; // @[RegisterRouter.scala:87:24]
wire out_wimask_704 = &_out_wimask_T_704; // @[RegisterRouter.scala:87:24]
wire out_romask_704 = |_out_romask_T_704; // @[RegisterRouter.scala:87:24]
wire out_womask_704 = &_out_womask_T_704; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_704 = out_rivalid_1_558 & out_rimask_704; // @[RegisterRouter.scala:87:24]
wire _out_T_7013 = out_f_rivalid_704; // @[RegisterRouter.scala:87:24]
wire out_f_roready_704 = out_roready_1_558 & out_romask_704; // @[RegisterRouter.scala:87:24]
wire _out_T_7014 = out_f_roready_704; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_704 = out_wivalid_1_558 & out_wimask_704; // @[RegisterRouter.scala:87:24]
wire out_f_woready_704 = out_woready_1_558 & out_womask_704; // @[RegisterRouter.scala:87:24]
wire _out_T_7015 = ~out_rimask_704; // @[RegisterRouter.scala:87:24]
wire _out_T_7016 = ~out_wimask_704; // @[RegisterRouter.scala:87:24]
wire _out_T_7017 = ~out_romask_704; // @[RegisterRouter.scala:87:24]
wire _out_T_7018 = ~out_womask_704; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_597 = {hi_270, flags_0_go, _out_prepend_T_597}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_7019 = out_prepend_597; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_7020 = _out_T_7019; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_598 = _out_T_7020; // @[RegisterRouter.scala:87:24]
wire out_rimask_705 = |_out_rimask_T_705; // @[RegisterRouter.scala:87:24]
wire out_wimask_705 = &_out_wimask_T_705; // @[RegisterRouter.scala:87:24]
wire out_romask_705 = |_out_romask_T_705; // @[RegisterRouter.scala:87:24]
wire out_womask_705 = &_out_womask_T_705; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_705 = out_rivalid_1_559 & out_rimask_705; // @[RegisterRouter.scala:87:24]
wire _out_T_7022 = out_f_rivalid_705; // @[RegisterRouter.scala:87:24]
wire out_f_roready_705 = out_roready_1_559 & out_romask_705; // @[RegisterRouter.scala:87:24]
wire _out_T_7023 = out_f_roready_705; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_705 = out_wivalid_1_559 & out_wimask_705; // @[RegisterRouter.scala:87:24]
wire out_f_woready_705 = out_woready_1_559 & out_womask_705; // @[RegisterRouter.scala:87:24]
wire _out_T_7024 = ~out_rimask_705; // @[RegisterRouter.scala:87:24]
wire _out_T_7025 = ~out_wimask_705; // @[RegisterRouter.scala:87:24]
wire _out_T_7026 = ~out_romask_705; // @[RegisterRouter.scala:87:24]
wire _out_T_7027 = ~out_womask_705; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_598 = {hi_271, flags_0_go, _out_prepend_T_598}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_7028 = out_prepend_598; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_7029 = _out_T_7028; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_599 = _out_T_7029; // @[RegisterRouter.scala:87:24]
wire out_rimask_706 = |_out_rimask_T_706; // @[RegisterRouter.scala:87:24]
wire out_wimask_706 = &_out_wimask_T_706; // @[RegisterRouter.scala:87:24]
wire out_romask_706 = |_out_romask_T_706; // @[RegisterRouter.scala:87:24]
wire out_womask_706 = &_out_womask_T_706; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_706 = out_rivalid_1_560 & out_rimask_706; // @[RegisterRouter.scala:87:24]
wire _out_T_7031 = out_f_rivalid_706; // @[RegisterRouter.scala:87:24]
wire out_f_roready_706 = out_roready_1_560 & out_romask_706; // @[RegisterRouter.scala:87:24]
wire _out_T_7032 = out_f_roready_706; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_706 = out_wivalid_1_560 & out_wimask_706; // @[RegisterRouter.scala:87:24]
wire out_f_woready_706 = out_woready_1_560 & out_womask_706; // @[RegisterRouter.scala:87:24]
wire _out_T_7033 = ~out_rimask_706; // @[RegisterRouter.scala:87:24]
wire _out_T_7034 = ~out_wimask_706; // @[RegisterRouter.scala:87:24]
wire _out_T_7035 = ~out_romask_706; // @[RegisterRouter.scala:87:24]
wire _out_T_7036 = ~out_womask_706; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_599 = {hi_272, flags_0_go, _out_prepend_T_599}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_7037 = out_prepend_599; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_7038 = _out_T_7037; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_161 = _out_T_7038; // @[MuxLiteral.scala:49:48]
wire out_rimask_707 = |_out_rimask_T_707; // @[RegisterRouter.scala:87:24]
wire out_wimask_707 = &_out_wimask_T_707; // @[RegisterRouter.scala:87:24]
wire out_romask_707 = |_out_romask_T_707; // @[RegisterRouter.scala:87:24]
wire out_womask_707 = &_out_womask_T_707; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_707 = out_rivalid_1_561 & out_rimask_707; // @[RegisterRouter.scala:87:24]
wire _out_T_7040 = out_f_rivalid_707; // @[RegisterRouter.scala:87:24]
wire out_f_roready_707 = out_roready_1_561 & out_romask_707; // @[RegisterRouter.scala:87:24]
wire _out_T_7041 = out_f_roready_707; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_707 = out_wivalid_1_561 & out_wimask_707; // @[RegisterRouter.scala:87:24]
wire out_f_woready_707 = out_woready_1_561 & out_womask_707; // @[RegisterRouter.scala:87:24]
wire _out_T_7042 = ~out_rimask_707; // @[RegisterRouter.scala:87:24]
wire _out_T_7043 = ~out_wimask_707; // @[RegisterRouter.scala:87:24]
wire _out_T_7044 = ~out_romask_707; // @[RegisterRouter.scala:87:24]
wire _out_T_7045 = ~out_womask_707; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7047 = _out_T_7046; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_600 = _out_T_7047; // @[RegisterRouter.scala:87:24]
wire out_rimask_708 = |_out_rimask_T_708; // @[RegisterRouter.scala:87:24]
wire out_wimask_708 = &_out_wimask_T_708; // @[RegisterRouter.scala:87:24]
wire out_romask_708 = |_out_romask_T_708; // @[RegisterRouter.scala:87:24]
wire out_womask_708 = &_out_womask_T_708; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_708 = out_rivalid_1_562 & out_rimask_708; // @[RegisterRouter.scala:87:24]
wire _out_T_7049 = out_f_rivalid_708; // @[RegisterRouter.scala:87:24]
wire out_f_roready_708 = out_roready_1_562 & out_romask_708; // @[RegisterRouter.scala:87:24]
wire _out_T_7050 = out_f_roready_708; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_708 = out_wivalid_1_562 & out_wimask_708; // @[RegisterRouter.scala:87:24]
wire out_f_woready_708 = out_woready_1_562 & out_womask_708; // @[RegisterRouter.scala:87:24]
wire _out_T_7051 = ~out_rimask_708; // @[RegisterRouter.scala:87:24]
wire _out_T_7052 = ~out_wimask_708; // @[RegisterRouter.scala:87:24]
wire _out_T_7053 = ~out_romask_708; // @[RegisterRouter.scala:87:24]
wire _out_T_7054 = ~out_womask_708; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_600 = {hi_418, flags_0_go, _out_prepend_T_600}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_7055 = out_prepend_600; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_7056 = _out_T_7055; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_601 = _out_T_7056; // @[RegisterRouter.scala:87:24]
wire out_rimask_709 = |_out_rimask_T_709; // @[RegisterRouter.scala:87:24]
wire out_wimask_709 = &_out_wimask_T_709; // @[RegisterRouter.scala:87:24]
wire out_romask_709 = |_out_romask_T_709; // @[RegisterRouter.scala:87:24]
wire out_womask_709 = &_out_womask_T_709; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_709 = out_rivalid_1_563 & out_rimask_709; // @[RegisterRouter.scala:87:24]
wire _out_T_7058 = out_f_rivalid_709; // @[RegisterRouter.scala:87:24]
wire out_f_roready_709 = out_roready_1_563 & out_romask_709; // @[RegisterRouter.scala:87:24]
wire _out_T_7059 = out_f_roready_709; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_709 = out_wivalid_1_563 & out_wimask_709; // @[RegisterRouter.scala:87:24]
wire out_f_woready_709 = out_woready_1_563 & out_womask_709; // @[RegisterRouter.scala:87:24]
wire _out_T_7060 = ~out_rimask_709; // @[RegisterRouter.scala:87:24]
wire _out_T_7061 = ~out_wimask_709; // @[RegisterRouter.scala:87:24]
wire _out_T_7062 = ~out_romask_709; // @[RegisterRouter.scala:87:24]
wire _out_T_7063 = ~out_womask_709; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_601 = {hi_419, flags_0_go, _out_prepend_T_601}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_7064 = out_prepend_601; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_7065 = _out_T_7064; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_602 = _out_T_7065; // @[RegisterRouter.scala:87:24]
wire out_rimask_710 = |_out_rimask_T_710; // @[RegisterRouter.scala:87:24]
wire out_wimask_710 = &_out_wimask_T_710; // @[RegisterRouter.scala:87:24]
wire out_romask_710 = |_out_romask_T_710; // @[RegisterRouter.scala:87:24]
wire out_womask_710 = &_out_womask_T_710; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_710 = out_rivalid_1_564 & out_rimask_710; // @[RegisterRouter.scala:87:24]
wire _out_T_7067 = out_f_rivalid_710; // @[RegisterRouter.scala:87:24]
wire out_f_roready_710 = out_roready_1_564 & out_romask_710; // @[RegisterRouter.scala:87:24]
wire _out_T_7068 = out_f_roready_710; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_710 = out_wivalid_1_564 & out_wimask_710; // @[RegisterRouter.scala:87:24]
wire out_f_woready_710 = out_woready_1_564 & out_womask_710; // @[RegisterRouter.scala:87:24]
wire _out_T_7069 = ~out_rimask_710; // @[RegisterRouter.scala:87:24]
wire _out_T_7070 = ~out_wimask_710; // @[RegisterRouter.scala:87:24]
wire _out_T_7071 = ~out_romask_710; // @[RegisterRouter.scala:87:24]
wire _out_T_7072 = ~out_womask_710; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_602 = {hi_420, flags_0_go, _out_prepend_T_602}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_7073 = out_prepend_602; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_7074 = _out_T_7073; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_603 = _out_T_7074; // @[RegisterRouter.scala:87:24]
wire out_rimask_711 = |_out_rimask_T_711; // @[RegisterRouter.scala:87:24]
wire out_wimask_711 = &_out_wimask_T_711; // @[RegisterRouter.scala:87:24]
wire out_romask_711 = |_out_romask_T_711; // @[RegisterRouter.scala:87:24]
wire out_womask_711 = &_out_womask_T_711; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_711 = out_rivalid_1_565 & out_rimask_711; // @[RegisterRouter.scala:87:24]
wire _out_T_7076 = out_f_rivalid_711; // @[RegisterRouter.scala:87:24]
wire out_f_roready_711 = out_roready_1_565 & out_romask_711; // @[RegisterRouter.scala:87:24]
wire _out_T_7077 = out_f_roready_711; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_711 = out_wivalid_1_565 & out_wimask_711; // @[RegisterRouter.scala:87:24]
wire out_f_woready_711 = out_woready_1_565 & out_womask_711; // @[RegisterRouter.scala:87:24]
wire _out_T_7078 = ~out_rimask_711; // @[RegisterRouter.scala:87:24]
wire _out_T_7079 = ~out_wimask_711; // @[RegisterRouter.scala:87:24]
wire _out_T_7080 = ~out_romask_711; // @[RegisterRouter.scala:87:24]
wire _out_T_7081 = ~out_womask_711; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_603 = {hi_421, flags_0_go, _out_prepend_T_603}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_7082 = out_prepend_603; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_7083 = _out_T_7082; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_604 = _out_T_7083; // @[RegisterRouter.scala:87:24]
wire out_rimask_712 = |_out_rimask_T_712; // @[RegisterRouter.scala:87:24]
wire out_wimask_712 = &_out_wimask_T_712; // @[RegisterRouter.scala:87:24]
wire out_romask_712 = |_out_romask_T_712; // @[RegisterRouter.scala:87:24]
wire out_womask_712 = &_out_womask_T_712; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_712 = out_rivalid_1_566 & out_rimask_712; // @[RegisterRouter.scala:87:24]
wire _out_T_7085 = out_f_rivalid_712; // @[RegisterRouter.scala:87:24]
wire out_f_roready_712 = out_roready_1_566 & out_romask_712; // @[RegisterRouter.scala:87:24]
wire _out_T_7086 = out_f_roready_712; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_712 = out_wivalid_1_566 & out_wimask_712; // @[RegisterRouter.scala:87:24]
wire out_f_woready_712 = out_woready_1_566 & out_womask_712; // @[RegisterRouter.scala:87:24]
wire _out_T_7087 = ~out_rimask_712; // @[RegisterRouter.scala:87:24]
wire _out_T_7088 = ~out_wimask_712; // @[RegisterRouter.scala:87:24]
wire _out_T_7089 = ~out_romask_712; // @[RegisterRouter.scala:87:24]
wire _out_T_7090 = ~out_womask_712; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_604 = {hi_422, flags_0_go, _out_prepend_T_604}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_7091 = out_prepend_604; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_7092 = _out_T_7091; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_605 = _out_T_7092; // @[RegisterRouter.scala:87:24]
wire out_rimask_713 = |_out_rimask_T_713; // @[RegisterRouter.scala:87:24]
wire out_wimask_713 = &_out_wimask_T_713; // @[RegisterRouter.scala:87:24]
wire out_romask_713 = |_out_romask_T_713; // @[RegisterRouter.scala:87:24]
wire out_womask_713 = &_out_womask_T_713; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_713 = out_rivalid_1_567 & out_rimask_713; // @[RegisterRouter.scala:87:24]
wire _out_T_7094 = out_f_rivalid_713; // @[RegisterRouter.scala:87:24]
wire out_f_roready_713 = out_roready_1_567 & out_romask_713; // @[RegisterRouter.scala:87:24]
wire _out_T_7095 = out_f_roready_713; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_713 = out_wivalid_1_567 & out_wimask_713; // @[RegisterRouter.scala:87:24]
wire out_f_woready_713 = out_woready_1_567 & out_womask_713; // @[RegisterRouter.scala:87:24]
wire _out_T_7096 = ~out_rimask_713; // @[RegisterRouter.scala:87:24]
wire _out_T_7097 = ~out_wimask_713; // @[RegisterRouter.scala:87:24]
wire _out_T_7098 = ~out_romask_713; // @[RegisterRouter.scala:87:24]
wire _out_T_7099 = ~out_womask_713; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_605 = {hi_423, flags_0_go, _out_prepend_T_605}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_7100 = out_prepend_605; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_7101 = _out_T_7100; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_606 = _out_T_7101; // @[RegisterRouter.scala:87:24]
wire out_rimask_714 = |_out_rimask_T_714; // @[RegisterRouter.scala:87:24]
wire out_wimask_714 = &_out_wimask_T_714; // @[RegisterRouter.scala:87:24]
wire out_romask_714 = |_out_romask_T_714; // @[RegisterRouter.scala:87:24]
wire out_womask_714 = &_out_womask_T_714; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_714 = out_rivalid_1_568 & out_rimask_714; // @[RegisterRouter.scala:87:24]
wire _out_T_7103 = out_f_rivalid_714; // @[RegisterRouter.scala:87:24]
wire out_f_roready_714 = out_roready_1_568 & out_romask_714; // @[RegisterRouter.scala:87:24]
wire _out_T_7104 = out_f_roready_714; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_714 = out_wivalid_1_568 & out_wimask_714; // @[RegisterRouter.scala:87:24]
wire out_f_woready_714 = out_woready_1_568 & out_womask_714; // @[RegisterRouter.scala:87:24]
wire _out_T_7105 = ~out_rimask_714; // @[RegisterRouter.scala:87:24]
wire _out_T_7106 = ~out_wimask_714; // @[RegisterRouter.scala:87:24]
wire _out_T_7107 = ~out_romask_714; // @[RegisterRouter.scala:87:24]
wire _out_T_7108 = ~out_womask_714; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_606 = {hi_424, flags_0_go, _out_prepend_T_606}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_7109 = out_prepend_606; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_7110 = _out_T_7109; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_180 = _out_T_7110; // @[MuxLiteral.scala:49:48]
wire out_rimask_715 = |_out_rimask_T_715; // @[RegisterRouter.scala:87:24]
wire out_wimask_715 = &_out_wimask_T_715; // @[RegisterRouter.scala:87:24]
wire out_romask_715 = |_out_romask_T_715; // @[RegisterRouter.scala:87:24]
wire out_womask_715 = &_out_womask_T_715; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_715 = out_rivalid_1_569 & out_rimask_715; // @[RegisterRouter.scala:87:24]
wire _out_T_7112 = out_f_rivalid_715; // @[RegisterRouter.scala:87:24]
wire out_f_roready_715 = out_roready_1_569 & out_romask_715; // @[RegisterRouter.scala:87:24]
wire _out_T_7113 = out_f_roready_715; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_715 = out_wivalid_1_569 & out_wimask_715; // @[RegisterRouter.scala:87:24]
wire out_f_woready_715 = out_woready_1_569 & out_womask_715; // @[RegisterRouter.scala:87:24]
wire _out_T_7114 = ~out_rimask_715; // @[RegisterRouter.scala:87:24]
wire _out_T_7115 = ~out_wimask_715; // @[RegisterRouter.scala:87:24]
wire _out_T_7116 = ~out_romask_715; // @[RegisterRouter.scala:87:24]
wire _out_T_7117 = ~out_womask_715; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7119 = _out_T_7118; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_607 = _out_T_7119; // @[RegisterRouter.scala:87:24]
wire out_rimask_716 = |_out_rimask_T_716; // @[RegisterRouter.scala:87:24]
wire out_wimask_716 = &_out_wimask_T_716; // @[RegisterRouter.scala:87:24]
wire out_romask_716 = |_out_romask_T_716; // @[RegisterRouter.scala:87:24]
wire out_womask_716 = &_out_womask_T_716; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_716 = out_rivalid_1_570 & out_rimask_716; // @[RegisterRouter.scala:87:24]
wire _out_T_7121 = out_f_rivalid_716; // @[RegisterRouter.scala:87:24]
wire out_f_roready_716 = out_roready_1_570 & out_romask_716; // @[RegisterRouter.scala:87:24]
wire _out_T_7122 = out_f_roready_716; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_716 = out_wivalid_1_570 & out_wimask_716; // @[RegisterRouter.scala:87:24]
wire out_f_woready_716 = out_woready_1_570 & out_womask_716; // @[RegisterRouter.scala:87:24]
wire _out_T_7123 = ~out_rimask_716; // @[RegisterRouter.scala:87:24]
wire _out_T_7124 = ~out_wimask_716; // @[RegisterRouter.scala:87:24]
wire _out_T_7125 = ~out_romask_716; // @[RegisterRouter.scala:87:24]
wire _out_T_7126 = ~out_womask_716; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_607 = {hi_170, flags_0_go, _out_prepend_T_607}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_7127 = out_prepend_607; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_7128 = _out_T_7127; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_608 = _out_T_7128; // @[RegisterRouter.scala:87:24]
wire out_rimask_717 = |_out_rimask_T_717; // @[RegisterRouter.scala:87:24]
wire out_wimask_717 = &_out_wimask_T_717; // @[RegisterRouter.scala:87:24]
wire out_romask_717 = |_out_romask_T_717; // @[RegisterRouter.scala:87:24]
wire out_womask_717 = &_out_womask_T_717; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_717 = out_rivalid_1_571 & out_rimask_717; // @[RegisterRouter.scala:87:24]
wire _out_T_7130 = out_f_rivalid_717; // @[RegisterRouter.scala:87:24]
wire out_f_roready_717 = out_roready_1_571 & out_romask_717; // @[RegisterRouter.scala:87:24]
wire _out_T_7131 = out_f_roready_717; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_717 = out_wivalid_1_571 & out_wimask_717; // @[RegisterRouter.scala:87:24]
wire out_f_woready_717 = out_woready_1_571 & out_womask_717; // @[RegisterRouter.scala:87:24]
wire _out_T_7132 = ~out_rimask_717; // @[RegisterRouter.scala:87:24]
wire _out_T_7133 = ~out_wimask_717; // @[RegisterRouter.scala:87:24]
wire _out_T_7134 = ~out_romask_717; // @[RegisterRouter.scala:87:24]
wire _out_T_7135 = ~out_womask_717; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_608 = {hi_171, flags_0_go, _out_prepend_T_608}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_7136 = out_prepend_608; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_7137 = _out_T_7136; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_609 = _out_T_7137; // @[RegisterRouter.scala:87:24]
wire out_rimask_718 = |_out_rimask_T_718; // @[RegisterRouter.scala:87:24]
wire out_wimask_718 = &_out_wimask_T_718; // @[RegisterRouter.scala:87:24]
wire out_romask_718 = |_out_romask_T_718; // @[RegisterRouter.scala:87:24]
wire out_womask_718 = &_out_womask_T_718; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_718 = out_rivalid_1_572 & out_rimask_718; // @[RegisterRouter.scala:87:24]
wire _out_T_7139 = out_f_rivalid_718; // @[RegisterRouter.scala:87:24]
wire out_f_roready_718 = out_roready_1_572 & out_romask_718; // @[RegisterRouter.scala:87:24]
wire _out_T_7140 = out_f_roready_718; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_718 = out_wivalid_1_572 & out_wimask_718; // @[RegisterRouter.scala:87:24]
wire out_f_woready_718 = out_woready_1_572 & out_womask_718; // @[RegisterRouter.scala:87:24]
wire _out_T_7141 = ~out_rimask_718; // @[RegisterRouter.scala:87:24]
wire _out_T_7142 = ~out_wimask_718; // @[RegisterRouter.scala:87:24]
wire _out_T_7143 = ~out_romask_718; // @[RegisterRouter.scala:87:24]
wire _out_T_7144 = ~out_womask_718; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_609 = {hi_172, flags_0_go, _out_prepend_T_609}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_7145 = out_prepend_609; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_7146 = _out_T_7145; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_610 = _out_T_7146; // @[RegisterRouter.scala:87:24]
wire out_rimask_719 = |_out_rimask_T_719; // @[RegisterRouter.scala:87:24]
wire out_wimask_719 = &_out_wimask_T_719; // @[RegisterRouter.scala:87:24]
wire out_romask_719 = |_out_romask_T_719; // @[RegisterRouter.scala:87:24]
wire out_womask_719 = &_out_womask_T_719; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_719 = out_rivalid_1_573 & out_rimask_719; // @[RegisterRouter.scala:87:24]
wire _out_T_7148 = out_f_rivalid_719; // @[RegisterRouter.scala:87:24]
wire out_f_roready_719 = out_roready_1_573 & out_romask_719; // @[RegisterRouter.scala:87:24]
wire _out_T_7149 = out_f_roready_719; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_719 = out_wivalid_1_573 & out_wimask_719; // @[RegisterRouter.scala:87:24]
wire out_f_woready_719 = out_woready_1_573 & out_womask_719; // @[RegisterRouter.scala:87:24]
wire _out_T_7150 = ~out_rimask_719; // @[RegisterRouter.scala:87:24]
wire _out_T_7151 = ~out_wimask_719; // @[RegisterRouter.scala:87:24]
wire _out_T_7152 = ~out_romask_719; // @[RegisterRouter.scala:87:24]
wire _out_T_7153 = ~out_womask_719; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_610 = {hi_173, flags_0_go, _out_prepend_T_610}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_7154 = out_prepend_610; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_7155 = _out_T_7154; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_611 = _out_T_7155; // @[RegisterRouter.scala:87:24]
wire out_rimask_720 = |_out_rimask_T_720; // @[RegisterRouter.scala:87:24]
wire out_wimask_720 = &_out_wimask_T_720; // @[RegisterRouter.scala:87:24]
wire out_romask_720 = |_out_romask_T_720; // @[RegisterRouter.scala:87:24]
wire out_womask_720 = &_out_womask_T_720; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_720 = out_rivalid_1_574 & out_rimask_720; // @[RegisterRouter.scala:87:24]
wire _out_T_7157 = out_f_rivalid_720; // @[RegisterRouter.scala:87:24]
wire out_f_roready_720 = out_roready_1_574 & out_romask_720; // @[RegisterRouter.scala:87:24]
wire _out_T_7158 = out_f_roready_720; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_720 = out_wivalid_1_574 & out_wimask_720; // @[RegisterRouter.scala:87:24]
wire out_f_woready_720 = out_woready_1_574 & out_womask_720; // @[RegisterRouter.scala:87:24]
wire _out_T_7159 = ~out_rimask_720; // @[RegisterRouter.scala:87:24]
wire _out_T_7160 = ~out_wimask_720; // @[RegisterRouter.scala:87:24]
wire _out_T_7161 = ~out_romask_720; // @[RegisterRouter.scala:87:24]
wire _out_T_7162 = ~out_womask_720; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_611 = {hi_174, flags_0_go, _out_prepend_T_611}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_7163 = out_prepend_611; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_7164 = _out_T_7163; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_612 = _out_T_7164; // @[RegisterRouter.scala:87:24]
wire out_rimask_721 = |_out_rimask_T_721; // @[RegisterRouter.scala:87:24]
wire out_wimask_721 = &_out_wimask_T_721; // @[RegisterRouter.scala:87:24]
wire out_romask_721 = |_out_romask_T_721; // @[RegisterRouter.scala:87:24]
wire out_womask_721 = &_out_womask_T_721; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_721 = out_rivalid_1_575 & out_rimask_721; // @[RegisterRouter.scala:87:24]
wire _out_T_7166 = out_f_rivalid_721; // @[RegisterRouter.scala:87:24]
wire out_f_roready_721 = out_roready_1_575 & out_romask_721; // @[RegisterRouter.scala:87:24]
wire _out_T_7167 = out_f_roready_721; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_721 = out_wivalid_1_575 & out_wimask_721; // @[RegisterRouter.scala:87:24]
wire out_f_woready_721 = out_woready_1_575 & out_womask_721; // @[RegisterRouter.scala:87:24]
wire _out_T_7168 = ~out_rimask_721; // @[RegisterRouter.scala:87:24]
wire _out_T_7169 = ~out_wimask_721; // @[RegisterRouter.scala:87:24]
wire _out_T_7170 = ~out_romask_721; // @[RegisterRouter.scala:87:24]
wire _out_T_7171 = ~out_womask_721; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_612 = {hi_175, flags_0_go, _out_prepend_T_612}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_7172 = out_prepend_612; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_7173 = _out_T_7172; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_613 = _out_T_7173; // @[RegisterRouter.scala:87:24]
wire out_rimask_722 = |_out_rimask_T_722; // @[RegisterRouter.scala:87:24]
wire out_wimask_722 = &_out_wimask_T_722; // @[RegisterRouter.scala:87:24]
wire out_romask_722 = |_out_romask_T_722; // @[RegisterRouter.scala:87:24]
wire out_womask_722 = &_out_womask_T_722; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_722 = out_rivalid_1_576 & out_rimask_722; // @[RegisterRouter.scala:87:24]
wire _out_T_7175 = out_f_rivalid_722; // @[RegisterRouter.scala:87:24]
wire out_f_roready_722 = out_roready_1_576 & out_romask_722; // @[RegisterRouter.scala:87:24]
wire _out_T_7176 = out_f_roready_722; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_722 = out_wivalid_1_576 & out_wimask_722; // @[RegisterRouter.scala:87:24]
wire out_f_woready_722 = out_woready_1_576 & out_womask_722; // @[RegisterRouter.scala:87:24]
wire _out_T_7177 = ~out_rimask_722; // @[RegisterRouter.scala:87:24]
wire _out_T_7178 = ~out_wimask_722; // @[RegisterRouter.scala:87:24]
wire _out_T_7179 = ~out_romask_722; // @[RegisterRouter.scala:87:24]
wire _out_T_7180 = ~out_womask_722; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_613 = {hi_176, flags_0_go, _out_prepend_T_613}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_7181 = out_prepend_613; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_7182 = _out_T_7181; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_149 = _out_T_7182; // @[MuxLiteral.scala:49:48]
wire out_rimask_723 = |_out_rimask_T_723; // @[RegisterRouter.scala:87:24]
wire out_wimask_723 = &_out_wimask_T_723; // @[RegisterRouter.scala:87:24]
wire out_romask_723 = |_out_romask_T_723; // @[RegisterRouter.scala:87:24]
wire out_womask_723 = &_out_womask_T_723; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_723 = out_rivalid_1_577 & out_rimask_723; // @[RegisterRouter.scala:87:24]
wire _out_T_7184 = out_f_rivalid_723; // @[RegisterRouter.scala:87:24]
wire out_f_roready_723 = out_roready_1_577 & out_romask_723; // @[RegisterRouter.scala:87:24]
wire _out_T_7185 = out_f_roready_723; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_723 = out_wivalid_1_577 & out_wimask_723; // @[RegisterRouter.scala:87:24]
wire out_f_woready_723 = out_woready_1_577 & out_womask_723; // @[RegisterRouter.scala:87:24]
wire _out_T_7186 = ~out_rimask_723; // @[RegisterRouter.scala:87:24]
wire _out_T_7187 = ~out_wimask_723; // @[RegisterRouter.scala:87:24]
wire _out_T_7188 = ~out_romask_723; // @[RegisterRouter.scala:87:24]
wire _out_T_7189 = ~out_womask_723; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7191 = _out_T_7190; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_614 = _out_T_7191; // @[RegisterRouter.scala:87:24]
wire out_rimask_724 = |_out_rimask_T_724; // @[RegisterRouter.scala:87:24]
wire out_wimask_724 = &_out_wimask_T_724; // @[RegisterRouter.scala:87:24]
wire out_romask_724 = |_out_romask_T_724; // @[RegisterRouter.scala:87:24]
wire out_womask_724 = &_out_womask_T_724; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_724 = out_rivalid_1_578 & out_rimask_724; // @[RegisterRouter.scala:87:24]
wire _out_T_7193 = out_f_rivalid_724; // @[RegisterRouter.scala:87:24]
wire out_f_roready_724 = out_roready_1_578 & out_romask_724; // @[RegisterRouter.scala:87:24]
wire _out_T_7194 = out_f_roready_724; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_724 = out_wivalid_1_578 & out_wimask_724; // @[RegisterRouter.scala:87:24]
wire out_f_woready_724 = out_woready_1_578 & out_womask_724; // @[RegisterRouter.scala:87:24]
wire _out_T_7195 = ~out_rimask_724; // @[RegisterRouter.scala:87:24]
wire _out_T_7196 = ~out_wimask_724; // @[RegisterRouter.scala:87:24]
wire _out_T_7197 = ~out_romask_724; // @[RegisterRouter.scala:87:24]
wire _out_T_7198 = ~out_womask_724; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_614 = {hi_386, flags_0_go, _out_prepend_T_614}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_7199 = out_prepend_614; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_7200 = _out_T_7199; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_615 = _out_T_7200; // @[RegisterRouter.scala:87:24]
wire out_rimask_725 = |_out_rimask_T_725; // @[RegisterRouter.scala:87:24]
wire out_wimask_725 = &_out_wimask_T_725; // @[RegisterRouter.scala:87:24]
wire out_romask_725 = |_out_romask_T_725; // @[RegisterRouter.scala:87:24]
wire out_womask_725 = &_out_womask_T_725; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_725 = out_rivalid_1_579 & out_rimask_725; // @[RegisterRouter.scala:87:24]
wire _out_T_7202 = out_f_rivalid_725; // @[RegisterRouter.scala:87:24]
wire out_f_roready_725 = out_roready_1_579 & out_romask_725; // @[RegisterRouter.scala:87:24]
wire _out_T_7203 = out_f_roready_725; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_725 = out_wivalid_1_579 & out_wimask_725; // @[RegisterRouter.scala:87:24]
wire out_f_woready_725 = out_woready_1_579 & out_womask_725; // @[RegisterRouter.scala:87:24]
wire _out_T_7204 = ~out_rimask_725; // @[RegisterRouter.scala:87:24]
wire _out_T_7205 = ~out_wimask_725; // @[RegisterRouter.scala:87:24]
wire _out_T_7206 = ~out_romask_725; // @[RegisterRouter.scala:87:24]
wire _out_T_7207 = ~out_womask_725; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_615 = {hi_387, flags_0_go, _out_prepend_T_615}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_7208 = out_prepend_615; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_7209 = _out_T_7208; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_616 = _out_T_7209; // @[RegisterRouter.scala:87:24]
wire out_rimask_726 = |_out_rimask_T_726; // @[RegisterRouter.scala:87:24]
wire out_wimask_726 = &_out_wimask_T_726; // @[RegisterRouter.scala:87:24]
wire out_romask_726 = |_out_romask_T_726; // @[RegisterRouter.scala:87:24]
wire out_womask_726 = &_out_womask_T_726; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_726 = out_rivalid_1_580 & out_rimask_726; // @[RegisterRouter.scala:87:24]
wire _out_T_7211 = out_f_rivalid_726; // @[RegisterRouter.scala:87:24]
wire out_f_roready_726 = out_roready_1_580 & out_romask_726; // @[RegisterRouter.scala:87:24]
wire _out_T_7212 = out_f_roready_726; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_726 = out_wivalid_1_580 & out_wimask_726; // @[RegisterRouter.scala:87:24]
wire out_f_woready_726 = out_woready_1_580 & out_womask_726; // @[RegisterRouter.scala:87:24]
wire _out_T_7213 = ~out_rimask_726; // @[RegisterRouter.scala:87:24]
wire _out_T_7214 = ~out_wimask_726; // @[RegisterRouter.scala:87:24]
wire _out_T_7215 = ~out_romask_726; // @[RegisterRouter.scala:87:24]
wire _out_T_7216 = ~out_womask_726; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_616 = {hi_388, flags_0_go, _out_prepend_T_616}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_7217 = out_prepend_616; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_7218 = _out_T_7217; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_617 = _out_T_7218; // @[RegisterRouter.scala:87:24]
wire out_rimask_727 = |_out_rimask_T_727; // @[RegisterRouter.scala:87:24]
wire out_wimask_727 = &_out_wimask_T_727; // @[RegisterRouter.scala:87:24]
wire out_romask_727 = |_out_romask_T_727; // @[RegisterRouter.scala:87:24]
wire out_womask_727 = &_out_womask_T_727; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_727 = out_rivalid_1_581 & out_rimask_727; // @[RegisterRouter.scala:87:24]
wire _out_T_7220 = out_f_rivalid_727; // @[RegisterRouter.scala:87:24]
wire out_f_roready_727 = out_roready_1_581 & out_romask_727; // @[RegisterRouter.scala:87:24]
wire _out_T_7221 = out_f_roready_727; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_727 = out_wivalid_1_581 & out_wimask_727; // @[RegisterRouter.scala:87:24]
wire out_f_woready_727 = out_woready_1_581 & out_womask_727; // @[RegisterRouter.scala:87:24]
wire _out_T_7222 = ~out_rimask_727; // @[RegisterRouter.scala:87:24]
wire _out_T_7223 = ~out_wimask_727; // @[RegisterRouter.scala:87:24]
wire _out_T_7224 = ~out_romask_727; // @[RegisterRouter.scala:87:24]
wire _out_T_7225 = ~out_womask_727; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_617 = {hi_389, flags_0_go, _out_prepend_T_617}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_7226 = out_prepend_617; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_7227 = _out_T_7226; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_618 = _out_T_7227; // @[RegisterRouter.scala:87:24]
wire out_rimask_728 = |_out_rimask_T_728; // @[RegisterRouter.scala:87:24]
wire out_wimask_728 = &_out_wimask_T_728; // @[RegisterRouter.scala:87:24]
wire out_romask_728 = |_out_romask_T_728; // @[RegisterRouter.scala:87:24]
wire out_womask_728 = &_out_womask_T_728; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_728 = out_rivalid_1_582 & out_rimask_728; // @[RegisterRouter.scala:87:24]
wire _out_T_7229 = out_f_rivalid_728; // @[RegisterRouter.scala:87:24]
wire out_f_roready_728 = out_roready_1_582 & out_romask_728; // @[RegisterRouter.scala:87:24]
wire _out_T_7230 = out_f_roready_728; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_728 = out_wivalid_1_582 & out_wimask_728; // @[RegisterRouter.scala:87:24]
wire out_f_woready_728 = out_woready_1_582 & out_womask_728; // @[RegisterRouter.scala:87:24]
wire _out_T_7231 = ~out_rimask_728; // @[RegisterRouter.scala:87:24]
wire _out_T_7232 = ~out_wimask_728; // @[RegisterRouter.scala:87:24]
wire _out_T_7233 = ~out_romask_728; // @[RegisterRouter.scala:87:24]
wire _out_T_7234 = ~out_womask_728; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_618 = {hi_390, flags_0_go, _out_prepend_T_618}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_7235 = out_prepend_618; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_7236 = _out_T_7235; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_619 = _out_T_7236; // @[RegisterRouter.scala:87:24]
wire out_rimask_729 = |_out_rimask_T_729; // @[RegisterRouter.scala:87:24]
wire out_wimask_729 = &_out_wimask_T_729; // @[RegisterRouter.scala:87:24]
wire out_romask_729 = |_out_romask_T_729; // @[RegisterRouter.scala:87:24]
wire out_womask_729 = &_out_womask_T_729; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_729 = out_rivalid_1_583 & out_rimask_729; // @[RegisterRouter.scala:87:24]
wire _out_T_7238 = out_f_rivalid_729; // @[RegisterRouter.scala:87:24]
wire out_f_roready_729 = out_roready_1_583 & out_romask_729; // @[RegisterRouter.scala:87:24]
wire _out_T_7239 = out_f_roready_729; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_729 = out_wivalid_1_583 & out_wimask_729; // @[RegisterRouter.scala:87:24]
wire out_f_woready_729 = out_woready_1_583 & out_womask_729; // @[RegisterRouter.scala:87:24]
wire _out_T_7240 = ~out_rimask_729; // @[RegisterRouter.scala:87:24]
wire _out_T_7241 = ~out_wimask_729; // @[RegisterRouter.scala:87:24]
wire _out_T_7242 = ~out_romask_729; // @[RegisterRouter.scala:87:24]
wire _out_T_7243 = ~out_womask_729; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_619 = {hi_391, flags_0_go, _out_prepend_T_619}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_7244 = out_prepend_619; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_7245 = _out_T_7244; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_620 = _out_T_7245; // @[RegisterRouter.scala:87:24]
wire out_rimask_730 = |_out_rimask_T_730; // @[RegisterRouter.scala:87:24]
wire out_wimask_730 = &_out_wimask_T_730; // @[RegisterRouter.scala:87:24]
wire out_romask_730 = |_out_romask_T_730; // @[RegisterRouter.scala:87:24]
wire out_womask_730 = &_out_womask_T_730; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_730 = out_rivalid_1_584 & out_rimask_730; // @[RegisterRouter.scala:87:24]
wire _out_T_7247 = out_f_rivalid_730; // @[RegisterRouter.scala:87:24]
wire out_f_roready_730 = out_roready_1_584 & out_romask_730; // @[RegisterRouter.scala:87:24]
wire _out_T_7248 = out_f_roready_730; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_730 = out_wivalid_1_584 & out_wimask_730; // @[RegisterRouter.scala:87:24]
wire out_f_woready_730 = out_woready_1_584 & out_womask_730; // @[RegisterRouter.scala:87:24]
wire _out_T_7249 = ~out_rimask_730; // @[RegisterRouter.scala:87:24]
wire _out_T_7250 = ~out_wimask_730; // @[RegisterRouter.scala:87:24]
wire _out_T_7251 = ~out_romask_730; // @[RegisterRouter.scala:87:24]
wire _out_T_7252 = ~out_womask_730; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_620 = {hi_392, flags_0_go, _out_prepend_T_620}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_7253 = out_prepend_620; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_7254 = _out_T_7253; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_176 = _out_T_7254; // @[MuxLiteral.scala:49:48]
wire out_rimask_731 = |_out_rimask_T_731; // @[RegisterRouter.scala:87:24]
wire out_wimask_731 = &_out_wimask_T_731; // @[RegisterRouter.scala:87:24]
wire out_romask_731 = |_out_romask_T_731; // @[RegisterRouter.scala:87:24]
wire out_womask_731 = &_out_womask_T_731; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_731 = out_rivalid_1_585 & out_rimask_731; // @[RegisterRouter.scala:87:24]
wire _out_T_7256 = out_f_rivalid_731; // @[RegisterRouter.scala:87:24]
wire out_f_roready_731 = out_roready_1_585 & out_romask_731; // @[RegisterRouter.scala:87:24]
wire _out_T_7257 = out_f_roready_731; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_731 = out_wivalid_1_585 & out_wimask_731; // @[RegisterRouter.scala:87:24]
wire out_f_woready_731 = out_woready_1_585 & out_womask_731; // @[RegisterRouter.scala:87:24]
wire _out_T_7258 = ~out_rimask_731; // @[RegisterRouter.scala:87:24]
wire _out_T_7259 = ~out_wimask_731; // @[RegisterRouter.scala:87:24]
wire _out_T_7260 = ~out_romask_731; // @[RegisterRouter.scala:87:24]
wire _out_T_7261 = ~out_womask_731; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7263 = _out_T_7262; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_621 = _out_T_7263; // @[RegisterRouter.scala:87:24]
wire out_rimask_732 = |_out_rimask_T_732; // @[RegisterRouter.scala:87:24]
wire out_wimask_732 = &_out_wimask_T_732; // @[RegisterRouter.scala:87:24]
wire out_romask_732 = |_out_romask_T_732; // @[RegisterRouter.scala:87:24]
wire out_womask_732 = &_out_womask_T_732; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_732 = out_rivalid_1_586 & out_rimask_732; // @[RegisterRouter.scala:87:24]
wire _out_T_7265 = out_f_rivalid_732; // @[RegisterRouter.scala:87:24]
wire out_f_roready_732 = out_roready_1_586 & out_romask_732; // @[RegisterRouter.scala:87:24]
wire _out_T_7266 = out_f_roready_732; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_732 = out_wivalid_1_586 & out_wimask_732; // @[RegisterRouter.scala:87:24]
wire out_f_woready_732 = out_woready_1_586 & out_womask_732; // @[RegisterRouter.scala:87:24]
wire _out_T_7267 = ~out_rimask_732; // @[RegisterRouter.scala:87:24]
wire _out_T_7268 = ~out_wimask_732; // @[RegisterRouter.scala:87:24]
wire _out_T_7269 = ~out_romask_732; // @[RegisterRouter.scala:87:24]
wire _out_T_7270 = ~out_womask_732; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_621 = {hi_506, flags_0_go, _out_prepend_T_621}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_7271 = out_prepend_621; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_7272 = _out_T_7271; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_622 = _out_T_7272; // @[RegisterRouter.scala:87:24]
wire out_rimask_733 = |_out_rimask_T_733; // @[RegisterRouter.scala:87:24]
wire out_wimask_733 = &_out_wimask_T_733; // @[RegisterRouter.scala:87:24]
wire out_romask_733 = |_out_romask_T_733; // @[RegisterRouter.scala:87:24]
wire out_womask_733 = &_out_womask_T_733; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_733 = out_rivalid_1_587 & out_rimask_733; // @[RegisterRouter.scala:87:24]
wire _out_T_7274 = out_f_rivalid_733; // @[RegisterRouter.scala:87:24]
wire out_f_roready_733 = out_roready_1_587 & out_romask_733; // @[RegisterRouter.scala:87:24]
wire _out_T_7275 = out_f_roready_733; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_733 = out_wivalid_1_587 & out_wimask_733; // @[RegisterRouter.scala:87:24]
wire out_f_woready_733 = out_woready_1_587 & out_womask_733; // @[RegisterRouter.scala:87:24]
wire _out_T_7276 = ~out_rimask_733; // @[RegisterRouter.scala:87:24]
wire _out_T_7277 = ~out_wimask_733; // @[RegisterRouter.scala:87:24]
wire _out_T_7278 = ~out_romask_733; // @[RegisterRouter.scala:87:24]
wire _out_T_7279 = ~out_womask_733; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_622 = {hi_507, flags_0_go, _out_prepend_T_622}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_7280 = out_prepend_622; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_7281 = _out_T_7280; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_623 = _out_T_7281; // @[RegisterRouter.scala:87:24]
wire out_rimask_734 = |_out_rimask_T_734; // @[RegisterRouter.scala:87:24]
wire out_wimask_734 = &_out_wimask_T_734; // @[RegisterRouter.scala:87:24]
wire out_romask_734 = |_out_romask_T_734; // @[RegisterRouter.scala:87:24]
wire out_womask_734 = &_out_womask_T_734; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_734 = out_rivalid_1_588 & out_rimask_734; // @[RegisterRouter.scala:87:24]
wire _out_T_7283 = out_f_rivalid_734; // @[RegisterRouter.scala:87:24]
wire out_f_roready_734 = out_roready_1_588 & out_romask_734; // @[RegisterRouter.scala:87:24]
wire _out_T_7284 = out_f_roready_734; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_734 = out_wivalid_1_588 & out_wimask_734; // @[RegisterRouter.scala:87:24]
wire out_f_woready_734 = out_woready_1_588 & out_womask_734; // @[RegisterRouter.scala:87:24]
wire _out_T_7285 = ~out_rimask_734; // @[RegisterRouter.scala:87:24]
wire _out_T_7286 = ~out_wimask_734; // @[RegisterRouter.scala:87:24]
wire _out_T_7287 = ~out_romask_734; // @[RegisterRouter.scala:87:24]
wire _out_T_7288 = ~out_womask_734; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_623 = {hi_508, flags_0_go, _out_prepend_T_623}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_7289 = out_prepend_623; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_7290 = _out_T_7289; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_624 = _out_T_7290; // @[RegisterRouter.scala:87:24]
wire out_rimask_735 = |_out_rimask_T_735; // @[RegisterRouter.scala:87:24]
wire out_wimask_735 = &_out_wimask_T_735; // @[RegisterRouter.scala:87:24]
wire out_romask_735 = |_out_romask_T_735; // @[RegisterRouter.scala:87:24]
wire out_womask_735 = &_out_womask_T_735; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_735 = out_rivalid_1_589 & out_rimask_735; // @[RegisterRouter.scala:87:24]
wire _out_T_7292 = out_f_rivalid_735; // @[RegisterRouter.scala:87:24]
wire out_f_roready_735 = out_roready_1_589 & out_romask_735; // @[RegisterRouter.scala:87:24]
wire _out_T_7293 = out_f_roready_735; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_735 = out_wivalid_1_589 & out_wimask_735; // @[RegisterRouter.scala:87:24]
wire out_f_woready_735 = out_woready_1_589 & out_womask_735; // @[RegisterRouter.scala:87:24]
wire _out_T_7294 = ~out_rimask_735; // @[RegisterRouter.scala:87:24]
wire _out_T_7295 = ~out_wimask_735; // @[RegisterRouter.scala:87:24]
wire _out_T_7296 = ~out_romask_735; // @[RegisterRouter.scala:87:24]
wire _out_T_7297 = ~out_womask_735; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_624 = {hi_509, flags_0_go, _out_prepend_T_624}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_7298 = out_prepend_624; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_7299 = _out_T_7298; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_625 = _out_T_7299; // @[RegisterRouter.scala:87:24]
wire out_rimask_736 = |_out_rimask_T_736; // @[RegisterRouter.scala:87:24]
wire out_wimask_736 = &_out_wimask_T_736; // @[RegisterRouter.scala:87:24]
wire out_romask_736 = |_out_romask_T_736; // @[RegisterRouter.scala:87:24]
wire out_womask_736 = &_out_womask_T_736; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_736 = out_rivalid_1_590 & out_rimask_736; // @[RegisterRouter.scala:87:24]
wire _out_T_7301 = out_f_rivalid_736; // @[RegisterRouter.scala:87:24]
wire out_f_roready_736 = out_roready_1_590 & out_romask_736; // @[RegisterRouter.scala:87:24]
wire _out_T_7302 = out_f_roready_736; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_736 = out_wivalid_1_590 & out_wimask_736; // @[RegisterRouter.scala:87:24]
wire out_f_woready_736 = out_woready_1_590 & out_womask_736; // @[RegisterRouter.scala:87:24]
wire _out_T_7303 = ~out_rimask_736; // @[RegisterRouter.scala:87:24]
wire _out_T_7304 = ~out_wimask_736; // @[RegisterRouter.scala:87:24]
wire _out_T_7305 = ~out_romask_736; // @[RegisterRouter.scala:87:24]
wire _out_T_7306 = ~out_womask_736; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_625 = {hi_510, flags_0_go, _out_prepend_T_625}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_7307 = out_prepend_625; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_7308 = _out_T_7307; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_626 = _out_T_7308; // @[RegisterRouter.scala:87:24]
wire out_rimask_737 = |_out_rimask_T_737; // @[RegisterRouter.scala:87:24]
wire out_wimask_737 = &_out_wimask_T_737; // @[RegisterRouter.scala:87:24]
wire out_romask_737 = |_out_romask_T_737; // @[RegisterRouter.scala:87:24]
wire out_womask_737 = &_out_womask_T_737; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_737 = out_rivalid_1_591 & out_rimask_737; // @[RegisterRouter.scala:87:24]
wire _out_T_7310 = out_f_rivalid_737; // @[RegisterRouter.scala:87:24]
wire out_f_roready_737 = out_roready_1_591 & out_romask_737; // @[RegisterRouter.scala:87:24]
wire _out_T_7311 = out_f_roready_737; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_737 = out_wivalid_1_591 & out_wimask_737; // @[RegisterRouter.scala:87:24]
wire out_f_woready_737 = out_woready_1_591 & out_womask_737; // @[RegisterRouter.scala:87:24]
wire _out_T_7312 = ~out_rimask_737; // @[RegisterRouter.scala:87:24]
wire _out_T_7313 = ~out_wimask_737; // @[RegisterRouter.scala:87:24]
wire _out_T_7314 = ~out_romask_737; // @[RegisterRouter.scala:87:24]
wire _out_T_7315 = ~out_womask_737; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_626 = {hi_511, flags_0_go, _out_prepend_T_626}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_7316 = out_prepend_626; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_7317 = _out_T_7316; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_627 = _out_T_7317; // @[RegisterRouter.scala:87:24]
wire out_rimask_738 = |_out_rimask_T_738; // @[RegisterRouter.scala:87:24]
wire out_wimask_738 = &_out_wimask_T_738; // @[RegisterRouter.scala:87:24]
wire out_romask_738 = |_out_romask_T_738; // @[RegisterRouter.scala:87:24]
wire out_womask_738 = &_out_womask_T_738; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_738 = out_rivalid_1_592 & out_rimask_738; // @[RegisterRouter.scala:87:24]
wire _out_T_7319 = out_f_rivalid_738; // @[RegisterRouter.scala:87:24]
wire out_f_roready_738 = out_roready_1_592 & out_romask_738; // @[RegisterRouter.scala:87:24]
wire _out_T_7320 = out_f_roready_738; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_738 = out_wivalid_1_592 & out_wimask_738; // @[RegisterRouter.scala:87:24]
wire out_f_woready_738 = out_woready_1_592 & out_womask_738; // @[RegisterRouter.scala:87:24]
wire _out_T_7321 = ~out_rimask_738; // @[RegisterRouter.scala:87:24]
wire _out_T_7322 = ~out_wimask_738; // @[RegisterRouter.scala:87:24]
wire _out_T_7323 = ~out_romask_738; // @[RegisterRouter.scala:87:24]
wire _out_T_7324 = ~out_womask_738; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_627 = {hi_512, flags_0_go, _out_prepend_T_627}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_7325 = out_prepend_627; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_7326 = _out_T_7325; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_191 = _out_T_7326; // @[MuxLiteral.scala:49:48]
wire out_rimask_739 = |_out_rimask_T_739; // @[RegisterRouter.scala:87:24]
wire out_wimask_739 = &_out_wimask_T_739; // @[RegisterRouter.scala:87:24]
wire out_romask_739 = |_out_romask_T_739; // @[RegisterRouter.scala:87:24]
wire out_womask_739 = &_out_womask_T_739; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_739 = out_rivalid_1_593 & out_rimask_739; // @[RegisterRouter.scala:87:24]
wire _out_T_7328 = out_f_rivalid_739; // @[RegisterRouter.scala:87:24]
wire out_f_roready_739 = out_roready_1_593 & out_romask_739; // @[RegisterRouter.scala:87:24]
wire _out_T_7329 = out_f_roready_739; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_739 = out_wivalid_1_593 & out_wimask_739; // @[RegisterRouter.scala:87:24]
wire out_f_woready_739 = out_woready_1_593 & out_womask_739; // @[RegisterRouter.scala:87:24]
wire _out_T_7330 = ~out_rimask_739; // @[RegisterRouter.scala:87:24]
wire _out_T_7331 = ~out_wimask_739; // @[RegisterRouter.scala:87:24]
wire _out_T_7332 = ~out_romask_739; // @[RegisterRouter.scala:87:24]
wire _out_T_7333 = ~out_womask_739; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7335 = _out_T_7334; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_628 = _out_T_7335; // @[RegisterRouter.scala:87:24]
wire out_rimask_740 = |_out_rimask_T_740; // @[RegisterRouter.scala:87:24]
wire out_wimask_740 = &_out_wimask_T_740; // @[RegisterRouter.scala:87:24]
wire out_romask_740 = |_out_romask_T_740; // @[RegisterRouter.scala:87:24]
wire out_womask_740 = &_out_womask_T_740; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_740 = out_rivalid_1_594 & out_rimask_740; // @[RegisterRouter.scala:87:24]
wire _out_T_7337 = out_f_rivalid_740; // @[RegisterRouter.scala:87:24]
wire out_f_roready_740 = out_roready_1_594 & out_romask_740; // @[RegisterRouter.scala:87:24]
wire _out_T_7338 = out_f_roready_740; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_740 = out_wivalid_1_594 & out_wimask_740; // @[RegisterRouter.scala:87:24]
wire out_f_woready_740 = out_woready_1_594 & out_womask_740; // @[RegisterRouter.scala:87:24]
wire _out_T_7339 = ~out_rimask_740; // @[RegisterRouter.scala:87:24]
wire _out_T_7340 = ~out_wimask_740; // @[RegisterRouter.scala:87:24]
wire _out_T_7341 = ~out_romask_740; // @[RegisterRouter.scala:87:24]
wire _out_T_7342 = ~out_womask_740; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_628 = {hi_610, flags_0_go, _out_prepend_T_628}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_7343 = out_prepend_628; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_7344 = _out_T_7343; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_629 = _out_T_7344; // @[RegisterRouter.scala:87:24]
wire out_rimask_741 = |_out_rimask_T_741; // @[RegisterRouter.scala:87:24]
wire out_wimask_741 = &_out_wimask_T_741; // @[RegisterRouter.scala:87:24]
wire out_romask_741 = |_out_romask_T_741; // @[RegisterRouter.scala:87:24]
wire out_womask_741 = &_out_womask_T_741; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_741 = out_rivalid_1_595 & out_rimask_741; // @[RegisterRouter.scala:87:24]
wire _out_T_7346 = out_f_rivalid_741; // @[RegisterRouter.scala:87:24]
wire out_f_roready_741 = out_roready_1_595 & out_romask_741; // @[RegisterRouter.scala:87:24]
wire _out_T_7347 = out_f_roready_741; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_741 = out_wivalid_1_595 & out_wimask_741; // @[RegisterRouter.scala:87:24]
wire out_f_woready_741 = out_woready_1_595 & out_womask_741; // @[RegisterRouter.scala:87:24]
wire _out_T_7348 = ~out_rimask_741; // @[RegisterRouter.scala:87:24]
wire _out_T_7349 = ~out_wimask_741; // @[RegisterRouter.scala:87:24]
wire _out_T_7350 = ~out_romask_741; // @[RegisterRouter.scala:87:24]
wire _out_T_7351 = ~out_womask_741; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_629 = {hi_611, flags_0_go, _out_prepend_T_629}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_7352 = out_prepend_629; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_7353 = _out_T_7352; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_630 = _out_T_7353; // @[RegisterRouter.scala:87:24]
wire out_rimask_742 = |_out_rimask_T_742; // @[RegisterRouter.scala:87:24]
wire out_wimask_742 = &_out_wimask_T_742; // @[RegisterRouter.scala:87:24]
wire out_romask_742 = |_out_romask_T_742; // @[RegisterRouter.scala:87:24]
wire out_womask_742 = &_out_womask_T_742; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_742 = out_rivalid_1_596 & out_rimask_742; // @[RegisterRouter.scala:87:24]
wire _out_T_7355 = out_f_rivalid_742; // @[RegisterRouter.scala:87:24]
wire out_f_roready_742 = out_roready_1_596 & out_romask_742; // @[RegisterRouter.scala:87:24]
wire _out_T_7356 = out_f_roready_742; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_742 = out_wivalid_1_596 & out_wimask_742; // @[RegisterRouter.scala:87:24]
wire out_f_woready_742 = out_woready_1_596 & out_womask_742; // @[RegisterRouter.scala:87:24]
wire _out_T_7357 = ~out_rimask_742; // @[RegisterRouter.scala:87:24]
wire _out_T_7358 = ~out_wimask_742; // @[RegisterRouter.scala:87:24]
wire _out_T_7359 = ~out_romask_742; // @[RegisterRouter.scala:87:24]
wire _out_T_7360 = ~out_womask_742; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_630 = {hi_612, flags_0_go, _out_prepend_T_630}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_7361 = out_prepend_630; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_7362 = _out_T_7361; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_631 = _out_T_7362; // @[RegisterRouter.scala:87:24]
wire out_rimask_743 = |_out_rimask_T_743; // @[RegisterRouter.scala:87:24]
wire out_wimask_743 = &_out_wimask_T_743; // @[RegisterRouter.scala:87:24]
wire out_romask_743 = |_out_romask_T_743; // @[RegisterRouter.scala:87:24]
wire out_womask_743 = &_out_womask_T_743; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_743 = out_rivalid_1_597 & out_rimask_743; // @[RegisterRouter.scala:87:24]
wire _out_T_7364 = out_f_rivalid_743; // @[RegisterRouter.scala:87:24]
wire out_f_roready_743 = out_roready_1_597 & out_romask_743; // @[RegisterRouter.scala:87:24]
wire _out_T_7365 = out_f_roready_743; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_743 = out_wivalid_1_597 & out_wimask_743; // @[RegisterRouter.scala:87:24]
wire out_f_woready_743 = out_woready_1_597 & out_womask_743; // @[RegisterRouter.scala:87:24]
wire _out_T_7366 = ~out_rimask_743; // @[RegisterRouter.scala:87:24]
wire _out_T_7367 = ~out_wimask_743; // @[RegisterRouter.scala:87:24]
wire _out_T_7368 = ~out_romask_743; // @[RegisterRouter.scala:87:24]
wire _out_T_7369 = ~out_womask_743; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_631 = {hi_613, flags_0_go, _out_prepend_T_631}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_7370 = out_prepend_631; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_7371 = _out_T_7370; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_632 = _out_T_7371; // @[RegisterRouter.scala:87:24]
wire out_rimask_744 = |_out_rimask_T_744; // @[RegisterRouter.scala:87:24]
wire out_wimask_744 = &_out_wimask_T_744; // @[RegisterRouter.scala:87:24]
wire out_romask_744 = |_out_romask_T_744; // @[RegisterRouter.scala:87:24]
wire out_womask_744 = &_out_womask_T_744; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_744 = out_rivalid_1_598 & out_rimask_744; // @[RegisterRouter.scala:87:24]
wire _out_T_7373 = out_f_rivalid_744; // @[RegisterRouter.scala:87:24]
wire out_f_roready_744 = out_roready_1_598 & out_romask_744; // @[RegisterRouter.scala:87:24]
wire _out_T_7374 = out_f_roready_744; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_744 = out_wivalid_1_598 & out_wimask_744; // @[RegisterRouter.scala:87:24]
wire out_f_woready_744 = out_woready_1_598 & out_womask_744; // @[RegisterRouter.scala:87:24]
wire _out_T_7375 = ~out_rimask_744; // @[RegisterRouter.scala:87:24]
wire _out_T_7376 = ~out_wimask_744; // @[RegisterRouter.scala:87:24]
wire _out_T_7377 = ~out_romask_744; // @[RegisterRouter.scala:87:24]
wire _out_T_7378 = ~out_womask_744; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_632 = {hi_614, flags_0_go, _out_prepend_T_632}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_7379 = out_prepend_632; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_7380 = _out_T_7379; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_633 = _out_T_7380; // @[RegisterRouter.scala:87:24]
wire out_rimask_745 = |_out_rimask_T_745; // @[RegisterRouter.scala:87:24]
wire out_wimask_745 = &_out_wimask_T_745; // @[RegisterRouter.scala:87:24]
wire out_romask_745 = |_out_romask_T_745; // @[RegisterRouter.scala:87:24]
wire out_womask_745 = &_out_womask_T_745; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_745 = out_rivalid_1_599 & out_rimask_745; // @[RegisterRouter.scala:87:24]
wire _out_T_7382 = out_f_rivalid_745; // @[RegisterRouter.scala:87:24]
wire out_f_roready_745 = out_roready_1_599 & out_romask_745; // @[RegisterRouter.scala:87:24]
wire _out_T_7383 = out_f_roready_745; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_745 = out_wivalid_1_599 & out_wimask_745; // @[RegisterRouter.scala:87:24]
wire out_f_woready_745 = out_woready_1_599 & out_womask_745; // @[RegisterRouter.scala:87:24]
wire _out_T_7384 = ~out_rimask_745; // @[RegisterRouter.scala:87:24]
wire _out_T_7385 = ~out_wimask_745; // @[RegisterRouter.scala:87:24]
wire _out_T_7386 = ~out_romask_745; // @[RegisterRouter.scala:87:24]
wire _out_T_7387 = ~out_womask_745; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_633 = {hi_615, flags_0_go, _out_prepend_T_633}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_7388 = out_prepend_633; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_7389 = _out_T_7388; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_634 = _out_T_7389; // @[RegisterRouter.scala:87:24]
wire out_rimask_746 = |_out_rimask_T_746; // @[RegisterRouter.scala:87:24]
wire out_wimask_746 = &_out_wimask_T_746; // @[RegisterRouter.scala:87:24]
wire out_romask_746 = |_out_romask_T_746; // @[RegisterRouter.scala:87:24]
wire out_womask_746 = &_out_womask_T_746; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_746 = out_rivalid_1_600 & out_rimask_746; // @[RegisterRouter.scala:87:24]
wire _out_T_7391 = out_f_rivalid_746; // @[RegisterRouter.scala:87:24]
wire out_f_roready_746 = out_roready_1_600 & out_romask_746; // @[RegisterRouter.scala:87:24]
wire _out_T_7392 = out_f_roready_746; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_746 = out_wivalid_1_600 & out_wimask_746; // @[RegisterRouter.scala:87:24]
wire out_f_woready_746 = out_woready_1_600 & out_womask_746; // @[RegisterRouter.scala:87:24]
wire _out_T_7393 = ~out_rimask_746; // @[RegisterRouter.scala:87:24]
wire _out_T_7394 = ~out_wimask_746; // @[RegisterRouter.scala:87:24]
wire _out_T_7395 = ~out_romask_746; // @[RegisterRouter.scala:87:24]
wire _out_T_7396 = ~out_womask_746; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_634 = {hi_616, flags_0_go, _out_prepend_T_634}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_7397 = out_prepend_634; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_7398 = _out_T_7397; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_204 = _out_T_7398; // @[MuxLiteral.scala:49:48]
wire out_rimask_747 = |_out_rimask_T_747; // @[RegisterRouter.scala:87:24]
wire out_wimask_747 = &_out_wimask_T_747; // @[RegisterRouter.scala:87:24]
wire out_romask_747 = |_out_romask_T_747; // @[RegisterRouter.scala:87:24]
wire out_womask_747 = &_out_womask_T_747; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_747 = out_rivalid_1_601 & out_rimask_747; // @[RegisterRouter.scala:87:24]
wire _out_T_7400 = out_f_rivalid_747; // @[RegisterRouter.scala:87:24]
wire out_f_roready_747 = out_roready_1_601 & out_romask_747; // @[RegisterRouter.scala:87:24]
wire _out_T_7401 = out_f_roready_747; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_747 = out_wivalid_1_601 & out_wimask_747; // @[RegisterRouter.scala:87:24]
wire out_f_woready_747 = out_woready_1_601 & out_womask_747; // @[RegisterRouter.scala:87:24]
wire _out_T_7402 = ~out_rimask_747; // @[RegisterRouter.scala:87:24]
wire _out_T_7403 = ~out_wimask_747; // @[RegisterRouter.scala:87:24]
wire _out_T_7404 = ~out_romask_747; // @[RegisterRouter.scala:87:24]
wire _out_T_7405 = ~out_womask_747; // @[RegisterRouter.scala:87:24]
wire out_rimask_748 = |_out_rimask_T_748; // @[RegisterRouter.scala:87:24]
wire out_wimask_748 = &_out_wimask_T_748; // @[RegisterRouter.scala:87:24]
wire out_romask_748 = |_out_romask_T_748; // @[RegisterRouter.scala:87:24]
wire out_womask_748 = &_out_womask_T_748; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_748 = out_rivalid_1_602 & out_rimask_748; // @[RegisterRouter.scala:87:24]
wire _out_T_7409 = out_f_rivalid_748; // @[RegisterRouter.scala:87:24]
wire out_f_roready_748 = out_roready_1_602 & out_romask_748; // @[RegisterRouter.scala:87:24]
wire _out_T_7410 = out_f_roready_748; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_748 = out_wivalid_1_602 & out_wimask_748; // @[RegisterRouter.scala:87:24]
wire out_f_woready_748 = out_woready_1_602 & out_womask_748; // @[RegisterRouter.scala:87:24]
wire _out_T_7411 = ~out_rimask_748; // @[RegisterRouter.scala:87:24]
wire _out_T_7412 = ~out_wimask_748; // @[RegisterRouter.scala:87:24]
wire _out_T_7413 = ~out_romask_748; // @[RegisterRouter.scala:87:24]
wire _out_T_7414 = ~out_womask_748; // @[RegisterRouter.scala:87:24]
wire out_rimask_749 = |_out_rimask_T_749; // @[RegisterRouter.scala:87:24]
wire out_wimask_749 = &_out_wimask_T_749; // @[RegisterRouter.scala:87:24]
wire out_romask_749 = |_out_romask_T_749; // @[RegisterRouter.scala:87:24]
wire out_womask_749 = &_out_womask_T_749; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_749 = out_rivalid_1_603 & out_rimask_749; // @[RegisterRouter.scala:87:24]
wire _out_T_7418 = out_f_rivalid_749; // @[RegisterRouter.scala:87:24]
wire out_f_roready_749 = out_roready_1_603 & out_romask_749; // @[RegisterRouter.scala:87:24]
wire _out_T_7419 = out_f_roready_749; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_749 = out_wivalid_1_603 & out_wimask_749; // @[RegisterRouter.scala:87:24]
wire out_f_woready_749 = out_woready_1_603 & out_womask_749; // @[RegisterRouter.scala:87:24]
wire _out_T_7420 = ~out_rimask_749; // @[RegisterRouter.scala:87:24]
wire _out_T_7421 = ~out_wimask_749; // @[RegisterRouter.scala:87:24]
wire _out_T_7422 = ~out_romask_749; // @[RegisterRouter.scala:87:24]
wire _out_T_7423 = ~out_womask_749; // @[RegisterRouter.scala:87:24]
wire out_rimask_750 = |_out_rimask_T_750; // @[RegisterRouter.scala:87:24]
wire out_wimask_750 = &_out_wimask_T_750; // @[RegisterRouter.scala:87:24]
wire out_romask_750 = |_out_romask_T_750; // @[RegisterRouter.scala:87:24]
wire out_womask_750 = &_out_womask_T_750; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_750 = out_rivalid_1_604 & out_rimask_750; // @[RegisterRouter.scala:87:24]
wire _out_T_7427 = out_f_rivalid_750; // @[RegisterRouter.scala:87:24]
wire out_f_roready_750 = out_roready_1_604 & out_romask_750; // @[RegisterRouter.scala:87:24]
wire _out_T_7428 = out_f_roready_750; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_750 = out_wivalid_1_604 & out_wimask_750; // @[RegisterRouter.scala:87:24]
wire out_f_woready_750 = out_woready_1_604 & out_womask_750; // @[RegisterRouter.scala:87:24]
wire _out_T_7429 = ~out_rimask_750; // @[RegisterRouter.scala:87:24]
wire _out_T_7430 = ~out_wimask_750; // @[RegisterRouter.scala:87:24]
wire _out_T_7431 = ~out_romask_750; // @[RegisterRouter.scala:87:24]
wire _out_T_7432 = ~out_womask_750; // @[RegisterRouter.scala:87:24]
wire out_rimask_751 = |_out_rimask_T_751; // @[RegisterRouter.scala:87:24]
wire out_wimask_751 = &_out_wimask_T_751; // @[RegisterRouter.scala:87:24]
wire out_romask_751 = |_out_romask_T_751; // @[RegisterRouter.scala:87:24]
wire out_womask_751 = &_out_womask_T_751; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_751 = out_rivalid_1_605 & out_rimask_751; // @[RegisterRouter.scala:87:24]
wire _out_T_7436 = out_f_rivalid_751; // @[RegisterRouter.scala:87:24]
wire out_f_roready_751 = out_roready_1_605 & out_romask_751; // @[RegisterRouter.scala:87:24]
wire _out_T_7437 = out_f_roready_751; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_751 = out_wivalid_1_605 & out_wimask_751; // @[RegisterRouter.scala:87:24]
wire out_f_woready_751 = out_woready_1_605 & out_womask_751; // @[RegisterRouter.scala:87:24]
wire _out_T_7438 = ~out_rimask_751; // @[RegisterRouter.scala:87:24]
wire _out_T_7439 = ~out_wimask_751; // @[RegisterRouter.scala:87:24]
wire _out_T_7440 = ~out_romask_751; // @[RegisterRouter.scala:87:24]
wire _out_T_7441 = ~out_womask_751; // @[RegisterRouter.scala:87:24]
wire out_rimask_752 = |_out_rimask_T_752; // @[RegisterRouter.scala:87:24]
wire out_wimask_752 = &_out_wimask_T_752; // @[RegisterRouter.scala:87:24]
wire out_romask_752 = |_out_romask_T_752; // @[RegisterRouter.scala:87:24]
wire out_womask_752 = &_out_womask_T_752; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_752 = out_rivalid_1_606 & out_rimask_752; // @[RegisterRouter.scala:87:24]
wire _out_T_7445 = out_f_rivalid_752; // @[RegisterRouter.scala:87:24]
wire out_f_roready_752 = out_roready_1_606 & out_romask_752; // @[RegisterRouter.scala:87:24]
wire _out_T_7446 = out_f_roready_752; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_752 = out_wivalid_1_606 & out_wimask_752; // @[RegisterRouter.scala:87:24]
wire out_f_woready_752 = out_woready_1_606 & out_womask_752; // @[RegisterRouter.scala:87:24]
wire _out_T_7447 = ~out_rimask_752; // @[RegisterRouter.scala:87:24]
wire _out_T_7448 = ~out_wimask_752; // @[RegisterRouter.scala:87:24]
wire _out_T_7449 = ~out_romask_752; // @[RegisterRouter.scala:87:24]
wire _out_T_7450 = ~out_womask_752; // @[RegisterRouter.scala:87:24]
wire out_rimask_753 = |_out_rimask_T_753; // @[RegisterRouter.scala:87:24]
wire out_wimask_753 = &_out_wimask_T_753; // @[RegisterRouter.scala:87:24]
wire out_romask_753 = |_out_romask_T_753; // @[RegisterRouter.scala:87:24]
wire out_womask_753 = &_out_womask_T_753; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_753 = out_rivalid_1_607 & out_rimask_753; // @[RegisterRouter.scala:87:24]
wire _out_T_7454 = out_f_rivalid_753; // @[RegisterRouter.scala:87:24]
wire out_f_roready_753 = out_roready_1_607 & out_romask_753; // @[RegisterRouter.scala:87:24]
wire _out_T_7455 = out_f_roready_753; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_753 = out_wivalid_1_607 & out_wimask_753; // @[RegisterRouter.scala:87:24]
wire out_f_woready_753 = out_woready_1_607 & out_womask_753; // @[RegisterRouter.scala:87:24]
wire _out_T_7456 = ~out_rimask_753; // @[RegisterRouter.scala:87:24]
wire _out_T_7457 = ~out_wimask_753; // @[RegisterRouter.scala:87:24]
wire _out_T_7458 = ~out_romask_753; // @[RegisterRouter.scala:87:24]
wire _out_T_7459 = ~out_womask_753; // @[RegisterRouter.scala:87:24]
wire out_rimask_754 = |_out_rimask_T_754; // @[RegisterRouter.scala:87:24]
wire out_wimask_754 = &_out_wimask_T_754; // @[RegisterRouter.scala:87:24]
wire out_romask_754 = |_out_romask_T_754; // @[RegisterRouter.scala:87:24]
wire out_womask_754 = &_out_womask_T_754; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_754 = out_rivalid_1_608 & out_rimask_754; // @[RegisterRouter.scala:87:24]
wire _out_T_7463 = out_f_rivalid_754; // @[RegisterRouter.scala:87:24]
wire out_f_roready_754 = out_roready_1_608 & out_romask_754; // @[RegisterRouter.scala:87:24]
wire _out_T_7464 = out_f_roready_754; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_754 = out_wivalid_1_608 & out_wimask_754; // @[RegisterRouter.scala:87:24]
wire out_f_woready_754 = out_woready_1_608 & out_womask_754; // @[RegisterRouter.scala:87:24]
wire _out_T_7465 = ~out_rimask_754; // @[RegisterRouter.scala:87:24]
wire _out_T_7466 = ~out_wimask_754; // @[RegisterRouter.scala:87:24]
wire _out_T_7467 = ~out_romask_754; // @[RegisterRouter.scala:87:24]
wire _out_T_7468 = ~out_womask_754; // @[RegisterRouter.scala:87:24]
wire out_rimask_755 = |_out_rimask_T_755; // @[RegisterRouter.scala:87:24]
wire out_wimask_755 = &_out_wimask_T_755; // @[RegisterRouter.scala:87:24]
wire out_romask_755 = |_out_romask_T_755; // @[RegisterRouter.scala:87:24]
wire out_womask_755 = &_out_womask_T_755; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_755 = out_rivalid_1_609 & out_rimask_755; // @[RegisterRouter.scala:87:24]
wire _out_T_7472 = out_f_rivalid_755; // @[RegisterRouter.scala:87:24]
wire out_f_roready_755 = out_roready_1_609 & out_romask_755; // @[RegisterRouter.scala:87:24]
wire _out_T_7473 = out_f_roready_755; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_755 = out_wivalid_1_609 & out_wimask_755; // @[RegisterRouter.scala:87:24]
wire out_f_woready_755 = out_woready_1_609 & out_womask_755; // @[RegisterRouter.scala:87:24]
wire _out_T_7474 = ~out_rimask_755; // @[RegisterRouter.scala:87:24]
wire _out_T_7475 = ~out_wimask_755; // @[RegisterRouter.scala:87:24]
wire _out_T_7476 = ~out_romask_755; // @[RegisterRouter.scala:87:24]
wire _out_T_7477 = ~out_womask_755; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7479 = _out_T_7478; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_642 = _out_T_7479; // @[RegisterRouter.scala:87:24]
wire out_rimask_756 = |_out_rimask_T_756; // @[RegisterRouter.scala:87:24]
wire out_wimask_756 = &_out_wimask_T_756; // @[RegisterRouter.scala:87:24]
wire out_romask_756 = |_out_romask_T_756; // @[RegisterRouter.scala:87:24]
wire out_womask_756 = &_out_womask_T_756; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_756 = out_rivalid_1_610 & out_rimask_756; // @[RegisterRouter.scala:87:24]
wire _out_T_7481 = out_f_rivalid_756; // @[RegisterRouter.scala:87:24]
wire out_f_roready_756 = out_roready_1_610 & out_romask_756; // @[RegisterRouter.scala:87:24]
wire _out_T_7482 = out_f_roready_756; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_756 = out_wivalid_1_610 & out_wimask_756; // @[RegisterRouter.scala:87:24]
wire out_f_woready_756 = out_woready_1_610 & out_womask_756; // @[RegisterRouter.scala:87:24]
wire _out_T_7483 = ~out_rimask_756; // @[RegisterRouter.scala:87:24]
wire _out_T_7484 = ~out_wimask_756; // @[RegisterRouter.scala:87:24]
wire _out_T_7485 = ~out_romask_756; // @[RegisterRouter.scala:87:24]
wire _out_T_7486 = ~out_womask_756; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_642 = {hi_130, flags_0_go, _out_prepend_T_642}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_7487 = out_prepend_642; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_7488 = _out_T_7487; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_643 = _out_T_7488; // @[RegisterRouter.scala:87:24]
wire out_rimask_757 = |_out_rimask_T_757; // @[RegisterRouter.scala:87:24]
wire out_wimask_757 = &_out_wimask_T_757; // @[RegisterRouter.scala:87:24]
wire out_romask_757 = |_out_romask_T_757; // @[RegisterRouter.scala:87:24]
wire out_womask_757 = &_out_womask_T_757; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_757 = out_rivalid_1_611 & out_rimask_757; // @[RegisterRouter.scala:87:24]
wire _out_T_7490 = out_f_rivalid_757; // @[RegisterRouter.scala:87:24]
wire out_f_roready_757 = out_roready_1_611 & out_romask_757; // @[RegisterRouter.scala:87:24]
wire _out_T_7491 = out_f_roready_757; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_757 = out_wivalid_1_611 & out_wimask_757; // @[RegisterRouter.scala:87:24]
wire out_f_woready_757 = out_woready_1_611 & out_womask_757; // @[RegisterRouter.scala:87:24]
wire _out_T_7492 = ~out_rimask_757; // @[RegisterRouter.scala:87:24]
wire _out_T_7493 = ~out_wimask_757; // @[RegisterRouter.scala:87:24]
wire _out_T_7494 = ~out_romask_757; // @[RegisterRouter.scala:87:24]
wire _out_T_7495 = ~out_womask_757; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_643 = {hi_131, flags_0_go, _out_prepend_T_643}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_7496 = out_prepend_643; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_7497 = _out_T_7496; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_644 = _out_T_7497; // @[RegisterRouter.scala:87:24]
wire out_rimask_758 = |_out_rimask_T_758; // @[RegisterRouter.scala:87:24]
wire out_wimask_758 = &_out_wimask_T_758; // @[RegisterRouter.scala:87:24]
wire out_romask_758 = |_out_romask_T_758; // @[RegisterRouter.scala:87:24]
wire out_womask_758 = &_out_womask_T_758; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_758 = out_rivalid_1_612 & out_rimask_758; // @[RegisterRouter.scala:87:24]
wire _out_T_7499 = out_f_rivalid_758; // @[RegisterRouter.scala:87:24]
wire out_f_roready_758 = out_roready_1_612 & out_romask_758; // @[RegisterRouter.scala:87:24]
wire _out_T_7500 = out_f_roready_758; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_758 = out_wivalid_1_612 & out_wimask_758; // @[RegisterRouter.scala:87:24]
wire out_f_woready_758 = out_woready_1_612 & out_womask_758; // @[RegisterRouter.scala:87:24]
wire _out_T_7501 = ~out_rimask_758; // @[RegisterRouter.scala:87:24]
wire _out_T_7502 = ~out_wimask_758; // @[RegisterRouter.scala:87:24]
wire _out_T_7503 = ~out_romask_758; // @[RegisterRouter.scala:87:24]
wire _out_T_7504 = ~out_womask_758; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_644 = {hi_132, flags_0_go, _out_prepend_T_644}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_7505 = out_prepend_644; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_7506 = _out_T_7505; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_645 = _out_T_7506; // @[RegisterRouter.scala:87:24]
wire out_rimask_759 = |_out_rimask_T_759; // @[RegisterRouter.scala:87:24]
wire out_wimask_759 = &_out_wimask_T_759; // @[RegisterRouter.scala:87:24]
wire out_romask_759 = |_out_romask_T_759; // @[RegisterRouter.scala:87:24]
wire out_womask_759 = &_out_womask_T_759; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_759 = out_rivalid_1_613 & out_rimask_759; // @[RegisterRouter.scala:87:24]
wire _out_T_7508 = out_f_rivalid_759; // @[RegisterRouter.scala:87:24]
wire out_f_roready_759 = out_roready_1_613 & out_romask_759; // @[RegisterRouter.scala:87:24]
wire _out_T_7509 = out_f_roready_759; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_759 = out_wivalid_1_613 & out_wimask_759; // @[RegisterRouter.scala:87:24]
wire out_f_woready_759 = out_woready_1_613 & out_womask_759; // @[RegisterRouter.scala:87:24]
wire _out_T_7510 = ~out_rimask_759; // @[RegisterRouter.scala:87:24]
wire _out_T_7511 = ~out_wimask_759; // @[RegisterRouter.scala:87:24]
wire _out_T_7512 = ~out_romask_759; // @[RegisterRouter.scala:87:24]
wire _out_T_7513 = ~out_womask_759; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_645 = {hi_133, flags_0_go, _out_prepend_T_645}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_7514 = out_prepend_645; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_7515 = _out_T_7514; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_646 = _out_T_7515; // @[RegisterRouter.scala:87:24]
wire out_rimask_760 = |_out_rimask_T_760; // @[RegisterRouter.scala:87:24]
wire out_wimask_760 = &_out_wimask_T_760; // @[RegisterRouter.scala:87:24]
wire out_romask_760 = |_out_romask_T_760; // @[RegisterRouter.scala:87:24]
wire out_womask_760 = &_out_womask_T_760; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_760 = out_rivalid_1_614 & out_rimask_760; // @[RegisterRouter.scala:87:24]
wire _out_T_7517 = out_f_rivalid_760; // @[RegisterRouter.scala:87:24]
wire out_f_roready_760 = out_roready_1_614 & out_romask_760; // @[RegisterRouter.scala:87:24]
wire _out_T_7518 = out_f_roready_760; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_760 = out_wivalid_1_614 & out_wimask_760; // @[RegisterRouter.scala:87:24]
wire out_f_woready_760 = out_woready_1_614 & out_womask_760; // @[RegisterRouter.scala:87:24]
wire _out_T_7519 = ~out_rimask_760; // @[RegisterRouter.scala:87:24]
wire _out_T_7520 = ~out_wimask_760; // @[RegisterRouter.scala:87:24]
wire _out_T_7521 = ~out_romask_760; // @[RegisterRouter.scala:87:24]
wire _out_T_7522 = ~out_womask_760; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_646 = {hi_134, flags_0_go, _out_prepend_T_646}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_7523 = out_prepend_646; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_7524 = _out_T_7523; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_647 = _out_T_7524; // @[RegisterRouter.scala:87:24]
wire out_rimask_761 = |_out_rimask_T_761; // @[RegisterRouter.scala:87:24]
wire out_wimask_761 = &_out_wimask_T_761; // @[RegisterRouter.scala:87:24]
wire out_romask_761 = |_out_romask_T_761; // @[RegisterRouter.scala:87:24]
wire out_womask_761 = &_out_womask_T_761; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_761 = out_rivalid_1_615 & out_rimask_761; // @[RegisterRouter.scala:87:24]
wire _out_T_7526 = out_f_rivalid_761; // @[RegisterRouter.scala:87:24]
wire out_f_roready_761 = out_roready_1_615 & out_romask_761; // @[RegisterRouter.scala:87:24]
wire _out_T_7527 = out_f_roready_761; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_761 = out_wivalid_1_615 & out_wimask_761; // @[RegisterRouter.scala:87:24]
wire out_f_woready_761 = out_woready_1_615 & out_womask_761; // @[RegisterRouter.scala:87:24]
wire _out_T_7528 = ~out_rimask_761; // @[RegisterRouter.scala:87:24]
wire _out_T_7529 = ~out_wimask_761; // @[RegisterRouter.scala:87:24]
wire _out_T_7530 = ~out_romask_761; // @[RegisterRouter.scala:87:24]
wire _out_T_7531 = ~out_womask_761; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_647 = {hi_135, flags_0_go, _out_prepend_T_647}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_7532 = out_prepend_647; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_7533 = _out_T_7532; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_648 = _out_T_7533; // @[RegisterRouter.scala:87:24]
wire out_rimask_762 = |_out_rimask_T_762; // @[RegisterRouter.scala:87:24]
wire out_wimask_762 = &_out_wimask_T_762; // @[RegisterRouter.scala:87:24]
wire out_romask_762 = |_out_romask_T_762; // @[RegisterRouter.scala:87:24]
wire out_womask_762 = &_out_womask_T_762; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_762 = out_rivalid_1_616 & out_rimask_762; // @[RegisterRouter.scala:87:24]
wire _out_T_7535 = out_f_rivalid_762; // @[RegisterRouter.scala:87:24]
wire out_f_roready_762 = out_roready_1_616 & out_romask_762; // @[RegisterRouter.scala:87:24]
wire _out_T_7536 = out_f_roready_762; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_762 = out_wivalid_1_616 & out_wimask_762; // @[RegisterRouter.scala:87:24]
wire out_f_woready_762 = out_woready_1_616 & out_womask_762; // @[RegisterRouter.scala:87:24]
wire _out_T_7537 = ~out_rimask_762; // @[RegisterRouter.scala:87:24]
wire _out_T_7538 = ~out_wimask_762; // @[RegisterRouter.scala:87:24]
wire _out_T_7539 = ~out_romask_762; // @[RegisterRouter.scala:87:24]
wire _out_T_7540 = ~out_womask_762; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_648 = {hi_136, flags_0_go, _out_prepend_T_648}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_7541 = out_prepend_648; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_7542 = _out_T_7541; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_144 = _out_T_7542; // @[MuxLiteral.scala:49:48]
wire out_rimask_763 = |_out_rimask_T_763; // @[RegisterRouter.scala:87:24]
wire out_wimask_763 = &_out_wimask_T_763; // @[RegisterRouter.scala:87:24]
wire out_romask_763 = |_out_romask_T_763; // @[RegisterRouter.scala:87:24]
wire out_womask_763 = &_out_womask_T_763; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_763 = out_rivalid_1_617 & out_rimask_763; // @[RegisterRouter.scala:87:24]
wire _out_T_7544 = out_f_rivalid_763; // @[RegisterRouter.scala:87:24]
wire out_f_roready_763 = out_roready_1_617 & out_romask_763; // @[RegisterRouter.scala:87:24]
wire _out_T_7545 = out_f_roready_763; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_763 = out_wivalid_1_617 & out_wimask_763; // @[RegisterRouter.scala:87:24]
wire out_f_woready_763 = out_woready_1_617 & out_womask_763; // @[RegisterRouter.scala:87:24]
wire _out_T_7546 = ~out_rimask_763; // @[RegisterRouter.scala:87:24]
wire _out_T_7547 = ~out_wimask_763; // @[RegisterRouter.scala:87:24]
wire _out_T_7548 = ~out_romask_763; // @[RegisterRouter.scala:87:24]
wire _out_T_7549 = ~out_womask_763; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7551 = _out_T_7550; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_649 = _out_T_7551; // @[RegisterRouter.scala:87:24]
wire out_rimask_764 = |_out_rimask_T_764; // @[RegisterRouter.scala:87:24]
wire out_wimask_764 = &_out_wimask_T_764; // @[RegisterRouter.scala:87:24]
wire out_romask_764 = |_out_romask_T_764; // @[RegisterRouter.scala:87:24]
wire out_womask_764 = &_out_womask_T_764; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_764 = out_rivalid_1_618 & out_rimask_764; // @[RegisterRouter.scala:87:24]
wire _out_T_7553 = out_f_rivalid_764; // @[RegisterRouter.scala:87:24]
wire out_f_roready_764 = out_roready_1_618 & out_romask_764; // @[RegisterRouter.scala:87:24]
wire _out_T_7554 = out_f_roready_764; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_764 = out_wivalid_1_618 & out_wimask_764; // @[RegisterRouter.scala:87:24]
wire out_f_woready_764 = out_woready_1_618 & out_womask_764; // @[RegisterRouter.scala:87:24]
wire _out_T_7555 = ~out_rimask_764; // @[RegisterRouter.scala:87:24]
wire _out_T_7556 = ~out_wimask_764; // @[RegisterRouter.scala:87:24]
wire _out_T_7557 = ~out_romask_764; // @[RegisterRouter.scala:87:24]
wire _out_T_7558 = ~out_womask_764; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_649 = {hi_866, flags_0_go, _out_prepend_T_649}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_7559 = out_prepend_649; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_7560 = _out_T_7559; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_650 = _out_T_7560; // @[RegisterRouter.scala:87:24]
wire out_rimask_765 = |_out_rimask_T_765; // @[RegisterRouter.scala:87:24]
wire out_wimask_765 = &_out_wimask_T_765; // @[RegisterRouter.scala:87:24]
wire out_romask_765 = |_out_romask_T_765; // @[RegisterRouter.scala:87:24]
wire out_womask_765 = &_out_womask_T_765; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_765 = out_rivalid_1_619 & out_rimask_765; // @[RegisterRouter.scala:87:24]
wire _out_T_7562 = out_f_rivalid_765; // @[RegisterRouter.scala:87:24]
wire out_f_roready_765 = out_roready_1_619 & out_romask_765; // @[RegisterRouter.scala:87:24]
wire _out_T_7563 = out_f_roready_765; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_765 = out_wivalid_1_619 & out_wimask_765; // @[RegisterRouter.scala:87:24]
wire out_f_woready_765 = out_woready_1_619 & out_womask_765; // @[RegisterRouter.scala:87:24]
wire _out_T_7564 = ~out_rimask_765; // @[RegisterRouter.scala:87:24]
wire _out_T_7565 = ~out_wimask_765; // @[RegisterRouter.scala:87:24]
wire _out_T_7566 = ~out_romask_765; // @[RegisterRouter.scala:87:24]
wire _out_T_7567 = ~out_womask_765; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_650 = {hi_867, flags_0_go, _out_prepend_T_650}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_7568 = out_prepend_650; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_7569 = _out_T_7568; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_651 = _out_T_7569; // @[RegisterRouter.scala:87:24]
wire out_rimask_766 = |_out_rimask_T_766; // @[RegisterRouter.scala:87:24]
wire out_wimask_766 = &_out_wimask_T_766; // @[RegisterRouter.scala:87:24]
wire out_romask_766 = |_out_romask_T_766; // @[RegisterRouter.scala:87:24]
wire out_womask_766 = &_out_womask_T_766; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_766 = out_rivalid_1_620 & out_rimask_766; // @[RegisterRouter.scala:87:24]
wire _out_T_7571 = out_f_rivalid_766; // @[RegisterRouter.scala:87:24]
wire out_f_roready_766 = out_roready_1_620 & out_romask_766; // @[RegisterRouter.scala:87:24]
wire _out_T_7572 = out_f_roready_766; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_766 = out_wivalid_1_620 & out_wimask_766; // @[RegisterRouter.scala:87:24]
wire out_f_woready_766 = out_woready_1_620 & out_womask_766; // @[RegisterRouter.scala:87:24]
wire _out_T_7573 = ~out_rimask_766; // @[RegisterRouter.scala:87:24]
wire _out_T_7574 = ~out_wimask_766; // @[RegisterRouter.scala:87:24]
wire _out_T_7575 = ~out_romask_766; // @[RegisterRouter.scala:87:24]
wire _out_T_7576 = ~out_womask_766; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_651 = {hi_868, flags_0_go, _out_prepend_T_651}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_7577 = out_prepend_651; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_7578 = _out_T_7577; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_652 = _out_T_7578; // @[RegisterRouter.scala:87:24]
wire out_rimask_767 = |_out_rimask_T_767; // @[RegisterRouter.scala:87:24]
wire out_wimask_767 = &_out_wimask_T_767; // @[RegisterRouter.scala:87:24]
wire out_romask_767 = |_out_romask_T_767; // @[RegisterRouter.scala:87:24]
wire out_womask_767 = &_out_womask_T_767; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_767 = out_rivalid_1_621 & out_rimask_767; // @[RegisterRouter.scala:87:24]
wire _out_T_7580 = out_f_rivalid_767; // @[RegisterRouter.scala:87:24]
wire out_f_roready_767 = out_roready_1_621 & out_romask_767; // @[RegisterRouter.scala:87:24]
wire _out_T_7581 = out_f_roready_767; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_767 = out_wivalid_1_621 & out_wimask_767; // @[RegisterRouter.scala:87:24]
wire out_f_woready_767 = out_woready_1_621 & out_womask_767; // @[RegisterRouter.scala:87:24]
wire _out_T_7582 = ~out_rimask_767; // @[RegisterRouter.scala:87:24]
wire _out_T_7583 = ~out_wimask_767; // @[RegisterRouter.scala:87:24]
wire _out_T_7584 = ~out_romask_767; // @[RegisterRouter.scala:87:24]
wire _out_T_7585 = ~out_womask_767; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_652 = {hi_869, flags_0_go, _out_prepend_T_652}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_7586 = out_prepend_652; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_7587 = _out_T_7586; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_653 = _out_T_7587; // @[RegisterRouter.scala:87:24]
wire out_rimask_768 = |_out_rimask_T_768; // @[RegisterRouter.scala:87:24]
wire out_wimask_768 = &_out_wimask_T_768; // @[RegisterRouter.scala:87:24]
wire out_romask_768 = |_out_romask_T_768; // @[RegisterRouter.scala:87:24]
wire out_womask_768 = &_out_womask_T_768; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_768 = out_rivalid_1_622 & out_rimask_768; // @[RegisterRouter.scala:87:24]
wire _out_T_7589 = out_f_rivalid_768; // @[RegisterRouter.scala:87:24]
wire out_f_roready_768 = out_roready_1_622 & out_romask_768; // @[RegisterRouter.scala:87:24]
wire _out_T_7590 = out_f_roready_768; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_768 = out_wivalid_1_622 & out_wimask_768; // @[RegisterRouter.scala:87:24]
wire out_f_woready_768 = out_woready_1_622 & out_womask_768; // @[RegisterRouter.scala:87:24]
wire _out_T_7591 = ~out_rimask_768; // @[RegisterRouter.scala:87:24]
wire _out_T_7592 = ~out_wimask_768; // @[RegisterRouter.scala:87:24]
wire _out_T_7593 = ~out_romask_768; // @[RegisterRouter.scala:87:24]
wire _out_T_7594 = ~out_womask_768; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_653 = {hi_870, flags_0_go, _out_prepend_T_653}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_7595 = out_prepend_653; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_7596 = _out_T_7595; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_654 = _out_T_7596; // @[RegisterRouter.scala:87:24]
wire out_rimask_769 = |_out_rimask_T_769; // @[RegisterRouter.scala:87:24]
wire out_wimask_769 = &_out_wimask_T_769; // @[RegisterRouter.scala:87:24]
wire out_romask_769 = |_out_romask_T_769; // @[RegisterRouter.scala:87:24]
wire out_womask_769 = &_out_womask_T_769; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_769 = out_rivalid_1_623 & out_rimask_769; // @[RegisterRouter.scala:87:24]
wire _out_T_7598 = out_f_rivalid_769; // @[RegisterRouter.scala:87:24]
wire out_f_roready_769 = out_roready_1_623 & out_romask_769; // @[RegisterRouter.scala:87:24]
wire _out_T_7599 = out_f_roready_769; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_769 = out_wivalid_1_623 & out_wimask_769; // @[RegisterRouter.scala:87:24]
wire out_f_woready_769 = out_woready_1_623 & out_womask_769; // @[RegisterRouter.scala:87:24]
wire _out_T_7600 = ~out_rimask_769; // @[RegisterRouter.scala:87:24]
wire _out_T_7601 = ~out_wimask_769; // @[RegisterRouter.scala:87:24]
wire _out_T_7602 = ~out_romask_769; // @[RegisterRouter.scala:87:24]
wire _out_T_7603 = ~out_womask_769; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_654 = {hi_871, flags_0_go, _out_prepend_T_654}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_7604 = out_prepend_654; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_7605 = _out_T_7604; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_655 = _out_T_7605; // @[RegisterRouter.scala:87:24]
wire out_rimask_770 = |_out_rimask_T_770; // @[RegisterRouter.scala:87:24]
wire out_wimask_770 = &_out_wimask_T_770; // @[RegisterRouter.scala:87:24]
wire out_romask_770 = |_out_romask_T_770; // @[RegisterRouter.scala:87:24]
wire out_womask_770 = &_out_womask_T_770; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_770 = out_rivalid_1_624 & out_rimask_770; // @[RegisterRouter.scala:87:24]
wire _out_T_7607 = out_f_rivalid_770; // @[RegisterRouter.scala:87:24]
wire out_f_roready_770 = out_roready_1_624 & out_romask_770; // @[RegisterRouter.scala:87:24]
wire _out_T_7608 = out_f_roready_770; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_770 = out_wivalid_1_624 & out_wimask_770; // @[RegisterRouter.scala:87:24]
wire out_f_woready_770 = out_woready_1_624 & out_womask_770; // @[RegisterRouter.scala:87:24]
wire _out_T_7609 = ~out_rimask_770; // @[RegisterRouter.scala:87:24]
wire _out_T_7610 = ~out_wimask_770; // @[RegisterRouter.scala:87:24]
wire _out_T_7611 = ~out_romask_770; // @[RegisterRouter.scala:87:24]
wire _out_T_7612 = ~out_womask_770; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_655 = {hi_872, flags_0_go, _out_prepend_T_655}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_7613 = out_prepend_655; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_7614 = _out_T_7613; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_236 = _out_T_7614; // @[MuxLiteral.scala:49:48]
wire out_rimask_771 = |_out_rimask_T_771; // @[RegisterRouter.scala:87:24]
wire out_wimask_771 = &_out_wimask_T_771; // @[RegisterRouter.scala:87:24]
wire out_romask_771 = |_out_romask_T_771; // @[RegisterRouter.scala:87:24]
wire out_womask_771 = &_out_womask_T_771; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_771 = out_rivalid_1_625 & out_rimask_771; // @[RegisterRouter.scala:87:24]
wire _out_T_7616 = out_f_rivalid_771; // @[RegisterRouter.scala:87:24]
wire out_f_roready_771 = out_roready_1_625 & out_romask_771; // @[RegisterRouter.scala:87:24]
wire _out_T_7617 = out_f_roready_771; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_771 = out_wivalid_1_625 & out_wimask_771; // @[RegisterRouter.scala:87:24]
wire out_f_woready_771 = out_woready_1_625 & out_womask_771; // @[RegisterRouter.scala:87:24]
wire _out_T_7618 = ~out_rimask_771; // @[RegisterRouter.scala:87:24]
wire _out_T_7619 = ~out_wimask_771; // @[RegisterRouter.scala:87:24]
wire _out_T_7620 = ~out_romask_771; // @[RegisterRouter.scala:87:24]
wire _out_T_7621 = ~out_womask_771; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7623 = _out_T_7622; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_656 = _out_T_7623; // @[RegisterRouter.scala:87:24]
wire out_rimask_772 = |_out_rimask_T_772; // @[RegisterRouter.scala:87:24]
wire out_wimask_772 = &_out_wimask_T_772; // @[RegisterRouter.scala:87:24]
wire out_romask_772 = |_out_romask_T_772; // @[RegisterRouter.scala:87:24]
wire out_womask_772 = &_out_womask_T_772; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_772 = out_rivalid_1_626 & out_rimask_772; // @[RegisterRouter.scala:87:24]
wire _out_T_7625 = out_f_rivalid_772; // @[RegisterRouter.scala:87:24]
wire out_f_roready_772 = out_roready_1_626 & out_romask_772; // @[RegisterRouter.scala:87:24]
wire _out_T_7626 = out_f_roready_772; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_772 = out_wivalid_1_626 & out_wimask_772; // @[RegisterRouter.scala:87:24]
wire out_f_woready_772 = out_woready_1_626 & out_womask_772; // @[RegisterRouter.scala:87:24]
wire _out_T_7627 = ~out_rimask_772; // @[RegisterRouter.scala:87:24]
wire _out_T_7628 = ~out_wimask_772; // @[RegisterRouter.scala:87:24]
wire _out_T_7629 = ~out_romask_772; // @[RegisterRouter.scala:87:24]
wire _out_T_7630 = ~out_womask_772; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_656 = {hi_426, flags_0_go, _out_prepend_T_656}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_7631 = out_prepend_656; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_7632 = _out_T_7631; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_657 = _out_T_7632; // @[RegisterRouter.scala:87:24]
wire out_rimask_773 = |_out_rimask_T_773; // @[RegisterRouter.scala:87:24]
wire out_wimask_773 = &_out_wimask_T_773; // @[RegisterRouter.scala:87:24]
wire out_romask_773 = |_out_romask_T_773; // @[RegisterRouter.scala:87:24]
wire out_womask_773 = &_out_womask_T_773; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_773 = out_rivalid_1_627 & out_rimask_773; // @[RegisterRouter.scala:87:24]
wire _out_T_7634 = out_f_rivalid_773; // @[RegisterRouter.scala:87:24]
wire out_f_roready_773 = out_roready_1_627 & out_romask_773; // @[RegisterRouter.scala:87:24]
wire _out_T_7635 = out_f_roready_773; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_773 = out_wivalid_1_627 & out_wimask_773; // @[RegisterRouter.scala:87:24]
wire out_f_woready_773 = out_woready_1_627 & out_womask_773; // @[RegisterRouter.scala:87:24]
wire _out_T_7636 = ~out_rimask_773; // @[RegisterRouter.scala:87:24]
wire _out_T_7637 = ~out_wimask_773; // @[RegisterRouter.scala:87:24]
wire _out_T_7638 = ~out_romask_773; // @[RegisterRouter.scala:87:24]
wire _out_T_7639 = ~out_womask_773; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_657 = {hi_427, flags_0_go, _out_prepend_T_657}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_7640 = out_prepend_657; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_7641 = _out_T_7640; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_658 = _out_T_7641; // @[RegisterRouter.scala:87:24]
wire out_rimask_774 = |_out_rimask_T_774; // @[RegisterRouter.scala:87:24]
wire out_wimask_774 = &_out_wimask_T_774; // @[RegisterRouter.scala:87:24]
wire out_romask_774 = |_out_romask_T_774; // @[RegisterRouter.scala:87:24]
wire out_womask_774 = &_out_womask_T_774; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_774 = out_rivalid_1_628 & out_rimask_774; // @[RegisterRouter.scala:87:24]
wire _out_T_7643 = out_f_rivalid_774; // @[RegisterRouter.scala:87:24]
wire out_f_roready_774 = out_roready_1_628 & out_romask_774; // @[RegisterRouter.scala:87:24]
wire _out_T_7644 = out_f_roready_774; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_774 = out_wivalid_1_628 & out_wimask_774; // @[RegisterRouter.scala:87:24]
wire out_f_woready_774 = out_woready_1_628 & out_womask_774; // @[RegisterRouter.scala:87:24]
wire _out_T_7645 = ~out_rimask_774; // @[RegisterRouter.scala:87:24]
wire _out_T_7646 = ~out_wimask_774; // @[RegisterRouter.scala:87:24]
wire _out_T_7647 = ~out_romask_774; // @[RegisterRouter.scala:87:24]
wire _out_T_7648 = ~out_womask_774; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_658 = {hi_428, flags_0_go, _out_prepend_T_658}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_7649 = out_prepend_658; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_7650 = _out_T_7649; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_659 = _out_T_7650; // @[RegisterRouter.scala:87:24]
wire out_rimask_775 = |_out_rimask_T_775; // @[RegisterRouter.scala:87:24]
wire out_wimask_775 = &_out_wimask_T_775; // @[RegisterRouter.scala:87:24]
wire out_romask_775 = |_out_romask_T_775; // @[RegisterRouter.scala:87:24]
wire out_womask_775 = &_out_womask_T_775; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_775 = out_rivalid_1_629 & out_rimask_775; // @[RegisterRouter.scala:87:24]
wire _out_T_7652 = out_f_rivalid_775; // @[RegisterRouter.scala:87:24]
wire out_f_roready_775 = out_roready_1_629 & out_romask_775; // @[RegisterRouter.scala:87:24]
wire _out_T_7653 = out_f_roready_775; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_775 = out_wivalid_1_629 & out_wimask_775; // @[RegisterRouter.scala:87:24]
wire out_f_woready_775 = out_woready_1_629 & out_womask_775; // @[RegisterRouter.scala:87:24]
wire _out_T_7654 = ~out_rimask_775; // @[RegisterRouter.scala:87:24]
wire _out_T_7655 = ~out_wimask_775; // @[RegisterRouter.scala:87:24]
wire _out_T_7656 = ~out_romask_775; // @[RegisterRouter.scala:87:24]
wire _out_T_7657 = ~out_womask_775; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_659 = {hi_429, flags_0_go, _out_prepend_T_659}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_7658 = out_prepend_659; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_7659 = _out_T_7658; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_660 = _out_T_7659; // @[RegisterRouter.scala:87:24]
wire out_rimask_776 = |_out_rimask_T_776; // @[RegisterRouter.scala:87:24]
wire out_wimask_776 = &_out_wimask_T_776; // @[RegisterRouter.scala:87:24]
wire out_romask_776 = |_out_romask_T_776; // @[RegisterRouter.scala:87:24]
wire out_womask_776 = &_out_womask_T_776; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_776 = out_rivalid_1_630 & out_rimask_776; // @[RegisterRouter.scala:87:24]
wire _out_T_7661 = out_f_rivalid_776; // @[RegisterRouter.scala:87:24]
wire out_f_roready_776 = out_roready_1_630 & out_romask_776; // @[RegisterRouter.scala:87:24]
wire _out_T_7662 = out_f_roready_776; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_776 = out_wivalid_1_630 & out_wimask_776; // @[RegisterRouter.scala:87:24]
wire out_f_woready_776 = out_woready_1_630 & out_womask_776; // @[RegisterRouter.scala:87:24]
wire _out_T_7663 = ~out_rimask_776; // @[RegisterRouter.scala:87:24]
wire _out_T_7664 = ~out_wimask_776; // @[RegisterRouter.scala:87:24]
wire _out_T_7665 = ~out_romask_776; // @[RegisterRouter.scala:87:24]
wire _out_T_7666 = ~out_womask_776; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_660 = {hi_430, flags_0_go, _out_prepend_T_660}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_7667 = out_prepend_660; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_7668 = _out_T_7667; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_661 = _out_T_7668; // @[RegisterRouter.scala:87:24]
wire out_rimask_777 = |_out_rimask_T_777; // @[RegisterRouter.scala:87:24]
wire out_wimask_777 = &_out_wimask_T_777; // @[RegisterRouter.scala:87:24]
wire out_romask_777 = |_out_romask_T_777; // @[RegisterRouter.scala:87:24]
wire out_womask_777 = &_out_womask_T_777; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_777 = out_rivalid_1_631 & out_rimask_777; // @[RegisterRouter.scala:87:24]
wire _out_T_7670 = out_f_rivalid_777; // @[RegisterRouter.scala:87:24]
wire out_f_roready_777 = out_roready_1_631 & out_romask_777; // @[RegisterRouter.scala:87:24]
wire _out_T_7671 = out_f_roready_777; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_777 = out_wivalid_1_631 & out_wimask_777; // @[RegisterRouter.scala:87:24]
wire out_f_woready_777 = out_woready_1_631 & out_womask_777; // @[RegisterRouter.scala:87:24]
wire _out_T_7672 = ~out_rimask_777; // @[RegisterRouter.scala:87:24]
wire _out_T_7673 = ~out_wimask_777; // @[RegisterRouter.scala:87:24]
wire _out_T_7674 = ~out_romask_777; // @[RegisterRouter.scala:87:24]
wire _out_T_7675 = ~out_womask_777; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_661 = {hi_431, flags_0_go, _out_prepend_T_661}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_7676 = out_prepend_661; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_7677 = _out_T_7676; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_662 = _out_T_7677; // @[RegisterRouter.scala:87:24]
wire out_rimask_778 = |_out_rimask_T_778; // @[RegisterRouter.scala:87:24]
wire out_wimask_778 = &_out_wimask_T_778; // @[RegisterRouter.scala:87:24]
wire out_romask_778 = |_out_romask_T_778; // @[RegisterRouter.scala:87:24]
wire out_womask_778 = &_out_womask_T_778; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_778 = out_rivalid_1_632 & out_rimask_778; // @[RegisterRouter.scala:87:24]
wire _out_T_7679 = out_f_rivalid_778; // @[RegisterRouter.scala:87:24]
wire out_f_roready_778 = out_roready_1_632 & out_romask_778; // @[RegisterRouter.scala:87:24]
wire _out_T_7680 = out_f_roready_778; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_778 = out_wivalid_1_632 & out_wimask_778; // @[RegisterRouter.scala:87:24]
wire out_f_woready_778 = out_woready_1_632 & out_womask_778; // @[RegisterRouter.scala:87:24]
wire _out_T_7681 = ~out_rimask_778; // @[RegisterRouter.scala:87:24]
wire _out_T_7682 = ~out_wimask_778; // @[RegisterRouter.scala:87:24]
wire _out_T_7683 = ~out_romask_778; // @[RegisterRouter.scala:87:24]
wire _out_T_7684 = ~out_womask_778; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_662 = {hi_432, flags_0_go, _out_prepend_T_662}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_7685 = out_prepend_662; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_7686 = _out_T_7685; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_181 = _out_T_7686; // @[MuxLiteral.scala:49:48]
wire out_rimask_779 = |_out_rimask_T_779; // @[RegisterRouter.scala:87:24]
wire out_wimask_779 = &_out_wimask_T_779; // @[RegisterRouter.scala:87:24]
wire out_romask_779 = |_out_romask_T_779; // @[RegisterRouter.scala:87:24]
wire out_womask_779 = &_out_womask_T_779; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_779 = out_rivalid_1_633 & out_rimask_779; // @[RegisterRouter.scala:87:24]
wire _out_T_7688 = out_f_rivalid_779; // @[RegisterRouter.scala:87:24]
wire out_f_roready_779 = out_roready_1_633 & out_romask_779; // @[RegisterRouter.scala:87:24]
wire _out_T_7689 = out_f_roready_779; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_779 = out_wivalid_1_633 & out_wimask_779; // @[RegisterRouter.scala:87:24]
wire out_f_woready_779 = out_woready_1_633 & out_womask_779; // @[RegisterRouter.scala:87:24]
wire _out_T_7690 = ~out_rimask_779; // @[RegisterRouter.scala:87:24]
wire _out_T_7691 = ~out_wimask_779; // @[RegisterRouter.scala:87:24]
wire _out_T_7692 = ~out_romask_779; // @[RegisterRouter.scala:87:24]
wire _out_T_7693 = ~out_womask_779; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7695 = _out_T_7694; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_663 = _out_T_7695; // @[RegisterRouter.scala:87:24]
wire out_rimask_780 = |_out_rimask_T_780; // @[RegisterRouter.scala:87:24]
wire out_wimask_780 = &_out_wimask_T_780; // @[RegisterRouter.scala:87:24]
wire out_romask_780 = |_out_romask_T_780; // @[RegisterRouter.scala:87:24]
wire out_womask_780 = &_out_womask_T_780; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_780 = out_rivalid_1_634 & out_rimask_780; // @[RegisterRouter.scala:87:24]
wire _out_T_7697 = out_f_rivalid_780; // @[RegisterRouter.scala:87:24]
wire out_f_roready_780 = out_roready_1_634 & out_romask_780; // @[RegisterRouter.scala:87:24]
wire _out_T_7698 = out_f_roready_780; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_780 = out_wivalid_1_634 & out_wimask_780; // @[RegisterRouter.scala:87:24]
wire out_f_woready_780 = out_woready_1_634 & out_womask_780; // @[RegisterRouter.scala:87:24]
wire _out_T_7699 = ~out_rimask_780; // @[RegisterRouter.scala:87:24]
wire _out_T_7700 = ~out_wimask_780; // @[RegisterRouter.scala:87:24]
wire _out_T_7701 = ~out_romask_780; // @[RegisterRouter.scala:87:24]
wire _out_T_7702 = ~out_womask_780; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_663 = {hi_250, flags_0_go, _out_prepend_T_663}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_7703 = out_prepend_663; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_7704 = _out_T_7703; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_664 = _out_T_7704; // @[RegisterRouter.scala:87:24]
wire out_rimask_781 = |_out_rimask_T_781; // @[RegisterRouter.scala:87:24]
wire out_wimask_781 = &_out_wimask_T_781; // @[RegisterRouter.scala:87:24]
wire out_romask_781 = |_out_romask_T_781; // @[RegisterRouter.scala:87:24]
wire out_womask_781 = &_out_womask_T_781; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_781 = out_rivalid_1_635 & out_rimask_781; // @[RegisterRouter.scala:87:24]
wire _out_T_7706 = out_f_rivalid_781; // @[RegisterRouter.scala:87:24]
wire out_f_roready_781 = out_roready_1_635 & out_romask_781; // @[RegisterRouter.scala:87:24]
wire _out_T_7707 = out_f_roready_781; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_781 = out_wivalid_1_635 & out_wimask_781; // @[RegisterRouter.scala:87:24]
wire out_f_woready_781 = out_woready_1_635 & out_womask_781; // @[RegisterRouter.scala:87:24]
wire _out_T_7708 = ~out_rimask_781; // @[RegisterRouter.scala:87:24]
wire _out_T_7709 = ~out_wimask_781; // @[RegisterRouter.scala:87:24]
wire _out_T_7710 = ~out_romask_781; // @[RegisterRouter.scala:87:24]
wire _out_T_7711 = ~out_womask_781; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_664 = {hi_251, flags_0_go, _out_prepend_T_664}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_7712 = out_prepend_664; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_7713 = _out_T_7712; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_665 = _out_T_7713; // @[RegisterRouter.scala:87:24]
wire out_rimask_782 = |_out_rimask_T_782; // @[RegisterRouter.scala:87:24]
wire out_wimask_782 = &_out_wimask_T_782; // @[RegisterRouter.scala:87:24]
wire out_romask_782 = |_out_romask_T_782; // @[RegisterRouter.scala:87:24]
wire out_womask_782 = &_out_womask_T_782; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_782 = out_rivalid_1_636 & out_rimask_782; // @[RegisterRouter.scala:87:24]
wire _out_T_7715 = out_f_rivalid_782; // @[RegisterRouter.scala:87:24]
wire out_f_roready_782 = out_roready_1_636 & out_romask_782; // @[RegisterRouter.scala:87:24]
wire _out_T_7716 = out_f_roready_782; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_782 = out_wivalid_1_636 & out_wimask_782; // @[RegisterRouter.scala:87:24]
wire out_f_woready_782 = out_woready_1_636 & out_womask_782; // @[RegisterRouter.scala:87:24]
wire _out_T_7717 = ~out_rimask_782; // @[RegisterRouter.scala:87:24]
wire _out_T_7718 = ~out_wimask_782; // @[RegisterRouter.scala:87:24]
wire _out_T_7719 = ~out_romask_782; // @[RegisterRouter.scala:87:24]
wire _out_T_7720 = ~out_womask_782; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_665 = {hi_252, flags_0_go, _out_prepend_T_665}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_7721 = out_prepend_665; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_7722 = _out_T_7721; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_666 = _out_T_7722; // @[RegisterRouter.scala:87:24]
wire out_rimask_783 = |_out_rimask_T_783; // @[RegisterRouter.scala:87:24]
wire out_wimask_783 = &_out_wimask_T_783; // @[RegisterRouter.scala:87:24]
wire out_romask_783 = |_out_romask_T_783; // @[RegisterRouter.scala:87:24]
wire out_womask_783 = &_out_womask_T_783; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_783 = out_rivalid_1_637 & out_rimask_783; // @[RegisterRouter.scala:87:24]
wire _out_T_7724 = out_f_rivalid_783; // @[RegisterRouter.scala:87:24]
wire out_f_roready_783 = out_roready_1_637 & out_romask_783; // @[RegisterRouter.scala:87:24]
wire _out_T_7725 = out_f_roready_783; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_783 = out_wivalid_1_637 & out_wimask_783; // @[RegisterRouter.scala:87:24]
wire out_f_woready_783 = out_woready_1_637 & out_womask_783; // @[RegisterRouter.scala:87:24]
wire _out_T_7726 = ~out_rimask_783; // @[RegisterRouter.scala:87:24]
wire _out_T_7727 = ~out_wimask_783; // @[RegisterRouter.scala:87:24]
wire _out_T_7728 = ~out_romask_783; // @[RegisterRouter.scala:87:24]
wire _out_T_7729 = ~out_womask_783; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_666 = {hi_253, flags_0_go, _out_prepend_T_666}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_7730 = out_prepend_666; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_7731 = _out_T_7730; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_667 = _out_T_7731; // @[RegisterRouter.scala:87:24]
wire out_rimask_784 = |_out_rimask_T_784; // @[RegisterRouter.scala:87:24]
wire out_wimask_784 = &_out_wimask_T_784; // @[RegisterRouter.scala:87:24]
wire out_romask_784 = |_out_romask_T_784; // @[RegisterRouter.scala:87:24]
wire out_womask_784 = &_out_womask_T_784; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_784 = out_rivalid_1_638 & out_rimask_784; // @[RegisterRouter.scala:87:24]
wire _out_T_7733 = out_f_rivalid_784; // @[RegisterRouter.scala:87:24]
wire out_f_roready_784 = out_roready_1_638 & out_romask_784; // @[RegisterRouter.scala:87:24]
wire _out_T_7734 = out_f_roready_784; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_784 = out_wivalid_1_638 & out_wimask_784; // @[RegisterRouter.scala:87:24]
wire out_f_woready_784 = out_woready_1_638 & out_womask_784; // @[RegisterRouter.scala:87:24]
wire _out_T_7735 = ~out_rimask_784; // @[RegisterRouter.scala:87:24]
wire _out_T_7736 = ~out_wimask_784; // @[RegisterRouter.scala:87:24]
wire _out_T_7737 = ~out_romask_784; // @[RegisterRouter.scala:87:24]
wire _out_T_7738 = ~out_womask_784; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_667 = {hi_254, flags_0_go, _out_prepend_T_667}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_7739 = out_prepend_667; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_7740 = _out_T_7739; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_668 = _out_T_7740; // @[RegisterRouter.scala:87:24]
wire out_rimask_785 = |_out_rimask_T_785; // @[RegisterRouter.scala:87:24]
wire out_wimask_785 = &_out_wimask_T_785; // @[RegisterRouter.scala:87:24]
wire out_romask_785 = |_out_romask_T_785; // @[RegisterRouter.scala:87:24]
wire out_womask_785 = &_out_womask_T_785; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_785 = out_rivalid_1_639 & out_rimask_785; // @[RegisterRouter.scala:87:24]
wire _out_T_7742 = out_f_rivalid_785; // @[RegisterRouter.scala:87:24]
wire out_f_roready_785 = out_roready_1_639 & out_romask_785; // @[RegisterRouter.scala:87:24]
wire _out_T_7743 = out_f_roready_785; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_785 = out_wivalid_1_639 & out_wimask_785; // @[RegisterRouter.scala:87:24]
wire out_f_woready_785 = out_woready_1_639 & out_womask_785; // @[RegisterRouter.scala:87:24]
wire _out_T_7744 = ~out_rimask_785; // @[RegisterRouter.scala:87:24]
wire _out_T_7745 = ~out_wimask_785; // @[RegisterRouter.scala:87:24]
wire _out_T_7746 = ~out_romask_785; // @[RegisterRouter.scala:87:24]
wire _out_T_7747 = ~out_womask_785; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_668 = {hi_255, flags_0_go, _out_prepend_T_668}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_7748 = out_prepend_668; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_7749 = _out_T_7748; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_669 = _out_T_7749; // @[RegisterRouter.scala:87:24]
wire out_rimask_786 = |_out_rimask_T_786; // @[RegisterRouter.scala:87:24]
wire out_wimask_786 = &_out_wimask_T_786; // @[RegisterRouter.scala:87:24]
wire out_romask_786 = |_out_romask_T_786; // @[RegisterRouter.scala:87:24]
wire out_womask_786 = &_out_womask_T_786; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_786 = out_rivalid_1_640 & out_rimask_786; // @[RegisterRouter.scala:87:24]
wire _out_T_7751 = out_f_rivalid_786; // @[RegisterRouter.scala:87:24]
wire out_f_roready_786 = out_roready_1_640 & out_romask_786; // @[RegisterRouter.scala:87:24]
wire _out_T_7752 = out_f_roready_786; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_786 = out_wivalid_1_640 & out_wimask_786; // @[RegisterRouter.scala:87:24]
wire out_f_woready_786 = out_woready_1_640 & out_womask_786; // @[RegisterRouter.scala:87:24]
wire _out_T_7753 = ~out_rimask_786; // @[RegisterRouter.scala:87:24]
wire _out_T_7754 = ~out_wimask_786; // @[RegisterRouter.scala:87:24]
wire _out_T_7755 = ~out_romask_786; // @[RegisterRouter.scala:87:24]
wire _out_T_7756 = ~out_womask_786; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_669 = {hi_256, flags_0_go, _out_prepend_T_669}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_7757 = out_prepend_669; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_7758 = _out_T_7757; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_159 = _out_T_7758; // @[MuxLiteral.scala:49:48]
wire out_rimask_787 = |_out_rimask_T_787; // @[RegisterRouter.scala:87:24]
wire out_wimask_787 = &_out_wimask_T_787; // @[RegisterRouter.scala:87:24]
wire out_romask_787 = |_out_romask_T_787; // @[RegisterRouter.scala:87:24]
wire out_womask_787 = &_out_womask_T_787; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_787 = out_rivalid_1_641 & out_rimask_787; // @[RegisterRouter.scala:87:24]
wire _out_T_7760 = out_f_rivalid_787; // @[RegisterRouter.scala:87:24]
wire out_f_roready_787 = out_roready_1_641 & out_romask_787; // @[RegisterRouter.scala:87:24]
wire _out_T_7761 = out_f_roready_787; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_787 = out_wivalid_1_641 & out_wimask_787; // @[RegisterRouter.scala:87:24]
wire out_f_woready_787 = out_woready_1_641 & out_womask_787; // @[RegisterRouter.scala:87:24]
wire _out_T_7762 = ~out_rimask_787; // @[RegisterRouter.scala:87:24]
wire _out_T_7763 = ~out_wimask_787; // @[RegisterRouter.scala:87:24]
wire _out_T_7764 = ~out_romask_787; // @[RegisterRouter.scala:87:24]
wire _out_T_7765 = ~out_womask_787; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7767 = _out_T_7766; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_670 = _out_T_7767; // @[RegisterRouter.scala:87:24]
wire out_rimask_788 = |_out_rimask_T_788; // @[RegisterRouter.scala:87:24]
wire out_wimask_788 = &_out_wimask_T_788; // @[RegisterRouter.scala:87:24]
wire out_romask_788 = |_out_romask_T_788; // @[RegisterRouter.scala:87:24]
wire out_womask_788 = &_out_womask_T_788; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_788 = out_rivalid_1_642 & out_rimask_788; // @[RegisterRouter.scala:87:24]
wire _out_T_7769 = out_f_rivalid_788; // @[RegisterRouter.scala:87:24]
wire out_f_roready_788 = out_roready_1_642 & out_romask_788; // @[RegisterRouter.scala:87:24]
wire _out_T_7770 = out_f_roready_788; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_788 = out_wivalid_1_642 & out_wimask_788; // @[RegisterRouter.scala:87:24]
wire out_f_woready_788 = out_woready_1_642 & out_womask_788; // @[RegisterRouter.scala:87:24]
wire _out_T_7771 = ~out_rimask_788; // @[RegisterRouter.scala:87:24]
wire _out_T_7772 = ~out_wimask_788; // @[RegisterRouter.scala:87:24]
wire _out_T_7773 = ~out_romask_788; // @[RegisterRouter.scala:87:24]
wire _out_T_7774 = ~out_womask_788; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_670 = {hi_474, flags_0_go, _out_prepend_T_670}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_7775 = out_prepend_670; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_7776 = _out_T_7775; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_671 = _out_T_7776; // @[RegisterRouter.scala:87:24]
wire out_rimask_789 = |_out_rimask_T_789; // @[RegisterRouter.scala:87:24]
wire out_wimask_789 = &_out_wimask_T_789; // @[RegisterRouter.scala:87:24]
wire out_romask_789 = |_out_romask_T_789; // @[RegisterRouter.scala:87:24]
wire out_womask_789 = &_out_womask_T_789; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_789 = out_rivalid_1_643 & out_rimask_789; // @[RegisterRouter.scala:87:24]
wire _out_T_7778 = out_f_rivalid_789; // @[RegisterRouter.scala:87:24]
wire out_f_roready_789 = out_roready_1_643 & out_romask_789; // @[RegisterRouter.scala:87:24]
wire _out_T_7779 = out_f_roready_789; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_789 = out_wivalid_1_643 & out_wimask_789; // @[RegisterRouter.scala:87:24]
wire out_f_woready_789 = out_woready_1_643 & out_womask_789; // @[RegisterRouter.scala:87:24]
wire _out_T_7780 = ~out_rimask_789; // @[RegisterRouter.scala:87:24]
wire _out_T_7781 = ~out_wimask_789; // @[RegisterRouter.scala:87:24]
wire _out_T_7782 = ~out_romask_789; // @[RegisterRouter.scala:87:24]
wire _out_T_7783 = ~out_womask_789; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_671 = {hi_475, flags_0_go, _out_prepend_T_671}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_7784 = out_prepend_671; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_7785 = _out_T_7784; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_672 = _out_T_7785; // @[RegisterRouter.scala:87:24]
wire out_rimask_790 = |_out_rimask_T_790; // @[RegisterRouter.scala:87:24]
wire out_wimask_790 = &_out_wimask_T_790; // @[RegisterRouter.scala:87:24]
wire out_romask_790 = |_out_romask_T_790; // @[RegisterRouter.scala:87:24]
wire out_womask_790 = &_out_womask_T_790; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_790 = out_rivalid_1_644 & out_rimask_790; // @[RegisterRouter.scala:87:24]
wire _out_T_7787 = out_f_rivalid_790; // @[RegisterRouter.scala:87:24]
wire out_f_roready_790 = out_roready_1_644 & out_romask_790; // @[RegisterRouter.scala:87:24]
wire _out_T_7788 = out_f_roready_790; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_790 = out_wivalid_1_644 & out_wimask_790; // @[RegisterRouter.scala:87:24]
wire out_f_woready_790 = out_woready_1_644 & out_womask_790; // @[RegisterRouter.scala:87:24]
wire _out_T_7789 = ~out_rimask_790; // @[RegisterRouter.scala:87:24]
wire _out_T_7790 = ~out_wimask_790; // @[RegisterRouter.scala:87:24]
wire _out_T_7791 = ~out_romask_790; // @[RegisterRouter.scala:87:24]
wire _out_T_7792 = ~out_womask_790; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_672 = {hi_476, flags_0_go, _out_prepend_T_672}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_7793 = out_prepend_672; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_7794 = _out_T_7793; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_673 = _out_T_7794; // @[RegisterRouter.scala:87:24]
wire out_rimask_791 = |_out_rimask_T_791; // @[RegisterRouter.scala:87:24]
wire out_wimask_791 = &_out_wimask_T_791; // @[RegisterRouter.scala:87:24]
wire out_romask_791 = |_out_romask_T_791; // @[RegisterRouter.scala:87:24]
wire out_womask_791 = &_out_womask_T_791; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_791 = out_rivalid_1_645 & out_rimask_791; // @[RegisterRouter.scala:87:24]
wire _out_T_7796 = out_f_rivalid_791; // @[RegisterRouter.scala:87:24]
wire out_f_roready_791 = out_roready_1_645 & out_romask_791; // @[RegisterRouter.scala:87:24]
wire _out_T_7797 = out_f_roready_791; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_791 = out_wivalid_1_645 & out_wimask_791; // @[RegisterRouter.scala:87:24]
wire out_f_woready_791 = out_woready_1_645 & out_womask_791; // @[RegisterRouter.scala:87:24]
wire _out_T_7798 = ~out_rimask_791; // @[RegisterRouter.scala:87:24]
wire _out_T_7799 = ~out_wimask_791; // @[RegisterRouter.scala:87:24]
wire _out_T_7800 = ~out_romask_791; // @[RegisterRouter.scala:87:24]
wire _out_T_7801 = ~out_womask_791; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_673 = {hi_477, flags_0_go, _out_prepend_T_673}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_7802 = out_prepend_673; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_7803 = _out_T_7802; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_674 = _out_T_7803; // @[RegisterRouter.scala:87:24]
wire out_rimask_792 = |_out_rimask_T_792; // @[RegisterRouter.scala:87:24]
wire out_wimask_792 = &_out_wimask_T_792; // @[RegisterRouter.scala:87:24]
wire out_romask_792 = |_out_romask_T_792; // @[RegisterRouter.scala:87:24]
wire out_womask_792 = &_out_womask_T_792; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_792 = out_rivalid_1_646 & out_rimask_792; // @[RegisterRouter.scala:87:24]
wire _out_T_7805 = out_f_rivalid_792; // @[RegisterRouter.scala:87:24]
wire out_f_roready_792 = out_roready_1_646 & out_romask_792; // @[RegisterRouter.scala:87:24]
wire _out_T_7806 = out_f_roready_792; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_792 = out_wivalid_1_646 & out_wimask_792; // @[RegisterRouter.scala:87:24]
wire out_f_woready_792 = out_woready_1_646 & out_womask_792; // @[RegisterRouter.scala:87:24]
wire _out_T_7807 = ~out_rimask_792; // @[RegisterRouter.scala:87:24]
wire _out_T_7808 = ~out_wimask_792; // @[RegisterRouter.scala:87:24]
wire _out_T_7809 = ~out_romask_792; // @[RegisterRouter.scala:87:24]
wire _out_T_7810 = ~out_womask_792; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_674 = {hi_478, flags_0_go, _out_prepend_T_674}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_7811 = out_prepend_674; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_7812 = _out_T_7811; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_675 = _out_T_7812; // @[RegisterRouter.scala:87:24]
wire out_rimask_793 = |_out_rimask_T_793; // @[RegisterRouter.scala:87:24]
wire out_wimask_793 = &_out_wimask_T_793; // @[RegisterRouter.scala:87:24]
wire out_romask_793 = |_out_romask_T_793; // @[RegisterRouter.scala:87:24]
wire out_womask_793 = &_out_womask_T_793; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_793 = out_rivalid_1_647 & out_rimask_793; // @[RegisterRouter.scala:87:24]
wire _out_T_7814 = out_f_rivalid_793; // @[RegisterRouter.scala:87:24]
wire out_f_roready_793 = out_roready_1_647 & out_romask_793; // @[RegisterRouter.scala:87:24]
wire _out_T_7815 = out_f_roready_793; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_793 = out_wivalid_1_647 & out_wimask_793; // @[RegisterRouter.scala:87:24]
wire out_f_woready_793 = out_woready_1_647 & out_womask_793; // @[RegisterRouter.scala:87:24]
wire _out_T_7816 = ~out_rimask_793; // @[RegisterRouter.scala:87:24]
wire _out_T_7817 = ~out_wimask_793; // @[RegisterRouter.scala:87:24]
wire _out_T_7818 = ~out_romask_793; // @[RegisterRouter.scala:87:24]
wire _out_T_7819 = ~out_womask_793; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_675 = {hi_479, flags_0_go, _out_prepend_T_675}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_7820 = out_prepend_675; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_7821 = _out_T_7820; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_676 = _out_T_7821; // @[RegisterRouter.scala:87:24]
wire out_rimask_794 = |_out_rimask_T_794; // @[RegisterRouter.scala:87:24]
wire out_wimask_794 = &_out_wimask_T_794; // @[RegisterRouter.scala:87:24]
wire out_romask_794 = |_out_romask_T_794; // @[RegisterRouter.scala:87:24]
wire out_womask_794 = &_out_womask_T_794; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_794 = out_rivalid_1_648 & out_rimask_794; // @[RegisterRouter.scala:87:24]
wire _out_T_7823 = out_f_rivalid_794; // @[RegisterRouter.scala:87:24]
wire out_f_roready_794 = out_roready_1_648 & out_romask_794; // @[RegisterRouter.scala:87:24]
wire _out_T_7824 = out_f_roready_794; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_794 = out_wivalid_1_648 & out_wimask_794; // @[RegisterRouter.scala:87:24]
wire out_f_woready_794 = out_woready_1_648 & out_womask_794; // @[RegisterRouter.scala:87:24]
wire _out_T_7825 = ~out_rimask_794; // @[RegisterRouter.scala:87:24]
wire _out_T_7826 = ~out_wimask_794; // @[RegisterRouter.scala:87:24]
wire _out_T_7827 = ~out_romask_794; // @[RegisterRouter.scala:87:24]
wire _out_T_7828 = ~out_womask_794; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_676 = {hi_480, flags_0_go, _out_prepend_T_676}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_7829 = out_prepend_676; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_7830 = _out_T_7829; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_187 = _out_T_7830; // @[MuxLiteral.scala:49:48]
wire out_rimask_795 = |_out_rimask_T_795; // @[RegisterRouter.scala:87:24]
wire out_wimask_795 = &_out_wimask_T_795; // @[RegisterRouter.scala:87:24]
wire out_romask_795 = |_out_romask_T_795; // @[RegisterRouter.scala:87:24]
wire out_womask_795 = &_out_womask_T_795; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_795 = out_rivalid_1_649 & out_rimask_795; // @[RegisterRouter.scala:87:24]
wire _out_T_7832 = out_f_rivalid_795; // @[RegisterRouter.scala:87:24]
wire out_f_roready_795 = out_roready_1_649 & out_romask_795; // @[RegisterRouter.scala:87:24]
wire _out_T_7833 = out_f_roready_795; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_795 = out_wivalid_1_649 & out_wimask_795; // @[RegisterRouter.scala:87:24]
wire out_f_woready_795 = out_woready_1_649 & out_womask_795; // @[RegisterRouter.scala:87:24]
wire _out_T_7834 = ~out_rimask_795; // @[RegisterRouter.scala:87:24]
wire _out_T_7835 = ~out_wimask_795; // @[RegisterRouter.scala:87:24]
wire _out_T_7836 = ~out_romask_795; // @[RegisterRouter.scala:87:24]
wire _out_T_7837 = ~out_womask_795; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7839 = _out_T_7838; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_677 = _out_T_7839; // @[RegisterRouter.scala:87:24]
wire out_rimask_796 = |_out_rimask_T_796; // @[RegisterRouter.scala:87:24]
wire out_wimask_796 = &_out_wimask_T_796; // @[RegisterRouter.scala:87:24]
wire out_romask_796 = |_out_romask_T_796; // @[RegisterRouter.scala:87:24]
wire out_womask_796 = &_out_womask_T_796; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_796 = out_rivalid_1_650 & out_rimask_796; // @[RegisterRouter.scala:87:24]
wire _out_T_7841 = out_f_rivalid_796; // @[RegisterRouter.scala:87:24]
wire out_f_roready_796 = out_roready_1_650 & out_romask_796; // @[RegisterRouter.scala:87:24]
wire _out_T_7842 = out_f_roready_796; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_796 = out_wivalid_1_650 & out_wimask_796; // @[RegisterRouter.scala:87:24]
wire out_f_woready_796 = out_woready_1_650 & out_womask_796; // @[RegisterRouter.scala:87:24]
wire _out_T_7843 = ~out_rimask_796; // @[RegisterRouter.scala:87:24]
wire _out_T_7844 = ~out_wimask_796; // @[RegisterRouter.scala:87:24]
wire _out_T_7845 = ~out_romask_796; // @[RegisterRouter.scala:87:24]
wire _out_T_7846 = ~out_womask_796; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_677 = {hi_354, flags_0_go, _out_prepend_T_677}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_7847 = out_prepend_677; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_7848 = _out_T_7847; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_678 = _out_T_7848; // @[RegisterRouter.scala:87:24]
wire out_rimask_797 = |_out_rimask_T_797; // @[RegisterRouter.scala:87:24]
wire out_wimask_797 = &_out_wimask_T_797; // @[RegisterRouter.scala:87:24]
wire out_romask_797 = |_out_romask_T_797; // @[RegisterRouter.scala:87:24]
wire out_womask_797 = &_out_womask_T_797; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_797 = out_rivalid_1_651 & out_rimask_797; // @[RegisterRouter.scala:87:24]
wire _out_T_7850 = out_f_rivalid_797; // @[RegisterRouter.scala:87:24]
wire out_f_roready_797 = out_roready_1_651 & out_romask_797; // @[RegisterRouter.scala:87:24]
wire _out_T_7851 = out_f_roready_797; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_797 = out_wivalid_1_651 & out_wimask_797; // @[RegisterRouter.scala:87:24]
wire out_f_woready_797 = out_woready_1_651 & out_womask_797; // @[RegisterRouter.scala:87:24]
wire _out_T_7852 = ~out_rimask_797; // @[RegisterRouter.scala:87:24]
wire _out_T_7853 = ~out_wimask_797; // @[RegisterRouter.scala:87:24]
wire _out_T_7854 = ~out_romask_797; // @[RegisterRouter.scala:87:24]
wire _out_T_7855 = ~out_womask_797; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_678 = {hi_355, flags_0_go, _out_prepend_T_678}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_7856 = out_prepend_678; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_7857 = _out_T_7856; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_679 = _out_T_7857; // @[RegisterRouter.scala:87:24]
wire out_rimask_798 = |_out_rimask_T_798; // @[RegisterRouter.scala:87:24]
wire out_wimask_798 = &_out_wimask_T_798; // @[RegisterRouter.scala:87:24]
wire out_romask_798 = |_out_romask_T_798; // @[RegisterRouter.scala:87:24]
wire out_womask_798 = &_out_womask_T_798; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_798 = out_rivalid_1_652 & out_rimask_798; // @[RegisterRouter.scala:87:24]
wire _out_T_7859 = out_f_rivalid_798; // @[RegisterRouter.scala:87:24]
wire out_f_roready_798 = out_roready_1_652 & out_romask_798; // @[RegisterRouter.scala:87:24]
wire _out_T_7860 = out_f_roready_798; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_798 = out_wivalid_1_652 & out_wimask_798; // @[RegisterRouter.scala:87:24]
wire out_f_woready_798 = out_woready_1_652 & out_womask_798; // @[RegisterRouter.scala:87:24]
wire _out_T_7861 = ~out_rimask_798; // @[RegisterRouter.scala:87:24]
wire _out_T_7862 = ~out_wimask_798; // @[RegisterRouter.scala:87:24]
wire _out_T_7863 = ~out_romask_798; // @[RegisterRouter.scala:87:24]
wire _out_T_7864 = ~out_womask_798; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_679 = {hi_356, flags_0_go, _out_prepend_T_679}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_7865 = out_prepend_679; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_7866 = _out_T_7865; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_680 = _out_T_7866; // @[RegisterRouter.scala:87:24]
wire out_rimask_799 = |_out_rimask_T_799; // @[RegisterRouter.scala:87:24]
wire out_wimask_799 = &_out_wimask_T_799; // @[RegisterRouter.scala:87:24]
wire out_romask_799 = |_out_romask_T_799; // @[RegisterRouter.scala:87:24]
wire out_womask_799 = &_out_womask_T_799; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_799 = out_rivalid_1_653 & out_rimask_799; // @[RegisterRouter.scala:87:24]
wire _out_T_7868 = out_f_rivalid_799; // @[RegisterRouter.scala:87:24]
wire out_f_roready_799 = out_roready_1_653 & out_romask_799; // @[RegisterRouter.scala:87:24]
wire _out_T_7869 = out_f_roready_799; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_799 = out_wivalid_1_653 & out_wimask_799; // @[RegisterRouter.scala:87:24]
wire out_f_woready_799 = out_woready_1_653 & out_womask_799; // @[RegisterRouter.scala:87:24]
wire _out_T_7870 = ~out_rimask_799; // @[RegisterRouter.scala:87:24]
wire _out_T_7871 = ~out_wimask_799; // @[RegisterRouter.scala:87:24]
wire _out_T_7872 = ~out_romask_799; // @[RegisterRouter.scala:87:24]
wire _out_T_7873 = ~out_womask_799; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_680 = {hi_357, flags_0_go, _out_prepend_T_680}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_7874 = out_prepend_680; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_7875 = _out_T_7874; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_681 = _out_T_7875; // @[RegisterRouter.scala:87:24]
wire out_rimask_800 = |_out_rimask_T_800; // @[RegisterRouter.scala:87:24]
wire out_wimask_800 = &_out_wimask_T_800; // @[RegisterRouter.scala:87:24]
wire out_romask_800 = |_out_romask_T_800; // @[RegisterRouter.scala:87:24]
wire out_womask_800 = &_out_womask_T_800; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_800 = out_rivalid_1_654 & out_rimask_800; // @[RegisterRouter.scala:87:24]
wire _out_T_7877 = out_f_rivalid_800; // @[RegisterRouter.scala:87:24]
wire out_f_roready_800 = out_roready_1_654 & out_romask_800; // @[RegisterRouter.scala:87:24]
wire _out_T_7878 = out_f_roready_800; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_800 = out_wivalid_1_654 & out_wimask_800; // @[RegisterRouter.scala:87:24]
wire out_f_woready_800 = out_woready_1_654 & out_womask_800; // @[RegisterRouter.scala:87:24]
wire _out_T_7879 = ~out_rimask_800; // @[RegisterRouter.scala:87:24]
wire _out_T_7880 = ~out_wimask_800; // @[RegisterRouter.scala:87:24]
wire _out_T_7881 = ~out_romask_800; // @[RegisterRouter.scala:87:24]
wire _out_T_7882 = ~out_womask_800; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_681 = {hi_358, flags_0_go, _out_prepend_T_681}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_7883 = out_prepend_681; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_7884 = _out_T_7883; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_682 = _out_T_7884; // @[RegisterRouter.scala:87:24]
wire out_rimask_801 = |_out_rimask_T_801; // @[RegisterRouter.scala:87:24]
wire out_wimask_801 = &_out_wimask_T_801; // @[RegisterRouter.scala:87:24]
wire out_romask_801 = |_out_romask_T_801; // @[RegisterRouter.scala:87:24]
wire out_womask_801 = &_out_womask_T_801; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_801 = out_rivalid_1_655 & out_rimask_801; // @[RegisterRouter.scala:87:24]
wire _out_T_7886 = out_f_rivalid_801; // @[RegisterRouter.scala:87:24]
wire out_f_roready_801 = out_roready_1_655 & out_romask_801; // @[RegisterRouter.scala:87:24]
wire _out_T_7887 = out_f_roready_801; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_801 = out_wivalid_1_655 & out_wimask_801; // @[RegisterRouter.scala:87:24]
wire out_f_woready_801 = out_woready_1_655 & out_womask_801; // @[RegisterRouter.scala:87:24]
wire _out_T_7888 = ~out_rimask_801; // @[RegisterRouter.scala:87:24]
wire _out_T_7889 = ~out_wimask_801; // @[RegisterRouter.scala:87:24]
wire _out_T_7890 = ~out_romask_801; // @[RegisterRouter.scala:87:24]
wire _out_T_7891 = ~out_womask_801; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_682 = {hi_359, flags_0_go, _out_prepend_T_682}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_7892 = out_prepend_682; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_7893 = _out_T_7892; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_683 = _out_T_7893; // @[RegisterRouter.scala:87:24]
wire out_rimask_802 = |_out_rimask_T_802; // @[RegisterRouter.scala:87:24]
wire out_wimask_802 = &_out_wimask_T_802; // @[RegisterRouter.scala:87:24]
wire out_romask_802 = |_out_romask_T_802; // @[RegisterRouter.scala:87:24]
wire out_womask_802 = &_out_womask_T_802; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_802 = out_rivalid_1_656 & out_rimask_802; // @[RegisterRouter.scala:87:24]
wire _out_T_7895 = out_f_rivalid_802; // @[RegisterRouter.scala:87:24]
wire out_f_roready_802 = out_roready_1_656 & out_romask_802; // @[RegisterRouter.scala:87:24]
wire _out_T_7896 = out_f_roready_802; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_802 = out_wivalid_1_656 & out_wimask_802; // @[RegisterRouter.scala:87:24]
wire out_f_woready_802 = out_woready_1_656 & out_womask_802; // @[RegisterRouter.scala:87:24]
wire _out_T_7897 = ~out_rimask_802; // @[RegisterRouter.scala:87:24]
wire _out_T_7898 = ~out_wimask_802; // @[RegisterRouter.scala:87:24]
wire _out_T_7899 = ~out_romask_802; // @[RegisterRouter.scala:87:24]
wire _out_T_7900 = ~out_womask_802; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_683 = {hi_360, flags_0_go, _out_prepend_T_683}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_7901 = out_prepend_683; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_7902 = _out_T_7901; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_172 = _out_T_7902; // @[MuxLiteral.scala:49:48]
wire out_rimask_803 = |_out_rimask_T_803; // @[RegisterRouter.scala:87:24]
wire out_wimask_803 = &_out_wimask_T_803; // @[RegisterRouter.scala:87:24]
wire out_romask_803 = |_out_romask_T_803; // @[RegisterRouter.scala:87:24]
wire out_womask_803 = &_out_womask_T_803; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_803 = out_rivalid_1_657 & out_rimask_803; // @[RegisterRouter.scala:87:24]
wire _out_T_7904 = out_f_rivalid_803; // @[RegisterRouter.scala:87:24]
wire out_f_roready_803 = out_roready_1_657 & out_romask_803; // @[RegisterRouter.scala:87:24]
wire _out_T_7905 = out_f_roready_803; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_803 = out_wivalid_1_657 & out_wimask_803; // @[RegisterRouter.scala:87:24]
wire _out_T_7906 = out_f_wivalid_803; // @[RegisterRouter.scala:87:24]
wire out_f_woready_803 = out_woready_1_657 & out_womask_803; // @[RegisterRouter.scala:87:24]
wire _out_T_7907 = out_f_woready_803; // @[RegisterRouter.scala:87:24]
wire _out_T_7908 = ~out_rimask_803; // @[RegisterRouter.scala:87:24]
wire _out_T_7909 = ~out_wimask_803; // @[RegisterRouter.scala:87:24]
wire _out_T_7910 = ~out_romask_803; // @[RegisterRouter.scala:87:24]
wire _out_T_7911 = ~out_womask_803; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7913 = _out_T_7912; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_684 = _out_T_7913; // @[RegisterRouter.scala:87:24]
wire out_rimask_804 = |_out_rimask_T_804; // @[RegisterRouter.scala:87:24]
wire out_wimask_804 = &_out_wimask_T_804; // @[RegisterRouter.scala:87:24]
wire out_romask_804 = |_out_romask_T_804; // @[RegisterRouter.scala:87:24]
wire out_womask_804 = &_out_womask_T_804; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_804 = out_rivalid_1_658 & out_rimask_804; // @[RegisterRouter.scala:87:24]
wire _out_T_7915 = out_f_rivalid_804; // @[RegisterRouter.scala:87:24]
wire out_f_roready_804 = out_roready_1_658 & out_romask_804; // @[RegisterRouter.scala:87:24]
wire _out_T_7916 = out_f_roready_804; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_804 = out_wivalid_1_658 & out_wimask_804; // @[RegisterRouter.scala:87:24]
wire _out_T_7917 = out_f_wivalid_804; // @[RegisterRouter.scala:87:24]
wire out_f_woready_804 = out_woready_1_658 & out_womask_804; // @[RegisterRouter.scala:87:24]
wire _out_T_7918 = out_f_woready_804; // @[RegisterRouter.scala:87:24]
wire _out_T_7919 = ~out_rimask_804; // @[RegisterRouter.scala:87:24]
wire _out_T_7920 = ~out_wimask_804; // @[RegisterRouter.scala:87:24]
wire _out_T_7921 = ~out_romask_804; // @[RegisterRouter.scala:87:24]
wire _out_T_7922 = ~out_womask_804; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_684 = {abstractDataMem_9, _out_prepend_T_684}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_7923 = out_prepend_684; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_7924 = _out_T_7923; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_685 = _out_T_7924; // @[RegisterRouter.scala:87:24]
wire out_rimask_805 = |_out_rimask_T_805; // @[RegisterRouter.scala:87:24]
wire out_wimask_805 = &_out_wimask_T_805; // @[RegisterRouter.scala:87:24]
wire out_romask_805 = |_out_romask_T_805; // @[RegisterRouter.scala:87:24]
wire out_womask_805 = &_out_womask_T_805; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_805 = out_rivalid_1_659 & out_rimask_805; // @[RegisterRouter.scala:87:24]
wire _out_T_7926 = out_f_rivalid_805; // @[RegisterRouter.scala:87:24]
wire out_f_roready_805 = out_roready_1_659 & out_romask_805; // @[RegisterRouter.scala:87:24]
wire _out_T_7927 = out_f_roready_805; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_805 = out_wivalid_1_659 & out_wimask_805; // @[RegisterRouter.scala:87:24]
wire _out_T_7928 = out_f_wivalid_805; // @[RegisterRouter.scala:87:24]
wire out_f_woready_805 = out_woready_1_659 & out_womask_805; // @[RegisterRouter.scala:87:24]
wire _out_T_7929 = out_f_woready_805; // @[RegisterRouter.scala:87:24]
wire _out_T_7930 = ~out_rimask_805; // @[RegisterRouter.scala:87:24]
wire _out_T_7931 = ~out_wimask_805; // @[RegisterRouter.scala:87:24]
wire _out_T_7932 = ~out_romask_805; // @[RegisterRouter.scala:87:24]
wire _out_T_7933 = ~out_womask_805; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_685 = {abstractDataMem_10, _out_prepend_T_685}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_7934 = out_prepend_685; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_7935 = _out_T_7934; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_686 = _out_T_7935; // @[RegisterRouter.scala:87:24]
wire out_rimask_806 = |_out_rimask_T_806; // @[RegisterRouter.scala:87:24]
wire out_wimask_806 = &_out_wimask_T_806; // @[RegisterRouter.scala:87:24]
wire out_romask_806 = |_out_romask_T_806; // @[RegisterRouter.scala:87:24]
wire out_womask_806 = &_out_womask_T_806; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_806 = out_rivalid_1_660 & out_rimask_806; // @[RegisterRouter.scala:87:24]
wire _out_T_7937 = out_f_rivalid_806; // @[RegisterRouter.scala:87:24]
wire out_f_roready_806 = out_roready_1_660 & out_romask_806; // @[RegisterRouter.scala:87:24]
wire _out_T_7938 = out_f_roready_806; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_806 = out_wivalid_1_660 & out_wimask_806; // @[RegisterRouter.scala:87:24]
wire _out_T_7939 = out_f_wivalid_806; // @[RegisterRouter.scala:87:24]
wire out_f_woready_806 = out_woready_1_660 & out_womask_806; // @[RegisterRouter.scala:87:24]
wire _out_T_7940 = out_f_woready_806; // @[RegisterRouter.scala:87:24]
wire _out_T_7941 = ~out_rimask_806; // @[RegisterRouter.scala:87:24]
wire _out_T_7942 = ~out_wimask_806; // @[RegisterRouter.scala:87:24]
wire _out_T_7943 = ~out_romask_806; // @[RegisterRouter.scala:87:24]
wire _out_T_7944 = ~out_womask_806; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_686 = {abstractDataMem_11, _out_prepend_T_686}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_7945 = out_prepend_686; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_7946 = _out_T_7945; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_687 = _out_T_7946; // @[RegisterRouter.scala:87:24]
wire out_rimask_807 = |_out_rimask_T_807; // @[RegisterRouter.scala:87:24]
wire out_wimask_807 = &_out_wimask_T_807; // @[RegisterRouter.scala:87:24]
wire out_romask_807 = |_out_romask_T_807; // @[RegisterRouter.scala:87:24]
wire out_womask_807 = &_out_womask_T_807; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_807 = out_rivalid_1_661 & out_rimask_807; // @[RegisterRouter.scala:87:24]
wire _out_T_7948 = out_f_rivalid_807; // @[RegisterRouter.scala:87:24]
wire out_f_roready_807 = out_roready_1_661 & out_romask_807; // @[RegisterRouter.scala:87:24]
wire _out_T_7949 = out_f_roready_807; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_807 = out_wivalid_1_661 & out_wimask_807; // @[RegisterRouter.scala:87:24]
wire _out_T_7950 = out_f_wivalid_807; // @[RegisterRouter.scala:87:24]
wire out_f_woready_807 = out_woready_1_661 & out_womask_807; // @[RegisterRouter.scala:87:24]
wire _out_T_7951 = out_f_woready_807; // @[RegisterRouter.scala:87:24]
wire _out_T_7952 = ~out_rimask_807; // @[RegisterRouter.scala:87:24]
wire _out_T_7953 = ~out_wimask_807; // @[RegisterRouter.scala:87:24]
wire _out_T_7954 = ~out_romask_807; // @[RegisterRouter.scala:87:24]
wire _out_T_7955 = ~out_womask_807; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_687 = {abstractDataMem_12, _out_prepend_T_687}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_7956 = out_prepend_687; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_7957 = _out_T_7956; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_688 = _out_T_7957; // @[RegisterRouter.scala:87:24]
wire out_rimask_808 = |_out_rimask_T_808; // @[RegisterRouter.scala:87:24]
wire out_wimask_808 = &_out_wimask_T_808; // @[RegisterRouter.scala:87:24]
wire out_romask_808 = |_out_romask_T_808; // @[RegisterRouter.scala:87:24]
wire out_womask_808 = &_out_womask_T_808; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_808 = out_rivalid_1_662 & out_rimask_808; // @[RegisterRouter.scala:87:24]
wire _out_T_7959 = out_f_rivalid_808; // @[RegisterRouter.scala:87:24]
wire out_f_roready_808 = out_roready_1_662 & out_romask_808; // @[RegisterRouter.scala:87:24]
wire _out_T_7960 = out_f_roready_808; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_808 = out_wivalid_1_662 & out_wimask_808; // @[RegisterRouter.scala:87:24]
wire _out_T_7961 = out_f_wivalid_808; // @[RegisterRouter.scala:87:24]
wire out_f_woready_808 = out_woready_1_662 & out_womask_808; // @[RegisterRouter.scala:87:24]
wire _out_T_7962 = out_f_woready_808; // @[RegisterRouter.scala:87:24]
wire _out_T_7963 = ~out_rimask_808; // @[RegisterRouter.scala:87:24]
wire _out_T_7964 = ~out_wimask_808; // @[RegisterRouter.scala:87:24]
wire _out_T_7965 = ~out_romask_808; // @[RegisterRouter.scala:87:24]
wire _out_T_7966 = ~out_womask_808; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_688 = {abstractDataMem_13, _out_prepend_T_688}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_7967 = out_prepend_688; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_7968 = _out_T_7967; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_689 = _out_T_7968; // @[RegisterRouter.scala:87:24]
wire out_rimask_809 = |_out_rimask_T_809; // @[RegisterRouter.scala:87:24]
wire out_wimask_809 = &_out_wimask_T_809; // @[RegisterRouter.scala:87:24]
wire out_romask_809 = |_out_romask_T_809; // @[RegisterRouter.scala:87:24]
wire out_womask_809 = &_out_womask_T_809; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_809 = out_rivalid_1_663 & out_rimask_809; // @[RegisterRouter.scala:87:24]
wire _out_T_7970 = out_f_rivalid_809; // @[RegisterRouter.scala:87:24]
wire out_f_roready_809 = out_roready_1_663 & out_romask_809; // @[RegisterRouter.scala:87:24]
wire _out_T_7971 = out_f_roready_809; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_809 = out_wivalid_1_663 & out_wimask_809; // @[RegisterRouter.scala:87:24]
wire _out_T_7972 = out_f_wivalid_809; // @[RegisterRouter.scala:87:24]
wire out_f_woready_809 = out_woready_1_663 & out_womask_809; // @[RegisterRouter.scala:87:24]
wire _out_T_7973 = out_f_woready_809; // @[RegisterRouter.scala:87:24]
wire _out_T_7974 = ~out_rimask_809; // @[RegisterRouter.scala:87:24]
wire _out_T_7975 = ~out_wimask_809; // @[RegisterRouter.scala:87:24]
wire _out_T_7976 = ~out_romask_809; // @[RegisterRouter.scala:87:24]
wire _out_T_7977 = ~out_womask_809; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_689 = {abstractDataMem_14, _out_prepend_T_689}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_7978 = out_prepend_689; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_7979 = _out_T_7978; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_690 = _out_T_7979; // @[RegisterRouter.scala:87:24]
wire out_rimask_810 = |_out_rimask_T_810; // @[RegisterRouter.scala:87:24]
wire out_wimask_810 = &_out_wimask_T_810; // @[RegisterRouter.scala:87:24]
wire out_romask_810 = |_out_romask_T_810; // @[RegisterRouter.scala:87:24]
wire out_womask_810 = &_out_womask_T_810; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_810 = out_rivalid_1_664 & out_rimask_810; // @[RegisterRouter.scala:87:24]
wire _out_T_7981 = out_f_rivalid_810; // @[RegisterRouter.scala:87:24]
wire out_f_roready_810 = out_roready_1_664 & out_romask_810; // @[RegisterRouter.scala:87:24]
wire _out_T_7982 = out_f_roready_810; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_810 = out_wivalid_1_664 & out_wimask_810; // @[RegisterRouter.scala:87:24]
wire _out_T_7983 = out_f_wivalid_810; // @[RegisterRouter.scala:87:24]
wire out_f_woready_810 = out_woready_1_664 & out_womask_810; // @[RegisterRouter.scala:87:24]
wire _out_T_7984 = out_f_woready_810; // @[RegisterRouter.scala:87:24]
wire _out_T_7985 = ~out_rimask_810; // @[RegisterRouter.scala:87:24]
wire _out_T_7986 = ~out_wimask_810; // @[RegisterRouter.scala:87:24]
wire _out_T_7987 = ~out_romask_810; // @[RegisterRouter.scala:87:24]
wire _out_T_7988 = ~out_womask_810; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_690 = {abstractDataMem_15, _out_prepend_T_690}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_7989 = out_prepend_690; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_7990 = _out_T_7989; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_113 = _out_T_7990; // @[MuxLiteral.scala:49:48]
wire out_rimask_811 = |_out_rimask_T_811; // @[RegisterRouter.scala:87:24]
wire out_wimask_811 = &_out_wimask_T_811; // @[RegisterRouter.scala:87:24]
wire out_romask_811 = |_out_romask_T_811; // @[RegisterRouter.scala:87:24]
wire out_womask_811 = &_out_womask_T_811; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_811 = out_rivalid_1_665 & out_rimask_811; // @[RegisterRouter.scala:87:24]
wire _out_T_7992 = out_f_rivalid_811; // @[RegisterRouter.scala:87:24]
wire out_f_roready_811 = out_roready_1_665 & out_romask_811; // @[RegisterRouter.scala:87:24]
wire _out_T_7993 = out_f_roready_811; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_811 = out_wivalid_1_665 & out_wimask_811; // @[RegisterRouter.scala:87:24]
wire out_f_woready_811 = out_woready_1_665 & out_womask_811; // @[RegisterRouter.scala:87:24]
wire _out_T_7994 = ~out_rimask_811; // @[RegisterRouter.scala:87:24]
wire _out_T_7995 = ~out_wimask_811; // @[RegisterRouter.scala:87:24]
wire _out_T_7996 = ~out_romask_811; // @[RegisterRouter.scala:87:24]
wire _out_T_7997 = ~out_womask_811; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_7999 = _out_T_7998; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_691 = _out_T_7999; // @[RegisterRouter.scala:87:24]
wire out_rimask_812 = |_out_rimask_T_812; // @[RegisterRouter.scala:87:24]
wire out_wimask_812 = &_out_wimask_T_812; // @[RegisterRouter.scala:87:24]
wire out_romask_812 = |_out_romask_T_812; // @[RegisterRouter.scala:87:24]
wire out_womask_812 = &_out_womask_T_812; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_812 = out_rivalid_1_666 & out_rimask_812; // @[RegisterRouter.scala:87:24]
wire _out_T_8001 = out_f_rivalid_812; // @[RegisterRouter.scala:87:24]
wire out_f_roready_812 = out_roready_1_666 & out_romask_812; // @[RegisterRouter.scala:87:24]
wire _out_T_8002 = out_f_roready_812; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_812 = out_wivalid_1_666 & out_wimask_812; // @[RegisterRouter.scala:87:24]
wire out_f_woready_812 = out_woready_1_666 & out_womask_812; // @[RegisterRouter.scala:87:24]
wire _out_T_8003 = ~out_rimask_812; // @[RegisterRouter.scala:87:24]
wire _out_T_8004 = ~out_wimask_812; // @[RegisterRouter.scala:87:24]
wire _out_T_8005 = ~out_romask_812; // @[RegisterRouter.scala:87:24]
wire _out_T_8006 = ~out_womask_812; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_691 = {hi_730, flags_0_go, _out_prepend_T_691}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_8007 = out_prepend_691; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_8008 = _out_T_8007; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_692 = _out_T_8008; // @[RegisterRouter.scala:87:24]
wire out_rimask_813 = |_out_rimask_T_813; // @[RegisterRouter.scala:87:24]
wire out_wimask_813 = &_out_wimask_T_813; // @[RegisterRouter.scala:87:24]
wire out_romask_813 = |_out_romask_T_813; // @[RegisterRouter.scala:87:24]
wire out_womask_813 = &_out_womask_T_813; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_813 = out_rivalid_1_667 & out_rimask_813; // @[RegisterRouter.scala:87:24]
wire _out_T_8010 = out_f_rivalid_813; // @[RegisterRouter.scala:87:24]
wire out_f_roready_813 = out_roready_1_667 & out_romask_813; // @[RegisterRouter.scala:87:24]
wire _out_T_8011 = out_f_roready_813; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_813 = out_wivalid_1_667 & out_wimask_813; // @[RegisterRouter.scala:87:24]
wire out_f_woready_813 = out_woready_1_667 & out_womask_813; // @[RegisterRouter.scala:87:24]
wire _out_T_8012 = ~out_rimask_813; // @[RegisterRouter.scala:87:24]
wire _out_T_8013 = ~out_wimask_813; // @[RegisterRouter.scala:87:24]
wire _out_T_8014 = ~out_romask_813; // @[RegisterRouter.scala:87:24]
wire _out_T_8015 = ~out_womask_813; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_692 = {hi_731, flags_0_go, _out_prepend_T_692}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_8016 = out_prepend_692; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_8017 = _out_T_8016; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_693 = _out_T_8017; // @[RegisterRouter.scala:87:24]
wire out_rimask_814 = |_out_rimask_T_814; // @[RegisterRouter.scala:87:24]
wire out_wimask_814 = &_out_wimask_T_814; // @[RegisterRouter.scala:87:24]
wire out_romask_814 = |_out_romask_T_814; // @[RegisterRouter.scala:87:24]
wire out_womask_814 = &_out_womask_T_814; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_814 = out_rivalid_1_668 & out_rimask_814; // @[RegisterRouter.scala:87:24]
wire _out_T_8019 = out_f_rivalid_814; // @[RegisterRouter.scala:87:24]
wire out_f_roready_814 = out_roready_1_668 & out_romask_814; // @[RegisterRouter.scala:87:24]
wire _out_T_8020 = out_f_roready_814; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_814 = out_wivalid_1_668 & out_wimask_814; // @[RegisterRouter.scala:87:24]
wire out_f_woready_814 = out_woready_1_668 & out_womask_814; // @[RegisterRouter.scala:87:24]
wire _out_T_8021 = ~out_rimask_814; // @[RegisterRouter.scala:87:24]
wire _out_T_8022 = ~out_wimask_814; // @[RegisterRouter.scala:87:24]
wire _out_T_8023 = ~out_romask_814; // @[RegisterRouter.scala:87:24]
wire _out_T_8024 = ~out_womask_814; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_693 = {hi_732, flags_0_go, _out_prepend_T_693}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_8025 = out_prepend_693; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_8026 = _out_T_8025; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_694 = _out_T_8026; // @[RegisterRouter.scala:87:24]
wire out_rimask_815 = |_out_rimask_T_815; // @[RegisterRouter.scala:87:24]
wire out_wimask_815 = &_out_wimask_T_815; // @[RegisterRouter.scala:87:24]
wire out_romask_815 = |_out_romask_T_815; // @[RegisterRouter.scala:87:24]
wire out_womask_815 = &_out_womask_T_815; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_815 = out_rivalid_1_669 & out_rimask_815; // @[RegisterRouter.scala:87:24]
wire _out_T_8028 = out_f_rivalid_815; // @[RegisterRouter.scala:87:24]
wire out_f_roready_815 = out_roready_1_669 & out_romask_815; // @[RegisterRouter.scala:87:24]
wire _out_T_8029 = out_f_roready_815; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_815 = out_wivalid_1_669 & out_wimask_815; // @[RegisterRouter.scala:87:24]
wire out_f_woready_815 = out_woready_1_669 & out_womask_815; // @[RegisterRouter.scala:87:24]
wire _out_T_8030 = ~out_rimask_815; // @[RegisterRouter.scala:87:24]
wire _out_T_8031 = ~out_wimask_815; // @[RegisterRouter.scala:87:24]
wire _out_T_8032 = ~out_romask_815; // @[RegisterRouter.scala:87:24]
wire _out_T_8033 = ~out_womask_815; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_694 = {hi_733, flags_0_go, _out_prepend_T_694}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_8034 = out_prepend_694; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_8035 = _out_T_8034; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_695 = _out_T_8035; // @[RegisterRouter.scala:87:24]
wire out_rimask_816 = |_out_rimask_T_816; // @[RegisterRouter.scala:87:24]
wire out_wimask_816 = &_out_wimask_T_816; // @[RegisterRouter.scala:87:24]
wire out_romask_816 = |_out_romask_T_816; // @[RegisterRouter.scala:87:24]
wire out_womask_816 = &_out_womask_T_816; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_816 = out_rivalid_1_670 & out_rimask_816; // @[RegisterRouter.scala:87:24]
wire _out_T_8037 = out_f_rivalid_816; // @[RegisterRouter.scala:87:24]
wire out_f_roready_816 = out_roready_1_670 & out_romask_816; // @[RegisterRouter.scala:87:24]
wire _out_T_8038 = out_f_roready_816; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_816 = out_wivalid_1_670 & out_wimask_816; // @[RegisterRouter.scala:87:24]
wire out_f_woready_816 = out_woready_1_670 & out_womask_816; // @[RegisterRouter.scala:87:24]
wire _out_T_8039 = ~out_rimask_816; // @[RegisterRouter.scala:87:24]
wire _out_T_8040 = ~out_wimask_816; // @[RegisterRouter.scala:87:24]
wire _out_T_8041 = ~out_romask_816; // @[RegisterRouter.scala:87:24]
wire _out_T_8042 = ~out_womask_816; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_695 = {hi_734, flags_0_go, _out_prepend_T_695}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_8043 = out_prepend_695; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_8044 = _out_T_8043; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_696 = _out_T_8044; // @[RegisterRouter.scala:87:24]
wire out_rimask_817 = |_out_rimask_T_817; // @[RegisterRouter.scala:87:24]
wire out_wimask_817 = &_out_wimask_T_817; // @[RegisterRouter.scala:87:24]
wire out_romask_817 = |_out_romask_T_817; // @[RegisterRouter.scala:87:24]
wire out_womask_817 = &_out_womask_T_817; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_817 = out_rivalid_1_671 & out_rimask_817; // @[RegisterRouter.scala:87:24]
wire _out_T_8046 = out_f_rivalid_817; // @[RegisterRouter.scala:87:24]
wire out_f_roready_817 = out_roready_1_671 & out_romask_817; // @[RegisterRouter.scala:87:24]
wire _out_T_8047 = out_f_roready_817; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_817 = out_wivalid_1_671 & out_wimask_817; // @[RegisterRouter.scala:87:24]
wire out_f_woready_817 = out_woready_1_671 & out_womask_817; // @[RegisterRouter.scala:87:24]
wire _out_T_8048 = ~out_rimask_817; // @[RegisterRouter.scala:87:24]
wire _out_T_8049 = ~out_wimask_817; // @[RegisterRouter.scala:87:24]
wire _out_T_8050 = ~out_romask_817; // @[RegisterRouter.scala:87:24]
wire _out_T_8051 = ~out_womask_817; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_696 = {hi_735, flags_0_go, _out_prepend_T_696}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_8052 = out_prepend_696; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_8053 = _out_T_8052; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_697 = _out_T_8053; // @[RegisterRouter.scala:87:24]
wire out_rimask_818 = |_out_rimask_T_818; // @[RegisterRouter.scala:87:24]
wire out_wimask_818 = &_out_wimask_T_818; // @[RegisterRouter.scala:87:24]
wire out_romask_818 = |_out_romask_T_818; // @[RegisterRouter.scala:87:24]
wire out_womask_818 = &_out_womask_T_818; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_818 = out_rivalid_1_672 & out_rimask_818; // @[RegisterRouter.scala:87:24]
wire _out_T_8055 = out_f_rivalid_818; // @[RegisterRouter.scala:87:24]
wire out_f_roready_818 = out_roready_1_672 & out_romask_818; // @[RegisterRouter.scala:87:24]
wire _out_T_8056 = out_f_roready_818; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_818 = out_wivalid_1_672 & out_wimask_818; // @[RegisterRouter.scala:87:24]
wire out_f_woready_818 = out_woready_1_672 & out_womask_818; // @[RegisterRouter.scala:87:24]
wire _out_T_8057 = ~out_rimask_818; // @[RegisterRouter.scala:87:24]
wire _out_T_8058 = ~out_wimask_818; // @[RegisterRouter.scala:87:24]
wire _out_T_8059 = ~out_romask_818; // @[RegisterRouter.scala:87:24]
wire _out_T_8060 = ~out_womask_818; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_697 = {hi_736, flags_0_go, _out_prepend_T_697}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_8061 = out_prepend_697; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_8062 = _out_T_8061; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_219 = _out_T_8062; // @[MuxLiteral.scala:49:48]
wire out_rimask_819 = |_out_rimask_T_819; // @[RegisterRouter.scala:87:24]
wire out_wimask_819 = &_out_wimask_T_819; // @[RegisterRouter.scala:87:24]
wire out_romask_819 = |_out_romask_T_819; // @[RegisterRouter.scala:87:24]
wire out_womask_819 = &_out_womask_T_819; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_819 = out_rivalid_1_673 & out_rimask_819; // @[RegisterRouter.scala:87:24]
wire _out_T_8064 = out_f_rivalid_819; // @[RegisterRouter.scala:87:24]
wire out_f_roready_819 = out_roready_1_673 & out_romask_819; // @[RegisterRouter.scala:87:24]
wire _out_T_8065 = out_f_roready_819; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_819 = out_wivalid_1_673 & out_wimask_819; // @[RegisterRouter.scala:87:24]
wire out_f_woready_819 = out_woready_1_673 & out_womask_819; // @[RegisterRouter.scala:87:24]
wire _out_T_8066 = ~out_rimask_819; // @[RegisterRouter.scala:87:24]
wire _out_T_8067 = ~out_wimask_819; // @[RegisterRouter.scala:87:24]
wire _out_T_8068 = ~out_romask_819; // @[RegisterRouter.scala:87:24]
wire _out_T_8069 = ~out_womask_819; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8071 = _out_T_8070; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_698 = _out_T_8071; // @[RegisterRouter.scala:87:24]
wire out_rimask_820 = |_out_rimask_T_820; // @[RegisterRouter.scala:87:24]
wire out_wimask_820 = &_out_wimask_T_820; // @[RegisterRouter.scala:87:24]
wire out_romask_820 = |_out_romask_T_820; // @[RegisterRouter.scala:87:24]
wire out_womask_820 = &_out_womask_T_820; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_820 = out_rivalid_1_674 & out_rimask_820; // @[RegisterRouter.scala:87:24]
wire _out_T_8073 = out_f_rivalid_820; // @[RegisterRouter.scala:87:24]
wire out_f_roready_820 = out_roready_1_674 & out_romask_820; // @[RegisterRouter.scala:87:24]
wire _out_T_8074 = out_f_roready_820; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_820 = out_wivalid_1_674 & out_wimask_820; // @[RegisterRouter.scala:87:24]
wire out_f_woready_820 = out_woready_1_674 & out_womask_820; // @[RegisterRouter.scala:87:24]
wire _out_T_8075 = ~out_rimask_820; // @[RegisterRouter.scala:87:24]
wire _out_T_8076 = ~out_wimask_820; // @[RegisterRouter.scala:87:24]
wire _out_T_8077 = ~out_romask_820; // @[RegisterRouter.scala:87:24]
wire _out_T_8078 = ~out_womask_820; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_698 = {hi_818, flags_0_go, _out_prepend_T_698}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_8079 = out_prepend_698; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_8080 = _out_T_8079; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_699 = _out_T_8080; // @[RegisterRouter.scala:87:24]
wire out_rimask_821 = |_out_rimask_T_821; // @[RegisterRouter.scala:87:24]
wire out_wimask_821 = &_out_wimask_T_821; // @[RegisterRouter.scala:87:24]
wire out_romask_821 = |_out_romask_T_821; // @[RegisterRouter.scala:87:24]
wire out_womask_821 = &_out_womask_T_821; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_821 = out_rivalid_1_675 & out_rimask_821; // @[RegisterRouter.scala:87:24]
wire _out_T_8082 = out_f_rivalid_821; // @[RegisterRouter.scala:87:24]
wire out_f_roready_821 = out_roready_1_675 & out_romask_821; // @[RegisterRouter.scala:87:24]
wire _out_T_8083 = out_f_roready_821; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_821 = out_wivalid_1_675 & out_wimask_821; // @[RegisterRouter.scala:87:24]
wire out_f_woready_821 = out_woready_1_675 & out_womask_821; // @[RegisterRouter.scala:87:24]
wire _out_T_8084 = ~out_rimask_821; // @[RegisterRouter.scala:87:24]
wire _out_T_8085 = ~out_wimask_821; // @[RegisterRouter.scala:87:24]
wire _out_T_8086 = ~out_romask_821; // @[RegisterRouter.scala:87:24]
wire _out_T_8087 = ~out_womask_821; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_699 = {hi_819, flags_0_go, _out_prepend_T_699}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_8088 = out_prepend_699; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_8089 = _out_T_8088; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_700 = _out_T_8089; // @[RegisterRouter.scala:87:24]
wire out_rimask_822 = |_out_rimask_T_822; // @[RegisterRouter.scala:87:24]
wire out_wimask_822 = &_out_wimask_T_822; // @[RegisterRouter.scala:87:24]
wire out_romask_822 = |_out_romask_T_822; // @[RegisterRouter.scala:87:24]
wire out_womask_822 = &_out_womask_T_822; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_822 = out_rivalid_1_676 & out_rimask_822; // @[RegisterRouter.scala:87:24]
wire _out_T_8091 = out_f_rivalid_822; // @[RegisterRouter.scala:87:24]
wire out_f_roready_822 = out_roready_1_676 & out_romask_822; // @[RegisterRouter.scala:87:24]
wire _out_T_8092 = out_f_roready_822; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_822 = out_wivalid_1_676 & out_wimask_822; // @[RegisterRouter.scala:87:24]
wire out_f_woready_822 = out_woready_1_676 & out_womask_822; // @[RegisterRouter.scala:87:24]
wire _out_T_8093 = ~out_rimask_822; // @[RegisterRouter.scala:87:24]
wire _out_T_8094 = ~out_wimask_822; // @[RegisterRouter.scala:87:24]
wire _out_T_8095 = ~out_romask_822; // @[RegisterRouter.scala:87:24]
wire _out_T_8096 = ~out_womask_822; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_700 = {hi_820, flags_0_go, _out_prepend_T_700}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_8097 = out_prepend_700; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_8098 = _out_T_8097; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_701 = _out_T_8098; // @[RegisterRouter.scala:87:24]
wire out_rimask_823 = |_out_rimask_T_823; // @[RegisterRouter.scala:87:24]
wire out_wimask_823 = &_out_wimask_T_823; // @[RegisterRouter.scala:87:24]
wire out_romask_823 = |_out_romask_T_823; // @[RegisterRouter.scala:87:24]
wire out_womask_823 = &_out_womask_T_823; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_823 = out_rivalid_1_677 & out_rimask_823; // @[RegisterRouter.scala:87:24]
wire _out_T_8100 = out_f_rivalid_823; // @[RegisterRouter.scala:87:24]
wire out_f_roready_823 = out_roready_1_677 & out_romask_823; // @[RegisterRouter.scala:87:24]
wire _out_T_8101 = out_f_roready_823; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_823 = out_wivalid_1_677 & out_wimask_823; // @[RegisterRouter.scala:87:24]
wire out_f_woready_823 = out_woready_1_677 & out_womask_823; // @[RegisterRouter.scala:87:24]
wire _out_T_8102 = ~out_rimask_823; // @[RegisterRouter.scala:87:24]
wire _out_T_8103 = ~out_wimask_823; // @[RegisterRouter.scala:87:24]
wire _out_T_8104 = ~out_romask_823; // @[RegisterRouter.scala:87:24]
wire _out_T_8105 = ~out_womask_823; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_701 = {hi_821, flags_0_go, _out_prepend_T_701}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_8106 = out_prepend_701; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_8107 = _out_T_8106; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_702 = _out_T_8107; // @[RegisterRouter.scala:87:24]
wire out_rimask_824 = |_out_rimask_T_824; // @[RegisterRouter.scala:87:24]
wire out_wimask_824 = &_out_wimask_T_824; // @[RegisterRouter.scala:87:24]
wire out_romask_824 = |_out_romask_T_824; // @[RegisterRouter.scala:87:24]
wire out_womask_824 = &_out_womask_T_824; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_824 = out_rivalid_1_678 & out_rimask_824; // @[RegisterRouter.scala:87:24]
wire _out_T_8109 = out_f_rivalid_824; // @[RegisterRouter.scala:87:24]
wire out_f_roready_824 = out_roready_1_678 & out_romask_824; // @[RegisterRouter.scala:87:24]
wire _out_T_8110 = out_f_roready_824; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_824 = out_wivalid_1_678 & out_wimask_824; // @[RegisterRouter.scala:87:24]
wire out_f_woready_824 = out_woready_1_678 & out_womask_824; // @[RegisterRouter.scala:87:24]
wire _out_T_8111 = ~out_rimask_824; // @[RegisterRouter.scala:87:24]
wire _out_T_8112 = ~out_wimask_824; // @[RegisterRouter.scala:87:24]
wire _out_T_8113 = ~out_romask_824; // @[RegisterRouter.scala:87:24]
wire _out_T_8114 = ~out_womask_824; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_702 = {hi_822, flags_0_go, _out_prepend_T_702}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_8115 = out_prepend_702; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_8116 = _out_T_8115; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_703 = _out_T_8116; // @[RegisterRouter.scala:87:24]
wire out_rimask_825 = |_out_rimask_T_825; // @[RegisterRouter.scala:87:24]
wire out_wimask_825 = &_out_wimask_T_825; // @[RegisterRouter.scala:87:24]
wire out_romask_825 = |_out_romask_T_825; // @[RegisterRouter.scala:87:24]
wire out_womask_825 = &_out_womask_T_825; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_825 = out_rivalid_1_679 & out_rimask_825; // @[RegisterRouter.scala:87:24]
wire _out_T_8118 = out_f_rivalid_825; // @[RegisterRouter.scala:87:24]
wire out_f_roready_825 = out_roready_1_679 & out_romask_825; // @[RegisterRouter.scala:87:24]
wire _out_T_8119 = out_f_roready_825; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_825 = out_wivalid_1_679 & out_wimask_825; // @[RegisterRouter.scala:87:24]
wire out_f_woready_825 = out_woready_1_679 & out_womask_825; // @[RegisterRouter.scala:87:24]
wire _out_T_8120 = ~out_rimask_825; // @[RegisterRouter.scala:87:24]
wire _out_T_8121 = ~out_wimask_825; // @[RegisterRouter.scala:87:24]
wire _out_T_8122 = ~out_romask_825; // @[RegisterRouter.scala:87:24]
wire _out_T_8123 = ~out_womask_825; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_703 = {hi_823, flags_0_go, _out_prepend_T_703}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_8124 = out_prepend_703; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_8125 = _out_T_8124; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_704 = _out_T_8125; // @[RegisterRouter.scala:87:24]
wire out_rimask_826 = |_out_rimask_T_826; // @[RegisterRouter.scala:87:24]
wire out_wimask_826 = &_out_wimask_T_826; // @[RegisterRouter.scala:87:24]
wire out_romask_826 = |_out_romask_T_826; // @[RegisterRouter.scala:87:24]
wire out_womask_826 = &_out_womask_T_826; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_826 = out_rivalid_1_680 & out_rimask_826; // @[RegisterRouter.scala:87:24]
wire _out_T_8127 = out_f_rivalid_826; // @[RegisterRouter.scala:87:24]
wire out_f_roready_826 = out_roready_1_680 & out_romask_826; // @[RegisterRouter.scala:87:24]
wire _out_T_8128 = out_f_roready_826; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_826 = out_wivalid_1_680 & out_wimask_826; // @[RegisterRouter.scala:87:24]
wire out_f_woready_826 = out_woready_1_680 & out_womask_826; // @[RegisterRouter.scala:87:24]
wire _out_T_8129 = ~out_rimask_826; // @[RegisterRouter.scala:87:24]
wire _out_T_8130 = ~out_wimask_826; // @[RegisterRouter.scala:87:24]
wire _out_T_8131 = ~out_romask_826; // @[RegisterRouter.scala:87:24]
wire _out_T_8132 = ~out_womask_826; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_704 = {hi_824, flags_0_go, _out_prepend_T_704}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_8133 = out_prepend_704; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_8134 = _out_T_8133; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_230 = _out_T_8134; // @[MuxLiteral.scala:49:48]
wire out_rimask_827 = |_out_rimask_T_827; // @[RegisterRouter.scala:87:24]
wire out_wimask_827 = &_out_wimask_T_827; // @[RegisterRouter.scala:87:24]
wire out_romask_827 = |_out_romask_T_827; // @[RegisterRouter.scala:87:24]
wire out_womask_827 = &_out_womask_T_827; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_827 = out_rivalid_1_681 & out_rimask_827; // @[RegisterRouter.scala:87:24]
wire _out_T_8136 = out_f_rivalid_827; // @[RegisterRouter.scala:87:24]
wire out_f_roready_827 = out_roready_1_681 & out_romask_827; // @[RegisterRouter.scala:87:24]
wire _out_T_8137 = out_f_roready_827; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_827 = out_wivalid_1_681 & out_wimask_827; // @[RegisterRouter.scala:87:24]
wire out_f_woready_827 = out_woready_1_681 & out_womask_827; // @[RegisterRouter.scala:87:24]
wire _out_T_8138 = ~out_rimask_827; // @[RegisterRouter.scala:87:24]
wire _out_T_8139 = ~out_wimask_827; // @[RegisterRouter.scala:87:24]
wire _out_T_8140 = ~out_romask_827; // @[RegisterRouter.scala:87:24]
wire _out_T_8141 = ~out_womask_827; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8143 = _out_T_8142; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_705 = _out_T_8143; // @[RegisterRouter.scala:87:24]
wire out_rimask_828 = |_out_rimask_T_828; // @[RegisterRouter.scala:87:24]
wire out_wimask_828 = &_out_wimask_T_828; // @[RegisterRouter.scala:87:24]
wire out_romask_828 = |_out_romask_T_828; // @[RegisterRouter.scala:87:24]
wire out_womask_828 = &_out_womask_T_828; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_828 = out_rivalid_1_682 & out_rimask_828; // @[RegisterRouter.scala:87:24]
wire _out_T_8145 = out_f_rivalid_828; // @[RegisterRouter.scala:87:24]
wire out_f_roready_828 = out_roready_1_682 & out_romask_828; // @[RegisterRouter.scala:87:24]
wire _out_T_8146 = out_f_roready_828; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_828 = out_wivalid_1_682 & out_wimask_828; // @[RegisterRouter.scala:87:24]
wire out_f_woready_828 = out_woready_1_682 & out_womask_828; // @[RegisterRouter.scala:87:24]
wire _out_T_8147 = ~out_rimask_828; // @[RegisterRouter.scala:87:24]
wire _out_T_8148 = ~out_wimask_828; // @[RegisterRouter.scala:87:24]
wire _out_T_8149 = ~out_romask_828; // @[RegisterRouter.scala:87:24]
wire _out_T_8150 = ~out_womask_828; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_705 = {hi_938, flags_0_go, _out_prepend_T_705}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_8151 = out_prepend_705; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_8152 = _out_T_8151; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_706 = _out_T_8152; // @[RegisterRouter.scala:87:24]
wire out_rimask_829 = |_out_rimask_T_829; // @[RegisterRouter.scala:87:24]
wire out_wimask_829 = &_out_wimask_T_829; // @[RegisterRouter.scala:87:24]
wire out_romask_829 = |_out_romask_T_829; // @[RegisterRouter.scala:87:24]
wire out_womask_829 = &_out_womask_T_829; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_829 = out_rivalid_1_683 & out_rimask_829; // @[RegisterRouter.scala:87:24]
wire _out_T_8154 = out_f_rivalid_829; // @[RegisterRouter.scala:87:24]
wire out_f_roready_829 = out_roready_1_683 & out_romask_829; // @[RegisterRouter.scala:87:24]
wire _out_T_8155 = out_f_roready_829; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_829 = out_wivalid_1_683 & out_wimask_829; // @[RegisterRouter.scala:87:24]
wire out_f_woready_829 = out_woready_1_683 & out_womask_829; // @[RegisterRouter.scala:87:24]
wire _out_T_8156 = ~out_rimask_829; // @[RegisterRouter.scala:87:24]
wire _out_T_8157 = ~out_wimask_829; // @[RegisterRouter.scala:87:24]
wire _out_T_8158 = ~out_romask_829; // @[RegisterRouter.scala:87:24]
wire _out_T_8159 = ~out_womask_829; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_706 = {hi_939, flags_0_go, _out_prepend_T_706}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_8160 = out_prepend_706; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_8161 = _out_T_8160; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_707 = _out_T_8161; // @[RegisterRouter.scala:87:24]
wire out_rimask_830 = |_out_rimask_T_830; // @[RegisterRouter.scala:87:24]
wire out_wimask_830 = &_out_wimask_T_830; // @[RegisterRouter.scala:87:24]
wire out_romask_830 = |_out_romask_T_830; // @[RegisterRouter.scala:87:24]
wire out_womask_830 = &_out_womask_T_830; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_830 = out_rivalid_1_684 & out_rimask_830; // @[RegisterRouter.scala:87:24]
wire _out_T_8163 = out_f_rivalid_830; // @[RegisterRouter.scala:87:24]
wire out_f_roready_830 = out_roready_1_684 & out_romask_830; // @[RegisterRouter.scala:87:24]
wire _out_T_8164 = out_f_roready_830; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_830 = out_wivalid_1_684 & out_wimask_830; // @[RegisterRouter.scala:87:24]
wire out_f_woready_830 = out_woready_1_684 & out_womask_830; // @[RegisterRouter.scala:87:24]
wire _out_T_8165 = ~out_rimask_830; // @[RegisterRouter.scala:87:24]
wire _out_T_8166 = ~out_wimask_830; // @[RegisterRouter.scala:87:24]
wire _out_T_8167 = ~out_romask_830; // @[RegisterRouter.scala:87:24]
wire _out_T_8168 = ~out_womask_830; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_707 = {hi_940, flags_0_go, _out_prepend_T_707}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_8169 = out_prepend_707; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_8170 = _out_T_8169; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_708 = _out_T_8170; // @[RegisterRouter.scala:87:24]
wire out_rimask_831 = |_out_rimask_T_831; // @[RegisterRouter.scala:87:24]
wire out_wimask_831 = &_out_wimask_T_831; // @[RegisterRouter.scala:87:24]
wire out_romask_831 = |_out_romask_T_831; // @[RegisterRouter.scala:87:24]
wire out_womask_831 = &_out_womask_T_831; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_831 = out_rivalid_1_685 & out_rimask_831; // @[RegisterRouter.scala:87:24]
wire _out_T_8172 = out_f_rivalid_831; // @[RegisterRouter.scala:87:24]
wire out_f_roready_831 = out_roready_1_685 & out_romask_831; // @[RegisterRouter.scala:87:24]
wire _out_T_8173 = out_f_roready_831; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_831 = out_wivalid_1_685 & out_wimask_831; // @[RegisterRouter.scala:87:24]
wire out_f_woready_831 = out_woready_1_685 & out_womask_831; // @[RegisterRouter.scala:87:24]
wire _out_T_8174 = ~out_rimask_831; // @[RegisterRouter.scala:87:24]
wire _out_T_8175 = ~out_wimask_831; // @[RegisterRouter.scala:87:24]
wire _out_T_8176 = ~out_romask_831; // @[RegisterRouter.scala:87:24]
wire _out_T_8177 = ~out_womask_831; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_708 = {hi_941, flags_0_go, _out_prepend_T_708}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_8178 = out_prepend_708; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_8179 = _out_T_8178; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_709 = _out_T_8179; // @[RegisterRouter.scala:87:24]
wire out_rimask_832 = |_out_rimask_T_832; // @[RegisterRouter.scala:87:24]
wire out_wimask_832 = &_out_wimask_T_832; // @[RegisterRouter.scala:87:24]
wire out_romask_832 = |_out_romask_T_832; // @[RegisterRouter.scala:87:24]
wire out_womask_832 = &_out_womask_T_832; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_832 = out_rivalid_1_686 & out_rimask_832; // @[RegisterRouter.scala:87:24]
wire _out_T_8181 = out_f_rivalid_832; // @[RegisterRouter.scala:87:24]
wire out_f_roready_832 = out_roready_1_686 & out_romask_832; // @[RegisterRouter.scala:87:24]
wire _out_T_8182 = out_f_roready_832; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_832 = out_wivalid_1_686 & out_wimask_832; // @[RegisterRouter.scala:87:24]
wire out_f_woready_832 = out_woready_1_686 & out_womask_832; // @[RegisterRouter.scala:87:24]
wire _out_T_8183 = ~out_rimask_832; // @[RegisterRouter.scala:87:24]
wire _out_T_8184 = ~out_wimask_832; // @[RegisterRouter.scala:87:24]
wire _out_T_8185 = ~out_romask_832; // @[RegisterRouter.scala:87:24]
wire _out_T_8186 = ~out_womask_832; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_709 = {hi_942, flags_0_go, _out_prepend_T_709}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_8187 = out_prepend_709; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_8188 = _out_T_8187; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_710 = _out_T_8188; // @[RegisterRouter.scala:87:24]
wire out_rimask_833 = |_out_rimask_T_833; // @[RegisterRouter.scala:87:24]
wire out_wimask_833 = &_out_wimask_T_833; // @[RegisterRouter.scala:87:24]
wire out_romask_833 = |_out_romask_T_833; // @[RegisterRouter.scala:87:24]
wire out_womask_833 = &_out_womask_T_833; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_833 = out_rivalid_1_687 & out_rimask_833; // @[RegisterRouter.scala:87:24]
wire _out_T_8190 = out_f_rivalid_833; // @[RegisterRouter.scala:87:24]
wire out_f_roready_833 = out_roready_1_687 & out_romask_833; // @[RegisterRouter.scala:87:24]
wire _out_T_8191 = out_f_roready_833; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_833 = out_wivalid_1_687 & out_wimask_833; // @[RegisterRouter.scala:87:24]
wire out_f_woready_833 = out_woready_1_687 & out_womask_833; // @[RegisterRouter.scala:87:24]
wire _out_T_8192 = ~out_rimask_833; // @[RegisterRouter.scala:87:24]
wire _out_T_8193 = ~out_wimask_833; // @[RegisterRouter.scala:87:24]
wire _out_T_8194 = ~out_romask_833; // @[RegisterRouter.scala:87:24]
wire _out_T_8195 = ~out_womask_833; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_710 = {hi_943, flags_0_go, _out_prepend_T_710}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_8196 = out_prepend_710; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_8197 = _out_T_8196; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_711 = _out_T_8197; // @[RegisterRouter.scala:87:24]
wire out_rimask_834 = |_out_rimask_T_834; // @[RegisterRouter.scala:87:24]
wire out_wimask_834 = &_out_wimask_T_834; // @[RegisterRouter.scala:87:24]
wire out_romask_834 = |_out_romask_T_834; // @[RegisterRouter.scala:87:24]
wire out_womask_834 = &_out_womask_T_834; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_834 = out_rivalid_1_688 & out_rimask_834; // @[RegisterRouter.scala:87:24]
wire _out_T_8199 = out_f_rivalid_834; // @[RegisterRouter.scala:87:24]
wire out_f_roready_834 = out_roready_1_688 & out_romask_834; // @[RegisterRouter.scala:87:24]
wire _out_T_8200 = out_f_roready_834; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_834 = out_wivalid_1_688 & out_wimask_834; // @[RegisterRouter.scala:87:24]
wire out_f_woready_834 = out_woready_1_688 & out_womask_834; // @[RegisterRouter.scala:87:24]
wire _out_T_8201 = ~out_rimask_834; // @[RegisterRouter.scala:87:24]
wire _out_T_8202 = ~out_wimask_834; // @[RegisterRouter.scala:87:24]
wire _out_T_8203 = ~out_romask_834; // @[RegisterRouter.scala:87:24]
wire _out_T_8204 = ~out_womask_834; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_711 = {hi_944, flags_0_go, _out_prepend_T_711}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_8205 = out_prepend_711; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_8206 = _out_T_8205; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_245 = _out_T_8206; // @[MuxLiteral.scala:49:48]
wire out_rimask_835 = |_out_rimask_T_835; // @[RegisterRouter.scala:87:24]
wire out_wimask_835 = &_out_wimask_T_835; // @[RegisterRouter.scala:87:24]
wire out_romask_835 = |_out_romask_T_835; // @[RegisterRouter.scala:87:24]
wire out_womask_835 = &_out_womask_T_835; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_835 = out_rivalid_1_689 & out_rimask_835; // @[RegisterRouter.scala:87:24]
wire _out_T_8208 = out_f_rivalid_835; // @[RegisterRouter.scala:87:24]
wire out_f_roready_835 = out_roready_1_689 & out_romask_835; // @[RegisterRouter.scala:87:24]
wire _out_T_8209 = out_f_roready_835; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_835 = out_wivalid_1_689 & out_wimask_835; // @[RegisterRouter.scala:87:24]
wire out_f_woready_835 = out_woready_1_689 & out_womask_835; // @[RegisterRouter.scala:87:24]
wire _out_T_8210 = ~out_rimask_835; // @[RegisterRouter.scala:87:24]
wire _out_T_8211 = ~out_wimask_835; // @[RegisterRouter.scala:87:24]
wire _out_T_8212 = ~out_romask_835; // @[RegisterRouter.scala:87:24]
wire _out_T_8213 = ~out_womask_835; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8215 = _out_T_8214; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_712 = _out_T_8215; // @[RegisterRouter.scala:87:24]
wire out_rimask_836 = |_out_rimask_T_836; // @[RegisterRouter.scala:87:24]
wire out_wimask_836 = &_out_wimask_T_836; // @[RegisterRouter.scala:87:24]
wire out_romask_836 = |_out_romask_T_836; // @[RegisterRouter.scala:87:24]
wire out_womask_836 = &_out_womask_T_836; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_836 = out_rivalid_1_690 & out_rimask_836; // @[RegisterRouter.scala:87:24]
wire _out_T_8217 = out_f_rivalid_836; // @[RegisterRouter.scala:87:24]
wire out_f_roready_836 = out_roready_1_690 & out_romask_836; // @[RegisterRouter.scala:87:24]
wire _out_T_8218 = out_f_roready_836; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_836 = out_wivalid_1_690 & out_wimask_836; // @[RegisterRouter.scala:87:24]
wire out_f_woready_836 = out_woready_1_690 & out_womask_836; // @[RegisterRouter.scala:87:24]
wire _out_T_8219 = ~out_rimask_836; // @[RegisterRouter.scala:87:24]
wire _out_T_8220 = ~out_wimask_836; // @[RegisterRouter.scala:87:24]
wire _out_T_8221 = ~out_romask_836; // @[RegisterRouter.scala:87:24]
wire _out_T_8222 = ~out_womask_836; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_712 = {hi_642, flags_0_go, _out_prepend_T_712}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_8223 = out_prepend_712; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_8224 = _out_T_8223; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_713 = _out_T_8224; // @[RegisterRouter.scala:87:24]
wire out_rimask_837 = |_out_rimask_T_837; // @[RegisterRouter.scala:87:24]
wire out_wimask_837 = &_out_wimask_T_837; // @[RegisterRouter.scala:87:24]
wire out_romask_837 = |_out_romask_T_837; // @[RegisterRouter.scala:87:24]
wire out_womask_837 = &_out_womask_T_837; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_837 = out_rivalid_1_691 & out_rimask_837; // @[RegisterRouter.scala:87:24]
wire _out_T_8226 = out_f_rivalid_837; // @[RegisterRouter.scala:87:24]
wire out_f_roready_837 = out_roready_1_691 & out_romask_837; // @[RegisterRouter.scala:87:24]
wire _out_T_8227 = out_f_roready_837; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_837 = out_wivalid_1_691 & out_wimask_837; // @[RegisterRouter.scala:87:24]
wire out_f_woready_837 = out_woready_1_691 & out_womask_837; // @[RegisterRouter.scala:87:24]
wire _out_T_8228 = ~out_rimask_837; // @[RegisterRouter.scala:87:24]
wire _out_T_8229 = ~out_wimask_837; // @[RegisterRouter.scala:87:24]
wire _out_T_8230 = ~out_romask_837; // @[RegisterRouter.scala:87:24]
wire _out_T_8231 = ~out_womask_837; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_713 = {hi_643, flags_0_go, _out_prepend_T_713}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_8232 = out_prepend_713; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_8233 = _out_T_8232; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_714 = _out_T_8233; // @[RegisterRouter.scala:87:24]
wire out_rimask_838 = |_out_rimask_T_838; // @[RegisterRouter.scala:87:24]
wire out_wimask_838 = &_out_wimask_T_838; // @[RegisterRouter.scala:87:24]
wire out_romask_838 = |_out_romask_T_838; // @[RegisterRouter.scala:87:24]
wire out_womask_838 = &_out_womask_T_838; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_838 = out_rivalid_1_692 & out_rimask_838; // @[RegisterRouter.scala:87:24]
wire _out_T_8235 = out_f_rivalid_838; // @[RegisterRouter.scala:87:24]
wire out_f_roready_838 = out_roready_1_692 & out_romask_838; // @[RegisterRouter.scala:87:24]
wire _out_T_8236 = out_f_roready_838; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_838 = out_wivalid_1_692 & out_wimask_838; // @[RegisterRouter.scala:87:24]
wire out_f_woready_838 = out_woready_1_692 & out_womask_838; // @[RegisterRouter.scala:87:24]
wire _out_T_8237 = ~out_rimask_838; // @[RegisterRouter.scala:87:24]
wire _out_T_8238 = ~out_wimask_838; // @[RegisterRouter.scala:87:24]
wire _out_T_8239 = ~out_romask_838; // @[RegisterRouter.scala:87:24]
wire _out_T_8240 = ~out_womask_838; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_714 = {hi_644, flags_0_go, _out_prepend_T_714}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_8241 = out_prepend_714; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_8242 = _out_T_8241; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_715 = _out_T_8242; // @[RegisterRouter.scala:87:24]
wire out_rimask_839 = |_out_rimask_T_839; // @[RegisterRouter.scala:87:24]
wire out_wimask_839 = &_out_wimask_T_839; // @[RegisterRouter.scala:87:24]
wire out_romask_839 = |_out_romask_T_839; // @[RegisterRouter.scala:87:24]
wire out_womask_839 = &_out_womask_T_839; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_839 = out_rivalid_1_693 & out_rimask_839; // @[RegisterRouter.scala:87:24]
wire _out_T_8244 = out_f_rivalid_839; // @[RegisterRouter.scala:87:24]
wire out_f_roready_839 = out_roready_1_693 & out_romask_839; // @[RegisterRouter.scala:87:24]
wire _out_T_8245 = out_f_roready_839; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_839 = out_wivalid_1_693 & out_wimask_839; // @[RegisterRouter.scala:87:24]
wire out_f_woready_839 = out_woready_1_693 & out_womask_839; // @[RegisterRouter.scala:87:24]
wire _out_T_8246 = ~out_rimask_839; // @[RegisterRouter.scala:87:24]
wire _out_T_8247 = ~out_wimask_839; // @[RegisterRouter.scala:87:24]
wire _out_T_8248 = ~out_romask_839; // @[RegisterRouter.scala:87:24]
wire _out_T_8249 = ~out_womask_839; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_715 = {hi_645, flags_0_go, _out_prepend_T_715}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_8250 = out_prepend_715; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_8251 = _out_T_8250; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_716 = _out_T_8251; // @[RegisterRouter.scala:87:24]
wire out_rimask_840 = |_out_rimask_T_840; // @[RegisterRouter.scala:87:24]
wire out_wimask_840 = &_out_wimask_T_840; // @[RegisterRouter.scala:87:24]
wire out_romask_840 = |_out_romask_T_840; // @[RegisterRouter.scala:87:24]
wire out_womask_840 = &_out_womask_T_840; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_840 = out_rivalid_1_694 & out_rimask_840; // @[RegisterRouter.scala:87:24]
wire _out_T_8253 = out_f_rivalid_840; // @[RegisterRouter.scala:87:24]
wire out_f_roready_840 = out_roready_1_694 & out_romask_840; // @[RegisterRouter.scala:87:24]
wire _out_T_8254 = out_f_roready_840; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_840 = out_wivalid_1_694 & out_wimask_840; // @[RegisterRouter.scala:87:24]
wire out_f_woready_840 = out_woready_1_694 & out_womask_840; // @[RegisterRouter.scala:87:24]
wire _out_T_8255 = ~out_rimask_840; // @[RegisterRouter.scala:87:24]
wire _out_T_8256 = ~out_wimask_840; // @[RegisterRouter.scala:87:24]
wire _out_T_8257 = ~out_romask_840; // @[RegisterRouter.scala:87:24]
wire _out_T_8258 = ~out_womask_840; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_716 = {hi_646, flags_0_go, _out_prepend_T_716}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_8259 = out_prepend_716; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_8260 = _out_T_8259; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_717 = _out_T_8260; // @[RegisterRouter.scala:87:24]
wire out_rimask_841 = |_out_rimask_T_841; // @[RegisterRouter.scala:87:24]
wire out_wimask_841 = &_out_wimask_T_841; // @[RegisterRouter.scala:87:24]
wire out_romask_841 = |_out_romask_T_841; // @[RegisterRouter.scala:87:24]
wire out_womask_841 = &_out_womask_T_841; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_841 = out_rivalid_1_695 & out_rimask_841; // @[RegisterRouter.scala:87:24]
wire _out_T_8262 = out_f_rivalid_841; // @[RegisterRouter.scala:87:24]
wire out_f_roready_841 = out_roready_1_695 & out_romask_841; // @[RegisterRouter.scala:87:24]
wire _out_T_8263 = out_f_roready_841; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_841 = out_wivalid_1_695 & out_wimask_841; // @[RegisterRouter.scala:87:24]
wire out_f_woready_841 = out_woready_1_695 & out_womask_841; // @[RegisterRouter.scala:87:24]
wire _out_T_8264 = ~out_rimask_841; // @[RegisterRouter.scala:87:24]
wire _out_T_8265 = ~out_wimask_841; // @[RegisterRouter.scala:87:24]
wire _out_T_8266 = ~out_romask_841; // @[RegisterRouter.scala:87:24]
wire _out_T_8267 = ~out_womask_841; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_717 = {hi_647, flags_0_go, _out_prepend_T_717}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_8268 = out_prepend_717; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_8269 = _out_T_8268; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_718 = _out_T_8269; // @[RegisterRouter.scala:87:24]
wire out_rimask_842 = |_out_rimask_T_842; // @[RegisterRouter.scala:87:24]
wire out_wimask_842 = &_out_wimask_T_842; // @[RegisterRouter.scala:87:24]
wire out_romask_842 = |_out_romask_T_842; // @[RegisterRouter.scala:87:24]
wire out_womask_842 = &_out_womask_T_842; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_842 = out_rivalid_1_696 & out_rimask_842; // @[RegisterRouter.scala:87:24]
wire _out_T_8271 = out_f_rivalid_842; // @[RegisterRouter.scala:87:24]
wire out_f_roready_842 = out_roready_1_696 & out_romask_842; // @[RegisterRouter.scala:87:24]
wire _out_T_8272 = out_f_roready_842; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_842 = out_wivalid_1_696 & out_wimask_842; // @[RegisterRouter.scala:87:24]
wire out_f_woready_842 = out_woready_1_696 & out_womask_842; // @[RegisterRouter.scala:87:24]
wire _out_T_8273 = ~out_rimask_842; // @[RegisterRouter.scala:87:24]
wire _out_T_8274 = ~out_wimask_842; // @[RegisterRouter.scala:87:24]
wire _out_T_8275 = ~out_romask_842; // @[RegisterRouter.scala:87:24]
wire _out_T_8276 = ~out_womask_842; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_718 = {hi_648, flags_0_go, _out_prepend_T_718}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_8277 = out_prepend_718; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_8278 = _out_T_8277; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_208 = _out_T_8278; // @[MuxLiteral.scala:49:48]
wire out_rimask_843 = |_out_rimask_T_843; // @[RegisterRouter.scala:87:24]
wire out_wimask_843 = &_out_wimask_T_843; // @[RegisterRouter.scala:87:24]
wire out_romask_843 = |_out_romask_T_843; // @[RegisterRouter.scala:87:24]
wire out_womask_843 = &_out_womask_T_843; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_843 = out_rivalid_1_697 & out_rimask_843; // @[RegisterRouter.scala:87:24]
wire _out_T_8280 = out_f_rivalid_843; // @[RegisterRouter.scala:87:24]
wire out_f_roready_843 = out_roready_1_697 & out_romask_843; // @[RegisterRouter.scala:87:24]
wire _out_T_8281 = out_f_roready_843; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_843 = out_wivalid_1_697 & out_wimask_843; // @[RegisterRouter.scala:87:24]
wire out_f_woready_843 = out_woready_1_697 & out_womask_843; // @[RegisterRouter.scala:87:24]
wire _out_T_8282 = ~out_rimask_843; // @[RegisterRouter.scala:87:24]
wire _out_T_8283 = ~out_wimask_843; // @[RegisterRouter.scala:87:24]
wire _out_T_8284 = ~out_romask_843; // @[RegisterRouter.scala:87:24]
wire _out_T_8285 = ~out_womask_843; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_8287 = _out_T_8286; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_719 = _out_T_8287; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_rimask_T_844 = out_frontMask_1[63:32]; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_wimask_T_844 = out_frontMask_1[63:32]; // @[RegisterRouter.scala:87:24]
wire out_rimask_844 = |_out_rimask_T_844; // @[RegisterRouter.scala:87:24]
wire out_wimask_844 = &_out_wimask_T_844; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_romask_T_844 = out_backMask_1[63:32]; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_womask_T_844 = out_backMask_1[63:32]; // @[RegisterRouter.scala:87:24]
wire out_romask_844 = |_out_romask_T_844; // @[RegisterRouter.scala:87:24]
wire out_womask_844 = &_out_womask_T_844; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_844 = out_rivalid_1_698 & out_rimask_844; // @[RegisterRouter.scala:87:24]
wire _out_T_8289 = out_f_rivalid_844; // @[RegisterRouter.scala:87:24]
wire out_f_roready_844 = out_roready_1_698 & out_romask_844; // @[RegisterRouter.scala:87:24]
wire _out_T_8290 = out_f_roready_844; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_844 = out_wivalid_1_698 & out_wimask_844; // @[RegisterRouter.scala:87:24]
wire out_f_woready_844 = out_woready_1_698 & out_womask_844; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_8288 = out_front_1_bits_data[63:32]; // @[RegisterRouter.scala:87:24]
wire _out_T_8291 = ~out_rimask_844; // @[RegisterRouter.scala:87:24]
wire _out_T_8292 = ~out_wimask_844; // @[RegisterRouter.scala:87:24]
wire _out_T_8293 = ~out_romask_844; // @[RegisterRouter.scala:87:24]
wire _out_T_8294 = ~out_womask_844; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_719 = {abstractGeneratedMem_1, _out_prepend_T_719}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_8295 = out_prepend_719; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_8296 = _out_T_8295; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_103 = _out_T_8296; // @[MuxLiteral.scala:49:48]
wire out_rimask_845 = |_out_rimask_T_845; // @[RegisterRouter.scala:87:24]
wire out_wimask_845 = &_out_wimask_T_845; // @[RegisterRouter.scala:87:24]
wire out_romask_845 = |_out_romask_T_845; // @[RegisterRouter.scala:87:24]
wire out_womask_845 = &_out_womask_T_845; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_845 = out_rivalid_1_699 & out_rimask_845; // @[RegisterRouter.scala:87:24]
wire _out_T_8298 = out_f_rivalid_845; // @[RegisterRouter.scala:87:24]
wire out_f_roready_845 = out_roready_1_699 & out_romask_845; // @[RegisterRouter.scala:87:24]
wire _out_T_8299 = out_f_roready_845; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_845 = out_wivalid_1_699 & out_wimask_845; // @[RegisterRouter.scala:87:24]
wire out_f_woready_845 = out_woready_1_699 & out_womask_845; // @[RegisterRouter.scala:87:24]
wire _out_T_8300 = ~out_rimask_845; // @[RegisterRouter.scala:87:24]
wire _out_T_8301 = ~out_wimask_845; // @[RegisterRouter.scala:87:24]
wire _out_T_8302 = ~out_romask_845; // @[RegisterRouter.scala:87:24]
wire _out_T_8303 = ~out_womask_845; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8305 = _out_T_8304; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_720 = _out_T_8305; // @[RegisterRouter.scala:87:24]
wire out_rimask_846 = |_out_rimask_T_846; // @[RegisterRouter.scala:87:24]
wire out_wimask_846 = &_out_wimask_T_846; // @[RegisterRouter.scala:87:24]
wire out_romask_846 = |_out_romask_T_846; // @[RegisterRouter.scala:87:24]
wire out_womask_846 = &_out_womask_T_846; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_846 = out_rivalid_1_700 & out_rimask_846; // @[RegisterRouter.scala:87:24]
wire _out_T_8307 = out_f_rivalid_846; // @[RegisterRouter.scala:87:24]
wire out_f_roready_846 = out_roready_1_700 & out_romask_846; // @[RegisterRouter.scala:87:24]
wire _out_T_8308 = out_f_roready_846; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_846 = out_wivalid_1_700 & out_wimask_846; // @[RegisterRouter.scala:87:24]
wire out_f_woready_846 = out_woready_1_700 & out_womask_846; // @[RegisterRouter.scala:87:24]
wire _out_T_8309 = ~out_rimask_846; // @[RegisterRouter.scala:87:24]
wire _out_T_8310 = ~out_wimask_846; // @[RegisterRouter.scala:87:24]
wire _out_T_8311 = ~out_romask_846; // @[RegisterRouter.scala:87:24]
wire _out_T_8312 = ~out_womask_846; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_720 = {hi_98, flags_0_go, _out_prepend_T_720}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_8313 = out_prepend_720; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_8314 = _out_T_8313; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_721 = _out_T_8314; // @[RegisterRouter.scala:87:24]
wire out_rimask_847 = |_out_rimask_T_847; // @[RegisterRouter.scala:87:24]
wire out_wimask_847 = &_out_wimask_T_847; // @[RegisterRouter.scala:87:24]
wire out_romask_847 = |_out_romask_T_847; // @[RegisterRouter.scala:87:24]
wire out_womask_847 = &_out_womask_T_847; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_847 = out_rivalid_1_701 & out_rimask_847; // @[RegisterRouter.scala:87:24]
wire _out_T_8316 = out_f_rivalid_847; // @[RegisterRouter.scala:87:24]
wire out_f_roready_847 = out_roready_1_701 & out_romask_847; // @[RegisterRouter.scala:87:24]
wire _out_T_8317 = out_f_roready_847; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_847 = out_wivalid_1_701 & out_wimask_847; // @[RegisterRouter.scala:87:24]
wire out_f_woready_847 = out_woready_1_701 & out_womask_847; // @[RegisterRouter.scala:87:24]
wire _out_T_8318 = ~out_rimask_847; // @[RegisterRouter.scala:87:24]
wire _out_T_8319 = ~out_wimask_847; // @[RegisterRouter.scala:87:24]
wire _out_T_8320 = ~out_romask_847; // @[RegisterRouter.scala:87:24]
wire _out_T_8321 = ~out_womask_847; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_721 = {hi_99, flags_0_go, _out_prepend_T_721}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_8322 = out_prepend_721; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_8323 = _out_T_8322; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_722 = _out_T_8323; // @[RegisterRouter.scala:87:24]
wire out_rimask_848 = |_out_rimask_T_848; // @[RegisterRouter.scala:87:24]
wire out_wimask_848 = &_out_wimask_T_848; // @[RegisterRouter.scala:87:24]
wire out_romask_848 = |_out_romask_T_848; // @[RegisterRouter.scala:87:24]
wire out_womask_848 = &_out_womask_T_848; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_848 = out_rivalid_1_702 & out_rimask_848; // @[RegisterRouter.scala:87:24]
wire _out_T_8325 = out_f_rivalid_848; // @[RegisterRouter.scala:87:24]
wire out_f_roready_848 = out_roready_1_702 & out_romask_848; // @[RegisterRouter.scala:87:24]
wire _out_T_8326 = out_f_roready_848; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_848 = out_wivalid_1_702 & out_wimask_848; // @[RegisterRouter.scala:87:24]
wire out_f_woready_848 = out_woready_1_702 & out_womask_848; // @[RegisterRouter.scala:87:24]
wire _out_T_8327 = ~out_rimask_848; // @[RegisterRouter.scala:87:24]
wire _out_T_8328 = ~out_wimask_848; // @[RegisterRouter.scala:87:24]
wire _out_T_8329 = ~out_romask_848; // @[RegisterRouter.scala:87:24]
wire _out_T_8330 = ~out_womask_848; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_722 = {hi_100, flags_0_go, _out_prepend_T_722}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_8331 = out_prepend_722; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_8332 = _out_T_8331; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_723 = _out_T_8332; // @[RegisterRouter.scala:87:24]
wire out_rimask_849 = |_out_rimask_T_849; // @[RegisterRouter.scala:87:24]
wire out_wimask_849 = &_out_wimask_T_849; // @[RegisterRouter.scala:87:24]
wire out_romask_849 = |_out_romask_T_849; // @[RegisterRouter.scala:87:24]
wire out_womask_849 = &_out_womask_T_849; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_849 = out_rivalid_1_703 & out_rimask_849; // @[RegisterRouter.scala:87:24]
wire _out_T_8334 = out_f_rivalid_849; // @[RegisterRouter.scala:87:24]
wire out_f_roready_849 = out_roready_1_703 & out_romask_849; // @[RegisterRouter.scala:87:24]
wire _out_T_8335 = out_f_roready_849; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_849 = out_wivalid_1_703 & out_wimask_849; // @[RegisterRouter.scala:87:24]
wire out_f_woready_849 = out_woready_1_703 & out_womask_849; // @[RegisterRouter.scala:87:24]
wire _out_T_8336 = ~out_rimask_849; // @[RegisterRouter.scala:87:24]
wire _out_T_8337 = ~out_wimask_849; // @[RegisterRouter.scala:87:24]
wire _out_T_8338 = ~out_romask_849; // @[RegisterRouter.scala:87:24]
wire _out_T_8339 = ~out_womask_849; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_723 = {hi_101, flags_0_go, _out_prepend_T_723}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_8340 = out_prepend_723; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_8341 = _out_T_8340; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_724 = _out_T_8341; // @[RegisterRouter.scala:87:24]
wire out_rimask_850 = |_out_rimask_T_850; // @[RegisterRouter.scala:87:24]
wire out_wimask_850 = &_out_wimask_T_850; // @[RegisterRouter.scala:87:24]
wire out_romask_850 = |_out_romask_T_850; // @[RegisterRouter.scala:87:24]
wire out_womask_850 = &_out_womask_T_850; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_850 = out_rivalid_1_704 & out_rimask_850; // @[RegisterRouter.scala:87:24]
wire _out_T_8343 = out_f_rivalid_850; // @[RegisterRouter.scala:87:24]
wire out_f_roready_850 = out_roready_1_704 & out_romask_850; // @[RegisterRouter.scala:87:24]
wire _out_T_8344 = out_f_roready_850; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_850 = out_wivalid_1_704 & out_wimask_850; // @[RegisterRouter.scala:87:24]
wire out_f_woready_850 = out_woready_1_704 & out_womask_850; // @[RegisterRouter.scala:87:24]
wire _out_T_8345 = ~out_rimask_850; // @[RegisterRouter.scala:87:24]
wire _out_T_8346 = ~out_wimask_850; // @[RegisterRouter.scala:87:24]
wire _out_T_8347 = ~out_romask_850; // @[RegisterRouter.scala:87:24]
wire _out_T_8348 = ~out_womask_850; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_724 = {hi_102, flags_0_go, _out_prepend_T_724}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_8349 = out_prepend_724; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_8350 = _out_T_8349; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_725 = _out_T_8350; // @[RegisterRouter.scala:87:24]
wire out_rimask_851 = |_out_rimask_T_851; // @[RegisterRouter.scala:87:24]
wire out_wimask_851 = &_out_wimask_T_851; // @[RegisterRouter.scala:87:24]
wire out_romask_851 = |_out_romask_T_851; // @[RegisterRouter.scala:87:24]
wire out_womask_851 = &_out_womask_T_851; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_851 = out_rivalid_1_705 & out_rimask_851; // @[RegisterRouter.scala:87:24]
wire _out_T_8352 = out_f_rivalid_851; // @[RegisterRouter.scala:87:24]
wire out_f_roready_851 = out_roready_1_705 & out_romask_851; // @[RegisterRouter.scala:87:24]
wire _out_T_8353 = out_f_roready_851; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_851 = out_wivalid_1_705 & out_wimask_851; // @[RegisterRouter.scala:87:24]
wire out_f_woready_851 = out_woready_1_705 & out_womask_851; // @[RegisterRouter.scala:87:24]
wire _out_T_8354 = ~out_rimask_851; // @[RegisterRouter.scala:87:24]
wire _out_T_8355 = ~out_wimask_851; // @[RegisterRouter.scala:87:24]
wire _out_T_8356 = ~out_romask_851; // @[RegisterRouter.scala:87:24]
wire _out_T_8357 = ~out_womask_851; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_725 = {hi_103, flags_0_go, _out_prepend_T_725}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_8358 = out_prepend_725; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_8359 = _out_T_8358; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_726 = _out_T_8359; // @[RegisterRouter.scala:87:24]
wire out_rimask_852 = |_out_rimask_T_852; // @[RegisterRouter.scala:87:24]
wire out_wimask_852 = &_out_wimask_T_852; // @[RegisterRouter.scala:87:24]
wire out_romask_852 = |_out_romask_T_852; // @[RegisterRouter.scala:87:24]
wire out_womask_852 = &_out_womask_T_852; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_852 = out_rivalid_1_706 & out_rimask_852; // @[RegisterRouter.scala:87:24]
wire _out_T_8361 = out_f_rivalid_852; // @[RegisterRouter.scala:87:24]
wire out_f_roready_852 = out_roready_1_706 & out_romask_852; // @[RegisterRouter.scala:87:24]
wire _out_T_8362 = out_f_roready_852; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_852 = out_wivalid_1_706 & out_wimask_852; // @[RegisterRouter.scala:87:24]
wire out_f_woready_852 = out_woready_1_706 & out_womask_852; // @[RegisterRouter.scala:87:24]
wire _out_T_8363 = ~out_rimask_852; // @[RegisterRouter.scala:87:24]
wire _out_T_8364 = ~out_wimask_852; // @[RegisterRouter.scala:87:24]
wire _out_T_8365 = ~out_romask_852; // @[RegisterRouter.scala:87:24]
wire _out_T_8366 = ~out_womask_852; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_726 = {hi_104, flags_0_go, _out_prepend_T_726}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_8367 = out_prepend_726; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_8368 = _out_T_8367; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_140 = _out_T_8368; // @[MuxLiteral.scala:49:48]
wire out_rimask_853 = |_out_rimask_T_853; // @[RegisterRouter.scala:87:24]
wire out_wimask_853 = &_out_wimask_T_853; // @[RegisterRouter.scala:87:24]
wire out_romask_853 = |_out_romask_T_853; // @[RegisterRouter.scala:87:24]
wire out_womask_853 = &_out_womask_T_853; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_853 = out_rivalid_1_707 & out_rimask_853; // @[RegisterRouter.scala:87:24]
wire _out_T_8370 = out_f_rivalid_853; // @[RegisterRouter.scala:87:24]
wire out_f_roready_853 = out_roready_1_707 & out_romask_853; // @[RegisterRouter.scala:87:24]
wire _out_T_8371 = out_f_roready_853; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_853 = out_wivalid_1_707 & out_wimask_853; // @[RegisterRouter.scala:87:24]
wire out_f_woready_853 = out_woready_1_707 & out_womask_853; // @[RegisterRouter.scala:87:24]
wire _out_T_8372 = ~out_rimask_853; // @[RegisterRouter.scala:87:24]
wire _out_T_8373 = ~out_wimask_853; // @[RegisterRouter.scala:87:24]
wire _out_T_8374 = ~out_romask_853; // @[RegisterRouter.scala:87:24]
wire _out_T_8375 = ~out_womask_853; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8377 = _out_T_8376; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_727 = _out_T_8377; // @[RegisterRouter.scala:87:24]
wire out_rimask_854 = |_out_rimask_T_854; // @[RegisterRouter.scala:87:24]
wire out_wimask_854 = &_out_wimask_T_854; // @[RegisterRouter.scala:87:24]
wire out_romask_854 = |_out_romask_T_854; // @[RegisterRouter.scala:87:24]
wire out_womask_854 = &_out_womask_T_854; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_854 = out_rivalid_1_708 & out_rimask_854; // @[RegisterRouter.scala:87:24]
wire _out_T_8379 = out_f_rivalid_854; // @[RegisterRouter.scala:87:24]
wire out_f_roready_854 = out_roready_1_708 & out_romask_854; // @[RegisterRouter.scala:87:24]
wire _out_T_8380 = out_f_roready_854; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_854 = out_wivalid_1_708 & out_wimask_854; // @[RegisterRouter.scala:87:24]
wire out_f_woready_854 = out_woready_1_708 & out_womask_854; // @[RegisterRouter.scala:87:24]
wire _out_T_8381 = ~out_rimask_854; // @[RegisterRouter.scala:87:24]
wire _out_T_8382 = ~out_wimask_854; // @[RegisterRouter.scala:87:24]
wire _out_T_8383 = ~out_romask_854; // @[RegisterRouter.scala:87:24]
wire _out_T_8384 = ~out_womask_854; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_727 = {hi_682, flags_0_go, _out_prepend_T_727}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_8385 = out_prepend_727; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_8386 = _out_T_8385; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_728 = _out_T_8386; // @[RegisterRouter.scala:87:24]
wire out_rimask_855 = |_out_rimask_T_855; // @[RegisterRouter.scala:87:24]
wire out_wimask_855 = &_out_wimask_T_855; // @[RegisterRouter.scala:87:24]
wire out_romask_855 = |_out_romask_T_855; // @[RegisterRouter.scala:87:24]
wire out_womask_855 = &_out_womask_T_855; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_855 = out_rivalid_1_709 & out_rimask_855; // @[RegisterRouter.scala:87:24]
wire _out_T_8388 = out_f_rivalid_855; // @[RegisterRouter.scala:87:24]
wire out_f_roready_855 = out_roready_1_709 & out_romask_855; // @[RegisterRouter.scala:87:24]
wire _out_T_8389 = out_f_roready_855; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_855 = out_wivalid_1_709 & out_wimask_855; // @[RegisterRouter.scala:87:24]
wire out_f_woready_855 = out_woready_1_709 & out_womask_855; // @[RegisterRouter.scala:87:24]
wire _out_T_8390 = ~out_rimask_855; // @[RegisterRouter.scala:87:24]
wire _out_T_8391 = ~out_wimask_855; // @[RegisterRouter.scala:87:24]
wire _out_T_8392 = ~out_romask_855; // @[RegisterRouter.scala:87:24]
wire _out_T_8393 = ~out_womask_855; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_728 = {hi_683, flags_0_go, _out_prepend_T_728}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_8394 = out_prepend_728; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_8395 = _out_T_8394; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_729 = _out_T_8395; // @[RegisterRouter.scala:87:24]
wire out_rimask_856 = |_out_rimask_T_856; // @[RegisterRouter.scala:87:24]
wire out_wimask_856 = &_out_wimask_T_856; // @[RegisterRouter.scala:87:24]
wire out_romask_856 = |_out_romask_T_856; // @[RegisterRouter.scala:87:24]
wire out_womask_856 = &_out_womask_T_856; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_856 = out_rivalid_1_710 & out_rimask_856; // @[RegisterRouter.scala:87:24]
wire _out_T_8397 = out_f_rivalid_856; // @[RegisterRouter.scala:87:24]
wire out_f_roready_856 = out_roready_1_710 & out_romask_856; // @[RegisterRouter.scala:87:24]
wire _out_T_8398 = out_f_roready_856; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_856 = out_wivalid_1_710 & out_wimask_856; // @[RegisterRouter.scala:87:24]
wire out_f_woready_856 = out_woready_1_710 & out_womask_856; // @[RegisterRouter.scala:87:24]
wire _out_T_8399 = ~out_rimask_856; // @[RegisterRouter.scala:87:24]
wire _out_T_8400 = ~out_wimask_856; // @[RegisterRouter.scala:87:24]
wire _out_T_8401 = ~out_romask_856; // @[RegisterRouter.scala:87:24]
wire _out_T_8402 = ~out_womask_856; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_729 = {hi_684, flags_0_go, _out_prepend_T_729}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_8403 = out_prepend_729; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_8404 = _out_T_8403; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_730 = _out_T_8404; // @[RegisterRouter.scala:87:24]
wire out_rimask_857 = |_out_rimask_T_857; // @[RegisterRouter.scala:87:24]
wire out_wimask_857 = &_out_wimask_T_857; // @[RegisterRouter.scala:87:24]
wire out_romask_857 = |_out_romask_T_857; // @[RegisterRouter.scala:87:24]
wire out_womask_857 = &_out_womask_T_857; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_857 = out_rivalid_1_711 & out_rimask_857; // @[RegisterRouter.scala:87:24]
wire _out_T_8406 = out_f_rivalid_857; // @[RegisterRouter.scala:87:24]
wire out_f_roready_857 = out_roready_1_711 & out_romask_857; // @[RegisterRouter.scala:87:24]
wire _out_T_8407 = out_f_roready_857; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_857 = out_wivalid_1_711 & out_wimask_857; // @[RegisterRouter.scala:87:24]
wire out_f_woready_857 = out_woready_1_711 & out_womask_857; // @[RegisterRouter.scala:87:24]
wire _out_T_8408 = ~out_rimask_857; // @[RegisterRouter.scala:87:24]
wire _out_T_8409 = ~out_wimask_857; // @[RegisterRouter.scala:87:24]
wire _out_T_8410 = ~out_romask_857; // @[RegisterRouter.scala:87:24]
wire _out_T_8411 = ~out_womask_857; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_730 = {hi_685, flags_0_go, _out_prepend_T_730}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_8412 = out_prepend_730; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_8413 = _out_T_8412; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_731 = _out_T_8413; // @[RegisterRouter.scala:87:24]
wire out_rimask_858 = |_out_rimask_T_858; // @[RegisterRouter.scala:87:24]
wire out_wimask_858 = &_out_wimask_T_858; // @[RegisterRouter.scala:87:24]
wire out_romask_858 = |_out_romask_T_858; // @[RegisterRouter.scala:87:24]
wire out_womask_858 = &_out_womask_T_858; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_858 = out_rivalid_1_712 & out_rimask_858; // @[RegisterRouter.scala:87:24]
wire _out_T_8415 = out_f_rivalid_858; // @[RegisterRouter.scala:87:24]
wire out_f_roready_858 = out_roready_1_712 & out_romask_858; // @[RegisterRouter.scala:87:24]
wire _out_T_8416 = out_f_roready_858; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_858 = out_wivalid_1_712 & out_wimask_858; // @[RegisterRouter.scala:87:24]
wire out_f_woready_858 = out_woready_1_712 & out_womask_858; // @[RegisterRouter.scala:87:24]
wire _out_T_8417 = ~out_rimask_858; // @[RegisterRouter.scala:87:24]
wire _out_T_8418 = ~out_wimask_858; // @[RegisterRouter.scala:87:24]
wire _out_T_8419 = ~out_romask_858; // @[RegisterRouter.scala:87:24]
wire _out_T_8420 = ~out_womask_858; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_731 = {hi_686, flags_0_go, _out_prepend_T_731}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_8421 = out_prepend_731; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_8422 = _out_T_8421; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_732 = _out_T_8422; // @[RegisterRouter.scala:87:24]
wire out_rimask_859 = |_out_rimask_T_859; // @[RegisterRouter.scala:87:24]
wire out_wimask_859 = &_out_wimask_T_859; // @[RegisterRouter.scala:87:24]
wire out_romask_859 = |_out_romask_T_859; // @[RegisterRouter.scala:87:24]
wire out_womask_859 = &_out_womask_T_859; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_859 = out_rivalid_1_713 & out_rimask_859; // @[RegisterRouter.scala:87:24]
wire _out_T_8424 = out_f_rivalid_859; // @[RegisterRouter.scala:87:24]
wire out_f_roready_859 = out_roready_1_713 & out_romask_859; // @[RegisterRouter.scala:87:24]
wire _out_T_8425 = out_f_roready_859; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_859 = out_wivalid_1_713 & out_wimask_859; // @[RegisterRouter.scala:87:24]
wire out_f_woready_859 = out_woready_1_713 & out_womask_859; // @[RegisterRouter.scala:87:24]
wire _out_T_8426 = ~out_rimask_859; // @[RegisterRouter.scala:87:24]
wire _out_T_8427 = ~out_wimask_859; // @[RegisterRouter.scala:87:24]
wire _out_T_8428 = ~out_romask_859; // @[RegisterRouter.scala:87:24]
wire _out_T_8429 = ~out_womask_859; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_732 = {hi_687, flags_0_go, _out_prepend_T_732}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_8430 = out_prepend_732; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_8431 = _out_T_8430; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_733 = _out_T_8431; // @[RegisterRouter.scala:87:24]
wire out_rimask_860 = |_out_rimask_T_860; // @[RegisterRouter.scala:87:24]
wire out_wimask_860 = &_out_wimask_T_860; // @[RegisterRouter.scala:87:24]
wire out_romask_860 = |_out_romask_T_860; // @[RegisterRouter.scala:87:24]
wire out_womask_860 = &_out_womask_T_860; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_860 = out_rivalid_1_714 & out_rimask_860; // @[RegisterRouter.scala:87:24]
wire _out_T_8433 = out_f_rivalid_860; // @[RegisterRouter.scala:87:24]
wire out_f_roready_860 = out_roready_1_714 & out_romask_860; // @[RegisterRouter.scala:87:24]
wire _out_T_8434 = out_f_roready_860; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_860 = out_wivalid_1_714 & out_wimask_860; // @[RegisterRouter.scala:87:24]
wire out_f_woready_860 = out_woready_1_714 & out_womask_860; // @[RegisterRouter.scala:87:24]
wire _out_T_8435 = ~out_rimask_860; // @[RegisterRouter.scala:87:24]
wire _out_T_8436 = ~out_wimask_860; // @[RegisterRouter.scala:87:24]
wire _out_T_8437 = ~out_romask_860; // @[RegisterRouter.scala:87:24]
wire _out_T_8438 = ~out_womask_860; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_733 = {hi_688, flags_0_go, _out_prepend_T_733}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_8439 = out_prepend_733; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_8440 = _out_T_8439; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_213 = _out_T_8440; // @[MuxLiteral.scala:49:48]
wire out_rimask_861 = |_out_rimask_T_861; // @[RegisterRouter.scala:87:24]
wire out_wimask_861 = &_out_wimask_T_861; // @[RegisterRouter.scala:87:24]
wire out_romask_861 = |_out_romask_T_861; // @[RegisterRouter.scala:87:24]
wire out_womask_861 = &_out_womask_T_861; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_861 = out_rivalid_1_715 & out_rimask_861; // @[RegisterRouter.scala:87:24]
wire _out_T_8442 = out_f_rivalid_861; // @[RegisterRouter.scala:87:24]
wire out_f_roready_861 = out_roready_1_715 & out_romask_861; // @[RegisterRouter.scala:87:24]
wire _out_T_8443 = out_f_roready_861; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_861 = out_wivalid_1_715 & out_wimask_861; // @[RegisterRouter.scala:87:24]
wire out_f_woready_861 = out_woready_1_715 & out_womask_861; // @[RegisterRouter.scala:87:24]
wire _out_T_8444 = ~out_rimask_861; // @[RegisterRouter.scala:87:24]
wire _out_T_8445 = ~out_wimask_861; // @[RegisterRouter.scala:87:24]
wire _out_T_8446 = ~out_romask_861; // @[RegisterRouter.scala:87:24]
wire _out_T_8447 = ~out_womask_861; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8449 = _out_T_8448; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_734 = _out_T_8449; // @[RegisterRouter.scala:87:24]
wire out_rimask_862 = |_out_rimask_T_862; // @[RegisterRouter.scala:87:24]
wire out_wimask_862 = &_out_wimask_T_862; // @[RegisterRouter.scala:87:24]
wire out_romask_862 = |_out_romask_T_862; // @[RegisterRouter.scala:87:24]
wire out_womask_862 = &_out_womask_T_862; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_862 = out_rivalid_1_716 & out_rimask_862; // @[RegisterRouter.scala:87:24]
wire _out_T_8451 = out_f_rivalid_862; // @[RegisterRouter.scala:87:24]
wire out_f_roready_862 = out_roready_1_716 & out_romask_862; // @[RegisterRouter.scala:87:24]
wire _out_T_8452 = out_f_roready_862; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_862 = out_wivalid_1_716 & out_wimask_862; // @[RegisterRouter.scala:87:24]
wire out_f_woready_862 = out_woready_1_716 & out_womask_862; // @[RegisterRouter.scala:87:24]
wire _out_T_8453 = ~out_rimask_862; // @[RegisterRouter.scala:87:24]
wire _out_T_8454 = ~out_wimask_862; // @[RegisterRouter.scala:87:24]
wire _out_T_8455 = ~out_romask_862; // @[RegisterRouter.scala:87:24]
wire _out_T_8456 = ~out_womask_862; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_734 = {hi_218, flags_0_go, _out_prepend_T_734}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_8457 = out_prepend_734; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_8458 = _out_T_8457; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_735 = _out_T_8458; // @[RegisterRouter.scala:87:24]
wire out_rimask_863 = |_out_rimask_T_863; // @[RegisterRouter.scala:87:24]
wire out_wimask_863 = &_out_wimask_T_863; // @[RegisterRouter.scala:87:24]
wire out_romask_863 = |_out_romask_T_863; // @[RegisterRouter.scala:87:24]
wire out_womask_863 = &_out_womask_T_863; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_863 = out_rivalid_1_717 & out_rimask_863; // @[RegisterRouter.scala:87:24]
wire _out_T_8460 = out_f_rivalid_863; // @[RegisterRouter.scala:87:24]
wire out_f_roready_863 = out_roready_1_717 & out_romask_863; // @[RegisterRouter.scala:87:24]
wire _out_T_8461 = out_f_roready_863; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_863 = out_wivalid_1_717 & out_wimask_863; // @[RegisterRouter.scala:87:24]
wire out_f_woready_863 = out_woready_1_717 & out_womask_863; // @[RegisterRouter.scala:87:24]
wire _out_T_8462 = ~out_rimask_863; // @[RegisterRouter.scala:87:24]
wire _out_T_8463 = ~out_wimask_863; // @[RegisterRouter.scala:87:24]
wire _out_T_8464 = ~out_romask_863; // @[RegisterRouter.scala:87:24]
wire _out_T_8465 = ~out_womask_863; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_735 = {hi_219, flags_0_go, _out_prepend_T_735}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_8466 = out_prepend_735; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_8467 = _out_T_8466; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_736 = _out_T_8467; // @[RegisterRouter.scala:87:24]
wire out_rimask_864 = |_out_rimask_T_864; // @[RegisterRouter.scala:87:24]
wire out_wimask_864 = &_out_wimask_T_864; // @[RegisterRouter.scala:87:24]
wire out_romask_864 = |_out_romask_T_864; // @[RegisterRouter.scala:87:24]
wire out_womask_864 = &_out_womask_T_864; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_864 = out_rivalid_1_718 & out_rimask_864; // @[RegisterRouter.scala:87:24]
wire _out_T_8469 = out_f_rivalid_864; // @[RegisterRouter.scala:87:24]
wire out_f_roready_864 = out_roready_1_718 & out_romask_864; // @[RegisterRouter.scala:87:24]
wire _out_T_8470 = out_f_roready_864; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_864 = out_wivalid_1_718 & out_wimask_864; // @[RegisterRouter.scala:87:24]
wire out_f_woready_864 = out_woready_1_718 & out_womask_864; // @[RegisterRouter.scala:87:24]
wire _out_T_8471 = ~out_rimask_864; // @[RegisterRouter.scala:87:24]
wire _out_T_8472 = ~out_wimask_864; // @[RegisterRouter.scala:87:24]
wire _out_T_8473 = ~out_romask_864; // @[RegisterRouter.scala:87:24]
wire _out_T_8474 = ~out_womask_864; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_736 = {hi_220, flags_0_go, _out_prepend_T_736}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_8475 = out_prepend_736; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_8476 = _out_T_8475; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_737 = _out_T_8476; // @[RegisterRouter.scala:87:24]
wire out_rimask_865 = |_out_rimask_T_865; // @[RegisterRouter.scala:87:24]
wire out_wimask_865 = &_out_wimask_T_865; // @[RegisterRouter.scala:87:24]
wire out_romask_865 = |_out_romask_T_865; // @[RegisterRouter.scala:87:24]
wire out_womask_865 = &_out_womask_T_865; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_865 = out_rivalid_1_719 & out_rimask_865; // @[RegisterRouter.scala:87:24]
wire _out_T_8478 = out_f_rivalid_865; // @[RegisterRouter.scala:87:24]
wire out_f_roready_865 = out_roready_1_719 & out_romask_865; // @[RegisterRouter.scala:87:24]
wire _out_T_8479 = out_f_roready_865; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_865 = out_wivalid_1_719 & out_wimask_865; // @[RegisterRouter.scala:87:24]
wire out_f_woready_865 = out_woready_1_719 & out_womask_865; // @[RegisterRouter.scala:87:24]
wire _out_T_8480 = ~out_rimask_865; // @[RegisterRouter.scala:87:24]
wire _out_T_8481 = ~out_wimask_865; // @[RegisterRouter.scala:87:24]
wire _out_T_8482 = ~out_romask_865; // @[RegisterRouter.scala:87:24]
wire _out_T_8483 = ~out_womask_865; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_737 = {hi_221, flags_0_go, _out_prepend_T_737}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_8484 = out_prepend_737; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_8485 = _out_T_8484; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_738 = _out_T_8485; // @[RegisterRouter.scala:87:24]
wire out_rimask_866 = |_out_rimask_T_866; // @[RegisterRouter.scala:87:24]
wire out_wimask_866 = &_out_wimask_T_866; // @[RegisterRouter.scala:87:24]
wire out_romask_866 = |_out_romask_T_866; // @[RegisterRouter.scala:87:24]
wire out_womask_866 = &_out_womask_T_866; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_866 = out_rivalid_1_720 & out_rimask_866; // @[RegisterRouter.scala:87:24]
wire _out_T_8487 = out_f_rivalid_866; // @[RegisterRouter.scala:87:24]
wire out_f_roready_866 = out_roready_1_720 & out_romask_866; // @[RegisterRouter.scala:87:24]
wire _out_T_8488 = out_f_roready_866; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_866 = out_wivalid_1_720 & out_wimask_866; // @[RegisterRouter.scala:87:24]
wire out_f_woready_866 = out_woready_1_720 & out_womask_866; // @[RegisterRouter.scala:87:24]
wire _out_T_8489 = ~out_rimask_866; // @[RegisterRouter.scala:87:24]
wire _out_T_8490 = ~out_wimask_866; // @[RegisterRouter.scala:87:24]
wire _out_T_8491 = ~out_romask_866; // @[RegisterRouter.scala:87:24]
wire _out_T_8492 = ~out_womask_866; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_738 = {hi_222, flags_0_go, _out_prepend_T_738}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_8493 = out_prepend_738; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_8494 = _out_T_8493; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_739 = _out_T_8494; // @[RegisterRouter.scala:87:24]
wire out_rimask_867 = |_out_rimask_T_867; // @[RegisterRouter.scala:87:24]
wire out_wimask_867 = &_out_wimask_T_867; // @[RegisterRouter.scala:87:24]
wire out_romask_867 = |_out_romask_T_867; // @[RegisterRouter.scala:87:24]
wire out_womask_867 = &_out_womask_T_867; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_867 = out_rivalid_1_721 & out_rimask_867; // @[RegisterRouter.scala:87:24]
wire _out_T_8496 = out_f_rivalid_867; // @[RegisterRouter.scala:87:24]
wire out_f_roready_867 = out_roready_1_721 & out_romask_867; // @[RegisterRouter.scala:87:24]
wire _out_T_8497 = out_f_roready_867; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_867 = out_wivalid_1_721 & out_wimask_867; // @[RegisterRouter.scala:87:24]
wire out_f_woready_867 = out_woready_1_721 & out_womask_867; // @[RegisterRouter.scala:87:24]
wire _out_T_8498 = ~out_rimask_867; // @[RegisterRouter.scala:87:24]
wire _out_T_8499 = ~out_wimask_867; // @[RegisterRouter.scala:87:24]
wire _out_T_8500 = ~out_romask_867; // @[RegisterRouter.scala:87:24]
wire _out_T_8501 = ~out_womask_867; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_739 = {hi_223, flags_0_go, _out_prepend_T_739}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_8502 = out_prepend_739; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_8503 = _out_T_8502; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_740 = _out_T_8503; // @[RegisterRouter.scala:87:24]
wire out_rimask_868 = |_out_rimask_T_868; // @[RegisterRouter.scala:87:24]
wire out_wimask_868 = &_out_wimask_T_868; // @[RegisterRouter.scala:87:24]
wire out_romask_868 = |_out_romask_T_868; // @[RegisterRouter.scala:87:24]
wire out_womask_868 = &_out_womask_T_868; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_868 = out_rivalid_1_722 & out_rimask_868; // @[RegisterRouter.scala:87:24]
wire _out_T_8505 = out_f_rivalid_868; // @[RegisterRouter.scala:87:24]
wire out_f_roready_868 = out_roready_1_722 & out_romask_868; // @[RegisterRouter.scala:87:24]
wire _out_T_8506 = out_f_roready_868; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_868 = out_wivalid_1_722 & out_wimask_868; // @[RegisterRouter.scala:87:24]
wire out_f_woready_868 = out_woready_1_722 & out_womask_868; // @[RegisterRouter.scala:87:24]
wire _out_T_8507 = ~out_rimask_868; // @[RegisterRouter.scala:87:24]
wire _out_T_8508 = ~out_wimask_868; // @[RegisterRouter.scala:87:24]
wire _out_T_8509 = ~out_romask_868; // @[RegisterRouter.scala:87:24]
wire _out_T_8510 = ~out_womask_868; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_740 = {hi_224, flags_0_go, _out_prepend_T_740}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_8511 = out_prepend_740; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_8512 = _out_T_8511; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_155 = _out_T_8512; // @[MuxLiteral.scala:49:48]
wire out_rimask_869 = |_out_rimask_T_869; // @[RegisterRouter.scala:87:24]
wire out_wimask_869 = &_out_wimask_T_869; // @[RegisterRouter.scala:87:24]
wire out_romask_869 = |_out_romask_T_869; // @[RegisterRouter.scala:87:24]
wire out_womask_869 = &_out_womask_T_869; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_869 = out_rivalid_1_723 & out_rimask_869; // @[RegisterRouter.scala:87:24]
wire _out_T_8514 = out_f_rivalid_869; // @[RegisterRouter.scala:87:24]
wire out_f_roready_869 = out_roready_1_723 & out_romask_869; // @[RegisterRouter.scala:87:24]
wire _out_T_8515 = out_f_roready_869; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_869 = out_wivalid_1_723 & out_wimask_869; // @[RegisterRouter.scala:87:24]
wire out_f_woready_869 = out_woready_1_723 & out_womask_869; // @[RegisterRouter.scala:87:24]
wire _out_T_8516 = ~out_rimask_869; // @[RegisterRouter.scala:87:24]
wire _out_T_8517 = ~out_wimask_869; // @[RegisterRouter.scala:87:24]
wire _out_T_8518 = ~out_romask_869; // @[RegisterRouter.scala:87:24]
wire _out_T_8519 = ~out_womask_869; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8521 = _out_T_8520; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_741 = _out_T_8521; // @[RegisterRouter.scala:87:24]
wire out_rimask_870 = |_out_rimask_T_870; // @[RegisterRouter.scala:87:24]
wire out_wimask_870 = &_out_wimask_T_870; // @[RegisterRouter.scala:87:24]
wire out_romask_870 = |_out_romask_T_870; // @[RegisterRouter.scala:87:24]
wire out_womask_870 = &_out_womask_T_870; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_870 = out_rivalid_1_724 & out_rimask_870; // @[RegisterRouter.scala:87:24]
wire _out_T_8523 = out_f_rivalid_870; // @[RegisterRouter.scala:87:24]
wire out_f_roready_870 = out_roready_1_724 & out_romask_870; // @[RegisterRouter.scala:87:24]
wire _out_T_8524 = out_f_roready_870; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_870 = out_wivalid_1_724 & out_wimask_870; // @[RegisterRouter.scala:87:24]
wire out_f_woready_870 = out_woready_1_724 & out_womask_870; // @[RegisterRouter.scala:87:24]
wire _out_T_8525 = ~out_rimask_870; // @[RegisterRouter.scala:87:24]
wire _out_T_8526 = ~out_wimask_870; // @[RegisterRouter.scala:87:24]
wire _out_T_8527 = ~out_romask_870; // @[RegisterRouter.scala:87:24]
wire _out_T_8528 = ~out_womask_870; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_741 = {hi_562, flags_0_go, _out_prepend_T_741}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_8529 = out_prepend_741; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_8530 = _out_T_8529; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_742 = _out_T_8530; // @[RegisterRouter.scala:87:24]
wire out_rimask_871 = |_out_rimask_T_871; // @[RegisterRouter.scala:87:24]
wire out_wimask_871 = &_out_wimask_T_871; // @[RegisterRouter.scala:87:24]
wire out_romask_871 = |_out_romask_T_871; // @[RegisterRouter.scala:87:24]
wire out_womask_871 = &_out_womask_T_871; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_871 = out_rivalid_1_725 & out_rimask_871; // @[RegisterRouter.scala:87:24]
wire _out_T_8532 = out_f_rivalid_871; // @[RegisterRouter.scala:87:24]
wire out_f_roready_871 = out_roready_1_725 & out_romask_871; // @[RegisterRouter.scala:87:24]
wire _out_T_8533 = out_f_roready_871; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_871 = out_wivalid_1_725 & out_wimask_871; // @[RegisterRouter.scala:87:24]
wire out_f_woready_871 = out_woready_1_725 & out_womask_871; // @[RegisterRouter.scala:87:24]
wire _out_T_8534 = ~out_rimask_871; // @[RegisterRouter.scala:87:24]
wire _out_T_8535 = ~out_wimask_871; // @[RegisterRouter.scala:87:24]
wire _out_T_8536 = ~out_romask_871; // @[RegisterRouter.scala:87:24]
wire _out_T_8537 = ~out_womask_871; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_742 = {hi_563, flags_0_go, _out_prepend_T_742}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_8538 = out_prepend_742; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_8539 = _out_T_8538; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_743 = _out_T_8539; // @[RegisterRouter.scala:87:24]
wire out_rimask_872 = |_out_rimask_T_872; // @[RegisterRouter.scala:87:24]
wire out_wimask_872 = &_out_wimask_T_872; // @[RegisterRouter.scala:87:24]
wire out_romask_872 = |_out_romask_T_872; // @[RegisterRouter.scala:87:24]
wire out_womask_872 = &_out_womask_T_872; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_872 = out_rivalid_1_726 & out_rimask_872; // @[RegisterRouter.scala:87:24]
wire _out_T_8541 = out_f_rivalid_872; // @[RegisterRouter.scala:87:24]
wire out_f_roready_872 = out_roready_1_726 & out_romask_872; // @[RegisterRouter.scala:87:24]
wire _out_T_8542 = out_f_roready_872; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_872 = out_wivalid_1_726 & out_wimask_872; // @[RegisterRouter.scala:87:24]
wire out_f_woready_872 = out_woready_1_726 & out_womask_872; // @[RegisterRouter.scala:87:24]
wire _out_T_8543 = ~out_rimask_872; // @[RegisterRouter.scala:87:24]
wire _out_T_8544 = ~out_wimask_872; // @[RegisterRouter.scala:87:24]
wire _out_T_8545 = ~out_romask_872; // @[RegisterRouter.scala:87:24]
wire _out_T_8546 = ~out_womask_872; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_743 = {hi_564, flags_0_go, _out_prepend_T_743}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_8547 = out_prepend_743; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_8548 = _out_T_8547; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_744 = _out_T_8548; // @[RegisterRouter.scala:87:24]
wire out_rimask_873 = |_out_rimask_T_873; // @[RegisterRouter.scala:87:24]
wire out_wimask_873 = &_out_wimask_T_873; // @[RegisterRouter.scala:87:24]
wire out_romask_873 = |_out_romask_T_873; // @[RegisterRouter.scala:87:24]
wire out_womask_873 = &_out_womask_T_873; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_873 = out_rivalid_1_727 & out_rimask_873; // @[RegisterRouter.scala:87:24]
wire _out_T_8550 = out_f_rivalid_873; // @[RegisterRouter.scala:87:24]
wire out_f_roready_873 = out_roready_1_727 & out_romask_873; // @[RegisterRouter.scala:87:24]
wire _out_T_8551 = out_f_roready_873; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_873 = out_wivalid_1_727 & out_wimask_873; // @[RegisterRouter.scala:87:24]
wire out_f_woready_873 = out_woready_1_727 & out_womask_873; // @[RegisterRouter.scala:87:24]
wire _out_T_8552 = ~out_rimask_873; // @[RegisterRouter.scala:87:24]
wire _out_T_8553 = ~out_wimask_873; // @[RegisterRouter.scala:87:24]
wire _out_T_8554 = ~out_romask_873; // @[RegisterRouter.scala:87:24]
wire _out_T_8555 = ~out_womask_873; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_744 = {hi_565, flags_0_go, _out_prepend_T_744}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_8556 = out_prepend_744; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_8557 = _out_T_8556; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_745 = _out_T_8557; // @[RegisterRouter.scala:87:24]
wire out_rimask_874 = |_out_rimask_T_874; // @[RegisterRouter.scala:87:24]
wire out_wimask_874 = &_out_wimask_T_874; // @[RegisterRouter.scala:87:24]
wire out_romask_874 = |_out_romask_T_874; // @[RegisterRouter.scala:87:24]
wire out_womask_874 = &_out_womask_T_874; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_874 = out_rivalid_1_728 & out_rimask_874; // @[RegisterRouter.scala:87:24]
wire _out_T_8559 = out_f_rivalid_874; // @[RegisterRouter.scala:87:24]
wire out_f_roready_874 = out_roready_1_728 & out_romask_874; // @[RegisterRouter.scala:87:24]
wire _out_T_8560 = out_f_roready_874; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_874 = out_wivalid_1_728 & out_wimask_874; // @[RegisterRouter.scala:87:24]
wire out_f_woready_874 = out_woready_1_728 & out_womask_874; // @[RegisterRouter.scala:87:24]
wire _out_T_8561 = ~out_rimask_874; // @[RegisterRouter.scala:87:24]
wire _out_T_8562 = ~out_wimask_874; // @[RegisterRouter.scala:87:24]
wire _out_T_8563 = ~out_romask_874; // @[RegisterRouter.scala:87:24]
wire _out_T_8564 = ~out_womask_874; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_745 = {hi_566, flags_0_go, _out_prepend_T_745}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_8565 = out_prepend_745; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_8566 = _out_T_8565; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_746 = _out_T_8566; // @[RegisterRouter.scala:87:24]
wire out_rimask_875 = |_out_rimask_T_875; // @[RegisterRouter.scala:87:24]
wire out_wimask_875 = &_out_wimask_T_875; // @[RegisterRouter.scala:87:24]
wire out_romask_875 = |_out_romask_T_875; // @[RegisterRouter.scala:87:24]
wire out_womask_875 = &_out_womask_T_875; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_875 = out_rivalid_1_729 & out_rimask_875; // @[RegisterRouter.scala:87:24]
wire _out_T_8568 = out_f_rivalid_875; // @[RegisterRouter.scala:87:24]
wire out_f_roready_875 = out_roready_1_729 & out_romask_875; // @[RegisterRouter.scala:87:24]
wire _out_T_8569 = out_f_roready_875; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_875 = out_wivalid_1_729 & out_wimask_875; // @[RegisterRouter.scala:87:24]
wire out_f_woready_875 = out_woready_1_729 & out_womask_875; // @[RegisterRouter.scala:87:24]
wire _out_T_8570 = ~out_rimask_875; // @[RegisterRouter.scala:87:24]
wire _out_T_8571 = ~out_wimask_875; // @[RegisterRouter.scala:87:24]
wire _out_T_8572 = ~out_romask_875; // @[RegisterRouter.scala:87:24]
wire _out_T_8573 = ~out_womask_875; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_746 = {hi_567, flags_0_go, _out_prepend_T_746}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_8574 = out_prepend_746; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_8575 = _out_T_8574; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_747 = _out_T_8575; // @[RegisterRouter.scala:87:24]
wire out_rimask_876 = |_out_rimask_T_876; // @[RegisterRouter.scala:87:24]
wire out_wimask_876 = &_out_wimask_T_876; // @[RegisterRouter.scala:87:24]
wire out_romask_876 = |_out_romask_T_876; // @[RegisterRouter.scala:87:24]
wire out_womask_876 = &_out_womask_T_876; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_876 = out_rivalid_1_730 & out_rimask_876; // @[RegisterRouter.scala:87:24]
wire _out_T_8577 = out_f_rivalid_876; // @[RegisterRouter.scala:87:24]
wire out_f_roready_876 = out_roready_1_730 & out_romask_876; // @[RegisterRouter.scala:87:24]
wire _out_T_8578 = out_f_roready_876; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_876 = out_wivalid_1_730 & out_wimask_876; // @[RegisterRouter.scala:87:24]
wire out_f_woready_876 = out_woready_1_730 & out_womask_876; // @[RegisterRouter.scala:87:24]
wire _out_T_8579 = ~out_rimask_876; // @[RegisterRouter.scala:87:24]
wire _out_T_8580 = ~out_wimask_876; // @[RegisterRouter.scala:87:24]
wire _out_T_8581 = ~out_romask_876; // @[RegisterRouter.scala:87:24]
wire _out_T_8582 = ~out_womask_876; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_747 = {hi_568, flags_0_go, _out_prepend_T_747}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_8583 = out_prepend_747; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_8584 = _out_T_8583; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_198 = _out_T_8584; // @[MuxLiteral.scala:49:48]
wire out_rimask_877 = |_out_rimask_T_877; // @[RegisterRouter.scala:87:24]
wire out_wimask_877 = &_out_wimask_T_877; // @[RegisterRouter.scala:87:24]
wire out_romask_877 = |_out_romask_T_877; // @[RegisterRouter.scala:87:24]
wire out_womask_877 = &_out_womask_T_877; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_877 = out_rivalid_1_731 & out_rimask_877; // @[RegisterRouter.scala:87:24]
wire _out_T_8586 = out_f_rivalid_877; // @[RegisterRouter.scala:87:24]
wire out_f_roready_877 = out_roready_1_731 & out_romask_877; // @[RegisterRouter.scala:87:24]
wire _out_T_8587 = out_f_roready_877; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_877 = out_wivalid_1_731 & out_wimask_877; // @[RegisterRouter.scala:87:24]
wire _out_T_8588 = out_f_wivalid_877; // @[RegisterRouter.scala:87:24]
wire out_f_woready_877 = out_woready_1_731 & out_womask_877; // @[RegisterRouter.scala:87:24]
wire _out_T_8589 = out_f_woready_877; // @[RegisterRouter.scala:87:24]
wire _out_T_8590 = ~out_rimask_877; // @[RegisterRouter.scala:87:24]
wire _out_T_8591 = ~out_wimask_877; // @[RegisterRouter.scala:87:24]
wire _out_T_8592 = ~out_romask_877; // @[RegisterRouter.scala:87:24]
wire _out_T_8593 = ~out_womask_877; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8595 = _out_T_8594; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_748 = _out_T_8595; // @[RegisterRouter.scala:87:24]
wire out_rimask_878 = |_out_rimask_T_878; // @[RegisterRouter.scala:87:24]
wire out_wimask_878 = &_out_wimask_T_878; // @[RegisterRouter.scala:87:24]
wire out_romask_878 = |_out_romask_T_878; // @[RegisterRouter.scala:87:24]
wire out_womask_878 = &_out_womask_T_878; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_878 = out_rivalid_1_732 & out_rimask_878; // @[RegisterRouter.scala:87:24]
wire _out_T_8597 = out_f_rivalid_878; // @[RegisterRouter.scala:87:24]
wire out_f_roready_878 = out_roready_1_732 & out_romask_878; // @[RegisterRouter.scala:87:24]
wire _out_T_8598 = out_f_roready_878; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_878 = out_wivalid_1_732 & out_wimask_878; // @[RegisterRouter.scala:87:24]
wire _out_T_8599 = out_f_wivalid_878; // @[RegisterRouter.scala:87:24]
wire out_f_woready_878 = out_woready_1_732 & out_womask_878; // @[RegisterRouter.scala:87:24]
wire _out_T_8600 = out_f_woready_878; // @[RegisterRouter.scala:87:24]
wire _out_T_8601 = ~out_rimask_878; // @[RegisterRouter.scala:87:24]
wire _out_T_8602 = ~out_wimask_878; // @[RegisterRouter.scala:87:24]
wire _out_T_8603 = ~out_romask_878; // @[RegisterRouter.scala:87:24]
wire _out_T_8604 = ~out_womask_878; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_748 = {programBufferMem_33, _out_prepend_T_748}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_8605 = out_prepend_748; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_8606 = _out_T_8605; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_749 = _out_T_8606; // @[RegisterRouter.scala:87:24]
wire out_rimask_879 = |_out_rimask_T_879; // @[RegisterRouter.scala:87:24]
wire out_wimask_879 = &_out_wimask_T_879; // @[RegisterRouter.scala:87:24]
wire out_romask_879 = |_out_romask_T_879; // @[RegisterRouter.scala:87:24]
wire out_womask_879 = &_out_womask_T_879; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_879 = out_rivalid_1_733 & out_rimask_879; // @[RegisterRouter.scala:87:24]
wire _out_T_8608 = out_f_rivalid_879; // @[RegisterRouter.scala:87:24]
wire out_f_roready_879 = out_roready_1_733 & out_romask_879; // @[RegisterRouter.scala:87:24]
wire _out_T_8609 = out_f_roready_879; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_879 = out_wivalid_1_733 & out_wimask_879; // @[RegisterRouter.scala:87:24]
wire _out_T_8610 = out_f_wivalid_879; // @[RegisterRouter.scala:87:24]
wire out_f_woready_879 = out_woready_1_733 & out_womask_879; // @[RegisterRouter.scala:87:24]
wire _out_T_8611 = out_f_woready_879; // @[RegisterRouter.scala:87:24]
wire _out_T_8612 = ~out_rimask_879; // @[RegisterRouter.scala:87:24]
wire _out_T_8613 = ~out_wimask_879; // @[RegisterRouter.scala:87:24]
wire _out_T_8614 = ~out_romask_879; // @[RegisterRouter.scala:87:24]
wire _out_T_8615 = ~out_womask_879; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_749 = {programBufferMem_34, _out_prepend_T_749}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_8616 = out_prepend_749; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_8617 = _out_T_8616; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_750 = _out_T_8617; // @[RegisterRouter.scala:87:24]
wire out_rimask_880 = |_out_rimask_T_880; // @[RegisterRouter.scala:87:24]
wire out_wimask_880 = &_out_wimask_T_880; // @[RegisterRouter.scala:87:24]
wire out_romask_880 = |_out_romask_T_880; // @[RegisterRouter.scala:87:24]
wire out_womask_880 = &_out_womask_T_880; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_880 = out_rivalid_1_734 & out_rimask_880; // @[RegisterRouter.scala:87:24]
wire _out_T_8619 = out_f_rivalid_880; // @[RegisterRouter.scala:87:24]
wire out_f_roready_880 = out_roready_1_734 & out_romask_880; // @[RegisterRouter.scala:87:24]
wire _out_T_8620 = out_f_roready_880; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_880 = out_wivalid_1_734 & out_wimask_880; // @[RegisterRouter.scala:87:24]
wire _out_T_8621 = out_f_wivalid_880; // @[RegisterRouter.scala:87:24]
wire out_f_woready_880 = out_woready_1_734 & out_womask_880; // @[RegisterRouter.scala:87:24]
wire _out_T_8622 = out_f_woready_880; // @[RegisterRouter.scala:87:24]
wire _out_T_8623 = ~out_rimask_880; // @[RegisterRouter.scala:87:24]
wire _out_T_8624 = ~out_wimask_880; // @[RegisterRouter.scala:87:24]
wire _out_T_8625 = ~out_romask_880; // @[RegisterRouter.scala:87:24]
wire _out_T_8626 = ~out_womask_880; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_750 = {programBufferMem_35, _out_prepend_T_750}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_8627 = out_prepend_750; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_8628 = _out_T_8627; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_751 = _out_T_8628; // @[RegisterRouter.scala:87:24]
wire out_rimask_881 = |_out_rimask_T_881; // @[RegisterRouter.scala:87:24]
wire out_wimask_881 = &_out_wimask_T_881; // @[RegisterRouter.scala:87:24]
wire out_romask_881 = |_out_romask_T_881; // @[RegisterRouter.scala:87:24]
wire out_womask_881 = &_out_womask_T_881; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_881 = out_rivalid_1_735 & out_rimask_881; // @[RegisterRouter.scala:87:24]
wire _out_T_8630 = out_f_rivalid_881; // @[RegisterRouter.scala:87:24]
wire out_f_roready_881 = out_roready_1_735 & out_romask_881; // @[RegisterRouter.scala:87:24]
wire _out_T_8631 = out_f_roready_881; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_881 = out_wivalid_1_735 & out_wimask_881; // @[RegisterRouter.scala:87:24]
wire _out_T_8632 = out_f_wivalid_881; // @[RegisterRouter.scala:87:24]
wire out_f_woready_881 = out_woready_1_735 & out_womask_881; // @[RegisterRouter.scala:87:24]
wire _out_T_8633 = out_f_woready_881; // @[RegisterRouter.scala:87:24]
wire _out_T_8634 = ~out_rimask_881; // @[RegisterRouter.scala:87:24]
wire _out_T_8635 = ~out_wimask_881; // @[RegisterRouter.scala:87:24]
wire _out_T_8636 = ~out_romask_881; // @[RegisterRouter.scala:87:24]
wire _out_T_8637 = ~out_womask_881; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_751 = {programBufferMem_36, _out_prepend_T_751}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_8638 = out_prepend_751; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_8639 = _out_T_8638; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_752 = _out_T_8639; // @[RegisterRouter.scala:87:24]
wire out_rimask_882 = |_out_rimask_T_882; // @[RegisterRouter.scala:87:24]
wire out_wimask_882 = &_out_wimask_T_882; // @[RegisterRouter.scala:87:24]
wire out_romask_882 = |_out_romask_T_882; // @[RegisterRouter.scala:87:24]
wire out_womask_882 = &_out_womask_T_882; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_882 = out_rivalid_1_736 & out_rimask_882; // @[RegisterRouter.scala:87:24]
wire _out_T_8641 = out_f_rivalid_882; // @[RegisterRouter.scala:87:24]
wire out_f_roready_882 = out_roready_1_736 & out_romask_882; // @[RegisterRouter.scala:87:24]
wire _out_T_8642 = out_f_roready_882; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_882 = out_wivalid_1_736 & out_wimask_882; // @[RegisterRouter.scala:87:24]
wire _out_T_8643 = out_f_wivalid_882; // @[RegisterRouter.scala:87:24]
wire out_f_woready_882 = out_woready_1_736 & out_womask_882; // @[RegisterRouter.scala:87:24]
wire _out_T_8644 = out_f_woready_882; // @[RegisterRouter.scala:87:24]
wire _out_T_8645 = ~out_rimask_882; // @[RegisterRouter.scala:87:24]
wire _out_T_8646 = ~out_wimask_882; // @[RegisterRouter.scala:87:24]
wire _out_T_8647 = ~out_romask_882; // @[RegisterRouter.scala:87:24]
wire _out_T_8648 = ~out_womask_882; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_752 = {programBufferMem_37, _out_prepend_T_752}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_8649 = out_prepend_752; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_8650 = _out_T_8649; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_753 = _out_T_8650; // @[RegisterRouter.scala:87:24]
wire out_rimask_883 = |_out_rimask_T_883; // @[RegisterRouter.scala:87:24]
wire out_wimask_883 = &_out_wimask_T_883; // @[RegisterRouter.scala:87:24]
wire out_romask_883 = |_out_romask_T_883; // @[RegisterRouter.scala:87:24]
wire out_womask_883 = &_out_womask_T_883; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_883 = out_rivalid_1_737 & out_rimask_883; // @[RegisterRouter.scala:87:24]
wire _out_T_8652 = out_f_rivalid_883; // @[RegisterRouter.scala:87:24]
wire out_f_roready_883 = out_roready_1_737 & out_romask_883; // @[RegisterRouter.scala:87:24]
wire _out_T_8653 = out_f_roready_883; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_883 = out_wivalid_1_737 & out_wimask_883; // @[RegisterRouter.scala:87:24]
wire _out_T_8654 = out_f_wivalid_883; // @[RegisterRouter.scala:87:24]
wire out_f_woready_883 = out_woready_1_737 & out_womask_883; // @[RegisterRouter.scala:87:24]
wire _out_T_8655 = out_f_woready_883; // @[RegisterRouter.scala:87:24]
wire _out_T_8656 = ~out_rimask_883; // @[RegisterRouter.scala:87:24]
wire _out_T_8657 = ~out_wimask_883; // @[RegisterRouter.scala:87:24]
wire _out_T_8658 = ~out_romask_883; // @[RegisterRouter.scala:87:24]
wire _out_T_8659 = ~out_womask_883; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_753 = {programBufferMem_38, _out_prepend_T_753}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_8660 = out_prepend_753; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_8661 = _out_T_8660; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_754 = _out_T_8661; // @[RegisterRouter.scala:87:24]
wire out_rimask_884 = |_out_rimask_T_884; // @[RegisterRouter.scala:87:24]
wire out_wimask_884 = &_out_wimask_T_884; // @[RegisterRouter.scala:87:24]
wire out_romask_884 = |_out_romask_T_884; // @[RegisterRouter.scala:87:24]
wire out_womask_884 = &_out_womask_T_884; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_884 = out_rivalid_1_738 & out_rimask_884; // @[RegisterRouter.scala:87:24]
wire _out_T_8663 = out_f_rivalid_884; // @[RegisterRouter.scala:87:24]
wire out_f_roready_884 = out_roready_1_738 & out_romask_884; // @[RegisterRouter.scala:87:24]
wire _out_T_8664 = out_f_roready_884; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_884 = out_wivalid_1_738 & out_wimask_884; // @[RegisterRouter.scala:87:24]
wire _out_T_8665 = out_f_wivalid_884; // @[RegisterRouter.scala:87:24]
wire out_f_woready_884 = out_woready_1_738 & out_womask_884; // @[RegisterRouter.scala:87:24]
wire _out_T_8666 = out_f_woready_884; // @[RegisterRouter.scala:87:24]
wire _out_T_8667 = ~out_rimask_884; // @[RegisterRouter.scala:87:24]
wire _out_T_8668 = ~out_wimask_884; // @[RegisterRouter.scala:87:24]
wire _out_T_8669 = ~out_romask_884; // @[RegisterRouter.scala:87:24]
wire _out_T_8670 = ~out_womask_884; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_754 = {programBufferMem_39, _out_prepend_T_754}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_8671 = out_prepend_754; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_8672 = _out_T_8671; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_108 = _out_T_8672; // @[MuxLiteral.scala:49:48]
wire out_rimask_885 = |_out_rimask_T_885; // @[RegisterRouter.scala:87:24]
wire out_wimask_885 = &_out_wimask_T_885; // @[RegisterRouter.scala:87:24]
wire out_romask_885 = |_out_romask_T_885; // @[RegisterRouter.scala:87:24]
wire out_womask_885 = &_out_womask_T_885; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_885 = out_rivalid_1_739 & out_rimask_885; // @[RegisterRouter.scala:87:24]
wire _out_T_8674 = out_f_rivalid_885; // @[RegisterRouter.scala:87:24]
wire out_f_roready_885 = out_roready_1_739 & out_romask_885; // @[RegisterRouter.scala:87:24]
wire _out_T_8675 = out_f_roready_885; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_885 = out_wivalid_1_739 & out_wimask_885; // @[RegisterRouter.scala:87:24]
wire out_f_woready_885 = out_woready_1_739 & out_womask_885; // @[RegisterRouter.scala:87:24]
wire _out_T_8676 = ~out_rimask_885; // @[RegisterRouter.scala:87:24]
wire _out_T_8677 = ~out_wimask_885; // @[RegisterRouter.scala:87:24]
wire _out_T_8678 = ~out_romask_885; // @[RegisterRouter.scala:87:24]
wire _out_T_8679 = ~out_womask_885; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8681 = _out_T_8680; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_755 = _out_T_8681; // @[RegisterRouter.scala:87:24]
wire out_rimask_886 = |_out_rimask_T_886; // @[RegisterRouter.scala:87:24]
wire out_wimask_886 = &_out_wimask_T_886; // @[RegisterRouter.scala:87:24]
wire out_romask_886 = |_out_romask_T_886; // @[RegisterRouter.scala:87:24]
wire out_womask_886 = &_out_womask_T_886; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_886 = out_rivalid_1_740 & out_rimask_886; // @[RegisterRouter.scala:87:24]
wire _out_T_8683 = out_f_rivalid_886; // @[RegisterRouter.scala:87:24]
wire out_f_roready_886 = out_roready_1_740 & out_romask_886; // @[RegisterRouter.scala:87:24]
wire _out_T_8684 = out_f_roready_886; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_886 = out_wivalid_1_740 & out_wimask_886; // @[RegisterRouter.scala:87:24]
wire out_f_woready_886 = out_woready_1_740 & out_womask_886; // @[RegisterRouter.scala:87:24]
wire _out_T_8685 = ~out_rimask_886; // @[RegisterRouter.scala:87:24]
wire _out_T_8686 = ~out_wimask_886; // @[RegisterRouter.scala:87:24]
wire _out_T_8687 = ~out_romask_886; // @[RegisterRouter.scala:87:24]
wire _out_T_8688 = ~out_womask_886; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_755 = {hi_898, flags_0_go, _out_prepend_T_755}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_8689 = out_prepend_755; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_8690 = _out_T_8689; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_756 = _out_T_8690; // @[RegisterRouter.scala:87:24]
wire out_rimask_887 = |_out_rimask_T_887; // @[RegisterRouter.scala:87:24]
wire out_wimask_887 = &_out_wimask_T_887; // @[RegisterRouter.scala:87:24]
wire out_romask_887 = |_out_romask_T_887; // @[RegisterRouter.scala:87:24]
wire out_womask_887 = &_out_womask_T_887; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_887 = out_rivalid_1_741 & out_rimask_887; // @[RegisterRouter.scala:87:24]
wire _out_T_8692 = out_f_rivalid_887; // @[RegisterRouter.scala:87:24]
wire out_f_roready_887 = out_roready_1_741 & out_romask_887; // @[RegisterRouter.scala:87:24]
wire _out_T_8693 = out_f_roready_887; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_887 = out_wivalid_1_741 & out_wimask_887; // @[RegisterRouter.scala:87:24]
wire out_f_woready_887 = out_woready_1_741 & out_womask_887; // @[RegisterRouter.scala:87:24]
wire _out_T_8694 = ~out_rimask_887; // @[RegisterRouter.scala:87:24]
wire _out_T_8695 = ~out_wimask_887; // @[RegisterRouter.scala:87:24]
wire _out_T_8696 = ~out_romask_887; // @[RegisterRouter.scala:87:24]
wire _out_T_8697 = ~out_womask_887; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_756 = {hi_899, flags_0_go, _out_prepend_T_756}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_8698 = out_prepend_756; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_8699 = _out_T_8698; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_757 = _out_T_8699; // @[RegisterRouter.scala:87:24]
wire out_rimask_888 = |_out_rimask_T_888; // @[RegisterRouter.scala:87:24]
wire out_wimask_888 = &_out_wimask_T_888; // @[RegisterRouter.scala:87:24]
wire out_romask_888 = |_out_romask_T_888; // @[RegisterRouter.scala:87:24]
wire out_womask_888 = &_out_womask_T_888; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_888 = out_rivalid_1_742 & out_rimask_888; // @[RegisterRouter.scala:87:24]
wire _out_T_8701 = out_f_rivalid_888; // @[RegisterRouter.scala:87:24]
wire out_f_roready_888 = out_roready_1_742 & out_romask_888; // @[RegisterRouter.scala:87:24]
wire _out_T_8702 = out_f_roready_888; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_888 = out_wivalid_1_742 & out_wimask_888; // @[RegisterRouter.scala:87:24]
wire out_f_woready_888 = out_woready_1_742 & out_womask_888; // @[RegisterRouter.scala:87:24]
wire _out_T_8703 = ~out_rimask_888; // @[RegisterRouter.scala:87:24]
wire _out_T_8704 = ~out_wimask_888; // @[RegisterRouter.scala:87:24]
wire _out_T_8705 = ~out_romask_888; // @[RegisterRouter.scala:87:24]
wire _out_T_8706 = ~out_womask_888; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_757 = {hi_900, flags_0_go, _out_prepend_T_757}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_8707 = out_prepend_757; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_8708 = _out_T_8707; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_758 = _out_T_8708; // @[RegisterRouter.scala:87:24]
wire out_rimask_889 = |_out_rimask_T_889; // @[RegisterRouter.scala:87:24]
wire out_wimask_889 = &_out_wimask_T_889; // @[RegisterRouter.scala:87:24]
wire out_romask_889 = |_out_romask_T_889; // @[RegisterRouter.scala:87:24]
wire out_womask_889 = &_out_womask_T_889; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_889 = out_rivalid_1_743 & out_rimask_889; // @[RegisterRouter.scala:87:24]
wire _out_T_8710 = out_f_rivalid_889; // @[RegisterRouter.scala:87:24]
wire out_f_roready_889 = out_roready_1_743 & out_romask_889; // @[RegisterRouter.scala:87:24]
wire _out_T_8711 = out_f_roready_889; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_889 = out_wivalid_1_743 & out_wimask_889; // @[RegisterRouter.scala:87:24]
wire out_f_woready_889 = out_woready_1_743 & out_womask_889; // @[RegisterRouter.scala:87:24]
wire _out_T_8712 = ~out_rimask_889; // @[RegisterRouter.scala:87:24]
wire _out_T_8713 = ~out_wimask_889; // @[RegisterRouter.scala:87:24]
wire _out_T_8714 = ~out_romask_889; // @[RegisterRouter.scala:87:24]
wire _out_T_8715 = ~out_womask_889; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_758 = {hi_901, flags_0_go, _out_prepend_T_758}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_8716 = out_prepend_758; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_8717 = _out_T_8716; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_759 = _out_T_8717; // @[RegisterRouter.scala:87:24]
wire out_rimask_890 = |_out_rimask_T_890; // @[RegisterRouter.scala:87:24]
wire out_wimask_890 = &_out_wimask_T_890; // @[RegisterRouter.scala:87:24]
wire out_romask_890 = |_out_romask_T_890; // @[RegisterRouter.scala:87:24]
wire out_womask_890 = &_out_womask_T_890; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_890 = out_rivalid_1_744 & out_rimask_890; // @[RegisterRouter.scala:87:24]
wire _out_T_8719 = out_f_rivalid_890; // @[RegisterRouter.scala:87:24]
wire out_f_roready_890 = out_roready_1_744 & out_romask_890; // @[RegisterRouter.scala:87:24]
wire _out_T_8720 = out_f_roready_890; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_890 = out_wivalid_1_744 & out_wimask_890; // @[RegisterRouter.scala:87:24]
wire out_f_woready_890 = out_woready_1_744 & out_womask_890; // @[RegisterRouter.scala:87:24]
wire _out_T_8721 = ~out_rimask_890; // @[RegisterRouter.scala:87:24]
wire _out_T_8722 = ~out_wimask_890; // @[RegisterRouter.scala:87:24]
wire _out_T_8723 = ~out_romask_890; // @[RegisterRouter.scala:87:24]
wire _out_T_8724 = ~out_womask_890; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_759 = {hi_902, flags_0_go, _out_prepend_T_759}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_8725 = out_prepend_759; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_8726 = _out_T_8725; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_760 = _out_T_8726; // @[RegisterRouter.scala:87:24]
wire out_rimask_891 = |_out_rimask_T_891; // @[RegisterRouter.scala:87:24]
wire out_wimask_891 = &_out_wimask_T_891; // @[RegisterRouter.scala:87:24]
wire out_romask_891 = |_out_romask_T_891; // @[RegisterRouter.scala:87:24]
wire out_womask_891 = &_out_womask_T_891; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_891 = out_rivalid_1_745 & out_rimask_891; // @[RegisterRouter.scala:87:24]
wire _out_T_8728 = out_f_rivalid_891; // @[RegisterRouter.scala:87:24]
wire out_f_roready_891 = out_roready_1_745 & out_romask_891; // @[RegisterRouter.scala:87:24]
wire _out_T_8729 = out_f_roready_891; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_891 = out_wivalid_1_745 & out_wimask_891; // @[RegisterRouter.scala:87:24]
wire out_f_woready_891 = out_woready_1_745 & out_womask_891; // @[RegisterRouter.scala:87:24]
wire _out_T_8730 = ~out_rimask_891; // @[RegisterRouter.scala:87:24]
wire _out_T_8731 = ~out_wimask_891; // @[RegisterRouter.scala:87:24]
wire _out_T_8732 = ~out_romask_891; // @[RegisterRouter.scala:87:24]
wire _out_T_8733 = ~out_womask_891; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_760 = {hi_903, flags_0_go, _out_prepend_T_760}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_8734 = out_prepend_760; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_8735 = _out_T_8734; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_761 = _out_T_8735; // @[RegisterRouter.scala:87:24]
wire out_rimask_892 = |_out_rimask_T_892; // @[RegisterRouter.scala:87:24]
wire out_wimask_892 = &_out_wimask_T_892; // @[RegisterRouter.scala:87:24]
wire out_romask_892 = |_out_romask_T_892; // @[RegisterRouter.scala:87:24]
wire out_womask_892 = &_out_womask_T_892; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_892 = out_rivalid_1_746 & out_rimask_892; // @[RegisterRouter.scala:87:24]
wire _out_T_8737 = out_f_rivalid_892; // @[RegisterRouter.scala:87:24]
wire out_f_roready_892 = out_roready_1_746 & out_romask_892; // @[RegisterRouter.scala:87:24]
wire _out_T_8738 = out_f_roready_892; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_892 = out_wivalid_1_746 & out_wimask_892; // @[RegisterRouter.scala:87:24]
wire out_f_woready_892 = out_woready_1_746 & out_womask_892; // @[RegisterRouter.scala:87:24]
wire _out_T_8739 = ~out_rimask_892; // @[RegisterRouter.scala:87:24]
wire _out_T_8740 = ~out_wimask_892; // @[RegisterRouter.scala:87:24]
wire _out_T_8741 = ~out_romask_892; // @[RegisterRouter.scala:87:24]
wire _out_T_8742 = ~out_womask_892; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_761 = {hi_904, flags_0_go, _out_prepend_T_761}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_8743 = out_prepend_761; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_8744 = _out_T_8743; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_240 = _out_T_8744; // @[MuxLiteral.scala:49:48]
wire out_rimask_893 = |_out_rimask_T_893; // @[RegisterRouter.scala:87:24]
wire out_wimask_893 = &_out_wimask_T_893; // @[RegisterRouter.scala:87:24]
wire out_romask_893 = |_out_romask_T_893; // @[RegisterRouter.scala:87:24]
wire out_womask_893 = &_out_womask_T_893; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_893 = out_rivalid_1_747 & out_rimask_893; // @[RegisterRouter.scala:87:24]
wire _out_T_8746 = out_f_rivalid_893; // @[RegisterRouter.scala:87:24]
wire out_f_roready_893 = out_roready_1_747 & out_romask_893; // @[RegisterRouter.scala:87:24]
wire _out_T_8747 = out_f_roready_893; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_893 = out_wivalid_1_747 & out_wimask_893; // @[RegisterRouter.scala:87:24]
wire out_f_woready_893 = out_woready_1_747 & out_womask_893; // @[RegisterRouter.scala:87:24]
wire _out_T_8748 = ~out_rimask_893; // @[RegisterRouter.scala:87:24]
wire _out_T_8749 = ~out_wimask_893; // @[RegisterRouter.scala:87:24]
wire _out_T_8750 = ~out_romask_893; // @[RegisterRouter.scala:87:24]
wire _out_T_8751 = ~out_womask_893; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8753 = _out_T_8752; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_762 = _out_T_8753; // @[RegisterRouter.scala:87:24]
wire out_rimask_894 = |_out_rimask_T_894; // @[RegisterRouter.scala:87:24]
wire out_wimask_894 = &_out_wimask_T_894; // @[RegisterRouter.scala:87:24]
wire out_romask_894 = |_out_romask_T_894; // @[RegisterRouter.scala:87:24]
wire out_womask_894 = &_out_womask_T_894; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_894 = out_rivalid_1_748 & out_rimask_894; // @[RegisterRouter.scala:87:24]
wire _out_T_8755 = out_f_rivalid_894; // @[RegisterRouter.scala:87:24]
wire out_f_roready_894 = out_roready_1_748 & out_romask_894; // @[RegisterRouter.scala:87:24]
wire _out_T_8756 = out_f_roready_894; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_894 = out_wivalid_1_748 & out_wimask_894; // @[RegisterRouter.scala:87:24]
wire out_f_woready_894 = out_woready_1_748 & out_womask_894; // @[RegisterRouter.scala:87:24]
wire _out_T_8757 = ~out_rimask_894; // @[RegisterRouter.scala:87:24]
wire _out_T_8758 = ~out_wimask_894; // @[RegisterRouter.scala:87:24]
wire _out_T_8759 = ~out_romask_894; // @[RegisterRouter.scala:87:24]
wire _out_T_8760 = ~out_womask_894; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_762 = {hi_986, flags_0_go, _out_prepend_T_762}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_8761 = out_prepend_762; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_8762 = _out_T_8761; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_763 = _out_T_8762; // @[RegisterRouter.scala:87:24]
wire out_rimask_895 = |_out_rimask_T_895; // @[RegisterRouter.scala:87:24]
wire out_wimask_895 = &_out_wimask_T_895; // @[RegisterRouter.scala:87:24]
wire out_romask_895 = |_out_romask_T_895; // @[RegisterRouter.scala:87:24]
wire out_womask_895 = &_out_womask_T_895; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_895 = out_rivalid_1_749 & out_rimask_895; // @[RegisterRouter.scala:87:24]
wire _out_T_8764 = out_f_rivalid_895; // @[RegisterRouter.scala:87:24]
wire out_f_roready_895 = out_roready_1_749 & out_romask_895; // @[RegisterRouter.scala:87:24]
wire _out_T_8765 = out_f_roready_895; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_895 = out_wivalid_1_749 & out_wimask_895; // @[RegisterRouter.scala:87:24]
wire out_f_woready_895 = out_woready_1_749 & out_womask_895; // @[RegisterRouter.scala:87:24]
wire _out_T_8766 = ~out_rimask_895; // @[RegisterRouter.scala:87:24]
wire _out_T_8767 = ~out_wimask_895; // @[RegisterRouter.scala:87:24]
wire _out_T_8768 = ~out_romask_895; // @[RegisterRouter.scala:87:24]
wire _out_T_8769 = ~out_womask_895; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_763 = {hi_987, flags_0_go, _out_prepend_T_763}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_8770 = out_prepend_763; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_8771 = _out_T_8770; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_764 = _out_T_8771; // @[RegisterRouter.scala:87:24]
wire out_rimask_896 = |_out_rimask_T_896; // @[RegisterRouter.scala:87:24]
wire out_wimask_896 = &_out_wimask_T_896; // @[RegisterRouter.scala:87:24]
wire out_romask_896 = |_out_romask_T_896; // @[RegisterRouter.scala:87:24]
wire out_womask_896 = &_out_womask_T_896; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_896 = out_rivalid_1_750 & out_rimask_896; // @[RegisterRouter.scala:87:24]
wire _out_T_8773 = out_f_rivalid_896; // @[RegisterRouter.scala:87:24]
wire out_f_roready_896 = out_roready_1_750 & out_romask_896; // @[RegisterRouter.scala:87:24]
wire _out_T_8774 = out_f_roready_896; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_896 = out_wivalid_1_750 & out_wimask_896; // @[RegisterRouter.scala:87:24]
wire out_f_woready_896 = out_woready_1_750 & out_womask_896; // @[RegisterRouter.scala:87:24]
wire _out_T_8775 = ~out_rimask_896; // @[RegisterRouter.scala:87:24]
wire _out_T_8776 = ~out_wimask_896; // @[RegisterRouter.scala:87:24]
wire _out_T_8777 = ~out_romask_896; // @[RegisterRouter.scala:87:24]
wire _out_T_8778 = ~out_womask_896; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_764 = {hi_988, flags_0_go, _out_prepend_T_764}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_8779 = out_prepend_764; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_8780 = _out_T_8779; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_765 = _out_T_8780; // @[RegisterRouter.scala:87:24]
wire out_rimask_897 = |_out_rimask_T_897; // @[RegisterRouter.scala:87:24]
wire out_wimask_897 = &_out_wimask_T_897; // @[RegisterRouter.scala:87:24]
wire out_romask_897 = |_out_romask_T_897; // @[RegisterRouter.scala:87:24]
wire out_womask_897 = &_out_womask_T_897; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_897 = out_rivalid_1_751 & out_rimask_897; // @[RegisterRouter.scala:87:24]
wire _out_T_8782 = out_f_rivalid_897; // @[RegisterRouter.scala:87:24]
wire out_f_roready_897 = out_roready_1_751 & out_romask_897; // @[RegisterRouter.scala:87:24]
wire _out_T_8783 = out_f_roready_897; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_897 = out_wivalid_1_751 & out_wimask_897; // @[RegisterRouter.scala:87:24]
wire out_f_woready_897 = out_woready_1_751 & out_womask_897; // @[RegisterRouter.scala:87:24]
wire _out_T_8784 = ~out_rimask_897; // @[RegisterRouter.scala:87:24]
wire _out_T_8785 = ~out_wimask_897; // @[RegisterRouter.scala:87:24]
wire _out_T_8786 = ~out_romask_897; // @[RegisterRouter.scala:87:24]
wire _out_T_8787 = ~out_womask_897; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_765 = {hi_989, flags_0_go, _out_prepend_T_765}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_8788 = out_prepend_765; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_8789 = _out_T_8788; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_766 = _out_T_8789; // @[RegisterRouter.scala:87:24]
wire out_rimask_898 = |_out_rimask_T_898; // @[RegisterRouter.scala:87:24]
wire out_wimask_898 = &_out_wimask_T_898; // @[RegisterRouter.scala:87:24]
wire out_romask_898 = |_out_romask_T_898; // @[RegisterRouter.scala:87:24]
wire out_womask_898 = &_out_womask_T_898; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_898 = out_rivalid_1_752 & out_rimask_898; // @[RegisterRouter.scala:87:24]
wire _out_T_8791 = out_f_rivalid_898; // @[RegisterRouter.scala:87:24]
wire out_f_roready_898 = out_roready_1_752 & out_romask_898; // @[RegisterRouter.scala:87:24]
wire _out_T_8792 = out_f_roready_898; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_898 = out_wivalid_1_752 & out_wimask_898; // @[RegisterRouter.scala:87:24]
wire out_f_woready_898 = out_woready_1_752 & out_womask_898; // @[RegisterRouter.scala:87:24]
wire _out_T_8793 = ~out_rimask_898; // @[RegisterRouter.scala:87:24]
wire _out_T_8794 = ~out_wimask_898; // @[RegisterRouter.scala:87:24]
wire _out_T_8795 = ~out_romask_898; // @[RegisterRouter.scala:87:24]
wire _out_T_8796 = ~out_womask_898; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_766 = {hi_990, flags_0_go, _out_prepend_T_766}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_8797 = out_prepend_766; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_8798 = _out_T_8797; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_767 = _out_T_8798; // @[RegisterRouter.scala:87:24]
wire out_rimask_899 = |_out_rimask_T_899; // @[RegisterRouter.scala:87:24]
wire out_wimask_899 = &_out_wimask_T_899; // @[RegisterRouter.scala:87:24]
wire out_romask_899 = |_out_romask_T_899; // @[RegisterRouter.scala:87:24]
wire out_womask_899 = &_out_womask_T_899; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_899 = out_rivalid_1_753 & out_rimask_899; // @[RegisterRouter.scala:87:24]
wire _out_T_8800 = out_f_rivalid_899; // @[RegisterRouter.scala:87:24]
wire out_f_roready_899 = out_roready_1_753 & out_romask_899; // @[RegisterRouter.scala:87:24]
wire _out_T_8801 = out_f_roready_899; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_899 = out_wivalid_1_753 & out_wimask_899; // @[RegisterRouter.scala:87:24]
wire out_f_woready_899 = out_woready_1_753 & out_womask_899; // @[RegisterRouter.scala:87:24]
wire _out_T_8802 = ~out_rimask_899; // @[RegisterRouter.scala:87:24]
wire _out_T_8803 = ~out_wimask_899; // @[RegisterRouter.scala:87:24]
wire _out_T_8804 = ~out_romask_899; // @[RegisterRouter.scala:87:24]
wire _out_T_8805 = ~out_womask_899; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_767 = {hi_991, flags_0_go, _out_prepend_T_767}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_8806 = out_prepend_767; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_8807 = _out_T_8806; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_768 = _out_T_8807; // @[RegisterRouter.scala:87:24]
wire out_rimask_900 = |_out_rimask_T_900; // @[RegisterRouter.scala:87:24]
wire out_wimask_900 = &_out_wimask_T_900; // @[RegisterRouter.scala:87:24]
wire out_romask_900 = |_out_romask_T_900; // @[RegisterRouter.scala:87:24]
wire out_womask_900 = &_out_womask_T_900; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_900 = out_rivalid_1_754 & out_rimask_900; // @[RegisterRouter.scala:87:24]
wire _out_T_8809 = out_f_rivalid_900; // @[RegisterRouter.scala:87:24]
wire out_f_roready_900 = out_roready_1_754 & out_romask_900; // @[RegisterRouter.scala:87:24]
wire _out_T_8810 = out_f_roready_900; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_900 = out_wivalid_1_754 & out_wimask_900; // @[RegisterRouter.scala:87:24]
wire out_f_woready_900 = out_woready_1_754 & out_womask_900; // @[RegisterRouter.scala:87:24]
wire _out_T_8811 = ~out_rimask_900; // @[RegisterRouter.scala:87:24]
wire _out_T_8812 = ~out_wimask_900; // @[RegisterRouter.scala:87:24]
wire _out_T_8813 = ~out_romask_900; // @[RegisterRouter.scala:87:24]
wire _out_T_8814 = ~out_womask_900; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_768 = {hi_992, flags_0_go, _out_prepend_T_768}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_8815 = out_prepend_768; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_8816 = _out_T_8815; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_251 = _out_T_8816; // @[MuxLiteral.scala:49:48]
wire out_rimask_901 = |_out_rimask_T_901; // @[RegisterRouter.scala:87:24]
wire out_wimask_901 = &_out_wimask_T_901; // @[RegisterRouter.scala:87:24]
wire out_romask_901 = |_out_romask_T_901; // @[RegisterRouter.scala:87:24]
wire out_womask_901 = &_out_womask_T_901; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_901 = out_rivalid_1_755 & out_rimask_901; // @[RegisterRouter.scala:87:24]
wire _out_T_8818 = out_f_rivalid_901; // @[RegisterRouter.scala:87:24]
wire out_f_roready_901 = out_roready_1_755 & out_romask_901; // @[RegisterRouter.scala:87:24]
wire _out_T_8819 = out_f_roready_901; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_901 = out_wivalid_1_755 & out_wimask_901; // @[RegisterRouter.scala:87:24]
wire out_f_woready_901 = out_woready_1_755 & out_womask_901; // @[RegisterRouter.scala:87:24]
wire _out_T_8820 = ~out_rimask_901; // @[RegisterRouter.scala:87:24]
wire _out_T_8821 = ~out_wimask_901; // @[RegisterRouter.scala:87:24]
wire _out_T_8822 = ~out_romask_901; // @[RegisterRouter.scala:87:24]
wire _out_T_8823 = ~out_womask_901; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8825 = _out_T_8824; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_769 = _out_T_8825; // @[RegisterRouter.scala:87:24]
wire out_rimask_902 = |_out_rimask_T_902; // @[RegisterRouter.scala:87:24]
wire out_wimask_902 = &_out_wimask_T_902; // @[RegisterRouter.scala:87:24]
wire out_romask_902 = |_out_romask_T_902; // @[RegisterRouter.scala:87:24]
wire out_womask_902 = &_out_womask_T_902; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_902 = out_rivalid_1_756 & out_rimask_902; // @[RegisterRouter.scala:87:24]
wire _out_T_8827 = out_f_rivalid_902; // @[RegisterRouter.scala:87:24]
wire out_f_roready_902 = out_roready_1_756 & out_romask_902; // @[RegisterRouter.scala:87:24]
wire _out_T_8828 = out_f_roready_902; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_902 = out_wivalid_1_756 & out_wimask_902; // @[RegisterRouter.scala:87:24]
wire out_f_woready_902 = out_woready_1_756 & out_womask_902; // @[RegisterRouter.scala:87:24]
wire _out_T_8829 = ~out_rimask_902; // @[RegisterRouter.scala:87:24]
wire _out_T_8830 = ~out_wimask_902; // @[RegisterRouter.scala:87:24]
wire _out_T_8831 = ~out_romask_902; // @[RegisterRouter.scala:87:24]
wire _out_T_8832 = ~out_womask_902; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_769 = {hi_18, flags_0_go, _out_prepend_T_769}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_8833 = out_prepend_769; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_8834 = _out_T_8833; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_770 = _out_T_8834; // @[RegisterRouter.scala:87:24]
wire out_rimask_903 = |_out_rimask_T_903; // @[RegisterRouter.scala:87:24]
wire out_wimask_903 = &_out_wimask_T_903; // @[RegisterRouter.scala:87:24]
wire out_romask_903 = |_out_romask_T_903; // @[RegisterRouter.scala:87:24]
wire out_womask_903 = &_out_womask_T_903; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_903 = out_rivalid_1_757 & out_rimask_903; // @[RegisterRouter.scala:87:24]
wire _out_T_8836 = out_f_rivalid_903; // @[RegisterRouter.scala:87:24]
wire out_f_roready_903 = out_roready_1_757 & out_romask_903; // @[RegisterRouter.scala:87:24]
wire _out_T_8837 = out_f_roready_903; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_903 = out_wivalid_1_757 & out_wimask_903; // @[RegisterRouter.scala:87:24]
wire out_f_woready_903 = out_woready_1_757 & out_womask_903; // @[RegisterRouter.scala:87:24]
wire _out_T_8838 = ~out_rimask_903; // @[RegisterRouter.scala:87:24]
wire _out_T_8839 = ~out_wimask_903; // @[RegisterRouter.scala:87:24]
wire _out_T_8840 = ~out_romask_903; // @[RegisterRouter.scala:87:24]
wire _out_T_8841 = ~out_womask_903; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_770 = {hi_19, flags_0_go, _out_prepend_T_770}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_8842 = out_prepend_770; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_8843 = _out_T_8842; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_771 = _out_T_8843; // @[RegisterRouter.scala:87:24]
wire out_rimask_904 = |_out_rimask_T_904; // @[RegisterRouter.scala:87:24]
wire out_wimask_904 = &_out_wimask_T_904; // @[RegisterRouter.scala:87:24]
wire out_romask_904 = |_out_romask_T_904; // @[RegisterRouter.scala:87:24]
wire out_womask_904 = &_out_womask_T_904; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_904 = out_rivalid_1_758 & out_rimask_904; // @[RegisterRouter.scala:87:24]
wire _out_T_8845 = out_f_rivalid_904; // @[RegisterRouter.scala:87:24]
wire out_f_roready_904 = out_roready_1_758 & out_romask_904; // @[RegisterRouter.scala:87:24]
wire _out_T_8846 = out_f_roready_904; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_904 = out_wivalid_1_758 & out_wimask_904; // @[RegisterRouter.scala:87:24]
wire out_f_woready_904 = out_woready_1_758 & out_womask_904; // @[RegisterRouter.scala:87:24]
wire _out_T_8847 = ~out_rimask_904; // @[RegisterRouter.scala:87:24]
wire _out_T_8848 = ~out_wimask_904; // @[RegisterRouter.scala:87:24]
wire _out_T_8849 = ~out_romask_904; // @[RegisterRouter.scala:87:24]
wire _out_T_8850 = ~out_womask_904; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_771 = {hi_20, flags_0_go, _out_prepend_T_771}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_8851 = out_prepend_771; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_8852 = _out_T_8851; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_772 = _out_T_8852; // @[RegisterRouter.scala:87:24]
wire out_rimask_905 = |_out_rimask_T_905; // @[RegisterRouter.scala:87:24]
wire out_wimask_905 = &_out_wimask_T_905; // @[RegisterRouter.scala:87:24]
wire out_romask_905 = |_out_romask_T_905; // @[RegisterRouter.scala:87:24]
wire out_womask_905 = &_out_womask_T_905; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_905 = out_rivalid_1_759 & out_rimask_905; // @[RegisterRouter.scala:87:24]
wire _out_T_8854 = out_f_rivalid_905; // @[RegisterRouter.scala:87:24]
wire out_f_roready_905 = out_roready_1_759 & out_romask_905; // @[RegisterRouter.scala:87:24]
wire _out_T_8855 = out_f_roready_905; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_905 = out_wivalid_1_759 & out_wimask_905; // @[RegisterRouter.scala:87:24]
wire out_f_woready_905 = out_woready_1_759 & out_womask_905; // @[RegisterRouter.scala:87:24]
wire _out_T_8856 = ~out_rimask_905; // @[RegisterRouter.scala:87:24]
wire _out_T_8857 = ~out_wimask_905; // @[RegisterRouter.scala:87:24]
wire _out_T_8858 = ~out_romask_905; // @[RegisterRouter.scala:87:24]
wire _out_T_8859 = ~out_womask_905; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_772 = {hi_21, flags_0_go, _out_prepend_T_772}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_8860 = out_prepend_772; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_8861 = _out_T_8860; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_773 = _out_T_8861; // @[RegisterRouter.scala:87:24]
wire out_rimask_906 = |_out_rimask_T_906; // @[RegisterRouter.scala:87:24]
wire out_wimask_906 = &_out_wimask_T_906; // @[RegisterRouter.scala:87:24]
wire out_romask_906 = |_out_romask_T_906; // @[RegisterRouter.scala:87:24]
wire out_womask_906 = &_out_womask_T_906; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_906 = out_rivalid_1_760 & out_rimask_906; // @[RegisterRouter.scala:87:24]
wire _out_T_8863 = out_f_rivalid_906; // @[RegisterRouter.scala:87:24]
wire out_f_roready_906 = out_roready_1_760 & out_romask_906; // @[RegisterRouter.scala:87:24]
wire _out_T_8864 = out_f_roready_906; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_906 = out_wivalid_1_760 & out_wimask_906; // @[RegisterRouter.scala:87:24]
wire out_f_woready_906 = out_woready_1_760 & out_womask_906; // @[RegisterRouter.scala:87:24]
wire _out_T_8865 = ~out_rimask_906; // @[RegisterRouter.scala:87:24]
wire _out_T_8866 = ~out_wimask_906; // @[RegisterRouter.scala:87:24]
wire _out_T_8867 = ~out_romask_906; // @[RegisterRouter.scala:87:24]
wire _out_T_8868 = ~out_womask_906; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_773 = {hi_22, flags_0_go, _out_prepend_T_773}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_8869 = out_prepend_773; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_8870 = _out_T_8869; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_774 = _out_T_8870; // @[RegisterRouter.scala:87:24]
wire out_rimask_907 = |_out_rimask_T_907; // @[RegisterRouter.scala:87:24]
wire out_wimask_907 = &_out_wimask_T_907; // @[RegisterRouter.scala:87:24]
wire out_romask_907 = |_out_romask_T_907; // @[RegisterRouter.scala:87:24]
wire out_womask_907 = &_out_womask_T_907; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_907 = out_rivalid_1_761 & out_rimask_907; // @[RegisterRouter.scala:87:24]
wire _out_T_8872 = out_f_rivalid_907; // @[RegisterRouter.scala:87:24]
wire out_f_roready_907 = out_roready_1_761 & out_romask_907; // @[RegisterRouter.scala:87:24]
wire _out_T_8873 = out_f_roready_907; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_907 = out_wivalid_1_761 & out_wimask_907; // @[RegisterRouter.scala:87:24]
wire out_f_woready_907 = out_woready_1_761 & out_womask_907; // @[RegisterRouter.scala:87:24]
wire _out_T_8874 = ~out_rimask_907; // @[RegisterRouter.scala:87:24]
wire _out_T_8875 = ~out_wimask_907; // @[RegisterRouter.scala:87:24]
wire _out_T_8876 = ~out_romask_907; // @[RegisterRouter.scala:87:24]
wire _out_T_8877 = ~out_womask_907; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_774 = {hi_23, flags_0_go, _out_prepend_T_774}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_8878 = out_prepend_774; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_8879 = _out_T_8878; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_775 = _out_T_8879; // @[RegisterRouter.scala:87:24]
wire out_rimask_908 = |_out_rimask_T_908; // @[RegisterRouter.scala:87:24]
wire out_wimask_908 = &_out_wimask_T_908; // @[RegisterRouter.scala:87:24]
wire out_romask_908 = |_out_romask_T_908; // @[RegisterRouter.scala:87:24]
wire out_womask_908 = &_out_womask_T_908; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_908 = out_rivalid_1_762 & out_rimask_908; // @[RegisterRouter.scala:87:24]
wire _out_T_8881 = out_f_rivalid_908; // @[RegisterRouter.scala:87:24]
wire out_f_roready_908 = out_roready_1_762 & out_romask_908; // @[RegisterRouter.scala:87:24]
wire _out_T_8882 = out_f_roready_908; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_908 = out_wivalid_1_762 & out_wimask_908; // @[RegisterRouter.scala:87:24]
wire out_f_woready_908 = out_woready_1_762 & out_womask_908; // @[RegisterRouter.scala:87:24]
wire _out_T_8883 = ~out_rimask_908; // @[RegisterRouter.scala:87:24]
wire _out_T_8884 = ~out_wimask_908; // @[RegisterRouter.scala:87:24]
wire _out_T_8885 = ~out_romask_908; // @[RegisterRouter.scala:87:24]
wire _out_T_8886 = ~out_womask_908; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_775 = {hi_24, flags_0_go, _out_prepend_T_775}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_8887 = out_prepend_775; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_8888 = _out_T_8887; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_130 = _out_T_8888; // @[MuxLiteral.scala:49:48]
wire out_rimask_909 = |_out_rimask_T_909; // @[RegisterRouter.scala:87:24]
wire out_wimask_909 = &_out_wimask_T_909; // @[RegisterRouter.scala:87:24]
wire out_romask_909 = |_out_romask_T_909; // @[RegisterRouter.scala:87:24]
wire out_womask_909 = &_out_womask_T_909; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_909 = out_rivalid_1_763 & out_rimask_909; // @[RegisterRouter.scala:87:24]
wire _out_T_8890 = out_f_rivalid_909; // @[RegisterRouter.scala:87:24]
wire out_f_roready_909 = out_roready_1_763 & out_romask_909; // @[RegisterRouter.scala:87:24]
wire _out_T_8891 = out_f_roready_909; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_909 = out_wivalid_1_763 & out_wimask_909; // @[RegisterRouter.scala:87:24]
wire out_f_woready_909 = out_woready_1_763 & out_womask_909; // @[RegisterRouter.scala:87:24]
wire _out_T_8892 = ~out_rimask_909; // @[RegisterRouter.scala:87:24]
wire _out_T_8893 = ~out_wimask_909; // @[RegisterRouter.scala:87:24]
wire _out_T_8894 = ~out_romask_909; // @[RegisterRouter.scala:87:24]
wire _out_T_8895 = ~out_womask_909; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8897 = _out_T_8896; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_776 = _out_T_8897; // @[RegisterRouter.scala:87:24]
wire out_rimask_910 = |_out_rimask_T_910; // @[RegisterRouter.scala:87:24]
wire out_wimask_910 = &_out_wimask_T_910; // @[RegisterRouter.scala:87:24]
wire out_romask_910 = |_out_romask_T_910; // @[RegisterRouter.scala:87:24]
wire out_womask_910 = &_out_womask_T_910; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_910 = out_rivalid_1_764 & out_rimask_910; // @[RegisterRouter.scala:87:24]
wire _out_T_8899 = out_f_rivalid_910; // @[RegisterRouter.scala:87:24]
wire out_f_roready_910 = out_roready_1_764 & out_romask_910; // @[RegisterRouter.scala:87:24]
wire _out_T_8900 = out_f_roready_910; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_910 = out_wivalid_1_764 & out_wimask_910; // @[RegisterRouter.scala:87:24]
wire out_f_woready_910 = out_woready_1_764 & out_womask_910; // @[RegisterRouter.scala:87:24]
wire _out_T_8901 = ~out_rimask_910; // @[RegisterRouter.scala:87:24]
wire _out_T_8902 = ~out_wimask_910; // @[RegisterRouter.scala:87:24]
wire _out_T_8903 = ~out_romask_910; // @[RegisterRouter.scala:87:24]
wire _out_T_8904 = ~out_womask_910; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_776 = {hi_762, flags_0_go, _out_prepend_T_776}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_8905 = out_prepend_776; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_8906 = _out_T_8905; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_777 = _out_T_8906; // @[RegisterRouter.scala:87:24]
wire out_rimask_911 = |_out_rimask_T_911; // @[RegisterRouter.scala:87:24]
wire out_wimask_911 = &_out_wimask_T_911; // @[RegisterRouter.scala:87:24]
wire out_romask_911 = |_out_romask_T_911; // @[RegisterRouter.scala:87:24]
wire out_womask_911 = &_out_womask_T_911; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_911 = out_rivalid_1_765 & out_rimask_911; // @[RegisterRouter.scala:87:24]
wire _out_T_8908 = out_f_rivalid_911; // @[RegisterRouter.scala:87:24]
wire out_f_roready_911 = out_roready_1_765 & out_romask_911; // @[RegisterRouter.scala:87:24]
wire _out_T_8909 = out_f_roready_911; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_911 = out_wivalid_1_765 & out_wimask_911; // @[RegisterRouter.scala:87:24]
wire out_f_woready_911 = out_woready_1_765 & out_womask_911; // @[RegisterRouter.scala:87:24]
wire _out_T_8910 = ~out_rimask_911; // @[RegisterRouter.scala:87:24]
wire _out_T_8911 = ~out_wimask_911; // @[RegisterRouter.scala:87:24]
wire _out_T_8912 = ~out_romask_911; // @[RegisterRouter.scala:87:24]
wire _out_T_8913 = ~out_womask_911; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_777 = {hi_763, flags_0_go, _out_prepend_T_777}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_8914 = out_prepend_777; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_8915 = _out_T_8914; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_778 = _out_T_8915; // @[RegisterRouter.scala:87:24]
wire out_rimask_912 = |_out_rimask_T_912; // @[RegisterRouter.scala:87:24]
wire out_wimask_912 = &_out_wimask_T_912; // @[RegisterRouter.scala:87:24]
wire out_romask_912 = |_out_romask_T_912; // @[RegisterRouter.scala:87:24]
wire out_womask_912 = &_out_womask_T_912; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_912 = out_rivalid_1_766 & out_rimask_912; // @[RegisterRouter.scala:87:24]
wire _out_T_8917 = out_f_rivalid_912; // @[RegisterRouter.scala:87:24]
wire out_f_roready_912 = out_roready_1_766 & out_romask_912; // @[RegisterRouter.scala:87:24]
wire _out_T_8918 = out_f_roready_912; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_912 = out_wivalid_1_766 & out_wimask_912; // @[RegisterRouter.scala:87:24]
wire out_f_woready_912 = out_woready_1_766 & out_womask_912; // @[RegisterRouter.scala:87:24]
wire _out_T_8919 = ~out_rimask_912; // @[RegisterRouter.scala:87:24]
wire _out_T_8920 = ~out_wimask_912; // @[RegisterRouter.scala:87:24]
wire _out_T_8921 = ~out_romask_912; // @[RegisterRouter.scala:87:24]
wire _out_T_8922 = ~out_womask_912; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_778 = {hi_764, flags_0_go, _out_prepend_T_778}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_8923 = out_prepend_778; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_8924 = _out_T_8923; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_779 = _out_T_8924; // @[RegisterRouter.scala:87:24]
wire out_rimask_913 = |_out_rimask_T_913; // @[RegisterRouter.scala:87:24]
wire out_wimask_913 = &_out_wimask_T_913; // @[RegisterRouter.scala:87:24]
wire out_romask_913 = |_out_romask_T_913; // @[RegisterRouter.scala:87:24]
wire out_womask_913 = &_out_womask_T_913; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_913 = out_rivalid_1_767 & out_rimask_913; // @[RegisterRouter.scala:87:24]
wire _out_T_8926 = out_f_rivalid_913; // @[RegisterRouter.scala:87:24]
wire out_f_roready_913 = out_roready_1_767 & out_romask_913; // @[RegisterRouter.scala:87:24]
wire _out_T_8927 = out_f_roready_913; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_913 = out_wivalid_1_767 & out_wimask_913; // @[RegisterRouter.scala:87:24]
wire out_f_woready_913 = out_woready_1_767 & out_womask_913; // @[RegisterRouter.scala:87:24]
wire _out_T_8928 = ~out_rimask_913; // @[RegisterRouter.scala:87:24]
wire _out_T_8929 = ~out_wimask_913; // @[RegisterRouter.scala:87:24]
wire _out_T_8930 = ~out_romask_913; // @[RegisterRouter.scala:87:24]
wire _out_T_8931 = ~out_womask_913; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_779 = {hi_765, flags_0_go, _out_prepend_T_779}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_8932 = out_prepend_779; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_8933 = _out_T_8932; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_780 = _out_T_8933; // @[RegisterRouter.scala:87:24]
wire out_rimask_914 = |_out_rimask_T_914; // @[RegisterRouter.scala:87:24]
wire out_wimask_914 = &_out_wimask_T_914; // @[RegisterRouter.scala:87:24]
wire out_romask_914 = |_out_romask_T_914; // @[RegisterRouter.scala:87:24]
wire out_womask_914 = &_out_womask_T_914; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_914 = out_rivalid_1_768 & out_rimask_914; // @[RegisterRouter.scala:87:24]
wire _out_T_8935 = out_f_rivalid_914; // @[RegisterRouter.scala:87:24]
wire out_f_roready_914 = out_roready_1_768 & out_romask_914; // @[RegisterRouter.scala:87:24]
wire _out_T_8936 = out_f_roready_914; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_914 = out_wivalid_1_768 & out_wimask_914; // @[RegisterRouter.scala:87:24]
wire out_f_woready_914 = out_woready_1_768 & out_womask_914; // @[RegisterRouter.scala:87:24]
wire _out_T_8937 = ~out_rimask_914; // @[RegisterRouter.scala:87:24]
wire _out_T_8938 = ~out_wimask_914; // @[RegisterRouter.scala:87:24]
wire _out_T_8939 = ~out_romask_914; // @[RegisterRouter.scala:87:24]
wire _out_T_8940 = ~out_womask_914; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_780 = {hi_766, flags_0_go, _out_prepend_T_780}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_8941 = out_prepend_780; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_8942 = _out_T_8941; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_781 = _out_T_8942; // @[RegisterRouter.scala:87:24]
wire out_rimask_915 = |_out_rimask_T_915; // @[RegisterRouter.scala:87:24]
wire out_wimask_915 = &_out_wimask_T_915; // @[RegisterRouter.scala:87:24]
wire out_romask_915 = |_out_romask_T_915; // @[RegisterRouter.scala:87:24]
wire out_womask_915 = &_out_womask_T_915; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_915 = out_rivalid_1_769 & out_rimask_915; // @[RegisterRouter.scala:87:24]
wire _out_T_8944 = out_f_rivalid_915; // @[RegisterRouter.scala:87:24]
wire out_f_roready_915 = out_roready_1_769 & out_romask_915; // @[RegisterRouter.scala:87:24]
wire _out_T_8945 = out_f_roready_915; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_915 = out_wivalid_1_769 & out_wimask_915; // @[RegisterRouter.scala:87:24]
wire out_f_woready_915 = out_woready_1_769 & out_womask_915; // @[RegisterRouter.scala:87:24]
wire _out_T_8946 = ~out_rimask_915; // @[RegisterRouter.scala:87:24]
wire _out_T_8947 = ~out_wimask_915; // @[RegisterRouter.scala:87:24]
wire _out_T_8948 = ~out_romask_915; // @[RegisterRouter.scala:87:24]
wire _out_T_8949 = ~out_womask_915; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_781 = {hi_767, flags_0_go, _out_prepend_T_781}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_8950 = out_prepend_781; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_8951 = _out_T_8950; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_782 = _out_T_8951; // @[RegisterRouter.scala:87:24]
wire out_rimask_916 = |_out_rimask_T_916; // @[RegisterRouter.scala:87:24]
wire out_wimask_916 = &_out_wimask_T_916; // @[RegisterRouter.scala:87:24]
wire out_romask_916 = |_out_romask_T_916; // @[RegisterRouter.scala:87:24]
wire out_womask_916 = &_out_womask_T_916; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_916 = out_rivalid_1_770 & out_rimask_916; // @[RegisterRouter.scala:87:24]
wire _out_T_8953 = out_f_rivalid_916; // @[RegisterRouter.scala:87:24]
wire out_f_roready_916 = out_roready_1_770 & out_romask_916; // @[RegisterRouter.scala:87:24]
wire _out_T_8954 = out_f_roready_916; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_916 = out_wivalid_1_770 & out_wimask_916; // @[RegisterRouter.scala:87:24]
wire out_f_woready_916 = out_woready_1_770 & out_womask_916; // @[RegisterRouter.scala:87:24]
wire _out_T_8955 = ~out_rimask_916; // @[RegisterRouter.scala:87:24]
wire _out_T_8956 = ~out_wimask_916; // @[RegisterRouter.scala:87:24]
wire _out_T_8957 = ~out_romask_916; // @[RegisterRouter.scala:87:24]
wire _out_T_8958 = ~out_womask_916; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_782 = {hi_768, flags_0_go, _out_prepend_T_782}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_8959 = out_prepend_782; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_8960 = _out_T_8959; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_223 = _out_T_8960; // @[MuxLiteral.scala:49:48]
wire out_rimask_917 = |_out_rimask_T_917; // @[RegisterRouter.scala:87:24]
wire out_wimask_917 = &_out_wimask_T_917; // @[RegisterRouter.scala:87:24]
wire out_romask_917 = |_out_romask_T_917; // @[RegisterRouter.scala:87:24]
wire out_womask_917 = &_out_womask_T_917; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_917 = out_rivalid_1_771 & out_rimask_917; // @[RegisterRouter.scala:87:24]
wire _out_T_8962 = out_f_rivalid_917; // @[RegisterRouter.scala:87:24]
wire out_f_roready_917 = out_roready_1_771 & out_romask_917; // @[RegisterRouter.scala:87:24]
wire _out_T_8963 = out_f_roready_917; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_917 = out_wivalid_1_771 & out_wimask_917; // @[RegisterRouter.scala:87:24]
wire out_f_woready_917 = out_woready_1_771 & out_womask_917; // @[RegisterRouter.scala:87:24]
wire _out_T_8964 = ~out_rimask_917; // @[RegisterRouter.scala:87:24]
wire _out_T_8965 = ~out_wimask_917; // @[RegisterRouter.scala:87:24]
wire _out_T_8966 = ~out_romask_917; // @[RegisterRouter.scala:87:24]
wire _out_T_8967 = ~out_womask_917; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8969 = _out_T_8968; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_783 = _out_T_8969; // @[RegisterRouter.scala:87:24]
wire out_rimask_918 = |_out_rimask_T_918; // @[RegisterRouter.scala:87:24]
wire out_wimask_918 = &_out_wimask_T_918; // @[RegisterRouter.scala:87:24]
wire out_romask_918 = |_out_romask_T_918; // @[RegisterRouter.scala:87:24]
wire out_womask_918 = &_out_womask_T_918; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_918 = out_rivalid_1_772 & out_rimask_918; // @[RegisterRouter.scala:87:24]
wire _out_T_8971 = out_f_rivalid_918; // @[RegisterRouter.scala:87:24]
wire out_f_roready_918 = out_roready_1_772 & out_romask_918; // @[RegisterRouter.scala:87:24]
wire _out_T_8972 = out_f_roready_918; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_918 = out_wivalid_1_772 & out_wimask_918; // @[RegisterRouter.scala:87:24]
wire out_f_woready_918 = out_woready_1_772 & out_womask_918; // @[RegisterRouter.scala:87:24]
wire _out_T_8973 = ~out_rimask_918; // @[RegisterRouter.scala:87:24]
wire _out_T_8974 = ~out_wimask_918; // @[RegisterRouter.scala:87:24]
wire _out_T_8975 = ~out_romask_918; // @[RegisterRouter.scala:87:24]
wire _out_T_8976 = ~out_womask_918; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_783 = {hi_58, flags_0_go, _out_prepend_T_783}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_8977 = out_prepend_783; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_8978 = _out_T_8977; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_784 = _out_T_8978; // @[RegisterRouter.scala:87:24]
wire out_rimask_919 = |_out_rimask_T_919; // @[RegisterRouter.scala:87:24]
wire out_wimask_919 = &_out_wimask_T_919; // @[RegisterRouter.scala:87:24]
wire out_romask_919 = |_out_romask_T_919; // @[RegisterRouter.scala:87:24]
wire out_womask_919 = &_out_womask_T_919; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_919 = out_rivalid_1_773 & out_rimask_919; // @[RegisterRouter.scala:87:24]
wire _out_T_8980 = out_f_rivalid_919; // @[RegisterRouter.scala:87:24]
wire out_f_roready_919 = out_roready_1_773 & out_romask_919; // @[RegisterRouter.scala:87:24]
wire _out_T_8981 = out_f_roready_919; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_919 = out_wivalid_1_773 & out_wimask_919; // @[RegisterRouter.scala:87:24]
wire out_f_woready_919 = out_woready_1_773 & out_womask_919; // @[RegisterRouter.scala:87:24]
wire _out_T_8982 = ~out_rimask_919; // @[RegisterRouter.scala:87:24]
wire _out_T_8983 = ~out_wimask_919; // @[RegisterRouter.scala:87:24]
wire _out_T_8984 = ~out_romask_919; // @[RegisterRouter.scala:87:24]
wire _out_T_8985 = ~out_womask_919; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_784 = {hi_59, flags_0_go, _out_prepend_T_784}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_8986 = out_prepend_784; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_8987 = _out_T_8986; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_785 = _out_T_8987; // @[RegisterRouter.scala:87:24]
wire out_rimask_920 = |_out_rimask_T_920; // @[RegisterRouter.scala:87:24]
wire out_wimask_920 = &_out_wimask_T_920; // @[RegisterRouter.scala:87:24]
wire out_romask_920 = |_out_romask_T_920; // @[RegisterRouter.scala:87:24]
wire out_womask_920 = &_out_womask_T_920; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_920 = out_rivalid_1_774 & out_rimask_920; // @[RegisterRouter.scala:87:24]
wire _out_T_8989 = out_f_rivalid_920; // @[RegisterRouter.scala:87:24]
wire out_f_roready_920 = out_roready_1_774 & out_romask_920; // @[RegisterRouter.scala:87:24]
wire _out_T_8990 = out_f_roready_920; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_920 = out_wivalid_1_774 & out_wimask_920; // @[RegisterRouter.scala:87:24]
wire out_f_woready_920 = out_woready_1_774 & out_womask_920; // @[RegisterRouter.scala:87:24]
wire _out_T_8991 = ~out_rimask_920; // @[RegisterRouter.scala:87:24]
wire _out_T_8992 = ~out_wimask_920; // @[RegisterRouter.scala:87:24]
wire _out_T_8993 = ~out_romask_920; // @[RegisterRouter.scala:87:24]
wire _out_T_8994 = ~out_womask_920; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_785 = {hi_60, flags_0_go, _out_prepend_T_785}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_8995 = out_prepend_785; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_8996 = _out_T_8995; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_786 = _out_T_8996; // @[RegisterRouter.scala:87:24]
wire out_rimask_921 = |_out_rimask_T_921; // @[RegisterRouter.scala:87:24]
wire out_wimask_921 = &_out_wimask_T_921; // @[RegisterRouter.scala:87:24]
wire out_romask_921 = |_out_romask_T_921; // @[RegisterRouter.scala:87:24]
wire out_womask_921 = &_out_womask_T_921; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_921 = out_rivalid_1_775 & out_rimask_921; // @[RegisterRouter.scala:87:24]
wire _out_T_8998 = out_f_rivalid_921; // @[RegisterRouter.scala:87:24]
wire out_f_roready_921 = out_roready_1_775 & out_romask_921; // @[RegisterRouter.scala:87:24]
wire _out_T_8999 = out_f_roready_921; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_921 = out_wivalid_1_775 & out_wimask_921; // @[RegisterRouter.scala:87:24]
wire out_f_woready_921 = out_woready_1_775 & out_womask_921; // @[RegisterRouter.scala:87:24]
wire _out_T_9000 = ~out_rimask_921; // @[RegisterRouter.scala:87:24]
wire _out_T_9001 = ~out_wimask_921; // @[RegisterRouter.scala:87:24]
wire _out_T_9002 = ~out_romask_921; // @[RegisterRouter.scala:87:24]
wire _out_T_9003 = ~out_womask_921; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_786 = {hi_61, flags_0_go, _out_prepend_T_786}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_9004 = out_prepend_786; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_9005 = _out_T_9004; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_787 = _out_T_9005; // @[RegisterRouter.scala:87:24]
wire out_rimask_922 = |_out_rimask_T_922; // @[RegisterRouter.scala:87:24]
wire out_wimask_922 = &_out_wimask_T_922; // @[RegisterRouter.scala:87:24]
wire out_romask_922 = |_out_romask_T_922; // @[RegisterRouter.scala:87:24]
wire out_womask_922 = &_out_womask_T_922; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_922 = out_rivalid_1_776 & out_rimask_922; // @[RegisterRouter.scala:87:24]
wire _out_T_9007 = out_f_rivalid_922; // @[RegisterRouter.scala:87:24]
wire out_f_roready_922 = out_roready_1_776 & out_romask_922; // @[RegisterRouter.scala:87:24]
wire _out_T_9008 = out_f_roready_922; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_922 = out_wivalid_1_776 & out_wimask_922; // @[RegisterRouter.scala:87:24]
wire out_f_woready_922 = out_woready_1_776 & out_womask_922; // @[RegisterRouter.scala:87:24]
wire _out_T_9009 = ~out_rimask_922; // @[RegisterRouter.scala:87:24]
wire _out_T_9010 = ~out_wimask_922; // @[RegisterRouter.scala:87:24]
wire _out_T_9011 = ~out_romask_922; // @[RegisterRouter.scala:87:24]
wire _out_T_9012 = ~out_womask_922; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_787 = {hi_62, flags_0_go, _out_prepend_T_787}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_9013 = out_prepend_787; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_9014 = _out_T_9013; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_788 = _out_T_9014; // @[RegisterRouter.scala:87:24]
wire out_rimask_923 = |_out_rimask_T_923; // @[RegisterRouter.scala:87:24]
wire out_wimask_923 = &_out_wimask_T_923; // @[RegisterRouter.scala:87:24]
wire out_romask_923 = |_out_romask_T_923; // @[RegisterRouter.scala:87:24]
wire out_womask_923 = &_out_womask_T_923; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_923 = out_rivalid_1_777 & out_rimask_923; // @[RegisterRouter.scala:87:24]
wire _out_T_9016 = out_f_rivalid_923; // @[RegisterRouter.scala:87:24]
wire out_f_roready_923 = out_roready_1_777 & out_romask_923; // @[RegisterRouter.scala:87:24]
wire _out_T_9017 = out_f_roready_923; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_923 = out_wivalid_1_777 & out_wimask_923; // @[RegisterRouter.scala:87:24]
wire out_f_woready_923 = out_woready_1_777 & out_womask_923; // @[RegisterRouter.scala:87:24]
wire _out_T_9018 = ~out_rimask_923; // @[RegisterRouter.scala:87:24]
wire _out_T_9019 = ~out_wimask_923; // @[RegisterRouter.scala:87:24]
wire _out_T_9020 = ~out_romask_923; // @[RegisterRouter.scala:87:24]
wire _out_T_9021 = ~out_womask_923; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_788 = {hi_63, flags_0_go, _out_prepend_T_788}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_9022 = out_prepend_788; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_9023 = _out_T_9022; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_789 = _out_T_9023; // @[RegisterRouter.scala:87:24]
wire out_rimask_924 = |_out_rimask_T_924; // @[RegisterRouter.scala:87:24]
wire out_wimask_924 = &_out_wimask_T_924; // @[RegisterRouter.scala:87:24]
wire out_romask_924 = |_out_romask_T_924; // @[RegisterRouter.scala:87:24]
wire out_womask_924 = &_out_womask_T_924; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_924 = out_rivalid_1_778 & out_rimask_924; // @[RegisterRouter.scala:87:24]
wire _out_T_9025 = out_f_rivalid_924; // @[RegisterRouter.scala:87:24]
wire out_f_roready_924 = out_roready_1_778 & out_romask_924; // @[RegisterRouter.scala:87:24]
wire _out_T_9026 = out_f_roready_924; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_924 = out_wivalid_1_778 & out_wimask_924; // @[RegisterRouter.scala:87:24]
wire out_f_woready_924 = out_woready_1_778 & out_womask_924; // @[RegisterRouter.scala:87:24]
wire _out_T_9027 = ~out_rimask_924; // @[RegisterRouter.scala:87:24]
wire _out_T_9028 = ~out_wimask_924; // @[RegisterRouter.scala:87:24]
wire _out_T_9029 = ~out_romask_924; // @[RegisterRouter.scala:87:24]
wire _out_T_9030 = ~out_womask_924; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_789 = {hi_64, flags_0_go, _out_prepend_T_789}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_9031 = out_prepend_789; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_9032 = _out_T_9031; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_135 = _out_T_9032; // @[MuxLiteral.scala:49:48]
wire out_rimask_925 = |_out_rimask_T_925; // @[RegisterRouter.scala:87:24]
wire out_wimask_925 = &_out_wimask_T_925; // @[RegisterRouter.scala:87:24]
wire out_romask_925 = |_out_romask_T_925; // @[RegisterRouter.scala:87:24]
wire out_womask_925 = &_out_womask_T_925; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_925 = out_rivalid_1_779 & out_rimask_925; // @[RegisterRouter.scala:87:24]
wire _out_T_9034 = out_f_rivalid_925; // @[RegisterRouter.scala:87:24]
wire out_f_roready_925 = out_roready_1_779 & out_romask_925; // @[RegisterRouter.scala:87:24]
wire _out_T_9035 = out_f_roready_925; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_925 = out_wivalid_1_779 & out_wimask_925; // @[RegisterRouter.scala:87:24]
wire out_f_woready_925 = out_woready_1_779 & out_womask_925; // @[RegisterRouter.scala:87:24]
wire _out_T_9036 = ~out_rimask_925; // @[RegisterRouter.scala:87:24]
wire _out_T_9037 = ~out_wimask_925; // @[RegisterRouter.scala:87:24]
wire _out_T_9038 = ~out_romask_925; // @[RegisterRouter.scala:87:24]
wire _out_T_9039 = ~out_womask_925; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9041 = _out_T_9040; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_790 = _out_T_9041; // @[RegisterRouter.scala:87:24]
wire out_rimask_926 = |_out_rimask_T_926; // @[RegisterRouter.scala:87:24]
wire out_wimask_926 = &_out_wimask_T_926; // @[RegisterRouter.scala:87:24]
wire out_romask_926 = |_out_romask_T_926; // @[RegisterRouter.scala:87:24]
wire out_womask_926 = &_out_womask_T_926; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_926 = out_rivalid_1_780 & out_rimask_926; // @[RegisterRouter.scala:87:24]
wire _out_T_9043 = out_f_rivalid_926; // @[RegisterRouter.scala:87:24]
wire out_f_roready_926 = out_roready_1_780 & out_romask_926; // @[RegisterRouter.scala:87:24]
wire _out_T_9044 = out_f_roready_926; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_926 = out_wivalid_1_780 & out_wimask_926; // @[RegisterRouter.scala:87:24]
wire out_f_woready_926 = out_woready_1_780 & out_womask_926; // @[RegisterRouter.scala:87:24]
wire _out_T_9045 = ~out_rimask_926; // @[RegisterRouter.scala:87:24]
wire _out_T_9046 = ~out_wimask_926; // @[RegisterRouter.scala:87:24]
wire _out_T_9047 = ~out_romask_926; // @[RegisterRouter.scala:87:24]
wire _out_T_9048 = ~out_womask_926; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_790 = {hi_786, flags_0_go, _out_prepend_T_790}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_9049 = out_prepend_790; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_9050 = _out_T_9049; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_791 = _out_T_9050; // @[RegisterRouter.scala:87:24]
wire out_rimask_927 = |_out_rimask_T_927; // @[RegisterRouter.scala:87:24]
wire out_wimask_927 = &_out_wimask_T_927; // @[RegisterRouter.scala:87:24]
wire out_romask_927 = |_out_romask_T_927; // @[RegisterRouter.scala:87:24]
wire out_womask_927 = &_out_womask_T_927; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_927 = out_rivalid_1_781 & out_rimask_927; // @[RegisterRouter.scala:87:24]
wire _out_T_9052 = out_f_rivalid_927; // @[RegisterRouter.scala:87:24]
wire out_f_roready_927 = out_roready_1_781 & out_romask_927; // @[RegisterRouter.scala:87:24]
wire _out_T_9053 = out_f_roready_927; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_927 = out_wivalid_1_781 & out_wimask_927; // @[RegisterRouter.scala:87:24]
wire out_f_woready_927 = out_woready_1_781 & out_womask_927; // @[RegisterRouter.scala:87:24]
wire _out_T_9054 = ~out_rimask_927; // @[RegisterRouter.scala:87:24]
wire _out_T_9055 = ~out_wimask_927; // @[RegisterRouter.scala:87:24]
wire _out_T_9056 = ~out_romask_927; // @[RegisterRouter.scala:87:24]
wire _out_T_9057 = ~out_womask_927; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_791 = {hi_787, flags_0_go, _out_prepend_T_791}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_9058 = out_prepend_791; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_9059 = _out_T_9058; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_792 = _out_T_9059; // @[RegisterRouter.scala:87:24]
wire out_rimask_928 = |_out_rimask_T_928; // @[RegisterRouter.scala:87:24]
wire out_wimask_928 = &_out_wimask_T_928; // @[RegisterRouter.scala:87:24]
wire out_romask_928 = |_out_romask_T_928; // @[RegisterRouter.scala:87:24]
wire out_womask_928 = &_out_womask_T_928; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_928 = out_rivalid_1_782 & out_rimask_928; // @[RegisterRouter.scala:87:24]
wire _out_T_9061 = out_f_rivalid_928; // @[RegisterRouter.scala:87:24]
wire out_f_roready_928 = out_roready_1_782 & out_romask_928; // @[RegisterRouter.scala:87:24]
wire _out_T_9062 = out_f_roready_928; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_928 = out_wivalid_1_782 & out_wimask_928; // @[RegisterRouter.scala:87:24]
wire out_f_woready_928 = out_woready_1_782 & out_womask_928; // @[RegisterRouter.scala:87:24]
wire _out_T_9063 = ~out_rimask_928; // @[RegisterRouter.scala:87:24]
wire _out_T_9064 = ~out_wimask_928; // @[RegisterRouter.scala:87:24]
wire _out_T_9065 = ~out_romask_928; // @[RegisterRouter.scala:87:24]
wire _out_T_9066 = ~out_womask_928; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_792 = {hi_788, flags_0_go, _out_prepend_T_792}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_9067 = out_prepend_792; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_9068 = _out_T_9067; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_793 = _out_T_9068; // @[RegisterRouter.scala:87:24]
wire out_rimask_929 = |_out_rimask_T_929; // @[RegisterRouter.scala:87:24]
wire out_wimask_929 = &_out_wimask_T_929; // @[RegisterRouter.scala:87:24]
wire out_romask_929 = |_out_romask_T_929; // @[RegisterRouter.scala:87:24]
wire out_womask_929 = &_out_womask_T_929; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_929 = out_rivalid_1_783 & out_rimask_929; // @[RegisterRouter.scala:87:24]
wire _out_T_9070 = out_f_rivalid_929; // @[RegisterRouter.scala:87:24]
wire out_f_roready_929 = out_roready_1_783 & out_romask_929; // @[RegisterRouter.scala:87:24]
wire _out_T_9071 = out_f_roready_929; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_929 = out_wivalid_1_783 & out_wimask_929; // @[RegisterRouter.scala:87:24]
wire out_f_woready_929 = out_woready_1_783 & out_womask_929; // @[RegisterRouter.scala:87:24]
wire _out_T_9072 = ~out_rimask_929; // @[RegisterRouter.scala:87:24]
wire _out_T_9073 = ~out_wimask_929; // @[RegisterRouter.scala:87:24]
wire _out_T_9074 = ~out_romask_929; // @[RegisterRouter.scala:87:24]
wire _out_T_9075 = ~out_womask_929; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_793 = {hi_789, flags_0_go, _out_prepend_T_793}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_9076 = out_prepend_793; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_9077 = _out_T_9076; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_794 = _out_T_9077; // @[RegisterRouter.scala:87:24]
wire out_rimask_930 = |_out_rimask_T_930; // @[RegisterRouter.scala:87:24]
wire out_wimask_930 = &_out_wimask_T_930; // @[RegisterRouter.scala:87:24]
wire out_romask_930 = |_out_romask_T_930; // @[RegisterRouter.scala:87:24]
wire out_womask_930 = &_out_womask_T_930; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_930 = out_rivalid_1_784 & out_rimask_930; // @[RegisterRouter.scala:87:24]
wire _out_T_9079 = out_f_rivalid_930; // @[RegisterRouter.scala:87:24]
wire out_f_roready_930 = out_roready_1_784 & out_romask_930; // @[RegisterRouter.scala:87:24]
wire _out_T_9080 = out_f_roready_930; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_930 = out_wivalid_1_784 & out_wimask_930; // @[RegisterRouter.scala:87:24]
wire out_f_woready_930 = out_woready_1_784 & out_womask_930; // @[RegisterRouter.scala:87:24]
wire _out_T_9081 = ~out_rimask_930; // @[RegisterRouter.scala:87:24]
wire _out_T_9082 = ~out_wimask_930; // @[RegisterRouter.scala:87:24]
wire _out_T_9083 = ~out_romask_930; // @[RegisterRouter.scala:87:24]
wire _out_T_9084 = ~out_womask_930; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_794 = {hi_790, flags_0_go, _out_prepend_T_794}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_9085 = out_prepend_794; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_9086 = _out_T_9085; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_795 = _out_T_9086; // @[RegisterRouter.scala:87:24]
wire out_rimask_931 = |_out_rimask_T_931; // @[RegisterRouter.scala:87:24]
wire out_wimask_931 = &_out_wimask_T_931; // @[RegisterRouter.scala:87:24]
wire out_romask_931 = |_out_romask_T_931; // @[RegisterRouter.scala:87:24]
wire out_womask_931 = &_out_womask_T_931; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_931 = out_rivalid_1_785 & out_rimask_931; // @[RegisterRouter.scala:87:24]
wire _out_T_9088 = out_f_rivalid_931; // @[RegisterRouter.scala:87:24]
wire out_f_roready_931 = out_roready_1_785 & out_romask_931; // @[RegisterRouter.scala:87:24]
wire _out_T_9089 = out_f_roready_931; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_931 = out_wivalid_1_785 & out_wimask_931; // @[RegisterRouter.scala:87:24]
wire out_f_woready_931 = out_woready_1_785 & out_womask_931; // @[RegisterRouter.scala:87:24]
wire _out_T_9090 = ~out_rimask_931; // @[RegisterRouter.scala:87:24]
wire _out_T_9091 = ~out_wimask_931; // @[RegisterRouter.scala:87:24]
wire _out_T_9092 = ~out_romask_931; // @[RegisterRouter.scala:87:24]
wire _out_T_9093 = ~out_womask_931; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_795 = {hi_791, flags_0_go, _out_prepend_T_795}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_9094 = out_prepend_795; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_9095 = _out_T_9094; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_796 = _out_T_9095; // @[RegisterRouter.scala:87:24]
wire out_rimask_932 = |_out_rimask_T_932; // @[RegisterRouter.scala:87:24]
wire out_wimask_932 = &_out_wimask_T_932; // @[RegisterRouter.scala:87:24]
wire out_romask_932 = |_out_romask_T_932; // @[RegisterRouter.scala:87:24]
wire out_womask_932 = &_out_womask_T_932; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_932 = out_rivalid_1_786 & out_rimask_932; // @[RegisterRouter.scala:87:24]
wire _out_T_9097 = out_f_rivalid_932; // @[RegisterRouter.scala:87:24]
wire out_f_roready_932 = out_roready_1_786 & out_romask_932; // @[RegisterRouter.scala:87:24]
wire _out_T_9098 = out_f_roready_932; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_932 = out_wivalid_1_786 & out_wimask_932; // @[RegisterRouter.scala:87:24]
wire out_f_woready_932 = out_woready_1_786 & out_womask_932; // @[RegisterRouter.scala:87:24]
wire _out_T_9099 = ~out_rimask_932; // @[RegisterRouter.scala:87:24]
wire _out_T_9100 = ~out_wimask_932; // @[RegisterRouter.scala:87:24]
wire _out_T_9101 = ~out_romask_932; // @[RegisterRouter.scala:87:24]
wire _out_T_9102 = ~out_womask_932; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_796 = {hi_792, flags_0_go, _out_prepend_T_796}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_9103 = out_prepend_796; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_9104 = _out_T_9103; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_226 = _out_T_9104; // @[MuxLiteral.scala:49:48]
wire out_rimask_933 = |_out_rimask_T_933; // @[RegisterRouter.scala:87:24]
wire out_wimask_933 = &_out_wimask_T_933; // @[RegisterRouter.scala:87:24]
wire out_romask_933 = |_out_romask_T_933; // @[RegisterRouter.scala:87:24]
wire out_womask_933 = &_out_womask_T_933; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_933 = out_rivalid_1_787 & out_rimask_933; // @[RegisterRouter.scala:87:24]
wire _out_T_9106 = out_f_rivalid_933; // @[RegisterRouter.scala:87:24]
wire out_f_roready_933 = out_roready_1_787 & out_romask_933; // @[RegisterRouter.scala:87:24]
wire _out_T_9107 = out_f_roready_933; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_933 = out_wivalid_1_787 & out_wimask_933; // @[RegisterRouter.scala:87:24]
wire out_f_woready_933 = out_woready_1_787 & out_womask_933; // @[RegisterRouter.scala:87:24]
wire _out_T_9108 = ~out_rimask_933; // @[RegisterRouter.scala:87:24]
wire _out_T_9109 = ~out_wimask_933; // @[RegisterRouter.scala:87:24]
wire _out_T_9110 = ~out_romask_933; // @[RegisterRouter.scala:87:24]
wire _out_T_9111 = ~out_womask_933; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9113 = _out_T_9112; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_797 = _out_T_9113; // @[RegisterRouter.scala:87:24]
wire out_rimask_934 = |_out_rimask_T_934; // @[RegisterRouter.scala:87:24]
wire out_wimask_934 = &_out_wimask_T_934; // @[RegisterRouter.scala:87:24]
wire out_romask_934 = |_out_romask_T_934; // @[RegisterRouter.scala:87:24]
wire out_womask_934 = &_out_womask_T_934; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_934 = out_rivalid_1_788 & out_rimask_934; // @[RegisterRouter.scala:87:24]
wire _out_T_9115 = out_f_rivalid_934; // @[RegisterRouter.scala:87:24]
wire out_f_roready_934 = out_roready_1_788 & out_romask_934; // @[RegisterRouter.scala:87:24]
wire _out_T_9116 = out_f_roready_934; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_934 = out_wivalid_1_788 & out_wimask_934; // @[RegisterRouter.scala:87:24]
wire out_f_woready_934 = out_woready_1_788 & out_womask_934; // @[RegisterRouter.scala:87:24]
wire _out_T_9117 = ~out_rimask_934; // @[RegisterRouter.scala:87:24]
wire _out_T_9118 = ~out_wimask_934; // @[RegisterRouter.scala:87:24]
wire _out_T_9119 = ~out_romask_934; // @[RegisterRouter.scala:87:24]
wire _out_T_9120 = ~out_womask_934; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_797 = {hi_906, flags_0_go, _out_prepend_T_797}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_9121 = out_prepend_797; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_9122 = _out_T_9121; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_798 = _out_T_9122; // @[RegisterRouter.scala:87:24]
wire out_rimask_935 = |_out_rimask_T_935; // @[RegisterRouter.scala:87:24]
wire out_wimask_935 = &_out_wimask_T_935; // @[RegisterRouter.scala:87:24]
wire out_romask_935 = |_out_romask_T_935; // @[RegisterRouter.scala:87:24]
wire out_womask_935 = &_out_womask_T_935; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_935 = out_rivalid_1_789 & out_rimask_935; // @[RegisterRouter.scala:87:24]
wire _out_T_9124 = out_f_rivalid_935; // @[RegisterRouter.scala:87:24]
wire out_f_roready_935 = out_roready_1_789 & out_romask_935; // @[RegisterRouter.scala:87:24]
wire _out_T_9125 = out_f_roready_935; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_935 = out_wivalid_1_789 & out_wimask_935; // @[RegisterRouter.scala:87:24]
wire out_f_woready_935 = out_woready_1_789 & out_womask_935; // @[RegisterRouter.scala:87:24]
wire _out_T_9126 = ~out_rimask_935; // @[RegisterRouter.scala:87:24]
wire _out_T_9127 = ~out_wimask_935; // @[RegisterRouter.scala:87:24]
wire _out_T_9128 = ~out_romask_935; // @[RegisterRouter.scala:87:24]
wire _out_T_9129 = ~out_womask_935; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_798 = {hi_907, flags_0_go, _out_prepend_T_798}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_9130 = out_prepend_798; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_9131 = _out_T_9130; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_799 = _out_T_9131; // @[RegisterRouter.scala:87:24]
wire out_rimask_936 = |_out_rimask_T_936; // @[RegisterRouter.scala:87:24]
wire out_wimask_936 = &_out_wimask_T_936; // @[RegisterRouter.scala:87:24]
wire out_romask_936 = |_out_romask_T_936; // @[RegisterRouter.scala:87:24]
wire out_womask_936 = &_out_womask_T_936; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_936 = out_rivalid_1_790 & out_rimask_936; // @[RegisterRouter.scala:87:24]
wire _out_T_9133 = out_f_rivalid_936; // @[RegisterRouter.scala:87:24]
wire out_f_roready_936 = out_roready_1_790 & out_romask_936; // @[RegisterRouter.scala:87:24]
wire _out_T_9134 = out_f_roready_936; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_936 = out_wivalid_1_790 & out_wimask_936; // @[RegisterRouter.scala:87:24]
wire out_f_woready_936 = out_woready_1_790 & out_womask_936; // @[RegisterRouter.scala:87:24]
wire _out_T_9135 = ~out_rimask_936; // @[RegisterRouter.scala:87:24]
wire _out_T_9136 = ~out_wimask_936; // @[RegisterRouter.scala:87:24]
wire _out_T_9137 = ~out_romask_936; // @[RegisterRouter.scala:87:24]
wire _out_T_9138 = ~out_womask_936; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_799 = {hi_908, flags_0_go, _out_prepend_T_799}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_9139 = out_prepend_799; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_9140 = _out_T_9139; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_800 = _out_T_9140; // @[RegisterRouter.scala:87:24]
wire out_rimask_937 = |_out_rimask_T_937; // @[RegisterRouter.scala:87:24]
wire out_wimask_937 = &_out_wimask_T_937; // @[RegisterRouter.scala:87:24]
wire out_romask_937 = |_out_romask_T_937; // @[RegisterRouter.scala:87:24]
wire out_womask_937 = &_out_womask_T_937; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_937 = out_rivalid_1_791 & out_rimask_937; // @[RegisterRouter.scala:87:24]
wire _out_T_9142 = out_f_rivalid_937; // @[RegisterRouter.scala:87:24]
wire out_f_roready_937 = out_roready_1_791 & out_romask_937; // @[RegisterRouter.scala:87:24]
wire _out_T_9143 = out_f_roready_937; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_937 = out_wivalid_1_791 & out_wimask_937; // @[RegisterRouter.scala:87:24]
wire out_f_woready_937 = out_woready_1_791 & out_womask_937; // @[RegisterRouter.scala:87:24]
wire _out_T_9144 = ~out_rimask_937; // @[RegisterRouter.scala:87:24]
wire _out_T_9145 = ~out_wimask_937; // @[RegisterRouter.scala:87:24]
wire _out_T_9146 = ~out_romask_937; // @[RegisterRouter.scala:87:24]
wire _out_T_9147 = ~out_womask_937; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_800 = {hi_909, flags_0_go, _out_prepend_T_800}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_9148 = out_prepend_800; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_9149 = _out_T_9148; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_801 = _out_T_9149; // @[RegisterRouter.scala:87:24]
wire out_rimask_938 = |_out_rimask_T_938; // @[RegisterRouter.scala:87:24]
wire out_wimask_938 = &_out_wimask_T_938; // @[RegisterRouter.scala:87:24]
wire out_romask_938 = |_out_romask_T_938; // @[RegisterRouter.scala:87:24]
wire out_womask_938 = &_out_womask_T_938; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_938 = out_rivalid_1_792 & out_rimask_938; // @[RegisterRouter.scala:87:24]
wire _out_T_9151 = out_f_rivalid_938; // @[RegisterRouter.scala:87:24]
wire out_f_roready_938 = out_roready_1_792 & out_romask_938; // @[RegisterRouter.scala:87:24]
wire _out_T_9152 = out_f_roready_938; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_938 = out_wivalid_1_792 & out_wimask_938; // @[RegisterRouter.scala:87:24]
wire out_f_woready_938 = out_woready_1_792 & out_womask_938; // @[RegisterRouter.scala:87:24]
wire _out_T_9153 = ~out_rimask_938; // @[RegisterRouter.scala:87:24]
wire _out_T_9154 = ~out_wimask_938; // @[RegisterRouter.scala:87:24]
wire _out_T_9155 = ~out_romask_938; // @[RegisterRouter.scala:87:24]
wire _out_T_9156 = ~out_womask_938; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_801 = {hi_910, flags_0_go, _out_prepend_T_801}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_9157 = out_prepend_801; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_9158 = _out_T_9157; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_802 = _out_T_9158; // @[RegisterRouter.scala:87:24]
wire out_rimask_939 = |_out_rimask_T_939; // @[RegisterRouter.scala:87:24]
wire out_wimask_939 = &_out_wimask_T_939; // @[RegisterRouter.scala:87:24]
wire out_romask_939 = |_out_romask_T_939; // @[RegisterRouter.scala:87:24]
wire out_womask_939 = &_out_womask_T_939; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_939 = out_rivalid_1_793 & out_rimask_939; // @[RegisterRouter.scala:87:24]
wire _out_T_9160 = out_f_rivalid_939; // @[RegisterRouter.scala:87:24]
wire out_f_roready_939 = out_roready_1_793 & out_romask_939; // @[RegisterRouter.scala:87:24]
wire _out_T_9161 = out_f_roready_939; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_939 = out_wivalid_1_793 & out_wimask_939; // @[RegisterRouter.scala:87:24]
wire out_f_woready_939 = out_woready_1_793 & out_womask_939; // @[RegisterRouter.scala:87:24]
wire _out_T_9162 = ~out_rimask_939; // @[RegisterRouter.scala:87:24]
wire _out_T_9163 = ~out_wimask_939; // @[RegisterRouter.scala:87:24]
wire _out_T_9164 = ~out_romask_939; // @[RegisterRouter.scala:87:24]
wire _out_T_9165 = ~out_womask_939; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_802 = {hi_911, flags_0_go, _out_prepend_T_802}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_9166 = out_prepend_802; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_9167 = _out_T_9166; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_803 = _out_T_9167; // @[RegisterRouter.scala:87:24]
wire out_rimask_940 = |_out_rimask_T_940; // @[RegisterRouter.scala:87:24]
wire out_wimask_940 = &_out_wimask_T_940; // @[RegisterRouter.scala:87:24]
wire out_romask_940 = |_out_romask_T_940; // @[RegisterRouter.scala:87:24]
wire out_womask_940 = &_out_womask_T_940; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_940 = out_rivalid_1_794 & out_rimask_940; // @[RegisterRouter.scala:87:24]
wire _out_T_9169 = out_f_rivalid_940; // @[RegisterRouter.scala:87:24]
wire out_f_roready_940 = out_roready_1_794 & out_romask_940; // @[RegisterRouter.scala:87:24]
wire _out_T_9170 = out_f_roready_940; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_940 = out_wivalid_1_794 & out_wimask_940; // @[RegisterRouter.scala:87:24]
wire out_f_woready_940 = out_woready_1_794 & out_womask_940; // @[RegisterRouter.scala:87:24]
wire _out_T_9171 = ~out_rimask_940; // @[RegisterRouter.scala:87:24]
wire _out_T_9172 = ~out_wimask_940; // @[RegisterRouter.scala:87:24]
wire _out_T_9173 = ~out_romask_940; // @[RegisterRouter.scala:87:24]
wire _out_T_9174 = ~out_womask_940; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_803 = {hi_912, flags_0_go, _out_prepend_T_803}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_9175 = out_prepend_803; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_9176 = _out_T_9175; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_241 = _out_T_9176; // @[MuxLiteral.scala:49:48]
wire out_rimask_941 = |_out_rimask_T_941; // @[RegisterRouter.scala:87:24]
wire out_wimask_941 = &_out_wimask_T_941; // @[RegisterRouter.scala:87:24]
wire out_romask_941 = |_out_romask_T_941; // @[RegisterRouter.scala:87:24]
wire out_womask_941 = &_out_womask_T_941; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_941 = out_rivalid_1_795 & out_rimask_941; // @[RegisterRouter.scala:87:24]
wire _out_T_9178 = out_f_rivalid_941; // @[RegisterRouter.scala:87:24]
wire out_f_roready_941 = out_roready_1_795 & out_romask_941; // @[RegisterRouter.scala:87:24]
wire _out_T_9179 = out_f_roready_941; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_941 = out_wivalid_1_795 & out_wimask_941; // @[RegisterRouter.scala:87:24]
wire out_f_woready_941 = out_woready_1_795 & out_womask_941; // @[RegisterRouter.scala:87:24]
wire _out_T_9180 = ~out_rimask_941; // @[RegisterRouter.scala:87:24]
wire _out_T_9181 = ~out_wimask_941; // @[RegisterRouter.scala:87:24]
wire _out_T_9182 = ~out_romask_941; // @[RegisterRouter.scala:87:24]
wire _out_T_9183 = ~out_womask_941; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9185 = _out_T_9184; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_804 = _out_T_9185; // @[RegisterRouter.scala:87:24]
wire out_rimask_942 = |_out_rimask_T_942; // @[RegisterRouter.scala:87:24]
wire out_wimask_942 = &_out_wimask_T_942; // @[RegisterRouter.scala:87:24]
wire out_romask_942 = |_out_romask_T_942; // @[RegisterRouter.scala:87:24]
wire out_womask_942 = &_out_womask_T_942; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_942 = out_rivalid_1_796 & out_rimask_942; // @[RegisterRouter.scala:87:24]
wire _out_T_9187 = out_f_rivalid_942; // @[RegisterRouter.scala:87:24]
wire out_f_roready_942 = out_roready_1_796 & out_romask_942; // @[RegisterRouter.scala:87:24]
wire _out_T_9188 = out_f_roready_942; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_942 = out_wivalid_1_796 & out_wimask_942; // @[RegisterRouter.scala:87:24]
wire out_f_woready_942 = out_woready_1_796 & out_womask_942; // @[RegisterRouter.scala:87:24]
wire _out_T_9189 = ~out_rimask_942; // @[RegisterRouter.scala:87:24]
wire _out_T_9190 = ~out_wimask_942; // @[RegisterRouter.scala:87:24]
wire _out_T_9191 = ~out_romask_942; // @[RegisterRouter.scala:87:24]
wire _out_T_9192 = ~out_womask_942; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_804 = {hi_314, flags_0_go, _out_prepend_T_804}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_9193 = out_prepend_804; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_9194 = _out_T_9193; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_805 = _out_T_9194; // @[RegisterRouter.scala:87:24]
wire out_rimask_943 = |_out_rimask_T_943; // @[RegisterRouter.scala:87:24]
wire out_wimask_943 = &_out_wimask_T_943; // @[RegisterRouter.scala:87:24]
wire out_romask_943 = |_out_romask_T_943; // @[RegisterRouter.scala:87:24]
wire out_womask_943 = &_out_womask_T_943; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_943 = out_rivalid_1_797 & out_rimask_943; // @[RegisterRouter.scala:87:24]
wire _out_T_9196 = out_f_rivalid_943; // @[RegisterRouter.scala:87:24]
wire out_f_roready_943 = out_roready_1_797 & out_romask_943; // @[RegisterRouter.scala:87:24]
wire _out_T_9197 = out_f_roready_943; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_943 = out_wivalid_1_797 & out_wimask_943; // @[RegisterRouter.scala:87:24]
wire out_f_woready_943 = out_woready_1_797 & out_womask_943; // @[RegisterRouter.scala:87:24]
wire _out_T_9198 = ~out_rimask_943; // @[RegisterRouter.scala:87:24]
wire _out_T_9199 = ~out_wimask_943; // @[RegisterRouter.scala:87:24]
wire _out_T_9200 = ~out_romask_943; // @[RegisterRouter.scala:87:24]
wire _out_T_9201 = ~out_womask_943; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_805 = {hi_315, flags_0_go, _out_prepend_T_805}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_9202 = out_prepend_805; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_9203 = _out_T_9202; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_806 = _out_T_9203; // @[RegisterRouter.scala:87:24]
wire out_rimask_944 = |_out_rimask_T_944; // @[RegisterRouter.scala:87:24]
wire out_wimask_944 = &_out_wimask_T_944; // @[RegisterRouter.scala:87:24]
wire out_romask_944 = |_out_romask_T_944; // @[RegisterRouter.scala:87:24]
wire out_womask_944 = &_out_womask_T_944; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_944 = out_rivalid_1_798 & out_rimask_944; // @[RegisterRouter.scala:87:24]
wire _out_T_9205 = out_f_rivalid_944; // @[RegisterRouter.scala:87:24]
wire out_f_roready_944 = out_roready_1_798 & out_romask_944; // @[RegisterRouter.scala:87:24]
wire _out_T_9206 = out_f_roready_944; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_944 = out_wivalid_1_798 & out_wimask_944; // @[RegisterRouter.scala:87:24]
wire out_f_woready_944 = out_woready_1_798 & out_womask_944; // @[RegisterRouter.scala:87:24]
wire _out_T_9207 = ~out_rimask_944; // @[RegisterRouter.scala:87:24]
wire _out_T_9208 = ~out_wimask_944; // @[RegisterRouter.scala:87:24]
wire _out_T_9209 = ~out_romask_944; // @[RegisterRouter.scala:87:24]
wire _out_T_9210 = ~out_womask_944; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_806 = {hi_316, flags_0_go, _out_prepend_T_806}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_9211 = out_prepend_806; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_9212 = _out_T_9211; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_807 = _out_T_9212; // @[RegisterRouter.scala:87:24]
wire out_rimask_945 = |_out_rimask_T_945; // @[RegisterRouter.scala:87:24]
wire out_wimask_945 = &_out_wimask_T_945; // @[RegisterRouter.scala:87:24]
wire out_romask_945 = |_out_romask_T_945; // @[RegisterRouter.scala:87:24]
wire out_womask_945 = &_out_womask_T_945; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_945 = out_rivalid_1_799 & out_rimask_945; // @[RegisterRouter.scala:87:24]
wire _out_T_9214 = out_f_rivalid_945; // @[RegisterRouter.scala:87:24]
wire out_f_roready_945 = out_roready_1_799 & out_romask_945; // @[RegisterRouter.scala:87:24]
wire _out_T_9215 = out_f_roready_945; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_945 = out_wivalid_1_799 & out_wimask_945; // @[RegisterRouter.scala:87:24]
wire out_f_woready_945 = out_woready_1_799 & out_womask_945; // @[RegisterRouter.scala:87:24]
wire _out_T_9216 = ~out_rimask_945; // @[RegisterRouter.scala:87:24]
wire _out_T_9217 = ~out_wimask_945; // @[RegisterRouter.scala:87:24]
wire _out_T_9218 = ~out_romask_945; // @[RegisterRouter.scala:87:24]
wire _out_T_9219 = ~out_womask_945; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_807 = {hi_317, flags_0_go, _out_prepend_T_807}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_9220 = out_prepend_807; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_9221 = _out_T_9220; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_808 = _out_T_9221; // @[RegisterRouter.scala:87:24]
wire out_rimask_946 = |_out_rimask_T_946; // @[RegisterRouter.scala:87:24]
wire out_wimask_946 = &_out_wimask_T_946; // @[RegisterRouter.scala:87:24]
wire out_romask_946 = |_out_romask_T_946; // @[RegisterRouter.scala:87:24]
wire out_womask_946 = &_out_womask_T_946; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_946 = out_rivalid_1_800 & out_rimask_946; // @[RegisterRouter.scala:87:24]
wire _out_T_9223 = out_f_rivalid_946; // @[RegisterRouter.scala:87:24]
wire out_f_roready_946 = out_roready_1_800 & out_romask_946; // @[RegisterRouter.scala:87:24]
wire _out_T_9224 = out_f_roready_946; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_946 = out_wivalid_1_800 & out_wimask_946; // @[RegisterRouter.scala:87:24]
wire out_f_woready_946 = out_woready_1_800 & out_womask_946; // @[RegisterRouter.scala:87:24]
wire _out_T_9225 = ~out_rimask_946; // @[RegisterRouter.scala:87:24]
wire _out_T_9226 = ~out_wimask_946; // @[RegisterRouter.scala:87:24]
wire _out_T_9227 = ~out_romask_946; // @[RegisterRouter.scala:87:24]
wire _out_T_9228 = ~out_womask_946; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_808 = {hi_318, flags_0_go, _out_prepend_T_808}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_9229 = out_prepend_808; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_9230 = _out_T_9229; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_809 = _out_T_9230; // @[RegisterRouter.scala:87:24]
wire out_rimask_947 = |_out_rimask_T_947; // @[RegisterRouter.scala:87:24]
wire out_wimask_947 = &_out_wimask_T_947; // @[RegisterRouter.scala:87:24]
wire out_romask_947 = |_out_romask_T_947; // @[RegisterRouter.scala:87:24]
wire out_womask_947 = &_out_womask_T_947; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_947 = out_rivalid_1_801 & out_rimask_947; // @[RegisterRouter.scala:87:24]
wire _out_T_9232 = out_f_rivalid_947; // @[RegisterRouter.scala:87:24]
wire out_f_roready_947 = out_roready_1_801 & out_romask_947; // @[RegisterRouter.scala:87:24]
wire _out_T_9233 = out_f_roready_947; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_947 = out_wivalid_1_801 & out_wimask_947; // @[RegisterRouter.scala:87:24]
wire out_f_woready_947 = out_woready_1_801 & out_womask_947; // @[RegisterRouter.scala:87:24]
wire _out_T_9234 = ~out_rimask_947; // @[RegisterRouter.scala:87:24]
wire _out_T_9235 = ~out_wimask_947; // @[RegisterRouter.scala:87:24]
wire _out_T_9236 = ~out_romask_947; // @[RegisterRouter.scala:87:24]
wire _out_T_9237 = ~out_womask_947; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_809 = {hi_319, flags_0_go, _out_prepend_T_809}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_9238 = out_prepend_809; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_9239 = _out_T_9238; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_810 = _out_T_9239; // @[RegisterRouter.scala:87:24]
wire out_rimask_948 = |_out_rimask_T_948; // @[RegisterRouter.scala:87:24]
wire out_wimask_948 = &_out_wimask_T_948; // @[RegisterRouter.scala:87:24]
wire out_romask_948 = |_out_romask_T_948; // @[RegisterRouter.scala:87:24]
wire out_womask_948 = &_out_womask_T_948; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_948 = out_rivalid_1_802 & out_rimask_948; // @[RegisterRouter.scala:87:24]
wire _out_T_9241 = out_f_rivalid_948; // @[RegisterRouter.scala:87:24]
wire out_f_roready_948 = out_roready_1_802 & out_romask_948; // @[RegisterRouter.scala:87:24]
wire _out_T_9242 = out_f_roready_948; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_948 = out_wivalid_1_802 & out_wimask_948; // @[RegisterRouter.scala:87:24]
wire out_f_woready_948 = out_woready_1_802 & out_womask_948; // @[RegisterRouter.scala:87:24]
wire _out_T_9243 = ~out_rimask_948; // @[RegisterRouter.scala:87:24]
wire _out_T_9244 = ~out_wimask_948; // @[RegisterRouter.scala:87:24]
wire _out_T_9245 = ~out_romask_948; // @[RegisterRouter.scala:87:24]
wire _out_T_9246 = ~out_womask_948; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_810 = {hi_320, flags_0_go, _out_prepend_T_810}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_9247 = out_prepend_810; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_9248 = _out_T_9247; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_167 = _out_T_9248; // @[MuxLiteral.scala:49:48]
wire out_rimask_949 = |_out_rimask_T_949; // @[RegisterRouter.scala:87:24]
wire out_wimask_949 = &_out_wimask_T_949; // @[RegisterRouter.scala:87:24]
wire out_romask_949 = |_out_romask_T_949; // @[RegisterRouter.scala:87:24]
wire out_womask_949 = &_out_womask_T_949; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_949 = out_rivalid_1_803 & out_rimask_949; // @[RegisterRouter.scala:87:24]
wire _out_T_9250 = out_f_rivalid_949; // @[RegisterRouter.scala:87:24]
wire out_f_roready_949 = out_roready_1_803 & out_romask_949; // @[RegisterRouter.scala:87:24]
wire _out_T_9251 = out_f_roready_949; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_949 = out_wivalid_1_803 & out_wimask_949; // @[RegisterRouter.scala:87:24]
wire out_f_woready_949 = out_woready_1_803 & out_womask_949; // @[RegisterRouter.scala:87:24]
wire _out_T_9252 = ~out_rimask_949; // @[RegisterRouter.scala:87:24]
wire _out_T_9253 = ~out_wimask_949; // @[RegisterRouter.scala:87:24]
wire _out_T_9254 = ~out_romask_949; // @[RegisterRouter.scala:87:24]
wire _out_T_9255 = ~out_womask_949; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9257 = _out_T_9256; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_811 = _out_T_9257; // @[RegisterRouter.scala:87:24]
wire out_rimask_950 = |_out_rimask_T_950; // @[RegisterRouter.scala:87:24]
wire out_wimask_950 = &_out_wimask_T_950; // @[RegisterRouter.scala:87:24]
wire out_romask_950 = |_out_romask_T_950; // @[RegisterRouter.scala:87:24]
wire out_womask_950 = &_out_womask_T_950; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_950 = out_rivalid_1_804 & out_rimask_950; // @[RegisterRouter.scala:87:24]
wire _out_T_9259 = out_f_rivalid_950; // @[RegisterRouter.scala:87:24]
wire out_f_roready_950 = out_roready_1_804 & out_romask_950; // @[RegisterRouter.scala:87:24]
wire _out_T_9260 = out_f_roready_950; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_950 = out_wivalid_1_804 & out_wimask_950; // @[RegisterRouter.scala:87:24]
wire out_f_woready_950 = out_woready_1_804 & out_womask_950; // @[RegisterRouter.scala:87:24]
wire _out_T_9261 = ~out_rimask_950; // @[RegisterRouter.scala:87:24]
wire _out_T_9262 = ~out_wimask_950; // @[RegisterRouter.scala:87:24]
wire _out_T_9263 = ~out_romask_950; // @[RegisterRouter.scala:87:24]
wire _out_T_9264 = ~out_womask_950; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_811 = {hi_274, flags_0_go, _out_prepend_T_811}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_9265 = out_prepend_811; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_9266 = _out_T_9265; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_812 = _out_T_9266; // @[RegisterRouter.scala:87:24]
wire out_rimask_951 = |_out_rimask_T_951; // @[RegisterRouter.scala:87:24]
wire out_wimask_951 = &_out_wimask_T_951; // @[RegisterRouter.scala:87:24]
wire out_romask_951 = |_out_romask_T_951; // @[RegisterRouter.scala:87:24]
wire out_womask_951 = &_out_womask_T_951; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_951 = out_rivalid_1_805 & out_rimask_951; // @[RegisterRouter.scala:87:24]
wire _out_T_9268 = out_f_rivalid_951; // @[RegisterRouter.scala:87:24]
wire out_f_roready_951 = out_roready_1_805 & out_romask_951; // @[RegisterRouter.scala:87:24]
wire _out_T_9269 = out_f_roready_951; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_951 = out_wivalid_1_805 & out_wimask_951; // @[RegisterRouter.scala:87:24]
wire out_f_woready_951 = out_woready_1_805 & out_womask_951; // @[RegisterRouter.scala:87:24]
wire _out_T_9270 = ~out_rimask_951; // @[RegisterRouter.scala:87:24]
wire _out_T_9271 = ~out_wimask_951; // @[RegisterRouter.scala:87:24]
wire _out_T_9272 = ~out_romask_951; // @[RegisterRouter.scala:87:24]
wire _out_T_9273 = ~out_womask_951; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_812 = {hi_275, flags_0_go, _out_prepend_T_812}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_9274 = out_prepend_812; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_9275 = _out_T_9274; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_813 = _out_T_9275; // @[RegisterRouter.scala:87:24]
wire out_rimask_952 = |_out_rimask_T_952; // @[RegisterRouter.scala:87:24]
wire out_wimask_952 = &_out_wimask_T_952; // @[RegisterRouter.scala:87:24]
wire out_romask_952 = |_out_romask_T_952; // @[RegisterRouter.scala:87:24]
wire out_womask_952 = &_out_womask_T_952; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_952 = out_rivalid_1_806 & out_rimask_952; // @[RegisterRouter.scala:87:24]
wire _out_T_9277 = out_f_rivalid_952; // @[RegisterRouter.scala:87:24]
wire out_f_roready_952 = out_roready_1_806 & out_romask_952; // @[RegisterRouter.scala:87:24]
wire _out_T_9278 = out_f_roready_952; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_952 = out_wivalid_1_806 & out_wimask_952; // @[RegisterRouter.scala:87:24]
wire out_f_woready_952 = out_woready_1_806 & out_womask_952; // @[RegisterRouter.scala:87:24]
wire _out_T_9279 = ~out_rimask_952; // @[RegisterRouter.scala:87:24]
wire _out_T_9280 = ~out_wimask_952; // @[RegisterRouter.scala:87:24]
wire _out_T_9281 = ~out_romask_952; // @[RegisterRouter.scala:87:24]
wire _out_T_9282 = ~out_womask_952; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_813 = {hi_276, flags_0_go, _out_prepend_T_813}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_9283 = out_prepend_813; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_9284 = _out_T_9283; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_814 = _out_T_9284; // @[RegisterRouter.scala:87:24]
wire out_rimask_953 = |_out_rimask_T_953; // @[RegisterRouter.scala:87:24]
wire out_wimask_953 = &_out_wimask_T_953; // @[RegisterRouter.scala:87:24]
wire out_romask_953 = |_out_romask_T_953; // @[RegisterRouter.scala:87:24]
wire out_womask_953 = &_out_womask_T_953; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_953 = out_rivalid_1_807 & out_rimask_953; // @[RegisterRouter.scala:87:24]
wire _out_T_9286 = out_f_rivalid_953; // @[RegisterRouter.scala:87:24]
wire out_f_roready_953 = out_roready_1_807 & out_romask_953; // @[RegisterRouter.scala:87:24]
wire _out_T_9287 = out_f_roready_953; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_953 = out_wivalid_1_807 & out_wimask_953; // @[RegisterRouter.scala:87:24]
wire out_f_woready_953 = out_woready_1_807 & out_womask_953; // @[RegisterRouter.scala:87:24]
wire _out_T_9288 = ~out_rimask_953; // @[RegisterRouter.scala:87:24]
wire _out_T_9289 = ~out_wimask_953; // @[RegisterRouter.scala:87:24]
wire _out_T_9290 = ~out_romask_953; // @[RegisterRouter.scala:87:24]
wire _out_T_9291 = ~out_womask_953; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_814 = {hi_277, flags_0_go, _out_prepend_T_814}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_9292 = out_prepend_814; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_9293 = _out_T_9292; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_815 = _out_T_9293; // @[RegisterRouter.scala:87:24]
wire out_rimask_954 = |_out_rimask_T_954; // @[RegisterRouter.scala:87:24]
wire out_wimask_954 = &_out_wimask_T_954; // @[RegisterRouter.scala:87:24]
wire out_romask_954 = |_out_romask_T_954; // @[RegisterRouter.scala:87:24]
wire out_womask_954 = &_out_womask_T_954; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_954 = out_rivalid_1_808 & out_rimask_954; // @[RegisterRouter.scala:87:24]
wire _out_T_9295 = out_f_rivalid_954; // @[RegisterRouter.scala:87:24]
wire out_f_roready_954 = out_roready_1_808 & out_romask_954; // @[RegisterRouter.scala:87:24]
wire _out_T_9296 = out_f_roready_954; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_954 = out_wivalid_1_808 & out_wimask_954; // @[RegisterRouter.scala:87:24]
wire out_f_woready_954 = out_woready_1_808 & out_womask_954; // @[RegisterRouter.scala:87:24]
wire _out_T_9297 = ~out_rimask_954; // @[RegisterRouter.scala:87:24]
wire _out_T_9298 = ~out_wimask_954; // @[RegisterRouter.scala:87:24]
wire _out_T_9299 = ~out_romask_954; // @[RegisterRouter.scala:87:24]
wire _out_T_9300 = ~out_womask_954; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_815 = {hi_278, flags_0_go, _out_prepend_T_815}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_9301 = out_prepend_815; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_9302 = _out_T_9301; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_816 = _out_T_9302; // @[RegisterRouter.scala:87:24]
wire out_rimask_955 = |_out_rimask_T_955; // @[RegisterRouter.scala:87:24]
wire out_wimask_955 = &_out_wimask_T_955; // @[RegisterRouter.scala:87:24]
wire out_romask_955 = |_out_romask_T_955; // @[RegisterRouter.scala:87:24]
wire out_womask_955 = &_out_womask_T_955; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_955 = out_rivalid_1_809 & out_rimask_955; // @[RegisterRouter.scala:87:24]
wire _out_T_9304 = out_f_rivalid_955; // @[RegisterRouter.scala:87:24]
wire out_f_roready_955 = out_roready_1_809 & out_romask_955; // @[RegisterRouter.scala:87:24]
wire _out_T_9305 = out_f_roready_955; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_955 = out_wivalid_1_809 & out_wimask_955; // @[RegisterRouter.scala:87:24]
wire out_f_woready_955 = out_woready_1_809 & out_womask_955; // @[RegisterRouter.scala:87:24]
wire _out_T_9306 = ~out_rimask_955; // @[RegisterRouter.scala:87:24]
wire _out_T_9307 = ~out_wimask_955; // @[RegisterRouter.scala:87:24]
wire _out_T_9308 = ~out_romask_955; // @[RegisterRouter.scala:87:24]
wire _out_T_9309 = ~out_womask_955; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_816 = {hi_279, flags_0_go, _out_prepend_T_816}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_9310 = out_prepend_816; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_9311 = _out_T_9310; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_817 = _out_T_9311; // @[RegisterRouter.scala:87:24]
wire out_rimask_956 = |_out_rimask_T_956; // @[RegisterRouter.scala:87:24]
wire out_wimask_956 = &_out_wimask_T_956; // @[RegisterRouter.scala:87:24]
wire out_romask_956 = |_out_romask_T_956; // @[RegisterRouter.scala:87:24]
wire out_womask_956 = &_out_womask_T_956; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_956 = out_rivalid_1_810 & out_rimask_956; // @[RegisterRouter.scala:87:24]
wire _out_T_9313 = out_f_rivalid_956; // @[RegisterRouter.scala:87:24]
wire out_f_roready_956 = out_roready_1_810 & out_romask_956; // @[RegisterRouter.scala:87:24]
wire _out_T_9314 = out_f_roready_956; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_956 = out_wivalid_1_810 & out_wimask_956; // @[RegisterRouter.scala:87:24]
wire out_f_woready_956 = out_woready_1_810 & out_womask_956; // @[RegisterRouter.scala:87:24]
wire _out_T_9315 = ~out_rimask_956; // @[RegisterRouter.scala:87:24]
wire _out_T_9316 = ~out_wimask_956; // @[RegisterRouter.scala:87:24]
wire _out_T_9317 = ~out_romask_956; // @[RegisterRouter.scala:87:24]
wire _out_T_9318 = ~out_womask_956; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_817 = {hi_280, flags_0_go, _out_prepend_T_817}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_9319 = out_prepend_817; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_9320 = _out_T_9319; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_162 = _out_T_9320; // @[MuxLiteral.scala:49:48]
wire out_rimask_957 = |_out_rimask_T_957; // @[RegisterRouter.scala:87:24]
wire out_wimask_957 = &_out_wimask_T_957; // @[RegisterRouter.scala:87:24]
wire out_romask_957 = |_out_romask_T_957; // @[RegisterRouter.scala:87:24]
wire out_womask_957 = &_out_womask_T_957; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_957 = out_rivalid_1_811 & out_rimask_957; // @[RegisterRouter.scala:87:24]
wire _out_T_9322 = out_f_rivalid_957; // @[RegisterRouter.scala:87:24]
wire out_f_roready_957 = out_roready_1_811 & out_romask_957; // @[RegisterRouter.scala:87:24]
wire _out_T_9323 = out_f_roready_957; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_957 = out_wivalid_1_811 & out_wimask_957; // @[RegisterRouter.scala:87:24]
wire out_f_woready_957 = out_woready_1_811 & out_womask_957; // @[RegisterRouter.scala:87:24]
wire _out_T_9324 = ~out_rimask_957; // @[RegisterRouter.scala:87:24]
wire _out_T_9325 = ~out_wimask_957; // @[RegisterRouter.scala:87:24]
wire _out_T_9326 = ~out_romask_957; // @[RegisterRouter.scala:87:24]
wire _out_T_9327 = ~out_womask_957; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9329 = _out_T_9328; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_818 = _out_T_9329; // @[RegisterRouter.scala:87:24]
wire out_rimask_958 = |_out_rimask_T_958; // @[RegisterRouter.scala:87:24]
wire out_wimask_958 = &_out_wimask_T_958; // @[RegisterRouter.scala:87:24]
wire out_romask_958 = |_out_romask_T_958; // @[RegisterRouter.scala:87:24]
wire out_womask_958 = &_out_womask_T_958; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_958 = out_rivalid_1_812 & out_rimask_958; // @[RegisterRouter.scala:87:24]
wire _out_T_9331 = out_f_rivalid_958; // @[RegisterRouter.scala:87:24]
wire out_f_roready_958 = out_roready_1_812 & out_romask_958; // @[RegisterRouter.scala:87:24]
wire _out_T_9332 = out_f_roready_958; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_958 = out_wivalid_1_812 & out_wimask_958; // @[RegisterRouter.scala:87:24]
wire out_f_woready_958 = out_woready_1_812 & out_womask_958; // @[RegisterRouter.scala:87:24]
wire _out_T_9333 = ~out_rimask_958; // @[RegisterRouter.scala:87:24]
wire _out_T_9334 = ~out_wimask_958; // @[RegisterRouter.scala:87:24]
wire _out_T_9335 = ~out_romask_958; // @[RegisterRouter.scala:87:24]
wire _out_T_9336 = ~out_womask_958; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_818 = {hi_1018, flags_0_go, _out_prepend_T_818}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_9337 = out_prepend_818; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_9338 = _out_T_9337; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_819 = _out_T_9338; // @[RegisterRouter.scala:87:24]
wire out_rimask_959 = |_out_rimask_T_959; // @[RegisterRouter.scala:87:24]
wire out_wimask_959 = &_out_wimask_T_959; // @[RegisterRouter.scala:87:24]
wire out_romask_959 = |_out_romask_T_959; // @[RegisterRouter.scala:87:24]
wire out_womask_959 = &_out_womask_T_959; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_959 = out_rivalid_1_813 & out_rimask_959; // @[RegisterRouter.scala:87:24]
wire _out_T_9340 = out_f_rivalid_959; // @[RegisterRouter.scala:87:24]
wire out_f_roready_959 = out_roready_1_813 & out_romask_959; // @[RegisterRouter.scala:87:24]
wire _out_T_9341 = out_f_roready_959; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_959 = out_wivalid_1_813 & out_wimask_959; // @[RegisterRouter.scala:87:24]
wire out_f_woready_959 = out_woready_1_813 & out_womask_959; // @[RegisterRouter.scala:87:24]
wire _out_T_9342 = ~out_rimask_959; // @[RegisterRouter.scala:87:24]
wire _out_T_9343 = ~out_wimask_959; // @[RegisterRouter.scala:87:24]
wire _out_T_9344 = ~out_romask_959; // @[RegisterRouter.scala:87:24]
wire _out_T_9345 = ~out_womask_959; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_819 = {hi_1019, flags_0_go, _out_prepend_T_819}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_9346 = out_prepend_819; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_9347 = _out_T_9346; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_820 = _out_T_9347; // @[RegisterRouter.scala:87:24]
wire out_rimask_960 = |_out_rimask_T_960; // @[RegisterRouter.scala:87:24]
wire out_wimask_960 = &_out_wimask_T_960; // @[RegisterRouter.scala:87:24]
wire out_romask_960 = |_out_romask_T_960; // @[RegisterRouter.scala:87:24]
wire out_womask_960 = &_out_womask_T_960; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_960 = out_rivalid_1_814 & out_rimask_960; // @[RegisterRouter.scala:87:24]
wire _out_T_9349 = out_f_rivalid_960; // @[RegisterRouter.scala:87:24]
wire out_f_roready_960 = out_roready_1_814 & out_romask_960; // @[RegisterRouter.scala:87:24]
wire _out_T_9350 = out_f_roready_960; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_960 = out_wivalid_1_814 & out_wimask_960; // @[RegisterRouter.scala:87:24]
wire out_f_woready_960 = out_woready_1_814 & out_womask_960; // @[RegisterRouter.scala:87:24]
wire _out_T_9351 = ~out_rimask_960; // @[RegisterRouter.scala:87:24]
wire _out_T_9352 = ~out_wimask_960; // @[RegisterRouter.scala:87:24]
wire _out_T_9353 = ~out_romask_960; // @[RegisterRouter.scala:87:24]
wire _out_T_9354 = ~out_womask_960; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_820 = {hi_1020, flags_0_go, _out_prepend_T_820}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_9355 = out_prepend_820; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_9356 = _out_T_9355; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_821 = _out_T_9356; // @[RegisterRouter.scala:87:24]
wire out_rimask_961 = |_out_rimask_T_961; // @[RegisterRouter.scala:87:24]
wire out_wimask_961 = &_out_wimask_T_961; // @[RegisterRouter.scala:87:24]
wire out_romask_961 = |_out_romask_T_961; // @[RegisterRouter.scala:87:24]
wire out_womask_961 = &_out_womask_T_961; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_961 = out_rivalid_1_815 & out_rimask_961; // @[RegisterRouter.scala:87:24]
wire _out_T_9358 = out_f_rivalid_961; // @[RegisterRouter.scala:87:24]
wire out_f_roready_961 = out_roready_1_815 & out_romask_961; // @[RegisterRouter.scala:87:24]
wire _out_T_9359 = out_f_roready_961; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_961 = out_wivalid_1_815 & out_wimask_961; // @[RegisterRouter.scala:87:24]
wire out_f_woready_961 = out_woready_1_815 & out_womask_961; // @[RegisterRouter.scala:87:24]
wire _out_T_9360 = ~out_rimask_961; // @[RegisterRouter.scala:87:24]
wire _out_T_9361 = ~out_wimask_961; // @[RegisterRouter.scala:87:24]
wire _out_T_9362 = ~out_romask_961; // @[RegisterRouter.scala:87:24]
wire _out_T_9363 = ~out_womask_961; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_821 = {hi_1021, flags_0_go, _out_prepend_T_821}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_9364 = out_prepend_821; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_9365 = _out_T_9364; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_822 = _out_T_9365; // @[RegisterRouter.scala:87:24]
wire out_rimask_962 = |_out_rimask_T_962; // @[RegisterRouter.scala:87:24]
wire out_wimask_962 = &_out_wimask_T_962; // @[RegisterRouter.scala:87:24]
wire out_romask_962 = |_out_romask_T_962; // @[RegisterRouter.scala:87:24]
wire out_womask_962 = &_out_womask_T_962; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_962 = out_rivalid_1_816 & out_rimask_962; // @[RegisterRouter.scala:87:24]
wire _out_T_9367 = out_f_rivalid_962; // @[RegisterRouter.scala:87:24]
wire out_f_roready_962 = out_roready_1_816 & out_romask_962; // @[RegisterRouter.scala:87:24]
wire _out_T_9368 = out_f_roready_962; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_962 = out_wivalid_1_816 & out_wimask_962; // @[RegisterRouter.scala:87:24]
wire out_f_woready_962 = out_woready_1_816 & out_womask_962; // @[RegisterRouter.scala:87:24]
wire _out_T_9369 = ~out_rimask_962; // @[RegisterRouter.scala:87:24]
wire _out_T_9370 = ~out_wimask_962; // @[RegisterRouter.scala:87:24]
wire _out_T_9371 = ~out_romask_962; // @[RegisterRouter.scala:87:24]
wire _out_T_9372 = ~out_womask_962; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_822 = {hi_1022, flags_0_go, _out_prepend_T_822}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_9373 = out_prepend_822; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_9374 = _out_T_9373; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_823 = _out_T_9374; // @[RegisterRouter.scala:87:24]
wire out_rimask_963 = |_out_rimask_T_963; // @[RegisterRouter.scala:87:24]
wire out_wimask_963 = &_out_wimask_T_963; // @[RegisterRouter.scala:87:24]
wire out_romask_963 = |_out_romask_T_963; // @[RegisterRouter.scala:87:24]
wire out_womask_963 = &_out_womask_T_963; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_963 = out_rivalid_1_817 & out_rimask_963; // @[RegisterRouter.scala:87:24]
wire _out_T_9376 = out_f_rivalid_963; // @[RegisterRouter.scala:87:24]
wire out_f_roready_963 = out_roready_1_817 & out_romask_963; // @[RegisterRouter.scala:87:24]
wire _out_T_9377 = out_f_roready_963; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_963 = out_wivalid_1_817 & out_wimask_963; // @[RegisterRouter.scala:87:24]
wire out_f_woready_963 = out_woready_1_817 & out_womask_963; // @[RegisterRouter.scala:87:24]
wire _out_T_9378 = ~out_rimask_963; // @[RegisterRouter.scala:87:24]
wire _out_T_9379 = ~out_wimask_963; // @[RegisterRouter.scala:87:24]
wire _out_T_9380 = ~out_romask_963; // @[RegisterRouter.scala:87:24]
wire _out_T_9381 = ~out_womask_963; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_823 = {hi_1023, flags_0_go, _out_prepend_T_823}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_9382 = out_prepend_823; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_9383 = _out_T_9382; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_824 = _out_T_9383; // @[RegisterRouter.scala:87:24]
wire out_rimask_964 = |_out_rimask_T_964; // @[RegisterRouter.scala:87:24]
wire out_wimask_964 = &_out_wimask_T_964; // @[RegisterRouter.scala:87:24]
wire out_romask_964 = |_out_romask_T_964; // @[RegisterRouter.scala:87:24]
wire out_womask_964 = &_out_womask_T_964; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_964 = out_rivalid_1_818 & out_rimask_964; // @[RegisterRouter.scala:87:24]
wire _out_T_9385 = out_f_rivalid_964; // @[RegisterRouter.scala:87:24]
wire out_f_roready_964 = out_roready_1_818 & out_romask_964; // @[RegisterRouter.scala:87:24]
wire _out_T_9386 = out_f_roready_964; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_964 = out_wivalid_1_818 & out_wimask_964; // @[RegisterRouter.scala:87:24]
wire out_f_woready_964 = out_woready_1_818 & out_womask_964; // @[RegisterRouter.scala:87:24]
wire _out_T_9387 = ~out_rimask_964; // @[RegisterRouter.scala:87:24]
wire _out_T_9388 = ~out_wimask_964; // @[RegisterRouter.scala:87:24]
wire _out_T_9389 = ~out_romask_964; // @[RegisterRouter.scala:87:24]
wire _out_T_9390 = ~out_womask_964; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_824 = {hi_1024, flags_0_go, _out_prepend_T_824}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_9391 = out_prepend_824; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_9392 = _out_T_9391; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_255 = _out_T_9392; // @[MuxLiteral.scala:49:48]
wire out_rimask_965 = |_out_rimask_T_965; // @[RegisterRouter.scala:87:24]
wire out_wimask_965 = &_out_wimask_T_965; // @[RegisterRouter.scala:87:24]
wire out_romask_965 = |_out_romask_T_965; // @[RegisterRouter.scala:87:24]
wire out_womask_965 = &_out_womask_T_965; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_965 = out_rivalid_1_819 & out_rimask_965; // @[RegisterRouter.scala:87:24]
wire _out_T_9394 = out_f_rivalid_965; // @[RegisterRouter.scala:87:24]
wire out_f_roready_965 = out_roready_1_819 & out_romask_965; // @[RegisterRouter.scala:87:24]
wire _out_T_9395 = out_f_roready_965; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_965 = out_wivalid_1_819 & out_wimask_965; // @[RegisterRouter.scala:87:24]
wire out_f_woready_965 = out_woready_1_819 & out_womask_965; // @[RegisterRouter.scala:87:24]
wire _out_T_9396 = ~out_rimask_965; // @[RegisterRouter.scala:87:24]
wire _out_T_9397 = ~out_wimask_965; // @[RegisterRouter.scala:87:24]
wire _out_T_9398 = ~out_romask_965; // @[RegisterRouter.scala:87:24]
wire _out_T_9399 = ~out_womask_965; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9401 = _out_T_9400; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_825 = _out_T_9401; // @[RegisterRouter.scala:87:24]
wire out_rimask_966 = |_out_rimask_T_966; // @[RegisterRouter.scala:87:24]
wire out_wimask_966 = &_out_wimask_T_966; // @[RegisterRouter.scala:87:24]
wire out_romask_966 = |_out_romask_T_966; // @[RegisterRouter.scala:87:24]
wire out_womask_966 = &_out_womask_T_966; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_966 = out_rivalid_1_820 & out_rimask_966; // @[RegisterRouter.scala:87:24]
wire _out_T_9403 = out_f_rivalid_966; // @[RegisterRouter.scala:87:24]
wire out_f_roready_966 = out_roready_1_820 & out_romask_966; // @[RegisterRouter.scala:87:24]
wire _out_T_9404 = out_f_roready_966; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_966 = out_wivalid_1_820 & out_wimask_966; // @[RegisterRouter.scala:87:24]
wire out_f_woready_966 = out_woready_1_820 & out_womask_966; // @[RegisterRouter.scala:87:24]
wire _out_T_9405 = ~out_rimask_966; // @[RegisterRouter.scala:87:24]
wire _out_T_9406 = ~out_wimask_966; // @[RegisterRouter.scala:87:24]
wire _out_T_9407 = ~out_romask_966; // @[RegisterRouter.scala:87:24]
wire _out_T_9408 = ~out_womask_966; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_825 = {hi_650, flags_0_go, _out_prepend_T_825}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_9409 = out_prepend_825; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_9410 = _out_T_9409; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_826 = _out_T_9410; // @[RegisterRouter.scala:87:24]
wire out_rimask_967 = |_out_rimask_T_967; // @[RegisterRouter.scala:87:24]
wire out_wimask_967 = &_out_wimask_T_967; // @[RegisterRouter.scala:87:24]
wire out_romask_967 = |_out_romask_T_967; // @[RegisterRouter.scala:87:24]
wire out_womask_967 = &_out_womask_T_967; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_967 = out_rivalid_1_821 & out_rimask_967; // @[RegisterRouter.scala:87:24]
wire _out_T_9412 = out_f_rivalid_967; // @[RegisterRouter.scala:87:24]
wire out_f_roready_967 = out_roready_1_821 & out_romask_967; // @[RegisterRouter.scala:87:24]
wire _out_T_9413 = out_f_roready_967; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_967 = out_wivalid_1_821 & out_wimask_967; // @[RegisterRouter.scala:87:24]
wire out_f_woready_967 = out_woready_1_821 & out_womask_967; // @[RegisterRouter.scala:87:24]
wire _out_T_9414 = ~out_rimask_967; // @[RegisterRouter.scala:87:24]
wire _out_T_9415 = ~out_wimask_967; // @[RegisterRouter.scala:87:24]
wire _out_T_9416 = ~out_romask_967; // @[RegisterRouter.scala:87:24]
wire _out_T_9417 = ~out_womask_967; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_826 = {hi_651, flags_0_go, _out_prepend_T_826}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_9418 = out_prepend_826; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_9419 = _out_T_9418; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_827 = _out_T_9419; // @[RegisterRouter.scala:87:24]
wire out_rimask_968 = |_out_rimask_T_968; // @[RegisterRouter.scala:87:24]
wire out_wimask_968 = &_out_wimask_T_968; // @[RegisterRouter.scala:87:24]
wire out_romask_968 = |_out_romask_T_968; // @[RegisterRouter.scala:87:24]
wire out_womask_968 = &_out_womask_T_968; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_968 = out_rivalid_1_822 & out_rimask_968; // @[RegisterRouter.scala:87:24]
wire _out_T_9421 = out_f_rivalid_968; // @[RegisterRouter.scala:87:24]
wire out_f_roready_968 = out_roready_1_822 & out_romask_968; // @[RegisterRouter.scala:87:24]
wire _out_T_9422 = out_f_roready_968; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_968 = out_wivalid_1_822 & out_wimask_968; // @[RegisterRouter.scala:87:24]
wire out_f_woready_968 = out_woready_1_822 & out_womask_968; // @[RegisterRouter.scala:87:24]
wire _out_T_9423 = ~out_rimask_968; // @[RegisterRouter.scala:87:24]
wire _out_T_9424 = ~out_wimask_968; // @[RegisterRouter.scala:87:24]
wire _out_T_9425 = ~out_romask_968; // @[RegisterRouter.scala:87:24]
wire _out_T_9426 = ~out_womask_968; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_827 = {hi_652, flags_0_go, _out_prepend_T_827}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_9427 = out_prepend_827; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_9428 = _out_T_9427; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_828 = _out_T_9428; // @[RegisterRouter.scala:87:24]
wire out_rimask_969 = |_out_rimask_T_969; // @[RegisterRouter.scala:87:24]
wire out_wimask_969 = &_out_wimask_T_969; // @[RegisterRouter.scala:87:24]
wire out_romask_969 = |_out_romask_T_969; // @[RegisterRouter.scala:87:24]
wire out_womask_969 = &_out_womask_T_969; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_969 = out_rivalid_1_823 & out_rimask_969; // @[RegisterRouter.scala:87:24]
wire _out_T_9430 = out_f_rivalid_969; // @[RegisterRouter.scala:87:24]
wire out_f_roready_969 = out_roready_1_823 & out_romask_969; // @[RegisterRouter.scala:87:24]
wire _out_T_9431 = out_f_roready_969; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_969 = out_wivalid_1_823 & out_wimask_969; // @[RegisterRouter.scala:87:24]
wire out_f_woready_969 = out_woready_1_823 & out_womask_969; // @[RegisterRouter.scala:87:24]
wire _out_T_9432 = ~out_rimask_969; // @[RegisterRouter.scala:87:24]
wire _out_T_9433 = ~out_wimask_969; // @[RegisterRouter.scala:87:24]
wire _out_T_9434 = ~out_romask_969; // @[RegisterRouter.scala:87:24]
wire _out_T_9435 = ~out_womask_969; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_828 = {hi_653, flags_0_go, _out_prepend_T_828}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_9436 = out_prepend_828; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_9437 = _out_T_9436; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_829 = _out_T_9437; // @[RegisterRouter.scala:87:24]
wire out_rimask_970 = |_out_rimask_T_970; // @[RegisterRouter.scala:87:24]
wire out_wimask_970 = &_out_wimask_T_970; // @[RegisterRouter.scala:87:24]
wire out_romask_970 = |_out_romask_T_970; // @[RegisterRouter.scala:87:24]
wire out_womask_970 = &_out_womask_T_970; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_970 = out_rivalid_1_824 & out_rimask_970; // @[RegisterRouter.scala:87:24]
wire _out_T_9439 = out_f_rivalid_970; // @[RegisterRouter.scala:87:24]
wire out_f_roready_970 = out_roready_1_824 & out_romask_970; // @[RegisterRouter.scala:87:24]
wire _out_T_9440 = out_f_roready_970; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_970 = out_wivalid_1_824 & out_wimask_970; // @[RegisterRouter.scala:87:24]
wire out_f_woready_970 = out_woready_1_824 & out_womask_970; // @[RegisterRouter.scala:87:24]
wire _out_T_9441 = ~out_rimask_970; // @[RegisterRouter.scala:87:24]
wire _out_T_9442 = ~out_wimask_970; // @[RegisterRouter.scala:87:24]
wire _out_T_9443 = ~out_romask_970; // @[RegisterRouter.scala:87:24]
wire _out_T_9444 = ~out_womask_970; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_829 = {hi_654, flags_0_go, _out_prepend_T_829}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_9445 = out_prepend_829; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_9446 = _out_T_9445; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_830 = _out_T_9446; // @[RegisterRouter.scala:87:24]
wire out_rimask_971 = |_out_rimask_T_971; // @[RegisterRouter.scala:87:24]
wire out_wimask_971 = &_out_wimask_T_971; // @[RegisterRouter.scala:87:24]
wire out_romask_971 = |_out_romask_T_971; // @[RegisterRouter.scala:87:24]
wire out_womask_971 = &_out_womask_T_971; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_971 = out_rivalid_1_825 & out_rimask_971; // @[RegisterRouter.scala:87:24]
wire _out_T_9448 = out_f_rivalid_971; // @[RegisterRouter.scala:87:24]
wire out_f_roready_971 = out_roready_1_825 & out_romask_971; // @[RegisterRouter.scala:87:24]
wire _out_T_9449 = out_f_roready_971; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_971 = out_wivalid_1_825 & out_wimask_971; // @[RegisterRouter.scala:87:24]
wire out_f_woready_971 = out_woready_1_825 & out_womask_971; // @[RegisterRouter.scala:87:24]
wire _out_T_9450 = ~out_rimask_971; // @[RegisterRouter.scala:87:24]
wire _out_T_9451 = ~out_wimask_971; // @[RegisterRouter.scala:87:24]
wire _out_T_9452 = ~out_romask_971; // @[RegisterRouter.scala:87:24]
wire _out_T_9453 = ~out_womask_971; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_830 = {hi_655, flags_0_go, _out_prepend_T_830}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_9454 = out_prepend_830; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_9455 = _out_T_9454; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_831 = _out_T_9455; // @[RegisterRouter.scala:87:24]
wire out_rimask_972 = |_out_rimask_T_972; // @[RegisterRouter.scala:87:24]
wire out_wimask_972 = &_out_wimask_T_972; // @[RegisterRouter.scala:87:24]
wire out_romask_972 = |_out_romask_T_972; // @[RegisterRouter.scala:87:24]
wire out_womask_972 = &_out_womask_T_972; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_972 = out_rivalid_1_826 & out_rimask_972; // @[RegisterRouter.scala:87:24]
wire _out_T_9457 = out_f_rivalid_972; // @[RegisterRouter.scala:87:24]
wire out_f_roready_972 = out_roready_1_826 & out_romask_972; // @[RegisterRouter.scala:87:24]
wire _out_T_9458 = out_f_roready_972; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_972 = out_wivalid_1_826 & out_wimask_972; // @[RegisterRouter.scala:87:24]
wire out_f_woready_972 = out_woready_1_826 & out_womask_972; // @[RegisterRouter.scala:87:24]
wire _out_T_9459 = ~out_rimask_972; // @[RegisterRouter.scala:87:24]
wire _out_T_9460 = ~out_wimask_972; // @[RegisterRouter.scala:87:24]
wire _out_T_9461 = ~out_romask_972; // @[RegisterRouter.scala:87:24]
wire _out_T_9462 = ~out_womask_972; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_831 = {hi_656, flags_0_go, _out_prepend_T_831}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_9463 = out_prepend_831; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_9464 = _out_T_9463; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_209 = _out_T_9464; // @[MuxLiteral.scala:49:48]
wire out_rimask_973 = |_out_rimask_T_973; // @[RegisterRouter.scala:87:24]
wire out_wimask_973 = &_out_wimask_T_973; // @[RegisterRouter.scala:87:24]
wire out_romask_973 = |_out_romask_T_973; // @[RegisterRouter.scala:87:24]
wire out_womask_973 = &_out_womask_T_973; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_973 = out_rivalid_1_827 & out_rimask_973; // @[RegisterRouter.scala:87:24]
wire _out_T_9466 = out_f_rivalid_973; // @[RegisterRouter.scala:87:24]
wire out_f_roready_973 = out_roready_1_827 & out_romask_973; // @[RegisterRouter.scala:87:24]
wire _out_T_9467 = out_f_roready_973; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_973 = out_wivalid_1_827 & out_wimask_973; // @[RegisterRouter.scala:87:24]
wire _out_T_9468 = out_f_wivalid_973; // @[RegisterRouter.scala:87:24]
wire out_f_woready_973 = out_woready_1_827 & out_womask_973; // @[RegisterRouter.scala:87:24]
wire _out_T_9469 = out_f_woready_973; // @[RegisterRouter.scala:87:24]
wire _out_T_9470 = ~out_rimask_973; // @[RegisterRouter.scala:87:24]
wire _out_T_9471 = ~out_wimask_973; // @[RegisterRouter.scala:87:24]
wire _out_T_9472 = ~out_romask_973; // @[RegisterRouter.scala:87:24]
wire _out_T_9473 = ~out_womask_973; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9475 = _out_T_9474; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_832 = _out_T_9475; // @[RegisterRouter.scala:87:24]
wire out_rimask_974 = |_out_rimask_T_974; // @[RegisterRouter.scala:87:24]
wire out_wimask_974 = &_out_wimask_T_974; // @[RegisterRouter.scala:87:24]
wire out_romask_974 = |_out_romask_T_974; // @[RegisterRouter.scala:87:24]
wire out_womask_974 = &_out_womask_T_974; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_974 = out_rivalid_1_828 & out_rimask_974; // @[RegisterRouter.scala:87:24]
wire _out_T_9477 = out_f_rivalid_974; // @[RegisterRouter.scala:87:24]
wire out_f_roready_974 = out_roready_1_828 & out_romask_974; // @[RegisterRouter.scala:87:24]
wire _out_T_9478 = out_f_roready_974; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_974 = out_wivalid_1_828 & out_wimask_974; // @[RegisterRouter.scala:87:24]
wire _out_T_9479 = out_f_wivalid_974; // @[RegisterRouter.scala:87:24]
wire out_f_woready_974 = out_woready_1_828 & out_womask_974; // @[RegisterRouter.scala:87:24]
wire _out_T_9480 = out_f_woready_974; // @[RegisterRouter.scala:87:24]
wire _out_T_9481 = ~out_rimask_974; // @[RegisterRouter.scala:87:24]
wire _out_T_9482 = ~out_wimask_974; // @[RegisterRouter.scala:87:24]
wire _out_T_9483 = ~out_romask_974; // @[RegisterRouter.scala:87:24]
wire _out_T_9484 = ~out_womask_974; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_832 = {abstractDataMem_1, _out_prepend_T_832}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_9485 = out_prepend_832; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_9486 = _out_T_9485; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_833 = _out_T_9486; // @[RegisterRouter.scala:87:24]
wire out_rimask_975 = |_out_rimask_T_975; // @[RegisterRouter.scala:87:24]
wire out_wimask_975 = &_out_wimask_T_975; // @[RegisterRouter.scala:87:24]
wire out_romask_975 = |_out_romask_T_975; // @[RegisterRouter.scala:87:24]
wire out_womask_975 = &_out_womask_T_975; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_975 = out_rivalid_1_829 & out_rimask_975; // @[RegisterRouter.scala:87:24]
wire _out_T_9488 = out_f_rivalid_975; // @[RegisterRouter.scala:87:24]
wire out_f_roready_975 = out_roready_1_829 & out_romask_975; // @[RegisterRouter.scala:87:24]
wire _out_T_9489 = out_f_roready_975; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_975 = out_wivalid_1_829 & out_wimask_975; // @[RegisterRouter.scala:87:24]
wire _out_T_9490 = out_f_wivalid_975; // @[RegisterRouter.scala:87:24]
wire out_f_woready_975 = out_woready_1_829 & out_womask_975; // @[RegisterRouter.scala:87:24]
wire _out_T_9491 = out_f_woready_975; // @[RegisterRouter.scala:87:24]
wire _out_T_9492 = ~out_rimask_975; // @[RegisterRouter.scala:87:24]
wire _out_T_9493 = ~out_wimask_975; // @[RegisterRouter.scala:87:24]
wire _out_T_9494 = ~out_romask_975; // @[RegisterRouter.scala:87:24]
wire _out_T_9495 = ~out_womask_975; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_833 = {abstractDataMem_2, _out_prepend_T_833}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_9496 = out_prepend_833; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_9497 = _out_T_9496; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_834 = _out_T_9497; // @[RegisterRouter.scala:87:24]
wire out_rimask_976 = |_out_rimask_T_976; // @[RegisterRouter.scala:87:24]
wire out_wimask_976 = &_out_wimask_T_976; // @[RegisterRouter.scala:87:24]
wire out_romask_976 = |_out_romask_T_976; // @[RegisterRouter.scala:87:24]
wire out_womask_976 = &_out_womask_T_976; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_976 = out_rivalid_1_830 & out_rimask_976; // @[RegisterRouter.scala:87:24]
wire _out_T_9499 = out_f_rivalid_976; // @[RegisterRouter.scala:87:24]
wire out_f_roready_976 = out_roready_1_830 & out_romask_976; // @[RegisterRouter.scala:87:24]
wire _out_T_9500 = out_f_roready_976; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_976 = out_wivalid_1_830 & out_wimask_976; // @[RegisterRouter.scala:87:24]
wire _out_T_9501 = out_f_wivalid_976; // @[RegisterRouter.scala:87:24]
wire out_f_woready_976 = out_woready_1_830 & out_womask_976; // @[RegisterRouter.scala:87:24]
wire _out_T_9502 = out_f_woready_976; // @[RegisterRouter.scala:87:24]
wire _out_T_9503 = ~out_rimask_976; // @[RegisterRouter.scala:87:24]
wire _out_T_9504 = ~out_wimask_976; // @[RegisterRouter.scala:87:24]
wire _out_T_9505 = ~out_romask_976; // @[RegisterRouter.scala:87:24]
wire _out_T_9506 = ~out_womask_976; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_834 = {abstractDataMem_3, _out_prepend_T_834}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_9507 = out_prepend_834; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_9508 = _out_T_9507; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_835 = _out_T_9508; // @[RegisterRouter.scala:87:24]
wire out_rimask_977 = |_out_rimask_T_977; // @[RegisterRouter.scala:87:24]
wire out_wimask_977 = &_out_wimask_T_977; // @[RegisterRouter.scala:87:24]
wire out_romask_977 = |_out_romask_T_977; // @[RegisterRouter.scala:87:24]
wire out_womask_977 = &_out_womask_T_977; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_977 = out_rivalid_1_831 & out_rimask_977; // @[RegisterRouter.scala:87:24]
wire _out_T_9510 = out_f_rivalid_977; // @[RegisterRouter.scala:87:24]
wire out_f_roready_977 = out_roready_1_831 & out_romask_977; // @[RegisterRouter.scala:87:24]
wire _out_T_9511 = out_f_roready_977; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_977 = out_wivalid_1_831 & out_wimask_977; // @[RegisterRouter.scala:87:24]
wire _out_T_9512 = out_f_wivalid_977; // @[RegisterRouter.scala:87:24]
wire out_f_woready_977 = out_woready_1_831 & out_womask_977; // @[RegisterRouter.scala:87:24]
wire _out_T_9513 = out_f_woready_977; // @[RegisterRouter.scala:87:24]
wire _out_T_9514 = ~out_rimask_977; // @[RegisterRouter.scala:87:24]
wire _out_T_9515 = ~out_wimask_977; // @[RegisterRouter.scala:87:24]
wire _out_T_9516 = ~out_romask_977; // @[RegisterRouter.scala:87:24]
wire _out_T_9517 = ~out_womask_977; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_835 = {abstractDataMem_4, _out_prepend_T_835}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_9518 = out_prepend_835; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_9519 = _out_T_9518; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_836 = _out_T_9519; // @[RegisterRouter.scala:87:24]
wire out_rimask_978 = |_out_rimask_T_978; // @[RegisterRouter.scala:87:24]
wire out_wimask_978 = &_out_wimask_T_978; // @[RegisterRouter.scala:87:24]
wire out_romask_978 = |_out_romask_T_978; // @[RegisterRouter.scala:87:24]
wire out_womask_978 = &_out_womask_T_978; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_978 = out_rivalid_1_832 & out_rimask_978; // @[RegisterRouter.scala:87:24]
wire _out_T_9521 = out_f_rivalid_978; // @[RegisterRouter.scala:87:24]
wire out_f_roready_978 = out_roready_1_832 & out_romask_978; // @[RegisterRouter.scala:87:24]
wire _out_T_9522 = out_f_roready_978; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_978 = out_wivalid_1_832 & out_wimask_978; // @[RegisterRouter.scala:87:24]
wire _out_T_9523 = out_f_wivalid_978; // @[RegisterRouter.scala:87:24]
wire out_f_woready_978 = out_woready_1_832 & out_womask_978; // @[RegisterRouter.scala:87:24]
wire _out_T_9524 = out_f_woready_978; // @[RegisterRouter.scala:87:24]
wire _out_T_9525 = ~out_rimask_978; // @[RegisterRouter.scala:87:24]
wire _out_T_9526 = ~out_wimask_978; // @[RegisterRouter.scala:87:24]
wire _out_T_9527 = ~out_romask_978; // @[RegisterRouter.scala:87:24]
wire _out_T_9528 = ~out_womask_978; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_836 = {abstractDataMem_5, _out_prepend_T_836}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_9529 = out_prepend_836; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_9530 = _out_T_9529; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_837 = _out_T_9530; // @[RegisterRouter.scala:87:24]
wire out_rimask_979 = |_out_rimask_T_979; // @[RegisterRouter.scala:87:24]
wire out_wimask_979 = &_out_wimask_T_979; // @[RegisterRouter.scala:87:24]
wire out_romask_979 = |_out_romask_T_979; // @[RegisterRouter.scala:87:24]
wire out_womask_979 = &_out_womask_T_979; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_979 = out_rivalid_1_833 & out_rimask_979; // @[RegisterRouter.scala:87:24]
wire _out_T_9532 = out_f_rivalid_979; // @[RegisterRouter.scala:87:24]
wire out_f_roready_979 = out_roready_1_833 & out_romask_979; // @[RegisterRouter.scala:87:24]
wire _out_T_9533 = out_f_roready_979; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_979 = out_wivalid_1_833 & out_wimask_979; // @[RegisterRouter.scala:87:24]
wire _out_T_9534 = out_f_wivalid_979; // @[RegisterRouter.scala:87:24]
wire out_f_woready_979 = out_woready_1_833 & out_womask_979; // @[RegisterRouter.scala:87:24]
wire _out_T_9535 = out_f_woready_979; // @[RegisterRouter.scala:87:24]
wire _out_T_9536 = ~out_rimask_979; // @[RegisterRouter.scala:87:24]
wire _out_T_9537 = ~out_wimask_979; // @[RegisterRouter.scala:87:24]
wire _out_T_9538 = ~out_romask_979; // @[RegisterRouter.scala:87:24]
wire _out_T_9539 = ~out_womask_979; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_837 = {abstractDataMem_6, _out_prepend_T_837}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_9540 = out_prepend_837; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_9541 = _out_T_9540; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_838 = _out_T_9541; // @[RegisterRouter.scala:87:24]
wire out_rimask_980 = |_out_rimask_T_980; // @[RegisterRouter.scala:87:24]
wire out_wimask_980 = &_out_wimask_T_980; // @[RegisterRouter.scala:87:24]
wire out_romask_980 = |_out_romask_T_980; // @[RegisterRouter.scala:87:24]
wire out_womask_980 = &_out_womask_T_980; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_980 = out_rivalid_1_834 & out_rimask_980; // @[RegisterRouter.scala:87:24]
wire _out_T_9543 = out_f_rivalid_980; // @[RegisterRouter.scala:87:24]
wire out_f_roready_980 = out_roready_1_834 & out_romask_980; // @[RegisterRouter.scala:87:24]
wire _out_T_9544 = out_f_roready_980; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_980 = out_wivalid_1_834 & out_wimask_980; // @[RegisterRouter.scala:87:24]
wire _out_T_9545 = out_f_wivalid_980; // @[RegisterRouter.scala:87:24]
wire out_f_woready_980 = out_woready_1_834 & out_womask_980; // @[RegisterRouter.scala:87:24]
wire _out_T_9546 = out_f_woready_980; // @[RegisterRouter.scala:87:24]
wire _out_T_9547 = ~out_rimask_980; // @[RegisterRouter.scala:87:24]
wire _out_T_9548 = ~out_wimask_980; // @[RegisterRouter.scala:87:24]
wire _out_T_9549 = ~out_romask_980; // @[RegisterRouter.scala:87:24]
wire _out_T_9550 = ~out_womask_980; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_838 = {abstractDataMem_7, _out_prepend_T_838}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_9551 = out_prepend_838; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_9552 = _out_T_9551; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_112 = _out_T_9552; // @[MuxLiteral.scala:49:48]
wire out_rimask_981 = |_out_rimask_T_981; // @[RegisterRouter.scala:87:24]
wire out_wimask_981 = &_out_wimask_T_981; // @[RegisterRouter.scala:87:24]
wire out_romask_981 = |_out_romask_T_981; // @[RegisterRouter.scala:87:24]
wire out_womask_981 = &_out_womask_T_981; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_981 = out_rivalid_1_835 & out_rimask_981; // @[RegisterRouter.scala:87:24]
wire _out_T_9554 = out_f_rivalid_981; // @[RegisterRouter.scala:87:24]
wire out_f_roready_981 = out_roready_1_835 & out_romask_981; // @[RegisterRouter.scala:87:24]
wire _out_T_9555 = out_f_roready_981; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_981 = out_wivalid_1_835 & out_wimask_981; // @[RegisterRouter.scala:87:24]
wire out_f_woready_981 = out_woready_1_835 & out_womask_981; // @[RegisterRouter.scala:87:24]
wire _out_T_9556 = ~out_rimask_981; // @[RegisterRouter.scala:87:24]
wire _out_T_9557 = ~out_wimask_981; // @[RegisterRouter.scala:87:24]
wire _out_T_9558 = ~out_romask_981; // @[RegisterRouter.scala:87:24]
wire _out_T_9559 = ~out_womask_981; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9561 = _out_T_9560; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_839 = _out_T_9561; // @[RegisterRouter.scala:87:24]
wire out_rimask_982 = |_out_rimask_T_982; // @[RegisterRouter.scala:87:24]
wire out_wimask_982 = &_out_wimask_T_982; // @[RegisterRouter.scala:87:24]
wire out_romask_982 = |_out_romask_T_982; // @[RegisterRouter.scala:87:24]
wire out_womask_982 = &_out_womask_T_982; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_982 = out_rivalid_1_836 & out_rimask_982; // @[RegisterRouter.scala:87:24]
wire _out_T_9563 = out_f_rivalid_982; // @[RegisterRouter.scala:87:24]
wire out_f_roready_982 = out_roready_1_836 & out_romask_982; // @[RegisterRouter.scala:87:24]
wire _out_T_9564 = out_f_roready_982; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_982 = out_wivalid_1_836 & out_wimask_982; // @[RegisterRouter.scala:87:24]
wire out_f_woready_982 = out_woready_1_836 & out_womask_982; // @[RegisterRouter.scala:87:24]
wire _out_T_9565 = ~out_rimask_982; // @[RegisterRouter.scala:87:24]
wire _out_T_9566 = ~out_wimask_982; // @[RegisterRouter.scala:87:24]
wire _out_T_9567 = ~out_romask_982; // @[RegisterRouter.scala:87:24]
wire _out_T_9568 = ~out_womask_982; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_839 = {hi_530, flags_0_go, _out_prepend_T_839}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_9569 = out_prepend_839; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_9570 = _out_T_9569; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_840 = _out_T_9570; // @[RegisterRouter.scala:87:24]
wire out_rimask_983 = |_out_rimask_T_983; // @[RegisterRouter.scala:87:24]
wire out_wimask_983 = &_out_wimask_T_983; // @[RegisterRouter.scala:87:24]
wire out_romask_983 = |_out_romask_T_983; // @[RegisterRouter.scala:87:24]
wire out_womask_983 = &_out_womask_T_983; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_983 = out_rivalid_1_837 & out_rimask_983; // @[RegisterRouter.scala:87:24]
wire _out_T_9572 = out_f_rivalid_983; // @[RegisterRouter.scala:87:24]
wire out_f_roready_983 = out_roready_1_837 & out_romask_983; // @[RegisterRouter.scala:87:24]
wire _out_T_9573 = out_f_roready_983; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_983 = out_wivalid_1_837 & out_wimask_983; // @[RegisterRouter.scala:87:24]
wire out_f_woready_983 = out_woready_1_837 & out_womask_983; // @[RegisterRouter.scala:87:24]
wire _out_T_9574 = ~out_rimask_983; // @[RegisterRouter.scala:87:24]
wire _out_T_9575 = ~out_wimask_983; // @[RegisterRouter.scala:87:24]
wire _out_T_9576 = ~out_romask_983; // @[RegisterRouter.scala:87:24]
wire _out_T_9577 = ~out_womask_983; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_840 = {hi_531, flags_0_go, _out_prepend_T_840}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_9578 = out_prepend_840; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_9579 = _out_T_9578; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_841 = _out_T_9579; // @[RegisterRouter.scala:87:24]
wire out_rimask_984 = |_out_rimask_T_984; // @[RegisterRouter.scala:87:24]
wire out_wimask_984 = &_out_wimask_T_984; // @[RegisterRouter.scala:87:24]
wire out_romask_984 = |_out_romask_T_984; // @[RegisterRouter.scala:87:24]
wire out_womask_984 = &_out_womask_T_984; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_984 = out_rivalid_1_838 & out_rimask_984; // @[RegisterRouter.scala:87:24]
wire _out_T_9581 = out_f_rivalid_984; // @[RegisterRouter.scala:87:24]
wire out_f_roready_984 = out_roready_1_838 & out_romask_984; // @[RegisterRouter.scala:87:24]
wire _out_T_9582 = out_f_roready_984; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_984 = out_wivalid_1_838 & out_wimask_984; // @[RegisterRouter.scala:87:24]
wire out_f_woready_984 = out_woready_1_838 & out_womask_984; // @[RegisterRouter.scala:87:24]
wire _out_T_9583 = ~out_rimask_984; // @[RegisterRouter.scala:87:24]
wire _out_T_9584 = ~out_wimask_984; // @[RegisterRouter.scala:87:24]
wire _out_T_9585 = ~out_romask_984; // @[RegisterRouter.scala:87:24]
wire _out_T_9586 = ~out_womask_984; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_841 = {hi_532, flags_0_go, _out_prepend_T_841}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_9587 = out_prepend_841; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_9588 = _out_T_9587; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_842 = _out_T_9588; // @[RegisterRouter.scala:87:24]
wire out_rimask_985 = |_out_rimask_T_985; // @[RegisterRouter.scala:87:24]
wire out_wimask_985 = &_out_wimask_T_985; // @[RegisterRouter.scala:87:24]
wire out_romask_985 = |_out_romask_T_985; // @[RegisterRouter.scala:87:24]
wire out_womask_985 = &_out_womask_T_985; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_985 = out_rivalid_1_839 & out_rimask_985; // @[RegisterRouter.scala:87:24]
wire _out_T_9590 = out_f_rivalid_985; // @[RegisterRouter.scala:87:24]
wire out_f_roready_985 = out_roready_1_839 & out_romask_985; // @[RegisterRouter.scala:87:24]
wire _out_T_9591 = out_f_roready_985; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_985 = out_wivalid_1_839 & out_wimask_985; // @[RegisterRouter.scala:87:24]
wire out_f_woready_985 = out_woready_1_839 & out_womask_985; // @[RegisterRouter.scala:87:24]
wire _out_T_9592 = ~out_rimask_985; // @[RegisterRouter.scala:87:24]
wire _out_T_9593 = ~out_wimask_985; // @[RegisterRouter.scala:87:24]
wire _out_T_9594 = ~out_romask_985; // @[RegisterRouter.scala:87:24]
wire _out_T_9595 = ~out_womask_985; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_842 = {hi_533, flags_0_go, _out_prepend_T_842}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_9596 = out_prepend_842; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_9597 = _out_T_9596; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_843 = _out_T_9597; // @[RegisterRouter.scala:87:24]
wire out_rimask_986 = |_out_rimask_T_986; // @[RegisterRouter.scala:87:24]
wire out_wimask_986 = &_out_wimask_T_986; // @[RegisterRouter.scala:87:24]
wire out_romask_986 = |_out_romask_T_986; // @[RegisterRouter.scala:87:24]
wire out_womask_986 = &_out_womask_T_986; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_986 = out_rivalid_1_840 & out_rimask_986; // @[RegisterRouter.scala:87:24]
wire _out_T_9599 = out_f_rivalid_986; // @[RegisterRouter.scala:87:24]
wire out_f_roready_986 = out_roready_1_840 & out_romask_986; // @[RegisterRouter.scala:87:24]
wire _out_T_9600 = out_f_roready_986; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_986 = out_wivalid_1_840 & out_wimask_986; // @[RegisterRouter.scala:87:24]
wire out_f_woready_986 = out_woready_1_840 & out_womask_986; // @[RegisterRouter.scala:87:24]
wire _out_T_9601 = ~out_rimask_986; // @[RegisterRouter.scala:87:24]
wire _out_T_9602 = ~out_wimask_986; // @[RegisterRouter.scala:87:24]
wire _out_T_9603 = ~out_romask_986; // @[RegisterRouter.scala:87:24]
wire _out_T_9604 = ~out_womask_986; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_843 = {hi_534, flags_0_go, _out_prepend_T_843}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_9605 = out_prepend_843; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_9606 = _out_T_9605; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_844 = _out_T_9606; // @[RegisterRouter.scala:87:24]
wire out_rimask_987 = |_out_rimask_T_987; // @[RegisterRouter.scala:87:24]
wire out_wimask_987 = &_out_wimask_T_987; // @[RegisterRouter.scala:87:24]
wire out_romask_987 = |_out_romask_T_987; // @[RegisterRouter.scala:87:24]
wire out_womask_987 = &_out_womask_T_987; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_987 = out_rivalid_1_841 & out_rimask_987; // @[RegisterRouter.scala:87:24]
wire _out_T_9608 = out_f_rivalid_987; // @[RegisterRouter.scala:87:24]
wire out_f_roready_987 = out_roready_1_841 & out_romask_987; // @[RegisterRouter.scala:87:24]
wire _out_T_9609 = out_f_roready_987; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_987 = out_wivalid_1_841 & out_wimask_987; // @[RegisterRouter.scala:87:24]
wire out_f_woready_987 = out_woready_1_841 & out_womask_987; // @[RegisterRouter.scala:87:24]
wire _out_T_9610 = ~out_rimask_987; // @[RegisterRouter.scala:87:24]
wire _out_T_9611 = ~out_wimask_987; // @[RegisterRouter.scala:87:24]
wire _out_T_9612 = ~out_romask_987; // @[RegisterRouter.scala:87:24]
wire _out_T_9613 = ~out_womask_987; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_844 = {hi_535, flags_0_go, _out_prepend_T_844}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_9614 = out_prepend_844; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_9615 = _out_T_9614; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_845 = _out_T_9615; // @[RegisterRouter.scala:87:24]
wire out_rimask_988 = |_out_rimask_T_988; // @[RegisterRouter.scala:87:24]
wire out_wimask_988 = &_out_wimask_T_988; // @[RegisterRouter.scala:87:24]
wire out_romask_988 = |_out_romask_T_988; // @[RegisterRouter.scala:87:24]
wire out_womask_988 = &_out_womask_T_988; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_988 = out_rivalid_1_842 & out_rimask_988; // @[RegisterRouter.scala:87:24]
wire _out_T_9617 = out_f_rivalid_988; // @[RegisterRouter.scala:87:24]
wire out_f_roready_988 = out_roready_1_842 & out_romask_988; // @[RegisterRouter.scala:87:24]
wire _out_T_9618 = out_f_roready_988; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_988 = out_wivalid_1_842 & out_wimask_988; // @[RegisterRouter.scala:87:24]
wire out_f_woready_988 = out_woready_1_842 & out_womask_988; // @[RegisterRouter.scala:87:24]
wire _out_T_9619 = ~out_rimask_988; // @[RegisterRouter.scala:87:24]
wire _out_T_9620 = ~out_wimask_988; // @[RegisterRouter.scala:87:24]
wire _out_T_9621 = ~out_romask_988; // @[RegisterRouter.scala:87:24]
wire _out_T_9622 = ~out_womask_988; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_845 = {hi_536, flags_0_go, _out_prepend_T_845}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_9623 = out_prepend_845; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_9624 = _out_T_9623; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_194 = _out_T_9624; // @[MuxLiteral.scala:49:48]
wire out_rimask_989 = |_out_rimask_T_989; // @[RegisterRouter.scala:87:24]
wire out_wimask_989 = &_out_wimask_T_989; // @[RegisterRouter.scala:87:24]
wire out_romask_989 = |_out_romask_T_989; // @[RegisterRouter.scala:87:24]
wire out_womask_989 = &_out_womask_T_989; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_989 = out_rivalid_1_843 & out_rimask_989; // @[RegisterRouter.scala:87:24]
wire _out_T_9626 = out_f_rivalid_989; // @[RegisterRouter.scala:87:24]
wire out_f_roready_989 = out_roready_1_843 & out_romask_989; // @[RegisterRouter.scala:87:24]
wire _out_T_9627 = out_f_roready_989; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_989 = out_wivalid_1_843 & out_wimask_989; // @[RegisterRouter.scala:87:24]
wire out_f_woready_989 = out_woready_1_843 & out_womask_989; // @[RegisterRouter.scala:87:24]
wire _out_T_9628 = ~out_rimask_989; // @[RegisterRouter.scala:87:24]
wire _out_T_9629 = ~out_wimask_989; // @[RegisterRouter.scala:87:24]
wire _out_T_9630 = ~out_romask_989; // @[RegisterRouter.scala:87:24]
wire _out_T_9631 = ~out_womask_989; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9633 = _out_T_9632; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_846 = _out_T_9633; // @[RegisterRouter.scala:87:24]
wire out_rimask_990 = |_out_rimask_T_990; // @[RegisterRouter.scala:87:24]
wire out_wimask_990 = &_out_wimask_T_990; // @[RegisterRouter.scala:87:24]
wire out_romask_990 = |_out_romask_T_990; // @[RegisterRouter.scala:87:24]
wire out_womask_990 = &_out_womask_T_990; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_990 = out_rivalid_1_844 & out_rimask_990; // @[RegisterRouter.scala:87:24]
wire _out_T_9635 = out_f_rivalid_990; // @[RegisterRouter.scala:87:24]
wire out_f_roready_990 = out_roready_1_844 & out_romask_990; // @[RegisterRouter.scala:87:24]
wire _out_T_9636 = out_f_roready_990; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_990 = out_wivalid_1_844 & out_wimask_990; // @[RegisterRouter.scala:87:24]
wire out_f_woready_990 = out_woready_1_844 & out_womask_990; // @[RegisterRouter.scala:87:24]
wire _out_T_9637 = ~out_rimask_990; // @[RegisterRouter.scala:87:24]
wire _out_T_9638 = ~out_wimask_990; // @[RegisterRouter.scala:87:24]
wire _out_T_9639 = ~out_romask_990; // @[RegisterRouter.scala:87:24]
wire _out_T_9640 = ~out_womask_990; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_846 = {hi_138, flags_0_go, _out_prepend_T_846}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_9641 = out_prepend_846; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_9642 = _out_T_9641; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_847 = _out_T_9642; // @[RegisterRouter.scala:87:24]
wire out_rimask_991 = |_out_rimask_T_991; // @[RegisterRouter.scala:87:24]
wire out_wimask_991 = &_out_wimask_T_991; // @[RegisterRouter.scala:87:24]
wire out_romask_991 = |_out_romask_T_991; // @[RegisterRouter.scala:87:24]
wire out_womask_991 = &_out_womask_T_991; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_991 = out_rivalid_1_845 & out_rimask_991; // @[RegisterRouter.scala:87:24]
wire _out_T_9644 = out_f_rivalid_991; // @[RegisterRouter.scala:87:24]
wire out_f_roready_991 = out_roready_1_845 & out_romask_991; // @[RegisterRouter.scala:87:24]
wire _out_T_9645 = out_f_roready_991; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_991 = out_wivalid_1_845 & out_wimask_991; // @[RegisterRouter.scala:87:24]
wire out_f_woready_991 = out_woready_1_845 & out_womask_991; // @[RegisterRouter.scala:87:24]
wire _out_T_9646 = ~out_rimask_991; // @[RegisterRouter.scala:87:24]
wire _out_T_9647 = ~out_wimask_991; // @[RegisterRouter.scala:87:24]
wire _out_T_9648 = ~out_romask_991; // @[RegisterRouter.scala:87:24]
wire _out_T_9649 = ~out_womask_991; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_847 = {hi_139, flags_0_go, _out_prepend_T_847}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_9650 = out_prepend_847; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_9651 = _out_T_9650; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_848 = _out_T_9651; // @[RegisterRouter.scala:87:24]
wire out_rimask_992 = |_out_rimask_T_992; // @[RegisterRouter.scala:87:24]
wire out_wimask_992 = &_out_wimask_T_992; // @[RegisterRouter.scala:87:24]
wire out_romask_992 = |_out_romask_T_992; // @[RegisterRouter.scala:87:24]
wire out_womask_992 = &_out_womask_T_992; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_992 = out_rivalid_1_846 & out_rimask_992; // @[RegisterRouter.scala:87:24]
wire _out_T_9653 = out_f_rivalid_992; // @[RegisterRouter.scala:87:24]
wire out_f_roready_992 = out_roready_1_846 & out_romask_992; // @[RegisterRouter.scala:87:24]
wire _out_T_9654 = out_f_roready_992; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_992 = out_wivalid_1_846 & out_wimask_992; // @[RegisterRouter.scala:87:24]
wire out_f_woready_992 = out_woready_1_846 & out_womask_992; // @[RegisterRouter.scala:87:24]
wire _out_T_9655 = ~out_rimask_992; // @[RegisterRouter.scala:87:24]
wire _out_T_9656 = ~out_wimask_992; // @[RegisterRouter.scala:87:24]
wire _out_T_9657 = ~out_romask_992; // @[RegisterRouter.scala:87:24]
wire _out_T_9658 = ~out_womask_992; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_848 = {hi_140, flags_0_go, _out_prepend_T_848}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_9659 = out_prepend_848; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_9660 = _out_T_9659; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_849 = _out_T_9660; // @[RegisterRouter.scala:87:24]
wire out_rimask_993 = |_out_rimask_T_993; // @[RegisterRouter.scala:87:24]
wire out_wimask_993 = &_out_wimask_T_993; // @[RegisterRouter.scala:87:24]
wire out_romask_993 = |_out_romask_T_993; // @[RegisterRouter.scala:87:24]
wire out_womask_993 = &_out_womask_T_993; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_993 = out_rivalid_1_847 & out_rimask_993; // @[RegisterRouter.scala:87:24]
wire _out_T_9662 = out_f_rivalid_993; // @[RegisterRouter.scala:87:24]
wire out_f_roready_993 = out_roready_1_847 & out_romask_993; // @[RegisterRouter.scala:87:24]
wire _out_T_9663 = out_f_roready_993; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_993 = out_wivalid_1_847 & out_wimask_993; // @[RegisterRouter.scala:87:24]
wire out_f_woready_993 = out_woready_1_847 & out_womask_993; // @[RegisterRouter.scala:87:24]
wire _out_T_9664 = ~out_rimask_993; // @[RegisterRouter.scala:87:24]
wire _out_T_9665 = ~out_wimask_993; // @[RegisterRouter.scala:87:24]
wire _out_T_9666 = ~out_romask_993; // @[RegisterRouter.scala:87:24]
wire _out_T_9667 = ~out_womask_993; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_849 = {hi_141, flags_0_go, _out_prepend_T_849}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_9668 = out_prepend_849; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_9669 = _out_T_9668; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_850 = _out_T_9669; // @[RegisterRouter.scala:87:24]
wire out_rimask_994 = |_out_rimask_T_994; // @[RegisterRouter.scala:87:24]
wire out_wimask_994 = &_out_wimask_T_994; // @[RegisterRouter.scala:87:24]
wire out_romask_994 = |_out_romask_T_994; // @[RegisterRouter.scala:87:24]
wire out_womask_994 = &_out_womask_T_994; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_994 = out_rivalid_1_848 & out_rimask_994; // @[RegisterRouter.scala:87:24]
wire _out_T_9671 = out_f_rivalid_994; // @[RegisterRouter.scala:87:24]
wire out_f_roready_994 = out_roready_1_848 & out_romask_994; // @[RegisterRouter.scala:87:24]
wire _out_T_9672 = out_f_roready_994; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_994 = out_wivalid_1_848 & out_wimask_994; // @[RegisterRouter.scala:87:24]
wire out_f_woready_994 = out_woready_1_848 & out_womask_994; // @[RegisterRouter.scala:87:24]
wire _out_T_9673 = ~out_rimask_994; // @[RegisterRouter.scala:87:24]
wire _out_T_9674 = ~out_wimask_994; // @[RegisterRouter.scala:87:24]
wire _out_T_9675 = ~out_romask_994; // @[RegisterRouter.scala:87:24]
wire _out_T_9676 = ~out_womask_994; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_850 = {hi_142, flags_0_go, _out_prepend_T_850}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_9677 = out_prepend_850; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_9678 = _out_T_9677; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_851 = _out_T_9678; // @[RegisterRouter.scala:87:24]
wire out_rimask_995 = |_out_rimask_T_995; // @[RegisterRouter.scala:87:24]
wire out_wimask_995 = &_out_wimask_T_995; // @[RegisterRouter.scala:87:24]
wire out_romask_995 = |_out_romask_T_995; // @[RegisterRouter.scala:87:24]
wire out_womask_995 = &_out_womask_T_995; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_995 = out_rivalid_1_849 & out_rimask_995; // @[RegisterRouter.scala:87:24]
wire _out_T_9680 = out_f_rivalid_995; // @[RegisterRouter.scala:87:24]
wire out_f_roready_995 = out_roready_1_849 & out_romask_995; // @[RegisterRouter.scala:87:24]
wire _out_T_9681 = out_f_roready_995; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_995 = out_wivalid_1_849 & out_wimask_995; // @[RegisterRouter.scala:87:24]
wire out_f_woready_995 = out_woready_1_849 & out_womask_995; // @[RegisterRouter.scala:87:24]
wire _out_T_9682 = ~out_rimask_995; // @[RegisterRouter.scala:87:24]
wire _out_T_9683 = ~out_wimask_995; // @[RegisterRouter.scala:87:24]
wire _out_T_9684 = ~out_romask_995; // @[RegisterRouter.scala:87:24]
wire _out_T_9685 = ~out_womask_995; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_851 = {hi_143, flags_0_go, _out_prepend_T_851}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_9686 = out_prepend_851; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_9687 = _out_T_9686; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_852 = _out_T_9687; // @[RegisterRouter.scala:87:24]
wire out_rimask_996 = |_out_rimask_T_996; // @[RegisterRouter.scala:87:24]
wire out_wimask_996 = &_out_wimask_T_996; // @[RegisterRouter.scala:87:24]
wire out_romask_996 = |_out_romask_T_996; // @[RegisterRouter.scala:87:24]
wire out_womask_996 = &_out_womask_T_996; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_996 = out_rivalid_1_850 & out_rimask_996; // @[RegisterRouter.scala:87:24]
wire _out_T_9689 = out_f_rivalid_996; // @[RegisterRouter.scala:87:24]
wire out_f_roready_996 = out_roready_1_850 & out_romask_996; // @[RegisterRouter.scala:87:24]
wire _out_T_9690 = out_f_roready_996; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_996 = out_wivalid_1_850 & out_wimask_996; // @[RegisterRouter.scala:87:24]
wire out_f_woready_996 = out_woready_1_850 & out_womask_996; // @[RegisterRouter.scala:87:24]
wire _out_T_9691 = ~out_rimask_996; // @[RegisterRouter.scala:87:24]
wire _out_T_9692 = ~out_wimask_996; // @[RegisterRouter.scala:87:24]
wire _out_T_9693 = ~out_romask_996; // @[RegisterRouter.scala:87:24]
wire _out_T_9694 = ~out_womask_996; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_852 = {hi_144, flags_0_go, _out_prepend_T_852}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_9695 = out_prepend_852; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_9696 = _out_T_9695; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_145 = _out_T_9696; // @[MuxLiteral.scala:49:48]
wire out_rimask_997 = |_out_rimask_T_997; // @[RegisterRouter.scala:87:24]
wire out_wimask_997 = &_out_wimask_T_997; // @[RegisterRouter.scala:87:24]
wire out_romask_997 = |_out_romask_T_997; // @[RegisterRouter.scala:87:24]
wire out_womask_997 = &_out_womask_T_997; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_997 = out_rivalid_1_851 & out_rimask_997; // @[RegisterRouter.scala:87:24]
wire _out_T_9698 = out_f_rivalid_997; // @[RegisterRouter.scala:87:24]
wire out_f_roready_997 = out_roready_1_851 & out_romask_997; // @[RegisterRouter.scala:87:24]
wire _out_T_9699 = out_f_roready_997; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_997 = out_wivalid_1_851 & out_wimask_997; // @[RegisterRouter.scala:87:24]
wire out_f_woready_997 = out_woready_1_851 & out_womask_997; // @[RegisterRouter.scala:87:24]
wire _out_T_9700 = ~out_rimask_997; // @[RegisterRouter.scala:87:24]
wire _out_T_9701 = ~out_wimask_997; // @[RegisterRouter.scala:87:24]
wire _out_T_9702 = ~out_romask_997; // @[RegisterRouter.scala:87:24]
wire _out_T_9703 = ~out_womask_997; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9705 = _out_T_9704; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_853 = _out_T_9705; // @[RegisterRouter.scala:87:24]
wire out_rimask_998 = |_out_rimask_T_998; // @[RegisterRouter.scala:87:24]
wire out_wimask_998 = &_out_wimask_T_998; // @[RegisterRouter.scala:87:24]
wire out_romask_998 = |_out_romask_T_998; // @[RegisterRouter.scala:87:24]
wire out_womask_998 = &_out_womask_T_998; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_998 = out_rivalid_1_852 & out_rimask_998; // @[RegisterRouter.scala:87:24]
wire _out_T_9707 = out_f_rivalid_998; // @[RegisterRouter.scala:87:24]
wire out_f_roready_998 = out_roready_1_852 & out_romask_998; // @[RegisterRouter.scala:87:24]
wire _out_T_9708 = out_f_roready_998; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_998 = out_wivalid_1_852 & out_wimask_998; // @[RegisterRouter.scala:87:24]
wire out_f_woready_998 = out_woready_1_852 & out_womask_998; // @[RegisterRouter.scala:87:24]
wire _out_T_9709 = ~out_rimask_998; // @[RegisterRouter.scala:87:24]
wire _out_T_9710 = ~out_wimask_998; // @[RegisterRouter.scala:87:24]
wire _out_T_9711 = ~out_romask_998; // @[RegisterRouter.scala:87:24]
wire _out_T_9712 = ~out_womask_998; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_853 = {hi_178, flags_0_go, _out_prepend_T_853}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_9713 = out_prepend_853; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_9714 = _out_T_9713; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_854 = _out_T_9714; // @[RegisterRouter.scala:87:24]
wire out_rimask_999 = |_out_rimask_T_999; // @[RegisterRouter.scala:87:24]
wire out_wimask_999 = &_out_wimask_T_999; // @[RegisterRouter.scala:87:24]
wire out_romask_999 = |_out_romask_T_999; // @[RegisterRouter.scala:87:24]
wire out_womask_999 = &_out_womask_T_999; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_999 = out_rivalid_1_853 & out_rimask_999; // @[RegisterRouter.scala:87:24]
wire _out_T_9716 = out_f_rivalid_999; // @[RegisterRouter.scala:87:24]
wire out_f_roready_999 = out_roready_1_853 & out_romask_999; // @[RegisterRouter.scala:87:24]
wire _out_T_9717 = out_f_roready_999; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_999 = out_wivalid_1_853 & out_wimask_999; // @[RegisterRouter.scala:87:24]
wire out_f_woready_999 = out_woready_1_853 & out_womask_999; // @[RegisterRouter.scala:87:24]
wire _out_T_9718 = ~out_rimask_999; // @[RegisterRouter.scala:87:24]
wire _out_T_9719 = ~out_wimask_999; // @[RegisterRouter.scala:87:24]
wire _out_T_9720 = ~out_romask_999; // @[RegisterRouter.scala:87:24]
wire _out_T_9721 = ~out_womask_999; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_854 = {hi_179, flags_0_go, _out_prepend_T_854}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_9722 = out_prepend_854; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_9723 = _out_T_9722; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_855 = _out_T_9723; // @[RegisterRouter.scala:87:24]
wire out_rimask_1000 = |_out_rimask_T_1000; // @[RegisterRouter.scala:87:24]
wire out_wimask_1000 = &_out_wimask_T_1000; // @[RegisterRouter.scala:87:24]
wire out_romask_1000 = |_out_romask_T_1000; // @[RegisterRouter.scala:87:24]
wire out_womask_1000 = &_out_womask_T_1000; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1000 = out_rivalid_1_854 & out_rimask_1000; // @[RegisterRouter.scala:87:24]
wire _out_T_9725 = out_f_rivalid_1000; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1000 = out_roready_1_854 & out_romask_1000; // @[RegisterRouter.scala:87:24]
wire _out_T_9726 = out_f_roready_1000; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1000 = out_wivalid_1_854 & out_wimask_1000; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1000 = out_woready_1_854 & out_womask_1000; // @[RegisterRouter.scala:87:24]
wire _out_T_9727 = ~out_rimask_1000; // @[RegisterRouter.scala:87:24]
wire _out_T_9728 = ~out_wimask_1000; // @[RegisterRouter.scala:87:24]
wire _out_T_9729 = ~out_romask_1000; // @[RegisterRouter.scala:87:24]
wire _out_T_9730 = ~out_womask_1000; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_855 = {hi_180, flags_0_go, _out_prepend_T_855}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_9731 = out_prepend_855; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_9732 = _out_T_9731; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_856 = _out_T_9732; // @[RegisterRouter.scala:87:24]
wire out_rimask_1001 = |_out_rimask_T_1001; // @[RegisterRouter.scala:87:24]
wire out_wimask_1001 = &_out_wimask_T_1001; // @[RegisterRouter.scala:87:24]
wire out_romask_1001 = |_out_romask_T_1001; // @[RegisterRouter.scala:87:24]
wire out_womask_1001 = &_out_womask_T_1001; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1001 = out_rivalid_1_855 & out_rimask_1001; // @[RegisterRouter.scala:87:24]
wire _out_T_9734 = out_f_rivalid_1001; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1001 = out_roready_1_855 & out_romask_1001; // @[RegisterRouter.scala:87:24]
wire _out_T_9735 = out_f_roready_1001; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1001 = out_wivalid_1_855 & out_wimask_1001; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1001 = out_woready_1_855 & out_womask_1001; // @[RegisterRouter.scala:87:24]
wire _out_T_9736 = ~out_rimask_1001; // @[RegisterRouter.scala:87:24]
wire _out_T_9737 = ~out_wimask_1001; // @[RegisterRouter.scala:87:24]
wire _out_T_9738 = ~out_romask_1001; // @[RegisterRouter.scala:87:24]
wire _out_T_9739 = ~out_womask_1001; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_856 = {hi_181, flags_0_go, _out_prepend_T_856}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_9740 = out_prepend_856; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_9741 = _out_T_9740; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_857 = _out_T_9741; // @[RegisterRouter.scala:87:24]
wire out_rimask_1002 = |_out_rimask_T_1002; // @[RegisterRouter.scala:87:24]
wire out_wimask_1002 = &_out_wimask_T_1002; // @[RegisterRouter.scala:87:24]
wire out_romask_1002 = |_out_romask_T_1002; // @[RegisterRouter.scala:87:24]
wire out_womask_1002 = &_out_womask_T_1002; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1002 = out_rivalid_1_856 & out_rimask_1002; // @[RegisterRouter.scala:87:24]
wire _out_T_9743 = out_f_rivalid_1002; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1002 = out_roready_1_856 & out_romask_1002; // @[RegisterRouter.scala:87:24]
wire _out_T_9744 = out_f_roready_1002; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1002 = out_wivalid_1_856 & out_wimask_1002; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1002 = out_woready_1_856 & out_womask_1002; // @[RegisterRouter.scala:87:24]
wire _out_T_9745 = ~out_rimask_1002; // @[RegisterRouter.scala:87:24]
wire _out_T_9746 = ~out_wimask_1002; // @[RegisterRouter.scala:87:24]
wire _out_T_9747 = ~out_romask_1002; // @[RegisterRouter.scala:87:24]
wire _out_T_9748 = ~out_womask_1002; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_857 = {hi_182, flags_0_go, _out_prepend_T_857}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_9749 = out_prepend_857; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_9750 = _out_T_9749; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_858 = _out_T_9750; // @[RegisterRouter.scala:87:24]
wire out_rimask_1003 = |_out_rimask_T_1003; // @[RegisterRouter.scala:87:24]
wire out_wimask_1003 = &_out_wimask_T_1003; // @[RegisterRouter.scala:87:24]
wire out_romask_1003 = |_out_romask_T_1003; // @[RegisterRouter.scala:87:24]
wire out_womask_1003 = &_out_womask_T_1003; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1003 = out_rivalid_1_857 & out_rimask_1003; // @[RegisterRouter.scala:87:24]
wire _out_T_9752 = out_f_rivalid_1003; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1003 = out_roready_1_857 & out_romask_1003; // @[RegisterRouter.scala:87:24]
wire _out_T_9753 = out_f_roready_1003; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1003 = out_wivalid_1_857 & out_wimask_1003; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1003 = out_woready_1_857 & out_womask_1003; // @[RegisterRouter.scala:87:24]
wire _out_T_9754 = ~out_rimask_1003; // @[RegisterRouter.scala:87:24]
wire _out_T_9755 = ~out_wimask_1003; // @[RegisterRouter.scala:87:24]
wire _out_T_9756 = ~out_romask_1003; // @[RegisterRouter.scala:87:24]
wire _out_T_9757 = ~out_womask_1003; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_858 = {hi_183, flags_0_go, _out_prepend_T_858}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_9758 = out_prepend_858; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_9759 = _out_T_9758; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_859 = _out_T_9759; // @[RegisterRouter.scala:87:24]
wire out_rimask_1004 = |_out_rimask_T_1004; // @[RegisterRouter.scala:87:24]
wire out_wimask_1004 = &_out_wimask_T_1004; // @[RegisterRouter.scala:87:24]
wire out_romask_1004 = |_out_romask_T_1004; // @[RegisterRouter.scala:87:24]
wire out_womask_1004 = &_out_womask_T_1004; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1004 = out_rivalid_1_858 & out_rimask_1004; // @[RegisterRouter.scala:87:24]
wire _out_T_9761 = out_f_rivalid_1004; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1004 = out_roready_1_858 & out_romask_1004; // @[RegisterRouter.scala:87:24]
wire _out_T_9762 = out_f_roready_1004; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1004 = out_wivalid_1_858 & out_wimask_1004; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1004 = out_woready_1_858 & out_womask_1004; // @[RegisterRouter.scala:87:24]
wire _out_T_9763 = ~out_rimask_1004; // @[RegisterRouter.scala:87:24]
wire _out_T_9764 = ~out_wimask_1004; // @[RegisterRouter.scala:87:24]
wire _out_T_9765 = ~out_romask_1004; // @[RegisterRouter.scala:87:24]
wire _out_T_9766 = ~out_womask_1004; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_859 = {hi_184, flags_0_go, _out_prepend_T_859}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_9767 = out_prepend_859; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_9768 = _out_T_9767; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_150 = _out_T_9768; // @[MuxLiteral.scala:49:48]
wire out_rimask_1005 = |_out_rimask_T_1005; // @[RegisterRouter.scala:87:24]
wire out_wimask_1005 = &_out_wimask_T_1005; // @[RegisterRouter.scala:87:24]
wire out_romask_1005 = |_out_romask_T_1005; // @[RegisterRouter.scala:87:24]
wire out_womask_1005 = &_out_womask_T_1005; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1005 = out_rivalid_1_859 & out_rimask_1005; // @[RegisterRouter.scala:87:24]
wire _out_T_9770 = out_f_rivalid_1005; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1005 = out_roready_1_859 & out_romask_1005; // @[RegisterRouter.scala:87:24]
wire _out_T_9771 = out_f_roready_1005; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1005 = out_wivalid_1_859 & out_wimask_1005; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1005 = out_woready_1_859 & out_womask_1005; // @[RegisterRouter.scala:87:24]
wire _out_T_9772 = ~out_rimask_1005; // @[RegisterRouter.scala:87:24]
wire _out_T_9773 = ~out_wimask_1005; // @[RegisterRouter.scala:87:24]
wire _out_T_9774 = ~out_romask_1005; // @[RegisterRouter.scala:87:24]
wire _out_T_9775 = ~out_womask_1005; // @[RegisterRouter.scala:87:24]
wire out_rimask_1006 = |_out_rimask_T_1006; // @[RegisterRouter.scala:87:24]
wire out_wimask_1006 = &_out_wimask_T_1006; // @[RegisterRouter.scala:87:24]
wire out_romask_1006 = |_out_romask_T_1006; // @[RegisterRouter.scala:87:24]
wire out_womask_1006 = &_out_womask_T_1006; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1006 = out_rivalid_1_860 & out_rimask_1006; // @[RegisterRouter.scala:87:24]
wire _out_T_9779 = out_f_rivalid_1006; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1006 = out_roready_1_860 & out_romask_1006; // @[RegisterRouter.scala:87:24]
wire _out_T_9780 = out_f_roready_1006; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1006 = out_wivalid_1_860 & out_wimask_1006; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1006 = out_woready_1_860 & out_womask_1006; // @[RegisterRouter.scala:87:24]
wire _out_T_9781 = ~out_rimask_1006; // @[RegisterRouter.scala:87:24]
wire _out_T_9782 = ~out_wimask_1006; // @[RegisterRouter.scala:87:24]
wire _out_T_9783 = ~out_romask_1006; // @[RegisterRouter.scala:87:24]
wire _out_T_9784 = ~out_womask_1006; // @[RegisterRouter.scala:87:24]
wire out_rimask_1007 = |_out_rimask_T_1007; // @[RegisterRouter.scala:87:24]
wire out_wimask_1007 = &_out_wimask_T_1007; // @[RegisterRouter.scala:87:24]
wire out_romask_1007 = |_out_romask_T_1007; // @[RegisterRouter.scala:87:24]
wire out_womask_1007 = &_out_womask_T_1007; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1007 = out_rivalid_1_861 & out_rimask_1007; // @[RegisterRouter.scala:87:24]
wire _out_T_9788 = out_f_rivalid_1007; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1007 = out_roready_1_861 & out_romask_1007; // @[RegisterRouter.scala:87:24]
wire _out_T_9789 = out_f_roready_1007; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1007 = out_wivalid_1_861 & out_wimask_1007; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1007 = out_woready_1_861 & out_womask_1007; // @[RegisterRouter.scala:87:24]
wire _out_T_9790 = ~out_rimask_1007; // @[RegisterRouter.scala:87:24]
wire _out_T_9791 = ~out_wimask_1007; // @[RegisterRouter.scala:87:24]
wire _out_T_9792 = ~out_romask_1007; // @[RegisterRouter.scala:87:24]
wire _out_T_9793 = ~out_womask_1007; // @[RegisterRouter.scala:87:24]
wire out_rimask_1008 = |_out_rimask_T_1008; // @[RegisterRouter.scala:87:24]
wire out_wimask_1008 = &_out_wimask_T_1008; // @[RegisterRouter.scala:87:24]
wire out_romask_1008 = |_out_romask_T_1008; // @[RegisterRouter.scala:87:24]
wire out_womask_1008 = &_out_womask_T_1008; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1008 = out_rivalid_1_862 & out_rimask_1008; // @[RegisterRouter.scala:87:24]
wire _out_T_9797 = out_f_rivalid_1008; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1008 = out_roready_1_862 & out_romask_1008; // @[RegisterRouter.scala:87:24]
wire _out_T_9798 = out_f_roready_1008; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1008 = out_wivalid_1_862 & out_wimask_1008; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1008 = out_woready_1_862 & out_womask_1008; // @[RegisterRouter.scala:87:24]
wire _out_T_9799 = ~out_rimask_1008; // @[RegisterRouter.scala:87:24]
wire _out_T_9800 = ~out_wimask_1008; // @[RegisterRouter.scala:87:24]
wire _out_T_9801 = ~out_romask_1008; // @[RegisterRouter.scala:87:24]
wire _out_T_9802 = ~out_womask_1008; // @[RegisterRouter.scala:87:24]
wire out_rimask_1009 = |_out_rimask_T_1009; // @[RegisterRouter.scala:87:24]
wire out_wimask_1009 = &_out_wimask_T_1009; // @[RegisterRouter.scala:87:24]
wire out_romask_1009 = |_out_romask_T_1009; // @[RegisterRouter.scala:87:24]
wire out_womask_1009 = &_out_womask_T_1009; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1009 = out_rivalid_1_863 & out_rimask_1009; // @[RegisterRouter.scala:87:24]
wire _out_T_9806 = out_f_rivalid_1009; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1009 = out_roready_1_863 & out_romask_1009; // @[RegisterRouter.scala:87:24]
wire _out_T_9807 = out_f_roready_1009; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1009 = out_wivalid_1_863 & out_wimask_1009; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1009 = out_woready_1_863 & out_womask_1009; // @[RegisterRouter.scala:87:24]
wire _out_T_9808 = ~out_rimask_1009; // @[RegisterRouter.scala:87:24]
wire _out_T_9809 = ~out_wimask_1009; // @[RegisterRouter.scala:87:24]
wire _out_T_9810 = ~out_romask_1009; // @[RegisterRouter.scala:87:24]
wire _out_T_9811 = ~out_womask_1009; // @[RegisterRouter.scala:87:24]
wire out_rimask_1010 = |_out_rimask_T_1010; // @[RegisterRouter.scala:87:24]
wire out_wimask_1010 = &_out_wimask_T_1010; // @[RegisterRouter.scala:87:24]
wire out_romask_1010 = |_out_romask_T_1010; // @[RegisterRouter.scala:87:24]
wire out_womask_1010 = &_out_womask_T_1010; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1010 = out_rivalid_1_864 & out_rimask_1010; // @[RegisterRouter.scala:87:24]
wire _out_T_9815 = out_f_rivalid_1010; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1010 = out_roready_1_864 & out_romask_1010; // @[RegisterRouter.scala:87:24]
wire _out_T_9816 = out_f_roready_1010; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1010 = out_wivalid_1_864 & out_wimask_1010; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1010 = out_woready_1_864 & out_womask_1010; // @[RegisterRouter.scala:87:24]
wire _out_T_9817 = ~out_rimask_1010; // @[RegisterRouter.scala:87:24]
wire _out_T_9818 = ~out_wimask_1010; // @[RegisterRouter.scala:87:24]
wire _out_T_9819 = ~out_romask_1010; // @[RegisterRouter.scala:87:24]
wire _out_T_9820 = ~out_womask_1010; // @[RegisterRouter.scala:87:24]
wire out_rimask_1011 = |_out_rimask_T_1011; // @[RegisterRouter.scala:87:24]
wire out_wimask_1011 = &_out_wimask_T_1011; // @[RegisterRouter.scala:87:24]
wire out_romask_1011 = |_out_romask_T_1011; // @[RegisterRouter.scala:87:24]
wire out_womask_1011 = &_out_womask_T_1011; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1011 = out_rivalid_1_865 & out_rimask_1011; // @[RegisterRouter.scala:87:24]
wire _out_T_9824 = out_f_rivalid_1011; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1011 = out_roready_1_865 & out_romask_1011; // @[RegisterRouter.scala:87:24]
wire _out_T_9825 = out_f_roready_1011; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1011 = out_wivalid_1_865 & out_wimask_1011; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1011 = out_woready_1_865 & out_womask_1011; // @[RegisterRouter.scala:87:24]
wire _out_T_9826 = ~out_rimask_1011; // @[RegisterRouter.scala:87:24]
wire _out_T_9827 = ~out_wimask_1011; // @[RegisterRouter.scala:87:24]
wire _out_T_9828 = ~out_romask_1011; // @[RegisterRouter.scala:87:24]
wire _out_T_9829 = ~out_womask_1011; // @[RegisterRouter.scala:87:24]
wire out_rimask_1012 = |_out_rimask_T_1012; // @[RegisterRouter.scala:87:24]
wire out_wimask_1012 = &_out_wimask_T_1012; // @[RegisterRouter.scala:87:24]
wire out_romask_1012 = |_out_romask_T_1012; // @[RegisterRouter.scala:87:24]
wire out_womask_1012 = &_out_womask_T_1012; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1012 = out_rivalid_1_866 & out_rimask_1012; // @[RegisterRouter.scala:87:24]
wire _out_T_9833 = out_f_rivalid_1012; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1012 = out_roready_1_866 & out_romask_1012; // @[RegisterRouter.scala:87:24]
wire _out_T_9834 = out_f_roready_1012; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1012 = out_wivalid_1_866 & out_wimask_1012; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1012 = out_woready_1_866 & out_womask_1012; // @[RegisterRouter.scala:87:24]
wire _out_T_9835 = ~out_rimask_1012; // @[RegisterRouter.scala:87:24]
wire _out_T_9836 = ~out_wimask_1012; // @[RegisterRouter.scala:87:24]
wire _out_T_9837 = ~out_romask_1012; // @[RegisterRouter.scala:87:24]
wire _out_T_9838 = ~out_womask_1012; // @[RegisterRouter.scala:87:24]
wire out_rimask_1013 = |_out_rimask_T_1013; // @[RegisterRouter.scala:87:24]
wire out_wimask_1013 = &_out_wimask_T_1013; // @[RegisterRouter.scala:87:24]
wire out_romask_1013 = |_out_romask_T_1013; // @[RegisterRouter.scala:87:24]
wire out_womask_1013 = &_out_womask_T_1013; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1013 = out_rivalid_1_867 & out_rimask_1013; // @[RegisterRouter.scala:87:24]
wire _out_T_9842 = out_f_rivalid_1013; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1013 = out_roready_1_867 & out_romask_1013; // @[RegisterRouter.scala:87:24]
wire _out_T_9843 = out_f_roready_1013; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1013 = out_wivalid_1_867 & out_wimask_1013; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1013 = out_woready_1_867 & out_womask_1013; // @[RegisterRouter.scala:87:24]
wire _out_T_9844 = ~out_rimask_1013; // @[RegisterRouter.scala:87:24]
wire _out_T_9845 = ~out_wimask_1013; // @[RegisterRouter.scala:87:24]
wire _out_T_9846 = ~out_romask_1013; // @[RegisterRouter.scala:87:24]
wire _out_T_9847 = ~out_womask_1013; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9849 = _out_T_9848; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_867 = _out_T_9849; // @[RegisterRouter.scala:87:24]
wire out_rimask_1014 = |_out_rimask_T_1014; // @[RegisterRouter.scala:87:24]
wire out_wimask_1014 = &_out_wimask_T_1014; // @[RegisterRouter.scala:87:24]
wire out_romask_1014 = |_out_romask_T_1014; // @[RegisterRouter.scala:87:24]
wire out_womask_1014 = &_out_womask_T_1014; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1014 = out_rivalid_1_868 & out_rimask_1014; // @[RegisterRouter.scala:87:24]
wire _out_T_9851 = out_f_rivalid_1014; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1014 = out_roready_1_868 & out_romask_1014; // @[RegisterRouter.scala:87:24]
wire _out_T_9852 = out_f_roready_1014; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1014 = out_wivalid_1_868 & out_wimask_1014; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1014 = out_woready_1_868 & out_womask_1014; // @[RegisterRouter.scala:87:24]
wire _out_T_9853 = ~out_rimask_1014; // @[RegisterRouter.scala:87:24]
wire _out_T_9854 = ~out_wimask_1014; // @[RegisterRouter.scala:87:24]
wire _out_T_9855 = ~out_romask_1014; // @[RegisterRouter.scala:87:24]
wire _out_T_9856 = ~out_womask_1014; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_867 = {hi_570, flags_0_go, _out_prepend_T_867}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_9857 = out_prepend_867; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_9858 = _out_T_9857; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_868 = _out_T_9858; // @[RegisterRouter.scala:87:24]
wire out_rimask_1015 = |_out_rimask_T_1015; // @[RegisterRouter.scala:87:24]
wire out_wimask_1015 = &_out_wimask_T_1015; // @[RegisterRouter.scala:87:24]
wire out_romask_1015 = |_out_romask_T_1015; // @[RegisterRouter.scala:87:24]
wire out_womask_1015 = &_out_womask_T_1015; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1015 = out_rivalid_1_869 & out_rimask_1015; // @[RegisterRouter.scala:87:24]
wire _out_T_9860 = out_f_rivalid_1015; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1015 = out_roready_1_869 & out_romask_1015; // @[RegisterRouter.scala:87:24]
wire _out_T_9861 = out_f_roready_1015; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1015 = out_wivalid_1_869 & out_wimask_1015; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1015 = out_woready_1_869 & out_womask_1015; // @[RegisterRouter.scala:87:24]
wire _out_T_9862 = ~out_rimask_1015; // @[RegisterRouter.scala:87:24]
wire _out_T_9863 = ~out_wimask_1015; // @[RegisterRouter.scala:87:24]
wire _out_T_9864 = ~out_romask_1015; // @[RegisterRouter.scala:87:24]
wire _out_T_9865 = ~out_womask_1015; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_868 = {hi_571, flags_0_go, _out_prepend_T_868}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_9866 = out_prepend_868; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_9867 = _out_T_9866; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_869 = _out_T_9867; // @[RegisterRouter.scala:87:24]
wire out_rimask_1016 = |_out_rimask_T_1016; // @[RegisterRouter.scala:87:24]
wire out_wimask_1016 = &_out_wimask_T_1016; // @[RegisterRouter.scala:87:24]
wire out_romask_1016 = |_out_romask_T_1016; // @[RegisterRouter.scala:87:24]
wire out_womask_1016 = &_out_womask_T_1016; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1016 = out_rivalid_1_870 & out_rimask_1016; // @[RegisterRouter.scala:87:24]
wire _out_T_9869 = out_f_rivalid_1016; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1016 = out_roready_1_870 & out_romask_1016; // @[RegisterRouter.scala:87:24]
wire _out_T_9870 = out_f_roready_1016; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1016 = out_wivalid_1_870 & out_wimask_1016; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1016 = out_woready_1_870 & out_womask_1016; // @[RegisterRouter.scala:87:24]
wire _out_T_9871 = ~out_rimask_1016; // @[RegisterRouter.scala:87:24]
wire _out_T_9872 = ~out_wimask_1016; // @[RegisterRouter.scala:87:24]
wire _out_T_9873 = ~out_romask_1016; // @[RegisterRouter.scala:87:24]
wire _out_T_9874 = ~out_womask_1016; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_869 = {hi_572, flags_0_go, _out_prepend_T_869}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_9875 = out_prepend_869; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_9876 = _out_T_9875; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_870 = _out_T_9876; // @[RegisterRouter.scala:87:24]
wire out_rimask_1017 = |_out_rimask_T_1017; // @[RegisterRouter.scala:87:24]
wire out_wimask_1017 = &_out_wimask_T_1017; // @[RegisterRouter.scala:87:24]
wire out_romask_1017 = |_out_romask_T_1017; // @[RegisterRouter.scala:87:24]
wire out_womask_1017 = &_out_womask_T_1017; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1017 = out_rivalid_1_871 & out_rimask_1017; // @[RegisterRouter.scala:87:24]
wire _out_T_9878 = out_f_rivalid_1017; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1017 = out_roready_1_871 & out_romask_1017; // @[RegisterRouter.scala:87:24]
wire _out_T_9879 = out_f_roready_1017; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1017 = out_wivalid_1_871 & out_wimask_1017; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1017 = out_woready_1_871 & out_womask_1017; // @[RegisterRouter.scala:87:24]
wire _out_T_9880 = ~out_rimask_1017; // @[RegisterRouter.scala:87:24]
wire _out_T_9881 = ~out_wimask_1017; // @[RegisterRouter.scala:87:24]
wire _out_T_9882 = ~out_romask_1017; // @[RegisterRouter.scala:87:24]
wire _out_T_9883 = ~out_womask_1017; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_870 = {hi_573, flags_0_go, _out_prepend_T_870}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_9884 = out_prepend_870; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_9885 = _out_T_9884; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_871 = _out_T_9885; // @[RegisterRouter.scala:87:24]
wire out_rimask_1018 = |_out_rimask_T_1018; // @[RegisterRouter.scala:87:24]
wire out_wimask_1018 = &_out_wimask_T_1018; // @[RegisterRouter.scala:87:24]
wire out_romask_1018 = |_out_romask_T_1018; // @[RegisterRouter.scala:87:24]
wire out_womask_1018 = &_out_womask_T_1018; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1018 = out_rivalid_1_872 & out_rimask_1018; // @[RegisterRouter.scala:87:24]
wire _out_T_9887 = out_f_rivalid_1018; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1018 = out_roready_1_872 & out_romask_1018; // @[RegisterRouter.scala:87:24]
wire _out_T_9888 = out_f_roready_1018; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1018 = out_wivalid_1_872 & out_wimask_1018; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1018 = out_woready_1_872 & out_womask_1018; // @[RegisterRouter.scala:87:24]
wire _out_T_9889 = ~out_rimask_1018; // @[RegisterRouter.scala:87:24]
wire _out_T_9890 = ~out_wimask_1018; // @[RegisterRouter.scala:87:24]
wire _out_T_9891 = ~out_romask_1018; // @[RegisterRouter.scala:87:24]
wire _out_T_9892 = ~out_womask_1018; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_871 = {hi_574, flags_0_go, _out_prepend_T_871}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_9893 = out_prepend_871; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_9894 = _out_T_9893; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_872 = _out_T_9894; // @[RegisterRouter.scala:87:24]
wire out_rimask_1019 = |_out_rimask_T_1019; // @[RegisterRouter.scala:87:24]
wire out_wimask_1019 = &_out_wimask_T_1019; // @[RegisterRouter.scala:87:24]
wire out_romask_1019 = |_out_romask_T_1019; // @[RegisterRouter.scala:87:24]
wire out_womask_1019 = &_out_womask_T_1019; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1019 = out_rivalid_1_873 & out_rimask_1019; // @[RegisterRouter.scala:87:24]
wire _out_T_9896 = out_f_rivalid_1019; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1019 = out_roready_1_873 & out_romask_1019; // @[RegisterRouter.scala:87:24]
wire _out_T_9897 = out_f_roready_1019; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1019 = out_wivalid_1_873 & out_wimask_1019; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1019 = out_woready_1_873 & out_womask_1019; // @[RegisterRouter.scala:87:24]
wire _out_T_9898 = ~out_rimask_1019; // @[RegisterRouter.scala:87:24]
wire _out_T_9899 = ~out_wimask_1019; // @[RegisterRouter.scala:87:24]
wire _out_T_9900 = ~out_romask_1019; // @[RegisterRouter.scala:87:24]
wire _out_T_9901 = ~out_womask_1019; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_872 = {hi_575, flags_0_go, _out_prepend_T_872}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_9902 = out_prepend_872; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_9903 = _out_T_9902; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_873 = _out_T_9903; // @[RegisterRouter.scala:87:24]
wire out_rimask_1020 = |_out_rimask_T_1020; // @[RegisterRouter.scala:87:24]
wire out_wimask_1020 = &_out_wimask_T_1020; // @[RegisterRouter.scala:87:24]
wire out_romask_1020 = |_out_romask_T_1020; // @[RegisterRouter.scala:87:24]
wire out_womask_1020 = &_out_womask_T_1020; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1020 = out_rivalid_1_874 & out_rimask_1020; // @[RegisterRouter.scala:87:24]
wire _out_T_9905 = out_f_rivalid_1020; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1020 = out_roready_1_874 & out_romask_1020; // @[RegisterRouter.scala:87:24]
wire _out_T_9906 = out_f_roready_1020; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1020 = out_wivalid_1_874 & out_wimask_1020; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1020 = out_woready_1_874 & out_womask_1020; // @[RegisterRouter.scala:87:24]
wire _out_T_9907 = ~out_rimask_1020; // @[RegisterRouter.scala:87:24]
wire _out_T_9908 = ~out_wimask_1020; // @[RegisterRouter.scala:87:24]
wire _out_T_9909 = ~out_romask_1020; // @[RegisterRouter.scala:87:24]
wire _out_T_9910 = ~out_womask_1020; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_873 = {hi_576, flags_0_go, _out_prepend_T_873}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_9911 = out_prepend_873; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_9912 = _out_T_9911; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_199 = _out_T_9912; // @[MuxLiteral.scala:49:48]
wire out_rimask_1021 = |_out_rimask_T_1021; // @[RegisterRouter.scala:87:24]
wire out_wimask_1021 = &_out_wimask_T_1021; // @[RegisterRouter.scala:87:24]
wire out_romask_1021 = |_out_romask_T_1021; // @[RegisterRouter.scala:87:24]
wire out_womask_1021 = &_out_womask_T_1021; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1021 = out_rivalid_1_875 & out_rimask_1021; // @[RegisterRouter.scala:87:24]
wire _out_T_9914 = out_f_rivalid_1021; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1021 = out_roready_1_875 & out_romask_1021; // @[RegisterRouter.scala:87:24]
wire _out_T_9915 = out_f_roready_1021; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1021 = out_wivalid_1_875 & out_wimask_1021; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1021 = out_woready_1_875 & out_womask_1021; // @[RegisterRouter.scala:87:24]
wire _out_T_9916 = ~out_rimask_1021; // @[RegisterRouter.scala:87:24]
wire _out_T_9917 = ~out_wimask_1021; // @[RegisterRouter.scala:87:24]
wire _out_T_9918 = ~out_romask_1021; // @[RegisterRouter.scala:87:24]
wire _out_T_9919 = ~out_womask_1021; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9921 = _out_T_9920; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_874 = _out_T_9921; // @[RegisterRouter.scala:87:24]
wire out_rimask_1022 = |_out_rimask_T_1022; // @[RegisterRouter.scala:87:24]
wire out_wimask_1022 = &_out_wimask_T_1022; // @[RegisterRouter.scala:87:24]
wire out_romask_1022 = |_out_romask_T_1022; // @[RegisterRouter.scala:87:24]
wire out_womask_1022 = &_out_womask_T_1022; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1022 = out_rivalid_1_876 & out_rimask_1022; // @[RegisterRouter.scala:87:24]
wire _out_T_9923 = out_f_rivalid_1022; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1022 = out_roready_1_876 & out_romask_1022; // @[RegisterRouter.scala:87:24]
wire _out_T_9924 = out_f_roready_1022; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1022 = out_wivalid_1_876 & out_wimask_1022; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1022 = out_woready_1_876 & out_womask_1022; // @[RegisterRouter.scala:87:24]
wire _out_T_9925 = ~out_rimask_1022; // @[RegisterRouter.scala:87:24]
wire _out_T_9926 = ~out_wimask_1022; // @[RegisterRouter.scala:87:24]
wire _out_T_9927 = ~out_romask_1022; // @[RegisterRouter.scala:87:24]
wire _out_T_9928 = ~out_womask_1022; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_874 = {hi_394, flags_0_go, _out_prepend_T_874}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_9929 = out_prepend_874; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_9930 = _out_T_9929; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_875 = _out_T_9930; // @[RegisterRouter.scala:87:24]
wire out_rimask_1023 = |_out_rimask_T_1023; // @[RegisterRouter.scala:87:24]
wire out_wimask_1023 = &_out_wimask_T_1023; // @[RegisterRouter.scala:87:24]
wire out_romask_1023 = |_out_romask_T_1023; // @[RegisterRouter.scala:87:24]
wire out_womask_1023 = &_out_womask_T_1023; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1023 = out_rivalid_1_877 & out_rimask_1023; // @[RegisterRouter.scala:87:24]
wire _out_T_9932 = out_f_rivalid_1023; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1023 = out_roready_1_877 & out_romask_1023; // @[RegisterRouter.scala:87:24]
wire _out_T_9933 = out_f_roready_1023; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1023 = out_wivalid_1_877 & out_wimask_1023; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1023 = out_woready_1_877 & out_womask_1023; // @[RegisterRouter.scala:87:24]
wire _out_T_9934 = ~out_rimask_1023; // @[RegisterRouter.scala:87:24]
wire _out_T_9935 = ~out_wimask_1023; // @[RegisterRouter.scala:87:24]
wire _out_T_9936 = ~out_romask_1023; // @[RegisterRouter.scala:87:24]
wire _out_T_9937 = ~out_womask_1023; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_875 = {hi_395, flags_0_go, _out_prepend_T_875}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_9938 = out_prepend_875; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_9939 = _out_T_9938; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_876 = _out_T_9939; // @[RegisterRouter.scala:87:24]
wire out_rimask_1024 = |_out_rimask_T_1024; // @[RegisterRouter.scala:87:24]
wire out_wimask_1024 = &_out_wimask_T_1024; // @[RegisterRouter.scala:87:24]
wire out_romask_1024 = |_out_romask_T_1024; // @[RegisterRouter.scala:87:24]
wire out_womask_1024 = &_out_womask_T_1024; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1024 = out_rivalid_1_878 & out_rimask_1024; // @[RegisterRouter.scala:87:24]
wire _out_T_9941 = out_f_rivalid_1024; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1024 = out_roready_1_878 & out_romask_1024; // @[RegisterRouter.scala:87:24]
wire _out_T_9942 = out_f_roready_1024; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1024 = out_wivalid_1_878 & out_wimask_1024; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1024 = out_woready_1_878 & out_womask_1024; // @[RegisterRouter.scala:87:24]
wire _out_T_9943 = ~out_rimask_1024; // @[RegisterRouter.scala:87:24]
wire _out_T_9944 = ~out_wimask_1024; // @[RegisterRouter.scala:87:24]
wire _out_T_9945 = ~out_romask_1024; // @[RegisterRouter.scala:87:24]
wire _out_T_9946 = ~out_womask_1024; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_876 = {hi_396, flags_0_go, _out_prepend_T_876}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_9947 = out_prepend_876; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_9948 = _out_T_9947; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_877 = _out_T_9948; // @[RegisterRouter.scala:87:24]
wire out_rimask_1025 = |_out_rimask_T_1025; // @[RegisterRouter.scala:87:24]
wire out_wimask_1025 = &_out_wimask_T_1025; // @[RegisterRouter.scala:87:24]
wire out_romask_1025 = |_out_romask_T_1025; // @[RegisterRouter.scala:87:24]
wire out_womask_1025 = &_out_womask_T_1025; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1025 = out_rivalid_1_879 & out_rimask_1025; // @[RegisterRouter.scala:87:24]
wire _out_T_9950 = out_f_rivalid_1025; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1025 = out_roready_1_879 & out_romask_1025; // @[RegisterRouter.scala:87:24]
wire _out_T_9951 = out_f_roready_1025; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1025 = out_wivalid_1_879 & out_wimask_1025; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1025 = out_woready_1_879 & out_womask_1025; // @[RegisterRouter.scala:87:24]
wire _out_T_9952 = ~out_rimask_1025; // @[RegisterRouter.scala:87:24]
wire _out_T_9953 = ~out_wimask_1025; // @[RegisterRouter.scala:87:24]
wire _out_T_9954 = ~out_romask_1025; // @[RegisterRouter.scala:87:24]
wire _out_T_9955 = ~out_womask_1025; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_877 = {hi_397, flags_0_go, _out_prepend_T_877}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_9956 = out_prepend_877; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_9957 = _out_T_9956; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_878 = _out_T_9957; // @[RegisterRouter.scala:87:24]
wire out_rimask_1026 = |_out_rimask_T_1026; // @[RegisterRouter.scala:87:24]
wire out_wimask_1026 = &_out_wimask_T_1026; // @[RegisterRouter.scala:87:24]
wire out_romask_1026 = |_out_romask_T_1026; // @[RegisterRouter.scala:87:24]
wire out_womask_1026 = &_out_womask_T_1026; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1026 = out_rivalid_1_880 & out_rimask_1026; // @[RegisterRouter.scala:87:24]
wire _out_T_9959 = out_f_rivalid_1026; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1026 = out_roready_1_880 & out_romask_1026; // @[RegisterRouter.scala:87:24]
wire _out_T_9960 = out_f_roready_1026; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1026 = out_wivalid_1_880 & out_wimask_1026; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1026 = out_woready_1_880 & out_womask_1026; // @[RegisterRouter.scala:87:24]
wire _out_T_9961 = ~out_rimask_1026; // @[RegisterRouter.scala:87:24]
wire _out_T_9962 = ~out_wimask_1026; // @[RegisterRouter.scala:87:24]
wire _out_T_9963 = ~out_romask_1026; // @[RegisterRouter.scala:87:24]
wire _out_T_9964 = ~out_womask_1026; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_878 = {hi_398, flags_0_go, _out_prepend_T_878}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_9965 = out_prepend_878; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_9966 = _out_T_9965; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_879 = _out_T_9966; // @[RegisterRouter.scala:87:24]
wire out_rimask_1027 = |_out_rimask_T_1027; // @[RegisterRouter.scala:87:24]
wire out_wimask_1027 = &_out_wimask_T_1027; // @[RegisterRouter.scala:87:24]
wire out_romask_1027 = |_out_romask_T_1027; // @[RegisterRouter.scala:87:24]
wire out_womask_1027 = &_out_womask_T_1027; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1027 = out_rivalid_1_881 & out_rimask_1027; // @[RegisterRouter.scala:87:24]
wire _out_T_9968 = out_f_rivalid_1027; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1027 = out_roready_1_881 & out_romask_1027; // @[RegisterRouter.scala:87:24]
wire _out_T_9969 = out_f_roready_1027; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1027 = out_wivalid_1_881 & out_wimask_1027; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1027 = out_woready_1_881 & out_womask_1027; // @[RegisterRouter.scala:87:24]
wire _out_T_9970 = ~out_rimask_1027; // @[RegisterRouter.scala:87:24]
wire _out_T_9971 = ~out_wimask_1027; // @[RegisterRouter.scala:87:24]
wire _out_T_9972 = ~out_romask_1027; // @[RegisterRouter.scala:87:24]
wire _out_T_9973 = ~out_womask_1027; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_879 = {hi_399, flags_0_go, _out_prepend_T_879}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_9974 = out_prepend_879; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_9975 = _out_T_9974; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_880 = _out_T_9975; // @[RegisterRouter.scala:87:24]
wire out_rimask_1028 = |_out_rimask_T_1028; // @[RegisterRouter.scala:87:24]
wire out_wimask_1028 = &_out_wimask_T_1028; // @[RegisterRouter.scala:87:24]
wire out_romask_1028 = |_out_romask_T_1028; // @[RegisterRouter.scala:87:24]
wire out_womask_1028 = &_out_womask_T_1028; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1028 = out_rivalid_1_882 & out_rimask_1028; // @[RegisterRouter.scala:87:24]
wire _out_T_9977 = out_f_rivalid_1028; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1028 = out_roready_1_882 & out_romask_1028; // @[RegisterRouter.scala:87:24]
wire _out_T_9978 = out_f_roready_1028; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1028 = out_wivalid_1_882 & out_wimask_1028; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1028 = out_woready_1_882 & out_womask_1028; // @[RegisterRouter.scala:87:24]
wire _out_T_9979 = ~out_rimask_1028; // @[RegisterRouter.scala:87:24]
wire _out_T_9980 = ~out_wimask_1028; // @[RegisterRouter.scala:87:24]
wire _out_T_9981 = ~out_romask_1028; // @[RegisterRouter.scala:87:24]
wire _out_T_9982 = ~out_womask_1028; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_880 = {hi_400, flags_0_go, _out_prepend_T_880}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_9983 = out_prepend_880; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_9984 = _out_T_9983; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_177 = _out_T_9984; // @[MuxLiteral.scala:49:48]
wire out_rimask_1029 = |_out_rimask_T_1029; // @[RegisterRouter.scala:87:24]
wire out_wimask_1029 = &_out_wimask_T_1029; // @[RegisterRouter.scala:87:24]
wire out_romask_1029 = |_out_romask_T_1029; // @[RegisterRouter.scala:87:24]
wire out_womask_1029 = &_out_womask_T_1029; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1029 = out_rivalid_1_883 & out_rimask_1029; // @[RegisterRouter.scala:87:24]
wire _out_T_9986 = out_f_rivalid_1029; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1029 = out_roready_1_883 & out_romask_1029; // @[RegisterRouter.scala:87:24]
wire _out_T_9987 = out_f_roready_1029; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1029 = out_wivalid_1_883 & out_wimask_1029; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1029 = out_woready_1_883 & out_womask_1029; // @[RegisterRouter.scala:87:24]
wire _out_T_9988 = ~out_rimask_1029; // @[RegisterRouter.scala:87:24]
wire _out_T_9989 = ~out_wimask_1029; // @[RegisterRouter.scala:87:24]
wire _out_T_9990 = ~out_romask_1029; // @[RegisterRouter.scala:87:24]
wire _out_T_9991 = ~out_womask_1029; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9993 = _out_T_9992; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_881 = _out_T_9993; // @[RegisterRouter.scala:87:24]
wire out_rimask_1030 = |_out_rimask_T_1030; // @[RegisterRouter.scala:87:24]
wire out_wimask_1030 = &_out_wimask_T_1030; // @[RegisterRouter.scala:87:24]
wire out_romask_1030 = |_out_romask_T_1030; // @[RegisterRouter.scala:87:24]
wire out_womask_1030 = &_out_womask_T_1030; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1030 = out_rivalid_1_884 & out_rimask_1030; // @[RegisterRouter.scala:87:24]
wire _out_T_9995 = out_f_rivalid_1030; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1030 = out_roready_1_884 & out_romask_1030; // @[RegisterRouter.scala:87:24]
wire _out_T_9996 = out_f_roready_1030; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1030 = out_wivalid_1_884 & out_wimask_1030; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1030 = out_woready_1_884 & out_womask_1030; // @[RegisterRouter.scala:87:24]
wire _out_T_9997 = ~out_rimask_1030; // @[RegisterRouter.scala:87:24]
wire _out_T_9998 = ~out_wimask_1030; // @[RegisterRouter.scala:87:24]
wire _out_T_9999 = ~out_romask_1030; // @[RegisterRouter.scala:87:24]
wire _out_T_10000 = ~out_womask_1030; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_881 = {hi_434, flags_0_go, _out_prepend_T_881}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_10001 = out_prepend_881; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_10002 = _out_T_10001; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_882 = _out_T_10002; // @[RegisterRouter.scala:87:24]
wire out_rimask_1031 = |_out_rimask_T_1031; // @[RegisterRouter.scala:87:24]
wire out_wimask_1031 = &_out_wimask_T_1031; // @[RegisterRouter.scala:87:24]
wire out_romask_1031 = |_out_romask_T_1031; // @[RegisterRouter.scala:87:24]
wire out_womask_1031 = &_out_womask_T_1031; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1031 = out_rivalid_1_885 & out_rimask_1031; // @[RegisterRouter.scala:87:24]
wire _out_T_10004 = out_f_rivalid_1031; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1031 = out_roready_1_885 & out_romask_1031; // @[RegisterRouter.scala:87:24]
wire _out_T_10005 = out_f_roready_1031; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1031 = out_wivalid_1_885 & out_wimask_1031; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1031 = out_woready_1_885 & out_womask_1031; // @[RegisterRouter.scala:87:24]
wire _out_T_10006 = ~out_rimask_1031; // @[RegisterRouter.scala:87:24]
wire _out_T_10007 = ~out_wimask_1031; // @[RegisterRouter.scala:87:24]
wire _out_T_10008 = ~out_romask_1031; // @[RegisterRouter.scala:87:24]
wire _out_T_10009 = ~out_womask_1031; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_882 = {hi_435, flags_0_go, _out_prepend_T_882}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_10010 = out_prepend_882; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_10011 = _out_T_10010; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_883 = _out_T_10011; // @[RegisterRouter.scala:87:24]
wire out_rimask_1032 = |_out_rimask_T_1032; // @[RegisterRouter.scala:87:24]
wire out_wimask_1032 = &_out_wimask_T_1032; // @[RegisterRouter.scala:87:24]
wire out_romask_1032 = |_out_romask_T_1032; // @[RegisterRouter.scala:87:24]
wire out_womask_1032 = &_out_womask_T_1032; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1032 = out_rivalid_1_886 & out_rimask_1032; // @[RegisterRouter.scala:87:24]
wire _out_T_10013 = out_f_rivalid_1032; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1032 = out_roready_1_886 & out_romask_1032; // @[RegisterRouter.scala:87:24]
wire _out_T_10014 = out_f_roready_1032; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1032 = out_wivalid_1_886 & out_wimask_1032; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1032 = out_woready_1_886 & out_womask_1032; // @[RegisterRouter.scala:87:24]
wire _out_T_10015 = ~out_rimask_1032; // @[RegisterRouter.scala:87:24]
wire _out_T_10016 = ~out_wimask_1032; // @[RegisterRouter.scala:87:24]
wire _out_T_10017 = ~out_romask_1032; // @[RegisterRouter.scala:87:24]
wire _out_T_10018 = ~out_womask_1032; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_883 = {hi_436, flags_0_go, _out_prepend_T_883}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_10019 = out_prepend_883; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_10020 = _out_T_10019; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_884 = _out_T_10020; // @[RegisterRouter.scala:87:24]
wire out_rimask_1033 = |_out_rimask_T_1033; // @[RegisterRouter.scala:87:24]
wire out_wimask_1033 = &_out_wimask_T_1033; // @[RegisterRouter.scala:87:24]
wire out_romask_1033 = |_out_romask_T_1033; // @[RegisterRouter.scala:87:24]
wire out_womask_1033 = &_out_womask_T_1033; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1033 = out_rivalid_1_887 & out_rimask_1033; // @[RegisterRouter.scala:87:24]
wire _out_T_10022 = out_f_rivalid_1033; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1033 = out_roready_1_887 & out_romask_1033; // @[RegisterRouter.scala:87:24]
wire _out_T_10023 = out_f_roready_1033; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1033 = out_wivalid_1_887 & out_wimask_1033; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1033 = out_woready_1_887 & out_womask_1033; // @[RegisterRouter.scala:87:24]
wire _out_T_10024 = ~out_rimask_1033; // @[RegisterRouter.scala:87:24]
wire _out_T_10025 = ~out_wimask_1033; // @[RegisterRouter.scala:87:24]
wire _out_T_10026 = ~out_romask_1033; // @[RegisterRouter.scala:87:24]
wire _out_T_10027 = ~out_womask_1033; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_884 = {hi_437, flags_0_go, _out_prepend_T_884}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_10028 = out_prepend_884; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_10029 = _out_T_10028; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_885 = _out_T_10029; // @[RegisterRouter.scala:87:24]
wire out_rimask_1034 = |_out_rimask_T_1034; // @[RegisterRouter.scala:87:24]
wire out_wimask_1034 = &_out_wimask_T_1034; // @[RegisterRouter.scala:87:24]
wire out_romask_1034 = |_out_romask_T_1034; // @[RegisterRouter.scala:87:24]
wire out_womask_1034 = &_out_womask_T_1034; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1034 = out_rivalid_1_888 & out_rimask_1034; // @[RegisterRouter.scala:87:24]
wire _out_T_10031 = out_f_rivalid_1034; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1034 = out_roready_1_888 & out_romask_1034; // @[RegisterRouter.scala:87:24]
wire _out_T_10032 = out_f_roready_1034; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1034 = out_wivalid_1_888 & out_wimask_1034; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1034 = out_woready_1_888 & out_womask_1034; // @[RegisterRouter.scala:87:24]
wire _out_T_10033 = ~out_rimask_1034; // @[RegisterRouter.scala:87:24]
wire _out_T_10034 = ~out_wimask_1034; // @[RegisterRouter.scala:87:24]
wire _out_T_10035 = ~out_romask_1034; // @[RegisterRouter.scala:87:24]
wire _out_T_10036 = ~out_womask_1034; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_885 = {hi_438, flags_0_go, _out_prepend_T_885}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_10037 = out_prepend_885; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_10038 = _out_T_10037; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_886 = _out_T_10038; // @[RegisterRouter.scala:87:24]
wire out_rimask_1035 = |_out_rimask_T_1035; // @[RegisterRouter.scala:87:24]
wire out_wimask_1035 = &_out_wimask_T_1035; // @[RegisterRouter.scala:87:24]
wire out_romask_1035 = |_out_romask_T_1035; // @[RegisterRouter.scala:87:24]
wire out_womask_1035 = &_out_womask_T_1035; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1035 = out_rivalid_1_889 & out_rimask_1035; // @[RegisterRouter.scala:87:24]
wire _out_T_10040 = out_f_rivalid_1035; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1035 = out_roready_1_889 & out_romask_1035; // @[RegisterRouter.scala:87:24]
wire _out_T_10041 = out_f_roready_1035; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1035 = out_wivalid_1_889 & out_wimask_1035; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1035 = out_woready_1_889 & out_womask_1035; // @[RegisterRouter.scala:87:24]
wire _out_T_10042 = ~out_rimask_1035; // @[RegisterRouter.scala:87:24]
wire _out_T_10043 = ~out_wimask_1035; // @[RegisterRouter.scala:87:24]
wire _out_T_10044 = ~out_romask_1035; // @[RegisterRouter.scala:87:24]
wire _out_T_10045 = ~out_womask_1035; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_886 = {hi_439, flags_0_go, _out_prepend_T_886}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_10046 = out_prepend_886; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_10047 = _out_T_10046; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_887 = _out_T_10047; // @[RegisterRouter.scala:87:24]
wire out_rimask_1036 = |_out_rimask_T_1036; // @[RegisterRouter.scala:87:24]
wire out_wimask_1036 = &_out_wimask_T_1036; // @[RegisterRouter.scala:87:24]
wire out_romask_1036 = |_out_romask_T_1036; // @[RegisterRouter.scala:87:24]
wire out_womask_1036 = &_out_womask_T_1036; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1036 = out_rivalid_1_890 & out_rimask_1036; // @[RegisterRouter.scala:87:24]
wire _out_T_10049 = out_f_rivalid_1036; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1036 = out_roready_1_890 & out_romask_1036; // @[RegisterRouter.scala:87:24]
wire _out_T_10050 = out_f_roready_1036; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1036 = out_wivalid_1_890 & out_wimask_1036; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1036 = out_woready_1_890 & out_womask_1036; // @[RegisterRouter.scala:87:24]
wire _out_T_10051 = ~out_rimask_1036; // @[RegisterRouter.scala:87:24]
wire _out_T_10052 = ~out_wimask_1036; // @[RegisterRouter.scala:87:24]
wire _out_T_10053 = ~out_romask_1036; // @[RegisterRouter.scala:87:24]
wire _out_T_10054 = ~out_womask_1036; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_887 = {hi_440, flags_0_go, _out_prepend_T_887}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_10055 = out_prepend_887; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_10056 = _out_T_10055; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_182 = _out_T_10056; // @[MuxLiteral.scala:49:48]
wire out_rimask_1037 = |_out_rimask_T_1037; // @[RegisterRouter.scala:87:24]
wire out_wimask_1037 = &_out_wimask_T_1037; // @[RegisterRouter.scala:87:24]
wire out_romask_1037 = |_out_romask_T_1037; // @[RegisterRouter.scala:87:24]
wire out_womask_1037 = &_out_womask_T_1037; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1037 = out_rivalid_1_891 & out_rimask_1037; // @[RegisterRouter.scala:87:24]
wire _out_T_10058 = out_f_rivalid_1037; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1037 = out_roready_1_891 & out_romask_1037; // @[RegisterRouter.scala:87:24]
wire _out_T_10059 = out_f_roready_1037; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1037 = out_wivalid_1_891 & out_wimask_1037; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1037 = out_woready_1_891 & out_womask_1037; // @[RegisterRouter.scala:87:24]
wire _out_T_10060 = ~out_rimask_1037; // @[RegisterRouter.scala:87:24]
wire _out_T_10061 = ~out_wimask_1037; // @[RegisterRouter.scala:87:24]
wire _out_T_10062 = ~out_romask_1037; // @[RegisterRouter.scala:87:24]
wire _out_T_10063 = ~out_womask_1037; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10065 = _out_T_10064; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_888 = _out_T_10065; // @[RegisterRouter.scala:87:24]
wire out_rimask_1038 = |_out_rimask_T_1038; // @[RegisterRouter.scala:87:24]
wire out_wimask_1038 = &_out_wimask_T_1038; // @[RegisterRouter.scala:87:24]
wire out_romask_1038 = |_out_romask_T_1038; // @[RegisterRouter.scala:87:24]
wire out_womask_1038 = &_out_womask_T_1038; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1038 = out_rivalid_1_892 & out_rimask_1038; // @[RegisterRouter.scala:87:24]
wire _out_T_10067 = out_f_rivalid_1038; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1038 = out_roready_1_892 & out_romask_1038; // @[RegisterRouter.scala:87:24]
wire _out_T_10068 = out_f_roready_1038; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1038 = out_wivalid_1_892 & out_wimask_1038; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1038 = out_woready_1_892 & out_womask_1038; // @[RegisterRouter.scala:87:24]
wire _out_T_10069 = ~out_rimask_1038; // @[RegisterRouter.scala:87:24]
wire _out_T_10070 = ~out_wimask_1038; // @[RegisterRouter.scala:87:24]
wire _out_T_10071 = ~out_romask_1038; // @[RegisterRouter.scala:87:24]
wire _out_T_10072 = ~out_womask_1038; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_888 = {hi_210, flags_0_go, _out_prepend_T_888}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_10073 = out_prepend_888; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_10074 = _out_T_10073; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_889 = _out_T_10074; // @[RegisterRouter.scala:87:24]
wire out_rimask_1039 = |_out_rimask_T_1039; // @[RegisterRouter.scala:87:24]
wire out_wimask_1039 = &_out_wimask_T_1039; // @[RegisterRouter.scala:87:24]
wire out_romask_1039 = |_out_romask_T_1039; // @[RegisterRouter.scala:87:24]
wire out_womask_1039 = &_out_womask_T_1039; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1039 = out_rivalid_1_893 & out_rimask_1039; // @[RegisterRouter.scala:87:24]
wire _out_T_10076 = out_f_rivalid_1039; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1039 = out_roready_1_893 & out_romask_1039; // @[RegisterRouter.scala:87:24]
wire _out_T_10077 = out_f_roready_1039; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1039 = out_wivalid_1_893 & out_wimask_1039; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1039 = out_woready_1_893 & out_womask_1039; // @[RegisterRouter.scala:87:24]
wire _out_T_10078 = ~out_rimask_1039; // @[RegisterRouter.scala:87:24]
wire _out_T_10079 = ~out_wimask_1039; // @[RegisterRouter.scala:87:24]
wire _out_T_10080 = ~out_romask_1039; // @[RegisterRouter.scala:87:24]
wire _out_T_10081 = ~out_womask_1039; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_889 = {hi_211, flags_0_go, _out_prepend_T_889}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_10082 = out_prepend_889; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_10083 = _out_T_10082; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_890 = _out_T_10083; // @[RegisterRouter.scala:87:24]
wire out_rimask_1040 = |_out_rimask_T_1040; // @[RegisterRouter.scala:87:24]
wire out_wimask_1040 = &_out_wimask_T_1040; // @[RegisterRouter.scala:87:24]
wire out_romask_1040 = |_out_romask_T_1040; // @[RegisterRouter.scala:87:24]
wire out_womask_1040 = &_out_womask_T_1040; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1040 = out_rivalid_1_894 & out_rimask_1040; // @[RegisterRouter.scala:87:24]
wire _out_T_10085 = out_f_rivalid_1040; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1040 = out_roready_1_894 & out_romask_1040; // @[RegisterRouter.scala:87:24]
wire _out_T_10086 = out_f_roready_1040; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1040 = out_wivalid_1_894 & out_wimask_1040; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1040 = out_woready_1_894 & out_womask_1040; // @[RegisterRouter.scala:87:24]
wire _out_T_10087 = ~out_rimask_1040; // @[RegisterRouter.scala:87:24]
wire _out_T_10088 = ~out_wimask_1040; // @[RegisterRouter.scala:87:24]
wire _out_T_10089 = ~out_romask_1040; // @[RegisterRouter.scala:87:24]
wire _out_T_10090 = ~out_womask_1040; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_890 = {hi_212, flags_0_go, _out_prepend_T_890}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_10091 = out_prepend_890; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_10092 = _out_T_10091; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_891 = _out_T_10092; // @[RegisterRouter.scala:87:24]
wire out_rimask_1041 = |_out_rimask_T_1041; // @[RegisterRouter.scala:87:24]
wire out_wimask_1041 = &_out_wimask_T_1041; // @[RegisterRouter.scala:87:24]
wire out_romask_1041 = |_out_romask_T_1041; // @[RegisterRouter.scala:87:24]
wire out_womask_1041 = &_out_womask_T_1041; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1041 = out_rivalid_1_895 & out_rimask_1041; // @[RegisterRouter.scala:87:24]
wire _out_T_10094 = out_f_rivalid_1041; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1041 = out_roready_1_895 & out_romask_1041; // @[RegisterRouter.scala:87:24]
wire _out_T_10095 = out_f_roready_1041; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1041 = out_wivalid_1_895 & out_wimask_1041; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1041 = out_woready_1_895 & out_womask_1041; // @[RegisterRouter.scala:87:24]
wire _out_T_10096 = ~out_rimask_1041; // @[RegisterRouter.scala:87:24]
wire _out_T_10097 = ~out_wimask_1041; // @[RegisterRouter.scala:87:24]
wire _out_T_10098 = ~out_romask_1041; // @[RegisterRouter.scala:87:24]
wire _out_T_10099 = ~out_womask_1041; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_891 = {hi_213, flags_0_go, _out_prepend_T_891}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_10100 = out_prepend_891; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_10101 = _out_T_10100; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_892 = _out_T_10101; // @[RegisterRouter.scala:87:24]
wire out_rimask_1042 = |_out_rimask_T_1042; // @[RegisterRouter.scala:87:24]
wire out_wimask_1042 = &_out_wimask_T_1042; // @[RegisterRouter.scala:87:24]
wire out_romask_1042 = |_out_romask_T_1042; // @[RegisterRouter.scala:87:24]
wire out_womask_1042 = &_out_womask_T_1042; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1042 = out_rivalid_1_896 & out_rimask_1042; // @[RegisterRouter.scala:87:24]
wire _out_T_10103 = out_f_rivalid_1042; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1042 = out_roready_1_896 & out_romask_1042; // @[RegisterRouter.scala:87:24]
wire _out_T_10104 = out_f_roready_1042; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1042 = out_wivalid_1_896 & out_wimask_1042; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1042 = out_woready_1_896 & out_womask_1042; // @[RegisterRouter.scala:87:24]
wire _out_T_10105 = ~out_rimask_1042; // @[RegisterRouter.scala:87:24]
wire _out_T_10106 = ~out_wimask_1042; // @[RegisterRouter.scala:87:24]
wire _out_T_10107 = ~out_romask_1042; // @[RegisterRouter.scala:87:24]
wire _out_T_10108 = ~out_womask_1042; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_892 = {hi_214, flags_0_go, _out_prepend_T_892}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_10109 = out_prepend_892; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_10110 = _out_T_10109; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_893 = _out_T_10110; // @[RegisterRouter.scala:87:24]
wire out_rimask_1043 = |_out_rimask_T_1043; // @[RegisterRouter.scala:87:24]
wire out_wimask_1043 = &_out_wimask_T_1043; // @[RegisterRouter.scala:87:24]
wire out_romask_1043 = |_out_romask_T_1043; // @[RegisterRouter.scala:87:24]
wire out_womask_1043 = &_out_womask_T_1043; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1043 = out_rivalid_1_897 & out_rimask_1043; // @[RegisterRouter.scala:87:24]
wire _out_T_10112 = out_f_rivalid_1043; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1043 = out_roready_1_897 & out_romask_1043; // @[RegisterRouter.scala:87:24]
wire _out_T_10113 = out_f_roready_1043; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1043 = out_wivalid_1_897 & out_wimask_1043; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1043 = out_woready_1_897 & out_womask_1043; // @[RegisterRouter.scala:87:24]
wire _out_T_10114 = ~out_rimask_1043; // @[RegisterRouter.scala:87:24]
wire _out_T_10115 = ~out_wimask_1043; // @[RegisterRouter.scala:87:24]
wire _out_T_10116 = ~out_romask_1043; // @[RegisterRouter.scala:87:24]
wire _out_T_10117 = ~out_womask_1043; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_893 = {hi_215, flags_0_go, _out_prepend_T_893}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_10118 = out_prepend_893; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_10119 = _out_T_10118; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_894 = _out_T_10119; // @[RegisterRouter.scala:87:24]
wire out_rimask_1044 = |_out_rimask_T_1044; // @[RegisterRouter.scala:87:24]
wire out_wimask_1044 = &_out_wimask_T_1044; // @[RegisterRouter.scala:87:24]
wire out_romask_1044 = |_out_romask_T_1044; // @[RegisterRouter.scala:87:24]
wire out_womask_1044 = &_out_womask_T_1044; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1044 = out_rivalid_1_898 & out_rimask_1044; // @[RegisterRouter.scala:87:24]
wire _out_T_10121 = out_f_rivalid_1044; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1044 = out_roready_1_898 & out_romask_1044; // @[RegisterRouter.scala:87:24]
wire _out_T_10122 = out_f_roready_1044; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1044 = out_wivalid_1_898 & out_wimask_1044; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1044 = out_woready_1_898 & out_womask_1044; // @[RegisterRouter.scala:87:24]
wire _out_T_10123 = ~out_rimask_1044; // @[RegisterRouter.scala:87:24]
wire _out_T_10124 = ~out_wimask_1044; // @[RegisterRouter.scala:87:24]
wire _out_T_10125 = ~out_romask_1044; // @[RegisterRouter.scala:87:24]
wire _out_T_10126 = ~out_womask_1044; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_894 = {hi_216, flags_0_go, _out_prepend_T_894}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_10127 = out_prepend_894; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_10128 = _out_T_10127; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_154 = _out_T_10128; // @[MuxLiteral.scala:49:48]
wire out_rimask_1045 = |_out_rimask_T_1045; // @[RegisterRouter.scala:87:24]
wire out_wimask_1045 = &_out_wimask_T_1045; // @[RegisterRouter.scala:87:24]
wire out_romask_1045 = |_out_romask_T_1045; // @[RegisterRouter.scala:87:24]
wire out_womask_1045 = &_out_womask_T_1045; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1045 = out_rivalid_1_899 & out_rimask_1045; // @[RegisterRouter.scala:87:24]
wire _out_T_10130 = out_f_rivalid_1045; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1045 = out_roready_1_899 & out_romask_1045; // @[RegisterRouter.scala:87:24]
wire _out_T_10131 = out_f_roready_1045; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1045 = out_wivalid_1_899 & out_wimask_1045; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1045 = out_woready_1_899 & out_womask_1045; // @[RegisterRouter.scala:87:24]
wire _out_T_10132 = ~out_rimask_1045; // @[RegisterRouter.scala:87:24]
wire _out_T_10133 = ~out_wimask_1045; // @[RegisterRouter.scala:87:24]
wire _out_T_10134 = ~out_romask_1045; // @[RegisterRouter.scala:87:24]
wire _out_T_10135 = ~out_womask_1045; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10137 = _out_T_10136; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_895 = _out_T_10137; // @[RegisterRouter.scala:87:24]
wire out_rimask_1046 = |_out_rimask_T_1046; // @[RegisterRouter.scala:87:24]
wire out_wimask_1046 = &_out_wimask_T_1046; // @[RegisterRouter.scala:87:24]
wire out_romask_1046 = |_out_romask_T_1046; // @[RegisterRouter.scala:87:24]
wire out_womask_1046 = &_out_womask_T_1046; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1046 = out_rivalid_1_900 & out_rimask_1046; // @[RegisterRouter.scala:87:24]
wire _out_T_10139 = out_f_rivalid_1046; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1046 = out_roready_1_900 & out_romask_1046; // @[RegisterRouter.scala:87:24]
wire _out_T_10140 = out_f_roready_1046; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1046 = out_wivalid_1_900 & out_wimask_1046; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1046 = out_woready_1_900 & out_womask_1046; // @[RegisterRouter.scala:87:24]
wire _out_T_10141 = ~out_rimask_1046; // @[RegisterRouter.scala:87:24]
wire _out_T_10142 = ~out_wimask_1046; // @[RegisterRouter.scala:87:24]
wire _out_T_10143 = ~out_romask_1046; // @[RegisterRouter.scala:87:24]
wire _out_T_10144 = ~out_womask_1046; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_895 = {hi_378, flags_0_go, _out_prepend_T_895}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_10145 = out_prepend_895; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_10146 = _out_T_10145; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_896 = _out_T_10146; // @[RegisterRouter.scala:87:24]
wire out_rimask_1047 = |_out_rimask_T_1047; // @[RegisterRouter.scala:87:24]
wire out_wimask_1047 = &_out_wimask_T_1047; // @[RegisterRouter.scala:87:24]
wire out_romask_1047 = |_out_romask_T_1047; // @[RegisterRouter.scala:87:24]
wire out_womask_1047 = &_out_womask_T_1047; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1047 = out_rivalid_1_901 & out_rimask_1047; // @[RegisterRouter.scala:87:24]
wire _out_T_10148 = out_f_rivalid_1047; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1047 = out_roready_1_901 & out_romask_1047; // @[RegisterRouter.scala:87:24]
wire _out_T_10149 = out_f_roready_1047; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1047 = out_wivalid_1_901 & out_wimask_1047; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1047 = out_woready_1_901 & out_womask_1047; // @[RegisterRouter.scala:87:24]
wire _out_T_10150 = ~out_rimask_1047; // @[RegisterRouter.scala:87:24]
wire _out_T_10151 = ~out_wimask_1047; // @[RegisterRouter.scala:87:24]
wire _out_T_10152 = ~out_romask_1047; // @[RegisterRouter.scala:87:24]
wire _out_T_10153 = ~out_womask_1047; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_896 = {hi_379, flags_0_go, _out_prepend_T_896}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_10154 = out_prepend_896; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_10155 = _out_T_10154; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_897 = _out_T_10155; // @[RegisterRouter.scala:87:24]
wire out_rimask_1048 = |_out_rimask_T_1048; // @[RegisterRouter.scala:87:24]
wire out_wimask_1048 = &_out_wimask_T_1048; // @[RegisterRouter.scala:87:24]
wire out_romask_1048 = |_out_romask_T_1048; // @[RegisterRouter.scala:87:24]
wire out_womask_1048 = &_out_womask_T_1048; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1048 = out_rivalid_1_902 & out_rimask_1048; // @[RegisterRouter.scala:87:24]
wire _out_T_10157 = out_f_rivalid_1048; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1048 = out_roready_1_902 & out_romask_1048; // @[RegisterRouter.scala:87:24]
wire _out_T_10158 = out_f_roready_1048; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1048 = out_wivalid_1_902 & out_wimask_1048; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1048 = out_woready_1_902 & out_womask_1048; // @[RegisterRouter.scala:87:24]
wire _out_T_10159 = ~out_rimask_1048; // @[RegisterRouter.scala:87:24]
wire _out_T_10160 = ~out_wimask_1048; // @[RegisterRouter.scala:87:24]
wire _out_T_10161 = ~out_romask_1048; // @[RegisterRouter.scala:87:24]
wire _out_T_10162 = ~out_womask_1048; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_897 = {hi_380, flags_0_go, _out_prepend_T_897}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_10163 = out_prepend_897; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_10164 = _out_T_10163; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_898 = _out_T_10164; // @[RegisterRouter.scala:87:24]
wire out_rimask_1049 = |_out_rimask_T_1049; // @[RegisterRouter.scala:87:24]
wire out_wimask_1049 = &_out_wimask_T_1049; // @[RegisterRouter.scala:87:24]
wire out_romask_1049 = |_out_romask_T_1049; // @[RegisterRouter.scala:87:24]
wire out_womask_1049 = &_out_womask_T_1049; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1049 = out_rivalid_1_903 & out_rimask_1049; // @[RegisterRouter.scala:87:24]
wire _out_T_10166 = out_f_rivalid_1049; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1049 = out_roready_1_903 & out_romask_1049; // @[RegisterRouter.scala:87:24]
wire _out_T_10167 = out_f_roready_1049; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1049 = out_wivalid_1_903 & out_wimask_1049; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1049 = out_woready_1_903 & out_womask_1049; // @[RegisterRouter.scala:87:24]
wire _out_T_10168 = ~out_rimask_1049; // @[RegisterRouter.scala:87:24]
wire _out_T_10169 = ~out_wimask_1049; // @[RegisterRouter.scala:87:24]
wire _out_T_10170 = ~out_romask_1049; // @[RegisterRouter.scala:87:24]
wire _out_T_10171 = ~out_womask_1049; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_898 = {hi_381, flags_0_go, _out_prepend_T_898}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_10172 = out_prepend_898; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_10173 = _out_T_10172; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_899 = _out_T_10173; // @[RegisterRouter.scala:87:24]
wire out_rimask_1050 = |_out_rimask_T_1050; // @[RegisterRouter.scala:87:24]
wire out_wimask_1050 = &_out_wimask_T_1050; // @[RegisterRouter.scala:87:24]
wire out_romask_1050 = |_out_romask_T_1050; // @[RegisterRouter.scala:87:24]
wire out_womask_1050 = &_out_womask_T_1050; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1050 = out_rivalid_1_904 & out_rimask_1050; // @[RegisterRouter.scala:87:24]
wire _out_T_10175 = out_f_rivalid_1050; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1050 = out_roready_1_904 & out_romask_1050; // @[RegisterRouter.scala:87:24]
wire _out_T_10176 = out_f_roready_1050; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1050 = out_wivalid_1_904 & out_wimask_1050; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1050 = out_woready_1_904 & out_womask_1050; // @[RegisterRouter.scala:87:24]
wire _out_T_10177 = ~out_rimask_1050; // @[RegisterRouter.scala:87:24]
wire _out_T_10178 = ~out_wimask_1050; // @[RegisterRouter.scala:87:24]
wire _out_T_10179 = ~out_romask_1050; // @[RegisterRouter.scala:87:24]
wire _out_T_10180 = ~out_womask_1050; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_899 = {hi_382, flags_0_go, _out_prepend_T_899}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_10181 = out_prepend_899; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_10182 = _out_T_10181; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_900 = _out_T_10182; // @[RegisterRouter.scala:87:24]
wire out_rimask_1051 = |_out_rimask_T_1051; // @[RegisterRouter.scala:87:24]
wire out_wimask_1051 = &_out_wimask_T_1051; // @[RegisterRouter.scala:87:24]
wire out_romask_1051 = |_out_romask_T_1051; // @[RegisterRouter.scala:87:24]
wire out_womask_1051 = &_out_womask_T_1051; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1051 = out_rivalid_1_905 & out_rimask_1051; // @[RegisterRouter.scala:87:24]
wire _out_T_10184 = out_f_rivalid_1051; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1051 = out_roready_1_905 & out_romask_1051; // @[RegisterRouter.scala:87:24]
wire _out_T_10185 = out_f_roready_1051; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1051 = out_wivalid_1_905 & out_wimask_1051; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1051 = out_woready_1_905 & out_womask_1051; // @[RegisterRouter.scala:87:24]
wire _out_T_10186 = ~out_rimask_1051; // @[RegisterRouter.scala:87:24]
wire _out_T_10187 = ~out_wimask_1051; // @[RegisterRouter.scala:87:24]
wire _out_T_10188 = ~out_romask_1051; // @[RegisterRouter.scala:87:24]
wire _out_T_10189 = ~out_womask_1051; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_900 = {hi_383, flags_0_go, _out_prepend_T_900}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_10190 = out_prepend_900; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_10191 = _out_T_10190; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_901 = _out_T_10191; // @[RegisterRouter.scala:87:24]
wire out_rimask_1052 = |_out_rimask_T_1052; // @[RegisterRouter.scala:87:24]
wire out_wimask_1052 = &_out_wimask_T_1052; // @[RegisterRouter.scala:87:24]
wire out_romask_1052 = |_out_romask_T_1052; // @[RegisterRouter.scala:87:24]
wire out_womask_1052 = &_out_womask_T_1052; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1052 = out_rivalid_1_906 & out_rimask_1052; // @[RegisterRouter.scala:87:24]
wire _out_T_10193 = out_f_rivalid_1052; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1052 = out_roready_1_906 & out_romask_1052; // @[RegisterRouter.scala:87:24]
wire _out_T_10194 = out_f_roready_1052; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1052 = out_wivalid_1_906 & out_wimask_1052; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1052 = out_woready_1_906 & out_womask_1052; // @[RegisterRouter.scala:87:24]
wire _out_T_10195 = ~out_rimask_1052; // @[RegisterRouter.scala:87:24]
wire _out_T_10196 = ~out_wimask_1052; // @[RegisterRouter.scala:87:24]
wire _out_T_10197 = ~out_romask_1052; // @[RegisterRouter.scala:87:24]
wire _out_T_10198 = ~out_womask_1052; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_901 = {hi_384, flags_0_go, _out_prepend_T_901}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_10199 = out_prepend_901; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_10200 = _out_T_10199; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_175 = _out_T_10200; // @[MuxLiteral.scala:49:48]
wire out_rimask_1053 = |_out_rimask_T_1053; // @[RegisterRouter.scala:87:24]
wire out_wimask_1053 = &_out_wimask_T_1053; // @[RegisterRouter.scala:87:24]
wire out_romask_1053 = |_out_romask_T_1053; // @[RegisterRouter.scala:87:24]
wire out_womask_1053 = &_out_womask_T_1053; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1053 = out_rivalid_1_907 & out_rimask_1053; // @[RegisterRouter.scala:87:24]
wire _out_T_10202 = out_f_rivalid_1053; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1053 = out_roready_1_907 & out_romask_1053; // @[RegisterRouter.scala:87:24]
wire _out_T_10203 = out_f_roready_1053; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1053 = out_wivalid_1_907 & out_wimask_1053; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1053 = out_woready_1_907 & out_womask_1053; // @[RegisterRouter.scala:87:24]
wire _out_T_10204 = ~out_rimask_1053; // @[RegisterRouter.scala:87:24]
wire _out_T_10205 = ~out_wimask_1053; // @[RegisterRouter.scala:87:24]
wire _out_T_10206 = ~out_romask_1053; // @[RegisterRouter.scala:87:24]
wire _out_T_10207 = ~out_womask_1053; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10209 = _out_T_10208; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_902 = _out_T_10209; // @[RegisterRouter.scala:87:24]
wire out_rimask_1054 = |_out_rimask_T_1054; // @[RegisterRouter.scala:87:24]
wire out_wimask_1054 = &_out_wimask_T_1054; // @[RegisterRouter.scala:87:24]
wire out_romask_1054 = |_out_romask_T_1054; // @[RegisterRouter.scala:87:24]
wire out_womask_1054 = &_out_womask_T_1054; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1054 = out_rivalid_1_908 & out_rimask_1054; // @[RegisterRouter.scala:87:24]
wire _out_T_10211 = out_f_rivalid_1054; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1054 = out_roready_1_908 & out_romask_1054; // @[RegisterRouter.scala:87:24]
wire _out_T_10212 = out_f_roready_1054; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1054 = out_wivalid_1_908 & out_wimask_1054; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1054 = out_woready_1_908 & out_womask_1054; // @[RegisterRouter.scala:87:24]
wire _out_T_10213 = ~out_rimask_1054; // @[RegisterRouter.scala:87:24]
wire _out_T_10214 = ~out_wimask_1054; // @[RegisterRouter.scala:87:24]
wire _out_T_10215 = ~out_romask_1054; // @[RegisterRouter.scala:87:24]
wire _out_T_10216 = ~out_womask_1054; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_902 = {hi_122, flags_0_go, _out_prepend_T_902}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_10217 = out_prepend_902; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_10218 = _out_T_10217; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_903 = _out_T_10218; // @[RegisterRouter.scala:87:24]
wire out_rimask_1055 = |_out_rimask_T_1055; // @[RegisterRouter.scala:87:24]
wire out_wimask_1055 = &_out_wimask_T_1055; // @[RegisterRouter.scala:87:24]
wire out_romask_1055 = |_out_romask_T_1055; // @[RegisterRouter.scala:87:24]
wire out_womask_1055 = &_out_womask_T_1055; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1055 = out_rivalid_1_909 & out_rimask_1055; // @[RegisterRouter.scala:87:24]
wire _out_T_10220 = out_f_rivalid_1055; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1055 = out_roready_1_909 & out_romask_1055; // @[RegisterRouter.scala:87:24]
wire _out_T_10221 = out_f_roready_1055; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1055 = out_wivalid_1_909 & out_wimask_1055; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1055 = out_woready_1_909 & out_womask_1055; // @[RegisterRouter.scala:87:24]
wire _out_T_10222 = ~out_rimask_1055; // @[RegisterRouter.scala:87:24]
wire _out_T_10223 = ~out_wimask_1055; // @[RegisterRouter.scala:87:24]
wire _out_T_10224 = ~out_romask_1055; // @[RegisterRouter.scala:87:24]
wire _out_T_10225 = ~out_womask_1055; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_903 = {hi_123, flags_0_go, _out_prepend_T_903}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_10226 = out_prepend_903; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_10227 = _out_T_10226; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_904 = _out_T_10227; // @[RegisterRouter.scala:87:24]
wire out_rimask_1056 = |_out_rimask_T_1056; // @[RegisterRouter.scala:87:24]
wire out_wimask_1056 = &_out_wimask_T_1056; // @[RegisterRouter.scala:87:24]
wire out_romask_1056 = |_out_romask_T_1056; // @[RegisterRouter.scala:87:24]
wire out_womask_1056 = &_out_womask_T_1056; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1056 = out_rivalid_1_910 & out_rimask_1056; // @[RegisterRouter.scala:87:24]
wire _out_T_10229 = out_f_rivalid_1056; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1056 = out_roready_1_910 & out_romask_1056; // @[RegisterRouter.scala:87:24]
wire _out_T_10230 = out_f_roready_1056; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1056 = out_wivalid_1_910 & out_wimask_1056; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1056 = out_woready_1_910 & out_womask_1056; // @[RegisterRouter.scala:87:24]
wire _out_T_10231 = ~out_rimask_1056; // @[RegisterRouter.scala:87:24]
wire _out_T_10232 = ~out_wimask_1056; // @[RegisterRouter.scala:87:24]
wire _out_T_10233 = ~out_romask_1056; // @[RegisterRouter.scala:87:24]
wire _out_T_10234 = ~out_womask_1056; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_904 = {hi_124, flags_0_go, _out_prepend_T_904}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_10235 = out_prepend_904; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_10236 = _out_T_10235; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_905 = _out_T_10236; // @[RegisterRouter.scala:87:24]
wire out_rimask_1057 = |_out_rimask_T_1057; // @[RegisterRouter.scala:87:24]
wire out_wimask_1057 = &_out_wimask_T_1057; // @[RegisterRouter.scala:87:24]
wire out_romask_1057 = |_out_romask_T_1057; // @[RegisterRouter.scala:87:24]
wire out_womask_1057 = &_out_womask_T_1057; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1057 = out_rivalid_1_911 & out_rimask_1057; // @[RegisterRouter.scala:87:24]
wire _out_T_10238 = out_f_rivalid_1057; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1057 = out_roready_1_911 & out_romask_1057; // @[RegisterRouter.scala:87:24]
wire _out_T_10239 = out_f_roready_1057; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1057 = out_wivalid_1_911 & out_wimask_1057; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1057 = out_woready_1_911 & out_womask_1057; // @[RegisterRouter.scala:87:24]
wire _out_T_10240 = ~out_rimask_1057; // @[RegisterRouter.scala:87:24]
wire _out_T_10241 = ~out_wimask_1057; // @[RegisterRouter.scala:87:24]
wire _out_T_10242 = ~out_romask_1057; // @[RegisterRouter.scala:87:24]
wire _out_T_10243 = ~out_womask_1057; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_905 = {hi_125, flags_0_go, _out_prepend_T_905}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_10244 = out_prepend_905; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_10245 = _out_T_10244; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_906 = _out_T_10245; // @[RegisterRouter.scala:87:24]
wire out_rimask_1058 = |_out_rimask_T_1058; // @[RegisterRouter.scala:87:24]
wire out_wimask_1058 = &_out_wimask_T_1058; // @[RegisterRouter.scala:87:24]
wire out_romask_1058 = |_out_romask_T_1058; // @[RegisterRouter.scala:87:24]
wire out_womask_1058 = &_out_womask_T_1058; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1058 = out_rivalid_1_912 & out_rimask_1058; // @[RegisterRouter.scala:87:24]
wire _out_T_10247 = out_f_rivalid_1058; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1058 = out_roready_1_912 & out_romask_1058; // @[RegisterRouter.scala:87:24]
wire _out_T_10248 = out_f_roready_1058; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1058 = out_wivalid_1_912 & out_wimask_1058; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1058 = out_woready_1_912 & out_womask_1058; // @[RegisterRouter.scala:87:24]
wire _out_T_10249 = ~out_rimask_1058; // @[RegisterRouter.scala:87:24]
wire _out_T_10250 = ~out_wimask_1058; // @[RegisterRouter.scala:87:24]
wire _out_T_10251 = ~out_romask_1058; // @[RegisterRouter.scala:87:24]
wire _out_T_10252 = ~out_womask_1058; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_906 = {hi_126, flags_0_go, _out_prepend_T_906}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_10253 = out_prepend_906; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_10254 = _out_T_10253; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_907 = _out_T_10254; // @[RegisterRouter.scala:87:24]
wire out_rimask_1059 = |_out_rimask_T_1059; // @[RegisterRouter.scala:87:24]
wire out_wimask_1059 = &_out_wimask_T_1059; // @[RegisterRouter.scala:87:24]
wire out_romask_1059 = |_out_romask_T_1059; // @[RegisterRouter.scala:87:24]
wire out_womask_1059 = &_out_womask_T_1059; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1059 = out_rivalid_1_913 & out_rimask_1059; // @[RegisterRouter.scala:87:24]
wire _out_T_10256 = out_f_rivalid_1059; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1059 = out_roready_1_913 & out_romask_1059; // @[RegisterRouter.scala:87:24]
wire _out_T_10257 = out_f_roready_1059; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1059 = out_wivalid_1_913 & out_wimask_1059; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1059 = out_woready_1_913 & out_womask_1059; // @[RegisterRouter.scala:87:24]
wire _out_T_10258 = ~out_rimask_1059; // @[RegisterRouter.scala:87:24]
wire _out_T_10259 = ~out_wimask_1059; // @[RegisterRouter.scala:87:24]
wire _out_T_10260 = ~out_romask_1059; // @[RegisterRouter.scala:87:24]
wire _out_T_10261 = ~out_womask_1059; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_907 = {hi_127, flags_0_go, _out_prepend_T_907}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_10262 = out_prepend_907; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_10263 = _out_T_10262; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_908 = _out_T_10263; // @[RegisterRouter.scala:87:24]
wire out_rimask_1060 = |_out_rimask_T_1060; // @[RegisterRouter.scala:87:24]
wire out_wimask_1060 = &_out_wimask_T_1060; // @[RegisterRouter.scala:87:24]
wire out_romask_1060 = |_out_romask_T_1060; // @[RegisterRouter.scala:87:24]
wire out_womask_1060 = &_out_womask_T_1060; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1060 = out_rivalid_1_914 & out_rimask_1060; // @[RegisterRouter.scala:87:24]
wire _out_T_10265 = out_f_rivalid_1060; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1060 = out_roready_1_914 & out_romask_1060; // @[RegisterRouter.scala:87:24]
wire _out_T_10266 = out_f_roready_1060; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1060 = out_wivalid_1_914 & out_wimask_1060; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1060 = out_woready_1_914 & out_womask_1060; // @[RegisterRouter.scala:87:24]
wire _out_T_10267 = ~out_rimask_1060; // @[RegisterRouter.scala:87:24]
wire _out_T_10268 = ~out_wimask_1060; // @[RegisterRouter.scala:87:24]
wire _out_T_10269 = ~out_romask_1060; // @[RegisterRouter.scala:87:24]
wire _out_T_10270 = ~out_womask_1060; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_908 = {hi_128, flags_0_go, _out_prepend_T_908}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_10271 = out_prepend_908; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_10272 = _out_T_10271; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_143 = _out_T_10272; // @[MuxLiteral.scala:49:48]
wire out_rimask_1061 = |_out_rimask_T_1061; // @[RegisterRouter.scala:87:24]
wire out_wimask_1061 = &_out_wimask_T_1061; // @[RegisterRouter.scala:87:24]
wire out_romask_1061 = |_out_romask_T_1061; // @[RegisterRouter.scala:87:24]
wire out_womask_1061 = &_out_womask_T_1061; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1061 = out_rivalid_1_915 & out_rimask_1061; // @[RegisterRouter.scala:87:24]
wire _out_T_10274 = out_f_rivalid_1061; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1061 = out_roready_1_915 & out_romask_1061; // @[RegisterRouter.scala:87:24]
wire _out_T_10275 = out_f_roready_1061; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1061 = out_wivalid_1_915 & out_wimask_1061; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1061 = out_woready_1_915 & out_womask_1061; // @[RegisterRouter.scala:87:24]
wire _out_T_10276 = ~out_rimask_1061; // @[RegisterRouter.scala:87:24]
wire _out_T_10277 = ~out_wimask_1061; // @[RegisterRouter.scala:87:24]
wire _out_T_10278 = ~out_romask_1061; // @[RegisterRouter.scala:87:24]
wire _out_T_10279 = ~out_womask_1061; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10281 = _out_T_10280; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_909 = _out_T_10281; // @[RegisterRouter.scala:87:24]
wire out_rimask_1062 = |_out_rimask_T_1062; // @[RegisterRouter.scala:87:24]
wire out_wimask_1062 = &_out_wimask_T_1062; // @[RegisterRouter.scala:87:24]
wire out_romask_1062 = |_out_romask_T_1062; // @[RegisterRouter.scala:87:24]
wire out_womask_1062 = &_out_womask_T_1062; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1062 = out_rivalid_1_916 & out_rimask_1062; // @[RegisterRouter.scala:87:24]
wire _out_T_10283 = out_f_rivalid_1062; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1062 = out_roready_1_916 & out_romask_1062; // @[RegisterRouter.scala:87:24]
wire _out_T_10284 = out_f_roready_1062; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1062 = out_wivalid_1_916 & out_wimask_1062; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1062 = out_woready_1_916 & out_womask_1062; // @[RegisterRouter.scala:87:24]
wire _out_T_10285 = ~out_rimask_1062; // @[RegisterRouter.scala:87:24]
wire _out_T_10286 = ~out_wimask_1062; // @[RegisterRouter.scala:87:24]
wire _out_T_10287 = ~out_romask_1062; // @[RegisterRouter.scala:87:24]
wire _out_T_10288 = ~out_womask_1062; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_909 = {hi_602, flags_0_go, _out_prepend_T_909}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_10289 = out_prepend_909; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_10290 = _out_T_10289; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_910 = _out_T_10290; // @[RegisterRouter.scala:87:24]
wire out_rimask_1063 = |_out_rimask_T_1063; // @[RegisterRouter.scala:87:24]
wire out_wimask_1063 = &_out_wimask_T_1063; // @[RegisterRouter.scala:87:24]
wire out_romask_1063 = |_out_romask_T_1063; // @[RegisterRouter.scala:87:24]
wire out_womask_1063 = &_out_womask_T_1063; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1063 = out_rivalid_1_917 & out_rimask_1063; // @[RegisterRouter.scala:87:24]
wire _out_T_10292 = out_f_rivalid_1063; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1063 = out_roready_1_917 & out_romask_1063; // @[RegisterRouter.scala:87:24]
wire _out_T_10293 = out_f_roready_1063; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1063 = out_wivalid_1_917 & out_wimask_1063; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1063 = out_woready_1_917 & out_womask_1063; // @[RegisterRouter.scala:87:24]
wire _out_T_10294 = ~out_rimask_1063; // @[RegisterRouter.scala:87:24]
wire _out_T_10295 = ~out_wimask_1063; // @[RegisterRouter.scala:87:24]
wire _out_T_10296 = ~out_romask_1063; // @[RegisterRouter.scala:87:24]
wire _out_T_10297 = ~out_womask_1063; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_910 = {hi_603, flags_0_go, _out_prepend_T_910}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_10298 = out_prepend_910; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_10299 = _out_T_10298; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_911 = _out_T_10299; // @[RegisterRouter.scala:87:24]
wire out_rimask_1064 = |_out_rimask_T_1064; // @[RegisterRouter.scala:87:24]
wire out_wimask_1064 = &_out_wimask_T_1064; // @[RegisterRouter.scala:87:24]
wire out_romask_1064 = |_out_romask_T_1064; // @[RegisterRouter.scala:87:24]
wire out_womask_1064 = &_out_womask_T_1064; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1064 = out_rivalid_1_918 & out_rimask_1064; // @[RegisterRouter.scala:87:24]
wire _out_T_10301 = out_f_rivalid_1064; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1064 = out_roready_1_918 & out_romask_1064; // @[RegisterRouter.scala:87:24]
wire _out_T_10302 = out_f_roready_1064; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1064 = out_wivalid_1_918 & out_wimask_1064; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1064 = out_woready_1_918 & out_womask_1064; // @[RegisterRouter.scala:87:24]
wire _out_T_10303 = ~out_rimask_1064; // @[RegisterRouter.scala:87:24]
wire _out_T_10304 = ~out_wimask_1064; // @[RegisterRouter.scala:87:24]
wire _out_T_10305 = ~out_romask_1064; // @[RegisterRouter.scala:87:24]
wire _out_T_10306 = ~out_womask_1064; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_911 = {hi_604, flags_0_go, _out_prepend_T_911}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_10307 = out_prepend_911; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_10308 = _out_T_10307; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_912 = _out_T_10308; // @[RegisterRouter.scala:87:24]
wire out_rimask_1065 = |_out_rimask_T_1065; // @[RegisterRouter.scala:87:24]
wire out_wimask_1065 = &_out_wimask_T_1065; // @[RegisterRouter.scala:87:24]
wire out_romask_1065 = |_out_romask_T_1065; // @[RegisterRouter.scala:87:24]
wire out_womask_1065 = &_out_womask_T_1065; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1065 = out_rivalid_1_919 & out_rimask_1065; // @[RegisterRouter.scala:87:24]
wire _out_T_10310 = out_f_rivalid_1065; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1065 = out_roready_1_919 & out_romask_1065; // @[RegisterRouter.scala:87:24]
wire _out_T_10311 = out_f_roready_1065; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1065 = out_wivalid_1_919 & out_wimask_1065; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1065 = out_woready_1_919 & out_womask_1065; // @[RegisterRouter.scala:87:24]
wire _out_T_10312 = ~out_rimask_1065; // @[RegisterRouter.scala:87:24]
wire _out_T_10313 = ~out_wimask_1065; // @[RegisterRouter.scala:87:24]
wire _out_T_10314 = ~out_romask_1065; // @[RegisterRouter.scala:87:24]
wire _out_T_10315 = ~out_womask_1065; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_912 = {hi_605, flags_0_go, _out_prepend_T_912}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_10316 = out_prepend_912; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_10317 = _out_T_10316; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_913 = _out_T_10317; // @[RegisterRouter.scala:87:24]
wire out_rimask_1066 = |_out_rimask_T_1066; // @[RegisterRouter.scala:87:24]
wire out_wimask_1066 = &_out_wimask_T_1066; // @[RegisterRouter.scala:87:24]
wire out_romask_1066 = |_out_romask_T_1066; // @[RegisterRouter.scala:87:24]
wire out_womask_1066 = &_out_womask_T_1066; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1066 = out_rivalid_1_920 & out_rimask_1066; // @[RegisterRouter.scala:87:24]
wire _out_T_10319 = out_f_rivalid_1066; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1066 = out_roready_1_920 & out_romask_1066; // @[RegisterRouter.scala:87:24]
wire _out_T_10320 = out_f_roready_1066; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1066 = out_wivalid_1_920 & out_wimask_1066; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1066 = out_woready_1_920 & out_womask_1066; // @[RegisterRouter.scala:87:24]
wire _out_T_10321 = ~out_rimask_1066; // @[RegisterRouter.scala:87:24]
wire _out_T_10322 = ~out_wimask_1066; // @[RegisterRouter.scala:87:24]
wire _out_T_10323 = ~out_romask_1066; // @[RegisterRouter.scala:87:24]
wire _out_T_10324 = ~out_womask_1066; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_913 = {hi_606, flags_0_go, _out_prepend_T_913}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_10325 = out_prepend_913; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_10326 = _out_T_10325; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_914 = _out_T_10326; // @[RegisterRouter.scala:87:24]
wire out_rimask_1067 = |_out_rimask_T_1067; // @[RegisterRouter.scala:87:24]
wire out_wimask_1067 = &_out_wimask_T_1067; // @[RegisterRouter.scala:87:24]
wire out_romask_1067 = |_out_romask_T_1067; // @[RegisterRouter.scala:87:24]
wire out_womask_1067 = &_out_womask_T_1067; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1067 = out_rivalid_1_921 & out_rimask_1067; // @[RegisterRouter.scala:87:24]
wire _out_T_10328 = out_f_rivalid_1067; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1067 = out_roready_1_921 & out_romask_1067; // @[RegisterRouter.scala:87:24]
wire _out_T_10329 = out_f_roready_1067; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1067 = out_wivalid_1_921 & out_wimask_1067; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1067 = out_woready_1_921 & out_womask_1067; // @[RegisterRouter.scala:87:24]
wire _out_T_10330 = ~out_rimask_1067; // @[RegisterRouter.scala:87:24]
wire _out_T_10331 = ~out_wimask_1067; // @[RegisterRouter.scala:87:24]
wire _out_T_10332 = ~out_romask_1067; // @[RegisterRouter.scala:87:24]
wire _out_T_10333 = ~out_womask_1067; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_914 = {hi_607, flags_0_go, _out_prepend_T_914}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_10334 = out_prepend_914; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_10335 = _out_T_10334; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_915 = _out_T_10335; // @[RegisterRouter.scala:87:24]
wire out_rimask_1068 = |_out_rimask_T_1068; // @[RegisterRouter.scala:87:24]
wire out_wimask_1068 = &_out_wimask_T_1068; // @[RegisterRouter.scala:87:24]
wire out_romask_1068 = |_out_romask_T_1068; // @[RegisterRouter.scala:87:24]
wire out_womask_1068 = &_out_womask_T_1068; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1068 = out_rivalid_1_922 & out_rimask_1068; // @[RegisterRouter.scala:87:24]
wire _out_T_10337 = out_f_rivalid_1068; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1068 = out_roready_1_922 & out_romask_1068; // @[RegisterRouter.scala:87:24]
wire _out_T_10338 = out_f_roready_1068; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1068 = out_wivalid_1_922 & out_wimask_1068; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1068 = out_woready_1_922 & out_womask_1068; // @[RegisterRouter.scala:87:24]
wire _out_T_10339 = ~out_rimask_1068; // @[RegisterRouter.scala:87:24]
wire _out_T_10340 = ~out_wimask_1068; // @[RegisterRouter.scala:87:24]
wire _out_T_10341 = ~out_romask_1068; // @[RegisterRouter.scala:87:24]
wire _out_T_10342 = ~out_womask_1068; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_915 = {hi_608, flags_0_go, _out_prepend_T_915}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_10343 = out_prepend_915; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_10344 = _out_T_10343; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_203 = _out_T_10344; // @[MuxLiteral.scala:49:48]
wire out_rimask_1069 = |_out_rimask_T_1069; // @[RegisterRouter.scala:87:24]
wire out_wimask_1069 = &_out_wimask_T_1069; // @[RegisterRouter.scala:87:24]
wire out_romask_1069 = |_out_romask_T_1069; // @[RegisterRouter.scala:87:24]
wire out_womask_1069 = &_out_womask_T_1069; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1069 = out_rivalid_1_923 & out_rimask_1069; // @[RegisterRouter.scala:87:24]
wire _out_T_10346 = out_f_rivalid_1069; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1069 = out_roready_1_923 & out_romask_1069; // @[RegisterRouter.scala:87:24]
wire _out_T_10347 = out_f_roready_1069; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1069 = out_wivalid_1_923 & out_wimask_1069; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1069 = out_woready_1_923 & out_womask_1069; // @[RegisterRouter.scala:87:24]
wire _out_T_10348 = ~out_rimask_1069; // @[RegisterRouter.scala:87:24]
wire _out_T_10349 = ~out_wimask_1069; // @[RegisterRouter.scala:87:24]
wire _out_T_10350 = ~out_romask_1069; // @[RegisterRouter.scala:87:24]
wire _out_T_10351 = ~out_womask_1069; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10353 = _out_T_10352; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_916 = _out_T_10353; // @[RegisterRouter.scala:87:24]
wire out_rimask_1070 = |_out_rimask_T_1070; // @[RegisterRouter.scala:87:24]
wire out_wimask_1070 = &_out_wimask_T_1070; // @[RegisterRouter.scala:87:24]
wire out_romask_1070 = |_out_romask_T_1070; // @[RegisterRouter.scala:87:24]
wire out_womask_1070 = &_out_womask_T_1070; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1070 = out_rivalid_1_924 & out_rimask_1070; // @[RegisterRouter.scala:87:24]
wire _out_T_10355 = out_f_rivalid_1070; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1070 = out_roready_1_924 & out_romask_1070; // @[RegisterRouter.scala:87:24]
wire _out_T_10356 = out_f_roready_1070; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1070 = out_wivalid_1_924 & out_wimask_1070; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1070 = out_woready_1_924 & out_womask_1070; // @[RegisterRouter.scala:87:24]
wire _out_T_10357 = ~out_rimask_1070; // @[RegisterRouter.scala:87:24]
wire _out_T_10358 = ~out_wimask_1070; // @[RegisterRouter.scala:87:24]
wire _out_T_10359 = ~out_romask_1070; // @[RegisterRouter.scala:87:24]
wire _out_T_10360 = ~out_womask_1070; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_916 = {hi_722, flags_0_go, _out_prepend_T_916}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_10361 = out_prepend_916; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_10362 = _out_T_10361; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_917 = _out_T_10362; // @[RegisterRouter.scala:87:24]
wire out_rimask_1071 = |_out_rimask_T_1071; // @[RegisterRouter.scala:87:24]
wire out_wimask_1071 = &_out_wimask_T_1071; // @[RegisterRouter.scala:87:24]
wire out_romask_1071 = |_out_romask_T_1071; // @[RegisterRouter.scala:87:24]
wire out_womask_1071 = &_out_womask_T_1071; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1071 = out_rivalid_1_925 & out_rimask_1071; // @[RegisterRouter.scala:87:24]
wire _out_T_10364 = out_f_rivalid_1071; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1071 = out_roready_1_925 & out_romask_1071; // @[RegisterRouter.scala:87:24]
wire _out_T_10365 = out_f_roready_1071; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1071 = out_wivalid_1_925 & out_wimask_1071; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1071 = out_woready_1_925 & out_womask_1071; // @[RegisterRouter.scala:87:24]
wire _out_T_10366 = ~out_rimask_1071; // @[RegisterRouter.scala:87:24]
wire _out_T_10367 = ~out_wimask_1071; // @[RegisterRouter.scala:87:24]
wire _out_T_10368 = ~out_romask_1071; // @[RegisterRouter.scala:87:24]
wire _out_T_10369 = ~out_womask_1071; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_917 = {hi_723, flags_0_go, _out_prepend_T_917}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_10370 = out_prepend_917; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_10371 = _out_T_10370; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_918 = _out_T_10371; // @[RegisterRouter.scala:87:24]
wire out_rimask_1072 = |_out_rimask_T_1072; // @[RegisterRouter.scala:87:24]
wire out_wimask_1072 = &_out_wimask_T_1072; // @[RegisterRouter.scala:87:24]
wire out_romask_1072 = |_out_romask_T_1072; // @[RegisterRouter.scala:87:24]
wire out_womask_1072 = &_out_womask_T_1072; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1072 = out_rivalid_1_926 & out_rimask_1072; // @[RegisterRouter.scala:87:24]
wire _out_T_10373 = out_f_rivalid_1072; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1072 = out_roready_1_926 & out_romask_1072; // @[RegisterRouter.scala:87:24]
wire _out_T_10374 = out_f_roready_1072; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1072 = out_wivalid_1_926 & out_wimask_1072; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1072 = out_woready_1_926 & out_womask_1072; // @[RegisterRouter.scala:87:24]
wire _out_T_10375 = ~out_rimask_1072; // @[RegisterRouter.scala:87:24]
wire _out_T_10376 = ~out_wimask_1072; // @[RegisterRouter.scala:87:24]
wire _out_T_10377 = ~out_romask_1072; // @[RegisterRouter.scala:87:24]
wire _out_T_10378 = ~out_womask_1072; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_918 = {hi_724, flags_0_go, _out_prepend_T_918}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_10379 = out_prepend_918; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_10380 = _out_T_10379; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_919 = _out_T_10380; // @[RegisterRouter.scala:87:24]
wire out_rimask_1073 = |_out_rimask_T_1073; // @[RegisterRouter.scala:87:24]
wire out_wimask_1073 = &_out_wimask_T_1073; // @[RegisterRouter.scala:87:24]
wire out_romask_1073 = |_out_romask_T_1073; // @[RegisterRouter.scala:87:24]
wire out_womask_1073 = &_out_womask_T_1073; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1073 = out_rivalid_1_927 & out_rimask_1073; // @[RegisterRouter.scala:87:24]
wire _out_T_10382 = out_f_rivalid_1073; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1073 = out_roready_1_927 & out_romask_1073; // @[RegisterRouter.scala:87:24]
wire _out_T_10383 = out_f_roready_1073; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1073 = out_wivalid_1_927 & out_wimask_1073; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1073 = out_woready_1_927 & out_womask_1073; // @[RegisterRouter.scala:87:24]
wire _out_T_10384 = ~out_rimask_1073; // @[RegisterRouter.scala:87:24]
wire _out_T_10385 = ~out_wimask_1073; // @[RegisterRouter.scala:87:24]
wire _out_T_10386 = ~out_romask_1073; // @[RegisterRouter.scala:87:24]
wire _out_T_10387 = ~out_womask_1073; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_919 = {hi_725, flags_0_go, _out_prepend_T_919}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_10388 = out_prepend_919; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_10389 = _out_T_10388; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_920 = _out_T_10389; // @[RegisterRouter.scala:87:24]
wire out_rimask_1074 = |_out_rimask_T_1074; // @[RegisterRouter.scala:87:24]
wire out_wimask_1074 = &_out_wimask_T_1074; // @[RegisterRouter.scala:87:24]
wire out_romask_1074 = |_out_romask_T_1074; // @[RegisterRouter.scala:87:24]
wire out_womask_1074 = &_out_womask_T_1074; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1074 = out_rivalid_1_928 & out_rimask_1074; // @[RegisterRouter.scala:87:24]
wire _out_T_10391 = out_f_rivalid_1074; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1074 = out_roready_1_928 & out_romask_1074; // @[RegisterRouter.scala:87:24]
wire _out_T_10392 = out_f_roready_1074; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1074 = out_wivalid_1_928 & out_wimask_1074; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1074 = out_woready_1_928 & out_womask_1074; // @[RegisterRouter.scala:87:24]
wire _out_T_10393 = ~out_rimask_1074; // @[RegisterRouter.scala:87:24]
wire _out_T_10394 = ~out_wimask_1074; // @[RegisterRouter.scala:87:24]
wire _out_T_10395 = ~out_romask_1074; // @[RegisterRouter.scala:87:24]
wire _out_T_10396 = ~out_womask_1074; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_920 = {hi_726, flags_0_go, _out_prepend_T_920}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_10397 = out_prepend_920; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_10398 = _out_T_10397; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_921 = _out_T_10398; // @[RegisterRouter.scala:87:24]
wire out_rimask_1075 = |_out_rimask_T_1075; // @[RegisterRouter.scala:87:24]
wire out_wimask_1075 = &_out_wimask_T_1075; // @[RegisterRouter.scala:87:24]
wire out_romask_1075 = |_out_romask_T_1075; // @[RegisterRouter.scala:87:24]
wire out_womask_1075 = &_out_womask_T_1075; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1075 = out_rivalid_1_929 & out_rimask_1075; // @[RegisterRouter.scala:87:24]
wire _out_T_10400 = out_f_rivalid_1075; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1075 = out_roready_1_929 & out_romask_1075; // @[RegisterRouter.scala:87:24]
wire _out_T_10401 = out_f_roready_1075; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1075 = out_wivalid_1_929 & out_wimask_1075; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1075 = out_woready_1_929 & out_womask_1075; // @[RegisterRouter.scala:87:24]
wire _out_T_10402 = ~out_rimask_1075; // @[RegisterRouter.scala:87:24]
wire _out_T_10403 = ~out_wimask_1075; // @[RegisterRouter.scala:87:24]
wire _out_T_10404 = ~out_romask_1075; // @[RegisterRouter.scala:87:24]
wire _out_T_10405 = ~out_womask_1075; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_921 = {hi_727, flags_0_go, _out_prepend_T_921}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_10406 = out_prepend_921; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_10407 = _out_T_10406; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_922 = _out_T_10407; // @[RegisterRouter.scala:87:24]
wire out_rimask_1076 = |_out_rimask_T_1076; // @[RegisterRouter.scala:87:24]
wire out_wimask_1076 = &_out_wimask_T_1076; // @[RegisterRouter.scala:87:24]
wire out_romask_1076 = |_out_romask_T_1076; // @[RegisterRouter.scala:87:24]
wire out_womask_1076 = &_out_womask_T_1076; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1076 = out_rivalid_1_930 & out_rimask_1076; // @[RegisterRouter.scala:87:24]
wire _out_T_10409 = out_f_rivalid_1076; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1076 = out_roready_1_930 & out_romask_1076; // @[RegisterRouter.scala:87:24]
wire _out_T_10410 = out_f_roready_1076; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1076 = out_wivalid_1_930 & out_wimask_1076; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1076 = out_woready_1_930 & out_womask_1076; // @[RegisterRouter.scala:87:24]
wire _out_T_10411 = ~out_rimask_1076; // @[RegisterRouter.scala:87:24]
wire _out_T_10412 = ~out_wimask_1076; // @[RegisterRouter.scala:87:24]
wire _out_T_10413 = ~out_romask_1076; // @[RegisterRouter.scala:87:24]
wire _out_T_10414 = ~out_womask_1076; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_922 = {hi_728, flags_0_go, _out_prepend_T_922}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_10415 = out_prepend_922; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_10416 = _out_T_10415; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_218 = _out_T_10416; // @[MuxLiteral.scala:49:48]
wire out_rimask_1077 = |_out_rimask_T_1077; // @[RegisterRouter.scala:87:24]
wire out_wimask_1077 = &_out_wimask_T_1077; // @[RegisterRouter.scala:87:24]
wire out_romask_1077 = |_out_romask_T_1077; // @[RegisterRouter.scala:87:24]
wire out_womask_1077 = &_out_womask_T_1077; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1077 = out_rivalid_1_931 & out_rimask_1077; // @[RegisterRouter.scala:87:24]
wire _out_T_10418 = out_f_rivalid_1077; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1077 = out_roready_1_931 & out_romask_1077; // @[RegisterRouter.scala:87:24]
wire _out_T_10419 = out_f_roready_1077; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1077 = out_wivalid_1_931 & out_wimask_1077; // @[RegisterRouter.scala:87:24]
wire _out_T_10420 = out_f_wivalid_1077; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1077 = out_woready_1_931 & out_womask_1077; // @[RegisterRouter.scala:87:24]
wire _out_T_10421 = out_f_woready_1077; // @[RegisterRouter.scala:87:24]
wire _out_T_10422 = ~out_rimask_1077; // @[RegisterRouter.scala:87:24]
wire _out_T_10423 = ~out_wimask_1077; // @[RegisterRouter.scala:87:24]
wire _out_T_10424 = ~out_romask_1077; // @[RegisterRouter.scala:87:24]
wire _out_T_10425 = ~out_womask_1077; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10427 = _out_T_10426; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_923 = _out_T_10427; // @[RegisterRouter.scala:87:24]
wire out_rimask_1078 = |_out_rimask_T_1078; // @[RegisterRouter.scala:87:24]
wire out_wimask_1078 = &_out_wimask_T_1078; // @[RegisterRouter.scala:87:24]
wire out_romask_1078 = |_out_romask_T_1078; // @[RegisterRouter.scala:87:24]
wire out_womask_1078 = &_out_womask_T_1078; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1078 = out_rivalid_1_932 & out_rimask_1078; // @[RegisterRouter.scala:87:24]
wire _out_T_10429 = out_f_rivalid_1078; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1078 = out_roready_1_932 & out_romask_1078; // @[RegisterRouter.scala:87:24]
wire _out_T_10430 = out_f_roready_1078; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1078 = out_wivalid_1_932 & out_wimask_1078; // @[RegisterRouter.scala:87:24]
wire _out_T_10431 = out_f_wivalid_1078; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1078 = out_woready_1_932 & out_womask_1078; // @[RegisterRouter.scala:87:24]
wire _out_T_10432 = out_f_woready_1078; // @[RegisterRouter.scala:87:24]
wire _out_T_10433 = ~out_rimask_1078; // @[RegisterRouter.scala:87:24]
wire _out_T_10434 = ~out_wimask_1078; // @[RegisterRouter.scala:87:24]
wire _out_T_10435 = ~out_romask_1078; // @[RegisterRouter.scala:87:24]
wire _out_T_10436 = ~out_womask_1078; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_923 = {programBufferMem_1, _out_prepend_T_923}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_10437 = out_prepend_923; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_10438 = _out_T_10437; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_924 = _out_T_10438; // @[RegisterRouter.scala:87:24]
wire out_rimask_1079 = |_out_rimask_T_1079; // @[RegisterRouter.scala:87:24]
wire out_wimask_1079 = &_out_wimask_T_1079; // @[RegisterRouter.scala:87:24]
wire out_romask_1079 = |_out_romask_T_1079; // @[RegisterRouter.scala:87:24]
wire out_womask_1079 = &_out_womask_T_1079; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1079 = out_rivalid_1_933 & out_rimask_1079; // @[RegisterRouter.scala:87:24]
wire _out_T_10440 = out_f_rivalid_1079; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1079 = out_roready_1_933 & out_romask_1079; // @[RegisterRouter.scala:87:24]
wire _out_T_10441 = out_f_roready_1079; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1079 = out_wivalid_1_933 & out_wimask_1079; // @[RegisterRouter.scala:87:24]
wire _out_T_10442 = out_f_wivalid_1079; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1079 = out_woready_1_933 & out_womask_1079; // @[RegisterRouter.scala:87:24]
wire _out_T_10443 = out_f_woready_1079; // @[RegisterRouter.scala:87:24]
wire _out_T_10444 = ~out_rimask_1079; // @[RegisterRouter.scala:87:24]
wire _out_T_10445 = ~out_wimask_1079; // @[RegisterRouter.scala:87:24]
wire _out_T_10446 = ~out_romask_1079; // @[RegisterRouter.scala:87:24]
wire _out_T_10447 = ~out_womask_1079; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_924 = {programBufferMem_2, _out_prepend_T_924}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_10448 = out_prepend_924; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_10449 = _out_T_10448; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_925 = _out_T_10449; // @[RegisterRouter.scala:87:24]
wire out_rimask_1080 = |_out_rimask_T_1080; // @[RegisterRouter.scala:87:24]
wire out_wimask_1080 = &_out_wimask_T_1080; // @[RegisterRouter.scala:87:24]
wire out_romask_1080 = |_out_romask_T_1080; // @[RegisterRouter.scala:87:24]
wire out_womask_1080 = &_out_womask_T_1080; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1080 = out_rivalid_1_934 & out_rimask_1080; // @[RegisterRouter.scala:87:24]
wire _out_T_10451 = out_f_rivalid_1080; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1080 = out_roready_1_934 & out_romask_1080; // @[RegisterRouter.scala:87:24]
wire _out_T_10452 = out_f_roready_1080; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1080 = out_wivalid_1_934 & out_wimask_1080; // @[RegisterRouter.scala:87:24]
wire _out_T_10453 = out_f_wivalid_1080; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1080 = out_woready_1_934 & out_womask_1080; // @[RegisterRouter.scala:87:24]
wire _out_T_10454 = out_f_woready_1080; // @[RegisterRouter.scala:87:24]
wire _out_T_10455 = ~out_rimask_1080; // @[RegisterRouter.scala:87:24]
wire _out_T_10456 = ~out_wimask_1080; // @[RegisterRouter.scala:87:24]
wire _out_T_10457 = ~out_romask_1080; // @[RegisterRouter.scala:87:24]
wire _out_T_10458 = ~out_womask_1080; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_925 = {programBufferMem_3, _out_prepend_T_925}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_10459 = out_prepend_925; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_10460 = _out_T_10459; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_926 = _out_T_10460; // @[RegisterRouter.scala:87:24]
wire out_rimask_1081 = |_out_rimask_T_1081; // @[RegisterRouter.scala:87:24]
wire out_wimask_1081 = &_out_wimask_T_1081; // @[RegisterRouter.scala:87:24]
wire out_romask_1081 = |_out_romask_T_1081; // @[RegisterRouter.scala:87:24]
wire out_womask_1081 = &_out_womask_T_1081; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1081 = out_rivalid_1_935 & out_rimask_1081; // @[RegisterRouter.scala:87:24]
wire _out_T_10462 = out_f_rivalid_1081; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1081 = out_roready_1_935 & out_romask_1081; // @[RegisterRouter.scala:87:24]
wire _out_T_10463 = out_f_roready_1081; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1081 = out_wivalid_1_935 & out_wimask_1081; // @[RegisterRouter.scala:87:24]
wire _out_T_10464 = out_f_wivalid_1081; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1081 = out_woready_1_935 & out_womask_1081; // @[RegisterRouter.scala:87:24]
wire _out_T_10465 = out_f_woready_1081; // @[RegisterRouter.scala:87:24]
wire _out_T_10466 = ~out_rimask_1081; // @[RegisterRouter.scala:87:24]
wire _out_T_10467 = ~out_wimask_1081; // @[RegisterRouter.scala:87:24]
wire _out_T_10468 = ~out_romask_1081; // @[RegisterRouter.scala:87:24]
wire _out_T_10469 = ~out_womask_1081; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_926 = {programBufferMem_4, _out_prepend_T_926}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_10470 = out_prepend_926; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_10471 = _out_T_10470; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_927 = _out_T_10471; // @[RegisterRouter.scala:87:24]
wire out_rimask_1082 = |_out_rimask_T_1082; // @[RegisterRouter.scala:87:24]
wire out_wimask_1082 = &_out_wimask_T_1082; // @[RegisterRouter.scala:87:24]
wire out_romask_1082 = |_out_romask_T_1082; // @[RegisterRouter.scala:87:24]
wire out_womask_1082 = &_out_womask_T_1082; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1082 = out_rivalid_1_936 & out_rimask_1082; // @[RegisterRouter.scala:87:24]
wire _out_T_10473 = out_f_rivalid_1082; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1082 = out_roready_1_936 & out_romask_1082; // @[RegisterRouter.scala:87:24]
wire _out_T_10474 = out_f_roready_1082; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1082 = out_wivalid_1_936 & out_wimask_1082; // @[RegisterRouter.scala:87:24]
wire _out_T_10475 = out_f_wivalid_1082; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1082 = out_woready_1_936 & out_womask_1082; // @[RegisterRouter.scala:87:24]
wire _out_T_10476 = out_f_woready_1082; // @[RegisterRouter.scala:87:24]
wire _out_T_10477 = ~out_rimask_1082; // @[RegisterRouter.scala:87:24]
wire _out_T_10478 = ~out_wimask_1082; // @[RegisterRouter.scala:87:24]
wire _out_T_10479 = ~out_romask_1082; // @[RegisterRouter.scala:87:24]
wire _out_T_10480 = ~out_womask_1082; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_927 = {programBufferMem_5, _out_prepend_T_927}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_10481 = out_prepend_927; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_10482 = _out_T_10481; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_928 = _out_T_10482; // @[RegisterRouter.scala:87:24]
wire out_rimask_1083 = |_out_rimask_T_1083; // @[RegisterRouter.scala:87:24]
wire out_wimask_1083 = &_out_wimask_T_1083; // @[RegisterRouter.scala:87:24]
wire out_romask_1083 = |_out_romask_T_1083; // @[RegisterRouter.scala:87:24]
wire out_womask_1083 = &_out_womask_T_1083; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1083 = out_rivalid_1_937 & out_rimask_1083; // @[RegisterRouter.scala:87:24]
wire _out_T_10484 = out_f_rivalid_1083; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1083 = out_roready_1_937 & out_romask_1083; // @[RegisterRouter.scala:87:24]
wire _out_T_10485 = out_f_roready_1083; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1083 = out_wivalid_1_937 & out_wimask_1083; // @[RegisterRouter.scala:87:24]
wire _out_T_10486 = out_f_wivalid_1083; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1083 = out_woready_1_937 & out_womask_1083; // @[RegisterRouter.scala:87:24]
wire _out_T_10487 = out_f_woready_1083; // @[RegisterRouter.scala:87:24]
wire _out_T_10488 = ~out_rimask_1083; // @[RegisterRouter.scala:87:24]
wire _out_T_10489 = ~out_wimask_1083; // @[RegisterRouter.scala:87:24]
wire _out_T_10490 = ~out_romask_1083; // @[RegisterRouter.scala:87:24]
wire _out_T_10491 = ~out_womask_1083; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_928 = {programBufferMem_6, _out_prepend_T_928}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_10492 = out_prepend_928; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_10493 = _out_T_10492; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_929 = _out_T_10493; // @[RegisterRouter.scala:87:24]
wire out_rimask_1084 = |_out_rimask_T_1084; // @[RegisterRouter.scala:87:24]
wire out_wimask_1084 = &_out_wimask_T_1084; // @[RegisterRouter.scala:87:24]
wire out_romask_1084 = |_out_romask_T_1084; // @[RegisterRouter.scala:87:24]
wire out_womask_1084 = &_out_womask_T_1084; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1084 = out_rivalid_1_938 & out_rimask_1084; // @[RegisterRouter.scala:87:24]
wire _out_T_10495 = out_f_rivalid_1084; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1084 = out_roready_1_938 & out_romask_1084; // @[RegisterRouter.scala:87:24]
wire _out_T_10496 = out_f_roready_1084; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1084 = out_wivalid_1_938 & out_wimask_1084; // @[RegisterRouter.scala:87:24]
wire _out_T_10497 = out_f_wivalid_1084; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1084 = out_woready_1_938 & out_womask_1084; // @[RegisterRouter.scala:87:24]
wire _out_T_10498 = out_f_woready_1084; // @[RegisterRouter.scala:87:24]
wire _out_T_10499 = ~out_rimask_1084; // @[RegisterRouter.scala:87:24]
wire _out_T_10500 = ~out_wimask_1084; // @[RegisterRouter.scala:87:24]
wire _out_T_10501 = ~out_romask_1084; // @[RegisterRouter.scala:87:24]
wire _out_T_10502 = ~out_womask_1084; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_929 = {programBufferMem_7, _out_prepend_T_929}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_10503 = out_prepend_929; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_10504 = _out_T_10503; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_104 = _out_T_10504; // @[MuxLiteral.scala:49:48]
wire out_rimask_1085 = |_out_rimask_T_1085; // @[RegisterRouter.scala:87:24]
wire out_wimask_1085 = &_out_wimask_T_1085; // @[RegisterRouter.scala:87:24]
wire out_romask_1085 = |_out_romask_T_1085; // @[RegisterRouter.scala:87:24]
wire out_womask_1085 = &_out_womask_T_1085; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1085 = out_rivalid_1_939 & out_rimask_1085; // @[RegisterRouter.scala:87:24]
wire _out_T_10506 = out_f_rivalid_1085; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1085 = out_roready_1_939 & out_romask_1085; // @[RegisterRouter.scala:87:24]
wire _out_T_10507 = out_f_roready_1085; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1085 = out_wivalid_1_939 & out_wimask_1085; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1085 = out_woready_1_939 & out_womask_1085; // @[RegisterRouter.scala:87:24]
wire _out_T_10508 = ~out_rimask_1085; // @[RegisterRouter.scala:87:24]
wire _out_T_10509 = ~out_wimask_1085; // @[RegisterRouter.scala:87:24]
wire _out_T_10510 = ~out_romask_1085; // @[RegisterRouter.scala:87:24]
wire _out_T_10511 = ~out_womask_1085; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10513 = _out_T_10512; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_930 = _out_T_10513; // @[RegisterRouter.scala:87:24]
wire out_rimask_1086 = |_out_rimask_T_1086; // @[RegisterRouter.scala:87:24]
wire out_wimask_1086 = &_out_wimask_T_1086; // @[RegisterRouter.scala:87:24]
wire out_romask_1086 = |_out_romask_T_1086; // @[RegisterRouter.scala:87:24]
wire out_womask_1086 = &_out_womask_T_1086; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1086 = out_rivalid_1_940 & out_rimask_1086; // @[RegisterRouter.scala:87:24]
wire _out_T_10515 = out_f_rivalid_1086; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1086 = out_roready_1_940 & out_romask_1086; // @[RegisterRouter.scala:87:24]
wire _out_T_10516 = out_f_roready_1086; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1086 = out_wivalid_1_940 & out_wimask_1086; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1086 = out_woready_1_940 & out_womask_1086; // @[RegisterRouter.scala:87:24]
wire _out_T_10517 = ~out_rimask_1086; // @[RegisterRouter.scala:87:24]
wire _out_T_10518 = ~out_wimask_1086; // @[RegisterRouter.scala:87:24]
wire _out_T_10519 = ~out_romask_1086; // @[RegisterRouter.scala:87:24]
wire _out_T_10520 = ~out_womask_1086; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_930 = {hi_978, flags_0_go, _out_prepend_T_930}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_10521 = out_prepend_930; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_10522 = _out_T_10521; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_931 = _out_T_10522; // @[RegisterRouter.scala:87:24]
wire out_rimask_1087 = |_out_rimask_T_1087; // @[RegisterRouter.scala:87:24]
wire out_wimask_1087 = &_out_wimask_T_1087; // @[RegisterRouter.scala:87:24]
wire out_romask_1087 = |_out_romask_T_1087; // @[RegisterRouter.scala:87:24]
wire out_womask_1087 = &_out_womask_T_1087; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1087 = out_rivalid_1_941 & out_rimask_1087; // @[RegisterRouter.scala:87:24]
wire _out_T_10524 = out_f_rivalid_1087; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1087 = out_roready_1_941 & out_romask_1087; // @[RegisterRouter.scala:87:24]
wire _out_T_10525 = out_f_roready_1087; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1087 = out_wivalid_1_941 & out_wimask_1087; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1087 = out_woready_1_941 & out_womask_1087; // @[RegisterRouter.scala:87:24]
wire _out_T_10526 = ~out_rimask_1087; // @[RegisterRouter.scala:87:24]
wire _out_T_10527 = ~out_wimask_1087; // @[RegisterRouter.scala:87:24]
wire _out_T_10528 = ~out_romask_1087; // @[RegisterRouter.scala:87:24]
wire _out_T_10529 = ~out_womask_1087; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_931 = {hi_979, flags_0_go, _out_prepend_T_931}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_10530 = out_prepend_931; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_10531 = _out_T_10530; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_932 = _out_T_10531; // @[RegisterRouter.scala:87:24]
wire out_rimask_1088 = |_out_rimask_T_1088; // @[RegisterRouter.scala:87:24]
wire out_wimask_1088 = &_out_wimask_T_1088; // @[RegisterRouter.scala:87:24]
wire out_romask_1088 = |_out_romask_T_1088; // @[RegisterRouter.scala:87:24]
wire out_womask_1088 = &_out_womask_T_1088; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1088 = out_rivalid_1_942 & out_rimask_1088; // @[RegisterRouter.scala:87:24]
wire _out_T_10533 = out_f_rivalid_1088; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1088 = out_roready_1_942 & out_romask_1088; // @[RegisterRouter.scala:87:24]
wire _out_T_10534 = out_f_roready_1088; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1088 = out_wivalid_1_942 & out_wimask_1088; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1088 = out_woready_1_942 & out_womask_1088; // @[RegisterRouter.scala:87:24]
wire _out_T_10535 = ~out_rimask_1088; // @[RegisterRouter.scala:87:24]
wire _out_T_10536 = ~out_wimask_1088; // @[RegisterRouter.scala:87:24]
wire _out_T_10537 = ~out_romask_1088; // @[RegisterRouter.scala:87:24]
wire _out_T_10538 = ~out_womask_1088; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_932 = {hi_980, flags_0_go, _out_prepend_T_932}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_10539 = out_prepend_932; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_10540 = _out_T_10539; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_933 = _out_T_10540; // @[RegisterRouter.scala:87:24]
wire out_rimask_1089 = |_out_rimask_T_1089; // @[RegisterRouter.scala:87:24]
wire out_wimask_1089 = &_out_wimask_T_1089; // @[RegisterRouter.scala:87:24]
wire out_romask_1089 = |_out_romask_T_1089; // @[RegisterRouter.scala:87:24]
wire out_womask_1089 = &_out_womask_T_1089; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1089 = out_rivalid_1_943 & out_rimask_1089; // @[RegisterRouter.scala:87:24]
wire _out_T_10542 = out_f_rivalid_1089; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1089 = out_roready_1_943 & out_romask_1089; // @[RegisterRouter.scala:87:24]
wire _out_T_10543 = out_f_roready_1089; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1089 = out_wivalid_1_943 & out_wimask_1089; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1089 = out_woready_1_943 & out_womask_1089; // @[RegisterRouter.scala:87:24]
wire _out_T_10544 = ~out_rimask_1089; // @[RegisterRouter.scala:87:24]
wire _out_T_10545 = ~out_wimask_1089; // @[RegisterRouter.scala:87:24]
wire _out_T_10546 = ~out_romask_1089; // @[RegisterRouter.scala:87:24]
wire _out_T_10547 = ~out_womask_1089; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_933 = {hi_981, flags_0_go, _out_prepend_T_933}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_10548 = out_prepend_933; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_10549 = _out_T_10548; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_934 = _out_T_10549; // @[RegisterRouter.scala:87:24]
wire out_rimask_1090 = |_out_rimask_T_1090; // @[RegisterRouter.scala:87:24]
wire out_wimask_1090 = &_out_wimask_T_1090; // @[RegisterRouter.scala:87:24]
wire out_romask_1090 = |_out_romask_T_1090; // @[RegisterRouter.scala:87:24]
wire out_womask_1090 = &_out_womask_T_1090; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1090 = out_rivalid_1_944 & out_rimask_1090; // @[RegisterRouter.scala:87:24]
wire _out_T_10551 = out_f_rivalid_1090; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1090 = out_roready_1_944 & out_romask_1090; // @[RegisterRouter.scala:87:24]
wire _out_T_10552 = out_f_roready_1090; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1090 = out_wivalid_1_944 & out_wimask_1090; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1090 = out_woready_1_944 & out_womask_1090; // @[RegisterRouter.scala:87:24]
wire _out_T_10553 = ~out_rimask_1090; // @[RegisterRouter.scala:87:24]
wire _out_T_10554 = ~out_wimask_1090; // @[RegisterRouter.scala:87:24]
wire _out_T_10555 = ~out_romask_1090; // @[RegisterRouter.scala:87:24]
wire _out_T_10556 = ~out_womask_1090; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_934 = {hi_982, flags_0_go, _out_prepend_T_934}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_10557 = out_prepend_934; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_10558 = _out_T_10557; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_935 = _out_T_10558; // @[RegisterRouter.scala:87:24]
wire out_rimask_1091 = |_out_rimask_T_1091; // @[RegisterRouter.scala:87:24]
wire out_wimask_1091 = &_out_wimask_T_1091; // @[RegisterRouter.scala:87:24]
wire out_romask_1091 = |_out_romask_T_1091; // @[RegisterRouter.scala:87:24]
wire out_womask_1091 = &_out_womask_T_1091; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1091 = out_rivalid_1_945 & out_rimask_1091; // @[RegisterRouter.scala:87:24]
wire _out_T_10560 = out_f_rivalid_1091; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1091 = out_roready_1_945 & out_romask_1091; // @[RegisterRouter.scala:87:24]
wire _out_T_10561 = out_f_roready_1091; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1091 = out_wivalid_1_945 & out_wimask_1091; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1091 = out_woready_1_945 & out_womask_1091; // @[RegisterRouter.scala:87:24]
wire _out_T_10562 = ~out_rimask_1091; // @[RegisterRouter.scala:87:24]
wire _out_T_10563 = ~out_wimask_1091; // @[RegisterRouter.scala:87:24]
wire _out_T_10564 = ~out_romask_1091; // @[RegisterRouter.scala:87:24]
wire _out_T_10565 = ~out_womask_1091; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_935 = {hi_983, flags_0_go, _out_prepend_T_935}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_10566 = out_prepend_935; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_10567 = _out_T_10566; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_936 = _out_T_10567; // @[RegisterRouter.scala:87:24]
wire out_rimask_1092 = |_out_rimask_T_1092; // @[RegisterRouter.scala:87:24]
wire out_wimask_1092 = &_out_wimask_T_1092; // @[RegisterRouter.scala:87:24]
wire out_romask_1092 = |_out_romask_T_1092; // @[RegisterRouter.scala:87:24]
wire out_womask_1092 = &_out_womask_T_1092; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1092 = out_rivalid_1_946 & out_rimask_1092; // @[RegisterRouter.scala:87:24]
wire _out_T_10569 = out_f_rivalid_1092; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1092 = out_roready_1_946 & out_romask_1092; // @[RegisterRouter.scala:87:24]
wire _out_T_10570 = out_f_roready_1092; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1092 = out_wivalid_1_946 & out_wimask_1092; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1092 = out_woready_1_946 & out_womask_1092; // @[RegisterRouter.scala:87:24]
wire _out_T_10571 = ~out_rimask_1092; // @[RegisterRouter.scala:87:24]
wire _out_T_10572 = ~out_wimask_1092; // @[RegisterRouter.scala:87:24]
wire _out_T_10573 = ~out_romask_1092; // @[RegisterRouter.scala:87:24]
wire _out_T_10574 = ~out_womask_1092; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_936 = {hi_984, flags_0_go, _out_prepend_T_936}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_10575 = out_prepend_936; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_10576 = _out_T_10575; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_250 = _out_T_10576; // @[MuxLiteral.scala:49:48]
wire out_rimask_1093 = |_out_rimask_T_1093; // @[RegisterRouter.scala:87:24]
wire out_wimask_1093 = &_out_wimask_T_1093; // @[RegisterRouter.scala:87:24]
wire out_romask_1093 = |_out_romask_T_1093; // @[RegisterRouter.scala:87:24]
wire out_womask_1093 = &_out_womask_T_1093; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1093 = out_rivalid_1_947 & out_rimask_1093; // @[RegisterRouter.scala:87:24]
wire _out_T_10578 = out_f_rivalid_1093; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1093 = out_roready_1_947 & out_romask_1093; // @[RegisterRouter.scala:87:24]
wire _out_T_10579 = out_f_roready_1093; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1093 = out_wivalid_1_947 & out_wimask_1093; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1093 = out_woready_1_947 & out_womask_1093; // @[RegisterRouter.scala:87:24]
wire _out_T_10580 = ~out_rimask_1093; // @[RegisterRouter.scala:87:24]
wire _out_T_10581 = ~out_wimask_1093; // @[RegisterRouter.scala:87:24]
wire _out_T_10582 = ~out_romask_1093; // @[RegisterRouter.scala:87:24]
wire _out_T_10583 = ~out_womask_1093; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10585 = _out_T_10584; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_937 = _out_T_10585; // @[RegisterRouter.scala:87:24]
wire out_rimask_1094 = |_out_rimask_T_1094; // @[RegisterRouter.scala:87:24]
wire out_wimask_1094 = &_out_wimask_T_1094; // @[RegisterRouter.scala:87:24]
wire out_romask_1094 = |_out_romask_T_1094; // @[RegisterRouter.scala:87:24]
wire out_womask_1094 = &_out_womask_T_1094; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1094 = out_rivalid_1_948 & out_rimask_1094; // @[RegisterRouter.scala:87:24]
wire _out_T_10587 = out_f_rivalid_1094; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1094 = out_roready_1_948 & out_romask_1094; // @[RegisterRouter.scala:87:24]
wire _out_T_10588 = out_f_roready_1094; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1094 = out_wivalid_1_948 & out_wimask_1094; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1094 = out_woready_1_948 & out_womask_1094; // @[RegisterRouter.scala:87:24]
wire _out_T_10589 = ~out_rimask_1094; // @[RegisterRouter.scala:87:24]
wire _out_T_10590 = ~out_wimask_1094; // @[RegisterRouter.scala:87:24]
wire _out_T_10591 = ~out_romask_1094; // @[RegisterRouter.scala:87:24]
wire _out_T_10592 = ~out_womask_1094; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_937 = {hi_826, flags_0_go, _out_prepend_T_937}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_10593 = out_prepend_937; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_10594 = _out_T_10593; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_938 = _out_T_10594; // @[RegisterRouter.scala:87:24]
wire out_rimask_1095 = |_out_rimask_T_1095; // @[RegisterRouter.scala:87:24]
wire out_wimask_1095 = &_out_wimask_T_1095; // @[RegisterRouter.scala:87:24]
wire out_romask_1095 = |_out_romask_T_1095; // @[RegisterRouter.scala:87:24]
wire out_womask_1095 = &_out_womask_T_1095; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1095 = out_rivalid_1_949 & out_rimask_1095; // @[RegisterRouter.scala:87:24]
wire _out_T_10596 = out_f_rivalid_1095; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1095 = out_roready_1_949 & out_romask_1095; // @[RegisterRouter.scala:87:24]
wire _out_T_10597 = out_f_roready_1095; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1095 = out_wivalid_1_949 & out_wimask_1095; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1095 = out_woready_1_949 & out_womask_1095; // @[RegisterRouter.scala:87:24]
wire _out_T_10598 = ~out_rimask_1095; // @[RegisterRouter.scala:87:24]
wire _out_T_10599 = ~out_wimask_1095; // @[RegisterRouter.scala:87:24]
wire _out_T_10600 = ~out_romask_1095; // @[RegisterRouter.scala:87:24]
wire _out_T_10601 = ~out_womask_1095; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_938 = {hi_827, flags_0_go, _out_prepend_T_938}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_10602 = out_prepend_938; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_10603 = _out_T_10602; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_939 = _out_T_10603; // @[RegisterRouter.scala:87:24]
wire out_rimask_1096 = |_out_rimask_T_1096; // @[RegisterRouter.scala:87:24]
wire out_wimask_1096 = &_out_wimask_T_1096; // @[RegisterRouter.scala:87:24]
wire out_romask_1096 = |_out_romask_T_1096; // @[RegisterRouter.scala:87:24]
wire out_womask_1096 = &_out_womask_T_1096; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1096 = out_rivalid_1_950 & out_rimask_1096; // @[RegisterRouter.scala:87:24]
wire _out_T_10605 = out_f_rivalid_1096; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1096 = out_roready_1_950 & out_romask_1096; // @[RegisterRouter.scala:87:24]
wire _out_T_10606 = out_f_roready_1096; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1096 = out_wivalid_1_950 & out_wimask_1096; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1096 = out_woready_1_950 & out_womask_1096; // @[RegisterRouter.scala:87:24]
wire _out_T_10607 = ~out_rimask_1096; // @[RegisterRouter.scala:87:24]
wire _out_T_10608 = ~out_wimask_1096; // @[RegisterRouter.scala:87:24]
wire _out_T_10609 = ~out_romask_1096; // @[RegisterRouter.scala:87:24]
wire _out_T_10610 = ~out_womask_1096; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_939 = {hi_828, flags_0_go, _out_prepend_T_939}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_10611 = out_prepend_939; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_10612 = _out_T_10611; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_940 = _out_T_10612; // @[RegisterRouter.scala:87:24]
wire out_rimask_1097 = |_out_rimask_T_1097; // @[RegisterRouter.scala:87:24]
wire out_wimask_1097 = &_out_wimask_T_1097; // @[RegisterRouter.scala:87:24]
wire out_romask_1097 = |_out_romask_T_1097; // @[RegisterRouter.scala:87:24]
wire out_womask_1097 = &_out_womask_T_1097; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1097 = out_rivalid_1_951 & out_rimask_1097; // @[RegisterRouter.scala:87:24]
wire _out_T_10614 = out_f_rivalid_1097; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1097 = out_roready_1_951 & out_romask_1097; // @[RegisterRouter.scala:87:24]
wire _out_T_10615 = out_f_roready_1097; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1097 = out_wivalid_1_951 & out_wimask_1097; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1097 = out_woready_1_951 & out_womask_1097; // @[RegisterRouter.scala:87:24]
wire _out_T_10616 = ~out_rimask_1097; // @[RegisterRouter.scala:87:24]
wire _out_T_10617 = ~out_wimask_1097; // @[RegisterRouter.scala:87:24]
wire _out_T_10618 = ~out_romask_1097; // @[RegisterRouter.scala:87:24]
wire _out_T_10619 = ~out_womask_1097; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_940 = {hi_829, flags_0_go, _out_prepend_T_940}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_10620 = out_prepend_940; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_10621 = _out_T_10620; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_941 = _out_T_10621; // @[RegisterRouter.scala:87:24]
wire out_rimask_1098 = |_out_rimask_T_1098; // @[RegisterRouter.scala:87:24]
wire out_wimask_1098 = &_out_wimask_T_1098; // @[RegisterRouter.scala:87:24]
wire out_romask_1098 = |_out_romask_T_1098; // @[RegisterRouter.scala:87:24]
wire out_womask_1098 = &_out_womask_T_1098; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1098 = out_rivalid_1_952 & out_rimask_1098; // @[RegisterRouter.scala:87:24]
wire _out_T_10623 = out_f_rivalid_1098; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1098 = out_roready_1_952 & out_romask_1098; // @[RegisterRouter.scala:87:24]
wire _out_T_10624 = out_f_roready_1098; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1098 = out_wivalid_1_952 & out_wimask_1098; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1098 = out_woready_1_952 & out_womask_1098; // @[RegisterRouter.scala:87:24]
wire _out_T_10625 = ~out_rimask_1098; // @[RegisterRouter.scala:87:24]
wire _out_T_10626 = ~out_wimask_1098; // @[RegisterRouter.scala:87:24]
wire _out_T_10627 = ~out_romask_1098; // @[RegisterRouter.scala:87:24]
wire _out_T_10628 = ~out_womask_1098; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_941 = {hi_830, flags_0_go, _out_prepend_T_941}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_10629 = out_prepend_941; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_10630 = _out_T_10629; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_942 = _out_T_10630; // @[RegisterRouter.scala:87:24]
wire out_rimask_1099 = |_out_rimask_T_1099; // @[RegisterRouter.scala:87:24]
wire out_wimask_1099 = &_out_wimask_T_1099; // @[RegisterRouter.scala:87:24]
wire out_romask_1099 = |_out_romask_T_1099; // @[RegisterRouter.scala:87:24]
wire out_womask_1099 = &_out_womask_T_1099; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1099 = out_rivalid_1_953 & out_rimask_1099; // @[RegisterRouter.scala:87:24]
wire _out_T_10632 = out_f_rivalid_1099; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1099 = out_roready_1_953 & out_romask_1099; // @[RegisterRouter.scala:87:24]
wire _out_T_10633 = out_f_roready_1099; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1099 = out_wivalid_1_953 & out_wimask_1099; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1099 = out_woready_1_953 & out_womask_1099; // @[RegisterRouter.scala:87:24]
wire _out_T_10634 = ~out_rimask_1099; // @[RegisterRouter.scala:87:24]
wire _out_T_10635 = ~out_wimask_1099; // @[RegisterRouter.scala:87:24]
wire _out_T_10636 = ~out_romask_1099; // @[RegisterRouter.scala:87:24]
wire _out_T_10637 = ~out_womask_1099; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_942 = {hi_831, flags_0_go, _out_prepend_T_942}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_10638 = out_prepend_942; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_10639 = _out_T_10638; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_943 = _out_T_10639; // @[RegisterRouter.scala:87:24]
wire out_rimask_1100 = |_out_rimask_T_1100; // @[RegisterRouter.scala:87:24]
wire out_wimask_1100 = &_out_wimask_T_1100; // @[RegisterRouter.scala:87:24]
wire out_romask_1100 = |_out_romask_T_1100; // @[RegisterRouter.scala:87:24]
wire out_womask_1100 = &_out_womask_T_1100; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1100 = out_rivalid_1_954 & out_rimask_1100; // @[RegisterRouter.scala:87:24]
wire _out_T_10641 = out_f_rivalid_1100; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1100 = out_roready_1_954 & out_romask_1100; // @[RegisterRouter.scala:87:24]
wire _out_T_10642 = out_f_roready_1100; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1100 = out_wivalid_1_954 & out_wimask_1100; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1100 = out_woready_1_954 & out_womask_1100; // @[RegisterRouter.scala:87:24]
wire _out_T_10643 = ~out_rimask_1100; // @[RegisterRouter.scala:87:24]
wire _out_T_10644 = ~out_wimask_1100; // @[RegisterRouter.scala:87:24]
wire _out_T_10645 = ~out_romask_1100; // @[RegisterRouter.scala:87:24]
wire _out_T_10646 = ~out_womask_1100; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_943 = {hi_832, flags_0_go, _out_prepend_T_943}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_10647 = out_prepend_943; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_10648 = _out_T_10647; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_231 = _out_T_10648; // @[MuxLiteral.scala:49:48]
wire out_rimask_1101 = |_out_rimask_T_1101; // @[RegisterRouter.scala:87:24]
wire out_wimask_1101 = &_out_wimask_T_1101; // @[RegisterRouter.scala:87:24]
wire out_romask_1101 = |_out_romask_T_1101; // @[RegisterRouter.scala:87:24]
wire out_womask_1101 = &_out_womask_T_1101; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1101 = out_rivalid_1_955 & out_rimask_1101; // @[RegisterRouter.scala:87:24]
wire _out_T_10650 = out_f_rivalid_1101; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1101 = out_roready_1_955 & out_romask_1101; // @[RegisterRouter.scala:87:24]
wire _out_T_10651 = out_f_roready_1101; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1101 = out_wivalid_1_955 & out_wimask_1101; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1101 = out_woready_1_955 & out_womask_1101; // @[RegisterRouter.scala:87:24]
wire _out_T_10652 = ~out_rimask_1101; // @[RegisterRouter.scala:87:24]
wire _out_T_10653 = ~out_wimask_1101; // @[RegisterRouter.scala:87:24]
wire _out_T_10654 = ~out_romask_1101; // @[RegisterRouter.scala:87:24]
wire _out_T_10655 = ~out_womask_1101; // @[RegisterRouter.scala:87:24]
wire out_rimask_1102 = |_out_rimask_T_1102; // @[RegisterRouter.scala:87:24]
wire out_wimask_1102 = &_out_wimask_T_1102; // @[RegisterRouter.scala:87:24]
wire out_romask_1102 = |_out_romask_T_1102; // @[RegisterRouter.scala:87:24]
wire out_womask_1102 = &_out_womask_T_1102; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1102 = out_rivalid_1_956 & out_rimask_1102; // @[RegisterRouter.scala:87:24]
wire _out_T_10659 = out_f_rivalid_1102; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1102 = out_roready_1_956 & out_romask_1102; // @[RegisterRouter.scala:87:24]
wire _out_T_10660 = out_f_roready_1102; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1102 = out_wivalid_1_956 & out_wimask_1102; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1102 = out_woready_1_956 & out_womask_1102; // @[RegisterRouter.scala:87:24]
wire _out_T_10661 = ~out_rimask_1102; // @[RegisterRouter.scala:87:24]
wire _out_T_10662 = ~out_wimask_1102; // @[RegisterRouter.scala:87:24]
wire _out_T_10663 = ~out_romask_1102; // @[RegisterRouter.scala:87:24]
wire _out_T_10664 = ~out_womask_1102; // @[RegisterRouter.scala:87:24]
wire out_rimask_1103 = |_out_rimask_T_1103; // @[RegisterRouter.scala:87:24]
wire out_wimask_1103 = &_out_wimask_T_1103; // @[RegisterRouter.scala:87:24]
wire out_romask_1103 = |_out_romask_T_1103; // @[RegisterRouter.scala:87:24]
wire out_womask_1103 = &_out_womask_T_1103; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1103 = out_rivalid_1_957 & out_rimask_1103; // @[RegisterRouter.scala:87:24]
wire _out_T_10668 = out_f_rivalid_1103; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1103 = out_roready_1_957 & out_romask_1103; // @[RegisterRouter.scala:87:24]
wire _out_T_10669 = out_f_roready_1103; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1103 = out_wivalid_1_957 & out_wimask_1103; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1103 = out_woready_1_957 & out_womask_1103; // @[RegisterRouter.scala:87:24]
wire _out_T_10670 = ~out_rimask_1103; // @[RegisterRouter.scala:87:24]
wire _out_T_10671 = ~out_wimask_1103; // @[RegisterRouter.scala:87:24]
wire _out_T_10672 = ~out_romask_1103; // @[RegisterRouter.scala:87:24]
wire _out_T_10673 = ~out_womask_1103; // @[RegisterRouter.scala:87:24]
wire out_rimask_1104 = |_out_rimask_T_1104; // @[RegisterRouter.scala:87:24]
wire out_wimask_1104 = &_out_wimask_T_1104; // @[RegisterRouter.scala:87:24]
wire out_romask_1104 = |_out_romask_T_1104; // @[RegisterRouter.scala:87:24]
wire out_womask_1104 = &_out_womask_T_1104; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1104 = out_rivalid_1_958 & out_rimask_1104; // @[RegisterRouter.scala:87:24]
wire _out_T_10677 = out_f_rivalid_1104; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1104 = out_roready_1_958 & out_romask_1104; // @[RegisterRouter.scala:87:24]
wire _out_T_10678 = out_f_roready_1104; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1104 = out_wivalid_1_958 & out_wimask_1104; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1104 = out_woready_1_958 & out_womask_1104; // @[RegisterRouter.scala:87:24]
wire _out_T_10679 = ~out_rimask_1104; // @[RegisterRouter.scala:87:24]
wire _out_T_10680 = ~out_wimask_1104; // @[RegisterRouter.scala:87:24]
wire _out_T_10681 = ~out_romask_1104; // @[RegisterRouter.scala:87:24]
wire _out_T_10682 = ~out_womask_1104; // @[RegisterRouter.scala:87:24]
wire out_rimask_1105 = |_out_rimask_T_1105; // @[RegisterRouter.scala:87:24]
wire out_wimask_1105 = &_out_wimask_T_1105; // @[RegisterRouter.scala:87:24]
wire out_romask_1105 = |_out_romask_T_1105; // @[RegisterRouter.scala:87:24]
wire out_womask_1105 = &_out_womask_T_1105; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1105 = out_rivalid_1_959 & out_rimask_1105; // @[RegisterRouter.scala:87:24]
wire _out_T_10686 = out_f_rivalid_1105; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1105 = out_roready_1_959 & out_romask_1105; // @[RegisterRouter.scala:87:24]
wire _out_T_10687 = out_f_roready_1105; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1105 = out_wivalid_1_959 & out_wimask_1105; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1105 = out_woready_1_959 & out_womask_1105; // @[RegisterRouter.scala:87:24]
wire _out_T_10688 = ~out_rimask_1105; // @[RegisterRouter.scala:87:24]
wire _out_T_10689 = ~out_wimask_1105; // @[RegisterRouter.scala:87:24]
wire _out_T_10690 = ~out_romask_1105; // @[RegisterRouter.scala:87:24]
wire _out_T_10691 = ~out_womask_1105; // @[RegisterRouter.scala:87:24]
wire out_rimask_1106 = |_out_rimask_T_1106; // @[RegisterRouter.scala:87:24]
wire out_wimask_1106 = &_out_wimask_T_1106; // @[RegisterRouter.scala:87:24]
wire out_romask_1106 = |_out_romask_T_1106; // @[RegisterRouter.scala:87:24]
wire out_womask_1106 = &_out_womask_T_1106; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1106 = out_rivalid_1_960 & out_rimask_1106; // @[RegisterRouter.scala:87:24]
wire _out_T_10695 = out_f_rivalid_1106; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1106 = out_roready_1_960 & out_romask_1106; // @[RegisterRouter.scala:87:24]
wire _out_T_10696 = out_f_roready_1106; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1106 = out_wivalid_1_960 & out_wimask_1106; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1106 = out_woready_1_960 & out_womask_1106; // @[RegisterRouter.scala:87:24]
wire _out_T_10697 = ~out_rimask_1106; // @[RegisterRouter.scala:87:24]
wire _out_T_10698 = ~out_wimask_1106; // @[RegisterRouter.scala:87:24]
wire _out_T_10699 = ~out_romask_1106; // @[RegisterRouter.scala:87:24]
wire _out_T_10700 = ~out_womask_1106; // @[RegisterRouter.scala:87:24]
wire out_rimask_1107 = |_out_rimask_T_1107; // @[RegisterRouter.scala:87:24]
wire out_wimask_1107 = &_out_wimask_T_1107; // @[RegisterRouter.scala:87:24]
wire out_romask_1107 = |_out_romask_T_1107; // @[RegisterRouter.scala:87:24]
wire out_womask_1107 = &_out_womask_T_1107; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1107 = out_rivalid_1_961 & out_rimask_1107; // @[RegisterRouter.scala:87:24]
wire _out_T_10704 = out_f_rivalid_1107; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1107 = out_roready_1_961 & out_romask_1107; // @[RegisterRouter.scala:87:24]
wire _out_T_10705 = out_f_roready_1107; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1107 = out_wivalid_1_961 & out_wimask_1107; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1107 = out_woready_1_961 & out_womask_1107; // @[RegisterRouter.scala:87:24]
wire _out_T_10706 = ~out_rimask_1107; // @[RegisterRouter.scala:87:24]
wire _out_T_10707 = ~out_wimask_1107; // @[RegisterRouter.scala:87:24]
wire _out_T_10708 = ~out_romask_1107; // @[RegisterRouter.scala:87:24]
wire _out_T_10709 = ~out_womask_1107; // @[RegisterRouter.scala:87:24]
wire out_rimask_1108 = |_out_rimask_T_1108; // @[RegisterRouter.scala:87:24]
wire out_wimask_1108 = &_out_wimask_T_1108; // @[RegisterRouter.scala:87:24]
wire out_romask_1108 = |_out_romask_T_1108; // @[RegisterRouter.scala:87:24]
wire out_womask_1108 = &_out_womask_T_1108; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1108 = out_rivalid_1_962 & out_rimask_1108; // @[RegisterRouter.scala:87:24]
wire _out_T_10713 = out_f_rivalid_1108; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1108 = out_roready_1_962 & out_romask_1108; // @[RegisterRouter.scala:87:24]
wire _out_T_10714 = out_f_roready_1108; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1108 = out_wivalid_1_962 & out_wimask_1108; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1108 = out_woready_1_962 & out_womask_1108; // @[RegisterRouter.scala:87:24]
wire _out_T_10715 = ~out_rimask_1108; // @[RegisterRouter.scala:87:24]
wire _out_T_10716 = ~out_wimask_1108; // @[RegisterRouter.scala:87:24]
wire _out_T_10717 = ~out_romask_1108; // @[RegisterRouter.scala:87:24]
wire _out_T_10718 = ~out_womask_1108; // @[RegisterRouter.scala:87:24]
wire out_rimask_1109 = |_out_rimask_T_1109; // @[RegisterRouter.scala:87:24]
wire out_wimask_1109 = &_out_wimask_T_1109; // @[RegisterRouter.scala:87:24]
wire out_romask_1109 = |_out_romask_T_1109; // @[RegisterRouter.scala:87:24]
wire out_womask_1109 = &_out_womask_T_1109; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1109 = out_rivalid_1_963 & out_rimask_1109; // @[RegisterRouter.scala:87:24]
wire _out_T_10722 = out_f_rivalid_1109; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1109 = out_roready_1_963 & out_romask_1109; // @[RegisterRouter.scala:87:24]
wire _out_T_10723 = out_f_roready_1109; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1109 = out_wivalid_1_963 & out_wimask_1109; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1109 = out_woready_1_963 & out_womask_1109; // @[RegisterRouter.scala:87:24]
wire _out_T_10724 = ~out_rimask_1109; // @[RegisterRouter.scala:87:24]
wire _out_T_10725 = ~out_wimask_1109; // @[RegisterRouter.scala:87:24]
wire _out_T_10726 = ~out_romask_1109; // @[RegisterRouter.scala:87:24]
wire _out_T_10727 = ~out_womask_1109; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10729 = _out_T_10728; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_951 = _out_T_10729; // @[RegisterRouter.scala:87:24]
wire out_rimask_1110 = |_out_rimask_T_1110; // @[RegisterRouter.scala:87:24]
wire out_wimask_1110 = &_out_wimask_T_1110; // @[RegisterRouter.scala:87:24]
wire out_romask_1110 = |_out_romask_T_1110; // @[RegisterRouter.scala:87:24]
wire out_womask_1110 = &_out_womask_T_1110; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1110 = out_rivalid_1_964 & out_rimask_1110; // @[RegisterRouter.scala:87:24]
wire _out_T_10731 = out_f_rivalid_1110; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1110 = out_roready_1_964 & out_romask_1110; // @[RegisterRouter.scala:87:24]
wire _out_T_10732 = out_f_roready_1110; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1110 = out_wivalid_1_964 & out_wimask_1110; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1110 = out_woready_1_964 & out_womask_1110; // @[RegisterRouter.scala:87:24]
wire _out_T_10733 = ~out_rimask_1110; // @[RegisterRouter.scala:87:24]
wire _out_T_10734 = ~out_wimask_1110; // @[RegisterRouter.scala:87:24]
wire _out_T_10735 = ~out_romask_1110; // @[RegisterRouter.scala:87:24]
wire _out_T_10736 = ~out_womask_1110; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_951 = {hi_242, flags_0_go, _out_prepend_T_951}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_10737 = out_prepend_951; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_10738 = _out_T_10737; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_952 = _out_T_10738; // @[RegisterRouter.scala:87:24]
wire out_rimask_1111 = |_out_rimask_T_1111; // @[RegisterRouter.scala:87:24]
wire out_wimask_1111 = &_out_wimask_T_1111; // @[RegisterRouter.scala:87:24]
wire out_romask_1111 = |_out_romask_T_1111; // @[RegisterRouter.scala:87:24]
wire out_womask_1111 = &_out_womask_T_1111; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1111 = out_rivalid_1_965 & out_rimask_1111; // @[RegisterRouter.scala:87:24]
wire _out_T_10740 = out_f_rivalid_1111; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1111 = out_roready_1_965 & out_romask_1111; // @[RegisterRouter.scala:87:24]
wire _out_T_10741 = out_f_roready_1111; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1111 = out_wivalid_1_965 & out_wimask_1111; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1111 = out_woready_1_965 & out_womask_1111; // @[RegisterRouter.scala:87:24]
wire _out_T_10742 = ~out_rimask_1111; // @[RegisterRouter.scala:87:24]
wire _out_T_10743 = ~out_wimask_1111; // @[RegisterRouter.scala:87:24]
wire _out_T_10744 = ~out_romask_1111; // @[RegisterRouter.scala:87:24]
wire _out_T_10745 = ~out_womask_1111; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_952 = {hi_243, flags_0_go, _out_prepend_T_952}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_10746 = out_prepend_952; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_10747 = _out_T_10746; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_953 = _out_T_10747; // @[RegisterRouter.scala:87:24]
wire out_rimask_1112 = |_out_rimask_T_1112; // @[RegisterRouter.scala:87:24]
wire out_wimask_1112 = &_out_wimask_T_1112; // @[RegisterRouter.scala:87:24]
wire out_romask_1112 = |_out_romask_T_1112; // @[RegisterRouter.scala:87:24]
wire out_womask_1112 = &_out_womask_T_1112; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1112 = out_rivalid_1_966 & out_rimask_1112; // @[RegisterRouter.scala:87:24]
wire _out_T_10749 = out_f_rivalid_1112; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1112 = out_roready_1_966 & out_romask_1112; // @[RegisterRouter.scala:87:24]
wire _out_T_10750 = out_f_roready_1112; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1112 = out_wivalid_1_966 & out_wimask_1112; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1112 = out_woready_1_966 & out_womask_1112; // @[RegisterRouter.scala:87:24]
wire _out_T_10751 = ~out_rimask_1112; // @[RegisterRouter.scala:87:24]
wire _out_T_10752 = ~out_wimask_1112; // @[RegisterRouter.scala:87:24]
wire _out_T_10753 = ~out_romask_1112; // @[RegisterRouter.scala:87:24]
wire _out_T_10754 = ~out_womask_1112; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_953 = {hi_244, flags_0_go, _out_prepend_T_953}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_10755 = out_prepend_953; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_10756 = _out_T_10755; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_954 = _out_T_10756; // @[RegisterRouter.scala:87:24]
wire out_rimask_1113 = |_out_rimask_T_1113; // @[RegisterRouter.scala:87:24]
wire out_wimask_1113 = &_out_wimask_T_1113; // @[RegisterRouter.scala:87:24]
wire out_romask_1113 = |_out_romask_T_1113; // @[RegisterRouter.scala:87:24]
wire out_womask_1113 = &_out_womask_T_1113; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1113 = out_rivalid_1_967 & out_rimask_1113; // @[RegisterRouter.scala:87:24]
wire _out_T_10758 = out_f_rivalid_1113; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1113 = out_roready_1_967 & out_romask_1113; // @[RegisterRouter.scala:87:24]
wire _out_T_10759 = out_f_roready_1113; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1113 = out_wivalid_1_967 & out_wimask_1113; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1113 = out_woready_1_967 & out_womask_1113; // @[RegisterRouter.scala:87:24]
wire _out_T_10760 = ~out_rimask_1113; // @[RegisterRouter.scala:87:24]
wire _out_T_10761 = ~out_wimask_1113; // @[RegisterRouter.scala:87:24]
wire _out_T_10762 = ~out_romask_1113; // @[RegisterRouter.scala:87:24]
wire _out_T_10763 = ~out_womask_1113; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_954 = {hi_245, flags_0_go, _out_prepend_T_954}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_10764 = out_prepend_954; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_10765 = _out_T_10764; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_955 = _out_T_10765; // @[RegisterRouter.scala:87:24]
wire out_rimask_1114 = |_out_rimask_T_1114; // @[RegisterRouter.scala:87:24]
wire out_wimask_1114 = &_out_wimask_T_1114; // @[RegisterRouter.scala:87:24]
wire out_romask_1114 = |_out_romask_T_1114; // @[RegisterRouter.scala:87:24]
wire out_womask_1114 = &_out_womask_T_1114; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1114 = out_rivalid_1_968 & out_rimask_1114; // @[RegisterRouter.scala:87:24]
wire _out_T_10767 = out_f_rivalid_1114; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1114 = out_roready_1_968 & out_romask_1114; // @[RegisterRouter.scala:87:24]
wire _out_T_10768 = out_f_roready_1114; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1114 = out_wivalid_1_968 & out_wimask_1114; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1114 = out_woready_1_968 & out_womask_1114; // @[RegisterRouter.scala:87:24]
wire _out_T_10769 = ~out_rimask_1114; // @[RegisterRouter.scala:87:24]
wire _out_T_10770 = ~out_wimask_1114; // @[RegisterRouter.scala:87:24]
wire _out_T_10771 = ~out_romask_1114; // @[RegisterRouter.scala:87:24]
wire _out_T_10772 = ~out_womask_1114; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_955 = {hi_246, flags_0_go, _out_prepend_T_955}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_10773 = out_prepend_955; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_10774 = _out_T_10773; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_956 = _out_T_10774; // @[RegisterRouter.scala:87:24]
wire out_rimask_1115 = |_out_rimask_T_1115; // @[RegisterRouter.scala:87:24]
wire out_wimask_1115 = &_out_wimask_T_1115; // @[RegisterRouter.scala:87:24]
wire out_romask_1115 = |_out_romask_T_1115; // @[RegisterRouter.scala:87:24]
wire out_womask_1115 = &_out_womask_T_1115; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1115 = out_rivalid_1_969 & out_rimask_1115; // @[RegisterRouter.scala:87:24]
wire _out_T_10776 = out_f_rivalid_1115; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1115 = out_roready_1_969 & out_romask_1115; // @[RegisterRouter.scala:87:24]
wire _out_T_10777 = out_f_roready_1115; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1115 = out_wivalid_1_969 & out_wimask_1115; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1115 = out_woready_1_969 & out_womask_1115; // @[RegisterRouter.scala:87:24]
wire _out_T_10778 = ~out_rimask_1115; // @[RegisterRouter.scala:87:24]
wire _out_T_10779 = ~out_wimask_1115; // @[RegisterRouter.scala:87:24]
wire _out_T_10780 = ~out_romask_1115; // @[RegisterRouter.scala:87:24]
wire _out_T_10781 = ~out_womask_1115; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_956 = {hi_247, flags_0_go, _out_prepend_T_956}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_10782 = out_prepend_956; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_10783 = _out_T_10782; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_957 = _out_T_10783; // @[RegisterRouter.scala:87:24]
wire out_rimask_1116 = |_out_rimask_T_1116; // @[RegisterRouter.scala:87:24]
wire out_wimask_1116 = &_out_wimask_T_1116; // @[RegisterRouter.scala:87:24]
wire out_romask_1116 = |_out_romask_T_1116; // @[RegisterRouter.scala:87:24]
wire out_womask_1116 = &_out_womask_T_1116; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1116 = out_rivalid_1_970 & out_rimask_1116; // @[RegisterRouter.scala:87:24]
wire _out_T_10785 = out_f_rivalid_1116; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1116 = out_roready_1_970 & out_romask_1116; // @[RegisterRouter.scala:87:24]
wire _out_T_10786 = out_f_roready_1116; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1116 = out_wivalid_1_970 & out_wimask_1116; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1116 = out_woready_1_970 & out_womask_1116; // @[RegisterRouter.scala:87:24]
wire _out_T_10787 = ~out_rimask_1116; // @[RegisterRouter.scala:87:24]
wire _out_T_10788 = ~out_wimask_1116; // @[RegisterRouter.scala:87:24]
wire _out_T_10789 = ~out_romask_1116; // @[RegisterRouter.scala:87:24]
wire _out_T_10790 = ~out_womask_1116; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_957 = {hi_248, flags_0_go, _out_prepend_T_957}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_10791 = out_prepend_957; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_10792 = _out_T_10791; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_158 = _out_T_10792; // @[MuxLiteral.scala:49:48]
wire out_rimask_1117 = |_out_rimask_T_1117; // @[RegisterRouter.scala:87:24]
wire out_wimask_1117 = &_out_wimask_T_1117; // @[RegisterRouter.scala:87:24]
wire out_romask_1117 = |_out_romask_T_1117; // @[RegisterRouter.scala:87:24]
wire out_womask_1117 = &_out_womask_T_1117; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1117 = out_rivalid_1_971 & out_rimask_1117; // @[RegisterRouter.scala:87:24]
wire _out_T_10794 = out_f_rivalid_1117; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1117 = out_roready_1_971 & out_romask_1117; // @[RegisterRouter.scala:87:24]
wire _out_T_10795 = out_f_roready_1117; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1117 = out_wivalid_1_971 & out_wimask_1117; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1117 = out_woready_1_971 & out_womask_1117; // @[RegisterRouter.scala:87:24]
wire _out_T_10796 = ~out_rimask_1117; // @[RegisterRouter.scala:87:24]
wire _out_T_10797 = ~out_wimask_1117; // @[RegisterRouter.scala:87:24]
wire _out_T_10798 = ~out_romask_1117; // @[RegisterRouter.scala:87:24]
wire _out_T_10799 = ~out_womask_1117; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10801 = _out_T_10800; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_958 = _out_T_10801; // @[RegisterRouter.scala:87:24]
wire out_rimask_1118 = |_out_rimask_T_1118; // @[RegisterRouter.scala:87:24]
wire out_wimask_1118 = &_out_wimask_T_1118; // @[RegisterRouter.scala:87:24]
wire out_romask_1118 = |_out_romask_T_1118; // @[RegisterRouter.scala:87:24]
wire out_womask_1118 = &_out_womask_T_1118; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1118 = out_rivalid_1_972 & out_rimask_1118; // @[RegisterRouter.scala:87:24]
wire _out_T_10803 = out_f_rivalid_1118; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1118 = out_roready_1_972 & out_romask_1118; // @[RegisterRouter.scala:87:24]
wire _out_T_10804 = out_f_roready_1118; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1118 = out_wivalid_1_972 & out_wimask_1118; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1118 = out_woready_1_972 & out_womask_1118; // @[RegisterRouter.scala:87:24]
wire _out_T_10805 = ~out_rimask_1118; // @[RegisterRouter.scala:87:24]
wire _out_T_10806 = ~out_wimask_1118; // @[RegisterRouter.scala:87:24]
wire _out_T_10807 = ~out_romask_1118; // @[RegisterRouter.scala:87:24]
wire _out_T_10808 = ~out_womask_1118; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_958 = {hi_466, flags_0_go, _out_prepend_T_958}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_10809 = out_prepend_958; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_10810 = _out_T_10809; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_959 = _out_T_10810; // @[RegisterRouter.scala:87:24]
wire out_rimask_1119 = |_out_rimask_T_1119; // @[RegisterRouter.scala:87:24]
wire out_wimask_1119 = &_out_wimask_T_1119; // @[RegisterRouter.scala:87:24]
wire out_romask_1119 = |_out_romask_T_1119; // @[RegisterRouter.scala:87:24]
wire out_womask_1119 = &_out_womask_T_1119; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1119 = out_rivalid_1_973 & out_rimask_1119; // @[RegisterRouter.scala:87:24]
wire _out_T_10812 = out_f_rivalid_1119; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1119 = out_roready_1_973 & out_romask_1119; // @[RegisterRouter.scala:87:24]
wire _out_T_10813 = out_f_roready_1119; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1119 = out_wivalid_1_973 & out_wimask_1119; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1119 = out_woready_1_973 & out_womask_1119; // @[RegisterRouter.scala:87:24]
wire _out_T_10814 = ~out_rimask_1119; // @[RegisterRouter.scala:87:24]
wire _out_T_10815 = ~out_wimask_1119; // @[RegisterRouter.scala:87:24]
wire _out_T_10816 = ~out_romask_1119; // @[RegisterRouter.scala:87:24]
wire _out_T_10817 = ~out_womask_1119; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_959 = {hi_467, flags_0_go, _out_prepend_T_959}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_10818 = out_prepend_959; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_10819 = _out_T_10818; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_960 = _out_T_10819; // @[RegisterRouter.scala:87:24]
wire out_rimask_1120 = |_out_rimask_T_1120; // @[RegisterRouter.scala:87:24]
wire out_wimask_1120 = &_out_wimask_T_1120; // @[RegisterRouter.scala:87:24]
wire out_romask_1120 = |_out_romask_T_1120; // @[RegisterRouter.scala:87:24]
wire out_womask_1120 = &_out_womask_T_1120; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1120 = out_rivalid_1_974 & out_rimask_1120; // @[RegisterRouter.scala:87:24]
wire _out_T_10821 = out_f_rivalid_1120; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1120 = out_roready_1_974 & out_romask_1120; // @[RegisterRouter.scala:87:24]
wire _out_T_10822 = out_f_roready_1120; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1120 = out_wivalid_1_974 & out_wimask_1120; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1120 = out_woready_1_974 & out_womask_1120; // @[RegisterRouter.scala:87:24]
wire _out_T_10823 = ~out_rimask_1120; // @[RegisterRouter.scala:87:24]
wire _out_T_10824 = ~out_wimask_1120; // @[RegisterRouter.scala:87:24]
wire _out_T_10825 = ~out_romask_1120; // @[RegisterRouter.scala:87:24]
wire _out_T_10826 = ~out_womask_1120; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_960 = {hi_468, flags_0_go, _out_prepend_T_960}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_10827 = out_prepend_960; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_10828 = _out_T_10827; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_961 = _out_T_10828; // @[RegisterRouter.scala:87:24]
wire out_rimask_1121 = |_out_rimask_T_1121; // @[RegisterRouter.scala:87:24]
wire out_wimask_1121 = &_out_wimask_T_1121; // @[RegisterRouter.scala:87:24]
wire out_romask_1121 = |_out_romask_T_1121; // @[RegisterRouter.scala:87:24]
wire out_womask_1121 = &_out_womask_T_1121; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1121 = out_rivalid_1_975 & out_rimask_1121; // @[RegisterRouter.scala:87:24]
wire _out_T_10830 = out_f_rivalid_1121; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1121 = out_roready_1_975 & out_romask_1121; // @[RegisterRouter.scala:87:24]
wire _out_T_10831 = out_f_roready_1121; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1121 = out_wivalid_1_975 & out_wimask_1121; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1121 = out_woready_1_975 & out_womask_1121; // @[RegisterRouter.scala:87:24]
wire _out_T_10832 = ~out_rimask_1121; // @[RegisterRouter.scala:87:24]
wire _out_T_10833 = ~out_wimask_1121; // @[RegisterRouter.scala:87:24]
wire _out_T_10834 = ~out_romask_1121; // @[RegisterRouter.scala:87:24]
wire _out_T_10835 = ~out_womask_1121; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_961 = {hi_469, flags_0_go, _out_prepend_T_961}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_10836 = out_prepend_961; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_10837 = _out_T_10836; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_962 = _out_T_10837; // @[RegisterRouter.scala:87:24]
wire out_rimask_1122 = |_out_rimask_T_1122; // @[RegisterRouter.scala:87:24]
wire out_wimask_1122 = &_out_wimask_T_1122; // @[RegisterRouter.scala:87:24]
wire out_romask_1122 = |_out_romask_T_1122; // @[RegisterRouter.scala:87:24]
wire out_womask_1122 = &_out_womask_T_1122; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1122 = out_rivalid_1_976 & out_rimask_1122; // @[RegisterRouter.scala:87:24]
wire _out_T_10839 = out_f_rivalid_1122; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1122 = out_roready_1_976 & out_romask_1122; // @[RegisterRouter.scala:87:24]
wire _out_T_10840 = out_f_roready_1122; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1122 = out_wivalid_1_976 & out_wimask_1122; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1122 = out_woready_1_976 & out_womask_1122; // @[RegisterRouter.scala:87:24]
wire _out_T_10841 = ~out_rimask_1122; // @[RegisterRouter.scala:87:24]
wire _out_T_10842 = ~out_wimask_1122; // @[RegisterRouter.scala:87:24]
wire _out_T_10843 = ~out_romask_1122; // @[RegisterRouter.scala:87:24]
wire _out_T_10844 = ~out_womask_1122; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_962 = {hi_470, flags_0_go, _out_prepend_T_962}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_10845 = out_prepend_962; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_10846 = _out_T_10845; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_963 = _out_T_10846; // @[RegisterRouter.scala:87:24]
wire out_rimask_1123 = |_out_rimask_T_1123; // @[RegisterRouter.scala:87:24]
wire out_wimask_1123 = &_out_wimask_T_1123; // @[RegisterRouter.scala:87:24]
wire out_romask_1123 = |_out_romask_T_1123; // @[RegisterRouter.scala:87:24]
wire out_womask_1123 = &_out_womask_T_1123; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1123 = out_rivalid_1_977 & out_rimask_1123; // @[RegisterRouter.scala:87:24]
wire _out_T_10848 = out_f_rivalid_1123; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1123 = out_roready_1_977 & out_romask_1123; // @[RegisterRouter.scala:87:24]
wire _out_T_10849 = out_f_roready_1123; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1123 = out_wivalid_1_977 & out_wimask_1123; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1123 = out_woready_1_977 & out_womask_1123; // @[RegisterRouter.scala:87:24]
wire _out_T_10850 = ~out_rimask_1123; // @[RegisterRouter.scala:87:24]
wire _out_T_10851 = ~out_wimask_1123; // @[RegisterRouter.scala:87:24]
wire _out_T_10852 = ~out_romask_1123; // @[RegisterRouter.scala:87:24]
wire _out_T_10853 = ~out_womask_1123; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_963 = {hi_471, flags_0_go, _out_prepend_T_963}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_10854 = out_prepend_963; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_10855 = _out_T_10854; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_964 = _out_T_10855; // @[RegisterRouter.scala:87:24]
wire out_rimask_1124 = |_out_rimask_T_1124; // @[RegisterRouter.scala:87:24]
wire out_wimask_1124 = &_out_wimask_T_1124; // @[RegisterRouter.scala:87:24]
wire out_romask_1124 = |_out_romask_T_1124; // @[RegisterRouter.scala:87:24]
wire out_womask_1124 = &_out_womask_T_1124; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1124 = out_rivalid_1_978 & out_rimask_1124; // @[RegisterRouter.scala:87:24]
wire _out_T_10857 = out_f_rivalid_1124; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1124 = out_roready_1_978 & out_romask_1124; // @[RegisterRouter.scala:87:24]
wire _out_T_10858 = out_f_roready_1124; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1124 = out_wivalid_1_978 & out_wimask_1124; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1124 = out_woready_1_978 & out_womask_1124; // @[RegisterRouter.scala:87:24]
wire _out_T_10859 = ~out_rimask_1124; // @[RegisterRouter.scala:87:24]
wire _out_T_10860 = ~out_wimask_1124; // @[RegisterRouter.scala:87:24]
wire _out_T_10861 = ~out_romask_1124; // @[RegisterRouter.scala:87:24]
wire _out_T_10862 = ~out_womask_1124; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_964 = {hi_472, flags_0_go, _out_prepend_T_964}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_10863 = out_prepend_964; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_10864 = _out_T_10863; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_186 = _out_T_10864; // @[MuxLiteral.scala:49:48]
wire out_rimask_1125 = |_out_rimask_T_1125; // @[RegisterRouter.scala:87:24]
wire out_wimask_1125 = &_out_wimask_T_1125; // @[RegisterRouter.scala:87:24]
wire out_romask_1125 = |_out_romask_T_1125; // @[RegisterRouter.scala:87:24]
wire out_womask_1125 = &_out_womask_T_1125; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1125 = out_rivalid_1_979 & out_rimask_1125; // @[RegisterRouter.scala:87:24]
wire _out_T_10866 = out_f_rivalid_1125; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1125 = out_roready_1_979 & out_romask_1125; // @[RegisterRouter.scala:87:24]
wire _out_T_10867 = out_f_roready_1125; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1125 = out_wivalid_1_979 & out_wimask_1125; // @[RegisterRouter.scala:87:24]
wire _out_T_10868 = out_f_wivalid_1125; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1125 = out_woready_1_979 & out_womask_1125; // @[RegisterRouter.scala:87:24]
wire _out_T_10869 = out_f_woready_1125; // @[RegisterRouter.scala:87:24]
wire _out_T_10870 = ~out_rimask_1125; // @[RegisterRouter.scala:87:24]
wire _out_T_10871 = ~out_wimask_1125; // @[RegisterRouter.scala:87:24]
wire _out_T_10872 = ~out_romask_1125; // @[RegisterRouter.scala:87:24]
wire _out_T_10873 = ~out_womask_1125; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10875 = _out_T_10874; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_965 = _out_T_10875; // @[RegisterRouter.scala:87:24]
wire out_rimask_1126 = |_out_rimask_T_1126; // @[RegisterRouter.scala:87:24]
wire out_wimask_1126 = &_out_wimask_T_1126; // @[RegisterRouter.scala:87:24]
wire out_romask_1126 = |_out_romask_T_1126; // @[RegisterRouter.scala:87:24]
wire out_womask_1126 = &_out_womask_T_1126; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1126 = out_rivalid_1_980 & out_rimask_1126; // @[RegisterRouter.scala:87:24]
wire _out_T_10877 = out_f_rivalid_1126; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1126 = out_roready_1_980 & out_romask_1126; // @[RegisterRouter.scala:87:24]
wire _out_T_10878 = out_f_roready_1126; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1126 = out_wivalid_1_980 & out_wimask_1126; // @[RegisterRouter.scala:87:24]
wire _out_T_10879 = out_f_wivalid_1126; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1126 = out_woready_1_980 & out_womask_1126; // @[RegisterRouter.scala:87:24]
wire _out_T_10880 = out_f_woready_1126; // @[RegisterRouter.scala:87:24]
wire _out_T_10881 = ~out_rimask_1126; // @[RegisterRouter.scala:87:24]
wire _out_T_10882 = ~out_wimask_1126; // @[RegisterRouter.scala:87:24]
wire _out_T_10883 = ~out_romask_1126; // @[RegisterRouter.scala:87:24]
wire _out_T_10884 = ~out_womask_1126; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_965 = {abstractDataMem_17, _out_prepend_T_965}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_10885 = out_prepend_965; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_10886 = _out_T_10885; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_966 = _out_T_10886; // @[RegisterRouter.scala:87:24]
wire out_rimask_1127 = |_out_rimask_T_1127; // @[RegisterRouter.scala:87:24]
wire out_wimask_1127 = &_out_wimask_T_1127; // @[RegisterRouter.scala:87:24]
wire out_romask_1127 = |_out_romask_T_1127; // @[RegisterRouter.scala:87:24]
wire out_womask_1127 = &_out_womask_T_1127; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1127 = out_rivalid_1_981 & out_rimask_1127; // @[RegisterRouter.scala:87:24]
wire _out_T_10888 = out_f_rivalid_1127; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1127 = out_roready_1_981 & out_romask_1127; // @[RegisterRouter.scala:87:24]
wire _out_T_10889 = out_f_roready_1127; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1127 = out_wivalid_1_981 & out_wimask_1127; // @[RegisterRouter.scala:87:24]
wire _out_T_10890 = out_f_wivalid_1127; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1127 = out_woready_1_981 & out_womask_1127; // @[RegisterRouter.scala:87:24]
wire _out_T_10891 = out_f_woready_1127; // @[RegisterRouter.scala:87:24]
wire _out_T_10892 = ~out_rimask_1127; // @[RegisterRouter.scala:87:24]
wire _out_T_10893 = ~out_wimask_1127; // @[RegisterRouter.scala:87:24]
wire _out_T_10894 = ~out_romask_1127; // @[RegisterRouter.scala:87:24]
wire _out_T_10895 = ~out_womask_1127; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_966 = {abstractDataMem_18, _out_prepend_T_966}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_10896 = out_prepend_966; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_10897 = _out_T_10896; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_967 = _out_T_10897; // @[RegisterRouter.scala:87:24]
wire out_rimask_1128 = |_out_rimask_T_1128; // @[RegisterRouter.scala:87:24]
wire out_wimask_1128 = &_out_wimask_T_1128; // @[RegisterRouter.scala:87:24]
wire out_romask_1128 = |_out_romask_T_1128; // @[RegisterRouter.scala:87:24]
wire out_womask_1128 = &_out_womask_T_1128; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1128 = out_rivalid_1_982 & out_rimask_1128; // @[RegisterRouter.scala:87:24]
wire _out_T_10899 = out_f_rivalid_1128; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1128 = out_roready_1_982 & out_romask_1128; // @[RegisterRouter.scala:87:24]
wire _out_T_10900 = out_f_roready_1128; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1128 = out_wivalid_1_982 & out_wimask_1128; // @[RegisterRouter.scala:87:24]
wire _out_T_10901 = out_f_wivalid_1128; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1128 = out_woready_1_982 & out_womask_1128; // @[RegisterRouter.scala:87:24]
wire _out_T_10902 = out_f_woready_1128; // @[RegisterRouter.scala:87:24]
wire _out_T_10903 = ~out_rimask_1128; // @[RegisterRouter.scala:87:24]
wire _out_T_10904 = ~out_wimask_1128; // @[RegisterRouter.scala:87:24]
wire _out_T_10905 = ~out_romask_1128; // @[RegisterRouter.scala:87:24]
wire _out_T_10906 = ~out_womask_1128; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_967 = {abstractDataMem_19, _out_prepend_T_967}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_10907 = out_prepend_967; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_10908 = _out_T_10907; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_968 = _out_T_10908; // @[RegisterRouter.scala:87:24]
wire out_rimask_1129 = |_out_rimask_T_1129; // @[RegisterRouter.scala:87:24]
wire out_wimask_1129 = &_out_wimask_T_1129; // @[RegisterRouter.scala:87:24]
wire out_romask_1129 = |_out_romask_T_1129; // @[RegisterRouter.scala:87:24]
wire out_womask_1129 = &_out_womask_T_1129; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1129 = out_rivalid_1_983 & out_rimask_1129; // @[RegisterRouter.scala:87:24]
wire _out_T_10910 = out_f_rivalid_1129; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1129 = out_roready_1_983 & out_romask_1129; // @[RegisterRouter.scala:87:24]
wire _out_T_10911 = out_f_roready_1129; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1129 = out_wivalid_1_983 & out_wimask_1129; // @[RegisterRouter.scala:87:24]
wire _out_T_10912 = out_f_wivalid_1129; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1129 = out_woready_1_983 & out_womask_1129; // @[RegisterRouter.scala:87:24]
wire _out_T_10913 = out_f_woready_1129; // @[RegisterRouter.scala:87:24]
wire _out_T_10914 = ~out_rimask_1129; // @[RegisterRouter.scala:87:24]
wire _out_T_10915 = ~out_wimask_1129; // @[RegisterRouter.scala:87:24]
wire _out_T_10916 = ~out_romask_1129; // @[RegisterRouter.scala:87:24]
wire _out_T_10917 = ~out_womask_1129; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_968 = {abstractDataMem_20, _out_prepend_T_968}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_10918 = out_prepend_968; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_10919 = _out_T_10918; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_969 = _out_T_10919; // @[RegisterRouter.scala:87:24]
wire out_rimask_1130 = |_out_rimask_T_1130; // @[RegisterRouter.scala:87:24]
wire out_wimask_1130 = &_out_wimask_T_1130; // @[RegisterRouter.scala:87:24]
wire out_romask_1130 = |_out_romask_T_1130; // @[RegisterRouter.scala:87:24]
wire out_womask_1130 = &_out_womask_T_1130; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1130 = out_rivalid_1_984 & out_rimask_1130; // @[RegisterRouter.scala:87:24]
wire _out_T_10921 = out_f_rivalid_1130; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1130 = out_roready_1_984 & out_romask_1130; // @[RegisterRouter.scala:87:24]
wire _out_T_10922 = out_f_roready_1130; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1130 = out_wivalid_1_984 & out_wimask_1130; // @[RegisterRouter.scala:87:24]
wire _out_T_10923 = out_f_wivalid_1130; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1130 = out_woready_1_984 & out_womask_1130; // @[RegisterRouter.scala:87:24]
wire _out_T_10924 = out_f_woready_1130; // @[RegisterRouter.scala:87:24]
wire _out_T_10925 = ~out_rimask_1130; // @[RegisterRouter.scala:87:24]
wire _out_T_10926 = ~out_wimask_1130; // @[RegisterRouter.scala:87:24]
wire _out_T_10927 = ~out_romask_1130; // @[RegisterRouter.scala:87:24]
wire _out_T_10928 = ~out_womask_1130; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_969 = {abstractDataMem_21, _out_prepend_T_969}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_10929 = out_prepend_969; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_10930 = _out_T_10929; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_970 = _out_T_10930; // @[RegisterRouter.scala:87:24]
wire out_rimask_1131 = |_out_rimask_T_1131; // @[RegisterRouter.scala:87:24]
wire out_wimask_1131 = &_out_wimask_T_1131; // @[RegisterRouter.scala:87:24]
wire out_romask_1131 = |_out_romask_T_1131; // @[RegisterRouter.scala:87:24]
wire out_womask_1131 = &_out_womask_T_1131; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1131 = out_rivalid_1_985 & out_rimask_1131; // @[RegisterRouter.scala:87:24]
wire _out_T_10932 = out_f_rivalid_1131; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1131 = out_roready_1_985 & out_romask_1131; // @[RegisterRouter.scala:87:24]
wire _out_T_10933 = out_f_roready_1131; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1131 = out_wivalid_1_985 & out_wimask_1131; // @[RegisterRouter.scala:87:24]
wire _out_T_10934 = out_f_wivalid_1131; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1131 = out_woready_1_985 & out_womask_1131; // @[RegisterRouter.scala:87:24]
wire _out_T_10935 = out_f_woready_1131; // @[RegisterRouter.scala:87:24]
wire _out_T_10936 = ~out_rimask_1131; // @[RegisterRouter.scala:87:24]
wire _out_T_10937 = ~out_wimask_1131; // @[RegisterRouter.scala:87:24]
wire _out_T_10938 = ~out_romask_1131; // @[RegisterRouter.scala:87:24]
wire _out_T_10939 = ~out_womask_1131; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_970 = {abstractDataMem_22, _out_prepend_T_970}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_10940 = out_prepend_970; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_10941 = _out_T_10940; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_971 = _out_T_10941; // @[RegisterRouter.scala:87:24]
wire out_rimask_1132 = |_out_rimask_T_1132; // @[RegisterRouter.scala:87:24]
wire out_wimask_1132 = &_out_wimask_T_1132; // @[RegisterRouter.scala:87:24]
wire out_romask_1132 = |_out_romask_T_1132; // @[RegisterRouter.scala:87:24]
wire out_womask_1132 = &_out_womask_T_1132; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1132 = out_rivalid_1_986 & out_rimask_1132; // @[RegisterRouter.scala:87:24]
wire _out_T_10943 = out_f_rivalid_1132; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1132 = out_roready_1_986 & out_romask_1132; // @[RegisterRouter.scala:87:24]
wire _out_T_10944 = out_f_roready_1132; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1132 = out_wivalid_1_986 & out_wimask_1132; // @[RegisterRouter.scala:87:24]
wire _out_T_10945 = out_f_wivalid_1132; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1132 = out_woready_1_986 & out_womask_1132; // @[RegisterRouter.scala:87:24]
wire _out_T_10946 = out_f_woready_1132; // @[RegisterRouter.scala:87:24]
wire _out_T_10947 = ~out_rimask_1132; // @[RegisterRouter.scala:87:24]
wire _out_T_10948 = ~out_wimask_1132; // @[RegisterRouter.scala:87:24]
wire _out_T_10949 = ~out_romask_1132; // @[RegisterRouter.scala:87:24]
wire _out_T_10950 = ~out_womask_1132; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_971 = {abstractDataMem_23, _out_prepend_T_971}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_10951 = out_prepend_971; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_10952 = _out_T_10951; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_114 = _out_T_10952; // @[MuxLiteral.scala:49:48]
wire out_rimask_1133 = |_out_rimask_T_1133; // @[RegisterRouter.scala:87:24]
wire out_wimask_1133 = &_out_wimask_T_1133; // @[RegisterRouter.scala:87:24]
wire out_romask_1133 = |_out_romask_T_1133; // @[RegisterRouter.scala:87:24]
wire out_womask_1133 = &_out_womask_T_1133; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1133 = out_rivalid_1_987 & out_rimask_1133; // @[RegisterRouter.scala:87:24]
wire _out_T_10954 = out_f_rivalid_1133; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1133 = out_roready_1_987 & out_romask_1133; // @[RegisterRouter.scala:87:24]
wire _out_T_10955 = out_f_roready_1133; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1133 = out_wivalid_1_987 & out_wimask_1133; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1133 = out_woready_1_987 & out_womask_1133; // @[RegisterRouter.scala:87:24]
wire _out_T_10956 = ~out_rimask_1133; // @[RegisterRouter.scala:87:24]
wire _out_T_10957 = ~out_wimask_1133; // @[RegisterRouter.scala:87:24]
wire _out_T_10958 = ~out_romask_1133; // @[RegisterRouter.scala:87:24]
wire _out_T_10959 = ~out_womask_1133; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_10961 = _out_T_10960; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_972 = _out_T_10961; // @[RegisterRouter.scala:87:24]
wire out_rimask_1134 = |_out_rimask_T_1134; // @[RegisterRouter.scala:87:24]
wire out_wimask_1134 = &_out_wimask_T_1134; // @[RegisterRouter.scala:87:24]
wire out_romask_1134 = |_out_romask_T_1134; // @[RegisterRouter.scala:87:24]
wire out_womask_1134 = &_out_womask_T_1134; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1134 = out_rivalid_1_988 & out_rimask_1134; // @[RegisterRouter.scala:87:24]
wire _out_T_10963 = out_f_rivalid_1134; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1134 = out_roready_1_988 & out_romask_1134; // @[RegisterRouter.scala:87:24]
wire _out_T_10964 = out_f_roready_1134; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1134 = out_wivalid_1_988 & out_wimask_1134; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1134 = out_woready_1_988 & out_womask_1134; // @[RegisterRouter.scala:87:24]
wire _out_T_10965 = ~out_rimask_1134; // @[RegisterRouter.scala:87:24]
wire _out_T_10966 = ~out_wimask_1134; // @[RegisterRouter.scala:87:24]
wire _out_T_10967 = ~out_romask_1134; // @[RegisterRouter.scala:87:24]
wire _out_T_10968 = ~out_womask_1134; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_972 = {hi_346, flags_0_go, _out_prepend_T_972}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_10969 = out_prepend_972; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_10970 = _out_T_10969; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_973 = _out_T_10970; // @[RegisterRouter.scala:87:24]
wire out_rimask_1135 = |_out_rimask_T_1135; // @[RegisterRouter.scala:87:24]
wire out_wimask_1135 = &_out_wimask_T_1135; // @[RegisterRouter.scala:87:24]
wire out_romask_1135 = |_out_romask_T_1135; // @[RegisterRouter.scala:87:24]
wire out_womask_1135 = &_out_womask_T_1135; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1135 = out_rivalid_1_989 & out_rimask_1135; // @[RegisterRouter.scala:87:24]
wire _out_T_10972 = out_f_rivalid_1135; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1135 = out_roready_1_989 & out_romask_1135; // @[RegisterRouter.scala:87:24]
wire _out_T_10973 = out_f_roready_1135; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1135 = out_wivalid_1_989 & out_wimask_1135; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1135 = out_woready_1_989 & out_womask_1135; // @[RegisterRouter.scala:87:24]
wire _out_T_10974 = ~out_rimask_1135; // @[RegisterRouter.scala:87:24]
wire _out_T_10975 = ~out_wimask_1135; // @[RegisterRouter.scala:87:24]
wire _out_T_10976 = ~out_romask_1135; // @[RegisterRouter.scala:87:24]
wire _out_T_10977 = ~out_womask_1135; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_973 = {hi_347, flags_0_go, _out_prepend_T_973}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_10978 = out_prepend_973; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_10979 = _out_T_10978; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_974 = _out_T_10979; // @[RegisterRouter.scala:87:24]
wire out_rimask_1136 = |_out_rimask_T_1136; // @[RegisterRouter.scala:87:24]
wire out_wimask_1136 = &_out_wimask_T_1136; // @[RegisterRouter.scala:87:24]
wire out_romask_1136 = |_out_romask_T_1136; // @[RegisterRouter.scala:87:24]
wire out_womask_1136 = &_out_womask_T_1136; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1136 = out_rivalid_1_990 & out_rimask_1136; // @[RegisterRouter.scala:87:24]
wire _out_T_10981 = out_f_rivalid_1136; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1136 = out_roready_1_990 & out_romask_1136; // @[RegisterRouter.scala:87:24]
wire _out_T_10982 = out_f_roready_1136; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1136 = out_wivalid_1_990 & out_wimask_1136; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1136 = out_woready_1_990 & out_womask_1136; // @[RegisterRouter.scala:87:24]
wire _out_T_10983 = ~out_rimask_1136; // @[RegisterRouter.scala:87:24]
wire _out_T_10984 = ~out_wimask_1136; // @[RegisterRouter.scala:87:24]
wire _out_T_10985 = ~out_romask_1136; // @[RegisterRouter.scala:87:24]
wire _out_T_10986 = ~out_womask_1136; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_974 = {hi_348, flags_0_go, _out_prepend_T_974}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_10987 = out_prepend_974; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_10988 = _out_T_10987; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_975 = _out_T_10988; // @[RegisterRouter.scala:87:24]
wire out_rimask_1137 = |_out_rimask_T_1137; // @[RegisterRouter.scala:87:24]
wire out_wimask_1137 = &_out_wimask_T_1137; // @[RegisterRouter.scala:87:24]
wire out_romask_1137 = |_out_romask_T_1137; // @[RegisterRouter.scala:87:24]
wire out_womask_1137 = &_out_womask_T_1137; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1137 = out_rivalid_1_991 & out_rimask_1137; // @[RegisterRouter.scala:87:24]
wire _out_T_10990 = out_f_rivalid_1137; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1137 = out_roready_1_991 & out_romask_1137; // @[RegisterRouter.scala:87:24]
wire _out_T_10991 = out_f_roready_1137; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1137 = out_wivalid_1_991 & out_wimask_1137; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1137 = out_woready_1_991 & out_womask_1137; // @[RegisterRouter.scala:87:24]
wire _out_T_10992 = ~out_rimask_1137; // @[RegisterRouter.scala:87:24]
wire _out_T_10993 = ~out_wimask_1137; // @[RegisterRouter.scala:87:24]
wire _out_T_10994 = ~out_romask_1137; // @[RegisterRouter.scala:87:24]
wire _out_T_10995 = ~out_womask_1137; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_975 = {hi_349, flags_0_go, _out_prepend_T_975}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_10996 = out_prepend_975; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_10997 = _out_T_10996; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_976 = _out_T_10997; // @[RegisterRouter.scala:87:24]
wire out_rimask_1138 = |_out_rimask_T_1138; // @[RegisterRouter.scala:87:24]
wire out_wimask_1138 = &_out_wimask_T_1138; // @[RegisterRouter.scala:87:24]
wire out_romask_1138 = |_out_romask_T_1138; // @[RegisterRouter.scala:87:24]
wire out_womask_1138 = &_out_womask_T_1138; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1138 = out_rivalid_1_992 & out_rimask_1138; // @[RegisterRouter.scala:87:24]
wire _out_T_10999 = out_f_rivalid_1138; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1138 = out_roready_1_992 & out_romask_1138; // @[RegisterRouter.scala:87:24]
wire _out_T_11000 = out_f_roready_1138; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1138 = out_wivalid_1_992 & out_wimask_1138; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1138 = out_woready_1_992 & out_womask_1138; // @[RegisterRouter.scala:87:24]
wire _out_T_11001 = ~out_rimask_1138; // @[RegisterRouter.scala:87:24]
wire _out_T_11002 = ~out_wimask_1138; // @[RegisterRouter.scala:87:24]
wire _out_T_11003 = ~out_romask_1138; // @[RegisterRouter.scala:87:24]
wire _out_T_11004 = ~out_womask_1138; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_976 = {hi_350, flags_0_go, _out_prepend_T_976}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_11005 = out_prepend_976; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_11006 = _out_T_11005; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_977 = _out_T_11006; // @[RegisterRouter.scala:87:24]
wire out_rimask_1139 = |_out_rimask_T_1139; // @[RegisterRouter.scala:87:24]
wire out_wimask_1139 = &_out_wimask_T_1139; // @[RegisterRouter.scala:87:24]
wire out_romask_1139 = |_out_romask_T_1139; // @[RegisterRouter.scala:87:24]
wire out_womask_1139 = &_out_womask_T_1139; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1139 = out_rivalid_1_993 & out_rimask_1139; // @[RegisterRouter.scala:87:24]
wire _out_T_11008 = out_f_rivalid_1139; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1139 = out_roready_1_993 & out_romask_1139; // @[RegisterRouter.scala:87:24]
wire _out_T_11009 = out_f_roready_1139; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1139 = out_wivalid_1_993 & out_wimask_1139; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1139 = out_woready_1_993 & out_womask_1139; // @[RegisterRouter.scala:87:24]
wire _out_T_11010 = ~out_rimask_1139; // @[RegisterRouter.scala:87:24]
wire _out_T_11011 = ~out_wimask_1139; // @[RegisterRouter.scala:87:24]
wire _out_T_11012 = ~out_romask_1139; // @[RegisterRouter.scala:87:24]
wire _out_T_11013 = ~out_womask_1139; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_977 = {hi_351, flags_0_go, _out_prepend_T_977}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_11014 = out_prepend_977; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_11015 = _out_T_11014; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_978 = _out_T_11015; // @[RegisterRouter.scala:87:24]
wire out_rimask_1140 = |_out_rimask_T_1140; // @[RegisterRouter.scala:87:24]
wire out_wimask_1140 = &_out_wimask_T_1140; // @[RegisterRouter.scala:87:24]
wire out_romask_1140 = |_out_romask_T_1140; // @[RegisterRouter.scala:87:24]
wire out_womask_1140 = &_out_womask_T_1140; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1140 = out_rivalid_1_994 & out_rimask_1140; // @[RegisterRouter.scala:87:24]
wire _out_T_11017 = out_f_rivalid_1140; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1140 = out_roready_1_994 & out_romask_1140; // @[RegisterRouter.scala:87:24]
wire _out_T_11018 = out_f_roready_1140; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1140 = out_wivalid_1_994 & out_wimask_1140; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1140 = out_woready_1_994 & out_womask_1140; // @[RegisterRouter.scala:87:24]
wire _out_T_11019 = ~out_rimask_1140; // @[RegisterRouter.scala:87:24]
wire _out_T_11020 = ~out_wimask_1140; // @[RegisterRouter.scala:87:24]
wire _out_T_11021 = ~out_romask_1140; // @[RegisterRouter.scala:87:24]
wire _out_T_11022 = ~out_womask_1140; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_978 = {hi_352, flags_0_go, _out_prepend_T_978}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_11023 = out_prepend_978; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_11024 = _out_T_11023; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_171 = _out_T_11024; // @[MuxLiteral.scala:49:48]
wire out_rimask_1141 = |_out_rimask_T_1141; // @[RegisterRouter.scala:87:24]
wire out_wimask_1141 = &_out_wimask_T_1141; // @[RegisterRouter.scala:87:24]
wire out_romask_1141 = |_out_romask_T_1141; // @[RegisterRouter.scala:87:24]
wire out_womask_1141 = &_out_womask_T_1141; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1141 = out_rivalid_1_995 & out_rimask_1141; // @[RegisterRouter.scala:87:24]
wire _out_T_11026 = out_f_rivalid_1141; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1141 = out_roready_1_995 & out_romask_1141; // @[RegisterRouter.scala:87:24]
wire _out_T_11027 = out_f_roready_1141; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1141 = out_wivalid_1_995 & out_wimask_1141; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1141 = out_woready_1_995 & out_womask_1141; // @[RegisterRouter.scala:87:24]
wire _out_T_11028 = ~out_rimask_1141; // @[RegisterRouter.scala:87:24]
wire _out_T_11029 = ~out_wimask_1141; // @[RegisterRouter.scala:87:24]
wire _out_T_11030 = ~out_romask_1141; // @[RegisterRouter.scala:87:24]
wire _out_T_11031 = ~out_womask_1141; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11033 = _out_T_11032; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_979 = _out_T_11033; // @[RegisterRouter.scala:87:24]
wire out_rimask_1142 = |_out_rimask_T_1142; // @[RegisterRouter.scala:87:24]
wire out_wimask_1142 = &_out_wimask_T_1142; // @[RegisterRouter.scala:87:24]
wire out_romask_1142 = |_out_romask_T_1142; // @[RegisterRouter.scala:87:24]
wire out_womask_1142 = &_out_womask_T_1142; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1142 = out_rivalid_1_996 & out_rimask_1142; // @[RegisterRouter.scala:87:24]
wire _out_T_11035 = out_f_rivalid_1142; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1142 = out_roready_1_996 & out_romask_1142; // @[RegisterRouter.scala:87:24]
wire _out_T_11036 = out_f_roready_1142; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1142 = out_wivalid_1_996 & out_wimask_1142; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1142 = out_woready_1_996 & out_womask_1142; // @[RegisterRouter.scala:87:24]
wire _out_T_11037 = ~out_rimask_1142; // @[RegisterRouter.scala:87:24]
wire _out_T_11038 = ~out_wimask_1142; // @[RegisterRouter.scala:87:24]
wire _out_T_11039 = ~out_romask_1142; // @[RegisterRouter.scala:87:24]
wire _out_T_11040 = ~out_womask_1142; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_979 = {hi_90, flags_0_go, _out_prepend_T_979}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_11041 = out_prepend_979; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_11042 = _out_T_11041; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_980 = _out_T_11042; // @[RegisterRouter.scala:87:24]
wire out_rimask_1143 = |_out_rimask_T_1143; // @[RegisterRouter.scala:87:24]
wire out_wimask_1143 = &_out_wimask_T_1143; // @[RegisterRouter.scala:87:24]
wire out_romask_1143 = |_out_romask_T_1143; // @[RegisterRouter.scala:87:24]
wire out_womask_1143 = &_out_womask_T_1143; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1143 = out_rivalid_1_997 & out_rimask_1143; // @[RegisterRouter.scala:87:24]
wire _out_T_11044 = out_f_rivalid_1143; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1143 = out_roready_1_997 & out_romask_1143; // @[RegisterRouter.scala:87:24]
wire _out_T_11045 = out_f_roready_1143; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1143 = out_wivalid_1_997 & out_wimask_1143; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1143 = out_woready_1_997 & out_womask_1143; // @[RegisterRouter.scala:87:24]
wire _out_T_11046 = ~out_rimask_1143; // @[RegisterRouter.scala:87:24]
wire _out_T_11047 = ~out_wimask_1143; // @[RegisterRouter.scala:87:24]
wire _out_T_11048 = ~out_romask_1143; // @[RegisterRouter.scala:87:24]
wire _out_T_11049 = ~out_womask_1143; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_980 = {hi_91, flags_0_go, _out_prepend_T_980}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_11050 = out_prepend_980; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_11051 = _out_T_11050; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_981 = _out_T_11051; // @[RegisterRouter.scala:87:24]
wire out_rimask_1144 = |_out_rimask_T_1144; // @[RegisterRouter.scala:87:24]
wire out_wimask_1144 = &_out_wimask_T_1144; // @[RegisterRouter.scala:87:24]
wire out_romask_1144 = |_out_romask_T_1144; // @[RegisterRouter.scala:87:24]
wire out_womask_1144 = &_out_womask_T_1144; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1144 = out_rivalid_1_998 & out_rimask_1144; // @[RegisterRouter.scala:87:24]
wire _out_T_11053 = out_f_rivalid_1144; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1144 = out_roready_1_998 & out_romask_1144; // @[RegisterRouter.scala:87:24]
wire _out_T_11054 = out_f_roready_1144; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1144 = out_wivalid_1_998 & out_wimask_1144; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1144 = out_woready_1_998 & out_womask_1144; // @[RegisterRouter.scala:87:24]
wire _out_T_11055 = ~out_rimask_1144; // @[RegisterRouter.scala:87:24]
wire _out_T_11056 = ~out_wimask_1144; // @[RegisterRouter.scala:87:24]
wire _out_T_11057 = ~out_romask_1144; // @[RegisterRouter.scala:87:24]
wire _out_T_11058 = ~out_womask_1144; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_981 = {hi_92, flags_0_go, _out_prepend_T_981}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_11059 = out_prepend_981; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_11060 = _out_T_11059; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_982 = _out_T_11060; // @[RegisterRouter.scala:87:24]
wire out_rimask_1145 = |_out_rimask_T_1145; // @[RegisterRouter.scala:87:24]
wire out_wimask_1145 = &_out_wimask_T_1145; // @[RegisterRouter.scala:87:24]
wire out_romask_1145 = |_out_romask_T_1145; // @[RegisterRouter.scala:87:24]
wire out_womask_1145 = &_out_womask_T_1145; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1145 = out_rivalid_1_999 & out_rimask_1145; // @[RegisterRouter.scala:87:24]
wire _out_T_11062 = out_f_rivalid_1145; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1145 = out_roready_1_999 & out_romask_1145; // @[RegisterRouter.scala:87:24]
wire _out_T_11063 = out_f_roready_1145; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1145 = out_wivalid_1_999 & out_wimask_1145; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1145 = out_woready_1_999 & out_womask_1145; // @[RegisterRouter.scala:87:24]
wire _out_T_11064 = ~out_rimask_1145; // @[RegisterRouter.scala:87:24]
wire _out_T_11065 = ~out_wimask_1145; // @[RegisterRouter.scala:87:24]
wire _out_T_11066 = ~out_romask_1145; // @[RegisterRouter.scala:87:24]
wire _out_T_11067 = ~out_womask_1145; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_982 = {hi_93, flags_0_go, _out_prepend_T_982}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_11068 = out_prepend_982; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_11069 = _out_T_11068; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_983 = _out_T_11069; // @[RegisterRouter.scala:87:24]
wire out_rimask_1146 = |_out_rimask_T_1146; // @[RegisterRouter.scala:87:24]
wire out_wimask_1146 = &_out_wimask_T_1146; // @[RegisterRouter.scala:87:24]
wire out_romask_1146 = |_out_romask_T_1146; // @[RegisterRouter.scala:87:24]
wire out_womask_1146 = &_out_womask_T_1146; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1146 = out_rivalid_1_1000 & out_rimask_1146; // @[RegisterRouter.scala:87:24]
wire _out_T_11071 = out_f_rivalid_1146; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1146 = out_roready_1_1000 & out_romask_1146; // @[RegisterRouter.scala:87:24]
wire _out_T_11072 = out_f_roready_1146; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1146 = out_wivalid_1_1000 & out_wimask_1146; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1146 = out_woready_1_1000 & out_womask_1146; // @[RegisterRouter.scala:87:24]
wire _out_T_11073 = ~out_rimask_1146; // @[RegisterRouter.scala:87:24]
wire _out_T_11074 = ~out_wimask_1146; // @[RegisterRouter.scala:87:24]
wire _out_T_11075 = ~out_romask_1146; // @[RegisterRouter.scala:87:24]
wire _out_T_11076 = ~out_womask_1146; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_983 = {hi_94, flags_0_go, _out_prepend_T_983}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_11077 = out_prepend_983; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_11078 = _out_T_11077; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_984 = _out_T_11078; // @[RegisterRouter.scala:87:24]
wire out_rimask_1147 = |_out_rimask_T_1147; // @[RegisterRouter.scala:87:24]
wire out_wimask_1147 = &_out_wimask_T_1147; // @[RegisterRouter.scala:87:24]
wire out_romask_1147 = |_out_romask_T_1147; // @[RegisterRouter.scala:87:24]
wire out_womask_1147 = &_out_womask_T_1147; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1147 = out_rivalid_1_1001 & out_rimask_1147; // @[RegisterRouter.scala:87:24]
wire _out_T_11080 = out_f_rivalid_1147; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1147 = out_roready_1_1001 & out_romask_1147; // @[RegisterRouter.scala:87:24]
wire _out_T_11081 = out_f_roready_1147; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1147 = out_wivalid_1_1001 & out_wimask_1147; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1147 = out_woready_1_1001 & out_womask_1147; // @[RegisterRouter.scala:87:24]
wire _out_T_11082 = ~out_rimask_1147; // @[RegisterRouter.scala:87:24]
wire _out_T_11083 = ~out_wimask_1147; // @[RegisterRouter.scala:87:24]
wire _out_T_11084 = ~out_romask_1147; // @[RegisterRouter.scala:87:24]
wire _out_T_11085 = ~out_womask_1147; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_984 = {hi_95, flags_0_go, _out_prepend_T_984}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_11086 = out_prepend_984; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_11087 = _out_T_11086; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_985 = _out_T_11087; // @[RegisterRouter.scala:87:24]
wire out_rimask_1148 = |_out_rimask_T_1148; // @[RegisterRouter.scala:87:24]
wire out_wimask_1148 = &_out_wimask_T_1148; // @[RegisterRouter.scala:87:24]
wire out_romask_1148 = |_out_romask_T_1148; // @[RegisterRouter.scala:87:24]
wire out_womask_1148 = &_out_womask_T_1148; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1148 = out_rivalid_1_1002 & out_rimask_1148; // @[RegisterRouter.scala:87:24]
wire _out_T_11089 = out_f_rivalid_1148; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1148 = out_roready_1_1002 & out_romask_1148; // @[RegisterRouter.scala:87:24]
wire _out_T_11090 = out_f_roready_1148; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1148 = out_wivalid_1_1002 & out_wimask_1148; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1148 = out_woready_1_1002 & out_womask_1148; // @[RegisterRouter.scala:87:24]
wire _out_T_11091 = ~out_rimask_1148; // @[RegisterRouter.scala:87:24]
wire _out_T_11092 = ~out_wimask_1148; // @[RegisterRouter.scala:87:24]
wire _out_T_11093 = ~out_romask_1148; // @[RegisterRouter.scala:87:24]
wire _out_T_11094 = ~out_womask_1148; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_985 = {hi_96, flags_0_go, _out_prepend_T_985}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_11095 = out_prepend_985; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_11096 = _out_T_11095; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_139 = _out_T_11096; // @[MuxLiteral.scala:49:48]
wire out_rimask_1149 = |_out_rimask_T_1149; // @[RegisterRouter.scala:87:24]
wire out_wimask_1149 = &_out_wimask_T_1149; // @[RegisterRouter.scala:87:24]
wire out_romask_1149 = |_out_romask_T_1149; // @[RegisterRouter.scala:87:24]
wire out_womask_1149 = &_out_womask_T_1149; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1149 = out_rivalid_1_1003 & out_rimask_1149; // @[RegisterRouter.scala:87:24]
wire _out_T_11098 = out_f_rivalid_1149; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1149 = out_roready_1_1003 & out_romask_1149; // @[RegisterRouter.scala:87:24]
wire _out_T_11099 = out_f_roready_1149; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1149 = out_wivalid_1_1003 & out_wimask_1149; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1149 = out_woready_1_1003 & out_womask_1149; // @[RegisterRouter.scala:87:24]
wire _out_T_11100 = ~out_rimask_1149; // @[RegisterRouter.scala:87:24]
wire _out_T_11101 = ~out_wimask_1149; // @[RegisterRouter.scala:87:24]
wire _out_T_11102 = ~out_romask_1149; // @[RegisterRouter.scala:87:24]
wire _out_T_11103 = ~out_womask_1149; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11105 = _out_T_11104; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_986 = _out_T_11105; // @[RegisterRouter.scala:87:24]
wire out_rimask_1150 = |_out_rimask_T_1150; // @[RegisterRouter.scala:87:24]
wire out_wimask_1150 = &_out_wimask_T_1150; // @[RegisterRouter.scala:87:24]
wire out_romask_1150 = |_out_romask_T_1150; // @[RegisterRouter.scala:87:24]
wire out_womask_1150 = &_out_womask_T_1150; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1150 = out_rivalid_1_1004 & out_rimask_1150; // @[RegisterRouter.scala:87:24]
wire _out_T_11107 = out_f_rivalid_1150; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1150 = out_roready_1_1004 & out_romask_1150; // @[RegisterRouter.scala:87:24]
wire _out_T_11108 = out_f_roready_1150; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1150 = out_wivalid_1_1004 & out_wimask_1150; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1150 = out_woready_1_1004 & out_womask_1150; // @[RegisterRouter.scala:87:24]
wire _out_T_11109 = ~out_rimask_1150; // @[RegisterRouter.scala:87:24]
wire _out_T_11110 = ~out_wimask_1150; // @[RegisterRouter.scala:87:24]
wire _out_T_11111 = ~out_romask_1150; // @[RegisterRouter.scala:87:24]
wire _out_T_11112 = ~out_womask_1150; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_986 = {hi_634, flags_0_go, _out_prepend_T_986}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_11113 = out_prepend_986; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_11114 = _out_T_11113; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_987 = _out_T_11114; // @[RegisterRouter.scala:87:24]
wire out_rimask_1151 = |_out_rimask_T_1151; // @[RegisterRouter.scala:87:24]
wire out_wimask_1151 = &_out_wimask_T_1151; // @[RegisterRouter.scala:87:24]
wire out_romask_1151 = |_out_romask_T_1151; // @[RegisterRouter.scala:87:24]
wire out_womask_1151 = &_out_womask_T_1151; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1151 = out_rivalid_1_1005 & out_rimask_1151; // @[RegisterRouter.scala:87:24]
wire _out_T_11116 = out_f_rivalid_1151; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1151 = out_roready_1_1005 & out_romask_1151; // @[RegisterRouter.scala:87:24]
wire _out_T_11117 = out_f_roready_1151; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1151 = out_wivalid_1_1005 & out_wimask_1151; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1151 = out_woready_1_1005 & out_womask_1151; // @[RegisterRouter.scala:87:24]
wire _out_T_11118 = ~out_rimask_1151; // @[RegisterRouter.scala:87:24]
wire _out_T_11119 = ~out_wimask_1151; // @[RegisterRouter.scala:87:24]
wire _out_T_11120 = ~out_romask_1151; // @[RegisterRouter.scala:87:24]
wire _out_T_11121 = ~out_womask_1151; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_987 = {hi_635, flags_0_go, _out_prepend_T_987}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_11122 = out_prepend_987; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_11123 = _out_T_11122; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_988 = _out_T_11123; // @[RegisterRouter.scala:87:24]
wire out_rimask_1152 = |_out_rimask_T_1152; // @[RegisterRouter.scala:87:24]
wire out_wimask_1152 = &_out_wimask_T_1152; // @[RegisterRouter.scala:87:24]
wire out_romask_1152 = |_out_romask_T_1152; // @[RegisterRouter.scala:87:24]
wire out_womask_1152 = &_out_womask_T_1152; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1152 = out_rivalid_1_1006 & out_rimask_1152; // @[RegisterRouter.scala:87:24]
wire _out_T_11125 = out_f_rivalid_1152; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1152 = out_roready_1_1006 & out_romask_1152; // @[RegisterRouter.scala:87:24]
wire _out_T_11126 = out_f_roready_1152; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1152 = out_wivalid_1_1006 & out_wimask_1152; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1152 = out_woready_1_1006 & out_womask_1152; // @[RegisterRouter.scala:87:24]
wire _out_T_11127 = ~out_rimask_1152; // @[RegisterRouter.scala:87:24]
wire _out_T_11128 = ~out_wimask_1152; // @[RegisterRouter.scala:87:24]
wire _out_T_11129 = ~out_romask_1152; // @[RegisterRouter.scala:87:24]
wire _out_T_11130 = ~out_womask_1152; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_988 = {hi_636, flags_0_go, _out_prepend_T_988}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_11131 = out_prepend_988; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_11132 = _out_T_11131; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_989 = _out_T_11132; // @[RegisterRouter.scala:87:24]
wire out_rimask_1153 = |_out_rimask_T_1153; // @[RegisterRouter.scala:87:24]
wire out_wimask_1153 = &_out_wimask_T_1153; // @[RegisterRouter.scala:87:24]
wire out_romask_1153 = |_out_romask_T_1153; // @[RegisterRouter.scala:87:24]
wire out_womask_1153 = &_out_womask_T_1153; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1153 = out_rivalid_1_1007 & out_rimask_1153; // @[RegisterRouter.scala:87:24]
wire _out_T_11134 = out_f_rivalid_1153; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1153 = out_roready_1_1007 & out_romask_1153; // @[RegisterRouter.scala:87:24]
wire _out_T_11135 = out_f_roready_1153; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1153 = out_wivalid_1_1007 & out_wimask_1153; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1153 = out_woready_1_1007 & out_womask_1153; // @[RegisterRouter.scala:87:24]
wire _out_T_11136 = ~out_rimask_1153; // @[RegisterRouter.scala:87:24]
wire _out_T_11137 = ~out_wimask_1153; // @[RegisterRouter.scala:87:24]
wire _out_T_11138 = ~out_romask_1153; // @[RegisterRouter.scala:87:24]
wire _out_T_11139 = ~out_womask_1153; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_989 = {hi_637, flags_0_go, _out_prepend_T_989}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_11140 = out_prepend_989; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_11141 = _out_T_11140; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_990 = _out_T_11141; // @[RegisterRouter.scala:87:24]
wire out_rimask_1154 = |_out_rimask_T_1154; // @[RegisterRouter.scala:87:24]
wire out_wimask_1154 = &_out_wimask_T_1154; // @[RegisterRouter.scala:87:24]
wire out_romask_1154 = |_out_romask_T_1154; // @[RegisterRouter.scala:87:24]
wire out_womask_1154 = &_out_womask_T_1154; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1154 = out_rivalid_1_1008 & out_rimask_1154; // @[RegisterRouter.scala:87:24]
wire _out_T_11143 = out_f_rivalid_1154; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1154 = out_roready_1_1008 & out_romask_1154; // @[RegisterRouter.scala:87:24]
wire _out_T_11144 = out_f_roready_1154; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1154 = out_wivalid_1_1008 & out_wimask_1154; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1154 = out_woready_1_1008 & out_womask_1154; // @[RegisterRouter.scala:87:24]
wire _out_T_11145 = ~out_rimask_1154; // @[RegisterRouter.scala:87:24]
wire _out_T_11146 = ~out_wimask_1154; // @[RegisterRouter.scala:87:24]
wire _out_T_11147 = ~out_romask_1154; // @[RegisterRouter.scala:87:24]
wire _out_T_11148 = ~out_womask_1154; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_990 = {hi_638, flags_0_go, _out_prepend_T_990}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_11149 = out_prepend_990; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_11150 = _out_T_11149; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_991 = _out_T_11150; // @[RegisterRouter.scala:87:24]
wire out_rimask_1155 = |_out_rimask_T_1155; // @[RegisterRouter.scala:87:24]
wire out_wimask_1155 = &_out_wimask_T_1155; // @[RegisterRouter.scala:87:24]
wire out_romask_1155 = |_out_romask_T_1155; // @[RegisterRouter.scala:87:24]
wire out_womask_1155 = &_out_womask_T_1155; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1155 = out_rivalid_1_1009 & out_rimask_1155; // @[RegisterRouter.scala:87:24]
wire _out_T_11152 = out_f_rivalid_1155; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1155 = out_roready_1_1009 & out_romask_1155; // @[RegisterRouter.scala:87:24]
wire _out_T_11153 = out_f_roready_1155; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1155 = out_wivalid_1_1009 & out_wimask_1155; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1155 = out_woready_1_1009 & out_womask_1155; // @[RegisterRouter.scala:87:24]
wire _out_T_11154 = ~out_rimask_1155; // @[RegisterRouter.scala:87:24]
wire _out_T_11155 = ~out_wimask_1155; // @[RegisterRouter.scala:87:24]
wire _out_T_11156 = ~out_romask_1155; // @[RegisterRouter.scala:87:24]
wire _out_T_11157 = ~out_womask_1155; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_991 = {hi_639, flags_0_go, _out_prepend_T_991}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_11158 = out_prepend_991; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_11159 = _out_T_11158; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_992 = _out_T_11159; // @[RegisterRouter.scala:87:24]
wire out_rimask_1156 = |_out_rimask_T_1156; // @[RegisterRouter.scala:87:24]
wire out_wimask_1156 = &_out_wimask_T_1156; // @[RegisterRouter.scala:87:24]
wire out_romask_1156 = |_out_romask_T_1156; // @[RegisterRouter.scala:87:24]
wire out_womask_1156 = &_out_womask_T_1156; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1156 = out_rivalid_1_1010 & out_rimask_1156; // @[RegisterRouter.scala:87:24]
wire _out_T_11161 = out_f_rivalid_1156; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1156 = out_roready_1_1010 & out_romask_1156; // @[RegisterRouter.scala:87:24]
wire _out_T_11162 = out_f_roready_1156; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1156 = out_wivalid_1_1010 & out_wimask_1156; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1156 = out_woready_1_1010 & out_womask_1156; // @[RegisterRouter.scala:87:24]
wire _out_T_11163 = ~out_rimask_1156; // @[RegisterRouter.scala:87:24]
wire _out_T_11164 = ~out_wimask_1156; // @[RegisterRouter.scala:87:24]
wire _out_T_11165 = ~out_romask_1156; // @[RegisterRouter.scala:87:24]
wire _out_T_11166 = ~out_womask_1156; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_992 = {hi_640, flags_0_go, _out_prepend_T_992}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_11167 = out_prepend_992; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_11168 = _out_T_11167; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_207 = _out_T_11168; // @[MuxLiteral.scala:49:48]
wire out_rimask_1157 = |_out_rimask_T_1157; // @[RegisterRouter.scala:87:24]
wire out_wimask_1157 = &_out_wimask_T_1157; // @[RegisterRouter.scala:87:24]
wire out_romask_1157 = |_out_romask_T_1157; // @[RegisterRouter.scala:87:24]
wire out_womask_1157 = &_out_womask_T_1157; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1157 = out_rivalid_1_1011 & out_rimask_1157; // @[RegisterRouter.scala:87:24]
wire _out_T_11170 = out_f_rivalid_1157; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1157 = out_roready_1_1011 & out_romask_1157; // @[RegisterRouter.scala:87:24]
wire _out_T_11171 = out_f_roready_1157; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1157 = out_wivalid_1_1011 & out_wimask_1157; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1157 = out_woready_1_1011 & out_womask_1157; // @[RegisterRouter.scala:87:24]
wire _out_T_11172 = ~out_rimask_1157; // @[RegisterRouter.scala:87:24]
wire _out_T_11173 = ~out_wimask_1157; // @[RegisterRouter.scala:87:24]
wire _out_T_11174 = ~out_romask_1157; // @[RegisterRouter.scala:87:24]
wire _out_T_11175 = ~out_womask_1157; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11177 = _out_T_11176; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_993 = _out_T_11177; // @[RegisterRouter.scala:87:24]
wire out_rimask_1158 = |_out_rimask_T_1158; // @[RegisterRouter.scala:87:24]
wire out_wimask_1158 = &_out_wimask_T_1158; // @[RegisterRouter.scala:87:24]
wire out_romask_1158 = |_out_romask_T_1158; // @[RegisterRouter.scala:87:24]
wire out_womask_1158 = &_out_womask_T_1158; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1158 = out_rivalid_1_1012 & out_rimask_1158; // @[RegisterRouter.scala:87:24]
wire _out_T_11179 = out_f_rivalid_1158; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1158 = out_roready_1_1012 & out_romask_1158; // @[RegisterRouter.scala:87:24]
wire _out_T_11180 = out_f_roready_1158; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1158 = out_wivalid_1_1012 & out_wimask_1158; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1158 = out_woready_1_1012 & out_womask_1158; // @[RegisterRouter.scala:87:24]
wire _out_T_11181 = ~out_rimask_1158; // @[RegisterRouter.scala:87:24]
wire _out_T_11182 = ~out_wimask_1158; // @[RegisterRouter.scala:87:24]
wire _out_T_11183 = ~out_romask_1158; // @[RegisterRouter.scala:87:24]
wire _out_T_11184 = ~out_womask_1158; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_993 = {hi_690, flags_0_go, _out_prepend_T_993}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_11185 = out_prepend_993; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_11186 = _out_T_11185; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_994 = _out_T_11186; // @[RegisterRouter.scala:87:24]
wire out_rimask_1159 = |_out_rimask_T_1159; // @[RegisterRouter.scala:87:24]
wire out_wimask_1159 = &_out_wimask_T_1159; // @[RegisterRouter.scala:87:24]
wire out_romask_1159 = |_out_romask_T_1159; // @[RegisterRouter.scala:87:24]
wire out_womask_1159 = &_out_womask_T_1159; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1159 = out_rivalid_1_1013 & out_rimask_1159; // @[RegisterRouter.scala:87:24]
wire _out_T_11188 = out_f_rivalid_1159; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1159 = out_roready_1_1013 & out_romask_1159; // @[RegisterRouter.scala:87:24]
wire _out_T_11189 = out_f_roready_1159; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1159 = out_wivalid_1_1013 & out_wimask_1159; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1159 = out_woready_1_1013 & out_womask_1159; // @[RegisterRouter.scala:87:24]
wire _out_T_11190 = ~out_rimask_1159; // @[RegisterRouter.scala:87:24]
wire _out_T_11191 = ~out_wimask_1159; // @[RegisterRouter.scala:87:24]
wire _out_T_11192 = ~out_romask_1159; // @[RegisterRouter.scala:87:24]
wire _out_T_11193 = ~out_womask_1159; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_994 = {hi_691, flags_0_go, _out_prepend_T_994}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_11194 = out_prepend_994; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_11195 = _out_T_11194; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_995 = _out_T_11195; // @[RegisterRouter.scala:87:24]
wire out_rimask_1160 = |_out_rimask_T_1160; // @[RegisterRouter.scala:87:24]
wire out_wimask_1160 = &_out_wimask_T_1160; // @[RegisterRouter.scala:87:24]
wire out_romask_1160 = |_out_romask_T_1160; // @[RegisterRouter.scala:87:24]
wire out_womask_1160 = &_out_womask_T_1160; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1160 = out_rivalid_1_1014 & out_rimask_1160; // @[RegisterRouter.scala:87:24]
wire _out_T_11197 = out_f_rivalid_1160; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1160 = out_roready_1_1014 & out_romask_1160; // @[RegisterRouter.scala:87:24]
wire _out_T_11198 = out_f_roready_1160; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1160 = out_wivalid_1_1014 & out_wimask_1160; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1160 = out_woready_1_1014 & out_womask_1160; // @[RegisterRouter.scala:87:24]
wire _out_T_11199 = ~out_rimask_1160; // @[RegisterRouter.scala:87:24]
wire _out_T_11200 = ~out_wimask_1160; // @[RegisterRouter.scala:87:24]
wire _out_T_11201 = ~out_romask_1160; // @[RegisterRouter.scala:87:24]
wire _out_T_11202 = ~out_womask_1160; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_995 = {hi_692, flags_0_go, _out_prepend_T_995}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_11203 = out_prepend_995; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_11204 = _out_T_11203; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_996 = _out_T_11204; // @[RegisterRouter.scala:87:24]
wire out_rimask_1161 = |_out_rimask_T_1161; // @[RegisterRouter.scala:87:24]
wire out_wimask_1161 = &_out_wimask_T_1161; // @[RegisterRouter.scala:87:24]
wire out_romask_1161 = |_out_romask_T_1161; // @[RegisterRouter.scala:87:24]
wire out_womask_1161 = &_out_womask_T_1161; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1161 = out_rivalid_1_1015 & out_rimask_1161; // @[RegisterRouter.scala:87:24]
wire _out_T_11206 = out_f_rivalid_1161; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1161 = out_roready_1_1015 & out_romask_1161; // @[RegisterRouter.scala:87:24]
wire _out_T_11207 = out_f_roready_1161; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1161 = out_wivalid_1_1015 & out_wimask_1161; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1161 = out_woready_1_1015 & out_womask_1161; // @[RegisterRouter.scala:87:24]
wire _out_T_11208 = ~out_rimask_1161; // @[RegisterRouter.scala:87:24]
wire _out_T_11209 = ~out_wimask_1161; // @[RegisterRouter.scala:87:24]
wire _out_T_11210 = ~out_romask_1161; // @[RegisterRouter.scala:87:24]
wire _out_T_11211 = ~out_womask_1161; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_996 = {hi_693, flags_0_go, _out_prepend_T_996}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_11212 = out_prepend_996; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_11213 = _out_T_11212; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_997 = _out_T_11213; // @[RegisterRouter.scala:87:24]
wire out_rimask_1162 = |_out_rimask_T_1162; // @[RegisterRouter.scala:87:24]
wire out_wimask_1162 = &_out_wimask_T_1162; // @[RegisterRouter.scala:87:24]
wire out_romask_1162 = |_out_romask_T_1162; // @[RegisterRouter.scala:87:24]
wire out_womask_1162 = &_out_womask_T_1162; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1162 = out_rivalid_1_1016 & out_rimask_1162; // @[RegisterRouter.scala:87:24]
wire _out_T_11215 = out_f_rivalid_1162; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1162 = out_roready_1_1016 & out_romask_1162; // @[RegisterRouter.scala:87:24]
wire _out_T_11216 = out_f_roready_1162; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1162 = out_wivalid_1_1016 & out_wimask_1162; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1162 = out_woready_1_1016 & out_womask_1162; // @[RegisterRouter.scala:87:24]
wire _out_T_11217 = ~out_rimask_1162; // @[RegisterRouter.scala:87:24]
wire _out_T_11218 = ~out_wimask_1162; // @[RegisterRouter.scala:87:24]
wire _out_T_11219 = ~out_romask_1162; // @[RegisterRouter.scala:87:24]
wire _out_T_11220 = ~out_womask_1162; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_997 = {hi_694, flags_0_go, _out_prepend_T_997}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_11221 = out_prepend_997; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_11222 = _out_T_11221; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_998 = _out_T_11222; // @[RegisterRouter.scala:87:24]
wire out_rimask_1163 = |_out_rimask_T_1163; // @[RegisterRouter.scala:87:24]
wire out_wimask_1163 = &_out_wimask_T_1163; // @[RegisterRouter.scala:87:24]
wire out_romask_1163 = |_out_romask_T_1163; // @[RegisterRouter.scala:87:24]
wire out_womask_1163 = &_out_womask_T_1163; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1163 = out_rivalid_1_1017 & out_rimask_1163; // @[RegisterRouter.scala:87:24]
wire _out_T_11224 = out_f_rivalid_1163; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1163 = out_roready_1_1017 & out_romask_1163; // @[RegisterRouter.scala:87:24]
wire _out_T_11225 = out_f_roready_1163; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1163 = out_wivalid_1_1017 & out_wimask_1163; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1163 = out_woready_1_1017 & out_womask_1163; // @[RegisterRouter.scala:87:24]
wire _out_T_11226 = ~out_rimask_1163; // @[RegisterRouter.scala:87:24]
wire _out_T_11227 = ~out_wimask_1163; // @[RegisterRouter.scala:87:24]
wire _out_T_11228 = ~out_romask_1163; // @[RegisterRouter.scala:87:24]
wire _out_T_11229 = ~out_womask_1163; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_998 = {hi_695, flags_0_go, _out_prepend_T_998}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_11230 = out_prepend_998; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_11231 = _out_T_11230; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_999 = _out_T_11231; // @[RegisterRouter.scala:87:24]
wire out_rimask_1164 = |_out_rimask_T_1164; // @[RegisterRouter.scala:87:24]
wire out_wimask_1164 = &_out_wimask_T_1164; // @[RegisterRouter.scala:87:24]
wire out_romask_1164 = |_out_romask_T_1164; // @[RegisterRouter.scala:87:24]
wire out_womask_1164 = &_out_womask_T_1164; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1164 = out_rivalid_1_1018 & out_rimask_1164; // @[RegisterRouter.scala:87:24]
wire _out_T_11233 = out_f_rivalid_1164; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1164 = out_roready_1_1018 & out_romask_1164; // @[RegisterRouter.scala:87:24]
wire _out_T_11234 = out_f_roready_1164; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1164 = out_wivalid_1_1018 & out_wimask_1164; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1164 = out_woready_1_1018 & out_womask_1164; // @[RegisterRouter.scala:87:24]
wire _out_T_11235 = ~out_rimask_1164; // @[RegisterRouter.scala:87:24]
wire _out_T_11236 = ~out_wimask_1164; // @[RegisterRouter.scala:87:24]
wire _out_T_11237 = ~out_romask_1164; // @[RegisterRouter.scala:87:24]
wire _out_T_11238 = ~out_womask_1164; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_999 = {hi_696, flags_0_go, _out_prepend_T_999}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_11239 = out_prepend_999; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_11240 = _out_T_11239; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_214 = _out_T_11240; // @[MuxLiteral.scala:49:48]
wire out_rimask_1165 = |_out_rimask_T_1165; // @[RegisterRouter.scala:87:24]
wire out_wimask_1165 = &_out_wimask_T_1165; // @[RegisterRouter.scala:87:24]
wire out_romask_1165 = |_out_romask_T_1165; // @[RegisterRouter.scala:87:24]
wire out_womask_1165 = &_out_womask_T_1165; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1165 = out_rivalid_1_1019 & out_rimask_1165; // @[RegisterRouter.scala:87:24]
wire _out_T_11242 = out_f_rivalid_1165; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1165 = out_roready_1_1019 & out_romask_1165; // @[RegisterRouter.scala:87:24]
wire _out_T_11243 = out_f_roready_1165; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1165 = out_wivalid_1_1019 & out_wimask_1165; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1165 = out_woready_1_1019 & out_womask_1165; // @[RegisterRouter.scala:87:24]
wire _out_T_11244 = ~out_rimask_1165; // @[RegisterRouter.scala:87:24]
wire _out_T_11245 = ~out_wimask_1165; // @[RegisterRouter.scala:87:24]
wire _out_T_11246 = ~out_romask_1165; // @[RegisterRouter.scala:87:24]
wire _out_T_11247 = ~out_womask_1165; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11249 = _out_T_11248; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_1000 = _out_T_11249; // @[RegisterRouter.scala:87:24]
wire out_rimask_1166 = |_out_rimask_T_1166; // @[RegisterRouter.scala:87:24]
wire out_wimask_1166 = &_out_wimask_T_1166; // @[RegisterRouter.scala:87:24]
wire out_romask_1166 = |_out_romask_T_1166; // @[RegisterRouter.scala:87:24]
wire out_womask_1166 = &_out_womask_T_1166; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1166 = out_rivalid_1_1020 & out_rimask_1166; // @[RegisterRouter.scala:87:24]
wire _out_T_11251 = out_f_rivalid_1166; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1166 = out_roready_1_1020 & out_romask_1166; // @[RegisterRouter.scala:87:24]
wire _out_T_11252 = out_f_roready_1166; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1166 = out_wivalid_1_1020 & out_wimask_1166; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1166 = out_woready_1_1020 & out_womask_1166; // @[RegisterRouter.scala:87:24]
wire _out_T_11253 = ~out_rimask_1166; // @[RegisterRouter.scala:87:24]
wire _out_T_11254 = ~out_wimask_1166; // @[RegisterRouter.scala:87:24]
wire _out_T_11255 = ~out_romask_1166; // @[RegisterRouter.scala:87:24]
wire _out_T_11256 = ~out_womask_1166; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_1000 = {hi_858, flags_0_go, _out_prepend_T_1000}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_11257 = out_prepend_1000; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_11258 = _out_T_11257; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_1001 = _out_T_11258; // @[RegisterRouter.scala:87:24]
wire out_rimask_1167 = |_out_rimask_T_1167; // @[RegisterRouter.scala:87:24]
wire out_wimask_1167 = &_out_wimask_T_1167; // @[RegisterRouter.scala:87:24]
wire out_romask_1167 = |_out_romask_T_1167; // @[RegisterRouter.scala:87:24]
wire out_womask_1167 = &_out_womask_T_1167; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1167 = out_rivalid_1_1021 & out_rimask_1167; // @[RegisterRouter.scala:87:24]
wire _out_T_11260 = out_f_rivalid_1167; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1167 = out_roready_1_1021 & out_romask_1167; // @[RegisterRouter.scala:87:24]
wire _out_T_11261 = out_f_roready_1167; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1167 = out_wivalid_1_1021 & out_wimask_1167; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1167 = out_woready_1_1021 & out_womask_1167; // @[RegisterRouter.scala:87:24]
wire _out_T_11262 = ~out_rimask_1167; // @[RegisterRouter.scala:87:24]
wire _out_T_11263 = ~out_wimask_1167; // @[RegisterRouter.scala:87:24]
wire _out_T_11264 = ~out_romask_1167; // @[RegisterRouter.scala:87:24]
wire _out_T_11265 = ~out_womask_1167; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_1001 = {hi_859, flags_0_go, _out_prepend_T_1001}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_11266 = out_prepend_1001; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_11267 = _out_T_11266; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_1002 = _out_T_11267; // @[RegisterRouter.scala:87:24]
wire out_rimask_1168 = |_out_rimask_T_1168; // @[RegisterRouter.scala:87:24]
wire out_wimask_1168 = &_out_wimask_T_1168; // @[RegisterRouter.scala:87:24]
wire out_romask_1168 = |_out_romask_T_1168; // @[RegisterRouter.scala:87:24]
wire out_womask_1168 = &_out_womask_T_1168; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1168 = out_rivalid_1_1022 & out_rimask_1168; // @[RegisterRouter.scala:87:24]
wire _out_T_11269 = out_f_rivalid_1168; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1168 = out_roready_1_1022 & out_romask_1168; // @[RegisterRouter.scala:87:24]
wire _out_T_11270 = out_f_roready_1168; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1168 = out_wivalid_1_1022 & out_wimask_1168; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1168 = out_woready_1_1022 & out_womask_1168; // @[RegisterRouter.scala:87:24]
wire _out_T_11271 = ~out_rimask_1168; // @[RegisterRouter.scala:87:24]
wire _out_T_11272 = ~out_wimask_1168; // @[RegisterRouter.scala:87:24]
wire _out_T_11273 = ~out_romask_1168; // @[RegisterRouter.scala:87:24]
wire _out_T_11274 = ~out_womask_1168; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_1002 = {hi_860, flags_0_go, _out_prepend_T_1002}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_11275 = out_prepend_1002; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_11276 = _out_T_11275; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_1003 = _out_T_11276; // @[RegisterRouter.scala:87:24]
wire out_rimask_1169 = |_out_rimask_T_1169; // @[RegisterRouter.scala:87:24]
wire out_wimask_1169 = &_out_wimask_T_1169; // @[RegisterRouter.scala:87:24]
wire out_romask_1169 = |_out_romask_T_1169; // @[RegisterRouter.scala:87:24]
wire out_womask_1169 = &_out_womask_T_1169; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1169 = out_rivalid_1_1023 & out_rimask_1169; // @[RegisterRouter.scala:87:24]
wire _out_T_11278 = out_f_rivalid_1169; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1169 = out_roready_1_1023 & out_romask_1169; // @[RegisterRouter.scala:87:24]
wire _out_T_11279 = out_f_roready_1169; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1169 = out_wivalid_1_1023 & out_wimask_1169; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1169 = out_woready_1_1023 & out_womask_1169; // @[RegisterRouter.scala:87:24]
wire _out_T_11280 = ~out_rimask_1169; // @[RegisterRouter.scala:87:24]
wire _out_T_11281 = ~out_wimask_1169; // @[RegisterRouter.scala:87:24]
wire _out_T_11282 = ~out_romask_1169; // @[RegisterRouter.scala:87:24]
wire _out_T_11283 = ~out_womask_1169; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_1003 = {hi_861, flags_0_go, _out_prepend_T_1003}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_11284 = out_prepend_1003; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_11285 = _out_T_11284; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_1004 = _out_T_11285; // @[RegisterRouter.scala:87:24]
wire out_rimask_1170 = |_out_rimask_T_1170; // @[RegisterRouter.scala:87:24]
wire out_wimask_1170 = &_out_wimask_T_1170; // @[RegisterRouter.scala:87:24]
wire out_romask_1170 = |_out_romask_T_1170; // @[RegisterRouter.scala:87:24]
wire out_womask_1170 = &_out_womask_T_1170; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1170 = out_rivalid_1_1024 & out_rimask_1170; // @[RegisterRouter.scala:87:24]
wire _out_T_11287 = out_f_rivalid_1170; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1170 = out_roready_1_1024 & out_romask_1170; // @[RegisterRouter.scala:87:24]
wire _out_T_11288 = out_f_roready_1170; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1170 = out_wivalid_1_1024 & out_wimask_1170; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1170 = out_woready_1_1024 & out_womask_1170; // @[RegisterRouter.scala:87:24]
wire _out_T_11289 = ~out_rimask_1170; // @[RegisterRouter.scala:87:24]
wire _out_T_11290 = ~out_wimask_1170; // @[RegisterRouter.scala:87:24]
wire _out_T_11291 = ~out_romask_1170; // @[RegisterRouter.scala:87:24]
wire _out_T_11292 = ~out_womask_1170; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_1004 = {hi_862, flags_0_go, _out_prepend_T_1004}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_11293 = out_prepend_1004; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_11294 = _out_T_11293; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_1005 = _out_T_11294; // @[RegisterRouter.scala:87:24]
wire out_rimask_1171 = |_out_rimask_T_1171; // @[RegisterRouter.scala:87:24]
wire out_wimask_1171 = &_out_wimask_T_1171; // @[RegisterRouter.scala:87:24]
wire out_romask_1171 = |_out_romask_T_1171; // @[RegisterRouter.scala:87:24]
wire out_womask_1171 = &_out_womask_T_1171; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1171 = out_rivalid_1_1025 & out_rimask_1171; // @[RegisterRouter.scala:87:24]
wire _out_T_11296 = out_f_rivalid_1171; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1171 = out_roready_1_1025 & out_romask_1171; // @[RegisterRouter.scala:87:24]
wire _out_T_11297 = out_f_roready_1171; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1171 = out_wivalid_1_1025 & out_wimask_1171; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1171 = out_woready_1_1025 & out_womask_1171; // @[RegisterRouter.scala:87:24]
wire _out_T_11298 = ~out_rimask_1171; // @[RegisterRouter.scala:87:24]
wire _out_T_11299 = ~out_wimask_1171; // @[RegisterRouter.scala:87:24]
wire _out_T_11300 = ~out_romask_1171; // @[RegisterRouter.scala:87:24]
wire _out_T_11301 = ~out_womask_1171; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_1005 = {hi_863, flags_0_go, _out_prepend_T_1005}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_11302 = out_prepend_1005; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_11303 = _out_T_11302; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_1006 = _out_T_11303; // @[RegisterRouter.scala:87:24]
wire out_rimask_1172 = |_out_rimask_T_1172; // @[RegisterRouter.scala:87:24]
wire out_wimask_1172 = &_out_wimask_T_1172; // @[RegisterRouter.scala:87:24]
wire out_romask_1172 = |_out_romask_T_1172; // @[RegisterRouter.scala:87:24]
wire out_womask_1172 = &_out_womask_T_1172; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1172 = out_rivalid_1_1026 & out_rimask_1172; // @[RegisterRouter.scala:87:24]
wire _out_T_11305 = out_f_rivalid_1172; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1172 = out_roready_1_1026 & out_romask_1172; // @[RegisterRouter.scala:87:24]
wire _out_T_11306 = out_f_roready_1172; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1172 = out_wivalid_1_1026 & out_wimask_1172; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1172 = out_woready_1_1026 & out_womask_1172; // @[RegisterRouter.scala:87:24]
wire _out_T_11307 = ~out_rimask_1172; // @[RegisterRouter.scala:87:24]
wire _out_T_11308 = ~out_wimask_1172; // @[RegisterRouter.scala:87:24]
wire _out_T_11309 = ~out_romask_1172; // @[RegisterRouter.scala:87:24]
wire _out_T_11310 = ~out_womask_1172; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_1006 = {hi_864, flags_0_go, _out_prepend_T_1006}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_11311 = out_prepend_1006; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_11312 = _out_T_11311; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_235 = _out_T_11312; // @[MuxLiteral.scala:49:48]
wire out_rimask_1173 = |_out_rimask_T_1173; // @[RegisterRouter.scala:87:24]
wire out_wimask_1173 = &_out_wimask_T_1173; // @[RegisterRouter.scala:87:24]
wire out_romask_1173 = |_out_romask_T_1173; // @[RegisterRouter.scala:87:24]
wire out_womask_1173 = &_out_womask_T_1173; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1173 = out_rivalid_1_1027 & out_rimask_1173; // @[RegisterRouter.scala:87:24]
wire _out_T_11314 = out_f_rivalid_1173; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1173 = out_roready_1_1027 & out_romask_1173; // @[RegisterRouter.scala:87:24]
wire _out_T_11315 = out_f_roready_1173; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1173 = out_wivalid_1_1027 & out_wimask_1173; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1173 = out_woready_1_1027 & out_womask_1173; // @[RegisterRouter.scala:87:24]
wire _out_T_11316 = ~out_rimask_1173; // @[RegisterRouter.scala:87:24]
wire _out_T_11317 = ~out_wimask_1173; // @[RegisterRouter.scala:87:24]
wire _out_T_11318 = ~out_romask_1173; // @[RegisterRouter.scala:87:24]
wire _out_T_11319 = ~out_womask_1173; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11321 = _out_T_11320; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_1007 = _out_T_11321; // @[RegisterRouter.scala:87:24]
wire out_rimask_1174 = |_out_rimask_T_1174; // @[RegisterRouter.scala:87:24]
wire out_wimask_1174 = &_out_wimask_T_1174; // @[RegisterRouter.scala:87:24]
wire out_romask_1174 = |_out_romask_T_1174; // @[RegisterRouter.scala:87:24]
wire out_womask_1174 = &_out_womask_T_1174; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1174 = out_rivalid_1_1028 & out_rimask_1174; // @[RegisterRouter.scala:87:24]
wire _out_T_11323 = out_f_rivalid_1174; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1174 = out_roready_1_1028 & out_romask_1174; // @[RegisterRouter.scala:87:24]
wire _out_T_11324 = out_f_roready_1174; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1174 = out_wivalid_1_1028 & out_wimask_1174; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1174 = out_woready_1_1028 & out_womask_1174; // @[RegisterRouter.scala:87:24]
wire _out_T_11325 = ~out_rimask_1174; // @[RegisterRouter.scala:87:24]
wire _out_T_11326 = ~out_wimask_1174; // @[RegisterRouter.scala:87:24]
wire _out_T_11327 = ~out_romask_1174; // @[RegisterRouter.scala:87:24]
wire _out_T_11328 = ~out_womask_1174; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_1007 = {hi_946, flags_0_go, _out_prepend_T_1007}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_11329 = out_prepend_1007; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_11330 = _out_T_11329; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_1008 = _out_T_11330; // @[RegisterRouter.scala:87:24]
wire out_rimask_1175 = |_out_rimask_T_1175; // @[RegisterRouter.scala:87:24]
wire out_wimask_1175 = &_out_wimask_T_1175; // @[RegisterRouter.scala:87:24]
wire out_romask_1175 = |_out_romask_T_1175; // @[RegisterRouter.scala:87:24]
wire out_womask_1175 = &_out_womask_T_1175; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1175 = out_rivalid_1_1029 & out_rimask_1175; // @[RegisterRouter.scala:87:24]
wire _out_T_11332 = out_f_rivalid_1175; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1175 = out_roready_1_1029 & out_romask_1175; // @[RegisterRouter.scala:87:24]
wire _out_T_11333 = out_f_roready_1175; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1175 = out_wivalid_1_1029 & out_wimask_1175; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1175 = out_woready_1_1029 & out_womask_1175; // @[RegisterRouter.scala:87:24]
wire _out_T_11334 = ~out_rimask_1175; // @[RegisterRouter.scala:87:24]
wire _out_T_11335 = ~out_wimask_1175; // @[RegisterRouter.scala:87:24]
wire _out_T_11336 = ~out_romask_1175; // @[RegisterRouter.scala:87:24]
wire _out_T_11337 = ~out_womask_1175; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_1008 = {hi_947, flags_0_go, _out_prepend_T_1008}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_11338 = out_prepend_1008; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_11339 = _out_T_11338; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_1009 = _out_T_11339; // @[RegisterRouter.scala:87:24]
wire out_rimask_1176 = |_out_rimask_T_1176; // @[RegisterRouter.scala:87:24]
wire out_wimask_1176 = &_out_wimask_T_1176; // @[RegisterRouter.scala:87:24]
wire out_romask_1176 = |_out_romask_T_1176; // @[RegisterRouter.scala:87:24]
wire out_womask_1176 = &_out_womask_T_1176; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1176 = out_rivalid_1_1030 & out_rimask_1176; // @[RegisterRouter.scala:87:24]
wire _out_T_11341 = out_f_rivalid_1176; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1176 = out_roready_1_1030 & out_romask_1176; // @[RegisterRouter.scala:87:24]
wire _out_T_11342 = out_f_roready_1176; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1176 = out_wivalid_1_1030 & out_wimask_1176; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1176 = out_woready_1_1030 & out_womask_1176; // @[RegisterRouter.scala:87:24]
wire _out_T_11343 = ~out_rimask_1176; // @[RegisterRouter.scala:87:24]
wire _out_T_11344 = ~out_wimask_1176; // @[RegisterRouter.scala:87:24]
wire _out_T_11345 = ~out_romask_1176; // @[RegisterRouter.scala:87:24]
wire _out_T_11346 = ~out_womask_1176; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_1009 = {hi_948, flags_0_go, _out_prepend_T_1009}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_11347 = out_prepend_1009; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_11348 = _out_T_11347; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_1010 = _out_T_11348; // @[RegisterRouter.scala:87:24]
wire out_rimask_1177 = |_out_rimask_T_1177; // @[RegisterRouter.scala:87:24]
wire out_wimask_1177 = &_out_wimask_T_1177; // @[RegisterRouter.scala:87:24]
wire out_romask_1177 = |_out_romask_T_1177; // @[RegisterRouter.scala:87:24]
wire out_womask_1177 = &_out_womask_T_1177; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1177 = out_rivalid_1_1031 & out_rimask_1177; // @[RegisterRouter.scala:87:24]
wire _out_T_11350 = out_f_rivalid_1177; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1177 = out_roready_1_1031 & out_romask_1177; // @[RegisterRouter.scala:87:24]
wire _out_T_11351 = out_f_roready_1177; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1177 = out_wivalid_1_1031 & out_wimask_1177; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1177 = out_woready_1_1031 & out_womask_1177; // @[RegisterRouter.scala:87:24]
wire _out_T_11352 = ~out_rimask_1177; // @[RegisterRouter.scala:87:24]
wire _out_T_11353 = ~out_wimask_1177; // @[RegisterRouter.scala:87:24]
wire _out_T_11354 = ~out_romask_1177; // @[RegisterRouter.scala:87:24]
wire _out_T_11355 = ~out_womask_1177; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_1010 = {hi_949, flags_0_go, _out_prepend_T_1010}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_11356 = out_prepend_1010; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_11357 = _out_T_11356; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_1011 = _out_T_11357; // @[RegisterRouter.scala:87:24]
wire out_rimask_1178 = |_out_rimask_T_1178; // @[RegisterRouter.scala:87:24]
wire out_wimask_1178 = &_out_wimask_T_1178; // @[RegisterRouter.scala:87:24]
wire out_romask_1178 = |_out_romask_T_1178; // @[RegisterRouter.scala:87:24]
wire out_womask_1178 = &_out_womask_T_1178; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1178 = out_rivalid_1_1032 & out_rimask_1178; // @[RegisterRouter.scala:87:24]
wire _out_T_11359 = out_f_rivalid_1178; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1178 = out_roready_1_1032 & out_romask_1178; // @[RegisterRouter.scala:87:24]
wire _out_T_11360 = out_f_roready_1178; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1178 = out_wivalid_1_1032 & out_wimask_1178; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1178 = out_woready_1_1032 & out_womask_1178; // @[RegisterRouter.scala:87:24]
wire _out_T_11361 = ~out_rimask_1178; // @[RegisterRouter.scala:87:24]
wire _out_T_11362 = ~out_wimask_1178; // @[RegisterRouter.scala:87:24]
wire _out_T_11363 = ~out_romask_1178; // @[RegisterRouter.scala:87:24]
wire _out_T_11364 = ~out_womask_1178; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_1011 = {hi_950, flags_0_go, _out_prepend_T_1011}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_11365 = out_prepend_1011; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_11366 = _out_T_11365; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_1012 = _out_T_11366; // @[RegisterRouter.scala:87:24]
wire out_rimask_1179 = |_out_rimask_T_1179; // @[RegisterRouter.scala:87:24]
wire out_wimask_1179 = &_out_wimask_T_1179; // @[RegisterRouter.scala:87:24]
wire out_romask_1179 = |_out_romask_T_1179; // @[RegisterRouter.scala:87:24]
wire out_womask_1179 = &_out_womask_T_1179; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1179 = out_rivalid_1_1033 & out_rimask_1179; // @[RegisterRouter.scala:87:24]
wire _out_T_11368 = out_f_rivalid_1179; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1179 = out_roready_1_1033 & out_romask_1179; // @[RegisterRouter.scala:87:24]
wire _out_T_11369 = out_f_roready_1179; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1179 = out_wivalid_1_1033 & out_wimask_1179; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1179 = out_woready_1_1033 & out_womask_1179; // @[RegisterRouter.scala:87:24]
wire _out_T_11370 = ~out_rimask_1179; // @[RegisterRouter.scala:87:24]
wire _out_T_11371 = ~out_wimask_1179; // @[RegisterRouter.scala:87:24]
wire _out_T_11372 = ~out_romask_1179; // @[RegisterRouter.scala:87:24]
wire _out_T_11373 = ~out_womask_1179; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_1012 = {hi_951, flags_0_go, _out_prepend_T_1012}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_11374 = out_prepend_1012; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_11375 = _out_T_11374; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_1013 = _out_T_11375; // @[RegisterRouter.scala:87:24]
wire out_rimask_1180 = |_out_rimask_T_1180; // @[RegisterRouter.scala:87:24]
wire out_wimask_1180 = &_out_wimask_T_1180; // @[RegisterRouter.scala:87:24]
wire out_romask_1180 = |_out_romask_T_1180; // @[RegisterRouter.scala:87:24]
wire out_womask_1180 = &_out_womask_T_1180; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1180 = out_rivalid_1_1034 & out_rimask_1180; // @[RegisterRouter.scala:87:24]
wire _out_T_11377 = out_f_rivalid_1180; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1180 = out_roready_1_1034 & out_romask_1180; // @[RegisterRouter.scala:87:24]
wire _out_T_11378 = out_f_roready_1180; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1180 = out_wivalid_1_1034 & out_wimask_1180; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1180 = out_woready_1_1034 & out_womask_1180; // @[RegisterRouter.scala:87:24]
wire _out_T_11379 = ~out_rimask_1180; // @[RegisterRouter.scala:87:24]
wire _out_T_11380 = ~out_wimask_1180; // @[RegisterRouter.scala:87:24]
wire _out_T_11381 = ~out_romask_1180; // @[RegisterRouter.scala:87:24]
wire _out_T_11382 = ~out_womask_1180; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_1013 = {hi_952, flags_0_go, _out_prepend_T_1013}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_11383 = out_prepend_1013; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_11384 = _out_T_11383; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_246 = _out_T_11384; // @[MuxLiteral.scala:49:48]
wire out_rimask_1181 = |_out_rimask_T_1181; // @[RegisterRouter.scala:87:24]
wire out_wimask_1181 = &_out_wimask_T_1181; // @[RegisterRouter.scala:87:24]
wire out_romask_1181 = |_out_romask_T_1181; // @[RegisterRouter.scala:87:24]
wire out_womask_1181 = &_out_womask_T_1181; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1181 = out_rivalid_1_1035 & out_rimask_1181; // @[RegisterRouter.scala:87:24]
wire _out_T_11386 = out_f_rivalid_1181; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1181 = out_roready_1_1035 & out_romask_1181; // @[RegisterRouter.scala:87:24]
wire _out_T_11387 = out_f_roready_1181; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1181 = out_wivalid_1_1035 & out_wimask_1181; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1181 = out_woready_1_1035 & out_womask_1181; // @[RegisterRouter.scala:87:24]
wire _out_T_11388 = ~out_rimask_1181; // @[RegisterRouter.scala:87:24]
wire _out_T_11389 = ~out_wimask_1181; // @[RegisterRouter.scala:87:24]
wire _out_T_11390 = ~out_romask_1181; // @[RegisterRouter.scala:87:24]
wire _out_T_11391 = ~out_womask_1181; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11393 = _out_T_11392; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_1014 = _out_T_11393; // @[RegisterRouter.scala:87:24]
wire out_rimask_1182 = |_out_rimask_T_1182; // @[RegisterRouter.scala:87:24]
wire out_wimask_1182 = &_out_wimask_T_1182; // @[RegisterRouter.scala:87:24]
wire out_romask_1182 = |_out_romask_T_1182; // @[RegisterRouter.scala:87:24]
wire out_womask_1182 = &_out_womask_T_1182; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1182 = out_rivalid_1_1036 & out_rimask_1182; // @[RegisterRouter.scala:87:24]
wire _out_T_11395 = out_f_rivalid_1182; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1182 = out_roready_1_1036 & out_romask_1182; // @[RegisterRouter.scala:87:24]
wire _out_T_11396 = out_f_roready_1182; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1182 = out_wivalid_1_1036 & out_wimask_1182; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1182 = out_woready_1_1036 & out_womask_1182; // @[RegisterRouter.scala:87:24]
wire _out_T_11397 = ~out_rimask_1182; // @[RegisterRouter.scala:87:24]
wire _out_T_11398 = ~out_wimask_1182; // @[RegisterRouter.scala:87:24]
wire _out_T_11399 = ~out_romask_1182; // @[RegisterRouter.scala:87:24]
wire _out_T_11400 = ~out_womask_1182; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_1014 = {hi_186, flags_0_go, _out_prepend_T_1014}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_11401 = out_prepend_1014; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_11402 = _out_T_11401; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_1015 = _out_T_11402; // @[RegisterRouter.scala:87:24]
wire out_rimask_1183 = |_out_rimask_T_1183; // @[RegisterRouter.scala:87:24]
wire out_wimask_1183 = &_out_wimask_T_1183; // @[RegisterRouter.scala:87:24]
wire out_romask_1183 = |_out_romask_T_1183; // @[RegisterRouter.scala:87:24]
wire out_womask_1183 = &_out_womask_T_1183; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1183 = out_rivalid_1_1037 & out_rimask_1183; // @[RegisterRouter.scala:87:24]
wire _out_T_11404 = out_f_rivalid_1183; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1183 = out_roready_1_1037 & out_romask_1183; // @[RegisterRouter.scala:87:24]
wire _out_T_11405 = out_f_roready_1183; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1183 = out_wivalid_1_1037 & out_wimask_1183; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1183 = out_woready_1_1037 & out_womask_1183; // @[RegisterRouter.scala:87:24]
wire _out_T_11406 = ~out_rimask_1183; // @[RegisterRouter.scala:87:24]
wire _out_T_11407 = ~out_wimask_1183; // @[RegisterRouter.scala:87:24]
wire _out_T_11408 = ~out_romask_1183; // @[RegisterRouter.scala:87:24]
wire _out_T_11409 = ~out_womask_1183; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_1015 = {hi_187, flags_0_go, _out_prepend_T_1015}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_11410 = out_prepend_1015; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_11411 = _out_T_11410; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_1016 = _out_T_11411; // @[RegisterRouter.scala:87:24]
wire out_rimask_1184 = |_out_rimask_T_1184; // @[RegisterRouter.scala:87:24]
wire out_wimask_1184 = &_out_wimask_T_1184; // @[RegisterRouter.scala:87:24]
wire out_romask_1184 = |_out_romask_T_1184; // @[RegisterRouter.scala:87:24]
wire out_womask_1184 = &_out_womask_T_1184; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1184 = out_rivalid_1_1038 & out_rimask_1184; // @[RegisterRouter.scala:87:24]
wire _out_T_11413 = out_f_rivalid_1184; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1184 = out_roready_1_1038 & out_romask_1184; // @[RegisterRouter.scala:87:24]
wire _out_T_11414 = out_f_roready_1184; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1184 = out_wivalid_1_1038 & out_wimask_1184; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1184 = out_woready_1_1038 & out_womask_1184; // @[RegisterRouter.scala:87:24]
wire _out_T_11415 = ~out_rimask_1184; // @[RegisterRouter.scala:87:24]
wire _out_T_11416 = ~out_wimask_1184; // @[RegisterRouter.scala:87:24]
wire _out_T_11417 = ~out_romask_1184; // @[RegisterRouter.scala:87:24]
wire _out_T_11418 = ~out_womask_1184; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_1016 = {hi_188, flags_0_go, _out_prepend_T_1016}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_11419 = out_prepend_1016; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_11420 = _out_T_11419; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_1017 = _out_T_11420; // @[RegisterRouter.scala:87:24]
wire out_rimask_1185 = |_out_rimask_T_1185; // @[RegisterRouter.scala:87:24]
wire out_wimask_1185 = &_out_wimask_T_1185; // @[RegisterRouter.scala:87:24]
wire out_romask_1185 = |_out_romask_T_1185; // @[RegisterRouter.scala:87:24]
wire out_womask_1185 = &_out_womask_T_1185; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1185 = out_rivalid_1_1039 & out_rimask_1185; // @[RegisterRouter.scala:87:24]
wire _out_T_11422 = out_f_rivalid_1185; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1185 = out_roready_1_1039 & out_romask_1185; // @[RegisterRouter.scala:87:24]
wire _out_T_11423 = out_f_roready_1185; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1185 = out_wivalid_1_1039 & out_wimask_1185; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1185 = out_woready_1_1039 & out_womask_1185; // @[RegisterRouter.scala:87:24]
wire _out_T_11424 = ~out_rimask_1185; // @[RegisterRouter.scala:87:24]
wire _out_T_11425 = ~out_wimask_1185; // @[RegisterRouter.scala:87:24]
wire _out_T_11426 = ~out_romask_1185; // @[RegisterRouter.scala:87:24]
wire _out_T_11427 = ~out_womask_1185; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_1017 = {hi_189, flags_0_go, _out_prepend_T_1017}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_11428 = out_prepend_1017; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_11429 = _out_T_11428; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_1018 = _out_T_11429; // @[RegisterRouter.scala:87:24]
wire out_rimask_1186 = |_out_rimask_T_1186; // @[RegisterRouter.scala:87:24]
wire out_wimask_1186 = &_out_wimask_T_1186; // @[RegisterRouter.scala:87:24]
wire out_romask_1186 = |_out_romask_T_1186; // @[RegisterRouter.scala:87:24]
wire out_womask_1186 = &_out_womask_T_1186; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1186 = out_rivalid_1_1040 & out_rimask_1186; // @[RegisterRouter.scala:87:24]
wire _out_T_11431 = out_f_rivalid_1186; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1186 = out_roready_1_1040 & out_romask_1186; // @[RegisterRouter.scala:87:24]
wire _out_T_11432 = out_f_roready_1186; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1186 = out_wivalid_1_1040 & out_wimask_1186; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1186 = out_woready_1_1040 & out_womask_1186; // @[RegisterRouter.scala:87:24]
wire _out_T_11433 = ~out_rimask_1186; // @[RegisterRouter.scala:87:24]
wire _out_T_11434 = ~out_wimask_1186; // @[RegisterRouter.scala:87:24]
wire _out_T_11435 = ~out_romask_1186; // @[RegisterRouter.scala:87:24]
wire _out_T_11436 = ~out_womask_1186; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_1018 = {hi_190, flags_0_go, _out_prepend_T_1018}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_11437 = out_prepend_1018; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_11438 = _out_T_11437; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_1019 = _out_T_11438; // @[RegisterRouter.scala:87:24]
wire out_rimask_1187 = |_out_rimask_T_1187; // @[RegisterRouter.scala:87:24]
wire out_wimask_1187 = &_out_wimask_T_1187; // @[RegisterRouter.scala:87:24]
wire out_romask_1187 = |_out_romask_T_1187; // @[RegisterRouter.scala:87:24]
wire out_womask_1187 = &_out_womask_T_1187; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1187 = out_rivalid_1_1041 & out_rimask_1187; // @[RegisterRouter.scala:87:24]
wire _out_T_11440 = out_f_rivalid_1187; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1187 = out_roready_1_1041 & out_romask_1187; // @[RegisterRouter.scala:87:24]
wire _out_T_11441 = out_f_roready_1187; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1187 = out_wivalid_1_1041 & out_wimask_1187; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1187 = out_woready_1_1041 & out_womask_1187; // @[RegisterRouter.scala:87:24]
wire _out_T_11442 = ~out_rimask_1187; // @[RegisterRouter.scala:87:24]
wire _out_T_11443 = ~out_wimask_1187; // @[RegisterRouter.scala:87:24]
wire _out_T_11444 = ~out_romask_1187; // @[RegisterRouter.scala:87:24]
wire _out_T_11445 = ~out_womask_1187; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_1019 = {hi_191, flags_0_go, _out_prepend_T_1019}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_11446 = out_prepend_1019; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_11447 = _out_T_11446; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_1020 = _out_T_11447; // @[RegisterRouter.scala:87:24]
wire out_rimask_1188 = |_out_rimask_T_1188; // @[RegisterRouter.scala:87:24]
wire out_wimask_1188 = &_out_wimask_T_1188; // @[RegisterRouter.scala:87:24]
wire out_romask_1188 = |_out_romask_T_1188; // @[RegisterRouter.scala:87:24]
wire out_womask_1188 = &_out_womask_T_1188; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1188 = out_rivalid_1_1042 & out_rimask_1188; // @[RegisterRouter.scala:87:24]
wire _out_T_11449 = out_f_rivalid_1188; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1188 = out_roready_1_1042 & out_romask_1188; // @[RegisterRouter.scala:87:24]
wire _out_T_11450 = out_f_roready_1188; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1188 = out_wivalid_1_1042 & out_wimask_1188; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1188 = out_woready_1_1042 & out_womask_1188; // @[RegisterRouter.scala:87:24]
wire _out_T_11451 = ~out_rimask_1188; // @[RegisterRouter.scala:87:24]
wire _out_T_11452 = ~out_wimask_1188; // @[RegisterRouter.scala:87:24]
wire _out_T_11453 = ~out_romask_1188; // @[RegisterRouter.scala:87:24]
wire _out_T_11454 = ~out_womask_1188; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_1020 = {hi_192, flags_0_go, _out_prepend_T_1020}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_11455 = out_prepend_1020; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_11456 = _out_T_11455; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_151 = _out_T_11456; // @[MuxLiteral.scala:49:48]
wire out_rimask_1189 = |_out_rimask_T_1189; // @[RegisterRouter.scala:87:24]
wire out_wimask_1189 = &_out_wimask_T_1189; // @[RegisterRouter.scala:87:24]
wire out_romask_1189 = |_out_romask_T_1189; // @[RegisterRouter.scala:87:24]
wire out_womask_1189 = &_out_womask_T_1189; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1189 = out_rivalid_1_1043 & out_rimask_1189; // @[RegisterRouter.scala:87:24]
wire _out_T_11458 = out_f_rivalid_1189; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1189 = out_roready_1_1043 & out_romask_1189; // @[RegisterRouter.scala:87:24]
wire _out_T_11459 = out_f_roready_1189; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1189 = out_wivalid_1_1043 & out_wimask_1189; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1189 = out_woready_1_1043 & out_womask_1189; // @[RegisterRouter.scala:87:24]
wire _out_T_11460 = ~out_rimask_1189; // @[RegisterRouter.scala:87:24]
wire _out_T_11461 = ~out_wimask_1189; // @[RegisterRouter.scala:87:24]
wire _out_T_11462 = ~out_romask_1189; // @[RegisterRouter.scala:87:24]
wire _out_T_11463 = ~out_womask_1189; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11465 = _out_T_11464; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_1021 = _out_T_11465; // @[RegisterRouter.scala:87:24]
wire out_rimask_1190 = |_out_rimask_T_1190; // @[RegisterRouter.scala:87:24]
wire out_wimask_1190 = &_out_wimask_T_1190; // @[RegisterRouter.scala:87:24]
wire out_romask_1190 = |_out_romask_T_1190; // @[RegisterRouter.scala:87:24]
wire out_womask_1190 = &_out_womask_T_1190; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1190 = out_rivalid_1_1044 & out_rimask_1190; // @[RegisterRouter.scala:87:24]
wire _out_T_11467 = out_f_rivalid_1190; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1190 = out_roready_1_1044 & out_romask_1190; // @[RegisterRouter.scala:87:24]
wire _out_T_11468 = out_f_roready_1190; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1190 = out_wivalid_1_1044 & out_wimask_1190; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1190 = out_woready_1_1044 & out_womask_1190; // @[RegisterRouter.scala:87:24]
wire _out_T_11469 = ~out_rimask_1190; // @[RegisterRouter.scala:87:24]
wire _out_T_11470 = ~out_wimask_1190; // @[RegisterRouter.scala:87:24]
wire _out_T_11471 = ~out_romask_1190; // @[RegisterRouter.scala:87:24]
wire _out_T_11472 = ~out_womask_1190; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_1021 = {hi_146, flags_0_go, _out_prepend_T_1021}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_11473 = out_prepend_1021; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_11474 = _out_T_11473; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_1022 = _out_T_11474; // @[RegisterRouter.scala:87:24]
wire out_rimask_1191 = |_out_rimask_T_1191; // @[RegisterRouter.scala:87:24]
wire out_wimask_1191 = &_out_wimask_T_1191; // @[RegisterRouter.scala:87:24]
wire out_romask_1191 = |_out_romask_T_1191; // @[RegisterRouter.scala:87:24]
wire out_womask_1191 = &_out_womask_T_1191; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1191 = out_rivalid_1_1045 & out_rimask_1191; // @[RegisterRouter.scala:87:24]
wire _out_T_11476 = out_f_rivalid_1191; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1191 = out_roready_1_1045 & out_romask_1191; // @[RegisterRouter.scala:87:24]
wire _out_T_11477 = out_f_roready_1191; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1191 = out_wivalid_1_1045 & out_wimask_1191; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1191 = out_woready_1_1045 & out_womask_1191; // @[RegisterRouter.scala:87:24]
wire _out_T_11478 = ~out_rimask_1191; // @[RegisterRouter.scala:87:24]
wire _out_T_11479 = ~out_wimask_1191; // @[RegisterRouter.scala:87:24]
wire _out_T_11480 = ~out_romask_1191; // @[RegisterRouter.scala:87:24]
wire _out_T_11481 = ~out_womask_1191; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_1022 = {hi_147, flags_0_go, _out_prepend_T_1022}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_11482 = out_prepend_1022; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_11483 = _out_T_11482; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_1023 = _out_T_11483; // @[RegisterRouter.scala:87:24]
wire out_rimask_1192 = |_out_rimask_T_1192; // @[RegisterRouter.scala:87:24]
wire out_wimask_1192 = &_out_wimask_T_1192; // @[RegisterRouter.scala:87:24]
wire out_romask_1192 = |_out_romask_T_1192; // @[RegisterRouter.scala:87:24]
wire out_womask_1192 = &_out_womask_T_1192; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1192 = out_rivalid_1_1046 & out_rimask_1192; // @[RegisterRouter.scala:87:24]
wire _out_T_11485 = out_f_rivalid_1192; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1192 = out_roready_1_1046 & out_romask_1192; // @[RegisterRouter.scala:87:24]
wire _out_T_11486 = out_f_roready_1192; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1192 = out_wivalid_1_1046 & out_wimask_1192; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1192 = out_woready_1_1046 & out_womask_1192; // @[RegisterRouter.scala:87:24]
wire _out_T_11487 = ~out_rimask_1192; // @[RegisterRouter.scala:87:24]
wire _out_T_11488 = ~out_wimask_1192; // @[RegisterRouter.scala:87:24]
wire _out_T_11489 = ~out_romask_1192; // @[RegisterRouter.scala:87:24]
wire _out_T_11490 = ~out_womask_1192; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_1023 = {hi_148, flags_0_go, _out_prepend_T_1023}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_11491 = out_prepend_1023; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_11492 = _out_T_11491; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_1024 = _out_T_11492; // @[RegisterRouter.scala:87:24]
wire out_rimask_1193 = |_out_rimask_T_1193; // @[RegisterRouter.scala:87:24]
wire out_wimask_1193 = &_out_wimask_T_1193; // @[RegisterRouter.scala:87:24]
wire out_romask_1193 = |_out_romask_T_1193; // @[RegisterRouter.scala:87:24]
wire out_womask_1193 = &_out_womask_T_1193; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1193 = out_rivalid_1_1047 & out_rimask_1193; // @[RegisterRouter.scala:87:24]
wire _out_T_11494 = out_f_rivalid_1193; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1193 = out_roready_1_1047 & out_romask_1193; // @[RegisterRouter.scala:87:24]
wire _out_T_11495 = out_f_roready_1193; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1193 = out_wivalid_1_1047 & out_wimask_1193; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1193 = out_woready_1_1047 & out_womask_1193; // @[RegisterRouter.scala:87:24]
wire _out_T_11496 = ~out_rimask_1193; // @[RegisterRouter.scala:87:24]
wire _out_T_11497 = ~out_wimask_1193; // @[RegisterRouter.scala:87:24]
wire _out_T_11498 = ~out_romask_1193; // @[RegisterRouter.scala:87:24]
wire _out_T_11499 = ~out_womask_1193; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_1024 = {hi_149, flags_0_go, _out_prepend_T_1024}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_11500 = out_prepend_1024; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_11501 = _out_T_11500; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_1025 = _out_T_11501; // @[RegisterRouter.scala:87:24]
wire out_rimask_1194 = |_out_rimask_T_1194; // @[RegisterRouter.scala:87:24]
wire out_wimask_1194 = &_out_wimask_T_1194; // @[RegisterRouter.scala:87:24]
wire out_romask_1194 = |_out_romask_T_1194; // @[RegisterRouter.scala:87:24]
wire out_womask_1194 = &_out_womask_T_1194; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1194 = out_rivalid_1_1048 & out_rimask_1194; // @[RegisterRouter.scala:87:24]
wire _out_T_11503 = out_f_rivalid_1194; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1194 = out_roready_1_1048 & out_romask_1194; // @[RegisterRouter.scala:87:24]
wire _out_T_11504 = out_f_roready_1194; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1194 = out_wivalid_1_1048 & out_wimask_1194; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1194 = out_woready_1_1048 & out_womask_1194; // @[RegisterRouter.scala:87:24]
wire _out_T_11505 = ~out_rimask_1194; // @[RegisterRouter.scala:87:24]
wire _out_T_11506 = ~out_wimask_1194; // @[RegisterRouter.scala:87:24]
wire _out_T_11507 = ~out_romask_1194; // @[RegisterRouter.scala:87:24]
wire _out_T_11508 = ~out_womask_1194; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_1025 = {hi_150, flags_0_go, _out_prepend_T_1025}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_11509 = out_prepend_1025; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_11510 = _out_T_11509; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_1026 = _out_T_11510; // @[RegisterRouter.scala:87:24]
wire out_rimask_1195 = |_out_rimask_T_1195; // @[RegisterRouter.scala:87:24]
wire out_wimask_1195 = &_out_wimask_T_1195; // @[RegisterRouter.scala:87:24]
wire out_romask_1195 = |_out_romask_T_1195; // @[RegisterRouter.scala:87:24]
wire out_womask_1195 = &_out_womask_T_1195; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1195 = out_rivalid_1_1049 & out_rimask_1195; // @[RegisterRouter.scala:87:24]
wire _out_T_11512 = out_f_rivalid_1195; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1195 = out_roready_1_1049 & out_romask_1195; // @[RegisterRouter.scala:87:24]
wire _out_T_11513 = out_f_roready_1195; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1195 = out_wivalid_1_1049 & out_wimask_1195; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1195 = out_woready_1_1049 & out_womask_1195; // @[RegisterRouter.scala:87:24]
wire _out_T_11514 = ~out_rimask_1195; // @[RegisterRouter.scala:87:24]
wire _out_T_11515 = ~out_wimask_1195; // @[RegisterRouter.scala:87:24]
wire _out_T_11516 = ~out_romask_1195; // @[RegisterRouter.scala:87:24]
wire _out_T_11517 = ~out_womask_1195; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_1026 = {hi_151, flags_0_go, _out_prepend_T_1026}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_11518 = out_prepend_1026; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_11519 = _out_T_11518; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_1027 = _out_T_11519; // @[RegisterRouter.scala:87:24]
wire out_rimask_1196 = |_out_rimask_T_1196; // @[RegisterRouter.scala:87:24]
wire out_wimask_1196 = &_out_wimask_T_1196; // @[RegisterRouter.scala:87:24]
wire out_romask_1196 = |_out_romask_T_1196; // @[RegisterRouter.scala:87:24]
wire out_womask_1196 = &_out_womask_T_1196; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1196 = out_rivalid_1_1050 & out_rimask_1196; // @[RegisterRouter.scala:87:24]
wire _out_T_11521 = out_f_rivalid_1196; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1196 = out_roready_1_1050 & out_romask_1196; // @[RegisterRouter.scala:87:24]
wire _out_T_11522 = out_f_roready_1196; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1196 = out_wivalid_1_1050 & out_wimask_1196; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1196 = out_woready_1_1050 & out_womask_1196; // @[RegisterRouter.scala:87:24]
wire _out_T_11523 = ~out_rimask_1196; // @[RegisterRouter.scala:87:24]
wire _out_T_11524 = ~out_wimask_1196; // @[RegisterRouter.scala:87:24]
wire _out_T_11525 = ~out_romask_1196; // @[RegisterRouter.scala:87:24]
wire _out_T_11526 = ~out_womask_1196; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_1027 = {hi_152, flags_0_go, _out_prepend_T_1027}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_11527 = out_prepend_1027; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_11528 = _out_T_11527; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_146 = _out_T_11528; // @[MuxLiteral.scala:49:48]
wire out_rimask_1197 = |_out_rimask_T_1197; // @[RegisterRouter.scala:87:24]
wire out_wimask_1197 = &_out_wimask_T_1197; // @[RegisterRouter.scala:87:24]
wire out_romask_1197 = |_out_romask_T_1197; // @[RegisterRouter.scala:87:24]
wire out_womask_1197 = &_out_womask_T_1197; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1197 = out_rivalid_1_1051 & out_rimask_1197; // @[RegisterRouter.scala:87:24]
wire _out_T_11530 = out_f_rivalid_1197; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1197 = out_roready_1_1051 & out_romask_1197; // @[RegisterRouter.scala:87:24]
wire _out_T_11531 = out_f_roready_1197; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1197 = out_wivalid_1_1051 & out_wimask_1197; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1197 = out_woready_1_1051 & out_womask_1197; // @[RegisterRouter.scala:87:24]
wire _out_T_11532 = ~out_rimask_1197; // @[RegisterRouter.scala:87:24]
wire _out_T_11533 = ~out_wimask_1197; // @[RegisterRouter.scala:87:24]
wire _out_T_11534 = ~out_romask_1197; // @[RegisterRouter.scala:87:24]
wire _out_T_11535 = ~out_womask_1197; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11537 = _out_T_11536; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_1028 = _out_T_11537; // @[RegisterRouter.scala:87:24]
wire out_rimask_1198 = |_out_rimask_T_1198; // @[RegisterRouter.scala:87:24]
wire out_wimask_1198 = &_out_wimask_T_1198; // @[RegisterRouter.scala:87:24]
wire out_romask_1198 = |_out_romask_T_1198; // @[RegisterRouter.scala:87:24]
wire out_womask_1198 = &_out_womask_T_1198; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1198 = out_rivalid_1_1052 & out_rimask_1198; // @[RegisterRouter.scala:87:24]
wire _out_T_11539 = out_f_rivalid_1198; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1198 = out_roready_1_1052 & out_romask_1198; // @[RegisterRouter.scala:87:24]
wire _out_T_11540 = out_f_roready_1198; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1198 = out_wivalid_1_1052 & out_wimask_1198; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1198 = out_woready_1_1052 & out_womask_1198; // @[RegisterRouter.scala:87:24]
wire _out_T_11541 = ~out_rimask_1198; // @[RegisterRouter.scala:87:24]
wire _out_T_11542 = ~out_wimask_1198; // @[RegisterRouter.scala:87:24]
wire _out_T_11543 = ~out_romask_1198; // @[RegisterRouter.scala:87:24]
wire _out_T_11544 = ~out_womask_1198; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_1028 = {hi_498, flags_0_go, _out_prepend_T_1028}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_11545 = out_prepend_1028; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_11546 = _out_T_11545; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_1029 = _out_T_11546; // @[RegisterRouter.scala:87:24]
wire out_rimask_1199 = |_out_rimask_T_1199; // @[RegisterRouter.scala:87:24]
wire out_wimask_1199 = &_out_wimask_T_1199; // @[RegisterRouter.scala:87:24]
wire out_romask_1199 = |_out_romask_T_1199; // @[RegisterRouter.scala:87:24]
wire out_womask_1199 = &_out_womask_T_1199; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1199 = out_rivalid_1_1053 & out_rimask_1199; // @[RegisterRouter.scala:87:24]
wire _out_T_11548 = out_f_rivalid_1199; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1199 = out_roready_1_1053 & out_romask_1199; // @[RegisterRouter.scala:87:24]
wire _out_T_11549 = out_f_roready_1199; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1199 = out_wivalid_1_1053 & out_wimask_1199; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1199 = out_woready_1_1053 & out_womask_1199; // @[RegisterRouter.scala:87:24]
wire _out_T_11550 = ~out_rimask_1199; // @[RegisterRouter.scala:87:24]
wire _out_T_11551 = ~out_wimask_1199; // @[RegisterRouter.scala:87:24]
wire _out_T_11552 = ~out_romask_1199; // @[RegisterRouter.scala:87:24]
wire _out_T_11553 = ~out_womask_1199; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_1029 = {hi_499, flags_0_go, _out_prepend_T_1029}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_11554 = out_prepend_1029; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_11555 = _out_T_11554; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_1030 = _out_T_11555; // @[RegisterRouter.scala:87:24]
wire out_rimask_1200 = |_out_rimask_T_1200; // @[RegisterRouter.scala:87:24]
wire out_wimask_1200 = &_out_wimask_T_1200; // @[RegisterRouter.scala:87:24]
wire out_romask_1200 = |_out_romask_T_1200; // @[RegisterRouter.scala:87:24]
wire out_womask_1200 = &_out_womask_T_1200; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1200 = out_rivalid_1_1054 & out_rimask_1200; // @[RegisterRouter.scala:87:24]
wire _out_T_11557 = out_f_rivalid_1200; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1200 = out_roready_1_1054 & out_romask_1200; // @[RegisterRouter.scala:87:24]
wire _out_T_11558 = out_f_roready_1200; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1200 = out_wivalid_1_1054 & out_wimask_1200; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1200 = out_woready_1_1054 & out_womask_1200; // @[RegisterRouter.scala:87:24]
wire _out_T_11559 = ~out_rimask_1200; // @[RegisterRouter.scala:87:24]
wire _out_T_11560 = ~out_wimask_1200; // @[RegisterRouter.scala:87:24]
wire _out_T_11561 = ~out_romask_1200; // @[RegisterRouter.scala:87:24]
wire _out_T_11562 = ~out_womask_1200; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_1030 = {hi_500, flags_0_go, _out_prepend_T_1030}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_11563 = out_prepend_1030; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_11564 = _out_T_11563; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_1031 = _out_T_11564; // @[RegisterRouter.scala:87:24]
wire out_rimask_1201 = |_out_rimask_T_1201; // @[RegisterRouter.scala:87:24]
wire out_wimask_1201 = &_out_wimask_T_1201; // @[RegisterRouter.scala:87:24]
wire out_romask_1201 = |_out_romask_T_1201; // @[RegisterRouter.scala:87:24]
wire out_womask_1201 = &_out_womask_T_1201; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1201 = out_rivalid_1_1055 & out_rimask_1201; // @[RegisterRouter.scala:87:24]
wire _out_T_11566 = out_f_rivalid_1201; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1201 = out_roready_1_1055 & out_romask_1201; // @[RegisterRouter.scala:87:24]
wire _out_T_11567 = out_f_roready_1201; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1201 = out_wivalid_1_1055 & out_wimask_1201; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1201 = out_woready_1_1055 & out_womask_1201; // @[RegisterRouter.scala:87:24]
wire _out_T_11568 = ~out_rimask_1201; // @[RegisterRouter.scala:87:24]
wire _out_T_11569 = ~out_wimask_1201; // @[RegisterRouter.scala:87:24]
wire _out_T_11570 = ~out_romask_1201; // @[RegisterRouter.scala:87:24]
wire _out_T_11571 = ~out_womask_1201; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_1031 = {hi_501, flags_0_go, _out_prepend_T_1031}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_11572 = out_prepend_1031; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_11573 = _out_T_11572; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_1032 = _out_T_11573; // @[RegisterRouter.scala:87:24]
wire out_rimask_1202 = |_out_rimask_T_1202; // @[RegisterRouter.scala:87:24]
wire out_wimask_1202 = &_out_wimask_T_1202; // @[RegisterRouter.scala:87:24]
wire out_romask_1202 = |_out_romask_T_1202; // @[RegisterRouter.scala:87:24]
wire out_womask_1202 = &_out_womask_T_1202; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1202 = out_rivalid_1_1056 & out_rimask_1202; // @[RegisterRouter.scala:87:24]
wire _out_T_11575 = out_f_rivalid_1202; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1202 = out_roready_1_1056 & out_romask_1202; // @[RegisterRouter.scala:87:24]
wire _out_T_11576 = out_f_roready_1202; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1202 = out_wivalid_1_1056 & out_wimask_1202; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1202 = out_woready_1_1056 & out_womask_1202; // @[RegisterRouter.scala:87:24]
wire _out_T_11577 = ~out_rimask_1202; // @[RegisterRouter.scala:87:24]
wire _out_T_11578 = ~out_wimask_1202; // @[RegisterRouter.scala:87:24]
wire _out_T_11579 = ~out_romask_1202; // @[RegisterRouter.scala:87:24]
wire _out_T_11580 = ~out_womask_1202; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_1032 = {hi_502, flags_0_go, _out_prepend_T_1032}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_11581 = out_prepend_1032; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_11582 = _out_T_11581; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_1033 = _out_T_11582; // @[RegisterRouter.scala:87:24]
wire out_rimask_1203 = |_out_rimask_T_1203; // @[RegisterRouter.scala:87:24]
wire out_wimask_1203 = &_out_wimask_T_1203; // @[RegisterRouter.scala:87:24]
wire out_romask_1203 = |_out_romask_T_1203; // @[RegisterRouter.scala:87:24]
wire out_womask_1203 = &_out_womask_T_1203; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1203 = out_rivalid_1_1057 & out_rimask_1203; // @[RegisterRouter.scala:87:24]
wire _out_T_11584 = out_f_rivalid_1203; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1203 = out_roready_1_1057 & out_romask_1203; // @[RegisterRouter.scala:87:24]
wire _out_T_11585 = out_f_roready_1203; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1203 = out_wivalid_1_1057 & out_wimask_1203; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1203 = out_woready_1_1057 & out_womask_1203; // @[RegisterRouter.scala:87:24]
wire _out_T_11586 = ~out_rimask_1203; // @[RegisterRouter.scala:87:24]
wire _out_T_11587 = ~out_wimask_1203; // @[RegisterRouter.scala:87:24]
wire _out_T_11588 = ~out_romask_1203; // @[RegisterRouter.scala:87:24]
wire _out_T_11589 = ~out_womask_1203; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_1033 = {hi_503, flags_0_go, _out_prepend_T_1033}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_11590 = out_prepend_1033; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_11591 = _out_T_11590; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_1034 = _out_T_11591; // @[RegisterRouter.scala:87:24]
wire out_rimask_1204 = |_out_rimask_T_1204; // @[RegisterRouter.scala:87:24]
wire out_wimask_1204 = &_out_wimask_T_1204; // @[RegisterRouter.scala:87:24]
wire out_romask_1204 = |_out_romask_T_1204; // @[RegisterRouter.scala:87:24]
wire out_womask_1204 = &_out_womask_T_1204; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1204 = out_rivalid_1_1058 & out_rimask_1204; // @[RegisterRouter.scala:87:24]
wire _out_T_11593 = out_f_rivalid_1204; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1204 = out_roready_1_1058 & out_romask_1204; // @[RegisterRouter.scala:87:24]
wire _out_T_11594 = out_f_roready_1204; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1204 = out_wivalid_1_1058 & out_wimask_1204; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1204 = out_woready_1_1058 & out_womask_1204; // @[RegisterRouter.scala:87:24]
wire _out_T_11595 = ~out_rimask_1204; // @[RegisterRouter.scala:87:24]
wire _out_T_11596 = ~out_wimask_1204; // @[RegisterRouter.scala:87:24]
wire _out_T_11597 = ~out_romask_1204; // @[RegisterRouter.scala:87:24]
wire _out_T_11598 = ~out_womask_1204; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_1034 = {hi_504, flags_0_go, _out_prepend_T_1034}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_11599 = out_prepend_1034; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_11600 = _out_T_11599; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_190 = _out_T_11600; // @[MuxLiteral.scala:49:48]
wire out_rimask_1205 = |_out_rimask_T_1205; // @[RegisterRouter.scala:87:24]
wire out_wimask_1205 = &_out_wimask_T_1205; // @[RegisterRouter.scala:87:24]
wire out_romask_1205 = |_out_romask_T_1205; // @[RegisterRouter.scala:87:24]
wire out_womask_1205 = &_out_womask_T_1205; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1205 = out_rivalid_1_1059 & out_rimask_1205; // @[RegisterRouter.scala:87:24]
wire _out_T_11602 = out_f_rivalid_1205; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1205 = out_roready_1_1059 & out_romask_1205; // @[RegisterRouter.scala:87:24]
wire _out_T_11603 = out_f_roready_1205; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1205 = out_wivalid_1_1059 & out_wimask_1205; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1205 = out_woready_1_1059 & out_womask_1205; // @[RegisterRouter.scala:87:24]
wire _out_T_11604 = ~out_rimask_1205; // @[RegisterRouter.scala:87:24]
wire _out_T_11605 = ~out_wimask_1205; // @[RegisterRouter.scala:87:24]
wire _out_T_11606 = ~out_romask_1205; // @[RegisterRouter.scala:87:24]
wire _out_T_11607 = ~out_womask_1205; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11609 = _out_T_11608; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_1035 = _out_T_11609; // @[RegisterRouter.scala:87:24]
wire out_rimask_1206 = |_out_rimask_T_1206; // @[RegisterRouter.scala:87:24]
wire out_wimask_1206 = &_out_wimask_T_1206; // @[RegisterRouter.scala:87:24]
wire out_romask_1206 = |_out_romask_T_1206; // @[RegisterRouter.scala:87:24]
wire out_womask_1206 = &_out_womask_T_1206; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1206 = out_rivalid_1_1060 & out_rimask_1206; // @[RegisterRouter.scala:87:24]
wire _out_T_11611 = out_f_rivalid_1206; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1206 = out_roready_1_1060 & out_romask_1206; // @[RegisterRouter.scala:87:24]
wire _out_T_11612 = out_f_roready_1206; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1206 = out_wivalid_1_1060 & out_wimask_1206; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1206 = out_woready_1_1060 & out_womask_1206; // @[RegisterRouter.scala:87:24]
wire _out_T_11613 = ~out_rimask_1206; // @[RegisterRouter.scala:87:24]
wire _out_T_11614 = ~out_wimask_1206; // @[RegisterRouter.scala:87:24]
wire _out_T_11615 = ~out_romask_1206; // @[RegisterRouter.scala:87:24]
wire _out_T_11616 = ~out_womask_1206; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_1035 = {hi_442, flags_0_go, _out_prepend_T_1035}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_11617 = out_prepend_1035; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_11618 = _out_T_11617; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_1036 = _out_T_11618; // @[RegisterRouter.scala:87:24]
wire out_rimask_1207 = |_out_rimask_T_1207; // @[RegisterRouter.scala:87:24]
wire out_wimask_1207 = &_out_wimask_T_1207; // @[RegisterRouter.scala:87:24]
wire out_romask_1207 = |_out_romask_T_1207; // @[RegisterRouter.scala:87:24]
wire out_womask_1207 = &_out_womask_T_1207; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1207 = out_rivalid_1_1061 & out_rimask_1207; // @[RegisterRouter.scala:87:24]
wire _out_T_11620 = out_f_rivalid_1207; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1207 = out_roready_1_1061 & out_romask_1207; // @[RegisterRouter.scala:87:24]
wire _out_T_11621 = out_f_roready_1207; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1207 = out_wivalid_1_1061 & out_wimask_1207; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1207 = out_woready_1_1061 & out_womask_1207; // @[RegisterRouter.scala:87:24]
wire _out_T_11622 = ~out_rimask_1207; // @[RegisterRouter.scala:87:24]
wire _out_T_11623 = ~out_wimask_1207; // @[RegisterRouter.scala:87:24]
wire _out_T_11624 = ~out_romask_1207; // @[RegisterRouter.scala:87:24]
wire _out_T_11625 = ~out_womask_1207; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_1036 = {hi_443, flags_0_go, _out_prepend_T_1036}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_11626 = out_prepend_1036; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_11627 = _out_T_11626; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_1037 = _out_T_11627; // @[RegisterRouter.scala:87:24]
wire out_rimask_1208 = |_out_rimask_T_1208; // @[RegisterRouter.scala:87:24]
wire out_wimask_1208 = &_out_wimask_T_1208; // @[RegisterRouter.scala:87:24]
wire out_romask_1208 = |_out_romask_T_1208; // @[RegisterRouter.scala:87:24]
wire out_womask_1208 = &_out_womask_T_1208; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1208 = out_rivalid_1_1062 & out_rimask_1208; // @[RegisterRouter.scala:87:24]
wire _out_T_11629 = out_f_rivalid_1208; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1208 = out_roready_1_1062 & out_romask_1208; // @[RegisterRouter.scala:87:24]
wire _out_T_11630 = out_f_roready_1208; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1208 = out_wivalid_1_1062 & out_wimask_1208; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1208 = out_woready_1_1062 & out_womask_1208; // @[RegisterRouter.scala:87:24]
wire _out_T_11631 = ~out_rimask_1208; // @[RegisterRouter.scala:87:24]
wire _out_T_11632 = ~out_wimask_1208; // @[RegisterRouter.scala:87:24]
wire _out_T_11633 = ~out_romask_1208; // @[RegisterRouter.scala:87:24]
wire _out_T_11634 = ~out_womask_1208; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_1037 = {hi_444, flags_0_go, _out_prepend_T_1037}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_11635 = out_prepend_1037; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_11636 = _out_T_11635; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_1038 = _out_T_11636; // @[RegisterRouter.scala:87:24]
wire out_rimask_1209 = |_out_rimask_T_1209; // @[RegisterRouter.scala:87:24]
wire out_wimask_1209 = &_out_wimask_T_1209; // @[RegisterRouter.scala:87:24]
wire out_romask_1209 = |_out_romask_T_1209; // @[RegisterRouter.scala:87:24]
wire out_womask_1209 = &_out_womask_T_1209; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1209 = out_rivalid_1_1063 & out_rimask_1209; // @[RegisterRouter.scala:87:24]
wire _out_T_11638 = out_f_rivalid_1209; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1209 = out_roready_1_1063 & out_romask_1209; // @[RegisterRouter.scala:87:24]
wire _out_T_11639 = out_f_roready_1209; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1209 = out_wivalid_1_1063 & out_wimask_1209; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1209 = out_woready_1_1063 & out_womask_1209; // @[RegisterRouter.scala:87:24]
wire _out_T_11640 = ~out_rimask_1209; // @[RegisterRouter.scala:87:24]
wire _out_T_11641 = ~out_wimask_1209; // @[RegisterRouter.scala:87:24]
wire _out_T_11642 = ~out_romask_1209; // @[RegisterRouter.scala:87:24]
wire _out_T_11643 = ~out_womask_1209; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_1038 = {hi_445, flags_0_go, _out_prepend_T_1038}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_11644 = out_prepend_1038; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_11645 = _out_T_11644; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_1039 = _out_T_11645; // @[RegisterRouter.scala:87:24]
wire out_rimask_1210 = |_out_rimask_T_1210; // @[RegisterRouter.scala:87:24]
wire out_wimask_1210 = &_out_wimask_T_1210; // @[RegisterRouter.scala:87:24]
wire out_romask_1210 = |_out_romask_T_1210; // @[RegisterRouter.scala:87:24]
wire out_womask_1210 = &_out_womask_T_1210; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1210 = out_rivalid_1_1064 & out_rimask_1210; // @[RegisterRouter.scala:87:24]
wire _out_T_11647 = out_f_rivalid_1210; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1210 = out_roready_1_1064 & out_romask_1210; // @[RegisterRouter.scala:87:24]
wire _out_T_11648 = out_f_roready_1210; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1210 = out_wivalid_1_1064 & out_wimask_1210; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1210 = out_woready_1_1064 & out_womask_1210; // @[RegisterRouter.scala:87:24]
wire _out_T_11649 = ~out_rimask_1210; // @[RegisterRouter.scala:87:24]
wire _out_T_11650 = ~out_wimask_1210; // @[RegisterRouter.scala:87:24]
wire _out_T_11651 = ~out_romask_1210; // @[RegisterRouter.scala:87:24]
wire _out_T_11652 = ~out_womask_1210; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_1039 = {hi_446, flags_0_go, _out_prepend_T_1039}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_11653 = out_prepend_1039; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_11654 = _out_T_11653; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_1040 = _out_T_11654; // @[RegisterRouter.scala:87:24]
wire out_rimask_1211 = |_out_rimask_T_1211; // @[RegisterRouter.scala:87:24]
wire out_wimask_1211 = &_out_wimask_T_1211; // @[RegisterRouter.scala:87:24]
wire out_romask_1211 = |_out_romask_T_1211; // @[RegisterRouter.scala:87:24]
wire out_womask_1211 = &_out_womask_T_1211; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1211 = out_rivalid_1_1065 & out_rimask_1211; // @[RegisterRouter.scala:87:24]
wire _out_T_11656 = out_f_rivalid_1211; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1211 = out_roready_1_1065 & out_romask_1211; // @[RegisterRouter.scala:87:24]
wire _out_T_11657 = out_f_roready_1211; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1211 = out_wivalid_1_1065 & out_wimask_1211; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1211 = out_woready_1_1065 & out_womask_1211; // @[RegisterRouter.scala:87:24]
wire _out_T_11658 = ~out_rimask_1211; // @[RegisterRouter.scala:87:24]
wire _out_T_11659 = ~out_wimask_1211; // @[RegisterRouter.scala:87:24]
wire _out_T_11660 = ~out_romask_1211; // @[RegisterRouter.scala:87:24]
wire _out_T_11661 = ~out_womask_1211; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_1040 = {hi_447, flags_0_go, _out_prepend_T_1040}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_11662 = out_prepend_1040; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_11663 = _out_T_11662; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_1041 = _out_T_11663; // @[RegisterRouter.scala:87:24]
wire out_rimask_1212 = |_out_rimask_T_1212; // @[RegisterRouter.scala:87:24]
wire out_wimask_1212 = &_out_wimask_T_1212; // @[RegisterRouter.scala:87:24]
wire out_romask_1212 = |_out_romask_T_1212; // @[RegisterRouter.scala:87:24]
wire out_womask_1212 = &_out_womask_T_1212; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1212 = out_rivalid_1_1066 & out_rimask_1212; // @[RegisterRouter.scala:87:24]
wire _out_T_11665 = out_f_rivalid_1212; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1212 = out_roready_1_1066 & out_romask_1212; // @[RegisterRouter.scala:87:24]
wire _out_T_11666 = out_f_roready_1212; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1212 = out_wivalid_1_1066 & out_wimask_1212; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1212 = out_woready_1_1066 & out_womask_1212; // @[RegisterRouter.scala:87:24]
wire _out_T_11667 = ~out_rimask_1212; // @[RegisterRouter.scala:87:24]
wire _out_T_11668 = ~out_wimask_1212; // @[RegisterRouter.scala:87:24]
wire _out_T_11669 = ~out_romask_1212; // @[RegisterRouter.scala:87:24]
wire _out_T_11670 = ~out_womask_1212; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_1041 = {hi_448, flags_0_go, _out_prepend_T_1041}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_11671 = out_prepend_1041; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_11672 = _out_T_11671; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_183 = _out_T_11672; // @[MuxLiteral.scala:49:48]
wire out_rimask_1213 = |_out_rimask_T_1213; // @[RegisterRouter.scala:87:24]
wire out_wimask_1213 = &_out_wimask_T_1213; // @[RegisterRouter.scala:87:24]
wire out_romask_1213 = |_out_romask_T_1213; // @[RegisterRouter.scala:87:24]
wire out_womask_1213 = &_out_womask_T_1213; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1213 = out_rivalid_1_1067 & out_rimask_1213; // @[RegisterRouter.scala:87:24]
wire _out_T_11674 = out_f_rivalid_1213; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1213 = out_roready_1_1067 & out_romask_1213; // @[RegisterRouter.scala:87:24]
wire _out_T_11675 = out_f_roready_1213; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1213 = out_wivalid_1_1067 & out_wimask_1213; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1213 = out_woready_1_1067 & out_womask_1213; // @[RegisterRouter.scala:87:24]
wire _out_T_11676 = ~out_rimask_1213; // @[RegisterRouter.scala:87:24]
wire _out_T_11677 = ~out_wimask_1213; // @[RegisterRouter.scala:87:24]
wire _out_T_11678 = ~out_romask_1213; // @[RegisterRouter.scala:87:24]
wire _out_T_11679 = ~out_womask_1213; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11681 = _out_T_11680; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_1042 = _out_T_11681; // @[RegisterRouter.scala:87:24]
wire out_rimask_1214 = |_out_rimask_T_1214; // @[RegisterRouter.scala:87:24]
wire out_wimask_1214 = &_out_wimask_T_1214; // @[RegisterRouter.scala:87:24]
wire out_romask_1214 = |_out_romask_T_1214; // @[RegisterRouter.scala:87:24]
wire out_womask_1214 = &_out_womask_T_1214; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1214 = out_rivalid_1_1068 & out_rimask_1214; // @[RegisterRouter.scala:87:24]
wire _out_T_11683 = out_f_rivalid_1214; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1214 = out_roready_1_1068 & out_romask_1214; // @[RegisterRouter.scala:87:24]
wire _out_T_11684 = out_f_roready_1214; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1214 = out_wivalid_1_1068 & out_wimask_1214; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1214 = out_woready_1_1068 & out_womask_1214; // @[RegisterRouter.scala:87:24]
wire _out_T_11685 = ~out_rimask_1214; // @[RegisterRouter.scala:87:24]
wire _out_T_11686 = ~out_wimask_1214; // @[RegisterRouter.scala:87:24]
wire _out_T_11687 = ~out_romask_1214; // @[RegisterRouter.scala:87:24]
wire _out_T_11688 = ~out_womask_1214; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_1042 = {hi_322, flags_0_go, _out_prepend_T_1042}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_11689 = out_prepend_1042; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_11690 = _out_T_11689; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_1043 = _out_T_11690; // @[RegisterRouter.scala:87:24]
wire out_rimask_1215 = |_out_rimask_T_1215; // @[RegisterRouter.scala:87:24]
wire out_wimask_1215 = &_out_wimask_T_1215; // @[RegisterRouter.scala:87:24]
wire out_romask_1215 = |_out_romask_T_1215; // @[RegisterRouter.scala:87:24]
wire out_womask_1215 = &_out_womask_T_1215; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1215 = out_rivalid_1_1069 & out_rimask_1215; // @[RegisterRouter.scala:87:24]
wire _out_T_11692 = out_f_rivalid_1215; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1215 = out_roready_1_1069 & out_romask_1215; // @[RegisterRouter.scala:87:24]
wire _out_T_11693 = out_f_roready_1215; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1215 = out_wivalid_1_1069 & out_wimask_1215; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1215 = out_woready_1_1069 & out_womask_1215; // @[RegisterRouter.scala:87:24]
wire _out_T_11694 = ~out_rimask_1215; // @[RegisterRouter.scala:87:24]
wire _out_T_11695 = ~out_wimask_1215; // @[RegisterRouter.scala:87:24]
wire _out_T_11696 = ~out_romask_1215; // @[RegisterRouter.scala:87:24]
wire _out_T_11697 = ~out_womask_1215; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_1043 = {hi_323, flags_0_go, _out_prepend_T_1043}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_11698 = out_prepend_1043; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_11699 = _out_T_11698; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_1044 = _out_T_11699; // @[RegisterRouter.scala:87:24]
wire out_rimask_1216 = |_out_rimask_T_1216; // @[RegisterRouter.scala:87:24]
wire out_wimask_1216 = &_out_wimask_T_1216; // @[RegisterRouter.scala:87:24]
wire out_romask_1216 = |_out_romask_T_1216; // @[RegisterRouter.scala:87:24]
wire out_womask_1216 = &_out_womask_T_1216; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1216 = out_rivalid_1_1070 & out_rimask_1216; // @[RegisterRouter.scala:87:24]
wire _out_T_11701 = out_f_rivalid_1216; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1216 = out_roready_1_1070 & out_romask_1216; // @[RegisterRouter.scala:87:24]
wire _out_T_11702 = out_f_roready_1216; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1216 = out_wivalid_1_1070 & out_wimask_1216; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1216 = out_woready_1_1070 & out_womask_1216; // @[RegisterRouter.scala:87:24]
wire _out_T_11703 = ~out_rimask_1216; // @[RegisterRouter.scala:87:24]
wire _out_T_11704 = ~out_wimask_1216; // @[RegisterRouter.scala:87:24]
wire _out_T_11705 = ~out_romask_1216; // @[RegisterRouter.scala:87:24]
wire _out_T_11706 = ~out_womask_1216; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_1044 = {hi_324, flags_0_go, _out_prepend_T_1044}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_11707 = out_prepend_1044; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_11708 = _out_T_11707; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_1045 = _out_T_11708; // @[RegisterRouter.scala:87:24]
wire out_rimask_1217 = |_out_rimask_T_1217; // @[RegisterRouter.scala:87:24]
wire out_wimask_1217 = &_out_wimask_T_1217; // @[RegisterRouter.scala:87:24]
wire out_romask_1217 = |_out_romask_T_1217; // @[RegisterRouter.scala:87:24]
wire out_womask_1217 = &_out_womask_T_1217; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1217 = out_rivalid_1_1071 & out_rimask_1217; // @[RegisterRouter.scala:87:24]
wire _out_T_11710 = out_f_rivalid_1217; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1217 = out_roready_1_1071 & out_romask_1217; // @[RegisterRouter.scala:87:24]
wire _out_T_11711 = out_f_roready_1217; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1217 = out_wivalid_1_1071 & out_wimask_1217; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1217 = out_woready_1_1071 & out_womask_1217; // @[RegisterRouter.scala:87:24]
wire _out_T_11712 = ~out_rimask_1217; // @[RegisterRouter.scala:87:24]
wire _out_T_11713 = ~out_wimask_1217; // @[RegisterRouter.scala:87:24]
wire _out_T_11714 = ~out_romask_1217; // @[RegisterRouter.scala:87:24]
wire _out_T_11715 = ~out_womask_1217; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_1045 = {hi_325, flags_0_go, _out_prepend_T_1045}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_11716 = out_prepend_1045; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_11717 = _out_T_11716; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_1046 = _out_T_11717; // @[RegisterRouter.scala:87:24]
wire out_rimask_1218 = |_out_rimask_T_1218; // @[RegisterRouter.scala:87:24]
wire out_wimask_1218 = &_out_wimask_T_1218; // @[RegisterRouter.scala:87:24]
wire out_romask_1218 = |_out_romask_T_1218; // @[RegisterRouter.scala:87:24]
wire out_womask_1218 = &_out_womask_T_1218; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1218 = out_rivalid_1_1072 & out_rimask_1218; // @[RegisterRouter.scala:87:24]
wire _out_T_11719 = out_f_rivalid_1218; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1218 = out_roready_1_1072 & out_romask_1218; // @[RegisterRouter.scala:87:24]
wire _out_T_11720 = out_f_roready_1218; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1218 = out_wivalid_1_1072 & out_wimask_1218; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1218 = out_woready_1_1072 & out_womask_1218; // @[RegisterRouter.scala:87:24]
wire _out_T_11721 = ~out_rimask_1218; // @[RegisterRouter.scala:87:24]
wire _out_T_11722 = ~out_wimask_1218; // @[RegisterRouter.scala:87:24]
wire _out_T_11723 = ~out_romask_1218; // @[RegisterRouter.scala:87:24]
wire _out_T_11724 = ~out_womask_1218; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_1046 = {hi_326, flags_0_go, _out_prepend_T_1046}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_11725 = out_prepend_1046; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_11726 = _out_T_11725; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_1047 = _out_T_11726; // @[RegisterRouter.scala:87:24]
wire out_rimask_1219 = |_out_rimask_T_1219; // @[RegisterRouter.scala:87:24]
wire out_wimask_1219 = &_out_wimask_T_1219; // @[RegisterRouter.scala:87:24]
wire out_romask_1219 = |_out_romask_T_1219; // @[RegisterRouter.scala:87:24]
wire out_womask_1219 = &_out_womask_T_1219; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1219 = out_rivalid_1_1073 & out_rimask_1219; // @[RegisterRouter.scala:87:24]
wire _out_T_11728 = out_f_rivalid_1219; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1219 = out_roready_1_1073 & out_romask_1219; // @[RegisterRouter.scala:87:24]
wire _out_T_11729 = out_f_roready_1219; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1219 = out_wivalid_1_1073 & out_wimask_1219; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1219 = out_woready_1_1073 & out_womask_1219; // @[RegisterRouter.scala:87:24]
wire _out_T_11730 = ~out_rimask_1219; // @[RegisterRouter.scala:87:24]
wire _out_T_11731 = ~out_wimask_1219; // @[RegisterRouter.scala:87:24]
wire _out_T_11732 = ~out_romask_1219; // @[RegisterRouter.scala:87:24]
wire _out_T_11733 = ~out_womask_1219; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_1047 = {hi_327, flags_0_go, _out_prepend_T_1047}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_11734 = out_prepend_1047; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_11735 = _out_T_11734; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_1048 = _out_T_11735; // @[RegisterRouter.scala:87:24]
wire out_rimask_1220 = |_out_rimask_T_1220; // @[RegisterRouter.scala:87:24]
wire out_wimask_1220 = &_out_wimask_T_1220; // @[RegisterRouter.scala:87:24]
wire out_romask_1220 = |_out_romask_T_1220; // @[RegisterRouter.scala:87:24]
wire out_womask_1220 = &_out_womask_T_1220; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1220 = out_rivalid_1_1074 & out_rimask_1220; // @[RegisterRouter.scala:87:24]
wire _out_T_11737 = out_f_rivalid_1220; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1220 = out_roready_1_1074 & out_romask_1220; // @[RegisterRouter.scala:87:24]
wire _out_T_11738 = out_f_roready_1220; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1220 = out_wivalid_1_1074 & out_wimask_1220; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1220 = out_woready_1_1074 & out_womask_1220; // @[RegisterRouter.scala:87:24]
wire _out_T_11739 = ~out_rimask_1220; // @[RegisterRouter.scala:87:24]
wire _out_T_11740 = ~out_wimask_1220; // @[RegisterRouter.scala:87:24]
wire _out_T_11741 = ~out_romask_1220; // @[RegisterRouter.scala:87:24]
wire _out_T_11742 = ~out_womask_1220; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_1048 = {hi_328, flags_0_go, _out_prepend_T_1048}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_11743 = out_prepend_1048; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_11744 = _out_T_11743; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_168 = _out_T_11744; // @[MuxLiteral.scala:49:48]
wire out_rimask_1221 = |_out_rimask_T_1221; // @[RegisterRouter.scala:87:24]
wire out_wimask_1221 = &_out_wimask_T_1221; // @[RegisterRouter.scala:87:24]
wire out_romask_1221 = |_out_romask_T_1221; // @[RegisterRouter.scala:87:24]
wire out_womask_1221 = &_out_womask_T_1221; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1221 = out_rivalid_1_1075 & out_rimask_1221; // @[RegisterRouter.scala:87:24]
wire _out_T_11746 = out_f_rivalid_1221; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1221 = out_roready_1_1075 & out_romask_1221; // @[RegisterRouter.scala:87:24]
wire _out_T_11747 = out_f_roready_1221; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1221 = out_wivalid_1_1075 & out_wimask_1221; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1221 = out_woready_1_1075 & out_womask_1221; // @[RegisterRouter.scala:87:24]
wire _out_T_11748 = ~out_rimask_1221; // @[RegisterRouter.scala:87:24]
wire _out_T_11749 = ~out_wimask_1221; // @[RegisterRouter.scala:87:24]
wire _out_T_11750 = ~out_romask_1221; // @[RegisterRouter.scala:87:24]
wire _out_T_11751 = ~out_womask_1221; // @[RegisterRouter.scala:87:24]
wire out_rimask_1222 = |_out_rimask_T_1222; // @[RegisterRouter.scala:87:24]
wire out_wimask_1222 = &_out_wimask_T_1222; // @[RegisterRouter.scala:87:24]
wire out_romask_1222 = |_out_romask_T_1222; // @[RegisterRouter.scala:87:24]
wire out_womask_1222 = &_out_womask_T_1222; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1222 = out_rivalid_1_1076 & out_rimask_1222; // @[RegisterRouter.scala:87:24]
wire _out_T_11755 = out_f_rivalid_1222; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1222 = out_roready_1_1076 & out_romask_1222; // @[RegisterRouter.scala:87:24]
wire _out_T_11756 = out_f_roready_1222; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1222 = out_wivalid_1_1076 & out_wimask_1222; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1222 = out_woready_1_1076 & out_womask_1222; // @[RegisterRouter.scala:87:24]
wire _out_T_11757 = ~out_rimask_1222; // @[RegisterRouter.scala:87:24]
wire _out_T_11758 = ~out_wimask_1222; // @[RegisterRouter.scala:87:24]
wire _out_T_11759 = ~out_romask_1222; // @[RegisterRouter.scala:87:24]
wire _out_T_11760 = ~out_womask_1222; // @[RegisterRouter.scala:87:24]
wire out_rimask_1223 = |_out_rimask_T_1223; // @[RegisterRouter.scala:87:24]
wire out_wimask_1223 = &_out_wimask_T_1223; // @[RegisterRouter.scala:87:24]
wire out_romask_1223 = |_out_romask_T_1223; // @[RegisterRouter.scala:87:24]
wire out_womask_1223 = &_out_womask_T_1223; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1223 = out_rivalid_1_1077 & out_rimask_1223; // @[RegisterRouter.scala:87:24]
wire _out_T_11764 = out_f_rivalid_1223; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1223 = out_roready_1_1077 & out_romask_1223; // @[RegisterRouter.scala:87:24]
wire _out_T_11765 = out_f_roready_1223; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1223 = out_wivalid_1_1077 & out_wimask_1223; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1223 = out_woready_1_1077 & out_womask_1223; // @[RegisterRouter.scala:87:24]
wire _out_T_11766 = ~out_rimask_1223; // @[RegisterRouter.scala:87:24]
wire _out_T_11767 = ~out_wimask_1223; // @[RegisterRouter.scala:87:24]
wire _out_T_11768 = ~out_romask_1223; // @[RegisterRouter.scala:87:24]
wire _out_T_11769 = ~out_womask_1223; // @[RegisterRouter.scala:87:24]
wire out_rimask_1224 = |_out_rimask_T_1224; // @[RegisterRouter.scala:87:24]
wire out_wimask_1224 = &_out_wimask_T_1224; // @[RegisterRouter.scala:87:24]
wire out_romask_1224 = |_out_romask_T_1224; // @[RegisterRouter.scala:87:24]
wire out_womask_1224 = &_out_womask_T_1224; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1224 = out_rivalid_1_1078 & out_rimask_1224; // @[RegisterRouter.scala:87:24]
wire _out_T_11773 = out_f_rivalid_1224; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1224 = out_roready_1_1078 & out_romask_1224; // @[RegisterRouter.scala:87:24]
wire _out_T_11774 = out_f_roready_1224; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1224 = out_wivalid_1_1078 & out_wimask_1224; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1224 = out_woready_1_1078 & out_womask_1224; // @[RegisterRouter.scala:87:24]
wire _out_T_11775 = ~out_rimask_1224; // @[RegisterRouter.scala:87:24]
wire _out_T_11776 = ~out_wimask_1224; // @[RegisterRouter.scala:87:24]
wire _out_T_11777 = ~out_romask_1224; // @[RegisterRouter.scala:87:24]
wire _out_T_11778 = ~out_womask_1224; // @[RegisterRouter.scala:87:24]
wire out_rimask_1225 = |_out_rimask_T_1225; // @[RegisterRouter.scala:87:24]
wire out_wimask_1225 = &_out_wimask_T_1225; // @[RegisterRouter.scala:87:24]
wire out_romask_1225 = |_out_romask_T_1225; // @[RegisterRouter.scala:87:24]
wire out_womask_1225 = &_out_womask_T_1225; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1225 = out_rivalid_1_1079 & out_rimask_1225; // @[RegisterRouter.scala:87:24]
wire _out_T_11782 = out_f_rivalid_1225; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1225 = out_roready_1_1079 & out_romask_1225; // @[RegisterRouter.scala:87:24]
wire _out_T_11783 = out_f_roready_1225; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1225 = out_wivalid_1_1079 & out_wimask_1225; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1225 = out_woready_1_1079 & out_womask_1225; // @[RegisterRouter.scala:87:24]
wire _out_T_11784 = ~out_rimask_1225; // @[RegisterRouter.scala:87:24]
wire _out_T_11785 = ~out_wimask_1225; // @[RegisterRouter.scala:87:24]
wire _out_T_11786 = ~out_romask_1225; // @[RegisterRouter.scala:87:24]
wire _out_T_11787 = ~out_womask_1225; // @[RegisterRouter.scala:87:24]
wire out_rimask_1226 = |_out_rimask_T_1226; // @[RegisterRouter.scala:87:24]
wire out_wimask_1226 = &_out_wimask_T_1226; // @[RegisterRouter.scala:87:24]
wire out_romask_1226 = |_out_romask_T_1226; // @[RegisterRouter.scala:87:24]
wire out_womask_1226 = &_out_womask_T_1226; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1226 = out_rivalid_1_1080 & out_rimask_1226; // @[RegisterRouter.scala:87:24]
wire _out_T_11791 = out_f_rivalid_1226; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1226 = out_roready_1_1080 & out_romask_1226; // @[RegisterRouter.scala:87:24]
wire _out_T_11792 = out_f_roready_1226; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1226 = out_wivalid_1_1080 & out_wimask_1226; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1226 = out_woready_1_1080 & out_womask_1226; // @[RegisterRouter.scala:87:24]
wire _out_T_11793 = ~out_rimask_1226; // @[RegisterRouter.scala:87:24]
wire _out_T_11794 = ~out_wimask_1226; // @[RegisterRouter.scala:87:24]
wire _out_T_11795 = ~out_romask_1226; // @[RegisterRouter.scala:87:24]
wire _out_T_11796 = ~out_womask_1226; // @[RegisterRouter.scala:87:24]
wire out_rimask_1227 = |_out_rimask_T_1227; // @[RegisterRouter.scala:87:24]
wire out_wimask_1227 = &_out_wimask_T_1227; // @[RegisterRouter.scala:87:24]
wire out_romask_1227 = |_out_romask_T_1227; // @[RegisterRouter.scala:87:24]
wire out_womask_1227 = &_out_womask_T_1227; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1227 = out_rivalid_1_1081 & out_rimask_1227; // @[RegisterRouter.scala:87:24]
wire _out_T_11800 = out_f_rivalid_1227; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1227 = out_roready_1_1081 & out_romask_1227; // @[RegisterRouter.scala:87:24]
wire _out_T_11801 = out_f_roready_1227; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1227 = out_wivalid_1_1081 & out_wimask_1227; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1227 = out_woready_1_1081 & out_womask_1227; // @[RegisterRouter.scala:87:24]
wire _out_T_11802 = ~out_rimask_1227; // @[RegisterRouter.scala:87:24]
wire _out_T_11803 = ~out_wimask_1227; // @[RegisterRouter.scala:87:24]
wire _out_T_11804 = ~out_romask_1227; // @[RegisterRouter.scala:87:24]
wire _out_T_11805 = ~out_womask_1227; // @[RegisterRouter.scala:87:24]
wire out_rimask_1228 = |_out_rimask_T_1228; // @[RegisterRouter.scala:87:24]
wire out_wimask_1228 = &_out_wimask_T_1228; // @[RegisterRouter.scala:87:24]
wire out_romask_1228 = |_out_romask_T_1228; // @[RegisterRouter.scala:87:24]
wire out_womask_1228 = &_out_womask_T_1228; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1228 = out_rivalid_1_1082 & out_rimask_1228; // @[RegisterRouter.scala:87:24]
wire _out_T_11809 = out_f_rivalid_1228; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1228 = out_roready_1_1082 & out_romask_1228; // @[RegisterRouter.scala:87:24]
wire _out_T_11810 = out_f_roready_1228; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1228 = out_wivalid_1_1082 & out_wimask_1228; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1228 = out_woready_1_1082 & out_womask_1228; // @[RegisterRouter.scala:87:24]
wire _out_T_11811 = ~out_rimask_1228; // @[RegisterRouter.scala:87:24]
wire _out_T_11812 = ~out_wimask_1228; // @[RegisterRouter.scala:87:24]
wire _out_T_11813 = ~out_romask_1228; // @[RegisterRouter.scala:87:24]
wire _out_T_11814 = ~out_womask_1228; // @[RegisterRouter.scala:87:24]
wire out_rimask_1229 = |_out_rimask_T_1229; // @[RegisterRouter.scala:87:24]
wire out_wimask_1229 = &_out_wimask_T_1229; // @[RegisterRouter.scala:87:24]
wire out_romask_1229 = |_out_romask_T_1229; // @[RegisterRouter.scala:87:24]
wire out_womask_1229 = &_out_womask_T_1229; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1229 = out_rivalid_1_1083 & out_rimask_1229; // @[RegisterRouter.scala:87:24]
wire _out_T_11818 = out_f_rivalid_1229; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1229 = out_roready_1_1083 & out_romask_1229; // @[RegisterRouter.scala:87:24]
wire _out_T_11819 = out_f_roready_1229; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1229 = out_wivalid_1_1083 & out_wimask_1229; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1229 = out_woready_1_1083 & out_womask_1229; // @[RegisterRouter.scala:87:24]
wire _out_T_11820 = ~out_rimask_1229; // @[RegisterRouter.scala:87:24]
wire _out_T_11821 = ~out_wimask_1229; // @[RegisterRouter.scala:87:24]
wire _out_T_11822 = ~out_romask_1229; // @[RegisterRouter.scala:87:24]
wire _out_T_11823 = ~out_womask_1229; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11825 = _out_T_11824; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_1056 = _out_T_11825; // @[RegisterRouter.scala:87:24]
wire out_rimask_1230 = |_out_rimask_T_1230; // @[RegisterRouter.scala:87:24]
wire out_wimask_1230 = &_out_wimask_T_1230; // @[RegisterRouter.scala:87:24]
wire out_romask_1230 = |_out_romask_T_1230; // @[RegisterRouter.scala:87:24]
wire out_womask_1230 = &_out_womask_T_1230; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1230 = out_rivalid_1_1084 & out_rimask_1230; // @[RegisterRouter.scala:87:24]
wire _out_T_11827 = out_f_rivalid_1230; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1230 = out_roready_1_1084 & out_romask_1230; // @[RegisterRouter.scala:87:24]
wire _out_T_11828 = out_f_roready_1230; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1230 = out_wivalid_1_1084 & out_wimask_1230; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1230 = out_woready_1_1084 & out_womask_1230; // @[RegisterRouter.scala:87:24]
wire _out_T_11829 = ~out_rimask_1230; // @[RegisterRouter.scala:87:24]
wire _out_T_11830 = ~out_wimask_1230; // @[RegisterRouter.scala:87:24]
wire _out_T_11831 = ~out_romask_1230; // @[RegisterRouter.scala:87:24]
wire _out_T_11832 = ~out_womask_1230; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_1056 = {hi_658, flags_0_go, _out_prepend_T_1056}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_11833 = out_prepend_1056; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_11834 = _out_T_11833; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_1057 = _out_T_11834; // @[RegisterRouter.scala:87:24]
wire out_rimask_1231 = |_out_rimask_T_1231; // @[RegisterRouter.scala:87:24]
wire out_wimask_1231 = &_out_wimask_T_1231; // @[RegisterRouter.scala:87:24]
wire out_romask_1231 = |_out_romask_T_1231; // @[RegisterRouter.scala:87:24]
wire out_womask_1231 = &_out_womask_T_1231; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1231 = out_rivalid_1_1085 & out_rimask_1231; // @[RegisterRouter.scala:87:24]
wire _out_T_11836 = out_f_rivalid_1231; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1231 = out_roready_1_1085 & out_romask_1231; // @[RegisterRouter.scala:87:24]
wire _out_T_11837 = out_f_roready_1231; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1231 = out_wivalid_1_1085 & out_wimask_1231; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1231 = out_woready_1_1085 & out_womask_1231; // @[RegisterRouter.scala:87:24]
wire _out_T_11838 = ~out_rimask_1231; // @[RegisterRouter.scala:87:24]
wire _out_T_11839 = ~out_wimask_1231; // @[RegisterRouter.scala:87:24]
wire _out_T_11840 = ~out_romask_1231; // @[RegisterRouter.scala:87:24]
wire _out_T_11841 = ~out_womask_1231; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_1057 = {hi_659, flags_0_go, _out_prepend_T_1057}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_11842 = out_prepend_1057; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_11843 = _out_T_11842; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_1058 = _out_T_11843; // @[RegisterRouter.scala:87:24]
wire out_rimask_1232 = |_out_rimask_T_1232; // @[RegisterRouter.scala:87:24]
wire out_wimask_1232 = &_out_wimask_T_1232; // @[RegisterRouter.scala:87:24]
wire out_romask_1232 = |_out_romask_T_1232; // @[RegisterRouter.scala:87:24]
wire out_womask_1232 = &_out_womask_T_1232; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1232 = out_rivalid_1_1086 & out_rimask_1232; // @[RegisterRouter.scala:87:24]
wire _out_T_11845 = out_f_rivalid_1232; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1232 = out_roready_1_1086 & out_romask_1232; // @[RegisterRouter.scala:87:24]
wire _out_T_11846 = out_f_roready_1232; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1232 = out_wivalid_1_1086 & out_wimask_1232; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1232 = out_woready_1_1086 & out_womask_1232; // @[RegisterRouter.scala:87:24]
wire _out_T_11847 = ~out_rimask_1232; // @[RegisterRouter.scala:87:24]
wire _out_T_11848 = ~out_wimask_1232; // @[RegisterRouter.scala:87:24]
wire _out_T_11849 = ~out_romask_1232; // @[RegisterRouter.scala:87:24]
wire _out_T_11850 = ~out_womask_1232; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_1058 = {hi_660, flags_0_go, _out_prepend_T_1058}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_11851 = out_prepend_1058; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_11852 = _out_T_11851; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_1059 = _out_T_11852; // @[RegisterRouter.scala:87:24]
wire out_rimask_1233 = |_out_rimask_T_1233; // @[RegisterRouter.scala:87:24]
wire out_wimask_1233 = &_out_wimask_T_1233; // @[RegisterRouter.scala:87:24]
wire out_romask_1233 = |_out_romask_T_1233; // @[RegisterRouter.scala:87:24]
wire out_womask_1233 = &_out_womask_T_1233; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1233 = out_rivalid_1_1087 & out_rimask_1233; // @[RegisterRouter.scala:87:24]
wire _out_T_11854 = out_f_rivalid_1233; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1233 = out_roready_1_1087 & out_romask_1233; // @[RegisterRouter.scala:87:24]
wire _out_T_11855 = out_f_roready_1233; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1233 = out_wivalid_1_1087 & out_wimask_1233; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1233 = out_woready_1_1087 & out_womask_1233; // @[RegisterRouter.scala:87:24]
wire _out_T_11856 = ~out_rimask_1233; // @[RegisterRouter.scala:87:24]
wire _out_T_11857 = ~out_wimask_1233; // @[RegisterRouter.scala:87:24]
wire _out_T_11858 = ~out_romask_1233; // @[RegisterRouter.scala:87:24]
wire _out_T_11859 = ~out_womask_1233; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_1059 = {hi_661, flags_0_go, _out_prepend_T_1059}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_11860 = out_prepend_1059; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_11861 = _out_T_11860; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_1060 = _out_T_11861; // @[RegisterRouter.scala:87:24]
wire out_rimask_1234 = |_out_rimask_T_1234; // @[RegisterRouter.scala:87:24]
wire out_wimask_1234 = &_out_wimask_T_1234; // @[RegisterRouter.scala:87:24]
wire out_romask_1234 = |_out_romask_T_1234; // @[RegisterRouter.scala:87:24]
wire out_womask_1234 = &_out_womask_T_1234; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1234 = out_rivalid_1_1088 & out_rimask_1234; // @[RegisterRouter.scala:87:24]
wire _out_T_11863 = out_f_rivalid_1234; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1234 = out_roready_1_1088 & out_romask_1234; // @[RegisterRouter.scala:87:24]
wire _out_T_11864 = out_f_roready_1234; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1234 = out_wivalid_1_1088 & out_wimask_1234; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1234 = out_woready_1_1088 & out_womask_1234; // @[RegisterRouter.scala:87:24]
wire _out_T_11865 = ~out_rimask_1234; // @[RegisterRouter.scala:87:24]
wire _out_T_11866 = ~out_wimask_1234; // @[RegisterRouter.scala:87:24]
wire _out_T_11867 = ~out_romask_1234; // @[RegisterRouter.scala:87:24]
wire _out_T_11868 = ~out_womask_1234; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_1060 = {hi_662, flags_0_go, _out_prepend_T_1060}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_11869 = out_prepend_1060; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_11870 = _out_T_11869; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_1061 = _out_T_11870; // @[RegisterRouter.scala:87:24]
wire out_rimask_1235 = |_out_rimask_T_1235; // @[RegisterRouter.scala:87:24]
wire out_wimask_1235 = &_out_wimask_T_1235; // @[RegisterRouter.scala:87:24]
wire out_romask_1235 = |_out_romask_T_1235; // @[RegisterRouter.scala:87:24]
wire out_womask_1235 = &_out_womask_T_1235; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1235 = out_rivalid_1_1089 & out_rimask_1235; // @[RegisterRouter.scala:87:24]
wire _out_T_11872 = out_f_rivalid_1235; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1235 = out_roready_1_1089 & out_romask_1235; // @[RegisterRouter.scala:87:24]
wire _out_T_11873 = out_f_roready_1235; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1235 = out_wivalid_1_1089 & out_wimask_1235; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1235 = out_woready_1_1089 & out_womask_1235; // @[RegisterRouter.scala:87:24]
wire _out_T_11874 = ~out_rimask_1235; // @[RegisterRouter.scala:87:24]
wire _out_T_11875 = ~out_wimask_1235; // @[RegisterRouter.scala:87:24]
wire _out_T_11876 = ~out_romask_1235; // @[RegisterRouter.scala:87:24]
wire _out_T_11877 = ~out_womask_1235; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_1061 = {hi_663, flags_0_go, _out_prepend_T_1061}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_11878 = out_prepend_1061; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_11879 = _out_T_11878; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_1062 = _out_T_11879; // @[RegisterRouter.scala:87:24]
wire out_rimask_1236 = |_out_rimask_T_1236; // @[RegisterRouter.scala:87:24]
wire out_wimask_1236 = &_out_wimask_T_1236; // @[RegisterRouter.scala:87:24]
wire out_romask_1236 = |_out_romask_T_1236; // @[RegisterRouter.scala:87:24]
wire out_womask_1236 = &_out_womask_T_1236; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1236 = out_rivalid_1_1090 & out_rimask_1236; // @[RegisterRouter.scala:87:24]
wire _out_T_11881 = out_f_rivalid_1236; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1236 = out_roready_1_1090 & out_romask_1236; // @[RegisterRouter.scala:87:24]
wire _out_T_11882 = out_f_roready_1236; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1236 = out_wivalid_1_1090 & out_wimask_1236; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1236 = out_woready_1_1090 & out_womask_1236; // @[RegisterRouter.scala:87:24]
wire _out_T_11883 = ~out_rimask_1236; // @[RegisterRouter.scala:87:24]
wire _out_T_11884 = ~out_wimask_1236; // @[RegisterRouter.scala:87:24]
wire _out_T_11885 = ~out_romask_1236; // @[RegisterRouter.scala:87:24]
wire _out_T_11886 = ~out_womask_1236; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_1062 = {hi_664, flags_0_go, _out_prepend_T_1062}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_11887 = out_prepend_1062; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_11888 = _out_T_11887; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_210 = _out_T_11888; // @[MuxLiteral.scala:49:48]
wire out_rimask_1237 = |_out_rimask_T_1237; // @[RegisterRouter.scala:87:24]
wire out_wimask_1237 = &_out_wimask_T_1237; // @[RegisterRouter.scala:87:24]
wire out_romask_1237 = |_out_romask_T_1237; // @[RegisterRouter.scala:87:24]
wire out_womask_1237 = &_out_womask_T_1237; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1237 = out_rivalid_1_1091 & out_rimask_1237; // @[RegisterRouter.scala:87:24]
wire _out_T_11890 = out_f_rivalid_1237; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1237 = out_roready_1_1091 & out_romask_1237; // @[RegisterRouter.scala:87:24]
wire _out_T_11891 = out_f_roready_1237; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1237 = out_wivalid_1_1091 & out_wimask_1237; // @[RegisterRouter.scala:87:24]
wire _out_T_11892 = out_f_wivalid_1237; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1237 = out_woready_1_1091 & out_womask_1237; // @[RegisterRouter.scala:87:24]
wire _out_T_11893 = out_f_woready_1237; // @[RegisterRouter.scala:87:24]
wire _out_T_11894 = ~out_rimask_1237; // @[RegisterRouter.scala:87:24]
wire _out_T_11895 = ~out_wimask_1237; // @[RegisterRouter.scala:87:24]
wire _out_T_11896 = ~out_romask_1237; // @[RegisterRouter.scala:87:24]
wire _out_T_11897 = ~out_womask_1237; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11899 = _out_T_11898; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_1063 = _out_T_11899; // @[RegisterRouter.scala:87:24]
wire out_rimask_1238 = |_out_rimask_T_1238; // @[RegisterRouter.scala:87:24]
wire out_wimask_1238 = &_out_wimask_T_1238; // @[RegisterRouter.scala:87:24]
wire out_romask_1238 = |_out_romask_T_1238; // @[RegisterRouter.scala:87:24]
wire out_womask_1238 = &_out_womask_T_1238; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1238 = out_rivalid_1_1092 & out_rimask_1238; // @[RegisterRouter.scala:87:24]
wire _out_T_11901 = out_f_rivalid_1238; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1238 = out_roready_1_1092 & out_romask_1238; // @[RegisterRouter.scala:87:24]
wire _out_T_11902 = out_f_roready_1238; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1238 = out_wivalid_1_1092 & out_wimask_1238; // @[RegisterRouter.scala:87:24]
wire _out_T_11903 = out_f_wivalid_1238; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1238 = out_woready_1_1092 & out_womask_1238; // @[RegisterRouter.scala:87:24]
wire _out_T_11904 = out_f_woready_1238; // @[RegisterRouter.scala:87:24]
wire _out_T_11905 = ~out_rimask_1238; // @[RegisterRouter.scala:87:24]
wire _out_T_11906 = ~out_wimask_1238; // @[RegisterRouter.scala:87:24]
wire _out_T_11907 = ~out_romask_1238; // @[RegisterRouter.scala:87:24]
wire _out_T_11908 = ~out_womask_1238; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_1063 = {programBufferMem_25, _out_prepend_T_1063}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_11909 = out_prepend_1063; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_11910 = _out_T_11909; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_1064 = _out_T_11910; // @[RegisterRouter.scala:87:24]
wire out_rimask_1239 = |_out_rimask_T_1239; // @[RegisterRouter.scala:87:24]
wire out_wimask_1239 = &_out_wimask_T_1239; // @[RegisterRouter.scala:87:24]
wire out_romask_1239 = |_out_romask_T_1239; // @[RegisterRouter.scala:87:24]
wire out_womask_1239 = &_out_womask_T_1239; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1239 = out_rivalid_1_1093 & out_rimask_1239; // @[RegisterRouter.scala:87:24]
wire _out_T_11912 = out_f_rivalid_1239; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1239 = out_roready_1_1093 & out_romask_1239; // @[RegisterRouter.scala:87:24]
wire _out_T_11913 = out_f_roready_1239; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1239 = out_wivalid_1_1093 & out_wimask_1239; // @[RegisterRouter.scala:87:24]
wire _out_T_11914 = out_f_wivalid_1239; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1239 = out_woready_1_1093 & out_womask_1239; // @[RegisterRouter.scala:87:24]
wire _out_T_11915 = out_f_woready_1239; // @[RegisterRouter.scala:87:24]
wire _out_T_11916 = ~out_rimask_1239; // @[RegisterRouter.scala:87:24]
wire _out_T_11917 = ~out_wimask_1239; // @[RegisterRouter.scala:87:24]
wire _out_T_11918 = ~out_romask_1239; // @[RegisterRouter.scala:87:24]
wire _out_T_11919 = ~out_womask_1239; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_1064 = {programBufferMem_26, _out_prepend_T_1064}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_11920 = out_prepend_1064; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_11921 = _out_T_11920; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_1065 = _out_T_11921; // @[RegisterRouter.scala:87:24]
wire out_rimask_1240 = |_out_rimask_T_1240; // @[RegisterRouter.scala:87:24]
wire out_wimask_1240 = &_out_wimask_T_1240; // @[RegisterRouter.scala:87:24]
wire out_romask_1240 = |_out_romask_T_1240; // @[RegisterRouter.scala:87:24]
wire out_womask_1240 = &_out_womask_T_1240; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1240 = out_rivalid_1_1094 & out_rimask_1240; // @[RegisterRouter.scala:87:24]
wire _out_T_11923 = out_f_rivalid_1240; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1240 = out_roready_1_1094 & out_romask_1240; // @[RegisterRouter.scala:87:24]
wire _out_T_11924 = out_f_roready_1240; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1240 = out_wivalid_1_1094 & out_wimask_1240; // @[RegisterRouter.scala:87:24]
wire _out_T_11925 = out_f_wivalid_1240; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1240 = out_woready_1_1094 & out_womask_1240; // @[RegisterRouter.scala:87:24]
wire _out_T_11926 = out_f_woready_1240; // @[RegisterRouter.scala:87:24]
wire _out_T_11927 = ~out_rimask_1240; // @[RegisterRouter.scala:87:24]
wire _out_T_11928 = ~out_wimask_1240; // @[RegisterRouter.scala:87:24]
wire _out_T_11929 = ~out_romask_1240; // @[RegisterRouter.scala:87:24]
wire _out_T_11930 = ~out_womask_1240; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_1065 = {programBufferMem_27, _out_prepend_T_1065}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_11931 = out_prepend_1065; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_11932 = _out_T_11931; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_1066 = _out_T_11932; // @[RegisterRouter.scala:87:24]
wire out_rimask_1241 = |_out_rimask_T_1241; // @[RegisterRouter.scala:87:24]
wire out_wimask_1241 = &_out_wimask_T_1241; // @[RegisterRouter.scala:87:24]
wire out_romask_1241 = |_out_romask_T_1241; // @[RegisterRouter.scala:87:24]
wire out_womask_1241 = &_out_womask_T_1241; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1241 = out_rivalid_1_1095 & out_rimask_1241; // @[RegisterRouter.scala:87:24]
wire _out_T_11934 = out_f_rivalid_1241; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1241 = out_roready_1_1095 & out_romask_1241; // @[RegisterRouter.scala:87:24]
wire _out_T_11935 = out_f_roready_1241; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1241 = out_wivalid_1_1095 & out_wimask_1241; // @[RegisterRouter.scala:87:24]
wire _out_T_11936 = out_f_wivalid_1241; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1241 = out_woready_1_1095 & out_womask_1241; // @[RegisterRouter.scala:87:24]
wire _out_T_11937 = out_f_woready_1241; // @[RegisterRouter.scala:87:24]
wire _out_T_11938 = ~out_rimask_1241; // @[RegisterRouter.scala:87:24]
wire _out_T_11939 = ~out_wimask_1241; // @[RegisterRouter.scala:87:24]
wire _out_T_11940 = ~out_romask_1241; // @[RegisterRouter.scala:87:24]
wire _out_T_11941 = ~out_womask_1241; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_1066 = {programBufferMem_28, _out_prepend_T_1066}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_11942 = out_prepend_1066; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_11943 = _out_T_11942; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_1067 = _out_T_11943; // @[RegisterRouter.scala:87:24]
wire out_rimask_1242 = |_out_rimask_T_1242; // @[RegisterRouter.scala:87:24]
wire out_wimask_1242 = &_out_wimask_T_1242; // @[RegisterRouter.scala:87:24]
wire out_romask_1242 = |_out_romask_T_1242; // @[RegisterRouter.scala:87:24]
wire out_womask_1242 = &_out_womask_T_1242; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1242 = out_rivalid_1_1096 & out_rimask_1242; // @[RegisterRouter.scala:87:24]
wire _out_T_11945 = out_f_rivalid_1242; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1242 = out_roready_1_1096 & out_romask_1242; // @[RegisterRouter.scala:87:24]
wire _out_T_11946 = out_f_roready_1242; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1242 = out_wivalid_1_1096 & out_wimask_1242; // @[RegisterRouter.scala:87:24]
wire _out_T_11947 = out_f_wivalid_1242; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1242 = out_woready_1_1096 & out_womask_1242; // @[RegisterRouter.scala:87:24]
wire _out_T_11948 = out_f_woready_1242; // @[RegisterRouter.scala:87:24]
wire _out_T_11949 = ~out_rimask_1242; // @[RegisterRouter.scala:87:24]
wire _out_T_11950 = ~out_wimask_1242; // @[RegisterRouter.scala:87:24]
wire _out_T_11951 = ~out_romask_1242; // @[RegisterRouter.scala:87:24]
wire _out_T_11952 = ~out_womask_1242; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_1067 = {programBufferMem_29, _out_prepend_T_1067}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_11953 = out_prepend_1067; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_11954 = _out_T_11953; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_1068 = _out_T_11954; // @[RegisterRouter.scala:87:24]
wire out_rimask_1243 = |_out_rimask_T_1243; // @[RegisterRouter.scala:87:24]
wire out_wimask_1243 = &_out_wimask_T_1243; // @[RegisterRouter.scala:87:24]
wire out_romask_1243 = |_out_romask_T_1243; // @[RegisterRouter.scala:87:24]
wire out_womask_1243 = &_out_womask_T_1243; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1243 = out_rivalid_1_1097 & out_rimask_1243; // @[RegisterRouter.scala:87:24]
wire _out_T_11956 = out_f_rivalid_1243; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1243 = out_roready_1_1097 & out_romask_1243; // @[RegisterRouter.scala:87:24]
wire _out_T_11957 = out_f_roready_1243; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1243 = out_wivalid_1_1097 & out_wimask_1243; // @[RegisterRouter.scala:87:24]
wire _out_T_11958 = out_f_wivalid_1243; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1243 = out_woready_1_1097 & out_womask_1243; // @[RegisterRouter.scala:87:24]
wire _out_T_11959 = out_f_woready_1243; // @[RegisterRouter.scala:87:24]
wire _out_T_11960 = ~out_rimask_1243; // @[RegisterRouter.scala:87:24]
wire _out_T_11961 = ~out_wimask_1243; // @[RegisterRouter.scala:87:24]
wire _out_T_11962 = ~out_romask_1243; // @[RegisterRouter.scala:87:24]
wire _out_T_11963 = ~out_womask_1243; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_1068 = {programBufferMem_30, _out_prepend_T_1068}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_11964 = out_prepend_1068; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_11965 = _out_T_11964; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_1069 = _out_T_11965; // @[RegisterRouter.scala:87:24]
wire out_rimask_1244 = |_out_rimask_T_1244; // @[RegisterRouter.scala:87:24]
wire out_wimask_1244 = &_out_wimask_T_1244; // @[RegisterRouter.scala:87:24]
wire out_romask_1244 = |_out_romask_T_1244; // @[RegisterRouter.scala:87:24]
wire out_womask_1244 = &_out_womask_T_1244; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1244 = out_rivalid_1_1098 & out_rimask_1244; // @[RegisterRouter.scala:87:24]
wire _out_T_11967 = out_f_rivalid_1244; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1244 = out_roready_1_1098 & out_romask_1244; // @[RegisterRouter.scala:87:24]
wire _out_T_11968 = out_f_roready_1244; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1244 = out_wivalid_1_1098 & out_wimask_1244; // @[RegisterRouter.scala:87:24]
wire _out_T_11969 = out_f_wivalid_1244; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1244 = out_woready_1_1098 & out_womask_1244; // @[RegisterRouter.scala:87:24]
wire _out_T_11970 = out_f_woready_1244; // @[RegisterRouter.scala:87:24]
wire _out_T_11971 = ~out_rimask_1244; // @[RegisterRouter.scala:87:24]
wire _out_T_11972 = ~out_wimask_1244; // @[RegisterRouter.scala:87:24]
wire _out_T_11973 = ~out_romask_1244; // @[RegisterRouter.scala:87:24]
wire _out_T_11974 = ~out_womask_1244; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_1069 = {programBufferMem_31, _out_prepend_T_1069}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_11975 = out_prepend_1069; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_11976 = _out_T_11975; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_107 = _out_T_11976; // @[MuxLiteral.scala:49:48]
wire out_rimask_1245 = |_out_rimask_T_1245; // @[RegisterRouter.scala:87:24]
wire out_wimask_1245 = &_out_wimask_T_1245; // @[RegisterRouter.scala:87:24]
wire out_romask_1245 = |_out_romask_T_1245; // @[RegisterRouter.scala:87:24]
wire out_womask_1245 = &_out_womask_T_1245; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1245 = out_rivalid_1_1099 & out_rimask_1245; // @[RegisterRouter.scala:87:24]
wire _out_T_11978 = out_f_rivalid_1245; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1245 = out_roready_1_1099 & out_romask_1245; // @[RegisterRouter.scala:87:24]
wire _out_T_11979 = out_f_roready_1245; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1245 = out_wivalid_1_1099 & out_wimask_1245; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1245 = out_woready_1_1099 & out_womask_1245; // @[RegisterRouter.scala:87:24]
wire _out_T_11980 = ~out_rimask_1245; // @[RegisterRouter.scala:87:24]
wire _out_T_11981 = ~out_wimask_1245; // @[RegisterRouter.scala:87:24]
wire _out_T_11982 = ~out_romask_1245; // @[RegisterRouter.scala:87:24]
wire _out_T_11983 = ~out_womask_1245; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_11985 = _out_T_11984; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_1070 = _out_T_11985; // @[RegisterRouter.scala:87:24]
wire out_rimask_1246 = |_out_rimask_T_1246; // @[RegisterRouter.scala:87:24]
wire out_wimask_1246 = &_out_wimask_T_1246; // @[RegisterRouter.scala:87:24]
wire out_romask_1246 = |_out_romask_T_1246; // @[RegisterRouter.scala:87:24]
wire out_womask_1246 = &_out_womask_T_1246; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1246 = out_rivalid_1_1100 & out_rimask_1246; // @[RegisterRouter.scala:87:24]
wire _out_T_11987 = out_f_rivalid_1246; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1246 = out_roready_1_1100 & out_romask_1246; // @[RegisterRouter.scala:87:24]
wire _out_T_11988 = out_f_roready_1246; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1246 = out_wivalid_1_1100 & out_wimask_1246; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1246 = out_woready_1_1100 & out_womask_1246; // @[RegisterRouter.scala:87:24]
wire _out_T_11989 = ~out_rimask_1246; // @[RegisterRouter.scala:87:24]
wire _out_T_11990 = ~out_wimask_1246; // @[RegisterRouter.scala:87:24]
wire _out_T_11991 = ~out_romask_1246; // @[RegisterRouter.scala:87:24]
wire _out_T_11992 = ~out_womask_1246; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_1070 = {hi_66, flags_0_go, _out_prepend_T_1070}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_11993 = out_prepend_1070; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_11994 = _out_T_11993; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_1071 = _out_T_11994; // @[RegisterRouter.scala:87:24]
wire out_rimask_1247 = |_out_rimask_T_1247; // @[RegisterRouter.scala:87:24]
wire out_wimask_1247 = &_out_wimask_T_1247; // @[RegisterRouter.scala:87:24]
wire out_romask_1247 = |_out_romask_T_1247; // @[RegisterRouter.scala:87:24]
wire out_womask_1247 = &_out_womask_T_1247; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1247 = out_rivalid_1_1101 & out_rimask_1247; // @[RegisterRouter.scala:87:24]
wire _out_T_11996 = out_f_rivalid_1247; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1247 = out_roready_1_1101 & out_romask_1247; // @[RegisterRouter.scala:87:24]
wire _out_T_11997 = out_f_roready_1247; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1247 = out_wivalid_1_1101 & out_wimask_1247; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1247 = out_woready_1_1101 & out_womask_1247; // @[RegisterRouter.scala:87:24]
wire _out_T_11998 = ~out_rimask_1247; // @[RegisterRouter.scala:87:24]
wire _out_T_11999 = ~out_wimask_1247; // @[RegisterRouter.scala:87:24]
wire _out_T_12000 = ~out_romask_1247; // @[RegisterRouter.scala:87:24]
wire _out_T_12001 = ~out_womask_1247; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_1071 = {hi_67, flags_0_go, _out_prepend_T_1071}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_12002 = out_prepend_1071; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_12003 = _out_T_12002; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_1072 = _out_T_12003; // @[RegisterRouter.scala:87:24]
wire out_rimask_1248 = |_out_rimask_T_1248; // @[RegisterRouter.scala:87:24]
wire out_wimask_1248 = &_out_wimask_T_1248; // @[RegisterRouter.scala:87:24]
wire out_romask_1248 = |_out_romask_T_1248; // @[RegisterRouter.scala:87:24]
wire out_womask_1248 = &_out_womask_T_1248; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1248 = out_rivalid_1_1102 & out_rimask_1248; // @[RegisterRouter.scala:87:24]
wire _out_T_12005 = out_f_rivalid_1248; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1248 = out_roready_1_1102 & out_romask_1248; // @[RegisterRouter.scala:87:24]
wire _out_T_12006 = out_f_roready_1248; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1248 = out_wivalid_1_1102 & out_wimask_1248; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1248 = out_woready_1_1102 & out_womask_1248; // @[RegisterRouter.scala:87:24]
wire _out_T_12007 = ~out_rimask_1248; // @[RegisterRouter.scala:87:24]
wire _out_T_12008 = ~out_wimask_1248; // @[RegisterRouter.scala:87:24]
wire _out_T_12009 = ~out_romask_1248; // @[RegisterRouter.scala:87:24]
wire _out_T_12010 = ~out_womask_1248; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_1072 = {hi_68, flags_0_go, _out_prepend_T_1072}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_12011 = out_prepend_1072; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_12012 = _out_T_12011; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_1073 = _out_T_12012; // @[RegisterRouter.scala:87:24]
wire out_rimask_1249 = |_out_rimask_T_1249; // @[RegisterRouter.scala:87:24]
wire out_wimask_1249 = &_out_wimask_T_1249; // @[RegisterRouter.scala:87:24]
wire out_romask_1249 = |_out_romask_T_1249; // @[RegisterRouter.scala:87:24]
wire out_womask_1249 = &_out_womask_T_1249; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1249 = out_rivalid_1_1103 & out_rimask_1249; // @[RegisterRouter.scala:87:24]
wire _out_T_12014 = out_f_rivalid_1249; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1249 = out_roready_1_1103 & out_romask_1249; // @[RegisterRouter.scala:87:24]
wire _out_T_12015 = out_f_roready_1249; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1249 = out_wivalid_1_1103 & out_wimask_1249; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1249 = out_woready_1_1103 & out_womask_1249; // @[RegisterRouter.scala:87:24]
wire _out_T_12016 = ~out_rimask_1249; // @[RegisterRouter.scala:87:24]
wire _out_T_12017 = ~out_wimask_1249; // @[RegisterRouter.scala:87:24]
wire _out_T_12018 = ~out_romask_1249; // @[RegisterRouter.scala:87:24]
wire _out_T_12019 = ~out_womask_1249; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_1073 = {hi_69, flags_0_go, _out_prepend_T_1073}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_12020 = out_prepend_1073; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_12021 = _out_T_12020; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_1074 = _out_T_12021; // @[RegisterRouter.scala:87:24]
wire out_rimask_1250 = |_out_rimask_T_1250; // @[RegisterRouter.scala:87:24]
wire out_wimask_1250 = &_out_wimask_T_1250; // @[RegisterRouter.scala:87:24]
wire out_romask_1250 = |_out_romask_T_1250; // @[RegisterRouter.scala:87:24]
wire out_womask_1250 = &_out_womask_T_1250; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1250 = out_rivalid_1_1104 & out_rimask_1250; // @[RegisterRouter.scala:87:24]
wire _out_T_12023 = out_f_rivalid_1250; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1250 = out_roready_1_1104 & out_romask_1250; // @[RegisterRouter.scala:87:24]
wire _out_T_12024 = out_f_roready_1250; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1250 = out_wivalid_1_1104 & out_wimask_1250; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1250 = out_woready_1_1104 & out_womask_1250; // @[RegisterRouter.scala:87:24]
wire _out_T_12025 = ~out_rimask_1250; // @[RegisterRouter.scala:87:24]
wire _out_T_12026 = ~out_wimask_1250; // @[RegisterRouter.scala:87:24]
wire _out_T_12027 = ~out_romask_1250; // @[RegisterRouter.scala:87:24]
wire _out_T_12028 = ~out_womask_1250; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_1074 = {hi_70, flags_0_go, _out_prepend_T_1074}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_12029 = out_prepend_1074; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_12030 = _out_T_12029; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_1075 = _out_T_12030; // @[RegisterRouter.scala:87:24]
wire out_rimask_1251 = |_out_rimask_T_1251; // @[RegisterRouter.scala:87:24]
wire out_wimask_1251 = &_out_wimask_T_1251; // @[RegisterRouter.scala:87:24]
wire out_romask_1251 = |_out_romask_T_1251; // @[RegisterRouter.scala:87:24]
wire out_womask_1251 = &_out_womask_T_1251; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1251 = out_rivalid_1_1105 & out_rimask_1251; // @[RegisterRouter.scala:87:24]
wire _out_T_12032 = out_f_rivalid_1251; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1251 = out_roready_1_1105 & out_romask_1251; // @[RegisterRouter.scala:87:24]
wire _out_T_12033 = out_f_roready_1251; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1251 = out_wivalid_1_1105 & out_wimask_1251; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1251 = out_woready_1_1105 & out_womask_1251; // @[RegisterRouter.scala:87:24]
wire _out_T_12034 = ~out_rimask_1251; // @[RegisterRouter.scala:87:24]
wire _out_T_12035 = ~out_wimask_1251; // @[RegisterRouter.scala:87:24]
wire _out_T_12036 = ~out_romask_1251; // @[RegisterRouter.scala:87:24]
wire _out_T_12037 = ~out_womask_1251; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_1075 = {hi_71, flags_0_go, _out_prepend_T_1075}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_12038 = out_prepend_1075; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_12039 = _out_T_12038; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_1076 = _out_T_12039; // @[RegisterRouter.scala:87:24]
wire out_rimask_1252 = |_out_rimask_T_1252; // @[RegisterRouter.scala:87:24]
wire out_wimask_1252 = &_out_wimask_T_1252; // @[RegisterRouter.scala:87:24]
wire out_romask_1252 = |_out_romask_T_1252; // @[RegisterRouter.scala:87:24]
wire out_womask_1252 = &_out_womask_T_1252; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1252 = out_rivalid_1_1106 & out_rimask_1252; // @[RegisterRouter.scala:87:24]
wire _out_T_12041 = out_f_rivalid_1252; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1252 = out_roready_1_1106 & out_romask_1252; // @[RegisterRouter.scala:87:24]
wire _out_T_12042 = out_f_roready_1252; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1252 = out_wivalid_1_1106 & out_wimask_1252; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1252 = out_woready_1_1106 & out_womask_1252; // @[RegisterRouter.scala:87:24]
wire _out_T_12043 = ~out_rimask_1252; // @[RegisterRouter.scala:87:24]
wire _out_T_12044 = ~out_wimask_1252; // @[RegisterRouter.scala:87:24]
wire _out_T_12045 = ~out_romask_1252; // @[RegisterRouter.scala:87:24]
wire _out_T_12046 = ~out_womask_1252; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_1076 = {hi_72, flags_0_go, _out_prepend_T_1076}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_12047 = out_prepend_1076; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_12048 = _out_T_12047; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_136 = _out_T_12048; // @[MuxLiteral.scala:49:48]
wire out_rimask_1253 = |_out_rimask_T_1253; // @[RegisterRouter.scala:87:24]
wire out_wimask_1253 = &_out_wimask_T_1253; // @[RegisterRouter.scala:87:24]
wire out_romask_1253 = |_out_romask_T_1253; // @[RegisterRouter.scala:87:24]
wire out_womask_1253 = &_out_womask_T_1253; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1253 = out_rivalid_1_1107 & out_rimask_1253; // @[RegisterRouter.scala:87:24]
wire _out_T_12050 = out_f_rivalid_1253; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1253 = out_roready_1_1107 & out_romask_1253; // @[RegisterRouter.scala:87:24]
wire _out_T_12051 = out_f_roready_1253; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1253 = out_wivalid_1_1107 & out_wimask_1253; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1253 = out_woready_1_1107 & out_womask_1253; // @[RegisterRouter.scala:87:24]
wire _out_T_12052 = ~out_rimask_1253; // @[RegisterRouter.scala:87:24]
wire _out_T_12053 = ~out_wimask_1253; // @[RegisterRouter.scala:87:24]
wire _out_T_12054 = ~out_romask_1253; // @[RegisterRouter.scala:87:24]
wire _out_T_12055 = ~out_womask_1253; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12057 = _out_T_12056; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_1077 = _out_T_12057; // @[RegisterRouter.scala:87:24]
wire out_rimask_1254 = |_out_rimask_T_1254; // @[RegisterRouter.scala:87:24]
wire out_wimask_1254 = &_out_wimask_T_1254; // @[RegisterRouter.scala:87:24]
wire out_romask_1254 = |_out_romask_T_1254; // @[RegisterRouter.scala:87:24]
wire out_womask_1254 = &_out_womask_T_1254; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1254 = out_rivalid_1_1108 & out_rimask_1254; // @[RegisterRouter.scala:87:24]
wire _out_T_12059 = out_f_rivalid_1254; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1254 = out_roready_1_1108 & out_romask_1254; // @[RegisterRouter.scala:87:24]
wire _out_T_12060 = out_f_roready_1254; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1254 = out_wivalid_1_1108 & out_wimask_1254; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1254 = out_woready_1_1108 & out_womask_1254; // @[RegisterRouter.scala:87:24]
wire _out_T_12061 = ~out_rimask_1254; // @[RegisterRouter.scala:87:24]
wire _out_T_12062 = ~out_wimask_1254; // @[RegisterRouter.scala:87:24]
wire _out_T_12063 = ~out_romask_1254; // @[RegisterRouter.scala:87:24]
wire _out_T_12064 = ~out_womask_1254; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_1077 = {hi_538, flags_0_go, _out_prepend_T_1077}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_12065 = out_prepend_1077; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_12066 = _out_T_12065; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_1078 = _out_T_12066; // @[RegisterRouter.scala:87:24]
wire out_rimask_1255 = |_out_rimask_T_1255; // @[RegisterRouter.scala:87:24]
wire out_wimask_1255 = &_out_wimask_T_1255; // @[RegisterRouter.scala:87:24]
wire out_romask_1255 = |_out_romask_T_1255; // @[RegisterRouter.scala:87:24]
wire out_womask_1255 = &_out_womask_T_1255; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1255 = out_rivalid_1_1109 & out_rimask_1255; // @[RegisterRouter.scala:87:24]
wire _out_T_12068 = out_f_rivalid_1255; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1255 = out_roready_1_1109 & out_romask_1255; // @[RegisterRouter.scala:87:24]
wire _out_T_12069 = out_f_roready_1255; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1255 = out_wivalid_1_1109 & out_wimask_1255; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1255 = out_woready_1_1109 & out_womask_1255; // @[RegisterRouter.scala:87:24]
wire _out_T_12070 = ~out_rimask_1255; // @[RegisterRouter.scala:87:24]
wire _out_T_12071 = ~out_wimask_1255; // @[RegisterRouter.scala:87:24]
wire _out_T_12072 = ~out_romask_1255; // @[RegisterRouter.scala:87:24]
wire _out_T_12073 = ~out_womask_1255; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_1078 = {hi_539, flags_0_go, _out_prepend_T_1078}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_12074 = out_prepend_1078; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_12075 = _out_T_12074; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_1079 = _out_T_12075; // @[RegisterRouter.scala:87:24]
wire out_rimask_1256 = |_out_rimask_T_1256; // @[RegisterRouter.scala:87:24]
wire out_wimask_1256 = &_out_wimask_T_1256; // @[RegisterRouter.scala:87:24]
wire out_romask_1256 = |_out_romask_T_1256; // @[RegisterRouter.scala:87:24]
wire out_womask_1256 = &_out_womask_T_1256; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1256 = out_rivalid_1_1110 & out_rimask_1256; // @[RegisterRouter.scala:87:24]
wire _out_T_12077 = out_f_rivalid_1256; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1256 = out_roready_1_1110 & out_romask_1256; // @[RegisterRouter.scala:87:24]
wire _out_T_12078 = out_f_roready_1256; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1256 = out_wivalid_1_1110 & out_wimask_1256; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1256 = out_woready_1_1110 & out_womask_1256; // @[RegisterRouter.scala:87:24]
wire _out_T_12079 = ~out_rimask_1256; // @[RegisterRouter.scala:87:24]
wire _out_T_12080 = ~out_wimask_1256; // @[RegisterRouter.scala:87:24]
wire _out_T_12081 = ~out_romask_1256; // @[RegisterRouter.scala:87:24]
wire _out_T_12082 = ~out_womask_1256; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_1079 = {hi_540, flags_0_go, _out_prepend_T_1079}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_12083 = out_prepend_1079; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_12084 = _out_T_12083; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_1080 = _out_T_12084; // @[RegisterRouter.scala:87:24]
wire out_rimask_1257 = |_out_rimask_T_1257; // @[RegisterRouter.scala:87:24]
wire out_wimask_1257 = &_out_wimask_T_1257; // @[RegisterRouter.scala:87:24]
wire out_romask_1257 = |_out_romask_T_1257; // @[RegisterRouter.scala:87:24]
wire out_womask_1257 = &_out_womask_T_1257; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1257 = out_rivalid_1_1111 & out_rimask_1257; // @[RegisterRouter.scala:87:24]
wire _out_T_12086 = out_f_rivalid_1257; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1257 = out_roready_1_1111 & out_romask_1257; // @[RegisterRouter.scala:87:24]
wire _out_T_12087 = out_f_roready_1257; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1257 = out_wivalid_1_1111 & out_wimask_1257; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1257 = out_woready_1_1111 & out_womask_1257; // @[RegisterRouter.scala:87:24]
wire _out_T_12088 = ~out_rimask_1257; // @[RegisterRouter.scala:87:24]
wire _out_T_12089 = ~out_wimask_1257; // @[RegisterRouter.scala:87:24]
wire _out_T_12090 = ~out_romask_1257; // @[RegisterRouter.scala:87:24]
wire _out_T_12091 = ~out_womask_1257; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_1080 = {hi_541, flags_0_go, _out_prepend_T_1080}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_12092 = out_prepend_1080; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_12093 = _out_T_12092; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_1081 = _out_T_12093; // @[RegisterRouter.scala:87:24]
wire out_rimask_1258 = |_out_rimask_T_1258; // @[RegisterRouter.scala:87:24]
wire out_wimask_1258 = &_out_wimask_T_1258; // @[RegisterRouter.scala:87:24]
wire out_romask_1258 = |_out_romask_T_1258; // @[RegisterRouter.scala:87:24]
wire out_womask_1258 = &_out_womask_T_1258; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1258 = out_rivalid_1_1112 & out_rimask_1258; // @[RegisterRouter.scala:87:24]
wire _out_T_12095 = out_f_rivalid_1258; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1258 = out_roready_1_1112 & out_romask_1258; // @[RegisterRouter.scala:87:24]
wire _out_T_12096 = out_f_roready_1258; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1258 = out_wivalid_1_1112 & out_wimask_1258; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1258 = out_woready_1_1112 & out_womask_1258; // @[RegisterRouter.scala:87:24]
wire _out_T_12097 = ~out_rimask_1258; // @[RegisterRouter.scala:87:24]
wire _out_T_12098 = ~out_wimask_1258; // @[RegisterRouter.scala:87:24]
wire _out_T_12099 = ~out_romask_1258; // @[RegisterRouter.scala:87:24]
wire _out_T_12100 = ~out_womask_1258; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_1081 = {hi_542, flags_0_go, _out_prepend_T_1081}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_12101 = out_prepend_1081; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_12102 = _out_T_12101; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_1082 = _out_T_12102; // @[RegisterRouter.scala:87:24]
wire out_rimask_1259 = |_out_rimask_T_1259; // @[RegisterRouter.scala:87:24]
wire out_wimask_1259 = &_out_wimask_T_1259; // @[RegisterRouter.scala:87:24]
wire out_romask_1259 = |_out_romask_T_1259; // @[RegisterRouter.scala:87:24]
wire out_womask_1259 = &_out_womask_T_1259; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1259 = out_rivalid_1_1113 & out_rimask_1259; // @[RegisterRouter.scala:87:24]
wire _out_T_12104 = out_f_rivalid_1259; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1259 = out_roready_1_1113 & out_romask_1259; // @[RegisterRouter.scala:87:24]
wire _out_T_12105 = out_f_roready_1259; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1259 = out_wivalid_1_1113 & out_wimask_1259; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1259 = out_woready_1_1113 & out_womask_1259; // @[RegisterRouter.scala:87:24]
wire _out_T_12106 = ~out_rimask_1259; // @[RegisterRouter.scala:87:24]
wire _out_T_12107 = ~out_wimask_1259; // @[RegisterRouter.scala:87:24]
wire _out_T_12108 = ~out_romask_1259; // @[RegisterRouter.scala:87:24]
wire _out_T_12109 = ~out_womask_1259; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_1082 = {hi_543, flags_0_go, _out_prepend_T_1082}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_12110 = out_prepend_1082; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_12111 = _out_T_12110; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_1083 = _out_T_12111; // @[RegisterRouter.scala:87:24]
wire out_rimask_1260 = |_out_rimask_T_1260; // @[RegisterRouter.scala:87:24]
wire out_wimask_1260 = &_out_wimask_T_1260; // @[RegisterRouter.scala:87:24]
wire out_romask_1260 = |_out_romask_T_1260; // @[RegisterRouter.scala:87:24]
wire out_womask_1260 = &_out_womask_T_1260; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1260 = out_rivalid_1_1114 & out_rimask_1260; // @[RegisterRouter.scala:87:24]
wire _out_T_12113 = out_f_rivalid_1260; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1260 = out_roready_1_1114 & out_romask_1260; // @[RegisterRouter.scala:87:24]
wire _out_T_12114 = out_f_roready_1260; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1260 = out_wivalid_1_1114 & out_wimask_1260; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1260 = out_woready_1_1114 & out_womask_1260; // @[RegisterRouter.scala:87:24]
wire _out_T_12115 = ~out_rimask_1260; // @[RegisterRouter.scala:87:24]
wire _out_T_12116 = ~out_wimask_1260; // @[RegisterRouter.scala:87:24]
wire _out_T_12117 = ~out_romask_1260; // @[RegisterRouter.scala:87:24]
wire _out_T_12118 = ~out_womask_1260; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_1083 = {hi_544, flags_0_go, _out_prepend_T_1083}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_12119 = out_prepend_1083; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_12120 = _out_T_12119; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_195 = _out_T_12120; // @[MuxLiteral.scala:49:48]
wire out_rimask_1261 = |_out_rimask_T_1261; // @[RegisterRouter.scala:87:24]
wire out_wimask_1261 = &_out_wimask_T_1261; // @[RegisterRouter.scala:87:24]
wire out_romask_1261 = |_out_romask_T_1261; // @[RegisterRouter.scala:87:24]
wire out_womask_1261 = &_out_womask_T_1261; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1261 = out_rivalid_1_1115 & out_rimask_1261; // @[RegisterRouter.scala:87:24]
wire _out_T_12122 = out_f_rivalid_1261; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1261 = out_roready_1_1115 & out_romask_1261; // @[RegisterRouter.scala:87:24]
wire _out_T_12123 = out_f_roready_1261; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1261 = out_wivalid_1_1115 & out_wimask_1261; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1261 = out_woready_1_1115 & out_womask_1261; // @[RegisterRouter.scala:87:24]
wire _out_T_12124 = ~out_rimask_1261; // @[RegisterRouter.scala:87:24]
wire _out_T_12125 = ~out_wimask_1261; // @[RegisterRouter.scala:87:24]
wire _out_T_12126 = ~out_romask_1261; // @[RegisterRouter.scala:87:24]
wire _out_T_12127 = ~out_womask_1261; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12129 = _out_T_12128; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_1084 = _out_T_12129; // @[RegisterRouter.scala:87:24]
wire out_rimask_1262 = |_out_rimask_T_1262; // @[RegisterRouter.scala:87:24]
wire out_wimask_1262 = &_out_wimask_T_1262; // @[RegisterRouter.scala:87:24]
wire out_romask_1262 = |_out_romask_T_1262; // @[RegisterRouter.scala:87:24]
wire out_womask_1262 = &_out_womask_T_1262; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1262 = out_rivalid_1_1116 & out_rimask_1262; // @[RegisterRouter.scala:87:24]
wire _out_T_12131 = out_f_rivalid_1262; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1262 = out_roready_1_1116 & out_romask_1262; // @[RegisterRouter.scala:87:24]
wire _out_T_12132 = out_f_roready_1262; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1262 = out_wivalid_1_1116 & out_wimask_1262; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1262 = out_woready_1_1116 & out_womask_1262; // @[RegisterRouter.scala:87:24]
wire _out_T_12133 = ~out_rimask_1262; // @[RegisterRouter.scala:87:24]
wire _out_T_12134 = ~out_wimask_1262; // @[RegisterRouter.scala:87:24]
wire _out_T_12135 = ~out_romask_1262; // @[RegisterRouter.scala:87:24]
wire _out_T_12136 = ~out_womask_1262; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_1084 = {hi_890, flags_0_go, _out_prepend_T_1084}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_12137 = out_prepend_1084; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_12138 = _out_T_12137; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_1085 = _out_T_12138; // @[RegisterRouter.scala:87:24]
wire out_rimask_1263 = |_out_rimask_T_1263; // @[RegisterRouter.scala:87:24]
wire out_wimask_1263 = &_out_wimask_T_1263; // @[RegisterRouter.scala:87:24]
wire out_romask_1263 = |_out_romask_T_1263; // @[RegisterRouter.scala:87:24]
wire out_womask_1263 = &_out_womask_T_1263; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1263 = out_rivalid_1_1117 & out_rimask_1263; // @[RegisterRouter.scala:87:24]
wire _out_T_12140 = out_f_rivalid_1263; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1263 = out_roready_1_1117 & out_romask_1263; // @[RegisterRouter.scala:87:24]
wire _out_T_12141 = out_f_roready_1263; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1263 = out_wivalid_1_1117 & out_wimask_1263; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1263 = out_woready_1_1117 & out_womask_1263; // @[RegisterRouter.scala:87:24]
wire _out_T_12142 = ~out_rimask_1263; // @[RegisterRouter.scala:87:24]
wire _out_T_12143 = ~out_wimask_1263; // @[RegisterRouter.scala:87:24]
wire _out_T_12144 = ~out_romask_1263; // @[RegisterRouter.scala:87:24]
wire _out_T_12145 = ~out_womask_1263; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_1085 = {hi_891, flags_0_go, _out_prepend_T_1085}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_12146 = out_prepend_1085; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_12147 = _out_T_12146; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_1086 = _out_T_12147; // @[RegisterRouter.scala:87:24]
wire out_rimask_1264 = |_out_rimask_T_1264; // @[RegisterRouter.scala:87:24]
wire out_wimask_1264 = &_out_wimask_T_1264; // @[RegisterRouter.scala:87:24]
wire out_romask_1264 = |_out_romask_T_1264; // @[RegisterRouter.scala:87:24]
wire out_womask_1264 = &_out_womask_T_1264; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1264 = out_rivalid_1_1118 & out_rimask_1264; // @[RegisterRouter.scala:87:24]
wire _out_T_12149 = out_f_rivalid_1264; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1264 = out_roready_1_1118 & out_romask_1264; // @[RegisterRouter.scala:87:24]
wire _out_T_12150 = out_f_roready_1264; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1264 = out_wivalid_1_1118 & out_wimask_1264; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1264 = out_woready_1_1118 & out_womask_1264; // @[RegisterRouter.scala:87:24]
wire _out_T_12151 = ~out_rimask_1264; // @[RegisterRouter.scala:87:24]
wire _out_T_12152 = ~out_wimask_1264; // @[RegisterRouter.scala:87:24]
wire _out_T_12153 = ~out_romask_1264; // @[RegisterRouter.scala:87:24]
wire _out_T_12154 = ~out_womask_1264; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_1086 = {hi_892, flags_0_go, _out_prepend_T_1086}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_12155 = out_prepend_1086; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_12156 = _out_T_12155; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_1087 = _out_T_12156; // @[RegisterRouter.scala:87:24]
wire out_rimask_1265 = |_out_rimask_T_1265; // @[RegisterRouter.scala:87:24]
wire out_wimask_1265 = &_out_wimask_T_1265; // @[RegisterRouter.scala:87:24]
wire out_romask_1265 = |_out_romask_T_1265; // @[RegisterRouter.scala:87:24]
wire out_womask_1265 = &_out_womask_T_1265; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1265 = out_rivalid_1_1119 & out_rimask_1265; // @[RegisterRouter.scala:87:24]
wire _out_T_12158 = out_f_rivalid_1265; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1265 = out_roready_1_1119 & out_romask_1265; // @[RegisterRouter.scala:87:24]
wire _out_T_12159 = out_f_roready_1265; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1265 = out_wivalid_1_1119 & out_wimask_1265; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1265 = out_woready_1_1119 & out_womask_1265; // @[RegisterRouter.scala:87:24]
wire _out_T_12160 = ~out_rimask_1265; // @[RegisterRouter.scala:87:24]
wire _out_T_12161 = ~out_wimask_1265; // @[RegisterRouter.scala:87:24]
wire _out_T_12162 = ~out_romask_1265; // @[RegisterRouter.scala:87:24]
wire _out_T_12163 = ~out_womask_1265; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_1087 = {hi_893, flags_0_go, _out_prepend_T_1087}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_12164 = out_prepend_1087; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_12165 = _out_T_12164; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_1088 = _out_T_12165; // @[RegisterRouter.scala:87:24]
wire out_rimask_1266 = |_out_rimask_T_1266; // @[RegisterRouter.scala:87:24]
wire out_wimask_1266 = &_out_wimask_T_1266; // @[RegisterRouter.scala:87:24]
wire out_romask_1266 = |_out_romask_T_1266; // @[RegisterRouter.scala:87:24]
wire out_womask_1266 = &_out_womask_T_1266; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1266 = out_rivalid_1_1120 & out_rimask_1266; // @[RegisterRouter.scala:87:24]
wire _out_T_12167 = out_f_rivalid_1266; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1266 = out_roready_1_1120 & out_romask_1266; // @[RegisterRouter.scala:87:24]
wire _out_T_12168 = out_f_roready_1266; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1266 = out_wivalid_1_1120 & out_wimask_1266; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1266 = out_woready_1_1120 & out_womask_1266; // @[RegisterRouter.scala:87:24]
wire _out_T_12169 = ~out_rimask_1266; // @[RegisterRouter.scala:87:24]
wire _out_T_12170 = ~out_wimask_1266; // @[RegisterRouter.scala:87:24]
wire _out_T_12171 = ~out_romask_1266; // @[RegisterRouter.scala:87:24]
wire _out_T_12172 = ~out_womask_1266; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_1088 = {hi_894, flags_0_go, _out_prepend_T_1088}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_12173 = out_prepend_1088; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_12174 = _out_T_12173; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_1089 = _out_T_12174; // @[RegisterRouter.scala:87:24]
wire out_rimask_1267 = |_out_rimask_T_1267; // @[RegisterRouter.scala:87:24]
wire out_wimask_1267 = &_out_wimask_T_1267; // @[RegisterRouter.scala:87:24]
wire out_romask_1267 = |_out_romask_T_1267; // @[RegisterRouter.scala:87:24]
wire out_womask_1267 = &_out_womask_T_1267; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1267 = out_rivalid_1_1121 & out_rimask_1267; // @[RegisterRouter.scala:87:24]
wire _out_T_12176 = out_f_rivalid_1267; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1267 = out_roready_1_1121 & out_romask_1267; // @[RegisterRouter.scala:87:24]
wire _out_T_12177 = out_f_roready_1267; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1267 = out_wivalid_1_1121 & out_wimask_1267; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1267 = out_woready_1_1121 & out_womask_1267; // @[RegisterRouter.scala:87:24]
wire _out_T_12178 = ~out_rimask_1267; // @[RegisterRouter.scala:87:24]
wire _out_T_12179 = ~out_wimask_1267; // @[RegisterRouter.scala:87:24]
wire _out_T_12180 = ~out_romask_1267; // @[RegisterRouter.scala:87:24]
wire _out_T_12181 = ~out_womask_1267; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_1089 = {hi_895, flags_0_go, _out_prepend_T_1089}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_12182 = out_prepend_1089; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_12183 = _out_T_12182; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_1090 = _out_T_12183; // @[RegisterRouter.scala:87:24]
wire out_rimask_1268 = |_out_rimask_T_1268; // @[RegisterRouter.scala:87:24]
wire out_wimask_1268 = &_out_wimask_T_1268; // @[RegisterRouter.scala:87:24]
wire out_romask_1268 = |_out_romask_T_1268; // @[RegisterRouter.scala:87:24]
wire out_womask_1268 = &_out_womask_T_1268; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1268 = out_rivalid_1_1122 & out_rimask_1268; // @[RegisterRouter.scala:87:24]
wire _out_T_12185 = out_f_rivalid_1268; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1268 = out_roready_1_1122 & out_romask_1268; // @[RegisterRouter.scala:87:24]
wire _out_T_12186 = out_f_roready_1268; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1268 = out_wivalid_1_1122 & out_wimask_1268; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1268 = out_woready_1_1122 & out_womask_1268; // @[RegisterRouter.scala:87:24]
wire _out_T_12187 = ~out_rimask_1268; // @[RegisterRouter.scala:87:24]
wire _out_T_12188 = ~out_wimask_1268; // @[RegisterRouter.scala:87:24]
wire _out_T_12189 = ~out_romask_1268; // @[RegisterRouter.scala:87:24]
wire _out_T_12190 = ~out_womask_1268; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_1090 = {hi_896, flags_0_go, _out_prepend_T_1090}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_12191 = out_prepend_1090; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_12192 = _out_T_12191; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_239 = _out_T_12192; // @[MuxLiteral.scala:49:48]
wire out_rimask_1269 = |_out_rimask_T_1269; // @[RegisterRouter.scala:87:24]
wire out_wimask_1269 = &_out_wimask_T_1269; // @[RegisterRouter.scala:87:24]
wire out_romask_1269 = |_out_romask_T_1269; // @[RegisterRouter.scala:87:24]
wire out_womask_1269 = &_out_womask_T_1269; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1269 = out_rivalid_1_1123 & out_rimask_1269; // @[RegisterRouter.scala:87:24]
wire _out_T_12194 = out_f_rivalid_1269; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1269 = out_roready_1_1123 & out_romask_1269; // @[RegisterRouter.scala:87:24]
wire _out_T_12195 = out_f_roready_1269; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1269 = out_wivalid_1_1123 & out_wimask_1269; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1269 = out_woready_1_1123 & out_womask_1269; // @[RegisterRouter.scala:87:24]
wire _out_T_12196 = ~out_rimask_1269; // @[RegisterRouter.scala:87:24]
wire _out_T_12197 = ~out_wimask_1269; // @[RegisterRouter.scala:87:24]
wire _out_T_12198 = ~out_romask_1269; // @[RegisterRouter.scala:87:24]
wire _out_T_12199 = ~out_womask_1269; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12201 = _out_T_12200; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_1091 = _out_T_12201; // @[RegisterRouter.scala:87:24]
wire out_rimask_1270 = |_out_rimask_T_1270; // @[RegisterRouter.scala:87:24]
wire out_wimask_1270 = &_out_wimask_T_1270; // @[RegisterRouter.scala:87:24]
wire out_romask_1270 = |_out_romask_T_1270; // @[RegisterRouter.scala:87:24]
wire out_womask_1270 = &_out_womask_T_1270; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1270 = out_rivalid_1_1124 & out_rimask_1270; // @[RegisterRouter.scala:87:24]
wire _out_T_12203 = out_f_rivalid_1270; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1270 = out_roready_1_1124 & out_romask_1270; // @[RegisterRouter.scala:87:24]
wire _out_T_12204 = out_f_roready_1270; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1270 = out_wivalid_1_1124 & out_wimask_1270; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1270 = out_woready_1_1124 & out_womask_1270; // @[RegisterRouter.scala:87:24]
wire _out_T_12205 = ~out_rimask_1270; // @[RegisterRouter.scala:87:24]
wire _out_T_12206 = ~out_wimask_1270; // @[RegisterRouter.scala:87:24]
wire _out_T_12207 = ~out_romask_1270; // @[RegisterRouter.scala:87:24]
wire _out_T_12208 = ~out_womask_1270; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_1091 = {hi_914, flags_0_go, _out_prepend_T_1091}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_12209 = out_prepend_1091; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_12210 = _out_T_12209; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_1092 = _out_T_12210; // @[RegisterRouter.scala:87:24]
wire out_rimask_1271 = |_out_rimask_T_1271; // @[RegisterRouter.scala:87:24]
wire out_wimask_1271 = &_out_wimask_T_1271; // @[RegisterRouter.scala:87:24]
wire out_romask_1271 = |_out_romask_T_1271; // @[RegisterRouter.scala:87:24]
wire out_womask_1271 = &_out_womask_T_1271; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1271 = out_rivalid_1_1125 & out_rimask_1271; // @[RegisterRouter.scala:87:24]
wire _out_T_12212 = out_f_rivalid_1271; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1271 = out_roready_1_1125 & out_romask_1271; // @[RegisterRouter.scala:87:24]
wire _out_T_12213 = out_f_roready_1271; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1271 = out_wivalid_1_1125 & out_wimask_1271; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1271 = out_woready_1_1125 & out_womask_1271; // @[RegisterRouter.scala:87:24]
wire _out_T_12214 = ~out_rimask_1271; // @[RegisterRouter.scala:87:24]
wire _out_T_12215 = ~out_wimask_1271; // @[RegisterRouter.scala:87:24]
wire _out_T_12216 = ~out_romask_1271; // @[RegisterRouter.scala:87:24]
wire _out_T_12217 = ~out_womask_1271; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_1092 = {hi_915, flags_0_go, _out_prepend_T_1092}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_12218 = out_prepend_1092; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_12219 = _out_T_12218; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_1093 = _out_T_12219; // @[RegisterRouter.scala:87:24]
wire out_rimask_1272 = |_out_rimask_T_1272; // @[RegisterRouter.scala:87:24]
wire out_wimask_1272 = &_out_wimask_T_1272; // @[RegisterRouter.scala:87:24]
wire out_romask_1272 = |_out_romask_T_1272; // @[RegisterRouter.scala:87:24]
wire out_womask_1272 = &_out_womask_T_1272; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1272 = out_rivalid_1_1126 & out_rimask_1272; // @[RegisterRouter.scala:87:24]
wire _out_T_12221 = out_f_rivalid_1272; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1272 = out_roready_1_1126 & out_romask_1272; // @[RegisterRouter.scala:87:24]
wire _out_T_12222 = out_f_roready_1272; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1272 = out_wivalid_1_1126 & out_wimask_1272; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1272 = out_woready_1_1126 & out_womask_1272; // @[RegisterRouter.scala:87:24]
wire _out_T_12223 = ~out_rimask_1272; // @[RegisterRouter.scala:87:24]
wire _out_T_12224 = ~out_wimask_1272; // @[RegisterRouter.scala:87:24]
wire _out_T_12225 = ~out_romask_1272; // @[RegisterRouter.scala:87:24]
wire _out_T_12226 = ~out_womask_1272; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_1093 = {hi_916, flags_0_go, _out_prepend_T_1093}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_12227 = out_prepend_1093; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_12228 = _out_T_12227; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_1094 = _out_T_12228; // @[RegisterRouter.scala:87:24]
wire out_rimask_1273 = |_out_rimask_T_1273; // @[RegisterRouter.scala:87:24]
wire out_wimask_1273 = &_out_wimask_T_1273; // @[RegisterRouter.scala:87:24]
wire out_romask_1273 = |_out_romask_T_1273; // @[RegisterRouter.scala:87:24]
wire out_womask_1273 = &_out_womask_T_1273; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1273 = out_rivalid_1_1127 & out_rimask_1273; // @[RegisterRouter.scala:87:24]
wire _out_T_12230 = out_f_rivalid_1273; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1273 = out_roready_1_1127 & out_romask_1273; // @[RegisterRouter.scala:87:24]
wire _out_T_12231 = out_f_roready_1273; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1273 = out_wivalid_1_1127 & out_wimask_1273; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1273 = out_woready_1_1127 & out_womask_1273; // @[RegisterRouter.scala:87:24]
wire _out_T_12232 = ~out_rimask_1273; // @[RegisterRouter.scala:87:24]
wire _out_T_12233 = ~out_wimask_1273; // @[RegisterRouter.scala:87:24]
wire _out_T_12234 = ~out_romask_1273; // @[RegisterRouter.scala:87:24]
wire _out_T_12235 = ~out_womask_1273; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_1094 = {hi_917, flags_0_go, _out_prepend_T_1094}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_12236 = out_prepend_1094; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_12237 = _out_T_12236; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_1095 = _out_T_12237; // @[RegisterRouter.scala:87:24]
wire out_rimask_1274 = |_out_rimask_T_1274; // @[RegisterRouter.scala:87:24]
wire out_wimask_1274 = &_out_wimask_T_1274; // @[RegisterRouter.scala:87:24]
wire out_romask_1274 = |_out_romask_T_1274; // @[RegisterRouter.scala:87:24]
wire out_womask_1274 = &_out_womask_T_1274; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1274 = out_rivalid_1_1128 & out_rimask_1274; // @[RegisterRouter.scala:87:24]
wire _out_T_12239 = out_f_rivalid_1274; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1274 = out_roready_1_1128 & out_romask_1274; // @[RegisterRouter.scala:87:24]
wire _out_T_12240 = out_f_roready_1274; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1274 = out_wivalid_1_1128 & out_wimask_1274; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1274 = out_woready_1_1128 & out_womask_1274; // @[RegisterRouter.scala:87:24]
wire _out_T_12241 = ~out_rimask_1274; // @[RegisterRouter.scala:87:24]
wire _out_T_12242 = ~out_wimask_1274; // @[RegisterRouter.scala:87:24]
wire _out_T_12243 = ~out_romask_1274; // @[RegisterRouter.scala:87:24]
wire _out_T_12244 = ~out_womask_1274; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_1095 = {hi_918, flags_0_go, _out_prepend_T_1095}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_12245 = out_prepend_1095; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_12246 = _out_T_12245; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_1096 = _out_T_12246; // @[RegisterRouter.scala:87:24]
wire out_rimask_1275 = |_out_rimask_T_1275; // @[RegisterRouter.scala:87:24]
wire out_wimask_1275 = &_out_wimask_T_1275; // @[RegisterRouter.scala:87:24]
wire out_romask_1275 = |_out_romask_T_1275; // @[RegisterRouter.scala:87:24]
wire out_womask_1275 = &_out_womask_T_1275; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1275 = out_rivalid_1_1129 & out_rimask_1275; // @[RegisterRouter.scala:87:24]
wire _out_T_12248 = out_f_rivalid_1275; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1275 = out_roready_1_1129 & out_romask_1275; // @[RegisterRouter.scala:87:24]
wire _out_T_12249 = out_f_roready_1275; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1275 = out_wivalid_1_1129 & out_wimask_1275; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1275 = out_woready_1_1129 & out_womask_1275; // @[RegisterRouter.scala:87:24]
wire _out_T_12250 = ~out_rimask_1275; // @[RegisterRouter.scala:87:24]
wire _out_T_12251 = ~out_wimask_1275; // @[RegisterRouter.scala:87:24]
wire _out_T_12252 = ~out_romask_1275; // @[RegisterRouter.scala:87:24]
wire _out_T_12253 = ~out_womask_1275; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_1096 = {hi_919, flags_0_go, _out_prepend_T_1096}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_12254 = out_prepend_1096; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_12255 = _out_T_12254; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_1097 = _out_T_12255; // @[RegisterRouter.scala:87:24]
wire out_rimask_1276 = |_out_rimask_T_1276; // @[RegisterRouter.scala:87:24]
wire out_wimask_1276 = &_out_wimask_T_1276; // @[RegisterRouter.scala:87:24]
wire out_romask_1276 = |_out_romask_T_1276; // @[RegisterRouter.scala:87:24]
wire out_womask_1276 = &_out_womask_T_1276; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1276 = out_rivalid_1_1130 & out_rimask_1276; // @[RegisterRouter.scala:87:24]
wire _out_T_12257 = out_f_rivalid_1276; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1276 = out_roready_1_1130 & out_romask_1276; // @[RegisterRouter.scala:87:24]
wire _out_T_12258 = out_f_roready_1276; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1276 = out_wivalid_1_1130 & out_wimask_1276; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1276 = out_woready_1_1130 & out_womask_1276; // @[RegisterRouter.scala:87:24]
wire _out_T_12259 = ~out_rimask_1276; // @[RegisterRouter.scala:87:24]
wire _out_T_12260 = ~out_wimask_1276; // @[RegisterRouter.scala:87:24]
wire _out_T_12261 = ~out_romask_1276; // @[RegisterRouter.scala:87:24]
wire _out_T_12262 = ~out_womask_1276; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_1097 = {hi_920, flags_0_go, _out_prepend_T_1097}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_12263 = out_prepend_1097; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_12264 = _out_T_12263; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_242 = _out_T_12264; // @[MuxLiteral.scala:49:48]
wire out_rimask_1277 = |_out_rimask_T_1277; // @[RegisterRouter.scala:87:24]
wire out_wimask_1277 = &_out_wimask_T_1277; // @[RegisterRouter.scala:87:24]
wire out_romask_1277 = |_out_romask_T_1277; // @[RegisterRouter.scala:87:24]
wire out_womask_1277 = &_out_womask_T_1277; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1277 = out_rivalid_1_1131 & out_rimask_1277; // @[RegisterRouter.scala:87:24]
wire _out_T_12266 = out_f_rivalid_1277; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1277 = out_roready_1_1131 & out_romask_1277; // @[RegisterRouter.scala:87:24]
wire _out_T_12267 = out_f_roready_1277; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1277 = out_wivalid_1_1131 & out_wimask_1277; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1277 = out_woready_1_1131 & out_womask_1277; // @[RegisterRouter.scala:87:24]
wire _out_T_12268 = ~out_rimask_1277; // @[RegisterRouter.scala:87:24]
wire _out_T_12269 = ~out_wimask_1277; // @[RegisterRouter.scala:87:24]
wire _out_T_12270 = ~out_romask_1277; // @[RegisterRouter.scala:87:24]
wire _out_T_12271 = ~out_womask_1277; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12273 = _out_T_12272; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_1098 = _out_T_12273; // @[RegisterRouter.scala:87:24]
wire out_rimask_1278 = |_out_rimask_T_1278; // @[RegisterRouter.scala:87:24]
wire out_wimask_1278 = &_out_wimask_T_1278; // @[RegisterRouter.scala:87:24]
wire out_romask_1278 = |_out_romask_T_1278; // @[RegisterRouter.scala:87:24]
wire out_womask_1278 = &_out_womask_T_1278; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1278 = out_rivalid_1_1132 & out_rimask_1278; // @[RegisterRouter.scala:87:24]
wire _out_T_12275 = out_f_rivalid_1278; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1278 = out_roready_1_1132 & out_romask_1278; // @[RegisterRouter.scala:87:24]
wire _out_T_12276 = out_f_roready_1278; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1278 = out_wivalid_1_1132 & out_wimask_1278; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1278 = out_woready_1_1132 & out_womask_1278; // @[RegisterRouter.scala:87:24]
wire _out_T_12277 = ~out_rimask_1278; // @[RegisterRouter.scala:87:24]
wire _out_T_12278 = ~out_wimask_1278; // @[RegisterRouter.scala:87:24]
wire _out_T_12279 = ~out_romask_1278; // @[RegisterRouter.scala:87:24]
wire _out_T_12280 = ~out_womask_1278; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_1098 = {hi_26, flags_0_go, _out_prepend_T_1098}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_12281 = out_prepend_1098; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_12282 = _out_T_12281; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_1099 = _out_T_12282; // @[RegisterRouter.scala:87:24]
wire out_rimask_1279 = |_out_rimask_T_1279; // @[RegisterRouter.scala:87:24]
wire out_wimask_1279 = &_out_wimask_T_1279; // @[RegisterRouter.scala:87:24]
wire out_romask_1279 = |_out_romask_T_1279; // @[RegisterRouter.scala:87:24]
wire out_womask_1279 = &_out_womask_T_1279; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1279 = out_rivalid_1_1133 & out_rimask_1279; // @[RegisterRouter.scala:87:24]
wire _out_T_12284 = out_f_rivalid_1279; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1279 = out_roready_1_1133 & out_romask_1279; // @[RegisterRouter.scala:87:24]
wire _out_T_12285 = out_f_roready_1279; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1279 = out_wivalid_1_1133 & out_wimask_1279; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1279 = out_woready_1_1133 & out_womask_1279; // @[RegisterRouter.scala:87:24]
wire _out_T_12286 = ~out_rimask_1279; // @[RegisterRouter.scala:87:24]
wire _out_T_12287 = ~out_wimask_1279; // @[RegisterRouter.scala:87:24]
wire _out_T_12288 = ~out_romask_1279; // @[RegisterRouter.scala:87:24]
wire _out_T_12289 = ~out_womask_1279; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_1099 = {hi_27, flags_0_go, _out_prepend_T_1099}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_12290 = out_prepend_1099; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_12291 = _out_T_12290; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_1100 = _out_T_12291; // @[RegisterRouter.scala:87:24]
wire out_rimask_1280 = |_out_rimask_T_1280; // @[RegisterRouter.scala:87:24]
wire out_wimask_1280 = &_out_wimask_T_1280; // @[RegisterRouter.scala:87:24]
wire out_romask_1280 = |_out_romask_T_1280; // @[RegisterRouter.scala:87:24]
wire out_womask_1280 = &_out_womask_T_1280; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1280 = out_rivalid_1_1134 & out_rimask_1280; // @[RegisterRouter.scala:87:24]
wire _out_T_12293 = out_f_rivalid_1280; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1280 = out_roready_1_1134 & out_romask_1280; // @[RegisterRouter.scala:87:24]
wire _out_T_12294 = out_f_roready_1280; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1280 = out_wivalid_1_1134 & out_wimask_1280; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1280 = out_woready_1_1134 & out_womask_1280; // @[RegisterRouter.scala:87:24]
wire _out_T_12295 = ~out_rimask_1280; // @[RegisterRouter.scala:87:24]
wire _out_T_12296 = ~out_wimask_1280; // @[RegisterRouter.scala:87:24]
wire _out_T_12297 = ~out_romask_1280; // @[RegisterRouter.scala:87:24]
wire _out_T_12298 = ~out_womask_1280; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_1100 = {hi_28, flags_0_go, _out_prepend_T_1100}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_12299 = out_prepend_1100; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_12300 = _out_T_12299; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_1101 = _out_T_12300; // @[RegisterRouter.scala:87:24]
wire out_rimask_1281 = |_out_rimask_T_1281; // @[RegisterRouter.scala:87:24]
wire out_wimask_1281 = &_out_wimask_T_1281; // @[RegisterRouter.scala:87:24]
wire out_romask_1281 = |_out_romask_T_1281; // @[RegisterRouter.scala:87:24]
wire out_womask_1281 = &_out_womask_T_1281; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1281 = out_rivalid_1_1135 & out_rimask_1281; // @[RegisterRouter.scala:87:24]
wire _out_T_12302 = out_f_rivalid_1281; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1281 = out_roready_1_1135 & out_romask_1281; // @[RegisterRouter.scala:87:24]
wire _out_T_12303 = out_f_roready_1281; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1281 = out_wivalid_1_1135 & out_wimask_1281; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1281 = out_woready_1_1135 & out_womask_1281; // @[RegisterRouter.scala:87:24]
wire _out_T_12304 = ~out_rimask_1281; // @[RegisterRouter.scala:87:24]
wire _out_T_12305 = ~out_wimask_1281; // @[RegisterRouter.scala:87:24]
wire _out_T_12306 = ~out_romask_1281; // @[RegisterRouter.scala:87:24]
wire _out_T_12307 = ~out_womask_1281; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_1101 = {hi_29, flags_0_go, _out_prepend_T_1101}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_12308 = out_prepend_1101; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_12309 = _out_T_12308; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_1102 = _out_T_12309; // @[RegisterRouter.scala:87:24]
wire out_rimask_1282 = |_out_rimask_T_1282; // @[RegisterRouter.scala:87:24]
wire out_wimask_1282 = &_out_wimask_T_1282; // @[RegisterRouter.scala:87:24]
wire out_romask_1282 = |_out_romask_T_1282; // @[RegisterRouter.scala:87:24]
wire out_womask_1282 = &_out_womask_T_1282; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1282 = out_rivalid_1_1136 & out_rimask_1282; // @[RegisterRouter.scala:87:24]
wire _out_T_12311 = out_f_rivalid_1282; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1282 = out_roready_1_1136 & out_romask_1282; // @[RegisterRouter.scala:87:24]
wire _out_T_12312 = out_f_roready_1282; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1282 = out_wivalid_1_1136 & out_wimask_1282; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1282 = out_woready_1_1136 & out_womask_1282; // @[RegisterRouter.scala:87:24]
wire _out_T_12313 = ~out_rimask_1282; // @[RegisterRouter.scala:87:24]
wire _out_T_12314 = ~out_wimask_1282; // @[RegisterRouter.scala:87:24]
wire _out_T_12315 = ~out_romask_1282; // @[RegisterRouter.scala:87:24]
wire _out_T_12316 = ~out_womask_1282; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_1102 = {hi_30, flags_0_go, _out_prepend_T_1102}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_12317 = out_prepend_1102; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_12318 = _out_T_12317; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_1103 = _out_T_12318; // @[RegisterRouter.scala:87:24]
wire out_rimask_1283 = |_out_rimask_T_1283; // @[RegisterRouter.scala:87:24]
wire out_wimask_1283 = &_out_wimask_T_1283; // @[RegisterRouter.scala:87:24]
wire out_romask_1283 = |_out_romask_T_1283; // @[RegisterRouter.scala:87:24]
wire out_womask_1283 = &_out_womask_T_1283; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1283 = out_rivalid_1_1137 & out_rimask_1283; // @[RegisterRouter.scala:87:24]
wire _out_T_12320 = out_f_rivalid_1283; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1283 = out_roready_1_1137 & out_romask_1283; // @[RegisterRouter.scala:87:24]
wire _out_T_12321 = out_f_roready_1283; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1283 = out_wivalid_1_1137 & out_wimask_1283; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1283 = out_woready_1_1137 & out_womask_1283; // @[RegisterRouter.scala:87:24]
wire _out_T_12322 = ~out_rimask_1283; // @[RegisterRouter.scala:87:24]
wire _out_T_12323 = ~out_wimask_1283; // @[RegisterRouter.scala:87:24]
wire _out_T_12324 = ~out_romask_1283; // @[RegisterRouter.scala:87:24]
wire _out_T_12325 = ~out_womask_1283; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_1103 = {hi_31, flags_0_go, _out_prepend_T_1103}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_12326 = out_prepend_1103; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_12327 = _out_T_12326; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_1104 = _out_T_12327; // @[RegisterRouter.scala:87:24]
wire out_rimask_1284 = |_out_rimask_T_1284; // @[RegisterRouter.scala:87:24]
wire out_wimask_1284 = &_out_wimask_T_1284; // @[RegisterRouter.scala:87:24]
wire out_romask_1284 = |_out_romask_T_1284; // @[RegisterRouter.scala:87:24]
wire out_womask_1284 = &_out_womask_T_1284; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1284 = out_rivalid_1_1138 & out_rimask_1284; // @[RegisterRouter.scala:87:24]
wire _out_T_12329 = out_f_rivalid_1284; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1284 = out_roready_1_1138 & out_romask_1284; // @[RegisterRouter.scala:87:24]
wire _out_T_12330 = out_f_roready_1284; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1284 = out_wivalid_1_1138 & out_wimask_1284; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1284 = out_woready_1_1138 & out_womask_1284; // @[RegisterRouter.scala:87:24]
wire _out_T_12331 = ~out_rimask_1284; // @[RegisterRouter.scala:87:24]
wire _out_T_12332 = ~out_wimask_1284; // @[RegisterRouter.scala:87:24]
wire _out_T_12333 = ~out_romask_1284; // @[RegisterRouter.scala:87:24]
wire _out_T_12334 = ~out_womask_1284; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_1104 = {hi_32, flags_0_go, _out_prepend_T_1104}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_12335 = out_prepend_1104; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_12336 = _out_T_12335; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_131 = _out_T_12336; // @[MuxLiteral.scala:49:48]
wire out_rimask_1285 = |_out_rimask_T_1285; // @[RegisterRouter.scala:87:24]
wire out_wimask_1285 = &_out_wimask_T_1285; // @[RegisterRouter.scala:87:24]
wire out_romask_1285 = |_out_romask_T_1285; // @[RegisterRouter.scala:87:24]
wire out_womask_1285 = &_out_womask_T_1285; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1285 = out_rivalid_1_1139 & out_rimask_1285; // @[RegisterRouter.scala:87:24]
wire _out_T_12338 = out_f_rivalid_1285; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1285 = out_roready_1_1139 & out_romask_1285; // @[RegisterRouter.scala:87:24]
wire _out_T_12339 = out_f_roready_1285; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1285 = out_wivalid_1_1139 & out_wimask_1285; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1285 = out_woready_1_1139 & out_womask_1285; // @[RegisterRouter.scala:87:24]
wire _out_T_12340 = ~out_rimask_1285; // @[RegisterRouter.scala:87:24]
wire _out_T_12341 = ~out_wimask_1285; // @[RegisterRouter.scala:87:24]
wire _out_T_12342 = ~out_romask_1285; // @[RegisterRouter.scala:87:24]
wire _out_T_12343 = ~out_womask_1285; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12345 = _out_T_12344; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_1105 = _out_T_12345; // @[RegisterRouter.scala:87:24]
wire out_rimask_1286 = |_out_rimask_T_1286; // @[RegisterRouter.scala:87:24]
wire out_wimask_1286 = &_out_wimask_T_1286; // @[RegisterRouter.scala:87:24]
wire out_romask_1286 = |_out_romask_T_1286; // @[RegisterRouter.scala:87:24]
wire out_womask_1286 = &_out_womask_T_1286; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1286 = out_rivalid_1_1140 & out_rimask_1286; // @[RegisterRouter.scala:87:24]
wire _out_T_12347 = out_f_rivalid_1286; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1286 = out_roready_1_1140 & out_romask_1286; // @[RegisterRouter.scala:87:24]
wire _out_T_12348 = out_f_roready_1286; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1286 = out_wivalid_1_1140 & out_wimask_1286; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1286 = out_woready_1_1140 & out_womask_1286; // @[RegisterRouter.scala:87:24]
wire _out_T_12349 = ~out_rimask_1286; // @[RegisterRouter.scala:87:24]
wire _out_T_12350 = ~out_wimask_1286; // @[RegisterRouter.scala:87:24]
wire _out_T_12351 = ~out_romask_1286; // @[RegisterRouter.scala:87:24]
wire _out_T_12352 = ~out_womask_1286; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_1105 = {hi_402, flags_0_go, _out_prepend_T_1105}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_12353 = out_prepend_1105; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_12354 = _out_T_12353; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_1106 = _out_T_12354; // @[RegisterRouter.scala:87:24]
wire out_rimask_1287 = |_out_rimask_T_1287; // @[RegisterRouter.scala:87:24]
wire out_wimask_1287 = &_out_wimask_T_1287; // @[RegisterRouter.scala:87:24]
wire out_romask_1287 = |_out_romask_T_1287; // @[RegisterRouter.scala:87:24]
wire out_womask_1287 = &_out_womask_T_1287; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1287 = out_rivalid_1_1141 & out_rimask_1287; // @[RegisterRouter.scala:87:24]
wire _out_T_12356 = out_f_rivalid_1287; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1287 = out_roready_1_1141 & out_romask_1287; // @[RegisterRouter.scala:87:24]
wire _out_T_12357 = out_f_roready_1287; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1287 = out_wivalid_1_1141 & out_wimask_1287; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1287 = out_woready_1_1141 & out_womask_1287; // @[RegisterRouter.scala:87:24]
wire _out_T_12358 = ~out_rimask_1287; // @[RegisterRouter.scala:87:24]
wire _out_T_12359 = ~out_wimask_1287; // @[RegisterRouter.scala:87:24]
wire _out_T_12360 = ~out_romask_1287; // @[RegisterRouter.scala:87:24]
wire _out_T_12361 = ~out_womask_1287; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_1106 = {hi_403, flags_0_go, _out_prepend_T_1106}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_12362 = out_prepend_1106; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_12363 = _out_T_12362; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_1107 = _out_T_12363; // @[RegisterRouter.scala:87:24]
wire out_rimask_1288 = |_out_rimask_T_1288; // @[RegisterRouter.scala:87:24]
wire out_wimask_1288 = &_out_wimask_T_1288; // @[RegisterRouter.scala:87:24]
wire out_romask_1288 = |_out_romask_T_1288; // @[RegisterRouter.scala:87:24]
wire out_womask_1288 = &_out_womask_T_1288; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1288 = out_rivalid_1_1142 & out_rimask_1288; // @[RegisterRouter.scala:87:24]
wire _out_T_12365 = out_f_rivalid_1288; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1288 = out_roready_1_1142 & out_romask_1288; // @[RegisterRouter.scala:87:24]
wire _out_T_12366 = out_f_roready_1288; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1288 = out_wivalid_1_1142 & out_wimask_1288; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1288 = out_woready_1_1142 & out_womask_1288; // @[RegisterRouter.scala:87:24]
wire _out_T_12367 = ~out_rimask_1288; // @[RegisterRouter.scala:87:24]
wire _out_T_12368 = ~out_wimask_1288; // @[RegisterRouter.scala:87:24]
wire _out_T_12369 = ~out_romask_1288; // @[RegisterRouter.scala:87:24]
wire _out_T_12370 = ~out_womask_1288; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_1107 = {hi_404, flags_0_go, _out_prepend_T_1107}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_12371 = out_prepend_1107; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_12372 = _out_T_12371; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_1108 = _out_T_12372; // @[RegisterRouter.scala:87:24]
wire out_rimask_1289 = |_out_rimask_T_1289; // @[RegisterRouter.scala:87:24]
wire out_wimask_1289 = &_out_wimask_T_1289; // @[RegisterRouter.scala:87:24]
wire out_romask_1289 = |_out_romask_T_1289; // @[RegisterRouter.scala:87:24]
wire out_womask_1289 = &_out_womask_T_1289; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1289 = out_rivalid_1_1143 & out_rimask_1289; // @[RegisterRouter.scala:87:24]
wire _out_T_12374 = out_f_rivalid_1289; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1289 = out_roready_1_1143 & out_romask_1289; // @[RegisterRouter.scala:87:24]
wire _out_T_12375 = out_f_roready_1289; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1289 = out_wivalid_1_1143 & out_wimask_1289; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1289 = out_woready_1_1143 & out_womask_1289; // @[RegisterRouter.scala:87:24]
wire _out_T_12376 = ~out_rimask_1289; // @[RegisterRouter.scala:87:24]
wire _out_T_12377 = ~out_wimask_1289; // @[RegisterRouter.scala:87:24]
wire _out_T_12378 = ~out_romask_1289; // @[RegisterRouter.scala:87:24]
wire _out_T_12379 = ~out_womask_1289; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_1108 = {hi_405, flags_0_go, _out_prepend_T_1108}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_12380 = out_prepend_1108; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_12381 = _out_T_12380; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_1109 = _out_T_12381; // @[RegisterRouter.scala:87:24]
wire out_rimask_1290 = |_out_rimask_T_1290; // @[RegisterRouter.scala:87:24]
wire out_wimask_1290 = &_out_wimask_T_1290; // @[RegisterRouter.scala:87:24]
wire out_romask_1290 = |_out_romask_T_1290; // @[RegisterRouter.scala:87:24]
wire out_womask_1290 = &_out_womask_T_1290; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1290 = out_rivalid_1_1144 & out_rimask_1290; // @[RegisterRouter.scala:87:24]
wire _out_T_12383 = out_f_rivalid_1290; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1290 = out_roready_1_1144 & out_romask_1290; // @[RegisterRouter.scala:87:24]
wire _out_T_12384 = out_f_roready_1290; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1290 = out_wivalid_1_1144 & out_wimask_1290; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1290 = out_woready_1_1144 & out_womask_1290; // @[RegisterRouter.scala:87:24]
wire _out_T_12385 = ~out_rimask_1290; // @[RegisterRouter.scala:87:24]
wire _out_T_12386 = ~out_wimask_1290; // @[RegisterRouter.scala:87:24]
wire _out_T_12387 = ~out_romask_1290; // @[RegisterRouter.scala:87:24]
wire _out_T_12388 = ~out_womask_1290; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_1109 = {hi_406, flags_0_go, _out_prepend_T_1109}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_12389 = out_prepend_1109; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_12390 = _out_T_12389; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_1110 = _out_T_12390; // @[RegisterRouter.scala:87:24]
wire out_rimask_1291 = |_out_rimask_T_1291; // @[RegisterRouter.scala:87:24]
wire out_wimask_1291 = &_out_wimask_T_1291; // @[RegisterRouter.scala:87:24]
wire out_romask_1291 = |_out_romask_T_1291; // @[RegisterRouter.scala:87:24]
wire out_womask_1291 = &_out_womask_T_1291; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1291 = out_rivalid_1_1145 & out_rimask_1291; // @[RegisterRouter.scala:87:24]
wire _out_T_12392 = out_f_rivalid_1291; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1291 = out_roready_1_1145 & out_romask_1291; // @[RegisterRouter.scala:87:24]
wire _out_T_12393 = out_f_roready_1291; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1291 = out_wivalid_1_1145 & out_wimask_1291; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1291 = out_woready_1_1145 & out_womask_1291; // @[RegisterRouter.scala:87:24]
wire _out_T_12394 = ~out_rimask_1291; // @[RegisterRouter.scala:87:24]
wire _out_T_12395 = ~out_wimask_1291; // @[RegisterRouter.scala:87:24]
wire _out_T_12396 = ~out_romask_1291; // @[RegisterRouter.scala:87:24]
wire _out_T_12397 = ~out_womask_1291; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_1110 = {hi_407, flags_0_go, _out_prepend_T_1110}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_12398 = out_prepend_1110; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_12399 = _out_T_12398; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_1111 = _out_T_12399; // @[RegisterRouter.scala:87:24]
wire out_rimask_1292 = |_out_rimask_T_1292; // @[RegisterRouter.scala:87:24]
wire out_wimask_1292 = &_out_wimask_T_1292; // @[RegisterRouter.scala:87:24]
wire out_romask_1292 = |_out_romask_T_1292; // @[RegisterRouter.scala:87:24]
wire out_womask_1292 = &_out_womask_T_1292; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1292 = out_rivalid_1_1146 & out_rimask_1292; // @[RegisterRouter.scala:87:24]
wire _out_T_12401 = out_f_rivalid_1292; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1292 = out_roready_1_1146 & out_romask_1292; // @[RegisterRouter.scala:87:24]
wire _out_T_12402 = out_f_roready_1292; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1292 = out_wivalid_1_1146 & out_wimask_1292; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1292 = out_woready_1_1146 & out_womask_1292; // @[RegisterRouter.scala:87:24]
wire _out_T_12403 = ~out_rimask_1292; // @[RegisterRouter.scala:87:24]
wire _out_T_12404 = ~out_wimask_1292; // @[RegisterRouter.scala:87:24]
wire _out_T_12405 = ~out_romask_1292; // @[RegisterRouter.scala:87:24]
wire _out_T_12406 = ~out_womask_1292; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_1111 = {hi_408, flags_0_go, _out_prepend_T_1111}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_12407 = out_prepend_1111; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_12408 = _out_T_12407; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_178 = _out_T_12408; // @[MuxLiteral.scala:49:48]
wire out_rimask_1293 = |_out_rimask_T_1293; // @[RegisterRouter.scala:87:24]
wire out_wimask_1293 = &_out_wimask_T_1293; // @[RegisterRouter.scala:87:24]
wire out_romask_1293 = |_out_romask_T_1293; // @[RegisterRouter.scala:87:24]
wire out_womask_1293 = &_out_womask_T_1293; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1293 = out_rivalid_1_1147 & out_rimask_1293; // @[RegisterRouter.scala:87:24]
wire _out_T_12410 = out_f_rivalid_1293; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1293 = out_roready_1_1147 & out_romask_1293; // @[RegisterRouter.scala:87:24]
wire _out_T_12411 = out_f_roready_1293; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1293 = out_wivalid_1_1147 & out_wimask_1293; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1293 = out_woready_1_1147 & out_womask_1293; // @[RegisterRouter.scala:87:24]
wire _out_T_12412 = ~out_rimask_1293; // @[RegisterRouter.scala:87:24]
wire _out_T_12413 = ~out_wimask_1293; // @[RegisterRouter.scala:87:24]
wire _out_T_12414 = ~out_romask_1293; // @[RegisterRouter.scala:87:24]
wire _out_T_12415 = ~out_womask_1293; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12417 = _out_T_12416; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_1112 = _out_T_12417; // @[RegisterRouter.scala:87:24]
wire out_rimask_1294 = |_out_rimask_T_1294; // @[RegisterRouter.scala:87:24]
wire out_wimask_1294 = &_out_wimask_T_1294; // @[RegisterRouter.scala:87:24]
wire out_romask_1294 = |_out_romask_T_1294; // @[RegisterRouter.scala:87:24]
wire out_womask_1294 = &_out_womask_T_1294; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1294 = out_rivalid_1_1148 & out_rimask_1294; // @[RegisterRouter.scala:87:24]
wire _out_T_12419 = out_f_rivalid_1294; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1294 = out_roready_1_1148 & out_romask_1294; // @[RegisterRouter.scala:87:24]
wire _out_T_12420 = out_f_roready_1294; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1294 = out_wivalid_1_1148 & out_wimask_1294; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1294 = out_woready_1_1148 & out_womask_1294; // @[RegisterRouter.scala:87:24]
wire _out_T_12421 = ~out_rimask_1294; // @[RegisterRouter.scala:87:24]
wire _out_T_12422 = ~out_wimask_1294; // @[RegisterRouter.scala:87:24]
wire _out_T_12423 = ~out_romask_1294; // @[RegisterRouter.scala:87:24]
wire _out_T_12424 = ~out_womask_1294; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_1112 = {hi_282, flags_0_go, _out_prepend_T_1112}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_12425 = out_prepend_1112; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_12426 = _out_T_12425; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_1113 = _out_T_12426; // @[RegisterRouter.scala:87:24]
wire out_rimask_1295 = |_out_rimask_T_1295; // @[RegisterRouter.scala:87:24]
wire out_wimask_1295 = &_out_wimask_T_1295; // @[RegisterRouter.scala:87:24]
wire out_romask_1295 = |_out_romask_T_1295; // @[RegisterRouter.scala:87:24]
wire out_womask_1295 = &_out_womask_T_1295; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1295 = out_rivalid_1_1149 & out_rimask_1295; // @[RegisterRouter.scala:87:24]
wire _out_T_12428 = out_f_rivalid_1295; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1295 = out_roready_1_1149 & out_romask_1295; // @[RegisterRouter.scala:87:24]
wire _out_T_12429 = out_f_roready_1295; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1295 = out_wivalid_1_1149 & out_wimask_1295; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1295 = out_woready_1_1149 & out_womask_1295; // @[RegisterRouter.scala:87:24]
wire _out_T_12430 = ~out_rimask_1295; // @[RegisterRouter.scala:87:24]
wire _out_T_12431 = ~out_wimask_1295; // @[RegisterRouter.scala:87:24]
wire _out_T_12432 = ~out_romask_1295; // @[RegisterRouter.scala:87:24]
wire _out_T_12433 = ~out_womask_1295; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_1113 = {hi_283, flags_0_go, _out_prepend_T_1113}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_12434 = out_prepend_1113; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_12435 = _out_T_12434; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_1114 = _out_T_12435; // @[RegisterRouter.scala:87:24]
wire out_rimask_1296 = |_out_rimask_T_1296; // @[RegisterRouter.scala:87:24]
wire out_wimask_1296 = &_out_wimask_T_1296; // @[RegisterRouter.scala:87:24]
wire out_romask_1296 = |_out_romask_T_1296; // @[RegisterRouter.scala:87:24]
wire out_womask_1296 = &_out_womask_T_1296; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1296 = out_rivalid_1_1150 & out_rimask_1296; // @[RegisterRouter.scala:87:24]
wire _out_T_12437 = out_f_rivalid_1296; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1296 = out_roready_1_1150 & out_romask_1296; // @[RegisterRouter.scala:87:24]
wire _out_T_12438 = out_f_roready_1296; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1296 = out_wivalid_1_1150 & out_wimask_1296; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1296 = out_woready_1_1150 & out_womask_1296; // @[RegisterRouter.scala:87:24]
wire _out_T_12439 = ~out_rimask_1296; // @[RegisterRouter.scala:87:24]
wire _out_T_12440 = ~out_wimask_1296; // @[RegisterRouter.scala:87:24]
wire _out_T_12441 = ~out_romask_1296; // @[RegisterRouter.scala:87:24]
wire _out_T_12442 = ~out_womask_1296; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_1114 = {hi_284, flags_0_go, _out_prepend_T_1114}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_12443 = out_prepend_1114; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_12444 = _out_T_12443; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_1115 = _out_T_12444; // @[RegisterRouter.scala:87:24]
wire out_rimask_1297 = |_out_rimask_T_1297; // @[RegisterRouter.scala:87:24]
wire out_wimask_1297 = &_out_wimask_T_1297; // @[RegisterRouter.scala:87:24]
wire out_romask_1297 = |_out_romask_T_1297; // @[RegisterRouter.scala:87:24]
wire out_womask_1297 = &_out_womask_T_1297; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1297 = out_rivalid_1_1151 & out_rimask_1297; // @[RegisterRouter.scala:87:24]
wire _out_T_12446 = out_f_rivalid_1297; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1297 = out_roready_1_1151 & out_romask_1297; // @[RegisterRouter.scala:87:24]
wire _out_T_12447 = out_f_roready_1297; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1297 = out_wivalid_1_1151 & out_wimask_1297; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1297 = out_woready_1_1151 & out_womask_1297; // @[RegisterRouter.scala:87:24]
wire _out_T_12448 = ~out_rimask_1297; // @[RegisterRouter.scala:87:24]
wire _out_T_12449 = ~out_wimask_1297; // @[RegisterRouter.scala:87:24]
wire _out_T_12450 = ~out_romask_1297; // @[RegisterRouter.scala:87:24]
wire _out_T_12451 = ~out_womask_1297; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_1115 = {hi_285, flags_0_go, _out_prepend_T_1115}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_12452 = out_prepend_1115; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_12453 = _out_T_12452; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_1116 = _out_T_12453; // @[RegisterRouter.scala:87:24]
wire out_rimask_1298 = |_out_rimask_T_1298; // @[RegisterRouter.scala:87:24]
wire out_wimask_1298 = &_out_wimask_T_1298; // @[RegisterRouter.scala:87:24]
wire out_romask_1298 = |_out_romask_T_1298; // @[RegisterRouter.scala:87:24]
wire out_womask_1298 = &_out_womask_T_1298; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1298 = out_rivalid_1_1152 & out_rimask_1298; // @[RegisterRouter.scala:87:24]
wire _out_T_12455 = out_f_rivalid_1298; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1298 = out_roready_1_1152 & out_romask_1298; // @[RegisterRouter.scala:87:24]
wire _out_T_12456 = out_f_roready_1298; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1298 = out_wivalid_1_1152 & out_wimask_1298; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1298 = out_woready_1_1152 & out_womask_1298; // @[RegisterRouter.scala:87:24]
wire _out_T_12457 = ~out_rimask_1298; // @[RegisterRouter.scala:87:24]
wire _out_T_12458 = ~out_wimask_1298; // @[RegisterRouter.scala:87:24]
wire _out_T_12459 = ~out_romask_1298; // @[RegisterRouter.scala:87:24]
wire _out_T_12460 = ~out_womask_1298; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_1116 = {hi_286, flags_0_go, _out_prepend_T_1116}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_12461 = out_prepend_1116; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_12462 = _out_T_12461; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_1117 = _out_T_12462; // @[RegisterRouter.scala:87:24]
wire out_rimask_1299 = |_out_rimask_T_1299; // @[RegisterRouter.scala:87:24]
wire out_wimask_1299 = &_out_wimask_T_1299; // @[RegisterRouter.scala:87:24]
wire out_romask_1299 = |_out_romask_T_1299; // @[RegisterRouter.scala:87:24]
wire out_womask_1299 = &_out_womask_T_1299; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1299 = out_rivalid_1_1153 & out_rimask_1299; // @[RegisterRouter.scala:87:24]
wire _out_T_12464 = out_f_rivalid_1299; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1299 = out_roready_1_1153 & out_romask_1299; // @[RegisterRouter.scala:87:24]
wire _out_T_12465 = out_f_roready_1299; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1299 = out_wivalid_1_1153 & out_wimask_1299; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1299 = out_woready_1_1153 & out_womask_1299; // @[RegisterRouter.scala:87:24]
wire _out_T_12466 = ~out_rimask_1299; // @[RegisterRouter.scala:87:24]
wire _out_T_12467 = ~out_wimask_1299; // @[RegisterRouter.scala:87:24]
wire _out_T_12468 = ~out_romask_1299; // @[RegisterRouter.scala:87:24]
wire _out_T_12469 = ~out_womask_1299; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_1117 = {hi_287, flags_0_go, _out_prepend_T_1117}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_12470 = out_prepend_1117; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_12471 = _out_T_12470; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_1118 = _out_T_12471; // @[RegisterRouter.scala:87:24]
wire out_rimask_1300 = |_out_rimask_T_1300; // @[RegisterRouter.scala:87:24]
wire out_wimask_1300 = &_out_wimask_T_1300; // @[RegisterRouter.scala:87:24]
wire out_romask_1300 = |_out_romask_T_1300; // @[RegisterRouter.scala:87:24]
wire out_womask_1300 = &_out_womask_T_1300; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1300 = out_rivalid_1_1154 & out_rimask_1300; // @[RegisterRouter.scala:87:24]
wire _out_T_12473 = out_f_rivalid_1300; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1300 = out_roready_1_1154 & out_romask_1300; // @[RegisterRouter.scala:87:24]
wire _out_T_12474 = out_f_roready_1300; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1300 = out_wivalid_1_1154 & out_wimask_1300; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1300 = out_woready_1_1154 & out_womask_1300; // @[RegisterRouter.scala:87:24]
wire _out_T_12475 = ~out_rimask_1300; // @[RegisterRouter.scala:87:24]
wire _out_T_12476 = ~out_wimask_1300; // @[RegisterRouter.scala:87:24]
wire _out_T_12477 = ~out_romask_1300; // @[RegisterRouter.scala:87:24]
wire _out_T_12478 = ~out_womask_1300; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_1118 = {hi_288, flags_0_go, _out_prepend_T_1118}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_12479 = out_prepend_1118; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_12480 = _out_T_12479; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_163 = _out_T_12480; // @[MuxLiteral.scala:49:48]
wire out_rimask_1301 = |_out_rimask_T_1301; // @[RegisterRouter.scala:87:24]
wire out_wimask_1301 = &_out_wimask_T_1301; // @[RegisterRouter.scala:87:24]
wire out_romask_1301 = |_out_romask_T_1301; // @[RegisterRouter.scala:87:24]
wire out_womask_1301 = &_out_womask_T_1301; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1301 = out_rivalid_1_1155 & out_rimask_1301; // @[RegisterRouter.scala:87:24]
wire _out_T_12482 = out_f_rivalid_1301; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1301 = out_roready_1_1155 & out_romask_1301; // @[RegisterRouter.scala:87:24]
wire _out_T_12483 = out_f_roready_1301; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1301 = out_wivalid_1_1155 & out_wimask_1301; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1301 = out_woready_1_1155 & out_womask_1301; // @[RegisterRouter.scala:87:24]
wire _out_T_12484 = ~out_rimask_1301; // @[RegisterRouter.scala:87:24]
wire _out_T_12485 = ~out_wimask_1301; // @[RegisterRouter.scala:87:24]
wire _out_T_12486 = ~out_romask_1301; // @[RegisterRouter.scala:87:24]
wire _out_T_12487 = ~out_womask_1301; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12489 = _out_T_12488; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_1119 = _out_T_12489; // @[RegisterRouter.scala:87:24]
wire out_rimask_1302 = |_out_rimask_T_1302; // @[RegisterRouter.scala:87:24]
wire out_wimask_1302 = &_out_wimask_T_1302; // @[RegisterRouter.scala:87:24]
wire out_romask_1302 = |_out_romask_T_1302; // @[RegisterRouter.scala:87:24]
wire out_womask_1302 = &_out_womask_T_1302; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1302 = out_rivalid_1_1156 & out_rimask_1302; // @[RegisterRouter.scala:87:24]
wire _out_T_12491 = out_f_rivalid_1302; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1302 = out_roready_1_1156 & out_romask_1302; // @[RegisterRouter.scala:87:24]
wire _out_T_12492 = out_f_roready_1302; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1302 = out_wivalid_1_1156 & out_wimask_1302; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1302 = out_woready_1_1156 & out_womask_1302; // @[RegisterRouter.scala:87:24]
wire _out_T_12493 = ~out_rimask_1302; // @[RegisterRouter.scala:87:24]
wire _out_T_12494 = ~out_wimask_1302; // @[RegisterRouter.scala:87:24]
wire _out_T_12495 = ~out_romask_1302; // @[RegisterRouter.scala:87:24]
wire _out_T_12496 = ~out_womask_1302; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_1119 = {hi_578, flags_0_go, _out_prepend_T_1119}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_12497 = out_prepend_1119; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_12498 = _out_T_12497; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_1120 = _out_T_12498; // @[RegisterRouter.scala:87:24]
wire out_rimask_1303 = |_out_rimask_T_1303; // @[RegisterRouter.scala:87:24]
wire out_wimask_1303 = &_out_wimask_T_1303; // @[RegisterRouter.scala:87:24]
wire out_romask_1303 = |_out_romask_T_1303; // @[RegisterRouter.scala:87:24]
wire out_womask_1303 = &_out_womask_T_1303; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1303 = out_rivalid_1_1157 & out_rimask_1303; // @[RegisterRouter.scala:87:24]
wire _out_T_12500 = out_f_rivalid_1303; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1303 = out_roready_1_1157 & out_romask_1303; // @[RegisterRouter.scala:87:24]
wire _out_T_12501 = out_f_roready_1303; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1303 = out_wivalid_1_1157 & out_wimask_1303; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1303 = out_woready_1_1157 & out_womask_1303; // @[RegisterRouter.scala:87:24]
wire _out_T_12502 = ~out_rimask_1303; // @[RegisterRouter.scala:87:24]
wire _out_T_12503 = ~out_wimask_1303; // @[RegisterRouter.scala:87:24]
wire _out_T_12504 = ~out_romask_1303; // @[RegisterRouter.scala:87:24]
wire _out_T_12505 = ~out_womask_1303; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_1120 = {hi_579, flags_0_go, _out_prepend_T_1120}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_12506 = out_prepend_1120; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_12507 = _out_T_12506; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_1121 = _out_T_12507; // @[RegisterRouter.scala:87:24]
wire out_rimask_1304 = |_out_rimask_T_1304; // @[RegisterRouter.scala:87:24]
wire out_wimask_1304 = &_out_wimask_T_1304; // @[RegisterRouter.scala:87:24]
wire out_romask_1304 = |_out_romask_T_1304; // @[RegisterRouter.scala:87:24]
wire out_womask_1304 = &_out_womask_T_1304; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1304 = out_rivalid_1_1158 & out_rimask_1304; // @[RegisterRouter.scala:87:24]
wire _out_T_12509 = out_f_rivalid_1304; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1304 = out_roready_1_1158 & out_romask_1304; // @[RegisterRouter.scala:87:24]
wire _out_T_12510 = out_f_roready_1304; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1304 = out_wivalid_1_1158 & out_wimask_1304; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1304 = out_woready_1_1158 & out_womask_1304; // @[RegisterRouter.scala:87:24]
wire _out_T_12511 = ~out_rimask_1304; // @[RegisterRouter.scala:87:24]
wire _out_T_12512 = ~out_wimask_1304; // @[RegisterRouter.scala:87:24]
wire _out_T_12513 = ~out_romask_1304; // @[RegisterRouter.scala:87:24]
wire _out_T_12514 = ~out_womask_1304; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_1121 = {hi_580, flags_0_go, _out_prepend_T_1121}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_12515 = out_prepend_1121; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_12516 = _out_T_12515; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_1122 = _out_T_12516; // @[RegisterRouter.scala:87:24]
wire out_rimask_1305 = |_out_rimask_T_1305; // @[RegisterRouter.scala:87:24]
wire out_wimask_1305 = &_out_wimask_T_1305; // @[RegisterRouter.scala:87:24]
wire out_romask_1305 = |_out_romask_T_1305; // @[RegisterRouter.scala:87:24]
wire out_womask_1305 = &_out_womask_T_1305; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1305 = out_rivalid_1_1159 & out_rimask_1305; // @[RegisterRouter.scala:87:24]
wire _out_T_12518 = out_f_rivalid_1305; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1305 = out_roready_1_1159 & out_romask_1305; // @[RegisterRouter.scala:87:24]
wire _out_T_12519 = out_f_roready_1305; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1305 = out_wivalid_1_1159 & out_wimask_1305; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1305 = out_woready_1_1159 & out_womask_1305; // @[RegisterRouter.scala:87:24]
wire _out_T_12520 = ~out_rimask_1305; // @[RegisterRouter.scala:87:24]
wire _out_T_12521 = ~out_wimask_1305; // @[RegisterRouter.scala:87:24]
wire _out_T_12522 = ~out_romask_1305; // @[RegisterRouter.scala:87:24]
wire _out_T_12523 = ~out_womask_1305; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_1122 = {hi_581, flags_0_go, _out_prepend_T_1122}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_12524 = out_prepend_1122; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_12525 = _out_T_12524; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_1123 = _out_T_12525; // @[RegisterRouter.scala:87:24]
wire out_rimask_1306 = |_out_rimask_T_1306; // @[RegisterRouter.scala:87:24]
wire out_wimask_1306 = &_out_wimask_T_1306; // @[RegisterRouter.scala:87:24]
wire out_romask_1306 = |_out_romask_T_1306; // @[RegisterRouter.scala:87:24]
wire out_womask_1306 = &_out_womask_T_1306; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1306 = out_rivalid_1_1160 & out_rimask_1306; // @[RegisterRouter.scala:87:24]
wire _out_T_12527 = out_f_rivalid_1306; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1306 = out_roready_1_1160 & out_romask_1306; // @[RegisterRouter.scala:87:24]
wire _out_T_12528 = out_f_roready_1306; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1306 = out_wivalid_1_1160 & out_wimask_1306; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1306 = out_woready_1_1160 & out_womask_1306; // @[RegisterRouter.scala:87:24]
wire _out_T_12529 = ~out_rimask_1306; // @[RegisterRouter.scala:87:24]
wire _out_T_12530 = ~out_wimask_1306; // @[RegisterRouter.scala:87:24]
wire _out_T_12531 = ~out_romask_1306; // @[RegisterRouter.scala:87:24]
wire _out_T_12532 = ~out_womask_1306; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_1123 = {hi_582, flags_0_go, _out_prepend_T_1123}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_12533 = out_prepend_1123; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_12534 = _out_T_12533; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_1124 = _out_T_12534; // @[RegisterRouter.scala:87:24]
wire out_rimask_1307 = |_out_rimask_T_1307; // @[RegisterRouter.scala:87:24]
wire out_wimask_1307 = &_out_wimask_T_1307; // @[RegisterRouter.scala:87:24]
wire out_romask_1307 = |_out_romask_T_1307; // @[RegisterRouter.scala:87:24]
wire out_womask_1307 = &_out_womask_T_1307; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1307 = out_rivalid_1_1161 & out_rimask_1307; // @[RegisterRouter.scala:87:24]
wire _out_T_12536 = out_f_rivalid_1307; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1307 = out_roready_1_1161 & out_romask_1307; // @[RegisterRouter.scala:87:24]
wire _out_T_12537 = out_f_roready_1307; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1307 = out_wivalid_1_1161 & out_wimask_1307; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1307 = out_woready_1_1161 & out_womask_1307; // @[RegisterRouter.scala:87:24]
wire _out_T_12538 = ~out_rimask_1307; // @[RegisterRouter.scala:87:24]
wire _out_T_12539 = ~out_wimask_1307; // @[RegisterRouter.scala:87:24]
wire _out_T_12540 = ~out_romask_1307; // @[RegisterRouter.scala:87:24]
wire _out_T_12541 = ~out_womask_1307; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_1124 = {hi_583, flags_0_go, _out_prepend_T_1124}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_12542 = out_prepend_1124; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_12543 = _out_T_12542; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_1125 = _out_T_12543; // @[RegisterRouter.scala:87:24]
wire out_rimask_1308 = |_out_rimask_T_1308; // @[RegisterRouter.scala:87:24]
wire out_wimask_1308 = &_out_wimask_T_1308; // @[RegisterRouter.scala:87:24]
wire out_romask_1308 = |_out_romask_T_1308; // @[RegisterRouter.scala:87:24]
wire out_womask_1308 = &_out_womask_T_1308; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1308 = out_rivalid_1_1162 & out_rimask_1308; // @[RegisterRouter.scala:87:24]
wire _out_T_12545 = out_f_rivalid_1308; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1308 = out_roready_1_1162 & out_romask_1308; // @[RegisterRouter.scala:87:24]
wire _out_T_12546 = out_f_roready_1308; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1308 = out_wivalid_1_1162 & out_wimask_1308; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1308 = out_woready_1_1162 & out_womask_1308; // @[RegisterRouter.scala:87:24]
wire _out_T_12547 = ~out_rimask_1308; // @[RegisterRouter.scala:87:24]
wire _out_T_12548 = ~out_wimask_1308; // @[RegisterRouter.scala:87:24]
wire _out_T_12549 = ~out_romask_1308; // @[RegisterRouter.scala:87:24]
wire _out_T_12550 = ~out_womask_1308; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_1125 = {hi_584, flags_0_go, _out_prepend_T_1125}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_12551 = out_prepend_1125; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_12552 = _out_T_12551; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_200 = _out_T_12552; // @[MuxLiteral.scala:49:48]
wire out_rimask_1309 = |_out_rimask_T_1309; // @[RegisterRouter.scala:87:24]
wire out_wimask_1309 = &_out_wimask_T_1309; // @[RegisterRouter.scala:87:24]
wire out_romask_1309 = |_out_romask_T_1309; // @[RegisterRouter.scala:87:24]
wire out_womask_1309 = &_out_womask_T_1309; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1309 = out_rivalid_1_1163 & out_rimask_1309; // @[RegisterRouter.scala:87:24]
wire _out_T_12554 = out_f_rivalid_1309; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1309 = out_roready_1_1163 & out_romask_1309; // @[RegisterRouter.scala:87:24]
wire _out_T_12555 = out_f_roready_1309; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1309 = out_wivalid_1_1163 & out_wimask_1309; // @[RegisterRouter.scala:87:24]
wire _out_T_12556 = out_f_wivalid_1309; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1309 = out_woready_1_1163 & out_womask_1309; // @[RegisterRouter.scala:87:24]
wire _out_T_12557 = out_f_woready_1309; // @[RegisterRouter.scala:87:24]
wire _out_T_12558 = ~out_rimask_1309; // @[RegisterRouter.scala:87:24]
wire _out_T_12559 = ~out_wimask_1309; // @[RegisterRouter.scala:87:24]
wire _out_T_12560 = ~out_romask_1309; // @[RegisterRouter.scala:87:24]
wire _out_T_12561 = ~out_womask_1309; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12563 = _out_T_12562; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_1126 = _out_T_12563; // @[RegisterRouter.scala:87:24]
wire out_rimask_1310 = |_out_rimask_T_1310; // @[RegisterRouter.scala:87:24]
wire out_wimask_1310 = &_out_wimask_T_1310; // @[RegisterRouter.scala:87:24]
wire out_romask_1310 = |_out_romask_T_1310; // @[RegisterRouter.scala:87:24]
wire out_womask_1310 = &_out_womask_T_1310; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1310 = out_rivalid_1_1164 & out_rimask_1310; // @[RegisterRouter.scala:87:24]
wire _out_T_12565 = out_f_rivalid_1310; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1310 = out_roready_1_1164 & out_romask_1310; // @[RegisterRouter.scala:87:24]
wire _out_T_12566 = out_f_roready_1310; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1310 = out_wivalid_1_1164 & out_wimask_1310; // @[RegisterRouter.scala:87:24]
wire _out_T_12567 = out_f_wivalid_1310; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1310 = out_woready_1_1164 & out_womask_1310; // @[RegisterRouter.scala:87:24]
wire _out_T_12568 = out_f_woready_1310; // @[RegisterRouter.scala:87:24]
wire _out_T_12569 = ~out_rimask_1310; // @[RegisterRouter.scala:87:24]
wire _out_T_12570 = ~out_wimask_1310; // @[RegisterRouter.scala:87:24]
wire _out_T_12571 = ~out_romask_1310; // @[RegisterRouter.scala:87:24]
wire _out_T_12572 = ~out_womask_1310; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_1126 = {programBufferMem_57, _out_prepend_T_1126}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_12573 = out_prepend_1126; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_12574 = _out_T_12573; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_1127 = _out_T_12574; // @[RegisterRouter.scala:87:24]
wire out_rimask_1311 = |_out_rimask_T_1311; // @[RegisterRouter.scala:87:24]
wire out_wimask_1311 = &_out_wimask_T_1311; // @[RegisterRouter.scala:87:24]
wire out_romask_1311 = |_out_romask_T_1311; // @[RegisterRouter.scala:87:24]
wire out_womask_1311 = &_out_womask_T_1311; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1311 = out_rivalid_1_1165 & out_rimask_1311; // @[RegisterRouter.scala:87:24]
wire _out_T_12576 = out_f_rivalid_1311; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1311 = out_roready_1_1165 & out_romask_1311; // @[RegisterRouter.scala:87:24]
wire _out_T_12577 = out_f_roready_1311; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1311 = out_wivalid_1_1165 & out_wimask_1311; // @[RegisterRouter.scala:87:24]
wire _out_T_12578 = out_f_wivalid_1311; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1311 = out_woready_1_1165 & out_womask_1311; // @[RegisterRouter.scala:87:24]
wire _out_T_12579 = out_f_woready_1311; // @[RegisterRouter.scala:87:24]
wire _out_T_12580 = ~out_rimask_1311; // @[RegisterRouter.scala:87:24]
wire _out_T_12581 = ~out_wimask_1311; // @[RegisterRouter.scala:87:24]
wire _out_T_12582 = ~out_romask_1311; // @[RegisterRouter.scala:87:24]
wire _out_T_12583 = ~out_womask_1311; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_1127 = {programBufferMem_58, _out_prepend_T_1127}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_12584 = out_prepend_1127; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_12585 = _out_T_12584; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_1128 = _out_T_12585; // @[RegisterRouter.scala:87:24]
wire out_rimask_1312 = |_out_rimask_T_1312; // @[RegisterRouter.scala:87:24]
wire out_wimask_1312 = &_out_wimask_T_1312; // @[RegisterRouter.scala:87:24]
wire out_romask_1312 = |_out_romask_T_1312; // @[RegisterRouter.scala:87:24]
wire out_womask_1312 = &_out_womask_T_1312; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1312 = out_rivalid_1_1166 & out_rimask_1312; // @[RegisterRouter.scala:87:24]
wire _out_T_12587 = out_f_rivalid_1312; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1312 = out_roready_1_1166 & out_romask_1312; // @[RegisterRouter.scala:87:24]
wire _out_T_12588 = out_f_roready_1312; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1312 = out_wivalid_1_1166 & out_wimask_1312; // @[RegisterRouter.scala:87:24]
wire _out_T_12589 = out_f_wivalid_1312; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1312 = out_woready_1_1166 & out_womask_1312; // @[RegisterRouter.scala:87:24]
wire _out_T_12590 = out_f_woready_1312; // @[RegisterRouter.scala:87:24]
wire _out_T_12591 = ~out_rimask_1312; // @[RegisterRouter.scala:87:24]
wire _out_T_12592 = ~out_wimask_1312; // @[RegisterRouter.scala:87:24]
wire _out_T_12593 = ~out_romask_1312; // @[RegisterRouter.scala:87:24]
wire _out_T_12594 = ~out_womask_1312; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_1128 = {programBufferMem_59, _out_prepend_T_1128}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_12595 = out_prepend_1128; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_12596 = _out_T_12595; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_1129 = _out_T_12596; // @[RegisterRouter.scala:87:24]
wire out_rimask_1313 = |_out_rimask_T_1313; // @[RegisterRouter.scala:87:24]
wire out_wimask_1313 = &_out_wimask_T_1313; // @[RegisterRouter.scala:87:24]
wire out_romask_1313 = |_out_romask_T_1313; // @[RegisterRouter.scala:87:24]
wire out_womask_1313 = &_out_womask_T_1313; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1313 = out_rivalid_1_1167 & out_rimask_1313; // @[RegisterRouter.scala:87:24]
wire _out_T_12598 = out_f_rivalid_1313; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1313 = out_roready_1_1167 & out_romask_1313; // @[RegisterRouter.scala:87:24]
wire _out_T_12599 = out_f_roready_1313; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1313 = out_wivalid_1_1167 & out_wimask_1313; // @[RegisterRouter.scala:87:24]
wire _out_T_12600 = out_f_wivalid_1313; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1313 = out_woready_1_1167 & out_womask_1313; // @[RegisterRouter.scala:87:24]
wire _out_T_12601 = out_f_woready_1313; // @[RegisterRouter.scala:87:24]
wire _out_T_12602 = ~out_rimask_1313; // @[RegisterRouter.scala:87:24]
wire _out_T_12603 = ~out_wimask_1313; // @[RegisterRouter.scala:87:24]
wire _out_T_12604 = ~out_romask_1313; // @[RegisterRouter.scala:87:24]
wire _out_T_12605 = ~out_womask_1313; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_1129 = {programBufferMem_60, _out_prepend_T_1129}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_12606 = out_prepend_1129; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_12607 = _out_T_12606; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_1130 = _out_T_12607; // @[RegisterRouter.scala:87:24]
wire out_rimask_1314 = |_out_rimask_T_1314; // @[RegisterRouter.scala:87:24]
wire out_wimask_1314 = &_out_wimask_T_1314; // @[RegisterRouter.scala:87:24]
wire out_romask_1314 = |_out_romask_T_1314; // @[RegisterRouter.scala:87:24]
wire out_womask_1314 = &_out_womask_T_1314; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1314 = out_rivalid_1_1168 & out_rimask_1314; // @[RegisterRouter.scala:87:24]
wire _out_T_12609 = out_f_rivalid_1314; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1314 = out_roready_1_1168 & out_romask_1314; // @[RegisterRouter.scala:87:24]
wire _out_T_12610 = out_f_roready_1314; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1314 = out_wivalid_1_1168 & out_wimask_1314; // @[RegisterRouter.scala:87:24]
wire _out_T_12611 = out_f_wivalid_1314; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1314 = out_woready_1_1168 & out_womask_1314; // @[RegisterRouter.scala:87:24]
wire _out_T_12612 = out_f_woready_1314; // @[RegisterRouter.scala:87:24]
wire _out_T_12613 = ~out_rimask_1314; // @[RegisterRouter.scala:87:24]
wire _out_T_12614 = ~out_wimask_1314; // @[RegisterRouter.scala:87:24]
wire _out_T_12615 = ~out_romask_1314; // @[RegisterRouter.scala:87:24]
wire _out_T_12616 = ~out_womask_1314; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_1130 = {programBufferMem_61, _out_prepend_T_1130}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_12617 = out_prepend_1130; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_12618 = _out_T_12617; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_1131 = _out_T_12618; // @[RegisterRouter.scala:87:24]
wire out_rimask_1315 = |_out_rimask_T_1315; // @[RegisterRouter.scala:87:24]
wire out_wimask_1315 = &_out_wimask_T_1315; // @[RegisterRouter.scala:87:24]
wire out_romask_1315 = |_out_romask_T_1315; // @[RegisterRouter.scala:87:24]
wire out_womask_1315 = &_out_womask_T_1315; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1315 = out_rivalid_1_1169 & out_rimask_1315; // @[RegisterRouter.scala:87:24]
wire _out_T_12620 = out_f_rivalid_1315; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1315 = out_roready_1_1169 & out_romask_1315; // @[RegisterRouter.scala:87:24]
wire _out_T_12621 = out_f_roready_1315; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1315 = out_wivalid_1_1169 & out_wimask_1315; // @[RegisterRouter.scala:87:24]
wire _out_T_12622 = out_f_wivalid_1315; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1315 = out_woready_1_1169 & out_womask_1315; // @[RegisterRouter.scala:87:24]
wire _out_T_12623 = out_f_woready_1315; // @[RegisterRouter.scala:87:24]
wire _out_T_12624 = ~out_rimask_1315; // @[RegisterRouter.scala:87:24]
wire _out_T_12625 = ~out_wimask_1315; // @[RegisterRouter.scala:87:24]
wire _out_T_12626 = ~out_romask_1315; // @[RegisterRouter.scala:87:24]
wire _out_T_12627 = ~out_womask_1315; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_1131 = {programBufferMem_62, _out_prepend_T_1131}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_12628 = out_prepend_1131; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_12629 = _out_T_12628; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_1132 = _out_T_12629; // @[RegisterRouter.scala:87:24]
wire out_rimask_1316 = |_out_rimask_T_1316; // @[RegisterRouter.scala:87:24]
wire out_wimask_1316 = &_out_wimask_T_1316; // @[RegisterRouter.scala:87:24]
wire out_romask_1316 = |_out_romask_T_1316; // @[RegisterRouter.scala:87:24]
wire out_womask_1316 = &_out_womask_T_1316; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1316 = out_rivalid_1_1170 & out_rimask_1316; // @[RegisterRouter.scala:87:24]
wire _out_T_12631 = out_f_rivalid_1316; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1316 = out_roready_1_1170 & out_romask_1316; // @[RegisterRouter.scala:87:24]
wire _out_T_12632 = out_f_roready_1316; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1316 = out_wivalid_1_1170 & out_wimask_1316; // @[RegisterRouter.scala:87:24]
wire _out_T_12633 = out_f_wivalid_1316; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1316 = out_woready_1_1170 & out_womask_1316; // @[RegisterRouter.scala:87:24]
wire _out_T_12634 = out_f_woready_1316; // @[RegisterRouter.scala:87:24]
wire _out_T_12635 = ~out_rimask_1316; // @[RegisterRouter.scala:87:24]
wire _out_T_12636 = ~out_wimask_1316; // @[RegisterRouter.scala:87:24]
wire _out_T_12637 = ~out_romask_1316; // @[RegisterRouter.scala:87:24]
wire _out_T_12638 = ~out_womask_1316; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_1132 = {programBufferMem_63, _out_prepend_T_1132}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_12639 = out_prepend_1132; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_12640 = _out_T_12639; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_111 = _out_T_12640; // @[MuxLiteral.scala:49:48]
wire out_rimask_1317 = |_out_rimask_T_1317; // @[RegisterRouter.scala:87:24]
wire out_wimask_1317 = &_out_wimask_T_1317; // @[RegisterRouter.scala:87:24]
wire out_romask_1317 = |_out_romask_T_1317; // @[RegisterRouter.scala:87:24]
wire out_womask_1317 = &_out_womask_T_1317; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1317 = out_rivalid_1_1171 & out_rimask_1317; // @[RegisterRouter.scala:87:24]
wire _out_T_12642 = out_f_rivalid_1317; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1317 = out_roready_1_1171 & out_romask_1317; // @[RegisterRouter.scala:87:24]
wire _out_T_12643 = out_f_roready_1317; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1317 = out_wivalid_1_1171 & out_wimask_1317; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1317 = out_woready_1_1171 & out_womask_1317; // @[RegisterRouter.scala:87:24]
wire _out_T_12644 = ~out_rimask_1317; // @[RegisterRouter.scala:87:24]
wire _out_T_12645 = ~out_wimask_1317; // @[RegisterRouter.scala:87:24]
wire _out_T_12646 = ~out_romask_1317; // @[RegisterRouter.scala:87:24]
wire _out_T_12647 = ~out_womask_1317; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12649 = _out_T_12648; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_1133 = _out_T_12649; // @[RegisterRouter.scala:87:24]
wire out_rimask_1318 = |_out_rimask_T_1318; // @[RegisterRouter.scala:87:24]
wire out_wimask_1318 = &_out_wimask_T_1318; // @[RegisterRouter.scala:87:24]
wire out_romask_1318 = |_out_romask_T_1318; // @[RegisterRouter.scala:87:24]
wire out_womask_1318 = &_out_womask_T_1318; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1318 = out_rivalid_1_1172 & out_rimask_1318; // @[RegisterRouter.scala:87:24]
wire _out_T_12651 = out_f_rivalid_1318; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1318 = out_roready_1_1172 & out_romask_1318; // @[RegisterRouter.scala:87:24]
wire _out_T_12652 = out_f_roready_1318; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1318 = out_wivalid_1_1172 & out_wimask_1318; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1318 = out_woready_1_1172 & out_womask_1318; // @[RegisterRouter.scala:87:24]
wire _out_T_12653 = ~out_rimask_1318; // @[RegisterRouter.scala:87:24]
wire _out_T_12654 = ~out_wimask_1318; // @[RegisterRouter.scala:87:24]
wire _out_T_12655 = ~out_romask_1318; // @[RegisterRouter.scala:87:24]
wire _out_T_12656 = ~out_womask_1318; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_1133 = {hi_698, flags_0_go, _out_prepend_T_1133}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_12657 = out_prepend_1133; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_12658 = _out_T_12657; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_1134 = _out_T_12658; // @[RegisterRouter.scala:87:24]
wire out_rimask_1319 = |_out_rimask_T_1319; // @[RegisterRouter.scala:87:24]
wire out_wimask_1319 = &_out_wimask_T_1319; // @[RegisterRouter.scala:87:24]
wire out_romask_1319 = |_out_romask_T_1319; // @[RegisterRouter.scala:87:24]
wire out_womask_1319 = &_out_womask_T_1319; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1319 = out_rivalid_1_1173 & out_rimask_1319; // @[RegisterRouter.scala:87:24]
wire _out_T_12660 = out_f_rivalid_1319; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1319 = out_roready_1_1173 & out_romask_1319; // @[RegisterRouter.scala:87:24]
wire _out_T_12661 = out_f_roready_1319; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1319 = out_wivalid_1_1173 & out_wimask_1319; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1319 = out_woready_1_1173 & out_womask_1319; // @[RegisterRouter.scala:87:24]
wire _out_T_12662 = ~out_rimask_1319; // @[RegisterRouter.scala:87:24]
wire _out_T_12663 = ~out_wimask_1319; // @[RegisterRouter.scala:87:24]
wire _out_T_12664 = ~out_romask_1319; // @[RegisterRouter.scala:87:24]
wire _out_T_12665 = ~out_womask_1319; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_1134 = {hi_699, flags_0_go, _out_prepend_T_1134}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_12666 = out_prepend_1134; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_12667 = _out_T_12666; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_1135 = _out_T_12667; // @[RegisterRouter.scala:87:24]
wire out_rimask_1320 = |_out_rimask_T_1320; // @[RegisterRouter.scala:87:24]
wire out_wimask_1320 = &_out_wimask_T_1320; // @[RegisterRouter.scala:87:24]
wire out_romask_1320 = |_out_romask_T_1320; // @[RegisterRouter.scala:87:24]
wire out_womask_1320 = &_out_womask_T_1320; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1320 = out_rivalid_1_1174 & out_rimask_1320; // @[RegisterRouter.scala:87:24]
wire _out_T_12669 = out_f_rivalid_1320; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1320 = out_roready_1_1174 & out_romask_1320; // @[RegisterRouter.scala:87:24]
wire _out_T_12670 = out_f_roready_1320; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1320 = out_wivalid_1_1174 & out_wimask_1320; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1320 = out_woready_1_1174 & out_womask_1320; // @[RegisterRouter.scala:87:24]
wire _out_T_12671 = ~out_rimask_1320; // @[RegisterRouter.scala:87:24]
wire _out_T_12672 = ~out_wimask_1320; // @[RegisterRouter.scala:87:24]
wire _out_T_12673 = ~out_romask_1320; // @[RegisterRouter.scala:87:24]
wire _out_T_12674 = ~out_womask_1320; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_1135 = {hi_700, flags_0_go, _out_prepend_T_1135}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_12675 = out_prepend_1135; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_12676 = _out_T_12675; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_1136 = _out_T_12676; // @[RegisterRouter.scala:87:24]
wire out_rimask_1321 = |_out_rimask_T_1321; // @[RegisterRouter.scala:87:24]
wire out_wimask_1321 = &_out_wimask_T_1321; // @[RegisterRouter.scala:87:24]
wire out_romask_1321 = |_out_romask_T_1321; // @[RegisterRouter.scala:87:24]
wire out_womask_1321 = &_out_womask_T_1321; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1321 = out_rivalid_1_1175 & out_rimask_1321; // @[RegisterRouter.scala:87:24]
wire _out_T_12678 = out_f_rivalid_1321; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1321 = out_roready_1_1175 & out_romask_1321; // @[RegisterRouter.scala:87:24]
wire _out_T_12679 = out_f_roready_1321; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1321 = out_wivalid_1_1175 & out_wimask_1321; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1321 = out_woready_1_1175 & out_womask_1321; // @[RegisterRouter.scala:87:24]
wire _out_T_12680 = ~out_rimask_1321; // @[RegisterRouter.scala:87:24]
wire _out_T_12681 = ~out_wimask_1321; // @[RegisterRouter.scala:87:24]
wire _out_T_12682 = ~out_romask_1321; // @[RegisterRouter.scala:87:24]
wire _out_T_12683 = ~out_womask_1321; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_1136 = {hi_701, flags_0_go, _out_prepend_T_1136}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_12684 = out_prepend_1136; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_12685 = _out_T_12684; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_1137 = _out_T_12685; // @[RegisterRouter.scala:87:24]
wire out_rimask_1322 = |_out_rimask_T_1322; // @[RegisterRouter.scala:87:24]
wire out_wimask_1322 = &_out_wimask_T_1322; // @[RegisterRouter.scala:87:24]
wire out_romask_1322 = |_out_romask_T_1322; // @[RegisterRouter.scala:87:24]
wire out_womask_1322 = &_out_womask_T_1322; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1322 = out_rivalid_1_1176 & out_rimask_1322; // @[RegisterRouter.scala:87:24]
wire _out_T_12687 = out_f_rivalid_1322; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1322 = out_roready_1_1176 & out_romask_1322; // @[RegisterRouter.scala:87:24]
wire _out_T_12688 = out_f_roready_1322; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1322 = out_wivalid_1_1176 & out_wimask_1322; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1322 = out_woready_1_1176 & out_womask_1322; // @[RegisterRouter.scala:87:24]
wire _out_T_12689 = ~out_rimask_1322; // @[RegisterRouter.scala:87:24]
wire _out_T_12690 = ~out_wimask_1322; // @[RegisterRouter.scala:87:24]
wire _out_T_12691 = ~out_romask_1322; // @[RegisterRouter.scala:87:24]
wire _out_T_12692 = ~out_womask_1322; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_1137 = {hi_702, flags_0_go, _out_prepend_T_1137}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_12693 = out_prepend_1137; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_12694 = _out_T_12693; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_1138 = _out_T_12694; // @[RegisterRouter.scala:87:24]
wire out_rimask_1323 = |_out_rimask_T_1323; // @[RegisterRouter.scala:87:24]
wire out_wimask_1323 = &_out_wimask_T_1323; // @[RegisterRouter.scala:87:24]
wire out_romask_1323 = |_out_romask_T_1323; // @[RegisterRouter.scala:87:24]
wire out_womask_1323 = &_out_womask_T_1323; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1323 = out_rivalid_1_1177 & out_rimask_1323; // @[RegisterRouter.scala:87:24]
wire _out_T_12696 = out_f_rivalid_1323; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1323 = out_roready_1_1177 & out_romask_1323; // @[RegisterRouter.scala:87:24]
wire _out_T_12697 = out_f_roready_1323; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1323 = out_wivalid_1_1177 & out_wimask_1323; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1323 = out_woready_1_1177 & out_womask_1323; // @[RegisterRouter.scala:87:24]
wire _out_T_12698 = ~out_rimask_1323; // @[RegisterRouter.scala:87:24]
wire _out_T_12699 = ~out_wimask_1323; // @[RegisterRouter.scala:87:24]
wire _out_T_12700 = ~out_romask_1323; // @[RegisterRouter.scala:87:24]
wire _out_T_12701 = ~out_womask_1323; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_1138 = {hi_703, flags_0_go, _out_prepend_T_1138}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_12702 = out_prepend_1138; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_12703 = _out_T_12702; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_1139 = _out_T_12703; // @[RegisterRouter.scala:87:24]
wire out_rimask_1324 = |_out_rimask_T_1324; // @[RegisterRouter.scala:87:24]
wire out_wimask_1324 = &_out_wimask_T_1324; // @[RegisterRouter.scala:87:24]
wire out_romask_1324 = |_out_romask_T_1324; // @[RegisterRouter.scala:87:24]
wire out_womask_1324 = &_out_womask_T_1324; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1324 = out_rivalid_1_1178 & out_rimask_1324; // @[RegisterRouter.scala:87:24]
wire _out_T_12705 = out_f_rivalid_1324; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1324 = out_roready_1_1178 & out_romask_1324; // @[RegisterRouter.scala:87:24]
wire _out_T_12706 = out_f_roready_1324; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1324 = out_wivalid_1_1178 & out_wimask_1324; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1324 = out_woready_1_1178 & out_womask_1324; // @[RegisterRouter.scala:87:24]
wire _out_T_12707 = ~out_rimask_1324; // @[RegisterRouter.scala:87:24]
wire _out_T_12708 = ~out_wimask_1324; // @[RegisterRouter.scala:87:24]
wire _out_T_12709 = ~out_romask_1324; // @[RegisterRouter.scala:87:24]
wire _out_T_12710 = ~out_womask_1324; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_1139 = {hi_704, flags_0_go, _out_prepend_T_1139}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_12711 = out_prepend_1139; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_12712 = _out_T_12711; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_215 = _out_T_12712; // @[MuxLiteral.scala:49:48]
wire out_rimask_1325 = |_out_rimask_T_1325; // @[RegisterRouter.scala:87:24]
wire out_wimask_1325 = &_out_wimask_T_1325; // @[RegisterRouter.scala:87:24]
wire out_romask_1325 = |_out_romask_T_1325; // @[RegisterRouter.scala:87:24]
wire out_womask_1325 = &_out_womask_T_1325; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1325 = out_rivalid_1_1179 & out_rimask_1325; // @[RegisterRouter.scala:87:24]
wire _out_T_12714 = out_f_rivalid_1325; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1325 = out_roready_1_1179 & out_romask_1325; // @[RegisterRouter.scala:87:24]
wire _out_T_12715 = out_f_roready_1325; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1325 = out_wivalid_1_1179 & out_wimask_1325; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1325 = out_woready_1_1179 & out_womask_1325; // @[RegisterRouter.scala:87:24]
wire _out_T_12716 = ~out_rimask_1325; // @[RegisterRouter.scala:87:24]
wire _out_T_12717 = ~out_wimask_1325; // @[RegisterRouter.scala:87:24]
wire _out_T_12718 = ~out_romask_1325; // @[RegisterRouter.scala:87:24]
wire _out_T_12719 = ~out_womask_1325; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12721 = _out_T_12720; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_1140 = _out_T_12721; // @[RegisterRouter.scala:87:24]
wire out_rimask_1326 = |_out_rimask_T_1326; // @[RegisterRouter.scala:87:24]
wire out_wimask_1326 = &_out_wimask_T_1326; // @[RegisterRouter.scala:87:24]
wire out_romask_1326 = |_out_romask_T_1326; // @[RegisterRouter.scala:87:24]
wire out_womask_1326 = &_out_womask_T_1326; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1326 = out_rivalid_1_1180 & out_rimask_1326; // @[RegisterRouter.scala:87:24]
wire _out_T_12723 = out_f_rivalid_1326; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1326 = out_roready_1_1180 & out_romask_1326; // @[RegisterRouter.scala:87:24]
wire _out_T_12724 = out_f_roready_1326; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1326 = out_wivalid_1_1180 & out_wimask_1326; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1326 = out_woready_1_1180 & out_womask_1326; // @[RegisterRouter.scala:87:24]
wire _out_T_12725 = ~out_rimask_1326; // @[RegisterRouter.scala:87:24]
wire _out_T_12726 = ~out_wimask_1326; // @[RegisterRouter.scala:87:24]
wire _out_T_12727 = ~out_romask_1326; // @[RegisterRouter.scala:87:24]
wire _out_T_12728 = ~out_womask_1326; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_1140 = {hi_754, flags_0_go, _out_prepend_T_1140}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_12729 = out_prepend_1140; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_12730 = _out_T_12729; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_1141 = _out_T_12730; // @[RegisterRouter.scala:87:24]
wire out_rimask_1327 = |_out_rimask_T_1327; // @[RegisterRouter.scala:87:24]
wire out_wimask_1327 = &_out_wimask_T_1327; // @[RegisterRouter.scala:87:24]
wire out_romask_1327 = |_out_romask_T_1327; // @[RegisterRouter.scala:87:24]
wire out_womask_1327 = &_out_womask_T_1327; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1327 = out_rivalid_1_1181 & out_rimask_1327; // @[RegisterRouter.scala:87:24]
wire _out_T_12732 = out_f_rivalid_1327; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1327 = out_roready_1_1181 & out_romask_1327; // @[RegisterRouter.scala:87:24]
wire _out_T_12733 = out_f_roready_1327; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1327 = out_wivalid_1_1181 & out_wimask_1327; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1327 = out_woready_1_1181 & out_womask_1327; // @[RegisterRouter.scala:87:24]
wire _out_T_12734 = ~out_rimask_1327; // @[RegisterRouter.scala:87:24]
wire _out_T_12735 = ~out_wimask_1327; // @[RegisterRouter.scala:87:24]
wire _out_T_12736 = ~out_romask_1327; // @[RegisterRouter.scala:87:24]
wire _out_T_12737 = ~out_womask_1327; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_1141 = {hi_755, flags_0_go, _out_prepend_T_1141}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_12738 = out_prepend_1141; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_12739 = _out_T_12738; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_1142 = _out_T_12739; // @[RegisterRouter.scala:87:24]
wire out_rimask_1328 = |_out_rimask_T_1328; // @[RegisterRouter.scala:87:24]
wire out_wimask_1328 = &_out_wimask_T_1328; // @[RegisterRouter.scala:87:24]
wire out_romask_1328 = |_out_romask_T_1328; // @[RegisterRouter.scala:87:24]
wire out_womask_1328 = &_out_womask_T_1328; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1328 = out_rivalid_1_1182 & out_rimask_1328; // @[RegisterRouter.scala:87:24]
wire _out_T_12741 = out_f_rivalid_1328; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1328 = out_roready_1_1182 & out_romask_1328; // @[RegisterRouter.scala:87:24]
wire _out_T_12742 = out_f_roready_1328; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1328 = out_wivalid_1_1182 & out_wimask_1328; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1328 = out_woready_1_1182 & out_womask_1328; // @[RegisterRouter.scala:87:24]
wire _out_T_12743 = ~out_rimask_1328; // @[RegisterRouter.scala:87:24]
wire _out_T_12744 = ~out_wimask_1328; // @[RegisterRouter.scala:87:24]
wire _out_T_12745 = ~out_romask_1328; // @[RegisterRouter.scala:87:24]
wire _out_T_12746 = ~out_womask_1328; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_1142 = {hi_756, flags_0_go, _out_prepend_T_1142}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_12747 = out_prepend_1142; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_12748 = _out_T_12747; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_1143 = _out_T_12748; // @[RegisterRouter.scala:87:24]
wire out_rimask_1329 = |_out_rimask_T_1329; // @[RegisterRouter.scala:87:24]
wire out_wimask_1329 = &_out_wimask_T_1329; // @[RegisterRouter.scala:87:24]
wire out_romask_1329 = |_out_romask_T_1329; // @[RegisterRouter.scala:87:24]
wire out_womask_1329 = &_out_womask_T_1329; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1329 = out_rivalid_1_1183 & out_rimask_1329; // @[RegisterRouter.scala:87:24]
wire _out_T_12750 = out_f_rivalid_1329; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1329 = out_roready_1_1183 & out_romask_1329; // @[RegisterRouter.scala:87:24]
wire _out_T_12751 = out_f_roready_1329; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1329 = out_wivalid_1_1183 & out_wimask_1329; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1329 = out_woready_1_1183 & out_womask_1329; // @[RegisterRouter.scala:87:24]
wire _out_T_12752 = ~out_rimask_1329; // @[RegisterRouter.scala:87:24]
wire _out_T_12753 = ~out_wimask_1329; // @[RegisterRouter.scala:87:24]
wire _out_T_12754 = ~out_romask_1329; // @[RegisterRouter.scala:87:24]
wire _out_T_12755 = ~out_womask_1329; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_1143 = {hi_757, flags_0_go, _out_prepend_T_1143}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_12756 = out_prepend_1143; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_12757 = _out_T_12756; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_1144 = _out_T_12757; // @[RegisterRouter.scala:87:24]
wire out_rimask_1330 = |_out_rimask_T_1330; // @[RegisterRouter.scala:87:24]
wire out_wimask_1330 = &_out_wimask_T_1330; // @[RegisterRouter.scala:87:24]
wire out_romask_1330 = |_out_romask_T_1330; // @[RegisterRouter.scala:87:24]
wire out_womask_1330 = &_out_womask_T_1330; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1330 = out_rivalid_1_1184 & out_rimask_1330; // @[RegisterRouter.scala:87:24]
wire _out_T_12759 = out_f_rivalid_1330; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1330 = out_roready_1_1184 & out_romask_1330; // @[RegisterRouter.scala:87:24]
wire _out_T_12760 = out_f_roready_1330; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1330 = out_wivalid_1_1184 & out_wimask_1330; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1330 = out_woready_1_1184 & out_womask_1330; // @[RegisterRouter.scala:87:24]
wire _out_T_12761 = ~out_rimask_1330; // @[RegisterRouter.scala:87:24]
wire _out_T_12762 = ~out_wimask_1330; // @[RegisterRouter.scala:87:24]
wire _out_T_12763 = ~out_romask_1330; // @[RegisterRouter.scala:87:24]
wire _out_T_12764 = ~out_womask_1330; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_1144 = {hi_758, flags_0_go, _out_prepend_T_1144}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_12765 = out_prepend_1144; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_12766 = _out_T_12765; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_1145 = _out_T_12766; // @[RegisterRouter.scala:87:24]
wire out_rimask_1331 = |_out_rimask_T_1331; // @[RegisterRouter.scala:87:24]
wire out_wimask_1331 = &_out_wimask_T_1331; // @[RegisterRouter.scala:87:24]
wire out_romask_1331 = |_out_romask_T_1331; // @[RegisterRouter.scala:87:24]
wire out_womask_1331 = &_out_womask_T_1331; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1331 = out_rivalid_1_1185 & out_rimask_1331; // @[RegisterRouter.scala:87:24]
wire _out_T_12768 = out_f_rivalid_1331; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1331 = out_roready_1_1185 & out_romask_1331; // @[RegisterRouter.scala:87:24]
wire _out_T_12769 = out_f_roready_1331; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1331 = out_wivalid_1_1185 & out_wimask_1331; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1331 = out_woready_1_1185 & out_womask_1331; // @[RegisterRouter.scala:87:24]
wire _out_T_12770 = ~out_rimask_1331; // @[RegisterRouter.scala:87:24]
wire _out_T_12771 = ~out_wimask_1331; // @[RegisterRouter.scala:87:24]
wire _out_T_12772 = ~out_romask_1331; // @[RegisterRouter.scala:87:24]
wire _out_T_12773 = ~out_womask_1331; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_1145 = {hi_759, flags_0_go, _out_prepend_T_1145}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_12774 = out_prepend_1145; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_12775 = _out_T_12774; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_1146 = _out_T_12775; // @[RegisterRouter.scala:87:24]
wire out_rimask_1332 = |_out_rimask_T_1332; // @[RegisterRouter.scala:87:24]
wire out_wimask_1332 = &_out_wimask_T_1332; // @[RegisterRouter.scala:87:24]
wire out_romask_1332 = |_out_romask_T_1332; // @[RegisterRouter.scala:87:24]
wire out_womask_1332 = &_out_womask_T_1332; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1332 = out_rivalid_1_1186 & out_rimask_1332; // @[RegisterRouter.scala:87:24]
wire _out_T_12777 = out_f_rivalid_1332; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1332 = out_roready_1_1186 & out_romask_1332; // @[RegisterRouter.scala:87:24]
wire _out_T_12778 = out_f_roready_1332; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1332 = out_wivalid_1_1186 & out_wimask_1332; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1332 = out_woready_1_1186 & out_womask_1332; // @[RegisterRouter.scala:87:24]
wire _out_T_12779 = ~out_rimask_1332; // @[RegisterRouter.scala:87:24]
wire _out_T_12780 = ~out_wimask_1332; // @[RegisterRouter.scala:87:24]
wire _out_T_12781 = ~out_romask_1332; // @[RegisterRouter.scala:87:24]
wire _out_T_12782 = ~out_womask_1332; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_1146 = {hi_760, flags_0_go, _out_prepend_T_1146}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_12783 = out_prepend_1146; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_12784 = _out_T_12783; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_222 = _out_T_12784; // @[MuxLiteral.scala:49:48]
wire out_rimask_1333 = |_out_rimask_T_1333; // @[RegisterRouter.scala:87:24]
wire out_wimask_1333 = &_out_wimask_T_1333; // @[RegisterRouter.scala:87:24]
wire out_romask_1333 = |_out_romask_T_1333; // @[RegisterRouter.scala:87:24]
wire out_womask_1333 = &_out_womask_T_1333; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1333 = out_rivalid_1_1187 & out_rimask_1333; // @[RegisterRouter.scala:87:24]
wire _out_T_12786 = out_f_rivalid_1333; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1333 = out_roready_1_1187 & out_romask_1333; // @[RegisterRouter.scala:87:24]
wire _out_T_12787 = out_f_roready_1333; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1333 = out_wivalid_1_1187 & out_wimask_1333; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1333 = out_woready_1_1187 & out_womask_1333; // @[RegisterRouter.scala:87:24]
wire _out_T_12788 = ~out_rimask_1333; // @[RegisterRouter.scala:87:24]
wire _out_T_12789 = ~out_wimask_1333; // @[RegisterRouter.scala:87:24]
wire _out_T_12790 = ~out_romask_1333; // @[RegisterRouter.scala:87:24]
wire _out_T_12791 = ~out_womask_1333; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12793 = _out_T_12792; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_1147 = _out_T_12793; // @[RegisterRouter.scala:87:24]
wire out_rimask_1334 = |_out_rimask_T_1334; // @[RegisterRouter.scala:87:24]
wire out_wimask_1334 = &_out_wimask_T_1334; // @[RegisterRouter.scala:87:24]
wire out_romask_1334 = |_out_romask_T_1334; // @[RegisterRouter.scala:87:24]
wire out_womask_1334 = &_out_womask_T_1334; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1334 = out_rivalid_1_1188 & out_rimask_1334; // @[RegisterRouter.scala:87:24]
wire _out_T_12795 = out_f_rivalid_1334; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1334 = out_roready_1_1188 & out_romask_1334; // @[RegisterRouter.scala:87:24]
wire _out_T_12796 = out_f_roready_1334; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1334 = out_wivalid_1_1188 & out_wimask_1334; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1334 = out_woready_1_1188 & out_womask_1334; // @[RegisterRouter.scala:87:24]
wire _out_T_12797 = ~out_rimask_1334; // @[RegisterRouter.scala:87:24]
wire _out_T_12798 = ~out_wimask_1334; // @[RegisterRouter.scala:87:24]
wire _out_T_12799 = ~out_romask_1334; // @[RegisterRouter.scala:87:24]
wire _out_T_12800 = ~out_womask_1334; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_1147 = {hi_834, flags_0_go, _out_prepend_T_1147}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_12801 = out_prepend_1147; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_12802 = _out_T_12801; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_1148 = _out_T_12802; // @[RegisterRouter.scala:87:24]
wire out_rimask_1335 = |_out_rimask_T_1335; // @[RegisterRouter.scala:87:24]
wire out_wimask_1335 = &_out_wimask_T_1335; // @[RegisterRouter.scala:87:24]
wire out_romask_1335 = |_out_romask_T_1335; // @[RegisterRouter.scala:87:24]
wire out_womask_1335 = &_out_womask_T_1335; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1335 = out_rivalid_1_1189 & out_rimask_1335; // @[RegisterRouter.scala:87:24]
wire _out_T_12804 = out_f_rivalid_1335; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1335 = out_roready_1_1189 & out_romask_1335; // @[RegisterRouter.scala:87:24]
wire _out_T_12805 = out_f_roready_1335; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1335 = out_wivalid_1_1189 & out_wimask_1335; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1335 = out_woready_1_1189 & out_womask_1335; // @[RegisterRouter.scala:87:24]
wire _out_T_12806 = ~out_rimask_1335; // @[RegisterRouter.scala:87:24]
wire _out_T_12807 = ~out_wimask_1335; // @[RegisterRouter.scala:87:24]
wire _out_T_12808 = ~out_romask_1335; // @[RegisterRouter.scala:87:24]
wire _out_T_12809 = ~out_womask_1335; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_1148 = {hi_835, flags_0_go, _out_prepend_T_1148}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_12810 = out_prepend_1148; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_12811 = _out_T_12810; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_1149 = _out_T_12811; // @[RegisterRouter.scala:87:24]
wire out_rimask_1336 = |_out_rimask_T_1336; // @[RegisterRouter.scala:87:24]
wire out_wimask_1336 = &_out_wimask_T_1336; // @[RegisterRouter.scala:87:24]
wire out_romask_1336 = |_out_romask_T_1336; // @[RegisterRouter.scala:87:24]
wire out_womask_1336 = &_out_womask_T_1336; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1336 = out_rivalid_1_1190 & out_rimask_1336; // @[RegisterRouter.scala:87:24]
wire _out_T_12813 = out_f_rivalid_1336; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1336 = out_roready_1_1190 & out_romask_1336; // @[RegisterRouter.scala:87:24]
wire _out_T_12814 = out_f_roready_1336; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1336 = out_wivalid_1_1190 & out_wimask_1336; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1336 = out_woready_1_1190 & out_womask_1336; // @[RegisterRouter.scala:87:24]
wire _out_T_12815 = ~out_rimask_1336; // @[RegisterRouter.scala:87:24]
wire _out_T_12816 = ~out_wimask_1336; // @[RegisterRouter.scala:87:24]
wire _out_T_12817 = ~out_romask_1336; // @[RegisterRouter.scala:87:24]
wire _out_T_12818 = ~out_womask_1336; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_1149 = {hi_836, flags_0_go, _out_prepend_T_1149}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_12819 = out_prepend_1149; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_12820 = _out_T_12819; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_1150 = _out_T_12820; // @[RegisterRouter.scala:87:24]
wire out_rimask_1337 = |_out_rimask_T_1337; // @[RegisterRouter.scala:87:24]
wire out_wimask_1337 = &_out_wimask_T_1337; // @[RegisterRouter.scala:87:24]
wire out_romask_1337 = |_out_romask_T_1337; // @[RegisterRouter.scala:87:24]
wire out_womask_1337 = &_out_womask_T_1337; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1337 = out_rivalid_1_1191 & out_rimask_1337; // @[RegisterRouter.scala:87:24]
wire _out_T_12822 = out_f_rivalid_1337; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1337 = out_roready_1_1191 & out_romask_1337; // @[RegisterRouter.scala:87:24]
wire _out_T_12823 = out_f_roready_1337; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1337 = out_wivalid_1_1191 & out_wimask_1337; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1337 = out_woready_1_1191 & out_womask_1337; // @[RegisterRouter.scala:87:24]
wire _out_T_12824 = ~out_rimask_1337; // @[RegisterRouter.scala:87:24]
wire _out_T_12825 = ~out_wimask_1337; // @[RegisterRouter.scala:87:24]
wire _out_T_12826 = ~out_romask_1337; // @[RegisterRouter.scala:87:24]
wire _out_T_12827 = ~out_womask_1337; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_1150 = {hi_837, flags_0_go, _out_prepend_T_1150}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_12828 = out_prepend_1150; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_12829 = _out_T_12828; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_1151 = _out_T_12829; // @[RegisterRouter.scala:87:24]
wire out_rimask_1338 = |_out_rimask_T_1338; // @[RegisterRouter.scala:87:24]
wire out_wimask_1338 = &_out_wimask_T_1338; // @[RegisterRouter.scala:87:24]
wire out_romask_1338 = |_out_romask_T_1338; // @[RegisterRouter.scala:87:24]
wire out_womask_1338 = &_out_womask_T_1338; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1338 = out_rivalid_1_1192 & out_rimask_1338; // @[RegisterRouter.scala:87:24]
wire _out_T_12831 = out_f_rivalid_1338; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1338 = out_roready_1_1192 & out_romask_1338; // @[RegisterRouter.scala:87:24]
wire _out_T_12832 = out_f_roready_1338; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1338 = out_wivalid_1_1192 & out_wimask_1338; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1338 = out_woready_1_1192 & out_womask_1338; // @[RegisterRouter.scala:87:24]
wire _out_T_12833 = ~out_rimask_1338; // @[RegisterRouter.scala:87:24]
wire _out_T_12834 = ~out_wimask_1338; // @[RegisterRouter.scala:87:24]
wire _out_T_12835 = ~out_romask_1338; // @[RegisterRouter.scala:87:24]
wire _out_T_12836 = ~out_womask_1338; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_1151 = {hi_838, flags_0_go, _out_prepend_T_1151}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_12837 = out_prepend_1151; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_12838 = _out_T_12837; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_1152 = _out_T_12838; // @[RegisterRouter.scala:87:24]
wire out_rimask_1339 = |_out_rimask_T_1339; // @[RegisterRouter.scala:87:24]
wire out_wimask_1339 = &_out_wimask_T_1339; // @[RegisterRouter.scala:87:24]
wire out_romask_1339 = |_out_romask_T_1339; // @[RegisterRouter.scala:87:24]
wire out_womask_1339 = &_out_womask_T_1339; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1339 = out_rivalid_1_1193 & out_rimask_1339; // @[RegisterRouter.scala:87:24]
wire _out_T_12840 = out_f_rivalid_1339; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1339 = out_roready_1_1193 & out_romask_1339; // @[RegisterRouter.scala:87:24]
wire _out_T_12841 = out_f_roready_1339; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1339 = out_wivalid_1_1193 & out_wimask_1339; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1339 = out_woready_1_1193 & out_womask_1339; // @[RegisterRouter.scala:87:24]
wire _out_T_12842 = ~out_rimask_1339; // @[RegisterRouter.scala:87:24]
wire _out_T_12843 = ~out_wimask_1339; // @[RegisterRouter.scala:87:24]
wire _out_T_12844 = ~out_romask_1339; // @[RegisterRouter.scala:87:24]
wire _out_T_12845 = ~out_womask_1339; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_1152 = {hi_839, flags_0_go, _out_prepend_T_1152}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_12846 = out_prepend_1152; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_12847 = _out_T_12846; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_1153 = _out_T_12847; // @[RegisterRouter.scala:87:24]
wire out_rimask_1340 = |_out_rimask_T_1340; // @[RegisterRouter.scala:87:24]
wire out_wimask_1340 = &_out_wimask_T_1340; // @[RegisterRouter.scala:87:24]
wire out_romask_1340 = |_out_romask_T_1340; // @[RegisterRouter.scala:87:24]
wire out_womask_1340 = &_out_womask_T_1340; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1340 = out_rivalid_1_1194 & out_rimask_1340; // @[RegisterRouter.scala:87:24]
wire _out_T_12849 = out_f_rivalid_1340; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1340 = out_roready_1_1194 & out_romask_1340; // @[RegisterRouter.scala:87:24]
wire _out_T_12850 = out_f_roready_1340; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1340 = out_wivalid_1_1194 & out_wimask_1340; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1340 = out_woready_1_1194 & out_womask_1340; // @[RegisterRouter.scala:87:24]
wire _out_T_12851 = ~out_rimask_1340; // @[RegisterRouter.scala:87:24]
wire _out_T_12852 = ~out_wimask_1340; // @[RegisterRouter.scala:87:24]
wire _out_T_12853 = ~out_romask_1340; // @[RegisterRouter.scala:87:24]
wire _out_T_12854 = ~out_womask_1340; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_1153 = {hi_840, flags_0_go, _out_prepend_T_1153}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_12855 = out_prepend_1153; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_12856 = _out_T_12855; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_232 = _out_T_12856; // @[MuxLiteral.scala:49:48]
wire out_rimask_1341 = |_out_rimask_T_1341; // @[RegisterRouter.scala:87:24]
wire out_wimask_1341 = &_out_wimask_T_1341; // @[RegisterRouter.scala:87:24]
wire out_romask_1341 = |_out_romask_T_1341; // @[RegisterRouter.scala:87:24]
wire out_womask_1341 = &_out_womask_T_1341; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1341 = out_rivalid_1_1195 & out_rimask_1341; // @[RegisterRouter.scala:87:24]
wire _out_T_12858 = out_f_rivalid_1341; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1341 = out_roready_1_1195 & out_romask_1341; // @[RegisterRouter.scala:87:24]
wire _out_T_12859 = out_f_roready_1341; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1341 = out_wivalid_1_1195 & out_wimask_1341; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1341 = out_woready_1_1195 & out_womask_1341; // @[RegisterRouter.scala:87:24]
wire _out_T_12860 = ~out_rimask_1341; // @[RegisterRouter.scala:87:24]
wire _out_T_12861 = ~out_wimask_1341; // @[RegisterRouter.scala:87:24]
wire _out_T_12862 = ~out_romask_1341; // @[RegisterRouter.scala:87:24]
wire _out_T_12863 = ~out_womask_1341; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12865 = _out_T_12864; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_1154 = _out_T_12865; // @[RegisterRouter.scala:87:24]
wire out_rimask_1342 = |_out_rimask_T_1342; // @[RegisterRouter.scala:87:24]
wire out_wimask_1342 = &_out_wimask_T_1342; // @[RegisterRouter.scala:87:24]
wire out_romask_1342 = |_out_romask_T_1342; // @[RegisterRouter.scala:87:24]
wire out_womask_1342 = &_out_womask_T_1342; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1342 = out_rivalid_1_1196 & out_rimask_1342; // @[RegisterRouter.scala:87:24]
wire _out_T_12867 = out_f_rivalid_1342; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1342 = out_roready_1_1196 & out_romask_1342; // @[RegisterRouter.scala:87:24]
wire _out_T_12868 = out_f_roready_1342; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1342 = out_wivalid_1_1196 & out_wimask_1342; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1342 = out_woready_1_1196 & out_womask_1342; // @[RegisterRouter.scala:87:24]
wire _out_T_12869 = ~out_rimask_1342; // @[RegisterRouter.scala:87:24]
wire _out_T_12870 = ~out_wimask_1342; // @[RegisterRouter.scala:87:24]
wire _out_T_12871 = ~out_romask_1342; // @[RegisterRouter.scala:87:24]
wire _out_T_12872 = ~out_womask_1342; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_1154 = {hi_1010, flags_0_go, _out_prepend_T_1154}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_12873 = out_prepend_1154; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_12874 = _out_T_12873; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_1155 = _out_T_12874; // @[RegisterRouter.scala:87:24]
wire out_rimask_1343 = |_out_rimask_T_1343; // @[RegisterRouter.scala:87:24]
wire out_wimask_1343 = &_out_wimask_T_1343; // @[RegisterRouter.scala:87:24]
wire out_romask_1343 = |_out_romask_T_1343; // @[RegisterRouter.scala:87:24]
wire out_womask_1343 = &_out_womask_T_1343; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1343 = out_rivalid_1_1197 & out_rimask_1343; // @[RegisterRouter.scala:87:24]
wire _out_T_12876 = out_f_rivalid_1343; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1343 = out_roready_1_1197 & out_romask_1343; // @[RegisterRouter.scala:87:24]
wire _out_T_12877 = out_f_roready_1343; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1343 = out_wivalid_1_1197 & out_wimask_1343; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1343 = out_woready_1_1197 & out_womask_1343; // @[RegisterRouter.scala:87:24]
wire _out_T_12878 = ~out_rimask_1343; // @[RegisterRouter.scala:87:24]
wire _out_T_12879 = ~out_wimask_1343; // @[RegisterRouter.scala:87:24]
wire _out_T_12880 = ~out_romask_1343; // @[RegisterRouter.scala:87:24]
wire _out_T_12881 = ~out_womask_1343; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_1155 = {hi_1011, flags_0_go, _out_prepend_T_1155}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_12882 = out_prepend_1155; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_12883 = _out_T_12882; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_1156 = _out_T_12883; // @[RegisterRouter.scala:87:24]
wire out_rimask_1344 = |_out_rimask_T_1344; // @[RegisterRouter.scala:87:24]
wire out_wimask_1344 = &_out_wimask_T_1344; // @[RegisterRouter.scala:87:24]
wire out_romask_1344 = |_out_romask_T_1344; // @[RegisterRouter.scala:87:24]
wire out_womask_1344 = &_out_womask_T_1344; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1344 = out_rivalid_1_1198 & out_rimask_1344; // @[RegisterRouter.scala:87:24]
wire _out_T_12885 = out_f_rivalid_1344; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1344 = out_roready_1_1198 & out_romask_1344; // @[RegisterRouter.scala:87:24]
wire _out_T_12886 = out_f_roready_1344; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1344 = out_wivalid_1_1198 & out_wimask_1344; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1344 = out_woready_1_1198 & out_womask_1344; // @[RegisterRouter.scala:87:24]
wire _out_T_12887 = ~out_rimask_1344; // @[RegisterRouter.scala:87:24]
wire _out_T_12888 = ~out_wimask_1344; // @[RegisterRouter.scala:87:24]
wire _out_T_12889 = ~out_romask_1344; // @[RegisterRouter.scala:87:24]
wire _out_T_12890 = ~out_womask_1344; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_1156 = {hi_1012, flags_0_go, _out_prepend_T_1156}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_12891 = out_prepend_1156; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_12892 = _out_T_12891; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_1157 = _out_T_12892; // @[RegisterRouter.scala:87:24]
wire out_rimask_1345 = |_out_rimask_T_1345; // @[RegisterRouter.scala:87:24]
wire out_wimask_1345 = &_out_wimask_T_1345; // @[RegisterRouter.scala:87:24]
wire out_romask_1345 = |_out_romask_T_1345; // @[RegisterRouter.scala:87:24]
wire out_womask_1345 = &_out_womask_T_1345; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1345 = out_rivalid_1_1199 & out_rimask_1345; // @[RegisterRouter.scala:87:24]
wire _out_T_12894 = out_f_rivalid_1345; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1345 = out_roready_1_1199 & out_romask_1345; // @[RegisterRouter.scala:87:24]
wire _out_T_12895 = out_f_roready_1345; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1345 = out_wivalid_1_1199 & out_wimask_1345; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1345 = out_woready_1_1199 & out_womask_1345; // @[RegisterRouter.scala:87:24]
wire _out_T_12896 = ~out_rimask_1345; // @[RegisterRouter.scala:87:24]
wire _out_T_12897 = ~out_wimask_1345; // @[RegisterRouter.scala:87:24]
wire _out_T_12898 = ~out_romask_1345; // @[RegisterRouter.scala:87:24]
wire _out_T_12899 = ~out_womask_1345; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_1157 = {hi_1013, flags_0_go, _out_prepend_T_1157}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_12900 = out_prepend_1157; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_12901 = _out_T_12900; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_1158 = _out_T_12901; // @[RegisterRouter.scala:87:24]
wire out_rimask_1346 = |_out_rimask_T_1346; // @[RegisterRouter.scala:87:24]
wire out_wimask_1346 = &_out_wimask_T_1346; // @[RegisterRouter.scala:87:24]
wire out_romask_1346 = |_out_romask_T_1346; // @[RegisterRouter.scala:87:24]
wire out_womask_1346 = &_out_womask_T_1346; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1346 = out_rivalid_1_1200 & out_rimask_1346; // @[RegisterRouter.scala:87:24]
wire _out_T_12903 = out_f_rivalid_1346; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1346 = out_roready_1_1200 & out_romask_1346; // @[RegisterRouter.scala:87:24]
wire _out_T_12904 = out_f_roready_1346; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1346 = out_wivalid_1_1200 & out_wimask_1346; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1346 = out_woready_1_1200 & out_womask_1346; // @[RegisterRouter.scala:87:24]
wire _out_T_12905 = ~out_rimask_1346; // @[RegisterRouter.scala:87:24]
wire _out_T_12906 = ~out_wimask_1346; // @[RegisterRouter.scala:87:24]
wire _out_T_12907 = ~out_romask_1346; // @[RegisterRouter.scala:87:24]
wire _out_T_12908 = ~out_womask_1346; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_1158 = {hi_1014, flags_0_go, _out_prepend_T_1158}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_12909 = out_prepend_1158; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_12910 = _out_T_12909; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_1159 = _out_T_12910; // @[RegisterRouter.scala:87:24]
wire out_rimask_1347 = |_out_rimask_T_1347; // @[RegisterRouter.scala:87:24]
wire out_wimask_1347 = &_out_wimask_T_1347; // @[RegisterRouter.scala:87:24]
wire out_romask_1347 = |_out_romask_T_1347; // @[RegisterRouter.scala:87:24]
wire out_womask_1347 = &_out_womask_T_1347; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1347 = out_rivalid_1_1201 & out_rimask_1347; // @[RegisterRouter.scala:87:24]
wire _out_T_12912 = out_f_rivalid_1347; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1347 = out_roready_1_1201 & out_romask_1347; // @[RegisterRouter.scala:87:24]
wire _out_T_12913 = out_f_roready_1347; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1347 = out_wivalid_1_1201 & out_wimask_1347; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1347 = out_woready_1_1201 & out_womask_1347; // @[RegisterRouter.scala:87:24]
wire _out_T_12914 = ~out_rimask_1347; // @[RegisterRouter.scala:87:24]
wire _out_T_12915 = ~out_wimask_1347; // @[RegisterRouter.scala:87:24]
wire _out_T_12916 = ~out_romask_1347; // @[RegisterRouter.scala:87:24]
wire _out_T_12917 = ~out_womask_1347; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_1159 = {hi_1015, flags_0_go, _out_prepend_T_1159}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_12918 = out_prepend_1159; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_12919 = _out_T_12918; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_1160 = _out_T_12919; // @[RegisterRouter.scala:87:24]
wire out_rimask_1348 = |_out_rimask_T_1348; // @[RegisterRouter.scala:87:24]
wire out_wimask_1348 = &_out_wimask_T_1348; // @[RegisterRouter.scala:87:24]
wire out_romask_1348 = |_out_romask_T_1348; // @[RegisterRouter.scala:87:24]
wire out_womask_1348 = &_out_womask_T_1348; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1348 = out_rivalid_1_1202 & out_rimask_1348; // @[RegisterRouter.scala:87:24]
wire _out_T_12921 = out_f_rivalid_1348; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1348 = out_roready_1_1202 & out_romask_1348; // @[RegisterRouter.scala:87:24]
wire _out_T_12922 = out_f_roready_1348; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1348 = out_wivalid_1_1202 & out_wimask_1348; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1348 = out_woready_1_1202 & out_womask_1348; // @[RegisterRouter.scala:87:24]
wire _out_T_12923 = ~out_rimask_1348; // @[RegisterRouter.scala:87:24]
wire _out_T_12924 = ~out_wimask_1348; // @[RegisterRouter.scala:87:24]
wire _out_T_12925 = ~out_romask_1348; // @[RegisterRouter.scala:87:24]
wire _out_T_12926 = ~out_womask_1348; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_1160 = {hi_1016, flags_0_go, _out_prepend_T_1160}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_12927 = out_prepend_1160; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_12928 = _out_T_12927; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_254 = _out_T_12928; // @[MuxLiteral.scala:49:48]
wire out_rimask_1349 = |_out_rimask_T_1349; // @[RegisterRouter.scala:87:24]
wire out_wimask_1349 = &_out_wimask_T_1349; // @[RegisterRouter.scala:87:24]
wire out_romask_1349 = |_out_romask_T_1349; // @[RegisterRouter.scala:87:24]
wire out_womask_1349 = &_out_womask_T_1349; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1349 = out_rivalid_1_1203 & out_rimask_1349; // @[RegisterRouter.scala:87:24]
wire _out_T_12930 = out_f_rivalid_1349; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1349 = out_roready_1_1203 & out_romask_1349; // @[RegisterRouter.scala:87:24]
wire _out_T_12931 = out_f_roready_1349; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1349 = out_wivalid_1_1203 & out_wimask_1349; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1349 = out_woready_1_1203 & out_womask_1349; // @[RegisterRouter.scala:87:24]
wire _out_T_12932 = ~out_rimask_1349; // @[RegisterRouter.scala:87:24]
wire _out_T_12933 = ~out_wimask_1349; // @[RegisterRouter.scala:87:24]
wire _out_T_12934 = ~out_romask_1349; // @[RegisterRouter.scala:87:24]
wire _out_T_12935 = ~out_womask_1349; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_12937 = _out_T_12936; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_1161 = _out_T_12937; // @[RegisterRouter.scala:87:24]
wire out_rimask_1350 = |_out_rimask_T_1350; // @[RegisterRouter.scala:87:24]
wire out_wimask_1350 = &_out_wimask_T_1350; // @[RegisterRouter.scala:87:24]
wire out_romask_1350 = |_out_romask_T_1350; // @[RegisterRouter.scala:87:24]
wire out_womask_1350 = &_out_womask_T_1350; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1350 = out_rivalid_1_1204 & out_rimask_1350; // @[RegisterRouter.scala:87:24]
wire _out_T_12939 = out_f_rivalid_1350; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1350 = out_roready_1_1204 & out_romask_1350; // @[RegisterRouter.scala:87:24]
wire _out_T_12940 = out_f_roready_1350; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1350 = out_wivalid_1_1204 & out_wimask_1350; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1350 = out_woready_1_1204 & out_womask_1350; // @[RegisterRouter.scala:87:24]
wire _out_T_12941 = ~out_rimask_1350; // @[RegisterRouter.scala:87:24]
wire _out_T_12942 = ~out_wimask_1350; // @[RegisterRouter.scala:87:24]
wire _out_T_12943 = ~out_romask_1350; // @[RegisterRouter.scala:87:24]
wire _out_T_12944 = ~out_womask_1350; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_1161 = {hi_794, flags_0_go, _out_prepend_T_1161}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_12945 = out_prepend_1161; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_12946 = _out_T_12945; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_1162 = _out_T_12946; // @[RegisterRouter.scala:87:24]
wire out_rimask_1351 = |_out_rimask_T_1351; // @[RegisterRouter.scala:87:24]
wire out_wimask_1351 = &_out_wimask_T_1351; // @[RegisterRouter.scala:87:24]
wire out_romask_1351 = |_out_romask_T_1351; // @[RegisterRouter.scala:87:24]
wire out_womask_1351 = &_out_womask_T_1351; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1351 = out_rivalid_1_1205 & out_rimask_1351; // @[RegisterRouter.scala:87:24]
wire _out_T_12948 = out_f_rivalid_1351; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1351 = out_roready_1_1205 & out_romask_1351; // @[RegisterRouter.scala:87:24]
wire _out_T_12949 = out_f_roready_1351; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1351 = out_wivalid_1_1205 & out_wimask_1351; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1351 = out_woready_1_1205 & out_womask_1351; // @[RegisterRouter.scala:87:24]
wire _out_T_12950 = ~out_rimask_1351; // @[RegisterRouter.scala:87:24]
wire _out_T_12951 = ~out_wimask_1351; // @[RegisterRouter.scala:87:24]
wire _out_T_12952 = ~out_romask_1351; // @[RegisterRouter.scala:87:24]
wire _out_T_12953 = ~out_womask_1351; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_1162 = {hi_795, flags_0_go, _out_prepend_T_1162}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_12954 = out_prepend_1162; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_12955 = _out_T_12954; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_1163 = _out_T_12955; // @[RegisterRouter.scala:87:24]
wire out_rimask_1352 = |_out_rimask_T_1352; // @[RegisterRouter.scala:87:24]
wire out_wimask_1352 = &_out_wimask_T_1352; // @[RegisterRouter.scala:87:24]
wire out_romask_1352 = |_out_romask_T_1352; // @[RegisterRouter.scala:87:24]
wire out_womask_1352 = &_out_womask_T_1352; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1352 = out_rivalid_1_1206 & out_rimask_1352; // @[RegisterRouter.scala:87:24]
wire _out_T_12957 = out_f_rivalid_1352; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1352 = out_roready_1_1206 & out_romask_1352; // @[RegisterRouter.scala:87:24]
wire _out_T_12958 = out_f_roready_1352; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1352 = out_wivalid_1_1206 & out_wimask_1352; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1352 = out_woready_1_1206 & out_womask_1352; // @[RegisterRouter.scala:87:24]
wire _out_T_12959 = ~out_rimask_1352; // @[RegisterRouter.scala:87:24]
wire _out_T_12960 = ~out_wimask_1352; // @[RegisterRouter.scala:87:24]
wire _out_T_12961 = ~out_romask_1352; // @[RegisterRouter.scala:87:24]
wire _out_T_12962 = ~out_womask_1352; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_1163 = {hi_796, flags_0_go, _out_prepend_T_1163}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_12963 = out_prepend_1163; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_12964 = _out_T_12963; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_1164 = _out_T_12964; // @[RegisterRouter.scala:87:24]
wire out_rimask_1353 = |_out_rimask_T_1353; // @[RegisterRouter.scala:87:24]
wire out_wimask_1353 = &_out_wimask_T_1353; // @[RegisterRouter.scala:87:24]
wire out_romask_1353 = |_out_romask_T_1353; // @[RegisterRouter.scala:87:24]
wire out_womask_1353 = &_out_womask_T_1353; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1353 = out_rivalid_1_1207 & out_rimask_1353; // @[RegisterRouter.scala:87:24]
wire _out_T_12966 = out_f_rivalid_1353; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1353 = out_roready_1_1207 & out_romask_1353; // @[RegisterRouter.scala:87:24]
wire _out_T_12967 = out_f_roready_1353; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1353 = out_wivalid_1_1207 & out_wimask_1353; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1353 = out_woready_1_1207 & out_womask_1353; // @[RegisterRouter.scala:87:24]
wire _out_T_12968 = ~out_rimask_1353; // @[RegisterRouter.scala:87:24]
wire _out_T_12969 = ~out_wimask_1353; // @[RegisterRouter.scala:87:24]
wire _out_T_12970 = ~out_romask_1353; // @[RegisterRouter.scala:87:24]
wire _out_T_12971 = ~out_womask_1353; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_1164 = {hi_797, flags_0_go, _out_prepend_T_1164}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_12972 = out_prepend_1164; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_12973 = _out_T_12972; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_1165 = _out_T_12973; // @[RegisterRouter.scala:87:24]
wire out_rimask_1354 = |_out_rimask_T_1354; // @[RegisterRouter.scala:87:24]
wire out_wimask_1354 = &_out_wimask_T_1354; // @[RegisterRouter.scala:87:24]
wire out_romask_1354 = |_out_romask_T_1354; // @[RegisterRouter.scala:87:24]
wire out_womask_1354 = &_out_womask_T_1354; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1354 = out_rivalid_1_1208 & out_rimask_1354; // @[RegisterRouter.scala:87:24]
wire _out_T_12975 = out_f_rivalid_1354; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1354 = out_roready_1_1208 & out_romask_1354; // @[RegisterRouter.scala:87:24]
wire _out_T_12976 = out_f_roready_1354; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1354 = out_wivalid_1_1208 & out_wimask_1354; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1354 = out_woready_1_1208 & out_womask_1354; // @[RegisterRouter.scala:87:24]
wire _out_T_12977 = ~out_rimask_1354; // @[RegisterRouter.scala:87:24]
wire _out_T_12978 = ~out_wimask_1354; // @[RegisterRouter.scala:87:24]
wire _out_T_12979 = ~out_romask_1354; // @[RegisterRouter.scala:87:24]
wire _out_T_12980 = ~out_womask_1354; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_1165 = {hi_798, flags_0_go, _out_prepend_T_1165}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_12981 = out_prepend_1165; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_12982 = _out_T_12981; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_1166 = _out_T_12982; // @[RegisterRouter.scala:87:24]
wire out_rimask_1355 = |_out_rimask_T_1355; // @[RegisterRouter.scala:87:24]
wire out_wimask_1355 = &_out_wimask_T_1355; // @[RegisterRouter.scala:87:24]
wire out_romask_1355 = |_out_romask_T_1355; // @[RegisterRouter.scala:87:24]
wire out_womask_1355 = &_out_womask_T_1355; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1355 = out_rivalid_1_1209 & out_rimask_1355; // @[RegisterRouter.scala:87:24]
wire _out_T_12984 = out_f_rivalid_1355; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1355 = out_roready_1_1209 & out_romask_1355; // @[RegisterRouter.scala:87:24]
wire _out_T_12985 = out_f_roready_1355; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1355 = out_wivalid_1_1209 & out_wimask_1355; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1355 = out_woready_1_1209 & out_womask_1355; // @[RegisterRouter.scala:87:24]
wire _out_T_12986 = ~out_rimask_1355; // @[RegisterRouter.scala:87:24]
wire _out_T_12987 = ~out_wimask_1355; // @[RegisterRouter.scala:87:24]
wire _out_T_12988 = ~out_romask_1355; // @[RegisterRouter.scala:87:24]
wire _out_T_12989 = ~out_womask_1355; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_1166 = {hi_799, flags_0_go, _out_prepend_T_1166}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_12990 = out_prepend_1166; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_12991 = _out_T_12990; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_1167 = _out_T_12991; // @[RegisterRouter.scala:87:24]
wire out_rimask_1356 = |_out_rimask_T_1356; // @[RegisterRouter.scala:87:24]
wire out_wimask_1356 = &_out_wimask_T_1356; // @[RegisterRouter.scala:87:24]
wire out_romask_1356 = |_out_romask_T_1356; // @[RegisterRouter.scala:87:24]
wire out_womask_1356 = &_out_womask_T_1356; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1356 = out_rivalid_1_1210 & out_rimask_1356; // @[RegisterRouter.scala:87:24]
wire _out_T_12993 = out_f_rivalid_1356; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1356 = out_roready_1_1210 & out_romask_1356; // @[RegisterRouter.scala:87:24]
wire _out_T_12994 = out_f_roready_1356; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1356 = out_wivalid_1_1210 & out_wimask_1356; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1356 = out_woready_1_1210 & out_womask_1356; // @[RegisterRouter.scala:87:24]
wire _out_T_12995 = ~out_rimask_1356; // @[RegisterRouter.scala:87:24]
wire _out_T_12996 = ~out_wimask_1356; // @[RegisterRouter.scala:87:24]
wire _out_T_12997 = ~out_romask_1356; // @[RegisterRouter.scala:87:24]
wire _out_T_12998 = ~out_womask_1356; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_1167 = {hi_800, flags_0_go, _out_prepend_T_1167}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_12999 = out_prepend_1167; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_13000 = _out_T_12999; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_3_227 = _out_T_13000; // @[MuxLiteral.scala:49:48]
wire _out_iindex_T_7 = out_front_1_bits_index[0]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_7 = out_front_1_bits_index[0]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_8 = out_front_1_bits_index[1]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_8 = out_front_1_bits_index[1]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_9 = out_front_1_bits_index[2]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_9 = out_front_1_bits_index[2]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_10 = out_front_1_bits_index[3]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_10 = out_front_1_bits_index[3]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_11 = out_front_1_bits_index[4]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_11 = out_front_1_bits_index[4]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_12 = out_front_1_bits_index[5]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_12 = out_front_1_bits_index[5]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_13 = out_front_1_bits_index[6]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_13 = out_front_1_bits_index[6]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_14 = out_front_1_bits_index[7]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_14 = out_front_1_bits_index[7]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_15 = out_front_1_bits_index[8]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_15 = out_front_1_bits_index[8]; // @[RegisterRouter.scala:87:24]
wire [1:0] out_iindex_lo_lo = {_out_iindex_T_8, _out_iindex_T_7}; // @[RegisterRouter.scala:87:24]
wire [1:0] out_iindex_lo_hi_1 = {_out_iindex_T_10, _out_iindex_T_9}; // @[RegisterRouter.scala:87:24]
wire [3:0] out_iindex_lo_1 = {out_iindex_lo_hi_1, out_iindex_lo_lo}; // @[RegisterRouter.scala:87:24]
wire [1:0] out_iindex_hi_lo = {_out_iindex_T_12, _out_iindex_T_11}; // @[RegisterRouter.scala:87:24]
wire [1:0] out_iindex_hi_hi_1 = {_out_iindex_T_14, _out_iindex_T_13}; // @[RegisterRouter.scala:87:24]
wire [3:0] out_iindex_hi_1 = {out_iindex_hi_hi_1, out_iindex_hi_lo}; // @[RegisterRouter.scala:87:24]
wire [7:0] out_iindex_1 = {out_iindex_hi_1, out_iindex_lo_1}; // @[RegisterRouter.scala:87:24]
wire [1:0] out_oindex_lo_lo = {_out_oindex_T_8, _out_oindex_T_7}; // @[RegisterRouter.scala:87:24]
wire [1:0] out_oindex_lo_hi_1 = {_out_oindex_T_10, _out_oindex_T_9}; // @[RegisterRouter.scala:87:24]
wire [3:0] out_oindex_lo_1 = {out_oindex_lo_hi_1, out_oindex_lo_lo}; // @[RegisterRouter.scala:87:24]
wire [1:0] out_oindex_hi_lo = {_out_oindex_T_12, _out_oindex_T_11}; // @[RegisterRouter.scala:87:24]
wire [1:0] out_oindex_hi_hi_1 = {_out_oindex_T_14, _out_oindex_T_13}; // @[RegisterRouter.scala:87:24]
wire [3:0] out_oindex_hi_1 = {out_oindex_hi_hi_1, out_oindex_hi_lo}; // @[RegisterRouter.scala:87:24]
wire [7:0] out_oindex_1 = {out_oindex_hi_1, out_oindex_lo_1}; // @[RegisterRouter.scala:87:24]
wire [255:0] _out_frontSel_T_1 = 256'h1 << out_iindex_1; // @[OneHot.scala:58:35]
wire out_frontSel_0_1 = _out_frontSel_T_1[0]; // @[OneHot.scala:58:35]
wire out_frontSel_1_1 = _out_frontSel_T_1[1]; // @[OneHot.scala:58:35]
wire out_frontSel_2_1 = _out_frontSel_T_1[2]; // @[OneHot.scala:58:35]
wire out_frontSel_3_1 = _out_frontSel_T_1[3]; // @[OneHot.scala:58:35]
wire out_frontSel_4_1 = _out_frontSel_T_1[4]; // @[OneHot.scala:58:35]
wire out_frontSel_5_1 = _out_frontSel_T_1[5]; // @[OneHot.scala:58:35]
wire out_frontSel_6_1 = _out_frontSel_T_1[6]; // @[OneHot.scala:58:35]
wire out_frontSel_7_1 = _out_frontSel_T_1[7]; // @[OneHot.scala:58:35]
wire out_frontSel_8_1 = _out_frontSel_T_1[8]; // @[OneHot.scala:58:35]
wire out_frontSel_9_1 = _out_frontSel_T_1[9]; // @[OneHot.scala:58:35]
wire out_frontSel_10_1 = _out_frontSel_T_1[10]; // @[OneHot.scala:58:35]
wire out_frontSel_11_1 = _out_frontSel_T_1[11]; // @[OneHot.scala:58:35]
wire out_frontSel_12_1 = _out_frontSel_T_1[12]; // @[OneHot.scala:58:35]
wire out_frontSel_13_1 = _out_frontSel_T_1[13]; // @[OneHot.scala:58:35]
wire out_frontSel_14_1 = _out_frontSel_T_1[14]; // @[OneHot.scala:58:35]
wire out_frontSel_15_1 = _out_frontSel_T_1[15]; // @[OneHot.scala:58:35]
wire out_frontSel_16_1 = _out_frontSel_T_1[16]; // @[OneHot.scala:58:35]
wire out_frontSel_17_1 = _out_frontSel_T_1[17]; // @[OneHot.scala:58:35]
wire out_frontSel_18_1 = _out_frontSel_T_1[18]; // @[OneHot.scala:58:35]
wire out_frontSel_19_1 = _out_frontSel_T_1[19]; // @[OneHot.scala:58:35]
wire out_frontSel_20_1 = _out_frontSel_T_1[20]; // @[OneHot.scala:58:35]
wire out_frontSel_21_1 = _out_frontSel_T_1[21]; // @[OneHot.scala:58:35]
wire out_frontSel_22_1 = _out_frontSel_T_1[22]; // @[OneHot.scala:58:35]
wire out_frontSel_23_1 = _out_frontSel_T_1[23]; // @[OneHot.scala:58:35]
wire out_frontSel_24_1 = _out_frontSel_T_1[24]; // @[OneHot.scala:58:35]
wire out_frontSel_25_1 = _out_frontSel_T_1[25]; // @[OneHot.scala:58:35]
wire out_frontSel_26_1 = _out_frontSel_T_1[26]; // @[OneHot.scala:58:35]
wire out_frontSel_27_1 = _out_frontSel_T_1[27]; // @[OneHot.scala:58:35]
wire out_frontSel_28_1 = _out_frontSel_T_1[28]; // @[OneHot.scala:58:35]
wire out_frontSel_29_1 = _out_frontSel_T_1[29]; // @[OneHot.scala:58:35]
wire out_frontSel_30_1 = _out_frontSel_T_1[30]; // @[OneHot.scala:58:35]
wire out_frontSel_31_1 = _out_frontSel_T_1[31]; // @[OneHot.scala:58:35]
wire out_frontSel_32_1 = _out_frontSel_T_1[32]; // @[OneHot.scala:58:35]
wire out_frontSel_33_1 = _out_frontSel_T_1[33]; // @[OneHot.scala:58:35]
wire out_frontSel_34_1 = _out_frontSel_T_1[34]; // @[OneHot.scala:58:35]
wire out_frontSel_35_1 = _out_frontSel_T_1[35]; // @[OneHot.scala:58:35]
wire out_frontSel_36_1 = _out_frontSel_T_1[36]; // @[OneHot.scala:58:35]
wire out_frontSel_37_1 = _out_frontSel_T_1[37]; // @[OneHot.scala:58:35]
wire out_frontSel_38_1 = _out_frontSel_T_1[38]; // @[OneHot.scala:58:35]
wire out_frontSel_39_1 = _out_frontSel_T_1[39]; // @[OneHot.scala:58:35]
wire out_frontSel_40_1 = _out_frontSel_T_1[40]; // @[OneHot.scala:58:35]
wire out_frontSel_41_1 = _out_frontSel_T_1[41]; // @[OneHot.scala:58:35]
wire out_frontSel_42_1 = _out_frontSel_T_1[42]; // @[OneHot.scala:58:35]
wire out_frontSel_43_1 = _out_frontSel_T_1[43]; // @[OneHot.scala:58:35]
wire out_frontSel_44_1 = _out_frontSel_T_1[44]; // @[OneHot.scala:58:35]
wire out_frontSel_45_1 = _out_frontSel_T_1[45]; // @[OneHot.scala:58:35]
wire out_frontSel_46_1 = _out_frontSel_T_1[46]; // @[OneHot.scala:58:35]
wire out_frontSel_47_1 = _out_frontSel_T_1[47]; // @[OneHot.scala:58:35]
wire out_frontSel_48_1 = _out_frontSel_T_1[48]; // @[OneHot.scala:58:35]
wire out_frontSel_49_1 = _out_frontSel_T_1[49]; // @[OneHot.scala:58:35]
wire out_frontSel_50_1 = _out_frontSel_T_1[50]; // @[OneHot.scala:58:35]
wire out_frontSel_51_1 = _out_frontSel_T_1[51]; // @[OneHot.scala:58:35]
wire out_frontSel_52_1 = _out_frontSel_T_1[52]; // @[OneHot.scala:58:35]
wire out_frontSel_53_1 = _out_frontSel_T_1[53]; // @[OneHot.scala:58:35]
wire out_frontSel_54_1 = _out_frontSel_T_1[54]; // @[OneHot.scala:58:35]
wire out_frontSel_55_1 = _out_frontSel_T_1[55]; // @[OneHot.scala:58:35]
wire out_frontSel_56_1 = _out_frontSel_T_1[56]; // @[OneHot.scala:58:35]
wire out_frontSel_57_1 = _out_frontSel_T_1[57]; // @[OneHot.scala:58:35]
wire out_frontSel_58_1 = _out_frontSel_T_1[58]; // @[OneHot.scala:58:35]
wire out_frontSel_59_1 = _out_frontSel_T_1[59]; // @[OneHot.scala:58:35]
wire out_frontSel_60_1 = _out_frontSel_T_1[60]; // @[OneHot.scala:58:35]
wire out_frontSel_61_1 = _out_frontSel_T_1[61]; // @[OneHot.scala:58:35]
wire out_frontSel_62_1 = _out_frontSel_T_1[62]; // @[OneHot.scala:58:35]
wire out_frontSel_63_1 = _out_frontSel_T_1[63]; // @[OneHot.scala:58:35]
wire out_frontSel_64 = _out_frontSel_T_1[64]; // @[OneHot.scala:58:35]
wire out_frontSel_65 = _out_frontSel_T_1[65]; // @[OneHot.scala:58:35]
wire out_frontSel_66 = _out_frontSel_T_1[66]; // @[OneHot.scala:58:35]
wire out_frontSel_67 = _out_frontSel_T_1[67]; // @[OneHot.scala:58:35]
wire out_frontSel_68 = _out_frontSel_T_1[68]; // @[OneHot.scala:58:35]
wire out_frontSel_69 = _out_frontSel_T_1[69]; // @[OneHot.scala:58:35]
wire out_frontSel_70 = _out_frontSel_T_1[70]; // @[OneHot.scala:58:35]
wire out_frontSel_71 = _out_frontSel_T_1[71]; // @[OneHot.scala:58:35]
wire out_frontSel_72 = _out_frontSel_T_1[72]; // @[OneHot.scala:58:35]
wire out_frontSel_73 = _out_frontSel_T_1[73]; // @[OneHot.scala:58:35]
wire out_frontSel_74 = _out_frontSel_T_1[74]; // @[OneHot.scala:58:35]
wire out_frontSel_75 = _out_frontSel_T_1[75]; // @[OneHot.scala:58:35]
wire out_frontSel_76 = _out_frontSel_T_1[76]; // @[OneHot.scala:58:35]
wire out_frontSel_77 = _out_frontSel_T_1[77]; // @[OneHot.scala:58:35]
wire out_frontSel_78 = _out_frontSel_T_1[78]; // @[OneHot.scala:58:35]
wire out_frontSel_79 = _out_frontSel_T_1[79]; // @[OneHot.scala:58:35]
wire out_frontSel_80 = _out_frontSel_T_1[80]; // @[OneHot.scala:58:35]
wire out_frontSel_81 = _out_frontSel_T_1[81]; // @[OneHot.scala:58:35]
wire out_frontSel_82 = _out_frontSel_T_1[82]; // @[OneHot.scala:58:35]
wire out_frontSel_83 = _out_frontSel_T_1[83]; // @[OneHot.scala:58:35]
wire out_frontSel_84 = _out_frontSel_T_1[84]; // @[OneHot.scala:58:35]
wire out_frontSel_85 = _out_frontSel_T_1[85]; // @[OneHot.scala:58:35]
wire out_frontSel_86 = _out_frontSel_T_1[86]; // @[OneHot.scala:58:35]
wire out_frontSel_87 = _out_frontSel_T_1[87]; // @[OneHot.scala:58:35]
wire out_frontSel_88 = _out_frontSel_T_1[88]; // @[OneHot.scala:58:35]
wire out_frontSel_89 = _out_frontSel_T_1[89]; // @[OneHot.scala:58:35]
wire out_frontSel_90 = _out_frontSel_T_1[90]; // @[OneHot.scala:58:35]
wire out_frontSel_91 = _out_frontSel_T_1[91]; // @[OneHot.scala:58:35]
wire out_frontSel_92 = _out_frontSel_T_1[92]; // @[OneHot.scala:58:35]
wire out_frontSel_93 = _out_frontSel_T_1[93]; // @[OneHot.scala:58:35]
wire out_frontSel_94 = _out_frontSel_T_1[94]; // @[OneHot.scala:58:35]
wire out_frontSel_95 = _out_frontSel_T_1[95]; // @[OneHot.scala:58:35]
wire out_frontSel_96 = _out_frontSel_T_1[96]; // @[OneHot.scala:58:35]
wire out_frontSel_97 = _out_frontSel_T_1[97]; // @[OneHot.scala:58:35]
wire out_frontSel_98 = _out_frontSel_T_1[98]; // @[OneHot.scala:58:35]
wire out_frontSel_99 = _out_frontSel_T_1[99]; // @[OneHot.scala:58:35]
wire out_frontSel_100 = _out_frontSel_T_1[100]; // @[OneHot.scala:58:35]
wire out_frontSel_101 = _out_frontSel_T_1[101]; // @[OneHot.scala:58:35]
wire out_frontSel_102 = _out_frontSel_T_1[102]; // @[OneHot.scala:58:35]
wire out_frontSel_103 = _out_frontSel_T_1[103]; // @[OneHot.scala:58:35]
wire out_frontSel_104 = _out_frontSel_T_1[104]; // @[OneHot.scala:58:35]
wire out_frontSel_105 = _out_frontSel_T_1[105]; // @[OneHot.scala:58:35]
wire out_frontSel_106 = _out_frontSel_T_1[106]; // @[OneHot.scala:58:35]
wire out_frontSel_107 = _out_frontSel_T_1[107]; // @[OneHot.scala:58:35]
wire out_frontSel_108 = _out_frontSel_T_1[108]; // @[OneHot.scala:58:35]
wire out_frontSel_109 = _out_frontSel_T_1[109]; // @[OneHot.scala:58:35]
wire out_frontSel_110 = _out_frontSel_T_1[110]; // @[OneHot.scala:58:35]
wire out_frontSel_111 = _out_frontSel_T_1[111]; // @[OneHot.scala:58:35]
wire out_frontSel_112 = _out_frontSel_T_1[112]; // @[OneHot.scala:58:35]
wire out_frontSel_113 = _out_frontSel_T_1[113]; // @[OneHot.scala:58:35]
wire out_frontSel_114 = _out_frontSel_T_1[114]; // @[OneHot.scala:58:35]
wire out_frontSel_115 = _out_frontSel_T_1[115]; // @[OneHot.scala:58:35]
wire out_frontSel_116 = _out_frontSel_T_1[116]; // @[OneHot.scala:58:35]
wire out_frontSel_117 = _out_frontSel_T_1[117]; // @[OneHot.scala:58:35]
wire out_frontSel_118 = _out_frontSel_T_1[118]; // @[OneHot.scala:58:35]
wire out_frontSel_119 = _out_frontSel_T_1[119]; // @[OneHot.scala:58:35]
wire out_frontSel_120 = _out_frontSel_T_1[120]; // @[OneHot.scala:58:35]
wire out_frontSel_121 = _out_frontSel_T_1[121]; // @[OneHot.scala:58:35]
wire out_frontSel_122 = _out_frontSel_T_1[122]; // @[OneHot.scala:58:35]
wire out_frontSel_123 = _out_frontSel_T_1[123]; // @[OneHot.scala:58:35]
wire out_frontSel_124 = _out_frontSel_T_1[124]; // @[OneHot.scala:58:35]
wire out_frontSel_125 = _out_frontSel_T_1[125]; // @[OneHot.scala:58:35]
wire out_frontSel_126 = _out_frontSel_T_1[126]; // @[OneHot.scala:58:35]
wire out_frontSel_127 = _out_frontSel_T_1[127]; // @[OneHot.scala:58:35]
wire out_frontSel_128 = _out_frontSel_T_1[128]; // @[OneHot.scala:58:35]
wire out_frontSel_129 = _out_frontSel_T_1[129]; // @[OneHot.scala:58:35]
wire out_frontSel_130 = _out_frontSel_T_1[130]; // @[OneHot.scala:58:35]
wire out_frontSel_131 = _out_frontSel_T_1[131]; // @[OneHot.scala:58:35]
wire out_frontSel_132 = _out_frontSel_T_1[132]; // @[OneHot.scala:58:35]
wire out_frontSel_133 = _out_frontSel_T_1[133]; // @[OneHot.scala:58:35]
wire out_frontSel_134 = _out_frontSel_T_1[134]; // @[OneHot.scala:58:35]
wire out_frontSel_135 = _out_frontSel_T_1[135]; // @[OneHot.scala:58:35]
wire out_frontSel_136 = _out_frontSel_T_1[136]; // @[OneHot.scala:58:35]
wire out_frontSel_137 = _out_frontSel_T_1[137]; // @[OneHot.scala:58:35]
wire out_frontSel_138 = _out_frontSel_T_1[138]; // @[OneHot.scala:58:35]
wire out_frontSel_139 = _out_frontSel_T_1[139]; // @[OneHot.scala:58:35]
wire out_frontSel_140 = _out_frontSel_T_1[140]; // @[OneHot.scala:58:35]
wire out_frontSel_141 = _out_frontSel_T_1[141]; // @[OneHot.scala:58:35]
wire out_frontSel_142 = _out_frontSel_T_1[142]; // @[OneHot.scala:58:35]
wire out_frontSel_143 = _out_frontSel_T_1[143]; // @[OneHot.scala:58:35]
wire out_frontSel_144 = _out_frontSel_T_1[144]; // @[OneHot.scala:58:35]
wire out_frontSel_145 = _out_frontSel_T_1[145]; // @[OneHot.scala:58:35]
wire out_frontSel_146 = _out_frontSel_T_1[146]; // @[OneHot.scala:58:35]
wire out_frontSel_147 = _out_frontSel_T_1[147]; // @[OneHot.scala:58:35]
wire out_frontSel_148 = _out_frontSel_T_1[148]; // @[OneHot.scala:58:35]
wire out_frontSel_149 = _out_frontSel_T_1[149]; // @[OneHot.scala:58:35]
wire out_frontSel_150 = _out_frontSel_T_1[150]; // @[OneHot.scala:58:35]
wire out_frontSel_151 = _out_frontSel_T_1[151]; // @[OneHot.scala:58:35]
wire out_frontSel_152 = _out_frontSel_T_1[152]; // @[OneHot.scala:58:35]
wire out_frontSel_153 = _out_frontSel_T_1[153]; // @[OneHot.scala:58:35]
wire out_frontSel_154 = _out_frontSel_T_1[154]; // @[OneHot.scala:58:35]
wire out_frontSel_155 = _out_frontSel_T_1[155]; // @[OneHot.scala:58:35]
wire out_frontSel_156 = _out_frontSel_T_1[156]; // @[OneHot.scala:58:35]
wire out_frontSel_157 = _out_frontSel_T_1[157]; // @[OneHot.scala:58:35]
wire out_frontSel_158 = _out_frontSel_T_1[158]; // @[OneHot.scala:58:35]
wire out_frontSel_159 = _out_frontSel_T_1[159]; // @[OneHot.scala:58:35]
wire out_frontSel_160 = _out_frontSel_T_1[160]; // @[OneHot.scala:58:35]
wire out_frontSel_161 = _out_frontSel_T_1[161]; // @[OneHot.scala:58:35]
wire out_frontSel_162 = _out_frontSel_T_1[162]; // @[OneHot.scala:58:35]
wire out_frontSel_163 = _out_frontSel_T_1[163]; // @[OneHot.scala:58:35]
wire out_frontSel_164 = _out_frontSel_T_1[164]; // @[OneHot.scala:58:35]
wire out_frontSel_165 = _out_frontSel_T_1[165]; // @[OneHot.scala:58:35]
wire out_frontSel_166 = _out_frontSel_T_1[166]; // @[OneHot.scala:58:35]
wire out_frontSel_167 = _out_frontSel_T_1[167]; // @[OneHot.scala:58:35]
wire out_frontSel_168 = _out_frontSel_T_1[168]; // @[OneHot.scala:58:35]
wire out_frontSel_169 = _out_frontSel_T_1[169]; // @[OneHot.scala:58:35]
wire out_frontSel_170 = _out_frontSel_T_1[170]; // @[OneHot.scala:58:35]
wire out_frontSel_171 = _out_frontSel_T_1[171]; // @[OneHot.scala:58:35]
wire out_frontSel_172 = _out_frontSel_T_1[172]; // @[OneHot.scala:58:35]
wire out_frontSel_173 = _out_frontSel_T_1[173]; // @[OneHot.scala:58:35]
wire out_frontSel_174 = _out_frontSel_T_1[174]; // @[OneHot.scala:58:35]
wire out_frontSel_175 = _out_frontSel_T_1[175]; // @[OneHot.scala:58:35]
wire out_frontSel_176 = _out_frontSel_T_1[176]; // @[OneHot.scala:58:35]
wire out_frontSel_177 = _out_frontSel_T_1[177]; // @[OneHot.scala:58:35]
wire out_frontSel_178 = _out_frontSel_T_1[178]; // @[OneHot.scala:58:35]
wire out_frontSel_179 = _out_frontSel_T_1[179]; // @[OneHot.scala:58:35]
wire out_frontSel_180 = _out_frontSel_T_1[180]; // @[OneHot.scala:58:35]
wire out_frontSel_181 = _out_frontSel_T_1[181]; // @[OneHot.scala:58:35]
wire out_frontSel_182 = _out_frontSel_T_1[182]; // @[OneHot.scala:58:35]
wire out_frontSel_183 = _out_frontSel_T_1[183]; // @[OneHot.scala:58:35]
wire out_frontSel_184 = _out_frontSel_T_1[184]; // @[OneHot.scala:58:35]
wire out_frontSel_185 = _out_frontSel_T_1[185]; // @[OneHot.scala:58:35]
wire out_frontSel_186 = _out_frontSel_T_1[186]; // @[OneHot.scala:58:35]
wire out_frontSel_187 = _out_frontSel_T_1[187]; // @[OneHot.scala:58:35]
wire out_frontSel_188 = _out_frontSel_T_1[188]; // @[OneHot.scala:58:35]
wire out_frontSel_189 = _out_frontSel_T_1[189]; // @[OneHot.scala:58:35]
wire out_frontSel_190 = _out_frontSel_T_1[190]; // @[OneHot.scala:58:35]
wire out_frontSel_191 = _out_frontSel_T_1[191]; // @[OneHot.scala:58:35]
wire out_frontSel_192 = _out_frontSel_T_1[192]; // @[OneHot.scala:58:35]
wire out_frontSel_193 = _out_frontSel_T_1[193]; // @[OneHot.scala:58:35]
wire out_frontSel_194 = _out_frontSel_T_1[194]; // @[OneHot.scala:58:35]
wire out_frontSel_195 = _out_frontSel_T_1[195]; // @[OneHot.scala:58:35]
wire out_frontSel_196 = _out_frontSel_T_1[196]; // @[OneHot.scala:58:35]
wire out_frontSel_197 = _out_frontSel_T_1[197]; // @[OneHot.scala:58:35]
wire out_frontSel_198 = _out_frontSel_T_1[198]; // @[OneHot.scala:58:35]
wire out_frontSel_199 = _out_frontSel_T_1[199]; // @[OneHot.scala:58:35]
wire out_frontSel_200 = _out_frontSel_T_1[200]; // @[OneHot.scala:58:35]
wire out_frontSel_201 = _out_frontSel_T_1[201]; // @[OneHot.scala:58:35]
wire out_frontSel_202 = _out_frontSel_T_1[202]; // @[OneHot.scala:58:35]
wire out_frontSel_203 = _out_frontSel_T_1[203]; // @[OneHot.scala:58:35]
wire out_frontSel_204 = _out_frontSel_T_1[204]; // @[OneHot.scala:58:35]
wire out_frontSel_205 = _out_frontSel_T_1[205]; // @[OneHot.scala:58:35]
wire out_frontSel_206 = _out_frontSel_T_1[206]; // @[OneHot.scala:58:35]
wire out_frontSel_207 = _out_frontSel_T_1[207]; // @[OneHot.scala:58:35]
wire out_frontSel_208 = _out_frontSel_T_1[208]; // @[OneHot.scala:58:35]
wire out_frontSel_209 = _out_frontSel_T_1[209]; // @[OneHot.scala:58:35]
wire out_frontSel_210 = _out_frontSel_T_1[210]; // @[OneHot.scala:58:35]
wire out_frontSel_211 = _out_frontSel_T_1[211]; // @[OneHot.scala:58:35]
wire out_frontSel_212 = _out_frontSel_T_1[212]; // @[OneHot.scala:58:35]
wire out_frontSel_213 = _out_frontSel_T_1[213]; // @[OneHot.scala:58:35]
wire out_frontSel_214 = _out_frontSel_T_1[214]; // @[OneHot.scala:58:35]
wire out_frontSel_215 = _out_frontSel_T_1[215]; // @[OneHot.scala:58:35]
wire out_frontSel_216 = _out_frontSel_T_1[216]; // @[OneHot.scala:58:35]
wire out_frontSel_217 = _out_frontSel_T_1[217]; // @[OneHot.scala:58:35]
wire out_frontSel_218 = _out_frontSel_T_1[218]; // @[OneHot.scala:58:35]
wire out_frontSel_219 = _out_frontSel_T_1[219]; // @[OneHot.scala:58:35]
wire out_frontSel_220 = _out_frontSel_T_1[220]; // @[OneHot.scala:58:35]
wire out_frontSel_221 = _out_frontSel_T_1[221]; // @[OneHot.scala:58:35]
wire out_frontSel_222 = _out_frontSel_T_1[222]; // @[OneHot.scala:58:35]
wire out_frontSel_223 = _out_frontSel_T_1[223]; // @[OneHot.scala:58:35]
wire out_frontSel_224 = _out_frontSel_T_1[224]; // @[OneHot.scala:58:35]
wire out_frontSel_225 = _out_frontSel_T_1[225]; // @[OneHot.scala:58:35]
wire out_frontSel_226 = _out_frontSel_T_1[226]; // @[OneHot.scala:58:35]
wire out_frontSel_227 = _out_frontSel_T_1[227]; // @[OneHot.scala:58:35]
wire out_frontSel_228 = _out_frontSel_T_1[228]; // @[OneHot.scala:58:35]
wire out_frontSel_229 = _out_frontSel_T_1[229]; // @[OneHot.scala:58:35]
wire out_frontSel_230 = _out_frontSel_T_1[230]; // @[OneHot.scala:58:35]
wire out_frontSel_231 = _out_frontSel_T_1[231]; // @[OneHot.scala:58:35]
wire out_frontSel_232 = _out_frontSel_T_1[232]; // @[OneHot.scala:58:35]
wire out_frontSel_233 = _out_frontSel_T_1[233]; // @[OneHot.scala:58:35]
wire out_frontSel_234 = _out_frontSel_T_1[234]; // @[OneHot.scala:58:35]
wire out_frontSel_235 = _out_frontSel_T_1[235]; // @[OneHot.scala:58:35]
wire out_frontSel_236 = _out_frontSel_T_1[236]; // @[OneHot.scala:58:35]
wire out_frontSel_237 = _out_frontSel_T_1[237]; // @[OneHot.scala:58:35]
wire out_frontSel_238 = _out_frontSel_T_1[238]; // @[OneHot.scala:58:35]
wire out_frontSel_239 = _out_frontSel_T_1[239]; // @[OneHot.scala:58:35]
wire out_frontSel_240 = _out_frontSel_T_1[240]; // @[OneHot.scala:58:35]
wire out_frontSel_241 = _out_frontSel_T_1[241]; // @[OneHot.scala:58:35]
wire out_frontSel_242 = _out_frontSel_T_1[242]; // @[OneHot.scala:58:35]
wire out_frontSel_243 = _out_frontSel_T_1[243]; // @[OneHot.scala:58:35]
wire out_frontSel_244 = _out_frontSel_T_1[244]; // @[OneHot.scala:58:35]
wire out_frontSel_245 = _out_frontSel_T_1[245]; // @[OneHot.scala:58:35]
wire out_frontSel_246 = _out_frontSel_T_1[246]; // @[OneHot.scala:58:35]
wire out_frontSel_247 = _out_frontSel_T_1[247]; // @[OneHot.scala:58:35]
wire out_frontSel_248 = _out_frontSel_T_1[248]; // @[OneHot.scala:58:35]
wire out_frontSel_249 = _out_frontSel_T_1[249]; // @[OneHot.scala:58:35]
wire out_frontSel_250 = _out_frontSel_T_1[250]; // @[OneHot.scala:58:35]
wire out_frontSel_251 = _out_frontSel_T_1[251]; // @[OneHot.scala:58:35]
wire out_frontSel_252 = _out_frontSel_T_1[252]; // @[OneHot.scala:58:35]
wire out_frontSel_253 = _out_frontSel_T_1[253]; // @[OneHot.scala:58:35]
wire out_frontSel_254 = _out_frontSel_T_1[254]; // @[OneHot.scala:58:35]
wire out_frontSel_255 = _out_frontSel_T_1[255]; // @[OneHot.scala:58:35]
wire [255:0] _out_backSel_T_1 = 256'h1 << out_oindex_1; // @[OneHot.scala:58:35]
wire out_backSel_0_1 = _out_backSel_T_1[0]; // @[OneHot.scala:58:35]
wire out_backSel_1_1 = _out_backSel_T_1[1]; // @[OneHot.scala:58:35]
wire out_backSel_2_1 = _out_backSel_T_1[2]; // @[OneHot.scala:58:35]
wire out_backSel_3_1 = _out_backSel_T_1[3]; // @[OneHot.scala:58:35]
wire out_backSel_4_1 = _out_backSel_T_1[4]; // @[OneHot.scala:58:35]
wire out_backSel_5_1 = _out_backSel_T_1[5]; // @[OneHot.scala:58:35]
wire out_backSel_6_1 = _out_backSel_T_1[6]; // @[OneHot.scala:58:35]
wire out_backSel_7_1 = _out_backSel_T_1[7]; // @[OneHot.scala:58:35]
wire out_backSel_8_1 = _out_backSel_T_1[8]; // @[OneHot.scala:58:35]
wire out_backSel_9_1 = _out_backSel_T_1[9]; // @[OneHot.scala:58:35]
wire out_backSel_10_1 = _out_backSel_T_1[10]; // @[OneHot.scala:58:35]
wire out_backSel_11_1 = _out_backSel_T_1[11]; // @[OneHot.scala:58:35]
wire out_backSel_12_1 = _out_backSel_T_1[12]; // @[OneHot.scala:58:35]
wire out_backSel_13_1 = _out_backSel_T_1[13]; // @[OneHot.scala:58:35]
wire out_backSel_14_1 = _out_backSel_T_1[14]; // @[OneHot.scala:58:35]
wire out_backSel_15_1 = _out_backSel_T_1[15]; // @[OneHot.scala:58:35]
wire out_backSel_16_1 = _out_backSel_T_1[16]; // @[OneHot.scala:58:35]
wire out_backSel_17_1 = _out_backSel_T_1[17]; // @[OneHot.scala:58:35]
wire out_backSel_18_1 = _out_backSel_T_1[18]; // @[OneHot.scala:58:35]
wire out_backSel_19_1 = _out_backSel_T_1[19]; // @[OneHot.scala:58:35]
wire out_backSel_20_1 = _out_backSel_T_1[20]; // @[OneHot.scala:58:35]
wire out_backSel_21_1 = _out_backSel_T_1[21]; // @[OneHot.scala:58:35]
wire out_backSel_22_1 = _out_backSel_T_1[22]; // @[OneHot.scala:58:35]
wire out_backSel_23_1 = _out_backSel_T_1[23]; // @[OneHot.scala:58:35]
wire out_backSel_24_1 = _out_backSel_T_1[24]; // @[OneHot.scala:58:35]
wire out_backSel_25_1 = _out_backSel_T_1[25]; // @[OneHot.scala:58:35]
wire out_backSel_26_1 = _out_backSel_T_1[26]; // @[OneHot.scala:58:35]
wire out_backSel_27_1 = _out_backSel_T_1[27]; // @[OneHot.scala:58:35]
wire out_backSel_28_1 = _out_backSel_T_1[28]; // @[OneHot.scala:58:35]
wire out_backSel_29_1 = _out_backSel_T_1[29]; // @[OneHot.scala:58:35]
wire out_backSel_30_1 = _out_backSel_T_1[30]; // @[OneHot.scala:58:35]
wire out_backSel_31_1 = _out_backSel_T_1[31]; // @[OneHot.scala:58:35]
wire out_backSel_32_1 = _out_backSel_T_1[32]; // @[OneHot.scala:58:35]
wire out_backSel_33_1 = _out_backSel_T_1[33]; // @[OneHot.scala:58:35]
wire out_backSel_34_1 = _out_backSel_T_1[34]; // @[OneHot.scala:58:35]
wire out_backSel_35_1 = _out_backSel_T_1[35]; // @[OneHot.scala:58:35]
wire out_backSel_36_1 = _out_backSel_T_1[36]; // @[OneHot.scala:58:35]
wire out_backSel_37_1 = _out_backSel_T_1[37]; // @[OneHot.scala:58:35]
wire out_backSel_38_1 = _out_backSel_T_1[38]; // @[OneHot.scala:58:35]
wire out_backSel_39_1 = _out_backSel_T_1[39]; // @[OneHot.scala:58:35]
wire out_backSel_40_1 = _out_backSel_T_1[40]; // @[OneHot.scala:58:35]
wire out_backSel_41_1 = _out_backSel_T_1[41]; // @[OneHot.scala:58:35]
wire out_backSel_42_1 = _out_backSel_T_1[42]; // @[OneHot.scala:58:35]
wire out_backSel_43_1 = _out_backSel_T_1[43]; // @[OneHot.scala:58:35]
wire out_backSel_44_1 = _out_backSel_T_1[44]; // @[OneHot.scala:58:35]
wire out_backSel_45_1 = _out_backSel_T_1[45]; // @[OneHot.scala:58:35]
wire out_backSel_46_1 = _out_backSel_T_1[46]; // @[OneHot.scala:58:35]
wire out_backSel_47_1 = _out_backSel_T_1[47]; // @[OneHot.scala:58:35]
wire out_backSel_48_1 = _out_backSel_T_1[48]; // @[OneHot.scala:58:35]
wire out_backSel_49_1 = _out_backSel_T_1[49]; // @[OneHot.scala:58:35]
wire out_backSel_50_1 = _out_backSel_T_1[50]; // @[OneHot.scala:58:35]
wire out_backSel_51_1 = _out_backSel_T_1[51]; // @[OneHot.scala:58:35]
wire out_backSel_52_1 = _out_backSel_T_1[52]; // @[OneHot.scala:58:35]
wire out_backSel_53_1 = _out_backSel_T_1[53]; // @[OneHot.scala:58:35]
wire out_backSel_54_1 = _out_backSel_T_1[54]; // @[OneHot.scala:58:35]
wire out_backSel_55_1 = _out_backSel_T_1[55]; // @[OneHot.scala:58:35]
wire out_backSel_56_1 = _out_backSel_T_1[56]; // @[OneHot.scala:58:35]
wire out_backSel_57_1 = _out_backSel_T_1[57]; // @[OneHot.scala:58:35]
wire out_backSel_58_1 = _out_backSel_T_1[58]; // @[OneHot.scala:58:35]
wire out_backSel_59_1 = _out_backSel_T_1[59]; // @[OneHot.scala:58:35]
wire out_backSel_60_1 = _out_backSel_T_1[60]; // @[OneHot.scala:58:35]
wire out_backSel_61_1 = _out_backSel_T_1[61]; // @[OneHot.scala:58:35]
wire out_backSel_62_1 = _out_backSel_T_1[62]; // @[OneHot.scala:58:35]
wire out_backSel_63_1 = _out_backSel_T_1[63]; // @[OneHot.scala:58:35]
wire out_backSel_64 = _out_backSel_T_1[64]; // @[OneHot.scala:58:35]
wire out_backSel_65 = _out_backSel_T_1[65]; // @[OneHot.scala:58:35]
wire out_backSel_66 = _out_backSel_T_1[66]; // @[OneHot.scala:58:35]
wire out_backSel_67 = _out_backSel_T_1[67]; // @[OneHot.scala:58:35]
wire out_backSel_68 = _out_backSel_T_1[68]; // @[OneHot.scala:58:35]
wire out_backSel_69 = _out_backSel_T_1[69]; // @[OneHot.scala:58:35]
wire out_backSel_70 = _out_backSel_T_1[70]; // @[OneHot.scala:58:35]
wire out_backSel_71 = _out_backSel_T_1[71]; // @[OneHot.scala:58:35]
wire out_backSel_72 = _out_backSel_T_1[72]; // @[OneHot.scala:58:35]
wire out_backSel_73 = _out_backSel_T_1[73]; // @[OneHot.scala:58:35]
wire out_backSel_74 = _out_backSel_T_1[74]; // @[OneHot.scala:58:35]
wire out_backSel_75 = _out_backSel_T_1[75]; // @[OneHot.scala:58:35]
wire out_backSel_76 = _out_backSel_T_1[76]; // @[OneHot.scala:58:35]
wire out_backSel_77 = _out_backSel_T_1[77]; // @[OneHot.scala:58:35]
wire out_backSel_78 = _out_backSel_T_1[78]; // @[OneHot.scala:58:35]
wire out_backSel_79 = _out_backSel_T_1[79]; // @[OneHot.scala:58:35]
wire out_backSel_80 = _out_backSel_T_1[80]; // @[OneHot.scala:58:35]
wire out_backSel_81 = _out_backSel_T_1[81]; // @[OneHot.scala:58:35]
wire out_backSel_82 = _out_backSel_T_1[82]; // @[OneHot.scala:58:35]
wire out_backSel_83 = _out_backSel_T_1[83]; // @[OneHot.scala:58:35]
wire out_backSel_84 = _out_backSel_T_1[84]; // @[OneHot.scala:58:35]
wire out_backSel_85 = _out_backSel_T_1[85]; // @[OneHot.scala:58:35]
wire out_backSel_86 = _out_backSel_T_1[86]; // @[OneHot.scala:58:35]
wire out_backSel_87 = _out_backSel_T_1[87]; // @[OneHot.scala:58:35]
wire out_backSel_88 = _out_backSel_T_1[88]; // @[OneHot.scala:58:35]
wire out_backSel_89 = _out_backSel_T_1[89]; // @[OneHot.scala:58:35]
wire out_backSel_90 = _out_backSel_T_1[90]; // @[OneHot.scala:58:35]
wire out_backSel_91 = _out_backSel_T_1[91]; // @[OneHot.scala:58:35]
wire out_backSel_92 = _out_backSel_T_1[92]; // @[OneHot.scala:58:35]
wire out_backSel_93 = _out_backSel_T_1[93]; // @[OneHot.scala:58:35]
wire out_backSel_94 = _out_backSel_T_1[94]; // @[OneHot.scala:58:35]
wire out_backSel_95 = _out_backSel_T_1[95]; // @[OneHot.scala:58:35]
wire out_backSel_96 = _out_backSel_T_1[96]; // @[OneHot.scala:58:35]
wire out_backSel_97 = _out_backSel_T_1[97]; // @[OneHot.scala:58:35]
wire out_backSel_98 = _out_backSel_T_1[98]; // @[OneHot.scala:58:35]
wire out_backSel_99 = _out_backSel_T_1[99]; // @[OneHot.scala:58:35]
wire out_backSel_100 = _out_backSel_T_1[100]; // @[OneHot.scala:58:35]
wire out_backSel_101 = _out_backSel_T_1[101]; // @[OneHot.scala:58:35]
wire out_backSel_102 = _out_backSel_T_1[102]; // @[OneHot.scala:58:35]
wire out_backSel_103 = _out_backSel_T_1[103]; // @[OneHot.scala:58:35]
wire out_backSel_104 = _out_backSel_T_1[104]; // @[OneHot.scala:58:35]
wire out_backSel_105 = _out_backSel_T_1[105]; // @[OneHot.scala:58:35]
wire out_backSel_106 = _out_backSel_T_1[106]; // @[OneHot.scala:58:35]
wire out_backSel_107 = _out_backSel_T_1[107]; // @[OneHot.scala:58:35]
wire out_backSel_108 = _out_backSel_T_1[108]; // @[OneHot.scala:58:35]
wire out_backSel_109 = _out_backSel_T_1[109]; // @[OneHot.scala:58:35]
wire out_backSel_110 = _out_backSel_T_1[110]; // @[OneHot.scala:58:35]
wire out_backSel_111 = _out_backSel_T_1[111]; // @[OneHot.scala:58:35]
wire out_backSel_112 = _out_backSel_T_1[112]; // @[OneHot.scala:58:35]
wire out_backSel_113 = _out_backSel_T_1[113]; // @[OneHot.scala:58:35]
wire out_backSel_114 = _out_backSel_T_1[114]; // @[OneHot.scala:58:35]
wire out_backSel_115 = _out_backSel_T_1[115]; // @[OneHot.scala:58:35]
wire out_backSel_116 = _out_backSel_T_1[116]; // @[OneHot.scala:58:35]
wire out_backSel_117 = _out_backSel_T_1[117]; // @[OneHot.scala:58:35]
wire out_backSel_118 = _out_backSel_T_1[118]; // @[OneHot.scala:58:35]
wire out_backSel_119 = _out_backSel_T_1[119]; // @[OneHot.scala:58:35]
wire out_backSel_120 = _out_backSel_T_1[120]; // @[OneHot.scala:58:35]
wire out_backSel_121 = _out_backSel_T_1[121]; // @[OneHot.scala:58:35]
wire out_backSel_122 = _out_backSel_T_1[122]; // @[OneHot.scala:58:35]
wire out_backSel_123 = _out_backSel_T_1[123]; // @[OneHot.scala:58:35]
wire out_backSel_124 = _out_backSel_T_1[124]; // @[OneHot.scala:58:35]
wire out_backSel_125 = _out_backSel_T_1[125]; // @[OneHot.scala:58:35]
wire out_backSel_126 = _out_backSel_T_1[126]; // @[OneHot.scala:58:35]
wire out_backSel_127 = _out_backSel_T_1[127]; // @[OneHot.scala:58:35]
wire out_backSel_128 = _out_backSel_T_1[128]; // @[OneHot.scala:58:35]
wire out_backSel_129 = _out_backSel_T_1[129]; // @[OneHot.scala:58:35]
wire out_backSel_130 = _out_backSel_T_1[130]; // @[OneHot.scala:58:35]
wire out_backSel_131 = _out_backSel_T_1[131]; // @[OneHot.scala:58:35]
wire out_backSel_132 = _out_backSel_T_1[132]; // @[OneHot.scala:58:35]
wire out_backSel_133 = _out_backSel_T_1[133]; // @[OneHot.scala:58:35]
wire out_backSel_134 = _out_backSel_T_1[134]; // @[OneHot.scala:58:35]
wire out_backSel_135 = _out_backSel_T_1[135]; // @[OneHot.scala:58:35]
wire out_backSel_136 = _out_backSel_T_1[136]; // @[OneHot.scala:58:35]
wire out_backSel_137 = _out_backSel_T_1[137]; // @[OneHot.scala:58:35]
wire out_backSel_138 = _out_backSel_T_1[138]; // @[OneHot.scala:58:35]
wire out_backSel_139 = _out_backSel_T_1[139]; // @[OneHot.scala:58:35]
wire out_backSel_140 = _out_backSel_T_1[140]; // @[OneHot.scala:58:35]
wire out_backSel_141 = _out_backSel_T_1[141]; // @[OneHot.scala:58:35]
wire out_backSel_142 = _out_backSel_T_1[142]; // @[OneHot.scala:58:35]
wire out_backSel_143 = _out_backSel_T_1[143]; // @[OneHot.scala:58:35]
wire out_backSel_144 = _out_backSel_T_1[144]; // @[OneHot.scala:58:35]
wire out_backSel_145 = _out_backSel_T_1[145]; // @[OneHot.scala:58:35]
wire out_backSel_146 = _out_backSel_T_1[146]; // @[OneHot.scala:58:35]
wire out_backSel_147 = _out_backSel_T_1[147]; // @[OneHot.scala:58:35]
wire out_backSel_148 = _out_backSel_T_1[148]; // @[OneHot.scala:58:35]
wire out_backSel_149 = _out_backSel_T_1[149]; // @[OneHot.scala:58:35]
wire out_backSel_150 = _out_backSel_T_1[150]; // @[OneHot.scala:58:35]
wire out_backSel_151 = _out_backSel_T_1[151]; // @[OneHot.scala:58:35]
wire out_backSel_152 = _out_backSel_T_1[152]; // @[OneHot.scala:58:35]
wire out_backSel_153 = _out_backSel_T_1[153]; // @[OneHot.scala:58:35]
wire out_backSel_154 = _out_backSel_T_1[154]; // @[OneHot.scala:58:35]
wire out_backSel_155 = _out_backSel_T_1[155]; // @[OneHot.scala:58:35]
wire out_backSel_156 = _out_backSel_T_1[156]; // @[OneHot.scala:58:35]
wire out_backSel_157 = _out_backSel_T_1[157]; // @[OneHot.scala:58:35]
wire out_backSel_158 = _out_backSel_T_1[158]; // @[OneHot.scala:58:35]
wire out_backSel_159 = _out_backSel_T_1[159]; // @[OneHot.scala:58:35]
wire out_backSel_160 = _out_backSel_T_1[160]; // @[OneHot.scala:58:35]
wire out_backSel_161 = _out_backSel_T_1[161]; // @[OneHot.scala:58:35]
wire out_backSel_162 = _out_backSel_T_1[162]; // @[OneHot.scala:58:35]
wire out_backSel_163 = _out_backSel_T_1[163]; // @[OneHot.scala:58:35]
wire out_backSel_164 = _out_backSel_T_1[164]; // @[OneHot.scala:58:35]
wire out_backSel_165 = _out_backSel_T_1[165]; // @[OneHot.scala:58:35]
wire out_backSel_166 = _out_backSel_T_1[166]; // @[OneHot.scala:58:35]
wire out_backSel_167 = _out_backSel_T_1[167]; // @[OneHot.scala:58:35]
wire out_backSel_168 = _out_backSel_T_1[168]; // @[OneHot.scala:58:35]
wire out_backSel_169 = _out_backSel_T_1[169]; // @[OneHot.scala:58:35]
wire out_backSel_170 = _out_backSel_T_1[170]; // @[OneHot.scala:58:35]
wire out_backSel_171 = _out_backSel_T_1[171]; // @[OneHot.scala:58:35]
wire out_backSel_172 = _out_backSel_T_1[172]; // @[OneHot.scala:58:35]
wire out_backSel_173 = _out_backSel_T_1[173]; // @[OneHot.scala:58:35]
wire out_backSel_174 = _out_backSel_T_1[174]; // @[OneHot.scala:58:35]
wire out_backSel_175 = _out_backSel_T_1[175]; // @[OneHot.scala:58:35]
wire out_backSel_176 = _out_backSel_T_1[176]; // @[OneHot.scala:58:35]
wire out_backSel_177 = _out_backSel_T_1[177]; // @[OneHot.scala:58:35]
wire out_backSel_178 = _out_backSel_T_1[178]; // @[OneHot.scala:58:35]
wire out_backSel_179 = _out_backSel_T_1[179]; // @[OneHot.scala:58:35]
wire out_backSel_180 = _out_backSel_T_1[180]; // @[OneHot.scala:58:35]
wire out_backSel_181 = _out_backSel_T_1[181]; // @[OneHot.scala:58:35]
wire out_backSel_182 = _out_backSel_T_1[182]; // @[OneHot.scala:58:35]
wire out_backSel_183 = _out_backSel_T_1[183]; // @[OneHot.scala:58:35]
wire out_backSel_184 = _out_backSel_T_1[184]; // @[OneHot.scala:58:35]
wire out_backSel_185 = _out_backSel_T_1[185]; // @[OneHot.scala:58:35]
wire out_backSel_186 = _out_backSel_T_1[186]; // @[OneHot.scala:58:35]
wire out_backSel_187 = _out_backSel_T_1[187]; // @[OneHot.scala:58:35]
wire out_backSel_188 = _out_backSel_T_1[188]; // @[OneHot.scala:58:35]
wire out_backSel_189 = _out_backSel_T_1[189]; // @[OneHot.scala:58:35]
wire out_backSel_190 = _out_backSel_T_1[190]; // @[OneHot.scala:58:35]
wire out_backSel_191 = _out_backSel_T_1[191]; // @[OneHot.scala:58:35]
wire out_backSel_192 = _out_backSel_T_1[192]; // @[OneHot.scala:58:35]
wire out_backSel_193 = _out_backSel_T_1[193]; // @[OneHot.scala:58:35]
wire out_backSel_194 = _out_backSel_T_1[194]; // @[OneHot.scala:58:35]
wire out_backSel_195 = _out_backSel_T_1[195]; // @[OneHot.scala:58:35]
wire out_backSel_196 = _out_backSel_T_1[196]; // @[OneHot.scala:58:35]
wire out_backSel_197 = _out_backSel_T_1[197]; // @[OneHot.scala:58:35]
wire out_backSel_198 = _out_backSel_T_1[198]; // @[OneHot.scala:58:35]
wire out_backSel_199 = _out_backSel_T_1[199]; // @[OneHot.scala:58:35]
wire out_backSel_200 = _out_backSel_T_1[200]; // @[OneHot.scala:58:35]
wire out_backSel_201 = _out_backSel_T_1[201]; // @[OneHot.scala:58:35]
wire out_backSel_202 = _out_backSel_T_1[202]; // @[OneHot.scala:58:35]
wire out_backSel_203 = _out_backSel_T_1[203]; // @[OneHot.scala:58:35]
wire out_backSel_204 = _out_backSel_T_1[204]; // @[OneHot.scala:58:35]
wire out_backSel_205 = _out_backSel_T_1[205]; // @[OneHot.scala:58:35]
wire out_backSel_206 = _out_backSel_T_1[206]; // @[OneHot.scala:58:35]
wire out_backSel_207 = _out_backSel_T_1[207]; // @[OneHot.scala:58:35]
wire out_backSel_208 = _out_backSel_T_1[208]; // @[OneHot.scala:58:35]
wire out_backSel_209 = _out_backSel_T_1[209]; // @[OneHot.scala:58:35]
wire out_backSel_210 = _out_backSel_T_1[210]; // @[OneHot.scala:58:35]
wire out_backSel_211 = _out_backSel_T_1[211]; // @[OneHot.scala:58:35]
wire out_backSel_212 = _out_backSel_T_1[212]; // @[OneHot.scala:58:35]
wire out_backSel_213 = _out_backSel_T_1[213]; // @[OneHot.scala:58:35]
wire out_backSel_214 = _out_backSel_T_1[214]; // @[OneHot.scala:58:35]
wire out_backSel_215 = _out_backSel_T_1[215]; // @[OneHot.scala:58:35]
wire out_backSel_216 = _out_backSel_T_1[216]; // @[OneHot.scala:58:35]
wire out_backSel_217 = _out_backSel_T_1[217]; // @[OneHot.scala:58:35]
wire out_backSel_218 = _out_backSel_T_1[218]; // @[OneHot.scala:58:35]
wire out_backSel_219 = _out_backSel_T_1[219]; // @[OneHot.scala:58:35]
wire out_backSel_220 = _out_backSel_T_1[220]; // @[OneHot.scala:58:35]
wire out_backSel_221 = _out_backSel_T_1[221]; // @[OneHot.scala:58:35]
wire out_backSel_222 = _out_backSel_T_1[222]; // @[OneHot.scala:58:35]
wire out_backSel_223 = _out_backSel_T_1[223]; // @[OneHot.scala:58:35]
wire out_backSel_224 = _out_backSel_T_1[224]; // @[OneHot.scala:58:35]
wire out_backSel_225 = _out_backSel_T_1[225]; // @[OneHot.scala:58:35]
wire out_backSel_226 = _out_backSel_T_1[226]; // @[OneHot.scala:58:35]
wire out_backSel_227 = _out_backSel_T_1[227]; // @[OneHot.scala:58:35]
wire out_backSel_228 = _out_backSel_T_1[228]; // @[OneHot.scala:58:35]
wire out_backSel_229 = _out_backSel_T_1[229]; // @[OneHot.scala:58:35]
wire out_backSel_230 = _out_backSel_T_1[230]; // @[OneHot.scala:58:35]
wire out_backSel_231 = _out_backSel_T_1[231]; // @[OneHot.scala:58:35]
wire out_backSel_232 = _out_backSel_T_1[232]; // @[OneHot.scala:58:35]
wire out_backSel_233 = _out_backSel_T_1[233]; // @[OneHot.scala:58:35]
wire out_backSel_234 = _out_backSel_T_1[234]; // @[OneHot.scala:58:35]
wire out_backSel_235 = _out_backSel_T_1[235]; // @[OneHot.scala:58:35]
wire out_backSel_236 = _out_backSel_T_1[236]; // @[OneHot.scala:58:35]
wire out_backSel_237 = _out_backSel_T_1[237]; // @[OneHot.scala:58:35]
wire out_backSel_238 = _out_backSel_T_1[238]; // @[OneHot.scala:58:35]
wire out_backSel_239 = _out_backSel_T_1[239]; // @[OneHot.scala:58:35]
wire out_backSel_240 = _out_backSel_T_1[240]; // @[OneHot.scala:58:35]
wire out_backSel_241 = _out_backSel_T_1[241]; // @[OneHot.scala:58:35]
wire out_backSel_242 = _out_backSel_T_1[242]; // @[OneHot.scala:58:35]
wire out_backSel_243 = _out_backSel_T_1[243]; // @[OneHot.scala:58:35]
wire out_backSel_244 = _out_backSel_T_1[244]; // @[OneHot.scala:58:35]
wire out_backSel_245 = _out_backSel_T_1[245]; // @[OneHot.scala:58:35]
wire out_backSel_246 = _out_backSel_T_1[246]; // @[OneHot.scala:58:35]
wire out_backSel_247 = _out_backSel_T_1[247]; // @[OneHot.scala:58:35]
wire out_backSel_248 = _out_backSel_T_1[248]; // @[OneHot.scala:58:35]
wire out_backSel_249 = _out_backSel_T_1[249]; // @[OneHot.scala:58:35]
wire out_backSel_250 = _out_backSel_T_1[250]; // @[OneHot.scala:58:35]
wire out_backSel_251 = _out_backSel_T_1[251]; // @[OneHot.scala:58:35]
wire out_backSel_252 = _out_backSel_T_1[252]; // @[OneHot.scala:58:35]
wire out_backSel_253 = _out_backSel_T_1[253]; // @[OneHot.scala:58:35]
wire out_backSel_254 = _out_backSel_T_1[254]; // @[OneHot.scala:58:35]
wire out_backSel_255 = _out_backSel_T_1[255]; // @[OneHot.scala:58:35]
wire _GEN_22 = in_1_valid & out_front_1_ready; // @[RegisterRouter.scala:73:18, :87:24]
wire _out_rifireMux_T_259; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_259 = _GEN_22; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_260; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_260 = _GEN_22; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_260 = _out_rifireMux_T_259 & out_front_1_bits_read; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_261 = _out_rifireMux_T_260 & out_frontSel_0_1; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_262 = _out_rifireMux_T_261 & _out_T_1716; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_451 = _out_rifireMux_T_262; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_452 = _out_rifireMux_T_262; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_453 = _out_rifireMux_T_262; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_454 = _out_rifireMux_T_262; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_455 = _out_rifireMux_T_262; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_456 = _out_rifireMux_T_262; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_457 = _out_rifireMux_T_262; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_458 = _out_rifireMux_T_262; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_263 = ~_out_T_1716; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_265 = _out_rifireMux_T_260 & out_frontSel_1_1; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_266 = _out_rifireMux_T_265 & _out_T_1624; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_96 = _out_rifireMux_T_266; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_97 = _out_rifireMux_T_266; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_98 = _out_rifireMux_T_266; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_99 = _out_rifireMux_T_266; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_100 = _out_rifireMux_T_266; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_101 = _out_rifireMux_T_266; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_102 = _out_rifireMux_T_266; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_103 = _out_rifireMux_T_266; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_267 = ~_out_T_1624; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_269 = _out_rifireMux_T_260 & out_frontSel_2_1; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_270 = _out_rifireMux_T_269 & _out_T_1846; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_955 = _out_rifireMux_T_270; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_956 = _out_rifireMux_T_270; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_957 = _out_rifireMux_T_270; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_958 = _out_rifireMux_T_270; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_959 = _out_rifireMux_T_270; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_960 = _out_rifireMux_T_270; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_961 = _out_rifireMux_T_270; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_962 = _out_rifireMux_T_270; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_271 = ~_out_T_1846; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_273 = _out_rifireMux_T_260 & out_frontSel_3_1; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_274 = _out_rifireMux_T_273 & _out_T_1756; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_601 = _out_rifireMux_T_274; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_602 = _out_rifireMux_T_274; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_603 = _out_rifireMux_T_274; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_604 = _out_rifireMux_T_274; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_605 = _out_rifireMux_T_274; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_606 = _out_rifireMux_T_274; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_607 = _out_rifireMux_T_274; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_608 = _out_rifireMux_T_274; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_275 = ~_out_T_1756; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_277 = _out_rifireMux_T_260 & out_frontSel_4_1; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_278 = _out_rifireMux_T_277 & _out_T_1678; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_312 = _out_rifireMux_T_278; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_313 = _out_rifireMux_T_278; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_314 = _out_rifireMux_T_278; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_315 = _out_rifireMux_T_278; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_316 = _out_rifireMux_T_278; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_317 = _out_rifireMux_T_278; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_318 = _out_rifireMux_T_278; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_319 = _out_rifireMux_T_278; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_279 = ~_out_T_1678; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_281 = _out_rifireMux_T_260 & out_frontSel_5_1; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_282 = _out_rifireMux_T_281 & _out_T_1640; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_160 = _out_rifireMux_T_282; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_161 = _out_rifireMux_T_282; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_162 = _out_rifireMux_T_282; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_163 = _out_rifireMux_T_282; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_164 = _out_rifireMux_T_282; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_165 = _out_rifireMux_T_282; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_166 = _out_rifireMux_T_282; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_167 = _out_rifireMux_T_282; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_283 = ~_out_T_1640; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_285 = _out_rifireMux_T_260 & out_frontSel_6_1; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_286 = _out_rifireMux_T_285 & _out_T_1876; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1075 = _out_rifireMux_T_286; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1076 = _out_rifireMux_T_286; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1077 = _out_rifireMux_T_286; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1078 = _out_rifireMux_T_286; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1079 = _out_rifireMux_T_286; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1080 = _out_rifireMux_T_286; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1081 = _out_rifireMux_T_286; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1082 = _out_rifireMux_T_286; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_287 = ~_out_T_1876; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_289 = _out_rifireMux_T_260 & out_frontSel_7_1; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_290 = _out_rifireMux_T_289 & _out_T_1822; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_859 = _out_rifireMux_T_290; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_860 = _out_rifireMux_T_290; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_861 = _out_rifireMux_T_290; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_862 = _out_rifireMux_T_290; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_863 = _out_rifireMux_T_290; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_864 = _out_rifireMux_T_290; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_865 = _out_rifireMux_T_290; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_866 = _out_rifireMux_T_290; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_291 = ~_out_T_1822; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_293 = _out_rifireMux_T_260 & out_frontSel_8_1; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_294 = _out_rifireMux_T_293 & _out_T_1742; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_545 = _out_rifireMux_T_294; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_546 = _out_rifireMux_T_294; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_547 = _out_rifireMux_T_294; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_548 = _out_rifireMux_T_294; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_549 = _out_rifireMux_T_294; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_550 = _out_rifireMux_T_294; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_551 = _out_rifireMux_T_294; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_552 = _out_rifireMux_T_294; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_295 = ~_out_T_1742; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_297 = _out_rifireMux_T_260 & out_frontSel_9_1; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_298 = _out_rifireMux_T_297 & _out_T_1666; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_264 = _out_rifireMux_T_298; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_265 = _out_rifireMux_T_298; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_266 = _out_rifireMux_T_298; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_267 = _out_rifireMux_T_298; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_268 = _out_rifireMux_T_298; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_269 = _out_rifireMux_T_298; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_270 = _out_rifireMux_T_298; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_271 = _out_rifireMux_T_298; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_299 = ~_out_T_1666; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_301 = _out_rifireMux_T_260 & out_frontSel_10_1; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_302 = _out_rifireMux_T_301 & _out_T_1724; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_483 = _out_rifireMux_T_302; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_484 = _out_rifireMux_T_302; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_485 = _out_rifireMux_T_302; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_486 = _out_rifireMux_T_302; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_303 = ~_out_T_1724; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_305 = _out_rifireMux_T_260 & out_frontSel_11_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_306 = _out_rifireMux_T_305; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_309 = _out_rifireMux_T_260 & out_frontSel_12_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_310 = _out_rifireMux_T_309; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_313 = _out_rifireMux_T_260 & out_frontSel_13_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_314 = _out_rifireMux_T_313; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_317 = _out_rifireMux_T_260 & out_frontSel_14_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_318 = _out_rifireMux_T_317; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_321 = _out_rifireMux_T_260 & out_frontSel_15_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_322 = _out_rifireMux_T_321; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_325 = _out_rifireMux_T_260 & out_frontSel_16_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_326 = _out_rifireMux_T_325; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_329 = _out_rifireMux_T_260 & out_frontSel_17_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_330 = _out_rifireMux_T_329; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_333 = _out_rifireMux_T_260 & out_frontSel_18_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_334 = _out_rifireMux_T_333; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_337 = _out_rifireMux_T_260 & out_frontSel_19_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_338 = _out_rifireMux_T_337; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_341 = _out_rifireMux_T_260 & out_frontSel_20_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_342 = _out_rifireMux_T_341; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_345 = _out_rifireMux_T_260 & out_frontSel_21_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_346 = _out_rifireMux_T_345; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_349 = _out_rifireMux_T_260 & out_frontSel_22_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_350 = _out_rifireMux_T_349; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_353 = _out_rifireMux_T_260 & out_frontSel_23_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_354 = _out_rifireMux_T_353; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_357 = _out_rifireMux_T_260 & out_frontSel_24_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_358 = _out_rifireMux_T_357; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_361 = _out_rifireMux_T_260 & out_frontSel_25_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_362 = _out_rifireMux_T_361; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_365 = _out_rifireMux_T_260 & out_frontSel_26_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_366 = _out_rifireMux_T_365; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_369 = _out_rifireMux_T_260 & out_frontSel_27_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_370 = _out_rifireMux_T_369; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_373 = _out_rifireMux_T_260 & out_frontSel_28_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_374 = _out_rifireMux_T_373; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_377 = _out_rifireMux_T_260 & out_frontSel_29_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_378 = _out_rifireMux_T_377; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_381 = _out_rifireMux_T_260 & out_frontSel_30_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_382 = _out_rifireMux_T_381; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_385 = _out_rifireMux_T_260 & out_frontSel_31_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_386 = _out_rifireMux_T_385; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_389 = _out_rifireMux_T_260 & out_frontSel_32_1; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_390 = _out_rifireMux_T_389 & _out_T_1738; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_535 = _out_rifireMux_T_390; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_536 = _out_rifireMux_T_390; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_391 = ~_out_T_1738; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_393 = _out_rifireMux_T_260 & out_frontSel_33_1; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_394 = _out_rifireMux_T_393 & _out_T_1688; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_352 = _out_rifireMux_T_394; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_353 = _out_rifireMux_T_394; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_395 = ~_out_T_1688; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_397 = _out_rifireMux_T_260 & out_frontSel_34_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_398 = _out_rifireMux_T_397; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_401 = _out_rifireMux_T_260 & out_frontSel_35_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_402 = _out_rifireMux_T_401; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_405 = _out_rifireMux_T_260 & out_frontSel_36_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_406 = _out_rifireMux_T_405; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_409 = _out_rifireMux_T_260 & out_frontSel_37_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_410 = _out_rifireMux_T_409; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_413 = _out_rifireMux_T_260 & out_frontSel_38_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_414 = _out_rifireMux_T_413; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_417 = _out_rifireMux_T_260 & out_frontSel_39_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_418 = _out_rifireMux_T_417; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_421 = _out_rifireMux_T_260 & out_frontSel_40_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_422 = _out_rifireMux_T_421; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_425 = _out_rifireMux_T_260 & out_frontSel_41_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_426 = _out_rifireMux_T_425; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_429 = _out_rifireMux_T_260 & out_frontSel_42_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_430 = _out_rifireMux_T_429; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_433 = _out_rifireMux_T_260 & out_frontSel_43_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_434 = _out_rifireMux_T_433; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_437 = _out_rifireMux_T_260 & out_frontSel_44_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_438 = _out_rifireMux_T_437; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_441 = _out_rifireMux_T_260 & out_frontSel_45_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_442 = _out_rifireMux_T_441; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_445 = _out_rifireMux_T_260 & out_frontSel_46_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_446 = _out_rifireMux_T_445; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_449 = _out_rifireMux_T_260 & out_frontSel_47_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_450 = _out_rifireMux_T_449; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_453 = _out_rifireMux_T_260 & out_frontSel_48_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_454 = _out_rifireMux_T_453; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_457 = _out_rifireMux_T_260 & out_frontSel_49_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_458 = _out_rifireMux_T_457; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_461 = _out_rifireMux_T_260 & out_frontSel_50_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_462 = _out_rifireMux_T_461; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_465 = _out_rifireMux_T_260 & out_frontSel_51_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_466 = _out_rifireMux_T_465; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_469 = _out_rifireMux_T_260 & out_frontSel_52_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_470 = _out_rifireMux_T_469; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_473 = _out_rifireMux_T_260 & out_frontSel_53_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_474 = _out_rifireMux_T_473; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_477 = _out_rifireMux_T_260 & out_frontSel_54_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_478 = _out_rifireMux_T_477; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_481 = _out_rifireMux_T_260 & out_frontSel_55_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_482 = _out_rifireMux_T_481; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_485 = _out_rifireMux_T_260 & out_frontSel_56_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_486 = _out_rifireMux_T_485; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_489 = _out_rifireMux_T_260 & out_frontSel_57_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_490 = _out_rifireMux_T_489; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_493 = _out_rifireMux_T_260 & out_frontSel_58_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_494 = _out_rifireMux_T_493; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_497 = _out_rifireMux_T_260 & out_frontSel_59_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_498 = _out_rifireMux_T_497; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_501 = _out_rifireMux_T_260 & out_frontSel_60_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_502 = _out_rifireMux_T_501; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_505 = _out_rifireMux_T_260 & out_frontSel_61_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_506 = _out_rifireMux_T_505; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_509 = _out_rifireMux_T_260 & out_frontSel_62_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_510 = _out_rifireMux_T_509; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_513 = _out_rifireMux_T_260 & out_frontSel_63_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_514 = _out_rifireMux_T_513; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_517 = _out_rifireMux_T_260 & out_frontSel_64; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_518 = _out_rifireMux_T_517; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_521 = _out_rifireMux_T_260 & out_frontSel_65; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_522 = _out_rifireMux_T_521; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_525 = _out_rifireMux_T_260 & out_frontSel_66; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_526 = _out_rifireMux_T_525; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_529 = _out_rifireMux_T_260 & out_frontSel_67; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_530 = _out_rifireMux_T_529; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_533 = _out_rifireMux_T_260 & out_frontSel_68; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_534 = _out_rifireMux_T_533; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_537 = _out_rifireMux_T_260 & out_frontSel_69; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_538 = _out_rifireMux_T_537; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_541 = _out_rifireMux_T_260 & out_frontSel_70; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_542 = _out_rifireMux_T_541; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_545 = _out_rifireMux_T_260 & out_frontSel_71; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_546 = _out_rifireMux_T_545; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_549 = _out_rifireMux_T_260 & out_frontSel_72; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_550 = _out_rifireMux_T_549; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_553 = _out_rifireMux_T_260 & out_frontSel_73; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_554 = _out_rifireMux_T_553; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_557 = _out_rifireMux_T_260 & out_frontSel_74; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_558 = _out_rifireMux_T_557; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_561 = _out_rifireMux_T_260 & out_frontSel_75; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_562 = _out_rifireMux_T_561; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_565 = _out_rifireMux_T_260 & out_frontSel_76; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_566 = _out_rifireMux_T_565; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_569 = _out_rifireMux_T_260 & out_frontSel_77; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_570 = _out_rifireMux_T_569; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_573 = _out_rifireMux_T_260 & out_frontSel_78; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_574 = _out_rifireMux_T_573; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_577 = _out_rifireMux_T_260 & out_frontSel_79; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_578 = _out_rifireMux_T_577; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_581 = _out_rifireMux_T_260 & out_frontSel_80; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_582 = _out_rifireMux_T_581; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_585 = _out_rifireMux_T_260 & out_frontSel_81; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_586 = _out_rifireMux_T_585; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_589 = _out_rifireMux_T_260 & out_frontSel_82; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_590 = _out_rifireMux_T_589; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_593 = _out_rifireMux_T_260 & out_frontSel_83; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_594 = _out_rifireMux_T_593; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_597 = _out_rifireMux_T_260 & out_frontSel_84; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_598 = _out_rifireMux_T_597; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_601 = _out_rifireMux_T_260 & out_frontSel_85; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_602 = _out_rifireMux_T_601; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_605 = _out_rifireMux_T_260 & out_frontSel_86; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_606 = _out_rifireMux_T_605; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_609 = _out_rifireMux_T_260 & out_frontSel_87; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_610 = _out_rifireMux_T_609; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_613 = _out_rifireMux_T_260 & out_frontSel_88; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_614 = _out_rifireMux_T_613; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_617 = _out_rifireMux_T_260 & out_frontSel_89; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_618 = _out_rifireMux_T_617; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_621 = _out_rifireMux_T_260 & out_frontSel_90; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_622 = _out_rifireMux_T_621; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_625 = _out_rifireMux_T_260 & out_frontSel_91; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_626 = _out_rifireMux_T_625; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_629 = _out_rifireMux_T_260 & out_frontSel_92; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_630 = _out_rifireMux_T_629; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_633 = _out_rifireMux_T_260 & out_frontSel_93; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_634 = _out_rifireMux_T_633; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_637 = _out_rifireMux_T_260 & out_frontSel_94; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_638 = _out_rifireMux_T_637; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_641 = _out_rifireMux_T_260 & out_frontSel_95; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_642 = _out_rifireMux_T_641; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_645 = _out_rifireMux_T_260 & out_frontSel_96; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_646 = _out_rifireMux_T_645 & _out_T_1712; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_442 = _out_rifireMux_T_646; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_647 = ~_out_T_1712; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_649 = _out_rifireMux_T_260 & out_frontSel_97; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_650 = _out_rifireMux_T_649; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_653 = _out_rifireMux_T_260 & out_frontSel_98; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_654 = _out_rifireMux_T_653; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_657 = _out_rifireMux_T_260 & out_frontSel_99; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_658 = _out_rifireMux_T_657; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_661 = _out_rifireMux_T_260 & out_frontSel_100; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_662 = _out_rifireMux_T_661; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_665 = _out_rifireMux_T_260 & out_frontSel_101; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_666 = _out_rifireMux_T_665; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_669 = _out_rifireMux_T_260 & out_frontSel_102; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_670 = _out_rifireMux_T_669; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_673 = _out_rifireMux_T_260 & out_frontSel_103; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_674 = _out_rifireMux_T_673 & _out_T_1780; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_697 = _out_rifireMux_T_674; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_698 = _out_rifireMux_T_674; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_675 = ~_out_T_1780; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_677 = _out_rifireMux_T_260 & out_frontSel_104; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_678 = _out_rifireMux_T_677 & _out_T_1840; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_931 = _out_rifireMux_T_678; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_932 = _out_rifireMux_T_678; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_933 = _out_rifireMux_T_678; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_934 = _out_rifireMux_T_678; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_935 = _out_rifireMux_T_678; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_936 = _out_rifireMux_T_678; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_937 = _out_rifireMux_T_678; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_938 = _out_rifireMux_T_678; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_679 = ~_out_T_1840; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_681 = _out_rifireMux_T_260 & out_frontSel_105; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_682 = _out_rifireMux_T_681 & _out_T_1732; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_511 = _out_rifireMux_T_682; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_512 = _out_rifireMux_T_682; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_513 = _out_rifireMux_T_682; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_514 = _out_rifireMux_T_682; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_515 = _out_rifireMux_T_682; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_516 = _out_rifireMux_T_682; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_517 = _out_rifireMux_T_682; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_518 = _out_rifireMux_T_682; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_683 = ~_out_T_1732; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_685 = _out_rifireMux_T_260 & out_frontSel_106; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_686 = _out_rifireMux_T_685 & _out_T_1648; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_192 = _out_rifireMux_T_686; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_193 = _out_rifireMux_T_686; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_194 = _out_rifireMux_T_686; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_195 = _out_rifireMux_T_686; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_196 = _out_rifireMux_T_686; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_197 = _out_rifireMux_T_686; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_198 = _out_rifireMux_T_686; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_199 = _out_rifireMux_T_686; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_687 = ~_out_T_1648; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_689 = _out_rifireMux_T_260 & out_frontSel_107; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_690 = _out_rifireMux_T_689 & _out_T_1880; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1091 = _out_rifireMux_T_690; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1092 = _out_rifireMux_T_690; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1093 = _out_rifireMux_T_690; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1094 = _out_rifireMux_T_690; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1095 = _out_rifireMux_T_690; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1096 = _out_rifireMux_T_690; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1097 = _out_rifireMux_T_690; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1098 = _out_rifireMux_T_690; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_691 = ~_out_T_1880; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_693 = _out_rifireMux_T_260 & out_frontSel_108; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_694 = _out_rifireMux_T_693 & _out_T_1790; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_731 = _out_rifireMux_T_694; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_732 = _out_rifireMux_T_694; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_733 = _out_rifireMux_T_694; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_734 = _out_rifireMux_T_694; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_735 = _out_rifireMux_T_694; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_736 = _out_rifireMux_T_694; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_737 = _out_rifireMux_T_694; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_738 = _out_rifireMux_T_694; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_695 = ~_out_T_1790; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_697 = _out_rifireMux_T_260 & out_frontSel_109; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_698 = _out_rifireMux_T_697 & _out_T_1714; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_443 = _out_rifireMux_T_698; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_444 = _out_rifireMux_T_698; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_445 = _out_rifireMux_T_698; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_446 = _out_rifireMux_T_698; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_447 = _out_rifireMux_T_698; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_448 = _out_rifireMux_T_698; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_449 = _out_rifireMux_T_698; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_450 = _out_rifireMux_T_698; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_699 = ~_out_T_1714; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_701 = _out_rifireMux_T_260 & out_frontSel_110; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_702 = _out_rifireMux_T_701 & _out_T_1628; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_112 = _out_rifireMux_T_702; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_113 = _out_rifireMux_T_702; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_114 = _out_rifireMux_T_702; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_115 = _out_rifireMux_T_702; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_116 = _out_rifireMux_T_702; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_117 = _out_rifireMux_T_702; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_118 = _out_rifireMux_T_702; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_119 = _out_rifireMux_T_702; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_703 = ~_out_T_1628; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_705 = _out_rifireMux_T_260 & out_frontSel_111; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_706 = _out_rifireMux_T_705 & _out_T_1898; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1163 = _out_rifireMux_T_706; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1164 = _out_rifireMux_T_706; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1165 = _out_rifireMux_T_706; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1166 = _out_rifireMux_T_706; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1167 = _out_rifireMux_T_706; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1168 = _out_rifireMux_T_706; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1169 = _out_rifireMux_T_706; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1170 = _out_rifireMux_T_706; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_707 = ~_out_T_1898; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_709 = _out_rifireMux_T_260 & out_frontSel_112; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_710 = _out_rifireMux_T_709 & _out_T_1814; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_827 = _out_rifireMux_T_710; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_828 = _out_rifireMux_T_710; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_829 = _out_rifireMux_T_710; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_830 = _out_rifireMux_T_710; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_831 = _out_rifireMux_T_710; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_832 = _out_rifireMux_T_710; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_833 = _out_rifireMux_T_710; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_834 = _out_rifireMux_T_710; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_711 = ~_out_T_1814; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_713 = _out_rifireMux_T_260 & out_frontSel_113; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_714 = _out_rifireMux_T_713 & _out_T_1770; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_657 = _out_rifireMux_T_714; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_658 = _out_rifireMux_T_714; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_659 = _out_rifireMux_T_714; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_660 = _out_rifireMux_T_714; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_661 = _out_rifireMux_T_714; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_662 = _out_rifireMux_T_714; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_663 = _out_rifireMux_T_714; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_664 = _out_rifireMux_T_714; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_715 = ~_out_T_1770; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_717 = _out_rifireMux_T_260 & out_frontSel_114; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_718 = _out_rifireMux_T_717 & _out_T_1852; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_979 = _out_rifireMux_T_718; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_980 = _out_rifireMux_T_718; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_981 = _out_rifireMux_T_718; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_982 = _out_rifireMux_T_718; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_983 = _out_rifireMux_T_718; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_984 = _out_rifireMux_T_718; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_985 = _out_rifireMux_T_718; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_986 = _out_rifireMux_T_718; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_719 = ~_out_T_1852; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_721 = _out_rifireMux_T_260 & out_frontSel_115; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_722 = _out_rifireMux_T_721 & _out_T_1608; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_32 = _out_rifireMux_T_722; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_33 = _out_rifireMux_T_722; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_34 = _out_rifireMux_T_722; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_35 = _out_rifireMux_T_722; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_36 = _out_rifireMux_T_722; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_37 = _out_rifireMux_T_722; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_38 = _out_rifireMux_T_722; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_39 = _out_rifireMux_T_722; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_723 = ~_out_T_1608; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_725 = _out_rifireMux_T_260 & out_frontSel_116; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_726 = _out_rifireMux_T_725; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_729 = _out_rifireMux_T_260 & out_frontSel_117; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_730 = _out_rifireMux_T_729; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_733 = _out_rifireMux_T_260 & out_frontSel_118; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_734 = _out_rifireMux_T_733; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_737 = _out_rifireMux_T_260 & out_frontSel_119; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_738 = _out_rifireMux_T_737; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_741 = _out_rifireMux_T_260 & out_frontSel_120; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_742 = _out_rifireMux_T_741; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_745 = _out_rifireMux_T_260 & out_frontSel_121; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_746 = _out_rifireMux_T_745; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_749 = _out_rifireMux_T_260 & out_frontSel_122; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_750 = _out_rifireMux_T_749; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_753 = _out_rifireMux_T_260 & out_frontSel_123; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_754 = _out_rifireMux_T_753; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_757 = _out_rifireMux_T_260 & out_frontSel_124; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_758 = _out_rifireMux_T_757; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_761 = _out_rifireMux_T_260 & out_frontSel_125; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_762 = _out_rifireMux_T_761; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_765 = _out_rifireMux_T_260 & out_frontSel_126; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_766 = _out_rifireMux_T_765; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_769 = _out_rifireMux_T_260 & out_frontSel_127; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_770 = _out_rifireMux_T_769; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_773 = _out_rifireMux_T_260 & out_frontSel_128; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_774 = _out_rifireMux_T_773 & _out_T_1728; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_495 = _out_rifireMux_T_774; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_496 = _out_rifireMux_T_774; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_497 = _out_rifireMux_T_774; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_498 = _out_rifireMux_T_774; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_499 = _out_rifireMux_T_774; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_500 = _out_rifireMux_T_774; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_501 = _out_rifireMux_T_774; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_502 = _out_rifireMux_T_774; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_775 = ~_out_T_1728; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_777 = _out_rifireMux_T_260 & out_frontSel_129; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_778 = _out_rifireMux_T_777 & _out_T_1720; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_467 = _out_rifireMux_T_778; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_468 = _out_rifireMux_T_778; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_469 = _out_rifireMux_T_778; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_470 = _out_rifireMux_T_778; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_471 = _out_rifireMux_T_778; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_472 = _out_rifireMux_T_778; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_473 = _out_rifireMux_T_778; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_474 = _out_rifireMux_T_778; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_779 = ~_out_T_1720; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_781 = _out_rifireMux_T_260 & out_frontSel_130; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_782 = _out_rifireMux_T_781 & _out_T_1796; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_755 = _out_rifireMux_T_782; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_756 = _out_rifireMux_T_782; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_757 = _out_rifireMux_T_782; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_758 = _out_rifireMux_T_782; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_759 = _out_rifireMux_T_782; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_760 = _out_rifireMux_T_782; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_761 = _out_rifireMux_T_782; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_762 = _out_rifireMux_T_782; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_783 = ~_out_T_1796; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_785 = _out_rifireMux_T_260 & out_frontSel_131; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_786 = _out_rifireMux_T_785 & _out_T_1890; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1131 = _out_rifireMux_T_786; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1132 = _out_rifireMux_T_786; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1133 = _out_rifireMux_T_786; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1134 = _out_rifireMux_T_786; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1135 = _out_rifireMux_T_786; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1136 = _out_rifireMux_T_786; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1137 = _out_rifireMux_T_786; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1138 = _out_rifireMux_T_786; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_787 = ~_out_T_1890; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_789 = _out_rifireMux_T_260 & out_frontSel_132; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_790 = _out_rifireMux_T_789 & _out_T_1660; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_240 = _out_rifireMux_T_790; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_241 = _out_rifireMux_T_790; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_242 = _out_rifireMux_T_790; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_243 = _out_rifireMux_T_790; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_244 = _out_rifireMux_T_790; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_245 = _out_rifireMux_T_790; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_246 = _out_rifireMux_T_790; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_247 = _out_rifireMux_T_790; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_791 = ~_out_T_1660; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_793 = _out_rifireMux_T_260 & out_frontSel_133; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_794 = _out_rifireMux_T_793 & _out_T_1662; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_248 = _out_rifireMux_T_794; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_249 = _out_rifireMux_T_794; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_250 = _out_rifireMux_T_794; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_251 = _out_rifireMux_T_794; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_252 = _out_rifireMux_T_794; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_253 = _out_rifireMux_T_794; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_254 = _out_rifireMux_T_794; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_255 = _out_rifireMux_T_794; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_795 = ~_out_T_1662; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_797 = _out_rifireMux_T_260 & out_frontSel_134; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_798 = _out_rifireMux_T_797 & _out_T_1722; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_475 = _out_rifireMux_T_798; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_476 = _out_rifireMux_T_798; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_477 = _out_rifireMux_T_798; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_478 = _out_rifireMux_T_798; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_479 = _out_rifireMux_T_798; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_480 = _out_rifireMux_T_798; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_481 = _out_rifireMux_T_798; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_482 = _out_rifireMux_T_798; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_799 = ~_out_T_1722; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_801 = _out_rifireMux_T_260 & out_frontSel_135; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_802 = _out_rifireMux_T_801 & _out_T_1800; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_771 = _out_rifireMux_T_802; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_772 = _out_rifireMux_T_802; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_773 = _out_rifireMux_T_802; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_774 = _out_rifireMux_T_802; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_775 = _out_rifireMux_T_802; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_776 = _out_rifireMux_T_802; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_777 = _out_rifireMux_T_802; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_778 = _out_rifireMux_T_802; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_803 = ~_out_T_1800; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_805 = _out_rifireMux_T_260 & out_frontSel_136; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_806 = _out_rifireMux_T_805 & _out_T_1882; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1099 = _out_rifireMux_T_806; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1100 = _out_rifireMux_T_806; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1101 = _out_rifireMux_T_806; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1102 = _out_rifireMux_T_806; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1103 = _out_rifireMux_T_806; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1104 = _out_rifireMux_T_806; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1105 = _out_rifireMux_T_806; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1106 = _out_rifireMux_T_806; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_807 = ~_out_T_1882; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_809 = _out_rifireMux_T_260 & out_frontSel_137; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_810 = _out_rifireMux_T_809 & _out_T_1684; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_336 = _out_rifireMux_T_810; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_337 = _out_rifireMux_T_810; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_338 = _out_rifireMux_T_810; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_339 = _out_rifireMux_T_810; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_340 = _out_rifireMux_T_810; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_341 = _out_rifireMux_T_810; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_342 = _out_rifireMux_T_810; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_343 = _out_rifireMux_T_810; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_811 = ~_out_T_1684; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_813 = _out_rifireMux_T_260 & out_frontSel_138; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_814 = _out_rifireMux_T_813 & _out_T_1600; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_0 = _out_rifireMux_T_814; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1 = _out_rifireMux_T_814; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_2 = _out_rifireMux_T_814; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_3 = _out_rifireMux_T_814; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_4 = _out_rifireMux_T_814; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_5 = _out_rifireMux_T_814; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_6 = _out_rifireMux_T_814; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_7 = _out_rifireMux_T_814; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_815 = ~_out_T_1600; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_817 = _out_rifireMux_T_260 & out_frontSel_139; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_818 = _out_rifireMux_T_817 & _out_T_1856; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_995 = _out_rifireMux_T_818; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_996 = _out_rifireMux_T_818; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_997 = _out_rifireMux_T_818; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_998 = _out_rifireMux_T_818; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_999 = _out_rifireMux_T_818; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1000 = _out_rifireMux_T_818; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1001 = _out_rifireMux_T_818; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1002 = _out_rifireMux_T_818; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_819 = ~_out_T_1856; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_821 = _out_rifireMux_T_260 & out_frontSel_140; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_822 = _out_rifireMux_T_821 & _out_T_1782; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_699 = _out_rifireMux_T_822; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_700 = _out_rifireMux_T_822; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_701 = _out_rifireMux_T_822; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_702 = _out_rifireMux_T_822; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_703 = _out_rifireMux_T_822; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_704 = _out_rifireMux_T_822; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_705 = _out_rifireMux_T_822; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_706 = _out_rifireMux_T_822; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_823 = ~_out_T_1782; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_825 = _out_rifireMux_T_260 & out_frontSel_141; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_826 = _out_rifireMux_T_825 & _out_T_1704; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_410 = _out_rifireMux_T_826; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_411 = _out_rifireMux_T_826; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_412 = _out_rifireMux_T_826; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_413 = _out_rifireMux_T_826; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_414 = _out_rifireMux_T_826; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_415 = _out_rifireMux_T_826; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_416 = _out_rifireMux_T_826; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_417 = _out_rifireMux_T_826; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_827 = ~_out_T_1704; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_829 = _out_rifireMux_T_260 & out_frontSel_142; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_830 = _out_rifireMux_T_829 & _out_T_1616; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_64 = _out_rifireMux_T_830; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_65 = _out_rifireMux_T_830; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_66 = _out_rifireMux_T_830; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_67 = _out_rifireMux_T_830; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_68 = _out_rifireMux_T_830; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_69 = _out_rifireMux_T_830; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_70 = _out_rifireMux_T_830; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_71 = _out_rifireMux_T_830; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_831 = ~_out_T_1616; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_833 = _out_rifireMux_T_260 & out_frontSel_143; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_834 = _out_rifireMux_T_833 & _out_T_1834; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_907 = _out_rifireMux_T_834; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_908 = _out_rifireMux_T_834; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_909 = _out_rifireMux_T_834; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_910 = _out_rifireMux_T_834; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_911 = _out_rifireMux_T_834; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_912 = _out_rifireMux_T_834; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_913 = _out_rifireMux_T_834; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_914 = _out_rifireMux_T_834; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_835 = ~_out_T_1834; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_837 = _out_rifireMux_T_260 & out_frontSel_144; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_838 = _out_rifireMux_T_837 & _out_T_1758; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_609 = _out_rifireMux_T_838; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_610 = _out_rifireMux_T_838; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_611 = _out_rifireMux_T_838; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_612 = _out_rifireMux_T_838; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_613 = _out_rifireMux_T_838; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_614 = _out_rifireMux_T_838; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_615 = _out_rifireMux_T_838; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_616 = _out_rifireMux_T_838; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_839 = ~_out_T_1758; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_841 = _out_rifireMux_T_260 & out_frontSel_145; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_842 = _out_rifireMux_T_841 & _out_T_1818; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_843 = _out_rifireMux_T_842; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_844 = _out_rifireMux_T_842; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_845 = _out_rifireMux_T_842; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_846 = _out_rifireMux_T_842; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_847 = _out_rifireMux_T_842; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_848 = _out_rifireMux_T_842; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_849 = _out_rifireMux_T_842; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_850 = _out_rifireMux_T_842; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_843 = ~_out_T_1818; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_845 = _out_rifireMux_T_260 & out_frontSel_146; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_846 = _out_rifireMux_T_845 & _out_T_1868; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1043 = _out_rifireMux_T_846; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1044 = _out_rifireMux_T_846; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1045 = _out_rifireMux_T_846; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1046 = _out_rifireMux_T_846; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1047 = _out_rifireMux_T_846; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1048 = _out_rifireMux_T_846; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1049 = _out_rifireMux_T_846; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1050 = _out_rifireMux_T_846; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_847 = ~_out_T_1868; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_849 = _out_rifireMux_T_260 & out_frontSel_147; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_850 = _out_rifireMux_T_849 & _out_T_1656; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_224 = _out_rifireMux_T_850; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_225 = _out_rifireMux_T_850; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_226 = _out_rifireMux_T_850; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_227 = _out_rifireMux_T_850; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_228 = _out_rifireMux_T_850; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_229 = _out_rifireMux_T_850; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_230 = _out_rifireMux_T_850; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_231 = _out_rifireMux_T_850; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_851 = ~_out_T_1656; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_853 = _out_rifireMux_T_260 & out_frontSel_148; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_854 = _out_rifireMux_T_853 & _out_T_1740; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_537 = _out_rifireMux_T_854; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_538 = _out_rifireMux_T_854; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_539 = _out_rifireMux_T_854; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_540 = _out_rifireMux_T_854; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_541 = _out_rifireMux_T_854; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_542 = _out_rifireMux_T_854; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_543 = _out_rifireMux_T_854; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_544 = _out_rifireMux_T_854; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_855 = ~_out_T_1740; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_857 = _out_rifireMux_T_260 & out_frontSel_149; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_858 = _out_rifireMux_T_857 & _out_T_1748; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_569 = _out_rifireMux_T_858; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_570 = _out_rifireMux_T_858; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_571 = _out_rifireMux_T_858; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_572 = _out_rifireMux_T_858; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_573 = _out_rifireMux_T_858; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_574 = _out_rifireMux_T_858; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_575 = _out_rifireMux_T_858; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_576 = _out_rifireMux_T_858; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_859 = ~_out_T_1748; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_861 = _out_rifireMux_T_260 & out_frontSel_150; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_862 = _out_rifireMux_T_861 & _out_T_1820; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_851 = _out_rifireMux_T_862; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_852 = _out_rifireMux_T_862; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_853 = _out_rifireMux_T_862; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_854 = _out_rifireMux_T_862; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_855 = _out_rifireMux_T_862; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_856 = _out_rifireMux_T_862; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_857 = _out_rifireMux_T_862; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_858 = _out_rifireMux_T_862; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_863 = ~_out_T_1820; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_865 = _out_rifireMux_T_260 & out_frontSel_151; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_866 = _out_rifireMux_T_865 & _out_T_1866; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1035 = _out_rifireMux_T_866; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1036 = _out_rifireMux_T_866; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1037 = _out_rifireMux_T_866; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1038 = _out_rifireMux_T_866; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1039 = _out_rifireMux_T_866; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1040 = _out_rifireMux_T_866; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1041 = _out_rifireMux_T_866; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1042 = _out_rifireMux_T_866; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_867 = ~_out_T_1866; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_869 = _out_rifireMux_T_260 & out_frontSel_152; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_870 = _out_rifireMux_T_869 & _out_T_1636; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_144 = _out_rifireMux_T_870; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_145 = _out_rifireMux_T_870; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_146 = _out_rifireMux_T_870; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_147 = _out_rifireMux_T_870; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_148 = _out_rifireMux_T_870; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_149 = _out_rifireMux_T_870; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_150 = _out_rifireMux_T_870; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_151 = _out_rifireMux_T_870; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_871 = ~_out_T_1636; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_873 = _out_rifireMux_T_260 & out_frontSel_153; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_874 = _out_rifireMux_T_873 & _out_T_1618; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_72 = _out_rifireMux_T_874; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_73 = _out_rifireMux_T_874; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_74 = _out_rifireMux_T_874; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_75 = _out_rifireMux_T_874; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_76 = _out_rifireMux_T_874; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_77 = _out_rifireMux_T_874; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_78 = _out_rifireMux_T_874; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_79 = _out_rifireMux_T_874; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_875 = ~_out_T_1618; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_877 = _out_rifireMux_T_260 & out_frontSel_154; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_878 = _out_rifireMux_T_877 & _out_T_1830; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_891 = _out_rifireMux_T_878; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_892 = _out_rifireMux_T_878; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_893 = _out_rifireMux_T_878; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_894 = _out_rifireMux_T_878; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_895 = _out_rifireMux_T_878; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_896 = _out_rifireMux_T_878; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_897 = _out_rifireMux_T_878; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_898 = _out_rifireMux_T_878; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_879 = ~_out_T_1830; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_881 = _out_rifireMux_T_260 & out_frontSel_155; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_882 = _out_rifireMux_T_881 & _out_T_1786; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_715 = _out_rifireMux_T_882; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_716 = _out_rifireMux_T_882; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_717 = _out_rifireMux_T_882; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_718 = _out_rifireMux_T_882; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_719 = _out_rifireMux_T_882; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_720 = _out_rifireMux_T_882; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_721 = _out_rifireMux_T_882; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_722 = _out_rifireMux_T_882; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_883 = ~_out_T_1786; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_885 = _out_rifireMux_T_260 & out_frontSel_156; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_886 = _out_rifireMux_T_885 & _out_T_1698; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_386 = _out_rifireMux_T_886; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_387 = _out_rifireMux_T_886; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_388 = _out_rifireMux_T_886; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_389 = _out_rifireMux_T_886; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_390 = _out_rifireMux_T_886; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_391 = _out_rifireMux_T_886; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_392 = _out_rifireMux_T_886; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_393 = _out_rifireMux_T_886; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_887 = ~_out_T_1698; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_889 = _out_rifireMux_T_260 & out_frontSel_157; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_890 = _out_rifireMux_T_889 & _out_T_1632; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_128 = _out_rifireMux_T_890; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_129 = _out_rifireMux_T_890; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_130 = _out_rifireMux_T_890; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_131 = _out_rifireMux_T_890; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_132 = _out_rifireMux_T_890; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_133 = _out_rifireMux_T_890; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_134 = _out_rifireMux_T_890; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_135 = _out_rifireMux_T_890; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_891 = ~_out_T_1632; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_893 = _out_rifireMux_T_260 & out_frontSel_158; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_894 = _out_rifireMux_T_893 & _out_T_1848; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_963 = _out_rifireMux_T_894; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_964 = _out_rifireMux_T_894; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_965 = _out_rifireMux_T_894; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_966 = _out_rifireMux_T_894; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_967 = _out_rifireMux_T_894; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_968 = _out_rifireMux_T_894; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_969 = _out_rifireMux_T_894; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_970 = _out_rifireMux_T_894; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_895 = ~_out_T_1848; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_897 = _out_rifireMux_T_260 & out_frontSel_159; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_898 = _out_rifireMux_T_897 & _out_T_1764; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_633 = _out_rifireMux_T_898; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_634 = _out_rifireMux_T_898; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_635 = _out_rifireMux_T_898; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_636 = _out_rifireMux_T_898; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_637 = _out_rifireMux_T_898; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_638 = _out_rifireMux_T_898; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_639 = _out_rifireMux_T_898; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_640 = _out_rifireMux_T_898; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_899 = ~_out_T_1764; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_901 = _out_rifireMux_T_260 & out_frontSel_160; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_902 = _out_rifireMux_T_901 & _out_T_1680; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_320 = _out_rifireMux_T_902; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_321 = _out_rifireMux_T_902; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_322 = _out_rifireMux_T_902; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_323 = _out_rifireMux_T_902; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_324 = _out_rifireMux_T_902; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_325 = _out_rifireMux_T_902; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_326 = _out_rifireMux_T_902; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_327 = _out_rifireMux_T_902; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_903 = ~_out_T_1680; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_905 = _out_rifireMux_T_260 & out_frontSel_161; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_906 = _out_rifireMux_T_905 & _out_T_1744; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_553 = _out_rifireMux_T_906; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_554 = _out_rifireMux_T_906; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_555 = _out_rifireMux_T_906; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_556 = _out_rifireMux_T_906; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_557 = _out_rifireMux_T_906; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_558 = _out_rifireMux_T_906; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_559 = _out_rifireMux_T_906; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_560 = _out_rifireMux_T_906; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_907 = ~_out_T_1744; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_909 = _out_rifireMux_T_260 & out_frontSel_162; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_910 = _out_rifireMux_T_909 & _out_T_1808; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_803 = _out_rifireMux_T_910; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_804 = _out_rifireMux_T_910; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_805 = _out_rifireMux_T_910; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_806 = _out_rifireMux_T_910; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_807 = _out_rifireMux_T_910; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_808 = _out_rifireMux_T_910; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_809 = _out_rifireMux_T_910; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_810 = _out_rifireMux_T_910; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_911 = ~_out_T_1808; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_913 = _out_rifireMux_T_260 & out_frontSel_163; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_914 = _out_rifireMux_T_913 & _out_T_1894; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1147 = _out_rifireMux_T_914; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1148 = _out_rifireMux_T_914; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1149 = _out_rifireMux_T_914; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1150 = _out_rifireMux_T_914; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1151 = _out_rifireMux_T_914; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1152 = _out_rifireMux_T_914; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1153 = _out_rifireMux_T_914; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1154 = _out_rifireMux_T_914; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_915 = ~_out_T_1894; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_917 = _out_rifireMux_T_260 & out_frontSel_164; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_918 = _out_rifireMux_T_917 & _out_T_1644; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_176 = _out_rifireMux_T_918; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_177 = _out_rifireMux_T_918; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_178 = _out_rifireMux_T_918; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_179 = _out_rifireMux_T_918; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_180 = _out_rifireMux_T_918; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_181 = _out_rifireMux_T_918; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_182 = _out_rifireMux_T_918; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_183 = _out_rifireMux_T_918; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_919 = ~_out_T_1644; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_921 = _out_rifireMux_T_260 & out_frontSel_165; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_922 = _out_rifireMux_T_921 & _out_T_1686; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_344 = _out_rifireMux_T_922; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_345 = _out_rifireMux_T_922; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_346 = _out_rifireMux_T_922; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_347 = _out_rifireMux_T_922; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_348 = _out_rifireMux_T_922; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_349 = _out_rifireMux_T_922; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_350 = _out_rifireMux_T_922; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_351 = _out_rifireMux_T_922; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_923 = ~_out_T_1686; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_925 = _out_rifireMux_T_260 & out_frontSel_166; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_926 = _out_rifireMux_T_925 & _out_T_1736; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_527 = _out_rifireMux_T_926; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_528 = _out_rifireMux_T_926; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_529 = _out_rifireMux_T_926; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_530 = _out_rifireMux_T_926; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_531 = _out_rifireMux_T_926; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_532 = _out_rifireMux_T_926; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_533 = _out_rifireMux_T_926; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_534 = _out_rifireMux_T_926; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_927 = ~_out_T_1736; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_929 = _out_rifireMux_T_260 & out_frontSel_167; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_930 = _out_rifireMux_T_929 & _out_T_1806; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_795 = _out_rifireMux_T_930; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_796 = _out_rifireMux_T_930; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_797 = _out_rifireMux_T_930; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_798 = _out_rifireMux_T_930; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_799 = _out_rifireMux_T_930; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_800 = _out_rifireMux_T_930; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_801 = _out_rifireMux_T_930; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_802 = _out_rifireMux_T_930; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_931 = ~_out_T_1806; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_933 = _out_rifireMux_T_260 & out_frontSel_168; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_934 = _out_rifireMux_T_933 & _out_T_1874; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1067 = _out_rifireMux_T_934; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1068 = _out_rifireMux_T_934; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1069 = _out_rifireMux_T_934; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1070 = _out_rifireMux_T_934; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1071 = _out_rifireMux_T_934; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1072 = _out_rifireMux_T_934; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1073 = _out_rifireMux_T_934; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1074 = _out_rifireMux_T_934; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_935 = ~_out_T_1874; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_937 = _out_rifireMux_T_260 & out_frontSel_169; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_938 = _out_rifireMux_T_937 & _out_T_1702; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_402 = _out_rifireMux_T_938; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_403 = _out_rifireMux_T_938; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_404 = _out_rifireMux_T_938; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_405 = _out_rifireMux_T_938; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_406 = _out_rifireMux_T_938; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_407 = _out_rifireMux_T_938; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_408 = _out_rifireMux_T_938; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_409 = _out_rifireMux_T_938; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_939 = ~_out_T_1702; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_941 = _out_rifireMux_T_260 & out_frontSel_170; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_942 = _out_rifireMux_T_941 & _out_T_1606; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_24 = _out_rifireMux_T_942; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_25 = _out_rifireMux_T_942; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_26 = _out_rifireMux_T_942; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_27 = _out_rifireMux_T_942; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_28 = _out_rifireMux_T_942; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_29 = _out_rifireMux_T_942; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_30 = _out_rifireMux_T_942; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_31 = _out_rifireMux_T_942; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_943 = ~_out_T_1606; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_945 = _out_rifireMux_T_260 & out_frontSel_171; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_946 = _out_rifireMux_T_945 & _out_T_1854; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_987 = _out_rifireMux_T_946; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_988 = _out_rifireMux_T_946; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_989 = _out_rifireMux_T_946; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_990 = _out_rifireMux_T_946; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_991 = _out_rifireMux_T_946; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_992 = _out_rifireMux_T_946; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_993 = _out_rifireMux_T_946; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_994 = _out_rifireMux_T_946; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_947 = ~_out_T_1854; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_949 = _out_rifireMux_T_260 & out_frontSel_172; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_950 = _out_rifireMux_T_949 & _out_T_1768; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_649 = _out_rifireMux_T_950; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_650 = _out_rifireMux_T_950; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_651 = _out_rifireMux_T_950; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_652 = _out_rifireMux_T_950; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_653 = _out_rifireMux_T_950; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_654 = _out_rifireMux_T_950; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_655 = _out_rifireMux_T_950; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_656 = _out_rifireMux_T_950; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_951 = ~_out_T_1768; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_953 = _out_rifireMux_T_260 & out_frontSel_173; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_954 = _out_rifireMux_T_953 & _out_T_1718; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_459 = _out_rifireMux_T_954; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_460 = _out_rifireMux_T_954; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_461 = _out_rifireMux_T_954; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_462 = _out_rifireMux_T_954; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_463 = _out_rifireMux_T_954; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_464 = _out_rifireMux_T_954; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_465 = _out_rifireMux_T_954; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_466 = _out_rifireMux_T_954; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_955 = ~_out_T_1718; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_957 = _out_rifireMux_T_260 & out_frontSel_174; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_958 = _out_rifireMux_T_957 & _out_T_1620; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_80 = _out_rifireMux_T_958; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_81 = _out_rifireMux_T_958; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_82 = _out_rifireMux_T_958; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_83 = _out_rifireMux_T_958; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_84 = _out_rifireMux_T_958; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_85 = _out_rifireMux_T_958; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_86 = _out_rifireMux_T_958; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_87 = _out_rifireMux_T_958; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_959 = ~_out_T_1620; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_961 = _out_rifireMux_T_260 & out_frontSel_175; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_962 = _out_rifireMux_T_961 & _out_T_1832; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_899 = _out_rifireMux_T_962; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_900 = _out_rifireMux_T_962; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_901 = _out_rifireMux_T_962; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_902 = _out_rifireMux_T_962; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_903 = _out_rifireMux_T_962; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_904 = _out_rifireMux_T_962; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_905 = _out_rifireMux_T_962; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_906 = _out_rifireMux_T_962; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_963 = ~_out_T_1832; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_965 = _out_rifireMux_T_260 & out_frontSel_176; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_966 = _out_rifireMux_T_965 & _out_T_1750; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_577 = _out_rifireMux_T_966; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_578 = _out_rifireMux_T_966; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_579 = _out_rifireMux_T_966; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_580 = _out_rifireMux_T_966; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_581 = _out_rifireMux_T_966; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_582 = _out_rifireMux_T_966; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_583 = _out_rifireMux_T_966; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_584 = _out_rifireMux_T_966; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_967 = ~_out_T_1750; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_969 = _out_rifireMux_T_260 & out_frontSel_177; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_970 = _out_rifireMux_T_969 & _out_T_1826; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_875 = _out_rifireMux_T_970; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_876 = _out_rifireMux_T_970; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_877 = _out_rifireMux_T_970; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_878 = _out_rifireMux_T_970; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_879 = _out_rifireMux_T_970; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_880 = _out_rifireMux_T_970; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_881 = _out_rifireMux_T_970; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_882 = _out_rifireMux_T_970; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_971 = ~_out_T_1826; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_973 = _out_rifireMux_T_260 & out_frontSel_178; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_974 = _out_rifireMux_T_973 & _out_T_1892; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1139 = _out_rifireMux_T_974; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1140 = _out_rifireMux_T_974; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1141 = _out_rifireMux_T_974; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1142 = _out_rifireMux_T_974; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1143 = _out_rifireMux_T_974; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1144 = _out_rifireMux_T_974; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1145 = _out_rifireMux_T_974; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1146 = _out_rifireMux_T_974; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_975 = ~_out_T_1892; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_977 = _out_rifireMux_T_260 & out_frontSel_179; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_978 = _out_rifireMux_T_977 & _out_T_1646; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_184 = _out_rifireMux_T_978; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_185 = _out_rifireMux_T_978; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_186 = _out_rifireMux_T_978; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_187 = _out_rifireMux_T_978; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_188 = _out_rifireMux_T_978; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_189 = _out_rifireMux_T_978; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_190 = _out_rifireMux_T_978; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_191 = _out_rifireMux_T_978; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_979 = ~_out_T_1646; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_981 = _out_rifireMux_T_260 & out_frontSel_180; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_982 = _out_rifireMux_T_981 & _out_T_1746; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_561 = _out_rifireMux_T_982; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_562 = _out_rifireMux_T_982; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_563 = _out_rifireMux_T_982; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_564 = _out_rifireMux_T_982; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_565 = _out_rifireMux_T_982; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_566 = _out_rifireMux_T_982; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_567 = _out_rifireMux_T_982; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_568 = _out_rifireMux_T_982; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_983 = ~_out_T_1746; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_985 = _out_rifireMux_T_260 & out_frontSel_181; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_986 = _out_rifireMux_T_985 & _out_T_1762; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_625 = _out_rifireMux_T_986; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_626 = _out_rifireMux_T_986; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_627 = _out_rifireMux_T_986; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_628 = _out_rifireMux_T_986; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_629 = _out_rifireMux_T_986; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_630 = _out_rifireMux_T_986; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_631 = _out_rifireMux_T_986; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_632 = _out_rifireMux_T_986; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_987 = ~_out_T_1762; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_989 = _out_rifireMux_T_260 & out_frontSel_182; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_990 = _out_rifireMux_T_989 & _out_T_1828; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_883 = _out_rifireMux_T_990; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_884 = _out_rifireMux_T_990; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_885 = _out_rifireMux_T_990; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_886 = _out_rifireMux_T_990; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_887 = _out_rifireMux_T_990; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_888 = _out_rifireMux_T_990; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_889 = _out_rifireMux_T_990; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_890 = _out_rifireMux_T_990; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_991 = ~_out_T_1828; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_993 = _out_rifireMux_T_260 & out_frontSel_183; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_994 = _out_rifireMux_T_993 & _out_T_1872; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1059 = _out_rifireMux_T_994; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1060 = _out_rifireMux_T_994; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1061 = _out_rifireMux_T_994; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1062 = _out_rifireMux_T_994; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1063 = _out_rifireMux_T_994; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1064 = _out_rifireMux_T_994; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1065 = _out_rifireMux_T_994; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1066 = _out_rifireMux_T_994; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_995 = ~_out_T_1872; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_997 = _out_rifireMux_T_260 & out_frontSel_184; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_998 = _out_rifireMux_T_997 & _out_T_1626; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_104 = _out_rifireMux_T_998; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_105 = _out_rifireMux_T_998; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_106 = _out_rifireMux_T_998; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_107 = _out_rifireMux_T_998; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_108 = _out_rifireMux_T_998; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_109 = _out_rifireMux_T_998; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_110 = _out_rifireMux_T_998; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_111 = _out_rifireMux_T_998; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_999 = ~_out_T_1626; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1001 = _out_rifireMux_T_260 & out_frontSel_185; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_1002 = _out_rifireMux_T_1001 & _out_T_1622; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_88 = _out_rifireMux_T_1002; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_89 = _out_rifireMux_T_1002; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_90 = _out_rifireMux_T_1002; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_91 = _out_rifireMux_T_1002; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_92 = _out_rifireMux_T_1002; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_93 = _out_rifireMux_T_1002; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_94 = _out_rifireMux_T_1002; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_95 = _out_rifireMux_T_1002; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1003 = ~_out_T_1622; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1005 = _out_rifireMux_T_260 & out_frontSel_186; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_1006 = _out_rifireMux_T_1005 & _out_T_1850; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_971 = _out_rifireMux_T_1006; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_972 = _out_rifireMux_T_1006; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_973 = _out_rifireMux_T_1006; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_974 = _out_rifireMux_T_1006; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_975 = _out_rifireMux_T_1006; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_976 = _out_rifireMux_T_1006; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_977 = _out_rifireMux_T_1006; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_978 = _out_rifireMux_T_1006; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1007 = ~_out_T_1850; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1009 = _out_rifireMux_T_260 & out_frontSel_187; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_1010 = _out_rifireMux_T_1009 & _out_T_1766; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_641 = _out_rifireMux_T_1010; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_642 = _out_rifireMux_T_1010; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_643 = _out_rifireMux_T_1010; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_644 = _out_rifireMux_T_1010; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_645 = _out_rifireMux_T_1010; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_646 = _out_rifireMux_T_1010; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_647 = _out_rifireMux_T_1010; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_648 = _out_rifireMux_T_1010; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1011 = ~_out_T_1766; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1013 = _out_rifireMux_T_260 & out_frontSel_188; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_1014 = _out_rifireMux_T_1013 & _out_T_1700; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_394 = _out_rifireMux_T_1014; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_395 = _out_rifireMux_T_1014; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_396 = _out_rifireMux_T_1014; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_397 = _out_rifireMux_T_1014; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_398 = _out_rifireMux_T_1014; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_399 = _out_rifireMux_T_1014; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_400 = _out_rifireMux_T_1014; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_401 = _out_rifireMux_T_1014; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1015 = ~_out_T_1700; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1017 = _out_rifireMux_T_260 & out_frontSel_189; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_1018 = _out_rifireMux_T_1017 & _out_T_1634; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_136 = _out_rifireMux_T_1018; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_137 = _out_rifireMux_T_1018; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_138 = _out_rifireMux_T_1018; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_139 = _out_rifireMux_T_1018; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_140 = _out_rifireMux_T_1018; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_141 = _out_rifireMux_T_1018; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_142 = _out_rifireMux_T_1018; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_143 = _out_rifireMux_T_1018; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1019 = ~_out_T_1634; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1021 = _out_rifireMux_T_260 & out_frontSel_190; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_1022 = _out_rifireMux_T_1021 & _out_T_1870; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1051 = _out_rifireMux_T_1022; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1052 = _out_rifireMux_T_1022; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1053 = _out_rifireMux_T_1022; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1054 = _out_rifireMux_T_1022; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1055 = _out_rifireMux_T_1022; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1056 = _out_rifireMux_T_1022; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1057 = _out_rifireMux_T_1022; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1058 = _out_rifireMux_T_1022; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1023 = ~_out_T_1870; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1025 = _out_rifireMux_T_260 & out_frontSel_191; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_1026 = _out_rifireMux_T_1025 & _out_T_1752; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_585 = _out_rifireMux_T_1026; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_586 = _out_rifireMux_T_1026; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_587 = _out_rifireMux_T_1026; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_588 = _out_rifireMux_T_1026; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_589 = _out_rifireMux_T_1026; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_590 = _out_rifireMux_T_1026; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_591 = _out_rifireMux_T_1026; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_592 = _out_rifireMux_T_1026; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1027 = ~_out_T_1752; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1029 = _out_rifireMux_T_260 & out_frontSel_192; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_1030 = _out_rifireMux_T_1029 & _out_T_1682; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_328 = _out_rifireMux_T_1030; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_329 = _out_rifireMux_T_1030; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_330 = _out_rifireMux_T_1030; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_331 = _out_rifireMux_T_1030; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_332 = _out_rifireMux_T_1030; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_333 = _out_rifireMux_T_1030; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_334 = _out_rifireMux_T_1030; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_335 = _out_rifireMux_T_1030; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1031 = ~_out_T_1682; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1033 = _out_rifireMux_T_260 & out_frontSel_193; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_1034 = _out_rifireMux_T_1033 & _out_T_1708; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_426 = _out_rifireMux_T_1034; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_427 = _out_rifireMux_T_1034; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_428 = _out_rifireMux_T_1034; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_429 = _out_rifireMux_T_1034; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_430 = _out_rifireMux_T_1034; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_431 = _out_rifireMux_T_1034; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_432 = _out_rifireMux_T_1034; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_433 = _out_rifireMux_T_1034; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1035 = ~_out_T_1708; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1037 = _out_rifireMux_T_260 & out_frontSel_194; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_1038 = _out_rifireMux_T_1037 & _out_T_1816; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_835 = _out_rifireMux_T_1038; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_836 = _out_rifireMux_T_1038; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_837 = _out_rifireMux_T_1038; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_838 = _out_rifireMux_T_1038; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_839 = _out_rifireMux_T_1038; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_840 = _out_rifireMux_T_1038; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_841 = _out_rifireMux_T_1038; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_842 = _out_rifireMux_T_1038; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1039 = ~_out_T_1816; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1041 = _out_rifireMux_T_260 & out_frontSel_195; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_1042 = _out_rifireMux_T_1041 & _out_T_1884; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1107 = _out_rifireMux_T_1042; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1108 = _out_rifireMux_T_1042; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1109 = _out_rifireMux_T_1042; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1110 = _out_rifireMux_T_1042; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1111 = _out_rifireMux_T_1042; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1112 = _out_rifireMux_T_1042; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1113 = _out_rifireMux_T_1042; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1114 = _out_rifireMux_T_1042; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1043 = ~_out_T_1884; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1045 = _out_rifireMux_T_260 & out_frontSel_196; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_1046 = _out_rifireMux_T_1045 & _out_T_1630; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_120 = _out_rifireMux_T_1046; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_121 = _out_rifireMux_T_1046; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_122 = _out_rifireMux_T_1046; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_123 = _out_rifireMux_T_1046; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_124 = _out_rifireMux_T_1046; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_125 = _out_rifireMux_T_1046; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_126 = _out_rifireMux_T_1046; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_127 = _out_rifireMux_T_1046; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1047 = ~_out_T_1630; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1049 = _out_rifireMux_T_260 & out_frontSel_197; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_1050 = _out_rifireMux_T_1049 & _out_T_1694; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_370 = _out_rifireMux_T_1050; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_371 = _out_rifireMux_T_1050; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_372 = _out_rifireMux_T_1050; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_373 = _out_rifireMux_T_1050; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_374 = _out_rifireMux_T_1050; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_375 = _out_rifireMux_T_1050; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_376 = _out_rifireMux_T_1050; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_377 = _out_rifireMux_T_1050; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1051 = ~_out_T_1694; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1053 = _out_rifireMux_T_260 & out_frontSel_198; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_1054 = _out_rifireMux_T_1053 & _out_T_1788; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_723 = _out_rifireMux_T_1054; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_724 = _out_rifireMux_T_1054; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_725 = _out_rifireMux_T_1054; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_726 = _out_rifireMux_T_1054; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_727 = _out_rifireMux_T_1054; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_728 = _out_rifireMux_T_1054; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_729 = _out_rifireMux_T_1054; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_730 = _out_rifireMux_T_1054; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1055 = ~_out_T_1788; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1057 = _out_rifireMux_T_260 & out_frontSel_199; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_1058 = _out_rifireMux_T_1057 & _out_T_1824; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_867 = _out_rifireMux_T_1058; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_868 = _out_rifireMux_T_1058; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_869 = _out_rifireMux_T_1058; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_870 = _out_rifireMux_T_1058; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_871 = _out_rifireMux_T_1058; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_872 = _out_rifireMux_T_1058; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_873 = _out_rifireMux_T_1058; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_874 = _out_rifireMux_T_1058; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1059 = ~_out_T_1824; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1061 = _out_rifireMux_T_260 & out_frontSel_200; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_1062 = _out_rifireMux_T_1061 & _out_T_1896; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1155 = _out_rifireMux_T_1062; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1156 = _out_rifireMux_T_1062; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1157 = _out_rifireMux_T_1062; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1158 = _out_rifireMux_T_1062; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1159 = _out_rifireMux_T_1062; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1160 = _out_rifireMux_T_1062; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1161 = _out_rifireMux_T_1062; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1162 = _out_rifireMux_T_1062; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1063 = ~_out_T_1896; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1065 = _out_rifireMux_T_260 & out_frontSel_201; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_1066 = _out_rifireMux_T_1065 & _out_T_1674; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_296 = _out_rifireMux_T_1066; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_297 = _out_rifireMux_T_1066; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_298 = _out_rifireMux_T_1066; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_299 = _out_rifireMux_T_1066; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_300 = _out_rifireMux_T_1066; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_301 = _out_rifireMux_T_1066; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_302 = _out_rifireMux_T_1066; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_303 = _out_rifireMux_T_1066; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1067 = ~_out_T_1674; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1069 = _out_rifireMux_T_260 & out_frontSel_202; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_1070 = _out_rifireMux_T_1069 & _out_T_1614; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_56 = _out_rifireMux_T_1070; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_57 = _out_rifireMux_T_1070; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_58 = _out_rifireMux_T_1070; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_59 = _out_rifireMux_T_1070; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_60 = _out_rifireMux_T_1070; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_61 = _out_rifireMux_T_1070; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_62 = _out_rifireMux_T_1070; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_63 = _out_rifireMux_T_1070; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1071 = ~_out_T_1614; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1073 = _out_rifireMux_T_260 & out_frontSel_203; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_1074 = _out_rifireMux_T_1073 & _out_T_1836; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_915 = _out_rifireMux_T_1074; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_916 = _out_rifireMux_T_1074; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_917 = _out_rifireMux_T_1074; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_918 = _out_rifireMux_T_1074; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_919 = _out_rifireMux_T_1074; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_920 = _out_rifireMux_T_1074; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_921 = _out_rifireMux_T_1074; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_922 = _out_rifireMux_T_1074; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1075 = ~_out_T_1836; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1077 = _out_rifireMux_T_260 & out_frontSel_204; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_1078 = _out_rifireMux_T_1077 & _out_T_1754; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_593 = _out_rifireMux_T_1078; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_594 = _out_rifireMux_T_1078; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_595 = _out_rifireMux_T_1078; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_596 = _out_rifireMux_T_1078; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_597 = _out_rifireMux_T_1078; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_598 = _out_rifireMux_T_1078; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_599 = _out_rifireMux_T_1078; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_600 = _out_rifireMux_T_1078; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1079 = ~_out_T_1754; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1081 = _out_rifireMux_T_260 & out_frontSel_205; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_1082 = _out_rifireMux_T_1081 & _out_T_1726; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_487 = _out_rifireMux_T_1082; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_488 = _out_rifireMux_T_1082; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_489 = _out_rifireMux_T_1082; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_490 = _out_rifireMux_T_1082; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_491 = _out_rifireMux_T_1082; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_492 = _out_rifireMux_T_1082; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_493 = _out_rifireMux_T_1082; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_494 = _out_rifireMux_T_1082; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1083 = ~_out_T_1726; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1085 = _out_rifireMux_T_260 & out_frontSel_206; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_1086 = _out_rifireMux_T_1085 & _out_T_1668; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_272 = _out_rifireMux_T_1086; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_273 = _out_rifireMux_T_1086; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_274 = _out_rifireMux_T_1086; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_275 = _out_rifireMux_T_1086; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_276 = _out_rifireMux_T_1086; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_277 = _out_rifireMux_T_1086; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_278 = _out_rifireMux_T_1086; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_279 = _out_rifireMux_T_1086; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1087 = ~_out_T_1668; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1089 = _out_rifireMux_T_260 & out_frontSel_207; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_1090 = _out_rifireMux_T_1089 & _out_T_1858; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1003 = _out_rifireMux_T_1090; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1004 = _out_rifireMux_T_1090; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1005 = _out_rifireMux_T_1090; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1006 = _out_rifireMux_T_1090; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1007 = _out_rifireMux_T_1090; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1008 = _out_rifireMux_T_1090; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1009 = _out_rifireMux_T_1090; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1010 = _out_rifireMux_T_1090; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1091 = ~_out_T_1858; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1093 = _out_rifireMux_T_260 & out_frontSel_208; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_1094 = _out_rifireMux_T_1093 & _out_T_1778; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_689 = _out_rifireMux_T_1094; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_690 = _out_rifireMux_T_1094; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_691 = _out_rifireMux_T_1094; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_692 = _out_rifireMux_T_1094; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_693 = _out_rifireMux_T_1094; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_694 = _out_rifireMux_T_1094; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_695 = _out_rifireMux_T_1094; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_696 = _out_rifireMux_T_1094; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1095 = ~_out_T_1778; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1097 = _out_rifireMux_T_260 & out_frontSel_209; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_1098 = _out_rifireMux_T_1097 & _out_T_1812; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_819 = _out_rifireMux_T_1098; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_820 = _out_rifireMux_T_1098; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_821 = _out_rifireMux_T_1098; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_822 = _out_rifireMux_T_1098; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_823 = _out_rifireMux_T_1098; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_824 = _out_rifireMux_T_1098; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_825 = _out_rifireMux_T_1098; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_826 = _out_rifireMux_T_1098; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1099 = ~_out_T_1812; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1101 = _out_rifireMux_T_260 & out_frontSel_210; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_1102 = _out_rifireMux_T_1101 & _out_T_1878; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1083 = _out_rifireMux_T_1102; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1084 = _out_rifireMux_T_1102; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1085 = _out_rifireMux_T_1102; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1086 = _out_rifireMux_T_1102; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1087 = _out_rifireMux_T_1102; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1088 = _out_rifireMux_T_1102; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1089 = _out_rifireMux_T_1102; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1090 = _out_rifireMux_T_1102; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1103 = ~_out_T_1878; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1105 = _out_rifireMux_T_260 & out_frontSel_211; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_1106 = _out_rifireMux_T_1105 & _out_T_1652; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_208 = _out_rifireMux_T_1106; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_209 = _out_rifireMux_T_1106; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_210 = _out_rifireMux_T_1106; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_211 = _out_rifireMux_T_1106; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_212 = _out_rifireMux_T_1106; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_213 = _out_rifireMux_T_1106; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_214 = _out_rifireMux_T_1106; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_215 = _out_rifireMux_T_1106; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1107 = ~_out_T_1652; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1109 = _out_rifireMux_T_260 & out_frontSel_212; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_1110 = _out_rifireMux_T_1109 & _out_T_1710; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_434 = _out_rifireMux_T_1110; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_435 = _out_rifireMux_T_1110; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_436 = _out_rifireMux_T_1110; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_437 = _out_rifireMux_T_1110; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_438 = _out_rifireMux_T_1110; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_439 = _out_rifireMux_T_1110; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_440 = _out_rifireMux_T_1110; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_441 = _out_rifireMux_T_1110; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1111 = ~_out_T_1710; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1113 = _out_rifireMux_T_260 & out_frontSel_213; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_1114 = _out_rifireMux_T_1113 & _out_T_1784; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_707 = _out_rifireMux_T_1114; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_708 = _out_rifireMux_T_1114; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_709 = _out_rifireMux_T_1114; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_710 = _out_rifireMux_T_1114; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_711 = _out_rifireMux_T_1114; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_712 = _out_rifireMux_T_1114; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_713 = _out_rifireMux_T_1114; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_714 = _out_rifireMux_T_1114; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1115 = ~_out_T_1784; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1117 = _out_rifireMux_T_260 & out_frontSel_214; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_1118 = _out_rifireMux_T_1117 & _out_T_1860; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1011 = _out_rifireMux_T_1118; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1012 = _out_rifireMux_T_1118; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1013 = _out_rifireMux_T_1118; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1014 = _out_rifireMux_T_1118; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1015 = _out_rifireMux_T_1118; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1016 = _out_rifireMux_T_1118; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1017 = _out_rifireMux_T_1118; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1018 = _out_rifireMux_T_1118; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1119 = ~_out_T_1860; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1121 = _out_rifireMux_T_260 & out_frontSel_215; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_1122 = _out_rifireMux_T_1121 & _out_T_1900; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1171 = _out_rifireMux_T_1122; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1172 = _out_rifireMux_T_1122; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1173 = _out_rifireMux_T_1122; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1174 = _out_rifireMux_T_1122; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1175 = _out_rifireMux_T_1122; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1176 = _out_rifireMux_T_1122; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1177 = _out_rifireMux_T_1122; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1178 = _out_rifireMux_T_1122; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1123 = ~_out_T_1900; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1125 = _out_rifireMux_T_260 & out_frontSel_216; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_1126 = _out_rifireMux_T_1125 & _out_T_1642; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_168 = _out_rifireMux_T_1126; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_169 = _out_rifireMux_T_1126; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_170 = _out_rifireMux_T_1126; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_171 = _out_rifireMux_T_1126; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_172 = _out_rifireMux_T_1126; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_173 = _out_rifireMux_T_1126; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_174 = _out_rifireMux_T_1126; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_175 = _out_rifireMux_T_1126; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1127 = ~_out_T_1642; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1129 = _out_rifireMux_T_260 & out_frontSel_217; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_1130 = _out_rifireMux_T_1129 & _out_T_1610; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_40 = _out_rifireMux_T_1130; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_41 = _out_rifireMux_T_1130; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_42 = _out_rifireMux_T_1130; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_43 = _out_rifireMux_T_1130; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_44 = _out_rifireMux_T_1130; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_45 = _out_rifireMux_T_1130; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_46 = _out_rifireMux_T_1130; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_47 = _out_rifireMux_T_1130; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1131 = ~_out_T_1610; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1133 = _out_rifireMux_T_260 & out_frontSel_218; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_1134 = _out_rifireMux_T_1133 & _out_T_1838; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_923 = _out_rifireMux_T_1134; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_924 = _out_rifireMux_T_1134; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_925 = _out_rifireMux_T_1134; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_926 = _out_rifireMux_T_1134; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_927 = _out_rifireMux_T_1134; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_928 = _out_rifireMux_T_1134; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_929 = _out_rifireMux_T_1134; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_930 = _out_rifireMux_T_1134; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1135 = ~_out_T_1838; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1137 = _out_rifireMux_T_260 & out_frontSel_219; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_1138 = _out_rifireMux_T_1137 & _out_T_1772; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_665 = _out_rifireMux_T_1138; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_666 = _out_rifireMux_T_1138; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_667 = _out_rifireMux_T_1138; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_668 = _out_rifireMux_T_1138; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_669 = _out_rifireMux_T_1138; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_670 = _out_rifireMux_T_1138; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_671 = _out_rifireMux_T_1138; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_672 = _out_rifireMux_T_1138; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1139 = ~_out_T_1772; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1141 = _out_rifireMux_T_260 & out_frontSel_220; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_1142 = _out_rifireMux_T_1141 & _out_T_1676; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_304 = _out_rifireMux_T_1142; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_305 = _out_rifireMux_T_1142; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_306 = _out_rifireMux_T_1142; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_307 = _out_rifireMux_T_1142; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_308 = _out_rifireMux_T_1142; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_309 = _out_rifireMux_T_1142; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_310 = _out_rifireMux_T_1142; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_311 = _out_rifireMux_T_1142; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1143 = ~_out_T_1676; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1145 = _out_rifireMux_T_260 & out_frontSel_221; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_1146 = _out_rifireMux_T_1145 & _out_T_1658; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_232 = _out_rifireMux_T_1146; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_233 = _out_rifireMux_T_1146; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_234 = _out_rifireMux_T_1146; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_235 = _out_rifireMux_T_1146; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_236 = _out_rifireMux_T_1146; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_237 = _out_rifireMux_T_1146; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_238 = _out_rifireMux_T_1146; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_239 = _out_rifireMux_T_1146; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1147 = ~_out_T_1658; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1149 = _out_rifireMux_T_260 & out_frontSel_222; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_1150 = _out_rifireMux_T_1149 & _out_T_1902; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1179 = _out_rifireMux_T_1150; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1180 = _out_rifireMux_T_1150; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1181 = _out_rifireMux_T_1150; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1182 = _out_rifireMux_T_1150; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1183 = _out_rifireMux_T_1150; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1184 = _out_rifireMux_T_1150; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1185 = _out_rifireMux_T_1150; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1186 = _out_rifireMux_T_1150; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1151 = ~_out_T_1902; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1153 = _out_rifireMux_T_260 & out_frontSel_223; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_1154 = _out_rifireMux_T_1153 & _out_T_1798; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_763 = _out_rifireMux_T_1154; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_764 = _out_rifireMux_T_1154; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_765 = _out_rifireMux_T_1154; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_766 = _out_rifireMux_T_1154; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_767 = _out_rifireMux_T_1154; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_768 = _out_rifireMux_T_1154; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_769 = _out_rifireMux_T_1154; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_770 = _out_rifireMux_T_1154; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1155 = ~_out_T_1798; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1157 = _out_rifireMux_T_260 & out_frontSel_224; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_1158 = _out_rifireMux_T_1157 & _out_T_1696; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_378 = _out_rifireMux_T_1158; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_379 = _out_rifireMux_T_1158; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_380 = _out_rifireMux_T_1158; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_381 = _out_rifireMux_T_1158; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_382 = _out_rifireMux_T_1158; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_383 = _out_rifireMux_T_1158; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_384 = _out_rifireMux_T_1158; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_385 = _out_rifireMux_T_1158; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1159 = ~_out_T_1696; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1161 = _out_rifireMux_T_260 & out_frontSel_225; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_1162 = _out_rifireMux_T_1161 & _out_T_1706; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_418 = _out_rifireMux_T_1162; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_419 = _out_rifireMux_T_1162; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_420 = _out_rifireMux_T_1162; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_421 = _out_rifireMux_T_1162; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_422 = _out_rifireMux_T_1162; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_423 = _out_rifireMux_T_1162; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_424 = _out_rifireMux_T_1162; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_425 = _out_rifireMux_T_1162; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1163 = ~_out_T_1706; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1165 = _out_rifireMux_T_260 & out_frontSel_226; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_1166 = _out_rifireMux_T_1165 & _out_T_1802; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_779 = _out_rifireMux_T_1166; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_780 = _out_rifireMux_T_1166; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_781 = _out_rifireMux_T_1166; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_782 = _out_rifireMux_T_1166; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_783 = _out_rifireMux_T_1166; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_784 = _out_rifireMux_T_1166; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_785 = _out_rifireMux_T_1166; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_786 = _out_rifireMux_T_1166; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1167 = ~_out_T_1802; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1169 = _out_rifireMux_T_260 & out_frontSel_227; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_1170 = _out_rifireMux_T_1169 & _out_T_1908; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1203 = _out_rifireMux_T_1170; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1204 = _out_rifireMux_T_1170; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1205 = _out_rifireMux_T_1170; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1206 = _out_rifireMux_T_1170; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1207 = _out_rifireMux_T_1170; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1208 = _out_rifireMux_T_1170; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1209 = _out_rifireMux_T_1170; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1210 = _out_rifireMux_T_1170; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1171 = ~_out_T_1908; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1173 = _out_rifireMux_T_260 & out_frontSel_228; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_1174 = _out_rifireMux_T_1173 & _out_T_1638; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_152 = _out_rifireMux_T_1174; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_153 = _out_rifireMux_T_1174; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_154 = _out_rifireMux_T_1174; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_155 = _out_rifireMux_T_1174; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_156 = _out_rifireMux_T_1174; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_157 = _out_rifireMux_T_1174; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_158 = _out_rifireMux_T_1174; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_159 = _out_rifireMux_T_1174; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1175 = ~_out_T_1638; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1177 = _out_rifireMux_T_260 & out_frontSel_229; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_1178 = _out_rifireMux_T_1177 & _out_T_1690; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_354 = _out_rifireMux_T_1178; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_355 = _out_rifireMux_T_1178; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_356 = _out_rifireMux_T_1178; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_357 = _out_rifireMux_T_1178; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_358 = _out_rifireMux_T_1178; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_359 = _out_rifireMux_T_1178; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_360 = _out_rifireMux_T_1178; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_361 = _out_rifireMux_T_1178; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1179 = ~_out_T_1690; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1181 = _out_rifireMux_T_260 & out_frontSel_230; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_1182 = _out_rifireMux_T_1181 & _out_T_1774; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_673 = _out_rifireMux_T_1182; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_674 = _out_rifireMux_T_1182; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_675 = _out_rifireMux_T_1182; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_676 = _out_rifireMux_T_1182; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_677 = _out_rifireMux_T_1182; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_678 = _out_rifireMux_T_1182; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_679 = _out_rifireMux_T_1182; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_680 = _out_rifireMux_T_1182; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1183 = ~_out_T_1774; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1185 = _out_rifireMux_T_260 & out_frontSel_231; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_1186 = _out_rifireMux_T_1185 & _out_T_1844; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_947 = _out_rifireMux_T_1186; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_948 = _out_rifireMux_T_1186; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_949 = _out_rifireMux_T_1186; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_950 = _out_rifireMux_T_1186; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_951 = _out_rifireMux_T_1186; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_952 = _out_rifireMux_T_1186; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_953 = _out_rifireMux_T_1186; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_954 = _out_rifireMux_T_1186; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1187 = ~_out_T_1844; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1189 = _out_rifireMux_T_260 & out_frontSel_232; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_1190 = _out_rifireMux_T_1189 & _out_T_1904; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1187 = _out_rifireMux_T_1190; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1188 = _out_rifireMux_T_1190; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1189 = _out_rifireMux_T_1190; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1190 = _out_rifireMux_T_1190; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1191 = _out_rifireMux_T_1190; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1192 = _out_rifireMux_T_1190; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1193 = _out_rifireMux_T_1190; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1194 = _out_rifireMux_T_1190; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1191 = ~_out_T_1904; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1193 = _out_rifireMux_T_260 & out_frontSel_233; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_1194 = _out_rifireMux_T_1193 & _out_T_1670; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_280 = _out_rifireMux_T_1194; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_281 = _out_rifireMux_T_1194; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_282 = _out_rifireMux_T_1194; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_283 = _out_rifireMux_T_1194; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_284 = _out_rifireMux_T_1194; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_285 = _out_rifireMux_T_1194; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_286 = _out_rifireMux_T_1194; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_287 = _out_rifireMux_T_1194; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1195 = ~_out_T_1670; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1197 = _out_rifireMux_T_260 & out_frontSel_234; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_1198 = _out_rifireMux_T_1197 & _out_T_1604; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_16 = _out_rifireMux_T_1198; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_17 = _out_rifireMux_T_1198; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_18 = _out_rifireMux_T_1198; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_19 = _out_rifireMux_T_1198; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_20 = _out_rifireMux_T_1198; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_21 = _out_rifireMux_T_1198; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_22 = _out_rifireMux_T_1198; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_23 = _out_rifireMux_T_1198; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1199 = ~_out_T_1604; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1201 = _out_rifireMux_T_260 & out_frontSel_235; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_1202 = _out_rifireMux_T_1201 & _out_T_1862; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1019 = _out_rifireMux_T_1202; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1020 = _out_rifireMux_T_1202; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1021 = _out_rifireMux_T_1202; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1022 = _out_rifireMux_T_1202; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1023 = _out_rifireMux_T_1202; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1024 = _out_rifireMux_T_1202; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1025 = _out_rifireMux_T_1202; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1026 = _out_rifireMux_T_1202; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1203 = ~_out_T_1862; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1205 = _out_rifireMux_T_260 & out_frontSel_236; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_1206 = _out_rifireMux_T_1205 & _out_T_1760; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_617 = _out_rifireMux_T_1206; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_618 = _out_rifireMux_T_1206; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_619 = _out_rifireMux_T_1206; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_620 = _out_rifireMux_T_1206; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_621 = _out_rifireMux_T_1206; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_622 = _out_rifireMux_T_1206; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_623 = _out_rifireMux_T_1206; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_624 = _out_rifireMux_T_1206; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1207 = ~_out_T_1760; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1209 = _out_rifireMux_T_260 & out_frontSel_237; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_1210 = _out_rifireMux_T_1209 & _out_T_1730; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_503 = _out_rifireMux_T_1210; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_504 = _out_rifireMux_T_1210; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_505 = _out_rifireMux_T_1210; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_506 = _out_rifireMux_T_1210; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_507 = _out_rifireMux_T_1210; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_508 = _out_rifireMux_T_1210; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_509 = _out_rifireMux_T_1210; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_510 = _out_rifireMux_T_1210; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1211 = ~_out_T_1730; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1213 = _out_rifireMux_T_260 & out_frontSel_238; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_1214 = _out_rifireMux_T_1213 & _out_T_1650; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_200 = _out_rifireMux_T_1214; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_201 = _out_rifireMux_T_1214; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_202 = _out_rifireMux_T_1214; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_203 = _out_rifireMux_T_1214; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_204 = _out_rifireMux_T_1214; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_205 = _out_rifireMux_T_1214; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_206 = _out_rifireMux_T_1214; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_207 = _out_rifireMux_T_1214; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1215 = ~_out_T_1650; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1217 = _out_rifireMux_T_260 & out_frontSel_239; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_1218 = _out_rifireMux_T_1217 & _out_T_1886; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1115 = _out_rifireMux_T_1218; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1116 = _out_rifireMux_T_1218; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1117 = _out_rifireMux_T_1218; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1118 = _out_rifireMux_T_1218; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1119 = _out_rifireMux_T_1218; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1120 = _out_rifireMux_T_1218; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1121 = _out_rifireMux_T_1218; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1122 = _out_rifireMux_T_1218; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1219 = ~_out_T_1886; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1221 = _out_rifireMux_T_260 & out_frontSel_240; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_1222 = _out_rifireMux_T_1221 & _out_T_1792; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_739 = _out_rifireMux_T_1222; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_740 = _out_rifireMux_T_1222; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_741 = _out_rifireMux_T_1222; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_742 = _out_rifireMux_T_1222; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_743 = _out_rifireMux_T_1222; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_744 = _out_rifireMux_T_1222; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_745 = _out_rifireMux_T_1222; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_746 = _out_rifireMux_T_1222; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1223 = ~_out_T_1792; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1225 = _out_rifireMux_T_260 & out_frontSel_241; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_1226 = _out_rifireMux_T_1225 & _out_T_1804; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_787 = _out_rifireMux_T_1226; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_788 = _out_rifireMux_T_1226; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_789 = _out_rifireMux_T_1226; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_790 = _out_rifireMux_T_1226; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_791 = _out_rifireMux_T_1226; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_792 = _out_rifireMux_T_1226; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_793 = _out_rifireMux_T_1226; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_794 = _out_rifireMux_T_1226; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1227 = ~_out_T_1804; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1229 = _out_rifireMux_T_260 & out_frontSel_242; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_1230 = _out_rifireMux_T_1229 & _out_T_1888; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1123 = _out_rifireMux_T_1230; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1124 = _out_rifireMux_T_1230; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1125 = _out_rifireMux_T_1230; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1126 = _out_rifireMux_T_1230; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1127 = _out_rifireMux_T_1230; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1128 = _out_rifireMux_T_1230; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1129 = _out_rifireMux_T_1230; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1130 = _out_rifireMux_T_1230; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1231 = ~_out_T_1888; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1233 = _out_rifireMux_T_260 & out_frontSel_243; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_1234 = _out_rifireMux_T_1233 & _out_T_1664; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_256 = _out_rifireMux_T_1234; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_257 = _out_rifireMux_T_1234; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_258 = _out_rifireMux_T_1234; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_259 = _out_rifireMux_T_1234; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_260 = _out_rifireMux_T_1234; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_261 = _out_rifireMux_T_1234; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_262 = _out_rifireMux_T_1234; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_263 = _out_rifireMux_T_1234; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1235 = ~_out_T_1664; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1237 = _out_rifireMux_T_260 & out_frontSel_244; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_1238 = _out_rifireMux_T_1237 & _out_T_1734; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_519 = _out_rifireMux_T_1238; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_520 = _out_rifireMux_T_1238; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_521 = _out_rifireMux_T_1238; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_522 = _out_rifireMux_T_1238; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_523 = _out_rifireMux_T_1238; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_524 = _out_rifireMux_T_1238; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_525 = _out_rifireMux_T_1238; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_526 = _out_rifireMux_T_1238; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1239 = ~_out_T_1734; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1241 = _out_rifireMux_T_260 & out_frontSel_245; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_1242 = _out_rifireMux_T_1241 & _out_T_1776; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_681 = _out_rifireMux_T_1242; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_682 = _out_rifireMux_T_1242; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_683 = _out_rifireMux_T_1242; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_684 = _out_rifireMux_T_1242; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_685 = _out_rifireMux_T_1242; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_686 = _out_rifireMux_T_1242; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_687 = _out_rifireMux_T_1242; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_688 = _out_rifireMux_T_1242; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1243 = ~_out_T_1776; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1245 = _out_rifireMux_T_260 & out_frontSel_246; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_1246 = _out_rifireMux_T_1245 & _out_T_1864; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1027 = _out_rifireMux_T_1246; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1028 = _out_rifireMux_T_1246; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1029 = _out_rifireMux_T_1246; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1030 = _out_rifireMux_T_1246; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1031 = _out_rifireMux_T_1246; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1032 = _out_rifireMux_T_1246; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1033 = _out_rifireMux_T_1246; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1034 = _out_rifireMux_T_1246; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1247 = ~_out_T_1864; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1249 = _out_rifireMux_T_260 & out_frontSel_247; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_1250 = _out_rifireMux_T_1249 & _out_T_1612; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_48 = _out_rifireMux_T_1250; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_49 = _out_rifireMux_T_1250; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_50 = _out_rifireMux_T_1250; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_51 = _out_rifireMux_T_1250; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_52 = _out_rifireMux_T_1250; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_53 = _out_rifireMux_T_1250; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_54 = _out_rifireMux_T_1250; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_55 = _out_rifireMux_T_1250; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1251 = ~_out_T_1612; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1253 = _out_rifireMux_T_260 & out_frontSel_248; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_1254 = _out_rifireMux_T_1253 & _out_T_1672; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_288 = _out_rifireMux_T_1254; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_289 = _out_rifireMux_T_1254; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_290 = _out_rifireMux_T_1254; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_291 = _out_rifireMux_T_1254; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_292 = _out_rifireMux_T_1254; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_293 = _out_rifireMux_T_1254; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_294 = _out_rifireMux_T_1254; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_295 = _out_rifireMux_T_1254; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1255 = ~_out_T_1672; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1257 = _out_rifireMux_T_260 & out_frontSel_249; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_1258 = _out_rifireMux_T_1257 & _out_T_1602; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_8 = _out_rifireMux_T_1258; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_9 = _out_rifireMux_T_1258; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_10 = _out_rifireMux_T_1258; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_11 = _out_rifireMux_T_1258; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_12 = _out_rifireMux_T_1258; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_13 = _out_rifireMux_T_1258; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_14 = _out_rifireMux_T_1258; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_15 = _out_rifireMux_T_1258; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1259 = ~_out_T_1602; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1261 = _out_rifireMux_T_260 & out_frontSel_250; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_1262 = _out_rifireMux_T_1261 & _out_T_1842; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_939 = _out_rifireMux_T_1262; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_940 = _out_rifireMux_T_1262; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_941 = _out_rifireMux_T_1262; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_942 = _out_rifireMux_T_1262; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_943 = _out_rifireMux_T_1262; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_944 = _out_rifireMux_T_1262; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_945 = _out_rifireMux_T_1262; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_946 = _out_rifireMux_T_1262; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1263 = ~_out_T_1842; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1265 = _out_rifireMux_T_260 & out_frontSel_251; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_1266 = _out_rifireMux_T_1265 & _out_T_1794; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_747 = _out_rifireMux_T_1266; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_748 = _out_rifireMux_T_1266; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_749 = _out_rifireMux_T_1266; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_750 = _out_rifireMux_T_1266; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_751 = _out_rifireMux_T_1266; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_752 = _out_rifireMux_T_1266; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_753 = _out_rifireMux_T_1266; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_754 = _out_rifireMux_T_1266; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1267 = ~_out_T_1794; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1269 = _out_rifireMux_T_260 & out_frontSel_252; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_1270 = _out_rifireMux_T_1269 & _out_T_1692; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_362 = _out_rifireMux_T_1270; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_363 = _out_rifireMux_T_1270; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_364 = _out_rifireMux_T_1270; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_365 = _out_rifireMux_T_1270; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_366 = _out_rifireMux_T_1270; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_367 = _out_rifireMux_T_1270; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_368 = _out_rifireMux_T_1270; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_369 = _out_rifireMux_T_1270; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1271 = ~_out_T_1692; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1273 = _out_rifireMux_T_260 & out_frontSel_253; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_1274 = _out_rifireMux_T_1273 & _out_T_1654; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_216 = _out_rifireMux_T_1274; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_217 = _out_rifireMux_T_1274; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_218 = _out_rifireMux_T_1274; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_219 = _out_rifireMux_T_1274; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_220 = _out_rifireMux_T_1274; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_221 = _out_rifireMux_T_1274; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_222 = _out_rifireMux_T_1274; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_223 = _out_rifireMux_T_1274; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1275 = ~_out_T_1654; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1277 = _out_rifireMux_T_260 & out_frontSel_254; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_1278 = _out_rifireMux_T_1277 & _out_T_1906; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1195 = _out_rifireMux_T_1278; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1196 = _out_rifireMux_T_1278; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1197 = _out_rifireMux_T_1278; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1198 = _out_rifireMux_T_1278; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1199 = _out_rifireMux_T_1278; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1200 = _out_rifireMux_T_1278; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1201 = _out_rifireMux_T_1278; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1202 = _out_rifireMux_T_1278; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1279 = ~_out_T_1906; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1281 = _out_rifireMux_T_260 & out_frontSel_255; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_1282 = _out_rifireMux_T_1281 & _out_T_1810; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_811 = _out_rifireMux_T_1282; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_812 = _out_rifireMux_T_1282; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_813 = _out_rifireMux_T_1282; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_814 = _out_rifireMux_T_1282; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_815 = _out_rifireMux_T_1282; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_816 = _out_rifireMux_T_1282; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_817 = _out_rifireMux_T_1282; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_818 = _out_rifireMux_T_1282; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1283 = ~_out_T_1810; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_261 = ~out_front_1_bits_read; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_262 = _out_wifireMux_T_260 & _out_wifireMux_T_261; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_263 = _out_wifireMux_T_262 & out_frontSel_0_1; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_264 = _out_wifireMux_T_263 & _out_T_1716; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_451 = _out_wifireMux_T_264; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_452 = _out_wifireMux_T_264; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_453 = _out_wifireMux_T_264; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_454 = _out_wifireMux_T_264; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_455 = _out_wifireMux_T_264; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_456 = _out_wifireMux_T_264; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_457 = _out_wifireMux_T_264; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_458 = _out_wifireMux_T_264; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_265 = ~_out_T_1716; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_267 = _out_wifireMux_T_262 & out_frontSel_1_1; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_268 = _out_wifireMux_T_267 & _out_T_1624; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_96 = _out_wifireMux_T_268; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_97 = _out_wifireMux_T_268; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_98 = _out_wifireMux_T_268; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_99 = _out_wifireMux_T_268; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_100 = _out_wifireMux_T_268; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_101 = _out_wifireMux_T_268; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_102 = _out_wifireMux_T_268; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_103 = _out_wifireMux_T_268; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_269 = ~_out_T_1624; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_271 = _out_wifireMux_T_262 & out_frontSel_2_1; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_272 = _out_wifireMux_T_271 & _out_T_1846; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_955 = _out_wifireMux_T_272; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_956 = _out_wifireMux_T_272; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_957 = _out_wifireMux_T_272; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_958 = _out_wifireMux_T_272; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_959 = _out_wifireMux_T_272; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_960 = _out_wifireMux_T_272; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_961 = _out_wifireMux_T_272; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_962 = _out_wifireMux_T_272; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_273 = ~_out_T_1846; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_275 = _out_wifireMux_T_262 & out_frontSel_3_1; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_276 = _out_wifireMux_T_275 & _out_T_1756; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_601 = _out_wifireMux_T_276; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_602 = _out_wifireMux_T_276; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_603 = _out_wifireMux_T_276; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_604 = _out_wifireMux_T_276; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_605 = _out_wifireMux_T_276; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_606 = _out_wifireMux_T_276; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_607 = _out_wifireMux_T_276; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_608 = _out_wifireMux_T_276; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_277 = ~_out_T_1756; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_279 = _out_wifireMux_T_262 & out_frontSel_4_1; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_280 = _out_wifireMux_T_279 & _out_T_1678; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_312 = _out_wifireMux_T_280; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_313 = _out_wifireMux_T_280; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_314 = _out_wifireMux_T_280; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_315 = _out_wifireMux_T_280; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_316 = _out_wifireMux_T_280; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_317 = _out_wifireMux_T_280; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_318 = _out_wifireMux_T_280; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_319 = _out_wifireMux_T_280; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_281 = ~_out_T_1678; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_283 = _out_wifireMux_T_262 & out_frontSel_5_1; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_284 = _out_wifireMux_T_283 & _out_T_1640; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_160 = _out_wifireMux_T_284; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_161 = _out_wifireMux_T_284; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_162 = _out_wifireMux_T_284; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_163 = _out_wifireMux_T_284; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_164 = _out_wifireMux_T_284; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_165 = _out_wifireMux_T_284; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_166 = _out_wifireMux_T_284; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_167 = _out_wifireMux_T_284; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_285 = ~_out_T_1640; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_287 = _out_wifireMux_T_262 & out_frontSel_6_1; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_288 = _out_wifireMux_T_287 & _out_T_1876; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1075 = _out_wifireMux_T_288; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1076 = _out_wifireMux_T_288; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1077 = _out_wifireMux_T_288; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1078 = _out_wifireMux_T_288; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1079 = _out_wifireMux_T_288; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1080 = _out_wifireMux_T_288; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1081 = _out_wifireMux_T_288; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1082 = _out_wifireMux_T_288; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_289 = ~_out_T_1876; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_291 = _out_wifireMux_T_262 & out_frontSel_7_1; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_292 = _out_wifireMux_T_291 & _out_T_1822; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_859 = _out_wifireMux_T_292; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_860 = _out_wifireMux_T_292; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_861 = _out_wifireMux_T_292; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_862 = _out_wifireMux_T_292; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_863 = _out_wifireMux_T_292; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_864 = _out_wifireMux_T_292; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_865 = _out_wifireMux_T_292; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_866 = _out_wifireMux_T_292; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_293 = ~_out_T_1822; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_295 = _out_wifireMux_T_262 & out_frontSel_8_1; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_296 = _out_wifireMux_T_295 & _out_T_1742; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_545 = _out_wifireMux_T_296; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_546 = _out_wifireMux_T_296; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_547 = _out_wifireMux_T_296; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_548 = _out_wifireMux_T_296; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_549 = _out_wifireMux_T_296; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_550 = _out_wifireMux_T_296; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_551 = _out_wifireMux_T_296; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_552 = _out_wifireMux_T_296; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_297 = ~_out_T_1742; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_299 = _out_wifireMux_T_262 & out_frontSel_9_1; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_300 = _out_wifireMux_T_299 & _out_T_1666; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_264 = _out_wifireMux_T_300; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_265 = _out_wifireMux_T_300; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_266 = _out_wifireMux_T_300; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_267 = _out_wifireMux_T_300; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_268 = _out_wifireMux_T_300; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_269 = _out_wifireMux_T_300; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_270 = _out_wifireMux_T_300; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_271 = _out_wifireMux_T_300; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_301 = ~_out_T_1666; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_303 = _out_wifireMux_T_262 & out_frontSel_10_1; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_304 = _out_wifireMux_T_303 & _out_T_1724; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_483 = _out_wifireMux_T_304; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_484 = _out_wifireMux_T_304; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_485 = _out_wifireMux_T_304; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_486 = _out_wifireMux_T_304; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_305 = ~_out_T_1724; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_307 = _out_wifireMux_T_262 & out_frontSel_11_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_308 = _out_wifireMux_T_307; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_311 = _out_wifireMux_T_262 & out_frontSel_12_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_312 = _out_wifireMux_T_311; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_315 = _out_wifireMux_T_262 & out_frontSel_13_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_316 = _out_wifireMux_T_315; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_319 = _out_wifireMux_T_262 & out_frontSel_14_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_320 = _out_wifireMux_T_319; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_323 = _out_wifireMux_T_262 & out_frontSel_15_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_324 = _out_wifireMux_T_323; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_327 = _out_wifireMux_T_262 & out_frontSel_16_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_328 = _out_wifireMux_T_327; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_331 = _out_wifireMux_T_262 & out_frontSel_17_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_332 = _out_wifireMux_T_331; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_335 = _out_wifireMux_T_262 & out_frontSel_18_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_336 = _out_wifireMux_T_335; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_339 = _out_wifireMux_T_262 & out_frontSel_19_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_340 = _out_wifireMux_T_339; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_343 = _out_wifireMux_T_262 & out_frontSel_20_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_344 = _out_wifireMux_T_343; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_347 = _out_wifireMux_T_262 & out_frontSel_21_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_348 = _out_wifireMux_T_347; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_351 = _out_wifireMux_T_262 & out_frontSel_22_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_352 = _out_wifireMux_T_351; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_355 = _out_wifireMux_T_262 & out_frontSel_23_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_356 = _out_wifireMux_T_355; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_359 = _out_wifireMux_T_262 & out_frontSel_24_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_360 = _out_wifireMux_T_359; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_363 = _out_wifireMux_T_262 & out_frontSel_25_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_364 = _out_wifireMux_T_363; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_367 = _out_wifireMux_T_262 & out_frontSel_26_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_368 = _out_wifireMux_T_367; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_371 = _out_wifireMux_T_262 & out_frontSel_27_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_372 = _out_wifireMux_T_371; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_375 = _out_wifireMux_T_262 & out_frontSel_28_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_376 = _out_wifireMux_T_375; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_379 = _out_wifireMux_T_262 & out_frontSel_29_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_380 = _out_wifireMux_T_379; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_383 = _out_wifireMux_T_262 & out_frontSel_30_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_384 = _out_wifireMux_T_383; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_387 = _out_wifireMux_T_262 & out_frontSel_31_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_388 = _out_wifireMux_T_387; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_391 = _out_wifireMux_T_262 & out_frontSel_32_1; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_392 = _out_wifireMux_T_391 & _out_T_1738; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_535 = _out_wifireMux_T_392; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_536 = _out_wifireMux_T_392; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_393 = ~_out_T_1738; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_395 = _out_wifireMux_T_262 & out_frontSel_33_1; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_396 = _out_wifireMux_T_395 & _out_T_1688; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_352 = _out_wifireMux_T_396; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_353 = _out_wifireMux_T_396; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_397 = ~_out_T_1688; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_399 = _out_wifireMux_T_262 & out_frontSel_34_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_400 = _out_wifireMux_T_399; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_403 = _out_wifireMux_T_262 & out_frontSel_35_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_404 = _out_wifireMux_T_403; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_407 = _out_wifireMux_T_262 & out_frontSel_36_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_408 = _out_wifireMux_T_407; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_411 = _out_wifireMux_T_262 & out_frontSel_37_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_412 = _out_wifireMux_T_411; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_415 = _out_wifireMux_T_262 & out_frontSel_38_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_416 = _out_wifireMux_T_415; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_419 = _out_wifireMux_T_262 & out_frontSel_39_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_420 = _out_wifireMux_T_419; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_423 = _out_wifireMux_T_262 & out_frontSel_40_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_424 = _out_wifireMux_T_423; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_427 = _out_wifireMux_T_262 & out_frontSel_41_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_428 = _out_wifireMux_T_427; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_431 = _out_wifireMux_T_262 & out_frontSel_42_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_432 = _out_wifireMux_T_431; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_435 = _out_wifireMux_T_262 & out_frontSel_43_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_436 = _out_wifireMux_T_435; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_439 = _out_wifireMux_T_262 & out_frontSel_44_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_440 = _out_wifireMux_T_439; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_443 = _out_wifireMux_T_262 & out_frontSel_45_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_444 = _out_wifireMux_T_443; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_447 = _out_wifireMux_T_262 & out_frontSel_46_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_448 = _out_wifireMux_T_447; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_451 = _out_wifireMux_T_262 & out_frontSel_47_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_452 = _out_wifireMux_T_451; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_455 = _out_wifireMux_T_262 & out_frontSel_48_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_456 = _out_wifireMux_T_455; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_459 = _out_wifireMux_T_262 & out_frontSel_49_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_460 = _out_wifireMux_T_459; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_463 = _out_wifireMux_T_262 & out_frontSel_50_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_464 = _out_wifireMux_T_463; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_467 = _out_wifireMux_T_262 & out_frontSel_51_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_468 = _out_wifireMux_T_467; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_471 = _out_wifireMux_T_262 & out_frontSel_52_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_472 = _out_wifireMux_T_471; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_475 = _out_wifireMux_T_262 & out_frontSel_53_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_476 = _out_wifireMux_T_475; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_479 = _out_wifireMux_T_262 & out_frontSel_54_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_480 = _out_wifireMux_T_479; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_483 = _out_wifireMux_T_262 & out_frontSel_55_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_484 = _out_wifireMux_T_483; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_487 = _out_wifireMux_T_262 & out_frontSel_56_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_488 = _out_wifireMux_T_487; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_491 = _out_wifireMux_T_262 & out_frontSel_57_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_492 = _out_wifireMux_T_491; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_495 = _out_wifireMux_T_262 & out_frontSel_58_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_496 = _out_wifireMux_T_495; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_499 = _out_wifireMux_T_262 & out_frontSel_59_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_500 = _out_wifireMux_T_499; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_503 = _out_wifireMux_T_262 & out_frontSel_60_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_504 = _out_wifireMux_T_503; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_507 = _out_wifireMux_T_262 & out_frontSel_61_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_508 = _out_wifireMux_T_507; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_511 = _out_wifireMux_T_262 & out_frontSel_62_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_512 = _out_wifireMux_T_511; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_515 = _out_wifireMux_T_262 & out_frontSel_63_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_516 = _out_wifireMux_T_515; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_519 = _out_wifireMux_T_262 & out_frontSel_64; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_520 = _out_wifireMux_T_519; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_523 = _out_wifireMux_T_262 & out_frontSel_65; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_524 = _out_wifireMux_T_523; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_527 = _out_wifireMux_T_262 & out_frontSel_66; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_528 = _out_wifireMux_T_527; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_531 = _out_wifireMux_T_262 & out_frontSel_67; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_532 = _out_wifireMux_T_531; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_535 = _out_wifireMux_T_262 & out_frontSel_68; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_536 = _out_wifireMux_T_535; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_539 = _out_wifireMux_T_262 & out_frontSel_69; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_540 = _out_wifireMux_T_539; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_543 = _out_wifireMux_T_262 & out_frontSel_70; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_544 = _out_wifireMux_T_543; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_547 = _out_wifireMux_T_262 & out_frontSel_71; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_548 = _out_wifireMux_T_547; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_551 = _out_wifireMux_T_262 & out_frontSel_72; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_552 = _out_wifireMux_T_551; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_555 = _out_wifireMux_T_262 & out_frontSel_73; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_556 = _out_wifireMux_T_555; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_559 = _out_wifireMux_T_262 & out_frontSel_74; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_560 = _out_wifireMux_T_559; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_563 = _out_wifireMux_T_262 & out_frontSel_75; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_564 = _out_wifireMux_T_563; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_567 = _out_wifireMux_T_262 & out_frontSel_76; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_568 = _out_wifireMux_T_567; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_571 = _out_wifireMux_T_262 & out_frontSel_77; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_572 = _out_wifireMux_T_571; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_575 = _out_wifireMux_T_262 & out_frontSel_78; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_576 = _out_wifireMux_T_575; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_579 = _out_wifireMux_T_262 & out_frontSel_79; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_580 = _out_wifireMux_T_579; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_583 = _out_wifireMux_T_262 & out_frontSel_80; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_584 = _out_wifireMux_T_583; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_587 = _out_wifireMux_T_262 & out_frontSel_81; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_588 = _out_wifireMux_T_587; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_591 = _out_wifireMux_T_262 & out_frontSel_82; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_592 = _out_wifireMux_T_591; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_595 = _out_wifireMux_T_262 & out_frontSel_83; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_596 = _out_wifireMux_T_595; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_599 = _out_wifireMux_T_262 & out_frontSel_84; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_600 = _out_wifireMux_T_599; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_603 = _out_wifireMux_T_262 & out_frontSel_85; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_604 = _out_wifireMux_T_603; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_607 = _out_wifireMux_T_262 & out_frontSel_86; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_608 = _out_wifireMux_T_607; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_611 = _out_wifireMux_T_262 & out_frontSel_87; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_612 = _out_wifireMux_T_611; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_615 = _out_wifireMux_T_262 & out_frontSel_88; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_616 = _out_wifireMux_T_615; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_619 = _out_wifireMux_T_262 & out_frontSel_89; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_620 = _out_wifireMux_T_619; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_623 = _out_wifireMux_T_262 & out_frontSel_90; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_624 = _out_wifireMux_T_623; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_627 = _out_wifireMux_T_262 & out_frontSel_91; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_628 = _out_wifireMux_T_627; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_631 = _out_wifireMux_T_262 & out_frontSel_92; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_632 = _out_wifireMux_T_631; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_635 = _out_wifireMux_T_262 & out_frontSel_93; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_636 = _out_wifireMux_T_635; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_639 = _out_wifireMux_T_262 & out_frontSel_94; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_640 = _out_wifireMux_T_639; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_643 = _out_wifireMux_T_262 & out_frontSel_95; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_644 = _out_wifireMux_T_643; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_647 = _out_wifireMux_T_262 & out_frontSel_96; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_648 = _out_wifireMux_T_647 & _out_T_1712; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_442 = _out_wifireMux_T_648; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_649 = ~_out_T_1712; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_651 = _out_wifireMux_T_262 & out_frontSel_97; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_652 = _out_wifireMux_T_651; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_655 = _out_wifireMux_T_262 & out_frontSel_98; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_656 = _out_wifireMux_T_655; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_659 = _out_wifireMux_T_262 & out_frontSel_99; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_660 = _out_wifireMux_T_659; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_663 = _out_wifireMux_T_262 & out_frontSel_100; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_664 = _out_wifireMux_T_663; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_667 = _out_wifireMux_T_262 & out_frontSel_101; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_668 = _out_wifireMux_T_667; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_671 = _out_wifireMux_T_262 & out_frontSel_102; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_672 = _out_wifireMux_T_671; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_675 = _out_wifireMux_T_262 & out_frontSel_103; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_676 = _out_wifireMux_T_675 & _out_T_1780; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_697 = _out_wifireMux_T_676; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_698 = _out_wifireMux_T_676; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_677 = ~_out_T_1780; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_679 = _out_wifireMux_T_262 & out_frontSel_104; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_680 = _out_wifireMux_T_679 & _out_T_1840; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_931 = _out_wifireMux_T_680; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_932 = _out_wifireMux_T_680; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_933 = _out_wifireMux_T_680; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_934 = _out_wifireMux_T_680; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_935 = _out_wifireMux_T_680; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_936 = _out_wifireMux_T_680; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_937 = _out_wifireMux_T_680; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_938 = _out_wifireMux_T_680; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_681 = ~_out_T_1840; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_683 = _out_wifireMux_T_262 & out_frontSel_105; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_684 = _out_wifireMux_T_683 & _out_T_1732; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_511 = _out_wifireMux_T_684; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_512 = _out_wifireMux_T_684; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_513 = _out_wifireMux_T_684; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_514 = _out_wifireMux_T_684; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_515 = _out_wifireMux_T_684; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_516 = _out_wifireMux_T_684; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_517 = _out_wifireMux_T_684; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_518 = _out_wifireMux_T_684; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_685 = ~_out_T_1732; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_687 = _out_wifireMux_T_262 & out_frontSel_106; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_688 = _out_wifireMux_T_687 & _out_T_1648; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_192 = _out_wifireMux_T_688; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_193 = _out_wifireMux_T_688; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_194 = _out_wifireMux_T_688; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_195 = _out_wifireMux_T_688; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_196 = _out_wifireMux_T_688; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_197 = _out_wifireMux_T_688; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_198 = _out_wifireMux_T_688; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_199 = _out_wifireMux_T_688; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_689 = ~_out_T_1648; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_691 = _out_wifireMux_T_262 & out_frontSel_107; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_692 = _out_wifireMux_T_691 & _out_T_1880; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1091 = _out_wifireMux_T_692; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1092 = _out_wifireMux_T_692; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1093 = _out_wifireMux_T_692; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1094 = _out_wifireMux_T_692; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1095 = _out_wifireMux_T_692; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1096 = _out_wifireMux_T_692; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1097 = _out_wifireMux_T_692; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1098 = _out_wifireMux_T_692; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_693 = ~_out_T_1880; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_695 = _out_wifireMux_T_262 & out_frontSel_108; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_696 = _out_wifireMux_T_695 & _out_T_1790; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_731 = _out_wifireMux_T_696; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_732 = _out_wifireMux_T_696; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_733 = _out_wifireMux_T_696; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_734 = _out_wifireMux_T_696; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_735 = _out_wifireMux_T_696; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_736 = _out_wifireMux_T_696; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_737 = _out_wifireMux_T_696; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_738 = _out_wifireMux_T_696; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_697 = ~_out_T_1790; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_699 = _out_wifireMux_T_262 & out_frontSel_109; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_700 = _out_wifireMux_T_699 & _out_T_1714; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_443 = _out_wifireMux_T_700; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_444 = _out_wifireMux_T_700; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_445 = _out_wifireMux_T_700; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_446 = _out_wifireMux_T_700; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_447 = _out_wifireMux_T_700; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_448 = _out_wifireMux_T_700; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_449 = _out_wifireMux_T_700; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_450 = _out_wifireMux_T_700; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_701 = ~_out_T_1714; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_703 = _out_wifireMux_T_262 & out_frontSel_110; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_704 = _out_wifireMux_T_703 & _out_T_1628; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_112 = _out_wifireMux_T_704; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_113 = _out_wifireMux_T_704; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_114 = _out_wifireMux_T_704; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_115 = _out_wifireMux_T_704; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_116 = _out_wifireMux_T_704; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_117 = _out_wifireMux_T_704; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_118 = _out_wifireMux_T_704; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_119 = _out_wifireMux_T_704; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_705 = ~_out_T_1628; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_707 = _out_wifireMux_T_262 & out_frontSel_111; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_708 = _out_wifireMux_T_707 & _out_T_1898; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1163 = _out_wifireMux_T_708; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1164 = _out_wifireMux_T_708; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1165 = _out_wifireMux_T_708; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1166 = _out_wifireMux_T_708; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1167 = _out_wifireMux_T_708; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1168 = _out_wifireMux_T_708; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1169 = _out_wifireMux_T_708; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1170 = _out_wifireMux_T_708; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_709 = ~_out_T_1898; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_711 = _out_wifireMux_T_262 & out_frontSel_112; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_712 = _out_wifireMux_T_711 & _out_T_1814; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_827 = _out_wifireMux_T_712; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_828 = _out_wifireMux_T_712; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_829 = _out_wifireMux_T_712; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_830 = _out_wifireMux_T_712; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_831 = _out_wifireMux_T_712; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_832 = _out_wifireMux_T_712; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_833 = _out_wifireMux_T_712; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_834 = _out_wifireMux_T_712; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_713 = ~_out_T_1814; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_715 = _out_wifireMux_T_262 & out_frontSel_113; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_716 = _out_wifireMux_T_715 & _out_T_1770; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_657 = _out_wifireMux_T_716; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_658 = _out_wifireMux_T_716; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_659 = _out_wifireMux_T_716; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_660 = _out_wifireMux_T_716; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_661 = _out_wifireMux_T_716; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_662 = _out_wifireMux_T_716; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_663 = _out_wifireMux_T_716; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_664 = _out_wifireMux_T_716; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_717 = ~_out_T_1770; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_719 = _out_wifireMux_T_262 & out_frontSel_114; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_720 = _out_wifireMux_T_719 & _out_T_1852; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_979 = _out_wifireMux_T_720; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_980 = _out_wifireMux_T_720; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_981 = _out_wifireMux_T_720; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_982 = _out_wifireMux_T_720; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_983 = _out_wifireMux_T_720; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_984 = _out_wifireMux_T_720; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_985 = _out_wifireMux_T_720; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_986 = _out_wifireMux_T_720; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_721 = ~_out_T_1852; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_723 = _out_wifireMux_T_262 & out_frontSel_115; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_724 = _out_wifireMux_T_723 & _out_T_1608; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_32 = _out_wifireMux_T_724; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_33 = _out_wifireMux_T_724; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_34 = _out_wifireMux_T_724; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_35 = _out_wifireMux_T_724; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_36 = _out_wifireMux_T_724; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_37 = _out_wifireMux_T_724; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_38 = _out_wifireMux_T_724; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_39 = _out_wifireMux_T_724; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_725 = ~_out_T_1608; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_727 = _out_wifireMux_T_262 & out_frontSel_116; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_728 = _out_wifireMux_T_727; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_731 = _out_wifireMux_T_262 & out_frontSel_117; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_732 = _out_wifireMux_T_731; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_735 = _out_wifireMux_T_262 & out_frontSel_118; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_736 = _out_wifireMux_T_735; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_739 = _out_wifireMux_T_262 & out_frontSel_119; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_740 = _out_wifireMux_T_739; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_743 = _out_wifireMux_T_262 & out_frontSel_120; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_744 = _out_wifireMux_T_743; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_747 = _out_wifireMux_T_262 & out_frontSel_121; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_748 = _out_wifireMux_T_747; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_751 = _out_wifireMux_T_262 & out_frontSel_122; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_752 = _out_wifireMux_T_751; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_755 = _out_wifireMux_T_262 & out_frontSel_123; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_756 = _out_wifireMux_T_755; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_759 = _out_wifireMux_T_262 & out_frontSel_124; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_760 = _out_wifireMux_T_759; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_763 = _out_wifireMux_T_262 & out_frontSel_125; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_764 = _out_wifireMux_T_763; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_767 = _out_wifireMux_T_262 & out_frontSel_126; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_768 = _out_wifireMux_T_767; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_771 = _out_wifireMux_T_262 & out_frontSel_127; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_772 = _out_wifireMux_T_771; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_775 = _out_wifireMux_T_262 & out_frontSel_128; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_776 = _out_wifireMux_T_775 & _out_T_1728; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_495 = _out_wifireMux_T_776; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_496 = _out_wifireMux_T_776; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_497 = _out_wifireMux_T_776; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_498 = _out_wifireMux_T_776; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_499 = _out_wifireMux_T_776; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_500 = _out_wifireMux_T_776; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_501 = _out_wifireMux_T_776; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_502 = _out_wifireMux_T_776; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_777 = ~_out_T_1728; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_779 = _out_wifireMux_T_262 & out_frontSel_129; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_780 = _out_wifireMux_T_779 & _out_T_1720; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_467 = _out_wifireMux_T_780; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_468 = _out_wifireMux_T_780; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_469 = _out_wifireMux_T_780; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_470 = _out_wifireMux_T_780; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_471 = _out_wifireMux_T_780; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_472 = _out_wifireMux_T_780; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_473 = _out_wifireMux_T_780; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_474 = _out_wifireMux_T_780; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_781 = ~_out_T_1720; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_783 = _out_wifireMux_T_262 & out_frontSel_130; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_784 = _out_wifireMux_T_783 & _out_T_1796; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_755 = _out_wifireMux_T_784; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_756 = _out_wifireMux_T_784; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_757 = _out_wifireMux_T_784; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_758 = _out_wifireMux_T_784; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_759 = _out_wifireMux_T_784; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_760 = _out_wifireMux_T_784; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_761 = _out_wifireMux_T_784; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_762 = _out_wifireMux_T_784; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_785 = ~_out_T_1796; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_787 = _out_wifireMux_T_262 & out_frontSel_131; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_788 = _out_wifireMux_T_787 & _out_T_1890; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1131 = _out_wifireMux_T_788; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1132 = _out_wifireMux_T_788; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1133 = _out_wifireMux_T_788; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1134 = _out_wifireMux_T_788; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1135 = _out_wifireMux_T_788; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1136 = _out_wifireMux_T_788; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1137 = _out_wifireMux_T_788; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1138 = _out_wifireMux_T_788; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_789 = ~_out_T_1890; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_791 = _out_wifireMux_T_262 & out_frontSel_132; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_792 = _out_wifireMux_T_791 & _out_T_1660; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_240 = _out_wifireMux_T_792; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_241 = _out_wifireMux_T_792; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_242 = _out_wifireMux_T_792; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_243 = _out_wifireMux_T_792; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_244 = _out_wifireMux_T_792; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_245 = _out_wifireMux_T_792; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_246 = _out_wifireMux_T_792; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_247 = _out_wifireMux_T_792; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_793 = ~_out_T_1660; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_795 = _out_wifireMux_T_262 & out_frontSel_133; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_796 = _out_wifireMux_T_795 & _out_T_1662; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_248 = _out_wifireMux_T_796; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_249 = _out_wifireMux_T_796; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_250 = _out_wifireMux_T_796; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_251 = _out_wifireMux_T_796; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_252 = _out_wifireMux_T_796; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_253 = _out_wifireMux_T_796; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_254 = _out_wifireMux_T_796; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_255 = _out_wifireMux_T_796; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_797 = ~_out_T_1662; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_799 = _out_wifireMux_T_262 & out_frontSel_134; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_800 = _out_wifireMux_T_799 & _out_T_1722; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_475 = _out_wifireMux_T_800; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_476 = _out_wifireMux_T_800; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_477 = _out_wifireMux_T_800; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_478 = _out_wifireMux_T_800; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_479 = _out_wifireMux_T_800; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_480 = _out_wifireMux_T_800; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_481 = _out_wifireMux_T_800; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_482 = _out_wifireMux_T_800; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_801 = ~_out_T_1722; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_803 = _out_wifireMux_T_262 & out_frontSel_135; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_804 = _out_wifireMux_T_803 & _out_T_1800; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_771 = _out_wifireMux_T_804; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_772 = _out_wifireMux_T_804; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_773 = _out_wifireMux_T_804; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_774 = _out_wifireMux_T_804; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_775 = _out_wifireMux_T_804; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_776 = _out_wifireMux_T_804; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_777 = _out_wifireMux_T_804; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_778 = _out_wifireMux_T_804; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_805 = ~_out_T_1800; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_807 = _out_wifireMux_T_262 & out_frontSel_136; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_808 = _out_wifireMux_T_807 & _out_T_1882; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1099 = _out_wifireMux_T_808; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1100 = _out_wifireMux_T_808; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1101 = _out_wifireMux_T_808; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1102 = _out_wifireMux_T_808; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1103 = _out_wifireMux_T_808; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1104 = _out_wifireMux_T_808; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1105 = _out_wifireMux_T_808; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1106 = _out_wifireMux_T_808; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_809 = ~_out_T_1882; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_811 = _out_wifireMux_T_262 & out_frontSel_137; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_812 = _out_wifireMux_T_811 & _out_T_1684; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_336 = _out_wifireMux_T_812; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_337 = _out_wifireMux_T_812; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_338 = _out_wifireMux_T_812; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_339 = _out_wifireMux_T_812; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_340 = _out_wifireMux_T_812; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_341 = _out_wifireMux_T_812; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_342 = _out_wifireMux_T_812; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_343 = _out_wifireMux_T_812; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_813 = ~_out_T_1684; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_815 = _out_wifireMux_T_262 & out_frontSel_138; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_816 = _out_wifireMux_T_815 & _out_T_1600; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_0 = _out_wifireMux_T_816; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1 = _out_wifireMux_T_816; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_2 = _out_wifireMux_T_816; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_3 = _out_wifireMux_T_816; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_4 = _out_wifireMux_T_816; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_5 = _out_wifireMux_T_816; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_6 = _out_wifireMux_T_816; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_7 = _out_wifireMux_T_816; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_817 = ~_out_T_1600; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_819 = _out_wifireMux_T_262 & out_frontSel_139; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_820 = _out_wifireMux_T_819 & _out_T_1856; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_995 = _out_wifireMux_T_820; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_996 = _out_wifireMux_T_820; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_997 = _out_wifireMux_T_820; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_998 = _out_wifireMux_T_820; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_999 = _out_wifireMux_T_820; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1000 = _out_wifireMux_T_820; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1001 = _out_wifireMux_T_820; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1002 = _out_wifireMux_T_820; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_821 = ~_out_T_1856; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_823 = _out_wifireMux_T_262 & out_frontSel_140; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_824 = _out_wifireMux_T_823 & _out_T_1782; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_699 = _out_wifireMux_T_824; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_700 = _out_wifireMux_T_824; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_701 = _out_wifireMux_T_824; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_702 = _out_wifireMux_T_824; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_703 = _out_wifireMux_T_824; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_704 = _out_wifireMux_T_824; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_705 = _out_wifireMux_T_824; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_706 = _out_wifireMux_T_824; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_825 = ~_out_T_1782; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_827 = _out_wifireMux_T_262 & out_frontSel_141; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_828 = _out_wifireMux_T_827 & _out_T_1704; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_410 = _out_wifireMux_T_828; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_411 = _out_wifireMux_T_828; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_412 = _out_wifireMux_T_828; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_413 = _out_wifireMux_T_828; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_414 = _out_wifireMux_T_828; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_415 = _out_wifireMux_T_828; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_416 = _out_wifireMux_T_828; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_417 = _out_wifireMux_T_828; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_829 = ~_out_T_1704; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_831 = _out_wifireMux_T_262 & out_frontSel_142; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_832 = _out_wifireMux_T_831 & _out_T_1616; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_64 = _out_wifireMux_T_832; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_65 = _out_wifireMux_T_832; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_66 = _out_wifireMux_T_832; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_67 = _out_wifireMux_T_832; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_68 = _out_wifireMux_T_832; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_69 = _out_wifireMux_T_832; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_70 = _out_wifireMux_T_832; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_71 = _out_wifireMux_T_832; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_833 = ~_out_T_1616; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_835 = _out_wifireMux_T_262 & out_frontSel_143; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_836 = _out_wifireMux_T_835 & _out_T_1834; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_907 = _out_wifireMux_T_836; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_908 = _out_wifireMux_T_836; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_909 = _out_wifireMux_T_836; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_910 = _out_wifireMux_T_836; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_911 = _out_wifireMux_T_836; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_912 = _out_wifireMux_T_836; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_913 = _out_wifireMux_T_836; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_914 = _out_wifireMux_T_836; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_837 = ~_out_T_1834; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_839 = _out_wifireMux_T_262 & out_frontSel_144; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_840 = _out_wifireMux_T_839 & _out_T_1758; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_609 = _out_wifireMux_T_840; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_610 = _out_wifireMux_T_840; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_611 = _out_wifireMux_T_840; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_612 = _out_wifireMux_T_840; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_613 = _out_wifireMux_T_840; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_614 = _out_wifireMux_T_840; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_615 = _out_wifireMux_T_840; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_616 = _out_wifireMux_T_840; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_841 = ~_out_T_1758; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_843 = _out_wifireMux_T_262 & out_frontSel_145; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_844 = _out_wifireMux_T_843 & _out_T_1818; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_843 = _out_wifireMux_T_844; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_844 = _out_wifireMux_T_844; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_845 = _out_wifireMux_T_844; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_846 = _out_wifireMux_T_844; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_847 = _out_wifireMux_T_844; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_848 = _out_wifireMux_T_844; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_849 = _out_wifireMux_T_844; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_850 = _out_wifireMux_T_844; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_845 = ~_out_T_1818; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_847 = _out_wifireMux_T_262 & out_frontSel_146; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_848 = _out_wifireMux_T_847 & _out_T_1868; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1043 = _out_wifireMux_T_848; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1044 = _out_wifireMux_T_848; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1045 = _out_wifireMux_T_848; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1046 = _out_wifireMux_T_848; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1047 = _out_wifireMux_T_848; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1048 = _out_wifireMux_T_848; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1049 = _out_wifireMux_T_848; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1050 = _out_wifireMux_T_848; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_849 = ~_out_T_1868; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_851 = _out_wifireMux_T_262 & out_frontSel_147; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_852 = _out_wifireMux_T_851 & _out_T_1656; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_224 = _out_wifireMux_T_852; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_225 = _out_wifireMux_T_852; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_226 = _out_wifireMux_T_852; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_227 = _out_wifireMux_T_852; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_228 = _out_wifireMux_T_852; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_229 = _out_wifireMux_T_852; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_230 = _out_wifireMux_T_852; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_231 = _out_wifireMux_T_852; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_853 = ~_out_T_1656; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_855 = _out_wifireMux_T_262 & out_frontSel_148; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_856 = _out_wifireMux_T_855 & _out_T_1740; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_537 = _out_wifireMux_T_856; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_538 = _out_wifireMux_T_856; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_539 = _out_wifireMux_T_856; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_540 = _out_wifireMux_T_856; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_541 = _out_wifireMux_T_856; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_542 = _out_wifireMux_T_856; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_543 = _out_wifireMux_T_856; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_544 = _out_wifireMux_T_856; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_857 = ~_out_T_1740; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_859 = _out_wifireMux_T_262 & out_frontSel_149; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_860 = _out_wifireMux_T_859 & _out_T_1748; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_569 = _out_wifireMux_T_860; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_570 = _out_wifireMux_T_860; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_571 = _out_wifireMux_T_860; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_572 = _out_wifireMux_T_860; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_573 = _out_wifireMux_T_860; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_574 = _out_wifireMux_T_860; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_575 = _out_wifireMux_T_860; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_576 = _out_wifireMux_T_860; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_861 = ~_out_T_1748; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_863 = _out_wifireMux_T_262 & out_frontSel_150; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_864 = _out_wifireMux_T_863 & _out_T_1820; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_851 = _out_wifireMux_T_864; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_852 = _out_wifireMux_T_864; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_853 = _out_wifireMux_T_864; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_854 = _out_wifireMux_T_864; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_855 = _out_wifireMux_T_864; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_856 = _out_wifireMux_T_864; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_857 = _out_wifireMux_T_864; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_858 = _out_wifireMux_T_864; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_865 = ~_out_T_1820; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_867 = _out_wifireMux_T_262 & out_frontSel_151; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_868 = _out_wifireMux_T_867 & _out_T_1866; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1035 = _out_wifireMux_T_868; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1036 = _out_wifireMux_T_868; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1037 = _out_wifireMux_T_868; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1038 = _out_wifireMux_T_868; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1039 = _out_wifireMux_T_868; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1040 = _out_wifireMux_T_868; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1041 = _out_wifireMux_T_868; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1042 = _out_wifireMux_T_868; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_869 = ~_out_T_1866; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_871 = _out_wifireMux_T_262 & out_frontSel_152; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_872 = _out_wifireMux_T_871 & _out_T_1636; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_144 = _out_wifireMux_T_872; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_145 = _out_wifireMux_T_872; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_146 = _out_wifireMux_T_872; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_147 = _out_wifireMux_T_872; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_148 = _out_wifireMux_T_872; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_149 = _out_wifireMux_T_872; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_150 = _out_wifireMux_T_872; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_151 = _out_wifireMux_T_872; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_873 = ~_out_T_1636; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_875 = _out_wifireMux_T_262 & out_frontSel_153; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_876 = _out_wifireMux_T_875 & _out_T_1618; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_72 = _out_wifireMux_T_876; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_73 = _out_wifireMux_T_876; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_74 = _out_wifireMux_T_876; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_75 = _out_wifireMux_T_876; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_76 = _out_wifireMux_T_876; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_77 = _out_wifireMux_T_876; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_78 = _out_wifireMux_T_876; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_79 = _out_wifireMux_T_876; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_877 = ~_out_T_1618; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_879 = _out_wifireMux_T_262 & out_frontSel_154; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_880 = _out_wifireMux_T_879 & _out_T_1830; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_891 = _out_wifireMux_T_880; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_892 = _out_wifireMux_T_880; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_893 = _out_wifireMux_T_880; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_894 = _out_wifireMux_T_880; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_895 = _out_wifireMux_T_880; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_896 = _out_wifireMux_T_880; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_897 = _out_wifireMux_T_880; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_898 = _out_wifireMux_T_880; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_881 = ~_out_T_1830; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_883 = _out_wifireMux_T_262 & out_frontSel_155; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_884 = _out_wifireMux_T_883 & _out_T_1786; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_715 = _out_wifireMux_T_884; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_716 = _out_wifireMux_T_884; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_717 = _out_wifireMux_T_884; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_718 = _out_wifireMux_T_884; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_719 = _out_wifireMux_T_884; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_720 = _out_wifireMux_T_884; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_721 = _out_wifireMux_T_884; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_722 = _out_wifireMux_T_884; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_885 = ~_out_T_1786; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_887 = _out_wifireMux_T_262 & out_frontSel_156; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_888 = _out_wifireMux_T_887 & _out_T_1698; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_386 = _out_wifireMux_T_888; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_387 = _out_wifireMux_T_888; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_388 = _out_wifireMux_T_888; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_389 = _out_wifireMux_T_888; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_390 = _out_wifireMux_T_888; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_391 = _out_wifireMux_T_888; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_392 = _out_wifireMux_T_888; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_393 = _out_wifireMux_T_888; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_889 = ~_out_T_1698; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_891 = _out_wifireMux_T_262 & out_frontSel_157; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_892 = _out_wifireMux_T_891 & _out_T_1632; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_128 = _out_wifireMux_T_892; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_129 = _out_wifireMux_T_892; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_130 = _out_wifireMux_T_892; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_131 = _out_wifireMux_T_892; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_132 = _out_wifireMux_T_892; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_133 = _out_wifireMux_T_892; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_134 = _out_wifireMux_T_892; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_135 = _out_wifireMux_T_892; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_893 = ~_out_T_1632; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_895 = _out_wifireMux_T_262 & out_frontSel_158; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_896 = _out_wifireMux_T_895 & _out_T_1848; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_963 = _out_wifireMux_T_896; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_964 = _out_wifireMux_T_896; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_965 = _out_wifireMux_T_896; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_966 = _out_wifireMux_T_896; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_967 = _out_wifireMux_T_896; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_968 = _out_wifireMux_T_896; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_969 = _out_wifireMux_T_896; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_970 = _out_wifireMux_T_896; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_897 = ~_out_T_1848; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_899 = _out_wifireMux_T_262 & out_frontSel_159; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_900 = _out_wifireMux_T_899 & _out_T_1764; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_633 = _out_wifireMux_T_900; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_634 = _out_wifireMux_T_900; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_635 = _out_wifireMux_T_900; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_636 = _out_wifireMux_T_900; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_637 = _out_wifireMux_T_900; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_638 = _out_wifireMux_T_900; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_639 = _out_wifireMux_T_900; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_640 = _out_wifireMux_T_900; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_901 = ~_out_T_1764; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_903 = _out_wifireMux_T_262 & out_frontSel_160; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_904 = _out_wifireMux_T_903 & _out_T_1680; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_320 = _out_wifireMux_T_904; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_321 = _out_wifireMux_T_904; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_322 = _out_wifireMux_T_904; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_323 = _out_wifireMux_T_904; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_324 = _out_wifireMux_T_904; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_325 = _out_wifireMux_T_904; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_326 = _out_wifireMux_T_904; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_327 = _out_wifireMux_T_904; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_905 = ~_out_T_1680; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_907 = _out_wifireMux_T_262 & out_frontSel_161; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_908 = _out_wifireMux_T_907 & _out_T_1744; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_553 = _out_wifireMux_T_908; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_554 = _out_wifireMux_T_908; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_555 = _out_wifireMux_T_908; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_556 = _out_wifireMux_T_908; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_557 = _out_wifireMux_T_908; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_558 = _out_wifireMux_T_908; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_559 = _out_wifireMux_T_908; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_560 = _out_wifireMux_T_908; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_909 = ~_out_T_1744; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_911 = _out_wifireMux_T_262 & out_frontSel_162; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_912 = _out_wifireMux_T_911 & _out_T_1808; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_803 = _out_wifireMux_T_912; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_804 = _out_wifireMux_T_912; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_805 = _out_wifireMux_T_912; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_806 = _out_wifireMux_T_912; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_807 = _out_wifireMux_T_912; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_808 = _out_wifireMux_T_912; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_809 = _out_wifireMux_T_912; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_810 = _out_wifireMux_T_912; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_913 = ~_out_T_1808; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_915 = _out_wifireMux_T_262 & out_frontSel_163; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_916 = _out_wifireMux_T_915 & _out_T_1894; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1147 = _out_wifireMux_T_916; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1148 = _out_wifireMux_T_916; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1149 = _out_wifireMux_T_916; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1150 = _out_wifireMux_T_916; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1151 = _out_wifireMux_T_916; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1152 = _out_wifireMux_T_916; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1153 = _out_wifireMux_T_916; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1154 = _out_wifireMux_T_916; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_917 = ~_out_T_1894; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_919 = _out_wifireMux_T_262 & out_frontSel_164; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_920 = _out_wifireMux_T_919 & _out_T_1644; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_176 = _out_wifireMux_T_920; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_177 = _out_wifireMux_T_920; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_178 = _out_wifireMux_T_920; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_179 = _out_wifireMux_T_920; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_180 = _out_wifireMux_T_920; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_181 = _out_wifireMux_T_920; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_182 = _out_wifireMux_T_920; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_183 = _out_wifireMux_T_920; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_921 = ~_out_T_1644; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_923 = _out_wifireMux_T_262 & out_frontSel_165; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_924 = _out_wifireMux_T_923 & _out_T_1686; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_344 = _out_wifireMux_T_924; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_345 = _out_wifireMux_T_924; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_346 = _out_wifireMux_T_924; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_347 = _out_wifireMux_T_924; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_348 = _out_wifireMux_T_924; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_349 = _out_wifireMux_T_924; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_350 = _out_wifireMux_T_924; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_351 = _out_wifireMux_T_924; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_925 = ~_out_T_1686; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_927 = _out_wifireMux_T_262 & out_frontSel_166; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_928 = _out_wifireMux_T_927 & _out_T_1736; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_527 = _out_wifireMux_T_928; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_528 = _out_wifireMux_T_928; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_529 = _out_wifireMux_T_928; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_530 = _out_wifireMux_T_928; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_531 = _out_wifireMux_T_928; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_532 = _out_wifireMux_T_928; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_533 = _out_wifireMux_T_928; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_534 = _out_wifireMux_T_928; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_929 = ~_out_T_1736; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_931 = _out_wifireMux_T_262 & out_frontSel_167; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_932 = _out_wifireMux_T_931 & _out_T_1806; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_795 = _out_wifireMux_T_932; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_796 = _out_wifireMux_T_932; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_797 = _out_wifireMux_T_932; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_798 = _out_wifireMux_T_932; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_799 = _out_wifireMux_T_932; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_800 = _out_wifireMux_T_932; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_801 = _out_wifireMux_T_932; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_802 = _out_wifireMux_T_932; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_933 = ~_out_T_1806; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_935 = _out_wifireMux_T_262 & out_frontSel_168; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_936 = _out_wifireMux_T_935 & _out_T_1874; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1067 = _out_wifireMux_T_936; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1068 = _out_wifireMux_T_936; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1069 = _out_wifireMux_T_936; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1070 = _out_wifireMux_T_936; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1071 = _out_wifireMux_T_936; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1072 = _out_wifireMux_T_936; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1073 = _out_wifireMux_T_936; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1074 = _out_wifireMux_T_936; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_937 = ~_out_T_1874; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_939 = _out_wifireMux_T_262 & out_frontSel_169; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_940 = _out_wifireMux_T_939 & _out_T_1702; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_402 = _out_wifireMux_T_940; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_403 = _out_wifireMux_T_940; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_404 = _out_wifireMux_T_940; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_405 = _out_wifireMux_T_940; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_406 = _out_wifireMux_T_940; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_407 = _out_wifireMux_T_940; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_408 = _out_wifireMux_T_940; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_409 = _out_wifireMux_T_940; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_941 = ~_out_T_1702; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_943 = _out_wifireMux_T_262 & out_frontSel_170; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_944 = _out_wifireMux_T_943 & _out_T_1606; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_24 = _out_wifireMux_T_944; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_25 = _out_wifireMux_T_944; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_26 = _out_wifireMux_T_944; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_27 = _out_wifireMux_T_944; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_28 = _out_wifireMux_T_944; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_29 = _out_wifireMux_T_944; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_30 = _out_wifireMux_T_944; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_31 = _out_wifireMux_T_944; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_945 = ~_out_T_1606; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_947 = _out_wifireMux_T_262 & out_frontSel_171; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_948 = _out_wifireMux_T_947 & _out_T_1854; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_987 = _out_wifireMux_T_948; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_988 = _out_wifireMux_T_948; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_989 = _out_wifireMux_T_948; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_990 = _out_wifireMux_T_948; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_991 = _out_wifireMux_T_948; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_992 = _out_wifireMux_T_948; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_993 = _out_wifireMux_T_948; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_994 = _out_wifireMux_T_948; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_949 = ~_out_T_1854; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_951 = _out_wifireMux_T_262 & out_frontSel_172; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_952 = _out_wifireMux_T_951 & _out_T_1768; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_649 = _out_wifireMux_T_952; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_650 = _out_wifireMux_T_952; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_651 = _out_wifireMux_T_952; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_652 = _out_wifireMux_T_952; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_653 = _out_wifireMux_T_952; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_654 = _out_wifireMux_T_952; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_655 = _out_wifireMux_T_952; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_656 = _out_wifireMux_T_952; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_953 = ~_out_T_1768; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_955 = _out_wifireMux_T_262 & out_frontSel_173; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_956 = _out_wifireMux_T_955 & _out_T_1718; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_459 = _out_wifireMux_T_956; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_460 = _out_wifireMux_T_956; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_461 = _out_wifireMux_T_956; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_462 = _out_wifireMux_T_956; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_463 = _out_wifireMux_T_956; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_464 = _out_wifireMux_T_956; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_465 = _out_wifireMux_T_956; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_466 = _out_wifireMux_T_956; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_957 = ~_out_T_1718; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_959 = _out_wifireMux_T_262 & out_frontSel_174; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_960 = _out_wifireMux_T_959 & _out_T_1620; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_80 = _out_wifireMux_T_960; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_81 = _out_wifireMux_T_960; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_82 = _out_wifireMux_T_960; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_83 = _out_wifireMux_T_960; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_84 = _out_wifireMux_T_960; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_85 = _out_wifireMux_T_960; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_86 = _out_wifireMux_T_960; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_87 = _out_wifireMux_T_960; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_961 = ~_out_T_1620; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_963 = _out_wifireMux_T_262 & out_frontSel_175; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_964 = _out_wifireMux_T_963 & _out_T_1832; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_899 = _out_wifireMux_T_964; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_900 = _out_wifireMux_T_964; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_901 = _out_wifireMux_T_964; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_902 = _out_wifireMux_T_964; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_903 = _out_wifireMux_T_964; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_904 = _out_wifireMux_T_964; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_905 = _out_wifireMux_T_964; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_906 = _out_wifireMux_T_964; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_965 = ~_out_T_1832; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_967 = _out_wifireMux_T_262 & out_frontSel_176; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_968 = _out_wifireMux_T_967 & _out_T_1750; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_577 = _out_wifireMux_T_968; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_578 = _out_wifireMux_T_968; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_579 = _out_wifireMux_T_968; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_580 = _out_wifireMux_T_968; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_581 = _out_wifireMux_T_968; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_582 = _out_wifireMux_T_968; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_583 = _out_wifireMux_T_968; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_584 = _out_wifireMux_T_968; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_969 = ~_out_T_1750; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_971 = _out_wifireMux_T_262 & out_frontSel_177; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_972 = _out_wifireMux_T_971 & _out_T_1826; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_875 = _out_wifireMux_T_972; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_876 = _out_wifireMux_T_972; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_877 = _out_wifireMux_T_972; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_878 = _out_wifireMux_T_972; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_879 = _out_wifireMux_T_972; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_880 = _out_wifireMux_T_972; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_881 = _out_wifireMux_T_972; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_882 = _out_wifireMux_T_972; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_973 = ~_out_T_1826; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_975 = _out_wifireMux_T_262 & out_frontSel_178; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_976 = _out_wifireMux_T_975 & _out_T_1892; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1139 = _out_wifireMux_T_976; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1140 = _out_wifireMux_T_976; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1141 = _out_wifireMux_T_976; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1142 = _out_wifireMux_T_976; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1143 = _out_wifireMux_T_976; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1144 = _out_wifireMux_T_976; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1145 = _out_wifireMux_T_976; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1146 = _out_wifireMux_T_976; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_977 = ~_out_T_1892; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_979 = _out_wifireMux_T_262 & out_frontSel_179; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_980 = _out_wifireMux_T_979 & _out_T_1646; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_184 = _out_wifireMux_T_980; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_185 = _out_wifireMux_T_980; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_186 = _out_wifireMux_T_980; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_187 = _out_wifireMux_T_980; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_188 = _out_wifireMux_T_980; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_189 = _out_wifireMux_T_980; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_190 = _out_wifireMux_T_980; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_191 = _out_wifireMux_T_980; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_981 = ~_out_T_1646; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_983 = _out_wifireMux_T_262 & out_frontSel_180; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_984 = _out_wifireMux_T_983 & _out_T_1746; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_561 = _out_wifireMux_T_984; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_562 = _out_wifireMux_T_984; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_563 = _out_wifireMux_T_984; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_564 = _out_wifireMux_T_984; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_565 = _out_wifireMux_T_984; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_566 = _out_wifireMux_T_984; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_567 = _out_wifireMux_T_984; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_568 = _out_wifireMux_T_984; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_985 = ~_out_T_1746; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_987 = _out_wifireMux_T_262 & out_frontSel_181; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_988 = _out_wifireMux_T_987 & _out_T_1762; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_625 = _out_wifireMux_T_988; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_626 = _out_wifireMux_T_988; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_627 = _out_wifireMux_T_988; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_628 = _out_wifireMux_T_988; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_629 = _out_wifireMux_T_988; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_630 = _out_wifireMux_T_988; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_631 = _out_wifireMux_T_988; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_632 = _out_wifireMux_T_988; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_989 = ~_out_T_1762; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_991 = _out_wifireMux_T_262 & out_frontSel_182; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_992 = _out_wifireMux_T_991 & _out_T_1828; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_883 = _out_wifireMux_T_992; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_884 = _out_wifireMux_T_992; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_885 = _out_wifireMux_T_992; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_886 = _out_wifireMux_T_992; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_887 = _out_wifireMux_T_992; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_888 = _out_wifireMux_T_992; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_889 = _out_wifireMux_T_992; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_890 = _out_wifireMux_T_992; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_993 = ~_out_T_1828; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_995 = _out_wifireMux_T_262 & out_frontSel_183; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_996 = _out_wifireMux_T_995 & _out_T_1872; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1059 = _out_wifireMux_T_996; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1060 = _out_wifireMux_T_996; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1061 = _out_wifireMux_T_996; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1062 = _out_wifireMux_T_996; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1063 = _out_wifireMux_T_996; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1064 = _out_wifireMux_T_996; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1065 = _out_wifireMux_T_996; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1066 = _out_wifireMux_T_996; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_997 = ~_out_T_1872; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_999 = _out_wifireMux_T_262 & out_frontSel_184; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_1000 = _out_wifireMux_T_999 & _out_T_1626; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_104 = _out_wifireMux_T_1000; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_105 = _out_wifireMux_T_1000; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_106 = _out_wifireMux_T_1000; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_107 = _out_wifireMux_T_1000; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_108 = _out_wifireMux_T_1000; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_109 = _out_wifireMux_T_1000; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_110 = _out_wifireMux_T_1000; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_111 = _out_wifireMux_T_1000; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1001 = ~_out_T_1626; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1003 = _out_wifireMux_T_262 & out_frontSel_185; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_1004 = _out_wifireMux_T_1003 & _out_T_1622; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_88 = _out_wifireMux_T_1004; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_89 = _out_wifireMux_T_1004; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_90 = _out_wifireMux_T_1004; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_91 = _out_wifireMux_T_1004; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_92 = _out_wifireMux_T_1004; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_93 = _out_wifireMux_T_1004; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_94 = _out_wifireMux_T_1004; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_95 = _out_wifireMux_T_1004; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1005 = ~_out_T_1622; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1007 = _out_wifireMux_T_262 & out_frontSel_186; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_1008 = _out_wifireMux_T_1007 & _out_T_1850; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_971 = _out_wifireMux_T_1008; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_972 = _out_wifireMux_T_1008; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_973 = _out_wifireMux_T_1008; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_974 = _out_wifireMux_T_1008; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_975 = _out_wifireMux_T_1008; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_976 = _out_wifireMux_T_1008; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_977 = _out_wifireMux_T_1008; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_978 = _out_wifireMux_T_1008; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1009 = ~_out_T_1850; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1011 = _out_wifireMux_T_262 & out_frontSel_187; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_1012 = _out_wifireMux_T_1011 & _out_T_1766; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_641 = _out_wifireMux_T_1012; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_642 = _out_wifireMux_T_1012; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_643 = _out_wifireMux_T_1012; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_644 = _out_wifireMux_T_1012; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_645 = _out_wifireMux_T_1012; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_646 = _out_wifireMux_T_1012; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_647 = _out_wifireMux_T_1012; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_648 = _out_wifireMux_T_1012; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1013 = ~_out_T_1766; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1015 = _out_wifireMux_T_262 & out_frontSel_188; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_1016 = _out_wifireMux_T_1015 & _out_T_1700; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_394 = _out_wifireMux_T_1016; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_395 = _out_wifireMux_T_1016; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_396 = _out_wifireMux_T_1016; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_397 = _out_wifireMux_T_1016; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_398 = _out_wifireMux_T_1016; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_399 = _out_wifireMux_T_1016; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_400 = _out_wifireMux_T_1016; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_401 = _out_wifireMux_T_1016; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1017 = ~_out_T_1700; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1019 = _out_wifireMux_T_262 & out_frontSel_189; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_1020 = _out_wifireMux_T_1019 & _out_T_1634; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_136 = _out_wifireMux_T_1020; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_137 = _out_wifireMux_T_1020; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_138 = _out_wifireMux_T_1020; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_139 = _out_wifireMux_T_1020; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_140 = _out_wifireMux_T_1020; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_141 = _out_wifireMux_T_1020; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_142 = _out_wifireMux_T_1020; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_143 = _out_wifireMux_T_1020; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1021 = ~_out_T_1634; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1023 = _out_wifireMux_T_262 & out_frontSel_190; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_1024 = _out_wifireMux_T_1023 & _out_T_1870; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1051 = _out_wifireMux_T_1024; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1052 = _out_wifireMux_T_1024; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1053 = _out_wifireMux_T_1024; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1054 = _out_wifireMux_T_1024; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1055 = _out_wifireMux_T_1024; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1056 = _out_wifireMux_T_1024; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1057 = _out_wifireMux_T_1024; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1058 = _out_wifireMux_T_1024; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1025 = ~_out_T_1870; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1027 = _out_wifireMux_T_262 & out_frontSel_191; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_1028 = _out_wifireMux_T_1027 & _out_T_1752; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_585 = _out_wifireMux_T_1028; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_586 = _out_wifireMux_T_1028; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_587 = _out_wifireMux_T_1028; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_588 = _out_wifireMux_T_1028; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_589 = _out_wifireMux_T_1028; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_590 = _out_wifireMux_T_1028; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_591 = _out_wifireMux_T_1028; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_592 = _out_wifireMux_T_1028; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1029 = ~_out_T_1752; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1031 = _out_wifireMux_T_262 & out_frontSel_192; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_1032 = _out_wifireMux_T_1031 & _out_T_1682; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_328 = _out_wifireMux_T_1032; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_329 = _out_wifireMux_T_1032; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_330 = _out_wifireMux_T_1032; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_331 = _out_wifireMux_T_1032; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_332 = _out_wifireMux_T_1032; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_333 = _out_wifireMux_T_1032; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_334 = _out_wifireMux_T_1032; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_335 = _out_wifireMux_T_1032; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1033 = ~_out_T_1682; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1035 = _out_wifireMux_T_262 & out_frontSel_193; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_1036 = _out_wifireMux_T_1035 & _out_T_1708; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_426 = _out_wifireMux_T_1036; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_427 = _out_wifireMux_T_1036; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_428 = _out_wifireMux_T_1036; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_429 = _out_wifireMux_T_1036; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_430 = _out_wifireMux_T_1036; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_431 = _out_wifireMux_T_1036; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_432 = _out_wifireMux_T_1036; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_433 = _out_wifireMux_T_1036; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1037 = ~_out_T_1708; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1039 = _out_wifireMux_T_262 & out_frontSel_194; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_1040 = _out_wifireMux_T_1039 & _out_T_1816; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_835 = _out_wifireMux_T_1040; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_836 = _out_wifireMux_T_1040; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_837 = _out_wifireMux_T_1040; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_838 = _out_wifireMux_T_1040; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_839 = _out_wifireMux_T_1040; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_840 = _out_wifireMux_T_1040; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_841 = _out_wifireMux_T_1040; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_842 = _out_wifireMux_T_1040; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1041 = ~_out_T_1816; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1043 = _out_wifireMux_T_262 & out_frontSel_195; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_1044 = _out_wifireMux_T_1043 & _out_T_1884; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1107 = _out_wifireMux_T_1044; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1108 = _out_wifireMux_T_1044; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1109 = _out_wifireMux_T_1044; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1110 = _out_wifireMux_T_1044; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1111 = _out_wifireMux_T_1044; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1112 = _out_wifireMux_T_1044; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1113 = _out_wifireMux_T_1044; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1114 = _out_wifireMux_T_1044; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1045 = ~_out_T_1884; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1047 = _out_wifireMux_T_262 & out_frontSel_196; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_1048 = _out_wifireMux_T_1047 & _out_T_1630; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_120 = _out_wifireMux_T_1048; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_121 = _out_wifireMux_T_1048; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_122 = _out_wifireMux_T_1048; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_123 = _out_wifireMux_T_1048; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_124 = _out_wifireMux_T_1048; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_125 = _out_wifireMux_T_1048; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_126 = _out_wifireMux_T_1048; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_127 = _out_wifireMux_T_1048; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1049 = ~_out_T_1630; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1051 = _out_wifireMux_T_262 & out_frontSel_197; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_1052 = _out_wifireMux_T_1051 & _out_T_1694; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_370 = _out_wifireMux_T_1052; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_371 = _out_wifireMux_T_1052; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_372 = _out_wifireMux_T_1052; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_373 = _out_wifireMux_T_1052; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_374 = _out_wifireMux_T_1052; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_375 = _out_wifireMux_T_1052; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_376 = _out_wifireMux_T_1052; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_377 = _out_wifireMux_T_1052; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1053 = ~_out_T_1694; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1055 = _out_wifireMux_T_262 & out_frontSel_198; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_1056 = _out_wifireMux_T_1055 & _out_T_1788; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_723 = _out_wifireMux_T_1056; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_724 = _out_wifireMux_T_1056; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_725 = _out_wifireMux_T_1056; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_726 = _out_wifireMux_T_1056; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_727 = _out_wifireMux_T_1056; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_728 = _out_wifireMux_T_1056; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_729 = _out_wifireMux_T_1056; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_730 = _out_wifireMux_T_1056; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1057 = ~_out_T_1788; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1059 = _out_wifireMux_T_262 & out_frontSel_199; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_1060 = _out_wifireMux_T_1059 & _out_T_1824; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_867 = _out_wifireMux_T_1060; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_868 = _out_wifireMux_T_1060; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_869 = _out_wifireMux_T_1060; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_870 = _out_wifireMux_T_1060; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_871 = _out_wifireMux_T_1060; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_872 = _out_wifireMux_T_1060; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_873 = _out_wifireMux_T_1060; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_874 = _out_wifireMux_T_1060; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1061 = ~_out_T_1824; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1063 = _out_wifireMux_T_262 & out_frontSel_200; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_1064 = _out_wifireMux_T_1063 & _out_T_1896; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1155 = _out_wifireMux_T_1064; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1156 = _out_wifireMux_T_1064; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1157 = _out_wifireMux_T_1064; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1158 = _out_wifireMux_T_1064; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1159 = _out_wifireMux_T_1064; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1160 = _out_wifireMux_T_1064; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1161 = _out_wifireMux_T_1064; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1162 = _out_wifireMux_T_1064; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1065 = ~_out_T_1896; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1067 = _out_wifireMux_T_262 & out_frontSel_201; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_1068 = _out_wifireMux_T_1067 & _out_T_1674; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_296 = _out_wifireMux_T_1068; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_297 = _out_wifireMux_T_1068; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_298 = _out_wifireMux_T_1068; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_299 = _out_wifireMux_T_1068; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_300 = _out_wifireMux_T_1068; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_301 = _out_wifireMux_T_1068; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_302 = _out_wifireMux_T_1068; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_303 = _out_wifireMux_T_1068; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1069 = ~_out_T_1674; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1071 = _out_wifireMux_T_262 & out_frontSel_202; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_1072 = _out_wifireMux_T_1071 & _out_T_1614; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_56 = _out_wifireMux_T_1072; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_57 = _out_wifireMux_T_1072; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_58 = _out_wifireMux_T_1072; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_59 = _out_wifireMux_T_1072; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_60 = _out_wifireMux_T_1072; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_61 = _out_wifireMux_T_1072; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_62 = _out_wifireMux_T_1072; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_63 = _out_wifireMux_T_1072; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1073 = ~_out_T_1614; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1075 = _out_wifireMux_T_262 & out_frontSel_203; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_1076 = _out_wifireMux_T_1075 & _out_T_1836; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_915 = _out_wifireMux_T_1076; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_916 = _out_wifireMux_T_1076; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_917 = _out_wifireMux_T_1076; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_918 = _out_wifireMux_T_1076; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_919 = _out_wifireMux_T_1076; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_920 = _out_wifireMux_T_1076; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_921 = _out_wifireMux_T_1076; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_922 = _out_wifireMux_T_1076; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1077 = ~_out_T_1836; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1079 = _out_wifireMux_T_262 & out_frontSel_204; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_1080 = _out_wifireMux_T_1079 & _out_T_1754; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_593 = _out_wifireMux_T_1080; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_594 = _out_wifireMux_T_1080; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_595 = _out_wifireMux_T_1080; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_596 = _out_wifireMux_T_1080; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_597 = _out_wifireMux_T_1080; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_598 = _out_wifireMux_T_1080; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_599 = _out_wifireMux_T_1080; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_600 = _out_wifireMux_T_1080; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1081 = ~_out_T_1754; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1083 = _out_wifireMux_T_262 & out_frontSel_205; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_1084 = _out_wifireMux_T_1083 & _out_T_1726; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_487 = _out_wifireMux_T_1084; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_488 = _out_wifireMux_T_1084; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_489 = _out_wifireMux_T_1084; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_490 = _out_wifireMux_T_1084; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_491 = _out_wifireMux_T_1084; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_492 = _out_wifireMux_T_1084; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_493 = _out_wifireMux_T_1084; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_494 = _out_wifireMux_T_1084; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1085 = ~_out_T_1726; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1087 = _out_wifireMux_T_262 & out_frontSel_206; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_1088 = _out_wifireMux_T_1087 & _out_T_1668; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_272 = _out_wifireMux_T_1088; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_273 = _out_wifireMux_T_1088; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_274 = _out_wifireMux_T_1088; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_275 = _out_wifireMux_T_1088; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_276 = _out_wifireMux_T_1088; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_277 = _out_wifireMux_T_1088; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_278 = _out_wifireMux_T_1088; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_279 = _out_wifireMux_T_1088; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1089 = ~_out_T_1668; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1091 = _out_wifireMux_T_262 & out_frontSel_207; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_1092 = _out_wifireMux_T_1091 & _out_T_1858; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1003 = _out_wifireMux_T_1092; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1004 = _out_wifireMux_T_1092; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1005 = _out_wifireMux_T_1092; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1006 = _out_wifireMux_T_1092; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1007 = _out_wifireMux_T_1092; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1008 = _out_wifireMux_T_1092; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1009 = _out_wifireMux_T_1092; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1010 = _out_wifireMux_T_1092; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1093 = ~_out_T_1858; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1095 = _out_wifireMux_T_262 & out_frontSel_208; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_1096 = _out_wifireMux_T_1095 & _out_T_1778; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_689 = _out_wifireMux_T_1096; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_690 = _out_wifireMux_T_1096; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_691 = _out_wifireMux_T_1096; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_692 = _out_wifireMux_T_1096; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_693 = _out_wifireMux_T_1096; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_694 = _out_wifireMux_T_1096; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_695 = _out_wifireMux_T_1096; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_696 = _out_wifireMux_T_1096; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1097 = ~_out_T_1778; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1099 = _out_wifireMux_T_262 & out_frontSel_209; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_1100 = _out_wifireMux_T_1099 & _out_T_1812; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_819 = _out_wifireMux_T_1100; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_820 = _out_wifireMux_T_1100; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_821 = _out_wifireMux_T_1100; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_822 = _out_wifireMux_T_1100; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_823 = _out_wifireMux_T_1100; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_824 = _out_wifireMux_T_1100; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_825 = _out_wifireMux_T_1100; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_826 = _out_wifireMux_T_1100; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1101 = ~_out_T_1812; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1103 = _out_wifireMux_T_262 & out_frontSel_210; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_1104 = _out_wifireMux_T_1103 & _out_T_1878; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1083 = _out_wifireMux_T_1104; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1084 = _out_wifireMux_T_1104; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1085 = _out_wifireMux_T_1104; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1086 = _out_wifireMux_T_1104; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1087 = _out_wifireMux_T_1104; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1088 = _out_wifireMux_T_1104; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1089 = _out_wifireMux_T_1104; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1090 = _out_wifireMux_T_1104; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1105 = ~_out_T_1878; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1107 = _out_wifireMux_T_262 & out_frontSel_211; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_1108 = _out_wifireMux_T_1107 & _out_T_1652; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_208 = _out_wifireMux_T_1108; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_209 = _out_wifireMux_T_1108; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_210 = _out_wifireMux_T_1108; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_211 = _out_wifireMux_T_1108; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_212 = _out_wifireMux_T_1108; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_213 = _out_wifireMux_T_1108; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_214 = _out_wifireMux_T_1108; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_215 = _out_wifireMux_T_1108; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1109 = ~_out_T_1652; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1111 = _out_wifireMux_T_262 & out_frontSel_212; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_1112 = _out_wifireMux_T_1111 & _out_T_1710; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_434 = _out_wifireMux_T_1112; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_435 = _out_wifireMux_T_1112; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_436 = _out_wifireMux_T_1112; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_437 = _out_wifireMux_T_1112; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_438 = _out_wifireMux_T_1112; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_439 = _out_wifireMux_T_1112; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_440 = _out_wifireMux_T_1112; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_441 = _out_wifireMux_T_1112; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1113 = ~_out_T_1710; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1115 = _out_wifireMux_T_262 & out_frontSel_213; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_1116 = _out_wifireMux_T_1115 & _out_T_1784; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_707 = _out_wifireMux_T_1116; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_708 = _out_wifireMux_T_1116; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_709 = _out_wifireMux_T_1116; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_710 = _out_wifireMux_T_1116; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_711 = _out_wifireMux_T_1116; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_712 = _out_wifireMux_T_1116; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_713 = _out_wifireMux_T_1116; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_714 = _out_wifireMux_T_1116; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1117 = ~_out_T_1784; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1119 = _out_wifireMux_T_262 & out_frontSel_214; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_1120 = _out_wifireMux_T_1119 & _out_T_1860; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1011 = _out_wifireMux_T_1120; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1012 = _out_wifireMux_T_1120; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1013 = _out_wifireMux_T_1120; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1014 = _out_wifireMux_T_1120; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1015 = _out_wifireMux_T_1120; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1016 = _out_wifireMux_T_1120; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1017 = _out_wifireMux_T_1120; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1018 = _out_wifireMux_T_1120; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1121 = ~_out_T_1860; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1123 = _out_wifireMux_T_262 & out_frontSel_215; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_1124 = _out_wifireMux_T_1123 & _out_T_1900; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1171 = _out_wifireMux_T_1124; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1172 = _out_wifireMux_T_1124; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1173 = _out_wifireMux_T_1124; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1174 = _out_wifireMux_T_1124; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1175 = _out_wifireMux_T_1124; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1176 = _out_wifireMux_T_1124; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1177 = _out_wifireMux_T_1124; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1178 = _out_wifireMux_T_1124; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1125 = ~_out_T_1900; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1127 = _out_wifireMux_T_262 & out_frontSel_216; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_1128 = _out_wifireMux_T_1127 & _out_T_1642; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_168 = _out_wifireMux_T_1128; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_169 = _out_wifireMux_T_1128; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_170 = _out_wifireMux_T_1128; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_171 = _out_wifireMux_T_1128; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_172 = _out_wifireMux_T_1128; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_173 = _out_wifireMux_T_1128; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_174 = _out_wifireMux_T_1128; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_175 = _out_wifireMux_T_1128; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1129 = ~_out_T_1642; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1131 = _out_wifireMux_T_262 & out_frontSel_217; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_1132 = _out_wifireMux_T_1131 & _out_T_1610; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_40 = _out_wifireMux_T_1132; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_41 = _out_wifireMux_T_1132; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_42 = _out_wifireMux_T_1132; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_43 = _out_wifireMux_T_1132; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_44 = _out_wifireMux_T_1132; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_45 = _out_wifireMux_T_1132; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_46 = _out_wifireMux_T_1132; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_47 = _out_wifireMux_T_1132; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1133 = ~_out_T_1610; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1135 = _out_wifireMux_T_262 & out_frontSel_218; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_1136 = _out_wifireMux_T_1135 & _out_T_1838; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_923 = _out_wifireMux_T_1136; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_924 = _out_wifireMux_T_1136; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_925 = _out_wifireMux_T_1136; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_926 = _out_wifireMux_T_1136; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_927 = _out_wifireMux_T_1136; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_928 = _out_wifireMux_T_1136; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_929 = _out_wifireMux_T_1136; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_930 = _out_wifireMux_T_1136; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1137 = ~_out_T_1838; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1139 = _out_wifireMux_T_262 & out_frontSel_219; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_1140 = _out_wifireMux_T_1139 & _out_T_1772; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_665 = _out_wifireMux_T_1140; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_666 = _out_wifireMux_T_1140; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_667 = _out_wifireMux_T_1140; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_668 = _out_wifireMux_T_1140; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_669 = _out_wifireMux_T_1140; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_670 = _out_wifireMux_T_1140; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_671 = _out_wifireMux_T_1140; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_672 = _out_wifireMux_T_1140; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1141 = ~_out_T_1772; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1143 = _out_wifireMux_T_262 & out_frontSel_220; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_1144 = _out_wifireMux_T_1143 & _out_T_1676; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_304 = _out_wifireMux_T_1144; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_305 = _out_wifireMux_T_1144; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_306 = _out_wifireMux_T_1144; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_307 = _out_wifireMux_T_1144; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_308 = _out_wifireMux_T_1144; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_309 = _out_wifireMux_T_1144; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_310 = _out_wifireMux_T_1144; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_311 = _out_wifireMux_T_1144; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1145 = ~_out_T_1676; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1147 = _out_wifireMux_T_262 & out_frontSel_221; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_1148 = _out_wifireMux_T_1147 & _out_T_1658; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_232 = _out_wifireMux_T_1148; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_233 = _out_wifireMux_T_1148; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_234 = _out_wifireMux_T_1148; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_235 = _out_wifireMux_T_1148; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_236 = _out_wifireMux_T_1148; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_237 = _out_wifireMux_T_1148; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_238 = _out_wifireMux_T_1148; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_239 = _out_wifireMux_T_1148; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1149 = ~_out_T_1658; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1151 = _out_wifireMux_T_262 & out_frontSel_222; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_1152 = _out_wifireMux_T_1151 & _out_T_1902; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1179 = _out_wifireMux_T_1152; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1180 = _out_wifireMux_T_1152; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1181 = _out_wifireMux_T_1152; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1182 = _out_wifireMux_T_1152; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1183 = _out_wifireMux_T_1152; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1184 = _out_wifireMux_T_1152; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1185 = _out_wifireMux_T_1152; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1186 = _out_wifireMux_T_1152; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1153 = ~_out_T_1902; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1155 = _out_wifireMux_T_262 & out_frontSel_223; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_1156 = _out_wifireMux_T_1155 & _out_T_1798; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_763 = _out_wifireMux_T_1156; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_764 = _out_wifireMux_T_1156; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_765 = _out_wifireMux_T_1156; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_766 = _out_wifireMux_T_1156; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_767 = _out_wifireMux_T_1156; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_768 = _out_wifireMux_T_1156; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_769 = _out_wifireMux_T_1156; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_770 = _out_wifireMux_T_1156; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1157 = ~_out_T_1798; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1159 = _out_wifireMux_T_262 & out_frontSel_224; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_1160 = _out_wifireMux_T_1159 & _out_T_1696; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_378 = _out_wifireMux_T_1160; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_379 = _out_wifireMux_T_1160; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_380 = _out_wifireMux_T_1160; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_381 = _out_wifireMux_T_1160; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_382 = _out_wifireMux_T_1160; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_383 = _out_wifireMux_T_1160; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_384 = _out_wifireMux_T_1160; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_385 = _out_wifireMux_T_1160; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1161 = ~_out_T_1696; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1163 = _out_wifireMux_T_262 & out_frontSel_225; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_1164 = _out_wifireMux_T_1163 & _out_T_1706; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_418 = _out_wifireMux_T_1164; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_419 = _out_wifireMux_T_1164; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_420 = _out_wifireMux_T_1164; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_421 = _out_wifireMux_T_1164; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_422 = _out_wifireMux_T_1164; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_423 = _out_wifireMux_T_1164; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_424 = _out_wifireMux_T_1164; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_425 = _out_wifireMux_T_1164; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1165 = ~_out_T_1706; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1167 = _out_wifireMux_T_262 & out_frontSel_226; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_1168 = _out_wifireMux_T_1167 & _out_T_1802; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_779 = _out_wifireMux_T_1168; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_780 = _out_wifireMux_T_1168; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_781 = _out_wifireMux_T_1168; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_782 = _out_wifireMux_T_1168; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_783 = _out_wifireMux_T_1168; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_784 = _out_wifireMux_T_1168; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_785 = _out_wifireMux_T_1168; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_786 = _out_wifireMux_T_1168; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1169 = ~_out_T_1802; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1171 = _out_wifireMux_T_262 & out_frontSel_227; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_1172 = _out_wifireMux_T_1171 & _out_T_1908; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1203 = _out_wifireMux_T_1172; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1204 = _out_wifireMux_T_1172; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1205 = _out_wifireMux_T_1172; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1206 = _out_wifireMux_T_1172; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1207 = _out_wifireMux_T_1172; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1208 = _out_wifireMux_T_1172; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1209 = _out_wifireMux_T_1172; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1210 = _out_wifireMux_T_1172; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1173 = ~_out_T_1908; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1175 = _out_wifireMux_T_262 & out_frontSel_228; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_1176 = _out_wifireMux_T_1175 & _out_T_1638; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_152 = _out_wifireMux_T_1176; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_153 = _out_wifireMux_T_1176; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_154 = _out_wifireMux_T_1176; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_155 = _out_wifireMux_T_1176; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_156 = _out_wifireMux_T_1176; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_157 = _out_wifireMux_T_1176; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_158 = _out_wifireMux_T_1176; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_159 = _out_wifireMux_T_1176; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1177 = ~_out_T_1638; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1179 = _out_wifireMux_T_262 & out_frontSel_229; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_1180 = _out_wifireMux_T_1179 & _out_T_1690; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_354 = _out_wifireMux_T_1180; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_355 = _out_wifireMux_T_1180; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_356 = _out_wifireMux_T_1180; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_357 = _out_wifireMux_T_1180; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_358 = _out_wifireMux_T_1180; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_359 = _out_wifireMux_T_1180; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_360 = _out_wifireMux_T_1180; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_361 = _out_wifireMux_T_1180; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1181 = ~_out_T_1690; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1183 = _out_wifireMux_T_262 & out_frontSel_230; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_1184 = _out_wifireMux_T_1183 & _out_T_1774; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_673 = _out_wifireMux_T_1184; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_674 = _out_wifireMux_T_1184; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_675 = _out_wifireMux_T_1184; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_676 = _out_wifireMux_T_1184; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_677 = _out_wifireMux_T_1184; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_678 = _out_wifireMux_T_1184; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_679 = _out_wifireMux_T_1184; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_680 = _out_wifireMux_T_1184; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1185 = ~_out_T_1774; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1187 = _out_wifireMux_T_262 & out_frontSel_231; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_1188 = _out_wifireMux_T_1187 & _out_T_1844; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_947 = _out_wifireMux_T_1188; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_948 = _out_wifireMux_T_1188; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_949 = _out_wifireMux_T_1188; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_950 = _out_wifireMux_T_1188; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_951 = _out_wifireMux_T_1188; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_952 = _out_wifireMux_T_1188; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_953 = _out_wifireMux_T_1188; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_954 = _out_wifireMux_T_1188; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1189 = ~_out_T_1844; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1191 = _out_wifireMux_T_262 & out_frontSel_232; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_1192 = _out_wifireMux_T_1191 & _out_T_1904; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1187 = _out_wifireMux_T_1192; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1188 = _out_wifireMux_T_1192; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1189 = _out_wifireMux_T_1192; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1190 = _out_wifireMux_T_1192; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1191 = _out_wifireMux_T_1192; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1192 = _out_wifireMux_T_1192; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1193 = _out_wifireMux_T_1192; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1194 = _out_wifireMux_T_1192; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1193 = ~_out_T_1904; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1195 = _out_wifireMux_T_262 & out_frontSel_233; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_1196 = _out_wifireMux_T_1195 & _out_T_1670; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_280 = _out_wifireMux_T_1196; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_281 = _out_wifireMux_T_1196; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_282 = _out_wifireMux_T_1196; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_283 = _out_wifireMux_T_1196; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_284 = _out_wifireMux_T_1196; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_285 = _out_wifireMux_T_1196; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_286 = _out_wifireMux_T_1196; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_287 = _out_wifireMux_T_1196; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1197 = ~_out_T_1670; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1199 = _out_wifireMux_T_262 & out_frontSel_234; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_1200 = _out_wifireMux_T_1199 & _out_T_1604; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_16 = _out_wifireMux_T_1200; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_17 = _out_wifireMux_T_1200; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_18 = _out_wifireMux_T_1200; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_19 = _out_wifireMux_T_1200; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_20 = _out_wifireMux_T_1200; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_21 = _out_wifireMux_T_1200; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_22 = _out_wifireMux_T_1200; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_23 = _out_wifireMux_T_1200; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1201 = ~_out_T_1604; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1203 = _out_wifireMux_T_262 & out_frontSel_235; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_1204 = _out_wifireMux_T_1203 & _out_T_1862; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1019 = _out_wifireMux_T_1204; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1020 = _out_wifireMux_T_1204; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1021 = _out_wifireMux_T_1204; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1022 = _out_wifireMux_T_1204; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1023 = _out_wifireMux_T_1204; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1024 = _out_wifireMux_T_1204; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1025 = _out_wifireMux_T_1204; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1026 = _out_wifireMux_T_1204; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1205 = ~_out_T_1862; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1207 = _out_wifireMux_T_262 & out_frontSel_236; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_1208 = _out_wifireMux_T_1207 & _out_T_1760; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_617 = _out_wifireMux_T_1208; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_618 = _out_wifireMux_T_1208; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_619 = _out_wifireMux_T_1208; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_620 = _out_wifireMux_T_1208; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_621 = _out_wifireMux_T_1208; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_622 = _out_wifireMux_T_1208; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_623 = _out_wifireMux_T_1208; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_624 = _out_wifireMux_T_1208; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1209 = ~_out_T_1760; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1211 = _out_wifireMux_T_262 & out_frontSel_237; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_1212 = _out_wifireMux_T_1211 & _out_T_1730; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_503 = _out_wifireMux_T_1212; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_504 = _out_wifireMux_T_1212; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_505 = _out_wifireMux_T_1212; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_506 = _out_wifireMux_T_1212; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_507 = _out_wifireMux_T_1212; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_508 = _out_wifireMux_T_1212; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_509 = _out_wifireMux_T_1212; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_510 = _out_wifireMux_T_1212; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1213 = ~_out_T_1730; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1215 = _out_wifireMux_T_262 & out_frontSel_238; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_1216 = _out_wifireMux_T_1215 & _out_T_1650; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_200 = _out_wifireMux_T_1216; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_201 = _out_wifireMux_T_1216; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_202 = _out_wifireMux_T_1216; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_203 = _out_wifireMux_T_1216; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_204 = _out_wifireMux_T_1216; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_205 = _out_wifireMux_T_1216; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_206 = _out_wifireMux_T_1216; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_207 = _out_wifireMux_T_1216; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1217 = ~_out_T_1650; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1219 = _out_wifireMux_T_262 & out_frontSel_239; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_1220 = _out_wifireMux_T_1219 & _out_T_1886; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1115 = _out_wifireMux_T_1220; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1116 = _out_wifireMux_T_1220; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1117 = _out_wifireMux_T_1220; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1118 = _out_wifireMux_T_1220; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1119 = _out_wifireMux_T_1220; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1120 = _out_wifireMux_T_1220; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1121 = _out_wifireMux_T_1220; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1122 = _out_wifireMux_T_1220; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1221 = ~_out_T_1886; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1223 = _out_wifireMux_T_262 & out_frontSel_240; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_1224 = _out_wifireMux_T_1223 & _out_T_1792; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_739 = _out_wifireMux_T_1224; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_740 = _out_wifireMux_T_1224; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_741 = _out_wifireMux_T_1224; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_742 = _out_wifireMux_T_1224; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_743 = _out_wifireMux_T_1224; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_744 = _out_wifireMux_T_1224; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_745 = _out_wifireMux_T_1224; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_746 = _out_wifireMux_T_1224; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1225 = ~_out_T_1792; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1227 = _out_wifireMux_T_262 & out_frontSel_241; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_1228 = _out_wifireMux_T_1227 & _out_T_1804; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_787 = _out_wifireMux_T_1228; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_788 = _out_wifireMux_T_1228; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_789 = _out_wifireMux_T_1228; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_790 = _out_wifireMux_T_1228; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_791 = _out_wifireMux_T_1228; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_792 = _out_wifireMux_T_1228; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_793 = _out_wifireMux_T_1228; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_794 = _out_wifireMux_T_1228; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1229 = ~_out_T_1804; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1231 = _out_wifireMux_T_262 & out_frontSel_242; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_1232 = _out_wifireMux_T_1231 & _out_T_1888; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1123 = _out_wifireMux_T_1232; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1124 = _out_wifireMux_T_1232; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1125 = _out_wifireMux_T_1232; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1126 = _out_wifireMux_T_1232; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1127 = _out_wifireMux_T_1232; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1128 = _out_wifireMux_T_1232; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1129 = _out_wifireMux_T_1232; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1130 = _out_wifireMux_T_1232; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1233 = ~_out_T_1888; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1235 = _out_wifireMux_T_262 & out_frontSel_243; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_1236 = _out_wifireMux_T_1235 & _out_T_1664; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_256 = _out_wifireMux_T_1236; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_257 = _out_wifireMux_T_1236; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_258 = _out_wifireMux_T_1236; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_259 = _out_wifireMux_T_1236; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_260 = _out_wifireMux_T_1236; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_261 = _out_wifireMux_T_1236; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_262 = _out_wifireMux_T_1236; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_263 = _out_wifireMux_T_1236; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1237 = ~_out_T_1664; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1239 = _out_wifireMux_T_262 & out_frontSel_244; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_1240 = _out_wifireMux_T_1239 & _out_T_1734; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_519 = _out_wifireMux_T_1240; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_520 = _out_wifireMux_T_1240; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_521 = _out_wifireMux_T_1240; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_522 = _out_wifireMux_T_1240; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_523 = _out_wifireMux_T_1240; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_524 = _out_wifireMux_T_1240; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_525 = _out_wifireMux_T_1240; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_526 = _out_wifireMux_T_1240; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1241 = ~_out_T_1734; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1243 = _out_wifireMux_T_262 & out_frontSel_245; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_1244 = _out_wifireMux_T_1243 & _out_T_1776; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_681 = _out_wifireMux_T_1244; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_682 = _out_wifireMux_T_1244; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_683 = _out_wifireMux_T_1244; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_684 = _out_wifireMux_T_1244; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_685 = _out_wifireMux_T_1244; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_686 = _out_wifireMux_T_1244; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_687 = _out_wifireMux_T_1244; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_688 = _out_wifireMux_T_1244; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1245 = ~_out_T_1776; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1247 = _out_wifireMux_T_262 & out_frontSel_246; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_1248 = _out_wifireMux_T_1247 & _out_T_1864; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1027 = _out_wifireMux_T_1248; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1028 = _out_wifireMux_T_1248; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1029 = _out_wifireMux_T_1248; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1030 = _out_wifireMux_T_1248; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1031 = _out_wifireMux_T_1248; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1032 = _out_wifireMux_T_1248; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1033 = _out_wifireMux_T_1248; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1034 = _out_wifireMux_T_1248; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1249 = ~_out_T_1864; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1251 = _out_wifireMux_T_262 & out_frontSel_247; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_1252 = _out_wifireMux_T_1251 & _out_T_1612; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_48 = _out_wifireMux_T_1252; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_49 = _out_wifireMux_T_1252; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_50 = _out_wifireMux_T_1252; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_51 = _out_wifireMux_T_1252; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_52 = _out_wifireMux_T_1252; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_53 = _out_wifireMux_T_1252; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_54 = _out_wifireMux_T_1252; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_55 = _out_wifireMux_T_1252; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1253 = ~_out_T_1612; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1255 = _out_wifireMux_T_262 & out_frontSel_248; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_1256 = _out_wifireMux_T_1255 & _out_T_1672; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_288 = _out_wifireMux_T_1256; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_289 = _out_wifireMux_T_1256; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_290 = _out_wifireMux_T_1256; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_291 = _out_wifireMux_T_1256; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_292 = _out_wifireMux_T_1256; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_293 = _out_wifireMux_T_1256; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_294 = _out_wifireMux_T_1256; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_295 = _out_wifireMux_T_1256; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1257 = ~_out_T_1672; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1259 = _out_wifireMux_T_262 & out_frontSel_249; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_1260 = _out_wifireMux_T_1259 & _out_T_1602; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_8 = _out_wifireMux_T_1260; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_9 = _out_wifireMux_T_1260; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_10 = _out_wifireMux_T_1260; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_11 = _out_wifireMux_T_1260; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_12 = _out_wifireMux_T_1260; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_13 = _out_wifireMux_T_1260; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_14 = _out_wifireMux_T_1260; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_15 = _out_wifireMux_T_1260; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1261 = ~_out_T_1602; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1263 = _out_wifireMux_T_262 & out_frontSel_250; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_1264 = _out_wifireMux_T_1263 & _out_T_1842; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_939 = _out_wifireMux_T_1264; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_940 = _out_wifireMux_T_1264; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_941 = _out_wifireMux_T_1264; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_942 = _out_wifireMux_T_1264; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_943 = _out_wifireMux_T_1264; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_944 = _out_wifireMux_T_1264; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_945 = _out_wifireMux_T_1264; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_946 = _out_wifireMux_T_1264; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1265 = ~_out_T_1842; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1267 = _out_wifireMux_T_262 & out_frontSel_251; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_1268 = _out_wifireMux_T_1267 & _out_T_1794; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_747 = _out_wifireMux_T_1268; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_748 = _out_wifireMux_T_1268; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_749 = _out_wifireMux_T_1268; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_750 = _out_wifireMux_T_1268; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_751 = _out_wifireMux_T_1268; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_752 = _out_wifireMux_T_1268; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_753 = _out_wifireMux_T_1268; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_754 = _out_wifireMux_T_1268; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1269 = ~_out_T_1794; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1271 = _out_wifireMux_T_262 & out_frontSel_252; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_1272 = _out_wifireMux_T_1271 & _out_T_1692; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_362 = _out_wifireMux_T_1272; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_363 = _out_wifireMux_T_1272; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_364 = _out_wifireMux_T_1272; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_365 = _out_wifireMux_T_1272; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_366 = _out_wifireMux_T_1272; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_367 = _out_wifireMux_T_1272; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_368 = _out_wifireMux_T_1272; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_369 = _out_wifireMux_T_1272; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1273 = ~_out_T_1692; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1275 = _out_wifireMux_T_262 & out_frontSel_253; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_1276 = _out_wifireMux_T_1275 & _out_T_1654; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_216 = _out_wifireMux_T_1276; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_217 = _out_wifireMux_T_1276; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_218 = _out_wifireMux_T_1276; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_219 = _out_wifireMux_T_1276; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_220 = _out_wifireMux_T_1276; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_221 = _out_wifireMux_T_1276; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_222 = _out_wifireMux_T_1276; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_223 = _out_wifireMux_T_1276; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1277 = ~_out_T_1654; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1279 = _out_wifireMux_T_262 & out_frontSel_254; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_1280 = _out_wifireMux_T_1279 & _out_T_1906; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1195 = _out_wifireMux_T_1280; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1196 = _out_wifireMux_T_1280; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1197 = _out_wifireMux_T_1280; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1198 = _out_wifireMux_T_1280; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1199 = _out_wifireMux_T_1280; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1200 = _out_wifireMux_T_1280; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1201 = _out_wifireMux_T_1280; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1202 = _out_wifireMux_T_1280; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1281 = ~_out_T_1906; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1283 = _out_wifireMux_T_262 & out_frontSel_255; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_1284 = _out_wifireMux_T_1283 & _out_T_1810; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_811 = _out_wifireMux_T_1284; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_812 = _out_wifireMux_T_1284; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_813 = _out_wifireMux_T_1284; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_814 = _out_wifireMux_T_1284; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_815 = _out_wifireMux_T_1284; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_816 = _out_wifireMux_T_1284; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_817 = _out_wifireMux_T_1284; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_818 = _out_wifireMux_T_1284; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1285 = ~_out_T_1810; // @[RegisterRouter.scala:87:24]
wire _GEN_23 = out_front_1_valid & out_1_ready; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_259; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_259 = _GEN_23; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_260; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_260 = _GEN_23; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_260 = _out_rofireMux_T_259 & out_front_1_bits_read; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_261 = _out_rofireMux_T_260 & out_backSel_0_1; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_262 = _out_rofireMux_T_261 & _out_T_1717; // @[RegisterRouter.scala:87:24]
assign out_roready_1_451 = _out_rofireMux_T_262; // @[RegisterRouter.scala:87:24]
assign out_roready_1_452 = _out_rofireMux_T_262; // @[RegisterRouter.scala:87:24]
assign out_roready_1_453 = _out_rofireMux_T_262; // @[RegisterRouter.scala:87:24]
assign out_roready_1_454 = _out_rofireMux_T_262; // @[RegisterRouter.scala:87:24]
assign out_roready_1_455 = _out_rofireMux_T_262; // @[RegisterRouter.scala:87:24]
assign out_roready_1_456 = _out_rofireMux_T_262; // @[RegisterRouter.scala:87:24]
assign out_roready_1_457 = _out_rofireMux_T_262; // @[RegisterRouter.scala:87:24]
assign out_roready_1_458 = _out_rofireMux_T_262; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_263 = ~_out_T_1717; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_265 = _out_rofireMux_T_260 & out_backSel_1_1; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_266 = _out_rofireMux_T_265 & _out_T_1625; // @[RegisterRouter.scala:87:24]
assign out_roready_1_96 = _out_rofireMux_T_266; // @[RegisterRouter.scala:87:24]
assign out_roready_1_97 = _out_rofireMux_T_266; // @[RegisterRouter.scala:87:24]
assign out_roready_1_98 = _out_rofireMux_T_266; // @[RegisterRouter.scala:87:24]
assign out_roready_1_99 = _out_rofireMux_T_266; // @[RegisterRouter.scala:87:24]
assign out_roready_1_100 = _out_rofireMux_T_266; // @[RegisterRouter.scala:87:24]
assign out_roready_1_101 = _out_rofireMux_T_266; // @[RegisterRouter.scala:87:24]
assign out_roready_1_102 = _out_rofireMux_T_266; // @[RegisterRouter.scala:87:24]
assign out_roready_1_103 = _out_rofireMux_T_266; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_267 = ~_out_T_1625; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_269 = _out_rofireMux_T_260 & out_backSel_2_1; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_270 = _out_rofireMux_T_269 & _out_T_1847; // @[RegisterRouter.scala:87:24]
assign out_roready_1_955 = _out_rofireMux_T_270; // @[RegisterRouter.scala:87:24]
assign out_roready_1_956 = _out_rofireMux_T_270; // @[RegisterRouter.scala:87:24]
assign out_roready_1_957 = _out_rofireMux_T_270; // @[RegisterRouter.scala:87:24]
assign out_roready_1_958 = _out_rofireMux_T_270; // @[RegisterRouter.scala:87:24]
assign out_roready_1_959 = _out_rofireMux_T_270; // @[RegisterRouter.scala:87:24]
assign out_roready_1_960 = _out_rofireMux_T_270; // @[RegisterRouter.scala:87:24]
assign out_roready_1_961 = _out_rofireMux_T_270; // @[RegisterRouter.scala:87:24]
assign out_roready_1_962 = _out_rofireMux_T_270; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_271 = ~_out_T_1847; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_273 = _out_rofireMux_T_260 & out_backSel_3_1; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_274 = _out_rofireMux_T_273 & _out_T_1757; // @[RegisterRouter.scala:87:24]
assign out_roready_1_601 = _out_rofireMux_T_274; // @[RegisterRouter.scala:87:24]
assign out_roready_1_602 = _out_rofireMux_T_274; // @[RegisterRouter.scala:87:24]
assign out_roready_1_603 = _out_rofireMux_T_274; // @[RegisterRouter.scala:87:24]
assign out_roready_1_604 = _out_rofireMux_T_274; // @[RegisterRouter.scala:87:24]
assign out_roready_1_605 = _out_rofireMux_T_274; // @[RegisterRouter.scala:87:24]
assign out_roready_1_606 = _out_rofireMux_T_274; // @[RegisterRouter.scala:87:24]
assign out_roready_1_607 = _out_rofireMux_T_274; // @[RegisterRouter.scala:87:24]
assign out_roready_1_608 = _out_rofireMux_T_274; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_275 = ~_out_T_1757; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_277 = _out_rofireMux_T_260 & out_backSel_4_1; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_278 = _out_rofireMux_T_277 & _out_T_1679; // @[RegisterRouter.scala:87:24]
assign out_roready_1_312 = _out_rofireMux_T_278; // @[RegisterRouter.scala:87:24]
assign out_roready_1_313 = _out_rofireMux_T_278; // @[RegisterRouter.scala:87:24]
assign out_roready_1_314 = _out_rofireMux_T_278; // @[RegisterRouter.scala:87:24]
assign out_roready_1_315 = _out_rofireMux_T_278; // @[RegisterRouter.scala:87:24]
assign out_roready_1_316 = _out_rofireMux_T_278; // @[RegisterRouter.scala:87:24]
assign out_roready_1_317 = _out_rofireMux_T_278; // @[RegisterRouter.scala:87:24]
assign out_roready_1_318 = _out_rofireMux_T_278; // @[RegisterRouter.scala:87:24]
assign out_roready_1_319 = _out_rofireMux_T_278; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_279 = ~_out_T_1679; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_281 = _out_rofireMux_T_260 & out_backSel_5_1; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_282 = _out_rofireMux_T_281 & _out_T_1641; // @[RegisterRouter.scala:87:24]
assign out_roready_1_160 = _out_rofireMux_T_282; // @[RegisterRouter.scala:87:24]
assign out_roready_1_161 = _out_rofireMux_T_282; // @[RegisterRouter.scala:87:24]
assign out_roready_1_162 = _out_rofireMux_T_282; // @[RegisterRouter.scala:87:24]
assign out_roready_1_163 = _out_rofireMux_T_282; // @[RegisterRouter.scala:87:24]
assign out_roready_1_164 = _out_rofireMux_T_282; // @[RegisterRouter.scala:87:24]
assign out_roready_1_165 = _out_rofireMux_T_282; // @[RegisterRouter.scala:87:24]
assign out_roready_1_166 = _out_rofireMux_T_282; // @[RegisterRouter.scala:87:24]
assign out_roready_1_167 = _out_rofireMux_T_282; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_283 = ~_out_T_1641; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_285 = _out_rofireMux_T_260 & out_backSel_6_1; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_286 = _out_rofireMux_T_285 & _out_T_1877; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1075 = _out_rofireMux_T_286; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1076 = _out_rofireMux_T_286; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1077 = _out_rofireMux_T_286; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1078 = _out_rofireMux_T_286; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1079 = _out_rofireMux_T_286; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1080 = _out_rofireMux_T_286; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1081 = _out_rofireMux_T_286; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1082 = _out_rofireMux_T_286; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_287 = ~_out_T_1877; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_289 = _out_rofireMux_T_260 & out_backSel_7_1; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_290 = _out_rofireMux_T_289 & _out_T_1823; // @[RegisterRouter.scala:87:24]
assign out_roready_1_859 = _out_rofireMux_T_290; // @[RegisterRouter.scala:87:24]
assign out_roready_1_860 = _out_rofireMux_T_290; // @[RegisterRouter.scala:87:24]
assign out_roready_1_861 = _out_rofireMux_T_290; // @[RegisterRouter.scala:87:24]
assign out_roready_1_862 = _out_rofireMux_T_290; // @[RegisterRouter.scala:87:24]
assign out_roready_1_863 = _out_rofireMux_T_290; // @[RegisterRouter.scala:87:24]
assign out_roready_1_864 = _out_rofireMux_T_290; // @[RegisterRouter.scala:87:24]
assign out_roready_1_865 = _out_rofireMux_T_290; // @[RegisterRouter.scala:87:24]
assign out_roready_1_866 = _out_rofireMux_T_290; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_291 = ~_out_T_1823; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_293 = _out_rofireMux_T_260 & out_backSel_8_1; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_294 = _out_rofireMux_T_293 & _out_T_1743; // @[RegisterRouter.scala:87:24]
assign out_roready_1_545 = _out_rofireMux_T_294; // @[RegisterRouter.scala:87:24]
assign out_roready_1_546 = _out_rofireMux_T_294; // @[RegisterRouter.scala:87:24]
assign out_roready_1_547 = _out_rofireMux_T_294; // @[RegisterRouter.scala:87:24]
assign out_roready_1_548 = _out_rofireMux_T_294; // @[RegisterRouter.scala:87:24]
assign out_roready_1_549 = _out_rofireMux_T_294; // @[RegisterRouter.scala:87:24]
assign out_roready_1_550 = _out_rofireMux_T_294; // @[RegisterRouter.scala:87:24]
assign out_roready_1_551 = _out_rofireMux_T_294; // @[RegisterRouter.scala:87:24]
assign out_roready_1_552 = _out_rofireMux_T_294; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_295 = ~_out_T_1743; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_297 = _out_rofireMux_T_260 & out_backSel_9_1; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_298 = _out_rofireMux_T_297 & _out_T_1667; // @[RegisterRouter.scala:87:24]
assign out_roready_1_264 = _out_rofireMux_T_298; // @[RegisterRouter.scala:87:24]
assign out_roready_1_265 = _out_rofireMux_T_298; // @[RegisterRouter.scala:87:24]
assign out_roready_1_266 = _out_rofireMux_T_298; // @[RegisterRouter.scala:87:24]
assign out_roready_1_267 = _out_rofireMux_T_298; // @[RegisterRouter.scala:87:24]
assign out_roready_1_268 = _out_rofireMux_T_298; // @[RegisterRouter.scala:87:24]
assign out_roready_1_269 = _out_rofireMux_T_298; // @[RegisterRouter.scala:87:24]
assign out_roready_1_270 = _out_rofireMux_T_298; // @[RegisterRouter.scala:87:24]
assign out_roready_1_271 = _out_rofireMux_T_298; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_299 = ~_out_T_1667; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_301 = _out_rofireMux_T_260 & out_backSel_10_1; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_302 = _out_rofireMux_T_301 & _out_T_1725; // @[RegisterRouter.scala:87:24]
assign out_roready_1_483 = _out_rofireMux_T_302; // @[RegisterRouter.scala:87:24]
assign out_roready_1_484 = _out_rofireMux_T_302; // @[RegisterRouter.scala:87:24]
assign out_roready_1_485 = _out_rofireMux_T_302; // @[RegisterRouter.scala:87:24]
assign out_roready_1_486 = _out_rofireMux_T_302; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_303 = ~_out_T_1725; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_305 = _out_rofireMux_T_260 & out_backSel_11_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_306 = _out_rofireMux_T_305; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_309 = _out_rofireMux_T_260 & out_backSel_12_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_310 = _out_rofireMux_T_309; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_313 = _out_rofireMux_T_260 & out_backSel_13_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_314 = _out_rofireMux_T_313; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_317 = _out_rofireMux_T_260 & out_backSel_14_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_318 = _out_rofireMux_T_317; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_321 = _out_rofireMux_T_260 & out_backSel_15_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_322 = _out_rofireMux_T_321; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_325 = _out_rofireMux_T_260 & out_backSel_16_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_326 = _out_rofireMux_T_325; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_329 = _out_rofireMux_T_260 & out_backSel_17_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_330 = _out_rofireMux_T_329; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_333 = _out_rofireMux_T_260 & out_backSel_18_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_334 = _out_rofireMux_T_333; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_337 = _out_rofireMux_T_260 & out_backSel_19_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_338 = _out_rofireMux_T_337; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_341 = _out_rofireMux_T_260 & out_backSel_20_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_342 = _out_rofireMux_T_341; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_345 = _out_rofireMux_T_260 & out_backSel_21_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_346 = _out_rofireMux_T_345; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_349 = _out_rofireMux_T_260 & out_backSel_22_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_350 = _out_rofireMux_T_349; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_353 = _out_rofireMux_T_260 & out_backSel_23_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_354 = _out_rofireMux_T_353; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_357 = _out_rofireMux_T_260 & out_backSel_24_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_358 = _out_rofireMux_T_357; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_361 = _out_rofireMux_T_260 & out_backSel_25_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_362 = _out_rofireMux_T_361; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_365 = _out_rofireMux_T_260 & out_backSel_26_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_366 = _out_rofireMux_T_365; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_369 = _out_rofireMux_T_260 & out_backSel_27_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_370 = _out_rofireMux_T_369; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_373 = _out_rofireMux_T_260 & out_backSel_28_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_374 = _out_rofireMux_T_373; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_377 = _out_rofireMux_T_260 & out_backSel_29_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_378 = _out_rofireMux_T_377; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_381 = _out_rofireMux_T_260 & out_backSel_30_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_382 = _out_rofireMux_T_381; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_385 = _out_rofireMux_T_260 & out_backSel_31_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_386 = _out_rofireMux_T_385; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_389 = _out_rofireMux_T_260 & out_backSel_32_1; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_390 = _out_rofireMux_T_389 & _out_T_1739; // @[RegisterRouter.scala:87:24]
assign out_roready_1_535 = _out_rofireMux_T_390; // @[RegisterRouter.scala:87:24]
assign out_roready_1_536 = _out_rofireMux_T_390; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_391 = ~_out_T_1739; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_393 = _out_rofireMux_T_260 & out_backSel_33_1; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_394 = _out_rofireMux_T_393 & _out_T_1689; // @[RegisterRouter.scala:87:24]
assign out_roready_1_352 = _out_rofireMux_T_394; // @[RegisterRouter.scala:87:24]
assign out_roready_1_353 = _out_rofireMux_T_394; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_395 = ~_out_T_1689; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_397 = _out_rofireMux_T_260 & out_backSel_34_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_398 = _out_rofireMux_T_397; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_401 = _out_rofireMux_T_260 & out_backSel_35_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_402 = _out_rofireMux_T_401; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_405 = _out_rofireMux_T_260 & out_backSel_36_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_406 = _out_rofireMux_T_405; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_409 = _out_rofireMux_T_260 & out_backSel_37_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_410 = _out_rofireMux_T_409; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_413 = _out_rofireMux_T_260 & out_backSel_38_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_414 = _out_rofireMux_T_413; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_417 = _out_rofireMux_T_260 & out_backSel_39_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_418 = _out_rofireMux_T_417; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_421 = _out_rofireMux_T_260 & out_backSel_40_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_422 = _out_rofireMux_T_421; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_425 = _out_rofireMux_T_260 & out_backSel_41_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_426 = _out_rofireMux_T_425; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_429 = _out_rofireMux_T_260 & out_backSel_42_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_430 = _out_rofireMux_T_429; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_433 = _out_rofireMux_T_260 & out_backSel_43_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_434 = _out_rofireMux_T_433; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_437 = _out_rofireMux_T_260 & out_backSel_44_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_438 = _out_rofireMux_T_437; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_441 = _out_rofireMux_T_260 & out_backSel_45_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_442 = _out_rofireMux_T_441; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_445 = _out_rofireMux_T_260 & out_backSel_46_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_446 = _out_rofireMux_T_445; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_449 = _out_rofireMux_T_260 & out_backSel_47_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_450 = _out_rofireMux_T_449; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_453 = _out_rofireMux_T_260 & out_backSel_48_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_454 = _out_rofireMux_T_453; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_457 = _out_rofireMux_T_260 & out_backSel_49_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_458 = _out_rofireMux_T_457; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_461 = _out_rofireMux_T_260 & out_backSel_50_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_462 = _out_rofireMux_T_461; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_465 = _out_rofireMux_T_260 & out_backSel_51_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_466 = _out_rofireMux_T_465; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_469 = _out_rofireMux_T_260 & out_backSel_52_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_470 = _out_rofireMux_T_469; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_473 = _out_rofireMux_T_260 & out_backSel_53_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_474 = _out_rofireMux_T_473; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_477 = _out_rofireMux_T_260 & out_backSel_54_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_478 = _out_rofireMux_T_477; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_481 = _out_rofireMux_T_260 & out_backSel_55_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_482 = _out_rofireMux_T_481; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_485 = _out_rofireMux_T_260 & out_backSel_56_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_486 = _out_rofireMux_T_485; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_489 = _out_rofireMux_T_260 & out_backSel_57_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_490 = _out_rofireMux_T_489; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_493 = _out_rofireMux_T_260 & out_backSel_58_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_494 = _out_rofireMux_T_493; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_497 = _out_rofireMux_T_260 & out_backSel_59_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_498 = _out_rofireMux_T_497; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_501 = _out_rofireMux_T_260 & out_backSel_60_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_502 = _out_rofireMux_T_501; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_505 = _out_rofireMux_T_260 & out_backSel_61_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_506 = _out_rofireMux_T_505; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_509 = _out_rofireMux_T_260 & out_backSel_62_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_510 = _out_rofireMux_T_509; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_513 = _out_rofireMux_T_260 & out_backSel_63_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_514 = _out_rofireMux_T_513; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_517 = _out_rofireMux_T_260 & out_backSel_64; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_518 = _out_rofireMux_T_517; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_521 = _out_rofireMux_T_260 & out_backSel_65; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_522 = _out_rofireMux_T_521; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_525 = _out_rofireMux_T_260 & out_backSel_66; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_526 = _out_rofireMux_T_525; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_529 = _out_rofireMux_T_260 & out_backSel_67; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_530 = _out_rofireMux_T_529; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_533 = _out_rofireMux_T_260 & out_backSel_68; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_534 = _out_rofireMux_T_533; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_537 = _out_rofireMux_T_260 & out_backSel_69; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_538 = _out_rofireMux_T_537; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_541 = _out_rofireMux_T_260 & out_backSel_70; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_542 = _out_rofireMux_T_541; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_545 = _out_rofireMux_T_260 & out_backSel_71; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_546 = _out_rofireMux_T_545; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_549 = _out_rofireMux_T_260 & out_backSel_72; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_550 = _out_rofireMux_T_549; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_553 = _out_rofireMux_T_260 & out_backSel_73; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_554 = _out_rofireMux_T_553; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_557 = _out_rofireMux_T_260 & out_backSel_74; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_558 = _out_rofireMux_T_557; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_561 = _out_rofireMux_T_260 & out_backSel_75; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_562 = _out_rofireMux_T_561; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_565 = _out_rofireMux_T_260 & out_backSel_76; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_566 = _out_rofireMux_T_565; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_569 = _out_rofireMux_T_260 & out_backSel_77; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_570 = _out_rofireMux_T_569; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_573 = _out_rofireMux_T_260 & out_backSel_78; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_574 = _out_rofireMux_T_573; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_577 = _out_rofireMux_T_260 & out_backSel_79; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_578 = _out_rofireMux_T_577; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_581 = _out_rofireMux_T_260 & out_backSel_80; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_582 = _out_rofireMux_T_581; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_585 = _out_rofireMux_T_260 & out_backSel_81; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_586 = _out_rofireMux_T_585; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_589 = _out_rofireMux_T_260 & out_backSel_82; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_590 = _out_rofireMux_T_589; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_593 = _out_rofireMux_T_260 & out_backSel_83; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_594 = _out_rofireMux_T_593; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_597 = _out_rofireMux_T_260 & out_backSel_84; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_598 = _out_rofireMux_T_597; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_601 = _out_rofireMux_T_260 & out_backSel_85; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_602 = _out_rofireMux_T_601; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_605 = _out_rofireMux_T_260 & out_backSel_86; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_606 = _out_rofireMux_T_605; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_609 = _out_rofireMux_T_260 & out_backSel_87; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_610 = _out_rofireMux_T_609; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_613 = _out_rofireMux_T_260 & out_backSel_88; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_614 = _out_rofireMux_T_613; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_617 = _out_rofireMux_T_260 & out_backSel_89; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_618 = _out_rofireMux_T_617; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_621 = _out_rofireMux_T_260 & out_backSel_90; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_622 = _out_rofireMux_T_621; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_625 = _out_rofireMux_T_260 & out_backSel_91; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_626 = _out_rofireMux_T_625; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_629 = _out_rofireMux_T_260 & out_backSel_92; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_630 = _out_rofireMux_T_629; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_633 = _out_rofireMux_T_260 & out_backSel_93; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_634 = _out_rofireMux_T_633; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_637 = _out_rofireMux_T_260 & out_backSel_94; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_638 = _out_rofireMux_T_637; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_641 = _out_rofireMux_T_260 & out_backSel_95; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_642 = _out_rofireMux_T_641; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_645 = _out_rofireMux_T_260 & out_backSel_96; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_646 = _out_rofireMux_T_645 & _out_T_1713; // @[RegisterRouter.scala:87:24]
assign out_roready_1_442 = _out_rofireMux_T_646; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_647 = ~_out_T_1713; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_649 = _out_rofireMux_T_260 & out_backSel_97; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_650 = _out_rofireMux_T_649; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_653 = _out_rofireMux_T_260 & out_backSel_98; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_654 = _out_rofireMux_T_653; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_657 = _out_rofireMux_T_260 & out_backSel_99; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_658 = _out_rofireMux_T_657; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_661 = _out_rofireMux_T_260 & out_backSel_100; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_662 = _out_rofireMux_T_661; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_665 = _out_rofireMux_T_260 & out_backSel_101; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_666 = _out_rofireMux_T_665; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_669 = _out_rofireMux_T_260 & out_backSel_102; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_670 = _out_rofireMux_T_669; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_673 = _out_rofireMux_T_260 & out_backSel_103; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_674 = _out_rofireMux_T_673 & _out_T_1781; // @[RegisterRouter.scala:87:24]
assign out_roready_1_697 = _out_rofireMux_T_674; // @[RegisterRouter.scala:87:24]
assign out_roready_1_698 = _out_rofireMux_T_674; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_675 = ~_out_T_1781; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_677 = _out_rofireMux_T_260 & out_backSel_104; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_678 = _out_rofireMux_T_677 & _out_T_1841; // @[RegisterRouter.scala:87:24]
assign out_roready_1_931 = _out_rofireMux_T_678; // @[RegisterRouter.scala:87:24]
assign out_roready_1_932 = _out_rofireMux_T_678; // @[RegisterRouter.scala:87:24]
assign out_roready_1_933 = _out_rofireMux_T_678; // @[RegisterRouter.scala:87:24]
assign out_roready_1_934 = _out_rofireMux_T_678; // @[RegisterRouter.scala:87:24]
assign out_roready_1_935 = _out_rofireMux_T_678; // @[RegisterRouter.scala:87:24]
assign out_roready_1_936 = _out_rofireMux_T_678; // @[RegisterRouter.scala:87:24]
assign out_roready_1_937 = _out_rofireMux_T_678; // @[RegisterRouter.scala:87:24]
assign out_roready_1_938 = _out_rofireMux_T_678; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_679 = ~_out_T_1841; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_681 = _out_rofireMux_T_260 & out_backSel_105; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_682 = _out_rofireMux_T_681 & _out_T_1733; // @[RegisterRouter.scala:87:24]
assign out_roready_1_511 = _out_rofireMux_T_682; // @[RegisterRouter.scala:87:24]
assign out_roready_1_512 = _out_rofireMux_T_682; // @[RegisterRouter.scala:87:24]
assign out_roready_1_513 = _out_rofireMux_T_682; // @[RegisterRouter.scala:87:24]
assign out_roready_1_514 = _out_rofireMux_T_682; // @[RegisterRouter.scala:87:24]
assign out_roready_1_515 = _out_rofireMux_T_682; // @[RegisterRouter.scala:87:24]
assign out_roready_1_516 = _out_rofireMux_T_682; // @[RegisterRouter.scala:87:24]
assign out_roready_1_517 = _out_rofireMux_T_682; // @[RegisterRouter.scala:87:24]
assign out_roready_1_518 = _out_rofireMux_T_682; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_683 = ~_out_T_1733; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_685 = _out_rofireMux_T_260 & out_backSel_106; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_686 = _out_rofireMux_T_685 & _out_T_1649; // @[RegisterRouter.scala:87:24]
assign out_roready_1_192 = _out_rofireMux_T_686; // @[RegisterRouter.scala:87:24]
assign out_roready_1_193 = _out_rofireMux_T_686; // @[RegisterRouter.scala:87:24]
assign out_roready_1_194 = _out_rofireMux_T_686; // @[RegisterRouter.scala:87:24]
assign out_roready_1_195 = _out_rofireMux_T_686; // @[RegisterRouter.scala:87:24]
assign out_roready_1_196 = _out_rofireMux_T_686; // @[RegisterRouter.scala:87:24]
assign out_roready_1_197 = _out_rofireMux_T_686; // @[RegisterRouter.scala:87:24]
assign out_roready_1_198 = _out_rofireMux_T_686; // @[RegisterRouter.scala:87:24]
assign out_roready_1_199 = _out_rofireMux_T_686; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_687 = ~_out_T_1649; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_689 = _out_rofireMux_T_260 & out_backSel_107; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_690 = _out_rofireMux_T_689 & _out_T_1881; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1091 = _out_rofireMux_T_690; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1092 = _out_rofireMux_T_690; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1093 = _out_rofireMux_T_690; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1094 = _out_rofireMux_T_690; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1095 = _out_rofireMux_T_690; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1096 = _out_rofireMux_T_690; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1097 = _out_rofireMux_T_690; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1098 = _out_rofireMux_T_690; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_691 = ~_out_T_1881; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_693 = _out_rofireMux_T_260 & out_backSel_108; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_694 = _out_rofireMux_T_693 & _out_T_1791; // @[RegisterRouter.scala:87:24]
assign out_roready_1_731 = _out_rofireMux_T_694; // @[RegisterRouter.scala:87:24]
assign out_roready_1_732 = _out_rofireMux_T_694; // @[RegisterRouter.scala:87:24]
assign out_roready_1_733 = _out_rofireMux_T_694; // @[RegisterRouter.scala:87:24]
assign out_roready_1_734 = _out_rofireMux_T_694; // @[RegisterRouter.scala:87:24]
assign out_roready_1_735 = _out_rofireMux_T_694; // @[RegisterRouter.scala:87:24]
assign out_roready_1_736 = _out_rofireMux_T_694; // @[RegisterRouter.scala:87:24]
assign out_roready_1_737 = _out_rofireMux_T_694; // @[RegisterRouter.scala:87:24]
assign out_roready_1_738 = _out_rofireMux_T_694; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_695 = ~_out_T_1791; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_697 = _out_rofireMux_T_260 & out_backSel_109; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_698 = _out_rofireMux_T_697 & _out_T_1715; // @[RegisterRouter.scala:87:24]
assign out_roready_1_443 = _out_rofireMux_T_698; // @[RegisterRouter.scala:87:24]
assign out_roready_1_444 = _out_rofireMux_T_698; // @[RegisterRouter.scala:87:24]
assign out_roready_1_445 = _out_rofireMux_T_698; // @[RegisterRouter.scala:87:24]
assign out_roready_1_446 = _out_rofireMux_T_698; // @[RegisterRouter.scala:87:24]
assign out_roready_1_447 = _out_rofireMux_T_698; // @[RegisterRouter.scala:87:24]
assign out_roready_1_448 = _out_rofireMux_T_698; // @[RegisterRouter.scala:87:24]
assign out_roready_1_449 = _out_rofireMux_T_698; // @[RegisterRouter.scala:87:24]
assign out_roready_1_450 = _out_rofireMux_T_698; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_699 = ~_out_T_1715; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_701 = _out_rofireMux_T_260 & out_backSel_110; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_702 = _out_rofireMux_T_701 & _out_T_1629; // @[RegisterRouter.scala:87:24]
assign out_roready_1_112 = _out_rofireMux_T_702; // @[RegisterRouter.scala:87:24]
assign out_roready_1_113 = _out_rofireMux_T_702; // @[RegisterRouter.scala:87:24]
assign out_roready_1_114 = _out_rofireMux_T_702; // @[RegisterRouter.scala:87:24]
assign out_roready_1_115 = _out_rofireMux_T_702; // @[RegisterRouter.scala:87:24]
assign out_roready_1_116 = _out_rofireMux_T_702; // @[RegisterRouter.scala:87:24]
assign out_roready_1_117 = _out_rofireMux_T_702; // @[RegisterRouter.scala:87:24]
assign out_roready_1_118 = _out_rofireMux_T_702; // @[RegisterRouter.scala:87:24]
assign out_roready_1_119 = _out_rofireMux_T_702; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_703 = ~_out_T_1629; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_705 = _out_rofireMux_T_260 & out_backSel_111; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_706 = _out_rofireMux_T_705 & _out_T_1899; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1163 = _out_rofireMux_T_706; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1164 = _out_rofireMux_T_706; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1165 = _out_rofireMux_T_706; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1166 = _out_rofireMux_T_706; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1167 = _out_rofireMux_T_706; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1168 = _out_rofireMux_T_706; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1169 = _out_rofireMux_T_706; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1170 = _out_rofireMux_T_706; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_707 = ~_out_T_1899; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_709 = _out_rofireMux_T_260 & out_backSel_112; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_710 = _out_rofireMux_T_709 & _out_T_1815; // @[RegisterRouter.scala:87:24]
assign out_roready_1_827 = _out_rofireMux_T_710; // @[RegisterRouter.scala:87:24]
assign out_roready_1_828 = _out_rofireMux_T_710; // @[RegisterRouter.scala:87:24]
assign out_roready_1_829 = _out_rofireMux_T_710; // @[RegisterRouter.scala:87:24]
assign out_roready_1_830 = _out_rofireMux_T_710; // @[RegisterRouter.scala:87:24]
assign out_roready_1_831 = _out_rofireMux_T_710; // @[RegisterRouter.scala:87:24]
assign out_roready_1_832 = _out_rofireMux_T_710; // @[RegisterRouter.scala:87:24]
assign out_roready_1_833 = _out_rofireMux_T_710; // @[RegisterRouter.scala:87:24]
assign out_roready_1_834 = _out_rofireMux_T_710; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_711 = ~_out_T_1815; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_713 = _out_rofireMux_T_260 & out_backSel_113; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_714 = _out_rofireMux_T_713 & _out_T_1771; // @[RegisterRouter.scala:87:24]
assign out_roready_1_657 = _out_rofireMux_T_714; // @[RegisterRouter.scala:87:24]
assign out_roready_1_658 = _out_rofireMux_T_714; // @[RegisterRouter.scala:87:24]
assign out_roready_1_659 = _out_rofireMux_T_714; // @[RegisterRouter.scala:87:24]
assign out_roready_1_660 = _out_rofireMux_T_714; // @[RegisterRouter.scala:87:24]
assign out_roready_1_661 = _out_rofireMux_T_714; // @[RegisterRouter.scala:87:24]
assign out_roready_1_662 = _out_rofireMux_T_714; // @[RegisterRouter.scala:87:24]
assign out_roready_1_663 = _out_rofireMux_T_714; // @[RegisterRouter.scala:87:24]
assign out_roready_1_664 = _out_rofireMux_T_714; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_715 = ~_out_T_1771; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_717 = _out_rofireMux_T_260 & out_backSel_114; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_718 = _out_rofireMux_T_717 & _out_T_1853; // @[RegisterRouter.scala:87:24]
assign out_roready_1_979 = _out_rofireMux_T_718; // @[RegisterRouter.scala:87:24]
assign out_roready_1_980 = _out_rofireMux_T_718; // @[RegisterRouter.scala:87:24]
assign out_roready_1_981 = _out_rofireMux_T_718; // @[RegisterRouter.scala:87:24]
assign out_roready_1_982 = _out_rofireMux_T_718; // @[RegisterRouter.scala:87:24]
assign out_roready_1_983 = _out_rofireMux_T_718; // @[RegisterRouter.scala:87:24]
assign out_roready_1_984 = _out_rofireMux_T_718; // @[RegisterRouter.scala:87:24]
assign out_roready_1_985 = _out_rofireMux_T_718; // @[RegisterRouter.scala:87:24]
assign out_roready_1_986 = _out_rofireMux_T_718; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_719 = ~_out_T_1853; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_721 = _out_rofireMux_T_260 & out_backSel_115; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_722 = _out_rofireMux_T_721 & _out_T_1609; // @[RegisterRouter.scala:87:24]
assign out_roready_1_32 = _out_rofireMux_T_722; // @[RegisterRouter.scala:87:24]
assign out_roready_1_33 = _out_rofireMux_T_722; // @[RegisterRouter.scala:87:24]
assign out_roready_1_34 = _out_rofireMux_T_722; // @[RegisterRouter.scala:87:24]
assign out_roready_1_35 = _out_rofireMux_T_722; // @[RegisterRouter.scala:87:24]
assign out_roready_1_36 = _out_rofireMux_T_722; // @[RegisterRouter.scala:87:24]
assign out_roready_1_37 = _out_rofireMux_T_722; // @[RegisterRouter.scala:87:24]
assign out_roready_1_38 = _out_rofireMux_T_722; // @[RegisterRouter.scala:87:24]
assign out_roready_1_39 = _out_rofireMux_T_722; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_723 = ~_out_T_1609; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_725 = _out_rofireMux_T_260 & out_backSel_116; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_726 = _out_rofireMux_T_725; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_729 = _out_rofireMux_T_260 & out_backSel_117; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_730 = _out_rofireMux_T_729; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_733 = _out_rofireMux_T_260 & out_backSel_118; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_734 = _out_rofireMux_T_733; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_737 = _out_rofireMux_T_260 & out_backSel_119; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_738 = _out_rofireMux_T_737; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_741 = _out_rofireMux_T_260 & out_backSel_120; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_742 = _out_rofireMux_T_741; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_745 = _out_rofireMux_T_260 & out_backSel_121; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_746 = _out_rofireMux_T_745; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_749 = _out_rofireMux_T_260 & out_backSel_122; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_750 = _out_rofireMux_T_749; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_753 = _out_rofireMux_T_260 & out_backSel_123; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_754 = _out_rofireMux_T_753; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_757 = _out_rofireMux_T_260 & out_backSel_124; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_758 = _out_rofireMux_T_757; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_761 = _out_rofireMux_T_260 & out_backSel_125; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_762 = _out_rofireMux_T_761; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_765 = _out_rofireMux_T_260 & out_backSel_126; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_766 = _out_rofireMux_T_765; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_769 = _out_rofireMux_T_260 & out_backSel_127; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_770 = _out_rofireMux_T_769; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_773 = _out_rofireMux_T_260 & out_backSel_128; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_774 = _out_rofireMux_T_773 & _out_T_1729; // @[RegisterRouter.scala:87:24]
assign out_roready_1_495 = _out_rofireMux_T_774; // @[RegisterRouter.scala:87:24]
assign out_roready_1_496 = _out_rofireMux_T_774; // @[RegisterRouter.scala:87:24]
assign out_roready_1_497 = _out_rofireMux_T_774; // @[RegisterRouter.scala:87:24]
assign out_roready_1_498 = _out_rofireMux_T_774; // @[RegisterRouter.scala:87:24]
assign out_roready_1_499 = _out_rofireMux_T_774; // @[RegisterRouter.scala:87:24]
assign out_roready_1_500 = _out_rofireMux_T_774; // @[RegisterRouter.scala:87:24]
assign out_roready_1_501 = _out_rofireMux_T_774; // @[RegisterRouter.scala:87:24]
assign out_roready_1_502 = _out_rofireMux_T_774; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_775 = ~_out_T_1729; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_777 = _out_rofireMux_T_260 & out_backSel_129; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_778 = _out_rofireMux_T_777 & _out_T_1721; // @[RegisterRouter.scala:87:24]
assign out_roready_1_467 = _out_rofireMux_T_778; // @[RegisterRouter.scala:87:24]
assign out_roready_1_468 = _out_rofireMux_T_778; // @[RegisterRouter.scala:87:24]
assign out_roready_1_469 = _out_rofireMux_T_778; // @[RegisterRouter.scala:87:24]
assign out_roready_1_470 = _out_rofireMux_T_778; // @[RegisterRouter.scala:87:24]
assign out_roready_1_471 = _out_rofireMux_T_778; // @[RegisterRouter.scala:87:24]
assign out_roready_1_472 = _out_rofireMux_T_778; // @[RegisterRouter.scala:87:24]
assign out_roready_1_473 = _out_rofireMux_T_778; // @[RegisterRouter.scala:87:24]
assign out_roready_1_474 = _out_rofireMux_T_778; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_779 = ~_out_T_1721; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_781 = _out_rofireMux_T_260 & out_backSel_130; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_782 = _out_rofireMux_T_781 & _out_T_1797; // @[RegisterRouter.scala:87:24]
assign out_roready_1_755 = _out_rofireMux_T_782; // @[RegisterRouter.scala:87:24]
assign out_roready_1_756 = _out_rofireMux_T_782; // @[RegisterRouter.scala:87:24]
assign out_roready_1_757 = _out_rofireMux_T_782; // @[RegisterRouter.scala:87:24]
assign out_roready_1_758 = _out_rofireMux_T_782; // @[RegisterRouter.scala:87:24]
assign out_roready_1_759 = _out_rofireMux_T_782; // @[RegisterRouter.scala:87:24]
assign out_roready_1_760 = _out_rofireMux_T_782; // @[RegisterRouter.scala:87:24]
assign out_roready_1_761 = _out_rofireMux_T_782; // @[RegisterRouter.scala:87:24]
assign out_roready_1_762 = _out_rofireMux_T_782; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_783 = ~_out_T_1797; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_785 = _out_rofireMux_T_260 & out_backSel_131; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_786 = _out_rofireMux_T_785 & _out_T_1891; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1131 = _out_rofireMux_T_786; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1132 = _out_rofireMux_T_786; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1133 = _out_rofireMux_T_786; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1134 = _out_rofireMux_T_786; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1135 = _out_rofireMux_T_786; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1136 = _out_rofireMux_T_786; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1137 = _out_rofireMux_T_786; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1138 = _out_rofireMux_T_786; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_787 = ~_out_T_1891; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_789 = _out_rofireMux_T_260 & out_backSel_132; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_790 = _out_rofireMux_T_789 & _out_T_1661; // @[RegisterRouter.scala:87:24]
assign out_roready_1_240 = _out_rofireMux_T_790; // @[RegisterRouter.scala:87:24]
assign out_roready_1_241 = _out_rofireMux_T_790; // @[RegisterRouter.scala:87:24]
assign out_roready_1_242 = _out_rofireMux_T_790; // @[RegisterRouter.scala:87:24]
assign out_roready_1_243 = _out_rofireMux_T_790; // @[RegisterRouter.scala:87:24]
assign out_roready_1_244 = _out_rofireMux_T_790; // @[RegisterRouter.scala:87:24]
assign out_roready_1_245 = _out_rofireMux_T_790; // @[RegisterRouter.scala:87:24]
assign out_roready_1_246 = _out_rofireMux_T_790; // @[RegisterRouter.scala:87:24]
assign out_roready_1_247 = _out_rofireMux_T_790; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_791 = ~_out_T_1661; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_793 = _out_rofireMux_T_260 & out_backSel_133; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_794 = _out_rofireMux_T_793 & _out_T_1663; // @[RegisterRouter.scala:87:24]
assign out_roready_1_248 = _out_rofireMux_T_794; // @[RegisterRouter.scala:87:24]
assign out_roready_1_249 = _out_rofireMux_T_794; // @[RegisterRouter.scala:87:24]
assign out_roready_1_250 = _out_rofireMux_T_794; // @[RegisterRouter.scala:87:24]
assign out_roready_1_251 = _out_rofireMux_T_794; // @[RegisterRouter.scala:87:24]
assign out_roready_1_252 = _out_rofireMux_T_794; // @[RegisterRouter.scala:87:24]
assign out_roready_1_253 = _out_rofireMux_T_794; // @[RegisterRouter.scala:87:24]
assign out_roready_1_254 = _out_rofireMux_T_794; // @[RegisterRouter.scala:87:24]
assign out_roready_1_255 = _out_rofireMux_T_794; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_795 = ~_out_T_1663; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_797 = _out_rofireMux_T_260 & out_backSel_134; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_798 = _out_rofireMux_T_797 & _out_T_1723; // @[RegisterRouter.scala:87:24]
assign out_roready_1_475 = _out_rofireMux_T_798; // @[RegisterRouter.scala:87:24]
assign out_roready_1_476 = _out_rofireMux_T_798; // @[RegisterRouter.scala:87:24]
assign out_roready_1_477 = _out_rofireMux_T_798; // @[RegisterRouter.scala:87:24]
assign out_roready_1_478 = _out_rofireMux_T_798; // @[RegisterRouter.scala:87:24]
assign out_roready_1_479 = _out_rofireMux_T_798; // @[RegisterRouter.scala:87:24]
assign out_roready_1_480 = _out_rofireMux_T_798; // @[RegisterRouter.scala:87:24]
assign out_roready_1_481 = _out_rofireMux_T_798; // @[RegisterRouter.scala:87:24]
assign out_roready_1_482 = _out_rofireMux_T_798; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_799 = ~_out_T_1723; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_801 = _out_rofireMux_T_260 & out_backSel_135; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_802 = _out_rofireMux_T_801 & _out_T_1801; // @[RegisterRouter.scala:87:24]
assign out_roready_1_771 = _out_rofireMux_T_802; // @[RegisterRouter.scala:87:24]
assign out_roready_1_772 = _out_rofireMux_T_802; // @[RegisterRouter.scala:87:24]
assign out_roready_1_773 = _out_rofireMux_T_802; // @[RegisterRouter.scala:87:24]
assign out_roready_1_774 = _out_rofireMux_T_802; // @[RegisterRouter.scala:87:24]
assign out_roready_1_775 = _out_rofireMux_T_802; // @[RegisterRouter.scala:87:24]
assign out_roready_1_776 = _out_rofireMux_T_802; // @[RegisterRouter.scala:87:24]
assign out_roready_1_777 = _out_rofireMux_T_802; // @[RegisterRouter.scala:87:24]
assign out_roready_1_778 = _out_rofireMux_T_802; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_803 = ~_out_T_1801; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_805 = _out_rofireMux_T_260 & out_backSel_136; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_806 = _out_rofireMux_T_805 & _out_T_1883; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1099 = _out_rofireMux_T_806; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1100 = _out_rofireMux_T_806; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1101 = _out_rofireMux_T_806; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1102 = _out_rofireMux_T_806; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1103 = _out_rofireMux_T_806; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1104 = _out_rofireMux_T_806; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1105 = _out_rofireMux_T_806; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1106 = _out_rofireMux_T_806; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_807 = ~_out_T_1883; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_809 = _out_rofireMux_T_260 & out_backSel_137; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_810 = _out_rofireMux_T_809 & _out_T_1685; // @[RegisterRouter.scala:87:24]
assign out_roready_1_336 = _out_rofireMux_T_810; // @[RegisterRouter.scala:87:24]
assign out_roready_1_337 = _out_rofireMux_T_810; // @[RegisterRouter.scala:87:24]
assign out_roready_1_338 = _out_rofireMux_T_810; // @[RegisterRouter.scala:87:24]
assign out_roready_1_339 = _out_rofireMux_T_810; // @[RegisterRouter.scala:87:24]
assign out_roready_1_340 = _out_rofireMux_T_810; // @[RegisterRouter.scala:87:24]
assign out_roready_1_341 = _out_rofireMux_T_810; // @[RegisterRouter.scala:87:24]
assign out_roready_1_342 = _out_rofireMux_T_810; // @[RegisterRouter.scala:87:24]
assign out_roready_1_343 = _out_rofireMux_T_810; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_811 = ~_out_T_1685; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_813 = _out_rofireMux_T_260 & out_backSel_138; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_814 = _out_rofireMux_T_813 & _out_T_1601; // @[RegisterRouter.scala:87:24]
assign out_roready_1_0 = _out_rofireMux_T_814; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1 = _out_rofireMux_T_814; // @[RegisterRouter.scala:87:24]
assign out_roready_1_2 = _out_rofireMux_T_814; // @[RegisterRouter.scala:87:24]
assign out_roready_1_3 = _out_rofireMux_T_814; // @[RegisterRouter.scala:87:24]
assign out_roready_1_4 = _out_rofireMux_T_814; // @[RegisterRouter.scala:87:24]
assign out_roready_1_5 = _out_rofireMux_T_814; // @[RegisterRouter.scala:87:24]
assign out_roready_1_6 = _out_rofireMux_T_814; // @[RegisterRouter.scala:87:24]
assign out_roready_1_7 = _out_rofireMux_T_814; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_815 = ~_out_T_1601; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_817 = _out_rofireMux_T_260 & out_backSel_139; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_818 = _out_rofireMux_T_817 & _out_T_1857; // @[RegisterRouter.scala:87:24]
assign out_roready_1_995 = _out_rofireMux_T_818; // @[RegisterRouter.scala:87:24]
assign out_roready_1_996 = _out_rofireMux_T_818; // @[RegisterRouter.scala:87:24]
assign out_roready_1_997 = _out_rofireMux_T_818; // @[RegisterRouter.scala:87:24]
assign out_roready_1_998 = _out_rofireMux_T_818; // @[RegisterRouter.scala:87:24]
assign out_roready_1_999 = _out_rofireMux_T_818; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1000 = _out_rofireMux_T_818; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1001 = _out_rofireMux_T_818; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1002 = _out_rofireMux_T_818; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_819 = ~_out_T_1857; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_821 = _out_rofireMux_T_260 & out_backSel_140; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_822 = _out_rofireMux_T_821 & _out_T_1783; // @[RegisterRouter.scala:87:24]
assign out_roready_1_699 = _out_rofireMux_T_822; // @[RegisterRouter.scala:87:24]
assign out_roready_1_700 = _out_rofireMux_T_822; // @[RegisterRouter.scala:87:24]
assign out_roready_1_701 = _out_rofireMux_T_822; // @[RegisterRouter.scala:87:24]
assign out_roready_1_702 = _out_rofireMux_T_822; // @[RegisterRouter.scala:87:24]
assign out_roready_1_703 = _out_rofireMux_T_822; // @[RegisterRouter.scala:87:24]
assign out_roready_1_704 = _out_rofireMux_T_822; // @[RegisterRouter.scala:87:24]
assign out_roready_1_705 = _out_rofireMux_T_822; // @[RegisterRouter.scala:87:24]
assign out_roready_1_706 = _out_rofireMux_T_822; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_823 = ~_out_T_1783; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_825 = _out_rofireMux_T_260 & out_backSel_141; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_826 = _out_rofireMux_T_825 & _out_T_1705; // @[RegisterRouter.scala:87:24]
assign out_roready_1_410 = _out_rofireMux_T_826; // @[RegisterRouter.scala:87:24]
assign out_roready_1_411 = _out_rofireMux_T_826; // @[RegisterRouter.scala:87:24]
assign out_roready_1_412 = _out_rofireMux_T_826; // @[RegisterRouter.scala:87:24]
assign out_roready_1_413 = _out_rofireMux_T_826; // @[RegisterRouter.scala:87:24]
assign out_roready_1_414 = _out_rofireMux_T_826; // @[RegisterRouter.scala:87:24]
assign out_roready_1_415 = _out_rofireMux_T_826; // @[RegisterRouter.scala:87:24]
assign out_roready_1_416 = _out_rofireMux_T_826; // @[RegisterRouter.scala:87:24]
assign out_roready_1_417 = _out_rofireMux_T_826; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_827 = ~_out_T_1705; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_829 = _out_rofireMux_T_260 & out_backSel_142; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_830 = _out_rofireMux_T_829 & _out_T_1617; // @[RegisterRouter.scala:87:24]
assign out_roready_1_64 = _out_rofireMux_T_830; // @[RegisterRouter.scala:87:24]
assign out_roready_1_65 = _out_rofireMux_T_830; // @[RegisterRouter.scala:87:24]
assign out_roready_1_66 = _out_rofireMux_T_830; // @[RegisterRouter.scala:87:24]
assign out_roready_1_67 = _out_rofireMux_T_830; // @[RegisterRouter.scala:87:24]
assign out_roready_1_68 = _out_rofireMux_T_830; // @[RegisterRouter.scala:87:24]
assign out_roready_1_69 = _out_rofireMux_T_830; // @[RegisterRouter.scala:87:24]
assign out_roready_1_70 = _out_rofireMux_T_830; // @[RegisterRouter.scala:87:24]
assign out_roready_1_71 = _out_rofireMux_T_830; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_831 = ~_out_T_1617; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_833 = _out_rofireMux_T_260 & out_backSel_143; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_834 = _out_rofireMux_T_833 & _out_T_1835; // @[RegisterRouter.scala:87:24]
assign out_roready_1_907 = _out_rofireMux_T_834; // @[RegisterRouter.scala:87:24]
assign out_roready_1_908 = _out_rofireMux_T_834; // @[RegisterRouter.scala:87:24]
assign out_roready_1_909 = _out_rofireMux_T_834; // @[RegisterRouter.scala:87:24]
assign out_roready_1_910 = _out_rofireMux_T_834; // @[RegisterRouter.scala:87:24]
assign out_roready_1_911 = _out_rofireMux_T_834; // @[RegisterRouter.scala:87:24]
assign out_roready_1_912 = _out_rofireMux_T_834; // @[RegisterRouter.scala:87:24]
assign out_roready_1_913 = _out_rofireMux_T_834; // @[RegisterRouter.scala:87:24]
assign out_roready_1_914 = _out_rofireMux_T_834; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_835 = ~_out_T_1835; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_837 = _out_rofireMux_T_260 & out_backSel_144; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_838 = _out_rofireMux_T_837 & _out_T_1759; // @[RegisterRouter.scala:87:24]
assign out_roready_1_609 = _out_rofireMux_T_838; // @[RegisterRouter.scala:87:24]
assign out_roready_1_610 = _out_rofireMux_T_838; // @[RegisterRouter.scala:87:24]
assign out_roready_1_611 = _out_rofireMux_T_838; // @[RegisterRouter.scala:87:24]
assign out_roready_1_612 = _out_rofireMux_T_838; // @[RegisterRouter.scala:87:24]
assign out_roready_1_613 = _out_rofireMux_T_838; // @[RegisterRouter.scala:87:24]
assign out_roready_1_614 = _out_rofireMux_T_838; // @[RegisterRouter.scala:87:24]
assign out_roready_1_615 = _out_rofireMux_T_838; // @[RegisterRouter.scala:87:24]
assign out_roready_1_616 = _out_rofireMux_T_838; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_839 = ~_out_T_1759; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_841 = _out_rofireMux_T_260 & out_backSel_145; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_842 = _out_rofireMux_T_841 & _out_T_1819; // @[RegisterRouter.scala:87:24]
assign out_roready_1_843 = _out_rofireMux_T_842; // @[RegisterRouter.scala:87:24]
assign out_roready_1_844 = _out_rofireMux_T_842; // @[RegisterRouter.scala:87:24]
assign out_roready_1_845 = _out_rofireMux_T_842; // @[RegisterRouter.scala:87:24]
assign out_roready_1_846 = _out_rofireMux_T_842; // @[RegisterRouter.scala:87:24]
assign out_roready_1_847 = _out_rofireMux_T_842; // @[RegisterRouter.scala:87:24]
assign out_roready_1_848 = _out_rofireMux_T_842; // @[RegisterRouter.scala:87:24]
assign out_roready_1_849 = _out_rofireMux_T_842; // @[RegisterRouter.scala:87:24]
assign out_roready_1_850 = _out_rofireMux_T_842; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_843 = ~_out_T_1819; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_845 = _out_rofireMux_T_260 & out_backSel_146; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_846 = _out_rofireMux_T_845 & _out_T_1869; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1043 = _out_rofireMux_T_846; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1044 = _out_rofireMux_T_846; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1045 = _out_rofireMux_T_846; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1046 = _out_rofireMux_T_846; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1047 = _out_rofireMux_T_846; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1048 = _out_rofireMux_T_846; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1049 = _out_rofireMux_T_846; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1050 = _out_rofireMux_T_846; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_847 = ~_out_T_1869; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_849 = _out_rofireMux_T_260 & out_backSel_147; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_850 = _out_rofireMux_T_849 & _out_T_1657; // @[RegisterRouter.scala:87:24]
assign out_roready_1_224 = _out_rofireMux_T_850; // @[RegisterRouter.scala:87:24]
assign out_roready_1_225 = _out_rofireMux_T_850; // @[RegisterRouter.scala:87:24]
assign out_roready_1_226 = _out_rofireMux_T_850; // @[RegisterRouter.scala:87:24]
assign out_roready_1_227 = _out_rofireMux_T_850; // @[RegisterRouter.scala:87:24]
assign out_roready_1_228 = _out_rofireMux_T_850; // @[RegisterRouter.scala:87:24]
assign out_roready_1_229 = _out_rofireMux_T_850; // @[RegisterRouter.scala:87:24]
assign out_roready_1_230 = _out_rofireMux_T_850; // @[RegisterRouter.scala:87:24]
assign out_roready_1_231 = _out_rofireMux_T_850; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_851 = ~_out_T_1657; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_853 = _out_rofireMux_T_260 & out_backSel_148; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_854 = _out_rofireMux_T_853 & _out_T_1741; // @[RegisterRouter.scala:87:24]
assign out_roready_1_537 = _out_rofireMux_T_854; // @[RegisterRouter.scala:87:24]
assign out_roready_1_538 = _out_rofireMux_T_854; // @[RegisterRouter.scala:87:24]
assign out_roready_1_539 = _out_rofireMux_T_854; // @[RegisterRouter.scala:87:24]
assign out_roready_1_540 = _out_rofireMux_T_854; // @[RegisterRouter.scala:87:24]
assign out_roready_1_541 = _out_rofireMux_T_854; // @[RegisterRouter.scala:87:24]
assign out_roready_1_542 = _out_rofireMux_T_854; // @[RegisterRouter.scala:87:24]
assign out_roready_1_543 = _out_rofireMux_T_854; // @[RegisterRouter.scala:87:24]
assign out_roready_1_544 = _out_rofireMux_T_854; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_855 = ~_out_T_1741; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_857 = _out_rofireMux_T_260 & out_backSel_149; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_858 = _out_rofireMux_T_857 & _out_T_1749; // @[RegisterRouter.scala:87:24]
assign out_roready_1_569 = _out_rofireMux_T_858; // @[RegisterRouter.scala:87:24]
assign out_roready_1_570 = _out_rofireMux_T_858; // @[RegisterRouter.scala:87:24]
assign out_roready_1_571 = _out_rofireMux_T_858; // @[RegisterRouter.scala:87:24]
assign out_roready_1_572 = _out_rofireMux_T_858; // @[RegisterRouter.scala:87:24]
assign out_roready_1_573 = _out_rofireMux_T_858; // @[RegisterRouter.scala:87:24]
assign out_roready_1_574 = _out_rofireMux_T_858; // @[RegisterRouter.scala:87:24]
assign out_roready_1_575 = _out_rofireMux_T_858; // @[RegisterRouter.scala:87:24]
assign out_roready_1_576 = _out_rofireMux_T_858; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_859 = ~_out_T_1749; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_861 = _out_rofireMux_T_260 & out_backSel_150; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_862 = _out_rofireMux_T_861 & _out_T_1821; // @[RegisterRouter.scala:87:24]
assign out_roready_1_851 = _out_rofireMux_T_862; // @[RegisterRouter.scala:87:24]
assign out_roready_1_852 = _out_rofireMux_T_862; // @[RegisterRouter.scala:87:24]
assign out_roready_1_853 = _out_rofireMux_T_862; // @[RegisterRouter.scala:87:24]
assign out_roready_1_854 = _out_rofireMux_T_862; // @[RegisterRouter.scala:87:24]
assign out_roready_1_855 = _out_rofireMux_T_862; // @[RegisterRouter.scala:87:24]
assign out_roready_1_856 = _out_rofireMux_T_862; // @[RegisterRouter.scala:87:24]
assign out_roready_1_857 = _out_rofireMux_T_862; // @[RegisterRouter.scala:87:24]
assign out_roready_1_858 = _out_rofireMux_T_862; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_863 = ~_out_T_1821; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_865 = _out_rofireMux_T_260 & out_backSel_151; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_866 = _out_rofireMux_T_865 & _out_T_1867; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1035 = _out_rofireMux_T_866; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1036 = _out_rofireMux_T_866; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1037 = _out_rofireMux_T_866; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1038 = _out_rofireMux_T_866; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1039 = _out_rofireMux_T_866; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1040 = _out_rofireMux_T_866; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1041 = _out_rofireMux_T_866; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1042 = _out_rofireMux_T_866; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_867 = ~_out_T_1867; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_869 = _out_rofireMux_T_260 & out_backSel_152; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_870 = _out_rofireMux_T_869 & _out_T_1637; // @[RegisterRouter.scala:87:24]
assign out_roready_1_144 = _out_rofireMux_T_870; // @[RegisterRouter.scala:87:24]
assign out_roready_1_145 = _out_rofireMux_T_870; // @[RegisterRouter.scala:87:24]
assign out_roready_1_146 = _out_rofireMux_T_870; // @[RegisterRouter.scala:87:24]
assign out_roready_1_147 = _out_rofireMux_T_870; // @[RegisterRouter.scala:87:24]
assign out_roready_1_148 = _out_rofireMux_T_870; // @[RegisterRouter.scala:87:24]
assign out_roready_1_149 = _out_rofireMux_T_870; // @[RegisterRouter.scala:87:24]
assign out_roready_1_150 = _out_rofireMux_T_870; // @[RegisterRouter.scala:87:24]
assign out_roready_1_151 = _out_rofireMux_T_870; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_871 = ~_out_T_1637; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_873 = _out_rofireMux_T_260 & out_backSel_153; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_874 = _out_rofireMux_T_873 & _out_T_1619; // @[RegisterRouter.scala:87:24]
assign out_roready_1_72 = _out_rofireMux_T_874; // @[RegisterRouter.scala:87:24]
assign out_roready_1_73 = _out_rofireMux_T_874; // @[RegisterRouter.scala:87:24]
assign out_roready_1_74 = _out_rofireMux_T_874; // @[RegisterRouter.scala:87:24]
assign out_roready_1_75 = _out_rofireMux_T_874; // @[RegisterRouter.scala:87:24]
assign out_roready_1_76 = _out_rofireMux_T_874; // @[RegisterRouter.scala:87:24]
assign out_roready_1_77 = _out_rofireMux_T_874; // @[RegisterRouter.scala:87:24]
assign out_roready_1_78 = _out_rofireMux_T_874; // @[RegisterRouter.scala:87:24]
assign out_roready_1_79 = _out_rofireMux_T_874; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_875 = ~_out_T_1619; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_877 = _out_rofireMux_T_260 & out_backSel_154; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_878 = _out_rofireMux_T_877 & _out_T_1831; // @[RegisterRouter.scala:87:24]
assign out_roready_1_891 = _out_rofireMux_T_878; // @[RegisterRouter.scala:87:24]
assign out_roready_1_892 = _out_rofireMux_T_878; // @[RegisterRouter.scala:87:24]
assign out_roready_1_893 = _out_rofireMux_T_878; // @[RegisterRouter.scala:87:24]
assign out_roready_1_894 = _out_rofireMux_T_878; // @[RegisterRouter.scala:87:24]
assign out_roready_1_895 = _out_rofireMux_T_878; // @[RegisterRouter.scala:87:24]
assign out_roready_1_896 = _out_rofireMux_T_878; // @[RegisterRouter.scala:87:24]
assign out_roready_1_897 = _out_rofireMux_T_878; // @[RegisterRouter.scala:87:24]
assign out_roready_1_898 = _out_rofireMux_T_878; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_879 = ~_out_T_1831; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_881 = _out_rofireMux_T_260 & out_backSel_155; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_882 = _out_rofireMux_T_881 & _out_T_1787; // @[RegisterRouter.scala:87:24]
assign out_roready_1_715 = _out_rofireMux_T_882; // @[RegisterRouter.scala:87:24]
assign out_roready_1_716 = _out_rofireMux_T_882; // @[RegisterRouter.scala:87:24]
assign out_roready_1_717 = _out_rofireMux_T_882; // @[RegisterRouter.scala:87:24]
assign out_roready_1_718 = _out_rofireMux_T_882; // @[RegisterRouter.scala:87:24]
assign out_roready_1_719 = _out_rofireMux_T_882; // @[RegisterRouter.scala:87:24]
assign out_roready_1_720 = _out_rofireMux_T_882; // @[RegisterRouter.scala:87:24]
assign out_roready_1_721 = _out_rofireMux_T_882; // @[RegisterRouter.scala:87:24]
assign out_roready_1_722 = _out_rofireMux_T_882; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_883 = ~_out_T_1787; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_885 = _out_rofireMux_T_260 & out_backSel_156; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_886 = _out_rofireMux_T_885 & _out_T_1699; // @[RegisterRouter.scala:87:24]
assign out_roready_1_386 = _out_rofireMux_T_886; // @[RegisterRouter.scala:87:24]
assign out_roready_1_387 = _out_rofireMux_T_886; // @[RegisterRouter.scala:87:24]
assign out_roready_1_388 = _out_rofireMux_T_886; // @[RegisterRouter.scala:87:24]
assign out_roready_1_389 = _out_rofireMux_T_886; // @[RegisterRouter.scala:87:24]
assign out_roready_1_390 = _out_rofireMux_T_886; // @[RegisterRouter.scala:87:24]
assign out_roready_1_391 = _out_rofireMux_T_886; // @[RegisterRouter.scala:87:24]
assign out_roready_1_392 = _out_rofireMux_T_886; // @[RegisterRouter.scala:87:24]
assign out_roready_1_393 = _out_rofireMux_T_886; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_887 = ~_out_T_1699; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_889 = _out_rofireMux_T_260 & out_backSel_157; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_890 = _out_rofireMux_T_889 & _out_T_1633; // @[RegisterRouter.scala:87:24]
assign out_roready_1_128 = _out_rofireMux_T_890; // @[RegisterRouter.scala:87:24]
assign out_roready_1_129 = _out_rofireMux_T_890; // @[RegisterRouter.scala:87:24]
assign out_roready_1_130 = _out_rofireMux_T_890; // @[RegisterRouter.scala:87:24]
assign out_roready_1_131 = _out_rofireMux_T_890; // @[RegisterRouter.scala:87:24]
assign out_roready_1_132 = _out_rofireMux_T_890; // @[RegisterRouter.scala:87:24]
assign out_roready_1_133 = _out_rofireMux_T_890; // @[RegisterRouter.scala:87:24]
assign out_roready_1_134 = _out_rofireMux_T_890; // @[RegisterRouter.scala:87:24]
assign out_roready_1_135 = _out_rofireMux_T_890; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_891 = ~_out_T_1633; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_893 = _out_rofireMux_T_260 & out_backSel_158; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_894 = _out_rofireMux_T_893 & _out_T_1849; // @[RegisterRouter.scala:87:24]
assign out_roready_1_963 = _out_rofireMux_T_894; // @[RegisterRouter.scala:87:24]
assign out_roready_1_964 = _out_rofireMux_T_894; // @[RegisterRouter.scala:87:24]
assign out_roready_1_965 = _out_rofireMux_T_894; // @[RegisterRouter.scala:87:24]
assign out_roready_1_966 = _out_rofireMux_T_894; // @[RegisterRouter.scala:87:24]
assign out_roready_1_967 = _out_rofireMux_T_894; // @[RegisterRouter.scala:87:24]
assign out_roready_1_968 = _out_rofireMux_T_894; // @[RegisterRouter.scala:87:24]
assign out_roready_1_969 = _out_rofireMux_T_894; // @[RegisterRouter.scala:87:24]
assign out_roready_1_970 = _out_rofireMux_T_894; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_895 = ~_out_T_1849; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_897 = _out_rofireMux_T_260 & out_backSel_159; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_898 = _out_rofireMux_T_897 & _out_T_1765; // @[RegisterRouter.scala:87:24]
assign out_roready_1_633 = _out_rofireMux_T_898; // @[RegisterRouter.scala:87:24]
assign out_roready_1_634 = _out_rofireMux_T_898; // @[RegisterRouter.scala:87:24]
assign out_roready_1_635 = _out_rofireMux_T_898; // @[RegisterRouter.scala:87:24]
assign out_roready_1_636 = _out_rofireMux_T_898; // @[RegisterRouter.scala:87:24]
assign out_roready_1_637 = _out_rofireMux_T_898; // @[RegisterRouter.scala:87:24]
assign out_roready_1_638 = _out_rofireMux_T_898; // @[RegisterRouter.scala:87:24]
assign out_roready_1_639 = _out_rofireMux_T_898; // @[RegisterRouter.scala:87:24]
assign out_roready_1_640 = _out_rofireMux_T_898; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_899 = ~_out_T_1765; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_901 = _out_rofireMux_T_260 & out_backSel_160; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_902 = _out_rofireMux_T_901 & _out_T_1681; // @[RegisterRouter.scala:87:24]
assign out_roready_1_320 = _out_rofireMux_T_902; // @[RegisterRouter.scala:87:24]
assign out_roready_1_321 = _out_rofireMux_T_902; // @[RegisterRouter.scala:87:24]
assign out_roready_1_322 = _out_rofireMux_T_902; // @[RegisterRouter.scala:87:24]
assign out_roready_1_323 = _out_rofireMux_T_902; // @[RegisterRouter.scala:87:24]
assign out_roready_1_324 = _out_rofireMux_T_902; // @[RegisterRouter.scala:87:24]
assign out_roready_1_325 = _out_rofireMux_T_902; // @[RegisterRouter.scala:87:24]
assign out_roready_1_326 = _out_rofireMux_T_902; // @[RegisterRouter.scala:87:24]
assign out_roready_1_327 = _out_rofireMux_T_902; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_903 = ~_out_T_1681; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_905 = _out_rofireMux_T_260 & out_backSel_161; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_906 = _out_rofireMux_T_905 & _out_T_1745; // @[RegisterRouter.scala:87:24]
assign out_roready_1_553 = _out_rofireMux_T_906; // @[RegisterRouter.scala:87:24]
assign out_roready_1_554 = _out_rofireMux_T_906; // @[RegisterRouter.scala:87:24]
assign out_roready_1_555 = _out_rofireMux_T_906; // @[RegisterRouter.scala:87:24]
assign out_roready_1_556 = _out_rofireMux_T_906; // @[RegisterRouter.scala:87:24]
assign out_roready_1_557 = _out_rofireMux_T_906; // @[RegisterRouter.scala:87:24]
assign out_roready_1_558 = _out_rofireMux_T_906; // @[RegisterRouter.scala:87:24]
assign out_roready_1_559 = _out_rofireMux_T_906; // @[RegisterRouter.scala:87:24]
assign out_roready_1_560 = _out_rofireMux_T_906; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_907 = ~_out_T_1745; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_909 = _out_rofireMux_T_260 & out_backSel_162; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_910 = _out_rofireMux_T_909 & _out_T_1809; // @[RegisterRouter.scala:87:24]
assign out_roready_1_803 = _out_rofireMux_T_910; // @[RegisterRouter.scala:87:24]
assign out_roready_1_804 = _out_rofireMux_T_910; // @[RegisterRouter.scala:87:24]
assign out_roready_1_805 = _out_rofireMux_T_910; // @[RegisterRouter.scala:87:24]
assign out_roready_1_806 = _out_rofireMux_T_910; // @[RegisterRouter.scala:87:24]
assign out_roready_1_807 = _out_rofireMux_T_910; // @[RegisterRouter.scala:87:24]
assign out_roready_1_808 = _out_rofireMux_T_910; // @[RegisterRouter.scala:87:24]
assign out_roready_1_809 = _out_rofireMux_T_910; // @[RegisterRouter.scala:87:24]
assign out_roready_1_810 = _out_rofireMux_T_910; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_911 = ~_out_T_1809; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_913 = _out_rofireMux_T_260 & out_backSel_163; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_914 = _out_rofireMux_T_913 & _out_T_1895; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1147 = _out_rofireMux_T_914; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1148 = _out_rofireMux_T_914; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1149 = _out_rofireMux_T_914; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1150 = _out_rofireMux_T_914; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1151 = _out_rofireMux_T_914; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1152 = _out_rofireMux_T_914; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1153 = _out_rofireMux_T_914; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1154 = _out_rofireMux_T_914; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_915 = ~_out_T_1895; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_917 = _out_rofireMux_T_260 & out_backSel_164; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_918 = _out_rofireMux_T_917 & _out_T_1645; // @[RegisterRouter.scala:87:24]
assign out_roready_1_176 = _out_rofireMux_T_918; // @[RegisterRouter.scala:87:24]
assign out_roready_1_177 = _out_rofireMux_T_918; // @[RegisterRouter.scala:87:24]
assign out_roready_1_178 = _out_rofireMux_T_918; // @[RegisterRouter.scala:87:24]
assign out_roready_1_179 = _out_rofireMux_T_918; // @[RegisterRouter.scala:87:24]
assign out_roready_1_180 = _out_rofireMux_T_918; // @[RegisterRouter.scala:87:24]
assign out_roready_1_181 = _out_rofireMux_T_918; // @[RegisterRouter.scala:87:24]
assign out_roready_1_182 = _out_rofireMux_T_918; // @[RegisterRouter.scala:87:24]
assign out_roready_1_183 = _out_rofireMux_T_918; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_919 = ~_out_T_1645; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_921 = _out_rofireMux_T_260 & out_backSel_165; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_922 = _out_rofireMux_T_921 & _out_T_1687; // @[RegisterRouter.scala:87:24]
assign out_roready_1_344 = _out_rofireMux_T_922; // @[RegisterRouter.scala:87:24]
assign out_roready_1_345 = _out_rofireMux_T_922; // @[RegisterRouter.scala:87:24]
assign out_roready_1_346 = _out_rofireMux_T_922; // @[RegisterRouter.scala:87:24]
assign out_roready_1_347 = _out_rofireMux_T_922; // @[RegisterRouter.scala:87:24]
assign out_roready_1_348 = _out_rofireMux_T_922; // @[RegisterRouter.scala:87:24]
assign out_roready_1_349 = _out_rofireMux_T_922; // @[RegisterRouter.scala:87:24]
assign out_roready_1_350 = _out_rofireMux_T_922; // @[RegisterRouter.scala:87:24]
assign out_roready_1_351 = _out_rofireMux_T_922; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_923 = ~_out_T_1687; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_925 = _out_rofireMux_T_260 & out_backSel_166; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_926 = _out_rofireMux_T_925 & _out_T_1737; // @[RegisterRouter.scala:87:24]
assign out_roready_1_527 = _out_rofireMux_T_926; // @[RegisterRouter.scala:87:24]
assign out_roready_1_528 = _out_rofireMux_T_926; // @[RegisterRouter.scala:87:24]
assign out_roready_1_529 = _out_rofireMux_T_926; // @[RegisterRouter.scala:87:24]
assign out_roready_1_530 = _out_rofireMux_T_926; // @[RegisterRouter.scala:87:24]
assign out_roready_1_531 = _out_rofireMux_T_926; // @[RegisterRouter.scala:87:24]
assign out_roready_1_532 = _out_rofireMux_T_926; // @[RegisterRouter.scala:87:24]
assign out_roready_1_533 = _out_rofireMux_T_926; // @[RegisterRouter.scala:87:24]
assign out_roready_1_534 = _out_rofireMux_T_926; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_927 = ~_out_T_1737; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_929 = _out_rofireMux_T_260 & out_backSel_167; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_930 = _out_rofireMux_T_929 & _out_T_1807; // @[RegisterRouter.scala:87:24]
assign out_roready_1_795 = _out_rofireMux_T_930; // @[RegisterRouter.scala:87:24]
assign out_roready_1_796 = _out_rofireMux_T_930; // @[RegisterRouter.scala:87:24]
assign out_roready_1_797 = _out_rofireMux_T_930; // @[RegisterRouter.scala:87:24]
assign out_roready_1_798 = _out_rofireMux_T_930; // @[RegisterRouter.scala:87:24]
assign out_roready_1_799 = _out_rofireMux_T_930; // @[RegisterRouter.scala:87:24]
assign out_roready_1_800 = _out_rofireMux_T_930; // @[RegisterRouter.scala:87:24]
assign out_roready_1_801 = _out_rofireMux_T_930; // @[RegisterRouter.scala:87:24]
assign out_roready_1_802 = _out_rofireMux_T_930; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_931 = ~_out_T_1807; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_933 = _out_rofireMux_T_260 & out_backSel_168; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_934 = _out_rofireMux_T_933 & _out_T_1875; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1067 = _out_rofireMux_T_934; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1068 = _out_rofireMux_T_934; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1069 = _out_rofireMux_T_934; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1070 = _out_rofireMux_T_934; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1071 = _out_rofireMux_T_934; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1072 = _out_rofireMux_T_934; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1073 = _out_rofireMux_T_934; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1074 = _out_rofireMux_T_934; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_935 = ~_out_T_1875; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_937 = _out_rofireMux_T_260 & out_backSel_169; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_938 = _out_rofireMux_T_937 & _out_T_1703; // @[RegisterRouter.scala:87:24]
assign out_roready_1_402 = _out_rofireMux_T_938; // @[RegisterRouter.scala:87:24]
assign out_roready_1_403 = _out_rofireMux_T_938; // @[RegisterRouter.scala:87:24]
assign out_roready_1_404 = _out_rofireMux_T_938; // @[RegisterRouter.scala:87:24]
assign out_roready_1_405 = _out_rofireMux_T_938; // @[RegisterRouter.scala:87:24]
assign out_roready_1_406 = _out_rofireMux_T_938; // @[RegisterRouter.scala:87:24]
assign out_roready_1_407 = _out_rofireMux_T_938; // @[RegisterRouter.scala:87:24]
assign out_roready_1_408 = _out_rofireMux_T_938; // @[RegisterRouter.scala:87:24]
assign out_roready_1_409 = _out_rofireMux_T_938; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_939 = ~_out_T_1703; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_941 = _out_rofireMux_T_260 & out_backSel_170; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_942 = _out_rofireMux_T_941 & _out_T_1607; // @[RegisterRouter.scala:87:24]
assign out_roready_1_24 = _out_rofireMux_T_942; // @[RegisterRouter.scala:87:24]
assign out_roready_1_25 = _out_rofireMux_T_942; // @[RegisterRouter.scala:87:24]
assign out_roready_1_26 = _out_rofireMux_T_942; // @[RegisterRouter.scala:87:24]
assign out_roready_1_27 = _out_rofireMux_T_942; // @[RegisterRouter.scala:87:24]
assign out_roready_1_28 = _out_rofireMux_T_942; // @[RegisterRouter.scala:87:24]
assign out_roready_1_29 = _out_rofireMux_T_942; // @[RegisterRouter.scala:87:24]
assign out_roready_1_30 = _out_rofireMux_T_942; // @[RegisterRouter.scala:87:24]
assign out_roready_1_31 = _out_rofireMux_T_942; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_943 = ~_out_T_1607; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_945 = _out_rofireMux_T_260 & out_backSel_171; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_946 = _out_rofireMux_T_945 & _out_T_1855; // @[RegisterRouter.scala:87:24]
assign out_roready_1_987 = _out_rofireMux_T_946; // @[RegisterRouter.scala:87:24]
assign out_roready_1_988 = _out_rofireMux_T_946; // @[RegisterRouter.scala:87:24]
assign out_roready_1_989 = _out_rofireMux_T_946; // @[RegisterRouter.scala:87:24]
assign out_roready_1_990 = _out_rofireMux_T_946; // @[RegisterRouter.scala:87:24]
assign out_roready_1_991 = _out_rofireMux_T_946; // @[RegisterRouter.scala:87:24]
assign out_roready_1_992 = _out_rofireMux_T_946; // @[RegisterRouter.scala:87:24]
assign out_roready_1_993 = _out_rofireMux_T_946; // @[RegisterRouter.scala:87:24]
assign out_roready_1_994 = _out_rofireMux_T_946; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_947 = ~_out_T_1855; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_949 = _out_rofireMux_T_260 & out_backSel_172; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_950 = _out_rofireMux_T_949 & _out_T_1769; // @[RegisterRouter.scala:87:24]
assign out_roready_1_649 = _out_rofireMux_T_950; // @[RegisterRouter.scala:87:24]
assign out_roready_1_650 = _out_rofireMux_T_950; // @[RegisterRouter.scala:87:24]
assign out_roready_1_651 = _out_rofireMux_T_950; // @[RegisterRouter.scala:87:24]
assign out_roready_1_652 = _out_rofireMux_T_950; // @[RegisterRouter.scala:87:24]
assign out_roready_1_653 = _out_rofireMux_T_950; // @[RegisterRouter.scala:87:24]
assign out_roready_1_654 = _out_rofireMux_T_950; // @[RegisterRouter.scala:87:24]
assign out_roready_1_655 = _out_rofireMux_T_950; // @[RegisterRouter.scala:87:24]
assign out_roready_1_656 = _out_rofireMux_T_950; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_951 = ~_out_T_1769; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_953 = _out_rofireMux_T_260 & out_backSel_173; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_954 = _out_rofireMux_T_953 & _out_T_1719; // @[RegisterRouter.scala:87:24]
assign out_roready_1_459 = _out_rofireMux_T_954; // @[RegisterRouter.scala:87:24]
assign out_roready_1_460 = _out_rofireMux_T_954; // @[RegisterRouter.scala:87:24]
assign out_roready_1_461 = _out_rofireMux_T_954; // @[RegisterRouter.scala:87:24]
assign out_roready_1_462 = _out_rofireMux_T_954; // @[RegisterRouter.scala:87:24]
assign out_roready_1_463 = _out_rofireMux_T_954; // @[RegisterRouter.scala:87:24]
assign out_roready_1_464 = _out_rofireMux_T_954; // @[RegisterRouter.scala:87:24]
assign out_roready_1_465 = _out_rofireMux_T_954; // @[RegisterRouter.scala:87:24]
assign out_roready_1_466 = _out_rofireMux_T_954; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_955 = ~_out_T_1719; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_957 = _out_rofireMux_T_260 & out_backSel_174; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_958 = _out_rofireMux_T_957 & _out_T_1621; // @[RegisterRouter.scala:87:24]
assign out_roready_1_80 = _out_rofireMux_T_958; // @[RegisterRouter.scala:87:24]
assign out_roready_1_81 = _out_rofireMux_T_958; // @[RegisterRouter.scala:87:24]
assign out_roready_1_82 = _out_rofireMux_T_958; // @[RegisterRouter.scala:87:24]
assign out_roready_1_83 = _out_rofireMux_T_958; // @[RegisterRouter.scala:87:24]
assign out_roready_1_84 = _out_rofireMux_T_958; // @[RegisterRouter.scala:87:24]
assign out_roready_1_85 = _out_rofireMux_T_958; // @[RegisterRouter.scala:87:24]
assign out_roready_1_86 = _out_rofireMux_T_958; // @[RegisterRouter.scala:87:24]
assign out_roready_1_87 = _out_rofireMux_T_958; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_959 = ~_out_T_1621; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_961 = _out_rofireMux_T_260 & out_backSel_175; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_962 = _out_rofireMux_T_961 & _out_T_1833; // @[RegisterRouter.scala:87:24]
assign out_roready_1_899 = _out_rofireMux_T_962; // @[RegisterRouter.scala:87:24]
assign out_roready_1_900 = _out_rofireMux_T_962; // @[RegisterRouter.scala:87:24]
assign out_roready_1_901 = _out_rofireMux_T_962; // @[RegisterRouter.scala:87:24]
assign out_roready_1_902 = _out_rofireMux_T_962; // @[RegisterRouter.scala:87:24]
assign out_roready_1_903 = _out_rofireMux_T_962; // @[RegisterRouter.scala:87:24]
assign out_roready_1_904 = _out_rofireMux_T_962; // @[RegisterRouter.scala:87:24]
assign out_roready_1_905 = _out_rofireMux_T_962; // @[RegisterRouter.scala:87:24]
assign out_roready_1_906 = _out_rofireMux_T_962; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_963 = ~_out_T_1833; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_965 = _out_rofireMux_T_260 & out_backSel_176; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_966 = _out_rofireMux_T_965 & _out_T_1751; // @[RegisterRouter.scala:87:24]
assign out_roready_1_577 = _out_rofireMux_T_966; // @[RegisterRouter.scala:87:24]
assign out_roready_1_578 = _out_rofireMux_T_966; // @[RegisterRouter.scala:87:24]
assign out_roready_1_579 = _out_rofireMux_T_966; // @[RegisterRouter.scala:87:24]
assign out_roready_1_580 = _out_rofireMux_T_966; // @[RegisterRouter.scala:87:24]
assign out_roready_1_581 = _out_rofireMux_T_966; // @[RegisterRouter.scala:87:24]
assign out_roready_1_582 = _out_rofireMux_T_966; // @[RegisterRouter.scala:87:24]
assign out_roready_1_583 = _out_rofireMux_T_966; // @[RegisterRouter.scala:87:24]
assign out_roready_1_584 = _out_rofireMux_T_966; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_967 = ~_out_T_1751; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_969 = _out_rofireMux_T_260 & out_backSel_177; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_970 = _out_rofireMux_T_969 & _out_T_1827; // @[RegisterRouter.scala:87:24]
assign out_roready_1_875 = _out_rofireMux_T_970; // @[RegisterRouter.scala:87:24]
assign out_roready_1_876 = _out_rofireMux_T_970; // @[RegisterRouter.scala:87:24]
assign out_roready_1_877 = _out_rofireMux_T_970; // @[RegisterRouter.scala:87:24]
assign out_roready_1_878 = _out_rofireMux_T_970; // @[RegisterRouter.scala:87:24]
assign out_roready_1_879 = _out_rofireMux_T_970; // @[RegisterRouter.scala:87:24]
assign out_roready_1_880 = _out_rofireMux_T_970; // @[RegisterRouter.scala:87:24]
assign out_roready_1_881 = _out_rofireMux_T_970; // @[RegisterRouter.scala:87:24]
assign out_roready_1_882 = _out_rofireMux_T_970; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_971 = ~_out_T_1827; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_973 = _out_rofireMux_T_260 & out_backSel_178; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_974 = _out_rofireMux_T_973 & _out_T_1893; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1139 = _out_rofireMux_T_974; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1140 = _out_rofireMux_T_974; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1141 = _out_rofireMux_T_974; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1142 = _out_rofireMux_T_974; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1143 = _out_rofireMux_T_974; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1144 = _out_rofireMux_T_974; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1145 = _out_rofireMux_T_974; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1146 = _out_rofireMux_T_974; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_975 = ~_out_T_1893; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_977 = _out_rofireMux_T_260 & out_backSel_179; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_978 = _out_rofireMux_T_977 & _out_T_1647; // @[RegisterRouter.scala:87:24]
assign out_roready_1_184 = _out_rofireMux_T_978; // @[RegisterRouter.scala:87:24]
assign out_roready_1_185 = _out_rofireMux_T_978; // @[RegisterRouter.scala:87:24]
assign out_roready_1_186 = _out_rofireMux_T_978; // @[RegisterRouter.scala:87:24]
assign out_roready_1_187 = _out_rofireMux_T_978; // @[RegisterRouter.scala:87:24]
assign out_roready_1_188 = _out_rofireMux_T_978; // @[RegisterRouter.scala:87:24]
assign out_roready_1_189 = _out_rofireMux_T_978; // @[RegisterRouter.scala:87:24]
assign out_roready_1_190 = _out_rofireMux_T_978; // @[RegisterRouter.scala:87:24]
assign out_roready_1_191 = _out_rofireMux_T_978; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_979 = ~_out_T_1647; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_981 = _out_rofireMux_T_260 & out_backSel_180; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_982 = _out_rofireMux_T_981 & _out_T_1747; // @[RegisterRouter.scala:87:24]
assign out_roready_1_561 = _out_rofireMux_T_982; // @[RegisterRouter.scala:87:24]
assign out_roready_1_562 = _out_rofireMux_T_982; // @[RegisterRouter.scala:87:24]
assign out_roready_1_563 = _out_rofireMux_T_982; // @[RegisterRouter.scala:87:24]
assign out_roready_1_564 = _out_rofireMux_T_982; // @[RegisterRouter.scala:87:24]
assign out_roready_1_565 = _out_rofireMux_T_982; // @[RegisterRouter.scala:87:24]
assign out_roready_1_566 = _out_rofireMux_T_982; // @[RegisterRouter.scala:87:24]
assign out_roready_1_567 = _out_rofireMux_T_982; // @[RegisterRouter.scala:87:24]
assign out_roready_1_568 = _out_rofireMux_T_982; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_983 = ~_out_T_1747; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_985 = _out_rofireMux_T_260 & out_backSel_181; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_986 = _out_rofireMux_T_985 & _out_T_1763; // @[RegisterRouter.scala:87:24]
assign out_roready_1_625 = _out_rofireMux_T_986; // @[RegisterRouter.scala:87:24]
assign out_roready_1_626 = _out_rofireMux_T_986; // @[RegisterRouter.scala:87:24]
assign out_roready_1_627 = _out_rofireMux_T_986; // @[RegisterRouter.scala:87:24]
assign out_roready_1_628 = _out_rofireMux_T_986; // @[RegisterRouter.scala:87:24]
assign out_roready_1_629 = _out_rofireMux_T_986; // @[RegisterRouter.scala:87:24]
assign out_roready_1_630 = _out_rofireMux_T_986; // @[RegisterRouter.scala:87:24]
assign out_roready_1_631 = _out_rofireMux_T_986; // @[RegisterRouter.scala:87:24]
assign out_roready_1_632 = _out_rofireMux_T_986; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_987 = ~_out_T_1763; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_989 = _out_rofireMux_T_260 & out_backSel_182; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_990 = _out_rofireMux_T_989 & _out_T_1829; // @[RegisterRouter.scala:87:24]
assign out_roready_1_883 = _out_rofireMux_T_990; // @[RegisterRouter.scala:87:24]
assign out_roready_1_884 = _out_rofireMux_T_990; // @[RegisterRouter.scala:87:24]
assign out_roready_1_885 = _out_rofireMux_T_990; // @[RegisterRouter.scala:87:24]
assign out_roready_1_886 = _out_rofireMux_T_990; // @[RegisterRouter.scala:87:24]
assign out_roready_1_887 = _out_rofireMux_T_990; // @[RegisterRouter.scala:87:24]
assign out_roready_1_888 = _out_rofireMux_T_990; // @[RegisterRouter.scala:87:24]
assign out_roready_1_889 = _out_rofireMux_T_990; // @[RegisterRouter.scala:87:24]
assign out_roready_1_890 = _out_rofireMux_T_990; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_991 = ~_out_T_1829; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_993 = _out_rofireMux_T_260 & out_backSel_183; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_994 = _out_rofireMux_T_993 & _out_T_1873; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1059 = _out_rofireMux_T_994; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1060 = _out_rofireMux_T_994; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1061 = _out_rofireMux_T_994; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1062 = _out_rofireMux_T_994; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1063 = _out_rofireMux_T_994; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1064 = _out_rofireMux_T_994; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1065 = _out_rofireMux_T_994; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1066 = _out_rofireMux_T_994; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_995 = ~_out_T_1873; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_997 = _out_rofireMux_T_260 & out_backSel_184; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_998 = _out_rofireMux_T_997 & _out_T_1627; // @[RegisterRouter.scala:87:24]
assign out_roready_1_104 = _out_rofireMux_T_998; // @[RegisterRouter.scala:87:24]
assign out_roready_1_105 = _out_rofireMux_T_998; // @[RegisterRouter.scala:87:24]
assign out_roready_1_106 = _out_rofireMux_T_998; // @[RegisterRouter.scala:87:24]
assign out_roready_1_107 = _out_rofireMux_T_998; // @[RegisterRouter.scala:87:24]
assign out_roready_1_108 = _out_rofireMux_T_998; // @[RegisterRouter.scala:87:24]
assign out_roready_1_109 = _out_rofireMux_T_998; // @[RegisterRouter.scala:87:24]
assign out_roready_1_110 = _out_rofireMux_T_998; // @[RegisterRouter.scala:87:24]
assign out_roready_1_111 = _out_rofireMux_T_998; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_999 = ~_out_T_1627; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1001 = _out_rofireMux_T_260 & out_backSel_185; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_1002 = _out_rofireMux_T_1001 & _out_T_1623; // @[RegisterRouter.scala:87:24]
assign out_roready_1_88 = _out_rofireMux_T_1002; // @[RegisterRouter.scala:87:24]
assign out_roready_1_89 = _out_rofireMux_T_1002; // @[RegisterRouter.scala:87:24]
assign out_roready_1_90 = _out_rofireMux_T_1002; // @[RegisterRouter.scala:87:24]
assign out_roready_1_91 = _out_rofireMux_T_1002; // @[RegisterRouter.scala:87:24]
assign out_roready_1_92 = _out_rofireMux_T_1002; // @[RegisterRouter.scala:87:24]
assign out_roready_1_93 = _out_rofireMux_T_1002; // @[RegisterRouter.scala:87:24]
assign out_roready_1_94 = _out_rofireMux_T_1002; // @[RegisterRouter.scala:87:24]
assign out_roready_1_95 = _out_rofireMux_T_1002; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1003 = ~_out_T_1623; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1005 = _out_rofireMux_T_260 & out_backSel_186; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_1006 = _out_rofireMux_T_1005 & _out_T_1851; // @[RegisterRouter.scala:87:24]
assign out_roready_1_971 = _out_rofireMux_T_1006; // @[RegisterRouter.scala:87:24]
assign out_roready_1_972 = _out_rofireMux_T_1006; // @[RegisterRouter.scala:87:24]
assign out_roready_1_973 = _out_rofireMux_T_1006; // @[RegisterRouter.scala:87:24]
assign out_roready_1_974 = _out_rofireMux_T_1006; // @[RegisterRouter.scala:87:24]
assign out_roready_1_975 = _out_rofireMux_T_1006; // @[RegisterRouter.scala:87:24]
assign out_roready_1_976 = _out_rofireMux_T_1006; // @[RegisterRouter.scala:87:24]
assign out_roready_1_977 = _out_rofireMux_T_1006; // @[RegisterRouter.scala:87:24]
assign out_roready_1_978 = _out_rofireMux_T_1006; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1007 = ~_out_T_1851; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1009 = _out_rofireMux_T_260 & out_backSel_187; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_1010 = _out_rofireMux_T_1009 & _out_T_1767; // @[RegisterRouter.scala:87:24]
assign out_roready_1_641 = _out_rofireMux_T_1010; // @[RegisterRouter.scala:87:24]
assign out_roready_1_642 = _out_rofireMux_T_1010; // @[RegisterRouter.scala:87:24]
assign out_roready_1_643 = _out_rofireMux_T_1010; // @[RegisterRouter.scala:87:24]
assign out_roready_1_644 = _out_rofireMux_T_1010; // @[RegisterRouter.scala:87:24]
assign out_roready_1_645 = _out_rofireMux_T_1010; // @[RegisterRouter.scala:87:24]
assign out_roready_1_646 = _out_rofireMux_T_1010; // @[RegisterRouter.scala:87:24]
assign out_roready_1_647 = _out_rofireMux_T_1010; // @[RegisterRouter.scala:87:24]
assign out_roready_1_648 = _out_rofireMux_T_1010; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1011 = ~_out_T_1767; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1013 = _out_rofireMux_T_260 & out_backSel_188; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_1014 = _out_rofireMux_T_1013 & _out_T_1701; // @[RegisterRouter.scala:87:24]
assign out_roready_1_394 = _out_rofireMux_T_1014; // @[RegisterRouter.scala:87:24]
assign out_roready_1_395 = _out_rofireMux_T_1014; // @[RegisterRouter.scala:87:24]
assign out_roready_1_396 = _out_rofireMux_T_1014; // @[RegisterRouter.scala:87:24]
assign out_roready_1_397 = _out_rofireMux_T_1014; // @[RegisterRouter.scala:87:24]
assign out_roready_1_398 = _out_rofireMux_T_1014; // @[RegisterRouter.scala:87:24]
assign out_roready_1_399 = _out_rofireMux_T_1014; // @[RegisterRouter.scala:87:24]
assign out_roready_1_400 = _out_rofireMux_T_1014; // @[RegisterRouter.scala:87:24]
assign out_roready_1_401 = _out_rofireMux_T_1014; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1015 = ~_out_T_1701; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1017 = _out_rofireMux_T_260 & out_backSel_189; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_1018 = _out_rofireMux_T_1017 & _out_T_1635; // @[RegisterRouter.scala:87:24]
assign out_roready_1_136 = _out_rofireMux_T_1018; // @[RegisterRouter.scala:87:24]
assign out_roready_1_137 = _out_rofireMux_T_1018; // @[RegisterRouter.scala:87:24]
assign out_roready_1_138 = _out_rofireMux_T_1018; // @[RegisterRouter.scala:87:24]
assign out_roready_1_139 = _out_rofireMux_T_1018; // @[RegisterRouter.scala:87:24]
assign out_roready_1_140 = _out_rofireMux_T_1018; // @[RegisterRouter.scala:87:24]
assign out_roready_1_141 = _out_rofireMux_T_1018; // @[RegisterRouter.scala:87:24]
assign out_roready_1_142 = _out_rofireMux_T_1018; // @[RegisterRouter.scala:87:24]
assign out_roready_1_143 = _out_rofireMux_T_1018; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1019 = ~_out_T_1635; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1021 = _out_rofireMux_T_260 & out_backSel_190; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_1022 = _out_rofireMux_T_1021 & _out_T_1871; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1051 = _out_rofireMux_T_1022; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1052 = _out_rofireMux_T_1022; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1053 = _out_rofireMux_T_1022; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1054 = _out_rofireMux_T_1022; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1055 = _out_rofireMux_T_1022; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1056 = _out_rofireMux_T_1022; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1057 = _out_rofireMux_T_1022; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1058 = _out_rofireMux_T_1022; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1023 = ~_out_T_1871; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1025 = _out_rofireMux_T_260 & out_backSel_191; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_1026 = _out_rofireMux_T_1025 & _out_T_1753; // @[RegisterRouter.scala:87:24]
assign out_roready_1_585 = _out_rofireMux_T_1026; // @[RegisterRouter.scala:87:24]
assign out_roready_1_586 = _out_rofireMux_T_1026; // @[RegisterRouter.scala:87:24]
assign out_roready_1_587 = _out_rofireMux_T_1026; // @[RegisterRouter.scala:87:24]
assign out_roready_1_588 = _out_rofireMux_T_1026; // @[RegisterRouter.scala:87:24]
assign out_roready_1_589 = _out_rofireMux_T_1026; // @[RegisterRouter.scala:87:24]
assign out_roready_1_590 = _out_rofireMux_T_1026; // @[RegisterRouter.scala:87:24]
assign out_roready_1_591 = _out_rofireMux_T_1026; // @[RegisterRouter.scala:87:24]
assign out_roready_1_592 = _out_rofireMux_T_1026; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1027 = ~_out_T_1753; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1029 = _out_rofireMux_T_260 & out_backSel_192; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_1030 = _out_rofireMux_T_1029 & _out_T_1683; // @[RegisterRouter.scala:87:24]
assign out_roready_1_328 = _out_rofireMux_T_1030; // @[RegisterRouter.scala:87:24]
assign out_roready_1_329 = _out_rofireMux_T_1030; // @[RegisterRouter.scala:87:24]
assign out_roready_1_330 = _out_rofireMux_T_1030; // @[RegisterRouter.scala:87:24]
assign out_roready_1_331 = _out_rofireMux_T_1030; // @[RegisterRouter.scala:87:24]
assign out_roready_1_332 = _out_rofireMux_T_1030; // @[RegisterRouter.scala:87:24]
assign out_roready_1_333 = _out_rofireMux_T_1030; // @[RegisterRouter.scala:87:24]
assign out_roready_1_334 = _out_rofireMux_T_1030; // @[RegisterRouter.scala:87:24]
assign out_roready_1_335 = _out_rofireMux_T_1030; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1031 = ~_out_T_1683; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1033 = _out_rofireMux_T_260 & out_backSel_193; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_1034 = _out_rofireMux_T_1033 & _out_T_1709; // @[RegisterRouter.scala:87:24]
assign out_roready_1_426 = _out_rofireMux_T_1034; // @[RegisterRouter.scala:87:24]
assign out_roready_1_427 = _out_rofireMux_T_1034; // @[RegisterRouter.scala:87:24]
assign out_roready_1_428 = _out_rofireMux_T_1034; // @[RegisterRouter.scala:87:24]
assign out_roready_1_429 = _out_rofireMux_T_1034; // @[RegisterRouter.scala:87:24]
assign out_roready_1_430 = _out_rofireMux_T_1034; // @[RegisterRouter.scala:87:24]
assign out_roready_1_431 = _out_rofireMux_T_1034; // @[RegisterRouter.scala:87:24]
assign out_roready_1_432 = _out_rofireMux_T_1034; // @[RegisterRouter.scala:87:24]
assign out_roready_1_433 = _out_rofireMux_T_1034; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1035 = ~_out_T_1709; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1037 = _out_rofireMux_T_260 & out_backSel_194; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_1038 = _out_rofireMux_T_1037 & _out_T_1817; // @[RegisterRouter.scala:87:24]
assign out_roready_1_835 = _out_rofireMux_T_1038; // @[RegisterRouter.scala:87:24]
assign out_roready_1_836 = _out_rofireMux_T_1038; // @[RegisterRouter.scala:87:24]
assign out_roready_1_837 = _out_rofireMux_T_1038; // @[RegisterRouter.scala:87:24]
assign out_roready_1_838 = _out_rofireMux_T_1038; // @[RegisterRouter.scala:87:24]
assign out_roready_1_839 = _out_rofireMux_T_1038; // @[RegisterRouter.scala:87:24]
assign out_roready_1_840 = _out_rofireMux_T_1038; // @[RegisterRouter.scala:87:24]
assign out_roready_1_841 = _out_rofireMux_T_1038; // @[RegisterRouter.scala:87:24]
assign out_roready_1_842 = _out_rofireMux_T_1038; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1039 = ~_out_T_1817; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1041 = _out_rofireMux_T_260 & out_backSel_195; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_1042 = _out_rofireMux_T_1041 & _out_T_1885; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1107 = _out_rofireMux_T_1042; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1108 = _out_rofireMux_T_1042; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1109 = _out_rofireMux_T_1042; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1110 = _out_rofireMux_T_1042; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1111 = _out_rofireMux_T_1042; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1112 = _out_rofireMux_T_1042; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1113 = _out_rofireMux_T_1042; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1114 = _out_rofireMux_T_1042; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1043 = ~_out_T_1885; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1045 = _out_rofireMux_T_260 & out_backSel_196; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_1046 = _out_rofireMux_T_1045 & _out_T_1631; // @[RegisterRouter.scala:87:24]
assign out_roready_1_120 = _out_rofireMux_T_1046; // @[RegisterRouter.scala:87:24]
assign out_roready_1_121 = _out_rofireMux_T_1046; // @[RegisterRouter.scala:87:24]
assign out_roready_1_122 = _out_rofireMux_T_1046; // @[RegisterRouter.scala:87:24]
assign out_roready_1_123 = _out_rofireMux_T_1046; // @[RegisterRouter.scala:87:24]
assign out_roready_1_124 = _out_rofireMux_T_1046; // @[RegisterRouter.scala:87:24]
assign out_roready_1_125 = _out_rofireMux_T_1046; // @[RegisterRouter.scala:87:24]
assign out_roready_1_126 = _out_rofireMux_T_1046; // @[RegisterRouter.scala:87:24]
assign out_roready_1_127 = _out_rofireMux_T_1046; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1047 = ~_out_T_1631; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1049 = _out_rofireMux_T_260 & out_backSel_197; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_1050 = _out_rofireMux_T_1049 & _out_T_1695; // @[RegisterRouter.scala:87:24]
assign out_roready_1_370 = _out_rofireMux_T_1050; // @[RegisterRouter.scala:87:24]
assign out_roready_1_371 = _out_rofireMux_T_1050; // @[RegisterRouter.scala:87:24]
assign out_roready_1_372 = _out_rofireMux_T_1050; // @[RegisterRouter.scala:87:24]
assign out_roready_1_373 = _out_rofireMux_T_1050; // @[RegisterRouter.scala:87:24]
assign out_roready_1_374 = _out_rofireMux_T_1050; // @[RegisterRouter.scala:87:24]
assign out_roready_1_375 = _out_rofireMux_T_1050; // @[RegisterRouter.scala:87:24]
assign out_roready_1_376 = _out_rofireMux_T_1050; // @[RegisterRouter.scala:87:24]
assign out_roready_1_377 = _out_rofireMux_T_1050; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1051 = ~_out_T_1695; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1053 = _out_rofireMux_T_260 & out_backSel_198; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_1054 = _out_rofireMux_T_1053 & _out_T_1789; // @[RegisterRouter.scala:87:24]
assign out_roready_1_723 = _out_rofireMux_T_1054; // @[RegisterRouter.scala:87:24]
assign out_roready_1_724 = _out_rofireMux_T_1054; // @[RegisterRouter.scala:87:24]
assign out_roready_1_725 = _out_rofireMux_T_1054; // @[RegisterRouter.scala:87:24]
assign out_roready_1_726 = _out_rofireMux_T_1054; // @[RegisterRouter.scala:87:24]
assign out_roready_1_727 = _out_rofireMux_T_1054; // @[RegisterRouter.scala:87:24]
assign out_roready_1_728 = _out_rofireMux_T_1054; // @[RegisterRouter.scala:87:24]
assign out_roready_1_729 = _out_rofireMux_T_1054; // @[RegisterRouter.scala:87:24]
assign out_roready_1_730 = _out_rofireMux_T_1054; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1055 = ~_out_T_1789; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1057 = _out_rofireMux_T_260 & out_backSel_199; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_1058 = _out_rofireMux_T_1057 & _out_T_1825; // @[RegisterRouter.scala:87:24]
assign out_roready_1_867 = _out_rofireMux_T_1058; // @[RegisterRouter.scala:87:24]
assign out_roready_1_868 = _out_rofireMux_T_1058; // @[RegisterRouter.scala:87:24]
assign out_roready_1_869 = _out_rofireMux_T_1058; // @[RegisterRouter.scala:87:24]
assign out_roready_1_870 = _out_rofireMux_T_1058; // @[RegisterRouter.scala:87:24]
assign out_roready_1_871 = _out_rofireMux_T_1058; // @[RegisterRouter.scala:87:24]
assign out_roready_1_872 = _out_rofireMux_T_1058; // @[RegisterRouter.scala:87:24]
assign out_roready_1_873 = _out_rofireMux_T_1058; // @[RegisterRouter.scala:87:24]
assign out_roready_1_874 = _out_rofireMux_T_1058; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1059 = ~_out_T_1825; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1061 = _out_rofireMux_T_260 & out_backSel_200; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_1062 = _out_rofireMux_T_1061 & _out_T_1897; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1155 = _out_rofireMux_T_1062; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1156 = _out_rofireMux_T_1062; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1157 = _out_rofireMux_T_1062; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1158 = _out_rofireMux_T_1062; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1159 = _out_rofireMux_T_1062; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1160 = _out_rofireMux_T_1062; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1161 = _out_rofireMux_T_1062; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1162 = _out_rofireMux_T_1062; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1063 = ~_out_T_1897; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1065 = _out_rofireMux_T_260 & out_backSel_201; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_1066 = _out_rofireMux_T_1065 & _out_T_1675; // @[RegisterRouter.scala:87:24]
assign out_roready_1_296 = _out_rofireMux_T_1066; // @[RegisterRouter.scala:87:24]
assign out_roready_1_297 = _out_rofireMux_T_1066; // @[RegisterRouter.scala:87:24]
assign out_roready_1_298 = _out_rofireMux_T_1066; // @[RegisterRouter.scala:87:24]
assign out_roready_1_299 = _out_rofireMux_T_1066; // @[RegisterRouter.scala:87:24]
assign out_roready_1_300 = _out_rofireMux_T_1066; // @[RegisterRouter.scala:87:24]
assign out_roready_1_301 = _out_rofireMux_T_1066; // @[RegisterRouter.scala:87:24]
assign out_roready_1_302 = _out_rofireMux_T_1066; // @[RegisterRouter.scala:87:24]
assign out_roready_1_303 = _out_rofireMux_T_1066; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1067 = ~_out_T_1675; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1069 = _out_rofireMux_T_260 & out_backSel_202; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_1070 = _out_rofireMux_T_1069 & _out_T_1615; // @[RegisterRouter.scala:87:24]
assign out_roready_1_56 = _out_rofireMux_T_1070; // @[RegisterRouter.scala:87:24]
assign out_roready_1_57 = _out_rofireMux_T_1070; // @[RegisterRouter.scala:87:24]
assign out_roready_1_58 = _out_rofireMux_T_1070; // @[RegisterRouter.scala:87:24]
assign out_roready_1_59 = _out_rofireMux_T_1070; // @[RegisterRouter.scala:87:24]
assign out_roready_1_60 = _out_rofireMux_T_1070; // @[RegisterRouter.scala:87:24]
assign out_roready_1_61 = _out_rofireMux_T_1070; // @[RegisterRouter.scala:87:24]
assign out_roready_1_62 = _out_rofireMux_T_1070; // @[RegisterRouter.scala:87:24]
assign out_roready_1_63 = _out_rofireMux_T_1070; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1071 = ~_out_T_1615; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1073 = _out_rofireMux_T_260 & out_backSel_203; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_1074 = _out_rofireMux_T_1073 & _out_T_1837; // @[RegisterRouter.scala:87:24]
assign out_roready_1_915 = _out_rofireMux_T_1074; // @[RegisterRouter.scala:87:24]
assign out_roready_1_916 = _out_rofireMux_T_1074; // @[RegisterRouter.scala:87:24]
assign out_roready_1_917 = _out_rofireMux_T_1074; // @[RegisterRouter.scala:87:24]
assign out_roready_1_918 = _out_rofireMux_T_1074; // @[RegisterRouter.scala:87:24]
assign out_roready_1_919 = _out_rofireMux_T_1074; // @[RegisterRouter.scala:87:24]
assign out_roready_1_920 = _out_rofireMux_T_1074; // @[RegisterRouter.scala:87:24]
assign out_roready_1_921 = _out_rofireMux_T_1074; // @[RegisterRouter.scala:87:24]
assign out_roready_1_922 = _out_rofireMux_T_1074; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1075 = ~_out_T_1837; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1077 = _out_rofireMux_T_260 & out_backSel_204; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_1078 = _out_rofireMux_T_1077 & _out_T_1755; // @[RegisterRouter.scala:87:24]
assign out_roready_1_593 = _out_rofireMux_T_1078; // @[RegisterRouter.scala:87:24]
assign out_roready_1_594 = _out_rofireMux_T_1078; // @[RegisterRouter.scala:87:24]
assign out_roready_1_595 = _out_rofireMux_T_1078; // @[RegisterRouter.scala:87:24]
assign out_roready_1_596 = _out_rofireMux_T_1078; // @[RegisterRouter.scala:87:24]
assign out_roready_1_597 = _out_rofireMux_T_1078; // @[RegisterRouter.scala:87:24]
assign out_roready_1_598 = _out_rofireMux_T_1078; // @[RegisterRouter.scala:87:24]
assign out_roready_1_599 = _out_rofireMux_T_1078; // @[RegisterRouter.scala:87:24]
assign out_roready_1_600 = _out_rofireMux_T_1078; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1079 = ~_out_T_1755; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1081 = _out_rofireMux_T_260 & out_backSel_205; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_1082 = _out_rofireMux_T_1081 & _out_T_1727; // @[RegisterRouter.scala:87:24]
assign out_roready_1_487 = _out_rofireMux_T_1082; // @[RegisterRouter.scala:87:24]
assign out_roready_1_488 = _out_rofireMux_T_1082; // @[RegisterRouter.scala:87:24]
assign out_roready_1_489 = _out_rofireMux_T_1082; // @[RegisterRouter.scala:87:24]
assign out_roready_1_490 = _out_rofireMux_T_1082; // @[RegisterRouter.scala:87:24]
assign out_roready_1_491 = _out_rofireMux_T_1082; // @[RegisterRouter.scala:87:24]
assign out_roready_1_492 = _out_rofireMux_T_1082; // @[RegisterRouter.scala:87:24]
assign out_roready_1_493 = _out_rofireMux_T_1082; // @[RegisterRouter.scala:87:24]
assign out_roready_1_494 = _out_rofireMux_T_1082; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1083 = ~_out_T_1727; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1085 = _out_rofireMux_T_260 & out_backSel_206; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_1086 = _out_rofireMux_T_1085 & _out_T_1669; // @[RegisterRouter.scala:87:24]
assign out_roready_1_272 = _out_rofireMux_T_1086; // @[RegisterRouter.scala:87:24]
assign out_roready_1_273 = _out_rofireMux_T_1086; // @[RegisterRouter.scala:87:24]
assign out_roready_1_274 = _out_rofireMux_T_1086; // @[RegisterRouter.scala:87:24]
assign out_roready_1_275 = _out_rofireMux_T_1086; // @[RegisterRouter.scala:87:24]
assign out_roready_1_276 = _out_rofireMux_T_1086; // @[RegisterRouter.scala:87:24]
assign out_roready_1_277 = _out_rofireMux_T_1086; // @[RegisterRouter.scala:87:24]
assign out_roready_1_278 = _out_rofireMux_T_1086; // @[RegisterRouter.scala:87:24]
assign out_roready_1_279 = _out_rofireMux_T_1086; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1087 = ~_out_T_1669; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1089 = _out_rofireMux_T_260 & out_backSel_207; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_1090 = _out_rofireMux_T_1089 & _out_T_1859; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1003 = _out_rofireMux_T_1090; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1004 = _out_rofireMux_T_1090; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1005 = _out_rofireMux_T_1090; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1006 = _out_rofireMux_T_1090; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1007 = _out_rofireMux_T_1090; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1008 = _out_rofireMux_T_1090; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1009 = _out_rofireMux_T_1090; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1010 = _out_rofireMux_T_1090; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1091 = ~_out_T_1859; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1093 = _out_rofireMux_T_260 & out_backSel_208; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_1094 = _out_rofireMux_T_1093 & _out_T_1779; // @[RegisterRouter.scala:87:24]
assign out_roready_1_689 = _out_rofireMux_T_1094; // @[RegisterRouter.scala:87:24]
assign out_roready_1_690 = _out_rofireMux_T_1094; // @[RegisterRouter.scala:87:24]
assign out_roready_1_691 = _out_rofireMux_T_1094; // @[RegisterRouter.scala:87:24]
assign out_roready_1_692 = _out_rofireMux_T_1094; // @[RegisterRouter.scala:87:24]
assign out_roready_1_693 = _out_rofireMux_T_1094; // @[RegisterRouter.scala:87:24]
assign out_roready_1_694 = _out_rofireMux_T_1094; // @[RegisterRouter.scala:87:24]
assign out_roready_1_695 = _out_rofireMux_T_1094; // @[RegisterRouter.scala:87:24]
assign out_roready_1_696 = _out_rofireMux_T_1094; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1095 = ~_out_T_1779; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1097 = _out_rofireMux_T_260 & out_backSel_209; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_1098 = _out_rofireMux_T_1097 & _out_T_1813; // @[RegisterRouter.scala:87:24]
assign out_roready_1_819 = _out_rofireMux_T_1098; // @[RegisterRouter.scala:87:24]
assign out_roready_1_820 = _out_rofireMux_T_1098; // @[RegisterRouter.scala:87:24]
assign out_roready_1_821 = _out_rofireMux_T_1098; // @[RegisterRouter.scala:87:24]
assign out_roready_1_822 = _out_rofireMux_T_1098; // @[RegisterRouter.scala:87:24]
assign out_roready_1_823 = _out_rofireMux_T_1098; // @[RegisterRouter.scala:87:24]
assign out_roready_1_824 = _out_rofireMux_T_1098; // @[RegisterRouter.scala:87:24]
assign out_roready_1_825 = _out_rofireMux_T_1098; // @[RegisterRouter.scala:87:24]
assign out_roready_1_826 = _out_rofireMux_T_1098; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1099 = ~_out_T_1813; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1101 = _out_rofireMux_T_260 & out_backSel_210; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_1102 = _out_rofireMux_T_1101 & _out_T_1879; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1083 = _out_rofireMux_T_1102; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1084 = _out_rofireMux_T_1102; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1085 = _out_rofireMux_T_1102; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1086 = _out_rofireMux_T_1102; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1087 = _out_rofireMux_T_1102; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1088 = _out_rofireMux_T_1102; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1089 = _out_rofireMux_T_1102; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1090 = _out_rofireMux_T_1102; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1103 = ~_out_T_1879; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1105 = _out_rofireMux_T_260 & out_backSel_211; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_1106 = _out_rofireMux_T_1105 & _out_T_1653; // @[RegisterRouter.scala:87:24]
assign out_roready_1_208 = _out_rofireMux_T_1106; // @[RegisterRouter.scala:87:24]
assign out_roready_1_209 = _out_rofireMux_T_1106; // @[RegisterRouter.scala:87:24]
assign out_roready_1_210 = _out_rofireMux_T_1106; // @[RegisterRouter.scala:87:24]
assign out_roready_1_211 = _out_rofireMux_T_1106; // @[RegisterRouter.scala:87:24]
assign out_roready_1_212 = _out_rofireMux_T_1106; // @[RegisterRouter.scala:87:24]
assign out_roready_1_213 = _out_rofireMux_T_1106; // @[RegisterRouter.scala:87:24]
assign out_roready_1_214 = _out_rofireMux_T_1106; // @[RegisterRouter.scala:87:24]
assign out_roready_1_215 = _out_rofireMux_T_1106; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1107 = ~_out_T_1653; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1109 = _out_rofireMux_T_260 & out_backSel_212; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_1110 = _out_rofireMux_T_1109 & _out_T_1711; // @[RegisterRouter.scala:87:24]
assign out_roready_1_434 = _out_rofireMux_T_1110; // @[RegisterRouter.scala:87:24]
assign out_roready_1_435 = _out_rofireMux_T_1110; // @[RegisterRouter.scala:87:24]
assign out_roready_1_436 = _out_rofireMux_T_1110; // @[RegisterRouter.scala:87:24]
assign out_roready_1_437 = _out_rofireMux_T_1110; // @[RegisterRouter.scala:87:24]
assign out_roready_1_438 = _out_rofireMux_T_1110; // @[RegisterRouter.scala:87:24]
assign out_roready_1_439 = _out_rofireMux_T_1110; // @[RegisterRouter.scala:87:24]
assign out_roready_1_440 = _out_rofireMux_T_1110; // @[RegisterRouter.scala:87:24]
assign out_roready_1_441 = _out_rofireMux_T_1110; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1111 = ~_out_T_1711; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1113 = _out_rofireMux_T_260 & out_backSel_213; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_1114 = _out_rofireMux_T_1113 & _out_T_1785; // @[RegisterRouter.scala:87:24]
assign out_roready_1_707 = _out_rofireMux_T_1114; // @[RegisterRouter.scala:87:24]
assign out_roready_1_708 = _out_rofireMux_T_1114; // @[RegisterRouter.scala:87:24]
assign out_roready_1_709 = _out_rofireMux_T_1114; // @[RegisterRouter.scala:87:24]
assign out_roready_1_710 = _out_rofireMux_T_1114; // @[RegisterRouter.scala:87:24]
assign out_roready_1_711 = _out_rofireMux_T_1114; // @[RegisterRouter.scala:87:24]
assign out_roready_1_712 = _out_rofireMux_T_1114; // @[RegisterRouter.scala:87:24]
assign out_roready_1_713 = _out_rofireMux_T_1114; // @[RegisterRouter.scala:87:24]
assign out_roready_1_714 = _out_rofireMux_T_1114; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1115 = ~_out_T_1785; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1117 = _out_rofireMux_T_260 & out_backSel_214; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_1118 = _out_rofireMux_T_1117 & _out_T_1861; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1011 = _out_rofireMux_T_1118; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1012 = _out_rofireMux_T_1118; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1013 = _out_rofireMux_T_1118; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1014 = _out_rofireMux_T_1118; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1015 = _out_rofireMux_T_1118; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1016 = _out_rofireMux_T_1118; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1017 = _out_rofireMux_T_1118; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1018 = _out_rofireMux_T_1118; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1119 = ~_out_T_1861; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1121 = _out_rofireMux_T_260 & out_backSel_215; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_1122 = _out_rofireMux_T_1121 & _out_T_1901; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1171 = _out_rofireMux_T_1122; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1172 = _out_rofireMux_T_1122; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1173 = _out_rofireMux_T_1122; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1174 = _out_rofireMux_T_1122; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1175 = _out_rofireMux_T_1122; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1176 = _out_rofireMux_T_1122; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1177 = _out_rofireMux_T_1122; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1178 = _out_rofireMux_T_1122; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1123 = ~_out_T_1901; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1125 = _out_rofireMux_T_260 & out_backSel_216; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_1126 = _out_rofireMux_T_1125 & _out_T_1643; // @[RegisterRouter.scala:87:24]
assign out_roready_1_168 = _out_rofireMux_T_1126; // @[RegisterRouter.scala:87:24]
assign out_roready_1_169 = _out_rofireMux_T_1126; // @[RegisterRouter.scala:87:24]
assign out_roready_1_170 = _out_rofireMux_T_1126; // @[RegisterRouter.scala:87:24]
assign out_roready_1_171 = _out_rofireMux_T_1126; // @[RegisterRouter.scala:87:24]
assign out_roready_1_172 = _out_rofireMux_T_1126; // @[RegisterRouter.scala:87:24]
assign out_roready_1_173 = _out_rofireMux_T_1126; // @[RegisterRouter.scala:87:24]
assign out_roready_1_174 = _out_rofireMux_T_1126; // @[RegisterRouter.scala:87:24]
assign out_roready_1_175 = _out_rofireMux_T_1126; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1127 = ~_out_T_1643; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1129 = _out_rofireMux_T_260 & out_backSel_217; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_1130 = _out_rofireMux_T_1129 & _out_T_1611; // @[RegisterRouter.scala:87:24]
assign out_roready_1_40 = _out_rofireMux_T_1130; // @[RegisterRouter.scala:87:24]
assign out_roready_1_41 = _out_rofireMux_T_1130; // @[RegisterRouter.scala:87:24]
assign out_roready_1_42 = _out_rofireMux_T_1130; // @[RegisterRouter.scala:87:24]
assign out_roready_1_43 = _out_rofireMux_T_1130; // @[RegisterRouter.scala:87:24]
assign out_roready_1_44 = _out_rofireMux_T_1130; // @[RegisterRouter.scala:87:24]
assign out_roready_1_45 = _out_rofireMux_T_1130; // @[RegisterRouter.scala:87:24]
assign out_roready_1_46 = _out_rofireMux_T_1130; // @[RegisterRouter.scala:87:24]
assign out_roready_1_47 = _out_rofireMux_T_1130; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1131 = ~_out_T_1611; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1133 = _out_rofireMux_T_260 & out_backSel_218; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_1134 = _out_rofireMux_T_1133 & _out_T_1839; // @[RegisterRouter.scala:87:24]
assign out_roready_1_923 = _out_rofireMux_T_1134; // @[RegisterRouter.scala:87:24]
assign out_roready_1_924 = _out_rofireMux_T_1134; // @[RegisterRouter.scala:87:24]
assign out_roready_1_925 = _out_rofireMux_T_1134; // @[RegisterRouter.scala:87:24]
assign out_roready_1_926 = _out_rofireMux_T_1134; // @[RegisterRouter.scala:87:24]
assign out_roready_1_927 = _out_rofireMux_T_1134; // @[RegisterRouter.scala:87:24]
assign out_roready_1_928 = _out_rofireMux_T_1134; // @[RegisterRouter.scala:87:24]
assign out_roready_1_929 = _out_rofireMux_T_1134; // @[RegisterRouter.scala:87:24]
assign out_roready_1_930 = _out_rofireMux_T_1134; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1135 = ~_out_T_1839; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1137 = _out_rofireMux_T_260 & out_backSel_219; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_1138 = _out_rofireMux_T_1137 & _out_T_1773; // @[RegisterRouter.scala:87:24]
assign out_roready_1_665 = _out_rofireMux_T_1138; // @[RegisterRouter.scala:87:24]
assign out_roready_1_666 = _out_rofireMux_T_1138; // @[RegisterRouter.scala:87:24]
assign out_roready_1_667 = _out_rofireMux_T_1138; // @[RegisterRouter.scala:87:24]
assign out_roready_1_668 = _out_rofireMux_T_1138; // @[RegisterRouter.scala:87:24]
assign out_roready_1_669 = _out_rofireMux_T_1138; // @[RegisterRouter.scala:87:24]
assign out_roready_1_670 = _out_rofireMux_T_1138; // @[RegisterRouter.scala:87:24]
assign out_roready_1_671 = _out_rofireMux_T_1138; // @[RegisterRouter.scala:87:24]
assign out_roready_1_672 = _out_rofireMux_T_1138; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1139 = ~_out_T_1773; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1141 = _out_rofireMux_T_260 & out_backSel_220; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_1142 = _out_rofireMux_T_1141 & _out_T_1677; // @[RegisterRouter.scala:87:24]
assign out_roready_1_304 = _out_rofireMux_T_1142; // @[RegisterRouter.scala:87:24]
assign out_roready_1_305 = _out_rofireMux_T_1142; // @[RegisterRouter.scala:87:24]
assign out_roready_1_306 = _out_rofireMux_T_1142; // @[RegisterRouter.scala:87:24]
assign out_roready_1_307 = _out_rofireMux_T_1142; // @[RegisterRouter.scala:87:24]
assign out_roready_1_308 = _out_rofireMux_T_1142; // @[RegisterRouter.scala:87:24]
assign out_roready_1_309 = _out_rofireMux_T_1142; // @[RegisterRouter.scala:87:24]
assign out_roready_1_310 = _out_rofireMux_T_1142; // @[RegisterRouter.scala:87:24]
assign out_roready_1_311 = _out_rofireMux_T_1142; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1143 = ~_out_T_1677; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1145 = _out_rofireMux_T_260 & out_backSel_221; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_1146 = _out_rofireMux_T_1145 & _out_T_1659; // @[RegisterRouter.scala:87:24]
assign out_roready_1_232 = _out_rofireMux_T_1146; // @[RegisterRouter.scala:87:24]
assign out_roready_1_233 = _out_rofireMux_T_1146; // @[RegisterRouter.scala:87:24]
assign out_roready_1_234 = _out_rofireMux_T_1146; // @[RegisterRouter.scala:87:24]
assign out_roready_1_235 = _out_rofireMux_T_1146; // @[RegisterRouter.scala:87:24]
assign out_roready_1_236 = _out_rofireMux_T_1146; // @[RegisterRouter.scala:87:24]
assign out_roready_1_237 = _out_rofireMux_T_1146; // @[RegisterRouter.scala:87:24]
assign out_roready_1_238 = _out_rofireMux_T_1146; // @[RegisterRouter.scala:87:24]
assign out_roready_1_239 = _out_rofireMux_T_1146; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1147 = ~_out_T_1659; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1149 = _out_rofireMux_T_260 & out_backSel_222; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_1150 = _out_rofireMux_T_1149 & _out_T_1903; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1179 = _out_rofireMux_T_1150; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1180 = _out_rofireMux_T_1150; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1181 = _out_rofireMux_T_1150; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1182 = _out_rofireMux_T_1150; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1183 = _out_rofireMux_T_1150; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1184 = _out_rofireMux_T_1150; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1185 = _out_rofireMux_T_1150; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1186 = _out_rofireMux_T_1150; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1151 = ~_out_T_1903; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1153 = _out_rofireMux_T_260 & out_backSel_223; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_1154 = _out_rofireMux_T_1153 & _out_T_1799; // @[RegisterRouter.scala:87:24]
assign out_roready_1_763 = _out_rofireMux_T_1154; // @[RegisterRouter.scala:87:24]
assign out_roready_1_764 = _out_rofireMux_T_1154; // @[RegisterRouter.scala:87:24]
assign out_roready_1_765 = _out_rofireMux_T_1154; // @[RegisterRouter.scala:87:24]
assign out_roready_1_766 = _out_rofireMux_T_1154; // @[RegisterRouter.scala:87:24]
assign out_roready_1_767 = _out_rofireMux_T_1154; // @[RegisterRouter.scala:87:24]
assign out_roready_1_768 = _out_rofireMux_T_1154; // @[RegisterRouter.scala:87:24]
assign out_roready_1_769 = _out_rofireMux_T_1154; // @[RegisterRouter.scala:87:24]
assign out_roready_1_770 = _out_rofireMux_T_1154; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1155 = ~_out_T_1799; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1157 = _out_rofireMux_T_260 & out_backSel_224; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_1158 = _out_rofireMux_T_1157 & _out_T_1697; // @[RegisterRouter.scala:87:24]
assign out_roready_1_378 = _out_rofireMux_T_1158; // @[RegisterRouter.scala:87:24]
assign out_roready_1_379 = _out_rofireMux_T_1158; // @[RegisterRouter.scala:87:24]
assign out_roready_1_380 = _out_rofireMux_T_1158; // @[RegisterRouter.scala:87:24]
assign out_roready_1_381 = _out_rofireMux_T_1158; // @[RegisterRouter.scala:87:24]
assign out_roready_1_382 = _out_rofireMux_T_1158; // @[RegisterRouter.scala:87:24]
assign out_roready_1_383 = _out_rofireMux_T_1158; // @[RegisterRouter.scala:87:24]
assign out_roready_1_384 = _out_rofireMux_T_1158; // @[RegisterRouter.scala:87:24]
assign out_roready_1_385 = _out_rofireMux_T_1158; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1159 = ~_out_T_1697; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1161 = _out_rofireMux_T_260 & out_backSel_225; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_1162 = _out_rofireMux_T_1161 & _out_T_1707; // @[RegisterRouter.scala:87:24]
assign out_roready_1_418 = _out_rofireMux_T_1162; // @[RegisterRouter.scala:87:24]
assign out_roready_1_419 = _out_rofireMux_T_1162; // @[RegisterRouter.scala:87:24]
assign out_roready_1_420 = _out_rofireMux_T_1162; // @[RegisterRouter.scala:87:24]
assign out_roready_1_421 = _out_rofireMux_T_1162; // @[RegisterRouter.scala:87:24]
assign out_roready_1_422 = _out_rofireMux_T_1162; // @[RegisterRouter.scala:87:24]
assign out_roready_1_423 = _out_rofireMux_T_1162; // @[RegisterRouter.scala:87:24]
assign out_roready_1_424 = _out_rofireMux_T_1162; // @[RegisterRouter.scala:87:24]
assign out_roready_1_425 = _out_rofireMux_T_1162; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1163 = ~_out_T_1707; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1165 = _out_rofireMux_T_260 & out_backSel_226; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_1166 = _out_rofireMux_T_1165 & _out_T_1803; // @[RegisterRouter.scala:87:24]
assign out_roready_1_779 = _out_rofireMux_T_1166; // @[RegisterRouter.scala:87:24]
assign out_roready_1_780 = _out_rofireMux_T_1166; // @[RegisterRouter.scala:87:24]
assign out_roready_1_781 = _out_rofireMux_T_1166; // @[RegisterRouter.scala:87:24]
assign out_roready_1_782 = _out_rofireMux_T_1166; // @[RegisterRouter.scala:87:24]
assign out_roready_1_783 = _out_rofireMux_T_1166; // @[RegisterRouter.scala:87:24]
assign out_roready_1_784 = _out_rofireMux_T_1166; // @[RegisterRouter.scala:87:24]
assign out_roready_1_785 = _out_rofireMux_T_1166; // @[RegisterRouter.scala:87:24]
assign out_roready_1_786 = _out_rofireMux_T_1166; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1167 = ~_out_T_1803; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1169 = _out_rofireMux_T_260 & out_backSel_227; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_1170 = _out_rofireMux_T_1169 & _out_T_1909; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1203 = _out_rofireMux_T_1170; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1204 = _out_rofireMux_T_1170; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1205 = _out_rofireMux_T_1170; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1206 = _out_rofireMux_T_1170; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1207 = _out_rofireMux_T_1170; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1208 = _out_rofireMux_T_1170; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1209 = _out_rofireMux_T_1170; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1210 = _out_rofireMux_T_1170; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1171 = ~_out_T_1909; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1173 = _out_rofireMux_T_260 & out_backSel_228; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_1174 = _out_rofireMux_T_1173 & _out_T_1639; // @[RegisterRouter.scala:87:24]
assign out_roready_1_152 = _out_rofireMux_T_1174; // @[RegisterRouter.scala:87:24]
assign out_roready_1_153 = _out_rofireMux_T_1174; // @[RegisterRouter.scala:87:24]
assign out_roready_1_154 = _out_rofireMux_T_1174; // @[RegisterRouter.scala:87:24]
assign out_roready_1_155 = _out_rofireMux_T_1174; // @[RegisterRouter.scala:87:24]
assign out_roready_1_156 = _out_rofireMux_T_1174; // @[RegisterRouter.scala:87:24]
assign out_roready_1_157 = _out_rofireMux_T_1174; // @[RegisterRouter.scala:87:24]
assign out_roready_1_158 = _out_rofireMux_T_1174; // @[RegisterRouter.scala:87:24]
assign out_roready_1_159 = _out_rofireMux_T_1174; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1175 = ~_out_T_1639; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1177 = _out_rofireMux_T_260 & out_backSel_229; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_1178 = _out_rofireMux_T_1177 & _out_T_1691; // @[RegisterRouter.scala:87:24]
assign out_roready_1_354 = _out_rofireMux_T_1178; // @[RegisterRouter.scala:87:24]
assign out_roready_1_355 = _out_rofireMux_T_1178; // @[RegisterRouter.scala:87:24]
assign out_roready_1_356 = _out_rofireMux_T_1178; // @[RegisterRouter.scala:87:24]
assign out_roready_1_357 = _out_rofireMux_T_1178; // @[RegisterRouter.scala:87:24]
assign out_roready_1_358 = _out_rofireMux_T_1178; // @[RegisterRouter.scala:87:24]
assign out_roready_1_359 = _out_rofireMux_T_1178; // @[RegisterRouter.scala:87:24]
assign out_roready_1_360 = _out_rofireMux_T_1178; // @[RegisterRouter.scala:87:24]
assign out_roready_1_361 = _out_rofireMux_T_1178; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1179 = ~_out_T_1691; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1181 = _out_rofireMux_T_260 & out_backSel_230; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_1182 = _out_rofireMux_T_1181 & _out_T_1775; // @[RegisterRouter.scala:87:24]
assign out_roready_1_673 = _out_rofireMux_T_1182; // @[RegisterRouter.scala:87:24]
assign out_roready_1_674 = _out_rofireMux_T_1182; // @[RegisterRouter.scala:87:24]
assign out_roready_1_675 = _out_rofireMux_T_1182; // @[RegisterRouter.scala:87:24]
assign out_roready_1_676 = _out_rofireMux_T_1182; // @[RegisterRouter.scala:87:24]
assign out_roready_1_677 = _out_rofireMux_T_1182; // @[RegisterRouter.scala:87:24]
assign out_roready_1_678 = _out_rofireMux_T_1182; // @[RegisterRouter.scala:87:24]
assign out_roready_1_679 = _out_rofireMux_T_1182; // @[RegisterRouter.scala:87:24]
assign out_roready_1_680 = _out_rofireMux_T_1182; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1183 = ~_out_T_1775; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1185 = _out_rofireMux_T_260 & out_backSel_231; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_1186 = _out_rofireMux_T_1185 & _out_T_1845; // @[RegisterRouter.scala:87:24]
assign out_roready_1_947 = _out_rofireMux_T_1186; // @[RegisterRouter.scala:87:24]
assign out_roready_1_948 = _out_rofireMux_T_1186; // @[RegisterRouter.scala:87:24]
assign out_roready_1_949 = _out_rofireMux_T_1186; // @[RegisterRouter.scala:87:24]
assign out_roready_1_950 = _out_rofireMux_T_1186; // @[RegisterRouter.scala:87:24]
assign out_roready_1_951 = _out_rofireMux_T_1186; // @[RegisterRouter.scala:87:24]
assign out_roready_1_952 = _out_rofireMux_T_1186; // @[RegisterRouter.scala:87:24]
assign out_roready_1_953 = _out_rofireMux_T_1186; // @[RegisterRouter.scala:87:24]
assign out_roready_1_954 = _out_rofireMux_T_1186; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1187 = ~_out_T_1845; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1189 = _out_rofireMux_T_260 & out_backSel_232; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_1190 = _out_rofireMux_T_1189 & _out_T_1905; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1187 = _out_rofireMux_T_1190; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1188 = _out_rofireMux_T_1190; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1189 = _out_rofireMux_T_1190; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1190 = _out_rofireMux_T_1190; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1191 = _out_rofireMux_T_1190; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1192 = _out_rofireMux_T_1190; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1193 = _out_rofireMux_T_1190; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1194 = _out_rofireMux_T_1190; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1191 = ~_out_T_1905; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1193 = _out_rofireMux_T_260 & out_backSel_233; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_1194 = _out_rofireMux_T_1193 & _out_T_1671; // @[RegisterRouter.scala:87:24]
assign out_roready_1_280 = _out_rofireMux_T_1194; // @[RegisterRouter.scala:87:24]
assign out_roready_1_281 = _out_rofireMux_T_1194; // @[RegisterRouter.scala:87:24]
assign out_roready_1_282 = _out_rofireMux_T_1194; // @[RegisterRouter.scala:87:24]
assign out_roready_1_283 = _out_rofireMux_T_1194; // @[RegisterRouter.scala:87:24]
assign out_roready_1_284 = _out_rofireMux_T_1194; // @[RegisterRouter.scala:87:24]
assign out_roready_1_285 = _out_rofireMux_T_1194; // @[RegisterRouter.scala:87:24]
assign out_roready_1_286 = _out_rofireMux_T_1194; // @[RegisterRouter.scala:87:24]
assign out_roready_1_287 = _out_rofireMux_T_1194; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1195 = ~_out_T_1671; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1197 = _out_rofireMux_T_260 & out_backSel_234; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_1198 = _out_rofireMux_T_1197 & _out_T_1605; // @[RegisterRouter.scala:87:24]
assign out_roready_1_16 = _out_rofireMux_T_1198; // @[RegisterRouter.scala:87:24]
assign out_roready_1_17 = _out_rofireMux_T_1198; // @[RegisterRouter.scala:87:24]
assign out_roready_1_18 = _out_rofireMux_T_1198; // @[RegisterRouter.scala:87:24]
assign out_roready_1_19 = _out_rofireMux_T_1198; // @[RegisterRouter.scala:87:24]
assign out_roready_1_20 = _out_rofireMux_T_1198; // @[RegisterRouter.scala:87:24]
assign out_roready_1_21 = _out_rofireMux_T_1198; // @[RegisterRouter.scala:87:24]
assign out_roready_1_22 = _out_rofireMux_T_1198; // @[RegisterRouter.scala:87:24]
assign out_roready_1_23 = _out_rofireMux_T_1198; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1199 = ~_out_T_1605; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1201 = _out_rofireMux_T_260 & out_backSel_235; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_1202 = _out_rofireMux_T_1201 & _out_T_1863; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1019 = _out_rofireMux_T_1202; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1020 = _out_rofireMux_T_1202; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1021 = _out_rofireMux_T_1202; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1022 = _out_rofireMux_T_1202; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1023 = _out_rofireMux_T_1202; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1024 = _out_rofireMux_T_1202; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1025 = _out_rofireMux_T_1202; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1026 = _out_rofireMux_T_1202; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1203 = ~_out_T_1863; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1205 = _out_rofireMux_T_260 & out_backSel_236; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_1206 = _out_rofireMux_T_1205 & _out_T_1761; // @[RegisterRouter.scala:87:24]
assign out_roready_1_617 = _out_rofireMux_T_1206; // @[RegisterRouter.scala:87:24]
assign out_roready_1_618 = _out_rofireMux_T_1206; // @[RegisterRouter.scala:87:24]
assign out_roready_1_619 = _out_rofireMux_T_1206; // @[RegisterRouter.scala:87:24]
assign out_roready_1_620 = _out_rofireMux_T_1206; // @[RegisterRouter.scala:87:24]
assign out_roready_1_621 = _out_rofireMux_T_1206; // @[RegisterRouter.scala:87:24]
assign out_roready_1_622 = _out_rofireMux_T_1206; // @[RegisterRouter.scala:87:24]
assign out_roready_1_623 = _out_rofireMux_T_1206; // @[RegisterRouter.scala:87:24]
assign out_roready_1_624 = _out_rofireMux_T_1206; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1207 = ~_out_T_1761; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1209 = _out_rofireMux_T_260 & out_backSel_237; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_1210 = _out_rofireMux_T_1209 & _out_T_1731; // @[RegisterRouter.scala:87:24]
assign out_roready_1_503 = _out_rofireMux_T_1210; // @[RegisterRouter.scala:87:24]
assign out_roready_1_504 = _out_rofireMux_T_1210; // @[RegisterRouter.scala:87:24]
assign out_roready_1_505 = _out_rofireMux_T_1210; // @[RegisterRouter.scala:87:24]
assign out_roready_1_506 = _out_rofireMux_T_1210; // @[RegisterRouter.scala:87:24]
assign out_roready_1_507 = _out_rofireMux_T_1210; // @[RegisterRouter.scala:87:24]
assign out_roready_1_508 = _out_rofireMux_T_1210; // @[RegisterRouter.scala:87:24]
assign out_roready_1_509 = _out_rofireMux_T_1210; // @[RegisterRouter.scala:87:24]
assign out_roready_1_510 = _out_rofireMux_T_1210; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1211 = ~_out_T_1731; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1213 = _out_rofireMux_T_260 & out_backSel_238; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_1214 = _out_rofireMux_T_1213 & _out_T_1651; // @[RegisterRouter.scala:87:24]
assign out_roready_1_200 = _out_rofireMux_T_1214; // @[RegisterRouter.scala:87:24]
assign out_roready_1_201 = _out_rofireMux_T_1214; // @[RegisterRouter.scala:87:24]
assign out_roready_1_202 = _out_rofireMux_T_1214; // @[RegisterRouter.scala:87:24]
assign out_roready_1_203 = _out_rofireMux_T_1214; // @[RegisterRouter.scala:87:24]
assign out_roready_1_204 = _out_rofireMux_T_1214; // @[RegisterRouter.scala:87:24]
assign out_roready_1_205 = _out_rofireMux_T_1214; // @[RegisterRouter.scala:87:24]
assign out_roready_1_206 = _out_rofireMux_T_1214; // @[RegisterRouter.scala:87:24]
assign out_roready_1_207 = _out_rofireMux_T_1214; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1215 = ~_out_T_1651; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1217 = _out_rofireMux_T_260 & out_backSel_239; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_1218 = _out_rofireMux_T_1217 & _out_T_1887; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1115 = _out_rofireMux_T_1218; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1116 = _out_rofireMux_T_1218; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1117 = _out_rofireMux_T_1218; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1118 = _out_rofireMux_T_1218; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1119 = _out_rofireMux_T_1218; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1120 = _out_rofireMux_T_1218; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1121 = _out_rofireMux_T_1218; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1122 = _out_rofireMux_T_1218; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1219 = ~_out_T_1887; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1221 = _out_rofireMux_T_260 & out_backSel_240; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_1222 = _out_rofireMux_T_1221 & _out_T_1793; // @[RegisterRouter.scala:87:24]
assign out_roready_1_739 = _out_rofireMux_T_1222; // @[RegisterRouter.scala:87:24]
assign out_roready_1_740 = _out_rofireMux_T_1222; // @[RegisterRouter.scala:87:24]
assign out_roready_1_741 = _out_rofireMux_T_1222; // @[RegisterRouter.scala:87:24]
assign out_roready_1_742 = _out_rofireMux_T_1222; // @[RegisterRouter.scala:87:24]
assign out_roready_1_743 = _out_rofireMux_T_1222; // @[RegisterRouter.scala:87:24]
assign out_roready_1_744 = _out_rofireMux_T_1222; // @[RegisterRouter.scala:87:24]
assign out_roready_1_745 = _out_rofireMux_T_1222; // @[RegisterRouter.scala:87:24]
assign out_roready_1_746 = _out_rofireMux_T_1222; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1223 = ~_out_T_1793; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1225 = _out_rofireMux_T_260 & out_backSel_241; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_1226 = _out_rofireMux_T_1225 & _out_T_1805; // @[RegisterRouter.scala:87:24]
assign out_roready_1_787 = _out_rofireMux_T_1226; // @[RegisterRouter.scala:87:24]
assign out_roready_1_788 = _out_rofireMux_T_1226; // @[RegisterRouter.scala:87:24]
assign out_roready_1_789 = _out_rofireMux_T_1226; // @[RegisterRouter.scala:87:24]
assign out_roready_1_790 = _out_rofireMux_T_1226; // @[RegisterRouter.scala:87:24]
assign out_roready_1_791 = _out_rofireMux_T_1226; // @[RegisterRouter.scala:87:24]
assign out_roready_1_792 = _out_rofireMux_T_1226; // @[RegisterRouter.scala:87:24]
assign out_roready_1_793 = _out_rofireMux_T_1226; // @[RegisterRouter.scala:87:24]
assign out_roready_1_794 = _out_rofireMux_T_1226; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1227 = ~_out_T_1805; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1229 = _out_rofireMux_T_260 & out_backSel_242; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_1230 = _out_rofireMux_T_1229 & _out_T_1889; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1123 = _out_rofireMux_T_1230; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1124 = _out_rofireMux_T_1230; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1125 = _out_rofireMux_T_1230; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1126 = _out_rofireMux_T_1230; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1127 = _out_rofireMux_T_1230; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1128 = _out_rofireMux_T_1230; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1129 = _out_rofireMux_T_1230; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1130 = _out_rofireMux_T_1230; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1231 = ~_out_T_1889; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1233 = _out_rofireMux_T_260 & out_backSel_243; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_1234 = _out_rofireMux_T_1233 & _out_T_1665; // @[RegisterRouter.scala:87:24]
assign out_roready_1_256 = _out_rofireMux_T_1234; // @[RegisterRouter.scala:87:24]
assign out_roready_1_257 = _out_rofireMux_T_1234; // @[RegisterRouter.scala:87:24]
assign out_roready_1_258 = _out_rofireMux_T_1234; // @[RegisterRouter.scala:87:24]
assign out_roready_1_259 = _out_rofireMux_T_1234; // @[RegisterRouter.scala:87:24]
assign out_roready_1_260 = _out_rofireMux_T_1234; // @[RegisterRouter.scala:87:24]
assign out_roready_1_261 = _out_rofireMux_T_1234; // @[RegisterRouter.scala:87:24]
assign out_roready_1_262 = _out_rofireMux_T_1234; // @[RegisterRouter.scala:87:24]
assign out_roready_1_263 = _out_rofireMux_T_1234; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1235 = ~_out_T_1665; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1237 = _out_rofireMux_T_260 & out_backSel_244; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_1238 = _out_rofireMux_T_1237 & _out_T_1735; // @[RegisterRouter.scala:87:24]
assign out_roready_1_519 = _out_rofireMux_T_1238; // @[RegisterRouter.scala:87:24]
assign out_roready_1_520 = _out_rofireMux_T_1238; // @[RegisterRouter.scala:87:24]
assign out_roready_1_521 = _out_rofireMux_T_1238; // @[RegisterRouter.scala:87:24]
assign out_roready_1_522 = _out_rofireMux_T_1238; // @[RegisterRouter.scala:87:24]
assign out_roready_1_523 = _out_rofireMux_T_1238; // @[RegisterRouter.scala:87:24]
assign out_roready_1_524 = _out_rofireMux_T_1238; // @[RegisterRouter.scala:87:24]
assign out_roready_1_525 = _out_rofireMux_T_1238; // @[RegisterRouter.scala:87:24]
assign out_roready_1_526 = _out_rofireMux_T_1238; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1239 = ~_out_T_1735; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1241 = _out_rofireMux_T_260 & out_backSel_245; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_1242 = _out_rofireMux_T_1241 & _out_T_1777; // @[RegisterRouter.scala:87:24]
assign out_roready_1_681 = _out_rofireMux_T_1242; // @[RegisterRouter.scala:87:24]
assign out_roready_1_682 = _out_rofireMux_T_1242; // @[RegisterRouter.scala:87:24]
assign out_roready_1_683 = _out_rofireMux_T_1242; // @[RegisterRouter.scala:87:24]
assign out_roready_1_684 = _out_rofireMux_T_1242; // @[RegisterRouter.scala:87:24]
assign out_roready_1_685 = _out_rofireMux_T_1242; // @[RegisterRouter.scala:87:24]
assign out_roready_1_686 = _out_rofireMux_T_1242; // @[RegisterRouter.scala:87:24]
assign out_roready_1_687 = _out_rofireMux_T_1242; // @[RegisterRouter.scala:87:24]
assign out_roready_1_688 = _out_rofireMux_T_1242; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1243 = ~_out_T_1777; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1245 = _out_rofireMux_T_260 & out_backSel_246; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_1246 = _out_rofireMux_T_1245 & _out_T_1865; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1027 = _out_rofireMux_T_1246; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1028 = _out_rofireMux_T_1246; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1029 = _out_rofireMux_T_1246; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1030 = _out_rofireMux_T_1246; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1031 = _out_rofireMux_T_1246; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1032 = _out_rofireMux_T_1246; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1033 = _out_rofireMux_T_1246; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1034 = _out_rofireMux_T_1246; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1247 = ~_out_T_1865; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1249 = _out_rofireMux_T_260 & out_backSel_247; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_1250 = _out_rofireMux_T_1249 & _out_T_1613; // @[RegisterRouter.scala:87:24]
assign out_roready_1_48 = _out_rofireMux_T_1250; // @[RegisterRouter.scala:87:24]
assign out_roready_1_49 = _out_rofireMux_T_1250; // @[RegisterRouter.scala:87:24]
assign out_roready_1_50 = _out_rofireMux_T_1250; // @[RegisterRouter.scala:87:24]
assign out_roready_1_51 = _out_rofireMux_T_1250; // @[RegisterRouter.scala:87:24]
assign out_roready_1_52 = _out_rofireMux_T_1250; // @[RegisterRouter.scala:87:24]
assign out_roready_1_53 = _out_rofireMux_T_1250; // @[RegisterRouter.scala:87:24]
assign out_roready_1_54 = _out_rofireMux_T_1250; // @[RegisterRouter.scala:87:24]
assign out_roready_1_55 = _out_rofireMux_T_1250; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1251 = ~_out_T_1613; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1253 = _out_rofireMux_T_260 & out_backSel_248; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_1254 = _out_rofireMux_T_1253 & _out_T_1673; // @[RegisterRouter.scala:87:24]
assign out_roready_1_288 = _out_rofireMux_T_1254; // @[RegisterRouter.scala:87:24]
assign out_roready_1_289 = _out_rofireMux_T_1254; // @[RegisterRouter.scala:87:24]
assign out_roready_1_290 = _out_rofireMux_T_1254; // @[RegisterRouter.scala:87:24]
assign out_roready_1_291 = _out_rofireMux_T_1254; // @[RegisterRouter.scala:87:24]
assign out_roready_1_292 = _out_rofireMux_T_1254; // @[RegisterRouter.scala:87:24]
assign out_roready_1_293 = _out_rofireMux_T_1254; // @[RegisterRouter.scala:87:24]
assign out_roready_1_294 = _out_rofireMux_T_1254; // @[RegisterRouter.scala:87:24]
assign out_roready_1_295 = _out_rofireMux_T_1254; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1255 = ~_out_T_1673; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1257 = _out_rofireMux_T_260 & out_backSel_249; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_1258 = _out_rofireMux_T_1257 & _out_T_1603; // @[RegisterRouter.scala:87:24]
assign out_roready_1_8 = _out_rofireMux_T_1258; // @[RegisterRouter.scala:87:24]
assign out_roready_1_9 = _out_rofireMux_T_1258; // @[RegisterRouter.scala:87:24]
assign out_roready_1_10 = _out_rofireMux_T_1258; // @[RegisterRouter.scala:87:24]
assign out_roready_1_11 = _out_rofireMux_T_1258; // @[RegisterRouter.scala:87:24]
assign out_roready_1_12 = _out_rofireMux_T_1258; // @[RegisterRouter.scala:87:24]
assign out_roready_1_13 = _out_rofireMux_T_1258; // @[RegisterRouter.scala:87:24]
assign out_roready_1_14 = _out_rofireMux_T_1258; // @[RegisterRouter.scala:87:24]
assign out_roready_1_15 = _out_rofireMux_T_1258; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1259 = ~_out_T_1603; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1261 = _out_rofireMux_T_260 & out_backSel_250; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_1262 = _out_rofireMux_T_1261 & _out_T_1843; // @[RegisterRouter.scala:87:24]
assign out_roready_1_939 = _out_rofireMux_T_1262; // @[RegisterRouter.scala:87:24]
assign out_roready_1_940 = _out_rofireMux_T_1262; // @[RegisterRouter.scala:87:24]
assign out_roready_1_941 = _out_rofireMux_T_1262; // @[RegisterRouter.scala:87:24]
assign out_roready_1_942 = _out_rofireMux_T_1262; // @[RegisterRouter.scala:87:24]
assign out_roready_1_943 = _out_rofireMux_T_1262; // @[RegisterRouter.scala:87:24]
assign out_roready_1_944 = _out_rofireMux_T_1262; // @[RegisterRouter.scala:87:24]
assign out_roready_1_945 = _out_rofireMux_T_1262; // @[RegisterRouter.scala:87:24]
assign out_roready_1_946 = _out_rofireMux_T_1262; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1263 = ~_out_T_1843; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1265 = _out_rofireMux_T_260 & out_backSel_251; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_1266 = _out_rofireMux_T_1265 & _out_T_1795; // @[RegisterRouter.scala:87:24]
assign out_roready_1_747 = _out_rofireMux_T_1266; // @[RegisterRouter.scala:87:24]
assign out_roready_1_748 = _out_rofireMux_T_1266; // @[RegisterRouter.scala:87:24]
assign out_roready_1_749 = _out_rofireMux_T_1266; // @[RegisterRouter.scala:87:24]
assign out_roready_1_750 = _out_rofireMux_T_1266; // @[RegisterRouter.scala:87:24]
assign out_roready_1_751 = _out_rofireMux_T_1266; // @[RegisterRouter.scala:87:24]
assign out_roready_1_752 = _out_rofireMux_T_1266; // @[RegisterRouter.scala:87:24]
assign out_roready_1_753 = _out_rofireMux_T_1266; // @[RegisterRouter.scala:87:24]
assign out_roready_1_754 = _out_rofireMux_T_1266; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1267 = ~_out_T_1795; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1269 = _out_rofireMux_T_260 & out_backSel_252; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_1270 = _out_rofireMux_T_1269 & _out_T_1693; // @[RegisterRouter.scala:87:24]
assign out_roready_1_362 = _out_rofireMux_T_1270; // @[RegisterRouter.scala:87:24]
assign out_roready_1_363 = _out_rofireMux_T_1270; // @[RegisterRouter.scala:87:24]
assign out_roready_1_364 = _out_rofireMux_T_1270; // @[RegisterRouter.scala:87:24]
assign out_roready_1_365 = _out_rofireMux_T_1270; // @[RegisterRouter.scala:87:24]
assign out_roready_1_366 = _out_rofireMux_T_1270; // @[RegisterRouter.scala:87:24]
assign out_roready_1_367 = _out_rofireMux_T_1270; // @[RegisterRouter.scala:87:24]
assign out_roready_1_368 = _out_rofireMux_T_1270; // @[RegisterRouter.scala:87:24]
assign out_roready_1_369 = _out_rofireMux_T_1270; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1271 = ~_out_T_1693; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1273 = _out_rofireMux_T_260 & out_backSel_253; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_1274 = _out_rofireMux_T_1273 & _out_T_1655; // @[RegisterRouter.scala:87:24]
assign out_roready_1_216 = _out_rofireMux_T_1274; // @[RegisterRouter.scala:87:24]
assign out_roready_1_217 = _out_rofireMux_T_1274; // @[RegisterRouter.scala:87:24]
assign out_roready_1_218 = _out_rofireMux_T_1274; // @[RegisterRouter.scala:87:24]
assign out_roready_1_219 = _out_rofireMux_T_1274; // @[RegisterRouter.scala:87:24]
assign out_roready_1_220 = _out_rofireMux_T_1274; // @[RegisterRouter.scala:87:24]
assign out_roready_1_221 = _out_rofireMux_T_1274; // @[RegisterRouter.scala:87:24]
assign out_roready_1_222 = _out_rofireMux_T_1274; // @[RegisterRouter.scala:87:24]
assign out_roready_1_223 = _out_rofireMux_T_1274; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1275 = ~_out_T_1655; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1277 = _out_rofireMux_T_260 & out_backSel_254; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_1278 = _out_rofireMux_T_1277 & _out_T_1907; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1195 = _out_rofireMux_T_1278; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1196 = _out_rofireMux_T_1278; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1197 = _out_rofireMux_T_1278; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1198 = _out_rofireMux_T_1278; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1199 = _out_rofireMux_T_1278; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1200 = _out_rofireMux_T_1278; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1201 = _out_rofireMux_T_1278; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1202 = _out_rofireMux_T_1278; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1279 = ~_out_T_1907; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1281 = _out_rofireMux_T_260 & out_backSel_255; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_1282 = _out_rofireMux_T_1281 & _out_T_1811; // @[RegisterRouter.scala:87:24]
assign out_roready_1_811 = _out_rofireMux_T_1282; // @[RegisterRouter.scala:87:24]
assign out_roready_1_812 = _out_rofireMux_T_1282; // @[RegisterRouter.scala:87:24]
assign out_roready_1_813 = _out_rofireMux_T_1282; // @[RegisterRouter.scala:87:24]
assign out_roready_1_814 = _out_rofireMux_T_1282; // @[RegisterRouter.scala:87:24]
assign out_roready_1_815 = _out_rofireMux_T_1282; // @[RegisterRouter.scala:87:24]
assign out_roready_1_816 = _out_rofireMux_T_1282; // @[RegisterRouter.scala:87:24]
assign out_roready_1_817 = _out_rofireMux_T_1282; // @[RegisterRouter.scala:87:24]
assign out_roready_1_818 = _out_rofireMux_T_1282; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1283 = ~_out_T_1811; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_261 = ~out_front_1_bits_read; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_262 = _out_wofireMux_T_260 & _out_wofireMux_T_261; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_263 = _out_wofireMux_T_262 & out_backSel_0_1; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_264 = _out_wofireMux_T_263 & _out_T_1717; // @[RegisterRouter.scala:87:24]
assign out_woready_1_451 = _out_wofireMux_T_264; // @[RegisterRouter.scala:87:24]
assign out_woready_1_452 = _out_wofireMux_T_264; // @[RegisterRouter.scala:87:24]
assign out_woready_1_453 = _out_wofireMux_T_264; // @[RegisterRouter.scala:87:24]
assign out_woready_1_454 = _out_wofireMux_T_264; // @[RegisterRouter.scala:87:24]
assign out_woready_1_455 = _out_wofireMux_T_264; // @[RegisterRouter.scala:87:24]
assign out_woready_1_456 = _out_wofireMux_T_264; // @[RegisterRouter.scala:87:24]
assign out_woready_1_457 = _out_wofireMux_T_264; // @[RegisterRouter.scala:87:24]
assign out_woready_1_458 = _out_wofireMux_T_264; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_265 = ~_out_T_1717; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_267 = _out_wofireMux_T_262 & out_backSel_1_1; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_268 = _out_wofireMux_T_267 & _out_T_1625; // @[RegisterRouter.scala:87:24]
assign out_woready_1_96 = _out_wofireMux_T_268; // @[RegisterRouter.scala:87:24]
assign out_woready_1_97 = _out_wofireMux_T_268; // @[RegisterRouter.scala:87:24]
assign out_woready_1_98 = _out_wofireMux_T_268; // @[RegisterRouter.scala:87:24]
assign out_woready_1_99 = _out_wofireMux_T_268; // @[RegisterRouter.scala:87:24]
assign out_woready_1_100 = _out_wofireMux_T_268; // @[RegisterRouter.scala:87:24]
assign out_woready_1_101 = _out_wofireMux_T_268; // @[RegisterRouter.scala:87:24]
assign out_woready_1_102 = _out_wofireMux_T_268; // @[RegisterRouter.scala:87:24]
assign out_woready_1_103 = _out_wofireMux_T_268; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_269 = ~_out_T_1625; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_271 = _out_wofireMux_T_262 & out_backSel_2_1; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_272 = _out_wofireMux_T_271 & _out_T_1847; // @[RegisterRouter.scala:87:24]
assign out_woready_1_955 = _out_wofireMux_T_272; // @[RegisterRouter.scala:87:24]
assign out_woready_1_956 = _out_wofireMux_T_272; // @[RegisterRouter.scala:87:24]
assign out_woready_1_957 = _out_wofireMux_T_272; // @[RegisterRouter.scala:87:24]
assign out_woready_1_958 = _out_wofireMux_T_272; // @[RegisterRouter.scala:87:24]
assign out_woready_1_959 = _out_wofireMux_T_272; // @[RegisterRouter.scala:87:24]
assign out_woready_1_960 = _out_wofireMux_T_272; // @[RegisterRouter.scala:87:24]
assign out_woready_1_961 = _out_wofireMux_T_272; // @[RegisterRouter.scala:87:24]
assign out_woready_1_962 = _out_wofireMux_T_272; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_273 = ~_out_T_1847; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_275 = _out_wofireMux_T_262 & out_backSel_3_1; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_276 = _out_wofireMux_T_275 & _out_T_1757; // @[RegisterRouter.scala:87:24]
assign out_woready_1_601 = _out_wofireMux_T_276; // @[RegisterRouter.scala:87:24]
assign out_woready_1_602 = _out_wofireMux_T_276; // @[RegisterRouter.scala:87:24]
assign out_woready_1_603 = _out_wofireMux_T_276; // @[RegisterRouter.scala:87:24]
assign out_woready_1_604 = _out_wofireMux_T_276; // @[RegisterRouter.scala:87:24]
assign out_woready_1_605 = _out_wofireMux_T_276; // @[RegisterRouter.scala:87:24]
assign out_woready_1_606 = _out_wofireMux_T_276; // @[RegisterRouter.scala:87:24]
assign out_woready_1_607 = _out_wofireMux_T_276; // @[RegisterRouter.scala:87:24]
assign out_woready_1_608 = _out_wofireMux_T_276; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_277 = ~_out_T_1757; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_279 = _out_wofireMux_T_262 & out_backSel_4_1; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_280 = _out_wofireMux_T_279 & _out_T_1679; // @[RegisterRouter.scala:87:24]
assign out_woready_1_312 = _out_wofireMux_T_280; // @[RegisterRouter.scala:87:24]
assign out_woready_1_313 = _out_wofireMux_T_280; // @[RegisterRouter.scala:87:24]
assign out_woready_1_314 = _out_wofireMux_T_280; // @[RegisterRouter.scala:87:24]
assign out_woready_1_315 = _out_wofireMux_T_280; // @[RegisterRouter.scala:87:24]
assign out_woready_1_316 = _out_wofireMux_T_280; // @[RegisterRouter.scala:87:24]
assign out_woready_1_317 = _out_wofireMux_T_280; // @[RegisterRouter.scala:87:24]
assign out_woready_1_318 = _out_wofireMux_T_280; // @[RegisterRouter.scala:87:24]
assign out_woready_1_319 = _out_wofireMux_T_280; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_281 = ~_out_T_1679; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_283 = _out_wofireMux_T_262 & out_backSel_5_1; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_284 = _out_wofireMux_T_283 & _out_T_1641; // @[RegisterRouter.scala:87:24]
assign out_woready_1_160 = _out_wofireMux_T_284; // @[RegisterRouter.scala:87:24]
assign out_woready_1_161 = _out_wofireMux_T_284; // @[RegisterRouter.scala:87:24]
assign out_woready_1_162 = _out_wofireMux_T_284; // @[RegisterRouter.scala:87:24]
assign out_woready_1_163 = _out_wofireMux_T_284; // @[RegisterRouter.scala:87:24]
assign out_woready_1_164 = _out_wofireMux_T_284; // @[RegisterRouter.scala:87:24]
assign out_woready_1_165 = _out_wofireMux_T_284; // @[RegisterRouter.scala:87:24]
assign out_woready_1_166 = _out_wofireMux_T_284; // @[RegisterRouter.scala:87:24]
assign out_woready_1_167 = _out_wofireMux_T_284; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_285 = ~_out_T_1641; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_287 = _out_wofireMux_T_262 & out_backSel_6_1; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_288 = _out_wofireMux_T_287 & _out_T_1877; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1075 = _out_wofireMux_T_288; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1076 = _out_wofireMux_T_288; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1077 = _out_wofireMux_T_288; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1078 = _out_wofireMux_T_288; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1079 = _out_wofireMux_T_288; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1080 = _out_wofireMux_T_288; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1081 = _out_wofireMux_T_288; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1082 = _out_wofireMux_T_288; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_289 = ~_out_T_1877; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_291 = _out_wofireMux_T_262 & out_backSel_7_1; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_292 = _out_wofireMux_T_291 & _out_T_1823; // @[RegisterRouter.scala:87:24]
assign out_woready_1_859 = _out_wofireMux_T_292; // @[RegisterRouter.scala:87:24]
assign out_woready_1_860 = _out_wofireMux_T_292; // @[RegisterRouter.scala:87:24]
assign out_woready_1_861 = _out_wofireMux_T_292; // @[RegisterRouter.scala:87:24]
assign out_woready_1_862 = _out_wofireMux_T_292; // @[RegisterRouter.scala:87:24]
assign out_woready_1_863 = _out_wofireMux_T_292; // @[RegisterRouter.scala:87:24]
assign out_woready_1_864 = _out_wofireMux_T_292; // @[RegisterRouter.scala:87:24]
assign out_woready_1_865 = _out_wofireMux_T_292; // @[RegisterRouter.scala:87:24]
assign out_woready_1_866 = _out_wofireMux_T_292; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_293 = ~_out_T_1823; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_295 = _out_wofireMux_T_262 & out_backSel_8_1; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_296 = _out_wofireMux_T_295 & _out_T_1743; // @[RegisterRouter.scala:87:24]
assign out_woready_1_545 = _out_wofireMux_T_296; // @[RegisterRouter.scala:87:24]
assign out_woready_1_546 = _out_wofireMux_T_296; // @[RegisterRouter.scala:87:24]
assign out_woready_1_547 = _out_wofireMux_T_296; // @[RegisterRouter.scala:87:24]
assign out_woready_1_548 = _out_wofireMux_T_296; // @[RegisterRouter.scala:87:24]
assign out_woready_1_549 = _out_wofireMux_T_296; // @[RegisterRouter.scala:87:24]
assign out_woready_1_550 = _out_wofireMux_T_296; // @[RegisterRouter.scala:87:24]
assign out_woready_1_551 = _out_wofireMux_T_296; // @[RegisterRouter.scala:87:24]
assign out_woready_1_552 = _out_wofireMux_T_296; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_297 = ~_out_T_1743; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_299 = _out_wofireMux_T_262 & out_backSel_9_1; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_300 = _out_wofireMux_T_299 & _out_T_1667; // @[RegisterRouter.scala:87:24]
assign out_woready_1_264 = _out_wofireMux_T_300; // @[RegisterRouter.scala:87:24]
assign out_woready_1_265 = _out_wofireMux_T_300; // @[RegisterRouter.scala:87:24]
assign out_woready_1_266 = _out_wofireMux_T_300; // @[RegisterRouter.scala:87:24]
assign out_woready_1_267 = _out_wofireMux_T_300; // @[RegisterRouter.scala:87:24]
assign out_woready_1_268 = _out_wofireMux_T_300; // @[RegisterRouter.scala:87:24]
assign out_woready_1_269 = _out_wofireMux_T_300; // @[RegisterRouter.scala:87:24]
assign out_woready_1_270 = _out_wofireMux_T_300; // @[RegisterRouter.scala:87:24]
assign out_woready_1_271 = _out_wofireMux_T_300; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_301 = ~_out_T_1667; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_303 = _out_wofireMux_T_262 & out_backSel_10_1; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_304 = _out_wofireMux_T_303 & _out_T_1725; // @[RegisterRouter.scala:87:24]
assign out_woready_1_483 = _out_wofireMux_T_304; // @[RegisterRouter.scala:87:24]
assign out_woready_1_484 = _out_wofireMux_T_304; // @[RegisterRouter.scala:87:24]
assign out_woready_1_485 = _out_wofireMux_T_304; // @[RegisterRouter.scala:87:24]
assign out_woready_1_486 = _out_wofireMux_T_304; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_305 = ~_out_T_1725; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_307 = _out_wofireMux_T_262 & out_backSel_11_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_308 = _out_wofireMux_T_307; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_311 = _out_wofireMux_T_262 & out_backSel_12_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_312 = _out_wofireMux_T_311; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_315 = _out_wofireMux_T_262 & out_backSel_13_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_316 = _out_wofireMux_T_315; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_319 = _out_wofireMux_T_262 & out_backSel_14_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_320 = _out_wofireMux_T_319; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_323 = _out_wofireMux_T_262 & out_backSel_15_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_324 = _out_wofireMux_T_323; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_327 = _out_wofireMux_T_262 & out_backSel_16_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_328 = _out_wofireMux_T_327; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_331 = _out_wofireMux_T_262 & out_backSel_17_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_332 = _out_wofireMux_T_331; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_335 = _out_wofireMux_T_262 & out_backSel_18_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_336 = _out_wofireMux_T_335; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_339 = _out_wofireMux_T_262 & out_backSel_19_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_340 = _out_wofireMux_T_339; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_343 = _out_wofireMux_T_262 & out_backSel_20_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_344 = _out_wofireMux_T_343; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_347 = _out_wofireMux_T_262 & out_backSel_21_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_348 = _out_wofireMux_T_347; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_351 = _out_wofireMux_T_262 & out_backSel_22_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_352 = _out_wofireMux_T_351; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_355 = _out_wofireMux_T_262 & out_backSel_23_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_356 = _out_wofireMux_T_355; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_359 = _out_wofireMux_T_262 & out_backSel_24_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_360 = _out_wofireMux_T_359; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_363 = _out_wofireMux_T_262 & out_backSel_25_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_364 = _out_wofireMux_T_363; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_367 = _out_wofireMux_T_262 & out_backSel_26_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_368 = _out_wofireMux_T_367; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_371 = _out_wofireMux_T_262 & out_backSel_27_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_372 = _out_wofireMux_T_371; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_375 = _out_wofireMux_T_262 & out_backSel_28_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_376 = _out_wofireMux_T_375; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_379 = _out_wofireMux_T_262 & out_backSel_29_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_380 = _out_wofireMux_T_379; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_383 = _out_wofireMux_T_262 & out_backSel_30_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_384 = _out_wofireMux_T_383; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_387 = _out_wofireMux_T_262 & out_backSel_31_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_388 = _out_wofireMux_T_387; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_391 = _out_wofireMux_T_262 & out_backSel_32_1; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_392 = _out_wofireMux_T_391 & _out_T_1739; // @[RegisterRouter.scala:87:24]
assign out_woready_1_535 = _out_wofireMux_T_392; // @[RegisterRouter.scala:87:24]
assign out_woready_1_536 = _out_wofireMux_T_392; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_393 = ~_out_T_1739; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_395 = _out_wofireMux_T_262 & out_backSel_33_1; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_396 = _out_wofireMux_T_395 & _out_T_1689; // @[RegisterRouter.scala:87:24]
assign out_woready_1_352 = _out_wofireMux_T_396; // @[RegisterRouter.scala:87:24]
assign out_woready_1_353 = _out_wofireMux_T_396; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_397 = ~_out_T_1689; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_399 = _out_wofireMux_T_262 & out_backSel_34_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_400 = _out_wofireMux_T_399; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_403 = _out_wofireMux_T_262 & out_backSel_35_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_404 = _out_wofireMux_T_403; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_407 = _out_wofireMux_T_262 & out_backSel_36_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_408 = _out_wofireMux_T_407; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_411 = _out_wofireMux_T_262 & out_backSel_37_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_412 = _out_wofireMux_T_411; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_415 = _out_wofireMux_T_262 & out_backSel_38_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_416 = _out_wofireMux_T_415; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_419 = _out_wofireMux_T_262 & out_backSel_39_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_420 = _out_wofireMux_T_419; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_423 = _out_wofireMux_T_262 & out_backSel_40_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_424 = _out_wofireMux_T_423; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_427 = _out_wofireMux_T_262 & out_backSel_41_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_428 = _out_wofireMux_T_427; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_431 = _out_wofireMux_T_262 & out_backSel_42_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_432 = _out_wofireMux_T_431; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_435 = _out_wofireMux_T_262 & out_backSel_43_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_436 = _out_wofireMux_T_435; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_439 = _out_wofireMux_T_262 & out_backSel_44_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_440 = _out_wofireMux_T_439; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_443 = _out_wofireMux_T_262 & out_backSel_45_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_444 = _out_wofireMux_T_443; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_447 = _out_wofireMux_T_262 & out_backSel_46_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_448 = _out_wofireMux_T_447; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_451 = _out_wofireMux_T_262 & out_backSel_47_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_452 = _out_wofireMux_T_451; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_455 = _out_wofireMux_T_262 & out_backSel_48_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_456 = _out_wofireMux_T_455; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_459 = _out_wofireMux_T_262 & out_backSel_49_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_460 = _out_wofireMux_T_459; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_463 = _out_wofireMux_T_262 & out_backSel_50_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_464 = _out_wofireMux_T_463; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_467 = _out_wofireMux_T_262 & out_backSel_51_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_468 = _out_wofireMux_T_467; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_471 = _out_wofireMux_T_262 & out_backSel_52_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_472 = _out_wofireMux_T_471; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_475 = _out_wofireMux_T_262 & out_backSel_53_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_476 = _out_wofireMux_T_475; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_479 = _out_wofireMux_T_262 & out_backSel_54_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_480 = _out_wofireMux_T_479; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_483 = _out_wofireMux_T_262 & out_backSel_55_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_484 = _out_wofireMux_T_483; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_487 = _out_wofireMux_T_262 & out_backSel_56_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_488 = _out_wofireMux_T_487; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_491 = _out_wofireMux_T_262 & out_backSel_57_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_492 = _out_wofireMux_T_491; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_495 = _out_wofireMux_T_262 & out_backSel_58_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_496 = _out_wofireMux_T_495; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_499 = _out_wofireMux_T_262 & out_backSel_59_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_500 = _out_wofireMux_T_499; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_503 = _out_wofireMux_T_262 & out_backSel_60_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_504 = _out_wofireMux_T_503; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_507 = _out_wofireMux_T_262 & out_backSel_61_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_508 = _out_wofireMux_T_507; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_511 = _out_wofireMux_T_262 & out_backSel_62_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_512 = _out_wofireMux_T_511; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_515 = _out_wofireMux_T_262 & out_backSel_63_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_516 = _out_wofireMux_T_515; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_519 = _out_wofireMux_T_262 & out_backSel_64; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_520 = _out_wofireMux_T_519; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_523 = _out_wofireMux_T_262 & out_backSel_65; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_524 = _out_wofireMux_T_523; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_527 = _out_wofireMux_T_262 & out_backSel_66; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_528 = _out_wofireMux_T_527; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_531 = _out_wofireMux_T_262 & out_backSel_67; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_532 = _out_wofireMux_T_531; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_535 = _out_wofireMux_T_262 & out_backSel_68; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_536 = _out_wofireMux_T_535; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_539 = _out_wofireMux_T_262 & out_backSel_69; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_540 = _out_wofireMux_T_539; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_543 = _out_wofireMux_T_262 & out_backSel_70; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_544 = _out_wofireMux_T_543; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_547 = _out_wofireMux_T_262 & out_backSel_71; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_548 = _out_wofireMux_T_547; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_551 = _out_wofireMux_T_262 & out_backSel_72; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_552 = _out_wofireMux_T_551; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_555 = _out_wofireMux_T_262 & out_backSel_73; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_556 = _out_wofireMux_T_555; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_559 = _out_wofireMux_T_262 & out_backSel_74; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_560 = _out_wofireMux_T_559; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_563 = _out_wofireMux_T_262 & out_backSel_75; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_564 = _out_wofireMux_T_563; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_567 = _out_wofireMux_T_262 & out_backSel_76; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_568 = _out_wofireMux_T_567; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_571 = _out_wofireMux_T_262 & out_backSel_77; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_572 = _out_wofireMux_T_571; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_575 = _out_wofireMux_T_262 & out_backSel_78; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_576 = _out_wofireMux_T_575; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_579 = _out_wofireMux_T_262 & out_backSel_79; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_580 = _out_wofireMux_T_579; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_583 = _out_wofireMux_T_262 & out_backSel_80; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_584 = _out_wofireMux_T_583; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_587 = _out_wofireMux_T_262 & out_backSel_81; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_588 = _out_wofireMux_T_587; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_591 = _out_wofireMux_T_262 & out_backSel_82; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_592 = _out_wofireMux_T_591; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_595 = _out_wofireMux_T_262 & out_backSel_83; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_596 = _out_wofireMux_T_595; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_599 = _out_wofireMux_T_262 & out_backSel_84; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_600 = _out_wofireMux_T_599; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_603 = _out_wofireMux_T_262 & out_backSel_85; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_604 = _out_wofireMux_T_603; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_607 = _out_wofireMux_T_262 & out_backSel_86; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_608 = _out_wofireMux_T_607; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_611 = _out_wofireMux_T_262 & out_backSel_87; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_612 = _out_wofireMux_T_611; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_615 = _out_wofireMux_T_262 & out_backSel_88; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_616 = _out_wofireMux_T_615; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_619 = _out_wofireMux_T_262 & out_backSel_89; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_620 = _out_wofireMux_T_619; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_623 = _out_wofireMux_T_262 & out_backSel_90; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_624 = _out_wofireMux_T_623; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_627 = _out_wofireMux_T_262 & out_backSel_91; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_628 = _out_wofireMux_T_627; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_631 = _out_wofireMux_T_262 & out_backSel_92; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_632 = _out_wofireMux_T_631; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_635 = _out_wofireMux_T_262 & out_backSel_93; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_636 = _out_wofireMux_T_635; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_639 = _out_wofireMux_T_262 & out_backSel_94; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_640 = _out_wofireMux_T_639; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_643 = _out_wofireMux_T_262 & out_backSel_95; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_644 = _out_wofireMux_T_643; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_647 = _out_wofireMux_T_262 & out_backSel_96; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_648 = _out_wofireMux_T_647 & _out_T_1713; // @[RegisterRouter.scala:87:24]
assign out_woready_1_442 = _out_wofireMux_T_648; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_649 = ~_out_T_1713; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_651 = _out_wofireMux_T_262 & out_backSel_97; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_652 = _out_wofireMux_T_651; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_655 = _out_wofireMux_T_262 & out_backSel_98; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_656 = _out_wofireMux_T_655; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_659 = _out_wofireMux_T_262 & out_backSel_99; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_660 = _out_wofireMux_T_659; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_663 = _out_wofireMux_T_262 & out_backSel_100; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_664 = _out_wofireMux_T_663; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_667 = _out_wofireMux_T_262 & out_backSel_101; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_668 = _out_wofireMux_T_667; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_671 = _out_wofireMux_T_262 & out_backSel_102; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_672 = _out_wofireMux_T_671; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_675 = _out_wofireMux_T_262 & out_backSel_103; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_676 = _out_wofireMux_T_675 & _out_T_1781; // @[RegisterRouter.scala:87:24]
assign out_woready_1_697 = _out_wofireMux_T_676; // @[RegisterRouter.scala:87:24]
assign out_woready_1_698 = _out_wofireMux_T_676; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_677 = ~_out_T_1781; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_679 = _out_wofireMux_T_262 & out_backSel_104; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_680 = _out_wofireMux_T_679 & _out_T_1841; // @[RegisterRouter.scala:87:24]
assign out_woready_1_931 = _out_wofireMux_T_680; // @[RegisterRouter.scala:87:24]
assign out_woready_1_932 = _out_wofireMux_T_680; // @[RegisterRouter.scala:87:24]
assign out_woready_1_933 = _out_wofireMux_T_680; // @[RegisterRouter.scala:87:24]
assign out_woready_1_934 = _out_wofireMux_T_680; // @[RegisterRouter.scala:87:24]
assign out_woready_1_935 = _out_wofireMux_T_680; // @[RegisterRouter.scala:87:24]
assign out_woready_1_936 = _out_wofireMux_T_680; // @[RegisterRouter.scala:87:24]
assign out_woready_1_937 = _out_wofireMux_T_680; // @[RegisterRouter.scala:87:24]
assign out_woready_1_938 = _out_wofireMux_T_680; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_681 = ~_out_T_1841; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_683 = _out_wofireMux_T_262 & out_backSel_105; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_684 = _out_wofireMux_T_683 & _out_T_1733; // @[RegisterRouter.scala:87:24]
assign out_woready_1_511 = _out_wofireMux_T_684; // @[RegisterRouter.scala:87:24]
assign out_woready_1_512 = _out_wofireMux_T_684; // @[RegisterRouter.scala:87:24]
assign out_woready_1_513 = _out_wofireMux_T_684; // @[RegisterRouter.scala:87:24]
assign out_woready_1_514 = _out_wofireMux_T_684; // @[RegisterRouter.scala:87:24]
assign out_woready_1_515 = _out_wofireMux_T_684; // @[RegisterRouter.scala:87:24]
assign out_woready_1_516 = _out_wofireMux_T_684; // @[RegisterRouter.scala:87:24]
assign out_woready_1_517 = _out_wofireMux_T_684; // @[RegisterRouter.scala:87:24]
assign out_woready_1_518 = _out_wofireMux_T_684; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_685 = ~_out_T_1733; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_687 = _out_wofireMux_T_262 & out_backSel_106; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_688 = _out_wofireMux_T_687 & _out_T_1649; // @[RegisterRouter.scala:87:24]
assign out_woready_1_192 = _out_wofireMux_T_688; // @[RegisterRouter.scala:87:24]
assign out_woready_1_193 = _out_wofireMux_T_688; // @[RegisterRouter.scala:87:24]
assign out_woready_1_194 = _out_wofireMux_T_688; // @[RegisterRouter.scala:87:24]
assign out_woready_1_195 = _out_wofireMux_T_688; // @[RegisterRouter.scala:87:24]
assign out_woready_1_196 = _out_wofireMux_T_688; // @[RegisterRouter.scala:87:24]
assign out_woready_1_197 = _out_wofireMux_T_688; // @[RegisterRouter.scala:87:24]
assign out_woready_1_198 = _out_wofireMux_T_688; // @[RegisterRouter.scala:87:24]
assign out_woready_1_199 = _out_wofireMux_T_688; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_689 = ~_out_T_1649; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_691 = _out_wofireMux_T_262 & out_backSel_107; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_692 = _out_wofireMux_T_691 & _out_T_1881; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1091 = _out_wofireMux_T_692; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1092 = _out_wofireMux_T_692; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1093 = _out_wofireMux_T_692; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1094 = _out_wofireMux_T_692; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1095 = _out_wofireMux_T_692; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1096 = _out_wofireMux_T_692; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1097 = _out_wofireMux_T_692; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1098 = _out_wofireMux_T_692; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_693 = ~_out_T_1881; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_695 = _out_wofireMux_T_262 & out_backSel_108; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_696 = _out_wofireMux_T_695 & _out_T_1791; // @[RegisterRouter.scala:87:24]
assign out_woready_1_731 = _out_wofireMux_T_696; // @[RegisterRouter.scala:87:24]
assign out_woready_1_732 = _out_wofireMux_T_696; // @[RegisterRouter.scala:87:24]
assign out_woready_1_733 = _out_wofireMux_T_696; // @[RegisterRouter.scala:87:24]
assign out_woready_1_734 = _out_wofireMux_T_696; // @[RegisterRouter.scala:87:24]
assign out_woready_1_735 = _out_wofireMux_T_696; // @[RegisterRouter.scala:87:24]
assign out_woready_1_736 = _out_wofireMux_T_696; // @[RegisterRouter.scala:87:24]
assign out_woready_1_737 = _out_wofireMux_T_696; // @[RegisterRouter.scala:87:24]
assign out_woready_1_738 = _out_wofireMux_T_696; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_697 = ~_out_T_1791; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_699 = _out_wofireMux_T_262 & out_backSel_109; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_700 = _out_wofireMux_T_699 & _out_T_1715; // @[RegisterRouter.scala:87:24]
assign out_woready_1_443 = _out_wofireMux_T_700; // @[RegisterRouter.scala:87:24]
assign out_woready_1_444 = _out_wofireMux_T_700; // @[RegisterRouter.scala:87:24]
assign out_woready_1_445 = _out_wofireMux_T_700; // @[RegisterRouter.scala:87:24]
assign out_woready_1_446 = _out_wofireMux_T_700; // @[RegisterRouter.scala:87:24]
assign out_woready_1_447 = _out_wofireMux_T_700; // @[RegisterRouter.scala:87:24]
assign out_woready_1_448 = _out_wofireMux_T_700; // @[RegisterRouter.scala:87:24]
assign out_woready_1_449 = _out_wofireMux_T_700; // @[RegisterRouter.scala:87:24]
assign out_woready_1_450 = _out_wofireMux_T_700; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_701 = ~_out_T_1715; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_703 = _out_wofireMux_T_262 & out_backSel_110; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_704 = _out_wofireMux_T_703 & _out_T_1629; // @[RegisterRouter.scala:87:24]
assign out_woready_1_112 = _out_wofireMux_T_704; // @[RegisterRouter.scala:87:24]
assign out_woready_1_113 = _out_wofireMux_T_704; // @[RegisterRouter.scala:87:24]
assign out_woready_1_114 = _out_wofireMux_T_704; // @[RegisterRouter.scala:87:24]
assign out_woready_1_115 = _out_wofireMux_T_704; // @[RegisterRouter.scala:87:24]
assign out_woready_1_116 = _out_wofireMux_T_704; // @[RegisterRouter.scala:87:24]
assign out_woready_1_117 = _out_wofireMux_T_704; // @[RegisterRouter.scala:87:24]
assign out_woready_1_118 = _out_wofireMux_T_704; // @[RegisterRouter.scala:87:24]
assign out_woready_1_119 = _out_wofireMux_T_704; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_705 = ~_out_T_1629; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_707 = _out_wofireMux_T_262 & out_backSel_111; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_708 = _out_wofireMux_T_707 & _out_T_1899; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1163 = _out_wofireMux_T_708; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1164 = _out_wofireMux_T_708; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1165 = _out_wofireMux_T_708; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1166 = _out_wofireMux_T_708; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1167 = _out_wofireMux_T_708; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1168 = _out_wofireMux_T_708; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1169 = _out_wofireMux_T_708; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1170 = _out_wofireMux_T_708; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_709 = ~_out_T_1899; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_711 = _out_wofireMux_T_262 & out_backSel_112; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_712 = _out_wofireMux_T_711 & _out_T_1815; // @[RegisterRouter.scala:87:24]
assign out_woready_1_827 = _out_wofireMux_T_712; // @[RegisterRouter.scala:87:24]
assign out_woready_1_828 = _out_wofireMux_T_712; // @[RegisterRouter.scala:87:24]
assign out_woready_1_829 = _out_wofireMux_T_712; // @[RegisterRouter.scala:87:24]
assign out_woready_1_830 = _out_wofireMux_T_712; // @[RegisterRouter.scala:87:24]
assign out_woready_1_831 = _out_wofireMux_T_712; // @[RegisterRouter.scala:87:24]
assign out_woready_1_832 = _out_wofireMux_T_712; // @[RegisterRouter.scala:87:24]
assign out_woready_1_833 = _out_wofireMux_T_712; // @[RegisterRouter.scala:87:24]
assign out_woready_1_834 = _out_wofireMux_T_712; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_713 = ~_out_T_1815; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_715 = _out_wofireMux_T_262 & out_backSel_113; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_716 = _out_wofireMux_T_715 & _out_T_1771; // @[RegisterRouter.scala:87:24]
assign out_woready_1_657 = _out_wofireMux_T_716; // @[RegisterRouter.scala:87:24]
assign out_woready_1_658 = _out_wofireMux_T_716; // @[RegisterRouter.scala:87:24]
assign out_woready_1_659 = _out_wofireMux_T_716; // @[RegisterRouter.scala:87:24]
assign out_woready_1_660 = _out_wofireMux_T_716; // @[RegisterRouter.scala:87:24]
assign out_woready_1_661 = _out_wofireMux_T_716; // @[RegisterRouter.scala:87:24]
assign out_woready_1_662 = _out_wofireMux_T_716; // @[RegisterRouter.scala:87:24]
assign out_woready_1_663 = _out_wofireMux_T_716; // @[RegisterRouter.scala:87:24]
assign out_woready_1_664 = _out_wofireMux_T_716; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_717 = ~_out_T_1771; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_719 = _out_wofireMux_T_262 & out_backSel_114; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_720 = _out_wofireMux_T_719 & _out_T_1853; // @[RegisterRouter.scala:87:24]
assign out_woready_1_979 = _out_wofireMux_T_720; // @[RegisterRouter.scala:87:24]
assign out_woready_1_980 = _out_wofireMux_T_720; // @[RegisterRouter.scala:87:24]
assign out_woready_1_981 = _out_wofireMux_T_720; // @[RegisterRouter.scala:87:24]
assign out_woready_1_982 = _out_wofireMux_T_720; // @[RegisterRouter.scala:87:24]
assign out_woready_1_983 = _out_wofireMux_T_720; // @[RegisterRouter.scala:87:24]
assign out_woready_1_984 = _out_wofireMux_T_720; // @[RegisterRouter.scala:87:24]
assign out_woready_1_985 = _out_wofireMux_T_720; // @[RegisterRouter.scala:87:24]
assign out_woready_1_986 = _out_wofireMux_T_720; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_721 = ~_out_T_1853; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_723 = _out_wofireMux_T_262 & out_backSel_115; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_724 = _out_wofireMux_T_723 & _out_T_1609; // @[RegisterRouter.scala:87:24]
assign out_woready_1_32 = _out_wofireMux_T_724; // @[RegisterRouter.scala:87:24]
assign out_woready_1_33 = _out_wofireMux_T_724; // @[RegisterRouter.scala:87:24]
assign out_woready_1_34 = _out_wofireMux_T_724; // @[RegisterRouter.scala:87:24]
assign out_woready_1_35 = _out_wofireMux_T_724; // @[RegisterRouter.scala:87:24]
assign out_woready_1_36 = _out_wofireMux_T_724; // @[RegisterRouter.scala:87:24]
assign out_woready_1_37 = _out_wofireMux_T_724; // @[RegisterRouter.scala:87:24]
assign out_woready_1_38 = _out_wofireMux_T_724; // @[RegisterRouter.scala:87:24]
assign out_woready_1_39 = _out_wofireMux_T_724; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_725 = ~_out_T_1609; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_727 = _out_wofireMux_T_262 & out_backSel_116; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_728 = _out_wofireMux_T_727; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_731 = _out_wofireMux_T_262 & out_backSel_117; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_732 = _out_wofireMux_T_731; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_735 = _out_wofireMux_T_262 & out_backSel_118; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_736 = _out_wofireMux_T_735; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_739 = _out_wofireMux_T_262 & out_backSel_119; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_740 = _out_wofireMux_T_739; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_743 = _out_wofireMux_T_262 & out_backSel_120; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_744 = _out_wofireMux_T_743; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_747 = _out_wofireMux_T_262 & out_backSel_121; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_748 = _out_wofireMux_T_747; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_751 = _out_wofireMux_T_262 & out_backSel_122; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_752 = _out_wofireMux_T_751; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_755 = _out_wofireMux_T_262 & out_backSel_123; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_756 = _out_wofireMux_T_755; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_759 = _out_wofireMux_T_262 & out_backSel_124; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_760 = _out_wofireMux_T_759; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_763 = _out_wofireMux_T_262 & out_backSel_125; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_764 = _out_wofireMux_T_763; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_767 = _out_wofireMux_T_262 & out_backSel_126; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_768 = _out_wofireMux_T_767; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_771 = _out_wofireMux_T_262 & out_backSel_127; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_772 = _out_wofireMux_T_771; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_775 = _out_wofireMux_T_262 & out_backSel_128; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_776 = _out_wofireMux_T_775 & _out_T_1729; // @[RegisterRouter.scala:87:24]
assign out_woready_1_495 = _out_wofireMux_T_776; // @[RegisterRouter.scala:87:24]
assign out_woready_1_496 = _out_wofireMux_T_776; // @[RegisterRouter.scala:87:24]
assign out_woready_1_497 = _out_wofireMux_T_776; // @[RegisterRouter.scala:87:24]
assign out_woready_1_498 = _out_wofireMux_T_776; // @[RegisterRouter.scala:87:24]
assign out_woready_1_499 = _out_wofireMux_T_776; // @[RegisterRouter.scala:87:24]
assign out_woready_1_500 = _out_wofireMux_T_776; // @[RegisterRouter.scala:87:24]
assign out_woready_1_501 = _out_wofireMux_T_776; // @[RegisterRouter.scala:87:24]
assign out_woready_1_502 = _out_wofireMux_T_776; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_777 = ~_out_T_1729; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_779 = _out_wofireMux_T_262 & out_backSel_129; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_780 = _out_wofireMux_T_779 & _out_T_1721; // @[RegisterRouter.scala:87:24]
assign out_woready_1_467 = _out_wofireMux_T_780; // @[RegisterRouter.scala:87:24]
assign out_woready_1_468 = _out_wofireMux_T_780; // @[RegisterRouter.scala:87:24]
assign out_woready_1_469 = _out_wofireMux_T_780; // @[RegisterRouter.scala:87:24]
assign out_woready_1_470 = _out_wofireMux_T_780; // @[RegisterRouter.scala:87:24]
assign out_woready_1_471 = _out_wofireMux_T_780; // @[RegisterRouter.scala:87:24]
assign out_woready_1_472 = _out_wofireMux_T_780; // @[RegisterRouter.scala:87:24]
assign out_woready_1_473 = _out_wofireMux_T_780; // @[RegisterRouter.scala:87:24]
assign out_woready_1_474 = _out_wofireMux_T_780; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_781 = ~_out_T_1721; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_783 = _out_wofireMux_T_262 & out_backSel_130; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_784 = _out_wofireMux_T_783 & _out_T_1797; // @[RegisterRouter.scala:87:24]
assign out_woready_1_755 = _out_wofireMux_T_784; // @[RegisterRouter.scala:87:24]
assign out_woready_1_756 = _out_wofireMux_T_784; // @[RegisterRouter.scala:87:24]
assign out_woready_1_757 = _out_wofireMux_T_784; // @[RegisterRouter.scala:87:24]
assign out_woready_1_758 = _out_wofireMux_T_784; // @[RegisterRouter.scala:87:24]
assign out_woready_1_759 = _out_wofireMux_T_784; // @[RegisterRouter.scala:87:24]
assign out_woready_1_760 = _out_wofireMux_T_784; // @[RegisterRouter.scala:87:24]
assign out_woready_1_761 = _out_wofireMux_T_784; // @[RegisterRouter.scala:87:24]
assign out_woready_1_762 = _out_wofireMux_T_784; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_785 = ~_out_T_1797; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_787 = _out_wofireMux_T_262 & out_backSel_131; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_788 = _out_wofireMux_T_787 & _out_T_1891; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1131 = _out_wofireMux_T_788; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1132 = _out_wofireMux_T_788; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1133 = _out_wofireMux_T_788; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1134 = _out_wofireMux_T_788; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1135 = _out_wofireMux_T_788; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1136 = _out_wofireMux_T_788; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1137 = _out_wofireMux_T_788; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1138 = _out_wofireMux_T_788; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_789 = ~_out_T_1891; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_791 = _out_wofireMux_T_262 & out_backSel_132; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_792 = _out_wofireMux_T_791 & _out_T_1661; // @[RegisterRouter.scala:87:24]
assign out_woready_1_240 = _out_wofireMux_T_792; // @[RegisterRouter.scala:87:24]
assign out_woready_1_241 = _out_wofireMux_T_792; // @[RegisterRouter.scala:87:24]
assign out_woready_1_242 = _out_wofireMux_T_792; // @[RegisterRouter.scala:87:24]
assign out_woready_1_243 = _out_wofireMux_T_792; // @[RegisterRouter.scala:87:24]
assign out_woready_1_244 = _out_wofireMux_T_792; // @[RegisterRouter.scala:87:24]
assign out_woready_1_245 = _out_wofireMux_T_792; // @[RegisterRouter.scala:87:24]
assign out_woready_1_246 = _out_wofireMux_T_792; // @[RegisterRouter.scala:87:24]
assign out_woready_1_247 = _out_wofireMux_T_792; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_793 = ~_out_T_1661; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_795 = _out_wofireMux_T_262 & out_backSel_133; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_796 = _out_wofireMux_T_795 & _out_T_1663; // @[RegisterRouter.scala:87:24]
assign out_woready_1_248 = _out_wofireMux_T_796; // @[RegisterRouter.scala:87:24]
assign out_woready_1_249 = _out_wofireMux_T_796; // @[RegisterRouter.scala:87:24]
assign out_woready_1_250 = _out_wofireMux_T_796; // @[RegisterRouter.scala:87:24]
assign out_woready_1_251 = _out_wofireMux_T_796; // @[RegisterRouter.scala:87:24]
assign out_woready_1_252 = _out_wofireMux_T_796; // @[RegisterRouter.scala:87:24]
assign out_woready_1_253 = _out_wofireMux_T_796; // @[RegisterRouter.scala:87:24]
assign out_woready_1_254 = _out_wofireMux_T_796; // @[RegisterRouter.scala:87:24]
assign out_woready_1_255 = _out_wofireMux_T_796; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_797 = ~_out_T_1663; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_799 = _out_wofireMux_T_262 & out_backSel_134; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_800 = _out_wofireMux_T_799 & _out_T_1723; // @[RegisterRouter.scala:87:24]
assign out_woready_1_475 = _out_wofireMux_T_800; // @[RegisterRouter.scala:87:24]
assign out_woready_1_476 = _out_wofireMux_T_800; // @[RegisterRouter.scala:87:24]
assign out_woready_1_477 = _out_wofireMux_T_800; // @[RegisterRouter.scala:87:24]
assign out_woready_1_478 = _out_wofireMux_T_800; // @[RegisterRouter.scala:87:24]
assign out_woready_1_479 = _out_wofireMux_T_800; // @[RegisterRouter.scala:87:24]
assign out_woready_1_480 = _out_wofireMux_T_800; // @[RegisterRouter.scala:87:24]
assign out_woready_1_481 = _out_wofireMux_T_800; // @[RegisterRouter.scala:87:24]
assign out_woready_1_482 = _out_wofireMux_T_800; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_801 = ~_out_T_1723; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_803 = _out_wofireMux_T_262 & out_backSel_135; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_804 = _out_wofireMux_T_803 & _out_T_1801; // @[RegisterRouter.scala:87:24]
assign out_woready_1_771 = _out_wofireMux_T_804; // @[RegisterRouter.scala:87:24]
assign out_woready_1_772 = _out_wofireMux_T_804; // @[RegisterRouter.scala:87:24]
assign out_woready_1_773 = _out_wofireMux_T_804; // @[RegisterRouter.scala:87:24]
assign out_woready_1_774 = _out_wofireMux_T_804; // @[RegisterRouter.scala:87:24]
assign out_woready_1_775 = _out_wofireMux_T_804; // @[RegisterRouter.scala:87:24]
assign out_woready_1_776 = _out_wofireMux_T_804; // @[RegisterRouter.scala:87:24]
assign out_woready_1_777 = _out_wofireMux_T_804; // @[RegisterRouter.scala:87:24]
assign out_woready_1_778 = _out_wofireMux_T_804; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_805 = ~_out_T_1801; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_807 = _out_wofireMux_T_262 & out_backSel_136; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_808 = _out_wofireMux_T_807 & _out_T_1883; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1099 = _out_wofireMux_T_808; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1100 = _out_wofireMux_T_808; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1101 = _out_wofireMux_T_808; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1102 = _out_wofireMux_T_808; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1103 = _out_wofireMux_T_808; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1104 = _out_wofireMux_T_808; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1105 = _out_wofireMux_T_808; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1106 = _out_wofireMux_T_808; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_809 = ~_out_T_1883; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_811 = _out_wofireMux_T_262 & out_backSel_137; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_812 = _out_wofireMux_T_811 & _out_T_1685; // @[RegisterRouter.scala:87:24]
assign out_woready_1_336 = _out_wofireMux_T_812; // @[RegisterRouter.scala:87:24]
assign out_woready_1_337 = _out_wofireMux_T_812; // @[RegisterRouter.scala:87:24]
assign out_woready_1_338 = _out_wofireMux_T_812; // @[RegisterRouter.scala:87:24]
assign out_woready_1_339 = _out_wofireMux_T_812; // @[RegisterRouter.scala:87:24]
assign out_woready_1_340 = _out_wofireMux_T_812; // @[RegisterRouter.scala:87:24]
assign out_woready_1_341 = _out_wofireMux_T_812; // @[RegisterRouter.scala:87:24]
assign out_woready_1_342 = _out_wofireMux_T_812; // @[RegisterRouter.scala:87:24]
assign out_woready_1_343 = _out_wofireMux_T_812; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_813 = ~_out_T_1685; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_815 = _out_wofireMux_T_262 & out_backSel_138; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_816 = _out_wofireMux_T_815 & _out_T_1601; // @[RegisterRouter.scala:87:24]
assign out_woready_1_0 = _out_wofireMux_T_816; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1 = _out_wofireMux_T_816; // @[RegisterRouter.scala:87:24]
assign out_woready_1_2 = _out_wofireMux_T_816; // @[RegisterRouter.scala:87:24]
assign out_woready_1_3 = _out_wofireMux_T_816; // @[RegisterRouter.scala:87:24]
assign out_woready_1_4 = _out_wofireMux_T_816; // @[RegisterRouter.scala:87:24]
assign out_woready_1_5 = _out_wofireMux_T_816; // @[RegisterRouter.scala:87:24]
assign out_woready_1_6 = _out_wofireMux_T_816; // @[RegisterRouter.scala:87:24]
assign out_woready_1_7 = _out_wofireMux_T_816; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_817 = ~_out_T_1601; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_819 = _out_wofireMux_T_262 & out_backSel_139; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_820 = _out_wofireMux_T_819 & _out_T_1857; // @[RegisterRouter.scala:87:24]
assign out_woready_1_995 = _out_wofireMux_T_820; // @[RegisterRouter.scala:87:24]
assign out_woready_1_996 = _out_wofireMux_T_820; // @[RegisterRouter.scala:87:24]
assign out_woready_1_997 = _out_wofireMux_T_820; // @[RegisterRouter.scala:87:24]
assign out_woready_1_998 = _out_wofireMux_T_820; // @[RegisterRouter.scala:87:24]
assign out_woready_1_999 = _out_wofireMux_T_820; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1000 = _out_wofireMux_T_820; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1001 = _out_wofireMux_T_820; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1002 = _out_wofireMux_T_820; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_821 = ~_out_T_1857; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_823 = _out_wofireMux_T_262 & out_backSel_140; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_824 = _out_wofireMux_T_823 & _out_T_1783; // @[RegisterRouter.scala:87:24]
assign out_woready_1_699 = _out_wofireMux_T_824; // @[RegisterRouter.scala:87:24]
assign out_woready_1_700 = _out_wofireMux_T_824; // @[RegisterRouter.scala:87:24]
assign out_woready_1_701 = _out_wofireMux_T_824; // @[RegisterRouter.scala:87:24]
assign out_woready_1_702 = _out_wofireMux_T_824; // @[RegisterRouter.scala:87:24]
assign out_woready_1_703 = _out_wofireMux_T_824; // @[RegisterRouter.scala:87:24]
assign out_woready_1_704 = _out_wofireMux_T_824; // @[RegisterRouter.scala:87:24]
assign out_woready_1_705 = _out_wofireMux_T_824; // @[RegisterRouter.scala:87:24]
assign out_woready_1_706 = _out_wofireMux_T_824; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_825 = ~_out_T_1783; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_827 = _out_wofireMux_T_262 & out_backSel_141; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_828 = _out_wofireMux_T_827 & _out_T_1705; // @[RegisterRouter.scala:87:24]
assign out_woready_1_410 = _out_wofireMux_T_828; // @[RegisterRouter.scala:87:24]
assign out_woready_1_411 = _out_wofireMux_T_828; // @[RegisterRouter.scala:87:24]
assign out_woready_1_412 = _out_wofireMux_T_828; // @[RegisterRouter.scala:87:24]
assign out_woready_1_413 = _out_wofireMux_T_828; // @[RegisterRouter.scala:87:24]
assign out_woready_1_414 = _out_wofireMux_T_828; // @[RegisterRouter.scala:87:24]
assign out_woready_1_415 = _out_wofireMux_T_828; // @[RegisterRouter.scala:87:24]
assign out_woready_1_416 = _out_wofireMux_T_828; // @[RegisterRouter.scala:87:24]
assign out_woready_1_417 = _out_wofireMux_T_828; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_829 = ~_out_T_1705; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_831 = _out_wofireMux_T_262 & out_backSel_142; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_832 = _out_wofireMux_T_831 & _out_T_1617; // @[RegisterRouter.scala:87:24]
assign out_woready_1_64 = _out_wofireMux_T_832; // @[RegisterRouter.scala:87:24]
assign out_woready_1_65 = _out_wofireMux_T_832; // @[RegisterRouter.scala:87:24]
assign out_woready_1_66 = _out_wofireMux_T_832; // @[RegisterRouter.scala:87:24]
assign out_woready_1_67 = _out_wofireMux_T_832; // @[RegisterRouter.scala:87:24]
assign out_woready_1_68 = _out_wofireMux_T_832; // @[RegisterRouter.scala:87:24]
assign out_woready_1_69 = _out_wofireMux_T_832; // @[RegisterRouter.scala:87:24]
assign out_woready_1_70 = _out_wofireMux_T_832; // @[RegisterRouter.scala:87:24]
assign out_woready_1_71 = _out_wofireMux_T_832; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_833 = ~_out_T_1617; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_835 = _out_wofireMux_T_262 & out_backSel_143; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_836 = _out_wofireMux_T_835 & _out_T_1835; // @[RegisterRouter.scala:87:24]
assign out_woready_1_907 = _out_wofireMux_T_836; // @[RegisterRouter.scala:87:24]
assign out_woready_1_908 = _out_wofireMux_T_836; // @[RegisterRouter.scala:87:24]
assign out_woready_1_909 = _out_wofireMux_T_836; // @[RegisterRouter.scala:87:24]
assign out_woready_1_910 = _out_wofireMux_T_836; // @[RegisterRouter.scala:87:24]
assign out_woready_1_911 = _out_wofireMux_T_836; // @[RegisterRouter.scala:87:24]
assign out_woready_1_912 = _out_wofireMux_T_836; // @[RegisterRouter.scala:87:24]
assign out_woready_1_913 = _out_wofireMux_T_836; // @[RegisterRouter.scala:87:24]
assign out_woready_1_914 = _out_wofireMux_T_836; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_837 = ~_out_T_1835; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_839 = _out_wofireMux_T_262 & out_backSel_144; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_840 = _out_wofireMux_T_839 & _out_T_1759; // @[RegisterRouter.scala:87:24]
assign out_woready_1_609 = _out_wofireMux_T_840; // @[RegisterRouter.scala:87:24]
assign out_woready_1_610 = _out_wofireMux_T_840; // @[RegisterRouter.scala:87:24]
assign out_woready_1_611 = _out_wofireMux_T_840; // @[RegisterRouter.scala:87:24]
assign out_woready_1_612 = _out_wofireMux_T_840; // @[RegisterRouter.scala:87:24]
assign out_woready_1_613 = _out_wofireMux_T_840; // @[RegisterRouter.scala:87:24]
assign out_woready_1_614 = _out_wofireMux_T_840; // @[RegisterRouter.scala:87:24]
assign out_woready_1_615 = _out_wofireMux_T_840; // @[RegisterRouter.scala:87:24]
assign out_woready_1_616 = _out_wofireMux_T_840; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_841 = ~_out_T_1759; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_843 = _out_wofireMux_T_262 & out_backSel_145; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_844 = _out_wofireMux_T_843 & _out_T_1819; // @[RegisterRouter.scala:87:24]
assign out_woready_1_843 = _out_wofireMux_T_844; // @[RegisterRouter.scala:87:24]
assign out_woready_1_844 = _out_wofireMux_T_844; // @[RegisterRouter.scala:87:24]
assign out_woready_1_845 = _out_wofireMux_T_844; // @[RegisterRouter.scala:87:24]
assign out_woready_1_846 = _out_wofireMux_T_844; // @[RegisterRouter.scala:87:24]
assign out_woready_1_847 = _out_wofireMux_T_844; // @[RegisterRouter.scala:87:24]
assign out_woready_1_848 = _out_wofireMux_T_844; // @[RegisterRouter.scala:87:24]
assign out_woready_1_849 = _out_wofireMux_T_844; // @[RegisterRouter.scala:87:24]
assign out_woready_1_850 = _out_wofireMux_T_844; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_845 = ~_out_T_1819; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_847 = _out_wofireMux_T_262 & out_backSel_146; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_848 = _out_wofireMux_T_847 & _out_T_1869; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1043 = _out_wofireMux_T_848; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1044 = _out_wofireMux_T_848; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1045 = _out_wofireMux_T_848; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1046 = _out_wofireMux_T_848; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1047 = _out_wofireMux_T_848; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1048 = _out_wofireMux_T_848; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1049 = _out_wofireMux_T_848; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1050 = _out_wofireMux_T_848; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_849 = ~_out_T_1869; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_851 = _out_wofireMux_T_262 & out_backSel_147; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_852 = _out_wofireMux_T_851 & _out_T_1657; // @[RegisterRouter.scala:87:24]
assign out_woready_1_224 = _out_wofireMux_T_852; // @[RegisterRouter.scala:87:24]
assign out_woready_1_225 = _out_wofireMux_T_852; // @[RegisterRouter.scala:87:24]
assign out_woready_1_226 = _out_wofireMux_T_852; // @[RegisterRouter.scala:87:24]
assign out_woready_1_227 = _out_wofireMux_T_852; // @[RegisterRouter.scala:87:24]
assign out_woready_1_228 = _out_wofireMux_T_852; // @[RegisterRouter.scala:87:24]
assign out_woready_1_229 = _out_wofireMux_T_852; // @[RegisterRouter.scala:87:24]
assign out_woready_1_230 = _out_wofireMux_T_852; // @[RegisterRouter.scala:87:24]
assign out_woready_1_231 = _out_wofireMux_T_852; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_853 = ~_out_T_1657; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_855 = _out_wofireMux_T_262 & out_backSel_148; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_856 = _out_wofireMux_T_855 & _out_T_1741; // @[RegisterRouter.scala:87:24]
assign out_woready_1_537 = _out_wofireMux_T_856; // @[RegisterRouter.scala:87:24]
assign out_woready_1_538 = _out_wofireMux_T_856; // @[RegisterRouter.scala:87:24]
assign out_woready_1_539 = _out_wofireMux_T_856; // @[RegisterRouter.scala:87:24]
assign out_woready_1_540 = _out_wofireMux_T_856; // @[RegisterRouter.scala:87:24]
assign out_woready_1_541 = _out_wofireMux_T_856; // @[RegisterRouter.scala:87:24]
assign out_woready_1_542 = _out_wofireMux_T_856; // @[RegisterRouter.scala:87:24]
assign out_woready_1_543 = _out_wofireMux_T_856; // @[RegisterRouter.scala:87:24]
assign out_woready_1_544 = _out_wofireMux_T_856; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_857 = ~_out_T_1741; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_859 = _out_wofireMux_T_262 & out_backSel_149; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_860 = _out_wofireMux_T_859 & _out_T_1749; // @[RegisterRouter.scala:87:24]
assign out_woready_1_569 = _out_wofireMux_T_860; // @[RegisterRouter.scala:87:24]
assign out_woready_1_570 = _out_wofireMux_T_860; // @[RegisterRouter.scala:87:24]
assign out_woready_1_571 = _out_wofireMux_T_860; // @[RegisterRouter.scala:87:24]
assign out_woready_1_572 = _out_wofireMux_T_860; // @[RegisterRouter.scala:87:24]
assign out_woready_1_573 = _out_wofireMux_T_860; // @[RegisterRouter.scala:87:24]
assign out_woready_1_574 = _out_wofireMux_T_860; // @[RegisterRouter.scala:87:24]
assign out_woready_1_575 = _out_wofireMux_T_860; // @[RegisterRouter.scala:87:24]
assign out_woready_1_576 = _out_wofireMux_T_860; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_861 = ~_out_T_1749; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_863 = _out_wofireMux_T_262 & out_backSel_150; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_864 = _out_wofireMux_T_863 & _out_T_1821; // @[RegisterRouter.scala:87:24]
assign out_woready_1_851 = _out_wofireMux_T_864; // @[RegisterRouter.scala:87:24]
assign out_woready_1_852 = _out_wofireMux_T_864; // @[RegisterRouter.scala:87:24]
assign out_woready_1_853 = _out_wofireMux_T_864; // @[RegisterRouter.scala:87:24]
assign out_woready_1_854 = _out_wofireMux_T_864; // @[RegisterRouter.scala:87:24]
assign out_woready_1_855 = _out_wofireMux_T_864; // @[RegisterRouter.scala:87:24]
assign out_woready_1_856 = _out_wofireMux_T_864; // @[RegisterRouter.scala:87:24]
assign out_woready_1_857 = _out_wofireMux_T_864; // @[RegisterRouter.scala:87:24]
assign out_woready_1_858 = _out_wofireMux_T_864; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_865 = ~_out_T_1821; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_867 = _out_wofireMux_T_262 & out_backSel_151; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_868 = _out_wofireMux_T_867 & _out_T_1867; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1035 = _out_wofireMux_T_868; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1036 = _out_wofireMux_T_868; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1037 = _out_wofireMux_T_868; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1038 = _out_wofireMux_T_868; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1039 = _out_wofireMux_T_868; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1040 = _out_wofireMux_T_868; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1041 = _out_wofireMux_T_868; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1042 = _out_wofireMux_T_868; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_869 = ~_out_T_1867; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_871 = _out_wofireMux_T_262 & out_backSel_152; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_872 = _out_wofireMux_T_871 & _out_T_1637; // @[RegisterRouter.scala:87:24]
assign out_woready_1_144 = _out_wofireMux_T_872; // @[RegisterRouter.scala:87:24]
assign out_woready_1_145 = _out_wofireMux_T_872; // @[RegisterRouter.scala:87:24]
assign out_woready_1_146 = _out_wofireMux_T_872; // @[RegisterRouter.scala:87:24]
assign out_woready_1_147 = _out_wofireMux_T_872; // @[RegisterRouter.scala:87:24]
assign out_woready_1_148 = _out_wofireMux_T_872; // @[RegisterRouter.scala:87:24]
assign out_woready_1_149 = _out_wofireMux_T_872; // @[RegisterRouter.scala:87:24]
assign out_woready_1_150 = _out_wofireMux_T_872; // @[RegisterRouter.scala:87:24]
assign out_woready_1_151 = _out_wofireMux_T_872; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_873 = ~_out_T_1637; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_875 = _out_wofireMux_T_262 & out_backSel_153; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_876 = _out_wofireMux_T_875 & _out_T_1619; // @[RegisterRouter.scala:87:24]
assign out_woready_1_72 = _out_wofireMux_T_876; // @[RegisterRouter.scala:87:24]
assign out_woready_1_73 = _out_wofireMux_T_876; // @[RegisterRouter.scala:87:24]
assign out_woready_1_74 = _out_wofireMux_T_876; // @[RegisterRouter.scala:87:24]
assign out_woready_1_75 = _out_wofireMux_T_876; // @[RegisterRouter.scala:87:24]
assign out_woready_1_76 = _out_wofireMux_T_876; // @[RegisterRouter.scala:87:24]
assign out_woready_1_77 = _out_wofireMux_T_876; // @[RegisterRouter.scala:87:24]
assign out_woready_1_78 = _out_wofireMux_T_876; // @[RegisterRouter.scala:87:24]
assign out_woready_1_79 = _out_wofireMux_T_876; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_877 = ~_out_T_1619; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_879 = _out_wofireMux_T_262 & out_backSel_154; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_880 = _out_wofireMux_T_879 & _out_T_1831; // @[RegisterRouter.scala:87:24]
assign out_woready_1_891 = _out_wofireMux_T_880; // @[RegisterRouter.scala:87:24]
assign out_woready_1_892 = _out_wofireMux_T_880; // @[RegisterRouter.scala:87:24]
assign out_woready_1_893 = _out_wofireMux_T_880; // @[RegisterRouter.scala:87:24]
assign out_woready_1_894 = _out_wofireMux_T_880; // @[RegisterRouter.scala:87:24]
assign out_woready_1_895 = _out_wofireMux_T_880; // @[RegisterRouter.scala:87:24]
assign out_woready_1_896 = _out_wofireMux_T_880; // @[RegisterRouter.scala:87:24]
assign out_woready_1_897 = _out_wofireMux_T_880; // @[RegisterRouter.scala:87:24]
assign out_woready_1_898 = _out_wofireMux_T_880; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_881 = ~_out_T_1831; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_883 = _out_wofireMux_T_262 & out_backSel_155; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_884 = _out_wofireMux_T_883 & _out_T_1787; // @[RegisterRouter.scala:87:24]
assign out_woready_1_715 = _out_wofireMux_T_884; // @[RegisterRouter.scala:87:24]
assign out_woready_1_716 = _out_wofireMux_T_884; // @[RegisterRouter.scala:87:24]
assign out_woready_1_717 = _out_wofireMux_T_884; // @[RegisterRouter.scala:87:24]
assign out_woready_1_718 = _out_wofireMux_T_884; // @[RegisterRouter.scala:87:24]
assign out_woready_1_719 = _out_wofireMux_T_884; // @[RegisterRouter.scala:87:24]
assign out_woready_1_720 = _out_wofireMux_T_884; // @[RegisterRouter.scala:87:24]
assign out_woready_1_721 = _out_wofireMux_T_884; // @[RegisterRouter.scala:87:24]
assign out_woready_1_722 = _out_wofireMux_T_884; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_885 = ~_out_T_1787; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_887 = _out_wofireMux_T_262 & out_backSel_156; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_888 = _out_wofireMux_T_887 & _out_T_1699; // @[RegisterRouter.scala:87:24]
assign out_woready_1_386 = _out_wofireMux_T_888; // @[RegisterRouter.scala:87:24]
assign out_woready_1_387 = _out_wofireMux_T_888; // @[RegisterRouter.scala:87:24]
assign out_woready_1_388 = _out_wofireMux_T_888; // @[RegisterRouter.scala:87:24]
assign out_woready_1_389 = _out_wofireMux_T_888; // @[RegisterRouter.scala:87:24]
assign out_woready_1_390 = _out_wofireMux_T_888; // @[RegisterRouter.scala:87:24]
assign out_woready_1_391 = _out_wofireMux_T_888; // @[RegisterRouter.scala:87:24]
assign out_woready_1_392 = _out_wofireMux_T_888; // @[RegisterRouter.scala:87:24]
assign out_woready_1_393 = _out_wofireMux_T_888; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_889 = ~_out_T_1699; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_891 = _out_wofireMux_T_262 & out_backSel_157; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_892 = _out_wofireMux_T_891 & _out_T_1633; // @[RegisterRouter.scala:87:24]
assign out_woready_1_128 = _out_wofireMux_T_892; // @[RegisterRouter.scala:87:24]
assign out_woready_1_129 = _out_wofireMux_T_892; // @[RegisterRouter.scala:87:24]
assign out_woready_1_130 = _out_wofireMux_T_892; // @[RegisterRouter.scala:87:24]
assign out_woready_1_131 = _out_wofireMux_T_892; // @[RegisterRouter.scala:87:24]
assign out_woready_1_132 = _out_wofireMux_T_892; // @[RegisterRouter.scala:87:24]
assign out_woready_1_133 = _out_wofireMux_T_892; // @[RegisterRouter.scala:87:24]
assign out_woready_1_134 = _out_wofireMux_T_892; // @[RegisterRouter.scala:87:24]
assign out_woready_1_135 = _out_wofireMux_T_892; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_893 = ~_out_T_1633; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_895 = _out_wofireMux_T_262 & out_backSel_158; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_896 = _out_wofireMux_T_895 & _out_T_1849; // @[RegisterRouter.scala:87:24]
assign out_woready_1_963 = _out_wofireMux_T_896; // @[RegisterRouter.scala:87:24]
assign out_woready_1_964 = _out_wofireMux_T_896; // @[RegisterRouter.scala:87:24]
assign out_woready_1_965 = _out_wofireMux_T_896; // @[RegisterRouter.scala:87:24]
assign out_woready_1_966 = _out_wofireMux_T_896; // @[RegisterRouter.scala:87:24]
assign out_woready_1_967 = _out_wofireMux_T_896; // @[RegisterRouter.scala:87:24]
assign out_woready_1_968 = _out_wofireMux_T_896; // @[RegisterRouter.scala:87:24]
assign out_woready_1_969 = _out_wofireMux_T_896; // @[RegisterRouter.scala:87:24]
assign out_woready_1_970 = _out_wofireMux_T_896; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_897 = ~_out_T_1849; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_899 = _out_wofireMux_T_262 & out_backSel_159; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_900 = _out_wofireMux_T_899 & _out_T_1765; // @[RegisterRouter.scala:87:24]
assign out_woready_1_633 = _out_wofireMux_T_900; // @[RegisterRouter.scala:87:24]
assign out_woready_1_634 = _out_wofireMux_T_900; // @[RegisterRouter.scala:87:24]
assign out_woready_1_635 = _out_wofireMux_T_900; // @[RegisterRouter.scala:87:24]
assign out_woready_1_636 = _out_wofireMux_T_900; // @[RegisterRouter.scala:87:24]
assign out_woready_1_637 = _out_wofireMux_T_900; // @[RegisterRouter.scala:87:24]
assign out_woready_1_638 = _out_wofireMux_T_900; // @[RegisterRouter.scala:87:24]
assign out_woready_1_639 = _out_wofireMux_T_900; // @[RegisterRouter.scala:87:24]
assign out_woready_1_640 = _out_wofireMux_T_900; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_901 = ~_out_T_1765; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_903 = _out_wofireMux_T_262 & out_backSel_160; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_904 = _out_wofireMux_T_903 & _out_T_1681; // @[RegisterRouter.scala:87:24]
assign out_woready_1_320 = _out_wofireMux_T_904; // @[RegisterRouter.scala:87:24]
assign out_woready_1_321 = _out_wofireMux_T_904; // @[RegisterRouter.scala:87:24]
assign out_woready_1_322 = _out_wofireMux_T_904; // @[RegisterRouter.scala:87:24]
assign out_woready_1_323 = _out_wofireMux_T_904; // @[RegisterRouter.scala:87:24]
assign out_woready_1_324 = _out_wofireMux_T_904; // @[RegisterRouter.scala:87:24]
assign out_woready_1_325 = _out_wofireMux_T_904; // @[RegisterRouter.scala:87:24]
assign out_woready_1_326 = _out_wofireMux_T_904; // @[RegisterRouter.scala:87:24]
assign out_woready_1_327 = _out_wofireMux_T_904; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_905 = ~_out_T_1681; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_907 = _out_wofireMux_T_262 & out_backSel_161; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_908 = _out_wofireMux_T_907 & _out_T_1745; // @[RegisterRouter.scala:87:24]
assign out_woready_1_553 = _out_wofireMux_T_908; // @[RegisterRouter.scala:87:24]
assign out_woready_1_554 = _out_wofireMux_T_908; // @[RegisterRouter.scala:87:24]
assign out_woready_1_555 = _out_wofireMux_T_908; // @[RegisterRouter.scala:87:24]
assign out_woready_1_556 = _out_wofireMux_T_908; // @[RegisterRouter.scala:87:24]
assign out_woready_1_557 = _out_wofireMux_T_908; // @[RegisterRouter.scala:87:24]
assign out_woready_1_558 = _out_wofireMux_T_908; // @[RegisterRouter.scala:87:24]
assign out_woready_1_559 = _out_wofireMux_T_908; // @[RegisterRouter.scala:87:24]
assign out_woready_1_560 = _out_wofireMux_T_908; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_909 = ~_out_T_1745; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_911 = _out_wofireMux_T_262 & out_backSel_162; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_912 = _out_wofireMux_T_911 & _out_T_1809; // @[RegisterRouter.scala:87:24]
assign out_woready_1_803 = _out_wofireMux_T_912; // @[RegisterRouter.scala:87:24]
assign out_woready_1_804 = _out_wofireMux_T_912; // @[RegisterRouter.scala:87:24]
assign out_woready_1_805 = _out_wofireMux_T_912; // @[RegisterRouter.scala:87:24]
assign out_woready_1_806 = _out_wofireMux_T_912; // @[RegisterRouter.scala:87:24]
assign out_woready_1_807 = _out_wofireMux_T_912; // @[RegisterRouter.scala:87:24]
assign out_woready_1_808 = _out_wofireMux_T_912; // @[RegisterRouter.scala:87:24]
assign out_woready_1_809 = _out_wofireMux_T_912; // @[RegisterRouter.scala:87:24]
assign out_woready_1_810 = _out_wofireMux_T_912; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_913 = ~_out_T_1809; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_915 = _out_wofireMux_T_262 & out_backSel_163; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_916 = _out_wofireMux_T_915 & _out_T_1895; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1147 = _out_wofireMux_T_916; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1148 = _out_wofireMux_T_916; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1149 = _out_wofireMux_T_916; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1150 = _out_wofireMux_T_916; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1151 = _out_wofireMux_T_916; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1152 = _out_wofireMux_T_916; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1153 = _out_wofireMux_T_916; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1154 = _out_wofireMux_T_916; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_917 = ~_out_T_1895; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_919 = _out_wofireMux_T_262 & out_backSel_164; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_920 = _out_wofireMux_T_919 & _out_T_1645; // @[RegisterRouter.scala:87:24]
assign out_woready_1_176 = _out_wofireMux_T_920; // @[RegisterRouter.scala:87:24]
assign out_woready_1_177 = _out_wofireMux_T_920; // @[RegisterRouter.scala:87:24]
assign out_woready_1_178 = _out_wofireMux_T_920; // @[RegisterRouter.scala:87:24]
assign out_woready_1_179 = _out_wofireMux_T_920; // @[RegisterRouter.scala:87:24]
assign out_woready_1_180 = _out_wofireMux_T_920; // @[RegisterRouter.scala:87:24]
assign out_woready_1_181 = _out_wofireMux_T_920; // @[RegisterRouter.scala:87:24]
assign out_woready_1_182 = _out_wofireMux_T_920; // @[RegisterRouter.scala:87:24]
assign out_woready_1_183 = _out_wofireMux_T_920; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_921 = ~_out_T_1645; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_923 = _out_wofireMux_T_262 & out_backSel_165; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_924 = _out_wofireMux_T_923 & _out_T_1687; // @[RegisterRouter.scala:87:24]
assign out_woready_1_344 = _out_wofireMux_T_924; // @[RegisterRouter.scala:87:24]
assign out_woready_1_345 = _out_wofireMux_T_924; // @[RegisterRouter.scala:87:24]
assign out_woready_1_346 = _out_wofireMux_T_924; // @[RegisterRouter.scala:87:24]
assign out_woready_1_347 = _out_wofireMux_T_924; // @[RegisterRouter.scala:87:24]
assign out_woready_1_348 = _out_wofireMux_T_924; // @[RegisterRouter.scala:87:24]
assign out_woready_1_349 = _out_wofireMux_T_924; // @[RegisterRouter.scala:87:24]
assign out_woready_1_350 = _out_wofireMux_T_924; // @[RegisterRouter.scala:87:24]
assign out_woready_1_351 = _out_wofireMux_T_924; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_925 = ~_out_T_1687; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_927 = _out_wofireMux_T_262 & out_backSel_166; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_928 = _out_wofireMux_T_927 & _out_T_1737; // @[RegisterRouter.scala:87:24]
assign out_woready_1_527 = _out_wofireMux_T_928; // @[RegisterRouter.scala:87:24]
assign out_woready_1_528 = _out_wofireMux_T_928; // @[RegisterRouter.scala:87:24]
assign out_woready_1_529 = _out_wofireMux_T_928; // @[RegisterRouter.scala:87:24]
assign out_woready_1_530 = _out_wofireMux_T_928; // @[RegisterRouter.scala:87:24]
assign out_woready_1_531 = _out_wofireMux_T_928; // @[RegisterRouter.scala:87:24]
assign out_woready_1_532 = _out_wofireMux_T_928; // @[RegisterRouter.scala:87:24]
assign out_woready_1_533 = _out_wofireMux_T_928; // @[RegisterRouter.scala:87:24]
assign out_woready_1_534 = _out_wofireMux_T_928; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_929 = ~_out_T_1737; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_931 = _out_wofireMux_T_262 & out_backSel_167; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_932 = _out_wofireMux_T_931 & _out_T_1807; // @[RegisterRouter.scala:87:24]
assign out_woready_1_795 = _out_wofireMux_T_932; // @[RegisterRouter.scala:87:24]
assign out_woready_1_796 = _out_wofireMux_T_932; // @[RegisterRouter.scala:87:24]
assign out_woready_1_797 = _out_wofireMux_T_932; // @[RegisterRouter.scala:87:24]
assign out_woready_1_798 = _out_wofireMux_T_932; // @[RegisterRouter.scala:87:24]
assign out_woready_1_799 = _out_wofireMux_T_932; // @[RegisterRouter.scala:87:24]
assign out_woready_1_800 = _out_wofireMux_T_932; // @[RegisterRouter.scala:87:24]
assign out_woready_1_801 = _out_wofireMux_T_932; // @[RegisterRouter.scala:87:24]
assign out_woready_1_802 = _out_wofireMux_T_932; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_933 = ~_out_T_1807; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_935 = _out_wofireMux_T_262 & out_backSel_168; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_936 = _out_wofireMux_T_935 & _out_T_1875; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1067 = _out_wofireMux_T_936; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1068 = _out_wofireMux_T_936; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1069 = _out_wofireMux_T_936; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1070 = _out_wofireMux_T_936; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1071 = _out_wofireMux_T_936; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1072 = _out_wofireMux_T_936; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1073 = _out_wofireMux_T_936; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1074 = _out_wofireMux_T_936; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_937 = ~_out_T_1875; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_939 = _out_wofireMux_T_262 & out_backSel_169; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_940 = _out_wofireMux_T_939 & _out_T_1703; // @[RegisterRouter.scala:87:24]
assign out_woready_1_402 = _out_wofireMux_T_940; // @[RegisterRouter.scala:87:24]
assign out_woready_1_403 = _out_wofireMux_T_940; // @[RegisterRouter.scala:87:24]
assign out_woready_1_404 = _out_wofireMux_T_940; // @[RegisterRouter.scala:87:24]
assign out_woready_1_405 = _out_wofireMux_T_940; // @[RegisterRouter.scala:87:24]
assign out_woready_1_406 = _out_wofireMux_T_940; // @[RegisterRouter.scala:87:24]
assign out_woready_1_407 = _out_wofireMux_T_940; // @[RegisterRouter.scala:87:24]
assign out_woready_1_408 = _out_wofireMux_T_940; // @[RegisterRouter.scala:87:24]
assign out_woready_1_409 = _out_wofireMux_T_940; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_941 = ~_out_T_1703; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_943 = _out_wofireMux_T_262 & out_backSel_170; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_944 = _out_wofireMux_T_943 & _out_T_1607; // @[RegisterRouter.scala:87:24]
assign out_woready_1_24 = _out_wofireMux_T_944; // @[RegisterRouter.scala:87:24]
assign out_woready_1_25 = _out_wofireMux_T_944; // @[RegisterRouter.scala:87:24]
assign out_woready_1_26 = _out_wofireMux_T_944; // @[RegisterRouter.scala:87:24]
assign out_woready_1_27 = _out_wofireMux_T_944; // @[RegisterRouter.scala:87:24]
assign out_woready_1_28 = _out_wofireMux_T_944; // @[RegisterRouter.scala:87:24]
assign out_woready_1_29 = _out_wofireMux_T_944; // @[RegisterRouter.scala:87:24]
assign out_woready_1_30 = _out_wofireMux_T_944; // @[RegisterRouter.scala:87:24]
assign out_woready_1_31 = _out_wofireMux_T_944; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_945 = ~_out_T_1607; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_947 = _out_wofireMux_T_262 & out_backSel_171; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_948 = _out_wofireMux_T_947 & _out_T_1855; // @[RegisterRouter.scala:87:24]
assign out_woready_1_987 = _out_wofireMux_T_948; // @[RegisterRouter.scala:87:24]
assign out_woready_1_988 = _out_wofireMux_T_948; // @[RegisterRouter.scala:87:24]
assign out_woready_1_989 = _out_wofireMux_T_948; // @[RegisterRouter.scala:87:24]
assign out_woready_1_990 = _out_wofireMux_T_948; // @[RegisterRouter.scala:87:24]
assign out_woready_1_991 = _out_wofireMux_T_948; // @[RegisterRouter.scala:87:24]
assign out_woready_1_992 = _out_wofireMux_T_948; // @[RegisterRouter.scala:87:24]
assign out_woready_1_993 = _out_wofireMux_T_948; // @[RegisterRouter.scala:87:24]
assign out_woready_1_994 = _out_wofireMux_T_948; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_949 = ~_out_T_1855; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_951 = _out_wofireMux_T_262 & out_backSel_172; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_952 = _out_wofireMux_T_951 & _out_T_1769; // @[RegisterRouter.scala:87:24]
assign out_woready_1_649 = _out_wofireMux_T_952; // @[RegisterRouter.scala:87:24]
assign out_woready_1_650 = _out_wofireMux_T_952; // @[RegisterRouter.scala:87:24]
assign out_woready_1_651 = _out_wofireMux_T_952; // @[RegisterRouter.scala:87:24]
assign out_woready_1_652 = _out_wofireMux_T_952; // @[RegisterRouter.scala:87:24]
assign out_woready_1_653 = _out_wofireMux_T_952; // @[RegisterRouter.scala:87:24]
assign out_woready_1_654 = _out_wofireMux_T_952; // @[RegisterRouter.scala:87:24]
assign out_woready_1_655 = _out_wofireMux_T_952; // @[RegisterRouter.scala:87:24]
assign out_woready_1_656 = _out_wofireMux_T_952; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_953 = ~_out_T_1769; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_955 = _out_wofireMux_T_262 & out_backSel_173; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_956 = _out_wofireMux_T_955 & _out_T_1719; // @[RegisterRouter.scala:87:24]
assign out_woready_1_459 = _out_wofireMux_T_956; // @[RegisterRouter.scala:87:24]
assign out_woready_1_460 = _out_wofireMux_T_956; // @[RegisterRouter.scala:87:24]
assign out_woready_1_461 = _out_wofireMux_T_956; // @[RegisterRouter.scala:87:24]
assign out_woready_1_462 = _out_wofireMux_T_956; // @[RegisterRouter.scala:87:24]
assign out_woready_1_463 = _out_wofireMux_T_956; // @[RegisterRouter.scala:87:24]
assign out_woready_1_464 = _out_wofireMux_T_956; // @[RegisterRouter.scala:87:24]
assign out_woready_1_465 = _out_wofireMux_T_956; // @[RegisterRouter.scala:87:24]
assign out_woready_1_466 = _out_wofireMux_T_956; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_957 = ~_out_T_1719; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_959 = _out_wofireMux_T_262 & out_backSel_174; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_960 = _out_wofireMux_T_959 & _out_T_1621; // @[RegisterRouter.scala:87:24]
assign out_woready_1_80 = _out_wofireMux_T_960; // @[RegisterRouter.scala:87:24]
assign out_woready_1_81 = _out_wofireMux_T_960; // @[RegisterRouter.scala:87:24]
assign out_woready_1_82 = _out_wofireMux_T_960; // @[RegisterRouter.scala:87:24]
assign out_woready_1_83 = _out_wofireMux_T_960; // @[RegisterRouter.scala:87:24]
assign out_woready_1_84 = _out_wofireMux_T_960; // @[RegisterRouter.scala:87:24]
assign out_woready_1_85 = _out_wofireMux_T_960; // @[RegisterRouter.scala:87:24]
assign out_woready_1_86 = _out_wofireMux_T_960; // @[RegisterRouter.scala:87:24]
assign out_woready_1_87 = _out_wofireMux_T_960; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_961 = ~_out_T_1621; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_963 = _out_wofireMux_T_262 & out_backSel_175; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_964 = _out_wofireMux_T_963 & _out_T_1833; // @[RegisterRouter.scala:87:24]
assign out_woready_1_899 = _out_wofireMux_T_964; // @[RegisterRouter.scala:87:24]
assign out_woready_1_900 = _out_wofireMux_T_964; // @[RegisterRouter.scala:87:24]
assign out_woready_1_901 = _out_wofireMux_T_964; // @[RegisterRouter.scala:87:24]
assign out_woready_1_902 = _out_wofireMux_T_964; // @[RegisterRouter.scala:87:24]
assign out_woready_1_903 = _out_wofireMux_T_964; // @[RegisterRouter.scala:87:24]
assign out_woready_1_904 = _out_wofireMux_T_964; // @[RegisterRouter.scala:87:24]
assign out_woready_1_905 = _out_wofireMux_T_964; // @[RegisterRouter.scala:87:24]
assign out_woready_1_906 = _out_wofireMux_T_964; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_965 = ~_out_T_1833; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_967 = _out_wofireMux_T_262 & out_backSel_176; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_968 = _out_wofireMux_T_967 & _out_T_1751; // @[RegisterRouter.scala:87:24]
assign out_woready_1_577 = _out_wofireMux_T_968; // @[RegisterRouter.scala:87:24]
assign out_woready_1_578 = _out_wofireMux_T_968; // @[RegisterRouter.scala:87:24]
assign out_woready_1_579 = _out_wofireMux_T_968; // @[RegisterRouter.scala:87:24]
assign out_woready_1_580 = _out_wofireMux_T_968; // @[RegisterRouter.scala:87:24]
assign out_woready_1_581 = _out_wofireMux_T_968; // @[RegisterRouter.scala:87:24]
assign out_woready_1_582 = _out_wofireMux_T_968; // @[RegisterRouter.scala:87:24]
assign out_woready_1_583 = _out_wofireMux_T_968; // @[RegisterRouter.scala:87:24]
assign out_woready_1_584 = _out_wofireMux_T_968; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_969 = ~_out_T_1751; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_971 = _out_wofireMux_T_262 & out_backSel_177; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_972 = _out_wofireMux_T_971 & _out_T_1827; // @[RegisterRouter.scala:87:24]
assign out_woready_1_875 = _out_wofireMux_T_972; // @[RegisterRouter.scala:87:24]
assign out_woready_1_876 = _out_wofireMux_T_972; // @[RegisterRouter.scala:87:24]
assign out_woready_1_877 = _out_wofireMux_T_972; // @[RegisterRouter.scala:87:24]
assign out_woready_1_878 = _out_wofireMux_T_972; // @[RegisterRouter.scala:87:24]
assign out_woready_1_879 = _out_wofireMux_T_972; // @[RegisterRouter.scala:87:24]
assign out_woready_1_880 = _out_wofireMux_T_972; // @[RegisterRouter.scala:87:24]
assign out_woready_1_881 = _out_wofireMux_T_972; // @[RegisterRouter.scala:87:24]
assign out_woready_1_882 = _out_wofireMux_T_972; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_973 = ~_out_T_1827; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_975 = _out_wofireMux_T_262 & out_backSel_178; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_976 = _out_wofireMux_T_975 & _out_T_1893; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1139 = _out_wofireMux_T_976; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1140 = _out_wofireMux_T_976; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1141 = _out_wofireMux_T_976; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1142 = _out_wofireMux_T_976; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1143 = _out_wofireMux_T_976; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1144 = _out_wofireMux_T_976; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1145 = _out_wofireMux_T_976; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1146 = _out_wofireMux_T_976; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_977 = ~_out_T_1893; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_979 = _out_wofireMux_T_262 & out_backSel_179; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_980 = _out_wofireMux_T_979 & _out_T_1647; // @[RegisterRouter.scala:87:24]
assign out_woready_1_184 = _out_wofireMux_T_980; // @[RegisterRouter.scala:87:24]
assign out_woready_1_185 = _out_wofireMux_T_980; // @[RegisterRouter.scala:87:24]
assign out_woready_1_186 = _out_wofireMux_T_980; // @[RegisterRouter.scala:87:24]
assign out_woready_1_187 = _out_wofireMux_T_980; // @[RegisterRouter.scala:87:24]
assign out_woready_1_188 = _out_wofireMux_T_980; // @[RegisterRouter.scala:87:24]
assign out_woready_1_189 = _out_wofireMux_T_980; // @[RegisterRouter.scala:87:24]
assign out_woready_1_190 = _out_wofireMux_T_980; // @[RegisterRouter.scala:87:24]
assign out_woready_1_191 = _out_wofireMux_T_980; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_981 = ~_out_T_1647; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_983 = _out_wofireMux_T_262 & out_backSel_180; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_984 = _out_wofireMux_T_983 & _out_T_1747; // @[RegisterRouter.scala:87:24]
assign out_woready_1_561 = _out_wofireMux_T_984; // @[RegisterRouter.scala:87:24]
assign out_woready_1_562 = _out_wofireMux_T_984; // @[RegisterRouter.scala:87:24]
assign out_woready_1_563 = _out_wofireMux_T_984; // @[RegisterRouter.scala:87:24]
assign out_woready_1_564 = _out_wofireMux_T_984; // @[RegisterRouter.scala:87:24]
assign out_woready_1_565 = _out_wofireMux_T_984; // @[RegisterRouter.scala:87:24]
assign out_woready_1_566 = _out_wofireMux_T_984; // @[RegisterRouter.scala:87:24]
assign out_woready_1_567 = _out_wofireMux_T_984; // @[RegisterRouter.scala:87:24]
assign out_woready_1_568 = _out_wofireMux_T_984; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_985 = ~_out_T_1747; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_987 = _out_wofireMux_T_262 & out_backSel_181; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_988 = _out_wofireMux_T_987 & _out_T_1763; // @[RegisterRouter.scala:87:24]
assign out_woready_1_625 = _out_wofireMux_T_988; // @[RegisterRouter.scala:87:24]
assign out_woready_1_626 = _out_wofireMux_T_988; // @[RegisterRouter.scala:87:24]
assign out_woready_1_627 = _out_wofireMux_T_988; // @[RegisterRouter.scala:87:24]
assign out_woready_1_628 = _out_wofireMux_T_988; // @[RegisterRouter.scala:87:24]
assign out_woready_1_629 = _out_wofireMux_T_988; // @[RegisterRouter.scala:87:24]
assign out_woready_1_630 = _out_wofireMux_T_988; // @[RegisterRouter.scala:87:24]
assign out_woready_1_631 = _out_wofireMux_T_988; // @[RegisterRouter.scala:87:24]
assign out_woready_1_632 = _out_wofireMux_T_988; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_989 = ~_out_T_1763; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_991 = _out_wofireMux_T_262 & out_backSel_182; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_992 = _out_wofireMux_T_991 & _out_T_1829; // @[RegisterRouter.scala:87:24]
assign out_woready_1_883 = _out_wofireMux_T_992; // @[RegisterRouter.scala:87:24]
assign out_woready_1_884 = _out_wofireMux_T_992; // @[RegisterRouter.scala:87:24]
assign out_woready_1_885 = _out_wofireMux_T_992; // @[RegisterRouter.scala:87:24]
assign out_woready_1_886 = _out_wofireMux_T_992; // @[RegisterRouter.scala:87:24]
assign out_woready_1_887 = _out_wofireMux_T_992; // @[RegisterRouter.scala:87:24]
assign out_woready_1_888 = _out_wofireMux_T_992; // @[RegisterRouter.scala:87:24]
assign out_woready_1_889 = _out_wofireMux_T_992; // @[RegisterRouter.scala:87:24]
assign out_woready_1_890 = _out_wofireMux_T_992; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_993 = ~_out_T_1829; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_995 = _out_wofireMux_T_262 & out_backSel_183; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_996 = _out_wofireMux_T_995 & _out_T_1873; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1059 = _out_wofireMux_T_996; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1060 = _out_wofireMux_T_996; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1061 = _out_wofireMux_T_996; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1062 = _out_wofireMux_T_996; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1063 = _out_wofireMux_T_996; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1064 = _out_wofireMux_T_996; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1065 = _out_wofireMux_T_996; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1066 = _out_wofireMux_T_996; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_997 = ~_out_T_1873; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_999 = _out_wofireMux_T_262 & out_backSel_184; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_1000 = _out_wofireMux_T_999 & _out_T_1627; // @[RegisterRouter.scala:87:24]
assign out_woready_1_104 = _out_wofireMux_T_1000; // @[RegisterRouter.scala:87:24]
assign out_woready_1_105 = _out_wofireMux_T_1000; // @[RegisterRouter.scala:87:24]
assign out_woready_1_106 = _out_wofireMux_T_1000; // @[RegisterRouter.scala:87:24]
assign out_woready_1_107 = _out_wofireMux_T_1000; // @[RegisterRouter.scala:87:24]
assign out_woready_1_108 = _out_wofireMux_T_1000; // @[RegisterRouter.scala:87:24]
assign out_woready_1_109 = _out_wofireMux_T_1000; // @[RegisterRouter.scala:87:24]
assign out_woready_1_110 = _out_wofireMux_T_1000; // @[RegisterRouter.scala:87:24]
assign out_woready_1_111 = _out_wofireMux_T_1000; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1001 = ~_out_T_1627; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1003 = _out_wofireMux_T_262 & out_backSel_185; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_1004 = _out_wofireMux_T_1003 & _out_T_1623; // @[RegisterRouter.scala:87:24]
assign out_woready_1_88 = _out_wofireMux_T_1004; // @[RegisterRouter.scala:87:24]
assign out_woready_1_89 = _out_wofireMux_T_1004; // @[RegisterRouter.scala:87:24]
assign out_woready_1_90 = _out_wofireMux_T_1004; // @[RegisterRouter.scala:87:24]
assign out_woready_1_91 = _out_wofireMux_T_1004; // @[RegisterRouter.scala:87:24]
assign out_woready_1_92 = _out_wofireMux_T_1004; // @[RegisterRouter.scala:87:24]
assign out_woready_1_93 = _out_wofireMux_T_1004; // @[RegisterRouter.scala:87:24]
assign out_woready_1_94 = _out_wofireMux_T_1004; // @[RegisterRouter.scala:87:24]
assign out_woready_1_95 = _out_wofireMux_T_1004; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1005 = ~_out_T_1623; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1007 = _out_wofireMux_T_262 & out_backSel_186; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_1008 = _out_wofireMux_T_1007 & _out_T_1851; // @[RegisterRouter.scala:87:24]
assign out_woready_1_971 = _out_wofireMux_T_1008; // @[RegisterRouter.scala:87:24]
assign out_woready_1_972 = _out_wofireMux_T_1008; // @[RegisterRouter.scala:87:24]
assign out_woready_1_973 = _out_wofireMux_T_1008; // @[RegisterRouter.scala:87:24]
assign out_woready_1_974 = _out_wofireMux_T_1008; // @[RegisterRouter.scala:87:24]
assign out_woready_1_975 = _out_wofireMux_T_1008; // @[RegisterRouter.scala:87:24]
assign out_woready_1_976 = _out_wofireMux_T_1008; // @[RegisterRouter.scala:87:24]
assign out_woready_1_977 = _out_wofireMux_T_1008; // @[RegisterRouter.scala:87:24]
assign out_woready_1_978 = _out_wofireMux_T_1008; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1009 = ~_out_T_1851; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1011 = _out_wofireMux_T_262 & out_backSel_187; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_1012 = _out_wofireMux_T_1011 & _out_T_1767; // @[RegisterRouter.scala:87:24]
assign out_woready_1_641 = _out_wofireMux_T_1012; // @[RegisterRouter.scala:87:24]
assign out_woready_1_642 = _out_wofireMux_T_1012; // @[RegisterRouter.scala:87:24]
assign out_woready_1_643 = _out_wofireMux_T_1012; // @[RegisterRouter.scala:87:24]
assign out_woready_1_644 = _out_wofireMux_T_1012; // @[RegisterRouter.scala:87:24]
assign out_woready_1_645 = _out_wofireMux_T_1012; // @[RegisterRouter.scala:87:24]
assign out_woready_1_646 = _out_wofireMux_T_1012; // @[RegisterRouter.scala:87:24]
assign out_woready_1_647 = _out_wofireMux_T_1012; // @[RegisterRouter.scala:87:24]
assign out_woready_1_648 = _out_wofireMux_T_1012; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1013 = ~_out_T_1767; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1015 = _out_wofireMux_T_262 & out_backSel_188; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_1016 = _out_wofireMux_T_1015 & _out_T_1701; // @[RegisterRouter.scala:87:24]
assign out_woready_1_394 = _out_wofireMux_T_1016; // @[RegisterRouter.scala:87:24]
assign out_woready_1_395 = _out_wofireMux_T_1016; // @[RegisterRouter.scala:87:24]
assign out_woready_1_396 = _out_wofireMux_T_1016; // @[RegisterRouter.scala:87:24]
assign out_woready_1_397 = _out_wofireMux_T_1016; // @[RegisterRouter.scala:87:24]
assign out_woready_1_398 = _out_wofireMux_T_1016; // @[RegisterRouter.scala:87:24]
assign out_woready_1_399 = _out_wofireMux_T_1016; // @[RegisterRouter.scala:87:24]
assign out_woready_1_400 = _out_wofireMux_T_1016; // @[RegisterRouter.scala:87:24]
assign out_woready_1_401 = _out_wofireMux_T_1016; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1017 = ~_out_T_1701; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1019 = _out_wofireMux_T_262 & out_backSel_189; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_1020 = _out_wofireMux_T_1019 & _out_T_1635; // @[RegisterRouter.scala:87:24]
assign out_woready_1_136 = _out_wofireMux_T_1020; // @[RegisterRouter.scala:87:24]
assign out_woready_1_137 = _out_wofireMux_T_1020; // @[RegisterRouter.scala:87:24]
assign out_woready_1_138 = _out_wofireMux_T_1020; // @[RegisterRouter.scala:87:24]
assign out_woready_1_139 = _out_wofireMux_T_1020; // @[RegisterRouter.scala:87:24]
assign out_woready_1_140 = _out_wofireMux_T_1020; // @[RegisterRouter.scala:87:24]
assign out_woready_1_141 = _out_wofireMux_T_1020; // @[RegisterRouter.scala:87:24]
assign out_woready_1_142 = _out_wofireMux_T_1020; // @[RegisterRouter.scala:87:24]
assign out_woready_1_143 = _out_wofireMux_T_1020; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1021 = ~_out_T_1635; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1023 = _out_wofireMux_T_262 & out_backSel_190; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_1024 = _out_wofireMux_T_1023 & _out_T_1871; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1051 = _out_wofireMux_T_1024; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1052 = _out_wofireMux_T_1024; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1053 = _out_wofireMux_T_1024; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1054 = _out_wofireMux_T_1024; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1055 = _out_wofireMux_T_1024; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1056 = _out_wofireMux_T_1024; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1057 = _out_wofireMux_T_1024; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1058 = _out_wofireMux_T_1024; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1025 = ~_out_T_1871; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1027 = _out_wofireMux_T_262 & out_backSel_191; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_1028 = _out_wofireMux_T_1027 & _out_T_1753; // @[RegisterRouter.scala:87:24]
assign out_woready_1_585 = _out_wofireMux_T_1028; // @[RegisterRouter.scala:87:24]
assign out_woready_1_586 = _out_wofireMux_T_1028; // @[RegisterRouter.scala:87:24]
assign out_woready_1_587 = _out_wofireMux_T_1028; // @[RegisterRouter.scala:87:24]
assign out_woready_1_588 = _out_wofireMux_T_1028; // @[RegisterRouter.scala:87:24]
assign out_woready_1_589 = _out_wofireMux_T_1028; // @[RegisterRouter.scala:87:24]
assign out_woready_1_590 = _out_wofireMux_T_1028; // @[RegisterRouter.scala:87:24]
assign out_woready_1_591 = _out_wofireMux_T_1028; // @[RegisterRouter.scala:87:24]
assign out_woready_1_592 = _out_wofireMux_T_1028; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1029 = ~_out_T_1753; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1031 = _out_wofireMux_T_262 & out_backSel_192; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_1032 = _out_wofireMux_T_1031 & _out_T_1683; // @[RegisterRouter.scala:87:24]
assign out_woready_1_328 = _out_wofireMux_T_1032; // @[RegisterRouter.scala:87:24]
assign out_woready_1_329 = _out_wofireMux_T_1032; // @[RegisterRouter.scala:87:24]
assign out_woready_1_330 = _out_wofireMux_T_1032; // @[RegisterRouter.scala:87:24]
assign out_woready_1_331 = _out_wofireMux_T_1032; // @[RegisterRouter.scala:87:24]
assign out_woready_1_332 = _out_wofireMux_T_1032; // @[RegisterRouter.scala:87:24]
assign out_woready_1_333 = _out_wofireMux_T_1032; // @[RegisterRouter.scala:87:24]
assign out_woready_1_334 = _out_wofireMux_T_1032; // @[RegisterRouter.scala:87:24]
assign out_woready_1_335 = _out_wofireMux_T_1032; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1033 = ~_out_T_1683; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1035 = _out_wofireMux_T_262 & out_backSel_193; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_1036 = _out_wofireMux_T_1035 & _out_T_1709; // @[RegisterRouter.scala:87:24]
assign out_woready_1_426 = _out_wofireMux_T_1036; // @[RegisterRouter.scala:87:24]
assign out_woready_1_427 = _out_wofireMux_T_1036; // @[RegisterRouter.scala:87:24]
assign out_woready_1_428 = _out_wofireMux_T_1036; // @[RegisterRouter.scala:87:24]
assign out_woready_1_429 = _out_wofireMux_T_1036; // @[RegisterRouter.scala:87:24]
assign out_woready_1_430 = _out_wofireMux_T_1036; // @[RegisterRouter.scala:87:24]
assign out_woready_1_431 = _out_wofireMux_T_1036; // @[RegisterRouter.scala:87:24]
assign out_woready_1_432 = _out_wofireMux_T_1036; // @[RegisterRouter.scala:87:24]
assign out_woready_1_433 = _out_wofireMux_T_1036; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1037 = ~_out_T_1709; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1039 = _out_wofireMux_T_262 & out_backSel_194; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_1040 = _out_wofireMux_T_1039 & _out_T_1817; // @[RegisterRouter.scala:87:24]
assign out_woready_1_835 = _out_wofireMux_T_1040; // @[RegisterRouter.scala:87:24]
assign out_woready_1_836 = _out_wofireMux_T_1040; // @[RegisterRouter.scala:87:24]
assign out_woready_1_837 = _out_wofireMux_T_1040; // @[RegisterRouter.scala:87:24]
assign out_woready_1_838 = _out_wofireMux_T_1040; // @[RegisterRouter.scala:87:24]
assign out_woready_1_839 = _out_wofireMux_T_1040; // @[RegisterRouter.scala:87:24]
assign out_woready_1_840 = _out_wofireMux_T_1040; // @[RegisterRouter.scala:87:24]
assign out_woready_1_841 = _out_wofireMux_T_1040; // @[RegisterRouter.scala:87:24]
assign out_woready_1_842 = _out_wofireMux_T_1040; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1041 = ~_out_T_1817; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1043 = _out_wofireMux_T_262 & out_backSel_195; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_1044 = _out_wofireMux_T_1043 & _out_T_1885; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1107 = _out_wofireMux_T_1044; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1108 = _out_wofireMux_T_1044; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1109 = _out_wofireMux_T_1044; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1110 = _out_wofireMux_T_1044; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1111 = _out_wofireMux_T_1044; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1112 = _out_wofireMux_T_1044; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1113 = _out_wofireMux_T_1044; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1114 = _out_wofireMux_T_1044; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1045 = ~_out_T_1885; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1047 = _out_wofireMux_T_262 & out_backSel_196; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_1048 = _out_wofireMux_T_1047 & _out_T_1631; // @[RegisterRouter.scala:87:24]
assign out_woready_1_120 = _out_wofireMux_T_1048; // @[RegisterRouter.scala:87:24]
assign out_woready_1_121 = _out_wofireMux_T_1048; // @[RegisterRouter.scala:87:24]
assign out_woready_1_122 = _out_wofireMux_T_1048; // @[RegisterRouter.scala:87:24]
assign out_woready_1_123 = _out_wofireMux_T_1048; // @[RegisterRouter.scala:87:24]
assign out_woready_1_124 = _out_wofireMux_T_1048; // @[RegisterRouter.scala:87:24]
assign out_woready_1_125 = _out_wofireMux_T_1048; // @[RegisterRouter.scala:87:24]
assign out_woready_1_126 = _out_wofireMux_T_1048; // @[RegisterRouter.scala:87:24]
assign out_woready_1_127 = _out_wofireMux_T_1048; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1049 = ~_out_T_1631; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1051 = _out_wofireMux_T_262 & out_backSel_197; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_1052 = _out_wofireMux_T_1051 & _out_T_1695; // @[RegisterRouter.scala:87:24]
assign out_woready_1_370 = _out_wofireMux_T_1052; // @[RegisterRouter.scala:87:24]
assign out_woready_1_371 = _out_wofireMux_T_1052; // @[RegisterRouter.scala:87:24]
assign out_woready_1_372 = _out_wofireMux_T_1052; // @[RegisterRouter.scala:87:24]
assign out_woready_1_373 = _out_wofireMux_T_1052; // @[RegisterRouter.scala:87:24]
assign out_woready_1_374 = _out_wofireMux_T_1052; // @[RegisterRouter.scala:87:24]
assign out_woready_1_375 = _out_wofireMux_T_1052; // @[RegisterRouter.scala:87:24]
assign out_woready_1_376 = _out_wofireMux_T_1052; // @[RegisterRouter.scala:87:24]
assign out_woready_1_377 = _out_wofireMux_T_1052; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1053 = ~_out_T_1695; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1055 = _out_wofireMux_T_262 & out_backSel_198; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_1056 = _out_wofireMux_T_1055 & _out_T_1789; // @[RegisterRouter.scala:87:24]
assign out_woready_1_723 = _out_wofireMux_T_1056; // @[RegisterRouter.scala:87:24]
assign out_woready_1_724 = _out_wofireMux_T_1056; // @[RegisterRouter.scala:87:24]
assign out_woready_1_725 = _out_wofireMux_T_1056; // @[RegisterRouter.scala:87:24]
assign out_woready_1_726 = _out_wofireMux_T_1056; // @[RegisterRouter.scala:87:24]
assign out_woready_1_727 = _out_wofireMux_T_1056; // @[RegisterRouter.scala:87:24]
assign out_woready_1_728 = _out_wofireMux_T_1056; // @[RegisterRouter.scala:87:24]
assign out_woready_1_729 = _out_wofireMux_T_1056; // @[RegisterRouter.scala:87:24]
assign out_woready_1_730 = _out_wofireMux_T_1056; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1057 = ~_out_T_1789; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1059 = _out_wofireMux_T_262 & out_backSel_199; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_1060 = _out_wofireMux_T_1059 & _out_T_1825; // @[RegisterRouter.scala:87:24]
assign out_woready_1_867 = _out_wofireMux_T_1060; // @[RegisterRouter.scala:87:24]
assign out_woready_1_868 = _out_wofireMux_T_1060; // @[RegisterRouter.scala:87:24]
assign out_woready_1_869 = _out_wofireMux_T_1060; // @[RegisterRouter.scala:87:24]
assign out_woready_1_870 = _out_wofireMux_T_1060; // @[RegisterRouter.scala:87:24]
assign out_woready_1_871 = _out_wofireMux_T_1060; // @[RegisterRouter.scala:87:24]
assign out_woready_1_872 = _out_wofireMux_T_1060; // @[RegisterRouter.scala:87:24]
assign out_woready_1_873 = _out_wofireMux_T_1060; // @[RegisterRouter.scala:87:24]
assign out_woready_1_874 = _out_wofireMux_T_1060; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1061 = ~_out_T_1825; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1063 = _out_wofireMux_T_262 & out_backSel_200; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_1064 = _out_wofireMux_T_1063 & _out_T_1897; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1155 = _out_wofireMux_T_1064; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1156 = _out_wofireMux_T_1064; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1157 = _out_wofireMux_T_1064; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1158 = _out_wofireMux_T_1064; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1159 = _out_wofireMux_T_1064; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1160 = _out_wofireMux_T_1064; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1161 = _out_wofireMux_T_1064; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1162 = _out_wofireMux_T_1064; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1065 = ~_out_T_1897; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1067 = _out_wofireMux_T_262 & out_backSel_201; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_1068 = _out_wofireMux_T_1067 & _out_T_1675; // @[RegisterRouter.scala:87:24]
assign out_woready_1_296 = _out_wofireMux_T_1068; // @[RegisterRouter.scala:87:24]
assign out_woready_1_297 = _out_wofireMux_T_1068; // @[RegisterRouter.scala:87:24]
assign out_woready_1_298 = _out_wofireMux_T_1068; // @[RegisterRouter.scala:87:24]
assign out_woready_1_299 = _out_wofireMux_T_1068; // @[RegisterRouter.scala:87:24]
assign out_woready_1_300 = _out_wofireMux_T_1068; // @[RegisterRouter.scala:87:24]
assign out_woready_1_301 = _out_wofireMux_T_1068; // @[RegisterRouter.scala:87:24]
assign out_woready_1_302 = _out_wofireMux_T_1068; // @[RegisterRouter.scala:87:24]
assign out_woready_1_303 = _out_wofireMux_T_1068; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1069 = ~_out_T_1675; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1071 = _out_wofireMux_T_262 & out_backSel_202; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_1072 = _out_wofireMux_T_1071 & _out_T_1615; // @[RegisterRouter.scala:87:24]
assign out_woready_1_56 = _out_wofireMux_T_1072; // @[RegisterRouter.scala:87:24]
assign out_woready_1_57 = _out_wofireMux_T_1072; // @[RegisterRouter.scala:87:24]
assign out_woready_1_58 = _out_wofireMux_T_1072; // @[RegisterRouter.scala:87:24]
assign out_woready_1_59 = _out_wofireMux_T_1072; // @[RegisterRouter.scala:87:24]
assign out_woready_1_60 = _out_wofireMux_T_1072; // @[RegisterRouter.scala:87:24]
assign out_woready_1_61 = _out_wofireMux_T_1072; // @[RegisterRouter.scala:87:24]
assign out_woready_1_62 = _out_wofireMux_T_1072; // @[RegisterRouter.scala:87:24]
assign out_woready_1_63 = _out_wofireMux_T_1072; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1073 = ~_out_T_1615; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1075 = _out_wofireMux_T_262 & out_backSel_203; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_1076 = _out_wofireMux_T_1075 & _out_T_1837; // @[RegisterRouter.scala:87:24]
assign out_woready_1_915 = _out_wofireMux_T_1076; // @[RegisterRouter.scala:87:24]
assign out_woready_1_916 = _out_wofireMux_T_1076; // @[RegisterRouter.scala:87:24]
assign out_woready_1_917 = _out_wofireMux_T_1076; // @[RegisterRouter.scala:87:24]
assign out_woready_1_918 = _out_wofireMux_T_1076; // @[RegisterRouter.scala:87:24]
assign out_woready_1_919 = _out_wofireMux_T_1076; // @[RegisterRouter.scala:87:24]
assign out_woready_1_920 = _out_wofireMux_T_1076; // @[RegisterRouter.scala:87:24]
assign out_woready_1_921 = _out_wofireMux_T_1076; // @[RegisterRouter.scala:87:24]
assign out_woready_1_922 = _out_wofireMux_T_1076; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1077 = ~_out_T_1837; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1079 = _out_wofireMux_T_262 & out_backSel_204; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_1080 = _out_wofireMux_T_1079 & _out_T_1755; // @[RegisterRouter.scala:87:24]
assign out_woready_1_593 = _out_wofireMux_T_1080; // @[RegisterRouter.scala:87:24]
assign out_woready_1_594 = _out_wofireMux_T_1080; // @[RegisterRouter.scala:87:24]
assign out_woready_1_595 = _out_wofireMux_T_1080; // @[RegisterRouter.scala:87:24]
assign out_woready_1_596 = _out_wofireMux_T_1080; // @[RegisterRouter.scala:87:24]
assign out_woready_1_597 = _out_wofireMux_T_1080; // @[RegisterRouter.scala:87:24]
assign out_woready_1_598 = _out_wofireMux_T_1080; // @[RegisterRouter.scala:87:24]
assign out_woready_1_599 = _out_wofireMux_T_1080; // @[RegisterRouter.scala:87:24]
assign out_woready_1_600 = _out_wofireMux_T_1080; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1081 = ~_out_T_1755; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1083 = _out_wofireMux_T_262 & out_backSel_205; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_1084 = _out_wofireMux_T_1083 & _out_T_1727; // @[RegisterRouter.scala:87:24]
assign out_woready_1_487 = _out_wofireMux_T_1084; // @[RegisterRouter.scala:87:24]
assign out_woready_1_488 = _out_wofireMux_T_1084; // @[RegisterRouter.scala:87:24]
assign out_woready_1_489 = _out_wofireMux_T_1084; // @[RegisterRouter.scala:87:24]
assign out_woready_1_490 = _out_wofireMux_T_1084; // @[RegisterRouter.scala:87:24]
assign out_woready_1_491 = _out_wofireMux_T_1084; // @[RegisterRouter.scala:87:24]
assign out_woready_1_492 = _out_wofireMux_T_1084; // @[RegisterRouter.scala:87:24]
assign out_woready_1_493 = _out_wofireMux_T_1084; // @[RegisterRouter.scala:87:24]
assign out_woready_1_494 = _out_wofireMux_T_1084; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1085 = ~_out_T_1727; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1087 = _out_wofireMux_T_262 & out_backSel_206; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_1088 = _out_wofireMux_T_1087 & _out_T_1669; // @[RegisterRouter.scala:87:24]
assign out_woready_1_272 = _out_wofireMux_T_1088; // @[RegisterRouter.scala:87:24]
assign out_woready_1_273 = _out_wofireMux_T_1088; // @[RegisterRouter.scala:87:24]
assign out_woready_1_274 = _out_wofireMux_T_1088; // @[RegisterRouter.scala:87:24]
assign out_woready_1_275 = _out_wofireMux_T_1088; // @[RegisterRouter.scala:87:24]
assign out_woready_1_276 = _out_wofireMux_T_1088; // @[RegisterRouter.scala:87:24]
assign out_woready_1_277 = _out_wofireMux_T_1088; // @[RegisterRouter.scala:87:24]
assign out_woready_1_278 = _out_wofireMux_T_1088; // @[RegisterRouter.scala:87:24]
assign out_woready_1_279 = _out_wofireMux_T_1088; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1089 = ~_out_T_1669; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1091 = _out_wofireMux_T_262 & out_backSel_207; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_1092 = _out_wofireMux_T_1091 & _out_T_1859; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1003 = _out_wofireMux_T_1092; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1004 = _out_wofireMux_T_1092; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1005 = _out_wofireMux_T_1092; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1006 = _out_wofireMux_T_1092; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1007 = _out_wofireMux_T_1092; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1008 = _out_wofireMux_T_1092; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1009 = _out_wofireMux_T_1092; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1010 = _out_wofireMux_T_1092; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1093 = ~_out_T_1859; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1095 = _out_wofireMux_T_262 & out_backSel_208; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_1096 = _out_wofireMux_T_1095 & _out_T_1779; // @[RegisterRouter.scala:87:24]
assign out_woready_1_689 = _out_wofireMux_T_1096; // @[RegisterRouter.scala:87:24]
assign out_woready_1_690 = _out_wofireMux_T_1096; // @[RegisterRouter.scala:87:24]
assign out_woready_1_691 = _out_wofireMux_T_1096; // @[RegisterRouter.scala:87:24]
assign out_woready_1_692 = _out_wofireMux_T_1096; // @[RegisterRouter.scala:87:24]
assign out_woready_1_693 = _out_wofireMux_T_1096; // @[RegisterRouter.scala:87:24]
assign out_woready_1_694 = _out_wofireMux_T_1096; // @[RegisterRouter.scala:87:24]
assign out_woready_1_695 = _out_wofireMux_T_1096; // @[RegisterRouter.scala:87:24]
assign out_woready_1_696 = _out_wofireMux_T_1096; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1097 = ~_out_T_1779; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1099 = _out_wofireMux_T_262 & out_backSel_209; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_1100 = _out_wofireMux_T_1099 & _out_T_1813; // @[RegisterRouter.scala:87:24]
assign out_woready_1_819 = _out_wofireMux_T_1100; // @[RegisterRouter.scala:87:24]
assign out_woready_1_820 = _out_wofireMux_T_1100; // @[RegisterRouter.scala:87:24]
assign out_woready_1_821 = _out_wofireMux_T_1100; // @[RegisterRouter.scala:87:24]
assign out_woready_1_822 = _out_wofireMux_T_1100; // @[RegisterRouter.scala:87:24]
assign out_woready_1_823 = _out_wofireMux_T_1100; // @[RegisterRouter.scala:87:24]
assign out_woready_1_824 = _out_wofireMux_T_1100; // @[RegisterRouter.scala:87:24]
assign out_woready_1_825 = _out_wofireMux_T_1100; // @[RegisterRouter.scala:87:24]
assign out_woready_1_826 = _out_wofireMux_T_1100; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1101 = ~_out_T_1813; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1103 = _out_wofireMux_T_262 & out_backSel_210; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_1104 = _out_wofireMux_T_1103 & _out_T_1879; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1083 = _out_wofireMux_T_1104; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1084 = _out_wofireMux_T_1104; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1085 = _out_wofireMux_T_1104; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1086 = _out_wofireMux_T_1104; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1087 = _out_wofireMux_T_1104; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1088 = _out_wofireMux_T_1104; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1089 = _out_wofireMux_T_1104; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1090 = _out_wofireMux_T_1104; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1105 = ~_out_T_1879; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1107 = _out_wofireMux_T_262 & out_backSel_211; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_1108 = _out_wofireMux_T_1107 & _out_T_1653; // @[RegisterRouter.scala:87:24]
assign out_woready_1_208 = _out_wofireMux_T_1108; // @[RegisterRouter.scala:87:24]
assign out_woready_1_209 = _out_wofireMux_T_1108; // @[RegisterRouter.scala:87:24]
assign out_woready_1_210 = _out_wofireMux_T_1108; // @[RegisterRouter.scala:87:24]
assign out_woready_1_211 = _out_wofireMux_T_1108; // @[RegisterRouter.scala:87:24]
assign out_woready_1_212 = _out_wofireMux_T_1108; // @[RegisterRouter.scala:87:24]
assign out_woready_1_213 = _out_wofireMux_T_1108; // @[RegisterRouter.scala:87:24]
assign out_woready_1_214 = _out_wofireMux_T_1108; // @[RegisterRouter.scala:87:24]
assign out_woready_1_215 = _out_wofireMux_T_1108; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1109 = ~_out_T_1653; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1111 = _out_wofireMux_T_262 & out_backSel_212; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_1112 = _out_wofireMux_T_1111 & _out_T_1711; // @[RegisterRouter.scala:87:24]
assign out_woready_1_434 = _out_wofireMux_T_1112; // @[RegisterRouter.scala:87:24]
assign out_woready_1_435 = _out_wofireMux_T_1112; // @[RegisterRouter.scala:87:24]
assign out_woready_1_436 = _out_wofireMux_T_1112; // @[RegisterRouter.scala:87:24]
assign out_woready_1_437 = _out_wofireMux_T_1112; // @[RegisterRouter.scala:87:24]
assign out_woready_1_438 = _out_wofireMux_T_1112; // @[RegisterRouter.scala:87:24]
assign out_woready_1_439 = _out_wofireMux_T_1112; // @[RegisterRouter.scala:87:24]
assign out_woready_1_440 = _out_wofireMux_T_1112; // @[RegisterRouter.scala:87:24]
assign out_woready_1_441 = _out_wofireMux_T_1112; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1113 = ~_out_T_1711; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1115 = _out_wofireMux_T_262 & out_backSel_213; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_1116 = _out_wofireMux_T_1115 & _out_T_1785; // @[RegisterRouter.scala:87:24]
assign out_woready_1_707 = _out_wofireMux_T_1116; // @[RegisterRouter.scala:87:24]
assign out_woready_1_708 = _out_wofireMux_T_1116; // @[RegisterRouter.scala:87:24]
assign out_woready_1_709 = _out_wofireMux_T_1116; // @[RegisterRouter.scala:87:24]
assign out_woready_1_710 = _out_wofireMux_T_1116; // @[RegisterRouter.scala:87:24]
assign out_woready_1_711 = _out_wofireMux_T_1116; // @[RegisterRouter.scala:87:24]
assign out_woready_1_712 = _out_wofireMux_T_1116; // @[RegisterRouter.scala:87:24]
assign out_woready_1_713 = _out_wofireMux_T_1116; // @[RegisterRouter.scala:87:24]
assign out_woready_1_714 = _out_wofireMux_T_1116; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1117 = ~_out_T_1785; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1119 = _out_wofireMux_T_262 & out_backSel_214; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_1120 = _out_wofireMux_T_1119 & _out_T_1861; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1011 = _out_wofireMux_T_1120; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1012 = _out_wofireMux_T_1120; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1013 = _out_wofireMux_T_1120; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1014 = _out_wofireMux_T_1120; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1015 = _out_wofireMux_T_1120; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1016 = _out_wofireMux_T_1120; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1017 = _out_wofireMux_T_1120; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1018 = _out_wofireMux_T_1120; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1121 = ~_out_T_1861; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1123 = _out_wofireMux_T_262 & out_backSel_215; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_1124 = _out_wofireMux_T_1123 & _out_T_1901; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1171 = _out_wofireMux_T_1124; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1172 = _out_wofireMux_T_1124; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1173 = _out_wofireMux_T_1124; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1174 = _out_wofireMux_T_1124; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1175 = _out_wofireMux_T_1124; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1176 = _out_wofireMux_T_1124; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1177 = _out_wofireMux_T_1124; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1178 = _out_wofireMux_T_1124; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1125 = ~_out_T_1901; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1127 = _out_wofireMux_T_262 & out_backSel_216; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_1128 = _out_wofireMux_T_1127 & _out_T_1643; // @[RegisterRouter.scala:87:24]
assign out_woready_1_168 = _out_wofireMux_T_1128; // @[RegisterRouter.scala:87:24]
assign out_woready_1_169 = _out_wofireMux_T_1128; // @[RegisterRouter.scala:87:24]
assign out_woready_1_170 = _out_wofireMux_T_1128; // @[RegisterRouter.scala:87:24]
assign out_woready_1_171 = _out_wofireMux_T_1128; // @[RegisterRouter.scala:87:24]
assign out_woready_1_172 = _out_wofireMux_T_1128; // @[RegisterRouter.scala:87:24]
assign out_woready_1_173 = _out_wofireMux_T_1128; // @[RegisterRouter.scala:87:24]
assign out_woready_1_174 = _out_wofireMux_T_1128; // @[RegisterRouter.scala:87:24]
assign out_woready_1_175 = _out_wofireMux_T_1128; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1129 = ~_out_T_1643; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1131 = _out_wofireMux_T_262 & out_backSel_217; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_1132 = _out_wofireMux_T_1131 & _out_T_1611; // @[RegisterRouter.scala:87:24]
assign out_woready_1_40 = _out_wofireMux_T_1132; // @[RegisterRouter.scala:87:24]
assign out_woready_1_41 = _out_wofireMux_T_1132; // @[RegisterRouter.scala:87:24]
assign out_woready_1_42 = _out_wofireMux_T_1132; // @[RegisterRouter.scala:87:24]
assign out_woready_1_43 = _out_wofireMux_T_1132; // @[RegisterRouter.scala:87:24]
assign out_woready_1_44 = _out_wofireMux_T_1132; // @[RegisterRouter.scala:87:24]
assign out_woready_1_45 = _out_wofireMux_T_1132; // @[RegisterRouter.scala:87:24]
assign out_woready_1_46 = _out_wofireMux_T_1132; // @[RegisterRouter.scala:87:24]
assign out_woready_1_47 = _out_wofireMux_T_1132; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1133 = ~_out_T_1611; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1135 = _out_wofireMux_T_262 & out_backSel_218; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_1136 = _out_wofireMux_T_1135 & _out_T_1839; // @[RegisterRouter.scala:87:24]
assign out_woready_1_923 = _out_wofireMux_T_1136; // @[RegisterRouter.scala:87:24]
assign out_woready_1_924 = _out_wofireMux_T_1136; // @[RegisterRouter.scala:87:24]
assign out_woready_1_925 = _out_wofireMux_T_1136; // @[RegisterRouter.scala:87:24]
assign out_woready_1_926 = _out_wofireMux_T_1136; // @[RegisterRouter.scala:87:24]
assign out_woready_1_927 = _out_wofireMux_T_1136; // @[RegisterRouter.scala:87:24]
assign out_woready_1_928 = _out_wofireMux_T_1136; // @[RegisterRouter.scala:87:24]
assign out_woready_1_929 = _out_wofireMux_T_1136; // @[RegisterRouter.scala:87:24]
assign out_woready_1_930 = _out_wofireMux_T_1136; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1137 = ~_out_T_1839; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1139 = _out_wofireMux_T_262 & out_backSel_219; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_1140 = _out_wofireMux_T_1139 & _out_T_1773; // @[RegisterRouter.scala:87:24]
assign out_woready_1_665 = _out_wofireMux_T_1140; // @[RegisterRouter.scala:87:24]
assign out_woready_1_666 = _out_wofireMux_T_1140; // @[RegisterRouter.scala:87:24]
assign out_woready_1_667 = _out_wofireMux_T_1140; // @[RegisterRouter.scala:87:24]
assign out_woready_1_668 = _out_wofireMux_T_1140; // @[RegisterRouter.scala:87:24]
assign out_woready_1_669 = _out_wofireMux_T_1140; // @[RegisterRouter.scala:87:24]
assign out_woready_1_670 = _out_wofireMux_T_1140; // @[RegisterRouter.scala:87:24]
assign out_woready_1_671 = _out_wofireMux_T_1140; // @[RegisterRouter.scala:87:24]
assign out_woready_1_672 = _out_wofireMux_T_1140; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1141 = ~_out_T_1773; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1143 = _out_wofireMux_T_262 & out_backSel_220; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_1144 = _out_wofireMux_T_1143 & _out_T_1677; // @[RegisterRouter.scala:87:24]
assign out_woready_1_304 = _out_wofireMux_T_1144; // @[RegisterRouter.scala:87:24]
assign out_woready_1_305 = _out_wofireMux_T_1144; // @[RegisterRouter.scala:87:24]
assign out_woready_1_306 = _out_wofireMux_T_1144; // @[RegisterRouter.scala:87:24]
assign out_woready_1_307 = _out_wofireMux_T_1144; // @[RegisterRouter.scala:87:24]
assign out_woready_1_308 = _out_wofireMux_T_1144; // @[RegisterRouter.scala:87:24]
assign out_woready_1_309 = _out_wofireMux_T_1144; // @[RegisterRouter.scala:87:24]
assign out_woready_1_310 = _out_wofireMux_T_1144; // @[RegisterRouter.scala:87:24]
assign out_woready_1_311 = _out_wofireMux_T_1144; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1145 = ~_out_T_1677; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1147 = _out_wofireMux_T_262 & out_backSel_221; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_1148 = _out_wofireMux_T_1147 & _out_T_1659; // @[RegisterRouter.scala:87:24]
assign out_woready_1_232 = _out_wofireMux_T_1148; // @[RegisterRouter.scala:87:24]
assign out_woready_1_233 = _out_wofireMux_T_1148; // @[RegisterRouter.scala:87:24]
assign out_woready_1_234 = _out_wofireMux_T_1148; // @[RegisterRouter.scala:87:24]
assign out_woready_1_235 = _out_wofireMux_T_1148; // @[RegisterRouter.scala:87:24]
assign out_woready_1_236 = _out_wofireMux_T_1148; // @[RegisterRouter.scala:87:24]
assign out_woready_1_237 = _out_wofireMux_T_1148; // @[RegisterRouter.scala:87:24]
assign out_woready_1_238 = _out_wofireMux_T_1148; // @[RegisterRouter.scala:87:24]
assign out_woready_1_239 = _out_wofireMux_T_1148; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1149 = ~_out_T_1659; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1151 = _out_wofireMux_T_262 & out_backSel_222; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_1152 = _out_wofireMux_T_1151 & _out_T_1903; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1179 = _out_wofireMux_T_1152; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1180 = _out_wofireMux_T_1152; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1181 = _out_wofireMux_T_1152; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1182 = _out_wofireMux_T_1152; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1183 = _out_wofireMux_T_1152; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1184 = _out_wofireMux_T_1152; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1185 = _out_wofireMux_T_1152; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1186 = _out_wofireMux_T_1152; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1153 = ~_out_T_1903; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1155 = _out_wofireMux_T_262 & out_backSel_223; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_1156 = _out_wofireMux_T_1155 & _out_T_1799; // @[RegisterRouter.scala:87:24]
assign out_woready_1_763 = _out_wofireMux_T_1156; // @[RegisterRouter.scala:87:24]
assign out_woready_1_764 = _out_wofireMux_T_1156; // @[RegisterRouter.scala:87:24]
assign out_woready_1_765 = _out_wofireMux_T_1156; // @[RegisterRouter.scala:87:24]
assign out_woready_1_766 = _out_wofireMux_T_1156; // @[RegisterRouter.scala:87:24]
assign out_woready_1_767 = _out_wofireMux_T_1156; // @[RegisterRouter.scala:87:24]
assign out_woready_1_768 = _out_wofireMux_T_1156; // @[RegisterRouter.scala:87:24]
assign out_woready_1_769 = _out_wofireMux_T_1156; // @[RegisterRouter.scala:87:24]
assign out_woready_1_770 = _out_wofireMux_T_1156; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1157 = ~_out_T_1799; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1159 = _out_wofireMux_T_262 & out_backSel_224; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_1160 = _out_wofireMux_T_1159 & _out_T_1697; // @[RegisterRouter.scala:87:24]
assign out_woready_1_378 = _out_wofireMux_T_1160; // @[RegisterRouter.scala:87:24]
assign out_woready_1_379 = _out_wofireMux_T_1160; // @[RegisterRouter.scala:87:24]
assign out_woready_1_380 = _out_wofireMux_T_1160; // @[RegisterRouter.scala:87:24]
assign out_woready_1_381 = _out_wofireMux_T_1160; // @[RegisterRouter.scala:87:24]
assign out_woready_1_382 = _out_wofireMux_T_1160; // @[RegisterRouter.scala:87:24]
assign out_woready_1_383 = _out_wofireMux_T_1160; // @[RegisterRouter.scala:87:24]
assign out_woready_1_384 = _out_wofireMux_T_1160; // @[RegisterRouter.scala:87:24]
assign out_woready_1_385 = _out_wofireMux_T_1160; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1161 = ~_out_T_1697; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1163 = _out_wofireMux_T_262 & out_backSel_225; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_1164 = _out_wofireMux_T_1163 & _out_T_1707; // @[RegisterRouter.scala:87:24]
assign out_woready_1_418 = _out_wofireMux_T_1164; // @[RegisterRouter.scala:87:24]
assign out_woready_1_419 = _out_wofireMux_T_1164; // @[RegisterRouter.scala:87:24]
assign out_woready_1_420 = _out_wofireMux_T_1164; // @[RegisterRouter.scala:87:24]
assign out_woready_1_421 = _out_wofireMux_T_1164; // @[RegisterRouter.scala:87:24]
assign out_woready_1_422 = _out_wofireMux_T_1164; // @[RegisterRouter.scala:87:24]
assign out_woready_1_423 = _out_wofireMux_T_1164; // @[RegisterRouter.scala:87:24]
assign out_woready_1_424 = _out_wofireMux_T_1164; // @[RegisterRouter.scala:87:24]
assign out_woready_1_425 = _out_wofireMux_T_1164; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1165 = ~_out_T_1707; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1167 = _out_wofireMux_T_262 & out_backSel_226; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_1168 = _out_wofireMux_T_1167 & _out_T_1803; // @[RegisterRouter.scala:87:24]
assign out_woready_1_779 = _out_wofireMux_T_1168; // @[RegisterRouter.scala:87:24]
assign out_woready_1_780 = _out_wofireMux_T_1168; // @[RegisterRouter.scala:87:24]
assign out_woready_1_781 = _out_wofireMux_T_1168; // @[RegisterRouter.scala:87:24]
assign out_woready_1_782 = _out_wofireMux_T_1168; // @[RegisterRouter.scala:87:24]
assign out_woready_1_783 = _out_wofireMux_T_1168; // @[RegisterRouter.scala:87:24]
assign out_woready_1_784 = _out_wofireMux_T_1168; // @[RegisterRouter.scala:87:24]
assign out_woready_1_785 = _out_wofireMux_T_1168; // @[RegisterRouter.scala:87:24]
assign out_woready_1_786 = _out_wofireMux_T_1168; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1169 = ~_out_T_1803; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1171 = _out_wofireMux_T_262 & out_backSel_227; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_1172 = _out_wofireMux_T_1171 & _out_T_1909; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1203 = _out_wofireMux_T_1172; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1204 = _out_wofireMux_T_1172; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1205 = _out_wofireMux_T_1172; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1206 = _out_wofireMux_T_1172; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1207 = _out_wofireMux_T_1172; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1208 = _out_wofireMux_T_1172; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1209 = _out_wofireMux_T_1172; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1210 = _out_wofireMux_T_1172; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1173 = ~_out_T_1909; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1175 = _out_wofireMux_T_262 & out_backSel_228; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_1176 = _out_wofireMux_T_1175 & _out_T_1639; // @[RegisterRouter.scala:87:24]
assign out_woready_1_152 = _out_wofireMux_T_1176; // @[RegisterRouter.scala:87:24]
assign out_woready_1_153 = _out_wofireMux_T_1176; // @[RegisterRouter.scala:87:24]
assign out_woready_1_154 = _out_wofireMux_T_1176; // @[RegisterRouter.scala:87:24]
assign out_woready_1_155 = _out_wofireMux_T_1176; // @[RegisterRouter.scala:87:24]
assign out_woready_1_156 = _out_wofireMux_T_1176; // @[RegisterRouter.scala:87:24]
assign out_woready_1_157 = _out_wofireMux_T_1176; // @[RegisterRouter.scala:87:24]
assign out_woready_1_158 = _out_wofireMux_T_1176; // @[RegisterRouter.scala:87:24]
assign out_woready_1_159 = _out_wofireMux_T_1176; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1177 = ~_out_T_1639; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1179 = _out_wofireMux_T_262 & out_backSel_229; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_1180 = _out_wofireMux_T_1179 & _out_T_1691; // @[RegisterRouter.scala:87:24]
assign out_woready_1_354 = _out_wofireMux_T_1180; // @[RegisterRouter.scala:87:24]
assign out_woready_1_355 = _out_wofireMux_T_1180; // @[RegisterRouter.scala:87:24]
assign out_woready_1_356 = _out_wofireMux_T_1180; // @[RegisterRouter.scala:87:24]
assign out_woready_1_357 = _out_wofireMux_T_1180; // @[RegisterRouter.scala:87:24]
assign out_woready_1_358 = _out_wofireMux_T_1180; // @[RegisterRouter.scala:87:24]
assign out_woready_1_359 = _out_wofireMux_T_1180; // @[RegisterRouter.scala:87:24]
assign out_woready_1_360 = _out_wofireMux_T_1180; // @[RegisterRouter.scala:87:24]
assign out_woready_1_361 = _out_wofireMux_T_1180; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1181 = ~_out_T_1691; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1183 = _out_wofireMux_T_262 & out_backSel_230; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_1184 = _out_wofireMux_T_1183 & _out_T_1775; // @[RegisterRouter.scala:87:24]
assign out_woready_1_673 = _out_wofireMux_T_1184; // @[RegisterRouter.scala:87:24]
assign out_woready_1_674 = _out_wofireMux_T_1184; // @[RegisterRouter.scala:87:24]
assign out_woready_1_675 = _out_wofireMux_T_1184; // @[RegisterRouter.scala:87:24]
assign out_woready_1_676 = _out_wofireMux_T_1184; // @[RegisterRouter.scala:87:24]
assign out_woready_1_677 = _out_wofireMux_T_1184; // @[RegisterRouter.scala:87:24]
assign out_woready_1_678 = _out_wofireMux_T_1184; // @[RegisterRouter.scala:87:24]
assign out_woready_1_679 = _out_wofireMux_T_1184; // @[RegisterRouter.scala:87:24]
assign out_woready_1_680 = _out_wofireMux_T_1184; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1185 = ~_out_T_1775; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1187 = _out_wofireMux_T_262 & out_backSel_231; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_1188 = _out_wofireMux_T_1187 & _out_T_1845; // @[RegisterRouter.scala:87:24]
assign out_woready_1_947 = _out_wofireMux_T_1188; // @[RegisterRouter.scala:87:24]
assign out_woready_1_948 = _out_wofireMux_T_1188; // @[RegisterRouter.scala:87:24]
assign out_woready_1_949 = _out_wofireMux_T_1188; // @[RegisterRouter.scala:87:24]
assign out_woready_1_950 = _out_wofireMux_T_1188; // @[RegisterRouter.scala:87:24]
assign out_woready_1_951 = _out_wofireMux_T_1188; // @[RegisterRouter.scala:87:24]
assign out_woready_1_952 = _out_wofireMux_T_1188; // @[RegisterRouter.scala:87:24]
assign out_woready_1_953 = _out_wofireMux_T_1188; // @[RegisterRouter.scala:87:24]
assign out_woready_1_954 = _out_wofireMux_T_1188; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1189 = ~_out_T_1845; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1191 = _out_wofireMux_T_262 & out_backSel_232; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_1192 = _out_wofireMux_T_1191 & _out_T_1905; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1187 = _out_wofireMux_T_1192; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1188 = _out_wofireMux_T_1192; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1189 = _out_wofireMux_T_1192; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1190 = _out_wofireMux_T_1192; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1191 = _out_wofireMux_T_1192; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1192 = _out_wofireMux_T_1192; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1193 = _out_wofireMux_T_1192; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1194 = _out_wofireMux_T_1192; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1193 = ~_out_T_1905; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1195 = _out_wofireMux_T_262 & out_backSel_233; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_1196 = _out_wofireMux_T_1195 & _out_T_1671; // @[RegisterRouter.scala:87:24]
assign out_woready_1_280 = _out_wofireMux_T_1196; // @[RegisterRouter.scala:87:24]
assign out_woready_1_281 = _out_wofireMux_T_1196; // @[RegisterRouter.scala:87:24]
assign out_woready_1_282 = _out_wofireMux_T_1196; // @[RegisterRouter.scala:87:24]
assign out_woready_1_283 = _out_wofireMux_T_1196; // @[RegisterRouter.scala:87:24]
assign out_woready_1_284 = _out_wofireMux_T_1196; // @[RegisterRouter.scala:87:24]
assign out_woready_1_285 = _out_wofireMux_T_1196; // @[RegisterRouter.scala:87:24]
assign out_woready_1_286 = _out_wofireMux_T_1196; // @[RegisterRouter.scala:87:24]
assign out_woready_1_287 = _out_wofireMux_T_1196; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1197 = ~_out_T_1671; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1199 = _out_wofireMux_T_262 & out_backSel_234; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_1200 = _out_wofireMux_T_1199 & _out_T_1605; // @[RegisterRouter.scala:87:24]
assign out_woready_1_16 = _out_wofireMux_T_1200; // @[RegisterRouter.scala:87:24]
assign out_woready_1_17 = _out_wofireMux_T_1200; // @[RegisterRouter.scala:87:24]
assign out_woready_1_18 = _out_wofireMux_T_1200; // @[RegisterRouter.scala:87:24]
assign out_woready_1_19 = _out_wofireMux_T_1200; // @[RegisterRouter.scala:87:24]
assign out_woready_1_20 = _out_wofireMux_T_1200; // @[RegisterRouter.scala:87:24]
assign out_woready_1_21 = _out_wofireMux_T_1200; // @[RegisterRouter.scala:87:24]
assign out_woready_1_22 = _out_wofireMux_T_1200; // @[RegisterRouter.scala:87:24]
assign out_woready_1_23 = _out_wofireMux_T_1200; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1201 = ~_out_T_1605; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1203 = _out_wofireMux_T_262 & out_backSel_235; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_1204 = _out_wofireMux_T_1203 & _out_T_1863; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1019 = _out_wofireMux_T_1204; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1020 = _out_wofireMux_T_1204; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1021 = _out_wofireMux_T_1204; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1022 = _out_wofireMux_T_1204; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1023 = _out_wofireMux_T_1204; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1024 = _out_wofireMux_T_1204; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1025 = _out_wofireMux_T_1204; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1026 = _out_wofireMux_T_1204; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1205 = ~_out_T_1863; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1207 = _out_wofireMux_T_262 & out_backSel_236; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_1208 = _out_wofireMux_T_1207 & _out_T_1761; // @[RegisterRouter.scala:87:24]
assign out_woready_1_617 = _out_wofireMux_T_1208; // @[RegisterRouter.scala:87:24]
assign out_woready_1_618 = _out_wofireMux_T_1208; // @[RegisterRouter.scala:87:24]
assign out_woready_1_619 = _out_wofireMux_T_1208; // @[RegisterRouter.scala:87:24]
assign out_woready_1_620 = _out_wofireMux_T_1208; // @[RegisterRouter.scala:87:24]
assign out_woready_1_621 = _out_wofireMux_T_1208; // @[RegisterRouter.scala:87:24]
assign out_woready_1_622 = _out_wofireMux_T_1208; // @[RegisterRouter.scala:87:24]
assign out_woready_1_623 = _out_wofireMux_T_1208; // @[RegisterRouter.scala:87:24]
assign out_woready_1_624 = _out_wofireMux_T_1208; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1209 = ~_out_T_1761; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1211 = _out_wofireMux_T_262 & out_backSel_237; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_1212 = _out_wofireMux_T_1211 & _out_T_1731; // @[RegisterRouter.scala:87:24]
assign out_woready_1_503 = _out_wofireMux_T_1212; // @[RegisterRouter.scala:87:24]
assign out_woready_1_504 = _out_wofireMux_T_1212; // @[RegisterRouter.scala:87:24]
assign out_woready_1_505 = _out_wofireMux_T_1212; // @[RegisterRouter.scala:87:24]
assign out_woready_1_506 = _out_wofireMux_T_1212; // @[RegisterRouter.scala:87:24]
assign out_woready_1_507 = _out_wofireMux_T_1212; // @[RegisterRouter.scala:87:24]
assign out_woready_1_508 = _out_wofireMux_T_1212; // @[RegisterRouter.scala:87:24]
assign out_woready_1_509 = _out_wofireMux_T_1212; // @[RegisterRouter.scala:87:24]
assign out_woready_1_510 = _out_wofireMux_T_1212; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1213 = ~_out_T_1731; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1215 = _out_wofireMux_T_262 & out_backSel_238; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_1216 = _out_wofireMux_T_1215 & _out_T_1651; // @[RegisterRouter.scala:87:24]
assign out_woready_1_200 = _out_wofireMux_T_1216; // @[RegisterRouter.scala:87:24]
assign out_woready_1_201 = _out_wofireMux_T_1216; // @[RegisterRouter.scala:87:24]
assign out_woready_1_202 = _out_wofireMux_T_1216; // @[RegisterRouter.scala:87:24]
assign out_woready_1_203 = _out_wofireMux_T_1216; // @[RegisterRouter.scala:87:24]
assign out_woready_1_204 = _out_wofireMux_T_1216; // @[RegisterRouter.scala:87:24]
assign out_woready_1_205 = _out_wofireMux_T_1216; // @[RegisterRouter.scala:87:24]
assign out_woready_1_206 = _out_wofireMux_T_1216; // @[RegisterRouter.scala:87:24]
assign out_woready_1_207 = _out_wofireMux_T_1216; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1217 = ~_out_T_1651; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1219 = _out_wofireMux_T_262 & out_backSel_239; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_1220 = _out_wofireMux_T_1219 & _out_T_1887; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1115 = _out_wofireMux_T_1220; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1116 = _out_wofireMux_T_1220; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1117 = _out_wofireMux_T_1220; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1118 = _out_wofireMux_T_1220; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1119 = _out_wofireMux_T_1220; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1120 = _out_wofireMux_T_1220; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1121 = _out_wofireMux_T_1220; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1122 = _out_wofireMux_T_1220; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1221 = ~_out_T_1887; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1223 = _out_wofireMux_T_262 & out_backSel_240; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_1224 = _out_wofireMux_T_1223 & _out_T_1793; // @[RegisterRouter.scala:87:24]
assign out_woready_1_739 = _out_wofireMux_T_1224; // @[RegisterRouter.scala:87:24]
assign out_woready_1_740 = _out_wofireMux_T_1224; // @[RegisterRouter.scala:87:24]
assign out_woready_1_741 = _out_wofireMux_T_1224; // @[RegisterRouter.scala:87:24]
assign out_woready_1_742 = _out_wofireMux_T_1224; // @[RegisterRouter.scala:87:24]
assign out_woready_1_743 = _out_wofireMux_T_1224; // @[RegisterRouter.scala:87:24]
assign out_woready_1_744 = _out_wofireMux_T_1224; // @[RegisterRouter.scala:87:24]
assign out_woready_1_745 = _out_wofireMux_T_1224; // @[RegisterRouter.scala:87:24]
assign out_woready_1_746 = _out_wofireMux_T_1224; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1225 = ~_out_T_1793; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1227 = _out_wofireMux_T_262 & out_backSel_241; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_1228 = _out_wofireMux_T_1227 & _out_T_1805; // @[RegisterRouter.scala:87:24]
assign out_woready_1_787 = _out_wofireMux_T_1228; // @[RegisterRouter.scala:87:24]
assign out_woready_1_788 = _out_wofireMux_T_1228; // @[RegisterRouter.scala:87:24]
assign out_woready_1_789 = _out_wofireMux_T_1228; // @[RegisterRouter.scala:87:24]
assign out_woready_1_790 = _out_wofireMux_T_1228; // @[RegisterRouter.scala:87:24]
assign out_woready_1_791 = _out_wofireMux_T_1228; // @[RegisterRouter.scala:87:24]
assign out_woready_1_792 = _out_wofireMux_T_1228; // @[RegisterRouter.scala:87:24]
assign out_woready_1_793 = _out_wofireMux_T_1228; // @[RegisterRouter.scala:87:24]
assign out_woready_1_794 = _out_wofireMux_T_1228; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1229 = ~_out_T_1805; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1231 = _out_wofireMux_T_262 & out_backSel_242; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_1232 = _out_wofireMux_T_1231 & _out_T_1889; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1123 = _out_wofireMux_T_1232; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1124 = _out_wofireMux_T_1232; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1125 = _out_wofireMux_T_1232; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1126 = _out_wofireMux_T_1232; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1127 = _out_wofireMux_T_1232; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1128 = _out_wofireMux_T_1232; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1129 = _out_wofireMux_T_1232; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1130 = _out_wofireMux_T_1232; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1233 = ~_out_T_1889; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1235 = _out_wofireMux_T_262 & out_backSel_243; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_1236 = _out_wofireMux_T_1235 & _out_T_1665; // @[RegisterRouter.scala:87:24]
assign out_woready_1_256 = _out_wofireMux_T_1236; // @[RegisterRouter.scala:87:24]
assign out_woready_1_257 = _out_wofireMux_T_1236; // @[RegisterRouter.scala:87:24]
assign out_woready_1_258 = _out_wofireMux_T_1236; // @[RegisterRouter.scala:87:24]
assign out_woready_1_259 = _out_wofireMux_T_1236; // @[RegisterRouter.scala:87:24]
assign out_woready_1_260 = _out_wofireMux_T_1236; // @[RegisterRouter.scala:87:24]
assign out_woready_1_261 = _out_wofireMux_T_1236; // @[RegisterRouter.scala:87:24]
assign out_woready_1_262 = _out_wofireMux_T_1236; // @[RegisterRouter.scala:87:24]
assign out_woready_1_263 = _out_wofireMux_T_1236; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1237 = ~_out_T_1665; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1239 = _out_wofireMux_T_262 & out_backSel_244; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_1240 = _out_wofireMux_T_1239 & _out_T_1735; // @[RegisterRouter.scala:87:24]
assign out_woready_1_519 = _out_wofireMux_T_1240; // @[RegisterRouter.scala:87:24]
assign out_woready_1_520 = _out_wofireMux_T_1240; // @[RegisterRouter.scala:87:24]
assign out_woready_1_521 = _out_wofireMux_T_1240; // @[RegisterRouter.scala:87:24]
assign out_woready_1_522 = _out_wofireMux_T_1240; // @[RegisterRouter.scala:87:24]
assign out_woready_1_523 = _out_wofireMux_T_1240; // @[RegisterRouter.scala:87:24]
assign out_woready_1_524 = _out_wofireMux_T_1240; // @[RegisterRouter.scala:87:24]
assign out_woready_1_525 = _out_wofireMux_T_1240; // @[RegisterRouter.scala:87:24]
assign out_woready_1_526 = _out_wofireMux_T_1240; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1241 = ~_out_T_1735; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1243 = _out_wofireMux_T_262 & out_backSel_245; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_1244 = _out_wofireMux_T_1243 & _out_T_1777; // @[RegisterRouter.scala:87:24]
assign out_woready_1_681 = _out_wofireMux_T_1244; // @[RegisterRouter.scala:87:24]
assign out_woready_1_682 = _out_wofireMux_T_1244; // @[RegisterRouter.scala:87:24]
assign out_woready_1_683 = _out_wofireMux_T_1244; // @[RegisterRouter.scala:87:24]
assign out_woready_1_684 = _out_wofireMux_T_1244; // @[RegisterRouter.scala:87:24]
assign out_woready_1_685 = _out_wofireMux_T_1244; // @[RegisterRouter.scala:87:24]
assign out_woready_1_686 = _out_wofireMux_T_1244; // @[RegisterRouter.scala:87:24]
assign out_woready_1_687 = _out_wofireMux_T_1244; // @[RegisterRouter.scala:87:24]
assign out_woready_1_688 = _out_wofireMux_T_1244; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1245 = ~_out_T_1777; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1247 = _out_wofireMux_T_262 & out_backSel_246; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_1248 = _out_wofireMux_T_1247 & _out_T_1865; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1027 = _out_wofireMux_T_1248; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1028 = _out_wofireMux_T_1248; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1029 = _out_wofireMux_T_1248; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1030 = _out_wofireMux_T_1248; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1031 = _out_wofireMux_T_1248; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1032 = _out_wofireMux_T_1248; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1033 = _out_wofireMux_T_1248; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1034 = _out_wofireMux_T_1248; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1249 = ~_out_T_1865; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1251 = _out_wofireMux_T_262 & out_backSel_247; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_1252 = _out_wofireMux_T_1251 & _out_T_1613; // @[RegisterRouter.scala:87:24]
assign out_woready_1_48 = _out_wofireMux_T_1252; // @[RegisterRouter.scala:87:24]
assign out_woready_1_49 = _out_wofireMux_T_1252; // @[RegisterRouter.scala:87:24]
assign out_woready_1_50 = _out_wofireMux_T_1252; // @[RegisterRouter.scala:87:24]
assign out_woready_1_51 = _out_wofireMux_T_1252; // @[RegisterRouter.scala:87:24]
assign out_woready_1_52 = _out_wofireMux_T_1252; // @[RegisterRouter.scala:87:24]
assign out_woready_1_53 = _out_wofireMux_T_1252; // @[RegisterRouter.scala:87:24]
assign out_woready_1_54 = _out_wofireMux_T_1252; // @[RegisterRouter.scala:87:24]
assign out_woready_1_55 = _out_wofireMux_T_1252; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1253 = ~_out_T_1613; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1255 = _out_wofireMux_T_262 & out_backSel_248; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_1256 = _out_wofireMux_T_1255 & _out_T_1673; // @[RegisterRouter.scala:87:24]
assign out_woready_1_288 = _out_wofireMux_T_1256; // @[RegisterRouter.scala:87:24]
assign out_woready_1_289 = _out_wofireMux_T_1256; // @[RegisterRouter.scala:87:24]
assign out_woready_1_290 = _out_wofireMux_T_1256; // @[RegisterRouter.scala:87:24]
assign out_woready_1_291 = _out_wofireMux_T_1256; // @[RegisterRouter.scala:87:24]
assign out_woready_1_292 = _out_wofireMux_T_1256; // @[RegisterRouter.scala:87:24]
assign out_woready_1_293 = _out_wofireMux_T_1256; // @[RegisterRouter.scala:87:24]
assign out_woready_1_294 = _out_wofireMux_T_1256; // @[RegisterRouter.scala:87:24]
assign out_woready_1_295 = _out_wofireMux_T_1256; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1257 = ~_out_T_1673; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1259 = _out_wofireMux_T_262 & out_backSel_249; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_1260 = _out_wofireMux_T_1259 & _out_T_1603; // @[RegisterRouter.scala:87:24]
assign out_woready_1_8 = _out_wofireMux_T_1260; // @[RegisterRouter.scala:87:24]
assign out_woready_1_9 = _out_wofireMux_T_1260; // @[RegisterRouter.scala:87:24]
assign out_woready_1_10 = _out_wofireMux_T_1260; // @[RegisterRouter.scala:87:24]
assign out_woready_1_11 = _out_wofireMux_T_1260; // @[RegisterRouter.scala:87:24]
assign out_woready_1_12 = _out_wofireMux_T_1260; // @[RegisterRouter.scala:87:24]
assign out_woready_1_13 = _out_wofireMux_T_1260; // @[RegisterRouter.scala:87:24]
assign out_woready_1_14 = _out_wofireMux_T_1260; // @[RegisterRouter.scala:87:24]
assign out_woready_1_15 = _out_wofireMux_T_1260; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1261 = ~_out_T_1603; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1263 = _out_wofireMux_T_262 & out_backSel_250; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_1264 = _out_wofireMux_T_1263 & _out_T_1843; // @[RegisterRouter.scala:87:24]
assign out_woready_1_939 = _out_wofireMux_T_1264; // @[RegisterRouter.scala:87:24]
assign out_woready_1_940 = _out_wofireMux_T_1264; // @[RegisterRouter.scala:87:24]
assign out_woready_1_941 = _out_wofireMux_T_1264; // @[RegisterRouter.scala:87:24]
assign out_woready_1_942 = _out_wofireMux_T_1264; // @[RegisterRouter.scala:87:24]
assign out_woready_1_943 = _out_wofireMux_T_1264; // @[RegisterRouter.scala:87:24]
assign out_woready_1_944 = _out_wofireMux_T_1264; // @[RegisterRouter.scala:87:24]
assign out_woready_1_945 = _out_wofireMux_T_1264; // @[RegisterRouter.scala:87:24]
assign out_woready_1_946 = _out_wofireMux_T_1264; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1265 = ~_out_T_1843; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1267 = _out_wofireMux_T_262 & out_backSel_251; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_1268 = _out_wofireMux_T_1267 & _out_T_1795; // @[RegisterRouter.scala:87:24]
assign out_woready_1_747 = _out_wofireMux_T_1268; // @[RegisterRouter.scala:87:24]
assign out_woready_1_748 = _out_wofireMux_T_1268; // @[RegisterRouter.scala:87:24]
assign out_woready_1_749 = _out_wofireMux_T_1268; // @[RegisterRouter.scala:87:24]
assign out_woready_1_750 = _out_wofireMux_T_1268; // @[RegisterRouter.scala:87:24]
assign out_woready_1_751 = _out_wofireMux_T_1268; // @[RegisterRouter.scala:87:24]
assign out_woready_1_752 = _out_wofireMux_T_1268; // @[RegisterRouter.scala:87:24]
assign out_woready_1_753 = _out_wofireMux_T_1268; // @[RegisterRouter.scala:87:24]
assign out_woready_1_754 = _out_wofireMux_T_1268; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1269 = ~_out_T_1795; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1271 = _out_wofireMux_T_262 & out_backSel_252; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_1272 = _out_wofireMux_T_1271 & _out_T_1693; // @[RegisterRouter.scala:87:24]
assign out_woready_1_362 = _out_wofireMux_T_1272; // @[RegisterRouter.scala:87:24]
assign out_woready_1_363 = _out_wofireMux_T_1272; // @[RegisterRouter.scala:87:24]
assign out_woready_1_364 = _out_wofireMux_T_1272; // @[RegisterRouter.scala:87:24]
assign out_woready_1_365 = _out_wofireMux_T_1272; // @[RegisterRouter.scala:87:24]
assign out_woready_1_366 = _out_wofireMux_T_1272; // @[RegisterRouter.scala:87:24]
assign out_woready_1_367 = _out_wofireMux_T_1272; // @[RegisterRouter.scala:87:24]
assign out_woready_1_368 = _out_wofireMux_T_1272; // @[RegisterRouter.scala:87:24]
assign out_woready_1_369 = _out_wofireMux_T_1272; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1273 = ~_out_T_1693; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1275 = _out_wofireMux_T_262 & out_backSel_253; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_1276 = _out_wofireMux_T_1275 & _out_T_1655; // @[RegisterRouter.scala:87:24]
assign out_woready_1_216 = _out_wofireMux_T_1276; // @[RegisterRouter.scala:87:24]
assign out_woready_1_217 = _out_wofireMux_T_1276; // @[RegisterRouter.scala:87:24]
assign out_woready_1_218 = _out_wofireMux_T_1276; // @[RegisterRouter.scala:87:24]
assign out_woready_1_219 = _out_wofireMux_T_1276; // @[RegisterRouter.scala:87:24]
assign out_woready_1_220 = _out_wofireMux_T_1276; // @[RegisterRouter.scala:87:24]
assign out_woready_1_221 = _out_wofireMux_T_1276; // @[RegisterRouter.scala:87:24]
assign out_woready_1_222 = _out_wofireMux_T_1276; // @[RegisterRouter.scala:87:24]
assign out_woready_1_223 = _out_wofireMux_T_1276; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1277 = ~_out_T_1655; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1279 = _out_wofireMux_T_262 & out_backSel_254; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_1280 = _out_wofireMux_T_1279 & _out_T_1907; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1195 = _out_wofireMux_T_1280; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1196 = _out_wofireMux_T_1280; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1197 = _out_wofireMux_T_1280; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1198 = _out_wofireMux_T_1280; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1199 = _out_wofireMux_T_1280; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1200 = _out_wofireMux_T_1280; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1201 = _out_wofireMux_T_1280; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1202 = _out_wofireMux_T_1280; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1281 = ~_out_T_1907; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1283 = _out_wofireMux_T_262 & out_backSel_255; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_1284 = _out_wofireMux_T_1283 & _out_T_1811; // @[RegisterRouter.scala:87:24]
assign out_woready_1_811 = _out_wofireMux_T_1284; // @[RegisterRouter.scala:87:24]
assign out_woready_1_812 = _out_wofireMux_T_1284; // @[RegisterRouter.scala:87:24]
assign out_woready_1_813 = _out_wofireMux_T_1284; // @[RegisterRouter.scala:87:24]
assign out_woready_1_814 = _out_wofireMux_T_1284; // @[RegisterRouter.scala:87:24]
assign out_woready_1_815 = _out_wofireMux_T_1284; // @[RegisterRouter.scala:87:24]
assign out_woready_1_816 = _out_wofireMux_T_1284; // @[RegisterRouter.scala:87:24]
assign out_woready_1_817 = _out_wofireMux_T_1284; // @[RegisterRouter.scala:87:24]
assign out_woready_1_818 = _out_wofireMux_T_1284; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1285 = ~_out_T_1811; // @[RegisterRouter.scala:87:24]
assign in_1_ready = _out_in_ready_T_1; // @[RegisterRouter.scala:73:18, :87:24]
assign out_front_1_valid = _out_front_valid_T_1; // @[RegisterRouter.scala:87:24]
assign out_front_1_ready = _out_front_ready_T_1; // @[RegisterRouter.scala:87:24]
assign out_1_valid = _out_out_valid_T_1; // @[RegisterRouter.scala:87:24]
wire [255:0] _GEN_24 =
{{_out_out_bits_data_WIRE_2_255},
{_out_out_bits_data_WIRE_2_254},
{_out_out_bits_data_WIRE_2_253},
{_out_out_bits_data_WIRE_2_252},
{_out_out_bits_data_WIRE_2_251},
{_out_out_bits_data_WIRE_2_250},
{_out_out_bits_data_WIRE_2_249},
{_out_out_bits_data_WIRE_2_248},
{_out_out_bits_data_WIRE_2_247},
{_out_out_bits_data_WIRE_2_246},
{_out_out_bits_data_WIRE_2_245},
{_out_out_bits_data_WIRE_2_244},
{_out_out_bits_data_WIRE_2_243},
{_out_out_bits_data_WIRE_2_242},
{_out_out_bits_data_WIRE_2_241},
{_out_out_bits_data_WIRE_2_240},
{_out_out_bits_data_WIRE_2_239},
{_out_out_bits_data_WIRE_2_238},
{_out_out_bits_data_WIRE_2_237},
{_out_out_bits_data_WIRE_2_236},
{_out_out_bits_data_WIRE_2_235},
{_out_out_bits_data_WIRE_2_234},
{_out_out_bits_data_WIRE_2_233},
{_out_out_bits_data_WIRE_2_232},
{_out_out_bits_data_WIRE_2_231},
{_out_out_bits_data_WIRE_2_230},
{_out_out_bits_data_WIRE_2_229},
{_out_out_bits_data_WIRE_2_228},
{_out_out_bits_data_WIRE_2_227},
{_out_out_bits_data_WIRE_2_226},
{_out_out_bits_data_WIRE_2_225},
{_out_out_bits_data_WIRE_2_224},
{_out_out_bits_data_WIRE_2_223},
{_out_out_bits_data_WIRE_2_222},
{_out_out_bits_data_WIRE_2_221},
{_out_out_bits_data_WIRE_2_220},
{_out_out_bits_data_WIRE_2_219},
{_out_out_bits_data_WIRE_2_218},
{_out_out_bits_data_WIRE_2_217},
{_out_out_bits_data_WIRE_2_216},
{_out_out_bits_data_WIRE_2_215},
{_out_out_bits_data_WIRE_2_214},
{_out_out_bits_data_WIRE_2_213},
{_out_out_bits_data_WIRE_2_212},
{_out_out_bits_data_WIRE_2_211},
{_out_out_bits_data_WIRE_2_210},
{_out_out_bits_data_WIRE_2_209},
{_out_out_bits_data_WIRE_2_208},
{_out_out_bits_data_WIRE_2_207},
{_out_out_bits_data_WIRE_2_206},
{_out_out_bits_data_WIRE_2_205},
{_out_out_bits_data_WIRE_2_204},
{_out_out_bits_data_WIRE_2_203},
{_out_out_bits_data_WIRE_2_202},
{_out_out_bits_data_WIRE_2_201},
{_out_out_bits_data_WIRE_2_200},
{_out_out_bits_data_WIRE_2_199},
{_out_out_bits_data_WIRE_2_198},
{_out_out_bits_data_WIRE_2_197},
{_out_out_bits_data_WIRE_2_196},
{_out_out_bits_data_WIRE_2_195},
{_out_out_bits_data_WIRE_2_194},
{_out_out_bits_data_WIRE_2_193},
{_out_out_bits_data_WIRE_2_192},
{_out_out_bits_data_WIRE_2_191},
{_out_out_bits_data_WIRE_2_190},
{_out_out_bits_data_WIRE_2_189},
{_out_out_bits_data_WIRE_2_188},
{_out_out_bits_data_WIRE_2_187},
{_out_out_bits_data_WIRE_2_186},
{_out_out_bits_data_WIRE_2_185},
{_out_out_bits_data_WIRE_2_184},
{_out_out_bits_data_WIRE_2_183},
{_out_out_bits_data_WIRE_2_182},
{_out_out_bits_data_WIRE_2_181},
{_out_out_bits_data_WIRE_2_180},
{_out_out_bits_data_WIRE_2_179},
{_out_out_bits_data_WIRE_2_178},
{_out_out_bits_data_WIRE_2_177},
{_out_out_bits_data_WIRE_2_176},
{_out_out_bits_data_WIRE_2_175},
{_out_out_bits_data_WIRE_2_174},
{_out_out_bits_data_WIRE_2_173},
{_out_out_bits_data_WIRE_2_172},
{_out_out_bits_data_WIRE_2_171},
{_out_out_bits_data_WIRE_2_170},
{_out_out_bits_data_WIRE_2_169},
{_out_out_bits_data_WIRE_2_168},
{_out_out_bits_data_WIRE_2_167},
{_out_out_bits_data_WIRE_2_166},
{_out_out_bits_data_WIRE_2_165},
{_out_out_bits_data_WIRE_2_164},
{_out_out_bits_data_WIRE_2_163},
{_out_out_bits_data_WIRE_2_162},
{_out_out_bits_data_WIRE_2_161},
{_out_out_bits_data_WIRE_2_160},
{_out_out_bits_data_WIRE_2_159},
{_out_out_bits_data_WIRE_2_158},
{_out_out_bits_data_WIRE_2_157},
{_out_out_bits_data_WIRE_2_156},
{_out_out_bits_data_WIRE_2_155},
{_out_out_bits_data_WIRE_2_154},
{_out_out_bits_data_WIRE_2_153},
{_out_out_bits_data_WIRE_2_152},
{_out_out_bits_data_WIRE_2_151},
{_out_out_bits_data_WIRE_2_150},
{_out_out_bits_data_WIRE_2_149},
{_out_out_bits_data_WIRE_2_148},
{_out_out_bits_data_WIRE_2_147},
{_out_out_bits_data_WIRE_2_146},
{_out_out_bits_data_WIRE_2_145},
{_out_out_bits_data_WIRE_2_144},
{_out_out_bits_data_WIRE_2_143},
{_out_out_bits_data_WIRE_2_142},
{_out_out_bits_data_WIRE_2_141},
{_out_out_bits_data_WIRE_2_140},
{_out_out_bits_data_WIRE_2_139},
{_out_out_bits_data_WIRE_2_138},
{_out_out_bits_data_WIRE_2_137},
{_out_out_bits_data_WIRE_2_136},
{_out_out_bits_data_WIRE_2_135},
{_out_out_bits_data_WIRE_2_134},
{_out_out_bits_data_WIRE_2_133},
{_out_out_bits_data_WIRE_2_132},
{_out_out_bits_data_WIRE_2_131},
{_out_out_bits_data_WIRE_2_130},
{_out_out_bits_data_WIRE_2_129},
{_out_out_bits_data_WIRE_2_128},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{_out_out_bits_data_WIRE_2_115},
{_out_out_bits_data_WIRE_2_114},
{_out_out_bits_data_WIRE_2_113},
{_out_out_bits_data_WIRE_2_112},
{_out_out_bits_data_WIRE_2_111},
{_out_out_bits_data_WIRE_2_110},
{_out_out_bits_data_WIRE_2_109},
{_out_out_bits_data_WIRE_2_108},
{_out_out_bits_data_WIRE_2_107},
{_out_out_bits_data_WIRE_2_106},
{_out_out_bits_data_WIRE_2_105},
{_out_out_bits_data_WIRE_2_104},
{_out_out_bits_data_WIRE_2_103},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{_out_out_bits_data_WIRE_2_96},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{_out_out_bits_data_WIRE_2_33},
{_out_out_bits_data_WIRE_2_32},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{_out_out_bits_data_WIRE_2_10},
{_out_out_bits_data_WIRE_2_9},
{_out_out_bits_data_WIRE_2_8},
{_out_out_bits_data_WIRE_2_7},
{_out_out_bits_data_WIRE_2_6},
{_out_out_bits_data_WIRE_2_5},
{_out_out_bits_data_WIRE_2_4},
{_out_out_bits_data_WIRE_2_3},
{_out_out_bits_data_WIRE_2_2},
{_out_out_bits_data_WIRE_2_1},
{_out_out_bits_data_WIRE_2_0}}; // @[MuxLiteral.scala:49:{10,48}]
wire _out_out_bits_data_T_6 = _GEN_24[out_oindex_1]; // @[MuxLiteral.scala:49:10]
wire [255:0][63:0] _GEN_25 =
{{_out_out_bits_data_WIRE_3_255},
{_out_out_bits_data_WIRE_3_254},
{_out_out_bits_data_WIRE_3_253},
{_out_out_bits_data_WIRE_3_252},
{_out_out_bits_data_WIRE_3_251},
{_out_out_bits_data_WIRE_3_250},
{_out_out_bits_data_WIRE_3_249},
{_out_out_bits_data_WIRE_3_248},
{_out_out_bits_data_WIRE_3_247},
{_out_out_bits_data_WIRE_3_246},
{_out_out_bits_data_WIRE_3_245},
{_out_out_bits_data_WIRE_3_244},
{_out_out_bits_data_WIRE_3_243},
{_out_out_bits_data_WIRE_3_242},
{_out_out_bits_data_WIRE_3_241},
{_out_out_bits_data_WIRE_3_240},
{_out_out_bits_data_WIRE_3_239},
{_out_out_bits_data_WIRE_3_238},
{_out_out_bits_data_WIRE_3_237},
{_out_out_bits_data_WIRE_3_236},
{_out_out_bits_data_WIRE_3_235},
{_out_out_bits_data_WIRE_3_234},
{_out_out_bits_data_WIRE_3_233},
{_out_out_bits_data_WIRE_3_232},
{_out_out_bits_data_WIRE_3_231},
{_out_out_bits_data_WIRE_3_230},
{_out_out_bits_data_WIRE_3_229},
{_out_out_bits_data_WIRE_3_228},
{_out_out_bits_data_WIRE_3_227},
{_out_out_bits_data_WIRE_3_226},
{_out_out_bits_data_WIRE_3_225},
{_out_out_bits_data_WIRE_3_224},
{_out_out_bits_data_WIRE_3_223},
{_out_out_bits_data_WIRE_3_222},
{_out_out_bits_data_WIRE_3_221},
{_out_out_bits_data_WIRE_3_220},
{_out_out_bits_data_WIRE_3_219},
{_out_out_bits_data_WIRE_3_218},
{_out_out_bits_data_WIRE_3_217},
{_out_out_bits_data_WIRE_3_216},
{_out_out_bits_data_WIRE_3_215},
{_out_out_bits_data_WIRE_3_214},
{_out_out_bits_data_WIRE_3_213},
{_out_out_bits_data_WIRE_3_212},
{_out_out_bits_data_WIRE_3_211},
{_out_out_bits_data_WIRE_3_210},
{_out_out_bits_data_WIRE_3_209},
{_out_out_bits_data_WIRE_3_208},
{_out_out_bits_data_WIRE_3_207},
{_out_out_bits_data_WIRE_3_206},
{_out_out_bits_data_WIRE_3_205},
{_out_out_bits_data_WIRE_3_204},
{_out_out_bits_data_WIRE_3_203},
{_out_out_bits_data_WIRE_3_202},
{_out_out_bits_data_WIRE_3_201},
{_out_out_bits_data_WIRE_3_200},
{_out_out_bits_data_WIRE_3_199},
{_out_out_bits_data_WIRE_3_198},
{_out_out_bits_data_WIRE_3_197},
{_out_out_bits_data_WIRE_3_196},
{_out_out_bits_data_WIRE_3_195},
{_out_out_bits_data_WIRE_3_194},
{_out_out_bits_data_WIRE_3_193},
{_out_out_bits_data_WIRE_3_192},
{_out_out_bits_data_WIRE_3_191},
{_out_out_bits_data_WIRE_3_190},
{_out_out_bits_data_WIRE_3_189},
{_out_out_bits_data_WIRE_3_188},
{_out_out_bits_data_WIRE_3_187},
{_out_out_bits_data_WIRE_3_186},
{_out_out_bits_data_WIRE_3_185},
{_out_out_bits_data_WIRE_3_184},
{_out_out_bits_data_WIRE_3_183},
{_out_out_bits_data_WIRE_3_182},
{_out_out_bits_data_WIRE_3_181},
{_out_out_bits_data_WIRE_3_180},
{_out_out_bits_data_WIRE_3_179},
{_out_out_bits_data_WIRE_3_178},
{_out_out_bits_data_WIRE_3_177},
{_out_out_bits_data_WIRE_3_176},
{_out_out_bits_data_WIRE_3_175},
{_out_out_bits_data_WIRE_3_174},
{_out_out_bits_data_WIRE_3_173},
{_out_out_bits_data_WIRE_3_172},
{_out_out_bits_data_WIRE_3_171},
{_out_out_bits_data_WIRE_3_170},
{_out_out_bits_data_WIRE_3_169},
{_out_out_bits_data_WIRE_3_168},
{_out_out_bits_data_WIRE_3_167},
{_out_out_bits_data_WIRE_3_166},
{_out_out_bits_data_WIRE_3_165},
{_out_out_bits_data_WIRE_3_164},
{_out_out_bits_data_WIRE_3_163},
{_out_out_bits_data_WIRE_3_162},
{_out_out_bits_data_WIRE_3_161},
{_out_out_bits_data_WIRE_3_160},
{_out_out_bits_data_WIRE_3_159},
{_out_out_bits_data_WIRE_3_158},
{_out_out_bits_data_WIRE_3_157},
{_out_out_bits_data_WIRE_3_156},
{_out_out_bits_data_WIRE_3_155},
{_out_out_bits_data_WIRE_3_154},
{_out_out_bits_data_WIRE_3_153},
{_out_out_bits_data_WIRE_3_152},
{_out_out_bits_data_WIRE_3_151},
{_out_out_bits_data_WIRE_3_150},
{_out_out_bits_data_WIRE_3_149},
{_out_out_bits_data_WIRE_3_148},
{_out_out_bits_data_WIRE_3_147},
{_out_out_bits_data_WIRE_3_146},
{_out_out_bits_data_WIRE_3_145},
{_out_out_bits_data_WIRE_3_144},
{_out_out_bits_data_WIRE_3_143},
{_out_out_bits_data_WIRE_3_142},
{_out_out_bits_data_WIRE_3_141},
{_out_out_bits_data_WIRE_3_140},
{_out_out_bits_data_WIRE_3_139},
{_out_out_bits_data_WIRE_3_138},
{_out_out_bits_data_WIRE_3_137},
{_out_out_bits_data_WIRE_3_136},
{_out_out_bits_data_WIRE_3_135},
{_out_out_bits_data_WIRE_3_134},
{_out_out_bits_data_WIRE_3_133},
{_out_out_bits_data_WIRE_3_132},
{_out_out_bits_data_WIRE_3_131},
{_out_out_bits_data_WIRE_3_130},
{_out_out_bits_data_WIRE_3_129},
{_out_out_bits_data_WIRE_3_128},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{_out_out_bits_data_WIRE_3_115},
{_out_out_bits_data_WIRE_3_114},
{_out_out_bits_data_WIRE_3_113},
{_out_out_bits_data_WIRE_3_112},
{_out_out_bits_data_WIRE_3_111},
{_out_out_bits_data_WIRE_3_110},
{_out_out_bits_data_WIRE_3_109},
{_out_out_bits_data_WIRE_3_108},
{_out_out_bits_data_WIRE_3_107},
{_out_out_bits_data_WIRE_3_106},
{_out_out_bits_data_WIRE_3_105},
{_out_out_bits_data_WIRE_3_104},
{_out_out_bits_data_WIRE_3_103},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h380006F},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h100073},
{64'h100026237B200073},
{64'h7B20247310802423},
{64'hF140247330000067},
{64'h100022237B202473},
{64'h4086300147413},
{64'hFE0408E300347413},
{64'h4004440310802023},
{64'hF14024737B241073},
{64'hFF0000F0440006F},
{64'h380006F00C0006F}}; // @[MuxLiteral.scala:49:{10,48}]
wire [63:0] _out_out_bits_data_T_8 = _GEN_25[out_oindex_1]; // @[MuxLiteral.scala:49:10]
assign _out_out_bits_data_T_9 = _out_out_bits_data_T_6 ? _out_out_bits_data_T_8 : 64'h0; // @[MuxLiteral.scala:49:10]
assign out_1_bits_data = _out_out_bits_data_T_9; // @[RegisterRouter.scala:87:24]
assign tlNodeIn_d_bits_size = tlNodeIn_d_bits_d_size; // @[Edges.scala:792:17]
assign tlNodeIn_d_bits_source = tlNodeIn_d_bits_d_source; // @[Edges.scala:792:17]
assign tlNodeIn_d_bits_opcode = {2'h0, _tlNodeIn_d_bits_opcode_T}; // @[RegisterRouter.scala:105:{19,25}]
reg [1:0] ctrlStateReg; // @[Debug.scala:1732:27]
wire hartHalted = _hartHalted_T; // @[Debug.scala:1734:37]
wire [1:0] ctrlStateNxt; // @[Debug.scala:1735:32]
assign _abstractCommandBusy_T = |ctrlStateReg; // @[Debug.scala:1732:27, :1740:42]
assign abstractCommandBusy = _abstractCommandBusy_T; // @[Debug.scala:1220:39, :1740:42]
assign _ABSTRACTCSWrEnLegal_T = ~(|ctrlStateReg); // @[Debug.scala:1732:27, :1740:42, :1742:44]
assign ABSTRACTCSWrEnLegal = _ABSTRACTCSWrEnLegal_T; // @[Debug.scala:1190:39, :1742:44]
assign _COMMANDWrEnLegal_T = ~(|ctrlStateReg); // @[Debug.scala:1732:27, :1740:42, :1742:44, :1743:44]
assign COMMANDWrEnLegal = _COMMANDWrEnLegal_T; // @[Debug.scala:1282:39, :1743:44]
assign _ABSTRACTAUTOWrEnLegal_T = ~(|ctrlStateReg); // @[Debug.scala:1732:27, :1740:42, :1742:44, :1744:44]
assign ABSTRACTAUTOWrEnLegal = _ABSTRACTAUTOWrEnLegal_T; // @[Debug.scala:1243:41, :1744:44]
assign _dmiAbstractDataAccessLegal_T = ~(|ctrlStateReg); // @[Debug.scala:1732:27, :1740:42, :1742:44, :1745:50]
assign dmiAbstractDataAccessLegal = _dmiAbstractDataAccessLegal_T; // @[Debug.scala:892:46, :1745:50]
assign _dmiProgramBufferAccessLegal_T = ~(|ctrlStateReg); // @[Debug.scala:1732:27, :1740:42, :1742:44, :1746:50]
assign dmiProgramBufferAccessLegal = _dmiProgramBufferAccessLegal_T; // @[Debug.scala:888:47, :1746:50]
wire _errorBusy_T = ~ABSTRACTCSWrEnLegal; // @[Debug.scala:1190:39, :1748:45]
wire _errorBusy_T_1 = ABSTRACTCSWrEnMaybe & _errorBusy_T; // @[Debug.scala:1188:39, :1748:{42,45}]
wire _errorBusy_T_2 = ~ABSTRACTAUTOWrEnLegal; // @[Debug.scala:1243:41, :1749:45]
wire _errorBusy_T_3 = autoexecdataWrEnMaybe & _errorBusy_T_2; // @[Debug.scala:1240:41, :1749:{42,45}]
wire _errorBusy_T_4 = _errorBusy_T_1 | _errorBusy_T_3; // @[Debug.scala:1748:{42,74}, :1749:42]
wire _errorBusy_T_5 = ~ABSTRACTAUTOWrEnLegal; // @[Debug.scala:1243:41, :1749:45, :1750:47]
wire _errorBusy_T_6 = autoexecprogbufWrEnMaybe & _errorBusy_T_5; // @[Debug.scala:1241:44, :1750:{44,47}]
wire _errorBusy_T_7 = _errorBusy_T_4 | _errorBusy_T_6; // @[Debug.scala:1748:74, :1749:74, :1750:44]
wire _errorBusy_T_8 = ~COMMANDWrEnLegal; // @[Debug.scala:1282:39, :1751:45]
wire _errorBusy_T_9 = COMMANDWrEnMaybe & _errorBusy_T_8; // @[Debug.scala:1281:39, :1751:{42,45}]
wire _errorBusy_T_10 = _errorBusy_T_7 | _errorBusy_T_9; // @[Debug.scala:1749:74, :1750:74, :1751:42]
wire _errorBusy_T_11 = ~dmiAbstractDataAccessLegal; // @[Debug.scala:892:46, :1752:45]
wire _errorBusy_T_12 = dmiAbstractDataAccess & _errorBusy_T_11; // @[Debug.scala:1263:68, :1752:{42,45}]
wire _errorBusy_T_13 = _errorBusy_T_10 | _errorBusy_T_12; // @[Debug.scala:1750:74, :1751:74, :1752:42]
wire _errorBusy_T_14 = ~dmiProgramBufferAccessLegal; // @[Debug.scala:888:47, :1753:45]
wire _errorBusy_T_15 = dmiProgramBufferAccess & _errorBusy_T_14; // @[Debug.scala:1264:69, :1753:{42,45}]
assign _errorBusy_T_16 = _errorBusy_T_13 | _errorBusy_T_15; // @[Debug.scala:1751:74, :1752:74, :1753:42]
assign errorBusy = _errorBusy_T_16; // @[Debug.scala:1195:36, :1752:74]
wire commandWrIsAccessRegister = COMMANDWrData_cmdtype == 8'h0; // @[Debug.scala:1280:39, :1756:60]
wire commandRegIsAccessRegister = COMMANDReg_cmdtype == 8'h0; // @[Debug.scala:1277:25, :1757:58]
wire _commandWrIsUnsupported_T = ~commandWrIsAccessRegister; // @[Debug.scala:1756:60, :1759:49]
wire commandWrIsUnsupported = COMMANDWrEn & _commandWrIsUnsupported_T; // @[Debug.scala:1285:40, :1759:{46,49}]
wire commandRegIsUnsupported; // @[Debug.scala:1761:43]
wire commandRegBadHaltResume; // @[Debug.scala:1762:43]
wire _accessRegIsLegalSize_T = accessRegisterCommandReg_size == 3'h2; // @[Debug.scala:1533:44, :1765:63]
wire _accessRegIsLegalSize_T_1 = accessRegisterCommandReg_size == 3'h3; // @[Debug.scala:1533:44, :1765:106]
wire accessRegIsLegalSize = _accessRegIsLegalSize_T | _accessRegIsLegalSize_T_1; // @[Debug.scala:1765:{63,72,106}]
wire _accessRegIsGPR_T = |(accessRegisterCommandReg_regno[15:12]); // @[Debug.scala:1533:44, :1766:58]
wire _accessRegIsGPR_T_1 = accessRegisterCommandReg_regno < 16'h1020; // @[Debug.scala:1533:44, :1766:104]
wire _accessRegIsGPR_T_2 = _accessRegIsGPR_T & _accessRegIsGPR_T_1; // @[Debug.scala:1766:{58,70,104}]
wire accessRegIsGPR = _accessRegIsGPR_T_2 & accessRegIsLegalSize; // @[Debug.scala:1765:72, :1766:{70,117}]
wire _T_1567 = ~accessRegisterCommandReg_transfer | accessRegIsGPR; // @[Debug.scala:1533:44, :1766:117, :1776:{19,54}]
assign commandRegIsUnsupported = ~commandRegIsAccessRegister | ~_T_1567; // @[Debug.scala:1757:58, :1761:43, :1773:39, :1774:115, :1775:33, :1776:{54,73}, :1777:33]
wire _commandRegBadHaltResume_T = ~hartHalted; // @[Debug.scala:1734:37, :1778:36]
assign commandRegBadHaltResume = commandRegIsAccessRegister & _T_1567 & _commandRegBadHaltResume_T; // @[Debug.scala:1757:58, :1762:43, :1773:39, :1774:115, :1776:{54,73}, :1778:{33,36}]
wire _wrAccessRegisterCommand_T = COMMANDWrEn & commandWrIsAccessRegister; // @[Debug.scala:1285:40, :1756:60, :1782:48]
wire _GEN_26 = ABSTRACTCSReg_cmderr == 3'h0; // @[Debug.scala:1183:34, :1782:103]
wire _wrAccessRegisterCommand_T_1; // @[Debug.scala:1782:103]
assign _wrAccessRegisterCommand_T_1 = _GEN_26; // @[Debug.scala:1782:103]
wire _regAccessRegisterCommand_T_1; // @[Debug.scala:1783:103]
assign _regAccessRegisterCommand_T_1 = _GEN_26; // @[Debug.scala:1782:103, :1783:103]
wire wrAccessRegisterCommand = _wrAccessRegisterCommand_T & _wrAccessRegisterCommand_T_1; // @[Debug.scala:1782:{48,78,103}]
wire _regAccessRegisterCommand_T = autoexec & commandRegIsAccessRegister; // @[Debug.scala:1272:48, :1757:58, :1783:48]
wire regAccessRegisterCommand = _regAccessRegisterCommand_T & _regAccessRegisterCommand_T_1; // @[Debug.scala:1783:{48,78,103}]
wire _T_1569 = wrAccessRegisterCommand | regAccessRegisterCommand; // @[Debug.scala:1782:78, :1783:78, :1790:37]
wire _T_1571 = ctrlStateReg == 2'h1; // @[Debug.scala:1732:27, :1797:30]
assign errorUnsupported = (|ctrlStateReg) ? _T_1571 & commandRegIsUnsupported : ~_T_1569 & (commandWrIsUnsupported | autoexec & commandRegIsUnsupported); // @[Debug.scala:1197:36, :1272:48, :1732:27, :1740:42, :1759:46, :1761:43, :1789:47, :1790:{37,66}, :1792:43, :1793:26, :1794:{28,56}, :1797:{30,59}, :1804:38]
assign errorHaltResume = (|ctrlStateReg) & _T_1571 & ~commandRegIsUnsupported & commandRegBadHaltResume; // @[Debug.scala:1198:36, :1732:27, :1740:42, :1761:43, :1762:43, :1789:47, :1797:{30,59}, :1804:38, :1807:43]
wire _GEN_27 = commandRegIsUnsupported | commandRegBadHaltResume; // @[Debug.scala:1761:43, :1762:43, :1804:38, :1806:22, :1807:43, :1809:22, :1811:33]
assign goAbstract = (|ctrlStateReg) & _T_1571 & ~_GEN_27; // @[Debug.scala:1495:32, :1732:27, :1740:42, :1789:47, :1797:{30,59}, :1804:38, :1806:22, :1807:43, :1809:22, :1811:33]
wire _T_1572 = ctrlStateReg == 2'h2; // @[Debug.scala:1732:27, :1818:30]
wire _GEN_28 = ~(|ctrlStateReg) | _T_1571; // @[Debug.scala:1196:36, :1732:27, :1740:42, :1742:44, :1789:47, :1797:{30,59}, :1818:51]
assign errorException = ~_GEN_28 & _T_1572 & hartExceptionWrEn; // @[Debug.scala:881:36, :1196:36, :1789:47, :1797:59, :1818:{30,51}, :1826:31]
assign goCustom = ~(_GEN_28 | _T_1572) & (&ctrlStateReg); // @[Debug.scala:1196:36, :1496:32, :1732:27, :1789:47, :1797:59, :1818:{30,51}, :1831:{30,53}]
assign ctrlStateNxt = (|ctrlStateReg) ? (_T_1571 ? {~_GEN_27, 1'h0} : _T_1572 & (hartExceptionWrEn | ~goReg & hartHaltedWrEn) ? 2'h0 : ctrlStateReg) : _T_1569 ? 2'h1 : ctrlStateReg; // @[Debug.scala:875:36, :881:36, :1494:27, :1732:27, :1735:32, :1740:42, :1789:47, :1790:{37,66}, :1791:22, :1797:{30,59}, :1804:38, :1806:22, :1807:43, :1809:22, :1811:33, :1818:{30,51}, :1823:{18,30,116}, :1824:22, :1826:31, :1828:24, :1831:53] |
Generate the Verilog code corresponding to the following Chisel files.
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File Debug.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.devices.debug
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.amba.apb.{APBFanout, APBToTL}
import freechips.rocketchip.devices.debug.systembusaccess.{SBToTL, SystemBusAccessModule}
import freechips.rocketchip.devices.tilelink.{DevNullParams, TLBusBypass, TLError}
import freechips.rocketchip.diplomacy.{AddressSet, BufferParams}
import freechips.rocketchip.resources.{Description, Device, Resource, ResourceBindings, ResourceString, SimpleDevice}
import freechips.rocketchip.interrupts.{IntNexusNode, IntSinkParameters, IntSinkPortParameters, IntSourceParameters, IntSourcePortParameters, IntSyncCrossingSource, IntSyncIdentityNode}
import freechips.rocketchip.regmapper.{RegField, RegFieldAccessType, RegFieldDesc, RegFieldGroup, RegFieldWrType, RegReadFn, RegWriteFn}
import freechips.rocketchip.rocket.{CSRs, Instructions}
import freechips.rocketchip.tile.MaxHartIdBits
import freechips.rocketchip.tilelink.{TLAsyncCrossingSink, TLAsyncCrossingSource, TLBuffer, TLRegisterNode, TLXbar}
import freechips.rocketchip.util.{Annotated, AsyncBundle, AsyncQueueParams, AsyncResetSynchronizerShiftReg, FromAsyncBundle, ParameterizedBundle, ResetSynchronizerShiftReg, ToAsyncBundle}
import freechips.rocketchip.util.SeqBoolBitwiseOps
import freechips.rocketchip.util.SeqToAugmentedSeq
import freechips.rocketchip.util.BooleanToAugmentedBoolean
object DsbBusConsts {
def sbAddrWidth = 12
def sbIdWidth = 10
}
object DsbRegAddrs{
// These are used by the ROM.
def HALTED = 0x100
def GOING = 0x104
def RESUMING = 0x108
def EXCEPTION = 0x10C
def WHERETO = 0x300
// This needs to be aligned for up to lq/sq
// This shows up in HartInfo, and needs to be aligned
// to enable up to LQ/SQ instructions.
def DATA = 0x380
// We want DATA to immediately follow PROGBUF so that we can
// use them interchangeably. Leave another slot if there is an
// implicit ebreak.
def PROGBUF(cfg:DebugModuleParams) = {
val tmp = DATA - (cfg.nProgramBufferWords * 4)
if (cfg.hasImplicitEbreak) (tmp - 4) else tmp
}
// This is unused if hasImpEbreak is false, and just points to the end of the PROGBUF.
def IMPEBREAK(cfg: DebugModuleParams) = { DATA - 4 }
// We want abstract to be immediately before PROGBUF
// because we auto-generate 2 (or 5) instructions.
def ABSTRACT(cfg:DebugModuleParams) = PROGBUF(cfg) - (cfg.nAbstractInstructions * 4)
def FLAGS = 0x400
def ROMBASE = 0x800
}
/** Enumerations used both in the hardware
* and in the configuration specification.
*/
object DebugModuleAccessType extends scala.Enumeration {
type DebugModuleAccessType = Value
val Access8Bit, Access16Bit, Access32Bit, Access64Bit, Access128Bit = Value
}
object DebugAbstractCommandError extends scala.Enumeration {
type DebugAbstractCommandError = Value
val Success, ErrBusy, ErrNotSupported, ErrException, ErrHaltResume = Value
}
object DebugAbstractCommandType extends scala.Enumeration {
type DebugAbstractCommandType = Value
val AccessRegister, QuickAccess = Value
}
/** Parameters exposed to the top-level design, set based on
* external requirements, etc.
*
* This object checks that the parameters conform to the
* full specification. The implementation which receives this
* object can perform more checks on what that implementation
* actually supports.
* @param nComponents Number of components to support debugging.
* @param baseAddress Base offest for debugEntry and debugException
* @param nDMIAddrSize Size of the Debug Bus Address
* @param nAbstractDataWords Number of 32-bit words for Abstract Commands
* @param nProgamBufferWords Number of 32-bit words for Program Buffer
* @param hasBusMaster Whether or not a bus master should be included
* @param clockGate Whether or not to use dmactive as the clockgate for debug module
* @param maxSupportedSBAccess Maximum transaction size supported by System Bus Access logic.
* @param supportQuickAccess Whether or not to support the quick access command.
* @param supportHartArray Whether or not to implement the hart array register (if >1 hart).
* @param nHaltGroups Number of halt groups
* @param nExtTriggers Number of external triggers
* @param hasHartResets Feature to reset all the currently selected harts
* @param hasImplicitEbreak There is an additional RO program buffer word containing an ebreak
* @param crossingHasSafeReset Include "safe" logic in Async Crossings so that only one side needs to be reset.
*/
case class DebugModuleParams (
baseAddress : BigInt = BigInt(0),
nDMIAddrSize : Int = 7,
nProgramBufferWords: Int = 16,
nAbstractDataWords : Int = 4,
nScratch : Int = 1,
hasBusMaster : Boolean = false,
clockGate : Boolean = true,
maxSupportedSBAccess : Int = 32,
supportQuickAccess : Boolean = false,
supportHartArray : Boolean = true,
nHaltGroups : Int = 1,
nExtTriggers : Int = 0,
hasHartResets : Boolean = false,
hasImplicitEbreak : Boolean = false,
hasAuthentication : Boolean = false,
crossingHasSafeReset : Boolean = true
) {
require ((nDMIAddrSize >= 7) && (nDMIAddrSize <= 32), s"Legal DMIAddrSize is 7-32, not ${nDMIAddrSize}")
require ((nAbstractDataWords > 0) && (nAbstractDataWords <= 16), s"Legal nAbstractDataWords is 0-16, not ${nAbstractDataWords}")
require ((nProgramBufferWords >= 0) && (nProgramBufferWords <= 16), s"Legal nProgramBufferWords is 0-16, not ${nProgramBufferWords}")
require (nHaltGroups < 32, s"Legal nHaltGroups is 0-31, not ${nHaltGroups}")
require (nExtTriggers <= 16, s"Legal nExtTriggers is 0-16, not ${nExtTriggers}")
if (supportQuickAccess) {
// TODO: Check that quick access requirements are met.
}
def address = AddressSet(baseAddress, 0xFFF)
/** the base address of DM */
def atzero = (baseAddress == 0)
/** The number of generated instructions
*
* When the base address is not zero, we need more instruction also,
* more dscratch registers) to load/store memory mapped data register
* because they may no longer be directly addressible with x0 + 12-bit imm
*/
def nAbstractInstructions = if (atzero) 2 else 5
def debugEntry: BigInt = baseAddress + 0x800
def debugException: BigInt = baseAddress + 0x808
def nDscratch: Int = if (atzero) 1 else 2
}
object DefaultDebugModuleParams {
def apply(xlen:Int /*TODO , val configStringAddr: Int*/): DebugModuleParams = {
new DebugModuleParams().copy(
nAbstractDataWords = (if (xlen == 32) 1 else if (xlen == 64) 2 else 4),
maxSupportedSBAccess = xlen
)
}
}
case object DebugModuleKey extends Field[Option[DebugModuleParams]](Some(DebugModuleParams()))
/** Functional parameters exposed to the design configuration.
*
* hartIdToHartSel: For systems where hart ids are not 1:1 with hartsel, provide the mapping.
* hartSelToHartId: Provide inverse mapping of the above
*/
case class DebugModuleHartSelFuncs (
hartIdToHartSel : (UInt) => UInt = (x:UInt) => x,
hartSelToHartId : (UInt) => UInt = (x:UInt) => x
)
case object DebugModuleHartSelKey extends Field(DebugModuleHartSelFuncs())
class DebugExtTriggerOut (val nExtTriggers: Int) extends Bundle {
val req = Output(UInt(nExtTriggers.W))
val ack = Input(UInt(nExtTriggers.W))
}
class DebugExtTriggerIn (val nExtTriggers: Int) extends Bundle {
val req = Input(UInt(nExtTriggers.W))
val ack = Output(UInt(nExtTriggers.W))
}
class DebugExtTriggerIO () (implicit val p: Parameters) extends ParameterizedBundle()(p) {
val out = new DebugExtTriggerOut(p(DebugModuleKey).get.nExtTriggers)
val in = new DebugExtTriggerIn (p(DebugModuleKey).get.nExtTriggers)
}
class DebugAuthenticationIO () (implicit val p: Parameters) extends ParameterizedBundle()(p) {
val dmactive = Output(Bool())
val dmAuthWrite = Output(Bool())
val dmAuthRead = Output(Bool())
val dmAuthWdata = Output(UInt(32.W))
val dmAuthBusy = Input(Bool())
val dmAuthRdata = Input(UInt(32.W))
val dmAuthenticated = Input(Bool())
}
// *****************************************
// Module Interfaces
//
// *****************************************
/** Control signals for Inner, generated in Outer
* {{{
* run control: resumreq, ackhavereset, halt-on-reset mask
* hart select: hasel, hartsel and the hart array mask
* }}}
*/
class DebugInternalBundle (val nComponents: Int)(implicit val p: Parameters) extends ParameterizedBundle()(p) {
/** resume request */
val resumereq = Bool()
/** hart select */
val hartsel = UInt(10.W)
/** reset acknowledge */
val ackhavereset = Bool()
/** hart array enable */
val hasel = Bool()
/** hart array mask */
val hamask = Vec(nComponents, Bool())
/** halt-on-reset mask */
val hrmask = Vec(nComponents, Bool())
}
/** structure for top-level Debug Module signals which aren't the bus interfaces. */
class DebugCtrlBundle (nComponents: Int)(implicit val p: Parameters) extends ParameterizedBundle()(p) {
/** debug availability status for all harts */
val debugUnavail = Input(Vec(nComponents, Bool()))
/** reset signal
*
* for every part of the hardware platform,
* including every hart, except for the DM and any
* logic required to access the DM
*/
val ndreset = Output(Bool())
/** reset signal for the DM itself */
val dmactive = Output(Bool())
/** dmactive acknowlege */
val dmactiveAck = Input(Bool())
}
// *****************************************
// Debug Module
//
// *****************************************
/** Parameterized version of the Debug Module defined in the
* RISC-V Debug Specification
*
* DebugModule is a slave to two asynchronous masters:
* The Debug Bus (DMI) -- This is driven by an external debugger
*
* The System Bus -- This services requests from the cores. Generally
* this interface should only be active at the request
* of the debugger, but the Debug Module may also
* provide the default MTVEC since it is mapped
* to address 0x0.
*
* DebugModule is responsible for control registers and RAM, and
* Debug ROM. It runs partially off of the dmiClk (e.g. TCK) and
* the TL clock. Therefore, it is divided into "Outer" portion (running
* off dmiClock and dmiReset) and "Inner" (running off tl_clock and tl_reset).
* This allows DMCONTROL.haltreq, hartsel, hasel, hawindowsel, hawindow, dmactive,
* and ndreset to be modified even while the Core is in reset or not being clocked.
* Not all reads from the Debugger to the Debug Module will actually complete
* in these scenarios either, they will just block until tl_clock and tl_reset
* allow them to complete. This is not strictly necessary for
* proper debugger functionality.
*/
// Local reg mapper function : Notify when written, but give the value as well.
object WNotifyWire {
def apply(n: Int, value: UInt, set: Bool, name: String, desc: String) : RegField = {
RegField(n, 0.U, RegWriteFn((valid, data) => {
set := valid
value := data
true.B
}), Some(RegFieldDesc(name = name, desc = desc,
access = RegFieldAccessType.W)))
}
}
// Local reg mapper function : Notify when accessed either as read or write.
object RWNotify {
def apply (n: Int, rVal: UInt, wVal: UInt, rNotify: Bool, wNotify: Bool, desc: Option[RegFieldDesc] = None): RegField = {
RegField(n,
RegReadFn ((ready) => {rNotify := ready ; (true.B, rVal)}),
RegWriteFn((valid, data) => {
wNotify := valid
when (valid) {wVal := data}
true.B
}
), desc)
}
}
// Local reg mapper function : Notify with value when written, take read input as presented.
// This allows checking or correcting the write value before storing it in the register field.
object WNotifyVal {
def apply(n: Int, rVal: UInt, wVal: UInt, wNotify: Bool, desc: RegFieldDesc): RegField = {
RegField(n, rVal, RegWriteFn((valid, data) => {
wNotify := valid
wVal := data
true.B
}
), desc)
}
}
class TLDebugModuleOuter(device: Device)(implicit p: Parameters) extends LazyModule {
// For Shorter Register Names
import DMI_RegAddrs._
val cfg = p(DebugModuleKey).get
val intnode = IntNexusNode(
sourceFn = { _ => IntSourcePortParameters(Seq(IntSourceParameters(1, Seq(Resource(device, "int"))))) },
sinkFn = { _ => IntSinkPortParameters(Seq(IntSinkParameters())) },
outputRequiresInput = false)
val dmiNode = TLRegisterNode (
address = AddressSet.misaligned(DMI_DMCONTROL << 2, 4) ++
AddressSet.misaligned(DMI_HARTINFO << 2, 4) ++
AddressSet.misaligned(DMI_HAWINDOWSEL << 2, 4) ++
AddressSet.misaligned(DMI_HAWINDOW << 2, 4),
device = device,
beatBytes = 4,
executable = false
)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
require (intnode.edges.in.size == 0, "Debug Module does not accept interrupts")
val nComponents = intnode.out.size
def getNComponents = () => nComponents
val supportHartArray = cfg.supportHartArray && (nComponents > 1) // no hart array if only one hart
val io = IO(new Bundle {
/** structure for top-level Debug Module signals which aren't the bus interfaces. */
val ctrl = (new DebugCtrlBundle(nComponents))
/** control signals for Inner, generated in Outer */
val innerCtrl = new DecoupledIO(new DebugInternalBundle(nComponents))
/** debug interruption from Inner to Outer
*
* contains 2 type of debug interruption causes:
* - halt group
* - halt-on-reset
*/
val hgDebugInt = Input(Vec(nComponents, Bool()))
/** hart reset request to core */
val hartResetReq = cfg.hasHartResets.option(Output(Vec(nComponents, Bool())))
/** authentication support */
val dmAuthenticated = cfg.hasAuthentication.option(Input(Bool()))
})
val omRegMap = withReset(reset.asAsyncReset) {
// FIXME: Instead of casting reset to ensure it is Async, assert/require reset.Type == AsyncReset (when this feature is available)
val dmAuthenticated = io.dmAuthenticated.map( dma =>
ResetSynchronizerShiftReg(in=dma, sync=3, name=Some("dmAuthenticated_sync"))).getOrElse(true.B)
//----DMCONTROL (The whole point of 'Outer' is to maintain this register on dmiClock (e.g. TCK) domain, so that it
// can be written even if 'Inner' is not being clocked or is in reset. This allows halting
// harts while the rest of the system is in reset. It doesn't really allow any other
// register accesses, which will keep returning 'busy' to the debugger interface.
val DMCONTROLReset = WireInit(0.U.asTypeOf(new DMCONTROLFields()))
val DMCONTROLNxt = WireInit(0.U.asTypeOf(new DMCONTROLFields()))
val DMCONTROLReg = RegNext(next=DMCONTROLNxt, init=0.U.asTypeOf(DMCONTROLNxt)).suggestName("DMCONTROLReg")
val hartsel_mask = if (nComponents > 1) ((1 << p(MaxHartIdBits)) - 1).U else 0.U
val DMCONTROLWrData = WireInit(0.U.asTypeOf(new DMCONTROLFields()))
val dmactiveWrEn = WireInit(false.B)
val ndmresetWrEn = WireInit(false.B)
val clrresethaltreqWrEn = WireInit(false.B)
val setresethaltreqWrEn = WireInit(false.B)
val hartselloWrEn = WireInit(false.B)
val haselWrEn = WireInit(false.B)
val ackhaveresetWrEn = WireInit(false.B)
val hartresetWrEn = WireInit(false.B)
val resumereqWrEn = WireInit(false.B)
val haltreqWrEn = WireInit(false.B)
val dmactive = DMCONTROLReg.dmactive
DMCONTROLNxt := DMCONTROLReg
when (~dmactive) {
DMCONTROLNxt := DMCONTROLReset
} .otherwise {
when (dmAuthenticated && ndmresetWrEn) { DMCONTROLNxt.ndmreset := DMCONTROLWrData.ndmreset }
when (dmAuthenticated && hartselloWrEn) { DMCONTROLNxt.hartsello := DMCONTROLWrData.hartsello & hartsel_mask}
when (dmAuthenticated && haselWrEn) { DMCONTROLNxt.hasel := DMCONTROLWrData.hasel }
when (dmAuthenticated && hartresetWrEn) { DMCONTROLNxt.hartreset := DMCONTROLWrData.hartreset }
when (dmAuthenticated && haltreqWrEn) { DMCONTROLNxt.haltreq := DMCONTROLWrData.haltreq }
}
// Put this last to override its own effects.
when (dmactiveWrEn) {
DMCONTROLNxt.dmactive := DMCONTROLWrData.dmactive
}
//----HARTINFO
// DATA registers are mapped to memory. The dataaddr field of HARTINFO has only
// 12 bits and assumes the DM base is 0. If not at 0, then HARTINFO reads as 0
// (implying nonexistence according to the Debug Spec).
val HARTINFORdData = WireInit(0.U.asTypeOf(new HARTINFOFields()))
if (cfg.atzero) when (dmAuthenticated) {
HARTINFORdData.dataaccess := true.B
HARTINFORdData.datasize := cfg.nAbstractDataWords.U
HARTINFORdData.dataaddr := DsbRegAddrs.DATA.U
HARTINFORdData.nscratch := cfg.nScratch.U
}
//--------------------------------------------------------------
// Hart array mask and window
// hamask is hart array mask(1 bit per component), which doesn't include the hart selected by dmcontrol.hartsello
// HAWINDOWSEL selects a 32-bit slice of HAMASK to be visible for read/write in HAWINDOW
//--------------------------------------------------------------
val hamask = WireInit(VecInit(Seq.fill(nComponents) {false.B} ))
def haWindowSize = 32
// The following need to be declared even if supportHartArray is false due to reference
// at compile time by dmiNode.regmap
val HAWINDOWSELWrData = WireInit(0.U.asTypeOf(new HAWINDOWSELFields()))
val HAWINDOWSELWrEn = WireInit(false.B)
val HAWINDOWRdData = WireInit(0.U.asTypeOf(new HAWINDOWFields()))
val HAWINDOWWrData = WireInit(0.U.asTypeOf(new HAWINDOWFields()))
val HAWINDOWWrEn = WireInit(false.B)
/** whether the hart is selected */
def hartSelected(hart: Int): Bool = {
((io.innerCtrl.bits.hartsel === hart.U) ||
(if (supportHartArray) io.innerCtrl.bits.hasel && io.innerCtrl.bits.hamask(hart) else false.B))
}
val HAWINDOWSELNxt = WireInit(0.U.asTypeOf(new HAWINDOWSELFields()))
val HAWINDOWSELReg = RegNext(next=HAWINDOWSELNxt, init=0.U.asTypeOf(HAWINDOWSELNxt))
if (supportHartArray) {
val HAWINDOWSELReset = WireInit(0.U.asTypeOf(new HAWINDOWSELFields()))
HAWINDOWSELNxt := HAWINDOWSELReg
when (~dmactive || ~dmAuthenticated) {
HAWINDOWSELNxt := HAWINDOWSELReset
} .otherwise {
when (HAWINDOWSELWrEn) {
// Unneeded upper bits of HAWINDOWSEL are tied to 0. Entire register is 0 if all harts fit in one window
if (nComponents > haWindowSize) {
HAWINDOWSELNxt.hawindowsel := HAWINDOWSELWrData.hawindowsel & ((1 << (log2Up(nComponents) - 5)) - 1).U
} else {
HAWINDOWSELNxt.hawindowsel := 0.U
}
}
}
val numHAMASKSlices = ((nComponents - 1)/haWindowSize)+1
HAWINDOWRdData.maskdata := 0.U // default, overridden below
// for each slice,use a hamaskReg to store the selection info
for (ii <- 0 until numHAMASKSlices) {
val sliceMask = if (nComponents > ((ii*haWindowSize) + haWindowSize-1)) (BigInt(1) << haWindowSize) - 1 // All harts in this slice exist
else (BigInt(1)<<(nComponents - (ii*haWindowSize))) - 1 // Partial last slice
val HAMASKRst = WireInit(0.U.asTypeOf(new HAWINDOWFields()))
val HAMASKNxt = WireInit(0.U.asTypeOf(new HAWINDOWFields()))
val HAMASKReg = RegNext(next=HAMASKNxt, init=0.U.asTypeOf(HAMASKNxt))
when (ii.U === HAWINDOWSELReg.hawindowsel) {
HAWINDOWRdData.maskdata := HAMASKReg.asUInt & sliceMask.U
}
HAMASKNxt.maskdata := HAMASKReg.asUInt
when (~dmactive || ~dmAuthenticated) {
HAMASKNxt := HAMASKRst
}.otherwise {
when (HAWINDOWWrEn && (ii.U === HAWINDOWSELReg.hawindowsel)) {
HAMASKNxt.maskdata := HAWINDOWWrData.maskdata
}
}
// drive each slice of hamask with stored HAMASKReg or with new value being written
for (jj <- 0 until haWindowSize) {
if (((ii*haWindowSize) + jj) < nComponents) {
val tempWrData = HAWINDOWWrData.maskdata.asBools
val tempMaskReg = HAMASKReg.asUInt.asBools
when (HAWINDOWWrEn && (ii.U === HAWINDOWSELReg.hawindowsel)) {
hamask(ii*haWindowSize + jj) := tempWrData(jj)
}.otherwise {
hamask(ii*haWindowSize + jj) := tempMaskReg(jj)
}
}
}
}
}
//--------------------------------------------------------------
// Halt-on-reset
// hrmaskReg is current set of harts that should halt-on-reset
// Reset state (dmactive=0) is all zeroes
// Bits are set by writing 1 to DMCONTROL.setresethaltreq
// Bits are cleared by writing 1 to DMCONTROL.clrresethaltreq
// Spec says if both are 1, then clrresethaltreq is executed
// hrmask is the halt-on-reset mask which will be sent to inner
//--------------------------------------------------------------
val hrmask = Wire(Vec(nComponents, Bool()))
val hrmaskNxt = Wire(Vec(nComponents, Bool()))
val hrmaskReg = RegNext(next=hrmaskNxt, init=0.U.asTypeOf(hrmaskNxt)).suggestName("hrmaskReg")
hrmaskNxt := hrmaskReg
for (component <- 0 until nComponents) {
when (~dmactive || ~dmAuthenticated) {
hrmaskNxt(component) := false.B
}.elsewhen (clrresethaltreqWrEn && DMCONTROLWrData.clrresethaltreq && hartSelected(component)) {
hrmaskNxt(component) := false.B
}.elsewhen (setresethaltreqWrEn && DMCONTROLWrData.setresethaltreq && hartSelected(component)) {
hrmaskNxt(component) := true.B
}
}
hrmask := hrmaskNxt
val dmControlRegFields = RegFieldGroup("dmcontrol", Some("debug module control register"), Seq(
WNotifyVal(1, DMCONTROLReg.dmactive & io.ctrl.dmactiveAck, DMCONTROLWrData.dmactive, dmactiveWrEn,
RegFieldDesc("dmactive", "debug module active", reset=Some(0))),
WNotifyVal(1, DMCONTROLReg.ndmreset, DMCONTROLWrData.ndmreset, ndmresetWrEn,
RegFieldDesc("ndmreset", "debug module reset output", reset=Some(0))),
WNotifyVal(1, 0.U, DMCONTROLWrData.clrresethaltreq, clrresethaltreqWrEn,
RegFieldDesc("clrresethaltreq", "clear reset halt request", reset=Some(0), access=RegFieldAccessType.W)),
WNotifyVal(1, 0.U, DMCONTROLWrData.setresethaltreq, setresethaltreqWrEn,
RegFieldDesc("setresethaltreq", "set reset halt request", reset=Some(0), access=RegFieldAccessType.W)),
RegField(12),
if (nComponents > 1) WNotifyVal(p(MaxHartIdBits),
DMCONTROLReg.hartsello, DMCONTROLWrData.hartsello, hartselloWrEn,
RegFieldDesc("hartsello", "hart select low", reset=Some(0)))
else RegField(1),
if (nComponents > 1) RegField(10-p(MaxHartIdBits))
else RegField(9),
if (supportHartArray)
WNotifyVal(1, DMCONTROLReg.hasel, DMCONTROLWrData.hasel, haselWrEn,
RegFieldDesc("hasel", "hart array select", reset=Some(0)))
else RegField(1),
RegField(1),
WNotifyVal(1, 0.U, DMCONTROLWrData.ackhavereset, ackhaveresetWrEn,
RegFieldDesc("ackhavereset", "acknowledge reset", reset=Some(0), access=RegFieldAccessType.W)),
if (cfg.hasHartResets)
WNotifyVal(1, DMCONTROLReg.hartreset, DMCONTROLWrData.hartreset, hartresetWrEn,
RegFieldDesc("hartreset", "hart reset request", reset=Some(0)))
else RegField(1),
WNotifyVal(1, 0.U, DMCONTROLWrData.resumereq, resumereqWrEn,
RegFieldDesc("resumereq", "resume request", reset=Some(0), access=RegFieldAccessType.W)),
WNotifyVal(1, DMCONTROLReg.haltreq, DMCONTROLWrData.haltreq, haltreqWrEn, // Spec says W, but maintaining previous behavior
RegFieldDesc("haltreq", "halt request", reset=Some(0)))
))
val hartinfoRegFields = RegFieldGroup("dmi_hartinfo", Some("hart information"), Seq(
RegField.r(12, HARTINFORdData.dataaddr, RegFieldDesc("dataaddr", "data address", reset=Some(if (cfg.atzero) DsbRegAddrs.DATA else 0))),
RegField.r(4, HARTINFORdData.datasize, RegFieldDesc("datasize", "number of DATA registers", reset=Some(if (cfg.atzero) cfg.nAbstractDataWords else 0))),
RegField.r(1, HARTINFORdData.dataaccess, RegFieldDesc("dataaccess", "data access type", reset=Some(if (cfg.atzero) 1 else 0))),
RegField(3),
RegField.r(4, HARTINFORdData.nscratch, RegFieldDesc("nscratch", "number of scratch registers", reset=Some(if (cfg.atzero) cfg.nScratch else 0)))
))
//--------------------------------------------------------------
// DMI register decoder for Outer
//--------------------------------------------------------------
// regmap addresses are byte offsets from lowest address
def DMI_DMCONTROL_OFFSET = 0
def DMI_HARTINFO_OFFSET = ((DMI_HARTINFO - DMI_DMCONTROL) << 2)
def DMI_HAWINDOWSEL_OFFSET = ((DMI_HAWINDOWSEL - DMI_DMCONTROL) << 2)
def DMI_HAWINDOW_OFFSET = ((DMI_HAWINDOW - DMI_DMCONTROL) << 2)
val omRegMap = dmiNode.regmap(
DMI_DMCONTROL_OFFSET -> dmControlRegFields,
DMI_HARTINFO_OFFSET -> hartinfoRegFields,
DMI_HAWINDOWSEL_OFFSET -> (if (supportHartArray && (nComponents > 32)) Seq(
WNotifyVal(log2Up(nComponents)-5, HAWINDOWSELReg.hawindowsel, HAWINDOWSELWrData.hawindowsel, HAWINDOWSELWrEn,
RegFieldDesc("hawindowsel", "hart array window select", reset=Some(0)))) else Nil),
DMI_HAWINDOW_OFFSET -> (if (supportHartArray) Seq(
WNotifyVal(if (nComponents > 31) 32 else nComponents, HAWINDOWRdData.maskdata, HAWINDOWWrData.maskdata, HAWINDOWWrEn,
RegFieldDesc("hawindow", "hart array window", reset=Some(0), volatile=(nComponents > 32)))) else Nil)
)
//--------------------------------------------------------------
// Interrupt Registers
//--------------------------------------------------------------
val debugIntNxt = WireInit(VecInit(Seq.fill(nComponents) {false.B} ))
val debugIntRegs = RegNext(next=debugIntNxt, init=0.U.asTypeOf(debugIntNxt)).suggestName("debugIntRegs")
debugIntNxt := debugIntRegs
val (intnode_out, _) = intnode.out.unzip
for (component <- 0 until nComponents) {
intnode_out(component)(0) := debugIntRegs(component) | io.hgDebugInt(component)
}
// sends debug interruption to Core when dmcs.haltreq is set,
for (component <- 0 until nComponents) {
when (~dmactive || ~dmAuthenticated) {
debugIntNxt(component) := false.B
}. otherwise {
when (haltreqWrEn && ((DMCONTROLWrData.hartsello === component.U)
|| (if (supportHartArray) DMCONTROLWrData.hasel && hamask(component) else false.B))) {
debugIntNxt(component) := DMCONTROLWrData.haltreq
}
}
}
// Halt request registers are set & cleared by writes to DMCONTROL.haltreq
// resumereq also causes the core to execute a 'dret',
// so resumereq is passed through to Inner.
// hartsel/hasel/hamask must also be used by the DebugModule state machine,
// so it is passed to Inner.
// These registers ensure that requests to dmInner are not lost if inner clock isn't running or requests occur too close together.
// If the innerCtrl async queue is not ready, the notification will be posted and held until ready is received.
// Additional notifications that occur while one is already waiting update the pending data so that the last value written is sent.
// Volatile events resumereq and ackhavereset are registered when they occur and remain pending until ready is received.
val innerCtrlValid = Wire(Bool())
val innerCtrlValidReg = RegInit(false.B).suggestName("innerCtrlValidReg")
val innerCtrlResumeReqReg = RegInit(false.B).suggestName("innerCtrlResumeReqReg")
val innerCtrlAckHaveResetReg = RegInit(false.B).suggestName("innerCtrlAckHaveResetReg")
innerCtrlValid := hartselloWrEn | resumereqWrEn | ackhaveresetWrEn | setresethaltreqWrEn | clrresethaltreqWrEn | haselWrEn |
(HAWINDOWWrEn & supportHartArray.B)
innerCtrlValidReg := io.innerCtrl.valid & ~io.innerCtrl.ready // Hold innerctrl request until the async queue accepts it
innerCtrlResumeReqReg := io.innerCtrl.bits.resumereq & ~io.innerCtrl.ready // Hold resumereq until accepted
innerCtrlAckHaveResetReg := io.innerCtrl.bits.ackhavereset & ~io.innerCtrl.ready // Hold ackhavereset until accepted
io.innerCtrl.valid := innerCtrlValid | innerCtrlValidReg
io.innerCtrl.bits.hartsel := Mux(hartselloWrEn, DMCONTROLWrData.hartsello, DMCONTROLReg.hartsello)
io.innerCtrl.bits.resumereq := (resumereqWrEn & DMCONTROLWrData.resumereq) | innerCtrlResumeReqReg
io.innerCtrl.bits.ackhavereset := (ackhaveresetWrEn & DMCONTROLWrData.ackhavereset) | innerCtrlAckHaveResetReg
io.innerCtrl.bits.hrmask := hrmask
if (supportHartArray) {
io.innerCtrl.bits.hasel := Mux(haselWrEn, DMCONTROLWrData.hasel, DMCONTROLReg.hasel)
io.innerCtrl.bits.hamask := hamask
} else {
io.innerCtrl.bits.hasel := DontCare
io.innerCtrl.bits.hamask := DontCare
}
io.ctrl.ndreset := DMCONTROLReg.ndmreset
io.ctrl.dmactive := DMCONTROLReg.dmactive
// hart reset mechanism implementation
if (cfg.hasHartResets) {
val hartResetNxt = Wire(Vec(nComponents, Bool()))
val hartResetReg = RegNext(next=hartResetNxt, init=0.U.asTypeOf(hartResetNxt))
for (component <- 0 until nComponents) {
hartResetNxt(component) := DMCONTROLReg.hartreset & hartSelected(component)
io.hartResetReq.get(component) := hartResetReg(component)
}
}
omRegMap // FIXME: Remove this when withReset is removed
}}
}
// wrap a Outer with a DMIToTL, derived by dmi clock & reset
class TLDebugModuleOuterAsync(device: Device)(implicit p: Parameters) extends LazyModule {
val cfg = p(DebugModuleKey).get
val dmiXbar = LazyModule (new TLXbar(nameSuffix = Some("dmixbar")))
val dmi2tlOpt = (!p(ExportDebug).apb).option({
val dmi2tl = LazyModule(new DMIToTL())
dmiXbar.node := dmi2tl.node
dmi2tl
})
val apbNodeOpt = p(ExportDebug).apb.option({
val apb2tl = LazyModule(new APBToTL())
val apb2tlBuffer = LazyModule(new TLBuffer(BufferParams.pipe))
val dmTopAddr = (1 << cfg.nDMIAddrSize) << 2
val tlErrorParams = DevNullParams(AddressSet.misaligned(dmTopAddr, APBDebugConsts.apbDebugRegBase-dmTopAddr), maxAtomic=0, maxTransfer=4)
val tlError = LazyModule(new TLError(tlErrorParams, buffer=false))
val apbXbar = LazyModule(new APBFanout())
val apbRegs = LazyModule(new APBDebugRegisters())
apbRegs.node := apbXbar.node
apb2tl.node := apbXbar.node
apb2tlBuffer.node := apb2tl.node
dmiXbar.node := apb2tlBuffer.node
tlError.node := dmiXbar.node
apbXbar.node
})
val dmOuter = LazyModule( new TLDebugModuleOuter(device))
val intnode = IntSyncIdentityNode()
intnode :*= IntSyncCrossingSource(alreadyRegistered = true) :*= dmOuter.intnode
val dmiBypass = LazyModule(new TLBusBypass(beatBytes=4, bufferError=false, maxAtomic=0, maxTransfer=4))
val dmiInnerNode = TLAsyncCrossingSource() := dmiBypass.node := dmiXbar.node
dmOuter.dmiNode := dmiXbar.node
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
val nComponents = dmOuter.intnode.edges.out.size
val io = IO(new Bundle {
val dmi_clock = Input(Clock())
val dmi_reset = Input(Reset())
/** Debug Module Interface bewteen DM and DTM
*
* The DTM provides access to one or more Debug Modules (DMs) using DMI
*/
val dmi = (!p(ExportDebug).apb).option(Flipped(new DMIIO()(p)))
// Optional APB Interface is fully diplomatic so is not listed here.
val ctrl = new DebugCtrlBundle(nComponents)
/** conrol signals for Inner, generated in Outer */
val innerCtrl = new AsyncBundle(new DebugInternalBundle(nComponents), AsyncQueueParams.singleton(safe=cfg.crossingHasSafeReset))
/** debug interruption generated in Inner */
val hgDebugInt = Input(Vec(nComponents, Bool()))
/** hart reset request to core */
val hartResetReq = p(DebugModuleKey).get.hasHartResets.option(Output(Vec(nComponents, Bool())))
/** Authentication signal from core */
val dmAuthenticated = p(DebugModuleKey).get.hasAuthentication.option(Input(Bool()))
})
val rf_reset = IO(Input(Reset())) // RF transform
childClock := io.dmi_clock
childReset := io.dmi_reset
override def provideImplicitClockToLazyChildren = true
withClockAndReset(childClock, childReset) {
dmi2tlOpt.foreach { _.module.io.dmi <> io.dmi.get }
val dmactiveAck = AsyncResetSynchronizerShiftReg(in=io.ctrl.dmactiveAck, sync=3, name=Some("dmactiveAckSync"))
dmiBypass.module.io.bypass := ~io.ctrl.dmactive | ~dmactiveAck
io.ctrl <> dmOuter.module.io.ctrl
dmOuter.module.io.ctrl.dmactiveAck := dmactiveAck // send synced version down to dmOuter
io.innerCtrl <> ToAsyncBundle(dmOuter.module.io.innerCtrl, AsyncQueueParams.singleton(safe=cfg.crossingHasSafeReset))
dmOuter.module.io.hgDebugInt := io.hgDebugInt
io.hartResetReq.foreach { x => dmOuter.module.io.hartResetReq.foreach {y => x := y}}
io.dmAuthenticated.foreach { x => dmOuter.module.io.dmAuthenticated.foreach { y => y := x}}
}
}
}
class TLDebugModuleInner(device: Device, getNComponents: () => Int, beatBytes: Int)(implicit p: Parameters) extends LazyModule
{
// For Shorter Register Names
import DMI_RegAddrs._
val cfg = p(DebugModuleKey).get
def getCfg = () => cfg
val dmTopAddr = (1 << cfg.nDMIAddrSize) << 2
/** dmiNode address set */
val dmiNode = TLRegisterNode(
// Address is range 0 to 0x1FF except DMCONTROL, HARTINFO, HAWINDOWSEL, HAWINDOW which are handled by Outer
address = AddressSet.misaligned(0, DMI_DMCONTROL << 2) ++
AddressSet.misaligned((DMI_DMCONTROL + 1) << 2, ((DMI_HARTINFO << 2) - ((DMI_DMCONTROL + 1) << 2))) ++
AddressSet.misaligned((DMI_HARTINFO + 1) << 2, ((DMI_HAWINDOWSEL << 2) - ((DMI_HARTINFO + 1) << 2))) ++
AddressSet.misaligned((DMI_HAWINDOW + 1) << 2, (dmTopAddr - ((DMI_HAWINDOW + 1) << 2))),
device = device,
beatBytes = 4,
executable = false
)
val tlNode = TLRegisterNode(
address=Seq(cfg.address),
device=device,
beatBytes=beatBytes,
executable=true
)
val sb2tlOpt = cfg.hasBusMaster.option(LazyModule(new SBToTL()))
// If we want to support custom registers read through Abstract Commands,
// provide a place to bring them into the debug module. What this connects
// to is up to the implementation.
val customNode = new DebugCustomSink()
lazy val module = new Impl
class Impl extends LazyModuleImp(this){
val nComponents = getNComponents()
Annotated.params(this, cfg)
val supportHartArray = cfg.supportHartArray & (nComponents > 1)
val nExtTriggers = cfg.nExtTriggers
val nHaltGroups = if ((nComponents > 1) | (nExtTriggers > 0)) cfg.nHaltGroups
else 0 // no halt groups possible if single hart with no external triggers
val hartSelFuncs = if (getNComponents() > 1) p(DebugModuleHartSelKey) else DebugModuleHartSelFuncs(
hartIdToHartSel = (x) => 0.U,
hartSelToHartId = (x) => x
)
val io = IO(new Bundle {
/** dm reset signal passed in from Outer */
val dmactive = Input(Bool())
/** conrol signals for Inner
*
* it's generated by Outer and comes in
*/
val innerCtrl = Flipped(new DecoupledIO(new DebugInternalBundle(nComponents)))
/** debug unavail signal passed in from Outer*/
val debugUnavail = Input(Vec(nComponents, Bool()))
/** debug interruption from Inner to Outer
*
* contain 2 type of debug interruption causes:
* - halt group
* - halt-on-reset
*/
val hgDebugInt = Output(Vec(nComponents, Bool()))
/** interface for trigger */
val extTrigger = (nExtTriggers > 0).option(new DebugExtTriggerIO())
/** vector to indicate which hart is in reset
*
* dm receives it from core and sends it to Inner
*/
val hartIsInReset = Input(Vec(nComponents, Bool()))
val tl_clock = Input(Clock())
val tl_reset = Input(Reset())
/** Debug Authentication signals from core */
val auth = cfg.hasAuthentication.option(new DebugAuthenticationIO())
})
sb2tlOpt.map { sb =>
sb.module.clock := io.tl_clock
sb.module.reset := io.tl_reset
sb.module.rf_reset := io.tl_reset
}
//--------------------------------------------------------------
// Import constants for shorter variable names
//--------------------------------------------------------------
import DMI_RegAddrs._
import DsbRegAddrs._
import DsbBusConsts._
//--------------------------------------------------------------
// Sanity Check Configuration For this implementation.
//--------------------------------------------------------------
require (cfg.supportQuickAccess == false, "No Quick Access support yet")
require ((nHaltGroups > 0) || (nExtTriggers == 0), "External triggers require at least 1 halt group")
//--------------------------------------------------------------
// Register & Wire Declarations (which need to be pre-declared)
//--------------------------------------------------------------
// run control regs: tracking all the harts
// implements: see implementation-specific bits part
/** all harts halted status */
val haltedBitRegs = Reg(UInt(nComponents.W))
/** all harts resume request status */
val resumeReqRegs = Reg(UInt(nComponents.W))
/** all harts have reset status */
val haveResetBitRegs = Reg(UInt(nComponents.W))
// default is 1,after resume, resumeAcks get 0
/** all harts resume ack status */
val resumeAcks = Wire(UInt(nComponents.W))
// --- regmapper outputs
// hart state Id and En
// in Hart Bus Access ROM
val hartHaltedWrEn = Wire(Bool())
val hartHaltedId = Wire(UInt(sbIdWidth.W))
val hartGoingWrEn = Wire(Bool())
val hartGoingId = Wire(UInt(sbIdWidth.W))
val hartResumingWrEn = Wire(Bool())
val hartResumingId = Wire(UInt(sbIdWidth.W))
val hartExceptionWrEn = Wire(Bool())
val hartExceptionId = Wire(UInt(sbIdWidth.W))
// progbuf and abstract data: byte-addressable control logic
// AccessLegal is set only when state = waiting
// RdEn and WrEnMaybe : contrl signal drived by DMI bus
val dmiProgramBufferRdEn = WireInit(VecInit(Seq.fill(cfg.nProgramBufferWords * 4) {false.B} ))
val dmiProgramBufferAccessLegal = WireInit(false.B)
val dmiProgramBufferWrEnMaybe = WireInit(VecInit(Seq.fill(cfg.nProgramBufferWords * 4) {false.B} ))
val dmiAbstractDataRdEn = WireInit(VecInit(Seq.fill(cfg.nAbstractDataWords * 4) {false.B} ))
val dmiAbstractDataAccessLegal = WireInit(false.B)
val dmiAbstractDataWrEnMaybe = WireInit(VecInit(Seq.fill(cfg.nAbstractDataWords * 4) {false.B} ))
//--------------------------------------------------------------
// Registers coming from 'CONTROL' in Outer
//--------------------------------------------------------------
val dmAuthenticated = io.auth.map(a => a.dmAuthenticated).getOrElse(true.B)
val selectedHartReg = Reg(UInt(p(MaxHartIdBits).W))
// hamaskFull is a vector of all selected harts including hartsel, whether or not supportHartArray is true
val hamaskFull = WireInit(VecInit(Seq.fill(nComponents) {false.B} ))
if (nComponents > 1) {
when (~io.dmactive) {
selectedHartReg := 0.U
}.elsewhen (io.innerCtrl.fire){
selectedHartReg := io.innerCtrl.bits.hartsel
}
}
if (supportHartArray) {
val hamaskZero = WireInit(VecInit(Seq.fill(nComponents) {false.B} ))
val hamaskReg = Reg(Vec(nComponents, Bool()))
when (~io.dmactive || ~dmAuthenticated) {
hamaskReg := hamaskZero
}.elsewhen (io.innerCtrl.fire){
hamaskReg := Mux(io.innerCtrl.bits.hasel, io.innerCtrl.bits.hamask, hamaskZero)
}
hamaskFull := hamaskReg
}
// Outer.hamask doesn't consider the hart selected by dmcontrol.hartsello,
// so append it here
when (selectedHartReg < nComponents.U) {
hamaskFull(if (nComponents == 1) 0.U(0.W) else selectedHartReg) := true.B
}
io.innerCtrl.ready := true.B
// Construct a Vec from io.innerCtrl fields indicating whether each hart is being selected in this write
// A hart may be selected by hartsel field or by hart array
val hamaskWrSel = WireInit(VecInit(Seq.fill(nComponents) {false.B} ))
for (component <- 0 until nComponents ) {
hamaskWrSel(component) := ((io.innerCtrl.bits.hartsel === component.U) ||
(if (supportHartArray) io.innerCtrl.bits.hasel && io.innerCtrl.bits.hamask(component) else false.B))
}
//-------------------------------------
// Halt-on-reset logic
// hrmask is set in dmOuter and passed in
// Debug interrupt is generated when a reset occurs whose corresponding hrmask bit is set
// Debug interrupt is maintained until the hart enters halted state
//-------------------------------------
val hrReset = WireInit(VecInit(Seq.fill(nComponents) { false.B } ))
val hrDebugInt = Wire(Vec(nComponents, Bool()))
val hrmaskReg = RegInit(hrReset)
val hartIsInResetSync = Wire(Vec(nComponents, Bool()))
for (component <- 0 until nComponents) {
hartIsInResetSync(component) := AsyncResetSynchronizerShiftReg(io.hartIsInReset(component), 3, Some(s"debug_hartReset_$component"))
}
when (~io.dmactive || ~dmAuthenticated) {
hrmaskReg := hrReset
}.elsewhen (io.innerCtrl.fire){
hrmaskReg := io.innerCtrl.bits.hrmask
}
withReset(reset.asAsyncReset) { // ensure interrupt requests are negated at first clock edge
val hrDebugIntReg = RegInit(VecInit(Seq.fill(nComponents) { false.B } ))
when (~io.dmactive || ~dmAuthenticated) {
hrDebugIntReg := hrReset
}.otherwise {
hrDebugIntReg := hrmaskReg &
(hartIsInResetSync | // set debugInt during reset
(hrDebugIntReg & ~(haltedBitRegs.asBools))) // maintain until core halts
}
hrDebugInt := hrDebugIntReg
}
//--------------------------------------------------------------
// DMI Registers
//--------------------------------------------------------------
//----DMSTATUS
val DMSTATUSRdData = WireInit(0.U.asTypeOf(new DMSTATUSFields()))
DMSTATUSRdData.authenticated := dmAuthenticated
DMSTATUSRdData.version := 2.U // Version 0.13
io.auth.map(a => DMSTATUSRdData.authbusy := a.dmAuthBusy)
val resumereq = io.innerCtrl.fire && io.innerCtrl.bits.resumereq
when (dmAuthenticated) {
DMSTATUSRdData.hasresethaltreq := true.B
DMSTATUSRdData.anynonexistent := (selectedHartReg >= nComponents.U) // only hartsel can be nonexistent
// all harts nonexistent if hartsel is out of range and there are no harts selected in the hart array
DMSTATUSRdData.allnonexistent := (selectedHartReg >= nComponents.U) & (~hamaskFull.reduce(_ | _))
when (~DMSTATUSRdData.allnonexistent) { // if no existent harts selected, all other status is false
DMSTATUSRdData.anyunavail := (io.debugUnavail & hamaskFull).reduce(_ | _)
DMSTATUSRdData.anyhalted := ((~io.debugUnavail & (haltedBitRegs.asBools)) & hamaskFull).reduce(_ | _)
DMSTATUSRdData.anyrunning := ((~io.debugUnavail & ~(haltedBitRegs.asBools)) & hamaskFull).reduce(_ | _)
DMSTATUSRdData.anyhavereset := (haveResetBitRegs.asBools & hamaskFull).reduce(_ | _)
DMSTATUSRdData.anyresumeack := (resumeAcks.asBools & hamaskFull).reduce(_ | _)
when (~DMSTATUSRdData.anynonexistent) { // if one hart is nonexistent, no 'all' status is set
DMSTATUSRdData.allunavail := (io.debugUnavail | ~hamaskFull).reduce(_ & _)
DMSTATUSRdData.allhalted := ((~io.debugUnavail & (haltedBitRegs.asBools)) | ~hamaskFull).reduce(_ & _)
DMSTATUSRdData.allrunning := ((~io.debugUnavail & ~(haltedBitRegs.asBools)) | ~hamaskFull).reduce(_ & _)
DMSTATUSRdData.allhavereset := (haveResetBitRegs.asBools | ~hamaskFull).reduce(_ & _)
DMSTATUSRdData.allresumeack := (resumeAcks.asBools | ~hamaskFull).reduce(_ & _)
}
}
//TODO
DMSTATUSRdData.confstrptrvalid := false.B
DMSTATUSRdData.impebreak := (cfg.hasImplicitEbreak).B
}
when(~io.dmactive || ~dmAuthenticated) {
haveResetBitRegs := 0.U
}.otherwise {
when (io.innerCtrl.fire && io.innerCtrl.bits.ackhavereset) {
haveResetBitRegs := (haveResetBitRegs & (~(hamaskWrSel.asUInt))) | hartIsInResetSync.asUInt
}.otherwise {
haveResetBitRegs := haveResetBitRegs | hartIsInResetSync.asUInt
}
}
//----DMCS2 (Halt Groups)
val DMCS2RdData = WireInit(0.U.asTypeOf(new DMCS2Fields()))
val DMCS2WrData = WireInit(0.U.asTypeOf(new DMCS2Fields()))
val hgselectWrEn = WireInit(false.B)
val hgwriteWrEn = WireInit(false.B)
val haltgroupWrEn = WireInit(false.B)
val exttriggerWrEn = WireInit(false.B)
val hgDebugInt = WireInit(VecInit(Seq.fill(nComponents) {false.B} ))
if (nHaltGroups > 0) withReset (reset.asAsyncReset) { // async reset ensures triggers don't falsely fire during startup
val hgBits = log2Up(nHaltGroups)
// hgParticipate: Each entry indicates which hg that entity belongs to (1 to nHartGroups). 0 means no hg assigned.
val hgParticipateHart = RegInit(VecInit(Seq.fill(nComponents)(0.U(hgBits.W))))
val hgParticipateTrig = if (nExtTriggers > 0) RegInit(VecInit(Seq.fill(nExtTriggers)(0.U(hgBits.W)))) else Nil
// assign group index to current seledcted harts
for (component <- 0 until nComponents) {
when (~io.dmactive || ~dmAuthenticated) {
hgParticipateHart(component) := 0.U
}.otherwise {
when (haltgroupWrEn & DMCS2WrData.hgwrite & ~DMCS2WrData.hgselect &
hamaskFull(component) & (DMCS2WrData.haltgroup <= nHaltGroups.U)) {
hgParticipateHart(component) := DMCS2WrData.haltgroup
}
}
}
DMCS2RdData.haltgroup := hgParticipateHart(if (nComponents == 1) 0.U(0.W) else selectedHartReg)
if (nExtTriggers > 0) {
val hgSelect = Reg(Bool())
when (~io.dmactive || ~dmAuthenticated) {
hgSelect := false.B
}.otherwise {
when (hgselectWrEn) {
hgSelect := DMCS2WrData.hgselect
}
}
// assign group index to trigger
for (trigger <- 0 until nExtTriggers) {
when (~io.dmactive || ~dmAuthenticated) {
hgParticipateTrig(trigger) := 0.U
}.otherwise {
when (haltgroupWrEn & DMCS2WrData.hgwrite & DMCS2WrData.hgselect &
(DMCS2WrData.exttrigger === trigger.U) & (DMCS2WrData.haltgroup <= nHaltGroups.U)) {
hgParticipateTrig(trigger) := DMCS2WrData.haltgroup
}
}
}
DMCS2RdData.hgselect := hgSelect
when (hgSelect) {
DMCS2RdData.haltgroup := hgParticipateTrig(0)
}
// If there is only 1 ext trigger, then the exttrigger field is fixed at 0
// Otherwise, instantiate a register with only the number of bits required
if (nExtTriggers > 1) {
val trigBits = log2Up(nExtTriggers-1)
val hgExtTrigger = Reg(UInt(trigBits.W))
when (~io.dmactive || ~dmAuthenticated) {
hgExtTrigger := 0.U
}.otherwise {
when (exttriggerWrEn & (DMCS2WrData.exttrigger < nExtTriggers.U)) {
hgExtTrigger := DMCS2WrData.exttrigger
}
}
DMCS2RdData.exttrigger := hgExtTrigger
when (hgSelect) {
DMCS2RdData.haltgroup := hgParticipateTrig(hgExtTrigger)
}
}
}
// Halt group state machine
// IDLE: Go to FIRED when any hart in this hg writes to HALTED while its HaltedBitRegs=0
// or when any trigin assigned to this hg occurs
// FIRED: Back to IDLE when all harts in this hg have set their haltedBitRegs
// and all trig out in this hg have been acknowledged
val hgFired = RegInit (VecInit(Seq.fill(nHaltGroups+1) {false.B} ))
val hgHartFiring = WireInit(VecInit(Seq.fill(nHaltGroups+1) {false.B} )) // which hg's are firing due to hart halting
val hgTrigFiring = WireInit(VecInit(Seq.fill(nHaltGroups+1) {false.B} )) // which hg's are firing due to trig in
val hgHartsAllHalted = WireInit(VecInit(Seq.fill(nHaltGroups+1) {false.B} )) // in which hg's have all harts halted
val hgTrigsAllAcked = WireInit(VecInit(Seq.fill(nHaltGroups+1) { true.B} )) // in which hg's have all trigouts been acked
io.extTrigger.foreach {extTrigger =>
val extTriggerInReq = Wire(Vec(nExtTriggers, Bool()))
val extTriggerOutAck = Wire(Vec(nExtTriggers, Bool()))
extTriggerInReq := extTrigger.in.req.asBools
extTriggerOutAck := extTrigger.out.ack.asBools
val trigInReq = ResetSynchronizerShiftReg(in=extTriggerInReq, sync=3, name=Some("dm_extTriggerInReqSync"))
val trigOutAck = ResetSynchronizerShiftReg(in=extTriggerOutAck, sync=3, name=Some("dm_extTriggerOutAckSync"))
for (hg <- 1 to nHaltGroups) {
hgTrigFiring(hg) := (trigInReq & ~RegNext(trigInReq) & hgParticipateTrig.map(_ === hg.U)).reduce(_ | _)
hgTrigsAllAcked(hg) := (trigOutAck | hgParticipateTrig.map(_ =/= hg.U)).reduce(_ & _)
}
extTrigger.in.ack := trigInReq.asUInt
}
for (hg <- 1 to nHaltGroups) {
hgHartFiring(hg) := hartHaltedWrEn & ~haltedBitRegs(hartHaltedId) & (hgParticipateHart(hartSelFuncs.hartIdToHartSel(hartHaltedId)) === hg.U)
hgHartsAllHalted(hg) := (haltedBitRegs.asBools | hgParticipateHart.map(_ =/= hg.U)).reduce(_ & _)
when (~io.dmactive || ~dmAuthenticated) {
hgFired(hg) := false.B
}.elsewhen (~hgFired(hg) & (hgHartFiring(hg) | hgTrigFiring(hg))) {
hgFired(hg) := true.B
}.elsewhen ( hgFired(hg) & hgHartsAllHalted(hg) & hgTrigsAllAcked(hg)) {
hgFired(hg) := false.B
}
}
// For each hg that has fired, assert debug interrupt to each hart in that hg
for (component <- 0 until nComponents) {
hgDebugInt(component) := hgFired(hgParticipateHart(component))
}
// For each hg that has fired, assert trigger out for all external triggers in that hg
io.extTrigger.foreach {extTrigger =>
val extTriggerOutReq = RegInit(VecInit(Seq.fill(cfg.nExtTriggers) {false.B} ))
for (trig <- 0 until nExtTriggers) {
extTriggerOutReq(trig) := hgFired(hgParticipateTrig(trig))
}
extTrigger.out.req := extTriggerOutReq.asUInt
}
}
io.hgDebugInt := hgDebugInt | hrDebugInt
//----HALTSUM*
val numHaltedStatus = ((nComponents - 1) / 32) + 1
val haltedStatus = Wire(Vec(numHaltedStatus, Bits(32.W)))
for (ii <- 0 until numHaltedStatus) {
when (dmAuthenticated) {
haltedStatus(ii) := haltedBitRegs >> (ii*32)
}.otherwise {
haltedStatus(ii) := 0.U
}
}
val haltedSummary = Cat(haltedStatus.map(_.orR).reverse)
val HALTSUM1RdData = haltedSummary.asTypeOf(new HALTSUM1Fields())
val selectedHaltedStatus = Mux((selectedHartReg >> 5) > numHaltedStatus.U, 0.U, haltedStatus(selectedHartReg >> 5))
val HALTSUM0RdData = selectedHaltedStatus.asTypeOf(new HALTSUM0Fields())
// Since we only support 1024 harts, we don't implement HALTSUM2 or HALTSUM3
//----ABSTRACTCS
val ABSTRACTCSReset = WireInit(0.U.asTypeOf(new ABSTRACTCSFields()))
ABSTRACTCSReset.datacount := cfg.nAbstractDataWords.U
ABSTRACTCSReset.progbufsize := cfg.nProgramBufferWords.U
val ABSTRACTCSReg = Reg(new ABSTRACTCSFields())
val ABSTRACTCSWrData = WireInit(0.U.asTypeOf(new ABSTRACTCSFields()))
val ABSTRACTCSRdData = WireInit(ABSTRACTCSReg)
val ABSTRACTCSRdEn = WireInit(false.B)
val ABSTRACTCSWrEnMaybe = WireInit(false.B)
val ABSTRACTCSWrEnLegal = WireInit(false.B)
val ABSTRACTCSWrEn = ABSTRACTCSWrEnMaybe && ABSTRACTCSWrEnLegal
// multiple error types
// find implement in the state machine part
val errorBusy = WireInit(false.B)
val errorException = WireInit(false.B)
val errorUnsupported = WireInit(false.B)
val errorHaltResume = WireInit(false.B)
when (~io.dmactive || ~dmAuthenticated) {
ABSTRACTCSReg := ABSTRACTCSReset
}.otherwise {
when (errorBusy){
ABSTRACTCSReg.cmderr := DebugAbstractCommandError.ErrBusy.id.U
}.elsewhen (errorException) {
ABSTRACTCSReg.cmderr := DebugAbstractCommandError.ErrException.id.U
}.elsewhen (errorUnsupported) {
ABSTRACTCSReg.cmderr := DebugAbstractCommandError.ErrNotSupported.id.U
}.elsewhen (errorHaltResume) {
ABSTRACTCSReg.cmderr := DebugAbstractCommandError.ErrHaltResume.id.U
}.otherwise {
//W1C
when (ABSTRACTCSWrEn){
ABSTRACTCSReg.cmderr := ABSTRACTCSReg.cmderr & ~(ABSTRACTCSWrData.cmderr);
}
}
}
// For busy, see below state machine.
val abstractCommandBusy = WireInit(true.B)
ABSTRACTCSRdData.busy := abstractCommandBusy
when (~dmAuthenticated) { // read value must be 0 when not authenticated
ABSTRACTCSRdData.datacount := 0.U
ABSTRACTCSRdData.progbufsize := 0.U
}
//---- ABSTRACTAUTO
// It is a mask indicating whether datai/probufi have the autoexcution permisson
// this part aims to produce 3 wires : autoexecData,autoexecProg,autoexec
// first two specify which reg supports autoexec
// autoexec is a control signal, meaning there is at least one enabled autoexec reg
// when autoexec is set, generate instructions using COMMAND register
val ABSTRACTAUTOReset = WireInit(0.U.asTypeOf(new ABSTRACTAUTOFields()))
val ABSTRACTAUTOReg = Reg(new ABSTRACTAUTOFields())
val ABSTRACTAUTOWrData = WireInit(0.U.asTypeOf(new ABSTRACTAUTOFields()))
val ABSTRACTAUTORdData = WireInit(ABSTRACTAUTOReg)
val ABSTRACTAUTORdEn = WireInit(false.B)
val autoexecdataWrEnMaybe = WireInit(false.B)
val autoexecprogbufWrEnMaybe = WireInit(false.B)
val ABSTRACTAUTOWrEnLegal = WireInit(false.B)
when (~io.dmactive || ~dmAuthenticated) {
ABSTRACTAUTOReg := ABSTRACTAUTOReset
}.otherwise {
when (autoexecprogbufWrEnMaybe && ABSTRACTAUTOWrEnLegal) {
ABSTRACTAUTOReg.autoexecprogbuf := ABSTRACTAUTOWrData.autoexecprogbuf & ( (1 << cfg.nProgramBufferWords) - 1).U
}
when (autoexecdataWrEnMaybe && ABSTRACTAUTOWrEnLegal) {
ABSTRACTAUTOReg.autoexecdata := ABSTRACTAUTOWrData.autoexecdata & ( (1 << cfg.nAbstractDataWords) - 1).U
}
}
// Abstract Data access vector(byte-addressable)
val dmiAbstractDataAccessVec = WireInit(VecInit(Seq.fill(cfg.nAbstractDataWords * 4) {false.B} ))
dmiAbstractDataAccessVec := (dmiAbstractDataWrEnMaybe zip dmiAbstractDataRdEn).map{ case (r,w) => r | w}
// Program Buffer access vector(byte-addressable)
val dmiProgramBufferAccessVec = WireInit(VecInit(Seq.fill(cfg.nProgramBufferWords * 4) {false.B} ))
dmiProgramBufferAccessVec := (dmiProgramBufferWrEnMaybe zip dmiProgramBufferRdEn).map{ case (r,w) => r | w}
// at least one word access
val dmiAbstractDataAccess = dmiAbstractDataAccessVec.reduce(_ || _ )
val dmiProgramBufferAccess = dmiProgramBufferAccessVec.reduce(_ || _)
// This will take the shorter of the lists, which is what we want.
val autoexecData = WireInit(VecInit(Seq.fill(cfg.nAbstractDataWords) {false.B} ))
val autoexecProg = WireInit(VecInit(Seq.fill(cfg.nProgramBufferWords) {false.B} ))
(autoexecData zip ABSTRACTAUTOReg.autoexecdata.asBools).zipWithIndex.foreach {case (t, i) => t._1 := dmiAbstractDataAccessVec(i * 4) && t._2 }
(autoexecProg zip ABSTRACTAUTOReg.autoexecprogbuf.asBools).zipWithIndex.foreach {case (t, i) => t._1 := dmiProgramBufferAccessVec(i * 4) && t._2}
val autoexec = autoexecData.reduce(_ || _) || autoexecProg.reduce(_ || _)
//---- COMMAND
val COMMANDReset = WireInit(0.U.asTypeOf(new COMMANDFields()))
val COMMANDReg = Reg(new COMMANDFields())
val COMMANDWrDataVal = WireInit(0.U(32.W))
val COMMANDWrData = WireInit(COMMANDWrDataVal.asTypeOf(new COMMANDFields()))
val COMMANDWrEnMaybe = WireInit(false.B)
val COMMANDWrEnLegal = WireInit(false.B)
val COMMANDRdEn = WireInit(false.B)
val COMMANDWrEn = COMMANDWrEnMaybe && COMMANDWrEnLegal
val COMMANDRdData = COMMANDReg
when (~io.dmactive || ~dmAuthenticated) {
COMMANDReg := COMMANDReset
}.otherwise {
when (COMMANDWrEn) {
COMMANDReg := COMMANDWrData
}
}
// --- Abstract Data
// These are byte addressible, s.t. the Processor can use
// byte-addressible instructions to store to them.
val abstractDataMem = Reg(Vec(cfg.nAbstractDataWords*4, UInt(8.W)))
val abstractDataNxt = WireInit(abstractDataMem)
// --- Program Buffer
// byte-addressible mem
val programBufferMem = Reg(Vec(cfg.nProgramBufferWords*4, UInt(8.W)))
val programBufferNxt = WireInit(programBufferMem)
//--------------------------------------------------------------
// These bits are implementation-specific bits set
// by harts executing code.
//--------------------------------------------------------------
// Run control logic
when (~io.dmactive || ~dmAuthenticated) {
haltedBitRegs := 0.U
resumeReqRegs := 0.U
}.otherwise {
//remove those harts in reset
resumeReqRegs := resumeReqRegs & ~(hartIsInResetSync.asUInt)
val hartHaltedIdIndex = UIntToOH(hartSelFuncs.hartIdToHartSel(hartHaltedId))
val hartResumingIdIndex = UIntToOH(hartSelFuncs.hartIdToHartSel(hartResumingId))
val hartselIndex = UIntToOH(io.innerCtrl.bits.hartsel)
when (hartHaltedWrEn) {
// add those harts halting and remove those in reset
haltedBitRegs := (haltedBitRegs | hartHaltedIdIndex) & ~(hartIsInResetSync.asUInt)
}.elsewhen (hartResumingWrEn) {
// remove those harts in reset and those in resume
haltedBitRegs := (haltedBitRegs & ~(hartResumingIdIndex)) & ~(hartIsInResetSync.asUInt)
}.otherwise {
// remove those harts in reset
haltedBitRegs := haltedBitRegs & ~(hartIsInResetSync.asUInt)
}
when (hartResumingWrEn) {
// remove those harts in resume and those in reset
resumeReqRegs := (resumeReqRegs & ~(hartResumingIdIndex)) & ~(hartIsInResetSync.asUInt)
}
when (resumereq) {
// set all sleceted harts to resumeReq, remove those in reset
resumeReqRegs := (resumeReqRegs | hamaskWrSel.asUInt) & ~(hartIsInResetSync.asUInt)
}
}
when (resumereq) {
// next cycle resumeAcls will be the negation of next cycle resumeReqRegs
resumeAcks := (~resumeReqRegs & ~(hamaskWrSel.asUInt))
}.otherwise {
resumeAcks := ~resumeReqRegs
}
//---- AUTHDATA
val authRdEnMaybe = WireInit(false.B)
val authWrEnMaybe = WireInit(false.B)
io.auth.map { a =>
a.dmactive := io.dmactive
a.dmAuthRead := authRdEnMaybe & ~a.dmAuthBusy
a.dmAuthWrite := authWrEnMaybe & ~a.dmAuthBusy
}
val dmstatusRegFields = RegFieldGroup("dmi_dmstatus", Some("debug module status register"), Seq(
RegField.r(4, DMSTATUSRdData.version, RegFieldDesc("version", "version", reset=Some(2))),
RegField.r(1, DMSTATUSRdData.confstrptrvalid, RegFieldDesc("confstrptrvalid", "confstrptrvalid", reset=Some(0))),
RegField.r(1, DMSTATUSRdData.hasresethaltreq, RegFieldDesc("hasresethaltreq", "hasresethaltreq", reset=Some(1))),
RegField.r(1, DMSTATUSRdData.authbusy, RegFieldDesc("authbusy", "authbusy", reset=Some(0))),
RegField.r(1, DMSTATUSRdData.authenticated, RegFieldDesc("authenticated", "authenticated", reset=Some(1))),
RegField.r(1, DMSTATUSRdData.anyhalted, RegFieldDesc("anyhalted", "anyhalted", reset=Some(0))),
RegField.r(1, DMSTATUSRdData.allhalted, RegFieldDesc("allhalted", "allhalted", reset=Some(0))),
RegField.r(1, DMSTATUSRdData.anyrunning, RegFieldDesc("anyrunning", "anyrunning", reset=Some(1))),
RegField.r(1, DMSTATUSRdData.allrunning, RegFieldDesc("allrunning", "allrunning", reset=Some(1))),
RegField.r(1, DMSTATUSRdData.anyunavail, RegFieldDesc("anyunavail", "anyunavail", reset=Some(0))),
RegField.r(1, DMSTATUSRdData.allunavail, RegFieldDesc("allunavail", "allunavail", reset=Some(0))),
RegField.r(1, DMSTATUSRdData.anynonexistent, RegFieldDesc("anynonexistent", "anynonexistent", reset=Some(0))),
RegField.r(1, DMSTATUSRdData.allnonexistent, RegFieldDesc("allnonexistent", "allnonexistent", reset=Some(0))),
RegField.r(1, DMSTATUSRdData.anyresumeack, RegFieldDesc("anyresumeack", "anyresumeack", reset=Some(1))),
RegField.r(1, DMSTATUSRdData.allresumeack, RegFieldDesc("allresumeack", "allresumeack", reset=Some(1))),
RegField.r(1, DMSTATUSRdData.anyhavereset, RegFieldDesc("anyhavereset", "anyhavereset", reset=Some(0))),
RegField.r(1, DMSTATUSRdData.allhavereset, RegFieldDesc("allhavereset", "allhavereset", reset=Some(0))),
RegField(2),
RegField.r(1, DMSTATUSRdData.impebreak, RegFieldDesc("impebreak", "impebreak", reset=Some(if (cfg.hasImplicitEbreak) 1 else 0)))
))
val dmcs2RegFields = RegFieldGroup("dmi_dmcs2", Some("debug module control/status register 2"), Seq(
WNotifyVal(1, DMCS2RdData.hgselect, DMCS2WrData.hgselect, hgselectWrEn,
RegFieldDesc("hgselect", "select halt groups or external triggers", reset=Some(0), volatile=true)),
WNotifyVal(1, 0.U, DMCS2WrData.hgwrite, hgwriteWrEn,
RegFieldDesc("hgwrite", "write 1 to change halt groups", reset=None, access=RegFieldAccessType.W)),
WNotifyVal(5, DMCS2RdData.haltgroup, DMCS2WrData.haltgroup, haltgroupWrEn,
RegFieldDesc("haltgroup", "halt group", reset=Some(0), volatile=true)),
if (nExtTriggers > 1)
WNotifyVal(4, DMCS2RdData.exttrigger, DMCS2WrData.exttrigger, exttriggerWrEn,
RegFieldDesc("exttrigger", "external trigger select", reset=Some(0), volatile=true))
else RegField(4)
))
val abstractcsRegFields = RegFieldGroup("dmi_abstractcs", Some("abstract command control/status"), Seq(
RegField.r(4, ABSTRACTCSRdData.datacount, RegFieldDesc("datacount", "number of DATA registers", reset=Some(cfg.nAbstractDataWords))),
RegField(4),
WNotifyVal(3, ABSTRACTCSRdData.cmderr, ABSTRACTCSWrData.cmderr, ABSTRACTCSWrEnMaybe,
RegFieldDesc("cmderr", "command error", reset=Some(0), wrType=Some(RegFieldWrType.ONE_TO_CLEAR))),
RegField(1),
RegField.r(1, ABSTRACTCSRdData.busy, RegFieldDesc("busy", "busy", reset=Some(0))),
RegField(11),
RegField.r(5, ABSTRACTCSRdData.progbufsize, RegFieldDesc("progbufsize", "number of PROGBUF registers", reset=Some(cfg.nProgramBufferWords)))
))
val (sbcsFields, sbAddrFields, sbDataFields):
(Seq[RegField], Seq[Seq[RegField]], Seq[Seq[RegField]]) = sb2tlOpt.map{ sb2tl =>
SystemBusAccessModule(sb2tl, io.dmactive, dmAuthenticated)(p)
}.getOrElse((Seq.empty[RegField], Seq.fill[Seq[RegField]](4)(Seq.empty[RegField]), Seq.fill[Seq[RegField]](4)(Seq.empty[RegField])))
//--------------------------------------------------------------
// Program Buffer Access (DMI ... System Bus can override)
//--------------------------------------------------------------
val omRegMap = dmiNode.regmap(
(DMI_DMSTATUS << 2) -> dmstatusRegFields,
//TODO (DMI_CFGSTRADDR0 << 2) -> cfgStrAddrFields,
(DMI_DMCS2 << 2) -> (if (nHaltGroups > 0) dmcs2RegFields else Nil),
(DMI_HALTSUM0 << 2) -> RegFieldGroup("dmi_haltsum0", Some("Halt Summary 0"),
Seq(RegField.r(32, HALTSUM0RdData.asUInt, RegFieldDesc("dmi_haltsum0", "halt summary 0")))),
(DMI_HALTSUM1 << 2) -> RegFieldGroup("dmi_haltsum1", Some("Halt Summary 1"),
Seq(RegField.r(32, HALTSUM1RdData.asUInt, RegFieldDesc("dmi_haltsum1", "halt summary 1")))),
(DMI_ABSTRACTCS << 2) -> abstractcsRegFields,
(DMI_ABSTRACTAUTO<< 2) -> RegFieldGroup("dmi_abstractauto", Some("abstract command autoexec"), Seq(
WNotifyVal(cfg.nAbstractDataWords, ABSTRACTAUTORdData.autoexecdata, ABSTRACTAUTOWrData.autoexecdata, autoexecdataWrEnMaybe,
RegFieldDesc("autoexecdata", "abstract command data autoexec", reset=Some(0))),
RegField(16-cfg.nAbstractDataWords),
WNotifyVal(cfg.nProgramBufferWords, ABSTRACTAUTORdData.autoexecprogbuf, ABSTRACTAUTOWrData.autoexecprogbuf, autoexecprogbufWrEnMaybe,
RegFieldDesc("autoexecprogbuf", "abstract command progbuf autoexec", reset=Some(0))))),
(DMI_COMMAND << 2) -> RegFieldGroup("dmi_command", Some("Abstract Command Register"),
Seq(RWNotify(32, COMMANDRdData.asUInt, COMMANDWrDataVal, COMMANDRdEn, COMMANDWrEnMaybe,
Some(RegFieldDesc("dmi_command", "abstract command register", reset=Some(0), volatile=true))))),
(DMI_DATA0 << 2) -> RegFieldGroup("dmi_data", Some("abstract command data registers"), abstractDataMem.zipWithIndex.map{case (x, i) =>
RWNotify(8, Mux(dmAuthenticated, x, 0.U), abstractDataNxt(i),
dmiAbstractDataRdEn(i),
dmiAbstractDataWrEnMaybe(i),
Some(RegFieldDesc(s"dmi_data_$i", s"abstract command data register $i", reset = Some(0), volatile=true)))}, false),
(DMI_PROGBUF0 << 2) -> RegFieldGroup("dmi_progbuf", Some("abstract command progbuf registers"), programBufferMem.zipWithIndex.map{case (x, i) =>
RWNotify(8, Mux(dmAuthenticated, x, 0.U), programBufferNxt(i),
dmiProgramBufferRdEn(i),
dmiProgramBufferWrEnMaybe(i),
Some(RegFieldDesc(s"dmi_progbuf_$i", s"abstract command progbuf register $i", reset = Some(0))))}, false),
(DMI_AUTHDATA << 2) -> (if (cfg.hasAuthentication) RegFieldGroup("dmi_authdata", Some("authentication data exchange register"),
Seq(RWNotify(32, io.auth.get.dmAuthRdata, io.auth.get.dmAuthWdata, authRdEnMaybe, authWrEnMaybe,
Some(RegFieldDesc("authdata", "authentication data exchange", volatile=true))))) else Nil),
(DMI_SBCS << 2) -> sbcsFields,
(DMI_SBDATA0 << 2) -> sbDataFields(0),
(DMI_SBDATA1 << 2) -> sbDataFields(1),
(DMI_SBDATA2 << 2) -> sbDataFields(2),
(DMI_SBDATA3 << 2) -> sbDataFields(3),
(DMI_SBADDRESS0 << 2) -> sbAddrFields(0),
(DMI_SBADDRESS1 << 2) -> sbAddrFields(1),
(DMI_SBADDRESS2 << 2) -> sbAddrFields(2),
(DMI_SBADDRESS3 << 2) -> sbAddrFields(3)
)
// Abstract data mem is written by both the tile link interface and DMI...
abstractDataMem.zipWithIndex.foreach { case (x, i) =>
when (dmAuthenticated && dmiAbstractDataWrEnMaybe(i) && dmiAbstractDataAccessLegal) {
x := abstractDataNxt(i)
}
}
// ... and also by custom register read (if implemented)
val (customs, customParams) = customNode.in.unzip
val needCustom = (customs.size > 0) && (customParams.head.addrs.size > 0)
def getNeedCustom = () => needCustom
if (needCustom) {
val (custom, customP) = customNode.in.head
require(customP.width % 8 == 0, s"Debug Custom width must be divisible by 8, not ${customP.width}")
val custom_data = custom.data.asBools
val custom_bytes = Seq.tabulate(customP.width/8){i => custom_data.slice(i*8, (i+1)*8).asUInt}
when (custom.ready && custom.valid) {
(abstractDataMem zip custom_bytes).zipWithIndex.foreach {case ((a, b), i) =>
a := b
}
}
}
programBufferMem.zipWithIndex.foreach { case (x, i) =>
when (dmAuthenticated && dmiProgramBufferWrEnMaybe(i) && dmiProgramBufferAccessLegal) {
x := programBufferNxt(i)
}
}
//--------------------------------------------------------------
// "Variable" ROM Generation
//--------------------------------------------------------------
val goReg = Reg(Bool())
val goAbstract = WireInit(false.B)
val goCustom = WireInit(false.B)
val jalAbstract = WireInit(Instructions.JAL.value.U.asTypeOf(new GeneratedUJ()))
jalAbstract.setImm(ABSTRACT(cfg) - WHERETO)
when (~io.dmactive){
goReg := false.B
}.otherwise {
when (goAbstract) {
goReg := true.B
}.elsewhen (hartGoingWrEn){
assert(hartGoingId === 0.U, "Unexpected 'GOING' hart.")//Chisel3 #540 %x, expected %x", hartGoingId, 0.U)
goReg := false.B
}
}
class flagBundle extends Bundle {
val reserved = UInt(6.W)
val resume = Bool()
val go = Bool()
}
val flags = WireInit(VecInit(Seq.fill(1 << selectedHartReg.getWidth) {0.U.asTypeOf(new flagBundle())} ))
assert ((hartSelFuncs.hartSelToHartId(selectedHartReg) < flags.size.U),
s"HartSel to HartId Mapping is illegal for this Debug Implementation, because HartID must be < ${flags.size} for it to work.")
flags(hartSelFuncs.hartSelToHartId(selectedHartReg)).go := goReg
for (component <- 0 until nComponents) {
val componentSel = WireInit(component.U)
flags(hartSelFuncs.hartSelToHartId(componentSel)).resume := resumeReqRegs(component)
}
//----------------------------
// Abstract Command Decoding & Generation
//----------------------------
val accessRegisterCommandWr = WireInit(COMMANDWrData.asUInt.asTypeOf(new ACCESS_REGISTERFields()))
/** real COMMAND*/
val accessRegisterCommandReg = WireInit(COMMANDReg.asUInt.asTypeOf(new ACCESS_REGISTERFields()))
// TODO: Quick Access
class GeneratedI extends Bundle {
val imm = UInt(12.W)
val rs1 = UInt(5.W)
val funct3 = UInt(3.W)
val rd = UInt(5.W)
val opcode = UInt(7.W)
}
class GeneratedS extends Bundle {
val immhi = UInt(7.W)
val rs2 = UInt(5.W)
val rs1 = UInt(5.W)
val funct3 = UInt(3.W)
val immlo = UInt(5.W)
val opcode = UInt(7.W)
}
class GeneratedCSR extends Bundle {
val imm = UInt(12.W)
val rs1 = UInt(5.W)
val funct3 = UInt(3.W)
val rd = UInt(5.W)
val opcode = UInt(7.W)
}
class GeneratedUJ extends Bundle {
val imm3 = UInt(1.W)
val imm0 = UInt(10.W)
val imm1 = UInt(1.W)
val imm2 = UInt(8.W)
val rd = UInt(5.W)
val opcode = UInt(7.W)
def setImm(imm: Int) : Unit = {
// TODO: Check bounds of imm.
require(imm % 2 == 0, "Immediate must be even for UJ encoding.")
val immWire = WireInit(imm.S(21.W))
val immBits = WireInit(VecInit(immWire.asBools))
imm0 := immBits.slice(1, 1 + 10).asUInt
imm1 := immBits.slice(11, 11 + 11).asUInt
imm2 := immBits.slice(12, 12 + 8).asUInt
imm3 := immBits.slice(20, 20 + 1).asUInt
}
}
require((cfg.atzero && cfg.nAbstractInstructions == 2) || (!cfg.atzero && cfg.nAbstractInstructions == 5),
"Mismatch between DebugModuleParams atzero and nAbstractInstructions")
val abstractGeneratedMem = Reg(Vec(cfg.nAbstractInstructions, (UInt(32.W))))
def abstractGeneratedI(cfg: DebugModuleParams): UInt = {
val inst = Wire(new GeneratedI())
val offset = if (cfg.atzero) DATA else (DATA-0x800) & 0xFFF
val base = if (cfg.atzero) 0.U else Mux(accessRegisterCommandReg.regno(0), 8.U, 9.U)
inst.opcode := (Instructions.LW.value.U.asTypeOf(new GeneratedI())).opcode
inst.rd := (accessRegisterCommandReg.regno & 0x1F.U)
inst.funct3 := accessRegisterCommandReg.size
inst.rs1 := base
inst.imm := offset.U
inst.asUInt
}
def abstractGeneratedS(cfg: DebugModuleParams): UInt = {
val inst = Wire(new GeneratedS())
val offset = if (cfg.atzero) DATA else (DATA-0x800) & 0xFFF
val base = if (cfg.atzero) 0.U else Mux(accessRegisterCommandReg.regno(0), 8.U, 9.U)
inst.opcode := (Instructions.SW.value.U.asTypeOf(new GeneratedS())).opcode
inst.immlo := (offset & 0x1F).U
inst.funct3 := accessRegisterCommandReg.size
inst.rs1 := base
inst.rs2 := (accessRegisterCommandReg.regno & 0x1F.U)
inst.immhi := (offset >> 5).U
inst.asUInt
}
def abstractGeneratedCSR: UInt = {
val inst = Wire(new GeneratedCSR())
val base = Mux(accessRegisterCommandReg.regno(0), 8.U, 9.U) // use s0 as base for odd regs, s1 as base for even regs
inst := (Instructions.CSRRW.value.U.asTypeOf(new GeneratedCSR()))
inst.imm := CSRs.dscratch1.U
inst.rs1 := base
inst.rd := base
inst.asUInt
}
val nop = Wire(new GeneratedI())
nop := Instructions.ADDI.value.U.asTypeOf(new GeneratedI())
nop.rd := 0.U
nop.rs1 := 0.U
nop.imm := 0.U
val isa = Wire(new GeneratedI())
isa := Instructions.ADDIW.value.U.asTypeOf(new GeneratedI())
isa.rd := 0.U
isa.rs1 := 0.U
isa.imm := 0.U
when (goAbstract) {
if (cfg.nAbstractInstructions == 2) {
// ABSTRACT(0): Transfer: LW or SW, else NOP
// ABSTRACT(1): Postexec: NOP else EBREAK
abstractGeneratedMem(0) := Mux(accessRegisterCommandReg.transfer,
Mux(accessRegisterCommandReg.write, abstractGeneratedI(cfg), abstractGeneratedS(cfg)),
nop.asUInt
)
abstractGeneratedMem(1) := Mux(accessRegisterCommandReg.postexec,
nop.asUInt,
Instructions.EBREAK.value.U)
} else {
// Entry: All regs in GPRs, dscratch1=offset 0x800 in DM
// ABSTRACT(0): CheckISA: ADDW or NOP (exception here if size=3 and not RV64)
// ABSTRACT(1): CSRRW s1,dscratch1,s1 or CSRRW s0,dscratch1,s0
// ABSTRACT(2): Transfer: LW, SW, LD, SD else NOP
// ABSTRACT(3): CSRRW s1,dscratch1,s1 or CSRRW s0,dscratch1,s0
// ABSTRACT(4): Postexec: NOP else EBREAK
abstractGeneratedMem(0) := Mux(accessRegisterCommandReg.transfer && accessRegisterCommandReg.size =/= 2.U, isa.asUInt, nop.asUInt)
abstractGeneratedMem(1) := abstractGeneratedCSR
abstractGeneratedMem(2) := Mux(accessRegisterCommandReg.transfer,
Mux(accessRegisterCommandReg.write, abstractGeneratedI(cfg), abstractGeneratedS(cfg)),
nop.asUInt
)
abstractGeneratedMem(3) := abstractGeneratedCSR
abstractGeneratedMem(4) := Mux(accessRegisterCommandReg.postexec,
nop.asUInt,
Instructions.EBREAK.value.U)
}
}
//--------------------------------------------------------------
// Drive Custom Access
//--------------------------------------------------------------
if (needCustom) {
val (custom, customP) = customNode.in.head
custom.addr := accessRegisterCommandReg.regno
custom.valid := goCustom
}
//--------------------------------------------------------------
// Hart Bus Access
//--------------------------------------------------------------
tlNode.regmap(
// This memory is writable.
HALTED -> Seq(WNotifyWire(sbIdWidth, hartHaltedId, hartHaltedWrEn,
"debug_hart_halted", "Debug ROM Causes hart to write its hartID here when it is in Debug Mode.")),
GOING -> Seq(WNotifyWire(sbIdWidth, hartGoingId, hartGoingWrEn,
"debug_hart_going", "Debug ROM causes hart to write 0 here when it begins executing Debug Mode instructions.")),
RESUMING -> Seq(WNotifyWire(sbIdWidth, hartResumingId, hartResumingWrEn,
"debug_hart_resuming", "Debug ROM causes hart to write its hartID here when it leaves Debug Mode.")),
EXCEPTION -> Seq(WNotifyWire(sbIdWidth, hartExceptionId, hartExceptionWrEn,
"debug_hart_exception", "Debug ROM causes hart to write 0 here if it gets an exception in Debug Mode.")),
DATA -> RegFieldGroup("debug_data", Some("Data used to communicate with Debug Module"),
abstractDataMem.zipWithIndex.map {case (x, i) => RegField(8, x, RegFieldDesc(s"debug_data_$i", ""))}),
PROGBUF(cfg)-> RegFieldGroup("debug_progbuf", Some("Program buffer used to communicate with Debug Module"),
programBufferMem.zipWithIndex.map {case (x, i) => RegField(8, x, RegFieldDesc(s"debug_progbuf_$i", ""))}),
// These sections are read-only.
IMPEBREAK(cfg)-> {if (cfg.hasImplicitEbreak) Seq(RegField.r(32, Instructions.EBREAK.value.U,
RegFieldDesc("debug_impebreak", "Debug Implicit EBREAK", reset=Some(Instructions.EBREAK.value)))) else Nil},
WHERETO -> Seq(RegField.r(32, jalAbstract.asUInt, RegFieldDesc("debug_whereto", "Instruction filled in by Debug Module to control hart in Debug Mode", volatile = true))),
ABSTRACT(cfg) -> RegFieldGroup("debug_abstract", Some("Instructions generated by Debug Module"),
abstractGeneratedMem.zipWithIndex.map{ case (x,i) => RegField.r(32, x, RegFieldDesc(s"debug_abstract_$i", "", volatile=true))}),
FLAGS -> RegFieldGroup("debug_flags", Some("Memory region used to control hart going/resuming in Debug Mode"),
if (nComponents == 1) {
Seq.tabulate(1024) { i => RegField.r(8, flags(0).asUInt, RegFieldDesc(s"debug_flags_$i", "", volatile=true)) }
} else {
flags.zipWithIndex.map{case(x, i) => RegField.r(8, x.asUInt, RegFieldDesc(s"debug_flags_$i", "", volatile=true))}
}),
ROMBASE -> RegFieldGroup("debug_rom", Some("Debug ROM"),
(if (cfg.atzero) DebugRomContents() else DebugRomNonzeroContents()).zipWithIndex.map{case (x, i) =>
RegField.r(8, (x & 0xFF).U(8.W), RegFieldDesc(s"debug_rom_$i", "", reset=Some(x)))})
)
// Override System Bus accesses with dmactive reset.
when (~io.dmactive){
abstractDataMem.foreach {x => x := 0.U}
programBufferMem.foreach {x => x := 0.U}
}
//--------------------------------------------------------------
// Abstract Command State Machine
//--------------------------------------------------------------
object CtrlState extends scala.Enumeration {
type CtrlState = Value
val Waiting, CheckGenerate, Exec, Custom = Value
def apply( t : Value) : UInt = {
t.id.U(log2Up(values.size).W)
}
}
import CtrlState._
// This is not an initialization!
val ctrlStateReg = Reg(chiselTypeOf(CtrlState(Waiting)))
val hartHalted = haltedBitRegs(if (nComponents == 1) 0.U(0.W) else selectedHartReg)
val ctrlStateNxt = WireInit(ctrlStateReg)
//------------------------
// DMI Register Control and Status
abstractCommandBusy := (ctrlStateReg =/= CtrlState(Waiting))
ABSTRACTCSWrEnLegal := (ctrlStateReg === CtrlState(Waiting))
COMMANDWrEnLegal := (ctrlStateReg === CtrlState(Waiting))
ABSTRACTAUTOWrEnLegal := (ctrlStateReg === CtrlState(Waiting))
dmiAbstractDataAccessLegal := (ctrlStateReg === CtrlState(Waiting))
dmiProgramBufferAccessLegal := (ctrlStateReg === CtrlState(Waiting))
errorBusy := (ABSTRACTCSWrEnMaybe && ~ABSTRACTCSWrEnLegal) ||
(autoexecdataWrEnMaybe && ~ABSTRACTAUTOWrEnLegal) ||
(autoexecprogbufWrEnMaybe && ~ABSTRACTAUTOWrEnLegal) ||
(COMMANDWrEnMaybe && ~COMMANDWrEnLegal) ||
(dmiAbstractDataAccess && ~dmiAbstractDataAccessLegal) ||
(dmiProgramBufferAccess && ~dmiProgramBufferAccessLegal)
// TODO: Maybe Quick Access
val commandWrIsAccessRegister = (COMMANDWrData.cmdtype === DebugAbstractCommandType.AccessRegister.id.U)
val commandRegIsAccessRegister = (COMMANDReg.cmdtype === DebugAbstractCommandType.AccessRegister.id.U)
val commandWrIsUnsupported = COMMANDWrEn && !commandWrIsAccessRegister
val commandRegIsUnsupported = WireInit(true.B)
val commandRegBadHaltResume = WireInit(false.B)
// We only support abstract commands for GPRs and any custom registers, if specified.
val accessRegIsLegalSize = (accessRegisterCommandReg.size === 2.U) || (accessRegisterCommandReg.size === 3.U)
val accessRegIsGPR = (accessRegisterCommandReg.regno >= 0x1000.U && accessRegisterCommandReg.regno <= 0x101F.U) && accessRegIsLegalSize
val accessRegIsCustom = if (needCustom) {
val (custom, customP) = customNode.in.head
customP.addrs.foldLeft(false.B){
(result, current) => result || (current.U === accessRegisterCommandReg.regno)}
} else false.B
when (commandRegIsAccessRegister) {
when (accessRegIsCustom && accessRegisterCommandReg.transfer && accessRegisterCommandReg.write === false.B) {
commandRegIsUnsupported := false.B
}.elsewhen (!accessRegisterCommandReg.transfer || accessRegIsGPR) {
commandRegIsUnsupported := false.B
commandRegBadHaltResume := ~hartHalted
}
}
val wrAccessRegisterCommand = COMMANDWrEn && commandWrIsAccessRegister && (ABSTRACTCSReg.cmderr === 0.U)
val regAccessRegisterCommand = autoexec && commandRegIsAccessRegister && (ABSTRACTCSReg.cmderr === 0.U)
//------------------------
// Variable ROM STATE MACHINE
// -----------------------
when (ctrlStateReg === CtrlState(Waiting)){
when (wrAccessRegisterCommand || regAccessRegisterCommand) {
ctrlStateNxt := CtrlState(CheckGenerate)
}.elsewhen (commandWrIsUnsupported) { // These checks are really on the command type.
errorUnsupported := true.B
}.elsewhen (autoexec && commandRegIsUnsupported) {
errorUnsupported := true.B
}
}.elsewhen (ctrlStateReg === CtrlState(CheckGenerate)){
// We use this state to ensure that the COMMAND has been
// registered by the time that we need to use it, to avoid
// generating it directly from the COMMANDWrData.
// This 'commandRegIsUnsupported' is really just checking the
// AccessRegisterCommand parameters (regno)
when (commandRegIsUnsupported) {
errorUnsupported := true.B
ctrlStateNxt := CtrlState(Waiting)
}.elsewhen (commandRegBadHaltResume){
errorHaltResume := true.B
ctrlStateNxt := CtrlState(Waiting)
}.otherwise {
when(accessRegIsCustom) {
ctrlStateNxt := CtrlState(Custom)
}.otherwise {
ctrlStateNxt := CtrlState(Exec)
goAbstract := true.B
}
}
}.elsewhen (ctrlStateReg === CtrlState(Exec)) {
// We can't just look at 'hartHalted' here, because
// hartHaltedWrEn is overloaded to mean 'got an ebreak'
// which may have happened when we were already halted.
when(goReg === false.B && hartHaltedWrEn && (hartSelFuncs.hartIdToHartSel(hartHaltedId) === selectedHartReg)){
ctrlStateNxt := CtrlState(Waiting)
}
when(hartExceptionWrEn) {
assert(hartExceptionId === 0.U, "Unexpected 'EXCEPTION' hart")//Chisel3 #540, %x, expected %x", hartExceptionId, 0.U)
ctrlStateNxt := CtrlState(Waiting)
errorException := true.B
}
}.elsewhen (ctrlStateReg === CtrlState(Custom)) {
assert(needCustom.B, "Should not be in custom state unless we need it.")
goCustom := true.B
val (custom, customP) = customNode.in.head
when (custom.ready && custom.valid) {
ctrlStateNxt := CtrlState(Waiting)
}
}
when (~io.dmactive || ~dmAuthenticated) {
ctrlStateReg := CtrlState(Waiting)
}.otherwise {
ctrlStateReg := ctrlStateNxt
}
assert ((!io.dmactive || !hartExceptionWrEn || ctrlStateReg === CtrlState(Exec)),
"Unexpected EXCEPTION write: should only get it in Debug Module EXEC state")
}
}
// Wrapper around TL Debug Module Inner and an Async DMI Sink interface.
// Handles the synchronization of dmactive, which is used as a synchronous reset
// inside the Inner block.
// Also is the Sink side of hartsel & resumereq fields of DMCONTROL.
class TLDebugModuleInnerAsync(device: Device, getNComponents: () => Int, beatBytes: Int)(implicit p: Parameters) extends LazyModule{
val cfg = p(DebugModuleKey).get
val dmInner = LazyModule(new TLDebugModuleInner(device, getNComponents, beatBytes))
val dmiXing = LazyModule(new TLAsyncCrossingSink(AsyncQueueParams.singleton(safe=cfg.crossingHasSafeReset)))
val dmiNode = dmiXing.node
val tlNode = dmInner.tlNode
dmInner.dmiNode := dmiXing.node
// Require that there are no registers in TL interface, so that spurious
// processor accesses to the DM don't need to enable the clock. We don't
// require this property of the SBA, because the debugger is responsible for
// raising dmactive (hence enabling the clock) during these transactions.
require(dmInner.tlNode.concurrency == 0)
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
// Clock/reset domains:
// debug_clock / debug_reset = Debug inner domain
// tl_clock / tl_reset = tilelink domain (External: clock / reset)
//
val io = IO(new Bundle {
val debug_clock = Input(Clock())
val debug_reset = Input(Reset())
val tl_clock = Input(Clock())
val tl_reset = Input(Reset())
// These are all asynchronous and come from Outer
/** reset signal for DM */
val dmactive = Input(Bool())
/** conrol signals for Inner
*
* generated in Outer
*/
val innerCtrl = Flipped(new AsyncBundle(new DebugInternalBundle(getNComponents()), AsyncQueueParams.singleton(safe=cfg.crossingHasSafeReset)))
// This comes from tlClk domain.
/** debug available status */
val debugUnavail = Input(Vec(getNComponents(), Bool()))
/** debug interruption*/
val hgDebugInt = Output(Vec(getNComponents(), Bool()))
val extTrigger = (p(DebugModuleKey).get.nExtTriggers > 0).option(new DebugExtTriggerIO())
/** vector to indicate which hart is in reset
*
* dm receives it from core and sends it to Inner
*/
val hartIsInReset = Input(Vec(getNComponents(), Bool()))
/** Debug Authentication signals from core */
val auth = p(DebugModuleKey).get.hasAuthentication.option(new DebugAuthenticationIO())
})
val rf_reset = IO(Input(Reset())) // RF transform
childClock := io.debug_clock
childReset := io.debug_reset
override def provideImplicitClockToLazyChildren = true
val dmactive_synced = withClockAndReset(childClock, childReset) {
val dmactive_synced = AsyncResetSynchronizerShiftReg(in=io.dmactive, sync=3, name=Some("dmactiveSync"))
dmInner.module.clock := io.debug_clock
dmInner.module.reset := io.debug_reset
dmInner.module.io.tl_clock := io.tl_clock
dmInner.module.io.tl_reset := io.tl_reset
dmInner.module.io.dmactive := dmactive_synced
dmInner.module.io.innerCtrl <> FromAsyncBundle(io.innerCtrl)
dmInner.module.io.debugUnavail := io.debugUnavail
io.hgDebugInt := dmInner.module.io.hgDebugInt
io.extTrigger.foreach { x => dmInner.module.io.extTrigger.foreach {y => x <> y}}
dmInner.module.io.hartIsInReset := io.hartIsInReset
io.auth.foreach { x => dmInner.module.io.auth.foreach {y => x <> y}}
dmactive_synced
}
}
}
/** Create a version of the TLDebugModule which includes a synchronization interface
* internally for the DMI. This is no longer optional outside of this module
* because the Clock must run when tl_clock isn't running or tl_reset is asserted.
*/
class TLDebugModule(beatBytes: Int)(implicit p: Parameters) extends LazyModule {
val device = new SimpleDevice("debug-controller", Seq("sifive,debug-013","riscv,debug-013")){
override val alwaysExtended = true
override def describe(resources: ResourceBindings): Description = {
val Description(name, mapping) = super.describe(resources)
val attach = Map(
"debug-attach" -> (
(if (p(ExportDebug).apb) Seq(ResourceString("apb")) else Seq()) ++
(if (p(ExportDebug).jtag) Seq(ResourceString("jtag")) else Seq()) ++
(if (p(ExportDebug).cjtag) Seq(ResourceString("cjtag")) else Seq()) ++
(if (p(ExportDebug).dmi) Seq(ResourceString("dmi")) else Seq())))
Description(name, mapping ++ attach)
}
}
val dmOuter : TLDebugModuleOuterAsync = LazyModule(new TLDebugModuleOuterAsync(device)(p))
val dmInner : TLDebugModuleInnerAsync = LazyModule(new TLDebugModuleInnerAsync(device, () => {dmOuter.dmOuter.intnode.edges.out.size}, beatBytes)(p))
val node = dmInner.tlNode
val intnode = dmOuter.intnode
val apbNodeOpt = dmOuter.apbNodeOpt
dmInner.dmiNode := dmOuter.dmiInnerNode
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
val nComponents = dmOuter.dmOuter.intnode.edges.out.size
// Clock/reset domains:
// tl_clock / tl_reset = tilelink domain
// debug_clock / debug_reset = Inner debug (synchronous to tl_clock)
// apb_clock / apb_reset = Outer debug with APB
// dmiClock / dmiReset = Outer debug without APB
//
val io = IO(new Bundle {
val debug_clock = Input(Clock())
val debug_reset = Input(Reset())
val tl_clock = Input(Clock())
val tl_reset = Input(Reset())
/** Debug control signals generated in Outer */
val ctrl = new DebugCtrlBundle(nComponents)
/** Debug Module Interface bewteen DM and DTM
*
* The DTM provides access to one or more Debug Modules (DMs) using DMI
*/
val dmi = (!p(ExportDebug).apb).option(Flipped(new ClockedDMIIO()))
val apb_clock = p(ExportDebug).apb.option(Input(Clock()))
val apb_reset = p(ExportDebug).apb.option(Input(Reset()))
val extTrigger = (p(DebugModuleKey).get.nExtTriggers > 0).option(new DebugExtTriggerIO())
/** vector to indicate which hart is in reset
*
* dm receives it from core and sends it to Inner
*/
val hartIsInReset = Input(Vec(nComponents, Bool()))
/** hart reset request generated by hartreset-logic in Outer */
val hartResetReq = p(DebugModuleKey).get.hasHartResets.option(Output(Vec(nComponents, Bool())))
/** Debug Authentication signals from core */
val auth = p(DebugModuleKey).get.hasAuthentication.option(new DebugAuthenticationIO())
})
childClock := io.tl_clock
childReset := io.tl_reset
override def provideImplicitClockToLazyChildren = true
dmOuter.module.io.dmi.foreach { dmOuterDMI =>
dmOuterDMI <> io.dmi.get.dmi
dmOuter.module.io.dmi_reset := io.dmi.get.dmiReset
dmOuter.module.io.dmi_clock := io.dmi.get.dmiClock
dmOuter.module.rf_reset := io.dmi.get.dmiReset
}
(io.apb_clock zip io.apb_reset) foreach { case (c, r) =>
dmOuter.module.io.dmi_reset := r
dmOuter.module.io.dmi_clock := c
dmOuter.module.rf_reset := r
}
dmInner.module.rf_reset := io.debug_reset
dmInner.module.io.debug_clock := io.debug_clock
dmInner.module.io.debug_reset := io.debug_reset
dmInner.module.io.tl_clock := io.tl_clock
dmInner.module.io.tl_reset := io.tl_reset
dmInner.module.io.innerCtrl <> dmOuter.module.io.innerCtrl
dmInner.module.io.dmactive := dmOuter.module.io.ctrl.dmactive
dmInner.module.io.debugUnavail := io.ctrl.debugUnavail
dmOuter.module.io.hgDebugInt := dmInner.module.io.hgDebugInt
io.ctrl <> dmOuter.module.io.ctrl
io.extTrigger.foreach { x => dmInner.module.io.extTrigger.foreach {y => x <> y}}
dmInner.module.io.hartIsInReset := io.hartIsInReset
io.hartResetReq.foreach { x => dmOuter.module.io.hartResetReq.foreach {y => x := y}}
io.auth.foreach { x => dmOuter.module.io.dmAuthenticated.get := x.dmAuthenticated }
io.auth.foreach { x => dmInner.module.io.auth.foreach {y => x <> y}}
}
}
| module TLDebugModule( // @[Debug.scala:1959:9]
input auto_dmInner_dmInner_sb2tlOpt_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_dmInner_dmInner_sb2tlOpt_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_dmInner_dmInner_sb2tlOpt_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_dmInner_dmInner_sb2tlOpt_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_dmInner_dmInner_sb2tlOpt_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_dmInner_dmInner_sb2tlOpt_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_dmInner_dmInner_sb2tlOpt_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_dmInner_dmInner_sb2tlOpt_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_dmInner_dmInner_sb2tlOpt_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_dmInner_dmInner_sb2tlOpt_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_dmInner_dmInner_sb2tlOpt_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_dmInner_dmInner_sb2tlOpt_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_dmInner_dmInner_sb2tlOpt_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_dmInner_dmInner_sb2tlOpt_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_dmInner_dmInner_sb2tlOpt_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_dmInner_dmInner_tl_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_dmInner_dmInner_tl_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_dmInner_dmInner_tl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_dmInner_dmInner_tl_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_dmInner_dmInner_tl_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [12:0] auto_dmInner_dmInner_tl_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [11:0] auto_dmInner_dmInner_tl_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_dmInner_dmInner_tl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_dmInner_dmInner_tl_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_dmInner_dmInner_tl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_dmInner_dmInner_tl_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_dmInner_dmInner_tl_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_dmInner_dmInner_tl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_dmInner_dmInner_tl_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [12:0] auto_dmInner_dmInner_tl_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_dmInner_dmInner_tl_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_dmOuter_int_out_sync_0, // @[LazyModuleImp.scala:107:25]
input io_debug_clock, // @[Debug.scala:1968:16]
input io_debug_reset, // @[Debug.scala:1968:16]
input io_tl_clock, // @[Debug.scala:1968:16]
input io_tl_reset, // @[Debug.scala:1968:16]
output io_ctrl_ndreset, // @[Debug.scala:1968:16]
output io_ctrl_dmactive, // @[Debug.scala:1968:16]
input io_ctrl_dmactiveAck, // @[Debug.scala:1968:16]
output io_dmi_dmi_req_ready, // @[Debug.scala:1968:16]
input io_dmi_dmi_req_valid, // @[Debug.scala:1968:16]
input [6:0] io_dmi_dmi_req_bits_addr, // @[Debug.scala:1968:16]
input [31:0] io_dmi_dmi_req_bits_data, // @[Debug.scala:1968:16]
input [1:0] io_dmi_dmi_req_bits_op, // @[Debug.scala:1968:16]
input io_dmi_dmi_resp_ready, // @[Debug.scala:1968:16]
output io_dmi_dmi_resp_valid, // @[Debug.scala:1968:16]
output [31:0] io_dmi_dmi_resp_bits_data, // @[Debug.scala:1968:16]
output [1:0] io_dmi_dmi_resp_bits_resp, // @[Debug.scala:1968:16]
input io_dmi_dmiClock, // @[Debug.scala:1968:16]
input io_dmi_dmiReset, // @[Debug.scala:1968:16]
input io_hartIsInReset_0 // @[Debug.scala:1968:16]
);
wire _dmInner_auto_dmiXing_in_a_ridx; // @[Debug.scala:1950:53]
wire _dmInner_auto_dmiXing_in_a_safe_ridx_valid; // @[Debug.scala:1950:53]
wire _dmInner_auto_dmiXing_in_a_safe_sink_reset_n; // @[Debug.scala:1950:53]
wire [2:0] _dmInner_auto_dmiXing_in_d_mem_0_opcode; // @[Debug.scala:1950:53]
wire [1:0] _dmInner_auto_dmiXing_in_d_mem_0_size; // @[Debug.scala:1950:53]
wire _dmInner_auto_dmiXing_in_d_mem_0_source; // @[Debug.scala:1950:53]
wire [31:0] _dmInner_auto_dmiXing_in_d_mem_0_data; // @[Debug.scala:1950:53]
wire _dmInner_auto_dmiXing_in_d_widx; // @[Debug.scala:1950:53]
wire _dmInner_auto_dmiXing_in_d_safe_widx_valid; // @[Debug.scala:1950:53]
wire _dmInner_auto_dmiXing_in_d_safe_source_reset_n; // @[Debug.scala:1950:53]
wire _dmInner_io_innerCtrl_ridx; // @[Debug.scala:1950:53]
wire _dmInner_io_innerCtrl_safe_ridx_valid; // @[Debug.scala:1950:53]
wire _dmInner_io_innerCtrl_safe_sink_reset_n; // @[Debug.scala:1950:53]
wire _dmInner_io_hgDebugInt_0; // @[Debug.scala:1950:53]
wire [2:0] _dmOuter_auto_asource_out_a_mem_0_opcode; // @[Debug.scala:1949:53]
wire [8:0] _dmOuter_auto_asource_out_a_mem_0_address; // @[Debug.scala:1949:53]
wire [31:0] _dmOuter_auto_asource_out_a_mem_0_data; // @[Debug.scala:1949:53]
wire _dmOuter_auto_asource_out_a_widx; // @[Debug.scala:1949:53]
wire _dmOuter_auto_asource_out_a_safe_widx_valid; // @[Debug.scala:1949:53]
wire _dmOuter_auto_asource_out_a_safe_source_reset_n; // @[Debug.scala:1949:53]
wire _dmOuter_auto_asource_out_d_ridx; // @[Debug.scala:1949:53]
wire _dmOuter_auto_asource_out_d_safe_ridx_valid; // @[Debug.scala:1949:53]
wire _dmOuter_auto_asource_out_d_safe_sink_reset_n; // @[Debug.scala:1949:53]
wire _dmOuter_io_ctrl_dmactive; // @[Debug.scala:1949:53]
wire _dmOuter_io_innerCtrl_mem_0_resumereq; // @[Debug.scala:1949:53]
wire [9:0] _dmOuter_io_innerCtrl_mem_0_hartsel; // @[Debug.scala:1949:53]
wire _dmOuter_io_innerCtrl_mem_0_ackhavereset; // @[Debug.scala:1949:53]
wire _dmOuter_io_innerCtrl_mem_0_hrmask_0; // @[Debug.scala:1949:53]
wire _dmOuter_io_innerCtrl_widx; // @[Debug.scala:1949:53]
wire _dmOuter_io_innerCtrl_safe_widx_valid; // @[Debug.scala:1949:53]
wire _dmOuter_io_innerCtrl_safe_source_reset_n; // @[Debug.scala:1949:53]
wire auto_dmInner_dmInner_sb2tlOpt_out_a_ready_0 = auto_dmInner_dmInner_sb2tlOpt_out_a_ready; // @[Debug.scala:1959:9]
wire auto_dmInner_dmInner_sb2tlOpt_out_d_valid_0 = auto_dmInner_dmInner_sb2tlOpt_out_d_valid; // @[Debug.scala:1959:9]
wire [2:0] auto_dmInner_dmInner_sb2tlOpt_out_d_bits_opcode_0 = auto_dmInner_dmInner_sb2tlOpt_out_d_bits_opcode; // @[Debug.scala:1959:9]
wire [1:0] auto_dmInner_dmInner_sb2tlOpt_out_d_bits_param_0 = auto_dmInner_dmInner_sb2tlOpt_out_d_bits_param; // @[Debug.scala:1959:9]
wire [3:0] auto_dmInner_dmInner_sb2tlOpt_out_d_bits_size_0 = auto_dmInner_dmInner_sb2tlOpt_out_d_bits_size; // @[Debug.scala:1959:9]
wire [4:0] auto_dmInner_dmInner_sb2tlOpt_out_d_bits_sink_0 = auto_dmInner_dmInner_sb2tlOpt_out_d_bits_sink; // @[Debug.scala:1959:9]
wire auto_dmInner_dmInner_sb2tlOpt_out_d_bits_denied_0 = auto_dmInner_dmInner_sb2tlOpt_out_d_bits_denied; // @[Debug.scala:1959:9]
wire [7:0] auto_dmInner_dmInner_sb2tlOpt_out_d_bits_data_0 = auto_dmInner_dmInner_sb2tlOpt_out_d_bits_data; // @[Debug.scala:1959:9]
wire auto_dmInner_dmInner_sb2tlOpt_out_d_bits_corrupt_0 = auto_dmInner_dmInner_sb2tlOpt_out_d_bits_corrupt; // @[Debug.scala:1959:9]
wire auto_dmInner_dmInner_tl_in_a_valid_0 = auto_dmInner_dmInner_tl_in_a_valid; // @[Debug.scala:1959:9]
wire [2:0] auto_dmInner_dmInner_tl_in_a_bits_opcode_0 = auto_dmInner_dmInner_tl_in_a_bits_opcode; // @[Debug.scala:1959:9]
wire [2:0] auto_dmInner_dmInner_tl_in_a_bits_param_0 = auto_dmInner_dmInner_tl_in_a_bits_param; // @[Debug.scala:1959:9]
wire [1:0] auto_dmInner_dmInner_tl_in_a_bits_size_0 = auto_dmInner_dmInner_tl_in_a_bits_size; // @[Debug.scala:1959:9]
wire [12:0] auto_dmInner_dmInner_tl_in_a_bits_source_0 = auto_dmInner_dmInner_tl_in_a_bits_source; // @[Debug.scala:1959:9]
wire [11:0] auto_dmInner_dmInner_tl_in_a_bits_address_0 = auto_dmInner_dmInner_tl_in_a_bits_address; // @[Debug.scala:1959:9]
wire [7:0] auto_dmInner_dmInner_tl_in_a_bits_mask_0 = auto_dmInner_dmInner_tl_in_a_bits_mask; // @[Debug.scala:1959:9]
wire [63:0] auto_dmInner_dmInner_tl_in_a_bits_data_0 = auto_dmInner_dmInner_tl_in_a_bits_data; // @[Debug.scala:1959:9]
wire auto_dmInner_dmInner_tl_in_a_bits_corrupt_0 = auto_dmInner_dmInner_tl_in_a_bits_corrupt; // @[Debug.scala:1959:9]
wire auto_dmInner_dmInner_tl_in_d_ready_0 = auto_dmInner_dmInner_tl_in_d_ready; // @[Debug.scala:1959:9]
wire io_debug_clock_0 = io_debug_clock; // @[Debug.scala:1959:9]
wire io_debug_reset_0 = io_debug_reset; // @[Debug.scala:1959:9]
wire io_tl_clock_0 = io_tl_clock; // @[Debug.scala:1959:9]
wire io_tl_reset_0 = io_tl_reset; // @[Debug.scala:1959:9]
wire io_ctrl_dmactiveAck_0 = io_ctrl_dmactiveAck; // @[Debug.scala:1959:9]
wire io_dmi_dmi_req_valid_0 = io_dmi_dmi_req_valid; // @[Debug.scala:1959:9]
wire [6:0] io_dmi_dmi_req_bits_addr_0 = io_dmi_dmi_req_bits_addr; // @[Debug.scala:1959:9]
wire [31:0] io_dmi_dmi_req_bits_data_0 = io_dmi_dmi_req_bits_data; // @[Debug.scala:1959:9]
wire [1:0] io_dmi_dmi_req_bits_op_0 = io_dmi_dmi_req_bits_op; // @[Debug.scala:1959:9]
wire io_dmi_dmi_resp_ready_0 = io_dmi_dmi_resp_ready; // @[Debug.scala:1959:9]
wire io_dmi_dmiClock_0 = io_dmi_dmiClock; // @[Debug.scala:1959:9]
wire io_dmi_dmiReset_0 = io_dmi_dmiReset; // @[Debug.scala:1959:9]
wire io_hartIsInReset_0_0 = io_hartIsInReset_0; // @[Debug.scala:1959:9]
wire auto_dmInner_dmInner_sb2tlOpt_out_a_bits_source = 1'h0; // @[Debug.scala:1959:9]
wire auto_dmInner_dmInner_sb2tlOpt_out_a_bits_corrupt = 1'h0; // @[Debug.scala:1959:9]
wire auto_dmInner_dmInner_sb2tlOpt_out_d_bits_source = 1'h0; // @[Debug.scala:1959:9]
wire auto_dmInner_dmInner_custom_in_addr = 1'h0; // @[Debug.scala:1959:9]
wire auto_dmInner_dmInner_custom_in_ready = 1'h0; // @[Debug.scala:1959:9]
wire auto_dmInner_dmInner_custom_in_valid = 1'h0; // @[Debug.scala:1959:9]
wire auto_dmInner_dmInner_tl_in_d_bits_sink = 1'h0; // @[Debug.scala:1959:9]
wire auto_dmInner_dmInner_tl_in_d_bits_denied = 1'h0; // @[Debug.scala:1959:9]
wire auto_dmInner_dmInner_tl_in_d_bits_corrupt = 1'h0; // @[Debug.scala:1959:9]
wire io_ctrl_debugUnavail_0 = 1'h0; // @[Debug.scala:1959:9]
wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire [1:0] auto_dmInner_dmInner_tl_in_d_bits_param = 2'h0; // @[Debug.scala:1949:53, :1950:53, :1959:9]
wire auto_dmInner_dmInner_sb2tlOpt_out_a_bits_mask = 1'h1; // @[Debug.scala:1950:53, :1959:9]
wire [2:0] auto_dmInner_dmInner_sb2tlOpt_out_a_bits_param = 3'h0; // @[Debug.scala:1949:53, :1950:53, :1959:9]
wire childClock = io_tl_clock_0; // @[Debug.scala:1959:9]
wire childReset = io_tl_reset_0; // @[Debug.scala:1959:9]
wire [2:0] auto_dmInner_dmInner_sb2tlOpt_out_a_bits_opcode_0; // @[Debug.scala:1959:9]
wire [3:0] auto_dmInner_dmInner_sb2tlOpt_out_a_bits_size_0; // @[Debug.scala:1959:9]
wire [31:0] auto_dmInner_dmInner_sb2tlOpt_out_a_bits_address_0; // @[Debug.scala:1959:9]
wire [7:0] auto_dmInner_dmInner_sb2tlOpt_out_a_bits_data_0; // @[Debug.scala:1959:9]
wire auto_dmInner_dmInner_sb2tlOpt_out_a_valid_0; // @[Debug.scala:1959:9]
wire auto_dmInner_dmInner_sb2tlOpt_out_d_ready_0; // @[Debug.scala:1959:9]
wire auto_dmInner_dmInner_tl_in_a_ready_0; // @[Debug.scala:1959:9]
wire [2:0] auto_dmInner_dmInner_tl_in_d_bits_opcode_0; // @[Debug.scala:1959:9]
wire [1:0] auto_dmInner_dmInner_tl_in_d_bits_size_0; // @[Debug.scala:1959:9]
wire [12:0] auto_dmInner_dmInner_tl_in_d_bits_source_0; // @[Debug.scala:1959:9]
wire [63:0] auto_dmInner_dmInner_tl_in_d_bits_data_0; // @[Debug.scala:1959:9]
wire auto_dmInner_dmInner_tl_in_d_valid_0; // @[Debug.scala:1959:9]
wire auto_dmOuter_int_out_sync_0_0; // @[Debug.scala:1959:9]
wire io_ctrl_ndreset_0; // @[Debug.scala:1959:9]
wire io_ctrl_dmactive_0; // @[Debug.scala:1959:9]
wire io_dmi_dmi_req_ready_0; // @[Debug.scala:1959:9]
wire [31:0] io_dmi_dmi_resp_bits_data_0; // @[Debug.scala:1959:9]
wire [1:0] io_dmi_dmi_resp_bits_resp_0; // @[Debug.scala:1959:9]
wire io_dmi_dmi_resp_valid_0; // @[Debug.scala:1959:9]
TLDebugModuleOuterAsync dmOuter ( // @[Debug.scala:1949:53]
.auto_asource_out_a_mem_0_opcode (_dmOuter_auto_asource_out_a_mem_0_opcode),
.auto_asource_out_a_mem_0_address (_dmOuter_auto_asource_out_a_mem_0_address),
.auto_asource_out_a_mem_0_data (_dmOuter_auto_asource_out_a_mem_0_data),
.auto_asource_out_a_ridx (_dmInner_auto_dmiXing_in_a_ridx), // @[Debug.scala:1950:53]
.auto_asource_out_a_widx (_dmOuter_auto_asource_out_a_widx),
.auto_asource_out_a_safe_ridx_valid (_dmInner_auto_dmiXing_in_a_safe_ridx_valid), // @[Debug.scala:1950:53]
.auto_asource_out_a_safe_widx_valid (_dmOuter_auto_asource_out_a_safe_widx_valid),
.auto_asource_out_a_safe_source_reset_n (_dmOuter_auto_asource_out_a_safe_source_reset_n),
.auto_asource_out_a_safe_sink_reset_n (_dmInner_auto_dmiXing_in_a_safe_sink_reset_n), // @[Debug.scala:1950:53]
.auto_asource_out_d_mem_0_opcode (_dmInner_auto_dmiXing_in_d_mem_0_opcode), // @[Debug.scala:1950:53]
.auto_asource_out_d_mem_0_size (_dmInner_auto_dmiXing_in_d_mem_0_size), // @[Debug.scala:1950:53]
.auto_asource_out_d_mem_0_source (_dmInner_auto_dmiXing_in_d_mem_0_source), // @[Debug.scala:1950:53]
.auto_asource_out_d_mem_0_data (_dmInner_auto_dmiXing_in_d_mem_0_data), // @[Debug.scala:1950:53]
.auto_asource_out_d_ridx (_dmOuter_auto_asource_out_d_ridx),
.auto_asource_out_d_widx (_dmInner_auto_dmiXing_in_d_widx), // @[Debug.scala:1950:53]
.auto_asource_out_d_safe_ridx_valid (_dmOuter_auto_asource_out_d_safe_ridx_valid),
.auto_asource_out_d_safe_widx_valid (_dmInner_auto_dmiXing_in_d_safe_widx_valid), // @[Debug.scala:1950:53]
.auto_asource_out_d_safe_source_reset_n (_dmInner_auto_dmiXing_in_d_safe_source_reset_n), // @[Debug.scala:1950:53]
.auto_asource_out_d_safe_sink_reset_n (_dmOuter_auto_asource_out_d_safe_sink_reset_n),
.auto_int_out_sync_0 (auto_dmOuter_int_out_sync_0_0),
.io_dmi_clock (io_dmi_dmiClock_0), // @[Debug.scala:1959:9]
.io_dmi_reset (io_dmi_dmiReset_0), // @[Debug.scala:1959:9]
.io_dmi_req_ready (io_dmi_dmi_req_ready_0),
.io_dmi_req_valid (io_dmi_dmi_req_valid_0), // @[Debug.scala:1959:9]
.io_dmi_req_bits_addr (io_dmi_dmi_req_bits_addr_0), // @[Debug.scala:1959:9]
.io_dmi_req_bits_data (io_dmi_dmi_req_bits_data_0), // @[Debug.scala:1959:9]
.io_dmi_req_bits_op (io_dmi_dmi_req_bits_op_0), // @[Debug.scala:1959:9]
.io_dmi_resp_ready (io_dmi_dmi_resp_ready_0), // @[Debug.scala:1959:9]
.io_dmi_resp_valid (io_dmi_dmi_resp_valid_0),
.io_dmi_resp_bits_data (io_dmi_dmi_resp_bits_data_0),
.io_dmi_resp_bits_resp (io_dmi_dmi_resp_bits_resp_0),
.io_ctrl_ndreset (io_ctrl_ndreset_0),
.io_ctrl_dmactive (_dmOuter_io_ctrl_dmactive),
.io_ctrl_dmactiveAck (io_ctrl_dmactiveAck_0), // @[Debug.scala:1959:9]
.io_innerCtrl_mem_0_resumereq (_dmOuter_io_innerCtrl_mem_0_resumereq),
.io_innerCtrl_mem_0_hartsel (_dmOuter_io_innerCtrl_mem_0_hartsel),
.io_innerCtrl_mem_0_ackhavereset (_dmOuter_io_innerCtrl_mem_0_ackhavereset),
.io_innerCtrl_mem_0_hrmask_0 (_dmOuter_io_innerCtrl_mem_0_hrmask_0),
.io_innerCtrl_ridx (_dmInner_io_innerCtrl_ridx), // @[Debug.scala:1950:53]
.io_innerCtrl_widx (_dmOuter_io_innerCtrl_widx),
.io_innerCtrl_safe_ridx_valid (_dmInner_io_innerCtrl_safe_ridx_valid), // @[Debug.scala:1950:53]
.io_innerCtrl_safe_widx_valid (_dmOuter_io_innerCtrl_safe_widx_valid),
.io_innerCtrl_safe_source_reset_n (_dmOuter_io_innerCtrl_safe_source_reset_n),
.io_innerCtrl_safe_sink_reset_n (_dmInner_io_innerCtrl_safe_sink_reset_n), // @[Debug.scala:1950:53]
.io_hgDebugInt_0 (_dmInner_io_hgDebugInt_0), // @[Debug.scala:1950:53]
.rf_reset (io_dmi_dmiReset_0) // @[Debug.scala:1959:9]
); // @[Debug.scala:1949:53]
assign io_ctrl_dmactive_0 = _dmOuter_io_ctrl_dmactive; // @[Debug.scala:1949:53, :1959:9]
TLDebugModuleInnerAsync dmInner ( // @[Debug.scala:1950:53]
.auto_dmiXing_in_a_mem_0_opcode (_dmOuter_auto_asource_out_a_mem_0_opcode), // @[Debug.scala:1949:53]
.auto_dmiXing_in_a_mem_0_address (_dmOuter_auto_asource_out_a_mem_0_address), // @[Debug.scala:1949:53]
.auto_dmiXing_in_a_mem_0_data (_dmOuter_auto_asource_out_a_mem_0_data), // @[Debug.scala:1949:53]
.auto_dmiXing_in_a_ridx (_dmInner_auto_dmiXing_in_a_ridx),
.auto_dmiXing_in_a_widx (_dmOuter_auto_asource_out_a_widx), // @[Debug.scala:1949:53]
.auto_dmiXing_in_a_safe_ridx_valid (_dmInner_auto_dmiXing_in_a_safe_ridx_valid),
.auto_dmiXing_in_a_safe_widx_valid (_dmOuter_auto_asource_out_a_safe_widx_valid), // @[Debug.scala:1949:53]
.auto_dmiXing_in_a_safe_source_reset_n (_dmOuter_auto_asource_out_a_safe_source_reset_n), // @[Debug.scala:1949:53]
.auto_dmiXing_in_a_safe_sink_reset_n (_dmInner_auto_dmiXing_in_a_safe_sink_reset_n),
.auto_dmiXing_in_d_mem_0_opcode (_dmInner_auto_dmiXing_in_d_mem_0_opcode),
.auto_dmiXing_in_d_mem_0_size (_dmInner_auto_dmiXing_in_d_mem_0_size),
.auto_dmiXing_in_d_mem_0_source (_dmInner_auto_dmiXing_in_d_mem_0_source),
.auto_dmiXing_in_d_mem_0_data (_dmInner_auto_dmiXing_in_d_mem_0_data),
.auto_dmiXing_in_d_ridx (_dmOuter_auto_asource_out_d_ridx), // @[Debug.scala:1949:53]
.auto_dmiXing_in_d_widx (_dmInner_auto_dmiXing_in_d_widx),
.auto_dmiXing_in_d_safe_ridx_valid (_dmOuter_auto_asource_out_d_safe_ridx_valid), // @[Debug.scala:1949:53]
.auto_dmiXing_in_d_safe_widx_valid (_dmInner_auto_dmiXing_in_d_safe_widx_valid),
.auto_dmiXing_in_d_safe_source_reset_n (_dmInner_auto_dmiXing_in_d_safe_source_reset_n),
.auto_dmiXing_in_d_safe_sink_reset_n (_dmOuter_auto_asource_out_d_safe_sink_reset_n), // @[Debug.scala:1949:53]
.auto_dmInner_sb2tlOpt_out_a_ready (auto_dmInner_dmInner_sb2tlOpt_out_a_ready_0), // @[Debug.scala:1959:9]
.auto_dmInner_sb2tlOpt_out_a_valid (auto_dmInner_dmInner_sb2tlOpt_out_a_valid_0),
.auto_dmInner_sb2tlOpt_out_a_bits_opcode (auto_dmInner_dmInner_sb2tlOpt_out_a_bits_opcode_0),
.auto_dmInner_sb2tlOpt_out_a_bits_size (auto_dmInner_dmInner_sb2tlOpt_out_a_bits_size_0),
.auto_dmInner_sb2tlOpt_out_a_bits_address (auto_dmInner_dmInner_sb2tlOpt_out_a_bits_address_0),
.auto_dmInner_sb2tlOpt_out_a_bits_data (auto_dmInner_dmInner_sb2tlOpt_out_a_bits_data_0),
.auto_dmInner_sb2tlOpt_out_d_ready (auto_dmInner_dmInner_sb2tlOpt_out_d_ready_0),
.auto_dmInner_sb2tlOpt_out_d_valid (auto_dmInner_dmInner_sb2tlOpt_out_d_valid_0), // @[Debug.scala:1959:9]
.auto_dmInner_sb2tlOpt_out_d_bits_opcode (auto_dmInner_dmInner_sb2tlOpt_out_d_bits_opcode_0), // @[Debug.scala:1959:9]
.auto_dmInner_sb2tlOpt_out_d_bits_param (auto_dmInner_dmInner_sb2tlOpt_out_d_bits_param_0), // @[Debug.scala:1959:9]
.auto_dmInner_sb2tlOpt_out_d_bits_size (auto_dmInner_dmInner_sb2tlOpt_out_d_bits_size_0), // @[Debug.scala:1959:9]
.auto_dmInner_sb2tlOpt_out_d_bits_sink (auto_dmInner_dmInner_sb2tlOpt_out_d_bits_sink_0), // @[Debug.scala:1959:9]
.auto_dmInner_sb2tlOpt_out_d_bits_denied (auto_dmInner_dmInner_sb2tlOpt_out_d_bits_denied_0), // @[Debug.scala:1959:9]
.auto_dmInner_sb2tlOpt_out_d_bits_data (auto_dmInner_dmInner_sb2tlOpt_out_d_bits_data_0), // @[Debug.scala:1959:9]
.auto_dmInner_sb2tlOpt_out_d_bits_corrupt (auto_dmInner_dmInner_sb2tlOpt_out_d_bits_corrupt_0), // @[Debug.scala:1959:9]
.auto_dmInner_tl_in_a_ready (auto_dmInner_dmInner_tl_in_a_ready_0),
.auto_dmInner_tl_in_a_valid (auto_dmInner_dmInner_tl_in_a_valid_0), // @[Debug.scala:1959:9]
.auto_dmInner_tl_in_a_bits_opcode (auto_dmInner_dmInner_tl_in_a_bits_opcode_0), // @[Debug.scala:1959:9]
.auto_dmInner_tl_in_a_bits_param (auto_dmInner_dmInner_tl_in_a_bits_param_0), // @[Debug.scala:1959:9]
.auto_dmInner_tl_in_a_bits_size (auto_dmInner_dmInner_tl_in_a_bits_size_0), // @[Debug.scala:1959:9]
.auto_dmInner_tl_in_a_bits_source (auto_dmInner_dmInner_tl_in_a_bits_source_0), // @[Debug.scala:1959:9]
.auto_dmInner_tl_in_a_bits_address (auto_dmInner_dmInner_tl_in_a_bits_address_0), // @[Debug.scala:1959:9]
.auto_dmInner_tl_in_a_bits_mask (auto_dmInner_dmInner_tl_in_a_bits_mask_0), // @[Debug.scala:1959:9]
.auto_dmInner_tl_in_a_bits_data (auto_dmInner_dmInner_tl_in_a_bits_data_0), // @[Debug.scala:1959:9]
.auto_dmInner_tl_in_a_bits_corrupt (auto_dmInner_dmInner_tl_in_a_bits_corrupt_0), // @[Debug.scala:1959:9]
.auto_dmInner_tl_in_d_ready (auto_dmInner_dmInner_tl_in_d_ready_0), // @[Debug.scala:1959:9]
.auto_dmInner_tl_in_d_valid (auto_dmInner_dmInner_tl_in_d_valid_0),
.auto_dmInner_tl_in_d_bits_opcode (auto_dmInner_dmInner_tl_in_d_bits_opcode_0),
.auto_dmInner_tl_in_d_bits_size (auto_dmInner_dmInner_tl_in_d_bits_size_0),
.auto_dmInner_tl_in_d_bits_source (auto_dmInner_dmInner_tl_in_d_bits_source_0),
.auto_dmInner_tl_in_d_bits_data (auto_dmInner_dmInner_tl_in_d_bits_data_0),
.io_debug_clock (io_debug_clock_0), // @[Debug.scala:1959:9]
.io_debug_reset (io_debug_reset_0), // @[Debug.scala:1959:9]
.io_tl_clock (io_tl_clock_0), // @[Debug.scala:1959:9]
.io_tl_reset (io_tl_reset_0), // @[Debug.scala:1959:9]
.io_dmactive (_dmOuter_io_ctrl_dmactive), // @[Debug.scala:1949:53]
.io_innerCtrl_mem_0_resumereq (_dmOuter_io_innerCtrl_mem_0_resumereq), // @[Debug.scala:1949:53]
.io_innerCtrl_mem_0_hartsel (_dmOuter_io_innerCtrl_mem_0_hartsel), // @[Debug.scala:1949:53]
.io_innerCtrl_mem_0_ackhavereset (_dmOuter_io_innerCtrl_mem_0_ackhavereset), // @[Debug.scala:1949:53]
.io_innerCtrl_mem_0_hrmask_0 (_dmOuter_io_innerCtrl_mem_0_hrmask_0), // @[Debug.scala:1949:53]
.io_innerCtrl_ridx (_dmInner_io_innerCtrl_ridx),
.io_innerCtrl_widx (_dmOuter_io_innerCtrl_widx), // @[Debug.scala:1949:53]
.io_innerCtrl_safe_ridx_valid (_dmInner_io_innerCtrl_safe_ridx_valid),
.io_innerCtrl_safe_widx_valid (_dmOuter_io_innerCtrl_safe_widx_valid), // @[Debug.scala:1949:53]
.io_innerCtrl_safe_source_reset_n (_dmOuter_io_innerCtrl_safe_source_reset_n), // @[Debug.scala:1949:53]
.io_innerCtrl_safe_sink_reset_n (_dmInner_io_innerCtrl_safe_sink_reset_n),
.io_hgDebugInt_0 (_dmInner_io_hgDebugInt_0),
.io_hartIsInReset_0 (io_hartIsInReset_0_0), // @[Debug.scala:1959:9]
.rf_reset (io_debug_reset_0) // @[Debug.scala:1959:9]
); // @[Debug.scala:1950:53]
assign auto_dmInner_dmInner_sb2tlOpt_out_a_valid = auto_dmInner_dmInner_sb2tlOpt_out_a_valid_0; // @[Debug.scala:1959:9]
assign auto_dmInner_dmInner_sb2tlOpt_out_a_bits_opcode = auto_dmInner_dmInner_sb2tlOpt_out_a_bits_opcode_0; // @[Debug.scala:1959:9]
assign auto_dmInner_dmInner_sb2tlOpt_out_a_bits_size = auto_dmInner_dmInner_sb2tlOpt_out_a_bits_size_0; // @[Debug.scala:1959:9]
assign auto_dmInner_dmInner_sb2tlOpt_out_a_bits_address = auto_dmInner_dmInner_sb2tlOpt_out_a_bits_address_0; // @[Debug.scala:1959:9]
assign auto_dmInner_dmInner_sb2tlOpt_out_a_bits_data = auto_dmInner_dmInner_sb2tlOpt_out_a_bits_data_0; // @[Debug.scala:1959:9]
assign auto_dmInner_dmInner_sb2tlOpt_out_d_ready = auto_dmInner_dmInner_sb2tlOpt_out_d_ready_0; // @[Debug.scala:1959:9]
assign auto_dmInner_dmInner_tl_in_a_ready = auto_dmInner_dmInner_tl_in_a_ready_0; // @[Debug.scala:1959:9]
assign auto_dmInner_dmInner_tl_in_d_valid = auto_dmInner_dmInner_tl_in_d_valid_0; // @[Debug.scala:1959:9]
assign auto_dmInner_dmInner_tl_in_d_bits_opcode = auto_dmInner_dmInner_tl_in_d_bits_opcode_0; // @[Debug.scala:1959:9]
assign auto_dmInner_dmInner_tl_in_d_bits_size = auto_dmInner_dmInner_tl_in_d_bits_size_0; // @[Debug.scala:1959:9]
assign auto_dmInner_dmInner_tl_in_d_bits_source = auto_dmInner_dmInner_tl_in_d_bits_source_0; // @[Debug.scala:1959:9]
assign auto_dmInner_dmInner_tl_in_d_bits_data = auto_dmInner_dmInner_tl_in_d_bits_data_0; // @[Debug.scala:1959:9]
assign auto_dmOuter_int_out_sync_0 = auto_dmOuter_int_out_sync_0_0; // @[Debug.scala:1959:9]
assign io_ctrl_ndreset = io_ctrl_ndreset_0; // @[Debug.scala:1959:9]
assign io_ctrl_dmactive = io_ctrl_dmactive_0; // @[Debug.scala:1959:9]
assign io_dmi_dmi_req_ready = io_dmi_dmi_req_ready_0; // @[Debug.scala:1959:9]
assign io_dmi_dmi_resp_valid = io_dmi_dmi_resp_valid_0; // @[Debug.scala:1959:9]
assign io_dmi_dmi_resp_bits_data = io_dmi_dmi_resp_bits_data_0; // @[Debug.scala:1959:9]
assign io_dmi_dmi_resp_bits_resp = io_dmi_dmi_resp_bits_resp_0; // @[Debug.scala:1959:9]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor_52( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71]
wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [3:0] source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [3:0] source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [9:0] inflight; // @[Monitor.scala:614:27]
reg [39:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [39:0] inflight_sizes; // @[Monitor.scala:618:33]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire [15:0] _GEN_0 = {12'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35]
wire _GEN_1 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35]
wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46]
wire _GEN_2 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74]
wire [15:0] _GEN_3 = {12'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [9:0] inflight_1; // @[Monitor.scala:726:35]
reg [39:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
| module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_289( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19]
wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to the following Chisel files.
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File Nodes.scala:
package constellation.channel
import chisel3._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Parameters, Field}
import freechips.rocketchip.diplomacy._
case class EmptyParams()
case class ChannelEdgeParams(cp: ChannelParams, p: Parameters)
object ChannelImp extends SimpleNodeImp[EmptyParams, ChannelParams, ChannelEdgeParams, Channel] {
def edge(pd: EmptyParams, pu: ChannelParams, p: Parameters, sourceInfo: SourceInfo) = {
ChannelEdgeParams(pu, p)
}
def bundle(e: ChannelEdgeParams) = new Channel(e.cp)(e.p)
def render(e: ChannelEdgeParams) = if (e.cp.possibleFlows.size == 0) {
RenderedEdge(colour = "ffffff", label = "X")
} else {
RenderedEdge(colour = "#0000ff", label = e.cp.payloadBits.toString)
}
override def monitor(bundle: Channel, edge: ChannelEdgeParams): Unit = {
val monitor = Module(new NoCMonitor(edge.cp)(edge.p))
monitor.io.in := bundle
}
// TODO: Add nodepath stuff? override def mixO, override def mixI
}
case class ChannelSourceNode(val destId: Int)(implicit valName: ValName) extends SourceNode(ChannelImp)(Seq(EmptyParams()))
case class ChannelDestNode(val destParams: ChannelParams)(implicit valName: ValName) extends SinkNode(ChannelImp)(Seq(destParams))
case class ChannelAdapterNode(
slaveFn: ChannelParams => ChannelParams = { d => d })(
implicit valName: ValName) extends AdapterNode(ChannelImp)((e: EmptyParams) => e, slaveFn)
case class ChannelIdentityNode()(implicit valName: ValName) extends IdentityNode(ChannelImp)()
case class ChannelEphemeralNode()(implicit valName: ValName) extends EphemeralNode(ChannelImp)()
case class IngressChannelEdgeParams(cp: IngressChannelParams, p: Parameters)
case class EgressChannelEdgeParams(cp: EgressChannelParams, p: Parameters)
object IngressChannelImp extends SimpleNodeImp[EmptyParams, IngressChannelParams, IngressChannelEdgeParams, IngressChannel] {
def edge(pd: EmptyParams, pu: IngressChannelParams, p: Parameters, sourceInfo: SourceInfo) = {
IngressChannelEdgeParams(pu, p)
}
def bundle(e: IngressChannelEdgeParams) = new IngressChannel(e.cp)(e.p)
def render(e: IngressChannelEdgeParams) = if (e.cp.possibleFlows.size == 0) {
RenderedEdge(colour = "ffffff", label = "X")
} else {
RenderedEdge(colour = "#00ff00", label = e.cp.payloadBits.toString)
}
}
object EgressChannelImp extends SimpleNodeImp[EmptyParams, EgressChannelParams, EgressChannelEdgeParams, EgressChannel] {
def edge(pd: EmptyParams, pu: EgressChannelParams, p: Parameters, sourceInfo: SourceInfo) = {
EgressChannelEdgeParams(pu, p)
}
def bundle(e: EgressChannelEdgeParams) = new EgressChannel(e.cp)(e.p)
def render(e: EgressChannelEdgeParams) = if (e.cp.possibleFlows.size == 0) {
RenderedEdge(colour = "ffffff", label = "X")
} else {
RenderedEdge(colour = "#ff0000", label = e.cp.payloadBits.toString)
}
}
case class IngressChannelSourceNode(val destId: Int)(implicit valName: ValName) extends SourceNode(IngressChannelImp)(Seq(EmptyParams()))
case class IngressChannelDestNode(val destParams: IngressChannelParams)(implicit valName: ValName) extends SinkNode(IngressChannelImp)(Seq(destParams))
case class EgressChannelSourceNode(val egressId: Int)(implicit valName: ValName) extends SourceNode(EgressChannelImp)(Seq(EmptyParams()))
case class EgressChannelDestNode(val destParams: EgressChannelParams)(implicit valName: ValName) extends SinkNode(EgressChannelImp)(Seq(destParams))
case class IngressChannelAdapterNode(
slaveFn: IngressChannelParams => IngressChannelParams = { d => d })(
implicit valName: ValName) extends AdapterNode(IngressChannelImp)(m => m, slaveFn)
case class EgressChannelAdapterNode(
slaveFn: EgressChannelParams => EgressChannelParams = { d => d })(
implicit valName: ValName) extends AdapterNode(EgressChannelImp)(m => m, slaveFn)
case class IngressChannelIdentityNode()(implicit valName: ValName) extends IdentityNode(IngressChannelImp)()
case class EgressChannelIdentityNode()(implicit valName: ValName) extends IdentityNode(EgressChannelImp)()
case class IngressChannelEphemeralNode()(implicit valName: ValName) extends EphemeralNode(IngressChannelImp)()
case class EgressChannelEphemeralNode()(implicit valName: ValName) extends EphemeralNode(EgressChannelImp)()
File Router.scala:
package constellation.router
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.util._
import constellation.channel._
import constellation.routing.{RoutingRelation}
import constellation.noc.{HasNoCParams}
case class UserRouterParams(
// Payload width. Must match payload width on all channels attached to this routing node
payloadBits: Int = 64,
// Combines SA and ST stages (removes pipeline register)
combineSAST: Boolean = false,
// Combines RC and VA stages (removes pipeline register)
combineRCVA: Boolean = false,
// Adds combinational path from SA to VA
coupleSAVA: Boolean = false,
vcAllocator: VCAllocatorParams => Parameters => VCAllocator = (vP) => (p) => new RotatingSingleVCAllocator(vP)(p)
)
case class RouterParams(
nodeId: Int,
nIngress: Int,
nEgress: Int,
user: UserRouterParams
)
trait HasRouterOutputParams {
def outParams: Seq[ChannelParams]
def egressParams: Seq[EgressChannelParams]
def allOutParams = outParams ++ egressParams
def nOutputs = outParams.size
def nEgress = egressParams.size
def nAllOutputs = allOutParams.size
}
trait HasRouterInputParams {
def inParams: Seq[ChannelParams]
def ingressParams: Seq[IngressChannelParams]
def allInParams = inParams ++ ingressParams
def nInputs = inParams.size
def nIngress = ingressParams.size
def nAllInputs = allInParams.size
}
trait HasRouterParams
{
def routerParams: RouterParams
def nodeId = routerParams.nodeId
def payloadBits = routerParams.user.payloadBits
}
class DebugBundle(val nIn: Int) extends Bundle {
val va_stall = Vec(nIn, UInt())
val sa_stall = Vec(nIn, UInt())
}
class Router(
val routerParams: RouterParams,
preDiplomaticInParams: Seq[ChannelParams],
preDiplomaticIngressParams: Seq[IngressChannelParams],
outDests: Seq[Int],
egressIds: Seq[Int]
)(implicit p: Parameters) extends LazyModule with HasNoCParams with HasRouterParams {
val allPreDiplomaticInParams = preDiplomaticInParams ++ preDiplomaticIngressParams
val destNodes = preDiplomaticInParams.map(u => ChannelDestNode(u))
val sourceNodes = outDests.map(u => ChannelSourceNode(u))
val ingressNodes = preDiplomaticIngressParams.map(u => IngressChannelDestNode(u))
val egressNodes = egressIds.map(u => EgressChannelSourceNode(u))
val debugNode = BundleBridgeSource(() => new DebugBundle(allPreDiplomaticInParams.size))
val ctrlNode = if (hasCtrl) Some(BundleBridgeSource(() => new RouterCtrlBundle)) else None
def inParams = module.inParams
def outParams = module.outParams
def ingressParams = module.ingressParams
def egressParams = module.egressParams
lazy val module = new LazyModuleImp(this) with HasRouterInputParams with HasRouterOutputParams {
val (io_in, edgesIn) = destNodes.map(_.in(0)).unzip
val (io_out, edgesOut) = sourceNodes.map(_.out(0)).unzip
val (io_ingress, edgesIngress) = ingressNodes.map(_.in(0)).unzip
val (io_egress, edgesEgress) = egressNodes.map(_.out(0)).unzip
val io_debug = debugNode.out(0)._1
val inParams = edgesIn.map(_.cp)
val outParams = edgesOut.map(_.cp)
val ingressParams = edgesIngress.map(_.cp)
val egressParams = edgesEgress.map(_.cp)
allOutParams.foreach(u => require(u.srcId == nodeId && u.payloadBits == routerParams.user.payloadBits))
allInParams.foreach(u => require(u.destId == nodeId && u.payloadBits == routerParams.user.payloadBits))
require(nIngress == routerParams.nIngress)
require(nEgress == routerParams.nEgress)
require(nAllInputs >= 1)
require(nAllOutputs >= 1)
require(nodeId < (1 << nodeIdBits))
val input_units = inParams.zipWithIndex.map { case (u,i) =>
Module(new InputUnit(u, outParams, egressParams,
routerParams.user.combineRCVA, routerParams.user.combineSAST))
.suggestName(s"input_unit_${i}_from_${u.srcId}") }
val ingress_units = ingressParams.zipWithIndex.map { case (u,i) =>
Module(new IngressUnit(i, u, outParams, egressParams,
routerParams.user.combineRCVA, routerParams.user.combineSAST))
.suggestName(s"ingress_unit_${i+nInputs}_from_${u.ingressId}") }
val all_input_units = input_units ++ ingress_units
val output_units = outParams.zipWithIndex.map { case (u,i) =>
Module(new OutputUnit(inParams, ingressParams, u))
.suggestName(s"output_unit_${i}_to_${u.destId}")}
val egress_units = egressParams.zipWithIndex.map { case (u,i) =>
Module(new EgressUnit(routerParams.user.coupleSAVA && all_input_units.size == 1,
routerParams.user.combineSAST,
inParams, ingressParams, u))
.suggestName(s"egress_unit_${i+nOutputs}_to_${u.egressId}")}
val all_output_units = output_units ++ egress_units
val switch = Module(new Switch(routerParams, inParams, outParams, ingressParams, egressParams))
val switch_allocator = Module(new SwitchAllocator(routerParams, inParams, outParams, ingressParams, egressParams))
val vc_allocator = Module(routerParams.user.vcAllocator(
VCAllocatorParams(routerParams, inParams, outParams, ingressParams, egressParams)
)(p))
val route_computer = Module(new RouteComputer(routerParams, inParams, outParams, ingressParams, egressParams))
val fires_count = WireInit(PopCount(vc_allocator.io.req.map(_.fire)))
dontTouch(fires_count)
(io_in zip input_units ).foreach { case (i,u) => u.io.in <> i }
(io_ingress zip ingress_units).foreach { case (i,u) => u.io.in <> i.flit }
(output_units zip io_out ).foreach { case (u,o) => o <> u.io.out }
(egress_units zip io_egress).foreach { case (u,o) => o.flit <> u.io.out }
(route_computer.io.req zip all_input_units).foreach {
case (i,u) => i <> u.io.router_req }
(all_input_units zip route_computer.io.resp).foreach {
case (u,o) => u.io.router_resp <> o }
(vc_allocator.io.req zip all_input_units).foreach {
case (i,u) => i <> u.io.vcalloc_req }
(all_input_units zip vc_allocator.io.resp).foreach {
case (u,o) => u.io.vcalloc_resp <> o }
(all_output_units zip vc_allocator.io.out_allocs).foreach {
case (u,a) => u.io.allocs <> a }
(vc_allocator.io.channel_status zip all_output_units).foreach {
case (a,u) => a := u.io.channel_status }
all_input_units.foreach(in => all_output_units.zipWithIndex.foreach { case (out,outIdx) =>
in.io.out_credit_available(outIdx) := out.io.credit_available
})
(all_input_units zip switch_allocator.io.req).foreach {
case (u,r) => r <> u.io.salloc_req }
(all_output_units zip switch_allocator.io.credit_alloc).foreach {
case (u,a) => u.io.credit_alloc := a }
(switch.io.in zip all_input_units).foreach {
case (i,u) => i <> u.io.out }
(all_output_units zip switch.io.out).foreach {
case (u,o) => u.io.in <> o }
switch.io.sel := (if (routerParams.user.combineSAST) {
switch_allocator.io.switch_sel
} else {
RegNext(switch_allocator.io.switch_sel)
})
if (hasCtrl) {
val io_ctrl = ctrlNode.get.out(0)._1
val ctrl = Module(new RouterControlUnit(routerParams, inParams, outParams, ingressParams, egressParams))
io_ctrl <> ctrl.io.ctrl
(all_input_units zip ctrl.io.in_block ).foreach { case (l,r) => l.io.block := r }
(all_input_units zip ctrl.io.in_fire ).foreach { case (l,r) => r := l.io.out.map(_.valid) }
} else {
input_units.foreach(_.io.block := false.B)
ingress_units.foreach(_.io.block := false.B)
}
(io_debug.va_stall zip all_input_units.map(_.io.debug.va_stall)).map { case (l,r) => l := r }
(io_debug.sa_stall zip all_input_units.map(_.io.debug.sa_stall)).map { case (l,r) => l := r }
val debug_tsc = RegInit(0.U(64.W))
debug_tsc := debug_tsc + 1.U
val debug_sample = RegInit(0.U(64.W))
debug_sample := debug_sample + 1.U
val sample_rate = PlusArg("noc_util_sample_rate", width=20)
when (debug_sample === sample_rate - 1.U) { debug_sample := 0.U }
def sample(fire: Bool, s: String) = {
val util_ctr = RegInit(0.U(64.W))
val fired = RegInit(false.B)
util_ctr := util_ctr + fire
fired := fired || fire
when (sample_rate =/= 0.U && debug_sample === sample_rate - 1.U && fired) {
val fmtStr = s"nocsample %d $s %d\n"
printf(fmtStr, debug_tsc, util_ctr);
fired := fire
}
}
destNodes.map(_.in(0)).foreach { case (in, edge) => in.flit.map { f =>
sample(f.fire, s"${edge.cp.srcId} $nodeId")
} }
ingressNodes.map(_.in(0)).foreach { case (in, edge) =>
sample(in.flit.fire, s"i${edge.cp.asInstanceOf[IngressChannelParams].ingressId} $nodeId")
}
egressNodes.map(_.out(0)).foreach { case (out, edge) =>
sample(out.flit.fire, s"$nodeId e${edge.cp.asInstanceOf[EgressChannelParams].egressId}")
}
}
}
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
| module Router_29( // @[Router.scala:89:25]
input clock, // @[Router.scala:89:25]
input reset, // @[Router.scala:89:25]
output [4:0] auto_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_1_flit_0_valid, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_source_nodes_out_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_source_nodes_out_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_source_nodes_out_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_source_nodes_out_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_source_nodes_out_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_source_nodes_out_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_source_nodes_out_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
input [21:0] auto_source_nodes_out_1_credit_return, // @[LazyModuleImp.scala:107:25]
input [21:0] auto_source_nodes_out_1_vc_free, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_0_flit_0_valid, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_source_nodes_out_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_source_nodes_out_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_source_nodes_out_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_source_nodes_out_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_source_nodes_out_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_source_nodes_out_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_source_nodes_out_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
input [21:0] auto_source_nodes_out_0_credit_return, // @[LazyModuleImp.scala:107:25]
input [21:0] auto_source_nodes_out_0_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_1_flit_0_valid, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_dest_nodes_in_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_dest_nodes_in_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_dest_nodes_in_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_dest_nodes_in_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_dest_nodes_in_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
output [21:0] auto_dest_nodes_in_1_credit_return, // @[LazyModuleImp.scala:107:25]
output [21:0] auto_dest_nodes_in_1_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_0_flit_0_valid, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_dest_nodes_in_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_dest_nodes_in_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_dest_nodes_in_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_dest_nodes_in_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_dest_nodes_in_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
output [21:0] auto_dest_nodes_in_0_credit_return, // @[LazyModuleImp.scala:107:25]
output [21:0] auto_dest_nodes_in_0_vc_free // @[LazyModuleImp.scala:107:25]
);
wire [19:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire _route_computer_io_resp_1_vc_sel_0_12; // @[Router.scala:136:32]
wire _route_computer_io_resp_1_vc_sel_0_13; // @[Router.scala:136:32]
wire _route_computer_io_resp_1_vc_sel_0_16; // @[Router.scala:136:32]
wire _route_computer_io_resp_1_vc_sel_0_17; // @[Router.scala:136:32]
wire _route_computer_io_resp_1_vc_sel_0_20; // @[Router.scala:136:32]
wire _route_computer_io_resp_1_vc_sel_0_21; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_1_10; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_1_11; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_1_14; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_1_15; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_1_18; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_1_19; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_1_20; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_1_21; // @[Router.scala:136:32]
wire _vc_allocator_io_req_1_ready; // @[Router.scala:133:30]
wire _vc_allocator_io_req_0_ready; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_12; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_13; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_16; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_17; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_20; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_21; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_1_10; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_1_11; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_1_14; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_1_15; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_1_18; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_1_19; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_1_20; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_1_21; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_1_10_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_1_11_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_1_14_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_1_15_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_1_18_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_1_19_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_1_20_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_1_21_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_12_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_13_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_16_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_17_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_20_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_21_alloc; // @[Router.scala:133:30]
wire _switch_allocator_io_req_1_0_ready; // @[Router.scala:132:34]
wire _switch_allocator_io_req_0_0_ready; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_1_10_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_1_11_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_1_14_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_1_15_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_1_18_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_1_19_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_1_20_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_1_21_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_12_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_13_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_16_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_17_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_20_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_21_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_1_0_1_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_1_0_0_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_0_0_1_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_0_0_0_0; // @[Router.scala:132:34]
wire _switch_io_out_1_0_valid; // @[Router.scala:131:24]
wire _switch_io_out_1_0_bits_head; // @[Router.scala:131:24]
wire _switch_io_out_1_0_bits_tail; // @[Router.scala:131:24]
wire [72:0] _switch_io_out_1_0_bits_payload; // @[Router.scala:131:24]
wire [3:0] _switch_io_out_1_0_bits_flow_vnet_id; // @[Router.scala:131:24]
wire [5:0] _switch_io_out_1_0_bits_flow_ingress_node; // @[Router.scala:131:24]
wire [2:0] _switch_io_out_1_0_bits_flow_ingress_node_id; // @[Router.scala:131:24]
wire [5:0] _switch_io_out_1_0_bits_flow_egress_node; // @[Router.scala:131:24]
wire [2:0] _switch_io_out_1_0_bits_flow_egress_node_id; // @[Router.scala:131:24]
wire [4:0] _switch_io_out_1_0_bits_virt_channel_id; // @[Router.scala:131:24]
wire _switch_io_out_0_0_valid; // @[Router.scala:131:24]
wire _switch_io_out_0_0_bits_head; // @[Router.scala:131:24]
wire _switch_io_out_0_0_bits_tail; // @[Router.scala:131:24]
wire [72:0] _switch_io_out_0_0_bits_payload; // @[Router.scala:131:24]
wire [3:0] _switch_io_out_0_0_bits_flow_vnet_id; // @[Router.scala:131:24]
wire [5:0] _switch_io_out_0_0_bits_flow_ingress_node; // @[Router.scala:131:24]
wire [2:0] _switch_io_out_0_0_bits_flow_ingress_node_id; // @[Router.scala:131:24]
wire [5:0] _switch_io_out_0_0_bits_flow_egress_node; // @[Router.scala:131:24]
wire [2:0] _switch_io_out_0_0_bits_flow_egress_node_id; // @[Router.scala:131:24]
wire [4:0] _switch_io_out_0_0_bits_virt_channel_id; // @[Router.scala:131:24]
wire _output_unit_1_to_33_io_credit_available_10; // @[Router.scala:122:13]
wire _output_unit_1_to_33_io_credit_available_11; // @[Router.scala:122:13]
wire _output_unit_1_to_33_io_credit_available_14; // @[Router.scala:122:13]
wire _output_unit_1_to_33_io_credit_available_15; // @[Router.scala:122:13]
wire _output_unit_1_to_33_io_credit_available_18; // @[Router.scala:122:13]
wire _output_unit_1_to_33_io_credit_available_19; // @[Router.scala:122:13]
wire _output_unit_1_to_33_io_credit_available_20; // @[Router.scala:122:13]
wire _output_unit_1_to_33_io_credit_available_21; // @[Router.scala:122:13]
wire _output_unit_1_to_33_io_channel_status_10_occupied; // @[Router.scala:122:13]
wire _output_unit_1_to_33_io_channel_status_11_occupied; // @[Router.scala:122:13]
wire _output_unit_1_to_33_io_channel_status_14_occupied; // @[Router.scala:122:13]
wire _output_unit_1_to_33_io_channel_status_15_occupied; // @[Router.scala:122:13]
wire _output_unit_1_to_33_io_channel_status_18_occupied; // @[Router.scala:122:13]
wire _output_unit_1_to_33_io_channel_status_19_occupied; // @[Router.scala:122:13]
wire _output_unit_1_to_33_io_channel_status_20_occupied; // @[Router.scala:122:13]
wire _output_unit_1_to_33_io_channel_status_21_occupied; // @[Router.scala:122:13]
wire _output_unit_0_to_14_io_credit_available_12; // @[Router.scala:122:13]
wire _output_unit_0_to_14_io_credit_available_13; // @[Router.scala:122:13]
wire _output_unit_0_to_14_io_credit_available_16; // @[Router.scala:122:13]
wire _output_unit_0_to_14_io_credit_available_17; // @[Router.scala:122:13]
wire _output_unit_0_to_14_io_credit_available_20; // @[Router.scala:122:13]
wire _output_unit_0_to_14_io_credit_available_21; // @[Router.scala:122:13]
wire _output_unit_0_to_14_io_channel_status_12_occupied; // @[Router.scala:122:13]
wire _output_unit_0_to_14_io_channel_status_13_occupied; // @[Router.scala:122:13]
wire _output_unit_0_to_14_io_channel_status_16_occupied; // @[Router.scala:122:13]
wire _output_unit_0_to_14_io_channel_status_17_occupied; // @[Router.scala:122:13]
wire _output_unit_0_to_14_io_channel_status_20_occupied; // @[Router.scala:122:13]
wire _output_unit_0_to_14_io_channel_status_21_occupied; // @[Router.scala:122:13]
wire [4:0] _input_unit_1_from_33_io_router_req_bits_src_virt_id; // @[Router.scala:112:13]
wire [3:0] _input_unit_1_from_33_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13]
wire [5:0] _input_unit_1_from_33_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13]
wire [2:0] _input_unit_1_from_33_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13]
wire [5:0] _input_unit_1_from_33_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13]
wire [2:0] _input_unit_1_from_33_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13]
wire _input_unit_1_from_33_io_vcalloc_req_valid; // @[Router.scala:112:13]
wire _input_unit_1_from_33_io_vcalloc_req_bits_vc_sel_0_12; // @[Router.scala:112:13]
wire _input_unit_1_from_33_io_vcalloc_req_bits_vc_sel_0_13; // @[Router.scala:112:13]
wire _input_unit_1_from_33_io_vcalloc_req_bits_vc_sel_0_16; // @[Router.scala:112:13]
wire _input_unit_1_from_33_io_vcalloc_req_bits_vc_sel_0_17; // @[Router.scala:112:13]
wire _input_unit_1_from_33_io_vcalloc_req_bits_vc_sel_0_20; // @[Router.scala:112:13]
wire _input_unit_1_from_33_io_vcalloc_req_bits_vc_sel_0_21; // @[Router.scala:112:13]
wire _input_unit_1_from_33_io_salloc_req_0_valid; // @[Router.scala:112:13]
wire _input_unit_1_from_33_io_salloc_req_0_bits_vc_sel_1_2; // @[Router.scala:112:13]
wire _input_unit_1_from_33_io_salloc_req_0_bits_vc_sel_1_3; // @[Router.scala:112:13]
wire _input_unit_1_from_33_io_salloc_req_0_bits_vc_sel_1_8; // @[Router.scala:112:13]
wire _input_unit_1_from_33_io_salloc_req_0_bits_vc_sel_1_9; // @[Router.scala:112:13]
wire _input_unit_1_from_33_io_salloc_req_0_bits_vc_sel_1_10; // @[Router.scala:112:13]
wire _input_unit_1_from_33_io_salloc_req_0_bits_vc_sel_1_11; // @[Router.scala:112:13]
wire _input_unit_1_from_33_io_salloc_req_0_bits_vc_sel_1_12; // @[Router.scala:112:13]
wire _input_unit_1_from_33_io_salloc_req_0_bits_vc_sel_1_13; // @[Router.scala:112:13]
wire _input_unit_1_from_33_io_salloc_req_0_bits_vc_sel_1_14; // @[Router.scala:112:13]
wire _input_unit_1_from_33_io_salloc_req_0_bits_vc_sel_1_15; // @[Router.scala:112:13]
wire _input_unit_1_from_33_io_salloc_req_0_bits_vc_sel_1_16; // @[Router.scala:112:13]
wire _input_unit_1_from_33_io_salloc_req_0_bits_vc_sel_1_17; // @[Router.scala:112:13]
wire _input_unit_1_from_33_io_salloc_req_0_bits_vc_sel_1_18; // @[Router.scala:112:13]
wire _input_unit_1_from_33_io_salloc_req_0_bits_vc_sel_1_19; // @[Router.scala:112:13]
wire _input_unit_1_from_33_io_salloc_req_0_bits_vc_sel_1_20; // @[Router.scala:112:13]
wire _input_unit_1_from_33_io_salloc_req_0_bits_vc_sel_1_21; // @[Router.scala:112:13]
wire _input_unit_1_from_33_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:112:13]
wire _input_unit_1_from_33_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:112:13]
wire _input_unit_1_from_33_io_salloc_req_0_bits_vc_sel_0_8; // @[Router.scala:112:13]
wire _input_unit_1_from_33_io_salloc_req_0_bits_vc_sel_0_9; // @[Router.scala:112:13]
wire _input_unit_1_from_33_io_salloc_req_0_bits_vc_sel_0_10; // @[Router.scala:112:13]
wire _input_unit_1_from_33_io_salloc_req_0_bits_vc_sel_0_11; // @[Router.scala:112:13]
wire _input_unit_1_from_33_io_salloc_req_0_bits_vc_sel_0_12; // @[Router.scala:112:13]
wire _input_unit_1_from_33_io_salloc_req_0_bits_vc_sel_0_13; // @[Router.scala:112:13]
wire _input_unit_1_from_33_io_salloc_req_0_bits_vc_sel_0_14; // @[Router.scala:112:13]
wire _input_unit_1_from_33_io_salloc_req_0_bits_vc_sel_0_15; // @[Router.scala:112:13]
wire _input_unit_1_from_33_io_salloc_req_0_bits_vc_sel_0_16; // @[Router.scala:112:13]
wire _input_unit_1_from_33_io_salloc_req_0_bits_vc_sel_0_17; // @[Router.scala:112:13]
wire _input_unit_1_from_33_io_salloc_req_0_bits_vc_sel_0_18; // @[Router.scala:112:13]
wire _input_unit_1_from_33_io_salloc_req_0_bits_vc_sel_0_19; // @[Router.scala:112:13]
wire _input_unit_1_from_33_io_salloc_req_0_bits_vc_sel_0_20; // @[Router.scala:112:13]
wire _input_unit_1_from_33_io_salloc_req_0_bits_vc_sel_0_21; // @[Router.scala:112:13]
wire _input_unit_1_from_33_io_salloc_req_0_bits_tail; // @[Router.scala:112:13]
wire _input_unit_1_from_33_io_out_0_valid; // @[Router.scala:112:13]
wire _input_unit_1_from_33_io_out_0_bits_flit_head; // @[Router.scala:112:13]
wire _input_unit_1_from_33_io_out_0_bits_flit_tail; // @[Router.scala:112:13]
wire [72:0] _input_unit_1_from_33_io_out_0_bits_flit_payload; // @[Router.scala:112:13]
wire [3:0] _input_unit_1_from_33_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13]
wire [5:0] _input_unit_1_from_33_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13]
wire [2:0] _input_unit_1_from_33_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13]
wire [5:0] _input_unit_1_from_33_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13]
wire [2:0] _input_unit_1_from_33_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13]
wire [4:0] _input_unit_1_from_33_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13]
wire [4:0] _input_unit_0_from_14_io_router_req_bits_src_virt_id; // @[Router.scala:112:13]
wire [3:0] _input_unit_0_from_14_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13]
wire [5:0] _input_unit_0_from_14_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13]
wire [2:0] _input_unit_0_from_14_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13]
wire [5:0] _input_unit_0_from_14_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13]
wire [2:0] _input_unit_0_from_14_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13]
wire _input_unit_0_from_14_io_vcalloc_req_valid; // @[Router.scala:112:13]
wire _input_unit_0_from_14_io_vcalloc_req_bits_vc_sel_1_10; // @[Router.scala:112:13]
wire _input_unit_0_from_14_io_vcalloc_req_bits_vc_sel_1_11; // @[Router.scala:112:13]
wire _input_unit_0_from_14_io_vcalloc_req_bits_vc_sel_1_14; // @[Router.scala:112:13]
wire _input_unit_0_from_14_io_vcalloc_req_bits_vc_sel_1_15; // @[Router.scala:112:13]
wire _input_unit_0_from_14_io_vcalloc_req_bits_vc_sel_1_18; // @[Router.scala:112:13]
wire _input_unit_0_from_14_io_vcalloc_req_bits_vc_sel_1_19; // @[Router.scala:112:13]
wire _input_unit_0_from_14_io_vcalloc_req_bits_vc_sel_1_20; // @[Router.scala:112:13]
wire _input_unit_0_from_14_io_vcalloc_req_bits_vc_sel_1_21; // @[Router.scala:112:13]
wire _input_unit_0_from_14_io_salloc_req_0_valid; // @[Router.scala:112:13]
wire _input_unit_0_from_14_io_salloc_req_0_bits_vc_sel_1_2; // @[Router.scala:112:13]
wire _input_unit_0_from_14_io_salloc_req_0_bits_vc_sel_1_3; // @[Router.scala:112:13]
wire _input_unit_0_from_14_io_salloc_req_0_bits_vc_sel_1_8; // @[Router.scala:112:13]
wire _input_unit_0_from_14_io_salloc_req_0_bits_vc_sel_1_9; // @[Router.scala:112:13]
wire _input_unit_0_from_14_io_salloc_req_0_bits_vc_sel_1_10; // @[Router.scala:112:13]
wire _input_unit_0_from_14_io_salloc_req_0_bits_vc_sel_1_11; // @[Router.scala:112:13]
wire _input_unit_0_from_14_io_salloc_req_0_bits_vc_sel_1_12; // @[Router.scala:112:13]
wire _input_unit_0_from_14_io_salloc_req_0_bits_vc_sel_1_13; // @[Router.scala:112:13]
wire _input_unit_0_from_14_io_salloc_req_0_bits_vc_sel_1_14; // @[Router.scala:112:13]
wire _input_unit_0_from_14_io_salloc_req_0_bits_vc_sel_1_15; // @[Router.scala:112:13]
wire _input_unit_0_from_14_io_salloc_req_0_bits_vc_sel_1_16; // @[Router.scala:112:13]
wire _input_unit_0_from_14_io_salloc_req_0_bits_vc_sel_1_17; // @[Router.scala:112:13]
wire _input_unit_0_from_14_io_salloc_req_0_bits_vc_sel_1_18; // @[Router.scala:112:13]
wire _input_unit_0_from_14_io_salloc_req_0_bits_vc_sel_1_19; // @[Router.scala:112:13]
wire _input_unit_0_from_14_io_salloc_req_0_bits_vc_sel_1_20; // @[Router.scala:112:13]
wire _input_unit_0_from_14_io_salloc_req_0_bits_vc_sel_1_21; // @[Router.scala:112:13]
wire _input_unit_0_from_14_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:112:13]
wire _input_unit_0_from_14_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:112:13]
wire _input_unit_0_from_14_io_salloc_req_0_bits_vc_sel_0_8; // @[Router.scala:112:13]
wire _input_unit_0_from_14_io_salloc_req_0_bits_vc_sel_0_9; // @[Router.scala:112:13]
wire _input_unit_0_from_14_io_salloc_req_0_bits_vc_sel_0_10; // @[Router.scala:112:13]
wire _input_unit_0_from_14_io_salloc_req_0_bits_vc_sel_0_11; // @[Router.scala:112:13]
wire _input_unit_0_from_14_io_salloc_req_0_bits_vc_sel_0_12; // @[Router.scala:112:13]
wire _input_unit_0_from_14_io_salloc_req_0_bits_vc_sel_0_13; // @[Router.scala:112:13]
wire _input_unit_0_from_14_io_salloc_req_0_bits_vc_sel_0_14; // @[Router.scala:112:13]
wire _input_unit_0_from_14_io_salloc_req_0_bits_vc_sel_0_15; // @[Router.scala:112:13]
wire _input_unit_0_from_14_io_salloc_req_0_bits_vc_sel_0_16; // @[Router.scala:112:13]
wire _input_unit_0_from_14_io_salloc_req_0_bits_vc_sel_0_17; // @[Router.scala:112:13]
wire _input_unit_0_from_14_io_salloc_req_0_bits_vc_sel_0_18; // @[Router.scala:112:13]
wire _input_unit_0_from_14_io_salloc_req_0_bits_vc_sel_0_19; // @[Router.scala:112:13]
wire _input_unit_0_from_14_io_salloc_req_0_bits_vc_sel_0_20; // @[Router.scala:112:13]
wire _input_unit_0_from_14_io_salloc_req_0_bits_vc_sel_0_21; // @[Router.scala:112:13]
wire _input_unit_0_from_14_io_salloc_req_0_bits_tail; // @[Router.scala:112:13]
wire _input_unit_0_from_14_io_out_0_valid; // @[Router.scala:112:13]
wire _input_unit_0_from_14_io_out_0_bits_flit_head; // @[Router.scala:112:13]
wire _input_unit_0_from_14_io_out_0_bits_flit_tail; // @[Router.scala:112:13]
wire [72:0] _input_unit_0_from_14_io_out_0_bits_flit_payload; // @[Router.scala:112:13]
wire [3:0] _input_unit_0_from_14_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13]
wire [5:0] _input_unit_0_from_14_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13]
wire [2:0] _input_unit_0_from_14_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13]
wire [5:0] _input_unit_0_from_14_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13]
wire [2:0] _input_unit_0_from_14_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13]
wire [4:0] _input_unit_0_from_14_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13]
wire [1:0] fires_count = {1'h0, _vc_allocator_io_req_0_ready & _input_unit_0_from_14_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_1_ready & _input_unit_1_from_33_io_vcalloc_req_valid}; // @[Decoupled.scala:51:35]
reg REG_1_0_1_0; // @[Router.scala:178:14]
reg REG_1_0_0_0; // @[Router.scala:178:14]
reg REG_0_0_1_0; // @[Router.scala:178:14]
reg REG_0_0_0_0; // @[Router.scala:178:14]
reg [63:0] debug_tsc; // @[Router.scala:195:28]
reg [63:0] debug_sample; // @[Router.scala:197:31]
wire _GEN = debug_sample == {44'h0, _plusarg_reader_out - 20'h1}; // @[PlusArg.scala:80:11]
reg [63:0] util_ctr; // @[Router.scala:203:29]
reg fired; // @[Router.scala:204:26]
wire _GEN_0 = (|_plusarg_reader_out) & _GEN; // @[PlusArg.scala:80:11]
wire _GEN_1 = _GEN_0 & fired; // @[Router.scala:204:26, :207:{33,71}]
reg [63:0] util_ctr_1; // @[Router.scala:203:29]
reg fired_1; // @[Router.scala:204:26]
wire _GEN_2 = _GEN_0 & fired_1; // @[Router.scala:204:26, :207:{33,71}] |
Generate the Verilog code corresponding to the following Chisel files.
File PE.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle {
val dataflow = UInt(1.W) // TODO make this an Enum
val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)?
val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats
}
class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module {
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(inputType)
val in_c = Input(cType)
val out_d = Output(dType)
})
io.out_d := io.in_c.mac(io.in_a, io.in_b)
}
// TODO update documentation
/**
* A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh.
* @param width Data width of operands
*/
class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int)
(implicit ev: Arithmetic[T]) extends Module { // Debugging variables
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(outputType)
val in_d = Input(outputType)
val out_a = Output(inputType)
val out_b = Output(outputType)
val out_c = Output(outputType)
val in_control = Input(new PEControl(accType))
val out_control = Output(new PEControl(accType))
val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W))
val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W))
val in_last = Input(Bool())
val out_last = Output(Bool())
val in_valid = Input(Bool())
val out_valid = Output(Bool())
val bad_dataflow = Output(Bool())
})
val cType = if (df == Dataflow.WS) inputType else accType
// When creating PEs that support multiple dataflows, the
// elaboration/synthesis tools often fail to consolidate and de-duplicate
// MAC units. To force mac circuitry to be re-used, we create a "mac_unit"
// module here which just performs a single MAC operation
val mac_unit = Module(new MacUnit(inputType,
if (df == Dataflow.WS) outputType else accType, outputType))
val a = io.in_a
val b = io.in_b
val d = io.in_d
val c1 = Reg(cType)
val c2 = Reg(cType)
val dataflow = io.in_control.dataflow
val prop = io.in_control.propagate
val shift = io.in_control.shift
val id = io.in_id
val last = io.in_last
val valid = io.in_valid
io.out_a := a
io.out_control.dataflow := dataflow
io.out_control.propagate := prop
io.out_control.shift := shift
io.out_id := id
io.out_last := last
io.out_valid := valid
mac_unit.io.in_a := a
val last_s = RegEnable(prop, valid)
val flip = last_s =/= prop
val shift_offset = Mux(flip, shift, 0.U)
// Which dataflow are we using?
val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W)
val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W)
// Is c1 being computed on, or propagated forward (in the output-stationary dataflow)?
val COMPUTE = 0.U(1.W)
val PROPAGATE = 1.U(1.W)
io.bad_dataflow := false.B
when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
c2 := mac_unit.io.out_d
c1 := d.withWidthOf(cType)
}.otherwise {
io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c1
c1 := mac_unit.io.out_d
c2 := d.withWidthOf(cType)
}
}.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := c1
mac_unit.io.in_b := c2.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c1 := d
}.otherwise {
io.out_c := c2
mac_unit.io.in_b := c1.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c2 := d
}
}.otherwise {
io.bad_dataflow := true.B
//assert(false.B, "unknown dataflow")
io.out_c := DontCare
io.out_b := DontCare
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
}
when (!valid) {
c1 := c1
c2 := c2
mac_unit.io.in_b := DontCare
mac_unit.io.in_c := DontCare
}
}
File Arithmetic.scala:
// A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own:
// implicit MyTypeArithmetic extends Arithmetic[MyType] { ... }
package gemmini
import chisel3._
import chisel3.util._
import hardfloat._
// Bundles that represent the raw bits of custom datatypes
case class Float(expWidth: Int, sigWidth: Int) extends Bundle {
val bits = UInt((expWidth + sigWidth).W)
val bias: Int = (1 << (expWidth-1)) - 1
}
case class DummySInt(w: Int) extends Bundle {
val bits = UInt(w.W)
def dontCare: DummySInt = {
val o = Wire(new DummySInt(w))
o.bits := 0.U
o
}
}
// The Arithmetic typeclass which implements various arithmetic operations on custom datatypes
abstract class Arithmetic[T <: Data] {
implicit def cast(t: T): ArithmeticOps[T]
}
abstract class ArithmeticOps[T <: Data](self: T) {
def *(t: T): T
def mac(m1: T, m2: T): T // Returns (m1 * m2 + self)
def +(t: T): T
def -(t: T): T
def >>(u: UInt): T // This is a rounding shift! Rounds away from 0
def >(t: T): Bool
def identity: T
def withWidthOf(t: T): T
def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates
def relu: T
def zero: T
def minimum: T
// Optional parameters, which only need to be defined if you want to enable various optimizations for transformers
def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None
def mult_with_reciprocal[U <: Data](reciprocal: U) = self
}
object Arithmetic {
implicit object UIntArithmetic extends Arithmetic[UInt] {
override implicit def cast(self: UInt) = new ArithmeticOps(self) {
override def *(t: UInt) = self * t
override def mac(m1: UInt, m2: UInt) = m1 * m2 + self
override def +(t: UInt) = self + t
override def -(t: UInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = point_five & (zeros | ones_digit)
(self >> u).asUInt + r
}
override def >(t: UInt): Bool = self > t
override def withWidthOf(t: UInt) = self.asTypeOf(t)
override def clippedToWidthOf(t: UInt) = {
val sat = ((1 << (t.getWidth-1))-1).U
Mux(self > sat, sat, self)(t.getWidth-1, 0)
}
override def relu: UInt = self
override def zero: UInt = 0.U
override def identity: UInt = 1.U
override def minimum: UInt = 0.U
}
}
implicit object SIntArithmetic extends Arithmetic[SInt] {
override implicit def cast(self: SInt) = new ArithmeticOps(self) {
override def *(t: SInt) = self * t
override def mac(m1: SInt, m2: SInt) = m1 * m2 + self
override def +(t: SInt) = self + t
override def -(t: SInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = (point_five & (zeros | ones_digit)).asBool
(self >> u).asSInt + Mux(r, 1.S, 0.S)
}
override def >(t: SInt): Bool = self > t
override def withWidthOf(t: SInt) = {
if (self.getWidth >= t.getWidth)
self(t.getWidth-1, 0).asSInt
else {
val sign_bits = t.getWidth - self.getWidth
val sign = self(self.getWidth-1)
Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t)
}
}
override def clippedToWidthOf(t: SInt): SInt = {
val maxsat = ((1 << (t.getWidth-1))-1).S
val minsat = (-(1 << (t.getWidth-1))).S
MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt
}
override def relu: SInt = Mux(self >= 0.S, self, 0.S)
override def zero: SInt = 0.S
override def identity: SInt = 1.S
override def minimum: SInt = (-(1 << (self.getWidth-1))).S
override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(denom_t.cloneType))
val output = Wire(Decoupled(self.cloneType))
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def sin_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def uin_to_float(x: UInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := x
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = sin_to_float(self)
val denom_rec = uin_to_float(input.bits)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := self_rec
divider.io.b := denom_rec
divider.io.roundingMode := consts.round_minMag
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := float_to_in(divider.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(self.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
// Instantiate the hardloat sqrt
val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0))
input.ready := sqrter.io.inReady
sqrter.io.inValid := input.valid
sqrter.io.sqrtOp := true.B
sqrter.io.a := self_rec
sqrter.io.b := DontCare
sqrter.io.roundingMode := consts.round_minMag
sqrter.io.detectTininess := consts.tininess_afterRounding
output.valid := sqrter.io.outValid_sqrt
output.bits := float_to_in(sqrter.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match {
case Float(expWidth, sigWidth) =>
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(u.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
val self_rec = in_to_float(self)
val one_rec = in_to_float(1.S)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := one_rec
divider.io.b := self_rec
divider.io.roundingMode := consts.round_near_even
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u)
assert(!output.valid || output.ready)
Some((input, output))
case _ => None
}
override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match {
case recip @ Float(expWidth, sigWidth) =>
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits)
// Instantiate the hardloat divider
val muladder = Module(new MulRecFN(expWidth, sigWidth))
muladder.io.roundingMode := consts.round_near_even
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := reciprocal_rec
float_to_in(muladder.io.out)
case _ => self
}
}
}
implicit object FloatArithmetic extends Arithmetic[Float] {
// TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array
override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) {
override def *(t: Float): Float = {
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := t_rec_resized
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def mac(m1: Float, m2: Float): Float = {
// Recode all operands
val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits)
val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize m1 to self's width
val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth))
m1_resizer.io.in := m1_rec
m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m1_resizer.io.detectTininess := consts.tininess_afterRounding
val m1_rec_resized = m1_resizer.io.out
// Resize m2 to self's width
val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth))
m2_resizer.io.in := m2_rec
m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m2_resizer.io.detectTininess := consts.tininess_afterRounding
val m2_rec_resized = m2_resizer.io.out
// Perform multiply-add
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := m1_rec_resized
muladder.io.b := m2_rec_resized
muladder.io.c := self_rec
// Convert result to standard format // TODO remove these intermediate recodings
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def +(t: Float): Float = {
require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Generate 1 as a float
val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := 1.U
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
val one_rec = in_to_rec_fn.io.out
// Resize t
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
// Perform addition
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := t_rec_resized
muladder.io.b := one_rec
muladder.io.c := self_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def -(t: Float): Float = {
val t_sgn = t.bits(t.getWidth-1)
val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t)
self + neg_t
}
override def >>(u: UInt): Float = {
// Recode self
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Get 2^(-u) as a recoded float
val shift_exp = Wire(UInt(self.expWidth.W))
shift_exp := self.bias.U - u
val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W))
val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn)
assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported")
// Multiply self and 2^(-u)
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := shift_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def >(t: Float): Bool = {
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize t to self's width
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth))
comparator.io.a := self_rec
comparator.io.b := t_rec_resized
comparator.io.signaling := false.B
comparator.io.gt
}
override def withWidthOf(t: Float): Float = {
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def clippedToWidthOf(t: Float): Float = {
// TODO check for overflow. Right now, we just assume that overflow doesn't happen
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def relu: Float = {
val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits)
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits)
result
}
override def zero: Float = 0.U.asTypeOf(self)
override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
}
}
implicit object DummySIntArithmetic extends Arithmetic[DummySInt] {
override implicit def cast(self: DummySInt) = new ArithmeticOps(self) {
override def *(t: DummySInt) = self.dontCare
override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare
override def +(t: DummySInt) = self.dontCare
override def -(t: DummySInt) = self.dontCare
override def >>(t: UInt) = self.dontCare
override def >(t: DummySInt): Bool = false.B
override def identity = self.dontCare
override def withWidthOf(t: DummySInt) = self.dontCare
override def clippedToWidthOf(t: DummySInt) = self.dontCare
override def relu = self.dontCare
override def zero = self.dontCare
override def minimum: DummySInt = self.dontCare
}
}
}
| module PE_496( // @[PE.scala:31:7]
input clock, // @[PE.scala:31:7]
input reset, // @[PE.scala:31:7]
input [7:0] io_in_a, // @[PE.scala:35:14]
input [19:0] io_in_b, // @[PE.scala:35:14]
input [19:0] io_in_d, // @[PE.scala:35:14]
output [7:0] io_out_a, // @[PE.scala:35:14]
output [19:0] io_out_b, // @[PE.scala:35:14]
output [19:0] io_out_c, // @[PE.scala:35:14]
input io_in_control_dataflow, // @[PE.scala:35:14]
input io_in_control_propagate, // @[PE.scala:35:14]
input [4:0] io_in_control_shift, // @[PE.scala:35:14]
output io_out_control_dataflow, // @[PE.scala:35:14]
output io_out_control_propagate, // @[PE.scala:35:14]
output [4:0] io_out_control_shift, // @[PE.scala:35:14]
input [2:0] io_in_id, // @[PE.scala:35:14]
output [2:0] io_out_id, // @[PE.scala:35:14]
input io_in_last, // @[PE.scala:35:14]
output io_out_last, // @[PE.scala:35:14]
input io_in_valid, // @[PE.scala:35:14]
output io_out_valid // @[PE.scala:35:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7]
wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7]
wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7]
wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7]
wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7]
wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7]
wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7]
wire io_in_last_0 = io_in_last; // @[PE.scala:31:7]
wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7]
wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7]
wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33]
wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60]
wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33]
wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60]
wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7]
wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37]
wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37]
wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35]
wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7]
wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7]
wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7]
wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7]
wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7]
wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7]
wire [19:0] io_out_b_0; // @[PE.scala:31:7]
wire [19:0] io_out_c_0; // @[PE.scala:31:7]
reg [7:0] c1; // @[PE.scala:70:15]
wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15]
wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38]
reg [7:0] c2; // @[PE.scala:71:15]
wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15]
wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38]
reg last_s; // @[PE.scala:89:25]
wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21]
wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25]
wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25]
wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32]
wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32]
wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25]
wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53]
wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15]
wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}]
wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25]
wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27]
wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27]
wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}]
wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25]
wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15]
wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30]
wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15]
assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33]
wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}]
wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28]
wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28]
wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37]
wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37]
wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7]
wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7]
wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}]
wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53]
wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15]
wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}]
wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}]
wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15]
wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30]
wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15]
assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33]
wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}]
wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28]
wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28]
wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37]
wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37]
wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}]
wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38]
assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38]
wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38]
assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16]
wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38]
assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38]
wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38]
wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35]
wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35]
always @(posedge clock) begin // @[PE.scala:31:7]
if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8]
c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15]
if (~(~io_in_valid_0 | io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8]
c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15]
if (io_in_valid_0) // @[PE.scala:31:7]
last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25]
always @(posedge)
MacUnit_240 mac_unit ( // @[PE.scala:64:24]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0), // @[PE.scala:31:7]
.io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}]
.io_in_c (io_in_b_0), // @[PE.scala:31:7]
.io_out_d (io_out_b_0)
); // @[PE.scala:64:24]
assign io_out_a = io_out_a_0; // @[PE.scala:31:7]
assign io_out_b = io_out_b_0; // @[PE.scala:31:7]
assign io_out_c = io_out_c_0; // @[PE.scala:31:7]
assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7]
assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7]
assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7]
assign io_out_id = io_out_id_0; // @[PE.scala:31:7]
assign io_out_last = io_out_last_0; // @[PE.scala:31:7]
assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor_9( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [7:0] io_in_d_bits_source // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71]
wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [7:0] source; // @[Monitor.scala:390:22]
reg [28:0] address; // @[Monitor.scala:391:22]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [7:0] source_1; // @[Monitor.scala:541:22]
reg [128:0] inflight; // @[Monitor.scala:614:27]
reg [515:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [515:0] inflight_sizes; // @[Monitor.scala:618:33]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _GEN_0 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35]
wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46]
wire _GEN_1 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [128:0] inflight_1; // @[Monitor.scala:726:35]
reg [515:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to the following Chisel files.
File PE.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle {
val dataflow = UInt(1.W) // TODO make this an Enum
val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)?
val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats
}
class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module {
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(inputType)
val in_c = Input(cType)
val out_d = Output(dType)
})
io.out_d := io.in_c.mac(io.in_a, io.in_b)
}
// TODO update documentation
/**
* A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh.
* @param width Data width of operands
*/
class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int)
(implicit ev: Arithmetic[T]) extends Module { // Debugging variables
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(outputType)
val in_d = Input(outputType)
val out_a = Output(inputType)
val out_b = Output(outputType)
val out_c = Output(outputType)
val in_control = Input(new PEControl(accType))
val out_control = Output(new PEControl(accType))
val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W))
val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W))
val in_last = Input(Bool())
val out_last = Output(Bool())
val in_valid = Input(Bool())
val out_valid = Output(Bool())
val bad_dataflow = Output(Bool())
})
val cType = if (df == Dataflow.WS) inputType else accType
// When creating PEs that support multiple dataflows, the
// elaboration/synthesis tools often fail to consolidate and de-duplicate
// MAC units. To force mac circuitry to be re-used, we create a "mac_unit"
// module here which just performs a single MAC operation
val mac_unit = Module(new MacUnit(inputType,
if (df == Dataflow.WS) outputType else accType, outputType))
val a = io.in_a
val b = io.in_b
val d = io.in_d
val c1 = Reg(cType)
val c2 = Reg(cType)
val dataflow = io.in_control.dataflow
val prop = io.in_control.propagate
val shift = io.in_control.shift
val id = io.in_id
val last = io.in_last
val valid = io.in_valid
io.out_a := a
io.out_control.dataflow := dataflow
io.out_control.propagate := prop
io.out_control.shift := shift
io.out_id := id
io.out_last := last
io.out_valid := valid
mac_unit.io.in_a := a
val last_s = RegEnable(prop, valid)
val flip = last_s =/= prop
val shift_offset = Mux(flip, shift, 0.U)
// Which dataflow are we using?
val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W)
val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W)
// Is c1 being computed on, or propagated forward (in the output-stationary dataflow)?
val COMPUTE = 0.U(1.W)
val PROPAGATE = 1.U(1.W)
io.bad_dataflow := false.B
when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
c2 := mac_unit.io.out_d
c1 := d.withWidthOf(cType)
}.otherwise {
io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c1
c1 := mac_unit.io.out_d
c2 := d.withWidthOf(cType)
}
}.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := c1
mac_unit.io.in_b := c2.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c1 := d
}.otherwise {
io.out_c := c2
mac_unit.io.in_b := c1.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c2 := d
}
}.otherwise {
io.bad_dataflow := true.B
//assert(false.B, "unknown dataflow")
io.out_c := DontCare
io.out_b := DontCare
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
}
when (!valid) {
c1 := c1
c2 := c2
mac_unit.io.in_b := DontCare
mac_unit.io.in_c := DontCare
}
}
File Arithmetic.scala:
// A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own:
// implicit MyTypeArithmetic extends Arithmetic[MyType] { ... }
package gemmini
import chisel3._
import chisel3.util._
import hardfloat._
// Bundles that represent the raw bits of custom datatypes
case class Float(expWidth: Int, sigWidth: Int) extends Bundle {
val bits = UInt((expWidth + sigWidth).W)
val bias: Int = (1 << (expWidth-1)) - 1
}
case class DummySInt(w: Int) extends Bundle {
val bits = UInt(w.W)
def dontCare: DummySInt = {
val o = Wire(new DummySInt(w))
o.bits := 0.U
o
}
}
// The Arithmetic typeclass which implements various arithmetic operations on custom datatypes
abstract class Arithmetic[T <: Data] {
implicit def cast(t: T): ArithmeticOps[T]
}
abstract class ArithmeticOps[T <: Data](self: T) {
def *(t: T): T
def mac(m1: T, m2: T): T // Returns (m1 * m2 + self)
def +(t: T): T
def -(t: T): T
def >>(u: UInt): T // This is a rounding shift! Rounds away from 0
def >(t: T): Bool
def identity: T
def withWidthOf(t: T): T
def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates
def relu: T
def zero: T
def minimum: T
// Optional parameters, which only need to be defined if you want to enable various optimizations for transformers
def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None
def mult_with_reciprocal[U <: Data](reciprocal: U) = self
}
object Arithmetic {
implicit object UIntArithmetic extends Arithmetic[UInt] {
override implicit def cast(self: UInt) = new ArithmeticOps(self) {
override def *(t: UInt) = self * t
override def mac(m1: UInt, m2: UInt) = m1 * m2 + self
override def +(t: UInt) = self + t
override def -(t: UInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = point_five & (zeros | ones_digit)
(self >> u).asUInt + r
}
override def >(t: UInt): Bool = self > t
override def withWidthOf(t: UInt) = self.asTypeOf(t)
override def clippedToWidthOf(t: UInt) = {
val sat = ((1 << (t.getWidth-1))-1).U
Mux(self > sat, sat, self)(t.getWidth-1, 0)
}
override def relu: UInt = self
override def zero: UInt = 0.U
override def identity: UInt = 1.U
override def minimum: UInt = 0.U
}
}
implicit object SIntArithmetic extends Arithmetic[SInt] {
override implicit def cast(self: SInt) = new ArithmeticOps(self) {
override def *(t: SInt) = self * t
override def mac(m1: SInt, m2: SInt) = m1 * m2 + self
override def +(t: SInt) = self + t
override def -(t: SInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = (point_five & (zeros | ones_digit)).asBool
(self >> u).asSInt + Mux(r, 1.S, 0.S)
}
override def >(t: SInt): Bool = self > t
override def withWidthOf(t: SInt) = {
if (self.getWidth >= t.getWidth)
self(t.getWidth-1, 0).asSInt
else {
val sign_bits = t.getWidth - self.getWidth
val sign = self(self.getWidth-1)
Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t)
}
}
override def clippedToWidthOf(t: SInt): SInt = {
val maxsat = ((1 << (t.getWidth-1))-1).S
val minsat = (-(1 << (t.getWidth-1))).S
MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt
}
override def relu: SInt = Mux(self >= 0.S, self, 0.S)
override def zero: SInt = 0.S
override def identity: SInt = 1.S
override def minimum: SInt = (-(1 << (self.getWidth-1))).S
override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(denom_t.cloneType))
val output = Wire(Decoupled(self.cloneType))
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def sin_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def uin_to_float(x: UInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := x
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = sin_to_float(self)
val denom_rec = uin_to_float(input.bits)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := self_rec
divider.io.b := denom_rec
divider.io.roundingMode := consts.round_minMag
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := float_to_in(divider.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(self.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
// Instantiate the hardloat sqrt
val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0))
input.ready := sqrter.io.inReady
sqrter.io.inValid := input.valid
sqrter.io.sqrtOp := true.B
sqrter.io.a := self_rec
sqrter.io.b := DontCare
sqrter.io.roundingMode := consts.round_minMag
sqrter.io.detectTininess := consts.tininess_afterRounding
output.valid := sqrter.io.outValid_sqrt
output.bits := float_to_in(sqrter.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match {
case Float(expWidth, sigWidth) =>
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(u.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
val self_rec = in_to_float(self)
val one_rec = in_to_float(1.S)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := one_rec
divider.io.b := self_rec
divider.io.roundingMode := consts.round_near_even
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u)
assert(!output.valid || output.ready)
Some((input, output))
case _ => None
}
override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match {
case recip @ Float(expWidth, sigWidth) =>
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits)
// Instantiate the hardloat divider
val muladder = Module(new MulRecFN(expWidth, sigWidth))
muladder.io.roundingMode := consts.round_near_even
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := reciprocal_rec
float_to_in(muladder.io.out)
case _ => self
}
}
}
implicit object FloatArithmetic extends Arithmetic[Float] {
// TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array
override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) {
override def *(t: Float): Float = {
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := t_rec_resized
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def mac(m1: Float, m2: Float): Float = {
// Recode all operands
val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits)
val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize m1 to self's width
val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth))
m1_resizer.io.in := m1_rec
m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m1_resizer.io.detectTininess := consts.tininess_afterRounding
val m1_rec_resized = m1_resizer.io.out
// Resize m2 to self's width
val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth))
m2_resizer.io.in := m2_rec
m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m2_resizer.io.detectTininess := consts.tininess_afterRounding
val m2_rec_resized = m2_resizer.io.out
// Perform multiply-add
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := m1_rec_resized
muladder.io.b := m2_rec_resized
muladder.io.c := self_rec
// Convert result to standard format // TODO remove these intermediate recodings
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def +(t: Float): Float = {
require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Generate 1 as a float
val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := 1.U
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
val one_rec = in_to_rec_fn.io.out
// Resize t
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
// Perform addition
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := t_rec_resized
muladder.io.b := one_rec
muladder.io.c := self_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def -(t: Float): Float = {
val t_sgn = t.bits(t.getWidth-1)
val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t)
self + neg_t
}
override def >>(u: UInt): Float = {
// Recode self
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Get 2^(-u) as a recoded float
val shift_exp = Wire(UInt(self.expWidth.W))
shift_exp := self.bias.U - u
val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W))
val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn)
assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported")
// Multiply self and 2^(-u)
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := shift_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def >(t: Float): Bool = {
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize t to self's width
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth))
comparator.io.a := self_rec
comparator.io.b := t_rec_resized
comparator.io.signaling := false.B
comparator.io.gt
}
override def withWidthOf(t: Float): Float = {
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def clippedToWidthOf(t: Float): Float = {
// TODO check for overflow. Right now, we just assume that overflow doesn't happen
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def relu: Float = {
val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits)
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits)
result
}
override def zero: Float = 0.U.asTypeOf(self)
override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
}
}
implicit object DummySIntArithmetic extends Arithmetic[DummySInt] {
override implicit def cast(self: DummySInt) = new ArithmeticOps(self) {
override def *(t: DummySInt) = self.dontCare
override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare
override def +(t: DummySInt) = self.dontCare
override def -(t: DummySInt) = self.dontCare
override def >>(t: UInt) = self.dontCare
override def >(t: DummySInt): Bool = false.B
override def identity = self.dontCare
override def withWidthOf(t: DummySInt) = self.dontCare
override def clippedToWidthOf(t: DummySInt) = self.dontCare
override def relu = self.dontCare
override def zero = self.dontCare
override def minimum: DummySInt = self.dontCare
}
}
}
| module PE_498( // @[PE.scala:31:7]
input clock, // @[PE.scala:31:7]
input reset, // @[PE.scala:31:7]
input [7:0] io_in_a, // @[PE.scala:35:14]
input [19:0] io_in_b, // @[PE.scala:35:14]
input [19:0] io_in_d, // @[PE.scala:35:14]
output [7:0] io_out_a, // @[PE.scala:35:14]
output [19:0] io_out_b, // @[PE.scala:35:14]
output [19:0] io_out_c, // @[PE.scala:35:14]
input io_in_control_dataflow, // @[PE.scala:35:14]
input io_in_control_propagate, // @[PE.scala:35:14]
input [4:0] io_in_control_shift, // @[PE.scala:35:14]
output io_out_control_dataflow, // @[PE.scala:35:14]
output io_out_control_propagate, // @[PE.scala:35:14]
output [4:0] io_out_control_shift, // @[PE.scala:35:14]
input [2:0] io_in_id, // @[PE.scala:35:14]
output [2:0] io_out_id, // @[PE.scala:35:14]
input io_in_last, // @[PE.scala:35:14]
output io_out_last, // @[PE.scala:35:14]
input io_in_valid, // @[PE.scala:35:14]
output io_out_valid // @[PE.scala:35:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7]
wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7]
wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7]
wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7]
wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7]
wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7]
wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7]
wire io_in_last_0 = io_in_last; // @[PE.scala:31:7]
wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7]
wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7]
wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33]
wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60]
wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33]
wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60]
wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7]
wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37]
wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37]
wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35]
wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7]
wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7]
wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7]
wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7]
wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7]
wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7]
wire [19:0] io_out_b_0; // @[PE.scala:31:7]
wire [19:0] io_out_c_0; // @[PE.scala:31:7]
reg [7:0] c1; // @[PE.scala:70:15]
wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15]
wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38]
reg [7:0] c2; // @[PE.scala:71:15]
wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15]
wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38]
reg last_s; // @[PE.scala:89:25]
wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21]
wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25]
wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25]
wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32]
wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32]
wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25]
wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53]
wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15]
wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}]
wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25]
wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27]
wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27]
wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}]
wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25]
wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15]
wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30]
wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15]
assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33]
wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}]
wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28]
wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28]
wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37]
wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37]
wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7]
wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7]
wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}]
wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53]
wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15]
wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}]
wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}]
wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15]
wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30]
wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15]
assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33]
wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}]
wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28]
wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28]
wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37]
wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37]
wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}]
wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38]
assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38]
wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38]
assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16]
wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38]
assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38]
wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38]
wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35]
wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35]
always @(posedge clock) begin // @[PE.scala:31:7]
if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8]
c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15]
if (~(~io_in_valid_0 | io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8]
c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15]
if (io_in_valid_0) // @[PE.scala:31:7]
last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25]
always @(posedge)
MacUnit_242 mac_unit ( // @[PE.scala:64:24]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0), // @[PE.scala:31:7]
.io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}]
.io_in_c (io_in_b_0), // @[PE.scala:31:7]
.io_out_d (io_out_b_0)
); // @[PE.scala:64:24]
assign io_out_a = io_out_a_0; // @[PE.scala:31:7]
assign io_out_b = io_out_b_0; // @[PE.scala:31:7]
assign io_out_c = io_out_c_0; // @[PE.scala:31:7]
assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7]
assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7]
assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7]
assign io_out_id = io_out_id_0; // @[PE.scala:31:7]
assign io_out_last = io_out_last_0; // @[PE.scala:31:7]
assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Bundles.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import freechips.rocketchip.util._
import scala.collection.immutable.ListMap
import chisel3.util.Decoupled
import chisel3.util.DecoupledIO
import chisel3.reflect.DataMirror
abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle
// common combos in lazy policy:
// Put + Acquire
// Release + AccessAck
object TLMessages
{
// A B C D E
def PutFullData = 0.U // . . => AccessAck
def PutPartialData = 1.U // . . => AccessAck
def ArithmeticData = 2.U // . . => AccessAckData
def LogicalData = 3.U // . . => AccessAckData
def Get = 4.U // . . => AccessAckData
def Hint = 5.U // . . => HintAck
def AcquireBlock = 6.U // . => Grant[Data]
def AcquirePerm = 7.U // . => Grant[Data]
def Probe = 6.U // . => ProbeAck[Data]
def AccessAck = 0.U // . .
def AccessAckData = 1.U // . .
def HintAck = 2.U // . .
def ProbeAck = 4.U // .
def ProbeAckData = 5.U // .
def Release = 6.U // . => ReleaseAck
def ReleaseData = 7.U // . => ReleaseAck
def Grant = 4.U // . => GrantAck
def GrantData = 5.U // . => GrantAck
def ReleaseAck = 6.U // .
def GrantAck = 0.U // .
def isA(x: UInt) = x <= AcquirePerm
def isB(x: UInt) = x <= Probe
def isC(x: UInt) = x <= ReleaseData
def isD(x: UInt) = x <= ReleaseAck
def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant)
def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck)
def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("AcquireBlock",TLPermissions.PermMsgGrow),
("AcquirePerm",TLPermissions.PermMsgGrow))
def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("Probe",TLPermissions.PermMsgCap))
def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("ProbeAck",TLPermissions.PermMsgReport),
("ProbeAckData",TLPermissions.PermMsgReport),
("Release",TLPermissions.PermMsgReport),
("ReleaseData",TLPermissions.PermMsgReport))
def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("Grant",TLPermissions.PermMsgCap),
("GrantData",TLPermissions.PermMsgCap),
("ReleaseAck",TLPermissions.PermMsgReserved))
}
/**
* The three primary TileLink permissions are:
* (T)runk: the agent is (or is on inwards path to) the global point of serialization.
* (B)ranch: the agent is on an outwards path to
* (N)one:
* These permissions are permuted by transfer operations in various ways.
* Operations can cap permissions, request for them to be grown or shrunk,
* or for a report on their current status.
*/
object TLPermissions
{
val aWidth = 2
val bdWidth = 2
val cWidth = 3
// Cap types (Grant = new permissions, Probe = permisions <= target)
def toT = 0.U(bdWidth.W)
def toB = 1.U(bdWidth.W)
def toN = 2.U(bdWidth.W)
def isCap(x: UInt) = x <= toN
// Grow types (Acquire = permissions >= target)
def NtoB = 0.U(aWidth.W)
def NtoT = 1.U(aWidth.W)
def BtoT = 2.U(aWidth.W)
def isGrow(x: UInt) = x <= BtoT
// Shrink types (ProbeAck, Release)
def TtoB = 0.U(cWidth.W)
def TtoN = 1.U(cWidth.W)
def BtoN = 2.U(cWidth.W)
def isShrink(x: UInt) = x <= BtoN
// Report types (ProbeAck, Release)
def TtoT = 3.U(cWidth.W)
def BtoB = 4.U(cWidth.W)
def NtoN = 5.U(cWidth.W)
def isReport(x: UInt) = x <= NtoN
def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT")
def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN")
def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN")
def PermMsgReserved:Seq[String] = Seq("Reserved")
}
object TLAtomics
{
val width = 3
// Arithmetic types
def MIN = 0.U(width.W)
def MAX = 1.U(width.W)
def MINU = 2.U(width.W)
def MAXU = 3.U(width.W)
def ADD = 4.U(width.W)
def isArithmetic(x: UInt) = x <= ADD
// Logical types
def XOR = 0.U(width.W)
def OR = 1.U(width.W)
def AND = 2.U(width.W)
def SWAP = 3.U(width.W)
def isLogical(x: UInt) = x <= SWAP
def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD")
def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP")
}
object TLHints
{
val width = 1
def PREFETCH_READ = 0.U(width.W)
def PREFETCH_WRITE = 1.U(width.W)
def isHints(x: UInt) = x <= PREFETCH_WRITE
def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite")
}
sealed trait TLChannel extends TLBundleBase {
val channelName: String
}
sealed trait TLDataChannel extends TLChannel
sealed trait TLAddrChannel extends TLDataChannel
final class TLBundleA(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleA_${params.shortName}"
val channelName = "'A' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleB(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleB_${params.shortName}"
val channelName = "'B' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val address = UInt(params.addressBits.W) // from
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleC(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleC_${params.shortName}"
val channelName = "'C' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.cWidth.W) // shrink or report perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleD(params: TLBundleParameters)
extends TLBundleBase(params) with TLDataChannel
{
override def typeName = s"TLBundleD_${params.shortName}"
val channelName = "'D' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val sink = UInt(params.sinkBits.W) // from
val denied = Bool() // implies corrupt iff *Data
val user = BundleMap(params.responseFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleE(params: TLBundleParameters)
extends TLBundleBase(params) with TLChannel
{
override def typeName = s"TLBundleE_${params.shortName}"
val channelName = "'E' channel"
val sink = UInt(params.sinkBits.W) // to
}
class TLBundle(val params: TLBundleParameters) extends Record
{
// Emulate a Bundle with elements abcde or ad depending on params.hasBCE
private val optA = Some (Decoupled(new TLBundleA(params)))
private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params))))
private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params)))
private val optD = Some (Flipped(Decoupled(new TLBundleD(params))))
private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params)))
def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params)))))
def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params)))))
def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params)))))
def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params)))))
def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params)))))
val elements =
if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a)
else ListMap("d" -> d, "a" -> a)
def tieoff(): Unit = {
DataMirror.specifiedDirectionOf(a.ready) match {
case SpecifiedDirection.Input =>
a.ready := false.B
c.ready := false.B
e.ready := false.B
b.valid := false.B
d.valid := false.B
case SpecifiedDirection.Output =>
a.valid := false.B
c.valid := false.B
e.valid := false.B
b.ready := false.B
d.ready := false.B
case _ =>
}
}
}
object TLBundle
{
def apply(params: TLBundleParameters) = new TLBundle(params)
}
class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle
class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params)
{
val a = new AsyncBundle(new TLBundleA(params.base), params.async)
val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async))
val c = new AsyncBundle(new TLBundleC(params.base), params.async)
val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async))
val e = new AsyncBundle(new TLBundleE(params.base), params.async)
}
class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = RationalIO(new TLBundleA(params))
val b = Flipped(RationalIO(new TLBundleB(params)))
val c = RationalIO(new TLBundleC(params))
val d = Flipped(RationalIO(new TLBundleD(params)))
val e = RationalIO(new TLBundleE(params))
}
class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = CreditedIO(new TLBundleA(params))
val b = Flipped(CreditedIO(new TLBundleB(params)))
val c = CreditedIO(new TLBundleC(params))
val d = Flipped(CreditedIO(new TLBundleD(params)))
val e = CreditedIO(new TLBundleE(params))
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor_55( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [27:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [7:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [27:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [7:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10]
wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire a_first_count = 1'h0; // @[Edges.scala:234:25]
wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count = 1'h0; // @[Edges.scala:234:25]
wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25]
wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27]
wire c_first_count = 1'h0; // @[Edges.scala:234:25]
wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21]
wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67]
wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last = 1'h1; // @[Edges.scala:232:33]
wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33]
wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28]
wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7]
wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_first_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_first_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_first_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_first_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_set_wo_ready_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_set_wo_ready_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_opcodes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_opcodes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_sizes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_sizes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_opcodes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_opcodes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_sizes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_sizes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_probe_ack_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_probe_ack_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_probe_ack_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_probe_ack_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _same_cycle_resp_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _same_cycle_resp_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _same_cycle_resp_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _same_cycle_resp_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _same_cycle_resp_WIRE_4_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _same_cycle_resp_WIRE_5_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_first_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_first_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_first_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_first_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_set_wo_ready_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_set_wo_ready_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_opcodes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_opcodes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_sizes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_sizes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_opcodes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_opcodes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_sizes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_sizes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_probe_ack_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_probe_ack_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_probe_ack_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_probe_ack_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _same_cycle_resp_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _same_cycle_resp_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _same_cycle_resp_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _same_cycle_resp_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _same_cycle_resp_WIRE_4_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _same_cycle_resp_WIRE_5_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46]
wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [2049:0] _c_sizes_set_T_1 = 2050'h0; // @[Monitor.scala:768:52]
wire [10:0] _c_opcodes_set_T = 11'h0; // @[Monitor.scala:767:79]
wire [10:0] _c_sizes_set_T = 11'h0; // @[Monitor.scala:768:77]
wire [2050:0] _c_opcodes_set_T_1 = 2051'h0; // @[Monitor.scala:767:54]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [255:0] _c_set_wo_ready_T = 256'h1; // @[OneHot.scala:58:35]
wire [255:0] _c_set_T = 256'h1; // @[OneHot.scala:58:35]
wire [639:0] c_opcodes_set = 640'h0; // @[Monitor.scala:740:34]
wire [639:0] c_sizes_set = 640'h0; // @[Monitor.scala:741:34]
wire [159:0] c_set = 160'h0; // @[Monitor.scala:738:34]
wire [159:0] c_set_wo_ready = 160'h0; // @[Monitor.scala:739:34]
wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76]
wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [7:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_4 = source_ok_uncommonBits < 8'hA0; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31]
wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [27:0] _is_aligned_T = {25'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 28'h0; // @[Edges.scala:21:{16,24}]
wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [7:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire [7:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire [7:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}]
wire [7:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}]
wire [7:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}]
wire [7:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}]
wire [7:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}]
wire [7:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}]
wire [7:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}]
wire [7:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_10 = source_ok_uncommonBits_1 < 8'hA0; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31]
wire _T_672 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_672; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_672; // @[Decoupled.scala:51:35]
wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
reg a_first_counter; // @[Edges.scala:229:27]
wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28]
wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25]
wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [1:0] size; // @[Monitor.scala:389:22]
reg [7:0] source; // @[Monitor.scala:390:22]
reg [27:0] address; // @[Monitor.scala:391:22]
wire _T_745 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_745; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_745; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_745; // @[Decoupled.scala:51:35]
wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35]
wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
reg d_first_counter; // @[Edges.scala:229:27]
wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28]
wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] size_1; // @[Monitor.scala:540:22]
reg [7:0] source_1; // @[Monitor.scala:541:22]
reg [159:0] inflight; // @[Monitor.scala:614:27]
reg [639:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [639:0] inflight_sizes; // @[Monitor.scala:618:33]
wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
reg a_first_counter_1; // @[Edges.scala:229:27]
wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28]
wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25]
wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
reg d_first_counter_1; // @[Edges.scala:229:27]
wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28]
wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire [159:0] a_set; // @[Monitor.scala:626:34]
wire [159:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [639:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [639:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [10:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [10:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [10:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [10:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [10:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [10:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [10:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [10:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [10:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [639:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [639:0] _a_opcode_lookup_T_6 = {636'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [639:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[639:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [639:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [639:0] _a_size_lookup_T_6 = {636'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [639:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[639:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [255:0] _GEN_2 = 256'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [255:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [255:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[159:0] : 160'h0; // @[OneHot.scala:58:35]
wire _T_598 = _T_672 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_598 ? _a_set_T[159:0] : 160'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [10:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [10:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [10:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [2050:0] _a_opcodes_set_T_1 = {2047'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[639:0] : 640'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [2049:0] _a_sizes_set_T_1 = {2047'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[639:0] : 640'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [159:0] d_clr; // @[Monitor.scala:664:34]
wire [159:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [639:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [639:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [255:0] _GEN_5 = 256'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[159:0] : 160'h0; // @[OneHot.scala:58:35]
wire _T_613 = _T_745 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_613 ? _d_clr_T[159:0] : 160'h0; // @[OneHot.scala:58:35]
wire [2062:0] _d_opcodes_clr_T_5 = 2063'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[639:0] : 640'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [2062:0] _d_sizes_clr_T_5 = 2063'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[639:0] : 640'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [159:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [159:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [159:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [639:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [639:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [639:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [639:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [639:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [639:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [159:0] inflight_1; // @[Monitor.scala:726:35]
wire [159:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [639:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [639:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [639:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [639:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
reg d_first_counter_2; // @[Edges.scala:229:27]
wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28]
wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [639:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [639:0] _c_opcode_lookup_T_6 = {636'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [639:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[639:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [639:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [639:0] _c_size_lookup_T_6 = {636'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [639:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[639:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [159:0] d_clr_1; // @[Monitor.scala:774:34]
wire [159:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [639:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [639:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_716 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_716 & d_release_ack_1 ? _d_clr_wo_ready_T_1[159:0] : 160'h0; // @[OneHot.scala:58:35]
wire _T_698 = _T_745 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_698 ? _d_clr_T_1[159:0] : 160'h0; // @[OneHot.scala:58:35]
wire [2062:0] _d_opcodes_clr_T_11 = 2063'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_698 ? _d_opcodes_clr_T_11[639:0] : 640'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [2062:0] _d_sizes_clr_T_11 = 2063'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_698 ? _d_sizes_clr_T_11[639:0] : 640'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 8'h0; // @[Monitor.scala:36:7, :795:113]
wire [159:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [159:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [639:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [639:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [639:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [639:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to the following Chisel files.
File FPU.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tile
import chisel3._
import chisel3.util._
import chisel3.{DontCare, WireInit, withClock, withReset}
import chisel3.experimental.SourceInfo
import chisel3.experimental.dataview._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.rocket._
import freechips.rocketchip.rocket.Instructions._
import freechips.rocketchip.util._
import freechips.rocketchip.util.property
case class FPUParams(
minFLen: Int = 32,
fLen: Int = 64,
divSqrt: Boolean = true,
sfmaLatency: Int = 3,
dfmaLatency: Int = 4,
fpmuLatency: Int = 2,
ifpuLatency: Int = 2
)
object FPConstants
{
val RM_SZ = 3
val FLAGS_SZ = 5
}
trait HasFPUCtrlSigs {
val ldst = Bool()
val wen = Bool()
val ren1 = Bool()
val ren2 = Bool()
val ren3 = Bool()
val swap12 = Bool()
val swap23 = Bool()
val typeTagIn = UInt(2.W)
val typeTagOut = UInt(2.W)
val fromint = Bool()
val toint = Bool()
val fastpipe = Bool()
val fma = Bool()
val div = Bool()
val sqrt = Bool()
val wflags = Bool()
val vec = Bool()
}
class FPUCtrlSigs extends Bundle with HasFPUCtrlSigs
class FPUDecoder(implicit p: Parameters) extends FPUModule()(p) {
val io = IO(new Bundle {
val inst = Input(Bits(32.W))
val sigs = Output(new FPUCtrlSigs())
})
private val X2 = BitPat.dontCare(2)
val default = List(X,X,X,X,X,X,X,X2,X2,X,X,X,X,X,X,X,N)
val h: Array[(BitPat, List[BitPat])] =
Array(FLH -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),
FSH -> List(Y,N,N,Y,N,Y,X, I, H,N,Y,N,N,N,N,N,N),
FMV_H_X -> List(N,Y,N,N,N,X,X, H, I,Y,N,N,N,N,N,N,N),
FCVT_H_W -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),
FCVT_H_WU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),
FCVT_H_L -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),
FCVT_H_LU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),
FMV_X_H -> List(N,N,Y,N,N,N,X, I, H,N,Y,N,N,N,N,N,N),
FCLASS_H -> List(N,N,Y,N,N,N,X, H, H,N,Y,N,N,N,N,N,N),
FCVT_W_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),
FCVT_WU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),
FCVT_L_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),
FCVT_LU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),
FCVT_S_H -> List(N,Y,Y,N,N,N,X, H, S,N,N,Y,N,N,N,Y,N),
FCVT_H_S -> List(N,Y,Y,N,N,N,X, S, H,N,N,Y,N,N,N,Y,N),
FEQ_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),
FLT_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),
FLE_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),
FSGNJ_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),
FSGNJN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),
FSGNJX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),
FMIN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N),
FMAX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N),
FADD_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N),
FSUB_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N),
FMUL_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,Y,N,N,Y,N),
FMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),
FMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),
FNMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),
FNMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),
FDIV_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,N,Y,N,Y,N),
FSQRT_H -> List(N,Y,Y,N,N,N,X, H, H,N,N,N,N,N,Y,Y,N))
val f: Array[(BitPat, List[BitPat])] =
Array(FLW -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),
FSW -> List(Y,N,N,Y,N,Y,X, I, S,N,Y,N,N,N,N,N,N),
FMV_W_X -> List(N,Y,N,N,N,X,X, S, I,Y,N,N,N,N,N,N,N),
FCVT_S_W -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),
FCVT_S_WU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),
FCVT_S_L -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),
FCVT_S_LU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),
FMV_X_W -> List(N,N,Y,N,N,N,X, I, S,N,Y,N,N,N,N,N,N),
FCLASS_S -> List(N,N,Y,N,N,N,X, S, S,N,Y,N,N,N,N,N,N),
FCVT_W_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),
FCVT_WU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),
FCVT_L_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),
FCVT_LU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),
FEQ_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),
FLT_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),
FLE_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),
FSGNJ_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),
FSGNJN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),
FSGNJX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),
FMIN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N),
FMAX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N),
FADD_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N),
FSUB_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N),
FMUL_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,Y,N,N,Y,N),
FMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),
FMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),
FNMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),
FNMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),
FDIV_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,N,Y,N,Y,N),
FSQRT_S -> List(N,Y,Y,N,N,N,X, S, S,N,N,N,N,N,Y,Y,N))
val d: Array[(BitPat, List[BitPat])] =
Array(FLD -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),
FSD -> List(Y,N,N,Y,N,Y,X, I, D,N,Y,N,N,N,N,N,N),
FMV_D_X -> List(N,Y,N,N,N,X,X, D, I,Y,N,N,N,N,N,N,N),
FCVT_D_W -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),
FCVT_D_WU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),
FCVT_D_L -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),
FCVT_D_LU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),
FMV_X_D -> List(N,N,Y,N,N,N,X, I, D,N,Y,N,N,N,N,N,N),
FCLASS_D -> List(N,N,Y,N,N,N,X, D, D,N,Y,N,N,N,N,N,N),
FCVT_W_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),
FCVT_WU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),
FCVT_L_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),
FCVT_LU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),
FCVT_S_D -> List(N,Y,Y,N,N,N,X, D, S,N,N,Y,N,N,N,Y,N),
FCVT_D_S -> List(N,Y,Y,N,N,N,X, S, D,N,N,Y,N,N,N,Y,N),
FEQ_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),
FLT_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),
FLE_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),
FSGNJ_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),
FSGNJN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),
FSGNJX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),
FMIN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N),
FMAX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N),
FADD_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N),
FSUB_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N),
FMUL_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,Y,N,N,Y,N),
FMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),
FMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),
FNMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),
FNMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),
FDIV_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,N,Y,N,Y,N),
FSQRT_D -> List(N,Y,Y,N,N,N,X, D, D,N,N,N,N,N,Y,Y,N))
val fcvt_hd: Array[(BitPat, List[BitPat])] =
Array(FCVT_H_D -> List(N,Y,Y,N,N,N,X, D, H,N,N,Y,N,N,N,Y,N),
FCVT_D_H -> List(N,Y,Y,N,N,N,X, H, D,N,N,Y,N,N,N,Y,N))
val vfmv_f_s: Array[(BitPat, List[BitPat])] =
Array(VFMV_F_S -> List(N,Y,N,N,N,N,X,X2,X2,N,N,N,N,N,N,N,Y))
val insns = ((minFLen, fLen) match {
case (32, 32) => f
case (16, 32) => h ++ f
case (32, 64) => f ++ d
case (16, 64) => h ++ f ++ d ++ fcvt_hd
case other => throw new Exception(s"minFLen = ${minFLen} & fLen = ${fLen} is an unsupported configuration")
}) ++ (if (usingVector) vfmv_f_s else Array[(BitPat, List[BitPat])]())
val decoder = DecodeLogic(io.inst, default, insns)
val s = io.sigs
val sigs = Seq(s.ldst, s.wen, s.ren1, s.ren2, s.ren3, s.swap12,
s.swap23, s.typeTagIn, s.typeTagOut, s.fromint, s.toint,
s.fastpipe, s.fma, s.div, s.sqrt, s.wflags, s.vec)
sigs zip decoder map {case(s,d) => s := d}
}
class FPUCoreIO(implicit p: Parameters) extends CoreBundle()(p) {
val hartid = Input(UInt(hartIdLen.W))
val time = Input(UInt(xLen.W))
val inst = Input(Bits(32.W))
val fromint_data = Input(Bits(xLen.W))
val fcsr_rm = Input(Bits(FPConstants.RM_SZ.W))
val fcsr_flags = Valid(Bits(FPConstants.FLAGS_SZ.W))
val v_sew = Input(UInt(3.W))
val store_data = Output(Bits(fLen.W))
val toint_data = Output(Bits(xLen.W))
val ll_resp_val = Input(Bool())
val ll_resp_type = Input(Bits(3.W))
val ll_resp_tag = Input(UInt(5.W))
val ll_resp_data = Input(Bits(fLen.W))
val valid = Input(Bool())
val fcsr_rdy = Output(Bool())
val nack_mem = Output(Bool())
val illegal_rm = Output(Bool())
val killx = Input(Bool())
val killm = Input(Bool())
val dec = Output(new FPUCtrlSigs())
val sboard_set = Output(Bool())
val sboard_clr = Output(Bool())
val sboard_clra = Output(UInt(5.W))
val keep_clock_enabled = Input(Bool())
}
class FPUIO(implicit p: Parameters) extends FPUCoreIO ()(p) {
val cp_req = Flipped(Decoupled(new FPInput())) //cp doesn't pay attn to kill sigs
val cp_resp = Decoupled(new FPResult())
}
class FPResult(implicit p: Parameters) extends CoreBundle()(p) {
val data = Bits((fLen+1).W)
val exc = Bits(FPConstants.FLAGS_SZ.W)
}
class IntToFPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs {
val rm = Bits(FPConstants.RM_SZ.W)
val typ = Bits(2.W)
val in1 = Bits(xLen.W)
}
class FPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs {
val rm = Bits(FPConstants.RM_SZ.W)
val fmaCmd = Bits(2.W)
val typ = Bits(2.W)
val fmt = Bits(2.W)
val in1 = Bits((fLen+1).W)
val in2 = Bits((fLen+1).W)
val in3 = Bits((fLen+1).W)
}
case class FType(exp: Int, sig: Int) {
def ieeeWidth = exp + sig
def recodedWidth = ieeeWidth + 1
def ieeeQNaN = ((BigInt(1) << (ieeeWidth - 1)) - (BigInt(1) << (sig - 2))).U(ieeeWidth.W)
def qNaN = ((BigInt(7) << (exp + sig - 3)) + (BigInt(1) << (sig - 2))).U(recodedWidth.W)
def isNaN(x: UInt) = x(sig + exp - 1, sig + exp - 3).andR
def isSNaN(x: UInt) = isNaN(x) && !x(sig - 2)
def classify(x: UInt) = {
val sign = x(sig + exp)
val code = x(exp + sig - 1, exp + sig - 3)
val codeHi = code(2, 1)
val isSpecial = codeHi === 3.U
val isHighSubnormalIn = x(exp + sig - 3, sig - 1) < 2.U
val isSubnormal = code === 1.U || codeHi === 1.U && isHighSubnormalIn
val isNormal = codeHi === 1.U && !isHighSubnormalIn || codeHi === 2.U
val isZero = code === 0.U
val isInf = isSpecial && !code(0)
val isNaN = code.andR
val isSNaN = isNaN && !x(sig-2)
val isQNaN = isNaN && x(sig-2)
Cat(isQNaN, isSNaN, isInf && !sign, isNormal && !sign,
isSubnormal && !sign, isZero && !sign, isZero && sign,
isSubnormal && sign, isNormal && sign, isInf && sign)
}
// convert between formats, ignoring rounding, range, NaN
def unsafeConvert(x: UInt, to: FType) = if (this == to) x else {
val sign = x(sig + exp)
val fractIn = x(sig - 2, 0)
val expIn = x(sig + exp - 1, sig - 1)
val fractOut = fractIn << to.sig >> sig
val expOut = {
val expCode = expIn(exp, exp - 2)
val commonCase = (expIn + (1 << to.exp).U) - (1 << exp).U
Mux(expCode === 0.U || expCode >= 6.U, Cat(expCode, commonCase(to.exp - 3, 0)), commonCase(to.exp, 0))
}
Cat(sign, expOut, fractOut)
}
private def ieeeBundle = {
val expWidth = exp
class IEEEBundle extends Bundle {
val sign = Bool()
val exp = UInt(expWidth.W)
val sig = UInt((ieeeWidth-expWidth-1).W)
}
new IEEEBundle
}
def unpackIEEE(x: UInt) = x.asTypeOf(ieeeBundle)
def recode(x: UInt) = hardfloat.recFNFromFN(exp, sig, x)
def ieee(x: UInt) = hardfloat.fNFromRecFN(exp, sig, x)
}
object FType {
val H = new FType(5, 11)
val S = new FType(8, 24)
val D = new FType(11, 53)
val all = List(H, S, D)
}
trait HasFPUParameters {
require(fLen == 0 || FType.all.exists(_.ieeeWidth == fLen))
val minFLen: Int
val fLen: Int
def xLen: Int
val minXLen = 32
val nIntTypes = log2Ceil(xLen/minXLen) + 1
def floatTypes = FType.all.filter(t => minFLen <= t.ieeeWidth && t.ieeeWidth <= fLen)
def minType = floatTypes.head
def maxType = floatTypes.last
def prevType(t: FType) = floatTypes(typeTag(t) - 1)
def maxExpWidth = maxType.exp
def maxSigWidth = maxType.sig
def typeTag(t: FType) = floatTypes.indexOf(t)
def typeTagWbOffset = (FType.all.indexOf(minType) + 1).U
def typeTagGroup(t: FType) = (if (floatTypes.contains(t)) typeTag(t) else typeTag(maxType)).U
// typeTag
def H = typeTagGroup(FType.H)
def S = typeTagGroup(FType.S)
def D = typeTagGroup(FType.D)
def I = typeTag(maxType).U
private def isBox(x: UInt, t: FType): Bool = x(t.sig + t.exp, t.sig + t.exp - 4).andR
private def box(x: UInt, xt: FType, y: UInt, yt: FType): UInt = {
require(xt.ieeeWidth == 2 * yt.ieeeWidth)
val swizzledNaN = Cat(
x(xt.sig + xt.exp, xt.sig + xt.exp - 3),
x(xt.sig - 2, yt.recodedWidth - 1).andR,
x(xt.sig + xt.exp - 5, xt.sig),
y(yt.recodedWidth - 2),
x(xt.sig - 2, yt.recodedWidth - 1),
y(yt.recodedWidth - 1),
y(yt.recodedWidth - 3, 0))
Mux(xt.isNaN(x), swizzledNaN, x)
}
// implement NaN unboxing for FU inputs
def unbox(x: UInt, tag: UInt, exactType: Option[FType]): UInt = {
val outType = exactType.getOrElse(maxType)
def helper(x: UInt, t: FType): Seq[(Bool, UInt)] = {
val prev =
if (t == minType) {
Seq()
} else {
val prevT = prevType(t)
val unswizzled = Cat(
x(prevT.sig + prevT.exp - 1),
x(t.sig - 1),
x(prevT.sig + prevT.exp - 2, 0))
val prev = helper(unswizzled, prevT)
val isbox = isBox(x, t)
prev.map(p => (isbox && p._1, p._2))
}
prev :+ (true.B, t.unsafeConvert(x, outType))
}
val (oks, floats) = helper(x, maxType).unzip
if (exactType.isEmpty || floatTypes.size == 1) {
Mux(oks(tag), floats(tag), maxType.qNaN)
} else {
val t = exactType.get
floats(typeTag(t)) | Mux(oks(typeTag(t)), 0.U, t.qNaN)
}
}
// make sure that the redundant bits in the NaN-boxed encoding are consistent
def consistent(x: UInt): Bool = {
def helper(x: UInt, t: FType): Bool = if (typeTag(t) == 0) true.B else {
val prevT = prevType(t)
val unswizzled = Cat(
x(prevT.sig + prevT.exp - 1),
x(t.sig - 1),
x(prevT.sig + prevT.exp - 2, 0))
val prevOK = !isBox(x, t) || helper(unswizzled, prevT)
val curOK = !t.isNaN(x) || x(t.sig + t.exp - 4) === x(t.sig - 2, prevT.recodedWidth - 1).andR
prevOK && curOK
}
helper(x, maxType)
}
// generate a NaN box from an FU result
def box(x: UInt, t: FType): UInt = {
if (t == maxType) {
x
} else {
val nt = floatTypes(typeTag(t) + 1)
val bigger = box(((BigInt(1) << nt.recodedWidth)-1).U, nt, x, t)
bigger | ((BigInt(1) << maxType.recodedWidth) - (BigInt(1) << nt.recodedWidth)).U
}
}
// generate a NaN box from an FU result
def box(x: UInt, tag: UInt): UInt = {
val opts = floatTypes.map(t => box(x, t))
opts(tag)
}
// zap bits that hardfloat thinks are don't-cares, but we do care about
def sanitizeNaN(x: UInt, t: FType): UInt = {
if (typeTag(t) == 0) {
x
} else {
val maskedNaN = x & ~((BigInt(1) << (t.sig-1)) | (BigInt(1) << (t.sig+t.exp-4))).U(t.recodedWidth.W)
Mux(t.isNaN(x), maskedNaN, x)
}
}
// implement NaN boxing and recoding for FL*/fmv.*.x
def recode(x: UInt, tag: UInt): UInt = {
def helper(x: UInt, t: FType): UInt = {
if (typeTag(t) == 0) {
t.recode(x)
} else {
val prevT = prevType(t)
box(t.recode(x), t, helper(x, prevT), prevT)
}
}
// fill MSBs of subword loads to emulate a wider load of a NaN-boxed value
val boxes = floatTypes.map(t => ((BigInt(1) << maxType.ieeeWidth) - (BigInt(1) << t.ieeeWidth)).U)
helper(boxes(tag) | x, maxType)
}
// implement NaN unboxing and un-recoding for FS*/fmv.x.*
def ieee(x: UInt, t: FType = maxType): UInt = {
if (typeTag(t) == 0) {
t.ieee(x)
} else {
val unrecoded = t.ieee(x)
val prevT = prevType(t)
val prevRecoded = Cat(
x(prevT.recodedWidth-2),
x(t.sig-1),
x(prevT.recodedWidth-3, 0))
val prevUnrecoded = ieee(prevRecoded, prevT)
Cat(unrecoded >> prevT.ieeeWidth, Mux(t.isNaN(x), prevUnrecoded, unrecoded(prevT.ieeeWidth-1, 0)))
}
}
}
abstract class FPUModule(implicit val p: Parameters) extends Module with HasCoreParameters with HasFPUParameters
class FPToInt(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {
class Output extends Bundle {
val in = new FPInput
val lt = Bool()
val store = Bits(fLen.W)
val toint = Bits(xLen.W)
val exc = Bits(FPConstants.FLAGS_SZ.W)
}
val io = IO(new Bundle {
val in = Flipped(Valid(new FPInput))
val out = Valid(new Output)
})
val in = RegEnable(io.in.bits, io.in.valid)
val valid = RegNext(io.in.valid)
val dcmp = Module(new hardfloat.CompareRecFN(maxExpWidth, maxSigWidth))
dcmp.io.a := in.in1
dcmp.io.b := in.in2
dcmp.io.signaling := !in.rm(1)
val tag = in.typeTagOut
val toint_ieee = (floatTypes.map(t => if (t == FType.H) Fill(maxType.ieeeWidth / minXLen, ieee(in.in1)(15, 0).sextTo(minXLen))
else Fill(maxType.ieeeWidth / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag)
val toint = WireDefault(toint_ieee)
val intType = WireDefault(in.fmt(0))
io.out.bits.store := (floatTypes.map(t => Fill(fLen / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag)
io.out.bits.toint := ((0 until nIntTypes).map(i => toint((minXLen << i) - 1, 0).sextTo(xLen)): Seq[UInt])(intType)
io.out.bits.exc := 0.U
when (in.rm(0)) {
val classify_out = (floatTypes.map(t => t.classify(maxType.unsafeConvert(in.in1, t))): Seq[UInt])(tag)
toint := classify_out | (toint_ieee >> minXLen << minXLen)
intType := false.B
}
when (in.wflags) { // feq/flt/fle, fcvt
toint := (~in.rm & Cat(dcmp.io.lt, dcmp.io.eq)).orR | (toint_ieee >> minXLen << minXLen)
io.out.bits.exc := dcmp.io.exceptionFlags
intType := false.B
when (!in.ren2) { // fcvt
val cvtType = in.typ.extract(log2Ceil(nIntTypes), 1)
intType := cvtType
val conv = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, xLen))
conv.io.in := in.in1
conv.io.roundingMode := in.rm
conv.io.signedOut := ~in.typ(0)
toint := conv.io.out
io.out.bits.exc := Cat(conv.io.intExceptionFlags(2, 1).orR, 0.U(3.W), conv.io.intExceptionFlags(0))
for (i <- 0 until nIntTypes-1) {
val w = minXLen << i
when (cvtType === i.U) {
val narrow = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, w))
narrow.io.in := in.in1
narrow.io.roundingMode := in.rm
narrow.io.signedOut := ~in.typ(0)
val excSign = in.in1(maxExpWidth + maxSigWidth) && !maxType.isNaN(in.in1)
val excOut = Cat(conv.io.signedOut === excSign, Fill(w-1, !excSign))
val invalid = conv.io.intExceptionFlags(2) || narrow.io.intExceptionFlags(1)
when (invalid) { toint := Cat(conv.io.out >> w, excOut) }
io.out.bits.exc := Cat(invalid, 0.U(3.W), !invalid && conv.io.intExceptionFlags(0))
}
}
}
}
io.out.valid := valid
io.out.bits.lt := dcmp.io.lt || (dcmp.io.a.asSInt < 0.S && dcmp.io.b.asSInt >= 0.S)
io.out.bits.in := in
}
class IntToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {
val io = IO(new Bundle {
val in = Flipped(Valid(new IntToFPInput))
val out = Valid(new FPResult)
})
val in = Pipe(io.in)
val tag = in.bits.typeTagIn
val mux = Wire(new FPResult)
mux.exc := 0.U
mux.data := recode(in.bits.in1, tag)
val intValue = {
val res = WireDefault(in.bits.in1.asSInt)
for (i <- 0 until nIntTypes-1) {
val smallInt = in.bits.in1((minXLen << i) - 1, 0)
when (in.bits.typ.extract(log2Ceil(nIntTypes), 1) === i.U) {
res := Mux(in.bits.typ(0), smallInt.zext, smallInt.asSInt)
}
}
res.asUInt
}
when (in.bits.wflags) { // fcvt
// could be improved for RVD/RVQ with a single variable-position rounding
// unit, rather than N fixed-position ones
val i2fResults = for (t <- floatTypes) yield {
val i2f = Module(new hardfloat.INToRecFN(xLen, t.exp, t.sig))
i2f.io.signedIn := ~in.bits.typ(0)
i2f.io.in := intValue
i2f.io.roundingMode := in.bits.rm
i2f.io.detectTininess := hardfloat.consts.tininess_afterRounding
(sanitizeNaN(i2f.io.out, t), i2f.io.exceptionFlags)
}
val (data, exc) = i2fResults.unzip
val dataPadded = data.init.map(d => Cat(data.last >> d.getWidth, d)) :+ data.last
mux.data := dataPadded(tag)
mux.exc := exc(tag)
}
io.out <> Pipe(in.valid, mux, latency-1)
}
class FPToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {
val io = IO(new Bundle {
val in = Flipped(Valid(new FPInput))
val out = Valid(new FPResult)
val lt = Input(Bool()) // from FPToInt
})
val in = Pipe(io.in)
val signNum = Mux(in.bits.rm(1), in.bits.in1 ^ in.bits.in2, Mux(in.bits.rm(0), ~in.bits.in2, in.bits.in2))
val fsgnj = Cat(signNum(fLen), in.bits.in1(fLen-1, 0))
val fsgnjMux = Wire(new FPResult)
fsgnjMux.exc := 0.U
fsgnjMux.data := fsgnj
when (in.bits.wflags) { // fmin/fmax
val isnan1 = maxType.isNaN(in.bits.in1)
val isnan2 = maxType.isNaN(in.bits.in2)
val isInvalid = maxType.isSNaN(in.bits.in1) || maxType.isSNaN(in.bits.in2)
val isNaNOut = isnan1 && isnan2
val isLHS = isnan2 || in.bits.rm(0) =/= io.lt && !isnan1
fsgnjMux.exc := isInvalid << 4
fsgnjMux.data := Mux(isNaNOut, maxType.qNaN, Mux(isLHS, in.bits.in1, in.bits.in2))
}
val inTag = in.bits.typeTagIn
val outTag = in.bits.typeTagOut
val mux = WireDefault(fsgnjMux)
for (t <- floatTypes.init) {
when (outTag === typeTag(t).U) {
mux.data := Cat(fsgnjMux.data >> t.recodedWidth, maxType.unsafeConvert(fsgnjMux.data, t))
}
}
when (in.bits.wflags && !in.bits.ren2) { // fcvt
if (floatTypes.size > 1) {
// widening conversions simply canonicalize NaN operands
val widened = Mux(maxType.isNaN(in.bits.in1), maxType.qNaN, in.bits.in1)
fsgnjMux.data := widened
fsgnjMux.exc := maxType.isSNaN(in.bits.in1) << 4
// narrowing conversions require rounding (for RVQ, this could be
// optimized to use a single variable-position rounding unit, rather
// than two fixed-position ones)
for (outType <- floatTypes.init) when (outTag === typeTag(outType).U && ((typeTag(outType) == 0).B || outTag < inTag)) {
val narrower = Module(new hardfloat.RecFNToRecFN(maxType.exp, maxType.sig, outType.exp, outType.sig))
narrower.io.in := in.bits.in1
narrower.io.roundingMode := in.bits.rm
narrower.io.detectTininess := hardfloat.consts.tininess_afterRounding
val narrowed = sanitizeNaN(narrower.io.out, outType)
mux.data := Cat(fsgnjMux.data >> narrowed.getWidth, narrowed)
mux.exc := narrower.io.exceptionFlags
}
}
}
io.out <> Pipe(in.valid, mux, latency-1)
}
class MulAddRecFNPipe(latency: Int, expWidth: Int, sigWidth: Int) extends Module
{
override def desiredName = s"MulAddRecFNPipe_l${latency}_e${expWidth}_s${sigWidth}"
require(latency<=2)
val io = IO(new Bundle {
val validin = Input(Bool())
val op = Input(Bits(2.W))
val a = Input(Bits((expWidth + sigWidth + 1).W))
val b = Input(Bits((expWidth + sigWidth + 1).W))
val c = Input(Bits((expWidth + sigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
val validout = Output(Bool())
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val mulAddRecFNToRaw_preMul = Module(new hardfloat.MulAddRecFNToRaw_preMul(expWidth, sigWidth))
val mulAddRecFNToRaw_postMul = Module(new hardfloat.MulAddRecFNToRaw_postMul(expWidth, sigWidth))
mulAddRecFNToRaw_preMul.io.op := io.op
mulAddRecFNToRaw_preMul.io.a := io.a
mulAddRecFNToRaw_preMul.io.b := io.b
mulAddRecFNToRaw_preMul.io.c := io.c
val mulAddResult =
(mulAddRecFNToRaw_preMul.io.mulAddA *
mulAddRecFNToRaw_preMul.io.mulAddB) +&
mulAddRecFNToRaw_preMul.io.mulAddC
val valid_stage0 = Wire(Bool())
val roundingMode_stage0 = Wire(UInt(3.W))
val detectTininess_stage0 = Wire(UInt(1.W))
val postmul_regs = if(latency>0) 1 else 0
mulAddRecFNToRaw_postMul.io.fromPreMul := Pipe(io.validin, mulAddRecFNToRaw_preMul.io.toPostMul, postmul_regs).bits
mulAddRecFNToRaw_postMul.io.mulAddResult := Pipe(io.validin, mulAddResult, postmul_regs).bits
mulAddRecFNToRaw_postMul.io.roundingMode := Pipe(io.validin, io.roundingMode, postmul_regs).bits
roundingMode_stage0 := Pipe(io.validin, io.roundingMode, postmul_regs).bits
detectTininess_stage0 := Pipe(io.validin, io.detectTininess, postmul_regs).bits
valid_stage0 := Pipe(io.validin, false.B, postmul_regs).valid
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundRawFNToRecFN = Module(new hardfloat.RoundRawFNToRecFN(expWidth, sigWidth, 0))
val round_regs = if(latency==2) 1 else 0
roundRawFNToRecFN.io.invalidExc := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.invalidExc, round_regs).bits
roundRawFNToRecFN.io.in := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.rawOut, round_regs).bits
roundRawFNToRecFN.io.roundingMode := Pipe(valid_stage0, roundingMode_stage0, round_regs).bits
roundRawFNToRecFN.io.detectTininess := Pipe(valid_stage0, detectTininess_stage0, round_regs).bits
io.validout := Pipe(valid_stage0, false.B, round_regs).valid
roundRawFNToRecFN.io.infiniteExc := false.B
io.out := roundRawFNToRecFN.io.out
io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags
}
class FPUFMAPipe(val latency: Int, val t: FType)
(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {
override def desiredName = s"FPUFMAPipe_l${latency}_f${t.ieeeWidth}"
require(latency>0)
val io = IO(new Bundle {
val in = Flipped(Valid(new FPInput))
val out = Valid(new FPResult)
})
val valid = RegNext(io.in.valid)
val in = Reg(new FPInput)
when (io.in.valid) {
val one = 1.U << (t.sig + t.exp - 1)
val zero = (io.in.bits.in1 ^ io.in.bits.in2) & (1.U << (t.sig + t.exp))
val cmd_fma = io.in.bits.ren3
val cmd_addsub = io.in.bits.swap23
in := io.in.bits
when (cmd_addsub) { in.in2 := one }
when (!(cmd_fma || cmd_addsub)) { in.in3 := zero }
}
val fma = Module(new MulAddRecFNPipe((latency-1) min 2, t.exp, t.sig))
fma.io.validin := valid
fma.io.op := in.fmaCmd
fma.io.roundingMode := in.rm
fma.io.detectTininess := hardfloat.consts.tininess_afterRounding
fma.io.a := in.in1
fma.io.b := in.in2
fma.io.c := in.in3
val res = Wire(new FPResult)
res.data := sanitizeNaN(fma.io.out, t)
res.exc := fma.io.exceptionFlags
io.out := Pipe(fma.io.validout, res, (latency-3) max 0)
}
class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) {
val io = IO(new FPUIO)
val (useClockGating, useDebugROB) = coreParams match {
case r: RocketCoreParams =>
val sz = if (r.debugROB.isDefined) r.debugROB.get.size else 1
(r.clockGate, sz < 1)
case _ => (false, false)
}
val clock_en_reg = Reg(Bool())
val clock_en = clock_en_reg || io.cp_req.valid
val gated_clock =
if (!useClockGating) clock
else ClockGate(clock, clock_en, "fpu_clock_gate")
val fp_decoder = Module(new FPUDecoder)
fp_decoder.io.inst := io.inst
val id_ctrl = WireInit(fp_decoder.io.sigs)
coreParams match { case r: RocketCoreParams => r.vector.map(v => {
val v_decode = v.decoder(p) // Only need to get ren1
v_decode.io.inst := io.inst
v_decode.io.vconfig := DontCare // core deals with this
when (v_decode.io.legal && v_decode.io.read_frs1) {
id_ctrl.ren1 := true.B
id_ctrl.swap12 := false.B
id_ctrl.toint := true.B
id_ctrl.typeTagIn := I
id_ctrl.typeTagOut := Mux(io.v_sew === 3.U, D, S)
}
when (v_decode.io.write_frd) { id_ctrl.wen := true.B }
})}
val ex_reg_valid = RegNext(io.valid, false.B)
val ex_reg_inst = RegEnable(io.inst, io.valid)
val ex_reg_ctrl = RegEnable(id_ctrl, io.valid)
val ex_ra = List.fill(3)(Reg(UInt()))
// load/vector response
val load_wb = RegNext(io.ll_resp_val)
val load_wb_typeTag = RegEnable(io.ll_resp_type(1,0) - typeTagWbOffset, io.ll_resp_val)
val load_wb_data = RegEnable(io.ll_resp_data, io.ll_resp_val)
val load_wb_tag = RegEnable(io.ll_resp_tag, io.ll_resp_val)
class FPUImpl { // entering gated-clock domain
val req_valid = ex_reg_valid || io.cp_req.valid
val ex_cp_valid = io.cp_req.fire
val mem_cp_valid = RegNext(ex_cp_valid, false.B)
val wb_cp_valid = RegNext(mem_cp_valid, false.B)
val mem_reg_valid = RegInit(false.B)
val killm = (io.killm || io.nack_mem) && !mem_cp_valid
// Kill X-stage instruction if M-stage is killed. This prevents it from
// speculatively being sent to the div-sqrt unit, which can cause priority
// inversion for two back-to-back divides, the first of which is killed.
val killx = io.killx || mem_reg_valid && killm
mem_reg_valid := ex_reg_valid && !killx || ex_cp_valid
val mem_reg_inst = RegEnable(ex_reg_inst, ex_reg_valid)
val wb_reg_valid = RegNext(mem_reg_valid && (!killm || mem_cp_valid), false.B)
val cp_ctrl = Wire(new FPUCtrlSigs)
cp_ctrl :<>= io.cp_req.bits.viewAsSupertype(new FPUCtrlSigs)
io.cp_resp.valid := false.B
io.cp_resp.bits.data := 0.U
io.cp_resp.bits.exc := DontCare
val ex_ctrl = Mux(ex_cp_valid, cp_ctrl, ex_reg_ctrl)
val mem_ctrl = RegEnable(ex_ctrl, req_valid)
val wb_ctrl = RegEnable(mem_ctrl, mem_reg_valid)
// CoreMonitorBundle to monitor fp register file writes
val frfWriteBundle = Seq.fill(2)(WireInit(new CoreMonitorBundle(xLen, fLen), DontCare))
frfWriteBundle.foreach { i =>
i.clock := clock
i.reset := reset
i.hartid := io.hartid
i.timer := io.time(31,0)
i.valid := false.B
i.wrenx := false.B
i.wrenf := false.B
i.excpt := false.B
}
// regfile
val regfile = Mem(32, Bits((fLen+1).W))
when (load_wb) {
val wdata = recode(load_wb_data, load_wb_typeTag)
regfile(load_wb_tag) := wdata
assert(consistent(wdata))
if (enableCommitLog)
printf("f%d p%d 0x%x\n", load_wb_tag, load_wb_tag + 32.U, ieee(wdata))
if (useDebugROB)
DebugROB.pushWb(clock, reset, io.hartid, load_wb, load_wb_tag + 32.U, ieee(wdata))
frfWriteBundle(0).wrdst := load_wb_tag
frfWriteBundle(0).wrenf := true.B
frfWriteBundle(0).wrdata := ieee(wdata)
}
val ex_rs = ex_ra.map(a => regfile(a))
when (io.valid) {
when (id_ctrl.ren1) {
when (!id_ctrl.swap12) { ex_ra(0) := io.inst(19,15) }
when (id_ctrl.swap12) { ex_ra(1) := io.inst(19,15) }
}
when (id_ctrl.ren2) {
when (id_ctrl.swap12) { ex_ra(0) := io.inst(24,20) }
when (id_ctrl.swap23) { ex_ra(2) := io.inst(24,20) }
when (!id_ctrl.swap12 && !id_ctrl.swap23) { ex_ra(1) := io.inst(24,20) }
}
when (id_ctrl.ren3) { ex_ra(2) := io.inst(31,27) }
}
val ex_rm = Mux(ex_reg_inst(14,12) === 7.U, io.fcsr_rm, ex_reg_inst(14,12))
def fuInput(minT: Option[FType]): FPInput = {
val req = Wire(new FPInput)
val tag = ex_ctrl.typeTagIn
req.viewAsSupertype(new Bundle with HasFPUCtrlSigs) :#= ex_ctrl.viewAsSupertype(new Bundle with HasFPUCtrlSigs)
req.rm := ex_rm
req.in1 := unbox(ex_rs(0), tag, minT)
req.in2 := unbox(ex_rs(1), tag, minT)
req.in3 := unbox(ex_rs(2), tag, minT)
req.typ := ex_reg_inst(21,20)
req.fmt := ex_reg_inst(26,25)
req.fmaCmd := ex_reg_inst(3,2) | (!ex_ctrl.ren3 && ex_reg_inst(27))
when (ex_cp_valid) {
req := io.cp_req.bits
when (io.cp_req.bits.swap12) {
req.in1 := io.cp_req.bits.in2
req.in2 := io.cp_req.bits.in1
}
when (io.cp_req.bits.swap23) {
req.in2 := io.cp_req.bits.in3
req.in3 := io.cp_req.bits.in2
}
}
req
}
val sfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.S))
sfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === S
sfma.io.in.bits := fuInput(Some(sfma.t))
val fpiu = Module(new FPToInt)
fpiu.io.in.valid := req_valid && (ex_ctrl.toint || ex_ctrl.div || ex_ctrl.sqrt || (ex_ctrl.fastpipe && ex_ctrl.wflags))
fpiu.io.in.bits := fuInput(None)
io.store_data := fpiu.io.out.bits.store
io.toint_data := fpiu.io.out.bits.toint
when(fpiu.io.out.valid && mem_cp_valid && mem_ctrl.toint){
io.cp_resp.bits.data := fpiu.io.out.bits.toint
io.cp_resp.valid := true.B
}
val ifpu = Module(new IntToFP(cfg.ifpuLatency))
ifpu.io.in.valid := req_valid && ex_ctrl.fromint
ifpu.io.in.bits := fpiu.io.in.bits
ifpu.io.in.bits.in1 := Mux(ex_cp_valid, io.cp_req.bits.in1, io.fromint_data)
val fpmu = Module(new FPToFP(cfg.fpmuLatency))
fpmu.io.in.valid := req_valid && ex_ctrl.fastpipe
fpmu.io.in.bits := fpiu.io.in.bits
fpmu.io.lt := fpiu.io.out.bits.lt
val divSqrt_wen = WireDefault(false.B)
val divSqrt_inFlight = WireDefault(false.B)
val divSqrt_waddr = Reg(UInt(5.W))
val divSqrt_cp = Reg(Bool())
val divSqrt_typeTag = Wire(UInt(log2Up(floatTypes.size).W))
val divSqrt_wdata = Wire(UInt((fLen+1).W))
val divSqrt_flags = Wire(UInt(FPConstants.FLAGS_SZ.W))
divSqrt_typeTag := DontCare
divSqrt_wdata := DontCare
divSqrt_flags := DontCare
// writeback arbitration
case class Pipe(p: Module, lat: Int, cond: (FPUCtrlSigs) => Bool, res: FPResult)
val pipes = List(
Pipe(fpmu, fpmu.latency, (c: FPUCtrlSigs) => c.fastpipe, fpmu.io.out.bits),
Pipe(ifpu, ifpu.latency, (c: FPUCtrlSigs) => c.fromint, ifpu.io.out.bits),
Pipe(sfma, sfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === S, sfma.io.out.bits)) ++
(fLen > 32).option({
val dfma = Module(new FPUFMAPipe(cfg.dfmaLatency, FType.D))
dfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === D
dfma.io.in.bits := fuInput(Some(dfma.t))
Pipe(dfma, dfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === D, dfma.io.out.bits)
}) ++
(minFLen == 16).option({
val hfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.H))
hfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === H
hfma.io.in.bits := fuInput(Some(hfma.t))
Pipe(hfma, hfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === H, hfma.io.out.bits)
})
def latencyMask(c: FPUCtrlSigs, offset: Int) = {
require(pipes.forall(_.lat >= offset))
pipes.map(p => Mux(p.cond(c), (1 << p.lat-offset).U, 0.U)).reduce(_|_)
}
def pipeid(c: FPUCtrlSigs) = pipes.zipWithIndex.map(p => Mux(p._1.cond(c), p._2.U, 0.U)).reduce(_|_)
val maxLatency = pipes.map(_.lat).max
val memLatencyMask = latencyMask(mem_ctrl, 2)
class WBInfo extends Bundle {
val rd = UInt(5.W)
val typeTag = UInt(log2Up(floatTypes.size).W)
val cp = Bool()
val pipeid = UInt(log2Ceil(pipes.size).W)
}
val wen = RegInit(0.U((maxLatency-1).W))
val wbInfo = Reg(Vec(maxLatency-1, new WBInfo))
val mem_wen = mem_reg_valid && (mem_ctrl.fma || mem_ctrl.fastpipe || mem_ctrl.fromint)
val write_port_busy = RegEnable(mem_wen && (memLatencyMask & latencyMask(ex_ctrl, 1)).orR || (wen & latencyMask(ex_ctrl, 0)).orR, req_valid)
ccover(mem_reg_valid && write_port_busy, "WB_STRUCTURAL", "structural hazard on writeback")
for (i <- 0 until maxLatency-2) {
when (wen(i+1)) { wbInfo(i) := wbInfo(i+1) }
}
wen := wen >> 1
when (mem_wen) {
when (!killm) {
wen := wen >> 1 | memLatencyMask
}
for (i <- 0 until maxLatency-1) {
when (!write_port_busy && memLatencyMask(i)) {
wbInfo(i).cp := mem_cp_valid
wbInfo(i).typeTag := mem_ctrl.typeTagOut
wbInfo(i).pipeid := pipeid(mem_ctrl)
wbInfo(i).rd := mem_reg_inst(11,7)
}
}
}
val waddr = Mux(divSqrt_wen, divSqrt_waddr, wbInfo(0).rd)
val wb_cp = Mux(divSqrt_wen, divSqrt_cp, wbInfo(0).cp)
val wtypeTag = Mux(divSqrt_wen, divSqrt_typeTag, wbInfo(0).typeTag)
val wdata = box(Mux(divSqrt_wen, divSqrt_wdata, (pipes.map(_.res.data): Seq[UInt])(wbInfo(0).pipeid)), wtypeTag)
val wexc = (pipes.map(_.res.exc): Seq[UInt])(wbInfo(0).pipeid)
when ((!wbInfo(0).cp && wen(0)) || divSqrt_wen) {
assert(consistent(wdata))
regfile(waddr) := wdata
if (enableCommitLog) {
printf("f%d p%d 0x%x\n", waddr, waddr + 32.U, ieee(wdata))
}
frfWriteBundle(1).wrdst := waddr
frfWriteBundle(1).wrenf := true.B
frfWriteBundle(1).wrdata := ieee(wdata)
}
if (useDebugROB) {
DebugROB.pushWb(clock, reset, io.hartid, (!wbInfo(0).cp && wen(0)) || divSqrt_wen, waddr + 32.U, ieee(wdata))
}
when (wb_cp && (wen(0) || divSqrt_wen)) {
io.cp_resp.bits.data := wdata
io.cp_resp.valid := true.B
}
assert(!io.cp_req.valid || pipes.forall(_.lat == pipes.head.lat).B,
s"FPU only supports coprocessor if FMA pipes have uniform latency ${pipes.map(_.lat)}")
// Avoid structural hazards and nacking of external requests
// toint responds in the MEM stage, so an incoming toint can induce a structural hazard against inflight FMAs
io.cp_req.ready := !ex_reg_valid && !(cp_ctrl.toint && wen =/= 0.U) && !divSqrt_inFlight
val wb_toint_valid = wb_reg_valid && wb_ctrl.toint
val wb_toint_exc = RegEnable(fpiu.io.out.bits.exc, mem_ctrl.toint)
io.fcsr_flags.valid := wb_toint_valid || divSqrt_wen || wen(0)
io.fcsr_flags.bits :=
Mux(wb_toint_valid, wb_toint_exc, 0.U) |
Mux(divSqrt_wen, divSqrt_flags, 0.U) |
Mux(wen(0), wexc, 0.U)
val divSqrt_write_port_busy = (mem_ctrl.div || mem_ctrl.sqrt) && wen.orR
io.fcsr_rdy := !(ex_reg_valid && ex_ctrl.wflags || mem_reg_valid && mem_ctrl.wflags || wb_reg_valid && wb_ctrl.toint || wen.orR || divSqrt_inFlight)
io.nack_mem := (write_port_busy || divSqrt_write_port_busy || divSqrt_inFlight) && !mem_cp_valid
io.dec <> id_ctrl
def useScoreboard(f: ((Pipe, Int)) => Bool) = pipes.zipWithIndex.filter(_._1.lat > 3).map(x => f(x)).fold(false.B)(_||_)
io.sboard_set := wb_reg_valid && !wb_cp_valid && RegNext(useScoreboard(_._1.cond(mem_ctrl)) || mem_ctrl.div || mem_ctrl.sqrt || mem_ctrl.vec)
io.sboard_clr := !wb_cp_valid && (divSqrt_wen || (wen(0) && useScoreboard(x => wbInfo(0).pipeid === x._2.U)))
io.sboard_clra := waddr
ccover(io.sboard_clr && load_wb, "DUAL_WRITEBACK", "load and FMA writeback on same cycle")
// we don't currently support round-max-magnitude (rm=4)
io.illegal_rm := io.inst(14,12).isOneOf(5.U, 6.U) || io.inst(14,12) === 7.U && io.fcsr_rm >= 5.U
if (cfg.divSqrt) {
val divSqrt_inValid = mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt) && !divSqrt_inFlight
val divSqrt_killed = RegNext(divSqrt_inValid && killm, true.B)
when (divSqrt_inValid) {
divSqrt_waddr := mem_reg_inst(11,7)
divSqrt_cp := mem_cp_valid
}
ccover(divSqrt_inFlight && divSqrt_killed, "DIV_KILLED", "divide killed after issued to divider")
ccover(divSqrt_inFlight && mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt), "DIV_BUSY", "divider structural hazard")
ccover(mem_reg_valid && divSqrt_write_port_busy, "DIV_WB_STRUCTURAL", "structural hazard on division writeback")
for (t <- floatTypes) {
val tag = mem_ctrl.typeTagOut
val divSqrt = withReset(divSqrt_killed) { Module(new hardfloat.DivSqrtRecFN_small(t.exp, t.sig, 0)) }
divSqrt.io.inValid := divSqrt_inValid && tag === typeTag(t).U
divSqrt.io.sqrtOp := mem_ctrl.sqrt
divSqrt.io.a := maxType.unsafeConvert(fpiu.io.out.bits.in.in1, t)
divSqrt.io.b := maxType.unsafeConvert(fpiu.io.out.bits.in.in2, t)
divSqrt.io.roundingMode := fpiu.io.out.bits.in.rm
divSqrt.io.detectTininess := hardfloat.consts.tininess_afterRounding
when (!divSqrt.io.inReady) { divSqrt_inFlight := true.B } // only 1 in flight
when (divSqrt.io.outValid_div || divSqrt.io.outValid_sqrt) {
divSqrt_wen := !divSqrt_killed
divSqrt_wdata := sanitizeNaN(divSqrt.io.out, t)
divSqrt_flags := divSqrt.io.exceptionFlags
divSqrt_typeTag := typeTag(t).U
}
}
when (divSqrt_killed) { divSqrt_inFlight := false.B }
} else {
when (id_ctrl.div || id_ctrl.sqrt) { io.illegal_rm := true.B }
}
// gate the clock
clock_en_reg := !useClockGating.B ||
io.keep_clock_enabled || // chicken bit
io.valid || // ID stage
req_valid || // EX stage
mem_reg_valid || mem_cp_valid || // MEM stage
wb_reg_valid || wb_cp_valid || // WB stage
wen.orR || divSqrt_inFlight || // post-WB stage
io.ll_resp_val // load writeback
} // leaving gated-clock domain
val fpuImpl = withClock (gated_clock) { new FPUImpl }
def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) =
property.cover(cond, s"FPU_$label", "Core;;" + desc)
}
| module MulAddRecFNPipe_l2_e8_s24_1( // @[FPU.scala:633:7]
input clock, // @[FPU.scala:633:7]
input reset, // @[FPU.scala:633:7]
input io_validin, // @[FPU.scala:638:16]
input [1:0] io_op, // @[FPU.scala:638:16]
input [32:0] io_a, // @[FPU.scala:638:16]
input [32:0] io_b, // @[FPU.scala:638:16]
input [32:0] io_c, // @[FPU.scala:638:16]
input [2:0] io_roundingMode, // @[FPU.scala:638:16]
output [32:0] io_out, // @[FPU.scala:638:16]
output [4:0] io_exceptionFlags, // @[FPU.scala:638:16]
output io_validout // @[FPU.scala:638:16]
);
wire _mulAddRecFNToRaw_postMul_io_invalidExc; // @[FPU.scala:655:42]
wire _mulAddRecFNToRaw_postMul_io_rawOut_isNaN; // @[FPU.scala:655:42]
wire _mulAddRecFNToRaw_postMul_io_rawOut_isInf; // @[FPU.scala:655:42]
wire _mulAddRecFNToRaw_postMul_io_rawOut_isZero; // @[FPU.scala:655:42]
wire _mulAddRecFNToRaw_postMul_io_rawOut_sign; // @[FPU.scala:655:42]
wire [9:0] _mulAddRecFNToRaw_postMul_io_rawOut_sExp; // @[FPU.scala:655:42]
wire [26:0] _mulAddRecFNToRaw_postMul_io_rawOut_sig; // @[FPU.scala:655:42]
wire [23:0] _mulAddRecFNToRaw_preMul_io_mulAddA; // @[FPU.scala:654:41]
wire [23:0] _mulAddRecFNToRaw_preMul_io_mulAddB; // @[FPU.scala:654:41]
wire [47:0] _mulAddRecFNToRaw_preMul_io_mulAddC; // @[FPU.scala:654:41]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny; // @[FPU.scala:654:41]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB; // @[FPU.scala:654:41]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfA; // @[FPU.scala:654:41]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA; // @[FPU.scala:654:41]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfB; // @[FPU.scala:654:41]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB; // @[FPU.scala:654:41]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_signProd; // @[FPU.scala:654:41]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC; // @[FPU.scala:654:41]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfC; // @[FPU.scala:654:41]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC; // @[FPU.scala:654:41]
wire [9:0] _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum; // @[FPU.scala:654:41]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags; // @[FPU.scala:654:41]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant; // @[FPU.scala:654:41]
wire [4:0] _mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist; // @[FPU.scala:654:41]
wire [25:0] _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC; // @[FPU.scala:654:41]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC; // @[FPU.scala:654:41]
wire io_validin_0 = io_validin; // @[FPU.scala:633:7]
wire [1:0] io_op_0 = io_op; // @[FPU.scala:633:7]
wire [32:0] io_a_0 = io_a; // @[FPU.scala:633:7]
wire [32:0] io_b_0 = io_b; // @[FPU.scala:633:7]
wire [32:0] io_c_0 = io_c; // @[FPU.scala:633:7]
wire [2:0] io_roundingMode_0 = io_roundingMode; // @[FPU.scala:633:7]
wire io_detectTininess = 1'h1; // @[FPU.scala:633:7]
wire detectTininess_stage0 = 1'h1; // @[FPU.scala:669:37]
wire detectTininess_stage0_pipe_out_bits = 1'h1; // @[Valid.scala:135:21]
wire valid_stage0_pipe_out_bits = 1'h0; // @[Valid.scala:135:21]
wire io_validout_pipe_out_bits = 1'h0; // @[Valid.scala:135:21]
wire io_validout_pipe_out_valid; // @[Valid.scala:135:21]
wire [32:0] io_out_0; // @[FPU.scala:633:7]
wire [4:0] io_exceptionFlags_0; // @[FPU.scala:633:7]
wire io_validout_0; // @[FPU.scala:633:7]
wire [47:0] _mulAddResult_T = {24'h0, _mulAddRecFNToRaw_preMul_io_mulAddA} * {24'h0, _mulAddRecFNToRaw_preMul_io_mulAddB}; // @[FPU.scala:654:41, :663:45]
wire [48:0] mulAddResult = {1'h0, _mulAddResult_T} + {1'h0, _mulAddRecFNToRaw_preMul_io_mulAddC}; // @[FPU.scala:654:41, :663:45, :664:50]
wire valid_stage0_pipe_out_valid; // @[Valid.scala:135:21]
wire valid_stage0; // @[FPU.scala:667:28]
wire [2:0] roundingMode_stage0_pipe_out_bits; // @[Valid.scala:135:21]
wire [2:0] roundingMode_stage0; // @[FPU.scala:668:35]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v; // @[Valid.scala:141:24]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_valid = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v; // @[Valid.scala:135:21, :141:24]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isSigNaNAny; // @[Valid.scala:142:26]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isSigNaNAny = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isSigNaNAny; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNAOrB; // @[Valid.scala:142:26]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isNaNAOrB = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNAOrB; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfA; // @[Valid.scala:142:26]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfA = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfA; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroA; // @[Valid.scala:142:26]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroA = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroA; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfB; // @[Valid.scala:142:26]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfB = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfB; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroB; // @[Valid.scala:142:26]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroB = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroB; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_signProd; // @[Valid.scala:142:26]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_signProd = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_signProd; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNC; // @[Valid.scala:142:26]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isNaNC = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNC; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfC; // @[Valid.scala:142:26]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfC = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfC; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroC; // @[Valid.scala:142:26]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroC = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroC; // @[Valid.scala:135:21, :142:26]
reg [9:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_sExpSum; // @[Valid.scala:142:26]
wire [9:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_sExpSum = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_sExpSum; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_doSubMags; // @[Valid.scala:142:26]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_doSubMags = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_doSubMags; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CIsDominant; // @[Valid.scala:142:26]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_CIsDominant = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CIsDominant; // @[Valid.scala:135:21, :142:26]
reg [4:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CDom_CAlignDist; // @[Valid.scala:142:26]
wire [4:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_CDom_CAlignDist = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CDom_CAlignDist; // @[Valid.scala:135:21, :142:26]
reg [25:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_highAlignedSigC; // @[Valid.scala:142:26]
wire [25:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_highAlignedSigC = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_highAlignedSigC; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_bit0AlignedSigC; // @[Valid.scala:142:26]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_bit0AlignedSigC = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_bit0AlignedSigC; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v; // @[Valid.scala:141:24]
wire mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out_valid = mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v; // @[Valid.scala:135:21, :141:24]
reg [48:0] mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b; // @[Valid.scala:142:26]
wire [48:0] mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out_bits = mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v; // @[Valid.scala:141:24]
wire mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out_valid = mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v; // @[Valid.scala:135:21, :141:24]
reg [2:0] mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b; // @[Valid.scala:142:26]
wire [2:0] mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out_bits = mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b; // @[Valid.scala:135:21, :142:26]
reg roundingMode_stage0_pipe_v; // @[Valid.scala:141:24]
wire roundingMode_stage0_pipe_out_valid = roundingMode_stage0_pipe_v; // @[Valid.scala:135:21, :141:24]
reg [2:0] roundingMode_stage0_pipe_b; // @[Valid.scala:142:26]
assign roundingMode_stage0_pipe_out_bits = roundingMode_stage0_pipe_b; // @[Valid.scala:135:21, :142:26]
assign roundingMode_stage0 = roundingMode_stage0_pipe_out_bits; // @[Valid.scala:135:21]
reg detectTininess_stage0_pipe_v; // @[Valid.scala:141:24]
wire detectTininess_stage0_pipe_out_valid = detectTininess_stage0_pipe_v; // @[Valid.scala:135:21, :141:24]
reg valid_stage0_pipe_v; // @[Valid.scala:141:24]
assign valid_stage0_pipe_out_valid = valid_stage0_pipe_v; // @[Valid.scala:135:21, :141:24]
assign valid_stage0 = valid_stage0_pipe_out_valid; // @[Valid.scala:135:21]
reg roundRawFNToRecFN_io_invalidExc_pipe_v; // @[Valid.scala:141:24]
wire roundRawFNToRecFN_io_invalidExc_pipe_out_valid = roundRawFNToRecFN_io_invalidExc_pipe_v; // @[Valid.scala:135:21, :141:24]
reg roundRawFNToRecFN_io_invalidExc_pipe_b; // @[Valid.scala:142:26]
wire roundRawFNToRecFN_io_invalidExc_pipe_out_bits = roundRawFNToRecFN_io_invalidExc_pipe_b; // @[Valid.scala:135:21, :142:26]
reg roundRawFNToRecFN_io_in_pipe_v; // @[Valid.scala:141:24]
wire roundRawFNToRecFN_io_in_pipe_out_valid = roundRawFNToRecFN_io_in_pipe_v; // @[Valid.scala:135:21, :141:24]
reg roundRawFNToRecFN_io_in_pipe_b_isNaN; // @[Valid.scala:142:26]
wire roundRawFNToRecFN_io_in_pipe_out_bits_isNaN = roundRawFNToRecFN_io_in_pipe_b_isNaN; // @[Valid.scala:135:21, :142:26]
reg roundRawFNToRecFN_io_in_pipe_b_isInf; // @[Valid.scala:142:26]
wire roundRawFNToRecFN_io_in_pipe_out_bits_isInf = roundRawFNToRecFN_io_in_pipe_b_isInf; // @[Valid.scala:135:21, :142:26]
reg roundRawFNToRecFN_io_in_pipe_b_isZero; // @[Valid.scala:142:26]
wire roundRawFNToRecFN_io_in_pipe_out_bits_isZero = roundRawFNToRecFN_io_in_pipe_b_isZero; // @[Valid.scala:135:21, :142:26]
reg roundRawFNToRecFN_io_in_pipe_b_sign; // @[Valid.scala:142:26]
wire roundRawFNToRecFN_io_in_pipe_out_bits_sign = roundRawFNToRecFN_io_in_pipe_b_sign; // @[Valid.scala:135:21, :142:26]
reg [9:0] roundRawFNToRecFN_io_in_pipe_b_sExp; // @[Valid.scala:142:26]
wire [9:0] roundRawFNToRecFN_io_in_pipe_out_bits_sExp = roundRawFNToRecFN_io_in_pipe_b_sExp; // @[Valid.scala:135:21, :142:26]
reg [26:0] roundRawFNToRecFN_io_in_pipe_b_sig; // @[Valid.scala:142:26]
wire [26:0] roundRawFNToRecFN_io_in_pipe_out_bits_sig = roundRawFNToRecFN_io_in_pipe_b_sig; // @[Valid.scala:135:21, :142:26]
reg roundRawFNToRecFN_io_roundingMode_pipe_v; // @[Valid.scala:141:24]
wire roundRawFNToRecFN_io_roundingMode_pipe_out_valid = roundRawFNToRecFN_io_roundingMode_pipe_v; // @[Valid.scala:135:21, :141:24]
reg [2:0] roundRawFNToRecFN_io_roundingMode_pipe_b; // @[Valid.scala:142:26]
wire [2:0] roundRawFNToRecFN_io_roundingMode_pipe_out_bits = roundRawFNToRecFN_io_roundingMode_pipe_b; // @[Valid.scala:135:21, :142:26]
reg roundRawFNToRecFN_io_detectTininess_pipe_v; // @[Valid.scala:141:24]
wire roundRawFNToRecFN_io_detectTininess_pipe_out_valid = roundRawFNToRecFN_io_detectTininess_pipe_v; // @[Valid.scala:135:21, :141:24]
reg roundRawFNToRecFN_io_detectTininess_pipe_b; // @[Valid.scala:142:26]
wire roundRawFNToRecFN_io_detectTininess_pipe_out_bits = roundRawFNToRecFN_io_detectTininess_pipe_b; // @[Valid.scala:135:21, :142:26]
reg io_validout_pipe_v; // @[Valid.scala:141:24]
assign io_validout_pipe_out_valid = io_validout_pipe_v; // @[Valid.scala:135:21, :141:24]
assign io_validout_0 = io_validout_pipe_out_valid; // @[Valid.scala:135:21]
always @(posedge clock) begin // @[FPU.scala:633:7]
if (reset) begin // @[FPU.scala:633:7]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v <= 1'h0; // @[Valid.scala:141:24]
mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v <= 1'h0; // @[Valid.scala:141:24]
mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v <= 1'h0; // @[Valid.scala:141:24]
roundingMode_stage0_pipe_v <= 1'h0; // @[Valid.scala:141:24]
detectTininess_stage0_pipe_v <= 1'h0; // @[Valid.scala:141:24]
valid_stage0_pipe_v <= 1'h0; // @[Valid.scala:141:24]
roundRawFNToRecFN_io_invalidExc_pipe_v <= 1'h0; // @[Valid.scala:141:24]
roundRawFNToRecFN_io_in_pipe_v <= 1'h0; // @[Valid.scala:141:24]
roundRawFNToRecFN_io_roundingMode_pipe_v <= 1'h0; // @[Valid.scala:141:24]
roundRawFNToRecFN_io_detectTininess_pipe_v <= 1'h0; // @[Valid.scala:141:24]
io_validout_pipe_v <= 1'h0; // @[Valid.scala:141:24]
end
else begin // @[FPU.scala:633:7]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v <= io_validin_0; // @[Valid.scala:141:24]
mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v <= io_validin_0; // @[Valid.scala:141:24]
mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v <= io_validin_0; // @[Valid.scala:141:24]
roundingMode_stage0_pipe_v <= io_validin_0; // @[Valid.scala:141:24]
detectTininess_stage0_pipe_v <= io_validin_0; // @[Valid.scala:141:24]
valid_stage0_pipe_v <= io_validin_0; // @[Valid.scala:141:24]
roundRawFNToRecFN_io_invalidExc_pipe_v <= valid_stage0; // @[Valid.scala:141:24]
roundRawFNToRecFN_io_in_pipe_v <= valid_stage0; // @[Valid.scala:141:24]
roundRawFNToRecFN_io_roundingMode_pipe_v <= valid_stage0; // @[Valid.scala:141:24]
roundRawFNToRecFN_io_detectTininess_pipe_v <= valid_stage0; // @[Valid.scala:141:24]
io_validout_pipe_v <= valid_stage0; // @[Valid.scala:141:24]
end
if (io_validin_0) begin // @[FPU.scala:633:7]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isSigNaNAny <= _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNAOrB <= _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfA <= _mulAddRecFNToRaw_preMul_io_toPostMul_isInfA; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroA <= _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfB <= _mulAddRecFNToRaw_preMul_io_toPostMul_isInfB; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroB <= _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_signProd <= _mulAddRecFNToRaw_preMul_io_toPostMul_signProd; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNC <= _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfC <= _mulAddRecFNToRaw_preMul_io_toPostMul_isInfC; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroC <= _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_sExpSum <= _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_doSubMags <= _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CIsDominant <= _mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CDom_CAlignDist <= _mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_highAlignedSigC <= _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_bit0AlignedSigC <= _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b <= mulAddResult; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b <= io_roundingMode_0; // @[Valid.scala:142:26]
roundingMode_stage0_pipe_b <= io_roundingMode_0; // @[Valid.scala:142:26]
end
if (valid_stage0) begin // @[FPU.scala:667:28]
roundRawFNToRecFN_io_invalidExc_pipe_b <= _mulAddRecFNToRaw_postMul_io_invalidExc; // @[Valid.scala:142:26]
roundRawFNToRecFN_io_in_pipe_b_isNaN <= _mulAddRecFNToRaw_postMul_io_rawOut_isNaN; // @[Valid.scala:142:26]
roundRawFNToRecFN_io_in_pipe_b_isInf <= _mulAddRecFNToRaw_postMul_io_rawOut_isInf; // @[Valid.scala:142:26]
roundRawFNToRecFN_io_in_pipe_b_isZero <= _mulAddRecFNToRaw_postMul_io_rawOut_isZero; // @[Valid.scala:142:26]
roundRawFNToRecFN_io_in_pipe_b_sign <= _mulAddRecFNToRaw_postMul_io_rawOut_sign; // @[Valid.scala:142:26]
roundRawFNToRecFN_io_in_pipe_b_sExp <= _mulAddRecFNToRaw_postMul_io_rawOut_sExp; // @[Valid.scala:142:26]
roundRawFNToRecFN_io_in_pipe_b_sig <= _mulAddRecFNToRaw_postMul_io_rawOut_sig; // @[Valid.scala:142:26]
roundRawFNToRecFN_io_roundingMode_pipe_b <= roundingMode_stage0; // @[Valid.scala:142:26]
end
roundRawFNToRecFN_io_detectTininess_pipe_b <= valid_stage0 | roundRawFNToRecFN_io_detectTininess_pipe_b; // @[Valid.scala:142:26]
always @(posedge)
MulAddRecFNToRaw_preMul_e8_s24_1 mulAddRecFNToRaw_preMul ( // @[FPU.scala:654:41]
.io_op (io_op_0), // @[FPU.scala:633:7]
.io_a (io_a_0), // @[FPU.scala:633:7]
.io_b (io_b_0), // @[FPU.scala:633:7]
.io_c (io_c_0), // @[FPU.scala:633:7]
.io_mulAddA (_mulAddRecFNToRaw_preMul_io_mulAddA),
.io_mulAddB (_mulAddRecFNToRaw_preMul_io_mulAddB),
.io_mulAddC (_mulAddRecFNToRaw_preMul_io_mulAddC),
.io_toPostMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny),
.io_toPostMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB),
.io_toPostMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA),
.io_toPostMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA),
.io_toPostMul_isInfB (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfB),
.io_toPostMul_isZeroB (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB),
.io_toPostMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd),
.io_toPostMul_isNaNC (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC),
.io_toPostMul_isInfC (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfC),
.io_toPostMul_isZeroC (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC),
.io_toPostMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum),
.io_toPostMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags),
.io_toPostMul_CIsDominant (_mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant),
.io_toPostMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist),
.io_toPostMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC),
.io_toPostMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC)
); // @[FPU.scala:654:41]
MulAddRecFNToRaw_postMul_e8_s24_1 mulAddRecFNToRaw_postMul ( // @[FPU.scala:655:42]
.io_fromPreMul_isSigNaNAny (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isSigNaNAny), // @[Valid.scala:135:21]
.io_fromPreMul_isNaNAOrB (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isNaNAOrB), // @[Valid.scala:135:21]
.io_fromPreMul_isInfA (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfA), // @[Valid.scala:135:21]
.io_fromPreMul_isZeroA (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroA), // @[Valid.scala:135:21]
.io_fromPreMul_isInfB (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfB), // @[Valid.scala:135:21]
.io_fromPreMul_isZeroB (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroB), // @[Valid.scala:135:21]
.io_fromPreMul_signProd (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_signProd), // @[Valid.scala:135:21]
.io_fromPreMul_isNaNC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isNaNC), // @[Valid.scala:135:21]
.io_fromPreMul_isInfC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfC), // @[Valid.scala:135:21]
.io_fromPreMul_isZeroC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroC), // @[Valid.scala:135:21]
.io_fromPreMul_sExpSum (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_sExpSum), // @[Valid.scala:135:21]
.io_fromPreMul_doSubMags (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_doSubMags), // @[Valid.scala:135:21]
.io_fromPreMul_CIsDominant (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_CIsDominant), // @[Valid.scala:135:21]
.io_fromPreMul_CDom_CAlignDist (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_CDom_CAlignDist), // @[Valid.scala:135:21]
.io_fromPreMul_highAlignedSigC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_highAlignedSigC), // @[Valid.scala:135:21]
.io_fromPreMul_bit0AlignedSigC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_bit0AlignedSigC), // @[Valid.scala:135:21]
.io_mulAddResult (mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out_bits), // @[Valid.scala:135:21]
.io_roundingMode (mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out_bits), // @[Valid.scala:135:21]
.io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc),
.io_rawOut_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN),
.io_rawOut_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf),
.io_rawOut_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero),
.io_rawOut_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign),
.io_rawOut_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp),
.io_rawOut_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig)
); // @[FPU.scala:655:42]
RoundRawFNToRecFN_e8_s24_1 roundRawFNToRecFN ( // @[FPU.scala:682:35]
.io_invalidExc (roundRawFNToRecFN_io_invalidExc_pipe_out_bits), // @[Valid.scala:135:21]
.io_in_isNaN (roundRawFNToRecFN_io_in_pipe_out_bits_isNaN), // @[Valid.scala:135:21]
.io_in_isInf (roundRawFNToRecFN_io_in_pipe_out_bits_isInf), // @[Valid.scala:135:21]
.io_in_isZero (roundRawFNToRecFN_io_in_pipe_out_bits_isZero), // @[Valid.scala:135:21]
.io_in_sign (roundRawFNToRecFN_io_in_pipe_out_bits_sign), // @[Valid.scala:135:21]
.io_in_sExp (roundRawFNToRecFN_io_in_pipe_out_bits_sExp), // @[Valid.scala:135:21]
.io_in_sig (roundRawFNToRecFN_io_in_pipe_out_bits_sig), // @[Valid.scala:135:21]
.io_roundingMode (roundRawFNToRecFN_io_roundingMode_pipe_out_bits), // @[Valid.scala:135:21]
.io_detectTininess (roundRawFNToRecFN_io_detectTininess_pipe_out_bits), // @[Valid.scala:135:21]
.io_out (io_out_0),
.io_exceptionFlags (io_exceptionFlags_0)
); // @[FPU.scala:682:35]
assign io_out = io_out_0; // @[FPU.scala:633:7]
assign io_exceptionFlags = io_exceptionFlags_0; // @[FPU.scala:633:7]
assign io_validout = io_validout_0; // @[FPU.scala:633:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File MSHR.scala:
/*
* Copyright 2019 SiFive, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You should have received a copy of LICENSE.Apache2 along with
* this software. If not, you may obtain a copy at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package sifive.blocks.inclusivecache
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import freechips.rocketchip.tilelink._
import TLPermissions._
import TLMessages._
import MetaData._
import chisel3.PrintableHelper
import chisel3.experimental.dataview._
class ScheduleRequest(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params)
{
val a = Valid(new SourceARequest(params))
val b = Valid(new SourceBRequest(params))
val c = Valid(new SourceCRequest(params))
val d = Valid(new SourceDRequest(params))
val e = Valid(new SourceERequest(params))
val x = Valid(new SourceXRequest(params))
val dir = Valid(new DirectoryWrite(params))
val reload = Bool() // get next request via allocate (if any)
}
class MSHRStatus(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params)
{
val set = UInt(params.setBits.W)
val tag = UInt(params.tagBits.W)
val way = UInt(params.wayBits.W)
val blockB = Bool()
val nestB = Bool()
val blockC = Bool()
val nestC = Bool()
}
class NestedWriteback(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params)
{
val set = UInt(params.setBits.W)
val tag = UInt(params.tagBits.W)
val b_toN = Bool() // nested Probes may unhit us
val b_toB = Bool() // nested Probes may demote us
val b_clr_dirty = Bool() // nested Probes clear dirty
val c_set_dirty = Bool() // nested Releases MAY set dirty
}
sealed trait CacheState
{
val code = CacheState.index.U
CacheState.index = CacheState.index + 1
}
object CacheState
{
var index = 0
}
case object S_INVALID extends CacheState
case object S_BRANCH extends CacheState
case object S_BRANCH_C extends CacheState
case object S_TIP extends CacheState
case object S_TIP_C extends CacheState
case object S_TIP_CD extends CacheState
case object S_TIP_D extends CacheState
case object S_TRUNK_C extends CacheState
case object S_TRUNK_CD extends CacheState
class MSHR(params: InclusiveCacheParameters) extends Module
{
val io = IO(new Bundle {
val allocate = Flipped(Valid(new AllocateRequest(params))) // refills MSHR for next cycle
val directory = Flipped(Valid(new DirectoryResult(params))) // triggers schedule setup
val status = Valid(new MSHRStatus(params))
val schedule = Decoupled(new ScheduleRequest(params))
val sinkc = Flipped(Valid(new SinkCResponse(params)))
val sinkd = Flipped(Valid(new SinkDResponse(params)))
val sinke = Flipped(Valid(new SinkEResponse(params)))
val nestedwb = Flipped(new NestedWriteback(params))
})
val request_valid = RegInit(false.B)
val request = Reg(new FullRequest(params))
val meta_valid = RegInit(false.B)
val meta = Reg(new DirectoryResult(params))
// Define which states are valid
when (meta_valid) {
when (meta.state === INVALID) {
assert (!meta.clients.orR)
assert (!meta.dirty)
}
when (meta.state === BRANCH) {
assert (!meta.dirty)
}
when (meta.state === TRUNK) {
assert (meta.clients.orR)
assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one
}
when (meta.state === TIP) {
// noop
}
}
// Completed transitions (s_ = scheduled), (w_ = waiting)
val s_rprobe = RegInit(true.B) // B
val w_rprobeackfirst = RegInit(true.B)
val w_rprobeacklast = RegInit(true.B)
val s_release = RegInit(true.B) // CW w_rprobeackfirst
val w_releaseack = RegInit(true.B)
val s_pprobe = RegInit(true.B) // B
val s_acquire = RegInit(true.B) // A s_release, s_pprobe [1]
val s_flush = RegInit(true.B) // X w_releaseack
val w_grantfirst = RegInit(true.B)
val w_grantlast = RegInit(true.B)
val w_grant = RegInit(true.B) // first | last depending on wormhole
val w_pprobeackfirst = RegInit(true.B)
val w_pprobeacklast = RegInit(true.B)
val w_pprobeack = RegInit(true.B) // first | last depending on wormhole
val s_probeack = RegInit(true.B) // C w_pprobeackfirst (mutually exclusive with next two s_*)
val s_grantack = RegInit(true.B) // E w_grantfirst ... CAN require both outE&inD to service outD
val s_execute = RegInit(true.B) // D w_pprobeack, w_grant
val w_grantack = RegInit(true.B)
val s_writeback = RegInit(true.B) // W w_*
// [1]: We cannot issue outer Acquire while holding blockB (=> outA can stall)
// However, inB and outC are higher priority than outB, so s_release and s_pprobe
// may be safely issued while blockB. Thus we must NOT try to schedule the
// potentially stuck s_acquire with either of them (scheduler is all or none).
// Meta-data that we discover underway
val sink = Reg(UInt(params.outer.bundle.sinkBits.W))
val gotT = Reg(Bool())
val bad_grant = Reg(Bool())
val probes_done = Reg(UInt(params.clientBits.W))
val probes_toN = Reg(UInt(params.clientBits.W))
val probes_noT = Reg(Bool())
// When a nested transaction completes, update our meta data
when (meta_valid && meta.state =/= INVALID &&
io.nestedwb.set === request.set && io.nestedwb.tag === meta.tag) {
when (io.nestedwb.b_clr_dirty) { meta.dirty := false.B }
when (io.nestedwb.c_set_dirty) { meta.dirty := true.B }
when (io.nestedwb.b_toB) { meta.state := BRANCH }
when (io.nestedwb.b_toN) { meta.hit := false.B }
}
// Scheduler status
io.status.valid := request_valid
io.status.bits.set := request.set
io.status.bits.tag := request.tag
io.status.bits.way := meta.way
io.status.bits.blockB := !meta_valid || ((!w_releaseack || !w_rprobeacklast || !w_pprobeacklast) && !w_grantfirst)
io.status.bits.nestB := meta_valid && w_releaseack && w_rprobeacklast && w_pprobeacklast && !w_grantfirst
// The above rules ensure we will block and not nest an outer probe while still doing our
// own inner probes. Thus every probe wakes exactly one MSHR.
io.status.bits.blockC := !meta_valid
io.status.bits.nestC := meta_valid && (!w_rprobeackfirst || !w_pprobeackfirst || !w_grantfirst)
// The w_grantfirst in nestC is necessary to deal with:
// acquire waiting for grant, inner release gets queued, outer probe -> inner probe -> deadlock
// ... this is possible because the release+probe can be for same set, but different tag
// We can only demand: block, nest, or queue
assert (!io.status.bits.nestB || !io.status.bits.blockB)
assert (!io.status.bits.nestC || !io.status.bits.blockC)
// Scheduler requests
val no_wait = w_rprobeacklast && w_releaseack && w_grantlast && w_pprobeacklast && w_grantack
io.schedule.bits.a.valid := !s_acquire && s_release && s_pprobe
io.schedule.bits.b.valid := !s_rprobe || !s_pprobe
io.schedule.bits.c.valid := (!s_release && w_rprobeackfirst) || (!s_probeack && w_pprobeackfirst)
io.schedule.bits.d.valid := !s_execute && w_pprobeack && w_grant
io.schedule.bits.e.valid := !s_grantack && w_grantfirst
io.schedule.bits.x.valid := !s_flush && w_releaseack
io.schedule.bits.dir.valid := (!s_release && w_rprobeackfirst) || (!s_writeback && no_wait)
io.schedule.bits.reload := no_wait
io.schedule.valid := io.schedule.bits.a.valid || io.schedule.bits.b.valid || io.schedule.bits.c.valid ||
io.schedule.bits.d.valid || io.schedule.bits.e.valid || io.schedule.bits.x.valid ||
io.schedule.bits.dir.valid
// Schedule completions
when (io.schedule.ready) {
s_rprobe := true.B
when (w_rprobeackfirst) { s_release := true.B }
s_pprobe := true.B
when (s_release && s_pprobe) { s_acquire := true.B }
when (w_releaseack) { s_flush := true.B }
when (w_pprobeackfirst) { s_probeack := true.B }
when (w_grantfirst) { s_grantack := true.B }
when (w_pprobeack && w_grant) { s_execute := true.B }
when (no_wait) { s_writeback := true.B }
// Await the next operation
when (no_wait) {
request_valid := false.B
meta_valid := false.B
}
}
// Resulting meta-data
val final_meta_writeback = WireInit(meta)
val req_clientBit = params.clientBit(request.source)
val req_needT = needT(request.opcode, request.param)
val req_acquire = request.opcode === AcquireBlock || request.opcode === AcquirePerm
val meta_no_clients = !meta.clients.orR
val req_promoteT = req_acquire && Mux(meta.hit, meta_no_clients && meta.state === TIP, gotT)
when (request.prio(2) && (!params.firstLevel).B) { // always a hit
final_meta_writeback.dirty := meta.dirty || request.opcode(0)
final_meta_writeback.state := Mux(request.param =/= TtoT && meta.state === TRUNK, TIP, meta.state)
final_meta_writeback.clients := meta.clients & ~Mux(isToN(request.param), req_clientBit, 0.U)
final_meta_writeback.hit := true.B // chained requests are hits
} .elsewhen (request.control && params.control.B) { // request.prio(0)
when (meta.hit) {
final_meta_writeback.dirty := false.B
final_meta_writeback.state := INVALID
final_meta_writeback.clients := meta.clients & ~probes_toN
}
final_meta_writeback.hit := false.B
} .otherwise {
final_meta_writeback.dirty := (meta.hit && meta.dirty) || !request.opcode(2)
final_meta_writeback.state := Mux(req_needT,
Mux(req_acquire, TRUNK, TIP),
Mux(!meta.hit, Mux(gotT, Mux(req_acquire, TRUNK, TIP), BRANCH),
MuxLookup(meta.state, 0.U(2.W))(Seq(
INVALID -> BRANCH,
BRANCH -> BRANCH,
TRUNK -> TIP,
TIP -> Mux(meta_no_clients && req_acquire, TRUNK, TIP)))))
final_meta_writeback.clients := Mux(meta.hit, meta.clients & ~probes_toN, 0.U) |
Mux(req_acquire, req_clientBit, 0.U)
final_meta_writeback.tag := request.tag
final_meta_writeback.hit := true.B
}
when (bad_grant) {
when (meta.hit) {
// upgrade failed (B -> T)
assert (!meta_valid || meta.state === BRANCH)
final_meta_writeback.hit := true.B
final_meta_writeback.dirty := false.B
final_meta_writeback.state := BRANCH
final_meta_writeback.clients := meta.clients & ~probes_toN
} .otherwise {
// failed N -> (T or B)
final_meta_writeback.hit := false.B
final_meta_writeback.dirty := false.B
final_meta_writeback.state := INVALID
final_meta_writeback.clients := 0.U
}
}
val invalid = Wire(new DirectoryEntry(params))
invalid.dirty := false.B
invalid.state := INVALID
invalid.clients := 0.U
invalid.tag := 0.U
// Just because a client says BtoT, by the time we process the request he may be N.
// Therefore, we must consult our own meta-data state to confirm he owns the line still.
val honour_BtoT = meta.hit && (meta.clients & req_clientBit).orR
// The client asking us to act is proof they don't have permissions.
val excluded_client = Mux(meta.hit && request.prio(0) && skipProbeN(request.opcode, params.cache.hintsSkipProbe), req_clientBit, 0.U)
io.schedule.bits.a.bits.tag := request.tag
io.schedule.bits.a.bits.set := request.set
io.schedule.bits.a.bits.param := Mux(req_needT, Mux(meta.hit, BtoT, NtoT), NtoB)
io.schedule.bits.a.bits.block := request.size =/= log2Ceil(params.cache.blockBytes).U ||
!(request.opcode === PutFullData || request.opcode === AcquirePerm)
io.schedule.bits.a.bits.source := 0.U
io.schedule.bits.b.bits.param := Mux(!s_rprobe, toN, Mux(request.prio(1), request.param, Mux(req_needT, toN, toB)))
io.schedule.bits.b.bits.tag := Mux(!s_rprobe, meta.tag, request.tag)
io.schedule.bits.b.bits.set := request.set
io.schedule.bits.b.bits.clients := meta.clients & ~excluded_client
io.schedule.bits.c.bits.opcode := Mux(meta.dirty, ReleaseData, Release)
io.schedule.bits.c.bits.param := Mux(meta.state === BRANCH, BtoN, TtoN)
io.schedule.bits.c.bits.source := 0.U
io.schedule.bits.c.bits.tag := meta.tag
io.schedule.bits.c.bits.set := request.set
io.schedule.bits.c.bits.way := meta.way
io.schedule.bits.c.bits.dirty := meta.dirty
io.schedule.bits.d.bits.viewAsSupertype(chiselTypeOf(request)) := request
io.schedule.bits.d.bits.param := Mux(!req_acquire, request.param,
MuxLookup(request.param, request.param)(Seq(
NtoB -> Mux(req_promoteT, NtoT, NtoB),
BtoT -> Mux(honour_BtoT, BtoT, NtoT),
NtoT -> NtoT)))
io.schedule.bits.d.bits.sink := 0.U
io.schedule.bits.d.bits.way := meta.way
io.schedule.bits.d.bits.bad := bad_grant
io.schedule.bits.e.bits.sink := sink
io.schedule.bits.x.bits.fail := false.B
io.schedule.bits.dir.bits.set := request.set
io.schedule.bits.dir.bits.way := meta.way
io.schedule.bits.dir.bits.data := Mux(!s_release, invalid, WireInit(new DirectoryEntry(params), init = final_meta_writeback))
// Coverage of state transitions
def cacheState(entry: DirectoryEntry, hit: Bool) = {
val out = WireDefault(0.U)
val c = entry.clients.orR
val d = entry.dirty
switch (entry.state) {
is (BRANCH) { out := Mux(c, S_BRANCH_C.code, S_BRANCH.code) }
is (TRUNK) { out := Mux(d, S_TRUNK_CD.code, S_TRUNK_C.code) }
is (TIP) { out := Mux(c, Mux(d, S_TIP_CD.code, S_TIP_C.code), Mux(d, S_TIP_D.code, S_TIP.code)) }
is (INVALID) { out := S_INVALID.code }
}
when (!hit) { out := S_INVALID.code }
out
}
val p = !params.lastLevel // can be probed
val c = !params.firstLevel // can be acquired
val m = params.inner.client.clients.exists(!_.supports.probe) // can be written (or read)
val r = params.outer.manager.managers.exists(!_.alwaysGrantsT) // read-only devices exist
val f = params.control // flush control register exists
val cfg = (p, c, m, r, f)
val b = r || p // can reach branch state (via probe downgrade or read-only device)
// The cache must be used for something or we would not be here
require(c || m)
val evict = cacheState(meta, !meta.hit)
val before = cacheState(meta, meta.hit)
val after = cacheState(final_meta_writeback, true.B)
def eviction(from: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) {
if (cover) {
params.ccover(evict === from.code, s"MSHR_${from}_EVICT", s"State transition from ${from} to evicted ${cfg}")
} else {
assert(!(evict === from.code), cf"State transition from ${from} to evicted should be impossible ${cfg}")
}
if (cover && f) {
params.ccover(before === from.code, s"MSHR_${from}_FLUSH", s"State transition from ${from} to flushed ${cfg}")
} else {
assert(!(before === from.code), cf"State transition from ${from} to flushed should be impossible ${cfg}")
}
}
def transition(from: CacheState, to: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) {
if (cover) {
params.ccover(before === from.code && after === to.code, s"MSHR_${from}_${to}", s"State transition from ${from} to ${to} ${cfg}")
} else {
assert(!(before === from.code && after === to.code), cf"State transition from ${from} to ${to} should be impossible ${cfg}")
}
}
when ((!s_release && w_rprobeackfirst) && io.schedule.ready) {
eviction(S_BRANCH, b) // MMIO read to read-only device
eviction(S_BRANCH_C, b && c) // you need children to become C
eviction(S_TIP, true) // MMIO read || clean release can lead to this state
eviction(S_TIP_C, c) // needs two clients || client + mmio || downgrading client
eviction(S_TIP_CD, c) // needs two clients || client + mmio || downgrading client
eviction(S_TIP_D, true) // MMIO write || dirty release lead here
eviction(S_TRUNK_C, c) // acquire for write
eviction(S_TRUNK_CD, c) // dirty release then reacquire
}
when ((!s_writeback && no_wait) && io.schedule.ready) {
transition(S_INVALID, S_BRANCH, b && m) // only MMIO can bring us to BRANCH state
transition(S_INVALID, S_BRANCH_C, b && c) // C state is only possible if there are inner caches
transition(S_INVALID, S_TIP, m) // MMIO read
transition(S_INVALID, S_TIP_C, false) // we would go S_TRUNK_C instead
transition(S_INVALID, S_TIP_CD, false) // acquire does not cause dirty immediately
transition(S_INVALID, S_TIP_D, m) // MMIO write
transition(S_INVALID, S_TRUNK_C, c) // acquire
transition(S_INVALID, S_TRUNK_CD, false) // acquire does not cause dirty immediately
transition(S_BRANCH, S_INVALID, b && p) // probe can do this (flushes run as evictions)
transition(S_BRANCH, S_BRANCH_C, b && c) // acquire
transition(S_BRANCH, S_TIP, b && m) // prefetch write
transition(S_BRANCH, S_TIP_C, false) // we would go S_TRUNK_C instead
transition(S_BRANCH, S_TIP_CD, false) // acquire does not cause dirty immediately
transition(S_BRANCH, S_TIP_D, b && m) // MMIO write
transition(S_BRANCH, S_TRUNK_C, b && c) // acquire
transition(S_BRANCH, S_TRUNK_CD, false) // acquire does not cause dirty immediately
transition(S_BRANCH_C, S_INVALID, b && c && p)
transition(S_BRANCH_C, S_BRANCH, b && c) // clean release (optional)
transition(S_BRANCH_C, S_TIP, b && c && m) // prefetch write
transition(S_BRANCH_C, S_TIP_C, false) // we would go S_TRUNK_C instead
transition(S_BRANCH_C, S_TIP_D, b && c && m) // MMIO write
transition(S_BRANCH_C, S_TIP_CD, false) // going dirty means we must shoot down clients
transition(S_BRANCH_C, S_TRUNK_C, b && c) // acquire
transition(S_BRANCH_C, S_TRUNK_CD, false) // acquire does not cause dirty immediately
transition(S_TIP, S_INVALID, p)
transition(S_TIP, S_BRANCH, p) // losing TIP only possible via probe
transition(S_TIP, S_BRANCH_C, false) // we would go S_TRUNK_C instead
transition(S_TIP, S_TIP_C, false) // we would go S_TRUNK_C instead
transition(S_TIP, S_TIP_D, m) // direct dirty only via MMIO write
transition(S_TIP, S_TIP_CD, false) // acquire does not make us dirty immediately
transition(S_TIP, S_TRUNK_C, c) // acquire
transition(S_TIP, S_TRUNK_CD, false) // acquire does not make us dirty immediately
transition(S_TIP_C, S_INVALID, c && p)
transition(S_TIP_C, S_BRANCH, c && p) // losing TIP only possible via probe
transition(S_TIP_C, S_BRANCH_C, c && p) // losing TIP only possible via probe
transition(S_TIP_C, S_TIP, c) // probed while MMIO read || clean release (optional)
transition(S_TIP_C, S_TIP_D, c && m) // direct dirty only via MMIO write
transition(S_TIP_C, S_TIP_CD, false) // going dirty means we must shoot down clients
transition(S_TIP_C, S_TRUNK_C, c) // acquire
transition(S_TIP_C, S_TRUNK_CD, false) // acquire does not make us immediately dirty
transition(S_TIP_D, S_INVALID, p)
transition(S_TIP_D, S_BRANCH, p) // losing D is only possible via probe
transition(S_TIP_D, S_BRANCH_C, p && c) // probed while acquire shared
transition(S_TIP_D, S_TIP, p) // probed while MMIO read || outer probe.toT (optional)
transition(S_TIP_D, S_TIP_C, false) // we would go S_TRUNK_C instead
transition(S_TIP_D, S_TIP_CD, false) // we would go S_TRUNK_CD instead
transition(S_TIP_D, S_TRUNK_C, p && c) // probed while acquired
transition(S_TIP_D, S_TRUNK_CD, c) // acquire
transition(S_TIP_CD, S_INVALID, c && p)
transition(S_TIP_CD, S_BRANCH, c && p) // losing D is only possible via probe
transition(S_TIP_CD, S_BRANCH_C, c && p) // losing D is only possible via probe
transition(S_TIP_CD, S_TIP, c && p) // probed while MMIO read || outer probe.toT (optional)
transition(S_TIP_CD, S_TIP_C, false) // we would go S_TRUNK_C instead
transition(S_TIP_CD, S_TIP_D, c) // MMIO write || clean release (optional)
transition(S_TIP_CD, S_TRUNK_C, c && p) // probed while acquire
transition(S_TIP_CD, S_TRUNK_CD, c) // acquire
transition(S_TRUNK_C, S_INVALID, c && p)
transition(S_TRUNK_C, S_BRANCH, c && p) // losing TIP only possible via probe
transition(S_TRUNK_C, S_BRANCH_C, c && p) // losing TIP only possible via probe
transition(S_TRUNK_C, S_TIP, c) // MMIO read || clean release (optional)
transition(S_TRUNK_C, S_TIP_C, c) // bounce shared
transition(S_TRUNK_C, S_TIP_D, c) // dirty release
transition(S_TRUNK_C, S_TIP_CD, c) // dirty bounce shared
transition(S_TRUNK_C, S_TRUNK_CD, c) // dirty bounce
transition(S_TRUNK_CD, S_INVALID, c && p)
transition(S_TRUNK_CD, S_BRANCH, c && p) // losing D only possible via probe
transition(S_TRUNK_CD, S_BRANCH_C, c && p) // losing D only possible via probe
transition(S_TRUNK_CD, S_TIP, c && p) // probed while MMIO read || outer probe.toT (optional)
transition(S_TRUNK_CD, S_TIP_C, false) // we would go S_TRUNK_C instead
transition(S_TRUNK_CD, S_TIP_D, c) // dirty release
transition(S_TRUNK_CD, S_TIP_CD, c) // bounce shared
transition(S_TRUNK_CD, S_TRUNK_C, c && p) // probed while acquire
}
// Handle response messages
val probe_bit = params.clientBit(io.sinkc.bits.source)
val last_probe = (probes_done | probe_bit) === (meta.clients & ~excluded_client)
val probe_toN = isToN(io.sinkc.bits.param)
if (!params.firstLevel) when (io.sinkc.valid) {
params.ccover( probe_toN && io.schedule.bits.b.bits.param === toB, "MSHR_PROBE_FULL", "Client downgraded to N when asked only to do B")
params.ccover(!probe_toN && io.schedule.bits.b.bits.param === toB, "MSHR_PROBE_HALF", "Client downgraded to B when asked only to do B")
// Caution: the probe matches us only in set.
// We would never allow an outer probe to nest until both w_[rp]probeack complete, so
// it is safe to just unguardedly update the probe FSM.
probes_done := probes_done | probe_bit
probes_toN := probes_toN | Mux(probe_toN, probe_bit, 0.U)
probes_noT := probes_noT || io.sinkc.bits.param =/= TtoT
w_rprobeackfirst := w_rprobeackfirst || last_probe
w_rprobeacklast := w_rprobeacklast || (last_probe && io.sinkc.bits.last)
w_pprobeackfirst := w_pprobeackfirst || last_probe
w_pprobeacklast := w_pprobeacklast || (last_probe && io.sinkc.bits.last)
// Allow wormhole routing from sinkC if the first request beat has offset 0
val set_pprobeack = last_probe && (io.sinkc.bits.last || request.offset === 0.U)
w_pprobeack := w_pprobeack || set_pprobeack
params.ccover(!set_pprobeack && w_rprobeackfirst, "MSHR_PROBE_SERIAL", "Sequential routing of probe response data")
params.ccover( set_pprobeack && w_rprobeackfirst, "MSHR_PROBE_WORMHOLE", "Wormhole routing of probe response data")
// However, meta-data updates need to be done more cautiously
when (meta.state =/= INVALID && io.sinkc.bits.tag === meta.tag && io.sinkc.bits.data) { meta.dirty := true.B } // !!!
}
when (io.sinkd.valid) {
when (io.sinkd.bits.opcode === Grant || io.sinkd.bits.opcode === GrantData) {
sink := io.sinkd.bits.sink
w_grantfirst := true.B
w_grantlast := io.sinkd.bits.last
// Record if we need to prevent taking ownership
bad_grant := io.sinkd.bits.denied
// Allow wormhole routing for requests whose first beat has offset 0
w_grant := request.offset === 0.U || io.sinkd.bits.last
params.ccover(io.sinkd.bits.opcode === GrantData && request.offset === 0.U, "MSHR_GRANT_WORMHOLE", "Wormhole routing of grant response data")
params.ccover(io.sinkd.bits.opcode === GrantData && request.offset =/= 0.U, "MSHR_GRANT_SERIAL", "Sequential routing of grant response data")
gotT := io.sinkd.bits.param === toT
}
.elsewhen (io.sinkd.bits.opcode === ReleaseAck) {
w_releaseack := true.B
}
}
when (io.sinke.valid) {
w_grantack := true.B
}
// Bootstrap new requests
val allocate_as_full = WireInit(new FullRequest(params), init = io.allocate.bits)
val new_meta = Mux(io.allocate.valid && io.allocate.bits.repeat, final_meta_writeback, io.directory.bits)
val new_request = Mux(io.allocate.valid, allocate_as_full, request)
val new_needT = needT(new_request.opcode, new_request.param)
val new_clientBit = params.clientBit(new_request.source)
val new_skipProbe = Mux(skipProbeN(new_request.opcode, params.cache.hintsSkipProbe), new_clientBit, 0.U)
val prior = cacheState(final_meta_writeback, true.B)
def bypass(from: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) {
if (cover) {
params.ccover(prior === from.code, s"MSHR_${from}_BYPASS", s"State bypass transition from ${from} ${cfg}")
} else {
assert(!(prior === from.code), cf"State bypass from ${from} should be impossible ${cfg}")
}
}
when (io.allocate.valid && io.allocate.bits.repeat) {
bypass(S_INVALID, f || p) // Can lose permissions (probe/flush)
bypass(S_BRANCH, b) // MMIO read to read-only device
bypass(S_BRANCH_C, b && c) // you need children to become C
bypass(S_TIP, true) // MMIO read || clean release can lead to this state
bypass(S_TIP_C, c) // needs two clients || client + mmio || downgrading client
bypass(S_TIP_CD, c) // needs two clients || client + mmio || downgrading client
bypass(S_TIP_D, true) // MMIO write || dirty release lead here
bypass(S_TRUNK_C, c) // acquire for write
bypass(S_TRUNK_CD, c) // dirty release then reacquire
}
when (io.allocate.valid) {
assert (!request_valid || (no_wait && io.schedule.fire))
request_valid := true.B
request := io.allocate.bits
}
// Create execution plan
when (io.directory.valid || (io.allocate.valid && io.allocate.bits.repeat)) {
meta_valid := true.B
meta := new_meta
probes_done := 0.U
probes_toN := 0.U
probes_noT := false.B
gotT := false.B
bad_grant := false.B
// These should already be either true or turning true
// We clear them here explicitly to simplify the mux tree
s_rprobe := true.B
w_rprobeackfirst := true.B
w_rprobeacklast := true.B
s_release := true.B
w_releaseack := true.B
s_pprobe := true.B
s_acquire := true.B
s_flush := true.B
w_grantfirst := true.B
w_grantlast := true.B
w_grant := true.B
w_pprobeackfirst := true.B
w_pprobeacklast := true.B
w_pprobeack := true.B
s_probeack := true.B
s_grantack := true.B
s_execute := true.B
w_grantack := true.B
s_writeback := true.B
// For C channel requests (ie: Release[Data])
when (new_request.prio(2) && (!params.firstLevel).B) {
s_execute := false.B
// Do we need to go dirty?
when (new_request.opcode(0) && !new_meta.dirty) {
s_writeback := false.B
}
// Does our state change?
when (isToB(new_request.param) && new_meta.state === TRUNK) {
s_writeback := false.B
}
// Do our clients change?
when (isToN(new_request.param) && (new_meta.clients & new_clientBit) =/= 0.U) {
s_writeback := false.B
}
assert (new_meta.hit)
}
// For X channel requests (ie: flush)
.elsewhen (new_request.control && params.control.B) { // new_request.prio(0)
s_flush := false.B
// Do we need to actually do something?
when (new_meta.hit) {
s_release := false.B
w_releaseack := false.B
// Do we need to shoot-down inner caches?
when ((!params.firstLevel).B && (new_meta.clients =/= 0.U)) {
s_rprobe := false.B
w_rprobeackfirst := false.B
w_rprobeacklast := false.B
}
}
}
// For A channel requests
.otherwise { // new_request.prio(0) && !new_request.control
s_execute := false.B
// Do we need an eviction?
when (!new_meta.hit && new_meta.state =/= INVALID) {
s_release := false.B
w_releaseack := false.B
// Do we need to shoot-down inner caches?
when ((!params.firstLevel).B & (new_meta.clients =/= 0.U)) {
s_rprobe := false.B
w_rprobeackfirst := false.B
w_rprobeacklast := false.B
}
}
// Do we need an acquire?
when (!new_meta.hit || (new_meta.state === BRANCH && new_needT)) {
s_acquire := false.B
w_grantfirst := false.B
w_grantlast := false.B
w_grant := false.B
s_grantack := false.B
s_writeback := false.B
}
// Do we need a probe?
when ((!params.firstLevel).B && (new_meta.hit &&
(new_needT || new_meta.state === TRUNK) &&
(new_meta.clients & ~new_skipProbe) =/= 0.U)) {
s_pprobe := false.B
w_pprobeackfirst := false.B
w_pprobeacklast := false.B
w_pprobeack := false.B
s_writeback := false.B
}
// Do we need a grantack?
when (new_request.opcode === AcquireBlock || new_request.opcode === AcquirePerm) {
w_grantack := false.B
s_writeback := false.B
}
// Becomes dirty?
when (!new_request.opcode(2) && new_meta.hit && !new_meta.dirty) {
s_writeback := false.B
}
}
}
}
File Parameters.scala:
/*
* Copyright 2019 SiFive, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You should have received a copy of LICENSE.Apache2 along with
* this software. If not, you may obtain a copy at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package sifive.blocks.inclusivecache
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
import freechips.rocketchip.util.property.cover
import scala.math.{min,max}
case class CacheParameters(
level: Int,
ways: Int,
sets: Int,
blockBytes: Int,
beatBytes: Int, // inner
hintsSkipProbe: Boolean)
{
require (ways > 0)
require (sets > 0)
require (blockBytes > 0 && isPow2(blockBytes))
require (beatBytes > 0 && isPow2(beatBytes))
require (blockBytes >= beatBytes)
val blocks = ways * sets
val sizeBytes = blocks * blockBytes
val blockBeats = blockBytes/beatBytes
}
case class InclusiveCachePortParameters(
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)
{
def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new TLBuffer(a, b, c, d, e))
}
object InclusiveCachePortParameters
{
val none = InclusiveCachePortParameters(
a = BufferParams.none,
b = BufferParams.none,
c = BufferParams.none,
d = BufferParams.none,
e = BufferParams.none)
val full = InclusiveCachePortParameters(
a = BufferParams.default,
b = BufferParams.default,
c = BufferParams.default,
d = BufferParams.default,
e = BufferParams.default)
// This removes feed-through paths from C=>A and A=>C
val fullC = InclusiveCachePortParameters(
a = BufferParams.none,
b = BufferParams.none,
c = BufferParams.default,
d = BufferParams.none,
e = BufferParams.none)
val flowAD = InclusiveCachePortParameters(
a = BufferParams.flow,
b = BufferParams.none,
c = BufferParams.none,
d = BufferParams.flow,
e = BufferParams.none)
val flowAE = InclusiveCachePortParameters(
a = BufferParams.flow,
b = BufferParams.none,
c = BufferParams.none,
d = BufferParams.none,
e = BufferParams.flow)
// For innerBuf:
// SinkA: no restrictions, flows into scheduler+putbuffer
// SourceB: no restrictions, flows out of scheduler
// sinkC: no restrictions, flows into scheduler+putbuffer & buffered to bankedStore
// SourceD: no restrictions, flows out of bankedStore/regout
// SinkE: no restrictions, flows into scheduler
//
// ... so while none is possible, you probably want at least flowAC to cut ready
// from the scheduler delay and flowD to ease SourceD back-pressure
// For outerBufer:
// SourceA: must not be pipe, flows out of scheduler
// SinkB: no restrictions, flows into scheduler
// SourceC: pipe is useless, flows out of bankedStore/regout, parameter depth ignored
// SinkD: no restrictions, flows into scheduler & bankedStore
// SourceE: must not be pipe, flows out of scheduler
//
// ... AE take the channel ready into the scheduler, so you need at least flowAE
}
case class InclusiveCacheMicroParameters(
writeBytes: Int, // backing store update granularity
memCycles: Int = 40, // # of L2 clock cycles for a memory round-trip (50ns @ 800MHz)
portFactor: Int = 4, // numSubBanks = (widest TL port * portFactor) / writeBytes
dirReg: Boolean = false,
innerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.fullC, // or none
outerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.full) // or flowAE
{
require (writeBytes > 0 && isPow2(writeBytes))
require (memCycles > 0)
require (portFactor >= 2) // for inner RMW and concurrent outer Relase + Grant
}
case class InclusiveCacheControlParameters(
address: BigInt,
beatBytes: Int,
bankedControl: Boolean)
case class InclusiveCacheParameters(
cache: CacheParameters,
micro: InclusiveCacheMicroParameters,
control: Boolean,
inner: TLEdgeIn,
outer: TLEdgeOut)(implicit val p: Parameters)
{
require (cache.ways > 1)
require (cache.sets > 1 && isPow2(cache.sets))
require (micro.writeBytes <= inner.manager.beatBytes)
require (micro.writeBytes <= outer.manager.beatBytes)
require (inner.manager.beatBytes <= cache.blockBytes)
require (outer.manager.beatBytes <= cache.blockBytes)
// Require that all cached address ranges have contiguous blocks
outer.manager.managers.flatMap(_.address).foreach { a =>
require (a.alignment >= cache.blockBytes)
}
// If we are the first level cache, we do not need to support inner-BCE
val firstLevel = !inner.client.clients.exists(_.supports.probe)
// If we are the last level cache, we do not need to support outer-B
val lastLevel = !outer.manager.managers.exists(_.regionType > RegionType.UNCACHED)
require (lastLevel)
// Provision enough resources to achieve full throughput with missing single-beat accesses
val mshrs = InclusiveCacheParameters.all_mshrs(cache, micro)
val secondary = max(mshrs, micro.memCycles - mshrs)
val putLists = micro.memCycles // allow every request to be single beat
val putBeats = max(2*cache.blockBeats, micro.memCycles)
val relLists = 2
val relBeats = relLists*cache.blockBeats
val flatAddresses = AddressSet.unify(outer.manager.managers.flatMap(_.address))
val pickMask = AddressDecoder(flatAddresses.map(Seq(_)), flatAddresses.map(_.mask).reduce(_|_))
def bitOffsets(x: BigInt, offset: Int = 0, tail: List[Int] = List.empty[Int]): List[Int] =
if (x == 0) tail.reverse else bitOffsets(x >> 1, offset + 1, if ((x & 1) == 1) offset :: tail else tail)
val addressMapping = bitOffsets(pickMask)
val addressBits = addressMapping.size
// println(s"addresses: ${flatAddresses} => ${pickMask} => ${addressBits}")
val allClients = inner.client.clients.size
val clientBitsRaw = inner.client.clients.filter(_.supports.probe).size
val clientBits = max(1, clientBitsRaw)
val stateBits = 2
val wayBits = log2Ceil(cache.ways)
val setBits = log2Ceil(cache.sets)
val offsetBits = log2Ceil(cache.blockBytes)
val tagBits = addressBits - setBits - offsetBits
val putBits = log2Ceil(max(putLists, relLists))
require (tagBits > 0)
require (offsetBits > 0)
val innerBeatBits = (offsetBits - log2Ceil(inner.manager.beatBytes)) max 1
val outerBeatBits = (offsetBits - log2Ceil(outer.manager.beatBytes)) max 1
val innerMaskBits = inner.manager.beatBytes / micro.writeBytes
val outerMaskBits = outer.manager.beatBytes / micro.writeBytes
def clientBit(source: UInt): UInt = {
if (clientBitsRaw == 0) {
0.U
} else {
Cat(inner.client.clients.filter(_.supports.probe).map(_.sourceId.contains(source)).reverse)
}
}
def clientSource(bit: UInt): UInt = {
if (clientBitsRaw == 0) {
0.U
} else {
Mux1H(bit, inner.client.clients.filter(_.supports.probe).map(c => c.sourceId.start.U))
}
}
def parseAddress(x: UInt): (UInt, UInt, UInt) = {
val offset = Cat(addressMapping.map(o => x(o,o)).reverse)
val set = offset >> offsetBits
val tag = set >> setBits
(tag(tagBits-1, 0), set(setBits-1, 0), offset(offsetBits-1, 0))
}
def widen(x: UInt, width: Int): UInt = {
val y = x | 0.U(width.W)
assert (y >> width === 0.U)
y(width-1, 0)
}
def expandAddress(tag: UInt, set: UInt, offset: UInt): UInt = {
val base = Cat(widen(tag, tagBits), widen(set, setBits), widen(offset, offsetBits))
val bits = Array.fill(outer.bundle.addressBits) { 0.U(1.W) }
addressMapping.zipWithIndex.foreach { case (a, i) => bits(a) = base(i,i) }
Cat(bits.reverse)
}
def restoreAddress(expanded: UInt): UInt = {
val missingBits = flatAddresses
.map { a => (a.widen(pickMask).base, a.widen(~pickMask)) } // key is the bits to restore on match
.groupBy(_._1)
.view
.mapValues(_.map(_._2))
val muxMask = AddressDecoder(missingBits.values.toList)
val mux = missingBits.toList.map { case (bits, addrs) =>
val widen = addrs.map(_.widen(~muxMask))
val matches = AddressSet
.unify(widen.distinct)
.map(_.contains(expanded))
.reduce(_ || _)
(matches, bits.U)
}
expanded | Mux1H(mux)
}
def dirReg[T <: Data](x: T, en: Bool = true.B): T = {
if (micro.dirReg) RegEnable(x, en) else x
}
def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) =
cover(cond, "CCACHE_L" + cache.level + "_" + label, "MemorySystem;;" + desc)
}
object MetaData
{
val stateBits = 2
def INVALID: UInt = 0.U(stateBits.W) // way is empty
def BRANCH: UInt = 1.U(stateBits.W) // outer slave cache is trunk
def TRUNK: UInt = 2.U(stateBits.W) // unique inner master cache is trunk
def TIP: UInt = 3.U(stateBits.W) // we are trunk, inner masters are branch
// Does a request need trunk?
def needT(opcode: UInt, param: UInt): Bool = {
!opcode(2) ||
(opcode === TLMessages.Hint && param === TLHints.PREFETCH_WRITE) ||
((opcode === TLMessages.AcquireBlock || opcode === TLMessages.AcquirePerm) && param =/= TLPermissions.NtoB)
}
// Does a request prove the client need not be probed?
def skipProbeN(opcode: UInt, hintsSkipProbe: Boolean): Bool = {
// Acquire(toB) and Get => is N, so no probe
// Acquire(*toT) => is N or B, but need T, so no probe
// Hint => could be anything, so probe IS needed, if hintsSkipProbe is enabled, skip probe the same client
// Put* => is N or B, so probe IS needed
opcode === TLMessages.AcquireBlock || opcode === TLMessages.AcquirePerm || opcode === TLMessages.Get || (opcode === TLMessages.Hint && hintsSkipProbe.B)
}
def isToN(param: UInt): Bool = {
param === TLPermissions.TtoN || param === TLPermissions.BtoN || param === TLPermissions.NtoN
}
def isToB(param: UInt): Bool = {
param === TLPermissions.TtoB || param === TLPermissions.BtoB
}
}
object InclusiveCacheParameters
{
val lfsrBits = 10
val L2ControlAddress = 0x2010000
val L2ControlSize = 0x1000
def out_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = {
// We need 2-3 normal MSHRs to cover the Directory latency
// To fully exploit memory bandwidth-delay-product, we need memCyles/blockBeats MSHRs
max(if (micro.dirReg) 3 else 2, (micro.memCycles + cache.blockBeats - 1) / cache.blockBeats)
}
def all_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int =
// We need a dedicated MSHR for B+C each
2 + out_mshrs(cache, micro)
}
class InclusiveCacheBundle(params: InclusiveCacheParameters) extends Bundle
| module MSHR_32( // @[MSHR.scala:84:7]
input clock, // @[MSHR.scala:84:7]
input reset, // @[MSHR.scala:84:7]
input io_allocate_valid, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_0, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_1, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_2, // @[MSHR.scala:86:14]
input io_allocate_bits_control, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_source, // @[MSHR.scala:86:14]
input [8:0] io_allocate_bits_tag, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14]
input [10:0] io_allocate_bits_set, // @[MSHR.scala:86:14]
input io_allocate_bits_repeat, // @[MSHR.scala:86:14]
input io_directory_valid, // @[MSHR.scala:86:14]
input io_directory_bits_dirty, // @[MSHR.scala:86:14]
input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14]
input io_directory_bits_clients, // @[MSHR.scala:86:14]
input [8:0] io_directory_bits_tag, // @[MSHR.scala:86:14]
input io_directory_bits_hit, // @[MSHR.scala:86:14]
input [3:0] io_directory_bits_way, // @[MSHR.scala:86:14]
output io_status_valid, // @[MSHR.scala:86:14]
output [10:0] io_status_bits_set, // @[MSHR.scala:86:14]
output [8:0] io_status_bits_tag, // @[MSHR.scala:86:14]
output [3:0] io_status_bits_way, // @[MSHR.scala:86:14]
output io_status_bits_blockB, // @[MSHR.scala:86:14]
output io_status_bits_nestB, // @[MSHR.scala:86:14]
output io_status_bits_blockC, // @[MSHR.scala:86:14]
output io_status_bits_nestC, // @[MSHR.scala:86:14]
input io_schedule_ready, // @[MSHR.scala:86:14]
output io_schedule_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_a_valid, // @[MSHR.scala:86:14]
output [8:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14]
output [10:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14]
output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14]
output io_schedule_bits_b_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14]
output [8:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14]
output [10:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14]
output io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14]
output io_schedule_bits_c_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14]
output [8:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14]
output [10:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14]
output [3:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14]
output io_schedule_bits_d_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_0, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14]
output [8:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14]
output [10:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14]
output [3:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14]
output io_schedule_bits_e_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14]
output io_schedule_bits_x_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14]
output [10:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14]
output [3:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14]
output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14]
output [8:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14]
output io_schedule_bits_reload, // @[MSHR.scala:86:14]
input io_sinkc_valid, // @[MSHR.scala:86:14]
input io_sinkc_bits_last, // @[MSHR.scala:86:14]
input [10:0] io_sinkc_bits_set, // @[MSHR.scala:86:14]
input [8:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14]
input [5:0] io_sinkc_bits_source, // @[MSHR.scala:86:14]
input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14]
input io_sinkc_bits_data, // @[MSHR.scala:86:14]
input io_sinkd_valid, // @[MSHR.scala:86:14]
input io_sinkd_bits_last, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14]
input [3:0] io_sinkd_bits_source, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14]
input io_sinkd_bits_denied, // @[MSHR.scala:86:14]
input io_sinke_valid, // @[MSHR.scala:86:14]
input [3:0] io_sinke_bits_sink, // @[MSHR.scala:86:14]
input [10:0] io_nestedwb_set, // @[MSHR.scala:86:14]
input [8:0] io_nestedwb_tag, // @[MSHR.scala:86:14]
input io_nestedwb_b_toN, // @[MSHR.scala:86:14]
input io_nestedwb_b_toB, // @[MSHR.scala:86:14]
input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14]
input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14]
);
wire [8:0] final_meta_writeback_tag; // @[MSHR.scala:215:38]
wire final_meta_writeback_clients; // @[MSHR.scala:215:38]
wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38]
wire final_meta_writeback_dirty; // @[MSHR.scala:215:38]
wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_0_0 = io_allocate_bits_prio_0; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7]
wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7]
wire [8:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7]
wire [10:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7]
wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7]
wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7]
wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7]
wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7]
wire io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7]
wire [8:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7]
wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7]
wire [3:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7]
wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7]
wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7]
wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7]
wire [10:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7]
wire [8:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7]
wire [5:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7]
wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7]
wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7]
wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7]
wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7]
wire [3:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7]
wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7]
wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7]
wire [3:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7]
wire [10:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7]
wire [8:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7]
wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7]
wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7]
wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7]
wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_a_bits_source = 4'h0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_c_bits_source = 4'h0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_d_bits_sink = 4'h0; // @[MSHR.scala:84:7]
wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7]
wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68]
wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80]
wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21]
wire invalid_clients = 1'h0; // @[MSHR.scala:268:21]
wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137]
wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11]
wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137]
wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11]
wire [8:0] invalid_tag = 9'h0; // @[MSHR.scala:268:21]
wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21]
wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70]
wire allocate_as_full_prio_0 = io_allocate_bits_prio_0_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34]
wire [8:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34]
wire [10:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34]
wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40]
wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93]
wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28]
wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39]
wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105]
wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55]
wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91]
wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41]
wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41]
wire [8:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41]
wire _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51]
wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64]
wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41]
wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41]
wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57]
wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41]
wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43]
wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40]
wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66]
wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41]
wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41]
wire _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41]
wire [8:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41]
wire no_wait; // @[MSHR.scala:183:83]
wire [10:0] io_status_bits_set_0; // @[MSHR.scala:84:7]
wire [8:0] io_status_bits_tag_0; // @[MSHR.scala:84:7]
wire [3:0] io_status_bits_way_0; // @[MSHR.scala:84:7]
wire io_status_bits_blockB_0; // @[MSHR.scala:84:7]
wire io_status_bits_nestB_0; // @[MSHR.scala:84:7]
wire io_status_bits_blockC_0; // @[MSHR.scala:84:7]
wire io_status_bits_nestC_0; // @[MSHR.scala:84:7]
wire io_status_valid_0; // @[MSHR.scala:84:7]
wire [8:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7]
wire [10:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7]
wire [8:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7]
wire [10:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7]
wire [8:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7]
wire [10:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_0_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7]
wire [8:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7]
wire [10:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7]
wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7]
wire [8:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7]
wire [10:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7]
wire io_schedule_valid_0; // @[MSHR.scala:84:7]
reg request_valid; // @[MSHR.scala:97:30]
assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30]
reg request_prio_0; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_0_0 = request_prio_0; // @[MSHR.scala:84:7, :98:20]
reg request_prio_1; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20]
reg request_prio_2; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20]
reg request_control; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20]
reg [2:0] request_opcode; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20]
reg [2:0] request_param; // @[MSHR.scala:98:20]
reg [2:0] request_size; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_source; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20]
reg [8:0] request_tag; // @[MSHR.scala:98:20]
assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_offset; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_put; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20]
reg [10:0] request_set; // @[MSHR.scala:98:20]
assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
reg meta_valid; // @[MSHR.scala:99:27]
reg meta_dirty; // @[MSHR.scala:100:17]
assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17]
reg [1:0] meta_state; // @[MSHR.scala:100:17]
reg meta_clients; // @[MSHR.scala:100:17]
wire _meta_no_clients_T = meta_clients; // @[MSHR.scala:100:17, :220:39]
wire evict_c = meta_clients; // @[MSHR.scala:100:17, :315:27]
wire before_c = meta_clients; // @[MSHR.scala:100:17, :315:27]
reg [8:0] meta_tag; // @[MSHR.scala:100:17]
assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17]
reg meta_hit; // @[MSHR.scala:100:17]
reg [3:0] meta_way; // @[MSHR.scala:100:17]
assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
wire [3:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38]
reg s_rprobe; // @[MSHR.scala:121:33]
reg w_rprobeackfirst; // @[MSHR.scala:122:33]
reg w_rprobeacklast; // @[MSHR.scala:123:33]
reg s_release; // @[MSHR.scala:124:33]
reg w_releaseack; // @[MSHR.scala:125:33]
reg s_pprobe; // @[MSHR.scala:126:33]
reg s_acquire; // @[MSHR.scala:127:33]
reg s_flush; // @[MSHR.scala:128:33]
reg w_grantfirst; // @[MSHR.scala:129:33]
reg w_grantlast; // @[MSHR.scala:130:33]
reg w_grant; // @[MSHR.scala:131:33]
reg w_pprobeackfirst; // @[MSHR.scala:132:33]
reg w_pprobeacklast; // @[MSHR.scala:133:33]
reg w_pprobeack; // @[MSHR.scala:134:33]
reg s_grantack; // @[MSHR.scala:136:33]
reg s_execute; // @[MSHR.scala:137:33]
reg w_grantack; // @[MSHR.scala:138:33]
reg s_writeback; // @[MSHR.scala:139:33]
reg [2:0] sink; // @[MSHR.scala:147:17]
assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17]
reg gotT; // @[MSHR.scala:148:17]
reg bad_grant; // @[MSHR.scala:149:22]
assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22]
reg probes_done; // @[MSHR.scala:150:24]
reg probes_toN; // @[MSHR.scala:151:23]
reg probes_noT; // @[MSHR.scala:152:23]
wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28]
wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45]
wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62]
wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 | _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}]
wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82]
wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 | _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}]
wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103]
wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}]
assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T | _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}]
assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40]
wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39]
wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}]
wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}]
wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96]
assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}]
assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93]
assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28]
assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28]
wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43]
wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64]
wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T | _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}]
wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85]
wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 | _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}]
assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}]
assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39]
wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33]
wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}]
wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}]
assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}]
assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83]
wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31]
wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}]
assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}]
assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55]
wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31]
wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44]
assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T | _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}]
assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41]
wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32]
wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}]
assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}]
assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64]
wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31]
wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}]
assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}]
assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57]
wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31]
assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}]
assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43]
wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31]
assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}]
assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40]
wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34]
wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}]
wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70]
wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}]
assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 | _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}]
assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66]
wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 | io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49]
wire _io_schedule_valid_T_1 = _io_schedule_valid_T | io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}]
wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 | io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}]
wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 | io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49]
wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 | io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}]
assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 | io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}]
assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105]
wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71]
wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71]
wire _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71]
wire after_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27]
wire prior_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27]
wire [8:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71]
wire final_meta_writeback_hit; // @[MSHR.scala:215:38]
wire req_clientBit = request_source == 6'h28; // @[Parameters.scala:46:9]
wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12]
wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12]
wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}]
wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13]
wire _req_needT_T_2; // @[Parameters.scala:270:13]
assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13]
wire _excluded_client_T_6; // @[Parameters.scala:279:117]
assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117]
wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42]
wire _req_needT_T_3; // @[Parameters.scala:270:42]
assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42]
wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11]
assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11]
wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42]
wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}]
wire _req_needT_T_5 = _req_needT_T_1 | _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33]
wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14]
wire _req_needT_T_6; // @[Parameters.scala:271:14]
assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14]
wire _req_acquire_T; // @[MSHR.scala:219:36]
assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14]
wire _excluded_client_T_1; // @[Parameters.scala:279:12]
assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12]
wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52]
wire _req_needT_T_8 = _req_needT_T_6 | _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}]
wire _req_needT_T_9 = |request_param; // @[Parameters.scala:271:89]
wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}]
wire req_needT = _req_needT_T_5 | _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80]
wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52]
wire req_acquire = _req_acquire_T | _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}]
wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}]
wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81]
wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}]
wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}]
wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}]
wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65]
wire _final_meta_writeback_dirty_T_1 = meta_dirty | _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}]
wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55]
wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78]
wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78]
assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78]
wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70]
assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70]
wire _evict_T_2; // @[MSHR.scala:317:26]
assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26]
wire _before_T_1; // @[MSHR.scala:317:26]
assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26]
wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}]
wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}]
wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43]
wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43]
assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43]
wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43]
wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T | _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}]
wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75]
wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 | _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}]
wire _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 & req_clientBit; // @[Parameters.scala:46:9]
wire _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}]
wire _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}]
wire _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54]
wire _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}]
wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45]
wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}]
wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 | _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}]
wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40]
wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40]
assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40]
wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65]
assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65]
wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41]
wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}]
wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72]
wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}]
wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70]
wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70]
assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70]
wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53]
assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53]
wire _evict_T_1; // @[MSHR.scala:317:26]
assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26]
wire _before_T; // @[MSHR.scala:317:26]
assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26]
wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70]
wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70]
wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55]
wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70]
wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70]
wire _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66]
wire _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}]
wire _final_meta_writeback_clients_T_12 = meta_hit & _final_meta_writeback_clients_T_11; // @[MSHR.scala:100:17, :245:{40,64}]
wire _final_meta_writeback_clients_T_13 = req_acquire & req_clientBit; // @[Parameters.scala:46:9]
wire _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 | _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40]
assign final_meta_writeback_tag = request_prio_2 | request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30]
wire _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54]
wire _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}]
assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 | ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21]
assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21]
assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36]
assign final_meta_writeback_clients = bad_grant ? meta_hit & _final_meta_writeback_clients_T_16 : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36]
wire _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:46:9]
wire _honour_BtoT_T_1 = _honour_BtoT_T; // @[MSHR.scala:276:{47,64}]
wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}]
wire _excluded_client_T = meta_hit & request_prio_0; // @[MSHR.scala:98:20, :100:17, :279:38]
wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50]
wire _excluded_client_T_3 = _excluded_client_T_1 | _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}]
wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87]
wire _excluded_client_T_5 = _excluded_client_T_3 | _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}]
wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}]
wire _excluded_client_T_9 = _excluded_client_T & _excluded_client_T_8; // @[Parameters.scala:279:106]
wire excluded_client = _excluded_client_T_9 & req_clientBit; // @[Parameters.scala:46:9]
wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56]
wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70]
assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}]
wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51]
wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55]
wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52]
wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 | _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}]
wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}]
assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T | _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38]
assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91]
wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42]
wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70]
wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}]
assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}]
assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41]
wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42]
assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}]
assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41]
wire _io_schedule_bits_b_bits_clients_T = ~excluded_client; // @[MSHR.scala:279:28, :289:53]
assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients & _io_schedule_bits_b_bits_clients_T; // @[MSHR.scala:100:17, :289:{51,53}]
assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51]
assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41]
assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41]
assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}]
assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41]
wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42]
wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53]
wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53]
wire _io_schedule_bits_d_bits_param_T_3 = ~(|request_param); // @[Parameters.scala:271:89]
wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53]
wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53]
wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79]
assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41]
wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42]
assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_clients = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 9'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}]
assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41]
wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32]
wire [3:0] evict; // @[MSHR.scala:314:26]
wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32]
wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32]
wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32]
assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32]
wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32]
assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32]
wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26]
wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39]
wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39]
assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39]
wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39]
assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39]
wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76]
wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76]
assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76]
wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76]
assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76]
wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _evict_T_4 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26]
wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32]
assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}]
wire [3:0] before_0; // @[MSHR.scala:314:26]
wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32]
wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26]
wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _before_T_3 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26]
wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11]
assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}]
wire [3:0] after; // @[MSHR.scala:314:26]
wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26]
wire _after_T; // @[MSHR.scala:317:26]
assign _after_T = _GEN_9; // @[MSHR.scala:317:26]
wire _prior_T; // @[MSHR.scala:317:26]
assign _prior_T = _GEN_9; // @[MSHR.scala:317:26]
wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32]
wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26]
wire _after_T_1; // @[MSHR.scala:317:26]
assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26]
wire _prior_T_1; // @[MSHR.scala:317:26]
assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26]
wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32]
wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32]
assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32]
wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32]
assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32]
wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26]
wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39]
wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39]
assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39]
wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39]
assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39]
wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76]
wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76]
assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76]
wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76]
assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76]
wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26]
wire _after_T_3; // @[MSHR.scala:317:26]
assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26]
wire _prior_T_3; // @[MSHR.scala:317:26]
assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26]
assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26]
wire probe_bit = io_sinkc_bits_source_0 == 6'h28; // @[Parameters.scala:46:9]
wire _GEN_15 = probes_done | probe_bit; // @[Parameters.scala:46:9]
wire _last_probe_T; // @[MSHR.scala:459:33]
assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33]
wire _probes_done_T; // @[MSHR.scala:467:32]
assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32]
wire _last_probe_T_1 = ~excluded_client; // @[MSHR.scala:279:28, :289:53, :459:66]
wire _last_probe_T_2 = meta_clients & _last_probe_T_1; // @[MSHR.scala:100:17, :459:{64,66}]
wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}]
wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11]
wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43]
wire _probe_toN_T_2 = _probe_toN_T | _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}]
wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75]
wire probe_toN = _probe_toN_T_2 | _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}]
wire _probes_toN_T = probe_toN & probe_bit; // @[Parameters.scala:46:9]
wire _probes_toN_T_1 = probes_toN | _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}]
wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53]
wire _probes_noT_T_1 = probes_noT | _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}]
wire _w_rprobeackfirst_T = w_rprobeackfirst | last_probe; // @[MSHR.scala:122:33, :459:46, :470:42]
wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55]
wire _w_rprobeacklast_T; // @[MSHR.scala:471:55]
assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55]
wire _w_pprobeacklast_T; // @[MSHR.scala:473:55]
assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55]
wire _w_rprobeacklast_T_1 = w_rprobeacklast | _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}]
wire _w_pprobeackfirst_T = w_pprobeackfirst | last_probe; // @[MSHR.scala:132:33, :459:46, :472:42]
wire _w_pprobeacklast_T_1 = w_pprobeacklast | _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}]
wire _set_pprobeack_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77]
wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 | _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}]
wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}]
wire _w_pprobeack_T = w_pprobeack | set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32]
wire _w_grant_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33]
wire _w_grant_T_1 = _w_grant_T | io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}]
wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35]
wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40]
wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [8:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [3:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_request_prio_0 = io_allocate_valid_0 ? allocate_as_full_prio_0 : request_prio_0; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [8:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [10:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12]
wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}]
wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13]
wire _new_needT_T_2; // @[Parameters.scala:270:13]
assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13]
wire _new_skipProbe_T_5; // @[Parameters.scala:279:117]
assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117]
wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42]
wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}]
wire _new_needT_T_5 = _new_needT_T_1 | _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33]
wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14]
wire _new_needT_T_6; // @[Parameters.scala:271:14]
assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14]
wire _new_skipProbe_T; // @[Parameters.scala:279:12]
assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12]
wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52]
wire _new_needT_T_8 = _new_needT_T_6 | _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}]
wire _new_needT_T_9 = |new_request_param; // @[Parameters.scala:271:89]
wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}]
wire new_needT = _new_needT_T_5 | _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80]
wire new_clientBit = new_request_source == 6'h28; // @[Parameters.scala:46:9]
wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50]
wire _new_skipProbe_T_2 = _new_skipProbe_T | _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}]
wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87]
wire _new_skipProbe_T_4 = _new_skipProbe_T_2 | _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}]
wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}]
wire new_skipProbe = _new_skipProbe_T_7 & new_clientBit; // @[Parameters.scala:46:9]
wire [3:0] prior; // @[MSHR.scala:314:26]
wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32]
wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26]
wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26]
wire _T_574 = io_directory_valid_0 | _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28] |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor_42( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [1:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input io_in_b_ready, // @[Monitor.scala:20:14]
input io_in_b_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_b_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_b_bits_size, // @[Monitor.scala:20:14]
input [1:0] io_in_b_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_b_bits_mask, // @[Monitor.scala:20:14]
input io_in_b_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_c_ready, // @[Monitor.scala:20:14]
input io_in_c_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_c_bits_size, // @[Monitor.scala:20:14]
input [1:0] io_in_c_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_e_ready, // @[Monitor.scala:20:14]
input io_in_e_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_e_bits_sink // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire [26:0] _GEN = {23'h0, io_in_a_bits_size}; // @[package.scala:243:71]
wire [26:0] _GEN_0 = {23'h0, io_in_c_bits_size}; // @[package.scala:243:71]
wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg [1:0] source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
wire _d_first_T_3 = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala:51:35]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg [1:0] source_1; // @[Monitor.scala:541:22]
reg [2:0] sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [8:0] b_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_2; // @[Monitor.scala:410:22]
reg [1:0] param_2; // @[Monitor.scala:411:22]
reg [3:0] size_2; // @[Monitor.scala:412:22]
reg [1:0] source_2; // @[Monitor.scala:413:22]
reg [31:0] address_1; // @[Monitor.scala:414:22]
wire _c_first_T_1 = io_in_c_ready & io_in_c_valid; // @[Decoupled.scala:51:35]
reg [8:0] c_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_3; // @[Monitor.scala:515:22]
reg [2:0] param_3; // @[Monitor.scala:516:22]
reg [3:0] size_3; // @[Monitor.scala:517:22]
reg [1:0] source_3; // @[Monitor.scala:518:22]
reg [31:0] address_2; // @[Monitor.scala:519:22]
reg [2:0] inflight; // @[Monitor.scala:614:27]
reg [11:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [23:0] inflight_sizes; // @[Monitor.scala:618:33]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire [3:0] _GEN_1 = {2'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35]
wire _GEN_2 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35]
wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46]
wire _GEN_3 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74]
wire [3:0] _GEN_4 = {2'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [2:0] inflight_1; // @[Monitor.scala:726:35]
reg [23:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg [8:0] c_first_counter_1; // @[Edges.scala:229:27]
wire c_first_1 = c_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _GEN_5 = io_in_c_bits_opcode[2] & io_in_c_bits_opcode[1]; // @[Edges.scala:68:{36,40,51}]
wire [3:0] _GEN_6 = {2'h0, io_in_c_bits_source}; // @[OneHot.scala:58:35]
wire _GEN_7 = _c_first_T_1 & c_first_1 & _GEN_5; // @[Decoupled.scala:51:35]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
reg [7:0] inflight_2; // @[Monitor.scala:828:27]
reg [8:0] d_first_counter_3; // @[Edges.scala:229:27]
wire d_first_3 = d_first_counter_3 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _GEN_8 = _d_first_T_3 & d_first_3 & io_in_d_bits_opcode[2] & ~(io_in_d_bits_opcode[1]); // @[Decoupled.scala:51:35]
wire [7:0] _GEN_9 = {5'h0, io_in_d_bits_sink}; // @[OneHot.scala:58:35]
wire [7:0] d_set = _GEN_8 ? 8'h1 << _GEN_9 : 8'h0; // @[OneHot.scala:58:35]
wire _GEN_10 = io_in_e_ready & io_in_e_valid; // @[Decoupled.scala:51:35]
wire [7:0] _GEN_11 = {5'h0, io_in_e_bits_sink}; // @[OneHot.scala:58:35] |
Generate the Verilog code corresponding to the following Chisel files.
File Nodes.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection}
case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args))
object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
{
def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo)
def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo)
def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle)
def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle)
def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString)
override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = {
val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge)))
monitor.io.in := bundle
}
override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters =
pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })
override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters =
pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })
}
trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut]
case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode
case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode
case class TLAdapterNode(
clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s },
managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLJunctionNode(
clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters],
managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])(
implicit valName: ValName)
extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode
object TLNameNode {
def apply(name: ValName) = TLIdentityNode()(name)
def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLIdentityNode = apply(Some(name))
}
case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)()
object TLTempNode {
def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp"))
}
case class TLNexusNode(
clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters,
managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)(
implicit valName: ValName)
extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode
abstract class TLCustomNode(implicit valName: ValName)
extends CustomNode(TLImp) with TLFormatNode
// Asynchronous crossings
trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters]
object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle]
{
def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle)
def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString)
override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLAsyncAdapterNode(
clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s },
managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode
case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode
object TLAsyncNameNode {
def apply(name: ValName) = TLAsyncIdentityNode()(name)
def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLAsyncIdentityNode = apply(Some(name))
}
case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLAsyncImp)(
dFn = { p => TLAsyncClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain
case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName)
extends MixedAdapterNode(TLAsyncImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) },
uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut]
// Rationally related crossings
trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters]
object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle]
{
def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle)
def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */)
override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLRationalAdapterNode(
clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s },
managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode
case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode
object TLRationalNameNode {
def apply(name: ValName) = TLRationalIdentityNode()(name)
def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLRationalIdentityNode = apply(Some(name))
}
case class TLRationalSourceNode()(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLRationalImp)(
dFn = { p => TLRationalClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain
case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName)
extends MixedAdapterNode(TLRationalImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut]
// Credited version of TileLink channels
trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters]
object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle]
{
def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle)
def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString)
override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLCreditedAdapterNode(
clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s },
managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode
case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode
object TLCreditedNameNode {
def apply(name: ValName) = TLCreditedIdentityNode()(name)
def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLCreditedIdentityNode = apply(Some(name))
}
case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLCreditedImp)(
dFn = { p => TLCreditedClientPortParameters(delay, p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain
case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLCreditedImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut]
File AsyncQueue.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
case class AsyncQueueParams(
depth: Int = 8,
sync: Int = 3,
safe: Boolean = true,
// If safe is true, then effort is made to resynchronize the crossing indices when either side is reset.
// This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty.
narrow: Boolean = false)
// If narrow is true then the read mux is moved to the source side of the crossing.
// This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing,
// at the expense of a combinational path from the sink to the source and back to the sink.
{
require (depth > 0 && isPow2(depth))
require (sync >= 2)
val bits = log2Ceil(depth)
val wires = if (narrow) 1 else depth
}
object AsyncQueueParams {
// When there is only one entry, we don't need narrow.
def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false)
}
class AsyncBundleSafety extends Bundle {
val ridx_valid = Input (Bool())
val widx_valid = Output(Bool())
val source_reset_n = Output(Bool())
val sink_reset_n = Input (Bool())
}
class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle {
// Data-path synchronization
val mem = Output(Vec(params.wires, gen))
val ridx = Input (UInt((params.bits+1).W))
val widx = Output(UInt((params.bits+1).W))
val index = params.narrow.option(Input(UInt(params.bits.W)))
// Signals used to self-stabilize a safe AsyncQueue
val safe = params.safe.option(new AsyncBundleSafety)
}
object GrayCounter {
def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = {
val incremented = Wire(UInt(bits.W))
val binary = RegNext(next=incremented, init=0.U).suggestName(name)
incremented := Mux(clear, 0.U, binary + increment.asUInt)
incremented ^ (incremented >> 1)
}
}
class AsyncValidSync(sync: Int, desc: String) extends RawModule {
val io = IO(new Bundle {
val in = Input(Bool())
val out = Output(Bool())
})
val clock = IO(Input(Clock()))
val reset = IO(Input(AsyncReset()))
withClockAndReset(clock, reset){
io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc))
}
}
class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSource_${gen.typeName}"
val io = IO(new Bundle {
// These come from the source domain
val enq = Flipped(Decoupled(gen))
// These cross to the sink clock domain
val async = new AsyncBundle(gen, params)
})
val bits = params.bits
val sink_ready = WireInit(true.B)
val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all.
val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin"))
val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray"))
val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U)
val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1))
when (io.enq.fire) { mem(index) := io.enq.bits }
val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg"))
io.enq.ready := ready_reg && sink_ready
val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray"))
io.async.widx := widx_reg
io.async.index match {
case Some(index) => io.async.mem(0) := mem(index)
case None => io.async.mem := mem
}
io.async.safe.foreach { sio =>
val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0"))
val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1"))
val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend"))
val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid"))
source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_valid .reset := reset.asAsyncReset
source_valid_0.clock := clock
source_valid_1.clock := clock
sink_extend .clock := clock
sink_valid .clock := clock
source_valid_0.io.in := true.B
source_valid_1.io.in := source_valid_0.io.out
sio.widx_valid := source_valid_1.io.out
sink_extend.io.in := sio.ridx_valid
sink_valid.io.in := sink_extend.io.out
sink_ready := sink_valid.io.out
sio.source_reset_n := !reset.asBool
// Assert that if there is stuff in the queue, then reset cannot happen
// Impossible to write because dequeue can occur on the receiving side,
// then reset allowed to happen, but write side cannot know that dequeue
// occurred.
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
// assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected")
// assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty")
}
}
class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSink_${gen.typeName}"
val io = IO(new Bundle {
// These come from the sink domain
val deq = Decoupled(gen)
// These cross to the source clock domain
val async = Flipped(new AsyncBundle(gen, params))
})
val bits = params.bits
val source_ready = WireInit(true.B)
val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin"))
val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray"))
val valid = source_ready && ridx =/= widx
// The mux is safe because timing analysis ensures ridx has reached the register
// On an ASIC, changes to the unread location cannot affect the selected value
// On an FPGA, only one input changes at a time => mem updates don't cause glitches
// The register only latches when the selected valued is not being written
val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1))
io.async.index.foreach { _ := index }
// This register does not NEED to be reset, as its contents will not
// be considered unless the asynchronously reset deq valid register is set.
// It is possible that bits latches when the source domain is reset / has power cut
// This is safe, because isolation gates brought mem low before the zeroed widx reached us
val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index)
io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg"))
val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg"))
io.deq.valid := valid_reg && source_ready
val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray"))
io.async.ridx := ridx_reg
io.async.safe.foreach { sio =>
val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0"))
val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1"))
val source_extend = Module(new AsyncValidSync(params.sync, "source_extend"))
val source_valid = Module(new AsyncValidSync(params.sync, "source_valid"))
sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_valid .reset := reset.asAsyncReset
sink_valid_0 .clock := clock
sink_valid_1 .clock := clock
source_extend.clock := clock
source_valid .clock := clock
sink_valid_0.io.in := true.B
sink_valid_1.io.in := sink_valid_0.io.out
sio.ridx_valid := sink_valid_1.io.out
source_extend.io.in := sio.widx_valid
source_valid.io.in := source_extend.io.out
source_ready := source_valid.io.out
sio.sink_reset_n := !reset.asBool
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
//
// val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool
// val reset_and_extend_prev = RegNext(reset_and_extend, true.B)
// val reset_rise = !reset_and_extend_prev && reset_and_extend
// val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0)
// assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty")
}
}
object FromAsyncBundle
{
// Sometimes it makes sense for the sink to have different sync than the source
def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync)
def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = {
val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync)))
sink.io.async <> x
sink.io.deq
}
}
object ToAsyncBundle
{
def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = {
val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params))
source.io.enq <> x
source.io.async
}
}
class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] {
val io = IO(new CrossingIO(gen))
val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) }
val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) }
source.io.enq <> io.enq
io.deq <> sink.io.deq
sink.io.async <> source.io.async
}
File AsyncCrossing.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.{AddressSet, NodeHandle}
import freechips.rocketchip.prci.{AsynchronousCrossing}
import freechips.rocketchip.subsystem.CrossingWrapper
import freechips.rocketchip.util.{AsyncQueueParams, ToAsyncBundle, FromAsyncBundle, Pow2ClockDivider, property}
class TLAsyncCrossingSource(sync: Option[Int])(implicit p: Parameters) extends LazyModule
{
def this(x: Int)(implicit p: Parameters) = this(Some(x))
def this()(implicit p: Parameters) = this(None)
val node = TLAsyncSourceNode(sync)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
override def desiredName = (Seq("TLAsyncCrossingSource") ++ node.in.headOption.map(_._2.bundle.shortName)).mkString("_")
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
val bce = edgeIn.manager.anySupportAcquireB && edgeIn.client.anySupportProbe
val psync = sync.getOrElse(edgeOut.manager.async.sync)
val params = edgeOut.manager.async.copy(sync = psync)
out.a <> ToAsyncBundle(in.a, params)
in.d <> FromAsyncBundle(out.d, psync)
property.cover(in.a, "TL_ASYNC_CROSSING_SOURCE_A", "MemorySystem;;TLAsyncCrossingSource Channel A")
property.cover(in.d, "TL_ASYNC_CROSSING_SOURCE_D", "MemorySystem;;TLAsyncCrossingSource Channel D")
if (bce) {
in.b <> FromAsyncBundle(out.b, psync)
out.c <> ToAsyncBundle(in.c, params)
out.e <> ToAsyncBundle(in.e, params)
property.cover(in.b, "TL_ASYNC_CROSSING_SOURCE_B", "MemorySystem;;TLAsyncCrossingSource Channel B")
property.cover(in.c, "TL_ASYNC_CROSSING_SOURCE_C", "MemorySystem;;TLAsyncCrossingSource Channel C")
property.cover(in.e, "TL_ASYNC_CROSSING_SOURCE_E", "MemorySystem;;TLAsyncCrossingSource Channel E")
} else {
in.b.valid := false.B
in.c.ready := true.B
in.e.ready := true.B
out.b.ridx := 0.U
out.c.widx := 0.U
out.e.widx := 0.U
}
}
}
}
class TLAsyncCrossingSink(params: AsyncQueueParams = AsyncQueueParams())(implicit p: Parameters) extends LazyModule
{
val node = TLAsyncSinkNode(params)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
override def desiredName = (Seq("TLAsyncCrossingSink") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_")
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
val bce = edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe
out.a <> FromAsyncBundle(in.a, params.sync)
in.d <> ToAsyncBundle(out.d, params)
property.cover(out.a, "TL_ASYNC_CROSSING_SINK_A", "MemorySystem;;TLAsyncCrossingSink Channel A")
property.cover(out.d, "TL_ASYNC_CROSSING_SINK_D", "MemorySystem;;TLAsyncCrossingSink Channel D")
if (bce) {
in.b <> ToAsyncBundle(out.b, params)
out.c <> FromAsyncBundle(in.c, params.sync)
out.e <> FromAsyncBundle(in.e, params.sync)
property.cover(out.b, "TL_ASYNC_CROSSING_SINK_B", "MemorySystem;;TLAsyncCrossingSinkChannel B")
property.cover(out.c, "TL_ASYNC_CROSSING_SINK_C", "MemorySystem;;TLAsyncCrossingSink Channel C")
property.cover(out.e, "TL_ASYNC_CROSSING_SINK_E", "MemorySystem;;TLAsyncCrossingSink Channel E")
} else {
in.b.widx := 0.U
in.c.ridx := 0.U
in.e.ridx := 0.U
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
}
}
}
}
object TLAsyncCrossingSource
{
def apply()(implicit p: Parameters): TLAsyncSourceNode = apply(None)
def apply(sync: Int)(implicit p: Parameters): TLAsyncSourceNode = apply(Some(sync))
def apply(sync: Option[Int])(implicit p: Parameters): TLAsyncSourceNode =
{
val asource = LazyModule(new TLAsyncCrossingSource(sync))
asource.node
}
}
object TLAsyncCrossingSink
{
def apply(params: AsyncQueueParams = AsyncQueueParams())(implicit p: Parameters) =
{
val asink = LazyModule(new TLAsyncCrossingSink(params))
asink.node
}
}
@deprecated("TLAsyncCrossing is fragile. Use TLAsyncCrossingSource and TLAsyncCrossingSink", "rocket-chip 1.2")
class TLAsyncCrossing(params: AsyncQueueParams = AsyncQueueParams())(implicit p: Parameters) extends LazyModule
{
val source = LazyModule(new TLAsyncCrossingSource())
val sink = LazyModule(new TLAsyncCrossingSink(params))
val node = NodeHandle(source.node, sink.node)
sink.node := source.node
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
val io = IO(new Bundle {
val in_clock = Input(Clock())
val in_reset = Input(Bool())
val out_clock = Input(Clock())
val out_reset = Input(Bool())
})
source.module.clock := io.in_clock
source.module.reset := io.in_reset
sink.module.clock := io.out_clock
sink.module.reset := io.out_reset
}
}
// Synthesizable unit tests
import freechips.rocketchip.unittest._
class TLRAMAsyncCrossing(txns: Int, params: AsynchronousCrossing = AsynchronousCrossing())(implicit p: Parameters) extends LazyModule {
val model = LazyModule(new TLRAMModel("AsyncCrossing"))
val fuzz = LazyModule(new TLFuzzer(txns))
val island = LazyModule(new CrossingWrapper(params))
val ram = island { LazyModule(new TLRAM(AddressSet(0x0, 0x3ff))) }
island.crossTLIn(ram.node) := TLFragmenter(4, 256) := TLDelayer(0.1) := model.node := fuzz.node
lazy val module = new Impl
class Impl extends LazyModuleImp(this) with UnitTestModule {
io.finished := fuzz.module.io.finished
// Shove the RAM into another clock domain
val clocks = Module(new Pow2ClockDivider(2))
island.module.clock := clocks.io.clock_out
}
}
class TLRAMAsyncCrossingTest(txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
val dut_wide = Module(LazyModule(new TLRAMAsyncCrossing(txns)).module)
val dut_narrow = Module(LazyModule(new TLRAMAsyncCrossing(txns, AsynchronousCrossing(safe = false, narrow = true))).module)
io.finished := dut_wide.io.finished && dut_narrow.io.finished
dut_wide.io.start := io.start
dut_narrow.io.start := io.start
}
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
| module TLAsyncCrossingSource_a32d64s2k3z4c( // @[AsyncCrossing.scala:23:9]
input clock, // @[AsyncCrossing.scala:23:9]
input reset, // @[AsyncCrossing.scala:23:9]
output auto_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_b_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_b_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_b_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_b_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_b_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_b_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_in_b_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_in_b_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_b_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_b_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_in_c_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_c_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_c_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_c_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_in_c_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_c_bits_address, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_c_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_in_e_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_e_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_e_bits_sink, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_mem_0_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_mem_0_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_a_mem_0_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_out_a_mem_0_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_a_mem_0_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_a_mem_0_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_a_mem_0_data, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_mem_1_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_mem_1_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_a_mem_1_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_out_a_mem_1_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_a_mem_1_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_a_mem_1_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_a_mem_1_data, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_mem_2_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_mem_2_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_a_mem_2_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_out_a_mem_2_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_a_mem_2_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_a_mem_2_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_a_mem_2_data, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_mem_3_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_mem_3_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_a_mem_3_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_out_a_mem_3_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_a_mem_3_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_a_mem_3_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_a_mem_3_data, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_mem_4_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_mem_4_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_a_mem_4_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_out_a_mem_4_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_a_mem_4_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_a_mem_4_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_a_mem_4_data, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_mem_5_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_mem_5_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_a_mem_5_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_out_a_mem_5_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_a_mem_5_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_a_mem_5_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_a_mem_5_data, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_mem_6_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_mem_6_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_a_mem_6_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_out_a_mem_6_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_a_mem_6_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_a_mem_6_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_a_mem_6_data, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_mem_7_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_mem_7_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_a_mem_7_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_out_a_mem_7_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_a_mem_7_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_a_mem_7_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_a_mem_7_data, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_a_ridx, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_a_widx, // @[LazyModuleImp.scala:107:25]
input auto_out_a_safe_ridx_valid, // @[LazyModuleImp.scala:107:25]
output auto_out_a_safe_widx_valid, // @[LazyModuleImp.scala:107:25]
output auto_out_a_safe_source_reset_n, // @[LazyModuleImp.scala:107:25]
input auto_out_a_safe_sink_reset_n, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_b_mem_0_param, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_out_b_mem_0_address, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_b_mem_1_param, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_out_b_mem_1_address, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_b_mem_2_param, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_out_b_mem_2_address, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_b_mem_3_param, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_out_b_mem_3_address, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_b_mem_4_param, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_out_b_mem_4_address, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_b_mem_5_param, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_out_b_mem_5_address, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_b_mem_6_param, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_out_b_mem_6_address, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_b_mem_7_param, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_out_b_mem_7_address, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_b_ridx, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_b_widx, // @[LazyModuleImp.scala:107:25]
output auto_out_b_safe_ridx_valid, // @[LazyModuleImp.scala:107:25]
input auto_out_b_safe_widx_valid, // @[LazyModuleImp.scala:107:25]
input auto_out_b_safe_source_reset_n, // @[LazyModuleImp.scala:107:25]
output auto_out_b_safe_sink_reset_n, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_c_mem_0_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_c_mem_0_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_c_mem_0_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_out_c_mem_0_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_c_mem_0_address, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_c_mem_0_data, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_c_mem_1_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_c_mem_1_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_c_mem_1_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_out_c_mem_1_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_c_mem_1_address, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_c_mem_1_data, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_c_mem_2_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_c_mem_2_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_c_mem_2_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_out_c_mem_2_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_c_mem_2_address, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_c_mem_2_data, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_c_mem_3_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_c_mem_3_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_c_mem_3_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_out_c_mem_3_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_c_mem_3_address, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_c_mem_3_data, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_c_mem_4_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_c_mem_4_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_c_mem_4_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_out_c_mem_4_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_c_mem_4_address, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_c_mem_4_data, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_c_mem_5_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_c_mem_5_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_c_mem_5_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_out_c_mem_5_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_c_mem_5_address, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_c_mem_5_data, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_c_mem_6_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_c_mem_6_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_c_mem_6_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_out_c_mem_6_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_c_mem_6_address, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_c_mem_6_data, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_c_mem_7_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_c_mem_7_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_c_mem_7_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_out_c_mem_7_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_c_mem_7_address, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_c_mem_7_data, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_c_ridx, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_c_widx, // @[LazyModuleImp.scala:107:25]
input auto_out_c_safe_ridx_valid, // @[LazyModuleImp.scala:107:25]
output auto_out_c_safe_widx_valid, // @[LazyModuleImp.scala:107:25]
output auto_out_c_safe_source_reset_n, // @[LazyModuleImp.scala:107:25]
input auto_out_c_safe_sink_reset_n, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_mem_0_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_mem_0_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_d_mem_0_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_mem_0_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_mem_0_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_d_mem_0_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_d_mem_0_data, // @[LazyModuleImp.scala:107:25]
input auto_out_d_mem_0_corrupt, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_mem_1_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_mem_1_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_d_mem_1_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_mem_1_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_mem_1_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_d_mem_1_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_d_mem_1_data, // @[LazyModuleImp.scala:107:25]
input auto_out_d_mem_1_corrupt, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_mem_2_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_mem_2_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_d_mem_2_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_mem_2_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_mem_2_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_d_mem_2_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_d_mem_2_data, // @[LazyModuleImp.scala:107:25]
input auto_out_d_mem_2_corrupt, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_mem_3_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_mem_3_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_d_mem_3_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_mem_3_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_mem_3_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_d_mem_3_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_d_mem_3_data, // @[LazyModuleImp.scala:107:25]
input auto_out_d_mem_3_corrupt, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_mem_4_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_mem_4_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_d_mem_4_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_mem_4_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_mem_4_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_d_mem_4_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_d_mem_4_data, // @[LazyModuleImp.scala:107:25]
input auto_out_d_mem_4_corrupt, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_mem_5_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_mem_5_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_d_mem_5_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_mem_5_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_mem_5_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_d_mem_5_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_d_mem_5_data, // @[LazyModuleImp.scala:107:25]
input auto_out_d_mem_5_corrupt, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_mem_6_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_mem_6_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_d_mem_6_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_mem_6_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_mem_6_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_d_mem_6_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_d_mem_6_data, // @[LazyModuleImp.scala:107:25]
input auto_out_d_mem_6_corrupt, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_mem_7_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_mem_7_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_d_mem_7_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_mem_7_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_mem_7_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_d_mem_7_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_d_mem_7_data, // @[LazyModuleImp.scala:107:25]
input auto_out_d_mem_7_corrupt, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_d_ridx, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_d_widx, // @[LazyModuleImp.scala:107:25]
output auto_out_d_safe_ridx_valid, // @[LazyModuleImp.scala:107:25]
input auto_out_d_safe_widx_valid, // @[LazyModuleImp.scala:107:25]
input auto_out_d_safe_source_reset_n, // @[LazyModuleImp.scala:107:25]
output auto_out_d_safe_sink_reset_n, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_e_mem_0_sink, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_e_mem_1_sink, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_e_mem_2_sink, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_e_mem_3_sink, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_e_mem_4_sink, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_e_mem_5_sink, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_e_mem_6_sink, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_e_mem_7_sink, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_e_ridx, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_e_widx, // @[LazyModuleImp.scala:107:25]
input auto_out_e_safe_ridx_valid, // @[LazyModuleImp.scala:107:25]
output auto_out_e_safe_widx_valid, // @[LazyModuleImp.scala:107:25]
output auto_out_e_safe_source_reset_n, // @[LazyModuleImp.scala:107:25]
input auto_out_e_safe_sink_reset_n // @[LazyModuleImp.scala:107:25]
);
wire auto_in_a_valid_0 = auto_in_a_valid; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[AsyncCrossing.scala:23:9]
wire [3:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[AsyncCrossing.scala:23:9]
wire [1:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[AsyncCrossing.scala:23:9]
wire [31:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[AsyncCrossing.scala:23:9]
wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[AsyncCrossing.scala:23:9]
wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[AsyncCrossing.scala:23:9]
wire auto_in_b_ready_0 = auto_in_b_ready; // @[AsyncCrossing.scala:23:9]
wire auto_in_c_valid_0 = auto_in_c_valid; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_in_c_bits_opcode_0 = auto_in_c_bits_opcode; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_in_c_bits_param_0 = auto_in_c_bits_param; // @[AsyncCrossing.scala:23:9]
wire [3:0] auto_in_c_bits_size_0 = auto_in_c_bits_size; // @[AsyncCrossing.scala:23:9]
wire [1:0] auto_in_c_bits_source_0 = auto_in_c_bits_source; // @[AsyncCrossing.scala:23:9]
wire [31:0] auto_in_c_bits_address_0 = auto_in_c_bits_address; // @[AsyncCrossing.scala:23:9]
wire [63:0] auto_in_c_bits_data_0 = auto_in_c_bits_data; // @[AsyncCrossing.scala:23:9]
wire auto_in_d_ready_0 = auto_in_d_ready; // @[AsyncCrossing.scala:23:9]
wire auto_in_e_valid_0 = auto_in_e_valid; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_in_e_bits_sink_0 = auto_in_e_bits_sink; // @[AsyncCrossing.scala:23:9]
wire [3:0] auto_out_a_ridx_0 = auto_out_a_ridx; // @[AsyncCrossing.scala:23:9]
wire auto_out_a_safe_ridx_valid_0 = auto_out_a_safe_ridx_valid; // @[AsyncCrossing.scala:23:9]
wire auto_out_a_safe_sink_reset_n_0 = auto_out_a_safe_sink_reset_n; // @[AsyncCrossing.scala:23:9]
wire [1:0] auto_out_b_mem_0_param_0 = auto_out_b_mem_0_param; // @[AsyncCrossing.scala:23:9]
wire [31:0] auto_out_b_mem_0_address_0 = auto_out_b_mem_0_address; // @[AsyncCrossing.scala:23:9]
wire [1:0] auto_out_b_mem_1_param_0 = auto_out_b_mem_1_param; // @[AsyncCrossing.scala:23:9]
wire [31:0] auto_out_b_mem_1_address_0 = auto_out_b_mem_1_address; // @[AsyncCrossing.scala:23:9]
wire [1:0] auto_out_b_mem_2_param_0 = auto_out_b_mem_2_param; // @[AsyncCrossing.scala:23:9]
wire [31:0] auto_out_b_mem_2_address_0 = auto_out_b_mem_2_address; // @[AsyncCrossing.scala:23:9]
wire [1:0] auto_out_b_mem_3_param_0 = auto_out_b_mem_3_param; // @[AsyncCrossing.scala:23:9]
wire [31:0] auto_out_b_mem_3_address_0 = auto_out_b_mem_3_address; // @[AsyncCrossing.scala:23:9]
wire [1:0] auto_out_b_mem_4_param_0 = auto_out_b_mem_4_param; // @[AsyncCrossing.scala:23:9]
wire [31:0] auto_out_b_mem_4_address_0 = auto_out_b_mem_4_address; // @[AsyncCrossing.scala:23:9]
wire [1:0] auto_out_b_mem_5_param_0 = auto_out_b_mem_5_param; // @[AsyncCrossing.scala:23:9]
wire [31:0] auto_out_b_mem_5_address_0 = auto_out_b_mem_5_address; // @[AsyncCrossing.scala:23:9]
wire [1:0] auto_out_b_mem_6_param_0 = auto_out_b_mem_6_param; // @[AsyncCrossing.scala:23:9]
wire [31:0] auto_out_b_mem_6_address_0 = auto_out_b_mem_6_address; // @[AsyncCrossing.scala:23:9]
wire [1:0] auto_out_b_mem_7_param_0 = auto_out_b_mem_7_param; // @[AsyncCrossing.scala:23:9]
wire [31:0] auto_out_b_mem_7_address_0 = auto_out_b_mem_7_address; // @[AsyncCrossing.scala:23:9]
wire [3:0] auto_out_b_widx_0 = auto_out_b_widx; // @[AsyncCrossing.scala:23:9]
wire auto_out_b_safe_widx_valid_0 = auto_out_b_safe_widx_valid; // @[AsyncCrossing.scala:23:9]
wire auto_out_b_safe_source_reset_n_0 = auto_out_b_safe_source_reset_n; // @[AsyncCrossing.scala:23:9]
wire [3:0] auto_out_c_ridx_0 = auto_out_c_ridx; // @[AsyncCrossing.scala:23:9]
wire auto_out_c_safe_ridx_valid_0 = auto_out_c_safe_ridx_valid; // @[AsyncCrossing.scala:23:9]
wire auto_out_c_safe_sink_reset_n_0 = auto_out_c_safe_sink_reset_n; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_d_mem_0_opcode_0 = auto_out_d_mem_0_opcode; // @[AsyncCrossing.scala:23:9]
wire [1:0] auto_out_d_mem_0_param_0 = auto_out_d_mem_0_param; // @[AsyncCrossing.scala:23:9]
wire [3:0] auto_out_d_mem_0_size_0 = auto_out_d_mem_0_size; // @[AsyncCrossing.scala:23:9]
wire [1:0] auto_out_d_mem_0_source_0 = auto_out_d_mem_0_source; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_d_mem_0_sink_0 = auto_out_d_mem_0_sink; // @[AsyncCrossing.scala:23:9]
wire auto_out_d_mem_0_denied_0 = auto_out_d_mem_0_denied; // @[AsyncCrossing.scala:23:9]
wire [63:0] auto_out_d_mem_0_data_0 = auto_out_d_mem_0_data; // @[AsyncCrossing.scala:23:9]
wire auto_out_d_mem_0_corrupt_0 = auto_out_d_mem_0_corrupt; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_d_mem_1_opcode_0 = auto_out_d_mem_1_opcode; // @[AsyncCrossing.scala:23:9]
wire [1:0] auto_out_d_mem_1_param_0 = auto_out_d_mem_1_param; // @[AsyncCrossing.scala:23:9]
wire [3:0] auto_out_d_mem_1_size_0 = auto_out_d_mem_1_size; // @[AsyncCrossing.scala:23:9]
wire [1:0] auto_out_d_mem_1_source_0 = auto_out_d_mem_1_source; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_d_mem_1_sink_0 = auto_out_d_mem_1_sink; // @[AsyncCrossing.scala:23:9]
wire auto_out_d_mem_1_denied_0 = auto_out_d_mem_1_denied; // @[AsyncCrossing.scala:23:9]
wire [63:0] auto_out_d_mem_1_data_0 = auto_out_d_mem_1_data; // @[AsyncCrossing.scala:23:9]
wire auto_out_d_mem_1_corrupt_0 = auto_out_d_mem_1_corrupt; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_d_mem_2_opcode_0 = auto_out_d_mem_2_opcode; // @[AsyncCrossing.scala:23:9]
wire [1:0] auto_out_d_mem_2_param_0 = auto_out_d_mem_2_param; // @[AsyncCrossing.scala:23:9]
wire [3:0] auto_out_d_mem_2_size_0 = auto_out_d_mem_2_size; // @[AsyncCrossing.scala:23:9]
wire [1:0] auto_out_d_mem_2_source_0 = auto_out_d_mem_2_source; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_d_mem_2_sink_0 = auto_out_d_mem_2_sink; // @[AsyncCrossing.scala:23:9]
wire auto_out_d_mem_2_denied_0 = auto_out_d_mem_2_denied; // @[AsyncCrossing.scala:23:9]
wire [63:0] auto_out_d_mem_2_data_0 = auto_out_d_mem_2_data; // @[AsyncCrossing.scala:23:9]
wire auto_out_d_mem_2_corrupt_0 = auto_out_d_mem_2_corrupt; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_d_mem_3_opcode_0 = auto_out_d_mem_3_opcode; // @[AsyncCrossing.scala:23:9]
wire [1:0] auto_out_d_mem_3_param_0 = auto_out_d_mem_3_param; // @[AsyncCrossing.scala:23:9]
wire [3:0] auto_out_d_mem_3_size_0 = auto_out_d_mem_3_size; // @[AsyncCrossing.scala:23:9]
wire [1:0] auto_out_d_mem_3_source_0 = auto_out_d_mem_3_source; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_d_mem_3_sink_0 = auto_out_d_mem_3_sink; // @[AsyncCrossing.scala:23:9]
wire auto_out_d_mem_3_denied_0 = auto_out_d_mem_3_denied; // @[AsyncCrossing.scala:23:9]
wire [63:0] auto_out_d_mem_3_data_0 = auto_out_d_mem_3_data; // @[AsyncCrossing.scala:23:9]
wire auto_out_d_mem_3_corrupt_0 = auto_out_d_mem_3_corrupt; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_d_mem_4_opcode_0 = auto_out_d_mem_4_opcode; // @[AsyncCrossing.scala:23:9]
wire [1:0] auto_out_d_mem_4_param_0 = auto_out_d_mem_4_param; // @[AsyncCrossing.scala:23:9]
wire [3:0] auto_out_d_mem_4_size_0 = auto_out_d_mem_4_size; // @[AsyncCrossing.scala:23:9]
wire [1:0] auto_out_d_mem_4_source_0 = auto_out_d_mem_4_source; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_d_mem_4_sink_0 = auto_out_d_mem_4_sink; // @[AsyncCrossing.scala:23:9]
wire auto_out_d_mem_4_denied_0 = auto_out_d_mem_4_denied; // @[AsyncCrossing.scala:23:9]
wire [63:0] auto_out_d_mem_4_data_0 = auto_out_d_mem_4_data; // @[AsyncCrossing.scala:23:9]
wire auto_out_d_mem_4_corrupt_0 = auto_out_d_mem_4_corrupt; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_d_mem_5_opcode_0 = auto_out_d_mem_5_opcode; // @[AsyncCrossing.scala:23:9]
wire [1:0] auto_out_d_mem_5_param_0 = auto_out_d_mem_5_param; // @[AsyncCrossing.scala:23:9]
wire [3:0] auto_out_d_mem_5_size_0 = auto_out_d_mem_5_size; // @[AsyncCrossing.scala:23:9]
wire [1:0] auto_out_d_mem_5_source_0 = auto_out_d_mem_5_source; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_d_mem_5_sink_0 = auto_out_d_mem_5_sink; // @[AsyncCrossing.scala:23:9]
wire auto_out_d_mem_5_denied_0 = auto_out_d_mem_5_denied; // @[AsyncCrossing.scala:23:9]
wire [63:0] auto_out_d_mem_5_data_0 = auto_out_d_mem_5_data; // @[AsyncCrossing.scala:23:9]
wire auto_out_d_mem_5_corrupt_0 = auto_out_d_mem_5_corrupt; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_d_mem_6_opcode_0 = auto_out_d_mem_6_opcode; // @[AsyncCrossing.scala:23:9]
wire [1:0] auto_out_d_mem_6_param_0 = auto_out_d_mem_6_param; // @[AsyncCrossing.scala:23:9]
wire [3:0] auto_out_d_mem_6_size_0 = auto_out_d_mem_6_size; // @[AsyncCrossing.scala:23:9]
wire [1:0] auto_out_d_mem_6_source_0 = auto_out_d_mem_6_source; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_d_mem_6_sink_0 = auto_out_d_mem_6_sink; // @[AsyncCrossing.scala:23:9]
wire auto_out_d_mem_6_denied_0 = auto_out_d_mem_6_denied; // @[AsyncCrossing.scala:23:9]
wire [63:0] auto_out_d_mem_6_data_0 = auto_out_d_mem_6_data; // @[AsyncCrossing.scala:23:9]
wire auto_out_d_mem_6_corrupt_0 = auto_out_d_mem_6_corrupt; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_d_mem_7_opcode_0 = auto_out_d_mem_7_opcode; // @[AsyncCrossing.scala:23:9]
wire [1:0] auto_out_d_mem_7_param_0 = auto_out_d_mem_7_param; // @[AsyncCrossing.scala:23:9]
wire [3:0] auto_out_d_mem_7_size_0 = auto_out_d_mem_7_size; // @[AsyncCrossing.scala:23:9]
wire [1:0] auto_out_d_mem_7_source_0 = auto_out_d_mem_7_source; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_d_mem_7_sink_0 = auto_out_d_mem_7_sink; // @[AsyncCrossing.scala:23:9]
wire auto_out_d_mem_7_denied_0 = auto_out_d_mem_7_denied; // @[AsyncCrossing.scala:23:9]
wire [63:0] auto_out_d_mem_7_data_0 = auto_out_d_mem_7_data; // @[AsyncCrossing.scala:23:9]
wire auto_out_d_mem_7_corrupt_0 = auto_out_d_mem_7_corrupt; // @[AsyncCrossing.scala:23:9]
wire [3:0] auto_out_d_widx_0 = auto_out_d_widx; // @[AsyncCrossing.scala:23:9]
wire auto_out_d_safe_widx_valid_0 = auto_out_d_safe_widx_valid; // @[AsyncCrossing.scala:23:9]
wire auto_out_d_safe_source_reset_n_0 = auto_out_d_safe_source_reset_n; // @[AsyncCrossing.scala:23:9]
wire [3:0] auto_out_e_ridx_0 = auto_out_e_ridx; // @[AsyncCrossing.scala:23:9]
wire auto_out_e_safe_ridx_valid_0 = auto_out_e_safe_ridx_valid; // @[AsyncCrossing.scala:23:9]
wire auto_out_e_safe_sink_reset_n_0 = auto_out_e_safe_sink_reset_n; // @[AsyncCrossing.scala:23:9]
wire [63:0] auto_out_b_mem_0_data = 64'h0; // @[AsyncQueue.scala:211:22]
wire [63:0] auto_out_b_mem_1_data = 64'h0; // @[AsyncQueue.scala:211:22]
wire [63:0] auto_out_b_mem_2_data = 64'h0; // @[AsyncQueue.scala:211:22]
wire [63:0] auto_out_b_mem_3_data = 64'h0; // @[AsyncQueue.scala:211:22]
wire [63:0] auto_out_b_mem_4_data = 64'h0; // @[AsyncQueue.scala:211:22]
wire [63:0] auto_out_b_mem_5_data = 64'h0; // @[AsyncQueue.scala:211:22]
wire [63:0] auto_out_b_mem_6_data = 64'h0; // @[AsyncQueue.scala:211:22]
wire [63:0] auto_out_b_mem_7_data = 64'h0; // @[AsyncQueue.scala:211:22]
wire [63:0] nodeOut_b_mem_0_data = 64'h0; // @[AsyncQueue.scala:211:22]
wire [63:0] nodeOut_b_mem_1_data = 64'h0; // @[AsyncQueue.scala:211:22]
wire [63:0] nodeOut_b_mem_2_data = 64'h0; // @[AsyncQueue.scala:211:22]
wire [63:0] nodeOut_b_mem_3_data = 64'h0; // @[AsyncQueue.scala:211:22]
wire [63:0] nodeOut_b_mem_4_data = 64'h0; // @[AsyncQueue.scala:211:22]
wire [63:0] nodeOut_b_mem_5_data = 64'h0; // @[AsyncQueue.scala:211:22]
wire [63:0] nodeOut_b_mem_6_data = 64'h0; // @[AsyncQueue.scala:211:22]
wire [63:0] nodeOut_b_mem_7_data = 64'h0; // @[AsyncQueue.scala:211:22]
wire [7:0] auto_out_b_mem_0_mask = 8'hFF; // @[AsyncQueue.scala:211:22]
wire [7:0] auto_out_b_mem_1_mask = 8'hFF; // @[AsyncQueue.scala:211:22]
wire [7:0] auto_out_b_mem_2_mask = 8'hFF; // @[AsyncQueue.scala:211:22]
wire [7:0] auto_out_b_mem_3_mask = 8'hFF; // @[AsyncQueue.scala:211:22]
wire [7:0] auto_out_b_mem_4_mask = 8'hFF; // @[AsyncQueue.scala:211:22]
wire [7:0] auto_out_b_mem_5_mask = 8'hFF; // @[AsyncQueue.scala:211:22]
wire [7:0] auto_out_b_mem_6_mask = 8'hFF; // @[AsyncQueue.scala:211:22]
wire [7:0] auto_out_b_mem_7_mask = 8'hFF; // @[AsyncQueue.scala:211:22]
wire [7:0] nodeOut_b_mem_0_mask = 8'hFF; // @[AsyncQueue.scala:211:22]
wire [7:0] nodeOut_b_mem_1_mask = 8'hFF; // @[AsyncQueue.scala:211:22]
wire [7:0] nodeOut_b_mem_2_mask = 8'hFF; // @[AsyncQueue.scala:211:22]
wire [7:0] nodeOut_b_mem_3_mask = 8'hFF; // @[AsyncQueue.scala:211:22]
wire [7:0] nodeOut_b_mem_4_mask = 8'hFF; // @[AsyncQueue.scala:211:22]
wire [7:0] nodeOut_b_mem_5_mask = 8'hFF; // @[AsyncQueue.scala:211:22]
wire [7:0] nodeOut_b_mem_6_mask = 8'hFF; // @[AsyncQueue.scala:211:22]
wire [7:0] nodeOut_b_mem_7_mask = 8'hFF; // @[AsyncQueue.scala:211:22]
wire [1:0] auto_out_b_mem_0_source = 2'h0; // @[AsyncQueue.scala:211:22]
wire [1:0] auto_out_b_mem_1_source = 2'h0; // @[AsyncQueue.scala:211:22]
wire [1:0] auto_out_b_mem_2_source = 2'h0; // @[AsyncQueue.scala:211:22]
wire [1:0] auto_out_b_mem_3_source = 2'h0; // @[AsyncQueue.scala:211:22]
wire [1:0] auto_out_b_mem_4_source = 2'h0; // @[AsyncQueue.scala:211:22]
wire [1:0] auto_out_b_mem_5_source = 2'h0; // @[AsyncQueue.scala:211:22]
wire [1:0] auto_out_b_mem_6_source = 2'h0; // @[AsyncQueue.scala:211:22]
wire [1:0] auto_out_b_mem_7_source = 2'h0; // @[AsyncQueue.scala:211:22]
wire [1:0] nodeOut_b_mem_0_source = 2'h0; // @[AsyncQueue.scala:211:22]
wire [1:0] nodeOut_b_mem_1_source = 2'h0; // @[AsyncQueue.scala:211:22]
wire [1:0] nodeOut_b_mem_2_source = 2'h0; // @[AsyncQueue.scala:211:22]
wire [1:0] nodeOut_b_mem_3_source = 2'h0; // @[AsyncQueue.scala:211:22]
wire [1:0] nodeOut_b_mem_4_source = 2'h0; // @[AsyncQueue.scala:211:22]
wire [1:0] nodeOut_b_mem_5_source = 2'h0; // @[AsyncQueue.scala:211:22]
wire [1:0] nodeOut_b_mem_6_source = 2'h0; // @[AsyncQueue.scala:211:22]
wire [1:0] nodeOut_b_mem_7_source = 2'h0; // @[AsyncQueue.scala:211:22]
wire [3:0] auto_out_b_mem_0_size = 4'h6; // @[AsyncQueue.scala:211:22]
wire [3:0] auto_out_b_mem_1_size = 4'h6; // @[AsyncQueue.scala:211:22]
wire [3:0] auto_out_b_mem_2_size = 4'h6; // @[AsyncQueue.scala:211:22]
wire [3:0] auto_out_b_mem_3_size = 4'h6; // @[AsyncQueue.scala:211:22]
wire [3:0] auto_out_b_mem_4_size = 4'h6; // @[AsyncQueue.scala:211:22]
wire [3:0] auto_out_b_mem_5_size = 4'h6; // @[AsyncQueue.scala:211:22]
wire [3:0] auto_out_b_mem_6_size = 4'h6; // @[AsyncQueue.scala:211:22]
wire [3:0] auto_out_b_mem_7_size = 4'h6; // @[AsyncQueue.scala:211:22]
wire [3:0] nodeOut_b_mem_0_size = 4'h6; // @[AsyncQueue.scala:211:22]
wire [3:0] nodeOut_b_mem_1_size = 4'h6; // @[AsyncQueue.scala:211:22]
wire [3:0] nodeOut_b_mem_2_size = 4'h6; // @[AsyncQueue.scala:211:22]
wire [3:0] nodeOut_b_mem_3_size = 4'h6; // @[AsyncQueue.scala:211:22]
wire [3:0] nodeOut_b_mem_4_size = 4'h6; // @[AsyncQueue.scala:211:22]
wire [3:0] nodeOut_b_mem_5_size = 4'h6; // @[AsyncQueue.scala:211:22]
wire [3:0] nodeOut_b_mem_6_size = 4'h6; // @[AsyncQueue.scala:211:22]
wire [3:0] nodeOut_b_mem_7_size = 4'h6; // @[AsyncQueue.scala:211:22]
wire [2:0] auto_out_b_mem_0_opcode = 3'h6; // @[AsyncQueue.scala:211:22]
wire [2:0] auto_out_b_mem_1_opcode = 3'h6; // @[AsyncQueue.scala:211:22]
wire [2:0] auto_out_b_mem_2_opcode = 3'h6; // @[AsyncQueue.scala:211:22]
wire [2:0] auto_out_b_mem_3_opcode = 3'h6; // @[AsyncQueue.scala:211:22]
wire [2:0] auto_out_b_mem_4_opcode = 3'h6; // @[AsyncQueue.scala:211:22]
wire [2:0] auto_out_b_mem_5_opcode = 3'h6; // @[AsyncQueue.scala:211:22]
wire [2:0] auto_out_b_mem_6_opcode = 3'h6; // @[AsyncQueue.scala:211:22]
wire [2:0] auto_out_b_mem_7_opcode = 3'h6; // @[AsyncQueue.scala:211:22]
wire [2:0] nodeOut_b_mem_0_opcode = 3'h6; // @[AsyncQueue.scala:211:22]
wire [2:0] nodeOut_b_mem_1_opcode = 3'h6; // @[AsyncQueue.scala:211:22]
wire [2:0] nodeOut_b_mem_2_opcode = 3'h6; // @[AsyncQueue.scala:211:22]
wire [2:0] nodeOut_b_mem_3_opcode = 3'h6; // @[AsyncQueue.scala:211:22]
wire [2:0] nodeOut_b_mem_4_opcode = 3'h6; // @[AsyncQueue.scala:211:22]
wire [2:0] nodeOut_b_mem_5_opcode = 3'h6; // @[AsyncQueue.scala:211:22]
wire [2:0] nodeOut_b_mem_6_opcode = 3'h6; // @[AsyncQueue.scala:211:22]
wire [2:0] nodeOut_b_mem_7_opcode = 3'h6; // @[AsyncQueue.scala:211:22]
wire auto_in_a_bits_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_in_c_bits_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_a_mem_0_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_a_mem_1_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_a_mem_2_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_a_mem_3_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_a_mem_4_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_a_mem_5_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_a_mem_6_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_a_mem_7_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_b_mem_0_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_b_mem_1_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_b_mem_2_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_b_mem_3_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_b_mem_4_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_b_mem_5_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_b_mem_6_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_b_mem_7_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_c_mem_0_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_c_mem_1_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_c_mem_2_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_c_mem_3_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_c_mem_4_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_c_mem_5_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_c_mem_6_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_c_mem_7_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9]
wire nodeIn_a_ready; // @[MixedNode.scala:551:17]
wire nodeIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire nodeIn_c_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire nodeOut_a_mem_0_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_a_mem_1_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_a_mem_2_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_a_mem_3_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_a_mem_4_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_a_mem_5_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_a_mem_6_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_a_mem_7_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_b_mem_0_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_b_mem_1_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_b_mem_2_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_b_mem_3_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_b_mem_4_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_b_mem_5_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_b_mem_6_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_b_mem_7_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_c_mem_0_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_c_mem_1_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_c_mem_2_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_c_mem_3_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_c_mem_4_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_c_mem_5_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_c_mem_6_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_c_mem_7_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire nodeIn_a_valid = auto_in_a_valid_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[AsyncCrossing.scala:23:9]
wire [3:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[AsyncCrossing.scala:23:9]
wire [1:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[AsyncCrossing.scala:23:9]
wire [31:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[AsyncCrossing.scala:23:9]
wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[AsyncCrossing.scala:23:9]
wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[AsyncCrossing.scala:23:9]
wire nodeIn_b_ready = auto_in_b_ready_0; // @[AsyncCrossing.scala:23:9]
wire nodeIn_b_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_b_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_b_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_b_bits_size; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_b_bits_source; // @[MixedNode.scala:551:17]
wire [31:0] nodeIn_b_bits_address; // @[MixedNode.scala:551:17]
wire [7:0] nodeIn_b_bits_mask; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_b_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_b_bits_corrupt; // @[MixedNode.scala:551:17]
wire nodeIn_c_ready; // @[MixedNode.scala:551:17]
wire nodeIn_c_valid = auto_in_c_valid_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] nodeIn_c_bits_opcode = auto_in_c_bits_opcode_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] nodeIn_c_bits_param = auto_in_c_bits_param_0; // @[AsyncCrossing.scala:23:9]
wire [3:0] nodeIn_c_bits_size = auto_in_c_bits_size_0; // @[AsyncCrossing.scala:23:9]
wire [1:0] nodeIn_c_bits_source = auto_in_c_bits_source_0; // @[AsyncCrossing.scala:23:9]
wire [31:0] nodeIn_c_bits_address = auto_in_c_bits_address_0; // @[AsyncCrossing.scala:23:9]
wire [63:0] nodeIn_c_bits_data = auto_in_c_bits_data_0; // @[AsyncCrossing.scala:23:9]
wire nodeIn_d_ready = auto_in_d_ready_0; // @[AsyncCrossing.scala:23:9]
wire nodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire nodeIn_e_ready; // @[MixedNode.scala:551:17]
wire nodeIn_e_valid = auto_in_e_valid_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] nodeIn_e_bits_sink = auto_in_e_bits_sink_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] nodeOut_a_mem_0_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_mem_0_param; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_a_mem_0_size; // @[MixedNode.scala:542:17]
wire [1:0] nodeOut_a_mem_0_source; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_a_mem_0_address; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_a_mem_0_mask; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_a_mem_0_data; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_mem_1_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_mem_1_param; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_a_mem_1_size; // @[MixedNode.scala:542:17]
wire [1:0] nodeOut_a_mem_1_source; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_a_mem_1_address; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_a_mem_1_mask; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_a_mem_1_data; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_mem_2_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_mem_2_param; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_a_mem_2_size; // @[MixedNode.scala:542:17]
wire [1:0] nodeOut_a_mem_2_source; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_a_mem_2_address; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_a_mem_2_mask; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_a_mem_2_data; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_mem_3_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_mem_3_param; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_a_mem_3_size; // @[MixedNode.scala:542:17]
wire [1:0] nodeOut_a_mem_3_source; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_a_mem_3_address; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_a_mem_3_mask; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_a_mem_3_data; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_mem_4_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_mem_4_param; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_a_mem_4_size; // @[MixedNode.scala:542:17]
wire [1:0] nodeOut_a_mem_4_source; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_a_mem_4_address; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_a_mem_4_mask; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_a_mem_4_data; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_mem_5_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_mem_5_param; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_a_mem_5_size; // @[MixedNode.scala:542:17]
wire [1:0] nodeOut_a_mem_5_source; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_a_mem_5_address; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_a_mem_5_mask; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_a_mem_5_data; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_mem_6_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_mem_6_param; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_a_mem_6_size; // @[MixedNode.scala:542:17]
wire [1:0] nodeOut_a_mem_6_source; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_a_mem_6_address; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_a_mem_6_mask; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_a_mem_6_data; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_mem_7_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_mem_7_param; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_a_mem_7_size; // @[MixedNode.scala:542:17]
wire [1:0] nodeOut_a_mem_7_source; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_a_mem_7_address; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_a_mem_7_mask; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_a_mem_7_data; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_a_ridx = auto_out_a_ridx_0; // @[AsyncCrossing.scala:23:9]
wire [3:0] nodeOut_a_widx; // @[MixedNode.scala:542:17]
wire nodeOut_a_safe_ridx_valid = auto_out_a_safe_ridx_valid_0; // @[AsyncCrossing.scala:23:9]
wire nodeOut_a_safe_widx_valid; // @[MixedNode.scala:542:17]
wire nodeOut_a_safe_source_reset_n; // @[MixedNode.scala:542:17]
wire nodeOut_a_safe_sink_reset_n = auto_out_a_safe_sink_reset_n_0; // @[AsyncCrossing.scala:23:9]
wire [1:0] nodeOut_b_mem_0_param = auto_out_b_mem_0_param_0; // @[AsyncCrossing.scala:23:9]
wire [31:0] nodeOut_b_mem_0_address = auto_out_b_mem_0_address_0; // @[AsyncCrossing.scala:23:9]
wire [1:0] nodeOut_b_mem_1_param = auto_out_b_mem_1_param_0; // @[AsyncCrossing.scala:23:9]
wire [31:0] nodeOut_b_mem_1_address = auto_out_b_mem_1_address_0; // @[AsyncCrossing.scala:23:9]
wire [1:0] nodeOut_b_mem_2_param = auto_out_b_mem_2_param_0; // @[AsyncCrossing.scala:23:9]
wire [31:0] nodeOut_b_mem_2_address = auto_out_b_mem_2_address_0; // @[AsyncCrossing.scala:23:9]
wire [1:0] nodeOut_b_mem_3_param = auto_out_b_mem_3_param_0; // @[AsyncCrossing.scala:23:9]
wire [31:0] nodeOut_b_mem_3_address = auto_out_b_mem_3_address_0; // @[AsyncCrossing.scala:23:9]
wire [1:0] nodeOut_b_mem_4_param = auto_out_b_mem_4_param_0; // @[AsyncCrossing.scala:23:9]
wire [31:0] nodeOut_b_mem_4_address = auto_out_b_mem_4_address_0; // @[AsyncCrossing.scala:23:9]
wire [1:0] nodeOut_b_mem_5_param = auto_out_b_mem_5_param_0; // @[AsyncCrossing.scala:23:9]
wire [31:0] nodeOut_b_mem_5_address = auto_out_b_mem_5_address_0; // @[AsyncCrossing.scala:23:9]
wire [1:0] nodeOut_b_mem_6_param = auto_out_b_mem_6_param_0; // @[AsyncCrossing.scala:23:9]
wire [31:0] nodeOut_b_mem_6_address = auto_out_b_mem_6_address_0; // @[AsyncCrossing.scala:23:9]
wire [1:0] nodeOut_b_mem_7_param = auto_out_b_mem_7_param_0; // @[AsyncCrossing.scala:23:9]
wire [31:0] nodeOut_b_mem_7_address = auto_out_b_mem_7_address_0; // @[AsyncCrossing.scala:23:9]
wire [3:0] nodeOut_b_ridx; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_b_widx = auto_out_b_widx_0; // @[AsyncCrossing.scala:23:9]
wire nodeOut_b_safe_ridx_valid; // @[MixedNode.scala:542:17]
wire nodeOut_b_safe_widx_valid = auto_out_b_safe_widx_valid_0; // @[AsyncCrossing.scala:23:9]
wire nodeOut_b_safe_source_reset_n = auto_out_b_safe_source_reset_n_0; // @[AsyncCrossing.scala:23:9]
wire nodeOut_b_safe_sink_reset_n; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_c_mem_0_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_c_mem_0_param; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_c_mem_0_size; // @[MixedNode.scala:542:17]
wire [1:0] nodeOut_c_mem_0_source; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_c_mem_0_address; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_c_mem_0_data; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_c_mem_1_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_c_mem_1_param; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_c_mem_1_size; // @[MixedNode.scala:542:17]
wire [1:0] nodeOut_c_mem_1_source; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_c_mem_1_address; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_c_mem_1_data; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_c_mem_2_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_c_mem_2_param; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_c_mem_2_size; // @[MixedNode.scala:542:17]
wire [1:0] nodeOut_c_mem_2_source; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_c_mem_2_address; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_c_mem_2_data; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_c_mem_3_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_c_mem_3_param; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_c_mem_3_size; // @[MixedNode.scala:542:17]
wire [1:0] nodeOut_c_mem_3_source; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_c_mem_3_address; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_c_mem_3_data; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_c_mem_4_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_c_mem_4_param; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_c_mem_4_size; // @[MixedNode.scala:542:17]
wire [1:0] nodeOut_c_mem_4_source; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_c_mem_4_address; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_c_mem_4_data; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_c_mem_5_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_c_mem_5_param; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_c_mem_5_size; // @[MixedNode.scala:542:17]
wire [1:0] nodeOut_c_mem_5_source; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_c_mem_5_address; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_c_mem_5_data; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_c_mem_6_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_c_mem_6_param; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_c_mem_6_size; // @[MixedNode.scala:542:17]
wire [1:0] nodeOut_c_mem_6_source; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_c_mem_6_address; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_c_mem_6_data; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_c_mem_7_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_c_mem_7_param; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_c_mem_7_size; // @[MixedNode.scala:542:17]
wire [1:0] nodeOut_c_mem_7_source; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_c_mem_7_address; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_c_mem_7_data; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_c_ridx = auto_out_c_ridx_0; // @[AsyncCrossing.scala:23:9]
wire [3:0] nodeOut_c_widx; // @[MixedNode.scala:542:17]
wire nodeOut_c_safe_ridx_valid = auto_out_c_safe_ridx_valid_0; // @[AsyncCrossing.scala:23:9]
wire nodeOut_c_safe_widx_valid; // @[MixedNode.scala:542:17]
wire nodeOut_c_safe_source_reset_n; // @[MixedNode.scala:542:17]
wire nodeOut_c_safe_sink_reset_n = auto_out_c_safe_sink_reset_n_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] nodeOut_d_mem_0_opcode = auto_out_d_mem_0_opcode_0; // @[AsyncCrossing.scala:23:9]
wire [1:0] nodeOut_d_mem_0_param = auto_out_d_mem_0_param_0; // @[AsyncCrossing.scala:23:9]
wire [3:0] nodeOut_d_mem_0_size = auto_out_d_mem_0_size_0; // @[AsyncCrossing.scala:23:9]
wire [1:0] nodeOut_d_mem_0_source = auto_out_d_mem_0_source_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] nodeOut_d_mem_0_sink = auto_out_d_mem_0_sink_0; // @[AsyncCrossing.scala:23:9]
wire nodeOut_d_mem_0_denied = auto_out_d_mem_0_denied_0; // @[AsyncCrossing.scala:23:9]
wire [63:0] nodeOut_d_mem_0_data = auto_out_d_mem_0_data_0; // @[AsyncCrossing.scala:23:9]
wire nodeOut_d_mem_0_corrupt = auto_out_d_mem_0_corrupt_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] nodeOut_d_mem_1_opcode = auto_out_d_mem_1_opcode_0; // @[AsyncCrossing.scala:23:9]
wire [1:0] nodeOut_d_mem_1_param = auto_out_d_mem_1_param_0; // @[AsyncCrossing.scala:23:9]
wire [3:0] nodeOut_d_mem_1_size = auto_out_d_mem_1_size_0; // @[AsyncCrossing.scala:23:9]
wire [1:0] nodeOut_d_mem_1_source = auto_out_d_mem_1_source_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] nodeOut_d_mem_1_sink = auto_out_d_mem_1_sink_0; // @[AsyncCrossing.scala:23:9]
wire nodeOut_d_mem_1_denied = auto_out_d_mem_1_denied_0; // @[AsyncCrossing.scala:23:9]
wire [63:0] nodeOut_d_mem_1_data = auto_out_d_mem_1_data_0; // @[AsyncCrossing.scala:23:9]
wire nodeOut_d_mem_1_corrupt = auto_out_d_mem_1_corrupt_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] nodeOut_d_mem_2_opcode = auto_out_d_mem_2_opcode_0; // @[AsyncCrossing.scala:23:9]
wire [1:0] nodeOut_d_mem_2_param = auto_out_d_mem_2_param_0; // @[AsyncCrossing.scala:23:9]
wire [3:0] nodeOut_d_mem_2_size = auto_out_d_mem_2_size_0; // @[AsyncCrossing.scala:23:9]
wire [1:0] nodeOut_d_mem_2_source = auto_out_d_mem_2_source_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] nodeOut_d_mem_2_sink = auto_out_d_mem_2_sink_0; // @[AsyncCrossing.scala:23:9]
wire nodeOut_d_mem_2_denied = auto_out_d_mem_2_denied_0; // @[AsyncCrossing.scala:23:9]
wire [63:0] nodeOut_d_mem_2_data = auto_out_d_mem_2_data_0; // @[AsyncCrossing.scala:23:9]
wire nodeOut_d_mem_2_corrupt = auto_out_d_mem_2_corrupt_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] nodeOut_d_mem_3_opcode = auto_out_d_mem_3_opcode_0; // @[AsyncCrossing.scala:23:9]
wire [1:0] nodeOut_d_mem_3_param = auto_out_d_mem_3_param_0; // @[AsyncCrossing.scala:23:9]
wire [3:0] nodeOut_d_mem_3_size = auto_out_d_mem_3_size_0; // @[AsyncCrossing.scala:23:9]
wire [1:0] nodeOut_d_mem_3_source = auto_out_d_mem_3_source_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] nodeOut_d_mem_3_sink = auto_out_d_mem_3_sink_0; // @[AsyncCrossing.scala:23:9]
wire nodeOut_d_mem_3_denied = auto_out_d_mem_3_denied_0; // @[AsyncCrossing.scala:23:9]
wire [63:0] nodeOut_d_mem_3_data = auto_out_d_mem_3_data_0; // @[AsyncCrossing.scala:23:9]
wire nodeOut_d_mem_3_corrupt = auto_out_d_mem_3_corrupt_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] nodeOut_d_mem_4_opcode = auto_out_d_mem_4_opcode_0; // @[AsyncCrossing.scala:23:9]
wire [1:0] nodeOut_d_mem_4_param = auto_out_d_mem_4_param_0; // @[AsyncCrossing.scala:23:9]
wire [3:0] nodeOut_d_mem_4_size = auto_out_d_mem_4_size_0; // @[AsyncCrossing.scala:23:9]
wire [1:0] nodeOut_d_mem_4_source = auto_out_d_mem_4_source_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] nodeOut_d_mem_4_sink = auto_out_d_mem_4_sink_0; // @[AsyncCrossing.scala:23:9]
wire nodeOut_d_mem_4_denied = auto_out_d_mem_4_denied_0; // @[AsyncCrossing.scala:23:9]
wire [63:0] nodeOut_d_mem_4_data = auto_out_d_mem_4_data_0; // @[AsyncCrossing.scala:23:9]
wire nodeOut_d_mem_4_corrupt = auto_out_d_mem_4_corrupt_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] nodeOut_d_mem_5_opcode = auto_out_d_mem_5_opcode_0; // @[AsyncCrossing.scala:23:9]
wire [1:0] nodeOut_d_mem_5_param = auto_out_d_mem_5_param_0; // @[AsyncCrossing.scala:23:9]
wire [3:0] nodeOut_d_mem_5_size = auto_out_d_mem_5_size_0; // @[AsyncCrossing.scala:23:9]
wire [1:0] nodeOut_d_mem_5_source = auto_out_d_mem_5_source_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] nodeOut_d_mem_5_sink = auto_out_d_mem_5_sink_0; // @[AsyncCrossing.scala:23:9]
wire nodeOut_d_mem_5_denied = auto_out_d_mem_5_denied_0; // @[AsyncCrossing.scala:23:9]
wire [63:0] nodeOut_d_mem_5_data = auto_out_d_mem_5_data_0; // @[AsyncCrossing.scala:23:9]
wire nodeOut_d_mem_5_corrupt = auto_out_d_mem_5_corrupt_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] nodeOut_d_mem_6_opcode = auto_out_d_mem_6_opcode_0; // @[AsyncCrossing.scala:23:9]
wire [1:0] nodeOut_d_mem_6_param = auto_out_d_mem_6_param_0; // @[AsyncCrossing.scala:23:9]
wire [3:0] nodeOut_d_mem_6_size = auto_out_d_mem_6_size_0; // @[AsyncCrossing.scala:23:9]
wire [1:0] nodeOut_d_mem_6_source = auto_out_d_mem_6_source_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] nodeOut_d_mem_6_sink = auto_out_d_mem_6_sink_0; // @[AsyncCrossing.scala:23:9]
wire nodeOut_d_mem_6_denied = auto_out_d_mem_6_denied_0; // @[AsyncCrossing.scala:23:9]
wire [63:0] nodeOut_d_mem_6_data = auto_out_d_mem_6_data_0; // @[AsyncCrossing.scala:23:9]
wire nodeOut_d_mem_6_corrupt = auto_out_d_mem_6_corrupt_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] nodeOut_d_mem_7_opcode = auto_out_d_mem_7_opcode_0; // @[AsyncCrossing.scala:23:9]
wire [1:0] nodeOut_d_mem_7_param = auto_out_d_mem_7_param_0; // @[AsyncCrossing.scala:23:9]
wire [3:0] nodeOut_d_mem_7_size = auto_out_d_mem_7_size_0; // @[AsyncCrossing.scala:23:9]
wire [1:0] nodeOut_d_mem_7_source = auto_out_d_mem_7_source_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] nodeOut_d_mem_7_sink = auto_out_d_mem_7_sink_0; // @[AsyncCrossing.scala:23:9]
wire nodeOut_d_mem_7_denied = auto_out_d_mem_7_denied_0; // @[AsyncCrossing.scala:23:9]
wire [63:0] nodeOut_d_mem_7_data = auto_out_d_mem_7_data_0; // @[AsyncCrossing.scala:23:9]
wire nodeOut_d_mem_7_corrupt = auto_out_d_mem_7_corrupt_0; // @[AsyncCrossing.scala:23:9]
wire [3:0] nodeOut_d_ridx; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_d_widx = auto_out_d_widx_0; // @[AsyncCrossing.scala:23:9]
wire nodeOut_d_safe_ridx_valid; // @[MixedNode.scala:542:17]
wire nodeOut_d_safe_widx_valid = auto_out_d_safe_widx_valid_0; // @[AsyncCrossing.scala:23:9]
wire nodeOut_d_safe_source_reset_n = auto_out_d_safe_source_reset_n_0; // @[AsyncCrossing.scala:23:9]
wire nodeOut_d_safe_sink_reset_n; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_e_mem_0_sink; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_e_mem_1_sink; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_e_mem_2_sink; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_e_mem_3_sink; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_e_mem_4_sink; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_e_mem_5_sink; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_e_mem_6_sink; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_e_mem_7_sink; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_e_ridx = auto_out_e_ridx_0; // @[AsyncCrossing.scala:23:9]
wire [3:0] nodeOut_e_widx; // @[MixedNode.scala:542:17]
wire nodeOut_e_safe_ridx_valid = auto_out_e_safe_ridx_valid_0; // @[AsyncCrossing.scala:23:9]
wire nodeOut_e_safe_widx_valid; // @[MixedNode.scala:542:17]
wire nodeOut_e_safe_source_reset_n; // @[MixedNode.scala:542:17]
wire nodeOut_e_safe_sink_reset_n = auto_out_e_safe_sink_reset_n_0; // @[AsyncCrossing.scala:23:9]
wire auto_in_a_ready_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_in_b_bits_opcode_0; // @[AsyncCrossing.scala:23:9]
wire [1:0] auto_in_b_bits_param_0; // @[AsyncCrossing.scala:23:9]
wire [3:0] auto_in_b_bits_size_0; // @[AsyncCrossing.scala:23:9]
wire [1:0] auto_in_b_bits_source_0; // @[AsyncCrossing.scala:23:9]
wire [31:0] auto_in_b_bits_address_0; // @[AsyncCrossing.scala:23:9]
wire [7:0] auto_in_b_bits_mask_0; // @[AsyncCrossing.scala:23:9]
wire [63:0] auto_in_b_bits_data_0; // @[AsyncCrossing.scala:23:9]
wire auto_in_b_bits_corrupt_0; // @[AsyncCrossing.scala:23:9]
wire auto_in_b_valid_0; // @[AsyncCrossing.scala:23:9]
wire auto_in_c_ready_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_in_d_bits_opcode_0; // @[AsyncCrossing.scala:23:9]
wire [1:0] auto_in_d_bits_param_0; // @[AsyncCrossing.scala:23:9]
wire [3:0] auto_in_d_bits_size_0; // @[AsyncCrossing.scala:23:9]
wire [1:0] auto_in_d_bits_source_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_in_d_bits_sink_0; // @[AsyncCrossing.scala:23:9]
wire auto_in_d_bits_denied_0; // @[AsyncCrossing.scala:23:9]
wire [63:0] auto_in_d_bits_data_0; // @[AsyncCrossing.scala:23:9]
wire auto_in_d_bits_corrupt_0; // @[AsyncCrossing.scala:23:9]
wire auto_in_d_valid_0; // @[AsyncCrossing.scala:23:9]
wire auto_in_e_ready_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_a_mem_0_opcode_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_a_mem_0_param_0; // @[AsyncCrossing.scala:23:9]
wire [3:0] auto_out_a_mem_0_size_0; // @[AsyncCrossing.scala:23:9]
wire [1:0] auto_out_a_mem_0_source_0; // @[AsyncCrossing.scala:23:9]
wire [31:0] auto_out_a_mem_0_address_0; // @[AsyncCrossing.scala:23:9]
wire [7:0] auto_out_a_mem_0_mask_0; // @[AsyncCrossing.scala:23:9]
wire [63:0] auto_out_a_mem_0_data_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_a_mem_1_opcode_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_a_mem_1_param_0; // @[AsyncCrossing.scala:23:9]
wire [3:0] auto_out_a_mem_1_size_0; // @[AsyncCrossing.scala:23:9]
wire [1:0] auto_out_a_mem_1_source_0; // @[AsyncCrossing.scala:23:9]
wire [31:0] auto_out_a_mem_1_address_0; // @[AsyncCrossing.scala:23:9]
wire [7:0] auto_out_a_mem_1_mask_0; // @[AsyncCrossing.scala:23:9]
wire [63:0] auto_out_a_mem_1_data_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_a_mem_2_opcode_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_a_mem_2_param_0; // @[AsyncCrossing.scala:23:9]
wire [3:0] auto_out_a_mem_2_size_0; // @[AsyncCrossing.scala:23:9]
wire [1:0] auto_out_a_mem_2_source_0; // @[AsyncCrossing.scala:23:9]
wire [31:0] auto_out_a_mem_2_address_0; // @[AsyncCrossing.scala:23:9]
wire [7:0] auto_out_a_mem_2_mask_0; // @[AsyncCrossing.scala:23:9]
wire [63:0] auto_out_a_mem_2_data_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_a_mem_3_opcode_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_a_mem_3_param_0; // @[AsyncCrossing.scala:23:9]
wire [3:0] auto_out_a_mem_3_size_0; // @[AsyncCrossing.scala:23:9]
wire [1:0] auto_out_a_mem_3_source_0; // @[AsyncCrossing.scala:23:9]
wire [31:0] auto_out_a_mem_3_address_0; // @[AsyncCrossing.scala:23:9]
wire [7:0] auto_out_a_mem_3_mask_0; // @[AsyncCrossing.scala:23:9]
wire [63:0] auto_out_a_mem_3_data_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_a_mem_4_opcode_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_a_mem_4_param_0; // @[AsyncCrossing.scala:23:9]
wire [3:0] auto_out_a_mem_4_size_0; // @[AsyncCrossing.scala:23:9]
wire [1:0] auto_out_a_mem_4_source_0; // @[AsyncCrossing.scala:23:9]
wire [31:0] auto_out_a_mem_4_address_0; // @[AsyncCrossing.scala:23:9]
wire [7:0] auto_out_a_mem_4_mask_0; // @[AsyncCrossing.scala:23:9]
wire [63:0] auto_out_a_mem_4_data_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_a_mem_5_opcode_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_a_mem_5_param_0; // @[AsyncCrossing.scala:23:9]
wire [3:0] auto_out_a_mem_5_size_0; // @[AsyncCrossing.scala:23:9]
wire [1:0] auto_out_a_mem_5_source_0; // @[AsyncCrossing.scala:23:9]
wire [31:0] auto_out_a_mem_5_address_0; // @[AsyncCrossing.scala:23:9]
wire [7:0] auto_out_a_mem_5_mask_0; // @[AsyncCrossing.scala:23:9]
wire [63:0] auto_out_a_mem_5_data_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_a_mem_6_opcode_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_a_mem_6_param_0; // @[AsyncCrossing.scala:23:9]
wire [3:0] auto_out_a_mem_6_size_0; // @[AsyncCrossing.scala:23:9]
wire [1:0] auto_out_a_mem_6_source_0; // @[AsyncCrossing.scala:23:9]
wire [31:0] auto_out_a_mem_6_address_0; // @[AsyncCrossing.scala:23:9]
wire [7:0] auto_out_a_mem_6_mask_0; // @[AsyncCrossing.scala:23:9]
wire [63:0] auto_out_a_mem_6_data_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_a_mem_7_opcode_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_a_mem_7_param_0; // @[AsyncCrossing.scala:23:9]
wire [3:0] auto_out_a_mem_7_size_0; // @[AsyncCrossing.scala:23:9]
wire [1:0] auto_out_a_mem_7_source_0; // @[AsyncCrossing.scala:23:9]
wire [31:0] auto_out_a_mem_7_address_0; // @[AsyncCrossing.scala:23:9]
wire [7:0] auto_out_a_mem_7_mask_0; // @[AsyncCrossing.scala:23:9]
wire [63:0] auto_out_a_mem_7_data_0; // @[AsyncCrossing.scala:23:9]
wire auto_out_a_safe_widx_valid_0; // @[AsyncCrossing.scala:23:9]
wire auto_out_a_safe_source_reset_n_0; // @[AsyncCrossing.scala:23:9]
wire [3:0] auto_out_a_widx_0; // @[AsyncCrossing.scala:23:9]
wire auto_out_b_safe_ridx_valid_0; // @[AsyncCrossing.scala:23:9]
wire auto_out_b_safe_sink_reset_n_0; // @[AsyncCrossing.scala:23:9]
wire [3:0] auto_out_b_ridx_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_c_mem_0_opcode_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_c_mem_0_param_0; // @[AsyncCrossing.scala:23:9]
wire [3:0] auto_out_c_mem_0_size_0; // @[AsyncCrossing.scala:23:9]
wire [1:0] auto_out_c_mem_0_source_0; // @[AsyncCrossing.scala:23:9]
wire [31:0] auto_out_c_mem_0_address_0; // @[AsyncCrossing.scala:23:9]
wire [63:0] auto_out_c_mem_0_data_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_c_mem_1_opcode_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_c_mem_1_param_0; // @[AsyncCrossing.scala:23:9]
wire [3:0] auto_out_c_mem_1_size_0; // @[AsyncCrossing.scala:23:9]
wire [1:0] auto_out_c_mem_1_source_0; // @[AsyncCrossing.scala:23:9]
wire [31:0] auto_out_c_mem_1_address_0; // @[AsyncCrossing.scala:23:9]
wire [63:0] auto_out_c_mem_1_data_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_c_mem_2_opcode_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_c_mem_2_param_0; // @[AsyncCrossing.scala:23:9]
wire [3:0] auto_out_c_mem_2_size_0; // @[AsyncCrossing.scala:23:9]
wire [1:0] auto_out_c_mem_2_source_0; // @[AsyncCrossing.scala:23:9]
wire [31:0] auto_out_c_mem_2_address_0; // @[AsyncCrossing.scala:23:9]
wire [63:0] auto_out_c_mem_2_data_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_c_mem_3_opcode_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_c_mem_3_param_0; // @[AsyncCrossing.scala:23:9]
wire [3:0] auto_out_c_mem_3_size_0; // @[AsyncCrossing.scala:23:9]
wire [1:0] auto_out_c_mem_3_source_0; // @[AsyncCrossing.scala:23:9]
wire [31:0] auto_out_c_mem_3_address_0; // @[AsyncCrossing.scala:23:9]
wire [63:0] auto_out_c_mem_3_data_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_c_mem_4_opcode_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_c_mem_4_param_0; // @[AsyncCrossing.scala:23:9]
wire [3:0] auto_out_c_mem_4_size_0; // @[AsyncCrossing.scala:23:9]
wire [1:0] auto_out_c_mem_4_source_0; // @[AsyncCrossing.scala:23:9]
wire [31:0] auto_out_c_mem_4_address_0; // @[AsyncCrossing.scala:23:9]
wire [63:0] auto_out_c_mem_4_data_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_c_mem_5_opcode_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_c_mem_5_param_0; // @[AsyncCrossing.scala:23:9]
wire [3:0] auto_out_c_mem_5_size_0; // @[AsyncCrossing.scala:23:9]
wire [1:0] auto_out_c_mem_5_source_0; // @[AsyncCrossing.scala:23:9]
wire [31:0] auto_out_c_mem_5_address_0; // @[AsyncCrossing.scala:23:9]
wire [63:0] auto_out_c_mem_5_data_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_c_mem_6_opcode_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_c_mem_6_param_0; // @[AsyncCrossing.scala:23:9]
wire [3:0] auto_out_c_mem_6_size_0; // @[AsyncCrossing.scala:23:9]
wire [1:0] auto_out_c_mem_6_source_0; // @[AsyncCrossing.scala:23:9]
wire [31:0] auto_out_c_mem_6_address_0; // @[AsyncCrossing.scala:23:9]
wire [63:0] auto_out_c_mem_6_data_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_c_mem_7_opcode_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_c_mem_7_param_0; // @[AsyncCrossing.scala:23:9]
wire [3:0] auto_out_c_mem_7_size_0; // @[AsyncCrossing.scala:23:9]
wire [1:0] auto_out_c_mem_7_source_0; // @[AsyncCrossing.scala:23:9]
wire [31:0] auto_out_c_mem_7_address_0; // @[AsyncCrossing.scala:23:9]
wire [63:0] auto_out_c_mem_7_data_0; // @[AsyncCrossing.scala:23:9]
wire auto_out_c_safe_widx_valid_0; // @[AsyncCrossing.scala:23:9]
wire auto_out_c_safe_source_reset_n_0; // @[AsyncCrossing.scala:23:9]
wire [3:0] auto_out_c_widx_0; // @[AsyncCrossing.scala:23:9]
wire auto_out_d_safe_ridx_valid_0; // @[AsyncCrossing.scala:23:9]
wire auto_out_d_safe_sink_reset_n_0; // @[AsyncCrossing.scala:23:9]
wire [3:0] auto_out_d_ridx_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_e_mem_0_sink_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_e_mem_1_sink_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_e_mem_2_sink_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_e_mem_3_sink_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_e_mem_4_sink_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_e_mem_5_sink_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_e_mem_6_sink_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_e_mem_7_sink_0; // @[AsyncCrossing.scala:23:9]
wire auto_out_e_safe_widx_valid_0; // @[AsyncCrossing.scala:23:9]
wire auto_out_e_safe_source_reset_n_0; // @[AsyncCrossing.scala:23:9]
wire [3:0] auto_out_e_widx_0; // @[AsyncCrossing.scala:23:9]
assign auto_in_a_ready_0 = nodeIn_a_ready; // @[AsyncCrossing.scala:23:9]
assign auto_in_b_valid_0 = nodeIn_b_valid; // @[AsyncCrossing.scala:23:9]
assign auto_in_b_bits_opcode_0 = nodeIn_b_bits_opcode; // @[AsyncCrossing.scala:23:9]
assign auto_in_b_bits_param_0 = nodeIn_b_bits_param; // @[AsyncCrossing.scala:23:9]
assign auto_in_b_bits_size_0 = nodeIn_b_bits_size; // @[AsyncCrossing.scala:23:9]
assign auto_in_b_bits_source_0 = nodeIn_b_bits_source; // @[AsyncCrossing.scala:23:9]
assign auto_in_b_bits_address_0 = nodeIn_b_bits_address; // @[AsyncCrossing.scala:23:9]
assign auto_in_b_bits_mask_0 = nodeIn_b_bits_mask; // @[AsyncCrossing.scala:23:9]
assign auto_in_b_bits_data_0 = nodeIn_b_bits_data; // @[AsyncCrossing.scala:23:9]
assign auto_in_b_bits_corrupt_0 = nodeIn_b_bits_corrupt; // @[AsyncCrossing.scala:23:9]
assign auto_in_c_ready_0 = nodeIn_c_ready; // @[AsyncCrossing.scala:23:9]
assign auto_in_d_valid_0 = nodeIn_d_valid; // @[AsyncCrossing.scala:23:9]
assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[AsyncCrossing.scala:23:9]
assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[AsyncCrossing.scala:23:9]
assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[AsyncCrossing.scala:23:9]
assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[AsyncCrossing.scala:23:9]
assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[AsyncCrossing.scala:23:9]
assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[AsyncCrossing.scala:23:9]
assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[AsyncCrossing.scala:23:9]
assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[AsyncCrossing.scala:23:9]
assign auto_in_e_ready_0 = nodeIn_e_ready; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_0_opcode_0 = nodeOut_a_mem_0_opcode; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_0_param_0 = nodeOut_a_mem_0_param; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_0_size_0 = nodeOut_a_mem_0_size; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_0_source_0 = nodeOut_a_mem_0_source; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_0_address_0 = nodeOut_a_mem_0_address; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_0_mask_0 = nodeOut_a_mem_0_mask; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_0_data_0 = nodeOut_a_mem_0_data; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_1_opcode_0 = nodeOut_a_mem_1_opcode; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_1_param_0 = nodeOut_a_mem_1_param; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_1_size_0 = nodeOut_a_mem_1_size; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_1_source_0 = nodeOut_a_mem_1_source; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_1_address_0 = nodeOut_a_mem_1_address; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_1_mask_0 = nodeOut_a_mem_1_mask; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_1_data_0 = nodeOut_a_mem_1_data; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_2_opcode_0 = nodeOut_a_mem_2_opcode; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_2_param_0 = nodeOut_a_mem_2_param; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_2_size_0 = nodeOut_a_mem_2_size; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_2_source_0 = nodeOut_a_mem_2_source; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_2_address_0 = nodeOut_a_mem_2_address; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_2_mask_0 = nodeOut_a_mem_2_mask; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_2_data_0 = nodeOut_a_mem_2_data; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_3_opcode_0 = nodeOut_a_mem_3_opcode; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_3_param_0 = nodeOut_a_mem_3_param; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_3_size_0 = nodeOut_a_mem_3_size; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_3_source_0 = nodeOut_a_mem_3_source; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_3_address_0 = nodeOut_a_mem_3_address; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_3_mask_0 = nodeOut_a_mem_3_mask; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_3_data_0 = nodeOut_a_mem_3_data; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_4_opcode_0 = nodeOut_a_mem_4_opcode; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_4_param_0 = nodeOut_a_mem_4_param; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_4_size_0 = nodeOut_a_mem_4_size; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_4_source_0 = nodeOut_a_mem_4_source; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_4_address_0 = nodeOut_a_mem_4_address; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_4_mask_0 = nodeOut_a_mem_4_mask; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_4_data_0 = nodeOut_a_mem_4_data; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_5_opcode_0 = nodeOut_a_mem_5_opcode; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_5_param_0 = nodeOut_a_mem_5_param; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_5_size_0 = nodeOut_a_mem_5_size; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_5_source_0 = nodeOut_a_mem_5_source; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_5_address_0 = nodeOut_a_mem_5_address; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_5_mask_0 = nodeOut_a_mem_5_mask; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_5_data_0 = nodeOut_a_mem_5_data; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_6_opcode_0 = nodeOut_a_mem_6_opcode; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_6_param_0 = nodeOut_a_mem_6_param; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_6_size_0 = nodeOut_a_mem_6_size; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_6_source_0 = nodeOut_a_mem_6_source; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_6_address_0 = nodeOut_a_mem_6_address; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_6_mask_0 = nodeOut_a_mem_6_mask; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_6_data_0 = nodeOut_a_mem_6_data; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_7_opcode_0 = nodeOut_a_mem_7_opcode; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_7_param_0 = nodeOut_a_mem_7_param; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_7_size_0 = nodeOut_a_mem_7_size; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_7_source_0 = nodeOut_a_mem_7_source; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_7_address_0 = nodeOut_a_mem_7_address; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_7_mask_0 = nodeOut_a_mem_7_mask; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_7_data_0 = nodeOut_a_mem_7_data; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_widx_0 = nodeOut_a_widx; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_safe_widx_valid_0 = nodeOut_a_safe_widx_valid; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_safe_source_reset_n_0 = nodeOut_a_safe_source_reset_n; // @[AsyncCrossing.scala:23:9]
assign auto_out_b_ridx_0 = nodeOut_b_ridx; // @[AsyncCrossing.scala:23:9]
assign auto_out_b_safe_ridx_valid_0 = nodeOut_b_safe_ridx_valid; // @[AsyncCrossing.scala:23:9]
assign auto_out_b_safe_sink_reset_n_0 = nodeOut_b_safe_sink_reset_n; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_0_opcode_0 = nodeOut_c_mem_0_opcode; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_0_param_0 = nodeOut_c_mem_0_param; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_0_size_0 = nodeOut_c_mem_0_size; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_0_source_0 = nodeOut_c_mem_0_source; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_0_address_0 = nodeOut_c_mem_0_address; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_0_data_0 = nodeOut_c_mem_0_data; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_1_opcode_0 = nodeOut_c_mem_1_opcode; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_1_param_0 = nodeOut_c_mem_1_param; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_1_size_0 = nodeOut_c_mem_1_size; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_1_source_0 = nodeOut_c_mem_1_source; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_1_address_0 = nodeOut_c_mem_1_address; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_1_data_0 = nodeOut_c_mem_1_data; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_2_opcode_0 = nodeOut_c_mem_2_opcode; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_2_param_0 = nodeOut_c_mem_2_param; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_2_size_0 = nodeOut_c_mem_2_size; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_2_source_0 = nodeOut_c_mem_2_source; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_2_address_0 = nodeOut_c_mem_2_address; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_2_data_0 = nodeOut_c_mem_2_data; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_3_opcode_0 = nodeOut_c_mem_3_opcode; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_3_param_0 = nodeOut_c_mem_3_param; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_3_size_0 = nodeOut_c_mem_3_size; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_3_source_0 = nodeOut_c_mem_3_source; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_3_address_0 = nodeOut_c_mem_3_address; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_3_data_0 = nodeOut_c_mem_3_data; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_4_opcode_0 = nodeOut_c_mem_4_opcode; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_4_param_0 = nodeOut_c_mem_4_param; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_4_size_0 = nodeOut_c_mem_4_size; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_4_source_0 = nodeOut_c_mem_4_source; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_4_address_0 = nodeOut_c_mem_4_address; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_4_data_0 = nodeOut_c_mem_4_data; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_5_opcode_0 = nodeOut_c_mem_5_opcode; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_5_param_0 = nodeOut_c_mem_5_param; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_5_size_0 = nodeOut_c_mem_5_size; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_5_source_0 = nodeOut_c_mem_5_source; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_5_address_0 = nodeOut_c_mem_5_address; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_5_data_0 = nodeOut_c_mem_5_data; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_6_opcode_0 = nodeOut_c_mem_6_opcode; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_6_param_0 = nodeOut_c_mem_6_param; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_6_size_0 = nodeOut_c_mem_6_size; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_6_source_0 = nodeOut_c_mem_6_source; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_6_address_0 = nodeOut_c_mem_6_address; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_6_data_0 = nodeOut_c_mem_6_data; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_7_opcode_0 = nodeOut_c_mem_7_opcode; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_7_param_0 = nodeOut_c_mem_7_param; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_7_size_0 = nodeOut_c_mem_7_size; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_7_source_0 = nodeOut_c_mem_7_source; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_7_address_0 = nodeOut_c_mem_7_address; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_7_data_0 = nodeOut_c_mem_7_data; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_widx_0 = nodeOut_c_widx; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_safe_widx_valid_0 = nodeOut_c_safe_widx_valid; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_safe_source_reset_n_0 = nodeOut_c_safe_source_reset_n; // @[AsyncCrossing.scala:23:9]
assign auto_out_d_ridx_0 = nodeOut_d_ridx; // @[AsyncCrossing.scala:23:9]
assign auto_out_d_safe_ridx_valid_0 = nodeOut_d_safe_ridx_valid; // @[AsyncCrossing.scala:23:9]
assign auto_out_d_safe_sink_reset_n_0 = nodeOut_d_safe_sink_reset_n; // @[AsyncCrossing.scala:23:9]
assign auto_out_e_mem_0_sink_0 = nodeOut_e_mem_0_sink; // @[AsyncCrossing.scala:23:9]
assign auto_out_e_mem_1_sink_0 = nodeOut_e_mem_1_sink; // @[AsyncCrossing.scala:23:9]
assign auto_out_e_mem_2_sink_0 = nodeOut_e_mem_2_sink; // @[AsyncCrossing.scala:23:9]
assign auto_out_e_mem_3_sink_0 = nodeOut_e_mem_3_sink; // @[AsyncCrossing.scala:23:9]
assign auto_out_e_mem_4_sink_0 = nodeOut_e_mem_4_sink; // @[AsyncCrossing.scala:23:9]
assign auto_out_e_mem_5_sink_0 = nodeOut_e_mem_5_sink; // @[AsyncCrossing.scala:23:9]
assign auto_out_e_mem_6_sink_0 = nodeOut_e_mem_6_sink; // @[AsyncCrossing.scala:23:9]
assign auto_out_e_mem_7_sink_0 = nodeOut_e_mem_7_sink; // @[AsyncCrossing.scala:23:9]
assign auto_out_e_widx_0 = nodeOut_e_widx; // @[AsyncCrossing.scala:23:9]
assign auto_out_e_safe_widx_valid_0 = nodeOut_e_safe_widx_valid; // @[AsyncCrossing.scala:23:9]
assign auto_out_e_safe_source_reset_n_0 = nodeOut_e_safe_source_reset_n; // @[AsyncCrossing.scala:23:9]
TLMonitor_41 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_b_ready (nodeIn_b_ready), // @[MixedNode.scala:551:17]
.io_in_b_valid (nodeIn_b_valid), // @[MixedNode.scala:551:17]
.io_in_b_bits_opcode (nodeIn_b_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_b_bits_param (nodeIn_b_bits_param), // @[MixedNode.scala:551:17]
.io_in_b_bits_size (nodeIn_b_bits_size), // @[MixedNode.scala:551:17]
.io_in_b_bits_source (nodeIn_b_bits_source), // @[MixedNode.scala:551:17]
.io_in_b_bits_address (nodeIn_b_bits_address), // @[MixedNode.scala:551:17]
.io_in_b_bits_mask (nodeIn_b_bits_mask), // @[MixedNode.scala:551:17]
.io_in_b_bits_data (nodeIn_b_bits_data), // @[MixedNode.scala:551:17]
.io_in_b_bits_corrupt (nodeIn_b_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_c_ready (nodeIn_c_ready), // @[MixedNode.scala:551:17]
.io_in_c_valid (nodeIn_c_valid), // @[MixedNode.scala:551:17]
.io_in_c_bits_opcode (nodeIn_c_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_c_bits_param (nodeIn_c_bits_param), // @[MixedNode.scala:551:17]
.io_in_c_bits_size (nodeIn_c_bits_size), // @[MixedNode.scala:551:17]
.io_in_c_bits_source (nodeIn_c_bits_source), // @[MixedNode.scala:551:17]
.io_in_c_bits_address (nodeIn_c_bits_address), // @[MixedNode.scala:551:17]
.io_in_c_bits_data (nodeIn_c_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17]
.io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_bits_corrupt (nodeIn_d_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_e_ready (nodeIn_e_ready), // @[MixedNode.scala:551:17]
.io_in_e_valid (nodeIn_e_valid), // @[MixedNode.scala:551:17]
.io_in_e_bits_sink (nodeIn_e_bits_sink) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
AsyncQueueSource_TLBundleA_a32d64s2k3z4c nodeOut_a_source ( // @[AsyncQueue.scala:220:24]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeIn_a_ready),
.io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_async_mem_0_opcode (nodeOut_a_mem_0_opcode),
.io_async_mem_0_param (nodeOut_a_mem_0_param),
.io_async_mem_0_size (nodeOut_a_mem_0_size),
.io_async_mem_0_source (nodeOut_a_mem_0_source),
.io_async_mem_0_address (nodeOut_a_mem_0_address),
.io_async_mem_0_mask (nodeOut_a_mem_0_mask),
.io_async_mem_0_data (nodeOut_a_mem_0_data),
.io_async_mem_1_opcode (nodeOut_a_mem_1_opcode),
.io_async_mem_1_param (nodeOut_a_mem_1_param),
.io_async_mem_1_size (nodeOut_a_mem_1_size),
.io_async_mem_1_source (nodeOut_a_mem_1_source),
.io_async_mem_1_address (nodeOut_a_mem_1_address),
.io_async_mem_1_mask (nodeOut_a_mem_1_mask),
.io_async_mem_1_data (nodeOut_a_mem_1_data),
.io_async_mem_2_opcode (nodeOut_a_mem_2_opcode),
.io_async_mem_2_param (nodeOut_a_mem_2_param),
.io_async_mem_2_size (nodeOut_a_mem_2_size),
.io_async_mem_2_source (nodeOut_a_mem_2_source),
.io_async_mem_2_address (nodeOut_a_mem_2_address),
.io_async_mem_2_mask (nodeOut_a_mem_2_mask),
.io_async_mem_2_data (nodeOut_a_mem_2_data),
.io_async_mem_3_opcode (nodeOut_a_mem_3_opcode),
.io_async_mem_3_param (nodeOut_a_mem_3_param),
.io_async_mem_3_size (nodeOut_a_mem_3_size),
.io_async_mem_3_source (nodeOut_a_mem_3_source),
.io_async_mem_3_address (nodeOut_a_mem_3_address),
.io_async_mem_3_mask (nodeOut_a_mem_3_mask),
.io_async_mem_3_data (nodeOut_a_mem_3_data),
.io_async_mem_4_opcode (nodeOut_a_mem_4_opcode),
.io_async_mem_4_param (nodeOut_a_mem_4_param),
.io_async_mem_4_size (nodeOut_a_mem_4_size),
.io_async_mem_4_source (nodeOut_a_mem_4_source),
.io_async_mem_4_address (nodeOut_a_mem_4_address),
.io_async_mem_4_mask (nodeOut_a_mem_4_mask),
.io_async_mem_4_data (nodeOut_a_mem_4_data),
.io_async_mem_5_opcode (nodeOut_a_mem_5_opcode),
.io_async_mem_5_param (nodeOut_a_mem_5_param),
.io_async_mem_5_size (nodeOut_a_mem_5_size),
.io_async_mem_5_source (nodeOut_a_mem_5_source),
.io_async_mem_5_address (nodeOut_a_mem_5_address),
.io_async_mem_5_mask (nodeOut_a_mem_5_mask),
.io_async_mem_5_data (nodeOut_a_mem_5_data),
.io_async_mem_6_opcode (nodeOut_a_mem_6_opcode),
.io_async_mem_6_param (nodeOut_a_mem_6_param),
.io_async_mem_6_size (nodeOut_a_mem_6_size),
.io_async_mem_6_source (nodeOut_a_mem_6_source),
.io_async_mem_6_address (nodeOut_a_mem_6_address),
.io_async_mem_6_mask (nodeOut_a_mem_6_mask),
.io_async_mem_6_data (nodeOut_a_mem_6_data),
.io_async_mem_7_opcode (nodeOut_a_mem_7_opcode),
.io_async_mem_7_param (nodeOut_a_mem_7_param),
.io_async_mem_7_size (nodeOut_a_mem_7_size),
.io_async_mem_7_source (nodeOut_a_mem_7_source),
.io_async_mem_7_address (nodeOut_a_mem_7_address),
.io_async_mem_7_mask (nodeOut_a_mem_7_mask),
.io_async_mem_7_data (nodeOut_a_mem_7_data),
.io_async_ridx (nodeOut_a_ridx), // @[MixedNode.scala:542:17]
.io_async_widx (nodeOut_a_widx),
.io_async_safe_ridx_valid (nodeOut_a_safe_ridx_valid), // @[MixedNode.scala:542:17]
.io_async_safe_widx_valid (nodeOut_a_safe_widx_valid),
.io_async_safe_source_reset_n (nodeOut_a_safe_source_reset_n),
.io_async_safe_sink_reset_n (nodeOut_a_safe_sink_reset_n) // @[MixedNode.scala:542:17]
); // @[AsyncQueue.scala:220:24]
AsyncQueueSink_TLBundleD_a32d64s2k3z4c nodeIn_d_sink ( // @[AsyncQueue.scala:211:22]
.clock (clock),
.reset (reset),
.io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_deq_valid (nodeIn_d_valid),
.io_deq_bits_opcode (nodeIn_d_bits_opcode),
.io_deq_bits_param (nodeIn_d_bits_param),
.io_deq_bits_size (nodeIn_d_bits_size),
.io_deq_bits_source (nodeIn_d_bits_source),
.io_deq_bits_sink (nodeIn_d_bits_sink),
.io_deq_bits_denied (nodeIn_d_bits_denied),
.io_deq_bits_data (nodeIn_d_bits_data),
.io_deq_bits_corrupt (nodeIn_d_bits_corrupt),
.io_async_mem_0_opcode (nodeOut_d_mem_0_opcode), // @[MixedNode.scala:542:17]
.io_async_mem_0_param (nodeOut_d_mem_0_param), // @[MixedNode.scala:542:17]
.io_async_mem_0_size (nodeOut_d_mem_0_size), // @[MixedNode.scala:542:17]
.io_async_mem_0_source (nodeOut_d_mem_0_source), // @[MixedNode.scala:542:17]
.io_async_mem_0_sink (nodeOut_d_mem_0_sink), // @[MixedNode.scala:542:17]
.io_async_mem_0_denied (nodeOut_d_mem_0_denied), // @[MixedNode.scala:542:17]
.io_async_mem_0_data (nodeOut_d_mem_0_data), // @[MixedNode.scala:542:17]
.io_async_mem_0_corrupt (nodeOut_d_mem_0_corrupt), // @[MixedNode.scala:542:17]
.io_async_mem_1_opcode (nodeOut_d_mem_1_opcode), // @[MixedNode.scala:542:17]
.io_async_mem_1_param (nodeOut_d_mem_1_param), // @[MixedNode.scala:542:17]
.io_async_mem_1_size (nodeOut_d_mem_1_size), // @[MixedNode.scala:542:17]
.io_async_mem_1_source (nodeOut_d_mem_1_source), // @[MixedNode.scala:542:17]
.io_async_mem_1_sink (nodeOut_d_mem_1_sink), // @[MixedNode.scala:542:17]
.io_async_mem_1_denied (nodeOut_d_mem_1_denied), // @[MixedNode.scala:542:17]
.io_async_mem_1_data (nodeOut_d_mem_1_data), // @[MixedNode.scala:542:17]
.io_async_mem_1_corrupt (nodeOut_d_mem_1_corrupt), // @[MixedNode.scala:542:17]
.io_async_mem_2_opcode (nodeOut_d_mem_2_opcode), // @[MixedNode.scala:542:17]
.io_async_mem_2_param (nodeOut_d_mem_2_param), // @[MixedNode.scala:542:17]
.io_async_mem_2_size (nodeOut_d_mem_2_size), // @[MixedNode.scala:542:17]
.io_async_mem_2_source (nodeOut_d_mem_2_source), // @[MixedNode.scala:542:17]
.io_async_mem_2_sink (nodeOut_d_mem_2_sink), // @[MixedNode.scala:542:17]
.io_async_mem_2_denied (nodeOut_d_mem_2_denied), // @[MixedNode.scala:542:17]
.io_async_mem_2_data (nodeOut_d_mem_2_data), // @[MixedNode.scala:542:17]
.io_async_mem_2_corrupt (nodeOut_d_mem_2_corrupt), // @[MixedNode.scala:542:17]
.io_async_mem_3_opcode (nodeOut_d_mem_3_opcode), // @[MixedNode.scala:542:17]
.io_async_mem_3_param (nodeOut_d_mem_3_param), // @[MixedNode.scala:542:17]
.io_async_mem_3_size (nodeOut_d_mem_3_size), // @[MixedNode.scala:542:17]
.io_async_mem_3_source (nodeOut_d_mem_3_source), // @[MixedNode.scala:542:17]
.io_async_mem_3_sink (nodeOut_d_mem_3_sink), // @[MixedNode.scala:542:17]
.io_async_mem_3_denied (nodeOut_d_mem_3_denied), // @[MixedNode.scala:542:17]
.io_async_mem_3_data (nodeOut_d_mem_3_data), // @[MixedNode.scala:542:17]
.io_async_mem_3_corrupt (nodeOut_d_mem_3_corrupt), // @[MixedNode.scala:542:17]
.io_async_mem_4_opcode (nodeOut_d_mem_4_opcode), // @[MixedNode.scala:542:17]
.io_async_mem_4_param (nodeOut_d_mem_4_param), // @[MixedNode.scala:542:17]
.io_async_mem_4_size (nodeOut_d_mem_4_size), // @[MixedNode.scala:542:17]
.io_async_mem_4_source (nodeOut_d_mem_4_source), // @[MixedNode.scala:542:17]
.io_async_mem_4_sink (nodeOut_d_mem_4_sink), // @[MixedNode.scala:542:17]
.io_async_mem_4_denied (nodeOut_d_mem_4_denied), // @[MixedNode.scala:542:17]
.io_async_mem_4_data (nodeOut_d_mem_4_data), // @[MixedNode.scala:542:17]
.io_async_mem_4_corrupt (nodeOut_d_mem_4_corrupt), // @[MixedNode.scala:542:17]
.io_async_mem_5_opcode (nodeOut_d_mem_5_opcode), // @[MixedNode.scala:542:17]
.io_async_mem_5_param (nodeOut_d_mem_5_param), // @[MixedNode.scala:542:17]
.io_async_mem_5_size (nodeOut_d_mem_5_size), // @[MixedNode.scala:542:17]
.io_async_mem_5_source (nodeOut_d_mem_5_source), // @[MixedNode.scala:542:17]
.io_async_mem_5_sink (nodeOut_d_mem_5_sink), // @[MixedNode.scala:542:17]
.io_async_mem_5_denied (nodeOut_d_mem_5_denied), // @[MixedNode.scala:542:17]
.io_async_mem_5_data (nodeOut_d_mem_5_data), // @[MixedNode.scala:542:17]
.io_async_mem_5_corrupt (nodeOut_d_mem_5_corrupt), // @[MixedNode.scala:542:17]
.io_async_mem_6_opcode (nodeOut_d_mem_6_opcode), // @[MixedNode.scala:542:17]
.io_async_mem_6_param (nodeOut_d_mem_6_param), // @[MixedNode.scala:542:17]
.io_async_mem_6_size (nodeOut_d_mem_6_size), // @[MixedNode.scala:542:17]
.io_async_mem_6_source (nodeOut_d_mem_6_source), // @[MixedNode.scala:542:17]
.io_async_mem_6_sink (nodeOut_d_mem_6_sink), // @[MixedNode.scala:542:17]
.io_async_mem_6_denied (nodeOut_d_mem_6_denied), // @[MixedNode.scala:542:17]
.io_async_mem_6_data (nodeOut_d_mem_6_data), // @[MixedNode.scala:542:17]
.io_async_mem_6_corrupt (nodeOut_d_mem_6_corrupt), // @[MixedNode.scala:542:17]
.io_async_mem_7_opcode (nodeOut_d_mem_7_opcode), // @[MixedNode.scala:542:17]
.io_async_mem_7_param (nodeOut_d_mem_7_param), // @[MixedNode.scala:542:17]
.io_async_mem_7_size (nodeOut_d_mem_7_size), // @[MixedNode.scala:542:17]
.io_async_mem_7_source (nodeOut_d_mem_7_source), // @[MixedNode.scala:542:17]
.io_async_mem_7_sink (nodeOut_d_mem_7_sink), // @[MixedNode.scala:542:17]
.io_async_mem_7_denied (nodeOut_d_mem_7_denied), // @[MixedNode.scala:542:17]
.io_async_mem_7_data (nodeOut_d_mem_7_data), // @[MixedNode.scala:542:17]
.io_async_mem_7_corrupt (nodeOut_d_mem_7_corrupt), // @[MixedNode.scala:542:17]
.io_async_ridx (nodeOut_d_ridx),
.io_async_widx (nodeOut_d_widx), // @[MixedNode.scala:542:17]
.io_async_safe_ridx_valid (nodeOut_d_safe_ridx_valid),
.io_async_safe_widx_valid (nodeOut_d_safe_widx_valid), // @[MixedNode.scala:542:17]
.io_async_safe_source_reset_n (nodeOut_d_safe_source_reset_n), // @[MixedNode.scala:542:17]
.io_async_safe_sink_reset_n (nodeOut_d_safe_sink_reset_n)
); // @[AsyncQueue.scala:211:22]
AsyncQueueSink_TLBundleB_a32d64s2k3z4c nodeIn_b_sink ( // @[AsyncQueue.scala:211:22]
.clock (clock),
.reset (reset),
.io_deq_ready (nodeIn_b_ready), // @[MixedNode.scala:551:17]
.io_deq_valid (nodeIn_b_valid),
.io_deq_bits_opcode (nodeIn_b_bits_opcode),
.io_deq_bits_param (nodeIn_b_bits_param),
.io_deq_bits_size (nodeIn_b_bits_size),
.io_deq_bits_source (nodeIn_b_bits_source),
.io_deq_bits_address (nodeIn_b_bits_address),
.io_deq_bits_mask (nodeIn_b_bits_mask),
.io_deq_bits_data (nodeIn_b_bits_data),
.io_deq_bits_corrupt (nodeIn_b_bits_corrupt),
.io_async_mem_0_param (nodeOut_b_mem_0_param), // @[MixedNode.scala:542:17]
.io_async_mem_0_address (nodeOut_b_mem_0_address), // @[MixedNode.scala:542:17]
.io_async_mem_1_param (nodeOut_b_mem_1_param), // @[MixedNode.scala:542:17]
.io_async_mem_1_address (nodeOut_b_mem_1_address), // @[MixedNode.scala:542:17]
.io_async_mem_2_param (nodeOut_b_mem_2_param), // @[MixedNode.scala:542:17]
.io_async_mem_2_address (nodeOut_b_mem_2_address), // @[MixedNode.scala:542:17]
.io_async_mem_3_param (nodeOut_b_mem_3_param), // @[MixedNode.scala:542:17]
.io_async_mem_3_address (nodeOut_b_mem_3_address), // @[MixedNode.scala:542:17]
.io_async_mem_4_param (nodeOut_b_mem_4_param), // @[MixedNode.scala:542:17]
.io_async_mem_4_address (nodeOut_b_mem_4_address), // @[MixedNode.scala:542:17]
.io_async_mem_5_param (nodeOut_b_mem_5_param), // @[MixedNode.scala:542:17]
.io_async_mem_5_address (nodeOut_b_mem_5_address), // @[MixedNode.scala:542:17]
.io_async_mem_6_param (nodeOut_b_mem_6_param), // @[MixedNode.scala:542:17]
.io_async_mem_6_address (nodeOut_b_mem_6_address), // @[MixedNode.scala:542:17]
.io_async_mem_7_param (nodeOut_b_mem_7_param), // @[MixedNode.scala:542:17]
.io_async_mem_7_address (nodeOut_b_mem_7_address), // @[MixedNode.scala:542:17]
.io_async_ridx (nodeOut_b_ridx),
.io_async_widx (nodeOut_b_widx), // @[MixedNode.scala:542:17]
.io_async_safe_ridx_valid (nodeOut_b_safe_ridx_valid),
.io_async_safe_widx_valid (nodeOut_b_safe_widx_valid), // @[MixedNode.scala:542:17]
.io_async_safe_source_reset_n (nodeOut_b_safe_source_reset_n), // @[MixedNode.scala:542:17]
.io_async_safe_sink_reset_n (nodeOut_b_safe_sink_reset_n)
); // @[AsyncQueue.scala:211:22]
AsyncQueueSource_TLBundleC_a32d64s2k3z4c nodeOut_c_source ( // @[AsyncQueue.scala:220:24]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeIn_c_ready),
.io_enq_valid (nodeIn_c_valid), // @[MixedNode.scala:551:17]
.io_enq_bits_opcode (nodeIn_c_bits_opcode), // @[MixedNode.scala:551:17]
.io_enq_bits_param (nodeIn_c_bits_param), // @[MixedNode.scala:551:17]
.io_enq_bits_size (nodeIn_c_bits_size), // @[MixedNode.scala:551:17]
.io_enq_bits_source (nodeIn_c_bits_source), // @[MixedNode.scala:551:17]
.io_enq_bits_address (nodeIn_c_bits_address), // @[MixedNode.scala:551:17]
.io_enq_bits_data (nodeIn_c_bits_data), // @[MixedNode.scala:551:17]
.io_async_mem_0_opcode (nodeOut_c_mem_0_opcode),
.io_async_mem_0_param (nodeOut_c_mem_0_param),
.io_async_mem_0_size (nodeOut_c_mem_0_size),
.io_async_mem_0_source (nodeOut_c_mem_0_source),
.io_async_mem_0_address (nodeOut_c_mem_0_address),
.io_async_mem_0_data (nodeOut_c_mem_0_data),
.io_async_mem_1_opcode (nodeOut_c_mem_1_opcode),
.io_async_mem_1_param (nodeOut_c_mem_1_param),
.io_async_mem_1_size (nodeOut_c_mem_1_size),
.io_async_mem_1_source (nodeOut_c_mem_1_source),
.io_async_mem_1_address (nodeOut_c_mem_1_address),
.io_async_mem_1_data (nodeOut_c_mem_1_data),
.io_async_mem_2_opcode (nodeOut_c_mem_2_opcode),
.io_async_mem_2_param (nodeOut_c_mem_2_param),
.io_async_mem_2_size (nodeOut_c_mem_2_size),
.io_async_mem_2_source (nodeOut_c_mem_2_source),
.io_async_mem_2_address (nodeOut_c_mem_2_address),
.io_async_mem_2_data (nodeOut_c_mem_2_data),
.io_async_mem_3_opcode (nodeOut_c_mem_3_opcode),
.io_async_mem_3_param (nodeOut_c_mem_3_param),
.io_async_mem_3_size (nodeOut_c_mem_3_size),
.io_async_mem_3_source (nodeOut_c_mem_3_source),
.io_async_mem_3_address (nodeOut_c_mem_3_address),
.io_async_mem_3_data (nodeOut_c_mem_3_data),
.io_async_mem_4_opcode (nodeOut_c_mem_4_opcode),
.io_async_mem_4_param (nodeOut_c_mem_4_param),
.io_async_mem_4_size (nodeOut_c_mem_4_size),
.io_async_mem_4_source (nodeOut_c_mem_4_source),
.io_async_mem_4_address (nodeOut_c_mem_4_address),
.io_async_mem_4_data (nodeOut_c_mem_4_data),
.io_async_mem_5_opcode (nodeOut_c_mem_5_opcode),
.io_async_mem_5_param (nodeOut_c_mem_5_param),
.io_async_mem_5_size (nodeOut_c_mem_5_size),
.io_async_mem_5_source (nodeOut_c_mem_5_source),
.io_async_mem_5_address (nodeOut_c_mem_5_address),
.io_async_mem_5_data (nodeOut_c_mem_5_data),
.io_async_mem_6_opcode (nodeOut_c_mem_6_opcode),
.io_async_mem_6_param (nodeOut_c_mem_6_param),
.io_async_mem_6_size (nodeOut_c_mem_6_size),
.io_async_mem_6_source (nodeOut_c_mem_6_source),
.io_async_mem_6_address (nodeOut_c_mem_6_address),
.io_async_mem_6_data (nodeOut_c_mem_6_data),
.io_async_mem_7_opcode (nodeOut_c_mem_7_opcode),
.io_async_mem_7_param (nodeOut_c_mem_7_param),
.io_async_mem_7_size (nodeOut_c_mem_7_size),
.io_async_mem_7_source (nodeOut_c_mem_7_source),
.io_async_mem_7_address (nodeOut_c_mem_7_address),
.io_async_mem_7_data (nodeOut_c_mem_7_data),
.io_async_ridx (nodeOut_c_ridx), // @[MixedNode.scala:542:17]
.io_async_widx (nodeOut_c_widx),
.io_async_safe_ridx_valid (nodeOut_c_safe_ridx_valid), // @[MixedNode.scala:542:17]
.io_async_safe_widx_valid (nodeOut_c_safe_widx_valid),
.io_async_safe_source_reset_n (nodeOut_c_safe_source_reset_n),
.io_async_safe_sink_reset_n (nodeOut_c_safe_sink_reset_n) // @[MixedNode.scala:542:17]
); // @[AsyncQueue.scala:220:24]
AsyncQueueSource_TLBundleE_a32d64s2k3z4c nodeOut_e_source ( // @[AsyncQueue.scala:220:24]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeIn_e_ready),
.io_enq_valid (nodeIn_e_valid), // @[MixedNode.scala:551:17]
.io_enq_bits_sink (nodeIn_e_bits_sink), // @[MixedNode.scala:551:17]
.io_async_mem_0_sink (nodeOut_e_mem_0_sink),
.io_async_mem_1_sink (nodeOut_e_mem_1_sink),
.io_async_mem_2_sink (nodeOut_e_mem_2_sink),
.io_async_mem_3_sink (nodeOut_e_mem_3_sink),
.io_async_mem_4_sink (nodeOut_e_mem_4_sink),
.io_async_mem_5_sink (nodeOut_e_mem_5_sink),
.io_async_mem_6_sink (nodeOut_e_mem_6_sink),
.io_async_mem_7_sink (nodeOut_e_mem_7_sink),
.io_async_ridx (nodeOut_e_ridx), // @[MixedNode.scala:542:17]
.io_async_widx (nodeOut_e_widx),
.io_async_safe_ridx_valid (nodeOut_e_safe_ridx_valid), // @[MixedNode.scala:542:17]
.io_async_safe_widx_valid (nodeOut_e_safe_widx_valid),
.io_async_safe_source_reset_n (nodeOut_e_safe_source_reset_n),
.io_async_safe_sink_reset_n (nodeOut_e_safe_sink_reset_n) // @[MixedNode.scala:542:17]
); // @[AsyncQueue.scala:220:24]
assign auto_in_a_ready = auto_in_a_ready_0; // @[AsyncCrossing.scala:23:9]
assign auto_in_b_valid = auto_in_b_valid_0; // @[AsyncCrossing.scala:23:9]
assign auto_in_b_bits_opcode = auto_in_b_bits_opcode_0; // @[AsyncCrossing.scala:23:9]
assign auto_in_b_bits_param = auto_in_b_bits_param_0; // @[AsyncCrossing.scala:23:9]
assign auto_in_b_bits_size = auto_in_b_bits_size_0; // @[AsyncCrossing.scala:23:9]
assign auto_in_b_bits_source = auto_in_b_bits_source_0; // @[AsyncCrossing.scala:23:9]
assign auto_in_b_bits_address = auto_in_b_bits_address_0; // @[AsyncCrossing.scala:23:9]
assign auto_in_b_bits_mask = auto_in_b_bits_mask_0; // @[AsyncCrossing.scala:23:9]
assign auto_in_b_bits_data = auto_in_b_bits_data_0; // @[AsyncCrossing.scala:23:9]
assign auto_in_b_bits_corrupt = auto_in_b_bits_corrupt_0; // @[AsyncCrossing.scala:23:9]
assign auto_in_c_ready = auto_in_c_ready_0; // @[AsyncCrossing.scala:23:9]
assign auto_in_d_valid = auto_in_d_valid_0; // @[AsyncCrossing.scala:23:9]
assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[AsyncCrossing.scala:23:9]
assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[AsyncCrossing.scala:23:9]
assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[AsyncCrossing.scala:23:9]
assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[AsyncCrossing.scala:23:9]
assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[AsyncCrossing.scala:23:9]
assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[AsyncCrossing.scala:23:9]
assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[AsyncCrossing.scala:23:9]
assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[AsyncCrossing.scala:23:9]
assign auto_in_e_ready = auto_in_e_ready_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_0_opcode = auto_out_a_mem_0_opcode_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_0_param = auto_out_a_mem_0_param_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_0_size = auto_out_a_mem_0_size_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_0_source = auto_out_a_mem_0_source_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_0_address = auto_out_a_mem_0_address_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_0_mask = auto_out_a_mem_0_mask_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_0_data = auto_out_a_mem_0_data_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_1_opcode = auto_out_a_mem_1_opcode_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_1_param = auto_out_a_mem_1_param_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_1_size = auto_out_a_mem_1_size_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_1_source = auto_out_a_mem_1_source_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_1_address = auto_out_a_mem_1_address_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_1_mask = auto_out_a_mem_1_mask_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_1_data = auto_out_a_mem_1_data_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_2_opcode = auto_out_a_mem_2_opcode_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_2_param = auto_out_a_mem_2_param_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_2_size = auto_out_a_mem_2_size_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_2_source = auto_out_a_mem_2_source_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_2_address = auto_out_a_mem_2_address_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_2_mask = auto_out_a_mem_2_mask_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_2_data = auto_out_a_mem_2_data_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_3_opcode = auto_out_a_mem_3_opcode_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_3_param = auto_out_a_mem_3_param_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_3_size = auto_out_a_mem_3_size_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_3_source = auto_out_a_mem_3_source_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_3_address = auto_out_a_mem_3_address_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_3_mask = auto_out_a_mem_3_mask_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_3_data = auto_out_a_mem_3_data_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_4_opcode = auto_out_a_mem_4_opcode_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_4_param = auto_out_a_mem_4_param_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_4_size = auto_out_a_mem_4_size_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_4_source = auto_out_a_mem_4_source_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_4_address = auto_out_a_mem_4_address_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_4_mask = auto_out_a_mem_4_mask_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_4_data = auto_out_a_mem_4_data_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_5_opcode = auto_out_a_mem_5_opcode_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_5_param = auto_out_a_mem_5_param_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_5_size = auto_out_a_mem_5_size_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_5_source = auto_out_a_mem_5_source_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_5_address = auto_out_a_mem_5_address_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_5_mask = auto_out_a_mem_5_mask_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_5_data = auto_out_a_mem_5_data_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_6_opcode = auto_out_a_mem_6_opcode_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_6_param = auto_out_a_mem_6_param_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_6_size = auto_out_a_mem_6_size_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_6_source = auto_out_a_mem_6_source_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_6_address = auto_out_a_mem_6_address_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_6_mask = auto_out_a_mem_6_mask_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_6_data = auto_out_a_mem_6_data_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_7_opcode = auto_out_a_mem_7_opcode_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_7_param = auto_out_a_mem_7_param_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_7_size = auto_out_a_mem_7_size_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_7_source = auto_out_a_mem_7_source_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_7_address = auto_out_a_mem_7_address_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_7_mask = auto_out_a_mem_7_mask_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_7_data = auto_out_a_mem_7_data_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_widx = auto_out_a_widx_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_safe_widx_valid = auto_out_a_safe_widx_valid_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_safe_source_reset_n = auto_out_a_safe_source_reset_n_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_b_ridx = auto_out_b_ridx_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_b_safe_ridx_valid = auto_out_b_safe_ridx_valid_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_b_safe_sink_reset_n = auto_out_b_safe_sink_reset_n_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_0_opcode = auto_out_c_mem_0_opcode_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_0_param = auto_out_c_mem_0_param_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_0_size = auto_out_c_mem_0_size_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_0_source = auto_out_c_mem_0_source_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_0_address = auto_out_c_mem_0_address_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_0_data = auto_out_c_mem_0_data_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_1_opcode = auto_out_c_mem_1_opcode_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_1_param = auto_out_c_mem_1_param_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_1_size = auto_out_c_mem_1_size_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_1_source = auto_out_c_mem_1_source_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_1_address = auto_out_c_mem_1_address_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_1_data = auto_out_c_mem_1_data_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_2_opcode = auto_out_c_mem_2_opcode_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_2_param = auto_out_c_mem_2_param_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_2_size = auto_out_c_mem_2_size_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_2_source = auto_out_c_mem_2_source_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_2_address = auto_out_c_mem_2_address_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_2_data = auto_out_c_mem_2_data_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_3_opcode = auto_out_c_mem_3_opcode_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_3_param = auto_out_c_mem_3_param_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_3_size = auto_out_c_mem_3_size_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_3_source = auto_out_c_mem_3_source_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_3_address = auto_out_c_mem_3_address_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_3_data = auto_out_c_mem_3_data_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_4_opcode = auto_out_c_mem_4_opcode_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_4_param = auto_out_c_mem_4_param_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_4_size = auto_out_c_mem_4_size_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_4_source = auto_out_c_mem_4_source_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_4_address = auto_out_c_mem_4_address_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_4_data = auto_out_c_mem_4_data_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_5_opcode = auto_out_c_mem_5_opcode_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_5_param = auto_out_c_mem_5_param_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_5_size = auto_out_c_mem_5_size_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_5_source = auto_out_c_mem_5_source_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_5_address = auto_out_c_mem_5_address_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_5_data = auto_out_c_mem_5_data_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_6_opcode = auto_out_c_mem_6_opcode_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_6_param = auto_out_c_mem_6_param_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_6_size = auto_out_c_mem_6_size_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_6_source = auto_out_c_mem_6_source_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_6_address = auto_out_c_mem_6_address_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_6_data = auto_out_c_mem_6_data_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_7_opcode = auto_out_c_mem_7_opcode_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_7_param = auto_out_c_mem_7_param_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_7_size = auto_out_c_mem_7_size_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_7_source = auto_out_c_mem_7_source_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_7_address = auto_out_c_mem_7_address_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_mem_7_data = auto_out_c_mem_7_data_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_widx = auto_out_c_widx_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_safe_widx_valid = auto_out_c_safe_widx_valid_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_c_safe_source_reset_n = auto_out_c_safe_source_reset_n_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_d_ridx = auto_out_d_ridx_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_d_safe_ridx_valid = auto_out_d_safe_ridx_valid_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_d_safe_sink_reset_n = auto_out_d_safe_sink_reset_n_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_e_mem_0_sink = auto_out_e_mem_0_sink_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_e_mem_1_sink = auto_out_e_mem_1_sink_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_e_mem_2_sink = auto_out_e_mem_2_sink_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_e_mem_3_sink = auto_out_e_mem_3_sink_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_e_mem_4_sink = auto_out_e_mem_4_sink_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_e_mem_5_sink = auto_out_e_mem_5_sink_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_e_mem_6_sink = auto_out_e_mem_6_sink_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_e_mem_7_sink = auto_out_e_mem_7_sink_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_e_widx = auto_out_e_widx_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_e_safe_widx_valid = auto_out_e_safe_widx_valid_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_e_safe_source_reset_n = auto_out_e_safe_source_reset_n_0; // @[AsyncCrossing.scala:23:9]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File AsyncQueue.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
case class AsyncQueueParams(
depth: Int = 8,
sync: Int = 3,
safe: Boolean = true,
// If safe is true, then effort is made to resynchronize the crossing indices when either side is reset.
// This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty.
narrow: Boolean = false)
// If narrow is true then the read mux is moved to the source side of the crossing.
// This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing,
// at the expense of a combinational path from the sink to the source and back to the sink.
{
require (depth > 0 && isPow2(depth))
require (sync >= 2)
val bits = log2Ceil(depth)
val wires = if (narrow) 1 else depth
}
object AsyncQueueParams {
// When there is only one entry, we don't need narrow.
def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false)
}
class AsyncBundleSafety extends Bundle {
val ridx_valid = Input (Bool())
val widx_valid = Output(Bool())
val source_reset_n = Output(Bool())
val sink_reset_n = Input (Bool())
}
class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle {
// Data-path synchronization
val mem = Output(Vec(params.wires, gen))
val ridx = Input (UInt((params.bits+1).W))
val widx = Output(UInt((params.bits+1).W))
val index = params.narrow.option(Input(UInt(params.bits.W)))
// Signals used to self-stabilize a safe AsyncQueue
val safe = params.safe.option(new AsyncBundleSafety)
}
object GrayCounter {
def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = {
val incremented = Wire(UInt(bits.W))
val binary = RegNext(next=incremented, init=0.U).suggestName(name)
incremented := Mux(clear, 0.U, binary + increment.asUInt)
incremented ^ (incremented >> 1)
}
}
class AsyncValidSync(sync: Int, desc: String) extends RawModule {
val io = IO(new Bundle {
val in = Input(Bool())
val out = Output(Bool())
})
val clock = IO(Input(Clock()))
val reset = IO(Input(AsyncReset()))
withClockAndReset(clock, reset){
io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc))
}
}
class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSource_${gen.typeName}"
val io = IO(new Bundle {
// These come from the source domain
val enq = Flipped(Decoupled(gen))
// These cross to the sink clock domain
val async = new AsyncBundle(gen, params)
})
val bits = params.bits
val sink_ready = WireInit(true.B)
val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all.
val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin"))
val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray"))
val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U)
val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1))
when (io.enq.fire) { mem(index) := io.enq.bits }
val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg"))
io.enq.ready := ready_reg && sink_ready
val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray"))
io.async.widx := widx_reg
io.async.index match {
case Some(index) => io.async.mem(0) := mem(index)
case None => io.async.mem := mem
}
io.async.safe.foreach { sio =>
val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0"))
val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1"))
val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend"))
val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid"))
source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_valid .reset := reset.asAsyncReset
source_valid_0.clock := clock
source_valid_1.clock := clock
sink_extend .clock := clock
sink_valid .clock := clock
source_valid_0.io.in := true.B
source_valid_1.io.in := source_valid_0.io.out
sio.widx_valid := source_valid_1.io.out
sink_extend.io.in := sio.ridx_valid
sink_valid.io.in := sink_extend.io.out
sink_ready := sink_valid.io.out
sio.source_reset_n := !reset.asBool
// Assert that if there is stuff in the queue, then reset cannot happen
// Impossible to write because dequeue can occur on the receiving side,
// then reset allowed to happen, but write side cannot know that dequeue
// occurred.
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
// assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected")
// assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty")
}
}
class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSink_${gen.typeName}"
val io = IO(new Bundle {
// These come from the sink domain
val deq = Decoupled(gen)
// These cross to the source clock domain
val async = Flipped(new AsyncBundle(gen, params))
})
val bits = params.bits
val source_ready = WireInit(true.B)
val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin"))
val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray"))
val valid = source_ready && ridx =/= widx
// The mux is safe because timing analysis ensures ridx has reached the register
// On an ASIC, changes to the unread location cannot affect the selected value
// On an FPGA, only one input changes at a time => mem updates don't cause glitches
// The register only latches when the selected valued is not being written
val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1))
io.async.index.foreach { _ := index }
// This register does not NEED to be reset, as its contents will not
// be considered unless the asynchronously reset deq valid register is set.
// It is possible that bits latches when the source domain is reset / has power cut
// This is safe, because isolation gates brought mem low before the zeroed widx reached us
val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index)
io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg"))
val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg"))
io.deq.valid := valid_reg && source_ready
val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray"))
io.async.ridx := ridx_reg
io.async.safe.foreach { sio =>
val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0"))
val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1"))
val source_extend = Module(new AsyncValidSync(params.sync, "source_extend"))
val source_valid = Module(new AsyncValidSync(params.sync, "source_valid"))
sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_valid .reset := reset.asAsyncReset
sink_valid_0 .clock := clock
sink_valid_1 .clock := clock
source_extend.clock := clock
source_valid .clock := clock
sink_valid_0.io.in := true.B
sink_valid_1.io.in := sink_valid_0.io.out
sio.ridx_valid := sink_valid_1.io.out
source_extend.io.in := sio.widx_valid
source_valid.io.in := source_extend.io.out
source_ready := source_valid.io.out
sio.sink_reset_n := !reset.asBool
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
//
// val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool
// val reset_and_extend_prev = RegNext(reset_and_extend, true.B)
// val reset_rise = !reset_and_extend_prev && reset_and_extend
// val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0)
// assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty")
}
}
object FromAsyncBundle
{
// Sometimes it makes sense for the sink to have different sync than the source
def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync)
def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = {
val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync)))
sink.io.async <> x
sink.io.deq
}
}
object ToAsyncBundle
{
def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = {
val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params))
source.io.enq <> x
source.io.async
}
}
class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] {
val io = IO(new CrossingIO(gen))
val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) }
val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) }
source.io.enq <> io.enq
io.deq <> sink.io.deq
sink.io.async <> source.io.async
}
| module AsyncValidSync_58( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_68 io_out_sink_extend ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
| module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_160( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19]
wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to the following Chisel files.
File Directory.scala:
/*
* Copyright 2019 SiFive, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You should have received a copy of LICENSE.Apache2 along with
* this software. If not, you may obtain a copy at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package sifive.blocks.inclusivecache
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import MetaData._
import chisel3.experimental.dataview._
import freechips.rocketchip.util.DescribedSRAM
class DirectoryEntry(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params)
{
val dirty = Bool() // true => TRUNK or TIP
val state = UInt(params.stateBits.W)
val clients = UInt(params.clientBits.W)
val tag = UInt(params.tagBits.W)
}
class DirectoryWrite(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params)
{
val set = UInt(params.setBits.W)
val way = UInt(params.wayBits.W)
val data = new DirectoryEntry(params)
}
class DirectoryRead(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params)
{
val set = UInt(params.setBits.W)
val tag = UInt(params.tagBits.W)
}
class DirectoryResult(params: InclusiveCacheParameters) extends DirectoryEntry(params)
{
val hit = Bool()
val way = UInt(params.wayBits.W)
}
class Directory(params: InclusiveCacheParameters) extends Module
{
val io = IO(new Bundle {
val write = Flipped(Decoupled(new DirectoryWrite(params)))
val read = Flipped(Valid(new DirectoryRead(params))) // sees same-cycle write
val result = Valid(new DirectoryResult(params))
val ready = Bool() // reset complete; can enable access
})
val codeBits = new DirectoryEntry(params).getWidth
val cc_dir = DescribedSRAM(
name = "cc_dir",
desc = "Directory RAM",
size = params.cache.sets,
data = Vec(params.cache.ways, UInt(codeBits.W))
)
val write = Queue(io.write, 1) // must inspect contents => max size 1
// a flow Q creates a WaR hazard... this MIGHT not cause a problem
// a pipe Q causes combinational loop through the scheduler
// Wiping the Directory with 0s on reset has ultimate priority
val wipeCount = RegInit(0.U((params.setBits + 1).W))
val wipeOff = RegNext(false.B, true.B) // don't wipe tags during reset
val wipeDone = wipeCount(params.setBits)
val wipeSet = wipeCount(params.setBits - 1,0)
io.ready := wipeDone
when (!wipeDone && !wipeOff) { wipeCount := wipeCount + 1.U }
assert (wipeDone || !io.read.valid)
// Be explicit for dumb 1-port inference
val ren = io.read.valid
val wen = (!wipeDone && !wipeOff) || write.valid
assert (!io.read.valid || wipeDone)
require (codeBits <= 256)
write.ready := !io.read.valid
when (!ren && wen) {
cc_dir.write(
Mux(wipeDone, write.bits.set, wipeSet),
VecInit.fill(params.cache.ways) { Mux(wipeDone, write.bits.data.asUInt, 0.U) },
UIntToOH(write.bits.way, params.cache.ways).asBools.map(_ || !wipeDone))
}
val ren1 = RegInit(false.B)
val ren2 = if (params.micro.dirReg) RegInit(false.B) else ren1
ren2 := ren1
ren1 := ren
val bypass_valid = params.dirReg(write.valid)
val bypass = params.dirReg(write.bits, ren1 && write.valid)
val regout = params.dirReg(cc_dir.read(io.read.bits.set, ren), ren1)
val tag = params.dirReg(RegEnable(io.read.bits.tag, ren), ren1)
val set = params.dirReg(RegEnable(io.read.bits.set, ren), ren1)
// Compute the victim way in case of an evicition
val victimLFSR = random.LFSR(width = 16, params.dirReg(ren))(InclusiveCacheParameters.lfsrBits-1, 0)
val victimSums = Seq.tabulate(params.cache.ways) { i => ((1 << InclusiveCacheParameters.lfsrBits)*i / params.cache.ways).U }
val victimLTE = Cat(victimSums.map { _ <= victimLFSR }.reverse)
val victimSimp = Cat(0.U(1.W), victimLTE(params.cache.ways-1, 1), 1.U(1.W))
val victimWayOH = victimSimp(params.cache.ways-1,0) & ~(victimSimp >> 1)
val victimWay = OHToUInt(victimWayOH)
assert (!ren2 || victimLTE(0) === 1.U)
assert (!ren2 || ((victimSimp >> 1) & ~victimSimp) === 0.U) // monotone
assert (!ren2 || PopCount(victimWayOH) === 1.U)
val setQuash = bypass_valid && bypass.set === set
val tagMatch = bypass.data.tag === tag
val wayMatch = bypass.way === victimWay
val ways = regout.map(d => d.asTypeOf(new DirectoryEntry(params)))
val hits = Cat(ways.zipWithIndex.map { case (w, i) =>
w.tag === tag && w.state =/= INVALID && (!setQuash || i.U =/= bypass.way)
}.reverse)
val hit = hits.orR
io.result.valid := ren2
io.result.bits.viewAsSupertype(chiselTypeOf(bypass.data)) := Mux(hit, Mux1H(hits, ways), Mux(setQuash && (tagMatch || wayMatch), bypass.data, Mux1H(victimWayOH, ways)))
io.result.bits.hit := hit || (setQuash && tagMatch && bypass.data.state =/= INVALID)
io.result.bits.way := Mux(hit, OHToUInt(hits), Mux(setQuash && tagMatch, bypass.way, victimWay))
params.ccover(ren2 && setQuash && tagMatch, "DIRECTORY_HIT_BYPASS", "Bypassing write to a directory hit")
params.ccover(ren2 && setQuash && !tagMatch && wayMatch, "DIRECTORY_EVICT_BYPASS", "Bypassing a write to a directory eviction")
def json: String = s"""{"clients":${params.clientBits},"mem":"${cc_dir.pathName}","clean":"${wipeDone.pathName}"}"""
}
File DescribedSRAM.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3.{Data, SyncReadMem, Vec}
import chisel3.util.log2Ceil
object DescribedSRAM {
def apply[T <: Data](
name: String,
desc: String,
size: BigInt, // depth
data: T
): SyncReadMem[T] = {
val mem = SyncReadMem(size, data)
mem.suggestName(name)
val granWidth = data match {
case v: Vec[_] => v.head.getWidth
case d => d.getWidth
}
val uid = 0
Annotated.srams(
component = mem,
name = name,
address_width = log2Ceil(size),
data_width = data.getWidth,
depth = size,
description = desc,
write_mask_granularity = granWidth
)
mem
}
}
| module Directory( // @[Directory.scala:56:7]
input clock, // @[Directory.scala:56:7]
input reset, // @[Directory.scala:56:7]
output io_write_ready, // @[Directory.scala:58:14]
input io_write_valid, // @[Directory.scala:58:14]
input [9:0] io_write_bits_set, // @[Directory.scala:58:14]
input [2:0] io_write_bits_way, // @[Directory.scala:58:14]
input io_write_bits_data_dirty, // @[Directory.scala:58:14]
input [1:0] io_write_bits_data_state, // @[Directory.scala:58:14]
input [7:0] io_write_bits_data_clients, // @[Directory.scala:58:14]
input [10:0] io_write_bits_data_tag, // @[Directory.scala:58:14]
input io_read_valid, // @[Directory.scala:58:14]
input [9:0] io_read_bits_set, // @[Directory.scala:58:14]
input [10:0] io_read_bits_tag, // @[Directory.scala:58:14]
output io_result_bits_dirty, // @[Directory.scala:58:14]
output [1:0] io_result_bits_state, // @[Directory.scala:58:14]
output [7:0] io_result_bits_clients, // @[Directory.scala:58:14]
output [10:0] io_result_bits_tag, // @[Directory.scala:58:14]
output io_result_bits_hit, // @[Directory.scala:58:14]
output [2:0] io_result_bits_way, // @[Directory.scala:58:14]
output io_ready // @[Directory.scala:58:14]
);
wire cc_dir_MPORT_mask_7; // @[Directory.scala:100:65]
wire cc_dir_MPORT_mask_6; // @[Directory.scala:100:65]
wire cc_dir_MPORT_mask_5; // @[Directory.scala:100:65]
wire cc_dir_MPORT_mask_4; // @[Directory.scala:100:65]
wire cc_dir_MPORT_mask_3; // @[Directory.scala:100:65]
wire cc_dir_MPORT_mask_2; // @[Directory.scala:100:65]
wire cc_dir_MPORT_mask_1; // @[Directory.scala:100:65]
wire cc_dir_MPORT_mask_0; // @[Directory.scala:100:65]
wire [21:0] cc_dir_MPORT_data_7; // @[Directory.scala:99:44]
wire [9:0] cc_dir_MPORT_addr; // @[Directory.scala:98:10]
wire cc_dir_MPORT_en; // @[Directory.scala:96:14]
wire _victimLFSR_prng_io_out_0; // @[PRNG.scala:91:22]
wire _victimLFSR_prng_io_out_1; // @[PRNG.scala:91:22]
wire _victimLFSR_prng_io_out_2; // @[PRNG.scala:91:22]
wire _victimLFSR_prng_io_out_3; // @[PRNG.scala:91:22]
wire _victimLFSR_prng_io_out_4; // @[PRNG.scala:91:22]
wire _victimLFSR_prng_io_out_5; // @[PRNG.scala:91:22]
wire _victimLFSR_prng_io_out_6; // @[PRNG.scala:91:22]
wire _victimLFSR_prng_io_out_7; // @[PRNG.scala:91:22]
wire _victimLFSR_prng_io_out_8; // @[PRNG.scala:91:22]
wire _victimLFSR_prng_io_out_9; // @[PRNG.scala:91:22]
wire _write_q_io_deq_valid; // @[Decoupled.scala:362:21]
wire [9:0] _write_q_io_deq_bits_set; // @[Decoupled.scala:362:21]
wire [2:0] _write_q_io_deq_bits_way; // @[Decoupled.scala:362:21]
wire _write_q_io_deq_bits_data_dirty; // @[Decoupled.scala:362:21]
wire [1:0] _write_q_io_deq_bits_data_state; // @[Decoupled.scala:362:21]
wire [7:0] _write_q_io_deq_bits_data_clients; // @[Decoupled.scala:362:21]
wire [10:0] _write_q_io_deq_bits_data_tag; // @[Decoupled.scala:362:21]
wire [175:0] _cc_dir_RW0_rdata; // @[DescribedSRAM.scala:17:26]
reg [10:0] wipeCount; // @[Directory.scala:79:26]
reg wipeOff; // @[Directory.scala:80:24]
assign cc_dir_MPORT_en = ~io_read_valid & (~(wipeCount[10]) & ~wipeOff | _write_q_io_deq_valid); // @[Decoupled.scala:362:21]
assign cc_dir_MPORT_addr = wipeCount[10] ? _write_q_io_deq_bits_set : wipeCount[9:0]; // @[Decoupled.scala:362:21]
assign cc_dir_MPORT_data_7 = wipeCount[10] ? {_write_q_io_deq_bits_data_dirty, _write_q_io_deq_bits_data_state, _write_q_io_deq_bits_data_clients, _write_q_io_deq_bits_data_tag} : 22'h0; // @[Decoupled.scala:362:21]
assign cc_dir_MPORT_mask_0 = _write_q_io_deq_bits_way == 3'h0 | ~(wipeCount[10]); // @[Decoupled.scala:362:21]
assign cc_dir_MPORT_mask_1 = _write_q_io_deq_bits_way == 3'h1 | ~(wipeCount[10]); // @[Decoupled.scala:362:21]
assign cc_dir_MPORT_mask_2 = _write_q_io_deq_bits_way == 3'h2 | ~(wipeCount[10]); // @[Decoupled.scala:362:21]
assign cc_dir_MPORT_mask_3 = _write_q_io_deq_bits_way == 3'h3 | ~(wipeCount[10]); // @[Decoupled.scala:362:21]
assign cc_dir_MPORT_mask_4 = _write_q_io_deq_bits_way == 3'h4 | ~(wipeCount[10]); // @[Decoupled.scala:362:21]
assign cc_dir_MPORT_mask_5 = _write_q_io_deq_bits_way == 3'h5 | ~(wipeCount[10]); // @[Decoupled.scala:362:21]
assign cc_dir_MPORT_mask_6 = _write_q_io_deq_bits_way == 3'h6 | ~(wipeCount[10]); // @[Decoupled.scala:362:21]
assign cc_dir_MPORT_mask_7 = (&_write_q_io_deq_bits_way) | ~(wipeCount[10]); // @[Decoupled.scala:362:21]
reg ren1; // @[Directory.scala:103:21]
reg [10:0] tag; // @[Directory.scala:111:36]
reg [9:0] set; // @[Directory.scala:112:36]
wire [9:0] victimLFSR = {_victimLFSR_prng_io_out_9, _victimLFSR_prng_io_out_8, _victimLFSR_prng_io_out_7, _victimLFSR_prng_io_out_6, _victimLFSR_prng_io_out_5, _victimLFSR_prng_io_out_4, _victimLFSR_prng_io_out_3, _victimLFSR_prng_io_out_2, _victimLFSR_prng_io_out_1, _victimLFSR_prng_io_out_0}; // @[PRNG.scala:91:22]
wire [2:0] _GEN = {_victimLFSR_prng_io_out_9, _victimLFSR_prng_io_out_8, _victimLFSR_prng_io_out_7}; // @[PRNG.scala:91:22]
wire [1:0] _GEN_0 = {_victimLFSR_prng_io_out_9, _victimLFSR_prng_io_out_8}; // @[PRNG.scala:91:22]
wire _victimLTE_T_3 = victimLFSR > 10'h17F; // @[Directory.scala:115:63, :117:43]
wire _victimLTE_T_5 = victimLFSR > 10'h27F; // @[Directory.scala:115:63, :117:43]
wire _victimLTE_T_6 = victimLFSR > 10'h2FF; // @[Directory.scala:115:63, :117:43]
wire _victimLTE_T_7 = victimLFSR > 10'h37F; // @[Directory.scala:115:63, :117:43]
wire [3:0] victimWay_hi = {_victimLTE_T_7, _victimLTE_T_6, _victimLTE_T_5, _victimLFSR_prng_io_out_9} & {1'h1, ~_victimLTE_T_7, ~_victimLTE_T_6, ~_victimLTE_T_5}; // @[PRNG.scala:91:22]
wire [2:0] _victimWay_T_1 = victimWay_hi[3:1] | {_victimLTE_T_3, |_GEN_0, |_GEN} & {~_victimLFSR_prng_io_out_9, ~_victimLTE_T_3, ~(|_GEN_0)}; // @[PRNG.scala:91:22]
wire [2:0] victimWay = {|victimWay_hi, |(_victimWay_T_1[2:1]), _victimWay_T_1[2] | _victimWay_T_1[0]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}]
wire _view__T_71 = (|_GEN) & ~(|_GEN_0); // @[Directory.scala:117:43, :119:{55,57}, :123:28]
wire _view__T_72 = (|_GEN_0) & ~_victimLTE_T_3; // @[Directory.scala:117:43, :119:{55,57}, :123:28]
wire _view__T_73 = _victimLTE_T_3 & ~_victimLFSR_prng_io_out_9; // @[PRNG.scala:91:22]
wire _view__T_74 = _victimLFSR_prng_io_out_9 & ~_victimLTE_T_5; // @[PRNG.scala:91:22]
wire _view__T_75 = _victimLTE_T_5 & ~_victimLTE_T_6; // @[Directory.scala:117:43, :119:{55,57}, :123:28]
wire _view__T_76 = _victimLTE_T_6 & ~_victimLTE_T_7; // @[Directory.scala:117:43, :119:{55,57}, :123:28] |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Bundles.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import freechips.rocketchip.util._
import scala.collection.immutable.ListMap
import chisel3.util.Decoupled
import chisel3.util.DecoupledIO
import chisel3.reflect.DataMirror
abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle
// common combos in lazy policy:
// Put + Acquire
// Release + AccessAck
object TLMessages
{
// A B C D E
def PutFullData = 0.U // . . => AccessAck
def PutPartialData = 1.U // . . => AccessAck
def ArithmeticData = 2.U // . . => AccessAckData
def LogicalData = 3.U // . . => AccessAckData
def Get = 4.U // . . => AccessAckData
def Hint = 5.U // . . => HintAck
def AcquireBlock = 6.U // . => Grant[Data]
def AcquirePerm = 7.U // . => Grant[Data]
def Probe = 6.U // . => ProbeAck[Data]
def AccessAck = 0.U // . .
def AccessAckData = 1.U // . .
def HintAck = 2.U // . .
def ProbeAck = 4.U // .
def ProbeAckData = 5.U // .
def Release = 6.U // . => ReleaseAck
def ReleaseData = 7.U // . => ReleaseAck
def Grant = 4.U // . => GrantAck
def GrantData = 5.U // . => GrantAck
def ReleaseAck = 6.U // .
def GrantAck = 0.U // .
def isA(x: UInt) = x <= AcquirePerm
def isB(x: UInt) = x <= Probe
def isC(x: UInt) = x <= ReleaseData
def isD(x: UInt) = x <= ReleaseAck
def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant)
def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck)
def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("AcquireBlock",TLPermissions.PermMsgGrow),
("AcquirePerm",TLPermissions.PermMsgGrow))
def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("Probe",TLPermissions.PermMsgCap))
def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("ProbeAck",TLPermissions.PermMsgReport),
("ProbeAckData",TLPermissions.PermMsgReport),
("Release",TLPermissions.PermMsgReport),
("ReleaseData",TLPermissions.PermMsgReport))
def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("Grant",TLPermissions.PermMsgCap),
("GrantData",TLPermissions.PermMsgCap),
("ReleaseAck",TLPermissions.PermMsgReserved))
}
/**
* The three primary TileLink permissions are:
* (T)runk: the agent is (or is on inwards path to) the global point of serialization.
* (B)ranch: the agent is on an outwards path to
* (N)one:
* These permissions are permuted by transfer operations in various ways.
* Operations can cap permissions, request for them to be grown or shrunk,
* or for a report on their current status.
*/
object TLPermissions
{
val aWidth = 2
val bdWidth = 2
val cWidth = 3
// Cap types (Grant = new permissions, Probe = permisions <= target)
def toT = 0.U(bdWidth.W)
def toB = 1.U(bdWidth.W)
def toN = 2.U(bdWidth.W)
def isCap(x: UInt) = x <= toN
// Grow types (Acquire = permissions >= target)
def NtoB = 0.U(aWidth.W)
def NtoT = 1.U(aWidth.W)
def BtoT = 2.U(aWidth.W)
def isGrow(x: UInt) = x <= BtoT
// Shrink types (ProbeAck, Release)
def TtoB = 0.U(cWidth.W)
def TtoN = 1.U(cWidth.W)
def BtoN = 2.U(cWidth.W)
def isShrink(x: UInt) = x <= BtoN
// Report types (ProbeAck, Release)
def TtoT = 3.U(cWidth.W)
def BtoB = 4.U(cWidth.W)
def NtoN = 5.U(cWidth.W)
def isReport(x: UInt) = x <= NtoN
def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT")
def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN")
def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN")
def PermMsgReserved:Seq[String] = Seq("Reserved")
}
object TLAtomics
{
val width = 3
// Arithmetic types
def MIN = 0.U(width.W)
def MAX = 1.U(width.W)
def MINU = 2.U(width.W)
def MAXU = 3.U(width.W)
def ADD = 4.U(width.W)
def isArithmetic(x: UInt) = x <= ADD
// Logical types
def XOR = 0.U(width.W)
def OR = 1.U(width.W)
def AND = 2.U(width.W)
def SWAP = 3.U(width.W)
def isLogical(x: UInt) = x <= SWAP
def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD")
def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP")
}
object TLHints
{
val width = 1
def PREFETCH_READ = 0.U(width.W)
def PREFETCH_WRITE = 1.U(width.W)
def isHints(x: UInt) = x <= PREFETCH_WRITE
def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite")
}
sealed trait TLChannel extends TLBundleBase {
val channelName: String
}
sealed trait TLDataChannel extends TLChannel
sealed trait TLAddrChannel extends TLDataChannel
final class TLBundleA(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleA_${params.shortName}"
val channelName = "'A' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleB(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleB_${params.shortName}"
val channelName = "'B' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val address = UInt(params.addressBits.W) // from
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleC(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleC_${params.shortName}"
val channelName = "'C' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.cWidth.W) // shrink or report perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleD(params: TLBundleParameters)
extends TLBundleBase(params) with TLDataChannel
{
override def typeName = s"TLBundleD_${params.shortName}"
val channelName = "'D' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val sink = UInt(params.sinkBits.W) // from
val denied = Bool() // implies corrupt iff *Data
val user = BundleMap(params.responseFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleE(params: TLBundleParameters)
extends TLBundleBase(params) with TLChannel
{
override def typeName = s"TLBundleE_${params.shortName}"
val channelName = "'E' channel"
val sink = UInt(params.sinkBits.W) // to
}
class TLBundle(val params: TLBundleParameters) extends Record
{
// Emulate a Bundle with elements abcde or ad depending on params.hasBCE
private val optA = Some (Decoupled(new TLBundleA(params)))
private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params))))
private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params)))
private val optD = Some (Flipped(Decoupled(new TLBundleD(params))))
private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params)))
def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params)))))
def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params)))))
def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params)))))
def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params)))))
def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params)))))
val elements =
if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a)
else ListMap("d" -> d, "a" -> a)
def tieoff(): Unit = {
DataMirror.specifiedDirectionOf(a.ready) match {
case SpecifiedDirection.Input =>
a.ready := false.B
c.ready := false.B
e.ready := false.B
b.valid := false.B
d.valid := false.B
case SpecifiedDirection.Output =>
a.valid := false.B
c.valid := false.B
e.valid := false.B
b.ready := false.B
d.ready := false.B
case _ =>
}
}
}
object TLBundle
{
def apply(params: TLBundleParameters) = new TLBundle(params)
}
class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle
class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params)
{
val a = new AsyncBundle(new TLBundleA(params.base), params.async)
val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async))
val c = new AsyncBundle(new TLBundleC(params.base), params.async)
val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async))
val e = new AsyncBundle(new TLBundleE(params.base), params.async)
}
class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = RationalIO(new TLBundleA(params))
val b = Flipped(RationalIO(new TLBundleB(params)))
val c = RationalIO(new TLBundleC(params))
val d = Flipped(RationalIO(new TLBundleD(params)))
val e = RationalIO(new TLBundleE(params))
}
class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = CreditedIO(new TLBundleA(params))
val b = Flipped(CreditedIO(new TLBundleB(params)))
val c = CreditedIO(new TLBundleC(params))
val d = Flipped(CreditedIO(new TLBundleD(params)))
val e = CreditedIO(new TLBundleE(params))
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor_22( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [25:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [25:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59]
wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27]
wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25]
wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_41 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_45 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_47 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_57 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_59 = 1'h1; // @[Parameters.scala:57:20]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28]
wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_first_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_first_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_first_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_first_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_set_wo_ready_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_set_wo_ready_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_opcodes_set_interm_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_opcodes_set_interm_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_sizes_set_interm_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_sizes_set_interm_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_opcodes_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_opcodes_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_sizes_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_sizes_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_probe_ack_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_probe_ack_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_probe_ack_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_probe_ack_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _same_cycle_resp_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _same_cycle_resp_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _same_cycle_resp_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _same_cycle_resp_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _same_cycle_resp_WIRE_4_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _same_cycle_resp_WIRE_5_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54]
wire [1026:0] _c_sizes_set_T_1 = 1027'h0; // @[Monitor.scala:768:52]
wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79]
wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51]
wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35]
wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35]
wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34]
wire [259:0] c_sizes_set = 260'h0; // @[Monitor.scala:741:34]
wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34]
wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34]
wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46]
wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76]
wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire _source_ok_T_25 = io_in_a_bits_source_0 == 7'h20; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31]
wire _source_ok_T_26 = io_in_a_bits_source_0 == 7'h21; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31]
wire _source_ok_T_27 = io_in_a_bits_source_0 == 7'h22; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_7 = _source_ok_T_27; // @[Parameters.scala:1138:31]
wire _source_ok_T_28 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_8 = _source_ok_T_28; // @[Parameters.scala:1138:31]
wire _source_ok_T_29 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_30 = _source_ok_T_29 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_31 = _source_ok_T_30 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_32 = _source_ok_T_31 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_33 = _source_ok_T_32 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_34 = _source_ok_T_33 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_35 = _source_ok_T_34 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_35 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46]
wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [25:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 26'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_36 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_36; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_37 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_43 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_49 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_55 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_38 = _source_ok_T_37 == 5'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_42 = _source_ok_T_40; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_42; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_44 = _source_ok_T_43 == 5'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_46 = _source_ok_T_44; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_48 = _source_ok_T_46; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_48; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_50 = _source_ok_T_49 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_54; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_56 = _source_ok_T_55 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_58 = _source_ok_T_56; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_60 = _source_ok_T_58; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_60; // @[Parameters.scala:1138:31]
wire _source_ok_T_61 = io_in_d_bits_source_0 == 7'h20; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_5 = _source_ok_T_61; // @[Parameters.scala:1138:31]
wire _source_ok_T_62 = io_in_d_bits_source_0 == 7'h21; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_6 = _source_ok_T_62; // @[Parameters.scala:1138:31]
wire _source_ok_T_63 = io_in_d_bits_source_0 == 7'h22; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_7 = _source_ok_T_63; // @[Parameters.scala:1138:31]
wire _source_ok_T_64 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_8 = _source_ok_T_64; // @[Parameters.scala:1138:31]
wire _source_ok_T_65 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_66 = _source_ok_T_65 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_67 = _source_ok_T_66 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_68 = _source_ok_T_67 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_69 = _source_ok_T_68 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_70 = _source_ok_T_69 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_71 = _source_ok_T_70 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_71 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46]
wire _T_1101 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1101; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1101; // @[Decoupled.scala:51:35]
wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [6:0] source; // @[Monitor.scala:390:22]
reg [25:0] address; // @[Monitor.scala:391:22]
wire _T_1174 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1174; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1174; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1174; // @[Decoupled.scala:51:35]
wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [6:0] source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [64:0] inflight; // @[Monitor.scala:614:27]
reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [259:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [64:0] a_set; // @[Monitor.scala:626:34]
wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [259:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [259:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [259:0] _a_size_lookup_T_6 = {256'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [259:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[259:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [127:0] _GEN_2 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [127:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1027 = _T_1101 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1027 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1027 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1027 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [9:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1027 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1027 ? _a_sizes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [64:0] d_clr; // @[Monitor.scala:664:34]
wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [259:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_1073 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1073 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1042 = _T_1174 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1042 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1042 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1042 ? _d_sizes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [64:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [259:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [259:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [259:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [259:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [64:0] inflight_1; // @[Monitor.scala:726:35]
wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [259:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [259:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [259:0] _c_size_lookup_T_6 = {256'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [259:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[259:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [64:0] d_clr_1; // @[Monitor.scala:774:34]
wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [259:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1145 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1145 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1127 = _T_1174 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1127 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1127 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1127 ? _d_sizes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113]
wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [259:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [259:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to the following Chisel files.
File EarlyTrapCheck.scala:
package saturn.frontend
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import freechips.rocketchip.rocket._
import freechips.rocketchip.util._
import freechips.rocketchip.tile._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.diplomacy._
import saturn.common._
import saturn.backend.{VectorBackend}
class EarlyTrapCheck(edge: TLEdge, sgSize: Option[BigInt])(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams {
val unified_addresses = AddressSet.unify(edge.manager.managers.map(_.address).flatten)
require(unified_addresses.forall(_.alignment >= (1 << pgIdxBits)),
"Memory devices on this system must be at least page-aligned")
val io = IO(new Bundle {
val sg_base = Input(UInt(coreMaxAddrBits.W))
val busy = Output(Bool())
val s0 = new Bundle {
val in = Input(Valid(new Bundle {
val inst = UInt(32.W)
val pc = UInt(vaddrBitsExtended.W)
val status = new MStatus
val vconfig = new VConfig
val vstart = UInt(log2Ceil(maxVLMax).W)
val rs1 = UInt(xLen.W)
val rs2 = UInt(xLen.W)
val phys = Bool()
}))
val tlb_req = Valid(new TLBReq(3))
}
val s1 = new Bundle {
val inst = Output(new VectorIssueInst)
val rs1 = Input(Valid(UInt(xLen.W)))
val kill = Input(Bool())
val tlb_req = Valid(new TLBReq(3))
val tlb_resp = Input(new TLBResp)
}
val s2 = new Bundle {
val scalar_store_pending = Input(Bool())
val inst = Valid(new VectorIssueInst)
val replay = Output(Bool())
val vstart = Valid(UInt(log2Ceil(maxVLMax).W))
val retire = Output(Bool())
val xcpt = Valid(new Bundle {
val cause = UInt(xLen.W)
val tval = UInt(coreMaxAddrBits.W)
})
val pc = Output(UInt(vaddrBitsExtended.W))
val internal_replay = Valid(new VectorIssueInst)
val issue = Decoupled(new VectorIssueInst)
val vxrm = Input(UInt(2.W))
val frm = Input(UInt(3.W))
}
})
val s1_valid = RegInit(false.B)
val s2_valid = RegInit(false.B)
io.busy := s1_valid || s2_valid
val s0_inst = Wire(new VectorIssueInst)
s0_inst.pc := io.s0.in.bits.pc
s0_inst.bits := io.s0.in.bits.inst
s0_inst.vconfig := io.s0.in.bits.vconfig
s0_inst.vstart := Mux(s1_valid || s2_valid, 0.U, io.s0.in.bits.vstart)
s0_inst.segstart := 0.U
s0_inst.segend := s0_inst.seg_nf
s0_inst.rs1_data := io.s0.in.bits.rs1
s0_inst.rs2_data := io.s0.in.bits.rs2
s0_inst.emul := Mux(io.s0.in.bits.vconfig.vtype.vlmul_sign, 0.U, io.s0.in.bits.vconfig.vtype.vlmul_mag)
s0_inst.page := DontCare
s0_inst.vat := DontCare
s0_inst.debug_id := DontCare
s0_inst.rm := DontCare
s0_inst.fast_sg := false.B
s0_inst.mop := s0_inst.orig_mop
when (s0_inst.vmu && s0_inst.mop === mopUnit) {
val mask_vl = (io.s0.in.bits.vconfig.vl >> 3) + Mux(io.s0.in.bits.vconfig.vl(2,0) === 0.U, 0.U, 1.U)
val whole_vl = (vLen.U >> (s0_inst.mem_elem_size +& 3.U)) * (s0_inst.nf +& 1.U)
s0_inst.vconfig.vl := MuxLookup(s0_inst.umop, io.s0.in.bits.vconfig.vl)(Seq(
(lumopWhole -> whole_vl), (lumopMask -> mask_vl)
))
when (s0_inst.umop === lumopWhole) {
s0_inst.emul := VecInit.tabulate(8)(nf => log2Ceil(nf+1).U)(s0_inst.nf)
}
}
when (!s0_inst.vmu && s0_inst.funct3 === OPIVI && s0_inst.funct6 === OPIFunct6.mvnrr.litValue.U) {
s0_inst.emul := log2_up(s0_inst.imm5, 8)
}
val s0_unit = s0_inst.mop === mopUnit || (s0_inst.mop === mopStrided && io.s0.in.bits.rs2 === ((s0_inst.nf +& 1.U) << s0_inst.mem_elem_size))
val s0_indexed = s0_inst.mop.isOneOf(mopOrdered, mopUnordered)
val s0_base = io.s0.in.bits.rs1 + (((s0_inst.seg_nf +& 1.U) * s0_inst.vstart ) << s0_inst.mem_elem_size)
val s0_bound = io.s0.in.bits.rs1 + (((s0_inst.seg_nf +& 1.U) * s0_inst.vconfig.vl) << s0_inst.mem_elem_size) - 1.U
val s0_single_page = (s0_base >> pgIdxBits) === (s0_bound >> pgIdxBits)
val s0_replay_next_page = s0_inst.vmu && s0_unit && s0_inst.nf === 0.U && !s0_single_page
val s0_iterative = (!s0_single_page || !s0_unit || s0_inst.umop === lumopFF) && !s0_replay_next_page
val s0_fast_sg = s0_iterative && io.s0.in.bits.phys && s0_inst.mop === mopUnordered && s0_inst.seg_nf === 0.U && sgSize.map { size =>
s0_base >= io.sg_base && s0_base < (io.sg_base + size.U)
}.getOrElse(false.B)
val s0_tlb_valid = !s0_iterative && s0_inst.vmu && s0_inst.vstart < s0_inst.vconfig.vl
io.s0.tlb_req.valid := s0_tlb_valid && io.s0.in.valid
io.s0.tlb_req.bits.vaddr := s0_base
io.s0.tlb_req.bits.passthrough := false.B
io.s0.tlb_req.bits.size := s0_inst.mem_elem_size
io.s0.tlb_req.bits.cmd := Mux(s0_inst.opcode(5), M_XWR, M_XRD)
io.s0.tlb_req.bits.prv := io.s0.in.bits.status.prv
io.s0.tlb_req.bits.v := io.s0.in.bits.status.v
// s1_stage
s1_valid := io.s0.in.fire
val s1_inst = RegEnable(s0_inst , io.s0.in.valid)
val s1_iterative = RegEnable(s0_iterative , io.s0.in.valid)
val s1_replay_next_page = RegEnable(s0_replay_next_page, io.s0.in.valid)
val s1_base = RegEnable(s0_base , io.s0.in.valid)
val s1_tlb_valid = RegEnable(s0_tlb_valid , io.s0.in.valid)
val s1_fast_sg = RegEnable(s0_fast_sg , io.s0.in.valid)
val s1_tlb_resp = WireInit(io.s1.tlb_resp)
when (!s1_tlb_valid) {
s1_tlb_resp := 0.U.asTypeOf(new TLBResp)
when (s1_fast_sg) {
s1_tlb_resp.paddr := s1_base
}
}
io.s1.inst := s1_inst
io.s1.tlb_req.valid := RegNext(io.s0.tlb_req.valid, false.B)
io.s1.tlb_req.bits := RegEnable(io.s0.tlb_req.bits, s0_tlb_valid)
// s2 stage
s2_valid := s1_valid && !io.s1.kill
val s2_inst = Reg(new VectorIssueInst)
val s2_base = RegEnable(s1_base, s1_valid)
val s2_iterative = RegEnable(s1_iterative , s1_valid)
val s2_fast_sg = RegEnable(s1_fast_sg , s1_valid)
val s2_replay_next_page = RegEnable(s1_replay_next_page, s1_valid)
when (s1_valid) {
s2_inst := s1_inst
when (io.s1.rs1.valid) { s2_inst.rs1_data := io.s1.rs1.bits }
}
val s2_tlb_resp = RegEnable(s1_tlb_resp, s1_valid)
val s2_xcpts = Seq(
(s2_tlb_resp.pf.st, Causes.store_page_fault.U),
(s2_tlb_resp.pf.ld, Causes.load_page_fault.U),
(s2_tlb_resp.gf.st, Causes.store_guest_page_fault.U),
(s2_tlb_resp.gf.ld, Causes.load_guest_page_fault.U),
(s2_tlb_resp.ae.st, Causes.store_access.U),
(s2_tlb_resp.ae.ld, Causes.load_access.U),
(s2_tlb_resp.ma.st, Causes.misaligned_store.U),
(s2_tlb_resp.ma.ld, Causes.misaligned_load.U)
)
val s2_xcpt = s2_xcpts.map(_._1).orR
val s2_cause = PriorityMux(s2_xcpts)
val s2_go_to_itc = WireInit(s2_inst.vmu && s2_iterative)
val s2_generate_xcpt = WireInit(s2_xcpt)
// masked checks, even in the fast case, need to
// to to ITC to get the precise element+address of the trap
when (s2_inst.vmu && s2_xcpt && !s2_inst.vm) {
s2_go_to_itc := true.B
s2_generate_xcpt := false.B
}
io.s2.inst.valid := s2_valid
io.s2.inst.bits := s2_inst
io.s2.replay := false.B
io.s2.vstart.valid := false.B
io.s2.vstart.bits := 0.U
io.s2.retire := false.B
io.s2.internal_replay.valid := false.B
io.s2.internal_replay.bits := s2_inst
io.s2.internal_replay.bits.rm := Mux(s2_inst.isOpf, io.s2.frm, io.s2.vxrm)
io.s2.xcpt.valid := false.B
io.s2.xcpt.bits.cause := s2_cause
io.s2.xcpt.bits.tval := s2_base
io.s2.pc := s2_inst.pc
io.s2.issue.valid := false.B
io.s2.issue.bits := s2_inst
io.s2.issue.bits.segstart := 0.U
io.s2.issue.bits.segend := s2_inst.seg_nf
io.s2.issue.bits.rm := Mux(s2_inst.isOpf, io.s2.frm, io.s2.vxrm)
io.s2.issue.bits.page := s2_tlb_resp.paddr >> pgIdxBits
val consumed = ((1 << pgIdxBits).U - s2_tlb_resp.paddr(pgIdxBits-1,0)) >> s2_inst.mem_elem_size
when (s2_inst.vmu && s2_replay_next_page) {
io.s2.issue.bits.vconfig.vl := s2_inst.vstart +& consumed
}
when (s2_valid) {
when (!io.s2.issue.ready || (io.s2.scalar_store_pending && s2_inst.vmu)) {
io.s2.replay := true.B
} .elsewhen (s2_inst.vstart =/= 0.U && !s2_inst.vmu) {
io.s2.xcpt.valid := true.B
io.s2.xcpt.bits.cause := Causes.illegal_instruction.U
io.s2.xcpt.bits.tval := s2_inst.pc
} .elsewhen (s2_inst.vstart >= s2_inst.vconfig.vl) {
io.s2.retire := true.B
io.s2.issue.valid := true.B
io.s2.vstart.valid := true.B
} .elsewhen (s2_tlb_resp.miss) {
io.s2.replay := true.B
} .elsewhen (s2_generate_xcpt) {
io.s2.xcpt.valid := true.B
} .elsewhen (s2_inst.vmu && s2_fast_sg) {
io.s2.retire := true.B
io.s2.issue.valid := true.B
io.s2.issue.bits.fast_sg := true.B
io.s2.vstart.valid := true.B
} .elsewhen (s2_go_to_itc) {
io.s2.internal_replay.valid := true.B
} .elsewhen (s2_replay_next_page) {
io.s2.replay := true.B
io.s2.issue.valid := true.B
io.s2.vstart.valid := true.B
io.s2.vstart.bits := s2_inst.vstart +& consumed
} .otherwise {
io.s2.retire := true.B
io.s2.vstart.valid := true.B
io.s2.issue.valid := true.B
}
}
}
| module EarlyTrapCheck( // @[EarlyTrapCheck.scala:15:7]
input clock, // @[EarlyTrapCheck.scala:15:7]
input reset, // @[EarlyTrapCheck.scala:15:7]
output io_busy, // @[EarlyTrapCheck.scala:21:14]
input io_s0_in_valid, // @[EarlyTrapCheck.scala:21:14]
input [31:0] io_s0_in_bits_inst, // @[EarlyTrapCheck.scala:21:14]
input [39:0] io_s0_in_bits_pc, // @[EarlyTrapCheck.scala:21:14]
input [1:0] io_s0_in_bits_status_prv, // @[EarlyTrapCheck.scala:21:14]
input [8:0] io_s0_in_bits_vconfig_vl, // @[EarlyTrapCheck.scala:21:14]
input io_s0_in_bits_vconfig_vtype_vill, // @[EarlyTrapCheck.scala:21:14]
input [54:0] io_s0_in_bits_vconfig_vtype_reserved, // @[EarlyTrapCheck.scala:21:14]
input io_s0_in_bits_vconfig_vtype_vma, // @[EarlyTrapCheck.scala:21:14]
input io_s0_in_bits_vconfig_vtype_vta, // @[EarlyTrapCheck.scala:21:14]
input [2:0] io_s0_in_bits_vconfig_vtype_vsew, // @[EarlyTrapCheck.scala:21:14]
input io_s0_in_bits_vconfig_vtype_vlmul_sign, // @[EarlyTrapCheck.scala:21:14]
input [1:0] io_s0_in_bits_vconfig_vtype_vlmul_mag, // @[EarlyTrapCheck.scala:21:14]
input [7:0] io_s0_in_bits_vstart, // @[EarlyTrapCheck.scala:21:14]
input [63:0] io_s0_in_bits_rs1, // @[EarlyTrapCheck.scala:21:14]
input [63:0] io_s0_in_bits_rs2, // @[EarlyTrapCheck.scala:21:14]
output [31:0] io_s1_inst_bits, // @[EarlyTrapCheck.scala:21:14]
input io_s1_rs1_valid, // @[EarlyTrapCheck.scala:21:14]
input [63:0] io_s1_rs1_bits, // @[EarlyTrapCheck.scala:21:14]
input io_s1_kill, // @[EarlyTrapCheck.scala:21:14]
output io_s1_tlb_req_valid, // @[EarlyTrapCheck.scala:21:14]
output [39:0] io_s1_tlb_req_bits_vaddr, // @[EarlyTrapCheck.scala:21:14]
output [1:0] io_s1_tlb_req_bits_size, // @[EarlyTrapCheck.scala:21:14]
output [4:0] io_s1_tlb_req_bits_cmd, // @[EarlyTrapCheck.scala:21:14]
output [1:0] io_s1_tlb_req_bits_prv, // @[EarlyTrapCheck.scala:21:14]
input io_s1_tlb_resp_miss, // @[EarlyTrapCheck.scala:21:14]
input [31:0] io_s1_tlb_resp_paddr, // @[EarlyTrapCheck.scala:21:14]
input io_s1_tlb_resp_pf_ld, // @[EarlyTrapCheck.scala:21:14]
input io_s1_tlb_resp_pf_st, // @[EarlyTrapCheck.scala:21:14]
input io_s1_tlb_resp_ae_ld, // @[EarlyTrapCheck.scala:21:14]
input io_s1_tlb_resp_ae_st, // @[EarlyTrapCheck.scala:21:14]
input io_s1_tlb_resp_ma_ld, // @[EarlyTrapCheck.scala:21:14]
input io_s1_tlb_resp_ma_st, // @[EarlyTrapCheck.scala:21:14]
input io_s2_scalar_store_pending, // @[EarlyTrapCheck.scala:21:14]
output io_s2_inst_valid, // @[EarlyTrapCheck.scala:21:14]
output [31:0] io_s2_inst_bits_bits, // @[EarlyTrapCheck.scala:21:14]
output io_s2_vstart_valid, // @[EarlyTrapCheck.scala:21:14]
output [7:0] io_s2_vstart_bits, // @[EarlyTrapCheck.scala:21:14]
output io_s2_retire, // @[EarlyTrapCheck.scala:21:14]
output io_s2_xcpt_valid, // @[EarlyTrapCheck.scala:21:14]
output [63:0] io_s2_xcpt_bits_cause, // @[EarlyTrapCheck.scala:21:14]
output [39:0] io_s2_xcpt_bits_tval, // @[EarlyTrapCheck.scala:21:14]
output [39:0] io_s2_pc, // @[EarlyTrapCheck.scala:21:14]
output io_s2_internal_replay_valid, // @[EarlyTrapCheck.scala:21:14]
output [39:0] io_s2_internal_replay_bits_pc, // @[EarlyTrapCheck.scala:21:14]
output [31:0] io_s2_internal_replay_bits_bits, // @[EarlyTrapCheck.scala:21:14]
output [8:0] io_s2_internal_replay_bits_vconfig_vl, // @[EarlyTrapCheck.scala:21:14]
output io_s2_internal_replay_bits_vconfig_vtype_vill, // @[EarlyTrapCheck.scala:21:14]
output [54:0] io_s2_internal_replay_bits_vconfig_vtype_reserved, // @[EarlyTrapCheck.scala:21:14]
output io_s2_internal_replay_bits_vconfig_vtype_vma, // @[EarlyTrapCheck.scala:21:14]
output io_s2_internal_replay_bits_vconfig_vtype_vta, // @[EarlyTrapCheck.scala:21:14]
output [2:0] io_s2_internal_replay_bits_vconfig_vtype_vsew, // @[EarlyTrapCheck.scala:21:14]
output io_s2_internal_replay_bits_vconfig_vtype_vlmul_sign, // @[EarlyTrapCheck.scala:21:14]
output [1:0] io_s2_internal_replay_bits_vconfig_vtype_vlmul_mag, // @[EarlyTrapCheck.scala:21:14]
output [7:0] io_s2_internal_replay_bits_vstart, // @[EarlyTrapCheck.scala:21:14]
output [63:0] io_s2_internal_replay_bits_rs1_data, // @[EarlyTrapCheck.scala:21:14]
output [63:0] io_s2_internal_replay_bits_rs2_data, // @[EarlyTrapCheck.scala:21:14]
output [2:0] io_s2_internal_replay_bits_rm, // @[EarlyTrapCheck.scala:21:14]
output [1:0] io_s2_internal_replay_bits_emul, // @[EarlyTrapCheck.scala:21:14]
output [1:0] io_s2_internal_replay_bits_mop, // @[EarlyTrapCheck.scala:21:14]
input io_s2_issue_ready, // @[EarlyTrapCheck.scala:21:14]
output io_s2_issue_valid, // @[EarlyTrapCheck.scala:21:14]
output [31:0] io_s2_issue_bits_bits, // @[EarlyTrapCheck.scala:21:14]
output [8:0] io_s2_issue_bits_vconfig_vl, // @[EarlyTrapCheck.scala:21:14]
output [2:0] io_s2_issue_bits_vconfig_vtype_vsew, // @[EarlyTrapCheck.scala:21:14]
output io_s2_issue_bits_vconfig_vtype_vlmul_sign, // @[EarlyTrapCheck.scala:21:14]
output [1:0] io_s2_issue_bits_vconfig_vtype_vlmul_mag, // @[EarlyTrapCheck.scala:21:14]
output [7:0] io_s2_issue_bits_vstart, // @[EarlyTrapCheck.scala:21:14]
output [2:0] io_s2_issue_bits_segend, // @[EarlyTrapCheck.scala:21:14]
output [63:0] io_s2_issue_bits_rs1_data, // @[EarlyTrapCheck.scala:21:14]
output [63:0] io_s2_issue_bits_rs2_data, // @[EarlyTrapCheck.scala:21:14]
output [19:0] io_s2_issue_bits_page, // @[EarlyTrapCheck.scala:21:14]
output [2:0] io_s2_issue_bits_rm, // @[EarlyTrapCheck.scala:21:14]
output [1:0] io_s2_issue_bits_emul, // @[EarlyTrapCheck.scala:21:14]
output [1:0] io_s2_issue_bits_mop, // @[EarlyTrapCheck.scala:21:14]
input [1:0] io_s2_vxrm, // @[EarlyTrapCheck.scala:21:14]
input [2:0] io_s2_frm // @[EarlyTrapCheck.scala:21:14]
);
reg s1_valid; // @[EarlyTrapCheck.scala:65:25]
reg s2_valid; // @[EarlyTrapCheck.scala:66:25]
wire io_busy_0 = s1_valid | s2_valid; // @[EarlyTrapCheck.scala:65:25, :66:25, :67:23]
reg [39:0] s1_inst_pc; // @[EarlyTrapCheck.scala:122:38]
reg [31:0] s1_inst_bits; // @[EarlyTrapCheck.scala:122:38]
reg [8:0] s1_inst_vconfig_vl; // @[EarlyTrapCheck.scala:122:38]
reg s1_inst_vconfig_vtype_vill; // @[EarlyTrapCheck.scala:122:38]
reg [54:0] s1_inst_vconfig_vtype_reserved; // @[EarlyTrapCheck.scala:122:38]
reg s1_inst_vconfig_vtype_vma; // @[EarlyTrapCheck.scala:122:38]
reg s1_inst_vconfig_vtype_vta; // @[EarlyTrapCheck.scala:122:38]
reg [2:0] s1_inst_vconfig_vtype_vsew; // @[EarlyTrapCheck.scala:122:38]
reg s1_inst_vconfig_vtype_vlmul_sign; // @[EarlyTrapCheck.scala:122:38]
reg [1:0] s1_inst_vconfig_vtype_vlmul_mag; // @[EarlyTrapCheck.scala:122:38]
reg [7:0] s1_inst_vstart; // @[EarlyTrapCheck.scala:122:38]
reg [63:0] s1_inst_rs1_data; // @[EarlyTrapCheck.scala:122:38]
reg [63:0] s1_inst_rs2_data; // @[EarlyTrapCheck.scala:122:38]
reg [1:0] s1_inst_emul; // @[EarlyTrapCheck.scala:122:38]
reg [1:0] s1_inst_mop; // @[EarlyTrapCheck.scala:122:38]
reg s1_iterative; // @[EarlyTrapCheck.scala:123:38]
reg s1_replay_next_page; // @[EarlyTrapCheck.scala:124:38]
reg [63:0] s1_base; // @[EarlyTrapCheck.scala:125:38]
reg s1_tlb_valid; // @[EarlyTrapCheck.scala:126:38]
reg io_s1_tlb_req_valid_REG; // @[EarlyTrapCheck.scala:138:33]
reg [39:0] io_s1_tlb_req_bits_r_vaddr; // @[EarlyTrapCheck.scala:139:35]
reg [1:0] io_s1_tlb_req_bits_r_size; // @[EarlyTrapCheck.scala:139:35]
reg [4:0] io_s1_tlb_req_bits_r_cmd; // @[EarlyTrapCheck.scala:139:35]
reg [1:0] io_s1_tlb_req_bits_r_prv; // @[EarlyTrapCheck.scala:139:35]
reg [39:0] s2_inst_pc; // @[EarlyTrapCheck.scala:143:20]
reg [31:0] s2_inst_bits; // @[EarlyTrapCheck.scala:143:20]
reg [8:0] s2_inst_vconfig_vl; // @[EarlyTrapCheck.scala:143:20]
reg s2_inst_vconfig_vtype_vill; // @[EarlyTrapCheck.scala:143:20]
reg [54:0] s2_inst_vconfig_vtype_reserved; // @[EarlyTrapCheck.scala:143:20]
reg s2_inst_vconfig_vtype_vma; // @[EarlyTrapCheck.scala:143:20]
reg s2_inst_vconfig_vtype_vta; // @[EarlyTrapCheck.scala:143:20]
reg [2:0] s2_inst_vconfig_vtype_vsew; // @[EarlyTrapCheck.scala:143:20]
reg s2_inst_vconfig_vtype_vlmul_sign; // @[EarlyTrapCheck.scala:143:20]
reg [1:0] s2_inst_vconfig_vtype_vlmul_mag; // @[EarlyTrapCheck.scala:143:20]
reg [7:0] s2_inst_vstart; // @[EarlyTrapCheck.scala:143:20]
reg [63:0] s2_inst_rs1_data; // @[EarlyTrapCheck.scala:143:20]
reg [63:0] s2_inst_rs2_data; // @[EarlyTrapCheck.scala:143:20]
reg [1:0] s2_inst_emul; // @[EarlyTrapCheck.scala:143:20]
reg [1:0] s2_inst_mop; // @[EarlyTrapCheck.scala:143:20]
reg [63:0] s2_base; // @[EarlyTrapCheck.scala:144:26]
reg s2_iterative; // @[EarlyTrapCheck.scala:145:38]
reg s2_replay_next_page; // @[EarlyTrapCheck.scala:147:38]
reg s2_tlb_resp_miss; // @[EarlyTrapCheck.scala:152:30]
reg [31:0] s2_tlb_resp_paddr; // @[EarlyTrapCheck.scala:152:30]
reg s2_tlb_resp_pf_ld; // @[EarlyTrapCheck.scala:152:30]
reg s2_tlb_resp_pf_st; // @[EarlyTrapCheck.scala:152:30]
reg s2_tlb_resp_ae_ld; // @[EarlyTrapCheck.scala:152:30]
reg s2_tlb_resp_ae_st; // @[EarlyTrapCheck.scala:152:30]
reg s2_tlb_resp_ma_ld; // @[EarlyTrapCheck.scala:152:30]
reg s2_tlb_resp_ma_st; // @[EarlyTrapCheck.scala:152:30]
wire s2_xcpt = s2_tlb_resp_pf_st | s2_tlb_resp_pf_ld | s2_tlb_resp_ae_st | s2_tlb_resp_ae_ld | s2_tlb_resp_ma_st | s2_tlb_resp_ma_ld; // @[EarlyTrapCheck.scala:152:30]
wire _GEN = s2_inst_bits[6:0] == 7'h7 | s2_inst_bits[6:0] == 7'h27; // @[EarlyTrapCheck.scala:143:20]
wire _GEN_0 = _GEN & s2_xcpt & ~(s2_inst_bits[25]); // @[EarlyTrapCheck.scala:143:20, :171:{21,32,35}]
wire s2_go_to_itc = _GEN_0 | (s2_inst_bits[6:0] == 7'h7 | s2_inst_bits[6:0] == 7'h27) & s2_iterative; // @[EarlyTrapCheck.scala:143:20, :145:38, :166:{30,43}, :171:{21,32,48}, :172:18]
wire s2_generate_xcpt = ~_GEN_0 & s2_xcpt; // @[EarlyTrapCheck.scala:167:34, :171:{21,32,48}, :173:22]
wire [2:0] _GEN_1 = {1'h0, io_s2_vxrm}; // @[EarlyTrapCheck.scala:184:39]
wire [12:0] consumed = 13'h1000 - {1'h0, s2_tlb_resp_paddr[11:0]} >> (s2_inst_mop[0] ? s2_inst_vconfig_vtype_vsew : {1'h0, s2_inst_bits[13:12]}); // @[EarlyTrapCheck.scala:143:20, :152:30, :196:{38,57,74}]
wire [8:0] _GEN_2 = {1'h0, s2_inst_vstart}; // @[EarlyTrapCheck.scala:143:20, :198:51]
wire _GEN_3 = ~io_s2_issue_ready | io_s2_scalar_store_pending & _GEN; // @[EarlyTrapCheck.scala:202:{11,30,61}]
wire _GEN_4 = (|s2_inst_vstart) & ~_GEN; // @[EarlyTrapCheck.scala:143:20, :204:{33,41,44}]
wire _GEN_5 = ~s2_valid | _GEN_3 | ~_GEN_4; // @[EarlyTrapCheck.scala:66:25, :186:29, :201:19, :202:{30,78}, :204:{41,58}]
wire _GEN_6 = _GEN_2 >= s2_inst_vconfig_vl; // @[EarlyTrapCheck.scala:143:20, :198:51, :208:33]
wire _GEN_7 = s2_tlb_resp_miss | s2_generate_xcpt; // @[EarlyTrapCheck.scala:152:30, :167:34, :171:48, :173:22, :182:33, :212:36, :214:36, :216:45, :221:32]
wire _GEN_8 = _GEN_3 | _GEN_4; // @[EarlyTrapCheck.scala:181:22, :202:{30,78}, :204:{41,58}, :208:56]
wire io_s2_issue_valid_0 = s2_valid & ~_GEN_8 & (_GEN_6 | ~_GEN_7 & ~s2_go_to_itc); // @[EarlyTrapCheck.scala:66:25, :166:30, :171:48, :172:18, :179:22, :181:22, :182:33, :201:19, :202:78, :204:58, :208:{33,56}, :211:26, :212:36, :214:36, :216:45, :221:32, :223:39]
wire [7:0][1:0] _GEN_9 = '{2'h3, 2'h3, 2'h3, 2'h3, 2'h2, 2'h2, 2'h1, 2'h0};
wire [7:0] s0_inst_vstart = io_busy_0 ? 8'h0 : io_s0_in_bits_vstart; // @[EarlyTrapCheck.scala:67:23, :73:26]
wire _GEN_10 = io_s0_in_bits_inst[6:0] == 7'h7 | io_s0_in_bits_inst[6:0] == 7'h27; // @[Bundles.scala:56:20]
wire _s0_unit_T = io_s0_in_bits_inst[27:26] == 2'h0; // @[EarlyTrapCheck.scala:85:36]
wire _GEN_11 = _GEN_10 & _s0_unit_T; // @[EarlyTrapCheck.scala:85:{21,36}]
wire [3:0] _GEN_12 = {1'h0, io_s0_in_bits_inst[31:29]}; // @[EarlyTrapCheck.scala:87:77]
wire [8:0] s0_inst_vconfig_vl = _GEN_11 ? (io_s0_in_bits_inst[24:20] == 5'hB ? {3'h0, io_s0_in_bits_vconfig_vl[8:3] + {5'h0, |(io_s0_in_bits_vconfig_vl[2:0])}} : io_s0_in_bits_inst[24:20] == 5'h8 ? (9'h100 >> {1'h0, io_s0_in_bits_inst[26] ? io_s0_in_bits_vconfig_vtype_vsew : {1'h0, io_s0_in_bits_inst[13:12]}} + 4'h3) * {5'h0, _GEN_12 + 4'h1} : io_s0_in_bits_vconfig_vl) : io_s0_in_bits_vconfig_vl; // @[EarlyTrapCheck.scala:15:7, :72:19, :85:{21,49}, :86:{45,51,81,87}, :87:{28,54,63,77}, :88:{24,76}]
wire [2:0] _GEN_13 = {1'h0, io_s0_in_bits_inst[13:12]}; // @[Bundles.scala:59:{26,59}]
wire s0_unit = _s0_unit_T | io_s0_in_bits_inst[27:26] == 2'h2 & io_s0_in_bits_rs2 == {53'h0, {7'h0, _GEN_12 + 4'h1} << (io_s0_in_bits_inst[26] ? io_s0_in_bits_vconfig_vtype_vsew : _GEN_13)}; // @[EarlyTrapCheck.scala:85:36, :87:77, :88:76, :99:{41,57,72,93,110,118}]
wire [63:0] _s0_base_T_13 = io_s0_in_bits_rs1 + {45'h0, {7'h0, {8'h0, {1'h0, ~(|(io_s0_in_bits_inst[27:26])) & io_s0_in_bits_inst[24:20] == 5'h8 ? 3'h0 : io_s0_in_bits_inst[31:29]} + 4'h1} * {4'h0, s0_inst_vstart}} << (io_s0_in_bits_inst[26] ? io_s0_in_bits_vconfig_vtype_vsew : _GEN_13)}; // @[EarlyTrapCheck.scala:15:7, :73:26, :88:76, :101:{36,56,64,86}]
wire [63:0] _s0_bound_T_15 = io_s0_in_bits_rs1 + {44'h0, {7'h0, {9'h0, {1'h0, ~(|(io_s0_in_bits_inst[27:26])) & io_s0_in_bits_inst[24:20] == 5'h8 ? 3'h0 : io_s0_in_bits_inst[31:29]} + 4'h1} * {4'h0, s0_inst_vconfig_vl}} << (io_s0_in_bits_inst[26] ? io_s0_in_bits_vconfig_vtype_vsew : _GEN_13)} - 64'h1; // @[EarlyTrapCheck.scala:15:7, :72:19, :85:49, :87:63, :88:{24,76}, :102:{36,56,64,86,112}]
wire _s0_iterative_T = _s0_base_T_13[63:12] != _s0_bound_T_15[63:12]; // @[EarlyTrapCheck.scala:101:36, :102:{36,112}, :103:{33,47,61}, :104:77]
wire s0_replay_next_page = (io_s0_in_bits_inst[6:0] == 7'h7 | io_s0_in_bits_inst[6:0] == 7'h27) & s0_unit & io_s0_in_bits_inst[31:29] == 3'h0 & _s0_iterative_T; // @[EarlyTrapCheck.scala:99:41, :103:47, :104:{41,52,66,74,77}]
wire s0_iterative = (_s0_iterative_T | ~s0_unit | io_s0_in_bits_inst[24:20] == 5'h10) & ~s0_replay_next_page; // @[EarlyTrapCheck.scala:15:7, :99:41, :103:47, :104:{41,52,74,77}, :105:{39,42,51,67,80,83}]
wire s0_tlb_valid = ~s0_iterative & (io_s0_in_bits_inst[6:0] == 7'h7 | io_s0_in_bits_inst[6:0] == 7'h27) & {1'h0, s0_inst_vstart} < s0_inst_vconfig_vl; // @[EarlyTrapCheck.scala:72:19, :73:26, :85:49, :88:24, :105:80, :110:{22,36,51,69}]
always @(posedge clock) begin // @[EarlyTrapCheck.scala:15:7]
if (reset) begin // @[EarlyTrapCheck.scala:15:7]
s1_valid <= 1'h0; // @[EarlyTrapCheck.scala:65:25]
s2_valid <= 1'h0; // @[EarlyTrapCheck.scala:66:25]
io_s1_tlb_req_valid_REG <= 1'h0; // @[EarlyTrapCheck.scala:138:33]
end
else begin // @[EarlyTrapCheck.scala:15:7]
s1_valid <= io_s0_in_valid; // @[EarlyTrapCheck.scala:65:25]
s2_valid <= s1_valid & ~io_s1_kill; // @[EarlyTrapCheck.scala:65:25, :66:25, :142:{24,27}]
io_s1_tlb_req_valid_REG <= s0_tlb_valid & io_s0_in_valid; // @[EarlyTrapCheck.scala:110:{36,51}, :112:50, :138:33]
end
if (io_s0_in_valid) begin // @[EarlyTrapCheck.scala:21:14]
s1_inst_pc <= io_s0_in_bits_pc; // @[EarlyTrapCheck.scala:122:38]
s1_inst_bits <= io_s0_in_bits_inst; // @[EarlyTrapCheck.scala:122:38]
s1_inst_vconfig_vl <= s0_inst_vconfig_vl; // @[EarlyTrapCheck.scala:72:19, :85:49, :88:24, :122:38]
s1_inst_vconfig_vtype_vill <= io_s0_in_bits_vconfig_vtype_vill; // @[EarlyTrapCheck.scala:122:38]
s1_inst_vconfig_vtype_reserved <= io_s0_in_bits_vconfig_vtype_reserved; // @[EarlyTrapCheck.scala:122:38]
s1_inst_vconfig_vtype_vma <= io_s0_in_bits_vconfig_vtype_vma; // @[EarlyTrapCheck.scala:122:38]
s1_inst_vconfig_vtype_vta <= io_s0_in_bits_vconfig_vtype_vta; // @[EarlyTrapCheck.scala:122:38]
s1_inst_vconfig_vtype_vsew <= io_s0_in_bits_vconfig_vtype_vsew; // @[EarlyTrapCheck.scala:122:38]
s1_inst_vconfig_vtype_vlmul_sign <= io_s0_in_bits_vconfig_vtype_vlmul_sign; // @[EarlyTrapCheck.scala:122:38]
s1_inst_vconfig_vtype_vlmul_mag <= io_s0_in_bits_vconfig_vtype_vlmul_mag; // @[EarlyTrapCheck.scala:122:38]
s1_inst_vstart <= s0_inst_vstart; // @[EarlyTrapCheck.scala:73:26, :122:38]
s1_inst_rs1_data <= io_s0_in_bits_rs1; // @[EarlyTrapCheck.scala:122:38]
s1_inst_rs2_data <= io_s0_in_bits_rs2; // @[EarlyTrapCheck.scala:122:38]
s1_inst_emul <= ~_GEN_10 & io_s0_in_bits_inst[14:12] == 3'h3 & io_s0_in_bits_inst[31:26] == 6'h27 ? _GEN_9[io_s0_in_bits_inst[17:15]] : _GEN_11 & io_s0_in_bits_inst[24:20] == 5'h8 ? _GEN_9[io_s0_in_bits_inst[31:29]] : io_s0_in_bits_vconfig_vtype_vlmul_sign ? 2'h0 : io_s0_in_bits_vconfig_vtype_vlmul_mag; // @[EarlyTrapCheck.scala:15:7, :78:{20,26}, :85:{21,49}, :91:{24,40}, :92:20, :95:{9,22,40,50,68,100}, :96:18, :122:38]
s1_inst_mop <= io_s0_in_bits_inst[27:26]; // @[EarlyTrapCheck.scala:122:38]
s1_iterative <= s0_iterative; // @[EarlyTrapCheck.scala:105:80, :123:38]
s1_replay_next_page <= s0_replay_next_page; // @[EarlyTrapCheck.scala:104:{41,52,74}, :124:38]
s1_base <= _s0_base_T_13; // @[EarlyTrapCheck.scala:101:36, :125:38]
s1_tlb_valid <= s0_tlb_valid; // @[EarlyTrapCheck.scala:110:{36,51}, :126:38]
end
if (s0_tlb_valid) begin // @[EarlyTrapCheck.scala:110:{36,51}]
io_s1_tlb_req_bits_r_vaddr <= _s0_base_T_13[39:0]; // @[EarlyTrapCheck.scala:101:36, :113:34, :139:35]
io_s1_tlb_req_bits_r_size <= io_s0_in_bits_inst[26] ? io_s0_in_bits_vconfig_vtype_vsew[1:0] : io_s0_in_bits_inst[13:12]; // @[EarlyTrapCheck.scala:21:14, :139:35]
io_s1_tlb_req_bits_r_cmd <= {4'h0, io_s0_in_bits_inst[5]}; // @[EarlyTrapCheck.scala:116:{34,55}, :139:35]
io_s1_tlb_req_bits_r_prv <= io_s0_in_bits_status_prv; // @[EarlyTrapCheck.scala:139:35]
end
if (s1_valid) begin // @[EarlyTrapCheck.scala:65:25]
s2_inst_pc <= s1_inst_pc; // @[EarlyTrapCheck.scala:122:38, :143:20]
s2_inst_bits <= s1_inst_bits; // @[EarlyTrapCheck.scala:122:38, :143:20]
s2_inst_vconfig_vl <= s1_inst_vconfig_vl; // @[EarlyTrapCheck.scala:122:38, :143:20]
s2_inst_vconfig_vtype_vill <= s1_inst_vconfig_vtype_vill; // @[EarlyTrapCheck.scala:122:38, :143:20]
s2_inst_vconfig_vtype_reserved <= s1_inst_vconfig_vtype_reserved; // @[EarlyTrapCheck.scala:122:38, :143:20]
s2_inst_vconfig_vtype_vma <= s1_inst_vconfig_vtype_vma; // @[EarlyTrapCheck.scala:122:38, :143:20]
s2_inst_vconfig_vtype_vta <= s1_inst_vconfig_vtype_vta; // @[EarlyTrapCheck.scala:122:38, :143:20]
s2_inst_vconfig_vtype_vsew <= s1_inst_vconfig_vtype_vsew; // @[EarlyTrapCheck.scala:122:38, :143:20]
s2_inst_vconfig_vtype_vlmul_sign <= s1_inst_vconfig_vtype_vlmul_sign; // @[EarlyTrapCheck.scala:122:38, :143:20]
s2_inst_vconfig_vtype_vlmul_mag <= s1_inst_vconfig_vtype_vlmul_mag; // @[EarlyTrapCheck.scala:122:38, :143:20]
s2_inst_vstart <= s1_inst_vstart; // @[EarlyTrapCheck.scala:122:38, :143:20]
s2_inst_rs1_data <= io_s1_rs1_valid ? io_s1_rs1_bits : s1_inst_rs1_data; // @[EarlyTrapCheck.scala:122:38, :143:20, :149:13, :150:{28,47}]
s2_inst_rs2_data <= s1_inst_rs2_data; // @[EarlyTrapCheck.scala:122:38, :143:20]
s2_inst_emul <= s1_inst_emul; // @[EarlyTrapCheck.scala:122:38, :143:20]
s2_inst_mop <= s1_inst_mop; // @[EarlyTrapCheck.scala:122:38, :143:20]
s2_base <= s1_base; // @[EarlyTrapCheck.scala:125:38, :144:26]
s2_iterative <= s1_iterative; // @[EarlyTrapCheck.scala:123:38, :145:38]
s2_replay_next_page <= s1_replay_next_page; // @[EarlyTrapCheck.scala:124:38, :147:38]
s2_tlb_resp_miss <= s1_tlb_valid & io_s1_tlb_resp_miss; // @[EarlyTrapCheck.scala:126:38, :128:37, :130:24, :131:17, :152:30]
s2_tlb_resp_paddr <= s1_tlb_valid ? io_s1_tlb_resp_paddr : 32'h0; // @[EarlyTrapCheck.scala:126:38, :128:37, :130:24, :132:23, :152:30]
s2_tlb_resp_pf_ld <= s1_tlb_valid & io_s1_tlb_resp_pf_ld; // @[EarlyTrapCheck.scala:126:38, :128:37, :130:24, :131:17, :152:30]
s2_tlb_resp_pf_st <= s1_tlb_valid & io_s1_tlb_resp_pf_st; // @[EarlyTrapCheck.scala:126:38, :128:37, :130:24, :131:17, :152:30]
s2_tlb_resp_ae_ld <= s1_tlb_valid & io_s1_tlb_resp_ae_ld; // @[EarlyTrapCheck.scala:126:38, :128:37, :130:24, :131:17, :152:30]
s2_tlb_resp_ae_st <= s1_tlb_valid & io_s1_tlb_resp_ae_st; // @[EarlyTrapCheck.scala:126:38, :128:37, :130:24, :131:17, :152:30]
s2_tlb_resp_ma_ld <= s1_tlb_valid & io_s1_tlb_resp_ma_ld; // @[EarlyTrapCheck.scala:126:38, :128:37, :130:24, :131:17, :152:30]
s2_tlb_resp_ma_st <= s1_tlb_valid & io_s1_tlb_resp_ma_st; // @[EarlyTrapCheck.scala:126:38, :128:37, :130:24, :131:17, :152:30]
end
always @(posedge) |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File AsyncQueue.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
case class AsyncQueueParams(
depth: Int = 8,
sync: Int = 3,
safe: Boolean = true,
// If safe is true, then effort is made to resynchronize the crossing indices when either side is reset.
// This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty.
narrow: Boolean = false)
// If narrow is true then the read mux is moved to the source side of the crossing.
// This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing,
// at the expense of a combinational path from the sink to the source and back to the sink.
{
require (depth > 0 && isPow2(depth))
require (sync >= 2)
val bits = log2Ceil(depth)
val wires = if (narrow) 1 else depth
}
object AsyncQueueParams {
// When there is only one entry, we don't need narrow.
def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false)
}
class AsyncBundleSafety extends Bundle {
val ridx_valid = Input (Bool())
val widx_valid = Output(Bool())
val source_reset_n = Output(Bool())
val sink_reset_n = Input (Bool())
}
class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle {
// Data-path synchronization
val mem = Output(Vec(params.wires, gen))
val ridx = Input (UInt((params.bits+1).W))
val widx = Output(UInt((params.bits+1).W))
val index = params.narrow.option(Input(UInt(params.bits.W)))
// Signals used to self-stabilize a safe AsyncQueue
val safe = params.safe.option(new AsyncBundleSafety)
}
object GrayCounter {
def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = {
val incremented = Wire(UInt(bits.W))
val binary = RegNext(next=incremented, init=0.U).suggestName(name)
incremented := Mux(clear, 0.U, binary + increment.asUInt)
incremented ^ (incremented >> 1)
}
}
class AsyncValidSync(sync: Int, desc: String) extends RawModule {
val io = IO(new Bundle {
val in = Input(Bool())
val out = Output(Bool())
})
val clock = IO(Input(Clock()))
val reset = IO(Input(AsyncReset()))
withClockAndReset(clock, reset){
io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc))
}
}
class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSource_${gen.typeName}"
val io = IO(new Bundle {
// These come from the source domain
val enq = Flipped(Decoupled(gen))
// These cross to the sink clock domain
val async = new AsyncBundle(gen, params)
})
val bits = params.bits
val sink_ready = WireInit(true.B)
val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all.
val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin"))
val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray"))
val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U)
val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1))
when (io.enq.fire) { mem(index) := io.enq.bits }
val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg"))
io.enq.ready := ready_reg && sink_ready
val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray"))
io.async.widx := widx_reg
io.async.index match {
case Some(index) => io.async.mem(0) := mem(index)
case None => io.async.mem := mem
}
io.async.safe.foreach { sio =>
val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0"))
val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1"))
val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend"))
val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid"))
source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_valid .reset := reset.asAsyncReset
source_valid_0.clock := clock
source_valid_1.clock := clock
sink_extend .clock := clock
sink_valid .clock := clock
source_valid_0.io.in := true.B
source_valid_1.io.in := source_valid_0.io.out
sio.widx_valid := source_valid_1.io.out
sink_extend.io.in := sio.ridx_valid
sink_valid.io.in := sink_extend.io.out
sink_ready := sink_valid.io.out
sio.source_reset_n := !reset.asBool
// Assert that if there is stuff in the queue, then reset cannot happen
// Impossible to write because dequeue can occur on the receiving side,
// then reset allowed to happen, but write side cannot know that dequeue
// occurred.
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
// assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected")
// assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty")
}
}
class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSink_${gen.typeName}"
val io = IO(new Bundle {
// These come from the sink domain
val deq = Decoupled(gen)
// These cross to the source clock domain
val async = Flipped(new AsyncBundle(gen, params))
})
val bits = params.bits
val source_ready = WireInit(true.B)
val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin"))
val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray"))
val valid = source_ready && ridx =/= widx
// The mux is safe because timing analysis ensures ridx has reached the register
// On an ASIC, changes to the unread location cannot affect the selected value
// On an FPGA, only one input changes at a time => mem updates don't cause glitches
// The register only latches when the selected valued is not being written
val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1))
io.async.index.foreach { _ := index }
// This register does not NEED to be reset, as its contents will not
// be considered unless the asynchronously reset deq valid register is set.
// It is possible that bits latches when the source domain is reset / has power cut
// This is safe, because isolation gates brought mem low before the zeroed widx reached us
val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index)
io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg"))
val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg"))
io.deq.valid := valid_reg && source_ready
val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray"))
io.async.ridx := ridx_reg
io.async.safe.foreach { sio =>
val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0"))
val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1"))
val source_extend = Module(new AsyncValidSync(params.sync, "source_extend"))
val source_valid = Module(new AsyncValidSync(params.sync, "source_valid"))
sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_valid .reset := reset.asAsyncReset
sink_valid_0 .clock := clock
sink_valid_1 .clock := clock
source_extend.clock := clock
source_valid .clock := clock
sink_valid_0.io.in := true.B
sink_valid_1.io.in := sink_valid_0.io.out
sio.ridx_valid := sink_valid_1.io.out
source_extend.io.in := sio.widx_valid
source_valid.io.in := source_extend.io.out
source_ready := source_valid.io.out
sio.sink_reset_n := !reset.asBool
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
//
// val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool
// val reset_and_extend_prev = RegNext(reset_and_extend, true.B)
// val reset_rise = !reset_and_extend_prev && reset_and_extend
// val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0)
// assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty")
}
}
object FromAsyncBundle
{
// Sometimes it makes sense for the sink to have different sync than the source
def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync)
def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = {
val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync)))
sink.io.async <> x
sink.io.deq
}
}
object ToAsyncBundle
{
def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = {
val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params))
source.io.enq <> x
source.io.async
}
}
class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] {
val io = IO(new CrossingIO(gen))
val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) }
val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) }
source.io.enq <> io.enq
io.deq <> sink.io.deq
sink.io.async <> source.io.async
}
| module AsyncValidSync_161( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_178 io_out_source_valid_1 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File DivSqrtRecFN_small.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2017 SiFive, Inc. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of SiFive nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY SIFIVE AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL SIFIVE OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
/*
s = sigWidth
c_i = newBit
Division:
width of a is (s+2)
Normal
------
(qi + ci * 2^(-i))*b <= a
q0 = 0
r0 = a
q(i+1) = qi + ci*2^(-i)
ri = a - qi*b
r(i+1) = a - q(i+1)*b
= a - qi*b - ci*2^(-i)*b
r(i+1) = ri - ci*2^(-i)*b
ci = ri >= 2^(-i)*b
summary_i = ri != 0
i = 0 to s+1
(s+1)th bit plus summary_(i+1) gives enough information for rounding
If (a < b), then we need to calculate (s+2)th bit and summary_(i+1)
because we need s bits ignoring the leading zero. (This is skipCycle2
part of Hauser's code.)
Hauser
------
sig_i = qi
rem_i = 2^(i-2)*ri
cycle_i = s+3-i
sig_0 = 0
rem_0 = a/4
cycle_0 = s+3
bit_0 = 2^0 (= 2^(s+1), since we represent a, b and q with (s+2) bits)
sig(i+1) = sig(i) + ci*bit_i
rem(i+1) = 2rem_i - ci*b/2
ci = 2rem_i >= b/2
bit_i = 2^-i (=2^(cycle_i-2), since we represent a, b and q with (s+2) bits)
cycle(i+1) = cycle_i-1
summary_1 = a <> b
summary(i+1) = if ci then 2rem_i-b/2 <> 0 else summary_i, i <> 0
Proof:
2^i*r(i+1) = 2^i*ri - ci*b. Qed
ci = 2^i*ri >= b. Qed
summary(i+1) = if ci then rem(i+1) else summary_i, i <> 0
Now, note that all of ck's cannot be 0, since that means
a is 0. So when you traverse through a chain of 0 ck's,
from the end,
eventually, you reach a non-zero cj. That is exactly the
value of ri as the reminder remains the same. When all ck's
are 0 except c0 (which must be 1) then summary_1 is set
correctly according
to r1 = a-b != 0. So summary(i+1) is always set correctly
according to r(i+1)
Square root:
width of a is (s+1)
Normal
------
(xi + ci*2^(-i))^2 <= a
xi^2 + ci*2^(-i)*(2xi+ci*2^(-i)) <= a
x0 = 0
x(i+1) = xi + ci*2^(-i)
ri = a - xi^2
r(i+1) = a - x(i+1)^2
= a - (xi^2 + ci*2^(-i)*(2xi+ci*2^(-i)))
= ri - ci*2^(-i)*(2xi+ci*2^(-i))
= ri - ci*2^(-i)*(2xi+2^(-i)) // ci is always 0 or 1
ci = ri >= 2^(-i)*(2xi + 2^(-i))
summary_i = ri != 0
i = 0 to s+1
For odd expression, do 2 steps initially.
(s+1)th bit plus summary_(i+1) gives enough information for rounding.
Hauser
------
sig_i = xi
rem_i = ri*2^(i-1)
cycle_i = s+2-i
bit_i = 2^(-i) (= 2^(s-i) = 2^(cycle_i-2) in terms of bit representation)
sig_0 = 0
rem_0 = a/2
cycle_0 = s+2
bit_0 = 1 (= 2^s in terms of bit representation)
sig(i+1) = sig_i + ci * bit_i
rem(i+1) = 2rem_i - ci*(2sig_i + bit_i)
ci = 2*sig_i + bit_i <= 2*rem_i
bit_i = 2^(cycle_i-2) (in terms of bit representation)
cycle(i+1) = cycle_i-1
summary_1 = a - (2^s) (in terms of bit representation)
summary(i+1) = if ci then rem(i+1) <> 0 else summary_i, i <> 0
Proof:
ci = 2*sig_i + bit_i <= 2*rem_i
ci = 2xi + 2^(-i) <= ri*2^i. Qed
sig(i+1) = sig_i + ci * bit_i
x(i+1) = xi + ci*2^(-i). Qed
rem(i+1) = 2rem_i - ci*(2sig_i + bit_i)
r(i+1)*2^i = ri*2^i - ci*(2xi + 2^(-i))
r(i+1) = ri - ci*2^(-i)*(2xi + 2^(-i)). Qed
Same argument as before for summary.
------------------------------
Note that all registers are updated normally until cycle == 2.
At cycle == 2, rem is not updated, but all other registers are updated normally.
But, cycle == 1 does not read rem to calculate anything (note that final summary
is calculated using the values at cycle = 2).
*/
package hardfloat
import chisel3._
import chisel3.util._
import consts._
/*----------------------------------------------------------------------------
| Computes a division or square root for floating-point in recoded form.
| Multiple clock cycles are needed for each division or square-root operation,
| except possibly in special cases.
*----------------------------------------------------------------------------*/
class
DivSqrtRawFN_small(expWidth: Int, sigWidth: Int, options: Int)
extends Module
{
override def desiredName = s"DivSqrtRawFN_small_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
val inReady = Output(Bool())
val inValid = Input(Bool())
val sqrtOp = Input(Bool())
val a = Input(new RawFloat(expWidth, sigWidth))
val b = Input(new RawFloat(expWidth, sigWidth))
val roundingMode = Input(UInt(3.W))
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
val rawOutValid_div = Output(Bool())
val rawOutValid_sqrt = Output(Bool())
val roundingModeOut = Output(UInt(3.W))
val invalidExc = Output(Bool())
val infiniteExc = Output(Bool())
val rawOut = Output(new RawFloat(expWidth, sigWidth + 2))
})
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
val cycleNum = RegInit(0.U(log2Ceil(sigWidth + 3).W))
val inReady = RegInit(true.B) // <-> (cycleNum <= 1)
val rawOutValid = RegInit(false.B) // <-> (cycleNum === 1)
val sqrtOp_Z = Reg(Bool())
val majorExc_Z = Reg(Bool())
//*** REDUCE 3 BITS TO 2-BIT CODE:
val isNaN_Z = Reg(Bool())
val isInf_Z = Reg(Bool())
val isZero_Z = Reg(Bool())
val sign_Z = Reg(Bool())
val sExp_Z = Reg(SInt((expWidth + 2).W))
val fractB_Z = Reg(UInt(sigWidth.W))
val roundingMode_Z = Reg(UInt(3.W))
/*------------------------------------------------------------------------
| (The most-significant and least-significant bits of 'rem_Z' are needed
| only for square roots.)
*------------------------------------------------------------------------*/
val rem_Z = Reg(UInt((sigWidth + 2).W))
val notZeroRem_Z = Reg(Bool())
val sigX_Z = Reg(UInt((sigWidth + 2).W))
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
val rawA_S = io.a
val rawB_S = io.b
//*** IMPROVE THESE:
val notSigNaNIn_invalidExc_S_div =
(rawA_S.isZero && rawB_S.isZero) || (rawA_S.isInf && rawB_S.isInf)
val notSigNaNIn_invalidExc_S_sqrt =
! rawA_S.isNaN && ! rawA_S.isZero && rawA_S.sign
val majorExc_S =
Mux(io.sqrtOp,
isSigNaNRawFloat(rawA_S) || notSigNaNIn_invalidExc_S_sqrt,
isSigNaNRawFloat(rawA_S) || isSigNaNRawFloat(rawB_S) ||
notSigNaNIn_invalidExc_S_div ||
(! rawA_S.isNaN && ! rawA_S.isInf && rawB_S.isZero)
)
val isNaN_S =
Mux(io.sqrtOp,
rawA_S.isNaN || notSigNaNIn_invalidExc_S_sqrt,
rawA_S.isNaN || rawB_S.isNaN || notSigNaNIn_invalidExc_S_div
)
val isInf_S = Mux(io.sqrtOp, rawA_S.isInf, rawA_S.isInf || rawB_S.isZero)
val isZero_S = Mux(io.sqrtOp, rawA_S.isZero, rawA_S.isZero || rawB_S.isInf)
val sign_S = rawA_S.sign ^ (! io.sqrtOp && rawB_S.sign)
val specialCaseA_S = rawA_S.isNaN || rawA_S.isInf || rawA_S.isZero
val specialCaseB_S = rawB_S.isNaN || rawB_S.isInf || rawB_S.isZero
val normalCase_S_div = ! specialCaseA_S && ! specialCaseB_S
val normalCase_S_sqrt = ! specialCaseA_S && ! rawA_S.sign
val normalCase_S = Mux(io.sqrtOp, normalCase_S_sqrt, normalCase_S_div)
val sExpQuot_S_div =
rawA_S.sExp +&
Cat(rawB_S.sExp(expWidth), ~rawB_S.sExp(expWidth - 1, 0)).asSInt
//*** IS THIS OPTIMAL?:
val sSatExpQuot_S_div =
Cat(Mux(((BigInt(7)<<(expWidth - 2)).S <= sExpQuot_S_div),
6.U,
sExpQuot_S_div(expWidth + 1, expWidth - 2)
),
sExpQuot_S_div(expWidth - 3, 0)
).asSInt
val evenSqrt_S = io.sqrtOp && ! rawA_S.sExp(0)
val oddSqrt_S = io.sqrtOp && rawA_S.sExp(0)
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
val idle = cycleNum === 0.U
val entering = inReady && io.inValid
val entering_normalCase = entering && normalCase_S
val processTwoBits = cycleNum >= 3.U && ((options & divSqrtOpt_twoBitsPerCycle) != 0).B
val skipCycle2 = cycleNum === 3.U && sigX_Z(sigWidth + 1) && ((options & divSqrtOpt_twoBitsPerCycle) == 0).B
when (! idle || entering) {
def computeCycleNum(f: UInt => UInt): UInt = {
Mux(entering & ! normalCase_S, f(1.U), 0.U) |
Mux(entering_normalCase,
Mux(io.sqrtOp,
Mux(rawA_S.sExp(0), f(sigWidth.U), f((sigWidth + 1).U)),
f((sigWidth + 2).U)
),
0.U
) |
Mux(! entering && ! skipCycle2, f(cycleNum - Mux(processTwoBits, 2.U, 1.U)), 0.U) |
Mux(skipCycle2, f(1.U), 0.U)
}
inReady := computeCycleNum(_ <= 1.U).asBool
rawOutValid := computeCycleNum(_ === 1.U).asBool
cycleNum := computeCycleNum(x => x)
}
io.inReady := inReady
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
when (entering) {
sqrtOp_Z := io.sqrtOp
majorExc_Z := majorExc_S
isNaN_Z := isNaN_S
isInf_Z := isInf_S
isZero_Z := isZero_S
sign_Z := sign_S
sExp_Z :=
Mux(io.sqrtOp,
(rawA_S.sExp>>1) +& (BigInt(1)<<(expWidth - 1)).S,
sSatExpQuot_S_div
)
roundingMode_Z := io.roundingMode
}
when (entering || ! inReady && sqrtOp_Z) {
fractB_Z :=
Mux(inReady && ! io.sqrtOp, rawB_S.sig(sigWidth - 2, 0)<<1, 0.U) |
Mux(inReady && io.sqrtOp && rawA_S.sExp(0), (BigInt(1)<<(sigWidth - 2)).U, 0.U) |
Mux(inReady && io.sqrtOp && ! rawA_S.sExp(0), (BigInt(1)<<(sigWidth - 1)).U, 0.U) |
Mux(! inReady /* sqrtOp_Z */ && processTwoBits, fractB_Z>>2, 0.U) |
Mux(! inReady /* sqrtOp_Z */ && ! processTwoBits, fractB_Z>>1, 0.U)
}
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
val rem =
Mux(inReady && ! oddSqrt_S, rawA_S.sig<<1, 0.U) |
Mux(inReady && oddSqrt_S,
Cat(rawA_S.sig(sigWidth - 1, sigWidth - 2) - 1.U,
rawA_S.sig(sigWidth - 3, 0)<<3
),
0.U
) |
Mux(! inReady, rem_Z<<1, 0.U)
val bitMask = (1.U<<cycleNum)>>2
val trialTerm =
Mux(inReady && ! io.sqrtOp, rawB_S.sig<<1, 0.U) |
Mux(inReady && evenSqrt_S, (BigInt(1)<<sigWidth).U, 0.U) |
Mux(inReady && oddSqrt_S, (BigInt(5)<<(sigWidth - 1)).U, 0.U) |
Mux(! inReady, fractB_Z, 0.U) |
Mux(! inReady && ! sqrtOp_Z, 1.U << sigWidth, 0.U) |
Mux(! inReady && sqrtOp_Z, sigX_Z<<1, 0.U)
val trialRem = rem.zext -& trialTerm.zext
val newBit = (0.S <= trialRem)
val nextRem_Z = Mux(newBit, trialRem.asUInt, rem)(sigWidth + 1, 0)
val rem2 = nextRem_Z<<1
val trialTerm2_newBit0 = Mux(sqrtOp_Z, fractB_Z>>1 | sigX_Z<<1, fractB_Z | (1.U << sigWidth))
val trialTerm2_newBit1 = trialTerm2_newBit0 | Mux(sqrtOp_Z, fractB_Z<<1, 0.U)
val trialRem2 =
Mux(newBit,
(trialRem<<1) - trialTerm2_newBit1.zext,
(rem_Z<<2)(sigWidth+2, 0).zext - trialTerm2_newBit0.zext)
val newBit2 = (0.S <= trialRem2)
val nextNotZeroRem_Z = Mux(inReady || newBit, trialRem =/= 0.S, notZeroRem_Z)
val nextNotZeroRem_Z_2 = // <-> Mux(newBit2, trialRem2 =/= 0.S, nextNotZeroRem_Z)
processTwoBits && newBit && (0.S < (trialRem<<1) - trialTerm2_newBit1.zext) ||
processTwoBits && !newBit && (0.S < (rem_Z<<2)(sigWidth+2, 0).zext - trialTerm2_newBit0.zext) ||
!(processTwoBits && newBit2) && nextNotZeroRem_Z
val nextRem_Z_2 =
Mux(processTwoBits && newBit2, trialRem2.asUInt(sigWidth + 1, 0), 0.U) |
Mux(processTwoBits && !newBit2, rem2(sigWidth + 1, 0), 0.U) |
Mux(!processTwoBits, nextRem_Z, 0.U)
when (entering || ! inReady) {
notZeroRem_Z := nextNotZeroRem_Z_2
rem_Z := nextRem_Z_2
sigX_Z :=
Mux(inReady && ! io.sqrtOp, newBit<<(sigWidth + 1), 0.U) |
Mux(inReady && io.sqrtOp, (BigInt(1)<<sigWidth).U, 0.U) |
Mux(inReady && oddSqrt_S, newBit<<(sigWidth - 1), 0.U) |
Mux(! inReady, sigX_Z, 0.U) |
Mux(! inReady && newBit, bitMask, 0.U) |
Mux(processTwoBits && newBit2, bitMask>>1, 0.U)
}
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
io.rawOutValid_div := rawOutValid && ! sqrtOp_Z
io.rawOutValid_sqrt := rawOutValid && sqrtOp_Z
io.roundingModeOut := roundingMode_Z
io.invalidExc := majorExc_Z && isNaN_Z
io.infiniteExc := majorExc_Z && ! isNaN_Z
io.rawOut.isNaN := isNaN_Z
io.rawOut.isInf := isInf_Z
io.rawOut.isZero := isZero_Z
io.rawOut.sign := sign_Z
io.rawOut.sExp := sExp_Z
io.rawOut.sig := sigX_Z<<1 | notZeroRem_Z
}
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
class
DivSqrtRecFNToRaw_small(expWidth: Int, sigWidth: Int, options: Int)
extends Module
{
override def desiredName = s"DivSqrtRecFMToRaw_small_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
val inReady = Output(Bool())
val inValid = Input(Bool())
val sqrtOp = Input(Bool())
val a = Input(UInt((expWidth + sigWidth + 1).W))
val b = Input(UInt((expWidth + sigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
val rawOutValid_div = Output(Bool())
val rawOutValid_sqrt = Output(Bool())
val roundingModeOut = Output(UInt(3.W))
val invalidExc = Output(Bool())
val infiniteExc = Output(Bool())
val rawOut = Output(new RawFloat(expWidth, sigWidth + 2))
})
val divSqrtRawFN =
Module(new DivSqrtRawFN_small(expWidth, sigWidth, options))
io.inReady := divSqrtRawFN.io.inReady
divSqrtRawFN.io.inValid := io.inValid
divSqrtRawFN.io.sqrtOp := io.sqrtOp
divSqrtRawFN.io.a := rawFloatFromRecFN(expWidth, sigWidth, io.a)
divSqrtRawFN.io.b := rawFloatFromRecFN(expWidth, sigWidth, io.b)
divSqrtRawFN.io.roundingMode := io.roundingMode
io.rawOutValid_div := divSqrtRawFN.io.rawOutValid_div
io.rawOutValid_sqrt := divSqrtRawFN.io.rawOutValid_sqrt
io.roundingModeOut := divSqrtRawFN.io.roundingModeOut
io.invalidExc := divSqrtRawFN.io.invalidExc
io.infiniteExc := divSqrtRawFN.io.infiniteExc
io.rawOut := divSqrtRawFN.io.rawOut
}
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
class
DivSqrtRecFN_small(expWidth: Int, sigWidth: Int, options: Int)
extends Module
{
override def desiredName = s"DivSqrtRecFM_small_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
val inReady = Output(Bool())
val inValid = Input(Bool())
val sqrtOp = Input(Bool())
val a = Input(UInt((expWidth + sigWidth + 1).W))
val b = Input(UInt((expWidth + sigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
val outValid_div = Output(Bool())
val outValid_sqrt = Output(Bool())
val out = Output(UInt((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(UInt(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val divSqrtRecFNToRaw =
Module(new DivSqrtRecFNToRaw_small(expWidth, sigWidth, options))
io.inReady := divSqrtRecFNToRaw.io.inReady
divSqrtRecFNToRaw.io.inValid := io.inValid
divSqrtRecFNToRaw.io.sqrtOp := io.sqrtOp
divSqrtRecFNToRaw.io.a := io.a
divSqrtRecFNToRaw.io.b := io.b
divSqrtRecFNToRaw.io.roundingMode := io.roundingMode
//------------------------------------------------------------------------
//------------------------------------------------------------------------
io.outValid_div := divSqrtRecFNToRaw.io.rawOutValid_div
io.outValid_sqrt := divSqrtRecFNToRaw.io.rawOutValid_sqrt
val roundRawFNToRecFN =
Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0))
roundRawFNToRecFN.io.invalidExc := divSqrtRecFNToRaw.io.invalidExc
roundRawFNToRecFN.io.infiniteExc := divSqrtRecFNToRaw.io.infiniteExc
roundRawFNToRecFN.io.in := divSqrtRecFNToRaw.io.rawOut
roundRawFNToRecFN.io.roundingMode := divSqrtRecFNToRaw.io.roundingModeOut
roundRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundRawFNToRecFN.io.out
io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags
}
| module DivSqrtRecFM_small_e5_s11_2( // @[DivSqrtRecFN_small.scala:468:5]
input clock, // @[DivSqrtRecFN_small.scala:468:5]
input reset, // @[DivSqrtRecFN_small.scala:468:5]
output io_inReady, // @[DivSqrtRecFN_small.scala:472:16]
input io_inValid, // @[DivSqrtRecFN_small.scala:472:16]
input io_sqrtOp, // @[DivSqrtRecFN_small.scala:472:16]
input [16:0] io_a, // @[DivSqrtRecFN_small.scala:472:16]
input [16:0] io_b, // @[DivSqrtRecFN_small.scala:472:16]
input [2:0] io_roundingMode, // @[DivSqrtRecFN_small.scala:472:16]
output io_outValid_div, // @[DivSqrtRecFN_small.scala:472:16]
output io_outValid_sqrt, // @[DivSqrtRecFN_small.scala:472:16]
output [16:0] io_out, // @[DivSqrtRecFN_small.scala:472:16]
output [4:0] io_exceptionFlags // @[DivSqrtRecFN_small.scala:472:16]
);
wire [2:0] _divSqrtRecFNToRaw_io_roundingModeOut; // @[DivSqrtRecFN_small.scala:493:15]
wire _divSqrtRecFNToRaw_io_invalidExc; // @[DivSqrtRecFN_small.scala:493:15]
wire _divSqrtRecFNToRaw_io_infiniteExc; // @[DivSqrtRecFN_small.scala:493:15]
wire _divSqrtRecFNToRaw_io_rawOut_isNaN; // @[DivSqrtRecFN_small.scala:493:15]
wire _divSqrtRecFNToRaw_io_rawOut_isInf; // @[DivSqrtRecFN_small.scala:493:15]
wire _divSqrtRecFNToRaw_io_rawOut_isZero; // @[DivSqrtRecFN_small.scala:493:15]
wire _divSqrtRecFNToRaw_io_rawOut_sign; // @[DivSqrtRecFN_small.scala:493:15]
wire [6:0] _divSqrtRecFNToRaw_io_rawOut_sExp; // @[DivSqrtRecFN_small.scala:493:15]
wire [13:0] _divSqrtRecFNToRaw_io_rawOut_sig; // @[DivSqrtRecFN_small.scala:493:15]
wire io_inValid_0 = io_inValid; // @[DivSqrtRecFN_small.scala:468:5]
wire io_sqrtOp_0 = io_sqrtOp; // @[DivSqrtRecFN_small.scala:468:5]
wire [16:0] io_a_0 = io_a; // @[DivSqrtRecFN_small.scala:468:5]
wire [16:0] io_b_0 = io_b; // @[DivSqrtRecFN_small.scala:468:5]
wire [2:0] io_roundingMode_0 = io_roundingMode; // @[DivSqrtRecFN_small.scala:468:5]
wire io_detectTininess = 1'h1; // @[DivSqrtRecFN_small.scala:468:5, :472:16, :508:15]
wire io_inReady_0; // @[DivSqrtRecFN_small.scala:468:5]
wire io_outValid_div_0; // @[DivSqrtRecFN_small.scala:468:5]
wire io_outValid_sqrt_0; // @[DivSqrtRecFN_small.scala:468:5]
wire [16:0] io_out_0; // @[DivSqrtRecFN_small.scala:468:5]
wire [4:0] io_exceptionFlags_0; // @[DivSqrtRecFN_small.scala:468:5]
DivSqrtRecFMToRaw_small_e5_s11_2 divSqrtRecFNToRaw ( // @[DivSqrtRecFN_small.scala:493:15]
.clock (clock),
.reset (reset),
.io_inReady (io_inReady_0),
.io_inValid (io_inValid_0), // @[DivSqrtRecFN_small.scala:468:5]
.io_sqrtOp (io_sqrtOp_0), // @[DivSqrtRecFN_small.scala:468:5]
.io_a (io_a_0), // @[DivSqrtRecFN_small.scala:468:5]
.io_b (io_b_0), // @[DivSqrtRecFN_small.scala:468:5]
.io_roundingMode (io_roundingMode_0), // @[DivSqrtRecFN_small.scala:468:5]
.io_rawOutValid_div (io_outValid_div_0),
.io_rawOutValid_sqrt (io_outValid_sqrt_0),
.io_roundingModeOut (_divSqrtRecFNToRaw_io_roundingModeOut),
.io_invalidExc (_divSqrtRecFNToRaw_io_invalidExc),
.io_infiniteExc (_divSqrtRecFNToRaw_io_infiniteExc),
.io_rawOut_isNaN (_divSqrtRecFNToRaw_io_rawOut_isNaN),
.io_rawOut_isInf (_divSqrtRecFNToRaw_io_rawOut_isInf),
.io_rawOut_isZero (_divSqrtRecFNToRaw_io_rawOut_isZero),
.io_rawOut_sign (_divSqrtRecFNToRaw_io_rawOut_sign),
.io_rawOut_sExp (_divSqrtRecFNToRaw_io_rawOut_sExp),
.io_rawOut_sig (_divSqrtRecFNToRaw_io_rawOut_sig)
); // @[DivSqrtRecFN_small.scala:493:15]
RoundRawFNToRecFN_e5_s11_5 roundRawFNToRecFN ( // @[DivSqrtRecFN_small.scala:508:15]
.io_invalidExc (_divSqrtRecFNToRaw_io_invalidExc), // @[DivSqrtRecFN_small.scala:493:15]
.io_infiniteExc (_divSqrtRecFNToRaw_io_infiniteExc), // @[DivSqrtRecFN_small.scala:493:15]
.io_in_isNaN (_divSqrtRecFNToRaw_io_rawOut_isNaN), // @[DivSqrtRecFN_small.scala:493:15]
.io_in_isInf (_divSqrtRecFNToRaw_io_rawOut_isInf), // @[DivSqrtRecFN_small.scala:493:15]
.io_in_isZero (_divSqrtRecFNToRaw_io_rawOut_isZero), // @[DivSqrtRecFN_small.scala:493:15]
.io_in_sign (_divSqrtRecFNToRaw_io_rawOut_sign), // @[DivSqrtRecFN_small.scala:493:15]
.io_in_sExp (_divSqrtRecFNToRaw_io_rawOut_sExp), // @[DivSqrtRecFN_small.scala:493:15]
.io_in_sig (_divSqrtRecFNToRaw_io_rawOut_sig), // @[DivSqrtRecFN_small.scala:493:15]
.io_roundingMode (_divSqrtRecFNToRaw_io_roundingModeOut), // @[DivSqrtRecFN_small.scala:493:15]
.io_out (io_out_0),
.io_exceptionFlags (io_exceptionFlags_0)
); // @[DivSqrtRecFN_small.scala:508:15]
assign io_inReady = io_inReady_0; // @[DivSqrtRecFN_small.scala:468:5]
assign io_outValid_div = io_outValid_div_0; // @[DivSqrtRecFN_small.scala:468:5]
assign io_outValid_sqrt = io_outValid_sqrt_0; // @[DivSqrtRecFN_small.scala:468:5]
assign io_out = io_out_0; // @[DivSqrtRecFN_small.scala:468:5]
assign io_exceptionFlags = io_exceptionFlags_0; // @[DivSqrtRecFN_small.scala:468:5]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Multiplier.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util.{Cat, log2Up, log2Ceil, log2Floor, Log2, Decoupled, Enum, Fill, Valid, Pipe}
import freechips.rocketchip.util._
import ALU._
class MultiplierReq(dataBits: Int, tagBits: Int) extends Bundle {
val fn = Bits(SZ_ALU_FN.W)
val dw = Bits(SZ_DW.W)
val in1 = Bits(dataBits.W)
val in2 = Bits(dataBits.W)
val tag = UInt(tagBits.W)
}
class MultiplierResp(dataBits: Int, tagBits: Int) extends Bundle {
val data = Bits(dataBits.W)
val full_data = Bits((2*dataBits).W)
val tag = UInt(tagBits.W)
}
class MultiplierIO(val dataBits: Int, val tagBits: Int) extends Bundle {
val req = Flipped(Decoupled(new MultiplierReq(dataBits, tagBits)))
val kill = Input(Bool())
val resp = Decoupled(new MultiplierResp(dataBits, tagBits))
}
case class MulDivParams(
mulUnroll: Int = 1,
divUnroll: Int = 1,
mulEarlyOut: Boolean = false,
divEarlyOut: Boolean = false,
divEarlyOutGranularity: Int = 1
)
class MulDiv(cfg: MulDivParams, width: Int, nXpr: Int = 32) extends Module {
private def minDivLatency = (cfg.divUnroll > 0).option(if (cfg.divEarlyOut) 3 else 1 + w/cfg.divUnroll)
private def minMulLatency = (cfg.mulUnroll > 0).option(if (cfg.mulEarlyOut) 2 else w/cfg.mulUnroll)
def minLatency: Int = (minDivLatency ++ minMulLatency).min
val io = IO(new MultiplierIO(width, log2Up(nXpr)))
val w = io.req.bits.in1.getWidth
val mulw = if (cfg.mulUnroll == 0) w else (w + cfg.mulUnroll - 1) / cfg.mulUnroll * cfg.mulUnroll
val fastMulW = if (cfg.mulUnroll == 0) false else w/2 > cfg.mulUnroll && w % (2*cfg.mulUnroll) == 0
val s_ready :: s_neg_inputs :: s_mul :: s_div :: s_dummy :: s_neg_output :: s_done_mul :: s_done_div :: Nil = Enum(8)
val state = RegInit(s_ready)
val req = Reg(chiselTypeOf(io.req.bits))
val count = Reg(UInt(log2Ceil(
((cfg.divUnroll != 0).option(w/cfg.divUnroll + 1).toSeq ++
(cfg.mulUnroll != 0).option(mulw/cfg.mulUnroll)).reduce(_ max _)).W))
val neg_out = Reg(Bool())
val isHi = Reg(Bool())
val resHi = Reg(Bool())
val divisor = Reg(Bits((w+1).W)) // div only needs w bits
val remainder = Reg(Bits((2*mulw+2).W)) // div only needs 2*w+1 bits
val mulDecode = List(
FN_MUL -> List(Y, N, X, X),
FN_MULH -> List(Y, Y, Y, Y),
FN_MULHU -> List(Y, Y, N, N),
FN_MULHSU -> List(Y, Y, Y, N))
val divDecode = List(
FN_DIV -> List(N, N, Y, Y),
FN_REM -> List(N, Y, Y, Y),
FN_DIVU -> List(N, N, N, N),
FN_REMU -> List(N, Y, N, N))
val cmdMul :: cmdHi :: lhsSigned :: rhsSigned :: Nil =
DecodeLogic(io.req.bits.fn, List(X, X, X, X),
(if (cfg.divUnroll != 0) divDecode else Nil) ++ (if (cfg.mulUnroll != 0) mulDecode else Nil)).map(_.asBool)
require(w == 32 || w == 64)
def halfWidth(req: MultiplierReq) = (w > 32).B && req.dw === DW_32
def sext(x: Bits, halfW: Bool, signed: Bool) = {
val sign = signed && Mux(halfW, x(w/2-1), x(w-1))
val hi = Mux(halfW, Fill(w/2, sign), x(w-1,w/2))
(Cat(hi, x(w/2-1,0)), sign)
}
val (lhs_in, lhs_sign) = sext(io.req.bits.in1, halfWidth(io.req.bits), lhsSigned)
val (rhs_in, rhs_sign) = sext(io.req.bits.in2, halfWidth(io.req.bits), rhsSigned)
val subtractor = remainder(2*w,w) - divisor
val result = Mux(resHi, remainder(2*w, w+1), remainder(w-1, 0))
val negated_remainder = -result
if (cfg.divUnroll != 0) when (state === s_neg_inputs) {
when (remainder(w-1)) {
remainder := negated_remainder
}
when (divisor(w-1)) {
divisor := subtractor
}
state := s_div
}
if (cfg.divUnroll != 0) when (state === s_neg_output) {
remainder := negated_remainder
state := s_done_div
resHi := false.B
}
if (cfg.mulUnroll != 0) when (state === s_mul) {
val mulReg = Cat(remainder(2*mulw+1,w+1),remainder(w-1,0))
val mplierSign = remainder(w)
val mplier = mulReg(mulw-1,0)
val accum = mulReg(2*mulw,mulw).asSInt
val mpcand = divisor.asSInt
val prod = Cat(mplierSign, mplier(cfg.mulUnroll-1, 0)).asSInt * mpcand + accum
val nextMulReg = Cat(prod, mplier(mulw-1, cfg.mulUnroll))
val nextMplierSign = count === (mulw/cfg.mulUnroll-2).U && neg_out
val eOutMask = ((BigInt(-1) << mulw).S >> (count * cfg.mulUnroll.U)(log2Up(mulw)-1,0))(mulw-1,0)
val eOut = (cfg.mulEarlyOut).B && count =/= (mulw/cfg.mulUnroll-1).U && count =/= 0.U &&
!isHi && (mplier & ~eOutMask) === 0.U
val eOutRes = (mulReg >> (mulw.U - count * cfg.mulUnroll.U)(log2Up(mulw)-1,0))
val nextMulReg1 = Cat(nextMulReg(2*mulw,mulw), Mux(eOut, eOutRes, nextMulReg)(mulw-1,0))
remainder := Cat(nextMulReg1 >> w, nextMplierSign, nextMulReg1(w-1,0))
count := count + 1.U
when (eOut || count === (mulw/cfg.mulUnroll-1).U) {
state := s_done_mul
resHi := isHi
}
}
if (cfg.divUnroll != 0) when (state === s_div) {
val unrolls = ((0 until cfg.divUnroll) scanLeft remainder) { case (rem, i) =>
// the special case for iteration 0 is to save HW, not for correctness
val difference = if (i == 0) subtractor else rem(2*w,w) - divisor(w-1,0)
val less = difference(w)
Cat(Mux(less, rem(2*w-1,w), difference(w-1,0)), rem(w-1,0), !less)
}.tail
remainder := unrolls.last
when (count === (w/cfg.divUnroll).U) {
state := Mux(neg_out, s_neg_output, s_done_div)
resHi := isHi
if (w % cfg.divUnroll < cfg.divUnroll - 1)
remainder := unrolls(w % cfg.divUnroll)
}
count := count + 1.U
val divby0 = count === 0.U && !subtractor(w)
if (cfg.divEarlyOut) {
val align = 1 << log2Floor(cfg.divUnroll max cfg.divEarlyOutGranularity)
val alignMask = ~((align-1).U(log2Ceil(w).W))
val divisorMSB = Log2(divisor(w-1,0), w) & alignMask
val dividendMSB = Log2(remainder(w-1,0), w) | ~alignMask
val eOutPos = ~(dividendMSB - divisorMSB)
val eOut = count === 0.U && !divby0 && eOutPos >= align.U
when (eOut) {
remainder := remainder(w-1,0) << eOutPos
count := eOutPos >> log2Floor(cfg.divUnroll)
}
}
when (divby0 && !isHi) { neg_out := false.B }
}
when (io.resp.fire || io.kill) {
state := s_ready
}
when (io.req.fire) {
state := Mux(cmdMul, s_mul, Mux(lhs_sign || rhs_sign, s_neg_inputs, s_div))
isHi := cmdHi
resHi := false.B
count := (if (fastMulW) Mux[UInt](cmdMul && halfWidth(io.req.bits), (w/cfg.mulUnroll/2).U, 0.U) else 0.U)
neg_out := Mux(cmdHi, lhs_sign, lhs_sign =/= rhs_sign)
divisor := Cat(rhs_sign, rhs_in)
remainder := lhs_in
req := io.req.bits
}
val outMul = (state & (s_done_mul ^ s_done_div)) === (s_done_mul & ~s_done_div)
val loOut = Mux(fastMulW.B && halfWidth(req) && outMul, result(w-1,w/2), result(w/2-1,0))
val hiOut = Mux(halfWidth(req), Fill(w/2, loOut(w/2-1)), result(w-1,w/2))
io.resp.bits.tag := req.tag
io.resp.bits.data := Cat(hiOut, loOut)
io.resp.bits.full_data := Cat(remainder(2*w, w+1), remainder(w-1, 0))
io.resp.valid := (state === s_done_mul || state === s_done_div)
io.req.ready := state === s_ready
}
class PipelinedMultiplier(width: Int, latency: Int, nXpr: Int = 32) extends Module with ShouldBeRetimed {
val io = IO(new Bundle {
val req = Flipped(Valid(new MultiplierReq(width, log2Ceil(nXpr))))
val resp = Valid(new MultiplierResp(width, log2Ceil(nXpr)))
})
val in = Pipe(io.req)
val decode = List(
FN_MUL -> List(N, X, X),
FN_MULH -> List(Y, Y, Y),
FN_MULHU -> List(Y, N, N),
FN_MULHSU -> List(Y, Y, N))
val cmdHi :: lhsSigned :: rhsSigned :: Nil =
DecodeLogic(in.bits.fn, List(X, X, X), decode).map(_.asBool)
val cmdHalf = (width > 32).B && in.bits.dw === DW_32
val lhs = Cat(lhsSigned && in.bits.in1(width-1), in.bits.in1).asSInt
val rhs = Cat(rhsSigned && in.bits.in2(width-1), in.bits.in2).asSInt
val prod = lhs * rhs
val muxed = Mux(cmdHi, prod(2*width-1, width), Mux(cmdHalf, prod(width/2-1, 0).sextTo(width), prod(width-1, 0)))
val resp = Pipe(in, latency-1)
io.resp.valid := resp.valid
io.resp.bits.tag := resp.bits.tag
io.resp.bits.data := Pipe(in.valid, muxed, latency-1).bits
io.resp.bits.full_data := Pipe(in.valid, prod, latency-1).bits.asUInt
}
| module MulDiv( // @[Multiplier.scala:40:7]
input clock, // @[Multiplier.scala:40:7]
input reset, // @[Multiplier.scala:40:7]
output io_req_ready, // @[Multiplier.scala:45:14]
input io_req_valid, // @[Multiplier.scala:45:14]
input [4:0] io_req_bits_fn, // @[Multiplier.scala:45:14]
input io_req_bits_dw, // @[Multiplier.scala:45:14]
input [63:0] io_req_bits_in1, // @[Multiplier.scala:45:14]
input [63:0] io_req_bits_in2, // @[Multiplier.scala:45:14]
input io_kill, // @[Multiplier.scala:45:14]
input io_resp_ready, // @[Multiplier.scala:45:14]
output io_resp_valid, // @[Multiplier.scala:45:14]
output [63:0] io_resp_bits_data // @[Multiplier.scala:45:14]
);
wire io_req_valid_0 = io_req_valid; // @[Multiplier.scala:40:7]
wire [4:0] io_req_bits_fn_0 = io_req_bits_fn; // @[Multiplier.scala:40:7]
wire io_req_bits_dw_0 = io_req_bits_dw; // @[Multiplier.scala:40:7]
wire [63:0] io_req_bits_in1_0 = io_req_bits_in1; // @[Multiplier.scala:40:7]
wire [63:0] io_req_bits_in2_0 = io_req_bits_in2; // @[Multiplier.scala:40:7]
wire io_kill_0 = io_kill; // @[Multiplier.scala:40:7]
wire io_resp_ready_0 = io_resp_ready; // @[Multiplier.scala:40:7]
wire _eOut_T_1 = 1'h0; // @[Multiplier.scala:117:36]
wire _eOut_T_3 = 1'h0; // @[Multiplier.scala:117:74]
wire _eOut_T_5 = 1'h0; // @[Multiplier.scala:117:91]
wire eOut = 1'h0; // @[Multiplier.scala:118:13]
wire [5:0] alignMask = 6'h3F; // @[Multiplier.scala:149:23]
wire [5:0] _dividendMSB_T_111 = 6'h0; // @[Multiplier.scala:151:53]
wire [2:0] _outMul_T = 3'h1; // @[Multiplier.scala:175:37]
wire [2:0] _outMul_T_2 = 3'h0; // @[Multiplier.scala:175:70]
wire [2:0] _outMul_T_3 = 3'h0; // @[Multiplier.scala:175:68]
wire [4:0] io_req_bits_tag = 5'h0; // @[Multiplier.scala:40:7]
wire [4:0] io_resp_bits_tag = 5'h0; // @[Multiplier.scala:40:7]
wire _io_req_ready_T; // @[Multiplier.scala:183:25]
wire _io_resp_valid_T_2; // @[Multiplier.scala:182:42]
wire [63:0] _io_resp_bits_data_T; // @[Multiplier.scala:180:27]
wire [127:0] _io_resp_bits_full_data_T_2; // @[Multiplier.scala:181:32]
wire io_req_ready_0; // @[Multiplier.scala:40:7]
wire [63:0] io_resp_bits_data_0; // @[Multiplier.scala:40:7]
wire [127:0] io_resp_bits_full_data; // @[Multiplier.scala:40:7]
wire io_resp_valid_0; // @[Multiplier.scala:40:7]
reg [2:0] state; // @[Multiplier.scala:51:22]
reg [4:0] req_fn; // @[Multiplier.scala:53:16]
reg req_dw; // @[Multiplier.scala:53:16]
reg [63:0] req_in1; // @[Multiplier.scala:53:16]
reg [63:0] req_in2; // @[Multiplier.scala:53:16]
reg [6:0] count; // @[Multiplier.scala:54:18]
reg neg_out; // @[Multiplier.scala:57:20]
reg isHi; // @[Multiplier.scala:58:17]
reg resHi; // @[Multiplier.scala:59:18]
reg [64:0] divisor; // @[Multiplier.scala:60:20]
wire [64:0] mpcand = divisor; // @[Multiplier.scala:60:20, :111:26]
reg [129:0] remainder; // @[Multiplier.scala:61:22]
wire [2:0] decoded_plaInput; // @[pla.scala:77:22]
wire [2:0] decoded_invInputs = ~decoded_plaInput; // @[pla.scala:77:22, :78:21]
wire [3:0] decoded_invMatrixOutputs; // @[pla.scala:120:37]
wire [3:0] decoded; // @[pla.scala:81:23]
wire decoded_andMatrixOutputs_andMatrixInput_0 = decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_0_5 = decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_3_2 = decoded_andMatrixOutputs_andMatrixInput_0; // @[pla.scala:91:29, :98:70]
wire decoded_andMatrixOutputs_andMatrixInput_0_1 = decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_1 = decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_1_1 = decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_4_2 = decoded_andMatrixOutputs_andMatrixInput_0_1; // @[pla.scala:91:29, :98:70]
wire _decoded_orMatrixOutputs_T_6 = decoded_andMatrixOutputs_4_2; // @[pla.scala:98:70, :114:36]
wire decoded_andMatrixOutputs_andMatrixInput_0_2 = decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire [1:0] _decoded_andMatrixOutputs_T = {decoded_andMatrixOutputs_andMatrixInput_0_2, decoded_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:91:29, :98:53]
wire decoded_andMatrixOutputs_2_2 = &_decoded_andMatrixOutputs_T; // @[pla.scala:98:{53,70}]
wire decoded_andMatrixOutputs_andMatrixInput_0_3 = decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire [1:0] _decoded_andMatrixOutputs_T_1 = {decoded_andMatrixOutputs_andMatrixInput_0_3, decoded_andMatrixOutputs_andMatrixInput_1_1}; // @[pla.scala:90:45, :91:29, :98:53]
wire decoded_andMatrixOutputs_0_2 = &_decoded_andMatrixOutputs_T_1; // @[pla.scala:98:{53,70}]
wire decoded_andMatrixOutputs_andMatrixInput_0_4 = decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_andMatrixOutputs_1_2 = decoded_andMatrixOutputs_andMatrixInput_0_4; // @[pla.scala:90:45, :98:70]
wire decoded_andMatrixOutputs_andMatrixInput_1_2 = decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire [1:0] _decoded_andMatrixOutputs_T_2 = {decoded_andMatrixOutputs_andMatrixInput_0_5, decoded_andMatrixOutputs_andMatrixInput_1_2}; // @[pla.scala:90:45, :91:29, :98:53]
wire decoded_andMatrixOutputs_5_2 = &_decoded_andMatrixOutputs_T_2; // @[pla.scala:98:{53,70}]
wire [1:0] _decoded_orMatrixOutputs_T = {decoded_andMatrixOutputs_2_2, decoded_andMatrixOutputs_5_2}; // @[pla.scala:98:70, :114:19]
wire _decoded_orMatrixOutputs_T_1 = |_decoded_orMatrixOutputs_T; // @[pla.scala:114:{19,36}]
wire [1:0] _decoded_orMatrixOutputs_T_2 = {decoded_andMatrixOutputs_3_2, decoded_andMatrixOutputs_2_2}; // @[pla.scala:98:70, :114:19]
wire _decoded_orMatrixOutputs_T_3 = |_decoded_orMatrixOutputs_T_2; // @[pla.scala:114:{19,36}]
wire [1:0] _decoded_orMatrixOutputs_T_4 = {decoded_andMatrixOutputs_0_2, decoded_andMatrixOutputs_1_2}; // @[pla.scala:98:70, :114:19]
wire _decoded_orMatrixOutputs_T_5 = |_decoded_orMatrixOutputs_T_4; // @[pla.scala:114:{19,36}]
wire [1:0] decoded_orMatrixOutputs_lo = {_decoded_orMatrixOutputs_T_3, _decoded_orMatrixOutputs_T_1}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_orMatrixOutputs_hi = {_decoded_orMatrixOutputs_T_6, _decoded_orMatrixOutputs_T_5}; // @[pla.scala:102:36, :114:36]
wire [3:0] decoded_orMatrixOutputs = {decoded_orMatrixOutputs_hi, decoded_orMatrixOutputs_lo}; // @[pla.scala:102:36]
wire _decoded_invMatrixOutputs_T = decoded_orMatrixOutputs[0]; // @[pla.scala:102:36, :124:31]
wire _decoded_invMatrixOutputs_T_1 = decoded_orMatrixOutputs[1]; // @[pla.scala:102:36, :124:31]
wire _decoded_invMatrixOutputs_T_2 = decoded_orMatrixOutputs[2]; // @[pla.scala:102:36, :124:31]
wire _decoded_invMatrixOutputs_T_3 = decoded_orMatrixOutputs[3]; // @[pla.scala:102:36, :124:31]
wire [1:0] decoded_invMatrixOutputs_lo = {_decoded_invMatrixOutputs_T_1, _decoded_invMatrixOutputs_T}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_invMatrixOutputs_hi = {_decoded_invMatrixOutputs_T_3, _decoded_invMatrixOutputs_T_2}; // @[pla.scala:120:37, :124:31]
assign decoded_invMatrixOutputs = {decoded_invMatrixOutputs_hi, decoded_invMatrixOutputs_lo}; // @[pla.scala:120:37]
assign decoded = decoded_invMatrixOutputs; // @[pla.scala:81:23, :120:37]
assign decoded_plaInput = io_req_bits_fn_0[2:0]; // @[pla.scala:77:22]
wire cmdMul = decoded[3]; // @[pla.scala:81:23]
wire cmdHi = decoded[2]; // @[pla.scala:81:23]
wire lhsSigned = decoded[1]; // @[pla.scala:81:23]
wire rhsSigned = decoded[0]; // @[pla.scala:81:23]
wire _count_T_5 = ~io_req_bits_dw_0; // @[Multiplier.scala:40:7, :78:60]
wire _sign_T = io_req_bits_in1_0[31]; // @[Multiplier.scala:40:7, :81:38]
wire _sign_T_1 = io_req_bits_in1_0[63]; // @[Multiplier.scala:40:7, :81:48]
wire _sign_T_2 = io_req_bits_dw_0 ? _sign_T_1 : _sign_T; // @[Multiplier.scala:40:7, :81:{29,38,48}]
wire lhs_sign = lhsSigned & _sign_T_2; // @[Multiplier.scala:75:107, :81:{23,29}]
wire [31:0] _hi_T = {32{lhs_sign}}; // @[Multiplier.scala:81:23, :82:29]
wire [31:0] _hi_T_1 = io_req_bits_in1_0[63:32]; // @[Multiplier.scala:40:7, :82:43]
wire [31:0] hi = io_req_bits_dw_0 ? _hi_T_1 : _hi_T; // @[Multiplier.scala:40:7, :82:{17,29,43}]
wire [63:0] lhs_in = {hi, io_req_bits_in1_0[31:0]}; // @[Multiplier.scala:40:7, :82:17, :83:{9,15}]
wire _sign_T_3 = io_req_bits_in2_0[31]; // @[Multiplier.scala:40:7, :81:38]
wire _sign_T_4 = io_req_bits_in2_0[63]; // @[Multiplier.scala:40:7, :81:48]
wire _sign_T_5 = io_req_bits_dw_0 ? _sign_T_4 : _sign_T_3; // @[Multiplier.scala:40:7, :81:{29,38,48}]
wire rhs_sign = rhsSigned & _sign_T_5; // @[Multiplier.scala:75:107, :81:{23,29}]
wire [31:0] _hi_T_2 = {32{rhs_sign}}; // @[Multiplier.scala:81:23, :82:29]
wire [31:0] _hi_T_3 = io_req_bits_in2_0[63:32]; // @[Multiplier.scala:40:7, :82:43]
wire [31:0] hi_1 = io_req_bits_dw_0 ? _hi_T_3 : _hi_T_2; // @[Multiplier.scala:40:7, :82:{17,29,43}]
wire [63:0] rhs_in = {hi_1, io_req_bits_in2_0[31:0]}; // @[Multiplier.scala:40:7, :82:17, :83:{9,15}]
wire [64:0] _subtractor_T = remainder[128:64]; // @[Multiplier.scala:61:22, :88:29]
wire [65:0] _subtractor_T_1 = {1'h0, _subtractor_T} - {1'h0, divisor}; // @[Multiplier.scala:60:20, :88:{29,37}]
wire [64:0] subtractor = _subtractor_T_1[64:0]; // @[Multiplier.scala:88:37]
wire [63:0] _result_T = remainder[128:65]; // @[Multiplier.scala:61:22, :89:36]
wire [63:0] _io_resp_bits_full_data_T = remainder[128:65]; // @[Multiplier.scala:61:22, :89:36, :181:42]
wire [63:0] _result_T_1 = remainder[63:0]; // @[Multiplier.scala:61:22, :89:57]
wire [63:0] _mulReg_T_1 = remainder[63:0]; // @[Multiplier.scala:61:22, :89:57, :107:55]
wire [63:0] _unrolls_T_3 = remainder[63:0]; // @[Multiplier.scala:61:22, :89:57, :134:58]
wire [63:0] _dividendMSB_T = remainder[63:0]; // @[Multiplier.scala:61:22, :89:57, :151:39]
wire [63:0] _remainder_T_3 = remainder[63:0]; // @[Multiplier.scala:61:22, :89:57, :155:31]
wire [63:0] _io_resp_bits_full_data_T_1 = remainder[63:0]; // @[Multiplier.scala:61:22, :89:57, :181:63]
wire [63:0] result = resHi ? _result_T : _result_T_1; // @[Multiplier.scala:59:18, :89:{19,36,57}]
wire [64:0] _negated_remainder_T = 65'h0 - {1'h0, result}; // @[Multiplier.scala:89:19, :90:27]
wire [63:0] negated_remainder = _negated_remainder_T[63:0]; // @[Multiplier.scala:90:27]
wire [64:0] _mulReg_T = remainder[129:65]; // @[Multiplier.scala:61:22, :107:31]
wire [128:0] mulReg = {_mulReg_T, _mulReg_T_1}; // @[Multiplier.scala:107:{21,31,55}]
wire mplierSign = remainder[64]; // @[Multiplier.scala:61:22, :108:31]
wire [63:0] mplier = mulReg[63:0]; // @[Multiplier.scala:107:21, :109:24]
wire [64:0] _accum_T = mulReg[128:64]; // @[Multiplier.scala:107:21, :110:23]
wire [64:0] accum = _accum_T; // @[Multiplier.scala:110:{23,37}]
wire _prod_T = mplier[0]; // @[Multiplier.scala:109:24, :112:38]
wire [1:0] _prod_T_1 = {mplierSign, _prod_T}; // @[Multiplier.scala:108:31, :112:{19,38}]
wire [1:0] _prod_T_2 = _prod_T_1; // @[Multiplier.scala:112:{19,60}]
wire [66:0] _prod_T_3 = {{65{_prod_T_2[1]}}, _prod_T_2} * {{2{mpcand[64]}}, mpcand}; // @[Multiplier.scala:111:26, :112:{60,67}]
wire [67:0] _prod_T_4 = {_prod_T_3[66], _prod_T_3} + {{3{accum[64]}}, accum}; // @[Multiplier.scala:110:37, :112:{67,76}]
wire [66:0] _prod_T_5 = _prod_T_4[66:0]; // @[Multiplier.scala:112:76]
wire [66:0] prod = _prod_T_5; // @[Multiplier.scala:112:76]
wire [66:0] nextMulReg_hi = prod; // @[Multiplier.scala:112:76, :113:25]
wire [62:0] _nextMulReg_T = mplier[63:1]; // @[Multiplier.scala:109:24, :113:38]
wire [129:0] nextMulReg = {nextMulReg_hi, _nextMulReg_T}; // @[Multiplier.scala:113:{25,38}]
wire [129:0] _nextMulReg1_T_1 = nextMulReg; // @[Multiplier.scala:113:25, :120:55]
wire _nextMplierSign_T = count == 7'h3E; // @[Multiplier.scala:54:18, :114:32]
wire nextMplierSign = _nextMplierSign_T & neg_out; // @[Multiplier.scala:57:20, :114:{32,61}]
wire [7:0] _GEN = {1'h0, count}; // @[Multiplier.scala:54:18, :116:54]
wire [7:0] _eOutMask_T; // @[Multiplier.scala:116:54]
assign _eOutMask_T = _GEN; // @[Multiplier.scala:116:54]
wire [7:0] _eOutRes_T; // @[Multiplier.scala:119:46]
assign _eOutRes_T = _GEN; // @[Multiplier.scala:116:54, :119:46]
wire [5:0] _eOutMask_T_1 = _eOutMask_T[5:0]; // @[Multiplier.scala:116:{54,72}]
wire [64:0] _eOutMask_T_2 = $signed(65'sh10000000000000000 >>> _eOutMask_T_1); // @[Multiplier.scala:116:{44,72}]
wire [63:0] eOutMask = _eOutMask_T_2[63:0]; // @[Multiplier.scala:116:{44,91}]
wire _eOut_T = count != 7'h3F; // @[Multiplier.scala:54:18, :117:45]
wire _eOut_T_2 = |count; // @[Multiplier.scala:54:18, :117:83]
wire _eOut_T_4 = ~isHi; // @[Multiplier.scala:58:17, :118:7]
wire [63:0] _eOut_T_6 = ~eOutMask; // @[Multiplier.scala:116:91, :118:26]
wire [63:0] _eOut_T_7 = mplier & _eOut_T_6; // @[Multiplier.scala:109:24, :118:{24,26}]
wire _eOut_T_8 = _eOut_T_7 == 64'h0; // @[Multiplier.scala:118:{24,37}]
wire [8:0] _eOutRes_T_1 = 9'h40 - {1'h0, _eOutRes_T}; // @[Multiplier.scala:119:{38,46}]
wire [7:0] _eOutRes_T_2 = _eOutRes_T_1[7:0]; // @[Multiplier.scala:119:38]
wire [5:0] _eOutRes_T_3 = _eOutRes_T_2[5:0]; // @[Multiplier.scala:119:{38,64}]
wire [128:0] eOutRes = mulReg >> _eOutRes_T_3; // @[Multiplier.scala:107:21, :119:{27,64}]
wire [64:0] _nextMulReg1_T = nextMulReg[128:64]; // @[Multiplier.scala:113:25, :120:37]
wire [63:0] _nextMulReg1_T_2 = _nextMulReg1_T_1[63:0]; // @[Multiplier.scala:120:{55,82}]
wire [128:0] nextMulReg1 = {_nextMulReg1_T, _nextMulReg1_T_2}; // @[Multiplier.scala:120:{26,37,82}]
wire [64:0] _remainder_T = nextMulReg1[128:64]; // @[Multiplier.scala:120:26, :121:34]
wire [63:0] _remainder_T_1 = nextMulReg1[63:0]; // @[Multiplier.scala:120:26, :121:67]
wire [65:0] remainder_hi = {_remainder_T, nextMplierSign}; // @[Multiplier.scala:114:61, :121:{21,34}]
wire [129:0] _remainder_T_2 = {remainder_hi, _remainder_T_1}; // @[Multiplier.scala:121:{21,67}]
wire [7:0] _GEN_0 = _GEN + 8'h1; // @[Multiplier.scala:116:54, :123:20]
wire [7:0] _count_T; // @[Multiplier.scala:123:20]
assign _count_T = _GEN_0; // @[Multiplier.scala:123:20]
wire [7:0] _count_T_2; // @[Multiplier.scala:144:20]
assign _count_T_2 = _GEN_0; // @[Multiplier.scala:123:20, :144:20]
wire [6:0] _count_T_1 = _count_T[6:0]; // @[Multiplier.scala:123:20]
wire unrolls_less = subtractor[64]; // @[Multiplier.scala:88:37, :133:28]
wire _divby0_T_1 = subtractor[64]; // @[Multiplier.scala:88:37, :133:28, :146:46]
wire [63:0] _unrolls_T = remainder[127:64]; // @[Multiplier.scala:61:22, :134:24]
wire [63:0] _unrolls_T_1 = subtractor[63:0]; // @[Multiplier.scala:88:37, :134:45]
wire [63:0] _unrolls_T_2 = unrolls_less ? _unrolls_T : _unrolls_T_1; // @[Multiplier.scala:133:28, :134:{14,24,45}]
wire _unrolls_T_4 = ~unrolls_less; // @[Multiplier.scala:133:28, :134:67]
wire [127:0] unrolls_hi = {_unrolls_T_2, _unrolls_T_3}; // @[Multiplier.scala:134:{10,14,58}]
wire [128:0] unrolls_0 = {unrolls_hi, _unrolls_T_4}; // @[Multiplier.scala:134:{10,67}]
wire [2:0] _state_T = {1'h1, ~neg_out, 1'h1}; // @[Multiplier.scala:57:20, :139:19]
wire [6:0] _count_T_3 = _count_T_2[6:0]; // @[Multiplier.scala:144:20]
wire _divby0_T = ~(|count); // @[Multiplier.scala:54:18, :117:83, :146:24]
wire _divby0_T_2 = ~_divby0_T_1; // @[Multiplier.scala:146:{35,46}]
wire divby0 = _divby0_T & _divby0_T_2; // @[Multiplier.scala:146:{24,32,35}]
wire [63:0] _divisorMSB_T = divisor[63:0]; // @[Multiplier.scala:60:20, :150:36]
wire [31:0] divisorMSB_hi = _divisorMSB_T[63:32]; // @[CircuitMath.scala:33:17]
wire [31:0] divisorMSB_lo = _divisorMSB_T[31:0]; // @[CircuitMath.scala:34:17]
wire divisorMSB_useHi = |divisorMSB_hi; // @[CircuitMath.scala:33:17, :35:22]
wire [15:0] divisorMSB_hi_1 = divisorMSB_hi[31:16]; // @[CircuitMath.scala:33:17]
wire [15:0] divisorMSB_lo_1 = divisorMSB_hi[15:0]; // @[CircuitMath.scala:33:17, :34:17]
wire divisorMSB_useHi_1 = |divisorMSB_hi_1; // @[CircuitMath.scala:33:17, :35:22]
wire [7:0] divisorMSB_hi_2 = divisorMSB_hi_1[15:8]; // @[CircuitMath.scala:33:17]
wire [7:0] divisorMSB_lo_2 = divisorMSB_hi_1[7:0]; // @[CircuitMath.scala:33:17, :34:17]
wire divisorMSB_useHi_2 = |divisorMSB_hi_2; // @[CircuitMath.scala:33:17, :35:22]
wire [3:0] divisorMSB_hi_3 = divisorMSB_hi_2[7:4]; // @[CircuitMath.scala:33:17]
wire [3:0] divisorMSB_lo_3 = divisorMSB_hi_2[3:0]; // @[CircuitMath.scala:33:17, :34:17]
wire divisorMSB_useHi_3 = |divisorMSB_hi_3; // @[CircuitMath.scala:33:17, :35:22]
wire _divisorMSB_T_1 = divisorMSB_hi_3[3]; // @[CircuitMath.scala:30:12, :33:17]
wire _divisorMSB_T_2 = divisorMSB_hi_3[2]; // @[CircuitMath.scala:30:12, :33:17]
wire _divisorMSB_T_3 = divisorMSB_hi_3[1]; // @[CircuitMath.scala:28:8, :33:17]
wire [1:0] _divisorMSB_T_4 = _divisorMSB_T_2 ? 2'h2 : {1'h0, _divisorMSB_T_3}; // @[CircuitMath.scala:28:8, :30:{10,12}]
wire [1:0] _divisorMSB_T_5 = _divisorMSB_T_1 ? 2'h3 : _divisorMSB_T_4; // @[CircuitMath.scala:30:{10,12}]
wire _divisorMSB_T_6 = divisorMSB_lo_3[3]; // @[CircuitMath.scala:30:12, :34:17]
wire _divisorMSB_T_7 = divisorMSB_lo_3[2]; // @[CircuitMath.scala:30:12, :34:17]
wire _divisorMSB_T_8 = divisorMSB_lo_3[1]; // @[CircuitMath.scala:28:8, :34:17]
wire [1:0] _divisorMSB_T_9 = _divisorMSB_T_7 ? 2'h2 : {1'h0, _divisorMSB_T_8}; // @[CircuitMath.scala:28:8, :30:{10,12}]
wire [1:0] _divisorMSB_T_10 = _divisorMSB_T_6 ? 2'h3 : _divisorMSB_T_9; // @[CircuitMath.scala:30:{10,12}]
wire [1:0] _divisorMSB_T_11 = divisorMSB_useHi_3 ? _divisorMSB_T_5 : _divisorMSB_T_10; // @[CircuitMath.scala:30:10, :35:22, :36:21]
wire [2:0] _divisorMSB_T_12 = {divisorMSB_useHi_3, _divisorMSB_T_11}; // @[CircuitMath.scala:35:22, :36:{10,21}]
wire [3:0] divisorMSB_hi_4 = divisorMSB_lo_2[7:4]; // @[CircuitMath.scala:33:17, :34:17]
wire [3:0] divisorMSB_lo_4 = divisorMSB_lo_2[3:0]; // @[CircuitMath.scala:34:17]
wire divisorMSB_useHi_4 = |divisorMSB_hi_4; // @[CircuitMath.scala:33:17, :35:22]
wire _divisorMSB_T_13 = divisorMSB_hi_4[3]; // @[CircuitMath.scala:30:12, :33:17]
wire _divisorMSB_T_14 = divisorMSB_hi_4[2]; // @[CircuitMath.scala:30:12, :33:17]
wire _divisorMSB_T_15 = divisorMSB_hi_4[1]; // @[CircuitMath.scala:28:8, :33:17]
wire [1:0] _divisorMSB_T_16 = _divisorMSB_T_14 ? 2'h2 : {1'h0, _divisorMSB_T_15}; // @[CircuitMath.scala:28:8, :30:{10,12}]
wire [1:0] _divisorMSB_T_17 = _divisorMSB_T_13 ? 2'h3 : _divisorMSB_T_16; // @[CircuitMath.scala:30:{10,12}]
wire _divisorMSB_T_18 = divisorMSB_lo_4[3]; // @[CircuitMath.scala:30:12, :34:17]
wire _divisorMSB_T_19 = divisorMSB_lo_4[2]; // @[CircuitMath.scala:30:12, :34:17]
wire _divisorMSB_T_20 = divisorMSB_lo_4[1]; // @[CircuitMath.scala:28:8, :34:17]
wire [1:0] _divisorMSB_T_21 = _divisorMSB_T_19 ? 2'h2 : {1'h0, _divisorMSB_T_20}; // @[CircuitMath.scala:28:8, :30:{10,12}]
wire [1:0] _divisorMSB_T_22 = _divisorMSB_T_18 ? 2'h3 : _divisorMSB_T_21; // @[CircuitMath.scala:30:{10,12}]
wire [1:0] _divisorMSB_T_23 = divisorMSB_useHi_4 ? _divisorMSB_T_17 : _divisorMSB_T_22; // @[CircuitMath.scala:30:10, :35:22, :36:21]
wire [2:0] _divisorMSB_T_24 = {divisorMSB_useHi_4, _divisorMSB_T_23}; // @[CircuitMath.scala:35:22, :36:{10,21}]
wire [2:0] _divisorMSB_T_25 = divisorMSB_useHi_2 ? _divisorMSB_T_12 : _divisorMSB_T_24; // @[CircuitMath.scala:35:22, :36:{10,21}]
wire [3:0] _divisorMSB_T_26 = {divisorMSB_useHi_2, _divisorMSB_T_25}; // @[CircuitMath.scala:35:22, :36:{10,21}]
wire [7:0] divisorMSB_hi_5 = divisorMSB_lo_1[15:8]; // @[CircuitMath.scala:33:17, :34:17]
wire [7:0] divisorMSB_lo_5 = divisorMSB_lo_1[7:0]; // @[CircuitMath.scala:34:17]
wire divisorMSB_useHi_5 = |divisorMSB_hi_5; // @[CircuitMath.scala:33:17, :35:22]
wire [3:0] divisorMSB_hi_6 = divisorMSB_hi_5[7:4]; // @[CircuitMath.scala:33:17]
wire [3:0] divisorMSB_lo_6 = divisorMSB_hi_5[3:0]; // @[CircuitMath.scala:33:17, :34:17]
wire divisorMSB_useHi_6 = |divisorMSB_hi_6; // @[CircuitMath.scala:33:17, :35:22]
wire _divisorMSB_T_27 = divisorMSB_hi_6[3]; // @[CircuitMath.scala:30:12, :33:17]
wire _divisorMSB_T_28 = divisorMSB_hi_6[2]; // @[CircuitMath.scala:30:12, :33:17]
wire _divisorMSB_T_29 = divisorMSB_hi_6[1]; // @[CircuitMath.scala:28:8, :33:17]
wire [1:0] _divisorMSB_T_30 = _divisorMSB_T_28 ? 2'h2 : {1'h0, _divisorMSB_T_29}; // @[CircuitMath.scala:28:8, :30:{10,12}]
wire [1:0] _divisorMSB_T_31 = _divisorMSB_T_27 ? 2'h3 : _divisorMSB_T_30; // @[CircuitMath.scala:30:{10,12}]
wire _divisorMSB_T_32 = divisorMSB_lo_6[3]; // @[CircuitMath.scala:30:12, :34:17]
wire _divisorMSB_T_33 = divisorMSB_lo_6[2]; // @[CircuitMath.scala:30:12, :34:17]
wire _divisorMSB_T_34 = divisorMSB_lo_6[1]; // @[CircuitMath.scala:28:8, :34:17]
wire [1:0] _divisorMSB_T_35 = _divisorMSB_T_33 ? 2'h2 : {1'h0, _divisorMSB_T_34}; // @[CircuitMath.scala:28:8, :30:{10,12}]
wire [1:0] _divisorMSB_T_36 = _divisorMSB_T_32 ? 2'h3 : _divisorMSB_T_35; // @[CircuitMath.scala:30:{10,12}]
wire [1:0] _divisorMSB_T_37 = divisorMSB_useHi_6 ? _divisorMSB_T_31 : _divisorMSB_T_36; // @[CircuitMath.scala:30:10, :35:22, :36:21]
wire [2:0] _divisorMSB_T_38 = {divisorMSB_useHi_6, _divisorMSB_T_37}; // @[CircuitMath.scala:35:22, :36:{10,21}]
wire [3:0] divisorMSB_hi_7 = divisorMSB_lo_5[7:4]; // @[CircuitMath.scala:33:17, :34:17]
wire [3:0] divisorMSB_lo_7 = divisorMSB_lo_5[3:0]; // @[CircuitMath.scala:34:17]
wire divisorMSB_useHi_7 = |divisorMSB_hi_7; // @[CircuitMath.scala:33:17, :35:22]
wire _divisorMSB_T_39 = divisorMSB_hi_7[3]; // @[CircuitMath.scala:30:12, :33:17]
wire _divisorMSB_T_40 = divisorMSB_hi_7[2]; // @[CircuitMath.scala:30:12, :33:17]
wire _divisorMSB_T_41 = divisorMSB_hi_7[1]; // @[CircuitMath.scala:28:8, :33:17]
wire [1:0] _divisorMSB_T_42 = _divisorMSB_T_40 ? 2'h2 : {1'h0, _divisorMSB_T_41}; // @[CircuitMath.scala:28:8, :30:{10,12}]
wire [1:0] _divisorMSB_T_43 = _divisorMSB_T_39 ? 2'h3 : _divisorMSB_T_42; // @[CircuitMath.scala:30:{10,12}]
wire _divisorMSB_T_44 = divisorMSB_lo_7[3]; // @[CircuitMath.scala:30:12, :34:17]
wire _divisorMSB_T_45 = divisorMSB_lo_7[2]; // @[CircuitMath.scala:30:12, :34:17]
wire _divisorMSB_T_46 = divisorMSB_lo_7[1]; // @[CircuitMath.scala:28:8, :34:17]
wire [1:0] _divisorMSB_T_47 = _divisorMSB_T_45 ? 2'h2 : {1'h0, _divisorMSB_T_46}; // @[CircuitMath.scala:28:8, :30:{10,12}]
wire [1:0] _divisorMSB_T_48 = _divisorMSB_T_44 ? 2'h3 : _divisorMSB_T_47; // @[CircuitMath.scala:30:{10,12}]
wire [1:0] _divisorMSB_T_49 = divisorMSB_useHi_7 ? _divisorMSB_T_43 : _divisorMSB_T_48; // @[CircuitMath.scala:30:10, :35:22, :36:21]
wire [2:0] _divisorMSB_T_50 = {divisorMSB_useHi_7, _divisorMSB_T_49}; // @[CircuitMath.scala:35:22, :36:{10,21}]
wire [2:0] _divisorMSB_T_51 = divisorMSB_useHi_5 ? _divisorMSB_T_38 : _divisorMSB_T_50; // @[CircuitMath.scala:35:22, :36:{10,21}]
wire [3:0] _divisorMSB_T_52 = {divisorMSB_useHi_5, _divisorMSB_T_51}; // @[CircuitMath.scala:35:22, :36:{10,21}]
wire [3:0] _divisorMSB_T_53 = divisorMSB_useHi_1 ? _divisorMSB_T_26 : _divisorMSB_T_52; // @[CircuitMath.scala:35:22, :36:{10,21}]
wire [4:0] _divisorMSB_T_54 = {divisorMSB_useHi_1, _divisorMSB_T_53}; // @[CircuitMath.scala:35:22, :36:{10,21}]
wire [15:0] divisorMSB_hi_8 = divisorMSB_lo[31:16]; // @[CircuitMath.scala:33:17, :34:17]
wire [15:0] divisorMSB_lo_8 = divisorMSB_lo[15:0]; // @[CircuitMath.scala:34:17]
wire divisorMSB_useHi_8 = |divisorMSB_hi_8; // @[CircuitMath.scala:33:17, :35:22]
wire [7:0] divisorMSB_hi_9 = divisorMSB_hi_8[15:8]; // @[CircuitMath.scala:33:17]
wire [7:0] divisorMSB_lo_9 = divisorMSB_hi_8[7:0]; // @[CircuitMath.scala:33:17, :34:17]
wire divisorMSB_useHi_9 = |divisorMSB_hi_9; // @[CircuitMath.scala:33:17, :35:22]
wire [3:0] divisorMSB_hi_10 = divisorMSB_hi_9[7:4]; // @[CircuitMath.scala:33:17]
wire [3:0] divisorMSB_lo_10 = divisorMSB_hi_9[3:0]; // @[CircuitMath.scala:33:17, :34:17]
wire divisorMSB_useHi_10 = |divisorMSB_hi_10; // @[CircuitMath.scala:33:17, :35:22]
wire _divisorMSB_T_55 = divisorMSB_hi_10[3]; // @[CircuitMath.scala:30:12, :33:17]
wire _divisorMSB_T_56 = divisorMSB_hi_10[2]; // @[CircuitMath.scala:30:12, :33:17]
wire _divisorMSB_T_57 = divisorMSB_hi_10[1]; // @[CircuitMath.scala:28:8, :33:17]
wire [1:0] _divisorMSB_T_58 = _divisorMSB_T_56 ? 2'h2 : {1'h0, _divisorMSB_T_57}; // @[CircuitMath.scala:28:8, :30:{10,12}]
wire [1:0] _divisorMSB_T_59 = _divisorMSB_T_55 ? 2'h3 : _divisorMSB_T_58; // @[CircuitMath.scala:30:{10,12}]
wire _divisorMSB_T_60 = divisorMSB_lo_10[3]; // @[CircuitMath.scala:30:12, :34:17]
wire _divisorMSB_T_61 = divisorMSB_lo_10[2]; // @[CircuitMath.scala:30:12, :34:17]
wire _divisorMSB_T_62 = divisorMSB_lo_10[1]; // @[CircuitMath.scala:28:8, :34:17]
wire [1:0] _divisorMSB_T_63 = _divisorMSB_T_61 ? 2'h2 : {1'h0, _divisorMSB_T_62}; // @[CircuitMath.scala:28:8, :30:{10,12}]
wire [1:0] _divisorMSB_T_64 = _divisorMSB_T_60 ? 2'h3 : _divisorMSB_T_63; // @[CircuitMath.scala:30:{10,12}]
wire [1:0] _divisorMSB_T_65 = divisorMSB_useHi_10 ? _divisorMSB_T_59 : _divisorMSB_T_64; // @[CircuitMath.scala:30:10, :35:22, :36:21]
wire [2:0] _divisorMSB_T_66 = {divisorMSB_useHi_10, _divisorMSB_T_65}; // @[CircuitMath.scala:35:22, :36:{10,21}]
wire [3:0] divisorMSB_hi_11 = divisorMSB_lo_9[7:4]; // @[CircuitMath.scala:33:17, :34:17]
wire [3:0] divisorMSB_lo_11 = divisorMSB_lo_9[3:0]; // @[CircuitMath.scala:34:17]
wire divisorMSB_useHi_11 = |divisorMSB_hi_11; // @[CircuitMath.scala:33:17, :35:22]
wire _divisorMSB_T_67 = divisorMSB_hi_11[3]; // @[CircuitMath.scala:30:12, :33:17]
wire _divisorMSB_T_68 = divisorMSB_hi_11[2]; // @[CircuitMath.scala:30:12, :33:17]
wire _divisorMSB_T_69 = divisorMSB_hi_11[1]; // @[CircuitMath.scala:28:8, :33:17]
wire [1:0] _divisorMSB_T_70 = _divisorMSB_T_68 ? 2'h2 : {1'h0, _divisorMSB_T_69}; // @[CircuitMath.scala:28:8, :30:{10,12}]
wire [1:0] _divisorMSB_T_71 = _divisorMSB_T_67 ? 2'h3 : _divisorMSB_T_70; // @[CircuitMath.scala:30:{10,12}]
wire _divisorMSB_T_72 = divisorMSB_lo_11[3]; // @[CircuitMath.scala:30:12, :34:17]
wire _divisorMSB_T_73 = divisorMSB_lo_11[2]; // @[CircuitMath.scala:30:12, :34:17]
wire _divisorMSB_T_74 = divisorMSB_lo_11[1]; // @[CircuitMath.scala:28:8, :34:17]
wire [1:0] _divisorMSB_T_75 = _divisorMSB_T_73 ? 2'h2 : {1'h0, _divisorMSB_T_74}; // @[CircuitMath.scala:28:8, :30:{10,12}]
wire [1:0] _divisorMSB_T_76 = _divisorMSB_T_72 ? 2'h3 : _divisorMSB_T_75; // @[CircuitMath.scala:30:{10,12}]
wire [1:0] _divisorMSB_T_77 = divisorMSB_useHi_11 ? _divisorMSB_T_71 : _divisorMSB_T_76; // @[CircuitMath.scala:30:10, :35:22, :36:21]
wire [2:0] _divisorMSB_T_78 = {divisorMSB_useHi_11, _divisorMSB_T_77}; // @[CircuitMath.scala:35:22, :36:{10,21}]
wire [2:0] _divisorMSB_T_79 = divisorMSB_useHi_9 ? _divisorMSB_T_66 : _divisorMSB_T_78; // @[CircuitMath.scala:35:22, :36:{10,21}]
wire [3:0] _divisorMSB_T_80 = {divisorMSB_useHi_9, _divisorMSB_T_79}; // @[CircuitMath.scala:35:22, :36:{10,21}]
wire [7:0] divisorMSB_hi_12 = divisorMSB_lo_8[15:8]; // @[CircuitMath.scala:33:17, :34:17]
wire [7:0] divisorMSB_lo_12 = divisorMSB_lo_8[7:0]; // @[CircuitMath.scala:34:17]
wire divisorMSB_useHi_12 = |divisorMSB_hi_12; // @[CircuitMath.scala:33:17, :35:22]
wire [3:0] divisorMSB_hi_13 = divisorMSB_hi_12[7:4]; // @[CircuitMath.scala:33:17]
wire [3:0] divisorMSB_lo_13 = divisorMSB_hi_12[3:0]; // @[CircuitMath.scala:33:17, :34:17]
wire divisorMSB_useHi_13 = |divisorMSB_hi_13; // @[CircuitMath.scala:33:17, :35:22]
wire _divisorMSB_T_81 = divisorMSB_hi_13[3]; // @[CircuitMath.scala:30:12, :33:17]
wire _divisorMSB_T_82 = divisorMSB_hi_13[2]; // @[CircuitMath.scala:30:12, :33:17]
wire _divisorMSB_T_83 = divisorMSB_hi_13[1]; // @[CircuitMath.scala:28:8, :33:17]
wire [1:0] _divisorMSB_T_84 = _divisorMSB_T_82 ? 2'h2 : {1'h0, _divisorMSB_T_83}; // @[CircuitMath.scala:28:8, :30:{10,12}]
wire [1:0] _divisorMSB_T_85 = _divisorMSB_T_81 ? 2'h3 : _divisorMSB_T_84; // @[CircuitMath.scala:30:{10,12}]
wire _divisorMSB_T_86 = divisorMSB_lo_13[3]; // @[CircuitMath.scala:30:12, :34:17]
wire _divisorMSB_T_87 = divisorMSB_lo_13[2]; // @[CircuitMath.scala:30:12, :34:17]
wire _divisorMSB_T_88 = divisorMSB_lo_13[1]; // @[CircuitMath.scala:28:8, :34:17]
wire [1:0] _divisorMSB_T_89 = _divisorMSB_T_87 ? 2'h2 : {1'h0, _divisorMSB_T_88}; // @[CircuitMath.scala:28:8, :30:{10,12}]
wire [1:0] _divisorMSB_T_90 = _divisorMSB_T_86 ? 2'h3 : _divisorMSB_T_89; // @[CircuitMath.scala:30:{10,12}]
wire [1:0] _divisorMSB_T_91 = divisorMSB_useHi_13 ? _divisorMSB_T_85 : _divisorMSB_T_90; // @[CircuitMath.scala:30:10, :35:22, :36:21]
wire [2:0] _divisorMSB_T_92 = {divisorMSB_useHi_13, _divisorMSB_T_91}; // @[CircuitMath.scala:35:22, :36:{10,21}]
wire [3:0] divisorMSB_hi_14 = divisorMSB_lo_12[7:4]; // @[CircuitMath.scala:33:17, :34:17]
wire [3:0] divisorMSB_lo_14 = divisorMSB_lo_12[3:0]; // @[CircuitMath.scala:34:17]
wire divisorMSB_useHi_14 = |divisorMSB_hi_14; // @[CircuitMath.scala:33:17, :35:22]
wire _divisorMSB_T_93 = divisorMSB_hi_14[3]; // @[CircuitMath.scala:30:12, :33:17]
wire _divisorMSB_T_94 = divisorMSB_hi_14[2]; // @[CircuitMath.scala:30:12, :33:17]
wire _divisorMSB_T_95 = divisorMSB_hi_14[1]; // @[CircuitMath.scala:28:8, :33:17]
wire [1:0] _divisorMSB_T_96 = _divisorMSB_T_94 ? 2'h2 : {1'h0, _divisorMSB_T_95}; // @[CircuitMath.scala:28:8, :30:{10,12}]
wire [1:0] _divisorMSB_T_97 = _divisorMSB_T_93 ? 2'h3 : _divisorMSB_T_96; // @[CircuitMath.scala:30:{10,12}]
wire _divisorMSB_T_98 = divisorMSB_lo_14[3]; // @[CircuitMath.scala:30:12, :34:17]
wire _divisorMSB_T_99 = divisorMSB_lo_14[2]; // @[CircuitMath.scala:30:12, :34:17]
wire _divisorMSB_T_100 = divisorMSB_lo_14[1]; // @[CircuitMath.scala:28:8, :34:17]
wire [1:0] _divisorMSB_T_101 = _divisorMSB_T_99 ? 2'h2 : {1'h0, _divisorMSB_T_100}; // @[CircuitMath.scala:28:8, :30:{10,12}]
wire [1:0] _divisorMSB_T_102 = _divisorMSB_T_98 ? 2'h3 : _divisorMSB_T_101; // @[CircuitMath.scala:30:{10,12}]
wire [1:0] _divisorMSB_T_103 = divisorMSB_useHi_14 ? _divisorMSB_T_97 : _divisorMSB_T_102; // @[CircuitMath.scala:30:10, :35:22, :36:21]
wire [2:0] _divisorMSB_T_104 = {divisorMSB_useHi_14, _divisorMSB_T_103}; // @[CircuitMath.scala:35:22, :36:{10,21}]
wire [2:0] _divisorMSB_T_105 = divisorMSB_useHi_12 ? _divisorMSB_T_92 : _divisorMSB_T_104; // @[CircuitMath.scala:35:22, :36:{10,21}]
wire [3:0] _divisorMSB_T_106 = {divisorMSB_useHi_12, _divisorMSB_T_105}; // @[CircuitMath.scala:35:22, :36:{10,21}]
wire [3:0] _divisorMSB_T_107 = divisorMSB_useHi_8 ? _divisorMSB_T_80 : _divisorMSB_T_106; // @[CircuitMath.scala:35:22, :36:{10,21}]
wire [4:0] _divisorMSB_T_108 = {divisorMSB_useHi_8, _divisorMSB_T_107}; // @[CircuitMath.scala:35:22, :36:{10,21}]
wire [4:0] _divisorMSB_T_109 = divisorMSB_useHi ? _divisorMSB_T_54 : _divisorMSB_T_108; // @[CircuitMath.scala:35:22, :36:{10,21}]
wire [5:0] _divisorMSB_T_110 = {divisorMSB_useHi, _divisorMSB_T_109}; // @[CircuitMath.scala:35:22, :36:{10,21}]
wire [5:0] divisorMSB = _divisorMSB_T_110; // @[CircuitMath.scala:36:10]
wire [31:0] dividendMSB_hi = _dividendMSB_T[63:32]; // @[CircuitMath.scala:33:17]
wire [31:0] dividendMSB_lo = _dividendMSB_T[31:0]; // @[CircuitMath.scala:34:17]
wire dividendMSB_useHi = |dividendMSB_hi; // @[CircuitMath.scala:33:17, :35:22]
wire [15:0] dividendMSB_hi_1 = dividendMSB_hi[31:16]; // @[CircuitMath.scala:33:17]
wire [15:0] dividendMSB_lo_1 = dividendMSB_hi[15:0]; // @[CircuitMath.scala:33:17, :34:17]
wire dividendMSB_useHi_1 = |dividendMSB_hi_1; // @[CircuitMath.scala:33:17, :35:22]
wire [7:0] dividendMSB_hi_2 = dividendMSB_hi_1[15:8]; // @[CircuitMath.scala:33:17]
wire [7:0] dividendMSB_lo_2 = dividendMSB_hi_1[7:0]; // @[CircuitMath.scala:33:17, :34:17]
wire dividendMSB_useHi_2 = |dividendMSB_hi_2; // @[CircuitMath.scala:33:17, :35:22]
wire [3:0] dividendMSB_hi_3 = dividendMSB_hi_2[7:4]; // @[CircuitMath.scala:33:17]
wire [3:0] dividendMSB_lo_3 = dividendMSB_hi_2[3:0]; // @[CircuitMath.scala:33:17, :34:17]
wire dividendMSB_useHi_3 = |dividendMSB_hi_3; // @[CircuitMath.scala:33:17, :35:22]
wire _dividendMSB_T_1 = dividendMSB_hi_3[3]; // @[CircuitMath.scala:30:12, :33:17]
wire _dividendMSB_T_2 = dividendMSB_hi_3[2]; // @[CircuitMath.scala:30:12, :33:17]
wire _dividendMSB_T_3 = dividendMSB_hi_3[1]; // @[CircuitMath.scala:28:8, :33:17]
wire [1:0] _dividendMSB_T_4 = _dividendMSB_T_2 ? 2'h2 : {1'h0, _dividendMSB_T_3}; // @[CircuitMath.scala:28:8, :30:{10,12}]
wire [1:0] _dividendMSB_T_5 = _dividendMSB_T_1 ? 2'h3 : _dividendMSB_T_4; // @[CircuitMath.scala:30:{10,12}]
wire _dividendMSB_T_6 = dividendMSB_lo_3[3]; // @[CircuitMath.scala:30:12, :34:17]
wire _dividendMSB_T_7 = dividendMSB_lo_3[2]; // @[CircuitMath.scala:30:12, :34:17]
wire _dividendMSB_T_8 = dividendMSB_lo_3[1]; // @[CircuitMath.scala:28:8, :34:17]
wire [1:0] _dividendMSB_T_9 = _dividendMSB_T_7 ? 2'h2 : {1'h0, _dividendMSB_T_8}; // @[CircuitMath.scala:28:8, :30:{10,12}]
wire [1:0] _dividendMSB_T_10 = _dividendMSB_T_6 ? 2'h3 : _dividendMSB_T_9; // @[CircuitMath.scala:30:{10,12}]
wire [1:0] _dividendMSB_T_11 = dividendMSB_useHi_3 ? _dividendMSB_T_5 : _dividendMSB_T_10; // @[CircuitMath.scala:30:10, :35:22, :36:21]
wire [2:0] _dividendMSB_T_12 = {dividendMSB_useHi_3, _dividendMSB_T_11}; // @[CircuitMath.scala:35:22, :36:{10,21}]
wire [3:0] dividendMSB_hi_4 = dividendMSB_lo_2[7:4]; // @[CircuitMath.scala:33:17, :34:17]
wire [3:0] dividendMSB_lo_4 = dividendMSB_lo_2[3:0]; // @[CircuitMath.scala:34:17]
wire dividendMSB_useHi_4 = |dividendMSB_hi_4; // @[CircuitMath.scala:33:17, :35:22]
wire _dividendMSB_T_13 = dividendMSB_hi_4[3]; // @[CircuitMath.scala:30:12, :33:17]
wire _dividendMSB_T_14 = dividendMSB_hi_4[2]; // @[CircuitMath.scala:30:12, :33:17]
wire _dividendMSB_T_15 = dividendMSB_hi_4[1]; // @[CircuitMath.scala:28:8, :33:17]
wire [1:0] _dividendMSB_T_16 = _dividendMSB_T_14 ? 2'h2 : {1'h0, _dividendMSB_T_15}; // @[CircuitMath.scala:28:8, :30:{10,12}]
wire [1:0] _dividendMSB_T_17 = _dividendMSB_T_13 ? 2'h3 : _dividendMSB_T_16; // @[CircuitMath.scala:30:{10,12}]
wire _dividendMSB_T_18 = dividendMSB_lo_4[3]; // @[CircuitMath.scala:30:12, :34:17]
wire _dividendMSB_T_19 = dividendMSB_lo_4[2]; // @[CircuitMath.scala:30:12, :34:17]
wire _dividendMSB_T_20 = dividendMSB_lo_4[1]; // @[CircuitMath.scala:28:8, :34:17]
wire [1:0] _dividendMSB_T_21 = _dividendMSB_T_19 ? 2'h2 : {1'h0, _dividendMSB_T_20}; // @[CircuitMath.scala:28:8, :30:{10,12}]
wire [1:0] _dividendMSB_T_22 = _dividendMSB_T_18 ? 2'h3 : _dividendMSB_T_21; // @[CircuitMath.scala:30:{10,12}]
wire [1:0] _dividendMSB_T_23 = dividendMSB_useHi_4 ? _dividendMSB_T_17 : _dividendMSB_T_22; // @[CircuitMath.scala:30:10, :35:22, :36:21]
wire [2:0] _dividendMSB_T_24 = {dividendMSB_useHi_4, _dividendMSB_T_23}; // @[CircuitMath.scala:35:22, :36:{10,21}]
wire [2:0] _dividendMSB_T_25 = dividendMSB_useHi_2 ? _dividendMSB_T_12 : _dividendMSB_T_24; // @[CircuitMath.scala:35:22, :36:{10,21}]
wire [3:0] _dividendMSB_T_26 = {dividendMSB_useHi_2, _dividendMSB_T_25}; // @[CircuitMath.scala:35:22, :36:{10,21}]
wire [7:0] dividendMSB_hi_5 = dividendMSB_lo_1[15:8]; // @[CircuitMath.scala:33:17, :34:17]
wire [7:0] dividendMSB_lo_5 = dividendMSB_lo_1[7:0]; // @[CircuitMath.scala:34:17]
wire dividendMSB_useHi_5 = |dividendMSB_hi_5; // @[CircuitMath.scala:33:17, :35:22]
wire [3:0] dividendMSB_hi_6 = dividendMSB_hi_5[7:4]; // @[CircuitMath.scala:33:17]
wire [3:0] dividendMSB_lo_6 = dividendMSB_hi_5[3:0]; // @[CircuitMath.scala:33:17, :34:17]
wire dividendMSB_useHi_6 = |dividendMSB_hi_6; // @[CircuitMath.scala:33:17, :35:22]
wire _dividendMSB_T_27 = dividendMSB_hi_6[3]; // @[CircuitMath.scala:30:12, :33:17]
wire _dividendMSB_T_28 = dividendMSB_hi_6[2]; // @[CircuitMath.scala:30:12, :33:17]
wire _dividendMSB_T_29 = dividendMSB_hi_6[1]; // @[CircuitMath.scala:28:8, :33:17]
wire [1:0] _dividendMSB_T_30 = _dividendMSB_T_28 ? 2'h2 : {1'h0, _dividendMSB_T_29}; // @[CircuitMath.scala:28:8, :30:{10,12}]
wire [1:0] _dividendMSB_T_31 = _dividendMSB_T_27 ? 2'h3 : _dividendMSB_T_30; // @[CircuitMath.scala:30:{10,12}]
wire _dividendMSB_T_32 = dividendMSB_lo_6[3]; // @[CircuitMath.scala:30:12, :34:17]
wire _dividendMSB_T_33 = dividendMSB_lo_6[2]; // @[CircuitMath.scala:30:12, :34:17]
wire _dividendMSB_T_34 = dividendMSB_lo_6[1]; // @[CircuitMath.scala:28:8, :34:17]
wire [1:0] _dividendMSB_T_35 = _dividendMSB_T_33 ? 2'h2 : {1'h0, _dividendMSB_T_34}; // @[CircuitMath.scala:28:8, :30:{10,12}]
wire [1:0] _dividendMSB_T_36 = _dividendMSB_T_32 ? 2'h3 : _dividendMSB_T_35; // @[CircuitMath.scala:30:{10,12}]
wire [1:0] _dividendMSB_T_37 = dividendMSB_useHi_6 ? _dividendMSB_T_31 : _dividendMSB_T_36; // @[CircuitMath.scala:30:10, :35:22, :36:21]
wire [2:0] _dividendMSB_T_38 = {dividendMSB_useHi_6, _dividendMSB_T_37}; // @[CircuitMath.scala:35:22, :36:{10,21}]
wire [3:0] dividendMSB_hi_7 = dividendMSB_lo_5[7:4]; // @[CircuitMath.scala:33:17, :34:17]
wire [3:0] dividendMSB_lo_7 = dividendMSB_lo_5[3:0]; // @[CircuitMath.scala:34:17]
wire dividendMSB_useHi_7 = |dividendMSB_hi_7; // @[CircuitMath.scala:33:17, :35:22]
wire _dividendMSB_T_39 = dividendMSB_hi_7[3]; // @[CircuitMath.scala:30:12, :33:17]
wire _dividendMSB_T_40 = dividendMSB_hi_7[2]; // @[CircuitMath.scala:30:12, :33:17]
wire _dividendMSB_T_41 = dividendMSB_hi_7[1]; // @[CircuitMath.scala:28:8, :33:17]
wire [1:0] _dividendMSB_T_42 = _dividendMSB_T_40 ? 2'h2 : {1'h0, _dividendMSB_T_41}; // @[CircuitMath.scala:28:8, :30:{10,12}]
wire [1:0] _dividendMSB_T_43 = _dividendMSB_T_39 ? 2'h3 : _dividendMSB_T_42; // @[CircuitMath.scala:30:{10,12}]
wire _dividendMSB_T_44 = dividendMSB_lo_7[3]; // @[CircuitMath.scala:30:12, :34:17]
wire _dividendMSB_T_45 = dividendMSB_lo_7[2]; // @[CircuitMath.scala:30:12, :34:17]
wire _dividendMSB_T_46 = dividendMSB_lo_7[1]; // @[CircuitMath.scala:28:8, :34:17]
wire [1:0] _dividendMSB_T_47 = _dividendMSB_T_45 ? 2'h2 : {1'h0, _dividendMSB_T_46}; // @[CircuitMath.scala:28:8, :30:{10,12}]
wire [1:0] _dividendMSB_T_48 = _dividendMSB_T_44 ? 2'h3 : _dividendMSB_T_47; // @[CircuitMath.scala:30:{10,12}]
wire [1:0] _dividendMSB_T_49 = dividendMSB_useHi_7 ? _dividendMSB_T_43 : _dividendMSB_T_48; // @[CircuitMath.scala:30:10, :35:22, :36:21]
wire [2:0] _dividendMSB_T_50 = {dividendMSB_useHi_7, _dividendMSB_T_49}; // @[CircuitMath.scala:35:22, :36:{10,21}]
wire [2:0] _dividendMSB_T_51 = dividendMSB_useHi_5 ? _dividendMSB_T_38 : _dividendMSB_T_50; // @[CircuitMath.scala:35:22, :36:{10,21}]
wire [3:0] _dividendMSB_T_52 = {dividendMSB_useHi_5, _dividendMSB_T_51}; // @[CircuitMath.scala:35:22, :36:{10,21}]
wire [3:0] _dividendMSB_T_53 = dividendMSB_useHi_1 ? _dividendMSB_T_26 : _dividendMSB_T_52; // @[CircuitMath.scala:35:22, :36:{10,21}]
wire [4:0] _dividendMSB_T_54 = {dividendMSB_useHi_1, _dividendMSB_T_53}; // @[CircuitMath.scala:35:22, :36:{10,21}]
wire [15:0] dividendMSB_hi_8 = dividendMSB_lo[31:16]; // @[CircuitMath.scala:33:17, :34:17]
wire [15:0] dividendMSB_lo_8 = dividendMSB_lo[15:0]; // @[CircuitMath.scala:34:17]
wire dividendMSB_useHi_8 = |dividendMSB_hi_8; // @[CircuitMath.scala:33:17, :35:22]
wire [7:0] dividendMSB_hi_9 = dividendMSB_hi_8[15:8]; // @[CircuitMath.scala:33:17]
wire [7:0] dividendMSB_lo_9 = dividendMSB_hi_8[7:0]; // @[CircuitMath.scala:33:17, :34:17]
wire dividendMSB_useHi_9 = |dividendMSB_hi_9; // @[CircuitMath.scala:33:17, :35:22]
wire [3:0] dividendMSB_hi_10 = dividendMSB_hi_9[7:4]; // @[CircuitMath.scala:33:17]
wire [3:0] dividendMSB_lo_10 = dividendMSB_hi_9[3:0]; // @[CircuitMath.scala:33:17, :34:17]
wire dividendMSB_useHi_10 = |dividendMSB_hi_10; // @[CircuitMath.scala:33:17, :35:22]
wire _dividendMSB_T_55 = dividendMSB_hi_10[3]; // @[CircuitMath.scala:30:12, :33:17]
wire _dividendMSB_T_56 = dividendMSB_hi_10[2]; // @[CircuitMath.scala:30:12, :33:17]
wire _dividendMSB_T_57 = dividendMSB_hi_10[1]; // @[CircuitMath.scala:28:8, :33:17]
wire [1:0] _dividendMSB_T_58 = _dividendMSB_T_56 ? 2'h2 : {1'h0, _dividendMSB_T_57}; // @[CircuitMath.scala:28:8, :30:{10,12}]
wire [1:0] _dividendMSB_T_59 = _dividendMSB_T_55 ? 2'h3 : _dividendMSB_T_58; // @[CircuitMath.scala:30:{10,12}]
wire _dividendMSB_T_60 = dividendMSB_lo_10[3]; // @[CircuitMath.scala:30:12, :34:17]
wire _dividendMSB_T_61 = dividendMSB_lo_10[2]; // @[CircuitMath.scala:30:12, :34:17]
wire _dividendMSB_T_62 = dividendMSB_lo_10[1]; // @[CircuitMath.scala:28:8, :34:17]
wire [1:0] _dividendMSB_T_63 = _dividendMSB_T_61 ? 2'h2 : {1'h0, _dividendMSB_T_62}; // @[CircuitMath.scala:28:8, :30:{10,12}]
wire [1:0] _dividendMSB_T_64 = _dividendMSB_T_60 ? 2'h3 : _dividendMSB_T_63; // @[CircuitMath.scala:30:{10,12}]
wire [1:0] _dividendMSB_T_65 = dividendMSB_useHi_10 ? _dividendMSB_T_59 : _dividendMSB_T_64; // @[CircuitMath.scala:30:10, :35:22, :36:21]
wire [2:0] _dividendMSB_T_66 = {dividendMSB_useHi_10, _dividendMSB_T_65}; // @[CircuitMath.scala:35:22, :36:{10,21}]
wire [3:0] dividendMSB_hi_11 = dividendMSB_lo_9[7:4]; // @[CircuitMath.scala:33:17, :34:17]
wire [3:0] dividendMSB_lo_11 = dividendMSB_lo_9[3:0]; // @[CircuitMath.scala:34:17]
wire dividendMSB_useHi_11 = |dividendMSB_hi_11; // @[CircuitMath.scala:33:17, :35:22]
wire _dividendMSB_T_67 = dividendMSB_hi_11[3]; // @[CircuitMath.scala:30:12, :33:17]
wire _dividendMSB_T_68 = dividendMSB_hi_11[2]; // @[CircuitMath.scala:30:12, :33:17]
wire _dividendMSB_T_69 = dividendMSB_hi_11[1]; // @[CircuitMath.scala:28:8, :33:17]
wire [1:0] _dividendMSB_T_70 = _dividendMSB_T_68 ? 2'h2 : {1'h0, _dividendMSB_T_69}; // @[CircuitMath.scala:28:8, :30:{10,12}]
wire [1:0] _dividendMSB_T_71 = _dividendMSB_T_67 ? 2'h3 : _dividendMSB_T_70; // @[CircuitMath.scala:30:{10,12}]
wire _dividendMSB_T_72 = dividendMSB_lo_11[3]; // @[CircuitMath.scala:30:12, :34:17]
wire _dividendMSB_T_73 = dividendMSB_lo_11[2]; // @[CircuitMath.scala:30:12, :34:17]
wire _dividendMSB_T_74 = dividendMSB_lo_11[1]; // @[CircuitMath.scala:28:8, :34:17]
wire [1:0] _dividendMSB_T_75 = _dividendMSB_T_73 ? 2'h2 : {1'h0, _dividendMSB_T_74}; // @[CircuitMath.scala:28:8, :30:{10,12}]
wire [1:0] _dividendMSB_T_76 = _dividendMSB_T_72 ? 2'h3 : _dividendMSB_T_75; // @[CircuitMath.scala:30:{10,12}]
wire [1:0] _dividendMSB_T_77 = dividendMSB_useHi_11 ? _dividendMSB_T_71 : _dividendMSB_T_76; // @[CircuitMath.scala:30:10, :35:22, :36:21]
wire [2:0] _dividendMSB_T_78 = {dividendMSB_useHi_11, _dividendMSB_T_77}; // @[CircuitMath.scala:35:22, :36:{10,21}]
wire [2:0] _dividendMSB_T_79 = dividendMSB_useHi_9 ? _dividendMSB_T_66 : _dividendMSB_T_78; // @[CircuitMath.scala:35:22, :36:{10,21}]
wire [3:0] _dividendMSB_T_80 = {dividendMSB_useHi_9, _dividendMSB_T_79}; // @[CircuitMath.scala:35:22, :36:{10,21}]
wire [7:0] dividendMSB_hi_12 = dividendMSB_lo_8[15:8]; // @[CircuitMath.scala:33:17, :34:17]
wire [7:0] dividendMSB_lo_12 = dividendMSB_lo_8[7:0]; // @[CircuitMath.scala:34:17]
wire dividendMSB_useHi_12 = |dividendMSB_hi_12; // @[CircuitMath.scala:33:17, :35:22]
wire [3:0] dividendMSB_hi_13 = dividendMSB_hi_12[7:4]; // @[CircuitMath.scala:33:17]
wire [3:0] dividendMSB_lo_13 = dividendMSB_hi_12[3:0]; // @[CircuitMath.scala:33:17, :34:17]
wire dividendMSB_useHi_13 = |dividendMSB_hi_13; // @[CircuitMath.scala:33:17, :35:22]
wire _dividendMSB_T_81 = dividendMSB_hi_13[3]; // @[CircuitMath.scala:30:12, :33:17]
wire _dividendMSB_T_82 = dividendMSB_hi_13[2]; // @[CircuitMath.scala:30:12, :33:17]
wire _dividendMSB_T_83 = dividendMSB_hi_13[1]; // @[CircuitMath.scala:28:8, :33:17]
wire [1:0] _dividendMSB_T_84 = _dividendMSB_T_82 ? 2'h2 : {1'h0, _dividendMSB_T_83}; // @[CircuitMath.scala:28:8, :30:{10,12}]
wire [1:0] _dividendMSB_T_85 = _dividendMSB_T_81 ? 2'h3 : _dividendMSB_T_84; // @[CircuitMath.scala:30:{10,12}]
wire _dividendMSB_T_86 = dividendMSB_lo_13[3]; // @[CircuitMath.scala:30:12, :34:17]
wire _dividendMSB_T_87 = dividendMSB_lo_13[2]; // @[CircuitMath.scala:30:12, :34:17]
wire _dividendMSB_T_88 = dividendMSB_lo_13[1]; // @[CircuitMath.scala:28:8, :34:17]
wire [1:0] _dividendMSB_T_89 = _dividendMSB_T_87 ? 2'h2 : {1'h0, _dividendMSB_T_88}; // @[CircuitMath.scala:28:8, :30:{10,12}]
wire [1:0] _dividendMSB_T_90 = _dividendMSB_T_86 ? 2'h3 : _dividendMSB_T_89; // @[CircuitMath.scala:30:{10,12}]
wire [1:0] _dividendMSB_T_91 = dividendMSB_useHi_13 ? _dividendMSB_T_85 : _dividendMSB_T_90; // @[CircuitMath.scala:30:10, :35:22, :36:21]
wire [2:0] _dividendMSB_T_92 = {dividendMSB_useHi_13, _dividendMSB_T_91}; // @[CircuitMath.scala:35:22, :36:{10,21}]
wire [3:0] dividendMSB_hi_14 = dividendMSB_lo_12[7:4]; // @[CircuitMath.scala:33:17, :34:17]
wire [3:0] dividendMSB_lo_14 = dividendMSB_lo_12[3:0]; // @[CircuitMath.scala:34:17]
wire dividendMSB_useHi_14 = |dividendMSB_hi_14; // @[CircuitMath.scala:33:17, :35:22]
wire _dividendMSB_T_93 = dividendMSB_hi_14[3]; // @[CircuitMath.scala:30:12, :33:17]
wire _dividendMSB_T_94 = dividendMSB_hi_14[2]; // @[CircuitMath.scala:30:12, :33:17]
wire _dividendMSB_T_95 = dividendMSB_hi_14[1]; // @[CircuitMath.scala:28:8, :33:17]
wire [1:0] _dividendMSB_T_96 = _dividendMSB_T_94 ? 2'h2 : {1'h0, _dividendMSB_T_95}; // @[CircuitMath.scala:28:8, :30:{10,12}]
wire [1:0] _dividendMSB_T_97 = _dividendMSB_T_93 ? 2'h3 : _dividendMSB_T_96; // @[CircuitMath.scala:30:{10,12}]
wire _dividendMSB_T_98 = dividendMSB_lo_14[3]; // @[CircuitMath.scala:30:12, :34:17]
wire _dividendMSB_T_99 = dividendMSB_lo_14[2]; // @[CircuitMath.scala:30:12, :34:17]
wire _dividendMSB_T_100 = dividendMSB_lo_14[1]; // @[CircuitMath.scala:28:8, :34:17]
wire [1:0] _dividendMSB_T_101 = _dividendMSB_T_99 ? 2'h2 : {1'h0, _dividendMSB_T_100}; // @[CircuitMath.scala:28:8, :30:{10,12}]
wire [1:0] _dividendMSB_T_102 = _dividendMSB_T_98 ? 2'h3 : _dividendMSB_T_101; // @[CircuitMath.scala:30:{10,12}]
wire [1:0] _dividendMSB_T_103 = dividendMSB_useHi_14 ? _dividendMSB_T_97 : _dividendMSB_T_102; // @[CircuitMath.scala:30:10, :35:22, :36:21]
wire [2:0] _dividendMSB_T_104 = {dividendMSB_useHi_14, _dividendMSB_T_103}; // @[CircuitMath.scala:35:22, :36:{10,21}]
wire [2:0] _dividendMSB_T_105 = dividendMSB_useHi_12 ? _dividendMSB_T_92 : _dividendMSB_T_104; // @[CircuitMath.scala:35:22, :36:{10,21}]
wire [3:0] _dividendMSB_T_106 = {dividendMSB_useHi_12, _dividendMSB_T_105}; // @[CircuitMath.scala:35:22, :36:{10,21}]
wire [3:0] _dividendMSB_T_107 = dividendMSB_useHi_8 ? _dividendMSB_T_80 : _dividendMSB_T_106; // @[CircuitMath.scala:35:22, :36:{10,21}]
wire [4:0] _dividendMSB_T_108 = {dividendMSB_useHi_8, _dividendMSB_T_107}; // @[CircuitMath.scala:35:22, :36:{10,21}]
wire [4:0] _dividendMSB_T_109 = dividendMSB_useHi ? _dividendMSB_T_54 : _dividendMSB_T_108; // @[CircuitMath.scala:35:22, :36:{10,21}]
wire [5:0] _dividendMSB_T_110 = {dividendMSB_useHi, _dividendMSB_T_109}; // @[CircuitMath.scala:35:22, :36:{10,21}]
wire [5:0] dividendMSB = _dividendMSB_T_110; // @[CircuitMath.scala:36:10]
wire [6:0] _eOutPos_T = {1'h0, dividendMSB} - {1'h0, divisorMSB}; // @[Multiplier.scala:150:48, :151:51, :152:35]
wire [5:0] _eOutPos_T_1 = _eOutPos_T[5:0]; // @[Multiplier.scala:152:35]
wire [5:0] eOutPos = ~_eOutPos_T_1; // @[Multiplier.scala:152:{21,35}]
wire [5:0] _count_T_4 = eOutPos; // @[Multiplier.scala:152:21, :156:26]
wire _eOut_T_9 = ~(|count); // @[Multiplier.scala:54:18, :117:83, :146:24, :153:24]
wire _eOut_T_10 = ~divby0; // @[Multiplier.scala:146:32, :153:35]
wire _eOut_T_11 = _eOut_T_9 & _eOut_T_10; // @[Multiplier.scala:153:{24,32,35}]
wire _eOut_T_12 = |eOutPos; // @[Multiplier.scala:152:21, :153:54]
wire eOut_1 = _eOut_T_11 & _eOut_T_12; // @[Multiplier.scala:153:{32,43,54}]
wire [126:0] _remainder_T_4 = {63'h0, _remainder_T_3} << eOutPos; // @[Multiplier.scala:152:21, :155:{31,39}]
wire _state_T_1 = lhs_sign | rhs_sign; // @[Multiplier.scala:81:23, :165:46]
wire [2:0] _state_T_2 = {1'h0, ~_state_T_1, 1'h1}; // @[Multiplier.scala:165:{36,46}]
wire [2:0] _state_T_3 = cmdMul ? 3'h2 : _state_T_2; // @[Multiplier.scala:75:107, :165:{17,36}]
wire _count_T_6 = _count_T_5; // @[Multiplier.scala:78:{50,60}]
wire _count_T_7 = cmdMul & _count_T_6; // @[Multiplier.scala:75:107, :78:50, :168:46]
wire [5:0] _count_T_8 = {_count_T_7, 5'h0}; // @[Multiplier.scala:168:{38,46}]
wire _neg_out_T = lhs_sign != rhs_sign; // @[Multiplier.scala:81:23, :169:46]
wire _neg_out_T_1 = cmdHi ? lhs_sign : _neg_out_T; // @[Multiplier.scala:75:107, :81:23, :169:{19,46}]
wire [64:0] _divisor_T = {rhs_sign, rhs_in}; // @[Multiplier.scala:81:23, :83:9, :170:19]
wire [2:0] _outMul_T_1 = state & 3'h1; // @[Multiplier.scala:51:22, :175:23]
wire outMul = _outMul_T_1 == 3'h0; // @[Multiplier.scala:175:{23,52}]
wire _loOut_T = ~req_dw; // @[Multiplier.scala:53:16, :78:60]
wire _loOut_T_1 = _loOut_T; // @[Multiplier.scala:78:{50,60}]
wire _loOut_T_2 = _loOut_T_1; // @[Multiplier.scala:78:50, :176:30]
wire _loOut_T_3 = _loOut_T_2 & outMul; // @[Multiplier.scala:175:52, :176:{30,48}]
wire [31:0] _loOut_T_4 = result[63:32]; // @[Multiplier.scala:89:19, :176:65]
wire [31:0] _hiOut_T_4 = result[63:32]; // @[Multiplier.scala:89:19, :176:65, :177:66]
wire [31:0] _loOut_T_5 = result[31:0]; // @[Multiplier.scala:89:19, :176:82]
wire [31:0] loOut = _loOut_T_3 ? _loOut_T_4 : _loOut_T_5; // @[Multiplier.scala:176:{18,48,65,82}]
wire _hiOut_T = ~req_dw; // @[Multiplier.scala:53:16, :78:60]
wire _hiOut_T_1 = _hiOut_T; // @[Multiplier.scala:78:{50,60}]
wire _hiOut_T_2 = loOut[31]; // @[Multiplier.scala:176:18, :177:50]
wire [31:0] _hiOut_T_3 = {32{_hiOut_T_2}}; // @[Multiplier.scala:177:{39,50}]
wire [31:0] hiOut = _hiOut_T_1 ? _hiOut_T_3 : _hiOut_T_4; // @[Multiplier.scala:78:50, :177:{18,39,66}]
assign _io_resp_bits_data_T = {hiOut, loOut}; // @[Multiplier.scala:176:18, :177:18, :180:27]
assign io_resp_bits_data_0 = _io_resp_bits_data_T; // @[Multiplier.scala:40:7, :180:27]
assign _io_resp_bits_full_data_T_2 = {_io_resp_bits_full_data_T, _io_resp_bits_full_data_T_1}; // @[Multiplier.scala:181:{32,42,63}]
assign io_resp_bits_full_data = _io_resp_bits_full_data_T_2; // @[Multiplier.scala:40:7, :181:32]
wire _io_resp_valid_T = state == 3'h6; // @[Multiplier.scala:51:22, :182:27]
wire _io_resp_valid_T_1 = &state; // @[Multiplier.scala:51:22, :182:51]
assign _io_resp_valid_T_2 = _io_resp_valid_T | _io_resp_valid_T_1; // @[Multiplier.scala:182:{27,42,51}]
assign io_resp_valid_0 = _io_resp_valid_T_2; // @[Multiplier.scala:40:7, :182:42]
assign _io_req_ready_T = state == 3'h0; // @[Multiplier.scala:51:22, :183:25]
assign io_req_ready_0 = _io_req_ready_T; // @[Multiplier.scala:40:7, :183:25]
wire _T_10 = state == 3'h1; // @[Multiplier.scala:51:22, :92:39]
wire _T_13 = state == 3'h5; // @[Multiplier.scala:51:22, :101:39]
wire _T_14 = state == 3'h2; // @[Multiplier.scala:51:22, :106:39]
wire _GEN_1 = _T_14 & count == 7'h3F; // @[Multiplier.scala:54:18, :101:57, :106:{39,50}, :124:{25,55}, :125:13]
wire _T_17 = state == 3'h3; // @[Multiplier.scala:51:22, :129:39]
wire _T_18 = count == 7'h40; // @[Multiplier.scala:54:18, :138:17]
wire _T_23 = io_req_ready_0 & io_req_valid_0; // @[Decoupled.scala:51:35]
always @(posedge clock) begin // @[Multiplier.scala:40:7]
if (reset) // @[Multiplier.scala:40:7]
state <= 3'h0; // @[Multiplier.scala:51:22]
else if (_T_23) // @[Decoupled.scala:51:35]
state <= _state_T_3; // @[Multiplier.scala:51:22, :165:17]
else if (io_resp_ready_0 & io_resp_valid_0 | io_kill_0) // @[Decoupled.scala:51:35]
state <= 3'h0; // @[Multiplier.scala:51:22]
else if (_T_17 & _T_18) // @[Multiplier.scala:106:50, :129:{39,50}, :138:{17,42}, :139:13]
state <= _state_T; // @[Multiplier.scala:51:22, :139:19]
else if (_GEN_1) // @[Multiplier.scala:101:57, :106:50, :124:55, :125:13]
state <= 3'h6; // @[Multiplier.scala:51:22]
else if (_T_13) // @[Multiplier.scala:101:39]
state <= 3'h7; // @[Multiplier.scala:51:22]
else if (_T_10) // @[Multiplier.scala:92:39]
state <= 3'h3; // @[Multiplier.scala:51:22]
if (_T_23) begin // @[Decoupled.scala:51:35]
req_fn <= io_req_bits_fn_0; // @[Multiplier.scala:40:7, :53:16]
req_dw <= io_req_bits_dw_0; // @[Multiplier.scala:40:7, :53:16]
req_in1 <= io_req_bits_in1_0; // @[Multiplier.scala:40:7, :53:16]
req_in2 <= io_req_bits_in2_0; // @[Multiplier.scala:40:7, :53:16]
count <= {1'h0, _count_T_8}; // @[Multiplier.scala:54:18, :168:{11,38}]
isHi <= cmdHi; // @[Multiplier.scala:58:17, :75:107]
divisor <= _divisor_T; // @[Multiplier.scala:60:20, :170:19]
remainder <= {66'h0, lhs_in}; // @[Multiplier.scala:61:22, :83:9, :94:17, :171:15]
end
else begin // @[Decoupled.scala:51:35]
if (_T_17) begin // @[Multiplier.scala:129:39]
count <= eOut_1 ? {1'h0, _count_T_4} : _count_T_3; // @[Multiplier.scala:54:18, :144:{11,20}, :153:43, :154:19, :156:{15,26}]
remainder <= eOut_1 ? {3'h0, _remainder_T_4} : {1'h0, unrolls_0}; // @[Multiplier.scala:61:22, :134:10, :137:15, :153:43, :154:19, :155:{19,39}]
end
else if (_T_14) begin // @[Multiplier.scala:106:39]
count <= _count_T_1; // @[Multiplier.scala:54:18, :123:20]
remainder <= _remainder_T_2; // @[Multiplier.scala:61:22, :121:21]
end
else if (_T_13 | _T_10 & remainder[63]) // @[Multiplier.scala:61:22, :92:{39,57}, :93:{20,27}, :94:17, :101:{39,57}, :102:15]
remainder <= {66'h0, negated_remainder}; // @[Multiplier.scala:61:22, :90:27, :94:17]
if (_T_10 & divisor[63]) // @[Multiplier.scala:60:20, :92:{39,57}, :96:{18,25}, :97:15]
divisor <= subtractor; // @[Multiplier.scala:60:20, :88:37]
end
neg_out <= _T_23 ? _neg_out_T_1 : ~(_T_17 & divby0 & ~isHi) & neg_out; // @[Decoupled.scala:51:35]
resHi <= ~_T_23 & (_T_17 & _T_18 | _GEN_1 ? isHi : ~_T_13 & resHi); // @[Decoupled.scala:51:35]
always @(posedge)
assign io_req_ready = io_req_ready_0; // @[Multiplier.scala:40:7]
assign io_resp_valid = io_resp_valid_0; // @[Multiplier.scala:40:7]
assign io_resp_bits_data = io_resp_bits_data_0; // @[Multiplier.scala:40:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File util.scala:
//******************************************************************************
// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Utility Functions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v4.util
import chisel3._
import chisel3.util._
import freechips.rocketchip.rocket.Instructions._
import freechips.rocketchip.rocket._
import freechips.rocketchip.util.{Str}
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.tile.{TileKey}
import boom.v4.common.{MicroOp}
import boom.v4.exu.{BrUpdateInfo}
/**
* Object to XOR fold a input register of fullLength into a compressedLength.
*/
object Fold
{
def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = {
val clen = compressedLength
val hlen = fullLength
if (hlen <= clen) {
input
} else {
var res = 0.U(clen.W)
var remaining = input.asUInt
for (i <- 0 to hlen-1 by clen) {
val len = if (i + clen > hlen ) (hlen - i) else clen
require(len > 0)
res = res(clen-1,0) ^ remaining(len-1,0)
remaining = remaining >> len.U
}
res
}
}
}
/**
* Object to check if MicroOp was killed due to a branch mispredict.
* Uses "Fast" branch masks
*/
object IsKilledByBranch
{
def apply(brupdate: BrUpdateInfo, flush: Bool, uop: MicroOp): Bool = {
return apply(brupdate, flush, uop.br_mask)
}
def apply(brupdate: BrUpdateInfo, flush: Bool, uop_mask: UInt): Bool = {
return maskMatch(brupdate.b1.mispredict_mask, uop_mask) || flush
}
def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: T): Bool = {
return apply(brupdate, flush, bundle.uop)
}
def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Bool = {
return apply(brupdate, flush, bundle.bits)
}
}
/**
* Object to return new MicroOp with a new BR mask given a MicroOp mask
* and old BR mask.
*/
object GetNewUopAndBrMask
{
def apply(uop: MicroOp, brupdate: BrUpdateInfo)
(implicit p: Parameters): MicroOp = {
val newuop = WireInit(uop)
newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask
newuop
}
}
/**
* Object to return a BR mask given a MicroOp mask and old BR mask.
*/
object GetNewBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = {
return uop.br_mask & ~brupdate.b1.resolve_mask
}
def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = {
return br_mask & ~brupdate.b1.resolve_mask
}
}
object UpdateBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = {
val out = WireInit(uop)
out.br_mask := GetNewBrMask(brupdate, uop)
out
}
def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = {
val out = WireInit(bundle)
out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask)
out
}
def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Valid[T] = {
val out = WireInit(bundle)
out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask)
out.valid := bundle.valid && !IsKilledByBranch(brupdate, flush, bundle.bits.uop.br_mask)
out
}
}
/**
* Object to check if at least 1 bit matches in two masks
*/
object maskMatch
{
def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U
}
/**
* Object to clear one bit in a mask given an index
*/
object clearMaskBit
{
def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0)
}
/**
* Object to shift a register over by one bit and concat a new one
*/
object PerformShiftRegister
{
def apply(reg_val: UInt, new_bit: Bool): UInt = {
reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt
reg_val
}
}
/**
* Object to shift a register over by one bit, wrapping the top bit around to the bottom
* (XOR'ed with a new-bit), and evicting a bit at index HLEN.
* This is used to simulate a longer HLEN-width shift register that is folded
* down to a compressed CLEN.
*/
object PerformCircularShiftRegister
{
def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = {
val carry = csr(clen-1)
val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U)
newval
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapAdd
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, amt: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + amt)(log2Ceil(n)-1,0)
} else {
val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt)
Mux(sum >= n.U,
sum - n.U,
sum)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapSub
{
// "n" is the number of increments, so we wrap to n-1.
def apply(value: UInt, amt: Int, n: Int): UInt = {
if (isPow2(n)) {
(value - amt.U)(log2Ceil(n)-1,0)
} else {
val v = Cat(0.U(1.W), value)
val b = Cat(0.U(1.W), amt.U)
Mux(value >= amt.U,
value - amt.U,
n.U - amt.U + value)
}
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapInc
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === (n-1).U)
Mux(wrap, 0.U, value + 1.U)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapDec
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value - 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === 0.U)
Mux(wrap, (n-1).U, value - 1.U)
}
}
}
/**
* Object to mask off lower bits of a PC to align to a "b"
* Byte boundary.
*/
object AlignPCToBoundary
{
def apply(pc: UInt, b: Int): UInt = {
// Invert for scenario where pc longer than b
// (which would clear all bits above size(b)).
~(~pc | (b-1).U)
}
}
/**
* Object to rotate a signal left by one
*/
object RotateL1
{
def apply(signal: UInt): UInt = {
val w = signal.getWidth
val out = Cat(signal(w-2,0), signal(w-1))
return out
}
}
/**
* Object to sext a value to a particular length.
*/
object Sext
{
def apply(x: UInt, length: Int): UInt = {
if (x.getWidth == length) return x
else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x)
}
}
/**
* Object to translate from BOOM's special "packed immediate" to a 32b signed immediate
* Asking for U-type gives it shifted up 12 bits.
*/
object ImmGen
{
import boom.v4.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U, IS_N}
def apply(i: UInt, isel: UInt): UInt = {
val ip = Mux(isel === IS_N, 0.U(LONGEST_IMM_SZ.W), i)
val sign = ip(LONGEST_IMM_SZ-1).asSInt
val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign)
val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign)
val i11 = Mux(isel === IS_U, 0.S,
Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign))
val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt)
val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt)
val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S)
return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0)
}
}
/**
* Object to see if an instruction is a JALR.
*/
object DebugIsJALR
{
def apply(inst: UInt): Bool = {
// TODO Chisel not sure why this won't compile
// val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)),
// Array(
// JALR -> Bool(true)))
inst(6,0) === "b1100111".U
}
}
/**
* Object to take an instruction and output its branch or jal target. Only used
* for a debug assert (no where else would we jump straight from instruction
* bits to a target).
*/
object DebugGetBJImm
{
def apply(inst: UInt): UInt = {
// TODO Chisel not sure why this won't compile
//val csignals =
//rocket.DecodeLogic(inst,
// List(Bool(false), Bool(false)),
// Array(
// BEQ -> List(Bool(true ), Bool(false)),
// BNE -> List(Bool(true ), Bool(false)),
// BGE -> List(Bool(true ), Bool(false)),
// BGEU -> List(Bool(true ), Bool(false)),
// BLT -> List(Bool(true ), Bool(false)),
// BLTU -> List(Bool(true ), Bool(false))
// ))
//val is_br :: nothing :: Nil = csignals
val is_br = (inst(6,0) === "b1100011".U)
val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W))
val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W))
Mux(is_br, br_targ, jal_targ)
}
}
/**
* Object to return the lowest bit position after the head.
*/
object AgePriorityEncoder
{
def apply(in: Seq[Bool], head: UInt): UInt = {
val n = in.size
val width = log2Ceil(in.size)
val n_padded = 1 << width
val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in
val idx = PriorityEncoder(temp_vec)
idx(width-1, 0) //discard msb
}
}
/**
* Object to determine whether queue
* index i0 is older than index i1.
*/
object IsOlder
{
def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head))
}
object IsYoungerMask
{
def apply(i: UInt, head: UInt, n: Integer): UInt = {
val hi_mask = ~MaskLower(UIntToOH(i)(n-1,0))
val lo_mask = ~MaskUpper(UIntToOH(head)(n-1,0))
Mux(i < head, hi_mask & lo_mask, hi_mask | lo_mask)(n-1,0)
}
}
/**
* Set all bits at or below the highest order '1'.
*/
object MaskLower
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => in >> i.U).reduce(_|_)
}
}
/**
* Set all bits at or above the lowest order '1'.
*/
object MaskUpper
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_)
}
}
/**
* Transpose a matrix of Chisel Vecs.
*/
object Transpose
{
def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = {
val n = in(0).size
VecInit((0 until n).map(i => VecInit(in.map(row => row(i)))))
}
}
/**
* N-wide one-hot priority encoder.
*/
object SelectFirstN
{
def apply(in: UInt, n: Int) = {
val sels = Wire(Vec(n, UInt(in.getWidth.W)))
var mask = in
for (i <- 0 until n) {
sels(i) := PriorityEncoderOH(mask)
mask = mask & ~sels(i)
}
sels
}
}
/**
* Connect the first k of n valid input interfaces to k output interfaces.
*/
class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module
{
require(n >= k)
val io = IO(new Bundle {
val in = Vec(n, Flipped(DecoupledIO(gen)))
val out = Vec(k, DecoupledIO(gen))
})
if (n == k) {
io.out <> io.in
} else {
val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c))
val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col =>
(col zip io.in.map(_.valid)) map {case (c,v) => c && v})
val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_))
val out_valids = sels map (col => col.reduce(_||_))
val out_data = sels map (s => Mux1H(s, io.in.map(_.bits)))
in_readys zip io.in foreach {case (r,i) => i.ready := r}
out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d}
}
}
/**
* Create a queue that can be killed with a branch kill signal.
* Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq).
*/
class BranchKillableQueue[T <: boom.v4.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v4.common.MicroOp => Bool = u => true.B, fastDeq: Boolean = false)
(implicit p: org.chipsalliance.cde.config.Parameters)
extends boom.v4.common.BoomModule()(p)
with boom.v4.common.HasBoomCoreParameters
{
val io = IO(new Bundle {
val enq = Flipped(Decoupled(gen))
val deq = Decoupled(gen)
val brupdate = Input(new BrUpdateInfo())
val flush = Input(Bool())
val empty = Output(Bool())
val count = Output(UInt(log2Ceil(entries).W))
})
if (fastDeq && entries > 1) {
// Pipeline dequeue selection so the mux gets an entire cycle
val main = Module(new BranchKillableQueue(gen, entries-1, flush_fn, false))
val out_reg = Reg(gen)
val out_valid = RegInit(false.B)
val out_uop = Reg(new MicroOp)
main.io.enq <> io.enq
main.io.brupdate := io.brupdate
main.io.flush := io.flush
io.empty := main.io.empty && !out_valid
io.count := main.io.count + out_valid
io.deq.valid := out_valid
io.deq.bits := out_reg
io.deq.bits.uop := out_uop
out_uop := UpdateBrMask(io.brupdate, out_uop)
out_valid := out_valid && !IsKilledByBranch(io.brupdate, false.B, out_uop) && !(io.flush && flush_fn(out_uop))
main.io.deq.ready := false.B
when (io.deq.fire || !out_valid) {
out_valid := main.io.deq.valid && !IsKilledByBranch(io.brupdate, false.B, main.io.deq.bits.uop) && !(io.flush && flush_fn(main.io.deq.bits.uop))
out_reg := main.io.deq.bits
out_uop := UpdateBrMask(io.brupdate, main.io.deq.bits.uop)
main.io.deq.ready := true.B
}
} else {
val ram = Mem(entries, gen)
val valids = RegInit(VecInit(Seq.fill(entries) {false.B}))
val uops = Reg(Vec(entries, new MicroOp))
val enq_ptr = Counter(entries)
val deq_ptr = Counter(entries)
val maybe_full = RegInit(false.B)
val ptr_match = enq_ptr.value === deq_ptr.value
io.empty := ptr_match && !maybe_full
val full = ptr_match && maybe_full
val do_enq = WireInit(io.enq.fire && !IsKilledByBranch(io.brupdate, false.B, io.enq.bits.uop) && !(io.flush && flush_fn(io.enq.bits.uop)))
val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty)
for (i <- 0 until entries) {
val mask = uops(i).br_mask
val uop = uops(i)
valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, false.B, mask) && !(io.flush && flush_fn(uop))
when (valids(i)) {
uops(i).br_mask := GetNewBrMask(io.brupdate, mask)
}
}
when (do_enq) {
ram(enq_ptr.value) := io.enq.bits
valids(enq_ptr.value) := true.B
uops(enq_ptr.value) := io.enq.bits.uop
uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)
enq_ptr.inc()
}
when (do_deq) {
valids(deq_ptr.value) := false.B
deq_ptr.inc()
}
when (do_enq =/= do_deq) {
maybe_full := do_enq
}
io.enq.ready := !full
val out = Wire(gen)
out := ram(deq_ptr.value)
out.uop := uops(deq_ptr.value)
io.deq.valid := !io.empty && valids(deq_ptr.value)
io.deq.bits := out
val ptr_diff = enq_ptr.value - deq_ptr.value
if (isPow2(entries)) {
io.count := Cat(maybe_full && ptr_match, ptr_diff)
}
else {
io.count := Mux(ptr_match,
Mux(maybe_full,
entries.asUInt, 0.U),
Mux(deq_ptr.value > enq_ptr.value,
entries.asUInt + ptr_diff, ptr_diff))
}
}
}
// ------------------------------------------
// Printf helper functions
// ------------------------------------------
object BoolToChar
{
/**
* Take in a Chisel Bool and convert it into a Str
* based on the Chars given
*
* @param c_bool Chisel Bool
* @param trueChar Scala Char if bool is true
* @param falseChar Scala Char if bool is false
* @return UInt ASCII Char for "trueChar" or "falseChar"
*/
def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = {
Mux(c_bool, Str(trueChar), Str(falseChar))
}
}
object CfiTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param cfi_type specific cfi type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(cfi_type: UInt) = {
val strings = Seq("----", "BR ", "JAL ", "JALR")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(cfi_type)
}
}
object BpdTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param bpd_type specific bpd type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(bpd_type: UInt) = {
val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(bpd_type)
}
}
object RobTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param rob_type specific rob type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(rob_type: UInt) = {
val strings = Seq("RST", "NML", "RBK", " WT")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(rob_type)
}
}
object XRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param xreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(xreg: UInt) = {
val strings = Seq(" x0", " ra", " sp", " gp",
" tp", " t0", " t1", " t2",
" s0", " s1", " a0", " a1",
" a2", " a3", " a4", " a5",
" a6", " a7", " s2", " s3",
" s4", " s5", " s6", " s7",
" s8", " s9", "s10", "s11",
" t3", " t4", " t5", " t6")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(xreg)
}
}
object FPRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param fpreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(fpreg: UInt) = {
val strings = Seq(" ft0", " ft1", " ft2", " ft3",
" ft4", " ft5", " ft6", " ft7",
" fs0", " fs1", " fa0", " fa1",
" fa2", " fa3", " fa4", " fa5",
" fa6", " fa7", " fs2", " fs3",
" fs4", " fs5", " fs6", " fs7",
" fs8", " fs9", "fs10", "fs11",
" ft8", " ft9", "ft10", "ft11")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(fpreg)
}
}
object BoomCoreStringPrefix
{
/**
* Add prefix to BOOM strings (currently only adds the hartId)
*
* @param strs list of strings
* @return String combining the list with the prefix per line
*/
def apply(strs: String*)(implicit p: Parameters) = {
val prefix = "[C" + s"${p(TileKey).tileId}" + "] "
strs.map(str => prefix + str + "\n").mkString("")
}
}
class BranchKillablePipeline[T <: boom.v4.common.HasBoomUOP](gen: T, stages: Int)
(implicit p: org.chipsalliance.cde.config.Parameters)
extends boom.v4.common.BoomModule()(p)
with boom.v4.common.HasBoomCoreParameters
{
val io = IO(new Bundle {
val req = Input(Valid(gen))
val flush = Input(Bool())
val brupdate = Input(new BrUpdateInfo)
val resp = Output(Vec(stages, Valid(gen)))
})
require(stages > 0)
val uops = Reg(Vec(stages, Valid(gen)))
uops(0).valid := io.req.valid && !IsKilledByBranch(io.brupdate, io.flush, io.req.bits)
uops(0).bits := UpdateBrMask(io.brupdate, io.req.bits)
for (i <- 1 until stages) {
uops(i).valid := uops(i-1).valid && !IsKilledByBranch(io.brupdate, io.flush, uops(i-1).bits)
uops(i).bits := UpdateBrMask(io.brupdate, uops(i-1).bits)
}
for (i <- 0 until stages) { when (reset.asBool) { uops(i).valid := false.B } }
io.resp := uops
}
File issue-slot.scala:
//******************************************************************************
// Copyright (c) 2015 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// RISCV Processor Issue Slot Logic
//--------------------------------------------------------------------------
//------------------------------------------------------------------------------
//
// Note: stores (and AMOs) are "broken down" into 2 uops, but stored within a single issue-slot.
// TODO XXX make a separate issueSlot for MemoryIssueSlots, and only they break apart stores.
// TODO Disable ldspec for FP queue.
package boom.v4.exu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import boom.v4.common._
import boom.v4.util._
class IssueSlotIO(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomBundle
{
val valid = Output(Bool())
val will_be_valid = Output(Bool()) // TODO code review, do we need this signal so explicitely?
val request = Output(Bool())
val grant = Input(Bool())
val iss_uop = Output(new MicroOp())
val in_uop = Input(Valid(new MicroOp())) // if valid, this WILL overwrite an entry!
val out_uop = Output(new MicroOp())
val brupdate = Input(new BrUpdateInfo())
val kill = Input(Bool()) // pipeline flush
val clear = Input(Bool()) // entry being moved elsewhere (not mutually exclusive with grant)
val squash_grant = Input(Bool())
val wakeup_ports = Flipped(Vec(numWakeupPorts, Valid(new Wakeup)))
val pred_wakeup_port = Flipped(Valid(UInt(log2Ceil(ftqSz).W)))
val child_rebusys = Input(UInt(aluWidth.W))
}
class IssueSlot(val numWakeupPorts: Int, val isMem: Boolean, val isFp: Boolean)(implicit p: Parameters)
extends BoomModule
{
val io = IO(new IssueSlotIO(numWakeupPorts))
val slot_valid = RegInit(false.B)
val slot_uop = Reg(new MicroOp())
val next_valid = WireInit(slot_valid)
val next_uop = WireInit(UpdateBrMask(io.brupdate, slot_uop))
val killed = IsKilledByBranch(io.brupdate, io.kill, slot_uop)
io.valid := slot_valid
io.out_uop := next_uop
io.will_be_valid := next_valid && !killed
when (io.kill) {
slot_valid := false.B
} .elsewhen (io.in_uop.valid) {
slot_valid := true.B
} .elsewhen (io.clear) {
slot_valid := false.B
} .otherwise {
slot_valid := next_valid && !killed
}
when (io.in_uop.valid) {
slot_uop := io.in_uop.bits
assert (!slot_valid || io.clear || io.kill)
} .otherwise {
slot_uop := next_uop
}
// Wakeups
next_uop.iw_p1_bypass_hint := false.B
next_uop.iw_p2_bypass_hint := false.B
next_uop.iw_p3_bypass_hint := false.B
next_uop.iw_p1_speculative_child := 0.U
next_uop.iw_p2_speculative_child := 0.U
val rebusied_prs1 = WireInit(false.B)
val rebusied_prs2 = WireInit(false.B)
val rebusied = rebusied_prs1 || rebusied_prs2
val prs1_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs1 }
val prs2_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs2 }
val prs3_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs3 }
val prs1_wakeups = (io.wakeup_ports zip prs1_matches).map { case (w,m) => w.valid && m }
val prs2_wakeups = (io.wakeup_ports zip prs2_matches).map { case (w,m) => w.valid && m }
val prs3_wakeups = (io.wakeup_ports zip prs3_matches).map { case (w,m) => w.valid && m }
val prs1_rebusys = (io.wakeup_ports zip prs1_matches).map { case (w,m) => w.bits.rebusy && m }
val prs2_rebusys = (io.wakeup_ports zip prs2_matches).map { case (w,m) => w.bits.rebusy && m }
val bypassables = io.wakeup_ports.map { w => w.bits.bypassable }
val speculative_masks = io.wakeup_ports.map { w => w.bits.speculative_mask }
when (prs1_wakeups.reduce(_||_)) {
next_uop.prs1_busy := false.B
next_uop.iw_p1_speculative_child := Mux1H(prs1_wakeups, speculative_masks)
next_uop.iw_p1_bypass_hint := Mux1H(prs1_wakeups, bypassables)
}
when ((prs1_rebusys.reduce(_||_) || ((io.child_rebusys & slot_uop.iw_p1_speculative_child) =/= 0.U)) &&
slot_uop.lrs1_rtype === RT_FIX) {
next_uop.prs1_busy := true.B
rebusied_prs1 := true.B
}
when (prs2_wakeups.reduce(_||_)) {
next_uop.prs2_busy := false.B
next_uop.iw_p2_speculative_child := Mux1H(prs2_wakeups, speculative_masks)
next_uop.iw_p2_bypass_hint := Mux1H(prs2_wakeups, bypassables)
}
when ((prs2_rebusys.reduce(_||_) || ((io.child_rebusys & slot_uop.iw_p2_speculative_child) =/= 0.U)) &&
slot_uop.lrs2_rtype === RT_FIX) {
next_uop.prs2_busy := true.B
rebusied_prs2 := true.B
}
when (prs3_wakeups.reduce(_||_)) {
next_uop.prs3_busy := false.B
next_uop.iw_p3_bypass_hint := Mux1H(prs3_wakeups, bypassables)
}
when (io.pred_wakeup_port.valid && io.pred_wakeup_port.bits === slot_uop.ppred) {
next_uop.ppred_busy := false.B
}
val iss_ready = !slot_uop.prs1_busy && !slot_uop.prs2_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && !(slot_uop.prs3_busy && isFp.B)
val agen_ready = (slot_uop.fu_code(FC_AGEN) && !slot_uop.prs1_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && isMem.B)
val dgen_ready = (slot_uop.fu_code(FC_DGEN) && !slot_uop.prs2_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && isMem.B)
io.request := slot_valid && !slot_uop.iw_issued && (
iss_ready || agen_ready || dgen_ready
)
io.iss_uop := slot_uop
// Update state for current micro-op based on grant
next_uop.iw_issued := false.B
next_uop.iw_issued_partial_agen := false.B
next_uop.iw_issued_partial_dgen := false.B
when (io.grant && !io.squash_grant) {
next_uop.iw_issued := true.B
}
if (isMem) {
when (slot_uop.fu_code(FC_AGEN) && slot_uop.fu_code(FC_DGEN)) {
when (agen_ready) {
// Issue the AGEN, next slot entry is a DGEN
when (io.grant && !io.squash_grant) {
next_uop.iw_issued_partial_agen := true.B
}
io.iss_uop.fu_code(FC_AGEN) := true.B
io.iss_uop.fu_code(FC_DGEN) := false.B
} .otherwise {
// Issue the DGEN, next slot entry is the AGEN
when (io.grant && !io.squash_grant) {
next_uop.iw_issued_partial_dgen := true.B
}
io.iss_uop.fu_code(FC_AGEN) := false.B
io.iss_uop.fu_code(FC_DGEN) := true.B
io.iss_uop.imm_sel := IS_N
io.iss_uop.prs1 := slot_uop.prs2
io.iss_uop.lrs1_rtype := slot_uop.lrs2_rtype
io.iss_uop.iw_p1_bypass_hint := slot_uop.iw_p2_bypass_hint
}
} .elsewhen (slot_uop.fu_code(FC_DGEN)) {
io.iss_uop.imm_sel := IS_N
io.iss_uop.prs1 := slot_uop.prs2
io.iss_uop.lrs1_rtype := slot_uop.lrs2_rtype
io.iss_uop.iw_p1_bypass_hint := slot_uop.iw_p2_bypass_hint
}
io.iss_uop.lrs2_rtype := RT_X
io.iss_uop.prs2 := io.iss_uop.prs1 // helps with DCE
}
when (slot_valid && slot_uop.iw_issued) {
next_valid := rebusied
if (isMem) {
when (slot_uop.iw_issued_partial_agen) {
next_valid := true.B
when (!rebusied_prs1) {
next_uop.fu_code(FC_AGEN) := false.B
next_uop.fu_code(FC_DGEN) := true.B
}
} .elsewhen (slot_uop.iw_issued_partial_dgen) {
next_valid := true.B
when (!rebusied_prs2) {
next_uop.fu_code(FC_AGEN) := true.B
next_uop.fu_code(FC_DGEN) := false.B
}
}
}
}
}
| module IssueSlot_76( // @[issue-slot.scala:49:7]
input clock, // @[issue-slot.scala:49:7]
input reset, // @[issue-slot.scala:49:7]
output io_valid, // @[issue-slot.scala:52:14]
output io_will_be_valid, // @[issue-slot.scala:52:14]
output io_request, // @[issue-slot.scala:52:14]
input io_grant, // @[issue-slot.scala:52:14]
output [31:0] io_iss_uop_inst, // @[issue-slot.scala:52:14]
output [31:0] io_iss_uop_debug_inst, // @[issue-slot.scala:52:14]
output io_iss_uop_is_rvc, // @[issue-slot.scala:52:14]
output [39:0] io_iss_uop_debug_pc, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_0, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_1, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_2, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_3, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_0, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_1, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_2, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_3, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_4, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_5, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_6, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_7, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_8, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_9, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_issued, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_dis_col_sel, // @[issue-slot.scala:52:14]
output [15:0] io_iss_uop_br_mask, // @[issue-slot.scala:52:14]
output [3:0] io_iss_uop_br_tag, // @[issue-slot.scala:52:14]
output [3:0] io_iss_uop_br_type, // @[issue-slot.scala:52:14]
output io_iss_uop_is_sfb, // @[issue-slot.scala:52:14]
output io_iss_uop_is_fence, // @[issue-slot.scala:52:14]
output io_iss_uop_is_fencei, // @[issue-slot.scala:52:14]
output io_iss_uop_is_sfence, // @[issue-slot.scala:52:14]
output io_iss_uop_is_amo, // @[issue-slot.scala:52:14]
output io_iss_uop_is_eret, // @[issue-slot.scala:52:14]
output io_iss_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
output io_iss_uop_is_rocc, // @[issue-slot.scala:52:14]
output io_iss_uop_is_mov, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_ftq_idx, // @[issue-slot.scala:52:14]
output io_iss_uop_edge_inst, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_pc_lob, // @[issue-slot.scala:52:14]
output io_iss_uop_taken, // @[issue-slot.scala:52:14]
output io_iss_uop_imm_rename, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_imm_sel, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_pimm, // @[issue-slot.scala:52:14]
output [19:0] io_iss_uop_imm_packed, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_op1_sel, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_op2_sel, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_rob_idx, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_ldq_idx, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_stq_idx, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_rxq_idx, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_pdst, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_prs1, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_prs2, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_prs3, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_ppred, // @[issue-slot.scala:52:14]
output io_iss_uop_prs1_busy, // @[issue-slot.scala:52:14]
output io_iss_uop_prs2_busy, // @[issue-slot.scala:52:14]
output io_iss_uop_prs3_busy, // @[issue-slot.scala:52:14]
output io_iss_uop_ppred_busy, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_stale_pdst, // @[issue-slot.scala:52:14]
output io_iss_uop_exception, // @[issue-slot.scala:52:14]
output [63:0] io_iss_uop_exc_cause, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_mem_cmd, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_mem_size, // @[issue-slot.scala:52:14]
output io_iss_uop_mem_signed, // @[issue-slot.scala:52:14]
output io_iss_uop_uses_ldq, // @[issue-slot.scala:52:14]
output io_iss_uop_uses_stq, // @[issue-slot.scala:52:14]
output io_iss_uop_is_unique, // @[issue-slot.scala:52:14]
output io_iss_uop_flush_on_commit, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_csr_cmd, // @[issue-slot.scala:52:14]
output io_iss_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_ldst, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_lrs1, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_lrs2, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_lrs3, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_dst_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
output io_iss_uop_frs3_en, // @[issue-slot.scala:52:14]
output io_iss_uop_fcn_dw, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_fcn_op, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_val, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_fp_rm, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_fp_typ, // @[issue-slot.scala:52:14]
output io_iss_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
output io_iss_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
output io_iss_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
output io_iss_uop_bp_debug_if, // @[issue-slot.scala:52:14]
output io_iss_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_debug_fsrc, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_in_uop_valid, // @[issue-slot.scala:52:14]
input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:52:14]
input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_0, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_1, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_2, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_3, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_0, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_1, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_2, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_3, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_4, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_5, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_6, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_7, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_8, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_9, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_issued, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_in_uop_bits_br_type, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_sfb, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_fence, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_fencei, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_sfence, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_amo, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_eret, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_rocc, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:52:14]
input io_in_uop_bits_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:52:14]
input io_in_uop_bits_taken, // @[issue-slot.scala:52:14]
input io_in_uop_bits_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_op2_sel, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:52:14]
input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:52:14]
input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:52:14]
input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:52:14]
input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:52:14]
input io_in_uop_bits_exception, // @[issue-slot.scala:52:14]
input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:52:14]
input io_in_uop_bits_mem_signed, // @[issue-slot.scala:52:14]
input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:52:14]
input io_in_uop_bits_uses_stq, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_unique, // @[issue-slot.scala:52:14]
input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_csr_cmd, // @[issue-slot.scala:52:14]
input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_in_uop_bits_frs3_en, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_fcn_op, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_fp_typ, // @[issue-slot.scala:52:14]
input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:52:14]
output [31:0] io_out_uop_inst, // @[issue-slot.scala:52:14]
output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:52:14]
output io_out_uop_is_rvc, // @[issue-slot.scala:52:14]
output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_0, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_1, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_2, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_3, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_0, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_1, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_2, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_3, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_4, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_5, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_6, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_7, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_8, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_9, // @[issue-slot.scala:52:14]
output io_out_uop_iw_issued, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
output io_out_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
output io_out_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
output io_out_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_dis_col_sel, // @[issue-slot.scala:52:14]
output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:52:14]
output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:52:14]
output [3:0] io_out_uop_br_type, // @[issue-slot.scala:52:14]
output io_out_uop_is_sfb, // @[issue-slot.scala:52:14]
output io_out_uop_is_fence, // @[issue-slot.scala:52:14]
output io_out_uop_is_fencei, // @[issue-slot.scala:52:14]
output io_out_uop_is_sfence, // @[issue-slot.scala:52:14]
output io_out_uop_is_amo, // @[issue-slot.scala:52:14]
output io_out_uop_is_eret, // @[issue-slot.scala:52:14]
output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
output io_out_uop_is_rocc, // @[issue-slot.scala:52:14]
output io_out_uop_is_mov, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:52:14]
output io_out_uop_edge_inst, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:52:14]
output io_out_uop_taken, // @[issue-slot.scala:52:14]
output io_out_uop_imm_rename, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_imm_sel, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_pimm, // @[issue-slot.scala:52:14]
output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_op1_sel, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_op2_sel, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_pdst, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_prs1, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_prs2, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_prs3, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_ppred, // @[issue-slot.scala:52:14]
output io_out_uop_prs1_busy, // @[issue-slot.scala:52:14]
output io_out_uop_prs2_busy, // @[issue-slot.scala:52:14]
output io_out_uop_prs3_busy, // @[issue-slot.scala:52:14]
output io_out_uop_ppred_busy, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:52:14]
output io_out_uop_exception, // @[issue-slot.scala:52:14]
output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:52:14]
output io_out_uop_mem_signed, // @[issue-slot.scala:52:14]
output io_out_uop_uses_ldq, // @[issue-slot.scala:52:14]
output io_out_uop_uses_stq, // @[issue-slot.scala:52:14]
output io_out_uop_is_unique, // @[issue-slot.scala:52:14]
output io_out_uop_flush_on_commit, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_csr_cmd, // @[issue-slot.scala:52:14]
output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_ldst, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
output io_out_uop_frs3_en, // @[issue-slot.scala:52:14]
output io_out_uop_fcn_dw, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_fcn_op, // @[issue-slot.scala:52:14]
output io_out_uop_fp_val, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_fp_rm, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_fp_typ, // @[issue-slot.scala:52:14]
output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
output io_out_uop_bp_debug_if, // @[issue-slot.scala:52:14]
output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:52:14]
input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:52:14]
input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_issued, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_brupdate_b2_uop_br_type, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_eret, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_taken, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_mispredict, // @[issue-slot.scala:52:14]
input io_brupdate_b2_taken, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:52:14]
input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:52:14]
input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:52:14]
input io_kill, // @[issue-slot.scala:52:14]
input io_clear, // @[issue-slot.scala:52:14]
input io_squash_grant, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_0_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_0_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_0_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_wakeup_ports_0_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_0_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_0_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_0_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_0_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_bypassable, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_speculative_mask, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_rebusy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_1_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_1_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_1_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_wakeup_ports_1_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_1_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_1_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_1_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_1_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_2_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_2_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_2_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_wakeup_ports_2_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_2_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_2_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_2_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_2_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_3_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_3_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_3_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_wakeup_ports_3_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_3_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_3_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_3_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_3_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_4_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_4_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_4_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_wakeup_ports_4_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_4_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_4_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_4_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_4_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_4_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_4_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_4_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_4_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_4_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_4_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_4_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_4_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_4_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_4_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_4_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_4_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_4_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_4_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_4_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_4_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_4_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_4_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_pred_wakeup_port_valid, // @[issue-slot.scala:52:14]
input [4:0] io_pred_wakeup_port_bits, // @[issue-slot.scala:52:14]
input [2:0] io_child_rebusys // @[issue-slot.scala:52:14]
);
wire [15:0] next_uop_out_br_mask; // @[util.scala:104:23]
wire io_grant_0 = io_grant; // @[issue-slot.scala:49:7]
wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_0_0 = io_in_uop_bits_iq_type_0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_1_0 = io_in_uop_bits_iq_type_1; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_2_0 = io_in_uop_bits_iq_type_2; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_3_0 = io_in_uop_bits_iq_type_3; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_0_0 = io_in_uop_bits_fu_code_0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_1_0 = io_in_uop_bits_fu_code_1; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_2_0 = io_in_uop_bits_fu_code_2; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_3_0 = io_in_uop_bits_fu_code_3; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_4_0 = io_in_uop_bits_fu_code_4; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_5_0 = io_in_uop_bits_fu_code_5; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_6_0 = io_in_uop_bits_fu_code_6; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_7_0 = io_in_uop_bits_fu_code_7; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_8_0 = io_in_uop_bits_fu_code_8; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_9_0 = io_in_uop_bits_fu_code_9; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_issued_0 = io_in_uop_bits_iw_issued; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_iw_p1_speculative_child_0 = io_in_uop_bits_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_iw_p2_speculative_child_0 = io_in_uop_bits_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_p1_bypass_hint_0 = io_in_uop_bits_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_p2_bypass_hint_0 = io_in_uop_bits_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_p3_bypass_hint_0 = io_in_uop_bits_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_dis_col_sel_0 = io_in_uop_bits_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_in_uop_bits_br_type_0 = io_in_uop_bits_br_type; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_sfence_0 = io_in_uop_bits_is_sfence; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_eret_0 = io_in_uop_bits_is_eret; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_rocc_0 = io_in_uop_bits_is_rocc; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_mov_0 = io_in_uop_bits_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_imm_rename_0 = io_in_uop_bits_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_imm_sel_0 = io_in_uop_bits_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_pimm_0 = io_in_uop_bits_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_op1_sel_0 = io_in_uop_bits_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_op2_sel_0 = io_in_uop_bits_op2_sel; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ldst_0 = io_in_uop_bits_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_wen_0 = io_in_uop_bits_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ren1_0 = io_in_uop_bits_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ren2_0 = io_in_uop_bits_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ren3_0 = io_in_uop_bits_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_swap12_0 = io_in_uop_bits_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_swap23_0 = io_in_uop_bits_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_fp_ctrl_typeTagIn_0 = io_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_fp_ctrl_typeTagOut_0 = io_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_fromint_0 = io_in_uop_bits_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_toint_0 = io_in_uop_bits_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_fastpipe_0 = io_in_uop_bits_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_fma_0 = io_in_uop_bits_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_div_0 = io_in_uop_bits_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_sqrt_0 = io_in_uop_bits_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_wflags_0 = io_in_uop_bits_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_vec_0 = io_in_uop_bits_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_csr_cmd_0 = io_in_uop_bits_csr_cmd; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fcn_dw_0 = io_in_uop_bits_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_fcn_op_0 = io_in_uop_bits_fcn_op; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_fp_rm_0 = io_in_uop_bits_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_fp_typ_0 = io_in_uop_bits_fp_typ; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:49:7]
wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:49:7]
wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:49:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:49:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:49:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:49:7]
wire io_kill_0 = io_kill; // @[issue-slot.scala:49:7]
wire io_clear_0 = io_clear; // @[issue-slot.scala:49:7]
wire io_squash_grant_0 = io_squash_grant; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_0_bits_uop_inst_0 = io_wakeup_ports_0_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_0_bits_uop_debug_inst_0 = io_wakeup_ports_0_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_rvc_0 = io_wakeup_ports_0_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_0_bits_uop_debug_pc_0 = io_wakeup_ports_0_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_0_0 = io_wakeup_ports_0_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_1_0 = io_wakeup_ports_0_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_2_0 = io_wakeup_ports_0_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_3_0 = io_wakeup_ports_0_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_0_0 = io_wakeup_ports_0_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_1_0 = io_wakeup_ports_0_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_2_0 = io_wakeup_ports_0_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_3_0 = io_wakeup_ports_0_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_4_0 = io_wakeup_ports_0_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_5_0 = io_wakeup_ports_0_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_6_0 = io_wakeup_ports_0_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_7_0 = io_wakeup_ports_0_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_8_0 = io_wakeup_ports_0_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_9_0 = io_wakeup_ports_0_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_issued_0 = io_wakeup_ports_0_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel_0 = io_wakeup_ports_0_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_wakeup_ports_0_bits_uop_br_mask_0 = io_wakeup_ports_0_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_0_bits_uop_br_tag_0 = io_wakeup_ports_0_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_0_bits_uop_br_type_0 = io_wakeup_ports_0_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_sfb_0 = io_wakeup_ports_0_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_fence_0 = io_wakeup_ports_0_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_fencei_0 = io_wakeup_ports_0_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_sfence_0 = io_wakeup_ports_0_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_amo_0 = io_wakeup_ports_0_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_eret_0 = io_wakeup_ports_0_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_0_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_rocc_0 = io_wakeup_ports_0_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_mov_0 = io_wakeup_ports_0_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_ftq_idx_0 = io_wakeup_ports_0_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_edge_inst_0 = io_wakeup_ports_0_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_pc_lob_0 = io_wakeup_ports_0_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_taken_0 = io_wakeup_ports_0_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_imm_rename_0 = io_wakeup_ports_0_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_imm_sel_0 = io_wakeup_ports_0_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_pimm_0 = io_wakeup_ports_0_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_0_bits_uop_imm_packed_0 = io_wakeup_ports_0_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_op1_sel_0 = io_wakeup_ports_0_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_op2_sel_0 = io_wakeup_ports_0_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_rob_idx_0 = io_wakeup_ports_0_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_ldq_idx_0 = io_wakeup_ports_0_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_stq_idx_0 = io_wakeup_ports_0_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_rxq_idx_0 = io_wakeup_ports_0_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_pdst_0 = io_wakeup_ports_0_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_prs1_0 = io_wakeup_ports_0_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_prs2_0 = io_wakeup_ports_0_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_prs3_0 = io_wakeup_ports_0_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_ppred_0 = io_wakeup_ports_0_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_prs1_busy_0 = io_wakeup_ports_0_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_prs2_busy_0 = io_wakeup_ports_0_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_prs3_busy_0 = io_wakeup_ports_0_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_ppred_busy_0 = io_wakeup_ports_0_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_stale_pdst_0 = io_wakeup_ports_0_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_exception_0 = io_wakeup_ports_0_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_0_bits_uop_exc_cause_0 = io_wakeup_ports_0_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_mem_cmd_0 = io_wakeup_ports_0_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_mem_size_0 = io_wakeup_ports_0_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_mem_signed_0 = io_wakeup_ports_0_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_uses_ldq_0 = io_wakeup_ports_0_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_uses_stq_0 = io_wakeup_ports_0_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_unique_0 = io_wakeup_ports_0_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_flush_on_commit_0 = io_wakeup_ports_0_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_csr_cmd_0 = io_wakeup_ports_0_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_0_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_ldst_0 = io_wakeup_ports_0_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_lrs1_0 = io_wakeup_ports_0_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_lrs2_0 = io_wakeup_ports_0_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_lrs3_0 = io_wakeup_ports_0_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_dst_rtype_0 = io_wakeup_ports_0_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype_0 = io_wakeup_ports_0_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype_0 = io_wakeup_ports_0_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_frs3_en_0 = io_wakeup_ports_0_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fcn_dw_0 = io_wakeup_ports_0_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_fcn_op_0 = io_wakeup_ports_0_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_val_0 = io_wakeup_ports_0_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_fp_rm_0 = io_wakeup_ports_0_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_fp_typ_0 = io_wakeup_ports_0_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_0_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_bp_debug_if_0 = io_wakeup_ports_0_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_0_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc_0 = io_wakeup_ports_0_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc_0 = io_wakeup_ports_0_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_bypassable_0 = io_wakeup_ports_0_bits_bypassable; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_speculative_mask_0 = io_wakeup_ports_0_bits_speculative_mask; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_rebusy_0 = io_wakeup_ports_0_bits_rebusy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_1_bits_uop_inst_0 = io_wakeup_ports_1_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_1_bits_uop_debug_inst_0 = io_wakeup_ports_1_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_rvc_0 = io_wakeup_ports_1_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_1_bits_uop_debug_pc_0 = io_wakeup_ports_1_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_0_0 = io_wakeup_ports_1_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_1_0 = io_wakeup_ports_1_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_2_0 = io_wakeup_ports_1_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_3_0 = io_wakeup_ports_1_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_0_0 = io_wakeup_ports_1_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_1_0 = io_wakeup_ports_1_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_2_0 = io_wakeup_ports_1_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_3_0 = io_wakeup_ports_1_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_4_0 = io_wakeup_ports_1_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_5_0 = io_wakeup_ports_1_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_6_0 = io_wakeup_ports_1_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_7_0 = io_wakeup_ports_1_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_8_0 = io_wakeup_ports_1_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_9_0 = io_wakeup_ports_1_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_issued_0 = io_wakeup_ports_1_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel_0 = io_wakeup_ports_1_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_wakeup_ports_1_bits_uop_br_mask_0 = io_wakeup_ports_1_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_1_bits_uop_br_tag_0 = io_wakeup_ports_1_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_1_bits_uop_br_type_0 = io_wakeup_ports_1_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_sfb_0 = io_wakeup_ports_1_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_fence_0 = io_wakeup_ports_1_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_fencei_0 = io_wakeup_ports_1_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_sfence_0 = io_wakeup_ports_1_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_amo_0 = io_wakeup_ports_1_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_eret_0 = io_wakeup_ports_1_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_1_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_rocc_0 = io_wakeup_ports_1_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_mov_0 = io_wakeup_ports_1_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_ftq_idx_0 = io_wakeup_ports_1_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_edge_inst_0 = io_wakeup_ports_1_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_pc_lob_0 = io_wakeup_ports_1_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_taken_0 = io_wakeup_ports_1_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_imm_rename_0 = io_wakeup_ports_1_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_imm_sel_0 = io_wakeup_ports_1_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_pimm_0 = io_wakeup_ports_1_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_1_bits_uop_imm_packed_0 = io_wakeup_ports_1_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_op1_sel_0 = io_wakeup_ports_1_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_op2_sel_0 = io_wakeup_ports_1_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_rob_idx_0 = io_wakeup_ports_1_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_ldq_idx_0 = io_wakeup_ports_1_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_stq_idx_0 = io_wakeup_ports_1_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_rxq_idx_0 = io_wakeup_ports_1_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_pdst_0 = io_wakeup_ports_1_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_prs1_0 = io_wakeup_ports_1_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_prs2_0 = io_wakeup_ports_1_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_prs3_0 = io_wakeup_ports_1_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_ppred_0 = io_wakeup_ports_1_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_prs1_busy_0 = io_wakeup_ports_1_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_prs2_busy_0 = io_wakeup_ports_1_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_prs3_busy_0 = io_wakeup_ports_1_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_ppred_busy_0 = io_wakeup_ports_1_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_stale_pdst_0 = io_wakeup_ports_1_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_exception_0 = io_wakeup_ports_1_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_1_bits_uop_exc_cause_0 = io_wakeup_ports_1_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_mem_cmd_0 = io_wakeup_ports_1_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_mem_size_0 = io_wakeup_ports_1_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_mem_signed_0 = io_wakeup_ports_1_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_uses_ldq_0 = io_wakeup_ports_1_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_uses_stq_0 = io_wakeup_ports_1_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_unique_0 = io_wakeup_ports_1_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_flush_on_commit_0 = io_wakeup_ports_1_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_csr_cmd_0 = io_wakeup_ports_1_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_1_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_ldst_0 = io_wakeup_ports_1_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_lrs1_0 = io_wakeup_ports_1_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_lrs2_0 = io_wakeup_ports_1_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_lrs3_0 = io_wakeup_ports_1_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_dst_rtype_0 = io_wakeup_ports_1_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype_0 = io_wakeup_ports_1_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype_0 = io_wakeup_ports_1_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_frs3_en_0 = io_wakeup_ports_1_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fcn_dw_0 = io_wakeup_ports_1_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_fcn_op_0 = io_wakeup_ports_1_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_val_0 = io_wakeup_ports_1_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_fp_rm_0 = io_wakeup_ports_1_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_fp_typ_0 = io_wakeup_ports_1_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_1_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_bp_debug_if_0 = io_wakeup_ports_1_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_1_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc_0 = io_wakeup_ports_1_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc_0 = io_wakeup_ports_1_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_2_bits_uop_inst_0 = io_wakeup_ports_2_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_2_bits_uop_debug_inst_0 = io_wakeup_ports_2_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_rvc_0 = io_wakeup_ports_2_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_2_bits_uop_debug_pc_0 = io_wakeup_ports_2_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iq_type_0_0 = io_wakeup_ports_2_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iq_type_1_0 = io_wakeup_ports_2_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iq_type_2_0 = io_wakeup_ports_2_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iq_type_3_0 = io_wakeup_ports_2_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_0_0 = io_wakeup_ports_2_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_1_0 = io_wakeup_ports_2_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_2_0 = io_wakeup_ports_2_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_3_0 = io_wakeup_ports_2_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_4_0 = io_wakeup_ports_2_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_5_0 = io_wakeup_ports_2_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_6_0 = io_wakeup_ports_2_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_7_0 = io_wakeup_ports_2_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_8_0 = io_wakeup_ports_2_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_9_0 = io_wakeup_ports_2_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_issued_0 = io_wakeup_ports_2_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_dis_col_sel_0 = io_wakeup_ports_2_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_wakeup_ports_2_bits_uop_br_mask_0 = io_wakeup_ports_2_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_2_bits_uop_br_tag_0 = io_wakeup_ports_2_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_2_bits_uop_br_type_0 = io_wakeup_ports_2_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_sfb_0 = io_wakeup_ports_2_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_fence_0 = io_wakeup_ports_2_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_fencei_0 = io_wakeup_ports_2_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_sfence_0 = io_wakeup_ports_2_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_amo_0 = io_wakeup_ports_2_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_eret_0 = io_wakeup_ports_2_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_2_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_rocc_0 = io_wakeup_ports_2_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_mov_0 = io_wakeup_ports_2_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_ftq_idx_0 = io_wakeup_ports_2_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_edge_inst_0 = io_wakeup_ports_2_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_pc_lob_0 = io_wakeup_ports_2_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_taken_0 = io_wakeup_ports_2_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_imm_rename_0 = io_wakeup_ports_2_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_imm_sel_0 = io_wakeup_ports_2_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_pimm_0 = io_wakeup_ports_2_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_2_bits_uop_imm_packed_0 = io_wakeup_ports_2_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_op1_sel_0 = io_wakeup_ports_2_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_op2_sel_0 = io_wakeup_ports_2_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_rob_idx_0 = io_wakeup_ports_2_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_ldq_idx_0 = io_wakeup_ports_2_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_stq_idx_0 = io_wakeup_ports_2_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_rxq_idx_0 = io_wakeup_ports_2_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_pdst_0 = io_wakeup_ports_2_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_prs1_0 = io_wakeup_ports_2_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_prs2_0 = io_wakeup_ports_2_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_prs3_0 = io_wakeup_ports_2_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_ppred_0 = io_wakeup_ports_2_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_prs1_busy_0 = io_wakeup_ports_2_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_prs2_busy_0 = io_wakeup_ports_2_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_prs3_busy_0 = io_wakeup_ports_2_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_ppred_busy_0 = io_wakeup_ports_2_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_stale_pdst_0 = io_wakeup_ports_2_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_exception_0 = io_wakeup_ports_2_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_2_bits_uop_exc_cause_0 = io_wakeup_ports_2_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_mem_cmd_0 = io_wakeup_ports_2_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_mem_size_0 = io_wakeup_ports_2_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_mem_signed_0 = io_wakeup_ports_2_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_uses_ldq_0 = io_wakeup_ports_2_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_uses_stq_0 = io_wakeup_ports_2_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_unique_0 = io_wakeup_ports_2_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_flush_on_commit_0 = io_wakeup_ports_2_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_csr_cmd_0 = io_wakeup_ports_2_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_2_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_ldst_0 = io_wakeup_ports_2_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_lrs1_0 = io_wakeup_ports_2_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_lrs2_0 = io_wakeup_ports_2_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_lrs3_0 = io_wakeup_ports_2_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_dst_rtype_0 = io_wakeup_ports_2_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype_0 = io_wakeup_ports_2_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype_0 = io_wakeup_ports_2_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_frs3_en_0 = io_wakeup_ports_2_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fcn_dw_0 = io_wakeup_ports_2_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_fcn_op_0 = io_wakeup_ports_2_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_val_0 = io_wakeup_ports_2_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_fp_rm_0 = io_wakeup_ports_2_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_fp_typ_0 = io_wakeup_ports_2_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_2_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_bp_debug_if_0 = io_wakeup_ports_2_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_2_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc_0 = io_wakeup_ports_2_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc_0 = io_wakeup_ports_2_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_3_bits_uop_inst_0 = io_wakeup_ports_3_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_3_bits_uop_debug_inst_0 = io_wakeup_ports_3_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_rvc_0 = io_wakeup_ports_3_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_3_bits_uop_debug_pc_0 = io_wakeup_ports_3_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iq_type_0_0 = io_wakeup_ports_3_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iq_type_1_0 = io_wakeup_ports_3_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iq_type_2_0 = io_wakeup_ports_3_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iq_type_3_0 = io_wakeup_ports_3_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_0_0 = io_wakeup_ports_3_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_1_0 = io_wakeup_ports_3_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_2_0 = io_wakeup_ports_3_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_3_0 = io_wakeup_ports_3_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_4_0 = io_wakeup_ports_3_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_5_0 = io_wakeup_ports_3_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_6_0 = io_wakeup_ports_3_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_7_0 = io_wakeup_ports_3_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_8_0 = io_wakeup_ports_3_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_9_0 = io_wakeup_ports_3_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_issued_0 = io_wakeup_ports_3_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_dis_col_sel_0 = io_wakeup_ports_3_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_wakeup_ports_3_bits_uop_br_mask_0 = io_wakeup_ports_3_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_3_bits_uop_br_tag_0 = io_wakeup_ports_3_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_3_bits_uop_br_type_0 = io_wakeup_ports_3_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_sfb_0 = io_wakeup_ports_3_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_fence_0 = io_wakeup_ports_3_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_fencei_0 = io_wakeup_ports_3_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_sfence_0 = io_wakeup_ports_3_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_amo_0 = io_wakeup_ports_3_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_eret_0 = io_wakeup_ports_3_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_3_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_rocc_0 = io_wakeup_ports_3_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_mov_0 = io_wakeup_ports_3_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_ftq_idx_0 = io_wakeup_ports_3_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_edge_inst_0 = io_wakeup_ports_3_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_pc_lob_0 = io_wakeup_ports_3_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_taken_0 = io_wakeup_ports_3_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_imm_rename_0 = io_wakeup_ports_3_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_imm_sel_0 = io_wakeup_ports_3_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_pimm_0 = io_wakeup_ports_3_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_3_bits_uop_imm_packed_0 = io_wakeup_ports_3_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_op1_sel_0 = io_wakeup_ports_3_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_op2_sel_0 = io_wakeup_ports_3_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_rob_idx_0 = io_wakeup_ports_3_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_ldq_idx_0 = io_wakeup_ports_3_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_stq_idx_0 = io_wakeup_ports_3_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_rxq_idx_0 = io_wakeup_ports_3_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_pdst_0 = io_wakeup_ports_3_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_prs1_0 = io_wakeup_ports_3_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_prs2_0 = io_wakeup_ports_3_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_prs3_0 = io_wakeup_ports_3_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_ppred_0 = io_wakeup_ports_3_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_prs1_busy_0 = io_wakeup_ports_3_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_prs2_busy_0 = io_wakeup_ports_3_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_prs3_busy_0 = io_wakeup_ports_3_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_ppred_busy_0 = io_wakeup_ports_3_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_stale_pdst_0 = io_wakeup_ports_3_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_exception_0 = io_wakeup_ports_3_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_3_bits_uop_exc_cause_0 = io_wakeup_ports_3_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_mem_cmd_0 = io_wakeup_ports_3_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_mem_size_0 = io_wakeup_ports_3_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_mem_signed_0 = io_wakeup_ports_3_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_uses_ldq_0 = io_wakeup_ports_3_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_uses_stq_0 = io_wakeup_ports_3_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_unique_0 = io_wakeup_ports_3_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_flush_on_commit_0 = io_wakeup_ports_3_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_csr_cmd_0 = io_wakeup_ports_3_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_3_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_ldst_0 = io_wakeup_ports_3_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_lrs1_0 = io_wakeup_ports_3_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_lrs2_0 = io_wakeup_ports_3_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_lrs3_0 = io_wakeup_ports_3_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_dst_rtype_0 = io_wakeup_ports_3_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype_0 = io_wakeup_ports_3_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype_0 = io_wakeup_ports_3_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_frs3_en_0 = io_wakeup_ports_3_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fcn_dw_0 = io_wakeup_ports_3_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_fcn_op_0 = io_wakeup_ports_3_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_val_0 = io_wakeup_ports_3_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_fp_rm_0 = io_wakeup_ports_3_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_fp_typ_0 = io_wakeup_ports_3_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_3_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_bp_debug_if_0 = io_wakeup_ports_3_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_3_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc_0 = io_wakeup_ports_3_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc_0 = io_wakeup_ports_3_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_valid_0 = io_wakeup_ports_4_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_4_bits_uop_inst_0 = io_wakeup_ports_4_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_4_bits_uop_debug_inst_0 = io_wakeup_ports_4_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_rvc_0 = io_wakeup_ports_4_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_4_bits_uop_debug_pc_0 = io_wakeup_ports_4_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iq_type_0_0 = io_wakeup_ports_4_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iq_type_1_0 = io_wakeup_ports_4_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iq_type_2_0 = io_wakeup_ports_4_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iq_type_3_0 = io_wakeup_ports_4_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_0_0 = io_wakeup_ports_4_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_1_0 = io_wakeup_ports_4_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_2_0 = io_wakeup_ports_4_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_3_0 = io_wakeup_ports_4_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_4_0 = io_wakeup_ports_4_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_5_0 = io_wakeup_ports_4_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_6_0 = io_wakeup_ports_4_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_7_0 = io_wakeup_ports_4_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_8_0 = io_wakeup_ports_4_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_9_0 = io_wakeup_ports_4_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iw_issued_0 = io_wakeup_ports_4_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_4_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_4_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_dis_col_sel_0 = io_wakeup_ports_4_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_wakeup_ports_4_bits_uop_br_mask_0 = io_wakeup_ports_4_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_4_bits_uop_br_tag_0 = io_wakeup_ports_4_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_4_bits_uop_br_type_0 = io_wakeup_ports_4_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_sfb_0 = io_wakeup_ports_4_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_fence_0 = io_wakeup_ports_4_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_fencei_0 = io_wakeup_ports_4_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_sfence_0 = io_wakeup_ports_4_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_amo_0 = io_wakeup_ports_4_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_eret_0 = io_wakeup_ports_4_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_4_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_rocc_0 = io_wakeup_ports_4_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_mov_0 = io_wakeup_ports_4_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_4_bits_uop_ftq_idx_0 = io_wakeup_ports_4_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_edge_inst_0 = io_wakeup_ports_4_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_4_bits_uop_pc_lob_0 = io_wakeup_ports_4_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_taken_0 = io_wakeup_ports_4_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_imm_rename_0 = io_wakeup_ports_4_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_imm_sel_0 = io_wakeup_ports_4_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_4_bits_uop_pimm_0 = io_wakeup_ports_4_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_4_bits_uop_imm_packed_0 = io_wakeup_ports_4_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_op1_sel_0 = io_wakeup_ports_4_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_op2_sel_0 = io_wakeup_ports_4_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_4_bits_uop_rob_idx_0 = io_wakeup_ports_4_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_4_bits_uop_ldq_idx_0 = io_wakeup_ports_4_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_4_bits_uop_stq_idx_0 = io_wakeup_ports_4_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_rxq_idx_0 = io_wakeup_ports_4_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_4_bits_uop_pdst_0 = io_wakeup_ports_4_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_4_bits_uop_prs1_0 = io_wakeup_ports_4_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_4_bits_uop_prs2_0 = io_wakeup_ports_4_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_4_bits_uop_prs3_0 = io_wakeup_ports_4_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_4_bits_uop_ppred_0 = io_wakeup_ports_4_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_prs1_busy_0 = io_wakeup_ports_4_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_prs2_busy_0 = io_wakeup_ports_4_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_prs3_busy_0 = io_wakeup_ports_4_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_ppred_busy_0 = io_wakeup_ports_4_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_4_bits_uop_stale_pdst_0 = io_wakeup_ports_4_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_exception_0 = io_wakeup_ports_4_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_4_bits_uop_exc_cause_0 = io_wakeup_ports_4_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_4_bits_uop_mem_cmd_0 = io_wakeup_ports_4_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_mem_size_0 = io_wakeup_ports_4_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_mem_signed_0 = io_wakeup_ports_4_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_uses_ldq_0 = io_wakeup_ports_4_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_uses_stq_0 = io_wakeup_ports_4_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_unique_0 = io_wakeup_ports_4_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_flush_on_commit_0 = io_wakeup_ports_4_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_csr_cmd_0 = io_wakeup_ports_4_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_4_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_4_bits_uop_ldst_0 = io_wakeup_ports_4_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_4_bits_uop_lrs1_0 = io_wakeup_ports_4_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_4_bits_uop_lrs2_0 = io_wakeup_ports_4_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_4_bits_uop_lrs3_0 = io_wakeup_ports_4_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_dst_rtype_0 = io_wakeup_ports_4_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_lrs1_rtype_0 = io_wakeup_ports_4_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_lrs2_rtype_0 = io_wakeup_ports_4_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_frs3_en_0 = io_wakeup_ports_4_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fcn_dw_0 = io_wakeup_ports_4_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_4_bits_uop_fcn_op_0 = io_wakeup_ports_4_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_val_0 = io_wakeup_ports_4_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_fp_rm_0 = io_wakeup_ports_4_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_fp_typ_0 = io_wakeup_ports_4_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_4_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_4_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_4_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_bp_debug_if_0 = io_wakeup_ports_4_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_4_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_debug_fsrc_0 = io_wakeup_ports_4_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_debug_tsrc_0 = io_wakeup_ports_4_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_pred_wakeup_port_valid_0 = io_pred_wakeup_port_valid; // @[issue-slot.scala:49:7]
wire [4:0] io_pred_wakeup_port_bits_0 = io_pred_wakeup_port_bits; // @[issue-slot.scala:49:7]
wire [2:0] io_child_rebusys_0 = io_child_rebusys; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7]
wire next_uop_out_iw_issued_partial_agen = 1'h0; // @[util.scala:104:23]
wire next_uop_out_iw_issued_partial_dgen = 1'h0; // @[util.scala:104:23]
wire next_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:59:28]
wire next_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:59:28]
wire prs1_rebusys_1 = 1'h0; // @[issue-slot.scala:102:91]
wire prs1_rebusys_2 = 1'h0; // @[issue-slot.scala:102:91]
wire prs1_rebusys_3 = 1'h0; // @[issue-slot.scala:102:91]
wire prs1_rebusys_4 = 1'h0; // @[issue-slot.scala:102:91]
wire prs2_rebusys_1 = 1'h0; // @[issue-slot.scala:103:91]
wire prs2_rebusys_2 = 1'h0; // @[issue-slot.scala:103:91]
wire prs2_rebusys_3 = 1'h0; // @[issue-slot.scala:103:91]
wire prs2_rebusys_4 = 1'h0; // @[issue-slot.scala:103:91]
wire _next_uop_iw_p1_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _next_uop_iw_p2_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _next_uop_iw_p3_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _iss_ready_T_6 = 1'h0; // @[issue-slot.scala:136:131]
wire agen_ready = 1'h0; // @[issue-slot.scala:137:114]
wire dgen_ready = 1'h0; // @[issue-slot.scala:138:114]
wire [2:0] io_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-slot.scala:49:7]
wire [2:0] _next_uop_iw_p1_speculative_child_T_1 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _next_uop_iw_p2_speculative_child_T_1 = 3'h0; // @[Mux.scala:30:73]
wire io_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7]
wire _iss_ready_T_7 = 1'h1; // @[issue-slot.scala:136:110]
wire [2:0] io_wakeup_ports_2_bits_speculative_mask = 3'h1; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_speculative_mask = 3'h2; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_speculative_mask = 3'h4; // @[issue-slot.scala:49:7]
wire _io_will_be_valid_T_1; // @[issue-slot.scala:65:34]
wire _io_request_T_4; // @[issue-slot.scala:140:51]
wire [31:0] next_uop_inst; // @[issue-slot.scala:59:28]
wire [31:0] next_uop_debug_inst; // @[issue-slot.scala:59:28]
wire next_uop_is_rvc; // @[issue-slot.scala:59:28]
wire [39:0] next_uop_debug_pc; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_0; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_1; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_2; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_3; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_0; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_1; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_2; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_3; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_4; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_5; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_6; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_7; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_8; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_9; // @[issue-slot.scala:59:28]
wire next_uop_iw_issued; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_iw_p1_speculative_child; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_iw_p2_speculative_child; // @[issue-slot.scala:59:28]
wire next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:59:28]
wire next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:59:28]
wire next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_dis_col_sel; // @[issue-slot.scala:59:28]
wire [15:0] next_uop_br_mask; // @[issue-slot.scala:59:28]
wire [3:0] next_uop_br_tag; // @[issue-slot.scala:59:28]
wire [3:0] next_uop_br_type; // @[issue-slot.scala:59:28]
wire next_uop_is_sfb; // @[issue-slot.scala:59:28]
wire next_uop_is_fence; // @[issue-slot.scala:59:28]
wire next_uop_is_fencei; // @[issue-slot.scala:59:28]
wire next_uop_is_sfence; // @[issue-slot.scala:59:28]
wire next_uop_is_amo; // @[issue-slot.scala:59:28]
wire next_uop_is_eret; // @[issue-slot.scala:59:28]
wire next_uop_is_sys_pc2epc; // @[issue-slot.scala:59:28]
wire next_uop_is_rocc; // @[issue-slot.scala:59:28]
wire next_uop_is_mov; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_ftq_idx; // @[issue-slot.scala:59:28]
wire next_uop_edge_inst; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_pc_lob; // @[issue-slot.scala:59:28]
wire next_uop_taken; // @[issue-slot.scala:59:28]
wire next_uop_imm_rename; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_imm_sel; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_pimm; // @[issue-slot.scala:59:28]
wire [19:0] next_uop_imm_packed; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_op1_sel; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_op2_sel; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ldst; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_wen; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ren1; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ren2; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ren3; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_swap12; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_swap23; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_fromint; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_toint; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_fma; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_div; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_wflags; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_vec; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_rob_idx; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_ldq_idx; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_stq_idx; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_rxq_idx; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_pdst; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_prs1; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_prs2; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_prs3; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_ppred; // @[issue-slot.scala:59:28]
wire next_uop_prs1_busy; // @[issue-slot.scala:59:28]
wire next_uop_prs2_busy; // @[issue-slot.scala:59:28]
wire next_uop_prs3_busy; // @[issue-slot.scala:59:28]
wire next_uop_ppred_busy; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_stale_pdst; // @[issue-slot.scala:59:28]
wire next_uop_exception; // @[issue-slot.scala:59:28]
wire [63:0] next_uop_exc_cause; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_mem_cmd; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_mem_size; // @[issue-slot.scala:59:28]
wire next_uop_mem_signed; // @[issue-slot.scala:59:28]
wire next_uop_uses_ldq; // @[issue-slot.scala:59:28]
wire next_uop_uses_stq; // @[issue-slot.scala:59:28]
wire next_uop_is_unique; // @[issue-slot.scala:59:28]
wire next_uop_flush_on_commit; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_csr_cmd; // @[issue-slot.scala:59:28]
wire next_uop_ldst_is_rs1; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_ldst; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_lrs1; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_lrs2; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_lrs3; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_dst_rtype; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_lrs1_rtype; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_lrs2_rtype; // @[issue-slot.scala:59:28]
wire next_uop_frs3_en; // @[issue-slot.scala:59:28]
wire next_uop_fcn_dw; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_fcn_op; // @[issue-slot.scala:59:28]
wire next_uop_fp_val; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_fp_rm; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_fp_typ; // @[issue-slot.scala:59:28]
wire next_uop_xcpt_pf_if; // @[issue-slot.scala:59:28]
wire next_uop_xcpt_ae_if; // @[issue-slot.scala:59:28]
wire next_uop_xcpt_ma_if; // @[issue-slot.scala:59:28]
wire next_uop_bp_debug_if; // @[issue-slot.scala:59:28]
wire next_uop_bp_xcpt_if; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_debug_fsrc; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_debug_tsrc; // @[issue-slot.scala:59:28]
wire io_iss_uop_iq_type_0_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iq_type_1_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iq_type_2_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iq_type_3_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_0_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_1_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_2_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_3_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_4_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_5_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_6_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_7_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_8_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_9_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7]
wire [31:0] io_iss_uop_inst_0; // @[issue-slot.scala:49:7]
wire [31:0] io_iss_uop_debug_inst_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_rvc_0; // @[issue-slot.scala:49:7]
wire [39:0] io_iss_uop_debug_pc_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_issued_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_dis_col_sel_0; // @[issue-slot.scala:49:7]
wire [15:0] io_iss_uop_br_mask_0; // @[issue-slot.scala:49:7]
wire [3:0] io_iss_uop_br_tag_0; // @[issue-slot.scala:49:7]
wire [3:0] io_iss_uop_br_type_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_sfb_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_fence_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_fencei_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_sfence_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_amo_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_eret_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_rocc_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_mov_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_ftq_idx_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_edge_inst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_pc_lob_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_taken_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_imm_rename_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_imm_sel_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_pimm_0; // @[issue-slot.scala:49:7]
wire [19:0] io_iss_uop_imm_packed_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_op1_sel_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_op2_sel_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_rob_idx_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_ldq_idx_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_stq_idx_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_rxq_idx_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_pdst_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_prs1_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_prs2_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_prs3_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_ppred_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_prs1_busy_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_prs2_busy_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_prs3_busy_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_ppred_busy_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_stale_pdst_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_exception_0; // @[issue-slot.scala:49:7]
wire [63:0] io_iss_uop_exc_cause_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_mem_cmd_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_mem_size_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_mem_signed_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_uses_ldq_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_uses_stq_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_unique_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_flush_on_commit_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_csr_cmd_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_ldst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_lrs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_lrs2_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_lrs3_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_dst_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_frs3_en_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fcn_dw_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_fcn_op_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_val_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_fp_rm_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_fp_typ_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_bp_debug_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_debug_fsrc_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_debug_tsrc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_0_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_1_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_2_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_3_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_0_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_1_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_2_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_3_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_4_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_5_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_6_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_7_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_8_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_9_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7]
wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:49:7]
wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_rvc_0; // @[issue-slot.scala:49:7]
wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_issued_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_dis_col_sel_0; // @[issue-slot.scala:49:7]
wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:49:7]
wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:49:7]
wire [3:0] io_out_uop_br_type_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_sfb_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_fence_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_fencei_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_sfence_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_amo_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_eret_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_rocc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_mov_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:49:7]
wire io_out_uop_edge_inst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:49:7]
wire io_out_uop_taken_0; // @[issue-slot.scala:49:7]
wire io_out_uop_imm_rename_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_imm_sel_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_pimm_0; // @[issue-slot.scala:49:7]
wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_op1_sel_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_op2_sel_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:49:7]
wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:49:7]
wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:49:7]
wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:49:7]
wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:49:7]
wire io_out_uop_exception_0; // @[issue-slot.scala:49:7]
wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:49:7]
wire io_out_uop_mem_signed_0; // @[issue-slot.scala:49:7]
wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:49:7]
wire io_out_uop_uses_stq_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_unique_0; // @[issue-slot.scala:49:7]
wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_csr_cmd_0; // @[issue-slot.scala:49:7]
wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7]
wire io_out_uop_frs3_en_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fcn_dw_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_fcn_op_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_val_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_fp_rm_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_fp_typ_0; // @[issue-slot.scala:49:7]
wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:49:7]
wire io_valid_0; // @[issue-slot.scala:49:7]
wire io_will_be_valid_0; // @[issue-slot.scala:49:7]
wire io_request_0; // @[issue-slot.scala:49:7]
reg slot_valid; // @[issue-slot.scala:55:27]
assign io_valid_0 = slot_valid; // @[issue-slot.scala:49:7, :55:27]
reg [31:0] slot_uop_inst; // @[issue-slot.scala:56:21]
assign io_iss_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:49:7, :56:21]
wire [31:0] next_uop_out_inst = slot_uop_inst; // @[util.scala:104:23]
reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:49:7, :56:21]
wire [31:0] next_uop_out_debug_inst = slot_uop_debug_inst; // @[util.scala:104:23]
reg slot_uop_is_rvc; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_rvc = slot_uop_is_rvc; // @[util.scala:104:23]
reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:49:7, :56:21]
wire [39:0] next_uop_out_debug_pc = slot_uop_debug_pc; // @[util.scala:104:23]
reg slot_uop_iq_type_0; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_0_0 = slot_uop_iq_type_0; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_0 = slot_uop_iq_type_0; // @[util.scala:104:23]
reg slot_uop_iq_type_1; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_1_0 = slot_uop_iq_type_1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_1 = slot_uop_iq_type_1; // @[util.scala:104:23]
reg slot_uop_iq_type_2; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_2_0 = slot_uop_iq_type_2; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_2 = slot_uop_iq_type_2; // @[util.scala:104:23]
reg slot_uop_iq_type_3; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_3_0 = slot_uop_iq_type_3; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_3 = slot_uop_iq_type_3; // @[util.scala:104:23]
reg slot_uop_fu_code_0; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_0_0 = slot_uop_fu_code_0; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_0 = slot_uop_fu_code_0; // @[util.scala:104:23]
reg slot_uop_fu_code_1; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_1_0 = slot_uop_fu_code_1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_1 = slot_uop_fu_code_1; // @[util.scala:104:23]
reg slot_uop_fu_code_2; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_2_0 = slot_uop_fu_code_2; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_2 = slot_uop_fu_code_2; // @[util.scala:104:23]
reg slot_uop_fu_code_3; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_3_0 = slot_uop_fu_code_3; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_3 = slot_uop_fu_code_3; // @[util.scala:104:23]
reg slot_uop_fu_code_4; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_4_0 = slot_uop_fu_code_4; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_4 = slot_uop_fu_code_4; // @[util.scala:104:23]
reg slot_uop_fu_code_5; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_5_0 = slot_uop_fu_code_5; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_5 = slot_uop_fu_code_5; // @[util.scala:104:23]
reg slot_uop_fu_code_6; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_6_0 = slot_uop_fu_code_6; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_6 = slot_uop_fu_code_6; // @[util.scala:104:23]
reg slot_uop_fu_code_7; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_7_0 = slot_uop_fu_code_7; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_7 = slot_uop_fu_code_7; // @[util.scala:104:23]
reg slot_uop_fu_code_8; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_8_0 = slot_uop_fu_code_8; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_8 = slot_uop_fu_code_8; // @[util.scala:104:23]
reg slot_uop_fu_code_9; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_9_0 = slot_uop_fu_code_9; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_9 = slot_uop_fu_code_9; // @[util.scala:104:23]
reg slot_uop_iw_issued; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_issued_0 = slot_uop_iw_issued; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_issued = slot_uop_iw_issued; // @[util.scala:104:23]
reg [2:0] slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p1_speculative_child_0 = slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_iw_p1_speculative_child = slot_uop_iw_p1_speculative_child; // @[util.scala:104:23]
reg [2:0] slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p2_speculative_child_0 = slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_iw_p2_speculative_child = slot_uop_iw_p2_speculative_child; // @[util.scala:104:23]
reg slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p1_bypass_hint_0 = slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_p1_bypass_hint = slot_uop_iw_p1_bypass_hint; // @[util.scala:104:23]
reg slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p2_bypass_hint_0 = slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_p2_bypass_hint = slot_uop_iw_p2_bypass_hint; // @[util.scala:104:23]
reg slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p3_bypass_hint_0 = slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_p3_bypass_hint = slot_uop_iw_p3_bypass_hint; // @[util.scala:104:23]
reg [2:0] slot_uop_dis_col_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_dis_col_sel_0 = slot_uop_dis_col_sel; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_dis_col_sel = slot_uop_dis_col_sel; // @[util.scala:104:23]
reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:56:21]
assign io_iss_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:49:7, :56:21]
reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:56:21]
assign io_iss_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:49:7, :56:21]
wire [3:0] next_uop_out_br_tag = slot_uop_br_tag; // @[util.scala:104:23]
reg [3:0] slot_uop_br_type; // @[issue-slot.scala:56:21]
assign io_iss_uop_br_type_0 = slot_uop_br_type; // @[issue-slot.scala:49:7, :56:21]
wire [3:0] next_uop_out_br_type = slot_uop_br_type; // @[util.scala:104:23]
reg slot_uop_is_sfb; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_sfb = slot_uop_is_sfb; // @[util.scala:104:23]
reg slot_uop_is_fence; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_fence = slot_uop_is_fence; // @[util.scala:104:23]
reg slot_uop_is_fencei; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_fencei = slot_uop_is_fencei; // @[util.scala:104:23]
reg slot_uop_is_sfence; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_sfence_0 = slot_uop_is_sfence; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_sfence = slot_uop_is_sfence; // @[util.scala:104:23]
reg slot_uop_is_amo; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_amo = slot_uop_is_amo; // @[util.scala:104:23]
reg slot_uop_is_eret; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_eret_0 = slot_uop_is_eret; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_eret = slot_uop_is_eret; // @[util.scala:104:23]
reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_sys_pc2epc = slot_uop_is_sys_pc2epc; // @[util.scala:104:23]
reg slot_uop_is_rocc; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_rocc_0 = slot_uop_is_rocc; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_rocc = slot_uop_is_rocc; // @[util.scala:104:23]
reg slot_uop_is_mov; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_mov_0 = slot_uop_is_mov; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_mov = slot_uop_is_mov; // @[util.scala:104:23]
reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_ftq_idx = slot_uop_ftq_idx; // @[util.scala:104:23]
reg slot_uop_edge_inst; // @[issue-slot.scala:56:21]
assign io_iss_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_edge_inst = slot_uop_edge_inst; // @[util.scala:104:23]
reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:56:21]
assign io_iss_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_pc_lob = slot_uop_pc_lob; // @[util.scala:104:23]
reg slot_uop_taken; // @[issue-slot.scala:56:21]
assign io_iss_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_taken = slot_uop_taken; // @[util.scala:104:23]
reg slot_uop_imm_rename; // @[issue-slot.scala:56:21]
assign io_iss_uop_imm_rename_0 = slot_uop_imm_rename; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_imm_rename = slot_uop_imm_rename; // @[util.scala:104:23]
reg [2:0] slot_uop_imm_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_imm_sel_0 = slot_uop_imm_sel; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_imm_sel = slot_uop_imm_sel; // @[util.scala:104:23]
reg [4:0] slot_uop_pimm; // @[issue-slot.scala:56:21]
assign io_iss_uop_pimm_0 = slot_uop_pimm; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_pimm = slot_uop_pimm; // @[util.scala:104:23]
reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:56:21]
assign io_iss_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:49:7, :56:21]
wire [19:0] next_uop_out_imm_packed = slot_uop_imm_packed; // @[util.scala:104:23]
reg [1:0] slot_uop_op1_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_op1_sel_0 = slot_uop_op1_sel; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_op1_sel = slot_uop_op1_sel; // @[util.scala:104:23]
reg [2:0] slot_uop_op2_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_op2_sel_0 = slot_uop_op2_sel; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_op2_sel = slot_uop_op2_sel; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ldst_0 = slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ldst = slot_uop_fp_ctrl_ldst; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_wen; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_wen_0 = slot_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_wen = slot_uop_fp_ctrl_wen; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ren1_0 = slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ren1 = slot_uop_fp_ctrl_ren1; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ren2_0 = slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ren2 = slot_uop_fp_ctrl_ren2; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ren3_0 = slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ren3 = slot_uop_fp_ctrl_ren3; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_swap12_0 = slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_swap12 = slot_uop_fp_ctrl_swap12; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_swap23_0 = slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_swap23 = slot_uop_fp_ctrl_swap23; // @[util.scala:104:23]
reg [1:0] slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_typeTagIn_0 = slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_fp_ctrl_typeTagIn = slot_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23]
reg [1:0] slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_typeTagOut_0 = slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_fp_ctrl_typeTagOut = slot_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_fromint_0 = slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_fromint = slot_uop_fp_ctrl_fromint; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_toint; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_toint_0 = slot_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_toint = slot_uop_fp_ctrl_toint; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_fastpipe_0 = slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_fastpipe = slot_uop_fp_ctrl_fastpipe; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_fma; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_fma_0 = slot_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_fma = slot_uop_fp_ctrl_fma; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_div; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_div_0 = slot_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_div = slot_uop_fp_ctrl_div; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_sqrt_0 = slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_sqrt = slot_uop_fp_ctrl_sqrt; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_wflags_0 = slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_wflags = slot_uop_fp_ctrl_wflags; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_vec; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_vec_0 = slot_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_vec = slot_uop_fp_ctrl_vec; // @[util.scala:104:23]
reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_rob_idx = slot_uop_rob_idx; // @[util.scala:104:23]
reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_ldq_idx = slot_uop_ldq_idx; // @[util.scala:104:23]
reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_stq_idx = slot_uop_stq_idx; // @[util.scala:104:23]
reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_rxq_idx = slot_uop_rxq_idx; // @[util.scala:104:23]
reg [6:0] slot_uop_pdst; // @[issue-slot.scala:56:21]
assign io_iss_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_pdst = slot_uop_pdst; // @[util.scala:104:23]
reg [6:0] slot_uop_prs1; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_prs1 = slot_uop_prs1; // @[util.scala:104:23]
reg [6:0] slot_uop_prs2; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_prs2 = slot_uop_prs2; // @[util.scala:104:23]
reg [6:0] slot_uop_prs3; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_prs3 = slot_uop_prs3; // @[util.scala:104:23]
reg [4:0] slot_uop_ppred; // @[issue-slot.scala:56:21]
assign io_iss_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_ppred = slot_uop_ppred; // @[util.scala:104:23]
reg slot_uop_prs1_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_prs1_busy = slot_uop_prs1_busy; // @[util.scala:104:23]
reg slot_uop_prs2_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_prs2_busy = slot_uop_prs2_busy; // @[util.scala:104:23]
reg slot_uop_prs3_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_prs3_busy = slot_uop_prs3_busy; // @[util.scala:104:23]
reg slot_uop_ppred_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_ppred_busy = slot_uop_ppred_busy; // @[util.scala:104:23]
wire _iss_ready_T_3 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :136:88]
wire _agen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :137:95]
wire _dgen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :138:95]
reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:56:21]
assign io_iss_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_stale_pdst = slot_uop_stale_pdst; // @[util.scala:104:23]
reg slot_uop_exception; // @[issue-slot.scala:56:21]
assign io_iss_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_exception = slot_uop_exception; // @[util.scala:104:23]
reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:56:21]
assign io_iss_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:49:7, :56:21]
wire [63:0] next_uop_out_exc_cause = slot_uop_exc_cause; // @[util.scala:104:23]
reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:56:21]
assign io_iss_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_mem_cmd = slot_uop_mem_cmd; // @[util.scala:104:23]
reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:56:21]
assign io_iss_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_mem_size = slot_uop_mem_size; // @[util.scala:104:23]
reg slot_uop_mem_signed; // @[issue-slot.scala:56:21]
assign io_iss_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_mem_signed = slot_uop_mem_signed; // @[util.scala:104:23]
reg slot_uop_uses_ldq; // @[issue-slot.scala:56:21]
assign io_iss_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_uses_ldq = slot_uop_uses_ldq; // @[util.scala:104:23]
reg slot_uop_uses_stq; // @[issue-slot.scala:56:21]
assign io_iss_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_uses_stq = slot_uop_uses_stq; // @[util.scala:104:23]
reg slot_uop_is_unique; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_unique = slot_uop_is_unique; // @[util.scala:104:23]
reg slot_uop_flush_on_commit; // @[issue-slot.scala:56:21]
assign io_iss_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_flush_on_commit = slot_uop_flush_on_commit; // @[util.scala:104:23]
reg [2:0] slot_uop_csr_cmd; // @[issue-slot.scala:56:21]
assign io_iss_uop_csr_cmd_0 = slot_uop_csr_cmd; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_csr_cmd = slot_uop_csr_cmd; // @[util.scala:104:23]
reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:56:21]
assign io_iss_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_ldst_is_rs1 = slot_uop_ldst_is_rs1; // @[util.scala:104:23]
reg [5:0] slot_uop_ldst; // @[issue-slot.scala:56:21]
assign io_iss_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_ldst = slot_uop_ldst; // @[util.scala:104:23]
reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_lrs1 = slot_uop_lrs1; // @[util.scala:104:23]
reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_lrs2 = slot_uop_lrs2; // @[util.scala:104:23]
reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_lrs3 = slot_uop_lrs3; // @[util.scala:104:23]
reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:56:21]
assign io_iss_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_dst_rtype = slot_uop_dst_rtype; // @[util.scala:104:23]
reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs1_rtype_0 = slot_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_lrs1_rtype = slot_uop_lrs1_rtype; // @[util.scala:104:23]
reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs2_rtype_0 = slot_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_lrs2_rtype = slot_uop_lrs2_rtype; // @[util.scala:104:23]
reg slot_uop_frs3_en; // @[issue-slot.scala:56:21]
assign io_iss_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_frs3_en = slot_uop_frs3_en; // @[util.scala:104:23]
reg slot_uop_fcn_dw; // @[issue-slot.scala:56:21]
assign io_iss_uop_fcn_dw_0 = slot_uop_fcn_dw; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fcn_dw = slot_uop_fcn_dw; // @[util.scala:104:23]
reg [4:0] slot_uop_fcn_op; // @[issue-slot.scala:56:21]
assign io_iss_uop_fcn_op_0 = slot_uop_fcn_op; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_fcn_op = slot_uop_fcn_op; // @[util.scala:104:23]
reg slot_uop_fp_val; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_val = slot_uop_fp_val; // @[util.scala:104:23]
reg [2:0] slot_uop_fp_rm; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_rm_0 = slot_uop_fp_rm; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_fp_rm = slot_uop_fp_rm; // @[util.scala:104:23]
reg [1:0] slot_uop_fp_typ; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_typ_0 = slot_uop_fp_typ; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_fp_typ = slot_uop_fp_typ; // @[util.scala:104:23]
reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_xcpt_pf_if = slot_uop_xcpt_pf_if; // @[util.scala:104:23]
reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_xcpt_ae_if = slot_uop_xcpt_ae_if; // @[util.scala:104:23]
reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_xcpt_ma_if = slot_uop_xcpt_ma_if; // @[util.scala:104:23]
reg slot_uop_bp_debug_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_bp_debug_if = slot_uop_bp_debug_if; // @[util.scala:104:23]
reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_bp_xcpt_if = slot_uop_bp_xcpt_if; // @[util.scala:104:23]
reg [2:0] slot_uop_debug_fsrc; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_debug_fsrc = slot_uop_debug_fsrc; // @[util.scala:104:23]
reg [2:0] slot_uop_debug_tsrc; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_debug_tsrc = slot_uop_debug_tsrc; // @[util.scala:104:23]
wire next_valid; // @[issue-slot.scala:58:28]
assign next_uop_inst = next_uop_out_inst; // @[util.scala:104:23]
assign next_uop_debug_inst = next_uop_out_debug_inst; // @[util.scala:104:23]
assign next_uop_is_rvc = next_uop_out_is_rvc; // @[util.scala:104:23]
assign next_uop_debug_pc = next_uop_out_debug_pc; // @[util.scala:104:23]
assign next_uop_iq_type_0 = next_uop_out_iq_type_0; // @[util.scala:104:23]
assign next_uop_iq_type_1 = next_uop_out_iq_type_1; // @[util.scala:104:23]
assign next_uop_iq_type_2 = next_uop_out_iq_type_2; // @[util.scala:104:23]
assign next_uop_iq_type_3 = next_uop_out_iq_type_3; // @[util.scala:104:23]
assign next_uop_fu_code_0 = next_uop_out_fu_code_0; // @[util.scala:104:23]
assign next_uop_fu_code_1 = next_uop_out_fu_code_1; // @[util.scala:104:23]
assign next_uop_fu_code_2 = next_uop_out_fu_code_2; // @[util.scala:104:23]
assign next_uop_fu_code_3 = next_uop_out_fu_code_3; // @[util.scala:104:23]
assign next_uop_fu_code_4 = next_uop_out_fu_code_4; // @[util.scala:104:23]
assign next_uop_fu_code_5 = next_uop_out_fu_code_5; // @[util.scala:104:23]
assign next_uop_fu_code_6 = next_uop_out_fu_code_6; // @[util.scala:104:23]
assign next_uop_fu_code_7 = next_uop_out_fu_code_7; // @[util.scala:104:23]
assign next_uop_fu_code_8 = next_uop_out_fu_code_8; // @[util.scala:104:23]
assign next_uop_fu_code_9 = next_uop_out_fu_code_9; // @[util.scala:104:23]
wire [15:0] _next_uop_out_br_mask_T_1; // @[util.scala:93:25]
assign next_uop_dis_col_sel = next_uop_out_dis_col_sel; // @[util.scala:104:23]
assign next_uop_br_mask = next_uop_out_br_mask; // @[util.scala:104:23]
assign next_uop_br_tag = next_uop_out_br_tag; // @[util.scala:104:23]
assign next_uop_br_type = next_uop_out_br_type; // @[util.scala:104:23]
assign next_uop_is_sfb = next_uop_out_is_sfb; // @[util.scala:104:23]
assign next_uop_is_fence = next_uop_out_is_fence; // @[util.scala:104:23]
assign next_uop_is_fencei = next_uop_out_is_fencei; // @[util.scala:104:23]
assign next_uop_is_sfence = next_uop_out_is_sfence; // @[util.scala:104:23]
assign next_uop_is_amo = next_uop_out_is_amo; // @[util.scala:104:23]
assign next_uop_is_eret = next_uop_out_is_eret; // @[util.scala:104:23]
assign next_uop_is_sys_pc2epc = next_uop_out_is_sys_pc2epc; // @[util.scala:104:23]
assign next_uop_is_rocc = next_uop_out_is_rocc; // @[util.scala:104:23]
assign next_uop_is_mov = next_uop_out_is_mov; // @[util.scala:104:23]
assign next_uop_ftq_idx = next_uop_out_ftq_idx; // @[util.scala:104:23]
assign next_uop_edge_inst = next_uop_out_edge_inst; // @[util.scala:104:23]
assign next_uop_pc_lob = next_uop_out_pc_lob; // @[util.scala:104:23]
assign next_uop_taken = next_uop_out_taken; // @[util.scala:104:23]
assign next_uop_imm_rename = next_uop_out_imm_rename; // @[util.scala:104:23]
assign next_uop_imm_sel = next_uop_out_imm_sel; // @[util.scala:104:23]
assign next_uop_pimm = next_uop_out_pimm; // @[util.scala:104:23]
assign next_uop_imm_packed = next_uop_out_imm_packed; // @[util.scala:104:23]
assign next_uop_op1_sel = next_uop_out_op1_sel; // @[util.scala:104:23]
assign next_uop_op2_sel = next_uop_out_op2_sel; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ldst = next_uop_out_fp_ctrl_ldst; // @[util.scala:104:23]
assign next_uop_fp_ctrl_wen = next_uop_out_fp_ctrl_wen; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ren1 = next_uop_out_fp_ctrl_ren1; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ren2 = next_uop_out_fp_ctrl_ren2; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ren3 = next_uop_out_fp_ctrl_ren3; // @[util.scala:104:23]
assign next_uop_fp_ctrl_swap12 = next_uop_out_fp_ctrl_swap12; // @[util.scala:104:23]
assign next_uop_fp_ctrl_swap23 = next_uop_out_fp_ctrl_swap23; // @[util.scala:104:23]
assign next_uop_fp_ctrl_typeTagIn = next_uop_out_fp_ctrl_typeTagIn; // @[util.scala:104:23]
assign next_uop_fp_ctrl_typeTagOut = next_uop_out_fp_ctrl_typeTagOut; // @[util.scala:104:23]
assign next_uop_fp_ctrl_fromint = next_uop_out_fp_ctrl_fromint; // @[util.scala:104:23]
assign next_uop_fp_ctrl_toint = next_uop_out_fp_ctrl_toint; // @[util.scala:104:23]
assign next_uop_fp_ctrl_fastpipe = next_uop_out_fp_ctrl_fastpipe; // @[util.scala:104:23]
assign next_uop_fp_ctrl_fma = next_uop_out_fp_ctrl_fma; // @[util.scala:104:23]
assign next_uop_fp_ctrl_div = next_uop_out_fp_ctrl_div; // @[util.scala:104:23]
assign next_uop_fp_ctrl_sqrt = next_uop_out_fp_ctrl_sqrt; // @[util.scala:104:23]
assign next_uop_fp_ctrl_wflags = next_uop_out_fp_ctrl_wflags; // @[util.scala:104:23]
assign next_uop_fp_ctrl_vec = next_uop_out_fp_ctrl_vec; // @[util.scala:104:23]
assign next_uop_rob_idx = next_uop_out_rob_idx; // @[util.scala:104:23]
assign next_uop_ldq_idx = next_uop_out_ldq_idx; // @[util.scala:104:23]
assign next_uop_stq_idx = next_uop_out_stq_idx; // @[util.scala:104:23]
assign next_uop_rxq_idx = next_uop_out_rxq_idx; // @[util.scala:104:23]
assign next_uop_pdst = next_uop_out_pdst; // @[util.scala:104:23]
assign next_uop_prs1 = next_uop_out_prs1; // @[util.scala:104:23]
assign next_uop_prs2 = next_uop_out_prs2; // @[util.scala:104:23]
assign next_uop_prs3 = next_uop_out_prs3; // @[util.scala:104:23]
assign next_uop_ppred = next_uop_out_ppred; // @[util.scala:104:23]
assign next_uop_stale_pdst = next_uop_out_stale_pdst; // @[util.scala:104:23]
assign next_uop_exception = next_uop_out_exception; // @[util.scala:104:23]
assign next_uop_exc_cause = next_uop_out_exc_cause; // @[util.scala:104:23]
assign next_uop_mem_cmd = next_uop_out_mem_cmd; // @[util.scala:104:23]
assign next_uop_mem_size = next_uop_out_mem_size; // @[util.scala:104:23]
assign next_uop_mem_signed = next_uop_out_mem_signed; // @[util.scala:104:23]
assign next_uop_uses_ldq = next_uop_out_uses_ldq; // @[util.scala:104:23]
assign next_uop_uses_stq = next_uop_out_uses_stq; // @[util.scala:104:23]
assign next_uop_is_unique = next_uop_out_is_unique; // @[util.scala:104:23]
assign next_uop_flush_on_commit = next_uop_out_flush_on_commit; // @[util.scala:104:23]
assign next_uop_csr_cmd = next_uop_out_csr_cmd; // @[util.scala:104:23]
assign next_uop_ldst_is_rs1 = next_uop_out_ldst_is_rs1; // @[util.scala:104:23]
assign next_uop_ldst = next_uop_out_ldst; // @[util.scala:104:23]
assign next_uop_lrs1 = next_uop_out_lrs1; // @[util.scala:104:23]
assign next_uop_lrs2 = next_uop_out_lrs2; // @[util.scala:104:23]
assign next_uop_lrs3 = next_uop_out_lrs3; // @[util.scala:104:23]
assign next_uop_dst_rtype = next_uop_out_dst_rtype; // @[util.scala:104:23]
assign next_uop_lrs1_rtype = next_uop_out_lrs1_rtype; // @[util.scala:104:23]
assign next_uop_lrs2_rtype = next_uop_out_lrs2_rtype; // @[util.scala:104:23]
assign next_uop_frs3_en = next_uop_out_frs3_en; // @[util.scala:104:23]
assign next_uop_fcn_dw = next_uop_out_fcn_dw; // @[util.scala:104:23]
assign next_uop_fcn_op = next_uop_out_fcn_op; // @[util.scala:104:23]
assign next_uop_fp_val = next_uop_out_fp_val; // @[util.scala:104:23]
assign next_uop_fp_rm = next_uop_out_fp_rm; // @[util.scala:104:23]
assign next_uop_fp_typ = next_uop_out_fp_typ; // @[util.scala:104:23]
assign next_uop_xcpt_pf_if = next_uop_out_xcpt_pf_if; // @[util.scala:104:23]
assign next_uop_xcpt_ae_if = next_uop_out_xcpt_ae_if; // @[util.scala:104:23]
assign next_uop_xcpt_ma_if = next_uop_out_xcpt_ma_if; // @[util.scala:104:23]
assign next_uop_bp_debug_if = next_uop_out_bp_debug_if; // @[util.scala:104:23]
assign next_uop_bp_xcpt_if = next_uop_out_bp_xcpt_if; // @[util.scala:104:23]
assign next_uop_debug_fsrc = next_uop_out_debug_fsrc; // @[util.scala:104:23]
assign next_uop_debug_tsrc = next_uop_out_debug_tsrc; // @[util.scala:104:23]
wire [15:0] _next_uop_out_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:93:27]
assign _next_uop_out_br_mask_T_1 = slot_uop_br_mask & _next_uop_out_br_mask_T; // @[util.scala:93:{25,27}]
assign next_uop_out_br_mask = _next_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23]
assign io_out_uop_inst_0 = next_uop_inst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_inst_0 = next_uop_debug_inst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_rvc_0 = next_uop_is_rvc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_pc_0 = next_uop_debug_pc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_0_0 = next_uop_iq_type_0; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_1_0 = next_uop_iq_type_1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_2_0 = next_uop_iq_type_2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_3_0 = next_uop_iq_type_3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_0_0 = next_uop_fu_code_0; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_1_0 = next_uop_fu_code_1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_2_0 = next_uop_fu_code_2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_3_0 = next_uop_fu_code_3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_4_0 = next_uop_fu_code_4; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_5_0 = next_uop_fu_code_5; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_6_0 = next_uop_fu_code_6; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_7_0 = next_uop_fu_code_7; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_8_0 = next_uop_fu_code_8; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_9_0 = next_uop_fu_code_9; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_issued_0 = next_uop_iw_issued; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p1_speculative_child_0 = next_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p2_speculative_child_0 = next_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p1_bypass_hint_0 = next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p2_bypass_hint_0 = next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p3_bypass_hint_0 = next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_dis_col_sel_0 = next_uop_dis_col_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_br_mask_0 = next_uop_br_mask; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_br_tag_0 = next_uop_br_tag; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_br_type_0 = next_uop_br_type; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_sfb_0 = next_uop_is_sfb; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_fence_0 = next_uop_is_fence; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_fencei_0 = next_uop_is_fencei; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_sfence_0 = next_uop_is_sfence; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_amo_0 = next_uop_is_amo; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_eret_0 = next_uop_is_eret; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_sys_pc2epc_0 = next_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_rocc_0 = next_uop_is_rocc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_mov_0 = next_uop_is_mov; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ftq_idx_0 = next_uop_ftq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_edge_inst_0 = next_uop_edge_inst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_pc_lob_0 = next_uop_pc_lob; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_taken_0 = next_uop_taken; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_imm_rename_0 = next_uop_imm_rename; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_imm_sel_0 = next_uop_imm_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_pimm_0 = next_uop_pimm; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_imm_packed_0 = next_uop_imm_packed; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_op1_sel_0 = next_uop_op1_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_op2_sel_0 = next_uop_op2_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ldst_0 = next_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_wen_0 = next_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ren1_0 = next_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ren2_0 = next_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ren3_0 = next_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_swap12_0 = next_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_swap23_0 = next_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_typeTagIn_0 = next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_typeTagOut_0 = next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_fromint_0 = next_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_toint_0 = next_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_fastpipe_0 = next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_fma_0 = next_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_div_0 = next_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_sqrt_0 = next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_wflags_0 = next_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_vec_0 = next_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_rob_idx_0 = next_uop_rob_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ldq_idx_0 = next_uop_ldq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_stq_idx_0 = next_uop_stq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_rxq_idx_0 = next_uop_rxq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_pdst_0 = next_uop_pdst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs1_0 = next_uop_prs1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs2_0 = next_uop_prs2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs3_0 = next_uop_prs3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ppred_0 = next_uop_ppred; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs1_busy_0 = next_uop_prs1_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs2_busy_0 = next_uop_prs2_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs3_busy_0 = next_uop_prs3_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ppred_busy_0 = next_uop_ppred_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_stale_pdst_0 = next_uop_stale_pdst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_exception_0 = next_uop_exception; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_exc_cause_0 = next_uop_exc_cause; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_mem_cmd_0 = next_uop_mem_cmd; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_mem_size_0 = next_uop_mem_size; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_mem_signed_0 = next_uop_mem_signed; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_uses_ldq_0 = next_uop_uses_ldq; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_uses_stq_0 = next_uop_uses_stq; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_unique_0 = next_uop_is_unique; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_flush_on_commit_0 = next_uop_flush_on_commit; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_csr_cmd_0 = next_uop_csr_cmd; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ldst_is_rs1_0 = next_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ldst_0 = next_uop_ldst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs1_0 = next_uop_lrs1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs2_0 = next_uop_lrs2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs3_0 = next_uop_lrs3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_dst_rtype_0 = next_uop_dst_rtype; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs1_rtype_0 = next_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs2_rtype_0 = next_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_frs3_en_0 = next_uop_frs3_en; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fcn_dw_0 = next_uop_fcn_dw; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fcn_op_0 = next_uop_fcn_op; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_val_0 = next_uop_fp_val; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_rm_0 = next_uop_fp_rm; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_typ_0 = next_uop_fp_typ; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_xcpt_pf_if_0 = next_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_xcpt_ae_if_0 = next_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_xcpt_ma_if_0 = next_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_bp_debug_if_0 = next_uop_bp_debug_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_bp_xcpt_if_0 = next_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_fsrc_0 = next_uop_debug_fsrc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_tsrc_0 = next_uop_debug_tsrc; // @[issue-slot.scala:49:7, :59:28]
wire [15:0] _killed_T = io_brupdate_b1_mispredict_mask_0 & slot_uop_br_mask; // @[util.scala:126:51]
wire _killed_T_1 = |_killed_T; // @[util.scala:126:{51,59}]
wire killed = _killed_T_1 | io_kill_0; // @[util.scala:61:61, :126:59]
wire _io_will_be_valid_T = ~killed; // @[util.scala:61:61]
assign _io_will_be_valid_T_1 = next_valid & _io_will_be_valid_T; // @[issue-slot.scala:58:28, :65:{34,37}]
assign io_will_be_valid_0 = _io_will_be_valid_T_1; // @[issue-slot.scala:49:7, :65:34]
wire _slot_valid_T = ~killed; // @[util.scala:61:61]
wire _slot_valid_T_1 = next_valid & _slot_valid_T; // @[issue-slot.scala:58:28, :74:{30,33}] |
Generate the Verilog code corresponding to the following Chisel files.
File Crossing.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.interrupts
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.util.{SynchronizerShiftReg, AsyncResetReg}
@deprecated("IntXing does not ensure interrupt source is glitch free. Use IntSyncSource and IntSyncSink", "rocket-chip 1.2")
class IntXing(sync: Int = 3)(implicit p: Parameters) extends LazyModule
{
val intnode = IntAdapterNode()
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
(intnode.in zip intnode.out) foreach { case ((in, _), (out, _)) =>
out := SynchronizerShiftReg(in, sync)
}
}
}
object IntSyncCrossingSource
{
def apply(alreadyRegistered: Boolean = false)(implicit p: Parameters) =
{
val intsource = LazyModule(new IntSyncCrossingSource(alreadyRegistered))
intsource.node
}
}
class IntSyncCrossingSource(alreadyRegistered: Boolean = false)(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSourceNode(alreadyRegistered)
lazy val module = if (alreadyRegistered) (new ImplRegistered) else (new Impl)
class Impl extends LazyModuleImp(this) {
def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0)
override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out.sync := AsyncResetReg(Cat(in.reverse)).asBools
}
}
class ImplRegistered extends LazyRawModuleImp(this) {
def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0)
override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}_Registered"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out.sync := in
}
}
}
object IntSyncCrossingSink
{
@deprecated("IntSyncCrossingSink which used the `sync` parameter to determine crossing type is deprecated. Use IntSyncAsyncCrossingSink, IntSyncRationalCrossingSink, or IntSyncSyncCrossingSink instead for > 1, 1, and 0 sync values respectively", "rocket-chip 1.2")
def apply(sync: Int = 3)(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync))
intsink.node
}
}
class IntSyncAsyncCrossingSink(sync: Int = 3)(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSinkNode(sync)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
override def desiredName = s"IntSyncAsyncCrossingSink_n${node.out.size}x${node.out.head._1.size}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out := SynchronizerShiftReg(in.sync, sync)
}
}
}
object IntSyncAsyncCrossingSink
{
def apply(sync: Int = 3)(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync))
intsink.node
}
}
class IntSyncSyncCrossingSink()(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSinkNode(0)
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
def outSize = node.out.headOption.map(_._1.size).getOrElse(0)
override def desiredName = s"IntSyncSyncCrossingSink_n${node.out.size}x${outSize}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out := in.sync
}
}
}
object IntSyncSyncCrossingSink
{
def apply()(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncSyncCrossingSink())
intsink.node
}
}
class IntSyncRationalCrossingSink()(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSinkNode(1)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
def outSize = node.out.headOption.map(_._1.size).getOrElse(0)
override def desiredName = s"IntSyncRationalCrossingSink_n${node.out.size}x${outSize}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out := RegNext(in.sync)
}
}
}
object IntSyncRationalCrossingSink
{
def apply()(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncRationalCrossingSink())
intsink.node
}
}
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
File AsyncResetReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
/** This black-boxes an Async Reset
* (or Set)
* Register.
*
* Because Chisel doesn't support
* parameterized black boxes,
* we unfortunately have to
* instantiate a number of these.
*
* We also have to hard-code the set/
* reset behavior.
*
* Do not confuse an asynchronous
* reset signal with an asynchronously
* reset reg. You should still
* properly synchronize your reset
* deassertion.
*
* @param d Data input
* @param q Data Output
* @param clk Clock Input
* @param rst Reset Input
* @param en Write Enable Input
*
*/
class AsyncResetReg(resetValue: Int = 0) extends RawModule {
val io = IO(new Bundle {
val d = Input(Bool())
val q = Output(Bool())
val en = Input(Bool())
val clk = Input(Clock())
val rst = Input(Reset())
})
val reg = withClockAndReset(io.clk, io.rst.asAsyncReset)(RegInit(resetValue.U(1.W)))
when (io.en) {
reg := io.d
}
io.q := reg
}
class SimpleRegIO(val w: Int) extends Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
}
class AsyncResetRegVec(val w: Int, val init: BigInt) extends Module {
override def desiredName = s"AsyncResetRegVec_w${w}_i${init}"
val io = IO(new SimpleRegIO(w))
val reg = withReset(reset.asAsyncReset)(RegInit(init.U(w.W)))
when (io.en) {
reg := io.d
}
io.q := reg
}
object AsyncResetReg {
// Create Single Registers
def apply(d: Bool, clk: Clock, rst: Bool, init: Boolean, name: Option[String]): Bool = {
val reg = Module(new AsyncResetReg(if (init) 1 else 0))
reg.io.d := d
reg.io.clk := clk
reg.io.rst := rst
reg.io.en := true.B
name.foreach(reg.suggestName(_))
reg.io.q
}
def apply(d: Bool, clk: Clock, rst: Bool): Bool = apply(d, clk, rst, false, None)
def apply(d: Bool, clk: Clock, rst: Bool, name: String): Bool = apply(d, clk, rst, false, Some(name))
// Create Vectors of Registers
def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: Option[String] = None): UInt = {
val w = updateData.getWidth max resetData.bitLength
val reg = Module(new AsyncResetRegVec(w, resetData))
name.foreach(reg.suggestName(_))
reg.io.d := updateData
reg.io.en := enable
reg.io.q
}
def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: String): UInt = apply(updateData,
resetData, enable, Some(name))
def apply(updateData: UInt, resetData: BigInt): UInt = apply(updateData, resetData, enable = true.B)
def apply(updateData: UInt, resetData: BigInt, name: String): UInt = apply(updateData, resetData, enable = true.B, Some(name))
def apply(updateData: UInt, enable: Bool): UInt = apply(updateData, resetData=BigInt(0), enable)
def apply(updateData: UInt, enable: Bool, name: String): UInt = apply(updateData, resetData = BigInt(0), enable, Some(name))
def apply(updateData: UInt): UInt = apply(updateData, resetData = BigInt(0), enable = true.B)
def apply(updateData: UInt, name:String): UInt = apply(updateData, resetData = BigInt(0), enable = true.B, Some(name))
}
| module IntSyncCrossingSource_n1x2_13( // @[Crossing.scala:41:9]
input clock, // @[Crossing.scala:41:9]
input reset, // @[Crossing.scala:41:9]
input auto_in_0, // @[LazyModuleImp.scala:107:25]
input auto_in_1, // @[LazyModuleImp.scala:107:25]
output auto_out_sync_0, // @[LazyModuleImp.scala:107:25]
output auto_out_sync_1 // @[LazyModuleImp.scala:107:25]
);
wire [1:0] _reg_io_q; // @[AsyncResetReg.scala:86:21]
wire auto_in_0_0 = auto_in_0; // @[Crossing.scala:41:9]
wire auto_in_1_0 = auto_in_1; // @[Crossing.scala:41:9]
wire nodeIn_0 = auto_in_0_0; // @[Crossing.scala:41:9]
wire nodeIn_1 = auto_in_1_0; // @[Crossing.scala:41:9]
wire nodeOut_sync_0; // @[MixedNode.scala:542:17]
wire nodeOut_sync_1; // @[MixedNode.scala:542:17]
wire auto_out_sync_0_0; // @[Crossing.scala:41:9]
wire auto_out_sync_1_0; // @[Crossing.scala:41:9]
assign auto_out_sync_0_0 = nodeOut_sync_0; // @[Crossing.scala:41:9]
assign auto_out_sync_1_0 = nodeOut_sync_1; // @[Crossing.scala:41:9]
assign nodeOut_sync_0 = _reg_io_q[0]; // @[AsyncResetReg.scala:86:21]
assign nodeOut_sync_1 = _reg_io_q[1]; // @[AsyncResetReg.scala:86:21]
AsyncResetRegVec_w2_i0_13 reg_0 ( // @[AsyncResetReg.scala:86:21]
.clock (clock),
.reset (reset),
.io_d ({nodeIn_1, nodeIn_0}), // @[Crossing.scala:45:36]
.io_q (_reg_io_q)
); // @[AsyncResetReg.scala:86:21]
assign auto_out_sync_0 = auto_out_sync_0_0; // @[Crossing.scala:41:9]
assign auto_out_sync_1 = auto_out_sync_1_0; // @[Crossing.scala:41:9]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
| module ClockCrossingReg_w32_TestHarness_UNIQUIFIED( // @[SynchronizerReg.scala:191:7]
input clock, // @[SynchronizerReg.scala:191:7]
input [31:0] io_d, // @[SynchronizerReg.scala:195:14]
output [31:0] io_q, // @[SynchronizerReg.scala:195:14]
input io_en // @[SynchronizerReg.scala:195:14]
);
reg [31:0] cdc_reg; // @[SynchronizerReg.scala:201:76]
always @(posedge clock) begin // @[SynchronizerReg.scala:191:7]
if (io_en) // @[SynchronizerReg.scala:195:14]
cdc_reg <= io_d; // @[SynchronizerReg.scala:201:76]
always @(posedge) |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File AsyncQueue.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
case class AsyncQueueParams(
depth: Int = 8,
sync: Int = 3,
safe: Boolean = true,
// If safe is true, then effort is made to resynchronize the crossing indices when either side is reset.
// This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty.
narrow: Boolean = false)
// If narrow is true then the read mux is moved to the source side of the crossing.
// This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing,
// at the expense of a combinational path from the sink to the source and back to the sink.
{
require (depth > 0 && isPow2(depth))
require (sync >= 2)
val bits = log2Ceil(depth)
val wires = if (narrow) 1 else depth
}
object AsyncQueueParams {
// When there is only one entry, we don't need narrow.
def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false)
}
class AsyncBundleSafety extends Bundle {
val ridx_valid = Input (Bool())
val widx_valid = Output(Bool())
val source_reset_n = Output(Bool())
val sink_reset_n = Input (Bool())
}
class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle {
// Data-path synchronization
val mem = Output(Vec(params.wires, gen))
val ridx = Input (UInt((params.bits+1).W))
val widx = Output(UInt((params.bits+1).W))
val index = params.narrow.option(Input(UInt(params.bits.W)))
// Signals used to self-stabilize a safe AsyncQueue
val safe = params.safe.option(new AsyncBundleSafety)
}
object GrayCounter {
def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = {
val incremented = Wire(UInt(bits.W))
val binary = RegNext(next=incremented, init=0.U).suggestName(name)
incremented := Mux(clear, 0.U, binary + increment.asUInt)
incremented ^ (incremented >> 1)
}
}
class AsyncValidSync(sync: Int, desc: String) extends RawModule {
val io = IO(new Bundle {
val in = Input(Bool())
val out = Output(Bool())
})
val clock = IO(Input(Clock()))
val reset = IO(Input(AsyncReset()))
withClockAndReset(clock, reset){
io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc))
}
}
class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSource_${gen.typeName}"
val io = IO(new Bundle {
// These come from the source domain
val enq = Flipped(Decoupled(gen))
// These cross to the sink clock domain
val async = new AsyncBundle(gen, params)
})
val bits = params.bits
val sink_ready = WireInit(true.B)
val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all.
val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin"))
val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray"))
val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U)
val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1))
when (io.enq.fire) { mem(index) := io.enq.bits }
val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg"))
io.enq.ready := ready_reg && sink_ready
val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray"))
io.async.widx := widx_reg
io.async.index match {
case Some(index) => io.async.mem(0) := mem(index)
case None => io.async.mem := mem
}
io.async.safe.foreach { sio =>
val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0"))
val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1"))
val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend"))
val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid"))
source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_valid .reset := reset.asAsyncReset
source_valid_0.clock := clock
source_valid_1.clock := clock
sink_extend .clock := clock
sink_valid .clock := clock
source_valid_0.io.in := true.B
source_valid_1.io.in := source_valid_0.io.out
sio.widx_valid := source_valid_1.io.out
sink_extend.io.in := sio.ridx_valid
sink_valid.io.in := sink_extend.io.out
sink_ready := sink_valid.io.out
sio.source_reset_n := !reset.asBool
// Assert that if there is stuff in the queue, then reset cannot happen
// Impossible to write because dequeue can occur on the receiving side,
// then reset allowed to happen, but write side cannot know that dequeue
// occurred.
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
// assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected")
// assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty")
}
}
class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSink_${gen.typeName}"
val io = IO(new Bundle {
// These come from the sink domain
val deq = Decoupled(gen)
// These cross to the source clock domain
val async = Flipped(new AsyncBundle(gen, params))
})
val bits = params.bits
val source_ready = WireInit(true.B)
val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin"))
val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray"))
val valid = source_ready && ridx =/= widx
// The mux is safe because timing analysis ensures ridx has reached the register
// On an ASIC, changes to the unread location cannot affect the selected value
// On an FPGA, only one input changes at a time => mem updates don't cause glitches
// The register only latches when the selected valued is not being written
val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1))
io.async.index.foreach { _ := index }
// This register does not NEED to be reset, as its contents will not
// be considered unless the asynchronously reset deq valid register is set.
// It is possible that bits latches when the source domain is reset / has power cut
// This is safe, because isolation gates brought mem low before the zeroed widx reached us
val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index)
io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg"))
val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg"))
io.deq.valid := valid_reg && source_ready
val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray"))
io.async.ridx := ridx_reg
io.async.safe.foreach { sio =>
val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0"))
val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1"))
val source_extend = Module(new AsyncValidSync(params.sync, "source_extend"))
val source_valid = Module(new AsyncValidSync(params.sync, "source_valid"))
sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_valid .reset := reset.asAsyncReset
sink_valid_0 .clock := clock
sink_valid_1 .clock := clock
source_extend.clock := clock
source_valid .clock := clock
sink_valid_0.io.in := true.B
sink_valid_1.io.in := sink_valid_0.io.out
sio.ridx_valid := sink_valid_1.io.out
source_extend.io.in := sio.widx_valid
source_valid.io.in := source_extend.io.out
source_ready := source_valid.io.out
sio.sink_reset_n := !reset.asBool
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
//
// val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool
// val reset_and_extend_prev = RegNext(reset_and_extend, true.B)
// val reset_rise = !reset_and_extend_prev && reset_and_extend
// val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0)
// assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty")
}
}
object FromAsyncBundle
{
// Sometimes it makes sense for the sink to have different sync than the source
def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync)
def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = {
val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync)))
sink.io.async <> x
sink.io.deq
}
}
object ToAsyncBundle
{
def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = {
val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params))
source.io.enq <> x
source.io.async
}
}
class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] {
val io = IO(new CrossingIO(gen))
val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) }
val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) }
source.io.enq <> io.enq
io.deq <> sink.io.deq
sink.io.async <> source.io.async
}
| module AsyncValidSync_68( // @[AsyncQueue.scala:58:7]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in = 1'h1; // @[ShiftReg.scala:45:23]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_68 io_out_source_valid_0 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Crossing.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.interrupts
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.util.{SynchronizerShiftReg, AsyncResetReg}
@deprecated("IntXing does not ensure interrupt source is glitch free. Use IntSyncSource and IntSyncSink", "rocket-chip 1.2")
class IntXing(sync: Int = 3)(implicit p: Parameters) extends LazyModule
{
val intnode = IntAdapterNode()
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
(intnode.in zip intnode.out) foreach { case ((in, _), (out, _)) =>
out := SynchronizerShiftReg(in, sync)
}
}
}
object IntSyncCrossingSource
{
def apply(alreadyRegistered: Boolean = false)(implicit p: Parameters) =
{
val intsource = LazyModule(new IntSyncCrossingSource(alreadyRegistered))
intsource.node
}
}
class IntSyncCrossingSource(alreadyRegistered: Boolean = false)(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSourceNode(alreadyRegistered)
lazy val module = if (alreadyRegistered) (new ImplRegistered) else (new Impl)
class Impl extends LazyModuleImp(this) {
def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0)
override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out.sync := AsyncResetReg(Cat(in.reverse)).asBools
}
}
class ImplRegistered extends LazyRawModuleImp(this) {
def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0)
override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}_Registered"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out.sync := in
}
}
}
object IntSyncCrossingSink
{
@deprecated("IntSyncCrossingSink which used the `sync` parameter to determine crossing type is deprecated. Use IntSyncAsyncCrossingSink, IntSyncRationalCrossingSink, or IntSyncSyncCrossingSink instead for > 1, 1, and 0 sync values respectively", "rocket-chip 1.2")
def apply(sync: Int = 3)(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync))
intsink.node
}
}
class IntSyncAsyncCrossingSink(sync: Int = 3)(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSinkNode(sync)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
override def desiredName = s"IntSyncAsyncCrossingSink_n${node.out.size}x${node.out.head._1.size}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out := SynchronizerShiftReg(in.sync, sync)
}
}
}
object IntSyncAsyncCrossingSink
{
def apply(sync: Int = 3)(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync))
intsink.node
}
}
class IntSyncSyncCrossingSink()(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSinkNode(0)
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
def outSize = node.out.headOption.map(_._1.size).getOrElse(0)
override def desiredName = s"IntSyncSyncCrossingSink_n${node.out.size}x${outSize}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out := in.sync
}
}
}
object IntSyncSyncCrossingSink
{
def apply()(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncSyncCrossingSink())
intsink.node
}
}
class IntSyncRationalCrossingSink()(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSinkNode(1)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
def outSize = node.out.headOption.map(_._1.size).getOrElse(0)
override def desiredName = s"IntSyncRationalCrossingSink_n${node.out.size}x${outSize}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out := RegNext(in.sync)
}
}
}
object IntSyncRationalCrossingSink
{
def apply()(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncRationalCrossingSink())
intsink.node
}
}
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
| module IntSyncSyncCrossingSink_n0x0_1(); // @[Crossing.scala:96:9]
wire childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File AsyncQueue.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
case class AsyncQueueParams(
depth: Int = 8,
sync: Int = 3,
safe: Boolean = true,
// If safe is true, then effort is made to resynchronize the crossing indices when either side is reset.
// This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty.
narrow: Boolean = false)
// If narrow is true then the read mux is moved to the source side of the crossing.
// This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing,
// at the expense of a combinational path from the sink to the source and back to the sink.
{
require (depth > 0 && isPow2(depth))
require (sync >= 2)
val bits = log2Ceil(depth)
val wires = if (narrow) 1 else depth
}
object AsyncQueueParams {
// When there is only one entry, we don't need narrow.
def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false)
}
class AsyncBundleSafety extends Bundle {
val ridx_valid = Input (Bool())
val widx_valid = Output(Bool())
val source_reset_n = Output(Bool())
val sink_reset_n = Input (Bool())
}
class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle {
// Data-path synchronization
val mem = Output(Vec(params.wires, gen))
val ridx = Input (UInt((params.bits+1).W))
val widx = Output(UInt((params.bits+1).W))
val index = params.narrow.option(Input(UInt(params.bits.W)))
// Signals used to self-stabilize a safe AsyncQueue
val safe = params.safe.option(new AsyncBundleSafety)
}
object GrayCounter {
def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = {
val incremented = Wire(UInt(bits.W))
val binary = RegNext(next=incremented, init=0.U).suggestName(name)
incremented := Mux(clear, 0.U, binary + increment.asUInt)
incremented ^ (incremented >> 1)
}
}
class AsyncValidSync(sync: Int, desc: String) extends RawModule {
val io = IO(new Bundle {
val in = Input(Bool())
val out = Output(Bool())
})
val clock = IO(Input(Clock()))
val reset = IO(Input(AsyncReset()))
withClockAndReset(clock, reset){
io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc))
}
}
class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSource_${gen.typeName}"
val io = IO(new Bundle {
// These come from the source domain
val enq = Flipped(Decoupled(gen))
// These cross to the sink clock domain
val async = new AsyncBundle(gen, params)
})
val bits = params.bits
val sink_ready = WireInit(true.B)
val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all.
val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin"))
val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray"))
val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U)
val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1))
when (io.enq.fire) { mem(index) := io.enq.bits }
val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg"))
io.enq.ready := ready_reg && sink_ready
val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray"))
io.async.widx := widx_reg
io.async.index match {
case Some(index) => io.async.mem(0) := mem(index)
case None => io.async.mem := mem
}
io.async.safe.foreach { sio =>
val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0"))
val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1"))
val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend"))
val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid"))
source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_valid .reset := reset.asAsyncReset
source_valid_0.clock := clock
source_valid_1.clock := clock
sink_extend .clock := clock
sink_valid .clock := clock
source_valid_0.io.in := true.B
source_valid_1.io.in := source_valid_0.io.out
sio.widx_valid := source_valid_1.io.out
sink_extend.io.in := sio.ridx_valid
sink_valid.io.in := sink_extend.io.out
sink_ready := sink_valid.io.out
sio.source_reset_n := !reset.asBool
// Assert that if there is stuff in the queue, then reset cannot happen
// Impossible to write because dequeue can occur on the receiving side,
// then reset allowed to happen, but write side cannot know that dequeue
// occurred.
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
// assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected")
// assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty")
}
}
class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSink_${gen.typeName}"
val io = IO(new Bundle {
// These come from the sink domain
val deq = Decoupled(gen)
// These cross to the source clock domain
val async = Flipped(new AsyncBundle(gen, params))
})
val bits = params.bits
val source_ready = WireInit(true.B)
val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin"))
val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray"))
val valid = source_ready && ridx =/= widx
// The mux is safe because timing analysis ensures ridx has reached the register
// On an ASIC, changes to the unread location cannot affect the selected value
// On an FPGA, only one input changes at a time => mem updates don't cause glitches
// The register only latches when the selected valued is not being written
val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1))
io.async.index.foreach { _ := index }
// This register does not NEED to be reset, as its contents will not
// be considered unless the asynchronously reset deq valid register is set.
// It is possible that bits latches when the source domain is reset / has power cut
// This is safe, because isolation gates brought mem low before the zeroed widx reached us
val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index)
io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg"))
val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg"))
io.deq.valid := valid_reg && source_ready
val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray"))
io.async.ridx := ridx_reg
io.async.safe.foreach { sio =>
val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0"))
val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1"))
val source_extend = Module(new AsyncValidSync(params.sync, "source_extend"))
val source_valid = Module(new AsyncValidSync(params.sync, "source_valid"))
sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_valid .reset := reset.asAsyncReset
sink_valid_0 .clock := clock
sink_valid_1 .clock := clock
source_extend.clock := clock
source_valid .clock := clock
sink_valid_0.io.in := true.B
sink_valid_1.io.in := sink_valid_0.io.out
sio.ridx_valid := sink_valid_1.io.out
source_extend.io.in := sio.widx_valid
source_valid.io.in := source_extend.io.out
source_ready := source_valid.io.out
sio.sink_reset_n := !reset.asBool
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
//
// val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool
// val reset_and_extend_prev = RegNext(reset_and_extend, true.B)
// val reset_rise = !reset_and_extend_prev && reset_and_extend
// val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0)
// assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty")
}
}
object FromAsyncBundle
{
// Sometimes it makes sense for the sink to have different sync than the source
def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync)
def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = {
val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync)))
sink.io.async <> x
sink.io.deq
}
}
object ToAsyncBundle
{
def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = {
val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params))
source.io.enq <> x
source.io.async
}
}
class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] {
val io = IO(new CrossingIO(gen))
val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) }
val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) }
source.io.enq <> io.enq
io.deq <> sink.io.deq
sink.io.async <> source.io.async
}
| module AsyncValidSync_53( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_63 io_out_sink_valid_1 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
| module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_215( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19]
wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to the following Chisel files.
File FIFOFixer.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.lazymodule._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.diplomacy.RegionType
import freechips.rocketchip.util.property
class TLFIFOFixer(policy: TLFIFOFixer.Policy = TLFIFOFixer.all)(implicit p: Parameters) extends LazyModule
{
private def fifoMap(seq: Seq[TLSlaveParameters]) = {
val (flatManagers, keepManagers) = seq.partition(policy)
// We need to be careful if one flatManager and one keepManager share an existing domain
// Erring on the side of caution, we will also flatten the keepManager in this case
val flatDomains = Set(flatManagers.flatMap(_.fifoId):_*) // => ID 0
val keepDomains = Set(keepManagers.flatMap(_.fifoId):_*) -- flatDomains // => IDs compacted
// Calculate what the FIFO domains look like after the fixer is applied
val flatMap = flatDomains.map { x => (x, 0) }.toMap
val keepMap = keepDomains.scanLeft((-1,0)) { case ((_,s),x) => (x, s+1) }.toMap
val map = flatMap ++ keepMap
val fixMap = seq.map { m => m.fifoId match {
case None => if (policy(m)) Some(0) else None
case Some(id) => Some(map(id)) // also flattens some who did not ask
} }
// Compress the FIFO domain space of those we are combining
val reMap = flatDomains.scanLeft((-1,-1)) { case ((_,s),x) => (x, s+1) }.toMap
val splatMap = seq.map { m => m.fifoId match {
case None => None
case Some(id) => reMap.lift(id)
} }
(fixMap, splatMap)
}
val node = new AdapterNode(TLImp)(
{ cp => cp },
{ mp =>
val (fixMap, _) = fifoMap(mp.managers)
mp.v1copy(managers = (fixMap zip mp.managers) map { case (id, m) => m.v1copy(fifoId = id) })
}) with TLFormatNode {
override def circuitIdentity = edges.in.map(_.client.clients.filter(c => c.requestFifo && c.sourceId.size > 1).size).sum == 0
}
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
val (fixMap, splatMap) = fifoMap(edgeOut.manager.managers)
// Do we need to serialize the request to this manager?
val a_notFIFO = edgeIn.manager.fastProperty(in.a.bits.address, _.fifoId != Some(0), (b:Boolean) => b.B)
// Compact the IDs of the cases we serialize
val compacted = ((fixMap zip splatMap) zip edgeOut.manager.managers) flatMap {
case ((f, s), m) => if (f == Some(0)) Some(m.v1copy(fifoId = s)) else None
}
val sinks = if (compacted.exists(_.supportsAcquireB)) edgeOut.manager.endSinkId else 0
val a_id = if (compacted.isEmpty) 0.U else
edgeOut.manager.v1copy(managers = compacted, endSinkId = sinks).findFifoIdFast(in.a.bits.address)
val a_noDomain = a_id === 0.U
if (false) {
println(s"FIFOFixer for: ${edgeIn.client.clients.map(_.name).mkString(", ")}")
println(s"make FIFO: ${edgeIn.manager.managers.filter(_.fifoId==Some(0)).map(_.name).mkString(", ")}")
println(s"not FIFO: ${edgeIn.manager.managers.filter(_.fifoId!=Some(0)).map(_.name).mkString(", ")}")
println(s"domains: ${compacted.groupBy(_.name).mapValues(_.map(_.fifoId))}")
println("")
}
// Count beats
val a_first = edgeIn.first(in.a)
val d_first = edgeOut.first(out.d) && out.d.bits.opcode =/= TLMessages.ReleaseAck
// Keep one bit for each source recording if there is an outstanding request that must be made FIFO
// Sources unused in the stall signal calculation should be pruned by DCE
val flight = RegInit(VecInit(Seq.fill(edgeIn.client.endSourceId) { false.B }))
when (a_first && in.a.fire) { flight(in.a.bits.source) := !a_notFIFO }
when (d_first && in.d.fire) { flight(in.d.bits.source) := false.B }
val stalls = edgeIn.client.clients.filter(c => c.requestFifo && c.sourceId.size > 1).map { c =>
val a_sel = c.sourceId.contains(in.a.bits.source)
val id = RegEnable(a_id, in.a.fire && a_sel && !a_notFIFO)
val track = flight.slice(c.sourceId.start, c.sourceId.end)
a_sel && a_first && track.reduce(_ || _) && (a_noDomain || id =/= a_id)
}
val stall = stalls.foldLeft(false.B)(_||_)
out.a <> in.a
in.d <> out.d
out.a.valid := in.a.valid && (a_notFIFO || !stall)
in.a.ready := out.a.ready && (a_notFIFO || !stall)
if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) {
in .b <> out.b
out.c <> in .c
out.e <> in .e
} else {
in.b.valid := false.B
in.c.ready := true.B
in.e.ready := true.B
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
}
//Functional cover properties
property.cover(in.a.valid && stall, "COVER FIFOFIXER STALL", "Cover: Stall occured for a valid transaction")
val SourceIdFIFOed = RegInit(0.U(edgeIn.client.endSourceId.W))
val SourceIdSet = WireDefault(0.U(edgeIn.client.endSourceId.W))
val SourceIdClear = WireDefault(0.U(edgeIn.client.endSourceId.W))
when (a_first && in.a.fire && !a_notFIFO) {
SourceIdSet := UIntToOH(in.a.bits.source)
}
when (d_first && in.d.fire) {
SourceIdClear := UIntToOH(in.d.bits.source)
}
SourceIdFIFOed := SourceIdFIFOed | SourceIdSet
val allIDs_FIFOed = SourceIdFIFOed===Fill(SourceIdFIFOed.getWidth, 1.U)
property.cover(allIDs_FIFOed, "COVER all sources", "Cover: FIFOFIXER covers all Source IDs")
//property.cover(flight.reduce(_ && _), "COVER full", "Cover: FIFO is full with all Source IDs")
property.cover(!(flight.reduce(_ || _)), "COVER empty", "Cover: FIFO is empty")
property.cover(SourceIdSet > 0.U, "COVER at least one push", "Cover: At least one Source ID is pushed")
property.cover(SourceIdClear > 0.U, "COVER at least one pop", "Cover: At least one Source ID is popped")
}
}
}
object TLFIFOFixer
{
// Which slaves should have their FIFOness combined?
// NOTE: this transformation is still only applied for masters with requestFifo
type Policy = TLSlaveParameters => Boolean
import RegionType._
val all: Policy = m => true
val allFIFO: Policy = m => m.fifoId.isDefined
val allVolatile: Policy = m => m.regionType <= VOLATILE
def apply(policy: Policy = all)(implicit p: Parameters): TLNode =
{
val fixer = LazyModule(new TLFIFOFixer(policy))
fixer.node
}
}
File Nodes.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection}
case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args))
object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
{
def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo)
def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo)
def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle)
def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle)
def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString)
override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = {
val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge)))
monitor.io.in := bundle
}
override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters =
pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })
override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters =
pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })
}
trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut]
case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode
case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode
case class TLAdapterNode(
clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s },
managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLJunctionNode(
clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters],
managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])(
implicit valName: ValName)
extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode
object TLNameNode {
def apply(name: ValName) = TLIdentityNode()(name)
def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLIdentityNode = apply(Some(name))
}
case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)()
object TLTempNode {
def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp"))
}
case class TLNexusNode(
clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters,
managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)(
implicit valName: ValName)
extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode
abstract class TLCustomNode(implicit valName: ValName)
extends CustomNode(TLImp) with TLFormatNode
// Asynchronous crossings
trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters]
object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle]
{
def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle)
def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString)
override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLAsyncAdapterNode(
clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s },
managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode
case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode
object TLAsyncNameNode {
def apply(name: ValName) = TLAsyncIdentityNode()(name)
def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLAsyncIdentityNode = apply(Some(name))
}
case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLAsyncImp)(
dFn = { p => TLAsyncClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain
case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName)
extends MixedAdapterNode(TLAsyncImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) },
uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut]
// Rationally related crossings
trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters]
object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle]
{
def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle)
def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */)
override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLRationalAdapterNode(
clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s },
managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode
case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode
object TLRationalNameNode {
def apply(name: ValName) = TLRationalIdentityNode()(name)
def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLRationalIdentityNode = apply(Some(name))
}
case class TLRationalSourceNode()(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLRationalImp)(
dFn = { p => TLRationalClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain
case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName)
extends MixedAdapterNode(TLRationalImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut]
// Credited version of TileLink channels
trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters]
object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle]
{
def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle)
def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString)
override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLCreditedAdapterNode(
clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s },
managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode
case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode
object TLCreditedNameNode {
def apply(name: ValName) = TLCreditedIdentityNode()(name)
def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLCreditedIdentityNode = apply(Some(name))
}
case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLCreditedImp)(
dFn = { p => TLCreditedClientPortParameters(delay, p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain
case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLCreditedImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut]
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLFIFOFixer( // @[FIFOFixer.scala:50:9]
input clock, // @[FIFOFixer.scala:50:9]
input reset, // @[FIFOFixer.scala:50:9]
output auto_anon_in_1_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_1_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_1_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_in_1_a_bits_size, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_1_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_in_1_a_bits_address, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_1_a_bits_user_amba_prot_bufferable, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_1_a_bits_user_amba_prot_modifiable, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_1_a_bits_user_amba_prot_readalloc, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_1_a_bits_user_amba_prot_writealloc, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_1_a_bits_user_amba_prot_privileged, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_1_a_bits_user_amba_prot_secure, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_1_a_bits_user_amba_prot_fetch, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_anon_in_1_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_in_1_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_1_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_1_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_1_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_in_1_d_bits_size, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_1_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_1_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_1_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_in_1_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_0_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_in_0_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_anon_in_0_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_in_0_a_bits_address, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_a_bits_user_amba_prot_bufferable, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_a_bits_user_amba_prot_modifiable, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_a_bits_user_amba_prot_readalloc, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_a_bits_user_amba_prot_writealloc, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_a_bits_user_amba_prot_privileged, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_a_bits_user_amba_prot_secure, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_a_bits_user_amba_prot_fetch, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_anon_in_0_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_in_0_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_0_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_in_0_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_anon_in_0_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_in_0_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_1_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_1_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_1_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_out_1_a_bits_size, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_1_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_anon_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_1_a_bits_user_amba_prot_bufferable, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_1_a_bits_user_amba_prot_modifiable, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_1_a_bits_user_amba_prot_readalloc, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_1_a_bits_user_amba_prot_writealloc, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_1_a_bits_user_amba_prot_privileged, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_1_a_bits_user_amba_prot_secure, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_1_a_bits_user_amba_prot_fetch, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_out_1_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_out_1_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_1_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_1_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_anon_out_1_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_out_1_d_bits_size, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_1_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_1_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_1_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_out_1_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_0_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_0_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_0_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_out_0_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_anon_out_0_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_anon_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_0_a_bits_user_amba_prot_bufferable, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_0_a_bits_user_amba_prot_modifiable, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_0_a_bits_user_amba_prot_readalloc, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_0_a_bits_user_amba_prot_writealloc, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_0_a_bits_user_amba_prot_privileged, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_0_a_bits_user_amba_prot_secure, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_0_a_bits_user_amba_prot_fetch, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_out_0_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_out_0_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_0_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_0_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_anon_out_0_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_anon_out_0_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_0_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_0_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_out_0_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_0_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
wire auto_anon_in_1_a_valid_0 = auto_anon_in_1_a_valid; // @[FIFOFixer.scala:50:9]
wire [2:0] auto_anon_in_1_a_bits_opcode_0 = auto_anon_in_1_a_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [2:0] auto_anon_in_1_a_bits_param_0 = auto_anon_in_1_a_bits_param; // @[FIFOFixer.scala:50:9]
wire [3:0] auto_anon_in_1_a_bits_size_0 = auto_anon_in_1_a_bits_size; // @[FIFOFixer.scala:50:9]
wire auto_anon_in_1_a_bits_source_0 = auto_anon_in_1_a_bits_source; // @[FIFOFixer.scala:50:9]
wire [31:0] auto_anon_in_1_a_bits_address_0 = auto_anon_in_1_a_bits_address; // @[FIFOFixer.scala:50:9]
wire auto_anon_in_1_a_bits_user_amba_prot_bufferable_0 = auto_anon_in_1_a_bits_user_amba_prot_bufferable; // @[FIFOFixer.scala:50:9]
wire auto_anon_in_1_a_bits_user_amba_prot_modifiable_0 = auto_anon_in_1_a_bits_user_amba_prot_modifiable; // @[FIFOFixer.scala:50:9]
wire auto_anon_in_1_a_bits_user_amba_prot_readalloc_0 = auto_anon_in_1_a_bits_user_amba_prot_readalloc; // @[FIFOFixer.scala:50:9]
wire auto_anon_in_1_a_bits_user_amba_prot_writealloc_0 = auto_anon_in_1_a_bits_user_amba_prot_writealloc; // @[FIFOFixer.scala:50:9]
wire auto_anon_in_1_a_bits_user_amba_prot_privileged_0 = auto_anon_in_1_a_bits_user_amba_prot_privileged; // @[FIFOFixer.scala:50:9]
wire auto_anon_in_1_a_bits_user_amba_prot_secure_0 = auto_anon_in_1_a_bits_user_amba_prot_secure; // @[FIFOFixer.scala:50:9]
wire auto_anon_in_1_a_bits_user_amba_prot_fetch_0 = auto_anon_in_1_a_bits_user_amba_prot_fetch; // @[FIFOFixer.scala:50:9]
wire [7:0] auto_anon_in_1_a_bits_mask_0 = auto_anon_in_1_a_bits_mask; // @[FIFOFixer.scala:50:9]
wire [63:0] auto_anon_in_1_a_bits_data_0 = auto_anon_in_1_a_bits_data; // @[FIFOFixer.scala:50:9]
wire auto_anon_in_1_a_bits_corrupt_0 = auto_anon_in_1_a_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire auto_anon_in_1_d_ready_0 = auto_anon_in_1_d_ready; // @[FIFOFixer.scala:50:9]
wire auto_anon_in_0_a_valid_0 = auto_anon_in_0_a_valid; // @[FIFOFixer.scala:50:9]
wire [2:0] auto_anon_in_0_a_bits_opcode_0 = auto_anon_in_0_a_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [2:0] auto_anon_in_0_a_bits_param_0 = auto_anon_in_0_a_bits_param; // @[FIFOFixer.scala:50:9]
wire [3:0] auto_anon_in_0_a_bits_size_0 = auto_anon_in_0_a_bits_size; // @[FIFOFixer.scala:50:9]
wire [5:0] auto_anon_in_0_a_bits_source_0 = auto_anon_in_0_a_bits_source; // @[FIFOFixer.scala:50:9]
wire [31:0] auto_anon_in_0_a_bits_address_0 = auto_anon_in_0_a_bits_address; // @[FIFOFixer.scala:50:9]
wire auto_anon_in_0_a_bits_user_amba_prot_bufferable_0 = auto_anon_in_0_a_bits_user_amba_prot_bufferable; // @[FIFOFixer.scala:50:9]
wire auto_anon_in_0_a_bits_user_amba_prot_modifiable_0 = auto_anon_in_0_a_bits_user_amba_prot_modifiable; // @[FIFOFixer.scala:50:9]
wire auto_anon_in_0_a_bits_user_amba_prot_readalloc_0 = auto_anon_in_0_a_bits_user_amba_prot_readalloc; // @[FIFOFixer.scala:50:9]
wire auto_anon_in_0_a_bits_user_amba_prot_writealloc_0 = auto_anon_in_0_a_bits_user_amba_prot_writealloc; // @[FIFOFixer.scala:50:9]
wire auto_anon_in_0_a_bits_user_amba_prot_privileged_0 = auto_anon_in_0_a_bits_user_amba_prot_privileged; // @[FIFOFixer.scala:50:9]
wire auto_anon_in_0_a_bits_user_amba_prot_secure_0 = auto_anon_in_0_a_bits_user_amba_prot_secure; // @[FIFOFixer.scala:50:9]
wire auto_anon_in_0_a_bits_user_amba_prot_fetch_0 = auto_anon_in_0_a_bits_user_amba_prot_fetch; // @[FIFOFixer.scala:50:9]
wire [7:0] auto_anon_in_0_a_bits_mask_0 = auto_anon_in_0_a_bits_mask; // @[FIFOFixer.scala:50:9]
wire [63:0] auto_anon_in_0_a_bits_data_0 = auto_anon_in_0_a_bits_data; // @[FIFOFixer.scala:50:9]
wire auto_anon_in_0_a_bits_corrupt_0 = auto_anon_in_0_a_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire auto_anon_in_0_d_ready_0 = auto_anon_in_0_d_ready; // @[FIFOFixer.scala:50:9]
wire auto_anon_out_1_a_ready_0 = auto_anon_out_1_a_ready; // @[FIFOFixer.scala:50:9]
wire auto_anon_out_1_d_valid_0 = auto_anon_out_1_d_valid; // @[FIFOFixer.scala:50:9]
wire [2:0] auto_anon_out_1_d_bits_opcode_0 = auto_anon_out_1_d_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [1:0] auto_anon_out_1_d_bits_param_0 = auto_anon_out_1_d_bits_param; // @[FIFOFixer.scala:50:9]
wire [3:0] auto_anon_out_1_d_bits_size_0 = auto_anon_out_1_d_bits_size; // @[FIFOFixer.scala:50:9]
wire auto_anon_out_1_d_bits_source_0 = auto_anon_out_1_d_bits_source; // @[FIFOFixer.scala:50:9]
wire auto_anon_out_1_d_bits_sink_0 = auto_anon_out_1_d_bits_sink; // @[FIFOFixer.scala:50:9]
wire auto_anon_out_1_d_bits_denied_0 = auto_anon_out_1_d_bits_denied; // @[FIFOFixer.scala:50:9]
wire [63:0] auto_anon_out_1_d_bits_data_0 = auto_anon_out_1_d_bits_data; // @[FIFOFixer.scala:50:9]
wire auto_anon_out_1_d_bits_corrupt_0 = auto_anon_out_1_d_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire auto_anon_out_0_a_ready_0 = auto_anon_out_0_a_ready; // @[FIFOFixer.scala:50:9]
wire auto_anon_out_0_d_valid_0 = auto_anon_out_0_d_valid; // @[FIFOFixer.scala:50:9]
wire [2:0] auto_anon_out_0_d_bits_opcode_0 = auto_anon_out_0_d_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [1:0] auto_anon_out_0_d_bits_param_0 = auto_anon_out_0_d_bits_param; // @[FIFOFixer.scala:50:9]
wire [3:0] auto_anon_out_0_d_bits_size_0 = auto_anon_out_0_d_bits_size; // @[FIFOFixer.scala:50:9]
wire [5:0] auto_anon_out_0_d_bits_source_0 = auto_anon_out_0_d_bits_source; // @[FIFOFixer.scala:50:9]
wire auto_anon_out_0_d_bits_sink_0 = auto_anon_out_0_d_bits_sink; // @[FIFOFixer.scala:50:9]
wire auto_anon_out_0_d_bits_denied_0 = auto_anon_out_0_d_bits_denied; // @[FIFOFixer.scala:50:9]
wire [63:0] auto_anon_out_0_d_bits_data_0 = auto_anon_out_0_d_bits_data; // @[FIFOFixer.scala:50:9]
wire auto_anon_out_0_d_bits_corrupt_0 = auto_anon_out_0_d_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire [32:0] _allIDs_FIFOed_T = 33'h1FFFFFFFF; // @[FIFOFixer.scala:127:48]
wire [32:0] _a_notFIFO_T_2 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _a_notFIFO_T_3 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _a_notFIFO_T_7 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _a_notFIFO_T_8 = 33'h0; // @[Parameters.scala:137:46]
wire _flight_WIRE_0 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_1 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_2 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_3 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_4 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_5 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_6 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_7 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_8 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_9 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_10 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_11 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_12 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_13 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_14 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_15 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_16 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_17 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_18 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_19 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_20 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_21 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_22 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_23 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_24 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_25 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_26 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_27 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_28 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_29 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_30 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_31 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_32 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_1_0 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_1_1 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _a_notFIFO_T_4 = 1'h1; // @[Parameters.scala:137:59]
wire _flight_T = 1'h1; // @[FIFOFixer.scala:80:65]
wire _stalls_a_sel_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _stalls_a_sel_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire _stalls_id_T_2 = 1'h1; // @[FIFOFixer.scala:85:59]
wire _stalls_a_sel_T_7 = 1'h1; // @[Parameters.scala:56:32]
wire _stalls_a_sel_T_9 = 1'h1; // @[Parameters.scala:57:20]
wire _stalls_id_T_6 = 1'h1; // @[FIFOFixer.scala:85:59]
wire _a_notFIFO_T_9 = 1'h1; // @[Parameters.scala:137:59]
wire _flight_T_1 = 1'h1; // @[FIFOFixer.scala:80:65]
wire _anonOut_a_valid_T_3 = 1'h1; // @[FIFOFixer.scala:95:50]
wire _anonOut_a_valid_T_4 = 1'h1; // @[FIFOFixer.scala:95:47]
wire _anonIn_a_ready_T_3 = 1'h1; // @[FIFOFixer.scala:96:50]
wire _anonIn_a_ready_T_4 = 1'h1; // @[FIFOFixer.scala:96:47]
wire anonIn_1_a_ready; // @[MixedNode.scala:551:17]
wire [1:0] _allIDs_FIFOed_T_1 = 2'h3; // @[FIFOFixer.scala:127:48]
wire anonIn_1_a_valid = auto_anon_in_1_a_valid_0; // @[FIFOFixer.scala:50:9]
wire [2:0] anonIn_1_a_bits_opcode = auto_anon_in_1_a_bits_opcode_0; // @[FIFOFixer.scala:50:9]
wire [2:0] anonIn_1_a_bits_param = auto_anon_in_1_a_bits_param_0; // @[FIFOFixer.scala:50:9]
wire [3:0] anonIn_1_a_bits_size = auto_anon_in_1_a_bits_size_0; // @[FIFOFixer.scala:50:9]
wire anonIn_1_a_bits_source = auto_anon_in_1_a_bits_source_0; // @[FIFOFixer.scala:50:9]
wire [31:0] anonIn_1_a_bits_address = auto_anon_in_1_a_bits_address_0; // @[FIFOFixer.scala:50:9]
wire anonIn_1_a_bits_user_amba_prot_bufferable = auto_anon_in_1_a_bits_user_amba_prot_bufferable_0; // @[FIFOFixer.scala:50:9]
wire anonIn_1_a_bits_user_amba_prot_modifiable = auto_anon_in_1_a_bits_user_amba_prot_modifiable_0; // @[FIFOFixer.scala:50:9]
wire anonIn_1_a_bits_user_amba_prot_readalloc = auto_anon_in_1_a_bits_user_amba_prot_readalloc_0; // @[FIFOFixer.scala:50:9]
wire anonIn_1_a_bits_user_amba_prot_writealloc = auto_anon_in_1_a_bits_user_amba_prot_writealloc_0; // @[FIFOFixer.scala:50:9]
wire anonIn_1_a_bits_user_amba_prot_privileged = auto_anon_in_1_a_bits_user_amba_prot_privileged_0; // @[FIFOFixer.scala:50:9]
wire anonIn_1_a_bits_user_amba_prot_secure = auto_anon_in_1_a_bits_user_amba_prot_secure_0; // @[FIFOFixer.scala:50:9]
wire anonIn_1_a_bits_user_amba_prot_fetch = auto_anon_in_1_a_bits_user_amba_prot_fetch_0; // @[FIFOFixer.scala:50:9]
wire [7:0] anonIn_1_a_bits_mask = auto_anon_in_1_a_bits_mask_0; // @[FIFOFixer.scala:50:9]
wire [63:0] anonIn_1_a_bits_data = auto_anon_in_1_a_bits_data_0; // @[FIFOFixer.scala:50:9]
wire anonIn_1_a_bits_corrupt = auto_anon_in_1_a_bits_corrupt_0; // @[FIFOFixer.scala:50:9]
wire anonIn_1_d_ready = auto_anon_in_1_d_ready_0; // @[FIFOFixer.scala:50:9]
wire anonIn_1_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_1_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] anonIn_1_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] anonIn_1_d_bits_size; // @[MixedNode.scala:551:17]
wire anonIn_1_d_bits_source; // @[MixedNode.scala:551:17]
wire anonIn_1_d_bits_sink; // @[MixedNode.scala:551:17]
wire anonIn_1_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] anonIn_1_d_bits_data; // @[MixedNode.scala:551:17]
wire anonIn_1_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire anonIn_a_ready; // @[MixedNode.scala:551:17]
wire anonIn_a_valid = auto_anon_in_0_a_valid_0; // @[FIFOFixer.scala:50:9]
wire [2:0] anonIn_a_bits_opcode = auto_anon_in_0_a_bits_opcode_0; // @[FIFOFixer.scala:50:9]
wire [2:0] anonIn_a_bits_param = auto_anon_in_0_a_bits_param_0; // @[FIFOFixer.scala:50:9]
wire [3:0] anonIn_a_bits_size = auto_anon_in_0_a_bits_size_0; // @[FIFOFixer.scala:50:9]
wire [5:0] anonIn_a_bits_source = auto_anon_in_0_a_bits_source_0; // @[FIFOFixer.scala:50:9]
wire [31:0] anonIn_a_bits_address = auto_anon_in_0_a_bits_address_0; // @[FIFOFixer.scala:50:9]
wire anonIn_a_bits_user_amba_prot_bufferable = auto_anon_in_0_a_bits_user_amba_prot_bufferable_0; // @[FIFOFixer.scala:50:9]
wire anonIn_a_bits_user_amba_prot_modifiable = auto_anon_in_0_a_bits_user_amba_prot_modifiable_0; // @[FIFOFixer.scala:50:9]
wire anonIn_a_bits_user_amba_prot_readalloc = auto_anon_in_0_a_bits_user_amba_prot_readalloc_0; // @[FIFOFixer.scala:50:9]
wire anonIn_a_bits_user_amba_prot_writealloc = auto_anon_in_0_a_bits_user_amba_prot_writealloc_0; // @[FIFOFixer.scala:50:9]
wire anonIn_a_bits_user_amba_prot_privileged = auto_anon_in_0_a_bits_user_amba_prot_privileged_0; // @[FIFOFixer.scala:50:9]
wire anonIn_a_bits_user_amba_prot_secure = auto_anon_in_0_a_bits_user_amba_prot_secure_0; // @[FIFOFixer.scala:50:9]
wire anonIn_a_bits_user_amba_prot_fetch = auto_anon_in_0_a_bits_user_amba_prot_fetch_0; // @[FIFOFixer.scala:50:9]
wire [7:0] anonIn_a_bits_mask = auto_anon_in_0_a_bits_mask_0; // @[FIFOFixer.scala:50:9]
wire [63:0] anonIn_a_bits_data = auto_anon_in_0_a_bits_data_0; // @[FIFOFixer.scala:50:9]
wire anonIn_a_bits_corrupt = auto_anon_in_0_a_bits_corrupt_0; // @[FIFOFixer.scala:50:9]
wire anonIn_d_ready = auto_anon_in_0_d_ready_0; // @[FIFOFixer.scala:50:9]
wire anonIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] anonIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [5:0] anonIn_d_bits_source; // @[MixedNode.scala:551:17]
wire anonIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire anonIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17]
wire anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire x1_anonOut_a_ready = auto_anon_out_1_a_ready_0; // @[FIFOFixer.scala:50:9]
wire x1_anonOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] x1_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] x1_anonOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] x1_anonOut_a_bits_size; // @[MixedNode.scala:542:17]
wire x1_anonOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] x1_anonOut_a_bits_address; // @[MixedNode.scala:542:17]
wire x1_anonOut_a_bits_user_amba_prot_bufferable; // @[MixedNode.scala:542:17]
wire x1_anonOut_a_bits_user_amba_prot_modifiable; // @[MixedNode.scala:542:17]
wire x1_anonOut_a_bits_user_amba_prot_readalloc; // @[MixedNode.scala:542:17]
wire x1_anonOut_a_bits_user_amba_prot_writealloc; // @[MixedNode.scala:542:17]
wire x1_anonOut_a_bits_user_amba_prot_privileged; // @[MixedNode.scala:542:17]
wire x1_anonOut_a_bits_user_amba_prot_secure; // @[MixedNode.scala:542:17]
wire x1_anonOut_a_bits_user_amba_prot_fetch; // @[MixedNode.scala:542:17]
wire [7:0] x1_anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] x1_anonOut_a_bits_data; // @[MixedNode.scala:542:17]
wire x1_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire x1_anonOut_d_ready; // @[MixedNode.scala:542:17]
wire x1_anonOut_d_valid = auto_anon_out_1_d_valid_0; // @[FIFOFixer.scala:50:9]
wire [2:0] x1_anonOut_d_bits_opcode = auto_anon_out_1_d_bits_opcode_0; // @[FIFOFixer.scala:50:9]
wire [1:0] x1_anonOut_d_bits_param = auto_anon_out_1_d_bits_param_0; // @[FIFOFixer.scala:50:9]
wire [3:0] x1_anonOut_d_bits_size = auto_anon_out_1_d_bits_size_0; // @[FIFOFixer.scala:50:9]
wire x1_anonOut_d_bits_source = auto_anon_out_1_d_bits_source_0; // @[FIFOFixer.scala:50:9]
wire x1_anonOut_d_bits_sink = auto_anon_out_1_d_bits_sink_0; // @[FIFOFixer.scala:50:9]
wire x1_anonOut_d_bits_denied = auto_anon_out_1_d_bits_denied_0; // @[FIFOFixer.scala:50:9]
wire [63:0] x1_anonOut_d_bits_data = auto_anon_out_1_d_bits_data_0; // @[FIFOFixer.scala:50:9]
wire x1_anonOut_d_bits_corrupt = auto_anon_out_1_d_bits_corrupt_0; // @[FIFOFixer.scala:50:9]
wire anonOut_a_ready = auto_anon_out_0_a_ready_0; // @[FIFOFixer.scala:50:9]
wire anonOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [5:0] anonOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17]
wire anonOut_a_bits_user_amba_prot_bufferable; // @[MixedNode.scala:542:17]
wire anonOut_a_bits_user_amba_prot_modifiable; // @[MixedNode.scala:542:17]
wire anonOut_a_bits_user_amba_prot_readalloc; // @[MixedNode.scala:542:17]
wire anonOut_a_bits_user_amba_prot_writealloc; // @[MixedNode.scala:542:17]
wire anonOut_a_bits_user_amba_prot_privileged; // @[MixedNode.scala:542:17]
wire anonOut_a_bits_user_amba_prot_secure; // @[MixedNode.scala:542:17]
wire anonOut_a_bits_user_amba_prot_fetch; // @[MixedNode.scala:542:17]
wire [7:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17]
wire anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire anonOut_d_ready; // @[MixedNode.scala:542:17]
wire anonOut_d_valid = auto_anon_out_0_d_valid_0; // @[FIFOFixer.scala:50:9]
wire [2:0] anonOut_d_bits_opcode = auto_anon_out_0_d_bits_opcode_0; // @[FIFOFixer.scala:50:9]
wire [1:0] anonOut_d_bits_param = auto_anon_out_0_d_bits_param_0; // @[FIFOFixer.scala:50:9]
wire [3:0] anonOut_d_bits_size = auto_anon_out_0_d_bits_size_0; // @[FIFOFixer.scala:50:9]
wire [5:0] anonOut_d_bits_source = auto_anon_out_0_d_bits_source_0; // @[FIFOFixer.scala:50:9]
wire anonOut_d_bits_sink = auto_anon_out_0_d_bits_sink_0; // @[FIFOFixer.scala:50:9]
wire anonOut_d_bits_denied = auto_anon_out_0_d_bits_denied_0; // @[FIFOFixer.scala:50:9]
wire [63:0] anonOut_d_bits_data = auto_anon_out_0_d_bits_data_0; // @[FIFOFixer.scala:50:9]
wire anonOut_d_bits_corrupt = auto_anon_out_0_d_bits_corrupt_0; // @[FIFOFixer.scala:50:9]
wire auto_anon_in_1_a_ready_0; // @[FIFOFixer.scala:50:9]
wire [2:0] auto_anon_in_1_d_bits_opcode_0; // @[FIFOFixer.scala:50:9]
wire [1:0] auto_anon_in_1_d_bits_param_0; // @[FIFOFixer.scala:50:9]
wire [3:0] auto_anon_in_1_d_bits_size_0; // @[FIFOFixer.scala:50:9]
wire auto_anon_in_1_d_bits_source_0; // @[FIFOFixer.scala:50:9]
wire auto_anon_in_1_d_bits_sink_0; // @[FIFOFixer.scala:50:9]
wire auto_anon_in_1_d_bits_denied_0; // @[FIFOFixer.scala:50:9]
wire [63:0] auto_anon_in_1_d_bits_data_0; // @[FIFOFixer.scala:50:9]
wire auto_anon_in_1_d_bits_corrupt_0; // @[FIFOFixer.scala:50:9]
wire auto_anon_in_1_d_valid_0; // @[FIFOFixer.scala:50:9]
wire auto_anon_in_0_a_ready_0; // @[FIFOFixer.scala:50:9]
wire [2:0] auto_anon_in_0_d_bits_opcode_0; // @[FIFOFixer.scala:50:9]
wire [1:0] auto_anon_in_0_d_bits_param_0; // @[FIFOFixer.scala:50:9]
wire [3:0] auto_anon_in_0_d_bits_size_0; // @[FIFOFixer.scala:50:9]
wire [5:0] auto_anon_in_0_d_bits_source_0; // @[FIFOFixer.scala:50:9]
wire auto_anon_in_0_d_bits_sink_0; // @[FIFOFixer.scala:50:9]
wire auto_anon_in_0_d_bits_denied_0; // @[FIFOFixer.scala:50:9]
wire [63:0] auto_anon_in_0_d_bits_data_0; // @[FIFOFixer.scala:50:9]
wire auto_anon_in_0_d_bits_corrupt_0; // @[FIFOFixer.scala:50:9]
wire auto_anon_in_0_d_valid_0; // @[FIFOFixer.scala:50:9]
wire auto_anon_out_1_a_bits_user_amba_prot_bufferable_0; // @[FIFOFixer.scala:50:9]
wire auto_anon_out_1_a_bits_user_amba_prot_modifiable_0; // @[FIFOFixer.scala:50:9]
wire auto_anon_out_1_a_bits_user_amba_prot_readalloc_0; // @[FIFOFixer.scala:50:9]
wire auto_anon_out_1_a_bits_user_amba_prot_writealloc_0; // @[FIFOFixer.scala:50:9]
wire auto_anon_out_1_a_bits_user_amba_prot_privileged_0; // @[FIFOFixer.scala:50:9]
wire auto_anon_out_1_a_bits_user_amba_prot_secure_0; // @[FIFOFixer.scala:50:9]
wire auto_anon_out_1_a_bits_user_amba_prot_fetch_0; // @[FIFOFixer.scala:50:9]
wire [2:0] auto_anon_out_1_a_bits_opcode_0; // @[FIFOFixer.scala:50:9]
wire [2:0] auto_anon_out_1_a_bits_param_0; // @[FIFOFixer.scala:50:9]
wire [3:0] auto_anon_out_1_a_bits_size_0; // @[FIFOFixer.scala:50:9]
wire auto_anon_out_1_a_bits_source_0; // @[FIFOFixer.scala:50:9]
wire [31:0] auto_anon_out_1_a_bits_address_0; // @[FIFOFixer.scala:50:9]
wire [7:0] auto_anon_out_1_a_bits_mask_0; // @[FIFOFixer.scala:50:9]
wire [63:0] auto_anon_out_1_a_bits_data_0; // @[FIFOFixer.scala:50:9]
wire auto_anon_out_1_a_bits_corrupt_0; // @[FIFOFixer.scala:50:9]
wire auto_anon_out_1_a_valid_0; // @[FIFOFixer.scala:50:9]
wire auto_anon_out_1_d_ready_0; // @[FIFOFixer.scala:50:9]
wire auto_anon_out_0_a_bits_user_amba_prot_bufferable_0; // @[FIFOFixer.scala:50:9]
wire auto_anon_out_0_a_bits_user_amba_prot_modifiable_0; // @[FIFOFixer.scala:50:9]
wire auto_anon_out_0_a_bits_user_amba_prot_readalloc_0; // @[FIFOFixer.scala:50:9]
wire auto_anon_out_0_a_bits_user_amba_prot_writealloc_0; // @[FIFOFixer.scala:50:9]
wire auto_anon_out_0_a_bits_user_amba_prot_privileged_0; // @[FIFOFixer.scala:50:9]
wire auto_anon_out_0_a_bits_user_amba_prot_secure_0; // @[FIFOFixer.scala:50:9]
wire auto_anon_out_0_a_bits_user_amba_prot_fetch_0; // @[FIFOFixer.scala:50:9]
wire [2:0] auto_anon_out_0_a_bits_opcode_0; // @[FIFOFixer.scala:50:9]
wire [2:0] auto_anon_out_0_a_bits_param_0; // @[FIFOFixer.scala:50:9]
wire [3:0] auto_anon_out_0_a_bits_size_0; // @[FIFOFixer.scala:50:9]
wire [5:0] auto_anon_out_0_a_bits_source_0; // @[FIFOFixer.scala:50:9]
wire [31:0] auto_anon_out_0_a_bits_address_0; // @[FIFOFixer.scala:50:9]
wire [7:0] auto_anon_out_0_a_bits_mask_0; // @[FIFOFixer.scala:50:9]
wire [63:0] auto_anon_out_0_a_bits_data_0; // @[FIFOFixer.scala:50:9]
wire auto_anon_out_0_a_bits_corrupt_0; // @[FIFOFixer.scala:50:9]
wire auto_anon_out_0_a_valid_0; // @[FIFOFixer.scala:50:9]
wire auto_anon_out_0_d_ready_0; // @[FIFOFixer.scala:50:9]
wire _anonIn_a_ready_T_2; // @[FIFOFixer.scala:96:33]
assign auto_anon_in_0_a_ready_0 = anonIn_a_ready; // @[FIFOFixer.scala:50:9]
assign anonOut_a_bits_opcode = anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign anonOut_a_bits_param = anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign anonOut_a_bits_size = anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign anonOut_a_bits_source = anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [5:0] _stalls_a_sel_uncommonBits_T = anonIn_a_bits_source; // @[Parameters.scala:52:29]
wire [5:0] _stalls_a_sel_uncommonBits_T_1 = anonIn_a_bits_source; // @[Parameters.scala:52:29]
assign anonOut_a_bits_address = anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] _a_notFIFO_T = anonIn_a_bits_address; // @[Parameters.scala:137:31]
wire [31:0] _a_id_T = anonIn_a_bits_address; // @[Parameters.scala:137:31]
assign anonOut_a_bits_user_amba_prot_bufferable = anonIn_a_bits_user_amba_prot_bufferable; // @[MixedNode.scala:542:17, :551:17]
assign anonOut_a_bits_user_amba_prot_modifiable = anonIn_a_bits_user_amba_prot_modifiable; // @[MixedNode.scala:542:17, :551:17]
assign anonOut_a_bits_user_amba_prot_readalloc = anonIn_a_bits_user_amba_prot_readalloc; // @[MixedNode.scala:542:17, :551:17]
assign anonOut_a_bits_user_amba_prot_writealloc = anonIn_a_bits_user_amba_prot_writealloc; // @[MixedNode.scala:542:17, :551:17]
assign anonOut_a_bits_user_amba_prot_privileged = anonIn_a_bits_user_amba_prot_privileged; // @[MixedNode.scala:542:17, :551:17]
assign anonOut_a_bits_user_amba_prot_secure = anonIn_a_bits_user_amba_prot_secure; // @[MixedNode.scala:542:17, :551:17]
assign anonOut_a_bits_user_amba_prot_fetch = anonIn_a_bits_user_amba_prot_fetch; // @[MixedNode.scala:542:17, :551:17]
assign anonOut_a_bits_mask = anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign anonOut_a_bits_data = anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign anonOut_a_bits_corrupt = anonIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign anonOut_d_ready = anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign auto_anon_in_0_d_valid_0 = anonIn_d_valid; // @[FIFOFixer.scala:50:9]
assign auto_anon_in_0_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[FIFOFixer.scala:50:9]
assign auto_anon_in_0_d_bits_param_0 = anonIn_d_bits_param; // @[FIFOFixer.scala:50:9]
assign auto_anon_in_0_d_bits_size_0 = anonIn_d_bits_size; // @[FIFOFixer.scala:50:9]
assign auto_anon_in_0_d_bits_source_0 = anonIn_d_bits_source; // @[FIFOFixer.scala:50:9]
assign auto_anon_in_0_d_bits_sink_0 = anonIn_d_bits_sink; // @[FIFOFixer.scala:50:9]
assign auto_anon_in_0_d_bits_denied_0 = anonIn_d_bits_denied; // @[FIFOFixer.scala:50:9]
assign auto_anon_in_0_d_bits_data_0 = anonIn_d_bits_data; // @[FIFOFixer.scala:50:9]
assign auto_anon_in_0_d_bits_corrupt_0 = anonIn_d_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire _anonIn_a_ready_T_5; // @[FIFOFixer.scala:96:33]
assign auto_anon_in_1_a_ready_0 = anonIn_1_a_ready; // @[FIFOFixer.scala:50:9]
wire _anonOut_a_valid_T_5 = anonIn_1_a_valid; // @[FIFOFixer.scala:95:33]
assign x1_anonOut_a_bits_opcode = anonIn_1_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign x1_anonOut_a_bits_param = anonIn_1_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign x1_anonOut_a_bits_size = anonIn_1_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign x1_anonOut_a_bits_source = anonIn_1_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign x1_anonOut_a_bits_address = anonIn_1_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] _a_notFIFO_T_5 = anonIn_1_a_bits_address; // @[Parameters.scala:137:31]
wire [31:0] _a_id_T_13 = anonIn_1_a_bits_address; // @[Parameters.scala:137:31]
assign x1_anonOut_a_bits_user_amba_prot_bufferable = anonIn_1_a_bits_user_amba_prot_bufferable; // @[MixedNode.scala:542:17, :551:17]
assign x1_anonOut_a_bits_user_amba_prot_modifiable = anonIn_1_a_bits_user_amba_prot_modifiable; // @[MixedNode.scala:542:17, :551:17]
assign x1_anonOut_a_bits_user_amba_prot_readalloc = anonIn_1_a_bits_user_amba_prot_readalloc; // @[MixedNode.scala:542:17, :551:17]
assign x1_anonOut_a_bits_user_amba_prot_writealloc = anonIn_1_a_bits_user_amba_prot_writealloc; // @[MixedNode.scala:542:17, :551:17]
assign x1_anonOut_a_bits_user_amba_prot_privileged = anonIn_1_a_bits_user_amba_prot_privileged; // @[MixedNode.scala:542:17, :551:17]
assign x1_anonOut_a_bits_user_amba_prot_secure = anonIn_1_a_bits_user_amba_prot_secure; // @[MixedNode.scala:542:17, :551:17]
assign x1_anonOut_a_bits_user_amba_prot_fetch = anonIn_1_a_bits_user_amba_prot_fetch; // @[MixedNode.scala:542:17, :551:17]
assign x1_anonOut_a_bits_mask = anonIn_1_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign x1_anonOut_a_bits_data = anonIn_1_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign x1_anonOut_a_bits_corrupt = anonIn_1_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign x1_anonOut_d_ready = anonIn_1_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign auto_anon_in_1_d_valid_0 = anonIn_1_d_valid; // @[FIFOFixer.scala:50:9]
assign auto_anon_in_1_d_bits_opcode_0 = anonIn_1_d_bits_opcode; // @[FIFOFixer.scala:50:9]
assign auto_anon_in_1_d_bits_param_0 = anonIn_1_d_bits_param; // @[FIFOFixer.scala:50:9]
assign auto_anon_in_1_d_bits_size_0 = anonIn_1_d_bits_size; // @[FIFOFixer.scala:50:9]
assign auto_anon_in_1_d_bits_source_0 = anonIn_1_d_bits_source; // @[FIFOFixer.scala:50:9]
assign auto_anon_in_1_d_bits_sink_0 = anonIn_1_d_bits_sink; // @[FIFOFixer.scala:50:9]
assign auto_anon_in_1_d_bits_denied_0 = anonIn_1_d_bits_denied; // @[FIFOFixer.scala:50:9]
assign auto_anon_in_1_d_bits_data_0 = anonIn_1_d_bits_data; // @[FIFOFixer.scala:50:9]
assign auto_anon_in_1_d_bits_corrupt_0 = anonIn_1_d_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire _anonOut_a_valid_T_2; // @[FIFOFixer.scala:95:33]
assign auto_anon_out_0_a_valid_0 = anonOut_a_valid; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_0_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_0_a_bits_param_0 = anonOut_a_bits_param; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_0_a_bits_size_0 = anonOut_a_bits_size; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_0_a_bits_source_0 = anonOut_a_bits_source; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_0_a_bits_address_0 = anonOut_a_bits_address; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_0_a_bits_user_amba_prot_bufferable_0 = anonOut_a_bits_user_amba_prot_bufferable; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_0_a_bits_user_amba_prot_modifiable_0 = anonOut_a_bits_user_amba_prot_modifiable; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_0_a_bits_user_amba_prot_readalloc_0 = anonOut_a_bits_user_amba_prot_readalloc; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_0_a_bits_user_amba_prot_writealloc_0 = anonOut_a_bits_user_amba_prot_writealloc; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_0_a_bits_user_amba_prot_privileged_0 = anonOut_a_bits_user_amba_prot_privileged; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_0_a_bits_user_amba_prot_secure_0 = anonOut_a_bits_user_amba_prot_secure; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_0_a_bits_user_amba_prot_fetch_0 = anonOut_a_bits_user_amba_prot_fetch; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_0_a_bits_mask_0 = anonOut_a_bits_mask; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_0_a_bits_data_0 = anonOut_a_bits_data; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_0_a_bits_corrupt_0 = anonOut_a_bits_corrupt; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_0_d_ready_0 = anonOut_d_ready; // @[FIFOFixer.scala:50:9]
assign anonIn_d_valid = anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign anonIn_d_bits_opcode = anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign anonIn_d_bits_param = anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign anonIn_d_bits_size = anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign anonIn_d_bits_source = anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign anonIn_d_bits_sink = anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign anonIn_d_bits_denied = anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign anonIn_d_bits_data = anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign anonIn_d_bits_corrupt = anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign _anonIn_a_ready_T_5 = x1_anonOut_a_ready; // @[FIFOFixer.scala:96:33]
assign auto_anon_out_1_a_valid_0 = x1_anonOut_a_valid; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_1_a_bits_opcode_0 = x1_anonOut_a_bits_opcode; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_1_a_bits_param_0 = x1_anonOut_a_bits_param; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_1_a_bits_size_0 = x1_anonOut_a_bits_size; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_1_a_bits_source_0 = x1_anonOut_a_bits_source; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_1_a_bits_address_0 = x1_anonOut_a_bits_address; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_1_a_bits_user_amba_prot_bufferable_0 = x1_anonOut_a_bits_user_amba_prot_bufferable; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_1_a_bits_user_amba_prot_modifiable_0 = x1_anonOut_a_bits_user_amba_prot_modifiable; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_1_a_bits_user_amba_prot_readalloc_0 = x1_anonOut_a_bits_user_amba_prot_readalloc; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_1_a_bits_user_amba_prot_writealloc_0 = x1_anonOut_a_bits_user_amba_prot_writealloc; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_1_a_bits_user_amba_prot_privileged_0 = x1_anonOut_a_bits_user_amba_prot_privileged; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_1_a_bits_user_amba_prot_secure_0 = x1_anonOut_a_bits_user_amba_prot_secure; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_1_a_bits_user_amba_prot_fetch_0 = x1_anonOut_a_bits_user_amba_prot_fetch; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_1_a_bits_mask_0 = x1_anonOut_a_bits_mask; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_1_a_bits_data_0 = x1_anonOut_a_bits_data; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_1_a_bits_corrupt_0 = x1_anonOut_a_bits_corrupt; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_1_d_ready_0 = x1_anonOut_d_ready; // @[FIFOFixer.scala:50:9]
assign anonIn_1_d_valid = x1_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign anonIn_1_d_bits_opcode = x1_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign anonIn_1_d_bits_param = x1_anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign anonIn_1_d_bits_size = x1_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign anonIn_1_d_bits_source = x1_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign anonIn_1_d_bits_sink = x1_anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign anonIn_1_d_bits_denied = x1_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign anonIn_1_d_bits_data = x1_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign anonIn_1_d_bits_corrupt = x1_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire [32:0] _a_notFIFO_T_1 = {1'h0, _a_notFIFO_T}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _a_id_T_1 = {1'h0, _a_id_T}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _a_id_T_2 = _a_id_T_1 & 33'h40000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _a_id_T_3 = _a_id_T_2; // @[Parameters.scala:137:46]
wire _a_id_T_4 = _a_id_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _a_id_T_10 = _a_id_T_4; // @[Mux.scala:30:73]
wire [31:0] _a_id_T_5 = {anonIn_a_bits_address[31], anonIn_a_bits_address[30:0] ^ 31'h40000000}; // @[Parameters.scala:137:31]
wire [32:0] _a_id_T_6 = {1'h0, _a_id_T_5}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _a_id_T_7 = _a_id_T_6 & 33'h40000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _a_id_T_8 = _a_id_T_7; // @[Parameters.scala:137:46]
wire _a_id_T_9 = _a_id_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [1:0] _a_id_T_11 = {_a_id_T_9, 1'h0}; // @[Mux.scala:30:73]
wire [1:0] _a_id_T_12 = {1'h0, _a_id_T_10} | _a_id_T_11; // @[Mux.scala:30:73]
wire [1:0] a_id = _a_id_T_12; // @[Mux.scala:30:73]
wire a_noDomain = a_id == 2'h0; // @[Mux.scala:30:73]
wire _T_5 = anonIn_a_ready & anonIn_a_valid; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_5; // @[Decoupled.scala:51:35]
wire _stalls_id_T; // @[Decoupled.scala:51:35]
assign _stalls_id_T = _T_5; // @[Decoupled.scala:51:35]
wire _stalls_id_T_4; // @[Decoupled.scala:51:35]
assign _stalls_id_T_4 = _T_5; // @[Decoupled.scala:51:35]
wire [26:0] _a_first_beats1_decode_T = 27'hFFF << anonIn_a_bits_size; // @[package.scala:243:71]
wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = anonIn_a_bits_opcode[2]; // @[Edges.scala:92:37]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire _d_first_T = anonOut_d_ready & anonOut_d_valid; // @[Decoupled.scala:51:35]
wire [26:0] _d_first_beats1_decode_T = 27'hFFF << anonOut_d_bits_size; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = anonOut_d_bits_opcode[0]; // @[Edges.scala:106:36]
wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire d_first_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T = d_first_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire _d_first_T_1 = anonOut_d_bits_opcode != 3'h6; // @[FIFOFixer.scala:75:63]
wire d_first = d_first_first & _d_first_T_1; // @[FIFOFixer.scala:75:{42,63}]
reg flight_0; // @[FIFOFixer.scala:79:27]
reg flight_1; // @[FIFOFixer.scala:79:27]
reg flight_2; // @[FIFOFixer.scala:79:27]
reg flight_3; // @[FIFOFixer.scala:79:27]
reg flight_4; // @[FIFOFixer.scala:79:27]
reg flight_5; // @[FIFOFixer.scala:79:27]
reg flight_6; // @[FIFOFixer.scala:79:27]
reg flight_7; // @[FIFOFixer.scala:79:27]
reg flight_8; // @[FIFOFixer.scala:79:27]
reg flight_9; // @[FIFOFixer.scala:79:27]
reg flight_10; // @[FIFOFixer.scala:79:27]
reg flight_11; // @[FIFOFixer.scala:79:27]
reg flight_12; // @[FIFOFixer.scala:79:27]
reg flight_13; // @[FIFOFixer.scala:79:27]
reg flight_14; // @[FIFOFixer.scala:79:27]
reg flight_15; // @[FIFOFixer.scala:79:27]
reg flight_16; // @[FIFOFixer.scala:79:27]
reg flight_17; // @[FIFOFixer.scala:79:27]
reg flight_18; // @[FIFOFixer.scala:79:27]
reg flight_19; // @[FIFOFixer.scala:79:27]
reg flight_20; // @[FIFOFixer.scala:79:27]
reg flight_21; // @[FIFOFixer.scala:79:27]
reg flight_22; // @[FIFOFixer.scala:79:27]
reg flight_23; // @[FIFOFixer.scala:79:27]
reg flight_24; // @[FIFOFixer.scala:79:27]
reg flight_25; // @[FIFOFixer.scala:79:27]
reg flight_26; // @[FIFOFixer.scala:79:27]
reg flight_27; // @[FIFOFixer.scala:79:27]
reg flight_28; // @[FIFOFixer.scala:79:27]
reg flight_29; // @[FIFOFixer.scala:79:27]
reg flight_30; // @[FIFOFixer.scala:79:27]
reg flight_31; // @[FIFOFixer.scala:79:27]
reg flight_32; // @[FIFOFixer.scala:79:27]
wire _T_9 = anonIn_d_ready & anonIn_d_valid; // @[Decoupled.scala:51:35]
wire [2:0] stalls_a_sel_uncommonBits = _stalls_a_sel_uncommonBits_T[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] _stalls_a_sel_T = anonIn_a_bits_source[5:3]; // @[Parameters.scala:54:10]
wire [2:0] _stalls_a_sel_T_5 = anonIn_a_bits_source[5:3]; // @[Parameters.scala:54:10]
wire _stalls_a_sel_T_1 = _stalls_a_sel_T == 3'h2; // @[Parameters.scala:54:{10,32}]
wire _stalls_a_sel_T_3 = _stalls_a_sel_T_1; // @[Parameters.scala:54:{32,67}]
wire stalls_a_sel = _stalls_a_sel_T_3; // @[Parameters.scala:54:67, :56:48]
wire _stalls_id_T_1 = _stalls_id_T & stalls_a_sel; // @[Decoupled.scala:51:35]
wire _stalls_id_T_3 = _stalls_id_T_1; // @[FIFOFixer.scala:85:{47,56}]
reg [1:0] stalls_id; // @[FIFOFixer.scala:85:30]
wire _stalls_T = stalls_a_sel & a_first; // @[FIFOFixer.scala:88:15]
wire _stalls_T_1 = flight_16 | flight_17; // @[FIFOFixer.scala:79:27, :88:44]
wire _stalls_T_2 = _stalls_T_1 | flight_18; // @[FIFOFixer.scala:79:27, :88:44]
wire _stalls_T_3 = _stalls_T_2 | flight_19; // @[FIFOFixer.scala:79:27, :88:44]
wire _stalls_T_4 = _stalls_T_3 | flight_20; // @[FIFOFixer.scala:79:27, :88:44]
wire _stalls_T_5 = _stalls_T_4 | flight_21; // @[FIFOFixer.scala:79:27, :88:44]
wire _stalls_T_6 = _stalls_T_5 | flight_22; // @[FIFOFixer.scala:79:27, :88:44]
wire _stalls_T_7 = _stalls_T_6 | flight_23; // @[FIFOFixer.scala:79:27, :88:44]
wire _stalls_T_8 = _stalls_T & _stalls_T_7; // @[FIFOFixer.scala:88:{15,26,44}]
wire _stalls_T_9 = stalls_id != a_id; // @[Mux.scala:30:73]
wire _stalls_T_10 = a_noDomain | _stalls_T_9; // @[FIFOFixer.scala:63:29, :88:{65,71}]
wire stalls_0 = _stalls_T_8 & _stalls_T_10; // @[FIFOFixer.scala:88:{26,50,65}]
wire _stall_T = stalls_0; // @[FIFOFixer.scala:88:50, :91:45]
wire [2:0] stalls_a_sel_uncommonBits_1 = _stalls_a_sel_uncommonBits_T_1[2:0]; // @[Parameters.scala:52:{29,56}]
wire _stalls_a_sel_T_6 = _stalls_a_sel_T_5 == 3'h3; // @[Parameters.scala:54:{10,32}]
wire _stalls_a_sel_T_8 = _stalls_a_sel_T_6; // @[Parameters.scala:54:{32,67}]
wire stalls_a_sel_1 = _stalls_a_sel_T_8; // @[Parameters.scala:54:67, :56:48]
wire _stalls_id_T_5 = _stalls_id_T_4 & stalls_a_sel_1; // @[Decoupled.scala:51:35]
wire _stalls_id_T_7 = _stalls_id_T_5; // @[FIFOFixer.scala:85:{47,56}]
reg [1:0] stalls_id_1; // @[FIFOFixer.scala:85:30]
wire _stalls_T_11 = stalls_a_sel_1 & a_first; // @[FIFOFixer.scala:88:15]
wire _stalls_T_12 = flight_24 | flight_25; // @[FIFOFixer.scala:79:27, :88:44]
wire _stalls_T_13 = _stalls_T_12 | flight_26; // @[FIFOFixer.scala:79:27, :88:44]
wire _stalls_T_14 = _stalls_T_13 | flight_27; // @[FIFOFixer.scala:79:27, :88:44]
wire _stalls_T_15 = _stalls_T_14 | flight_28; // @[FIFOFixer.scala:79:27, :88:44]
wire _stalls_T_16 = _stalls_T_15 | flight_29; // @[FIFOFixer.scala:79:27, :88:44]
wire _stalls_T_17 = _stalls_T_16 | flight_30; // @[FIFOFixer.scala:79:27, :88:44]
wire _stalls_T_18 = _stalls_T_17 | flight_31; // @[FIFOFixer.scala:79:27, :88:44]
wire _stalls_T_19 = _stalls_T_11 & _stalls_T_18; // @[FIFOFixer.scala:88:{15,26,44}]
wire _stalls_T_20 = stalls_id_1 != a_id; // @[Mux.scala:30:73]
wire _stalls_T_21 = a_noDomain | _stalls_T_20; // @[FIFOFixer.scala:63:29, :88:{65,71}]
wire stalls_1 = _stalls_T_19 & _stalls_T_21; // @[FIFOFixer.scala:88:{26,50,65}]
wire stall = _stall_T | stalls_1; // @[FIFOFixer.scala:88:50, :91:45]
wire _anonOut_a_valid_T = ~stall; // @[FIFOFixer.scala:91:45, :95:50]
wire _anonOut_a_valid_T_1 = _anonOut_a_valid_T; // @[FIFOFixer.scala:95:{47,50}]
assign _anonOut_a_valid_T_2 = anonIn_a_valid & _anonOut_a_valid_T_1; // @[FIFOFixer.scala:95:{33,47}]
assign anonOut_a_valid = _anonOut_a_valid_T_2; // @[FIFOFixer.scala:95:33]
wire _anonIn_a_ready_T = ~stall; // @[FIFOFixer.scala:91:45, :95:50, :96:50]
wire _anonIn_a_ready_T_1 = _anonIn_a_ready_T; // @[FIFOFixer.scala:96:{47,50}]
assign _anonIn_a_ready_T_2 = anonOut_a_ready & _anonIn_a_ready_T_1; // @[FIFOFixer.scala:96:{33,47}]
assign anonIn_a_ready = _anonIn_a_ready_T_2; // @[FIFOFixer.scala:96:33]
reg [32:0] SourceIdFIFOed; // @[FIFOFixer.scala:115:35]
wire [32:0] SourceIdSet; // @[FIFOFixer.scala:116:36]
wire [32:0] SourceIdClear; // @[FIFOFixer.scala:117:38]
wire [63:0] _SourceIdSet_T = 64'h1 << anonIn_a_bits_source; // @[OneHot.scala:58:35]
assign SourceIdSet = a_first & _T_5 ? _SourceIdSet_T[32:0] : 33'h0; // @[OneHot.scala:58:35]
wire [63:0] _SourceIdClear_T = 64'h1 << anonIn_d_bits_source; // @[OneHot.scala:58:35]
assign SourceIdClear = d_first & _T_9 ? _SourceIdClear_T[32:0] : 33'h0; // @[OneHot.scala:58:35]
wire [32:0] _SourceIdFIFOed_T = SourceIdFIFOed | SourceIdSet; // @[FIFOFixer.scala:115:35, :116:36, :126:40]
wire allIDs_FIFOed = &SourceIdFIFOed; // @[FIFOFixer.scala:115:35, :127:41]
wire [32:0] _a_notFIFO_T_6 = {1'h0, _a_notFIFO_T_5}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _a_id_T_14 = {1'h0, _a_id_T_13}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _a_id_T_15 = _a_id_T_14 & 33'h40000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _a_id_T_16 = _a_id_T_15; // @[Parameters.scala:137:46]
wire _a_id_T_17 = _a_id_T_16 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _a_id_T_23 = _a_id_T_17; // @[Mux.scala:30:73]
wire [31:0] _a_id_T_18 = {anonIn_1_a_bits_address[31], anonIn_1_a_bits_address[30:0] ^ 31'h40000000}; // @[Parameters.scala:137:31]
wire [32:0] _a_id_T_19 = {1'h0, _a_id_T_18}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _a_id_T_20 = _a_id_T_19 & 33'h40000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _a_id_T_21 = _a_id_T_20; // @[Parameters.scala:137:46]
wire _a_id_T_22 = _a_id_T_21 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [1:0] _a_id_T_24 = {_a_id_T_22, 1'h0}; // @[Mux.scala:30:73]
wire [1:0] _a_id_T_25 = {1'h0, _a_id_T_23} | _a_id_T_24; // @[Mux.scala:30:73]
wire [1:0] a_id_1 = _a_id_T_25; // @[Mux.scala:30:73]
wire a_noDomain_1 = a_id_1 == 2'h0; // @[Mux.scala:30:73]
wire _a_first_T_1 = anonIn_1_a_ready & anonIn_1_a_valid; // @[Decoupled.scala:51:35]
wire [26:0] _a_first_beats1_decode_T_3 = 27'hFFF << anonIn_1_a_bits_size; // @[package.scala:243:71]
wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T_1 = anonIn_1_a_bits_opcode[2]; // @[Edges.scala:92:37]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire _d_first_T_2 = x1_anonOut_d_ready & x1_anonOut_d_valid; // @[Decoupled.scala:51:35]
wire [26:0] _d_first_beats1_decode_T_3 = 27'hFFF << x1_anonOut_d_bits_size; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata_1 = x1_anonOut_d_bits_opcode[0]; // @[Edges.scala:106:36]
wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire d_first_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_1 = d_first_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire _d_first_T_3 = x1_anonOut_d_bits_opcode != 3'h6; // @[FIFOFixer.scala:75:63]
wire d_first_1 = d_first_first_1 & _d_first_T_3; // @[FIFOFixer.scala:75:{42,63}]
reg flight_1_0; // @[FIFOFixer.scala:79:27]
reg flight_1_1; // @[FIFOFixer.scala:79:27]
wire _T_55 = anonIn_1_d_ready & anonIn_1_d_valid; // @[Decoupled.scala:51:35]
assign x1_anonOut_a_valid = _anonOut_a_valid_T_5; // @[FIFOFixer.scala:95:33]
assign anonIn_1_a_ready = _anonIn_a_ready_T_5; // @[FIFOFixer.scala:96:33]
reg [1:0] SourceIdFIFOed_1; // @[FIFOFixer.scala:115:35]
wire [1:0] SourceIdSet_1; // @[FIFOFixer.scala:116:36]
wire [1:0] SourceIdClear_1; // @[FIFOFixer.scala:117:38]
wire [1:0] _SourceIdSet_T_1 = 2'h1 << anonIn_1_a_bits_source; // @[OneHot.scala:58:35]
assign SourceIdSet_1 = a_first_1 & _a_first_T_1 ? _SourceIdSet_T_1 : 2'h0; // @[OneHot.scala:58:35]
wire [1:0] _SourceIdClear_T_1 = 2'h1 << anonIn_1_d_bits_source; // @[OneHot.scala:58:35]
assign SourceIdClear_1 = d_first_1 & _T_55 ? _SourceIdClear_T_1 : 2'h0; // @[OneHot.scala:58:35]
wire [1:0] _SourceIdFIFOed_T_1 = SourceIdFIFOed_1 | SourceIdSet_1; // @[FIFOFixer.scala:115:35, :116:36, :126:40]
wire allIDs_FIFOed_1 = &SourceIdFIFOed_1; // @[FIFOFixer.scala:115:35, :127:41]
wire _T_1 = a_first & _T_5; // @[Decoupled.scala:51:35]
wire _T_3 = d_first & _T_9; // @[Decoupled.scala:51:35]
wire _T_47 = a_first_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire _T_49 = d_first_1 & _T_55; // @[Decoupled.scala:51:35]
always @(posedge clock) begin // @[FIFOFixer.scala:50:9]
if (reset) begin // @[FIFOFixer.scala:50:9]
a_first_counter <= 9'h0; // @[Edges.scala:229:27]
d_first_counter <= 9'h0; // @[Edges.scala:229:27]
flight_0 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_1 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_2 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_3 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_4 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_5 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_6 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_7 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_8 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_9 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_10 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_11 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_12 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_13 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_14 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_15 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_16 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_17 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_18 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_19 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_20 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_21 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_22 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_23 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_24 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_25 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_26 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_27 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_28 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_29 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_30 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_31 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_32 <= 1'h0; // @[FIFOFixer.scala:79:27]
SourceIdFIFOed <= 33'h0; // @[FIFOFixer.scala:115:35]
a_first_counter_1 <= 9'h0; // @[Edges.scala:229:27]
d_first_counter_1 <= 9'h0; // @[Edges.scala:229:27]
flight_1_0 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_1_1 <= 1'h0; // @[FIFOFixer.scala:79:27]
SourceIdFIFOed_1 <= 2'h0; // @[FIFOFixer.scala:115:35]
end
else begin // @[FIFOFixer.scala:50:9]
if (_a_first_T) // @[Decoupled.scala:51:35]
a_first_counter <= _a_first_counter_T; // @[Edges.scala:229:27, :236:21]
if (_d_first_T) // @[Decoupled.scala:51:35]
d_first_counter <= _d_first_counter_T; // @[Edges.scala:229:27, :236:21]
flight_0 <= ~(_T_3 & anonIn_d_bits_source == 6'h0) & (_T_1 & anonIn_a_bits_source == 6'h0 | flight_0); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_1 <= ~(_T_3 & anonIn_d_bits_source == 6'h1) & (_T_1 & anonIn_a_bits_source == 6'h1 | flight_1); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_2 <= ~(_T_3 & anonIn_d_bits_source == 6'h2) & (_T_1 & anonIn_a_bits_source == 6'h2 | flight_2); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_3 <= ~(_T_3 & anonIn_d_bits_source == 6'h3) & (_T_1 & anonIn_a_bits_source == 6'h3 | flight_3); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_4 <= ~(_T_3 & anonIn_d_bits_source == 6'h4) & (_T_1 & anonIn_a_bits_source == 6'h4 | flight_4); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_5 <= ~(_T_3 & anonIn_d_bits_source == 6'h5) & (_T_1 & anonIn_a_bits_source == 6'h5 | flight_5); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_6 <= ~(_T_3 & anonIn_d_bits_source == 6'h6) & (_T_1 & anonIn_a_bits_source == 6'h6 | flight_6); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_7 <= ~(_T_3 & anonIn_d_bits_source == 6'h7) & (_T_1 & anonIn_a_bits_source == 6'h7 | flight_7); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_8 <= ~(_T_3 & anonIn_d_bits_source == 6'h8) & (_T_1 & anonIn_a_bits_source == 6'h8 | flight_8); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_9 <= ~(_T_3 & anonIn_d_bits_source == 6'h9) & (_T_1 & anonIn_a_bits_source == 6'h9 | flight_9); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_10 <= ~(_T_3 & anonIn_d_bits_source == 6'hA) & (_T_1 & anonIn_a_bits_source == 6'hA | flight_10); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_11 <= ~(_T_3 & anonIn_d_bits_source == 6'hB) & (_T_1 & anonIn_a_bits_source == 6'hB | flight_11); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_12 <= ~(_T_3 & anonIn_d_bits_source == 6'hC) & (_T_1 & anonIn_a_bits_source == 6'hC | flight_12); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_13 <= ~(_T_3 & anonIn_d_bits_source == 6'hD) & (_T_1 & anonIn_a_bits_source == 6'hD | flight_13); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_14 <= ~(_T_3 & anonIn_d_bits_source == 6'hE) & (_T_1 & anonIn_a_bits_source == 6'hE | flight_14); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_15 <= ~(_T_3 & anonIn_d_bits_source == 6'hF) & (_T_1 & anonIn_a_bits_source == 6'hF | flight_15); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_16 <= ~(_T_3 & anonIn_d_bits_source == 6'h10) & (_T_1 & anonIn_a_bits_source == 6'h10 | flight_16); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_17 <= ~(_T_3 & anonIn_d_bits_source == 6'h11) & (_T_1 & anonIn_a_bits_source == 6'h11 | flight_17); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_18 <= ~(_T_3 & anonIn_d_bits_source == 6'h12) & (_T_1 & anonIn_a_bits_source == 6'h12 | flight_18); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_19 <= ~(_T_3 & anonIn_d_bits_source == 6'h13) & (_T_1 & anonIn_a_bits_source == 6'h13 | flight_19); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_20 <= ~(_T_3 & anonIn_d_bits_source == 6'h14) & (_T_1 & anonIn_a_bits_source == 6'h14 | flight_20); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_21 <= ~(_T_3 & anonIn_d_bits_source == 6'h15) & (_T_1 & anonIn_a_bits_source == 6'h15 | flight_21); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_22 <= ~(_T_3 & anonIn_d_bits_source == 6'h16) & (_T_1 & anonIn_a_bits_source == 6'h16 | flight_22); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_23 <= ~(_T_3 & anonIn_d_bits_source == 6'h17) & (_T_1 & anonIn_a_bits_source == 6'h17 | flight_23); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_24 <= ~(_T_3 & anonIn_d_bits_source == 6'h18) & (_T_1 & anonIn_a_bits_source == 6'h18 | flight_24); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_25 <= ~(_T_3 & anonIn_d_bits_source == 6'h19) & (_T_1 & anonIn_a_bits_source == 6'h19 | flight_25); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_26 <= ~(_T_3 & anonIn_d_bits_source == 6'h1A) & (_T_1 & anonIn_a_bits_source == 6'h1A | flight_26); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_27 <= ~(_T_3 & anonIn_d_bits_source == 6'h1B) & (_T_1 & anonIn_a_bits_source == 6'h1B | flight_27); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_28 <= ~(_T_3 & anonIn_d_bits_source == 6'h1C) & (_T_1 & anonIn_a_bits_source == 6'h1C | flight_28); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_29 <= ~(_T_3 & anonIn_d_bits_source == 6'h1D) & (_T_1 & anonIn_a_bits_source == 6'h1D | flight_29); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_30 <= ~(_T_3 & anonIn_d_bits_source == 6'h1E) & (_T_1 & anonIn_a_bits_source == 6'h1E | flight_30); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_31 <= ~(_T_3 & anonIn_d_bits_source == 6'h1F) & (_T_1 & anonIn_a_bits_source == 6'h1F | flight_31); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_32 <= ~(_T_3 & anonIn_d_bits_source == 6'h20) & (_T_1 & anonIn_a_bits_source == 6'h20 | flight_32); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
SourceIdFIFOed <= _SourceIdFIFOed_T; // @[FIFOFixer.scala:115:35, :126:40]
if (_a_first_T_1) // @[Decoupled.scala:51:35]
a_first_counter_1 <= _a_first_counter_T_1; // @[Edges.scala:229:27, :236:21]
if (_d_first_T_2) // @[Decoupled.scala:51:35]
d_first_counter_1 <= _d_first_counter_T_1; // @[Edges.scala:229:27, :236:21]
flight_1_0 <= ~(_T_49 & ~anonIn_1_d_bits_source) & (_T_47 & ~anonIn_1_a_bits_source | flight_1_0); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_1_1 <= ~(_T_49 & anonIn_1_d_bits_source) & (_T_47 & anonIn_1_a_bits_source | flight_1_1); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
SourceIdFIFOed_1 <= _SourceIdFIFOed_T_1; // @[FIFOFixer.scala:115:35, :126:40]
end
if (_stalls_id_T_3) // @[FIFOFixer.scala:85:56]
stalls_id <= a_id; // @[Mux.scala:30:73]
if (_stalls_id_T_7) // @[FIFOFixer.scala:85:56]
stalls_id_1 <= a_id; // @[Mux.scala:30:73]
always @(posedge)
TLMonitor_2 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (anonIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (anonIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (anonIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (anonIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (anonIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (anonIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (anonIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_user_amba_prot_bufferable (anonIn_a_bits_user_amba_prot_bufferable), // @[MixedNode.scala:551:17]
.io_in_a_bits_user_amba_prot_modifiable (anonIn_a_bits_user_amba_prot_modifiable), // @[MixedNode.scala:551:17]
.io_in_a_bits_user_amba_prot_readalloc (anonIn_a_bits_user_amba_prot_readalloc), // @[MixedNode.scala:551:17]
.io_in_a_bits_user_amba_prot_writealloc (anonIn_a_bits_user_amba_prot_writealloc), // @[MixedNode.scala:551:17]
.io_in_a_bits_user_amba_prot_privileged (anonIn_a_bits_user_amba_prot_privileged), // @[MixedNode.scala:551:17]
.io_in_a_bits_user_amba_prot_secure (anonIn_a_bits_user_amba_prot_secure), // @[MixedNode.scala:551:17]
.io_in_a_bits_user_amba_prot_fetch (anonIn_a_bits_user_amba_prot_fetch), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (anonIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (anonIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_a_bits_corrupt (anonIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_d_ready (anonIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (anonIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (anonIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_param (anonIn_d_bits_param), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (anonIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (anonIn_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_sink (anonIn_d_bits_sink), // @[MixedNode.scala:551:17]
.io_in_d_bits_denied (anonIn_d_bits_denied), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (anonIn_d_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_bits_corrupt (anonIn_d_bits_corrupt) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
TLMonitor_3 monitor_1 ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (anonIn_1_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (anonIn_1_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (anonIn_1_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (anonIn_1_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (anonIn_1_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (anonIn_1_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (anonIn_1_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_user_amba_prot_bufferable (anonIn_1_a_bits_user_amba_prot_bufferable), // @[MixedNode.scala:551:17]
.io_in_a_bits_user_amba_prot_modifiable (anonIn_1_a_bits_user_amba_prot_modifiable), // @[MixedNode.scala:551:17]
.io_in_a_bits_user_amba_prot_readalloc (anonIn_1_a_bits_user_amba_prot_readalloc), // @[MixedNode.scala:551:17]
.io_in_a_bits_user_amba_prot_writealloc (anonIn_1_a_bits_user_amba_prot_writealloc), // @[MixedNode.scala:551:17]
.io_in_a_bits_user_amba_prot_privileged (anonIn_1_a_bits_user_amba_prot_privileged), // @[MixedNode.scala:551:17]
.io_in_a_bits_user_amba_prot_secure (anonIn_1_a_bits_user_amba_prot_secure), // @[MixedNode.scala:551:17]
.io_in_a_bits_user_amba_prot_fetch (anonIn_1_a_bits_user_amba_prot_fetch), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (anonIn_1_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (anonIn_1_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_a_bits_corrupt (anonIn_1_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_d_ready (anonIn_1_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (anonIn_1_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (anonIn_1_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_param (anonIn_1_d_bits_param), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (anonIn_1_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (anonIn_1_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_sink (anonIn_1_d_bits_sink), // @[MixedNode.scala:551:17]
.io_in_d_bits_denied (anonIn_1_d_bits_denied), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (anonIn_1_d_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_bits_corrupt (anonIn_1_d_bits_corrupt) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
assign auto_anon_in_1_a_ready = auto_anon_in_1_a_ready_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_in_1_d_valid = auto_anon_in_1_d_valid_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_in_1_d_bits_opcode = auto_anon_in_1_d_bits_opcode_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_in_1_d_bits_param = auto_anon_in_1_d_bits_param_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_in_1_d_bits_size = auto_anon_in_1_d_bits_size_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_in_1_d_bits_source = auto_anon_in_1_d_bits_source_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_in_1_d_bits_sink = auto_anon_in_1_d_bits_sink_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_in_1_d_bits_denied = auto_anon_in_1_d_bits_denied_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_in_1_d_bits_data = auto_anon_in_1_d_bits_data_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_in_1_d_bits_corrupt = auto_anon_in_1_d_bits_corrupt_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_in_0_a_ready = auto_anon_in_0_a_ready_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_in_0_d_valid = auto_anon_in_0_d_valid_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_in_0_d_bits_opcode = auto_anon_in_0_d_bits_opcode_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_in_0_d_bits_param = auto_anon_in_0_d_bits_param_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_in_0_d_bits_size = auto_anon_in_0_d_bits_size_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_in_0_d_bits_source = auto_anon_in_0_d_bits_source_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_in_0_d_bits_sink = auto_anon_in_0_d_bits_sink_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_in_0_d_bits_denied = auto_anon_in_0_d_bits_denied_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_in_0_d_bits_data = auto_anon_in_0_d_bits_data_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_in_0_d_bits_corrupt = auto_anon_in_0_d_bits_corrupt_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_1_a_valid = auto_anon_out_1_a_valid_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_1_a_bits_opcode = auto_anon_out_1_a_bits_opcode_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_1_a_bits_param = auto_anon_out_1_a_bits_param_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_1_a_bits_size = auto_anon_out_1_a_bits_size_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_1_a_bits_source = auto_anon_out_1_a_bits_source_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_1_a_bits_address = auto_anon_out_1_a_bits_address_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_1_a_bits_user_amba_prot_bufferable = auto_anon_out_1_a_bits_user_amba_prot_bufferable_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_1_a_bits_user_amba_prot_modifiable = auto_anon_out_1_a_bits_user_amba_prot_modifiable_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_1_a_bits_user_amba_prot_readalloc = auto_anon_out_1_a_bits_user_amba_prot_readalloc_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_1_a_bits_user_amba_prot_writealloc = auto_anon_out_1_a_bits_user_amba_prot_writealloc_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_1_a_bits_user_amba_prot_privileged = auto_anon_out_1_a_bits_user_amba_prot_privileged_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_1_a_bits_user_amba_prot_secure = auto_anon_out_1_a_bits_user_amba_prot_secure_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_1_a_bits_user_amba_prot_fetch = auto_anon_out_1_a_bits_user_amba_prot_fetch_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_1_a_bits_mask = auto_anon_out_1_a_bits_mask_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_1_a_bits_data = auto_anon_out_1_a_bits_data_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_1_a_bits_corrupt = auto_anon_out_1_a_bits_corrupt_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_1_d_ready = auto_anon_out_1_d_ready_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_0_a_valid = auto_anon_out_0_a_valid_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_0_a_bits_opcode = auto_anon_out_0_a_bits_opcode_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_0_a_bits_param = auto_anon_out_0_a_bits_param_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_0_a_bits_size = auto_anon_out_0_a_bits_size_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_0_a_bits_source = auto_anon_out_0_a_bits_source_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_0_a_bits_address = auto_anon_out_0_a_bits_address_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_0_a_bits_user_amba_prot_bufferable = auto_anon_out_0_a_bits_user_amba_prot_bufferable_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_0_a_bits_user_amba_prot_modifiable = auto_anon_out_0_a_bits_user_amba_prot_modifiable_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_0_a_bits_user_amba_prot_readalloc = auto_anon_out_0_a_bits_user_amba_prot_readalloc_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_0_a_bits_user_amba_prot_writealloc = auto_anon_out_0_a_bits_user_amba_prot_writealloc_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_0_a_bits_user_amba_prot_privileged = auto_anon_out_0_a_bits_user_amba_prot_privileged_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_0_a_bits_user_amba_prot_secure = auto_anon_out_0_a_bits_user_amba_prot_secure_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_0_a_bits_user_amba_prot_fetch = auto_anon_out_0_a_bits_user_amba_prot_fetch_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_0_a_bits_mask = auto_anon_out_0_a_bits_mask_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_0_a_bits_data = auto_anon_out_0_a_bits_data_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_0_a_bits_corrupt = auto_anon_out_0_a_bits_corrupt_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_0_d_ready = auto_anon_out_0_d_ready_0; // @[FIFOFixer.scala:50:9]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Transposer.scala:
package gemmini
import chisel3._
import chisel3.util._
import Util._
trait Transposer[T <: Data] extends Module {
def dim: Int
def dataType: T
val io = IO(new Bundle {
val inRow = Flipped(Decoupled(Vec(dim, dataType)))
val outCol = Decoupled(Vec(dim, dataType))
})
}
class PipelinedTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] {
require(isPow2(dim))
val regArray = Seq.fill(dim, dim)(Reg(dataType))
val regArrayT = regArray.transpose
val sMoveUp :: sMoveLeft :: Nil = Enum(2)
val state = RegInit(sMoveUp)
val leftCounter = RegInit(0.U(log2Ceil(dim+1).W)) //(io.inRow.fire && state === sMoveLeft, dim+1)
val upCounter = RegInit(0.U(log2Ceil(dim+1).W)) //Counter(io.inRow.fire && state === sMoveUp, dim+1)
io.outCol.valid := 0.U
io.inRow.ready := 0.U
switch(state) {
is(sMoveUp) {
io.inRow.ready := upCounter <= dim.U
io.outCol.valid := leftCounter > 0.U
when(io.inRow.fire) {
upCounter := upCounter + 1.U
}
when(upCounter === (dim-1).U) {
state := sMoveLeft
leftCounter := 0.U
}
when(io.outCol.fire) {
leftCounter := leftCounter - 1.U
}
}
is(sMoveLeft) {
io.inRow.ready := leftCounter <= dim.U // TODO: this is naive
io.outCol.valid := upCounter > 0.U
when(leftCounter === (dim-1).U) {
state := sMoveUp
}
when(io.inRow.fire) {
leftCounter := leftCounter + 1.U
upCounter := 0.U
}
when(io.outCol.fire) {
upCounter := upCounter - 1.U
}
}
}
// Propagate input from bottom row to top row systolically in the move up phase
// TODO: need to iterate over columns to connect Chisel values of type T
// Should be able to operate directly on the Vec, but Seq and Vec don't mix (try Array?)
for (colIdx <- 0 until dim) {
regArray.foldRight(io.inRow.bits(colIdx)) {
case (regRow, prevReg) =>
when (state === sMoveUp) {
regRow(colIdx) := prevReg
}
regRow(colIdx)
}
}
// Propagate input from right side to left side systolically in the move left phase
for (rowIdx <- 0 until dim) {
regArrayT.foldRight(io.inRow.bits(rowIdx)) {
case (regCol, prevReg) =>
when (state === sMoveLeft) {
regCol(rowIdx) := prevReg
}
regCol(rowIdx)
}
}
// Pull from the left side or the top side based on the state
for (idx <- 0 until dim) {
when (state === sMoveUp) {
io.outCol.bits(idx) := regArray(0)(idx)
}.elsewhen(state === sMoveLeft) {
io.outCol.bits(idx) := regArrayT(0)(idx)
}.otherwise {
io.outCol.bits(idx) := DontCare
}
}
}
class AlwaysOutTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] {
require(isPow2(dim))
val LEFT_DIR = 0.U(1.W)
val UP_DIR = 1.U(1.W)
class PE extends Module {
val io = IO(new Bundle {
val inR = Input(dataType)
val inD = Input(dataType)
val outL = Output(dataType)
val outU = Output(dataType)
val dir = Input(UInt(1.W))
val en = Input(Bool())
})
val reg = RegEnable(Mux(io.dir === LEFT_DIR, io.inR, io.inD), io.en)
io.outU := reg
io.outL := reg
}
val pes = Seq.fill(dim,dim)(Module(new PE))
val counter = RegInit(0.U((log2Ceil(dim) max 1).W)) // TODO replace this with a standard Chisel counter
val dir = RegInit(LEFT_DIR)
// Wire up horizontal signals
for (row <- 0 until dim; col <- 0 until dim) {
val right_in = if (col == dim-1) io.inRow.bits(row) else pes(row)(col+1).io.outL
pes(row)(col).io.inR := right_in
}
// Wire up vertical signals
for (row <- 0 until dim; col <- 0 until dim) {
val down_in = if (row == dim-1) io.inRow.bits(col) else pes(row+1)(col).io.outU
pes(row)(col).io.inD := down_in
}
// Wire up global signals
pes.flatten.foreach(_.io.dir := dir)
pes.flatten.foreach(_.io.en := io.inRow.fire)
io.outCol.valid := true.B
io.inRow.ready := true.B
val left_out = VecInit(pes.transpose.head.map(_.io.outL))
val up_out = VecInit(pes.head.map(_.io.outU))
io.outCol.bits := Mux(dir === LEFT_DIR, left_out, up_out)
when (io.inRow.fire) {
counter := wrappingAdd(counter, 1.U, dim)
}
when (counter === (dim-1).U && io.inRow.fire) {
dir := ~dir
}
}
class NaiveTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] {
val regArray = Seq.fill(dim, dim)(Reg(dataType))
val regArrayT = regArray.transpose
// state = 0 => filling regArray row-wise, state = 1 => draining regArray column-wise
val state = RegInit(0.U(1.W))
val countInc = io.inRow.fire || io.outCol.fire
val (countValue, countWrap) = Counter(countInc, dim)
io.inRow.ready := state === 0.U
io.outCol.valid := state === 1.U
for (i <- 0 until dim) {
for (j <- 0 until dim) {
when(countValue === i.U && io.inRow.fire) {
regArray(i)(j) := io.inRow.bits(j)
}
}
}
for (i <- 0 until dim) {
io.outCol.bits(i) := 0.U
for (j <- 0 until dim) {
when(countValue === j.U) {
io.outCol.bits(i) := regArrayT(j)(i)
}
}
}
when (io.inRow.fire && countWrap) {
state := 1.U
}
when (io.outCol.fire && countWrap) {
state := 0.U
}
assert(!(state === 0.U) || !io.outCol.fire)
assert(!(state === 1.U) || !io.inRow.fire)
}
| module PE_220( // @[Transposer.scala:100:9]
input clock, // @[Transposer.scala:100:9]
input reset, // @[Transposer.scala:100:9]
input [7:0] io_inR, // @[Transposer.scala:101:16]
input [7:0] io_inD, // @[Transposer.scala:101:16]
output [7:0] io_outL, // @[Transposer.scala:101:16]
output [7:0] io_outU, // @[Transposer.scala:101:16]
input io_dir, // @[Transposer.scala:101:16]
input io_en // @[Transposer.scala:101:16]
);
wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9]
wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9]
wire io_dir_0 = io_dir; // @[Transposer.scala:100:9]
wire io_en_0 = io_en; // @[Transposer.scala:100:9]
wire [7:0] io_outL_0; // @[Transposer.scala:100:9]
wire [7:0] io_outU_0; // @[Transposer.scala:100:9]
wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36]
wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}]
reg [7:0] reg_0; // @[Transposer.scala:110:24]
assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24]
assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24]
always @(posedge clock) begin // @[Transposer.scala:100:9]
if (io_en_0) // @[Transposer.scala:100:9]
reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}]
always @(posedge)
assign io_outL = io_outL_0; // @[Transposer.scala:100:9]
assign io_outU = io_outU_0; // @[Transposer.scala:100:9]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File PMP.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util.{Cat, log2Ceil}
import org.chipsalliance.cde.config._
import freechips.rocketchip.tile._
import freechips.rocketchip.util._
class PMPConfig extends Bundle {
val l = Bool()
val res = UInt(2.W)
val a = UInt(2.W)
val x = Bool()
val w = Bool()
val r = Bool()
}
object PMP {
def lgAlign = 2
def apply(reg: PMPReg): PMP = {
val pmp = Wire(new PMP()(reg.p))
pmp.cfg := reg.cfg
pmp.addr := reg.addr
pmp.mask := pmp.computeMask
pmp
}
}
class PMPReg(implicit p: Parameters) extends CoreBundle()(p) {
val cfg = new PMPConfig
val addr = UInt((paddrBits - PMP.lgAlign).W)
def reset(): Unit = {
cfg.a := 0.U
cfg.l := 0.U
}
def readAddr = if (pmpGranularity.log2 == PMP.lgAlign) addr else {
val mask = ((BigInt(1) << (pmpGranularity.log2 - PMP.lgAlign)) - 1).U
Mux(napot, addr | (mask >> 1), ~(~addr | mask))
}
def napot = cfg.a(1)
def torNotNAPOT = cfg.a(0)
def tor = !napot && torNotNAPOT
def cfgLocked = cfg.l
def addrLocked(next: PMPReg) = cfgLocked || next.cfgLocked && next.tor
}
class PMP(implicit p: Parameters) extends PMPReg {
val mask = UInt(paddrBits.W)
import PMP._
def computeMask = {
val base = Cat(addr, cfg.a(0)) | ((pmpGranularity - 1).U >> lgAlign)
Cat(base & ~(base + 1.U), ((1 << lgAlign) - 1).U)
}
private def comparand = ~(~(addr << lgAlign) | (pmpGranularity - 1).U)
private def pow2Match(x: UInt, lgSize: UInt, lgMaxSize: Int) = {
def eval(a: UInt, b: UInt, m: UInt) = ((a ^ b) & ~m) === 0.U
if (lgMaxSize <= pmpGranularity.log2) {
eval(x, comparand, mask)
} else {
// break up the circuit; the MSB part will be CSE'd
val lsbMask = mask | UIntToOH1(lgSize, lgMaxSize)
val msbMatch = eval(x >> lgMaxSize, comparand >> lgMaxSize, mask >> lgMaxSize)
val lsbMatch = eval(x(lgMaxSize-1, 0), comparand(lgMaxSize-1, 0), lsbMask(lgMaxSize-1, 0))
msbMatch && lsbMatch
}
}
private def boundMatch(x: UInt, lsbMask: UInt, lgMaxSize: Int) = {
if (lgMaxSize <= pmpGranularity.log2) {
x < comparand
} else {
// break up the circuit; the MSB part will be CSE'd
val msbsLess = (x >> lgMaxSize) < (comparand >> lgMaxSize)
val msbsEqual = ((x >> lgMaxSize) ^ (comparand >> lgMaxSize)) === 0.U
val lsbsLess = (x(lgMaxSize-1, 0) | lsbMask) < comparand(lgMaxSize-1, 0)
msbsLess || (msbsEqual && lsbsLess)
}
}
private def lowerBoundMatch(x: UInt, lgSize: UInt, lgMaxSize: Int) =
!boundMatch(x, UIntToOH1(lgSize, lgMaxSize), lgMaxSize)
private def upperBoundMatch(x: UInt, lgMaxSize: Int) =
boundMatch(x, 0.U, lgMaxSize)
private def rangeMatch(x: UInt, lgSize: UInt, lgMaxSize: Int, prev: PMP) =
prev.lowerBoundMatch(x, lgSize, lgMaxSize) && upperBoundMatch(x, lgMaxSize)
private def pow2Homogeneous(x: UInt, pgLevel: UInt) = {
val maskHomogeneous = pgLevelMap { idxBits => if (idxBits > paddrBits) false.B else mask(idxBits - 1) } (pgLevel)
maskHomogeneous || (pgLevelMap { idxBits => ((x ^ comparand) >> idxBits) =/= 0.U } (pgLevel))
}
private def pgLevelMap[T](f: Int => T) = (0 until pgLevels).map { i =>
f(pgIdxBits + (pgLevels - 1 - i) * pgLevelBits)
}
private def rangeHomogeneous(x: UInt, pgLevel: UInt, prev: PMP) = {
val beginsAfterLower = !(x < prev.comparand)
val beginsAfterUpper = !(x < comparand)
val pgMask = pgLevelMap { idxBits => (((BigInt(1) << paddrBits) - (BigInt(1) << idxBits)) max 0).U } (pgLevel)
val endsBeforeLower = (x & pgMask) < (prev.comparand & pgMask)
val endsBeforeUpper = (x & pgMask) < (comparand & pgMask)
endsBeforeLower || beginsAfterUpper || (beginsAfterLower && endsBeforeUpper)
}
// returns whether this PMP completely contains, or contains none of, a page
def homogeneous(x: UInt, pgLevel: UInt, prev: PMP): Bool =
Mux(napot, pow2Homogeneous(x, pgLevel), !torNotNAPOT || rangeHomogeneous(x, pgLevel, prev))
// returns whether this matching PMP fully contains the access
def aligned(x: UInt, lgSize: UInt, lgMaxSize: Int, prev: PMP): Bool = if (lgMaxSize <= pmpGranularity.log2) true.B else {
val lsbMask = UIntToOH1(lgSize, lgMaxSize)
val straddlesLowerBound = ((x >> lgMaxSize) ^ (prev.comparand >> lgMaxSize)) === 0.U && (prev.comparand(lgMaxSize-1, 0) & ~x(lgMaxSize-1, 0)) =/= 0.U
val straddlesUpperBound = ((x >> lgMaxSize) ^ (comparand >> lgMaxSize)) === 0.U && (comparand(lgMaxSize-1, 0) & (x(lgMaxSize-1, 0) | lsbMask)) =/= 0.U
val rangeAligned = !(straddlesLowerBound || straddlesUpperBound)
val pow2Aligned = (lsbMask & ~mask(lgMaxSize-1, 0)) === 0.U
Mux(napot, pow2Aligned, rangeAligned)
}
// returns whether this PMP matches at least one byte of the access
def hit(x: UInt, lgSize: UInt, lgMaxSize: Int, prev: PMP): Bool =
Mux(napot, pow2Match(x, lgSize, lgMaxSize), torNotNAPOT && rangeMatch(x, lgSize, lgMaxSize, prev))
}
class PMPHomogeneityChecker(pmps: Seq[PMP])(implicit p: Parameters) {
def apply(addr: UInt, pgLevel: UInt): Bool = {
pmps.foldLeft((true.B, 0.U.asTypeOf(new PMP))) { case ((h, prev), pmp) =>
(h && pmp.homogeneous(addr, pgLevel, prev), pmp)
}._1
}
}
class PMPChecker(lgMaxSize: Int)(implicit val p: Parameters) extends Module
with HasCoreParameters {
override def desiredName = s"PMPChecker_s${lgMaxSize}"
val io = IO(new Bundle {
val prv = Input(UInt(PRV.SZ.W))
val pmp = Input(Vec(nPMPs, new PMP))
val addr = Input(UInt(paddrBits.W))
val size = Input(UInt(log2Ceil(lgMaxSize + 1).W))
val r = Output(Bool())
val w = Output(Bool())
val x = Output(Bool())
})
val default = if (io.pmp.isEmpty) true.B else io.prv > PRV.S.U
val pmp0 = WireInit(0.U.asTypeOf(new PMP))
pmp0.cfg.r := default
pmp0.cfg.w := default
pmp0.cfg.x := default
val res = (io.pmp zip (pmp0 +: io.pmp)).reverse.foldLeft(pmp0) { case (prev, (pmp, prevPMP)) =>
val hit = pmp.hit(io.addr, io.size, lgMaxSize, prevPMP)
val ignore = default && !pmp.cfg.l
val aligned = pmp.aligned(io.addr, io.size, lgMaxSize, prevPMP)
for ((name, idx) <- Seq("no", "TOR", if (pmpGranularity <= 4) "NA4" else "", "NAPOT").zipWithIndex; if name.nonEmpty)
property.cover(pmp.cfg.a === idx.U, s"The cfg access is set to ${name} access ", "Cover PMP access mode setting")
property.cover(pmp.cfg.l === 0x1.U, s"The cfg lock is set to high ", "Cover PMP lock mode setting")
// Not including Write and no Read permission as the combination is reserved
for ((name, idx) <- Seq("no", "RO", "", "RW", "X", "RX", "", "RWX").zipWithIndex; if name.nonEmpty)
property.cover((Cat(pmp.cfg.x, pmp.cfg.w, pmp.cfg.r) === idx.U), s"The permission is set to ${name} access ", "Cover PMP access permission setting")
for ((name, idx) <- Seq("", "TOR", if (pmpGranularity <= 4) "NA4" else "", "NAPOT").zipWithIndex; if name.nonEmpty) {
property.cover(!ignore && hit && aligned && pmp.cfg.a === idx.U, s"The access matches ${name} mode ", "Cover PMP access")
property.cover(pmp.cfg.l && hit && aligned && pmp.cfg.a === idx.U, s"The access matches ${name} mode with lock bit high", "Cover PMP access with lock bit")
}
val cur = WireInit(pmp)
cur.cfg.r := aligned && (pmp.cfg.r || ignore)
cur.cfg.w := aligned && (pmp.cfg.w || ignore)
cur.cfg.x := aligned && (pmp.cfg.x || ignore)
Mux(hit, cur, prev)
}
io.r := res.cfg.r
io.w := res.cfg.w
io.x := res.cfg.x
}
| module PMPChecker_s2( // @[PMP.scala:143:7]
input [1:0] io_prv, // @[PMP.scala:146:14]
input io_pmp_0_cfg_l, // @[PMP.scala:146:14]
input [1:0] io_pmp_0_cfg_a, // @[PMP.scala:146:14]
input io_pmp_0_cfg_x, // @[PMP.scala:146:14]
input io_pmp_0_cfg_w, // @[PMP.scala:146:14]
input io_pmp_0_cfg_r, // @[PMP.scala:146:14]
input [29:0] io_pmp_0_addr, // @[PMP.scala:146:14]
input [31:0] io_pmp_0_mask, // @[PMP.scala:146:14]
input io_pmp_1_cfg_l, // @[PMP.scala:146:14]
input [1:0] io_pmp_1_cfg_a, // @[PMP.scala:146:14]
input io_pmp_1_cfg_x, // @[PMP.scala:146:14]
input io_pmp_1_cfg_w, // @[PMP.scala:146:14]
input io_pmp_1_cfg_r, // @[PMP.scala:146:14]
input [29:0] io_pmp_1_addr, // @[PMP.scala:146:14]
input [31:0] io_pmp_1_mask, // @[PMP.scala:146:14]
input io_pmp_2_cfg_l, // @[PMP.scala:146:14]
input [1:0] io_pmp_2_cfg_a, // @[PMP.scala:146:14]
input io_pmp_2_cfg_x, // @[PMP.scala:146:14]
input io_pmp_2_cfg_w, // @[PMP.scala:146:14]
input io_pmp_2_cfg_r, // @[PMP.scala:146:14]
input [29:0] io_pmp_2_addr, // @[PMP.scala:146:14]
input [31:0] io_pmp_2_mask, // @[PMP.scala:146:14]
input io_pmp_3_cfg_l, // @[PMP.scala:146:14]
input [1:0] io_pmp_3_cfg_a, // @[PMP.scala:146:14]
input io_pmp_3_cfg_x, // @[PMP.scala:146:14]
input io_pmp_3_cfg_w, // @[PMP.scala:146:14]
input io_pmp_3_cfg_r, // @[PMP.scala:146:14]
input [29:0] io_pmp_3_addr, // @[PMP.scala:146:14]
input [31:0] io_pmp_3_mask, // @[PMP.scala:146:14]
input io_pmp_4_cfg_l, // @[PMP.scala:146:14]
input [1:0] io_pmp_4_cfg_a, // @[PMP.scala:146:14]
input io_pmp_4_cfg_x, // @[PMP.scala:146:14]
input io_pmp_4_cfg_w, // @[PMP.scala:146:14]
input io_pmp_4_cfg_r, // @[PMP.scala:146:14]
input [29:0] io_pmp_4_addr, // @[PMP.scala:146:14]
input [31:0] io_pmp_4_mask, // @[PMP.scala:146:14]
input io_pmp_5_cfg_l, // @[PMP.scala:146:14]
input [1:0] io_pmp_5_cfg_a, // @[PMP.scala:146:14]
input io_pmp_5_cfg_x, // @[PMP.scala:146:14]
input io_pmp_5_cfg_w, // @[PMP.scala:146:14]
input io_pmp_5_cfg_r, // @[PMP.scala:146:14]
input [29:0] io_pmp_5_addr, // @[PMP.scala:146:14]
input [31:0] io_pmp_5_mask, // @[PMP.scala:146:14]
input io_pmp_6_cfg_l, // @[PMP.scala:146:14]
input [1:0] io_pmp_6_cfg_a, // @[PMP.scala:146:14]
input io_pmp_6_cfg_x, // @[PMP.scala:146:14]
input io_pmp_6_cfg_w, // @[PMP.scala:146:14]
input io_pmp_6_cfg_r, // @[PMP.scala:146:14]
input [29:0] io_pmp_6_addr, // @[PMP.scala:146:14]
input [31:0] io_pmp_6_mask, // @[PMP.scala:146:14]
input io_pmp_7_cfg_l, // @[PMP.scala:146:14]
input [1:0] io_pmp_7_cfg_a, // @[PMP.scala:146:14]
input io_pmp_7_cfg_x, // @[PMP.scala:146:14]
input io_pmp_7_cfg_w, // @[PMP.scala:146:14]
input io_pmp_7_cfg_r, // @[PMP.scala:146:14]
input [29:0] io_pmp_7_addr, // @[PMP.scala:146:14]
input [31:0] io_pmp_7_mask, // @[PMP.scala:146:14]
input [31:0] io_addr, // @[PMP.scala:146:14]
output io_r, // @[PMP.scala:146:14]
output io_w, // @[PMP.scala:146:14]
output io_x // @[PMP.scala:146:14]
);
wire res_hit = io_pmp_7_cfg_a[1] ? ((io_addr ^ {io_pmp_7_addr, 2'h0}) & ~io_pmp_7_mask) == 32'h0 : io_pmp_7_cfg_a[0] & io_addr >= {io_pmp_6_addr, 2'h0} & io_addr < {io_pmp_7_addr, 2'h0}; // @[PMP.scala:45:20, :46:26, :60:48, :63:{47,52,54,58}, :77:9, :88:5, :94:48, :132:{8,61}]
wire res_ignore = io_prv[1] & ~io_pmp_7_cfg_l; // @[PMP.scala:156:56, :164:{26,29}]
wire res_hit_1 = io_pmp_6_cfg_a[1] ? ((io_addr ^ {io_pmp_6_addr, 2'h0}) & ~io_pmp_6_mask) == 32'h0 : io_pmp_6_cfg_a[0] & io_addr >= {io_pmp_5_addr, 2'h0} & io_addr < {io_pmp_6_addr, 2'h0}; // @[PMP.scala:45:20, :46:26, :60:48, :63:{47,52,54,58}, :77:9, :88:5, :94:48, :132:{8,61}]
wire res_ignore_1 = io_prv[1] & ~io_pmp_6_cfg_l; // @[PMP.scala:156:56, :164:{26,29}]
wire res_hit_2 = io_pmp_5_cfg_a[1] ? ((io_addr ^ {io_pmp_5_addr, 2'h0}) & ~io_pmp_5_mask) == 32'h0 : io_pmp_5_cfg_a[0] & io_addr >= {io_pmp_4_addr, 2'h0} & io_addr < {io_pmp_5_addr, 2'h0}; // @[PMP.scala:45:20, :46:26, :60:48, :63:{47,52,54,58}, :77:9, :88:5, :94:48, :132:{8,61}]
wire res_ignore_2 = io_prv[1] & ~io_pmp_5_cfg_l; // @[PMP.scala:156:56, :164:{26,29}]
wire res_hit_3 = io_pmp_4_cfg_a[1] ? ((io_addr ^ {io_pmp_4_addr, 2'h0}) & ~io_pmp_4_mask) == 32'h0 : io_pmp_4_cfg_a[0] & io_addr >= {io_pmp_3_addr, 2'h0} & io_addr < {io_pmp_4_addr, 2'h0}; // @[PMP.scala:45:20, :46:26, :60:48, :63:{47,52,54,58}, :77:9, :88:5, :94:48, :132:{8,61}]
wire res_ignore_3 = io_prv[1] & ~io_pmp_4_cfg_l; // @[PMP.scala:156:56, :164:{26,29}]
wire res_hit_4 = io_pmp_3_cfg_a[1] ? ((io_addr ^ {io_pmp_3_addr, 2'h0}) & ~io_pmp_3_mask) == 32'h0 : io_pmp_3_cfg_a[0] & io_addr >= {io_pmp_2_addr, 2'h0} & io_addr < {io_pmp_3_addr, 2'h0}; // @[PMP.scala:45:20, :46:26, :60:48, :63:{47,52,54,58}, :77:9, :88:5, :94:48, :132:{8,61}]
wire res_ignore_4 = io_prv[1] & ~io_pmp_3_cfg_l; // @[PMP.scala:156:56, :164:{26,29}]
wire res_hit_5 = io_pmp_2_cfg_a[1] ? ((io_addr ^ {io_pmp_2_addr, 2'h0}) & ~io_pmp_2_mask) == 32'h0 : io_pmp_2_cfg_a[0] & io_addr >= {io_pmp_1_addr, 2'h0} & io_addr < {io_pmp_2_addr, 2'h0}; // @[PMP.scala:45:20, :46:26, :60:48, :63:{47,52,54,58}, :77:9, :88:5, :94:48, :132:{8,61}]
wire res_ignore_5 = io_prv[1] & ~io_pmp_2_cfg_l; // @[PMP.scala:156:56, :164:{26,29}]
wire res_hit_6 = io_pmp_1_cfg_a[1] ? ((io_addr ^ {io_pmp_1_addr, 2'h0}) & ~io_pmp_1_mask) == 32'h0 : io_pmp_1_cfg_a[0] & io_addr >= {io_pmp_0_addr, 2'h0} & io_addr < {io_pmp_1_addr, 2'h0}; // @[PMP.scala:45:20, :46:26, :60:48, :63:{47,52,54,58}, :77:9, :88:5, :94:48, :132:{8,61}]
wire res_ignore_6 = io_prv[1] & ~io_pmp_1_cfg_l; // @[PMP.scala:156:56, :164:{26,29}]
wire res_hit_7 = io_pmp_0_cfg_a[1] ? ((io_addr ^ {io_pmp_0_addr, 2'h0}) & ~io_pmp_0_mask) == 32'h0 : io_pmp_0_cfg_a[0] & io_addr < {io_pmp_0_addr, 2'h0}; // @[PMP.scala:45:20, :46:26, :60:48, :63:{47,52,54,58}, :77:9, :132:{8,61}]
wire res_ignore_7 = io_prv[1] & ~io_pmp_0_cfg_l; // @[PMP.scala:156:56, :164:{26,29}]
assign io_r = res_hit_7 ? io_pmp_0_cfg_r | res_ignore_7 : res_hit_6 ? io_pmp_1_cfg_r | res_ignore_6 : res_hit_5 ? io_pmp_2_cfg_r | res_ignore_5 : res_hit_4 ? io_pmp_3_cfg_r | res_ignore_4 : res_hit_3 ? io_pmp_4_cfg_r | res_ignore_3 : res_hit_2 ? io_pmp_5_cfg_r | res_ignore_2 : res_hit_1 ? io_pmp_6_cfg_r | res_ignore_1 : res_hit ? io_pmp_7_cfg_r | res_ignore : io_prv[1]; // @[PMP.scala:132:8, :143:7, :156:56, :164:26, :182:40, :185:8]
assign io_w = res_hit_7 ? io_pmp_0_cfg_w | res_ignore_7 : res_hit_6 ? io_pmp_1_cfg_w | res_ignore_6 : res_hit_5 ? io_pmp_2_cfg_w | res_ignore_5 : res_hit_4 ? io_pmp_3_cfg_w | res_ignore_4 : res_hit_3 ? io_pmp_4_cfg_w | res_ignore_3 : res_hit_2 ? io_pmp_5_cfg_w | res_ignore_2 : res_hit_1 ? io_pmp_6_cfg_w | res_ignore_1 : res_hit ? io_pmp_7_cfg_w | res_ignore : io_prv[1]; // @[PMP.scala:132:8, :143:7, :156:56, :164:26, :183:40, :185:8]
assign io_x = res_hit_7 ? io_pmp_0_cfg_x | res_ignore_7 : res_hit_6 ? io_pmp_1_cfg_x | res_ignore_6 : res_hit_5 ? io_pmp_2_cfg_x | res_ignore_5 : res_hit_4 ? io_pmp_3_cfg_x | res_ignore_4 : res_hit_3 ? io_pmp_4_cfg_x | res_ignore_3 : res_hit_2 ? io_pmp_5_cfg_x | res_ignore_2 : res_hit_1 ? io_pmp_6_cfg_x | res_ignore_1 : res_hit ? io_pmp_7_cfg_x | res_ignore : io_prv[1]; // @[PMP.scala:132:8, :143:7, :156:56, :164:26, :184:40, :185:8]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File HistoryBufferSRAM.scala:
package compressacc
import chisel3._
import chisel3.util._
import chisel3.{Printable, SyncReadMem}
import freechips.rocketchip.tile._
import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.rocket.{TLBConfig}
import freechips.rocketchip.util.DecoupledHelper
import freechips.rocketchip.rocket.constants.MemoryOpConstants
// there is no offset here, because we always just add on at the current
// pointer
class HBSRAMWrite extends Bundle {
val data = UInt(256.W)
val valid_bytes = UInt(6.W)
}
class HBSRAMReadReq extends Bundle {
val offset = UInt(48.W)
}
class HBSRAMReadResp extends Bundle {
val data = UInt(256.W)
}
class HBSRAMAdvanceReadPtr extends Bundle {
val advance_bytes = UInt(6.W)
}
/*
* This block maintains the history of everything that has been
* loaded from a buffer to compress. It runs at least one cycle
* AHEAD of the state machine doing compression, so that handling
* cases where the offset is less than 32B is easy.
*
* The write interface is "valid" only, it does not have the ability
* to backpressure.
*/
class HistoryBufferSRAM()(implicit p: Parameters) extends Module with MemoryOpConstants {
val io = IO(new Bundle {
val writes_in = Flipped((Valid(new HBSRAMWrite)))
// these valids are technically not necessary, but useful for debugging/
// tracking purposes
val read_req_in = Flipped((Valid(new HBSRAMReadReq)))
val read_resp_out = (Valid(new HBSRAMReadResp))
val read_advance_ptr = Flipped((Valid(new HBSRAMAdvanceReadPtr)))
})
println(s"HIST BUF OVERPROV FACTOR: ${p(LZ77HistBufOverProvisionFactor)}")
val HIST_BUF_WIDTH = 32
val HIST_BUF_ELEMS_PER_CHUNK = 4 * 512 * p(LZ77HistBufOverProvisionFactor)
val HIST_SIZE_BYTES = HIST_BUF_WIDTH * HIST_BUF_ELEMS_PER_CHUNK
val HIST_BUF_INDEX_WIDTH = log2Up(HIST_SIZE_BYTES)
val BYTE_SIZE = 8
println(s"HIST BUF WIDTH: ${HIST_BUF_WIDTH}")
println(s"HIST BUF ELEMS PER CHUNK: ${HIST_BUF_ELEMS_PER_CHUNK}")
println(s"TOTAL HIST BUF SIZE (B): ${HIST_SIZE_BYTES}")
val recent_history_vec = Array.fill(HIST_BUF_WIDTH) {SyncReadMem(HIST_BUF_ELEMS_PER_CHUNK, UInt(BYTE_SIZE.W))}
val read_indexing_vec = Wire(Vec(HIST_BUF_WIDTH, UInt(HIST_BUF_INDEX_WIDTH.W)))
val read_ports_vec = Wire(Vec(HIST_BUF_WIDTH, UInt(BYTE_SIZE.W)))
for (i <- 0 until HIST_BUF_WIDTH) {
read_indexing_vec(i) := DontCare
}
// shift amount to remove memindex part of addr (low # of bits required to count HIST BUF WIDTH items)
val MEMINDEX_BITS = log2Up(HIST_BUF_WIDTH)
// mask to get only memindex part of addr
val MEMINDEX_MASK = (1 << MEMINDEX_BITS) - 1
// HANDLE READS:
val read_addr_ptr = RegInit(0.U(HIST_BUF_INDEX_WIDTH.W))
when (io.read_advance_ptr.valid) {
// TODO: should an ongoing read account for advance_bytes?
read_addr_ptr := read_addr_ptr + io.read_advance_ptr.bits.advance_bytes
}
val read_result_valid = RegNext(io.read_req_in.valid)
val read_result_addr_ptr = RegNext(read_addr_ptr)
val read_result_offset = RegNext(io.read_req_in.bits.offset)
io.read_resp_out.valid := read_result_valid
for (elemno <- 0 until HIST_BUF_WIDTH) {
read_ports_vec(elemno) := recent_history_vec(elemno)(read_indexing_vec(elemno))
}
for (elemno <- 0 until HIST_BUF_WIDTH) {
val read_memaddr = (read_addr_ptr + 32.U - io.read_req_in.bits.offset - elemno.U - 1.U) >> MEMINDEX_BITS
val read_memno = (read_addr_ptr + 32.U - io.read_req_in.bits.offset - elemno.U - 1.U) & MEMINDEX_MASK.U
read_indexing_vec(read_memno) := read_memaddr
when (io.read_req_in.valid) {
CompressAccelLogger.logInfo("issued hist_read(elemno:%d): from memno:%d,memaddr:%d\n", elemno.U, read_memno, read_memaddr)
}
}
val read_output_vec = Wire(Vec(HIST_BUF_WIDTH, UInt(BYTE_SIZE.W)))
for (elemno <- 0 until HIST_BUF_WIDTH) {
// get read data
val read_memaddr = (read_result_addr_ptr + 32.U - read_result_offset - elemno.U - 1.U) >> MEMINDEX_BITS
val read_memno = (read_result_addr_ptr + 32.U - read_result_offset - elemno.U - 1.U) & MEMINDEX_MASK.U
read_output_vec(elemno) := read_ports_vec(read_memno)
val print_read_ports_vec = Wire(UInt(BYTE_SIZE.W))
print_read_ports_vec := read_ports_vec(read_memno)
when (read_result_valid) {
CompressAccelLogger.logInfo("got hist_read(elemno:%d): from memno:%d,memaddr:%d = val:0x%x\n", elemno.U, read_memno, read_memaddr, print_read_ports_vec)
}
}
io.read_resp_out.bits.data := Cat(read_output_vec)
when (read_result_valid) {
CompressAccelLogger.logInfo("read_resp: 0x%x\n", io.read_resp_out.bits.data)
}
// HANDLE WRITES:
val write_addr_ptr = RegInit(0.U(HIST_BUF_INDEX_WIDTH.W))
when (io.writes_in.valid) {
write_addr_ptr := write_addr_ptr + io.writes_in.bits.valid_bytes
}
val write_indexing_vec = Wire(Vec(HIST_BUF_WIDTH, UInt(HIST_BUF_INDEX_WIDTH.W)))
val write_ports_vec = Wire(Vec(HIST_BUF_WIDTH, UInt(BYTE_SIZE.W)))
val write_ports_write_enable = Wire(Vec(HIST_BUF_WIDTH, Bool()))
for (elemno <- 0 until HIST_BUF_WIDTH) {
write_ports_write_enable(elemno) := false.B
write_indexing_vec(elemno) := DontCare
write_ports_vec(elemno) := DontCare
}
for (elemno <- 0 until HIST_BUF_WIDTH) {
when (write_ports_write_enable(elemno)) {
recent_history_vec(elemno)(write_indexing_vec(elemno)) := write_ports_vec(elemno)
}
}
val recent_history_vec_next = Wire(Vec(HIST_BUF_WIDTH, UInt(BYTE_SIZE.W)))
for (elemno <- 0 until HIST_BUF_WIDTH) {
recent_history_vec_next(elemno) := DontCare
}
for (elemno <- 0 until HIST_BUF_WIDTH) {
recent_history_vec_next(io.writes_in.bits.valid_bytes - elemno.U - 1.U) := io.writes_in.bits.data(((elemno+1) << 3) - 1, elemno << 3)
}
for (elemno <- 0 until HIST_BUF_WIDTH) {
when (io.writes_in.valid && (elemno.U(MEMINDEX_BITS.W) < io.writes_in.bits.valid_bytes)) {
val full_address = write_addr_ptr + io.writes_in.bits.valid_bytes - elemno.U - 1.U
val memno = full_address & (MEMINDEX_MASK).U
val memaddr = full_address >> MEMINDEX_BITS
write_indexing_vec(memno) := memaddr
write_ports_vec(memno) := recent_history_vec_next(elemno)
write_ports_write_enable(memno) := true.B
val print_recent_history_vec = Wire(UInt(BYTE_SIZE.W))
//recent_history_vec_next(elemno))
print_recent_history_vec := recent_history_vec_next(elemno)
CompressAccelLogger.logInfo("do_write:mem(memno:%d,memaddr:%d): from rhvn(elemno:%d) = val:0x%x\n", memno, memaddr, elemno.U, print_recent_history_vec)
}
}
}
| module MEM_14( // @[HistoryBufferSRAM.scala:66:67]
input [11:0] R0_addr,
input R0_clk,
output [7:0] R0_data,
input [11:0] W0_addr,
input W0_en,
input W0_clk,
input [7:0] W0_data
);
MEM_ext MEM_ext ( // @[HistoryBufferSRAM.scala:66:67]
.R0_addr (R0_addr),
.R0_en (1'h1), // @[HistoryBufferSRAM.scala:66:67]
.R0_clk (R0_clk),
.R0_data (R0_data),
.W0_addr (W0_addr),
.W0_en (W0_en),
.W0_clk (W0_clk),
.W0_data (W0_data)
); // @[HistoryBufferSRAM.scala:66:67]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftRegisterPriorityQueue.scala:
package compressacc
import chisel3._
import chisel3.util._
import chisel3.util._
// TODO : support enq & deq at the same cycle
class PriorityQueueStageIO(keyWidth: Int, value: ValueInfo) extends Bundle {
val output_prev = KeyValue(keyWidth, value)
val output_nxt = KeyValue(keyWidth, value)
val input_prev = Flipped(KeyValue(keyWidth, value))
val input_nxt = Flipped(KeyValue(keyWidth, value))
val cmd = Flipped(Valid(UInt(1.W)))
val insert_here = Input(Bool())
val cur_input_keyval = Flipped(KeyValue(keyWidth, value))
val cur_output_keyval = KeyValue(keyWidth, value)
}
class PriorityQueueStage(keyWidth: Int, value: ValueInfo) extends Module {
val io = IO(new PriorityQueueStageIO(keyWidth, value))
dontTouch(io)
val CMD_DEQ = 0.U
val CMD_ENQ = 1.U
val MAX_VALUE = (1 << keyWidth) - 1
val key_reg = RegInit(MAX_VALUE.U(keyWidth.W))
val value_reg = Reg(value)
io.output_prev.key := key_reg
io.output_prev.value := value_reg
io.output_nxt.key := key_reg
io.output_nxt.value := value_reg
io.cur_output_keyval.key := key_reg
io.cur_output_keyval.value := value_reg
when (io.cmd.valid) {
switch (io.cmd.bits) {
is (CMD_DEQ) {
key_reg := io.input_nxt.key
value_reg := io.input_nxt.value
}
is (CMD_ENQ) {
when (io.insert_here) {
key_reg := io.cur_input_keyval.key
value_reg := io.cur_input_keyval.value
} .elsewhen (key_reg >= io.cur_input_keyval.key) {
key_reg := io.input_prev.key
value_reg := io.input_prev.value
} .otherwise {
// do nothing
}
}
}
}
}
object PriorityQueueStage {
def apply(keyWidth: Int, v: ValueInfo): PriorityQueueStage = new PriorityQueueStage(keyWidth, v)
}
// TODO
// - This design is not scalable as the enqued_keyval is broadcasted to all the stages
// - Add pipeline registers later
class PriorityQueueIO(queSize: Int, keyWidth: Int, value: ValueInfo) extends Bundle {
val cnt_bits = log2Ceil(queSize+1)
val counter = Output(UInt(cnt_bits.W))
val enq = Flipped(Decoupled(KeyValue(keyWidth, value)))
val deq = Decoupled(KeyValue(keyWidth, value))
}
class PriorityQueue(queSize: Int, keyWidth: Int, value: ValueInfo) extends Module {
val keyWidthInternal = keyWidth + 1
val CMD_DEQ = 0.U
val CMD_ENQ = 1.U
val io = IO(new PriorityQueueIO(queSize, keyWidthInternal, value))
dontTouch(io)
val MAX_VALUE = ((1 << keyWidthInternal) - 1).U
val cnt_bits = log2Ceil(queSize+1)
// do not consider cases where we are inserting more entries then the queSize
val counter = RegInit(0.U(cnt_bits.W))
io.counter := counter
val full = (counter === queSize.U)
val empty = (counter === 0.U)
io.deq.valid := !empty
io.enq.ready := !full
when (io.enq.fire) {
counter := counter + 1.U
}
when (io.deq.fire) {
counter := counter - 1.U
}
val cmd_valid = io.enq.valid || io.deq.ready
val cmd = Mux(io.enq.valid, CMD_ENQ, CMD_DEQ)
assert(!(io.enq.valid && io.deq.ready))
val stages = Seq.fill(queSize)(Module(new PriorityQueueStage(keyWidthInternal, value)))
for (i <- 0 until (queSize - 1)) {
stages(i+1).io.input_prev <> stages(i).io.output_nxt
stages(i).io.input_nxt <> stages(i+1).io.output_prev
}
stages(queSize-1).io.input_nxt.key := MAX_VALUE
// stages(queSize-1).io.input_nxt.value :=
stages(queSize-1).io.input_nxt.value.symbol := 0.U
// stages(queSize-1).io.input_nxt.value.child(0) := 0.U
// stages(queSize-1).io.input_nxt.value.child(1) := 0.U
stages(0).io.input_prev.key := io.enq.bits.key
stages(0).io.input_prev.value <> io.enq.bits.value
for (i <- 0 until queSize) {
stages(i).io.cmd.valid := cmd_valid
stages(i).io.cmd.bits := cmd
stages(i).io.cur_input_keyval <> io.enq.bits
}
val is_large_or_equal = WireInit(VecInit(Seq.fill(queSize)(false.B)))
for (i <- 0 until queSize) {
is_large_or_equal(i) := (stages(i).io.cur_output_keyval.key >= io.enq.bits.key)
}
val is_large_or_equal_cat = Wire(UInt(queSize.W))
is_large_or_equal_cat := Cat(is_large_or_equal.reverse)
val insert_here_idx = PriorityEncoder(is_large_or_equal_cat)
for (i <- 0 until queSize) {
when (i.U === insert_here_idx) {
stages(i).io.insert_here := true.B
} .otherwise {
stages(i).io.insert_here := false.B
}
}
io.deq.bits <> stages(0).io.output_prev
}
| module PriorityQueueStage_244( // @[ShiftRegisterPriorityQueue.scala:21:7]
input clock, // @[ShiftRegisterPriorityQueue.scala:21:7]
input reset, // @[ShiftRegisterPriorityQueue.scala:21:7]
output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14]
);
wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24]
assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22]
assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30]
always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24]
else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30]
key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
end
else // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
end
if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7]
value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30]
value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
end
else // @[ShiftRegisterPriorityQueue.scala:21:7]
value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
end
always @(posedge)
assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File core.scala:
//******************************************************************************
// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// RISC-V Processor Core
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//
// BOOM has the following (conceptual) stages:
// if0 - Instruction Fetch 0 (next-pc select)
// if1 - Instruction Fetch 1 (I$ access)
// if2 - Instruction Fetch 2 (instruction return)
// if3 - Instruction Fetch 3 (enqueue to fetch buffer)
// if4 - Instruction Fetch 4 (redirect from bpd)
// dec - Decode
// ren - Rename1
// dis - Rename2/Dispatch
// iss - Issue
// rrd - Register Read
// exe - Execute
// mem - Memory
// sxt - Sign-extend
// wb - Writeback
// com - Commit
package boom.v3.exu
import java.nio.file.{Paths}
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.rocket.Instructions._
import freechips.rocketchip.tile.{TraceBundle}
import freechips.rocketchip.rocket.{Causes, PRV, TracedInstruction}
import freechips.rocketchip.util.{Str, UIntIsOneOf, CoreMonitorBundle}
import freechips.rocketchip.devices.tilelink.{PLICConsts, CLINTConsts}
import boom.v3.common._
import boom.v3.ifu.{GlobalHistory, HasBoomFrontendParameters}
import boom.v3.exu.FUConstants._
import boom.v3.util._
/**
* Top level core object that connects the Frontend to the rest of the pipeline.
*/
class BoomCore()(implicit p: Parameters) extends BoomModule
with HasBoomFrontendParameters // TODO: Don't add this trait
{
val io = IO(new Bundle {
val hartid = Input(UInt(hartIdLen.W))
val interrupts = Input(new freechips.rocketchip.rocket.CoreInterrupts(false))
val ifu = new boom.v3.ifu.BoomFrontendIO
val ptw = Flipped(new freechips.rocketchip.rocket.DatapathPTWIO())
val rocc = Flipped(new freechips.rocketchip.tile.RoCCCoreIO())
val lsu = Flipped(new boom.v3.lsu.LSUCoreIO)
val ptw_tlb = new freechips.rocketchip.rocket.TLBPTWIO()
val trace = Output(new TraceBundle)
val fcsr_rm = UInt(freechips.rocketchip.tile.FPConstants.RM_SZ.W)
})
io.ptw_tlb := DontCare
io.ptw := DontCare
io.ifu := DontCare
//**********************************
// construct all of the modules
// Only holds integer-registerfile execution units.
val exe_units = new boom.v3.exu.ExecutionUnits(fpu=false)
val jmp_unit_idx = exe_units.jmp_unit_idx
val jmp_unit = exe_units(jmp_unit_idx)
// Meanwhile, the FP pipeline holds the FP issue window, FP regfile, and FP arithmetic units.
var fp_pipeline: FpPipeline = null
if (usingFPU) fp_pipeline = Module(new FpPipeline)
// ********************************************************
// Clear fp_pipeline before use
if (usingFPU) {
fp_pipeline.io.ll_wports := DontCare
fp_pipeline.io.wb_valids := DontCare
fp_pipeline.io.wb_pdsts := DontCare
}
val numIrfWritePorts = exe_units.numIrfWritePorts + memWidth
val numLlIrfWritePorts = exe_units.numLlIrfWritePorts
val numIrfReadPorts = exe_units.numIrfReadPorts
val numFastWakeupPorts = exe_units.count(_.bypassable)
val numAlwaysBypassable = exe_units.count(_.alwaysBypassable)
val numIntIssueWakeupPorts = numIrfWritePorts + numFastWakeupPorts - numAlwaysBypassable // + memWidth for ll_wb
val numIntRenameWakeupPorts = numIntIssueWakeupPorts
val numFpWakeupPorts = if (usingFPU) fp_pipeline.io.wakeups.length else 0
val decode_units = for (w <- 0 until decodeWidth) yield { val d = Module(new DecodeUnit); d }
val dec_brmask_logic = Module(new BranchMaskGenerationLogic(coreWidth))
val rename_stage = Module(new RenameStage(coreWidth, numIntPhysRegs, numIntRenameWakeupPorts, false))
val fp_rename_stage = if (usingFPU) Module(new RenameStage(coreWidth, numFpPhysRegs, numFpWakeupPorts, true)) else null
val pred_rename_stage = Module(new PredRenameStage(coreWidth, ftqSz, 1))
val rename_stages = if (usingFPU) Seq(rename_stage, fp_rename_stage, pred_rename_stage) else Seq(rename_stage, pred_rename_stage)
val mem_iss_unit = Module(new IssueUnitCollapsing(memIssueParam, numIntIssueWakeupPorts))
mem_iss_unit.suggestName("mem_issue_unit")
val int_iss_unit = Module(new IssueUnitCollapsing(intIssueParam, numIntIssueWakeupPorts))
int_iss_unit.suggestName("int_issue_unit")
val issue_units = Seq(mem_iss_unit, int_iss_unit)
val dispatcher = Module(new BasicDispatcher)
val iregfile = Module(new RegisterFileSynthesizable(
numIntPhysRegs,
numIrfReadPorts,
numIrfWritePorts,
xLen,
Seq.fill(memWidth) {true} ++ exe_units.bypassable_write_port_mask)) // bypassable ll_wb
val pregfile = Module(new RegisterFileSynthesizable(
ftqSz,
exe_units.numIrfReaders,
1,
1,
Seq(true))) // The jmp unit is always bypassable
pregfile.io := DontCare // Only use the IO if enableSFBOpt
// wb arbiter for the 0th ll writeback
// TODO: should this be a multi-arb?
val ll_wbarb = Module(new Arbiter(new ExeUnitResp(xLen), 1 +
(if (usingFPU) 1 else 0) +
(if (usingRoCC) 1 else 0)))
val iregister_read = Module(new RegisterRead(
issue_units.map(_.issueWidth).sum,
exe_units.withFilter(_.readsIrf).map(_.supportedFuncUnits).toSeq,
numIrfReadPorts,
exe_units.withFilter(_.readsIrf).map(x => 2).toSeq,
exe_units.numTotalBypassPorts,
jmp_unit.numBypassStages,
xLen))
val rob = Module(new Rob(
numIrfWritePorts + numFpWakeupPorts, // +memWidth for ll writebacks
numFpWakeupPorts))
// Used to wakeup registers in rename and issue. ROB needs to listen to something else.
val int_iss_wakeups = Wire(Vec(numIntIssueWakeupPorts, Valid(new ExeUnitResp(xLen))))
val int_ren_wakeups = Wire(Vec(numIntRenameWakeupPorts, Valid(new ExeUnitResp(xLen))))
val pred_wakeup = Wire(Valid(new ExeUnitResp(1)))
require (exe_units.length == issue_units.map(_.issueWidth).sum)
//***********************************
// Pipeline State Registers and Wires
// Decode/Rename1 Stage
val dec_valids = Wire(Vec(coreWidth, Bool())) // are the decoded instruction valid? It may be held up though.
val dec_uops = Wire(Vec(coreWidth, new MicroOp()))
val dec_fire = Wire(Vec(coreWidth, Bool())) // can the instruction fire beyond decode?
// (can still be stopped in ren or dis)
val dec_ready = Wire(Bool())
val dec_xcpts = Wire(Vec(coreWidth, Bool()))
val ren_stalls = Wire(Vec(coreWidth, Bool()))
// Rename2/Dispatch stage
val dis_valids = Wire(Vec(coreWidth, Bool()))
val dis_uops = Wire(Vec(coreWidth, new MicroOp))
val dis_fire = Wire(Vec(coreWidth, Bool()))
val dis_ready = Wire(Bool())
// Issue Stage/Register Read
val iss_valids = Wire(Vec(exe_units.numIrfReaders, Bool()))
val iss_uops = Wire(Vec(exe_units.numIrfReaders, new MicroOp()))
val bypasses = Wire(Vec(exe_units.numTotalBypassPorts, Valid(new ExeUnitResp(xLen))))
val pred_bypasses = Wire(Vec(jmp_unit.numBypassStages, Valid(new ExeUnitResp(1))))
require(jmp_unit.bypassable)
// --------------------------------------
// Dealing with branch resolutions
// The individual branch resolutions from each ALU
val brinfos = Reg(Vec(coreWidth, new BrResolutionInfo()))
// "Merged" branch update info from all ALUs
// brmask contains masks for rapidly clearing mispredicted instructions
// brindices contains indices to reset pointers for allocated structures
// brindices is delayed a cycle
val brupdate = Wire(new BrUpdateInfo)
val b1 = Wire(new BrUpdateMasks)
val b2 = Reg(new BrResolutionInfo)
brupdate.b1 := b1
brupdate.b2 := b2
for ((b, a) <- brinfos zip exe_units.alu_units) {
b := a.io.brinfo
b.valid := a.io.brinfo.valid && !rob.io.flush.valid
}
b1.resolve_mask := brinfos.map(x => x.valid << x.uop.br_tag).reduce(_|_)
b1.mispredict_mask := brinfos.map(x => (x.valid && x.mispredict) << x.uop.br_tag).reduce(_|_)
// Find the oldest mispredict and use it to update indices
var mispredict_val = false.B
var oldest_mispredict = brinfos(0)
for (b <- brinfos) {
val use_this_mispredict = !mispredict_val ||
b.valid && b.mispredict && IsOlder(b.uop.rob_idx, oldest_mispredict.uop.rob_idx, rob.io.rob_head_idx)
mispredict_val = mispredict_val || (b.valid && b.mispredict)
oldest_mispredict = Mux(use_this_mispredict, b, oldest_mispredict)
}
b2.mispredict := mispredict_val
b2.cfi_type := oldest_mispredict.cfi_type
b2.taken := oldest_mispredict.taken
b2.pc_sel := oldest_mispredict.pc_sel
b2.uop := UpdateBrMask(brupdate, oldest_mispredict.uop)
b2.jalr_target := RegNext(jmp_unit.io.brinfo.jalr_target)
b2.target_offset := oldest_mispredict.target_offset
val oldest_mispredict_ftq_idx = oldest_mispredict.uop.ftq_idx
assert (!((brupdate.b1.mispredict_mask =/= 0.U || brupdate.b2.mispredict)
&& rob.io.commit.rollback), "Can't have a mispredict during rollback.")
io.ifu.brupdate := brupdate
for (eu <- exe_units) {
eu.io.brupdate := brupdate
}
if (usingFPU) {
fp_pipeline.io.brupdate := brupdate
}
// Load/Store Unit & ExeUnits
val mem_units = exe_units.memory_units
val mem_resps = mem_units.map(_.io.ll_iresp)
for (i <- 0 until memWidth) {
mem_units(i).io.lsu_io <> io.lsu.exe(i)
}
//-------------------------------------------------------------
// Uarch Hardware Performance Events (HPEs)
val perfEvents = new freechips.rocketchip.rocket.EventSets(Seq(
new freechips.rocketchip.rocket.EventSet((mask, hits) => (mask & hits).orR, Seq(
("exception", () => rob.io.com_xcpt.valid),
("nop", () => false.B),
("nop", () => false.B),
("nop", () => false.B))),
new freechips.rocketchip.rocket.EventSet((mask, hits) => (mask & hits).orR, Seq(
// ("I$ blocked", () => icache_blocked),
("nop", () => false.B),
("branch misprediction", () => b2.mispredict),
("control-flow target misprediction", () => b2.mispredict &&
b2.cfi_type === CFI_JALR),
("flush", () => rob.io.flush.valid),
("branch resolved", () => b2.valid)
)),
new freechips.rocketchip.rocket.EventSet((mask, hits) => (mask & hits).orR, Seq(
("I$ miss", () => io.ifu.perf.acquire),
("D$ miss", () => io.lsu.perf.acquire),
("D$ release", () => io.lsu.perf.release),
("ITLB miss", () => io.ifu.perf.tlbMiss),
("DTLB miss", () => io.lsu.perf.tlbMiss),
("L2 TLB miss", () => io.ptw.perf.l2miss)))))
val csr = Module(new freechips.rocketchip.rocket.CSRFile(perfEvents, boomParams.customCSRs.decls))
csr.io.inst foreach { c => c := DontCare }
csr.io.rocc_interrupt := io.rocc.interrupt
csr.io.mhtinst_read_pseudo := false.B
val custom_csrs = Wire(new BoomCustomCSRs)
custom_csrs.csrs.foreach { c => c.stall := false.B; c.set := false.B; c.sdata := DontCare }
(custom_csrs.csrs zip csr.io.customCSRs).map { case (lhs, rhs) => lhs <> rhs }
//val icache_blocked = !(io.ifu.fetchpacket.valid || RegNext(io.ifu.fetchpacket.valid))
val icache_blocked = false.B
csr.io.counters foreach { c => c.inc := RegNext(perfEvents.evaluate(c.eventSel)) }
//****************************************
// Time Stamp Counter & Retired Instruction Counter
// (only used for printf and vcd dumps - the actual counters are in the CSRFile)
val debug_tsc_reg = RegInit(0.U(xLen.W))
val debug_irt_reg = RegInit(0.U(xLen.W))
val debug_brs = Reg(Vec(4, UInt(xLen.W)))
val debug_jals = Reg(Vec(4, UInt(xLen.W)))
val debug_jalrs = Reg(Vec(4, UInt(xLen.W)))
for (j <- 0 until 4) {
debug_brs(j) := debug_brs(j) + PopCount(VecInit((0 until coreWidth) map {i =>
rob.io.commit.arch_valids(i) &&
(rob.io.commit.uops(i).debug_fsrc === j.U) &&
rob.io.commit.uops(i).is_br
}))
debug_jals(j) := debug_jals(j) + PopCount(VecInit((0 until coreWidth) map {i =>
rob.io.commit.arch_valids(i) &&
(rob.io.commit.uops(i).debug_fsrc === j.U) &&
rob.io.commit.uops(i).is_jal
}))
debug_jalrs(j) := debug_jalrs(j) + PopCount(VecInit((0 until coreWidth) map {i =>
rob.io.commit.arch_valids(i) &&
(rob.io.commit.uops(i).debug_fsrc === j.U) &&
rob.io.commit.uops(i).is_jalr
}))
}
dontTouch(debug_brs)
dontTouch(debug_jals)
dontTouch(debug_jalrs)
debug_tsc_reg := debug_tsc_reg + 1.U
debug_irt_reg := debug_irt_reg + PopCount(rob.io.commit.arch_valids.asUInt)
dontTouch(debug_tsc_reg)
dontTouch(debug_irt_reg)
//****************************************
// Print-out information about the machine
val issStr =
if (enableAgePriorityIssue) " (Age-based Priority)"
else " (Unordered Priority)"
// val btbStr =
// if (enableBTB) ("" + boomParams.btb.nSets * boomParams.btb.nWays + " entries (" + boomParams.btb.nSets + " x " + boomParams.btb.nWays + " ways)")
// else 0
val btbStr = ""
val fpPipelineStr =
if (usingFPU) fp_pipeline.toString
else ""
override def toString: String =
(BoomCoreStringPrefix("====Overall Core Params====") + "\n"
+ exe_units.toString + "\n"
+ fpPipelineStr + "\n"
+ rob.toString + "\n"
+ BoomCoreStringPrefix(
"===Other Core Params===",
"Fetch Width : " + fetchWidth,
"Decode Width : " + coreWidth,
"Issue Width : " + issueParams.map(_.issueWidth).sum,
"ROB Size : " + numRobEntries,
"Issue Window Size : " + issueParams.map(_.numEntries) + issStr,
"Load/Store Unit Size : " + numLdqEntries + "/" + numStqEntries,
"Num Int Phys Registers: " + numIntPhysRegs,
"Num FP Phys Registers: " + numFpPhysRegs,
"Max Branch Count : " + maxBrCount)
+ iregfile.toString + "\n"
+ BoomCoreStringPrefix(
"Num Slow Wakeup Ports : " + numIrfWritePorts,
"Num Fast Wakeup Ports : " + exe_units.count(_.bypassable),
"Num Bypass Ports : " + exe_units.numTotalBypassPorts) + "\n"
+ BoomCoreStringPrefix(
"DCache Ways : " + dcacheParams.nWays,
"DCache Sets : " + dcacheParams.nSets,
"DCache nMSHRs : " + dcacheParams.nMSHRs,
"ICache Ways : " + icacheParams.nWays,
"ICache Sets : " + icacheParams.nSets,
"D-TLB Ways : " + dcacheParams.nTLBWays,
"I-TLB Ways : " + icacheParams.nTLBWays,
"Paddr Bits : " + paddrBits,
"Vaddr Bits : " + vaddrBits) + "\n"
+ BoomCoreStringPrefix(
"Using FPU Unit? : " + usingFPU.toString,
"Using FDivSqrt? : " + usingFDivSqrt.toString,
"Using VM? : " + usingVM.toString) + "\n")
//-------------------------------------------------------------
//-------------------------------------------------------------
// **** Fetch Stage/Frontend ****
//-------------------------------------------------------------
//-------------------------------------------------------------
io.ifu.redirect_val := false.B
io.ifu.redirect_flush := false.B
// Breakpoint info
io.ifu.status := csr.io.status
io.ifu.bp := csr.io.bp
io.ifu.mcontext := csr.io.mcontext
io.ifu.scontext := csr.io.scontext
io.ifu.flush_icache := (0 until coreWidth).map { i =>
(rob.io.commit.arch_valids(i) && rob.io.commit.uops(i).is_fencei) ||
(RegNext(dec_valids(i) && dec_uops(i).is_jalr && csr.io.status.debug))
}.reduce(_||_)
// TODO FIX THIS HACK
// The below code works because of two quirks with the flush mechanism
// 1 ) All flush_on_commit instructions are also is_unique,
// In the future, this constraint will be relaxed.
// 2 ) We send out flush signals one cycle after the commit signal. We need to
// mux between one/two cycle delay for the following cases:
// ERETs are reported to the CSR two cycles before we send the flush
// Exceptions are reported to the CSR on the cycle we send the flush
// This discrepency should be resolved elsewhere.
when (RegNext(rob.io.flush.valid)) {
io.ifu.redirect_val := true.B
io.ifu.redirect_flush := true.B
val flush_typ = RegNext(rob.io.flush.bits.flush_typ)
// Clear the global history when we flush the ROB (exceptions, AMOs, unique instructions, etc.)
val new_ghist = WireInit((0.U).asTypeOf(new GlobalHistory))
new_ghist.current_saw_branch_not_taken := true.B
new_ghist.ras_idx := io.ifu.get_pc(0).entry.ras_idx
io.ifu.redirect_ghist := new_ghist
when (FlushTypes.useCsrEvec(flush_typ)) {
io.ifu.redirect_pc := Mux(flush_typ === FlushTypes.eret,
RegNext(RegNext(csr.io.evec)),
csr.io.evec)
} .otherwise {
val flush_pc = (AlignPCToBoundary(io.ifu.get_pc(0).pc, icBlockBytes)
+ RegNext(rob.io.flush.bits.pc_lob)
- Mux(RegNext(rob.io.flush.bits.edge_inst), 2.U, 0.U))
val flush_pc_next = flush_pc + Mux(RegNext(rob.io.flush.bits.is_rvc), 2.U, 4.U)
io.ifu.redirect_pc := Mux(FlushTypes.useSamePC(flush_typ),
flush_pc, flush_pc_next)
}
io.ifu.redirect_ftq_idx := RegNext(rob.io.flush.bits.ftq_idx)
} .elsewhen (brupdate.b2.mispredict && !RegNext(rob.io.flush.valid)) {
val block_pc = AlignPCToBoundary(io.ifu.get_pc(1).pc, icBlockBytes)
val uop_maybe_pc = block_pc | brupdate.b2.uop.pc_lob
val npc = uop_maybe_pc + Mux(brupdate.b2.uop.is_rvc || brupdate.b2.uop.edge_inst, 2.U, 4.U)
val jal_br_target = Wire(UInt(vaddrBitsExtended.W))
jal_br_target := (uop_maybe_pc.asSInt + brupdate.b2.target_offset +
(Fill(vaddrBitsExtended-1, brupdate.b2.uop.edge_inst) << 1).asSInt).asUInt
val bj_addr = Mux(brupdate.b2.cfi_type === CFI_JALR, brupdate.b2.jalr_target, jal_br_target)
val mispredict_target = Mux(brupdate.b2.pc_sel === PC_PLUS4, npc, bj_addr)
io.ifu.redirect_val := true.B
io.ifu.redirect_pc := mispredict_target
io.ifu.redirect_flush := true.B
io.ifu.redirect_ftq_idx := brupdate.b2.uop.ftq_idx
val use_same_ghist = (brupdate.b2.cfi_type === CFI_BR &&
!brupdate.b2.taken &&
bankAlign(block_pc) === bankAlign(npc))
val ftq_entry = io.ifu.get_pc(1).entry
val cfi_idx = (brupdate.b2.uop.pc_lob ^
Mux(ftq_entry.start_bank === 1.U, 1.U << log2Ceil(bankBytes), 0.U))(log2Ceil(fetchWidth), 1)
val ftq_ghist = io.ifu.get_pc(1).ghist
val next_ghist = ftq_ghist.update(
ftq_entry.br_mask.asUInt,
brupdate.b2.taken,
brupdate.b2.cfi_type === CFI_BR,
cfi_idx,
true.B,
io.ifu.get_pc(1).pc,
ftq_entry.cfi_is_call && ftq_entry.cfi_idx.bits === cfi_idx,
ftq_entry.cfi_is_ret && ftq_entry.cfi_idx.bits === cfi_idx)
io.ifu.redirect_ghist := Mux(
use_same_ghist,
ftq_ghist,
next_ghist)
io.ifu.redirect_ghist.current_saw_branch_not_taken := use_same_ghist
} .elsewhen (rob.io.flush_frontend || brupdate.b1.mispredict_mask =/= 0.U) {
io.ifu.redirect_flush := true.B
}
// Tell the FTQ it can deallocate entries by passing youngest ftq_idx.
val youngest_com_idx = (coreWidth-1).U - PriorityEncoder(rob.io.commit.valids.reverse)
io.ifu.commit.valid := rob.io.commit.valids.reduce(_|_) || rob.io.com_xcpt.valid
io.ifu.commit.bits := Mux(rob.io.com_xcpt.valid,
rob.io.com_xcpt.bits.ftq_idx,
rob.io.commit.uops(youngest_com_idx).ftq_idx)
assert(!(rob.io.commit.valids.reduce(_|_) && rob.io.com_xcpt.valid),
"ROB can't commit and except in same cycle!")
for (i <- 0 until memWidth) {
when (RegNext(io.lsu.exe(i).req.bits.sfence.valid)) {
io.ifu.sfence := RegNext(io.lsu.exe(i).req.bits.sfence)
}
}
//-------------------------------------------------------------
//-------------------------------------------------------------
// **** Branch Prediction ****
//-------------------------------------------------------------
//-------------------------------------------------------------
//-------------------------------------------------------------
//-------------------------------------------------------------
// **** Decode Stage ****
//-------------------------------------------------------------
//-------------------------------------------------------------
// track mask of finished instructions in the bundle
// use this to mask out insts coming from FetchBuffer that have been finished
// for example, back pressure may cause us to only issue some instructions from FetchBuffer
// but on the next cycle, we only want to retry a subset
val dec_finished_mask = RegInit(0.U(coreWidth.W))
//-------------------------------------------------------------
// Pull out instructions and send to the Decoders
io.ifu.fetchpacket.ready := dec_ready
val dec_fbundle = io.ifu.fetchpacket.bits
//-------------------------------------------------------------
// Decoders
for (w <- 0 until coreWidth) {
dec_valids(w) := io.ifu.fetchpacket.valid && dec_fbundle.uops(w).valid &&
!dec_finished_mask(w)
decode_units(w).io.enq.uop := dec_fbundle.uops(w).bits
decode_units(w).io.status := csr.io.status
decode_units(w).io.csr_decode <> csr.io.decode(w)
decode_units(w).io.interrupt := csr.io.interrupt
decode_units(w).io.interrupt_cause := csr.io.interrupt_cause
dec_uops(w) := decode_units(w).io.deq.uop
}
//-------------------------------------------------------------
// FTQ GetPC Port Arbitration
val jmp_pc_req = Wire(Decoupled(UInt(log2Ceil(ftqSz).W)))
val xcpt_pc_req = Wire(Decoupled(UInt(log2Ceil(ftqSz).W)))
val flush_pc_req = Wire(Decoupled(UInt(log2Ceil(ftqSz).W)))
val ftq_arb = Module(new Arbiter(UInt(log2Ceil(ftqSz).W), 3))
// Order by the oldest. Flushes come from the oldest instructions in pipe
// Decoding exceptions come from youngest
ftq_arb.io.in(0) <> flush_pc_req
ftq_arb.io.in(1) <> jmp_pc_req
ftq_arb.io.in(2) <> xcpt_pc_req
// Hookup FTQ
io.ifu.get_pc(0).ftq_idx := ftq_arb.io.out.bits
ftq_arb.io.out.ready := true.B
// Branch Unit Requests (for JALs) (Should delay issue of JALs if this not ready)
jmp_pc_req.valid := RegNext(iss_valids(jmp_unit_idx) && iss_uops(jmp_unit_idx).fu_code === FU_JMP)
jmp_pc_req.bits := RegNext(iss_uops(jmp_unit_idx).ftq_idx)
jmp_unit.io.get_ftq_pc := DontCare
jmp_unit.io.get_ftq_pc.pc := io.ifu.get_pc(0).pc
jmp_unit.io.get_ftq_pc.entry := io.ifu.get_pc(0).entry
jmp_unit.io.get_ftq_pc.next_val := io.ifu.get_pc(0).next_val
jmp_unit.io.get_ftq_pc.next_pc := io.ifu.get_pc(0).next_pc
// Frontend Exception Requests
val xcpt_idx = PriorityEncoder(dec_xcpts)
xcpt_pc_req.valid := dec_xcpts.reduce(_||_)
xcpt_pc_req.bits := dec_uops(xcpt_idx).ftq_idx
//rob.io.xcpt_fetch_pc := RegEnable(io.ifu.get_pc.fetch_pc, dis_ready)
rob.io.xcpt_fetch_pc := io.ifu.get_pc(0).pc
flush_pc_req.valid := rob.io.flush.valid
flush_pc_req.bits := rob.io.flush.bits.ftq_idx
// Mispredict requests (to get the correct target)
io.ifu.get_pc(1).ftq_idx := oldest_mispredict_ftq_idx
//-------------------------------------------------------------
// Decode/Rename1 pipeline logic
dec_xcpts := dec_uops zip dec_valids map {case (u,v) => u.exception && v}
val dec_xcpt_stall = dec_xcpts.reduce(_||_) && !xcpt_pc_req.ready
// stall fetch/dcode because we ran out of branch tags
val branch_mask_full = Wire(Vec(coreWidth, Bool()))
val dec_hazards = (0 until coreWidth).map(w =>
dec_valids(w) &&
( !dis_ready
|| rob.io.commit.rollback
|| dec_xcpt_stall
|| branch_mask_full(w)
|| brupdate.b1.mispredict_mask =/= 0.U
|| brupdate.b2.mispredict
|| io.ifu.redirect_flush))
val dec_stalls = dec_hazards.scanLeft(false.B) ((s,h) => s || h).takeRight(coreWidth)
dec_fire := (0 until coreWidth).map(w => dec_valids(w) && !dec_stalls(w))
// all decoders are empty and ready for new instructions
dec_ready := dec_fire.last
when (dec_ready || io.ifu.redirect_flush) {
dec_finished_mask := 0.U
} .otherwise {
dec_finished_mask := dec_fire.asUInt | dec_finished_mask
}
//-------------------------------------------------------------
// Branch Mask Logic
dec_brmask_logic.io.brupdate := brupdate
dec_brmask_logic.io.flush_pipeline := RegNext(rob.io.flush.valid)
for (w <- 0 until coreWidth) {
dec_brmask_logic.io.is_branch(w) := !dec_finished_mask(w) && dec_uops(w).allocate_brtag
dec_brmask_logic.io.will_fire(w) := dec_fire(w) &&
dec_uops(w).allocate_brtag // ren, dis can back pressure us
dec_uops(w).br_tag := dec_brmask_logic.io.br_tag(w)
dec_uops(w).br_mask := dec_brmask_logic.io.br_mask(w)
}
branch_mask_full := dec_brmask_logic.io.is_full
//-------------------------------------------------------------
//-------------------------------------------------------------
// **** Register Rename Stage ****
//-------------------------------------------------------------
//-------------------------------------------------------------
// Inputs
for (rename <- rename_stages) {
rename.io.kill := io.ifu.redirect_flush
rename.io.brupdate := brupdate
rename.io.debug_rob_empty := rob.io.empty
rename.io.dec_fire := dec_fire
rename.io.dec_uops := dec_uops
rename.io.dis_fire := dis_fire
rename.io.dis_ready := dis_ready
rename.io.com_valids := rob.io.commit.valids
rename.io.com_uops := rob.io.commit.uops
rename.io.rbk_valids := rob.io.commit.rbk_valids
rename.io.rollback := rob.io.commit.rollback
}
// Outputs
dis_uops := rename_stage.io.ren2_uops
dis_valids := rename_stage.io.ren2_mask
ren_stalls := rename_stage.io.ren_stalls
/**
* TODO This is a bit nasty, but it's currently necessary to
* split the INT/FP rename pipelines into separate instantiations.
* Won't have to do this anymore with a properly decoupled FP pipeline.
*/
for (w <- 0 until coreWidth) {
val i_uop = rename_stage.io.ren2_uops(w)
val f_uop = if (usingFPU) fp_rename_stage.io.ren2_uops(w) else NullMicroOp
val p_uop = if (enableSFBOpt) pred_rename_stage.io.ren2_uops(w) else NullMicroOp
val f_stall = if (usingFPU) fp_rename_stage.io.ren_stalls(w) else false.B
val p_stall = if (enableSFBOpt) pred_rename_stage.io.ren_stalls(w) else false.B
// lrs1 can "pass through" to prs1. Used solely to index the csr file.
dis_uops(w).prs1 := Mux(dis_uops(w).lrs1_rtype === RT_FLT, f_uop.prs1,
Mux(dis_uops(w).lrs1_rtype === RT_FIX, i_uop.prs1, dis_uops(w).lrs1))
dis_uops(w).prs2 := Mux(dis_uops(w).lrs2_rtype === RT_FLT, f_uop.prs2, i_uop.prs2)
dis_uops(w).prs3 := f_uop.prs3
dis_uops(w).ppred := p_uop.ppred
dis_uops(w).pdst := Mux(dis_uops(w).dst_rtype === RT_FLT, f_uop.pdst,
Mux(dis_uops(w).dst_rtype === RT_FIX, i_uop.pdst,
p_uop.pdst))
dis_uops(w).stale_pdst := Mux(dis_uops(w).dst_rtype === RT_FLT, f_uop.stale_pdst, i_uop.stale_pdst)
dis_uops(w).prs1_busy := i_uop.prs1_busy && (dis_uops(w).lrs1_rtype === RT_FIX) ||
f_uop.prs1_busy && (dis_uops(w).lrs1_rtype === RT_FLT)
dis_uops(w).prs2_busy := i_uop.prs2_busy && (dis_uops(w).lrs2_rtype === RT_FIX) ||
f_uop.prs2_busy && (dis_uops(w).lrs2_rtype === RT_FLT)
dis_uops(w).prs3_busy := f_uop.prs3_busy && dis_uops(w).frs3_en
dis_uops(w).ppred_busy := p_uop.ppred_busy && dis_uops(w).is_sfb_shadow
ren_stalls(w) := rename_stage.io.ren_stalls(w) || f_stall || p_stall
}
//-------------------------------------------------------------
//-------------------------------------------------------------
// **** Dispatch Stage ****
//-------------------------------------------------------------
//-------------------------------------------------------------
//-------------------------------------------------------------
// Rename2/Dispatch pipeline logic
val dis_prior_slot_valid = dis_valids.scanLeft(false.B) ((s,v) => s || v)
val dis_prior_slot_unique = (dis_uops zip dis_valids).scanLeft(false.B) {case (s,(u,v)) => s || v && u.is_unique}
val wait_for_empty_pipeline = (0 until coreWidth).map(w => (dis_uops(w).is_unique || custom_csrs.disableOOO) &&
(!rob.io.empty || !io.lsu.fencei_rdy || dis_prior_slot_valid(w)))
val rocc_shim_busy = if (usingRoCC) !exe_units.rocc_unit.io.rocc.rxq_empty else false.B
val wait_for_rocc = (0 until coreWidth).map(w =>
(dis_uops(w).is_fence || dis_uops(w).is_fencei) && (io.rocc.busy || rocc_shim_busy))
val rxq_full = if (usingRoCC) exe_units.rocc_unit.io.rocc.rxq_full else false.B
val block_rocc = (dis_uops zip dis_valids).map{case (u,v) => v && u.uopc === uopROCC}.scanLeft(rxq_full)(_||_)
val dis_rocc_alloc_stall = (dis_uops.map(_.uopc === uopROCC) zip block_rocc) map {case (p,r) =>
if (usingRoCC) p && r else false.B}
val dis_hazards = (0 until coreWidth).map(w =>
dis_valids(w) &&
( !rob.io.ready
|| ren_stalls(w)
|| io.lsu.ldq_full(w) && dis_uops(w).uses_ldq
|| io.lsu.stq_full(w) && dis_uops(w).uses_stq
|| !dispatcher.io.ren_uops(w).ready
|| wait_for_empty_pipeline(w)
|| wait_for_rocc(w)
|| dis_prior_slot_unique(w)
|| dis_rocc_alloc_stall(w)
|| brupdate.b1.mispredict_mask =/= 0.U
|| brupdate.b2.mispredict
|| io.ifu.redirect_flush))
io.lsu.fence_dmem := (dis_valids zip wait_for_empty_pipeline).map {case (v,w) => v && w} .reduce(_||_)
val dis_stalls = dis_hazards.scanLeft(false.B) ((s,h) => s || h).takeRight(coreWidth)
dis_fire := dis_valids zip dis_stalls map {case (v,s) => v && !s}
dis_ready := !dis_stalls.last
//-------------------------------------------------------------
// LDQ/STQ Allocation Logic
for (w <- 0 until coreWidth) {
// Dispatching instructions request load/store queue entries when they can proceed.
dis_uops(w).ldq_idx := io.lsu.dis_ldq_idx(w)
dis_uops(w).stq_idx := io.lsu.dis_stq_idx(w)
}
//-------------------------------------------------------------
// Rob Allocation Logic
rob.io.enq_valids := dis_fire
rob.io.enq_uops := dis_uops
rob.io.enq_partial_stall := dis_stalls.last // TODO come up with better ROB compacting scheme.
rob.io.debug_tsc := debug_tsc_reg
rob.io.csr_stall := csr.io.csr_stall
// Minor hack: ecall and breaks need to increment the FTQ deq ptr earlier than commit, since
// they write their PC into the CSR the cycle before they commit.
// Since these are also unique, increment the FTQ ptr when they are dispatched
when (RegNext(dis_fire.reduce(_||_) && dis_uops(PriorityEncoder(dis_fire)).is_sys_pc2epc)) {
io.ifu.commit.valid := true.B
io.ifu.commit.bits := RegNext(dis_uops(PriorityEncoder(dis_valids)).ftq_idx)
}
for (w <- 0 until coreWidth) {
// note: this assumes uops haven't been shifted - there's a 1:1 match between PC's LSBs and "w" here
// (thus the LSB of the rob_idx gives part of the PC)
if (coreWidth == 1) {
dis_uops(w).rob_idx := rob.io.rob_tail_idx
} else {
dis_uops(w).rob_idx := Cat(rob.io.rob_tail_idx >> log2Ceil(coreWidth).U,
w.U(log2Ceil(coreWidth).W))
}
}
//-------------------------------------------------------------
// RoCC allocation logic
if (usingRoCC) {
for (w <- 0 until coreWidth) {
// We guarantee only decoding 1 RoCC instruction per cycle
dis_uops(w).rxq_idx := exe_units.rocc_unit.io.rocc.rxq_idx(w)
}
}
//-------------------------------------------------------------
// Dispatch to issue queues
// Get uops from rename2
for (w <- 0 until coreWidth) {
dispatcher.io.ren_uops(w).valid := dis_fire(w)
dispatcher.io.ren_uops(w).bits := dis_uops(w)
}
var iu_idx = 0
// Send dispatched uops to correct issue queues
// Backpressure through dispatcher if necessary
for (i <- 0 until issueParams.size) {
if (issueParams(i).iqType == IQT_FP.litValue) {
fp_pipeline.io.dis_uops <> dispatcher.io.dis_uops(i)
} else {
issue_units(iu_idx).io.dis_uops <> dispatcher.io.dis_uops(i)
iu_idx += 1
}
}
//-------------------------------------------------------------
//-------------------------------------------------------------
// **** Issue Stage ****
//-------------------------------------------------------------
//-------------------------------------------------------------
require (issue_units.map(_.issueWidth).sum == exe_units.length)
var iss_wu_idx = 1
var ren_wu_idx = 1
// The 0th wakeup port goes to the ll_wbarb
int_iss_wakeups(0).valid := ll_wbarb.io.out.fire && ll_wbarb.io.out.bits.uop.dst_rtype === RT_FIX
int_iss_wakeups(0).bits := ll_wbarb.io.out.bits
int_ren_wakeups(0).valid := ll_wbarb.io.out.fire && ll_wbarb.io.out.bits.uop.dst_rtype === RT_FIX
int_ren_wakeups(0).bits := ll_wbarb.io.out.bits
for (i <- 1 until memWidth) {
int_iss_wakeups(i).valid := mem_resps(i).valid && mem_resps(i).bits.uop.dst_rtype === RT_FIX
int_iss_wakeups(i).bits := mem_resps(i).bits
int_ren_wakeups(i).valid := mem_resps(i).valid && mem_resps(i).bits.uop.dst_rtype === RT_FIX
int_ren_wakeups(i).bits := mem_resps(i).bits
iss_wu_idx += 1
ren_wu_idx += 1
}
// loop through each issue-port (exe_units are statically connected to an issue-port)
for (i <- 0 until exe_units.length) {
if (exe_units(i).writesIrf) {
val fast_wakeup = Wire(Valid(new ExeUnitResp(xLen)))
val slow_wakeup = Wire(Valid(new ExeUnitResp(xLen)))
fast_wakeup := DontCare
slow_wakeup := DontCare
val resp = exe_units(i).io.iresp
assert(!(resp.valid && resp.bits.uop.rf_wen && resp.bits.uop.dst_rtype =/= RT_FIX))
// Fast Wakeup (uses just-issued uops that have known latencies)
fast_wakeup.bits.uop := iss_uops(i)
fast_wakeup.valid := iss_valids(i) &&
iss_uops(i).bypassable &&
iss_uops(i).dst_rtype === RT_FIX &&
iss_uops(i).ldst_val &&
!(io.lsu.ld_miss && (iss_uops(i).iw_p1_poisoned || iss_uops(i).iw_p2_poisoned))
// Slow Wakeup (uses write-port to register file)
slow_wakeup.bits.uop := resp.bits.uop
slow_wakeup.valid := resp.valid &&
resp.bits.uop.rf_wen &&
!resp.bits.uop.bypassable &&
resp.bits.uop.dst_rtype === RT_FIX
if (exe_units(i).bypassable) {
int_iss_wakeups(iss_wu_idx) := fast_wakeup
iss_wu_idx += 1
}
if (!exe_units(i).alwaysBypassable) {
int_iss_wakeups(iss_wu_idx) := slow_wakeup
iss_wu_idx += 1
}
if (exe_units(i).bypassable) {
int_ren_wakeups(ren_wu_idx) := fast_wakeup
ren_wu_idx += 1
}
if (!exe_units(i).alwaysBypassable) {
int_ren_wakeups(ren_wu_idx) := slow_wakeup
ren_wu_idx += 1
}
}
}
require (iss_wu_idx == numIntIssueWakeupPorts)
require (ren_wu_idx == numIntRenameWakeupPorts)
require (iss_wu_idx == ren_wu_idx)
// jmp unit performs fast wakeup of the predicate bits
require (jmp_unit.bypassable)
pred_wakeup.valid := (iss_valids(jmp_unit_idx) &&
iss_uops(jmp_unit_idx).is_sfb_br &&
!(io.lsu.ld_miss && (iss_uops(jmp_unit_idx).iw_p1_poisoned || iss_uops(jmp_unit_idx).iw_p2_poisoned))
)
pred_wakeup.bits.uop := iss_uops(jmp_unit_idx)
pred_wakeup.bits.fflags := DontCare
pred_wakeup.bits.data := DontCare
pred_wakeup.bits.predicated := DontCare
// Perform load-hit speculative wakeup through a special port (performs a poison wake-up).
issue_units map { iu =>
iu.io.spec_ld_wakeup := io.lsu.spec_ld_wakeup
}
// Connect the predicate wakeup port
issue_units map { iu =>
iu.io.pred_wakeup_port.valid := false.B
iu.io.pred_wakeup_port.bits := DontCare
}
if (enableSFBOpt) {
int_iss_unit.io.pred_wakeup_port.valid := pred_wakeup.valid
int_iss_unit.io.pred_wakeup_port.bits := pred_wakeup.bits.uop.pdst
}
// ----------------------------------------------------------------
// Connect the wakeup ports to the busy tables in the rename stages
for ((renport, intport) <- rename_stage.io.wakeups zip int_ren_wakeups) {
renport <> intport
}
if (usingFPU) {
for ((renport, fpport) <- fp_rename_stage.io.wakeups zip fp_pipeline.io.wakeups) {
renport <> fpport
}
}
if (enableSFBOpt) {
pred_rename_stage.io.wakeups(0) := pred_wakeup
} else {
pred_rename_stage.io.wakeups := DontCare
}
// If we issue loads back-to-back endlessly (probably because we are executing some tight loop)
// the store buffer will never drain, breaking the memory-model forward-progress guarantee
// If we see a large number of loads saturate the LSU, pause for a cycle to let a store drain
val loads_saturating = (mem_iss_unit.io.iss_valids(0) && mem_iss_unit.io.iss_uops(0).uses_ldq)
val saturating_loads_counter = RegInit(0.U(5.W))
when (loads_saturating) { saturating_loads_counter := saturating_loads_counter + 1.U }
.otherwise { saturating_loads_counter := 0.U }
val pause_mem = RegNext(loads_saturating) && saturating_loads_counter === ~(0.U(5.W))
var iss_idx = 0
var int_iss_cnt = 0
var mem_iss_cnt = 0
for (w <- 0 until exe_units.length) {
var fu_types = exe_units(w).io.fu_types
val exe_unit = exe_units(w)
if (exe_unit.readsIrf) {
if (exe_unit.supportedFuncUnits.muld) {
// Supress just-issued divides from issuing back-to-back, since it's an iterative divider.
// But it takes a cycle to get to the Exe stage, so it can't tell us it is busy yet.
val idiv_issued = iss_valids(iss_idx) && iss_uops(iss_idx).fu_code_is(FU_DIV)
fu_types = fu_types & RegNext(~Mux(idiv_issued, FU_DIV, 0.U))
}
if (exe_unit.hasMem) {
iss_valids(iss_idx) := mem_iss_unit.io.iss_valids(mem_iss_cnt)
iss_uops(iss_idx) := mem_iss_unit.io.iss_uops(mem_iss_cnt)
mem_iss_unit.io.fu_types(mem_iss_cnt) := Mux(pause_mem, 0.U, fu_types)
mem_iss_cnt += 1
} else {
iss_valids(iss_idx) := int_iss_unit.io.iss_valids(int_iss_cnt)
iss_uops(iss_idx) := int_iss_unit.io.iss_uops(int_iss_cnt)
int_iss_unit.io.fu_types(int_iss_cnt) := fu_types
int_iss_cnt += 1
}
iss_idx += 1
}
}
require(iss_idx == exe_units.numIrfReaders)
issue_units.map(_.io.tsc_reg := debug_tsc_reg)
issue_units.map(_.io.brupdate := brupdate)
issue_units.map(_.io.flush_pipeline := RegNext(rob.io.flush.valid))
// Load-hit Misspeculations
require (mem_iss_unit.issueWidth <= 2)
issue_units.map(_.io.ld_miss := io.lsu.ld_miss)
mem_units.map(u => u.io.com_exception := RegNext(rob.io.flush.valid))
// Wakeup (Issue & Writeback)
for {
iu <- issue_units
(issport, wakeup) <- iu.io.wakeup_ports zip int_iss_wakeups
}{
issport.valid := wakeup.valid
issport.bits.pdst := wakeup.bits.uop.pdst
issport.bits.poisoned := wakeup.bits.uop.iw_p1_poisoned || wakeup.bits.uop.iw_p2_poisoned
require (iu.io.wakeup_ports.length == int_iss_wakeups.length)
}
//-------------------------------------------------------------
//-------------------------------------------------------------
// **** Register Read Stage ****
//-------------------------------------------------------------
//-------------------------------------------------------------
// Register Read <- Issue (rrd <- iss)
iregister_read.io.rf_read_ports <> iregfile.io.read_ports
iregister_read.io.prf_read_ports := DontCare
if (enableSFBOpt) {
iregister_read.io.prf_read_ports <> pregfile.io.read_ports
}
for (w <- 0 until exe_units.numIrfReaders) {
iregister_read.io.iss_valids(w) :=
iss_valids(w) && !(io.lsu.ld_miss && (iss_uops(w).iw_p1_poisoned || iss_uops(w).iw_p2_poisoned))
}
iregister_read.io.iss_uops := iss_uops
iregister_read.io.iss_uops map { u => u.iw_p1_poisoned := false.B; u.iw_p2_poisoned := false.B }
iregister_read.io.brupdate := brupdate
iregister_read.io.kill := RegNext(rob.io.flush.valid)
iregister_read.io.bypass := bypasses
iregister_read.io.pred_bypass := pred_bypasses
//-------------------------------------------------------------
// Privileged Co-processor 0 Register File
// Note: Normally this would be bad in that I'm writing state before
// committing, so to get this to work I stall the entire pipeline for
// CSR instructions so I never speculate these instructions.
val csr_exe_unit = exe_units.csr_unit
// for critical path reasons, we aren't zero'ing this out if resp is not valid
val csr_rw_cmd = csr_exe_unit.io.iresp.bits.uop.ctrl.csr_cmd
val wb_wdata = csr_exe_unit.io.iresp.bits.data
csr.io.rw.addr := csr_exe_unit.io.iresp.bits.uop.csr_addr
csr.io.rw.cmd := freechips.rocketchip.rocket.CSR.maskCmd(csr_exe_unit.io.iresp.valid, csr_rw_cmd)
csr.io.rw.wdata := wb_wdata
rob.io.csr_replay.valid := csr_exe_unit.io.iresp.valid && csr.io.rw_stall
rob.io.csr_replay.bits.uop := csr_exe_unit.io.iresp.bits.uop
rob.io.csr_replay.bits.cause := MINI_EXCEPTION_CSR_REPLAY
rob.io.csr_replay.bits.badvaddr := DontCare
// Extra I/O
// Delay retire/exception 1 cycle
csr.io.retire := RegNext(PopCount(rob.io.commit.arch_valids.asUInt))
csr.io.exception := RegNext(rob.io.com_xcpt.valid)
// csr.io.pc used for setting EPC during exception or CSR.io.trace.
csr.io.pc := (boom.v3.util.AlignPCToBoundary(io.ifu.get_pc(0).com_pc, icBlockBytes)
+ RegNext(rob.io.com_xcpt.bits.pc_lob)
- Mux(RegNext(rob.io.com_xcpt.bits.edge_inst), 2.U, 0.U))
// Cause not valid for for CALL or BREAKPOINTs (CSRFile will override it).
csr.io.cause := RegNext(rob.io.com_xcpt.bits.cause)
csr.io.ungated_clock := clock
val tval_valid = csr.io.exception &&
csr.io.cause.isOneOf(
//Causes.illegal_instruction.U, we currently only write 0x0 for illegal instructions
Causes.breakpoint.U,
Causes.misaligned_load.U,
Causes.misaligned_store.U,
Causes.load_access.U,
Causes.store_access.U,
Causes.fetch_access.U,
Causes.load_page_fault.U,
Causes.store_page_fault.U,
Causes.fetch_page_fault.U)
csr.io.tval := Mux(tval_valid,
RegNext(encodeVirtualAddress(rob.io.com_xcpt.bits.badvaddr, rob.io.com_xcpt.bits.badvaddr)), 0.U)
// TODO move this function to some central location (since this is used elsewhere).
def encodeVirtualAddress(a0: UInt, ea: UInt) =
if (vaddrBitsExtended == vaddrBits) {
ea
} else {
// Efficient means to compress 64-bit VA into vaddrBits+1 bits.
// (VA is bad if VA(vaddrBits) != VA(vaddrBits-1)).
val a = a0.asSInt >> vaddrBits
val msb = Mux(a === 0.S || a === -1.S, ea(vaddrBits), !ea(vaddrBits-1))
Cat(msb, ea(vaddrBits-1,0))
}
// reading requires serializing the entire pipeline
csr.io.fcsr_flags.valid := rob.io.commit.fflags.valid
csr.io.fcsr_flags.bits := rob.io.commit.fflags.bits
csr.io.set_fs_dirty.get := rob.io.commit.fflags.valid
exe_units.withFilter(_.hasFcsr).map(_.io.fcsr_rm := csr.io.fcsr_rm)
io.fcsr_rm := csr.io.fcsr_rm
if (usingFPU) {
fp_pipeline.io.fcsr_rm := csr.io.fcsr_rm
}
csr.io.hartid := io.hartid
csr.io.interrupts := io.interrupts
// we do not support the H-extension
csr.io.htval := DontCare
csr.io.gva := DontCare
// TODO can we add this back in, but handle reset properly and save us
// the mux above on csr.io.rw.cmd?
// assert (!(csr_rw_cmd =/= rocket.CSR.N && !exe_units(0).io.resp(0).valid),
// "CSRFile is being written to spuriously.")
//-------------------------------------------------------------
//-------------------------------------------------------------
// **** Execute Stage ****
//-------------------------------------------------------------
//-------------------------------------------------------------
iss_idx = 0
var bypass_idx = 0
for (w <- 0 until exe_units.length) {
val exe_unit = exe_units(w)
if (exe_unit.readsIrf) {
exe_unit.io.req <> iregister_read.io.exe_reqs(iss_idx)
if (exe_unit.bypassable) {
for (i <- 0 until exe_unit.numBypassStages) {
bypasses(bypass_idx) := exe_unit.io.bypass(i)
bypass_idx += 1
}
}
iss_idx += 1
}
}
require (bypass_idx == exe_units.numTotalBypassPorts)
for (i <- 0 until jmp_unit.numBypassStages) {
pred_bypasses(i) := jmp_unit.io.bypass(i)
}
//-------------------------------------------------------------
//-------------------------------------------------------------
// **** Load/Store Unit ****
//-------------------------------------------------------------
//-------------------------------------------------------------
// enqueue basic load/store info in Decode
for (w <- 0 until coreWidth) {
io.lsu.dis_uops(w).valid := dis_fire(w)
io.lsu.dis_uops(w).bits := dis_uops(w)
}
// tell LSU about committing loads and stores to clear entries
io.lsu.commit := rob.io.commit
// tell LSU that it should fire a load that waits for the rob to clear
io.lsu.commit_load_at_rob_head := rob.io.com_load_is_at_rob_head
//com_xcpt.valid comes too early, will fight against a branch that resolves same cycle as an exception
io.lsu.exception := RegNext(rob.io.flush.valid)
// Handle Branch Mispeculations
io.lsu.brupdate := brupdate
io.lsu.rob_head_idx := rob.io.rob_head_idx
io.lsu.rob_pnr_idx := rob.io.rob_pnr_idx
io.lsu.tsc_reg := debug_tsc_reg
if (usingFPU) {
io.lsu.fp_stdata <> fp_pipeline.io.to_sdq
}
//-------------------------------------------------------------
//-------------------------------------------------------------
// **** Writeback Stage ****
//-------------------------------------------------------------
//-------------------------------------------------------------
var w_cnt = 1
iregfile.io.write_ports(0) := WritePort(ll_wbarb.io.out, ipregSz, xLen, RT_FIX)
ll_wbarb.io.in(0) <> mem_resps(0)
assert (ll_wbarb.io.in(0).ready) // never backpressure the memory unit.
for (i <- 1 until memWidth) {
iregfile.io.write_ports(w_cnt) := WritePort(mem_resps(i), ipregSz, xLen, RT_FIX)
w_cnt += 1
}
for (i <- 0 until exe_units.length) {
if (exe_units(i).writesIrf) {
val wbresp = exe_units(i).io.iresp
val wbpdst = wbresp.bits.uop.pdst
val wbdata = wbresp.bits.data
def wbIsValid(rtype: UInt) =
wbresp.valid && wbresp.bits.uop.rf_wen && wbresp.bits.uop.dst_rtype === rtype
val wbReadsCSR = wbresp.bits.uop.ctrl.csr_cmd =/= freechips.rocketchip.rocket.CSR.N
iregfile.io.write_ports(w_cnt).valid := wbIsValid(RT_FIX)
iregfile.io.write_ports(w_cnt).bits.addr := wbpdst
wbresp.ready := true.B
if (exe_units(i).hasCSR) {
iregfile.io.write_ports(w_cnt).bits.data := Mux(wbReadsCSR, csr.io.rw.rdata, wbdata)
} else {
iregfile.io.write_ports(w_cnt).bits.data := wbdata
}
assert (!wbIsValid(RT_FLT), "[fppipeline] An FP writeback is being attempted to the Int Regfile.")
assert (!(wbresp.valid &&
!wbresp.bits.uop.rf_wen &&
wbresp.bits.uop.dst_rtype === RT_FIX),
"[fppipeline] An Int writeback is being attempted with rf_wen disabled.")
assert (!(wbresp.valid &&
wbresp.bits.uop.rf_wen &&
wbresp.bits.uop.dst_rtype =/= RT_FIX),
"[fppipeline] writeback being attempted to Int RF with dst != Int type exe_units("+i+").iresp")
w_cnt += 1
}
}
require(w_cnt == iregfile.io.write_ports.length)
if (enableSFBOpt) {
pregfile.io.write_ports(0).valid := jmp_unit.io.iresp.valid && jmp_unit.io.iresp.bits.uop.is_sfb_br
pregfile.io.write_ports(0).bits.addr := jmp_unit.io.iresp.bits.uop.pdst
pregfile.io.write_ports(0).bits.data := jmp_unit.io.iresp.bits.data
}
if (usingFPU) {
// Connect IFPU
fp_pipeline.io.from_int <> exe_units.ifpu_unit.io.ll_fresp
// Connect FPIU
ll_wbarb.io.in(1) <> fp_pipeline.io.to_int
// Connect FLDs
fp_pipeline.io.ll_wports <> exe_units.memory_units.map(_.io.ll_fresp).toSeq
}
if (usingRoCC) {
require(usingFPU)
ll_wbarb.io.in(2) <> exe_units.rocc_unit.io.ll_iresp
}
//-------------------------------------------------------------
//-------------------------------------------------------------
// **** Commit Stage ****
//-------------------------------------------------------------
//-------------------------------------------------------------
// Writeback
// ---------
// First connect the ll_wport
val ll_uop = ll_wbarb.io.out.bits.uop
rob.io.wb_resps(0).valid := ll_wbarb.io.out.valid && !(ll_uop.uses_stq && !ll_uop.is_amo)
rob.io.wb_resps(0).bits <> ll_wbarb.io.out.bits
rob.io.debug_wb_valids(0) := ll_wbarb.io.out.valid && ll_uop.dst_rtype =/= RT_X
rob.io.debug_wb_wdata(0) := ll_wbarb.io.out.bits.data
var cnt = 1
for (i <- 1 until memWidth) {
val mem_uop = mem_resps(i).bits.uop
rob.io.wb_resps(cnt).valid := mem_resps(i).valid && !(mem_uop.uses_stq && !mem_uop.is_amo)
rob.io.wb_resps(cnt).bits := mem_resps(i).bits
rob.io.debug_wb_valids(cnt) := mem_resps(i).valid && mem_uop.dst_rtype =/= RT_X
rob.io.debug_wb_wdata(cnt) := mem_resps(i).bits.data
cnt += 1
}
var f_cnt = 0 // rob fflags port index
for (eu <- exe_units) {
if (eu.writesIrf)
{
val resp = eu.io.iresp
val wb_uop = resp.bits.uop
val data = resp.bits.data
rob.io.wb_resps(cnt).valid := resp.valid && !(wb_uop.uses_stq && !wb_uop.is_amo)
rob.io.wb_resps(cnt).bits <> resp.bits
rob.io.debug_wb_valids(cnt) := resp.valid && wb_uop.rf_wen && wb_uop.dst_rtype === RT_FIX
if (eu.hasFFlags) {
rob.io.fflags(f_cnt) <> resp.bits.fflags
f_cnt += 1
}
if (eu.hasCSR) {
rob.io.debug_wb_wdata(cnt) := Mux(wb_uop.ctrl.csr_cmd =/= freechips.rocketchip.rocket.CSR.N,
csr.io.rw.rdata,
data)
} else {
rob.io.debug_wb_wdata(cnt) := data
}
cnt += 1
}
}
require(cnt == numIrfWritePorts)
if (usingFPU) {
for ((wdata, wakeup) <- fp_pipeline.io.debug_wb_wdata zip fp_pipeline.io.wakeups) {
rob.io.wb_resps(cnt) <> wakeup
rob.io.fflags(f_cnt) <> wakeup.bits.fflags
rob.io.debug_wb_valids(cnt) := wakeup.valid
rob.io.debug_wb_wdata(cnt) := wdata
cnt += 1
f_cnt += 1
assert (!(wakeup.valid && wakeup.bits.uop.dst_rtype =/= RT_FLT),
"[core] FP wakeup does not write back to a FP register.")
assert (!(wakeup.valid && !wakeup.bits.uop.fp_val),
"[core] FP wakeup does not involve an FP instruction.")
}
}
require (cnt == rob.numWakeupPorts)
require (f_cnt == rob.numFpuPorts)
// branch resolution
rob.io.brupdate <> brupdate
exe_units.map(u => u.io.status := csr.io.status)
if (usingFPU)
fp_pipeline.io.status := csr.io.status
// Connect breakpoint info to memaddrcalcunit
for (i <- 0 until memWidth) {
mem_units(i).io.status := csr.io.status
mem_units(i).io.bp := csr.io.bp
mem_units(i).io.mcontext := csr.io.mcontext
mem_units(i).io.scontext := csr.io.scontext
}
// LSU <> ROB
rob.io.lsu_clr_bsy := io.lsu.clr_bsy
rob.io.lsu_clr_unsafe := io.lsu.clr_unsafe
rob.io.lxcpt <> io.lsu.lxcpt
assert (!(csr.io.singleStep), "[core] single-step is unsupported.")
//-------------------------------------------------------------
// **** Flush Pipeline ****
//-------------------------------------------------------------
// flush on exceptions, miniexeptions, and after some special instructions
if (usingFPU) {
fp_pipeline.io.flush_pipeline := RegNext(rob.io.flush.valid)
}
for (w <- 0 until exe_units.length) {
exe_units(w).io.req.bits.kill := RegNext(rob.io.flush.valid)
}
assert (!(rob.io.com_xcpt.valid && !rob.io.flush.valid),
"[core] exception occurred, but pipeline flush signal not set!")
//-------------------------------------------------------------
//-------------------------------------------------------------
// **** Outputs to the External World ****
//-------------------------------------------------------------
//-------------------------------------------------------------
// detect pipeline freezes and throw error
val idle_cycles = freechips.rocketchip.util.WideCounter(32)
when (rob.io.commit.valids.asUInt.orR ||
csr.io.csr_stall ||
io.rocc.busy ||
reset.asBool) {
idle_cycles := 0.U
}
assert (!(idle_cycles.value(13)), "Pipeline has hung.")
if (usingFPU) {
fp_pipeline.io.debug_tsc_reg := debug_tsc_reg
}
//-------------------------------------------------------------
//-------------------------------------------------------------
// **** Handle Cycle-by-Cycle Printouts ****
//-------------------------------------------------------------
//-------------------------------------------------------------
if (COMMIT_LOG_PRINTF) {
var new_commit_cnt = 0.U
for (w <- 0 until coreWidth) {
val priv = RegNext(csr.io.status.prv) // erets change the privilege. Get the old one
// To allow for diffs against spike :/
def printf_inst(uop: MicroOp) = {
when (uop.is_rvc) {
printf("(0x%x)", uop.debug_inst(15,0))
} .otherwise {
printf("(0x%x)", uop.debug_inst)
}
}
when (rob.io.commit.arch_valids(w)) {
printf("%d 0x%x ",
priv,
Sext(rob.io.commit.uops(w).debug_pc(vaddrBits-1,0), xLen))
printf_inst(rob.io.commit.uops(w))
when (rob.io.commit.uops(w).dst_rtype === RT_FIX && rob.io.commit.uops(w).ldst =/= 0.U) {
printf(" x%d 0x%x\n",
rob.io.commit.uops(w).ldst,
rob.io.commit.debug_wdata(w))
} .elsewhen (rob.io.commit.uops(w).dst_rtype === RT_FLT) {
printf(" f%d 0x%x\n",
rob.io.commit.uops(w).ldst,
rob.io.commit.debug_wdata(w))
} .otherwise {
printf("\n")
}
}
}
} else if (BRANCH_PRINTF) {
val debug_ghist = RegInit(0.U(globalHistoryLength.W))
when (rob.io.flush.valid && FlushTypes.useCsrEvec(rob.io.flush.bits.flush_typ)) {
debug_ghist := 0.U
}
var new_ghist = debug_ghist
for (w <- 0 until coreWidth) {
when (rob.io.commit.arch_valids(w) &&
(rob.io.commit.uops(w).is_br || rob.io.commit.uops(w).is_jal || rob.io.commit.uops(w).is_jalr)) {
// for (i <- 0 until globalHistoryLength) {
// printf("%x", new_ghist(globalHistoryLength-i-1))
// }
// printf("\n")
printf("%x %x %x %x %x %x\n",
rob.io.commit.uops(w).debug_fsrc, rob.io.commit.uops(w).taken,
rob.io.commit.uops(w).is_br, rob.io.commit.uops(w).is_jal,
rob.io.commit.uops(w).is_jalr, Sext(rob.io.commit.uops(w).debug_pc(vaddrBits-1,0), xLen))
}
new_ghist = Mux(rob.io.commit.arch_valids(w) && rob.io.commit.uops(w).is_br,
Mux(rob.io.commit.uops(w).taken, new_ghist << 1 | 1.U(1.W), new_ghist << 1),
new_ghist)
}
debug_ghist := new_ghist
}
// TODO: Does anyone want this debugging functionality?
val coreMonitorBundle = Wire(new CoreMonitorBundle(xLen, fLen))
coreMonitorBundle := DontCare
coreMonitorBundle.clock := clock
coreMonitorBundle.reset := reset
//-------------------------------------------------------------
//-------------------------------------------------------------
// Page Table Walker
io.ptw.ptbr := csr.io.ptbr
io.ptw.status := csr.io.status
io.ptw.pmp := csr.io.pmp
io.ptw.sfence := io.ifu.sfence
//-------------------------------------------------------------
//-------------------------------------------------------------
io.rocc := DontCare
io.rocc.exception := csr.io.exception && csr.io.status.xs.orR
io.rocc.csrs <> csr.io.roccCSRs
if (usingRoCC) {
exe_units.rocc_unit.io.rocc.rocc <> io.rocc
exe_units.rocc_unit.io.rocc.dis_uops := dis_uops
exe_units.rocc_unit.io.rocc.rob_head_idx := rob.io.rob_head_idx
exe_units.rocc_unit.io.rocc.rob_pnr_idx := rob.io.rob_pnr_idx
exe_units.rocc_unit.io.com_exception := rob.io.flush.valid
exe_units.rocc_unit.io.status := csr.io.status
for (w <- 0 until coreWidth) {
exe_units.rocc_unit.io.rocc.dis_rocc_vals(w) := (
dis_fire(w) &&
dis_uops(w).uopc === uopROCC &&
!dis_uops(w).exception
)
}
}
io.trace := DontCare
io.trace.time := csr.io.time
io.trace.insns map (t => t.valid := false.B)
io.trace.custom.get.asInstanceOf[BoomTraceBundle].rob_empty := rob.io.empty
if (trace) {
for (w <- 0 until coreWidth) {
// Delay the trace so we have a cycle to pull PCs out of the FTQ
io.trace.insns(w).valid := RegNext(rob.io.commit.arch_valids(w))
// Recalculate the PC
io.ifu.debug_ftq_idx(w) := rob.io.commit.uops(w).ftq_idx
val iaddr = (AlignPCToBoundary(io.ifu.debug_fetch_pc(w), icBlockBytes)
+ RegNext(rob.io.commit.uops(w).pc_lob)
- Mux(RegNext(rob.io.commit.uops(w).edge_inst), 2.U, 0.U))(vaddrBits-1,0)
io.trace.insns(w).iaddr := Sext(iaddr, xLen)
def getInst(uop: MicroOp, inst: UInt): UInt = {
Mux(uop.is_rvc, Cat(0.U(16.W), inst(15,0)), inst)
}
def getWdata(uop: MicroOp, wdata: UInt): UInt = {
Mux((uop.dst_rtype === RT_FIX && uop.ldst =/= 0.U) || (uop.dst_rtype === RT_FLT), wdata, 0.U(xLen.W))
}
// use debug_insts instead of uop.debug_inst to use the rob's debug_inst_mem
// note: rob.debug_insts comes 1 cycle later
io.trace.insns(w).insn := getInst(RegNext(rob.io.commit.uops(w)), rob.io.commit.debug_insts(w))
io.trace.insns(w).wdata.map { _ := RegNext(getWdata(rob.io.commit.uops(w), rob.io.commit.debug_wdata(w))) }
// Comment out this assert because it blows up FPGA synth-asserts
// This tests correctedness of the debug_inst mem
// when (RegNext(rob.io.commit.valids(w))) {
// assert(rob.io.commit.debug_insts(w) === RegNext(rob.io.commit.uops(w).debug_inst))
// }
// This tests correctedness of recovering pcs through ftq debug ports
// when (RegNext(rob.io.commit.valids(w))) {
// assert(Sext(io.trace.insns(w).iaddr, xLen) ===
// RegNext(Sext(rob.io.commit.uops(w).debug_pc(vaddrBits-1,0), xLen)))
// }
// These csr signals do not exactly match up with the ROB commit signals.
io.trace.insns(w).priv := RegNext(Cat(RegNext(csr.io.status.debug), csr.io.status.prv))
// Can determine if it is an interrupt or not based on the MSB of the cause
io.trace.insns(w).exception := RegNext(rob.io.com_xcpt.valid && !rob.io.com_xcpt.bits.cause(xLen - 1)) && (w == 0).B
io.trace.insns(w).interrupt := RegNext(rob.io.com_xcpt.valid && rob.io.com_xcpt.bits.cause(xLen - 1)) && (w == 0).B
io.trace.insns(w).cause := RegNext(rob.io.com_xcpt.bits.cause)
io.trace.insns(w).tval := RegNext(csr.io.tval)
}
dontTouch(io.trace)
} else {
io.ifu.debug_ftq_idx := DontCare
}
}
File Counters.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
// Produces 0-width value when counting to 1
class ZCounter(val n: Int) {
val value = RegInit(0.U(log2Ceil(n).W))
def inc(): Bool = {
if (n == 1) true.B
else {
val wrap = value === (n-1).U
value := Mux(!isPow2(n).B && wrap, 0.U, value + 1.U)
wrap
}
}
}
object ZCounter {
def apply(n: Int) = new ZCounter(n)
def apply(cond: Bool, n: Int): (UInt, Bool) = {
val c = new ZCounter(n)
var wrap: Bool = null
when (cond) { wrap = c.inc() }
(c.value, cond && wrap)
}
}
object TwoWayCounter {
def apply(up: Bool, down: Bool, max: Int): UInt = {
val cnt = RegInit(0.U(log2Up(max + 1).W))
when (up && !down) { cnt := cnt + 1.U }
when (down && !up) { cnt := cnt - 1.U }
cnt
}
}
// a counter that clock gates most of its MSBs using the LSB carry-out
case class WideCounter(width: Int, inc: UInt = 1.U, reset: Boolean = true, inhibit: Bool = false.B) {
private val isWide = width > (2 * inc.getWidth)
private val smallWidth = if (isWide) inc.getWidth max log2Up(width) else width
private val small = if (reset) RegInit(0.U(smallWidth.W)) else Reg(UInt(smallWidth.W))
private val nextSmall = small +& inc
when (!inhibit) { small := nextSmall }
private val large = if (isWide) {
val r = if (reset) RegInit(0.U((width - smallWidth).W)) else Reg(UInt((width - smallWidth).W))
when (nextSmall(smallWidth) && !inhibit) { r := r + 1.U }
r
} else null
val value = if (isWide) Cat(large, small) else small
lazy val carryOut = {
val lo = (small ^ nextSmall) >> 1
if (!isWide)
lo
else {
val hi = Mux(nextSmall(smallWidth), large ^ (large +& 1.U), 0.U) >> 1
Cat(hi, lo)
}
}
def := (x: UInt) = {
small := x
if (isWide) large := x >> smallWidth
}
}
File util.scala:
//******************************************************************************
// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Utility Functions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v3.util
import chisel3._
import chisel3.util._
import freechips.rocketchip.rocket.Instructions._
import freechips.rocketchip.rocket._
import freechips.rocketchip.util.{Str}
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.tile.{TileKey}
import boom.v3.common.{MicroOp}
import boom.v3.exu.{BrUpdateInfo}
/**
* Object to XOR fold a input register of fullLength into a compressedLength.
*/
object Fold
{
def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = {
val clen = compressedLength
val hlen = fullLength
if (hlen <= clen) {
input
} else {
var res = 0.U(clen.W)
var remaining = input.asUInt
for (i <- 0 to hlen-1 by clen) {
val len = if (i + clen > hlen ) (hlen - i) else clen
require(len > 0)
res = res(clen-1,0) ^ remaining(len-1,0)
remaining = remaining >> len.U
}
res
}
}
}
/**
* Object to check if MicroOp was killed due to a branch mispredict.
* Uses "Fast" branch masks
*/
object IsKilledByBranch
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): Bool = {
return maskMatch(brupdate.b1.mispredict_mask, uop.br_mask)
}
def apply(brupdate: BrUpdateInfo, uop_mask: UInt): Bool = {
return maskMatch(brupdate.b1.mispredict_mask, uop_mask)
}
}
/**
* Object to return new MicroOp with a new BR mask given a MicroOp mask
* and old BR mask.
*/
object GetNewUopAndBrMask
{
def apply(uop: MicroOp, brupdate: BrUpdateInfo)
(implicit p: Parameters): MicroOp = {
val newuop = WireInit(uop)
newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask
newuop
}
}
/**
* Object to return a BR mask given a MicroOp mask and old BR mask.
*/
object GetNewBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = {
return uop.br_mask & ~brupdate.b1.resolve_mask
}
def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = {
return br_mask & ~brupdate.b1.resolve_mask
}
}
object UpdateBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = {
val out = WireInit(uop)
out.br_mask := GetNewBrMask(brupdate, uop)
out
}
def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = {
val out = WireInit(bundle)
out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask)
out
}
def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: Valid[T]): Valid[T] = {
val out = WireInit(bundle)
out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask)
out.valid := bundle.valid && !IsKilledByBranch(brupdate, bundle.bits.uop.br_mask)
out
}
}
/**
* Object to check if at least 1 bit matches in two masks
*/
object maskMatch
{
def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U
}
/**
* Object to clear one bit in a mask given an index
*/
object clearMaskBit
{
def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0)
}
/**
* Object to shift a register over by one bit and concat a new one
*/
object PerformShiftRegister
{
def apply(reg_val: UInt, new_bit: Bool): UInt = {
reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt
reg_val
}
}
/**
* Object to shift a register over by one bit, wrapping the top bit around to the bottom
* (XOR'ed with a new-bit), and evicting a bit at index HLEN.
* This is used to simulate a longer HLEN-width shift register that is folded
* down to a compressed CLEN.
*/
object PerformCircularShiftRegister
{
def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = {
val carry = csr(clen-1)
val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U)
newval
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapAdd
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, amt: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + amt)(log2Ceil(n)-1,0)
} else {
val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt)
Mux(sum >= n.U,
sum - n.U,
sum)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapSub
{
// "n" is the number of increments, so we wrap to n-1.
def apply(value: UInt, amt: Int, n: Int): UInt = {
if (isPow2(n)) {
(value - amt.U)(log2Ceil(n)-1,0)
} else {
val v = Cat(0.U(1.W), value)
val b = Cat(0.U(1.W), amt.U)
Mux(value >= amt.U,
value - amt.U,
n.U - amt.U + value)
}
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapInc
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === (n-1).U)
Mux(wrap, 0.U, value + 1.U)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapDec
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value - 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === 0.U)
Mux(wrap, (n-1).U, value - 1.U)
}
}
}
/**
* Object to mask off lower bits of a PC to align to a "b"
* Byte boundary.
*/
object AlignPCToBoundary
{
def apply(pc: UInt, b: Int): UInt = {
// Invert for scenario where pc longer than b
// (which would clear all bits above size(b)).
~(~pc | (b-1).U)
}
}
/**
* Object to rotate a signal left by one
*/
object RotateL1
{
def apply(signal: UInt): UInt = {
val w = signal.getWidth
val out = Cat(signal(w-2,0), signal(w-1))
return out
}
}
/**
* Object to sext a value to a particular length.
*/
object Sext
{
def apply(x: UInt, length: Int): UInt = {
if (x.getWidth == length) return x
else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x)
}
}
/**
* Object to translate from BOOM's special "packed immediate" to a 32b signed immediate
* Asking for U-type gives it shifted up 12 bits.
*/
object ImmGen
{
import boom.v3.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U}
def apply(ip: UInt, isel: UInt): SInt = {
val sign = ip(LONGEST_IMM_SZ-1).asSInt
val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign)
val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign)
val i11 = Mux(isel === IS_U, 0.S,
Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign))
val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt)
val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt)
val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S)
return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0).asSInt
}
}
/**
* Object to get the FP rounding mode out of a packed immediate.
*/
object ImmGenRm { def apply(ip: UInt): UInt = { return ip(2,0) } }
/**
* Object to get the FP function fype from a packed immediate.
* Note: only works if !(IS_B or IS_S)
*/
object ImmGenTyp { def apply(ip: UInt): UInt = { return ip(9,8) } }
/**
* Object to see if an instruction is a JALR.
*/
object DebugIsJALR
{
def apply(inst: UInt): Bool = {
// TODO Chisel not sure why this won't compile
// val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)),
// Array(
// JALR -> Bool(true)))
inst(6,0) === "b1100111".U
}
}
/**
* Object to take an instruction and output its branch or jal target. Only used
* for a debug assert (no where else would we jump straight from instruction
* bits to a target).
*/
object DebugGetBJImm
{
def apply(inst: UInt): UInt = {
// TODO Chisel not sure why this won't compile
//val csignals =
//rocket.DecodeLogic(inst,
// List(Bool(false), Bool(false)),
// Array(
// BEQ -> List(Bool(true ), Bool(false)),
// BNE -> List(Bool(true ), Bool(false)),
// BGE -> List(Bool(true ), Bool(false)),
// BGEU -> List(Bool(true ), Bool(false)),
// BLT -> List(Bool(true ), Bool(false)),
// BLTU -> List(Bool(true ), Bool(false))
// ))
//val is_br :: nothing :: Nil = csignals
val is_br = (inst(6,0) === "b1100011".U)
val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W))
val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W))
Mux(is_br, br_targ, jal_targ)
}
}
/**
* Object to return the lowest bit position after the head.
*/
object AgePriorityEncoder
{
def apply(in: Seq[Bool], head: UInt): UInt = {
val n = in.size
val width = log2Ceil(in.size)
val n_padded = 1 << width
val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in
val idx = PriorityEncoder(temp_vec)
idx(width-1, 0) //discard msb
}
}
/**
* Object to determine whether queue
* index i0 is older than index i1.
*/
object IsOlder
{
def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head))
}
/**
* Set all bits at or below the highest order '1'.
*/
object MaskLower
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => in >> i.U).reduce(_|_)
}
}
/**
* Set all bits at or above the lowest order '1'.
*/
object MaskUpper
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_)
}
}
/**
* Transpose a matrix of Chisel Vecs.
*/
object Transpose
{
def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = {
val n = in(0).size
VecInit((0 until n).map(i => VecInit(in.map(row => row(i)))))
}
}
/**
* N-wide one-hot priority encoder.
*/
object SelectFirstN
{
def apply(in: UInt, n: Int) = {
val sels = Wire(Vec(n, UInt(in.getWidth.W)))
var mask = in
for (i <- 0 until n) {
sels(i) := PriorityEncoderOH(mask)
mask = mask & ~sels(i)
}
sels
}
}
/**
* Connect the first k of n valid input interfaces to k output interfaces.
*/
class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module
{
require(n >= k)
val io = IO(new Bundle {
val in = Vec(n, Flipped(DecoupledIO(gen)))
val out = Vec(k, DecoupledIO(gen))
})
if (n == k) {
io.out <> io.in
} else {
val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c))
val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col =>
(col zip io.in.map(_.valid)) map {case (c,v) => c && v})
val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_))
val out_valids = sels map (col => col.reduce(_||_))
val out_data = sels map (s => Mux1H(s, io.in.map(_.bits)))
in_readys zip io.in foreach {case (r,i) => i.ready := r}
out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d}
}
}
/**
* Create a queue that can be killed with a branch kill signal.
* Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq).
*/
class BranchKillableQueue[T <: boom.v3.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v3.common.MicroOp => Bool = u => true.B, flow: Boolean = true)
(implicit p: org.chipsalliance.cde.config.Parameters)
extends boom.v3.common.BoomModule()(p)
with boom.v3.common.HasBoomCoreParameters
{
val io = IO(new Bundle {
val enq = Flipped(Decoupled(gen))
val deq = Decoupled(gen)
val brupdate = Input(new BrUpdateInfo())
val flush = Input(Bool())
val empty = Output(Bool())
val count = Output(UInt(log2Ceil(entries).W))
})
val ram = Mem(entries, gen)
val valids = RegInit(VecInit(Seq.fill(entries) {false.B}))
val uops = Reg(Vec(entries, new MicroOp))
val enq_ptr = Counter(entries)
val deq_ptr = Counter(entries)
val maybe_full = RegInit(false.B)
val ptr_match = enq_ptr.value === deq_ptr.value
io.empty := ptr_match && !maybe_full
val full = ptr_match && maybe_full
val do_enq = WireInit(io.enq.fire)
val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty)
for (i <- 0 until entries) {
val mask = uops(i).br_mask
val uop = uops(i)
valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, mask) && !(io.flush && flush_fn(uop))
when (valids(i)) {
uops(i).br_mask := GetNewBrMask(io.brupdate, mask)
}
}
when (do_enq) {
ram(enq_ptr.value) := io.enq.bits
valids(enq_ptr.value) := true.B //!IsKilledByBranch(io.brupdate, io.enq.bits.uop)
uops(enq_ptr.value) := io.enq.bits.uop
uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)
enq_ptr.inc()
}
when (do_deq) {
valids(deq_ptr.value) := false.B
deq_ptr.inc()
}
when (do_enq =/= do_deq) {
maybe_full := do_enq
}
io.enq.ready := !full
val out = Wire(gen)
out := ram(deq_ptr.value)
out.uop := uops(deq_ptr.value)
io.deq.valid := !io.empty && valids(deq_ptr.value) && !IsKilledByBranch(io.brupdate, out.uop) && !(io.flush && flush_fn(out.uop))
io.deq.bits := out
io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, out.uop)
// For flow queue behavior.
if (flow) {
when (io.empty) {
io.deq.valid := io.enq.valid //&& !IsKilledByBranch(io.brupdate, io.enq.bits.uop)
io.deq.bits := io.enq.bits
io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)
do_deq := false.B
when (io.deq.ready) { do_enq := false.B }
}
}
private val ptr_diff = enq_ptr.value - deq_ptr.value
if (isPow2(entries)) {
io.count := Cat(maybe_full && ptr_match, ptr_diff)
}
else {
io.count := Mux(ptr_match,
Mux(maybe_full,
entries.asUInt, 0.U),
Mux(deq_ptr.value > enq_ptr.value,
entries.asUInt + ptr_diff, ptr_diff))
}
}
// ------------------------------------------
// Printf helper functions
// ------------------------------------------
object BoolToChar
{
/**
* Take in a Chisel Bool and convert it into a Str
* based on the Chars given
*
* @param c_bool Chisel Bool
* @param trueChar Scala Char if bool is true
* @param falseChar Scala Char if bool is false
* @return UInt ASCII Char for "trueChar" or "falseChar"
*/
def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = {
Mux(c_bool, Str(trueChar), Str(falseChar))
}
}
object CfiTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param cfi_type specific cfi type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(cfi_type: UInt) = {
val strings = Seq("----", "BR ", "JAL ", "JALR")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(cfi_type)
}
}
object BpdTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param bpd_type specific bpd type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(bpd_type: UInt) = {
val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(bpd_type)
}
}
object RobTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param rob_type specific rob type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(rob_type: UInt) = {
val strings = Seq("RST", "NML", "RBK", " WT")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(rob_type)
}
}
object XRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param xreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(xreg: UInt) = {
val strings = Seq(" x0", " ra", " sp", " gp",
" tp", " t0", " t1", " t2",
" s0", " s1", " a0", " a1",
" a2", " a3", " a4", " a5",
" a6", " a7", " s2", " s3",
" s4", " s5", " s6", " s7",
" s8", " s9", "s10", "s11",
" t3", " t4", " t5", " t6")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(xreg)
}
}
object FPRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param fpreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(fpreg: UInt) = {
val strings = Seq(" ft0", " ft1", " ft2", " ft3",
" ft4", " ft5", " ft6", " ft7",
" fs0", " fs1", " fa0", " fa1",
" fa2", " fa3", " fa4", " fa5",
" fa6", " fa7", " fs2", " fs3",
" fs4", " fs5", " fs6", " fs7",
" fs8", " fs9", "fs10", "fs11",
" ft8", " ft9", "ft10", "ft11")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(fpreg)
}
}
object BoomCoreStringPrefix
{
/**
* Add prefix to BOOM strings (currently only adds the hartId)
*
* @param strs list of strings
* @return String combining the list with the prefix per line
*/
def apply(strs: String*)(implicit p: Parameters) = {
val prefix = "[C" + s"${p(TileKey).tileId}" + "] "
strs.map(str => prefix + str + "\n").mkString("")
}
}
File Events.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util.log2Ceil
import freechips.rocketchip.util._
import freechips.rocketchip.util.property
class EventSet(val gate: (UInt, UInt) => Bool, val events: Seq[(String, () => Bool)]) {
def size = events.size
val hits = WireDefault(VecInit(Seq.fill(size)(false.B)))
def check(mask: UInt) = {
hits := events.map(_._2())
gate(mask, hits.asUInt)
}
def dump(): Unit = {
for (((name, _), i) <- events.zipWithIndex)
when (check(1.U << i)) { printf(s"Event $name\n") }
}
def withCovers: Unit = {
events.zipWithIndex.foreach {
case ((name, func), i) => property.cover(gate((1.U << i), (func() << i)), name)
}
}
}
class EventSets(val eventSets: Seq[EventSet]) {
def maskEventSelector(eventSel: UInt): UInt = {
// allow full associativity between counters and event sets (for now?)
val setMask = (BigInt(1) << eventSetIdBits) - 1
val maskMask = ((BigInt(1) << eventSets.map(_.size).max) - 1) << maxEventSetIdBits
eventSel & (setMask | maskMask).U
}
private def decode(counter: UInt): (UInt, UInt) = {
require(eventSets.size <= (1 << maxEventSetIdBits))
require(eventSetIdBits > 0)
(counter(eventSetIdBits-1, 0), counter >> maxEventSetIdBits)
}
def evaluate(eventSel: UInt): Bool = {
val (set, mask) = decode(eventSel)
val sets = for (e <- eventSets) yield {
require(e.hits.getWidth <= mask.getWidth, s"too many events ${e.hits.getWidth} wider than mask ${mask.getWidth}")
e check mask
}
sets(set)
}
def cover() = eventSets.foreach { _.withCovers }
private def eventSetIdBits = log2Ceil(eventSets.size)
private def maxEventSetIdBits = 8
require(eventSetIdBits <= maxEventSetIdBits)
}
class SuperscalarEventSets(val eventSets: Seq[(Seq[EventSet], (UInt, UInt) => UInt)]) {
def evaluate(eventSel: UInt): UInt = {
val (set, mask) = decode(eventSel)
val sets = for ((sets, reducer) <- eventSets) yield {
sets.map { set =>
require(set.hits.getWidth <= mask.getWidth, s"too many events ${set.hits.getWidth} wider than mask ${mask.getWidth}")
set.check(mask)
}.reduce(reducer)
}
val zeroPadded = sets.padTo(1 << eventSetIdBits, 0.U)
zeroPadded(set)
}
def toScalarEventSets: EventSets = new EventSets(eventSets.map(_._1.head))
def cover(): Unit = { eventSets.foreach(_._1.foreach(_.withCovers)) }
private def decode(counter: UInt): (UInt, UInt) = {
require(eventSets.size <= (1 << maxEventSetIdBits))
require(eventSetIdBits > 0)
(counter(eventSetIdBits-1, 0), counter >> maxEventSetIdBits)
}
private def eventSetIdBits = log2Ceil(eventSets.size)
private def maxEventSetIdBits = 8
require(eventSets.forall(s => s._1.forall(_.size == s._1.head.size)))
require(eventSetIdBits <= maxEventSetIdBits)
}
File consts.scala:
//******************************************************************************
// Copyright (c) 2011 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// RISCV Processor Constants
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v3.common.constants
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util.Str
import freechips.rocketchip.rocket.RVCExpander
/**
* Mixin for issue queue types
*/
trait IQType
{
val IQT_SZ = 3
val IQT_INT = 1.U(IQT_SZ.W)
val IQT_MEM = 2.U(IQT_SZ.W)
val IQT_FP = 4.U(IQT_SZ.W)
val IQT_MFP = 6.U(IQT_SZ.W)
}
/**
* Mixin for scalar operation constants
*/
trait ScalarOpConstants
{
val X = BitPat("b?")
val Y = BitPat("b1")
val N = BitPat("b0")
//************************************
// Extra Constants
// Which branch predictor predicted us
val BSRC_SZ = 2
val BSRC_1 = 0.U(BSRC_SZ.W) // 1-cycle branch pred
val BSRC_2 = 1.U(BSRC_SZ.W) // 2-cycle branch pred
val BSRC_3 = 2.U(BSRC_SZ.W) // 3-cycle branch pred
val BSRC_C = 3.U(BSRC_SZ.W) // core branch resolution
//************************************
// Control Signals
// CFI types
val CFI_SZ = 3
val CFI_X = 0.U(CFI_SZ.W) // Not a CFI instruction
val CFI_BR = 1.U(CFI_SZ.W) // Branch
val CFI_JAL = 2.U(CFI_SZ.W) // JAL
val CFI_JALR = 3.U(CFI_SZ.W) // JALR
// PC Select Signal
val PC_PLUS4 = 0.U(2.W) // PC + 4
val PC_BRJMP = 1.U(2.W) // brjmp_target
val PC_JALR = 2.U(2.W) // jump_reg_target
// Branch Type
val BR_N = 0.U(4.W) // Next
val BR_NE = 1.U(4.W) // Branch on NotEqual
val BR_EQ = 2.U(4.W) // Branch on Equal
val BR_GE = 3.U(4.W) // Branch on Greater/Equal
val BR_GEU = 4.U(4.W) // Branch on Greater/Equal Unsigned
val BR_LT = 5.U(4.W) // Branch on Less Than
val BR_LTU = 6.U(4.W) // Branch on Less Than Unsigned
val BR_J = 7.U(4.W) // Jump
val BR_JR = 8.U(4.W) // Jump Register
// RS1 Operand Select Signal
val OP1_RS1 = 0.U(2.W) // Register Source #1
val OP1_ZERO= 1.U(2.W)
val OP1_PC = 2.U(2.W)
val OP1_X = BitPat("b??")
// RS2 Operand Select Signal
val OP2_RS2 = 0.U(3.W) // Register Source #2
val OP2_IMM = 1.U(3.W) // immediate
val OP2_ZERO= 2.U(3.W) // constant 0
val OP2_NEXT= 3.U(3.W) // constant 2/4 (for PC+2/4)
val OP2_IMMC= 4.U(3.W) // for CSR imm found in RS1
val OP2_X = BitPat("b???")
// Register File Write Enable Signal
val REN_0 = false.B
val REN_1 = true.B
// Is 32b Word or 64b Doubldword?
val SZ_DW = 1
val DW_X = true.B // Bool(xLen==64)
val DW_32 = false.B
val DW_64 = true.B
val DW_XPR = true.B // Bool(xLen==64)
// Memory Enable Signal
val MEN_0 = false.B
val MEN_1 = true.B
val MEN_X = false.B
// Immediate Extend Select
val IS_I = 0.U(3.W) // I-Type (LD,ALU)
val IS_S = 1.U(3.W) // S-Type (ST)
val IS_B = 2.U(3.W) // SB-Type (BR)
val IS_U = 3.U(3.W) // U-Type (LUI/AUIPC)
val IS_J = 4.U(3.W) // UJ-Type (J/JAL)
val IS_X = BitPat("b???")
// Decode Stage Control Signals
val RT_FIX = 0.U(2.W)
val RT_FLT = 1.U(2.W)
val RT_PAS = 3.U(2.W) // pass-through (prs1 := lrs1, etc)
val RT_X = 2.U(2.W) // not-a-register (but shouldn't get a busy-bit, etc.)
// TODO rename RT_NAR
// Micro-op opcodes
// TODO change micro-op opcodes into using enum
val UOPC_SZ = 7
val uopX = BitPat.dontCare(UOPC_SZ)
val uopNOP = 0.U(UOPC_SZ.W)
val uopLD = 1.U(UOPC_SZ.W)
val uopSTA = 2.U(UOPC_SZ.W) // store address generation
val uopSTD = 3.U(UOPC_SZ.W) // store data generation
val uopLUI = 4.U(UOPC_SZ.W)
val uopADDI = 5.U(UOPC_SZ.W)
val uopANDI = 6.U(UOPC_SZ.W)
val uopORI = 7.U(UOPC_SZ.W)
val uopXORI = 8.U(UOPC_SZ.W)
val uopSLTI = 9.U(UOPC_SZ.W)
val uopSLTIU= 10.U(UOPC_SZ.W)
val uopSLLI = 11.U(UOPC_SZ.W)
val uopSRAI = 12.U(UOPC_SZ.W)
val uopSRLI = 13.U(UOPC_SZ.W)
val uopSLL = 14.U(UOPC_SZ.W)
val uopADD = 15.U(UOPC_SZ.W)
val uopSUB = 16.U(UOPC_SZ.W)
val uopSLT = 17.U(UOPC_SZ.W)
val uopSLTU = 18.U(UOPC_SZ.W)
val uopAND = 19.U(UOPC_SZ.W)
val uopOR = 20.U(UOPC_SZ.W)
val uopXOR = 21.U(UOPC_SZ.W)
val uopSRA = 22.U(UOPC_SZ.W)
val uopSRL = 23.U(UOPC_SZ.W)
val uopBEQ = 24.U(UOPC_SZ.W)
val uopBNE = 25.U(UOPC_SZ.W)
val uopBGE = 26.U(UOPC_SZ.W)
val uopBGEU = 27.U(UOPC_SZ.W)
val uopBLT = 28.U(UOPC_SZ.W)
val uopBLTU = 29.U(UOPC_SZ.W)
val uopCSRRW= 30.U(UOPC_SZ.W)
val uopCSRRS= 31.U(UOPC_SZ.W)
val uopCSRRC= 32.U(UOPC_SZ.W)
val uopCSRRWI=33.U(UOPC_SZ.W)
val uopCSRRSI=34.U(UOPC_SZ.W)
val uopCSRRCI=35.U(UOPC_SZ.W)
val uopJ = 36.U(UOPC_SZ.W)
val uopJAL = 37.U(UOPC_SZ.W)
val uopJALR = 38.U(UOPC_SZ.W)
val uopAUIPC= 39.U(UOPC_SZ.W)
//val uopSRET = 40.U(UOPC_SZ.W)
val uopCFLSH= 41.U(UOPC_SZ.W)
val uopFENCE= 42.U(UOPC_SZ.W)
val uopADDIW= 43.U(UOPC_SZ.W)
val uopADDW = 44.U(UOPC_SZ.W)
val uopSUBW = 45.U(UOPC_SZ.W)
val uopSLLIW= 46.U(UOPC_SZ.W)
val uopSLLW = 47.U(UOPC_SZ.W)
val uopSRAIW= 48.U(UOPC_SZ.W)
val uopSRAW = 49.U(UOPC_SZ.W)
val uopSRLIW= 50.U(UOPC_SZ.W)
val uopSRLW = 51.U(UOPC_SZ.W)
val uopMUL = 52.U(UOPC_SZ.W)
val uopMULH = 53.U(UOPC_SZ.W)
val uopMULHU= 54.U(UOPC_SZ.W)
val uopMULHSU=55.U(UOPC_SZ.W)
val uopMULW = 56.U(UOPC_SZ.W)
val uopDIV = 57.U(UOPC_SZ.W)
val uopDIVU = 58.U(UOPC_SZ.W)
val uopREM = 59.U(UOPC_SZ.W)
val uopREMU = 60.U(UOPC_SZ.W)
val uopDIVW = 61.U(UOPC_SZ.W)
val uopDIVUW= 62.U(UOPC_SZ.W)
val uopREMW = 63.U(UOPC_SZ.W)
val uopREMUW= 64.U(UOPC_SZ.W)
val uopFENCEI = 65.U(UOPC_SZ.W)
// = 66.U(UOPC_SZ.W)
val uopAMO_AG = 67.U(UOPC_SZ.W) // AMO-address gen (use normal STD for datagen)
val uopFMV_W_X = 68.U(UOPC_SZ.W)
val uopFMV_D_X = 69.U(UOPC_SZ.W)
val uopFMV_X_W = 70.U(UOPC_SZ.W)
val uopFMV_X_D = 71.U(UOPC_SZ.W)
val uopFSGNJ_S = 72.U(UOPC_SZ.W)
val uopFSGNJ_D = 73.U(UOPC_SZ.W)
val uopFCVT_S_D = 74.U(UOPC_SZ.W)
val uopFCVT_D_S = 75.U(UOPC_SZ.W)
val uopFCVT_S_X = 76.U(UOPC_SZ.W)
val uopFCVT_D_X = 77.U(UOPC_SZ.W)
val uopFCVT_X_S = 78.U(UOPC_SZ.W)
val uopFCVT_X_D = 79.U(UOPC_SZ.W)
val uopCMPR_S = 80.U(UOPC_SZ.W)
val uopCMPR_D = 81.U(UOPC_SZ.W)
val uopFCLASS_S = 82.U(UOPC_SZ.W)
val uopFCLASS_D = 83.U(UOPC_SZ.W)
val uopFMINMAX_S = 84.U(UOPC_SZ.W)
val uopFMINMAX_D = 85.U(UOPC_SZ.W)
// = 86.U(UOPC_SZ.W)
val uopFADD_S = 87.U(UOPC_SZ.W)
val uopFSUB_S = 88.U(UOPC_SZ.W)
val uopFMUL_S = 89.U(UOPC_SZ.W)
val uopFADD_D = 90.U(UOPC_SZ.W)
val uopFSUB_D = 91.U(UOPC_SZ.W)
val uopFMUL_D = 92.U(UOPC_SZ.W)
val uopFMADD_S = 93.U(UOPC_SZ.W)
val uopFMSUB_S = 94.U(UOPC_SZ.W)
val uopFNMADD_S = 95.U(UOPC_SZ.W)
val uopFNMSUB_S = 96.U(UOPC_SZ.W)
val uopFMADD_D = 97.U(UOPC_SZ.W)
val uopFMSUB_D = 98.U(UOPC_SZ.W)
val uopFNMADD_D = 99.U(UOPC_SZ.W)
val uopFNMSUB_D = 100.U(UOPC_SZ.W)
val uopFDIV_S = 101.U(UOPC_SZ.W)
val uopFDIV_D = 102.U(UOPC_SZ.W)
val uopFSQRT_S = 103.U(UOPC_SZ.W)
val uopFSQRT_D = 104.U(UOPC_SZ.W)
val uopWFI = 105.U(UOPC_SZ.W) // pass uop down the CSR pipeline
val uopERET = 106.U(UOPC_SZ.W) // pass uop down the CSR pipeline, also is ERET
val uopSFENCE = 107.U(UOPC_SZ.W)
val uopROCC = 108.U(UOPC_SZ.W)
val uopMOV = 109.U(UOPC_SZ.W) // conditional mov decoded from "add rd, x0, rs2"
// The Bubble Instruction (Machine generated NOP)
// Insert (XOR x0,x0,x0) which is different from software compiler
// generated NOPs which are (ADDI x0, x0, 0).
// Reasoning for this is to let visualizers and stat-trackers differentiate
// between software NOPs and machine-generated Bubbles in the pipeline.
val BUBBLE = (0x4033).U(32.W)
def NullMicroOp()(implicit p: Parameters): boom.v3.common.MicroOp = {
val uop = Wire(new boom.v3.common.MicroOp)
uop := DontCare // Overridden in the following lines
uop.uopc := uopNOP // maybe not required, but helps on asserts that try to catch spurious behavior
uop.bypassable := false.B
uop.fp_val := false.B
uop.uses_stq := false.B
uop.uses_ldq := false.B
uop.pdst := 0.U
uop.dst_rtype := RT_X
val cs = Wire(new boom.v3.common.CtrlSignals())
cs := DontCare // Overridden in the following lines
cs.br_type := BR_N
cs.csr_cmd := freechips.rocketchip.rocket.CSR.N
cs.is_load := false.B
cs.is_sta := false.B
cs.is_std := false.B
uop.ctrl := cs
uop
}
}
/**
* Mixin for RISCV constants
*/
trait RISCVConstants
{
// abstract out instruction decode magic numbers
val RD_MSB = 11
val RD_LSB = 7
val RS1_MSB = 19
val RS1_LSB = 15
val RS2_MSB = 24
val RS2_LSB = 20
val RS3_MSB = 31
val RS3_LSB = 27
val CSR_ADDR_MSB = 31
val CSR_ADDR_LSB = 20
val CSR_ADDR_SZ = 12
// location of the fifth bit in the shamt (for checking for illegal ops for SRAIW,etc.)
val SHAMT_5_BIT = 25
val LONGEST_IMM_SZ = 20
val X0 = 0.U
val RA = 1.U // return address register
// memory consistency model
// The C/C++ atomics MCM requires that two loads to the same address maintain program order.
// The Cortex A9 does NOT enforce load/load ordering (which leads to buggy behavior).
val MCM_ORDER_DEPENDENT_LOADS = true
val jal_opc = (0x6f).U
val jalr_opc = (0x67).U
def GetUop(inst: UInt): UInt = inst(6,0)
def GetRd (inst: UInt): UInt = inst(RD_MSB,RD_LSB)
def GetRs1(inst: UInt): UInt = inst(RS1_MSB,RS1_LSB)
def ExpandRVC(inst: UInt)(implicit p: Parameters): UInt = {
val rvc_exp = Module(new RVCExpander)
rvc_exp.io.in := inst
Mux(rvc_exp.io.rvc, rvc_exp.io.out.bits, inst)
}
// Note: Accepts only EXPANDED rvc instructions
def ComputeBranchTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = {
val b_imm32 = Cat(Fill(20,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W))
((pc.asSInt + b_imm32.asSInt).asSInt & (-2).S).asUInt
}
// Note: Accepts only EXPANDED rvc instructions
def ComputeJALTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = {
val j_imm32 = Cat(Fill(12,inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W))
((pc.asSInt + j_imm32.asSInt).asSInt & (-2).S).asUInt
}
// Note: Accepts only EXPANDED rvc instructions
def GetCfiType(inst: UInt)(implicit p: Parameters): UInt = {
val bdecode = Module(new boom.v3.exu.BranchDecode)
bdecode.io.inst := inst
bdecode.io.pc := 0.U
bdecode.io.out.cfi_type
}
}
/**
* Mixin for exception cause constants
*/
trait ExcCauseConstants
{
// a memory disambigious misspeculation occurred
val MINI_EXCEPTION_MEM_ORDERING = 16.U
val MINI_EXCEPTION_CSR_REPLAY = 17.U
require (!freechips.rocketchip.rocket.Causes.all.contains(16))
require (!freechips.rocketchip.rocket.Causes.all.contains(17))
}
File frontend.scala:
//******************************************************************************
// Copyright (c) 2017 - 2019, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Frontend
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v3.ifu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.rocket._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.tile._
import freechips.rocketchip.util._
import freechips.rocketchip.util.property._
import boom.v3.common._
import boom.v3.exu.{CommitExceptionSignals, BranchDecode, BrUpdateInfo, BranchDecodeSignals}
import boom.v3.util._
class FrontendResp(implicit p: Parameters) extends BoomBundle()(p) {
val pc = UInt(vaddrBitsExtended.W) // ID stage PC
val data = UInt((fetchWidth * coreInstBits).W)
val mask = UInt(fetchWidth.W)
val xcpt = new FrontendExceptions
val ghist = new GlobalHistory
// fsrc provides the prediction FROM a branch in this packet
// tsrc provides the prediction TO this packet
val fsrc = UInt(BSRC_SZ.W)
val tsrc = UInt(BSRC_SZ.W)
}
class GlobalHistory(implicit p: Parameters) extends BoomBundle()(p)
with HasBoomFrontendParameters
{
// For the dual banked case, each bank ignores the contribution of the
// last bank to the history. Thus we have to track the most recent update to the
// history in that case
val old_history = UInt(globalHistoryLength.W)
val current_saw_branch_not_taken = Bool()
val new_saw_branch_not_taken = Bool()
val new_saw_branch_taken = Bool()
val ras_idx = UInt(log2Ceil(nRasEntries).W)
def histories(bank: Int) = {
if (nBanks == 1) {
old_history
} else {
require(nBanks == 2)
if (bank == 0) {
old_history
} else {
Mux(new_saw_branch_taken , old_history << 1 | 1.U,
Mux(new_saw_branch_not_taken , old_history << 1,
old_history))
}
}
}
def ===(other: GlobalHistory): Bool = {
((old_history === other.old_history) &&
(new_saw_branch_not_taken === other.new_saw_branch_not_taken) &&
(new_saw_branch_taken === other.new_saw_branch_taken)
)
}
def =/=(other: GlobalHistory): Bool = !(this === other)
def update(branches: UInt, cfi_taken: Bool, cfi_is_br: Bool, cfi_idx: UInt,
cfi_valid: Bool, addr: UInt,
cfi_is_call: Bool, cfi_is_ret: Bool): GlobalHistory = {
val cfi_idx_fixed = cfi_idx(log2Ceil(fetchWidth)-1,0)
val cfi_idx_oh = UIntToOH(cfi_idx_fixed)
val new_history = Wire(new GlobalHistory)
val not_taken_branches = branches & Mux(cfi_valid,
MaskLower(cfi_idx_oh) & ~Mux(cfi_is_br && cfi_taken, cfi_idx_oh, 0.U(fetchWidth.W)),
~(0.U(fetchWidth.W)))
if (nBanks == 1) {
// In the single bank case every bank sees the history including the previous bank
new_history := DontCare
new_history.current_saw_branch_not_taken := false.B
val saw_not_taken_branch = not_taken_branches =/= 0.U || current_saw_branch_not_taken
new_history.old_history := Mux(cfi_is_br && cfi_taken && cfi_valid , histories(0) << 1 | 1.U,
Mux(saw_not_taken_branch , histories(0) << 1,
histories(0)))
} else {
// In the two bank case every bank ignore the history added by the previous bank
val base = histories(1)
val cfi_in_bank_0 = cfi_valid && cfi_taken && cfi_idx_fixed < bankWidth.U
val ignore_second_bank = cfi_in_bank_0 || mayNotBeDualBanked(addr)
val first_bank_saw_not_taken = not_taken_branches(bankWidth-1,0) =/= 0.U || current_saw_branch_not_taken
new_history.current_saw_branch_not_taken := false.B
when (ignore_second_bank) {
new_history.old_history := histories(1)
new_history.new_saw_branch_not_taken := first_bank_saw_not_taken
new_history.new_saw_branch_taken := cfi_is_br && cfi_in_bank_0
} .otherwise {
new_history.old_history := Mux(cfi_is_br && cfi_in_bank_0 , histories(1) << 1 | 1.U,
Mux(first_bank_saw_not_taken , histories(1) << 1,
histories(1)))
new_history.new_saw_branch_not_taken := not_taken_branches(fetchWidth-1,bankWidth) =/= 0.U
new_history.new_saw_branch_taken := cfi_valid && cfi_taken && cfi_is_br && !cfi_in_bank_0
}
}
new_history.ras_idx := Mux(cfi_valid && cfi_is_call, WrapInc(ras_idx, nRasEntries),
Mux(cfi_valid && cfi_is_ret , WrapDec(ras_idx, nRasEntries), ras_idx))
new_history
}
}
/**
* Parameters to manage a L1 Banked ICache
*/
trait HasBoomFrontendParameters extends HasL1ICacheParameters
{
// How many banks does the ICache use?
val nBanks = if (cacheParams.fetchBytes <= 8) 1 else 2
// How many bytes wide is a bank?
val bankBytes = fetchBytes/nBanks
val bankWidth = fetchWidth/nBanks
require(nBanks == 1 || nBanks == 2)
// How many "chunks"/interleavings make up a cache line?
val numChunks = cacheParams.blockBytes / bankBytes
// Which bank is the address pointing to?
def bank(addr: UInt) = if (nBanks == 2) addr(log2Ceil(bankBytes)) else 0.U
def isLastBankInBlock(addr: UInt) = {
(nBanks == 2).B && addr(blockOffBits-1, log2Ceil(bankBytes)) === (numChunks-1).U
}
def mayNotBeDualBanked(addr: UInt) = {
require(nBanks == 2)
isLastBankInBlock(addr)
}
def blockAlign(addr: UInt) = ~(~addr | (cacheParams.blockBytes-1).U)
def bankAlign(addr: UInt) = ~(~addr | (bankBytes-1).U)
def fetchIdx(addr: UInt) = addr >> log2Ceil(fetchBytes)
def nextBank(addr: UInt) = bankAlign(addr) + bankBytes.U
def nextFetch(addr: UInt) = {
if (nBanks == 1) {
bankAlign(addr) + bankBytes.U
} else {
require(nBanks == 2)
bankAlign(addr) + Mux(mayNotBeDualBanked(addr), bankBytes.U, fetchBytes.U)
}
}
def fetchMask(addr: UInt) = {
val idx = addr.extract(log2Ceil(fetchWidth)+log2Ceil(coreInstBytes)-1, log2Ceil(coreInstBytes))
if (nBanks == 1) {
((1 << fetchWidth)-1).U << idx
} else {
val shamt = idx.extract(log2Ceil(fetchWidth)-2, 0)
val end_mask = Mux(mayNotBeDualBanked(addr), Fill(fetchWidth/2, 1.U), Fill(fetchWidth, 1.U))
((1 << fetchWidth)-1).U << shamt & end_mask
}
}
def bankMask(addr: UInt) = {
val idx = addr.extract(log2Ceil(fetchWidth)+log2Ceil(coreInstBytes)-1, log2Ceil(coreInstBytes))
if (nBanks == 1) {
1.U(1.W)
} else {
Mux(mayNotBeDualBanked(addr), 1.U(2.W), 3.U(2.W))
}
}
}
/**
* Bundle passed into the FetchBuffer and used to combine multiple
* relevant signals together.
*/
class FetchBundle(implicit p: Parameters) extends BoomBundle
with HasBoomFrontendParameters
{
val pc = UInt(vaddrBitsExtended.W)
val next_pc = UInt(vaddrBitsExtended.W)
val edge_inst = Vec(nBanks, Bool()) // True if 1st instruction in this bundle is pc - 2
val insts = Vec(fetchWidth, Bits(32.W))
val exp_insts = Vec(fetchWidth, Bits(32.W))
// Information for sfb folding
// NOTE: This IS NOT equivalent to uop.pc_lob, that gets calculated in the FB
val sfbs = Vec(fetchWidth, Bool())
val sfb_masks = Vec(fetchWidth, UInt((2*fetchWidth).W))
val sfb_dests = Vec(fetchWidth, UInt((1+log2Ceil(fetchBytes)).W))
val shadowable_mask = Vec(fetchWidth, Bool())
val shadowed_mask = Vec(fetchWidth, Bool())
val cfi_idx = Valid(UInt(log2Ceil(fetchWidth).W))
val cfi_type = UInt(CFI_SZ.W)
val cfi_is_call = Bool()
val cfi_is_ret = Bool()
val cfi_npc_plus4 = Bool()
val ras_top = UInt(vaddrBitsExtended.W)
val ftq_idx = UInt(log2Ceil(ftqSz).W)
val mask = UInt(fetchWidth.W) // mark which words are valid instructions
val br_mask = UInt(fetchWidth.W)
val ghist = new GlobalHistory
val lhist = Vec(nBanks, UInt(localHistoryLength.W))
val xcpt_pf_if = Bool() // I-TLB miss (instruction fetch fault).
val xcpt_ae_if = Bool() // Access exception.
val bp_debug_if_oh= Vec(fetchWidth, Bool())
val bp_xcpt_if_oh = Vec(fetchWidth, Bool())
val end_half = Valid(UInt(16.W))
val bpd_meta = Vec(nBanks, UInt())
// Source of the prediction from this bundle
val fsrc = UInt(BSRC_SZ.W)
// Source of the prediction to this bundle
val tsrc = UInt(BSRC_SZ.W)
}
/**
* IO for the BOOM Frontend to/from the CPU
*/
class BoomFrontendIO(implicit p: Parameters) extends BoomBundle
{
// Give the backend a packet of instructions.
val fetchpacket = Flipped(new DecoupledIO(new FetchBufferResp))
// 1 for xcpt/jalr/auipc/flush
val get_pc = Flipped(Vec(2, new GetPCFromFtqIO()))
val debug_ftq_idx = Output(Vec(coreWidth, UInt(log2Ceil(ftqSz).W)))
val debug_fetch_pc = Input(Vec(coreWidth, UInt(vaddrBitsExtended.W)))
// Breakpoint info
val status = Output(new MStatus)
val bp = Output(Vec(nBreakpoints, new BP))
val mcontext = Output(UInt(coreParams.mcontextWidth.W))
val scontext = Output(UInt(coreParams.scontextWidth.W))
val sfence = Valid(new SFenceReq)
val brupdate = Output(new BrUpdateInfo)
// Redirects change the PC
val redirect_flush = Output(Bool()) // Flush and hang the frontend?
val redirect_val = Output(Bool()) // Redirect the frontend?
val redirect_pc = Output(UInt()) // Where do we redirect to?
val redirect_ftq_idx = Output(UInt()) // Which ftq entry should we reset to?
val redirect_ghist = Output(new GlobalHistory) // What are we setting as the global history?
val commit = Valid(UInt(ftqSz.W))
val flush_icache = Output(Bool())
val perf = Input(new FrontendPerfEvents)
}
/**
* Top level Frontend class
*
* @param icacheParams parameters for the icache
* @param hartid id for the hardware thread of the core
*/
class BoomFrontend(val icacheParams: ICacheParams, staticIdForMetadataUseOnly: Int)(implicit p: Parameters) extends LazyModule
{
lazy val module = new BoomFrontendModule(this)
val icache = LazyModule(new boom.v3.ifu.ICache(icacheParams, staticIdForMetadataUseOnly))
val masterNode = icache.masterNode
val resetVectorSinkNode = BundleBridgeSink[UInt](Some(() =>
UInt(masterNode.edges.out.head.bundle.addressBits.W)))
}
/**
* Bundle wrapping the IO for the Frontend as a whole
*
* @param outer top level Frontend class
*/
class BoomFrontendBundle(val outer: BoomFrontend) extends CoreBundle()(outer.p)
{
val cpu = Flipped(new BoomFrontendIO())
val ptw = new TLBPTWIO()
}
/**
* Main Frontend module that connects the icache, TLB, fetch controller,
* and branch prediction pipeline together.
*
* @param outer top level Frontend class
*/
class BoomFrontendModule(outer: BoomFrontend) extends LazyModuleImp(outer)
with HasBoomCoreParameters
with HasBoomFrontendParameters
{
val io = IO(new BoomFrontendBundle(outer))
val io_reset_vector = outer.resetVectorSinkNode.bundle
implicit val edge = outer.masterNode.edges.out(0)
require(fetchWidth*coreInstBytes == outer.icacheParams.fetchBytes)
val bpd = Module(new BranchPredictor)
bpd.io.f3_fire := false.B
val ras = Module(new BoomRAS)
val icache = outer.icache.module
icache.io.invalidate := io.cpu.flush_icache
val tlb = Module(new TLB(true, log2Ceil(fetchBytes), TLBConfig(nTLBSets, nTLBWays)))
io.ptw <> tlb.io.ptw
io.cpu.perf.tlbMiss := io.ptw.req.fire
io.cpu.perf.acquire := icache.io.perf.acquire
// --------------------------------------------------------
// **** NextPC Select (F0) ****
// Send request to ICache
// --------------------------------------------------------
val s0_vpc = WireInit(0.U(vaddrBitsExtended.W))
val s0_ghist = WireInit((0.U).asTypeOf(new GlobalHistory))
val s0_tsrc = WireInit(0.U(BSRC_SZ.W))
val s0_valid = WireInit(false.B)
val s0_is_replay = WireInit(false.B)
val s0_is_sfence = WireInit(false.B)
val s0_replay_resp = Wire(new TLBResp(log2Ceil(fetchBytes)))
val s0_replay_bpd_resp = Wire(new BranchPredictionBundle)
val s0_replay_ppc = Wire(UInt())
val s0_s1_use_f3_bpd_resp = WireInit(false.B)
when (RegNext(reset.asBool) && !reset.asBool) {
s0_valid := true.B
s0_vpc := io_reset_vector
s0_ghist := (0.U).asTypeOf(new GlobalHistory)
s0_tsrc := BSRC_C
}
icache.io.req.valid := s0_valid
icache.io.req.bits.addr := s0_vpc
bpd.io.f0_req.valid := s0_valid
bpd.io.f0_req.bits.pc := s0_vpc
bpd.io.f0_req.bits.ghist := s0_ghist
// --------------------------------------------------------
// **** ICache Access (F1) ****
// Translate VPC
// --------------------------------------------------------
val s1_vpc = RegNext(s0_vpc)
val s1_valid = RegNext(s0_valid, false.B)
val s1_ghist = RegNext(s0_ghist)
val s1_is_replay = RegNext(s0_is_replay)
val s1_is_sfence = RegNext(s0_is_sfence)
val f1_clear = WireInit(false.B)
val s1_tsrc = RegNext(s0_tsrc)
tlb.io.req.valid := (s1_valid && !s1_is_replay && !f1_clear) || s1_is_sfence
tlb.io.req.bits.cmd := DontCare
tlb.io.req.bits.vaddr := s1_vpc
tlb.io.req.bits.passthrough := false.B
tlb.io.req.bits.size := log2Ceil(coreInstBytes * fetchWidth).U
tlb.io.req.bits.v := io.ptw.status.v
tlb.io.req.bits.prv := io.ptw.status.prv
tlb.io.sfence := RegNext(io.cpu.sfence)
tlb.io.kill := false.B
val s1_tlb_miss = !s1_is_replay && tlb.io.resp.miss
val s1_tlb_resp = Mux(s1_is_replay, RegNext(s0_replay_resp), tlb.io.resp)
val s1_ppc = Mux(s1_is_replay, RegNext(s0_replay_ppc), tlb.io.resp.paddr)
val s1_bpd_resp = bpd.io.resp.f1
icache.io.s1_paddr := s1_ppc
icache.io.s1_kill := tlb.io.resp.miss || f1_clear
val f1_mask = fetchMask(s1_vpc)
val f1_redirects = (0 until fetchWidth) map { i =>
s1_valid && f1_mask(i) && s1_bpd_resp.preds(i).predicted_pc.valid &&
(s1_bpd_resp.preds(i).is_jal ||
(s1_bpd_resp.preds(i).is_br && s1_bpd_resp.preds(i).taken))
}
val f1_redirect_idx = PriorityEncoder(f1_redirects)
val f1_do_redirect = f1_redirects.reduce(_||_) && useBPD.B
val f1_targs = s1_bpd_resp.preds.map(_.predicted_pc.bits)
val f1_predicted_target = Mux(f1_do_redirect,
f1_targs(f1_redirect_idx),
nextFetch(s1_vpc))
val f1_predicted_ghist = s1_ghist.update(
s1_bpd_resp.preds.map(p => p.is_br && p.predicted_pc.valid).asUInt & f1_mask,
s1_bpd_resp.preds(f1_redirect_idx).taken && f1_do_redirect,
s1_bpd_resp.preds(f1_redirect_idx).is_br,
f1_redirect_idx,
f1_do_redirect,
s1_vpc,
false.B,
false.B)
when (s1_valid && !s1_tlb_miss) {
// Stop fetching on fault
s0_valid := !(s1_tlb_resp.ae.inst || s1_tlb_resp.pf.inst)
s0_tsrc := BSRC_1
s0_vpc := f1_predicted_target
s0_ghist := f1_predicted_ghist
s0_is_replay := false.B
}
// --------------------------------------------------------
// **** ICache Response (F2) ****
// --------------------------------------------------------
val s2_valid = RegNext(s1_valid && !f1_clear, false.B)
val s2_vpc = RegNext(s1_vpc)
val s2_ghist = Reg(new GlobalHistory)
s2_ghist := s1_ghist
val s2_ppc = RegNext(s1_ppc)
val s2_tsrc = RegNext(s1_tsrc) // tsrc provides the predictor component which provided the prediction TO this instruction
val s2_fsrc = WireInit(BSRC_1) // fsrc provides the predictor component which provided the prediction FROM this instruction
val f2_clear = WireInit(false.B)
val s2_tlb_resp = RegNext(s1_tlb_resp)
val s2_tlb_miss = RegNext(s1_tlb_miss)
val s2_is_replay = RegNext(s1_is_replay) && s2_valid
val s2_xcpt = s2_valid && (s2_tlb_resp.ae.inst || s2_tlb_resp.pf.inst) && !s2_is_replay
val f3_ready = Wire(Bool())
icache.io.s2_kill := s2_xcpt
val f2_bpd_resp = bpd.io.resp.f2
val f2_mask = fetchMask(s2_vpc)
val f2_redirects = (0 until fetchWidth) map { i =>
s2_valid && f2_mask(i) && f2_bpd_resp.preds(i).predicted_pc.valid &&
(f2_bpd_resp.preds(i).is_jal ||
(f2_bpd_resp.preds(i).is_br && f2_bpd_resp.preds(i).taken))
}
val f2_redirect_idx = PriorityEncoder(f2_redirects)
val f2_targs = f2_bpd_resp.preds.map(_.predicted_pc.bits)
val f2_do_redirect = f2_redirects.reduce(_||_) && useBPD.B
val f2_predicted_target = Mux(f2_do_redirect,
f2_targs(f2_redirect_idx),
nextFetch(s2_vpc))
val f2_predicted_ghist = s2_ghist.update(
f2_bpd_resp.preds.map(p => p.is_br && p.predicted_pc.valid).asUInt & f2_mask,
f2_bpd_resp.preds(f2_redirect_idx).taken && f2_do_redirect,
f2_bpd_resp.preds(f2_redirect_idx).is_br,
f2_redirect_idx,
f2_do_redirect,
s2_vpc,
false.B,
false.B)
val f2_correct_f1_ghist = s1_ghist =/= f2_predicted_ghist && enableGHistStallRepair.B
when ((s2_valid && !icache.io.resp.valid) ||
(s2_valid && icache.io.resp.valid && !f3_ready)) {
s0_valid := (!s2_tlb_resp.ae.inst && !s2_tlb_resp.pf.inst) || s2_is_replay || s2_tlb_miss
s0_vpc := s2_vpc
s0_is_replay := s2_valid && icache.io.resp.valid
// When this is not a replay (it queried the BPDs, we should use f3 resp in the replaying s1)
s0_s1_use_f3_bpd_resp := !s2_is_replay
s0_ghist := s2_ghist
s0_tsrc := s2_tsrc
f1_clear := true.B
} .elsewhen (s2_valid && f3_ready) {
when (s1_valid && s1_vpc === f2_predicted_target && !f2_correct_f1_ghist) {
// We trust our prediction of what the global history for the next branch should be
s2_ghist := f2_predicted_ghist
}
when ((s1_valid && (s1_vpc =/= f2_predicted_target || f2_correct_f1_ghist)) || !s1_valid) {
f1_clear := true.B
s0_valid := !((s2_tlb_resp.ae.inst || s2_tlb_resp.pf.inst) && !s2_is_replay)
s0_vpc := f2_predicted_target
s0_is_replay := false.B
s0_ghist := f2_predicted_ghist
s2_fsrc := BSRC_2
s0_tsrc := BSRC_2
}
}
s0_replay_bpd_resp := f2_bpd_resp
s0_replay_resp := s2_tlb_resp
s0_replay_ppc := s2_ppc
// --------------------------------------------------------
// **** F3 ****
// --------------------------------------------------------
val f3_clear = WireInit(false.B)
val f3 = withReset(reset.asBool || f3_clear) {
Module(new Queue(new FrontendResp, 1, pipe=true, flow=false)) }
// Queue up the bpd resp as well, incase f4 backpressures f3
// This is "flow" because the response (enq) arrives in f3, not f2
val f3_bpd_resp = withReset(reset.asBool || f3_clear) {
Module(new Queue(new BranchPredictionBundle, 1, pipe=true, flow=true)) }
val f4_ready = Wire(Bool())
f3_ready := f3.io.enq.ready
f3.io.enq.valid := (s2_valid && !f2_clear &&
(icache.io.resp.valid || ((s2_tlb_resp.ae.inst || s2_tlb_resp.pf.inst) && !s2_tlb_miss))
)
f3.io.enq.bits.pc := s2_vpc
f3.io.enq.bits.data := Mux(s2_xcpt, 0.U, icache.io.resp.bits.data)
f3.io.enq.bits.ghist := s2_ghist
f3.io.enq.bits.mask := fetchMask(s2_vpc)
f3.io.enq.bits.xcpt := s2_tlb_resp
f3.io.enq.bits.fsrc := s2_fsrc
f3.io.enq.bits.tsrc := s2_tsrc
// RAS takes a cycle to read
val ras_read_idx = RegInit(0.U(log2Ceil(nRasEntries).W))
ras.io.read_idx := ras_read_idx
when (f3.io.enq.fire) {
ras_read_idx := f3.io.enq.bits.ghist.ras_idx
ras.io.read_idx := f3.io.enq.bits.ghist.ras_idx
}
// The BPD resp comes in f3
f3_bpd_resp.io.enq.valid := f3.io.deq.valid && RegNext(f3.io.enq.ready)
f3_bpd_resp.io.enq.bits := bpd.io.resp.f3
when (f3_bpd_resp.io.enq.fire) {
bpd.io.f3_fire := true.B
}
f3.io.deq.ready := f4_ready
f3_bpd_resp.io.deq.ready := f4_ready
val f3_imemresp = f3.io.deq.bits
val f3_bank_mask = bankMask(f3_imemresp.pc)
val f3_data = f3_imemresp.data
val f3_aligned_pc = bankAlign(f3_imemresp.pc)
val f3_is_last_bank_in_block = isLastBankInBlock(f3_aligned_pc)
val f3_is_rvc = Wire(Vec(fetchWidth, Bool()))
val f3_redirects = Wire(Vec(fetchWidth, Bool()))
val f3_targs = Wire(Vec(fetchWidth, UInt(vaddrBitsExtended.W)))
val f3_cfi_types = Wire(Vec(fetchWidth, UInt(CFI_SZ.W)))
val f3_shadowed_mask = Wire(Vec(fetchWidth, Bool()))
val f3_fetch_bundle = Wire(new FetchBundle)
val f3_mask = Wire(Vec(fetchWidth, Bool()))
val f3_br_mask = Wire(Vec(fetchWidth, Bool()))
val f3_call_mask = Wire(Vec(fetchWidth, Bool()))
val f3_ret_mask = Wire(Vec(fetchWidth, Bool()))
val f3_npc_plus4_mask = Wire(Vec(fetchWidth, Bool()))
val f3_btb_mispredicts = Wire(Vec(fetchWidth, Bool()))
f3_fetch_bundle.mask := f3_mask.asUInt
f3_fetch_bundle.br_mask := f3_br_mask.asUInt
f3_fetch_bundle.pc := f3_imemresp.pc
f3_fetch_bundle.ftq_idx := 0.U // This gets assigned later
f3_fetch_bundle.xcpt_pf_if := f3_imemresp.xcpt.pf.inst
f3_fetch_bundle.xcpt_ae_if := f3_imemresp.xcpt.ae.inst
f3_fetch_bundle.fsrc := f3_imemresp.fsrc
f3_fetch_bundle.tsrc := f3_imemresp.tsrc
f3_fetch_bundle.shadowed_mask := f3_shadowed_mask
// Tracks trailing 16b of previous fetch packet
val f3_prev_half = Reg(UInt(16.W))
// Tracks if last fetchpacket contained a half-inst
val f3_prev_is_half = RegInit(false.B)
require(fetchWidth >= 4) // Logic gets kind of annoying with fetchWidth = 2
def isRVC(inst: UInt) = (inst(1,0) =/= 3.U)
var redirect_found = false.B
var bank_prev_is_half = f3_prev_is_half
var bank_prev_half = f3_prev_half
var last_inst = 0.U(16.W)
for (b <- 0 until nBanks) {
val bank_data = f3_data((b+1)*bankWidth*16-1, b*bankWidth*16)
val bank_mask = Wire(Vec(bankWidth, Bool()))
val bank_insts = Wire(Vec(bankWidth, UInt(32.W)))
for (w <- 0 until bankWidth) {
val i = (b * bankWidth) + w
val valid = Wire(Bool())
val bpu = Module(new BreakpointUnit(nBreakpoints))
bpu.io.status := io.cpu.status
bpu.io.bp := io.cpu.bp
bpu.io.ea := DontCare
bpu.io.mcontext := io.cpu.mcontext
bpu.io.scontext := io.cpu.scontext
val brsigs = Wire(new BranchDecodeSignals)
if (w == 0) {
val inst0 = Cat(bank_data(15,0), f3_prev_half)
val inst1 = bank_data(31,0)
val exp_inst0 = ExpandRVC(inst0)
val exp_inst1 = ExpandRVC(inst1)
val pc0 = (f3_aligned_pc + (i << log2Ceil(coreInstBytes)).U - 2.U)
val pc1 = (f3_aligned_pc + (i << log2Ceil(coreInstBytes)).U)
val bpd_decoder0 = Module(new BranchDecode)
bpd_decoder0.io.inst := exp_inst0
bpd_decoder0.io.pc := pc0
val bpd_decoder1 = Module(new BranchDecode)
bpd_decoder1.io.inst := exp_inst1
bpd_decoder1.io.pc := pc1
when (bank_prev_is_half) {
bank_insts(w) := inst0
f3_fetch_bundle.insts(i) := inst0
f3_fetch_bundle.exp_insts(i) := exp_inst0
bpu.io.pc := pc0
brsigs := bpd_decoder0.io.out
f3_fetch_bundle.edge_inst(b) := true.B
if (b > 0) {
val inst0b = Cat(bank_data(15,0), last_inst)
val exp_inst0b = ExpandRVC(inst0b)
val bpd_decoder0b = Module(new BranchDecode)
bpd_decoder0b.io.inst := exp_inst0b
bpd_decoder0b.io.pc := pc0
when (f3_bank_mask(b-1)) {
bank_insts(w) := inst0b
f3_fetch_bundle.insts(i) := inst0b
f3_fetch_bundle.exp_insts(i) := exp_inst0b
brsigs := bpd_decoder0b.io.out
}
}
} .otherwise {
bank_insts(w) := inst1
f3_fetch_bundle.insts(i) := inst1
f3_fetch_bundle.exp_insts(i) := exp_inst1
bpu.io.pc := pc1
brsigs := bpd_decoder1.io.out
f3_fetch_bundle.edge_inst(b) := false.B
}
valid := true.B
} else {
val inst = Wire(UInt(32.W))
val exp_inst = ExpandRVC(inst)
val pc = f3_aligned_pc + (i << log2Ceil(coreInstBytes)).U
val bpd_decoder = Module(new BranchDecode)
bpd_decoder.io.inst := exp_inst
bpd_decoder.io.pc := pc
bank_insts(w) := inst
f3_fetch_bundle.insts(i) := inst
f3_fetch_bundle.exp_insts(i) := exp_inst
bpu.io.pc := pc
brsigs := bpd_decoder.io.out
if (w == 1) {
// Need special case since 0th instruction may carry over the wrap around
inst := bank_data(47,16)
valid := bank_prev_is_half || !(bank_mask(0) && !isRVC(bank_insts(0)))
} else if (w == bankWidth - 1) {
inst := Cat(0.U(16.W), bank_data(bankWidth*16-1,(bankWidth-1)*16))
valid := !((bank_mask(w-1) && !isRVC(bank_insts(w-1))) ||
!isRVC(inst))
} else {
inst := bank_data(w*16+32-1,w*16)
valid := !(bank_mask(w-1) && !isRVC(bank_insts(w-1)))
}
}
f3_is_rvc(i) := isRVC(bank_insts(w))
bank_mask(w) := f3.io.deq.valid && f3_imemresp.mask(i) && valid && !redirect_found
f3_mask (i) := f3.io.deq.valid && f3_imemresp.mask(i) && valid && !redirect_found
f3_targs (i) := Mux(brsigs.cfi_type === CFI_JALR,
f3_bpd_resp.io.deq.bits.preds(i).predicted_pc.bits,
brsigs.target)
// Flush BTB entries for JALs if we mispredict the target
f3_btb_mispredicts(i) := (brsigs.cfi_type === CFI_JAL && valid &&
f3_bpd_resp.io.deq.bits.preds(i).predicted_pc.valid &&
(f3_bpd_resp.io.deq.bits.preds(i).predicted_pc.bits =/= brsigs.target)
)
f3_npc_plus4_mask(i) := (if (w == 0) {
!f3_is_rvc(i) && !bank_prev_is_half
} else {
!f3_is_rvc(i)
})
val offset_from_aligned_pc = (
(i << 1).U((log2Ceil(icBlockBytes)+1).W) +
brsigs.sfb_offset.bits -
Mux(bank_prev_is_half && (w == 0).B, 2.U, 0.U)
)
val lower_mask = Wire(UInt((2*fetchWidth).W))
val upper_mask = Wire(UInt((2*fetchWidth).W))
lower_mask := UIntToOH(i.U)
upper_mask := UIntToOH(offset_from_aligned_pc(log2Ceil(fetchBytes)+1,1)) << Mux(f3_is_last_bank_in_block, bankWidth.U, 0.U)
f3_fetch_bundle.sfbs(i) := (
f3_mask(i) &&
brsigs.sfb_offset.valid &&
(offset_from_aligned_pc <= Mux(f3_is_last_bank_in_block, (fetchBytes+bankBytes).U,(2*fetchBytes).U))
)
f3_fetch_bundle.sfb_masks(i) := ~MaskLower(lower_mask) & ~MaskUpper(upper_mask)
f3_fetch_bundle.shadowable_mask(i) := (!(f3_fetch_bundle.xcpt_pf_if || f3_fetch_bundle.xcpt_ae_if || bpu.io.debug_if || bpu.io.xcpt_if) &&
f3_bank_mask(b) &&
(brsigs.shadowable || !f3_mask(i)))
f3_fetch_bundle.sfb_dests(i) := offset_from_aligned_pc
// Redirect if
// 1) its a JAL/JALR (unconditional)
// 2) the BPD believes this is a branch and says we should take it
f3_redirects(i) := f3_mask(i) && (
brsigs.cfi_type === CFI_JAL || brsigs.cfi_type === CFI_JALR ||
(brsigs.cfi_type === CFI_BR && f3_bpd_resp.io.deq.bits.preds(i).taken && useBPD.B)
)
f3_br_mask(i) := f3_mask(i) && brsigs.cfi_type === CFI_BR
f3_cfi_types(i) := brsigs.cfi_type
f3_call_mask(i) := brsigs.is_call
f3_ret_mask(i) := brsigs.is_ret
f3_fetch_bundle.bp_debug_if_oh(i) := bpu.io.debug_if
f3_fetch_bundle.bp_xcpt_if_oh (i) := bpu.io.xcpt_if
redirect_found = redirect_found || f3_redirects(i)
}
last_inst = bank_insts(bankWidth-1)(15,0)
bank_prev_is_half = Mux(f3_bank_mask(b),
(!(bank_mask(bankWidth-2) && !isRVC(bank_insts(bankWidth-2))) && !isRVC(last_inst)),
bank_prev_is_half)
bank_prev_half = Mux(f3_bank_mask(b),
last_inst(15,0),
bank_prev_half)
}
f3_fetch_bundle.cfi_type := f3_cfi_types(f3_fetch_bundle.cfi_idx.bits)
f3_fetch_bundle.cfi_is_call := f3_call_mask(f3_fetch_bundle.cfi_idx.bits)
f3_fetch_bundle.cfi_is_ret := f3_ret_mask (f3_fetch_bundle.cfi_idx.bits)
f3_fetch_bundle.cfi_npc_plus4 := f3_npc_plus4_mask(f3_fetch_bundle.cfi_idx.bits)
f3_fetch_bundle.ghist := f3.io.deq.bits.ghist
f3_fetch_bundle.lhist := f3_bpd_resp.io.deq.bits.lhist
f3_fetch_bundle.bpd_meta := f3_bpd_resp.io.deq.bits.meta
f3_fetch_bundle.end_half.valid := bank_prev_is_half
f3_fetch_bundle.end_half.bits := bank_prev_half
when (f3.io.deq.fire) {
f3_prev_is_half := bank_prev_is_half
f3_prev_half := bank_prev_half
assert(f3_bpd_resp.io.deq.bits.pc === f3_fetch_bundle.pc)
}
when (f3_clear) {
f3_prev_is_half := false.B
}
f3_fetch_bundle.cfi_idx.valid := f3_redirects.reduce(_||_)
f3_fetch_bundle.cfi_idx.bits := PriorityEncoder(f3_redirects)
f3_fetch_bundle.ras_top := ras.io.read_addr
// Redirect earlier stages only if the later stage
// can consume this packet
val f3_predicted_target = Mux(f3_redirects.reduce(_||_),
Mux(f3_fetch_bundle.cfi_is_ret && useBPD.B && useRAS.B,
ras.io.read_addr,
f3_targs(PriorityEncoder(f3_redirects))
),
nextFetch(f3_fetch_bundle.pc)
)
f3_fetch_bundle.next_pc := f3_predicted_target
val f3_predicted_ghist = f3_fetch_bundle.ghist.update(
f3_fetch_bundle.br_mask,
f3_fetch_bundle.cfi_idx.valid,
f3_fetch_bundle.br_mask(f3_fetch_bundle.cfi_idx.bits),
f3_fetch_bundle.cfi_idx.bits,
f3_fetch_bundle.cfi_idx.valid,
f3_fetch_bundle.pc,
f3_fetch_bundle.cfi_is_call,
f3_fetch_bundle.cfi_is_ret
)
ras.io.write_valid := false.B
ras.io.write_addr := f3_aligned_pc + (f3_fetch_bundle.cfi_idx.bits << 1) + Mux(
f3_fetch_bundle.cfi_npc_plus4, 4.U, 2.U)
ras.io.write_idx := WrapInc(f3_fetch_bundle.ghist.ras_idx, nRasEntries)
val f3_correct_f1_ghist = s1_ghist =/= f3_predicted_ghist && enableGHistStallRepair.B
val f3_correct_f2_ghist = s2_ghist =/= f3_predicted_ghist && enableGHistStallRepair.B
when (f3.io.deq.valid && f4_ready) {
when (f3_fetch_bundle.cfi_is_call && f3_fetch_bundle.cfi_idx.valid) {
ras.io.write_valid := true.B
}
when (f3_redirects.reduce(_||_)) {
f3_prev_is_half := false.B
}
when (s2_valid && s2_vpc === f3_predicted_target && !f3_correct_f2_ghist) {
f3.io.enq.bits.ghist := f3_predicted_ghist
} .elsewhen (!s2_valid && s1_valid && s1_vpc === f3_predicted_target && !f3_correct_f1_ghist) {
s2_ghist := f3_predicted_ghist
} .elsewhen (( s2_valid && (s2_vpc =/= f3_predicted_target || f3_correct_f2_ghist)) ||
(!s2_valid && s1_valid && (s1_vpc =/= f3_predicted_target || f3_correct_f1_ghist)) ||
(!s2_valid && !s1_valid)) {
f2_clear := true.B
f1_clear := true.B
s0_valid := !(f3_fetch_bundle.xcpt_pf_if || f3_fetch_bundle.xcpt_ae_if)
s0_vpc := f3_predicted_target
s0_is_replay := false.B
s0_ghist := f3_predicted_ghist
s0_tsrc := BSRC_3
f3_fetch_bundle.fsrc := BSRC_3
}
}
// When f3 finds a btb mispredict, queue up a bpd correction update
val f4_btb_corrections = Module(new Queue(new BranchPredictionUpdate, 2))
f4_btb_corrections.io.enq.valid := f3.io.deq.fire && f3_btb_mispredicts.reduce(_||_) && enableBTBFastRepair.B
f4_btb_corrections.io.enq.bits := DontCare
f4_btb_corrections.io.enq.bits.is_mispredict_update := false.B
f4_btb_corrections.io.enq.bits.is_repair_update := false.B
f4_btb_corrections.io.enq.bits.btb_mispredicts := f3_btb_mispredicts.asUInt
f4_btb_corrections.io.enq.bits.pc := f3_fetch_bundle.pc
f4_btb_corrections.io.enq.bits.ghist := f3_fetch_bundle.ghist
f4_btb_corrections.io.enq.bits.lhist := f3_fetch_bundle.lhist
f4_btb_corrections.io.enq.bits.meta := f3_fetch_bundle.bpd_meta
// -------------------------------------------------------
// **** F4 ****
// -------------------------------------------------------
val f4_clear = WireInit(false.B)
val f4 = withReset(reset.asBool || f4_clear) {
Module(new Queue(new FetchBundle, 1, pipe=true, flow=false))}
val fb = Module(new FetchBuffer)
val ftq = Module(new FetchTargetQueue)
// When we mispredict, we need to repair
// Deal with sfbs
val f4_shadowable_masks = VecInit((0 until fetchWidth) map { i =>
f4.io.deq.bits.shadowable_mask.asUInt |
~f4.io.deq.bits.sfb_masks(i)(fetchWidth-1,0)
})
val f3_shadowable_masks = VecInit((0 until fetchWidth) map { i =>
Mux(f4.io.enq.valid, f4.io.enq.bits.shadowable_mask.asUInt, 0.U) |
~f4.io.deq.bits.sfb_masks(i)(2*fetchWidth-1,fetchWidth)
})
val f4_sfbs = VecInit((0 until fetchWidth) map { i =>
enableSFBOpt.B &&
((~f4_shadowable_masks(i) === 0.U) &&
(~f3_shadowable_masks(i) === 0.U) &&
f4.io.deq.bits.sfbs(i) &&
!(f4.io.deq.bits.cfi_idx.valid && f4.io.deq.bits.cfi_idx.bits === i.U) &&
Mux(f4.io.deq.bits.sfb_dests(i) === 0.U,
!bank_prev_is_half,
Mux(f4.io.deq.bits.sfb_dests(i) === fetchBytes.U,
!f4.io.deq.bits.end_half.valid,
true.B)
)
)
})
val f4_sfb_valid = f4_sfbs.reduce(_||_) && f4.io.deq.valid
val f4_sfb_idx = PriorityEncoder(f4_sfbs)
val f4_sfb_mask = f4.io.deq.bits.sfb_masks(f4_sfb_idx)
// If we have a SFB, wait for next fetch to be available in f3
val f4_delay = (
f4.io.deq.bits.sfbs.reduce(_||_) &&
!f4.io.deq.bits.cfi_idx.valid &&
!f4.io.enq.valid &&
!f4.io.deq.bits.xcpt_pf_if &&
!f4.io.deq.bits.xcpt_ae_if
)
when (f4_sfb_valid) {
f3_shadowed_mask := f4_sfb_mask(2*fetchWidth-1,fetchWidth).asBools
} .otherwise {
f3_shadowed_mask := VecInit(0.U(fetchWidth.W).asBools)
}
f4_ready := f4.io.enq.ready
f4.io.enq.valid := f3.io.deq.valid && !f3_clear
f4.io.enq.bits := f3_fetch_bundle
f4.io.deq.ready := fb.io.enq.ready && ftq.io.enq.ready && !f4_delay
fb.io.enq.valid := f4.io.deq.valid && ftq.io.enq.ready && !f4_delay
fb.io.enq.bits := f4.io.deq.bits
fb.io.enq.bits.ftq_idx := ftq.io.enq_idx
fb.io.enq.bits.sfbs := Mux(f4_sfb_valid, UIntToOH(f4_sfb_idx), 0.U(fetchWidth.W)).asBools
fb.io.enq.bits.shadowed_mask := (
Mux(f4_sfb_valid, f4_sfb_mask(fetchWidth-1,0), 0.U(fetchWidth.W)) |
f4.io.deq.bits.shadowed_mask.asUInt
).asBools
ftq.io.enq.valid := f4.io.deq.valid && fb.io.enq.ready && !f4_delay
ftq.io.enq.bits := f4.io.deq.bits
val bpd_update_arbiter = Module(new Arbiter(new BranchPredictionUpdate, 2))
bpd_update_arbiter.io.in(0).valid := ftq.io.bpdupdate.valid
bpd_update_arbiter.io.in(0).bits := ftq.io.bpdupdate.bits
assert(bpd_update_arbiter.io.in(0).ready)
bpd_update_arbiter.io.in(1) <> f4_btb_corrections.io.deq
bpd.io.update := bpd_update_arbiter.io.out
bpd_update_arbiter.io.out.ready := true.B
when (ftq.io.ras_update && enableRasTopRepair.B) {
ras.io.write_valid := true.B
ras.io.write_idx := ftq.io.ras_update_idx
ras.io.write_addr := ftq.io.ras_update_pc
}
// -------------------------------------------------------
// **** To Core (F5) ****
// -------------------------------------------------------
io.cpu.fetchpacket <> fb.io.deq
io.cpu.get_pc <> ftq.io.get_ftq_pc
ftq.io.deq := io.cpu.commit
ftq.io.brupdate := io.cpu.brupdate
ftq.io.redirect.valid := io.cpu.redirect_val
ftq.io.redirect.bits := io.cpu.redirect_ftq_idx
fb.io.clear := false.B
when (io.cpu.sfence.valid) {
fb.io.clear := true.B
f4_clear := true.B
f3_clear := true.B
f2_clear := true.B
f1_clear := true.B
s0_valid := false.B
s0_vpc := io.cpu.sfence.bits.addr
s0_is_replay := false.B
s0_is_sfence := true.B
}.elsewhen (io.cpu.redirect_flush) {
fb.io.clear := true.B
f4_clear := true.B
f3_clear := true.B
f2_clear := true.B
f1_clear := true.B
f3_prev_is_half := false.B
s0_valid := io.cpu.redirect_val
s0_vpc := io.cpu.redirect_pc
s0_ghist := io.cpu.redirect_ghist
s0_tsrc := BSRC_C
s0_is_replay := false.B
ftq.io.redirect.valid := io.cpu.redirect_val
ftq.io.redirect.bits := io.cpu.redirect_ftq_idx
}
ftq.io.debug_ftq_idx := io.cpu.debug_ftq_idx
io.cpu.debug_fetch_pc := ftq.io.debug_fetch_pc
override def toString: String =
(BoomCoreStringPrefix("====Overall Frontend Params====") + "\n"
+ icache.toString + bpd.toString)
}
File regfile.scala:
//******************************************************************************
// Copyright (c) 2013 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Register File (Abstract class and Synthesizable RegFile)
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v3.exu
import scala.collection.mutable.ArrayBuffer
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import boom.v3.common._
import boom.v3.util.{BoomCoreStringPrefix}
/**
* IO bundle for a register read port
*
* @param addrWidth size of register address in bits
* @param dataWidth size of register in bits
*/
class RegisterFileReadPortIO(val addrWidth: Int, val dataWidth: Int)(implicit p: Parameters) extends BoomBundle
{
val addr = Input(UInt(addrWidth.W))
val data = Output(UInt(dataWidth.W))
}
/**
* IO bundle for the register write port
*
* @param addrWidth size of register address in bits
* @param dataWidth size of register in bits
*/
class RegisterFileWritePort(val addrWidth: Int, val dataWidth: Int)(implicit p: Parameters) extends BoomBundle
{
val addr = UInt(addrWidth.W)
val data = UInt(dataWidth.W)
}
/**
* Utility function to turn ExeUnitResps to match the regfile's WritePort I/Os.
*/
object WritePort
{
def apply(enq: DecoupledIO[ExeUnitResp], addrWidth: Int, dataWidth: Int, rtype: UInt)
(implicit p: Parameters): Valid[RegisterFileWritePort] = {
val wport = Wire(Valid(new RegisterFileWritePort(addrWidth, dataWidth)))
wport.valid := enq.valid && enq.bits.uop.dst_rtype === rtype
wport.bits.addr := enq.bits.uop.pdst
wport.bits.data := enq.bits.data
enq.ready := true.B
wport
}
}
/**
* Register file abstract class
*
* @param numRegisters number of registers
* @param numReadPorts number of read ports
* @param numWritePorts number of write ports
* @param registerWidth size of registers in bits
* @param bypassableArray list of write ports from func units to the read port of the regfile
*/
abstract class RegisterFile(
numRegisters: Int,
numReadPorts: Int,
numWritePorts: Int,
registerWidth: Int,
bypassableArray: Seq[Boolean]) // which write ports can be bypassed to the read ports?
(implicit p: Parameters) extends BoomModule
{
val io = IO(new BoomBundle {
val read_ports = Vec(numReadPorts, new RegisterFileReadPortIO(maxPregSz, registerWidth))
val write_ports = Flipped(Vec(numWritePorts, Valid(new RegisterFileWritePort(maxPregSz, registerWidth))))
})
private val rf_cost = (numReadPorts + numWritePorts) * (numReadPorts + 2*numWritePorts)
private val type_str = if (registerWidth == fLen+1) "Floating Point" else "Integer"
override def toString: String = BoomCoreStringPrefix(
"==" + type_str + " Regfile==",
"Num RF Read Ports : " + numReadPorts,
"Num RF Write Ports : " + numWritePorts,
"RF Cost (R+W)*(R+2W) : " + rf_cost,
"Bypassable Units : " + bypassableArray)
}
/**
* A synthesizable model of a Register File. You will likely want to blackbox this for more than modest port counts.
*
* @param numRegisters number of registers
* @param numReadPorts number of read ports
* @param numWritePorts number of write ports
* @param registerWidth size of registers in bits
* @param bypassableArray list of write ports from func units to the read port of the regfile
*/
class RegisterFileSynthesizable(
numRegisters: Int,
numReadPorts: Int,
numWritePorts: Int,
registerWidth: Int,
bypassableArray: Seq[Boolean])
(implicit p: Parameters)
extends RegisterFile(numRegisters, numReadPorts, numWritePorts, registerWidth, bypassableArray)
{
// --------------------------------------------------------------
val regfile = Mem(numRegisters, UInt(registerWidth.W))
// --------------------------------------------------------------
// Read ports.
val read_data = Wire(Vec(numReadPorts, UInt(registerWidth.W)))
// Register the read port addresses to give a full cycle to the RegisterRead Stage (if desired).
val read_addrs = io.read_ports.map(p => RegNext(p.addr))
for (i <- 0 until numReadPorts) {
read_data(i) := regfile(read_addrs(i))
}
// --------------------------------------------------------------
// Bypass out of the ALU's write ports.
// We are assuming we cannot bypass a writer to a reader within the regfile memory
// for a write that occurs at the end of cycle S1 and a read that returns data on cycle S1.
// But since these bypasses are expensive, and not all write ports need to bypass their data,
// only perform the w->r bypass on a select number of write ports.
require (bypassableArray.length == io.write_ports.length)
if (bypassableArray.reduce(_||_)) {
val bypassable_wports = ArrayBuffer[Valid[RegisterFileWritePort]]()
io.write_ports zip bypassableArray map { case (wport, b) => if (b) { bypassable_wports += wport} }
for (i <- 0 until numReadPorts) {
val bypass_ens = bypassable_wports.map(x => x.valid &&
x.bits.addr === read_addrs(i))
val bypass_data = Mux1H(VecInit(bypass_ens.toSeq), VecInit(bypassable_wports.map(_.bits.data).toSeq))
io.read_ports(i).data := Mux(bypass_ens.reduce(_|_), bypass_data, read_data(i))
}
} else {
for (i <- 0 until numReadPorts) {
io.read_ports(i).data := read_data(i)
}
}
// --------------------------------------------------------------
// Write ports.
for (wport <- io.write_ports) {
when (wport.valid) {
regfile(wport.bits.addr) := wport.bits.data
}
}
// ensure there is only 1 writer per register (unless to preg0)
if (numWritePorts > 1) {
for (i <- 0 until (numWritePorts - 1)) {
for (j <- (i + 1) until numWritePorts) {
assert(!io.write_ports(i).valid ||
!io.write_ports(j).valid ||
(io.write_ports(i).bits.addr =/= io.write_ports(j).bits.addr) ||
(io.write_ports(i).bits.addr === 0.U), // note: you only have to check one here
"[regfile] too many writers a register")
}
}
}
}
File execution-units.scala:
//******************************************************************************
// Copyright (c) 2015 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// RISC-V Constructing the Execution Units
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v3.exu
import scala.collection.mutable.{ArrayBuffer}
import chisel3._
import org.chipsalliance.cde.config.{Parameters}
import boom.v3.common._
import boom.v3.util.{BoomCoreStringPrefix}
/**
* Top level class to wrap all execution units together into a "collection"
*
* @param fpu using a FPU?
*/
class ExecutionUnits(val fpu: Boolean)(implicit val p: Parameters) extends HasBoomCoreParameters
{
val totalIssueWidth = issueParams.map(_.issueWidth).sum
//*******************************
// Instantiate the ExecutionUnits
private val exe_units = ArrayBuffer[ExecutionUnit]()
//*******************************
// Act like a collection
def length = exe_units.length
def apply(n: Int) = exe_units(n)
def map[T](f: ExecutionUnit => T) = {
exe_units.map(f)
}
def withFilter(f: ExecutionUnit => Boolean) = {
exe_units.withFilter(f)
}
def foreach[U](f: ExecutionUnit => U) = {
exe_units.foreach(f)
}
def zipWithIndex = {
exe_units.zipWithIndex
}
def indexWhere(f: ExecutionUnit => Boolean) = {
exe_units.indexWhere(f)
}
def count(f: ExecutionUnit => Boolean) = {
exe_units.count(f)
}
lazy val memory_units = {
exe_units.filter(_.hasMem)
}
lazy val alu_units = {
exe_units.filter(_.hasAlu)
}
lazy val csr_unit = {
require (exe_units.count(_.hasCSR) == 1)
exe_units.find(_.hasCSR).get
}
lazy val ifpu_unit = {
require (usingFPU)
require (exe_units.count(_.hasIfpu) == 1)
exe_units.find(_.hasIfpu).get
}
lazy val fpiu_unit = {
require (usingFPU)
require (exe_units.count(_.hasFpiu) == 1)
exe_units.find(_.hasFpiu).get
}
lazy val jmp_unit_idx = {
exe_units.indexWhere(_.hasJmpUnit)
}
lazy val rocc_unit = {
require (usingRoCC)
require (exe_units.count(_.hasRocc) == 1)
exe_units.find(_.hasRocc).get
}
if (!fpu) {
val int_width = issueParams.find(_.iqType == IQT_INT.litValue).get.issueWidth
for (w <- 0 until memWidth) {
val memExeUnit = Module(new ALUExeUnit(
hasAlu = false,
hasMem = true))
memExeUnit.io.ll_iresp.ready := DontCare
exe_units += memExeUnit
}
for (w <- 0 until int_width) {
def is_nth(n: Int): Boolean = w == ((n) % int_width)
val alu_exe_unit = Module(new ALUExeUnit(
hasJmpUnit = is_nth(0),
hasCSR = is_nth(1),
hasRocc = is_nth(1) && usingRoCC,
hasMul = is_nth(2),
hasDiv = is_nth(3),
hasIfpu = is_nth(4) && usingFPU))
exe_units += alu_exe_unit
}
} else {
val fp_width = issueParams.find(_.iqType == IQT_FP.litValue).get.issueWidth
for (w <- 0 until fp_width) {
val fpu_exe_unit = Module(new FPUExeUnit(hasFpu = true,
hasFdiv = usingFDivSqrt && (w==0),
hasFpiu = (w==0)))
exe_units += fpu_exe_unit
}
}
val exeUnitsStr = new StringBuilder
for (exe_unit <- exe_units) {
exeUnitsStr.append(exe_unit.toString)
}
override def toString: String =
(BoomCoreStringPrefix("===ExecutionUnits===") + "\n"
+ (if (!fpu) {
BoomCoreStringPrefix(
"==" + coreWidth + "-wide Machine==",
"==" + totalIssueWidth + " Issue==")
} else {
""
}) + "\n"
+ exeUnitsStr.toString)
require (exe_units.length != 0)
if (!fpu) {
// if this is for FPU units, we don't need a memory unit (or other integer units).
require (exe_units.map(_.hasMem).reduce(_|_), "Datapath is missing a memory unit.")
require (exe_units.map(_.hasMul).reduce(_|_), "Datapath is missing a multiplier.")
require (exe_units.map(_.hasDiv).reduce(_|_), "Datapath is missing a divider.")
} else {
require (exe_units.map(_.hasFpu).reduce(_|_),
"Datapath is missing a fpu (or has an fpu and shouldnt).")
}
val numIrfReaders = exe_units.count(_.readsIrf)
val numIrfReadPorts = exe_units.count(_.readsIrf) * 2
val numIrfWritePorts = exe_units.count(_.writesIrf)
val numLlIrfWritePorts = exe_units.count(_.writesLlIrf)
val numTotalBypassPorts = exe_units.withFilter(_.bypassable).map(_.numBypassStages).foldLeft(0)(_+_)
val numFrfReaders = exe_units.count(_.readsFrf)
val numFrfReadPorts = exe_units.count(_.readsFrf) * 3
val numFrfWritePorts = exe_units.count(_.writesFrf)
val numLlFrfWritePorts = exe_units.count(_.writesLlFrf)
// The mem-unit will also bypass writes to readers in the RRD stage.
// NOTE: This does NOT include the ll_wport
val bypassable_write_port_mask = exe_units.withFilter(x => x.writesIrf).map(u => u.bypassable)
}
File micro-op.scala:
//******************************************************************************
// Copyright (c) 2015 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// MicroOp
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v3.common
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import boom.v3.exu.FUConstants
/**
* Extension to BoomBundle to add a MicroOp
*/
abstract trait HasBoomUOP extends BoomBundle
{
val uop = new MicroOp()
}
/**
* MicroOp passing through the pipeline
*/
class MicroOp(implicit p: Parameters) extends BoomBundle
with freechips.rocketchip.rocket.constants.MemoryOpConstants
with freechips.rocketchip.rocket.constants.ScalarOpConstants
{
val uopc = UInt(UOPC_SZ.W) // micro-op code
val inst = UInt(32.W)
val debug_inst = UInt(32.W)
val is_rvc = Bool()
val debug_pc = UInt(coreMaxAddrBits.W)
val iq_type = UInt(IQT_SZ.W) // which issue unit do we use?
val fu_code = UInt(FUConstants.FUC_SZ.W) // which functional unit do we use?
val ctrl = new CtrlSignals
// What is the next state of this uop in the issue window? useful
// for the compacting queue.
val iw_state = UInt(2.W)
// Has operand 1 or 2 been waken speculatively by a load?
// Only integer operands are speculaively woken up,
// so we can ignore p3.
val iw_p1_poisoned = Bool()
val iw_p2_poisoned = Bool()
val is_br = Bool() // is this micro-op a (branch) vs a regular PC+4 inst?
val is_jalr = Bool() // is this a jump? (jal or jalr)
val is_jal = Bool() // is this a JAL (doesn't include JR)? used for branch unit
val is_sfb = Bool() // is this a sfb or in the shadow of a sfb
val br_mask = UInt(maxBrCount.W) // which branches are we being speculated under?
val br_tag = UInt(brTagSz.W)
// Index into FTQ to figure out our fetch PC.
val ftq_idx = UInt(log2Ceil(ftqSz).W)
// This inst straddles two fetch packets
val edge_inst = Bool()
// Low-order bits of our own PC. Combine with ftq[ftq_idx] to get PC.
// Aligned to a cache-line size, as that is the greater fetch granularity.
// TODO: Shouldn't this be aligned to fetch-width size?
val pc_lob = UInt(log2Ceil(icBlockBytes).W)
// Was this a branch that was predicted taken?
val taken = Bool()
val imm_packed = UInt(LONGEST_IMM_SZ.W) // densely pack the imm in decode...
// then translate and sign-extend in execute
val csr_addr = UInt(CSR_ADDR_SZ.W) // only used for critical path reasons in Exe
val rob_idx = UInt(robAddrSz.W)
val ldq_idx = UInt(ldqAddrSz.W)
val stq_idx = UInt(stqAddrSz.W)
val rxq_idx = UInt(log2Ceil(numRxqEntries).W)
val pdst = UInt(maxPregSz.W)
val prs1 = UInt(maxPregSz.W)
val prs2 = UInt(maxPregSz.W)
val prs3 = UInt(maxPregSz.W)
val ppred = UInt(log2Ceil(ftqSz).W)
val prs1_busy = Bool()
val prs2_busy = Bool()
val prs3_busy = Bool()
val ppred_busy = Bool()
val stale_pdst = UInt(maxPregSz.W)
val exception = Bool()
val exc_cause = UInt(xLen.W) // TODO compress this down, xlen is insanity
val bypassable = Bool() // can we bypass ALU results? (doesn't include loads, csr, etc...)
val mem_cmd = UInt(M_SZ.W) // sync primitives/cache flushes
val mem_size = UInt(2.W)
val mem_signed = Bool()
val is_fence = Bool()
val is_fencei = Bool()
val is_amo = Bool()
val uses_ldq = Bool()
val uses_stq = Bool()
val is_sys_pc2epc = Bool() // Is a ECall or Breakpoint -- both set EPC to PC.
val is_unique = Bool() // only allow this instruction in the pipeline, wait for STQ to
// drain, clear fetcha fter it (tell ROB to un-ready until empty)
val flush_on_commit = Bool() // some instructions need to flush the pipeline behind them
// Preditation
def is_sfb_br = is_br && is_sfb && enableSFBOpt.B // Does this write a predicate
def is_sfb_shadow = !is_br && is_sfb && enableSFBOpt.B // Is this predicated
val ldst_is_rs1 = Bool() // If this is set and we are predicated off, copy rs1 to dst,
// else copy rs2 to dst
// logical specifiers (only used in Decode->Rename), except rollback (ldst)
val ldst = UInt(lregSz.W)
val lrs1 = UInt(lregSz.W)
val lrs2 = UInt(lregSz.W)
val lrs3 = UInt(lregSz.W)
val ldst_val = Bool() // is there a destination? invalid for stores, rd==x0, etc.
val dst_rtype = UInt(2.W)
val lrs1_rtype = UInt(2.W)
val lrs2_rtype = UInt(2.W)
val frs3_en = Bool()
// floating point information
val fp_val = Bool() // is a floating-point instruction (F- or D-extension)?
// If it's non-ld/st it will write back exception bits to the fcsr.
val fp_single = Bool() // single-precision floating point instruction (F-extension)
// frontend exception information
val xcpt_pf_if = Bool() // I-TLB page fault.
val xcpt_ae_if = Bool() // I$ access exception.
val xcpt_ma_if = Bool() // Misaligned fetch (jal/brjumping to misaligned addr).
val bp_debug_if = Bool() // Breakpoint
val bp_xcpt_if = Bool() // Breakpoint
// What prediction structure provides the prediction FROM this op
val debug_fsrc = UInt(BSRC_SZ.W)
// What prediction structure provides the prediction TO this op
val debug_tsrc = UInt(BSRC_SZ.W)
// Do we allocate a branch tag for this?
// SFB branches don't get a mask, they get a predicate bit
def allocate_brtag = (is_br && !is_sfb) || is_jalr
// Does this register write-back
def rf_wen = dst_rtype =/= RT_X
// Is it possible for this uop to misspeculate, preventing the commit of subsequent uops?
def unsafe = uses_ldq || (uses_stq && !is_fence) || is_br || is_jalr
def fu_code_is(_fu: UInt) = (fu_code & _fu) =/= 0.U
}
/**
* Control signals within a MicroOp
*
* TODO REFACTOR this, as this should no longer be true, as bypass occurs in stage before branch resolution
*/
class CtrlSignals extends Bundle()
{
val br_type = UInt(BR_N.getWidth.W)
val op1_sel = UInt(OP1_X.getWidth.W)
val op2_sel = UInt(OP2_X.getWidth.W)
val imm_sel = UInt(IS_X.getWidth.W)
val op_fcn = UInt(freechips.rocketchip.rocket.ALU.SZ_ALU_FN.W)
val fcn_dw = Bool()
val csr_cmd = UInt(freechips.rocketchip.rocket.CSR.SZ.W)
val is_load = Bool() // will invoke TLB address lookup
val is_sta = Bool() // will invoke TLB address lookup
val is_std = Bool()
}
File CSR.scala:
// See LICENSE.SiFive for license details.
// See LICENSE.Berkeley for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util.{BitPat, Cat, Fill, Mux1H, PopCount, PriorityMux, RegEnable, UIntToOH, Valid, log2Ceil, log2Up}
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.devices.debug.DebugModuleKey
import freechips.rocketchip.tile._
import freechips.rocketchip.util._
import freechips.rocketchip.util.property
import scala.collection.mutable.LinkedHashMap
import Instructions._
import CustomInstructions._
class MStatus extends Bundle {
// not truly part of mstatus, but convenient
val debug = Bool()
val cease = Bool()
val wfi = Bool()
val isa = UInt(32.W)
val dprv = UInt(PRV.SZ.W) // effective prv for data accesses
val dv = Bool() // effective v for data accesses
val prv = UInt(PRV.SZ.W)
val v = Bool()
val sd = Bool()
val zero2 = UInt(23.W)
val mpv = Bool()
val gva = Bool()
val mbe = Bool()
val sbe = Bool()
val sxl = UInt(2.W)
val uxl = UInt(2.W)
val sd_rv32 = Bool()
val zero1 = UInt(8.W)
val tsr = Bool()
val tw = Bool()
val tvm = Bool()
val mxr = Bool()
val sum = Bool()
val mprv = Bool()
val xs = UInt(2.W)
val fs = UInt(2.W)
val mpp = UInt(2.W)
val vs = UInt(2.W)
val spp = UInt(1.W)
val mpie = Bool()
val ube = Bool()
val spie = Bool()
val upie = Bool()
val mie = Bool()
val hie = Bool()
val sie = Bool()
val uie = Bool()
}
class MNStatus extends Bundle {
val mpp = UInt(2.W)
val zero3 = UInt(3.W)
val mpv = Bool()
val zero2 = UInt(3.W)
val mie = Bool()
val zero1 = UInt(3.W)
}
class HStatus extends Bundle {
val zero6 = UInt(30.W)
val vsxl = UInt(2.W)
val zero5 = UInt(9.W)
val vtsr = Bool()
val vtw = Bool()
val vtvm = Bool()
val zero3 = UInt(2.W)
val vgein = UInt(6.W)
val zero2 = UInt(2.W)
val hu = Bool()
val spvp = Bool()
val spv = Bool()
val gva = Bool()
val vsbe = Bool()
val zero1 = UInt(5.W)
}
class DCSR extends Bundle {
val xdebugver = UInt(2.W)
val zero4 = UInt(2.W)
val zero3 = UInt(12.W)
val ebreakm = Bool()
val ebreakh = Bool()
val ebreaks = Bool()
val ebreaku = Bool()
val zero2 = Bool()
val stopcycle = Bool()
val stoptime = Bool()
val cause = UInt(3.W)
val v = Bool()
val zero1 = UInt(2.W)
val step = Bool()
val prv = UInt(PRV.SZ.W)
}
class MIP(implicit p: Parameters) extends CoreBundle()(p)
with HasCoreParameters {
val lip = Vec(coreParams.nLocalInterrupts, Bool())
val zero1 = Bool()
val debug = Bool() // keep in sync with CSR.debugIntCause
val rocc = Bool()
val sgeip = Bool()
val meip = Bool()
val vseip = Bool()
val seip = Bool()
val ueip = Bool()
val mtip = Bool()
val vstip = Bool()
val stip = Bool()
val utip = Bool()
val msip = Bool()
val vssip = Bool()
val ssip = Bool()
val usip = Bool()
}
class Envcfg extends Bundle {
val stce = Bool() // only for menvcfg/henvcfg
val pbmte = Bool() // only for menvcfg/henvcfg
val zero54 = UInt(54.W)
val cbze = Bool()
val cbcfe = Bool()
val cbie = UInt(2.W)
val zero3 = UInt(3.W)
val fiom = Bool()
def write(wdata: UInt) {
val new_envcfg = wdata.asTypeOf(new Envcfg)
fiom := new_envcfg.fiom // only FIOM is writable currently
}
}
class PTBR(implicit p: Parameters) extends CoreBundle()(p) {
def additionalPgLevels = mode.extract(log2Ceil(pgLevels-minPgLevels+1)-1, 0)
def pgLevelsToMode(i: Int) = (xLen, i) match {
case (32, 2) => 1
case (64, x) if x >= 3 && x <= 6 => x + 5
}
val (modeBits, maxASIdBits) = xLen match {
case 32 => (1, 9)
case 64 => (4, 16)
}
require(modeBits + maxASIdBits + maxPAddrBits - pgIdxBits == xLen)
val mode = UInt(modeBits.W)
val asid = UInt(maxASIdBits.W)
val ppn = UInt((maxPAddrBits - pgIdxBits).W)
}
object PRV
{
val SZ = 2
val U = 0
val S = 1
val H = 2
val M = 3
}
object CSR
{
// commands
val SZ = 3
def X = BitPat.dontCare(SZ)
def N = 0.U(SZ.W)
def R = 2.U(SZ.W)
def I = 4.U(SZ.W)
def W = 5.U(SZ.W)
def S = 6.U(SZ.W)
def C = 7.U(SZ.W)
// mask a CSR cmd with a valid bit
def maskCmd(valid: Bool, cmd: UInt): UInt = {
// all commands less than CSR.I are treated by CSRFile as NOPs
cmd & ~Mux(valid, 0.U, CSR.I)
}
val ADDRSZ = 12
def modeLSB: Int = 8
def mode(addr: Int): Int = (addr >> modeLSB) % (1 << PRV.SZ)
def mode(addr: UInt): UInt = addr(modeLSB + PRV.SZ - 1, modeLSB)
def busErrorIntCause = 128
def debugIntCause = 14 // keep in sync with MIP.debug
def debugTriggerCause = {
val res = debugIntCause
require(!(Causes.all contains res))
res
}
def rnmiIntCause = 13 // NMI: Higher numbers = higher priority, must not reuse debugIntCause
def rnmiBEUCause = 12
val firstCtr = CSRs.cycle
val firstCtrH = CSRs.cycleh
val firstHPC = CSRs.hpmcounter3
val firstHPCH = CSRs.hpmcounter3h
val firstHPE = CSRs.mhpmevent3
val firstMHPC = CSRs.mhpmcounter3
val firstMHPCH = CSRs.mhpmcounter3h
val firstHPM = 3
val nCtr = 32
val nHPM = nCtr - firstHPM
val hpmWidth = 40
val maxPMPs = 16
}
class PerfCounterIO(implicit p: Parameters) extends CoreBundle
with HasCoreParameters {
val eventSel = Output(UInt(xLen.W))
val inc = Input(UInt(log2Ceil(1+retireWidth).W))
}
class TracedInstruction(implicit p: Parameters) extends CoreBundle {
val valid = Bool()
val iaddr = UInt(coreMaxAddrBits.W)
val insn = UInt(iLen.W)
val priv = UInt(3.W)
val exception = Bool()
val interrupt = Bool()
val cause = UInt(xLen.W)
val tval = UInt((coreMaxAddrBits max iLen).W)
val wdata = Option.when(traceHasWdata)(UInt((vLen max xLen).W))
}
class TraceAux extends Bundle {
val enable = Bool()
val stall = Bool()
}
class CSRDecodeIO(implicit p: Parameters) extends CoreBundle {
val inst = Input(UInt(iLen.W))
def csr_addr = (inst >> 20)(CSR.ADDRSZ-1, 0)
val fp_illegal = Output(Bool())
val vector_illegal = Output(Bool())
val fp_csr = Output(Bool())
val vector_csr = Output(Bool())
val rocc_illegal = Output(Bool())
val read_illegal = Output(Bool())
val write_illegal = Output(Bool())
val write_flush = Output(Bool())
val system_illegal = Output(Bool())
val virtual_access_illegal = Output(Bool())
val virtual_system_illegal = Output(Bool())
}
class CSRFileIO(hasBeu: Boolean)(implicit p: Parameters) extends CoreBundle
with HasCoreParameters {
val ungated_clock = Input(Clock())
val interrupts = Input(new CoreInterrupts(hasBeu))
val hartid = Input(UInt(hartIdLen.W))
val rw = new Bundle {
val addr = Input(UInt(CSR.ADDRSZ.W))
val cmd = Input(Bits(CSR.SZ.W))
val rdata = Output(Bits(xLen.W))
val wdata = Input(Bits(xLen.W))
}
val decode = Vec(decodeWidth, new CSRDecodeIO)
val csr_stall = Output(Bool()) // stall retire for wfi
val rw_stall = Output(Bool()) // stall rw, rw will have no effect while rw_stall
val eret = Output(Bool())
val singleStep = Output(Bool())
val status = Output(new MStatus())
val hstatus = Output(new HStatus())
val gstatus = Output(new MStatus())
val ptbr = Output(new PTBR())
val hgatp = Output(new PTBR())
val vsatp = Output(new PTBR())
val evec = Output(UInt(vaddrBitsExtended.W))
val exception = Input(Bool())
val retire = Input(UInt(log2Up(1+retireWidth).W))
val cause = Input(UInt(xLen.W))
val pc = Input(UInt(vaddrBitsExtended.W))
val tval = Input(UInt(vaddrBitsExtended.W))
val htval = Input(UInt(((maxSVAddrBits + 1) min xLen).W))
val mhtinst_read_pseudo = Input(Bool())
val gva = Input(Bool())
val time = Output(UInt(xLen.W))
val fcsr_rm = Output(Bits(FPConstants.RM_SZ.W))
val fcsr_flags = Flipped(Valid(Bits(FPConstants.FLAGS_SZ.W)))
val set_fs_dirty = coreParams.haveFSDirty.option(Input(Bool()))
val rocc_interrupt = Input(Bool())
val interrupt = Output(Bool())
val interrupt_cause = Output(UInt(xLen.W))
val bp = Output(Vec(nBreakpoints, new BP))
val pmp = Output(Vec(nPMPs, new PMP))
val counters = Vec(nPerfCounters, new PerfCounterIO)
val csrw_counter = Output(UInt(CSR.nCtr.W))
val inhibit_cycle = Output(Bool())
val inst = Input(Vec(retireWidth, UInt(iLen.W)))
val trace = Output(Vec(retireWidth, new TracedInstruction))
val mcontext = Output(UInt(coreParams.mcontextWidth.W))
val scontext = Output(UInt(coreParams.scontextWidth.W))
val fiom = Output(Bool())
val vector = usingVector.option(new Bundle {
val vconfig = Output(new VConfig())
val vstart = Output(UInt(maxVLMax.log2.W))
val vxrm = Output(UInt(2.W))
val set_vs_dirty = Input(Bool())
val set_vconfig = Flipped(Valid(new VConfig))
val set_vstart = Flipped(Valid(vstart))
val set_vxsat = Input(Bool())
})
}
class VConfig(implicit p: Parameters) extends CoreBundle {
val vl = UInt((maxVLMax.log2 + 1).W)
val vtype = new VType
}
object VType {
def fromUInt(that: UInt, ignore_vill: Boolean = false)(implicit p: Parameters): VType = {
val res = 0.U.asTypeOf(new VType)
val in = that.asTypeOf(res)
val vill = (in.max_vsew.U < in.vsew) || !in.lmul_ok || in.reserved =/= 0.U || in.vill
when (!vill || ignore_vill.B) {
res := in
res.vsew := in.vsew(log2Ceil(1 + in.max_vsew) - 1, 0)
}
res.reserved := 0.U
res.vill := vill
res
}
def computeVL(avl: UInt, vtype: UInt, currentVL: UInt, useCurrentVL: Bool, useMax: Bool, useZero: Bool)(implicit p: Parameters): UInt =
VType.fromUInt(vtype, true).vl(avl, currentVL, useCurrentVL, useMax, useZero)
}
class VType(implicit p: Parameters) extends CoreBundle {
val vill = Bool()
val reserved = UInt((xLen - 9).W)
val vma = Bool()
val vta = Bool()
val vsew = UInt(3.W)
val vlmul_sign = Bool()
val vlmul_mag = UInt(2.W)
def vlmul_signed: SInt = Cat(vlmul_sign, vlmul_mag).asSInt
@deprecated("use vlmul_sign, vlmul_mag, or vlmul_signed", "RVV 0.9")
def vlmul: UInt = vlmul_mag
def max_vsew = log2Ceil(eLen/8)
def max_vlmul = (1 << vlmul_mag.getWidth) - 1
def lmul_ok: Bool = Mux(this.vlmul_sign, this.vlmul_mag =/= 0.U && ~this.vlmul_mag < max_vsew.U - this.vsew, true.B)
def minVLMax: Int = ((maxVLMax / eLen) >> ((1 << vlmul_mag.getWidth) - 1)) max 1
def vlMax: UInt = (maxVLMax.U >> (this.vsew +& Cat(this.vlmul_sign, ~this.vlmul_mag))).andNot((minVLMax-1).U)
def vl(avl: UInt, currentVL: UInt, useCurrentVL: Bool, useMax: Bool, useZero: Bool): UInt = {
val atLeastMaxVLMax = useMax || Mux(useCurrentVL, currentVL >= maxVLMax.U, avl >= maxVLMax.U)
val avl_lsbs = Mux(useCurrentVL, currentVL, avl)(maxVLMax.log2 - 1, 0)
val atLeastVLMax = atLeastMaxVLMax || (avl_lsbs & (-maxVLMax.S >> (this.vsew +& Cat(this.vlmul_sign, ~this.vlmul_mag))).asUInt.andNot((minVLMax-1).U)).orR
val isZero = vill || useZero
Mux(!isZero && atLeastVLMax, vlMax, 0.U) | Mux(!isZero && !atLeastVLMax, avl_lsbs, 0.U)
}
}
class CSRFile(
perfEventSets: EventSets = new EventSets(Seq()),
customCSRs: Seq[CustomCSR] = Nil,
roccCSRs: Seq[CustomCSR] = Nil,
hasBeu: Boolean = false)(implicit p: Parameters)
extends CoreModule()(p)
with HasCoreParameters {
val io = IO(new CSRFileIO(hasBeu) {
val customCSRs = Vec(CSRFile.this.customCSRs.size, new CustomCSRIO)
val roccCSRs = Vec(CSRFile.this.roccCSRs.size, new CustomCSRIO)
})
io.rw_stall := false.B
val reset_mstatus = WireDefault(0.U.asTypeOf(new MStatus()))
reset_mstatus.mpp := PRV.M.U
reset_mstatus.prv := PRV.M.U
reset_mstatus.xs := (if (usingRoCC) 3.U else 0.U)
val reg_mstatus = RegInit(reset_mstatus)
val new_prv = WireDefault(reg_mstatus.prv)
reg_mstatus.prv := legalizePrivilege(new_prv)
val reset_dcsr = WireDefault(0.U.asTypeOf(new DCSR()))
reset_dcsr.xdebugver := 1.U
reset_dcsr.prv := PRV.M.U
val reg_dcsr = RegInit(reset_dcsr)
val (supported_interrupts, delegable_interrupts) = {
val sup = Wire(new MIP)
sup.usip := false.B
sup.ssip := usingSupervisor.B
sup.vssip := usingHypervisor.B
sup.msip := true.B
sup.utip := false.B
sup.stip := usingSupervisor.B
sup.vstip := usingHypervisor.B
sup.mtip := true.B
sup.ueip := false.B
sup.seip := usingSupervisor.B
sup.vseip := usingHypervisor.B
sup.meip := true.B
sup.sgeip := false.B
sup.rocc := usingRoCC.B
sup.debug := false.B
sup.zero1 := false.B
sup.lip foreach { _ := true.B }
val supported_high_interrupts = if (io.interrupts.buserror.nonEmpty && !usingNMI) (BigInt(1) << CSR.busErrorIntCause).U else 0.U
val del = WireDefault(sup)
del.msip := false.B
del.mtip := false.B
del.meip := false.B
(sup.asUInt | supported_high_interrupts, del.asUInt)
}
val delegable_base_exceptions = Seq(
Causes.misaligned_fetch,
Causes.fetch_page_fault,
Causes.breakpoint,
Causes.load_page_fault,
Causes.store_page_fault,
Causes.misaligned_load,
Causes.misaligned_store,
Causes.illegal_instruction,
Causes.user_ecall,
)
val delegable_hypervisor_exceptions = Seq(
Causes.virtual_supervisor_ecall,
Causes.fetch_guest_page_fault,
Causes.load_guest_page_fault,
Causes.virtual_instruction,
Causes.store_guest_page_fault,
)
val delegable_exceptions = (
delegable_base_exceptions
++ (if (usingHypervisor) delegable_hypervisor_exceptions else Seq())
).map(1 << _).sum.U
val hs_delegable_exceptions = Seq(
Causes.misaligned_fetch,
Causes.fetch_access,
Causes.illegal_instruction,
Causes.breakpoint,
Causes.misaligned_load,
Causes.load_access,
Causes.misaligned_store,
Causes.store_access,
Causes.user_ecall,
Causes.fetch_page_fault,
Causes.load_page_fault,
Causes.store_page_fault).map(1 << _).sum.U
val (hs_delegable_interrupts, mideleg_always_hs) = {
val always = WireDefault(0.U.asTypeOf(new MIP()))
always.vssip := usingHypervisor.B
always.vstip := usingHypervisor.B
always.vseip := usingHypervisor.B
val deleg = WireDefault(always)
deleg.lip.foreach { _ := usingHypervisor.B }
(deleg.asUInt, always.asUInt)
}
val reg_debug = RegInit(false.B)
val reg_dpc = Reg(UInt(vaddrBitsExtended.W))
val reg_dscratch0 = Reg(UInt(xLen.W))
val reg_dscratch1 = (p(DebugModuleKey).map(_.nDscratch).getOrElse(1) > 1).option(Reg(UInt(xLen.W)))
val reg_singleStepped = Reg(Bool())
val reg_mcontext = (coreParams.mcontextWidth > 0).option(RegInit(0.U(coreParams.mcontextWidth.W)))
val reg_scontext = (coreParams.scontextWidth > 0).option(RegInit(0.U(coreParams.scontextWidth.W)))
val reg_tselect = Reg(UInt(log2Up(nBreakpoints).W))
val reg_bp = Reg(Vec(1 << log2Up(nBreakpoints), new BP))
val reg_pmp = Reg(Vec(nPMPs, new PMPReg))
val reg_mie = Reg(UInt(xLen.W))
val (reg_mideleg, read_mideleg) = {
val reg = Reg(UInt(xLen.W))
(reg, Mux(usingSupervisor.B, reg & delegable_interrupts | mideleg_always_hs, 0.U))
}
val (reg_medeleg, read_medeleg) = {
val reg = Reg(UInt(xLen.W))
(reg, Mux(usingSupervisor.B, reg & delegable_exceptions, 0.U))
}
val reg_mip = Reg(new MIP)
val reg_mepc = Reg(UInt(vaddrBitsExtended.W))
val reg_mcause = RegInit(0.U(xLen.W))
val reg_mtval = Reg(UInt(vaddrBitsExtended.W))
val reg_mtval2 = Reg(UInt(((maxSVAddrBits + 1) min xLen).W))
val reg_mscratch = Reg(Bits(xLen.W))
val mtvecWidth = paddrBits min xLen
val reg_mtvec = mtvecInit match {
case Some(addr) => RegInit(addr.U(mtvecWidth.W))
case None => Reg(UInt(mtvecWidth.W))
}
val reset_mnstatus = WireDefault(0.U.asTypeOf(new MNStatus()))
reset_mnstatus.mpp := PRV.M.U
val reg_mnscratch = Reg(Bits(xLen.W))
val reg_mnepc = Reg(UInt(vaddrBitsExtended.W))
val reg_mncause = RegInit(0.U(xLen.W))
val reg_mnstatus = RegInit(reset_mnstatus)
val reg_rnmie = RegInit(true.B)
val nmie = reg_rnmie
val reg_menvcfg = RegInit(0.U.asTypeOf(new Envcfg))
val reg_senvcfg = RegInit(0.U.asTypeOf(new Envcfg))
val reg_henvcfg = RegInit(0.U.asTypeOf(new Envcfg))
val delegable_counters = ((BigInt(1) << (nPerfCounters + CSR.firstHPM)) - 1).U
val (reg_mcounteren, read_mcounteren) = {
val reg = Reg(UInt(32.W))
(reg, Mux(usingUser.B, reg & delegable_counters, 0.U))
}
val (reg_scounteren, read_scounteren) = {
val reg = Reg(UInt(32.W))
(reg, Mux(usingSupervisor.B, reg & delegable_counters, 0.U))
}
val (reg_hideleg, read_hideleg) = {
val reg = Reg(UInt(xLen.W))
(reg, Mux(usingHypervisor.B, reg & hs_delegable_interrupts, 0.U))
}
val (reg_hedeleg, read_hedeleg) = {
val reg = Reg(UInt(xLen.W))
(reg, Mux(usingHypervisor.B, reg & hs_delegable_exceptions, 0.U))
}
val hs_delegable_counters = delegable_counters
val (reg_hcounteren, read_hcounteren) = {
val reg = Reg(UInt(32.W))
(reg, Mux(usingHypervisor.B, reg & hs_delegable_counters, 0.U))
}
val reg_hstatus = RegInit(0.U.asTypeOf(new HStatus))
val reg_hgatp = Reg(new PTBR)
val reg_htval = Reg(reg_mtval2.cloneType)
val read_hvip = reg_mip.asUInt & hs_delegable_interrupts
val read_hie = reg_mie & hs_delegable_interrupts
val (reg_vstvec, read_vstvec) = {
val reg = Reg(UInt(vaddrBitsExtended.W))
(reg, formTVec(reg).sextTo(xLen))
}
val reg_vsstatus = Reg(new MStatus)
val reg_vsscratch = Reg(Bits(xLen.W))
val reg_vsepc = Reg(UInt(vaddrBitsExtended.W))
val reg_vscause = Reg(Bits(xLen.W))
val reg_vstval = Reg(UInt(vaddrBitsExtended.W))
val reg_vsatp = Reg(new PTBR)
val reg_sepc = Reg(UInt(vaddrBitsExtended.W))
val reg_scause = Reg(Bits(xLen.W))
val reg_stval = Reg(UInt(vaddrBitsExtended.W))
val reg_sscratch = Reg(Bits(xLen.W))
val reg_stvec = Reg(UInt((if (usingHypervisor) vaddrBitsExtended else vaddrBits).W))
val reg_satp = Reg(new PTBR)
val reg_wfi = withClock(io.ungated_clock) { RegInit(false.B) }
val reg_fflags = Reg(UInt(5.W))
val reg_frm = Reg(UInt(3.W))
val reg_vconfig = usingVector.option(Reg(new VConfig))
val reg_vstart = usingVector.option(Reg(UInt(maxVLMax.log2.W)))
val reg_vxsat = usingVector.option(Reg(Bool()))
val reg_vxrm = usingVector.option(Reg(UInt(io.vector.get.vxrm.getWidth.W)))
val reg_mtinst_read_pseudo = Reg(Bool())
val reg_htinst_read_pseudo = Reg(Bool())
// XLEN=32: 0x00002000
// XLEN=64: 0x00003000
val Seq(read_mtinst, read_htinst) = Seq(reg_mtinst_read_pseudo, reg_htinst_read_pseudo).map(r => Cat(r, (xLen == 32).option(0.U).getOrElse(r), 0.U(12.W)))
val reg_mcountinhibit = RegInit(0.U((CSR.firstHPM + nPerfCounters).W))
io.inhibit_cycle := reg_mcountinhibit(0)
val reg_instret = WideCounter(64, io.retire, inhibit = reg_mcountinhibit(2))
val reg_cycle = if (enableCommitLog) WideCounter(64, io.retire, inhibit = reg_mcountinhibit(0))
else withClock(io.ungated_clock) { WideCounter(64, !io.csr_stall, inhibit = reg_mcountinhibit(0)) }
val reg_hpmevent = io.counters.map(c => RegInit(0.U(xLen.W)))
(io.counters zip reg_hpmevent) foreach { case (c, e) => c.eventSel := e }
val reg_hpmcounter = io.counters.zipWithIndex.map { case (c, i) =>
WideCounter(CSR.hpmWidth, c.inc, reset = false, inhibit = reg_mcountinhibit(CSR.firstHPM+i)) }
val mip = WireDefault(reg_mip)
mip.lip := (io.interrupts.lip: Seq[Bool])
mip.mtip := io.interrupts.mtip
mip.msip := io.interrupts.msip
mip.meip := io.interrupts.meip
// seip is the OR of reg_mip.seip and the actual line from the PLIC
io.interrupts.seip.foreach { mip.seip := reg_mip.seip || _ }
// Simimlar sort of thing would apply if the PLIC had a VSEIP line:
//io.interrupts.vseip.foreach { mip.vseip := reg_mip.vseip || _ }
mip.rocc := io.rocc_interrupt
val read_mip = mip.asUInt & supported_interrupts
val read_hip = read_mip & hs_delegable_interrupts
val high_interrupts = (if (usingNMI) 0.U else io.interrupts.buserror.map(_ << CSR.busErrorIntCause).getOrElse(0.U))
val pending_interrupts = high_interrupts | (read_mip & reg_mie)
val d_interrupts = io.interrupts.debug << CSR.debugIntCause
val (nmi_interrupts, nmiFlag) = io.interrupts.nmi.map(nmi =>
(((nmi.rnmi && reg_rnmie) << CSR.rnmiIntCause) |
io.interrupts.buserror.map(_ << CSR.rnmiBEUCause).getOrElse(0.U),
!io.interrupts.debug && nmi.rnmi && reg_rnmie)).getOrElse(0.U, false.B)
val m_interrupts = Mux(nmie && (reg_mstatus.prv <= PRV.S.U || reg_mstatus.mie), ~(~pending_interrupts | read_mideleg), 0.U)
val s_interrupts = Mux(nmie && (reg_mstatus.v || reg_mstatus.prv < PRV.S.U || (reg_mstatus.prv === PRV.S.U && reg_mstatus.sie)), pending_interrupts & read_mideleg & ~read_hideleg, 0.U)
val vs_interrupts = Mux(nmie && (reg_mstatus.v && (reg_mstatus.prv < PRV.S.U || reg_mstatus.prv === PRV.S.U && reg_vsstatus.sie)), pending_interrupts & read_hideleg, 0.U)
val (anyInterrupt, whichInterrupt) = chooseInterrupt(Seq(vs_interrupts, s_interrupts, m_interrupts, nmi_interrupts, d_interrupts))
val interruptMSB = BigInt(1) << (xLen-1)
val interruptCause = interruptMSB.U + (nmiFlag << (xLen-2)) + whichInterrupt
io.interrupt := (anyInterrupt && !io.singleStep || reg_singleStepped) && !(reg_debug || io.status.cease)
io.interrupt_cause := interruptCause
io.bp := reg_bp take nBreakpoints
io.mcontext := reg_mcontext.getOrElse(0.U)
io.scontext := reg_scontext.getOrElse(0.U)
io.fiom := (reg_mstatus.prv < PRV.M.U && reg_menvcfg.fiom) || (reg_mstatus.prv < PRV.S.U && reg_senvcfg.fiom) || (reg_mstatus.v && reg_henvcfg.fiom)
io.pmp := reg_pmp.map(PMP(_))
val isaMaskString =
(if (usingMulDiv) "M" else "") +
(if (usingAtomics) "A" else "") +
(if (fLen >= 32) "F" else "") +
(if (fLen >= 64) "D" else "") +
(if (coreParams.hasV) "V" else "") +
(if (usingCompressed) "C" else "")
val isaString = (if (coreParams.useRVE) "E" else "I") +
isaMaskString +
(if (customIsaExt.isDefined || usingRoCC) "X" else "") +
(if (usingSupervisor) "S" else "") +
(if (usingHypervisor) "H" else "") +
(if (usingUser) "U" else "")
val isaMax = (BigInt(log2Ceil(xLen) - 4) << (xLen-2)) | isaStringToMask(isaString)
val reg_misa = RegInit(isaMax.U)
val read_mstatus = io.status.asUInt.extract(xLen-1,0)
val read_mtvec = formTVec(reg_mtvec).padTo(xLen)
val read_stvec = formTVec(reg_stvec).sextTo(xLen)
val read_mapping = LinkedHashMap[Int,Bits](
CSRs.tselect -> reg_tselect,
CSRs.tdata1 -> reg_bp(reg_tselect).control.asUInt,
CSRs.tdata2 -> reg_bp(reg_tselect).address.sextTo(xLen),
CSRs.tdata3 -> reg_bp(reg_tselect).textra.asUInt,
CSRs.misa -> reg_misa,
CSRs.mstatus -> read_mstatus,
CSRs.mtvec -> read_mtvec,
CSRs.mip -> read_mip,
CSRs.mie -> reg_mie,
CSRs.mscratch -> reg_mscratch,
CSRs.mepc -> readEPC(reg_mepc).sextTo(xLen),
CSRs.mtval -> reg_mtval.sextTo(xLen),
CSRs.mcause -> reg_mcause,
CSRs.mhartid -> io.hartid)
val debug_csrs = if (!usingDebug) LinkedHashMap() else LinkedHashMap[Int,Bits](
CSRs.dcsr -> reg_dcsr.asUInt,
CSRs.dpc -> readEPC(reg_dpc).sextTo(xLen),
CSRs.dscratch0 -> reg_dscratch0.asUInt) ++
reg_dscratch1.map(r => CSRs.dscratch1 -> r)
val read_mnstatus = WireInit(0.U.asTypeOf(new MNStatus()))
read_mnstatus.mpp := reg_mnstatus.mpp
read_mnstatus.mpv := reg_mnstatus.mpv
read_mnstatus.mie := reg_rnmie
val nmi_csrs = if (!usingNMI) LinkedHashMap() else LinkedHashMap[Int,Bits](
CustomCSRs.mnscratch -> reg_mnscratch,
CustomCSRs.mnepc -> readEPC(reg_mnepc).sextTo(xLen),
CustomCSRs.mncause -> reg_mncause,
CustomCSRs.mnstatus -> read_mnstatus.asUInt)
val context_csrs = LinkedHashMap[Int,Bits]() ++
reg_mcontext.map(r => CSRs.mcontext -> r) ++
reg_scontext.map(r => CSRs.scontext -> r)
val read_fcsr = Cat(reg_frm, reg_fflags)
val fp_csrs = LinkedHashMap[Int,Bits]() ++
usingFPU.option(CSRs.fflags -> reg_fflags) ++
usingFPU.option(CSRs.frm -> reg_frm) ++
(usingFPU || usingVector).option(CSRs.fcsr -> read_fcsr)
val read_vcsr = Cat(reg_vxrm.getOrElse(0.U), reg_vxsat.getOrElse(0.U))
val vector_csrs = if (!usingVector) LinkedHashMap() else LinkedHashMap[Int,Bits](
CSRs.vxsat -> reg_vxsat.get,
CSRs.vxrm -> reg_vxrm.get,
CSRs.vcsr -> read_vcsr,
CSRs.vstart -> reg_vstart.get,
CSRs.vtype -> reg_vconfig.get.vtype.asUInt,
CSRs.vl -> reg_vconfig.get.vl,
CSRs.vlenb -> (vLen / 8).U)
read_mapping ++= debug_csrs
read_mapping ++= nmi_csrs
read_mapping ++= context_csrs
read_mapping ++= fp_csrs
read_mapping ++= vector_csrs
if (coreParams.haveBasicCounters) {
read_mapping += CSRs.mcountinhibit -> reg_mcountinhibit
read_mapping += CSRs.mcycle -> reg_cycle
read_mapping += CSRs.minstret -> reg_instret
for (((e, c), i) <- (reg_hpmevent.padTo(CSR.nHPM, 0.U)
zip reg_hpmcounter.map(x => x: UInt).padTo(CSR.nHPM, 0.U)).zipWithIndex) {
read_mapping += (i + CSR.firstHPE) -> e // mhpmeventN
read_mapping += (i + CSR.firstMHPC) -> c // mhpmcounterN
read_mapping += (i + CSR.firstHPC) -> c // hpmcounterN
if (xLen == 32) {
read_mapping += (i + CSR.firstMHPCH) -> (c >> 32) // mhpmcounterNh
read_mapping += (i + CSR.firstHPCH) -> (c >> 32) // hpmcounterNh
}
}
if (usingUser) {
read_mapping += CSRs.mcounteren -> read_mcounteren
}
read_mapping += CSRs.cycle -> reg_cycle
read_mapping += CSRs.instret -> reg_instret
if (xLen == 32) {
read_mapping += CSRs.mcycleh -> (reg_cycle >> 32)
read_mapping += CSRs.minstreth -> (reg_instret >> 32)
read_mapping += CSRs.cycleh -> (reg_cycle >> 32)
read_mapping += CSRs.instreth -> (reg_instret >> 32)
}
}
if (usingUser) {
read_mapping += CSRs.menvcfg -> reg_menvcfg.asUInt
if (xLen == 32)
read_mapping += CSRs.menvcfgh -> (reg_menvcfg.asUInt >> 32)
}
val sie_mask = {
val sgeip_mask = WireInit(0.U.asTypeOf(new MIP))
sgeip_mask.sgeip := true.B
read_mideleg & ~(hs_delegable_interrupts | sgeip_mask.asUInt)
}
if (usingSupervisor) {
val read_sie = reg_mie & sie_mask
val read_sip = read_mip & sie_mask
val read_sstatus = WireDefault(0.U.asTypeOf(new MStatus))
read_sstatus.sd := io.status.sd
read_sstatus.uxl := io.status.uxl
read_sstatus.sd_rv32 := io.status.sd_rv32
read_sstatus.mxr := io.status.mxr
read_sstatus.sum := io.status.sum
read_sstatus.xs := io.status.xs
read_sstatus.fs := io.status.fs
read_sstatus.vs := io.status.vs
read_sstatus.spp := io.status.spp
read_sstatus.spie := io.status.spie
read_sstatus.sie := io.status.sie
read_mapping += CSRs.sstatus -> (read_sstatus.asUInt)(xLen-1,0)
read_mapping += CSRs.sip -> read_sip.asUInt
read_mapping += CSRs.sie -> read_sie.asUInt
read_mapping += CSRs.sscratch -> reg_sscratch
read_mapping += CSRs.scause -> reg_scause
read_mapping += CSRs.stval -> reg_stval.sextTo(xLen)
read_mapping += CSRs.satp -> reg_satp.asUInt
read_mapping += CSRs.sepc -> readEPC(reg_sepc).sextTo(xLen)
read_mapping += CSRs.stvec -> read_stvec
read_mapping += CSRs.scounteren -> read_scounteren
read_mapping += CSRs.mideleg -> read_mideleg
read_mapping += CSRs.medeleg -> read_medeleg
read_mapping += CSRs.senvcfg -> reg_senvcfg.asUInt
}
val pmpCfgPerCSR = xLen / new PMPConfig().getWidth
def pmpCfgIndex(i: Int) = (xLen / 32) * (i / pmpCfgPerCSR)
if (reg_pmp.nonEmpty) {
require(reg_pmp.size <= CSR.maxPMPs)
val read_pmp = reg_pmp.padTo(CSR.maxPMPs, 0.U.asTypeOf(new PMP))
for (i <- 0 until read_pmp.size by pmpCfgPerCSR)
read_mapping += (CSRs.pmpcfg0 + pmpCfgIndex(i)) -> read_pmp.map(_.cfg).slice(i, i + pmpCfgPerCSR).asUInt
for ((pmp, i) <- read_pmp.zipWithIndex)
read_mapping += (CSRs.pmpaddr0 + i) -> pmp.readAddr
}
// implementation-defined CSRs
def generateCustomCSR(csr: CustomCSR, csr_io: CustomCSRIO) = {
require(csr.mask >= 0 && csr.mask.bitLength <= xLen)
require(!read_mapping.contains(csr.id))
val reg = csr.init.map(init => RegInit(init.U(xLen.W))).getOrElse(Reg(UInt(xLen.W)))
val read = io.rw.cmd =/= CSR.N && io.rw.addr === csr.id.U
csr_io.ren := read
when (read && csr_io.stall) { io.rw_stall := true.B }
read_mapping += csr.id -> reg
reg
}
val reg_custom = customCSRs.zip(io.customCSRs).map(t => generateCustomCSR(t._1, t._2))
val reg_rocc = roccCSRs.zip(io.roccCSRs).map(t => generateCustomCSR(t._1, t._2))
if (usingHypervisor) {
read_mapping += CSRs.mtinst -> read_mtinst
read_mapping += CSRs.mtval2 -> reg_mtval2
val read_hstatus = io.hstatus.asUInt.extract(xLen-1,0)
read_mapping += CSRs.hstatus -> read_hstatus
read_mapping += CSRs.hedeleg -> read_hedeleg
read_mapping += CSRs.hideleg -> read_hideleg
read_mapping += CSRs.hcounteren-> read_hcounteren
read_mapping += CSRs.hgatp -> reg_hgatp.asUInt
read_mapping += CSRs.hip -> read_hip
read_mapping += CSRs.hie -> read_hie
read_mapping += CSRs.hvip -> read_hvip
read_mapping += CSRs.hgeie -> 0.U
read_mapping += CSRs.hgeip -> 0.U
read_mapping += CSRs.htval -> reg_htval
read_mapping += CSRs.htinst -> read_htinst
read_mapping += CSRs.henvcfg -> reg_henvcfg.asUInt
if (xLen == 32)
read_mapping += CSRs.henvcfgh -> (reg_henvcfg.asUInt >> 32)
val read_vsie = (read_hie & read_hideleg) >> 1
val read_vsip = (read_hip & read_hideleg) >> 1
val read_vsepc = readEPC(reg_vsepc).sextTo(xLen)
val read_vstval = reg_vstval.sextTo(xLen)
val read_vsstatus = io.gstatus.asUInt.extract(xLen-1,0)
read_mapping += CSRs.vsstatus -> read_vsstatus
read_mapping += CSRs.vsip -> read_vsip
read_mapping += CSRs.vsie -> read_vsie
read_mapping += CSRs.vsscratch -> reg_vsscratch
read_mapping += CSRs.vscause -> reg_vscause
read_mapping += CSRs.vstval -> read_vstval
read_mapping += CSRs.vsatp -> reg_vsatp.asUInt
read_mapping += CSRs.vsepc -> read_vsepc
read_mapping += CSRs.vstvec -> read_vstvec
}
// mimpid, marchid, mvendorid, and mconfigptr are 0 unless overridden by customCSRs
Seq(CSRs.mimpid, CSRs.marchid, CSRs.mvendorid, CSRs.mconfigptr).foreach(id => read_mapping.getOrElseUpdate(id, 0.U))
val decoded_addr = {
val addr = Cat(io.status.v, io.rw.addr)
val pats = for (((k, _), i) <- read_mapping.zipWithIndex)
yield (BitPat(k.U), (0 until read_mapping.size).map(j => BitPat((i == j).B)))
val decoded = DecodeLogic(addr, Seq.fill(read_mapping.size)(X), pats)
val unvirtualized_mapping = (for (((k, _), v) <- read_mapping zip decoded) yield k -> v.asBool).toMap
for ((k, v) <- unvirtualized_mapping) yield k -> {
val alt: Option[Bool] = CSR.mode(k) match {
// hcontext was assigned an unfortunate address; it lives where a
// hypothetical vscontext will live. Exclude them from the S/VS remapping.
// (on separate lines so scala-lint doesnt do something stupid)
case _ if k == CSRs.scontext => None
case _ if k == CSRs.hcontext => None
// When V=1, if a corresponding VS CSR exists, access it instead...
case PRV.H => unvirtualized_mapping.lift(k - (1 << CSR.modeLSB))
// ...and don't access the original S-mode version.
case PRV.S => unvirtualized_mapping.contains(k + (1 << CSR.modeLSB)).option(false.B)
case _ => None
}
alt.map(Mux(reg_mstatus.v, _, v)).getOrElse(v)
}
}
val wdata = readModifyWriteCSR(io.rw.cmd, io.rw.rdata, io.rw.wdata)
val system_insn = io.rw.cmd === CSR.I
val hlsv = Seq(HLV_B, HLV_BU, HLV_H, HLV_HU, HLV_W, HLV_WU, HLV_D, HSV_B, HSV_H, HSV_W, HSV_D, HLVX_HU, HLVX_WU)
val decode_table = Seq( ECALL-> List(Y,N,N,N,N,N,N,N,N),
EBREAK-> List(N,Y,N,N,N,N,N,N,N),
MRET-> List(N,N,Y,N,N,N,N,N,N),
CEASE-> List(N,N,N,Y,N,N,N,N,N),
WFI-> List(N,N,N,N,Y,N,N,N,N)) ++
usingDebug.option( DRET-> List(N,N,Y,N,N,N,N,N,N)) ++
usingNMI.option( MNRET-> List(N,N,Y,N,N,N,N,N,N)) ++
coreParams.haveCFlush.option(CFLUSH_D_L1-> List(N,N,N,N,N,N,N,N,N)) ++
usingSupervisor.option( SRET-> List(N,N,Y,N,N,N,N,N,N)) ++
usingVM.option( SFENCE_VMA-> List(N,N,N,N,N,Y,N,N,N)) ++
usingHypervisor.option( HFENCE_VVMA-> List(N,N,N,N,N,N,Y,N,N)) ++
usingHypervisor.option( HFENCE_GVMA-> List(N,N,N,N,N,N,N,Y,N)) ++
(if (usingHypervisor) hlsv.map(_-> List(N,N,N,N,N,N,N,N,Y)) else Seq())
val insn_call :: insn_break :: insn_ret :: insn_cease :: insn_wfi :: _ :: _ :: _ :: _ :: Nil = {
val insn = ECALL.value.U | (io.rw.addr << 20)
DecodeLogic(insn, decode_table(0)._2.map(x=>X), decode_table).map(system_insn && _.asBool)
}
for (io_dec <- io.decode) {
val addr = io_dec.inst(31, 20)
def decodeAny(m: LinkedHashMap[Int,Bits]): Bool = m.map { case(k: Int, _: Bits) => addr === k.U }.reduce(_||_)
def decodeFast(s: Seq[Int]): Bool = DecodeLogic(addr, s.map(_.U), (read_mapping -- s).keys.toList.map(_.U))
val _ :: is_break :: is_ret :: _ :: is_wfi :: is_sfence :: is_hfence_vvma :: is_hfence_gvma :: is_hlsv :: Nil =
DecodeLogic(io_dec.inst, decode_table(0)._2.map(x=>X), decode_table).map(_.asBool)
val is_counter = (addr.inRange(CSR.firstCtr.U, (CSR.firstCtr + CSR.nCtr).U) || addr.inRange(CSR.firstCtrH.U, (CSR.firstCtrH + CSR.nCtr).U))
val allow_wfi = (!usingSupervisor).B || reg_mstatus.prv > PRV.S.U || !reg_mstatus.tw && (!reg_mstatus.v || !reg_hstatus.vtw)
val allow_sfence_vma = (!usingVM).B || reg_mstatus.prv > PRV.S.U || !Mux(reg_mstatus.v, reg_hstatus.vtvm, reg_mstatus.tvm)
val allow_hfence_vvma = (!usingHypervisor).B || !reg_mstatus.v && (reg_mstatus.prv >= PRV.S.U)
val allow_hlsv = (!usingHypervisor).B || !reg_mstatus.v && (reg_mstatus.prv >= PRV.S.U || reg_hstatus.hu)
val allow_sret = (!usingSupervisor).B || reg_mstatus.prv > PRV.S.U || !Mux(reg_mstatus.v, reg_hstatus.vtsr, reg_mstatus.tsr)
val counter_addr = addr(log2Ceil(read_mcounteren.getWidth)-1, 0)
val allow_counter = (reg_mstatus.prv > PRV.S.U || read_mcounteren(counter_addr)) &&
(!usingSupervisor.B || reg_mstatus.prv >= PRV.S.U || read_scounteren(counter_addr)) &&
(!usingHypervisor.B || !reg_mstatus.v || read_hcounteren(counter_addr))
io_dec.fp_illegal := io.status.fs === 0.U || reg_mstatus.v && reg_vsstatus.fs === 0.U || !reg_misa('f'-'a')
io_dec.vector_illegal := io.status.vs === 0.U || reg_mstatus.v && reg_vsstatus.vs === 0.U || !reg_misa('v'-'a')
io_dec.fp_csr := decodeFast(fp_csrs.keys.toList)
io_dec.vector_csr := decodeFast(vector_csrs.keys.toList)
io_dec.rocc_illegal := io.status.xs === 0.U || reg_mstatus.v && reg_vsstatus.xs === 0.U || !reg_misa('x'-'a')
val csr_addr_legal = reg_mstatus.prv >= CSR.mode(addr) ||
usingHypervisor.B && !reg_mstatus.v && reg_mstatus.prv === PRV.S.U && CSR.mode(addr) === PRV.H.U
val csr_exists = decodeAny(read_mapping)
io_dec.read_illegal := !csr_addr_legal ||
!csr_exists ||
((addr === CSRs.satp.U || addr === CSRs.hgatp.U) && !allow_sfence_vma) ||
is_counter && !allow_counter ||
decodeFast(debug_csrs.keys.toList) && !reg_debug ||
decodeFast(vector_csrs.keys.toList) && io_dec.vector_illegal ||
io_dec.fp_csr && io_dec.fp_illegal
io_dec.write_illegal := addr(11,10).andR
io_dec.write_flush := {
val addr_m = addr | (PRV.M.U << CSR.modeLSB)
!(addr_m >= CSRs.mscratch.U && addr_m <= CSRs.mtval.U)
}
io_dec.system_illegal := !csr_addr_legal && !is_hlsv ||
is_wfi && !allow_wfi ||
is_ret && !allow_sret ||
is_ret && addr(10) && addr(7) && !reg_debug ||
(is_sfence || is_hfence_gvma) && !allow_sfence_vma ||
is_hfence_vvma && !allow_hfence_vvma ||
is_hlsv && !allow_hlsv
io_dec.virtual_access_illegal := reg_mstatus.v && csr_exists && (
CSR.mode(addr) === PRV.H.U ||
is_counter && read_mcounteren(counter_addr) && (!read_hcounteren(counter_addr) || !reg_mstatus.prv(0) && !read_scounteren(counter_addr)) ||
CSR.mode(addr) === PRV.S.U && !reg_mstatus.prv(0) ||
addr === CSRs.satp.U && reg_mstatus.prv(0) && reg_hstatus.vtvm)
io_dec.virtual_system_illegal := reg_mstatus.v && (
is_hfence_vvma ||
is_hfence_gvma ||
is_hlsv ||
is_wfi && (!reg_mstatus.prv(0) || !reg_mstatus.tw && reg_hstatus.vtw) ||
is_ret && CSR.mode(addr) === PRV.S.U && (!reg_mstatus.prv(0) || reg_hstatus.vtsr) ||
is_sfence && (!reg_mstatus.prv(0) || reg_hstatus.vtvm))
}
val cause =
Mux(insn_call, Causes.user_ecall.U + Mux(reg_mstatus.prv(0) && reg_mstatus.v, PRV.H.U, reg_mstatus.prv),
Mux[UInt](insn_break, Causes.breakpoint.U, io.cause))
val cause_lsbs = cause(log2Ceil(1 + CSR.busErrorIntCause)-1, 0)
val cause_deleg_lsbs = cause(log2Ceil(xLen)-1,0)
val causeIsDebugInt = cause(xLen-1) && cause_lsbs === CSR.debugIntCause.U
val causeIsDebugTrigger = !cause(xLen-1) && cause_lsbs === CSR.debugTriggerCause.U
val causeIsDebugBreak = !cause(xLen-1) && insn_break && Cat(reg_dcsr.ebreakm, reg_dcsr.ebreakh, reg_dcsr.ebreaks, reg_dcsr.ebreaku)(reg_mstatus.prv)
val trapToDebug = usingDebug.B && (reg_singleStepped || causeIsDebugInt || causeIsDebugTrigger || causeIsDebugBreak || reg_debug)
val debugEntry = p(DebugModuleKey).map(_.debugEntry).getOrElse(BigInt(0x800))
val debugException = p(DebugModuleKey).map(_.debugException).getOrElse(BigInt(0x808))
val debugTVec = Mux(reg_debug, Mux(insn_break, debugEntry.U, debugException.U), debugEntry.U)
val delegate = usingSupervisor.B && reg_mstatus.prv <= PRV.S.U && Mux(cause(xLen-1), read_mideleg(cause_deleg_lsbs), read_medeleg(cause_deleg_lsbs))
val delegateVS = reg_mstatus.v && delegate && Mux(cause(xLen-1), read_hideleg(cause_deleg_lsbs), read_hedeleg(cause_deleg_lsbs))
def mtvecBaseAlign = 2
def mtvecInterruptAlign = {
require(reg_mip.getWidth <= xLen)
log2Ceil(xLen)
}
val notDebugTVec = {
val base = Mux(delegate, Mux(delegateVS, read_vstvec, read_stvec), read_mtvec)
val interruptOffset = cause(mtvecInterruptAlign-1, 0) << mtvecBaseAlign
val interruptVec = Cat(base >> (mtvecInterruptAlign + mtvecBaseAlign), interruptOffset)
val doVector = base(0) && cause(cause.getWidth-1) && (cause_lsbs >> mtvecInterruptAlign) === 0.U
Mux(doVector, interruptVec, base >> mtvecBaseAlign << mtvecBaseAlign)
}
val causeIsRnmiInt = cause(xLen-1) && cause(xLen-2) && (cause_lsbs === CSR.rnmiIntCause.U || cause_lsbs === CSR.rnmiBEUCause.U)
val causeIsRnmiBEU = cause(xLen-1) && cause(xLen-2) && cause_lsbs === CSR.rnmiBEUCause.U
val causeIsNmi = causeIsRnmiInt
val nmiTVecInt = io.interrupts.nmi.map(nmi => nmi.rnmi_interrupt_vector).getOrElse(0.U)
val nmiTVecXcpt = io.interrupts.nmi.map(nmi => nmi.rnmi_exception_vector).getOrElse(0.U)
val trapToNmiInt = usingNMI.B && causeIsNmi
val trapToNmiXcpt = usingNMI.B && !nmie
val trapToNmi = trapToNmiInt || trapToNmiXcpt
val nmiTVec = (Mux(causeIsNmi, nmiTVecInt, nmiTVecXcpt)>>1)<<1
val tvec = Mux(trapToDebug, debugTVec, Mux(trapToNmi, nmiTVec, notDebugTVec))
io.evec := tvec
io.ptbr := reg_satp
io.hgatp := reg_hgatp
io.vsatp := reg_vsatp
io.eret := insn_call || insn_break || insn_ret
io.singleStep := reg_dcsr.step && !reg_debug
io.status := reg_mstatus
io.status.sd := io.status.fs.andR || io.status.xs.andR || io.status.vs.andR
io.status.debug := reg_debug
io.status.isa := reg_misa
io.status.uxl := (if (usingUser) log2Ceil(xLen) - 4 else 0).U
io.status.sxl := (if (usingSupervisor) log2Ceil(xLen) - 4 else 0).U
io.status.dprv := Mux(reg_mstatus.mprv && !reg_debug, reg_mstatus.mpp, reg_mstatus.prv)
io.status.dv := reg_mstatus.v || Mux(reg_mstatus.mprv && !reg_debug, reg_mstatus.mpv, false.B)
io.status.sd_rv32 := (xLen == 32).B && io.status.sd
io.status.mpv := reg_mstatus.mpv
io.status.gva := reg_mstatus.gva
io.hstatus := reg_hstatus
io.hstatus.vsxl := (if (usingSupervisor) log2Ceil(xLen) - 4 else 0).U
io.gstatus := reg_vsstatus
io.gstatus.sd := io.gstatus.fs.andR || io.gstatus.xs.andR || io.gstatus.vs.andR
io.gstatus.uxl := (if (usingUser) log2Ceil(xLen) - 4 else 0).U
io.gstatus.sd_rv32 := (xLen == 32).B && io.gstatus.sd
val exception = insn_call || insn_break || io.exception
assert(PopCount(insn_ret :: insn_call :: insn_break :: io.exception :: Nil) <= 1.U, "these conditions must be mutually exclusive")
when (insn_wfi && !io.singleStep && !reg_debug) { reg_wfi := true.B }
when (pending_interrupts.orR || io.interrupts.debug || exception) { reg_wfi := false.B }
io.interrupts.nmi.map(nmi => when (nmi.rnmi) { reg_wfi := false.B } )
when (io.retire(0) || exception) { reg_singleStepped := true.B }
when (!io.singleStep) { reg_singleStepped := false.B }
assert(!io.singleStep || io.retire <= 1.U)
assert(!reg_singleStepped || io.retire === 0.U)
val epc = formEPC(io.pc)
val tval = Mux(insn_break, epc, io.tval)
when (exception) {
when (trapToDebug) {
when (!reg_debug) {
reg_mstatus.v := false.B
reg_debug := true.B
reg_dpc := epc
reg_dcsr.cause := Mux(reg_singleStepped, 4.U, Mux(causeIsDebugInt, 3.U, Mux[UInt](causeIsDebugTrigger, 2.U, 1.U)))
reg_dcsr.prv := trimPrivilege(reg_mstatus.prv)
reg_dcsr.v := reg_mstatus.v
new_prv := PRV.M.U
}
}.elsewhen (trapToNmiInt) {
when (reg_rnmie) {
reg_mstatus.v := false.B
reg_mnstatus.mpv := reg_mstatus.v
reg_rnmie := false.B
reg_mnepc := epc
reg_mncause := (BigInt(1) << (xLen-1)).U | Mux(causeIsRnmiBEU, 3.U, 2.U)
reg_mnstatus.mpp := trimPrivilege(reg_mstatus.prv)
new_prv := PRV.M.U
}
}.elsewhen (delegateVS && nmie) {
reg_mstatus.v := true.B
reg_vsstatus.spp := reg_mstatus.prv
reg_vsepc := epc
reg_vscause := Mux(cause(xLen-1), Cat(cause(xLen-1, 2), 1.U(2.W)), cause)
reg_vstval := tval
reg_vsstatus.spie := reg_vsstatus.sie
reg_vsstatus.sie := false.B
new_prv := PRV.S.U
}.elsewhen (delegate && nmie) {
reg_mstatus.v := false.B
reg_hstatus.spvp := Mux(reg_mstatus.v, reg_mstatus.prv(0),reg_hstatus.spvp)
reg_hstatus.gva := io.gva
reg_hstatus.spv := reg_mstatus.v
reg_sepc := epc
reg_scause := cause
reg_stval := tval
reg_htval := io.htval
reg_htinst_read_pseudo := io.mhtinst_read_pseudo
reg_mstatus.spie := reg_mstatus.sie
reg_mstatus.spp := reg_mstatus.prv
reg_mstatus.sie := false.B
new_prv := PRV.S.U
}.otherwise {
reg_mstatus.v := false.B
reg_mstatus.mpv := reg_mstatus.v
reg_mstatus.gva := io.gva
reg_mepc := epc
reg_mcause := cause
reg_mtval := tval
reg_mtval2 := io.htval
reg_mtinst_read_pseudo := io.mhtinst_read_pseudo
reg_mstatus.mpie := reg_mstatus.mie
reg_mstatus.mpp := trimPrivilege(reg_mstatus.prv)
reg_mstatus.mie := false.B
new_prv := PRV.M.U
}
}
for (i <- 0 until supported_interrupts.getWidth) {
val en = exception && (supported_interrupts & (BigInt(1) << i).U) =/= 0.U && cause === (BigInt(1) << (xLen - 1)).U + i.U
val delegable = (delegable_interrupts & (BigInt(1) << i).U) =/= 0.U
property.cover(en && !delegate, s"INTERRUPT_M_$i")
property.cover(en && delegable && delegate, s"INTERRUPT_S_$i")
}
for (i <- 0 until xLen) {
val supported_exceptions: BigInt = 0x8fe |
(if (usingCompressed && !coreParams.misaWritable) 0 else 1) |
(if (usingUser) 0x100 else 0) |
(if (usingSupervisor) 0x200 else 0) |
(if (usingVM) 0xb000 else 0)
if (((supported_exceptions >> i) & 1) != 0) {
val en = exception && cause === i.U
val delegable = (delegable_exceptions & (BigInt(1) << i).U) =/= 0.U
property.cover(en && !delegate, s"EXCEPTION_M_$i")
property.cover(en && delegable && delegate, s"EXCEPTION_S_$i")
}
}
when (insn_ret) {
val ret_prv = WireInit(UInt(), DontCare)
when (usingSupervisor.B && !io.rw.addr(9)) {
when (!reg_mstatus.v) {
reg_mstatus.sie := reg_mstatus.spie
reg_mstatus.spie := true.B
reg_mstatus.spp := PRV.U.U
ret_prv := reg_mstatus.spp
reg_mstatus.v := usingHypervisor.B && reg_hstatus.spv
io.evec := readEPC(reg_sepc)
reg_hstatus.spv := false.B
}.otherwise {
reg_vsstatus.sie := reg_vsstatus.spie
reg_vsstatus.spie := true.B
reg_vsstatus.spp := PRV.U.U
ret_prv := reg_vsstatus.spp
reg_mstatus.v := usingHypervisor.B
io.evec := readEPC(reg_vsepc)
}
}.elsewhen (usingDebug.B && io.rw.addr(10) && io.rw.addr(7)) {
ret_prv := reg_dcsr.prv
reg_mstatus.v := usingHypervisor.B && reg_dcsr.v && reg_dcsr.prv <= PRV.S.U
reg_debug := false.B
io.evec := readEPC(reg_dpc)
}.elsewhen (usingNMI.B && io.rw.addr(10) && !io.rw.addr(7)) {
ret_prv := reg_mnstatus.mpp
reg_mstatus.v := usingHypervisor.B && reg_mnstatus.mpv && reg_mnstatus.mpp <= PRV.S.U
reg_rnmie := true.B
io.evec := readEPC(reg_mnepc)
}.otherwise {
reg_mstatus.mie := reg_mstatus.mpie
reg_mstatus.mpie := true.B
reg_mstatus.mpp := legalizePrivilege(PRV.U.U)
reg_mstatus.mpv := false.B
ret_prv := reg_mstatus.mpp
reg_mstatus.v := usingHypervisor.B && reg_mstatus.mpv && reg_mstatus.mpp <= PRV.S.U
io.evec := readEPC(reg_mepc)
}
new_prv := ret_prv
when (usingUser.B && ret_prv <= PRV.S.U) {
reg_mstatus.mprv := false.B
}
}
io.time := reg_cycle
io.csr_stall := reg_wfi || io.status.cease
io.status.cease := RegEnable(true.B, false.B, insn_cease)
io.status.wfi := reg_wfi
for ((io, reg) <- io.customCSRs zip reg_custom) {
io.wen := false.B
io.wdata := wdata
io.value := reg
}
for ((io, reg) <- io.roccCSRs zip reg_rocc) {
io.wen := false.B
io.wdata := wdata
io.value := reg
}
io.rw.rdata := Mux1H(for ((k, v) <- read_mapping) yield decoded_addr(k) -> v)
// cover access to register
val coverable_counters = read_mapping.filterNot { case (k, _) =>
k >= CSR.firstHPC + nPerfCounters && k < CSR.firstHPC + CSR.nHPM
}
coverable_counters.foreach( {case (k, v) => {
when (!k.U(11,10).andR) { // Cover points for RW CSR registers
property.cover(io.rw.cmd.isOneOf(CSR.W, CSR.S, CSR.C) && io.rw.addr===k.U, "CSR_access_"+k.toString, "Cover Accessing Core CSR field")
} .otherwise { // Cover points for RO CSR registers
property.cover(io.rw.cmd===CSR.R && io.rw.addr===k.U, "CSR_access_"+k.toString, "Cover Accessing Core CSR field")
}
}})
val set_vs_dirty = WireDefault(io.vector.map(_.set_vs_dirty).getOrElse(false.B))
io.vector.foreach { vio =>
when (set_vs_dirty) {
assert(reg_mstatus.vs > 0.U)
when (reg_mstatus.v) { reg_vsstatus.vs := 3.U }
reg_mstatus.vs := 3.U
}
}
val set_fs_dirty = WireDefault(io.set_fs_dirty.getOrElse(false.B))
if (coreParams.haveFSDirty) {
when (set_fs_dirty) {
assert(reg_mstatus.fs > 0.U)
when (reg_mstatus.v) { reg_vsstatus.fs := 3.U }
reg_mstatus.fs := 3.U
}
}
io.fcsr_rm := reg_frm
when (io.fcsr_flags.valid) {
reg_fflags := reg_fflags | io.fcsr_flags.bits
set_fs_dirty := true.B
}
io.vector.foreach { vio =>
when (vio.set_vxsat) {
reg_vxsat.get := true.B
set_vs_dirty := true.B
}
}
val csr_wen = io.rw.cmd.isOneOf(CSR.S, CSR.C, CSR.W) && !io.rw_stall
io.csrw_counter := Mux(coreParams.haveBasicCounters.B && csr_wen && (io.rw.addr.inRange(CSRs.mcycle.U, (CSRs.mcycle + CSR.nCtr).U) || io.rw.addr.inRange(CSRs.mcycleh.U, (CSRs.mcycleh + CSR.nCtr).U)), UIntToOH(io.rw.addr(log2Ceil(CSR.nCtr+nPerfCounters)-1, 0)), 0.U)
when (csr_wen) {
val scause_mask = ((BigInt(1) << (xLen-1)) + 31).U /* only implement 5 LSBs and MSB */
val satp_valid_modes = 0 +: (minPgLevels to pgLevels).map(new PTBR().pgLevelsToMode(_))
when (decoded_addr(CSRs.mstatus)) {
val new_mstatus = wdata.asTypeOf(new MStatus())
reg_mstatus.mie := new_mstatus.mie
reg_mstatus.mpie := new_mstatus.mpie
if (usingUser) {
reg_mstatus.mprv := new_mstatus.mprv
reg_mstatus.mpp := legalizePrivilege(new_mstatus.mpp)
if (usingSupervisor) {
reg_mstatus.spp := new_mstatus.spp
reg_mstatus.spie := new_mstatus.spie
reg_mstatus.sie := new_mstatus.sie
reg_mstatus.tw := new_mstatus.tw
reg_mstatus.tsr := new_mstatus.tsr
}
if (usingVM) {
reg_mstatus.mxr := new_mstatus.mxr
reg_mstatus.sum := new_mstatus.sum
reg_mstatus.tvm := new_mstatus.tvm
}
if (usingHypervisor) {
reg_mstatus.mpv := new_mstatus.mpv
reg_mstatus.gva := new_mstatus.gva
}
}
if (usingSupervisor || usingFPU) reg_mstatus.fs := formFS(new_mstatus.fs)
reg_mstatus.vs := formVS(new_mstatus.vs)
}
when (decoded_addr(CSRs.misa)) {
val mask = isaStringToMask(isaMaskString).U(xLen.W)
val f = wdata('f' - 'a')
// suppress write if it would cause the next fetch to be misaligned
when (!usingCompressed.B || !io.pc(1) || wdata('c' - 'a')) {
if (coreParams.misaWritable)
reg_misa := ~(~wdata | (!f << ('d' - 'a'))) & mask | reg_misa & ~mask
}
}
when (decoded_addr(CSRs.mip)) {
// MIP should be modified based on the value in reg_mip, not the value
// in read_mip, since read_mip.seip is the OR of reg_mip.seip and
// io.interrupts.seip. We don't want the value on the PLIC line to
// inadvertently be OR'd into read_mip.seip.
val new_mip = readModifyWriteCSR(io.rw.cmd, reg_mip.asUInt, io.rw.wdata).asTypeOf(new MIP)
if (usingSupervisor) {
reg_mip.ssip := new_mip.ssip
reg_mip.stip := new_mip.stip
reg_mip.seip := new_mip.seip
}
if (usingHypervisor) {
reg_mip.vssip := new_mip.vssip
}
}
when (decoded_addr(CSRs.mie)) { reg_mie := wdata & supported_interrupts }
when (decoded_addr(CSRs.mepc)) { reg_mepc := formEPC(wdata) }
when (decoded_addr(CSRs.mscratch)) { reg_mscratch := wdata }
if (mtvecWritable)
when (decoded_addr(CSRs.mtvec)) { reg_mtvec := wdata }
when (decoded_addr(CSRs.mcause)) { reg_mcause := wdata & ((BigInt(1) << (xLen-1)) + (BigInt(1) << whichInterrupt.getWidth) - 1).U }
when (decoded_addr(CSRs.mtval)) { reg_mtval := wdata }
if (usingNMI) {
val new_mnstatus = wdata.asTypeOf(new MNStatus())
when (decoded_addr(CustomCSRs.mnscratch)) { reg_mnscratch := wdata }
when (decoded_addr(CustomCSRs.mnepc)) { reg_mnepc := formEPC(wdata) }
when (decoded_addr(CustomCSRs.mncause)) { reg_mncause := wdata & ((BigInt(1) << (xLen-1)) + BigInt(3)).U }
when (decoded_addr(CustomCSRs.mnstatus)) {
reg_mnstatus.mpp := legalizePrivilege(new_mnstatus.mpp)
reg_mnstatus.mpv := usingHypervisor.B && new_mnstatus.mpv
reg_rnmie := reg_rnmie | new_mnstatus.mie // mnie bit settable but not clearable from software
}
}
for (((e, c), i) <- (reg_hpmevent zip reg_hpmcounter).zipWithIndex) {
writeCounter(i + CSR.firstMHPC, c, wdata)
when (decoded_addr(i + CSR.firstHPE)) { e := perfEventSets.maskEventSelector(wdata) }
}
if (coreParams.haveBasicCounters) {
when (decoded_addr(CSRs.mcountinhibit)) { reg_mcountinhibit := wdata & ~2.U(xLen.W) } // mcountinhibit bit [1] is tied zero
writeCounter(CSRs.mcycle, reg_cycle, wdata)
writeCounter(CSRs.minstret, reg_instret, wdata)
}
if (usingFPU) {
when (decoded_addr(CSRs.fflags)) { set_fs_dirty := true.B; reg_fflags := wdata }
when (decoded_addr(CSRs.frm)) { set_fs_dirty := true.B; reg_frm := wdata }
when (decoded_addr(CSRs.fcsr)) {
set_fs_dirty := true.B
reg_fflags := wdata
reg_frm := wdata >> reg_fflags.getWidth
}
}
if (usingDebug) {
when (decoded_addr(CSRs.dcsr)) {
val new_dcsr = wdata.asTypeOf(new DCSR())
reg_dcsr.step := new_dcsr.step
reg_dcsr.ebreakm := new_dcsr.ebreakm
if (usingSupervisor) reg_dcsr.ebreaks := new_dcsr.ebreaks
if (usingUser) reg_dcsr.ebreaku := new_dcsr.ebreaku
if (usingUser) reg_dcsr.prv := legalizePrivilege(new_dcsr.prv)
if (usingHypervisor) reg_dcsr.v := new_dcsr.v
}
when (decoded_addr(CSRs.dpc)) { reg_dpc := formEPC(wdata) }
when (decoded_addr(CSRs.dscratch0)) { reg_dscratch0 := wdata }
reg_dscratch1.foreach { r =>
when (decoded_addr(CSRs.dscratch1)) { r := wdata }
}
}
if (usingSupervisor) {
when (decoded_addr(CSRs.sstatus)) {
val new_sstatus = wdata.asTypeOf(new MStatus())
reg_mstatus.sie := new_sstatus.sie
reg_mstatus.spie := new_sstatus.spie
reg_mstatus.spp := new_sstatus.spp
reg_mstatus.fs := formFS(new_sstatus.fs)
reg_mstatus.vs := formVS(new_sstatus.vs)
if (usingVM) {
reg_mstatus.mxr := new_sstatus.mxr
reg_mstatus.sum := new_sstatus.sum
}
}
when (decoded_addr(CSRs.sip)) {
val new_sip = ((read_mip & ~read_mideleg) | (wdata & read_mideleg)).asTypeOf(new MIP())
reg_mip.ssip := new_sip.ssip
}
when (decoded_addr(CSRs.satp)) {
if (usingVM) {
val new_satp = wdata.asTypeOf(new PTBR())
when (new_satp.mode.isOneOf(satp_valid_modes.map(_.U))) {
reg_satp.mode := new_satp.mode & satp_valid_modes.reduce(_|_).U
reg_satp.ppn := new_satp.ppn(ppnBits-1,0)
if (asIdBits > 0) reg_satp.asid := new_satp.asid(asIdBits-1,0)
}
}
}
when (decoded_addr(CSRs.sie)) { reg_mie := (reg_mie & ~sie_mask) | (wdata & sie_mask) }
when (decoded_addr(CSRs.sscratch)) { reg_sscratch := wdata }
when (decoded_addr(CSRs.sepc)) { reg_sepc := formEPC(wdata) }
when (decoded_addr(CSRs.stvec)) { reg_stvec := wdata }
when (decoded_addr(CSRs.scause)) { reg_scause := wdata & scause_mask }
when (decoded_addr(CSRs.stval)) { reg_stval := wdata }
when (decoded_addr(CSRs.mideleg)) { reg_mideleg := wdata }
when (decoded_addr(CSRs.medeleg)) { reg_medeleg := wdata }
when (decoded_addr(CSRs.scounteren)) { reg_scounteren := wdata }
when (decoded_addr(CSRs.senvcfg)) { reg_senvcfg.write(wdata) }
}
if (usingHypervisor) {
when (decoded_addr(CSRs.hstatus)) {
val new_hstatus = wdata.asTypeOf(new HStatus())
reg_hstatus.gva := new_hstatus.gva
reg_hstatus.spv := new_hstatus.spv
reg_hstatus.spvp := new_hstatus.spvp
reg_hstatus.hu := new_hstatus.hu
reg_hstatus.vtvm := new_hstatus.vtvm
reg_hstatus.vtw := new_hstatus.vtw
reg_hstatus.vtsr := new_hstatus.vtsr
reg_hstatus.vsxl := new_hstatus.vsxl
}
when (decoded_addr(CSRs.hideleg)) { reg_hideleg := wdata }
when (decoded_addr(CSRs.hedeleg)) { reg_hedeleg := wdata }
when (decoded_addr(CSRs.hgatp)) {
val new_hgatp = wdata.asTypeOf(new PTBR())
val valid_modes = 0 +: (minPgLevels to pgLevels).map(new_hgatp.pgLevelsToMode(_))
when (new_hgatp.mode.isOneOf(valid_modes.map(_.U))) {
reg_hgatp.mode := new_hgatp.mode & valid_modes.reduce(_|_).U
}
reg_hgatp.ppn := Cat(new_hgatp.ppn(ppnBits-1,2), 0.U(2.W))
if (vmIdBits > 0) reg_hgatp.asid := new_hgatp.asid(vmIdBits-1,0)
}
when (decoded_addr(CSRs.hip)) {
val new_hip = ((read_mip & ~hs_delegable_interrupts) | (wdata & hs_delegable_interrupts)).asTypeOf(new MIP())
reg_mip.vssip := new_hip.vssip
}
when (decoded_addr(CSRs.hie)) { reg_mie := (reg_mie & ~hs_delegable_interrupts) | (wdata & hs_delegable_interrupts) }
when (decoded_addr(CSRs.hvip)) {
val new_sip = ((read_mip & ~hs_delegable_interrupts) | (wdata & hs_delegable_interrupts)).asTypeOf(new MIP())
reg_mip.vssip := new_sip.vssip
reg_mip.vstip := new_sip.vstip
reg_mip.vseip := new_sip.vseip
}
when (decoded_addr(CSRs.hcounteren)) { reg_hcounteren := wdata }
when (decoded_addr(CSRs.htval)) { reg_htval := wdata }
when (decoded_addr(CSRs.mtval2)) { reg_mtval2 := wdata }
val write_mhtinst_read_pseudo = wdata(13) && (xLen == 32).option(true.B).getOrElse(wdata(12))
when(decoded_addr(CSRs.mtinst)) { reg_mtinst_read_pseudo := write_mhtinst_read_pseudo }
when(decoded_addr(CSRs.htinst)) { reg_htinst_read_pseudo := write_mhtinst_read_pseudo }
when (decoded_addr(CSRs.vsstatus)) {
val new_vsstatus = wdata.asTypeOf(new MStatus())
reg_vsstatus.sie := new_vsstatus.sie
reg_vsstatus.spie := new_vsstatus.spie
reg_vsstatus.spp := new_vsstatus.spp
reg_vsstatus.mxr := new_vsstatus.mxr
reg_vsstatus.sum := new_vsstatus.sum
reg_vsstatus.fs := formFS(new_vsstatus.fs)
reg_vsstatus.vs := formVS(new_vsstatus.vs)
}
when (decoded_addr(CSRs.vsip)) {
val new_vsip = ((read_hip & ~read_hideleg) | ((wdata << 1) & read_hideleg)).asTypeOf(new MIP())
reg_mip.vssip := new_vsip.vssip
}
when (decoded_addr(CSRs.vsatp)) {
val new_vsatp = wdata.asTypeOf(new PTBR())
val mode_ok = new_vsatp.mode.isOneOf(satp_valid_modes.map(_.U))
when (mode_ok) {
reg_vsatp.mode := new_vsatp.mode & satp_valid_modes.reduce(_|_).U
}
when (mode_ok || !reg_mstatus.v) {
reg_vsatp.ppn := new_vsatp.ppn(vpnBits.min(new_vsatp.ppn.getWidth)-1,0)
if (asIdBits > 0) reg_vsatp.asid := new_vsatp.asid(asIdBits-1,0)
}
}
when (decoded_addr(CSRs.vsie)) { reg_mie := (reg_mie & ~read_hideleg) | ((wdata << 1) & read_hideleg) }
when (decoded_addr(CSRs.vsscratch)) { reg_vsscratch := wdata }
when (decoded_addr(CSRs.vsepc)) { reg_vsepc := formEPC(wdata) }
when (decoded_addr(CSRs.vstvec)) { reg_vstvec := wdata }
when (decoded_addr(CSRs.vscause)) { reg_vscause := wdata & scause_mask }
when (decoded_addr(CSRs.vstval)) { reg_vstval := wdata }
when (decoded_addr(CSRs.henvcfg)) { reg_henvcfg.write(wdata) }
}
if (usingUser) {
when (decoded_addr(CSRs.mcounteren)) { reg_mcounteren := wdata }
when (decoded_addr(CSRs.menvcfg)) { reg_menvcfg.write(wdata) }
}
if (nBreakpoints > 0) {
when (decoded_addr(CSRs.tselect)) { reg_tselect := wdata }
for ((bp, i) <- reg_bp.zipWithIndex) {
when (i.U === reg_tselect && (!bp.control.dmode || reg_debug)) {
when (decoded_addr(CSRs.tdata2)) { bp.address := wdata }
when (decoded_addr(CSRs.tdata3)) {
if (coreParams.mcontextWidth > 0) {
bp.textra.mselect := wdata(bp.textra.mselectPos)
bp.textra.mvalue := wdata >> bp.textra.mvaluePos
}
if (coreParams.scontextWidth > 0) {
bp.textra.sselect := wdata(bp.textra.sselectPos)
bp.textra.svalue := wdata >> bp.textra.svaluePos
}
}
when (decoded_addr(CSRs.tdata1)) {
bp.control := wdata.asTypeOf(bp.control)
val prevChain = if (i == 0) false.B else reg_bp(i-1).control.chain
val prevDMode = if (i == 0) false.B else reg_bp(i-1).control.dmode
val nextChain = if (i >= nBreakpoints-1) true.B else reg_bp(i+1).control.chain
val nextDMode = if (i >= nBreakpoints-1) true.B else reg_bp(i+1).control.dmode
val newBPC = readModifyWriteCSR(io.rw.cmd, bp.control.asUInt, io.rw.wdata).asTypeOf(bp.control)
val dMode = newBPC.dmode && reg_debug && (prevDMode || !prevChain)
bp.control.dmode := dMode
when (dMode || (newBPC.action > 1.U)) { bp.control.action := newBPC.action }.otherwise { bp.control.action := 0.U }
bp.control.chain := newBPC.chain && !(prevChain || nextChain) && (dMode || !nextDMode)
}
}
}
}
reg_mcontext.foreach { r => when (decoded_addr(CSRs.mcontext)) { r := wdata }}
reg_scontext.foreach { r => when (decoded_addr(CSRs.scontext)) { r := wdata }}
if (reg_pmp.nonEmpty) for (((pmp, next), i) <- (reg_pmp zip (reg_pmp.tail :+ reg_pmp.last)).zipWithIndex) {
require(xLen % pmp.cfg.getWidth == 0)
when (decoded_addr(CSRs.pmpcfg0 + pmpCfgIndex(i)) && !pmp.cfgLocked) {
val newCfg = (wdata >> ((i * pmp.cfg.getWidth) % xLen)).asTypeOf(new PMPConfig())
pmp.cfg := newCfg
// disallow unreadable but writable PMPs
pmp.cfg.w := newCfg.w && newCfg.r
// can't select a=NA4 with coarse-grained PMPs
if (pmpGranularity.log2 > PMP.lgAlign)
pmp.cfg.a := Cat(newCfg.a(1), newCfg.a.orR)
}
when (decoded_addr(CSRs.pmpaddr0 + i) && !pmp.addrLocked(next)) {
pmp.addr := wdata
}
}
def writeCustomCSR(io: CustomCSRIO, csr: CustomCSR, reg: UInt) = {
val mask = csr.mask.U(xLen.W)
when (decoded_addr(csr.id)) {
reg := (wdata & mask) | (reg & ~mask)
io.wen := true.B
}
}
for ((io, csr, reg) <- (io.customCSRs, customCSRs, reg_custom).zipped) {
writeCustomCSR(io, csr, reg)
}
for ((io, csr, reg) <- (io.roccCSRs, roccCSRs, reg_rocc).zipped) {
writeCustomCSR(io, csr, reg)
}
if (usingVector) {
when (decoded_addr(CSRs.vstart)) { set_vs_dirty := true.B; reg_vstart.get := wdata }
when (decoded_addr(CSRs.vxrm)) { set_vs_dirty := true.B; reg_vxrm.get := wdata }
when (decoded_addr(CSRs.vxsat)) { set_vs_dirty := true.B; reg_vxsat.get := wdata }
when (decoded_addr(CSRs.vcsr)) {
set_vs_dirty := true.B
reg_vxsat.get := wdata
reg_vxrm.get := wdata >> 1
}
}
}
def setCustomCSR(io: CustomCSRIO, csr: CustomCSR, reg: UInt) = {
val mask = csr.mask.U(xLen.W)
when (io.set) {
reg := (io.sdata & mask) | (reg & ~mask)
}
}
for ((io, csr, reg) <- (io.customCSRs, customCSRs, reg_custom).zipped) {
setCustomCSR(io, csr, reg)
}
for ((io, csr, reg) <- (io.roccCSRs, roccCSRs, reg_rocc).zipped) {
setCustomCSR(io, csr, reg)
}
io.vector.map { vio =>
when (vio.set_vconfig.valid) {
// user of CSRFile is responsible for set_vs_dirty in this case
assert(vio.set_vconfig.bits.vl <= vio.set_vconfig.bits.vtype.vlMax)
reg_vconfig.get := vio.set_vconfig.bits
}
when (vio.set_vstart.valid) {
set_vs_dirty := true.B
reg_vstart.get := vio.set_vstart.bits
}
vio.vstart := reg_vstart.get
vio.vconfig := reg_vconfig.get
vio.vxrm := reg_vxrm.get
when (reset.asBool) {
reg_vconfig.get.vl := 0.U
reg_vconfig.get.vtype := 0.U.asTypeOf(new VType)
reg_vconfig.get.vtype.vill := true.B
}
}
when(reset.asBool) {
reg_satp.mode := 0.U
reg_vsatp.mode := 0.U
reg_hgatp.mode := 0.U
}
if (!usingVM) {
reg_satp.mode := 0.U
reg_satp.ppn := 0.U
reg_satp.asid := 0.U
}
if (!usingHypervisor) {
reg_vsatp.mode := 0.U
reg_vsatp.ppn := 0.U
reg_vsatp.asid := 0.U
reg_hgatp.mode := 0.U
reg_hgatp.ppn := 0.U
reg_hgatp.asid := 0.U
}
if (!(asIdBits > 0)) {
reg_satp.asid := 0.U
reg_vsatp.asid := 0.U
}
if (!(vmIdBits > 0)) {
reg_hgatp.asid := 0.U
}
reg_vsstatus.xs := (if (usingRoCC) 3.U else 0.U)
if (nBreakpoints <= 1) reg_tselect := 0.U
for (bpc <- reg_bp map {_.control}) {
bpc.ttype := bpc.tType.U
bpc.maskmax := bpc.maskMax.U
bpc.reserved := 0.U
bpc.zero := 0.U
bpc.h := false.B
if (!usingSupervisor) bpc.s := false.B
if (!usingUser) bpc.u := false.B
if (!usingSupervisor && !usingUser) bpc.m := true.B
when (reset.asBool) {
bpc.action := 0.U
bpc.dmode := false.B
bpc.chain := false.B
bpc.r := false.B
bpc.w := false.B
bpc.x := false.B
}
}
for (bpx <- reg_bp map {_.textra}) {
if (coreParams.mcontextWidth == 0) bpx.mselect := false.B
if (coreParams.scontextWidth == 0) bpx.sselect := false.B
}
for (bp <- reg_bp drop nBreakpoints)
bp := 0.U.asTypeOf(new BP())
for (pmp <- reg_pmp) {
pmp.cfg.res := 0.U
when (reset.asBool) { pmp.reset() }
}
for (((t, insn), i) <- (io.trace zip io.inst).zipWithIndex) {
t.exception := io.retire >= i.U && exception
t.valid := io.retire > i.U || t.exception
t.insn := insn
t.iaddr := io.pc
t.priv := Cat(reg_debug, reg_mstatus.prv)
t.cause := cause
t.interrupt := cause(xLen-1)
t.tval := io.tval
t.wdata.foreach(_ := DontCare)
}
def chooseInterrupt(masksIn: Seq[UInt]): (Bool, UInt) = {
val nonstandard = supported_interrupts.getWidth-1 to 12 by -1
// MEI, MSI, MTI, SEI, SSI, STI, VSEI, VSSI, VSTI, UEI, USI, UTI
val standard = Seq(11, 3, 7, 9, 1, 5, 10, 2, 6, 8, 0, 4)
val priority = nonstandard ++ standard
val masks = masksIn.reverse
val any = masks.flatMap(m => priority.filter(_ < m.getWidth).map(i => m(i))).reduce(_||_)
val which = PriorityMux(masks.flatMap(m => priority.filter(_ < m.getWidth).map(i => (m(i), i.U))))
(any, which)
}
def readModifyWriteCSR(cmd: UInt, rdata: UInt, wdata: UInt) = {
(Mux(cmd(1), rdata, 0.U) | wdata) & ~Mux(cmd(1,0).andR, wdata, 0.U)
}
def legalizePrivilege(priv: UInt): UInt =
if (usingSupervisor) Mux(priv === PRV.H.U, PRV.U.U, priv)
else if (usingUser) Fill(2, priv(0))
else PRV.M.U
def trimPrivilege(priv: UInt): UInt =
if (usingSupervisor) priv
else legalizePrivilege(priv)
def writeCounter(lo: Int, ctr: WideCounter, wdata: UInt) = {
if (xLen == 32) {
val hi = lo + CSRs.mcycleh - CSRs.mcycle
when (decoded_addr(lo)) { ctr := Cat(ctr(ctr.getWidth-1, 32), wdata) }
when (decoded_addr(hi)) { ctr := Cat(wdata(ctr.getWidth-33, 0), ctr(31, 0)) }
} else {
when (decoded_addr(lo)) { ctr := wdata(ctr.getWidth-1, 0) }
}
}
def formEPC(x: UInt) = ~(~x | (if (usingCompressed) 1.U else 3.U))
def readEPC(x: UInt) = ~(~x | Mux(reg_misa('c' - 'a'), 1.U, 3.U))
def formTVec(x: UInt) = x andNot Mux(x(0), ((((BigInt(1) << mtvecInterruptAlign) - 1) << mtvecBaseAlign) | 2).U, 2.U)
def isaStringToMask(s: String) = s.map(x => 1 << (x - 'A')).foldLeft(0)(_|_)
def formFS(fs: UInt) = if (coreParams.haveFSDirty) fs else Fill(2, fs.orR)
def formVS(vs: UInt) = if (usingVector) vs else 0.U
}
| module BoomCore( // @[core.scala:51:7]
input clock, // @[core.scala:51:7]
input reset, // @[core.scala:51:7]
input io_hartid, // @[core.scala:54:14]
input io_interrupts_debug, // @[core.scala:54:14]
input io_interrupts_mtip, // @[core.scala:54:14]
input io_interrupts_msip, // @[core.scala:54:14]
input io_interrupts_meip, // @[core.scala:54:14]
input io_interrupts_seip, // @[core.scala:54:14]
output io_ifu_fetchpacket_ready, // @[core.scala:54:14]
input io_ifu_fetchpacket_valid, // @[core.scala:54:14]
input io_ifu_fetchpacket_bits_uops_0_valid, // @[core.scala:54:14]
input [31:0] io_ifu_fetchpacket_bits_uops_0_bits_inst, // @[core.scala:54:14]
input [31:0] io_ifu_fetchpacket_bits_uops_0_bits_debug_inst, // @[core.scala:54:14]
input io_ifu_fetchpacket_bits_uops_0_bits_is_rvc, // @[core.scala:54:14]
input [39:0] io_ifu_fetchpacket_bits_uops_0_bits_debug_pc, // @[core.scala:54:14]
input io_ifu_fetchpacket_bits_uops_0_bits_is_sfb, // @[core.scala:54:14]
input [4:0] io_ifu_fetchpacket_bits_uops_0_bits_ftq_idx, // @[core.scala:54:14]
input io_ifu_fetchpacket_bits_uops_0_bits_edge_inst, // @[core.scala:54:14]
input [5:0] io_ifu_fetchpacket_bits_uops_0_bits_pc_lob, // @[core.scala:54:14]
input io_ifu_fetchpacket_bits_uops_0_bits_taken, // @[core.scala:54:14]
input io_ifu_fetchpacket_bits_uops_0_bits_xcpt_pf_if, // @[core.scala:54:14]
input io_ifu_fetchpacket_bits_uops_0_bits_xcpt_ae_if, // @[core.scala:54:14]
input io_ifu_fetchpacket_bits_uops_0_bits_bp_debug_if, // @[core.scala:54:14]
input io_ifu_fetchpacket_bits_uops_0_bits_bp_xcpt_if, // @[core.scala:54:14]
input [1:0] io_ifu_fetchpacket_bits_uops_0_bits_debug_fsrc, // @[core.scala:54:14]
input io_ifu_fetchpacket_bits_uops_1_valid, // @[core.scala:54:14]
input [31:0] io_ifu_fetchpacket_bits_uops_1_bits_inst, // @[core.scala:54:14]
input [31:0] io_ifu_fetchpacket_bits_uops_1_bits_debug_inst, // @[core.scala:54:14]
input io_ifu_fetchpacket_bits_uops_1_bits_is_rvc, // @[core.scala:54:14]
input [39:0] io_ifu_fetchpacket_bits_uops_1_bits_debug_pc, // @[core.scala:54:14]
input io_ifu_fetchpacket_bits_uops_1_bits_is_sfb, // @[core.scala:54:14]
input [4:0] io_ifu_fetchpacket_bits_uops_1_bits_ftq_idx, // @[core.scala:54:14]
input io_ifu_fetchpacket_bits_uops_1_bits_edge_inst, // @[core.scala:54:14]
input [5:0] io_ifu_fetchpacket_bits_uops_1_bits_pc_lob, // @[core.scala:54:14]
input io_ifu_fetchpacket_bits_uops_1_bits_taken, // @[core.scala:54:14]
input io_ifu_fetchpacket_bits_uops_1_bits_xcpt_pf_if, // @[core.scala:54:14]
input io_ifu_fetchpacket_bits_uops_1_bits_xcpt_ae_if, // @[core.scala:54:14]
input io_ifu_fetchpacket_bits_uops_1_bits_bp_debug_if, // @[core.scala:54:14]
input io_ifu_fetchpacket_bits_uops_1_bits_bp_xcpt_if, // @[core.scala:54:14]
input [1:0] io_ifu_fetchpacket_bits_uops_1_bits_debug_fsrc, // @[core.scala:54:14]
input io_ifu_fetchpacket_bits_uops_2_valid, // @[core.scala:54:14]
input [31:0] io_ifu_fetchpacket_bits_uops_2_bits_inst, // @[core.scala:54:14]
input [31:0] io_ifu_fetchpacket_bits_uops_2_bits_debug_inst, // @[core.scala:54:14]
input io_ifu_fetchpacket_bits_uops_2_bits_is_rvc, // @[core.scala:54:14]
input [39:0] io_ifu_fetchpacket_bits_uops_2_bits_debug_pc, // @[core.scala:54:14]
input io_ifu_fetchpacket_bits_uops_2_bits_is_sfb, // @[core.scala:54:14]
input [4:0] io_ifu_fetchpacket_bits_uops_2_bits_ftq_idx, // @[core.scala:54:14]
input io_ifu_fetchpacket_bits_uops_2_bits_edge_inst, // @[core.scala:54:14]
input [5:0] io_ifu_fetchpacket_bits_uops_2_bits_pc_lob, // @[core.scala:54:14]
input io_ifu_fetchpacket_bits_uops_2_bits_taken, // @[core.scala:54:14]
input io_ifu_fetchpacket_bits_uops_2_bits_xcpt_pf_if, // @[core.scala:54:14]
input io_ifu_fetchpacket_bits_uops_2_bits_xcpt_ae_if, // @[core.scala:54:14]
input io_ifu_fetchpacket_bits_uops_2_bits_bp_debug_if, // @[core.scala:54:14]
input io_ifu_fetchpacket_bits_uops_2_bits_bp_xcpt_if, // @[core.scala:54:14]
input [1:0] io_ifu_fetchpacket_bits_uops_2_bits_debug_fsrc, // @[core.scala:54:14]
output [4:0] io_ifu_get_pc_0_ftq_idx, // @[core.scala:54:14]
input io_ifu_get_pc_0_entry_cfi_idx_valid, // @[core.scala:54:14]
input [2:0] io_ifu_get_pc_0_entry_cfi_idx_bits, // @[core.scala:54:14]
input io_ifu_get_pc_0_entry_cfi_taken, // @[core.scala:54:14]
input io_ifu_get_pc_0_entry_cfi_mispredicted, // @[core.scala:54:14]
input [2:0] io_ifu_get_pc_0_entry_cfi_type, // @[core.scala:54:14]
input [7:0] io_ifu_get_pc_0_entry_br_mask, // @[core.scala:54:14]
input io_ifu_get_pc_0_entry_cfi_is_call, // @[core.scala:54:14]
input io_ifu_get_pc_0_entry_cfi_is_ret, // @[core.scala:54:14]
input io_ifu_get_pc_0_entry_cfi_npc_plus4, // @[core.scala:54:14]
input [39:0] io_ifu_get_pc_0_entry_ras_top, // @[core.scala:54:14]
input [4:0] io_ifu_get_pc_0_entry_ras_idx, // @[core.scala:54:14]
input io_ifu_get_pc_0_entry_start_bank, // @[core.scala:54:14]
input [39:0] io_ifu_get_pc_0_pc, // @[core.scala:54:14]
input [39:0] io_ifu_get_pc_0_com_pc, // @[core.scala:54:14]
input io_ifu_get_pc_0_next_val, // @[core.scala:54:14]
input [39:0] io_ifu_get_pc_0_next_pc, // @[core.scala:54:14]
output [4:0] io_ifu_get_pc_1_ftq_idx, // @[core.scala:54:14]
input io_ifu_get_pc_1_entry_cfi_idx_valid, // @[core.scala:54:14]
input [2:0] io_ifu_get_pc_1_entry_cfi_idx_bits, // @[core.scala:54:14]
input io_ifu_get_pc_1_entry_cfi_taken, // @[core.scala:54:14]
input io_ifu_get_pc_1_entry_cfi_mispredicted, // @[core.scala:54:14]
input [2:0] io_ifu_get_pc_1_entry_cfi_type, // @[core.scala:54:14]
input [7:0] io_ifu_get_pc_1_entry_br_mask, // @[core.scala:54:14]
input io_ifu_get_pc_1_entry_cfi_is_call, // @[core.scala:54:14]
input io_ifu_get_pc_1_entry_cfi_is_ret, // @[core.scala:54:14]
input io_ifu_get_pc_1_entry_cfi_npc_plus4, // @[core.scala:54:14]
input [39:0] io_ifu_get_pc_1_entry_ras_top, // @[core.scala:54:14]
input [4:0] io_ifu_get_pc_1_entry_ras_idx, // @[core.scala:54:14]
input io_ifu_get_pc_1_entry_start_bank, // @[core.scala:54:14]
input [63:0] io_ifu_get_pc_1_ghist_old_history, // @[core.scala:54:14]
input io_ifu_get_pc_1_ghist_current_saw_branch_not_taken, // @[core.scala:54:14]
input io_ifu_get_pc_1_ghist_new_saw_branch_not_taken, // @[core.scala:54:14]
input io_ifu_get_pc_1_ghist_new_saw_branch_taken, // @[core.scala:54:14]
input [4:0] io_ifu_get_pc_1_ghist_ras_idx, // @[core.scala:54:14]
input [39:0] io_ifu_get_pc_1_pc, // @[core.scala:54:14]
input [39:0] io_ifu_get_pc_1_com_pc, // @[core.scala:54:14]
input io_ifu_get_pc_1_next_val, // @[core.scala:54:14]
input [39:0] io_ifu_get_pc_1_next_pc, // @[core.scala:54:14]
input [39:0] io_ifu_debug_fetch_pc_0, // @[core.scala:54:14]
input [39:0] io_ifu_debug_fetch_pc_1, // @[core.scala:54:14]
input [39:0] io_ifu_debug_fetch_pc_2, // @[core.scala:54:14]
output io_ifu_status_debug, // @[core.scala:54:14]
output io_ifu_status_cease, // @[core.scala:54:14]
output io_ifu_status_wfi, // @[core.scala:54:14]
output [1:0] io_ifu_status_dprv, // @[core.scala:54:14]
output io_ifu_status_dv, // @[core.scala:54:14]
output [1:0] io_ifu_status_prv, // @[core.scala:54:14]
output io_ifu_status_v, // @[core.scala:54:14]
output io_ifu_status_sd, // @[core.scala:54:14]
output io_ifu_status_mpv, // @[core.scala:54:14]
output io_ifu_status_gva, // @[core.scala:54:14]
output io_ifu_status_tsr, // @[core.scala:54:14]
output io_ifu_status_tw, // @[core.scala:54:14]
output io_ifu_status_tvm, // @[core.scala:54:14]
output io_ifu_status_mxr, // @[core.scala:54:14]
output io_ifu_status_sum, // @[core.scala:54:14]
output io_ifu_status_mprv, // @[core.scala:54:14]
output [1:0] io_ifu_status_fs, // @[core.scala:54:14]
output [1:0] io_ifu_status_mpp, // @[core.scala:54:14]
output io_ifu_status_spp, // @[core.scala:54:14]
output io_ifu_status_mpie, // @[core.scala:54:14]
output io_ifu_status_spie, // @[core.scala:54:14]
output io_ifu_status_mie, // @[core.scala:54:14]
output io_ifu_status_sie, // @[core.scala:54:14]
output io_ifu_sfence_valid, // @[core.scala:54:14]
output io_ifu_sfence_bits_rs1, // @[core.scala:54:14]
output io_ifu_sfence_bits_rs2, // @[core.scala:54:14]
output [38:0] io_ifu_sfence_bits_addr, // @[core.scala:54:14]
output io_ifu_sfence_bits_asid, // @[core.scala:54:14]
output [15:0] io_ifu_brupdate_b1_resolve_mask, // @[core.scala:54:14]
output [15:0] io_ifu_brupdate_b1_mispredict_mask, // @[core.scala:54:14]
output [6:0] io_ifu_brupdate_b2_uop_uopc, // @[core.scala:54:14]
output [31:0] io_ifu_brupdate_b2_uop_inst, // @[core.scala:54:14]
output [31:0] io_ifu_brupdate_b2_uop_debug_inst, // @[core.scala:54:14]
output io_ifu_brupdate_b2_uop_is_rvc, // @[core.scala:54:14]
output [39:0] io_ifu_brupdate_b2_uop_debug_pc, // @[core.scala:54:14]
output [2:0] io_ifu_brupdate_b2_uop_iq_type, // @[core.scala:54:14]
output [9:0] io_ifu_brupdate_b2_uop_fu_code, // @[core.scala:54:14]
output [3:0] io_ifu_brupdate_b2_uop_ctrl_br_type, // @[core.scala:54:14]
output [1:0] io_ifu_brupdate_b2_uop_ctrl_op1_sel, // @[core.scala:54:14]
output [2:0] io_ifu_brupdate_b2_uop_ctrl_op2_sel, // @[core.scala:54:14]
output [2:0] io_ifu_brupdate_b2_uop_ctrl_imm_sel, // @[core.scala:54:14]
output [4:0] io_ifu_brupdate_b2_uop_ctrl_op_fcn, // @[core.scala:54:14]
output io_ifu_brupdate_b2_uop_ctrl_fcn_dw, // @[core.scala:54:14]
output [2:0] io_ifu_brupdate_b2_uop_ctrl_csr_cmd, // @[core.scala:54:14]
output io_ifu_brupdate_b2_uop_ctrl_is_load, // @[core.scala:54:14]
output io_ifu_brupdate_b2_uop_ctrl_is_sta, // @[core.scala:54:14]
output io_ifu_brupdate_b2_uop_ctrl_is_std, // @[core.scala:54:14]
output [1:0] io_ifu_brupdate_b2_uop_iw_state, // @[core.scala:54:14]
output io_ifu_brupdate_b2_uop_iw_p1_poisoned, // @[core.scala:54:14]
output io_ifu_brupdate_b2_uop_iw_p2_poisoned, // @[core.scala:54:14]
output io_ifu_brupdate_b2_uop_is_br, // @[core.scala:54:14]
output io_ifu_brupdate_b2_uop_is_jalr, // @[core.scala:54:14]
output io_ifu_brupdate_b2_uop_is_jal, // @[core.scala:54:14]
output io_ifu_brupdate_b2_uop_is_sfb, // @[core.scala:54:14]
output [15:0] io_ifu_brupdate_b2_uop_br_mask, // @[core.scala:54:14]
output [3:0] io_ifu_brupdate_b2_uop_br_tag, // @[core.scala:54:14]
output [4:0] io_ifu_brupdate_b2_uop_ftq_idx, // @[core.scala:54:14]
output io_ifu_brupdate_b2_uop_edge_inst, // @[core.scala:54:14]
output [5:0] io_ifu_brupdate_b2_uop_pc_lob, // @[core.scala:54:14]
output io_ifu_brupdate_b2_uop_taken, // @[core.scala:54:14]
output [19:0] io_ifu_brupdate_b2_uop_imm_packed, // @[core.scala:54:14]
output [11:0] io_ifu_brupdate_b2_uop_csr_addr, // @[core.scala:54:14]
output [6:0] io_ifu_brupdate_b2_uop_rob_idx, // @[core.scala:54:14]
output [4:0] io_ifu_brupdate_b2_uop_ldq_idx, // @[core.scala:54:14]
output [4:0] io_ifu_brupdate_b2_uop_stq_idx, // @[core.scala:54:14]
output [1:0] io_ifu_brupdate_b2_uop_rxq_idx, // @[core.scala:54:14]
output [6:0] io_ifu_brupdate_b2_uop_pdst, // @[core.scala:54:14]
output [6:0] io_ifu_brupdate_b2_uop_prs1, // @[core.scala:54:14]
output [6:0] io_ifu_brupdate_b2_uop_prs2, // @[core.scala:54:14]
output [6:0] io_ifu_brupdate_b2_uop_prs3, // @[core.scala:54:14]
output [4:0] io_ifu_brupdate_b2_uop_ppred, // @[core.scala:54:14]
output io_ifu_brupdate_b2_uop_prs1_busy, // @[core.scala:54:14]
output io_ifu_brupdate_b2_uop_prs2_busy, // @[core.scala:54:14]
output io_ifu_brupdate_b2_uop_prs3_busy, // @[core.scala:54:14]
output io_ifu_brupdate_b2_uop_ppred_busy, // @[core.scala:54:14]
output [6:0] io_ifu_brupdate_b2_uop_stale_pdst, // @[core.scala:54:14]
output io_ifu_brupdate_b2_uop_exception, // @[core.scala:54:14]
output [63:0] io_ifu_brupdate_b2_uop_exc_cause, // @[core.scala:54:14]
output io_ifu_brupdate_b2_uop_bypassable, // @[core.scala:54:14]
output [4:0] io_ifu_brupdate_b2_uop_mem_cmd, // @[core.scala:54:14]
output [1:0] io_ifu_brupdate_b2_uop_mem_size, // @[core.scala:54:14]
output io_ifu_brupdate_b2_uop_mem_signed, // @[core.scala:54:14]
output io_ifu_brupdate_b2_uop_is_fence, // @[core.scala:54:14]
output io_ifu_brupdate_b2_uop_is_fencei, // @[core.scala:54:14]
output io_ifu_brupdate_b2_uop_is_amo, // @[core.scala:54:14]
output io_ifu_brupdate_b2_uop_uses_ldq, // @[core.scala:54:14]
output io_ifu_brupdate_b2_uop_uses_stq, // @[core.scala:54:14]
output io_ifu_brupdate_b2_uop_is_sys_pc2epc, // @[core.scala:54:14]
output io_ifu_brupdate_b2_uop_is_unique, // @[core.scala:54:14]
output io_ifu_brupdate_b2_uop_flush_on_commit, // @[core.scala:54:14]
output io_ifu_brupdate_b2_uop_ldst_is_rs1, // @[core.scala:54:14]
output [5:0] io_ifu_brupdate_b2_uop_ldst, // @[core.scala:54:14]
output [5:0] io_ifu_brupdate_b2_uop_lrs1, // @[core.scala:54:14]
output [5:0] io_ifu_brupdate_b2_uop_lrs2, // @[core.scala:54:14]
output [5:0] io_ifu_brupdate_b2_uop_lrs3, // @[core.scala:54:14]
output io_ifu_brupdate_b2_uop_ldst_val, // @[core.scala:54:14]
output [1:0] io_ifu_brupdate_b2_uop_dst_rtype, // @[core.scala:54:14]
output [1:0] io_ifu_brupdate_b2_uop_lrs1_rtype, // @[core.scala:54:14]
output [1:0] io_ifu_brupdate_b2_uop_lrs2_rtype, // @[core.scala:54:14]
output io_ifu_brupdate_b2_uop_frs3_en, // @[core.scala:54:14]
output io_ifu_brupdate_b2_uop_fp_val, // @[core.scala:54:14]
output io_ifu_brupdate_b2_uop_fp_single, // @[core.scala:54:14]
output io_ifu_brupdate_b2_uop_xcpt_pf_if, // @[core.scala:54:14]
output io_ifu_brupdate_b2_uop_xcpt_ae_if, // @[core.scala:54:14]
output io_ifu_brupdate_b2_uop_xcpt_ma_if, // @[core.scala:54:14]
output io_ifu_brupdate_b2_uop_bp_debug_if, // @[core.scala:54:14]
output io_ifu_brupdate_b2_uop_bp_xcpt_if, // @[core.scala:54:14]
output [1:0] io_ifu_brupdate_b2_uop_debug_fsrc, // @[core.scala:54:14]
output [1:0] io_ifu_brupdate_b2_uop_debug_tsrc, // @[core.scala:54:14]
output io_ifu_brupdate_b2_valid, // @[core.scala:54:14]
output io_ifu_brupdate_b2_mispredict, // @[core.scala:54:14]
output io_ifu_brupdate_b2_taken, // @[core.scala:54:14]
output [2:0] io_ifu_brupdate_b2_cfi_type, // @[core.scala:54:14]
output [1:0] io_ifu_brupdate_b2_pc_sel, // @[core.scala:54:14]
output [39:0] io_ifu_brupdate_b2_jalr_target, // @[core.scala:54:14]
output [20:0] io_ifu_brupdate_b2_target_offset, // @[core.scala:54:14]
output io_ifu_redirect_flush, // @[core.scala:54:14]
output io_ifu_redirect_val, // @[core.scala:54:14]
output [39:0] io_ifu_redirect_pc, // @[core.scala:54:14]
output [4:0] io_ifu_redirect_ftq_idx, // @[core.scala:54:14]
output [63:0] io_ifu_redirect_ghist_old_history, // @[core.scala:54:14]
output io_ifu_redirect_ghist_current_saw_branch_not_taken, // @[core.scala:54:14]
output io_ifu_redirect_ghist_new_saw_branch_not_taken, // @[core.scala:54:14]
output io_ifu_redirect_ghist_new_saw_branch_taken, // @[core.scala:54:14]
output [4:0] io_ifu_redirect_ghist_ras_idx, // @[core.scala:54:14]
output io_ifu_commit_valid, // @[core.scala:54:14]
output [31:0] io_ifu_commit_bits, // @[core.scala:54:14]
output io_ifu_flush_icache, // @[core.scala:54:14]
input io_ifu_perf_acquire, // @[core.scala:54:14]
input io_ifu_perf_tlbMiss, // @[core.scala:54:14]
output [3:0] io_ptw_ptbr_mode, // @[core.scala:54:14]
output [43:0] io_ptw_ptbr_ppn, // @[core.scala:54:14]
output io_ptw_sfence_valid, // @[core.scala:54:14]
output io_ptw_sfence_bits_rs1, // @[core.scala:54:14]
output io_ptw_sfence_bits_rs2, // @[core.scala:54:14]
output [38:0] io_ptw_sfence_bits_addr, // @[core.scala:54:14]
output io_ptw_sfence_bits_asid, // @[core.scala:54:14]
output io_ptw_status_debug, // @[core.scala:54:14]
output io_ptw_status_cease, // @[core.scala:54:14]
output io_ptw_status_wfi, // @[core.scala:54:14]
output [1:0] io_ptw_status_dprv, // @[core.scala:54:14]
output io_ptw_status_dv, // @[core.scala:54:14]
output [1:0] io_ptw_status_prv, // @[core.scala:54:14]
output io_ptw_status_v, // @[core.scala:54:14]
output io_ptw_status_sd, // @[core.scala:54:14]
output io_ptw_status_mpv, // @[core.scala:54:14]
output io_ptw_status_gva, // @[core.scala:54:14]
output io_ptw_status_tsr, // @[core.scala:54:14]
output io_ptw_status_tw, // @[core.scala:54:14]
output io_ptw_status_tvm, // @[core.scala:54:14]
output io_ptw_status_mxr, // @[core.scala:54:14]
output io_ptw_status_sum, // @[core.scala:54:14]
output io_ptw_status_mprv, // @[core.scala:54:14]
output [1:0] io_ptw_status_fs, // @[core.scala:54:14]
output [1:0] io_ptw_status_mpp, // @[core.scala:54:14]
output io_ptw_status_spp, // @[core.scala:54:14]
output io_ptw_status_mpie, // @[core.scala:54:14]
output io_ptw_status_spie, // @[core.scala:54:14]
output io_ptw_status_mie, // @[core.scala:54:14]
output io_ptw_status_sie, // @[core.scala:54:14]
output io_ptw_pmp_0_cfg_l, // @[core.scala:54:14]
output [1:0] io_ptw_pmp_0_cfg_a, // @[core.scala:54:14]
output io_ptw_pmp_0_cfg_x, // @[core.scala:54:14]
output io_ptw_pmp_0_cfg_w, // @[core.scala:54:14]
output io_ptw_pmp_0_cfg_r, // @[core.scala:54:14]
output [29:0] io_ptw_pmp_0_addr, // @[core.scala:54:14]
output [31:0] io_ptw_pmp_0_mask, // @[core.scala:54:14]
output io_ptw_pmp_1_cfg_l, // @[core.scala:54:14]
output [1:0] io_ptw_pmp_1_cfg_a, // @[core.scala:54:14]
output io_ptw_pmp_1_cfg_x, // @[core.scala:54:14]
output io_ptw_pmp_1_cfg_w, // @[core.scala:54:14]
output io_ptw_pmp_1_cfg_r, // @[core.scala:54:14]
output [29:0] io_ptw_pmp_1_addr, // @[core.scala:54:14]
output [31:0] io_ptw_pmp_1_mask, // @[core.scala:54:14]
output io_ptw_pmp_2_cfg_l, // @[core.scala:54:14]
output [1:0] io_ptw_pmp_2_cfg_a, // @[core.scala:54:14]
output io_ptw_pmp_2_cfg_x, // @[core.scala:54:14]
output io_ptw_pmp_2_cfg_w, // @[core.scala:54:14]
output io_ptw_pmp_2_cfg_r, // @[core.scala:54:14]
output [29:0] io_ptw_pmp_2_addr, // @[core.scala:54:14]
output [31:0] io_ptw_pmp_2_mask, // @[core.scala:54:14]
output io_ptw_pmp_3_cfg_l, // @[core.scala:54:14]
output [1:0] io_ptw_pmp_3_cfg_a, // @[core.scala:54:14]
output io_ptw_pmp_3_cfg_x, // @[core.scala:54:14]
output io_ptw_pmp_3_cfg_w, // @[core.scala:54:14]
output io_ptw_pmp_3_cfg_r, // @[core.scala:54:14]
output [29:0] io_ptw_pmp_3_addr, // @[core.scala:54:14]
output [31:0] io_ptw_pmp_3_mask, // @[core.scala:54:14]
output io_ptw_pmp_4_cfg_l, // @[core.scala:54:14]
output [1:0] io_ptw_pmp_4_cfg_a, // @[core.scala:54:14]
output io_ptw_pmp_4_cfg_x, // @[core.scala:54:14]
output io_ptw_pmp_4_cfg_w, // @[core.scala:54:14]
output io_ptw_pmp_4_cfg_r, // @[core.scala:54:14]
output [29:0] io_ptw_pmp_4_addr, // @[core.scala:54:14]
output [31:0] io_ptw_pmp_4_mask, // @[core.scala:54:14]
output io_ptw_pmp_5_cfg_l, // @[core.scala:54:14]
output [1:0] io_ptw_pmp_5_cfg_a, // @[core.scala:54:14]
output io_ptw_pmp_5_cfg_x, // @[core.scala:54:14]
output io_ptw_pmp_5_cfg_w, // @[core.scala:54:14]
output io_ptw_pmp_5_cfg_r, // @[core.scala:54:14]
output [29:0] io_ptw_pmp_5_addr, // @[core.scala:54:14]
output [31:0] io_ptw_pmp_5_mask, // @[core.scala:54:14]
output io_ptw_pmp_6_cfg_l, // @[core.scala:54:14]
output [1:0] io_ptw_pmp_6_cfg_a, // @[core.scala:54:14]
output io_ptw_pmp_6_cfg_x, // @[core.scala:54:14]
output io_ptw_pmp_6_cfg_w, // @[core.scala:54:14]
output io_ptw_pmp_6_cfg_r, // @[core.scala:54:14]
output [29:0] io_ptw_pmp_6_addr, // @[core.scala:54:14]
output [31:0] io_ptw_pmp_6_mask, // @[core.scala:54:14]
output io_ptw_pmp_7_cfg_l, // @[core.scala:54:14]
output [1:0] io_ptw_pmp_7_cfg_a, // @[core.scala:54:14]
output io_ptw_pmp_7_cfg_x, // @[core.scala:54:14]
output io_ptw_pmp_7_cfg_w, // @[core.scala:54:14]
output io_ptw_pmp_7_cfg_r, // @[core.scala:54:14]
output [29:0] io_ptw_pmp_7_addr, // @[core.scala:54:14]
output [31:0] io_ptw_pmp_7_mask, // @[core.scala:54:14]
input io_ptw_perf_l2miss, // @[core.scala:54:14]
input io_ptw_perf_l2hit, // @[core.scala:54:14]
input io_ptw_perf_pte_miss, // @[core.scala:54:14]
input io_ptw_perf_pte_hit, // @[core.scala:54:14]
input io_ptw_clock_enabled, // @[core.scala:54:14]
output io_lsu_exe_0_req_valid, // @[core.scala:54:14]
output [6:0] io_lsu_exe_0_req_bits_uop_uopc, // @[core.scala:54:14]
output [31:0] io_lsu_exe_0_req_bits_uop_inst, // @[core.scala:54:14]
output [31:0] io_lsu_exe_0_req_bits_uop_debug_inst, // @[core.scala:54:14]
output io_lsu_exe_0_req_bits_uop_is_rvc, // @[core.scala:54:14]
output [39:0] io_lsu_exe_0_req_bits_uop_debug_pc, // @[core.scala:54:14]
output [2:0] io_lsu_exe_0_req_bits_uop_iq_type, // @[core.scala:54:14]
output [9:0] io_lsu_exe_0_req_bits_uop_fu_code, // @[core.scala:54:14]
output [3:0] io_lsu_exe_0_req_bits_uop_ctrl_br_type, // @[core.scala:54:14]
output [1:0] io_lsu_exe_0_req_bits_uop_ctrl_op1_sel, // @[core.scala:54:14]
output [2:0] io_lsu_exe_0_req_bits_uop_ctrl_op2_sel, // @[core.scala:54:14]
output [2:0] io_lsu_exe_0_req_bits_uop_ctrl_imm_sel, // @[core.scala:54:14]
output [4:0] io_lsu_exe_0_req_bits_uop_ctrl_op_fcn, // @[core.scala:54:14]
output io_lsu_exe_0_req_bits_uop_ctrl_fcn_dw, // @[core.scala:54:14]
output [2:0] io_lsu_exe_0_req_bits_uop_ctrl_csr_cmd, // @[core.scala:54:14]
output io_lsu_exe_0_req_bits_uop_ctrl_is_load, // @[core.scala:54:14]
output io_lsu_exe_0_req_bits_uop_ctrl_is_sta, // @[core.scala:54:14]
output io_lsu_exe_0_req_bits_uop_ctrl_is_std, // @[core.scala:54:14]
output [1:0] io_lsu_exe_0_req_bits_uop_iw_state, // @[core.scala:54:14]
output io_lsu_exe_0_req_bits_uop_iw_p1_poisoned, // @[core.scala:54:14]
output io_lsu_exe_0_req_bits_uop_iw_p2_poisoned, // @[core.scala:54:14]
output io_lsu_exe_0_req_bits_uop_is_br, // @[core.scala:54:14]
output io_lsu_exe_0_req_bits_uop_is_jalr, // @[core.scala:54:14]
output io_lsu_exe_0_req_bits_uop_is_jal, // @[core.scala:54:14]
output io_lsu_exe_0_req_bits_uop_is_sfb, // @[core.scala:54:14]
output [15:0] io_lsu_exe_0_req_bits_uop_br_mask, // @[core.scala:54:14]
output [3:0] io_lsu_exe_0_req_bits_uop_br_tag, // @[core.scala:54:14]
output [4:0] io_lsu_exe_0_req_bits_uop_ftq_idx, // @[core.scala:54:14]
output io_lsu_exe_0_req_bits_uop_edge_inst, // @[core.scala:54:14]
output [5:0] io_lsu_exe_0_req_bits_uop_pc_lob, // @[core.scala:54:14]
output io_lsu_exe_0_req_bits_uop_taken, // @[core.scala:54:14]
output [19:0] io_lsu_exe_0_req_bits_uop_imm_packed, // @[core.scala:54:14]
output [11:0] io_lsu_exe_0_req_bits_uop_csr_addr, // @[core.scala:54:14]
output [6:0] io_lsu_exe_0_req_bits_uop_rob_idx, // @[core.scala:54:14]
output [4:0] io_lsu_exe_0_req_bits_uop_ldq_idx, // @[core.scala:54:14]
output [4:0] io_lsu_exe_0_req_bits_uop_stq_idx, // @[core.scala:54:14]
output [1:0] io_lsu_exe_0_req_bits_uop_rxq_idx, // @[core.scala:54:14]
output [6:0] io_lsu_exe_0_req_bits_uop_pdst, // @[core.scala:54:14]
output [6:0] io_lsu_exe_0_req_bits_uop_prs1, // @[core.scala:54:14]
output [6:0] io_lsu_exe_0_req_bits_uop_prs2, // @[core.scala:54:14]
output [6:0] io_lsu_exe_0_req_bits_uop_prs3, // @[core.scala:54:14]
output [4:0] io_lsu_exe_0_req_bits_uop_ppred, // @[core.scala:54:14]
output io_lsu_exe_0_req_bits_uop_prs1_busy, // @[core.scala:54:14]
output io_lsu_exe_0_req_bits_uop_prs2_busy, // @[core.scala:54:14]
output io_lsu_exe_0_req_bits_uop_prs3_busy, // @[core.scala:54:14]
output io_lsu_exe_0_req_bits_uop_ppred_busy, // @[core.scala:54:14]
output [6:0] io_lsu_exe_0_req_bits_uop_stale_pdst, // @[core.scala:54:14]
output io_lsu_exe_0_req_bits_uop_exception, // @[core.scala:54:14]
output [63:0] io_lsu_exe_0_req_bits_uop_exc_cause, // @[core.scala:54:14]
output io_lsu_exe_0_req_bits_uop_bypassable, // @[core.scala:54:14]
output [4:0] io_lsu_exe_0_req_bits_uop_mem_cmd, // @[core.scala:54:14]
output [1:0] io_lsu_exe_0_req_bits_uop_mem_size, // @[core.scala:54:14]
output io_lsu_exe_0_req_bits_uop_mem_signed, // @[core.scala:54:14]
output io_lsu_exe_0_req_bits_uop_is_fence, // @[core.scala:54:14]
output io_lsu_exe_0_req_bits_uop_is_fencei, // @[core.scala:54:14]
output io_lsu_exe_0_req_bits_uop_is_amo, // @[core.scala:54:14]
output io_lsu_exe_0_req_bits_uop_uses_ldq, // @[core.scala:54:14]
output io_lsu_exe_0_req_bits_uop_uses_stq, // @[core.scala:54:14]
output io_lsu_exe_0_req_bits_uop_is_sys_pc2epc, // @[core.scala:54:14]
output io_lsu_exe_0_req_bits_uop_is_unique, // @[core.scala:54:14]
output io_lsu_exe_0_req_bits_uop_flush_on_commit, // @[core.scala:54:14]
output io_lsu_exe_0_req_bits_uop_ldst_is_rs1, // @[core.scala:54:14]
output [5:0] io_lsu_exe_0_req_bits_uop_ldst, // @[core.scala:54:14]
output [5:0] io_lsu_exe_0_req_bits_uop_lrs1, // @[core.scala:54:14]
output [5:0] io_lsu_exe_0_req_bits_uop_lrs2, // @[core.scala:54:14]
output [5:0] io_lsu_exe_0_req_bits_uop_lrs3, // @[core.scala:54:14]
output io_lsu_exe_0_req_bits_uop_ldst_val, // @[core.scala:54:14]
output [1:0] io_lsu_exe_0_req_bits_uop_dst_rtype, // @[core.scala:54:14]
output [1:0] io_lsu_exe_0_req_bits_uop_lrs1_rtype, // @[core.scala:54:14]
output [1:0] io_lsu_exe_0_req_bits_uop_lrs2_rtype, // @[core.scala:54:14]
output io_lsu_exe_0_req_bits_uop_frs3_en, // @[core.scala:54:14]
output io_lsu_exe_0_req_bits_uop_fp_val, // @[core.scala:54:14]
output io_lsu_exe_0_req_bits_uop_fp_single, // @[core.scala:54:14]
output io_lsu_exe_0_req_bits_uop_xcpt_pf_if, // @[core.scala:54:14]
output io_lsu_exe_0_req_bits_uop_xcpt_ae_if, // @[core.scala:54:14]
output io_lsu_exe_0_req_bits_uop_xcpt_ma_if, // @[core.scala:54:14]
output io_lsu_exe_0_req_bits_uop_bp_debug_if, // @[core.scala:54:14]
output io_lsu_exe_0_req_bits_uop_bp_xcpt_if, // @[core.scala:54:14]
output [1:0] io_lsu_exe_0_req_bits_uop_debug_fsrc, // @[core.scala:54:14]
output [1:0] io_lsu_exe_0_req_bits_uop_debug_tsrc, // @[core.scala:54:14]
output [63:0] io_lsu_exe_0_req_bits_data, // @[core.scala:54:14]
output [39:0] io_lsu_exe_0_req_bits_addr, // @[core.scala:54:14]
output io_lsu_exe_0_req_bits_mxcpt_valid, // @[core.scala:54:14]
output [24:0] io_lsu_exe_0_req_bits_mxcpt_bits, // @[core.scala:54:14]
output io_lsu_exe_0_req_bits_sfence_valid, // @[core.scala:54:14]
output io_lsu_exe_0_req_bits_sfence_bits_rs1, // @[core.scala:54:14]
output io_lsu_exe_0_req_bits_sfence_bits_rs2, // @[core.scala:54:14]
output [38:0] io_lsu_exe_0_req_bits_sfence_bits_addr, // @[core.scala:54:14]
output io_lsu_exe_0_req_bits_sfence_bits_asid, // @[core.scala:54:14]
input io_lsu_exe_0_iresp_valid, // @[core.scala:54:14]
input [6:0] io_lsu_exe_0_iresp_bits_uop_uopc, // @[core.scala:54:14]
input [31:0] io_lsu_exe_0_iresp_bits_uop_inst, // @[core.scala:54:14]
input [31:0] io_lsu_exe_0_iresp_bits_uop_debug_inst, // @[core.scala:54:14]
input io_lsu_exe_0_iresp_bits_uop_is_rvc, // @[core.scala:54:14]
input [39:0] io_lsu_exe_0_iresp_bits_uop_debug_pc, // @[core.scala:54:14]
input [2:0] io_lsu_exe_0_iresp_bits_uop_iq_type, // @[core.scala:54:14]
input [9:0] io_lsu_exe_0_iresp_bits_uop_fu_code, // @[core.scala:54:14]
input [3:0] io_lsu_exe_0_iresp_bits_uop_ctrl_br_type, // @[core.scala:54:14]
input [1:0] io_lsu_exe_0_iresp_bits_uop_ctrl_op1_sel, // @[core.scala:54:14]
input [2:0] io_lsu_exe_0_iresp_bits_uop_ctrl_op2_sel, // @[core.scala:54:14]
input [2:0] io_lsu_exe_0_iresp_bits_uop_ctrl_imm_sel, // @[core.scala:54:14]
input [4:0] io_lsu_exe_0_iresp_bits_uop_ctrl_op_fcn, // @[core.scala:54:14]
input io_lsu_exe_0_iresp_bits_uop_ctrl_fcn_dw, // @[core.scala:54:14]
input [2:0] io_lsu_exe_0_iresp_bits_uop_ctrl_csr_cmd, // @[core.scala:54:14]
input io_lsu_exe_0_iresp_bits_uop_ctrl_is_load, // @[core.scala:54:14]
input io_lsu_exe_0_iresp_bits_uop_ctrl_is_sta, // @[core.scala:54:14]
input io_lsu_exe_0_iresp_bits_uop_ctrl_is_std, // @[core.scala:54:14]
input [1:0] io_lsu_exe_0_iresp_bits_uop_iw_state, // @[core.scala:54:14]
input io_lsu_exe_0_iresp_bits_uop_iw_p1_poisoned, // @[core.scala:54:14]
input io_lsu_exe_0_iresp_bits_uop_iw_p2_poisoned, // @[core.scala:54:14]
input io_lsu_exe_0_iresp_bits_uop_is_br, // @[core.scala:54:14]
input io_lsu_exe_0_iresp_bits_uop_is_jalr, // @[core.scala:54:14]
input io_lsu_exe_0_iresp_bits_uop_is_jal, // @[core.scala:54:14]
input io_lsu_exe_0_iresp_bits_uop_is_sfb, // @[core.scala:54:14]
input [15:0] io_lsu_exe_0_iresp_bits_uop_br_mask, // @[core.scala:54:14]
input [3:0] io_lsu_exe_0_iresp_bits_uop_br_tag, // @[core.scala:54:14]
input [4:0] io_lsu_exe_0_iresp_bits_uop_ftq_idx, // @[core.scala:54:14]
input io_lsu_exe_0_iresp_bits_uop_edge_inst, // @[core.scala:54:14]
input [5:0] io_lsu_exe_0_iresp_bits_uop_pc_lob, // @[core.scala:54:14]
input io_lsu_exe_0_iresp_bits_uop_taken, // @[core.scala:54:14]
input [19:0] io_lsu_exe_0_iresp_bits_uop_imm_packed, // @[core.scala:54:14]
input [11:0] io_lsu_exe_0_iresp_bits_uop_csr_addr, // @[core.scala:54:14]
input [6:0] io_lsu_exe_0_iresp_bits_uop_rob_idx, // @[core.scala:54:14]
input [4:0] io_lsu_exe_0_iresp_bits_uop_ldq_idx, // @[core.scala:54:14]
input [4:0] io_lsu_exe_0_iresp_bits_uop_stq_idx, // @[core.scala:54:14]
input [1:0] io_lsu_exe_0_iresp_bits_uop_rxq_idx, // @[core.scala:54:14]
input [6:0] io_lsu_exe_0_iresp_bits_uop_pdst, // @[core.scala:54:14]
input [6:0] io_lsu_exe_0_iresp_bits_uop_prs1, // @[core.scala:54:14]
input [6:0] io_lsu_exe_0_iresp_bits_uop_prs2, // @[core.scala:54:14]
input [6:0] io_lsu_exe_0_iresp_bits_uop_prs3, // @[core.scala:54:14]
input [4:0] io_lsu_exe_0_iresp_bits_uop_ppred, // @[core.scala:54:14]
input io_lsu_exe_0_iresp_bits_uop_prs1_busy, // @[core.scala:54:14]
input io_lsu_exe_0_iresp_bits_uop_prs2_busy, // @[core.scala:54:14]
input io_lsu_exe_0_iresp_bits_uop_prs3_busy, // @[core.scala:54:14]
input io_lsu_exe_0_iresp_bits_uop_ppred_busy, // @[core.scala:54:14]
input [6:0] io_lsu_exe_0_iresp_bits_uop_stale_pdst, // @[core.scala:54:14]
input io_lsu_exe_0_iresp_bits_uop_exception, // @[core.scala:54:14]
input [63:0] io_lsu_exe_0_iresp_bits_uop_exc_cause, // @[core.scala:54:14]
input io_lsu_exe_0_iresp_bits_uop_bypassable, // @[core.scala:54:14]
input [4:0] io_lsu_exe_0_iresp_bits_uop_mem_cmd, // @[core.scala:54:14]
input [1:0] io_lsu_exe_0_iresp_bits_uop_mem_size, // @[core.scala:54:14]
input io_lsu_exe_0_iresp_bits_uop_mem_signed, // @[core.scala:54:14]
input io_lsu_exe_0_iresp_bits_uop_is_fence, // @[core.scala:54:14]
input io_lsu_exe_0_iresp_bits_uop_is_fencei, // @[core.scala:54:14]
input io_lsu_exe_0_iresp_bits_uop_is_amo, // @[core.scala:54:14]
input io_lsu_exe_0_iresp_bits_uop_uses_ldq, // @[core.scala:54:14]
input io_lsu_exe_0_iresp_bits_uop_uses_stq, // @[core.scala:54:14]
input io_lsu_exe_0_iresp_bits_uop_is_sys_pc2epc, // @[core.scala:54:14]
input io_lsu_exe_0_iresp_bits_uop_is_unique, // @[core.scala:54:14]
input io_lsu_exe_0_iresp_bits_uop_flush_on_commit, // @[core.scala:54:14]
input io_lsu_exe_0_iresp_bits_uop_ldst_is_rs1, // @[core.scala:54:14]
input [5:0] io_lsu_exe_0_iresp_bits_uop_ldst, // @[core.scala:54:14]
input [5:0] io_lsu_exe_0_iresp_bits_uop_lrs1, // @[core.scala:54:14]
input [5:0] io_lsu_exe_0_iresp_bits_uop_lrs2, // @[core.scala:54:14]
input [5:0] io_lsu_exe_0_iresp_bits_uop_lrs3, // @[core.scala:54:14]
input io_lsu_exe_0_iresp_bits_uop_ldst_val, // @[core.scala:54:14]
input [1:0] io_lsu_exe_0_iresp_bits_uop_dst_rtype, // @[core.scala:54:14]
input [1:0] io_lsu_exe_0_iresp_bits_uop_lrs1_rtype, // @[core.scala:54:14]
input [1:0] io_lsu_exe_0_iresp_bits_uop_lrs2_rtype, // @[core.scala:54:14]
input io_lsu_exe_0_iresp_bits_uop_frs3_en, // @[core.scala:54:14]
input io_lsu_exe_0_iresp_bits_uop_fp_val, // @[core.scala:54:14]
input io_lsu_exe_0_iresp_bits_uop_fp_single, // @[core.scala:54:14]
input io_lsu_exe_0_iresp_bits_uop_xcpt_pf_if, // @[core.scala:54:14]
input io_lsu_exe_0_iresp_bits_uop_xcpt_ae_if, // @[core.scala:54:14]
input io_lsu_exe_0_iresp_bits_uop_xcpt_ma_if, // @[core.scala:54:14]
input io_lsu_exe_0_iresp_bits_uop_bp_debug_if, // @[core.scala:54:14]
input io_lsu_exe_0_iresp_bits_uop_bp_xcpt_if, // @[core.scala:54:14]
input [1:0] io_lsu_exe_0_iresp_bits_uop_debug_fsrc, // @[core.scala:54:14]
input [1:0] io_lsu_exe_0_iresp_bits_uop_debug_tsrc, // @[core.scala:54:14]
input [63:0] io_lsu_exe_0_iresp_bits_data, // @[core.scala:54:14]
input io_lsu_exe_0_fresp_valid, // @[core.scala:54:14]
input [6:0] io_lsu_exe_0_fresp_bits_uop_uopc, // @[core.scala:54:14]
input [31:0] io_lsu_exe_0_fresp_bits_uop_inst, // @[core.scala:54:14]
input [31:0] io_lsu_exe_0_fresp_bits_uop_debug_inst, // @[core.scala:54:14]
input io_lsu_exe_0_fresp_bits_uop_is_rvc, // @[core.scala:54:14]
input [39:0] io_lsu_exe_0_fresp_bits_uop_debug_pc, // @[core.scala:54:14]
input [2:0] io_lsu_exe_0_fresp_bits_uop_iq_type, // @[core.scala:54:14]
input [9:0] io_lsu_exe_0_fresp_bits_uop_fu_code, // @[core.scala:54:14]
input [3:0] io_lsu_exe_0_fresp_bits_uop_ctrl_br_type, // @[core.scala:54:14]
input [1:0] io_lsu_exe_0_fresp_bits_uop_ctrl_op1_sel, // @[core.scala:54:14]
input [2:0] io_lsu_exe_0_fresp_bits_uop_ctrl_op2_sel, // @[core.scala:54:14]
input [2:0] io_lsu_exe_0_fresp_bits_uop_ctrl_imm_sel, // @[core.scala:54:14]
input [4:0] io_lsu_exe_0_fresp_bits_uop_ctrl_op_fcn, // @[core.scala:54:14]
input io_lsu_exe_0_fresp_bits_uop_ctrl_fcn_dw, // @[core.scala:54:14]
input [2:0] io_lsu_exe_0_fresp_bits_uop_ctrl_csr_cmd, // @[core.scala:54:14]
input io_lsu_exe_0_fresp_bits_uop_ctrl_is_load, // @[core.scala:54:14]
input io_lsu_exe_0_fresp_bits_uop_ctrl_is_sta, // @[core.scala:54:14]
input io_lsu_exe_0_fresp_bits_uop_ctrl_is_std, // @[core.scala:54:14]
input [1:0] io_lsu_exe_0_fresp_bits_uop_iw_state, // @[core.scala:54:14]
input io_lsu_exe_0_fresp_bits_uop_iw_p1_poisoned, // @[core.scala:54:14]
input io_lsu_exe_0_fresp_bits_uop_iw_p2_poisoned, // @[core.scala:54:14]
input io_lsu_exe_0_fresp_bits_uop_is_br, // @[core.scala:54:14]
input io_lsu_exe_0_fresp_bits_uop_is_jalr, // @[core.scala:54:14]
input io_lsu_exe_0_fresp_bits_uop_is_jal, // @[core.scala:54:14]
input io_lsu_exe_0_fresp_bits_uop_is_sfb, // @[core.scala:54:14]
input [15:0] io_lsu_exe_0_fresp_bits_uop_br_mask, // @[core.scala:54:14]
input [3:0] io_lsu_exe_0_fresp_bits_uop_br_tag, // @[core.scala:54:14]
input [4:0] io_lsu_exe_0_fresp_bits_uop_ftq_idx, // @[core.scala:54:14]
input io_lsu_exe_0_fresp_bits_uop_edge_inst, // @[core.scala:54:14]
input [5:0] io_lsu_exe_0_fresp_bits_uop_pc_lob, // @[core.scala:54:14]
input io_lsu_exe_0_fresp_bits_uop_taken, // @[core.scala:54:14]
input [19:0] io_lsu_exe_0_fresp_bits_uop_imm_packed, // @[core.scala:54:14]
input [11:0] io_lsu_exe_0_fresp_bits_uop_csr_addr, // @[core.scala:54:14]
input [6:0] io_lsu_exe_0_fresp_bits_uop_rob_idx, // @[core.scala:54:14]
input [4:0] io_lsu_exe_0_fresp_bits_uop_ldq_idx, // @[core.scala:54:14]
input [4:0] io_lsu_exe_0_fresp_bits_uop_stq_idx, // @[core.scala:54:14]
input [1:0] io_lsu_exe_0_fresp_bits_uop_rxq_idx, // @[core.scala:54:14]
input [6:0] io_lsu_exe_0_fresp_bits_uop_pdst, // @[core.scala:54:14]
input [6:0] io_lsu_exe_0_fresp_bits_uop_prs1, // @[core.scala:54:14]
input [6:0] io_lsu_exe_0_fresp_bits_uop_prs2, // @[core.scala:54:14]
input [6:0] io_lsu_exe_0_fresp_bits_uop_prs3, // @[core.scala:54:14]
input [4:0] io_lsu_exe_0_fresp_bits_uop_ppred, // @[core.scala:54:14]
input io_lsu_exe_0_fresp_bits_uop_prs1_busy, // @[core.scala:54:14]
input io_lsu_exe_0_fresp_bits_uop_prs2_busy, // @[core.scala:54:14]
input io_lsu_exe_0_fresp_bits_uop_prs3_busy, // @[core.scala:54:14]
input io_lsu_exe_0_fresp_bits_uop_ppred_busy, // @[core.scala:54:14]
input [6:0] io_lsu_exe_0_fresp_bits_uop_stale_pdst, // @[core.scala:54:14]
input io_lsu_exe_0_fresp_bits_uop_exception, // @[core.scala:54:14]
input [63:0] io_lsu_exe_0_fresp_bits_uop_exc_cause, // @[core.scala:54:14]
input io_lsu_exe_0_fresp_bits_uop_bypassable, // @[core.scala:54:14]
input [4:0] io_lsu_exe_0_fresp_bits_uop_mem_cmd, // @[core.scala:54:14]
input [1:0] io_lsu_exe_0_fresp_bits_uop_mem_size, // @[core.scala:54:14]
input io_lsu_exe_0_fresp_bits_uop_mem_signed, // @[core.scala:54:14]
input io_lsu_exe_0_fresp_bits_uop_is_fence, // @[core.scala:54:14]
input io_lsu_exe_0_fresp_bits_uop_is_fencei, // @[core.scala:54:14]
input io_lsu_exe_0_fresp_bits_uop_is_amo, // @[core.scala:54:14]
input io_lsu_exe_0_fresp_bits_uop_uses_ldq, // @[core.scala:54:14]
input io_lsu_exe_0_fresp_bits_uop_uses_stq, // @[core.scala:54:14]
input io_lsu_exe_0_fresp_bits_uop_is_sys_pc2epc, // @[core.scala:54:14]
input io_lsu_exe_0_fresp_bits_uop_is_unique, // @[core.scala:54:14]
input io_lsu_exe_0_fresp_bits_uop_flush_on_commit, // @[core.scala:54:14]
input io_lsu_exe_0_fresp_bits_uop_ldst_is_rs1, // @[core.scala:54:14]
input [5:0] io_lsu_exe_0_fresp_bits_uop_ldst, // @[core.scala:54:14]
input [5:0] io_lsu_exe_0_fresp_bits_uop_lrs1, // @[core.scala:54:14]
input [5:0] io_lsu_exe_0_fresp_bits_uop_lrs2, // @[core.scala:54:14]
input [5:0] io_lsu_exe_0_fresp_bits_uop_lrs3, // @[core.scala:54:14]
input io_lsu_exe_0_fresp_bits_uop_ldst_val, // @[core.scala:54:14]
input [1:0] io_lsu_exe_0_fresp_bits_uop_dst_rtype, // @[core.scala:54:14]
input [1:0] io_lsu_exe_0_fresp_bits_uop_lrs1_rtype, // @[core.scala:54:14]
input [1:0] io_lsu_exe_0_fresp_bits_uop_lrs2_rtype, // @[core.scala:54:14]
input io_lsu_exe_0_fresp_bits_uop_frs3_en, // @[core.scala:54:14]
input io_lsu_exe_0_fresp_bits_uop_fp_val, // @[core.scala:54:14]
input io_lsu_exe_0_fresp_bits_uop_fp_single, // @[core.scala:54:14]
input io_lsu_exe_0_fresp_bits_uop_xcpt_pf_if, // @[core.scala:54:14]
input io_lsu_exe_0_fresp_bits_uop_xcpt_ae_if, // @[core.scala:54:14]
input io_lsu_exe_0_fresp_bits_uop_xcpt_ma_if, // @[core.scala:54:14]
input io_lsu_exe_0_fresp_bits_uop_bp_debug_if, // @[core.scala:54:14]
input io_lsu_exe_0_fresp_bits_uop_bp_xcpt_if, // @[core.scala:54:14]
input [1:0] io_lsu_exe_0_fresp_bits_uop_debug_fsrc, // @[core.scala:54:14]
input [1:0] io_lsu_exe_0_fresp_bits_uop_debug_tsrc, // @[core.scala:54:14]
input [64:0] io_lsu_exe_0_fresp_bits_data, // @[core.scala:54:14]
output io_lsu_dis_uops_0_valid, // @[core.scala:54:14]
output [6:0] io_lsu_dis_uops_0_bits_uopc, // @[core.scala:54:14]
output [31:0] io_lsu_dis_uops_0_bits_inst, // @[core.scala:54:14]
output [31:0] io_lsu_dis_uops_0_bits_debug_inst, // @[core.scala:54:14]
output io_lsu_dis_uops_0_bits_is_rvc, // @[core.scala:54:14]
output [39:0] io_lsu_dis_uops_0_bits_debug_pc, // @[core.scala:54:14]
output [2:0] io_lsu_dis_uops_0_bits_iq_type, // @[core.scala:54:14]
output [9:0] io_lsu_dis_uops_0_bits_fu_code, // @[core.scala:54:14]
output [3:0] io_lsu_dis_uops_0_bits_ctrl_br_type, // @[core.scala:54:14]
output [1:0] io_lsu_dis_uops_0_bits_ctrl_op1_sel, // @[core.scala:54:14]
output [2:0] io_lsu_dis_uops_0_bits_ctrl_op2_sel, // @[core.scala:54:14]
output [2:0] io_lsu_dis_uops_0_bits_ctrl_imm_sel, // @[core.scala:54:14]
output [4:0] io_lsu_dis_uops_0_bits_ctrl_op_fcn, // @[core.scala:54:14]
output io_lsu_dis_uops_0_bits_ctrl_fcn_dw, // @[core.scala:54:14]
output [2:0] io_lsu_dis_uops_0_bits_ctrl_csr_cmd, // @[core.scala:54:14]
output io_lsu_dis_uops_0_bits_ctrl_is_load, // @[core.scala:54:14]
output io_lsu_dis_uops_0_bits_ctrl_is_sta, // @[core.scala:54:14]
output io_lsu_dis_uops_0_bits_ctrl_is_std, // @[core.scala:54:14]
output [1:0] io_lsu_dis_uops_0_bits_iw_state, // @[core.scala:54:14]
output io_lsu_dis_uops_0_bits_iw_p1_poisoned, // @[core.scala:54:14]
output io_lsu_dis_uops_0_bits_iw_p2_poisoned, // @[core.scala:54:14]
output io_lsu_dis_uops_0_bits_is_br, // @[core.scala:54:14]
output io_lsu_dis_uops_0_bits_is_jalr, // @[core.scala:54:14]
output io_lsu_dis_uops_0_bits_is_jal, // @[core.scala:54:14]
output io_lsu_dis_uops_0_bits_is_sfb, // @[core.scala:54:14]
output [15:0] io_lsu_dis_uops_0_bits_br_mask, // @[core.scala:54:14]
output [3:0] io_lsu_dis_uops_0_bits_br_tag, // @[core.scala:54:14]
output [4:0] io_lsu_dis_uops_0_bits_ftq_idx, // @[core.scala:54:14]
output io_lsu_dis_uops_0_bits_edge_inst, // @[core.scala:54:14]
output [5:0] io_lsu_dis_uops_0_bits_pc_lob, // @[core.scala:54:14]
output io_lsu_dis_uops_0_bits_taken, // @[core.scala:54:14]
output [19:0] io_lsu_dis_uops_0_bits_imm_packed, // @[core.scala:54:14]
output [11:0] io_lsu_dis_uops_0_bits_csr_addr, // @[core.scala:54:14]
output [6:0] io_lsu_dis_uops_0_bits_rob_idx, // @[core.scala:54:14]
output [4:0] io_lsu_dis_uops_0_bits_ldq_idx, // @[core.scala:54:14]
output [4:0] io_lsu_dis_uops_0_bits_stq_idx, // @[core.scala:54:14]
output [1:0] io_lsu_dis_uops_0_bits_rxq_idx, // @[core.scala:54:14]
output [6:0] io_lsu_dis_uops_0_bits_pdst, // @[core.scala:54:14]
output [6:0] io_lsu_dis_uops_0_bits_prs1, // @[core.scala:54:14]
output [6:0] io_lsu_dis_uops_0_bits_prs2, // @[core.scala:54:14]
output [6:0] io_lsu_dis_uops_0_bits_prs3, // @[core.scala:54:14]
output io_lsu_dis_uops_0_bits_prs1_busy, // @[core.scala:54:14]
output io_lsu_dis_uops_0_bits_prs2_busy, // @[core.scala:54:14]
output io_lsu_dis_uops_0_bits_prs3_busy, // @[core.scala:54:14]
output [6:0] io_lsu_dis_uops_0_bits_stale_pdst, // @[core.scala:54:14]
output io_lsu_dis_uops_0_bits_exception, // @[core.scala:54:14]
output [63:0] io_lsu_dis_uops_0_bits_exc_cause, // @[core.scala:54:14]
output io_lsu_dis_uops_0_bits_bypassable, // @[core.scala:54:14]
output [4:0] io_lsu_dis_uops_0_bits_mem_cmd, // @[core.scala:54:14]
output [1:0] io_lsu_dis_uops_0_bits_mem_size, // @[core.scala:54:14]
output io_lsu_dis_uops_0_bits_mem_signed, // @[core.scala:54:14]
output io_lsu_dis_uops_0_bits_is_fence, // @[core.scala:54:14]
output io_lsu_dis_uops_0_bits_is_fencei, // @[core.scala:54:14]
output io_lsu_dis_uops_0_bits_is_amo, // @[core.scala:54:14]
output io_lsu_dis_uops_0_bits_uses_ldq, // @[core.scala:54:14]
output io_lsu_dis_uops_0_bits_uses_stq, // @[core.scala:54:14]
output io_lsu_dis_uops_0_bits_is_sys_pc2epc, // @[core.scala:54:14]
output io_lsu_dis_uops_0_bits_is_unique, // @[core.scala:54:14]
output io_lsu_dis_uops_0_bits_flush_on_commit, // @[core.scala:54:14]
output io_lsu_dis_uops_0_bits_ldst_is_rs1, // @[core.scala:54:14]
output [5:0] io_lsu_dis_uops_0_bits_ldst, // @[core.scala:54:14]
output [5:0] io_lsu_dis_uops_0_bits_lrs1, // @[core.scala:54:14]
output [5:0] io_lsu_dis_uops_0_bits_lrs2, // @[core.scala:54:14]
output [5:0] io_lsu_dis_uops_0_bits_lrs3, // @[core.scala:54:14]
output io_lsu_dis_uops_0_bits_ldst_val, // @[core.scala:54:14]
output [1:0] io_lsu_dis_uops_0_bits_dst_rtype, // @[core.scala:54:14]
output [1:0] io_lsu_dis_uops_0_bits_lrs1_rtype, // @[core.scala:54:14]
output [1:0] io_lsu_dis_uops_0_bits_lrs2_rtype, // @[core.scala:54:14]
output io_lsu_dis_uops_0_bits_frs3_en, // @[core.scala:54:14]
output io_lsu_dis_uops_0_bits_fp_val, // @[core.scala:54:14]
output io_lsu_dis_uops_0_bits_fp_single, // @[core.scala:54:14]
output io_lsu_dis_uops_0_bits_xcpt_pf_if, // @[core.scala:54:14]
output io_lsu_dis_uops_0_bits_xcpt_ae_if, // @[core.scala:54:14]
output io_lsu_dis_uops_0_bits_xcpt_ma_if, // @[core.scala:54:14]
output io_lsu_dis_uops_0_bits_bp_debug_if, // @[core.scala:54:14]
output io_lsu_dis_uops_0_bits_bp_xcpt_if, // @[core.scala:54:14]
output [1:0] io_lsu_dis_uops_0_bits_debug_fsrc, // @[core.scala:54:14]
output [1:0] io_lsu_dis_uops_0_bits_debug_tsrc, // @[core.scala:54:14]
output io_lsu_dis_uops_1_valid, // @[core.scala:54:14]
output [6:0] io_lsu_dis_uops_1_bits_uopc, // @[core.scala:54:14]
output [31:0] io_lsu_dis_uops_1_bits_inst, // @[core.scala:54:14]
output [31:0] io_lsu_dis_uops_1_bits_debug_inst, // @[core.scala:54:14]
output io_lsu_dis_uops_1_bits_is_rvc, // @[core.scala:54:14]
output [39:0] io_lsu_dis_uops_1_bits_debug_pc, // @[core.scala:54:14]
output [2:0] io_lsu_dis_uops_1_bits_iq_type, // @[core.scala:54:14]
output [9:0] io_lsu_dis_uops_1_bits_fu_code, // @[core.scala:54:14]
output [3:0] io_lsu_dis_uops_1_bits_ctrl_br_type, // @[core.scala:54:14]
output [1:0] io_lsu_dis_uops_1_bits_ctrl_op1_sel, // @[core.scala:54:14]
output [2:0] io_lsu_dis_uops_1_bits_ctrl_op2_sel, // @[core.scala:54:14]
output [2:0] io_lsu_dis_uops_1_bits_ctrl_imm_sel, // @[core.scala:54:14]
output [4:0] io_lsu_dis_uops_1_bits_ctrl_op_fcn, // @[core.scala:54:14]
output io_lsu_dis_uops_1_bits_ctrl_fcn_dw, // @[core.scala:54:14]
output [2:0] io_lsu_dis_uops_1_bits_ctrl_csr_cmd, // @[core.scala:54:14]
output io_lsu_dis_uops_1_bits_ctrl_is_load, // @[core.scala:54:14]
output io_lsu_dis_uops_1_bits_ctrl_is_sta, // @[core.scala:54:14]
output io_lsu_dis_uops_1_bits_ctrl_is_std, // @[core.scala:54:14]
output [1:0] io_lsu_dis_uops_1_bits_iw_state, // @[core.scala:54:14]
output io_lsu_dis_uops_1_bits_iw_p1_poisoned, // @[core.scala:54:14]
output io_lsu_dis_uops_1_bits_iw_p2_poisoned, // @[core.scala:54:14]
output io_lsu_dis_uops_1_bits_is_br, // @[core.scala:54:14]
output io_lsu_dis_uops_1_bits_is_jalr, // @[core.scala:54:14]
output io_lsu_dis_uops_1_bits_is_jal, // @[core.scala:54:14]
output io_lsu_dis_uops_1_bits_is_sfb, // @[core.scala:54:14]
output [15:0] io_lsu_dis_uops_1_bits_br_mask, // @[core.scala:54:14]
output [3:0] io_lsu_dis_uops_1_bits_br_tag, // @[core.scala:54:14]
output [4:0] io_lsu_dis_uops_1_bits_ftq_idx, // @[core.scala:54:14]
output io_lsu_dis_uops_1_bits_edge_inst, // @[core.scala:54:14]
output [5:0] io_lsu_dis_uops_1_bits_pc_lob, // @[core.scala:54:14]
output io_lsu_dis_uops_1_bits_taken, // @[core.scala:54:14]
output [19:0] io_lsu_dis_uops_1_bits_imm_packed, // @[core.scala:54:14]
output [11:0] io_lsu_dis_uops_1_bits_csr_addr, // @[core.scala:54:14]
output [6:0] io_lsu_dis_uops_1_bits_rob_idx, // @[core.scala:54:14]
output [4:0] io_lsu_dis_uops_1_bits_ldq_idx, // @[core.scala:54:14]
output [4:0] io_lsu_dis_uops_1_bits_stq_idx, // @[core.scala:54:14]
output [1:0] io_lsu_dis_uops_1_bits_rxq_idx, // @[core.scala:54:14]
output [6:0] io_lsu_dis_uops_1_bits_pdst, // @[core.scala:54:14]
output [6:0] io_lsu_dis_uops_1_bits_prs1, // @[core.scala:54:14]
output [6:0] io_lsu_dis_uops_1_bits_prs2, // @[core.scala:54:14]
output [6:0] io_lsu_dis_uops_1_bits_prs3, // @[core.scala:54:14]
output io_lsu_dis_uops_1_bits_prs1_busy, // @[core.scala:54:14]
output io_lsu_dis_uops_1_bits_prs2_busy, // @[core.scala:54:14]
output io_lsu_dis_uops_1_bits_prs3_busy, // @[core.scala:54:14]
output [6:0] io_lsu_dis_uops_1_bits_stale_pdst, // @[core.scala:54:14]
output io_lsu_dis_uops_1_bits_exception, // @[core.scala:54:14]
output [63:0] io_lsu_dis_uops_1_bits_exc_cause, // @[core.scala:54:14]
output io_lsu_dis_uops_1_bits_bypassable, // @[core.scala:54:14]
output [4:0] io_lsu_dis_uops_1_bits_mem_cmd, // @[core.scala:54:14]
output [1:0] io_lsu_dis_uops_1_bits_mem_size, // @[core.scala:54:14]
output io_lsu_dis_uops_1_bits_mem_signed, // @[core.scala:54:14]
output io_lsu_dis_uops_1_bits_is_fence, // @[core.scala:54:14]
output io_lsu_dis_uops_1_bits_is_fencei, // @[core.scala:54:14]
output io_lsu_dis_uops_1_bits_is_amo, // @[core.scala:54:14]
output io_lsu_dis_uops_1_bits_uses_ldq, // @[core.scala:54:14]
output io_lsu_dis_uops_1_bits_uses_stq, // @[core.scala:54:14]
output io_lsu_dis_uops_1_bits_is_sys_pc2epc, // @[core.scala:54:14]
output io_lsu_dis_uops_1_bits_is_unique, // @[core.scala:54:14]
output io_lsu_dis_uops_1_bits_flush_on_commit, // @[core.scala:54:14]
output io_lsu_dis_uops_1_bits_ldst_is_rs1, // @[core.scala:54:14]
output [5:0] io_lsu_dis_uops_1_bits_ldst, // @[core.scala:54:14]
output [5:0] io_lsu_dis_uops_1_bits_lrs1, // @[core.scala:54:14]
output [5:0] io_lsu_dis_uops_1_bits_lrs2, // @[core.scala:54:14]
output [5:0] io_lsu_dis_uops_1_bits_lrs3, // @[core.scala:54:14]
output io_lsu_dis_uops_1_bits_ldst_val, // @[core.scala:54:14]
output [1:0] io_lsu_dis_uops_1_bits_dst_rtype, // @[core.scala:54:14]
output [1:0] io_lsu_dis_uops_1_bits_lrs1_rtype, // @[core.scala:54:14]
output [1:0] io_lsu_dis_uops_1_bits_lrs2_rtype, // @[core.scala:54:14]
output io_lsu_dis_uops_1_bits_frs3_en, // @[core.scala:54:14]
output io_lsu_dis_uops_1_bits_fp_val, // @[core.scala:54:14]
output io_lsu_dis_uops_1_bits_fp_single, // @[core.scala:54:14]
output io_lsu_dis_uops_1_bits_xcpt_pf_if, // @[core.scala:54:14]
output io_lsu_dis_uops_1_bits_xcpt_ae_if, // @[core.scala:54:14]
output io_lsu_dis_uops_1_bits_xcpt_ma_if, // @[core.scala:54:14]
output io_lsu_dis_uops_1_bits_bp_debug_if, // @[core.scala:54:14]
output io_lsu_dis_uops_1_bits_bp_xcpt_if, // @[core.scala:54:14]
output [1:0] io_lsu_dis_uops_1_bits_debug_fsrc, // @[core.scala:54:14]
output [1:0] io_lsu_dis_uops_1_bits_debug_tsrc, // @[core.scala:54:14]
output io_lsu_dis_uops_2_valid, // @[core.scala:54:14]
output [6:0] io_lsu_dis_uops_2_bits_uopc, // @[core.scala:54:14]
output [31:0] io_lsu_dis_uops_2_bits_inst, // @[core.scala:54:14]
output [31:0] io_lsu_dis_uops_2_bits_debug_inst, // @[core.scala:54:14]
output io_lsu_dis_uops_2_bits_is_rvc, // @[core.scala:54:14]
output [39:0] io_lsu_dis_uops_2_bits_debug_pc, // @[core.scala:54:14]
output [2:0] io_lsu_dis_uops_2_bits_iq_type, // @[core.scala:54:14]
output [9:0] io_lsu_dis_uops_2_bits_fu_code, // @[core.scala:54:14]
output [3:0] io_lsu_dis_uops_2_bits_ctrl_br_type, // @[core.scala:54:14]
output [1:0] io_lsu_dis_uops_2_bits_ctrl_op1_sel, // @[core.scala:54:14]
output [2:0] io_lsu_dis_uops_2_bits_ctrl_op2_sel, // @[core.scala:54:14]
output [2:0] io_lsu_dis_uops_2_bits_ctrl_imm_sel, // @[core.scala:54:14]
output [4:0] io_lsu_dis_uops_2_bits_ctrl_op_fcn, // @[core.scala:54:14]
output io_lsu_dis_uops_2_bits_ctrl_fcn_dw, // @[core.scala:54:14]
output [2:0] io_lsu_dis_uops_2_bits_ctrl_csr_cmd, // @[core.scala:54:14]
output io_lsu_dis_uops_2_bits_ctrl_is_load, // @[core.scala:54:14]
output io_lsu_dis_uops_2_bits_ctrl_is_sta, // @[core.scala:54:14]
output io_lsu_dis_uops_2_bits_ctrl_is_std, // @[core.scala:54:14]
output [1:0] io_lsu_dis_uops_2_bits_iw_state, // @[core.scala:54:14]
output io_lsu_dis_uops_2_bits_iw_p1_poisoned, // @[core.scala:54:14]
output io_lsu_dis_uops_2_bits_iw_p2_poisoned, // @[core.scala:54:14]
output io_lsu_dis_uops_2_bits_is_br, // @[core.scala:54:14]
output io_lsu_dis_uops_2_bits_is_jalr, // @[core.scala:54:14]
output io_lsu_dis_uops_2_bits_is_jal, // @[core.scala:54:14]
output io_lsu_dis_uops_2_bits_is_sfb, // @[core.scala:54:14]
output [15:0] io_lsu_dis_uops_2_bits_br_mask, // @[core.scala:54:14]
output [3:0] io_lsu_dis_uops_2_bits_br_tag, // @[core.scala:54:14]
output [4:0] io_lsu_dis_uops_2_bits_ftq_idx, // @[core.scala:54:14]
output io_lsu_dis_uops_2_bits_edge_inst, // @[core.scala:54:14]
output [5:0] io_lsu_dis_uops_2_bits_pc_lob, // @[core.scala:54:14]
output io_lsu_dis_uops_2_bits_taken, // @[core.scala:54:14]
output [19:0] io_lsu_dis_uops_2_bits_imm_packed, // @[core.scala:54:14]
output [11:0] io_lsu_dis_uops_2_bits_csr_addr, // @[core.scala:54:14]
output [6:0] io_lsu_dis_uops_2_bits_rob_idx, // @[core.scala:54:14]
output [4:0] io_lsu_dis_uops_2_bits_ldq_idx, // @[core.scala:54:14]
output [4:0] io_lsu_dis_uops_2_bits_stq_idx, // @[core.scala:54:14]
output [1:0] io_lsu_dis_uops_2_bits_rxq_idx, // @[core.scala:54:14]
output [6:0] io_lsu_dis_uops_2_bits_pdst, // @[core.scala:54:14]
output [6:0] io_lsu_dis_uops_2_bits_prs1, // @[core.scala:54:14]
output [6:0] io_lsu_dis_uops_2_bits_prs2, // @[core.scala:54:14]
output [6:0] io_lsu_dis_uops_2_bits_prs3, // @[core.scala:54:14]
output io_lsu_dis_uops_2_bits_prs1_busy, // @[core.scala:54:14]
output io_lsu_dis_uops_2_bits_prs2_busy, // @[core.scala:54:14]
output io_lsu_dis_uops_2_bits_prs3_busy, // @[core.scala:54:14]
output [6:0] io_lsu_dis_uops_2_bits_stale_pdst, // @[core.scala:54:14]
output io_lsu_dis_uops_2_bits_exception, // @[core.scala:54:14]
output [63:0] io_lsu_dis_uops_2_bits_exc_cause, // @[core.scala:54:14]
output io_lsu_dis_uops_2_bits_bypassable, // @[core.scala:54:14]
output [4:0] io_lsu_dis_uops_2_bits_mem_cmd, // @[core.scala:54:14]
output [1:0] io_lsu_dis_uops_2_bits_mem_size, // @[core.scala:54:14]
output io_lsu_dis_uops_2_bits_mem_signed, // @[core.scala:54:14]
output io_lsu_dis_uops_2_bits_is_fence, // @[core.scala:54:14]
output io_lsu_dis_uops_2_bits_is_fencei, // @[core.scala:54:14]
output io_lsu_dis_uops_2_bits_is_amo, // @[core.scala:54:14]
output io_lsu_dis_uops_2_bits_uses_ldq, // @[core.scala:54:14]
output io_lsu_dis_uops_2_bits_uses_stq, // @[core.scala:54:14]
output io_lsu_dis_uops_2_bits_is_sys_pc2epc, // @[core.scala:54:14]
output io_lsu_dis_uops_2_bits_is_unique, // @[core.scala:54:14]
output io_lsu_dis_uops_2_bits_flush_on_commit, // @[core.scala:54:14]
output io_lsu_dis_uops_2_bits_ldst_is_rs1, // @[core.scala:54:14]
output [5:0] io_lsu_dis_uops_2_bits_ldst, // @[core.scala:54:14]
output [5:0] io_lsu_dis_uops_2_bits_lrs1, // @[core.scala:54:14]
output [5:0] io_lsu_dis_uops_2_bits_lrs2, // @[core.scala:54:14]
output [5:0] io_lsu_dis_uops_2_bits_lrs3, // @[core.scala:54:14]
output io_lsu_dis_uops_2_bits_ldst_val, // @[core.scala:54:14]
output [1:0] io_lsu_dis_uops_2_bits_dst_rtype, // @[core.scala:54:14]
output [1:0] io_lsu_dis_uops_2_bits_lrs1_rtype, // @[core.scala:54:14]
output [1:0] io_lsu_dis_uops_2_bits_lrs2_rtype, // @[core.scala:54:14]
output io_lsu_dis_uops_2_bits_frs3_en, // @[core.scala:54:14]
output io_lsu_dis_uops_2_bits_fp_val, // @[core.scala:54:14]
output io_lsu_dis_uops_2_bits_fp_single, // @[core.scala:54:14]
output io_lsu_dis_uops_2_bits_xcpt_pf_if, // @[core.scala:54:14]
output io_lsu_dis_uops_2_bits_xcpt_ae_if, // @[core.scala:54:14]
output io_lsu_dis_uops_2_bits_xcpt_ma_if, // @[core.scala:54:14]
output io_lsu_dis_uops_2_bits_bp_debug_if, // @[core.scala:54:14]
output io_lsu_dis_uops_2_bits_bp_xcpt_if, // @[core.scala:54:14]
output [1:0] io_lsu_dis_uops_2_bits_debug_fsrc, // @[core.scala:54:14]
output [1:0] io_lsu_dis_uops_2_bits_debug_tsrc, // @[core.scala:54:14]
input [4:0] io_lsu_dis_ldq_idx_0, // @[core.scala:54:14]
input [4:0] io_lsu_dis_ldq_idx_1, // @[core.scala:54:14]
input [4:0] io_lsu_dis_ldq_idx_2, // @[core.scala:54:14]
input [4:0] io_lsu_dis_stq_idx_0, // @[core.scala:54:14]
input [4:0] io_lsu_dis_stq_idx_1, // @[core.scala:54:14]
input [4:0] io_lsu_dis_stq_idx_2, // @[core.scala:54:14]
input io_lsu_ldq_full_0, // @[core.scala:54:14]
input io_lsu_ldq_full_1, // @[core.scala:54:14]
input io_lsu_ldq_full_2, // @[core.scala:54:14]
input io_lsu_stq_full_0, // @[core.scala:54:14]
input io_lsu_stq_full_1, // @[core.scala:54:14]
input io_lsu_stq_full_2, // @[core.scala:54:14]
input io_lsu_fp_stdata_ready, // @[core.scala:54:14]
output io_lsu_fp_stdata_valid, // @[core.scala:54:14]
output [6:0] io_lsu_fp_stdata_bits_uop_uopc, // @[core.scala:54:14]
output [31:0] io_lsu_fp_stdata_bits_uop_inst, // @[core.scala:54:14]
output [31:0] io_lsu_fp_stdata_bits_uop_debug_inst, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_uop_is_rvc, // @[core.scala:54:14]
output [39:0] io_lsu_fp_stdata_bits_uop_debug_pc, // @[core.scala:54:14]
output [2:0] io_lsu_fp_stdata_bits_uop_iq_type, // @[core.scala:54:14]
output [9:0] io_lsu_fp_stdata_bits_uop_fu_code, // @[core.scala:54:14]
output [3:0] io_lsu_fp_stdata_bits_uop_ctrl_br_type, // @[core.scala:54:14]
output [1:0] io_lsu_fp_stdata_bits_uop_ctrl_op1_sel, // @[core.scala:54:14]
output [2:0] io_lsu_fp_stdata_bits_uop_ctrl_op2_sel, // @[core.scala:54:14]
output [2:0] io_lsu_fp_stdata_bits_uop_ctrl_imm_sel, // @[core.scala:54:14]
output [4:0] io_lsu_fp_stdata_bits_uop_ctrl_op_fcn, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_uop_ctrl_fcn_dw, // @[core.scala:54:14]
output [2:0] io_lsu_fp_stdata_bits_uop_ctrl_csr_cmd, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_uop_ctrl_is_load, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_uop_ctrl_is_sta, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_uop_ctrl_is_std, // @[core.scala:54:14]
output [1:0] io_lsu_fp_stdata_bits_uop_iw_state, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_uop_iw_p1_poisoned, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_uop_iw_p2_poisoned, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_uop_is_br, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_uop_is_jalr, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_uop_is_jal, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_uop_is_sfb, // @[core.scala:54:14]
output [15:0] io_lsu_fp_stdata_bits_uop_br_mask, // @[core.scala:54:14]
output [3:0] io_lsu_fp_stdata_bits_uop_br_tag, // @[core.scala:54:14]
output [4:0] io_lsu_fp_stdata_bits_uop_ftq_idx, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_uop_edge_inst, // @[core.scala:54:14]
output [5:0] io_lsu_fp_stdata_bits_uop_pc_lob, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_uop_taken, // @[core.scala:54:14]
output [19:0] io_lsu_fp_stdata_bits_uop_imm_packed, // @[core.scala:54:14]
output [11:0] io_lsu_fp_stdata_bits_uop_csr_addr, // @[core.scala:54:14]
output [6:0] io_lsu_fp_stdata_bits_uop_rob_idx, // @[core.scala:54:14]
output [4:0] io_lsu_fp_stdata_bits_uop_ldq_idx, // @[core.scala:54:14]
output [4:0] io_lsu_fp_stdata_bits_uop_stq_idx, // @[core.scala:54:14]
output [1:0] io_lsu_fp_stdata_bits_uop_rxq_idx, // @[core.scala:54:14]
output [6:0] io_lsu_fp_stdata_bits_uop_pdst, // @[core.scala:54:14]
output [6:0] io_lsu_fp_stdata_bits_uop_prs1, // @[core.scala:54:14]
output [6:0] io_lsu_fp_stdata_bits_uop_prs2, // @[core.scala:54:14]
output [6:0] io_lsu_fp_stdata_bits_uop_prs3, // @[core.scala:54:14]
output [4:0] io_lsu_fp_stdata_bits_uop_ppred, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_uop_prs1_busy, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_uop_prs2_busy, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_uop_prs3_busy, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_uop_ppred_busy, // @[core.scala:54:14]
output [6:0] io_lsu_fp_stdata_bits_uop_stale_pdst, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_uop_exception, // @[core.scala:54:14]
output [63:0] io_lsu_fp_stdata_bits_uop_exc_cause, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_uop_bypassable, // @[core.scala:54:14]
output [4:0] io_lsu_fp_stdata_bits_uop_mem_cmd, // @[core.scala:54:14]
output [1:0] io_lsu_fp_stdata_bits_uop_mem_size, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_uop_mem_signed, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_uop_is_fence, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_uop_is_fencei, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_uop_is_amo, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_uop_uses_ldq, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_uop_uses_stq, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_uop_is_sys_pc2epc, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_uop_is_unique, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_uop_flush_on_commit, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_uop_ldst_is_rs1, // @[core.scala:54:14]
output [5:0] io_lsu_fp_stdata_bits_uop_ldst, // @[core.scala:54:14]
output [5:0] io_lsu_fp_stdata_bits_uop_lrs1, // @[core.scala:54:14]
output [5:0] io_lsu_fp_stdata_bits_uop_lrs2, // @[core.scala:54:14]
output [5:0] io_lsu_fp_stdata_bits_uop_lrs3, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_uop_ldst_val, // @[core.scala:54:14]
output [1:0] io_lsu_fp_stdata_bits_uop_dst_rtype, // @[core.scala:54:14]
output [1:0] io_lsu_fp_stdata_bits_uop_lrs1_rtype, // @[core.scala:54:14]
output [1:0] io_lsu_fp_stdata_bits_uop_lrs2_rtype, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_uop_frs3_en, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_uop_fp_val, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_uop_fp_single, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_uop_xcpt_pf_if, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_uop_xcpt_ae_if, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_uop_xcpt_ma_if, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_uop_bp_debug_if, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_uop_bp_xcpt_if, // @[core.scala:54:14]
output [1:0] io_lsu_fp_stdata_bits_uop_debug_fsrc, // @[core.scala:54:14]
output [1:0] io_lsu_fp_stdata_bits_uop_debug_tsrc, // @[core.scala:54:14]
output [63:0] io_lsu_fp_stdata_bits_data, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_predicated, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_fflags_valid, // @[core.scala:54:14]
output [6:0] io_lsu_fp_stdata_bits_fflags_bits_uop_uopc, // @[core.scala:54:14]
output [31:0] io_lsu_fp_stdata_bits_fflags_bits_uop_inst, // @[core.scala:54:14]
output [31:0] io_lsu_fp_stdata_bits_fflags_bits_uop_debug_inst, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_fflags_bits_uop_is_rvc, // @[core.scala:54:14]
output [39:0] io_lsu_fp_stdata_bits_fflags_bits_uop_debug_pc, // @[core.scala:54:14]
output [2:0] io_lsu_fp_stdata_bits_fflags_bits_uop_iq_type, // @[core.scala:54:14]
output [9:0] io_lsu_fp_stdata_bits_fflags_bits_uop_fu_code, // @[core.scala:54:14]
output [3:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_br_type, // @[core.scala:54:14]
output [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_op1_sel, // @[core.scala:54:14]
output [2:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_op2_sel, // @[core.scala:54:14]
output [2:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_imm_sel, // @[core.scala:54:14]
output [4:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_op_fcn, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_fcn_dw, // @[core.scala:54:14]
output [2:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_csr_cmd, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_is_load, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_is_sta, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_is_std, // @[core.scala:54:14]
output [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_iw_state, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_fflags_bits_uop_iw_p1_poisoned, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_fflags_bits_uop_iw_p2_poisoned, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_fflags_bits_uop_is_br, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_fflags_bits_uop_is_jalr, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_fflags_bits_uop_is_jal, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_fflags_bits_uop_is_sfb, // @[core.scala:54:14]
output [15:0] io_lsu_fp_stdata_bits_fflags_bits_uop_br_mask, // @[core.scala:54:14]
output [3:0] io_lsu_fp_stdata_bits_fflags_bits_uop_br_tag, // @[core.scala:54:14]
output [4:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ftq_idx, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_fflags_bits_uop_edge_inst, // @[core.scala:54:14]
output [5:0] io_lsu_fp_stdata_bits_fflags_bits_uop_pc_lob, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_fflags_bits_uop_taken, // @[core.scala:54:14]
output [19:0] io_lsu_fp_stdata_bits_fflags_bits_uop_imm_packed, // @[core.scala:54:14]
output [11:0] io_lsu_fp_stdata_bits_fflags_bits_uop_csr_addr, // @[core.scala:54:14]
output [6:0] io_lsu_fp_stdata_bits_fflags_bits_uop_rob_idx, // @[core.scala:54:14]
output [4:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ldq_idx, // @[core.scala:54:14]
output [4:0] io_lsu_fp_stdata_bits_fflags_bits_uop_stq_idx, // @[core.scala:54:14]
output [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_rxq_idx, // @[core.scala:54:14]
output [6:0] io_lsu_fp_stdata_bits_fflags_bits_uop_pdst, // @[core.scala:54:14]
output [6:0] io_lsu_fp_stdata_bits_fflags_bits_uop_prs1, // @[core.scala:54:14]
output [6:0] io_lsu_fp_stdata_bits_fflags_bits_uop_prs2, // @[core.scala:54:14]
output [6:0] io_lsu_fp_stdata_bits_fflags_bits_uop_prs3, // @[core.scala:54:14]
output [4:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ppred, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_fflags_bits_uop_prs1_busy, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_fflags_bits_uop_prs2_busy, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_fflags_bits_uop_prs3_busy, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_fflags_bits_uop_ppred_busy, // @[core.scala:54:14]
output [6:0] io_lsu_fp_stdata_bits_fflags_bits_uop_stale_pdst, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_fflags_bits_uop_exception, // @[core.scala:54:14]
output [63:0] io_lsu_fp_stdata_bits_fflags_bits_uop_exc_cause, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_fflags_bits_uop_bypassable, // @[core.scala:54:14]
output [4:0] io_lsu_fp_stdata_bits_fflags_bits_uop_mem_cmd, // @[core.scala:54:14]
output [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_mem_size, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_fflags_bits_uop_mem_signed, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_fflags_bits_uop_is_fence, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_fflags_bits_uop_is_fencei, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_fflags_bits_uop_is_amo, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_fflags_bits_uop_uses_ldq, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_fflags_bits_uop_uses_stq, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_fflags_bits_uop_is_sys_pc2epc, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_fflags_bits_uop_is_unique, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_fflags_bits_uop_flush_on_commit, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_fflags_bits_uop_ldst_is_rs1, // @[core.scala:54:14]
output [5:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ldst, // @[core.scala:54:14]
output [5:0] io_lsu_fp_stdata_bits_fflags_bits_uop_lrs1, // @[core.scala:54:14]
output [5:0] io_lsu_fp_stdata_bits_fflags_bits_uop_lrs2, // @[core.scala:54:14]
output [5:0] io_lsu_fp_stdata_bits_fflags_bits_uop_lrs3, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_fflags_bits_uop_ldst_val, // @[core.scala:54:14]
output [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_dst_rtype, // @[core.scala:54:14]
output [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_lrs1_rtype, // @[core.scala:54:14]
output [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_lrs2_rtype, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_fflags_bits_uop_frs3_en, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_fflags_bits_uop_fp_val, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_fflags_bits_uop_fp_single, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_fflags_bits_uop_xcpt_pf_if, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_fflags_bits_uop_xcpt_ae_if, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_fflags_bits_uop_xcpt_ma_if, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_fflags_bits_uop_bp_debug_if, // @[core.scala:54:14]
output io_lsu_fp_stdata_bits_fflags_bits_uop_bp_xcpt_if, // @[core.scala:54:14]
output [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_debug_fsrc, // @[core.scala:54:14]
output [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_debug_tsrc, // @[core.scala:54:14]
output [4:0] io_lsu_fp_stdata_bits_fflags_bits_flags, // @[core.scala:54:14]
output io_lsu_commit_valids_0, // @[core.scala:54:14]
output io_lsu_commit_valids_1, // @[core.scala:54:14]
output io_lsu_commit_valids_2, // @[core.scala:54:14]
output io_lsu_commit_arch_valids_0, // @[core.scala:54:14]
output io_lsu_commit_arch_valids_1, // @[core.scala:54:14]
output io_lsu_commit_arch_valids_2, // @[core.scala:54:14]
output [6:0] io_lsu_commit_uops_0_uopc, // @[core.scala:54:14]
output [31:0] io_lsu_commit_uops_0_inst, // @[core.scala:54:14]
output [31:0] io_lsu_commit_uops_0_debug_inst, // @[core.scala:54:14]
output io_lsu_commit_uops_0_is_rvc, // @[core.scala:54:14]
output [39:0] io_lsu_commit_uops_0_debug_pc, // @[core.scala:54:14]
output [2:0] io_lsu_commit_uops_0_iq_type, // @[core.scala:54:14]
output [9:0] io_lsu_commit_uops_0_fu_code, // @[core.scala:54:14]
output [3:0] io_lsu_commit_uops_0_ctrl_br_type, // @[core.scala:54:14]
output [1:0] io_lsu_commit_uops_0_ctrl_op1_sel, // @[core.scala:54:14]
output [2:0] io_lsu_commit_uops_0_ctrl_op2_sel, // @[core.scala:54:14]
output [2:0] io_lsu_commit_uops_0_ctrl_imm_sel, // @[core.scala:54:14]
output [4:0] io_lsu_commit_uops_0_ctrl_op_fcn, // @[core.scala:54:14]
output io_lsu_commit_uops_0_ctrl_fcn_dw, // @[core.scala:54:14]
output [2:0] io_lsu_commit_uops_0_ctrl_csr_cmd, // @[core.scala:54:14]
output io_lsu_commit_uops_0_ctrl_is_load, // @[core.scala:54:14]
output io_lsu_commit_uops_0_ctrl_is_sta, // @[core.scala:54:14]
output io_lsu_commit_uops_0_ctrl_is_std, // @[core.scala:54:14]
output [1:0] io_lsu_commit_uops_0_iw_state, // @[core.scala:54:14]
output io_lsu_commit_uops_0_iw_p1_poisoned, // @[core.scala:54:14]
output io_lsu_commit_uops_0_iw_p2_poisoned, // @[core.scala:54:14]
output io_lsu_commit_uops_0_is_br, // @[core.scala:54:14]
output io_lsu_commit_uops_0_is_jalr, // @[core.scala:54:14]
output io_lsu_commit_uops_0_is_jal, // @[core.scala:54:14]
output io_lsu_commit_uops_0_is_sfb, // @[core.scala:54:14]
output [15:0] io_lsu_commit_uops_0_br_mask, // @[core.scala:54:14]
output [3:0] io_lsu_commit_uops_0_br_tag, // @[core.scala:54:14]
output [4:0] io_lsu_commit_uops_0_ftq_idx, // @[core.scala:54:14]
output io_lsu_commit_uops_0_edge_inst, // @[core.scala:54:14]
output [5:0] io_lsu_commit_uops_0_pc_lob, // @[core.scala:54:14]
output io_lsu_commit_uops_0_taken, // @[core.scala:54:14]
output [19:0] io_lsu_commit_uops_0_imm_packed, // @[core.scala:54:14]
output [11:0] io_lsu_commit_uops_0_csr_addr, // @[core.scala:54:14]
output [6:0] io_lsu_commit_uops_0_rob_idx, // @[core.scala:54:14]
output [4:0] io_lsu_commit_uops_0_ldq_idx, // @[core.scala:54:14]
output [4:0] io_lsu_commit_uops_0_stq_idx, // @[core.scala:54:14]
output [1:0] io_lsu_commit_uops_0_rxq_idx, // @[core.scala:54:14]
output [6:0] io_lsu_commit_uops_0_pdst, // @[core.scala:54:14]
output [6:0] io_lsu_commit_uops_0_prs1, // @[core.scala:54:14]
output [6:0] io_lsu_commit_uops_0_prs2, // @[core.scala:54:14]
output [6:0] io_lsu_commit_uops_0_prs3, // @[core.scala:54:14]
output [4:0] io_lsu_commit_uops_0_ppred, // @[core.scala:54:14]
output io_lsu_commit_uops_0_prs1_busy, // @[core.scala:54:14]
output io_lsu_commit_uops_0_prs2_busy, // @[core.scala:54:14]
output io_lsu_commit_uops_0_prs3_busy, // @[core.scala:54:14]
output io_lsu_commit_uops_0_ppred_busy, // @[core.scala:54:14]
output [6:0] io_lsu_commit_uops_0_stale_pdst, // @[core.scala:54:14]
output io_lsu_commit_uops_0_exception, // @[core.scala:54:14]
output [63:0] io_lsu_commit_uops_0_exc_cause, // @[core.scala:54:14]
output io_lsu_commit_uops_0_bypassable, // @[core.scala:54:14]
output [4:0] io_lsu_commit_uops_0_mem_cmd, // @[core.scala:54:14]
output [1:0] io_lsu_commit_uops_0_mem_size, // @[core.scala:54:14]
output io_lsu_commit_uops_0_mem_signed, // @[core.scala:54:14]
output io_lsu_commit_uops_0_is_fence, // @[core.scala:54:14]
output io_lsu_commit_uops_0_is_fencei, // @[core.scala:54:14]
output io_lsu_commit_uops_0_is_amo, // @[core.scala:54:14]
output io_lsu_commit_uops_0_uses_ldq, // @[core.scala:54:14]
output io_lsu_commit_uops_0_uses_stq, // @[core.scala:54:14]
output io_lsu_commit_uops_0_is_sys_pc2epc, // @[core.scala:54:14]
output io_lsu_commit_uops_0_is_unique, // @[core.scala:54:14]
output io_lsu_commit_uops_0_flush_on_commit, // @[core.scala:54:14]
output io_lsu_commit_uops_0_ldst_is_rs1, // @[core.scala:54:14]
output [5:0] io_lsu_commit_uops_0_ldst, // @[core.scala:54:14]
output [5:0] io_lsu_commit_uops_0_lrs1, // @[core.scala:54:14]
output [5:0] io_lsu_commit_uops_0_lrs2, // @[core.scala:54:14]
output [5:0] io_lsu_commit_uops_0_lrs3, // @[core.scala:54:14]
output io_lsu_commit_uops_0_ldst_val, // @[core.scala:54:14]
output [1:0] io_lsu_commit_uops_0_dst_rtype, // @[core.scala:54:14]
output [1:0] io_lsu_commit_uops_0_lrs1_rtype, // @[core.scala:54:14]
output [1:0] io_lsu_commit_uops_0_lrs2_rtype, // @[core.scala:54:14]
output io_lsu_commit_uops_0_frs3_en, // @[core.scala:54:14]
output io_lsu_commit_uops_0_fp_val, // @[core.scala:54:14]
output io_lsu_commit_uops_0_fp_single, // @[core.scala:54:14]
output io_lsu_commit_uops_0_xcpt_pf_if, // @[core.scala:54:14]
output io_lsu_commit_uops_0_xcpt_ae_if, // @[core.scala:54:14]
output io_lsu_commit_uops_0_xcpt_ma_if, // @[core.scala:54:14]
output io_lsu_commit_uops_0_bp_debug_if, // @[core.scala:54:14]
output io_lsu_commit_uops_0_bp_xcpt_if, // @[core.scala:54:14]
output [1:0] io_lsu_commit_uops_0_debug_fsrc, // @[core.scala:54:14]
output [1:0] io_lsu_commit_uops_0_debug_tsrc, // @[core.scala:54:14]
output [6:0] io_lsu_commit_uops_1_uopc, // @[core.scala:54:14]
output [31:0] io_lsu_commit_uops_1_inst, // @[core.scala:54:14]
output [31:0] io_lsu_commit_uops_1_debug_inst, // @[core.scala:54:14]
output io_lsu_commit_uops_1_is_rvc, // @[core.scala:54:14]
output [39:0] io_lsu_commit_uops_1_debug_pc, // @[core.scala:54:14]
output [2:0] io_lsu_commit_uops_1_iq_type, // @[core.scala:54:14]
output [9:0] io_lsu_commit_uops_1_fu_code, // @[core.scala:54:14]
output [3:0] io_lsu_commit_uops_1_ctrl_br_type, // @[core.scala:54:14]
output [1:0] io_lsu_commit_uops_1_ctrl_op1_sel, // @[core.scala:54:14]
output [2:0] io_lsu_commit_uops_1_ctrl_op2_sel, // @[core.scala:54:14]
output [2:0] io_lsu_commit_uops_1_ctrl_imm_sel, // @[core.scala:54:14]
output [4:0] io_lsu_commit_uops_1_ctrl_op_fcn, // @[core.scala:54:14]
output io_lsu_commit_uops_1_ctrl_fcn_dw, // @[core.scala:54:14]
output [2:0] io_lsu_commit_uops_1_ctrl_csr_cmd, // @[core.scala:54:14]
output io_lsu_commit_uops_1_ctrl_is_load, // @[core.scala:54:14]
output io_lsu_commit_uops_1_ctrl_is_sta, // @[core.scala:54:14]
output io_lsu_commit_uops_1_ctrl_is_std, // @[core.scala:54:14]
output [1:0] io_lsu_commit_uops_1_iw_state, // @[core.scala:54:14]
output io_lsu_commit_uops_1_iw_p1_poisoned, // @[core.scala:54:14]
output io_lsu_commit_uops_1_iw_p2_poisoned, // @[core.scala:54:14]
output io_lsu_commit_uops_1_is_br, // @[core.scala:54:14]
output io_lsu_commit_uops_1_is_jalr, // @[core.scala:54:14]
output io_lsu_commit_uops_1_is_jal, // @[core.scala:54:14]
output io_lsu_commit_uops_1_is_sfb, // @[core.scala:54:14]
output [15:0] io_lsu_commit_uops_1_br_mask, // @[core.scala:54:14]
output [3:0] io_lsu_commit_uops_1_br_tag, // @[core.scala:54:14]
output [4:0] io_lsu_commit_uops_1_ftq_idx, // @[core.scala:54:14]
output io_lsu_commit_uops_1_edge_inst, // @[core.scala:54:14]
output [5:0] io_lsu_commit_uops_1_pc_lob, // @[core.scala:54:14]
output io_lsu_commit_uops_1_taken, // @[core.scala:54:14]
output [19:0] io_lsu_commit_uops_1_imm_packed, // @[core.scala:54:14]
output [11:0] io_lsu_commit_uops_1_csr_addr, // @[core.scala:54:14]
output [6:0] io_lsu_commit_uops_1_rob_idx, // @[core.scala:54:14]
output [4:0] io_lsu_commit_uops_1_ldq_idx, // @[core.scala:54:14]
output [4:0] io_lsu_commit_uops_1_stq_idx, // @[core.scala:54:14]
output [1:0] io_lsu_commit_uops_1_rxq_idx, // @[core.scala:54:14]
output [6:0] io_lsu_commit_uops_1_pdst, // @[core.scala:54:14]
output [6:0] io_lsu_commit_uops_1_prs1, // @[core.scala:54:14]
output [6:0] io_lsu_commit_uops_1_prs2, // @[core.scala:54:14]
output [6:0] io_lsu_commit_uops_1_prs3, // @[core.scala:54:14]
output [4:0] io_lsu_commit_uops_1_ppred, // @[core.scala:54:14]
output io_lsu_commit_uops_1_prs1_busy, // @[core.scala:54:14]
output io_lsu_commit_uops_1_prs2_busy, // @[core.scala:54:14]
output io_lsu_commit_uops_1_prs3_busy, // @[core.scala:54:14]
output io_lsu_commit_uops_1_ppred_busy, // @[core.scala:54:14]
output [6:0] io_lsu_commit_uops_1_stale_pdst, // @[core.scala:54:14]
output io_lsu_commit_uops_1_exception, // @[core.scala:54:14]
output [63:0] io_lsu_commit_uops_1_exc_cause, // @[core.scala:54:14]
output io_lsu_commit_uops_1_bypassable, // @[core.scala:54:14]
output [4:0] io_lsu_commit_uops_1_mem_cmd, // @[core.scala:54:14]
output [1:0] io_lsu_commit_uops_1_mem_size, // @[core.scala:54:14]
output io_lsu_commit_uops_1_mem_signed, // @[core.scala:54:14]
output io_lsu_commit_uops_1_is_fence, // @[core.scala:54:14]
output io_lsu_commit_uops_1_is_fencei, // @[core.scala:54:14]
output io_lsu_commit_uops_1_is_amo, // @[core.scala:54:14]
output io_lsu_commit_uops_1_uses_ldq, // @[core.scala:54:14]
output io_lsu_commit_uops_1_uses_stq, // @[core.scala:54:14]
output io_lsu_commit_uops_1_is_sys_pc2epc, // @[core.scala:54:14]
output io_lsu_commit_uops_1_is_unique, // @[core.scala:54:14]
output io_lsu_commit_uops_1_flush_on_commit, // @[core.scala:54:14]
output io_lsu_commit_uops_1_ldst_is_rs1, // @[core.scala:54:14]
output [5:0] io_lsu_commit_uops_1_ldst, // @[core.scala:54:14]
output [5:0] io_lsu_commit_uops_1_lrs1, // @[core.scala:54:14]
output [5:0] io_lsu_commit_uops_1_lrs2, // @[core.scala:54:14]
output [5:0] io_lsu_commit_uops_1_lrs3, // @[core.scala:54:14]
output io_lsu_commit_uops_1_ldst_val, // @[core.scala:54:14]
output [1:0] io_lsu_commit_uops_1_dst_rtype, // @[core.scala:54:14]
output [1:0] io_lsu_commit_uops_1_lrs1_rtype, // @[core.scala:54:14]
output [1:0] io_lsu_commit_uops_1_lrs2_rtype, // @[core.scala:54:14]
output io_lsu_commit_uops_1_frs3_en, // @[core.scala:54:14]
output io_lsu_commit_uops_1_fp_val, // @[core.scala:54:14]
output io_lsu_commit_uops_1_fp_single, // @[core.scala:54:14]
output io_lsu_commit_uops_1_xcpt_pf_if, // @[core.scala:54:14]
output io_lsu_commit_uops_1_xcpt_ae_if, // @[core.scala:54:14]
output io_lsu_commit_uops_1_xcpt_ma_if, // @[core.scala:54:14]
output io_lsu_commit_uops_1_bp_debug_if, // @[core.scala:54:14]
output io_lsu_commit_uops_1_bp_xcpt_if, // @[core.scala:54:14]
output [1:0] io_lsu_commit_uops_1_debug_fsrc, // @[core.scala:54:14]
output [1:0] io_lsu_commit_uops_1_debug_tsrc, // @[core.scala:54:14]
output [6:0] io_lsu_commit_uops_2_uopc, // @[core.scala:54:14]
output [31:0] io_lsu_commit_uops_2_inst, // @[core.scala:54:14]
output [31:0] io_lsu_commit_uops_2_debug_inst, // @[core.scala:54:14]
output io_lsu_commit_uops_2_is_rvc, // @[core.scala:54:14]
output [39:0] io_lsu_commit_uops_2_debug_pc, // @[core.scala:54:14]
output [2:0] io_lsu_commit_uops_2_iq_type, // @[core.scala:54:14]
output [9:0] io_lsu_commit_uops_2_fu_code, // @[core.scala:54:14]
output [3:0] io_lsu_commit_uops_2_ctrl_br_type, // @[core.scala:54:14]
output [1:0] io_lsu_commit_uops_2_ctrl_op1_sel, // @[core.scala:54:14]
output [2:0] io_lsu_commit_uops_2_ctrl_op2_sel, // @[core.scala:54:14]
output [2:0] io_lsu_commit_uops_2_ctrl_imm_sel, // @[core.scala:54:14]
output [4:0] io_lsu_commit_uops_2_ctrl_op_fcn, // @[core.scala:54:14]
output io_lsu_commit_uops_2_ctrl_fcn_dw, // @[core.scala:54:14]
output [2:0] io_lsu_commit_uops_2_ctrl_csr_cmd, // @[core.scala:54:14]
output io_lsu_commit_uops_2_ctrl_is_load, // @[core.scala:54:14]
output io_lsu_commit_uops_2_ctrl_is_sta, // @[core.scala:54:14]
output io_lsu_commit_uops_2_ctrl_is_std, // @[core.scala:54:14]
output [1:0] io_lsu_commit_uops_2_iw_state, // @[core.scala:54:14]
output io_lsu_commit_uops_2_iw_p1_poisoned, // @[core.scala:54:14]
output io_lsu_commit_uops_2_iw_p2_poisoned, // @[core.scala:54:14]
output io_lsu_commit_uops_2_is_br, // @[core.scala:54:14]
output io_lsu_commit_uops_2_is_jalr, // @[core.scala:54:14]
output io_lsu_commit_uops_2_is_jal, // @[core.scala:54:14]
output io_lsu_commit_uops_2_is_sfb, // @[core.scala:54:14]
output [15:0] io_lsu_commit_uops_2_br_mask, // @[core.scala:54:14]
output [3:0] io_lsu_commit_uops_2_br_tag, // @[core.scala:54:14]
output [4:0] io_lsu_commit_uops_2_ftq_idx, // @[core.scala:54:14]
output io_lsu_commit_uops_2_edge_inst, // @[core.scala:54:14]
output [5:0] io_lsu_commit_uops_2_pc_lob, // @[core.scala:54:14]
output io_lsu_commit_uops_2_taken, // @[core.scala:54:14]
output [19:0] io_lsu_commit_uops_2_imm_packed, // @[core.scala:54:14]
output [11:0] io_lsu_commit_uops_2_csr_addr, // @[core.scala:54:14]
output [6:0] io_lsu_commit_uops_2_rob_idx, // @[core.scala:54:14]
output [4:0] io_lsu_commit_uops_2_ldq_idx, // @[core.scala:54:14]
output [4:0] io_lsu_commit_uops_2_stq_idx, // @[core.scala:54:14]
output [1:0] io_lsu_commit_uops_2_rxq_idx, // @[core.scala:54:14]
output [6:0] io_lsu_commit_uops_2_pdst, // @[core.scala:54:14]
output [6:0] io_lsu_commit_uops_2_prs1, // @[core.scala:54:14]
output [6:0] io_lsu_commit_uops_2_prs2, // @[core.scala:54:14]
output [6:0] io_lsu_commit_uops_2_prs3, // @[core.scala:54:14]
output [4:0] io_lsu_commit_uops_2_ppred, // @[core.scala:54:14]
output io_lsu_commit_uops_2_prs1_busy, // @[core.scala:54:14]
output io_lsu_commit_uops_2_prs2_busy, // @[core.scala:54:14]
output io_lsu_commit_uops_2_prs3_busy, // @[core.scala:54:14]
output io_lsu_commit_uops_2_ppred_busy, // @[core.scala:54:14]
output [6:0] io_lsu_commit_uops_2_stale_pdst, // @[core.scala:54:14]
output io_lsu_commit_uops_2_exception, // @[core.scala:54:14]
output [63:0] io_lsu_commit_uops_2_exc_cause, // @[core.scala:54:14]
output io_lsu_commit_uops_2_bypassable, // @[core.scala:54:14]
output [4:0] io_lsu_commit_uops_2_mem_cmd, // @[core.scala:54:14]
output [1:0] io_lsu_commit_uops_2_mem_size, // @[core.scala:54:14]
output io_lsu_commit_uops_2_mem_signed, // @[core.scala:54:14]
output io_lsu_commit_uops_2_is_fence, // @[core.scala:54:14]
output io_lsu_commit_uops_2_is_fencei, // @[core.scala:54:14]
output io_lsu_commit_uops_2_is_amo, // @[core.scala:54:14]
output io_lsu_commit_uops_2_uses_ldq, // @[core.scala:54:14]
output io_lsu_commit_uops_2_uses_stq, // @[core.scala:54:14]
output io_lsu_commit_uops_2_is_sys_pc2epc, // @[core.scala:54:14]
output io_lsu_commit_uops_2_is_unique, // @[core.scala:54:14]
output io_lsu_commit_uops_2_flush_on_commit, // @[core.scala:54:14]
output io_lsu_commit_uops_2_ldst_is_rs1, // @[core.scala:54:14]
output [5:0] io_lsu_commit_uops_2_ldst, // @[core.scala:54:14]
output [5:0] io_lsu_commit_uops_2_lrs1, // @[core.scala:54:14]
output [5:0] io_lsu_commit_uops_2_lrs2, // @[core.scala:54:14]
output [5:0] io_lsu_commit_uops_2_lrs3, // @[core.scala:54:14]
output io_lsu_commit_uops_2_ldst_val, // @[core.scala:54:14]
output [1:0] io_lsu_commit_uops_2_dst_rtype, // @[core.scala:54:14]
output [1:0] io_lsu_commit_uops_2_lrs1_rtype, // @[core.scala:54:14]
output [1:0] io_lsu_commit_uops_2_lrs2_rtype, // @[core.scala:54:14]
output io_lsu_commit_uops_2_frs3_en, // @[core.scala:54:14]
output io_lsu_commit_uops_2_fp_val, // @[core.scala:54:14]
output io_lsu_commit_uops_2_fp_single, // @[core.scala:54:14]
output io_lsu_commit_uops_2_xcpt_pf_if, // @[core.scala:54:14]
output io_lsu_commit_uops_2_xcpt_ae_if, // @[core.scala:54:14]
output io_lsu_commit_uops_2_xcpt_ma_if, // @[core.scala:54:14]
output io_lsu_commit_uops_2_bp_debug_if, // @[core.scala:54:14]
output io_lsu_commit_uops_2_bp_xcpt_if, // @[core.scala:54:14]
output [1:0] io_lsu_commit_uops_2_debug_fsrc, // @[core.scala:54:14]
output [1:0] io_lsu_commit_uops_2_debug_tsrc, // @[core.scala:54:14]
output io_lsu_commit_fflags_valid, // @[core.scala:54:14]
output [4:0] io_lsu_commit_fflags_bits, // @[core.scala:54:14]
output [31:0] io_lsu_commit_debug_insts_0, // @[core.scala:54:14]
output [31:0] io_lsu_commit_debug_insts_1, // @[core.scala:54:14]
output [31:0] io_lsu_commit_debug_insts_2, // @[core.scala:54:14]
output io_lsu_commit_rbk_valids_0, // @[core.scala:54:14]
output io_lsu_commit_rbk_valids_1, // @[core.scala:54:14]
output io_lsu_commit_rbk_valids_2, // @[core.scala:54:14]
output io_lsu_commit_rollback, // @[core.scala:54:14]
output [63:0] io_lsu_commit_debug_wdata_0, // @[core.scala:54:14]
output [63:0] io_lsu_commit_debug_wdata_1, // @[core.scala:54:14]
output [63:0] io_lsu_commit_debug_wdata_2, // @[core.scala:54:14]
output io_lsu_commit_load_at_rob_head, // @[core.scala:54:14]
input io_lsu_clr_bsy_0_valid, // @[core.scala:54:14]
input [6:0] io_lsu_clr_bsy_0_bits, // @[core.scala:54:14]
input io_lsu_clr_bsy_1_valid, // @[core.scala:54:14]
input [6:0] io_lsu_clr_bsy_1_bits, // @[core.scala:54:14]
input [6:0] io_lsu_clr_unsafe_0_bits, // @[core.scala:54:14]
output io_lsu_fence_dmem, // @[core.scala:54:14]
input io_lsu_spec_ld_wakeup_0_valid, // @[core.scala:54:14]
input [6:0] io_lsu_spec_ld_wakeup_0_bits, // @[core.scala:54:14]
input io_lsu_ld_miss, // @[core.scala:54:14]
output [15:0] io_lsu_brupdate_b1_resolve_mask, // @[core.scala:54:14]
output [15:0] io_lsu_brupdate_b1_mispredict_mask, // @[core.scala:54:14]
output [6:0] io_lsu_brupdate_b2_uop_uopc, // @[core.scala:54:14]
output [31:0] io_lsu_brupdate_b2_uop_inst, // @[core.scala:54:14]
output [31:0] io_lsu_brupdate_b2_uop_debug_inst, // @[core.scala:54:14]
output io_lsu_brupdate_b2_uop_is_rvc, // @[core.scala:54:14]
output [39:0] io_lsu_brupdate_b2_uop_debug_pc, // @[core.scala:54:14]
output [2:0] io_lsu_brupdate_b2_uop_iq_type, // @[core.scala:54:14]
output [9:0] io_lsu_brupdate_b2_uop_fu_code, // @[core.scala:54:14]
output [3:0] io_lsu_brupdate_b2_uop_ctrl_br_type, // @[core.scala:54:14]
output [1:0] io_lsu_brupdate_b2_uop_ctrl_op1_sel, // @[core.scala:54:14]
output [2:0] io_lsu_brupdate_b2_uop_ctrl_op2_sel, // @[core.scala:54:14]
output [2:0] io_lsu_brupdate_b2_uop_ctrl_imm_sel, // @[core.scala:54:14]
output [4:0] io_lsu_brupdate_b2_uop_ctrl_op_fcn, // @[core.scala:54:14]
output io_lsu_brupdate_b2_uop_ctrl_fcn_dw, // @[core.scala:54:14]
output [2:0] io_lsu_brupdate_b2_uop_ctrl_csr_cmd, // @[core.scala:54:14]
output io_lsu_brupdate_b2_uop_ctrl_is_load, // @[core.scala:54:14]
output io_lsu_brupdate_b2_uop_ctrl_is_sta, // @[core.scala:54:14]
output io_lsu_brupdate_b2_uop_ctrl_is_std, // @[core.scala:54:14]
output [1:0] io_lsu_brupdate_b2_uop_iw_state, // @[core.scala:54:14]
output io_lsu_brupdate_b2_uop_iw_p1_poisoned, // @[core.scala:54:14]
output io_lsu_brupdate_b2_uop_iw_p2_poisoned, // @[core.scala:54:14]
output io_lsu_brupdate_b2_uop_is_br, // @[core.scala:54:14]
output io_lsu_brupdate_b2_uop_is_jalr, // @[core.scala:54:14]
output io_lsu_brupdate_b2_uop_is_jal, // @[core.scala:54:14]
output io_lsu_brupdate_b2_uop_is_sfb, // @[core.scala:54:14]
output [15:0] io_lsu_brupdate_b2_uop_br_mask, // @[core.scala:54:14]
output [3:0] io_lsu_brupdate_b2_uop_br_tag, // @[core.scala:54:14]
output [4:0] io_lsu_brupdate_b2_uop_ftq_idx, // @[core.scala:54:14]
output io_lsu_brupdate_b2_uop_edge_inst, // @[core.scala:54:14]
output [5:0] io_lsu_brupdate_b2_uop_pc_lob, // @[core.scala:54:14]
output io_lsu_brupdate_b2_uop_taken, // @[core.scala:54:14]
output [19:0] io_lsu_brupdate_b2_uop_imm_packed, // @[core.scala:54:14]
output [11:0] io_lsu_brupdate_b2_uop_csr_addr, // @[core.scala:54:14]
output [6:0] io_lsu_brupdate_b2_uop_rob_idx, // @[core.scala:54:14]
output [4:0] io_lsu_brupdate_b2_uop_ldq_idx, // @[core.scala:54:14]
output [4:0] io_lsu_brupdate_b2_uop_stq_idx, // @[core.scala:54:14]
output [1:0] io_lsu_brupdate_b2_uop_rxq_idx, // @[core.scala:54:14]
output [6:0] io_lsu_brupdate_b2_uop_pdst, // @[core.scala:54:14]
output [6:0] io_lsu_brupdate_b2_uop_prs1, // @[core.scala:54:14]
output [6:0] io_lsu_brupdate_b2_uop_prs2, // @[core.scala:54:14]
output [6:0] io_lsu_brupdate_b2_uop_prs3, // @[core.scala:54:14]
output [4:0] io_lsu_brupdate_b2_uop_ppred, // @[core.scala:54:14]
output io_lsu_brupdate_b2_uop_prs1_busy, // @[core.scala:54:14]
output io_lsu_brupdate_b2_uop_prs2_busy, // @[core.scala:54:14]
output io_lsu_brupdate_b2_uop_prs3_busy, // @[core.scala:54:14]
output io_lsu_brupdate_b2_uop_ppred_busy, // @[core.scala:54:14]
output [6:0] io_lsu_brupdate_b2_uop_stale_pdst, // @[core.scala:54:14]
output io_lsu_brupdate_b2_uop_exception, // @[core.scala:54:14]
output [63:0] io_lsu_brupdate_b2_uop_exc_cause, // @[core.scala:54:14]
output io_lsu_brupdate_b2_uop_bypassable, // @[core.scala:54:14]
output [4:0] io_lsu_brupdate_b2_uop_mem_cmd, // @[core.scala:54:14]
output [1:0] io_lsu_brupdate_b2_uop_mem_size, // @[core.scala:54:14]
output io_lsu_brupdate_b2_uop_mem_signed, // @[core.scala:54:14]
output io_lsu_brupdate_b2_uop_is_fence, // @[core.scala:54:14]
output io_lsu_brupdate_b2_uop_is_fencei, // @[core.scala:54:14]
output io_lsu_brupdate_b2_uop_is_amo, // @[core.scala:54:14]
output io_lsu_brupdate_b2_uop_uses_ldq, // @[core.scala:54:14]
output io_lsu_brupdate_b2_uop_uses_stq, // @[core.scala:54:14]
output io_lsu_brupdate_b2_uop_is_sys_pc2epc, // @[core.scala:54:14]
output io_lsu_brupdate_b2_uop_is_unique, // @[core.scala:54:14]
output io_lsu_brupdate_b2_uop_flush_on_commit, // @[core.scala:54:14]
output io_lsu_brupdate_b2_uop_ldst_is_rs1, // @[core.scala:54:14]
output [5:0] io_lsu_brupdate_b2_uop_ldst, // @[core.scala:54:14]
output [5:0] io_lsu_brupdate_b2_uop_lrs1, // @[core.scala:54:14]
output [5:0] io_lsu_brupdate_b2_uop_lrs2, // @[core.scala:54:14]
output [5:0] io_lsu_brupdate_b2_uop_lrs3, // @[core.scala:54:14]
output io_lsu_brupdate_b2_uop_ldst_val, // @[core.scala:54:14]
output [1:0] io_lsu_brupdate_b2_uop_dst_rtype, // @[core.scala:54:14]
output [1:0] io_lsu_brupdate_b2_uop_lrs1_rtype, // @[core.scala:54:14]
output [1:0] io_lsu_brupdate_b2_uop_lrs2_rtype, // @[core.scala:54:14]
output io_lsu_brupdate_b2_uop_frs3_en, // @[core.scala:54:14]
output io_lsu_brupdate_b2_uop_fp_val, // @[core.scala:54:14]
output io_lsu_brupdate_b2_uop_fp_single, // @[core.scala:54:14]
output io_lsu_brupdate_b2_uop_xcpt_pf_if, // @[core.scala:54:14]
output io_lsu_brupdate_b2_uop_xcpt_ae_if, // @[core.scala:54:14]
output io_lsu_brupdate_b2_uop_xcpt_ma_if, // @[core.scala:54:14]
output io_lsu_brupdate_b2_uop_bp_debug_if, // @[core.scala:54:14]
output io_lsu_brupdate_b2_uop_bp_xcpt_if, // @[core.scala:54:14]
output [1:0] io_lsu_brupdate_b2_uop_debug_fsrc, // @[core.scala:54:14]
output [1:0] io_lsu_brupdate_b2_uop_debug_tsrc, // @[core.scala:54:14]
output io_lsu_brupdate_b2_valid, // @[core.scala:54:14]
output io_lsu_brupdate_b2_mispredict, // @[core.scala:54:14]
output io_lsu_brupdate_b2_taken, // @[core.scala:54:14]
output [2:0] io_lsu_brupdate_b2_cfi_type, // @[core.scala:54:14]
output [1:0] io_lsu_brupdate_b2_pc_sel, // @[core.scala:54:14]
output [39:0] io_lsu_brupdate_b2_jalr_target, // @[core.scala:54:14]
output [20:0] io_lsu_brupdate_b2_target_offset, // @[core.scala:54:14]
output [6:0] io_lsu_rob_pnr_idx, // @[core.scala:54:14]
output [6:0] io_lsu_rob_head_idx, // @[core.scala:54:14]
output io_lsu_exception, // @[core.scala:54:14]
input io_lsu_fencei_rdy, // @[core.scala:54:14]
input io_lsu_lxcpt_valid, // @[core.scala:54:14]
input [6:0] io_lsu_lxcpt_bits_uop_uopc, // @[core.scala:54:14]
input [31:0] io_lsu_lxcpt_bits_uop_inst, // @[core.scala:54:14]
input [31:0] io_lsu_lxcpt_bits_uop_debug_inst, // @[core.scala:54:14]
input io_lsu_lxcpt_bits_uop_is_rvc, // @[core.scala:54:14]
input [39:0] io_lsu_lxcpt_bits_uop_debug_pc, // @[core.scala:54:14]
input [2:0] io_lsu_lxcpt_bits_uop_iq_type, // @[core.scala:54:14]
input [9:0] io_lsu_lxcpt_bits_uop_fu_code, // @[core.scala:54:14]
input [3:0] io_lsu_lxcpt_bits_uop_ctrl_br_type, // @[core.scala:54:14]
input [1:0] io_lsu_lxcpt_bits_uop_ctrl_op1_sel, // @[core.scala:54:14]
input [2:0] io_lsu_lxcpt_bits_uop_ctrl_op2_sel, // @[core.scala:54:14]
input [2:0] io_lsu_lxcpt_bits_uop_ctrl_imm_sel, // @[core.scala:54:14]
input [4:0] io_lsu_lxcpt_bits_uop_ctrl_op_fcn, // @[core.scala:54:14]
input io_lsu_lxcpt_bits_uop_ctrl_fcn_dw, // @[core.scala:54:14]
input [2:0] io_lsu_lxcpt_bits_uop_ctrl_csr_cmd, // @[core.scala:54:14]
input io_lsu_lxcpt_bits_uop_ctrl_is_load, // @[core.scala:54:14]
input io_lsu_lxcpt_bits_uop_ctrl_is_sta, // @[core.scala:54:14]
input io_lsu_lxcpt_bits_uop_ctrl_is_std, // @[core.scala:54:14]
input [1:0] io_lsu_lxcpt_bits_uop_iw_state, // @[core.scala:54:14]
input io_lsu_lxcpt_bits_uop_iw_p1_poisoned, // @[core.scala:54:14]
input io_lsu_lxcpt_bits_uop_iw_p2_poisoned, // @[core.scala:54:14]
input io_lsu_lxcpt_bits_uop_is_br, // @[core.scala:54:14]
input io_lsu_lxcpt_bits_uop_is_jalr, // @[core.scala:54:14]
input io_lsu_lxcpt_bits_uop_is_jal, // @[core.scala:54:14]
input io_lsu_lxcpt_bits_uop_is_sfb, // @[core.scala:54:14]
input [15:0] io_lsu_lxcpt_bits_uop_br_mask, // @[core.scala:54:14]
input [3:0] io_lsu_lxcpt_bits_uop_br_tag, // @[core.scala:54:14]
input [4:0] io_lsu_lxcpt_bits_uop_ftq_idx, // @[core.scala:54:14]
input io_lsu_lxcpt_bits_uop_edge_inst, // @[core.scala:54:14]
input [5:0] io_lsu_lxcpt_bits_uop_pc_lob, // @[core.scala:54:14]
input io_lsu_lxcpt_bits_uop_taken, // @[core.scala:54:14]
input [19:0] io_lsu_lxcpt_bits_uop_imm_packed, // @[core.scala:54:14]
input [11:0] io_lsu_lxcpt_bits_uop_csr_addr, // @[core.scala:54:14]
input [6:0] io_lsu_lxcpt_bits_uop_rob_idx, // @[core.scala:54:14]
input [4:0] io_lsu_lxcpt_bits_uop_ldq_idx, // @[core.scala:54:14]
input [4:0] io_lsu_lxcpt_bits_uop_stq_idx, // @[core.scala:54:14]
input [1:0] io_lsu_lxcpt_bits_uop_rxq_idx, // @[core.scala:54:14]
input [6:0] io_lsu_lxcpt_bits_uop_pdst, // @[core.scala:54:14]
input [6:0] io_lsu_lxcpt_bits_uop_prs1, // @[core.scala:54:14]
input [6:0] io_lsu_lxcpt_bits_uop_prs2, // @[core.scala:54:14]
input [6:0] io_lsu_lxcpt_bits_uop_prs3, // @[core.scala:54:14]
input [4:0] io_lsu_lxcpt_bits_uop_ppred, // @[core.scala:54:14]
input io_lsu_lxcpt_bits_uop_prs1_busy, // @[core.scala:54:14]
input io_lsu_lxcpt_bits_uop_prs2_busy, // @[core.scala:54:14]
input io_lsu_lxcpt_bits_uop_prs3_busy, // @[core.scala:54:14]
input io_lsu_lxcpt_bits_uop_ppred_busy, // @[core.scala:54:14]
input [6:0] io_lsu_lxcpt_bits_uop_stale_pdst, // @[core.scala:54:14]
input io_lsu_lxcpt_bits_uop_exception, // @[core.scala:54:14]
input [63:0] io_lsu_lxcpt_bits_uop_exc_cause, // @[core.scala:54:14]
input io_lsu_lxcpt_bits_uop_bypassable, // @[core.scala:54:14]
input [4:0] io_lsu_lxcpt_bits_uop_mem_cmd, // @[core.scala:54:14]
input [1:0] io_lsu_lxcpt_bits_uop_mem_size, // @[core.scala:54:14]
input io_lsu_lxcpt_bits_uop_mem_signed, // @[core.scala:54:14]
input io_lsu_lxcpt_bits_uop_is_fence, // @[core.scala:54:14]
input io_lsu_lxcpt_bits_uop_is_fencei, // @[core.scala:54:14]
input io_lsu_lxcpt_bits_uop_is_amo, // @[core.scala:54:14]
input io_lsu_lxcpt_bits_uop_uses_ldq, // @[core.scala:54:14]
input io_lsu_lxcpt_bits_uop_uses_stq, // @[core.scala:54:14]
input io_lsu_lxcpt_bits_uop_is_sys_pc2epc, // @[core.scala:54:14]
input io_lsu_lxcpt_bits_uop_is_unique, // @[core.scala:54:14]
input io_lsu_lxcpt_bits_uop_flush_on_commit, // @[core.scala:54:14]
input io_lsu_lxcpt_bits_uop_ldst_is_rs1, // @[core.scala:54:14]
input [5:0] io_lsu_lxcpt_bits_uop_ldst, // @[core.scala:54:14]
input [5:0] io_lsu_lxcpt_bits_uop_lrs1, // @[core.scala:54:14]
input [5:0] io_lsu_lxcpt_bits_uop_lrs2, // @[core.scala:54:14]
input [5:0] io_lsu_lxcpt_bits_uop_lrs3, // @[core.scala:54:14]
input io_lsu_lxcpt_bits_uop_ldst_val, // @[core.scala:54:14]
input [1:0] io_lsu_lxcpt_bits_uop_dst_rtype, // @[core.scala:54:14]
input [1:0] io_lsu_lxcpt_bits_uop_lrs1_rtype, // @[core.scala:54:14]
input [1:0] io_lsu_lxcpt_bits_uop_lrs2_rtype, // @[core.scala:54:14]
input io_lsu_lxcpt_bits_uop_frs3_en, // @[core.scala:54:14]
input io_lsu_lxcpt_bits_uop_fp_val, // @[core.scala:54:14]
input io_lsu_lxcpt_bits_uop_fp_single, // @[core.scala:54:14]
input io_lsu_lxcpt_bits_uop_xcpt_pf_if, // @[core.scala:54:14]
input io_lsu_lxcpt_bits_uop_xcpt_ae_if, // @[core.scala:54:14]
input io_lsu_lxcpt_bits_uop_xcpt_ma_if, // @[core.scala:54:14]
input io_lsu_lxcpt_bits_uop_bp_debug_if, // @[core.scala:54:14]
input io_lsu_lxcpt_bits_uop_bp_xcpt_if, // @[core.scala:54:14]
input [1:0] io_lsu_lxcpt_bits_uop_debug_fsrc, // @[core.scala:54:14]
input [1:0] io_lsu_lxcpt_bits_uop_debug_tsrc, // @[core.scala:54:14]
input [4:0] io_lsu_lxcpt_bits_cause, // @[core.scala:54:14]
input [39:0] io_lsu_lxcpt_bits_badvaddr, // @[core.scala:54:14]
output [63:0] io_lsu_tsc_reg, // @[core.scala:54:14]
input io_lsu_perf_acquire, // @[core.scala:54:14]
input io_lsu_perf_release, // @[core.scala:54:14]
input io_lsu_perf_tlbMiss, // @[core.scala:54:14]
input io_ptw_tlb_req_ready, // @[core.scala:54:14]
input io_ptw_tlb_resp_valid, // @[core.scala:54:14]
input io_ptw_tlb_resp_bits_ae_ptw, // @[core.scala:54:14]
input io_ptw_tlb_resp_bits_ae_final, // @[core.scala:54:14]
input io_ptw_tlb_resp_bits_pf, // @[core.scala:54:14]
input io_ptw_tlb_resp_bits_gf, // @[core.scala:54:14]
input io_ptw_tlb_resp_bits_hr, // @[core.scala:54:14]
input io_ptw_tlb_resp_bits_hw, // @[core.scala:54:14]
input io_ptw_tlb_resp_bits_hx, // @[core.scala:54:14]
input [9:0] io_ptw_tlb_resp_bits_pte_reserved_for_future, // @[core.scala:54:14]
input [43:0] io_ptw_tlb_resp_bits_pte_ppn, // @[core.scala:54:14]
input [1:0] io_ptw_tlb_resp_bits_pte_reserved_for_software, // @[core.scala:54:14]
input io_ptw_tlb_resp_bits_pte_d, // @[core.scala:54:14]
input io_ptw_tlb_resp_bits_pte_a, // @[core.scala:54:14]
input io_ptw_tlb_resp_bits_pte_g, // @[core.scala:54:14]
input io_ptw_tlb_resp_bits_pte_u, // @[core.scala:54:14]
input io_ptw_tlb_resp_bits_pte_x, // @[core.scala:54:14]
input io_ptw_tlb_resp_bits_pte_w, // @[core.scala:54:14]
input io_ptw_tlb_resp_bits_pte_r, // @[core.scala:54:14]
input io_ptw_tlb_resp_bits_pte_v, // @[core.scala:54:14]
input [1:0] io_ptw_tlb_resp_bits_level, // @[core.scala:54:14]
input io_ptw_tlb_resp_bits_homogeneous, // @[core.scala:54:14]
input io_ptw_tlb_resp_bits_gpa_valid, // @[core.scala:54:14]
input [38:0] io_ptw_tlb_resp_bits_gpa_bits, // @[core.scala:54:14]
input io_ptw_tlb_resp_bits_gpa_is_pte, // @[core.scala:54:14]
input [3:0] io_ptw_tlb_ptbr_mode, // @[core.scala:54:14]
input [43:0] io_ptw_tlb_ptbr_ppn, // @[core.scala:54:14]
input io_ptw_tlb_status_debug, // @[core.scala:54:14]
input io_ptw_tlb_status_cease, // @[core.scala:54:14]
input io_ptw_tlb_status_wfi, // @[core.scala:54:14]
input [1:0] io_ptw_tlb_status_dprv, // @[core.scala:54:14]
input io_ptw_tlb_status_dv, // @[core.scala:54:14]
input [1:0] io_ptw_tlb_status_prv, // @[core.scala:54:14]
input io_ptw_tlb_status_v, // @[core.scala:54:14]
input io_ptw_tlb_status_sd, // @[core.scala:54:14]
input io_ptw_tlb_status_mpv, // @[core.scala:54:14]
input io_ptw_tlb_status_gva, // @[core.scala:54:14]
input io_ptw_tlb_status_tsr, // @[core.scala:54:14]
input io_ptw_tlb_status_tw, // @[core.scala:54:14]
input io_ptw_tlb_status_tvm, // @[core.scala:54:14]
input io_ptw_tlb_status_mxr, // @[core.scala:54:14]
input io_ptw_tlb_status_sum, // @[core.scala:54:14]
input io_ptw_tlb_status_mprv, // @[core.scala:54:14]
input [1:0] io_ptw_tlb_status_fs, // @[core.scala:54:14]
input [1:0] io_ptw_tlb_status_mpp, // @[core.scala:54:14]
input io_ptw_tlb_status_spp, // @[core.scala:54:14]
input io_ptw_tlb_status_mpie, // @[core.scala:54:14]
input io_ptw_tlb_status_spie, // @[core.scala:54:14]
input io_ptw_tlb_status_mie, // @[core.scala:54:14]
input io_ptw_tlb_status_sie, // @[core.scala:54:14]
input io_ptw_tlb_pmp_0_cfg_l, // @[core.scala:54:14]
input [1:0] io_ptw_tlb_pmp_0_cfg_a, // @[core.scala:54:14]
input io_ptw_tlb_pmp_0_cfg_x, // @[core.scala:54:14]
input io_ptw_tlb_pmp_0_cfg_w, // @[core.scala:54:14]
input io_ptw_tlb_pmp_0_cfg_r, // @[core.scala:54:14]
input [29:0] io_ptw_tlb_pmp_0_addr, // @[core.scala:54:14]
input [31:0] io_ptw_tlb_pmp_0_mask, // @[core.scala:54:14]
input io_ptw_tlb_pmp_1_cfg_l, // @[core.scala:54:14]
input [1:0] io_ptw_tlb_pmp_1_cfg_a, // @[core.scala:54:14]
input io_ptw_tlb_pmp_1_cfg_x, // @[core.scala:54:14]
input io_ptw_tlb_pmp_1_cfg_w, // @[core.scala:54:14]
input io_ptw_tlb_pmp_1_cfg_r, // @[core.scala:54:14]
input [29:0] io_ptw_tlb_pmp_1_addr, // @[core.scala:54:14]
input [31:0] io_ptw_tlb_pmp_1_mask, // @[core.scala:54:14]
input io_ptw_tlb_pmp_2_cfg_l, // @[core.scala:54:14]
input [1:0] io_ptw_tlb_pmp_2_cfg_a, // @[core.scala:54:14]
input io_ptw_tlb_pmp_2_cfg_x, // @[core.scala:54:14]
input io_ptw_tlb_pmp_2_cfg_w, // @[core.scala:54:14]
input io_ptw_tlb_pmp_2_cfg_r, // @[core.scala:54:14]
input [29:0] io_ptw_tlb_pmp_2_addr, // @[core.scala:54:14]
input [31:0] io_ptw_tlb_pmp_2_mask, // @[core.scala:54:14]
input io_ptw_tlb_pmp_3_cfg_l, // @[core.scala:54:14]
input [1:0] io_ptw_tlb_pmp_3_cfg_a, // @[core.scala:54:14]
input io_ptw_tlb_pmp_3_cfg_x, // @[core.scala:54:14]
input io_ptw_tlb_pmp_3_cfg_w, // @[core.scala:54:14]
input io_ptw_tlb_pmp_3_cfg_r, // @[core.scala:54:14]
input [29:0] io_ptw_tlb_pmp_3_addr, // @[core.scala:54:14]
input [31:0] io_ptw_tlb_pmp_3_mask, // @[core.scala:54:14]
input io_ptw_tlb_pmp_4_cfg_l, // @[core.scala:54:14]
input [1:0] io_ptw_tlb_pmp_4_cfg_a, // @[core.scala:54:14]
input io_ptw_tlb_pmp_4_cfg_x, // @[core.scala:54:14]
input io_ptw_tlb_pmp_4_cfg_w, // @[core.scala:54:14]
input io_ptw_tlb_pmp_4_cfg_r, // @[core.scala:54:14]
input [29:0] io_ptw_tlb_pmp_4_addr, // @[core.scala:54:14]
input [31:0] io_ptw_tlb_pmp_4_mask, // @[core.scala:54:14]
input io_ptw_tlb_pmp_5_cfg_l, // @[core.scala:54:14]
input [1:0] io_ptw_tlb_pmp_5_cfg_a, // @[core.scala:54:14]
input io_ptw_tlb_pmp_5_cfg_x, // @[core.scala:54:14]
input io_ptw_tlb_pmp_5_cfg_w, // @[core.scala:54:14]
input io_ptw_tlb_pmp_5_cfg_r, // @[core.scala:54:14]
input [29:0] io_ptw_tlb_pmp_5_addr, // @[core.scala:54:14]
input [31:0] io_ptw_tlb_pmp_5_mask, // @[core.scala:54:14]
input io_ptw_tlb_pmp_6_cfg_l, // @[core.scala:54:14]
input [1:0] io_ptw_tlb_pmp_6_cfg_a, // @[core.scala:54:14]
input io_ptw_tlb_pmp_6_cfg_x, // @[core.scala:54:14]
input io_ptw_tlb_pmp_6_cfg_w, // @[core.scala:54:14]
input io_ptw_tlb_pmp_6_cfg_r, // @[core.scala:54:14]
input [29:0] io_ptw_tlb_pmp_6_addr, // @[core.scala:54:14]
input [31:0] io_ptw_tlb_pmp_6_mask, // @[core.scala:54:14]
input io_ptw_tlb_pmp_7_cfg_l, // @[core.scala:54:14]
input [1:0] io_ptw_tlb_pmp_7_cfg_a, // @[core.scala:54:14]
input io_ptw_tlb_pmp_7_cfg_x, // @[core.scala:54:14]
input io_ptw_tlb_pmp_7_cfg_w, // @[core.scala:54:14]
input io_ptw_tlb_pmp_7_cfg_r, // @[core.scala:54:14]
input [29:0] io_ptw_tlb_pmp_7_addr, // @[core.scala:54:14]
input [31:0] io_ptw_tlb_pmp_7_mask, // @[core.scala:54:14]
output [63:0] io_trace_time, // @[core.scala:54:14]
output io_trace_custom_rob_empty // @[core.scala:54:14]
);
wire [1:0] iss_uops_3_debug_tsrc; // @[core.scala:173:24]
wire [1:0] iss_uops_3_debug_fsrc; // @[core.scala:173:24]
wire iss_uops_3_bp_xcpt_if; // @[core.scala:173:24]
wire iss_uops_3_bp_debug_if; // @[core.scala:173:24]
wire iss_uops_3_xcpt_ma_if; // @[core.scala:173:24]
wire iss_uops_3_xcpt_ae_if; // @[core.scala:173:24]
wire iss_uops_3_xcpt_pf_if; // @[core.scala:173:24]
wire iss_uops_3_fp_single; // @[core.scala:173:24]
wire iss_uops_3_fp_val; // @[core.scala:173:24]
wire iss_uops_3_frs3_en; // @[core.scala:173:24]
wire [1:0] iss_uops_3_lrs2_rtype; // @[core.scala:173:24]
wire [1:0] iss_uops_3_lrs1_rtype; // @[core.scala:173:24]
wire [1:0] iss_uops_3_dst_rtype; // @[core.scala:173:24]
wire iss_uops_3_ldst_val; // @[core.scala:173:24]
wire [5:0] iss_uops_3_lrs3; // @[core.scala:173:24]
wire [5:0] iss_uops_3_lrs2; // @[core.scala:173:24]
wire [5:0] iss_uops_3_lrs1; // @[core.scala:173:24]
wire [5:0] iss_uops_3_ldst; // @[core.scala:173:24]
wire iss_uops_3_ldst_is_rs1; // @[core.scala:173:24]
wire iss_uops_3_flush_on_commit; // @[core.scala:173:24]
wire iss_uops_3_is_unique; // @[core.scala:173:24]
wire iss_uops_3_is_sys_pc2epc; // @[core.scala:173:24]
wire iss_uops_3_uses_stq; // @[core.scala:173:24]
wire iss_uops_3_uses_ldq; // @[core.scala:173:24]
wire iss_uops_3_is_amo; // @[core.scala:173:24]
wire iss_uops_3_is_fencei; // @[core.scala:173:24]
wire iss_uops_3_is_fence; // @[core.scala:173:24]
wire iss_uops_3_mem_signed; // @[core.scala:173:24]
wire [1:0] iss_uops_3_mem_size; // @[core.scala:173:24]
wire [4:0] iss_uops_3_mem_cmd; // @[core.scala:173:24]
wire iss_uops_3_bypassable; // @[core.scala:173:24]
wire [63:0] iss_uops_3_exc_cause; // @[core.scala:173:24]
wire iss_uops_3_exception; // @[core.scala:173:24]
wire [6:0] iss_uops_3_stale_pdst; // @[core.scala:173:24]
wire iss_uops_3_ppred_busy; // @[core.scala:173:24]
wire iss_uops_3_prs3_busy; // @[core.scala:173:24]
wire iss_uops_3_prs2_busy; // @[core.scala:173:24]
wire iss_uops_3_prs1_busy; // @[core.scala:173:24]
wire [4:0] iss_uops_3_ppred; // @[core.scala:173:24]
wire [6:0] iss_uops_3_prs3; // @[core.scala:173:24]
wire [6:0] iss_uops_3_prs2; // @[core.scala:173:24]
wire [6:0] iss_uops_3_prs1; // @[core.scala:173:24]
wire [6:0] iss_uops_3_pdst; // @[core.scala:173:24]
wire [1:0] iss_uops_3_rxq_idx; // @[core.scala:173:24]
wire [4:0] iss_uops_3_stq_idx; // @[core.scala:173:24]
wire [4:0] iss_uops_3_ldq_idx; // @[core.scala:173:24]
wire [6:0] iss_uops_3_rob_idx; // @[core.scala:173:24]
wire [11:0] iss_uops_3_csr_addr; // @[core.scala:173:24]
wire [19:0] iss_uops_3_imm_packed; // @[core.scala:173:24]
wire iss_uops_3_taken; // @[core.scala:173:24]
wire [5:0] iss_uops_3_pc_lob; // @[core.scala:173:24]
wire iss_uops_3_edge_inst; // @[core.scala:173:24]
wire [4:0] iss_uops_3_ftq_idx; // @[core.scala:173:24]
wire [3:0] iss_uops_3_br_tag; // @[core.scala:173:24]
wire [15:0] iss_uops_3_br_mask; // @[core.scala:173:24]
wire iss_uops_3_is_sfb; // @[core.scala:173:24]
wire iss_uops_3_is_jal; // @[core.scala:173:24]
wire iss_uops_3_is_jalr; // @[core.scala:173:24]
wire iss_uops_3_is_br; // @[core.scala:173:24]
wire iss_uops_3_iw_p2_poisoned; // @[core.scala:173:24]
wire iss_uops_3_iw_p1_poisoned; // @[core.scala:173:24]
wire [1:0] iss_uops_3_iw_state; // @[core.scala:173:24]
wire [9:0] iss_uops_3_fu_code; // @[core.scala:173:24]
wire [2:0] iss_uops_3_iq_type; // @[core.scala:173:24]
wire [39:0] iss_uops_3_debug_pc; // @[core.scala:173:24]
wire iss_uops_3_is_rvc; // @[core.scala:173:24]
wire [31:0] iss_uops_3_debug_inst; // @[core.scala:173:24]
wire [31:0] iss_uops_3_inst; // @[core.scala:173:24]
wire [6:0] iss_uops_3_uopc; // @[core.scala:173:24]
wire iss_uops_3_ctrl_is_std; // @[core.scala:173:24]
wire iss_uops_3_ctrl_is_sta; // @[core.scala:173:24]
wire iss_uops_3_ctrl_is_load; // @[core.scala:173:24]
wire [2:0] iss_uops_3_ctrl_csr_cmd; // @[core.scala:173:24]
wire iss_uops_3_ctrl_fcn_dw; // @[core.scala:173:24]
wire [4:0] iss_uops_3_ctrl_op_fcn; // @[core.scala:173:24]
wire [2:0] iss_uops_3_ctrl_imm_sel; // @[core.scala:173:24]
wire [2:0] iss_uops_3_ctrl_op2_sel; // @[core.scala:173:24]
wire [1:0] iss_uops_3_ctrl_op1_sel; // @[core.scala:173:24]
wire [3:0] iss_uops_3_ctrl_br_type; // @[core.scala:173:24]
wire [1:0] iss_uops_2_debug_tsrc; // @[core.scala:173:24]
wire [1:0] iss_uops_2_debug_fsrc; // @[core.scala:173:24]
wire iss_uops_2_bp_xcpt_if; // @[core.scala:173:24]
wire iss_uops_2_bp_debug_if; // @[core.scala:173:24]
wire iss_uops_2_xcpt_ma_if; // @[core.scala:173:24]
wire iss_uops_2_xcpt_ae_if; // @[core.scala:173:24]
wire iss_uops_2_xcpt_pf_if; // @[core.scala:173:24]
wire iss_uops_2_fp_single; // @[core.scala:173:24]
wire iss_uops_2_fp_val; // @[core.scala:173:24]
wire iss_uops_2_frs3_en; // @[core.scala:173:24]
wire [1:0] iss_uops_2_lrs2_rtype; // @[core.scala:173:24]
wire [1:0] iss_uops_2_lrs1_rtype; // @[core.scala:173:24]
wire [1:0] iss_uops_2_dst_rtype; // @[core.scala:173:24]
wire iss_uops_2_ldst_val; // @[core.scala:173:24]
wire [5:0] iss_uops_2_lrs3; // @[core.scala:173:24]
wire [5:0] iss_uops_2_lrs2; // @[core.scala:173:24]
wire [5:0] iss_uops_2_lrs1; // @[core.scala:173:24]
wire [5:0] iss_uops_2_ldst; // @[core.scala:173:24]
wire iss_uops_2_ldst_is_rs1; // @[core.scala:173:24]
wire iss_uops_2_flush_on_commit; // @[core.scala:173:24]
wire iss_uops_2_is_unique; // @[core.scala:173:24]
wire iss_uops_2_is_sys_pc2epc; // @[core.scala:173:24]
wire iss_uops_2_uses_stq; // @[core.scala:173:24]
wire iss_uops_2_uses_ldq; // @[core.scala:173:24]
wire iss_uops_2_is_amo; // @[core.scala:173:24]
wire iss_uops_2_is_fencei; // @[core.scala:173:24]
wire iss_uops_2_is_fence; // @[core.scala:173:24]
wire iss_uops_2_mem_signed; // @[core.scala:173:24]
wire [1:0] iss_uops_2_mem_size; // @[core.scala:173:24]
wire [4:0] iss_uops_2_mem_cmd; // @[core.scala:173:24]
wire iss_uops_2_bypassable; // @[core.scala:173:24]
wire [63:0] iss_uops_2_exc_cause; // @[core.scala:173:24]
wire iss_uops_2_exception; // @[core.scala:173:24]
wire [6:0] iss_uops_2_stale_pdst; // @[core.scala:173:24]
wire iss_uops_2_ppred_busy; // @[core.scala:173:24]
wire iss_uops_2_prs3_busy; // @[core.scala:173:24]
wire iss_uops_2_prs2_busy; // @[core.scala:173:24]
wire iss_uops_2_prs1_busy; // @[core.scala:173:24]
wire [4:0] iss_uops_2_ppred; // @[core.scala:173:24]
wire [6:0] iss_uops_2_prs3; // @[core.scala:173:24]
wire [6:0] iss_uops_2_prs2; // @[core.scala:173:24]
wire [6:0] iss_uops_2_prs1; // @[core.scala:173:24]
wire [6:0] iss_uops_2_pdst; // @[core.scala:173:24]
wire [1:0] iss_uops_2_rxq_idx; // @[core.scala:173:24]
wire [4:0] iss_uops_2_stq_idx; // @[core.scala:173:24]
wire [4:0] iss_uops_2_ldq_idx; // @[core.scala:173:24]
wire [6:0] iss_uops_2_rob_idx; // @[core.scala:173:24]
wire [11:0] iss_uops_2_csr_addr; // @[core.scala:173:24]
wire [19:0] iss_uops_2_imm_packed; // @[core.scala:173:24]
wire iss_uops_2_taken; // @[core.scala:173:24]
wire [5:0] iss_uops_2_pc_lob; // @[core.scala:173:24]
wire iss_uops_2_edge_inst; // @[core.scala:173:24]
wire [4:0] iss_uops_2_ftq_idx; // @[core.scala:173:24]
wire [3:0] iss_uops_2_br_tag; // @[core.scala:173:24]
wire [15:0] iss_uops_2_br_mask; // @[core.scala:173:24]
wire iss_uops_2_is_sfb; // @[core.scala:173:24]
wire iss_uops_2_is_jal; // @[core.scala:173:24]
wire iss_uops_2_is_jalr; // @[core.scala:173:24]
wire iss_uops_2_is_br; // @[core.scala:173:24]
wire iss_uops_2_iw_p2_poisoned; // @[core.scala:173:24]
wire iss_uops_2_iw_p1_poisoned; // @[core.scala:173:24]
wire [1:0] iss_uops_2_iw_state; // @[core.scala:173:24]
wire [9:0] iss_uops_2_fu_code; // @[core.scala:173:24]
wire [2:0] iss_uops_2_iq_type; // @[core.scala:173:24]
wire [39:0] iss_uops_2_debug_pc; // @[core.scala:173:24]
wire iss_uops_2_is_rvc; // @[core.scala:173:24]
wire [31:0] iss_uops_2_debug_inst; // @[core.scala:173:24]
wire [31:0] iss_uops_2_inst; // @[core.scala:173:24]
wire [6:0] iss_uops_2_uopc; // @[core.scala:173:24]
wire iss_uops_2_ctrl_is_std; // @[core.scala:173:24]
wire iss_uops_2_ctrl_is_sta; // @[core.scala:173:24]
wire iss_uops_2_ctrl_is_load; // @[core.scala:173:24]
wire [2:0] iss_uops_2_ctrl_csr_cmd; // @[core.scala:173:24]
wire iss_uops_2_ctrl_fcn_dw; // @[core.scala:173:24]
wire [4:0] iss_uops_2_ctrl_op_fcn; // @[core.scala:173:24]
wire [2:0] iss_uops_2_ctrl_imm_sel; // @[core.scala:173:24]
wire [2:0] iss_uops_2_ctrl_op2_sel; // @[core.scala:173:24]
wire [1:0] iss_uops_2_ctrl_op1_sel; // @[core.scala:173:24]
wire [3:0] iss_uops_2_ctrl_br_type; // @[core.scala:173:24]
wire dis_valids_0; // @[core.scala:166:24]
wire io_ifu_sfence_bits_asid_0; // @[core.scala:51:7]
wire [38:0] io_ifu_sfence_bits_addr_0; // @[core.scala:51:7]
wire io_ifu_sfence_bits_rs2_0; // @[core.scala:51:7]
wire io_ifu_sfence_bits_rs1_0; // @[core.scala:51:7]
wire io_ifu_sfence_valid_0; // @[core.scala:51:7]
wire [63:0] _csr_io_rw_rdata; // @[core.scala:271:19]
wire _csr_io_decode_0_fp_illegal; // @[core.scala:271:19]
wire _csr_io_decode_0_fp_csr; // @[core.scala:271:19]
wire _csr_io_decode_0_read_illegal; // @[core.scala:271:19]
wire _csr_io_decode_0_write_illegal; // @[core.scala:271:19]
wire _csr_io_decode_0_write_flush; // @[core.scala:271:19]
wire _csr_io_decode_0_system_illegal; // @[core.scala:271:19]
wire _csr_io_decode_0_virtual_access_illegal; // @[core.scala:271:19]
wire _csr_io_decode_0_virtual_system_illegal; // @[core.scala:271:19]
wire _csr_io_decode_1_fp_illegal; // @[core.scala:271:19]
wire _csr_io_decode_1_fp_csr; // @[core.scala:271:19]
wire _csr_io_decode_1_read_illegal; // @[core.scala:271:19]
wire _csr_io_decode_1_write_illegal; // @[core.scala:271:19]
wire _csr_io_decode_1_write_flush; // @[core.scala:271:19]
wire _csr_io_decode_1_system_illegal; // @[core.scala:271:19]
wire _csr_io_decode_1_virtual_access_illegal; // @[core.scala:271:19]
wire _csr_io_decode_1_virtual_system_illegal; // @[core.scala:271:19]
wire _csr_io_decode_2_fp_illegal; // @[core.scala:271:19]
wire _csr_io_decode_2_fp_csr; // @[core.scala:271:19]
wire _csr_io_decode_2_read_illegal; // @[core.scala:271:19]
wire _csr_io_decode_2_write_illegal; // @[core.scala:271:19]
wire _csr_io_decode_2_write_flush; // @[core.scala:271:19]
wire _csr_io_decode_2_system_illegal; // @[core.scala:271:19]
wire _csr_io_decode_2_virtual_access_illegal; // @[core.scala:271:19]
wire _csr_io_decode_2_virtual_system_illegal; // @[core.scala:271:19]
wire _csr_io_csr_stall; // @[core.scala:271:19]
wire _csr_io_singleStep; // @[core.scala:271:19]
wire _csr_io_status_debug; // @[core.scala:271:19]
wire _csr_io_status_cease; // @[core.scala:271:19]
wire _csr_io_status_wfi; // @[core.scala:271:19]
wire [1:0] _csr_io_status_dprv; // @[core.scala:271:19]
wire _csr_io_status_dv; // @[core.scala:271:19]
wire [1:0] _csr_io_status_prv; // @[core.scala:271:19]
wire _csr_io_status_v; // @[core.scala:271:19]
wire _csr_io_status_sd; // @[core.scala:271:19]
wire _csr_io_status_mpv; // @[core.scala:271:19]
wire _csr_io_status_gva; // @[core.scala:271:19]
wire _csr_io_status_tsr; // @[core.scala:271:19]
wire _csr_io_status_tw; // @[core.scala:271:19]
wire _csr_io_status_tvm; // @[core.scala:271:19]
wire _csr_io_status_mxr; // @[core.scala:271:19]
wire _csr_io_status_sum; // @[core.scala:271:19]
wire _csr_io_status_mprv; // @[core.scala:271:19]
wire [1:0] _csr_io_status_fs; // @[core.scala:271:19]
wire [1:0] _csr_io_status_mpp; // @[core.scala:271:19]
wire _csr_io_status_spp; // @[core.scala:271:19]
wire _csr_io_status_mpie; // @[core.scala:271:19]
wire _csr_io_status_spie; // @[core.scala:271:19]
wire _csr_io_status_mie; // @[core.scala:271:19]
wire _csr_io_status_sie; // @[core.scala:271:19]
wire [39:0] _csr_io_evec; // @[core.scala:271:19]
wire [2:0] _csr_io_fcsr_rm; // @[core.scala:271:19]
wire _csr_io_interrupt; // @[core.scala:271:19]
wire [63:0] _csr_io_interrupt_cause; // @[core.scala:271:19]
wire [6:0] _rob_io_rob_tail_idx; // @[core.scala:143:32]
wire [6:0] _rob_io_rob_head_idx; // @[core.scala:143:32]
wire _rob_io_commit_valids_0; // @[core.scala:143:32]
wire _rob_io_commit_valids_1; // @[core.scala:143:32]
wire _rob_io_commit_valids_2; // @[core.scala:143:32]
wire _rob_io_commit_arch_valids_0; // @[core.scala:143:32]
wire _rob_io_commit_arch_valids_1; // @[core.scala:143:32]
wire _rob_io_commit_arch_valids_2; // @[core.scala:143:32]
wire [6:0] _rob_io_commit_uops_0_uopc; // @[core.scala:143:32]
wire [31:0] _rob_io_commit_uops_0_inst; // @[core.scala:143:32]
wire [31:0] _rob_io_commit_uops_0_debug_inst; // @[core.scala:143:32]
wire _rob_io_commit_uops_0_is_rvc; // @[core.scala:143:32]
wire [39:0] _rob_io_commit_uops_0_debug_pc; // @[core.scala:143:32]
wire [2:0] _rob_io_commit_uops_0_iq_type; // @[core.scala:143:32]
wire [9:0] _rob_io_commit_uops_0_fu_code; // @[core.scala:143:32]
wire [3:0] _rob_io_commit_uops_0_ctrl_br_type; // @[core.scala:143:32]
wire [1:0] _rob_io_commit_uops_0_ctrl_op1_sel; // @[core.scala:143:32]
wire [2:0] _rob_io_commit_uops_0_ctrl_op2_sel; // @[core.scala:143:32]
wire [2:0] _rob_io_commit_uops_0_ctrl_imm_sel; // @[core.scala:143:32]
wire [4:0] _rob_io_commit_uops_0_ctrl_op_fcn; // @[core.scala:143:32]
wire _rob_io_commit_uops_0_ctrl_fcn_dw; // @[core.scala:143:32]
wire [2:0] _rob_io_commit_uops_0_ctrl_csr_cmd; // @[core.scala:143:32]
wire _rob_io_commit_uops_0_ctrl_is_load; // @[core.scala:143:32]
wire _rob_io_commit_uops_0_ctrl_is_sta; // @[core.scala:143:32]
wire _rob_io_commit_uops_0_ctrl_is_std; // @[core.scala:143:32]
wire [1:0] _rob_io_commit_uops_0_iw_state; // @[core.scala:143:32]
wire _rob_io_commit_uops_0_iw_p1_poisoned; // @[core.scala:143:32]
wire _rob_io_commit_uops_0_iw_p2_poisoned; // @[core.scala:143:32]
wire _rob_io_commit_uops_0_is_br; // @[core.scala:143:32]
wire _rob_io_commit_uops_0_is_jalr; // @[core.scala:143:32]
wire _rob_io_commit_uops_0_is_jal; // @[core.scala:143:32]
wire _rob_io_commit_uops_0_is_sfb; // @[core.scala:143:32]
wire [15:0] _rob_io_commit_uops_0_br_mask; // @[core.scala:143:32]
wire [3:0] _rob_io_commit_uops_0_br_tag; // @[core.scala:143:32]
wire [4:0] _rob_io_commit_uops_0_ftq_idx; // @[core.scala:143:32]
wire _rob_io_commit_uops_0_edge_inst; // @[core.scala:143:32]
wire [5:0] _rob_io_commit_uops_0_pc_lob; // @[core.scala:143:32]
wire _rob_io_commit_uops_0_taken; // @[core.scala:143:32]
wire [19:0] _rob_io_commit_uops_0_imm_packed; // @[core.scala:143:32]
wire [11:0] _rob_io_commit_uops_0_csr_addr; // @[core.scala:143:32]
wire [6:0] _rob_io_commit_uops_0_rob_idx; // @[core.scala:143:32]
wire [4:0] _rob_io_commit_uops_0_ldq_idx; // @[core.scala:143:32]
wire [4:0] _rob_io_commit_uops_0_stq_idx; // @[core.scala:143:32]
wire [1:0] _rob_io_commit_uops_0_rxq_idx; // @[core.scala:143:32]
wire [6:0] _rob_io_commit_uops_0_pdst; // @[core.scala:143:32]
wire [6:0] _rob_io_commit_uops_0_prs1; // @[core.scala:143:32]
wire [6:0] _rob_io_commit_uops_0_prs2; // @[core.scala:143:32]
wire [6:0] _rob_io_commit_uops_0_prs3; // @[core.scala:143:32]
wire [4:0] _rob_io_commit_uops_0_ppred; // @[core.scala:143:32]
wire _rob_io_commit_uops_0_prs1_busy; // @[core.scala:143:32]
wire _rob_io_commit_uops_0_prs2_busy; // @[core.scala:143:32]
wire _rob_io_commit_uops_0_prs3_busy; // @[core.scala:143:32]
wire _rob_io_commit_uops_0_ppred_busy; // @[core.scala:143:32]
wire [6:0] _rob_io_commit_uops_0_stale_pdst; // @[core.scala:143:32]
wire _rob_io_commit_uops_0_exception; // @[core.scala:143:32]
wire [63:0] _rob_io_commit_uops_0_exc_cause; // @[core.scala:143:32]
wire _rob_io_commit_uops_0_bypassable; // @[core.scala:143:32]
wire [4:0] _rob_io_commit_uops_0_mem_cmd; // @[core.scala:143:32]
wire [1:0] _rob_io_commit_uops_0_mem_size; // @[core.scala:143:32]
wire _rob_io_commit_uops_0_mem_signed; // @[core.scala:143:32]
wire _rob_io_commit_uops_0_is_fence; // @[core.scala:143:32]
wire _rob_io_commit_uops_0_is_fencei; // @[core.scala:143:32]
wire _rob_io_commit_uops_0_is_amo; // @[core.scala:143:32]
wire _rob_io_commit_uops_0_uses_ldq; // @[core.scala:143:32]
wire _rob_io_commit_uops_0_uses_stq; // @[core.scala:143:32]
wire _rob_io_commit_uops_0_is_sys_pc2epc; // @[core.scala:143:32]
wire _rob_io_commit_uops_0_is_unique; // @[core.scala:143:32]
wire _rob_io_commit_uops_0_flush_on_commit; // @[core.scala:143:32]
wire _rob_io_commit_uops_0_ldst_is_rs1; // @[core.scala:143:32]
wire [5:0] _rob_io_commit_uops_0_ldst; // @[core.scala:143:32]
wire [5:0] _rob_io_commit_uops_0_lrs1; // @[core.scala:143:32]
wire [5:0] _rob_io_commit_uops_0_lrs2; // @[core.scala:143:32]
wire [5:0] _rob_io_commit_uops_0_lrs3; // @[core.scala:143:32]
wire _rob_io_commit_uops_0_ldst_val; // @[core.scala:143:32]
wire [1:0] _rob_io_commit_uops_0_dst_rtype; // @[core.scala:143:32]
wire [1:0] _rob_io_commit_uops_0_lrs1_rtype; // @[core.scala:143:32]
wire [1:0] _rob_io_commit_uops_0_lrs2_rtype; // @[core.scala:143:32]
wire _rob_io_commit_uops_0_frs3_en; // @[core.scala:143:32]
wire _rob_io_commit_uops_0_fp_val; // @[core.scala:143:32]
wire _rob_io_commit_uops_0_fp_single; // @[core.scala:143:32]
wire _rob_io_commit_uops_0_xcpt_pf_if; // @[core.scala:143:32]
wire _rob_io_commit_uops_0_xcpt_ae_if; // @[core.scala:143:32]
wire _rob_io_commit_uops_0_xcpt_ma_if; // @[core.scala:143:32]
wire _rob_io_commit_uops_0_bp_debug_if; // @[core.scala:143:32]
wire _rob_io_commit_uops_0_bp_xcpt_if; // @[core.scala:143:32]
wire [1:0] _rob_io_commit_uops_0_debug_fsrc; // @[core.scala:143:32]
wire [1:0] _rob_io_commit_uops_0_debug_tsrc; // @[core.scala:143:32]
wire [6:0] _rob_io_commit_uops_1_uopc; // @[core.scala:143:32]
wire [31:0] _rob_io_commit_uops_1_inst; // @[core.scala:143:32]
wire [31:0] _rob_io_commit_uops_1_debug_inst; // @[core.scala:143:32]
wire _rob_io_commit_uops_1_is_rvc; // @[core.scala:143:32]
wire [39:0] _rob_io_commit_uops_1_debug_pc; // @[core.scala:143:32]
wire [2:0] _rob_io_commit_uops_1_iq_type; // @[core.scala:143:32]
wire [9:0] _rob_io_commit_uops_1_fu_code; // @[core.scala:143:32]
wire [3:0] _rob_io_commit_uops_1_ctrl_br_type; // @[core.scala:143:32]
wire [1:0] _rob_io_commit_uops_1_ctrl_op1_sel; // @[core.scala:143:32]
wire [2:0] _rob_io_commit_uops_1_ctrl_op2_sel; // @[core.scala:143:32]
wire [2:0] _rob_io_commit_uops_1_ctrl_imm_sel; // @[core.scala:143:32]
wire [4:0] _rob_io_commit_uops_1_ctrl_op_fcn; // @[core.scala:143:32]
wire _rob_io_commit_uops_1_ctrl_fcn_dw; // @[core.scala:143:32]
wire [2:0] _rob_io_commit_uops_1_ctrl_csr_cmd; // @[core.scala:143:32]
wire _rob_io_commit_uops_1_ctrl_is_load; // @[core.scala:143:32]
wire _rob_io_commit_uops_1_ctrl_is_sta; // @[core.scala:143:32]
wire _rob_io_commit_uops_1_ctrl_is_std; // @[core.scala:143:32]
wire [1:0] _rob_io_commit_uops_1_iw_state; // @[core.scala:143:32]
wire _rob_io_commit_uops_1_iw_p1_poisoned; // @[core.scala:143:32]
wire _rob_io_commit_uops_1_iw_p2_poisoned; // @[core.scala:143:32]
wire _rob_io_commit_uops_1_is_br; // @[core.scala:143:32]
wire _rob_io_commit_uops_1_is_jalr; // @[core.scala:143:32]
wire _rob_io_commit_uops_1_is_jal; // @[core.scala:143:32]
wire _rob_io_commit_uops_1_is_sfb; // @[core.scala:143:32]
wire [15:0] _rob_io_commit_uops_1_br_mask; // @[core.scala:143:32]
wire [3:0] _rob_io_commit_uops_1_br_tag; // @[core.scala:143:32]
wire [4:0] _rob_io_commit_uops_1_ftq_idx; // @[core.scala:143:32]
wire _rob_io_commit_uops_1_edge_inst; // @[core.scala:143:32]
wire [5:0] _rob_io_commit_uops_1_pc_lob; // @[core.scala:143:32]
wire _rob_io_commit_uops_1_taken; // @[core.scala:143:32]
wire [19:0] _rob_io_commit_uops_1_imm_packed; // @[core.scala:143:32]
wire [11:0] _rob_io_commit_uops_1_csr_addr; // @[core.scala:143:32]
wire [6:0] _rob_io_commit_uops_1_rob_idx; // @[core.scala:143:32]
wire [4:0] _rob_io_commit_uops_1_ldq_idx; // @[core.scala:143:32]
wire [4:0] _rob_io_commit_uops_1_stq_idx; // @[core.scala:143:32]
wire [1:0] _rob_io_commit_uops_1_rxq_idx; // @[core.scala:143:32]
wire [6:0] _rob_io_commit_uops_1_pdst; // @[core.scala:143:32]
wire [6:0] _rob_io_commit_uops_1_prs1; // @[core.scala:143:32]
wire [6:0] _rob_io_commit_uops_1_prs2; // @[core.scala:143:32]
wire [6:0] _rob_io_commit_uops_1_prs3; // @[core.scala:143:32]
wire [4:0] _rob_io_commit_uops_1_ppred; // @[core.scala:143:32]
wire _rob_io_commit_uops_1_prs1_busy; // @[core.scala:143:32]
wire _rob_io_commit_uops_1_prs2_busy; // @[core.scala:143:32]
wire _rob_io_commit_uops_1_prs3_busy; // @[core.scala:143:32]
wire _rob_io_commit_uops_1_ppred_busy; // @[core.scala:143:32]
wire [6:0] _rob_io_commit_uops_1_stale_pdst; // @[core.scala:143:32]
wire _rob_io_commit_uops_1_exception; // @[core.scala:143:32]
wire [63:0] _rob_io_commit_uops_1_exc_cause; // @[core.scala:143:32]
wire _rob_io_commit_uops_1_bypassable; // @[core.scala:143:32]
wire [4:0] _rob_io_commit_uops_1_mem_cmd; // @[core.scala:143:32]
wire [1:0] _rob_io_commit_uops_1_mem_size; // @[core.scala:143:32]
wire _rob_io_commit_uops_1_mem_signed; // @[core.scala:143:32]
wire _rob_io_commit_uops_1_is_fence; // @[core.scala:143:32]
wire _rob_io_commit_uops_1_is_fencei; // @[core.scala:143:32]
wire _rob_io_commit_uops_1_is_amo; // @[core.scala:143:32]
wire _rob_io_commit_uops_1_uses_ldq; // @[core.scala:143:32]
wire _rob_io_commit_uops_1_uses_stq; // @[core.scala:143:32]
wire _rob_io_commit_uops_1_is_sys_pc2epc; // @[core.scala:143:32]
wire _rob_io_commit_uops_1_is_unique; // @[core.scala:143:32]
wire _rob_io_commit_uops_1_flush_on_commit; // @[core.scala:143:32]
wire _rob_io_commit_uops_1_ldst_is_rs1; // @[core.scala:143:32]
wire [5:0] _rob_io_commit_uops_1_ldst; // @[core.scala:143:32]
wire [5:0] _rob_io_commit_uops_1_lrs1; // @[core.scala:143:32]
wire [5:0] _rob_io_commit_uops_1_lrs2; // @[core.scala:143:32]
wire [5:0] _rob_io_commit_uops_1_lrs3; // @[core.scala:143:32]
wire _rob_io_commit_uops_1_ldst_val; // @[core.scala:143:32]
wire [1:0] _rob_io_commit_uops_1_dst_rtype; // @[core.scala:143:32]
wire [1:0] _rob_io_commit_uops_1_lrs1_rtype; // @[core.scala:143:32]
wire [1:0] _rob_io_commit_uops_1_lrs2_rtype; // @[core.scala:143:32]
wire _rob_io_commit_uops_1_frs3_en; // @[core.scala:143:32]
wire _rob_io_commit_uops_1_fp_val; // @[core.scala:143:32]
wire _rob_io_commit_uops_1_fp_single; // @[core.scala:143:32]
wire _rob_io_commit_uops_1_xcpt_pf_if; // @[core.scala:143:32]
wire _rob_io_commit_uops_1_xcpt_ae_if; // @[core.scala:143:32]
wire _rob_io_commit_uops_1_xcpt_ma_if; // @[core.scala:143:32]
wire _rob_io_commit_uops_1_bp_debug_if; // @[core.scala:143:32]
wire _rob_io_commit_uops_1_bp_xcpt_if; // @[core.scala:143:32]
wire [1:0] _rob_io_commit_uops_1_debug_fsrc; // @[core.scala:143:32]
wire [1:0] _rob_io_commit_uops_1_debug_tsrc; // @[core.scala:143:32]
wire [6:0] _rob_io_commit_uops_2_uopc; // @[core.scala:143:32]
wire [31:0] _rob_io_commit_uops_2_inst; // @[core.scala:143:32]
wire [31:0] _rob_io_commit_uops_2_debug_inst; // @[core.scala:143:32]
wire _rob_io_commit_uops_2_is_rvc; // @[core.scala:143:32]
wire [39:0] _rob_io_commit_uops_2_debug_pc; // @[core.scala:143:32]
wire [2:0] _rob_io_commit_uops_2_iq_type; // @[core.scala:143:32]
wire [9:0] _rob_io_commit_uops_2_fu_code; // @[core.scala:143:32]
wire [3:0] _rob_io_commit_uops_2_ctrl_br_type; // @[core.scala:143:32]
wire [1:0] _rob_io_commit_uops_2_ctrl_op1_sel; // @[core.scala:143:32]
wire [2:0] _rob_io_commit_uops_2_ctrl_op2_sel; // @[core.scala:143:32]
wire [2:0] _rob_io_commit_uops_2_ctrl_imm_sel; // @[core.scala:143:32]
wire [4:0] _rob_io_commit_uops_2_ctrl_op_fcn; // @[core.scala:143:32]
wire _rob_io_commit_uops_2_ctrl_fcn_dw; // @[core.scala:143:32]
wire [2:0] _rob_io_commit_uops_2_ctrl_csr_cmd; // @[core.scala:143:32]
wire _rob_io_commit_uops_2_ctrl_is_load; // @[core.scala:143:32]
wire _rob_io_commit_uops_2_ctrl_is_sta; // @[core.scala:143:32]
wire _rob_io_commit_uops_2_ctrl_is_std; // @[core.scala:143:32]
wire [1:0] _rob_io_commit_uops_2_iw_state; // @[core.scala:143:32]
wire _rob_io_commit_uops_2_iw_p1_poisoned; // @[core.scala:143:32]
wire _rob_io_commit_uops_2_iw_p2_poisoned; // @[core.scala:143:32]
wire _rob_io_commit_uops_2_is_br; // @[core.scala:143:32]
wire _rob_io_commit_uops_2_is_jalr; // @[core.scala:143:32]
wire _rob_io_commit_uops_2_is_jal; // @[core.scala:143:32]
wire _rob_io_commit_uops_2_is_sfb; // @[core.scala:143:32]
wire [15:0] _rob_io_commit_uops_2_br_mask; // @[core.scala:143:32]
wire [3:0] _rob_io_commit_uops_2_br_tag; // @[core.scala:143:32]
wire [4:0] _rob_io_commit_uops_2_ftq_idx; // @[core.scala:143:32]
wire _rob_io_commit_uops_2_edge_inst; // @[core.scala:143:32]
wire [5:0] _rob_io_commit_uops_2_pc_lob; // @[core.scala:143:32]
wire _rob_io_commit_uops_2_taken; // @[core.scala:143:32]
wire [19:0] _rob_io_commit_uops_2_imm_packed; // @[core.scala:143:32]
wire [11:0] _rob_io_commit_uops_2_csr_addr; // @[core.scala:143:32]
wire [6:0] _rob_io_commit_uops_2_rob_idx; // @[core.scala:143:32]
wire [4:0] _rob_io_commit_uops_2_ldq_idx; // @[core.scala:143:32]
wire [4:0] _rob_io_commit_uops_2_stq_idx; // @[core.scala:143:32]
wire [1:0] _rob_io_commit_uops_2_rxq_idx; // @[core.scala:143:32]
wire [6:0] _rob_io_commit_uops_2_pdst; // @[core.scala:143:32]
wire [6:0] _rob_io_commit_uops_2_prs1; // @[core.scala:143:32]
wire [6:0] _rob_io_commit_uops_2_prs2; // @[core.scala:143:32]
wire [6:0] _rob_io_commit_uops_2_prs3; // @[core.scala:143:32]
wire [4:0] _rob_io_commit_uops_2_ppred; // @[core.scala:143:32]
wire _rob_io_commit_uops_2_prs1_busy; // @[core.scala:143:32]
wire _rob_io_commit_uops_2_prs2_busy; // @[core.scala:143:32]
wire _rob_io_commit_uops_2_prs3_busy; // @[core.scala:143:32]
wire _rob_io_commit_uops_2_ppred_busy; // @[core.scala:143:32]
wire [6:0] _rob_io_commit_uops_2_stale_pdst; // @[core.scala:143:32]
wire _rob_io_commit_uops_2_exception; // @[core.scala:143:32]
wire [63:0] _rob_io_commit_uops_2_exc_cause; // @[core.scala:143:32]
wire _rob_io_commit_uops_2_bypassable; // @[core.scala:143:32]
wire [4:0] _rob_io_commit_uops_2_mem_cmd; // @[core.scala:143:32]
wire [1:0] _rob_io_commit_uops_2_mem_size; // @[core.scala:143:32]
wire _rob_io_commit_uops_2_mem_signed; // @[core.scala:143:32]
wire _rob_io_commit_uops_2_is_fence; // @[core.scala:143:32]
wire _rob_io_commit_uops_2_is_fencei; // @[core.scala:143:32]
wire _rob_io_commit_uops_2_is_amo; // @[core.scala:143:32]
wire _rob_io_commit_uops_2_uses_ldq; // @[core.scala:143:32]
wire _rob_io_commit_uops_2_uses_stq; // @[core.scala:143:32]
wire _rob_io_commit_uops_2_is_sys_pc2epc; // @[core.scala:143:32]
wire _rob_io_commit_uops_2_is_unique; // @[core.scala:143:32]
wire _rob_io_commit_uops_2_flush_on_commit; // @[core.scala:143:32]
wire _rob_io_commit_uops_2_ldst_is_rs1; // @[core.scala:143:32]
wire [5:0] _rob_io_commit_uops_2_ldst; // @[core.scala:143:32]
wire [5:0] _rob_io_commit_uops_2_lrs1; // @[core.scala:143:32]
wire [5:0] _rob_io_commit_uops_2_lrs2; // @[core.scala:143:32]
wire [5:0] _rob_io_commit_uops_2_lrs3; // @[core.scala:143:32]
wire _rob_io_commit_uops_2_ldst_val; // @[core.scala:143:32]
wire [1:0] _rob_io_commit_uops_2_dst_rtype; // @[core.scala:143:32]
wire [1:0] _rob_io_commit_uops_2_lrs1_rtype; // @[core.scala:143:32]
wire [1:0] _rob_io_commit_uops_2_lrs2_rtype; // @[core.scala:143:32]
wire _rob_io_commit_uops_2_frs3_en; // @[core.scala:143:32]
wire _rob_io_commit_uops_2_fp_val; // @[core.scala:143:32]
wire _rob_io_commit_uops_2_fp_single; // @[core.scala:143:32]
wire _rob_io_commit_uops_2_xcpt_pf_if; // @[core.scala:143:32]
wire _rob_io_commit_uops_2_xcpt_ae_if; // @[core.scala:143:32]
wire _rob_io_commit_uops_2_xcpt_ma_if; // @[core.scala:143:32]
wire _rob_io_commit_uops_2_bp_debug_if; // @[core.scala:143:32]
wire _rob_io_commit_uops_2_bp_xcpt_if; // @[core.scala:143:32]
wire [1:0] _rob_io_commit_uops_2_debug_fsrc; // @[core.scala:143:32]
wire [1:0] _rob_io_commit_uops_2_debug_tsrc; // @[core.scala:143:32]
wire _rob_io_commit_fflags_valid; // @[core.scala:143:32]
wire [4:0] _rob_io_commit_fflags_bits; // @[core.scala:143:32]
wire _rob_io_commit_rbk_valids_0; // @[core.scala:143:32]
wire _rob_io_commit_rbk_valids_1; // @[core.scala:143:32]
wire _rob_io_commit_rbk_valids_2; // @[core.scala:143:32]
wire _rob_io_commit_rollback; // @[core.scala:143:32]
wire _rob_io_com_xcpt_valid; // @[core.scala:143:32]
wire [4:0] _rob_io_com_xcpt_bits_ftq_idx; // @[core.scala:143:32]
wire _rob_io_com_xcpt_bits_edge_inst; // @[core.scala:143:32]
wire [5:0] _rob_io_com_xcpt_bits_pc_lob; // @[core.scala:143:32]
wire [63:0] _rob_io_com_xcpt_bits_cause; // @[core.scala:143:32]
wire [63:0] _rob_io_com_xcpt_bits_badvaddr; // @[core.scala:143:32]
wire _rob_io_flush_valid; // @[core.scala:143:32]
wire [4:0] _rob_io_flush_bits_ftq_idx; // @[core.scala:143:32]
wire _rob_io_flush_bits_edge_inst; // @[core.scala:143:32]
wire _rob_io_flush_bits_is_rvc; // @[core.scala:143:32]
wire [5:0] _rob_io_flush_bits_pc_lob; // @[core.scala:143:32]
wire [2:0] _rob_io_flush_bits_flush_typ; // @[core.scala:143:32]
wire _rob_io_empty; // @[core.scala:143:32]
wire _rob_io_ready; // @[core.scala:143:32]
wire _rob_io_flush_frontend; // @[core.scala:143:32]
wire [6:0] _iregister_read_io_rf_read_ports_0_addr; // @[core.scala:135:32]
wire [6:0] _iregister_read_io_rf_read_ports_1_addr; // @[core.scala:135:32]
wire [6:0] _iregister_read_io_rf_read_ports_2_addr; // @[core.scala:135:32]
wire [6:0] _iregister_read_io_rf_read_ports_3_addr; // @[core.scala:135:32]
wire [6:0] _iregister_read_io_rf_read_ports_4_addr; // @[core.scala:135:32]
wire [6:0] _iregister_read_io_rf_read_ports_5_addr; // @[core.scala:135:32]
wire [6:0] _iregister_read_io_rf_read_ports_6_addr; // @[core.scala:135:32]
wire [6:0] _iregister_read_io_rf_read_ports_7_addr; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_0_valid; // @[core.scala:135:32]
wire [6:0] _iregister_read_io_exe_reqs_0_bits_uop_uopc; // @[core.scala:135:32]
wire [31:0] _iregister_read_io_exe_reqs_0_bits_uop_inst; // @[core.scala:135:32]
wire [31:0] _iregister_read_io_exe_reqs_0_bits_uop_debug_inst; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_0_bits_uop_is_rvc; // @[core.scala:135:32]
wire [39:0] _iregister_read_io_exe_reqs_0_bits_uop_debug_pc; // @[core.scala:135:32]
wire [2:0] _iregister_read_io_exe_reqs_0_bits_uop_iq_type; // @[core.scala:135:32]
wire [9:0] _iregister_read_io_exe_reqs_0_bits_uop_fu_code; // @[core.scala:135:32]
wire [3:0] _iregister_read_io_exe_reqs_0_bits_uop_ctrl_br_type; // @[core.scala:135:32]
wire [1:0] _iregister_read_io_exe_reqs_0_bits_uop_ctrl_op1_sel; // @[core.scala:135:32]
wire [2:0] _iregister_read_io_exe_reqs_0_bits_uop_ctrl_op2_sel; // @[core.scala:135:32]
wire [2:0] _iregister_read_io_exe_reqs_0_bits_uop_ctrl_imm_sel; // @[core.scala:135:32]
wire [4:0] _iregister_read_io_exe_reqs_0_bits_uop_ctrl_op_fcn; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_0_bits_uop_ctrl_fcn_dw; // @[core.scala:135:32]
wire [2:0] _iregister_read_io_exe_reqs_0_bits_uop_ctrl_csr_cmd; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_0_bits_uop_ctrl_is_load; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_0_bits_uop_ctrl_is_sta; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_0_bits_uop_ctrl_is_std; // @[core.scala:135:32]
wire [1:0] _iregister_read_io_exe_reqs_0_bits_uop_iw_state; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_0_bits_uop_iw_p1_poisoned; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_0_bits_uop_iw_p2_poisoned; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_0_bits_uop_is_br; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_0_bits_uop_is_jalr; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_0_bits_uop_is_jal; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_0_bits_uop_is_sfb; // @[core.scala:135:32]
wire [15:0] _iregister_read_io_exe_reqs_0_bits_uop_br_mask; // @[core.scala:135:32]
wire [3:0] _iregister_read_io_exe_reqs_0_bits_uop_br_tag; // @[core.scala:135:32]
wire [4:0] _iregister_read_io_exe_reqs_0_bits_uop_ftq_idx; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_0_bits_uop_edge_inst; // @[core.scala:135:32]
wire [5:0] _iregister_read_io_exe_reqs_0_bits_uop_pc_lob; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_0_bits_uop_taken; // @[core.scala:135:32]
wire [19:0] _iregister_read_io_exe_reqs_0_bits_uop_imm_packed; // @[core.scala:135:32]
wire [11:0] _iregister_read_io_exe_reqs_0_bits_uop_csr_addr; // @[core.scala:135:32]
wire [6:0] _iregister_read_io_exe_reqs_0_bits_uop_rob_idx; // @[core.scala:135:32]
wire [4:0] _iregister_read_io_exe_reqs_0_bits_uop_ldq_idx; // @[core.scala:135:32]
wire [4:0] _iregister_read_io_exe_reqs_0_bits_uop_stq_idx; // @[core.scala:135:32]
wire [1:0] _iregister_read_io_exe_reqs_0_bits_uop_rxq_idx; // @[core.scala:135:32]
wire [6:0] _iregister_read_io_exe_reqs_0_bits_uop_pdst; // @[core.scala:135:32]
wire [6:0] _iregister_read_io_exe_reqs_0_bits_uop_prs1; // @[core.scala:135:32]
wire [6:0] _iregister_read_io_exe_reqs_0_bits_uop_prs2; // @[core.scala:135:32]
wire [6:0] _iregister_read_io_exe_reqs_0_bits_uop_prs3; // @[core.scala:135:32]
wire [4:0] _iregister_read_io_exe_reqs_0_bits_uop_ppred; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_0_bits_uop_prs1_busy; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_0_bits_uop_prs2_busy; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_0_bits_uop_prs3_busy; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_0_bits_uop_ppred_busy; // @[core.scala:135:32]
wire [6:0] _iregister_read_io_exe_reqs_0_bits_uop_stale_pdst; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_0_bits_uop_exception; // @[core.scala:135:32]
wire [63:0] _iregister_read_io_exe_reqs_0_bits_uop_exc_cause; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_0_bits_uop_bypassable; // @[core.scala:135:32]
wire [4:0] _iregister_read_io_exe_reqs_0_bits_uop_mem_cmd; // @[core.scala:135:32]
wire [1:0] _iregister_read_io_exe_reqs_0_bits_uop_mem_size; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_0_bits_uop_mem_signed; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_0_bits_uop_is_fence; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_0_bits_uop_is_fencei; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_0_bits_uop_is_amo; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_0_bits_uop_uses_ldq; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_0_bits_uop_uses_stq; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_0_bits_uop_is_sys_pc2epc; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_0_bits_uop_is_unique; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_0_bits_uop_flush_on_commit; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_0_bits_uop_ldst_is_rs1; // @[core.scala:135:32]
wire [5:0] _iregister_read_io_exe_reqs_0_bits_uop_ldst; // @[core.scala:135:32]
wire [5:0] _iregister_read_io_exe_reqs_0_bits_uop_lrs1; // @[core.scala:135:32]
wire [5:0] _iregister_read_io_exe_reqs_0_bits_uop_lrs2; // @[core.scala:135:32]
wire [5:0] _iregister_read_io_exe_reqs_0_bits_uop_lrs3; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_0_bits_uop_ldst_val; // @[core.scala:135:32]
wire [1:0] _iregister_read_io_exe_reqs_0_bits_uop_dst_rtype; // @[core.scala:135:32]
wire [1:0] _iregister_read_io_exe_reqs_0_bits_uop_lrs1_rtype; // @[core.scala:135:32]
wire [1:0] _iregister_read_io_exe_reqs_0_bits_uop_lrs2_rtype; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_0_bits_uop_frs3_en; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_0_bits_uop_fp_val; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_0_bits_uop_fp_single; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_0_bits_uop_xcpt_pf_if; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_0_bits_uop_xcpt_ae_if; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_0_bits_uop_xcpt_ma_if; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_0_bits_uop_bp_debug_if; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_0_bits_uop_bp_xcpt_if; // @[core.scala:135:32]
wire [1:0] _iregister_read_io_exe_reqs_0_bits_uop_debug_fsrc; // @[core.scala:135:32]
wire [1:0] _iregister_read_io_exe_reqs_0_bits_uop_debug_tsrc; // @[core.scala:135:32]
wire [63:0] _iregister_read_io_exe_reqs_0_bits_rs1_data; // @[core.scala:135:32]
wire [63:0] _iregister_read_io_exe_reqs_0_bits_rs2_data; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_1_valid; // @[core.scala:135:32]
wire [6:0] _iregister_read_io_exe_reqs_1_bits_uop_uopc; // @[core.scala:135:32]
wire [31:0] _iregister_read_io_exe_reqs_1_bits_uop_inst; // @[core.scala:135:32]
wire [31:0] _iregister_read_io_exe_reqs_1_bits_uop_debug_inst; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_1_bits_uop_is_rvc; // @[core.scala:135:32]
wire [39:0] _iregister_read_io_exe_reqs_1_bits_uop_debug_pc; // @[core.scala:135:32]
wire [2:0] _iregister_read_io_exe_reqs_1_bits_uop_iq_type; // @[core.scala:135:32]
wire [9:0] _iregister_read_io_exe_reqs_1_bits_uop_fu_code; // @[core.scala:135:32]
wire [3:0] _iregister_read_io_exe_reqs_1_bits_uop_ctrl_br_type; // @[core.scala:135:32]
wire [1:0] _iregister_read_io_exe_reqs_1_bits_uop_ctrl_op1_sel; // @[core.scala:135:32]
wire [2:0] _iregister_read_io_exe_reqs_1_bits_uop_ctrl_op2_sel; // @[core.scala:135:32]
wire [2:0] _iregister_read_io_exe_reqs_1_bits_uop_ctrl_imm_sel; // @[core.scala:135:32]
wire [4:0] _iregister_read_io_exe_reqs_1_bits_uop_ctrl_op_fcn; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_1_bits_uop_ctrl_fcn_dw; // @[core.scala:135:32]
wire [2:0] _iregister_read_io_exe_reqs_1_bits_uop_ctrl_csr_cmd; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_1_bits_uop_ctrl_is_load; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_1_bits_uop_ctrl_is_sta; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_1_bits_uop_ctrl_is_std; // @[core.scala:135:32]
wire [1:0] _iregister_read_io_exe_reqs_1_bits_uop_iw_state; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_1_bits_uop_iw_p1_poisoned; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_1_bits_uop_iw_p2_poisoned; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_1_bits_uop_is_br; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_1_bits_uop_is_jalr; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_1_bits_uop_is_jal; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_1_bits_uop_is_sfb; // @[core.scala:135:32]
wire [15:0] _iregister_read_io_exe_reqs_1_bits_uop_br_mask; // @[core.scala:135:32]
wire [3:0] _iregister_read_io_exe_reqs_1_bits_uop_br_tag; // @[core.scala:135:32]
wire [4:0] _iregister_read_io_exe_reqs_1_bits_uop_ftq_idx; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_1_bits_uop_edge_inst; // @[core.scala:135:32]
wire [5:0] _iregister_read_io_exe_reqs_1_bits_uop_pc_lob; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_1_bits_uop_taken; // @[core.scala:135:32]
wire [19:0] _iregister_read_io_exe_reqs_1_bits_uop_imm_packed; // @[core.scala:135:32]
wire [11:0] _iregister_read_io_exe_reqs_1_bits_uop_csr_addr; // @[core.scala:135:32]
wire [6:0] _iregister_read_io_exe_reqs_1_bits_uop_rob_idx; // @[core.scala:135:32]
wire [4:0] _iregister_read_io_exe_reqs_1_bits_uop_ldq_idx; // @[core.scala:135:32]
wire [4:0] _iregister_read_io_exe_reqs_1_bits_uop_stq_idx; // @[core.scala:135:32]
wire [1:0] _iregister_read_io_exe_reqs_1_bits_uop_rxq_idx; // @[core.scala:135:32]
wire [6:0] _iregister_read_io_exe_reqs_1_bits_uop_pdst; // @[core.scala:135:32]
wire [6:0] _iregister_read_io_exe_reqs_1_bits_uop_prs1; // @[core.scala:135:32]
wire [6:0] _iregister_read_io_exe_reqs_1_bits_uop_prs2; // @[core.scala:135:32]
wire [6:0] _iregister_read_io_exe_reqs_1_bits_uop_prs3; // @[core.scala:135:32]
wire [4:0] _iregister_read_io_exe_reqs_1_bits_uop_ppred; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_1_bits_uop_prs1_busy; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_1_bits_uop_prs2_busy; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_1_bits_uop_prs3_busy; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_1_bits_uop_ppred_busy; // @[core.scala:135:32]
wire [6:0] _iregister_read_io_exe_reqs_1_bits_uop_stale_pdst; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_1_bits_uop_exception; // @[core.scala:135:32]
wire [63:0] _iregister_read_io_exe_reqs_1_bits_uop_exc_cause; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_1_bits_uop_bypassable; // @[core.scala:135:32]
wire [4:0] _iregister_read_io_exe_reqs_1_bits_uop_mem_cmd; // @[core.scala:135:32]
wire [1:0] _iregister_read_io_exe_reqs_1_bits_uop_mem_size; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_1_bits_uop_mem_signed; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_1_bits_uop_is_fence; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_1_bits_uop_is_fencei; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_1_bits_uop_is_amo; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_1_bits_uop_uses_ldq; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_1_bits_uop_uses_stq; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_1_bits_uop_is_sys_pc2epc; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_1_bits_uop_is_unique; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_1_bits_uop_flush_on_commit; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_1_bits_uop_ldst_is_rs1; // @[core.scala:135:32]
wire [5:0] _iregister_read_io_exe_reqs_1_bits_uop_ldst; // @[core.scala:135:32]
wire [5:0] _iregister_read_io_exe_reqs_1_bits_uop_lrs1; // @[core.scala:135:32]
wire [5:0] _iregister_read_io_exe_reqs_1_bits_uop_lrs2; // @[core.scala:135:32]
wire [5:0] _iregister_read_io_exe_reqs_1_bits_uop_lrs3; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_1_bits_uop_ldst_val; // @[core.scala:135:32]
wire [1:0] _iregister_read_io_exe_reqs_1_bits_uop_dst_rtype; // @[core.scala:135:32]
wire [1:0] _iregister_read_io_exe_reqs_1_bits_uop_lrs1_rtype; // @[core.scala:135:32]
wire [1:0] _iregister_read_io_exe_reqs_1_bits_uop_lrs2_rtype; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_1_bits_uop_frs3_en; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_1_bits_uop_fp_val; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_1_bits_uop_fp_single; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_1_bits_uop_xcpt_pf_if; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_1_bits_uop_xcpt_ae_if; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_1_bits_uop_xcpt_ma_if; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_1_bits_uop_bp_debug_if; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_1_bits_uop_bp_xcpt_if; // @[core.scala:135:32]
wire [1:0] _iregister_read_io_exe_reqs_1_bits_uop_debug_fsrc; // @[core.scala:135:32]
wire [1:0] _iregister_read_io_exe_reqs_1_bits_uop_debug_tsrc; // @[core.scala:135:32]
wire [63:0] _iregister_read_io_exe_reqs_1_bits_rs1_data; // @[core.scala:135:32]
wire [63:0] _iregister_read_io_exe_reqs_1_bits_rs2_data; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_2_valid; // @[core.scala:135:32]
wire [6:0] _iregister_read_io_exe_reqs_2_bits_uop_uopc; // @[core.scala:135:32]
wire [31:0] _iregister_read_io_exe_reqs_2_bits_uop_inst; // @[core.scala:135:32]
wire [31:0] _iregister_read_io_exe_reqs_2_bits_uop_debug_inst; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_2_bits_uop_is_rvc; // @[core.scala:135:32]
wire [39:0] _iregister_read_io_exe_reqs_2_bits_uop_debug_pc; // @[core.scala:135:32]
wire [2:0] _iregister_read_io_exe_reqs_2_bits_uop_iq_type; // @[core.scala:135:32]
wire [9:0] _iregister_read_io_exe_reqs_2_bits_uop_fu_code; // @[core.scala:135:32]
wire [3:0] _iregister_read_io_exe_reqs_2_bits_uop_ctrl_br_type; // @[core.scala:135:32]
wire [1:0] _iregister_read_io_exe_reqs_2_bits_uop_ctrl_op1_sel; // @[core.scala:135:32]
wire [2:0] _iregister_read_io_exe_reqs_2_bits_uop_ctrl_op2_sel; // @[core.scala:135:32]
wire [2:0] _iregister_read_io_exe_reqs_2_bits_uop_ctrl_imm_sel; // @[core.scala:135:32]
wire [4:0] _iregister_read_io_exe_reqs_2_bits_uop_ctrl_op_fcn; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_2_bits_uop_ctrl_fcn_dw; // @[core.scala:135:32]
wire [2:0] _iregister_read_io_exe_reqs_2_bits_uop_ctrl_csr_cmd; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_2_bits_uop_ctrl_is_load; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_2_bits_uop_ctrl_is_sta; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_2_bits_uop_ctrl_is_std; // @[core.scala:135:32]
wire [1:0] _iregister_read_io_exe_reqs_2_bits_uop_iw_state; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_2_bits_uop_iw_p1_poisoned; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_2_bits_uop_iw_p2_poisoned; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_2_bits_uop_is_br; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_2_bits_uop_is_jalr; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_2_bits_uop_is_jal; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_2_bits_uop_is_sfb; // @[core.scala:135:32]
wire [15:0] _iregister_read_io_exe_reqs_2_bits_uop_br_mask; // @[core.scala:135:32]
wire [3:0] _iregister_read_io_exe_reqs_2_bits_uop_br_tag; // @[core.scala:135:32]
wire [4:0] _iregister_read_io_exe_reqs_2_bits_uop_ftq_idx; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_2_bits_uop_edge_inst; // @[core.scala:135:32]
wire [5:0] _iregister_read_io_exe_reqs_2_bits_uop_pc_lob; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_2_bits_uop_taken; // @[core.scala:135:32]
wire [19:0] _iregister_read_io_exe_reqs_2_bits_uop_imm_packed; // @[core.scala:135:32]
wire [11:0] _iregister_read_io_exe_reqs_2_bits_uop_csr_addr; // @[core.scala:135:32]
wire [6:0] _iregister_read_io_exe_reqs_2_bits_uop_rob_idx; // @[core.scala:135:32]
wire [4:0] _iregister_read_io_exe_reqs_2_bits_uop_ldq_idx; // @[core.scala:135:32]
wire [4:0] _iregister_read_io_exe_reqs_2_bits_uop_stq_idx; // @[core.scala:135:32]
wire [1:0] _iregister_read_io_exe_reqs_2_bits_uop_rxq_idx; // @[core.scala:135:32]
wire [6:0] _iregister_read_io_exe_reqs_2_bits_uop_pdst; // @[core.scala:135:32]
wire [6:0] _iregister_read_io_exe_reqs_2_bits_uop_prs1; // @[core.scala:135:32]
wire [6:0] _iregister_read_io_exe_reqs_2_bits_uop_prs2; // @[core.scala:135:32]
wire [6:0] _iregister_read_io_exe_reqs_2_bits_uop_prs3; // @[core.scala:135:32]
wire [4:0] _iregister_read_io_exe_reqs_2_bits_uop_ppred; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_2_bits_uop_prs1_busy; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_2_bits_uop_prs2_busy; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_2_bits_uop_prs3_busy; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_2_bits_uop_ppred_busy; // @[core.scala:135:32]
wire [6:0] _iregister_read_io_exe_reqs_2_bits_uop_stale_pdst; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_2_bits_uop_exception; // @[core.scala:135:32]
wire [63:0] _iregister_read_io_exe_reqs_2_bits_uop_exc_cause; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_2_bits_uop_bypassable; // @[core.scala:135:32]
wire [4:0] _iregister_read_io_exe_reqs_2_bits_uop_mem_cmd; // @[core.scala:135:32]
wire [1:0] _iregister_read_io_exe_reqs_2_bits_uop_mem_size; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_2_bits_uop_mem_signed; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_2_bits_uop_is_fence; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_2_bits_uop_is_fencei; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_2_bits_uop_is_amo; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_2_bits_uop_uses_ldq; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_2_bits_uop_uses_stq; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_2_bits_uop_is_sys_pc2epc; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_2_bits_uop_is_unique; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_2_bits_uop_flush_on_commit; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_2_bits_uop_ldst_is_rs1; // @[core.scala:135:32]
wire [5:0] _iregister_read_io_exe_reqs_2_bits_uop_ldst; // @[core.scala:135:32]
wire [5:0] _iregister_read_io_exe_reqs_2_bits_uop_lrs1; // @[core.scala:135:32]
wire [5:0] _iregister_read_io_exe_reqs_2_bits_uop_lrs2; // @[core.scala:135:32]
wire [5:0] _iregister_read_io_exe_reqs_2_bits_uop_lrs3; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_2_bits_uop_ldst_val; // @[core.scala:135:32]
wire [1:0] _iregister_read_io_exe_reqs_2_bits_uop_dst_rtype; // @[core.scala:135:32]
wire [1:0] _iregister_read_io_exe_reqs_2_bits_uop_lrs1_rtype; // @[core.scala:135:32]
wire [1:0] _iregister_read_io_exe_reqs_2_bits_uop_lrs2_rtype; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_2_bits_uop_frs3_en; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_2_bits_uop_fp_val; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_2_bits_uop_fp_single; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_2_bits_uop_xcpt_pf_if; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_2_bits_uop_xcpt_ae_if; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_2_bits_uop_xcpt_ma_if; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_2_bits_uop_bp_debug_if; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_2_bits_uop_bp_xcpt_if; // @[core.scala:135:32]
wire [1:0] _iregister_read_io_exe_reqs_2_bits_uop_debug_fsrc; // @[core.scala:135:32]
wire [1:0] _iregister_read_io_exe_reqs_2_bits_uop_debug_tsrc; // @[core.scala:135:32]
wire [63:0] _iregister_read_io_exe_reqs_2_bits_rs1_data; // @[core.scala:135:32]
wire [63:0] _iregister_read_io_exe_reqs_2_bits_rs2_data; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_3_valid; // @[core.scala:135:32]
wire [6:0] _iregister_read_io_exe_reqs_3_bits_uop_uopc; // @[core.scala:135:32]
wire [31:0] _iregister_read_io_exe_reqs_3_bits_uop_inst; // @[core.scala:135:32]
wire [31:0] _iregister_read_io_exe_reqs_3_bits_uop_debug_inst; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_3_bits_uop_is_rvc; // @[core.scala:135:32]
wire [39:0] _iregister_read_io_exe_reqs_3_bits_uop_debug_pc; // @[core.scala:135:32]
wire [2:0] _iregister_read_io_exe_reqs_3_bits_uop_iq_type; // @[core.scala:135:32]
wire [9:0] _iregister_read_io_exe_reqs_3_bits_uop_fu_code; // @[core.scala:135:32]
wire [3:0] _iregister_read_io_exe_reqs_3_bits_uop_ctrl_br_type; // @[core.scala:135:32]
wire [1:0] _iregister_read_io_exe_reqs_3_bits_uop_ctrl_op1_sel; // @[core.scala:135:32]
wire [2:0] _iregister_read_io_exe_reqs_3_bits_uop_ctrl_op2_sel; // @[core.scala:135:32]
wire [2:0] _iregister_read_io_exe_reqs_3_bits_uop_ctrl_imm_sel; // @[core.scala:135:32]
wire [4:0] _iregister_read_io_exe_reqs_3_bits_uop_ctrl_op_fcn; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_3_bits_uop_ctrl_fcn_dw; // @[core.scala:135:32]
wire [2:0] _iregister_read_io_exe_reqs_3_bits_uop_ctrl_csr_cmd; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_3_bits_uop_ctrl_is_load; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_3_bits_uop_ctrl_is_sta; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_3_bits_uop_ctrl_is_std; // @[core.scala:135:32]
wire [1:0] _iregister_read_io_exe_reqs_3_bits_uop_iw_state; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_3_bits_uop_iw_p1_poisoned; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_3_bits_uop_iw_p2_poisoned; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_3_bits_uop_is_br; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_3_bits_uop_is_jalr; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_3_bits_uop_is_jal; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_3_bits_uop_is_sfb; // @[core.scala:135:32]
wire [15:0] _iregister_read_io_exe_reqs_3_bits_uop_br_mask; // @[core.scala:135:32]
wire [3:0] _iregister_read_io_exe_reqs_3_bits_uop_br_tag; // @[core.scala:135:32]
wire [4:0] _iregister_read_io_exe_reqs_3_bits_uop_ftq_idx; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_3_bits_uop_edge_inst; // @[core.scala:135:32]
wire [5:0] _iregister_read_io_exe_reqs_3_bits_uop_pc_lob; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_3_bits_uop_taken; // @[core.scala:135:32]
wire [19:0] _iregister_read_io_exe_reqs_3_bits_uop_imm_packed; // @[core.scala:135:32]
wire [11:0] _iregister_read_io_exe_reqs_3_bits_uop_csr_addr; // @[core.scala:135:32]
wire [6:0] _iregister_read_io_exe_reqs_3_bits_uop_rob_idx; // @[core.scala:135:32]
wire [4:0] _iregister_read_io_exe_reqs_3_bits_uop_ldq_idx; // @[core.scala:135:32]
wire [4:0] _iregister_read_io_exe_reqs_3_bits_uop_stq_idx; // @[core.scala:135:32]
wire [1:0] _iregister_read_io_exe_reqs_3_bits_uop_rxq_idx; // @[core.scala:135:32]
wire [6:0] _iregister_read_io_exe_reqs_3_bits_uop_pdst; // @[core.scala:135:32]
wire [6:0] _iregister_read_io_exe_reqs_3_bits_uop_prs1; // @[core.scala:135:32]
wire [6:0] _iregister_read_io_exe_reqs_3_bits_uop_prs2; // @[core.scala:135:32]
wire [6:0] _iregister_read_io_exe_reqs_3_bits_uop_prs3; // @[core.scala:135:32]
wire [4:0] _iregister_read_io_exe_reqs_3_bits_uop_ppred; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_3_bits_uop_prs1_busy; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_3_bits_uop_prs2_busy; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_3_bits_uop_prs3_busy; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_3_bits_uop_ppred_busy; // @[core.scala:135:32]
wire [6:0] _iregister_read_io_exe_reqs_3_bits_uop_stale_pdst; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_3_bits_uop_exception; // @[core.scala:135:32]
wire [63:0] _iregister_read_io_exe_reqs_3_bits_uop_exc_cause; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_3_bits_uop_bypassable; // @[core.scala:135:32]
wire [4:0] _iregister_read_io_exe_reqs_3_bits_uop_mem_cmd; // @[core.scala:135:32]
wire [1:0] _iregister_read_io_exe_reqs_3_bits_uop_mem_size; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_3_bits_uop_mem_signed; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_3_bits_uop_is_fence; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_3_bits_uop_is_fencei; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_3_bits_uop_is_amo; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_3_bits_uop_uses_ldq; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_3_bits_uop_uses_stq; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_3_bits_uop_is_sys_pc2epc; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_3_bits_uop_is_unique; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_3_bits_uop_flush_on_commit; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_3_bits_uop_ldst_is_rs1; // @[core.scala:135:32]
wire [5:0] _iregister_read_io_exe_reqs_3_bits_uop_ldst; // @[core.scala:135:32]
wire [5:0] _iregister_read_io_exe_reqs_3_bits_uop_lrs1; // @[core.scala:135:32]
wire [5:0] _iregister_read_io_exe_reqs_3_bits_uop_lrs2; // @[core.scala:135:32]
wire [5:0] _iregister_read_io_exe_reqs_3_bits_uop_lrs3; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_3_bits_uop_ldst_val; // @[core.scala:135:32]
wire [1:0] _iregister_read_io_exe_reqs_3_bits_uop_dst_rtype; // @[core.scala:135:32]
wire [1:0] _iregister_read_io_exe_reqs_3_bits_uop_lrs1_rtype; // @[core.scala:135:32]
wire [1:0] _iregister_read_io_exe_reqs_3_bits_uop_lrs2_rtype; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_3_bits_uop_frs3_en; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_3_bits_uop_fp_val; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_3_bits_uop_fp_single; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_3_bits_uop_xcpt_pf_if; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_3_bits_uop_xcpt_ae_if; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_3_bits_uop_xcpt_ma_if; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_3_bits_uop_bp_debug_if; // @[core.scala:135:32]
wire _iregister_read_io_exe_reqs_3_bits_uop_bp_xcpt_if; // @[core.scala:135:32]
wire [1:0] _iregister_read_io_exe_reqs_3_bits_uop_debug_fsrc; // @[core.scala:135:32]
wire [1:0] _iregister_read_io_exe_reqs_3_bits_uop_debug_tsrc; // @[core.scala:135:32]
wire [63:0] _iregister_read_io_exe_reqs_3_bits_rs1_data; // @[core.scala:135:32]
wire [63:0] _iregister_read_io_exe_reqs_3_bits_rs2_data; // @[core.scala:135:32]
wire _ll_wbarb_io_in_1_ready; // @[core.scala:132:32]
wire _ll_wbarb_io_out_valid; // @[core.scala:132:32]
wire [6:0] _ll_wbarb_io_out_bits_uop_uopc; // @[core.scala:132:32]
wire [31:0] _ll_wbarb_io_out_bits_uop_inst; // @[core.scala:132:32]
wire [31:0] _ll_wbarb_io_out_bits_uop_debug_inst; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_uop_is_rvc; // @[core.scala:132:32]
wire [39:0] _ll_wbarb_io_out_bits_uop_debug_pc; // @[core.scala:132:32]
wire [2:0] _ll_wbarb_io_out_bits_uop_iq_type; // @[core.scala:132:32]
wire [9:0] _ll_wbarb_io_out_bits_uop_fu_code; // @[core.scala:132:32]
wire [3:0] _ll_wbarb_io_out_bits_uop_ctrl_br_type; // @[core.scala:132:32]
wire [1:0] _ll_wbarb_io_out_bits_uop_ctrl_op1_sel; // @[core.scala:132:32]
wire [2:0] _ll_wbarb_io_out_bits_uop_ctrl_op2_sel; // @[core.scala:132:32]
wire [2:0] _ll_wbarb_io_out_bits_uop_ctrl_imm_sel; // @[core.scala:132:32]
wire [4:0] _ll_wbarb_io_out_bits_uop_ctrl_op_fcn; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_uop_ctrl_fcn_dw; // @[core.scala:132:32]
wire [2:0] _ll_wbarb_io_out_bits_uop_ctrl_csr_cmd; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_uop_ctrl_is_load; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_uop_ctrl_is_sta; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_uop_ctrl_is_std; // @[core.scala:132:32]
wire [1:0] _ll_wbarb_io_out_bits_uop_iw_state; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_uop_iw_p1_poisoned; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_uop_iw_p2_poisoned; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_uop_is_br; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_uop_is_jalr; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_uop_is_jal; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_uop_is_sfb; // @[core.scala:132:32]
wire [15:0] _ll_wbarb_io_out_bits_uop_br_mask; // @[core.scala:132:32]
wire [3:0] _ll_wbarb_io_out_bits_uop_br_tag; // @[core.scala:132:32]
wire [4:0] _ll_wbarb_io_out_bits_uop_ftq_idx; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_uop_edge_inst; // @[core.scala:132:32]
wire [5:0] _ll_wbarb_io_out_bits_uop_pc_lob; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_uop_taken; // @[core.scala:132:32]
wire [19:0] _ll_wbarb_io_out_bits_uop_imm_packed; // @[core.scala:132:32]
wire [11:0] _ll_wbarb_io_out_bits_uop_csr_addr; // @[core.scala:132:32]
wire [6:0] _ll_wbarb_io_out_bits_uop_rob_idx; // @[core.scala:132:32]
wire [4:0] _ll_wbarb_io_out_bits_uop_ldq_idx; // @[core.scala:132:32]
wire [4:0] _ll_wbarb_io_out_bits_uop_stq_idx; // @[core.scala:132:32]
wire [1:0] _ll_wbarb_io_out_bits_uop_rxq_idx; // @[core.scala:132:32]
wire [6:0] _ll_wbarb_io_out_bits_uop_pdst; // @[core.scala:132:32]
wire [6:0] _ll_wbarb_io_out_bits_uop_prs1; // @[core.scala:132:32]
wire [6:0] _ll_wbarb_io_out_bits_uop_prs2; // @[core.scala:132:32]
wire [6:0] _ll_wbarb_io_out_bits_uop_prs3; // @[core.scala:132:32]
wire [4:0] _ll_wbarb_io_out_bits_uop_ppred; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_uop_prs1_busy; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_uop_prs2_busy; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_uop_prs3_busy; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_uop_ppred_busy; // @[core.scala:132:32]
wire [6:0] _ll_wbarb_io_out_bits_uop_stale_pdst; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_uop_exception; // @[core.scala:132:32]
wire [63:0] _ll_wbarb_io_out_bits_uop_exc_cause; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_uop_bypassable; // @[core.scala:132:32]
wire [4:0] _ll_wbarb_io_out_bits_uop_mem_cmd; // @[core.scala:132:32]
wire [1:0] _ll_wbarb_io_out_bits_uop_mem_size; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_uop_mem_signed; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_uop_is_fence; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_uop_is_fencei; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_uop_is_amo; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_uop_uses_ldq; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_uop_uses_stq; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_uop_is_sys_pc2epc; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_uop_is_unique; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_uop_flush_on_commit; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_uop_ldst_is_rs1; // @[core.scala:132:32]
wire [5:0] _ll_wbarb_io_out_bits_uop_ldst; // @[core.scala:132:32]
wire [5:0] _ll_wbarb_io_out_bits_uop_lrs1; // @[core.scala:132:32]
wire [5:0] _ll_wbarb_io_out_bits_uop_lrs2; // @[core.scala:132:32]
wire [5:0] _ll_wbarb_io_out_bits_uop_lrs3; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_uop_ldst_val; // @[core.scala:132:32]
wire [1:0] _ll_wbarb_io_out_bits_uop_dst_rtype; // @[core.scala:132:32]
wire [1:0] _ll_wbarb_io_out_bits_uop_lrs1_rtype; // @[core.scala:132:32]
wire [1:0] _ll_wbarb_io_out_bits_uop_lrs2_rtype; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_uop_frs3_en; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_uop_fp_val; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_uop_fp_single; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_uop_xcpt_pf_if; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_uop_xcpt_ae_if; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_uop_xcpt_ma_if; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_uop_bp_debug_if; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_uop_bp_xcpt_if; // @[core.scala:132:32]
wire [1:0] _ll_wbarb_io_out_bits_uop_debug_fsrc; // @[core.scala:132:32]
wire [1:0] _ll_wbarb_io_out_bits_uop_debug_tsrc; // @[core.scala:132:32]
wire [63:0] _ll_wbarb_io_out_bits_data; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_predicated; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_fflags_valid; // @[core.scala:132:32]
wire [6:0] _ll_wbarb_io_out_bits_fflags_bits_uop_uopc; // @[core.scala:132:32]
wire [31:0] _ll_wbarb_io_out_bits_fflags_bits_uop_inst; // @[core.scala:132:32]
wire [31:0] _ll_wbarb_io_out_bits_fflags_bits_uop_debug_inst; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_fflags_bits_uop_is_rvc; // @[core.scala:132:32]
wire [39:0] _ll_wbarb_io_out_bits_fflags_bits_uop_debug_pc; // @[core.scala:132:32]
wire [2:0] _ll_wbarb_io_out_bits_fflags_bits_uop_iq_type; // @[core.scala:132:32]
wire [9:0] _ll_wbarb_io_out_bits_fflags_bits_uop_fu_code; // @[core.scala:132:32]
wire [3:0] _ll_wbarb_io_out_bits_fflags_bits_uop_ctrl_br_type; // @[core.scala:132:32]
wire [1:0] _ll_wbarb_io_out_bits_fflags_bits_uop_ctrl_op1_sel; // @[core.scala:132:32]
wire [2:0] _ll_wbarb_io_out_bits_fflags_bits_uop_ctrl_op2_sel; // @[core.scala:132:32]
wire [2:0] _ll_wbarb_io_out_bits_fflags_bits_uop_ctrl_imm_sel; // @[core.scala:132:32]
wire [4:0] _ll_wbarb_io_out_bits_fflags_bits_uop_ctrl_op_fcn; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_fflags_bits_uop_ctrl_fcn_dw; // @[core.scala:132:32]
wire [2:0] _ll_wbarb_io_out_bits_fflags_bits_uop_ctrl_csr_cmd; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_fflags_bits_uop_ctrl_is_load; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_fflags_bits_uop_ctrl_is_sta; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_fflags_bits_uop_ctrl_is_std; // @[core.scala:132:32]
wire [1:0] _ll_wbarb_io_out_bits_fflags_bits_uop_iw_state; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_fflags_bits_uop_iw_p1_poisoned; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_fflags_bits_uop_iw_p2_poisoned; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_fflags_bits_uop_is_br; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_fflags_bits_uop_is_jalr; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_fflags_bits_uop_is_jal; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_fflags_bits_uop_is_sfb; // @[core.scala:132:32]
wire [15:0] _ll_wbarb_io_out_bits_fflags_bits_uop_br_mask; // @[core.scala:132:32]
wire [3:0] _ll_wbarb_io_out_bits_fflags_bits_uop_br_tag; // @[core.scala:132:32]
wire [4:0] _ll_wbarb_io_out_bits_fflags_bits_uop_ftq_idx; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_fflags_bits_uop_edge_inst; // @[core.scala:132:32]
wire [5:0] _ll_wbarb_io_out_bits_fflags_bits_uop_pc_lob; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_fflags_bits_uop_taken; // @[core.scala:132:32]
wire [19:0] _ll_wbarb_io_out_bits_fflags_bits_uop_imm_packed; // @[core.scala:132:32]
wire [11:0] _ll_wbarb_io_out_bits_fflags_bits_uop_csr_addr; // @[core.scala:132:32]
wire [6:0] _ll_wbarb_io_out_bits_fflags_bits_uop_rob_idx; // @[core.scala:132:32]
wire [4:0] _ll_wbarb_io_out_bits_fflags_bits_uop_ldq_idx; // @[core.scala:132:32]
wire [4:0] _ll_wbarb_io_out_bits_fflags_bits_uop_stq_idx; // @[core.scala:132:32]
wire [1:0] _ll_wbarb_io_out_bits_fflags_bits_uop_rxq_idx; // @[core.scala:132:32]
wire [6:0] _ll_wbarb_io_out_bits_fflags_bits_uop_pdst; // @[core.scala:132:32]
wire [6:0] _ll_wbarb_io_out_bits_fflags_bits_uop_prs1; // @[core.scala:132:32]
wire [6:0] _ll_wbarb_io_out_bits_fflags_bits_uop_prs2; // @[core.scala:132:32]
wire [6:0] _ll_wbarb_io_out_bits_fflags_bits_uop_prs3; // @[core.scala:132:32]
wire [4:0] _ll_wbarb_io_out_bits_fflags_bits_uop_ppred; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_fflags_bits_uop_prs1_busy; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_fflags_bits_uop_prs2_busy; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_fflags_bits_uop_prs3_busy; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_fflags_bits_uop_ppred_busy; // @[core.scala:132:32]
wire [6:0] _ll_wbarb_io_out_bits_fflags_bits_uop_stale_pdst; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_fflags_bits_uop_exception; // @[core.scala:132:32]
wire [63:0] _ll_wbarb_io_out_bits_fflags_bits_uop_exc_cause; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_fflags_bits_uop_bypassable; // @[core.scala:132:32]
wire [4:0] _ll_wbarb_io_out_bits_fflags_bits_uop_mem_cmd; // @[core.scala:132:32]
wire [1:0] _ll_wbarb_io_out_bits_fflags_bits_uop_mem_size; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_fflags_bits_uop_mem_signed; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_fflags_bits_uop_is_fence; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_fflags_bits_uop_is_fencei; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_fflags_bits_uop_is_amo; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_fflags_bits_uop_uses_ldq; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_fflags_bits_uop_uses_stq; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_fflags_bits_uop_is_sys_pc2epc; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_fflags_bits_uop_is_unique; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_fflags_bits_uop_flush_on_commit; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_fflags_bits_uop_ldst_is_rs1; // @[core.scala:132:32]
wire [5:0] _ll_wbarb_io_out_bits_fflags_bits_uop_ldst; // @[core.scala:132:32]
wire [5:0] _ll_wbarb_io_out_bits_fflags_bits_uop_lrs1; // @[core.scala:132:32]
wire [5:0] _ll_wbarb_io_out_bits_fflags_bits_uop_lrs2; // @[core.scala:132:32]
wire [5:0] _ll_wbarb_io_out_bits_fflags_bits_uop_lrs3; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_fflags_bits_uop_ldst_val; // @[core.scala:132:32]
wire [1:0] _ll_wbarb_io_out_bits_fflags_bits_uop_dst_rtype; // @[core.scala:132:32]
wire [1:0] _ll_wbarb_io_out_bits_fflags_bits_uop_lrs1_rtype; // @[core.scala:132:32]
wire [1:0] _ll_wbarb_io_out_bits_fflags_bits_uop_lrs2_rtype; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_fflags_bits_uop_frs3_en; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_fflags_bits_uop_fp_val; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_fflags_bits_uop_fp_single; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_fflags_bits_uop_xcpt_pf_if; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_fflags_bits_uop_xcpt_ae_if; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_fflags_bits_uop_xcpt_ma_if; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_fflags_bits_uop_bp_debug_if; // @[core.scala:132:32]
wire _ll_wbarb_io_out_bits_fflags_bits_uop_bp_xcpt_if; // @[core.scala:132:32]
wire [1:0] _ll_wbarb_io_out_bits_fflags_bits_uop_debug_fsrc; // @[core.scala:132:32]
wire [1:0] _ll_wbarb_io_out_bits_fflags_bits_uop_debug_tsrc; // @[core.scala:132:32]
wire [4:0] _ll_wbarb_io_out_bits_fflags_bits_flags; // @[core.scala:132:32]
wire [63:0] _iregfile_io_read_ports_0_data; // @[core.scala:116:32]
wire [63:0] _iregfile_io_read_ports_1_data; // @[core.scala:116:32]
wire [63:0] _iregfile_io_read_ports_2_data; // @[core.scala:116:32]
wire [63:0] _iregfile_io_read_ports_3_data; // @[core.scala:116:32]
wire [63:0] _iregfile_io_read_ports_4_data; // @[core.scala:116:32]
wire [63:0] _iregfile_io_read_ports_5_data; // @[core.scala:116:32]
wire [63:0] _iregfile_io_read_ports_6_data; // @[core.scala:116:32]
wire [63:0] _iregfile_io_read_ports_7_data; // @[core.scala:116:32]
wire _dispatcher_io_ren_uops_0_ready; // @[core.scala:114:32]
wire _dispatcher_io_ren_uops_1_ready; // @[core.scala:114:32]
wire _dispatcher_io_ren_uops_2_ready; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_0_valid; // @[core.scala:114:32]
wire [6:0] _dispatcher_io_dis_uops_2_0_bits_uopc; // @[core.scala:114:32]
wire [31:0] _dispatcher_io_dis_uops_2_0_bits_inst; // @[core.scala:114:32]
wire [31:0] _dispatcher_io_dis_uops_2_0_bits_debug_inst; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_0_bits_is_rvc; // @[core.scala:114:32]
wire [39:0] _dispatcher_io_dis_uops_2_0_bits_debug_pc; // @[core.scala:114:32]
wire [2:0] _dispatcher_io_dis_uops_2_0_bits_iq_type; // @[core.scala:114:32]
wire [9:0] _dispatcher_io_dis_uops_2_0_bits_fu_code; // @[core.scala:114:32]
wire [3:0] _dispatcher_io_dis_uops_2_0_bits_ctrl_br_type; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_2_0_bits_ctrl_op1_sel; // @[core.scala:114:32]
wire [2:0] _dispatcher_io_dis_uops_2_0_bits_ctrl_op2_sel; // @[core.scala:114:32]
wire [2:0] _dispatcher_io_dis_uops_2_0_bits_ctrl_imm_sel; // @[core.scala:114:32]
wire [4:0] _dispatcher_io_dis_uops_2_0_bits_ctrl_op_fcn; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_0_bits_ctrl_fcn_dw; // @[core.scala:114:32]
wire [2:0] _dispatcher_io_dis_uops_2_0_bits_ctrl_csr_cmd; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_0_bits_ctrl_is_load; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_0_bits_ctrl_is_sta; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_0_bits_ctrl_is_std; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_2_0_bits_iw_state; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_0_bits_iw_p1_poisoned; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_0_bits_iw_p2_poisoned; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_0_bits_is_br; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_0_bits_is_jalr; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_0_bits_is_jal; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_0_bits_is_sfb; // @[core.scala:114:32]
wire [15:0] _dispatcher_io_dis_uops_2_0_bits_br_mask; // @[core.scala:114:32]
wire [3:0] _dispatcher_io_dis_uops_2_0_bits_br_tag; // @[core.scala:114:32]
wire [4:0] _dispatcher_io_dis_uops_2_0_bits_ftq_idx; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_0_bits_edge_inst; // @[core.scala:114:32]
wire [5:0] _dispatcher_io_dis_uops_2_0_bits_pc_lob; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_0_bits_taken; // @[core.scala:114:32]
wire [19:0] _dispatcher_io_dis_uops_2_0_bits_imm_packed; // @[core.scala:114:32]
wire [11:0] _dispatcher_io_dis_uops_2_0_bits_csr_addr; // @[core.scala:114:32]
wire [6:0] _dispatcher_io_dis_uops_2_0_bits_rob_idx; // @[core.scala:114:32]
wire [4:0] _dispatcher_io_dis_uops_2_0_bits_ldq_idx; // @[core.scala:114:32]
wire [4:0] _dispatcher_io_dis_uops_2_0_bits_stq_idx; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_2_0_bits_rxq_idx; // @[core.scala:114:32]
wire [6:0] _dispatcher_io_dis_uops_2_0_bits_pdst; // @[core.scala:114:32]
wire [6:0] _dispatcher_io_dis_uops_2_0_bits_prs1; // @[core.scala:114:32]
wire [6:0] _dispatcher_io_dis_uops_2_0_bits_prs2; // @[core.scala:114:32]
wire [6:0] _dispatcher_io_dis_uops_2_0_bits_prs3; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_0_bits_prs1_busy; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_0_bits_prs2_busy; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_0_bits_prs3_busy; // @[core.scala:114:32]
wire [6:0] _dispatcher_io_dis_uops_2_0_bits_stale_pdst; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_0_bits_exception; // @[core.scala:114:32]
wire [63:0] _dispatcher_io_dis_uops_2_0_bits_exc_cause; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_0_bits_bypassable; // @[core.scala:114:32]
wire [4:0] _dispatcher_io_dis_uops_2_0_bits_mem_cmd; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_2_0_bits_mem_size; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_0_bits_mem_signed; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_0_bits_is_fence; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_0_bits_is_fencei; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_0_bits_is_amo; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_0_bits_uses_ldq; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_0_bits_uses_stq; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_0_bits_is_sys_pc2epc; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_0_bits_is_unique; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_0_bits_flush_on_commit; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_0_bits_ldst_is_rs1; // @[core.scala:114:32]
wire [5:0] _dispatcher_io_dis_uops_2_0_bits_ldst; // @[core.scala:114:32]
wire [5:0] _dispatcher_io_dis_uops_2_0_bits_lrs1; // @[core.scala:114:32]
wire [5:0] _dispatcher_io_dis_uops_2_0_bits_lrs2; // @[core.scala:114:32]
wire [5:0] _dispatcher_io_dis_uops_2_0_bits_lrs3; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_0_bits_ldst_val; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_2_0_bits_dst_rtype; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_2_0_bits_lrs1_rtype; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_2_0_bits_lrs2_rtype; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_0_bits_frs3_en; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_0_bits_fp_val; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_0_bits_fp_single; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_0_bits_xcpt_pf_if; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_0_bits_xcpt_ae_if; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_0_bits_xcpt_ma_if; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_0_bits_bp_debug_if; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_0_bits_bp_xcpt_if; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_2_0_bits_debug_fsrc; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_2_0_bits_debug_tsrc; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_1_valid; // @[core.scala:114:32]
wire [6:0] _dispatcher_io_dis_uops_2_1_bits_uopc; // @[core.scala:114:32]
wire [31:0] _dispatcher_io_dis_uops_2_1_bits_inst; // @[core.scala:114:32]
wire [31:0] _dispatcher_io_dis_uops_2_1_bits_debug_inst; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_1_bits_is_rvc; // @[core.scala:114:32]
wire [39:0] _dispatcher_io_dis_uops_2_1_bits_debug_pc; // @[core.scala:114:32]
wire [2:0] _dispatcher_io_dis_uops_2_1_bits_iq_type; // @[core.scala:114:32]
wire [9:0] _dispatcher_io_dis_uops_2_1_bits_fu_code; // @[core.scala:114:32]
wire [3:0] _dispatcher_io_dis_uops_2_1_bits_ctrl_br_type; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_2_1_bits_ctrl_op1_sel; // @[core.scala:114:32]
wire [2:0] _dispatcher_io_dis_uops_2_1_bits_ctrl_op2_sel; // @[core.scala:114:32]
wire [2:0] _dispatcher_io_dis_uops_2_1_bits_ctrl_imm_sel; // @[core.scala:114:32]
wire [4:0] _dispatcher_io_dis_uops_2_1_bits_ctrl_op_fcn; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_1_bits_ctrl_fcn_dw; // @[core.scala:114:32]
wire [2:0] _dispatcher_io_dis_uops_2_1_bits_ctrl_csr_cmd; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_1_bits_ctrl_is_load; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_1_bits_ctrl_is_sta; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_1_bits_ctrl_is_std; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_2_1_bits_iw_state; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_1_bits_iw_p1_poisoned; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_1_bits_iw_p2_poisoned; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_1_bits_is_br; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_1_bits_is_jalr; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_1_bits_is_jal; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_1_bits_is_sfb; // @[core.scala:114:32]
wire [15:0] _dispatcher_io_dis_uops_2_1_bits_br_mask; // @[core.scala:114:32]
wire [3:0] _dispatcher_io_dis_uops_2_1_bits_br_tag; // @[core.scala:114:32]
wire [4:0] _dispatcher_io_dis_uops_2_1_bits_ftq_idx; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_1_bits_edge_inst; // @[core.scala:114:32]
wire [5:0] _dispatcher_io_dis_uops_2_1_bits_pc_lob; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_1_bits_taken; // @[core.scala:114:32]
wire [19:0] _dispatcher_io_dis_uops_2_1_bits_imm_packed; // @[core.scala:114:32]
wire [11:0] _dispatcher_io_dis_uops_2_1_bits_csr_addr; // @[core.scala:114:32]
wire [6:0] _dispatcher_io_dis_uops_2_1_bits_rob_idx; // @[core.scala:114:32]
wire [4:0] _dispatcher_io_dis_uops_2_1_bits_ldq_idx; // @[core.scala:114:32]
wire [4:0] _dispatcher_io_dis_uops_2_1_bits_stq_idx; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_2_1_bits_rxq_idx; // @[core.scala:114:32]
wire [6:0] _dispatcher_io_dis_uops_2_1_bits_pdst; // @[core.scala:114:32]
wire [6:0] _dispatcher_io_dis_uops_2_1_bits_prs1; // @[core.scala:114:32]
wire [6:0] _dispatcher_io_dis_uops_2_1_bits_prs2; // @[core.scala:114:32]
wire [6:0] _dispatcher_io_dis_uops_2_1_bits_prs3; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_1_bits_prs1_busy; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_1_bits_prs2_busy; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_1_bits_prs3_busy; // @[core.scala:114:32]
wire [6:0] _dispatcher_io_dis_uops_2_1_bits_stale_pdst; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_1_bits_exception; // @[core.scala:114:32]
wire [63:0] _dispatcher_io_dis_uops_2_1_bits_exc_cause; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_1_bits_bypassable; // @[core.scala:114:32]
wire [4:0] _dispatcher_io_dis_uops_2_1_bits_mem_cmd; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_2_1_bits_mem_size; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_1_bits_mem_signed; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_1_bits_is_fence; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_1_bits_is_fencei; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_1_bits_is_amo; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_1_bits_uses_ldq; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_1_bits_uses_stq; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_1_bits_is_sys_pc2epc; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_1_bits_is_unique; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_1_bits_flush_on_commit; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_1_bits_ldst_is_rs1; // @[core.scala:114:32]
wire [5:0] _dispatcher_io_dis_uops_2_1_bits_ldst; // @[core.scala:114:32]
wire [5:0] _dispatcher_io_dis_uops_2_1_bits_lrs1; // @[core.scala:114:32]
wire [5:0] _dispatcher_io_dis_uops_2_1_bits_lrs2; // @[core.scala:114:32]
wire [5:0] _dispatcher_io_dis_uops_2_1_bits_lrs3; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_1_bits_ldst_val; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_2_1_bits_dst_rtype; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_2_1_bits_lrs1_rtype; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_2_1_bits_lrs2_rtype; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_1_bits_frs3_en; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_1_bits_fp_val; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_1_bits_fp_single; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_1_bits_xcpt_pf_if; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_1_bits_xcpt_ae_if; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_1_bits_xcpt_ma_if; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_1_bits_bp_debug_if; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_1_bits_bp_xcpt_if; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_2_1_bits_debug_fsrc; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_2_1_bits_debug_tsrc; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_2_valid; // @[core.scala:114:32]
wire [6:0] _dispatcher_io_dis_uops_2_2_bits_uopc; // @[core.scala:114:32]
wire [31:0] _dispatcher_io_dis_uops_2_2_bits_inst; // @[core.scala:114:32]
wire [31:0] _dispatcher_io_dis_uops_2_2_bits_debug_inst; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_2_bits_is_rvc; // @[core.scala:114:32]
wire [39:0] _dispatcher_io_dis_uops_2_2_bits_debug_pc; // @[core.scala:114:32]
wire [2:0] _dispatcher_io_dis_uops_2_2_bits_iq_type; // @[core.scala:114:32]
wire [9:0] _dispatcher_io_dis_uops_2_2_bits_fu_code; // @[core.scala:114:32]
wire [3:0] _dispatcher_io_dis_uops_2_2_bits_ctrl_br_type; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_2_2_bits_ctrl_op1_sel; // @[core.scala:114:32]
wire [2:0] _dispatcher_io_dis_uops_2_2_bits_ctrl_op2_sel; // @[core.scala:114:32]
wire [2:0] _dispatcher_io_dis_uops_2_2_bits_ctrl_imm_sel; // @[core.scala:114:32]
wire [4:0] _dispatcher_io_dis_uops_2_2_bits_ctrl_op_fcn; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_2_bits_ctrl_fcn_dw; // @[core.scala:114:32]
wire [2:0] _dispatcher_io_dis_uops_2_2_bits_ctrl_csr_cmd; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_2_bits_ctrl_is_load; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_2_bits_ctrl_is_sta; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_2_bits_ctrl_is_std; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_2_2_bits_iw_state; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_2_bits_iw_p1_poisoned; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_2_bits_iw_p2_poisoned; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_2_bits_is_br; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_2_bits_is_jalr; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_2_bits_is_jal; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_2_bits_is_sfb; // @[core.scala:114:32]
wire [15:0] _dispatcher_io_dis_uops_2_2_bits_br_mask; // @[core.scala:114:32]
wire [3:0] _dispatcher_io_dis_uops_2_2_bits_br_tag; // @[core.scala:114:32]
wire [4:0] _dispatcher_io_dis_uops_2_2_bits_ftq_idx; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_2_bits_edge_inst; // @[core.scala:114:32]
wire [5:0] _dispatcher_io_dis_uops_2_2_bits_pc_lob; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_2_bits_taken; // @[core.scala:114:32]
wire [19:0] _dispatcher_io_dis_uops_2_2_bits_imm_packed; // @[core.scala:114:32]
wire [11:0] _dispatcher_io_dis_uops_2_2_bits_csr_addr; // @[core.scala:114:32]
wire [6:0] _dispatcher_io_dis_uops_2_2_bits_rob_idx; // @[core.scala:114:32]
wire [4:0] _dispatcher_io_dis_uops_2_2_bits_ldq_idx; // @[core.scala:114:32]
wire [4:0] _dispatcher_io_dis_uops_2_2_bits_stq_idx; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_2_2_bits_rxq_idx; // @[core.scala:114:32]
wire [6:0] _dispatcher_io_dis_uops_2_2_bits_pdst; // @[core.scala:114:32]
wire [6:0] _dispatcher_io_dis_uops_2_2_bits_prs1; // @[core.scala:114:32]
wire [6:0] _dispatcher_io_dis_uops_2_2_bits_prs2; // @[core.scala:114:32]
wire [6:0] _dispatcher_io_dis_uops_2_2_bits_prs3; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_2_bits_prs1_busy; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_2_bits_prs2_busy; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_2_bits_prs3_busy; // @[core.scala:114:32]
wire [6:0] _dispatcher_io_dis_uops_2_2_bits_stale_pdst; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_2_bits_exception; // @[core.scala:114:32]
wire [63:0] _dispatcher_io_dis_uops_2_2_bits_exc_cause; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_2_bits_bypassable; // @[core.scala:114:32]
wire [4:0] _dispatcher_io_dis_uops_2_2_bits_mem_cmd; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_2_2_bits_mem_size; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_2_bits_mem_signed; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_2_bits_is_fence; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_2_bits_is_fencei; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_2_bits_is_amo; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_2_bits_uses_ldq; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_2_bits_uses_stq; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_2_bits_is_sys_pc2epc; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_2_bits_is_unique; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_2_bits_flush_on_commit; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_2_bits_ldst_is_rs1; // @[core.scala:114:32]
wire [5:0] _dispatcher_io_dis_uops_2_2_bits_ldst; // @[core.scala:114:32]
wire [5:0] _dispatcher_io_dis_uops_2_2_bits_lrs1; // @[core.scala:114:32]
wire [5:0] _dispatcher_io_dis_uops_2_2_bits_lrs2; // @[core.scala:114:32]
wire [5:0] _dispatcher_io_dis_uops_2_2_bits_lrs3; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_2_bits_ldst_val; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_2_2_bits_dst_rtype; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_2_2_bits_lrs1_rtype; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_2_2_bits_lrs2_rtype; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_2_bits_frs3_en; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_2_bits_fp_val; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_2_bits_fp_single; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_2_bits_xcpt_pf_if; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_2_bits_xcpt_ae_if; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_2_bits_xcpt_ma_if; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_2_bits_bp_debug_if; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_2_2_bits_bp_xcpt_if; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_2_2_bits_debug_fsrc; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_2_2_bits_debug_tsrc; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_0_valid; // @[core.scala:114:32]
wire [6:0] _dispatcher_io_dis_uops_1_0_bits_uopc; // @[core.scala:114:32]
wire [31:0] _dispatcher_io_dis_uops_1_0_bits_inst; // @[core.scala:114:32]
wire [31:0] _dispatcher_io_dis_uops_1_0_bits_debug_inst; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_0_bits_is_rvc; // @[core.scala:114:32]
wire [39:0] _dispatcher_io_dis_uops_1_0_bits_debug_pc; // @[core.scala:114:32]
wire [2:0] _dispatcher_io_dis_uops_1_0_bits_iq_type; // @[core.scala:114:32]
wire [9:0] _dispatcher_io_dis_uops_1_0_bits_fu_code; // @[core.scala:114:32]
wire [3:0] _dispatcher_io_dis_uops_1_0_bits_ctrl_br_type; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_1_0_bits_ctrl_op1_sel; // @[core.scala:114:32]
wire [2:0] _dispatcher_io_dis_uops_1_0_bits_ctrl_op2_sel; // @[core.scala:114:32]
wire [2:0] _dispatcher_io_dis_uops_1_0_bits_ctrl_imm_sel; // @[core.scala:114:32]
wire [4:0] _dispatcher_io_dis_uops_1_0_bits_ctrl_op_fcn; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_0_bits_ctrl_fcn_dw; // @[core.scala:114:32]
wire [2:0] _dispatcher_io_dis_uops_1_0_bits_ctrl_csr_cmd; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_0_bits_ctrl_is_load; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_0_bits_ctrl_is_sta; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_0_bits_ctrl_is_std; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_1_0_bits_iw_state; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_0_bits_iw_p1_poisoned; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_0_bits_iw_p2_poisoned; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_0_bits_is_br; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_0_bits_is_jalr; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_0_bits_is_jal; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_0_bits_is_sfb; // @[core.scala:114:32]
wire [15:0] _dispatcher_io_dis_uops_1_0_bits_br_mask; // @[core.scala:114:32]
wire [3:0] _dispatcher_io_dis_uops_1_0_bits_br_tag; // @[core.scala:114:32]
wire [4:0] _dispatcher_io_dis_uops_1_0_bits_ftq_idx; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_0_bits_edge_inst; // @[core.scala:114:32]
wire [5:0] _dispatcher_io_dis_uops_1_0_bits_pc_lob; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_0_bits_taken; // @[core.scala:114:32]
wire [19:0] _dispatcher_io_dis_uops_1_0_bits_imm_packed; // @[core.scala:114:32]
wire [11:0] _dispatcher_io_dis_uops_1_0_bits_csr_addr; // @[core.scala:114:32]
wire [6:0] _dispatcher_io_dis_uops_1_0_bits_rob_idx; // @[core.scala:114:32]
wire [4:0] _dispatcher_io_dis_uops_1_0_bits_ldq_idx; // @[core.scala:114:32]
wire [4:0] _dispatcher_io_dis_uops_1_0_bits_stq_idx; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_1_0_bits_rxq_idx; // @[core.scala:114:32]
wire [6:0] _dispatcher_io_dis_uops_1_0_bits_pdst; // @[core.scala:114:32]
wire [6:0] _dispatcher_io_dis_uops_1_0_bits_prs1; // @[core.scala:114:32]
wire [6:0] _dispatcher_io_dis_uops_1_0_bits_prs2; // @[core.scala:114:32]
wire [6:0] _dispatcher_io_dis_uops_1_0_bits_prs3; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_0_bits_prs1_busy; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_0_bits_prs2_busy; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_0_bits_prs3_busy; // @[core.scala:114:32]
wire [6:0] _dispatcher_io_dis_uops_1_0_bits_stale_pdst; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_0_bits_exception; // @[core.scala:114:32]
wire [63:0] _dispatcher_io_dis_uops_1_0_bits_exc_cause; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_0_bits_bypassable; // @[core.scala:114:32]
wire [4:0] _dispatcher_io_dis_uops_1_0_bits_mem_cmd; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_1_0_bits_mem_size; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_0_bits_mem_signed; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_0_bits_is_fence; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_0_bits_is_fencei; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_0_bits_is_amo; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_0_bits_uses_ldq; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_0_bits_uses_stq; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_0_bits_is_sys_pc2epc; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_0_bits_is_unique; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_0_bits_flush_on_commit; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_0_bits_ldst_is_rs1; // @[core.scala:114:32]
wire [5:0] _dispatcher_io_dis_uops_1_0_bits_ldst; // @[core.scala:114:32]
wire [5:0] _dispatcher_io_dis_uops_1_0_bits_lrs1; // @[core.scala:114:32]
wire [5:0] _dispatcher_io_dis_uops_1_0_bits_lrs2; // @[core.scala:114:32]
wire [5:0] _dispatcher_io_dis_uops_1_0_bits_lrs3; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_0_bits_ldst_val; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_1_0_bits_dst_rtype; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_1_0_bits_lrs1_rtype; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_1_0_bits_lrs2_rtype; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_0_bits_frs3_en; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_0_bits_fp_val; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_0_bits_fp_single; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_0_bits_xcpt_pf_if; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_0_bits_xcpt_ae_if; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_0_bits_xcpt_ma_if; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_0_bits_bp_debug_if; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_0_bits_bp_xcpt_if; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_1_0_bits_debug_fsrc; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_1_0_bits_debug_tsrc; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_1_valid; // @[core.scala:114:32]
wire [6:0] _dispatcher_io_dis_uops_1_1_bits_uopc; // @[core.scala:114:32]
wire [31:0] _dispatcher_io_dis_uops_1_1_bits_inst; // @[core.scala:114:32]
wire [31:0] _dispatcher_io_dis_uops_1_1_bits_debug_inst; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_1_bits_is_rvc; // @[core.scala:114:32]
wire [39:0] _dispatcher_io_dis_uops_1_1_bits_debug_pc; // @[core.scala:114:32]
wire [2:0] _dispatcher_io_dis_uops_1_1_bits_iq_type; // @[core.scala:114:32]
wire [9:0] _dispatcher_io_dis_uops_1_1_bits_fu_code; // @[core.scala:114:32]
wire [3:0] _dispatcher_io_dis_uops_1_1_bits_ctrl_br_type; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_1_1_bits_ctrl_op1_sel; // @[core.scala:114:32]
wire [2:0] _dispatcher_io_dis_uops_1_1_bits_ctrl_op2_sel; // @[core.scala:114:32]
wire [2:0] _dispatcher_io_dis_uops_1_1_bits_ctrl_imm_sel; // @[core.scala:114:32]
wire [4:0] _dispatcher_io_dis_uops_1_1_bits_ctrl_op_fcn; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_1_bits_ctrl_fcn_dw; // @[core.scala:114:32]
wire [2:0] _dispatcher_io_dis_uops_1_1_bits_ctrl_csr_cmd; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_1_bits_ctrl_is_load; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_1_bits_ctrl_is_sta; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_1_bits_ctrl_is_std; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_1_1_bits_iw_state; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_1_bits_iw_p1_poisoned; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_1_bits_iw_p2_poisoned; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_1_bits_is_br; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_1_bits_is_jalr; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_1_bits_is_jal; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_1_bits_is_sfb; // @[core.scala:114:32]
wire [15:0] _dispatcher_io_dis_uops_1_1_bits_br_mask; // @[core.scala:114:32]
wire [3:0] _dispatcher_io_dis_uops_1_1_bits_br_tag; // @[core.scala:114:32]
wire [4:0] _dispatcher_io_dis_uops_1_1_bits_ftq_idx; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_1_bits_edge_inst; // @[core.scala:114:32]
wire [5:0] _dispatcher_io_dis_uops_1_1_bits_pc_lob; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_1_bits_taken; // @[core.scala:114:32]
wire [19:0] _dispatcher_io_dis_uops_1_1_bits_imm_packed; // @[core.scala:114:32]
wire [11:0] _dispatcher_io_dis_uops_1_1_bits_csr_addr; // @[core.scala:114:32]
wire [6:0] _dispatcher_io_dis_uops_1_1_bits_rob_idx; // @[core.scala:114:32]
wire [4:0] _dispatcher_io_dis_uops_1_1_bits_ldq_idx; // @[core.scala:114:32]
wire [4:0] _dispatcher_io_dis_uops_1_1_bits_stq_idx; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_1_1_bits_rxq_idx; // @[core.scala:114:32]
wire [6:0] _dispatcher_io_dis_uops_1_1_bits_pdst; // @[core.scala:114:32]
wire [6:0] _dispatcher_io_dis_uops_1_1_bits_prs1; // @[core.scala:114:32]
wire [6:0] _dispatcher_io_dis_uops_1_1_bits_prs2; // @[core.scala:114:32]
wire [6:0] _dispatcher_io_dis_uops_1_1_bits_prs3; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_1_bits_prs1_busy; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_1_bits_prs2_busy; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_1_bits_prs3_busy; // @[core.scala:114:32]
wire [6:0] _dispatcher_io_dis_uops_1_1_bits_stale_pdst; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_1_bits_exception; // @[core.scala:114:32]
wire [63:0] _dispatcher_io_dis_uops_1_1_bits_exc_cause; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_1_bits_bypassable; // @[core.scala:114:32]
wire [4:0] _dispatcher_io_dis_uops_1_1_bits_mem_cmd; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_1_1_bits_mem_size; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_1_bits_mem_signed; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_1_bits_is_fence; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_1_bits_is_fencei; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_1_bits_is_amo; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_1_bits_uses_ldq; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_1_bits_uses_stq; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_1_bits_is_sys_pc2epc; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_1_bits_is_unique; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_1_bits_flush_on_commit; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_1_bits_ldst_is_rs1; // @[core.scala:114:32]
wire [5:0] _dispatcher_io_dis_uops_1_1_bits_ldst; // @[core.scala:114:32]
wire [5:0] _dispatcher_io_dis_uops_1_1_bits_lrs1; // @[core.scala:114:32]
wire [5:0] _dispatcher_io_dis_uops_1_1_bits_lrs2; // @[core.scala:114:32]
wire [5:0] _dispatcher_io_dis_uops_1_1_bits_lrs3; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_1_bits_ldst_val; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_1_1_bits_dst_rtype; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_1_1_bits_lrs1_rtype; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_1_1_bits_lrs2_rtype; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_1_bits_frs3_en; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_1_bits_fp_val; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_1_bits_fp_single; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_1_bits_xcpt_pf_if; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_1_bits_xcpt_ae_if; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_1_bits_xcpt_ma_if; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_1_bits_bp_debug_if; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_1_bits_bp_xcpt_if; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_1_1_bits_debug_fsrc; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_1_1_bits_debug_tsrc; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_2_valid; // @[core.scala:114:32]
wire [6:0] _dispatcher_io_dis_uops_1_2_bits_uopc; // @[core.scala:114:32]
wire [31:0] _dispatcher_io_dis_uops_1_2_bits_inst; // @[core.scala:114:32]
wire [31:0] _dispatcher_io_dis_uops_1_2_bits_debug_inst; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_2_bits_is_rvc; // @[core.scala:114:32]
wire [39:0] _dispatcher_io_dis_uops_1_2_bits_debug_pc; // @[core.scala:114:32]
wire [2:0] _dispatcher_io_dis_uops_1_2_bits_iq_type; // @[core.scala:114:32]
wire [9:0] _dispatcher_io_dis_uops_1_2_bits_fu_code; // @[core.scala:114:32]
wire [3:0] _dispatcher_io_dis_uops_1_2_bits_ctrl_br_type; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_1_2_bits_ctrl_op1_sel; // @[core.scala:114:32]
wire [2:0] _dispatcher_io_dis_uops_1_2_bits_ctrl_op2_sel; // @[core.scala:114:32]
wire [2:0] _dispatcher_io_dis_uops_1_2_bits_ctrl_imm_sel; // @[core.scala:114:32]
wire [4:0] _dispatcher_io_dis_uops_1_2_bits_ctrl_op_fcn; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_2_bits_ctrl_fcn_dw; // @[core.scala:114:32]
wire [2:0] _dispatcher_io_dis_uops_1_2_bits_ctrl_csr_cmd; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_2_bits_ctrl_is_load; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_2_bits_ctrl_is_sta; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_2_bits_ctrl_is_std; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_1_2_bits_iw_state; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_2_bits_iw_p1_poisoned; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_2_bits_iw_p2_poisoned; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_2_bits_is_br; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_2_bits_is_jalr; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_2_bits_is_jal; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_2_bits_is_sfb; // @[core.scala:114:32]
wire [15:0] _dispatcher_io_dis_uops_1_2_bits_br_mask; // @[core.scala:114:32]
wire [3:0] _dispatcher_io_dis_uops_1_2_bits_br_tag; // @[core.scala:114:32]
wire [4:0] _dispatcher_io_dis_uops_1_2_bits_ftq_idx; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_2_bits_edge_inst; // @[core.scala:114:32]
wire [5:0] _dispatcher_io_dis_uops_1_2_bits_pc_lob; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_2_bits_taken; // @[core.scala:114:32]
wire [19:0] _dispatcher_io_dis_uops_1_2_bits_imm_packed; // @[core.scala:114:32]
wire [11:0] _dispatcher_io_dis_uops_1_2_bits_csr_addr; // @[core.scala:114:32]
wire [6:0] _dispatcher_io_dis_uops_1_2_bits_rob_idx; // @[core.scala:114:32]
wire [4:0] _dispatcher_io_dis_uops_1_2_bits_ldq_idx; // @[core.scala:114:32]
wire [4:0] _dispatcher_io_dis_uops_1_2_bits_stq_idx; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_1_2_bits_rxq_idx; // @[core.scala:114:32]
wire [6:0] _dispatcher_io_dis_uops_1_2_bits_pdst; // @[core.scala:114:32]
wire [6:0] _dispatcher_io_dis_uops_1_2_bits_prs1; // @[core.scala:114:32]
wire [6:0] _dispatcher_io_dis_uops_1_2_bits_prs2; // @[core.scala:114:32]
wire [6:0] _dispatcher_io_dis_uops_1_2_bits_prs3; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_2_bits_prs1_busy; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_2_bits_prs2_busy; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_2_bits_prs3_busy; // @[core.scala:114:32]
wire [6:0] _dispatcher_io_dis_uops_1_2_bits_stale_pdst; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_2_bits_exception; // @[core.scala:114:32]
wire [63:0] _dispatcher_io_dis_uops_1_2_bits_exc_cause; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_2_bits_bypassable; // @[core.scala:114:32]
wire [4:0] _dispatcher_io_dis_uops_1_2_bits_mem_cmd; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_1_2_bits_mem_size; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_2_bits_mem_signed; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_2_bits_is_fence; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_2_bits_is_fencei; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_2_bits_is_amo; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_2_bits_uses_ldq; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_2_bits_uses_stq; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_2_bits_is_sys_pc2epc; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_2_bits_is_unique; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_2_bits_flush_on_commit; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_2_bits_ldst_is_rs1; // @[core.scala:114:32]
wire [5:0] _dispatcher_io_dis_uops_1_2_bits_ldst; // @[core.scala:114:32]
wire [5:0] _dispatcher_io_dis_uops_1_2_bits_lrs1; // @[core.scala:114:32]
wire [5:0] _dispatcher_io_dis_uops_1_2_bits_lrs2; // @[core.scala:114:32]
wire [5:0] _dispatcher_io_dis_uops_1_2_bits_lrs3; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_2_bits_ldst_val; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_1_2_bits_dst_rtype; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_1_2_bits_lrs1_rtype; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_1_2_bits_lrs2_rtype; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_2_bits_frs3_en; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_2_bits_fp_val; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_2_bits_fp_single; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_2_bits_xcpt_pf_if; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_2_bits_xcpt_ae_if; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_2_bits_xcpt_ma_if; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_2_bits_bp_debug_if; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_1_2_bits_bp_xcpt_if; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_1_2_bits_debug_fsrc; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_1_2_bits_debug_tsrc; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_0_valid; // @[core.scala:114:32]
wire [6:0] _dispatcher_io_dis_uops_0_0_bits_uopc; // @[core.scala:114:32]
wire [31:0] _dispatcher_io_dis_uops_0_0_bits_inst; // @[core.scala:114:32]
wire [31:0] _dispatcher_io_dis_uops_0_0_bits_debug_inst; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_0_bits_is_rvc; // @[core.scala:114:32]
wire [39:0] _dispatcher_io_dis_uops_0_0_bits_debug_pc; // @[core.scala:114:32]
wire [2:0] _dispatcher_io_dis_uops_0_0_bits_iq_type; // @[core.scala:114:32]
wire [9:0] _dispatcher_io_dis_uops_0_0_bits_fu_code; // @[core.scala:114:32]
wire [3:0] _dispatcher_io_dis_uops_0_0_bits_ctrl_br_type; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_0_0_bits_ctrl_op1_sel; // @[core.scala:114:32]
wire [2:0] _dispatcher_io_dis_uops_0_0_bits_ctrl_op2_sel; // @[core.scala:114:32]
wire [2:0] _dispatcher_io_dis_uops_0_0_bits_ctrl_imm_sel; // @[core.scala:114:32]
wire [4:0] _dispatcher_io_dis_uops_0_0_bits_ctrl_op_fcn; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_0_bits_ctrl_fcn_dw; // @[core.scala:114:32]
wire [2:0] _dispatcher_io_dis_uops_0_0_bits_ctrl_csr_cmd; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_0_bits_ctrl_is_load; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_0_bits_ctrl_is_sta; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_0_bits_ctrl_is_std; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_0_0_bits_iw_state; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_0_bits_iw_p1_poisoned; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_0_bits_iw_p2_poisoned; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_0_bits_is_br; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_0_bits_is_jalr; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_0_bits_is_jal; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_0_bits_is_sfb; // @[core.scala:114:32]
wire [15:0] _dispatcher_io_dis_uops_0_0_bits_br_mask; // @[core.scala:114:32]
wire [3:0] _dispatcher_io_dis_uops_0_0_bits_br_tag; // @[core.scala:114:32]
wire [4:0] _dispatcher_io_dis_uops_0_0_bits_ftq_idx; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_0_bits_edge_inst; // @[core.scala:114:32]
wire [5:0] _dispatcher_io_dis_uops_0_0_bits_pc_lob; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_0_bits_taken; // @[core.scala:114:32]
wire [19:0] _dispatcher_io_dis_uops_0_0_bits_imm_packed; // @[core.scala:114:32]
wire [11:0] _dispatcher_io_dis_uops_0_0_bits_csr_addr; // @[core.scala:114:32]
wire [6:0] _dispatcher_io_dis_uops_0_0_bits_rob_idx; // @[core.scala:114:32]
wire [4:0] _dispatcher_io_dis_uops_0_0_bits_ldq_idx; // @[core.scala:114:32]
wire [4:0] _dispatcher_io_dis_uops_0_0_bits_stq_idx; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_0_0_bits_rxq_idx; // @[core.scala:114:32]
wire [6:0] _dispatcher_io_dis_uops_0_0_bits_pdst; // @[core.scala:114:32]
wire [6:0] _dispatcher_io_dis_uops_0_0_bits_prs1; // @[core.scala:114:32]
wire [6:0] _dispatcher_io_dis_uops_0_0_bits_prs2; // @[core.scala:114:32]
wire [6:0] _dispatcher_io_dis_uops_0_0_bits_prs3; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_0_bits_prs1_busy; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_0_bits_prs2_busy; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_0_bits_prs3_busy; // @[core.scala:114:32]
wire [6:0] _dispatcher_io_dis_uops_0_0_bits_stale_pdst; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_0_bits_exception; // @[core.scala:114:32]
wire [63:0] _dispatcher_io_dis_uops_0_0_bits_exc_cause; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_0_bits_bypassable; // @[core.scala:114:32]
wire [4:0] _dispatcher_io_dis_uops_0_0_bits_mem_cmd; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_0_0_bits_mem_size; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_0_bits_mem_signed; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_0_bits_is_fence; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_0_bits_is_fencei; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_0_bits_is_amo; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_0_bits_uses_ldq; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_0_bits_uses_stq; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_0_bits_is_sys_pc2epc; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_0_bits_is_unique; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_0_bits_flush_on_commit; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_0_bits_ldst_is_rs1; // @[core.scala:114:32]
wire [5:0] _dispatcher_io_dis_uops_0_0_bits_ldst; // @[core.scala:114:32]
wire [5:0] _dispatcher_io_dis_uops_0_0_bits_lrs1; // @[core.scala:114:32]
wire [5:0] _dispatcher_io_dis_uops_0_0_bits_lrs2; // @[core.scala:114:32]
wire [5:0] _dispatcher_io_dis_uops_0_0_bits_lrs3; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_0_bits_ldst_val; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_0_0_bits_dst_rtype; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_0_0_bits_lrs1_rtype; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_0_0_bits_lrs2_rtype; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_0_bits_frs3_en; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_0_bits_fp_val; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_0_bits_fp_single; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_0_bits_xcpt_pf_if; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_0_bits_xcpt_ae_if; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_0_bits_xcpt_ma_if; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_0_bits_bp_debug_if; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_0_bits_bp_xcpt_if; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_0_0_bits_debug_fsrc; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_0_0_bits_debug_tsrc; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_1_valid; // @[core.scala:114:32]
wire [6:0] _dispatcher_io_dis_uops_0_1_bits_uopc; // @[core.scala:114:32]
wire [31:0] _dispatcher_io_dis_uops_0_1_bits_inst; // @[core.scala:114:32]
wire [31:0] _dispatcher_io_dis_uops_0_1_bits_debug_inst; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_1_bits_is_rvc; // @[core.scala:114:32]
wire [39:0] _dispatcher_io_dis_uops_0_1_bits_debug_pc; // @[core.scala:114:32]
wire [2:0] _dispatcher_io_dis_uops_0_1_bits_iq_type; // @[core.scala:114:32]
wire [9:0] _dispatcher_io_dis_uops_0_1_bits_fu_code; // @[core.scala:114:32]
wire [3:0] _dispatcher_io_dis_uops_0_1_bits_ctrl_br_type; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_0_1_bits_ctrl_op1_sel; // @[core.scala:114:32]
wire [2:0] _dispatcher_io_dis_uops_0_1_bits_ctrl_op2_sel; // @[core.scala:114:32]
wire [2:0] _dispatcher_io_dis_uops_0_1_bits_ctrl_imm_sel; // @[core.scala:114:32]
wire [4:0] _dispatcher_io_dis_uops_0_1_bits_ctrl_op_fcn; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_1_bits_ctrl_fcn_dw; // @[core.scala:114:32]
wire [2:0] _dispatcher_io_dis_uops_0_1_bits_ctrl_csr_cmd; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_1_bits_ctrl_is_load; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_1_bits_ctrl_is_sta; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_1_bits_ctrl_is_std; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_0_1_bits_iw_state; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_1_bits_iw_p1_poisoned; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_1_bits_iw_p2_poisoned; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_1_bits_is_br; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_1_bits_is_jalr; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_1_bits_is_jal; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_1_bits_is_sfb; // @[core.scala:114:32]
wire [15:0] _dispatcher_io_dis_uops_0_1_bits_br_mask; // @[core.scala:114:32]
wire [3:0] _dispatcher_io_dis_uops_0_1_bits_br_tag; // @[core.scala:114:32]
wire [4:0] _dispatcher_io_dis_uops_0_1_bits_ftq_idx; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_1_bits_edge_inst; // @[core.scala:114:32]
wire [5:0] _dispatcher_io_dis_uops_0_1_bits_pc_lob; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_1_bits_taken; // @[core.scala:114:32]
wire [19:0] _dispatcher_io_dis_uops_0_1_bits_imm_packed; // @[core.scala:114:32]
wire [11:0] _dispatcher_io_dis_uops_0_1_bits_csr_addr; // @[core.scala:114:32]
wire [6:0] _dispatcher_io_dis_uops_0_1_bits_rob_idx; // @[core.scala:114:32]
wire [4:0] _dispatcher_io_dis_uops_0_1_bits_ldq_idx; // @[core.scala:114:32]
wire [4:0] _dispatcher_io_dis_uops_0_1_bits_stq_idx; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_0_1_bits_rxq_idx; // @[core.scala:114:32]
wire [6:0] _dispatcher_io_dis_uops_0_1_bits_pdst; // @[core.scala:114:32]
wire [6:0] _dispatcher_io_dis_uops_0_1_bits_prs1; // @[core.scala:114:32]
wire [6:0] _dispatcher_io_dis_uops_0_1_bits_prs2; // @[core.scala:114:32]
wire [6:0] _dispatcher_io_dis_uops_0_1_bits_prs3; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_1_bits_prs1_busy; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_1_bits_prs2_busy; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_1_bits_prs3_busy; // @[core.scala:114:32]
wire [6:0] _dispatcher_io_dis_uops_0_1_bits_stale_pdst; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_1_bits_exception; // @[core.scala:114:32]
wire [63:0] _dispatcher_io_dis_uops_0_1_bits_exc_cause; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_1_bits_bypassable; // @[core.scala:114:32]
wire [4:0] _dispatcher_io_dis_uops_0_1_bits_mem_cmd; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_0_1_bits_mem_size; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_1_bits_mem_signed; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_1_bits_is_fence; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_1_bits_is_fencei; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_1_bits_is_amo; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_1_bits_uses_ldq; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_1_bits_uses_stq; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_1_bits_is_sys_pc2epc; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_1_bits_is_unique; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_1_bits_flush_on_commit; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_1_bits_ldst_is_rs1; // @[core.scala:114:32]
wire [5:0] _dispatcher_io_dis_uops_0_1_bits_ldst; // @[core.scala:114:32]
wire [5:0] _dispatcher_io_dis_uops_0_1_bits_lrs1; // @[core.scala:114:32]
wire [5:0] _dispatcher_io_dis_uops_0_1_bits_lrs2; // @[core.scala:114:32]
wire [5:0] _dispatcher_io_dis_uops_0_1_bits_lrs3; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_1_bits_ldst_val; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_0_1_bits_dst_rtype; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_0_1_bits_lrs1_rtype; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_0_1_bits_lrs2_rtype; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_1_bits_frs3_en; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_1_bits_fp_val; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_1_bits_fp_single; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_1_bits_xcpt_pf_if; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_1_bits_xcpt_ae_if; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_1_bits_xcpt_ma_if; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_1_bits_bp_debug_if; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_1_bits_bp_xcpt_if; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_0_1_bits_debug_fsrc; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_0_1_bits_debug_tsrc; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_2_valid; // @[core.scala:114:32]
wire [6:0] _dispatcher_io_dis_uops_0_2_bits_uopc; // @[core.scala:114:32]
wire [31:0] _dispatcher_io_dis_uops_0_2_bits_inst; // @[core.scala:114:32]
wire [31:0] _dispatcher_io_dis_uops_0_2_bits_debug_inst; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_2_bits_is_rvc; // @[core.scala:114:32]
wire [39:0] _dispatcher_io_dis_uops_0_2_bits_debug_pc; // @[core.scala:114:32]
wire [2:0] _dispatcher_io_dis_uops_0_2_bits_iq_type; // @[core.scala:114:32]
wire [9:0] _dispatcher_io_dis_uops_0_2_bits_fu_code; // @[core.scala:114:32]
wire [3:0] _dispatcher_io_dis_uops_0_2_bits_ctrl_br_type; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_0_2_bits_ctrl_op1_sel; // @[core.scala:114:32]
wire [2:0] _dispatcher_io_dis_uops_0_2_bits_ctrl_op2_sel; // @[core.scala:114:32]
wire [2:0] _dispatcher_io_dis_uops_0_2_bits_ctrl_imm_sel; // @[core.scala:114:32]
wire [4:0] _dispatcher_io_dis_uops_0_2_bits_ctrl_op_fcn; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_2_bits_ctrl_fcn_dw; // @[core.scala:114:32]
wire [2:0] _dispatcher_io_dis_uops_0_2_bits_ctrl_csr_cmd; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_2_bits_ctrl_is_load; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_2_bits_ctrl_is_sta; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_2_bits_ctrl_is_std; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_0_2_bits_iw_state; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_2_bits_iw_p1_poisoned; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_2_bits_iw_p2_poisoned; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_2_bits_is_br; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_2_bits_is_jalr; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_2_bits_is_jal; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_2_bits_is_sfb; // @[core.scala:114:32]
wire [15:0] _dispatcher_io_dis_uops_0_2_bits_br_mask; // @[core.scala:114:32]
wire [3:0] _dispatcher_io_dis_uops_0_2_bits_br_tag; // @[core.scala:114:32]
wire [4:0] _dispatcher_io_dis_uops_0_2_bits_ftq_idx; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_2_bits_edge_inst; // @[core.scala:114:32]
wire [5:0] _dispatcher_io_dis_uops_0_2_bits_pc_lob; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_2_bits_taken; // @[core.scala:114:32]
wire [19:0] _dispatcher_io_dis_uops_0_2_bits_imm_packed; // @[core.scala:114:32]
wire [11:0] _dispatcher_io_dis_uops_0_2_bits_csr_addr; // @[core.scala:114:32]
wire [6:0] _dispatcher_io_dis_uops_0_2_bits_rob_idx; // @[core.scala:114:32]
wire [4:0] _dispatcher_io_dis_uops_0_2_bits_ldq_idx; // @[core.scala:114:32]
wire [4:0] _dispatcher_io_dis_uops_0_2_bits_stq_idx; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_0_2_bits_rxq_idx; // @[core.scala:114:32]
wire [6:0] _dispatcher_io_dis_uops_0_2_bits_pdst; // @[core.scala:114:32]
wire [6:0] _dispatcher_io_dis_uops_0_2_bits_prs1; // @[core.scala:114:32]
wire [6:0] _dispatcher_io_dis_uops_0_2_bits_prs2; // @[core.scala:114:32]
wire [6:0] _dispatcher_io_dis_uops_0_2_bits_prs3; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_2_bits_prs1_busy; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_2_bits_prs2_busy; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_2_bits_prs3_busy; // @[core.scala:114:32]
wire [6:0] _dispatcher_io_dis_uops_0_2_bits_stale_pdst; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_2_bits_exception; // @[core.scala:114:32]
wire [63:0] _dispatcher_io_dis_uops_0_2_bits_exc_cause; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_2_bits_bypassable; // @[core.scala:114:32]
wire [4:0] _dispatcher_io_dis_uops_0_2_bits_mem_cmd; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_0_2_bits_mem_size; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_2_bits_mem_signed; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_2_bits_is_fence; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_2_bits_is_fencei; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_2_bits_is_amo; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_2_bits_uses_ldq; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_2_bits_uses_stq; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_2_bits_is_sys_pc2epc; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_2_bits_is_unique; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_2_bits_flush_on_commit; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_2_bits_ldst_is_rs1; // @[core.scala:114:32]
wire [5:0] _dispatcher_io_dis_uops_0_2_bits_ldst; // @[core.scala:114:32]
wire [5:0] _dispatcher_io_dis_uops_0_2_bits_lrs1; // @[core.scala:114:32]
wire [5:0] _dispatcher_io_dis_uops_0_2_bits_lrs2; // @[core.scala:114:32]
wire [5:0] _dispatcher_io_dis_uops_0_2_bits_lrs3; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_2_bits_ldst_val; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_0_2_bits_dst_rtype; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_0_2_bits_lrs1_rtype; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_0_2_bits_lrs2_rtype; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_2_bits_frs3_en; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_2_bits_fp_val; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_2_bits_fp_single; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_2_bits_xcpt_pf_if; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_2_bits_xcpt_ae_if; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_2_bits_xcpt_ma_if; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_2_bits_bp_debug_if; // @[core.scala:114:32]
wire _dispatcher_io_dis_uops_0_2_bits_bp_xcpt_if; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_0_2_bits_debug_fsrc; // @[core.scala:114:32]
wire [1:0] _dispatcher_io_dis_uops_0_2_bits_debug_tsrc; // @[core.scala:114:32]
wire _int_issue_unit_io_dis_uops_0_ready; // @[core.scala:110:32]
wire _int_issue_unit_io_dis_uops_1_ready; // @[core.scala:110:32]
wire _int_issue_unit_io_dis_uops_2_ready; // @[core.scala:110:32]
wire _mem_issue_unit_io_dis_uops_0_ready; // @[core.scala:108:32]
wire _mem_issue_unit_io_dis_uops_1_ready; // @[core.scala:108:32]
wire _mem_issue_unit_io_dis_uops_2_ready; // @[core.scala:108:32]
wire _mem_issue_unit_io_iss_valids_0; // @[core.scala:108:32]
wire _mem_issue_unit_io_iss_uops_0_uses_ldq; // @[core.scala:108:32]
wire _fp_rename_stage_io_ren_stalls_0; // @[core.scala:104:46]
wire _fp_rename_stage_io_ren_stalls_1; // @[core.scala:104:46]
wire _fp_rename_stage_io_ren_stalls_2; // @[core.scala:104:46]
wire [6:0] _fp_rename_stage_io_ren2_uops_0_pdst; // @[core.scala:104:46]
wire [6:0] _fp_rename_stage_io_ren2_uops_0_prs1; // @[core.scala:104:46]
wire [6:0] _fp_rename_stage_io_ren2_uops_0_prs2; // @[core.scala:104:46]
wire _fp_rename_stage_io_ren2_uops_0_prs1_busy; // @[core.scala:104:46]
wire _fp_rename_stage_io_ren2_uops_0_prs2_busy; // @[core.scala:104:46]
wire _fp_rename_stage_io_ren2_uops_0_prs3_busy; // @[core.scala:104:46]
wire [6:0] _fp_rename_stage_io_ren2_uops_0_stale_pdst; // @[core.scala:104:46]
wire [6:0] _fp_rename_stage_io_ren2_uops_1_pdst; // @[core.scala:104:46]
wire [6:0] _fp_rename_stage_io_ren2_uops_1_prs1; // @[core.scala:104:46]
wire [6:0] _fp_rename_stage_io_ren2_uops_1_prs2; // @[core.scala:104:46]
wire _fp_rename_stage_io_ren2_uops_1_prs1_busy; // @[core.scala:104:46]
wire _fp_rename_stage_io_ren2_uops_1_prs2_busy; // @[core.scala:104:46]
wire _fp_rename_stage_io_ren2_uops_1_prs3_busy; // @[core.scala:104:46]
wire [6:0] _fp_rename_stage_io_ren2_uops_1_stale_pdst; // @[core.scala:104:46]
wire [6:0] _fp_rename_stage_io_ren2_uops_2_pdst; // @[core.scala:104:46]
wire [6:0] _fp_rename_stage_io_ren2_uops_2_prs1; // @[core.scala:104:46]
wire [6:0] _fp_rename_stage_io_ren2_uops_2_prs2; // @[core.scala:104:46]
wire _fp_rename_stage_io_ren2_uops_2_prs1_busy; // @[core.scala:104:46]
wire _fp_rename_stage_io_ren2_uops_2_prs2_busy; // @[core.scala:104:46]
wire _fp_rename_stage_io_ren2_uops_2_prs3_busy; // @[core.scala:104:46]
wire [6:0] _fp_rename_stage_io_ren2_uops_2_stale_pdst; // @[core.scala:104:46]
wire _rename_stage_io_ren_stalls_0; // @[core.scala:103:32]
wire _rename_stage_io_ren_stalls_1; // @[core.scala:103:32]
wire _rename_stage_io_ren_stalls_2; // @[core.scala:103:32]
wire [6:0] _rename_stage_io_ren2_uops_0_pdst; // @[core.scala:103:32]
wire [6:0] _rename_stage_io_ren2_uops_0_prs1; // @[core.scala:103:32]
wire [6:0] _rename_stage_io_ren2_uops_0_prs2; // @[core.scala:103:32]
wire _rename_stage_io_ren2_uops_0_prs1_busy; // @[core.scala:103:32]
wire _rename_stage_io_ren2_uops_0_prs2_busy; // @[core.scala:103:32]
wire [6:0] _rename_stage_io_ren2_uops_0_stale_pdst; // @[core.scala:103:32]
wire [6:0] _rename_stage_io_ren2_uops_1_pdst; // @[core.scala:103:32]
wire [6:0] _rename_stage_io_ren2_uops_1_prs1; // @[core.scala:103:32]
wire [6:0] _rename_stage_io_ren2_uops_1_prs2; // @[core.scala:103:32]
wire _rename_stage_io_ren2_uops_1_prs1_busy; // @[core.scala:103:32]
wire _rename_stage_io_ren2_uops_1_prs2_busy; // @[core.scala:103:32]
wire [6:0] _rename_stage_io_ren2_uops_1_stale_pdst; // @[core.scala:103:32]
wire [6:0] _rename_stage_io_ren2_uops_2_pdst; // @[core.scala:103:32]
wire [6:0] _rename_stage_io_ren2_uops_2_prs1; // @[core.scala:103:32]
wire [6:0] _rename_stage_io_ren2_uops_2_prs2; // @[core.scala:103:32]
wire _rename_stage_io_ren2_uops_2_prs1_busy; // @[core.scala:103:32]
wire _rename_stage_io_ren2_uops_2_prs2_busy; // @[core.scala:103:32]
wire [6:0] _rename_stage_io_ren2_uops_2_stale_pdst; // @[core.scala:103:32]
wire [31:0] _decode_units_2_io_csr_decode_inst; // @[core.scala:101:79]
wire [31:0] _decode_units_1_io_csr_decode_inst; // @[core.scala:101:79]
wire [31:0] _decode_units_0_io_csr_decode_inst; // @[core.scala:101:79]
wire _FpPipeline_io_dis_uops_0_ready; // @[core.scala:80:37]
wire _FpPipeline_io_dis_uops_1_ready; // @[core.scala:80:37]
wire _FpPipeline_io_dis_uops_2_ready; // @[core.scala:80:37]
wire _FpPipeline_io_from_int_ready; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_valid; // @[core.scala:80:37]
wire [6:0] _FpPipeline_io_to_int_bits_uop_uopc; // @[core.scala:80:37]
wire [31:0] _FpPipeline_io_to_int_bits_uop_inst; // @[core.scala:80:37]
wire [31:0] _FpPipeline_io_to_int_bits_uop_debug_inst; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_uop_is_rvc; // @[core.scala:80:37]
wire [39:0] _FpPipeline_io_to_int_bits_uop_debug_pc; // @[core.scala:80:37]
wire [2:0] _FpPipeline_io_to_int_bits_uop_iq_type; // @[core.scala:80:37]
wire [9:0] _FpPipeline_io_to_int_bits_uop_fu_code; // @[core.scala:80:37]
wire [3:0] _FpPipeline_io_to_int_bits_uop_ctrl_br_type; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_to_int_bits_uop_ctrl_op1_sel; // @[core.scala:80:37]
wire [2:0] _FpPipeline_io_to_int_bits_uop_ctrl_op2_sel; // @[core.scala:80:37]
wire [2:0] _FpPipeline_io_to_int_bits_uop_ctrl_imm_sel; // @[core.scala:80:37]
wire [4:0] _FpPipeline_io_to_int_bits_uop_ctrl_op_fcn; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_uop_ctrl_fcn_dw; // @[core.scala:80:37]
wire [2:0] _FpPipeline_io_to_int_bits_uop_ctrl_csr_cmd; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_uop_ctrl_is_load; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_uop_ctrl_is_sta; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_uop_ctrl_is_std; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_to_int_bits_uop_iw_state; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_uop_iw_p1_poisoned; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_uop_iw_p2_poisoned; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_uop_is_br; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_uop_is_jalr; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_uop_is_jal; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_uop_is_sfb; // @[core.scala:80:37]
wire [15:0] _FpPipeline_io_to_int_bits_uop_br_mask; // @[core.scala:80:37]
wire [3:0] _FpPipeline_io_to_int_bits_uop_br_tag; // @[core.scala:80:37]
wire [4:0] _FpPipeline_io_to_int_bits_uop_ftq_idx; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_uop_edge_inst; // @[core.scala:80:37]
wire [5:0] _FpPipeline_io_to_int_bits_uop_pc_lob; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_uop_taken; // @[core.scala:80:37]
wire [19:0] _FpPipeline_io_to_int_bits_uop_imm_packed; // @[core.scala:80:37]
wire [11:0] _FpPipeline_io_to_int_bits_uop_csr_addr; // @[core.scala:80:37]
wire [6:0] _FpPipeline_io_to_int_bits_uop_rob_idx; // @[core.scala:80:37]
wire [4:0] _FpPipeline_io_to_int_bits_uop_ldq_idx; // @[core.scala:80:37]
wire [4:0] _FpPipeline_io_to_int_bits_uop_stq_idx; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_to_int_bits_uop_rxq_idx; // @[core.scala:80:37]
wire [6:0] _FpPipeline_io_to_int_bits_uop_pdst; // @[core.scala:80:37]
wire [6:0] _FpPipeline_io_to_int_bits_uop_prs1; // @[core.scala:80:37]
wire [6:0] _FpPipeline_io_to_int_bits_uop_prs2; // @[core.scala:80:37]
wire [6:0] _FpPipeline_io_to_int_bits_uop_prs3; // @[core.scala:80:37]
wire [4:0] _FpPipeline_io_to_int_bits_uop_ppred; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_uop_prs1_busy; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_uop_prs2_busy; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_uop_prs3_busy; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_uop_ppred_busy; // @[core.scala:80:37]
wire [6:0] _FpPipeline_io_to_int_bits_uop_stale_pdst; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_uop_exception; // @[core.scala:80:37]
wire [63:0] _FpPipeline_io_to_int_bits_uop_exc_cause; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_uop_bypassable; // @[core.scala:80:37]
wire [4:0] _FpPipeline_io_to_int_bits_uop_mem_cmd; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_to_int_bits_uop_mem_size; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_uop_mem_signed; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_uop_is_fence; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_uop_is_fencei; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_uop_is_amo; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_uop_uses_ldq; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_uop_uses_stq; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_uop_is_sys_pc2epc; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_uop_is_unique; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_uop_flush_on_commit; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_uop_ldst_is_rs1; // @[core.scala:80:37]
wire [5:0] _FpPipeline_io_to_int_bits_uop_ldst; // @[core.scala:80:37]
wire [5:0] _FpPipeline_io_to_int_bits_uop_lrs1; // @[core.scala:80:37]
wire [5:0] _FpPipeline_io_to_int_bits_uop_lrs2; // @[core.scala:80:37]
wire [5:0] _FpPipeline_io_to_int_bits_uop_lrs3; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_uop_ldst_val; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_to_int_bits_uop_dst_rtype; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_to_int_bits_uop_lrs1_rtype; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_to_int_bits_uop_lrs2_rtype; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_uop_frs3_en; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_uop_fp_val; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_uop_fp_single; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_uop_xcpt_pf_if; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_uop_xcpt_ae_if; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_uop_xcpt_ma_if; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_uop_bp_debug_if; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_uop_bp_xcpt_if; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_to_int_bits_uop_debug_fsrc; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_to_int_bits_uop_debug_tsrc; // @[core.scala:80:37]
wire [63:0] _FpPipeline_io_to_int_bits_data; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_predicated; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_fflags_valid; // @[core.scala:80:37]
wire [6:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_uopc; // @[core.scala:80:37]
wire [31:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_inst; // @[core.scala:80:37]
wire [31:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_debug_inst; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_fflags_bits_uop_is_rvc; // @[core.scala:80:37]
wire [39:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_debug_pc; // @[core.scala:80:37]
wire [2:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_iq_type; // @[core.scala:80:37]
wire [9:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_fu_code; // @[core.scala:80:37]
wire [3:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_ctrl_br_type; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_ctrl_op1_sel; // @[core.scala:80:37]
wire [2:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_ctrl_op2_sel; // @[core.scala:80:37]
wire [2:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_ctrl_imm_sel; // @[core.scala:80:37]
wire [4:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_ctrl_op_fcn; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_fflags_bits_uop_ctrl_fcn_dw; // @[core.scala:80:37]
wire [2:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_ctrl_csr_cmd; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_fflags_bits_uop_ctrl_is_load; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_fflags_bits_uop_ctrl_is_sta; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_fflags_bits_uop_ctrl_is_std; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_iw_state; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_fflags_bits_uop_iw_p1_poisoned; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_fflags_bits_uop_iw_p2_poisoned; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_fflags_bits_uop_is_br; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_fflags_bits_uop_is_jalr; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_fflags_bits_uop_is_jal; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_fflags_bits_uop_is_sfb; // @[core.scala:80:37]
wire [15:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_br_mask; // @[core.scala:80:37]
wire [3:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_br_tag; // @[core.scala:80:37]
wire [4:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_ftq_idx; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_fflags_bits_uop_edge_inst; // @[core.scala:80:37]
wire [5:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_pc_lob; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_fflags_bits_uop_taken; // @[core.scala:80:37]
wire [19:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_imm_packed; // @[core.scala:80:37]
wire [11:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_csr_addr; // @[core.scala:80:37]
wire [6:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_rob_idx; // @[core.scala:80:37]
wire [4:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_ldq_idx; // @[core.scala:80:37]
wire [4:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_stq_idx; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_rxq_idx; // @[core.scala:80:37]
wire [6:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_pdst; // @[core.scala:80:37]
wire [6:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_prs1; // @[core.scala:80:37]
wire [6:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_prs2; // @[core.scala:80:37]
wire [6:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_prs3; // @[core.scala:80:37]
wire [4:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_ppred; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_fflags_bits_uop_prs1_busy; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_fflags_bits_uop_prs2_busy; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_fflags_bits_uop_prs3_busy; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_fflags_bits_uop_ppred_busy; // @[core.scala:80:37]
wire [6:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_stale_pdst; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_fflags_bits_uop_exception; // @[core.scala:80:37]
wire [63:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_exc_cause; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_fflags_bits_uop_bypassable; // @[core.scala:80:37]
wire [4:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_mem_cmd; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_mem_size; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_fflags_bits_uop_mem_signed; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_fflags_bits_uop_is_fence; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_fflags_bits_uop_is_fencei; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_fflags_bits_uop_is_amo; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_fflags_bits_uop_uses_ldq; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_fflags_bits_uop_uses_stq; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_fflags_bits_uop_is_sys_pc2epc; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_fflags_bits_uop_is_unique; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_fflags_bits_uop_flush_on_commit; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_fflags_bits_uop_ldst_is_rs1; // @[core.scala:80:37]
wire [5:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_ldst; // @[core.scala:80:37]
wire [5:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_lrs1; // @[core.scala:80:37]
wire [5:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_lrs2; // @[core.scala:80:37]
wire [5:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_lrs3; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_fflags_bits_uop_ldst_val; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_dst_rtype; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_lrs1_rtype; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_lrs2_rtype; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_fflags_bits_uop_frs3_en; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_fflags_bits_uop_fp_val; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_fflags_bits_uop_fp_single; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_fflags_bits_uop_xcpt_pf_if; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_fflags_bits_uop_xcpt_ae_if; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_fflags_bits_uop_xcpt_ma_if; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_fflags_bits_uop_bp_debug_if; // @[core.scala:80:37]
wire _FpPipeline_io_to_int_bits_fflags_bits_uop_bp_xcpt_if; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_debug_fsrc; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_debug_tsrc; // @[core.scala:80:37]
wire [4:0] _FpPipeline_io_to_int_bits_fflags_bits_flags; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_valid; // @[core.scala:80:37]
wire [6:0] _FpPipeline_io_wakeups_0_bits_uop_uopc; // @[core.scala:80:37]
wire [31:0] _FpPipeline_io_wakeups_0_bits_uop_inst; // @[core.scala:80:37]
wire [31:0] _FpPipeline_io_wakeups_0_bits_uop_debug_inst; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_uop_is_rvc; // @[core.scala:80:37]
wire [39:0] _FpPipeline_io_wakeups_0_bits_uop_debug_pc; // @[core.scala:80:37]
wire [2:0] _FpPipeline_io_wakeups_0_bits_uop_iq_type; // @[core.scala:80:37]
wire [9:0] _FpPipeline_io_wakeups_0_bits_uop_fu_code; // @[core.scala:80:37]
wire [3:0] _FpPipeline_io_wakeups_0_bits_uop_ctrl_br_type; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_wakeups_0_bits_uop_ctrl_op1_sel; // @[core.scala:80:37]
wire [2:0] _FpPipeline_io_wakeups_0_bits_uop_ctrl_op2_sel; // @[core.scala:80:37]
wire [2:0] _FpPipeline_io_wakeups_0_bits_uop_ctrl_imm_sel; // @[core.scala:80:37]
wire [4:0] _FpPipeline_io_wakeups_0_bits_uop_ctrl_op_fcn; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_uop_ctrl_fcn_dw; // @[core.scala:80:37]
wire [2:0] _FpPipeline_io_wakeups_0_bits_uop_ctrl_csr_cmd; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_uop_ctrl_is_load; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_uop_ctrl_is_sta; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_uop_ctrl_is_std; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_wakeups_0_bits_uop_iw_state; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_uop_iw_p1_poisoned; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_uop_iw_p2_poisoned; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_uop_is_br; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_uop_is_jalr; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_uop_is_jal; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_uop_is_sfb; // @[core.scala:80:37]
wire [15:0] _FpPipeline_io_wakeups_0_bits_uop_br_mask; // @[core.scala:80:37]
wire [3:0] _FpPipeline_io_wakeups_0_bits_uop_br_tag; // @[core.scala:80:37]
wire [4:0] _FpPipeline_io_wakeups_0_bits_uop_ftq_idx; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_uop_edge_inst; // @[core.scala:80:37]
wire [5:0] _FpPipeline_io_wakeups_0_bits_uop_pc_lob; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_uop_taken; // @[core.scala:80:37]
wire [19:0] _FpPipeline_io_wakeups_0_bits_uop_imm_packed; // @[core.scala:80:37]
wire [11:0] _FpPipeline_io_wakeups_0_bits_uop_csr_addr; // @[core.scala:80:37]
wire [6:0] _FpPipeline_io_wakeups_0_bits_uop_rob_idx; // @[core.scala:80:37]
wire [4:0] _FpPipeline_io_wakeups_0_bits_uop_ldq_idx; // @[core.scala:80:37]
wire [4:0] _FpPipeline_io_wakeups_0_bits_uop_stq_idx; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_wakeups_0_bits_uop_rxq_idx; // @[core.scala:80:37]
wire [6:0] _FpPipeline_io_wakeups_0_bits_uop_pdst; // @[core.scala:80:37]
wire [6:0] _FpPipeline_io_wakeups_0_bits_uop_prs1; // @[core.scala:80:37]
wire [6:0] _FpPipeline_io_wakeups_0_bits_uop_prs2; // @[core.scala:80:37]
wire [6:0] _FpPipeline_io_wakeups_0_bits_uop_prs3; // @[core.scala:80:37]
wire [4:0] _FpPipeline_io_wakeups_0_bits_uop_ppred; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_uop_prs1_busy; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_uop_prs2_busy; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_uop_prs3_busy; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_uop_ppred_busy; // @[core.scala:80:37]
wire [6:0] _FpPipeline_io_wakeups_0_bits_uop_stale_pdst; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_uop_exception; // @[core.scala:80:37]
wire [63:0] _FpPipeline_io_wakeups_0_bits_uop_exc_cause; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_uop_bypassable; // @[core.scala:80:37]
wire [4:0] _FpPipeline_io_wakeups_0_bits_uop_mem_cmd; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_wakeups_0_bits_uop_mem_size; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_uop_mem_signed; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_uop_is_fence; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_uop_is_fencei; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_uop_is_amo; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_uop_uses_ldq; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_uop_uses_stq; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_uop_is_sys_pc2epc; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_uop_is_unique; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_uop_flush_on_commit; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_uop_ldst_is_rs1; // @[core.scala:80:37]
wire [5:0] _FpPipeline_io_wakeups_0_bits_uop_ldst; // @[core.scala:80:37]
wire [5:0] _FpPipeline_io_wakeups_0_bits_uop_lrs1; // @[core.scala:80:37]
wire [5:0] _FpPipeline_io_wakeups_0_bits_uop_lrs2; // @[core.scala:80:37]
wire [5:0] _FpPipeline_io_wakeups_0_bits_uop_lrs3; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_uop_ldst_val; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_wakeups_0_bits_uop_dst_rtype; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_wakeups_0_bits_uop_lrs1_rtype; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_wakeups_0_bits_uop_lrs2_rtype; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_uop_frs3_en; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_uop_fp_val; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_uop_fp_single; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_uop_xcpt_pf_if; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_uop_xcpt_ae_if; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_uop_xcpt_ma_if; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_uop_bp_debug_if; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_uop_bp_xcpt_if; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_wakeups_0_bits_uop_debug_fsrc; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_wakeups_0_bits_uop_debug_tsrc; // @[core.scala:80:37]
wire [64:0] _FpPipeline_io_wakeups_0_bits_data; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_predicated; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_fflags_valid; // @[core.scala:80:37]
wire [6:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_uopc; // @[core.scala:80:37]
wire [31:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_inst; // @[core.scala:80:37]
wire [31:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_debug_inst; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_is_rvc; // @[core.scala:80:37]
wire [39:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_debug_pc; // @[core.scala:80:37]
wire [2:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_iq_type; // @[core.scala:80:37]
wire [9:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_fu_code; // @[core.scala:80:37]
wire [3:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_ctrl_br_type; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_ctrl_op1_sel; // @[core.scala:80:37]
wire [2:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_ctrl_op2_sel; // @[core.scala:80:37]
wire [2:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_ctrl_imm_sel; // @[core.scala:80:37]
wire [4:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_ctrl_op_fcn; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_ctrl_fcn_dw; // @[core.scala:80:37]
wire [2:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_ctrl_csr_cmd; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_ctrl_is_load; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_ctrl_is_sta; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_ctrl_is_std; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_iw_state; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_iw_p1_poisoned; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_iw_p2_poisoned; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_is_br; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_is_jalr; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_is_jal; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_is_sfb; // @[core.scala:80:37]
wire [15:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_br_mask; // @[core.scala:80:37]
wire [3:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_br_tag; // @[core.scala:80:37]
wire [4:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_ftq_idx; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_edge_inst; // @[core.scala:80:37]
wire [5:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_pc_lob; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_taken; // @[core.scala:80:37]
wire [19:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_imm_packed; // @[core.scala:80:37]
wire [11:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_csr_addr; // @[core.scala:80:37]
wire [6:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_rob_idx; // @[core.scala:80:37]
wire [4:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_ldq_idx; // @[core.scala:80:37]
wire [4:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_stq_idx; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_rxq_idx; // @[core.scala:80:37]
wire [6:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_pdst; // @[core.scala:80:37]
wire [6:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_prs1; // @[core.scala:80:37]
wire [6:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_prs2; // @[core.scala:80:37]
wire [6:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_prs3; // @[core.scala:80:37]
wire [4:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_ppred; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_prs1_busy; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_prs2_busy; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_prs3_busy; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_ppred_busy; // @[core.scala:80:37]
wire [6:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_stale_pdst; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_exception; // @[core.scala:80:37]
wire [63:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_exc_cause; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_bypassable; // @[core.scala:80:37]
wire [4:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_mem_cmd; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_mem_size; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_mem_signed; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_is_fence; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_is_fencei; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_is_amo; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_uses_ldq; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_uses_stq; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_is_sys_pc2epc; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_is_unique; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_flush_on_commit; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_ldst_is_rs1; // @[core.scala:80:37]
wire [5:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_ldst; // @[core.scala:80:37]
wire [5:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_lrs1; // @[core.scala:80:37]
wire [5:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_lrs2; // @[core.scala:80:37]
wire [5:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_lrs3; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_ldst_val; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_dst_rtype; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_lrs1_rtype; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_lrs2_rtype; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_frs3_en; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_fp_val; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_fp_single; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_xcpt_pf_if; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_xcpt_ae_if; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_xcpt_ma_if; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_bp_debug_if; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_bp_xcpt_if; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_debug_fsrc; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_debug_tsrc; // @[core.scala:80:37]
wire [4:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_flags; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_valid; // @[core.scala:80:37]
wire [6:0] _FpPipeline_io_wakeups_1_bits_uop_uopc; // @[core.scala:80:37]
wire [31:0] _FpPipeline_io_wakeups_1_bits_uop_inst; // @[core.scala:80:37]
wire [31:0] _FpPipeline_io_wakeups_1_bits_uop_debug_inst; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_uop_is_rvc; // @[core.scala:80:37]
wire [39:0] _FpPipeline_io_wakeups_1_bits_uop_debug_pc; // @[core.scala:80:37]
wire [2:0] _FpPipeline_io_wakeups_1_bits_uop_iq_type; // @[core.scala:80:37]
wire [9:0] _FpPipeline_io_wakeups_1_bits_uop_fu_code; // @[core.scala:80:37]
wire [3:0] _FpPipeline_io_wakeups_1_bits_uop_ctrl_br_type; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_wakeups_1_bits_uop_ctrl_op1_sel; // @[core.scala:80:37]
wire [2:0] _FpPipeline_io_wakeups_1_bits_uop_ctrl_op2_sel; // @[core.scala:80:37]
wire [2:0] _FpPipeline_io_wakeups_1_bits_uop_ctrl_imm_sel; // @[core.scala:80:37]
wire [4:0] _FpPipeline_io_wakeups_1_bits_uop_ctrl_op_fcn; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_uop_ctrl_fcn_dw; // @[core.scala:80:37]
wire [2:0] _FpPipeline_io_wakeups_1_bits_uop_ctrl_csr_cmd; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_uop_ctrl_is_load; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_uop_ctrl_is_sta; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_uop_ctrl_is_std; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_wakeups_1_bits_uop_iw_state; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_uop_iw_p1_poisoned; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_uop_iw_p2_poisoned; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_uop_is_br; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_uop_is_jalr; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_uop_is_jal; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_uop_is_sfb; // @[core.scala:80:37]
wire [15:0] _FpPipeline_io_wakeups_1_bits_uop_br_mask; // @[core.scala:80:37]
wire [3:0] _FpPipeline_io_wakeups_1_bits_uop_br_tag; // @[core.scala:80:37]
wire [4:0] _FpPipeline_io_wakeups_1_bits_uop_ftq_idx; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_uop_edge_inst; // @[core.scala:80:37]
wire [5:0] _FpPipeline_io_wakeups_1_bits_uop_pc_lob; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_uop_taken; // @[core.scala:80:37]
wire [19:0] _FpPipeline_io_wakeups_1_bits_uop_imm_packed; // @[core.scala:80:37]
wire [11:0] _FpPipeline_io_wakeups_1_bits_uop_csr_addr; // @[core.scala:80:37]
wire [6:0] _FpPipeline_io_wakeups_1_bits_uop_rob_idx; // @[core.scala:80:37]
wire [4:0] _FpPipeline_io_wakeups_1_bits_uop_ldq_idx; // @[core.scala:80:37]
wire [4:0] _FpPipeline_io_wakeups_1_bits_uop_stq_idx; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_wakeups_1_bits_uop_rxq_idx; // @[core.scala:80:37]
wire [6:0] _FpPipeline_io_wakeups_1_bits_uop_pdst; // @[core.scala:80:37]
wire [6:0] _FpPipeline_io_wakeups_1_bits_uop_prs1; // @[core.scala:80:37]
wire [6:0] _FpPipeline_io_wakeups_1_bits_uop_prs2; // @[core.scala:80:37]
wire [6:0] _FpPipeline_io_wakeups_1_bits_uop_prs3; // @[core.scala:80:37]
wire [4:0] _FpPipeline_io_wakeups_1_bits_uop_ppred; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_uop_prs1_busy; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_uop_prs2_busy; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_uop_prs3_busy; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_uop_ppred_busy; // @[core.scala:80:37]
wire [6:0] _FpPipeline_io_wakeups_1_bits_uop_stale_pdst; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_uop_exception; // @[core.scala:80:37]
wire [63:0] _FpPipeline_io_wakeups_1_bits_uop_exc_cause; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_uop_bypassable; // @[core.scala:80:37]
wire [4:0] _FpPipeline_io_wakeups_1_bits_uop_mem_cmd; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_wakeups_1_bits_uop_mem_size; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_uop_mem_signed; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_uop_is_fence; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_uop_is_fencei; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_uop_is_amo; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_uop_uses_ldq; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_uop_uses_stq; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_uop_is_sys_pc2epc; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_uop_is_unique; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_uop_flush_on_commit; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_uop_ldst_is_rs1; // @[core.scala:80:37]
wire [5:0] _FpPipeline_io_wakeups_1_bits_uop_ldst; // @[core.scala:80:37]
wire [5:0] _FpPipeline_io_wakeups_1_bits_uop_lrs1; // @[core.scala:80:37]
wire [5:0] _FpPipeline_io_wakeups_1_bits_uop_lrs2; // @[core.scala:80:37]
wire [5:0] _FpPipeline_io_wakeups_1_bits_uop_lrs3; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_uop_ldst_val; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_wakeups_1_bits_uop_dst_rtype; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_wakeups_1_bits_uop_lrs1_rtype; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_wakeups_1_bits_uop_lrs2_rtype; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_uop_frs3_en; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_uop_fp_val; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_uop_fp_single; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_uop_xcpt_pf_if; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_uop_xcpt_ae_if; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_uop_xcpt_ma_if; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_uop_bp_debug_if; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_uop_bp_xcpt_if; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_wakeups_1_bits_uop_debug_fsrc; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_wakeups_1_bits_uop_debug_tsrc; // @[core.scala:80:37]
wire [64:0] _FpPipeline_io_wakeups_1_bits_data; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_fflags_valid; // @[core.scala:80:37]
wire [6:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_uopc; // @[core.scala:80:37]
wire [31:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_inst; // @[core.scala:80:37]
wire [31:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_debug_inst; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_is_rvc; // @[core.scala:80:37]
wire [39:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_debug_pc; // @[core.scala:80:37]
wire [2:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_iq_type; // @[core.scala:80:37]
wire [9:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_fu_code; // @[core.scala:80:37]
wire [3:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_ctrl_br_type; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_ctrl_op1_sel; // @[core.scala:80:37]
wire [2:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_ctrl_op2_sel; // @[core.scala:80:37]
wire [2:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_ctrl_imm_sel; // @[core.scala:80:37]
wire [4:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_ctrl_op_fcn; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_ctrl_fcn_dw; // @[core.scala:80:37]
wire [2:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_ctrl_csr_cmd; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_ctrl_is_load; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_ctrl_is_sta; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_ctrl_is_std; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_iw_state; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_iw_p1_poisoned; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_iw_p2_poisoned; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_is_br; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_is_jalr; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_is_jal; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_is_sfb; // @[core.scala:80:37]
wire [15:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_br_mask; // @[core.scala:80:37]
wire [3:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_br_tag; // @[core.scala:80:37]
wire [4:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_ftq_idx; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_edge_inst; // @[core.scala:80:37]
wire [5:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_pc_lob; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_taken; // @[core.scala:80:37]
wire [19:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_imm_packed; // @[core.scala:80:37]
wire [11:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_csr_addr; // @[core.scala:80:37]
wire [6:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_rob_idx; // @[core.scala:80:37]
wire [4:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_ldq_idx; // @[core.scala:80:37]
wire [4:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_stq_idx; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_rxq_idx; // @[core.scala:80:37]
wire [6:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_pdst; // @[core.scala:80:37]
wire [6:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_prs1; // @[core.scala:80:37]
wire [6:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_prs2; // @[core.scala:80:37]
wire [6:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_prs3; // @[core.scala:80:37]
wire [4:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_ppred; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_prs1_busy; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_prs2_busy; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_prs3_busy; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_ppred_busy; // @[core.scala:80:37]
wire [6:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_stale_pdst; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_exception; // @[core.scala:80:37]
wire [63:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_exc_cause; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_bypassable; // @[core.scala:80:37]
wire [4:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_mem_cmd; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_mem_size; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_mem_signed; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_is_fence; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_is_fencei; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_is_amo; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_uses_ldq; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_uses_stq; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_is_sys_pc2epc; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_is_unique; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_flush_on_commit; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_ldst_is_rs1; // @[core.scala:80:37]
wire [5:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_ldst; // @[core.scala:80:37]
wire [5:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_lrs1; // @[core.scala:80:37]
wire [5:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_lrs2; // @[core.scala:80:37]
wire [5:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_lrs3; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_ldst_val; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_dst_rtype; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_lrs1_rtype; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_lrs2_rtype; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_frs3_en; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_fp_val; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_fp_single; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_xcpt_pf_if; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_xcpt_ae_if; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_xcpt_ma_if; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_bp_debug_if; // @[core.scala:80:37]
wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_bp_xcpt_if; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_debug_fsrc; // @[core.scala:80:37]
wire [1:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_debug_tsrc; // @[core.scala:80:37]
wire [4:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_flags; // @[core.scala:80:37]
wire [64:0] _FpPipeline_io_debug_wb_wdata_0; // @[core.scala:80:37]
wire [64:0] _FpPipeline_io_debug_wb_wdata_1; // @[core.scala:80:37]
wire _alu_exe_unit_2_io_iresp_valid; // @[execution-units.scala:119:32]
wire [6:0] _alu_exe_unit_2_io_iresp_bits_uop_uopc; // @[execution-units.scala:119:32]
wire [31:0] _alu_exe_unit_2_io_iresp_bits_uop_inst; // @[execution-units.scala:119:32]
wire [31:0] _alu_exe_unit_2_io_iresp_bits_uop_debug_inst; // @[execution-units.scala:119:32]
wire _alu_exe_unit_2_io_iresp_bits_uop_is_rvc; // @[execution-units.scala:119:32]
wire [39:0] _alu_exe_unit_2_io_iresp_bits_uop_debug_pc; // @[execution-units.scala:119:32]
wire [2:0] _alu_exe_unit_2_io_iresp_bits_uop_iq_type; // @[execution-units.scala:119:32]
wire [9:0] _alu_exe_unit_2_io_iresp_bits_uop_fu_code; // @[execution-units.scala:119:32]
wire [3:0] _alu_exe_unit_2_io_iresp_bits_uop_ctrl_br_type; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_2_io_iresp_bits_uop_ctrl_op1_sel; // @[execution-units.scala:119:32]
wire [2:0] _alu_exe_unit_2_io_iresp_bits_uop_ctrl_op2_sel; // @[execution-units.scala:119:32]
wire [2:0] _alu_exe_unit_2_io_iresp_bits_uop_ctrl_imm_sel; // @[execution-units.scala:119:32]
wire [4:0] _alu_exe_unit_2_io_iresp_bits_uop_ctrl_op_fcn; // @[execution-units.scala:119:32]
wire _alu_exe_unit_2_io_iresp_bits_uop_ctrl_fcn_dw; // @[execution-units.scala:119:32]
wire [2:0] _alu_exe_unit_2_io_iresp_bits_uop_ctrl_csr_cmd; // @[execution-units.scala:119:32]
wire _alu_exe_unit_2_io_iresp_bits_uop_ctrl_is_load; // @[execution-units.scala:119:32]
wire _alu_exe_unit_2_io_iresp_bits_uop_ctrl_is_sta; // @[execution-units.scala:119:32]
wire _alu_exe_unit_2_io_iresp_bits_uop_ctrl_is_std; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_2_io_iresp_bits_uop_iw_state; // @[execution-units.scala:119:32]
wire _alu_exe_unit_2_io_iresp_bits_uop_iw_p1_poisoned; // @[execution-units.scala:119:32]
wire _alu_exe_unit_2_io_iresp_bits_uop_iw_p2_poisoned; // @[execution-units.scala:119:32]
wire _alu_exe_unit_2_io_iresp_bits_uop_is_br; // @[execution-units.scala:119:32]
wire _alu_exe_unit_2_io_iresp_bits_uop_is_jalr; // @[execution-units.scala:119:32]
wire _alu_exe_unit_2_io_iresp_bits_uop_is_jal; // @[execution-units.scala:119:32]
wire _alu_exe_unit_2_io_iresp_bits_uop_is_sfb; // @[execution-units.scala:119:32]
wire [15:0] _alu_exe_unit_2_io_iresp_bits_uop_br_mask; // @[execution-units.scala:119:32]
wire [3:0] _alu_exe_unit_2_io_iresp_bits_uop_br_tag; // @[execution-units.scala:119:32]
wire [4:0] _alu_exe_unit_2_io_iresp_bits_uop_ftq_idx; // @[execution-units.scala:119:32]
wire _alu_exe_unit_2_io_iresp_bits_uop_edge_inst; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_2_io_iresp_bits_uop_pc_lob; // @[execution-units.scala:119:32]
wire _alu_exe_unit_2_io_iresp_bits_uop_taken; // @[execution-units.scala:119:32]
wire [19:0] _alu_exe_unit_2_io_iresp_bits_uop_imm_packed; // @[execution-units.scala:119:32]
wire [11:0] _alu_exe_unit_2_io_iresp_bits_uop_csr_addr; // @[execution-units.scala:119:32]
wire [6:0] _alu_exe_unit_2_io_iresp_bits_uop_rob_idx; // @[execution-units.scala:119:32]
wire [4:0] _alu_exe_unit_2_io_iresp_bits_uop_ldq_idx; // @[execution-units.scala:119:32]
wire [4:0] _alu_exe_unit_2_io_iresp_bits_uop_stq_idx; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_2_io_iresp_bits_uop_rxq_idx; // @[execution-units.scala:119:32]
wire [6:0] _alu_exe_unit_2_io_iresp_bits_uop_pdst; // @[execution-units.scala:119:32]
wire [6:0] _alu_exe_unit_2_io_iresp_bits_uop_prs1; // @[execution-units.scala:119:32]
wire [6:0] _alu_exe_unit_2_io_iresp_bits_uop_prs2; // @[execution-units.scala:119:32]
wire [6:0] _alu_exe_unit_2_io_iresp_bits_uop_prs3; // @[execution-units.scala:119:32]
wire [4:0] _alu_exe_unit_2_io_iresp_bits_uop_ppred; // @[execution-units.scala:119:32]
wire _alu_exe_unit_2_io_iresp_bits_uop_prs1_busy; // @[execution-units.scala:119:32]
wire _alu_exe_unit_2_io_iresp_bits_uop_prs2_busy; // @[execution-units.scala:119:32]
wire _alu_exe_unit_2_io_iresp_bits_uop_prs3_busy; // @[execution-units.scala:119:32]
wire _alu_exe_unit_2_io_iresp_bits_uop_ppred_busy; // @[execution-units.scala:119:32]
wire [6:0] _alu_exe_unit_2_io_iresp_bits_uop_stale_pdst; // @[execution-units.scala:119:32]
wire _alu_exe_unit_2_io_iresp_bits_uop_exception; // @[execution-units.scala:119:32]
wire [63:0] _alu_exe_unit_2_io_iresp_bits_uop_exc_cause; // @[execution-units.scala:119:32]
wire _alu_exe_unit_2_io_iresp_bits_uop_bypassable; // @[execution-units.scala:119:32]
wire [4:0] _alu_exe_unit_2_io_iresp_bits_uop_mem_cmd; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_2_io_iresp_bits_uop_mem_size; // @[execution-units.scala:119:32]
wire _alu_exe_unit_2_io_iresp_bits_uop_mem_signed; // @[execution-units.scala:119:32]
wire _alu_exe_unit_2_io_iresp_bits_uop_is_fence; // @[execution-units.scala:119:32]
wire _alu_exe_unit_2_io_iresp_bits_uop_is_fencei; // @[execution-units.scala:119:32]
wire _alu_exe_unit_2_io_iresp_bits_uop_is_amo; // @[execution-units.scala:119:32]
wire _alu_exe_unit_2_io_iresp_bits_uop_uses_ldq; // @[execution-units.scala:119:32]
wire _alu_exe_unit_2_io_iresp_bits_uop_uses_stq; // @[execution-units.scala:119:32]
wire _alu_exe_unit_2_io_iresp_bits_uop_is_sys_pc2epc; // @[execution-units.scala:119:32]
wire _alu_exe_unit_2_io_iresp_bits_uop_is_unique; // @[execution-units.scala:119:32]
wire _alu_exe_unit_2_io_iresp_bits_uop_flush_on_commit; // @[execution-units.scala:119:32]
wire _alu_exe_unit_2_io_iresp_bits_uop_ldst_is_rs1; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_2_io_iresp_bits_uop_ldst; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_2_io_iresp_bits_uop_lrs1; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_2_io_iresp_bits_uop_lrs2; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_2_io_iresp_bits_uop_lrs3; // @[execution-units.scala:119:32]
wire _alu_exe_unit_2_io_iresp_bits_uop_ldst_val; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_2_io_iresp_bits_uop_dst_rtype; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_2_io_iresp_bits_uop_lrs1_rtype; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_2_io_iresp_bits_uop_lrs2_rtype; // @[execution-units.scala:119:32]
wire _alu_exe_unit_2_io_iresp_bits_uop_frs3_en; // @[execution-units.scala:119:32]
wire _alu_exe_unit_2_io_iresp_bits_uop_fp_val; // @[execution-units.scala:119:32]
wire _alu_exe_unit_2_io_iresp_bits_uop_fp_single; // @[execution-units.scala:119:32]
wire _alu_exe_unit_2_io_iresp_bits_uop_xcpt_pf_if; // @[execution-units.scala:119:32]
wire _alu_exe_unit_2_io_iresp_bits_uop_xcpt_ae_if; // @[execution-units.scala:119:32]
wire _alu_exe_unit_2_io_iresp_bits_uop_xcpt_ma_if; // @[execution-units.scala:119:32]
wire _alu_exe_unit_2_io_iresp_bits_uop_bp_debug_if; // @[execution-units.scala:119:32]
wire _alu_exe_unit_2_io_iresp_bits_uop_bp_xcpt_if; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_2_io_iresp_bits_uop_debug_fsrc; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_2_io_iresp_bits_uop_debug_tsrc; // @[execution-units.scala:119:32]
wire [64:0] _alu_exe_unit_2_io_iresp_bits_data; // @[execution-units.scala:119:32]
wire [64:0] _alu_exe_unit_2_io_bypass_0_bits_data; // @[execution-units.scala:119:32]
wire [64:0] _alu_exe_unit_2_io_bypass_1_bits_data; // @[execution-units.scala:119:32]
wire [64:0] _alu_exe_unit_2_io_bypass_2_bits_data; // @[execution-units.scala:119:32]
wire [6:0] _alu_exe_unit_2_io_brinfo_uop_uopc; // @[execution-units.scala:119:32]
wire [31:0] _alu_exe_unit_2_io_brinfo_uop_inst; // @[execution-units.scala:119:32]
wire [31:0] _alu_exe_unit_2_io_brinfo_uop_debug_inst; // @[execution-units.scala:119:32]
wire _alu_exe_unit_2_io_brinfo_uop_is_rvc; // @[execution-units.scala:119:32]
wire [39:0] _alu_exe_unit_2_io_brinfo_uop_debug_pc; // @[execution-units.scala:119:32]
wire [2:0] _alu_exe_unit_2_io_brinfo_uop_iq_type; // @[execution-units.scala:119:32]
wire [9:0] _alu_exe_unit_2_io_brinfo_uop_fu_code; // @[execution-units.scala:119:32]
wire [3:0] _alu_exe_unit_2_io_brinfo_uop_ctrl_br_type; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_2_io_brinfo_uop_ctrl_op1_sel; // @[execution-units.scala:119:32]
wire [2:0] _alu_exe_unit_2_io_brinfo_uop_ctrl_op2_sel; // @[execution-units.scala:119:32]
wire [2:0] _alu_exe_unit_2_io_brinfo_uop_ctrl_imm_sel; // @[execution-units.scala:119:32]
wire [4:0] _alu_exe_unit_2_io_brinfo_uop_ctrl_op_fcn; // @[execution-units.scala:119:32]
wire _alu_exe_unit_2_io_brinfo_uop_ctrl_fcn_dw; // @[execution-units.scala:119:32]
wire [2:0] _alu_exe_unit_2_io_brinfo_uop_ctrl_csr_cmd; // @[execution-units.scala:119:32]
wire _alu_exe_unit_2_io_brinfo_uop_ctrl_is_load; // @[execution-units.scala:119:32]
wire _alu_exe_unit_2_io_brinfo_uop_ctrl_is_sta; // @[execution-units.scala:119:32]
wire _alu_exe_unit_2_io_brinfo_uop_ctrl_is_std; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_2_io_brinfo_uop_iw_state; // @[execution-units.scala:119:32]
wire _alu_exe_unit_2_io_brinfo_uop_iw_p1_poisoned; // @[execution-units.scala:119:32]
wire _alu_exe_unit_2_io_brinfo_uop_iw_p2_poisoned; // @[execution-units.scala:119:32]
wire _alu_exe_unit_2_io_brinfo_uop_is_br; // @[execution-units.scala:119:32]
wire _alu_exe_unit_2_io_brinfo_uop_is_jalr; // @[execution-units.scala:119:32]
wire _alu_exe_unit_2_io_brinfo_uop_is_jal; // @[execution-units.scala:119:32]
wire _alu_exe_unit_2_io_brinfo_uop_is_sfb; // @[execution-units.scala:119:32]
wire [15:0] _alu_exe_unit_2_io_brinfo_uop_br_mask; // @[execution-units.scala:119:32]
wire [3:0] _alu_exe_unit_2_io_brinfo_uop_br_tag; // @[execution-units.scala:119:32]
wire [4:0] _alu_exe_unit_2_io_brinfo_uop_ftq_idx; // @[execution-units.scala:119:32]
wire _alu_exe_unit_2_io_brinfo_uop_edge_inst; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_2_io_brinfo_uop_pc_lob; // @[execution-units.scala:119:32]
wire _alu_exe_unit_2_io_brinfo_uop_taken; // @[execution-units.scala:119:32]
wire [19:0] _alu_exe_unit_2_io_brinfo_uop_imm_packed; // @[execution-units.scala:119:32]
wire [11:0] _alu_exe_unit_2_io_brinfo_uop_csr_addr; // @[execution-units.scala:119:32]
wire [6:0] _alu_exe_unit_2_io_brinfo_uop_rob_idx; // @[execution-units.scala:119:32]
wire [4:0] _alu_exe_unit_2_io_brinfo_uop_ldq_idx; // @[execution-units.scala:119:32]
wire [4:0] _alu_exe_unit_2_io_brinfo_uop_stq_idx; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_2_io_brinfo_uop_rxq_idx; // @[execution-units.scala:119:32]
wire [6:0] _alu_exe_unit_2_io_brinfo_uop_pdst; // @[execution-units.scala:119:32]
wire [6:0] _alu_exe_unit_2_io_brinfo_uop_prs1; // @[execution-units.scala:119:32]
wire [6:0] _alu_exe_unit_2_io_brinfo_uop_prs2; // @[execution-units.scala:119:32]
wire [6:0] _alu_exe_unit_2_io_brinfo_uop_prs3; // @[execution-units.scala:119:32]
wire [4:0] _alu_exe_unit_2_io_brinfo_uop_ppred; // @[execution-units.scala:119:32]
wire _alu_exe_unit_2_io_brinfo_uop_prs1_busy; // @[execution-units.scala:119:32]
wire _alu_exe_unit_2_io_brinfo_uop_prs2_busy; // @[execution-units.scala:119:32]
wire _alu_exe_unit_2_io_brinfo_uop_prs3_busy; // @[execution-units.scala:119:32]
wire _alu_exe_unit_2_io_brinfo_uop_ppred_busy; // @[execution-units.scala:119:32]
wire [6:0] _alu_exe_unit_2_io_brinfo_uop_stale_pdst; // @[execution-units.scala:119:32]
wire _alu_exe_unit_2_io_brinfo_uop_exception; // @[execution-units.scala:119:32]
wire [63:0] _alu_exe_unit_2_io_brinfo_uop_exc_cause; // @[execution-units.scala:119:32]
wire _alu_exe_unit_2_io_brinfo_uop_bypassable; // @[execution-units.scala:119:32]
wire [4:0] _alu_exe_unit_2_io_brinfo_uop_mem_cmd; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_2_io_brinfo_uop_mem_size; // @[execution-units.scala:119:32]
wire _alu_exe_unit_2_io_brinfo_uop_mem_signed; // @[execution-units.scala:119:32]
wire _alu_exe_unit_2_io_brinfo_uop_is_fence; // @[execution-units.scala:119:32]
wire _alu_exe_unit_2_io_brinfo_uop_is_fencei; // @[execution-units.scala:119:32]
wire _alu_exe_unit_2_io_brinfo_uop_is_amo; // @[execution-units.scala:119:32]
wire _alu_exe_unit_2_io_brinfo_uop_uses_ldq; // @[execution-units.scala:119:32]
wire _alu_exe_unit_2_io_brinfo_uop_uses_stq; // @[execution-units.scala:119:32]
wire _alu_exe_unit_2_io_brinfo_uop_is_sys_pc2epc; // @[execution-units.scala:119:32]
wire _alu_exe_unit_2_io_brinfo_uop_is_unique; // @[execution-units.scala:119:32]
wire _alu_exe_unit_2_io_brinfo_uop_flush_on_commit; // @[execution-units.scala:119:32]
wire _alu_exe_unit_2_io_brinfo_uop_ldst_is_rs1; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_2_io_brinfo_uop_ldst; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_2_io_brinfo_uop_lrs1; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_2_io_brinfo_uop_lrs2; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_2_io_brinfo_uop_lrs3; // @[execution-units.scala:119:32]
wire _alu_exe_unit_2_io_brinfo_uop_ldst_val; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_2_io_brinfo_uop_dst_rtype; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_2_io_brinfo_uop_lrs1_rtype; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_2_io_brinfo_uop_lrs2_rtype; // @[execution-units.scala:119:32]
wire _alu_exe_unit_2_io_brinfo_uop_frs3_en; // @[execution-units.scala:119:32]
wire _alu_exe_unit_2_io_brinfo_uop_fp_val; // @[execution-units.scala:119:32]
wire _alu_exe_unit_2_io_brinfo_uop_fp_single; // @[execution-units.scala:119:32]
wire _alu_exe_unit_2_io_brinfo_uop_xcpt_pf_if; // @[execution-units.scala:119:32]
wire _alu_exe_unit_2_io_brinfo_uop_xcpt_ae_if; // @[execution-units.scala:119:32]
wire _alu_exe_unit_2_io_brinfo_uop_xcpt_ma_if; // @[execution-units.scala:119:32]
wire _alu_exe_unit_2_io_brinfo_uop_bp_debug_if; // @[execution-units.scala:119:32]
wire _alu_exe_unit_2_io_brinfo_uop_bp_xcpt_if; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_2_io_brinfo_uop_debug_fsrc; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_2_io_brinfo_uop_debug_tsrc; // @[execution-units.scala:119:32]
wire _alu_exe_unit_2_io_brinfo_valid; // @[execution-units.scala:119:32]
wire _alu_exe_unit_2_io_brinfo_mispredict; // @[execution-units.scala:119:32]
wire _alu_exe_unit_2_io_brinfo_taken; // @[execution-units.scala:119:32]
wire [2:0] _alu_exe_unit_2_io_brinfo_cfi_type; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_2_io_brinfo_pc_sel; // @[execution-units.scala:119:32]
wire [20:0] _alu_exe_unit_2_io_brinfo_target_offset; // @[execution-units.scala:119:32]
wire [9:0] _alu_exe_unit_1_io_fu_types; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_iresp_valid; // @[execution-units.scala:119:32]
wire [6:0] _alu_exe_unit_1_io_iresp_bits_uop_uopc; // @[execution-units.scala:119:32]
wire [31:0] _alu_exe_unit_1_io_iresp_bits_uop_inst; // @[execution-units.scala:119:32]
wire [31:0] _alu_exe_unit_1_io_iresp_bits_uop_debug_inst; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_iresp_bits_uop_is_rvc; // @[execution-units.scala:119:32]
wire [39:0] _alu_exe_unit_1_io_iresp_bits_uop_debug_pc; // @[execution-units.scala:119:32]
wire [2:0] _alu_exe_unit_1_io_iresp_bits_uop_iq_type; // @[execution-units.scala:119:32]
wire [9:0] _alu_exe_unit_1_io_iresp_bits_uop_fu_code; // @[execution-units.scala:119:32]
wire [3:0] _alu_exe_unit_1_io_iresp_bits_uop_ctrl_br_type; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_1_io_iresp_bits_uop_ctrl_op1_sel; // @[execution-units.scala:119:32]
wire [2:0] _alu_exe_unit_1_io_iresp_bits_uop_ctrl_op2_sel; // @[execution-units.scala:119:32]
wire [2:0] _alu_exe_unit_1_io_iresp_bits_uop_ctrl_imm_sel; // @[execution-units.scala:119:32]
wire [4:0] _alu_exe_unit_1_io_iresp_bits_uop_ctrl_op_fcn; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_iresp_bits_uop_ctrl_fcn_dw; // @[execution-units.scala:119:32]
wire [2:0] _alu_exe_unit_1_io_iresp_bits_uop_ctrl_csr_cmd; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_iresp_bits_uop_ctrl_is_load; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_iresp_bits_uop_ctrl_is_sta; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_iresp_bits_uop_ctrl_is_std; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_1_io_iresp_bits_uop_iw_state; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_iresp_bits_uop_iw_p1_poisoned; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_iresp_bits_uop_iw_p2_poisoned; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_iresp_bits_uop_is_br; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_iresp_bits_uop_is_jalr; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_iresp_bits_uop_is_jal; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_iresp_bits_uop_is_sfb; // @[execution-units.scala:119:32]
wire [15:0] _alu_exe_unit_1_io_iresp_bits_uop_br_mask; // @[execution-units.scala:119:32]
wire [3:0] _alu_exe_unit_1_io_iresp_bits_uop_br_tag; // @[execution-units.scala:119:32]
wire [4:0] _alu_exe_unit_1_io_iresp_bits_uop_ftq_idx; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_iresp_bits_uop_edge_inst; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_1_io_iresp_bits_uop_pc_lob; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_iresp_bits_uop_taken; // @[execution-units.scala:119:32]
wire [19:0] _alu_exe_unit_1_io_iresp_bits_uop_imm_packed; // @[execution-units.scala:119:32]
wire [11:0] _alu_exe_unit_1_io_iresp_bits_uop_csr_addr; // @[execution-units.scala:119:32]
wire [6:0] _alu_exe_unit_1_io_iresp_bits_uop_rob_idx; // @[execution-units.scala:119:32]
wire [4:0] _alu_exe_unit_1_io_iresp_bits_uop_ldq_idx; // @[execution-units.scala:119:32]
wire [4:0] _alu_exe_unit_1_io_iresp_bits_uop_stq_idx; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_1_io_iresp_bits_uop_rxq_idx; // @[execution-units.scala:119:32]
wire [6:0] _alu_exe_unit_1_io_iresp_bits_uop_pdst; // @[execution-units.scala:119:32]
wire [6:0] _alu_exe_unit_1_io_iresp_bits_uop_prs1; // @[execution-units.scala:119:32]
wire [6:0] _alu_exe_unit_1_io_iresp_bits_uop_prs2; // @[execution-units.scala:119:32]
wire [6:0] _alu_exe_unit_1_io_iresp_bits_uop_prs3; // @[execution-units.scala:119:32]
wire [4:0] _alu_exe_unit_1_io_iresp_bits_uop_ppred; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_iresp_bits_uop_prs1_busy; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_iresp_bits_uop_prs2_busy; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_iresp_bits_uop_prs3_busy; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_iresp_bits_uop_ppred_busy; // @[execution-units.scala:119:32]
wire [6:0] _alu_exe_unit_1_io_iresp_bits_uop_stale_pdst; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_iresp_bits_uop_exception; // @[execution-units.scala:119:32]
wire [63:0] _alu_exe_unit_1_io_iresp_bits_uop_exc_cause; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_iresp_bits_uop_bypassable; // @[execution-units.scala:119:32]
wire [4:0] _alu_exe_unit_1_io_iresp_bits_uop_mem_cmd; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_1_io_iresp_bits_uop_mem_size; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_iresp_bits_uop_mem_signed; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_iresp_bits_uop_is_fence; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_iresp_bits_uop_is_fencei; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_iresp_bits_uop_is_amo; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_iresp_bits_uop_uses_ldq; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_iresp_bits_uop_uses_stq; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_iresp_bits_uop_is_sys_pc2epc; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_iresp_bits_uop_is_unique; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_iresp_bits_uop_flush_on_commit; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_iresp_bits_uop_ldst_is_rs1; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_1_io_iresp_bits_uop_ldst; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_1_io_iresp_bits_uop_lrs1; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_1_io_iresp_bits_uop_lrs2; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_1_io_iresp_bits_uop_lrs3; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_iresp_bits_uop_ldst_val; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_1_io_iresp_bits_uop_dst_rtype; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_1_io_iresp_bits_uop_lrs1_rtype; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_1_io_iresp_bits_uop_lrs2_rtype; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_iresp_bits_uop_frs3_en; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_iresp_bits_uop_fp_val; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_iresp_bits_uop_fp_single; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_iresp_bits_uop_xcpt_pf_if; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_iresp_bits_uop_xcpt_ae_if; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_iresp_bits_uop_xcpt_ma_if; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_iresp_bits_uop_bp_debug_if; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_iresp_bits_uop_bp_xcpt_if; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_1_io_iresp_bits_uop_debug_fsrc; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_1_io_iresp_bits_uop_debug_tsrc; // @[execution-units.scala:119:32]
wire [64:0] _alu_exe_unit_1_io_iresp_bits_data; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_ll_fresp_valid; // @[execution-units.scala:119:32]
wire [6:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_uopc; // @[execution-units.scala:119:32]
wire [31:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_inst; // @[execution-units.scala:119:32]
wire [31:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_debug_inst; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_ll_fresp_bits_uop_is_rvc; // @[execution-units.scala:119:32]
wire [39:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_debug_pc; // @[execution-units.scala:119:32]
wire [2:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_iq_type; // @[execution-units.scala:119:32]
wire [9:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_fu_code; // @[execution-units.scala:119:32]
wire [3:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_ctrl_br_type; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_ctrl_op1_sel; // @[execution-units.scala:119:32]
wire [2:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_ctrl_op2_sel; // @[execution-units.scala:119:32]
wire [2:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_ctrl_imm_sel; // @[execution-units.scala:119:32]
wire [4:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_ctrl_op_fcn; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_ll_fresp_bits_uop_ctrl_fcn_dw; // @[execution-units.scala:119:32]
wire [2:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_ctrl_csr_cmd; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_ll_fresp_bits_uop_ctrl_is_load; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_ll_fresp_bits_uop_ctrl_is_sta; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_ll_fresp_bits_uop_ctrl_is_std; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_iw_state; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_ll_fresp_bits_uop_iw_p1_poisoned; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_ll_fresp_bits_uop_iw_p2_poisoned; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_ll_fresp_bits_uop_is_br; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_ll_fresp_bits_uop_is_jalr; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_ll_fresp_bits_uop_is_jal; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_ll_fresp_bits_uop_is_sfb; // @[execution-units.scala:119:32]
wire [15:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_br_mask; // @[execution-units.scala:119:32]
wire [3:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_br_tag; // @[execution-units.scala:119:32]
wire [4:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_ftq_idx; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_ll_fresp_bits_uop_edge_inst; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_pc_lob; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_ll_fresp_bits_uop_taken; // @[execution-units.scala:119:32]
wire [19:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_imm_packed; // @[execution-units.scala:119:32]
wire [11:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_csr_addr; // @[execution-units.scala:119:32]
wire [6:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_rob_idx; // @[execution-units.scala:119:32]
wire [4:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_ldq_idx; // @[execution-units.scala:119:32]
wire [4:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_stq_idx; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_rxq_idx; // @[execution-units.scala:119:32]
wire [6:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_pdst; // @[execution-units.scala:119:32]
wire [6:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_prs1; // @[execution-units.scala:119:32]
wire [6:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_prs2; // @[execution-units.scala:119:32]
wire [6:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_prs3; // @[execution-units.scala:119:32]
wire [4:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_ppred; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_ll_fresp_bits_uop_prs1_busy; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_ll_fresp_bits_uop_prs2_busy; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_ll_fresp_bits_uop_prs3_busy; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_ll_fresp_bits_uop_ppred_busy; // @[execution-units.scala:119:32]
wire [6:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_stale_pdst; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_ll_fresp_bits_uop_exception; // @[execution-units.scala:119:32]
wire [63:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_exc_cause; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_ll_fresp_bits_uop_bypassable; // @[execution-units.scala:119:32]
wire [4:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_mem_cmd; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_mem_size; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_ll_fresp_bits_uop_mem_signed; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_ll_fresp_bits_uop_is_fence; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_ll_fresp_bits_uop_is_fencei; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_ll_fresp_bits_uop_is_amo; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_ll_fresp_bits_uop_uses_ldq; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_ll_fresp_bits_uop_uses_stq; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_ll_fresp_bits_uop_is_sys_pc2epc; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_ll_fresp_bits_uop_is_unique; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_ll_fresp_bits_uop_flush_on_commit; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_ll_fresp_bits_uop_ldst_is_rs1; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_ldst; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_lrs1; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_lrs2; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_lrs3; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_ll_fresp_bits_uop_ldst_val; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_dst_rtype; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_lrs1_rtype; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_lrs2_rtype; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_ll_fresp_bits_uop_frs3_en; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_ll_fresp_bits_uop_fp_val; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_ll_fresp_bits_uop_fp_single; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_ll_fresp_bits_uop_xcpt_pf_if; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_ll_fresp_bits_uop_xcpt_ae_if; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_ll_fresp_bits_uop_xcpt_ma_if; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_ll_fresp_bits_uop_bp_debug_if; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_ll_fresp_bits_uop_bp_xcpt_if; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_debug_fsrc; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_debug_tsrc; // @[execution-units.scala:119:32]
wire [64:0] _alu_exe_unit_1_io_ll_fresp_bits_data; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_ll_fresp_bits_predicated; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_valid; // @[execution-units.scala:119:32]
wire [6:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_uopc; // @[execution-units.scala:119:32]
wire [31:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_inst; // @[execution-units.scala:119:32]
wire [31:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_debug_inst; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_is_rvc; // @[execution-units.scala:119:32]
wire [39:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_debug_pc; // @[execution-units.scala:119:32]
wire [2:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_iq_type; // @[execution-units.scala:119:32]
wire [9:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_fu_code; // @[execution-units.scala:119:32]
wire [3:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_ctrl_br_type; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_ctrl_op1_sel; // @[execution-units.scala:119:32]
wire [2:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_ctrl_op2_sel; // @[execution-units.scala:119:32]
wire [2:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_ctrl_imm_sel; // @[execution-units.scala:119:32]
wire [4:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_ctrl_op_fcn; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_ctrl_fcn_dw; // @[execution-units.scala:119:32]
wire [2:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_ctrl_csr_cmd; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_ctrl_is_load; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_ctrl_is_sta; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_ctrl_is_std; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_iw_state; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_iw_p1_poisoned; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_iw_p2_poisoned; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_is_br; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_is_jalr; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_is_jal; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_is_sfb; // @[execution-units.scala:119:32]
wire [15:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_br_mask; // @[execution-units.scala:119:32]
wire [3:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_br_tag; // @[execution-units.scala:119:32]
wire [4:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_ftq_idx; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_edge_inst; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_pc_lob; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_taken; // @[execution-units.scala:119:32]
wire [19:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_imm_packed; // @[execution-units.scala:119:32]
wire [11:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_csr_addr; // @[execution-units.scala:119:32]
wire [6:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_rob_idx; // @[execution-units.scala:119:32]
wire [4:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_ldq_idx; // @[execution-units.scala:119:32]
wire [4:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_stq_idx; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_rxq_idx; // @[execution-units.scala:119:32]
wire [6:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_pdst; // @[execution-units.scala:119:32]
wire [6:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_prs1; // @[execution-units.scala:119:32]
wire [6:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_prs2; // @[execution-units.scala:119:32]
wire [6:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_prs3; // @[execution-units.scala:119:32]
wire [4:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_ppred; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_prs1_busy; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_prs2_busy; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_prs3_busy; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_ppred_busy; // @[execution-units.scala:119:32]
wire [6:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_stale_pdst; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_exception; // @[execution-units.scala:119:32]
wire [63:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_exc_cause; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_bypassable; // @[execution-units.scala:119:32]
wire [4:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_mem_cmd; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_mem_size; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_mem_signed; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_is_fence; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_is_fencei; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_is_amo; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_uses_ldq; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_uses_stq; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_is_sys_pc2epc; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_is_unique; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_flush_on_commit; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_ldst_is_rs1; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_ldst; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_lrs1; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_lrs2; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_lrs3; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_ldst_val; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_dst_rtype; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_lrs1_rtype; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_lrs2_rtype; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_frs3_en; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_fp_val; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_fp_single; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_xcpt_pf_if; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_xcpt_ae_if; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_xcpt_ma_if; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_bp_debug_if; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_bp_xcpt_if; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_debug_fsrc; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_debug_tsrc; // @[execution-units.scala:119:32]
wire [4:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_flags; // @[execution-units.scala:119:32]
wire [64:0] _alu_exe_unit_1_io_bypass_0_bits_data; // @[execution-units.scala:119:32]
wire [6:0] _alu_exe_unit_1_io_brinfo_uop_uopc; // @[execution-units.scala:119:32]
wire [31:0] _alu_exe_unit_1_io_brinfo_uop_inst; // @[execution-units.scala:119:32]
wire [31:0] _alu_exe_unit_1_io_brinfo_uop_debug_inst; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_brinfo_uop_is_rvc; // @[execution-units.scala:119:32]
wire [39:0] _alu_exe_unit_1_io_brinfo_uop_debug_pc; // @[execution-units.scala:119:32]
wire [2:0] _alu_exe_unit_1_io_brinfo_uop_iq_type; // @[execution-units.scala:119:32]
wire [9:0] _alu_exe_unit_1_io_brinfo_uop_fu_code; // @[execution-units.scala:119:32]
wire [3:0] _alu_exe_unit_1_io_brinfo_uop_ctrl_br_type; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_1_io_brinfo_uop_ctrl_op1_sel; // @[execution-units.scala:119:32]
wire [2:0] _alu_exe_unit_1_io_brinfo_uop_ctrl_op2_sel; // @[execution-units.scala:119:32]
wire [2:0] _alu_exe_unit_1_io_brinfo_uop_ctrl_imm_sel; // @[execution-units.scala:119:32]
wire [4:0] _alu_exe_unit_1_io_brinfo_uop_ctrl_op_fcn; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_brinfo_uop_ctrl_fcn_dw; // @[execution-units.scala:119:32]
wire [2:0] _alu_exe_unit_1_io_brinfo_uop_ctrl_csr_cmd; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_brinfo_uop_ctrl_is_load; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_brinfo_uop_ctrl_is_sta; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_brinfo_uop_ctrl_is_std; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_1_io_brinfo_uop_iw_state; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_brinfo_uop_iw_p1_poisoned; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_brinfo_uop_iw_p2_poisoned; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_brinfo_uop_is_br; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_brinfo_uop_is_jalr; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_brinfo_uop_is_jal; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_brinfo_uop_is_sfb; // @[execution-units.scala:119:32]
wire [15:0] _alu_exe_unit_1_io_brinfo_uop_br_mask; // @[execution-units.scala:119:32]
wire [3:0] _alu_exe_unit_1_io_brinfo_uop_br_tag; // @[execution-units.scala:119:32]
wire [4:0] _alu_exe_unit_1_io_brinfo_uop_ftq_idx; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_brinfo_uop_edge_inst; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_1_io_brinfo_uop_pc_lob; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_brinfo_uop_taken; // @[execution-units.scala:119:32]
wire [19:0] _alu_exe_unit_1_io_brinfo_uop_imm_packed; // @[execution-units.scala:119:32]
wire [11:0] _alu_exe_unit_1_io_brinfo_uop_csr_addr; // @[execution-units.scala:119:32]
wire [6:0] _alu_exe_unit_1_io_brinfo_uop_rob_idx; // @[execution-units.scala:119:32]
wire [4:0] _alu_exe_unit_1_io_brinfo_uop_ldq_idx; // @[execution-units.scala:119:32]
wire [4:0] _alu_exe_unit_1_io_brinfo_uop_stq_idx; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_1_io_brinfo_uop_rxq_idx; // @[execution-units.scala:119:32]
wire [6:0] _alu_exe_unit_1_io_brinfo_uop_pdst; // @[execution-units.scala:119:32]
wire [6:0] _alu_exe_unit_1_io_brinfo_uop_prs1; // @[execution-units.scala:119:32]
wire [6:0] _alu_exe_unit_1_io_brinfo_uop_prs2; // @[execution-units.scala:119:32]
wire [6:0] _alu_exe_unit_1_io_brinfo_uop_prs3; // @[execution-units.scala:119:32]
wire [4:0] _alu_exe_unit_1_io_brinfo_uop_ppred; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_brinfo_uop_prs1_busy; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_brinfo_uop_prs2_busy; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_brinfo_uop_prs3_busy; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_brinfo_uop_ppred_busy; // @[execution-units.scala:119:32]
wire [6:0] _alu_exe_unit_1_io_brinfo_uop_stale_pdst; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_brinfo_uop_exception; // @[execution-units.scala:119:32]
wire [63:0] _alu_exe_unit_1_io_brinfo_uop_exc_cause; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_brinfo_uop_bypassable; // @[execution-units.scala:119:32]
wire [4:0] _alu_exe_unit_1_io_brinfo_uop_mem_cmd; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_1_io_brinfo_uop_mem_size; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_brinfo_uop_mem_signed; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_brinfo_uop_is_fence; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_brinfo_uop_is_fencei; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_brinfo_uop_is_amo; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_brinfo_uop_uses_ldq; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_brinfo_uop_uses_stq; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_brinfo_uop_is_sys_pc2epc; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_brinfo_uop_is_unique; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_brinfo_uop_flush_on_commit; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_brinfo_uop_ldst_is_rs1; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_1_io_brinfo_uop_ldst; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_1_io_brinfo_uop_lrs1; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_1_io_brinfo_uop_lrs2; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_1_io_brinfo_uop_lrs3; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_brinfo_uop_ldst_val; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_1_io_brinfo_uop_dst_rtype; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_1_io_brinfo_uop_lrs1_rtype; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_1_io_brinfo_uop_lrs2_rtype; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_brinfo_uop_frs3_en; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_brinfo_uop_fp_val; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_brinfo_uop_fp_single; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_brinfo_uop_xcpt_pf_if; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_brinfo_uop_xcpt_ae_if; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_brinfo_uop_xcpt_ma_if; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_brinfo_uop_bp_debug_if; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_brinfo_uop_bp_xcpt_if; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_1_io_brinfo_uop_debug_fsrc; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_1_io_brinfo_uop_debug_tsrc; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_brinfo_valid; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_brinfo_mispredict; // @[execution-units.scala:119:32]
wire _alu_exe_unit_1_io_brinfo_taken; // @[execution-units.scala:119:32]
wire [2:0] _alu_exe_unit_1_io_brinfo_cfi_type; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_1_io_brinfo_pc_sel; // @[execution-units.scala:119:32]
wire [20:0] _alu_exe_unit_1_io_brinfo_target_offset; // @[execution-units.scala:119:32]
wire [9:0] _alu_exe_unit_io_fu_types; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_iresp_valid; // @[execution-units.scala:119:32]
wire [6:0] _alu_exe_unit_io_iresp_bits_uop_uopc; // @[execution-units.scala:119:32]
wire [31:0] _alu_exe_unit_io_iresp_bits_uop_inst; // @[execution-units.scala:119:32]
wire [31:0] _alu_exe_unit_io_iresp_bits_uop_debug_inst; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_iresp_bits_uop_is_rvc; // @[execution-units.scala:119:32]
wire [39:0] _alu_exe_unit_io_iresp_bits_uop_debug_pc; // @[execution-units.scala:119:32]
wire [2:0] _alu_exe_unit_io_iresp_bits_uop_iq_type; // @[execution-units.scala:119:32]
wire [9:0] _alu_exe_unit_io_iresp_bits_uop_fu_code; // @[execution-units.scala:119:32]
wire [3:0] _alu_exe_unit_io_iresp_bits_uop_ctrl_br_type; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_io_iresp_bits_uop_ctrl_op1_sel; // @[execution-units.scala:119:32]
wire [2:0] _alu_exe_unit_io_iresp_bits_uop_ctrl_op2_sel; // @[execution-units.scala:119:32]
wire [2:0] _alu_exe_unit_io_iresp_bits_uop_ctrl_imm_sel; // @[execution-units.scala:119:32]
wire [4:0] _alu_exe_unit_io_iresp_bits_uop_ctrl_op_fcn; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_iresp_bits_uop_ctrl_fcn_dw; // @[execution-units.scala:119:32]
wire [2:0] _alu_exe_unit_io_iresp_bits_uop_ctrl_csr_cmd; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_iresp_bits_uop_ctrl_is_load; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_iresp_bits_uop_ctrl_is_sta; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_iresp_bits_uop_ctrl_is_std; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_io_iresp_bits_uop_iw_state; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_iresp_bits_uop_iw_p1_poisoned; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_iresp_bits_uop_iw_p2_poisoned; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_iresp_bits_uop_is_br; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_iresp_bits_uop_is_jalr; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_iresp_bits_uop_is_jal; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_iresp_bits_uop_is_sfb; // @[execution-units.scala:119:32]
wire [15:0] _alu_exe_unit_io_iresp_bits_uop_br_mask; // @[execution-units.scala:119:32]
wire [3:0] _alu_exe_unit_io_iresp_bits_uop_br_tag; // @[execution-units.scala:119:32]
wire [4:0] _alu_exe_unit_io_iresp_bits_uop_ftq_idx; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_iresp_bits_uop_edge_inst; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_io_iresp_bits_uop_pc_lob; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_iresp_bits_uop_taken; // @[execution-units.scala:119:32]
wire [19:0] _alu_exe_unit_io_iresp_bits_uop_imm_packed; // @[execution-units.scala:119:32]
wire [11:0] _alu_exe_unit_io_iresp_bits_uop_csr_addr; // @[execution-units.scala:119:32]
wire [6:0] _alu_exe_unit_io_iresp_bits_uop_rob_idx; // @[execution-units.scala:119:32]
wire [4:0] _alu_exe_unit_io_iresp_bits_uop_ldq_idx; // @[execution-units.scala:119:32]
wire [4:0] _alu_exe_unit_io_iresp_bits_uop_stq_idx; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_io_iresp_bits_uop_rxq_idx; // @[execution-units.scala:119:32]
wire [6:0] _alu_exe_unit_io_iresp_bits_uop_pdst; // @[execution-units.scala:119:32]
wire [6:0] _alu_exe_unit_io_iresp_bits_uop_prs1; // @[execution-units.scala:119:32]
wire [6:0] _alu_exe_unit_io_iresp_bits_uop_prs2; // @[execution-units.scala:119:32]
wire [6:0] _alu_exe_unit_io_iresp_bits_uop_prs3; // @[execution-units.scala:119:32]
wire [4:0] _alu_exe_unit_io_iresp_bits_uop_ppred; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_iresp_bits_uop_prs1_busy; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_iresp_bits_uop_prs2_busy; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_iresp_bits_uop_prs3_busy; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_iresp_bits_uop_ppred_busy; // @[execution-units.scala:119:32]
wire [6:0] _alu_exe_unit_io_iresp_bits_uop_stale_pdst; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_iresp_bits_uop_exception; // @[execution-units.scala:119:32]
wire [63:0] _alu_exe_unit_io_iresp_bits_uop_exc_cause; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_iresp_bits_uop_bypassable; // @[execution-units.scala:119:32]
wire [4:0] _alu_exe_unit_io_iresp_bits_uop_mem_cmd; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_io_iresp_bits_uop_mem_size; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_iresp_bits_uop_mem_signed; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_iresp_bits_uop_is_fence; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_iresp_bits_uop_is_fencei; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_iresp_bits_uop_is_amo; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_iresp_bits_uop_uses_ldq; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_iresp_bits_uop_uses_stq; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_iresp_bits_uop_is_sys_pc2epc; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_iresp_bits_uop_is_unique; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_iresp_bits_uop_flush_on_commit; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_iresp_bits_uop_ldst_is_rs1; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_io_iresp_bits_uop_ldst; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_io_iresp_bits_uop_lrs1; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_io_iresp_bits_uop_lrs2; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_io_iresp_bits_uop_lrs3; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_iresp_bits_uop_ldst_val; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_io_iresp_bits_uop_dst_rtype; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_io_iresp_bits_uop_lrs1_rtype; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_io_iresp_bits_uop_lrs2_rtype; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_iresp_bits_uop_frs3_en; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_iresp_bits_uop_fp_val; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_iresp_bits_uop_fp_single; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_iresp_bits_uop_xcpt_pf_if; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_iresp_bits_uop_xcpt_ae_if; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_iresp_bits_uop_xcpt_ma_if; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_iresp_bits_uop_bp_debug_if; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_iresp_bits_uop_bp_xcpt_if; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_io_iresp_bits_uop_debug_fsrc; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_io_iresp_bits_uop_debug_tsrc; // @[execution-units.scala:119:32]
wire [64:0] _alu_exe_unit_io_iresp_bits_data; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_0_valid; // @[execution-units.scala:119:32]
wire [6:0] _alu_exe_unit_io_bypass_0_bits_uop_uopc; // @[execution-units.scala:119:32]
wire [31:0] _alu_exe_unit_io_bypass_0_bits_uop_inst; // @[execution-units.scala:119:32]
wire [31:0] _alu_exe_unit_io_bypass_0_bits_uop_debug_inst; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_0_bits_uop_is_rvc; // @[execution-units.scala:119:32]
wire [39:0] _alu_exe_unit_io_bypass_0_bits_uop_debug_pc; // @[execution-units.scala:119:32]
wire [2:0] _alu_exe_unit_io_bypass_0_bits_uop_iq_type; // @[execution-units.scala:119:32]
wire [9:0] _alu_exe_unit_io_bypass_0_bits_uop_fu_code; // @[execution-units.scala:119:32]
wire [3:0] _alu_exe_unit_io_bypass_0_bits_uop_ctrl_br_type; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_io_bypass_0_bits_uop_ctrl_op1_sel; // @[execution-units.scala:119:32]
wire [2:0] _alu_exe_unit_io_bypass_0_bits_uop_ctrl_op2_sel; // @[execution-units.scala:119:32]
wire [2:0] _alu_exe_unit_io_bypass_0_bits_uop_ctrl_imm_sel; // @[execution-units.scala:119:32]
wire [4:0] _alu_exe_unit_io_bypass_0_bits_uop_ctrl_op_fcn; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_0_bits_uop_ctrl_fcn_dw; // @[execution-units.scala:119:32]
wire [2:0] _alu_exe_unit_io_bypass_0_bits_uop_ctrl_csr_cmd; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_0_bits_uop_ctrl_is_load; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_0_bits_uop_ctrl_is_sta; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_0_bits_uop_ctrl_is_std; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_io_bypass_0_bits_uop_iw_state; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_0_bits_uop_iw_p1_poisoned; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_0_bits_uop_iw_p2_poisoned; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_0_bits_uop_is_br; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_0_bits_uop_is_jalr; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_0_bits_uop_is_jal; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_0_bits_uop_is_sfb; // @[execution-units.scala:119:32]
wire [15:0] _alu_exe_unit_io_bypass_0_bits_uop_br_mask; // @[execution-units.scala:119:32]
wire [3:0] _alu_exe_unit_io_bypass_0_bits_uop_br_tag; // @[execution-units.scala:119:32]
wire [4:0] _alu_exe_unit_io_bypass_0_bits_uop_ftq_idx; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_0_bits_uop_edge_inst; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_io_bypass_0_bits_uop_pc_lob; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_0_bits_uop_taken; // @[execution-units.scala:119:32]
wire [19:0] _alu_exe_unit_io_bypass_0_bits_uop_imm_packed; // @[execution-units.scala:119:32]
wire [11:0] _alu_exe_unit_io_bypass_0_bits_uop_csr_addr; // @[execution-units.scala:119:32]
wire [6:0] _alu_exe_unit_io_bypass_0_bits_uop_rob_idx; // @[execution-units.scala:119:32]
wire [4:0] _alu_exe_unit_io_bypass_0_bits_uop_ldq_idx; // @[execution-units.scala:119:32]
wire [4:0] _alu_exe_unit_io_bypass_0_bits_uop_stq_idx; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_io_bypass_0_bits_uop_rxq_idx; // @[execution-units.scala:119:32]
wire [6:0] _alu_exe_unit_io_bypass_0_bits_uop_pdst; // @[execution-units.scala:119:32]
wire [6:0] _alu_exe_unit_io_bypass_0_bits_uop_prs1; // @[execution-units.scala:119:32]
wire [6:0] _alu_exe_unit_io_bypass_0_bits_uop_prs2; // @[execution-units.scala:119:32]
wire [6:0] _alu_exe_unit_io_bypass_0_bits_uop_prs3; // @[execution-units.scala:119:32]
wire [4:0] _alu_exe_unit_io_bypass_0_bits_uop_ppred; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_0_bits_uop_prs1_busy; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_0_bits_uop_prs2_busy; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_0_bits_uop_prs3_busy; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_0_bits_uop_ppred_busy; // @[execution-units.scala:119:32]
wire [6:0] _alu_exe_unit_io_bypass_0_bits_uop_stale_pdst; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_0_bits_uop_exception; // @[execution-units.scala:119:32]
wire [63:0] _alu_exe_unit_io_bypass_0_bits_uop_exc_cause; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_0_bits_uop_bypassable; // @[execution-units.scala:119:32]
wire [4:0] _alu_exe_unit_io_bypass_0_bits_uop_mem_cmd; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_io_bypass_0_bits_uop_mem_size; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_0_bits_uop_mem_signed; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_0_bits_uop_is_fence; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_0_bits_uop_is_fencei; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_0_bits_uop_is_amo; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_0_bits_uop_uses_ldq; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_0_bits_uop_uses_stq; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_0_bits_uop_is_sys_pc2epc; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_0_bits_uop_is_unique; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_0_bits_uop_flush_on_commit; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_0_bits_uop_ldst_is_rs1; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_io_bypass_0_bits_uop_ldst; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_io_bypass_0_bits_uop_lrs1; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_io_bypass_0_bits_uop_lrs2; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_io_bypass_0_bits_uop_lrs3; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_0_bits_uop_ldst_val; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_io_bypass_0_bits_uop_dst_rtype; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_io_bypass_0_bits_uop_lrs1_rtype; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_io_bypass_0_bits_uop_lrs2_rtype; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_0_bits_uop_frs3_en; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_0_bits_uop_fp_val; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_0_bits_uop_fp_single; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_0_bits_uop_xcpt_pf_if; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_0_bits_uop_xcpt_ae_if; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_0_bits_uop_xcpt_ma_if; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_0_bits_uop_bp_debug_if; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_bypass_0_bits_uop_bp_xcpt_if; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_io_bypass_0_bits_uop_debug_fsrc; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_io_bypass_0_bits_uop_debug_tsrc; // @[execution-units.scala:119:32]
wire [64:0] _alu_exe_unit_io_bypass_0_bits_data; // @[execution-units.scala:119:32]
wire [6:0] _alu_exe_unit_io_brinfo_uop_uopc; // @[execution-units.scala:119:32]
wire [31:0] _alu_exe_unit_io_brinfo_uop_inst; // @[execution-units.scala:119:32]
wire [31:0] _alu_exe_unit_io_brinfo_uop_debug_inst; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_brinfo_uop_is_rvc; // @[execution-units.scala:119:32]
wire [39:0] _alu_exe_unit_io_brinfo_uop_debug_pc; // @[execution-units.scala:119:32]
wire [2:0] _alu_exe_unit_io_brinfo_uop_iq_type; // @[execution-units.scala:119:32]
wire [9:0] _alu_exe_unit_io_brinfo_uop_fu_code; // @[execution-units.scala:119:32]
wire [3:0] _alu_exe_unit_io_brinfo_uop_ctrl_br_type; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_io_brinfo_uop_ctrl_op1_sel; // @[execution-units.scala:119:32]
wire [2:0] _alu_exe_unit_io_brinfo_uop_ctrl_op2_sel; // @[execution-units.scala:119:32]
wire [2:0] _alu_exe_unit_io_brinfo_uop_ctrl_imm_sel; // @[execution-units.scala:119:32]
wire [4:0] _alu_exe_unit_io_brinfo_uop_ctrl_op_fcn; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_brinfo_uop_ctrl_fcn_dw; // @[execution-units.scala:119:32]
wire [2:0] _alu_exe_unit_io_brinfo_uop_ctrl_csr_cmd; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_brinfo_uop_ctrl_is_load; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_brinfo_uop_ctrl_is_sta; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_brinfo_uop_ctrl_is_std; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_io_brinfo_uop_iw_state; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_brinfo_uop_iw_p1_poisoned; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_brinfo_uop_iw_p2_poisoned; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_brinfo_uop_is_br; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_brinfo_uop_is_jalr; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_brinfo_uop_is_jal; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_brinfo_uop_is_sfb; // @[execution-units.scala:119:32]
wire [15:0] _alu_exe_unit_io_brinfo_uop_br_mask; // @[execution-units.scala:119:32]
wire [3:0] _alu_exe_unit_io_brinfo_uop_br_tag; // @[execution-units.scala:119:32]
wire [4:0] _alu_exe_unit_io_brinfo_uop_ftq_idx; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_brinfo_uop_edge_inst; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_io_brinfo_uop_pc_lob; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_brinfo_uop_taken; // @[execution-units.scala:119:32]
wire [19:0] _alu_exe_unit_io_brinfo_uop_imm_packed; // @[execution-units.scala:119:32]
wire [11:0] _alu_exe_unit_io_brinfo_uop_csr_addr; // @[execution-units.scala:119:32]
wire [6:0] _alu_exe_unit_io_brinfo_uop_rob_idx; // @[execution-units.scala:119:32]
wire [4:0] _alu_exe_unit_io_brinfo_uop_ldq_idx; // @[execution-units.scala:119:32]
wire [4:0] _alu_exe_unit_io_brinfo_uop_stq_idx; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_io_brinfo_uop_rxq_idx; // @[execution-units.scala:119:32]
wire [6:0] _alu_exe_unit_io_brinfo_uop_pdst; // @[execution-units.scala:119:32]
wire [6:0] _alu_exe_unit_io_brinfo_uop_prs1; // @[execution-units.scala:119:32]
wire [6:0] _alu_exe_unit_io_brinfo_uop_prs2; // @[execution-units.scala:119:32]
wire [6:0] _alu_exe_unit_io_brinfo_uop_prs3; // @[execution-units.scala:119:32]
wire [4:0] _alu_exe_unit_io_brinfo_uop_ppred; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_brinfo_uop_prs1_busy; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_brinfo_uop_prs2_busy; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_brinfo_uop_prs3_busy; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_brinfo_uop_ppred_busy; // @[execution-units.scala:119:32]
wire [6:0] _alu_exe_unit_io_brinfo_uop_stale_pdst; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_brinfo_uop_exception; // @[execution-units.scala:119:32]
wire [63:0] _alu_exe_unit_io_brinfo_uop_exc_cause; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_brinfo_uop_bypassable; // @[execution-units.scala:119:32]
wire [4:0] _alu_exe_unit_io_brinfo_uop_mem_cmd; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_io_brinfo_uop_mem_size; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_brinfo_uop_mem_signed; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_brinfo_uop_is_fence; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_brinfo_uop_is_fencei; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_brinfo_uop_is_amo; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_brinfo_uop_uses_ldq; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_brinfo_uop_uses_stq; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_brinfo_uop_is_sys_pc2epc; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_brinfo_uop_is_unique; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_brinfo_uop_flush_on_commit; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_brinfo_uop_ldst_is_rs1; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_io_brinfo_uop_ldst; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_io_brinfo_uop_lrs1; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_io_brinfo_uop_lrs2; // @[execution-units.scala:119:32]
wire [5:0] _alu_exe_unit_io_brinfo_uop_lrs3; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_brinfo_uop_ldst_val; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_io_brinfo_uop_dst_rtype; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_io_brinfo_uop_lrs1_rtype; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_io_brinfo_uop_lrs2_rtype; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_brinfo_uop_frs3_en; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_brinfo_uop_fp_val; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_brinfo_uop_fp_single; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_brinfo_uop_xcpt_pf_if; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_brinfo_uop_xcpt_ae_if; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_brinfo_uop_xcpt_ma_if; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_brinfo_uop_bp_debug_if; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_brinfo_uop_bp_xcpt_if; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_io_brinfo_uop_debug_fsrc; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_io_brinfo_uop_debug_tsrc; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_brinfo_valid; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_brinfo_mispredict; // @[execution-units.scala:119:32]
wire _alu_exe_unit_io_brinfo_taken; // @[execution-units.scala:119:32]
wire [2:0] _alu_exe_unit_io_brinfo_cfi_type; // @[execution-units.scala:119:32]
wire [1:0] _alu_exe_unit_io_brinfo_pc_sel; // @[execution-units.scala:119:32]
wire [39:0] _alu_exe_unit_io_brinfo_jalr_target; // @[execution-units.scala:119:32]
wire [20:0] _alu_exe_unit_io_brinfo_target_offset; // @[execution-units.scala:119:32]
wire _memExeUnit_io_ll_iresp_valid; // @[execution-units.scala:108:30]
wire [6:0] _memExeUnit_io_ll_iresp_bits_uop_uopc; // @[execution-units.scala:108:30]
wire [31:0] _memExeUnit_io_ll_iresp_bits_uop_inst; // @[execution-units.scala:108:30]
wire [31:0] _memExeUnit_io_ll_iresp_bits_uop_debug_inst; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_iresp_bits_uop_is_rvc; // @[execution-units.scala:108:30]
wire [39:0] _memExeUnit_io_ll_iresp_bits_uop_debug_pc; // @[execution-units.scala:108:30]
wire [2:0] _memExeUnit_io_ll_iresp_bits_uop_iq_type; // @[execution-units.scala:108:30]
wire [9:0] _memExeUnit_io_ll_iresp_bits_uop_fu_code; // @[execution-units.scala:108:30]
wire [3:0] _memExeUnit_io_ll_iresp_bits_uop_ctrl_br_type; // @[execution-units.scala:108:30]
wire [1:0] _memExeUnit_io_ll_iresp_bits_uop_ctrl_op1_sel; // @[execution-units.scala:108:30]
wire [2:0] _memExeUnit_io_ll_iresp_bits_uop_ctrl_op2_sel; // @[execution-units.scala:108:30]
wire [2:0] _memExeUnit_io_ll_iresp_bits_uop_ctrl_imm_sel; // @[execution-units.scala:108:30]
wire [4:0] _memExeUnit_io_ll_iresp_bits_uop_ctrl_op_fcn; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_iresp_bits_uop_ctrl_fcn_dw; // @[execution-units.scala:108:30]
wire [2:0] _memExeUnit_io_ll_iresp_bits_uop_ctrl_csr_cmd; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_iresp_bits_uop_ctrl_is_load; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_iresp_bits_uop_ctrl_is_sta; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_iresp_bits_uop_ctrl_is_std; // @[execution-units.scala:108:30]
wire [1:0] _memExeUnit_io_ll_iresp_bits_uop_iw_state; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_iresp_bits_uop_iw_p1_poisoned; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_iresp_bits_uop_iw_p2_poisoned; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_iresp_bits_uop_is_br; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_iresp_bits_uop_is_jalr; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_iresp_bits_uop_is_jal; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_iresp_bits_uop_is_sfb; // @[execution-units.scala:108:30]
wire [15:0] _memExeUnit_io_ll_iresp_bits_uop_br_mask; // @[execution-units.scala:108:30]
wire [3:0] _memExeUnit_io_ll_iresp_bits_uop_br_tag; // @[execution-units.scala:108:30]
wire [4:0] _memExeUnit_io_ll_iresp_bits_uop_ftq_idx; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_iresp_bits_uop_edge_inst; // @[execution-units.scala:108:30]
wire [5:0] _memExeUnit_io_ll_iresp_bits_uop_pc_lob; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_iresp_bits_uop_taken; // @[execution-units.scala:108:30]
wire [19:0] _memExeUnit_io_ll_iresp_bits_uop_imm_packed; // @[execution-units.scala:108:30]
wire [11:0] _memExeUnit_io_ll_iresp_bits_uop_csr_addr; // @[execution-units.scala:108:30]
wire [6:0] _memExeUnit_io_ll_iresp_bits_uop_rob_idx; // @[execution-units.scala:108:30]
wire [4:0] _memExeUnit_io_ll_iresp_bits_uop_ldq_idx; // @[execution-units.scala:108:30]
wire [4:0] _memExeUnit_io_ll_iresp_bits_uop_stq_idx; // @[execution-units.scala:108:30]
wire [1:0] _memExeUnit_io_ll_iresp_bits_uop_rxq_idx; // @[execution-units.scala:108:30]
wire [6:0] _memExeUnit_io_ll_iresp_bits_uop_pdst; // @[execution-units.scala:108:30]
wire [6:0] _memExeUnit_io_ll_iresp_bits_uop_prs1; // @[execution-units.scala:108:30]
wire [6:0] _memExeUnit_io_ll_iresp_bits_uop_prs2; // @[execution-units.scala:108:30]
wire [6:0] _memExeUnit_io_ll_iresp_bits_uop_prs3; // @[execution-units.scala:108:30]
wire [4:0] _memExeUnit_io_ll_iresp_bits_uop_ppred; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_iresp_bits_uop_prs1_busy; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_iresp_bits_uop_prs2_busy; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_iresp_bits_uop_prs3_busy; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_iresp_bits_uop_ppred_busy; // @[execution-units.scala:108:30]
wire [6:0] _memExeUnit_io_ll_iresp_bits_uop_stale_pdst; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_iresp_bits_uop_exception; // @[execution-units.scala:108:30]
wire [63:0] _memExeUnit_io_ll_iresp_bits_uop_exc_cause; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_iresp_bits_uop_bypassable; // @[execution-units.scala:108:30]
wire [4:0] _memExeUnit_io_ll_iresp_bits_uop_mem_cmd; // @[execution-units.scala:108:30]
wire [1:0] _memExeUnit_io_ll_iresp_bits_uop_mem_size; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_iresp_bits_uop_mem_signed; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_iresp_bits_uop_is_fence; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_iresp_bits_uop_is_fencei; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_iresp_bits_uop_is_amo; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_iresp_bits_uop_uses_ldq; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_iresp_bits_uop_uses_stq; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_iresp_bits_uop_is_sys_pc2epc; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_iresp_bits_uop_is_unique; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_iresp_bits_uop_flush_on_commit; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_iresp_bits_uop_ldst_is_rs1; // @[execution-units.scala:108:30]
wire [5:0] _memExeUnit_io_ll_iresp_bits_uop_ldst; // @[execution-units.scala:108:30]
wire [5:0] _memExeUnit_io_ll_iresp_bits_uop_lrs1; // @[execution-units.scala:108:30]
wire [5:0] _memExeUnit_io_ll_iresp_bits_uop_lrs2; // @[execution-units.scala:108:30]
wire [5:0] _memExeUnit_io_ll_iresp_bits_uop_lrs3; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_iresp_bits_uop_ldst_val; // @[execution-units.scala:108:30]
wire [1:0] _memExeUnit_io_ll_iresp_bits_uop_dst_rtype; // @[execution-units.scala:108:30]
wire [1:0] _memExeUnit_io_ll_iresp_bits_uop_lrs1_rtype; // @[execution-units.scala:108:30]
wire [1:0] _memExeUnit_io_ll_iresp_bits_uop_lrs2_rtype; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_iresp_bits_uop_frs3_en; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_iresp_bits_uop_fp_val; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_iresp_bits_uop_fp_single; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_iresp_bits_uop_xcpt_pf_if; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_iresp_bits_uop_xcpt_ae_if; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_iresp_bits_uop_xcpt_ma_if; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_iresp_bits_uop_bp_debug_if; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_iresp_bits_uop_bp_xcpt_if; // @[execution-units.scala:108:30]
wire [1:0] _memExeUnit_io_ll_iresp_bits_uop_debug_fsrc; // @[execution-units.scala:108:30]
wire [1:0] _memExeUnit_io_ll_iresp_bits_uop_debug_tsrc; // @[execution-units.scala:108:30]
wire [64:0] _memExeUnit_io_ll_iresp_bits_data; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_fresp_valid; // @[execution-units.scala:108:30]
wire [6:0] _memExeUnit_io_ll_fresp_bits_uop_uopc; // @[execution-units.scala:108:30]
wire [31:0] _memExeUnit_io_ll_fresp_bits_uop_inst; // @[execution-units.scala:108:30]
wire [31:0] _memExeUnit_io_ll_fresp_bits_uop_debug_inst; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_fresp_bits_uop_is_rvc; // @[execution-units.scala:108:30]
wire [39:0] _memExeUnit_io_ll_fresp_bits_uop_debug_pc; // @[execution-units.scala:108:30]
wire [2:0] _memExeUnit_io_ll_fresp_bits_uop_iq_type; // @[execution-units.scala:108:30]
wire [9:0] _memExeUnit_io_ll_fresp_bits_uop_fu_code; // @[execution-units.scala:108:30]
wire [3:0] _memExeUnit_io_ll_fresp_bits_uop_ctrl_br_type; // @[execution-units.scala:108:30]
wire [1:0] _memExeUnit_io_ll_fresp_bits_uop_ctrl_op1_sel; // @[execution-units.scala:108:30]
wire [2:0] _memExeUnit_io_ll_fresp_bits_uop_ctrl_op2_sel; // @[execution-units.scala:108:30]
wire [2:0] _memExeUnit_io_ll_fresp_bits_uop_ctrl_imm_sel; // @[execution-units.scala:108:30]
wire [4:0] _memExeUnit_io_ll_fresp_bits_uop_ctrl_op_fcn; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_fresp_bits_uop_ctrl_fcn_dw; // @[execution-units.scala:108:30]
wire [2:0] _memExeUnit_io_ll_fresp_bits_uop_ctrl_csr_cmd; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_fresp_bits_uop_ctrl_is_load; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_fresp_bits_uop_ctrl_is_sta; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_fresp_bits_uop_ctrl_is_std; // @[execution-units.scala:108:30]
wire [1:0] _memExeUnit_io_ll_fresp_bits_uop_iw_state; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_fresp_bits_uop_iw_p1_poisoned; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_fresp_bits_uop_iw_p2_poisoned; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_fresp_bits_uop_is_br; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_fresp_bits_uop_is_jalr; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_fresp_bits_uop_is_jal; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_fresp_bits_uop_is_sfb; // @[execution-units.scala:108:30]
wire [15:0] _memExeUnit_io_ll_fresp_bits_uop_br_mask; // @[execution-units.scala:108:30]
wire [3:0] _memExeUnit_io_ll_fresp_bits_uop_br_tag; // @[execution-units.scala:108:30]
wire [4:0] _memExeUnit_io_ll_fresp_bits_uop_ftq_idx; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_fresp_bits_uop_edge_inst; // @[execution-units.scala:108:30]
wire [5:0] _memExeUnit_io_ll_fresp_bits_uop_pc_lob; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_fresp_bits_uop_taken; // @[execution-units.scala:108:30]
wire [19:0] _memExeUnit_io_ll_fresp_bits_uop_imm_packed; // @[execution-units.scala:108:30]
wire [11:0] _memExeUnit_io_ll_fresp_bits_uop_csr_addr; // @[execution-units.scala:108:30]
wire [6:0] _memExeUnit_io_ll_fresp_bits_uop_rob_idx; // @[execution-units.scala:108:30]
wire [4:0] _memExeUnit_io_ll_fresp_bits_uop_ldq_idx; // @[execution-units.scala:108:30]
wire [4:0] _memExeUnit_io_ll_fresp_bits_uop_stq_idx; // @[execution-units.scala:108:30]
wire [1:0] _memExeUnit_io_ll_fresp_bits_uop_rxq_idx; // @[execution-units.scala:108:30]
wire [6:0] _memExeUnit_io_ll_fresp_bits_uop_pdst; // @[execution-units.scala:108:30]
wire [6:0] _memExeUnit_io_ll_fresp_bits_uop_prs1; // @[execution-units.scala:108:30]
wire [6:0] _memExeUnit_io_ll_fresp_bits_uop_prs2; // @[execution-units.scala:108:30]
wire [6:0] _memExeUnit_io_ll_fresp_bits_uop_prs3; // @[execution-units.scala:108:30]
wire [4:0] _memExeUnit_io_ll_fresp_bits_uop_ppred; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_fresp_bits_uop_prs1_busy; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_fresp_bits_uop_prs2_busy; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_fresp_bits_uop_prs3_busy; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_fresp_bits_uop_ppred_busy; // @[execution-units.scala:108:30]
wire [6:0] _memExeUnit_io_ll_fresp_bits_uop_stale_pdst; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_fresp_bits_uop_exception; // @[execution-units.scala:108:30]
wire [63:0] _memExeUnit_io_ll_fresp_bits_uop_exc_cause; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_fresp_bits_uop_bypassable; // @[execution-units.scala:108:30]
wire [4:0] _memExeUnit_io_ll_fresp_bits_uop_mem_cmd; // @[execution-units.scala:108:30]
wire [1:0] _memExeUnit_io_ll_fresp_bits_uop_mem_size; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_fresp_bits_uop_mem_signed; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_fresp_bits_uop_is_fence; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_fresp_bits_uop_is_fencei; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_fresp_bits_uop_is_amo; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_fresp_bits_uop_uses_ldq; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_fresp_bits_uop_uses_stq; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_fresp_bits_uop_is_sys_pc2epc; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_fresp_bits_uop_is_unique; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_fresp_bits_uop_flush_on_commit; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_fresp_bits_uop_ldst_is_rs1; // @[execution-units.scala:108:30]
wire [5:0] _memExeUnit_io_ll_fresp_bits_uop_ldst; // @[execution-units.scala:108:30]
wire [5:0] _memExeUnit_io_ll_fresp_bits_uop_lrs1; // @[execution-units.scala:108:30]
wire [5:0] _memExeUnit_io_ll_fresp_bits_uop_lrs2; // @[execution-units.scala:108:30]
wire [5:0] _memExeUnit_io_ll_fresp_bits_uop_lrs3; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_fresp_bits_uop_ldst_val; // @[execution-units.scala:108:30]
wire [1:0] _memExeUnit_io_ll_fresp_bits_uop_dst_rtype; // @[execution-units.scala:108:30]
wire [1:0] _memExeUnit_io_ll_fresp_bits_uop_lrs1_rtype; // @[execution-units.scala:108:30]
wire [1:0] _memExeUnit_io_ll_fresp_bits_uop_lrs2_rtype; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_fresp_bits_uop_frs3_en; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_fresp_bits_uop_fp_val; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_fresp_bits_uop_fp_single; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_fresp_bits_uop_xcpt_pf_if; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_fresp_bits_uop_xcpt_ae_if; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_fresp_bits_uop_xcpt_ma_if; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_fresp_bits_uop_bp_debug_if; // @[execution-units.scala:108:30]
wire _memExeUnit_io_ll_fresp_bits_uop_bp_xcpt_if; // @[execution-units.scala:108:30]
wire [1:0] _memExeUnit_io_ll_fresp_bits_uop_debug_fsrc; // @[execution-units.scala:108:30]
wire [1:0] _memExeUnit_io_ll_fresp_bits_uop_debug_tsrc; // @[execution-units.scala:108:30]
wire [64:0] _memExeUnit_io_ll_fresp_bits_data; // @[execution-units.scala:108:30]
wire io_hartid_0 = io_hartid; // @[core.scala:51:7]
wire io_interrupts_debug_0 = io_interrupts_debug; // @[core.scala:51:7]
wire io_interrupts_mtip_0 = io_interrupts_mtip; // @[core.scala:51:7]
wire io_interrupts_msip_0 = io_interrupts_msip; // @[core.scala:51:7]
wire io_interrupts_meip_0 = io_interrupts_meip; // @[core.scala:51:7]
wire io_interrupts_seip_0 = io_interrupts_seip; // @[core.scala:51:7]
wire io_ifu_fetchpacket_valid_0 = io_ifu_fetchpacket_valid; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_0_valid_0 = io_ifu_fetchpacket_bits_uops_0_valid; // @[core.scala:51:7]
wire [31:0] io_ifu_fetchpacket_bits_uops_0_bits_inst_0 = io_ifu_fetchpacket_bits_uops_0_bits_inst; // @[core.scala:51:7]
wire [31:0] io_ifu_fetchpacket_bits_uops_0_bits_debug_inst_0 = io_ifu_fetchpacket_bits_uops_0_bits_debug_inst; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_0_bits_is_rvc_0 = io_ifu_fetchpacket_bits_uops_0_bits_is_rvc; // @[core.scala:51:7]
wire [39:0] io_ifu_fetchpacket_bits_uops_0_bits_debug_pc_0 = io_ifu_fetchpacket_bits_uops_0_bits_debug_pc; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_0_bits_is_sfb_0 = io_ifu_fetchpacket_bits_uops_0_bits_is_sfb; // @[core.scala:51:7]
wire [4:0] io_ifu_fetchpacket_bits_uops_0_bits_ftq_idx_0 = io_ifu_fetchpacket_bits_uops_0_bits_ftq_idx; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_0_bits_edge_inst_0 = io_ifu_fetchpacket_bits_uops_0_bits_edge_inst; // @[core.scala:51:7]
wire [5:0] io_ifu_fetchpacket_bits_uops_0_bits_pc_lob_0 = io_ifu_fetchpacket_bits_uops_0_bits_pc_lob; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_0_bits_taken_0 = io_ifu_fetchpacket_bits_uops_0_bits_taken; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_0_bits_xcpt_pf_if_0 = io_ifu_fetchpacket_bits_uops_0_bits_xcpt_pf_if; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_0_bits_xcpt_ae_if_0 = io_ifu_fetchpacket_bits_uops_0_bits_xcpt_ae_if; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_0_bits_bp_debug_if_0 = io_ifu_fetchpacket_bits_uops_0_bits_bp_debug_if; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_0_bits_bp_xcpt_if_0 = io_ifu_fetchpacket_bits_uops_0_bits_bp_xcpt_if; // @[core.scala:51:7]
wire [1:0] io_ifu_fetchpacket_bits_uops_0_bits_debug_fsrc_0 = io_ifu_fetchpacket_bits_uops_0_bits_debug_fsrc; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_1_valid_0 = io_ifu_fetchpacket_bits_uops_1_valid; // @[core.scala:51:7]
wire [31:0] io_ifu_fetchpacket_bits_uops_1_bits_inst_0 = io_ifu_fetchpacket_bits_uops_1_bits_inst; // @[core.scala:51:7]
wire [31:0] io_ifu_fetchpacket_bits_uops_1_bits_debug_inst_0 = io_ifu_fetchpacket_bits_uops_1_bits_debug_inst; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_1_bits_is_rvc_0 = io_ifu_fetchpacket_bits_uops_1_bits_is_rvc; // @[core.scala:51:7]
wire [39:0] io_ifu_fetchpacket_bits_uops_1_bits_debug_pc_0 = io_ifu_fetchpacket_bits_uops_1_bits_debug_pc; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_1_bits_is_sfb_0 = io_ifu_fetchpacket_bits_uops_1_bits_is_sfb; // @[core.scala:51:7]
wire [4:0] io_ifu_fetchpacket_bits_uops_1_bits_ftq_idx_0 = io_ifu_fetchpacket_bits_uops_1_bits_ftq_idx; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_1_bits_edge_inst_0 = io_ifu_fetchpacket_bits_uops_1_bits_edge_inst; // @[core.scala:51:7]
wire [5:0] io_ifu_fetchpacket_bits_uops_1_bits_pc_lob_0 = io_ifu_fetchpacket_bits_uops_1_bits_pc_lob; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_1_bits_taken_0 = io_ifu_fetchpacket_bits_uops_1_bits_taken; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_1_bits_xcpt_pf_if_0 = io_ifu_fetchpacket_bits_uops_1_bits_xcpt_pf_if; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_1_bits_xcpt_ae_if_0 = io_ifu_fetchpacket_bits_uops_1_bits_xcpt_ae_if; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_1_bits_bp_debug_if_0 = io_ifu_fetchpacket_bits_uops_1_bits_bp_debug_if; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_1_bits_bp_xcpt_if_0 = io_ifu_fetchpacket_bits_uops_1_bits_bp_xcpt_if; // @[core.scala:51:7]
wire [1:0] io_ifu_fetchpacket_bits_uops_1_bits_debug_fsrc_0 = io_ifu_fetchpacket_bits_uops_1_bits_debug_fsrc; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_2_valid_0 = io_ifu_fetchpacket_bits_uops_2_valid; // @[core.scala:51:7]
wire [31:0] io_ifu_fetchpacket_bits_uops_2_bits_inst_0 = io_ifu_fetchpacket_bits_uops_2_bits_inst; // @[core.scala:51:7]
wire [31:0] io_ifu_fetchpacket_bits_uops_2_bits_debug_inst_0 = io_ifu_fetchpacket_bits_uops_2_bits_debug_inst; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_2_bits_is_rvc_0 = io_ifu_fetchpacket_bits_uops_2_bits_is_rvc; // @[core.scala:51:7]
wire [39:0] io_ifu_fetchpacket_bits_uops_2_bits_debug_pc_0 = io_ifu_fetchpacket_bits_uops_2_bits_debug_pc; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_2_bits_is_sfb_0 = io_ifu_fetchpacket_bits_uops_2_bits_is_sfb; // @[core.scala:51:7]
wire [4:0] io_ifu_fetchpacket_bits_uops_2_bits_ftq_idx_0 = io_ifu_fetchpacket_bits_uops_2_bits_ftq_idx; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_2_bits_edge_inst_0 = io_ifu_fetchpacket_bits_uops_2_bits_edge_inst; // @[core.scala:51:7]
wire [5:0] io_ifu_fetchpacket_bits_uops_2_bits_pc_lob_0 = io_ifu_fetchpacket_bits_uops_2_bits_pc_lob; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_2_bits_taken_0 = io_ifu_fetchpacket_bits_uops_2_bits_taken; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_2_bits_xcpt_pf_if_0 = io_ifu_fetchpacket_bits_uops_2_bits_xcpt_pf_if; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_2_bits_xcpt_ae_if_0 = io_ifu_fetchpacket_bits_uops_2_bits_xcpt_ae_if; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_2_bits_bp_debug_if_0 = io_ifu_fetchpacket_bits_uops_2_bits_bp_debug_if; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_2_bits_bp_xcpt_if_0 = io_ifu_fetchpacket_bits_uops_2_bits_bp_xcpt_if; // @[core.scala:51:7]
wire [1:0] io_ifu_fetchpacket_bits_uops_2_bits_debug_fsrc_0 = io_ifu_fetchpacket_bits_uops_2_bits_debug_fsrc; // @[core.scala:51:7]
wire io_ifu_get_pc_0_entry_cfi_idx_valid_0 = io_ifu_get_pc_0_entry_cfi_idx_valid; // @[core.scala:51:7]
wire [2:0] io_ifu_get_pc_0_entry_cfi_idx_bits_0 = io_ifu_get_pc_0_entry_cfi_idx_bits; // @[core.scala:51:7]
wire io_ifu_get_pc_0_entry_cfi_taken_0 = io_ifu_get_pc_0_entry_cfi_taken; // @[core.scala:51:7]
wire io_ifu_get_pc_0_entry_cfi_mispredicted_0 = io_ifu_get_pc_0_entry_cfi_mispredicted; // @[core.scala:51:7]
wire [2:0] io_ifu_get_pc_0_entry_cfi_type_0 = io_ifu_get_pc_0_entry_cfi_type; // @[core.scala:51:7]
wire [7:0] io_ifu_get_pc_0_entry_br_mask_0 = io_ifu_get_pc_0_entry_br_mask; // @[core.scala:51:7]
wire io_ifu_get_pc_0_entry_cfi_is_call_0 = io_ifu_get_pc_0_entry_cfi_is_call; // @[core.scala:51:7]
wire io_ifu_get_pc_0_entry_cfi_is_ret_0 = io_ifu_get_pc_0_entry_cfi_is_ret; // @[core.scala:51:7]
wire io_ifu_get_pc_0_entry_cfi_npc_plus4_0 = io_ifu_get_pc_0_entry_cfi_npc_plus4; // @[core.scala:51:7]
wire [39:0] io_ifu_get_pc_0_entry_ras_top_0 = io_ifu_get_pc_0_entry_ras_top; // @[core.scala:51:7]
wire [4:0] io_ifu_get_pc_0_entry_ras_idx_0 = io_ifu_get_pc_0_entry_ras_idx; // @[core.scala:51:7]
wire io_ifu_get_pc_0_entry_start_bank_0 = io_ifu_get_pc_0_entry_start_bank; // @[core.scala:51:7]
wire [39:0] io_ifu_get_pc_0_pc_0 = io_ifu_get_pc_0_pc; // @[core.scala:51:7]
wire [39:0] io_ifu_get_pc_0_com_pc_0 = io_ifu_get_pc_0_com_pc; // @[core.scala:51:7]
wire io_ifu_get_pc_0_next_val_0 = io_ifu_get_pc_0_next_val; // @[core.scala:51:7]
wire [39:0] io_ifu_get_pc_0_next_pc_0 = io_ifu_get_pc_0_next_pc; // @[core.scala:51:7]
wire io_ifu_get_pc_1_entry_cfi_idx_valid_0 = io_ifu_get_pc_1_entry_cfi_idx_valid; // @[core.scala:51:7]
wire [2:0] io_ifu_get_pc_1_entry_cfi_idx_bits_0 = io_ifu_get_pc_1_entry_cfi_idx_bits; // @[core.scala:51:7]
wire io_ifu_get_pc_1_entry_cfi_taken_0 = io_ifu_get_pc_1_entry_cfi_taken; // @[core.scala:51:7]
wire io_ifu_get_pc_1_entry_cfi_mispredicted_0 = io_ifu_get_pc_1_entry_cfi_mispredicted; // @[core.scala:51:7]
wire [2:0] io_ifu_get_pc_1_entry_cfi_type_0 = io_ifu_get_pc_1_entry_cfi_type; // @[core.scala:51:7]
wire [7:0] io_ifu_get_pc_1_entry_br_mask_0 = io_ifu_get_pc_1_entry_br_mask; // @[core.scala:51:7]
wire io_ifu_get_pc_1_entry_cfi_is_call_0 = io_ifu_get_pc_1_entry_cfi_is_call; // @[core.scala:51:7]
wire io_ifu_get_pc_1_entry_cfi_is_ret_0 = io_ifu_get_pc_1_entry_cfi_is_ret; // @[core.scala:51:7]
wire io_ifu_get_pc_1_entry_cfi_npc_plus4_0 = io_ifu_get_pc_1_entry_cfi_npc_plus4; // @[core.scala:51:7]
wire [39:0] io_ifu_get_pc_1_entry_ras_top_0 = io_ifu_get_pc_1_entry_ras_top; // @[core.scala:51:7]
wire [4:0] io_ifu_get_pc_1_entry_ras_idx_0 = io_ifu_get_pc_1_entry_ras_idx; // @[core.scala:51:7]
wire io_ifu_get_pc_1_entry_start_bank_0 = io_ifu_get_pc_1_entry_start_bank; // @[core.scala:51:7]
wire [63:0] io_ifu_get_pc_1_ghist_old_history_0 = io_ifu_get_pc_1_ghist_old_history; // @[core.scala:51:7]
wire io_ifu_get_pc_1_ghist_current_saw_branch_not_taken_0 = io_ifu_get_pc_1_ghist_current_saw_branch_not_taken; // @[core.scala:51:7]
wire io_ifu_get_pc_1_ghist_new_saw_branch_not_taken_0 = io_ifu_get_pc_1_ghist_new_saw_branch_not_taken; // @[core.scala:51:7]
wire io_ifu_get_pc_1_ghist_new_saw_branch_taken_0 = io_ifu_get_pc_1_ghist_new_saw_branch_taken; // @[core.scala:51:7]
wire [4:0] io_ifu_get_pc_1_ghist_ras_idx_0 = io_ifu_get_pc_1_ghist_ras_idx; // @[core.scala:51:7]
wire [39:0] io_ifu_get_pc_1_pc_0 = io_ifu_get_pc_1_pc; // @[core.scala:51:7]
wire [39:0] io_ifu_get_pc_1_com_pc_0 = io_ifu_get_pc_1_com_pc; // @[core.scala:51:7]
wire io_ifu_get_pc_1_next_val_0 = io_ifu_get_pc_1_next_val; // @[core.scala:51:7]
wire [39:0] io_ifu_get_pc_1_next_pc_0 = io_ifu_get_pc_1_next_pc; // @[core.scala:51:7]
wire [39:0] io_ifu_debug_fetch_pc_0_0 = io_ifu_debug_fetch_pc_0; // @[core.scala:51:7]
wire [39:0] io_ifu_debug_fetch_pc_1_0 = io_ifu_debug_fetch_pc_1; // @[core.scala:51:7]
wire [39:0] io_ifu_debug_fetch_pc_2_0 = io_ifu_debug_fetch_pc_2; // @[core.scala:51:7]
wire io_ifu_perf_acquire_0 = io_ifu_perf_acquire; // @[core.scala:51:7]
wire io_ifu_perf_tlbMiss_0 = io_ifu_perf_tlbMiss; // @[core.scala:51:7]
wire io_ptw_perf_l2miss_0 = io_ptw_perf_l2miss; // @[core.scala:51:7]
wire io_ptw_perf_l2hit_0 = io_ptw_perf_l2hit; // @[core.scala:51:7]
wire io_ptw_perf_pte_miss_0 = io_ptw_perf_pte_miss; // @[core.scala:51:7]
wire io_ptw_perf_pte_hit_0 = io_ptw_perf_pte_hit; // @[core.scala:51:7]
wire io_ptw_clock_enabled_0 = io_ptw_clock_enabled; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_valid_0 = io_lsu_exe_0_iresp_valid; // @[core.scala:51:7]
wire [6:0] io_lsu_exe_0_iresp_bits_uop_uopc_0 = io_lsu_exe_0_iresp_bits_uop_uopc; // @[core.scala:51:7]
wire [31:0] io_lsu_exe_0_iresp_bits_uop_inst_0 = io_lsu_exe_0_iresp_bits_uop_inst; // @[core.scala:51:7]
wire [31:0] io_lsu_exe_0_iresp_bits_uop_debug_inst_0 = io_lsu_exe_0_iresp_bits_uop_debug_inst; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_uop_is_rvc_0 = io_lsu_exe_0_iresp_bits_uop_is_rvc; // @[core.scala:51:7]
wire [39:0] io_lsu_exe_0_iresp_bits_uop_debug_pc_0 = io_lsu_exe_0_iresp_bits_uop_debug_pc; // @[core.scala:51:7]
wire [2:0] io_lsu_exe_0_iresp_bits_uop_iq_type_0 = io_lsu_exe_0_iresp_bits_uop_iq_type; // @[core.scala:51:7]
wire [9:0] io_lsu_exe_0_iresp_bits_uop_fu_code_0 = io_lsu_exe_0_iresp_bits_uop_fu_code; // @[core.scala:51:7]
wire [3:0] io_lsu_exe_0_iresp_bits_uop_ctrl_br_type_0 = io_lsu_exe_0_iresp_bits_uop_ctrl_br_type; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_iresp_bits_uop_ctrl_op1_sel_0 = io_lsu_exe_0_iresp_bits_uop_ctrl_op1_sel; // @[core.scala:51:7]
wire [2:0] io_lsu_exe_0_iresp_bits_uop_ctrl_op2_sel_0 = io_lsu_exe_0_iresp_bits_uop_ctrl_op2_sel; // @[core.scala:51:7]
wire [2:0] io_lsu_exe_0_iresp_bits_uop_ctrl_imm_sel_0 = io_lsu_exe_0_iresp_bits_uop_ctrl_imm_sel; // @[core.scala:51:7]
wire [4:0] io_lsu_exe_0_iresp_bits_uop_ctrl_op_fcn_0 = io_lsu_exe_0_iresp_bits_uop_ctrl_op_fcn; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_uop_ctrl_fcn_dw_0 = io_lsu_exe_0_iresp_bits_uop_ctrl_fcn_dw; // @[core.scala:51:7]
wire [2:0] io_lsu_exe_0_iresp_bits_uop_ctrl_csr_cmd_0 = io_lsu_exe_0_iresp_bits_uop_ctrl_csr_cmd; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_uop_ctrl_is_load_0 = io_lsu_exe_0_iresp_bits_uop_ctrl_is_load; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_uop_ctrl_is_sta_0 = io_lsu_exe_0_iresp_bits_uop_ctrl_is_sta; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_uop_ctrl_is_std_0 = io_lsu_exe_0_iresp_bits_uop_ctrl_is_std; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_iresp_bits_uop_iw_state_0 = io_lsu_exe_0_iresp_bits_uop_iw_state; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_uop_iw_p1_poisoned_0 = io_lsu_exe_0_iresp_bits_uop_iw_p1_poisoned; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_uop_iw_p2_poisoned_0 = io_lsu_exe_0_iresp_bits_uop_iw_p2_poisoned; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_uop_is_br_0 = io_lsu_exe_0_iresp_bits_uop_is_br; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_uop_is_jalr_0 = io_lsu_exe_0_iresp_bits_uop_is_jalr; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_uop_is_jal_0 = io_lsu_exe_0_iresp_bits_uop_is_jal; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_uop_is_sfb_0 = io_lsu_exe_0_iresp_bits_uop_is_sfb; // @[core.scala:51:7]
wire [15:0] io_lsu_exe_0_iresp_bits_uop_br_mask_0 = io_lsu_exe_0_iresp_bits_uop_br_mask; // @[core.scala:51:7]
wire [3:0] io_lsu_exe_0_iresp_bits_uop_br_tag_0 = io_lsu_exe_0_iresp_bits_uop_br_tag; // @[core.scala:51:7]
wire [4:0] io_lsu_exe_0_iresp_bits_uop_ftq_idx_0 = io_lsu_exe_0_iresp_bits_uop_ftq_idx; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_uop_edge_inst_0 = io_lsu_exe_0_iresp_bits_uop_edge_inst; // @[core.scala:51:7]
wire [5:0] io_lsu_exe_0_iresp_bits_uop_pc_lob_0 = io_lsu_exe_0_iresp_bits_uop_pc_lob; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_uop_taken_0 = io_lsu_exe_0_iresp_bits_uop_taken; // @[core.scala:51:7]
wire [19:0] io_lsu_exe_0_iresp_bits_uop_imm_packed_0 = io_lsu_exe_0_iresp_bits_uop_imm_packed; // @[core.scala:51:7]
wire [11:0] io_lsu_exe_0_iresp_bits_uop_csr_addr_0 = io_lsu_exe_0_iresp_bits_uop_csr_addr; // @[core.scala:51:7]
wire [6:0] io_lsu_exe_0_iresp_bits_uop_rob_idx_0 = io_lsu_exe_0_iresp_bits_uop_rob_idx; // @[core.scala:51:7]
wire [4:0] io_lsu_exe_0_iresp_bits_uop_ldq_idx_0 = io_lsu_exe_0_iresp_bits_uop_ldq_idx; // @[core.scala:51:7]
wire [4:0] io_lsu_exe_0_iresp_bits_uop_stq_idx_0 = io_lsu_exe_0_iresp_bits_uop_stq_idx; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_iresp_bits_uop_rxq_idx_0 = io_lsu_exe_0_iresp_bits_uop_rxq_idx; // @[core.scala:51:7]
wire [6:0] io_lsu_exe_0_iresp_bits_uop_pdst_0 = io_lsu_exe_0_iresp_bits_uop_pdst; // @[core.scala:51:7]
wire [6:0] io_lsu_exe_0_iresp_bits_uop_prs1_0 = io_lsu_exe_0_iresp_bits_uop_prs1; // @[core.scala:51:7]
wire [6:0] io_lsu_exe_0_iresp_bits_uop_prs2_0 = io_lsu_exe_0_iresp_bits_uop_prs2; // @[core.scala:51:7]
wire [6:0] io_lsu_exe_0_iresp_bits_uop_prs3_0 = io_lsu_exe_0_iresp_bits_uop_prs3; // @[core.scala:51:7]
wire [4:0] io_lsu_exe_0_iresp_bits_uop_ppred_0 = io_lsu_exe_0_iresp_bits_uop_ppred; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_uop_prs1_busy_0 = io_lsu_exe_0_iresp_bits_uop_prs1_busy; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_uop_prs2_busy_0 = io_lsu_exe_0_iresp_bits_uop_prs2_busy; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_uop_prs3_busy_0 = io_lsu_exe_0_iresp_bits_uop_prs3_busy; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_uop_ppred_busy_0 = io_lsu_exe_0_iresp_bits_uop_ppred_busy; // @[core.scala:51:7]
wire [6:0] io_lsu_exe_0_iresp_bits_uop_stale_pdst_0 = io_lsu_exe_0_iresp_bits_uop_stale_pdst; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_uop_exception_0 = io_lsu_exe_0_iresp_bits_uop_exception; // @[core.scala:51:7]
wire [63:0] io_lsu_exe_0_iresp_bits_uop_exc_cause_0 = io_lsu_exe_0_iresp_bits_uop_exc_cause; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_uop_bypassable_0 = io_lsu_exe_0_iresp_bits_uop_bypassable; // @[core.scala:51:7]
wire [4:0] io_lsu_exe_0_iresp_bits_uop_mem_cmd_0 = io_lsu_exe_0_iresp_bits_uop_mem_cmd; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_iresp_bits_uop_mem_size_0 = io_lsu_exe_0_iresp_bits_uop_mem_size; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_uop_mem_signed_0 = io_lsu_exe_0_iresp_bits_uop_mem_signed; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_uop_is_fence_0 = io_lsu_exe_0_iresp_bits_uop_is_fence; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_uop_is_fencei_0 = io_lsu_exe_0_iresp_bits_uop_is_fencei; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_uop_is_amo_0 = io_lsu_exe_0_iresp_bits_uop_is_amo; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_uop_uses_ldq_0 = io_lsu_exe_0_iresp_bits_uop_uses_ldq; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_uop_uses_stq_0 = io_lsu_exe_0_iresp_bits_uop_uses_stq; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_uop_is_sys_pc2epc_0 = io_lsu_exe_0_iresp_bits_uop_is_sys_pc2epc; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_uop_is_unique_0 = io_lsu_exe_0_iresp_bits_uop_is_unique; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_uop_flush_on_commit_0 = io_lsu_exe_0_iresp_bits_uop_flush_on_commit; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_uop_ldst_is_rs1_0 = io_lsu_exe_0_iresp_bits_uop_ldst_is_rs1; // @[core.scala:51:7]
wire [5:0] io_lsu_exe_0_iresp_bits_uop_ldst_0 = io_lsu_exe_0_iresp_bits_uop_ldst; // @[core.scala:51:7]
wire [5:0] io_lsu_exe_0_iresp_bits_uop_lrs1_0 = io_lsu_exe_0_iresp_bits_uop_lrs1; // @[core.scala:51:7]
wire [5:0] io_lsu_exe_0_iresp_bits_uop_lrs2_0 = io_lsu_exe_0_iresp_bits_uop_lrs2; // @[core.scala:51:7]
wire [5:0] io_lsu_exe_0_iresp_bits_uop_lrs3_0 = io_lsu_exe_0_iresp_bits_uop_lrs3; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_uop_ldst_val_0 = io_lsu_exe_0_iresp_bits_uop_ldst_val; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_iresp_bits_uop_dst_rtype_0 = io_lsu_exe_0_iresp_bits_uop_dst_rtype; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_iresp_bits_uop_lrs1_rtype_0 = io_lsu_exe_0_iresp_bits_uop_lrs1_rtype; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_iresp_bits_uop_lrs2_rtype_0 = io_lsu_exe_0_iresp_bits_uop_lrs2_rtype; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_uop_frs3_en_0 = io_lsu_exe_0_iresp_bits_uop_frs3_en; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_uop_fp_val_0 = io_lsu_exe_0_iresp_bits_uop_fp_val; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_uop_fp_single_0 = io_lsu_exe_0_iresp_bits_uop_fp_single; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_uop_xcpt_pf_if_0 = io_lsu_exe_0_iresp_bits_uop_xcpt_pf_if; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_uop_xcpt_ae_if_0 = io_lsu_exe_0_iresp_bits_uop_xcpt_ae_if; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_uop_xcpt_ma_if_0 = io_lsu_exe_0_iresp_bits_uop_xcpt_ma_if; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_uop_bp_debug_if_0 = io_lsu_exe_0_iresp_bits_uop_bp_debug_if; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_uop_bp_xcpt_if_0 = io_lsu_exe_0_iresp_bits_uop_bp_xcpt_if; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_iresp_bits_uop_debug_fsrc_0 = io_lsu_exe_0_iresp_bits_uop_debug_fsrc; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_iresp_bits_uop_debug_tsrc_0 = io_lsu_exe_0_iresp_bits_uop_debug_tsrc; // @[core.scala:51:7]
wire [63:0] io_lsu_exe_0_iresp_bits_data_0 = io_lsu_exe_0_iresp_bits_data; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_valid_0 = io_lsu_exe_0_fresp_valid; // @[core.scala:51:7]
wire [6:0] io_lsu_exe_0_fresp_bits_uop_uopc_0 = io_lsu_exe_0_fresp_bits_uop_uopc; // @[core.scala:51:7]
wire [31:0] io_lsu_exe_0_fresp_bits_uop_inst_0 = io_lsu_exe_0_fresp_bits_uop_inst; // @[core.scala:51:7]
wire [31:0] io_lsu_exe_0_fresp_bits_uop_debug_inst_0 = io_lsu_exe_0_fresp_bits_uop_debug_inst; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_uop_is_rvc_0 = io_lsu_exe_0_fresp_bits_uop_is_rvc; // @[core.scala:51:7]
wire [39:0] io_lsu_exe_0_fresp_bits_uop_debug_pc_0 = io_lsu_exe_0_fresp_bits_uop_debug_pc; // @[core.scala:51:7]
wire [2:0] io_lsu_exe_0_fresp_bits_uop_iq_type_0 = io_lsu_exe_0_fresp_bits_uop_iq_type; // @[core.scala:51:7]
wire [9:0] io_lsu_exe_0_fresp_bits_uop_fu_code_0 = io_lsu_exe_0_fresp_bits_uop_fu_code; // @[core.scala:51:7]
wire [3:0] io_lsu_exe_0_fresp_bits_uop_ctrl_br_type_0 = io_lsu_exe_0_fresp_bits_uop_ctrl_br_type; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_fresp_bits_uop_ctrl_op1_sel_0 = io_lsu_exe_0_fresp_bits_uop_ctrl_op1_sel; // @[core.scala:51:7]
wire [2:0] io_lsu_exe_0_fresp_bits_uop_ctrl_op2_sel_0 = io_lsu_exe_0_fresp_bits_uop_ctrl_op2_sel; // @[core.scala:51:7]
wire [2:0] io_lsu_exe_0_fresp_bits_uop_ctrl_imm_sel_0 = io_lsu_exe_0_fresp_bits_uop_ctrl_imm_sel; // @[core.scala:51:7]
wire [4:0] io_lsu_exe_0_fresp_bits_uop_ctrl_op_fcn_0 = io_lsu_exe_0_fresp_bits_uop_ctrl_op_fcn; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_uop_ctrl_fcn_dw_0 = io_lsu_exe_0_fresp_bits_uop_ctrl_fcn_dw; // @[core.scala:51:7]
wire [2:0] io_lsu_exe_0_fresp_bits_uop_ctrl_csr_cmd_0 = io_lsu_exe_0_fresp_bits_uop_ctrl_csr_cmd; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_uop_ctrl_is_load_0 = io_lsu_exe_0_fresp_bits_uop_ctrl_is_load; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_uop_ctrl_is_sta_0 = io_lsu_exe_0_fresp_bits_uop_ctrl_is_sta; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_uop_ctrl_is_std_0 = io_lsu_exe_0_fresp_bits_uop_ctrl_is_std; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_fresp_bits_uop_iw_state_0 = io_lsu_exe_0_fresp_bits_uop_iw_state; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_uop_iw_p1_poisoned_0 = io_lsu_exe_0_fresp_bits_uop_iw_p1_poisoned; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_uop_iw_p2_poisoned_0 = io_lsu_exe_0_fresp_bits_uop_iw_p2_poisoned; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_uop_is_br_0 = io_lsu_exe_0_fresp_bits_uop_is_br; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_uop_is_jalr_0 = io_lsu_exe_0_fresp_bits_uop_is_jalr; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_uop_is_jal_0 = io_lsu_exe_0_fresp_bits_uop_is_jal; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_uop_is_sfb_0 = io_lsu_exe_0_fresp_bits_uop_is_sfb; // @[core.scala:51:7]
wire [15:0] io_lsu_exe_0_fresp_bits_uop_br_mask_0 = io_lsu_exe_0_fresp_bits_uop_br_mask; // @[core.scala:51:7]
wire [3:0] io_lsu_exe_0_fresp_bits_uop_br_tag_0 = io_lsu_exe_0_fresp_bits_uop_br_tag; // @[core.scala:51:7]
wire [4:0] io_lsu_exe_0_fresp_bits_uop_ftq_idx_0 = io_lsu_exe_0_fresp_bits_uop_ftq_idx; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_uop_edge_inst_0 = io_lsu_exe_0_fresp_bits_uop_edge_inst; // @[core.scala:51:7]
wire [5:0] io_lsu_exe_0_fresp_bits_uop_pc_lob_0 = io_lsu_exe_0_fresp_bits_uop_pc_lob; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_uop_taken_0 = io_lsu_exe_0_fresp_bits_uop_taken; // @[core.scala:51:7]
wire [19:0] io_lsu_exe_0_fresp_bits_uop_imm_packed_0 = io_lsu_exe_0_fresp_bits_uop_imm_packed; // @[core.scala:51:7]
wire [11:0] io_lsu_exe_0_fresp_bits_uop_csr_addr_0 = io_lsu_exe_0_fresp_bits_uop_csr_addr; // @[core.scala:51:7]
wire [6:0] io_lsu_exe_0_fresp_bits_uop_rob_idx_0 = io_lsu_exe_0_fresp_bits_uop_rob_idx; // @[core.scala:51:7]
wire [4:0] io_lsu_exe_0_fresp_bits_uop_ldq_idx_0 = io_lsu_exe_0_fresp_bits_uop_ldq_idx; // @[core.scala:51:7]
wire [4:0] io_lsu_exe_0_fresp_bits_uop_stq_idx_0 = io_lsu_exe_0_fresp_bits_uop_stq_idx; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_fresp_bits_uop_rxq_idx_0 = io_lsu_exe_0_fresp_bits_uop_rxq_idx; // @[core.scala:51:7]
wire [6:0] io_lsu_exe_0_fresp_bits_uop_pdst_0 = io_lsu_exe_0_fresp_bits_uop_pdst; // @[core.scala:51:7]
wire [6:0] io_lsu_exe_0_fresp_bits_uop_prs1_0 = io_lsu_exe_0_fresp_bits_uop_prs1; // @[core.scala:51:7]
wire [6:0] io_lsu_exe_0_fresp_bits_uop_prs2_0 = io_lsu_exe_0_fresp_bits_uop_prs2; // @[core.scala:51:7]
wire [6:0] io_lsu_exe_0_fresp_bits_uop_prs3_0 = io_lsu_exe_0_fresp_bits_uop_prs3; // @[core.scala:51:7]
wire [4:0] io_lsu_exe_0_fresp_bits_uop_ppred_0 = io_lsu_exe_0_fresp_bits_uop_ppred; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_uop_prs1_busy_0 = io_lsu_exe_0_fresp_bits_uop_prs1_busy; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_uop_prs2_busy_0 = io_lsu_exe_0_fresp_bits_uop_prs2_busy; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_uop_prs3_busy_0 = io_lsu_exe_0_fresp_bits_uop_prs3_busy; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_uop_ppred_busy_0 = io_lsu_exe_0_fresp_bits_uop_ppred_busy; // @[core.scala:51:7]
wire [6:0] io_lsu_exe_0_fresp_bits_uop_stale_pdst_0 = io_lsu_exe_0_fresp_bits_uop_stale_pdst; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_uop_exception_0 = io_lsu_exe_0_fresp_bits_uop_exception; // @[core.scala:51:7]
wire [63:0] io_lsu_exe_0_fresp_bits_uop_exc_cause_0 = io_lsu_exe_0_fresp_bits_uop_exc_cause; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_uop_bypassable_0 = io_lsu_exe_0_fresp_bits_uop_bypassable; // @[core.scala:51:7]
wire [4:0] io_lsu_exe_0_fresp_bits_uop_mem_cmd_0 = io_lsu_exe_0_fresp_bits_uop_mem_cmd; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_fresp_bits_uop_mem_size_0 = io_lsu_exe_0_fresp_bits_uop_mem_size; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_uop_mem_signed_0 = io_lsu_exe_0_fresp_bits_uop_mem_signed; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_uop_is_fence_0 = io_lsu_exe_0_fresp_bits_uop_is_fence; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_uop_is_fencei_0 = io_lsu_exe_0_fresp_bits_uop_is_fencei; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_uop_is_amo_0 = io_lsu_exe_0_fresp_bits_uop_is_amo; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_uop_uses_ldq_0 = io_lsu_exe_0_fresp_bits_uop_uses_ldq; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_uop_uses_stq_0 = io_lsu_exe_0_fresp_bits_uop_uses_stq; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_uop_is_sys_pc2epc_0 = io_lsu_exe_0_fresp_bits_uop_is_sys_pc2epc; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_uop_is_unique_0 = io_lsu_exe_0_fresp_bits_uop_is_unique; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_uop_flush_on_commit_0 = io_lsu_exe_0_fresp_bits_uop_flush_on_commit; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_uop_ldst_is_rs1_0 = io_lsu_exe_0_fresp_bits_uop_ldst_is_rs1; // @[core.scala:51:7]
wire [5:0] io_lsu_exe_0_fresp_bits_uop_ldst_0 = io_lsu_exe_0_fresp_bits_uop_ldst; // @[core.scala:51:7]
wire [5:0] io_lsu_exe_0_fresp_bits_uop_lrs1_0 = io_lsu_exe_0_fresp_bits_uop_lrs1; // @[core.scala:51:7]
wire [5:0] io_lsu_exe_0_fresp_bits_uop_lrs2_0 = io_lsu_exe_0_fresp_bits_uop_lrs2; // @[core.scala:51:7]
wire [5:0] io_lsu_exe_0_fresp_bits_uop_lrs3_0 = io_lsu_exe_0_fresp_bits_uop_lrs3; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_uop_ldst_val_0 = io_lsu_exe_0_fresp_bits_uop_ldst_val; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_fresp_bits_uop_dst_rtype_0 = io_lsu_exe_0_fresp_bits_uop_dst_rtype; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_fresp_bits_uop_lrs1_rtype_0 = io_lsu_exe_0_fresp_bits_uop_lrs1_rtype; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_fresp_bits_uop_lrs2_rtype_0 = io_lsu_exe_0_fresp_bits_uop_lrs2_rtype; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_uop_frs3_en_0 = io_lsu_exe_0_fresp_bits_uop_frs3_en; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_uop_fp_val_0 = io_lsu_exe_0_fresp_bits_uop_fp_val; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_uop_fp_single_0 = io_lsu_exe_0_fresp_bits_uop_fp_single; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_uop_xcpt_pf_if_0 = io_lsu_exe_0_fresp_bits_uop_xcpt_pf_if; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_uop_xcpt_ae_if_0 = io_lsu_exe_0_fresp_bits_uop_xcpt_ae_if; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_uop_xcpt_ma_if_0 = io_lsu_exe_0_fresp_bits_uop_xcpt_ma_if; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_uop_bp_debug_if_0 = io_lsu_exe_0_fresp_bits_uop_bp_debug_if; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_uop_bp_xcpt_if_0 = io_lsu_exe_0_fresp_bits_uop_bp_xcpt_if; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_fresp_bits_uop_debug_fsrc_0 = io_lsu_exe_0_fresp_bits_uop_debug_fsrc; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_fresp_bits_uop_debug_tsrc_0 = io_lsu_exe_0_fresp_bits_uop_debug_tsrc; // @[core.scala:51:7]
wire [64:0] io_lsu_exe_0_fresp_bits_data_0 = io_lsu_exe_0_fresp_bits_data; // @[core.scala:51:7]
wire [4:0] io_lsu_dis_ldq_idx_0_0 = io_lsu_dis_ldq_idx_0; // @[core.scala:51:7]
wire [4:0] io_lsu_dis_ldq_idx_1_0 = io_lsu_dis_ldq_idx_1; // @[core.scala:51:7]
wire [4:0] io_lsu_dis_ldq_idx_2_0 = io_lsu_dis_ldq_idx_2; // @[core.scala:51:7]
wire [4:0] io_lsu_dis_stq_idx_0_0 = io_lsu_dis_stq_idx_0; // @[core.scala:51:7]
wire [4:0] io_lsu_dis_stq_idx_1_0 = io_lsu_dis_stq_idx_1; // @[core.scala:51:7]
wire [4:0] io_lsu_dis_stq_idx_2_0 = io_lsu_dis_stq_idx_2; // @[core.scala:51:7]
wire io_lsu_ldq_full_0_0 = io_lsu_ldq_full_0; // @[core.scala:51:7]
wire io_lsu_ldq_full_1_0 = io_lsu_ldq_full_1; // @[core.scala:51:7]
wire io_lsu_ldq_full_2_0 = io_lsu_ldq_full_2; // @[core.scala:51:7]
wire io_lsu_stq_full_0_0 = io_lsu_stq_full_0; // @[core.scala:51:7]
wire io_lsu_stq_full_1_0 = io_lsu_stq_full_1; // @[core.scala:51:7]
wire io_lsu_stq_full_2_0 = io_lsu_stq_full_2; // @[core.scala:51:7]
wire io_lsu_fp_stdata_ready_0 = io_lsu_fp_stdata_ready; // @[core.scala:51:7]
wire io_lsu_clr_bsy_0_valid_0 = io_lsu_clr_bsy_0_valid; // @[core.scala:51:7]
wire [6:0] io_lsu_clr_bsy_0_bits_0 = io_lsu_clr_bsy_0_bits; // @[core.scala:51:7]
wire io_lsu_clr_bsy_1_valid_0 = io_lsu_clr_bsy_1_valid; // @[core.scala:51:7]
wire [6:0] io_lsu_clr_bsy_1_bits_0 = io_lsu_clr_bsy_1_bits; // @[core.scala:51:7]
wire [6:0] io_lsu_clr_unsafe_0_bits_0 = io_lsu_clr_unsafe_0_bits; // @[core.scala:51:7]
wire io_lsu_spec_ld_wakeup_0_valid_0 = io_lsu_spec_ld_wakeup_0_valid; // @[core.scala:51:7]
wire [6:0] io_lsu_spec_ld_wakeup_0_bits_0 = io_lsu_spec_ld_wakeup_0_bits; // @[core.scala:51:7]
wire io_lsu_ld_miss_0 = io_lsu_ld_miss; // @[core.scala:51:7]
wire io_lsu_fencei_rdy_0 = io_lsu_fencei_rdy; // @[core.scala:51:7]
wire io_lsu_lxcpt_valid_0 = io_lsu_lxcpt_valid; // @[core.scala:51:7]
wire [6:0] io_lsu_lxcpt_bits_uop_uopc_0 = io_lsu_lxcpt_bits_uop_uopc; // @[core.scala:51:7]
wire [31:0] io_lsu_lxcpt_bits_uop_inst_0 = io_lsu_lxcpt_bits_uop_inst; // @[core.scala:51:7]
wire [31:0] io_lsu_lxcpt_bits_uop_debug_inst_0 = io_lsu_lxcpt_bits_uop_debug_inst; // @[core.scala:51:7]
wire io_lsu_lxcpt_bits_uop_is_rvc_0 = io_lsu_lxcpt_bits_uop_is_rvc; // @[core.scala:51:7]
wire [39:0] io_lsu_lxcpt_bits_uop_debug_pc_0 = io_lsu_lxcpt_bits_uop_debug_pc; // @[core.scala:51:7]
wire [2:0] io_lsu_lxcpt_bits_uop_iq_type_0 = io_lsu_lxcpt_bits_uop_iq_type; // @[core.scala:51:7]
wire [9:0] io_lsu_lxcpt_bits_uop_fu_code_0 = io_lsu_lxcpt_bits_uop_fu_code; // @[core.scala:51:7]
wire [3:0] io_lsu_lxcpt_bits_uop_ctrl_br_type_0 = io_lsu_lxcpt_bits_uop_ctrl_br_type; // @[core.scala:51:7]
wire [1:0] io_lsu_lxcpt_bits_uop_ctrl_op1_sel_0 = io_lsu_lxcpt_bits_uop_ctrl_op1_sel; // @[core.scala:51:7]
wire [2:0] io_lsu_lxcpt_bits_uop_ctrl_op2_sel_0 = io_lsu_lxcpt_bits_uop_ctrl_op2_sel; // @[core.scala:51:7]
wire [2:0] io_lsu_lxcpt_bits_uop_ctrl_imm_sel_0 = io_lsu_lxcpt_bits_uop_ctrl_imm_sel; // @[core.scala:51:7]
wire [4:0] io_lsu_lxcpt_bits_uop_ctrl_op_fcn_0 = io_lsu_lxcpt_bits_uop_ctrl_op_fcn; // @[core.scala:51:7]
wire io_lsu_lxcpt_bits_uop_ctrl_fcn_dw_0 = io_lsu_lxcpt_bits_uop_ctrl_fcn_dw; // @[core.scala:51:7]
wire [2:0] io_lsu_lxcpt_bits_uop_ctrl_csr_cmd_0 = io_lsu_lxcpt_bits_uop_ctrl_csr_cmd; // @[core.scala:51:7]
wire io_lsu_lxcpt_bits_uop_ctrl_is_load_0 = io_lsu_lxcpt_bits_uop_ctrl_is_load; // @[core.scala:51:7]
wire io_lsu_lxcpt_bits_uop_ctrl_is_sta_0 = io_lsu_lxcpt_bits_uop_ctrl_is_sta; // @[core.scala:51:7]
wire io_lsu_lxcpt_bits_uop_ctrl_is_std_0 = io_lsu_lxcpt_bits_uop_ctrl_is_std; // @[core.scala:51:7]
wire [1:0] io_lsu_lxcpt_bits_uop_iw_state_0 = io_lsu_lxcpt_bits_uop_iw_state; // @[core.scala:51:7]
wire io_lsu_lxcpt_bits_uop_iw_p1_poisoned_0 = io_lsu_lxcpt_bits_uop_iw_p1_poisoned; // @[core.scala:51:7]
wire io_lsu_lxcpt_bits_uop_iw_p2_poisoned_0 = io_lsu_lxcpt_bits_uop_iw_p2_poisoned; // @[core.scala:51:7]
wire io_lsu_lxcpt_bits_uop_is_br_0 = io_lsu_lxcpt_bits_uop_is_br; // @[core.scala:51:7]
wire io_lsu_lxcpt_bits_uop_is_jalr_0 = io_lsu_lxcpt_bits_uop_is_jalr; // @[core.scala:51:7]
wire io_lsu_lxcpt_bits_uop_is_jal_0 = io_lsu_lxcpt_bits_uop_is_jal; // @[core.scala:51:7]
wire io_lsu_lxcpt_bits_uop_is_sfb_0 = io_lsu_lxcpt_bits_uop_is_sfb; // @[core.scala:51:7]
wire [15:0] io_lsu_lxcpt_bits_uop_br_mask_0 = io_lsu_lxcpt_bits_uop_br_mask; // @[core.scala:51:7]
wire [3:0] io_lsu_lxcpt_bits_uop_br_tag_0 = io_lsu_lxcpt_bits_uop_br_tag; // @[core.scala:51:7]
wire [4:0] io_lsu_lxcpt_bits_uop_ftq_idx_0 = io_lsu_lxcpt_bits_uop_ftq_idx; // @[core.scala:51:7]
wire io_lsu_lxcpt_bits_uop_edge_inst_0 = io_lsu_lxcpt_bits_uop_edge_inst; // @[core.scala:51:7]
wire [5:0] io_lsu_lxcpt_bits_uop_pc_lob_0 = io_lsu_lxcpt_bits_uop_pc_lob; // @[core.scala:51:7]
wire io_lsu_lxcpt_bits_uop_taken_0 = io_lsu_lxcpt_bits_uop_taken; // @[core.scala:51:7]
wire [19:0] io_lsu_lxcpt_bits_uop_imm_packed_0 = io_lsu_lxcpt_bits_uop_imm_packed; // @[core.scala:51:7]
wire [11:0] io_lsu_lxcpt_bits_uop_csr_addr_0 = io_lsu_lxcpt_bits_uop_csr_addr; // @[core.scala:51:7]
wire [6:0] io_lsu_lxcpt_bits_uop_rob_idx_0 = io_lsu_lxcpt_bits_uop_rob_idx; // @[core.scala:51:7]
wire [4:0] io_lsu_lxcpt_bits_uop_ldq_idx_0 = io_lsu_lxcpt_bits_uop_ldq_idx; // @[core.scala:51:7]
wire [4:0] io_lsu_lxcpt_bits_uop_stq_idx_0 = io_lsu_lxcpt_bits_uop_stq_idx; // @[core.scala:51:7]
wire [1:0] io_lsu_lxcpt_bits_uop_rxq_idx_0 = io_lsu_lxcpt_bits_uop_rxq_idx; // @[core.scala:51:7]
wire [6:0] io_lsu_lxcpt_bits_uop_pdst_0 = io_lsu_lxcpt_bits_uop_pdst; // @[core.scala:51:7]
wire [6:0] io_lsu_lxcpt_bits_uop_prs1_0 = io_lsu_lxcpt_bits_uop_prs1; // @[core.scala:51:7]
wire [6:0] io_lsu_lxcpt_bits_uop_prs2_0 = io_lsu_lxcpt_bits_uop_prs2; // @[core.scala:51:7]
wire [6:0] io_lsu_lxcpt_bits_uop_prs3_0 = io_lsu_lxcpt_bits_uop_prs3; // @[core.scala:51:7]
wire [4:0] io_lsu_lxcpt_bits_uop_ppred_0 = io_lsu_lxcpt_bits_uop_ppred; // @[core.scala:51:7]
wire io_lsu_lxcpt_bits_uop_prs1_busy_0 = io_lsu_lxcpt_bits_uop_prs1_busy; // @[core.scala:51:7]
wire io_lsu_lxcpt_bits_uop_prs2_busy_0 = io_lsu_lxcpt_bits_uop_prs2_busy; // @[core.scala:51:7]
wire io_lsu_lxcpt_bits_uop_prs3_busy_0 = io_lsu_lxcpt_bits_uop_prs3_busy; // @[core.scala:51:7]
wire io_lsu_lxcpt_bits_uop_ppred_busy_0 = io_lsu_lxcpt_bits_uop_ppred_busy; // @[core.scala:51:7]
wire [6:0] io_lsu_lxcpt_bits_uop_stale_pdst_0 = io_lsu_lxcpt_bits_uop_stale_pdst; // @[core.scala:51:7]
wire io_lsu_lxcpt_bits_uop_exception_0 = io_lsu_lxcpt_bits_uop_exception; // @[core.scala:51:7]
wire [63:0] io_lsu_lxcpt_bits_uop_exc_cause_0 = io_lsu_lxcpt_bits_uop_exc_cause; // @[core.scala:51:7]
wire io_lsu_lxcpt_bits_uop_bypassable_0 = io_lsu_lxcpt_bits_uop_bypassable; // @[core.scala:51:7]
wire [4:0] io_lsu_lxcpt_bits_uop_mem_cmd_0 = io_lsu_lxcpt_bits_uop_mem_cmd; // @[core.scala:51:7]
wire [1:0] io_lsu_lxcpt_bits_uop_mem_size_0 = io_lsu_lxcpt_bits_uop_mem_size; // @[core.scala:51:7]
wire io_lsu_lxcpt_bits_uop_mem_signed_0 = io_lsu_lxcpt_bits_uop_mem_signed; // @[core.scala:51:7]
wire io_lsu_lxcpt_bits_uop_is_fence_0 = io_lsu_lxcpt_bits_uop_is_fence; // @[core.scala:51:7]
wire io_lsu_lxcpt_bits_uop_is_fencei_0 = io_lsu_lxcpt_bits_uop_is_fencei; // @[core.scala:51:7]
wire io_lsu_lxcpt_bits_uop_is_amo_0 = io_lsu_lxcpt_bits_uop_is_amo; // @[core.scala:51:7]
wire io_lsu_lxcpt_bits_uop_uses_ldq_0 = io_lsu_lxcpt_bits_uop_uses_ldq; // @[core.scala:51:7]
wire io_lsu_lxcpt_bits_uop_uses_stq_0 = io_lsu_lxcpt_bits_uop_uses_stq; // @[core.scala:51:7]
wire io_lsu_lxcpt_bits_uop_is_sys_pc2epc_0 = io_lsu_lxcpt_bits_uop_is_sys_pc2epc; // @[core.scala:51:7]
wire io_lsu_lxcpt_bits_uop_is_unique_0 = io_lsu_lxcpt_bits_uop_is_unique; // @[core.scala:51:7]
wire io_lsu_lxcpt_bits_uop_flush_on_commit_0 = io_lsu_lxcpt_bits_uop_flush_on_commit; // @[core.scala:51:7]
wire io_lsu_lxcpt_bits_uop_ldst_is_rs1_0 = io_lsu_lxcpt_bits_uop_ldst_is_rs1; // @[core.scala:51:7]
wire [5:0] io_lsu_lxcpt_bits_uop_ldst_0 = io_lsu_lxcpt_bits_uop_ldst; // @[core.scala:51:7]
wire [5:0] io_lsu_lxcpt_bits_uop_lrs1_0 = io_lsu_lxcpt_bits_uop_lrs1; // @[core.scala:51:7]
wire [5:0] io_lsu_lxcpt_bits_uop_lrs2_0 = io_lsu_lxcpt_bits_uop_lrs2; // @[core.scala:51:7]
wire [5:0] io_lsu_lxcpt_bits_uop_lrs3_0 = io_lsu_lxcpt_bits_uop_lrs3; // @[core.scala:51:7]
wire io_lsu_lxcpt_bits_uop_ldst_val_0 = io_lsu_lxcpt_bits_uop_ldst_val; // @[core.scala:51:7]
wire [1:0] io_lsu_lxcpt_bits_uop_dst_rtype_0 = io_lsu_lxcpt_bits_uop_dst_rtype; // @[core.scala:51:7]
wire [1:0] io_lsu_lxcpt_bits_uop_lrs1_rtype_0 = io_lsu_lxcpt_bits_uop_lrs1_rtype; // @[core.scala:51:7]
wire [1:0] io_lsu_lxcpt_bits_uop_lrs2_rtype_0 = io_lsu_lxcpt_bits_uop_lrs2_rtype; // @[core.scala:51:7]
wire io_lsu_lxcpt_bits_uop_frs3_en_0 = io_lsu_lxcpt_bits_uop_frs3_en; // @[core.scala:51:7]
wire io_lsu_lxcpt_bits_uop_fp_val_0 = io_lsu_lxcpt_bits_uop_fp_val; // @[core.scala:51:7]
wire io_lsu_lxcpt_bits_uop_fp_single_0 = io_lsu_lxcpt_bits_uop_fp_single; // @[core.scala:51:7]
wire io_lsu_lxcpt_bits_uop_xcpt_pf_if_0 = io_lsu_lxcpt_bits_uop_xcpt_pf_if; // @[core.scala:51:7]
wire io_lsu_lxcpt_bits_uop_xcpt_ae_if_0 = io_lsu_lxcpt_bits_uop_xcpt_ae_if; // @[core.scala:51:7]
wire io_lsu_lxcpt_bits_uop_xcpt_ma_if_0 = io_lsu_lxcpt_bits_uop_xcpt_ma_if; // @[core.scala:51:7]
wire io_lsu_lxcpt_bits_uop_bp_debug_if_0 = io_lsu_lxcpt_bits_uop_bp_debug_if; // @[core.scala:51:7]
wire io_lsu_lxcpt_bits_uop_bp_xcpt_if_0 = io_lsu_lxcpt_bits_uop_bp_xcpt_if; // @[core.scala:51:7]
wire [1:0] io_lsu_lxcpt_bits_uop_debug_fsrc_0 = io_lsu_lxcpt_bits_uop_debug_fsrc; // @[core.scala:51:7]
wire [1:0] io_lsu_lxcpt_bits_uop_debug_tsrc_0 = io_lsu_lxcpt_bits_uop_debug_tsrc; // @[core.scala:51:7]
wire [4:0] io_lsu_lxcpt_bits_cause_0 = io_lsu_lxcpt_bits_cause; // @[core.scala:51:7]
wire [39:0] io_lsu_lxcpt_bits_badvaddr_0 = io_lsu_lxcpt_bits_badvaddr; // @[core.scala:51:7]
wire io_lsu_perf_acquire_0 = io_lsu_perf_acquire; // @[core.scala:51:7]
wire io_lsu_perf_release_0 = io_lsu_perf_release; // @[core.scala:51:7]
wire io_lsu_perf_tlbMiss_0 = io_lsu_perf_tlbMiss; // @[core.scala:51:7]
wire io_ptw_tlb_req_ready_0 = io_ptw_tlb_req_ready; // @[core.scala:51:7]
wire io_ptw_tlb_resp_valid_0 = io_ptw_tlb_resp_valid; // @[core.scala:51:7]
wire io_ptw_tlb_resp_bits_ae_ptw_0 = io_ptw_tlb_resp_bits_ae_ptw; // @[core.scala:51:7]
wire io_ptw_tlb_resp_bits_ae_final_0 = io_ptw_tlb_resp_bits_ae_final; // @[core.scala:51:7]
wire io_ptw_tlb_resp_bits_pf_0 = io_ptw_tlb_resp_bits_pf; // @[core.scala:51:7]
wire io_ptw_tlb_resp_bits_gf_0 = io_ptw_tlb_resp_bits_gf; // @[core.scala:51:7]
wire io_ptw_tlb_resp_bits_hr_0 = io_ptw_tlb_resp_bits_hr; // @[core.scala:51:7]
wire io_ptw_tlb_resp_bits_hw_0 = io_ptw_tlb_resp_bits_hw; // @[core.scala:51:7]
wire io_ptw_tlb_resp_bits_hx_0 = io_ptw_tlb_resp_bits_hx; // @[core.scala:51:7]
wire [9:0] io_ptw_tlb_resp_bits_pte_reserved_for_future_0 = io_ptw_tlb_resp_bits_pte_reserved_for_future; // @[core.scala:51:7]
wire [43:0] io_ptw_tlb_resp_bits_pte_ppn_0 = io_ptw_tlb_resp_bits_pte_ppn; // @[core.scala:51:7]
wire [1:0] io_ptw_tlb_resp_bits_pte_reserved_for_software_0 = io_ptw_tlb_resp_bits_pte_reserved_for_software; // @[core.scala:51:7]
wire io_ptw_tlb_resp_bits_pte_d_0 = io_ptw_tlb_resp_bits_pte_d; // @[core.scala:51:7]
wire io_ptw_tlb_resp_bits_pte_a_0 = io_ptw_tlb_resp_bits_pte_a; // @[core.scala:51:7]
wire io_ptw_tlb_resp_bits_pte_g_0 = io_ptw_tlb_resp_bits_pte_g; // @[core.scala:51:7]
wire io_ptw_tlb_resp_bits_pte_u_0 = io_ptw_tlb_resp_bits_pte_u; // @[core.scala:51:7]
wire io_ptw_tlb_resp_bits_pte_x_0 = io_ptw_tlb_resp_bits_pte_x; // @[core.scala:51:7]
wire io_ptw_tlb_resp_bits_pte_w_0 = io_ptw_tlb_resp_bits_pte_w; // @[core.scala:51:7]
wire io_ptw_tlb_resp_bits_pte_r_0 = io_ptw_tlb_resp_bits_pte_r; // @[core.scala:51:7]
wire io_ptw_tlb_resp_bits_pte_v_0 = io_ptw_tlb_resp_bits_pte_v; // @[core.scala:51:7]
wire [1:0] io_ptw_tlb_resp_bits_level_0 = io_ptw_tlb_resp_bits_level; // @[core.scala:51:7]
wire io_ptw_tlb_resp_bits_homogeneous_0 = io_ptw_tlb_resp_bits_homogeneous; // @[core.scala:51:7]
wire io_ptw_tlb_resp_bits_gpa_valid_0 = io_ptw_tlb_resp_bits_gpa_valid; // @[core.scala:51:7]
wire [38:0] io_ptw_tlb_resp_bits_gpa_bits_0 = io_ptw_tlb_resp_bits_gpa_bits; // @[core.scala:51:7]
wire io_ptw_tlb_resp_bits_gpa_is_pte_0 = io_ptw_tlb_resp_bits_gpa_is_pte; // @[core.scala:51:7]
wire [3:0] io_ptw_tlb_ptbr_mode_0 = io_ptw_tlb_ptbr_mode; // @[core.scala:51:7]
wire [43:0] io_ptw_tlb_ptbr_ppn_0 = io_ptw_tlb_ptbr_ppn; // @[core.scala:51:7]
wire io_ptw_tlb_status_debug_0 = io_ptw_tlb_status_debug; // @[core.scala:51:7]
wire io_ptw_tlb_status_cease_0 = io_ptw_tlb_status_cease; // @[core.scala:51:7]
wire io_ptw_tlb_status_wfi_0 = io_ptw_tlb_status_wfi; // @[core.scala:51:7]
wire [1:0] io_ptw_tlb_status_dprv_0 = io_ptw_tlb_status_dprv; // @[core.scala:51:7]
wire io_ptw_tlb_status_dv_0 = io_ptw_tlb_status_dv; // @[core.scala:51:7]
wire [1:0] io_ptw_tlb_status_prv_0 = io_ptw_tlb_status_prv; // @[core.scala:51:7]
wire io_ptw_tlb_status_v_0 = io_ptw_tlb_status_v; // @[core.scala:51:7]
wire io_ptw_tlb_status_sd_0 = io_ptw_tlb_status_sd; // @[core.scala:51:7]
wire io_ptw_tlb_status_mpv_0 = io_ptw_tlb_status_mpv; // @[core.scala:51:7]
wire io_ptw_tlb_status_gva_0 = io_ptw_tlb_status_gva; // @[core.scala:51:7]
wire io_ptw_tlb_status_tsr_0 = io_ptw_tlb_status_tsr; // @[core.scala:51:7]
wire io_ptw_tlb_status_tw_0 = io_ptw_tlb_status_tw; // @[core.scala:51:7]
wire io_ptw_tlb_status_tvm_0 = io_ptw_tlb_status_tvm; // @[core.scala:51:7]
wire io_ptw_tlb_status_mxr_0 = io_ptw_tlb_status_mxr; // @[core.scala:51:7]
wire io_ptw_tlb_status_sum_0 = io_ptw_tlb_status_sum; // @[core.scala:51:7]
wire io_ptw_tlb_status_mprv_0 = io_ptw_tlb_status_mprv; // @[core.scala:51:7]
wire [1:0] io_ptw_tlb_status_fs_0 = io_ptw_tlb_status_fs; // @[core.scala:51:7]
wire [1:0] io_ptw_tlb_status_mpp_0 = io_ptw_tlb_status_mpp; // @[core.scala:51:7]
wire io_ptw_tlb_status_spp_0 = io_ptw_tlb_status_spp; // @[core.scala:51:7]
wire io_ptw_tlb_status_mpie_0 = io_ptw_tlb_status_mpie; // @[core.scala:51:7]
wire io_ptw_tlb_status_spie_0 = io_ptw_tlb_status_spie; // @[core.scala:51:7]
wire io_ptw_tlb_status_mie_0 = io_ptw_tlb_status_mie; // @[core.scala:51:7]
wire io_ptw_tlb_status_sie_0 = io_ptw_tlb_status_sie; // @[core.scala:51:7]
wire io_ptw_tlb_pmp_0_cfg_l_0 = io_ptw_tlb_pmp_0_cfg_l; // @[core.scala:51:7]
wire [1:0] io_ptw_tlb_pmp_0_cfg_a_0 = io_ptw_tlb_pmp_0_cfg_a; // @[core.scala:51:7]
wire io_ptw_tlb_pmp_0_cfg_x_0 = io_ptw_tlb_pmp_0_cfg_x; // @[core.scala:51:7]
wire io_ptw_tlb_pmp_0_cfg_w_0 = io_ptw_tlb_pmp_0_cfg_w; // @[core.scala:51:7]
wire io_ptw_tlb_pmp_0_cfg_r_0 = io_ptw_tlb_pmp_0_cfg_r; // @[core.scala:51:7]
wire [29:0] io_ptw_tlb_pmp_0_addr_0 = io_ptw_tlb_pmp_0_addr; // @[core.scala:51:7]
wire [31:0] io_ptw_tlb_pmp_0_mask_0 = io_ptw_tlb_pmp_0_mask; // @[core.scala:51:7]
wire io_ptw_tlb_pmp_1_cfg_l_0 = io_ptw_tlb_pmp_1_cfg_l; // @[core.scala:51:7]
wire [1:0] io_ptw_tlb_pmp_1_cfg_a_0 = io_ptw_tlb_pmp_1_cfg_a; // @[core.scala:51:7]
wire io_ptw_tlb_pmp_1_cfg_x_0 = io_ptw_tlb_pmp_1_cfg_x; // @[core.scala:51:7]
wire io_ptw_tlb_pmp_1_cfg_w_0 = io_ptw_tlb_pmp_1_cfg_w; // @[core.scala:51:7]
wire io_ptw_tlb_pmp_1_cfg_r_0 = io_ptw_tlb_pmp_1_cfg_r; // @[core.scala:51:7]
wire [29:0] io_ptw_tlb_pmp_1_addr_0 = io_ptw_tlb_pmp_1_addr; // @[core.scala:51:7]
wire [31:0] io_ptw_tlb_pmp_1_mask_0 = io_ptw_tlb_pmp_1_mask; // @[core.scala:51:7]
wire io_ptw_tlb_pmp_2_cfg_l_0 = io_ptw_tlb_pmp_2_cfg_l; // @[core.scala:51:7]
wire [1:0] io_ptw_tlb_pmp_2_cfg_a_0 = io_ptw_tlb_pmp_2_cfg_a; // @[core.scala:51:7]
wire io_ptw_tlb_pmp_2_cfg_x_0 = io_ptw_tlb_pmp_2_cfg_x; // @[core.scala:51:7]
wire io_ptw_tlb_pmp_2_cfg_w_0 = io_ptw_tlb_pmp_2_cfg_w; // @[core.scala:51:7]
wire io_ptw_tlb_pmp_2_cfg_r_0 = io_ptw_tlb_pmp_2_cfg_r; // @[core.scala:51:7]
wire [29:0] io_ptw_tlb_pmp_2_addr_0 = io_ptw_tlb_pmp_2_addr; // @[core.scala:51:7]
wire [31:0] io_ptw_tlb_pmp_2_mask_0 = io_ptw_tlb_pmp_2_mask; // @[core.scala:51:7]
wire io_ptw_tlb_pmp_3_cfg_l_0 = io_ptw_tlb_pmp_3_cfg_l; // @[core.scala:51:7]
wire [1:0] io_ptw_tlb_pmp_3_cfg_a_0 = io_ptw_tlb_pmp_3_cfg_a; // @[core.scala:51:7]
wire io_ptw_tlb_pmp_3_cfg_x_0 = io_ptw_tlb_pmp_3_cfg_x; // @[core.scala:51:7]
wire io_ptw_tlb_pmp_3_cfg_w_0 = io_ptw_tlb_pmp_3_cfg_w; // @[core.scala:51:7]
wire io_ptw_tlb_pmp_3_cfg_r_0 = io_ptw_tlb_pmp_3_cfg_r; // @[core.scala:51:7]
wire [29:0] io_ptw_tlb_pmp_3_addr_0 = io_ptw_tlb_pmp_3_addr; // @[core.scala:51:7]
wire [31:0] io_ptw_tlb_pmp_3_mask_0 = io_ptw_tlb_pmp_3_mask; // @[core.scala:51:7]
wire io_ptw_tlb_pmp_4_cfg_l_0 = io_ptw_tlb_pmp_4_cfg_l; // @[core.scala:51:7]
wire [1:0] io_ptw_tlb_pmp_4_cfg_a_0 = io_ptw_tlb_pmp_4_cfg_a; // @[core.scala:51:7]
wire io_ptw_tlb_pmp_4_cfg_x_0 = io_ptw_tlb_pmp_4_cfg_x; // @[core.scala:51:7]
wire io_ptw_tlb_pmp_4_cfg_w_0 = io_ptw_tlb_pmp_4_cfg_w; // @[core.scala:51:7]
wire io_ptw_tlb_pmp_4_cfg_r_0 = io_ptw_tlb_pmp_4_cfg_r; // @[core.scala:51:7]
wire [29:0] io_ptw_tlb_pmp_4_addr_0 = io_ptw_tlb_pmp_4_addr; // @[core.scala:51:7]
wire [31:0] io_ptw_tlb_pmp_4_mask_0 = io_ptw_tlb_pmp_4_mask; // @[core.scala:51:7]
wire io_ptw_tlb_pmp_5_cfg_l_0 = io_ptw_tlb_pmp_5_cfg_l; // @[core.scala:51:7]
wire [1:0] io_ptw_tlb_pmp_5_cfg_a_0 = io_ptw_tlb_pmp_5_cfg_a; // @[core.scala:51:7]
wire io_ptw_tlb_pmp_5_cfg_x_0 = io_ptw_tlb_pmp_5_cfg_x; // @[core.scala:51:7]
wire io_ptw_tlb_pmp_5_cfg_w_0 = io_ptw_tlb_pmp_5_cfg_w; // @[core.scala:51:7]
wire io_ptw_tlb_pmp_5_cfg_r_0 = io_ptw_tlb_pmp_5_cfg_r; // @[core.scala:51:7]
wire [29:0] io_ptw_tlb_pmp_5_addr_0 = io_ptw_tlb_pmp_5_addr; // @[core.scala:51:7]
wire [31:0] io_ptw_tlb_pmp_5_mask_0 = io_ptw_tlb_pmp_5_mask; // @[core.scala:51:7]
wire io_ptw_tlb_pmp_6_cfg_l_0 = io_ptw_tlb_pmp_6_cfg_l; // @[core.scala:51:7]
wire [1:0] io_ptw_tlb_pmp_6_cfg_a_0 = io_ptw_tlb_pmp_6_cfg_a; // @[core.scala:51:7]
wire io_ptw_tlb_pmp_6_cfg_x_0 = io_ptw_tlb_pmp_6_cfg_x; // @[core.scala:51:7]
wire io_ptw_tlb_pmp_6_cfg_w_0 = io_ptw_tlb_pmp_6_cfg_w; // @[core.scala:51:7]
wire io_ptw_tlb_pmp_6_cfg_r_0 = io_ptw_tlb_pmp_6_cfg_r; // @[core.scala:51:7]
wire [29:0] io_ptw_tlb_pmp_6_addr_0 = io_ptw_tlb_pmp_6_addr; // @[core.scala:51:7]
wire [31:0] io_ptw_tlb_pmp_6_mask_0 = io_ptw_tlb_pmp_6_mask; // @[core.scala:51:7]
wire io_ptw_tlb_pmp_7_cfg_l_0 = io_ptw_tlb_pmp_7_cfg_l; // @[core.scala:51:7]
wire [1:0] io_ptw_tlb_pmp_7_cfg_a_0 = io_ptw_tlb_pmp_7_cfg_a; // @[core.scala:51:7]
wire io_ptw_tlb_pmp_7_cfg_x_0 = io_ptw_tlb_pmp_7_cfg_x; // @[core.scala:51:7]
wire io_ptw_tlb_pmp_7_cfg_w_0 = io_ptw_tlb_pmp_7_cfg_w; // @[core.scala:51:7]
wire io_ptw_tlb_pmp_7_cfg_r_0 = io_ptw_tlb_pmp_7_cfg_r; // @[core.scala:51:7]
wire [29:0] io_ptw_tlb_pmp_7_addr_0 = io_ptw_tlb_pmp_7_addr; // @[core.scala:51:7]
wire [31:0] io_ptw_tlb_pmp_7_mask_0 = io_ptw_tlb_pmp_7_mask; // @[core.scala:51:7]
wire coreMonitorBundle_clock = clock; // @[core.scala:1405:31]
wire coreMonitorBundle_reset = reset; // @[core.scala:1405:31]
wire [6:0] io_ifu_fetchpacket_bits_uops_0_bits_uopc = 7'h0; // @[core.scala:51:7]
wire [6:0] io_ifu_fetchpacket_bits_uops_0_bits_rob_idx = 7'h0; // @[core.scala:51:7]
wire [6:0] io_ifu_fetchpacket_bits_uops_0_bits_pdst = 7'h0; // @[core.scala:51:7]
wire [6:0] io_ifu_fetchpacket_bits_uops_0_bits_prs1 = 7'h0; // @[core.scala:51:7]
wire [6:0] io_ifu_fetchpacket_bits_uops_0_bits_prs2 = 7'h0; // @[core.scala:51:7]
wire [6:0] io_ifu_fetchpacket_bits_uops_0_bits_prs3 = 7'h0; // @[core.scala:51:7]
wire [6:0] io_ifu_fetchpacket_bits_uops_0_bits_stale_pdst = 7'h0; // @[core.scala:51:7]
wire [6:0] io_ifu_fetchpacket_bits_uops_1_bits_uopc = 7'h0; // @[core.scala:51:7]
wire [6:0] io_ifu_fetchpacket_bits_uops_1_bits_rob_idx = 7'h0; // @[core.scala:51:7]
wire [6:0] io_ifu_fetchpacket_bits_uops_1_bits_pdst = 7'h0; // @[core.scala:51:7]
wire [6:0] io_ifu_fetchpacket_bits_uops_1_bits_prs1 = 7'h0; // @[core.scala:51:7]
wire [6:0] io_ifu_fetchpacket_bits_uops_1_bits_prs2 = 7'h0; // @[core.scala:51:7]
wire [6:0] io_ifu_fetchpacket_bits_uops_1_bits_prs3 = 7'h0; // @[core.scala:51:7]
wire [6:0] io_ifu_fetchpacket_bits_uops_1_bits_stale_pdst = 7'h0; // @[core.scala:51:7]
wire [6:0] io_ifu_fetchpacket_bits_uops_2_bits_uopc = 7'h0; // @[core.scala:51:7]
wire [6:0] io_ifu_fetchpacket_bits_uops_2_bits_rob_idx = 7'h0; // @[core.scala:51:7]
wire [6:0] io_ifu_fetchpacket_bits_uops_2_bits_pdst = 7'h0; // @[core.scala:51:7]
wire [6:0] io_ifu_fetchpacket_bits_uops_2_bits_prs1 = 7'h0; // @[core.scala:51:7]
wire [6:0] io_ifu_fetchpacket_bits_uops_2_bits_prs2 = 7'h0; // @[core.scala:51:7]
wire [6:0] io_ifu_fetchpacket_bits_uops_2_bits_prs3 = 7'h0; // @[core.scala:51:7]
wire [6:0] io_ifu_fetchpacket_bits_uops_2_bits_stale_pdst = 7'h0; // @[core.scala:51:7]
wire [6:0] io_rocc_cmd_bits_inst_funct = 7'h0; // @[core.scala:51:7]
wire [6:0] io_rocc_cmd_bits_inst_opcode = 7'h0; // @[core.scala:51:7]
wire [6:0] io_rocc_mem_req_bits_tag = 7'h0; // @[core.scala:51:7]
wire [6:0] io_rocc_mem_resp_bits_tag = 7'h0; // @[core.scala:51:7]
wire [6:0] io_lsu_exe_0_req_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:51:7]
wire [6:0] io_lsu_exe_0_req_bits_fflags_bits_uop_rob_idx = 7'h0; // @[core.scala:51:7]
wire [6:0] io_lsu_exe_0_req_bits_fflags_bits_uop_pdst = 7'h0; // @[core.scala:51:7]
wire [6:0] io_lsu_exe_0_req_bits_fflags_bits_uop_prs1 = 7'h0; // @[core.scala:51:7]
wire [6:0] io_lsu_exe_0_req_bits_fflags_bits_uop_prs2 = 7'h0; // @[core.scala:51:7]
wire [6:0] io_lsu_exe_0_req_bits_fflags_bits_uop_prs3 = 7'h0; // @[core.scala:51:7]
wire [6:0] io_lsu_exe_0_req_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[core.scala:51:7]
wire [6:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:51:7]
wire [6:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_rob_idx = 7'h0; // @[core.scala:51:7]
wire [6:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_pdst = 7'h0; // @[core.scala:51:7]
wire [6:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_prs1 = 7'h0; // @[core.scala:51:7]
wire [6:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_prs2 = 7'h0; // @[core.scala:51:7]
wire [6:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_prs3 = 7'h0; // @[core.scala:51:7]
wire [6:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[core.scala:51:7]
wire [6:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:51:7]
wire [6:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_rob_idx = 7'h0; // @[core.scala:51:7]
wire [6:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_pdst = 7'h0; // @[core.scala:51:7]
wire [6:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_prs1 = 7'h0; // @[core.scala:51:7]
wire [6:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_prs2 = 7'h0; // @[core.scala:51:7]
wire [6:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_prs3 = 7'h0; // @[core.scala:51:7]
wire [6:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[core.scala:51:7]
wire [6:0] int_iss_wakeups_1_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_1_bits_fflags_bits_uop_rob_idx = 7'h0; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_1_bits_fflags_bits_uop_pdst = 7'h0; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_1_bits_fflags_bits_uop_prs1 = 7'h0; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_1_bits_fflags_bits_uop_prs2 = 7'h0; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_1_bits_fflags_bits_uop_prs3 = 7'h0; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_1_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_2_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_2_bits_fflags_bits_uop_rob_idx = 7'h0; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_2_bits_fflags_bits_uop_pdst = 7'h0; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_2_bits_fflags_bits_uop_prs1 = 7'h0; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_2_bits_fflags_bits_uop_prs2 = 7'h0; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_2_bits_fflags_bits_uop_prs3 = 7'h0; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_2_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_3_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_3_bits_fflags_bits_uop_rob_idx = 7'h0; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_3_bits_fflags_bits_uop_pdst = 7'h0; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_3_bits_fflags_bits_uop_prs1 = 7'h0; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_3_bits_fflags_bits_uop_prs2 = 7'h0; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_3_bits_fflags_bits_uop_prs3 = 7'h0; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_3_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_4_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_4_bits_fflags_bits_uop_rob_idx = 7'h0; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_4_bits_fflags_bits_uop_pdst = 7'h0; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_4_bits_fflags_bits_uop_prs1 = 7'h0; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_4_bits_fflags_bits_uop_prs2 = 7'h0; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_4_bits_fflags_bits_uop_prs3 = 7'h0; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_4_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_5_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_5_bits_fflags_bits_uop_rob_idx = 7'h0; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_5_bits_fflags_bits_uop_pdst = 7'h0; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_5_bits_fflags_bits_uop_prs1 = 7'h0; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_5_bits_fflags_bits_uop_prs2 = 7'h0; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_5_bits_fflags_bits_uop_prs3 = 7'h0; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_5_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_6_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_6_bits_fflags_bits_uop_rob_idx = 7'h0; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_6_bits_fflags_bits_uop_pdst = 7'h0; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_6_bits_fflags_bits_uop_prs1 = 7'h0; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_6_bits_fflags_bits_uop_prs2 = 7'h0; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_6_bits_fflags_bits_uop_prs3 = 7'h0; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_6_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[core.scala:147:30]
wire [6:0] int_ren_wakeups_1_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_1_bits_fflags_bits_uop_rob_idx = 7'h0; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_1_bits_fflags_bits_uop_pdst = 7'h0; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_1_bits_fflags_bits_uop_prs1 = 7'h0; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_1_bits_fflags_bits_uop_prs2 = 7'h0; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_1_bits_fflags_bits_uop_prs3 = 7'h0; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_1_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_2_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_2_bits_fflags_bits_uop_rob_idx = 7'h0; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_2_bits_fflags_bits_uop_pdst = 7'h0; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_2_bits_fflags_bits_uop_prs1 = 7'h0; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_2_bits_fflags_bits_uop_prs2 = 7'h0; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_2_bits_fflags_bits_uop_prs3 = 7'h0; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_2_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_3_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_3_bits_fflags_bits_uop_rob_idx = 7'h0; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_3_bits_fflags_bits_uop_pdst = 7'h0; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_3_bits_fflags_bits_uop_prs1 = 7'h0; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_3_bits_fflags_bits_uop_prs2 = 7'h0; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_3_bits_fflags_bits_uop_prs3 = 7'h0; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_3_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_4_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_4_bits_fflags_bits_uop_rob_idx = 7'h0; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_4_bits_fflags_bits_uop_pdst = 7'h0; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_4_bits_fflags_bits_uop_prs1 = 7'h0; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_4_bits_fflags_bits_uop_prs2 = 7'h0; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_4_bits_fflags_bits_uop_prs3 = 7'h0; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_4_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_5_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_5_bits_fflags_bits_uop_rob_idx = 7'h0; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_5_bits_fflags_bits_uop_pdst = 7'h0; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_5_bits_fflags_bits_uop_prs1 = 7'h0; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_5_bits_fflags_bits_uop_prs2 = 7'h0; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_5_bits_fflags_bits_uop_prs3 = 7'h0; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_5_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_6_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_6_bits_fflags_bits_uop_rob_idx = 7'h0; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_6_bits_fflags_bits_uop_pdst = 7'h0; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_6_bits_fflags_bits_uop_prs1 = 7'h0; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_6_bits_fflags_bits_uop_prs2 = 7'h0; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_6_bits_fflags_bits_uop_prs3 = 7'h0; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_6_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[core.scala:148:30]
wire [6:0] pred_wakeup_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:149:26]
wire [6:0] pred_wakeup_bits_fflags_bits_uop_rob_idx = 7'h0; // @[core.scala:149:26]
wire [6:0] pred_wakeup_bits_fflags_bits_uop_pdst = 7'h0; // @[core.scala:149:26]
wire [6:0] pred_wakeup_bits_fflags_bits_uop_prs1 = 7'h0; // @[core.scala:149:26]
wire [6:0] pred_wakeup_bits_fflags_bits_uop_prs2 = 7'h0; // @[core.scala:149:26]
wire [6:0] pred_wakeup_bits_fflags_bits_uop_prs3 = 7'h0; // @[core.scala:149:26]
wire [6:0] pred_wakeup_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[core.scala:149:26]
wire [6:0] dec_uops_0_rob_idx = 7'h0; // @[core.scala:158:24]
wire [6:0] dec_uops_0_pdst = 7'h0; // @[core.scala:158:24]
wire [6:0] dec_uops_0_prs1 = 7'h0; // @[core.scala:158:24]
wire [6:0] dec_uops_0_prs2 = 7'h0; // @[core.scala:158:24]
wire [6:0] dec_uops_0_prs3 = 7'h0; // @[core.scala:158:24]
wire [6:0] dec_uops_0_stale_pdst = 7'h0; // @[core.scala:158:24]
wire [6:0] dec_uops_1_rob_idx = 7'h0; // @[core.scala:158:24]
wire [6:0] dec_uops_1_pdst = 7'h0; // @[core.scala:158:24]
wire [6:0] dec_uops_1_prs1 = 7'h0; // @[core.scala:158:24]
wire [6:0] dec_uops_1_prs2 = 7'h0; // @[core.scala:158:24]
wire [6:0] dec_uops_1_prs3 = 7'h0; // @[core.scala:158:24]
wire [6:0] dec_uops_1_stale_pdst = 7'h0; // @[core.scala:158:24]
wire [6:0] dec_uops_2_rob_idx = 7'h0; // @[core.scala:158:24]
wire [6:0] dec_uops_2_pdst = 7'h0; // @[core.scala:158:24]
wire [6:0] dec_uops_2_prs1 = 7'h0; // @[core.scala:158:24]
wire [6:0] dec_uops_2_prs2 = 7'h0; // @[core.scala:158:24]
wire [6:0] dec_uops_2_prs3 = 7'h0; // @[core.scala:158:24]
wire [6:0] dec_uops_2_stale_pdst = 7'h0; // @[core.scala:158:24]
wire [6:0] bypasses_0_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:174:24]
wire [6:0] bypasses_0_bits_fflags_bits_uop_rob_idx = 7'h0; // @[core.scala:174:24]
wire [6:0] bypasses_0_bits_fflags_bits_uop_pdst = 7'h0; // @[core.scala:174:24]
wire [6:0] bypasses_0_bits_fflags_bits_uop_prs1 = 7'h0; // @[core.scala:174:24]
wire [6:0] bypasses_0_bits_fflags_bits_uop_prs2 = 7'h0; // @[core.scala:174:24]
wire [6:0] bypasses_0_bits_fflags_bits_uop_prs3 = 7'h0; // @[core.scala:174:24]
wire [6:0] bypasses_0_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[core.scala:174:24]
wire [6:0] bypasses_1_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:174:24]
wire [6:0] bypasses_1_bits_fflags_bits_uop_rob_idx = 7'h0; // @[core.scala:174:24]
wire [6:0] bypasses_1_bits_fflags_bits_uop_pdst = 7'h0; // @[core.scala:174:24]
wire [6:0] bypasses_1_bits_fflags_bits_uop_prs1 = 7'h0; // @[core.scala:174:24]
wire [6:0] bypasses_1_bits_fflags_bits_uop_prs2 = 7'h0; // @[core.scala:174:24]
wire [6:0] bypasses_1_bits_fflags_bits_uop_prs3 = 7'h0; // @[core.scala:174:24]
wire [6:0] bypasses_1_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[core.scala:174:24]
wire [6:0] bypasses_2_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:174:24]
wire [6:0] bypasses_2_bits_fflags_bits_uop_rob_idx = 7'h0; // @[core.scala:174:24]
wire [6:0] bypasses_2_bits_fflags_bits_uop_pdst = 7'h0; // @[core.scala:174:24]
wire [6:0] bypasses_2_bits_fflags_bits_uop_prs1 = 7'h0; // @[core.scala:174:24]
wire [6:0] bypasses_2_bits_fflags_bits_uop_prs2 = 7'h0; // @[core.scala:174:24]
wire [6:0] bypasses_2_bits_fflags_bits_uop_prs3 = 7'h0; // @[core.scala:174:24]
wire [6:0] bypasses_2_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[core.scala:174:24]
wire [6:0] bypasses_3_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:174:24]
wire [6:0] bypasses_3_bits_fflags_bits_uop_rob_idx = 7'h0; // @[core.scala:174:24]
wire [6:0] bypasses_3_bits_fflags_bits_uop_pdst = 7'h0; // @[core.scala:174:24]
wire [6:0] bypasses_3_bits_fflags_bits_uop_prs1 = 7'h0; // @[core.scala:174:24]
wire [6:0] bypasses_3_bits_fflags_bits_uop_prs2 = 7'h0; // @[core.scala:174:24]
wire [6:0] bypasses_3_bits_fflags_bits_uop_prs3 = 7'h0; // @[core.scala:174:24]
wire [6:0] bypasses_3_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[core.scala:174:24]
wire [6:0] bypasses_4_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:174:24]
wire [6:0] bypasses_4_bits_fflags_bits_uop_rob_idx = 7'h0; // @[core.scala:174:24]
wire [6:0] bypasses_4_bits_fflags_bits_uop_pdst = 7'h0; // @[core.scala:174:24]
wire [6:0] bypasses_4_bits_fflags_bits_uop_prs1 = 7'h0; // @[core.scala:174:24]
wire [6:0] bypasses_4_bits_fflags_bits_uop_prs2 = 7'h0; // @[core.scala:174:24]
wire [6:0] bypasses_4_bits_fflags_bits_uop_prs3 = 7'h0; // @[core.scala:174:24]
wire [6:0] bypasses_4_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[core.scala:174:24]
wire [6:0] pred_bypasses_0_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:175:27]
wire [6:0] pred_bypasses_0_bits_fflags_bits_uop_rob_idx = 7'h0; // @[core.scala:175:27]
wire [6:0] pred_bypasses_0_bits_fflags_bits_uop_pdst = 7'h0; // @[core.scala:175:27]
wire [6:0] pred_bypasses_0_bits_fflags_bits_uop_prs1 = 7'h0; // @[core.scala:175:27]
wire [6:0] pred_bypasses_0_bits_fflags_bits_uop_prs2 = 7'h0; // @[core.scala:175:27]
wire [6:0] pred_bypasses_0_bits_fflags_bits_uop_prs3 = 7'h0; // @[core.scala:175:27]
wire [6:0] pred_bypasses_0_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[core.scala:175:27]
wire [6:0] p_uop_uopc = 7'h0; // @[consts.scala:269:19]
wire [6:0] p_uop_rob_idx = 7'h0; // @[consts.scala:269:19]
wire [6:0] p_uop_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] p_uop_prs1 = 7'h0; // @[consts.scala:269:19]
wire [6:0] p_uop_prs2 = 7'h0; // @[consts.scala:269:19]
wire [6:0] p_uop_prs3 = 7'h0; // @[consts.scala:269:19]
wire [6:0] p_uop_stale_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] p_uop_1_uopc = 7'h0; // @[consts.scala:269:19]
wire [6:0] p_uop_1_rob_idx = 7'h0; // @[consts.scala:269:19]
wire [6:0] p_uop_1_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] p_uop_1_prs1 = 7'h0; // @[consts.scala:269:19]
wire [6:0] p_uop_1_prs2 = 7'h0; // @[consts.scala:269:19]
wire [6:0] p_uop_1_prs3 = 7'h0; // @[consts.scala:269:19]
wire [6:0] p_uop_1_stale_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] p_uop_2_uopc = 7'h0; // @[consts.scala:269:19]
wire [6:0] p_uop_2_rob_idx = 7'h0; // @[consts.scala:269:19]
wire [6:0] p_uop_2_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] p_uop_2_prs1 = 7'h0; // @[consts.scala:269:19]
wire [6:0] p_uop_2_prs2 = 7'h0; // @[consts.scala:269:19]
wire [6:0] p_uop_2_prs3 = 7'h0; // @[consts.scala:269:19]
wire [6:0] p_uop_2_stale_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] fast_wakeup_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:814:29]
wire [6:0] fast_wakeup_bits_fflags_bits_uop_rob_idx = 7'h0; // @[core.scala:814:29]
wire [6:0] fast_wakeup_bits_fflags_bits_uop_pdst = 7'h0; // @[core.scala:814:29]
wire [6:0] fast_wakeup_bits_fflags_bits_uop_prs1 = 7'h0; // @[core.scala:814:29]
wire [6:0] fast_wakeup_bits_fflags_bits_uop_prs2 = 7'h0; // @[core.scala:814:29]
wire [6:0] fast_wakeup_bits_fflags_bits_uop_prs3 = 7'h0; // @[core.scala:814:29]
wire [6:0] fast_wakeup_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[core.scala:814:29]
wire [6:0] slow_wakeup_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:815:29]
wire [6:0] slow_wakeup_bits_fflags_bits_uop_rob_idx = 7'h0; // @[core.scala:815:29]
wire [6:0] slow_wakeup_bits_fflags_bits_uop_pdst = 7'h0; // @[core.scala:815:29]
wire [6:0] slow_wakeup_bits_fflags_bits_uop_prs1 = 7'h0; // @[core.scala:815:29]
wire [6:0] slow_wakeup_bits_fflags_bits_uop_prs2 = 7'h0; // @[core.scala:815:29]
wire [6:0] slow_wakeup_bits_fflags_bits_uop_prs3 = 7'h0; // @[core.scala:815:29]
wire [6:0] slow_wakeup_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[core.scala:815:29]
wire [6:0] fast_wakeup_1_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:814:29]
wire [6:0] fast_wakeup_1_bits_fflags_bits_uop_rob_idx = 7'h0; // @[core.scala:814:29]
wire [6:0] fast_wakeup_1_bits_fflags_bits_uop_pdst = 7'h0; // @[core.scala:814:29]
wire [6:0] fast_wakeup_1_bits_fflags_bits_uop_prs1 = 7'h0; // @[core.scala:814:29]
wire [6:0] fast_wakeup_1_bits_fflags_bits_uop_prs2 = 7'h0; // @[core.scala:814:29]
wire [6:0] fast_wakeup_1_bits_fflags_bits_uop_prs3 = 7'h0; // @[core.scala:814:29]
wire [6:0] fast_wakeup_1_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[core.scala:814:29]
wire [6:0] slow_wakeup_1_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:815:29]
wire [6:0] slow_wakeup_1_bits_fflags_bits_uop_rob_idx = 7'h0; // @[core.scala:815:29]
wire [6:0] slow_wakeup_1_bits_fflags_bits_uop_pdst = 7'h0; // @[core.scala:815:29]
wire [6:0] slow_wakeup_1_bits_fflags_bits_uop_prs1 = 7'h0; // @[core.scala:815:29]
wire [6:0] slow_wakeup_1_bits_fflags_bits_uop_prs2 = 7'h0; // @[core.scala:815:29]
wire [6:0] slow_wakeup_1_bits_fflags_bits_uop_prs3 = 7'h0; // @[core.scala:815:29]
wire [6:0] slow_wakeup_1_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[core.scala:815:29]
wire [6:0] fast_wakeup_2_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:814:29]
wire [6:0] fast_wakeup_2_bits_fflags_bits_uop_rob_idx = 7'h0; // @[core.scala:814:29]
wire [6:0] fast_wakeup_2_bits_fflags_bits_uop_pdst = 7'h0; // @[core.scala:814:29]
wire [6:0] fast_wakeup_2_bits_fflags_bits_uop_prs1 = 7'h0; // @[core.scala:814:29]
wire [6:0] fast_wakeup_2_bits_fflags_bits_uop_prs2 = 7'h0; // @[core.scala:814:29]
wire [6:0] fast_wakeup_2_bits_fflags_bits_uop_prs3 = 7'h0; // @[core.scala:814:29]
wire [6:0] fast_wakeup_2_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[core.scala:814:29]
wire [6:0] slow_wakeup_2_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:815:29]
wire [6:0] slow_wakeup_2_bits_fflags_bits_uop_rob_idx = 7'h0; // @[core.scala:815:29]
wire [6:0] slow_wakeup_2_bits_fflags_bits_uop_pdst = 7'h0; // @[core.scala:815:29]
wire [6:0] slow_wakeup_2_bits_fflags_bits_uop_prs1 = 7'h0; // @[core.scala:815:29]
wire [6:0] slow_wakeup_2_bits_fflags_bits_uop_prs2 = 7'h0; // @[core.scala:815:29]
wire [6:0] slow_wakeup_2_bits_fflags_bits_uop_prs3 = 7'h0; // @[core.scala:815:29]
wire [6:0] slow_wakeup_2_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[core.scala:815:29]
wire [2:0] io_ifu_fetchpacket_bits_uops_0_bits_iq_type = 3'h0; // @[core.scala:51:7]
wire [2:0] io_ifu_fetchpacket_bits_uops_0_bits_ctrl_op2_sel = 3'h0; // @[core.scala:51:7]
wire [2:0] io_ifu_fetchpacket_bits_uops_0_bits_ctrl_imm_sel = 3'h0; // @[core.scala:51:7]
wire [2:0] io_ifu_fetchpacket_bits_uops_0_bits_ctrl_csr_cmd = 3'h0; // @[core.scala:51:7]
wire [2:0] io_ifu_fetchpacket_bits_uops_1_bits_iq_type = 3'h0; // @[core.scala:51:7]
wire [2:0] io_ifu_fetchpacket_bits_uops_1_bits_ctrl_op2_sel = 3'h0; // @[core.scala:51:7]
wire [2:0] io_ifu_fetchpacket_bits_uops_1_bits_ctrl_imm_sel = 3'h0; // @[core.scala:51:7]
wire [2:0] io_ifu_fetchpacket_bits_uops_1_bits_ctrl_csr_cmd = 3'h0; // @[core.scala:51:7]
wire [2:0] io_ifu_fetchpacket_bits_uops_2_bits_iq_type = 3'h0; // @[core.scala:51:7]
wire [2:0] io_ifu_fetchpacket_bits_uops_2_bits_ctrl_op2_sel = 3'h0; // @[core.scala:51:7]
wire [2:0] io_ifu_fetchpacket_bits_uops_2_bits_ctrl_imm_sel = 3'h0; // @[core.scala:51:7]
wire [2:0] io_ifu_fetchpacket_bits_uops_2_bits_ctrl_csr_cmd = 3'h0; // @[core.scala:51:7]
wire [2:0] io_lsu_exe_0_req_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:51:7]
wire [2:0] io_lsu_exe_0_req_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:51:7]
wire [2:0] io_lsu_exe_0_req_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:51:7]
wire [2:0] io_lsu_exe_0_req_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:51:7]
wire [2:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:51:7]
wire [2:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:51:7]
wire [2:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:51:7]
wire [2:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:51:7]
wire [2:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:51:7]
wire [2:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:51:7]
wire [2:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:51:7]
wire [2:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:51:7]
wire [2:0] io_trace_insns_0_priv = 3'h0; // @[core.scala:51:7]
wire [2:0] io_trace_insns_1_priv = 3'h0; // @[core.scala:51:7]
wire [2:0] io_trace_insns_2_priv = 3'h0; // @[core.scala:51:7]
wire [2:0] int_iss_wakeups_1_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_1_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_1_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_1_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_2_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_2_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_2_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_2_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_3_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_3_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_3_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_3_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_4_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_4_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_4_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_4_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_5_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_5_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_5_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_5_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_6_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_6_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_6_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_6_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:147:30]
wire [2:0] int_ren_wakeups_1_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_1_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_1_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_1_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_2_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_2_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_2_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_2_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_3_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_3_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_3_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_3_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_4_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_4_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_4_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_4_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_5_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_5_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_5_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_5_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_6_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_6_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_6_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_6_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:148:30]
wire [2:0] pred_wakeup_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:149:26]
wire [2:0] pred_wakeup_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:149:26]
wire [2:0] pred_wakeup_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:149:26]
wire [2:0] pred_wakeup_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:149:26]
wire [2:0] dec_uops_0_ctrl_op2_sel = 3'h0; // @[core.scala:158:24]
wire [2:0] dec_uops_0_ctrl_imm_sel = 3'h0; // @[core.scala:158:24]
wire [2:0] dec_uops_0_ctrl_csr_cmd = 3'h0; // @[core.scala:158:24]
wire [2:0] dec_uops_1_ctrl_op2_sel = 3'h0; // @[core.scala:158:24]
wire [2:0] dec_uops_1_ctrl_imm_sel = 3'h0; // @[core.scala:158:24]
wire [2:0] dec_uops_1_ctrl_csr_cmd = 3'h0; // @[core.scala:158:24]
wire [2:0] dec_uops_2_ctrl_op2_sel = 3'h0; // @[core.scala:158:24]
wire [2:0] dec_uops_2_ctrl_imm_sel = 3'h0; // @[core.scala:158:24]
wire [2:0] dec_uops_2_ctrl_csr_cmd = 3'h0; // @[core.scala:158:24]
wire [2:0] bypasses_0_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:174:24]
wire [2:0] bypasses_0_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:174:24]
wire [2:0] bypasses_0_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:174:24]
wire [2:0] bypasses_0_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:174:24]
wire [2:0] bypasses_1_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:174:24]
wire [2:0] bypasses_1_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:174:24]
wire [2:0] bypasses_1_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:174:24]
wire [2:0] bypasses_1_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:174:24]
wire [2:0] bypasses_2_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:174:24]
wire [2:0] bypasses_2_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:174:24]
wire [2:0] bypasses_2_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:174:24]
wire [2:0] bypasses_2_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:174:24]
wire [2:0] bypasses_3_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:174:24]
wire [2:0] bypasses_3_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:174:24]
wire [2:0] bypasses_3_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:174:24]
wire [2:0] bypasses_3_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:174:24]
wire [2:0] bypasses_4_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:174:24]
wire [2:0] bypasses_4_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:174:24]
wire [2:0] bypasses_4_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:174:24]
wire [2:0] bypasses_4_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:174:24]
wire [2:0] pred_bypasses_0_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:175:27]
wire [2:0] pred_bypasses_0_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:175:27]
wire [2:0] pred_bypasses_0_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:175:27]
wire [2:0] pred_bypasses_0_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:175:27]
wire [2:0] p_uop_iq_type = 3'h0; // @[consts.scala:269:19]
wire [2:0] p_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] p_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] p_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19]
wire [2:0] p_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] p_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] p_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18]
wire [2:0] p_uop_1_iq_type = 3'h0; // @[consts.scala:269:19]
wire [2:0] p_uop_1_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] p_uop_1_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] p_uop_1_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19]
wire [2:0] p_uop_cs_1_op2_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] p_uop_cs_1_imm_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] p_uop_cs_1_csr_cmd = 3'h0; // @[consts.scala:279:18]
wire [2:0] p_uop_2_iq_type = 3'h0; // @[consts.scala:269:19]
wire [2:0] p_uop_2_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] p_uop_2_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] p_uop_2_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19]
wire [2:0] p_uop_cs_2_op2_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] p_uop_cs_2_imm_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] p_uop_cs_2_csr_cmd = 3'h0; // @[consts.scala:279:18]
wire [2:0] fast_wakeup_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:814:29]
wire [2:0] fast_wakeup_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:814:29]
wire [2:0] fast_wakeup_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:814:29]
wire [2:0] fast_wakeup_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:814:29]
wire [2:0] slow_wakeup_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:815:29]
wire [2:0] slow_wakeup_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:815:29]
wire [2:0] slow_wakeup_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:815:29]
wire [2:0] slow_wakeup_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:815:29]
wire [2:0] fast_wakeup_1_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:814:29]
wire [2:0] fast_wakeup_1_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:814:29]
wire [2:0] fast_wakeup_1_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:814:29]
wire [2:0] fast_wakeup_1_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:814:29]
wire [2:0] slow_wakeup_1_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:815:29]
wire [2:0] slow_wakeup_1_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:815:29]
wire [2:0] slow_wakeup_1_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:815:29]
wire [2:0] slow_wakeup_1_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:815:29]
wire [2:0] fast_wakeup_2_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:814:29]
wire [2:0] fast_wakeup_2_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:814:29]
wire [2:0] fast_wakeup_2_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:814:29]
wire [2:0] fast_wakeup_2_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:814:29]
wire [2:0] slow_wakeup_2_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:815:29]
wire [2:0] slow_wakeup_2_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:815:29]
wire [2:0] slow_wakeup_2_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:815:29]
wire [2:0] slow_wakeup_2_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:815:29]
wire [2:0] coreMonitorBundle_priv_mode = 3'h0; // @[core.scala:1405:31]
wire [9:0] io_ifu_fetchpacket_bits_uops_0_bits_fu_code = 10'h0; // @[core.scala:51:7]
wire [9:0] io_ifu_fetchpacket_bits_uops_1_bits_fu_code = 10'h0; // @[core.scala:51:7]
wire [9:0] io_ifu_fetchpacket_bits_uops_2_bits_fu_code = 10'h0; // @[core.scala:51:7]
wire [9:0] io_lsu_exe_0_req_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:51:7]
wire [9:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:51:7]
wire [9:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:51:7]
wire [9:0] int_iss_wakeups_1_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:147:30]
wire [9:0] int_iss_wakeups_2_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:147:30]
wire [9:0] int_iss_wakeups_3_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:147:30]
wire [9:0] int_iss_wakeups_4_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:147:30]
wire [9:0] int_iss_wakeups_5_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:147:30]
wire [9:0] int_iss_wakeups_6_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:147:30]
wire [9:0] int_ren_wakeups_1_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:148:30]
wire [9:0] int_ren_wakeups_2_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:148:30]
wire [9:0] int_ren_wakeups_3_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:148:30]
wire [9:0] int_ren_wakeups_4_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:148:30]
wire [9:0] int_ren_wakeups_5_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:148:30]
wire [9:0] int_ren_wakeups_6_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:148:30]
wire [9:0] pred_wakeup_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:149:26]
wire [9:0] bypasses_0_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:174:24]
wire [9:0] bypasses_1_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:174:24]
wire [9:0] bypasses_2_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:174:24]
wire [9:0] bypasses_3_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:174:24]
wire [9:0] bypasses_4_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:174:24]
wire [9:0] pred_bypasses_0_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:175:27]
wire [9:0] p_uop_fu_code = 10'h0; // @[consts.scala:269:19]
wire [9:0] p_uop_1_fu_code = 10'h0; // @[consts.scala:269:19]
wire [9:0] p_uop_2_fu_code = 10'h0; // @[consts.scala:269:19]
wire [9:0] fast_wakeup_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:814:29]
wire [9:0] slow_wakeup_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:815:29]
wire [9:0] fast_wakeup_1_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:814:29]
wire [9:0] slow_wakeup_1_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:815:29]
wire [9:0] fast_wakeup_2_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:814:29]
wire [9:0] slow_wakeup_2_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:815:29]
wire [3:0] io_ifu_fetchpacket_bits_uops_0_bits_ctrl_br_type = 4'h0; // @[core.scala:51:7]
wire [3:0] io_ifu_fetchpacket_bits_uops_0_bits_br_tag = 4'h0; // @[core.scala:51:7]
wire [3:0] io_ifu_fetchpacket_bits_uops_1_bits_ctrl_br_type = 4'h0; // @[core.scala:51:7]
wire [3:0] io_ifu_fetchpacket_bits_uops_1_bits_br_tag = 4'h0; // @[core.scala:51:7]
wire [3:0] io_ifu_fetchpacket_bits_uops_2_bits_ctrl_br_type = 4'h0; // @[core.scala:51:7]
wire [3:0] io_ifu_fetchpacket_bits_uops_2_bits_br_tag = 4'h0; // @[core.scala:51:7]
wire [3:0] io_ptw_hgatp_mode = 4'h0; // @[core.scala:51:7]
wire [3:0] io_ptw_vsatp_mode = 4'h0; // @[core.scala:51:7]
wire [3:0] io_lsu_exe_0_req_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:51:7]
wire [3:0] io_lsu_exe_0_req_bits_fflags_bits_uop_br_tag = 4'h0; // @[core.scala:51:7]
wire [3:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:51:7]
wire [3:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_br_tag = 4'h0; // @[core.scala:51:7]
wire [3:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:51:7]
wire [3:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_br_tag = 4'h0; // @[core.scala:51:7]
wire [3:0] io_ptw_tlb_hgatp_mode = 4'h0; // @[core.scala:51:7]
wire [3:0] io_ptw_tlb_vsatp_mode = 4'h0; // @[core.scala:51:7]
wire [3:0] int_iss_wakeups_1_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:147:30]
wire [3:0] int_iss_wakeups_1_bits_fflags_bits_uop_br_tag = 4'h0; // @[core.scala:147:30]
wire [3:0] int_iss_wakeups_2_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:147:30]
wire [3:0] int_iss_wakeups_2_bits_fflags_bits_uop_br_tag = 4'h0; // @[core.scala:147:30]
wire [3:0] int_iss_wakeups_3_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:147:30]
wire [3:0] int_iss_wakeups_3_bits_fflags_bits_uop_br_tag = 4'h0; // @[core.scala:147:30]
wire [3:0] int_iss_wakeups_4_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:147:30]
wire [3:0] int_iss_wakeups_4_bits_fflags_bits_uop_br_tag = 4'h0; // @[core.scala:147:30]
wire [3:0] int_iss_wakeups_5_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:147:30]
wire [3:0] int_iss_wakeups_5_bits_fflags_bits_uop_br_tag = 4'h0; // @[core.scala:147:30]
wire [3:0] int_iss_wakeups_6_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:147:30]
wire [3:0] int_iss_wakeups_6_bits_fflags_bits_uop_br_tag = 4'h0; // @[core.scala:147:30]
wire [3:0] int_ren_wakeups_1_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:148:30]
wire [3:0] int_ren_wakeups_1_bits_fflags_bits_uop_br_tag = 4'h0; // @[core.scala:148:30]
wire [3:0] int_ren_wakeups_2_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:148:30]
wire [3:0] int_ren_wakeups_2_bits_fflags_bits_uop_br_tag = 4'h0; // @[core.scala:148:30]
wire [3:0] int_ren_wakeups_3_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:148:30]
wire [3:0] int_ren_wakeups_3_bits_fflags_bits_uop_br_tag = 4'h0; // @[core.scala:148:30]
wire [3:0] int_ren_wakeups_4_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:148:30]
wire [3:0] int_ren_wakeups_4_bits_fflags_bits_uop_br_tag = 4'h0; // @[core.scala:148:30]
wire [3:0] int_ren_wakeups_5_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:148:30]
wire [3:0] int_ren_wakeups_5_bits_fflags_bits_uop_br_tag = 4'h0; // @[core.scala:148:30]
wire [3:0] int_ren_wakeups_6_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:148:30]
wire [3:0] int_ren_wakeups_6_bits_fflags_bits_uop_br_tag = 4'h0; // @[core.scala:148:30]
wire [3:0] pred_wakeup_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:149:26]
wire [3:0] pred_wakeup_bits_fflags_bits_uop_br_tag = 4'h0; // @[core.scala:149:26]
wire [3:0] dec_uops_0_ctrl_br_type = 4'h0; // @[core.scala:158:24]
wire [3:0] dec_uops_1_ctrl_br_type = 4'h0; // @[core.scala:158:24]
wire [3:0] dec_uops_2_ctrl_br_type = 4'h0; // @[core.scala:158:24]
wire [3:0] bypasses_0_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:174:24]
wire [3:0] bypasses_0_bits_fflags_bits_uop_br_tag = 4'h0; // @[core.scala:174:24]
wire [3:0] bypasses_1_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:174:24]
wire [3:0] bypasses_1_bits_fflags_bits_uop_br_tag = 4'h0; // @[core.scala:174:24]
wire [3:0] bypasses_2_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:174:24]
wire [3:0] bypasses_2_bits_fflags_bits_uop_br_tag = 4'h0; // @[core.scala:174:24]
wire [3:0] bypasses_3_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:174:24]
wire [3:0] bypasses_3_bits_fflags_bits_uop_br_tag = 4'h0; // @[core.scala:174:24]
wire [3:0] bypasses_4_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:174:24]
wire [3:0] bypasses_4_bits_fflags_bits_uop_br_tag = 4'h0; // @[core.scala:174:24]
wire [3:0] pred_bypasses_0_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:175:27]
wire [3:0] pred_bypasses_0_bits_fflags_bits_uop_br_tag = 4'h0; // @[core.scala:175:27]
wire [3:0] p_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19]
wire [3:0] p_uop_br_tag = 4'h0; // @[consts.scala:269:19]
wire [3:0] p_uop_cs_br_type = 4'h0; // @[consts.scala:279:18]
wire [3:0] p_uop_1_ctrl_br_type = 4'h0; // @[consts.scala:269:19]
wire [3:0] p_uop_1_br_tag = 4'h0; // @[consts.scala:269:19]
wire [3:0] p_uop_cs_1_br_type = 4'h0; // @[consts.scala:279:18]
wire [3:0] p_uop_2_ctrl_br_type = 4'h0; // @[consts.scala:269:19]
wire [3:0] p_uop_2_br_tag = 4'h0; // @[consts.scala:269:19]
wire [3:0] p_uop_cs_2_br_type = 4'h0; // @[consts.scala:279:18]
wire [3:0] fast_wakeup_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:814:29]
wire [3:0] fast_wakeup_bits_fflags_bits_uop_br_tag = 4'h0; // @[core.scala:814:29]
wire [3:0] slow_wakeup_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:815:29]
wire [3:0] slow_wakeup_bits_fflags_bits_uop_br_tag = 4'h0; // @[core.scala:815:29]
wire [3:0] fast_wakeup_1_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:814:29]
wire [3:0] fast_wakeup_1_bits_fflags_bits_uop_br_tag = 4'h0; // @[core.scala:814:29]
wire [3:0] slow_wakeup_1_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:815:29]
wire [3:0] slow_wakeup_1_bits_fflags_bits_uop_br_tag = 4'h0; // @[core.scala:815:29]
wire [3:0] fast_wakeup_2_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:814:29]
wire [3:0] fast_wakeup_2_bits_fflags_bits_uop_br_tag = 4'h0; // @[core.scala:814:29]
wire [3:0] slow_wakeup_2_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:815:29]
wire [3:0] slow_wakeup_2_bits_fflags_bits_uop_br_tag = 4'h0; // @[core.scala:815:29]
wire [1:0] io_ifu_fetchpacket_bits_uops_0_bits_ctrl_op1_sel = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ifu_fetchpacket_bits_uops_0_bits_iw_state = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ifu_fetchpacket_bits_uops_0_bits_rxq_idx = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ifu_fetchpacket_bits_uops_0_bits_mem_size = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ifu_fetchpacket_bits_uops_0_bits_dst_rtype = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ifu_fetchpacket_bits_uops_0_bits_lrs1_rtype = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ifu_fetchpacket_bits_uops_0_bits_lrs2_rtype = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ifu_fetchpacket_bits_uops_0_bits_debug_tsrc = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ifu_fetchpacket_bits_uops_1_bits_ctrl_op1_sel = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ifu_fetchpacket_bits_uops_1_bits_iw_state = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ifu_fetchpacket_bits_uops_1_bits_rxq_idx = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ifu_fetchpacket_bits_uops_1_bits_mem_size = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ifu_fetchpacket_bits_uops_1_bits_dst_rtype = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ifu_fetchpacket_bits_uops_1_bits_lrs1_rtype = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ifu_fetchpacket_bits_uops_1_bits_lrs2_rtype = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ifu_fetchpacket_bits_uops_1_bits_debug_tsrc = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ifu_fetchpacket_bits_uops_2_bits_ctrl_op1_sel = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ifu_fetchpacket_bits_uops_2_bits_iw_state = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ifu_fetchpacket_bits_uops_2_bits_rxq_idx = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ifu_fetchpacket_bits_uops_2_bits_mem_size = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ifu_fetchpacket_bits_uops_2_bits_dst_rtype = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ifu_fetchpacket_bits_uops_2_bits_lrs1_rtype = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ifu_fetchpacket_bits_uops_2_bits_lrs2_rtype = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ifu_fetchpacket_bits_uops_2_bits_debug_tsrc = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ifu_status_xs = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ifu_status_vs = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ptw_status_xs = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ptw_status_vs = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ptw_hstatus_vsxl = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ptw_hstatus_zero3 = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ptw_hstatus_zero2 = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ptw_gstatus_dprv = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ptw_gstatus_prv = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ptw_gstatus_sxl = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ptw_gstatus_uxl = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ptw_gstatus_xs = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ptw_gstatus_fs = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ptw_gstatus_mpp = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ptw_gstatus_vs = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ptw_pmp_0_cfg_res = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ptw_pmp_1_cfg_res = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ptw_pmp_2_cfg_res = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ptw_pmp_3_cfg_res = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ptw_pmp_4_cfg_res = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ptw_pmp_5_cfg_res = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ptw_pmp_6_cfg_res = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ptw_pmp_7_cfg_res = 2'h0; // @[core.scala:51:7]
wire [1:0] io_rocc_cmd_bits_status_dprv = 2'h0; // @[core.scala:51:7]
wire [1:0] io_rocc_cmd_bits_status_prv = 2'h0; // @[core.scala:51:7]
wire [1:0] io_rocc_cmd_bits_status_sxl = 2'h0; // @[core.scala:51:7]
wire [1:0] io_rocc_cmd_bits_status_uxl = 2'h0; // @[core.scala:51:7]
wire [1:0] io_rocc_cmd_bits_status_xs = 2'h0; // @[core.scala:51:7]
wire [1:0] io_rocc_cmd_bits_status_fs = 2'h0; // @[core.scala:51:7]
wire [1:0] io_rocc_cmd_bits_status_mpp = 2'h0; // @[core.scala:51:7]
wire [1:0] io_rocc_cmd_bits_status_vs = 2'h0; // @[core.scala:51:7]
wire [1:0] io_rocc_mem_req_bits_size = 2'h0; // @[core.scala:51:7]
wire [1:0] io_rocc_mem_req_bits_dprv = 2'h0; // @[core.scala:51:7]
wire [1:0] io_rocc_mem_resp_bits_size = 2'h0; // @[core.scala:51:7]
wire [1:0] io_rocc_mem_resp_bits_dprv = 2'h0; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_req_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_req_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_req_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_req_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_req_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_req_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_req_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_req_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_req_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ptw_tlb_status_xs = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ptw_tlb_status_vs = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ptw_tlb_hstatus_vsxl = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ptw_tlb_hstatus_zero3 = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ptw_tlb_hstatus_zero2 = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ptw_tlb_gstatus_dprv = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ptw_tlb_gstatus_prv = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ptw_tlb_gstatus_sxl = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ptw_tlb_gstatus_uxl = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ptw_tlb_gstatus_xs = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ptw_tlb_gstatus_fs = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ptw_tlb_gstatus_mpp = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ptw_tlb_gstatus_vs = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ptw_tlb_pmp_0_cfg_res = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ptw_tlb_pmp_1_cfg_res = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ptw_tlb_pmp_2_cfg_res = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ptw_tlb_pmp_3_cfg_res = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ptw_tlb_pmp_4_cfg_res = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ptw_tlb_pmp_5_cfg_res = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ptw_tlb_pmp_6_cfg_res = 2'h0; // @[core.scala:51:7]
wire [1:0] io_ptw_tlb_pmp_7_cfg_res = 2'h0; // @[core.scala:51:7]
wire [1:0] int_iss_wakeups_1_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_1_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_1_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_1_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_1_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_1_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_1_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_1_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_1_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_2_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_2_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_2_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_2_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_2_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_2_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_2_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_2_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_2_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_3_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_3_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_3_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_3_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_3_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_3_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_3_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_3_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_3_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_4_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_4_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_4_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_4_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_4_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_4_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_4_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_4_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_4_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_5_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_5_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_5_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_5_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_5_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_5_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_5_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_5_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_5_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_6_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_6_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_6_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_6_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_6_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_6_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_6_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_6_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_6_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:147:30]
wire [1:0] int_ren_wakeups_1_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_1_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_1_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_1_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_1_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_1_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_1_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_1_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_1_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_2_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_2_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_2_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_2_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_2_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_2_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_2_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_2_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_2_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_3_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_3_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_3_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_3_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_3_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_3_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_3_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_3_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_3_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_4_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_4_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_4_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_4_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_4_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_4_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_4_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_4_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_4_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_5_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_5_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_5_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_5_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_5_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_5_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_5_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_5_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_5_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_6_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_6_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_6_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_6_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_6_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_6_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_6_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_6_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_6_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:148:30]
wire [1:0] pred_wakeup_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:149:26]
wire [1:0] pred_wakeup_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:149:26]
wire [1:0] pred_wakeup_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:149:26]
wire [1:0] pred_wakeup_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:149:26]
wire [1:0] pred_wakeup_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:149:26]
wire [1:0] pred_wakeup_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:149:26]
wire [1:0] pred_wakeup_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:149:26]
wire [1:0] pred_wakeup_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:149:26]
wire [1:0] pred_wakeup_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:149:26]
wire [1:0] dec_uops_0_ctrl_op1_sel = 2'h0; // @[core.scala:158:24]
wire [1:0] dec_uops_0_iw_state = 2'h0; // @[core.scala:158:24]
wire [1:0] dec_uops_0_rxq_idx = 2'h0; // @[core.scala:158:24]
wire [1:0] dec_uops_0_debug_tsrc = 2'h0; // @[core.scala:158:24]
wire [1:0] dec_uops_1_ctrl_op1_sel = 2'h0; // @[core.scala:158:24]
wire [1:0] dec_uops_1_iw_state = 2'h0; // @[core.scala:158:24]
wire [1:0] dec_uops_1_rxq_idx = 2'h0; // @[core.scala:158:24]
wire [1:0] dec_uops_1_debug_tsrc = 2'h0; // @[core.scala:158:24]
wire [1:0] dec_uops_2_ctrl_op1_sel = 2'h0; // @[core.scala:158:24]
wire [1:0] dec_uops_2_iw_state = 2'h0; // @[core.scala:158:24]
wire [1:0] dec_uops_2_rxq_idx = 2'h0; // @[core.scala:158:24]
wire [1:0] dec_uops_2_debug_tsrc = 2'h0; // @[core.scala:158:24]
wire [1:0] bypasses_0_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:174:24]
wire [1:0] bypasses_0_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:174:24]
wire [1:0] bypasses_0_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:174:24]
wire [1:0] bypasses_0_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:174:24]
wire [1:0] bypasses_0_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:174:24]
wire [1:0] bypasses_0_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:174:24]
wire [1:0] bypasses_0_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:174:24]
wire [1:0] bypasses_0_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:174:24]
wire [1:0] bypasses_0_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:174:24]
wire [1:0] bypasses_1_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:174:24]
wire [1:0] bypasses_1_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:174:24]
wire [1:0] bypasses_1_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:174:24]
wire [1:0] bypasses_1_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:174:24]
wire [1:0] bypasses_1_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:174:24]
wire [1:0] bypasses_1_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:174:24]
wire [1:0] bypasses_1_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:174:24]
wire [1:0] bypasses_1_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:174:24]
wire [1:0] bypasses_1_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:174:24]
wire [1:0] bypasses_2_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:174:24]
wire [1:0] bypasses_2_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:174:24]
wire [1:0] bypasses_2_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:174:24]
wire [1:0] bypasses_2_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:174:24]
wire [1:0] bypasses_2_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:174:24]
wire [1:0] bypasses_2_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:174:24]
wire [1:0] bypasses_2_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:174:24]
wire [1:0] bypasses_2_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:174:24]
wire [1:0] bypasses_2_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:174:24]
wire [1:0] bypasses_3_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:174:24]
wire [1:0] bypasses_3_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:174:24]
wire [1:0] bypasses_3_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:174:24]
wire [1:0] bypasses_3_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:174:24]
wire [1:0] bypasses_3_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:174:24]
wire [1:0] bypasses_3_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:174:24]
wire [1:0] bypasses_3_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:174:24]
wire [1:0] bypasses_3_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:174:24]
wire [1:0] bypasses_3_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:174:24]
wire [1:0] bypasses_4_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:174:24]
wire [1:0] bypasses_4_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:174:24]
wire [1:0] bypasses_4_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:174:24]
wire [1:0] bypasses_4_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:174:24]
wire [1:0] bypasses_4_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:174:24]
wire [1:0] bypasses_4_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:174:24]
wire [1:0] bypasses_4_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:174:24]
wire [1:0] bypasses_4_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:174:24]
wire [1:0] bypasses_4_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:174:24]
wire [1:0] pred_bypasses_0_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:175:27]
wire [1:0] pred_bypasses_0_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:175:27]
wire [1:0] pred_bypasses_0_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:175:27]
wire [1:0] pred_bypasses_0_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:175:27]
wire [1:0] pred_bypasses_0_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:175:27]
wire [1:0] pred_bypasses_0_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:175:27]
wire [1:0] pred_bypasses_0_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:175:27]
wire [1:0] pred_bypasses_0_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:175:27]
wire [1:0] pred_bypasses_0_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:175:27]
wire [1:0] p_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19]
wire [1:0] p_uop_iw_state = 2'h0; // @[consts.scala:269:19]
wire [1:0] p_uop_rxq_idx = 2'h0; // @[consts.scala:269:19]
wire [1:0] p_uop_mem_size = 2'h0; // @[consts.scala:269:19]
wire [1:0] p_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] p_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] p_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] p_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] p_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18]
wire [1:0] p_uop_1_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19]
wire [1:0] p_uop_1_iw_state = 2'h0; // @[consts.scala:269:19]
wire [1:0] p_uop_1_rxq_idx = 2'h0; // @[consts.scala:269:19]
wire [1:0] p_uop_1_mem_size = 2'h0; // @[consts.scala:269:19]
wire [1:0] p_uop_1_lrs1_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] p_uop_1_lrs2_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] p_uop_1_debug_fsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] p_uop_1_debug_tsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] p_uop_cs_1_op1_sel = 2'h0; // @[consts.scala:279:18]
wire [1:0] p_uop_2_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19]
wire [1:0] p_uop_2_iw_state = 2'h0; // @[consts.scala:269:19]
wire [1:0] p_uop_2_rxq_idx = 2'h0; // @[consts.scala:269:19]
wire [1:0] p_uop_2_mem_size = 2'h0; // @[consts.scala:269:19]
wire [1:0] p_uop_2_lrs1_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] p_uop_2_lrs2_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] p_uop_2_debug_fsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] p_uop_2_debug_tsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] p_uop_cs_2_op1_sel = 2'h0; // @[consts.scala:279:18]
wire [1:0] fast_wakeup_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:814:29]
wire [1:0] fast_wakeup_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:814:29]
wire [1:0] fast_wakeup_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:814:29]
wire [1:0] fast_wakeup_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:814:29]
wire [1:0] fast_wakeup_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:814:29]
wire [1:0] fast_wakeup_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:814:29]
wire [1:0] fast_wakeup_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:814:29]
wire [1:0] fast_wakeup_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:814:29]
wire [1:0] fast_wakeup_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:814:29]
wire [1:0] slow_wakeup_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:815:29]
wire [1:0] slow_wakeup_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:815:29]
wire [1:0] slow_wakeup_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:815:29]
wire [1:0] slow_wakeup_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:815:29]
wire [1:0] slow_wakeup_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:815:29]
wire [1:0] slow_wakeup_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:815:29]
wire [1:0] slow_wakeup_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:815:29]
wire [1:0] slow_wakeup_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:815:29]
wire [1:0] slow_wakeup_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:815:29]
wire [1:0] fast_wakeup_1_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:814:29]
wire [1:0] fast_wakeup_1_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:814:29]
wire [1:0] fast_wakeup_1_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:814:29]
wire [1:0] fast_wakeup_1_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:814:29]
wire [1:0] fast_wakeup_1_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:814:29]
wire [1:0] fast_wakeup_1_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:814:29]
wire [1:0] fast_wakeup_1_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:814:29]
wire [1:0] fast_wakeup_1_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:814:29]
wire [1:0] fast_wakeup_1_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:814:29]
wire [1:0] slow_wakeup_1_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:815:29]
wire [1:0] slow_wakeup_1_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:815:29]
wire [1:0] slow_wakeup_1_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:815:29]
wire [1:0] slow_wakeup_1_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:815:29]
wire [1:0] slow_wakeup_1_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:815:29]
wire [1:0] slow_wakeup_1_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:815:29]
wire [1:0] slow_wakeup_1_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:815:29]
wire [1:0] slow_wakeup_1_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:815:29]
wire [1:0] slow_wakeup_1_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:815:29]
wire [1:0] fast_wakeup_2_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:814:29]
wire [1:0] fast_wakeup_2_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:814:29]
wire [1:0] fast_wakeup_2_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:814:29]
wire [1:0] fast_wakeup_2_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:814:29]
wire [1:0] fast_wakeup_2_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:814:29]
wire [1:0] fast_wakeup_2_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:814:29]
wire [1:0] fast_wakeup_2_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:814:29]
wire [1:0] fast_wakeup_2_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:814:29]
wire [1:0] fast_wakeup_2_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:814:29]
wire [1:0] slow_wakeup_2_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:815:29]
wire [1:0] slow_wakeup_2_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:815:29]
wire [1:0] slow_wakeup_2_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:815:29]
wire [1:0] slow_wakeup_2_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:815:29]
wire [1:0] slow_wakeup_2_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:815:29]
wire [1:0] slow_wakeup_2_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:815:29]
wire [1:0] slow_wakeup_2_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:815:29]
wire [1:0] slow_wakeup_2_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:815:29]
wire [1:0] slow_wakeup_2_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:815:29]
wire [4:0] io_ifu_fetchpacket_bits_uops_0_bits_ctrl_op_fcn = 5'h0; // @[core.scala:51:7]
wire [4:0] io_ifu_fetchpacket_bits_uops_0_bits_ldq_idx = 5'h0; // @[core.scala:51:7]
wire [4:0] io_ifu_fetchpacket_bits_uops_0_bits_stq_idx = 5'h0; // @[core.scala:51:7]
wire [4:0] io_ifu_fetchpacket_bits_uops_0_bits_ppred = 5'h0; // @[core.scala:51:7]
wire [4:0] io_ifu_fetchpacket_bits_uops_0_bits_mem_cmd = 5'h0; // @[core.scala:51:7]
wire [4:0] io_ifu_fetchpacket_bits_uops_1_bits_ctrl_op_fcn = 5'h0; // @[core.scala:51:7]
wire [4:0] io_ifu_fetchpacket_bits_uops_1_bits_ldq_idx = 5'h0; // @[core.scala:51:7]
wire [4:0] io_ifu_fetchpacket_bits_uops_1_bits_stq_idx = 5'h0; // @[core.scala:51:7]
wire [4:0] io_ifu_fetchpacket_bits_uops_1_bits_ppred = 5'h0; // @[core.scala:51:7]
wire [4:0] io_ifu_fetchpacket_bits_uops_1_bits_mem_cmd = 5'h0; // @[core.scala:51:7]
wire [4:0] io_ifu_fetchpacket_bits_uops_2_bits_ctrl_op_fcn = 5'h0; // @[core.scala:51:7]
wire [4:0] io_ifu_fetchpacket_bits_uops_2_bits_ldq_idx = 5'h0; // @[core.scala:51:7]
wire [4:0] io_ifu_fetchpacket_bits_uops_2_bits_stq_idx = 5'h0; // @[core.scala:51:7]
wire [4:0] io_ifu_fetchpacket_bits_uops_2_bits_ppred = 5'h0; // @[core.scala:51:7]
wire [4:0] io_ifu_fetchpacket_bits_uops_2_bits_mem_cmd = 5'h0; // @[core.scala:51:7]
wire [4:0] io_ifu_get_pc_0_ghist_ras_idx = 5'h0; // @[core.scala:51:7]
wire [4:0] io_ifu_debug_ftq_idx_0 = 5'h0; // @[core.scala:51:7]
wire [4:0] io_ifu_debug_ftq_idx_1 = 5'h0; // @[core.scala:51:7]
wire [4:0] io_ifu_debug_ftq_idx_2 = 5'h0; // @[core.scala:51:7]
wire [4:0] io_ptw_hstatus_zero1 = 5'h0; // @[core.scala:51:7]
wire [4:0] io_rocc_cmd_bits_inst_rs2 = 5'h0; // @[core.scala:51:7]
wire [4:0] io_rocc_cmd_bits_inst_rs1 = 5'h0; // @[core.scala:51:7]
wire [4:0] io_rocc_cmd_bits_inst_rd = 5'h0; // @[core.scala:51:7]
wire [4:0] io_rocc_resp_bits_rd = 5'h0; // @[core.scala:51:7]
wire [4:0] io_rocc_mem_req_bits_cmd = 5'h0; // @[core.scala:51:7]
wire [4:0] io_rocc_mem_resp_bits_cmd = 5'h0; // @[core.scala:51:7]
wire [4:0] io_lsu_exe_0_req_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:51:7]
wire [4:0] io_lsu_exe_0_req_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[core.scala:51:7]
wire [4:0] io_lsu_exe_0_req_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[core.scala:51:7]
wire [4:0] io_lsu_exe_0_req_bits_fflags_bits_uop_stq_idx = 5'h0; // @[core.scala:51:7]
wire [4:0] io_lsu_exe_0_req_bits_fflags_bits_uop_ppred = 5'h0; // @[core.scala:51:7]
wire [4:0] io_lsu_exe_0_req_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:51:7]
wire [4:0] io_lsu_exe_0_req_bits_fflags_bits_flags = 5'h0; // @[core.scala:51:7]
wire [4:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:51:7]
wire [4:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[core.scala:51:7]
wire [4:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[core.scala:51:7]
wire [4:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_stq_idx = 5'h0; // @[core.scala:51:7]
wire [4:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_ppred = 5'h0; // @[core.scala:51:7]
wire [4:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:51:7]
wire [4:0] io_lsu_exe_0_iresp_bits_fflags_bits_flags = 5'h0; // @[core.scala:51:7]
wire [4:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:51:7]
wire [4:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[core.scala:51:7]
wire [4:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[core.scala:51:7]
wire [4:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_stq_idx = 5'h0; // @[core.scala:51:7]
wire [4:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_ppred = 5'h0; // @[core.scala:51:7]
wire [4:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:51:7]
wire [4:0] io_lsu_exe_0_fresp_bits_fflags_bits_flags = 5'h0; // @[core.scala:51:7]
wire [4:0] io_lsu_dis_uops_0_bits_ppred = 5'h0; // @[core.scala:51:7]
wire [4:0] io_lsu_dis_uops_1_bits_ppred = 5'h0; // @[core.scala:51:7]
wire [4:0] io_lsu_dis_uops_2_bits_ppred = 5'h0; // @[core.scala:51:7]
wire [4:0] io_ptw_tlb_hstatus_zero1 = 5'h0; // @[core.scala:51:7]
wire [4:0] int_iss_wakeups_1_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_1_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_1_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_1_bits_fflags_bits_uop_stq_idx = 5'h0; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_1_bits_fflags_bits_uop_ppred = 5'h0; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_1_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_1_bits_fflags_bits_flags = 5'h0; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_2_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_2_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_2_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_2_bits_fflags_bits_uop_stq_idx = 5'h0; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_2_bits_fflags_bits_uop_ppred = 5'h0; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_2_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_2_bits_fflags_bits_flags = 5'h0; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_3_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_3_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_3_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_3_bits_fflags_bits_uop_stq_idx = 5'h0; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_3_bits_fflags_bits_uop_ppred = 5'h0; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_3_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_3_bits_fflags_bits_flags = 5'h0; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_4_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_4_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_4_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_4_bits_fflags_bits_uop_stq_idx = 5'h0; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_4_bits_fflags_bits_uop_ppred = 5'h0; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_4_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_4_bits_fflags_bits_flags = 5'h0; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_5_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_5_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_5_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_5_bits_fflags_bits_uop_stq_idx = 5'h0; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_5_bits_fflags_bits_uop_ppred = 5'h0; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_5_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_5_bits_fflags_bits_flags = 5'h0; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_6_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_6_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_6_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_6_bits_fflags_bits_uop_stq_idx = 5'h0; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_6_bits_fflags_bits_uop_ppred = 5'h0; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_6_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_6_bits_fflags_bits_flags = 5'h0; // @[core.scala:147:30]
wire [4:0] int_ren_wakeups_1_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_1_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_1_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_1_bits_fflags_bits_uop_stq_idx = 5'h0; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_1_bits_fflags_bits_uop_ppred = 5'h0; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_1_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_1_bits_fflags_bits_flags = 5'h0; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_2_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_2_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_2_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_2_bits_fflags_bits_uop_stq_idx = 5'h0; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_2_bits_fflags_bits_uop_ppred = 5'h0; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_2_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_2_bits_fflags_bits_flags = 5'h0; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_3_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_3_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_3_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_3_bits_fflags_bits_uop_stq_idx = 5'h0; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_3_bits_fflags_bits_uop_ppred = 5'h0; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_3_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_3_bits_fflags_bits_flags = 5'h0; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_4_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_4_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_4_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_4_bits_fflags_bits_uop_stq_idx = 5'h0; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_4_bits_fflags_bits_uop_ppred = 5'h0; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_4_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_4_bits_fflags_bits_flags = 5'h0; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_5_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_5_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_5_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_5_bits_fflags_bits_uop_stq_idx = 5'h0; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_5_bits_fflags_bits_uop_ppred = 5'h0; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_5_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_5_bits_fflags_bits_flags = 5'h0; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_6_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_6_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_6_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_6_bits_fflags_bits_uop_stq_idx = 5'h0; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_6_bits_fflags_bits_uop_ppred = 5'h0; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_6_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_6_bits_fflags_bits_flags = 5'h0; // @[core.scala:148:30]
wire [4:0] pred_wakeup_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:149:26]
wire [4:0] pred_wakeup_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[core.scala:149:26]
wire [4:0] pred_wakeup_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[core.scala:149:26]
wire [4:0] pred_wakeup_bits_fflags_bits_uop_stq_idx = 5'h0; // @[core.scala:149:26]
wire [4:0] pred_wakeup_bits_fflags_bits_uop_ppred = 5'h0; // @[core.scala:149:26]
wire [4:0] pred_wakeup_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:149:26]
wire [4:0] pred_wakeup_bits_fflags_bits_flags = 5'h0; // @[core.scala:149:26]
wire [4:0] dec_uops_0_ctrl_op_fcn = 5'h0; // @[core.scala:158:24]
wire [4:0] dec_uops_0_ldq_idx = 5'h0; // @[core.scala:158:24]
wire [4:0] dec_uops_0_stq_idx = 5'h0; // @[core.scala:158:24]
wire [4:0] dec_uops_0_ppred = 5'h0; // @[core.scala:158:24]
wire [4:0] dec_uops_1_ctrl_op_fcn = 5'h0; // @[core.scala:158:24]
wire [4:0] dec_uops_1_ldq_idx = 5'h0; // @[core.scala:158:24]
wire [4:0] dec_uops_1_stq_idx = 5'h0; // @[core.scala:158:24]
wire [4:0] dec_uops_1_ppred = 5'h0; // @[core.scala:158:24]
wire [4:0] dec_uops_2_ctrl_op_fcn = 5'h0; // @[core.scala:158:24]
wire [4:0] dec_uops_2_ldq_idx = 5'h0; // @[core.scala:158:24]
wire [4:0] dec_uops_2_stq_idx = 5'h0; // @[core.scala:158:24]
wire [4:0] dec_uops_2_ppred = 5'h0; // @[core.scala:158:24]
wire [4:0] dis_uops_0_ppred = 5'h0; // @[core.scala:167:24]
wire [4:0] dis_uops_1_ppred = 5'h0; // @[core.scala:167:24]
wire [4:0] dis_uops_2_ppred = 5'h0; // @[core.scala:167:24]
wire [4:0] bypasses_0_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:174:24]
wire [4:0] bypasses_0_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[core.scala:174:24]
wire [4:0] bypasses_0_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[core.scala:174:24]
wire [4:0] bypasses_0_bits_fflags_bits_uop_stq_idx = 5'h0; // @[core.scala:174:24]
wire [4:0] bypasses_0_bits_fflags_bits_uop_ppred = 5'h0; // @[core.scala:174:24]
wire [4:0] bypasses_0_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:174:24]
wire [4:0] bypasses_0_bits_fflags_bits_flags = 5'h0; // @[core.scala:174:24]
wire [4:0] bypasses_1_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:174:24]
wire [4:0] bypasses_1_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[core.scala:174:24]
wire [4:0] bypasses_1_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[core.scala:174:24]
wire [4:0] bypasses_1_bits_fflags_bits_uop_stq_idx = 5'h0; // @[core.scala:174:24]
wire [4:0] bypasses_1_bits_fflags_bits_uop_ppred = 5'h0; // @[core.scala:174:24]
wire [4:0] bypasses_1_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:174:24]
wire [4:0] bypasses_1_bits_fflags_bits_flags = 5'h0; // @[core.scala:174:24]
wire [4:0] bypasses_2_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:174:24]
wire [4:0] bypasses_2_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[core.scala:174:24]
wire [4:0] bypasses_2_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[core.scala:174:24]
wire [4:0] bypasses_2_bits_fflags_bits_uop_stq_idx = 5'h0; // @[core.scala:174:24]
wire [4:0] bypasses_2_bits_fflags_bits_uop_ppred = 5'h0; // @[core.scala:174:24]
wire [4:0] bypasses_2_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:174:24]
wire [4:0] bypasses_2_bits_fflags_bits_flags = 5'h0; // @[core.scala:174:24]
wire [4:0] bypasses_3_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:174:24]
wire [4:0] bypasses_3_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[core.scala:174:24]
wire [4:0] bypasses_3_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[core.scala:174:24]
wire [4:0] bypasses_3_bits_fflags_bits_uop_stq_idx = 5'h0; // @[core.scala:174:24]
wire [4:0] bypasses_3_bits_fflags_bits_uop_ppred = 5'h0; // @[core.scala:174:24]
wire [4:0] bypasses_3_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:174:24]
wire [4:0] bypasses_3_bits_fflags_bits_flags = 5'h0; // @[core.scala:174:24]
wire [4:0] bypasses_4_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:174:24]
wire [4:0] bypasses_4_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[core.scala:174:24]
wire [4:0] bypasses_4_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[core.scala:174:24]
wire [4:0] bypasses_4_bits_fflags_bits_uop_stq_idx = 5'h0; // @[core.scala:174:24]
wire [4:0] bypasses_4_bits_fflags_bits_uop_ppred = 5'h0; // @[core.scala:174:24]
wire [4:0] bypasses_4_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:174:24]
wire [4:0] bypasses_4_bits_fflags_bits_flags = 5'h0; // @[core.scala:174:24]
wire [4:0] pred_bypasses_0_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:175:27]
wire [4:0] pred_bypasses_0_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[core.scala:175:27]
wire [4:0] pred_bypasses_0_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[core.scala:175:27]
wire [4:0] pred_bypasses_0_bits_fflags_bits_uop_stq_idx = 5'h0; // @[core.scala:175:27]
wire [4:0] pred_bypasses_0_bits_fflags_bits_uop_ppred = 5'h0; // @[core.scala:175:27]
wire [4:0] pred_bypasses_0_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:175:27]
wire [4:0] pred_bypasses_0_bits_fflags_bits_flags = 5'h0; // @[core.scala:175:27]
wire [4:0] _new_ghist_WIRE_ras_idx = 5'h0; // @[core.scala:406:44]
wire [4:0] p_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19]
wire [4:0] p_uop_ftq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] p_uop_ldq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] p_uop_stq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] p_uop_ppred = 5'h0; // @[consts.scala:269:19]
wire [4:0] p_uop_mem_cmd = 5'h0; // @[consts.scala:269:19]
wire [4:0] p_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18]
wire [4:0] p_uop_1_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19]
wire [4:0] p_uop_1_ftq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] p_uop_1_ldq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] p_uop_1_stq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] p_uop_1_ppred = 5'h0; // @[consts.scala:269:19]
wire [4:0] p_uop_1_mem_cmd = 5'h0; // @[consts.scala:269:19]
wire [4:0] p_uop_cs_1_op_fcn = 5'h0; // @[consts.scala:279:18]
wire [4:0] p_uop_2_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19]
wire [4:0] p_uop_2_ftq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] p_uop_2_ldq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] p_uop_2_stq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] p_uop_2_ppred = 5'h0; // @[consts.scala:269:19]
wire [4:0] p_uop_2_mem_cmd = 5'h0; // @[consts.scala:269:19]
wire [4:0] p_uop_cs_2_op_fcn = 5'h0; // @[consts.scala:279:18]
wire [4:0] fast_wakeup_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:814:29]
wire [4:0] fast_wakeup_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[core.scala:814:29]
wire [4:0] fast_wakeup_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[core.scala:814:29]
wire [4:0] fast_wakeup_bits_fflags_bits_uop_stq_idx = 5'h0; // @[core.scala:814:29]
wire [4:0] fast_wakeup_bits_fflags_bits_uop_ppred = 5'h0; // @[core.scala:814:29]
wire [4:0] fast_wakeup_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:814:29]
wire [4:0] fast_wakeup_bits_fflags_bits_flags = 5'h0; // @[core.scala:814:29]
wire [4:0] slow_wakeup_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:815:29]
wire [4:0] slow_wakeup_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[core.scala:815:29]
wire [4:0] slow_wakeup_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[core.scala:815:29]
wire [4:0] slow_wakeup_bits_fflags_bits_uop_stq_idx = 5'h0; // @[core.scala:815:29]
wire [4:0] slow_wakeup_bits_fflags_bits_uop_ppred = 5'h0; // @[core.scala:815:29]
wire [4:0] slow_wakeup_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:815:29]
wire [4:0] slow_wakeup_bits_fflags_bits_flags = 5'h0; // @[core.scala:815:29]
wire [4:0] fast_wakeup_1_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:814:29]
wire [4:0] fast_wakeup_1_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[core.scala:814:29]
wire [4:0] fast_wakeup_1_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[core.scala:814:29]
wire [4:0] fast_wakeup_1_bits_fflags_bits_uop_stq_idx = 5'h0; // @[core.scala:814:29]
wire [4:0] fast_wakeup_1_bits_fflags_bits_uop_ppred = 5'h0; // @[core.scala:814:29]
wire [4:0] fast_wakeup_1_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:814:29]
wire [4:0] fast_wakeup_1_bits_fflags_bits_flags = 5'h0; // @[core.scala:814:29]
wire [4:0] slow_wakeup_1_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:815:29]
wire [4:0] slow_wakeup_1_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[core.scala:815:29]
wire [4:0] slow_wakeup_1_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[core.scala:815:29]
wire [4:0] slow_wakeup_1_bits_fflags_bits_uop_stq_idx = 5'h0; // @[core.scala:815:29]
wire [4:0] slow_wakeup_1_bits_fflags_bits_uop_ppred = 5'h0; // @[core.scala:815:29]
wire [4:0] slow_wakeup_1_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:815:29]
wire [4:0] slow_wakeup_1_bits_fflags_bits_flags = 5'h0; // @[core.scala:815:29]
wire [4:0] fast_wakeup_2_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:814:29]
wire [4:0] fast_wakeup_2_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[core.scala:814:29]
wire [4:0] fast_wakeup_2_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[core.scala:814:29]
wire [4:0] fast_wakeup_2_bits_fflags_bits_uop_stq_idx = 5'h0; // @[core.scala:814:29]
wire [4:0] fast_wakeup_2_bits_fflags_bits_uop_ppred = 5'h0; // @[core.scala:814:29]
wire [4:0] fast_wakeup_2_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:814:29]
wire [4:0] fast_wakeup_2_bits_fflags_bits_flags = 5'h0; // @[core.scala:814:29]
wire [4:0] slow_wakeup_2_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:815:29]
wire [4:0] slow_wakeup_2_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[core.scala:815:29]
wire [4:0] slow_wakeup_2_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[core.scala:815:29]
wire [4:0] slow_wakeup_2_bits_fflags_bits_uop_stq_idx = 5'h0; // @[core.scala:815:29]
wire [4:0] slow_wakeup_2_bits_fflags_bits_uop_ppred = 5'h0; // @[core.scala:815:29]
wire [4:0] slow_wakeup_2_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:815:29]
wire [4:0] slow_wakeup_2_bits_fflags_bits_flags = 5'h0; // @[core.scala:815:29]
wire [4:0] coreMonitorBundle_wrdst = 5'h0; // @[core.scala:1405:31]
wire [4:0] coreMonitorBundle_rd0src = 5'h0; // @[core.scala:1405:31]
wire [4:0] coreMonitorBundle_rd1src = 5'h0; // @[core.scala:1405:31]
wire io_ifu_fetchpacket_bits_uops_0_bits_ctrl_fcn_dw = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_0_bits_ctrl_is_load = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_0_bits_ctrl_is_sta = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_0_bits_ctrl_is_std = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_0_bits_iw_p1_poisoned = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_0_bits_iw_p2_poisoned = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_0_bits_is_br = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_0_bits_is_jalr = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_0_bits_is_jal = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_0_bits_prs1_busy = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_0_bits_prs2_busy = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_0_bits_prs3_busy = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_0_bits_ppred_busy = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_0_bits_exception = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_0_bits_bypassable = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_0_bits_mem_signed = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_0_bits_is_fence = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_0_bits_is_fencei = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_0_bits_is_amo = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_0_bits_uses_ldq = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_0_bits_uses_stq = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_0_bits_is_sys_pc2epc = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_0_bits_is_unique = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_0_bits_flush_on_commit = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_0_bits_ldst_is_rs1 = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_0_bits_ldst_val = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_0_bits_frs3_en = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_0_bits_fp_val = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_0_bits_fp_single = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_0_bits_xcpt_ma_if = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_1_bits_ctrl_fcn_dw = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_1_bits_ctrl_is_load = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_1_bits_ctrl_is_sta = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_1_bits_ctrl_is_std = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_1_bits_iw_p1_poisoned = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_1_bits_iw_p2_poisoned = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_1_bits_is_br = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_1_bits_is_jalr = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_1_bits_is_jal = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_1_bits_prs1_busy = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_1_bits_prs2_busy = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_1_bits_prs3_busy = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_1_bits_ppred_busy = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_1_bits_exception = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_1_bits_bypassable = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_1_bits_mem_signed = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_1_bits_is_fence = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_1_bits_is_fencei = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_1_bits_is_amo = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_1_bits_uses_ldq = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_1_bits_uses_stq = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_1_bits_is_sys_pc2epc = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_1_bits_is_unique = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_1_bits_flush_on_commit = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_1_bits_ldst_is_rs1 = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_1_bits_ldst_val = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_1_bits_frs3_en = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_1_bits_fp_val = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_1_bits_fp_single = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_1_bits_xcpt_ma_if = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_2_bits_ctrl_fcn_dw = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_2_bits_ctrl_is_load = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_2_bits_ctrl_is_sta = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_2_bits_ctrl_is_std = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_2_bits_iw_p1_poisoned = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_2_bits_iw_p2_poisoned = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_2_bits_is_br = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_2_bits_is_jalr = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_2_bits_is_jal = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_2_bits_prs1_busy = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_2_bits_prs2_busy = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_2_bits_prs3_busy = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_2_bits_ppred_busy = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_2_bits_exception = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_2_bits_bypassable = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_2_bits_mem_signed = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_2_bits_is_fence = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_2_bits_is_fencei = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_2_bits_is_amo = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_2_bits_uses_ldq = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_2_bits_uses_stq = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_2_bits_is_sys_pc2epc = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_2_bits_is_unique = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_2_bits_flush_on_commit = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_2_bits_ldst_is_rs1 = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_2_bits_ldst_val = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_2_bits_frs3_en = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_2_bits_fp_val = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_2_bits_fp_single = 1'h0; // @[core.scala:51:7]
wire io_ifu_fetchpacket_bits_uops_2_bits_xcpt_ma_if = 1'h0; // @[core.scala:51:7]
wire io_ifu_get_pc_0_ghist_current_saw_branch_not_taken = 1'h0; // @[core.scala:51:7]
wire io_ifu_get_pc_0_ghist_new_saw_branch_not_taken = 1'h0; // @[core.scala:51:7]
wire io_ifu_get_pc_0_ghist_new_saw_branch_taken = 1'h0; // @[core.scala:51:7]
wire io_ifu_status_mbe = 1'h0; // @[core.scala:51:7]
wire io_ifu_status_sbe = 1'h0; // @[core.scala:51:7]
wire io_ifu_status_sd_rv32 = 1'h0; // @[core.scala:51:7]
wire io_ifu_status_ube = 1'h0; // @[core.scala:51:7]
wire io_ifu_status_upie = 1'h0; // @[core.scala:51:7]
wire io_ifu_status_hie = 1'h0; // @[core.scala:51:7]
wire io_ifu_status_uie = 1'h0; // @[core.scala:51:7]
wire io_ifu_sfence_bits_hv = 1'h0; // @[core.scala:51:7]
wire io_ifu_sfence_bits_hg = 1'h0; // @[core.scala:51:7]
wire io_ptw_sfence_bits_hv = 1'h0; // @[core.scala:51:7]
wire io_ptw_sfence_bits_hg = 1'h0; // @[core.scala:51:7]
wire io_ptw_status_mbe = 1'h0; // @[core.scala:51:7]
wire io_ptw_status_sbe = 1'h0; // @[core.scala:51:7]
wire io_ptw_status_sd_rv32 = 1'h0; // @[core.scala:51:7]
wire io_ptw_status_ube = 1'h0; // @[core.scala:51:7]
wire io_ptw_status_upie = 1'h0; // @[core.scala:51:7]
wire io_ptw_status_hie = 1'h0; // @[core.scala:51:7]
wire io_ptw_status_uie = 1'h0; // @[core.scala:51:7]
wire io_ptw_hstatus_vtsr = 1'h0; // @[core.scala:51:7]
wire io_ptw_hstatus_vtw = 1'h0; // @[core.scala:51:7]
wire io_ptw_hstatus_vtvm = 1'h0; // @[core.scala:51:7]
wire io_ptw_hstatus_hu = 1'h0; // @[core.scala:51:7]
wire io_ptw_hstatus_spvp = 1'h0; // @[core.scala:51:7]
wire io_ptw_hstatus_spv = 1'h0; // @[core.scala:51:7]
wire io_ptw_hstatus_gva = 1'h0; // @[core.scala:51:7]
wire io_ptw_hstatus_vsbe = 1'h0; // @[core.scala:51:7]
wire io_ptw_gstatus_debug = 1'h0; // @[core.scala:51:7]
wire io_ptw_gstatus_cease = 1'h0; // @[core.scala:51:7]
wire io_ptw_gstatus_wfi = 1'h0; // @[core.scala:51:7]
wire io_ptw_gstatus_dv = 1'h0; // @[core.scala:51:7]
wire io_ptw_gstatus_v = 1'h0; // @[core.scala:51:7]
wire io_ptw_gstatus_sd = 1'h0; // @[core.scala:51:7]
wire io_ptw_gstatus_mpv = 1'h0; // @[core.scala:51:7]
wire io_ptw_gstatus_gva = 1'h0; // @[core.scala:51:7]
wire io_ptw_gstatus_mbe = 1'h0; // @[core.scala:51:7]
wire io_ptw_gstatus_sbe = 1'h0; // @[core.scala:51:7]
wire io_ptw_gstatus_sd_rv32 = 1'h0; // @[core.scala:51:7]
wire io_ptw_gstatus_tsr = 1'h0; // @[core.scala:51:7]
wire io_ptw_gstatus_tw = 1'h0; // @[core.scala:51:7]
wire io_ptw_gstatus_tvm = 1'h0; // @[core.scala:51:7]
wire io_ptw_gstatus_mxr = 1'h0; // @[core.scala:51:7]
wire io_ptw_gstatus_sum = 1'h0; // @[core.scala:51:7]
wire io_ptw_gstatus_mprv = 1'h0; // @[core.scala:51:7]
wire io_ptw_gstatus_spp = 1'h0; // @[core.scala:51:7]
wire io_ptw_gstatus_mpie = 1'h0; // @[core.scala:51:7]
wire io_ptw_gstatus_ube = 1'h0; // @[core.scala:51:7]
wire io_ptw_gstatus_spie = 1'h0; // @[core.scala:51:7]
wire io_ptw_gstatus_upie = 1'h0; // @[core.scala:51:7]
wire io_ptw_gstatus_mie = 1'h0; // @[core.scala:51:7]
wire io_ptw_gstatus_hie = 1'h0; // @[core.scala:51:7]
wire io_ptw_gstatus_sie = 1'h0; // @[core.scala:51:7]
wire io_ptw_gstatus_uie = 1'h0; // @[core.scala:51:7]
wire io_ptw_customCSRs_csrs_0_ren = 1'h0; // @[core.scala:51:7]
wire io_ptw_customCSRs_csrs_0_wen = 1'h0; // @[core.scala:51:7]
wire io_ptw_customCSRs_csrs_0_stall = 1'h0; // @[core.scala:51:7]
wire io_ptw_customCSRs_csrs_0_set = 1'h0; // @[core.scala:51:7]
wire io_ptw_customCSRs_csrs_1_ren = 1'h0; // @[core.scala:51:7]
wire io_ptw_customCSRs_csrs_1_wen = 1'h0; // @[core.scala:51:7]
wire io_ptw_customCSRs_csrs_1_stall = 1'h0; // @[core.scala:51:7]
wire io_ptw_customCSRs_csrs_1_set = 1'h0; // @[core.scala:51:7]
wire io_rocc_cmd_ready = 1'h0; // @[core.scala:51:7]
wire io_rocc_cmd_valid = 1'h0; // @[core.scala:51:7]
wire io_rocc_cmd_bits_inst_xd = 1'h0; // @[core.scala:51:7]
wire io_rocc_cmd_bits_inst_xs1 = 1'h0; // @[core.scala:51:7]
wire io_rocc_cmd_bits_inst_xs2 = 1'h0; // @[core.scala:51:7]
wire io_rocc_cmd_bits_status_debug = 1'h0; // @[core.scala:51:7]
wire io_rocc_cmd_bits_status_cease = 1'h0; // @[core.scala:51:7]
wire io_rocc_cmd_bits_status_wfi = 1'h0; // @[core.scala:51:7]
wire io_rocc_cmd_bits_status_dv = 1'h0; // @[core.scala:51:7]
wire io_rocc_cmd_bits_status_v = 1'h0; // @[core.scala:51:7]
wire io_rocc_cmd_bits_status_sd = 1'h0; // @[core.scala:51:7]
wire io_rocc_cmd_bits_status_mpv = 1'h0; // @[core.scala:51:7]
wire io_rocc_cmd_bits_status_gva = 1'h0; // @[core.scala:51:7]
wire io_rocc_cmd_bits_status_mbe = 1'h0; // @[core.scala:51:7]
wire io_rocc_cmd_bits_status_sbe = 1'h0; // @[core.scala:51:7]
wire io_rocc_cmd_bits_status_sd_rv32 = 1'h0; // @[core.scala:51:7]
wire io_rocc_cmd_bits_status_tsr = 1'h0; // @[core.scala:51:7]
wire io_rocc_cmd_bits_status_tw = 1'h0; // @[core.scala:51:7]
wire io_rocc_cmd_bits_status_tvm = 1'h0; // @[core.scala:51:7]
wire io_rocc_cmd_bits_status_mxr = 1'h0; // @[core.scala:51:7]
wire io_rocc_cmd_bits_status_sum = 1'h0; // @[core.scala:51:7]
wire io_rocc_cmd_bits_status_mprv = 1'h0; // @[core.scala:51:7]
wire io_rocc_cmd_bits_status_spp = 1'h0; // @[core.scala:51:7]
wire io_rocc_cmd_bits_status_mpie = 1'h0; // @[core.scala:51:7]
wire io_rocc_cmd_bits_status_ube = 1'h0; // @[core.scala:51:7]
wire io_rocc_cmd_bits_status_spie = 1'h0; // @[core.scala:51:7]
wire io_rocc_cmd_bits_status_upie = 1'h0; // @[core.scala:51:7]
wire io_rocc_cmd_bits_status_mie = 1'h0; // @[core.scala:51:7]
wire io_rocc_cmd_bits_status_hie = 1'h0; // @[core.scala:51:7]
wire io_rocc_cmd_bits_status_sie = 1'h0; // @[core.scala:51:7]
wire io_rocc_cmd_bits_status_uie = 1'h0; // @[core.scala:51:7]
wire io_rocc_resp_ready = 1'h0; // @[core.scala:51:7]
wire io_rocc_resp_valid = 1'h0; // @[core.scala:51:7]
wire io_rocc_mem_req_ready = 1'h0; // @[core.scala:51:7]
wire io_rocc_mem_req_valid = 1'h0; // @[core.scala:51:7]
wire io_rocc_mem_req_bits_signed = 1'h0; // @[core.scala:51:7]
wire io_rocc_mem_req_bits_dv = 1'h0; // @[core.scala:51:7]
wire io_rocc_mem_req_bits_phys = 1'h0; // @[core.scala:51:7]
wire io_rocc_mem_req_bits_no_resp = 1'h0; // @[core.scala:51:7]
wire io_rocc_mem_req_bits_no_alloc = 1'h0; // @[core.scala:51:7]
wire io_rocc_mem_req_bits_no_xcpt = 1'h0; // @[core.scala:51:7]
wire io_rocc_mem_s1_kill = 1'h0; // @[core.scala:51:7]
wire io_rocc_mem_s2_nack = 1'h0; // @[core.scala:51:7]
wire io_rocc_mem_s2_nack_cause_raw = 1'h0; // @[core.scala:51:7]
wire io_rocc_mem_s2_kill = 1'h0; // @[core.scala:51:7]
wire io_rocc_mem_s2_uncached = 1'h0; // @[core.scala:51:7]
wire io_rocc_mem_resp_valid = 1'h0; // @[core.scala:51:7]
wire io_rocc_mem_resp_bits_signed = 1'h0; // @[core.scala:51:7]
wire io_rocc_mem_resp_bits_dv = 1'h0; // @[core.scala:51:7]
wire io_rocc_mem_resp_bits_replay = 1'h0; // @[core.scala:51:7]
wire io_rocc_mem_resp_bits_has_data = 1'h0; // @[core.scala:51:7]
wire io_rocc_mem_replay_next = 1'h0; // @[core.scala:51:7]
wire io_rocc_mem_s2_xcpt_ma_ld = 1'h0; // @[core.scala:51:7]
wire io_rocc_mem_s2_xcpt_ma_st = 1'h0; // @[core.scala:51:7]
wire io_rocc_mem_s2_xcpt_pf_ld = 1'h0; // @[core.scala:51:7]
wire io_rocc_mem_s2_xcpt_pf_st = 1'h0; // @[core.scala:51:7]
wire io_rocc_mem_s2_xcpt_gf_ld = 1'h0; // @[core.scala:51:7]
wire io_rocc_mem_s2_xcpt_gf_st = 1'h0; // @[core.scala:51:7]
wire io_rocc_mem_s2_xcpt_ae_ld = 1'h0; // @[core.scala:51:7]
wire io_rocc_mem_s2_xcpt_ae_st = 1'h0; // @[core.scala:51:7]
wire io_rocc_mem_s2_gpa_is_pte = 1'h0; // @[core.scala:51:7]
wire io_rocc_mem_ordered = 1'h0; // @[core.scala:51:7]
wire io_rocc_mem_store_pending = 1'h0; // @[core.scala:51:7]
wire io_rocc_mem_perf_acquire = 1'h0; // @[core.scala:51:7]
wire io_rocc_mem_perf_release = 1'h0; // @[core.scala:51:7]
wire io_rocc_mem_perf_grant = 1'h0; // @[core.scala:51:7]
wire io_rocc_mem_perf_tlbMiss = 1'h0; // @[core.scala:51:7]
wire io_rocc_mem_perf_blocked = 1'h0; // @[core.scala:51:7]
wire io_rocc_mem_perf_canAcceptStoreThenLoad = 1'h0; // @[core.scala:51:7]
wire io_rocc_mem_perf_canAcceptStoreThenRMW = 1'h0; // @[core.scala:51:7]
wire io_rocc_mem_perf_canAcceptLoadThenLoad = 1'h0; // @[core.scala:51:7]
wire io_rocc_mem_perf_storeBufferEmptyAfterLoad = 1'h0; // @[core.scala:51:7]
wire io_rocc_mem_perf_storeBufferEmptyAfterStore = 1'h0; // @[core.scala:51:7]
wire io_rocc_mem_keep_clock_enabled = 1'h0; // @[core.scala:51:7]
wire io_rocc_mem_clock_enabled = 1'h0; // @[core.scala:51:7]
wire io_rocc_busy = 1'h0; // @[core.scala:51:7]
wire io_rocc_interrupt = 1'h0; // @[core.scala:51:7]
wire io_rocc_exception = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_predicated = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_fflags_valid = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_sfence_bits_hv = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_sfence_bits_hg = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_predicated = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_fflags_valid = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_predicated = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_fflags_valid = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:51:7]
wire io_lsu_dis_uops_0_bits_ppred_busy = 1'h0; // @[core.scala:51:7]
wire io_lsu_dis_uops_1_bits_ppred_busy = 1'h0; // @[core.scala:51:7]
wire io_lsu_dis_uops_2_bits_ppred_busy = 1'h0; // @[core.scala:51:7]
wire io_lsu_clr_unsafe_0_valid = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_req_valid = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_req_bits_valid = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_req_bits_bits_need_gpa = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_req_bits_bits_vstage1 = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_req_bits_bits_stage2 = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_resp_bits_fragmented_superpage = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_status_mbe = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_status_sbe = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_status_sd_rv32 = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_status_ube = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_status_upie = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_status_hie = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_status_uie = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_hstatus_vtsr = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_hstatus_vtw = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_hstatus_vtvm = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_hstatus_hu = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_hstatus_spvp = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_hstatus_spv = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_hstatus_gva = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_hstatus_vsbe = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_gstatus_debug = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_gstatus_cease = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_gstatus_wfi = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_gstatus_dv = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_gstatus_v = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_gstatus_sd = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_gstatus_mpv = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_gstatus_gva = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_gstatus_mbe = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_gstatus_sbe = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_gstatus_sd_rv32 = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_gstatus_tsr = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_gstatus_tw = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_gstatus_tvm = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_gstatus_mxr = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_gstatus_sum = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_gstatus_mprv = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_gstatus_spp = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_gstatus_mpie = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_gstatus_ube = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_gstatus_spie = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_gstatus_upie = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_gstatus_mie = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_gstatus_hie = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_gstatus_sie = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_gstatus_uie = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_customCSRs_csrs_0_ren = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_customCSRs_csrs_0_wen = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_customCSRs_csrs_0_stall = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_customCSRs_csrs_0_set = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_customCSRs_csrs_1_ren = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_customCSRs_csrs_1_wen = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_customCSRs_csrs_1_stall = 1'h0; // @[core.scala:51:7]
wire io_ptw_tlb_customCSRs_csrs_1_set = 1'h0; // @[core.scala:51:7]
wire io_trace_insns_0_valid = 1'h0; // @[core.scala:51:7]
wire io_trace_insns_0_exception = 1'h0; // @[core.scala:51:7]
wire io_trace_insns_0_interrupt = 1'h0; // @[core.scala:51:7]
wire io_trace_insns_1_valid = 1'h0; // @[core.scala:51:7]
wire io_trace_insns_1_exception = 1'h0; // @[core.scala:51:7]
wire io_trace_insns_1_interrupt = 1'h0; // @[core.scala:51:7]
wire io_trace_insns_2_valid = 1'h0; // @[core.scala:51:7]
wire io_trace_insns_2_exception = 1'h0; // @[core.scala:51:7]
wire io_trace_insns_2_interrupt = 1'h0; // @[core.scala:51:7]
wire int_iss_wakeups_1_bits_predicated = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_fflags_valid = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_predicated = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_fflags_valid = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_3_bits_predicated = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_3_bits_fflags_valid = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_3_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_3_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_3_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_3_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_3_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_3_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_3_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_3_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_3_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_3_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_3_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_3_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_3_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_3_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_3_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_3_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_3_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_3_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_3_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_3_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_3_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_3_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_3_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_3_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_3_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_3_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_3_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_3_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_3_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_3_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_3_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_3_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_3_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_3_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_3_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_3_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_3_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_3_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_4_bits_predicated = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_4_bits_fflags_valid = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_4_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_4_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_4_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_4_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_4_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_4_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_4_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_4_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_4_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_4_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_4_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_4_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_4_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_4_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_4_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_4_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_4_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_4_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_4_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_4_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_4_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_4_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_4_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_4_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_4_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_4_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_4_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_4_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_4_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_4_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_4_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_4_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_4_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_4_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_4_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_4_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_4_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_4_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_5_bits_predicated = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_5_bits_fflags_valid = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_5_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_5_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_5_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_5_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_5_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_5_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_5_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_5_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_5_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_5_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_5_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_5_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_5_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_5_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_5_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_5_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_5_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_5_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_5_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_5_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_5_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_5_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_5_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_5_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_5_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_5_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_5_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_5_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_5_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_5_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_5_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_5_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_5_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_5_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_5_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_5_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_5_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_5_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_6_bits_predicated = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_6_bits_fflags_valid = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_6_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_6_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_6_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_6_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_6_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_6_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_6_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_6_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_6_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_6_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_6_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_6_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_6_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_6_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_6_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_6_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_6_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_6_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_6_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_6_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_6_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_6_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_6_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_6_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_6_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_6_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_6_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_6_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_6_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_6_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_6_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_6_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_6_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_6_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_6_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_6_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_6_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:147:30]
wire int_iss_wakeups_6_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:147:30]
wire int_ren_wakeups_1_bits_predicated = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_fflags_valid = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_predicated = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_fflags_valid = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_3_bits_predicated = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_3_bits_fflags_valid = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_3_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_3_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_3_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_3_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_3_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_3_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_3_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_3_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_3_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_3_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_3_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_3_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_3_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_3_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_3_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_3_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_3_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_3_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_3_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_3_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_3_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_3_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_3_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_3_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_3_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_3_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_3_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_3_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_3_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_3_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_3_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_3_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_3_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_3_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_3_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_3_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_3_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_3_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_4_bits_predicated = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_4_bits_fflags_valid = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_4_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_4_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_4_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_4_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_4_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_4_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_4_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_4_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_4_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_4_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_4_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_4_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_4_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_4_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_4_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_4_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_4_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_4_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_4_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_4_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_4_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_4_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_4_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_4_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_4_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_4_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_4_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_4_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_4_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_4_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_4_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_4_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_4_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_4_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_4_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_4_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_4_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_4_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_5_bits_predicated = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_5_bits_fflags_valid = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_5_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_5_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_5_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_5_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_5_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_5_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_5_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_5_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_5_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_5_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_5_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_5_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_5_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_5_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_5_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_5_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_5_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_5_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_5_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_5_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_5_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_5_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_5_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_5_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_5_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_5_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_5_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_5_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_5_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_5_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_5_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_5_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_5_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_5_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_5_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_5_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_5_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_5_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_6_bits_predicated = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_6_bits_fflags_valid = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_6_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_6_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_6_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_6_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_6_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_6_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_6_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_6_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_6_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_6_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_6_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_6_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_6_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_6_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_6_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_6_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_6_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_6_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_6_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_6_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_6_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_6_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_6_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_6_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_6_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_6_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_6_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_6_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_6_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_6_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_6_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_6_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_6_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_6_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_6_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_6_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_6_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:148:30]
wire int_ren_wakeups_6_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:148:30]
wire pred_wakeup_valid = 1'h0; // @[core.scala:149:26]
wire pred_wakeup_bits_data = 1'h0; // @[core.scala:149:26]
wire pred_wakeup_bits_predicated = 1'h0; // @[core.scala:149:26]
wire pred_wakeup_bits_fflags_valid = 1'h0; // @[core.scala:149:26]
wire pred_wakeup_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:149:26]
wire pred_wakeup_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:149:26]
wire pred_wakeup_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:149:26]
wire pred_wakeup_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:149:26]
wire pred_wakeup_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:149:26]
wire pred_wakeup_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:149:26]
wire pred_wakeup_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:149:26]
wire pred_wakeup_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:149:26]
wire pred_wakeup_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:149:26]
wire pred_wakeup_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:149:26]
wire pred_wakeup_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:149:26]
wire pred_wakeup_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:149:26]
wire pred_wakeup_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:149:26]
wire pred_wakeup_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:149:26]
wire pred_wakeup_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:149:26]
wire pred_wakeup_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:149:26]
wire pred_wakeup_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:149:26]
wire pred_wakeup_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:149:26]
wire pred_wakeup_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:149:26]
wire pred_wakeup_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:149:26]
wire pred_wakeup_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:149:26]
wire pred_wakeup_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:149:26]
wire pred_wakeup_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:149:26]
wire pred_wakeup_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:149:26]
wire pred_wakeup_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:149:26]
wire pred_wakeup_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:149:26]
wire pred_wakeup_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:149:26]
wire pred_wakeup_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:149:26]
wire pred_wakeup_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:149:26]
wire pred_wakeup_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:149:26]
wire pred_wakeup_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:149:26]
wire pred_wakeup_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:149:26]
wire pred_wakeup_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:149:26]
wire pred_wakeup_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:149:26]
wire pred_wakeup_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:149:26]
wire pred_wakeup_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:149:26]
wire pred_wakeup_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:149:26]
wire pred_wakeup_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:149:26]
wire dec_uops_0_ctrl_fcn_dw = 1'h0; // @[core.scala:158:24]
wire dec_uops_0_ctrl_is_load = 1'h0; // @[core.scala:158:24]
wire dec_uops_0_ctrl_is_sta = 1'h0; // @[core.scala:158:24]
wire dec_uops_0_ctrl_is_std = 1'h0; // @[core.scala:158:24]
wire dec_uops_0_iw_p1_poisoned = 1'h0; // @[core.scala:158:24]
wire dec_uops_0_iw_p2_poisoned = 1'h0; // @[core.scala:158:24]
wire dec_uops_0_prs1_busy = 1'h0; // @[core.scala:158:24]
wire dec_uops_0_prs2_busy = 1'h0; // @[core.scala:158:24]
wire dec_uops_0_prs3_busy = 1'h0; // @[core.scala:158:24]
wire dec_uops_0_ppred_busy = 1'h0; // @[core.scala:158:24]
wire dec_uops_0_ldst_is_rs1 = 1'h0; // @[core.scala:158:24]
wire dec_uops_0_xcpt_ma_if = 1'h0; // @[core.scala:158:24]
wire dec_uops_1_ctrl_fcn_dw = 1'h0; // @[core.scala:158:24]
wire dec_uops_1_ctrl_is_load = 1'h0; // @[core.scala:158:24]
wire dec_uops_1_ctrl_is_sta = 1'h0; // @[core.scala:158:24]
wire dec_uops_1_ctrl_is_std = 1'h0; // @[core.scala:158:24]
wire dec_uops_1_iw_p1_poisoned = 1'h0; // @[core.scala:158:24]
wire dec_uops_1_iw_p2_poisoned = 1'h0; // @[core.scala:158:24]
wire dec_uops_1_prs1_busy = 1'h0; // @[core.scala:158:24]
wire dec_uops_1_prs2_busy = 1'h0; // @[core.scala:158:24]
wire dec_uops_1_prs3_busy = 1'h0; // @[core.scala:158:24]
wire dec_uops_1_ppred_busy = 1'h0; // @[core.scala:158:24]
wire dec_uops_1_ldst_is_rs1 = 1'h0; // @[core.scala:158:24]
wire dec_uops_1_xcpt_ma_if = 1'h0; // @[core.scala:158:24]
wire dec_uops_2_ctrl_fcn_dw = 1'h0; // @[core.scala:158:24]
wire dec_uops_2_ctrl_is_load = 1'h0; // @[core.scala:158:24]
wire dec_uops_2_ctrl_is_sta = 1'h0; // @[core.scala:158:24]
wire dec_uops_2_ctrl_is_std = 1'h0; // @[core.scala:158:24]
wire dec_uops_2_iw_p1_poisoned = 1'h0; // @[core.scala:158:24]
wire dec_uops_2_iw_p2_poisoned = 1'h0; // @[core.scala:158:24]
wire dec_uops_2_prs1_busy = 1'h0; // @[core.scala:158:24]
wire dec_uops_2_prs2_busy = 1'h0; // @[core.scala:158:24]
wire dec_uops_2_prs3_busy = 1'h0; // @[core.scala:158:24]
wire dec_uops_2_ppred_busy = 1'h0; // @[core.scala:158:24]
wire dec_uops_2_ldst_is_rs1 = 1'h0; // @[core.scala:158:24]
wire dec_uops_2_xcpt_ma_if = 1'h0; // @[core.scala:158:24]
wire dis_uops_0_ppred_busy = 1'h0; // @[core.scala:167:24]
wire dis_uops_1_ppred_busy = 1'h0; // @[core.scala:167:24]
wire dis_uops_2_ppred_busy = 1'h0; // @[core.scala:167:24]
wire bypasses_0_bits_predicated = 1'h0; // @[core.scala:174:24]
wire bypasses_0_bits_fflags_valid = 1'h0; // @[core.scala:174:24]
wire bypasses_0_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:174:24]
wire bypasses_0_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:174:24]
wire bypasses_0_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:174:24]
wire bypasses_0_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:174:24]
wire bypasses_0_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:174:24]
wire bypasses_0_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:174:24]
wire bypasses_0_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:174:24]
wire bypasses_0_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:174:24]
wire bypasses_0_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:174:24]
wire bypasses_0_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:174:24]
wire bypasses_0_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:174:24]
wire bypasses_0_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:174:24]
wire bypasses_0_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:174:24]
wire bypasses_0_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:174:24]
wire bypasses_0_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:174:24]
wire bypasses_0_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:174:24]
wire bypasses_0_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:174:24]
wire bypasses_0_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:174:24]
wire bypasses_0_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:174:24]
wire bypasses_0_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:174:24]
wire bypasses_0_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:174:24]
wire bypasses_0_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:174:24]
wire bypasses_0_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:174:24]
wire bypasses_0_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:174:24]
wire bypasses_0_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:174:24]
wire bypasses_0_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:174:24]
wire bypasses_0_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:174:24]
wire bypasses_0_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:174:24]
wire bypasses_0_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:174:24]
wire bypasses_0_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:174:24]
wire bypasses_0_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:174:24]
wire bypasses_0_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:174:24]
wire bypasses_0_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:174:24]
wire bypasses_0_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:174:24]
wire bypasses_0_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:174:24]
wire bypasses_0_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:174:24]
wire bypasses_0_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:174:24]
wire bypasses_0_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:174:24]
wire bypasses_1_bits_predicated = 1'h0; // @[core.scala:174:24]
wire bypasses_1_bits_fflags_valid = 1'h0; // @[core.scala:174:24]
wire bypasses_1_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:174:24]
wire bypasses_1_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:174:24]
wire bypasses_1_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:174:24]
wire bypasses_1_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:174:24]
wire bypasses_1_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:174:24]
wire bypasses_1_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:174:24]
wire bypasses_1_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:174:24]
wire bypasses_1_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:174:24]
wire bypasses_1_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:174:24]
wire bypasses_1_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:174:24]
wire bypasses_1_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:174:24]
wire bypasses_1_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:174:24]
wire bypasses_1_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:174:24]
wire bypasses_1_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:174:24]
wire bypasses_1_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:174:24]
wire bypasses_1_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:174:24]
wire bypasses_1_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:174:24]
wire bypasses_1_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:174:24]
wire bypasses_1_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:174:24]
wire bypasses_1_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:174:24]
wire bypasses_1_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:174:24]
wire bypasses_1_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:174:24]
wire bypasses_1_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:174:24]
wire bypasses_1_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:174:24]
wire bypasses_1_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:174:24]
wire bypasses_1_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:174:24]
wire bypasses_1_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:174:24]
wire bypasses_1_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:174:24]
wire bypasses_1_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:174:24]
wire bypasses_1_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:174:24]
wire bypasses_1_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:174:24]
wire bypasses_1_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:174:24]
wire bypasses_1_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:174:24]
wire bypasses_1_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:174:24]
wire bypasses_1_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:174:24]
wire bypasses_1_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:174:24]
wire bypasses_1_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:174:24]
wire bypasses_1_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:174:24]
wire bypasses_2_bits_predicated = 1'h0; // @[core.scala:174:24]
wire bypasses_2_bits_fflags_valid = 1'h0; // @[core.scala:174:24]
wire bypasses_2_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:174:24]
wire bypasses_2_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:174:24]
wire bypasses_2_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:174:24]
wire bypasses_2_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:174:24]
wire bypasses_2_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:174:24]
wire bypasses_2_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:174:24]
wire bypasses_2_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:174:24]
wire bypasses_2_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:174:24]
wire bypasses_2_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:174:24]
wire bypasses_2_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:174:24]
wire bypasses_2_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:174:24]
wire bypasses_2_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:174:24]
wire bypasses_2_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:174:24]
wire bypasses_2_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:174:24]
wire bypasses_2_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:174:24]
wire bypasses_2_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:174:24]
wire bypasses_2_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:174:24]
wire bypasses_2_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:174:24]
wire bypasses_2_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:174:24]
wire bypasses_2_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:174:24]
wire bypasses_2_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:174:24]
wire bypasses_2_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:174:24]
wire bypasses_2_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:174:24]
wire bypasses_2_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:174:24]
wire bypasses_2_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:174:24]
wire bypasses_2_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:174:24]
wire bypasses_2_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:174:24]
wire bypasses_2_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:174:24]
wire bypasses_2_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:174:24]
wire bypasses_2_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:174:24]
wire bypasses_2_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:174:24]
wire bypasses_2_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:174:24]
wire bypasses_2_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:174:24]
wire bypasses_2_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:174:24]
wire bypasses_2_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:174:24]
wire bypasses_2_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:174:24]
wire bypasses_2_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:174:24]
wire bypasses_2_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:174:24]
wire bypasses_3_bits_predicated = 1'h0; // @[core.scala:174:24]
wire bypasses_3_bits_fflags_valid = 1'h0; // @[core.scala:174:24]
wire bypasses_3_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:174:24]
wire bypasses_3_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:174:24]
wire bypasses_3_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:174:24]
wire bypasses_3_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:174:24]
wire bypasses_3_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:174:24]
wire bypasses_3_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:174:24]
wire bypasses_3_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:174:24]
wire bypasses_3_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:174:24]
wire bypasses_3_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:174:24]
wire bypasses_3_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:174:24]
wire bypasses_3_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:174:24]
wire bypasses_3_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:174:24]
wire bypasses_3_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:174:24]
wire bypasses_3_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:174:24]
wire bypasses_3_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:174:24]
wire bypasses_3_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:174:24]
wire bypasses_3_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:174:24]
wire bypasses_3_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:174:24]
wire bypasses_3_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:174:24]
wire bypasses_3_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:174:24]
wire bypasses_3_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:174:24]
wire bypasses_3_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:174:24]
wire bypasses_3_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:174:24]
wire bypasses_3_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:174:24]
wire bypasses_3_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:174:24]
wire bypasses_3_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:174:24]
wire bypasses_3_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:174:24]
wire bypasses_3_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:174:24]
wire bypasses_3_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:174:24]
wire bypasses_3_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:174:24]
wire bypasses_3_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:174:24]
wire bypasses_3_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:174:24]
wire bypasses_3_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:174:24]
wire bypasses_3_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:174:24]
wire bypasses_3_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:174:24]
wire bypasses_3_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:174:24]
wire bypasses_3_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:174:24]
wire bypasses_3_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:174:24]
wire bypasses_4_bits_predicated = 1'h0; // @[core.scala:174:24]
wire bypasses_4_bits_fflags_valid = 1'h0; // @[core.scala:174:24]
wire bypasses_4_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:174:24]
wire bypasses_4_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:174:24]
wire bypasses_4_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:174:24]
wire bypasses_4_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:174:24]
wire bypasses_4_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:174:24]
wire bypasses_4_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:174:24]
wire bypasses_4_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:174:24]
wire bypasses_4_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:174:24]
wire bypasses_4_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:174:24]
wire bypasses_4_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:174:24]
wire bypasses_4_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:174:24]
wire bypasses_4_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:174:24]
wire bypasses_4_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:174:24]
wire bypasses_4_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:174:24]
wire bypasses_4_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:174:24]
wire bypasses_4_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:174:24]
wire bypasses_4_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:174:24]
wire bypasses_4_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:174:24]
wire bypasses_4_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:174:24]
wire bypasses_4_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:174:24]
wire bypasses_4_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:174:24]
wire bypasses_4_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:174:24]
wire bypasses_4_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:174:24]
wire bypasses_4_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:174:24]
wire bypasses_4_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:174:24]
wire bypasses_4_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:174:24]
wire bypasses_4_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:174:24]
wire bypasses_4_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:174:24]
wire bypasses_4_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:174:24]
wire bypasses_4_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:174:24]
wire bypasses_4_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:174:24]
wire bypasses_4_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:174:24]
wire bypasses_4_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:174:24]
wire bypasses_4_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:174:24]
wire bypasses_4_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:174:24]
wire bypasses_4_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:174:24]
wire bypasses_4_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:174:24]
wire bypasses_4_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:174:24]
wire pred_bypasses_0_bits_predicated = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_0_bits_fflags_valid = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_0_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_0_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_0_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_0_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_0_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_0_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_0_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_0_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_0_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_0_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_0_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_0_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_0_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_0_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_0_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_0_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_0_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_0_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_0_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_0_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_0_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_0_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_0_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_0_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_0_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_0_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_0_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_0_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_0_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_0_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_0_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_0_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_0_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_0_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_0_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_0_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_0_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:175:27]
wire pred_bypasses_0_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:175:27]
wire brupdate_b2_valid = 1'h0; // @[core.scala:188:23]
wire _use_this_mispredict_T_2 = 1'h0; // @[util.scala:363:52]
wire _hits_WIRE_0 = 1'h0; // @[Events.scala:13:33]
wire _hits_WIRE_1 = 1'h0; // @[Events.scala:13:33]
wire _hits_WIRE_2 = 1'h0; // @[Events.scala:13:33]
wire _hits_WIRE_3 = 1'h0; // @[Events.scala:13:33]
wire hits_0 = 1'h0; // @[Events.scala:13:25]
wire hits_1 = 1'h0; // @[Events.scala:13:25]
wire hits_2 = 1'h0; // @[Events.scala:13:25]
wire hits_3 = 1'h0; // @[Events.scala:13:25]
wire _hits_WIRE_1_0 = 1'h0; // @[Events.scala:13:33]
wire _hits_WIRE_1_1 = 1'h0; // @[Events.scala:13:33]
wire _hits_WIRE_1_2 = 1'h0; // @[Events.scala:13:33]
wire _hits_WIRE_1_3 = 1'h0; // @[Events.scala:13:33]
wire _hits_WIRE_1_4 = 1'h0; // @[Events.scala:13:33]
wire hits_1_0 = 1'h0; // @[Events.scala:13:25]
wire hits_1_1 = 1'h0; // @[Events.scala:13:25]
wire hits_1_2 = 1'h0; // @[Events.scala:13:25]
wire hits_1_3 = 1'h0; // @[Events.scala:13:25]
wire hits_1_4 = 1'h0; // @[Events.scala:13:25]
wire _hits_WIRE_2_0 = 1'h0; // @[Events.scala:13:33]
wire _hits_WIRE_2_1 = 1'h0; // @[Events.scala:13:33]
wire _hits_WIRE_2_2 = 1'h0; // @[Events.scala:13:33]
wire _hits_WIRE_2_3 = 1'h0; // @[Events.scala:13:33]
wire _hits_WIRE_2_4 = 1'h0; // @[Events.scala:13:33]
wire _hits_WIRE_2_5 = 1'h0; // @[Events.scala:13:33]
wire hits_2_0 = 1'h0; // @[Events.scala:13:25]
wire hits_2_1 = 1'h0; // @[Events.scala:13:25]
wire hits_2_2 = 1'h0; // @[Events.scala:13:25]
wire hits_2_3 = 1'h0; // @[Events.scala:13:25]
wire hits_2_4 = 1'h0; // @[Events.scala:13:25]
wire hits_2_5 = 1'h0; // @[Events.scala:13:25]
wire custom_csrs_csrs_0_stall = 1'h0; // @[core.scala:276:25]
wire custom_csrs_csrs_0_set = 1'h0; // @[core.scala:276:25]
wire custom_csrs_csrs_1_stall = 1'h0; // @[core.scala:276:25]
wire custom_csrs_csrs_1_set = 1'h0; // @[core.scala:276:25]
wire _new_ghist_WIRE_current_saw_branch_not_taken = 1'h0; // @[core.scala:406:44]
wire _new_ghist_WIRE_new_saw_branch_not_taken = 1'h0; // @[core.scala:406:44]
wire _new_ghist_WIRE_new_saw_branch_taken = 1'h0; // @[core.scala:406:44]
wire new_ghist_new_saw_branch_not_taken = 1'h0; // @[core.scala:406:29]
wire new_ghist_new_saw_branch_taken = 1'h0; // @[core.scala:406:29]
wire next_ghist_current_saw_branch_not_taken = 1'h0; // @[frontend.scala:87:27]
wire p_uop_is_rvc = 1'h0; // @[consts.scala:269:19]
wire p_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19]
wire p_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19]
wire p_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19]
wire p_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19]
wire p_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19]
wire p_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19]
wire p_uop_is_br = 1'h0; // @[consts.scala:269:19]
wire p_uop_is_jalr = 1'h0; // @[consts.scala:269:19]
wire p_uop_is_jal = 1'h0; // @[consts.scala:269:19]
wire p_uop_is_sfb = 1'h0; // @[consts.scala:269:19]
wire p_uop_edge_inst = 1'h0; // @[consts.scala:269:19]
wire p_uop_taken = 1'h0; // @[consts.scala:269:19]
wire p_uop_prs1_busy = 1'h0; // @[consts.scala:269:19]
wire p_uop_prs2_busy = 1'h0; // @[consts.scala:269:19]
wire p_uop_prs3_busy = 1'h0; // @[consts.scala:269:19]
wire p_uop_ppred_busy = 1'h0; // @[consts.scala:269:19]
wire p_uop_exception = 1'h0; // @[consts.scala:269:19]
wire p_uop_bypassable = 1'h0; // @[consts.scala:269:19]
wire p_uop_mem_signed = 1'h0; // @[consts.scala:269:19]
wire p_uop_is_fence = 1'h0; // @[consts.scala:269:19]
wire p_uop_is_fencei = 1'h0; // @[consts.scala:269:19]
wire p_uop_is_amo = 1'h0; // @[consts.scala:269:19]
wire p_uop_uses_ldq = 1'h0; // @[consts.scala:269:19]
wire p_uop_uses_stq = 1'h0; // @[consts.scala:269:19]
wire p_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19]
wire p_uop_is_unique = 1'h0; // @[consts.scala:269:19]
wire p_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19]
wire p_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19]
wire p_uop_ldst_val = 1'h0; // @[consts.scala:269:19]
wire p_uop_frs3_en = 1'h0; // @[consts.scala:269:19]
wire p_uop_fp_val = 1'h0; // @[consts.scala:269:19]
wire p_uop_fp_single = 1'h0; // @[consts.scala:269:19]
wire p_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19]
wire p_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19]
wire p_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19]
wire p_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19]
wire p_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19]
wire p_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18]
wire p_uop_cs_is_load = 1'h0; // @[consts.scala:279:18]
wire p_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18]
wire p_uop_cs_is_std = 1'h0; // @[consts.scala:279:18]
wire _dis_uops_0_ppred_busy_T_2 = 1'h0; // @[micro-op.scala:110:43]
wire _dis_uops_0_ppred_busy_T_3 = 1'h0; // @[core.scala:669:48]
wire p_uop_1_is_rvc = 1'h0; // @[consts.scala:269:19]
wire p_uop_1_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19]
wire p_uop_1_ctrl_is_load = 1'h0; // @[consts.scala:269:19]
wire p_uop_1_ctrl_is_sta = 1'h0; // @[consts.scala:269:19]
wire p_uop_1_ctrl_is_std = 1'h0; // @[consts.scala:269:19]
wire p_uop_1_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19]
wire p_uop_1_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19]
wire p_uop_1_is_br = 1'h0; // @[consts.scala:269:19]
wire p_uop_1_is_jalr = 1'h0; // @[consts.scala:269:19]
wire p_uop_1_is_jal = 1'h0; // @[consts.scala:269:19]
wire p_uop_1_is_sfb = 1'h0; // @[consts.scala:269:19]
wire p_uop_1_edge_inst = 1'h0; // @[consts.scala:269:19]
wire p_uop_1_taken = 1'h0; // @[consts.scala:269:19]
wire p_uop_1_prs1_busy = 1'h0; // @[consts.scala:269:19]
wire p_uop_1_prs2_busy = 1'h0; // @[consts.scala:269:19]
wire p_uop_1_prs3_busy = 1'h0; // @[consts.scala:269:19]
wire p_uop_1_ppred_busy = 1'h0; // @[consts.scala:269:19]
wire p_uop_1_exception = 1'h0; // @[consts.scala:269:19]
wire p_uop_1_bypassable = 1'h0; // @[consts.scala:269:19]
wire p_uop_1_mem_signed = 1'h0; // @[consts.scala:269:19]
wire p_uop_1_is_fence = 1'h0; // @[consts.scala:269:19]
wire p_uop_1_is_fencei = 1'h0; // @[consts.scala:269:19]
wire p_uop_1_is_amo = 1'h0; // @[consts.scala:269:19]
wire p_uop_1_uses_ldq = 1'h0; // @[consts.scala:269:19]
wire p_uop_1_uses_stq = 1'h0; // @[consts.scala:269:19]
wire p_uop_1_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19]
wire p_uop_1_is_unique = 1'h0; // @[consts.scala:269:19]
wire p_uop_1_flush_on_commit = 1'h0; // @[consts.scala:269:19]
wire p_uop_1_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19]
wire p_uop_1_ldst_val = 1'h0; // @[consts.scala:269:19]
wire p_uop_1_frs3_en = 1'h0; // @[consts.scala:269:19]
wire p_uop_1_fp_val = 1'h0; // @[consts.scala:269:19]
wire p_uop_1_fp_single = 1'h0; // @[consts.scala:269:19]
wire p_uop_1_xcpt_pf_if = 1'h0; // @[consts.scala:269:19]
wire p_uop_1_xcpt_ae_if = 1'h0; // @[consts.scala:269:19]
wire p_uop_1_xcpt_ma_if = 1'h0; // @[consts.scala:269:19]
wire p_uop_1_bp_debug_if = 1'h0; // @[consts.scala:269:19]
wire p_uop_1_bp_xcpt_if = 1'h0; // @[consts.scala:269:19]
wire p_uop_cs_1_fcn_dw = 1'h0; // @[consts.scala:279:18]
wire p_uop_cs_1_is_load = 1'h0; // @[consts.scala:279:18]
wire p_uop_cs_1_is_sta = 1'h0; // @[consts.scala:279:18]
wire p_uop_cs_1_is_std = 1'h0; // @[consts.scala:279:18]
wire _dis_uops_1_ppred_busy_T_2 = 1'h0; // @[micro-op.scala:110:43]
wire _dis_uops_1_ppred_busy_T_3 = 1'h0; // @[core.scala:669:48]
wire p_uop_2_is_rvc = 1'h0; // @[consts.scala:269:19]
wire p_uop_2_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19]
wire p_uop_2_ctrl_is_load = 1'h0; // @[consts.scala:269:19]
wire p_uop_2_ctrl_is_sta = 1'h0; // @[consts.scala:269:19]
wire p_uop_2_ctrl_is_std = 1'h0; // @[consts.scala:269:19]
wire p_uop_2_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19]
wire p_uop_2_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19]
wire p_uop_2_is_br = 1'h0; // @[consts.scala:269:19]
wire p_uop_2_is_jalr = 1'h0; // @[consts.scala:269:19]
wire p_uop_2_is_jal = 1'h0; // @[consts.scala:269:19]
wire p_uop_2_is_sfb = 1'h0; // @[consts.scala:269:19]
wire p_uop_2_edge_inst = 1'h0; // @[consts.scala:269:19]
wire p_uop_2_taken = 1'h0; // @[consts.scala:269:19]
wire p_uop_2_prs1_busy = 1'h0; // @[consts.scala:269:19]
wire p_uop_2_prs2_busy = 1'h0; // @[consts.scala:269:19]
wire p_uop_2_prs3_busy = 1'h0; // @[consts.scala:269:19]
wire p_uop_2_ppred_busy = 1'h0; // @[consts.scala:269:19]
wire p_uop_2_exception = 1'h0; // @[consts.scala:269:19]
wire p_uop_2_bypassable = 1'h0; // @[consts.scala:269:19]
wire p_uop_2_mem_signed = 1'h0; // @[consts.scala:269:19]
wire p_uop_2_is_fence = 1'h0; // @[consts.scala:269:19]
wire p_uop_2_is_fencei = 1'h0; // @[consts.scala:269:19]
wire p_uop_2_is_amo = 1'h0; // @[consts.scala:269:19]
wire p_uop_2_uses_ldq = 1'h0; // @[consts.scala:269:19]
wire p_uop_2_uses_stq = 1'h0; // @[consts.scala:269:19]
wire p_uop_2_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19]
wire p_uop_2_is_unique = 1'h0; // @[consts.scala:269:19]
wire p_uop_2_flush_on_commit = 1'h0; // @[consts.scala:269:19]
wire p_uop_2_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19]
wire p_uop_2_ldst_val = 1'h0; // @[consts.scala:269:19]
wire p_uop_2_frs3_en = 1'h0; // @[consts.scala:269:19]
wire p_uop_2_fp_val = 1'h0; // @[consts.scala:269:19]
wire p_uop_2_fp_single = 1'h0; // @[consts.scala:269:19]
wire p_uop_2_xcpt_pf_if = 1'h0; // @[consts.scala:269:19]
wire p_uop_2_xcpt_ae_if = 1'h0; // @[consts.scala:269:19]
wire p_uop_2_xcpt_ma_if = 1'h0; // @[consts.scala:269:19]
wire p_uop_2_bp_debug_if = 1'h0; // @[consts.scala:269:19]
wire p_uop_2_bp_xcpt_if = 1'h0; // @[consts.scala:269:19]
wire p_uop_cs_2_fcn_dw = 1'h0; // @[consts.scala:279:18]
wire p_uop_cs_2_is_load = 1'h0; // @[consts.scala:279:18]
wire p_uop_cs_2_is_sta = 1'h0; // @[consts.scala:279:18]
wire p_uop_cs_2_is_std = 1'h0; // @[consts.scala:279:18]
wire _dis_uops_2_ppred_busy_T_2 = 1'h0; // @[micro-op.scala:110:43]
wire _dis_uops_2_ppred_busy_T_3 = 1'h0; // @[core.scala:669:48]
wire _wait_for_rocc_T_1 = 1'h0; // @[core.scala:689:90]
wire wait_for_rocc_0 = 1'h0; // @[core.scala:689:73]
wire _wait_for_rocc_T_3 = 1'h0; // @[core.scala:689:90]
wire wait_for_rocc_1 = 1'h0; // @[core.scala:689:73]
wire _wait_for_rocc_T_5 = 1'h0; // @[core.scala:689:90]
wire wait_for_rocc_2 = 1'h0; // @[core.scala:689:73]
wire fast_wakeup_bits_predicated = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_bits_fflags_valid = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:814:29]
wire slow_wakeup_bits_predicated = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_bits_fflags_valid = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:815:29]
wire fast_wakeup_1_bits_predicated = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_1_bits_fflags_valid = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_1_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_1_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_1_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_1_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_1_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_1_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_1_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_1_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_1_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_1_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_1_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_1_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_1_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_1_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_1_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_1_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_1_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_1_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_1_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_1_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_1_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_1_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_1_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_1_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_1_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_1_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_1_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_1_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_1_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_1_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_1_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_1_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_1_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_1_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_1_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_1_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_1_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_1_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:814:29]
wire slow_wakeup_1_bits_predicated = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_1_bits_fflags_valid = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_1_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_1_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_1_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_1_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_1_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_1_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_1_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_1_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_1_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_1_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_1_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_1_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_1_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_1_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_1_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_1_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_1_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_1_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_1_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_1_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_1_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_1_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_1_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_1_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_1_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_1_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_1_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_1_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_1_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_1_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_1_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_1_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_1_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_1_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_1_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_1_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_1_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_1_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:815:29]
wire fast_wakeup_2_bits_predicated = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_2_bits_fflags_valid = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_2_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_2_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_2_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_2_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_2_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_2_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_2_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_2_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_2_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_2_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_2_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_2_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_2_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_2_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_2_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_2_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_2_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_2_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_2_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_2_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_2_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_2_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_2_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_2_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_2_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_2_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_2_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_2_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_2_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_2_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_2_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_2_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_2_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_2_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_2_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_2_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_2_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:814:29]
wire fast_wakeup_2_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:814:29]
wire slow_wakeup_2_bits_predicated = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_2_bits_fflags_valid = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_2_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_2_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_2_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_2_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_2_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_2_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_2_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_2_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_2_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_2_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_2_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_2_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_2_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_2_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_2_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_2_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_2_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_2_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_2_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_2_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_2_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_2_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_2_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_2_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_2_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_2_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_2_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_2_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_2_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_2_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_2_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_2_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_2_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_2_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_2_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_2_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_2_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:815:29]
wire slow_wakeup_2_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:815:29]
wire _pred_wakeup_valid_T_1 = 1'h0; // @[micro-op.scala:109:42]
wire _pred_wakeup_valid_T_2 = 1'h0; // @[core.scala:862:50]
wire _pred_wakeup_valid_T_6 = 1'h0; // @[core.scala:863:58]
wire _rob_io_csr_replay_valid_T = 1'h0; // @[core.scala:1008:58]
wire _large_T_3 = 1'h0; // @[Counters.scala:68:28]
wire coreMonitorBundle_excpt = 1'h0; // @[core.scala:1405:31]
wire coreMonitorBundle_valid = 1'h0; // @[core.scala:1405:31]
wire coreMonitorBundle_wrenx = 1'h0; // @[core.scala:1405:31]
wire coreMonitorBundle_wrenf = 1'h0; // @[core.scala:1405:31]
wire _io_rocc_exception_T = 1'h0; // @[core.scala:1424:61]
wire _io_rocc_exception_T_1 = 1'h0; // @[core.scala:1424:41]
wire [15:0] io_ifu_fetchpacket_bits_uops_0_bits_br_mask = 16'h0; // @[core.scala:51:7]
wire [15:0] io_ifu_fetchpacket_bits_uops_1_bits_br_mask = 16'h0; // @[core.scala:51:7]
wire [15:0] io_ifu_fetchpacket_bits_uops_2_bits_br_mask = 16'h0; // @[core.scala:51:7]
wire [15:0] io_ptw_ptbr_asid = 16'h0; // @[core.scala:51:7]
wire [15:0] io_ptw_hgatp_asid = 16'h0; // @[core.scala:51:7]
wire [15:0] io_ptw_vsatp_asid = 16'h0; // @[core.scala:51:7]
wire [15:0] io_lsu_exe_0_req_bits_fflags_bits_uop_br_mask = 16'h0; // @[core.scala:51:7]
wire [15:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_br_mask = 16'h0; // @[core.scala:51:7]
wire [15:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_br_mask = 16'h0; // @[core.scala:51:7]
wire [15:0] io_ptw_tlb_ptbr_asid = 16'h0; // @[core.scala:51:7]
wire [15:0] io_ptw_tlb_hgatp_asid = 16'h0; // @[core.scala:51:7]
wire [15:0] io_ptw_tlb_vsatp_asid = 16'h0; // @[core.scala:51:7]
wire [15:0] int_iss_wakeups_1_bits_fflags_bits_uop_br_mask = 16'h0; // @[core.scala:147:30]
wire [15:0] int_iss_wakeups_2_bits_fflags_bits_uop_br_mask = 16'h0; // @[core.scala:147:30]
wire [15:0] int_iss_wakeups_3_bits_fflags_bits_uop_br_mask = 16'h0; // @[core.scala:147:30]
wire [15:0] int_iss_wakeups_4_bits_fflags_bits_uop_br_mask = 16'h0; // @[core.scala:147:30]
wire [15:0] int_iss_wakeups_5_bits_fflags_bits_uop_br_mask = 16'h0; // @[core.scala:147:30]
wire [15:0] int_iss_wakeups_6_bits_fflags_bits_uop_br_mask = 16'h0; // @[core.scala:147:30]
wire [15:0] int_ren_wakeups_1_bits_fflags_bits_uop_br_mask = 16'h0; // @[core.scala:148:30]
wire [15:0] int_ren_wakeups_2_bits_fflags_bits_uop_br_mask = 16'h0; // @[core.scala:148:30]
wire [15:0] int_ren_wakeups_3_bits_fflags_bits_uop_br_mask = 16'h0; // @[core.scala:148:30]
wire [15:0] int_ren_wakeups_4_bits_fflags_bits_uop_br_mask = 16'h0; // @[core.scala:148:30]
wire [15:0] int_ren_wakeups_5_bits_fflags_bits_uop_br_mask = 16'h0; // @[core.scala:148:30]
wire [15:0] int_ren_wakeups_6_bits_fflags_bits_uop_br_mask = 16'h0; // @[core.scala:148:30]
wire [15:0] pred_wakeup_bits_fflags_bits_uop_br_mask = 16'h0; // @[core.scala:149:26]
wire [15:0] bypasses_0_bits_fflags_bits_uop_br_mask = 16'h0; // @[core.scala:174:24]
wire [15:0] bypasses_1_bits_fflags_bits_uop_br_mask = 16'h0; // @[core.scala:174:24]
wire [15:0] bypasses_2_bits_fflags_bits_uop_br_mask = 16'h0; // @[core.scala:174:24]
wire [15:0] bypasses_3_bits_fflags_bits_uop_br_mask = 16'h0; // @[core.scala:174:24]
wire [15:0] bypasses_4_bits_fflags_bits_uop_br_mask = 16'h0; // @[core.scala:174:24]
wire [15:0] pred_bypasses_0_bits_fflags_bits_uop_br_mask = 16'h0; // @[core.scala:175:27]
wire [15:0] p_uop_br_mask = 16'h0; // @[consts.scala:269:19]
wire [15:0] p_uop_1_br_mask = 16'h0; // @[consts.scala:269:19]
wire [15:0] p_uop_2_br_mask = 16'h0; // @[consts.scala:269:19]
wire [15:0] fast_wakeup_bits_fflags_bits_uop_br_mask = 16'h0; // @[core.scala:814:29]
wire [15:0] slow_wakeup_bits_fflags_bits_uop_br_mask = 16'h0; // @[core.scala:815:29]
wire [15:0] fast_wakeup_1_bits_fflags_bits_uop_br_mask = 16'h0; // @[core.scala:814:29]
wire [15:0] slow_wakeup_1_bits_fflags_bits_uop_br_mask = 16'h0; // @[core.scala:815:29]
wire [15:0] fast_wakeup_2_bits_fflags_bits_uop_br_mask = 16'h0; // @[core.scala:814:29]
wire [15:0] slow_wakeup_2_bits_fflags_bits_uop_br_mask = 16'h0; // @[core.scala:815:29]
wire [19:0] io_ifu_fetchpacket_bits_uops_0_bits_imm_packed = 20'h0; // @[core.scala:51:7]
wire [19:0] io_ifu_fetchpacket_bits_uops_1_bits_imm_packed = 20'h0; // @[core.scala:51:7]
wire [19:0] io_ifu_fetchpacket_bits_uops_2_bits_imm_packed = 20'h0; // @[core.scala:51:7]
wire [19:0] io_lsu_exe_0_req_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:51:7]
wire [19:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:51:7]
wire [19:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:51:7]
wire [19:0] int_iss_wakeups_1_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:147:30]
wire [19:0] int_iss_wakeups_2_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:147:30]
wire [19:0] int_iss_wakeups_3_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:147:30]
wire [19:0] int_iss_wakeups_4_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:147:30]
wire [19:0] int_iss_wakeups_5_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:147:30]
wire [19:0] int_iss_wakeups_6_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:147:30]
wire [19:0] int_ren_wakeups_1_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:148:30]
wire [19:0] int_ren_wakeups_2_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:148:30]
wire [19:0] int_ren_wakeups_3_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:148:30]
wire [19:0] int_ren_wakeups_4_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:148:30]
wire [19:0] int_ren_wakeups_5_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:148:30]
wire [19:0] int_ren_wakeups_6_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:148:30]
wire [19:0] pred_wakeup_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:149:26]
wire [19:0] bypasses_0_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:174:24]
wire [19:0] bypasses_1_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:174:24]
wire [19:0] bypasses_2_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:174:24]
wire [19:0] bypasses_3_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:174:24]
wire [19:0] bypasses_4_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:174:24]
wire [19:0] pred_bypasses_0_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:175:27]
wire [19:0] p_uop_imm_packed = 20'h0; // @[consts.scala:269:19]
wire [19:0] p_uop_1_imm_packed = 20'h0; // @[consts.scala:269:19]
wire [19:0] p_uop_2_imm_packed = 20'h0; // @[consts.scala:269:19]
wire [19:0] fast_wakeup_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:814:29]
wire [19:0] slow_wakeup_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:815:29]
wire [19:0] fast_wakeup_1_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:814:29]
wire [19:0] slow_wakeup_1_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:815:29]
wire [19:0] fast_wakeup_2_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:814:29]
wire [19:0] slow_wakeup_2_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:815:29]
wire [11:0] io_ifu_fetchpacket_bits_uops_0_bits_csr_addr = 12'h0; // @[core.scala:51:7]
wire [11:0] io_ifu_fetchpacket_bits_uops_1_bits_csr_addr = 12'h0; // @[core.scala:51:7]
wire [11:0] io_ifu_fetchpacket_bits_uops_2_bits_csr_addr = 12'h0; // @[core.scala:51:7]
wire [11:0] io_lsu_exe_0_req_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:51:7]
wire [11:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:51:7]
wire [11:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:51:7]
wire [11:0] int_iss_wakeups_1_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:147:30]
wire [11:0] int_iss_wakeups_2_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:147:30]
wire [11:0] int_iss_wakeups_3_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:147:30]
wire [11:0] int_iss_wakeups_4_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:147:30]
wire [11:0] int_iss_wakeups_5_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:147:30]
wire [11:0] int_iss_wakeups_6_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:147:30]
wire [11:0] int_ren_wakeups_1_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:148:30]
wire [11:0] int_ren_wakeups_2_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:148:30]
wire [11:0] int_ren_wakeups_3_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:148:30]
wire [11:0] int_ren_wakeups_4_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:148:30]
wire [11:0] int_ren_wakeups_5_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:148:30]
wire [11:0] int_ren_wakeups_6_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:148:30]
wire [11:0] pred_wakeup_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:149:26]
wire [11:0] dec_uops_0_csr_addr = 12'h0; // @[core.scala:158:24]
wire [11:0] dec_uops_1_csr_addr = 12'h0; // @[core.scala:158:24]
wire [11:0] dec_uops_2_csr_addr = 12'h0; // @[core.scala:158:24]
wire [11:0] bypasses_0_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:174:24]
wire [11:0] bypasses_1_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:174:24]
wire [11:0] bypasses_2_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:174:24]
wire [11:0] bypasses_3_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:174:24]
wire [11:0] bypasses_4_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:174:24]
wire [11:0] pred_bypasses_0_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:175:27]
wire [11:0] p_uop_csr_addr = 12'h0; // @[consts.scala:269:19]
wire [11:0] p_uop_1_csr_addr = 12'h0; // @[consts.scala:269:19]
wire [11:0] p_uop_2_csr_addr = 12'h0; // @[consts.scala:269:19]
wire [11:0] fast_wakeup_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:814:29]
wire [11:0] slow_wakeup_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:815:29]
wire [11:0] fast_wakeup_1_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:814:29]
wire [11:0] slow_wakeup_1_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:815:29]
wire [11:0] fast_wakeup_2_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:814:29]
wire [11:0] slow_wakeup_2_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:815:29]
wire [63:0] io_ifu_fetchpacket_bits_uops_0_bits_exc_cause = 64'h0; // @[core.scala:51:7]
wire [63:0] io_ifu_fetchpacket_bits_uops_1_bits_exc_cause = 64'h0; // @[core.scala:51:7]
wire [63:0] io_ifu_fetchpacket_bits_uops_2_bits_exc_cause = 64'h0; // @[core.scala:51:7]
wire [63:0] io_ifu_get_pc_0_ghist_old_history = 64'h0; // @[core.scala:51:7]
wire [63:0] io_ptw_customCSRs_csrs_0_wdata = 64'h0; // @[core.scala:51:7]
wire [63:0] io_ptw_customCSRs_csrs_0_value = 64'h0; // @[core.scala:51:7]
wire [63:0] io_ptw_customCSRs_csrs_0_sdata = 64'h0; // @[core.scala:51:7]
wire [63:0] io_ptw_customCSRs_csrs_1_wdata = 64'h0; // @[core.scala:51:7]
wire [63:0] io_ptw_customCSRs_csrs_1_value = 64'h0; // @[core.scala:51:7]
wire [63:0] io_ptw_customCSRs_csrs_1_sdata = 64'h0; // @[core.scala:51:7]
wire [63:0] io_rocc_cmd_bits_rs1 = 64'h0; // @[core.scala:51:7]
wire [63:0] io_rocc_cmd_bits_rs2 = 64'h0; // @[core.scala:51:7]
wire [63:0] io_rocc_resp_bits_data = 64'h0; // @[core.scala:51:7]
wire [63:0] io_rocc_mem_req_bits_data = 64'h0; // @[core.scala:51:7]
wire [63:0] io_rocc_mem_s1_data_data = 64'h0; // @[core.scala:51:7]
wire [63:0] io_rocc_mem_resp_bits_data = 64'h0; // @[core.scala:51:7]
wire [63:0] io_rocc_mem_resp_bits_data_word_bypass = 64'h0; // @[core.scala:51:7]
wire [63:0] io_rocc_mem_resp_bits_data_raw = 64'h0; // @[core.scala:51:7]
wire [63:0] io_rocc_mem_resp_bits_store_data = 64'h0; // @[core.scala:51:7]
wire [63:0] io_lsu_exe_0_req_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:51:7]
wire [63:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:51:7]
wire [63:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:51:7]
wire [63:0] io_ptw_tlb_customCSRs_csrs_0_wdata = 64'h0; // @[core.scala:51:7]
wire [63:0] io_ptw_tlb_customCSRs_csrs_0_value = 64'h0; // @[core.scala:51:7]
wire [63:0] io_ptw_tlb_customCSRs_csrs_0_sdata = 64'h0; // @[core.scala:51:7]
wire [63:0] io_ptw_tlb_customCSRs_csrs_1_wdata = 64'h0; // @[core.scala:51:7]
wire [63:0] io_ptw_tlb_customCSRs_csrs_1_value = 64'h0; // @[core.scala:51:7]
wire [63:0] io_ptw_tlb_customCSRs_csrs_1_sdata = 64'h0; // @[core.scala:51:7]
wire [63:0] io_trace_insns_0_cause = 64'h0; // @[core.scala:51:7]
wire [63:0] io_trace_insns_1_cause = 64'h0; // @[core.scala:51:7]
wire [63:0] io_trace_insns_2_cause = 64'h0; // @[core.scala:51:7]
wire [63:0] int_iss_wakeups_1_bits_data = 64'h0; // @[core.scala:147:30]
wire [63:0] int_iss_wakeups_1_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:147:30]
wire [63:0] int_iss_wakeups_2_bits_data = 64'h0; // @[core.scala:147:30]
wire [63:0] int_iss_wakeups_2_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:147:30]
wire [63:0] int_iss_wakeups_3_bits_data = 64'h0; // @[core.scala:147:30]
wire [63:0] int_iss_wakeups_3_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:147:30]
wire [63:0] int_iss_wakeups_4_bits_data = 64'h0; // @[core.scala:147:30]
wire [63:0] int_iss_wakeups_4_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:147:30]
wire [63:0] int_iss_wakeups_5_bits_data = 64'h0; // @[core.scala:147:30]
wire [63:0] int_iss_wakeups_5_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:147:30]
wire [63:0] int_iss_wakeups_6_bits_data = 64'h0; // @[core.scala:147:30]
wire [63:0] int_iss_wakeups_6_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:147:30]
wire [63:0] int_ren_wakeups_1_bits_data = 64'h0; // @[core.scala:148:30]
wire [63:0] int_ren_wakeups_1_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:148:30]
wire [63:0] int_ren_wakeups_2_bits_data = 64'h0; // @[core.scala:148:30]
wire [63:0] int_ren_wakeups_2_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:148:30]
wire [63:0] int_ren_wakeups_3_bits_data = 64'h0; // @[core.scala:148:30]
wire [63:0] int_ren_wakeups_3_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:148:30]
wire [63:0] int_ren_wakeups_4_bits_data = 64'h0; // @[core.scala:148:30]
wire [63:0] int_ren_wakeups_4_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:148:30]
wire [63:0] int_ren_wakeups_5_bits_data = 64'h0; // @[core.scala:148:30]
wire [63:0] int_ren_wakeups_5_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:148:30]
wire [63:0] int_ren_wakeups_6_bits_data = 64'h0; // @[core.scala:148:30]
wire [63:0] int_ren_wakeups_6_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:148:30]
wire [63:0] pred_wakeup_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:149:26]
wire [63:0] bypasses_0_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:174:24]
wire [63:0] bypasses_1_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:174:24]
wire [63:0] bypasses_2_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:174:24]
wire [63:0] bypasses_3_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:174:24]
wire [63:0] bypasses_4_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:174:24]
wire [63:0] pred_bypasses_0_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:175:27]
wire [63:0] custom_csrs_csrs_0_sdata = 64'h0; // @[core.scala:276:25]
wire [63:0] custom_csrs_csrs_1_sdata = 64'h0; // @[core.scala:276:25]
wire [63:0] _new_ghist_WIRE_old_history = 64'h0; // @[core.scala:406:44]
wire [63:0] new_ghist_old_history = 64'h0; // @[core.scala:406:29]
wire [63:0] p_uop_exc_cause = 64'h0; // @[consts.scala:269:19]
wire [63:0] p_uop_1_exc_cause = 64'h0; // @[consts.scala:269:19]
wire [63:0] p_uop_2_exc_cause = 64'h0; // @[consts.scala:269:19]
wire [63:0] fast_wakeup_bits_data = 64'h0; // @[core.scala:814:29]
wire [63:0] fast_wakeup_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:814:29]
wire [63:0] slow_wakeup_bits_data = 64'h0; // @[core.scala:815:29]
wire [63:0] slow_wakeup_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:815:29]
wire [63:0] fast_wakeup_1_bits_data = 64'h0; // @[core.scala:814:29]
wire [63:0] fast_wakeup_1_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:814:29]
wire [63:0] slow_wakeup_1_bits_data = 64'h0; // @[core.scala:815:29]
wire [63:0] slow_wakeup_1_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:815:29]
wire [63:0] fast_wakeup_2_bits_data = 64'h0; // @[core.scala:814:29]
wire [63:0] fast_wakeup_2_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:814:29]
wire [63:0] slow_wakeup_2_bits_data = 64'h0; // @[core.scala:815:29]
wire [63:0] slow_wakeup_2_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:815:29]
wire [63:0] coreMonitorBundle_hartid = 64'h0; // @[core.scala:1405:31]
wire [63:0] coreMonitorBundle_pc = 64'h0; // @[core.scala:1405:31]
wire [63:0] coreMonitorBundle_wrdata = 64'h0; // @[core.scala:1405:31]
wire [63:0] coreMonitorBundle_rd0val = 64'h0; // @[core.scala:1405:31]
wire [63:0] coreMonitorBundle_rd1val = 64'h0; // @[core.scala:1405:31]
wire [5:0] io_ifu_fetchpacket_bits_uops_0_bits_ldst = 6'h0; // @[core.scala:51:7]
wire [5:0] io_ifu_fetchpacket_bits_uops_0_bits_lrs1 = 6'h0; // @[core.scala:51:7]
wire [5:0] io_ifu_fetchpacket_bits_uops_0_bits_lrs2 = 6'h0; // @[core.scala:51:7]
wire [5:0] io_ifu_fetchpacket_bits_uops_0_bits_lrs3 = 6'h0; // @[core.scala:51:7]
wire [5:0] io_ifu_fetchpacket_bits_uops_1_bits_ldst = 6'h0; // @[core.scala:51:7]
wire [5:0] io_ifu_fetchpacket_bits_uops_1_bits_lrs1 = 6'h0; // @[core.scala:51:7]
wire [5:0] io_ifu_fetchpacket_bits_uops_1_bits_lrs2 = 6'h0; // @[core.scala:51:7]
wire [5:0] io_ifu_fetchpacket_bits_uops_1_bits_lrs3 = 6'h0; // @[core.scala:51:7]
wire [5:0] io_ifu_fetchpacket_bits_uops_2_bits_ldst = 6'h0; // @[core.scala:51:7]
wire [5:0] io_ifu_fetchpacket_bits_uops_2_bits_lrs1 = 6'h0; // @[core.scala:51:7]
wire [5:0] io_ifu_fetchpacket_bits_uops_2_bits_lrs2 = 6'h0; // @[core.scala:51:7]
wire [5:0] io_ifu_fetchpacket_bits_uops_2_bits_lrs3 = 6'h0; // @[core.scala:51:7]
wire [5:0] io_ptw_hstatus_vgein = 6'h0; // @[core.scala:51:7]
wire [5:0] io_lsu_exe_0_req_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:51:7]
wire [5:0] io_lsu_exe_0_req_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:51:7]
wire [5:0] io_lsu_exe_0_req_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:51:7]
wire [5:0] io_lsu_exe_0_req_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:51:7]
wire [5:0] io_lsu_exe_0_req_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:51:7]
wire [5:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:51:7]
wire [5:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:51:7]
wire [5:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:51:7]
wire [5:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:51:7]
wire [5:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:51:7]
wire [5:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:51:7]
wire [5:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:51:7]
wire [5:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:51:7]
wire [5:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:51:7]
wire [5:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:51:7]
wire [5:0] io_ptw_tlb_hstatus_vgein = 6'h0; // @[core.scala:51:7]
wire [5:0] int_iss_wakeups_1_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_1_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_1_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_1_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_1_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_2_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_2_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_2_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_2_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_2_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_3_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_3_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_3_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_3_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_3_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_4_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_4_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_4_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_4_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_4_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_5_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_5_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_5_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_5_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_5_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_6_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_6_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_6_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_6_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_6_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:147:30]
wire [5:0] int_ren_wakeups_1_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_1_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_1_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_1_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_1_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_2_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_2_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_2_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_2_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_2_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_3_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_3_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_3_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_3_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_3_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_4_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_4_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_4_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_4_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_4_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_5_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_5_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_5_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_5_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_5_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_6_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_6_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_6_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_6_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_6_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:148:30]
wire [5:0] pred_wakeup_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:149:26]
wire [5:0] pred_wakeup_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:149:26]
wire [5:0] pred_wakeup_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:149:26]
wire [5:0] pred_wakeup_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:149:26]
wire [5:0] pred_wakeup_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:149:26]
wire [5:0] bypasses_0_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:174:24]
wire [5:0] bypasses_0_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:174:24]
wire [5:0] bypasses_0_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:174:24]
wire [5:0] bypasses_0_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:174:24]
wire [5:0] bypasses_0_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:174:24]
wire [5:0] bypasses_1_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:174:24]
wire [5:0] bypasses_1_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:174:24]
wire [5:0] bypasses_1_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:174:24]
wire [5:0] bypasses_1_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:174:24]
wire [5:0] bypasses_1_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:174:24]
wire [5:0] bypasses_2_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:174:24]
wire [5:0] bypasses_2_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:174:24]
wire [5:0] bypasses_2_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:174:24]
wire [5:0] bypasses_2_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:174:24]
wire [5:0] bypasses_2_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:174:24]
wire [5:0] bypasses_3_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:174:24]
wire [5:0] bypasses_3_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:174:24]
wire [5:0] bypasses_3_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:174:24]
wire [5:0] bypasses_3_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:174:24]
wire [5:0] bypasses_3_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:174:24]
wire [5:0] bypasses_4_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:174:24]
wire [5:0] bypasses_4_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:174:24]
wire [5:0] bypasses_4_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:174:24]
wire [5:0] bypasses_4_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:174:24]
wire [5:0] bypasses_4_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:174:24]
wire [5:0] pred_bypasses_0_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:175:27]
wire [5:0] pred_bypasses_0_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:175:27]
wire [5:0] pred_bypasses_0_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:175:27]
wire [5:0] pred_bypasses_0_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:175:27]
wire [5:0] pred_bypasses_0_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:175:27]
wire [5:0] p_uop_pc_lob = 6'h0; // @[consts.scala:269:19]
wire [5:0] p_uop_ldst = 6'h0; // @[consts.scala:269:19]
wire [5:0] p_uop_lrs1 = 6'h0; // @[consts.scala:269:19]
wire [5:0] p_uop_lrs2 = 6'h0; // @[consts.scala:269:19]
wire [5:0] p_uop_lrs3 = 6'h0; // @[consts.scala:269:19]
wire [5:0] p_uop_1_pc_lob = 6'h0; // @[consts.scala:269:19]
wire [5:0] p_uop_1_ldst = 6'h0; // @[consts.scala:269:19]
wire [5:0] p_uop_1_lrs1 = 6'h0; // @[consts.scala:269:19]
wire [5:0] p_uop_1_lrs2 = 6'h0; // @[consts.scala:269:19]
wire [5:0] p_uop_1_lrs3 = 6'h0; // @[consts.scala:269:19]
wire [5:0] p_uop_2_pc_lob = 6'h0; // @[consts.scala:269:19]
wire [5:0] p_uop_2_ldst = 6'h0; // @[consts.scala:269:19]
wire [5:0] p_uop_2_lrs1 = 6'h0; // @[consts.scala:269:19]
wire [5:0] p_uop_2_lrs2 = 6'h0; // @[consts.scala:269:19]
wire [5:0] p_uop_2_lrs3 = 6'h0; // @[consts.scala:269:19]
wire [5:0] fast_wakeup_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:814:29]
wire [5:0] fast_wakeup_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:814:29]
wire [5:0] fast_wakeup_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:814:29]
wire [5:0] fast_wakeup_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:814:29]
wire [5:0] fast_wakeup_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:814:29]
wire [5:0] slow_wakeup_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:815:29]
wire [5:0] slow_wakeup_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:815:29]
wire [5:0] slow_wakeup_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:815:29]
wire [5:0] slow_wakeup_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:815:29]
wire [5:0] slow_wakeup_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:815:29]
wire [5:0] fast_wakeup_1_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:814:29]
wire [5:0] fast_wakeup_1_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:814:29]
wire [5:0] fast_wakeup_1_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:814:29]
wire [5:0] fast_wakeup_1_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:814:29]
wire [5:0] fast_wakeup_1_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:814:29]
wire [5:0] slow_wakeup_1_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:815:29]
wire [5:0] slow_wakeup_1_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:815:29]
wire [5:0] slow_wakeup_1_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:815:29]
wire [5:0] slow_wakeup_1_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:815:29]
wire [5:0] slow_wakeup_1_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:815:29]
wire [5:0] fast_wakeup_2_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:814:29]
wire [5:0] fast_wakeup_2_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:814:29]
wire [5:0] fast_wakeup_2_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:814:29]
wire [5:0] fast_wakeup_2_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:814:29]
wire [5:0] fast_wakeup_2_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:814:29]
wire [5:0] slow_wakeup_2_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:815:29]
wire [5:0] slow_wakeup_2_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:815:29]
wire [5:0] slow_wakeup_2_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:815:29]
wire [5:0] slow_wakeup_2_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:815:29]
wire [5:0] slow_wakeup_2_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:815:29]
wire [31:0] io_ifu_status_isa = 32'h14112D; // @[core.scala:51:7]
wire [31:0] io_ptw_status_isa = 32'h14112D; // @[core.scala:51:7]
wire [31:0] io_ptw_tlb_status_isa = 32'h14112D; // @[core.scala:51:7]
wire [22:0] io_ifu_status_zero2 = 23'h0; // @[core.scala:51:7]
wire [22:0] io_ptw_status_zero2 = 23'h0; // @[core.scala:51:7]
wire [22:0] io_ptw_gstatus_zero2 = 23'h0; // @[core.scala:51:7]
wire [22:0] io_rocc_cmd_bits_status_zero2 = 23'h0; // @[core.scala:51:7]
wire [22:0] io_ptw_tlb_status_zero2 = 23'h0; // @[core.scala:51:7]
wire [22:0] io_ptw_tlb_gstatus_zero2 = 23'h0; // @[core.scala:51:7]
wire [7:0] io_ifu_status_zero1 = 8'h0; // @[core.scala:51:7]
wire [7:0] io_ptw_status_zero1 = 8'h0; // @[core.scala:51:7]
wire [7:0] io_ptw_gstatus_zero1 = 8'h0; // @[core.scala:51:7]
wire [7:0] io_rocc_cmd_bits_status_zero1 = 8'h0; // @[core.scala:51:7]
wire [7:0] io_rocc_mem_req_bits_mask = 8'h0; // @[core.scala:51:7]
wire [7:0] io_rocc_mem_s1_data_mask = 8'h0; // @[core.scala:51:7]
wire [7:0] io_rocc_mem_resp_bits_mask = 8'h0; // @[core.scala:51:7]
wire [7:0] io_ptw_tlb_status_zero1 = 8'h0; // @[core.scala:51:7]
wire [7:0] io_ptw_tlb_gstatus_zero1 = 8'h0; // @[core.scala:51:7]
wire [39:0] io_rocc_mem_req_bits_addr = 40'h0; // @[core.scala:51:7]
wire [39:0] io_rocc_mem_resp_bits_addr = 40'h0; // @[core.scala:51:7]
wire [39:0] io_rocc_mem_s2_gpa = 40'h0; // @[core.scala:51:7]
wire [39:0] io_lsu_exe_0_req_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:51:7]
wire [39:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:51:7]
wire [39:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:51:7]
wire [39:0] io_trace_insns_0_iaddr = 40'h0; // @[core.scala:51:7]
wire [39:0] io_trace_insns_0_tval = 40'h0; // @[core.scala:51:7]
wire [39:0] io_trace_insns_1_iaddr = 40'h0; // @[core.scala:51:7]
wire [39:0] io_trace_insns_1_tval = 40'h0; // @[core.scala:51:7]
wire [39:0] io_trace_insns_2_iaddr = 40'h0; // @[core.scala:51:7]
wire [39:0] io_trace_insns_2_tval = 40'h0; // @[core.scala:51:7]
wire [39:0] int_iss_wakeups_1_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:147:30]
wire [39:0] int_iss_wakeups_2_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:147:30]
wire [39:0] int_iss_wakeups_3_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:147:30]
wire [39:0] int_iss_wakeups_4_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:147:30]
wire [39:0] int_iss_wakeups_5_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:147:30]
wire [39:0] int_iss_wakeups_6_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:147:30]
wire [39:0] int_ren_wakeups_1_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:148:30]
wire [39:0] int_ren_wakeups_2_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:148:30]
wire [39:0] int_ren_wakeups_3_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:148:30]
wire [39:0] int_ren_wakeups_4_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:148:30]
wire [39:0] int_ren_wakeups_5_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:148:30]
wire [39:0] int_ren_wakeups_6_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:148:30]
wire [39:0] pred_wakeup_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:149:26]
wire [39:0] bypasses_0_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:174:24]
wire [39:0] bypasses_1_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:174:24]
wire [39:0] bypasses_2_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:174:24]
wire [39:0] bypasses_3_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:174:24]
wire [39:0] bypasses_4_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:174:24]
wire [39:0] pred_bypasses_0_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:175:27]
wire [39:0] p_uop_debug_pc = 40'h0; // @[consts.scala:269:19]
wire [39:0] p_uop_1_debug_pc = 40'h0; // @[consts.scala:269:19]
wire [39:0] p_uop_2_debug_pc = 40'h0; // @[consts.scala:269:19]
wire [39:0] fast_wakeup_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:814:29]
wire [39:0] slow_wakeup_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:815:29]
wire [39:0] fast_wakeup_1_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:814:29]
wire [39:0] slow_wakeup_1_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:815:29]
wire [39:0] fast_wakeup_2_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:814:29]
wire [39:0] slow_wakeup_2_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:815:29]
wire [1:0] io_ifu_status_sxl = 2'h2; // @[core.scala:51:7]
wire [1:0] io_ifu_status_uxl = 2'h2; // @[core.scala:51:7]
wire [1:0] io_ptw_status_sxl = 2'h2; // @[core.scala:51:7]
wire [1:0] io_ptw_status_uxl = 2'h2; // @[core.scala:51:7]
wire [1:0] io_ptw_tlb_status_sxl = 2'h2; // @[core.scala:51:7]
wire [1:0] io_ptw_tlb_status_uxl = 2'h2; // @[core.scala:51:7]
wire [1:0] p_uop_dst_rtype = 2'h2; // @[consts.scala:269:19]
wire [1:0] p_uop_1_dst_rtype = 2'h2; // @[consts.scala:269:19]
wire [1:0] p_uop_2_dst_rtype = 2'h2; // @[consts.scala:269:19]
wire [43:0] io_ptw_hgatp_ppn = 44'h0; // @[core.scala:51:7]
wire [43:0] io_ptw_vsatp_ppn = 44'h0; // @[core.scala:51:7]
wire [43:0] io_ptw_tlb_hgatp_ppn = 44'h0; // @[core.scala:51:7]
wire [43:0] io_ptw_tlb_vsatp_ppn = 44'h0; // @[core.scala:51:7]
wire [29:0] io_ptw_hstatus_zero6 = 30'h0; // @[core.scala:51:7]
wire [29:0] io_ptw_tlb_hstatus_zero6 = 30'h0; // @[core.scala:51:7]
wire [8:0] io_ptw_hstatus_zero5 = 9'h0; // @[core.scala:51:7]
wire [8:0] io_ptw_tlb_hstatus_zero5 = 9'h0; // @[core.scala:51:7]
wire [31:0] io_ptw_gstatus_isa = 32'h0; // @[core.scala:51:7]
wire [31:0] io_rocc_cmd_bits_status_isa = 32'h0; // @[core.scala:51:7]
wire [31:0] io_rocc_mem_s2_paddr = 32'h0; // @[core.scala:51:7]
wire [31:0] io_lsu_exe_0_req_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:51:7]
wire [31:0] io_lsu_exe_0_req_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:51:7]
wire [31:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:51:7]
wire [31:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:51:7]
wire [31:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:51:7]
wire [31:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:51:7]
wire [31:0] io_ptw_tlb_gstatus_isa = 32'h0; // @[core.scala:51:7]
wire [31:0] io_trace_insns_0_insn = 32'h0; // @[core.scala:51:7]
wire [31:0] io_trace_insns_1_insn = 32'h0; // @[core.scala:51:7]
wire [31:0] io_trace_insns_2_insn = 32'h0; // @[core.scala:51:7]
wire [31:0] int_iss_wakeups_1_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:147:30]
wire [31:0] int_iss_wakeups_1_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:147:30]
wire [31:0] int_iss_wakeups_2_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:147:30]
wire [31:0] int_iss_wakeups_2_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:147:30]
wire [31:0] int_iss_wakeups_3_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:147:30]
wire [31:0] int_iss_wakeups_3_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:147:30]
wire [31:0] int_iss_wakeups_4_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:147:30]
wire [31:0] int_iss_wakeups_4_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:147:30]
wire [31:0] int_iss_wakeups_5_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:147:30]
wire [31:0] int_iss_wakeups_5_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:147:30]
wire [31:0] int_iss_wakeups_6_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:147:30]
wire [31:0] int_iss_wakeups_6_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:147:30]
wire [31:0] int_ren_wakeups_1_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:148:30]
wire [31:0] int_ren_wakeups_1_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:148:30]
wire [31:0] int_ren_wakeups_2_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:148:30]
wire [31:0] int_ren_wakeups_2_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:148:30]
wire [31:0] int_ren_wakeups_3_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:148:30]
wire [31:0] int_ren_wakeups_3_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:148:30]
wire [31:0] int_ren_wakeups_4_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:148:30]
wire [31:0] int_ren_wakeups_4_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:148:30]
wire [31:0] int_ren_wakeups_5_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:148:30]
wire [31:0] int_ren_wakeups_5_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:148:30]
wire [31:0] int_ren_wakeups_6_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:148:30]
wire [31:0] int_ren_wakeups_6_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:148:30]
wire [31:0] pred_wakeup_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:149:26]
wire [31:0] pred_wakeup_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:149:26]
wire [31:0] bypasses_0_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:174:24]
wire [31:0] bypasses_0_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:174:24]
wire [31:0] bypasses_1_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:174:24]
wire [31:0] bypasses_1_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:174:24]
wire [31:0] bypasses_2_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:174:24]
wire [31:0] bypasses_2_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:174:24]
wire [31:0] bypasses_3_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:174:24]
wire [31:0] bypasses_3_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:174:24]
wire [31:0] bypasses_4_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:174:24]
wire [31:0] bypasses_4_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:174:24]
wire [31:0] pred_bypasses_0_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:175:27]
wire [31:0] pred_bypasses_0_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:175:27]
wire [31:0] p_uop_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] p_uop_debug_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] p_uop_1_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] p_uop_1_debug_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] p_uop_2_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] p_uop_2_debug_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] fast_wakeup_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:814:29]
wire [31:0] fast_wakeup_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:814:29]
wire [31:0] slow_wakeup_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:815:29]
wire [31:0] slow_wakeup_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:815:29]
wire [31:0] fast_wakeup_1_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:814:29]
wire [31:0] fast_wakeup_1_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:814:29]
wire [31:0] slow_wakeup_1_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:815:29]
wire [31:0] slow_wakeup_1_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:815:29]
wire [31:0] fast_wakeup_2_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:814:29]
wire [31:0] fast_wakeup_2_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:814:29]
wire [31:0] slow_wakeup_2_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:815:29]
wire [31:0] slow_wakeup_2_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:815:29]
wire [31:0] coreMonitorBundle_timer = 32'h0; // @[core.scala:1405:31]
wire [31:0] coreMonitorBundle_inst = 32'h0; // @[core.scala:1405:31]
wire io_lsu_exe_0_iresp_ready = 1'h1; // @[core.scala:51:7]
wire io_lsu_exe_0_fresp_ready = 1'h1; // @[core.scala:51:7]
wire _use_this_mispredict_T = 1'h1; // @[core.scala:206:31]
wire use_this_mispredict = 1'h1; // @[core.scala:206:47]
wire new_ghist_current_saw_branch_not_taken = 1'h1; // @[core.scala:406:29]
wire flush_pc_req_ready = 1'h1; // @[core.scala:524:26]
wire _large_T_1 = 1'h1; // @[Counters.scala:51:36]
wire [26:0] io_ptw_tlb_req_bits_bits_addr = 27'h0; // @[core.scala:51:7]
wire [4:0] _pause_mem_T = 5'h1F; // @[core.scala:912:77]
wire [3:0] _cfi_idx_T_1 = 4'h8; // @[core.scala:442:45]
wire [7:0] _next_ghist_not_taken_branches_T_19 = 8'hFF; // @[frontend.scala:91:45]
wire dec_ready; // @[core.scala:161:24]
wire [4:0] new_ghist_ras_idx = io_ifu_get_pc_0_entry_ras_idx_0; // @[core.scala:51:7, :406:29]
wire _cfi_idx_T = io_ifu_get_pc_1_entry_start_bank_0; // @[core.scala:51:7, :442:32]
wire io_ptw_sfence_valid_0 = io_ifu_sfence_valid_0; // @[core.scala:51:7]
wire io_ptw_sfence_bits_rs1_0 = io_ifu_sfence_bits_rs1_0; // @[core.scala:51:7]
wire io_ptw_sfence_bits_rs2_0 = io_ifu_sfence_bits_rs2_0; // @[core.scala:51:7]
wire [38:0] io_ptw_sfence_bits_addr_0 = io_ifu_sfence_bits_addr_0; // @[core.scala:51:7]
wire io_ptw_sfence_bits_asid_0 = io_ifu_sfence_bits_asid_0; // @[core.scala:51:7]
wire [15:0] brupdate_b1_resolve_mask; // @[core.scala:188:23]
wire [15:0] brupdate_b1_mispredict_mask; // @[core.scala:188:23]
wire [6:0] brupdate_b2_uop_uopc; // @[core.scala:188:23]
wire [31:0] brupdate_b2_uop_inst; // @[core.scala:188:23]
wire [31:0] brupdate_b2_uop_debug_inst; // @[core.scala:188:23]
wire brupdate_b2_uop_is_rvc; // @[core.scala:188:23]
wire [39:0] brupdate_b2_uop_debug_pc; // @[core.scala:188:23]
wire [2:0] brupdate_b2_uop_iq_type; // @[core.scala:188:23]
wire [9:0] brupdate_b2_uop_fu_code; // @[core.scala:188:23]
wire [3:0] brupdate_b2_uop_ctrl_br_type; // @[core.scala:188:23]
wire [1:0] brupdate_b2_uop_ctrl_op1_sel; // @[core.scala:188:23]
wire [2:0] brupdate_b2_uop_ctrl_op2_sel; // @[core.scala:188:23]
wire [2:0] brupdate_b2_uop_ctrl_imm_sel; // @[core.scala:188:23]
wire [4:0] brupdate_b2_uop_ctrl_op_fcn; // @[core.scala:188:23]
wire brupdate_b2_uop_ctrl_fcn_dw; // @[core.scala:188:23]
wire [2:0] brupdate_b2_uop_ctrl_csr_cmd; // @[core.scala:188:23]
wire brupdate_b2_uop_ctrl_is_load; // @[core.scala:188:23]
wire brupdate_b2_uop_ctrl_is_sta; // @[core.scala:188:23]
wire brupdate_b2_uop_ctrl_is_std; // @[core.scala:188:23]
wire [1:0] brupdate_b2_uop_iw_state; // @[core.scala:188:23]
wire brupdate_b2_uop_iw_p1_poisoned; // @[core.scala:188:23]
wire brupdate_b2_uop_iw_p2_poisoned; // @[core.scala:188:23]
wire brupdate_b2_uop_is_br; // @[core.scala:188:23]
wire brupdate_b2_uop_is_jalr; // @[core.scala:188:23]
wire brupdate_b2_uop_is_jal; // @[core.scala:188:23]
wire brupdate_b2_uop_is_sfb; // @[core.scala:188:23]
wire [15:0] brupdate_b2_uop_br_mask; // @[core.scala:188:23]
wire [3:0] brupdate_b2_uop_br_tag; // @[core.scala:188:23]
wire [4:0] brupdate_b2_uop_ftq_idx; // @[core.scala:188:23]
wire brupdate_b2_uop_edge_inst; // @[core.scala:188:23]
wire [5:0] brupdate_b2_uop_pc_lob; // @[core.scala:188:23]
wire brupdate_b2_uop_taken; // @[core.scala:188:23]
wire [19:0] brupdate_b2_uop_imm_packed; // @[core.scala:188:23]
wire [11:0] brupdate_b2_uop_csr_addr; // @[core.scala:188:23]
wire [6:0] brupdate_b2_uop_rob_idx; // @[core.scala:188:23]
wire [4:0] brupdate_b2_uop_ldq_idx; // @[core.scala:188:23]
wire [4:0] brupdate_b2_uop_stq_idx; // @[core.scala:188:23]
wire [1:0] brupdate_b2_uop_rxq_idx; // @[core.scala:188:23]
wire [6:0] brupdate_b2_uop_pdst; // @[core.scala:188:23]
wire [6:0] brupdate_b2_uop_prs1; // @[core.scala:188:23]
wire [6:0] brupdate_b2_uop_prs2; // @[core.scala:188:23]
wire [6:0] brupdate_b2_uop_prs3; // @[core.scala:188:23]
wire [4:0] brupdate_b2_uop_ppred; // @[core.scala:188:23]
wire brupdate_b2_uop_prs1_busy; // @[core.scala:188:23]
wire brupdate_b2_uop_prs2_busy; // @[core.scala:188:23]
wire brupdate_b2_uop_prs3_busy; // @[core.scala:188:23]
wire brupdate_b2_uop_ppred_busy; // @[core.scala:188:23]
wire [6:0] brupdate_b2_uop_stale_pdst; // @[core.scala:188:23]
wire brupdate_b2_uop_exception; // @[core.scala:188:23]
wire [63:0] brupdate_b2_uop_exc_cause; // @[core.scala:188:23]
wire brupdate_b2_uop_bypassable; // @[core.scala:188:23]
wire [4:0] brupdate_b2_uop_mem_cmd; // @[core.scala:188:23]
wire [1:0] brupdate_b2_uop_mem_size; // @[core.scala:188:23]
wire brupdate_b2_uop_mem_signed; // @[core.scala:188:23]
wire brupdate_b2_uop_is_fence; // @[core.scala:188:23]
wire brupdate_b2_uop_is_fencei; // @[core.scala:188:23]
wire brupdate_b2_uop_is_amo; // @[core.scala:188:23]
wire brupdate_b2_uop_uses_ldq; // @[core.scala:188:23]
wire brupdate_b2_uop_uses_stq; // @[core.scala:188:23]
wire brupdate_b2_uop_is_sys_pc2epc; // @[core.scala:188:23]
wire brupdate_b2_uop_is_unique; // @[core.scala:188:23]
wire brupdate_b2_uop_flush_on_commit; // @[core.scala:188:23]
wire brupdate_b2_uop_ldst_is_rs1; // @[core.scala:188:23]
wire [5:0] brupdate_b2_uop_ldst; // @[core.scala:188:23]
wire [5:0] brupdate_b2_uop_lrs1; // @[core.scala:188:23]
wire [5:0] brupdate_b2_uop_lrs2; // @[core.scala:188:23]
wire [5:0] brupdate_b2_uop_lrs3; // @[core.scala:188:23]
wire brupdate_b2_uop_ldst_val; // @[core.scala:188:23]
wire [1:0] brupdate_b2_uop_dst_rtype; // @[core.scala:188:23]
wire [1:0] brupdate_b2_uop_lrs1_rtype; // @[core.scala:188:23]
wire [1:0] brupdate_b2_uop_lrs2_rtype; // @[core.scala:188:23]
wire brupdate_b2_uop_frs3_en; // @[core.scala:188:23]
wire brupdate_b2_uop_fp_val; // @[core.scala:188:23]
wire brupdate_b2_uop_fp_single; // @[core.scala:188:23]
wire brupdate_b2_uop_xcpt_pf_if; // @[core.scala:188:23]
wire brupdate_b2_uop_xcpt_ae_if; // @[core.scala:188:23]
wire brupdate_b2_uop_xcpt_ma_if; // @[core.scala:188:23]
wire brupdate_b2_uop_bp_debug_if; // @[core.scala:188:23]
wire brupdate_b2_uop_bp_xcpt_if; // @[core.scala:188:23]
wire [1:0] brupdate_b2_uop_debug_fsrc; // @[core.scala:188:23]
wire [1:0] brupdate_b2_uop_debug_tsrc; // @[core.scala:188:23]
wire brupdate_b2_mispredict; // @[core.scala:188:23]
wire brupdate_b2_taken; // @[core.scala:188:23]
wire [2:0] brupdate_b2_cfi_type; // @[core.scala:188:23]
wire [1:0] brupdate_b2_pc_sel; // @[core.scala:188:23]
wire [39:0] brupdate_b2_jalr_target; // @[core.scala:188:23]
wire [20:0] brupdate_b2_target_offset; // @[core.scala:188:23]
wire _io_ifu_flush_icache_T_13; // @[core.scala:390:13]
wire dis_fire_0; // @[core.scala:168:24]
wire [6:0] dis_uops_0_uopc; // @[core.scala:167:24]
wire [31:0] dis_uops_0_inst; // @[core.scala:167:24]
wire [31:0] dis_uops_0_debug_inst; // @[core.scala:167:24]
wire dis_uops_0_is_rvc; // @[core.scala:167:24]
wire [39:0] dis_uops_0_debug_pc; // @[core.scala:167:24]
wire [2:0] dis_uops_0_iq_type; // @[core.scala:167:24]
wire [9:0] dis_uops_0_fu_code; // @[core.scala:167:24]
wire [3:0] dis_uops_0_ctrl_br_type; // @[core.scala:167:24]
wire [1:0] dis_uops_0_ctrl_op1_sel; // @[core.scala:167:24]
wire [2:0] dis_uops_0_ctrl_op2_sel; // @[core.scala:167:24]
wire [2:0] dis_uops_0_ctrl_imm_sel; // @[core.scala:167:24]
wire [4:0] dis_uops_0_ctrl_op_fcn; // @[core.scala:167:24]
wire dis_uops_0_ctrl_fcn_dw; // @[core.scala:167:24]
wire [2:0] dis_uops_0_ctrl_csr_cmd; // @[core.scala:167:24]
wire dis_uops_0_ctrl_is_load; // @[core.scala:167:24]
wire dis_uops_0_ctrl_is_sta; // @[core.scala:167:24]
wire dis_uops_0_ctrl_is_std; // @[core.scala:167:24]
wire [1:0] dis_uops_0_iw_state; // @[core.scala:167:24]
wire dis_uops_0_iw_p1_poisoned; // @[core.scala:167:24]
wire dis_uops_0_iw_p2_poisoned; // @[core.scala:167:24]
wire dis_uops_0_is_br; // @[core.scala:167:24]
wire dis_uops_0_is_jalr; // @[core.scala:167:24]
wire dis_uops_0_is_jal; // @[core.scala:167:24]
wire dis_uops_0_is_sfb; // @[core.scala:167:24]
wire [15:0] dis_uops_0_br_mask; // @[core.scala:167:24]
wire [3:0] dis_uops_0_br_tag; // @[core.scala:167:24]
wire [4:0] dis_uops_0_ftq_idx; // @[core.scala:167:24]
wire dis_uops_0_edge_inst; // @[core.scala:167:24]
wire [5:0] dis_uops_0_pc_lob; // @[core.scala:167:24]
wire dis_uops_0_taken; // @[core.scala:167:24]
wire [19:0] dis_uops_0_imm_packed; // @[core.scala:167:24]
wire [11:0] dis_uops_0_csr_addr; // @[core.scala:167:24]
wire [6:0] dis_uops_0_rob_idx; // @[core.scala:167:24]
wire [4:0] dis_uops_0_ldq_idx; // @[core.scala:167:24]
wire [4:0] dis_uops_0_stq_idx; // @[core.scala:167:24]
wire [1:0] dis_uops_0_rxq_idx; // @[core.scala:167:24]
wire [6:0] dis_uops_0_pdst; // @[core.scala:167:24]
wire [6:0] dis_uops_0_prs1; // @[core.scala:167:24]
wire [6:0] dis_uops_0_prs2; // @[core.scala:167:24]
wire [6:0] dis_uops_0_prs3; // @[core.scala:167:24]
wire dis_uops_0_prs1_busy; // @[core.scala:167:24]
wire dis_uops_0_prs2_busy; // @[core.scala:167:24]
wire dis_uops_0_prs3_busy; // @[core.scala:167:24]
wire [6:0] dis_uops_0_stale_pdst; // @[core.scala:167:24]
wire dis_uops_0_exception; // @[core.scala:167:24]
wire [63:0] dis_uops_0_exc_cause; // @[core.scala:167:24]
wire dis_uops_0_bypassable; // @[core.scala:167:24]
wire [4:0] dis_uops_0_mem_cmd; // @[core.scala:167:24]
wire [1:0] dis_uops_0_mem_size; // @[core.scala:167:24]
wire dis_uops_0_mem_signed; // @[core.scala:167:24]
wire dis_uops_0_is_fence; // @[core.scala:167:24]
wire dis_uops_0_is_fencei; // @[core.scala:167:24]
wire dis_uops_0_is_amo; // @[core.scala:167:24]
wire dis_uops_0_uses_ldq; // @[core.scala:167:24]
wire dis_uops_0_uses_stq; // @[core.scala:167:24]
wire dis_uops_0_is_sys_pc2epc; // @[core.scala:167:24]
wire dis_uops_0_is_unique; // @[core.scala:167:24]
wire dis_uops_0_flush_on_commit; // @[core.scala:167:24]
wire dis_uops_0_ldst_is_rs1; // @[core.scala:167:24]
wire [5:0] dis_uops_0_ldst; // @[core.scala:167:24]
wire [5:0] dis_uops_0_lrs1; // @[core.scala:167:24]
wire [5:0] dis_uops_0_lrs2; // @[core.scala:167:24]
wire [5:0] dis_uops_0_lrs3; // @[core.scala:167:24]
wire dis_uops_0_ldst_val; // @[core.scala:167:24]
wire [1:0] dis_uops_0_dst_rtype; // @[core.scala:167:24]
wire [1:0] dis_uops_0_lrs1_rtype; // @[core.scala:167:24]
wire [1:0] dis_uops_0_lrs2_rtype; // @[core.scala:167:24]
wire dis_uops_0_frs3_en; // @[core.scala:167:24]
wire dis_uops_0_fp_val; // @[core.scala:167:24]
wire dis_uops_0_fp_single; // @[core.scala:167:24]
wire dis_uops_0_xcpt_pf_if; // @[core.scala:167:24]
wire dis_uops_0_xcpt_ae_if; // @[core.scala:167:24]
wire dis_uops_0_xcpt_ma_if; // @[core.scala:167:24]
wire dis_uops_0_bp_debug_if; // @[core.scala:167:24]
wire dis_uops_0_bp_xcpt_if; // @[core.scala:167:24]
wire [1:0] dis_uops_0_debug_fsrc; // @[core.scala:167:24]
wire [1:0] dis_uops_0_debug_tsrc; // @[core.scala:167:24]
wire dis_fire_1; // @[core.scala:168:24]
wire [6:0] dis_uops_1_uopc; // @[core.scala:167:24]
wire [31:0] dis_uops_1_inst; // @[core.scala:167:24]
wire [31:0] dis_uops_1_debug_inst; // @[core.scala:167:24]
wire dis_uops_1_is_rvc; // @[core.scala:167:24]
wire [39:0] dis_uops_1_debug_pc; // @[core.scala:167:24]
wire [2:0] dis_uops_1_iq_type; // @[core.scala:167:24]
wire [9:0] dis_uops_1_fu_code; // @[core.scala:167:24]
wire [3:0] dis_uops_1_ctrl_br_type; // @[core.scala:167:24]
wire [1:0] dis_uops_1_ctrl_op1_sel; // @[core.scala:167:24]
wire [2:0] dis_uops_1_ctrl_op2_sel; // @[core.scala:167:24]
wire [2:0] dis_uops_1_ctrl_imm_sel; // @[core.scala:167:24]
wire [4:0] dis_uops_1_ctrl_op_fcn; // @[core.scala:167:24]
wire dis_uops_1_ctrl_fcn_dw; // @[core.scala:167:24]
wire [2:0] dis_uops_1_ctrl_csr_cmd; // @[core.scala:167:24]
wire dis_uops_1_ctrl_is_load; // @[core.scala:167:24]
wire dis_uops_1_ctrl_is_sta; // @[core.scala:167:24]
wire dis_uops_1_ctrl_is_std; // @[core.scala:167:24]
wire [1:0] dis_uops_1_iw_state; // @[core.scala:167:24]
wire dis_uops_1_iw_p1_poisoned; // @[core.scala:167:24]
wire dis_uops_1_iw_p2_poisoned; // @[core.scala:167:24]
wire dis_uops_1_is_br; // @[core.scala:167:24]
wire dis_uops_1_is_jalr; // @[core.scala:167:24]
wire dis_uops_1_is_jal; // @[core.scala:167:24]
wire dis_uops_1_is_sfb; // @[core.scala:167:24]
wire [15:0] dis_uops_1_br_mask; // @[core.scala:167:24]
wire [3:0] dis_uops_1_br_tag; // @[core.scala:167:24]
wire [4:0] dis_uops_1_ftq_idx; // @[core.scala:167:24]
wire dis_uops_1_edge_inst; // @[core.scala:167:24]
wire [5:0] dis_uops_1_pc_lob; // @[core.scala:167:24]
wire dis_uops_1_taken; // @[core.scala:167:24]
wire [19:0] dis_uops_1_imm_packed; // @[core.scala:167:24]
wire [11:0] dis_uops_1_csr_addr; // @[core.scala:167:24]
wire [6:0] dis_uops_1_rob_idx; // @[core.scala:167:24]
wire [4:0] dis_uops_1_ldq_idx; // @[core.scala:167:24]
wire [4:0] dis_uops_1_stq_idx; // @[core.scala:167:24]
wire [1:0] dis_uops_1_rxq_idx; // @[core.scala:167:24]
wire [6:0] dis_uops_1_pdst; // @[core.scala:167:24]
wire [6:0] dis_uops_1_prs1; // @[core.scala:167:24]
wire [6:0] dis_uops_1_prs2; // @[core.scala:167:24]
wire [6:0] dis_uops_1_prs3; // @[core.scala:167:24]
wire dis_uops_1_prs1_busy; // @[core.scala:167:24]
wire dis_uops_1_prs2_busy; // @[core.scala:167:24]
wire dis_uops_1_prs3_busy; // @[core.scala:167:24]
wire [6:0] dis_uops_1_stale_pdst; // @[core.scala:167:24]
wire dis_uops_1_exception; // @[core.scala:167:24]
wire [63:0] dis_uops_1_exc_cause; // @[core.scala:167:24]
wire dis_uops_1_bypassable; // @[core.scala:167:24]
wire [4:0] dis_uops_1_mem_cmd; // @[core.scala:167:24]
wire [1:0] dis_uops_1_mem_size; // @[core.scala:167:24]
wire dis_uops_1_mem_signed; // @[core.scala:167:24]
wire dis_uops_1_is_fence; // @[core.scala:167:24]
wire dis_uops_1_is_fencei; // @[core.scala:167:24]
wire dis_uops_1_is_amo; // @[core.scala:167:24]
wire dis_uops_1_uses_ldq; // @[core.scala:167:24]
wire dis_uops_1_uses_stq; // @[core.scala:167:24]
wire dis_uops_1_is_sys_pc2epc; // @[core.scala:167:24]
wire dis_uops_1_is_unique; // @[core.scala:167:24]
wire dis_uops_1_flush_on_commit; // @[core.scala:167:24]
wire dis_uops_1_ldst_is_rs1; // @[core.scala:167:24]
wire [5:0] dis_uops_1_ldst; // @[core.scala:167:24]
wire [5:0] dis_uops_1_lrs1; // @[core.scala:167:24]
wire [5:0] dis_uops_1_lrs2; // @[core.scala:167:24]
wire [5:0] dis_uops_1_lrs3; // @[core.scala:167:24]
wire dis_uops_1_ldst_val; // @[core.scala:167:24]
wire [1:0] dis_uops_1_dst_rtype; // @[core.scala:167:24]
wire [1:0] dis_uops_1_lrs1_rtype; // @[core.scala:167:24]
wire [1:0] dis_uops_1_lrs2_rtype; // @[core.scala:167:24]
wire dis_uops_1_frs3_en; // @[core.scala:167:24]
wire dis_uops_1_fp_val; // @[core.scala:167:24]
wire dis_uops_1_fp_single; // @[core.scala:167:24]
wire dis_uops_1_xcpt_pf_if; // @[core.scala:167:24]
wire dis_uops_1_xcpt_ae_if; // @[core.scala:167:24]
wire dis_uops_1_xcpt_ma_if; // @[core.scala:167:24]
wire dis_uops_1_bp_debug_if; // @[core.scala:167:24]
wire dis_uops_1_bp_xcpt_if; // @[core.scala:167:24]
wire [1:0] dis_uops_1_debug_fsrc; // @[core.scala:167:24]
wire [1:0] dis_uops_1_debug_tsrc; // @[core.scala:167:24]
wire dis_fire_2; // @[core.scala:168:24]
wire [6:0] dis_uops_2_uopc; // @[core.scala:167:24]
wire [31:0] dis_uops_2_inst; // @[core.scala:167:24]
wire [31:0] dis_uops_2_debug_inst; // @[core.scala:167:24]
wire dis_uops_2_is_rvc; // @[core.scala:167:24]
wire [39:0] dis_uops_2_debug_pc; // @[core.scala:167:24]
wire [2:0] dis_uops_2_iq_type; // @[core.scala:167:24]
wire [9:0] dis_uops_2_fu_code; // @[core.scala:167:24]
wire [3:0] dis_uops_2_ctrl_br_type; // @[core.scala:167:24]
wire [1:0] dis_uops_2_ctrl_op1_sel; // @[core.scala:167:24]
wire [2:0] dis_uops_2_ctrl_op2_sel; // @[core.scala:167:24]
wire [2:0] dis_uops_2_ctrl_imm_sel; // @[core.scala:167:24]
wire [4:0] dis_uops_2_ctrl_op_fcn; // @[core.scala:167:24]
wire dis_uops_2_ctrl_fcn_dw; // @[core.scala:167:24]
wire [2:0] dis_uops_2_ctrl_csr_cmd; // @[core.scala:167:24]
wire dis_uops_2_ctrl_is_load; // @[core.scala:167:24]
wire dis_uops_2_ctrl_is_sta; // @[core.scala:167:24]
wire dis_uops_2_ctrl_is_std; // @[core.scala:167:24]
wire [1:0] dis_uops_2_iw_state; // @[core.scala:167:24]
wire dis_uops_2_iw_p1_poisoned; // @[core.scala:167:24]
wire dis_uops_2_iw_p2_poisoned; // @[core.scala:167:24]
wire dis_uops_2_is_br; // @[core.scala:167:24]
wire dis_uops_2_is_jalr; // @[core.scala:167:24]
wire dis_uops_2_is_jal; // @[core.scala:167:24]
wire dis_uops_2_is_sfb; // @[core.scala:167:24]
wire [15:0] dis_uops_2_br_mask; // @[core.scala:167:24]
wire [3:0] dis_uops_2_br_tag; // @[core.scala:167:24]
wire [4:0] dis_uops_2_ftq_idx; // @[core.scala:167:24]
wire dis_uops_2_edge_inst; // @[core.scala:167:24]
wire [5:0] dis_uops_2_pc_lob; // @[core.scala:167:24]
wire dis_uops_2_taken; // @[core.scala:167:24]
wire [19:0] dis_uops_2_imm_packed; // @[core.scala:167:24]
wire [11:0] dis_uops_2_csr_addr; // @[core.scala:167:24]
wire [6:0] dis_uops_2_rob_idx; // @[core.scala:167:24]
wire [4:0] dis_uops_2_ldq_idx; // @[core.scala:167:24]
wire [4:0] dis_uops_2_stq_idx; // @[core.scala:167:24]
wire [1:0] dis_uops_2_rxq_idx; // @[core.scala:167:24]
wire [6:0] dis_uops_2_pdst; // @[core.scala:167:24]
wire [6:0] dis_uops_2_prs1; // @[core.scala:167:24]
wire [6:0] dis_uops_2_prs2; // @[core.scala:167:24]
wire [6:0] dis_uops_2_prs3; // @[core.scala:167:24]
wire dis_uops_2_prs1_busy; // @[core.scala:167:24]
wire dis_uops_2_prs2_busy; // @[core.scala:167:24]
wire dis_uops_2_prs3_busy; // @[core.scala:167:24]
wire [6:0] dis_uops_2_stale_pdst; // @[core.scala:167:24]
wire dis_uops_2_exception; // @[core.scala:167:24]
wire [63:0] dis_uops_2_exc_cause; // @[core.scala:167:24]
wire dis_uops_2_bypassable; // @[core.scala:167:24]
wire [4:0] dis_uops_2_mem_cmd; // @[core.scala:167:24]
wire [1:0] dis_uops_2_mem_size; // @[core.scala:167:24]
wire dis_uops_2_mem_signed; // @[core.scala:167:24]
wire dis_uops_2_is_fence; // @[core.scala:167:24]
wire dis_uops_2_is_fencei; // @[core.scala:167:24]
wire dis_uops_2_is_amo; // @[core.scala:167:24]
wire dis_uops_2_uses_ldq; // @[core.scala:167:24]
wire dis_uops_2_uses_stq; // @[core.scala:167:24]
wire dis_uops_2_is_sys_pc2epc; // @[core.scala:167:24]
wire dis_uops_2_is_unique; // @[core.scala:167:24]
wire dis_uops_2_flush_on_commit; // @[core.scala:167:24]
wire dis_uops_2_ldst_is_rs1; // @[core.scala:167:24]
wire [5:0] dis_uops_2_ldst; // @[core.scala:167:24]
wire [5:0] dis_uops_2_lrs1; // @[core.scala:167:24]
wire [5:0] dis_uops_2_lrs2; // @[core.scala:167:24]
wire [5:0] dis_uops_2_lrs3; // @[core.scala:167:24]
wire dis_uops_2_ldst_val; // @[core.scala:167:24]
wire [1:0] dis_uops_2_dst_rtype; // @[core.scala:167:24]
wire [1:0] dis_uops_2_lrs1_rtype; // @[core.scala:167:24]
wire [1:0] dis_uops_2_lrs2_rtype; // @[core.scala:167:24]
wire dis_uops_2_frs3_en; // @[core.scala:167:24]
wire dis_uops_2_fp_val; // @[core.scala:167:24]
wire dis_uops_2_fp_single; // @[core.scala:167:24]
wire dis_uops_2_xcpt_pf_if; // @[core.scala:167:24]
wire dis_uops_2_xcpt_ae_if; // @[core.scala:167:24]
wire dis_uops_2_xcpt_ma_if; // @[core.scala:167:24]
wire dis_uops_2_bp_debug_if; // @[core.scala:167:24]
wire dis_uops_2_bp_xcpt_if; // @[core.scala:167:24]
wire [1:0] dis_uops_2_debug_fsrc; // @[core.scala:167:24]
wire [1:0] dis_uops_2_debug_tsrc; // @[core.scala:167:24]
assign dis_uops_0_ldq_idx = io_lsu_dis_ldq_idx_0_0; // @[core.scala:51:7, :167:24]
assign dis_uops_1_ldq_idx = io_lsu_dis_ldq_idx_1_0; // @[core.scala:51:7, :167:24]
assign dis_uops_2_ldq_idx = io_lsu_dis_ldq_idx_2_0; // @[core.scala:51:7, :167:24]
assign dis_uops_0_stq_idx = io_lsu_dis_stq_idx_0_0; // @[core.scala:51:7, :167:24]
assign dis_uops_1_stq_idx = io_lsu_dis_stq_idx_1_0; // @[core.scala:51:7, :167:24]
assign dis_uops_2_stq_idx = io_lsu_dis_stq_idx_2_0; // @[core.scala:51:7, :167:24]
wire _io_lsu_fence_dmem_T_4; // @[core.scala:711:101]
wire io_ifu_fetchpacket_ready_0; // @[core.scala:51:7]
wire [4:0] io_ifu_get_pc_0_ftq_idx_0; // @[core.scala:51:7]
wire [4:0] io_ifu_get_pc_1_ftq_idx_0; // @[core.scala:51:7]
wire io_ifu_status_debug_0; // @[core.scala:51:7]
wire io_ifu_status_cease_0; // @[core.scala:51:7]
wire io_ifu_status_wfi_0; // @[core.scala:51:7]
wire [1:0] io_ifu_status_dprv_0; // @[core.scala:51:7]
wire io_ifu_status_dv_0; // @[core.scala:51:7]
wire [1:0] io_ifu_status_prv_0; // @[core.scala:51:7]
wire io_ifu_status_v_0; // @[core.scala:51:7]
wire io_ifu_status_sd_0; // @[core.scala:51:7]
wire io_ifu_status_mpv_0; // @[core.scala:51:7]
wire io_ifu_status_gva_0; // @[core.scala:51:7]
wire io_ifu_status_tsr_0; // @[core.scala:51:7]
wire io_ifu_status_tw_0; // @[core.scala:51:7]
wire io_ifu_status_tvm_0; // @[core.scala:51:7]
wire io_ifu_status_mxr_0; // @[core.scala:51:7]
wire io_ifu_status_sum_0; // @[core.scala:51:7]
wire io_ifu_status_mprv_0; // @[core.scala:51:7]
wire [1:0] io_ifu_status_fs_0; // @[core.scala:51:7]
wire [1:0] io_ifu_status_mpp_0; // @[core.scala:51:7]
wire io_ifu_status_spp_0; // @[core.scala:51:7]
wire io_ifu_status_mpie_0; // @[core.scala:51:7]
wire io_ifu_status_spie_0; // @[core.scala:51:7]
wire io_ifu_status_mie_0; // @[core.scala:51:7]
wire io_ifu_status_sie_0; // @[core.scala:51:7]
wire [15:0] io_ifu_brupdate_b1_resolve_mask_0; // @[core.scala:51:7]
wire [15:0] io_ifu_brupdate_b1_mispredict_mask_0; // @[core.scala:51:7]
wire [3:0] io_ifu_brupdate_b2_uop_ctrl_br_type_0; // @[core.scala:51:7]
wire [1:0] io_ifu_brupdate_b2_uop_ctrl_op1_sel_0; // @[core.scala:51:7]
wire [2:0] io_ifu_brupdate_b2_uop_ctrl_op2_sel_0; // @[core.scala:51:7]
wire [2:0] io_ifu_brupdate_b2_uop_ctrl_imm_sel_0; // @[core.scala:51:7]
wire [4:0] io_ifu_brupdate_b2_uop_ctrl_op_fcn_0; // @[core.scala:51:7]
wire io_ifu_brupdate_b2_uop_ctrl_fcn_dw_0; // @[core.scala:51:7]
wire [2:0] io_ifu_brupdate_b2_uop_ctrl_csr_cmd_0; // @[core.scala:51:7]
wire io_ifu_brupdate_b2_uop_ctrl_is_load_0; // @[core.scala:51:7]
wire io_ifu_brupdate_b2_uop_ctrl_is_sta_0; // @[core.scala:51:7]
wire io_ifu_brupdate_b2_uop_ctrl_is_std_0; // @[core.scala:51:7]
wire [6:0] io_ifu_brupdate_b2_uop_uopc_0; // @[core.scala:51:7]
wire [31:0] io_ifu_brupdate_b2_uop_inst_0; // @[core.scala:51:7]
wire [31:0] io_ifu_brupdate_b2_uop_debug_inst_0; // @[core.scala:51:7]
wire io_ifu_brupdate_b2_uop_is_rvc_0; // @[core.scala:51:7]
wire [39:0] io_ifu_brupdate_b2_uop_debug_pc_0; // @[core.scala:51:7]
wire [2:0] io_ifu_brupdate_b2_uop_iq_type_0; // @[core.scala:51:7]
wire [9:0] io_ifu_brupdate_b2_uop_fu_code_0; // @[core.scala:51:7]
wire [1:0] io_ifu_brupdate_b2_uop_iw_state_0; // @[core.scala:51:7]
wire io_ifu_brupdate_b2_uop_iw_p1_poisoned_0; // @[core.scala:51:7]
wire io_ifu_brupdate_b2_uop_iw_p2_poisoned_0; // @[core.scala:51:7]
wire io_ifu_brupdate_b2_uop_is_br_0; // @[core.scala:51:7]
wire io_ifu_brupdate_b2_uop_is_jalr_0; // @[core.scala:51:7]
wire io_ifu_brupdate_b2_uop_is_jal_0; // @[core.scala:51:7]
wire io_ifu_brupdate_b2_uop_is_sfb_0; // @[core.scala:51:7]
wire [15:0] io_ifu_brupdate_b2_uop_br_mask_0; // @[core.scala:51:7]
wire [3:0] io_ifu_brupdate_b2_uop_br_tag_0; // @[core.scala:51:7]
wire [4:0] io_ifu_brupdate_b2_uop_ftq_idx_0; // @[core.scala:51:7]
wire io_ifu_brupdate_b2_uop_edge_inst_0; // @[core.scala:51:7]
wire [5:0] io_ifu_brupdate_b2_uop_pc_lob_0; // @[core.scala:51:7]
wire io_ifu_brupdate_b2_uop_taken_0; // @[core.scala:51:7]
wire [19:0] io_ifu_brupdate_b2_uop_imm_packed_0; // @[core.scala:51:7]
wire [11:0] io_ifu_brupdate_b2_uop_csr_addr_0; // @[core.scala:51:7]
wire [6:0] io_ifu_brupdate_b2_uop_rob_idx_0; // @[core.scala:51:7]
wire [4:0] io_ifu_brupdate_b2_uop_ldq_idx_0; // @[core.scala:51:7]
wire [4:0] io_ifu_brupdate_b2_uop_stq_idx_0; // @[core.scala:51:7]
wire [1:0] io_ifu_brupdate_b2_uop_rxq_idx_0; // @[core.scala:51:7]
wire [6:0] io_ifu_brupdate_b2_uop_pdst_0; // @[core.scala:51:7]
wire [6:0] io_ifu_brupdate_b2_uop_prs1_0; // @[core.scala:51:7]
wire [6:0] io_ifu_brupdate_b2_uop_prs2_0; // @[core.scala:51:7]
wire [6:0] io_ifu_brupdate_b2_uop_prs3_0; // @[core.scala:51:7]
wire [4:0] io_ifu_brupdate_b2_uop_ppred_0; // @[core.scala:51:7]
wire io_ifu_brupdate_b2_uop_prs1_busy_0; // @[core.scala:51:7]
wire io_ifu_brupdate_b2_uop_prs2_busy_0; // @[core.scala:51:7]
wire io_ifu_brupdate_b2_uop_prs3_busy_0; // @[core.scala:51:7]
wire io_ifu_brupdate_b2_uop_ppred_busy_0; // @[core.scala:51:7]
wire [6:0] io_ifu_brupdate_b2_uop_stale_pdst_0; // @[core.scala:51:7]
wire io_ifu_brupdate_b2_uop_exception_0; // @[core.scala:51:7]
wire [63:0] io_ifu_brupdate_b2_uop_exc_cause_0; // @[core.scala:51:7]
wire io_ifu_brupdate_b2_uop_bypassable_0; // @[core.scala:51:7]
wire [4:0] io_ifu_brupdate_b2_uop_mem_cmd_0; // @[core.scala:51:7]
wire [1:0] io_ifu_brupdate_b2_uop_mem_size_0; // @[core.scala:51:7]
wire io_ifu_brupdate_b2_uop_mem_signed_0; // @[core.scala:51:7]
wire io_ifu_brupdate_b2_uop_is_fence_0; // @[core.scala:51:7]
wire io_ifu_brupdate_b2_uop_is_fencei_0; // @[core.scala:51:7]
wire io_ifu_brupdate_b2_uop_is_amo_0; // @[core.scala:51:7]
wire io_ifu_brupdate_b2_uop_uses_ldq_0; // @[core.scala:51:7]
wire io_ifu_brupdate_b2_uop_uses_stq_0; // @[core.scala:51:7]
wire io_ifu_brupdate_b2_uop_is_sys_pc2epc_0; // @[core.scala:51:7]
wire io_ifu_brupdate_b2_uop_is_unique_0; // @[core.scala:51:7]
wire io_ifu_brupdate_b2_uop_flush_on_commit_0; // @[core.scala:51:7]
wire io_ifu_brupdate_b2_uop_ldst_is_rs1_0; // @[core.scala:51:7]
wire [5:0] io_ifu_brupdate_b2_uop_ldst_0; // @[core.scala:51:7]
wire [5:0] io_ifu_brupdate_b2_uop_lrs1_0; // @[core.scala:51:7]
wire [5:0] io_ifu_brupdate_b2_uop_lrs2_0; // @[core.scala:51:7]
wire [5:0] io_ifu_brupdate_b2_uop_lrs3_0; // @[core.scala:51:7]
wire io_ifu_brupdate_b2_uop_ldst_val_0; // @[core.scala:51:7]
wire [1:0] io_ifu_brupdate_b2_uop_dst_rtype_0; // @[core.scala:51:7]
wire [1:0] io_ifu_brupdate_b2_uop_lrs1_rtype_0; // @[core.scala:51:7]
wire [1:0] io_ifu_brupdate_b2_uop_lrs2_rtype_0; // @[core.scala:51:7]
wire io_ifu_brupdate_b2_uop_frs3_en_0; // @[core.scala:51:7]
wire io_ifu_brupdate_b2_uop_fp_val_0; // @[core.scala:51:7]
wire io_ifu_brupdate_b2_uop_fp_single_0; // @[core.scala:51:7]
wire io_ifu_brupdate_b2_uop_xcpt_pf_if_0; // @[core.scala:51:7]
wire io_ifu_brupdate_b2_uop_xcpt_ae_if_0; // @[core.scala:51:7]
wire io_ifu_brupdate_b2_uop_xcpt_ma_if_0; // @[core.scala:51:7]
wire io_ifu_brupdate_b2_uop_bp_debug_if_0; // @[core.scala:51:7]
wire io_ifu_brupdate_b2_uop_bp_xcpt_if_0; // @[core.scala:51:7]
wire [1:0] io_ifu_brupdate_b2_uop_debug_fsrc_0; // @[core.scala:51:7]
wire [1:0] io_ifu_brupdate_b2_uop_debug_tsrc_0; // @[core.scala:51:7]
wire io_ifu_brupdate_b2_valid_0; // @[core.scala:51:7]
wire io_ifu_brupdate_b2_mispredict_0; // @[core.scala:51:7]
wire io_ifu_brupdate_b2_taken_0; // @[core.scala:51:7]
wire [2:0] io_ifu_brupdate_b2_cfi_type_0; // @[core.scala:51:7]
wire [1:0] io_ifu_brupdate_b2_pc_sel_0; // @[core.scala:51:7]
wire [39:0] io_ifu_brupdate_b2_jalr_target_0; // @[core.scala:51:7]
wire [20:0] io_ifu_brupdate_b2_target_offset_0; // @[core.scala:51:7]
wire [63:0] io_ifu_redirect_ghist_old_history_0; // @[core.scala:51:7]
wire io_ifu_redirect_ghist_current_saw_branch_not_taken_0; // @[core.scala:51:7]
wire io_ifu_redirect_ghist_new_saw_branch_not_taken_0; // @[core.scala:51:7]
wire io_ifu_redirect_ghist_new_saw_branch_taken_0; // @[core.scala:51:7]
wire [4:0] io_ifu_redirect_ghist_ras_idx_0; // @[core.scala:51:7]
wire io_ifu_commit_valid_0; // @[core.scala:51:7]
wire [31:0] io_ifu_commit_bits_0; // @[core.scala:51:7]
wire io_ifu_redirect_flush_0; // @[core.scala:51:7]
wire io_ifu_redirect_val_0; // @[core.scala:51:7]
wire [39:0] io_ifu_redirect_pc_0; // @[core.scala:51:7]
wire [4:0] io_ifu_redirect_ftq_idx_0; // @[core.scala:51:7]
wire io_ifu_flush_icache_0; // @[core.scala:51:7]
wire [3:0] io_ptw_ptbr_mode_0; // @[core.scala:51:7]
wire [43:0] io_ptw_ptbr_ppn_0; // @[core.scala:51:7]
wire io_ptw_status_debug_0; // @[core.scala:51:7]
wire io_ptw_status_cease_0; // @[core.scala:51:7]
wire io_ptw_status_wfi_0; // @[core.scala:51:7]
wire [1:0] io_ptw_status_dprv_0; // @[core.scala:51:7]
wire io_ptw_status_dv_0; // @[core.scala:51:7]
wire [1:0] io_ptw_status_prv_0; // @[core.scala:51:7]
wire io_ptw_status_v_0; // @[core.scala:51:7]
wire io_ptw_status_sd_0; // @[core.scala:51:7]
wire io_ptw_status_mpv_0; // @[core.scala:51:7]
wire io_ptw_status_gva_0; // @[core.scala:51:7]
wire io_ptw_status_tsr_0; // @[core.scala:51:7]
wire io_ptw_status_tw_0; // @[core.scala:51:7]
wire io_ptw_status_tvm_0; // @[core.scala:51:7]
wire io_ptw_status_mxr_0; // @[core.scala:51:7]
wire io_ptw_status_sum_0; // @[core.scala:51:7]
wire io_ptw_status_mprv_0; // @[core.scala:51:7]
wire [1:0] io_ptw_status_fs_0; // @[core.scala:51:7]
wire [1:0] io_ptw_status_mpp_0; // @[core.scala:51:7]
wire io_ptw_status_spp_0; // @[core.scala:51:7]
wire io_ptw_status_mpie_0; // @[core.scala:51:7]
wire io_ptw_status_spie_0; // @[core.scala:51:7]
wire io_ptw_status_mie_0; // @[core.scala:51:7]
wire io_ptw_status_sie_0; // @[core.scala:51:7]
wire io_ptw_pmp_0_cfg_l_0; // @[core.scala:51:7]
wire [1:0] io_ptw_pmp_0_cfg_a_0; // @[core.scala:51:7]
wire io_ptw_pmp_0_cfg_x_0; // @[core.scala:51:7]
wire io_ptw_pmp_0_cfg_w_0; // @[core.scala:51:7]
wire io_ptw_pmp_0_cfg_r_0; // @[core.scala:51:7]
wire [29:0] io_ptw_pmp_0_addr_0; // @[core.scala:51:7]
wire [31:0] io_ptw_pmp_0_mask_0; // @[core.scala:51:7]
wire io_ptw_pmp_1_cfg_l_0; // @[core.scala:51:7]
wire [1:0] io_ptw_pmp_1_cfg_a_0; // @[core.scala:51:7]
wire io_ptw_pmp_1_cfg_x_0; // @[core.scala:51:7]
wire io_ptw_pmp_1_cfg_w_0; // @[core.scala:51:7]
wire io_ptw_pmp_1_cfg_r_0; // @[core.scala:51:7]
wire [29:0] io_ptw_pmp_1_addr_0; // @[core.scala:51:7]
wire [31:0] io_ptw_pmp_1_mask_0; // @[core.scala:51:7]
wire io_ptw_pmp_2_cfg_l_0; // @[core.scala:51:7]
wire [1:0] io_ptw_pmp_2_cfg_a_0; // @[core.scala:51:7]
wire io_ptw_pmp_2_cfg_x_0; // @[core.scala:51:7]
wire io_ptw_pmp_2_cfg_w_0; // @[core.scala:51:7]
wire io_ptw_pmp_2_cfg_r_0; // @[core.scala:51:7]
wire [29:0] io_ptw_pmp_2_addr_0; // @[core.scala:51:7]
wire [31:0] io_ptw_pmp_2_mask_0; // @[core.scala:51:7]
wire io_ptw_pmp_3_cfg_l_0; // @[core.scala:51:7]
wire [1:0] io_ptw_pmp_3_cfg_a_0; // @[core.scala:51:7]
wire io_ptw_pmp_3_cfg_x_0; // @[core.scala:51:7]
wire io_ptw_pmp_3_cfg_w_0; // @[core.scala:51:7]
wire io_ptw_pmp_3_cfg_r_0; // @[core.scala:51:7]
wire [29:0] io_ptw_pmp_3_addr_0; // @[core.scala:51:7]
wire [31:0] io_ptw_pmp_3_mask_0; // @[core.scala:51:7]
wire io_ptw_pmp_4_cfg_l_0; // @[core.scala:51:7]
wire [1:0] io_ptw_pmp_4_cfg_a_0; // @[core.scala:51:7]
wire io_ptw_pmp_4_cfg_x_0; // @[core.scala:51:7]
wire io_ptw_pmp_4_cfg_w_0; // @[core.scala:51:7]
wire io_ptw_pmp_4_cfg_r_0; // @[core.scala:51:7]
wire [29:0] io_ptw_pmp_4_addr_0; // @[core.scala:51:7]
wire [31:0] io_ptw_pmp_4_mask_0; // @[core.scala:51:7]
wire io_ptw_pmp_5_cfg_l_0; // @[core.scala:51:7]
wire [1:0] io_ptw_pmp_5_cfg_a_0; // @[core.scala:51:7]
wire io_ptw_pmp_5_cfg_x_0; // @[core.scala:51:7]
wire io_ptw_pmp_5_cfg_w_0; // @[core.scala:51:7]
wire io_ptw_pmp_5_cfg_r_0; // @[core.scala:51:7]
wire [29:0] io_ptw_pmp_5_addr_0; // @[core.scala:51:7]
wire [31:0] io_ptw_pmp_5_mask_0; // @[core.scala:51:7]
wire io_ptw_pmp_6_cfg_l_0; // @[core.scala:51:7]
wire [1:0] io_ptw_pmp_6_cfg_a_0; // @[core.scala:51:7]
wire io_ptw_pmp_6_cfg_x_0; // @[core.scala:51:7]
wire io_ptw_pmp_6_cfg_w_0; // @[core.scala:51:7]
wire io_ptw_pmp_6_cfg_r_0; // @[core.scala:51:7]
wire [29:0] io_ptw_pmp_6_addr_0; // @[core.scala:51:7]
wire [31:0] io_ptw_pmp_6_mask_0; // @[core.scala:51:7]
wire io_ptw_pmp_7_cfg_l_0; // @[core.scala:51:7]
wire [1:0] io_ptw_pmp_7_cfg_a_0; // @[core.scala:51:7]
wire io_ptw_pmp_7_cfg_x_0; // @[core.scala:51:7]
wire io_ptw_pmp_7_cfg_w_0; // @[core.scala:51:7]
wire io_ptw_pmp_7_cfg_r_0; // @[core.scala:51:7]
wire [29:0] io_ptw_pmp_7_addr_0; // @[core.scala:51:7]
wire [31:0] io_ptw_pmp_7_mask_0; // @[core.scala:51:7]
wire [3:0] io_lsu_exe_0_req_bits_uop_ctrl_br_type_0; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_req_bits_uop_ctrl_op1_sel_0; // @[core.scala:51:7]
wire [2:0] io_lsu_exe_0_req_bits_uop_ctrl_op2_sel_0; // @[core.scala:51:7]
wire [2:0] io_lsu_exe_0_req_bits_uop_ctrl_imm_sel_0; // @[core.scala:51:7]
wire [4:0] io_lsu_exe_0_req_bits_uop_ctrl_op_fcn_0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_uop_ctrl_fcn_dw_0; // @[core.scala:51:7]
wire [2:0] io_lsu_exe_0_req_bits_uop_ctrl_csr_cmd_0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_uop_ctrl_is_load_0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_uop_ctrl_is_sta_0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_uop_ctrl_is_std_0; // @[core.scala:51:7]
wire [6:0] io_lsu_exe_0_req_bits_uop_uopc_0; // @[core.scala:51:7]
wire [31:0] io_lsu_exe_0_req_bits_uop_inst_0; // @[core.scala:51:7]
wire [31:0] io_lsu_exe_0_req_bits_uop_debug_inst_0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_uop_is_rvc_0; // @[core.scala:51:7]
wire [39:0] io_lsu_exe_0_req_bits_uop_debug_pc_0; // @[core.scala:51:7]
wire [2:0] io_lsu_exe_0_req_bits_uop_iq_type_0; // @[core.scala:51:7]
wire [9:0] io_lsu_exe_0_req_bits_uop_fu_code_0; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_req_bits_uop_iw_state_0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_uop_iw_p1_poisoned_0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_uop_iw_p2_poisoned_0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_uop_is_br_0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_uop_is_jalr_0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_uop_is_jal_0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_uop_is_sfb_0; // @[core.scala:51:7]
wire [15:0] io_lsu_exe_0_req_bits_uop_br_mask_0; // @[core.scala:51:7]
wire [3:0] io_lsu_exe_0_req_bits_uop_br_tag_0; // @[core.scala:51:7]
wire [4:0] io_lsu_exe_0_req_bits_uop_ftq_idx_0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_uop_edge_inst_0; // @[core.scala:51:7]
wire [5:0] io_lsu_exe_0_req_bits_uop_pc_lob_0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_uop_taken_0; // @[core.scala:51:7]
wire [19:0] io_lsu_exe_0_req_bits_uop_imm_packed_0; // @[core.scala:51:7]
wire [11:0] io_lsu_exe_0_req_bits_uop_csr_addr_0; // @[core.scala:51:7]
wire [6:0] io_lsu_exe_0_req_bits_uop_rob_idx_0; // @[core.scala:51:7]
wire [4:0] io_lsu_exe_0_req_bits_uop_ldq_idx_0; // @[core.scala:51:7]
wire [4:0] io_lsu_exe_0_req_bits_uop_stq_idx_0; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_req_bits_uop_rxq_idx_0; // @[core.scala:51:7]
wire [6:0] io_lsu_exe_0_req_bits_uop_pdst_0; // @[core.scala:51:7]
wire [6:0] io_lsu_exe_0_req_bits_uop_prs1_0; // @[core.scala:51:7]
wire [6:0] io_lsu_exe_0_req_bits_uop_prs2_0; // @[core.scala:51:7]
wire [6:0] io_lsu_exe_0_req_bits_uop_prs3_0; // @[core.scala:51:7]
wire [4:0] io_lsu_exe_0_req_bits_uop_ppred_0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_uop_prs1_busy_0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_uop_prs2_busy_0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_uop_prs3_busy_0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_uop_ppred_busy_0; // @[core.scala:51:7]
wire [6:0] io_lsu_exe_0_req_bits_uop_stale_pdst_0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_uop_exception_0; // @[core.scala:51:7]
wire [63:0] io_lsu_exe_0_req_bits_uop_exc_cause_0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_uop_bypassable_0; // @[core.scala:51:7]
wire [4:0] io_lsu_exe_0_req_bits_uop_mem_cmd_0; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_req_bits_uop_mem_size_0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_uop_mem_signed_0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_uop_is_fence_0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_uop_is_fencei_0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_uop_is_amo_0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_uop_uses_ldq_0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_uop_uses_stq_0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_uop_is_sys_pc2epc_0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_uop_is_unique_0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_uop_flush_on_commit_0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_uop_ldst_is_rs1_0; // @[core.scala:51:7]
wire [5:0] io_lsu_exe_0_req_bits_uop_ldst_0; // @[core.scala:51:7]
wire [5:0] io_lsu_exe_0_req_bits_uop_lrs1_0; // @[core.scala:51:7]
wire [5:0] io_lsu_exe_0_req_bits_uop_lrs2_0; // @[core.scala:51:7]
wire [5:0] io_lsu_exe_0_req_bits_uop_lrs3_0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_uop_ldst_val_0; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_req_bits_uop_dst_rtype_0; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_req_bits_uop_lrs1_rtype_0; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_req_bits_uop_lrs2_rtype_0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_uop_frs3_en_0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_uop_fp_val_0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_uop_fp_single_0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_uop_xcpt_pf_if_0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_uop_xcpt_ae_if_0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_uop_xcpt_ma_if_0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_uop_bp_debug_if_0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_uop_bp_xcpt_if_0; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_req_bits_uop_debug_fsrc_0; // @[core.scala:51:7]
wire [1:0] io_lsu_exe_0_req_bits_uop_debug_tsrc_0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_mxcpt_valid_0; // @[core.scala:51:7]
wire [24:0] io_lsu_exe_0_req_bits_mxcpt_bits_0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_sfence_bits_rs1_0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_sfence_bits_rs2_0; // @[core.scala:51:7]
wire [38:0] io_lsu_exe_0_req_bits_sfence_bits_addr_0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_sfence_bits_asid_0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_bits_sfence_valid_0; // @[core.scala:51:7]
wire [63:0] io_lsu_exe_0_req_bits_data_0; // @[core.scala:51:7]
wire [39:0] io_lsu_exe_0_req_bits_addr_0; // @[core.scala:51:7]
wire io_lsu_exe_0_req_valid_0; // @[core.scala:51:7]
wire [3:0] io_lsu_dis_uops_0_bits_ctrl_br_type_0; // @[core.scala:51:7]
wire [1:0] io_lsu_dis_uops_0_bits_ctrl_op1_sel_0; // @[core.scala:51:7]
wire [2:0] io_lsu_dis_uops_0_bits_ctrl_op2_sel_0; // @[core.scala:51:7]
wire [2:0] io_lsu_dis_uops_0_bits_ctrl_imm_sel_0; // @[core.scala:51:7]
wire [4:0] io_lsu_dis_uops_0_bits_ctrl_op_fcn_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_0_bits_ctrl_fcn_dw_0; // @[core.scala:51:7]
wire [2:0] io_lsu_dis_uops_0_bits_ctrl_csr_cmd_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_0_bits_ctrl_is_load_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_0_bits_ctrl_is_sta_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_0_bits_ctrl_is_std_0; // @[core.scala:51:7]
wire [6:0] io_lsu_dis_uops_0_bits_uopc_0; // @[core.scala:51:7]
wire [31:0] io_lsu_dis_uops_0_bits_inst_0; // @[core.scala:51:7]
wire [31:0] io_lsu_dis_uops_0_bits_debug_inst_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_0_bits_is_rvc_0; // @[core.scala:51:7]
wire [39:0] io_lsu_dis_uops_0_bits_debug_pc_0; // @[core.scala:51:7]
wire [2:0] io_lsu_dis_uops_0_bits_iq_type_0; // @[core.scala:51:7]
wire [9:0] io_lsu_dis_uops_0_bits_fu_code_0; // @[core.scala:51:7]
wire [1:0] io_lsu_dis_uops_0_bits_iw_state_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_0_bits_iw_p1_poisoned_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_0_bits_iw_p2_poisoned_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_0_bits_is_br_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_0_bits_is_jalr_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_0_bits_is_jal_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_0_bits_is_sfb_0; // @[core.scala:51:7]
wire [15:0] io_lsu_dis_uops_0_bits_br_mask_0; // @[core.scala:51:7]
wire [3:0] io_lsu_dis_uops_0_bits_br_tag_0; // @[core.scala:51:7]
wire [4:0] io_lsu_dis_uops_0_bits_ftq_idx_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_0_bits_edge_inst_0; // @[core.scala:51:7]
wire [5:0] io_lsu_dis_uops_0_bits_pc_lob_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_0_bits_taken_0; // @[core.scala:51:7]
wire [19:0] io_lsu_dis_uops_0_bits_imm_packed_0; // @[core.scala:51:7]
wire [11:0] io_lsu_dis_uops_0_bits_csr_addr_0; // @[core.scala:51:7]
wire [6:0] io_lsu_dis_uops_0_bits_rob_idx_0; // @[core.scala:51:7]
wire [4:0] io_lsu_dis_uops_0_bits_ldq_idx_0; // @[core.scala:51:7]
wire [4:0] io_lsu_dis_uops_0_bits_stq_idx_0; // @[core.scala:51:7]
wire [1:0] io_lsu_dis_uops_0_bits_rxq_idx_0; // @[core.scala:51:7]
wire [6:0] io_lsu_dis_uops_0_bits_pdst_0; // @[core.scala:51:7]
wire [6:0] io_lsu_dis_uops_0_bits_prs1_0; // @[core.scala:51:7]
wire [6:0] io_lsu_dis_uops_0_bits_prs2_0; // @[core.scala:51:7]
wire [6:0] io_lsu_dis_uops_0_bits_prs3_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_0_bits_prs1_busy_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_0_bits_prs2_busy_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_0_bits_prs3_busy_0; // @[core.scala:51:7]
wire [6:0] io_lsu_dis_uops_0_bits_stale_pdst_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_0_bits_exception_0; // @[core.scala:51:7]
wire [63:0] io_lsu_dis_uops_0_bits_exc_cause_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_0_bits_bypassable_0; // @[core.scala:51:7]
wire [4:0] io_lsu_dis_uops_0_bits_mem_cmd_0; // @[core.scala:51:7]
wire [1:0] io_lsu_dis_uops_0_bits_mem_size_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_0_bits_mem_signed_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_0_bits_is_fence_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_0_bits_is_fencei_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_0_bits_is_amo_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_0_bits_uses_ldq_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_0_bits_uses_stq_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_0_bits_is_sys_pc2epc_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_0_bits_is_unique_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_0_bits_flush_on_commit_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_0_bits_ldst_is_rs1_0; // @[core.scala:51:7]
wire [5:0] io_lsu_dis_uops_0_bits_ldst_0; // @[core.scala:51:7]
wire [5:0] io_lsu_dis_uops_0_bits_lrs1_0; // @[core.scala:51:7]
wire [5:0] io_lsu_dis_uops_0_bits_lrs2_0; // @[core.scala:51:7]
wire [5:0] io_lsu_dis_uops_0_bits_lrs3_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_0_bits_ldst_val_0; // @[core.scala:51:7]
wire [1:0] io_lsu_dis_uops_0_bits_dst_rtype_0; // @[core.scala:51:7]
wire [1:0] io_lsu_dis_uops_0_bits_lrs1_rtype_0; // @[core.scala:51:7]
wire [1:0] io_lsu_dis_uops_0_bits_lrs2_rtype_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_0_bits_frs3_en_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_0_bits_fp_val_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_0_bits_fp_single_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_0_bits_xcpt_pf_if_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_0_bits_xcpt_ae_if_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_0_bits_xcpt_ma_if_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_0_bits_bp_debug_if_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_0_bits_bp_xcpt_if_0; // @[core.scala:51:7]
wire [1:0] io_lsu_dis_uops_0_bits_debug_fsrc_0; // @[core.scala:51:7]
wire [1:0] io_lsu_dis_uops_0_bits_debug_tsrc_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_0_valid_0; // @[core.scala:51:7]
wire [3:0] io_lsu_dis_uops_1_bits_ctrl_br_type_0; // @[core.scala:51:7]
wire [1:0] io_lsu_dis_uops_1_bits_ctrl_op1_sel_0; // @[core.scala:51:7]
wire [2:0] io_lsu_dis_uops_1_bits_ctrl_op2_sel_0; // @[core.scala:51:7]
wire [2:0] io_lsu_dis_uops_1_bits_ctrl_imm_sel_0; // @[core.scala:51:7]
wire [4:0] io_lsu_dis_uops_1_bits_ctrl_op_fcn_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_1_bits_ctrl_fcn_dw_0; // @[core.scala:51:7]
wire [2:0] io_lsu_dis_uops_1_bits_ctrl_csr_cmd_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_1_bits_ctrl_is_load_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_1_bits_ctrl_is_sta_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_1_bits_ctrl_is_std_0; // @[core.scala:51:7]
wire [6:0] io_lsu_dis_uops_1_bits_uopc_0; // @[core.scala:51:7]
wire [31:0] io_lsu_dis_uops_1_bits_inst_0; // @[core.scala:51:7]
wire [31:0] io_lsu_dis_uops_1_bits_debug_inst_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_1_bits_is_rvc_0; // @[core.scala:51:7]
wire [39:0] io_lsu_dis_uops_1_bits_debug_pc_0; // @[core.scala:51:7]
wire [2:0] io_lsu_dis_uops_1_bits_iq_type_0; // @[core.scala:51:7]
wire [9:0] io_lsu_dis_uops_1_bits_fu_code_0; // @[core.scala:51:7]
wire [1:0] io_lsu_dis_uops_1_bits_iw_state_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_1_bits_iw_p1_poisoned_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_1_bits_iw_p2_poisoned_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_1_bits_is_br_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_1_bits_is_jalr_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_1_bits_is_jal_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_1_bits_is_sfb_0; // @[core.scala:51:7]
wire [15:0] io_lsu_dis_uops_1_bits_br_mask_0; // @[core.scala:51:7]
wire [3:0] io_lsu_dis_uops_1_bits_br_tag_0; // @[core.scala:51:7]
wire [4:0] io_lsu_dis_uops_1_bits_ftq_idx_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_1_bits_edge_inst_0; // @[core.scala:51:7]
wire [5:0] io_lsu_dis_uops_1_bits_pc_lob_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_1_bits_taken_0; // @[core.scala:51:7]
wire [19:0] io_lsu_dis_uops_1_bits_imm_packed_0; // @[core.scala:51:7]
wire [11:0] io_lsu_dis_uops_1_bits_csr_addr_0; // @[core.scala:51:7]
wire [6:0] io_lsu_dis_uops_1_bits_rob_idx_0; // @[core.scala:51:7]
wire [4:0] io_lsu_dis_uops_1_bits_ldq_idx_0; // @[core.scala:51:7]
wire [4:0] io_lsu_dis_uops_1_bits_stq_idx_0; // @[core.scala:51:7]
wire [1:0] io_lsu_dis_uops_1_bits_rxq_idx_0; // @[core.scala:51:7]
wire [6:0] io_lsu_dis_uops_1_bits_pdst_0; // @[core.scala:51:7]
wire [6:0] io_lsu_dis_uops_1_bits_prs1_0; // @[core.scala:51:7]
wire [6:0] io_lsu_dis_uops_1_bits_prs2_0; // @[core.scala:51:7]
wire [6:0] io_lsu_dis_uops_1_bits_prs3_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_1_bits_prs1_busy_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_1_bits_prs2_busy_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_1_bits_prs3_busy_0; // @[core.scala:51:7]
wire [6:0] io_lsu_dis_uops_1_bits_stale_pdst_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_1_bits_exception_0; // @[core.scala:51:7]
wire [63:0] io_lsu_dis_uops_1_bits_exc_cause_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_1_bits_bypassable_0; // @[core.scala:51:7]
wire [4:0] io_lsu_dis_uops_1_bits_mem_cmd_0; // @[core.scala:51:7]
wire [1:0] io_lsu_dis_uops_1_bits_mem_size_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_1_bits_mem_signed_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_1_bits_is_fence_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_1_bits_is_fencei_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_1_bits_is_amo_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_1_bits_uses_ldq_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_1_bits_uses_stq_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_1_bits_is_sys_pc2epc_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_1_bits_is_unique_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_1_bits_flush_on_commit_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_1_bits_ldst_is_rs1_0; // @[core.scala:51:7]
wire [5:0] io_lsu_dis_uops_1_bits_ldst_0; // @[core.scala:51:7]
wire [5:0] io_lsu_dis_uops_1_bits_lrs1_0; // @[core.scala:51:7]
wire [5:0] io_lsu_dis_uops_1_bits_lrs2_0; // @[core.scala:51:7]
wire [5:0] io_lsu_dis_uops_1_bits_lrs3_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_1_bits_ldst_val_0; // @[core.scala:51:7]
wire [1:0] io_lsu_dis_uops_1_bits_dst_rtype_0; // @[core.scala:51:7]
wire [1:0] io_lsu_dis_uops_1_bits_lrs1_rtype_0; // @[core.scala:51:7]
wire [1:0] io_lsu_dis_uops_1_bits_lrs2_rtype_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_1_bits_frs3_en_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_1_bits_fp_val_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_1_bits_fp_single_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_1_bits_xcpt_pf_if_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_1_bits_xcpt_ae_if_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_1_bits_xcpt_ma_if_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_1_bits_bp_debug_if_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_1_bits_bp_xcpt_if_0; // @[core.scala:51:7]
wire [1:0] io_lsu_dis_uops_1_bits_debug_fsrc_0; // @[core.scala:51:7]
wire [1:0] io_lsu_dis_uops_1_bits_debug_tsrc_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_1_valid_0; // @[core.scala:51:7]
wire [3:0] io_lsu_dis_uops_2_bits_ctrl_br_type_0; // @[core.scala:51:7]
wire [1:0] io_lsu_dis_uops_2_bits_ctrl_op1_sel_0; // @[core.scala:51:7]
wire [2:0] io_lsu_dis_uops_2_bits_ctrl_op2_sel_0; // @[core.scala:51:7]
wire [2:0] io_lsu_dis_uops_2_bits_ctrl_imm_sel_0; // @[core.scala:51:7]
wire [4:0] io_lsu_dis_uops_2_bits_ctrl_op_fcn_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_2_bits_ctrl_fcn_dw_0; // @[core.scala:51:7]
wire [2:0] io_lsu_dis_uops_2_bits_ctrl_csr_cmd_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_2_bits_ctrl_is_load_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_2_bits_ctrl_is_sta_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_2_bits_ctrl_is_std_0; // @[core.scala:51:7]
wire [6:0] io_lsu_dis_uops_2_bits_uopc_0; // @[core.scala:51:7]
wire [31:0] io_lsu_dis_uops_2_bits_inst_0; // @[core.scala:51:7]
wire [31:0] io_lsu_dis_uops_2_bits_debug_inst_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_2_bits_is_rvc_0; // @[core.scala:51:7]
wire [39:0] io_lsu_dis_uops_2_bits_debug_pc_0; // @[core.scala:51:7]
wire [2:0] io_lsu_dis_uops_2_bits_iq_type_0; // @[core.scala:51:7]
wire [9:0] io_lsu_dis_uops_2_bits_fu_code_0; // @[core.scala:51:7]
wire [1:0] io_lsu_dis_uops_2_bits_iw_state_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_2_bits_iw_p1_poisoned_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_2_bits_iw_p2_poisoned_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_2_bits_is_br_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_2_bits_is_jalr_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_2_bits_is_jal_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_2_bits_is_sfb_0; // @[core.scala:51:7]
wire [15:0] io_lsu_dis_uops_2_bits_br_mask_0; // @[core.scala:51:7]
wire [3:0] io_lsu_dis_uops_2_bits_br_tag_0; // @[core.scala:51:7]
wire [4:0] io_lsu_dis_uops_2_bits_ftq_idx_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_2_bits_edge_inst_0; // @[core.scala:51:7]
wire [5:0] io_lsu_dis_uops_2_bits_pc_lob_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_2_bits_taken_0; // @[core.scala:51:7]
wire [19:0] io_lsu_dis_uops_2_bits_imm_packed_0; // @[core.scala:51:7]
wire [11:0] io_lsu_dis_uops_2_bits_csr_addr_0; // @[core.scala:51:7]
wire [6:0] io_lsu_dis_uops_2_bits_rob_idx_0; // @[core.scala:51:7]
wire [4:0] io_lsu_dis_uops_2_bits_ldq_idx_0; // @[core.scala:51:7]
wire [4:0] io_lsu_dis_uops_2_bits_stq_idx_0; // @[core.scala:51:7]
wire [1:0] io_lsu_dis_uops_2_bits_rxq_idx_0; // @[core.scala:51:7]
wire [6:0] io_lsu_dis_uops_2_bits_pdst_0; // @[core.scala:51:7]
wire [6:0] io_lsu_dis_uops_2_bits_prs1_0; // @[core.scala:51:7]
wire [6:0] io_lsu_dis_uops_2_bits_prs2_0; // @[core.scala:51:7]
wire [6:0] io_lsu_dis_uops_2_bits_prs3_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_2_bits_prs1_busy_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_2_bits_prs2_busy_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_2_bits_prs3_busy_0; // @[core.scala:51:7]
wire [6:0] io_lsu_dis_uops_2_bits_stale_pdst_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_2_bits_exception_0; // @[core.scala:51:7]
wire [63:0] io_lsu_dis_uops_2_bits_exc_cause_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_2_bits_bypassable_0; // @[core.scala:51:7]
wire [4:0] io_lsu_dis_uops_2_bits_mem_cmd_0; // @[core.scala:51:7]
wire [1:0] io_lsu_dis_uops_2_bits_mem_size_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_2_bits_mem_signed_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_2_bits_is_fence_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_2_bits_is_fencei_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_2_bits_is_amo_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_2_bits_uses_ldq_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_2_bits_uses_stq_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_2_bits_is_sys_pc2epc_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_2_bits_is_unique_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_2_bits_flush_on_commit_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_2_bits_ldst_is_rs1_0; // @[core.scala:51:7]
wire [5:0] io_lsu_dis_uops_2_bits_ldst_0; // @[core.scala:51:7]
wire [5:0] io_lsu_dis_uops_2_bits_lrs1_0; // @[core.scala:51:7]
wire [5:0] io_lsu_dis_uops_2_bits_lrs2_0; // @[core.scala:51:7]
wire [5:0] io_lsu_dis_uops_2_bits_lrs3_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_2_bits_ldst_val_0; // @[core.scala:51:7]
wire [1:0] io_lsu_dis_uops_2_bits_dst_rtype_0; // @[core.scala:51:7]
wire [1:0] io_lsu_dis_uops_2_bits_lrs1_rtype_0; // @[core.scala:51:7]
wire [1:0] io_lsu_dis_uops_2_bits_lrs2_rtype_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_2_bits_frs3_en_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_2_bits_fp_val_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_2_bits_fp_single_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_2_bits_xcpt_pf_if_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_2_bits_xcpt_ae_if_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_2_bits_xcpt_ma_if_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_2_bits_bp_debug_if_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_2_bits_bp_xcpt_if_0; // @[core.scala:51:7]
wire [1:0] io_lsu_dis_uops_2_bits_debug_fsrc_0; // @[core.scala:51:7]
wire [1:0] io_lsu_dis_uops_2_bits_debug_tsrc_0; // @[core.scala:51:7]
wire io_lsu_dis_uops_2_valid_0; // @[core.scala:51:7]
wire [3:0] io_lsu_fp_stdata_bits_uop_ctrl_br_type_0; // @[core.scala:51:7]
wire [1:0] io_lsu_fp_stdata_bits_uop_ctrl_op1_sel_0; // @[core.scala:51:7]
wire [2:0] io_lsu_fp_stdata_bits_uop_ctrl_op2_sel_0; // @[core.scala:51:7]
wire [2:0] io_lsu_fp_stdata_bits_uop_ctrl_imm_sel_0; // @[core.scala:51:7]
wire [4:0] io_lsu_fp_stdata_bits_uop_ctrl_op_fcn_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_uop_ctrl_fcn_dw_0; // @[core.scala:51:7]
wire [2:0] io_lsu_fp_stdata_bits_uop_ctrl_csr_cmd_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_uop_ctrl_is_load_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_uop_ctrl_is_sta_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_uop_ctrl_is_std_0; // @[core.scala:51:7]
wire [6:0] io_lsu_fp_stdata_bits_uop_uopc_0; // @[core.scala:51:7]
wire [31:0] io_lsu_fp_stdata_bits_uop_inst_0; // @[core.scala:51:7]
wire [31:0] io_lsu_fp_stdata_bits_uop_debug_inst_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_uop_is_rvc_0; // @[core.scala:51:7]
wire [39:0] io_lsu_fp_stdata_bits_uop_debug_pc_0; // @[core.scala:51:7]
wire [2:0] io_lsu_fp_stdata_bits_uop_iq_type_0; // @[core.scala:51:7]
wire [9:0] io_lsu_fp_stdata_bits_uop_fu_code_0; // @[core.scala:51:7]
wire [1:0] io_lsu_fp_stdata_bits_uop_iw_state_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_uop_iw_p1_poisoned_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_uop_iw_p2_poisoned_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_uop_is_br_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_uop_is_jalr_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_uop_is_jal_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_uop_is_sfb_0; // @[core.scala:51:7]
wire [15:0] io_lsu_fp_stdata_bits_uop_br_mask_0; // @[core.scala:51:7]
wire [3:0] io_lsu_fp_stdata_bits_uop_br_tag_0; // @[core.scala:51:7]
wire [4:0] io_lsu_fp_stdata_bits_uop_ftq_idx_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_uop_edge_inst_0; // @[core.scala:51:7]
wire [5:0] io_lsu_fp_stdata_bits_uop_pc_lob_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_uop_taken_0; // @[core.scala:51:7]
wire [19:0] io_lsu_fp_stdata_bits_uop_imm_packed_0; // @[core.scala:51:7]
wire [11:0] io_lsu_fp_stdata_bits_uop_csr_addr_0; // @[core.scala:51:7]
wire [6:0] io_lsu_fp_stdata_bits_uop_rob_idx_0; // @[core.scala:51:7]
wire [4:0] io_lsu_fp_stdata_bits_uop_ldq_idx_0; // @[core.scala:51:7]
wire [4:0] io_lsu_fp_stdata_bits_uop_stq_idx_0; // @[core.scala:51:7]
wire [1:0] io_lsu_fp_stdata_bits_uop_rxq_idx_0; // @[core.scala:51:7]
wire [6:0] io_lsu_fp_stdata_bits_uop_pdst_0; // @[core.scala:51:7]
wire [6:0] io_lsu_fp_stdata_bits_uop_prs1_0; // @[core.scala:51:7]
wire [6:0] io_lsu_fp_stdata_bits_uop_prs2_0; // @[core.scala:51:7]
wire [6:0] io_lsu_fp_stdata_bits_uop_prs3_0; // @[core.scala:51:7]
wire [4:0] io_lsu_fp_stdata_bits_uop_ppred_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_uop_prs1_busy_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_uop_prs2_busy_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_uop_prs3_busy_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_uop_ppred_busy_0; // @[core.scala:51:7]
wire [6:0] io_lsu_fp_stdata_bits_uop_stale_pdst_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_uop_exception_0; // @[core.scala:51:7]
wire [63:0] io_lsu_fp_stdata_bits_uop_exc_cause_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_uop_bypassable_0; // @[core.scala:51:7]
wire [4:0] io_lsu_fp_stdata_bits_uop_mem_cmd_0; // @[core.scala:51:7]
wire [1:0] io_lsu_fp_stdata_bits_uop_mem_size_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_uop_mem_signed_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_uop_is_fence_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_uop_is_fencei_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_uop_is_amo_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_uop_uses_ldq_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_uop_uses_stq_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_uop_is_sys_pc2epc_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_uop_is_unique_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_uop_flush_on_commit_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_uop_ldst_is_rs1_0; // @[core.scala:51:7]
wire [5:0] io_lsu_fp_stdata_bits_uop_ldst_0; // @[core.scala:51:7]
wire [5:0] io_lsu_fp_stdata_bits_uop_lrs1_0; // @[core.scala:51:7]
wire [5:0] io_lsu_fp_stdata_bits_uop_lrs2_0; // @[core.scala:51:7]
wire [5:0] io_lsu_fp_stdata_bits_uop_lrs3_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_uop_ldst_val_0; // @[core.scala:51:7]
wire [1:0] io_lsu_fp_stdata_bits_uop_dst_rtype_0; // @[core.scala:51:7]
wire [1:0] io_lsu_fp_stdata_bits_uop_lrs1_rtype_0; // @[core.scala:51:7]
wire [1:0] io_lsu_fp_stdata_bits_uop_lrs2_rtype_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_uop_frs3_en_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_uop_fp_val_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_uop_fp_single_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_uop_xcpt_pf_if_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_uop_xcpt_ae_if_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_uop_xcpt_ma_if_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_uop_bp_debug_if_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_uop_bp_xcpt_if_0; // @[core.scala:51:7]
wire [1:0] io_lsu_fp_stdata_bits_uop_debug_fsrc_0; // @[core.scala:51:7]
wire [1:0] io_lsu_fp_stdata_bits_uop_debug_tsrc_0; // @[core.scala:51:7]
wire [3:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_br_type_0; // @[core.scala:51:7]
wire [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_op1_sel_0; // @[core.scala:51:7]
wire [2:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_op2_sel_0; // @[core.scala:51:7]
wire [2:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_imm_sel_0; // @[core.scala:51:7]
wire [4:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_op_fcn_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_fcn_dw_0; // @[core.scala:51:7]
wire [2:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_csr_cmd_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_is_load_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_is_sta_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_is_std_0; // @[core.scala:51:7]
wire [6:0] io_lsu_fp_stdata_bits_fflags_bits_uop_uopc_0; // @[core.scala:51:7]
wire [31:0] io_lsu_fp_stdata_bits_fflags_bits_uop_inst_0; // @[core.scala:51:7]
wire [31:0] io_lsu_fp_stdata_bits_fflags_bits_uop_debug_inst_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_is_rvc_0; // @[core.scala:51:7]
wire [39:0] io_lsu_fp_stdata_bits_fflags_bits_uop_debug_pc_0; // @[core.scala:51:7]
wire [2:0] io_lsu_fp_stdata_bits_fflags_bits_uop_iq_type_0; // @[core.scala:51:7]
wire [9:0] io_lsu_fp_stdata_bits_fflags_bits_uop_fu_code_0; // @[core.scala:51:7]
wire [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_iw_state_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_iw_p1_poisoned_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_iw_p2_poisoned_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_is_br_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_is_jalr_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_is_jal_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_is_sfb_0; // @[core.scala:51:7]
wire [15:0] io_lsu_fp_stdata_bits_fflags_bits_uop_br_mask_0; // @[core.scala:51:7]
wire [3:0] io_lsu_fp_stdata_bits_fflags_bits_uop_br_tag_0; // @[core.scala:51:7]
wire [4:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ftq_idx_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_edge_inst_0; // @[core.scala:51:7]
wire [5:0] io_lsu_fp_stdata_bits_fflags_bits_uop_pc_lob_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_taken_0; // @[core.scala:51:7]
wire [19:0] io_lsu_fp_stdata_bits_fflags_bits_uop_imm_packed_0; // @[core.scala:51:7]
wire [11:0] io_lsu_fp_stdata_bits_fflags_bits_uop_csr_addr_0; // @[core.scala:51:7]
wire [6:0] io_lsu_fp_stdata_bits_fflags_bits_uop_rob_idx_0; // @[core.scala:51:7]
wire [4:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ldq_idx_0; // @[core.scala:51:7]
wire [4:0] io_lsu_fp_stdata_bits_fflags_bits_uop_stq_idx_0; // @[core.scala:51:7]
wire [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_rxq_idx_0; // @[core.scala:51:7]
wire [6:0] io_lsu_fp_stdata_bits_fflags_bits_uop_pdst_0; // @[core.scala:51:7]
wire [6:0] io_lsu_fp_stdata_bits_fflags_bits_uop_prs1_0; // @[core.scala:51:7]
wire [6:0] io_lsu_fp_stdata_bits_fflags_bits_uop_prs2_0; // @[core.scala:51:7]
wire [6:0] io_lsu_fp_stdata_bits_fflags_bits_uop_prs3_0; // @[core.scala:51:7]
wire [4:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ppred_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_prs1_busy_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_prs2_busy_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_prs3_busy_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_ppred_busy_0; // @[core.scala:51:7]
wire [6:0] io_lsu_fp_stdata_bits_fflags_bits_uop_stale_pdst_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_exception_0; // @[core.scala:51:7]
wire [63:0] io_lsu_fp_stdata_bits_fflags_bits_uop_exc_cause_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_bypassable_0; // @[core.scala:51:7]
wire [4:0] io_lsu_fp_stdata_bits_fflags_bits_uop_mem_cmd_0; // @[core.scala:51:7]
wire [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_mem_size_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_mem_signed_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_is_fence_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_is_fencei_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_is_amo_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_uses_ldq_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_uses_stq_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_is_sys_pc2epc_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_is_unique_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_flush_on_commit_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_ldst_is_rs1_0; // @[core.scala:51:7]
wire [5:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ldst_0; // @[core.scala:51:7]
wire [5:0] io_lsu_fp_stdata_bits_fflags_bits_uop_lrs1_0; // @[core.scala:51:7]
wire [5:0] io_lsu_fp_stdata_bits_fflags_bits_uop_lrs2_0; // @[core.scala:51:7]
wire [5:0] io_lsu_fp_stdata_bits_fflags_bits_uop_lrs3_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_ldst_val_0; // @[core.scala:51:7]
wire [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_dst_rtype_0; // @[core.scala:51:7]
wire [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_lrs1_rtype_0; // @[core.scala:51:7]
wire [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_lrs2_rtype_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_frs3_en_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_fp_val_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_fp_single_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_xcpt_pf_if_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_xcpt_ae_if_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_xcpt_ma_if_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_bp_debug_if_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_bp_xcpt_if_0; // @[core.scala:51:7]
wire [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_debug_fsrc_0; // @[core.scala:51:7]
wire [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_debug_tsrc_0; // @[core.scala:51:7]
wire [4:0] io_lsu_fp_stdata_bits_fflags_bits_flags_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_fflags_valid_0; // @[core.scala:51:7]
wire [63:0] io_lsu_fp_stdata_bits_data_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_bits_predicated_0; // @[core.scala:51:7]
wire io_lsu_fp_stdata_valid_0; // @[core.scala:51:7]
wire io_lsu_commit_valids_0_0; // @[core.scala:51:7]
wire io_lsu_commit_valids_1_0; // @[core.scala:51:7]
wire io_lsu_commit_valids_2_0; // @[core.scala:51:7]
wire io_lsu_commit_arch_valids_0_0; // @[core.scala:51:7]
wire io_lsu_commit_arch_valids_1_0; // @[core.scala:51:7]
wire io_lsu_commit_arch_valids_2_0; // @[core.scala:51:7]
wire [3:0] io_lsu_commit_uops_0_ctrl_br_type_0; // @[core.scala:51:7]
wire [1:0] io_lsu_commit_uops_0_ctrl_op1_sel_0; // @[core.scala:51:7]
wire [2:0] io_lsu_commit_uops_0_ctrl_op2_sel_0; // @[core.scala:51:7]
wire [2:0] io_lsu_commit_uops_0_ctrl_imm_sel_0; // @[core.scala:51:7]
wire [4:0] io_lsu_commit_uops_0_ctrl_op_fcn_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_0_ctrl_fcn_dw_0; // @[core.scala:51:7]
wire [2:0] io_lsu_commit_uops_0_ctrl_csr_cmd_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_0_ctrl_is_load_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_0_ctrl_is_sta_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_0_ctrl_is_std_0; // @[core.scala:51:7]
wire [6:0] io_lsu_commit_uops_0_uopc_0; // @[core.scala:51:7]
wire [31:0] io_lsu_commit_uops_0_inst_0; // @[core.scala:51:7]
wire [31:0] io_lsu_commit_uops_0_debug_inst_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_0_is_rvc_0; // @[core.scala:51:7]
wire [39:0] io_lsu_commit_uops_0_debug_pc_0; // @[core.scala:51:7]
wire [2:0] io_lsu_commit_uops_0_iq_type_0; // @[core.scala:51:7]
wire [9:0] io_lsu_commit_uops_0_fu_code_0; // @[core.scala:51:7]
wire [1:0] io_lsu_commit_uops_0_iw_state_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_0_iw_p1_poisoned_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_0_iw_p2_poisoned_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_0_is_br_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_0_is_jalr_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_0_is_jal_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_0_is_sfb_0; // @[core.scala:51:7]
wire [15:0] io_lsu_commit_uops_0_br_mask_0; // @[core.scala:51:7]
wire [3:0] io_lsu_commit_uops_0_br_tag_0; // @[core.scala:51:7]
wire [4:0] io_lsu_commit_uops_0_ftq_idx_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_0_edge_inst_0; // @[core.scala:51:7]
wire [5:0] io_lsu_commit_uops_0_pc_lob_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_0_taken_0; // @[core.scala:51:7]
wire [19:0] io_lsu_commit_uops_0_imm_packed_0; // @[core.scala:51:7]
wire [11:0] io_lsu_commit_uops_0_csr_addr_0; // @[core.scala:51:7]
wire [6:0] io_lsu_commit_uops_0_rob_idx_0; // @[core.scala:51:7]
wire [4:0] io_lsu_commit_uops_0_ldq_idx_0; // @[core.scala:51:7]
wire [4:0] io_lsu_commit_uops_0_stq_idx_0; // @[core.scala:51:7]
wire [1:0] io_lsu_commit_uops_0_rxq_idx_0; // @[core.scala:51:7]
wire [6:0] io_lsu_commit_uops_0_pdst_0; // @[core.scala:51:7]
wire [6:0] io_lsu_commit_uops_0_prs1_0; // @[core.scala:51:7]
wire [6:0] io_lsu_commit_uops_0_prs2_0; // @[core.scala:51:7]
wire [6:0] io_lsu_commit_uops_0_prs3_0; // @[core.scala:51:7]
wire [4:0] io_lsu_commit_uops_0_ppred_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_0_prs1_busy_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_0_prs2_busy_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_0_prs3_busy_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_0_ppred_busy_0; // @[core.scala:51:7]
wire [6:0] io_lsu_commit_uops_0_stale_pdst_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_0_exception_0; // @[core.scala:51:7]
wire [63:0] io_lsu_commit_uops_0_exc_cause_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_0_bypassable_0; // @[core.scala:51:7]
wire [4:0] io_lsu_commit_uops_0_mem_cmd_0; // @[core.scala:51:7]
wire [1:0] io_lsu_commit_uops_0_mem_size_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_0_mem_signed_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_0_is_fence_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_0_is_fencei_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_0_is_amo_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_0_uses_ldq_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_0_uses_stq_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_0_is_sys_pc2epc_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_0_is_unique_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_0_flush_on_commit_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_0_ldst_is_rs1_0; // @[core.scala:51:7]
wire [5:0] io_lsu_commit_uops_0_ldst_0; // @[core.scala:51:7]
wire [5:0] io_lsu_commit_uops_0_lrs1_0; // @[core.scala:51:7]
wire [5:0] io_lsu_commit_uops_0_lrs2_0; // @[core.scala:51:7]
wire [5:0] io_lsu_commit_uops_0_lrs3_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_0_ldst_val_0; // @[core.scala:51:7]
wire [1:0] io_lsu_commit_uops_0_dst_rtype_0; // @[core.scala:51:7]
wire [1:0] io_lsu_commit_uops_0_lrs1_rtype_0; // @[core.scala:51:7]
wire [1:0] io_lsu_commit_uops_0_lrs2_rtype_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_0_frs3_en_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_0_fp_val_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_0_fp_single_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_0_xcpt_pf_if_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_0_xcpt_ae_if_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_0_xcpt_ma_if_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_0_bp_debug_if_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_0_bp_xcpt_if_0; // @[core.scala:51:7]
wire [1:0] io_lsu_commit_uops_0_debug_fsrc_0; // @[core.scala:51:7]
wire [1:0] io_lsu_commit_uops_0_debug_tsrc_0; // @[core.scala:51:7]
wire [3:0] io_lsu_commit_uops_1_ctrl_br_type_0; // @[core.scala:51:7]
wire [1:0] io_lsu_commit_uops_1_ctrl_op1_sel_0; // @[core.scala:51:7]
wire [2:0] io_lsu_commit_uops_1_ctrl_op2_sel_0; // @[core.scala:51:7]
wire [2:0] io_lsu_commit_uops_1_ctrl_imm_sel_0; // @[core.scala:51:7]
wire [4:0] io_lsu_commit_uops_1_ctrl_op_fcn_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_1_ctrl_fcn_dw_0; // @[core.scala:51:7]
wire [2:0] io_lsu_commit_uops_1_ctrl_csr_cmd_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_1_ctrl_is_load_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_1_ctrl_is_sta_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_1_ctrl_is_std_0; // @[core.scala:51:7]
wire [6:0] io_lsu_commit_uops_1_uopc_0; // @[core.scala:51:7]
wire [31:0] io_lsu_commit_uops_1_inst_0; // @[core.scala:51:7]
wire [31:0] io_lsu_commit_uops_1_debug_inst_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_1_is_rvc_0; // @[core.scala:51:7]
wire [39:0] io_lsu_commit_uops_1_debug_pc_0; // @[core.scala:51:7]
wire [2:0] io_lsu_commit_uops_1_iq_type_0; // @[core.scala:51:7]
wire [9:0] io_lsu_commit_uops_1_fu_code_0; // @[core.scala:51:7]
wire [1:0] io_lsu_commit_uops_1_iw_state_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_1_iw_p1_poisoned_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_1_iw_p2_poisoned_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_1_is_br_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_1_is_jalr_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_1_is_jal_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_1_is_sfb_0; // @[core.scala:51:7]
wire [15:0] io_lsu_commit_uops_1_br_mask_0; // @[core.scala:51:7]
wire [3:0] io_lsu_commit_uops_1_br_tag_0; // @[core.scala:51:7]
wire [4:0] io_lsu_commit_uops_1_ftq_idx_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_1_edge_inst_0; // @[core.scala:51:7]
wire [5:0] io_lsu_commit_uops_1_pc_lob_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_1_taken_0; // @[core.scala:51:7]
wire [19:0] io_lsu_commit_uops_1_imm_packed_0; // @[core.scala:51:7]
wire [11:0] io_lsu_commit_uops_1_csr_addr_0; // @[core.scala:51:7]
wire [6:0] io_lsu_commit_uops_1_rob_idx_0; // @[core.scala:51:7]
wire [4:0] io_lsu_commit_uops_1_ldq_idx_0; // @[core.scala:51:7]
wire [4:0] io_lsu_commit_uops_1_stq_idx_0; // @[core.scala:51:7]
wire [1:0] io_lsu_commit_uops_1_rxq_idx_0; // @[core.scala:51:7]
wire [6:0] io_lsu_commit_uops_1_pdst_0; // @[core.scala:51:7]
wire [6:0] io_lsu_commit_uops_1_prs1_0; // @[core.scala:51:7]
wire [6:0] io_lsu_commit_uops_1_prs2_0; // @[core.scala:51:7]
wire [6:0] io_lsu_commit_uops_1_prs3_0; // @[core.scala:51:7]
wire [4:0] io_lsu_commit_uops_1_ppred_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_1_prs1_busy_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_1_prs2_busy_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_1_prs3_busy_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_1_ppred_busy_0; // @[core.scala:51:7]
wire [6:0] io_lsu_commit_uops_1_stale_pdst_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_1_exception_0; // @[core.scala:51:7]
wire [63:0] io_lsu_commit_uops_1_exc_cause_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_1_bypassable_0; // @[core.scala:51:7]
wire [4:0] io_lsu_commit_uops_1_mem_cmd_0; // @[core.scala:51:7]
wire [1:0] io_lsu_commit_uops_1_mem_size_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_1_mem_signed_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_1_is_fence_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_1_is_fencei_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_1_is_amo_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_1_uses_ldq_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_1_uses_stq_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_1_is_sys_pc2epc_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_1_is_unique_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_1_flush_on_commit_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_1_ldst_is_rs1_0; // @[core.scala:51:7]
wire [5:0] io_lsu_commit_uops_1_ldst_0; // @[core.scala:51:7]
wire [5:0] io_lsu_commit_uops_1_lrs1_0; // @[core.scala:51:7]
wire [5:0] io_lsu_commit_uops_1_lrs2_0; // @[core.scala:51:7]
wire [5:0] io_lsu_commit_uops_1_lrs3_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_1_ldst_val_0; // @[core.scala:51:7]
wire [1:0] io_lsu_commit_uops_1_dst_rtype_0; // @[core.scala:51:7]
wire [1:0] io_lsu_commit_uops_1_lrs1_rtype_0; // @[core.scala:51:7]
wire [1:0] io_lsu_commit_uops_1_lrs2_rtype_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_1_frs3_en_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_1_fp_val_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_1_fp_single_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_1_xcpt_pf_if_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_1_xcpt_ae_if_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_1_xcpt_ma_if_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_1_bp_debug_if_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_1_bp_xcpt_if_0; // @[core.scala:51:7]
wire [1:0] io_lsu_commit_uops_1_debug_fsrc_0; // @[core.scala:51:7]
wire [1:0] io_lsu_commit_uops_1_debug_tsrc_0; // @[core.scala:51:7]
wire [3:0] io_lsu_commit_uops_2_ctrl_br_type_0; // @[core.scala:51:7]
wire [1:0] io_lsu_commit_uops_2_ctrl_op1_sel_0; // @[core.scala:51:7]
wire [2:0] io_lsu_commit_uops_2_ctrl_op2_sel_0; // @[core.scala:51:7]
wire [2:0] io_lsu_commit_uops_2_ctrl_imm_sel_0; // @[core.scala:51:7]
wire [4:0] io_lsu_commit_uops_2_ctrl_op_fcn_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_2_ctrl_fcn_dw_0; // @[core.scala:51:7]
wire [2:0] io_lsu_commit_uops_2_ctrl_csr_cmd_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_2_ctrl_is_load_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_2_ctrl_is_sta_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_2_ctrl_is_std_0; // @[core.scala:51:7]
wire [6:0] io_lsu_commit_uops_2_uopc_0; // @[core.scala:51:7]
wire [31:0] io_lsu_commit_uops_2_inst_0; // @[core.scala:51:7]
wire [31:0] io_lsu_commit_uops_2_debug_inst_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_2_is_rvc_0; // @[core.scala:51:7]
wire [39:0] io_lsu_commit_uops_2_debug_pc_0; // @[core.scala:51:7]
wire [2:0] io_lsu_commit_uops_2_iq_type_0; // @[core.scala:51:7]
wire [9:0] io_lsu_commit_uops_2_fu_code_0; // @[core.scala:51:7]
wire [1:0] io_lsu_commit_uops_2_iw_state_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_2_iw_p1_poisoned_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_2_iw_p2_poisoned_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_2_is_br_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_2_is_jalr_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_2_is_jal_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_2_is_sfb_0; // @[core.scala:51:7]
wire [15:0] io_lsu_commit_uops_2_br_mask_0; // @[core.scala:51:7]
wire [3:0] io_lsu_commit_uops_2_br_tag_0; // @[core.scala:51:7]
wire [4:0] io_lsu_commit_uops_2_ftq_idx_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_2_edge_inst_0; // @[core.scala:51:7]
wire [5:0] io_lsu_commit_uops_2_pc_lob_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_2_taken_0; // @[core.scala:51:7]
wire [19:0] io_lsu_commit_uops_2_imm_packed_0; // @[core.scala:51:7]
wire [11:0] io_lsu_commit_uops_2_csr_addr_0; // @[core.scala:51:7]
wire [6:0] io_lsu_commit_uops_2_rob_idx_0; // @[core.scala:51:7]
wire [4:0] io_lsu_commit_uops_2_ldq_idx_0; // @[core.scala:51:7]
wire [4:0] io_lsu_commit_uops_2_stq_idx_0; // @[core.scala:51:7]
wire [1:0] io_lsu_commit_uops_2_rxq_idx_0; // @[core.scala:51:7]
wire [6:0] io_lsu_commit_uops_2_pdst_0; // @[core.scala:51:7]
wire [6:0] io_lsu_commit_uops_2_prs1_0; // @[core.scala:51:7]
wire [6:0] io_lsu_commit_uops_2_prs2_0; // @[core.scala:51:7]
wire [6:0] io_lsu_commit_uops_2_prs3_0; // @[core.scala:51:7]
wire [4:0] io_lsu_commit_uops_2_ppred_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_2_prs1_busy_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_2_prs2_busy_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_2_prs3_busy_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_2_ppred_busy_0; // @[core.scala:51:7]
wire [6:0] io_lsu_commit_uops_2_stale_pdst_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_2_exception_0; // @[core.scala:51:7]
wire [63:0] io_lsu_commit_uops_2_exc_cause_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_2_bypassable_0; // @[core.scala:51:7]
wire [4:0] io_lsu_commit_uops_2_mem_cmd_0; // @[core.scala:51:7]
wire [1:0] io_lsu_commit_uops_2_mem_size_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_2_mem_signed_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_2_is_fence_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_2_is_fencei_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_2_is_amo_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_2_uses_ldq_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_2_uses_stq_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_2_is_sys_pc2epc_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_2_is_unique_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_2_flush_on_commit_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_2_ldst_is_rs1_0; // @[core.scala:51:7]
wire [5:0] io_lsu_commit_uops_2_ldst_0; // @[core.scala:51:7]
wire [5:0] io_lsu_commit_uops_2_lrs1_0; // @[core.scala:51:7]
wire [5:0] io_lsu_commit_uops_2_lrs2_0; // @[core.scala:51:7]
wire [5:0] io_lsu_commit_uops_2_lrs3_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_2_ldst_val_0; // @[core.scala:51:7]
wire [1:0] io_lsu_commit_uops_2_dst_rtype_0; // @[core.scala:51:7]
wire [1:0] io_lsu_commit_uops_2_lrs1_rtype_0; // @[core.scala:51:7]
wire [1:0] io_lsu_commit_uops_2_lrs2_rtype_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_2_frs3_en_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_2_fp_val_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_2_fp_single_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_2_xcpt_pf_if_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_2_xcpt_ae_if_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_2_xcpt_ma_if_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_2_bp_debug_if_0; // @[core.scala:51:7]
wire io_lsu_commit_uops_2_bp_xcpt_if_0; // @[core.scala:51:7]
wire [1:0] io_lsu_commit_uops_2_debug_fsrc_0; // @[core.scala:51:7]
wire [1:0] io_lsu_commit_uops_2_debug_tsrc_0; // @[core.scala:51:7]
wire io_lsu_commit_fflags_valid_0; // @[core.scala:51:7]
wire [4:0] io_lsu_commit_fflags_bits_0; // @[core.scala:51:7]
wire [31:0] io_lsu_commit_debug_insts_0_0; // @[core.scala:51:7]
wire [31:0] io_lsu_commit_debug_insts_1_0; // @[core.scala:51:7]
wire [31:0] io_lsu_commit_debug_insts_2_0; // @[core.scala:51:7]
wire io_lsu_commit_rbk_valids_0_0; // @[core.scala:51:7]
wire io_lsu_commit_rbk_valids_1_0; // @[core.scala:51:7]
wire io_lsu_commit_rbk_valids_2_0; // @[core.scala:51:7]
wire [63:0] io_lsu_commit_debug_wdata_0_0; // @[core.scala:51:7]
wire [63:0] io_lsu_commit_debug_wdata_1_0; // @[core.scala:51:7]
wire [63:0] io_lsu_commit_debug_wdata_2_0; // @[core.scala:51:7]
wire io_lsu_commit_rollback_0; // @[core.scala:51:7]
wire [15:0] io_lsu_brupdate_b1_resolve_mask_0; // @[core.scala:51:7]
wire [15:0] io_lsu_brupdate_b1_mispredict_mask_0; // @[core.scala:51:7]
wire [3:0] io_lsu_brupdate_b2_uop_ctrl_br_type_0; // @[core.scala:51:7]
wire [1:0] io_lsu_brupdate_b2_uop_ctrl_op1_sel_0; // @[core.scala:51:7]
wire [2:0] io_lsu_brupdate_b2_uop_ctrl_op2_sel_0; // @[core.scala:51:7]
wire [2:0] io_lsu_brupdate_b2_uop_ctrl_imm_sel_0; // @[core.scala:51:7]
wire [4:0] io_lsu_brupdate_b2_uop_ctrl_op_fcn_0; // @[core.scala:51:7]
wire io_lsu_brupdate_b2_uop_ctrl_fcn_dw_0; // @[core.scala:51:7]
wire [2:0] io_lsu_brupdate_b2_uop_ctrl_csr_cmd_0; // @[core.scala:51:7]
wire io_lsu_brupdate_b2_uop_ctrl_is_load_0; // @[core.scala:51:7]
wire io_lsu_brupdate_b2_uop_ctrl_is_sta_0; // @[core.scala:51:7]
wire io_lsu_brupdate_b2_uop_ctrl_is_std_0; // @[core.scala:51:7]
wire [6:0] io_lsu_brupdate_b2_uop_uopc_0; // @[core.scala:51:7]
wire [31:0] io_lsu_brupdate_b2_uop_inst_0; // @[core.scala:51:7]
wire [31:0] io_lsu_brupdate_b2_uop_debug_inst_0; // @[core.scala:51:7]
wire io_lsu_brupdate_b2_uop_is_rvc_0; // @[core.scala:51:7]
wire [39:0] io_lsu_brupdate_b2_uop_debug_pc_0; // @[core.scala:51:7]
wire [2:0] io_lsu_brupdate_b2_uop_iq_type_0; // @[core.scala:51:7]
wire [9:0] io_lsu_brupdate_b2_uop_fu_code_0; // @[core.scala:51:7]
wire [1:0] io_lsu_brupdate_b2_uop_iw_state_0; // @[core.scala:51:7]
wire io_lsu_brupdate_b2_uop_iw_p1_poisoned_0; // @[core.scala:51:7]
wire io_lsu_brupdate_b2_uop_iw_p2_poisoned_0; // @[core.scala:51:7]
wire io_lsu_brupdate_b2_uop_is_br_0; // @[core.scala:51:7]
wire io_lsu_brupdate_b2_uop_is_jalr_0; // @[core.scala:51:7]
wire io_lsu_brupdate_b2_uop_is_jal_0; // @[core.scala:51:7]
wire io_lsu_brupdate_b2_uop_is_sfb_0; // @[core.scala:51:7]
wire [15:0] io_lsu_brupdate_b2_uop_br_mask_0; // @[core.scala:51:7]
wire [3:0] io_lsu_brupdate_b2_uop_br_tag_0; // @[core.scala:51:7]
wire [4:0] io_lsu_brupdate_b2_uop_ftq_idx_0; // @[core.scala:51:7]
wire io_lsu_brupdate_b2_uop_edge_inst_0; // @[core.scala:51:7]
wire [5:0] io_lsu_brupdate_b2_uop_pc_lob_0; // @[core.scala:51:7]
wire io_lsu_brupdate_b2_uop_taken_0; // @[core.scala:51:7]
wire [19:0] io_lsu_brupdate_b2_uop_imm_packed_0; // @[core.scala:51:7]
wire [11:0] io_lsu_brupdate_b2_uop_csr_addr_0; // @[core.scala:51:7]
wire [6:0] io_lsu_brupdate_b2_uop_rob_idx_0; // @[core.scala:51:7]
wire [4:0] io_lsu_brupdate_b2_uop_ldq_idx_0; // @[core.scala:51:7]
wire [4:0] io_lsu_brupdate_b2_uop_stq_idx_0; // @[core.scala:51:7]
wire [1:0] io_lsu_brupdate_b2_uop_rxq_idx_0; // @[core.scala:51:7]
wire [6:0] io_lsu_brupdate_b2_uop_pdst_0; // @[core.scala:51:7]
wire [6:0] io_lsu_brupdate_b2_uop_prs1_0; // @[core.scala:51:7]
wire [6:0] io_lsu_brupdate_b2_uop_prs2_0; // @[core.scala:51:7]
wire [6:0] io_lsu_brupdate_b2_uop_prs3_0; // @[core.scala:51:7]
wire [4:0] io_lsu_brupdate_b2_uop_ppred_0; // @[core.scala:51:7]
wire io_lsu_brupdate_b2_uop_prs1_busy_0; // @[core.scala:51:7]
wire io_lsu_brupdate_b2_uop_prs2_busy_0; // @[core.scala:51:7]
wire io_lsu_brupdate_b2_uop_prs3_busy_0; // @[core.scala:51:7]
wire io_lsu_brupdate_b2_uop_ppred_busy_0; // @[core.scala:51:7]
wire [6:0] io_lsu_brupdate_b2_uop_stale_pdst_0; // @[core.scala:51:7]
wire io_lsu_brupdate_b2_uop_exception_0; // @[core.scala:51:7]
wire [63:0] io_lsu_brupdate_b2_uop_exc_cause_0; // @[core.scala:51:7]
wire io_lsu_brupdate_b2_uop_bypassable_0; // @[core.scala:51:7]
wire [4:0] io_lsu_brupdate_b2_uop_mem_cmd_0; // @[core.scala:51:7]
wire [1:0] io_lsu_brupdate_b2_uop_mem_size_0; // @[core.scala:51:7]
wire io_lsu_brupdate_b2_uop_mem_signed_0; // @[core.scala:51:7]
wire io_lsu_brupdate_b2_uop_is_fence_0; // @[core.scala:51:7]
wire io_lsu_brupdate_b2_uop_is_fencei_0; // @[core.scala:51:7]
wire io_lsu_brupdate_b2_uop_is_amo_0; // @[core.scala:51:7]
wire io_lsu_brupdate_b2_uop_uses_ldq_0; // @[core.scala:51:7]
wire io_lsu_brupdate_b2_uop_uses_stq_0; // @[core.scala:51:7]
wire io_lsu_brupdate_b2_uop_is_sys_pc2epc_0; // @[core.scala:51:7]
wire io_lsu_brupdate_b2_uop_is_unique_0; // @[core.scala:51:7]
wire io_lsu_brupdate_b2_uop_flush_on_commit_0; // @[core.scala:51:7]
wire io_lsu_brupdate_b2_uop_ldst_is_rs1_0; // @[core.scala:51:7]
wire [5:0] io_lsu_brupdate_b2_uop_ldst_0; // @[core.scala:51:7]
wire [5:0] io_lsu_brupdate_b2_uop_lrs1_0; // @[core.scala:51:7]
wire [5:0] io_lsu_brupdate_b2_uop_lrs2_0; // @[core.scala:51:7]
wire [5:0] io_lsu_brupdate_b2_uop_lrs3_0; // @[core.scala:51:7]
wire io_lsu_brupdate_b2_uop_ldst_val_0; // @[core.scala:51:7]
wire [1:0] io_lsu_brupdate_b2_uop_dst_rtype_0; // @[core.scala:51:7]
wire [1:0] io_lsu_brupdate_b2_uop_lrs1_rtype_0; // @[core.scala:51:7]
wire [1:0] io_lsu_brupdate_b2_uop_lrs2_rtype_0; // @[core.scala:51:7]
wire io_lsu_brupdate_b2_uop_frs3_en_0; // @[core.scala:51:7]
wire io_lsu_brupdate_b2_uop_fp_val_0; // @[core.scala:51:7]
wire io_lsu_brupdate_b2_uop_fp_single_0; // @[core.scala:51:7]
wire io_lsu_brupdate_b2_uop_xcpt_pf_if_0; // @[core.scala:51:7]
wire io_lsu_brupdate_b2_uop_xcpt_ae_if_0; // @[core.scala:51:7]
wire io_lsu_brupdate_b2_uop_xcpt_ma_if_0; // @[core.scala:51:7]
wire io_lsu_brupdate_b2_uop_bp_debug_if_0; // @[core.scala:51:7]
wire io_lsu_brupdate_b2_uop_bp_xcpt_if_0; // @[core.scala:51:7]
wire [1:0] io_lsu_brupdate_b2_uop_debug_fsrc_0; // @[core.scala:51:7]
wire [1:0] io_lsu_brupdate_b2_uop_debug_tsrc_0; // @[core.scala:51:7]
wire io_lsu_brupdate_b2_valid_0; // @[core.scala:51:7]
wire io_lsu_brupdate_b2_mispredict_0; // @[core.scala:51:7]
wire io_lsu_brupdate_b2_taken_0; // @[core.scala:51:7]
wire [2:0] io_lsu_brupdate_b2_cfi_type_0; // @[core.scala:51:7]
wire [1:0] io_lsu_brupdate_b2_pc_sel_0; // @[core.scala:51:7]
wire [39:0] io_lsu_brupdate_b2_jalr_target_0; // @[core.scala:51:7]
wire [20:0] io_lsu_brupdate_b2_target_offset_0; // @[core.scala:51:7]
wire io_lsu_commit_load_at_rob_head_0; // @[core.scala:51:7]
wire io_lsu_fence_dmem_0; // @[core.scala:51:7]
wire [6:0] io_lsu_rob_pnr_idx_0; // @[core.scala:51:7]
wire [6:0] io_lsu_rob_head_idx_0; // @[core.scala:51:7]
wire io_lsu_exception_0; // @[core.scala:51:7]
wire [63:0] io_lsu_tsc_reg_0; // @[core.scala:51:7]
wire io_trace_custom_rob_empty_0; // @[core.scala:51:7]
wire [63:0] io_trace_time_0; // @[core.scala:51:7]
wire [2:0] io_fcsr_rm; // @[core.scala:51:7]
wire _int_iss_wakeups_0_valid_T_2; // @[core.scala:795:52]
wire fast_wakeup_valid; // @[core.scala:814:29]
wire [6:0] fast_wakeup_bits_uop_uopc; // @[core.scala:814:29]
wire [31:0] fast_wakeup_bits_uop_inst; // @[core.scala:814:29]
wire [31:0] fast_wakeup_bits_uop_debug_inst; // @[core.scala:814:29]
wire fast_wakeup_bits_uop_is_rvc; // @[core.scala:814:29]
wire [39:0] fast_wakeup_bits_uop_debug_pc; // @[core.scala:814:29]
wire [2:0] fast_wakeup_bits_uop_iq_type; // @[core.scala:814:29]
wire [9:0] fast_wakeup_bits_uop_fu_code; // @[core.scala:814:29]
wire [3:0] fast_wakeup_bits_uop_ctrl_br_type; // @[core.scala:814:29]
wire [1:0] fast_wakeup_bits_uop_ctrl_op1_sel; // @[core.scala:814:29]
wire [2:0] fast_wakeup_bits_uop_ctrl_op2_sel; // @[core.scala:814:29]
wire [2:0] fast_wakeup_bits_uop_ctrl_imm_sel; // @[core.scala:814:29]
wire [4:0] fast_wakeup_bits_uop_ctrl_op_fcn; // @[core.scala:814:29]
wire fast_wakeup_bits_uop_ctrl_fcn_dw; // @[core.scala:814:29]
wire [2:0] fast_wakeup_bits_uop_ctrl_csr_cmd; // @[core.scala:814:29]
wire fast_wakeup_bits_uop_ctrl_is_load; // @[core.scala:814:29]
wire fast_wakeup_bits_uop_ctrl_is_sta; // @[core.scala:814:29]
wire fast_wakeup_bits_uop_ctrl_is_std; // @[core.scala:814:29]
wire [1:0] fast_wakeup_bits_uop_iw_state; // @[core.scala:814:29]
wire fast_wakeup_bits_uop_iw_p1_poisoned; // @[core.scala:814:29]
wire fast_wakeup_bits_uop_iw_p2_poisoned; // @[core.scala:814:29]
wire fast_wakeup_bits_uop_is_br; // @[core.scala:814:29]
wire fast_wakeup_bits_uop_is_jalr; // @[core.scala:814:29]
wire fast_wakeup_bits_uop_is_jal; // @[core.scala:814:29]
wire fast_wakeup_bits_uop_is_sfb; // @[core.scala:814:29]
wire [15:0] fast_wakeup_bits_uop_br_mask; // @[core.scala:814:29]
wire [3:0] fast_wakeup_bits_uop_br_tag; // @[core.scala:814:29]
wire [4:0] fast_wakeup_bits_uop_ftq_idx; // @[core.scala:814:29]
wire fast_wakeup_bits_uop_edge_inst; // @[core.scala:814:29]
wire [5:0] fast_wakeup_bits_uop_pc_lob; // @[core.scala:814:29]
wire fast_wakeup_bits_uop_taken; // @[core.scala:814:29]
wire [19:0] fast_wakeup_bits_uop_imm_packed; // @[core.scala:814:29]
wire [11:0] fast_wakeup_bits_uop_csr_addr; // @[core.scala:814:29]
wire [6:0] fast_wakeup_bits_uop_rob_idx; // @[core.scala:814:29]
wire [4:0] fast_wakeup_bits_uop_ldq_idx; // @[core.scala:814:29]
wire [4:0] fast_wakeup_bits_uop_stq_idx; // @[core.scala:814:29]
wire [1:0] fast_wakeup_bits_uop_rxq_idx; // @[core.scala:814:29]
wire [6:0] fast_wakeup_bits_uop_pdst; // @[core.scala:814:29]
wire [6:0] fast_wakeup_bits_uop_prs1; // @[core.scala:814:29]
wire [6:0] fast_wakeup_bits_uop_prs2; // @[core.scala:814:29]
wire [6:0] fast_wakeup_bits_uop_prs3; // @[core.scala:814:29]
wire [4:0] fast_wakeup_bits_uop_ppred; // @[core.scala:814:29]
wire fast_wakeup_bits_uop_prs1_busy; // @[core.scala:814:29]
wire fast_wakeup_bits_uop_prs2_busy; // @[core.scala:814:29]
wire fast_wakeup_bits_uop_prs3_busy; // @[core.scala:814:29]
wire fast_wakeup_bits_uop_ppred_busy; // @[core.scala:814:29]
wire [6:0] fast_wakeup_bits_uop_stale_pdst; // @[core.scala:814:29]
wire fast_wakeup_bits_uop_exception; // @[core.scala:814:29]
wire [63:0] fast_wakeup_bits_uop_exc_cause; // @[core.scala:814:29]
wire fast_wakeup_bits_uop_bypassable; // @[core.scala:814:29]
wire [4:0] fast_wakeup_bits_uop_mem_cmd; // @[core.scala:814:29]
wire [1:0] fast_wakeup_bits_uop_mem_size; // @[core.scala:814:29]
wire fast_wakeup_bits_uop_mem_signed; // @[core.scala:814:29]
wire fast_wakeup_bits_uop_is_fence; // @[core.scala:814:29]
wire fast_wakeup_bits_uop_is_fencei; // @[core.scala:814:29]
wire fast_wakeup_bits_uop_is_amo; // @[core.scala:814:29]
wire fast_wakeup_bits_uop_uses_ldq; // @[core.scala:814:29]
wire fast_wakeup_bits_uop_uses_stq; // @[core.scala:814:29]
wire fast_wakeup_bits_uop_is_sys_pc2epc; // @[core.scala:814:29]
wire fast_wakeup_bits_uop_is_unique; // @[core.scala:814:29]
wire fast_wakeup_bits_uop_flush_on_commit; // @[core.scala:814:29]
wire fast_wakeup_bits_uop_ldst_is_rs1; // @[core.scala:814:29]
wire [5:0] fast_wakeup_bits_uop_ldst; // @[core.scala:814:29]
wire [5:0] fast_wakeup_bits_uop_lrs1; // @[core.scala:814:29]
wire [5:0] fast_wakeup_bits_uop_lrs2; // @[core.scala:814:29]
wire [5:0] fast_wakeup_bits_uop_lrs3; // @[core.scala:814:29]
wire fast_wakeup_bits_uop_ldst_val; // @[core.scala:814:29]
wire [1:0] fast_wakeup_bits_uop_dst_rtype; // @[core.scala:814:29]
wire [1:0] fast_wakeup_bits_uop_lrs1_rtype; // @[core.scala:814:29]
wire [1:0] fast_wakeup_bits_uop_lrs2_rtype; // @[core.scala:814:29]
wire fast_wakeup_bits_uop_frs3_en; // @[core.scala:814:29]
wire fast_wakeup_bits_uop_fp_val; // @[core.scala:814:29]
wire fast_wakeup_bits_uop_fp_single; // @[core.scala:814:29]
wire fast_wakeup_bits_uop_xcpt_pf_if; // @[core.scala:814:29]
wire fast_wakeup_bits_uop_xcpt_ae_if; // @[core.scala:814:29]
wire fast_wakeup_bits_uop_xcpt_ma_if; // @[core.scala:814:29]
wire fast_wakeup_bits_uop_bp_debug_if; // @[core.scala:814:29]
wire fast_wakeup_bits_uop_bp_xcpt_if; // @[core.scala:814:29]
wire [1:0] fast_wakeup_bits_uop_debug_fsrc; // @[core.scala:814:29]
wire [1:0] fast_wakeup_bits_uop_debug_tsrc; // @[core.scala:814:29]
wire slow_wakeup_valid; // @[core.scala:815:29]
wire [6:0] slow_wakeup_bits_uop_uopc; // @[core.scala:815:29]
wire [31:0] slow_wakeup_bits_uop_inst; // @[core.scala:815:29]
wire [31:0] slow_wakeup_bits_uop_debug_inst; // @[core.scala:815:29]
wire slow_wakeup_bits_uop_is_rvc; // @[core.scala:815:29]
wire [39:0] slow_wakeup_bits_uop_debug_pc; // @[core.scala:815:29]
wire [2:0] slow_wakeup_bits_uop_iq_type; // @[core.scala:815:29]
wire [9:0] slow_wakeup_bits_uop_fu_code; // @[core.scala:815:29]
wire [3:0] slow_wakeup_bits_uop_ctrl_br_type; // @[core.scala:815:29]
wire [1:0] slow_wakeup_bits_uop_ctrl_op1_sel; // @[core.scala:815:29]
wire [2:0] slow_wakeup_bits_uop_ctrl_op2_sel; // @[core.scala:815:29]
wire [2:0] slow_wakeup_bits_uop_ctrl_imm_sel; // @[core.scala:815:29]
wire [4:0] slow_wakeup_bits_uop_ctrl_op_fcn; // @[core.scala:815:29]
wire slow_wakeup_bits_uop_ctrl_fcn_dw; // @[core.scala:815:29]
wire [2:0] slow_wakeup_bits_uop_ctrl_csr_cmd; // @[core.scala:815:29]
wire slow_wakeup_bits_uop_ctrl_is_load; // @[core.scala:815:29]
wire slow_wakeup_bits_uop_ctrl_is_sta; // @[core.scala:815:29]
wire slow_wakeup_bits_uop_ctrl_is_std; // @[core.scala:815:29]
wire [1:0] slow_wakeup_bits_uop_iw_state; // @[core.scala:815:29]
wire slow_wakeup_bits_uop_iw_p1_poisoned; // @[core.scala:815:29]
wire slow_wakeup_bits_uop_iw_p2_poisoned; // @[core.scala:815:29]
wire slow_wakeup_bits_uop_is_br; // @[core.scala:815:29]
wire slow_wakeup_bits_uop_is_jalr; // @[core.scala:815:29]
wire slow_wakeup_bits_uop_is_jal; // @[core.scala:815:29]
wire slow_wakeup_bits_uop_is_sfb; // @[core.scala:815:29]
wire [15:0] slow_wakeup_bits_uop_br_mask; // @[core.scala:815:29]
wire [3:0] slow_wakeup_bits_uop_br_tag; // @[core.scala:815:29]
wire [4:0] slow_wakeup_bits_uop_ftq_idx; // @[core.scala:815:29]
wire slow_wakeup_bits_uop_edge_inst; // @[core.scala:815:29]
wire [5:0] slow_wakeup_bits_uop_pc_lob; // @[core.scala:815:29]
wire slow_wakeup_bits_uop_taken; // @[core.scala:815:29]
wire [19:0] slow_wakeup_bits_uop_imm_packed; // @[core.scala:815:29]
wire [11:0] slow_wakeup_bits_uop_csr_addr; // @[core.scala:815:29]
wire [6:0] slow_wakeup_bits_uop_rob_idx; // @[core.scala:815:29]
wire [4:0] slow_wakeup_bits_uop_ldq_idx; // @[core.scala:815:29]
wire [4:0] slow_wakeup_bits_uop_stq_idx; // @[core.scala:815:29]
wire [1:0] slow_wakeup_bits_uop_rxq_idx; // @[core.scala:815:29]
wire [6:0] slow_wakeup_bits_uop_pdst; // @[core.scala:815:29]
wire [6:0] slow_wakeup_bits_uop_prs1; // @[core.scala:815:29]
wire [6:0] slow_wakeup_bits_uop_prs2; // @[core.scala:815:29]
wire [6:0] slow_wakeup_bits_uop_prs3; // @[core.scala:815:29]
wire [4:0] slow_wakeup_bits_uop_ppred; // @[core.scala:815:29]
wire slow_wakeup_bits_uop_prs1_busy; // @[core.scala:815:29]
wire slow_wakeup_bits_uop_prs2_busy; // @[core.scala:815:29]
wire slow_wakeup_bits_uop_prs3_busy; // @[core.scala:815:29]
wire slow_wakeup_bits_uop_ppred_busy; // @[core.scala:815:29]
wire [6:0] slow_wakeup_bits_uop_stale_pdst; // @[core.scala:815:29]
wire slow_wakeup_bits_uop_exception; // @[core.scala:815:29]
wire [63:0] slow_wakeup_bits_uop_exc_cause; // @[core.scala:815:29]
wire slow_wakeup_bits_uop_bypassable; // @[core.scala:815:29]
wire [4:0] slow_wakeup_bits_uop_mem_cmd; // @[core.scala:815:29]
wire [1:0] slow_wakeup_bits_uop_mem_size; // @[core.scala:815:29]
wire slow_wakeup_bits_uop_mem_signed; // @[core.scala:815:29]
wire slow_wakeup_bits_uop_is_fence; // @[core.scala:815:29]
wire slow_wakeup_bits_uop_is_fencei; // @[core.scala:815:29]
wire slow_wakeup_bits_uop_is_amo; // @[core.scala:815:29]
wire slow_wakeup_bits_uop_uses_ldq; // @[core.scala:815:29]
wire slow_wakeup_bits_uop_uses_stq; // @[core.scala:815:29]
wire slow_wakeup_bits_uop_is_sys_pc2epc; // @[core.scala:815:29]
wire slow_wakeup_bits_uop_is_unique; // @[core.scala:815:29]
wire slow_wakeup_bits_uop_flush_on_commit; // @[core.scala:815:29]
wire slow_wakeup_bits_uop_ldst_is_rs1; // @[core.scala:815:29]
wire [5:0] slow_wakeup_bits_uop_ldst; // @[core.scala:815:29]
wire [5:0] slow_wakeup_bits_uop_lrs1; // @[core.scala:815:29]
wire [5:0] slow_wakeup_bits_uop_lrs2; // @[core.scala:815:29]
wire [5:0] slow_wakeup_bits_uop_lrs3; // @[core.scala:815:29]
wire slow_wakeup_bits_uop_ldst_val; // @[core.scala:815:29]
wire [1:0] slow_wakeup_bits_uop_dst_rtype; // @[core.scala:815:29]
wire [1:0] slow_wakeup_bits_uop_lrs1_rtype; // @[core.scala:815:29]
wire [1:0] slow_wakeup_bits_uop_lrs2_rtype; // @[core.scala:815:29]
wire slow_wakeup_bits_uop_frs3_en; // @[core.scala:815:29]
wire slow_wakeup_bits_uop_fp_val; // @[core.scala:815:29]
wire slow_wakeup_bits_uop_fp_single; // @[core.scala:815:29]
wire slow_wakeup_bits_uop_xcpt_pf_if; // @[core.scala:815:29]
wire slow_wakeup_bits_uop_xcpt_ae_if; // @[core.scala:815:29]
wire slow_wakeup_bits_uop_xcpt_ma_if; // @[core.scala:815:29]
wire slow_wakeup_bits_uop_bp_debug_if; // @[core.scala:815:29]
wire slow_wakeup_bits_uop_bp_xcpt_if; // @[core.scala:815:29]
wire [1:0] slow_wakeup_bits_uop_debug_fsrc; // @[core.scala:815:29]
wire [1:0] slow_wakeup_bits_uop_debug_tsrc; // @[core.scala:815:29]
wire fast_wakeup_1_valid; // @[core.scala:814:29]
wire [6:0] fast_wakeup_1_bits_uop_uopc; // @[core.scala:814:29]
wire [31:0] fast_wakeup_1_bits_uop_inst; // @[core.scala:814:29]
wire [31:0] fast_wakeup_1_bits_uop_debug_inst; // @[core.scala:814:29]
wire fast_wakeup_1_bits_uop_is_rvc; // @[core.scala:814:29]
wire [39:0] fast_wakeup_1_bits_uop_debug_pc; // @[core.scala:814:29]
wire [2:0] fast_wakeup_1_bits_uop_iq_type; // @[core.scala:814:29]
wire [9:0] fast_wakeup_1_bits_uop_fu_code; // @[core.scala:814:29]
wire [3:0] fast_wakeup_1_bits_uop_ctrl_br_type; // @[core.scala:814:29]
wire [1:0] fast_wakeup_1_bits_uop_ctrl_op1_sel; // @[core.scala:814:29]
wire [2:0] fast_wakeup_1_bits_uop_ctrl_op2_sel; // @[core.scala:814:29]
wire [2:0] fast_wakeup_1_bits_uop_ctrl_imm_sel; // @[core.scala:814:29]
wire [4:0] fast_wakeup_1_bits_uop_ctrl_op_fcn; // @[core.scala:814:29]
wire fast_wakeup_1_bits_uop_ctrl_fcn_dw; // @[core.scala:814:29]
wire [2:0] fast_wakeup_1_bits_uop_ctrl_csr_cmd; // @[core.scala:814:29]
wire fast_wakeup_1_bits_uop_ctrl_is_load; // @[core.scala:814:29]
wire fast_wakeup_1_bits_uop_ctrl_is_sta; // @[core.scala:814:29]
wire fast_wakeup_1_bits_uop_ctrl_is_std; // @[core.scala:814:29]
wire [1:0] fast_wakeup_1_bits_uop_iw_state; // @[core.scala:814:29]
wire fast_wakeup_1_bits_uop_iw_p1_poisoned; // @[core.scala:814:29]
wire fast_wakeup_1_bits_uop_iw_p2_poisoned; // @[core.scala:814:29]
wire fast_wakeup_1_bits_uop_is_br; // @[core.scala:814:29]
wire fast_wakeup_1_bits_uop_is_jalr; // @[core.scala:814:29]
wire fast_wakeup_1_bits_uop_is_jal; // @[core.scala:814:29]
wire fast_wakeup_1_bits_uop_is_sfb; // @[core.scala:814:29]
wire [15:0] fast_wakeup_1_bits_uop_br_mask; // @[core.scala:814:29]
wire [3:0] fast_wakeup_1_bits_uop_br_tag; // @[core.scala:814:29]
wire [4:0] fast_wakeup_1_bits_uop_ftq_idx; // @[core.scala:814:29]
wire fast_wakeup_1_bits_uop_edge_inst; // @[core.scala:814:29]
wire [5:0] fast_wakeup_1_bits_uop_pc_lob; // @[core.scala:814:29]
wire fast_wakeup_1_bits_uop_taken; // @[core.scala:814:29]
wire [19:0] fast_wakeup_1_bits_uop_imm_packed; // @[core.scala:814:29]
wire [11:0] fast_wakeup_1_bits_uop_csr_addr; // @[core.scala:814:29]
wire [6:0] fast_wakeup_1_bits_uop_rob_idx; // @[core.scala:814:29]
wire [4:0] fast_wakeup_1_bits_uop_ldq_idx; // @[core.scala:814:29]
wire [4:0] fast_wakeup_1_bits_uop_stq_idx; // @[core.scala:814:29]
wire [1:0] fast_wakeup_1_bits_uop_rxq_idx; // @[core.scala:814:29]
wire [6:0] fast_wakeup_1_bits_uop_pdst; // @[core.scala:814:29]
wire [6:0] fast_wakeup_1_bits_uop_prs1; // @[core.scala:814:29]
wire [6:0] fast_wakeup_1_bits_uop_prs2; // @[core.scala:814:29]
wire [6:0] fast_wakeup_1_bits_uop_prs3; // @[core.scala:814:29]
wire [4:0] fast_wakeup_1_bits_uop_ppred; // @[core.scala:814:29]
wire fast_wakeup_1_bits_uop_prs1_busy; // @[core.scala:814:29]
wire fast_wakeup_1_bits_uop_prs2_busy; // @[core.scala:814:29]
wire fast_wakeup_1_bits_uop_prs3_busy; // @[core.scala:814:29]
wire fast_wakeup_1_bits_uop_ppred_busy; // @[core.scala:814:29]
wire [6:0] fast_wakeup_1_bits_uop_stale_pdst; // @[core.scala:814:29]
wire fast_wakeup_1_bits_uop_exception; // @[core.scala:814:29]
wire [63:0] fast_wakeup_1_bits_uop_exc_cause; // @[core.scala:814:29]
wire fast_wakeup_1_bits_uop_bypassable; // @[core.scala:814:29]
wire [4:0] fast_wakeup_1_bits_uop_mem_cmd; // @[core.scala:814:29]
wire [1:0] fast_wakeup_1_bits_uop_mem_size; // @[core.scala:814:29]
wire fast_wakeup_1_bits_uop_mem_signed; // @[core.scala:814:29]
wire fast_wakeup_1_bits_uop_is_fence; // @[core.scala:814:29]
wire fast_wakeup_1_bits_uop_is_fencei; // @[core.scala:814:29]
wire fast_wakeup_1_bits_uop_is_amo; // @[core.scala:814:29]
wire fast_wakeup_1_bits_uop_uses_ldq; // @[core.scala:814:29]
wire fast_wakeup_1_bits_uop_uses_stq; // @[core.scala:814:29]
wire fast_wakeup_1_bits_uop_is_sys_pc2epc; // @[core.scala:814:29]
wire fast_wakeup_1_bits_uop_is_unique; // @[core.scala:814:29]
wire fast_wakeup_1_bits_uop_flush_on_commit; // @[core.scala:814:29]
wire fast_wakeup_1_bits_uop_ldst_is_rs1; // @[core.scala:814:29]
wire [5:0] fast_wakeup_1_bits_uop_ldst; // @[core.scala:814:29]
wire [5:0] fast_wakeup_1_bits_uop_lrs1; // @[core.scala:814:29]
wire [5:0] fast_wakeup_1_bits_uop_lrs2; // @[core.scala:814:29]
wire [5:0] fast_wakeup_1_bits_uop_lrs3; // @[core.scala:814:29]
wire fast_wakeup_1_bits_uop_ldst_val; // @[core.scala:814:29]
wire [1:0] fast_wakeup_1_bits_uop_dst_rtype; // @[core.scala:814:29]
wire [1:0] fast_wakeup_1_bits_uop_lrs1_rtype; // @[core.scala:814:29]
wire [1:0] fast_wakeup_1_bits_uop_lrs2_rtype; // @[core.scala:814:29]
wire fast_wakeup_1_bits_uop_frs3_en; // @[core.scala:814:29]
wire fast_wakeup_1_bits_uop_fp_val; // @[core.scala:814:29]
wire fast_wakeup_1_bits_uop_fp_single; // @[core.scala:814:29]
wire fast_wakeup_1_bits_uop_xcpt_pf_if; // @[core.scala:814:29]
wire fast_wakeup_1_bits_uop_xcpt_ae_if; // @[core.scala:814:29]
wire fast_wakeup_1_bits_uop_xcpt_ma_if; // @[core.scala:814:29]
wire fast_wakeup_1_bits_uop_bp_debug_if; // @[core.scala:814:29]
wire fast_wakeup_1_bits_uop_bp_xcpt_if; // @[core.scala:814:29]
wire [1:0] fast_wakeup_1_bits_uop_debug_fsrc; // @[core.scala:814:29]
wire [1:0] fast_wakeup_1_bits_uop_debug_tsrc; // @[core.scala:814:29]
wire slow_wakeup_1_valid; // @[core.scala:815:29]
wire [6:0] slow_wakeup_1_bits_uop_uopc; // @[core.scala:815:29]
wire [31:0] slow_wakeup_1_bits_uop_inst; // @[core.scala:815:29]
wire [31:0] slow_wakeup_1_bits_uop_debug_inst; // @[core.scala:815:29]
wire slow_wakeup_1_bits_uop_is_rvc; // @[core.scala:815:29]
wire [39:0] slow_wakeup_1_bits_uop_debug_pc; // @[core.scala:815:29]
wire [2:0] slow_wakeup_1_bits_uop_iq_type; // @[core.scala:815:29]
wire [9:0] slow_wakeup_1_bits_uop_fu_code; // @[core.scala:815:29]
wire [3:0] slow_wakeup_1_bits_uop_ctrl_br_type; // @[core.scala:815:29]
wire [1:0] slow_wakeup_1_bits_uop_ctrl_op1_sel; // @[core.scala:815:29]
wire [2:0] slow_wakeup_1_bits_uop_ctrl_op2_sel; // @[core.scala:815:29]
wire [2:0] slow_wakeup_1_bits_uop_ctrl_imm_sel; // @[core.scala:815:29]
wire [4:0] slow_wakeup_1_bits_uop_ctrl_op_fcn; // @[core.scala:815:29]
wire slow_wakeup_1_bits_uop_ctrl_fcn_dw; // @[core.scala:815:29]
wire [2:0] slow_wakeup_1_bits_uop_ctrl_csr_cmd; // @[core.scala:815:29]
wire slow_wakeup_1_bits_uop_ctrl_is_load; // @[core.scala:815:29]
wire slow_wakeup_1_bits_uop_ctrl_is_sta; // @[core.scala:815:29]
wire slow_wakeup_1_bits_uop_ctrl_is_std; // @[core.scala:815:29]
wire [1:0] slow_wakeup_1_bits_uop_iw_state; // @[core.scala:815:29]
wire slow_wakeup_1_bits_uop_iw_p1_poisoned; // @[core.scala:815:29]
wire slow_wakeup_1_bits_uop_iw_p2_poisoned; // @[core.scala:815:29]
wire slow_wakeup_1_bits_uop_is_br; // @[core.scala:815:29]
wire slow_wakeup_1_bits_uop_is_jalr; // @[core.scala:815:29]
wire slow_wakeup_1_bits_uop_is_jal; // @[core.scala:815:29]
wire slow_wakeup_1_bits_uop_is_sfb; // @[core.scala:815:29]
wire [15:0] slow_wakeup_1_bits_uop_br_mask; // @[core.scala:815:29]
wire [3:0] slow_wakeup_1_bits_uop_br_tag; // @[core.scala:815:29]
wire [4:0] slow_wakeup_1_bits_uop_ftq_idx; // @[core.scala:815:29]
wire slow_wakeup_1_bits_uop_edge_inst; // @[core.scala:815:29]
wire [5:0] slow_wakeup_1_bits_uop_pc_lob; // @[core.scala:815:29]
wire slow_wakeup_1_bits_uop_taken; // @[core.scala:815:29]
wire [19:0] slow_wakeup_1_bits_uop_imm_packed; // @[core.scala:815:29]
wire [11:0] slow_wakeup_1_bits_uop_csr_addr; // @[core.scala:815:29]
wire [6:0] slow_wakeup_1_bits_uop_rob_idx; // @[core.scala:815:29]
wire [4:0] slow_wakeup_1_bits_uop_ldq_idx; // @[core.scala:815:29]
wire [4:0] slow_wakeup_1_bits_uop_stq_idx; // @[core.scala:815:29]
wire [1:0] slow_wakeup_1_bits_uop_rxq_idx; // @[core.scala:815:29]
wire [6:0] slow_wakeup_1_bits_uop_pdst; // @[core.scala:815:29]
wire [6:0] slow_wakeup_1_bits_uop_prs1; // @[core.scala:815:29]
wire [6:0] slow_wakeup_1_bits_uop_prs2; // @[core.scala:815:29]
wire [6:0] slow_wakeup_1_bits_uop_prs3; // @[core.scala:815:29]
wire [4:0] slow_wakeup_1_bits_uop_ppred; // @[core.scala:815:29]
wire slow_wakeup_1_bits_uop_prs1_busy; // @[core.scala:815:29]
wire slow_wakeup_1_bits_uop_prs2_busy; // @[core.scala:815:29]
wire slow_wakeup_1_bits_uop_prs3_busy; // @[core.scala:815:29]
wire slow_wakeup_1_bits_uop_ppred_busy; // @[core.scala:815:29]
wire [6:0] slow_wakeup_1_bits_uop_stale_pdst; // @[core.scala:815:29]
wire slow_wakeup_1_bits_uop_exception; // @[core.scala:815:29]
wire [63:0] slow_wakeup_1_bits_uop_exc_cause; // @[core.scala:815:29]
wire slow_wakeup_1_bits_uop_bypassable; // @[core.scala:815:29]
wire [4:0] slow_wakeup_1_bits_uop_mem_cmd; // @[core.scala:815:29]
wire [1:0] slow_wakeup_1_bits_uop_mem_size; // @[core.scala:815:29]
wire slow_wakeup_1_bits_uop_mem_signed; // @[core.scala:815:29]
wire slow_wakeup_1_bits_uop_is_fence; // @[core.scala:815:29]
wire slow_wakeup_1_bits_uop_is_fencei; // @[core.scala:815:29]
wire slow_wakeup_1_bits_uop_is_amo; // @[core.scala:815:29]
wire slow_wakeup_1_bits_uop_uses_ldq; // @[core.scala:815:29]
wire slow_wakeup_1_bits_uop_uses_stq; // @[core.scala:815:29]
wire slow_wakeup_1_bits_uop_is_sys_pc2epc; // @[core.scala:815:29]
wire slow_wakeup_1_bits_uop_is_unique; // @[core.scala:815:29]
wire slow_wakeup_1_bits_uop_flush_on_commit; // @[core.scala:815:29]
wire slow_wakeup_1_bits_uop_ldst_is_rs1; // @[core.scala:815:29]
wire [5:0] slow_wakeup_1_bits_uop_ldst; // @[core.scala:815:29]
wire [5:0] slow_wakeup_1_bits_uop_lrs1; // @[core.scala:815:29]
wire [5:0] slow_wakeup_1_bits_uop_lrs2; // @[core.scala:815:29]
wire [5:0] slow_wakeup_1_bits_uop_lrs3; // @[core.scala:815:29]
wire slow_wakeup_1_bits_uop_ldst_val; // @[core.scala:815:29]
wire [1:0] slow_wakeup_1_bits_uop_dst_rtype; // @[core.scala:815:29]
wire [1:0] slow_wakeup_1_bits_uop_lrs1_rtype; // @[core.scala:815:29]
wire [1:0] slow_wakeup_1_bits_uop_lrs2_rtype; // @[core.scala:815:29]
wire slow_wakeup_1_bits_uop_frs3_en; // @[core.scala:815:29]
wire slow_wakeup_1_bits_uop_fp_val; // @[core.scala:815:29]
wire slow_wakeup_1_bits_uop_fp_single; // @[core.scala:815:29]
wire slow_wakeup_1_bits_uop_xcpt_pf_if; // @[core.scala:815:29]
wire slow_wakeup_1_bits_uop_xcpt_ae_if; // @[core.scala:815:29]
wire slow_wakeup_1_bits_uop_xcpt_ma_if; // @[core.scala:815:29]
wire slow_wakeup_1_bits_uop_bp_debug_if; // @[core.scala:815:29]
wire slow_wakeup_1_bits_uop_bp_xcpt_if; // @[core.scala:815:29]
wire [1:0] slow_wakeup_1_bits_uop_debug_fsrc; // @[core.scala:815:29]
wire [1:0] slow_wakeup_1_bits_uop_debug_tsrc; // @[core.scala:815:29]
wire fast_wakeup_2_valid; // @[core.scala:814:29]
wire [6:0] fast_wakeup_2_bits_uop_uopc; // @[core.scala:814:29]
wire [31:0] fast_wakeup_2_bits_uop_inst; // @[core.scala:814:29]
wire [31:0] fast_wakeup_2_bits_uop_debug_inst; // @[core.scala:814:29]
wire fast_wakeup_2_bits_uop_is_rvc; // @[core.scala:814:29]
wire [39:0] fast_wakeup_2_bits_uop_debug_pc; // @[core.scala:814:29]
wire [2:0] fast_wakeup_2_bits_uop_iq_type; // @[core.scala:814:29]
wire [9:0] fast_wakeup_2_bits_uop_fu_code; // @[core.scala:814:29]
wire [3:0] fast_wakeup_2_bits_uop_ctrl_br_type; // @[core.scala:814:29]
wire [1:0] fast_wakeup_2_bits_uop_ctrl_op1_sel; // @[core.scala:814:29]
wire [2:0] fast_wakeup_2_bits_uop_ctrl_op2_sel; // @[core.scala:814:29]
wire [2:0] fast_wakeup_2_bits_uop_ctrl_imm_sel; // @[core.scala:814:29]
wire [4:0] fast_wakeup_2_bits_uop_ctrl_op_fcn; // @[core.scala:814:29]
wire fast_wakeup_2_bits_uop_ctrl_fcn_dw; // @[core.scala:814:29]
wire [2:0] fast_wakeup_2_bits_uop_ctrl_csr_cmd; // @[core.scala:814:29]
wire fast_wakeup_2_bits_uop_ctrl_is_load; // @[core.scala:814:29]
wire fast_wakeup_2_bits_uop_ctrl_is_sta; // @[core.scala:814:29]
wire fast_wakeup_2_bits_uop_ctrl_is_std; // @[core.scala:814:29]
wire [1:0] fast_wakeup_2_bits_uop_iw_state; // @[core.scala:814:29]
wire fast_wakeup_2_bits_uop_iw_p1_poisoned; // @[core.scala:814:29]
wire fast_wakeup_2_bits_uop_iw_p2_poisoned; // @[core.scala:814:29]
wire fast_wakeup_2_bits_uop_is_br; // @[core.scala:814:29]
wire fast_wakeup_2_bits_uop_is_jalr; // @[core.scala:814:29]
wire fast_wakeup_2_bits_uop_is_jal; // @[core.scala:814:29]
wire fast_wakeup_2_bits_uop_is_sfb; // @[core.scala:814:29]
wire [15:0] fast_wakeup_2_bits_uop_br_mask; // @[core.scala:814:29]
wire [3:0] fast_wakeup_2_bits_uop_br_tag; // @[core.scala:814:29]
wire [4:0] fast_wakeup_2_bits_uop_ftq_idx; // @[core.scala:814:29]
wire fast_wakeup_2_bits_uop_edge_inst; // @[core.scala:814:29]
wire [5:0] fast_wakeup_2_bits_uop_pc_lob; // @[core.scala:814:29]
wire fast_wakeup_2_bits_uop_taken; // @[core.scala:814:29]
wire [19:0] fast_wakeup_2_bits_uop_imm_packed; // @[core.scala:814:29]
wire [11:0] fast_wakeup_2_bits_uop_csr_addr; // @[core.scala:814:29]
wire [6:0] fast_wakeup_2_bits_uop_rob_idx; // @[core.scala:814:29]
wire [4:0] fast_wakeup_2_bits_uop_ldq_idx; // @[core.scala:814:29]
wire [4:0] fast_wakeup_2_bits_uop_stq_idx; // @[core.scala:814:29]
wire [1:0] fast_wakeup_2_bits_uop_rxq_idx; // @[core.scala:814:29]
wire [6:0] fast_wakeup_2_bits_uop_pdst; // @[core.scala:814:29]
wire [6:0] fast_wakeup_2_bits_uop_prs1; // @[core.scala:814:29]
wire [6:0] fast_wakeup_2_bits_uop_prs2; // @[core.scala:814:29]
wire [6:0] fast_wakeup_2_bits_uop_prs3; // @[core.scala:814:29]
wire [4:0] fast_wakeup_2_bits_uop_ppred; // @[core.scala:814:29]
wire fast_wakeup_2_bits_uop_prs1_busy; // @[core.scala:814:29]
wire fast_wakeup_2_bits_uop_prs2_busy; // @[core.scala:814:29]
wire fast_wakeup_2_bits_uop_prs3_busy; // @[core.scala:814:29]
wire fast_wakeup_2_bits_uop_ppred_busy; // @[core.scala:814:29]
wire [6:0] fast_wakeup_2_bits_uop_stale_pdst; // @[core.scala:814:29]
wire fast_wakeup_2_bits_uop_exception; // @[core.scala:814:29]
wire [63:0] fast_wakeup_2_bits_uop_exc_cause; // @[core.scala:814:29]
wire fast_wakeup_2_bits_uop_bypassable; // @[core.scala:814:29]
wire [4:0] fast_wakeup_2_bits_uop_mem_cmd; // @[core.scala:814:29]
wire [1:0] fast_wakeup_2_bits_uop_mem_size; // @[core.scala:814:29]
wire fast_wakeup_2_bits_uop_mem_signed; // @[core.scala:814:29]
wire fast_wakeup_2_bits_uop_is_fence; // @[core.scala:814:29]
wire fast_wakeup_2_bits_uop_is_fencei; // @[core.scala:814:29]
wire fast_wakeup_2_bits_uop_is_amo; // @[core.scala:814:29]
wire fast_wakeup_2_bits_uop_uses_ldq; // @[core.scala:814:29]
wire fast_wakeup_2_bits_uop_uses_stq; // @[core.scala:814:29]
wire fast_wakeup_2_bits_uop_is_sys_pc2epc; // @[core.scala:814:29]
wire fast_wakeup_2_bits_uop_is_unique; // @[core.scala:814:29]
wire fast_wakeup_2_bits_uop_flush_on_commit; // @[core.scala:814:29]
wire fast_wakeup_2_bits_uop_ldst_is_rs1; // @[core.scala:814:29]
wire [5:0] fast_wakeup_2_bits_uop_ldst; // @[core.scala:814:29]
wire [5:0] fast_wakeup_2_bits_uop_lrs1; // @[core.scala:814:29]
wire [5:0] fast_wakeup_2_bits_uop_lrs2; // @[core.scala:814:29]
wire [5:0] fast_wakeup_2_bits_uop_lrs3; // @[core.scala:814:29]
wire fast_wakeup_2_bits_uop_ldst_val; // @[core.scala:814:29]
wire [1:0] fast_wakeup_2_bits_uop_dst_rtype; // @[core.scala:814:29]
wire [1:0] fast_wakeup_2_bits_uop_lrs1_rtype; // @[core.scala:814:29]
wire [1:0] fast_wakeup_2_bits_uop_lrs2_rtype; // @[core.scala:814:29]
wire fast_wakeup_2_bits_uop_frs3_en; // @[core.scala:814:29]
wire fast_wakeup_2_bits_uop_fp_val; // @[core.scala:814:29]
wire fast_wakeup_2_bits_uop_fp_single; // @[core.scala:814:29]
wire fast_wakeup_2_bits_uop_xcpt_pf_if; // @[core.scala:814:29]
wire fast_wakeup_2_bits_uop_xcpt_ae_if; // @[core.scala:814:29]
wire fast_wakeup_2_bits_uop_xcpt_ma_if; // @[core.scala:814:29]
wire fast_wakeup_2_bits_uop_bp_debug_if; // @[core.scala:814:29]
wire fast_wakeup_2_bits_uop_bp_xcpt_if; // @[core.scala:814:29]
wire [1:0] fast_wakeup_2_bits_uop_debug_fsrc; // @[core.scala:814:29]
wire [1:0] fast_wakeup_2_bits_uop_debug_tsrc; // @[core.scala:814:29]
wire slow_wakeup_2_valid; // @[core.scala:815:29]
wire [6:0] slow_wakeup_2_bits_uop_uopc; // @[core.scala:815:29]
wire [31:0] slow_wakeup_2_bits_uop_inst; // @[core.scala:815:29]
wire [31:0] slow_wakeup_2_bits_uop_debug_inst; // @[core.scala:815:29]
wire slow_wakeup_2_bits_uop_is_rvc; // @[core.scala:815:29]
wire [39:0] slow_wakeup_2_bits_uop_debug_pc; // @[core.scala:815:29]
wire [2:0] slow_wakeup_2_bits_uop_iq_type; // @[core.scala:815:29]
wire [9:0] slow_wakeup_2_bits_uop_fu_code; // @[core.scala:815:29]
wire [3:0] slow_wakeup_2_bits_uop_ctrl_br_type; // @[core.scala:815:29]
wire [1:0] slow_wakeup_2_bits_uop_ctrl_op1_sel; // @[core.scala:815:29]
wire [2:0] slow_wakeup_2_bits_uop_ctrl_op2_sel; // @[core.scala:815:29]
wire [2:0] slow_wakeup_2_bits_uop_ctrl_imm_sel; // @[core.scala:815:29]
wire [4:0] slow_wakeup_2_bits_uop_ctrl_op_fcn; // @[core.scala:815:29]
wire slow_wakeup_2_bits_uop_ctrl_fcn_dw; // @[core.scala:815:29]
wire [2:0] slow_wakeup_2_bits_uop_ctrl_csr_cmd; // @[core.scala:815:29]
wire slow_wakeup_2_bits_uop_ctrl_is_load; // @[core.scala:815:29]
wire slow_wakeup_2_bits_uop_ctrl_is_sta; // @[core.scala:815:29]
wire slow_wakeup_2_bits_uop_ctrl_is_std; // @[core.scala:815:29]
wire [1:0] slow_wakeup_2_bits_uop_iw_state; // @[core.scala:815:29]
wire slow_wakeup_2_bits_uop_iw_p1_poisoned; // @[core.scala:815:29]
wire slow_wakeup_2_bits_uop_iw_p2_poisoned; // @[core.scala:815:29]
wire slow_wakeup_2_bits_uop_is_br; // @[core.scala:815:29]
wire slow_wakeup_2_bits_uop_is_jalr; // @[core.scala:815:29]
wire slow_wakeup_2_bits_uop_is_jal; // @[core.scala:815:29]
wire slow_wakeup_2_bits_uop_is_sfb; // @[core.scala:815:29]
wire [15:0] slow_wakeup_2_bits_uop_br_mask; // @[core.scala:815:29]
wire [3:0] slow_wakeup_2_bits_uop_br_tag; // @[core.scala:815:29]
wire [4:0] slow_wakeup_2_bits_uop_ftq_idx; // @[core.scala:815:29]
wire slow_wakeup_2_bits_uop_edge_inst; // @[core.scala:815:29]
wire [5:0] slow_wakeup_2_bits_uop_pc_lob; // @[core.scala:815:29]
wire slow_wakeup_2_bits_uop_taken; // @[core.scala:815:29]
wire [19:0] slow_wakeup_2_bits_uop_imm_packed; // @[core.scala:815:29]
wire [11:0] slow_wakeup_2_bits_uop_csr_addr; // @[core.scala:815:29]
wire [6:0] slow_wakeup_2_bits_uop_rob_idx; // @[core.scala:815:29]
wire [4:0] slow_wakeup_2_bits_uop_ldq_idx; // @[core.scala:815:29]
wire [4:0] slow_wakeup_2_bits_uop_stq_idx; // @[core.scala:815:29]
wire [1:0] slow_wakeup_2_bits_uop_rxq_idx; // @[core.scala:815:29]
wire [6:0] slow_wakeup_2_bits_uop_pdst; // @[core.scala:815:29]
wire [6:0] slow_wakeup_2_bits_uop_prs1; // @[core.scala:815:29]
wire [6:0] slow_wakeup_2_bits_uop_prs2; // @[core.scala:815:29]
wire [6:0] slow_wakeup_2_bits_uop_prs3; // @[core.scala:815:29]
wire [4:0] slow_wakeup_2_bits_uop_ppred; // @[core.scala:815:29]
wire slow_wakeup_2_bits_uop_prs1_busy; // @[core.scala:815:29]
wire slow_wakeup_2_bits_uop_prs2_busy; // @[core.scala:815:29]
wire slow_wakeup_2_bits_uop_prs3_busy; // @[core.scala:815:29]
wire slow_wakeup_2_bits_uop_ppred_busy; // @[core.scala:815:29]
wire [6:0] slow_wakeup_2_bits_uop_stale_pdst; // @[core.scala:815:29]
wire slow_wakeup_2_bits_uop_exception; // @[core.scala:815:29]
wire [63:0] slow_wakeup_2_bits_uop_exc_cause; // @[core.scala:815:29]
wire slow_wakeup_2_bits_uop_bypassable; // @[core.scala:815:29]
wire [4:0] slow_wakeup_2_bits_uop_mem_cmd; // @[core.scala:815:29]
wire [1:0] slow_wakeup_2_bits_uop_mem_size; // @[core.scala:815:29]
wire slow_wakeup_2_bits_uop_mem_signed; // @[core.scala:815:29]
wire slow_wakeup_2_bits_uop_is_fence; // @[core.scala:815:29]
wire slow_wakeup_2_bits_uop_is_fencei; // @[core.scala:815:29]
wire slow_wakeup_2_bits_uop_is_amo; // @[core.scala:815:29]
wire slow_wakeup_2_bits_uop_uses_ldq; // @[core.scala:815:29]
wire slow_wakeup_2_bits_uop_uses_stq; // @[core.scala:815:29]
wire slow_wakeup_2_bits_uop_is_sys_pc2epc; // @[core.scala:815:29]
wire slow_wakeup_2_bits_uop_is_unique; // @[core.scala:815:29]
wire slow_wakeup_2_bits_uop_flush_on_commit; // @[core.scala:815:29]
wire slow_wakeup_2_bits_uop_ldst_is_rs1; // @[core.scala:815:29]
wire [5:0] slow_wakeup_2_bits_uop_ldst; // @[core.scala:815:29]
wire [5:0] slow_wakeup_2_bits_uop_lrs1; // @[core.scala:815:29]
wire [5:0] slow_wakeup_2_bits_uop_lrs2; // @[core.scala:815:29]
wire [5:0] slow_wakeup_2_bits_uop_lrs3; // @[core.scala:815:29]
wire slow_wakeup_2_bits_uop_ldst_val; // @[core.scala:815:29]
wire [1:0] slow_wakeup_2_bits_uop_dst_rtype; // @[core.scala:815:29]
wire [1:0] slow_wakeup_2_bits_uop_lrs1_rtype; // @[core.scala:815:29]
wire [1:0] slow_wakeup_2_bits_uop_lrs2_rtype; // @[core.scala:815:29]
wire slow_wakeup_2_bits_uop_frs3_en; // @[core.scala:815:29]
wire slow_wakeup_2_bits_uop_fp_val; // @[core.scala:815:29]
wire slow_wakeup_2_bits_uop_fp_single; // @[core.scala:815:29]
wire slow_wakeup_2_bits_uop_xcpt_pf_if; // @[core.scala:815:29]
wire slow_wakeup_2_bits_uop_xcpt_ae_if; // @[core.scala:815:29]
wire slow_wakeup_2_bits_uop_xcpt_ma_if; // @[core.scala:815:29]
wire slow_wakeup_2_bits_uop_bp_debug_if; // @[core.scala:815:29]
wire slow_wakeup_2_bits_uop_bp_xcpt_if; // @[core.scala:815:29]
wire [1:0] slow_wakeup_2_bits_uop_debug_fsrc; // @[core.scala:815:29]
wire [1:0] slow_wakeup_2_bits_uop_debug_tsrc; // @[core.scala:815:29]
wire [3:0] int_iss_wakeups_0_bits_uop_ctrl_br_type; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_0_bits_uop_ctrl_op1_sel; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_0_bits_uop_ctrl_op2_sel; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_0_bits_uop_ctrl_imm_sel; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_0_bits_uop_ctrl_op_fcn; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_uop_ctrl_fcn_dw; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_0_bits_uop_ctrl_csr_cmd; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_uop_ctrl_is_load; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_uop_ctrl_is_sta; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_uop_ctrl_is_std; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_0_bits_uop_uopc; // @[core.scala:147:30]
wire [31:0] int_iss_wakeups_0_bits_uop_inst; // @[core.scala:147:30]
wire [31:0] int_iss_wakeups_0_bits_uop_debug_inst; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_uop_is_rvc; // @[core.scala:147:30]
wire [39:0] int_iss_wakeups_0_bits_uop_debug_pc; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_0_bits_uop_iq_type; // @[core.scala:147:30]
wire [9:0] int_iss_wakeups_0_bits_uop_fu_code; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_0_bits_uop_iw_state; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_uop_iw_p1_poisoned; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_uop_iw_p2_poisoned; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_uop_is_br; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_uop_is_jalr; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_uop_is_jal; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_uop_is_sfb; // @[core.scala:147:30]
wire [15:0] int_iss_wakeups_0_bits_uop_br_mask; // @[core.scala:147:30]
wire [3:0] int_iss_wakeups_0_bits_uop_br_tag; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_0_bits_uop_ftq_idx; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_uop_edge_inst; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_0_bits_uop_pc_lob; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_uop_taken; // @[core.scala:147:30]
wire [19:0] int_iss_wakeups_0_bits_uop_imm_packed; // @[core.scala:147:30]
wire [11:0] int_iss_wakeups_0_bits_uop_csr_addr; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_0_bits_uop_rob_idx; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_0_bits_uop_ldq_idx; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_0_bits_uop_stq_idx; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_0_bits_uop_rxq_idx; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_0_bits_uop_pdst; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_0_bits_uop_prs1; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_0_bits_uop_prs2; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_0_bits_uop_prs3; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_0_bits_uop_ppred; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_uop_prs1_busy; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_uop_prs2_busy; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_uop_prs3_busy; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_uop_ppred_busy; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_0_bits_uop_stale_pdst; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_uop_exception; // @[core.scala:147:30]
wire [63:0] int_iss_wakeups_0_bits_uop_exc_cause; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_uop_bypassable; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_0_bits_uop_mem_cmd; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_0_bits_uop_mem_size; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_uop_mem_signed; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_uop_is_fence; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_uop_is_fencei; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_uop_is_amo; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_uop_uses_ldq; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_uop_uses_stq; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_uop_is_sys_pc2epc; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_uop_is_unique; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_uop_flush_on_commit; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_uop_ldst_is_rs1; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_0_bits_uop_ldst; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_0_bits_uop_lrs1; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_0_bits_uop_lrs2; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_0_bits_uop_lrs3; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_uop_ldst_val; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_0_bits_uop_dst_rtype; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_0_bits_uop_lrs1_rtype; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_0_bits_uop_lrs2_rtype; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_uop_frs3_en; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_uop_fp_val; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_uop_fp_single; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_uop_xcpt_pf_if; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_uop_xcpt_ae_if; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_uop_xcpt_ma_if; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_uop_bp_debug_if; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_uop_bp_xcpt_if; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_0_bits_uop_debug_fsrc; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_0_bits_uop_debug_tsrc; // @[core.scala:147:30]
wire [3:0] int_iss_wakeups_0_bits_fflags_bits_uop_ctrl_br_type; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_0_bits_fflags_bits_uop_ctrl_op1_sel; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_0_bits_fflags_bits_uop_ctrl_op2_sel; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_0_bits_fflags_bits_uop_ctrl_imm_sel; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_0_bits_fflags_bits_uop_ctrl_op_fcn; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_fflags_bits_uop_ctrl_fcn_dw; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_0_bits_fflags_bits_uop_ctrl_csr_cmd; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_fflags_bits_uop_ctrl_is_load; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_fflags_bits_uop_ctrl_is_sta; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_fflags_bits_uop_ctrl_is_std; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_0_bits_fflags_bits_uop_uopc; // @[core.scala:147:30]
wire [31:0] int_iss_wakeups_0_bits_fflags_bits_uop_inst; // @[core.scala:147:30]
wire [31:0] int_iss_wakeups_0_bits_fflags_bits_uop_debug_inst; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_fflags_bits_uop_is_rvc; // @[core.scala:147:30]
wire [39:0] int_iss_wakeups_0_bits_fflags_bits_uop_debug_pc; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_0_bits_fflags_bits_uop_iq_type; // @[core.scala:147:30]
wire [9:0] int_iss_wakeups_0_bits_fflags_bits_uop_fu_code; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_0_bits_fflags_bits_uop_iw_state; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_fflags_bits_uop_iw_p1_poisoned; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_fflags_bits_uop_iw_p2_poisoned; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_fflags_bits_uop_is_br; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_fflags_bits_uop_is_jalr; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_fflags_bits_uop_is_jal; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_fflags_bits_uop_is_sfb; // @[core.scala:147:30]
wire [15:0] int_iss_wakeups_0_bits_fflags_bits_uop_br_mask; // @[core.scala:147:30]
wire [3:0] int_iss_wakeups_0_bits_fflags_bits_uop_br_tag; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_0_bits_fflags_bits_uop_ftq_idx; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_fflags_bits_uop_edge_inst; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_0_bits_fflags_bits_uop_pc_lob; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_fflags_bits_uop_taken; // @[core.scala:147:30]
wire [19:0] int_iss_wakeups_0_bits_fflags_bits_uop_imm_packed; // @[core.scala:147:30]
wire [11:0] int_iss_wakeups_0_bits_fflags_bits_uop_csr_addr; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_0_bits_fflags_bits_uop_rob_idx; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_0_bits_fflags_bits_uop_ldq_idx; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_0_bits_fflags_bits_uop_stq_idx; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_0_bits_fflags_bits_uop_rxq_idx; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_0_bits_fflags_bits_uop_pdst; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_0_bits_fflags_bits_uop_prs1; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_0_bits_fflags_bits_uop_prs2; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_0_bits_fflags_bits_uop_prs3; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_0_bits_fflags_bits_uop_ppred; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_fflags_bits_uop_prs1_busy; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_fflags_bits_uop_prs2_busy; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_fflags_bits_uop_prs3_busy; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_fflags_bits_uop_ppred_busy; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_0_bits_fflags_bits_uop_stale_pdst; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_fflags_bits_uop_exception; // @[core.scala:147:30]
wire [63:0] int_iss_wakeups_0_bits_fflags_bits_uop_exc_cause; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_fflags_bits_uop_bypassable; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_0_bits_fflags_bits_uop_mem_cmd; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_0_bits_fflags_bits_uop_mem_size; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_fflags_bits_uop_mem_signed; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_fflags_bits_uop_is_fence; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_fflags_bits_uop_is_fencei; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_fflags_bits_uop_is_amo; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_fflags_bits_uop_uses_ldq; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_fflags_bits_uop_uses_stq; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_fflags_bits_uop_is_sys_pc2epc; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_fflags_bits_uop_is_unique; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_fflags_bits_uop_flush_on_commit; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_fflags_bits_uop_ldst_is_rs1; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_0_bits_fflags_bits_uop_ldst; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_0_bits_fflags_bits_uop_lrs1; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_0_bits_fflags_bits_uop_lrs2; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_0_bits_fflags_bits_uop_lrs3; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_fflags_bits_uop_ldst_val; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_0_bits_fflags_bits_uop_dst_rtype; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_0_bits_fflags_bits_uop_lrs1_rtype; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_0_bits_fflags_bits_uop_lrs2_rtype; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_fflags_bits_uop_frs3_en; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_fflags_bits_uop_fp_val; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_fflags_bits_uop_fp_single; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_fflags_bits_uop_xcpt_pf_if; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_fflags_bits_uop_xcpt_ae_if; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_fflags_bits_uop_xcpt_ma_if; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_fflags_bits_uop_bp_debug_if; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_fflags_bits_uop_bp_xcpt_if; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_0_bits_fflags_bits_uop_debug_fsrc; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_0_bits_fflags_bits_uop_debug_tsrc; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_0_bits_fflags_bits_flags; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_fflags_valid; // @[core.scala:147:30]
wire [63:0] int_iss_wakeups_0_bits_data; // @[core.scala:147:30]
wire int_iss_wakeups_0_bits_predicated; // @[core.scala:147:30]
wire int_iss_wakeups_0_valid; // @[core.scala:147:30]
wire [3:0] int_iss_wakeups_1_bits_uop_ctrl_br_type; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_1_bits_uop_ctrl_op1_sel; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_1_bits_uop_ctrl_op2_sel; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_1_bits_uop_ctrl_imm_sel; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_1_bits_uop_ctrl_op_fcn; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_uop_ctrl_fcn_dw; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_1_bits_uop_ctrl_csr_cmd; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_uop_ctrl_is_load; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_uop_ctrl_is_sta; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_uop_ctrl_is_std; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_1_bits_uop_uopc; // @[core.scala:147:30]
wire [31:0] int_iss_wakeups_1_bits_uop_inst; // @[core.scala:147:30]
wire [31:0] int_iss_wakeups_1_bits_uop_debug_inst; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_uop_is_rvc; // @[core.scala:147:30]
wire [39:0] int_iss_wakeups_1_bits_uop_debug_pc; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_1_bits_uop_iq_type; // @[core.scala:147:30]
wire [9:0] int_iss_wakeups_1_bits_uop_fu_code; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_1_bits_uop_iw_state; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_uop_iw_p1_poisoned; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_uop_iw_p2_poisoned; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_uop_is_br; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_uop_is_jalr; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_uop_is_jal; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_uop_is_sfb; // @[core.scala:147:30]
wire [15:0] int_iss_wakeups_1_bits_uop_br_mask; // @[core.scala:147:30]
wire [3:0] int_iss_wakeups_1_bits_uop_br_tag; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_1_bits_uop_ftq_idx; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_uop_edge_inst; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_1_bits_uop_pc_lob; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_uop_taken; // @[core.scala:147:30]
wire [19:0] int_iss_wakeups_1_bits_uop_imm_packed; // @[core.scala:147:30]
wire [11:0] int_iss_wakeups_1_bits_uop_csr_addr; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_1_bits_uop_rob_idx; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_1_bits_uop_ldq_idx; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_1_bits_uop_stq_idx; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_1_bits_uop_rxq_idx; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_1_bits_uop_pdst; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_1_bits_uop_prs1; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_1_bits_uop_prs2; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_1_bits_uop_prs3; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_1_bits_uop_ppred; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_uop_prs1_busy; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_uop_prs2_busy; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_uop_prs3_busy; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_uop_ppred_busy; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_1_bits_uop_stale_pdst; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_uop_exception; // @[core.scala:147:30]
wire [63:0] int_iss_wakeups_1_bits_uop_exc_cause; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_uop_bypassable; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_1_bits_uop_mem_cmd; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_1_bits_uop_mem_size; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_uop_mem_signed; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_uop_is_fence; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_uop_is_fencei; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_uop_is_amo; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_uop_uses_ldq; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_uop_uses_stq; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_uop_is_sys_pc2epc; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_uop_is_unique; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_uop_flush_on_commit; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_uop_ldst_is_rs1; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_1_bits_uop_ldst; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_1_bits_uop_lrs1; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_1_bits_uop_lrs2; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_1_bits_uop_lrs3; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_uop_ldst_val; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_1_bits_uop_dst_rtype; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_1_bits_uop_lrs1_rtype; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_1_bits_uop_lrs2_rtype; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_uop_frs3_en; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_uop_fp_val; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_uop_fp_single; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_uop_xcpt_pf_if; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_uop_xcpt_ae_if; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_uop_xcpt_ma_if; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_uop_bp_debug_if; // @[core.scala:147:30]
wire int_iss_wakeups_1_bits_uop_bp_xcpt_if; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_1_bits_uop_debug_fsrc; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_1_bits_uop_debug_tsrc; // @[core.scala:147:30]
wire int_iss_wakeups_1_valid; // @[core.scala:147:30]
wire [3:0] int_iss_wakeups_2_bits_uop_ctrl_br_type; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_2_bits_uop_ctrl_op1_sel; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_2_bits_uop_ctrl_op2_sel; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_2_bits_uop_ctrl_imm_sel; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_2_bits_uop_ctrl_op_fcn; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_uop_ctrl_fcn_dw; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_2_bits_uop_ctrl_csr_cmd; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_uop_ctrl_is_load; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_uop_ctrl_is_sta; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_uop_ctrl_is_std; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_2_bits_uop_uopc; // @[core.scala:147:30]
wire [31:0] int_iss_wakeups_2_bits_uop_inst; // @[core.scala:147:30]
wire [31:0] int_iss_wakeups_2_bits_uop_debug_inst; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_uop_is_rvc; // @[core.scala:147:30]
wire [39:0] int_iss_wakeups_2_bits_uop_debug_pc; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_2_bits_uop_iq_type; // @[core.scala:147:30]
wire [9:0] int_iss_wakeups_2_bits_uop_fu_code; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_2_bits_uop_iw_state; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_uop_iw_p1_poisoned; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_uop_iw_p2_poisoned; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_uop_is_br; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_uop_is_jalr; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_uop_is_jal; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_uop_is_sfb; // @[core.scala:147:30]
wire [15:0] int_iss_wakeups_2_bits_uop_br_mask; // @[core.scala:147:30]
wire [3:0] int_iss_wakeups_2_bits_uop_br_tag; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_2_bits_uop_ftq_idx; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_uop_edge_inst; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_2_bits_uop_pc_lob; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_uop_taken; // @[core.scala:147:30]
wire [19:0] int_iss_wakeups_2_bits_uop_imm_packed; // @[core.scala:147:30]
wire [11:0] int_iss_wakeups_2_bits_uop_csr_addr; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_2_bits_uop_rob_idx; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_2_bits_uop_ldq_idx; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_2_bits_uop_stq_idx; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_2_bits_uop_rxq_idx; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_2_bits_uop_pdst; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_2_bits_uop_prs1; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_2_bits_uop_prs2; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_2_bits_uop_prs3; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_2_bits_uop_ppred; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_uop_prs1_busy; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_uop_prs2_busy; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_uop_prs3_busy; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_uop_ppred_busy; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_2_bits_uop_stale_pdst; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_uop_exception; // @[core.scala:147:30]
wire [63:0] int_iss_wakeups_2_bits_uop_exc_cause; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_uop_bypassable; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_2_bits_uop_mem_cmd; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_2_bits_uop_mem_size; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_uop_mem_signed; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_uop_is_fence; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_uop_is_fencei; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_uop_is_amo; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_uop_uses_ldq; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_uop_uses_stq; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_uop_is_sys_pc2epc; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_uop_is_unique; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_uop_flush_on_commit; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_uop_ldst_is_rs1; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_2_bits_uop_ldst; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_2_bits_uop_lrs1; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_2_bits_uop_lrs2; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_2_bits_uop_lrs3; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_uop_ldst_val; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_2_bits_uop_dst_rtype; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_2_bits_uop_lrs1_rtype; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_2_bits_uop_lrs2_rtype; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_uop_frs3_en; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_uop_fp_val; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_uop_fp_single; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_uop_xcpt_pf_if; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_uop_xcpt_ae_if; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_uop_xcpt_ma_if; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_uop_bp_debug_if; // @[core.scala:147:30]
wire int_iss_wakeups_2_bits_uop_bp_xcpt_if; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_2_bits_uop_debug_fsrc; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_2_bits_uop_debug_tsrc; // @[core.scala:147:30]
wire int_iss_wakeups_2_valid; // @[core.scala:147:30]
wire [3:0] int_iss_wakeups_3_bits_uop_ctrl_br_type; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_3_bits_uop_ctrl_op1_sel; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_3_bits_uop_ctrl_op2_sel; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_3_bits_uop_ctrl_imm_sel; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_3_bits_uop_ctrl_op_fcn; // @[core.scala:147:30]
wire int_iss_wakeups_3_bits_uop_ctrl_fcn_dw; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_3_bits_uop_ctrl_csr_cmd; // @[core.scala:147:30]
wire int_iss_wakeups_3_bits_uop_ctrl_is_load; // @[core.scala:147:30]
wire int_iss_wakeups_3_bits_uop_ctrl_is_sta; // @[core.scala:147:30]
wire int_iss_wakeups_3_bits_uop_ctrl_is_std; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_3_bits_uop_uopc; // @[core.scala:147:30]
wire [31:0] int_iss_wakeups_3_bits_uop_inst; // @[core.scala:147:30]
wire [31:0] int_iss_wakeups_3_bits_uop_debug_inst; // @[core.scala:147:30]
wire int_iss_wakeups_3_bits_uop_is_rvc; // @[core.scala:147:30]
wire [39:0] int_iss_wakeups_3_bits_uop_debug_pc; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_3_bits_uop_iq_type; // @[core.scala:147:30]
wire [9:0] int_iss_wakeups_3_bits_uop_fu_code; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_3_bits_uop_iw_state; // @[core.scala:147:30]
wire int_iss_wakeups_3_bits_uop_iw_p1_poisoned; // @[core.scala:147:30]
wire int_iss_wakeups_3_bits_uop_iw_p2_poisoned; // @[core.scala:147:30]
wire int_iss_wakeups_3_bits_uop_is_br; // @[core.scala:147:30]
wire int_iss_wakeups_3_bits_uop_is_jalr; // @[core.scala:147:30]
wire int_iss_wakeups_3_bits_uop_is_jal; // @[core.scala:147:30]
wire int_iss_wakeups_3_bits_uop_is_sfb; // @[core.scala:147:30]
wire [15:0] int_iss_wakeups_3_bits_uop_br_mask; // @[core.scala:147:30]
wire [3:0] int_iss_wakeups_3_bits_uop_br_tag; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_3_bits_uop_ftq_idx; // @[core.scala:147:30]
wire int_iss_wakeups_3_bits_uop_edge_inst; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_3_bits_uop_pc_lob; // @[core.scala:147:30]
wire int_iss_wakeups_3_bits_uop_taken; // @[core.scala:147:30]
wire [19:0] int_iss_wakeups_3_bits_uop_imm_packed; // @[core.scala:147:30]
wire [11:0] int_iss_wakeups_3_bits_uop_csr_addr; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_3_bits_uop_rob_idx; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_3_bits_uop_ldq_idx; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_3_bits_uop_stq_idx; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_3_bits_uop_rxq_idx; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_3_bits_uop_pdst; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_3_bits_uop_prs1; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_3_bits_uop_prs2; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_3_bits_uop_prs3; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_3_bits_uop_ppred; // @[core.scala:147:30]
wire int_iss_wakeups_3_bits_uop_prs1_busy; // @[core.scala:147:30]
wire int_iss_wakeups_3_bits_uop_prs2_busy; // @[core.scala:147:30]
wire int_iss_wakeups_3_bits_uop_prs3_busy; // @[core.scala:147:30]
wire int_iss_wakeups_3_bits_uop_ppred_busy; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_3_bits_uop_stale_pdst; // @[core.scala:147:30]
wire int_iss_wakeups_3_bits_uop_exception; // @[core.scala:147:30]
wire [63:0] int_iss_wakeups_3_bits_uop_exc_cause; // @[core.scala:147:30]
wire int_iss_wakeups_3_bits_uop_bypassable; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_3_bits_uop_mem_cmd; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_3_bits_uop_mem_size; // @[core.scala:147:30]
wire int_iss_wakeups_3_bits_uop_mem_signed; // @[core.scala:147:30]
wire int_iss_wakeups_3_bits_uop_is_fence; // @[core.scala:147:30]
wire int_iss_wakeups_3_bits_uop_is_fencei; // @[core.scala:147:30]
wire int_iss_wakeups_3_bits_uop_is_amo; // @[core.scala:147:30]
wire int_iss_wakeups_3_bits_uop_uses_ldq; // @[core.scala:147:30]
wire int_iss_wakeups_3_bits_uop_uses_stq; // @[core.scala:147:30]
wire int_iss_wakeups_3_bits_uop_is_sys_pc2epc; // @[core.scala:147:30]
wire int_iss_wakeups_3_bits_uop_is_unique; // @[core.scala:147:30]
wire int_iss_wakeups_3_bits_uop_flush_on_commit; // @[core.scala:147:30]
wire int_iss_wakeups_3_bits_uop_ldst_is_rs1; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_3_bits_uop_ldst; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_3_bits_uop_lrs1; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_3_bits_uop_lrs2; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_3_bits_uop_lrs3; // @[core.scala:147:30]
wire int_iss_wakeups_3_bits_uop_ldst_val; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_3_bits_uop_dst_rtype; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_3_bits_uop_lrs1_rtype; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_3_bits_uop_lrs2_rtype; // @[core.scala:147:30]
wire int_iss_wakeups_3_bits_uop_frs3_en; // @[core.scala:147:30]
wire int_iss_wakeups_3_bits_uop_fp_val; // @[core.scala:147:30]
wire int_iss_wakeups_3_bits_uop_fp_single; // @[core.scala:147:30]
wire int_iss_wakeups_3_bits_uop_xcpt_pf_if; // @[core.scala:147:30]
wire int_iss_wakeups_3_bits_uop_xcpt_ae_if; // @[core.scala:147:30]
wire int_iss_wakeups_3_bits_uop_xcpt_ma_if; // @[core.scala:147:30]
wire int_iss_wakeups_3_bits_uop_bp_debug_if; // @[core.scala:147:30]
wire int_iss_wakeups_3_bits_uop_bp_xcpt_if; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_3_bits_uop_debug_fsrc; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_3_bits_uop_debug_tsrc; // @[core.scala:147:30]
wire int_iss_wakeups_3_valid; // @[core.scala:147:30]
wire [3:0] int_iss_wakeups_4_bits_uop_ctrl_br_type; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_4_bits_uop_ctrl_op1_sel; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_4_bits_uop_ctrl_op2_sel; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_4_bits_uop_ctrl_imm_sel; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_4_bits_uop_ctrl_op_fcn; // @[core.scala:147:30]
wire int_iss_wakeups_4_bits_uop_ctrl_fcn_dw; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_4_bits_uop_ctrl_csr_cmd; // @[core.scala:147:30]
wire int_iss_wakeups_4_bits_uop_ctrl_is_load; // @[core.scala:147:30]
wire int_iss_wakeups_4_bits_uop_ctrl_is_sta; // @[core.scala:147:30]
wire int_iss_wakeups_4_bits_uop_ctrl_is_std; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_4_bits_uop_uopc; // @[core.scala:147:30]
wire [31:0] int_iss_wakeups_4_bits_uop_inst; // @[core.scala:147:30]
wire [31:0] int_iss_wakeups_4_bits_uop_debug_inst; // @[core.scala:147:30]
wire int_iss_wakeups_4_bits_uop_is_rvc; // @[core.scala:147:30]
wire [39:0] int_iss_wakeups_4_bits_uop_debug_pc; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_4_bits_uop_iq_type; // @[core.scala:147:30]
wire [9:0] int_iss_wakeups_4_bits_uop_fu_code; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_4_bits_uop_iw_state; // @[core.scala:147:30]
wire int_iss_wakeups_4_bits_uop_iw_p1_poisoned; // @[core.scala:147:30]
wire int_iss_wakeups_4_bits_uop_iw_p2_poisoned; // @[core.scala:147:30]
wire int_iss_wakeups_4_bits_uop_is_br; // @[core.scala:147:30]
wire int_iss_wakeups_4_bits_uop_is_jalr; // @[core.scala:147:30]
wire int_iss_wakeups_4_bits_uop_is_jal; // @[core.scala:147:30]
wire int_iss_wakeups_4_bits_uop_is_sfb; // @[core.scala:147:30]
wire [15:0] int_iss_wakeups_4_bits_uop_br_mask; // @[core.scala:147:30]
wire [3:0] int_iss_wakeups_4_bits_uop_br_tag; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_4_bits_uop_ftq_idx; // @[core.scala:147:30]
wire int_iss_wakeups_4_bits_uop_edge_inst; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_4_bits_uop_pc_lob; // @[core.scala:147:30]
wire int_iss_wakeups_4_bits_uop_taken; // @[core.scala:147:30]
wire [19:0] int_iss_wakeups_4_bits_uop_imm_packed; // @[core.scala:147:30]
wire [11:0] int_iss_wakeups_4_bits_uop_csr_addr; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_4_bits_uop_rob_idx; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_4_bits_uop_ldq_idx; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_4_bits_uop_stq_idx; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_4_bits_uop_rxq_idx; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_4_bits_uop_pdst; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_4_bits_uop_prs1; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_4_bits_uop_prs2; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_4_bits_uop_prs3; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_4_bits_uop_ppred; // @[core.scala:147:30]
wire int_iss_wakeups_4_bits_uop_prs1_busy; // @[core.scala:147:30]
wire int_iss_wakeups_4_bits_uop_prs2_busy; // @[core.scala:147:30]
wire int_iss_wakeups_4_bits_uop_prs3_busy; // @[core.scala:147:30]
wire int_iss_wakeups_4_bits_uop_ppred_busy; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_4_bits_uop_stale_pdst; // @[core.scala:147:30]
wire int_iss_wakeups_4_bits_uop_exception; // @[core.scala:147:30]
wire [63:0] int_iss_wakeups_4_bits_uop_exc_cause; // @[core.scala:147:30]
wire int_iss_wakeups_4_bits_uop_bypassable; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_4_bits_uop_mem_cmd; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_4_bits_uop_mem_size; // @[core.scala:147:30]
wire int_iss_wakeups_4_bits_uop_mem_signed; // @[core.scala:147:30]
wire int_iss_wakeups_4_bits_uop_is_fence; // @[core.scala:147:30]
wire int_iss_wakeups_4_bits_uop_is_fencei; // @[core.scala:147:30]
wire int_iss_wakeups_4_bits_uop_is_amo; // @[core.scala:147:30]
wire int_iss_wakeups_4_bits_uop_uses_ldq; // @[core.scala:147:30]
wire int_iss_wakeups_4_bits_uop_uses_stq; // @[core.scala:147:30]
wire int_iss_wakeups_4_bits_uop_is_sys_pc2epc; // @[core.scala:147:30]
wire int_iss_wakeups_4_bits_uop_is_unique; // @[core.scala:147:30]
wire int_iss_wakeups_4_bits_uop_flush_on_commit; // @[core.scala:147:30]
wire int_iss_wakeups_4_bits_uop_ldst_is_rs1; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_4_bits_uop_ldst; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_4_bits_uop_lrs1; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_4_bits_uop_lrs2; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_4_bits_uop_lrs3; // @[core.scala:147:30]
wire int_iss_wakeups_4_bits_uop_ldst_val; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_4_bits_uop_dst_rtype; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_4_bits_uop_lrs1_rtype; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_4_bits_uop_lrs2_rtype; // @[core.scala:147:30]
wire int_iss_wakeups_4_bits_uop_frs3_en; // @[core.scala:147:30]
wire int_iss_wakeups_4_bits_uop_fp_val; // @[core.scala:147:30]
wire int_iss_wakeups_4_bits_uop_fp_single; // @[core.scala:147:30]
wire int_iss_wakeups_4_bits_uop_xcpt_pf_if; // @[core.scala:147:30]
wire int_iss_wakeups_4_bits_uop_xcpt_ae_if; // @[core.scala:147:30]
wire int_iss_wakeups_4_bits_uop_xcpt_ma_if; // @[core.scala:147:30]
wire int_iss_wakeups_4_bits_uop_bp_debug_if; // @[core.scala:147:30]
wire int_iss_wakeups_4_bits_uop_bp_xcpt_if; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_4_bits_uop_debug_fsrc; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_4_bits_uop_debug_tsrc; // @[core.scala:147:30]
wire int_iss_wakeups_4_valid; // @[core.scala:147:30]
wire [3:0] int_iss_wakeups_5_bits_uop_ctrl_br_type; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_5_bits_uop_ctrl_op1_sel; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_5_bits_uop_ctrl_op2_sel; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_5_bits_uop_ctrl_imm_sel; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_5_bits_uop_ctrl_op_fcn; // @[core.scala:147:30]
wire int_iss_wakeups_5_bits_uop_ctrl_fcn_dw; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_5_bits_uop_ctrl_csr_cmd; // @[core.scala:147:30]
wire int_iss_wakeups_5_bits_uop_ctrl_is_load; // @[core.scala:147:30]
wire int_iss_wakeups_5_bits_uop_ctrl_is_sta; // @[core.scala:147:30]
wire int_iss_wakeups_5_bits_uop_ctrl_is_std; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_5_bits_uop_uopc; // @[core.scala:147:30]
wire [31:0] int_iss_wakeups_5_bits_uop_inst; // @[core.scala:147:30]
wire [31:0] int_iss_wakeups_5_bits_uop_debug_inst; // @[core.scala:147:30]
wire int_iss_wakeups_5_bits_uop_is_rvc; // @[core.scala:147:30]
wire [39:0] int_iss_wakeups_5_bits_uop_debug_pc; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_5_bits_uop_iq_type; // @[core.scala:147:30]
wire [9:0] int_iss_wakeups_5_bits_uop_fu_code; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_5_bits_uop_iw_state; // @[core.scala:147:30]
wire int_iss_wakeups_5_bits_uop_iw_p1_poisoned; // @[core.scala:147:30]
wire int_iss_wakeups_5_bits_uop_iw_p2_poisoned; // @[core.scala:147:30]
wire int_iss_wakeups_5_bits_uop_is_br; // @[core.scala:147:30]
wire int_iss_wakeups_5_bits_uop_is_jalr; // @[core.scala:147:30]
wire int_iss_wakeups_5_bits_uop_is_jal; // @[core.scala:147:30]
wire int_iss_wakeups_5_bits_uop_is_sfb; // @[core.scala:147:30]
wire [15:0] int_iss_wakeups_5_bits_uop_br_mask; // @[core.scala:147:30]
wire [3:0] int_iss_wakeups_5_bits_uop_br_tag; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_5_bits_uop_ftq_idx; // @[core.scala:147:30]
wire int_iss_wakeups_5_bits_uop_edge_inst; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_5_bits_uop_pc_lob; // @[core.scala:147:30]
wire int_iss_wakeups_5_bits_uop_taken; // @[core.scala:147:30]
wire [19:0] int_iss_wakeups_5_bits_uop_imm_packed; // @[core.scala:147:30]
wire [11:0] int_iss_wakeups_5_bits_uop_csr_addr; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_5_bits_uop_rob_idx; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_5_bits_uop_ldq_idx; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_5_bits_uop_stq_idx; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_5_bits_uop_rxq_idx; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_5_bits_uop_pdst; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_5_bits_uop_prs1; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_5_bits_uop_prs2; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_5_bits_uop_prs3; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_5_bits_uop_ppred; // @[core.scala:147:30]
wire int_iss_wakeups_5_bits_uop_prs1_busy; // @[core.scala:147:30]
wire int_iss_wakeups_5_bits_uop_prs2_busy; // @[core.scala:147:30]
wire int_iss_wakeups_5_bits_uop_prs3_busy; // @[core.scala:147:30]
wire int_iss_wakeups_5_bits_uop_ppred_busy; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_5_bits_uop_stale_pdst; // @[core.scala:147:30]
wire int_iss_wakeups_5_bits_uop_exception; // @[core.scala:147:30]
wire [63:0] int_iss_wakeups_5_bits_uop_exc_cause; // @[core.scala:147:30]
wire int_iss_wakeups_5_bits_uop_bypassable; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_5_bits_uop_mem_cmd; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_5_bits_uop_mem_size; // @[core.scala:147:30]
wire int_iss_wakeups_5_bits_uop_mem_signed; // @[core.scala:147:30]
wire int_iss_wakeups_5_bits_uop_is_fence; // @[core.scala:147:30]
wire int_iss_wakeups_5_bits_uop_is_fencei; // @[core.scala:147:30]
wire int_iss_wakeups_5_bits_uop_is_amo; // @[core.scala:147:30]
wire int_iss_wakeups_5_bits_uop_uses_ldq; // @[core.scala:147:30]
wire int_iss_wakeups_5_bits_uop_uses_stq; // @[core.scala:147:30]
wire int_iss_wakeups_5_bits_uop_is_sys_pc2epc; // @[core.scala:147:30]
wire int_iss_wakeups_5_bits_uop_is_unique; // @[core.scala:147:30]
wire int_iss_wakeups_5_bits_uop_flush_on_commit; // @[core.scala:147:30]
wire int_iss_wakeups_5_bits_uop_ldst_is_rs1; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_5_bits_uop_ldst; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_5_bits_uop_lrs1; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_5_bits_uop_lrs2; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_5_bits_uop_lrs3; // @[core.scala:147:30]
wire int_iss_wakeups_5_bits_uop_ldst_val; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_5_bits_uop_dst_rtype; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_5_bits_uop_lrs1_rtype; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_5_bits_uop_lrs2_rtype; // @[core.scala:147:30]
wire int_iss_wakeups_5_bits_uop_frs3_en; // @[core.scala:147:30]
wire int_iss_wakeups_5_bits_uop_fp_val; // @[core.scala:147:30]
wire int_iss_wakeups_5_bits_uop_fp_single; // @[core.scala:147:30]
wire int_iss_wakeups_5_bits_uop_xcpt_pf_if; // @[core.scala:147:30]
wire int_iss_wakeups_5_bits_uop_xcpt_ae_if; // @[core.scala:147:30]
wire int_iss_wakeups_5_bits_uop_xcpt_ma_if; // @[core.scala:147:30]
wire int_iss_wakeups_5_bits_uop_bp_debug_if; // @[core.scala:147:30]
wire int_iss_wakeups_5_bits_uop_bp_xcpt_if; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_5_bits_uop_debug_fsrc; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_5_bits_uop_debug_tsrc; // @[core.scala:147:30]
wire int_iss_wakeups_5_valid; // @[core.scala:147:30]
wire [3:0] int_iss_wakeups_6_bits_uop_ctrl_br_type; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_6_bits_uop_ctrl_op1_sel; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_6_bits_uop_ctrl_op2_sel; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_6_bits_uop_ctrl_imm_sel; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_6_bits_uop_ctrl_op_fcn; // @[core.scala:147:30]
wire int_iss_wakeups_6_bits_uop_ctrl_fcn_dw; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_6_bits_uop_ctrl_csr_cmd; // @[core.scala:147:30]
wire int_iss_wakeups_6_bits_uop_ctrl_is_load; // @[core.scala:147:30]
wire int_iss_wakeups_6_bits_uop_ctrl_is_sta; // @[core.scala:147:30]
wire int_iss_wakeups_6_bits_uop_ctrl_is_std; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_6_bits_uop_uopc; // @[core.scala:147:30]
wire [31:0] int_iss_wakeups_6_bits_uop_inst; // @[core.scala:147:30]
wire [31:0] int_iss_wakeups_6_bits_uop_debug_inst; // @[core.scala:147:30]
wire int_iss_wakeups_6_bits_uop_is_rvc; // @[core.scala:147:30]
wire [39:0] int_iss_wakeups_6_bits_uop_debug_pc; // @[core.scala:147:30]
wire [2:0] int_iss_wakeups_6_bits_uop_iq_type; // @[core.scala:147:30]
wire [9:0] int_iss_wakeups_6_bits_uop_fu_code; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_6_bits_uop_iw_state; // @[core.scala:147:30]
wire int_iss_wakeups_6_bits_uop_iw_p1_poisoned; // @[core.scala:147:30]
wire int_iss_wakeups_6_bits_uop_iw_p2_poisoned; // @[core.scala:147:30]
wire int_iss_wakeups_6_bits_uop_is_br; // @[core.scala:147:30]
wire int_iss_wakeups_6_bits_uop_is_jalr; // @[core.scala:147:30]
wire int_iss_wakeups_6_bits_uop_is_jal; // @[core.scala:147:30]
wire int_iss_wakeups_6_bits_uop_is_sfb; // @[core.scala:147:30]
wire [15:0] int_iss_wakeups_6_bits_uop_br_mask; // @[core.scala:147:30]
wire [3:0] int_iss_wakeups_6_bits_uop_br_tag; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_6_bits_uop_ftq_idx; // @[core.scala:147:30]
wire int_iss_wakeups_6_bits_uop_edge_inst; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_6_bits_uop_pc_lob; // @[core.scala:147:30]
wire int_iss_wakeups_6_bits_uop_taken; // @[core.scala:147:30]
wire [19:0] int_iss_wakeups_6_bits_uop_imm_packed; // @[core.scala:147:30]
wire [11:0] int_iss_wakeups_6_bits_uop_csr_addr; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_6_bits_uop_rob_idx; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_6_bits_uop_ldq_idx; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_6_bits_uop_stq_idx; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_6_bits_uop_rxq_idx; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_6_bits_uop_pdst; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_6_bits_uop_prs1; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_6_bits_uop_prs2; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_6_bits_uop_prs3; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_6_bits_uop_ppred; // @[core.scala:147:30]
wire int_iss_wakeups_6_bits_uop_prs1_busy; // @[core.scala:147:30]
wire int_iss_wakeups_6_bits_uop_prs2_busy; // @[core.scala:147:30]
wire int_iss_wakeups_6_bits_uop_prs3_busy; // @[core.scala:147:30]
wire int_iss_wakeups_6_bits_uop_ppred_busy; // @[core.scala:147:30]
wire [6:0] int_iss_wakeups_6_bits_uop_stale_pdst; // @[core.scala:147:30]
wire int_iss_wakeups_6_bits_uop_exception; // @[core.scala:147:30]
wire [63:0] int_iss_wakeups_6_bits_uop_exc_cause; // @[core.scala:147:30]
wire int_iss_wakeups_6_bits_uop_bypassable; // @[core.scala:147:30]
wire [4:0] int_iss_wakeups_6_bits_uop_mem_cmd; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_6_bits_uop_mem_size; // @[core.scala:147:30]
wire int_iss_wakeups_6_bits_uop_mem_signed; // @[core.scala:147:30]
wire int_iss_wakeups_6_bits_uop_is_fence; // @[core.scala:147:30]
wire int_iss_wakeups_6_bits_uop_is_fencei; // @[core.scala:147:30]
wire int_iss_wakeups_6_bits_uop_is_amo; // @[core.scala:147:30]
wire int_iss_wakeups_6_bits_uop_uses_ldq; // @[core.scala:147:30]
wire int_iss_wakeups_6_bits_uop_uses_stq; // @[core.scala:147:30]
wire int_iss_wakeups_6_bits_uop_is_sys_pc2epc; // @[core.scala:147:30]
wire int_iss_wakeups_6_bits_uop_is_unique; // @[core.scala:147:30]
wire int_iss_wakeups_6_bits_uop_flush_on_commit; // @[core.scala:147:30]
wire int_iss_wakeups_6_bits_uop_ldst_is_rs1; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_6_bits_uop_ldst; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_6_bits_uop_lrs1; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_6_bits_uop_lrs2; // @[core.scala:147:30]
wire [5:0] int_iss_wakeups_6_bits_uop_lrs3; // @[core.scala:147:30]
wire int_iss_wakeups_6_bits_uop_ldst_val; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_6_bits_uop_dst_rtype; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_6_bits_uop_lrs1_rtype; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_6_bits_uop_lrs2_rtype; // @[core.scala:147:30]
wire int_iss_wakeups_6_bits_uop_frs3_en; // @[core.scala:147:30]
wire int_iss_wakeups_6_bits_uop_fp_val; // @[core.scala:147:30]
wire int_iss_wakeups_6_bits_uop_fp_single; // @[core.scala:147:30]
wire int_iss_wakeups_6_bits_uop_xcpt_pf_if; // @[core.scala:147:30]
wire int_iss_wakeups_6_bits_uop_xcpt_ae_if; // @[core.scala:147:30]
wire int_iss_wakeups_6_bits_uop_xcpt_ma_if; // @[core.scala:147:30]
wire int_iss_wakeups_6_bits_uop_bp_debug_if; // @[core.scala:147:30]
wire int_iss_wakeups_6_bits_uop_bp_xcpt_if; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_6_bits_uop_debug_fsrc; // @[core.scala:147:30]
wire [1:0] int_iss_wakeups_6_bits_uop_debug_tsrc; // @[core.scala:147:30]
wire int_iss_wakeups_6_valid; // @[core.scala:147:30]
wire _int_ren_wakeups_0_valid_T_2; // @[core.scala:798:52]
wire [3:0] int_ren_wakeups_0_bits_uop_ctrl_br_type; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_0_bits_uop_ctrl_op1_sel; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_0_bits_uop_ctrl_op2_sel; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_0_bits_uop_ctrl_imm_sel; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_0_bits_uop_ctrl_op_fcn; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_uop_ctrl_fcn_dw; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_0_bits_uop_ctrl_csr_cmd; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_uop_ctrl_is_load; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_uop_ctrl_is_sta; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_uop_ctrl_is_std; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_0_bits_uop_uopc; // @[core.scala:148:30]
wire [31:0] int_ren_wakeups_0_bits_uop_inst; // @[core.scala:148:30]
wire [31:0] int_ren_wakeups_0_bits_uop_debug_inst; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_uop_is_rvc; // @[core.scala:148:30]
wire [39:0] int_ren_wakeups_0_bits_uop_debug_pc; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_0_bits_uop_iq_type; // @[core.scala:148:30]
wire [9:0] int_ren_wakeups_0_bits_uop_fu_code; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_0_bits_uop_iw_state; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_uop_iw_p1_poisoned; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_uop_iw_p2_poisoned; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_uop_is_br; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_uop_is_jalr; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_uop_is_jal; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_uop_is_sfb; // @[core.scala:148:30]
wire [15:0] int_ren_wakeups_0_bits_uop_br_mask; // @[core.scala:148:30]
wire [3:0] int_ren_wakeups_0_bits_uop_br_tag; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_0_bits_uop_ftq_idx; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_uop_edge_inst; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_0_bits_uop_pc_lob; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_uop_taken; // @[core.scala:148:30]
wire [19:0] int_ren_wakeups_0_bits_uop_imm_packed; // @[core.scala:148:30]
wire [11:0] int_ren_wakeups_0_bits_uop_csr_addr; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_0_bits_uop_rob_idx; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_0_bits_uop_ldq_idx; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_0_bits_uop_stq_idx; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_0_bits_uop_rxq_idx; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_0_bits_uop_pdst; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_0_bits_uop_prs1; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_0_bits_uop_prs2; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_0_bits_uop_prs3; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_0_bits_uop_ppred; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_uop_prs1_busy; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_uop_prs2_busy; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_uop_prs3_busy; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_uop_ppred_busy; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_0_bits_uop_stale_pdst; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_uop_exception; // @[core.scala:148:30]
wire [63:0] int_ren_wakeups_0_bits_uop_exc_cause; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_uop_bypassable; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_0_bits_uop_mem_cmd; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_0_bits_uop_mem_size; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_uop_mem_signed; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_uop_is_fence; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_uop_is_fencei; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_uop_is_amo; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_uop_uses_ldq; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_uop_uses_stq; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_uop_is_sys_pc2epc; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_uop_is_unique; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_uop_flush_on_commit; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_uop_ldst_is_rs1; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_0_bits_uop_ldst; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_0_bits_uop_lrs1; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_0_bits_uop_lrs2; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_0_bits_uop_lrs3; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_uop_ldst_val; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_0_bits_uop_dst_rtype; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_0_bits_uop_lrs1_rtype; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_0_bits_uop_lrs2_rtype; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_uop_frs3_en; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_uop_fp_val; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_uop_fp_single; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_uop_xcpt_pf_if; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_uop_xcpt_ae_if; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_uop_xcpt_ma_if; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_uop_bp_debug_if; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_uop_bp_xcpt_if; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_0_bits_uop_debug_fsrc; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_0_bits_uop_debug_tsrc; // @[core.scala:148:30]
wire [3:0] int_ren_wakeups_0_bits_fflags_bits_uop_ctrl_br_type; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_0_bits_fflags_bits_uop_ctrl_op1_sel; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_0_bits_fflags_bits_uop_ctrl_op2_sel; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_0_bits_fflags_bits_uop_ctrl_imm_sel; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_0_bits_fflags_bits_uop_ctrl_op_fcn; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_fflags_bits_uop_ctrl_fcn_dw; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_0_bits_fflags_bits_uop_ctrl_csr_cmd; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_fflags_bits_uop_ctrl_is_load; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_fflags_bits_uop_ctrl_is_sta; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_fflags_bits_uop_ctrl_is_std; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_0_bits_fflags_bits_uop_uopc; // @[core.scala:148:30]
wire [31:0] int_ren_wakeups_0_bits_fflags_bits_uop_inst; // @[core.scala:148:30]
wire [31:0] int_ren_wakeups_0_bits_fflags_bits_uop_debug_inst; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_fflags_bits_uop_is_rvc; // @[core.scala:148:30]
wire [39:0] int_ren_wakeups_0_bits_fflags_bits_uop_debug_pc; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_0_bits_fflags_bits_uop_iq_type; // @[core.scala:148:30]
wire [9:0] int_ren_wakeups_0_bits_fflags_bits_uop_fu_code; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_0_bits_fflags_bits_uop_iw_state; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_fflags_bits_uop_iw_p1_poisoned; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_fflags_bits_uop_iw_p2_poisoned; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_fflags_bits_uop_is_br; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_fflags_bits_uop_is_jalr; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_fflags_bits_uop_is_jal; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_fflags_bits_uop_is_sfb; // @[core.scala:148:30]
wire [15:0] int_ren_wakeups_0_bits_fflags_bits_uop_br_mask; // @[core.scala:148:30]
wire [3:0] int_ren_wakeups_0_bits_fflags_bits_uop_br_tag; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_0_bits_fflags_bits_uop_ftq_idx; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_fflags_bits_uop_edge_inst; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_0_bits_fflags_bits_uop_pc_lob; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_fflags_bits_uop_taken; // @[core.scala:148:30]
wire [19:0] int_ren_wakeups_0_bits_fflags_bits_uop_imm_packed; // @[core.scala:148:30]
wire [11:0] int_ren_wakeups_0_bits_fflags_bits_uop_csr_addr; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_0_bits_fflags_bits_uop_rob_idx; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_0_bits_fflags_bits_uop_ldq_idx; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_0_bits_fflags_bits_uop_stq_idx; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_0_bits_fflags_bits_uop_rxq_idx; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_0_bits_fflags_bits_uop_pdst; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_0_bits_fflags_bits_uop_prs1; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_0_bits_fflags_bits_uop_prs2; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_0_bits_fflags_bits_uop_prs3; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_0_bits_fflags_bits_uop_ppred; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_fflags_bits_uop_prs1_busy; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_fflags_bits_uop_prs2_busy; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_fflags_bits_uop_prs3_busy; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_fflags_bits_uop_ppred_busy; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_0_bits_fflags_bits_uop_stale_pdst; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_fflags_bits_uop_exception; // @[core.scala:148:30]
wire [63:0] int_ren_wakeups_0_bits_fflags_bits_uop_exc_cause; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_fflags_bits_uop_bypassable; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_0_bits_fflags_bits_uop_mem_cmd; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_0_bits_fflags_bits_uop_mem_size; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_fflags_bits_uop_mem_signed; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_fflags_bits_uop_is_fence; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_fflags_bits_uop_is_fencei; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_fflags_bits_uop_is_amo; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_fflags_bits_uop_uses_ldq; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_fflags_bits_uop_uses_stq; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_fflags_bits_uop_is_sys_pc2epc; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_fflags_bits_uop_is_unique; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_fflags_bits_uop_flush_on_commit; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_fflags_bits_uop_ldst_is_rs1; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_0_bits_fflags_bits_uop_ldst; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_0_bits_fflags_bits_uop_lrs1; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_0_bits_fflags_bits_uop_lrs2; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_0_bits_fflags_bits_uop_lrs3; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_fflags_bits_uop_ldst_val; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_0_bits_fflags_bits_uop_dst_rtype; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_0_bits_fflags_bits_uop_lrs1_rtype; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_0_bits_fflags_bits_uop_lrs2_rtype; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_fflags_bits_uop_frs3_en; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_fflags_bits_uop_fp_val; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_fflags_bits_uop_fp_single; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_fflags_bits_uop_xcpt_pf_if; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_fflags_bits_uop_xcpt_ae_if; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_fflags_bits_uop_xcpt_ma_if; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_fflags_bits_uop_bp_debug_if; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_fflags_bits_uop_bp_xcpt_if; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_0_bits_fflags_bits_uop_debug_fsrc; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_0_bits_fflags_bits_uop_debug_tsrc; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_0_bits_fflags_bits_flags; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_fflags_valid; // @[core.scala:148:30]
wire [63:0] int_ren_wakeups_0_bits_data; // @[core.scala:148:30]
wire int_ren_wakeups_0_bits_predicated; // @[core.scala:148:30]
wire int_ren_wakeups_0_valid; // @[core.scala:148:30]
wire [3:0] int_ren_wakeups_1_bits_uop_ctrl_br_type; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_1_bits_uop_ctrl_op1_sel; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_1_bits_uop_ctrl_op2_sel; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_1_bits_uop_ctrl_imm_sel; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_1_bits_uop_ctrl_op_fcn; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_uop_ctrl_fcn_dw; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_1_bits_uop_ctrl_csr_cmd; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_uop_ctrl_is_load; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_uop_ctrl_is_sta; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_uop_ctrl_is_std; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_1_bits_uop_uopc; // @[core.scala:148:30]
wire [31:0] int_ren_wakeups_1_bits_uop_inst; // @[core.scala:148:30]
wire [31:0] int_ren_wakeups_1_bits_uop_debug_inst; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_uop_is_rvc; // @[core.scala:148:30]
wire [39:0] int_ren_wakeups_1_bits_uop_debug_pc; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_1_bits_uop_iq_type; // @[core.scala:148:30]
wire [9:0] int_ren_wakeups_1_bits_uop_fu_code; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_1_bits_uop_iw_state; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_uop_iw_p1_poisoned; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_uop_iw_p2_poisoned; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_uop_is_br; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_uop_is_jalr; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_uop_is_jal; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_uop_is_sfb; // @[core.scala:148:30]
wire [15:0] int_ren_wakeups_1_bits_uop_br_mask; // @[core.scala:148:30]
wire [3:0] int_ren_wakeups_1_bits_uop_br_tag; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_1_bits_uop_ftq_idx; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_uop_edge_inst; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_1_bits_uop_pc_lob; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_uop_taken; // @[core.scala:148:30]
wire [19:0] int_ren_wakeups_1_bits_uop_imm_packed; // @[core.scala:148:30]
wire [11:0] int_ren_wakeups_1_bits_uop_csr_addr; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_1_bits_uop_rob_idx; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_1_bits_uop_ldq_idx; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_1_bits_uop_stq_idx; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_1_bits_uop_rxq_idx; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_1_bits_uop_pdst; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_1_bits_uop_prs1; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_1_bits_uop_prs2; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_1_bits_uop_prs3; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_1_bits_uop_ppred; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_uop_prs1_busy; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_uop_prs2_busy; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_uop_prs3_busy; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_uop_ppred_busy; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_1_bits_uop_stale_pdst; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_uop_exception; // @[core.scala:148:30]
wire [63:0] int_ren_wakeups_1_bits_uop_exc_cause; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_uop_bypassable; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_1_bits_uop_mem_cmd; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_1_bits_uop_mem_size; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_uop_mem_signed; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_uop_is_fence; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_uop_is_fencei; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_uop_is_amo; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_uop_uses_ldq; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_uop_uses_stq; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_uop_is_sys_pc2epc; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_uop_is_unique; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_uop_flush_on_commit; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_uop_ldst_is_rs1; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_1_bits_uop_ldst; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_1_bits_uop_lrs1; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_1_bits_uop_lrs2; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_1_bits_uop_lrs3; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_uop_ldst_val; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_1_bits_uop_dst_rtype; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_1_bits_uop_lrs1_rtype; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_1_bits_uop_lrs2_rtype; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_uop_frs3_en; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_uop_fp_val; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_uop_fp_single; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_uop_xcpt_pf_if; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_uop_xcpt_ae_if; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_uop_xcpt_ma_if; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_uop_bp_debug_if; // @[core.scala:148:30]
wire int_ren_wakeups_1_bits_uop_bp_xcpt_if; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_1_bits_uop_debug_fsrc; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_1_bits_uop_debug_tsrc; // @[core.scala:148:30]
wire int_ren_wakeups_1_valid; // @[core.scala:148:30]
wire [3:0] int_ren_wakeups_2_bits_uop_ctrl_br_type; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_2_bits_uop_ctrl_op1_sel; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_2_bits_uop_ctrl_op2_sel; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_2_bits_uop_ctrl_imm_sel; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_2_bits_uop_ctrl_op_fcn; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_uop_ctrl_fcn_dw; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_2_bits_uop_ctrl_csr_cmd; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_uop_ctrl_is_load; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_uop_ctrl_is_sta; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_uop_ctrl_is_std; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_2_bits_uop_uopc; // @[core.scala:148:30]
wire [31:0] int_ren_wakeups_2_bits_uop_inst; // @[core.scala:148:30]
wire [31:0] int_ren_wakeups_2_bits_uop_debug_inst; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_uop_is_rvc; // @[core.scala:148:30]
wire [39:0] int_ren_wakeups_2_bits_uop_debug_pc; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_2_bits_uop_iq_type; // @[core.scala:148:30]
wire [9:0] int_ren_wakeups_2_bits_uop_fu_code; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_2_bits_uop_iw_state; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_uop_iw_p1_poisoned; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_uop_iw_p2_poisoned; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_uop_is_br; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_uop_is_jalr; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_uop_is_jal; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_uop_is_sfb; // @[core.scala:148:30]
wire [15:0] int_ren_wakeups_2_bits_uop_br_mask; // @[core.scala:148:30]
wire [3:0] int_ren_wakeups_2_bits_uop_br_tag; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_2_bits_uop_ftq_idx; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_uop_edge_inst; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_2_bits_uop_pc_lob; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_uop_taken; // @[core.scala:148:30]
wire [19:0] int_ren_wakeups_2_bits_uop_imm_packed; // @[core.scala:148:30]
wire [11:0] int_ren_wakeups_2_bits_uop_csr_addr; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_2_bits_uop_rob_idx; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_2_bits_uop_ldq_idx; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_2_bits_uop_stq_idx; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_2_bits_uop_rxq_idx; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_2_bits_uop_pdst; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_2_bits_uop_prs1; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_2_bits_uop_prs2; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_2_bits_uop_prs3; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_2_bits_uop_ppred; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_uop_prs1_busy; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_uop_prs2_busy; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_uop_prs3_busy; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_uop_ppred_busy; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_2_bits_uop_stale_pdst; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_uop_exception; // @[core.scala:148:30]
wire [63:0] int_ren_wakeups_2_bits_uop_exc_cause; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_uop_bypassable; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_2_bits_uop_mem_cmd; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_2_bits_uop_mem_size; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_uop_mem_signed; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_uop_is_fence; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_uop_is_fencei; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_uop_is_amo; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_uop_uses_ldq; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_uop_uses_stq; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_uop_is_sys_pc2epc; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_uop_is_unique; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_uop_flush_on_commit; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_uop_ldst_is_rs1; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_2_bits_uop_ldst; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_2_bits_uop_lrs1; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_2_bits_uop_lrs2; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_2_bits_uop_lrs3; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_uop_ldst_val; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_2_bits_uop_dst_rtype; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_2_bits_uop_lrs1_rtype; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_2_bits_uop_lrs2_rtype; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_uop_frs3_en; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_uop_fp_val; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_uop_fp_single; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_uop_xcpt_pf_if; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_uop_xcpt_ae_if; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_uop_xcpt_ma_if; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_uop_bp_debug_if; // @[core.scala:148:30]
wire int_ren_wakeups_2_bits_uop_bp_xcpt_if; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_2_bits_uop_debug_fsrc; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_2_bits_uop_debug_tsrc; // @[core.scala:148:30]
wire int_ren_wakeups_2_valid; // @[core.scala:148:30]
wire [3:0] int_ren_wakeups_3_bits_uop_ctrl_br_type; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_3_bits_uop_ctrl_op1_sel; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_3_bits_uop_ctrl_op2_sel; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_3_bits_uop_ctrl_imm_sel; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_3_bits_uop_ctrl_op_fcn; // @[core.scala:148:30]
wire int_ren_wakeups_3_bits_uop_ctrl_fcn_dw; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_3_bits_uop_ctrl_csr_cmd; // @[core.scala:148:30]
wire int_ren_wakeups_3_bits_uop_ctrl_is_load; // @[core.scala:148:30]
wire int_ren_wakeups_3_bits_uop_ctrl_is_sta; // @[core.scala:148:30]
wire int_ren_wakeups_3_bits_uop_ctrl_is_std; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_3_bits_uop_uopc; // @[core.scala:148:30]
wire [31:0] int_ren_wakeups_3_bits_uop_inst; // @[core.scala:148:30]
wire [31:0] int_ren_wakeups_3_bits_uop_debug_inst; // @[core.scala:148:30]
wire int_ren_wakeups_3_bits_uop_is_rvc; // @[core.scala:148:30]
wire [39:0] int_ren_wakeups_3_bits_uop_debug_pc; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_3_bits_uop_iq_type; // @[core.scala:148:30]
wire [9:0] int_ren_wakeups_3_bits_uop_fu_code; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_3_bits_uop_iw_state; // @[core.scala:148:30]
wire int_ren_wakeups_3_bits_uop_iw_p1_poisoned; // @[core.scala:148:30]
wire int_ren_wakeups_3_bits_uop_iw_p2_poisoned; // @[core.scala:148:30]
wire int_ren_wakeups_3_bits_uop_is_br; // @[core.scala:148:30]
wire int_ren_wakeups_3_bits_uop_is_jalr; // @[core.scala:148:30]
wire int_ren_wakeups_3_bits_uop_is_jal; // @[core.scala:148:30]
wire int_ren_wakeups_3_bits_uop_is_sfb; // @[core.scala:148:30]
wire [15:0] int_ren_wakeups_3_bits_uop_br_mask; // @[core.scala:148:30]
wire [3:0] int_ren_wakeups_3_bits_uop_br_tag; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_3_bits_uop_ftq_idx; // @[core.scala:148:30]
wire int_ren_wakeups_3_bits_uop_edge_inst; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_3_bits_uop_pc_lob; // @[core.scala:148:30]
wire int_ren_wakeups_3_bits_uop_taken; // @[core.scala:148:30]
wire [19:0] int_ren_wakeups_3_bits_uop_imm_packed; // @[core.scala:148:30]
wire [11:0] int_ren_wakeups_3_bits_uop_csr_addr; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_3_bits_uop_rob_idx; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_3_bits_uop_ldq_idx; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_3_bits_uop_stq_idx; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_3_bits_uop_rxq_idx; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_3_bits_uop_pdst; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_3_bits_uop_prs1; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_3_bits_uop_prs2; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_3_bits_uop_prs3; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_3_bits_uop_ppred; // @[core.scala:148:30]
wire int_ren_wakeups_3_bits_uop_prs1_busy; // @[core.scala:148:30]
wire int_ren_wakeups_3_bits_uop_prs2_busy; // @[core.scala:148:30]
wire int_ren_wakeups_3_bits_uop_prs3_busy; // @[core.scala:148:30]
wire int_ren_wakeups_3_bits_uop_ppred_busy; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_3_bits_uop_stale_pdst; // @[core.scala:148:30]
wire int_ren_wakeups_3_bits_uop_exception; // @[core.scala:148:30]
wire [63:0] int_ren_wakeups_3_bits_uop_exc_cause; // @[core.scala:148:30]
wire int_ren_wakeups_3_bits_uop_bypassable; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_3_bits_uop_mem_cmd; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_3_bits_uop_mem_size; // @[core.scala:148:30]
wire int_ren_wakeups_3_bits_uop_mem_signed; // @[core.scala:148:30]
wire int_ren_wakeups_3_bits_uop_is_fence; // @[core.scala:148:30]
wire int_ren_wakeups_3_bits_uop_is_fencei; // @[core.scala:148:30]
wire int_ren_wakeups_3_bits_uop_is_amo; // @[core.scala:148:30]
wire int_ren_wakeups_3_bits_uop_uses_ldq; // @[core.scala:148:30]
wire int_ren_wakeups_3_bits_uop_uses_stq; // @[core.scala:148:30]
wire int_ren_wakeups_3_bits_uop_is_sys_pc2epc; // @[core.scala:148:30]
wire int_ren_wakeups_3_bits_uop_is_unique; // @[core.scala:148:30]
wire int_ren_wakeups_3_bits_uop_flush_on_commit; // @[core.scala:148:30]
wire int_ren_wakeups_3_bits_uop_ldst_is_rs1; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_3_bits_uop_ldst; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_3_bits_uop_lrs1; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_3_bits_uop_lrs2; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_3_bits_uop_lrs3; // @[core.scala:148:30]
wire int_ren_wakeups_3_bits_uop_ldst_val; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_3_bits_uop_dst_rtype; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_3_bits_uop_lrs1_rtype; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_3_bits_uop_lrs2_rtype; // @[core.scala:148:30]
wire int_ren_wakeups_3_bits_uop_frs3_en; // @[core.scala:148:30]
wire int_ren_wakeups_3_bits_uop_fp_val; // @[core.scala:148:30]
wire int_ren_wakeups_3_bits_uop_fp_single; // @[core.scala:148:30]
wire int_ren_wakeups_3_bits_uop_xcpt_pf_if; // @[core.scala:148:30]
wire int_ren_wakeups_3_bits_uop_xcpt_ae_if; // @[core.scala:148:30]
wire int_ren_wakeups_3_bits_uop_xcpt_ma_if; // @[core.scala:148:30]
wire int_ren_wakeups_3_bits_uop_bp_debug_if; // @[core.scala:148:30]
wire int_ren_wakeups_3_bits_uop_bp_xcpt_if; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_3_bits_uop_debug_fsrc; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_3_bits_uop_debug_tsrc; // @[core.scala:148:30]
wire int_ren_wakeups_3_valid; // @[core.scala:148:30]
wire [3:0] int_ren_wakeups_4_bits_uop_ctrl_br_type; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_4_bits_uop_ctrl_op1_sel; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_4_bits_uop_ctrl_op2_sel; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_4_bits_uop_ctrl_imm_sel; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_4_bits_uop_ctrl_op_fcn; // @[core.scala:148:30]
wire int_ren_wakeups_4_bits_uop_ctrl_fcn_dw; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_4_bits_uop_ctrl_csr_cmd; // @[core.scala:148:30]
wire int_ren_wakeups_4_bits_uop_ctrl_is_load; // @[core.scala:148:30]
wire int_ren_wakeups_4_bits_uop_ctrl_is_sta; // @[core.scala:148:30]
wire int_ren_wakeups_4_bits_uop_ctrl_is_std; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_4_bits_uop_uopc; // @[core.scala:148:30]
wire [31:0] int_ren_wakeups_4_bits_uop_inst; // @[core.scala:148:30]
wire [31:0] int_ren_wakeups_4_bits_uop_debug_inst; // @[core.scala:148:30]
wire int_ren_wakeups_4_bits_uop_is_rvc; // @[core.scala:148:30]
wire [39:0] int_ren_wakeups_4_bits_uop_debug_pc; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_4_bits_uop_iq_type; // @[core.scala:148:30]
wire [9:0] int_ren_wakeups_4_bits_uop_fu_code; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_4_bits_uop_iw_state; // @[core.scala:148:30]
wire int_ren_wakeups_4_bits_uop_iw_p1_poisoned; // @[core.scala:148:30]
wire int_ren_wakeups_4_bits_uop_iw_p2_poisoned; // @[core.scala:148:30]
wire int_ren_wakeups_4_bits_uop_is_br; // @[core.scala:148:30]
wire int_ren_wakeups_4_bits_uop_is_jalr; // @[core.scala:148:30]
wire int_ren_wakeups_4_bits_uop_is_jal; // @[core.scala:148:30]
wire int_ren_wakeups_4_bits_uop_is_sfb; // @[core.scala:148:30]
wire [15:0] int_ren_wakeups_4_bits_uop_br_mask; // @[core.scala:148:30]
wire [3:0] int_ren_wakeups_4_bits_uop_br_tag; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_4_bits_uop_ftq_idx; // @[core.scala:148:30]
wire int_ren_wakeups_4_bits_uop_edge_inst; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_4_bits_uop_pc_lob; // @[core.scala:148:30]
wire int_ren_wakeups_4_bits_uop_taken; // @[core.scala:148:30]
wire [19:0] int_ren_wakeups_4_bits_uop_imm_packed; // @[core.scala:148:30]
wire [11:0] int_ren_wakeups_4_bits_uop_csr_addr; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_4_bits_uop_rob_idx; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_4_bits_uop_ldq_idx; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_4_bits_uop_stq_idx; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_4_bits_uop_rxq_idx; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_4_bits_uop_pdst; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_4_bits_uop_prs1; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_4_bits_uop_prs2; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_4_bits_uop_prs3; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_4_bits_uop_ppred; // @[core.scala:148:30]
wire int_ren_wakeups_4_bits_uop_prs1_busy; // @[core.scala:148:30]
wire int_ren_wakeups_4_bits_uop_prs2_busy; // @[core.scala:148:30]
wire int_ren_wakeups_4_bits_uop_prs3_busy; // @[core.scala:148:30]
wire int_ren_wakeups_4_bits_uop_ppred_busy; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_4_bits_uop_stale_pdst; // @[core.scala:148:30]
wire int_ren_wakeups_4_bits_uop_exception; // @[core.scala:148:30]
wire [63:0] int_ren_wakeups_4_bits_uop_exc_cause; // @[core.scala:148:30]
wire int_ren_wakeups_4_bits_uop_bypassable; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_4_bits_uop_mem_cmd; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_4_bits_uop_mem_size; // @[core.scala:148:30]
wire int_ren_wakeups_4_bits_uop_mem_signed; // @[core.scala:148:30]
wire int_ren_wakeups_4_bits_uop_is_fence; // @[core.scala:148:30]
wire int_ren_wakeups_4_bits_uop_is_fencei; // @[core.scala:148:30]
wire int_ren_wakeups_4_bits_uop_is_amo; // @[core.scala:148:30]
wire int_ren_wakeups_4_bits_uop_uses_ldq; // @[core.scala:148:30]
wire int_ren_wakeups_4_bits_uop_uses_stq; // @[core.scala:148:30]
wire int_ren_wakeups_4_bits_uop_is_sys_pc2epc; // @[core.scala:148:30]
wire int_ren_wakeups_4_bits_uop_is_unique; // @[core.scala:148:30]
wire int_ren_wakeups_4_bits_uop_flush_on_commit; // @[core.scala:148:30]
wire int_ren_wakeups_4_bits_uop_ldst_is_rs1; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_4_bits_uop_ldst; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_4_bits_uop_lrs1; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_4_bits_uop_lrs2; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_4_bits_uop_lrs3; // @[core.scala:148:30]
wire int_ren_wakeups_4_bits_uop_ldst_val; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_4_bits_uop_dst_rtype; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_4_bits_uop_lrs1_rtype; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_4_bits_uop_lrs2_rtype; // @[core.scala:148:30]
wire int_ren_wakeups_4_bits_uop_frs3_en; // @[core.scala:148:30]
wire int_ren_wakeups_4_bits_uop_fp_val; // @[core.scala:148:30]
wire int_ren_wakeups_4_bits_uop_fp_single; // @[core.scala:148:30]
wire int_ren_wakeups_4_bits_uop_xcpt_pf_if; // @[core.scala:148:30]
wire int_ren_wakeups_4_bits_uop_xcpt_ae_if; // @[core.scala:148:30]
wire int_ren_wakeups_4_bits_uop_xcpt_ma_if; // @[core.scala:148:30]
wire int_ren_wakeups_4_bits_uop_bp_debug_if; // @[core.scala:148:30]
wire int_ren_wakeups_4_bits_uop_bp_xcpt_if; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_4_bits_uop_debug_fsrc; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_4_bits_uop_debug_tsrc; // @[core.scala:148:30]
wire int_ren_wakeups_4_valid; // @[core.scala:148:30]
wire [3:0] int_ren_wakeups_5_bits_uop_ctrl_br_type; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_5_bits_uop_ctrl_op1_sel; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_5_bits_uop_ctrl_op2_sel; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_5_bits_uop_ctrl_imm_sel; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_5_bits_uop_ctrl_op_fcn; // @[core.scala:148:30]
wire int_ren_wakeups_5_bits_uop_ctrl_fcn_dw; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_5_bits_uop_ctrl_csr_cmd; // @[core.scala:148:30]
wire int_ren_wakeups_5_bits_uop_ctrl_is_load; // @[core.scala:148:30]
wire int_ren_wakeups_5_bits_uop_ctrl_is_sta; // @[core.scala:148:30]
wire int_ren_wakeups_5_bits_uop_ctrl_is_std; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_5_bits_uop_uopc; // @[core.scala:148:30]
wire [31:0] int_ren_wakeups_5_bits_uop_inst; // @[core.scala:148:30]
wire [31:0] int_ren_wakeups_5_bits_uop_debug_inst; // @[core.scala:148:30]
wire int_ren_wakeups_5_bits_uop_is_rvc; // @[core.scala:148:30]
wire [39:0] int_ren_wakeups_5_bits_uop_debug_pc; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_5_bits_uop_iq_type; // @[core.scala:148:30]
wire [9:0] int_ren_wakeups_5_bits_uop_fu_code; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_5_bits_uop_iw_state; // @[core.scala:148:30]
wire int_ren_wakeups_5_bits_uop_iw_p1_poisoned; // @[core.scala:148:30]
wire int_ren_wakeups_5_bits_uop_iw_p2_poisoned; // @[core.scala:148:30]
wire int_ren_wakeups_5_bits_uop_is_br; // @[core.scala:148:30]
wire int_ren_wakeups_5_bits_uop_is_jalr; // @[core.scala:148:30]
wire int_ren_wakeups_5_bits_uop_is_jal; // @[core.scala:148:30]
wire int_ren_wakeups_5_bits_uop_is_sfb; // @[core.scala:148:30]
wire [15:0] int_ren_wakeups_5_bits_uop_br_mask; // @[core.scala:148:30]
wire [3:0] int_ren_wakeups_5_bits_uop_br_tag; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_5_bits_uop_ftq_idx; // @[core.scala:148:30]
wire int_ren_wakeups_5_bits_uop_edge_inst; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_5_bits_uop_pc_lob; // @[core.scala:148:30]
wire int_ren_wakeups_5_bits_uop_taken; // @[core.scala:148:30]
wire [19:0] int_ren_wakeups_5_bits_uop_imm_packed; // @[core.scala:148:30]
wire [11:0] int_ren_wakeups_5_bits_uop_csr_addr; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_5_bits_uop_rob_idx; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_5_bits_uop_ldq_idx; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_5_bits_uop_stq_idx; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_5_bits_uop_rxq_idx; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_5_bits_uop_pdst; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_5_bits_uop_prs1; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_5_bits_uop_prs2; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_5_bits_uop_prs3; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_5_bits_uop_ppred; // @[core.scala:148:30]
wire int_ren_wakeups_5_bits_uop_prs1_busy; // @[core.scala:148:30]
wire int_ren_wakeups_5_bits_uop_prs2_busy; // @[core.scala:148:30]
wire int_ren_wakeups_5_bits_uop_prs3_busy; // @[core.scala:148:30]
wire int_ren_wakeups_5_bits_uop_ppred_busy; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_5_bits_uop_stale_pdst; // @[core.scala:148:30]
wire int_ren_wakeups_5_bits_uop_exception; // @[core.scala:148:30]
wire [63:0] int_ren_wakeups_5_bits_uop_exc_cause; // @[core.scala:148:30]
wire int_ren_wakeups_5_bits_uop_bypassable; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_5_bits_uop_mem_cmd; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_5_bits_uop_mem_size; // @[core.scala:148:30]
wire int_ren_wakeups_5_bits_uop_mem_signed; // @[core.scala:148:30]
wire int_ren_wakeups_5_bits_uop_is_fence; // @[core.scala:148:30]
wire int_ren_wakeups_5_bits_uop_is_fencei; // @[core.scala:148:30]
wire int_ren_wakeups_5_bits_uop_is_amo; // @[core.scala:148:30]
wire int_ren_wakeups_5_bits_uop_uses_ldq; // @[core.scala:148:30]
wire int_ren_wakeups_5_bits_uop_uses_stq; // @[core.scala:148:30]
wire int_ren_wakeups_5_bits_uop_is_sys_pc2epc; // @[core.scala:148:30]
wire int_ren_wakeups_5_bits_uop_is_unique; // @[core.scala:148:30]
wire int_ren_wakeups_5_bits_uop_flush_on_commit; // @[core.scala:148:30]
wire int_ren_wakeups_5_bits_uop_ldst_is_rs1; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_5_bits_uop_ldst; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_5_bits_uop_lrs1; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_5_bits_uop_lrs2; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_5_bits_uop_lrs3; // @[core.scala:148:30]
wire int_ren_wakeups_5_bits_uop_ldst_val; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_5_bits_uop_dst_rtype; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_5_bits_uop_lrs1_rtype; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_5_bits_uop_lrs2_rtype; // @[core.scala:148:30]
wire int_ren_wakeups_5_bits_uop_frs3_en; // @[core.scala:148:30]
wire int_ren_wakeups_5_bits_uop_fp_val; // @[core.scala:148:30]
wire int_ren_wakeups_5_bits_uop_fp_single; // @[core.scala:148:30]
wire int_ren_wakeups_5_bits_uop_xcpt_pf_if; // @[core.scala:148:30]
wire int_ren_wakeups_5_bits_uop_xcpt_ae_if; // @[core.scala:148:30]
wire int_ren_wakeups_5_bits_uop_xcpt_ma_if; // @[core.scala:148:30]
wire int_ren_wakeups_5_bits_uop_bp_debug_if; // @[core.scala:148:30]
wire int_ren_wakeups_5_bits_uop_bp_xcpt_if; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_5_bits_uop_debug_fsrc; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_5_bits_uop_debug_tsrc; // @[core.scala:148:30]
wire int_ren_wakeups_5_valid; // @[core.scala:148:30]
wire [3:0] int_ren_wakeups_6_bits_uop_ctrl_br_type; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_6_bits_uop_ctrl_op1_sel; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_6_bits_uop_ctrl_op2_sel; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_6_bits_uop_ctrl_imm_sel; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_6_bits_uop_ctrl_op_fcn; // @[core.scala:148:30]
wire int_ren_wakeups_6_bits_uop_ctrl_fcn_dw; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_6_bits_uop_ctrl_csr_cmd; // @[core.scala:148:30]
wire int_ren_wakeups_6_bits_uop_ctrl_is_load; // @[core.scala:148:30]
wire int_ren_wakeups_6_bits_uop_ctrl_is_sta; // @[core.scala:148:30]
wire int_ren_wakeups_6_bits_uop_ctrl_is_std; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_6_bits_uop_uopc; // @[core.scala:148:30]
wire [31:0] int_ren_wakeups_6_bits_uop_inst; // @[core.scala:148:30]
wire [31:0] int_ren_wakeups_6_bits_uop_debug_inst; // @[core.scala:148:30]
wire int_ren_wakeups_6_bits_uop_is_rvc; // @[core.scala:148:30]
wire [39:0] int_ren_wakeups_6_bits_uop_debug_pc; // @[core.scala:148:30]
wire [2:0] int_ren_wakeups_6_bits_uop_iq_type; // @[core.scala:148:30]
wire [9:0] int_ren_wakeups_6_bits_uop_fu_code; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_6_bits_uop_iw_state; // @[core.scala:148:30]
wire int_ren_wakeups_6_bits_uop_iw_p1_poisoned; // @[core.scala:148:30]
wire int_ren_wakeups_6_bits_uop_iw_p2_poisoned; // @[core.scala:148:30]
wire int_ren_wakeups_6_bits_uop_is_br; // @[core.scala:148:30]
wire int_ren_wakeups_6_bits_uop_is_jalr; // @[core.scala:148:30]
wire int_ren_wakeups_6_bits_uop_is_jal; // @[core.scala:148:30]
wire int_ren_wakeups_6_bits_uop_is_sfb; // @[core.scala:148:30]
wire [15:0] int_ren_wakeups_6_bits_uop_br_mask; // @[core.scala:148:30]
wire [3:0] int_ren_wakeups_6_bits_uop_br_tag; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_6_bits_uop_ftq_idx; // @[core.scala:148:30]
wire int_ren_wakeups_6_bits_uop_edge_inst; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_6_bits_uop_pc_lob; // @[core.scala:148:30]
wire int_ren_wakeups_6_bits_uop_taken; // @[core.scala:148:30]
wire [19:0] int_ren_wakeups_6_bits_uop_imm_packed; // @[core.scala:148:30]
wire [11:0] int_ren_wakeups_6_bits_uop_csr_addr; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_6_bits_uop_rob_idx; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_6_bits_uop_ldq_idx; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_6_bits_uop_stq_idx; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_6_bits_uop_rxq_idx; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_6_bits_uop_pdst; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_6_bits_uop_prs1; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_6_bits_uop_prs2; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_6_bits_uop_prs3; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_6_bits_uop_ppred; // @[core.scala:148:30]
wire int_ren_wakeups_6_bits_uop_prs1_busy; // @[core.scala:148:30]
wire int_ren_wakeups_6_bits_uop_prs2_busy; // @[core.scala:148:30]
wire int_ren_wakeups_6_bits_uop_prs3_busy; // @[core.scala:148:30]
wire int_ren_wakeups_6_bits_uop_ppred_busy; // @[core.scala:148:30]
wire [6:0] int_ren_wakeups_6_bits_uop_stale_pdst; // @[core.scala:148:30]
wire int_ren_wakeups_6_bits_uop_exception; // @[core.scala:148:30]
wire [63:0] int_ren_wakeups_6_bits_uop_exc_cause; // @[core.scala:148:30]
wire int_ren_wakeups_6_bits_uop_bypassable; // @[core.scala:148:30]
wire [4:0] int_ren_wakeups_6_bits_uop_mem_cmd; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_6_bits_uop_mem_size; // @[core.scala:148:30]
wire int_ren_wakeups_6_bits_uop_mem_signed; // @[core.scala:148:30]
wire int_ren_wakeups_6_bits_uop_is_fence; // @[core.scala:148:30]
wire int_ren_wakeups_6_bits_uop_is_fencei; // @[core.scala:148:30]
wire int_ren_wakeups_6_bits_uop_is_amo; // @[core.scala:148:30]
wire int_ren_wakeups_6_bits_uop_uses_ldq; // @[core.scala:148:30]
wire int_ren_wakeups_6_bits_uop_uses_stq; // @[core.scala:148:30]
wire int_ren_wakeups_6_bits_uop_is_sys_pc2epc; // @[core.scala:148:30]
wire int_ren_wakeups_6_bits_uop_is_unique; // @[core.scala:148:30]
wire int_ren_wakeups_6_bits_uop_flush_on_commit; // @[core.scala:148:30]
wire int_ren_wakeups_6_bits_uop_ldst_is_rs1; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_6_bits_uop_ldst; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_6_bits_uop_lrs1; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_6_bits_uop_lrs2; // @[core.scala:148:30]
wire [5:0] int_ren_wakeups_6_bits_uop_lrs3; // @[core.scala:148:30]
wire int_ren_wakeups_6_bits_uop_ldst_val; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_6_bits_uop_dst_rtype; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_6_bits_uop_lrs1_rtype; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_6_bits_uop_lrs2_rtype; // @[core.scala:148:30]
wire int_ren_wakeups_6_bits_uop_frs3_en; // @[core.scala:148:30]
wire int_ren_wakeups_6_bits_uop_fp_val; // @[core.scala:148:30]
wire int_ren_wakeups_6_bits_uop_fp_single; // @[core.scala:148:30]
wire int_ren_wakeups_6_bits_uop_xcpt_pf_if; // @[core.scala:148:30]
wire int_ren_wakeups_6_bits_uop_xcpt_ae_if; // @[core.scala:148:30]
wire int_ren_wakeups_6_bits_uop_xcpt_ma_if; // @[core.scala:148:30]
wire int_ren_wakeups_6_bits_uop_bp_debug_if; // @[core.scala:148:30]
wire int_ren_wakeups_6_bits_uop_bp_xcpt_if; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_6_bits_uop_debug_fsrc; // @[core.scala:148:30]
wire [1:0] int_ren_wakeups_6_bits_uop_debug_tsrc; // @[core.scala:148:30]
wire int_ren_wakeups_6_valid; // @[core.scala:148:30]
wire [6:0] iss_uops_1_uopc; // @[core.scala:173:24]
wire [31:0] iss_uops_1_inst; // @[core.scala:173:24]
wire [31:0] iss_uops_1_debug_inst; // @[core.scala:173:24]
wire iss_uops_1_is_rvc; // @[core.scala:173:24]
wire [39:0] iss_uops_1_debug_pc; // @[core.scala:173:24]
wire [2:0] iss_uops_1_iq_type; // @[core.scala:173:24]
wire [9:0] iss_uops_1_fu_code; // @[core.scala:173:24]
wire [3:0] iss_uops_1_ctrl_br_type; // @[core.scala:173:24]
wire [1:0] iss_uops_1_ctrl_op1_sel; // @[core.scala:173:24]
wire [2:0] iss_uops_1_ctrl_op2_sel; // @[core.scala:173:24]
wire [2:0] iss_uops_1_ctrl_imm_sel; // @[core.scala:173:24]
wire [4:0] iss_uops_1_ctrl_op_fcn; // @[core.scala:173:24]
wire iss_uops_1_ctrl_fcn_dw; // @[core.scala:173:24]
wire [2:0] iss_uops_1_ctrl_csr_cmd; // @[core.scala:173:24]
wire iss_uops_1_ctrl_is_load; // @[core.scala:173:24]
wire iss_uops_1_ctrl_is_sta; // @[core.scala:173:24]
wire iss_uops_1_ctrl_is_std; // @[core.scala:173:24]
wire [1:0] iss_uops_1_iw_state; // @[core.scala:173:24]
wire iss_uops_1_iw_p1_poisoned; // @[core.scala:173:24]
wire iss_uops_1_iw_p2_poisoned; // @[core.scala:173:24]
wire iss_uops_1_is_br; // @[core.scala:173:24]
wire iss_uops_1_is_jalr; // @[core.scala:173:24]
wire iss_uops_1_is_jal; // @[core.scala:173:24]
wire iss_uops_1_is_sfb; // @[core.scala:173:24]
wire [15:0] iss_uops_1_br_mask; // @[core.scala:173:24]
wire [3:0] iss_uops_1_br_tag; // @[core.scala:173:24]
wire [4:0] iss_uops_1_ftq_idx; // @[core.scala:173:24]
wire iss_uops_1_edge_inst; // @[core.scala:173:24]
wire [5:0] iss_uops_1_pc_lob; // @[core.scala:173:24]
wire iss_uops_1_taken; // @[core.scala:173:24]
wire [19:0] iss_uops_1_imm_packed; // @[core.scala:173:24]
wire [11:0] iss_uops_1_csr_addr; // @[core.scala:173:24]
wire [6:0] iss_uops_1_rob_idx; // @[core.scala:173:24]
wire [4:0] iss_uops_1_ldq_idx; // @[core.scala:173:24]
wire [4:0] iss_uops_1_stq_idx; // @[core.scala:173:24]
wire [1:0] iss_uops_1_rxq_idx; // @[core.scala:173:24]
wire [6:0] iss_uops_1_pdst; // @[core.scala:173:24]
wire [6:0] iss_uops_1_prs1; // @[core.scala:173:24]
wire [6:0] iss_uops_1_prs2; // @[core.scala:173:24]
wire [6:0] iss_uops_1_prs3; // @[core.scala:173:24]
wire [4:0] iss_uops_1_ppred; // @[core.scala:173:24]
wire iss_uops_1_prs1_busy; // @[core.scala:173:24]
wire iss_uops_1_prs2_busy; // @[core.scala:173:24]
wire iss_uops_1_prs3_busy; // @[core.scala:173:24]
wire iss_uops_1_ppred_busy; // @[core.scala:173:24]
wire [6:0] iss_uops_1_stale_pdst; // @[core.scala:173:24]
wire iss_uops_1_exception; // @[core.scala:173:24]
wire [63:0] iss_uops_1_exc_cause; // @[core.scala:173:24]
wire iss_uops_1_bypassable; // @[core.scala:173:24]
wire [4:0] iss_uops_1_mem_cmd; // @[core.scala:173:24]
wire [1:0] iss_uops_1_mem_size; // @[core.scala:173:24]
wire iss_uops_1_mem_signed; // @[core.scala:173:24]
wire iss_uops_1_is_fence; // @[core.scala:173:24]
wire iss_uops_1_is_fencei; // @[core.scala:173:24]
wire iss_uops_1_is_amo; // @[core.scala:173:24]
wire iss_uops_1_uses_ldq; // @[core.scala:173:24]
wire iss_uops_1_uses_stq; // @[core.scala:173:24]
wire iss_uops_1_is_sys_pc2epc; // @[core.scala:173:24]
wire iss_uops_1_is_unique; // @[core.scala:173:24]
wire iss_uops_1_flush_on_commit; // @[core.scala:173:24]
wire iss_uops_1_ldst_is_rs1; // @[core.scala:173:24]
wire [5:0] iss_uops_1_ldst; // @[core.scala:173:24]
wire [5:0] iss_uops_1_lrs1; // @[core.scala:173:24]
wire [5:0] iss_uops_1_lrs2; // @[core.scala:173:24]
wire [5:0] iss_uops_1_lrs3; // @[core.scala:173:24]
wire iss_uops_1_ldst_val; // @[core.scala:173:24]
wire [1:0] iss_uops_1_dst_rtype; // @[core.scala:173:24]
wire [1:0] iss_uops_1_lrs1_rtype; // @[core.scala:173:24]
wire [1:0] iss_uops_1_lrs2_rtype; // @[core.scala:173:24]
wire iss_uops_1_frs3_en; // @[core.scala:173:24]
wire iss_uops_1_fp_val; // @[core.scala:173:24]
wire iss_uops_1_fp_single; // @[core.scala:173:24]
wire iss_uops_1_xcpt_pf_if; // @[core.scala:173:24]
wire iss_uops_1_xcpt_ae_if; // @[core.scala:173:24]
wire iss_uops_1_xcpt_ma_if; // @[core.scala:173:24]
wire iss_uops_1_bp_debug_if; // @[core.scala:173:24]
wire iss_uops_1_bp_xcpt_if; // @[core.scala:173:24]
wire [1:0] iss_uops_1_debug_fsrc; // @[core.scala:173:24]
wire [1:0] iss_uops_1_debug_tsrc; // @[core.scala:173:24]
wire [3:0] pred_wakeup_bits_uop_ctrl_br_type; // @[core.scala:149:26]
wire [1:0] pred_wakeup_bits_uop_ctrl_op1_sel; // @[core.scala:149:26]
wire [2:0] pred_wakeup_bits_uop_ctrl_op2_sel; // @[core.scala:149:26]
wire [2:0] pred_wakeup_bits_uop_ctrl_imm_sel; // @[core.scala:149:26]
wire [4:0] pred_wakeup_bits_uop_ctrl_op_fcn; // @[core.scala:149:26]
wire pred_wakeup_bits_uop_ctrl_fcn_dw; // @[core.scala:149:26]
wire [2:0] pred_wakeup_bits_uop_ctrl_csr_cmd; // @[core.scala:149:26]
wire pred_wakeup_bits_uop_ctrl_is_load; // @[core.scala:149:26]
wire pred_wakeup_bits_uop_ctrl_is_sta; // @[core.scala:149:26]
wire pred_wakeup_bits_uop_ctrl_is_std; // @[core.scala:149:26]
wire [6:0] pred_wakeup_bits_uop_uopc; // @[core.scala:149:26]
wire [31:0] pred_wakeup_bits_uop_inst; // @[core.scala:149:26]
wire [31:0] pred_wakeup_bits_uop_debug_inst; // @[core.scala:149:26]
wire pred_wakeup_bits_uop_is_rvc; // @[core.scala:149:26]
wire [39:0] pred_wakeup_bits_uop_debug_pc; // @[core.scala:149:26]
wire [2:0] pred_wakeup_bits_uop_iq_type; // @[core.scala:149:26]
wire [9:0] pred_wakeup_bits_uop_fu_code; // @[core.scala:149:26]
wire [1:0] pred_wakeup_bits_uop_iw_state; // @[core.scala:149:26]
wire pred_wakeup_bits_uop_iw_p1_poisoned; // @[core.scala:149:26]
wire pred_wakeup_bits_uop_iw_p2_poisoned; // @[core.scala:149:26]
wire pred_wakeup_bits_uop_is_br; // @[core.scala:149:26]
wire pred_wakeup_bits_uop_is_jalr; // @[core.scala:149:26]
wire pred_wakeup_bits_uop_is_jal; // @[core.scala:149:26]
wire pred_wakeup_bits_uop_is_sfb; // @[core.scala:149:26]
wire [15:0] pred_wakeup_bits_uop_br_mask; // @[core.scala:149:26]
wire [3:0] pred_wakeup_bits_uop_br_tag; // @[core.scala:149:26]
wire [4:0] pred_wakeup_bits_uop_ftq_idx; // @[core.scala:149:26]
wire pred_wakeup_bits_uop_edge_inst; // @[core.scala:149:26]
wire [5:0] pred_wakeup_bits_uop_pc_lob; // @[core.scala:149:26]
wire pred_wakeup_bits_uop_taken; // @[core.scala:149:26]
wire [19:0] pred_wakeup_bits_uop_imm_packed; // @[core.scala:149:26]
wire [11:0] pred_wakeup_bits_uop_csr_addr; // @[core.scala:149:26]
wire [6:0] pred_wakeup_bits_uop_rob_idx; // @[core.scala:149:26]
wire [4:0] pred_wakeup_bits_uop_ldq_idx; // @[core.scala:149:26]
wire [4:0] pred_wakeup_bits_uop_stq_idx; // @[core.scala:149:26]
wire [1:0] pred_wakeup_bits_uop_rxq_idx; // @[core.scala:149:26]
wire [6:0] pred_wakeup_bits_uop_pdst; // @[core.scala:149:26]
wire [6:0] pred_wakeup_bits_uop_prs1; // @[core.scala:149:26]
wire [6:0] pred_wakeup_bits_uop_prs2; // @[core.scala:149:26]
wire [6:0] pred_wakeup_bits_uop_prs3; // @[core.scala:149:26]
wire [4:0] pred_wakeup_bits_uop_ppred; // @[core.scala:149:26]
wire pred_wakeup_bits_uop_prs1_busy; // @[core.scala:149:26]
wire pred_wakeup_bits_uop_prs2_busy; // @[core.scala:149:26]
wire pred_wakeup_bits_uop_prs3_busy; // @[core.scala:149:26]
wire pred_wakeup_bits_uop_ppred_busy; // @[core.scala:149:26]
wire [6:0] pred_wakeup_bits_uop_stale_pdst; // @[core.scala:149:26]
wire pred_wakeup_bits_uop_exception; // @[core.scala:149:26]
wire [63:0] pred_wakeup_bits_uop_exc_cause; // @[core.scala:149:26]
wire pred_wakeup_bits_uop_bypassable; // @[core.scala:149:26]
wire [4:0] pred_wakeup_bits_uop_mem_cmd; // @[core.scala:149:26]
wire [1:0] pred_wakeup_bits_uop_mem_size; // @[core.scala:149:26]
wire pred_wakeup_bits_uop_mem_signed; // @[core.scala:149:26]
wire pred_wakeup_bits_uop_is_fence; // @[core.scala:149:26]
wire pred_wakeup_bits_uop_is_fencei; // @[core.scala:149:26]
wire pred_wakeup_bits_uop_is_amo; // @[core.scala:149:26]
wire pred_wakeup_bits_uop_uses_ldq; // @[core.scala:149:26]
wire pred_wakeup_bits_uop_uses_stq; // @[core.scala:149:26]
wire pred_wakeup_bits_uop_is_sys_pc2epc; // @[core.scala:149:26]
wire pred_wakeup_bits_uop_is_unique; // @[core.scala:149:26]
wire pred_wakeup_bits_uop_flush_on_commit; // @[core.scala:149:26]
wire pred_wakeup_bits_uop_ldst_is_rs1; // @[core.scala:149:26]
wire [5:0] pred_wakeup_bits_uop_ldst; // @[core.scala:149:26]
wire [5:0] pred_wakeup_bits_uop_lrs1; // @[core.scala:149:26]
wire [5:0] pred_wakeup_bits_uop_lrs2; // @[core.scala:149:26]
wire [5:0] pred_wakeup_bits_uop_lrs3; // @[core.scala:149:26]
wire pred_wakeup_bits_uop_ldst_val; // @[core.scala:149:26]
wire [1:0] pred_wakeup_bits_uop_dst_rtype; // @[core.scala:149:26]
wire [1:0] pred_wakeup_bits_uop_lrs1_rtype; // @[core.scala:149:26]
wire [1:0] pred_wakeup_bits_uop_lrs2_rtype; // @[core.scala:149:26]
wire pred_wakeup_bits_uop_frs3_en; // @[core.scala:149:26]
wire pred_wakeup_bits_uop_fp_val; // @[core.scala:149:26]
wire pred_wakeup_bits_uop_fp_single; // @[core.scala:149:26]
wire pred_wakeup_bits_uop_xcpt_pf_if; // @[core.scala:149:26]
wire pred_wakeup_bits_uop_xcpt_ae_if; // @[core.scala:149:26]
wire pred_wakeup_bits_uop_xcpt_ma_if; // @[core.scala:149:26]
wire pred_wakeup_bits_uop_bp_debug_if; // @[core.scala:149:26]
wire pred_wakeup_bits_uop_bp_xcpt_if; // @[core.scala:149:26]
wire [1:0] pred_wakeup_bits_uop_debug_fsrc; // @[core.scala:149:26]
wire [1:0] pred_wakeup_bits_uop_debug_tsrc; // @[core.scala:149:26]
wire _dec_valids_0_T_3; // @[core.scala:508:97]
wire _dec_valids_1_T_3; // @[core.scala:508:97]
wire _dec_valids_2_T_3; // @[core.scala:508:97]
wire dec_valids_0; // @[core.scala:157:24]
wire dec_valids_1; // @[core.scala:157:24]
wire dec_valids_2; // @[core.scala:157:24]
wire [6:0] dec_uops_0_uopc; // @[core.scala:158:24]
wire [31:0] dec_uops_0_inst; // @[core.scala:158:24]
wire [31:0] dec_uops_0_debug_inst; // @[core.scala:158:24]
wire dec_uops_0_is_rvc; // @[core.scala:158:24]
wire [39:0] dec_uops_0_debug_pc; // @[core.scala:158:24]
wire [2:0] dec_uops_0_iq_type; // @[core.scala:158:24]
wire [9:0] dec_uops_0_fu_code; // @[core.scala:158:24]
wire dec_uops_0_is_br; // @[core.scala:158:24]
wire dec_uops_0_is_jalr; // @[core.scala:158:24]
wire dec_uops_0_is_jal; // @[core.scala:158:24]
wire dec_uops_0_is_sfb; // @[core.scala:158:24]
wire [15:0] dec_uops_0_br_mask; // @[core.scala:158:24]
wire [3:0] dec_uops_0_br_tag; // @[core.scala:158:24]
wire [4:0] dec_uops_0_ftq_idx; // @[core.scala:158:24]
wire dec_uops_0_edge_inst; // @[core.scala:158:24]
wire [5:0] dec_uops_0_pc_lob; // @[core.scala:158:24]
wire dec_uops_0_taken; // @[core.scala:158:24]
wire [19:0] dec_uops_0_imm_packed; // @[core.scala:158:24]
wire dec_uops_0_exception; // @[core.scala:158:24]
wire [63:0] dec_uops_0_exc_cause; // @[core.scala:158:24]
wire dec_uops_0_bypassable; // @[core.scala:158:24]
wire [4:0] dec_uops_0_mem_cmd; // @[core.scala:158:24]
wire [1:0] dec_uops_0_mem_size; // @[core.scala:158:24]
wire dec_uops_0_mem_signed; // @[core.scala:158:24]
wire dec_uops_0_is_fence; // @[core.scala:158:24]
wire dec_uops_0_is_fencei; // @[core.scala:158:24]
wire dec_uops_0_is_amo; // @[core.scala:158:24]
wire dec_uops_0_uses_ldq; // @[core.scala:158:24]
wire dec_uops_0_uses_stq; // @[core.scala:158:24]
wire dec_uops_0_is_sys_pc2epc; // @[core.scala:158:24]
wire dec_uops_0_is_unique; // @[core.scala:158:24]
wire dec_uops_0_flush_on_commit; // @[core.scala:158:24]
wire [5:0] dec_uops_0_ldst; // @[core.scala:158:24]
wire [5:0] dec_uops_0_lrs1; // @[core.scala:158:24]
wire [5:0] dec_uops_0_lrs2; // @[core.scala:158:24]
wire [5:0] dec_uops_0_lrs3; // @[core.scala:158:24]
wire dec_uops_0_ldst_val; // @[core.scala:158:24]
wire [1:0] dec_uops_0_dst_rtype; // @[core.scala:158:24]
wire [1:0] dec_uops_0_lrs1_rtype; // @[core.scala:158:24]
wire [1:0] dec_uops_0_lrs2_rtype; // @[core.scala:158:24]
wire dec_uops_0_frs3_en; // @[core.scala:158:24]
wire dec_uops_0_fp_val; // @[core.scala:158:24]
wire dec_uops_0_fp_single; // @[core.scala:158:24]
wire dec_uops_0_xcpt_pf_if; // @[core.scala:158:24]
wire dec_uops_0_xcpt_ae_if; // @[core.scala:158:24]
wire dec_uops_0_bp_debug_if; // @[core.scala:158:24]
wire dec_uops_0_bp_xcpt_if; // @[core.scala:158:24]
wire [1:0] dec_uops_0_debug_fsrc; // @[core.scala:158:24]
wire [6:0] dec_uops_1_uopc; // @[core.scala:158:24]
wire [31:0] dec_uops_1_inst; // @[core.scala:158:24]
wire [31:0] dec_uops_1_debug_inst; // @[core.scala:158:24]
wire dec_uops_1_is_rvc; // @[core.scala:158:24]
wire [39:0] dec_uops_1_debug_pc; // @[core.scala:158:24]
wire [2:0] dec_uops_1_iq_type; // @[core.scala:158:24]
wire [9:0] dec_uops_1_fu_code; // @[core.scala:158:24]
wire dec_uops_1_is_br; // @[core.scala:158:24]
wire dec_uops_1_is_jalr; // @[core.scala:158:24]
wire dec_uops_1_is_jal; // @[core.scala:158:24]
wire dec_uops_1_is_sfb; // @[core.scala:158:24]
wire [15:0] dec_uops_1_br_mask; // @[core.scala:158:24]
wire [3:0] dec_uops_1_br_tag; // @[core.scala:158:24]
wire [4:0] dec_uops_1_ftq_idx; // @[core.scala:158:24]
wire dec_uops_1_edge_inst; // @[core.scala:158:24]
wire [5:0] dec_uops_1_pc_lob; // @[core.scala:158:24]
wire dec_uops_1_taken; // @[core.scala:158:24]
wire [19:0] dec_uops_1_imm_packed; // @[core.scala:158:24]
wire dec_uops_1_exception; // @[core.scala:158:24]
wire [63:0] dec_uops_1_exc_cause; // @[core.scala:158:24]
wire dec_uops_1_bypassable; // @[core.scala:158:24]
wire [4:0] dec_uops_1_mem_cmd; // @[core.scala:158:24]
wire [1:0] dec_uops_1_mem_size; // @[core.scala:158:24]
wire dec_uops_1_mem_signed; // @[core.scala:158:24]
wire dec_uops_1_is_fence; // @[core.scala:158:24]
wire dec_uops_1_is_fencei; // @[core.scala:158:24]
wire dec_uops_1_is_amo; // @[core.scala:158:24]
wire dec_uops_1_uses_ldq; // @[core.scala:158:24]
wire dec_uops_1_uses_stq; // @[core.scala:158:24]
wire dec_uops_1_is_sys_pc2epc; // @[core.scala:158:24]
wire dec_uops_1_is_unique; // @[core.scala:158:24]
wire dec_uops_1_flush_on_commit; // @[core.scala:158:24]
wire [5:0] dec_uops_1_ldst; // @[core.scala:158:24]
wire [5:0] dec_uops_1_lrs1; // @[core.scala:158:24]
wire [5:0] dec_uops_1_lrs2; // @[core.scala:158:24]
wire [5:0] dec_uops_1_lrs3; // @[core.scala:158:24]
wire dec_uops_1_ldst_val; // @[core.scala:158:24]
wire [1:0] dec_uops_1_dst_rtype; // @[core.scala:158:24]
wire [1:0] dec_uops_1_lrs1_rtype; // @[core.scala:158:24]
wire [1:0] dec_uops_1_lrs2_rtype; // @[core.scala:158:24]
wire dec_uops_1_frs3_en; // @[core.scala:158:24]
wire dec_uops_1_fp_val; // @[core.scala:158:24]
wire dec_uops_1_fp_single; // @[core.scala:158:24]
wire dec_uops_1_xcpt_pf_if; // @[core.scala:158:24]
wire dec_uops_1_xcpt_ae_if; // @[core.scala:158:24]
wire dec_uops_1_bp_debug_if; // @[core.scala:158:24]
wire dec_uops_1_bp_xcpt_if; // @[core.scala:158:24]
wire [1:0] dec_uops_1_debug_fsrc; // @[core.scala:158:24]
wire [6:0] dec_uops_2_uopc; // @[core.scala:158:24]
wire [31:0] dec_uops_2_inst; // @[core.scala:158:24]
wire [31:0] dec_uops_2_debug_inst; // @[core.scala:158:24]
wire dec_uops_2_is_rvc; // @[core.scala:158:24]
wire [39:0] dec_uops_2_debug_pc; // @[core.scala:158:24]
wire [2:0] dec_uops_2_iq_type; // @[core.scala:158:24]
wire [9:0] dec_uops_2_fu_code; // @[core.scala:158:24]
wire dec_uops_2_is_br; // @[core.scala:158:24]
wire dec_uops_2_is_jalr; // @[core.scala:158:24]
wire dec_uops_2_is_jal; // @[core.scala:158:24]
wire dec_uops_2_is_sfb; // @[core.scala:158:24]
wire [15:0] dec_uops_2_br_mask; // @[core.scala:158:24]
wire [3:0] dec_uops_2_br_tag; // @[core.scala:158:24]
wire [4:0] dec_uops_2_ftq_idx; // @[core.scala:158:24]
wire dec_uops_2_edge_inst; // @[core.scala:158:24]
wire [5:0] dec_uops_2_pc_lob; // @[core.scala:158:24]
wire dec_uops_2_taken; // @[core.scala:158:24]
wire [19:0] dec_uops_2_imm_packed; // @[core.scala:158:24]
wire dec_uops_2_exception; // @[core.scala:158:24]
wire [63:0] dec_uops_2_exc_cause; // @[core.scala:158:24]
wire dec_uops_2_bypassable; // @[core.scala:158:24]
wire [4:0] dec_uops_2_mem_cmd; // @[core.scala:158:24]
wire [1:0] dec_uops_2_mem_size; // @[core.scala:158:24]
wire dec_uops_2_mem_signed; // @[core.scala:158:24]
wire dec_uops_2_is_fence; // @[core.scala:158:24]
wire dec_uops_2_is_fencei; // @[core.scala:158:24]
wire dec_uops_2_is_amo; // @[core.scala:158:24]
wire dec_uops_2_uses_ldq; // @[core.scala:158:24]
wire dec_uops_2_uses_stq; // @[core.scala:158:24]
wire dec_uops_2_is_sys_pc2epc; // @[core.scala:158:24]
wire dec_uops_2_is_unique; // @[core.scala:158:24]
wire dec_uops_2_flush_on_commit; // @[core.scala:158:24]
wire [5:0] dec_uops_2_ldst; // @[core.scala:158:24]
wire [5:0] dec_uops_2_lrs1; // @[core.scala:158:24]
wire [5:0] dec_uops_2_lrs2; // @[core.scala:158:24]
wire [5:0] dec_uops_2_lrs3; // @[core.scala:158:24]
wire dec_uops_2_ldst_val; // @[core.scala:158:24]
wire [1:0] dec_uops_2_dst_rtype; // @[core.scala:158:24]
wire [1:0] dec_uops_2_lrs1_rtype; // @[core.scala:158:24]
wire [1:0] dec_uops_2_lrs2_rtype; // @[core.scala:158:24]
wire dec_uops_2_frs3_en; // @[core.scala:158:24]
wire dec_uops_2_fp_val; // @[core.scala:158:24]
wire dec_uops_2_fp_single; // @[core.scala:158:24]
wire dec_uops_2_xcpt_pf_if; // @[core.scala:158:24]
wire dec_uops_2_xcpt_ae_if; // @[core.scala:158:24]
wire dec_uops_2_bp_debug_if; // @[core.scala:158:24]
wire dec_uops_2_bp_xcpt_if; // @[core.scala:158:24]
wire [1:0] dec_uops_2_debug_fsrc; // @[core.scala:158:24]
wire dec_fire_0; // @[core.scala:159:24]
wire dec_fire_1; // @[core.scala:159:24]
wire dec_fire_2; // @[core.scala:159:24]
assign dec_ready = dec_fire_2; // @[core.scala:159:24, :161:24]
assign io_ifu_fetchpacket_ready_0 = dec_ready; // @[core.scala:51:7, :161:24]
wire dec_xcpts_0; // @[core.scala:162:24]
wire dec_xcpts_1; // @[core.scala:162:24]
wire dec_xcpts_2; // @[core.scala:162:24]
wire _ren_stalls_0_T_1; // @[core.scala:671:63]
wire _ren_stalls_1_T_1; // @[core.scala:671:63]
wire _ren_stalls_2_T_1; // @[core.scala:671:63]
wire ren_stalls_0; // @[core.scala:163:24]
wire ren_stalls_1; // @[core.scala:163:24]
wire ren_stalls_2; // @[core.scala:163:24]
wire dis_prior_slot_valid_1 = dis_valids_0; // @[core.scala:166:24, :683:71]
wire dis_valids_1; // @[core.scala:166:24]
wire dis_valids_2; // @[core.scala:166:24]
assign io_lsu_dis_uops_0_bits_uopc_0 = dis_uops_0_uopc; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_inst_0 = dis_uops_0_inst; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_debug_inst_0 = dis_uops_0_debug_inst; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_is_rvc_0 = dis_uops_0_is_rvc; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_debug_pc_0 = dis_uops_0_debug_pc; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_iq_type_0 = dis_uops_0_iq_type; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_fu_code_0 = dis_uops_0_fu_code; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_ctrl_br_type_0 = dis_uops_0_ctrl_br_type; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_ctrl_op1_sel_0 = dis_uops_0_ctrl_op1_sel; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_ctrl_op2_sel_0 = dis_uops_0_ctrl_op2_sel; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_ctrl_imm_sel_0 = dis_uops_0_ctrl_imm_sel; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_ctrl_op_fcn_0 = dis_uops_0_ctrl_op_fcn; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_ctrl_fcn_dw_0 = dis_uops_0_ctrl_fcn_dw; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_ctrl_csr_cmd_0 = dis_uops_0_ctrl_csr_cmd; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_ctrl_is_load_0 = dis_uops_0_ctrl_is_load; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_ctrl_is_sta_0 = dis_uops_0_ctrl_is_sta; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_ctrl_is_std_0 = dis_uops_0_ctrl_is_std; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_iw_state_0 = dis_uops_0_iw_state; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_iw_p1_poisoned_0 = dis_uops_0_iw_p1_poisoned; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_iw_p2_poisoned_0 = dis_uops_0_iw_p2_poisoned; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_is_br_0 = dis_uops_0_is_br; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_is_jalr_0 = dis_uops_0_is_jalr; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_is_jal_0 = dis_uops_0_is_jal; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_is_sfb_0 = dis_uops_0_is_sfb; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_br_mask_0 = dis_uops_0_br_mask; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_br_tag_0 = dis_uops_0_br_tag; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_ftq_idx_0 = dis_uops_0_ftq_idx; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_edge_inst_0 = dis_uops_0_edge_inst; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_pc_lob_0 = dis_uops_0_pc_lob; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_taken_0 = dis_uops_0_taken; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_imm_packed_0 = dis_uops_0_imm_packed; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_csr_addr_0 = dis_uops_0_csr_addr; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_rob_idx_0 = dis_uops_0_rob_idx; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_ldq_idx_0 = dis_uops_0_ldq_idx; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_stq_idx_0 = dis_uops_0_stq_idx; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_rxq_idx_0 = dis_uops_0_rxq_idx; // @[core.scala:51:7, :167:24]
wire [6:0] _dis_uops_0_pdst_T_3; // @[core.scala:659:28]
assign io_lsu_dis_uops_0_bits_pdst_0 = dis_uops_0_pdst; // @[core.scala:51:7, :167:24]
wire [6:0] _dis_uops_0_prs1_T_3; // @[core.scala:654:28]
assign io_lsu_dis_uops_0_bits_prs1_0 = dis_uops_0_prs1; // @[core.scala:51:7, :167:24]
wire [6:0] _dis_uops_0_prs2_T_1; // @[core.scala:656:28]
assign io_lsu_dis_uops_0_bits_prs2_0 = dis_uops_0_prs2; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_prs3_0 = dis_uops_0_prs3; // @[core.scala:51:7, :167:24]
wire _dis_uops_0_prs1_busy_T_4; // @[core.scala:664:85]
assign io_lsu_dis_uops_0_bits_prs1_busy_0 = dis_uops_0_prs1_busy; // @[core.scala:51:7, :167:24]
wire _dis_uops_0_prs2_busy_T_4; // @[core.scala:666:85]
assign io_lsu_dis_uops_0_bits_prs2_busy_0 = dis_uops_0_prs2_busy; // @[core.scala:51:7, :167:24]
wire _dis_uops_0_prs3_busy_T; // @[core.scala:668:46]
assign io_lsu_dis_uops_0_bits_prs3_busy_0 = dis_uops_0_prs3_busy; // @[core.scala:51:7, :167:24]
wire [6:0] _dis_uops_0_stale_pdst_T_1; // @[core.scala:662:34]
assign io_lsu_dis_uops_0_bits_stale_pdst_0 = dis_uops_0_stale_pdst; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_exception_0 = dis_uops_0_exception; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_exc_cause_0 = dis_uops_0_exc_cause; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_bypassable_0 = dis_uops_0_bypassable; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_mem_cmd_0 = dis_uops_0_mem_cmd; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_mem_size_0 = dis_uops_0_mem_size; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_mem_signed_0 = dis_uops_0_mem_signed; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_is_fence_0 = dis_uops_0_is_fence; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_is_fencei_0 = dis_uops_0_is_fencei; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_is_amo_0 = dis_uops_0_is_amo; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_uses_ldq_0 = dis_uops_0_uses_ldq; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_uses_stq_0 = dis_uops_0_uses_stq; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_is_sys_pc2epc_0 = dis_uops_0_is_sys_pc2epc; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_is_unique_0 = dis_uops_0_is_unique; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_flush_on_commit_0 = dis_uops_0_flush_on_commit; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_ldst_is_rs1_0 = dis_uops_0_ldst_is_rs1; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_ldst_0 = dis_uops_0_ldst; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_lrs1_0 = dis_uops_0_lrs1; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_lrs2_0 = dis_uops_0_lrs2; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_lrs3_0 = dis_uops_0_lrs3; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_ldst_val_0 = dis_uops_0_ldst_val; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_dst_rtype_0 = dis_uops_0_dst_rtype; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_lrs1_rtype_0 = dis_uops_0_lrs1_rtype; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_lrs2_rtype_0 = dis_uops_0_lrs2_rtype; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_frs3_en_0 = dis_uops_0_frs3_en; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_fp_val_0 = dis_uops_0_fp_val; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_fp_single_0 = dis_uops_0_fp_single; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_xcpt_pf_if_0 = dis_uops_0_xcpt_pf_if; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_xcpt_ae_if_0 = dis_uops_0_xcpt_ae_if; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_xcpt_ma_if_0 = dis_uops_0_xcpt_ma_if; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_bp_debug_if_0 = dis_uops_0_bp_debug_if; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_bp_xcpt_if_0 = dis_uops_0_bp_xcpt_if; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_debug_fsrc_0 = dis_uops_0_debug_fsrc; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_bits_debug_tsrc_0 = dis_uops_0_debug_tsrc; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_1_bits_uopc_0 = dis_uops_1_uopc; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_1_bits_inst_0 = dis_uops_1_inst; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_1_bits_debug_inst_0 = dis_uops_1_debug_inst; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_1_bits_is_rvc_0 = dis_uops_1_is_rvc; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_1_bits_debug_pc_0 = dis_uops_1_debug_pc; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_1_bits_iq_type_0 = dis_uops_1_iq_type; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_1_bits_fu_code_0 = dis_uops_1_fu_code; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_1_bits_ctrl_br_type_0 = dis_uops_1_ctrl_br_type; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_1_bits_ctrl_op1_sel_0 = dis_uops_1_ctrl_op1_sel; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_1_bits_ctrl_op2_sel_0 = dis_uops_1_ctrl_op2_sel; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_1_bits_ctrl_imm_sel_0 = dis_uops_1_ctrl_imm_sel; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_1_bits_ctrl_op_fcn_0 = dis_uops_1_ctrl_op_fcn; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_1_bits_ctrl_fcn_dw_0 = dis_uops_1_ctrl_fcn_dw; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_1_bits_ctrl_csr_cmd_0 = dis_uops_1_ctrl_csr_cmd; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_1_bits_ctrl_is_load_0 = dis_uops_1_ctrl_is_load; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_1_bits_ctrl_is_sta_0 = dis_uops_1_ctrl_is_sta; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_1_bits_ctrl_is_std_0 = dis_uops_1_ctrl_is_std; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_1_bits_iw_state_0 = dis_uops_1_iw_state; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_1_bits_iw_p1_poisoned_0 = dis_uops_1_iw_p1_poisoned; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_1_bits_iw_p2_poisoned_0 = dis_uops_1_iw_p2_poisoned; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_1_bits_is_br_0 = dis_uops_1_is_br; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_1_bits_is_jalr_0 = dis_uops_1_is_jalr; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_1_bits_is_jal_0 = dis_uops_1_is_jal; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_1_bits_is_sfb_0 = dis_uops_1_is_sfb; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_1_bits_br_mask_0 = dis_uops_1_br_mask; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_1_bits_br_tag_0 = dis_uops_1_br_tag; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_1_bits_ftq_idx_0 = dis_uops_1_ftq_idx; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_1_bits_edge_inst_0 = dis_uops_1_edge_inst; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_1_bits_pc_lob_0 = dis_uops_1_pc_lob; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_1_bits_taken_0 = dis_uops_1_taken; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_1_bits_imm_packed_0 = dis_uops_1_imm_packed; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_1_bits_csr_addr_0 = dis_uops_1_csr_addr; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_1_bits_rob_idx_0 = dis_uops_1_rob_idx; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_1_bits_ldq_idx_0 = dis_uops_1_ldq_idx; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_1_bits_stq_idx_0 = dis_uops_1_stq_idx; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_1_bits_rxq_idx_0 = dis_uops_1_rxq_idx; // @[core.scala:51:7, :167:24]
wire [6:0] _dis_uops_1_pdst_T_3; // @[core.scala:659:28]
assign io_lsu_dis_uops_1_bits_pdst_0 = dis_uops_1_pdst; // @[core.scala:51:7, :167:24]
wire [6:0] _dis_uops_1_prs1_T_3; // @[core.scala:654:28]
assign io_lsu_dis_uops_1_bits_prs1_0 = dis_uops_1_prs1; // @[core.scala:51:7, :167:24]
wire [6:0] _dis_uops_1_prs2_T_1; // @[core.scala:656:28]
assign io_lsu_dis_uops_1_bits_prs2_0 = dis_uops_1_prs2; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_1_bits_prs3_0 = dis_uops_1_prs3; // @[core.scala:51:7, :167:24]
wire _dis_uops_1_prs1_busy_T_4; // @[core.scala:664:85]
assign io_lsu_dis_uops_1_bits_prs1_busy_0 = dis_uops_1_prs1_busy; // @[core.scala:51:7, :167:24]
wire _dis_uops_1_prs2_busy_T_4; // @[core.scala:666:85]
assign io_lsu_dis_uops_1_bits_prs2_busy_0 = dis_uops_1_prs2_busy; // @[core.scala:51:7, :167:24]
wire _dis_uops_1_prs3_busy_T; // @[core.scala:668:46]
assign io_lsu_dis_uops_1_bits_prs3_busy_0 = dis_uops_1_prs3_busy; // @[core.scala:51:7, :167:24]
wire [6:0] _dis_uops_1_stale_pdst_T_1; // @[core.scala:662:34]
assign io_lsu_dis_uops_1_bits_stale_pdst_0 = dis_uops_1_stale_pdst; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_1_bits_exception_0 = dis_uops_1_exception; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_1_bits_exc_cause_0 = dis_uops_1_exc_cause; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_1_bits_bypassable_0 = dis_uops_1_bypassable; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_1_bits_mem_cmd_0 = dis_uops_1_mem_cmd; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_1_bits_mem_size_0 = dis_uops_1_mem_size; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_1_bits_mem_signed_0 = dis_uops_1_mem_signed; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_1_bits_is_fence_0 = dis_uops_1_is_fence; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_1_bits_is_fencei_0 = dis_uops_1_is_fencei; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_1_bits_is_amo_0 = dis_uops_1_is_amo; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_1_bits_uses_ldq_0 = dis_uops_1_uses_ldq; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_1_bits_uses_stq_0 = dis_uops_1_uses_stq; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_1_bits_is_sys_pc2epc_0 = dis_uops_1_is_sys_pc2epc; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_1_bits_is_unique_0 = dis_uops_1_is_unique; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_1_bits_flush_on_commit_0 = dis_uops_1_flush_on_commit; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_1_bits_ldst_is_rs1_0 = dis_uops_1_ldst_is_rs1; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_1_bits_ldst_0 = dis_uops_1_ldst; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_1_bits_lrs1_0 = dis_uops_1_lrs1; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_1_bits_lrs2_0 = dis_uops_1_lrs2; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_1_bits_lrs3_0 = dis_uops_1_lrs3; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_1_bits_ldst_val_0 = dis_uops_1_ldst_val; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_1_bits_dst_rtype_0 = dis_uops_1_dst_rtype; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_1_bits_lrs1_rtype_0 = dis_uops_1_lrs1_rtype; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_1_bits_lrs2_rtype_0 = dis_uops_1_lrs2_rtype; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_1_bits_frs3_en_0 = dis_uops_1_frs3_en; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_1_bits_fp_val_0 = dis_uops_1_fp_val; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_1_bits_fp_single_0 = dis_uops_1_fp_single; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_1_bits_xcpt_pf_if_0 = dis_uops_1_xcpt_pf_if; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_1_bits_xcpt_ae_if_0 = dis_uops_1_xcpt_ae_if; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_1_bits_xcpt_ma_if_0 = dis_uops_1_xcpt_ma_if; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_1_bits_bp_debug_if_0 = dis_uops_1_bp_debug_if; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_1_bits_bp_xcpt_if_0 = dis_uops_1_bp_xcpt_if; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_1_bits_debug_fsrc_0 = dis_uops_1_debug_fsrc; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_1_bits_debug_tsrc_0 = dis_uops_1_debug_tsrc; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_2_bits_uopc_0 = dis_uops_2_uopc; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_2_bits_inst_0 = dis_uops_2_inst; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_2_bits_debug_inst_0 = dis_uops_2_debug_inst; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_2_bits_is_rvc_0 = dis_uops_2_is_rvc; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_2_bits_debug_pc_0 = dis_uops_2_debug_pc; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_2_bits_iq_type_0 = dis_uops_2_iq_type; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_2_bits_fu_code_0 = dis_uops_2_fu_code; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_2_bits_ctrl_br_type_0 = dis_uops_2_ctrl_br_type; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_2_bits_ctrl_op1_sel_0 = dis_uops_2_ctrl_op1_sel; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_2_bits_ctrl_op2_sel_0 = dis_uops_2_ctrl_op2_sel; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_2_bits_ctrl_imm_sel_0 = dis_uops_2_ctrl_imm_sel; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_2_bits_ctrl_op_fcn_0 = dis_uops_2_ctrl_op_fcn; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_2_bits_ctrl_fcn_dw_0 = dis_uops_2_ctrl_fcn_dw; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_2_bits_ctrl_csr_cmd_0 = dis_uops_2_ctrl_csr_cmd; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_2_bits_ctrl_is_load_0 = dis_uops_2_ctrl_is_load; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_2_bits_ctrl_is_sta_0 = dis_uops_2_ctrl_is_sta; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_2_bits_ctrl_is_std_0 = dis_uops_2_ctrl_is_std; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_2_bits_iw_state_0 = dis_uops_2_iw_state; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_2_bits_iw_p1_poisoned_0 = dis_uops_2_iw_p1_poisoned; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_2_bits_iw_p2_poisoned_0 = dis_uops_2_iw_p2_poisoned; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_2_bits_is_br_0 = dis_uops_2_is_br; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_2_bits_is_jalr_0 = dis_uops_2_is_jalr; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_2_bits_is_jal_0 = dis_uops_2_is_jal; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_2_bits_is_sfb_0 = dis_uops_2_is_sfb; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_2_bits_br_mask_0 = dis_uops_2_br_mask; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_2_bits_br_tag_0 = dis_uops_2_br_tag; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_2_bits_ftq_idx_0 = dis_uops_2_ftq_idx; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_2_bits_edge_inst_0 = dis_uops_2_edge_inst; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_2_bits_pc_lob_0 = dis_uops_2_pc_lob; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_2_bits_taken_0 = dis_uops_2_taken; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_2_bits_imm_packed_0 = dis_uops_2_imm_packed; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_2_bits_csr_addr_0 = dis_uops_2_csr_addr; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_2_bits_rob_idx_0 = dis_uops_2_rob_idx; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_2_bits_ldq_idx_0 = dis_uops_2_ldq_idx; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_2_bits_stq_idx_0 = dis_uops_2_stq_idx; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_2_bits_rxq_idx_0 = dis_uops_2_rxq_idx; // @[core.scala:51:7, :167:24]
wire [6:0] _dis_uops_2_pdst_T_3; // @[core.scala:659:28]
assign io_lsu_dis_uops_2_bits_pdst_0 = dis_uops_2_pdst; // @[core.scala:51:7, :167:24]
wire [6:0] _dis_uops_2_prs1_T_3; // @[core.scala:654:28]
assign io_lsu_dis_uops_2_bits_prs1_0 = dis_uops_2_prs1; // @[core.scala:51:7, :167:24]
wire [6:0] _dis_uops_2_prs2_T_1; // @[core.scala:656:28]
assign io_lsu_dis_uops_2_bits_prs2_0 = dis_uops_2_prs2; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_2_bits_prs3_0 = dis_uops_2_prs3; // @[core.scala:51:7, :167:24]
wire _dis_uops_2_prs1_busy_T_4; // @[core.scala:664:85]
assign io_lsu_dis_uops_2_bits_prs1_busy_0 = dis_uops_2_prs1_busy; // @[core.scala:51:7, :167:24]
wire _dis_uops_2_prs2_busy_T_4; // @[core.scala:666:85]
assign io_lsu_dis_uops_2_bits_prs2_busy_0 = dis_uops_2_prs2_busy; // @[core.scala:51:7, :167:24]
wire _dis_uops_2_prs3_busy_T; // @[core.scala:668:46]
assign io_lsu_dis_uops_2_bits_prs3_busy_0 = dis_uops_2_prs3_busy; // @[core.scala:51:7, :167:24]
wire [6:0] _dis_uops_2_stale_pdst_T_1; // @[core.scala:662:34]
assign io_lsu_dis_uops_2_bits_stale_pdst_0 = dis_uops_2_stale_pdst; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_2_bits_exception_0 = dis_uops_2_exception; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_2_bits_exc_cause_0 = dis_uops_2_exc_cause; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_2_bits_bypassable_0 = dis_uops_2_bypassable; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_2_bits_mem_cmd_0 = dis_uops_2_mem_cmd; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_2_bits_mem_size_0 = dis_uops_2_mem_size; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_2_bits_mem_signed_0 = dis_uops_2_mem_signed; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_2_bits_is_fence_0 = dis_uops_2_is_fence; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_2_bits_is_fencei_0 = dis_uops_2_is_fencei; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_2_bits_is_amo_0 = dis_uops_2_is_amo; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_2_bits_uses_ldq_0 = dis_uops_2_uses_ldq; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_2_bits_uses_stq_0 = dis_uops_2_uses_stq; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_2_bits_is_sys_pc2epc_0 = dis_uops_2_is_sys_pc2epc; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_2_bits_is_unique_0 = dis_uops_2_is_unique; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_2_bits_flush_on_commit_0 = dis_uops_2_flush_on_commit; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_2_bits_ldst_is_rs1_0 = dis_uops_2_ldst_is_rs1; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_2_bits_ldst_0 = dis_uops_2_ldst; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_2_bits_lrs1_0 = dis_uops_2_lrs1; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_2_bits_lrs2_0 = dis_uops_2_lrs2; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_2_bits_lrs3_0 = dis_uops_2_lrs3; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_2_bits_ldst_val_0 = dis_uops_2_ldst_val; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_2_bits_dst_rtype_0 = dis_uops_2_dst_rtype; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_2_bits_lrs1_rtype_0 = dis_uops_2_lrs1_rtype; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_2_bits_lrs2_rtype_0 = dis_uops_2_lrs2_rtype; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_2_bits_frs3_en_0 = dis_uops_2_frs3_en; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_2_bits_fp_val_0 = dis_uops_2_fp_val; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_2_bits_fp_single_0 = dis_uops_2_fp_single; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_2_bits_xcpt_pf_if_0 = dis_uops_2_xcpt_pf_if; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_2_bits_xcpt_ae_if_0 = dis_uops_2_xcpt_ae_if; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_2_bits_xcpt_ma_if_0 = dis_uops_2_xcpt_ma_if; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_2_bits_bp_debug_if_0 = dis_uops_2_bp_debug_if; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_2_bits_bp_xcpt_if_0 = dis_uops_2_bp_xcpt_if; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_2_bits_debug_fsrc_0 = dis_uops_2_debug_fsrc; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_2_bits_debug_tsrc_0 = dis_uops_2_debug_tsrc; // @[core.scala:51:7, :167:24]
assign io_lsu_dis_uops_0_valid_0 = dis_fire_0; // @[core.scala:51:7, :168:24]
assign io_lsu_dis_uops_1_valid_0 = dis_fire_1; // @[core.scala:51:7, :168:24]
assign io_lsu_dis_uops_2_valid_0 = dis_fire_2; // @[core.scala:51:7, :168:24]
wire _dis_ready_T; // @[core.scala:715:16]
wire dis_ready; // @[core.scala:169:24]
wire iss_valids_0; // @[core.scala:172:24]
wire iss_valids_1; // @[core.scala:172:24]
wire iss_valids_2; // @[core.scala:172:24]
wire iss_valids_3; // @[core.scala:172:24]
assign pred_wakeup_bits_uop_uopc = iss_uops_1_uopc; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_uopc = iss_uops_1_uopc; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_inst = iss_uops_1_inst; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_inst = iss_uops_1_inst; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_debug_inst = iss_uops_1_debug_inst; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_debug_inst = iss_uops_1_debug_inst; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_is_rvc = iss_uops_1_is_rvc; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_is_rvc = iss_uops_1_is_rvc; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_debug_pc = iss_uops_1_debug_pc; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_debug_pc = iss_uops_1_debug_pc; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_iq_type = iss_uops_1_iq_type; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_iq_type = iss_uops_1_iq_type; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_fu_code = iss_uops_1_fu_code; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_fu_code = iss_uops_1_fu_code; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_ctrl_br_type = iss_uops_1_ctrl_br_type; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_ctrl_br_type = iss_uops_1_ctrl_br_type; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_ctrl_op1_sel = iss_uops_1_ctrl_op1_sel; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_ctrl_op1_sel = iss_uops_1_ctrl_op1_sel; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_ctrl_op2_sel = iss_uops_1_ctrl_op2_sel; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_ctrl_op2_sel = iss_uops_1_ctrl_op2_sel; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_ctrl_imm_sel = iss_uops_1_ctrl_imm_sel; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_ctrl_imm_sel = iss_uops_1_ctrl_imm_sel; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_ctrl_op_fcn = iss_uops_1_ctrl_op_fcn; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_ctrl_op_fcn = iss_uops_1_ctrl_op_fcn; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_ctrl_fcn_dw = iss_uops_1_ctrl_fcn_dw; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_ctrl_fcn_dw = iss_uops_1_ctrl_fcn_dw; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_ctrl_csr_cmd = iss_uops_1_ctrl_csr_cmd; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_ctrl_csr_cmd = iss_uops_1_ctrl_csr_cmd; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_ctrl_is_load = iss_uops_1_ctrl_is_load; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_ctrl_is_load = iss_uops_1_ctrl_is_load; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_ctrl_is_sta = iss_uops_1_ctrl_is_sta; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_ctrl_is_sta = iss_uops_1_ctrl_is_sta; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_ctrl_is_std = iss_uops_1_ctrl_is_std; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_ctrl_is_std = iss_uops_1_ctrl_is_std; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_iw_state = iss_uops_1_iw_state; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_iw_state = iss_uops_1_iw_state; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_iw_p1_poisoned = iss_uops_1_iw_p1_poisoned; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_iw_p1_poisoned = iss_uops_1_iw_p1_poisoned; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_iw_p2_poisoned = iss_uops_1_iw_p2_poisoned; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_iw_p2_poisoned = iss_uops_1_iw_p2_poisoned; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_is_br = iss_uops_1_is_br; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_is_br = iss_uops_1_is_br; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_is_jalr = iss_uops_1_is_jalr; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_is_jalr = iss_uops_1_is_jalr; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_is_jal = iss_uops_1_is_jal; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_is_jal = iss_uops_1_is_jal; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_is_sfb = iss_uops_1_is_sfb; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_is_sfb = iss_uops_1_is_sfb; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_br_mask = iss_uops_1_br_mask; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_br_mask = iss_uops_1_br_mask; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_br_tag = iss_uops_1_br_tag; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_br_tag = iss_uops_1_br_tag; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_ftq_idx = iss_uops_1_ftq_idx; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_ftq_idx = iss_uops_1_ftq_idx; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_edge_inst = iss_uops_1_edge_inst; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_edge_inst = iss_uops_1_edge_inst; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_pc_lob = iss_uops_1_pc_lob; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_pc_lob = iss_uops_1_pc_lob; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_taken = iss_uops_1_taken; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_taken = iss_uops_1_taken; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_imm_packed = iss_uops_1_imm_packed; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_imm_packed = iss_uops_1_imm_packed; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_csr_addr = iss_uops_1_csr_addr; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_csr_addr = iss_uops_1_csr_addr; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_rob_idx = iss_uops_1_rob_idx; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_rob_idx = iss_uops_1_rob_idx; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_ldq_idx = iss_uops_1_ldq_idx; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_ldq_idx = iss_uops_1_ldq_idx; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_stq_idx = iss_uops_1_stq_idx; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_stq_idx = iss_uops_1_stq_idx; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_rxq_idx = iss_uops_1_rxq_idx; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_rxq_idx = iss_uops_1_rxq_idx; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_pdst = iss_uops_1_pdst; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_pdst = iss_uops_1_pdst; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_prs1 = iss_uops_1_prs1; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_prs1 = iss_uops_1_prs1; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_prs2 = iss_uops_1_prs2; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_prs2 = iss_uops_1_prs2; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_prs3 = iss_uops_1_prs3; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_prs3 = iss_uops_1_prs3; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_ppred = iss_uops_1_ppred; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_ppred = iss_uops_1_ppred; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_prs1_busy = iss_uops_1_prs1_busy; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_prs1_busy = iss_uops_1_prs1_busy; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_prs2_busy = iss_uops_1_prs2_busy; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_prs2_busy = iss_uops_1_prs2_busy; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_prs3_busy = iss_uops_1_prs3_busy; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_prs3_busy = iss_uops_1_prs3_busy; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_ppred_busy = iss_uops_1_ppred_busy; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_ppred_busy = iss_uops_1_ppred_busy; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_stale_pdst = iss_uops_1_stale_pdst; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_stale_pdst = iss_uops_1_stale_pdst; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_exception = iss_uops_1_exception; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_exception = iss_uops_1_exception; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_exc_cause = iss_uops_1_exc_cause; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_exc_cause = iss_uops_1_exc_cause; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_bypassable = iss_uops_1_bypassable; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_bypassable = iss_uops_1_bypassable; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_mem_cmd = iss_uops_1_mem_cmd; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_mem_cmd = iss_uops_1_mem_cmd; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_mem_size = iss_uops_1_mem_size; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_mem_size = iss_uops_1_mem_size; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_mem_signed = iss_uops_1_mem_signed; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_mem_signed = iss_uops_1_mem_signed; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_is_fence = iss_uops_1_is_fence; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_is_fence = iss_uops_1_is_fence; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_is_fencei = iss_uops_1_is_fencei; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_is_fencei = iss_uops_1_is_fencei; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_is_amo = iss_uops_1_is_amo; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_is_amo = iss_uops_1_is_amo; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_uses_ldq = iss_uops_1_uses_ldq; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_uses_ldq = iss_uops_1_uses_ldq; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_uses_stq = iss_uops_1_uses_stq; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_uses_stq = iss_uops_1_uses_stq; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_is_sys_pc2epc = iss_uops_1_is_sys_pc2epc; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_is_sys_pc2epc = iss_uops_1_is_sys_pc2epc; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_is_unique = iss_uops_1_is_unique; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_is_unique = iss_uops_1_is_unique; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_flush_on_commit = iss_uops_1_flush_on_commit; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_flush_on_commit = iss_uops_1_flush_on_commit; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_ldst_is_rs1 = iss_uops_1_ldst_is_rs1; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_ldst_is_rs1 = iss_uops_1_ldst_is_rs1; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_ldst = iss_uops_1_ldst; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_ldst = iss_uops_1_ldst; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_lrs1 = iss_uops_1_lrs1; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_lrs1 = iss_uops_1_lrs1; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_lrs2 = iss_uops_1_lrs2; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_lrs2 = iss_uops_1_lrs2; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_lrs3 = iss_uops_1_lrs3; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_lrs3 = iss_uops_1_lrs3; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_ldst_val = iss_uops_1_ldst_val; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_ldst_val = iss_uops_1_ldst_val; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_dst_rtype = iss_uops_1_dst_rtype; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_dst_rtype = iss_uops_1_dst_rtype; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_lrs1_rtype = iss_uops_1_lrs1_rtype; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_lrs1_rtype = iss_uops_1_lrs1_rtype; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_lrs2_rtype = iss_uops_1_lrs2_rtype; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_lrs2_rtype = iss_uops_1_lrs2_rtype; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_frs3_en = iss_uops_1_frs3_en; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_frs3_en = iss_uops_1_frs3_en; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_fp_val = iss_uops_1_fp_val; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_fp_val = iss_uops_1_fp_val; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_fp_single = iss_uops_1_fp_single; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_fp_single = iss_uops_1_fp_single; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_xcpt_pf_if = iss_uops_1_xcpt_pf_if; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_xcpt_pf_if = iss_uops_1_xcpt_pf_if; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_xcpt_ae_if = iss_uops_1_xcpt_ae_if; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_xcpt_ae_if = iss_uops_1_xcpt_ae_if; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_xcpt_ma_if = iss_uops_1_xcpt_ma_if; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_xcpt_ma_if = iss_uops_1_xcpt_ma_if; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_bp_debug_if = iss_uops_1_bp_debug_if; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_bp_debug_if = iss_uops_1_bp_debug_if; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_bp_xcpt_if = iss_uops_1_bp_xcpt_if; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_bp_xcpt_if = iss_uops_1_bp_xcpt_if; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_debug_fsrc = iss_uops_1_debug_fsrc; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_debug_fsrc = iss_uops_1_debug_fsrc; // @[core.scala:173:24, :814:29]
assign pred_wakeup_bits_uop_debug_tsrc = iss_uops_1_debug_tsrc; // @[core.scala:149:26, :173:24]
assign fast_wakeup_bits_uop_debug_tsrc = iss_uops_1_debug_tsrc; // @[core.scala:173:24, :814:29]
assign fast_wakeup_1_bits_uop_uopc = iss_uops_2_uopc; // @[core.scala:173:24, :814:29]
assign fast_wakeup_1_bits_uop_inst = iss_uops_2_inst; // @[core.scala:173:24, :814:29]
assign fast_wakeup_1_bits_uop_debug_inst = iss_uops_2_debug_inst; // @[core.scala:173:24, :814:29]
assign fast_wakeup_1_bits_uop_is_rvc = iss_uops_2_is_rvc; // @[core.scala:173:24, :814:29]
assign fast_wakeup_1_bits_uop_debug_pc = iss_uops_2_debug_pc; // @[core.scala:173:24, :814:29]
assign fast_wakeup_1_bits_uop_iq_type = iss_uops_2_iq_type; // @[core.scala:173:24, :814:29]
assign fast_wakeup_1_bits_uop_fu_code = iss_uops_2_fu_code; // @[core.scala:173:24, :814:29]
assign fast_wakeup_1_bits_uop_ctrl_br_type = iss_uops_2_ctrl_br_type; // @[core.scala:173:24, :814:29]
assign fast_wakeup_1_bits_uop_ctrl_op1_sel = iss_uops_2_ctrl_op1_sel; // @[core.scala:173:24, :814:29]
assign fast_wakeup_1_bits_uop_ctrl_op2_sel = iss_uops_2_ctrl_op2_sel; // @[core.scala:173:24, :814:29]
assign fast_wakeup_1_bits_uop_ctrl_imm_sel = iss_uops_2_ctrl_imm_sel; // @[core.scala:173:24, :814:29]
assign fast_wakeup_1_bits_uop_ctrl_op_fcn = iss_uops_2_ctrl_op_fcn; // @[core.scala:173:24, :814:29]
assign fast_wakeup_1_bits_uop_ctrl_fcn_dw = iss_uops_2_ctrl_fcn_dw; // @[core.scala:173:24, :814:29]
assign fast_wakeup_1_bits_uop_ctrl_csr_cmd = iss_uops_2_ctrl_csr_cmd; // @[core.scala:173:24, :814:29]
assign fast_wakeup_1_bits_uop_ctrl_is_load = iss_uops_2_ctrl_is_load; // @[core.scala:173:24, :814:29]
assign fast_wakeup_1_bits_uop_ctrl_is_sta = iss_uops_2_ctrl_is_sta; // @[core.scala:173:24, :814:29]
assign fast_wakeup_1_bits_uop_ctrl_is_std = iss_uops_2_ctrl_is_std; // @[core.scala:173:24, :814:29]
assign fast_wakeup_1_bits_uop_iw_state = iss_uops_2_iw_state; // @[core.scala:173:24, :814:29]
assign fast_wakeup_1_bits_uop_iw_p1_poisoned = iss_uops_2_iw_p1_poisoned; // @[core.scala:173:24, :814:29]
assign fast_wakeup_1_bits_uop_iw_p2_poisoned = iss_uops_2_iw_p2_poisoned; // @[core.scala:173:24, :814:29]
assign fast_wakeup_1_bits_uop_is_br = iss_uops_2_is_br; // @[core.scala:173:24, :814:29]
assign fast_wakeup_1_bits_uop_is_jalr = iss_uops_2_is_jalr; // @[core.scala:173:24, :814:29]
assign fast_wakeup_1_bits_uop_is_jal = iss_uops_2_is_jal; // @[core.scala:173:24, :814:29]
assign fast_wakeup_1_bits_uop_is_sfb = iss_uops_2_is_sfb; // @[core.scala:173:24, :814:29]
assign fast_wakeup_1_bits_uop_br_mask = iss_uops_2_br_mask; // @[core.scala:173:24, :814:29]
assign fast_wakeup_1_bits_uop_br_tag = iss_uops_2_br_tag; // @[core.scala:173:24, :814:29]
assign fast_wakeup_1_bits_uop_ftq_idx = iss_uops_2_ftq_idx; // @[core.scala:173:24, :814:29]
assign fast_wakeup_1_bits_uop_edge_inst = iss_uops_2_edge_inst; // @[core.scala:173:24, :814:29]
assign fast_wakeup_1_bits_uop_pc_lob = iss_uops_2_pc_lob; // @[core.scala:173:24, :814:29]
assign fast_wakeup_1_bits_uop_taken = iss_uops_2_taken; // @[core.scala:173:24, :814:29]
assign fast_wakeup_1_bits_uop_imm_packed = iss_uops_2_imm_packed; // @[core.scala:173:24, :814:29]
assign fast_wakeup_1_bits_uop_csr_addr = iss_uops_2_csr_addr; // @[core.scala:173:24, :814:29]
assign fast_wakeup_1_bits_uop_rob_idx = iss_uops_2_rob_idx; // @[core.scala:173:24, :814:29]
assign fast_wakeup_1_bits_uop_ldq_idx = iss_uops_2_ldq_idx; // @[core.scala:173:24, :814:29]
assign fast_wakeup_1_bits_uop_stq_idx = iss_uops_2_stq_idx; // @[core.scala:173:24, :814:29]
assign fast_wakeup_1_bits_uop_rxq_idx = iss_uops_2_rxq_idx; // @[core.scala:173:24, :814:29]
assign fast_wakeup_1_bits_uop_pdst = iss_uops_2_pdst; // @[core.scala:173:24, :814:29]
assign fast_wakeup_1_bits_uop_prs1 = iss_uops_2_prs1; // @[core.scala:173:24, :814:29]
assign fast_wakeup_1_bits_uop_prs2 = iss_uops_2_prs2; // @[core.scala:173:24, :814:29]
assign fast_wakeup_1_bits_uop_prs3 = iss_uops_2_prs3; // @[core.scala:173:24, :814:29]
assign fast_wakeup_1_bits_uop_ppred = iss_uops_2_ppred; // @[core.scala:173:24, :814:29]
assign fast_wakeup_1_bits_uop_prs1_busy = iss_uops_2_prs1_busy; // @[core.scala:173:24, :814:29]
assign fast_wakeup_1_bits_uop_prs2_busy = iss_uops_2_prs2_busy; // @[core.scala:173:24, :814:29]
assign fast_wakeup_1_bits_uop_prs3_busy = iss_uops_2_prs3_busy; // @[core.scala:173:24, :814:29]
assign fast_wakeup_1_bits_uop_ppred_busy = iss_uops_2_ppred_busy; // @[core.scala:173:24, :814:29]
assign fast_wakeup_1_bits_uop_stale_pdst = iss_uops_2_stale_pdst; // @[core.scala:173:24, :814:29]
assign fast_wakeup_1_bits_uop_exception = iss_uops_2_exception; // @[core.scala:173:24, :814:29]
assign fast_wakeup_1_bits_uop_exc_cause = iss_uops_2_exc_cause; // @[core.scala:173:24, :814:29]
assign fast_wakeup_1_bits_uop_bypassable = iss_uops_2_bypassable; // @[core.scala:173:24, :814:29]
assign fast_wakeup_1_bits_uop_mem_cmd = iss_uops_2_mem_cmd; // @[core.scala:173:24, :814:29]
assign fast_wakeup_1_bits_uop_mem_size = iss_uops_2_mem_size; // @[core.scala:173:24, :814:29]
assign fast_wakeup_1_bits_uop_mem_signed = iss_uops_2_mem_signed; // @[core.scala:173:24, :814:29]
assign fast_wakeup_1_bits_uop_is_fence = iss_uops_2_is_fence; // @[core.scala:173:24, :814:29]
assign fast_wakeup_1_bits_uop_is_fencei = iss_uops_2_is_fencei; // @[core.scala:173:24, :814:29]
assign fast_wakeup_1_bits_uop_is_amo = iss_uops_2_is_amo; // @[core.scala:173:24, :814:29]
assign fast_wakeup_1_bits_uop_uses_ldq = iss_uops_2_uses_ldq; // @[core.scala:173:24, :814:29]
assign fast_wakeup_1_bits_uop_uses_stq = iss_uops_2_uses_stq; // @[core.scala:173:24, :814:29]
assign fast_wakeup_1_bits_uop_is_sys_pc2epc = iss_uops_2_is_sys_pc2epc; // @[core.scala:173:24, :814:29]
assign fast_wakeup_1_bits_uop_is_unique = iss_uops_2_is_unique; // @[core.scala:173:24, :814:29]
assign fast_wakeup_1_bits_uop_flush_on_commit = iss_uops_2_flush_on_commit; // @[core.scala:173:24, :814:29]
assign fast_wakeup_1_bits_uop_ldst_is_rs1 = iss_uops_2_ldst_is_rs1; // @[core.scala:173:24, :814:29]
assign fast_wakeup_1_bits_uop_ldst = iss_uops_2_ldst; // @[core.scala:173:24, :814:29]
assign fast_wakeup_1_bits_uop_lrs1 = iss_uops_2_lrs1; // @[core.scala:173:24, :814:29]
assign fast_wakeup_1_bits_uop_lrs2 = iss_uops_2_lrs2; // @[core.scala:173:24, :814:29]
assign fast_wakeup_1_bits_uop_lrs3 = iss_uops_2_lrs3; // @[core.scala:173:24, :814:29]
assign fast_wakeup_1_bits_uop_ldst_val = iss_uops_2_ldst_val; // @[core.scala:173:24, :814:29]
assign fast_wakeup_1_bits_uop_dst_rtype = iss_uops_2_dst_rtype; // @[core.scala:173:24, :814:29]
assign fast_wakeup_1_bits_uop_lrs1_rtype = iss_uops_2_lrs1_rtype; // @[core.scala:173:24, :814:29]
assign fast_wakeup_1_bits_uop_lrs2_rtype = iss_uops_2_lrs2_rtype; // @[core.scala:173:24, :814:29]
assign fast_wakeup_1_bits_uop_frs3_en = iss_uops_2_frs3_en; // @[core.scala:173:24, :814:29]
assign fast_wakeup_1_bits_uop_fp_val = iss_uops_2_fp_val; // @[core.scala:173:24, :814:29]
assign fast_wakeup_1_bits_uop_fp_single = iss_uops_2_fp_single; // @[core.scala:173:24, :814:29]
assign fast_wakeup_1_bits_uop_xcpt_pf_if = iss_uops_2_xcpt_pf_if; // @[core.scala:173:24, :814:29]
assign fast_wakeup_1_bits_uop_xcpt_ae_if = iss_uops_2_xcpt_ae_if; // @[core.scala:173:24, :814:29]
assign fast_wakeup_1_bits_uop_xcpt_ma_if = iss_uops_2_xcpt_ma_if; // @[core.scala:173:24, :814:29]
assign fast_wakeup_1_bits_uop_bp_debug_if = iss_uops_2_bp_debug_if; // @[core.scala:173:24, :814:29]
assign fast_wakeup_1_bits_uop_bp_xcpt_if = iss_uops_2_bp_xcpt_if; // @[core.scala:173:24, :814:29]
assign fast_wakeup_1_bits_uop_debug_fsrc = iss_uops_2_debug_fsrc; // @[core.scala:173:24, :814:29]
assign fast_wakeup_1_bits_uop_debug_tsrc = iss_uops_2_debug_tsrc; // @[core.scala:173:24, :814:29]
assign fast_wakeup_2_bits_uop_uopc = iss_uops_3_uopc; // @[core.scala:173:24, :814:29]
assign fast_wakeup_2_bits_uop_inst = iss_uops_3_inst; // @[core.scala:173:24, :814:29]
assign fast_wakeup_2_bits_uop_debug_inst = iss_uops_3_debug_inst; // @[core.scala:173:24, :814:29]
assign fast_wakeup_2_bits_uop_is_rvc = iss_uops_3_is_rvc; // @[core.scala:173:24, :814:29]
assign fast_wakeup_2_bits_uop_debug_pc = iss_uops_3_debug_pc; // @[core.scala:173:24, :814:29]
assign fast_wakeup_2_bits_uop_iq_type = iss_uops_3_iq_type; // @[core.scala:173:24, :814:29]
assign fast_wakeup_2_bits_uop_fu_code = iss_uops_3_fu_code; // @[core.scala:173:24, :814:29]
assign fast_wakeup_2_bits_uop_ctrl_br_type = iss_uops_3_ctrl_br_type; // @[core.scala:173:24, :814:29]
assign fast_wakeup_2_bits_uop_ctrl_op1_sel = iss_uops_3_ctrl_op1_sel; // @[core.scala:173:24, :814:29]
assign fast_wakeup_2_bits_uop_ctrl_op2_sel = iss_uops_3_ctrl_op2_sel; // @[core.scala:173:24, :814:29]
assign fast_wakeup_2_bits_uop_ctrl_imm_sel = iss_uops_3_ctrl_imm_sel; // @[core.scala:173:24, :814:29]
assign fast_wakeup_2_bits_uop_ctrl_op_fcn = iss_uops_3_ctrl_op_fcn; // @[core.scala:173:24, :814:29]
assign fast_wakeup_2_bits_uop_ctrl_fcn_dw = iss_uops_3_ctrl_fcn_dw; // @[core.scala:173:24, :814:29]
assign fast_wakeup_2_bits_uop_ctrl_csr_cmd = iss_uops_3_ctrl_csr_cmd; // @[core.scala:173:24, :814:29]
assign fast_wakeup_2_bits_uop_ctrl_is_load = iss_uops_3_ctrl_is_load; // @[core.scala:173:24, :814:29]
assign fast_wakeup_2_bits_uop_ctrl_is_sta = iss_uops_3_ctrl_is_sta; // @[core.scala:173:24, :814:29]
assign fast_wakeup_2_bits_uop_ctrl_is_std = iss_uops_3_ctrl_is_std; // @[core.scala:173:24, :814:29]
assign fast_wakeup_2_bits_uop_iw_state = iss_uops_3_iw_state; // @[core.scala:173:24, :814:29]
assign fast_wakeup_2_bits_uop_iw_p1_poisoned = iss_uops_3_iw_p1_poisoned; // @[core.scala:173:24, :814:29]
assign fast_wakeup_2_bits_uop_iw_p2_poisoned = iss_uops_3_iw_p2_poisoned; // @[core.scala:173:24, :814:29]
assign fast_wakeup_2_bits_uop_is_br = iss_uops_3_is_br; // @[core.scala:173:24, :814:29]
assign fast_wakeup_2_bits_uop_is_jalr = iss_uops_3_is_jalr; // @[core.scala:173:24, :814:29]
assign fast_wakeup_2_bits_uop_is_jal = iss_uops_3_is_jal; // @[core.scala:173:24, :814:29]
assign fast_wakeup_2_bits_uop_is_sfb = iss_uops_3_is_sfb; // @[core.scala:173:24, :814:29]
assign fast_wakeup_2_bits_uop_br_mask = iss_uops_3_br_mask; // @[core.scala:173:24, :814:29]
assign fast_wakeup_2_bits_uop_br_tag = iss_uops_3_br_tag; // @[core.scala:173:24, :814:29]
assign fast_wakeup_2_bits_uop_ftq_idx = iss_uops_3_ftq_idx; // @[core.scala:173:24, :814:29]
assign fast_wakeup_2_bits_uop_edge_inst = iss_uops_3_edge_inst; // @[core.scala:173:24, :814:29]
assign fast_wakeup_2_bits_uop_pc_lob = iss_uops_3_pc_lob; // @[core.scala:173:24, :814:29]
assign fast_wakeup_2_bits_uop_taken = iss_uops_3_taken; // @[core.scala:173:24, :814:29]
assign fast_wakeup_2_bits_uop_imm_packed = iss_uops_3_imm_packed; // @[core.scala:173:24, :814:29]
assign fast_wakeup_2_bits_uop_csr_addr = iss_uops_3_csr_addr; // @[core.scala:173:24, :814:29]
assign fast_wakeup_2_bits_uop_rob_idx = iss_uops_3_rob_idx; // @[core.scala:173:24, :814:29]
assign fast_wakeup_2_bits_uop_ldq_idx = iss_uops_3_ldq_idx; // @[core.scala:173:24, :814:29]
assign fast_wakeup_2_bits_uop_stq_idx = iss_uops_3_stq_idx; // @[core.scala:173:24, :814:29]
assign fast_wakeup_2_bits_uop_rxq_idx = iss_uops_3_rxq_idx; // @[core.scala:173:24, :814:29]
assign fast_wakeup_2_bits_uop_pdst = iss_uops_3_pdst; // @[core.scala:173:24, :814:29]
assign fast_wakeup_2_bits_uop_prs1 = iss_uops_3_prs1; // @[core.scala:173:24, :814:29]
assign fast_wakeup_2_bits_uop_prs2 = iss_uops_3_prs2; // @[core.scala:173:24, :814:29]
assign fast_wakeup_2_bits_uop_prs3 = iss_uops_3_prs3; // @[core.scala:173:24, :814:29]
assign fast_wakeup_2_bits_uop_ppred = iss_uops_3_ppred; // @[core.scala:173:24, :814:29]
assign fast_wakeup_2_bits_uop_prs1_busy = iss_uops_3_prs1_busy; // @[core.scala:173:24, :814:29]
assign fast_wakeup_2_bits_uop_prs2_busy = iss_uops_3_prs2_busy; // @[core.scala:173:24, :814:29]
assign fast_wakeup_2_bits_uop_prs3_busy = iss_uops_3_prs3_busy; // @[core.scala:173:24, :814:29]
assign fast_wakeup_2_bits_uop_ppred_busy = iss_uops_3_ppred_busy; // @[core.scala:173:24, :814:29]
assign fast_wakeup_2_bits_uop_stale_pdst = iss_uops_3_stale_pdst; // @[core.scala:173:24, :814:29]
assign fast_wakeup_2_bits_uop_exception = iss_uops_3_exception; // @[core.scala:173:24, :814:29]
assign fast_wakeup_2_bits_uop_exc_cause = iss_uops_3_exc_cause; // @[core.scala:173:24, :814:29]
assign fast_wakeup_2_bits_uop_bypassable = iss_uops_3_bypassable; // @[core.scala:173:24, :814:29]
assign fast_wakeup_2_bits_uop_mem_cmd = iss_uops_3_mem_cmd; // @[core.scala:173:24, :814:29]
assign fast_wakeup_2_bits_uop_mem_size = iss_uops_3_mem_size; // @[core.scala:173:24, :814:29]
assign fast_wakeup_2_bits_uop_mem_signed = iss_uops_3_mem_signed; // @[core.scala:173:24, :814:29]
assign fast_wakeup_2_bits_uop_is_fence = iss_uops_3_is_fence; // @[core.scala:173:24, :814:29]
assign fast_wakeup_2_bits_uop_is_fencei = iss_uops_3_is_fencei; // @[core.scala:173:24, :814:29]
assign fast_wakeup_2_bits_uop_is_amo = iss_uops_3_is_amo; // @[core.scala:173:24, :814:29]
assign fast_wakeup_2_bits_uop_uses_ldq = iss_uops_3_uses_ldq; // @[core.scala:173:24, :814:29]
assign fast_wakeup_2_bits_uop_uses_stq = iss_uops_3_uses_stq; // @[core.scala:173:24, :814:29]
assign fast_wakeup_2_bits_uop_is_sys_pc2epc = iss_uops_3_is_sys_pc2epc; // @[core.scala:173:24, :814:29]
assign fast_wakeup_2_bits_uop_is_unique = iss_uops_3_is_unique; // @[core.scala:173:24, :814:29]
assign fast_wakeup_2_bits_uop_flush_on_commit = iss_uops_3_flush_on_commit; // @[core.scala:173:24, :814:29]
assign fast_wakeup_2_bits_uop_ldst_is_rs1 = iss_uops_3_ldst_is_rs1; // @[core.scala:173:24, :814:29]
assign fast_wakeup_2_bits_uop_ldst = iss_uops_3_ldst; // @[core.scala:173:24, :814:29]
assign fast_wakeup_2_bits_uop_lrs1 = iss_uops_3_lrs1; // @[core.scala:173:24, :814:29]
assign fast_wakeup_2_bits_uop_lrs2 = iss_uops_3_lrs2; // @[core.scala:173:24, :814:29]
assign fast_wakeup_2_bits_uop_lrs3 = iss_uops_3_lrs3; // @[core.scala:173:24, :814:29]
assign fast_wakeup_2_bits_uop_ldst_val = iss_uops_3_ldst_val; // @[core.scala:173:24, :814:29]
assign fast_wakeup_2_bits_uop_dst_rtype = iss_uops_3_dst_rtype; // @[core.scala:173:24, :814:29]
assign fast_wakeup_2_bits_uop_lrs1_rtype = iss_uops_3_lrs1_rtype; // @[core.scala:173:24, :814:29]
assign fast_wakeup_2_bits_uop_lrs2_rtype = iss_uops_3_lrs2_rtype; // @[core.scala:173:24, :814:29]
assign fast_wakeup_2_bits_uop_frs3_en = iss_uops_3_frs3_en; // @[core.scala:173:24, :814:29]
assign fast_wakeup_2_bits_uop_fp_val = iss_uops_3_fp_val; // @[core.scala:173:24, :814:29]
assign fast_wakeup_2_bits_uop_fp_single = iss_uops_3_fp_single; // @[core.scala:173:24, :814:29]
assign fast_wakeup_2_bits_uop_xcpt_pf_if = iss_uops_3_xcpt_pf_if; // @[core.scala:173:24, :814:29]
assign fast_wakeup_2_bits_uop_xcpt_ae_if = iss_uops_3_xcpt_ae_if; // @[core.scala:173:24, :814:29]
assign fast_wakeup_2_bits_uop_xcpt_ma_if = iss_uops_3_xcpt_ma_if; // @[core.scala:173:24, :814:29]
assign fast_wakeup_2_bits_uop_bp_debug_if = iss_uops_3_bp_debug_if; // @[core.scala:173:24, :814:29]
assign fast_wakeup_2_bits_uop_bp_xcpt_if = iss_uops_3_bp_xcpt_if; // @[core.scala:173:24, :814:29]
assign fast_wakeup_2_bits_uop_debug_fsrc = iss_uops_3_debug_fsrc; // @[core.scala:173:24, :814:29]
wire [3:0] iss_uops_0_ctrl_br_type; // @[core.scala:173:24]
wire [1:0] iss_uops_0_ctrl_op1_sel; // @[core.scala:173:24]
wire [2:0] iss_uops_0_ctrl_op2_sel; // @[core.scala:173:24]
wire [2:0] iss_uops_0_ctrl_imm_sel; // @[core.scala:173:24]
wire [4:0] iss_uops_0_ctrl_op_fcn; // @[core.scala:173:24]
wire iss_uops_0_ctrl_fcn_dw; // @[core.scala:173:24]
wire [2:0] iss_uops_0_ctrl_csr_cmd; // @[core.scala:173:24]
wire iss_uops_0_ctrl_is_load; // @[core.scala:173:24]
wire iss_uops_0_ctrl_is_sta; // @[core.scala:173:24]
wire iss_uops_0_ctrl_is_std; // @[core.scala:173:24]
assign fast_wakeup_2_bits_uop_debug_tsrc = iss_uops_3_debug_tsrc; // @[core.scala:173:24, :814:29]
wire [6:0] iss_uops_0_uopc; // @[core.scala:173:24]
wire [31:0] iss_uops_0_inst; // @[core.scala:173:24]
wire [31:0] iss_uops_0_debug_inst; // @[core.scala:173:24]
wire iss_uops_0_is_rvc; // @[core.scala:173:24]
wire [39:0] iss_uops_0_debug_pc; // @[core.scala:173:24]
wire [2:0] iss_uops_0_iq_type; // @[core.scala:173:24]
wire [9:0] iss_uops_0_fu_code; // @[core.scala:173:24]
wire [1:0] iss_uops_0_iw_state; // @[core.scala:173:24]
wire iss_uops_0_iw_p1_poisoned; // @[core.scala:173:24]
wire iss_uops_0_iw_p2_poisoned; // @[core.scala:173:24]
wire iss_uops_0_is_br; // @[core.scala:173:24]
wire iss_uops_0_is_jalr; // @[core.scala:173:24]
wire iss_uops_0_is_jal; // @[core.scala:173:24]
wire iss_uops_0_is_sfb; // @[core.scala:173:24]
wire [15:0] iss_uops_0_br_mask; // @[core.scala:173:24]
wire [3:0] iss_uops_0_br_tag; // @[core.scala:173:24]
wire [4:0] iss_uops_0_ftq_idx; // @[core.scala:173:24]
wire iss_uops_0_edge_inst; // @[core.scala:173:24]
wire [5:0] iss_uops_0_pc_lob; // @[core.scala:173:24]
wire iss_uops_0_taken; // @[core.scala:173:24]
wire [19:0] iss_uops_0_imm_packed; // @[core.scala:173:24]
wire [11:0] iss_uops_0_csr_addr; // @[core.scala:173:24]
wire [6:0] iss_uops_0_rob_idx; // @[core.scala:173:24]
wire [4:0] iss_uops_0_ldq_idx; // @[core.scala:173:24]
wire [4:0] iss_uops_0_stq_idx; // @[core.scala:173:24]
wire [1:0] iss_uops_0_rxq_idx; // @[core.scala:173:24]
wire [6:0] iss_uops_0_pdst; // @[core.scala:173:24]
wire [6:0] iss_uops_0_prs1; // @[core.scala:173:24]
wire [6:0] iss_uops_0_prs2; // @[core.scala:173:24]
wire [6:0] iss_uops_0_prs3; // @[core.scala:173:24]
wire [4:0] iss_uops_0_ppred; // @[core.scala:173:24]
wire iss_uops_0_prs1_busy; // @[core.scala:173:24]
wire iss_uops_0_prs2_busy; // @[core.scala:173:24]
wire iss_uops_0_prs3_busy; // @[core.scala:173:24]
wire iss_uops_0_ppred_busy; // @[core.scala:173:24]
wire [6:0] iss_uops_0_stale_pdst; // @[core.scala:173:24]
wire iss_uops_0_exception; // @[core.scala:173:24]
wire [63:0] iss_uops_0_exc_cause; // @[core.scala:173:24]
wire iss_uops_0_bypassable; // @[core.scala:173:24]
wire [4:0] iss_uops_0_mem_cmd; // @[core.scala:173:24]
wire [1:0] iss_uops_0_mem_size; // @[core.scala:173:24]
wire iss_uops_0_mem_signed; // @[core.scala:173:24]
wire iss_uops_0_is_fence; // @[core.scala:173:24]
wire iss_uops_0_is_fencei; // @[core.scala:173:24]
wire iss_uops_0_is_amo; // @[core.scala:173:24]
wire iss_uops_0_uses_ldq; // @[core.scala:173:24]
wire iss_uops_0_uses_stq; // @[core.scala:173:24]
wire iss_uops_0_is_sys_pc2epc; // @[core.scala:173:24]
wire iss_uops_0_is_unique; // @[core.scala:173:24]
wire iss_uops_0_flush_on_commit; // @[core.scala:173:24]
wire iss_uops_0_ldst_is_rs1; // @[core.scala:173:24]
wire [5:0] iss_uops_0_ldst; // @[core.scala:173:24]
wire [5:0] iss_uops_0_lrs1; // @[core.scala:173:24]
wire [5:0] iss_uops_0_lrs2; // @[core.scala:173:24]
wire [5:0] iss_uops_0_lrs3; // @[core.scala:173:24]
wire iss_uops_0_ldst_val; // @[core.scala:173:24]
wire [1:0] iss_uops_0_dst_rtype; // @[core.scala:173:24]
wire [1:0] iss_uops_0_lrs1_rtype; // @[core.scala:173:24]
wire [1:0] iss_uops_0_lrs2_rtype; // @[core.scala:173:24]
wire iss_uops_0_frs3_en; // @[core.scala:173:24]
wire iss_uops_0_fp_val; // @[core.scala:173:24]
wire iss_uops_0_fp_single; // @[core.scala:173:24]
wire iss_uops_0_xcpt_pf_if; // @[core.scala:173:24]
wire iss_uops_0_xcpt_ae_if; // @[core.scala:173:24]
wire iss_uops_0_xcpt_ma_if; // @[core.scala:173:24]
wire iss_uops_0_bp_debug_if; // @[core.scala:173:24]
wire iss_uops_0_bp_xcpt_if; // @[core.scala:173:24]
wire [1:0] iss_uops_0_debug_fsrc; // @[core.scala:173:24]
wire [1:0] iss_uops_0_debug_tsrc; // @[core.scala:173:24]
wire [3:0] bypasses_0_bits_uop_ctrl_br_type; // @[core.scala:174:24]
wire [1:0] bypasses_0_bits_uop_ctrl_op1_sel; // @[core.scala:174:24]
wire [2:0] bypasses_0_bits_uop_ctrl_op2_sel; // @[core.scala:174:24]
wire [2:0] bypasses_0_bits_uop_ctrl_imm_sel; // @[core.scala:174:24]
wire [4:0] bypasses_0_bits_uop_ctrl_op_fcn; // @[core.scala:174:24]
wire bypasses_0_bits_uop_ctrl_fcn_dw; // @[core.scala:174:24]
wire [2:0] bypasses_0_bits_uop_ctrl_csr_cmd; // @[core.scala:174:24]
wire bypasses_0_bits_uop_ctrl_is_load; // @[core.scala:174:24]
wire bypasses_0_bits_uop_ctrl_is_sta; // @[core.scala:174:24]
wire bypasses_0_bits_uop_ctrl_is_std; // @[core.scala:174:24]
wire [6:0] bypasses_0_bits_uop_uopc; // @[core.scala:174:24]
wire [31:0] bypasses_0_bits_uop_inst; // @[core.scala:174:24]
wire [31:0] bypasses_0_bits_uop_debug_inst; // @[core.scala:174:24]
wire bypasses_0_bits_uop_is_rvc; // @[core.scala:174:24]
wire [39:0] bypasses_0_bits_uop_debug_pc; // @[core.scala:174:24]
wire [2:0] bypasses_0_bits_uop_iq_type; // @[core.scala:174:24]
wire [9:0] bypasses_0_bits_uop_fu_code; // @[core.scala:174:24]
wire [1:0] bypasses_0_bits_uop_iw_state; // @[core.scala:174:24]
wire bypasses_0_bits_uop_iw_p1_poisoned; // @[core.scala:174:24]
wire bypasses_0_bits_uop_iw_p2_poisoned; // @[core.scala:174:24]
wire bypasses_0_bits_uop_is_br; // @[core.scala:174:24]
wire bypasses_0_bits_uop_is_jalr; // @[core.scala:174:24]
wire bypasses_0_bits_uop_is_jal; // @[core.scala:174:24]
wire bypasses_0_bits_uop_is_sfb; // @[core.scala:174:24]
wire [15:0] bypasses_0_bits_uop_br_mask; // @[core.scala:174:24]
wire [3:0] bypasses_0_bits_uop_br_tag; // @[core.scala:174:24]
wire [4:0] bypasses_0_bits_uop_ftq_idx; // @[core.scala:174:24]
wire bypasses_0_bits_uop_edge_inst; // @[core.scala:174:24]
wire [5:0] bypasses_0_bits_uop_pc_lob; // @[core.scala:174:24]
wire bypasses_0_bits_uop_taken; // @[core.scala:174:24]
wire [19:0] bypasses_0_bits_uop_imm_packed; // @[core.scala:174:24]
wire [11:0] bypasses_0_bits_uop_csr_addr; // @[core.scala:174:24]
wire [6:0] bypasses_0_bits_uop_rob_idx; // @[core.scala:174:24]
wire [4:0] bypasses_0_bits_uop_ldq_idx; // @[core.scala:174:24]
wire [4:0] bypasses_0_bits_uop_stq_idx; // @[core.scala:174:24]
wire [1:0] bypasses_0_bits_uop_rxq_idx; // @[core.scala:174:24]
wire [6:0] bypasses_0_bits_uop_pdst; // @[core.scala:174:24]
wire [6:0] bypasses_0_bits_uop_prs1; // @[core.scala:174:24]
wire [6:0] bypasses_0_bits_uop_prs2; // @[core.scala:174:24]
wire [6:0] bypasses_0_bits_uop_prs3; // @[core.scala:174:24]
wire [4:0] bypasses_0_bits_uop_ppred; // @[core.scala:174:24]
wire bypasses_0_bits_uop_prs1_busy; // @[core.scala:174:24]
wire bypasses_0_bits_uop_prs2_busy; // @[core.scala:174:24]
wire bypasses_0_bits_uop_prs3_busy; // @[core.scala:174:24]
wire bypasses_0_bits_uop_ppred_busy; // @[core.scala:174:24]
wire [6:0] bypasses_0_bits_uop_stale_pdst; // @[core.scala:174:24]
wire bypasses_0_bits_uop_exception; // @[core.scala:174:24]
wire [63:0] bypasses_0_bits_uop_exc_cause; // @[core.scala:174:24]
wire bypasses_0_bits_uop_bypassable; // @[core.scala:174:24]
wire [4:0] bypasses_0_bits_uop_mem_cmd; // @[core.scala:174:24]
wire [1:0] bypasses_0_bits_uop_mem_size; // @[core.scala:174:24]
wire bypasses_0_bits_uop_mem_signed; // @[core.scala:174:24]
wire bypasses_0_bits_uop_is_fence; // @[core.scala:174:24]
wire bypasses_0_bits_uop_is_fencei; // @[core.scala:174:24]
wire bypasses_0_bits_uop_is_amo; // @[core.scala:174:24]
wire bypasses_0_bits_uop_uses_ldq; // @[core.scala:174:24]
wire bypasses_0_bits_uop_uses_stq; // @[core.scala:174:24]
wire bypasses_0_bits_uop_is_sys_pc2epc; // @[core.scala:174:24]
wire bypasses_0_bits_uop_is_unique; // @[core.scala:174:24]
wire bypasses_0_bits_uop_flush_on_commit; // @[core.scala:174:24]
wire bypasses_0_bits_uop_ldst_is_rs1; // @[core.scala:174:24]
wire [5:0] bypasses_0_bits_uop_ldst; // @[core.scala:174:24]
wire [5:0] bypasses_0_bits_uop_lrs1; // @[core.scala:174:24]
wire [5:0] bypasses_0_bits_uop_lrs2; // @[core.scala:174:24]
wire [5:0] bypasses_0_bits_uop_lrs3; // @[core.scala:174:24]
wire bypasses_0_bits_uop_ldst_val; // @[core.scala:174:24]
wire [1:0] bypasses_0_bits_uop_dst_rtype; // @[core.scala:174:24]
wire [1:0] bypasses_0_bits_uop_lrs1_rtype; // @[core.scala:174:24]
wire [1:0] bypasses_0_bits_uop_lrs2_rtype; // @[core.scala:174:24]
wire bypasses_0_bits_uop_frs3_en; // @[core.scala:174:24]
wire bypasses_0_bits_uop_fp_val; // @[core.scala:174:24]
wire bypasses_0_bits_uop_fp_single; // @[core.scala:174:24]
wire bypasses_0_bits_uop_xcpt_pf_if; // @[core.scala:174:24]
wire bypasses_0_bits_uop_xcpt_ae_if; // @[core.scala:174:24]
wire bypasses_0_bits_uop_xcpt_ma_if; // @[core.scala:174:24]
wire bypasses_0_bits_uop_bp_debug_if; // @[core.scala:174:24]
wire bypasses_0_bits_uop_bp_xcpt_if; // @[core.scala:174:24]
wire [1:0] bypasses_0_bits_uop_debug_fsrc; // @[core.scala:174:24]
wire [1:0] bypasses_0_bits_uop_debug_tsrc; // @[core.scala:174:24]
wire [63:0] bypasses_0_bits_data; // @[core.scala:174:24]
wire bypasses_0_valid; // @[core.scala:174:24]
wire [3:0] bypasses_1_bits_uop_ctrl_br_type; // @[core.scala:174:24]
wire [1:0] bypasses_1_bits_uop_ctrl_op1_sel; // @[core.scala:174:24]
wire [2:0] bypasses_1_bits_uop_ctrl_op2_sel; // @[core.scala:174:24]
wire [2:0] bypasses_1_bits_uop_ctrl_imm_sel; // @[core.scala:174:24]
wire [4:0] bypasses_1_bits_uop_ctrl_op_fcn; // @[core.scala:174:24]
wire bypasses_1_bits_uop_ctrl_fcn_dw; // @[core.scala:174:24]
wire [2:0] bypasses_1_bits_uop_ctrl_csr_cmd; // @[core.scala:174:24]
wire bypasses_1_bits_uop_ctrl_is_load; // @[core.scala:174:24]
wire bypasses_1_bits_uop_ctrl_is_sta; // @[core.scala:174:24]
wire bypasses_1_bits_uop_ctrl_is_std; // @[core.scala:174:24]
wire [6:0] bypasses_1_bits_uop_uopc; // @[core.scala:174:24]
wire [31:0] bypasses_1_bits_uop_inst; // @[core.scala:174:24]
wire [31:0] bypasses_1_bits_uop_debug_inst; // @[core.scala:174:24]
wire bypasses_1_bits_uop_is_rvc; // @[core.scala:174:24]
wire [39:0] bypasses_1_bits_uop_debug_pc; // @[core.scala:174:24]
wire [2:0] bypasses_1_bits_uop_iq_type; // @[core.scala:174:24]
wire [9:0] bypasses_1_bits_uop_fu_code; // @[core.scala:174:24]
wire [1:0] bypasses_1_bits_uop_iw_state; // @[core.scala:174:24]
wire bypasses_1_bits_uop_iw_p1_poisoned; // @[core.scala:174:24]
wire bypasses_1_bits_uop_iw_p2_poisoned; // @[core.scala:174:24]
wire bypasses_1_bits_uop_is_br; // @[core.scala:174:24]
wire bypasses_1_bits_uop_is_jalr; // @[core.scala:174:24]
wire bypasses_1_bits_uop_is_jal; // @[core.scala:174:24]
wire bypasses_1_bits_uop_is_sfb; // @[core.scala:174:24]
wire [15:0] bypasses_1_bits_uop_br_mask; // @[core.scala:174:24]
wire [3:0] bypasses_1_bits_uop_br_tag; // @[core.scala:174:24]
wire [4:0] bypasses_1_bits_uop_ftq_idx; // @[core.scala:174:24]
wire bypasses_1_bits_uop_edge_inst; // @[core.scala:174:24]
wire [5:0] bypasses_1_bits_uop_pc_lob; // @[core.scala:174:24]
wire bypasses_1_bits_uop_taken; // @[core.scala:174:24]
wire [19:0] bypasses_1_bits_uop_imm_packed; // @[core.scala:174:24]
wire [11:0] bypasses_1_bits_uop_csr_addr; // @[core.scala:174:24]
wire [6:0] bypasses_1_bits_uop_rob_idx; // @[core.scala:174:24]
wire [4:0] bypasses_1_bits_uop_ldq_idx; // @[core.scala:174:24]
wire [4:0] bypasses_1_bits_uop_stq_idx; // @[core.scala:174:24]
wire [1:0] bypasses_1_bits_uop_rxq_idx; // @[core.scala:174:24]
wire [6:0] bypasses_1_bits_uop_pdst; // @[core.scala:174:24]
wire [6:0] bypasses_1_bits_uop_prs1; // @[core.scala:174:24]
wire [6:0] bypasses_1_bits_uop_prs2; // @[core.scala:174:24]
wire [6:0] bypasses_1_bits_uop_prs3; // @[core.scala:174:24]
wire [4:0] bypasses_1_bits_uop_ppred; // @[core.scala:174:24]
wire bypasses_1_bits_uop_prs1_busy; // @[core.scala:174:24]
wire bypasses_1_bits_uop_prs2_busy; // @[core.scala:174:24]
wire bypasses_1_bits_uop_prs3_busy; // @[core.scala:174:24]
wire bypasses_1_bits_uop_ppred_busy; // @[core.scala:174:24]
wire [6:0] bypasses_1_bits_uop_stale_pdst; // @[core.scala:174:24]
wire bypasses_1_bits_uop_exception; // @[core.scala:174:24]
wire [63:0] bypasses_1_bits_uop_exc_cause; // @[core.scala:174:24]
wire bypasses_1_bits_uop_bypassable; // @[core.scala:174:24]
wire [4:0] bypasses_1_bits_uop_mem_cmd; // @[core.scala:174:24]
wire [1:0] bypasses_1_bits_uop_mem_size; // @[core.scala:174:24]
wire bypasses_1_bits_uop_mem_signed; // @[core.scala:174:24]
wire bypasses_1_bits_uop_is_fence; // @[core.scala:174:24]
wire bypasses_1_bits_uop_is_fencei; // @[core.scala:174:24]
wire bypasses_1_bits_uop_is_amo; // @[core.scala:174:24]
wire bypasses_1_bits_uop_uses_ldq; // @[core.scala:174:24]
wire bypasses_1_bits_uop_uses_stq; // @[core.scala:174:24]
wire bypasses_1_bits_uop_is_sys_pc2epc; // @[core.scala:174:24]
wire bypasses_1_bits_uop_is_unique; // @[core.scala:174:24]
wire bypasses_1_bits_uop_flush_on_commit; // @[core.scala:174:24]
wire bypasses_1_bits_uop_ldst_is_rs1; // @[core.scala:174:24]
wire [5:0] bypasses_1_bits_uop_ldst; // @[core.scala:174:24]
wire [5:0] bypasses_1_bits_uop_lrs1; // @[core.scala:174:24]
wire [5:0] bypasses_1_bits_uop_lrs2; // @[core.scala:174:24]
wire [5:0] bypasses_1_bits_uop_lrs3; // @[core.scala:174:24]
wire bypasses_1_bits_uop_ldst_val; // @[core.scala:174:24]
wire [1:0] bypasses_1_bits_uop_dst_rtype; // @[core.scala:174:24]
wire [1:0] bypasses_1_bits_uop_lrs1_rtype; // @[core.scala:174:24]
wire [1:0] bypasses_1_bits_uop_lrs2_rtype; // @[core.scala:174:24]
wire bypasses_1_bits_uop_frs3_en; // @[core.scala:174:24]
wire bypasses_1_bits_uop_fp_val; // @[core.scala:174:24]
wire bypasses_1_bits_uop_fp_single; // @[core.scala:174:24]
wire bypasses_1_bits_uop_xcpt_pf_if; // @[core.scala:174:24]
wire bypasses_1_bits_uop_xcpt_ae_if; // @[core.scala:174:24]
wire bypasses_1_bits_uop_xcpt_ma_if; // @[core.scala:174:24]
wire bypasses_1_bits_uop_bp_debug_if; // @[core.scala:174:24]
wire bypasses_1_bits_uop_bp_xcpt_if; // @[core.scala:174:24]
wire [1:0] bypasses_1_bits_uop_debug_fsrc; // @[core.scala:174:24]
wire [1:0] bypasses_1_bits_uop_debug_tsrc; // @[core.scala:174:24]
wire [63:0] bypasses_1_bits_data; // @[core.scala:174:24]
wire bypasses_1_valid; // @[core.scala:174:24]
wire [3:0] bypasses_2_bits_uop_ctrl_br_type; // @[core.scala:174:24]
wire [1:0] bypasses_2_bits_uop_ctrl_op1_sel; // @[core.scala:174:24]
wire [2:0] bypasses_2_bits_uop_ctrl_op2_sel; // @[core.scala:174:24]
wire [2:0] bypasses_2_bits_uop_ctrl_imm_sel; // @[core.scala:174:24]
wire [4:0] bypasses_2_bits_uop_ctrl_op_fcn; // @[core.scala:174:24]
wire bypasses_2_bits_uop_ctrl_fcn_dw; // @[core.scala:174:24]
wire [2:0] bypasses_2_bits_uop_ctrl_csr_cmd; // @[core.scala:174:24]
wire bypasses_2_bits_uop_ctrl_is_load; // @[core.scala:174:24]
wire bypasses_2_bits_uop_ctrl_is_sta; // @[core.scala:174:24]
wire bypasses_2_bits_uop_ctrl_is_std; // @[core.scala:174:24]
wire [6:0] bypasses_2_bits_uop_uopc; // @[core.scala:174:24]
wire [31:0] bypasses_2_bits_uop_inst; // @[core.scala:174:24]
wire [31:0] bypasses_2_bits_uop_debug_inst; // @[core.scala:174:24]
wire bypasses_2_bits_uop_is_rvc; // @[core.scala:174:24]
wire [39:0] bypasses_2_bits_uop_debug_pc; // @[core.scala:174:24]
wire [2:0] bypasses_2_bits_uop_iq_type; // @[core.scala:174:24]
wire [9:0] bypasses_2_bits_uop_fu_code; // @[core.scala:174:24]
wire [1:0] bypasses_2_bits_uop_iw_state; // @[core.scala:174:24]
wire bypasses_2_bits_uop_iw_p1_poisoned; // @[core.scala:174:24]
wire bypasses_2_bits_uop_iw_p2_poisoned; // @[core.scala:174:24]
wire bypasses_2_bits_uop_is_br; // @[core.scala:174:24]
wire bypasses_2_bits_uop_is_jalr; // @[core.scala:174:24]
wire bypasses_2_bits_uop_is_jal; // @[core.scala:174:24]
wire bypasses_2_bits_uop_is_sfb; // @[core.scala:174:24]
wire [15:0] bypasses_2_bits_uop_br_mask; // @[core.scala:174:24]
wire [3:0] bypasses_2_bits_uop_br_tag; // @[core.scala:174:24]
wire [4:0] bypasses_2_bits_uop_ftq_idx; // @[core.scala:174:24]
wire bypasses_2_bits_uop_edge_inst; // @[core.scala:174:24]
wire [5:0] bypasses_2_bits_uop_pc_lob; // @[core.scala:174:24]
wire bypasses_2_bits_uop_taken; // @[core.scala:174:24]
wire [19:0] bypasses_2_bits_uop_imm_packed; // @[core.scala:174:24]
wire [11:0] bypasses_2_bits_uop_csr_addr; // @[core.scala:174:24]
wire [6:0] bypasses_2_bits_uop_rob_idx; // @[core.scala:174:24]
wire [4:0] bypasses_2_bits_uop_ldq_idx; // @[core.scala:174:24]
wire [4:0] bypasses_2_bits_uop_stq_idx; // @[core.scala:174:24]
wire [1:0] bypasses_2_bits_uop_rxq_idx; // @[core.scala:174:24]
wire [6:0] bypasses_2_bits_uop_pdst; // @[core.scala:174:24]
wire [6:0] bypasses_2_bits_uop_prs1; // @[core.scala:174:24]
wire [6:0] bypasses_2_bits_uop_prs2; // @[core.scala:174:24]
wire [6:0] bypasses_2_bits_uop_prs3; // @[core.scala:174:24]
wire [4:0] bypasses_2_bits_uop_ppred; // @[core.scala:174:24]
wire bypasses_2_bits_uop_prs1_busy; // @[core.scala:174:24]
wire bypasses_2_bits_uop_prs2_busy; // @[core.scala:174:24]
wire bypasses_2_bits_uop_prs3_busy; // @[core.scala:174:24]
wire bypasses_2_bits_uop_ppred_busy; // @[core.scala:174:24]
wire [6:0] bypasses_2_bits_uop_stale_pdst; // @[core.scala:174:24]
wire bypasses_2_bits_uop_exception; // @[core.scala:174:24]
wire [63:0] bypasses_2_bits_uop_exc_cause; // @[core.scala:174:24]
wire bypasses_2_bits_uop_bypassable; // @[core.scala:174:24]
wire [4:0] bypasses_2_bits_uop_mem_cmd; // @[core.scala:174:24]
wire [1:0] bypasses_2_bits_uop_mem_size; // @[core.scala:174:24]
wire bypasses_2_bits_uop_mem_signed; // @[core.scala:174:24]
wire bypasses_2_bits_uop_is_fence; // @[core.scala:174:24]
wire bypasses_2_bits_uop_is_fencei; // @[core.scala:174:24]
wire bypasses_2_bits_uop_is_amo; // @[core.scala:174:24]
wire bypasses_2_bits_uop_uses_ldq; // @[core.scala:174:24]
wire bypasses_2_bits_uop_uses_stq; // @[core.scala:174:24]
wire bypasses_2_bits_uop_is_sys_pc2epc; // @[core.scala:174:24]
wire bypasses_2_bits_uop_is_unique; // @[core.scala:174:24]
wire bypasses_2_bits_uop_flush_on_commit; // @[core.scala:174:24]
wire bypasses_2_bits_uop_ldst_is_rs1; // @[core.scala:174:24]
wire [5:0] bypasses_2_bits_uop_ldst; // @[core.scala:174:24]
wire [5:0] bypasses_2_bits_uop_lrs1; // @[core.scala:174:24]
wire [5:0] bypasses_2_bits_uop_lrs2; // @[core.scala:174:24]
wire [5:0] bypasses_2_bits_uop_lrs3; // @[core.scala:174:24]
wire bypasses_2_bits_uop_ldst_val; // @[core.scala:174:24]
wire [1:0] bypasses_2_bits_uop_dst_rtype; // @[core.scala:174:24]
wire [1:0] bypasses_2_bits_uop_lrs1_rtype; // @[core.scala:174:24]
wire [1:0] bypasses_2_bits_uop_lrs2_rtype; // @[core.scala:174:24]
wire bypasses_2_bits_uop_frs3_en; // @[core.scala:174:24]
wire bypasses_2_bits_uop_fp_val; // @[core.scala:174:24]
wire bypasses_2_bits_uop_fp_single; // @[core.scala:174:24]
wire bypasses_2_bits_uop_xcpt_pf_if; // @[core.scala:174:24]
wire bypasses_2_bits_uop_xcpt_ae_if; // @[core.scala:174:24]
wire bypasses_2_bits_uop_xcpt_ma_if; // @[core.scala:174:24]
wire bypasses_2_bits_uop_bp_debug_if; // @[core.scala:174:24]
wire bypasses_2_bits_uop_bp_xcpt_if; // @[core.scala:174:24]
wire [1:0] bypasses_2_bits_uop_debug_fsrc; // @[core.scala:174:24]
wire [1:0] bypasses_2_bits_uop_debug_tsrc; // @[core.scala:174:24]
wire [63:0] bypasses_2_bits_data; // @[core.scala:174:24]
wire bypasses_2_valid; // @[core.scala:174:24]
wire [3:0] bypasses_3_bits_uop_ctrl_br_type; // @[core.scala:174:24]
wire [1:0] bypasses_3_bits_uop_ctrl_op1_sel; // @[core.scala:174:24]
wire [2:0] bypasses_3_bits_uop_ctrl_op2_sel; // @[core.scala:174:24]
wire [2:0] bypasses_3_bits_uop_ctrl_imm_sel; // @[core.scala:174:24]
wire [4:0] bypasses_3_bits_uop_ctrl_op_fcn; // @[core.scala:174:24]
wire bypasses_3_bits_uop_ctrl_fcn_dw; // @[core.scala:174:24]
wire [2:0] bypasses_3_bits_uop_ctrl_csr_cmd; // @[core.scala:174:24]
wire bypasses_3_bits_uop_ctrl_is_load; // @[core.scala:174:24]
wire bypasses_3_bits_uop_ctrl_is_sta; // @[core.scala:174:24]
wire bypasses_3_bits_uop_ctrl_is_std; // @[core.scala:174:24]
wire [6:0] bypasses_3_bits_uop_uopc; // @[core.scala:174:24]
wire [31:0] bypasses_3_bits_uop_inst; // @[core.scala:174:24]
wire [31:0] bypasses_3_bits_uop_debug_inst; // @[core.scala:174:24]
wire bypasses_3_bits_uop_is_rvc; // @[core.scala:174:24]
wire [39:0] bypasses_3_bits_uop_debug_pc; // @[core.scala:174:24]
wire [2:0] bypasses_3_bits_uop_iq_type; // @[core.scala:174:24]
wire [9:0] bypasses_3_bits_uop_fu_code; // @[core.scala:174:24]
wire [1:0] bypasses_3_bits_uop_iw_state; // @[core.scala:174:24]
wire bypasses_3_bits_uop_iw_p1_poisoned; // @[core.scala:174:24]
wire bypasses_3_bits_uop_iw_p2_poisoned; // @[core.scala:174:24]
wire bypasses_3_bits_uop_is_br; // @[core.scala:174:24]
wire bypasses_3_bits_uop_is_jalr; // @[core.scala:174:24]
wire bypasses_3_bits_uop_is_jal; // @[core.scala:174:24]
wire bypasses_3_bits_uop_is_sfb; // @[core.scala:174:24]
wire [15:0] bypasses_3_bits_uop_br_mask; // @[core.scala:174:24]
wire [3:0] bypasses_3_bits_uop_br_tag; // @[core.scala:174:24]
wire [4:0] bypasses_3_bits_uop_ftq_idx; // @[core.scala:174:24]
wire bypasses_3_bits_uop_edge_inst; // @[core.scala:174:24]
wire [5:0] bypasses_3_bits_uop_pc_lob; // @[core.scala:174:24]
wire bypasses_3_bits_uop_taken; // @[core.scala:174:24]
wire [19:0] bypasses_3_bits_uop_imm_packed; // @[core.scala:174:24]
wire [11:0] bypasses_3_bits_uop_csr_addr; // @[core.scala:174:24]
wire [6:0] bypasses_3_bits_uop_rob_idx; // @[core.scala:174:24]
wire [4:0] bypasses_3_bits_uop_ldq_idx; // @[core.scala:174:24]
wire [4:0] bypasses_3_bits_uop_stq_idx; // @[core.scala:174:24]
wire [1:0] bypasses_3_bits_uop_rxq_idx; // @[core.scala:174:24]
wire [6:0] bypasses_3_bits_uop_pdst; // @[core.scala:174:24]
wire [6:0] bypasses_3_bits_uop_prs1; // @[core.scala:174:24]
wire [6:0] bypasses_3_bits_uop_prs2; // @[core.scala:174:24]
wire [6:0] bypasses_3_bits_uop_prs3; // @[core.scala:174:24]
wire [4:0] bypasses_3_bits_uop_ppred; // @[core.scala:174:24]
wire bypasses_3_bits_uop_prs1_busy; // @[core.scala:174:24]
wire bypasses_3_bits_uop_prs2_busy; // @[core.scala:174:24]
wire bypasses_3_bits_uop_prs3_busy; // @[core.scala:174:24]
wire bypasses_3_bits_uop_ppred_busy; // @[core.scala:174:24]
wire [6:0] bypasses_3_bits_uop_stale_pdst; // @[core.scala:174:24]
wire bypasses_3_bits_uop_exception; // @[core.scala:174:24]
wire [63:0] bypasses_3_bits_uop_exc_cause; // @[core.scala:174:24]
wire bypasses_3_bits_uop_bypassable; // @[core.scala:174:24]
wire [4:0] bypasses_3_bits_uop_mem_cmd; // @[core.scala:174:24]
wire [1:0] bypasses_3_bits_uop_mem_size; // @[core.scala:174:24]
wire bypasses_3_bits_uop_mem_signed; // @[core.scala:174:24]
wire bypasses_3_bits_uop_is_fence; // @[core.scala:174:24]
wire bypasses_3_bits_uop_is_fencei; // @[core.scala:174:24]
wire bypasses_3_bits_uop_is_amo; // @[core.scala:174:24]
wire bypasses_3_bits_uop_uses_ldq; // @[core.scala:174:24]
wire bypasses_3_bits_uop_uses_stq; // @[core.scala:174:24]
wire bypasses_3_bits_uop_is_sys_pc2epc; // @[core.scala:174:24]
wire bypasses_3_bits_uop_is_unique; // @[core.scala:174:24]
wire bypasses_3_bits_uop_flush_on_commit; // @[core.scala:174:24]
wire bypasses_3_bits_uop_ldst_is_rs1; // @[core.scala:174:24]
wire [5:0] bypasses_3_bits_uop_ldst; // @[core.scala:174:24]
wire [5:0] bypasses_3_bits_uop_lrs1; // @[core.scala:174:24]
wire [5:0] bypasses_3_bits_uop_lrs2; // @[core.scala:174:24]
wire [5:0] bypasses_3_bits_uop_lrs3; // @[core.scala:174:24]
wire bypasses_3_bits_uop_ldst_val; // @[core.scala:174:24]
wire [1:0] bypasses_3_bits_uop_dst_rtype; // @[core.scala:174:24]
wire [1:0] bypasses_3_bits_uop_lrs1_rtype; // @[core.scala:174:24]
wire [1:0] bypasses_3_bits_uop_lrs2_rtype; // @[core.scala:174:24]
wire bypasses_3_bits_uop_frs3_en; // @[core.scala:174:24]
wire bypasses_3_bits_uop_fp_val; // @[core.scala:174:24]
wire bypasses_3_bits_uop_fp_single; // @[core.scala:174:24]
wire bypasses_3_bits_uop_xcpt_pf_if; // @[core.scala:174:24]
wire bypasses_3_bits_uop_xcpt_ae_if; // @[core.scala:174:24]
wire bypasses_3_bits_uop_xcpt_ma_if; // @[core.scala:174:24]
wire bypasses_3_bits_uop_bp_debug_if; // @[core.scala:174:24]
wire bypasses_3_bits_uop_bp_xcpt_if; // @[core.scala:174:24]
wire [1:0] bypasses_3_bits_uop_debug_fsrc; // @[core.scala:174:24]
wire [1:0] bypasses_3_bits_uop_debug_tsrc; // @[core.scala:174:24]
wire [63:0] bypasses_3_bits_data; // @[core.scala:174:24]
wire bypasses_3_valid; // @[core.scala:174:24]
wire [3:0] bypasses_4_bits_uop_ctrl_br_type; // @[core.scala:174:24]
wire [1:0] bypasses_4_bits_uop_ctrl_op1_sel; // @[core.scala:174:24]
wire [2:0] bypasses_4_bits_uop_ctrl_op2_sel; // @[core.scala:174:24]
wire [2:0] bypasses_4_bits_uop_ctrl_imm_sel; // @[core.scala:174:24]
wire [4:0] bypasses_4_bits_uop_ctrl_op_fcn; // @[core.scala:174:24]
wire bypasses_4_bits_uop_ctrl_fcn_dw; // @[core.scala:174:24]
wire [2:0] bypasses_4_bits_uop_ctrl_csr_cmd; // @[core.scala:174:24]
wire bypasses_4_bits_uop_ctrl_is_load; // @[core.scala:174:24]
wire bypasses_4_bits_uop_ctrl_is_sta; // @[core.scala:174:24]
wire bypasses_4_bits_uop_ctrl_is_std; // @[core.scala:174:24]
wire [6:0] bypasses_4_bits_uop_uopc; // @[core.scala:174:24]
wire [31:0] bypasses_4_bits_uop_inst; // @[core.scala:174:24]
wire [31:0] bypasses_4_bits_uop_debug_inst; // @[core.scala:174:24]
wire bypasses_4_bits_uop_is_rvc; // @[core.scala:174:24]
wire [39:0] bypasses_4_bits_uop_debug_pc; // @[core.scala:174:24]
wire [2:0] bypasses_4_bits_uop_iq_type; // @[core.scala:174:24]
wire [9:0] bypasses_4_bits_uop_fu_code; // @[core.scala:174:24]
wire [1:0] bypasses_4_bits_uop_iw_state; // @[core.scala:174:24]
wire bypasses_4_bits_uop_iw_p1_poisoned; // @[core.scala:174:24]
wire bypasses_4_bits_uop_iw_p2_poisoned; // @[core.scala:174:24]
wire bypasses_4_bits_uop_is_br; // @[core.scala:174:24]
wire bypasses_4_bits_uop_is_jalr; // @[core.scala:174:24]
wire bypasses_4_bits_uop_is_jal; // @[core.scala:174:24]
wire bypasses_4_bits_uop_is_sfb; // @[core.scala:174:24]
wire [15:0] bypasses_4_bits_uop_br_mask; // @[core.scala:174:24]
wire [3:0] bypasses_4_bits_uop_br_tag; // @[core.scala:174:24]
wire [4:0] bypasses_4_bits_uop_ftq_idx; // @[core.scala:174:24]
wire bypasses_4_bits_uop_edge_inst; // @[core.scala:174:24]
wire [5:0] bypasses_4_bits_uop_pc_lob; // @[core.scala:174:24]
wire bypasses_4_bits_uop_taken; // @[core.scala:174:24]
wire [19:0] bypasses_4_bits_uop_imm_packed; // @[core.scala:174:24]
wire [11:0] bypasses_4_bits_uop_csr_addr; // @[core.scala:174:24]
wire [6:0] bypasses_4_bits_uop_rob_idx; // @[core.scala:174:24]
wire [4:0] bypasses_4_bits_uop_ldq_idx; // @[core.scala:174:24]
wire [4:0] bypasses_4_bits_uop_stq_idx; // @[core.scala:174:24]
wire [1:0] bypasses_4_bits_uop_rxq_idx; // @[core.scala:174:24]
wire [6:0] bypasses_4_bits_uop_pdst; // @[core.scala:174:24]
wire [6:0] bypasses_4_bits_uop_prs1; // @[core.scala:174:24]
wire [6:0] bypasses_4_bits_uop_prs2; // @[core.scala:174:24]
wire [6:0] bypasses_4_bits_uop_prs3; // @[core.scala:174:24]
wire [4:0] bypasses_4_bits_uop_ppred; // @[core.scala:174:24]
wire bypasses_4_bits_uop_prs1_busy; // @[core.scala:174:24]
wire bypasses_4_bits_uop_prs2_busy; // @[core.scala:174:24]
wire bypasses_4_bits_uop_prs3_busy; // @[core.scala:174:24]
wire bypasses_4_bits_uop_ppred_busy; // @[core.scala:174:24]
wire [6:0] bypasses_4_bits_uop_stale_pdst; // @[core.scala:174:24]
wire bypasses_4_bits_uop_exception; // @[core.scala:174:24]
wire [63:0] bypasses_4_bits_uop_exc_cause; // @[core.scala:174:24]
wire bypasses_4_bits_uop_bypassable; // @[core.scala:174:24]
wire [4:0] bypasses_4_bits_uop_mem_cmd; // @[core.scala:174:24]
wire [1:0] bypasses_4_bits_uop_mem_size; // @[core.scala:174:24]
wire bypasses_4_bits_uop_mem_signed; // @[core.scala:174:24]
wire bypasses_4_bits_uop_is_fence; // @[core.scala:174:24]
wire bypasses_4_bits_uop_is_fencei; // @[core.scala:174:24]
wire bypasses_4_bits_uop_is_amo; // @[core.scala:174:24]
wire bypasses_4_bits_uop_uses_ldq; // @[core.scala:174:24]
wire bypasses_4_bits_uop_uses_stq; // @[core.scala:174:24]
wire bypasses_4_bits_uop_is_sys_pc2epc; // @[core.scala:174:24]
wire bypasses_4_bits_uop_is_unique; // @[core.scala:174:24]
wire bypasses_4_bits_uop_flush_on_commit; // @[core.scala:174:24]
wire bypasses_4_bits_uop_ldst_is_rs1; // @[core.scala:174:24]
wire [5:0] bypasses_4_bits_uop_ldst; // @[core.scala:174:24]
wire [5:0] bypasses_4_bits_uop_lrs1; // @[core.scala:174:24]
wire [5:0] bypasses_4_bits_uop_lrs2; // @[core.scala:174:24]
wire [5:0] bypasses_4_bits_uop_lrs3; // @[core.scala:174:24]
wire bypasses_4_bits_uop_ldst_val; // @[core.scala:174:24]
wire [1:0] bypasses_4_bits_uop_dst_rtype; // @[core.scala:174:24]
wire [1:0] bypasses_4_bits_uop_lrs1_rtype; // @[core.scala:174:24]
wire [1:0] bypasses_4_bits_uop_lrs2_rtype; // @[core.scala:174:24]
wire bypasses_4_bits_uop_frs3_en; // @[core.scala:174:24]
wire bypasses_4_bits_uop_fp_val; // @[core.scala:174:24]
wire bypasses_4_bits_uop_fp_single; // @[core.scala:174:24]
wire bypasses_4_bits_uop_xcpt_pf_if; // @[core.scala:174:24]
wire bypasses_4_bits_uop_xcpt_ae_if; // @[core.scala:174:24]
wire bypasses_4_bits_uop_xcpt_ma_if; // @[core.scala:174:24]
wire bypasses_4_bits_uop_bp_debug_if; // @[core.scala:174:24]
wire bypasses_4_bits_uop_bp_xcpt_if; // @[core.scala:174:24]
wire [1:0] bypasses_4_bits_uop_debug_fsrc; // @[core.scala:174:24]
wire [1:0] bypasses_4_bits_uop_debug_tsrc; // @[core.scala:174:24]
wire [63:0] bypasses_4_bits_data; // @[core.scala:174:24]
wire bypasses_4_valid; // @[core.scala:174:24]
wire [3:0] pred_bypasses_0_bits_uop_ctrl_br_type; // @[core.scala:175:27]
wire [1:0] pred_bypasses_0_bits_uop_ctrl_op1_sel; // @[core.scala:175:27]
wire [2:0] pred_bypasses_0_bits_uop_ctrl_op2_sel; // @[core.scala:175:27]
wire [2:0] pred_bypasses_0_bits_uop_ctrl_imm_sel; // @[core.scala:175:27]
wire [4:0] pred_bypasses_0_bits_uop_ctrl_op_fcn; // @[core.scala:175:27]
wire pred_bypasses_0_bits_uop_ctrl_fcn_dw; // @[core.scala:175:27]
wire [2:0] pred_bypasses_0_bits_uop_ctrl_csr_cmd; // @[core.scala:175:27]
wire pred_bypasses_0_bits_uop_ctrl_is_load; // @[core.scala:175:27]
wire pred_bypasses_0_bits_uop_ctrl_is_sta; // @[core.scala:175:27]
wire pred_bypasses_0_bits_uop_ctrl_is_std; // @[core.scala:175:27]
wire [6:0] pred_bypasses_0_bits_uop_uopc; // @[core.scala:175:27]
wire [31:0] pred_bypasses_0_bits_uop_inst; // @[core.scala:175:27]
wire [31:0] pred_bypasses_0_bits_uop_debug_inst; // @[core.scala:175:27]
wire pred_bypasses_0_bits_uop_is_rvc; // @[core.scala:175:27]
wire [39:0] pred_bypasses_0_bits_uop_debug_pc; // @[core.scala:175:27]
wire [2:0] pred_bypasses_0_bits_uop_iq_type; // @[core.scala:175:27]
wire [9:0] pred_bypasses_0_bits_uop_fu_code; // @[core.scala:175:27]
wire [1:0] pred_bypasses_0_bits_uop_iw_state; // @[core.scala:175:27]
wire pred_bypasses_0_bits_uop_iw_p1_poisoned; // @[core.scala:175:27]
wire pred_bypasses_0_bits_uop_iw_p2_poisoned; // @[core.scala:175:27]
wire pred_bypasses_0_bits_uop_is_br; // @[core.scala:175:27]
wire pred_bypasses_0_bits_uop_is_jalr; // @[core.scala:175:27]
wire pred_bypasses_0_bits_uop_is_jal; // @[core.scala:175:27]
wire pred_bypasses_0_bits_uop_is_sfb; // @[core.scala:175:27]
wire [15:0] pred_bypasses_0_bits_uop_br_mask; // @[core.scala:175:27]
wire [3:0] pred_bypasses_0_bits_uop_br_tag; // @[core.scala:175:27]
wire [4:0] pred_bypasses_0_bits_uop_ftq_idx; // @[core.scala:175:27]
wire pred_bypasses_0_bits_uop_edge_inst; // @[core.scala:175:27]
wire [5:0] pred_bypasses_0_bits_uop_pc_lob; // @[core.scala:175:27]
wire pred_bypasses_0_bits_uop_taken; // @[core.scala:175:27]
wire [19:0] pred_bypasses_0_bits_uop_imm_packed; // @[core.scala:175:27]
wire [11:0] pred_bypasses_0_bits_uop_csr_addr; // @[core.scala:175:27]
wire [6:0] pred_bypasses_0_bits_uop_rob_idx; // @[core.scala:175:27]
wire [4:0] pred_bypasses_0_bits_uop_ldq_idx; // @[core.scala:175:27]
wire [4:0] pred_bypasses_0_bits_uop_stq_idx; // @[core.scala:175:27]
wire [1:0] pred_bypasses_0_bits_uop_rxq_idx; // @[core.scala:175:27]
wire [6:0] pred_bypasses_0_bits_uop_pdst; // @[core.scala:175:27]
wire [6:0] pred_bypasses_0_bits_uop_prs1; // @[core.scala:175:27]
wire [6:0] pred_bypasses_0_bits_uop_prs2; // @[core.scala:175:27]
wire [6:0] pred_bypasses_0_bits_uop_prs3; // @[core.scala:175:27]
wire [4:0] pred_bypasses_0_bits_uop_ppred; // @[core.scala:175:27]
wire pred_bypasses_0_bits_uop_prs1_busy; // @[core.scala:175:27]
wire pred_bypasses_0_bits_uop_prs2_busy; // @[core.scala:175:27]
wire pred_bypasses_0_bits_uop_prs3_busy; // @[core.scala:175:27]
wire pred_bypasses_0_bits_uop_ppred_busy; // @[core.scala:175:27]
wire [6:0] pred_bypasses_0_bits_uop_stale_pdst; // @[core.scala:175:27]
wire pred_bypasses_0_bits_uop_exception; // @[core.scala:175:27]
wire [63:0] pred_bypasses_0_bits_uop_exc_cause; // @[core.scala:175:27]
wire pred_bypasses_0_bits_uop_bypassable; // @[core.scala:175:27]
wire [4:0] pred_bypasses_0_bits_uop_mem_cmd; // @[core.scala:175:27]
wire [1:0] pred_bypasses_0_bits_uop_mem_size; // @[core.scala:175:27]
wire pred_bypasses_0_bits_uop_mem_signed; // @[core.scala:175:27]
wire pred_bypasses_0_bits_uop_is_fence; // @[core.scala:175:27]
wire pred_bypasses_0_bits_uop_is_fencei; // @[core.scala:175:27]
wire pred_bypasses_0_bits_uop_is_amo; // @[core.scala:175:27]
wire pred_bypasses_0_bits_uop_uses_ldq; // @[core.scala:175:27]
wire pred_bypasses_0_bits_uop_uses_stq; // @[core.scala:175:27]
wire pred_bypasses_0_bits_uop_is_sys_pc2epc; // @[core.scala:175:27]
wire pred_bypasses_0_bits_uop_is_unique; // @[core.scala:175:27]
wire pred_bypasses_0_bits_uop_flush_on_commit; // @[core.scala:175:27]
wire pred_bypasses_0_bits_uop_ldst_is_rs1; // @[core.scala:175:27]
wire [5:0] pred_bypasses_0_bits_uop_ldst; // @[core.scala:175:27]
wire [5:0] pred_bypasses_0_bits_uop_lrs1; // @[core.scala:175:27]
wire [5:0] pred_bypasses_0_bits_uop_lrs2; // @[core.scala:175:27]
wire [5:0] pred_bypasses_0_bits_uop_lrs3; // @[core.scala:175:27]
wire pred_bypasses_0_bits_uop_ldst_val; // @[core.scala:175:27]
wire [1:0] pred_bypasses_0_bits_uop_dst_rtype; // @[core.scala:175:27]
wire [1:0] pred_bypasses_0_bits_uop_lrs1_rtype; // @[core.scala:175:27]
wire [1:0] pred_bypasses_0_bits_uop_lrs2_rtype; // @[core.scala:175:27]
wire pred_bypasses_0_bits_uop_frs3_en; // @[core.scala:175:27]
wire pred_bypasses_0_bits_uop_fp_val; // @[core.scala:175:27]
wire pred_bypasses_0_bits_uop_fp_single; // @[core.scala:175:27]
wire pred_bypasses_0_bits_uop_xcpt_pf_if; // @[core.scala:175:27]
wire pred_bypasses_0_bits_uop_xcpt_ae_if; // @[core.scala:175:27]
wire pred_bypasses_0_bits_uop_xcpt_ma_if; // @[core.scala:175:27]
wire pred_bypasses_0_bits_uop_bp_debug_if; // @[core.scala:175:27]
wire pred_bypasses_0_bits_uop_bp_xcpt_if; // @[core.scala:175:27]
wire [1:0] pred_bypasses_0_bits_uop_debug_fsrc; // @[core.scala:175:27]
wire [1:0] pred_bypasses_0_bits_uop_debug_tsrc; // @[core.scala:175:27]
wire pred_bypasses_0_bits_data; // @[core.scala:175:27]
wire pred_bypasses_0_valid; // @[core.scala:175:27]
reg [6:0] brinfos_0_uop_uopc; // @[core.scala:182:20]
reg [31:0] brinfos_0_uop_inst; // @[core.scala:182:20]
reg [31:0] brinfos_0_uop_debug_inst; // @[core.scala:182:20]
reg brinfos_0_uop_is_rvc; // @[core.scala:182:20]
reg [39:0] brinfos_0_uop_debug_pc; // @[core.scala:182:20]
reg [2:0] brinfos_0_uop_iq_type; // @[core.scala:182:20]
reg [9:0] brinfos_0_uop_fu_code; // @[core.scala:182:20]
reg [3:0] brinfos_0_uop_ctrl_br_type; // @[core.scala:182:20]
reg [1:0] brinfos_0_uop_ctrl_op1_sel; // @[core.scala:182:20]
reg [2:0] brinfos_0_uop_ctrl_op2_sel; // @[core.scala:182:20]
reg [2:0] brinfos_0_uop_ctrl_imm_sel; // @[core.scala:182:20]
reg [4:0] brinfos_0_uop_ctrl_op_fcn; // @[core.scala:182:20]
reg brinfos_0_uop_ctrl_fcn_dw; // @[core.scala:182:20]
reg [2:0] brinfos_0_uop_ctrl_csr_cmd; // @[core.scala:182:20]
reg brinfos_0_uop_ctrl_is_load; // @[core.scala:182:20]
reg brinfos_0_uop_ctrl_is_sta; // @[core.scala:182:20]
reg brinfos_0_uop_ctrl_is_std; // @[core.scala:182:20]
reg [1:0] brinfos_0_uop_iw_state; // @[core.scala:182:20]
reg brinfos_0_uop_iw_p1_poisoned; // @[core.scala:182:20]
reg brinfos_0_uop_iw_p2_poisoned; // @[core.scala:182:20]
reg brinfos_0_uop_is_br; // @[core.scala:182:20]
reg brinfos_0_uop_is_jalr; // @[core.scala:182:20]
reg brinfos_0_uop_is_jal; // @[core.scala:182:20]
reg brinfos_0_uop_is_sfb; // @[core.scala:182:20]
reg [15:0] brinfos_0_uop_br_mask; // @[core.scala:182:20]
reg [3:0] brinfos_0_uop_br_tag; // @[core.scala:182:20]
reg [4:0] brinfos_0_uop_ftq_idx; // @[core.scala:182:20]
reg brinfos_0_uop_edge_inst; // @[core.scala:182:20]
reg [5:0] brinfos_0_uop_pc_lob; // @[core.scala:182:20]
reg brinfos_0_uop_taken; // @[core.scala:182:20]
reg [19:0] brinfos_0_uop_imm_packed; // @[core.scala:182:20]
reg [11:0] brinfos_0_uop_csr_addr; // @[core.scala:182:20]
reg [6:0] brinfos_0_uop_rob_idx; // @[core.scala:182:20]
reg [4:0] brinfos_0_uop_ldq_idx; // @[core.scala:182:20]
reg [4:0] brinfos_0_uop_stq_idx; // @[core.scala:182:20]
reg [1:0] brinfos_0_uop_rxq_idx; // @[core.scala:182:20]
reg [6:0] brinfos_0_uop_pdst; // @[core.scala:182:20]
reg [6:0] brinfos_0_uop_prs1; // @[core.scala:182:20]
reg [6:0] brinfos_0_uop_prs2; // @[core.scala:182:20]
reg [6:0] brinfos_0_uop_prs3; // @[core.scala:182:20]
reg [4:0] brinfos_0_uop_ppred; // @[core.scala:182:20]
reg brinfos_0_uop_prs1_busy; // @[core.scala:182:20]
reg brinfos_0_uop_prs2_busy; // @[core.scala:182:20]
reg brinfos_0_uop_prs3_busy; // @[core.scala:182:20]
reg brinfos_0_uop_ppred_busy; // @[core.scala:182:20]
reg [6:0] brinfos_0_uop_stale_pdst; // @[core.scala:182:20]
reg brinfos_0_uop_exception; // @[core.scala:182:20]
reg [63:0] brinfos_0_uop_exc_cause; // @[core.scala:182:20]
reg brinfos_0_uop_bypassable; // @[core.scala:182:20]
reg [4:0] brinfos_0_uop_mem_cmd; // @[core.scala:182:20]
reg [1:0] brinfos_0_uop_mem_size; // @[core.scala:182:20]
reg brinfos_0_uop_mem_signed; // @[core.scala:182:20]
reg brinfos_0_uop_is_fence; // @[core.scala:182:20]
reg brinfos_0_uop_is_fencei; // @[core.scala:182:20]
reg brinfos_0_uop_is_amo; // @[core.scala:182:20]
reg brinfos_0_uop_uses_ldq; // @[core.scala:182:20]
reg brinfos_0_uop_uses_stq; // @[core.scala:182:20]
reg brinfos_0_uop_is_sys_pc2epc; // @[core.scala:182:20]
reg brinfos_0_uop_is_unique; // @[core.scala:182:20]
reg brinfos_0_uop_flush_on_commit; // @[core.scala:182:20]
reg brinfos_0_uop_ldst_is_rs1; // @[core.scala:182:20]
reg [5:0] brinfos_0_uop_ldst; // @[core.scala:182:20]
reg [5:0] brinfos_0_uop_lrs1; // @[core.scala:182:20]
reg [5:0] brinfos_0_uop_lrs2; // @[core.scala:182:20]
reg [5:0] brinfos_0_uop_lrs3; // @[core.scala:182:20]
reg brinfos_0_uop_ldst_val; // @[core.scala:182:20]
reg [1:0] brinfos_0_uop_dst_rtype; // @[core.scala:182:20]
reg [1:0] brinfos_0_uop_lrs1_rtype; // @[core.scala:182:20]
reg [1:0] brinfos_0_uop_lrs2_rtype; // @[core.scala:182:20]
reg brinfos_0_uop_frs3_en; // @[core.scala:182:20]
reg brinfos_0_uop_fp_val; // @[core.scala:182:20]
reg brinfos_0_uop_fp_single; // @[core.scala:182:20]
reg brinfos_0_uop_xcpt_pf_if; // @[core.scala:182:20]
reg brinfos_0_uop_xcpt_ae_if; // @[core.scala:182:20]
reg brinfos_0_uop_xcpt_ma_if; // @[core.scala:182:20]
reg brinfos_0_uop_bp_debug_if; // @[core.scala:182:20]
reg brinfos_0_uop_bp_xcpt_if; // @[core.scala:182:20]
reg [1:0] brinfos_0_uop_debug_fsrc; // @[core.scala:182:20]
reg [1:0] brinfos_0_uop_debug_tsrc; // @[core.scala:182:20]
reg brinfos_0_valid; // @[core.scala:182:20]
reg brinfos_0_mispredict; // @[core.scala:182:20]
reg brinfos_0_taken; // @[core.scala:182:20]
reg [2:0] brinfos_0_cfi_type; // @[core.scala:182:20]
reg [1:0] brinfos_0_pc_sel; // @[core.scala:182:20]
reg [39:0] brinfos_0_jalr_target; // @[core.scala:182:20]
reg [20:0] brinfos_0_target_offset; // @[core.scala:182:20]
reg [6:0] brinfos_1_uop_uopc; // @[core.scala:182:20]
reg [31:0] brinfos_1_uop_inst; // @[core.scala:182:20]
reg [31:0] brinfos_1_uop_debug_inst; // @[core.scala:182:20]
reg brinfos_1_uop_is_rvc; // @[core.scala:182:20]
reg [39:0] brinfos_1_uop_debug_pc; // @[core.scala:182:20]
reg [2:0] brinfos_1_uop_iq_type; // @[core.scala:182:20]
reg [9:0] brinfos_1_uop_fu_code; // @[core.scala:182:20]
reg [3:0] brinfos_1_uop_ctrl_br_type; // @[core.scala:182:20]
reg [1:0] brinfos_1_uop_ctrl_op1_sel; // @[core.scala:182:20]
reg [2:0] brinfos_1_uop_ctrl_op2_sel; // @[core.scala:182:20]
reg [2:0] brinfos_1_uop_ctrl_imm_sel; // @[core.scala:182:20]
reg [4:0] brinfos_1_uop_ctrl_op_fcn; // @[core.scala:182:20]
reg brinfos_1_uop_ctrl_fcn_dw; // @[core.scala:182:20]
reg [2:0] brinfos_1_uop_ctrl_csr_cmd; // @[core.scala:182:20]
reg brinfos_1_uop_ctrl_is_load; // @[core.scala:182:20]
reg brinfos_1_uop_ctrl_is_sta; // @[core.scala:182:20]
reg brinfos_1_uop_ctrl_is_std; // @[core.scala:182:20]
reg [1:0] brinfos_1_uop_iw_state; // @[core.scala:182:20]
reg brinfos_1_uop_iw_p1_poisoned; // @[core.scala:182:20]
reg brinfos_1_uop_iw_p2_poisoned; // @[core.scala:182:20]
reg brinfos_1_uop_is_br; // @[core.scala:182:20]
reg brinfos_1_uop_is_jalr; // @[core.scala:182:20]
reg brinfos_1_uop_is_jal; // @[core.scala:182:20]
reg brinfos_1_uop_is_sfb; // @[core.scala:182:20]
reg [15:0] brinfos_1_uop_br_mask; // @[core.scala:182:20]
reg [3:0] brinfos_1_uop_br_tag; // @[core.scala:182:20]
reg [4:0] brinfos_1_uop_ftq_idx; // @[core.scala:182:20]
reg brinfos_1_uop_edge_inst; // @[core.scala:182:20]
reg [5:0] brinfos_1_uop_pc_lob; // @[core.scala:182:20]
reg brinfos_1_uop_taken; // @[core.scala:182:20]
reg [19:0] brinfos_1_uop_imm_packed; // @[core.scala:182:20]
reg [11:0] brinfos_1_uop_csr_addr; // @[core.scala:182:20]
reg [6:0] brinfos_1_uop_rob_idx; // @[core.scala:182:20]
reg [4:0] brinfos_1_uop_ldq_idx; // @[core.scala:182:20]
reg [4:0] brinfos_1_uop_stq_idx; // @[core.scala:182:20]
reg [1:0] brinfos_1_uop_rxq_idx; // @[core.scala:182:20]
reg [6:0] brinfos_1_uop_pdst; // @[core.scala:182:20]
reg [6:0] brinfos_1_uop_prs1; // @[core.scala:182:20]
reg [6:0] brinfos_1_uop_prs2; // @[core.scala:182:20]
reg [6:0] brinfos_1_uop_prs3; // @[core.scala:182:20]
reg [4:0] brinfos_1_uop_ppred; // @[core.scala:182:20]
reg brinfos_1_uop_prs1_busy; // @[core.scala:182:20]
reg brinfos_1_uop_prs2_busy; // @[core.scala:182:20]
reg brinfos_1_uop_prs3_busy; // @[core.scala:182:20]
reg brinfos_1_uop_ppred_busy; // @[core.scala:182:20]
reg [6:0] brinfos_1_uop_stale_pdst; // @[core.scala:182:20]
reg brinfos_1_uop_exception; // @[core.scala:182:20]
reg [63:0] brinfos_1_uop_exc_cause; // @[core.scala:182:20]
reg brinfos_1_uop_bypassable; // @[core.scala:182:20]
reg [4:0] brinfos_1_uop_mem_cmd; // @[core.scala:182:20]
reg [1:0] brinfos_1_uop_mem_size; // @[core.scala:182:20]
reg brinfos_1_uop_mem_signed; // @[core.scala:182:20]
reg brinfos_1_uop_is_fence; // @[core.scala:182:20]
reg brinfos_1_uop_is_fencei; // @[core.scala:182:20]
reg brinfos_1_uop_is_amo; // @[core.scala:182:20]
reg brinfos_1_uop_uses_ldq; // @[core.scala:182:20]
reg brinfos_1_uop_uses_stq; // @[core.scala:182:20]
reg brinfos_1_uop_is_sys_pc2epc; // @[core.scala:182:20]
reg brinfos_1_uop_is_unique; // @[core.scala:182:20]
reg brinfos_1_uop_flush_on_commit; // @[core.scala:182:20]
reg brinfos_1_uop_ldst_is_rs1; // @[core.scala:182:20]
reg [5:0] brinfos_1_uop_ldst; // @[core.scala:182:20]
reg [5:0] brinfos_1_uop_lrs1; // @[core.scala:182:20]
reg [5:0] brinfos_1_uop_lrs2; // @[core.scala:182:20]
reg [5:0] brinfos_1_uop_lrs3; // @[core.scala:182:20]
reg brinfos_1_uop_ldst_val; // @[core.scala:182:20]
reg [1:0] brinfos_1_uop_dst_rtype; // @[core.scala:182:20]
reg [1:0] brinfos_1_uop_lrs1_rtype; // @[core.scala:182:20]
reg [1:0] brinfos_1_uop_lrs2_rtype; // @[core.scala:182:20]
reg brinfos_1_uop_frs3_en; // @[core.scala:182:20]
reg brinfos_1_uop_fp_val; // @[core.scala:182:20]
reg brinfos_1_uop_fp_single; // @[core.scala:182:20]
reg brinfos_1_uop_xcpt_pf_if; // @[core.scala:182:20]
reg brinfos_1_uop_xcpt_ae_if; // @[core.scala:182:20]
reg brinfos_1_uop_xcpt_ma_if; // @[core.scala:182:20]
reg brinfos_1_uop_bp_debug_if; // @[core.scala:182:20]
reg brinfos_1_uop_bp_xcpt_if; // @[core.scala:182:20]
reg [1:0] brinfos_1_uop_debug_fsrc; // @[core.scala:182:20]
reg [1:0] brinfos_1_uop_debug_tsrc; // @[core.scala:182:20]
reg brinfos_1_valid; // @[core.scala:182:20]
reg brinfos_1_mispredict; // @[core.scala:182:20]
reg brinfos_1_taken; // @[core.scala:182:20]
reg [2:0] brinfos_1_cfi_type; // @[core.scala:182:20]
reg [1:0] brinfos_1_pc_sel; // @[core.scala:182:20]
reg [20:0] brinfos_1_target_offset; // @[core.scala:182:20]
reg [6:0] brinfos_2_uop_uopc; // @[core.scala:182:20]
reg [31:0] brinfos_2_uop_inst; // @[core.scala:182:20]
reg [31:0] brinfos_2_uop_debug_inst; // @[core.scala:182:20]
reg brinfos_2_uop_is_rvc; // @[core.scala:182:20]
reg [39:0] brinfos_2_uop_debug_pc; // @[core.scala:182:20]
reg [2:0] brinfos_2_uop_iq_type; // @[core.scala:182:20]
reg [9:0] brinfos_2_uop_fu_code; // @[core.scala:182:20]
reg [3:0] brinfos_2_uop_ctrl_br_type; // @[core.scala:182:20]
reg [1:0] brinfos_2_uop_ctrl_op1_sel; // @[core.scala:182:20]
reg [2:0] brinfos_2_uop_ctrl_op2_sel; // @[core.scala:182:20]
reg [2:0] brinfos_2_uop_ctrl_imm_sel; // @[core.scala:182:20]
reg [4:0] brinfos_2_uop_ctrl_op_fcn; // @[core.scala:182:20]
reg brinfos_2_uop_ctrl_fcn_dw; // @[core.scala:182:20]
reg [2:0] brinfos_2_uop_ctrl_csr_cmd; // @[core.scala:182:20]
reg brinfos_2_uop_ctrl_is_load; // @[core.scala:182:20]
reg brinfos_2_uop_ctrl_is_sta; // @[core.scala:182:20]
reg brinfos_2_uop_ctrl_is_std; // @[core.scala:182:20]
reg [1:0] brinfos_2_uop_iw_state; // @[core.scala:182:20]
reg brinfos_2_uop_iw_p1_poisoned; // @[core.scala:182:20]
reg brinfos_2_uop_iw_p2_poisoned; // @[core.scala:182:20]
reg brinfos_2_uop_is_br; // @[core.scala:182:20]
reg brinfos_2_uop_is_jalr; // @[core.scala:182:20]
reg brinfos_2_uop_is_jal; // @[core.scala:182:20]
reg brinfos_2_uop_is_sfb; // @[core.scala:182:20]
reg [15:0] brinfos_2_uop_br_mask; // @[core.scala:182:20]
reg [3:0] brinfos_2_uop_br_tag; // @[core.scala:182:20]
reg [4:0] brinfos_2_uop_ftq_idx; // @[core.scala:182:20]
reg brinfos_2_uop_edge_inst; // @[core.scala:182:20]
reg [5:0] brinfos_2_uop_pc_lob; // @[core.scala:182:20]
reg brinfos_2_uop_taken; // @[core.scala:182:20]
reg [19:0] brinfos_2_uop_imm_packed; // @[core.scala:182:20]
reg [11:0] brinfos_2_uop_csr_addr; // @[core.scala:182:20]
reg [6:0] brinfos_2_uop_rob_idx; // @[core.scala:182:20]
reg [4:0] brinfos_2_uop_ldq_idx; // @[core.scala:182:20]
reg [4:0] brinfos_2_uop_stq_idx; // @[core.scala:182:20]
reg [1:0] brinfos_2_uop_rxq_idx; // @[core.scala:182:20]
reg [6:0] brinfos_2_uop_pdst; // @[core.scala:182:20]
reg [6:0] brinfos_2_uop_prs1; // @[core.scala:182:20]
reg [6:0] brinfos_2_uop_prs2; // @[core.scala:182:20]
reg [6:0] brinfos_2_uop_prs3; // @[core.scala:182:20]
reg [4:0] brinfos_2_uop_ppred; // @[core.scala:182:20]
reg brinfos_2_uop_prs1_busy; // @[core.scala:182:20]
reg brinfos_2_uop_prs2_busy; // @[core.scala:182:20]
reg brinfos_2_uop_prs3_busy; // @[core.scala:182:20]
reg brinfos_2_uop_ppred_busy; // @[core.scala:182:20]
reg [6:0] brinfos_2_uop_stale_pdst; // @[core.scala:182:20]
reg brinfos_2_uop_exception; // @[core.scala:182:20]
reg [63:0] brinfos_2_uop_exc_cause; // @[core.scala:182:20]
reg brinfos_2_uop_bypassable; // @[core.scala:182:20]
reg [4:0] brinfos_2_uop_mem_cmd; // @[core.scala:182:20]
reg [1:0] brinfos_2_uop_mem_size; // @[core.scala:182:20]
reg brinfos_2_uop_mem_signed; // @[core.scala:182:20]
reg brinfos_2_uop_is_fence; // @[core.scala:182:20]
reg brinfos_2_uop_is_fencei; // @[core.scala:182:20]
reg brinfos_2_uop_is_amo; // @[core.scala:182:20]
reg brinfos_2_uop_uses_ldq; // @[core.scala:182:20]
reg brinfos_2_uop_uses_stq; // @[core.scala:182:20]
reg brinfos_2_uop_is_sys_pc2epc; // @[core.scala:182:20]
reg brinfos_2_uop_is_unique; // @[core.scala:182:20]
reg brinfos_2_uop_flush_on_commit; // @[core.scala:182:20]
reg brinfos_2_uop_ldst_is_rs1; // @[core.scala:182:20]
reg [5:0] brinfos_2_uop_ldst; // @[core.scala:182:20]
reg [5:0] brinfos_2_uop_lrs1; // @[core.scala:182:20]
reg [5:0] brinfos_2_uop_lrs2; // @[core.scala:182:20]
reg [5:0] brinfos_2_uop_lrs3; // @[core.scala:182:20]
reg brinfos_2_uop_ldst_val; // @[core.scala:182:20]
reg [1:0] brinfos_2_uop_dst_rtype; // @[core.scala:182:20]
reg [1:0] brinfos_2_uop_lrs1_rtype; // @[core.scala:182:20]
reg [1:0] brinfos_2_uop_lrs2_rtype; // @[core.scala:182:20]
reg brinfos_2_uop_frs3_en; // @[core.scala:182:20]
reg brinfos_2_uop_fp_val; // @[core.scala:182:20]
reg brinfos_2_uop_fp_single; // @[core.scala:182:20]
reg brinfos_2_uop_xcpt_pf_if; // @[core.scala:182:20]
reg brinfos_2_uop_xcpt_ae_if; // @[core.scala:182:20]
reg brinfos_2_uop_xcpt_ma_if; // @[core.scala:182:20]
reg brinfos_2_uop_bp_debug_if; // @[core.scala:182:20]
reg brinfos_2_uop_bp_xcpt_if; // @[core.scala:182:20]
reg [1:0] brinfos_2_uop_debug_fsrc; // @[core.scala:182:20]
reg [1:0] brinfos_2_uop_debug_tsrc; // @[core.scala:182:20]
reg brinfos_2_valid; // @[core.scala:182:20]
reg brinfos_2_mispredict; // @[core.scala:182:20]
reg brinfos_2_taken; // @[core.scala:182:20]
reg [2:0] brinfos_2_cfi_type; // @[core.scala:182:20]
reg [1:0] brinfos_2_pc_sel; // @[core.scala:182:20]
reg [20:0] brinfos_2_target_offset; // @[core.scala:182:20]
wire [15:0] b1_resolve_mask; // @[core.scala:189:19]
assign io_ifu_brupdate_b1_resolve_mask_0 = brupdate_b1_resolve_mask; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b1_resolve_mask_0 = brupdate_b1_resolve_mask; // @[core.scala:51:7, :188:23]
wire [15:0] b1_mispredict_mask; // @[core.scala:189:19]
assign io_ifu_brupdate_b1_mispredict_mask_0 = brupdate_b1_mispredict_mask; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b1_mispredict_mask_0 = brupdate_b1_mispredict_mask; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_uopc_0 = brupdate_b2_uop_uopc; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_uopc_0 = brupdate_b2_uop_uopc; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_inst_0 = brupdate_b2_uop_inst; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_inst_0 = brupdate_b2_uop_inst; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_debug_inst_0 = brupdate_b2_uop_debug_inst; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_debug_inst_0 = brupdate_b2_uop_debug_inst; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_is_rvc_0 = brupdate_b2_uop_is_rvc; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_is_rvc_0 = brupdate_b2_uop_is_rvc; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_debug_pc_0 = brupdate_b2_uop_debug_pc; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_debug_pc_0 = brupdate_b2_uop_debug_pc; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_iq_type_0 = brupdate_b2_uop_iq_type; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_iq_type_0 = brupdate_b2_uop_iq_type; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_fu_code_0 = brupdate_b2_uop_fu_code; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_fu_code_0 = brupdate_b2_uop_fu_code; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_ctrl_br_type_0 = brupdate_b2_uop_ctrl_br_type; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_ctrl_br_type_0 = brupdate_b2_uop_ctrl_br_type; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_ctrl_op1_sel_0 = brupdate_b2_uop_ctrl_op1_sel; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_ctrl_op1_sel_0 = brupdate_b2_uop_ctrl_op1_sel; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_ctrl_op2_sel_0 = brupdate_b2_uop_ctrl_op2_sel; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_ctrl_op2_sel_0 = brupdate_b2_uop_ctrl_op2_sel; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_ctrl_imm_sel_0 = brupdate_b2_uop_ctrl_imm_sel; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_ctrl_imm_sel_0 = brupdate_b2_uop_ctrl_imm_sel; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_ctrl_op_fcn_0 = brupdate_b2_uop_ctrl_op_fcn; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_ctrl_op_fcn_0 = brupdate_b2_uop_ctrl_op_fcn; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_ctrl_fcn_dw_0 = brupdate_b2_uop_ctrl_fcn_dw; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_ctrl_fcn_dw_0 = brupdate_b2_uop_ctrl_fcn_dw; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_ctrl_csr_cmd_0 = brupdate_b2_uop_ctrl_csr_cmd; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_ctrl_csr_cmd_0 = brupdate_b2_uop_ctrl_csr_cmd; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_ctrl_is_load_0 = brupdate_b2_uop_ctrl_is_load; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_ctrl_is_load_0 = brupdate_b2_uop_ctrl_is_load; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_ctrl_is_sta_0 = brupdate_b2_uop_ctrl_is_sta; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_ctrl_is_sta_0 = brupdate_b2_uop_ctrl_is_sta; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_ctrl_is_std_0 = brupdate_b2_uop_ctrl_is_std; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_ctrl_is_std_0 = brupdate_b2_uop_ctrl_is_std; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_iw_state_0 = brupdate_b2_uop_iw_state; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_iw_state_0 = brupdate_b2_uop_iw_state; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_iw_p1_poisoned_0 = brupdate_b2_uop_iw_p1_poisoned; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_iw_p1_poisoned_0 = brupdate_b2_uop_iw_p1_poisoned; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_iw_p2_poisoned_0 = brupdate_b2_uop_iw_p2_poisoned; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_iw_p2_poisoned_0 = brupdate_b2_uop_iw_p2_poisoned; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_is_br_0 = brupdate_b2_uop_is_br; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_is_br_0 = brupdate_b2_uop_is_br; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_is_jalr_0 = brupdate_b2_uop_is_jalr; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_is_jalr_0 = brupdate_b2_uop_is_jalr; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_is_jal_0 = brupdate_b2_uop_is_jal; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_is_jal_0 = brupdate_b2_uop_is_jal; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_is_sfb_0 = brupdate_b2_uop_is_sfb; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_is_sfb_0 = brupdate_b2_uop_is_sfb; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_br_mask_0 = brupdate_b2_uop_br_mask; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_br_mask_0 = brupdate_b2_uop_br_mask; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_br_tag_0 = brupdate_b2_uop_br_tag; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_br_tag_0 = brupdate_b2_uop_br_tag; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_ftq_idx_0 = brupdate_b2_uop_ftq_idx; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_ftq_idx_0 = brupdate_b2_uop_ftq_idx; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_edge_inst_0 = brupdate_b2_uop_edge_inst; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_edge_inst_0 = brupdate_b2_uop_edge_inst; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_pc_lob_0 = brupdate_b2_uop_pc_lob; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_pc_lob_0 = brupdate_b2_uop_pc_lob; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_taken_0 = brupdate_b2_uop_taken; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_taken_0 = brupdate_b2_uop_taken; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_imm_packed_0 = brupdate_b2_uop_imm_packed; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_imm_packed_0 = brupdate_b2_uop_imm_packed; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_csr_addr_0 = brupdate_b2_uop_csr_addr; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_csr_addr_0 = brupdate_b2_uop_csr_addr; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_rob_idx_0 = brupdate_b2_uop_rob_idx; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_rob_idx_0 = brupdate_b2_uop_rob_idx; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_ldq_idx_0 = brupdate_b2_uop_ldq_idx; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_ldq_idx_0 = brupdate_b2_uop_ldq_idx; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_stq_idx_0 = brupdate_b2_uop_stq_idx; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_stq_idx_0 = brupdate_b2_uop_stq_idx; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_rxq_idx_0 = brupdate_b2_uop_rxq_idx; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_rxq_idx_0 = brupdate_b2_uop_rxq_idx; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_pdst_0 = brupdate_b2_uop_pdst; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_pdst_0 = brupdate_b2_uop_pdst; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_prs1_0 = brupdate_b2_uop_prs1; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_prs1_0 = brupdate_b2_uop_prs1; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_prs2_0 = brupdate_b2_uop_prs2; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_prs2_0 = brupdate_b2_uop_prs2; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_prs3_0 = brupdate_b2_uop_prs3; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_prs3_0 = brupdate_b2_uop_prs3; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_ppred_0 = brupdate_b2_uop_ppred; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_ppred_0 = brupdate_b2_uop_ppred; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_prs1_busy_0 = brupdate_b2_uop_prs1_busy; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_prs1_busy_0 = brupdate_b2_uop_prs1_busy; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_prs2_busy_0 = brupdate_b2_uop_prs2_busy; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_prs2_busy_0 = brupdate_b2_uop_prs2_busy; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_prs3_busy_0 = brupdate_b2_uop_prs3_busy; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_prs3_busy_0 = brupdate_b2_uop_prs3_busy; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_ppred_busy_0 = brupdate_b2_uop_ppred_busy; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_ppred_busy_0 = brupdate_b2_uop_ppred_busy; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_stale_pdst_0 = brupdate_b2_uop_stale_pdst; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_stale_pdst_0 = brupdate_b2_uop_stale_pdst; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_exception_0 = brupdate_b2_uop_exception; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_exception_0 = brupdate_b2_uop_exception; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_exc_cause_0 = brupdate_b2_uop_exc_cause; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_exc_cause_0 = brupdate_b2_uop_exc_cause; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_bypassable_0 = brupdate_b2_uop_bypassable; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_bypassable_0 = brupdate_b2_uop_bypassable; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_mem_cmd_0 = brupdate_b2_uop_mem_cmd; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_mem_cmd_0 = brupdate_b2_uop_mem_cmd; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_mem_size_0 = brupdate_b2_uop_mem_size; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_mem_size_0 = brupdate_b2_uop_mem_size; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_mem_signed_0 = brupdate_b2_uop_mem_signed; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_mem_signed_0 = brupdate_b2_uop_mem_signed; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_is_fence_0 = brupdate_b2_uop_is_fence; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_is_fence_0 = brupdate_b2_uop_is_fence; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_is_fencei_0 = brupdate_b2_uop_is_fencei; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_is_fencei_0 = brupdate_b2_uop_is_fencei; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_is_amo_0 = brupdate_b2_uop_is_amo; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_is_amo_0 = brupdate_b2_uop_is_amo; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_uses_ldq_0 = brupdate_b2_uop_uses_ldq; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_uses_ldq_0 = brupdate_b2_uop_uses_ldq; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_uses_stq_0 = brupdate_b2_uop_uses_stq; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_uses_stq_0 = brupdate_b2_uop_uses_stq; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_is_sys_pc2epc_0 = brupdate_b2_uop_is_sys_pc2epc; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_is_sys_pc2epc_0 = brupdate_b2_uop_is_sys_pc2epc; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_is_unique_0 = brupdate_b2_uop_is_unique; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_is_unique_0 = brupdate_b2_uop_is_unique; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_flush_on_commit_0 = brupdate_b2_uop_flush_on_commit; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_flush_on_commit_0 = brupdate_b2_uop_flush_on_commit; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_ldst_is_rs1_0 = brupdate_b2_uop_ldst_is_rs1; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_ldst_is_rs1_0 = brupdate_b2_uop_ldst_is_rs1; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_ldst_0 = brupdate_b2_uop_ldst; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_ldst_0 = brupdate_b2_uop_ldst; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_lrs1_0 = brupdate_b2_uop_lrs1; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_lrs1_0 = brupdate_b2_uop_lrs1; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_lrs2_0 = brupdate_b2_uop_lrs2; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_lrs2_0 = brupdate_b2_uop_lrs2; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_lrs3_0 = brupdate_b2_uop_lrs3; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_lrs3_0 = brupdate_b2_uop_lrs3; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_ldst_val_0 = brupdate_b2_uop_ldst_val; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_ldst_val_0 = brupdate_b2_uop_ldst_val; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_dst_rtype_0 = brupdate_b2_uop_dst_rtype; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_dst_rtype_0 = brupdate_b2_uop_dst_rtype; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_lrs1_rtype_0 = brupdate_b2_uop_lrs1_rtype; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_lrs1_rtype_0 = brupdate_b2_uop_lrs1_rtype; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_lrs2_rtype_0 = brupdate_b2_uop_lrs2_rtype; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_lrs2_rtype_0 = brupdate_b2_uop_lrs2_rtype; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_frs3_en_0 = brupdate_b2_uop_frs3_en; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_frs3_en_0 = brupdate_b2_uop_frs3_en; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_fp_val_0 = brupdate_b2_uop_fp_val; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_fp_val_0 = brupdate_b2_uop_fp_val; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_fp_single_0 = brupdate_b2_uop_fp_single; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_fp_single_0 = brupdate_b2_uop_fp_single; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_xcpt_pf_if_0 = brupdate_b2_uop_xcpt_pf_if; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_xcpt_pf_if_0 = brupdate_b2_uop_xcpt_pf_if; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_xcpt_ae_if_0 = brupdate_b2_uop_xcpt_ae_if; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_xcpt_ae_if_0 = brupdate_b2_uop_xcpt_ae_if; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_xcpt_ma_if_0 = brupdate_b2_uop_xcpt_ma_if; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_xcpt_ma_if_0 = brupdate_b2_uop_xcpt_ma_if; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_bp_debug_if_0 = brupdate_b2_uop_bp_debug_if; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_bp_debug_if_0 = brupdate_b2_uop_bp_debug_if; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_bp_xcpt_if_0 = brupdate_b2_uop_bp_xcpt_if; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_bp_xcpt_if_0 = brupdate_b2_uop_bp_xcpt_if; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_debug_fsrc_0 = brupdate_b2_uop_debug_fsrc; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_debug_fsrc_0 = brupdate_b2_uop_debug_fsrc; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_uop_debug_tsrc_0 = brupdate_b2_uop_debug_tsrc; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_uop_debug_tsrc_0 = brupdate_b2_uop_debug_tsrc; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_valid_0 = brupdate_b2_valid; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_valid_0 = brupdate_b2_valid; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_mispredict_0 = brupdate_b2_mispredict; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_mispredict_0 = brupdate_b2_mispredict; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_taken_0 = brupdate_b2_taken; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_taken_0 = brupdate_b2_taken; // @[core.scala:51:7, :188:23]
wire _next_ghist_cfi_in_bank_0_T = brupdate_b2_taken; // @[frontend.scala:104:37]
wire _next_ghist_new_history_new_saw_branch_taken_T_1 = brupdate_b2_taken; // @[frontend.scala:119:59]
assign io_ifu_brupdate_b2_cfi_type_0 = brupdate_b2_cfi_type; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_cfi_type_0 = brupdate_b2_cfi_type; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_pc_sel_0 = brupdate_b2_pc_sel; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_pc_sel_0 = brupdate_b2_pc_sel; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_jalr_target_0 = brupdate_b2_jalr_target; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_jalr_target_0 = brupdate_b2_jalr_target; // @[core.scala:51:7, :188:23]
assign io_ifu_brupdate_b2_target_offset_0 = brupdate_b2_target_offset; // @[core.scala:51:7, :188:23]
assign io_lsu_brupdate_b2_target_offset_0 = brupdate_b2_target_offset; // @[core.scala:51:7, :188:23]
wire [15:0] _b1_resolve_mask_T_4; // @[core.scala:199:72]
assign brupdate_b1_resolve_mask = b1_resolve_mask; // @[core.scala:188:23, :189:19]
wire [15:0] _b1_mispredict_mask_T_7; // @[core.scala:200:93]
assign brupdate_b1_mispredict_mask = b1_mispredict_mask; // @[core.scala:188:23, :189:19]
reg [6:0] b2_uop_uopc; // @[core.scala:190:18]
assign brupdate_b2_uop_uopc = b2_uop_uopc; // @[core.scala:188:23, :190:18]
reg [31:0] b2_uop_inst; // @[core.scala:190:18]
assign brupdate_b2_uop_inst = b2_uop_inst; // @[core.scala:188:23, :190:18]
reg [31:0] b2_uop_debug_inst; // @[core.scala:190:18]
assign brupdate_b2_uop_debug_inst = b2_uop_debug_inst; // @[core.scala:188:23, :190:18]
reg b2_uop_is_rvc; // @[core.scala:190:18]
assign brupdate_b2_uop_is_rvc = b2_uop_is_rvc; // @[core.scala:188:23, :190:18]
reg [39:0] b2_uop_debug_pc; // @[core.scala:190:18]
assign brupdate_b2_uop_debug_pc = b2_uop_debug_pc; // @[core.scala:188:23, :190:18]
reg [2:0] b2_uop_iq_type; // @[core.scala:190:18]
assign brupdate_b2_uop_iq_type = b2_uop_iq_type; // @[core.scala:188:23, :190:18]
reg [9:0] b2_uop_fu_code; // @[core.scala:190:18]
assign brupdate_b2_uop_fu_code = b2_uop_fu_code; // @[core.scala:188:23, :190:18]
reg [3:0] b2_uop_ctrl_br_type; // @[core.scala:190:18]
assign brupdate_b2_uop_ctrl_br_type = b2_uop_ctrl_br_type; // @[core.scala:188:23, :190:18]
reg [1:0] b2_uop_ctrl_op1_sel; // @[core.scala:190:18]
assign brupdate_b2_uop_ctrl_op1_sel = b2_uop_ctrl_op1_sel; // @[core.scala:188:23, :190:18]
reg [2:0] b2_uop_ctrl_op2_sel; // @[core.scala:190:18]
assign brupdate_b2_uop_ctrl_op2_sel = b2_uop_ctrl_op2_sel; // @[core.scala:188:23, :190:18]
reg [2:0] b2_uop_ctrl_imm_sel; // @[core.scala:190:18]
assign brupdate_b2_uop_ctrl_imm_sel = b2_uop_ctrl_imm_sel; // @[core.scala:188:23, :190:18]
reg [4:0] b2_uop_ctrl_op_fcn; // @[core.scala:190:18]
assign brupdate_b2_uop_ctrl_op_fcn = b2_uop_ctrl_op_fcn; // @[core.scala:188:23, :190:18]
reg b2_uop_ctrl_fcn_dw; // @[core.scala:190:18]
assign brupdate_b2_uop_ctrl_fcn_dw = b2_uop_ctrl_fcn_dw; // @[core.scala:188:23, :190:18]
reg [2:0] b2_uop_ctrl_csr_cmd; // @[core.scala:190:18]
assign brupdate_b2_uop_ctrl_csr_cmd = b2_uop_ctrl_csr_cmd; // @[core.scala:188:23, :190:18]
reg b2_uop_ctrl_is_load; // @[core.scala:190:18]
assign brupdate_b2_uop_ctrl_is_load = b2_uop_ctrl_is_load; // @[core.scala:188:23, :190:18]
reg b2_uop_ctrl_is_sta; // @[core.scala:190:18]
assign brupdate_b2_uop_ctrl_is_sta = b2_uop_ctrl_is_sta; // @[core.scala:188:23, :190:18]
reg b2_uop_ctrl_is_std; // @[core.scala:190:18]
assign brupdate_b2_uop_ctrl_is_std = b2_uop_ctrl_is_std; // @[core.scala:188:23, :190:18]
reg [1:0] b2_uop_iw_state; // @[core.scala:190:18]
assign brupdate_b2_uop_iw_state = b2_uop_iw_state; // @[core.scala:188:23, :190:18]
reg b2_uop_iw_p1_poisoned; // @[core.scala:190:18]
assign brupdate_b2_uop_iw_p1_poisoned = b2_uop_iw_p1_poisoned; // @[core.scala:188:23, :190:18]
reg b2_uop_iw_p2_poisoned; // @[core.scala:190:18]
assign brupdate_b2_uop_iw_p2_poisoned = b2_uop_iw_p2_poisoned; // @[core.scala:188:23, :190:18]
reg b2_uop_is_br; // @[core.scala:190:18]
assign brupdate_b2_uop_is_br = b2_uop_is_br; // @[core.scala:188:23, :190:18]
reg b2_uop_is_jalr; // @[core.scala:190:18]
assign brupdate_b2_uop_is_jalr = b2_uop_is_jalr; // @[core.scala:188:23, :190:18]
reg b2_uop_is_jal; // @[core.scala:190:18]
assign brupdate_b2_uop_is_jal = b2_uop_is_jal; // @[core.scala:188:23, :190:18]
reg b2_uop_is_sfb; // @[core.scala:190:18]
assign brupdate_b2_uop_is_sfb = b2_uop_is_sfb; // @[core.scala:188:23, :190:18]
reg [15:0] b2_uop_br_mask; // @[core.scala:190:18]
assign brupdate_b2_uop_br_mask = b2_uop_br_mask; // @[core.scala:188:23, :190:18]
reg [3:0] b2_uop_br_tag; // @[core.scala:190:18]
assign brupdate_b2_uop_br_tag = b2_uop_br_tag; // @[core.scala:188:23, :190:18]
reg [4:0] b2_uop_ftq_idx; // @[core.scala:190:18]
assign brupdate_b2_uop_ftq_idx = b2_uop_ftq_idx; // @[core.scala:188:23, :190:18]
reg b2_uop_edge_inst; // @[core.scala:190:18]
assign brupdate_b2_uop_edge_inst = b2_uop_edge_inst; // @[core.scala:188:23, :190:18]
reg [5:0] b2_uop_pc_lob; // @[core.scala:190:18]
assign brupdate_b2_uop_pc_lob = b2_uop_pc_lob; // @[core.scala:188:23, :190:18]
reg b2_uop_taken; // @[core.scala:190:18]
assign brupdate_b2_uop_taken = b2_uop_taken; // @[core.scala:188:23, :190:18]
reg [19:0] b2_uop_imm_packed; // @[core.scala:190:18]
assign brupdate_b2_uop_imm_packed = b2_uop_imm_packed; // @[core.scala:188:23, :190:18]
reg [11:0] b2_uop_csr_addr; // @[core.scala:190:18]
assign brupdate_b2_uop_csr_addr = b2_uop_csr_addr; // @[core.scala:188:23, :190:18]
reg [6:0] b2_uop_rob_idx; // @[core.scala:190:18]
assign brupdate_b2_uop_rob_idx = b2_uop_rob_idx; // @[core.scala:188:23, :190:18]
reg [4:0] b2_uop_ldq_idx; // @[core.scala:190:18]
assign brupdate_b2_uop_ldq_idx = b2_uop_ldq_idx; // @[core.scala:188:23, :190:18]
reg [4:0] b2_uop_stq_idx; // @[core.scala:190:18]
assign brupdate_b2_uop_stq_idx = b2_uop_stq_idx; // @[core.scala:188:23, :190:18]
reg [1:0] b2_uop_rxq_idx; // @[core.scala:190:18]
assign brupdate_b2_uop_rxq_idx = b2_uop_rxq_idx; // @[core.scala:188:23, :190:18]
reg [6:0] b2_uop_pdst; // @[core.scala:190:18]
assign brupdate_b2_uop_pdst = b2_uop_pdst; // @[core.scala:188:23, :190:18]
reg [6:0] b2_uop_prs1; // @[core.scala:190:18]
assign brupdate_b2_uop_prs1 = b2_uop_prs1; // @[core.scala:188:23, :190:18]
reg [6:0] b2_uop_prs2; // @[core.scala:190:18]
assign brupdate_b2_uop_prs2 = b2_uop_prs2; // @[core.scala:188:23, :190:18]
reg [6:0] b2_uop_prs3; // @[core.scala:190:18]
assign brupdate_b2_uop_prs3 = b2_uop_prs3; // @[core.scala:188:23, :190:18]
reg [4:0] b2_uop_ppred; // @[core.scala:190:18]
assign brupdate_b2_uop_ppred = b2_uop_ppred; // @[core.scala:188:23, :190:18]
reg b2_uop_prs1_busy; // @[core.scala:190:18]
assign brupdate_b2_uop_prs1_busy = b2_uop_prs1_busy; // @[core.scala:188:23, :190:18]
reg b2_uop_prs2_busy; // @[core.scala:190:18]
assign brupdate_b2_uop_prs2_busy = b2_uop_prs2_busy; // @[core.scala:188:23, :190:18]
reg b2_uop_prs3_busy; // @[core.scala:190:18]
assign brupdate_b2_uop_prs3_busy = b2_uop_prs3_busy; // @[core.scala:188:23, :190:18]
reg b2_uop_ppred_busy; // @[core.scala:190:18]
assign brupdate_b2_uop_ppred_busy = b2_uop_ppred_busy; // @[core.scala:188:23, :190:18]
reg [6:0] b2_uop_stale_pdst; // @[core.scala:190:18]
assign brupdate_b2_uop_stale_pdst = b2_uop_stale_pdst; // @[core.scala:188:23, :190:18]
reg b2_uop_exception; // @[core.scala:190:18]
assign brupdate_b2_uop_exception = b2_uop_exception; // @[core.scala:188:23, :190:18]
reg [63:0] b2_uop_exc_cause; // @[core.scala:190:18]
assign brupdate_b2_uop_exc_cause = b2_uop_exc_cause; // @[core.scala:188:23, :190:18]
reg b2_uop_bypassable; // @[core.scala:190:18]
assign brupdate_b2_uop_bypassable = b2_uop_bypassable; // @[core.scala:188:23, :190:18]
reg [4:0] b2_uop_mem_cmd; // @[core.scala:190:18]
assign brupdate_b2_uop_mem_cmd = b2_uop_mem_cmd; // @[core.scala:188:23, :190:18]
reg [1:0] b2_uop_mem_size; // @[core.scala:190:18]
assign brupdate_b2_uop_mem_size = b2_uop_mem_size; // @[core.scala:188:23, :190:18]
reg b2_uop_mem_signed; // @[core.scala:190:18]
assign brupdate_b2_uop_mem_signed = b2_uop_mem_signed; // @[core.scala:188:23, :190:18]
reg b2_uop_is_fence; // @[core.scala:190:18]
assign brupdate_b2_uop_is_fence = b2_uop_is_fence; // @[core.scala:188:23, :190:18]
reg b2_uop_is_fencei; // @[core.scala:190:18]
assign brupdate_b2_uop_is_fencei = b2_uop_is_fencei; // @[core.scala:188:23, :190:18]
reg b2_uop_is_amo; // @[core.scala:190:18]
assign brupdate_b2_uop_is_amo = b2_uop_is_amo; // @[core.scala:188:23, :190:18]
reg b2_uop_uses_ldq; // @[core.scala:190:18]
assign brupdate_b2_uop_uses_ldq = b2_uop_uses_ldq; // @[core.scala:188:23, :190:18]
reg b2_uop_uses_stq; // @[core.scala:190:18]
assign brupdate_b2_uop_uses_stq = b2_uop_uses_stq; // @[core.scala:188:23, :190:18]
reg b2_uop_is_sys_pc2epc; // @[core.scala:190:18]
assign brupdate_b2_uop_is_sys_pc2epc = b2_uop_is_sys_pc2epc; // @[core.scala:188:23, :190:18]
reg b2_uop_is_unique; // @[core.scala:190:18]
assign brupdate_b2_uop_is_unique = b2_uop_is_unique; // @[core.scala:188:23, :190:18]
reg b2_uop_flush_on_commit; // @[core.scala:190:18]
assign brupdate_b2_uop_flush_on_commit = b2_uop_flush_on_commit; // @[core.scala:188:23, :190:18]
reg b2_uop_ldst_is_rs1; // @[core.scala:190:18]
assign brupdate_b2_uop_ldst_is_rs1 = b2_uop_ldst_is_rs1; // @[core.scala:188:23, :190:18]
reg [5:0] b2_uop_ldst; // @[core.scala:190:18]
assign brupdate_b2_uop_ldst = b2_uop_ldst; // @[core.scala:188:23, :190:18]
reg [5:0] b2_uop_lrs1; // @[core.scala:190:18]
assign brupdate_b2_uop_lrs1 = b2_uop_lrs1; // @[core.scala:188:23, :190:18]
reg [5:0] b2_uop_lrs2; // @[core.scala:190:18]
assign brupdate_b2_uop_lrs2 = b2_uop_lrs2; // @[core.scala:188:23, :190:18]
reg [5:0] b2_uop_lrs3; // @[core.scala:190:18]
assign brupdate_b2_uop_lrs3 = b2_uop_lrs3; // @[core.scala:188:23, :190:18]
reg b2_uop_ldst_val; // @[core.scala:190:18]
assign brupdate_b2_uop_ldst_val = b2_uop_ldst_val; // @[core.scala:188:23, :190:18]
reg [1:0] b2_uop_dst_rtype; // @[core.scala:190:18]
assign brupdate_b2_uop_dst_rtype = b2_uop_dst_rtype; // @[core.scala:188:23, :190:18]
reg [1:0] b2_uop_lrs1_rtype; // @[core.scala:190:18]
assign brupdate_b2_uop_lrs1_rtype = b2_uop_lrs1_rtype; // @[core.scala:188:23, :190:18]
reg [1:0] b2_uop_lrs2_rtype; // @[core.scala:190:18]
assign brupdate_b2_uop_lrs2_rtype = b2_uop_lrs2_rtype; // @[core.scala:188:23, :190:18]
reg b2_uop_frs3_en; // @[core.scala:190:18]
assign brupdate_b2_uop_frs3_en = b2_uop_frs3_en; // @[core.scala:188:23, :190:18]
reg b2_uop_fp_val; // @[core.scala:190:18]
assign brupdate_b2_uop_fp_val = b2_uop_fp_val; // @[core.scala:188:23, :190:18]
reg b2_uop_fp_single; // @[core.scala:190:18]
assign brupdate_b2_uop_fp_single = b2_uop_fp_single; // @[core.scala:188:23, :190:18]
reg b2_uop_xcpt_pf_if; // @[core.scala:190:18]
assign brupdate_b2_uop_xcpt_pf_if = b2_uop_xcpt_pf_if; // @[core.scala:188:23, :190:18]
reg b2_uop_xcpt_ae_if; // @[core.scala:190:18]
assign brupdate_b2_uop_xcpt_ae_if = b2_uop_xcpt_ae_if; // @[core.scala:188:23, :190:18]
reg b2_uop_xcpt_ma_if; // @[core.scala:190:18]
assign brupdate_b2_uop_xcpt_ma_if = b2_uop_xcpt_ma_if; // @[core.scala:188:23, :190:18]
reg b2_uop_bp_debug_if; // @[core.scala:190:18]
assign brupdate_b2_uop_bp_debug_if = b2_uop_bp_debug_if; // @[core.scala:188:23, :190:18]
reg b2_uop_bp_xcpt_if; // @[core.scala:190:18]
assign brupdate_b2_uop_bp_xcpt_if = b2_uop_bp_xcpt_if; // @[core.scala:188:23, :190:18]
reg [1:0] b2_uop_debug_fsrc; // @[core.scala:190:18]
assign brupdate_b2_uop_debug_fsrc = b2_uop_debug_fsrc; // @[core.scala:188:23, :190:18]
reg [1:0] b2_uop_debug_tsrc; // @[core.scala:190:18]
assign brupdate_b2_uop_debug_tsrc = b2_uop_debug_tsrc; // @[core.scala:188:23, :190:18]
reg b2_mispredict; // @[core.scala:190:18]
assign brupdate_b2_mispredict = b2_mispredict; // @[core.scala:188:23, :190:18]
reg b2_taken; // @[core.scala:190:18]
assign brupdate_b2_taken = b2_taken; // @[core.scala:188:23, :190:18]
reg [2:0] b2_cfi_type; // @[core.scala:190:18]
assign brupdate_b2_cfi_type = b2_cfi_type; // @[core.scala:188:23, :190:18]
reg [1:0] b2_pc_sel; // @[core.scala:190:18]
assign brupdate_b2_pc_sel = b2_pc_sel; // @[core.scala:188:23, :190:18]
reg [39:0] b2_jalr_target; // @[core.scala:190:18]
assign brupdate_b2_jalr_target = b2_jalr_target; // @[core.scala:188:23, :190:18]
reg [20:0] b2_target_offset; // @[core.scala:190:18]
assign brupdate_b2_target_offset = b2_target_offset; // @[core.scala:188:23, :190:18]
wire _brinfos_0_valid_T = ~_rob_io_flush_valid; // @[core.scala:143:32, :197:37]
wire _brinfos_0_valid_T_1 = _alu_exe_unit_io_brinfo_valid & _brinfos_0_valid_T; // @[execution-units.scala:119:32]
wire _brinfos_1_valid_T = ~_rob_io_flush_valid; // @[core.scala:143:32, :197:37]
wire _brinfos_1_valid_T_1 = _alu_exe_unit_1_io_brinfo_valid & _brinfos_1_valid_T; // @[execution-units.scala:119:32]
wire _brinfos_2_valid_T = ~_rob_io_flush_valid; // @[core.scala:143:32, :197:37]
wire _brinfos_2_valid_T_1 = _alu_exe_unit_2_io_brinfo_valid & _brinfos_2_valid_T; // @[execution-units.scala:119:32]
wire [15:0] _GEN = {12'h0, brinfos_0_uop_br_tag}; // @[core.scala:182:20, :199:47]
wire [15:0] _b1_resolve_mask_T = {15'h0, brinfos_0_valid} << _GEN; // @[core.scala:182:20, :199:47]
wire [15:0] _GEN_0 = {12'h0, brinfos_1_uop_br_tag}; // @[core.scala:182:20, :199:47]
wire [15:0] _b1_resolve_mask_T_1 = {15'h0, brinfos_1_valid} << _GEN_0; // @[core.scala:182:20, :199:47]
wire [15:0] _GEN_1 = {12'h0, brinfos_2_uop_br_tag}; // @[core.scala:182:20, :199:47]
wire [15:0] _b1_resolve_mask_T_2 = {15'h0, brinfos_2_valid} << _GEN_1; // @[core.scala:182:20, :199:47]
wire [15:0] _b1_resolve_mask_T_3 = _b1_resolve_mask_T | _b1_resolve_mask_T_1; // @[core.scala:199:{47,72}]
assign _b1_resolve_mask_T_4 = _b1_resolve_mask_T_3 | _b1_resolve_mask_T_2; // @[core.scala:199:{47,72}]
assign b1_resolve_mask = _b1_resolve_mask_T_4; // @[core.scala:189:19, :199:72]
wire _T_1 = brinfos_0_valid & brinfos_0_mispredict; // @[core.scala:182:20, :200:51]
wire _b1_mispredict_mask_T; // @[core.scala:200:51]
assign _b1_mispredict_mask_T = _T_1; // @[core.scala:200:51]
wire _use_this_mispredict_T_1; // @[core.scala:207:13]
assign _use_this_mispredict_T_1 = _T_1; // @[core.scala:200:51, :207:13]
wire [15:0] _b1_mispredict_mask_T_1 = {15'h0, _b1_mispredict_mask_T} << _GEN; // @[core.scala:199:47, :200:{51,68}]
wire _T_3 = brinfos_1_valid & brinfos_1_mispredict; // @[core.scala:182:20, :200:51]
wire _b1_mispredict_mask_T_2; // @[core.scala:200:51]
assign _b1_mispredict_mask_T_2 = _T_3; // @[core.scala:200:51]
wire _use_this_mispredict_T_9; // @[core.scala:207:13]
assign _use_this_mispredict_T_9 = _T_3; // @[core.scala:200:51, :207:13]
wire [15:0] _b1_mispredict_mask_T_3 = {15'h0, _b1_mispredict_mask_T_2} << _GEN_0; // @[core.scala:199:47, :200:{51,68}]
wire _T_6 = brinfos_2_valid & brinfos_2_mispredict; // @[core.scala:182:20, :200:51]
wire _b1_mispredict_mask_T_4; // @[core.scala:200:51]
assign _b1_mispredict_mask_T_4 = _T_6; // @[core.scala:200:51]
wire _use_this_mispredict_T_17; // @[core.scala:207:13]
assign _use_this_mispredict_T_17 = _T_6; // @[core.scala:200:51, :207:13]
wire [15:0] _b1_mispredict_mask_T_5 = {15'h0, _b1_mispredict_mask_T_4} << _GEN_1; // @[core.scala:199:47, :200:{51,68}]
wire [15:0] _b1_mispredict_mask_T_6 = _b1_mispredict_mask_T_1 | _b1_mispredict_mask_T_3; // @[core.scala:200:{68,93}]
assign _b1_mispredict_mask_T_7 = _b1_mispredict_mask_T_6 | _b1_mispredict_mask_T_5; // @[core.scala:200:{68,93}]
assign b1_mispredict_mask = _b1_mispredict_mask_T_7; // @[core.scala:189:19, :200:93]
wire _GEN_2 = brinfos_0_uop_rob_idx < _rob_io_rob_head_idx; // @[util.scala:363:64]
wire _use_this_mispredict_T_3; // @[util.scala:363:64]
assign _use_this_mispredict_T_3 = _GEN_2; // @[util.scala:363:64]
wire _use_this_mispredict_T_5; // @[util.scala:363:78]
assign _use_this_mispredict_T_5 = _GEN_2; // @[util.scala:363:{64,78}]
wire _use_this_mispredict_T_13; // @[util.scala:363:78]
assign _use_this_mispredict_T_13 = _GEN_2; // @[util.scala:363:{64,78}]
wire _use_this_mispredict_T_4 = _use_this_mispredict_T_3; // @[util.scala:363:{58,64}]
wire _use_this_mispredict_T_6 = _use_this_mispredict_T_4 ^ _use_this_mispredict_T_5; // @[util.scala:363:{58,72,78}]
wire _use_this_mispredict_T_7 = _use_this_mispredict_T_1 & _use_this_mispredict_T_6; // @[util.scala:363:72]
wire _use_this_mispredict_T_8 = ~_T_1; // @[core.scala:200:51, :206:31]
wire _use_this_mispredict_T_10 = brinfos_1_uop_rob_idx < brinfos_0_uop_rob_idx; // @[util.scala:363:52]
wire _use_this_mispredict_T_11 = brinfos_1_uop_rob_idx < _rob_io_rob_head_idx; // @[util.scala:363:64]
wire _use_this_mispredict_T_12 = _use_this_mispredict_T_10 ^ _use_this_mispredict_T_11; // @[util.scala:363:{52,58,64}]
wire _use_this_mispredict_T_14 = _use_this_mispredict_T_12 ^ _use_this_mispredict_T_13; // @[util.scala:363:{58,72,78}]
wire _use_this_mispredict_T_15 = _use_this_mispredict_T_9 & _use_this_mispredict_T_14; // @[util.scala:363:72]
wire use_this_mispredict_1 = _use_this_mispredict_T_8 | _use_this_mispredict_T_15; // @[core.scala:206:{31,47}, :207:29]
wire _T_4 = _T_1 | _T_3; // @[core.scala:200:51, :209:37]
wire [6:0] _T_5_uop_rob_idx = use_this_mispredict_1 ? brinfos_1_uop_rob_idx : brinfos_0_uop_rob_idx; // @[core.scala:182:20, :206:47, :210:28]
wire _use_this_mispredict_T_16 = ~_T_4; // @[core.scala:206:31, :209:37]
wire _use_this_mispredict_T_18 = brinfos_2_uop_rob_idx < _T_5_uop_rob_idx; // @[util.scala:363:52]
wire _use_this_mispredict_T_19 = brinfos_2_uop_rob_idx < _rob_io_rob_head_idx; // @[util.scala:363:64]
wire _use_this_mispredict_T_20 = _use_this_mispredict_T_18 ^ _use_this_mispredict_T_19; // @[util.scala:363:{52,58,64}]
wire _use_this_mispredict_T_21 = _T_5_uop_rob_idx < _rob_io_rob_head_idx; // @[util.scala:363:78]
wire _use_this_mispredict_T_22 = _use_this_mispredict_T_20 ^ _use_this_mispredict_T_21; // @[util.scala:363:{58,72,78}]
wire _use_this_mispredict_T_23 = _use_this_mispredict_T_17 & _use_this_mispredict_T_22; // @[util.scala:363:72]
wire use_this_mispredict_2 = _use_this_mispredict_T_16 | _use_this_mispredict_T_23; // @[core.scala:206:{31,47}, :207:29]
wire [6:0] b2_uop_out_uopc = use_this_mispredict_2 ? brinfos_2_uop_uopc : use_this_mispredict_1 ? brinfos_1_uop_uopc : brinfos_0_uop_uopc; // @[util.scala:96:23]
wire [31:0] b2_uop_out_inst = use_this_mispredict_2 ? brinfos_2_uop_inst : use_this_mispredict_1 ? brinfos_1_uop_inst : brinfos_0_uop_inst; // @[util.scala:96:23]
wire [31:0] b2_uop_out_debug_inst = use_this_mispredict_2 ? brinfos_2_uop_debug_inst : use_this_mispredict_1 ? brinfos_1_uop_debug_inst : brinfos_0_uop_debug_inst; // @[util.scala:96:23]
wire b2_uop_out_is_rvc = use_this_mispredict_2 ? brinfos_2_uop_is_rvc : use_this_mispredict_1 ? brinfos_1_uop_is_rvc : brinfos_0_uop_is_rvc; // @[util.scala:96:23]
wire [39:0] b2_uop_out_debug_pc = use_this_mispredict_2 ? brinfos_2_uop_debug_pc : use_this_mispredict_1 ? brinfos_1_uop_debug_pc : brinfos_0_uop_debug_pc; // @[util.scala:96:23]
wire [2:0] b2_uop_out_iq_type = use_this_mispredict_2 ? brinfos_2_uop_iq_type : use_this_mispredict_1 ? brinfos_1_uop_iq_type : brinfos_0_uop_iq_type; // @[util.scala:96:23]
wire [9:0] b2_uop_out_fu_code = use_this_mispredict_2 ? brinfos_2_uop_fu_code : use_this_mispredict_1 ? brinfos_1_uop_fu_code : brinfos_0_uop_fu_code; // @[util.scala:96:23]
wire [3:0] b2_uop_out_ctrl_br_type = use_this_mispredict_2 ? brinfos_2_uop_ctrl_br_type : use_this_mispredict_1 ? brinfos_1_uop_ctrl_br_type : brinfos_0_uop_ctrl_br_type; // @[util.scala:96:23]
wire [1:0] b2_uop_out_ctrl_op1_sel = use_this_mispredict_2 ? brinfos_2_uop_ctrl_op1_sel : use_this_mispredict_1 ? brinfos_1_uop_ctrl_op1_sel : brinfos_0_uop_ctrl_op1_sel; // @[util.scala:96:23]
wire [2:0] b2_uop_out_ctrl_op2_sel = use_this_mispredict_2 ? brinfos_2_uop_ctrl_op2_sel : use_this_mispredict_1 ? brinfos_1_uop_ctrl_op2_sel : brinfos_0_uop_ctrl_op2_sel; // @[util.scala:96:23]
wire [2:0] b2_uop_out_ctrl_imm_sel = use_this_mispredict_2 ? brinfos_2_uop_ctrl_imm_sel : use_this_mispredict_1 ? brinfos_1_uop_ctrl_imm_sel : brinfos_0_uop_ctrl_imm_sel; // @[util.scala:96:23]
wire [4:0] b2_uop_out_ctrl_op_fcn = use_this_mispredict_2 ? brinfos_2_uop_ctrl_op_fcn : use_this_mispredict_1 ? brinfos_1_uop_ctrl_op_fcn : brinfos_0_uop_ctrl_op_fcn; // @[util.scala:96:23]
wire b2_uop_out_ctrl_fcn_dw = use_this_mispredict_2 ? brinfos_2_uop_ctrl_fcn_dw : use_this_mispredict_1 ? brinfos_1_uop_ctrl_fcn_dw : brinfos_0_uop_ctrl_fcn_dw; // @[util.scala:96:23]
wire [2:0] b2_uop_out_ctrl_csr_cmd = use_this_mispredict_2 ? brinfos_2_uop_ctrl_csr_cmd : use_this_mispredict_1 ? brinfos_1_uop_ctrl_csr_cmd : brinfos_0_uop_ctrl_csr_cmd; // @[util.scala:96:23]
wire b2_uop_out_ctrl_is_load = use_this_mispredict_2 ? brinfos_2_uop_ctrl_is_load : use_this_mispredict_1 ? brinfos_1_uop_ctrl_is_load : brinfos_0_uop_ctrl_is_load; // @[util.scala:96:23]
wire b2_uop_out_ctrl_is_sta = use_this_mispredict_2 ? brinfos_2_uop_ctrl_is_sta : use_this_mispredict_1 ? brinfos_1_uop_ctrl_is_sta : brinfos_0_uop_ctrl_is_sta; // @[util.scala:96:23]
wire b2_uop_out_ctrl_is_std = use_this_mispredict_2 ? brinfos_2_uop_ctrl_is_std : use_this_mispredict_1 ? brinfos_1_uop_ctrl_is_std : brinfos_0_uop_ctrl_is_std; // @[util.scala:96:23]
wire [1:0] b2_uop_out_iw_state = use_this_mispredict_2 ? brinfos_2_uop_iw_state : use_this_mispredict_1 ? brinfos_1_uop_iw_state : brinfos_0_uop_iw_state; // @[util.scala:96:23]
wire b2_uop_out_iw_p1_poisoned = use_this_mispredict_2 ? brinfos_2_uop_iw_p1_poisoned : use_this_mispredict_1 ? brinfos_1_uop_iw_p1_poisoned : brinfos_0_uop_iw_p1_poisoned; // @[util.scala:96:23]
wire b2_uop_out_iw_p2_poisoned = use_this_mispredict_2 ? brinfos_2_uop_iw_p2_poisoned : use_this_mispredict_1 ? brinfos_1_uop_iw_p2_poisoned : brinfos_0_uop_iw_p2_poisoned; // @[util.scala:96:23]
wire b2_uop_out_is_br = use_this_mispredict_2 ? brinfos_2_uop_is_br : use_this_mispredict_1 ? brinfos_1_uop_is_br : brinfos_0_uop_is_br; // @[util.scala:96:23]
wire b2_uop_out_is_jalr = use_this_mispredict_2 ? brinfos_2_uop_is_jalr : use_this_mispredict_1 ? brinfos_1_uop_is_jalr : brinfos_0_uop_is_jalr; // @[util.scala:96:23]
wire b2_uop_out_is_jal = use_this_mispredict_2 ? brinfos_2_uop_is_jal : use_this_mispredict_1 ? brinfos_1_uop_is_jal : brinfos_0_uop_is_jal; // @[util.scala:96:23]
wire b2_uop_out_is_sfb = use_this_mispredict_2 ? brinfos_2_uop_is_sfb : use_this_mispredict_1 ? brinfos_1_uop_is_sfb : brinfos_0_uop_is_sfb; // @[util.scala:96:23]
wire [3:0] b2_uop_out_br_tag = use_this_mispredict_2 ? brinfos_2_uop_br_tag : use_this_mispredict_1 ? brinfos_1_uop_br_tag : brinfos_0_uop_br_tag; // @[util.scala:96:23]
wire [4:0] _T_8_uop_ftq_idx = use_this_mispredict_2 ? brinfos_2_uop_ftq_idx : use_this_mispredict_1 ? brinfos_1_uop_ftq_idx : brinfos_0_uop_ftq_idx; // @[core.scala:182:20, :206:47, :210:28]
assign io_ifu_get_pc_1_ftq_idx_0 = _T_8_uop_ftq_idx; // @[core.scala:51:7, :210:28]
wire [4:0] b2_uop_out_ftq_idx; // @[util.scala:96:23]
assign b2_uop_out_ftq_idx = _T_8_uop_ftq_idx; // @[util.scala:96:23]
wire b2_uop_out_edge_inst = use_this_mispredict_2 ? brinfos_2_uop_edge_inst : use_this_mispredict_1 ? brinfos_1_uop_edge_inst : brinfos_0_uop_edge_inst; // @[util.scala:96:23]
wire [5:0] b2_uop_out_pc_lob = use_this_mispredict_2 ? brinfos_2_uop_pc_lob : use_this_mispredict_1 ? brinfos_1_uop_pc_lob : brinfos_0_uop_pc_lob; // @[util.scala:96:23]
wire b2_uop_out_taken = use_this_mispredict_2 ? brinfos_2_uop_taken : use_this_mispredict_1 ? brinfos_1_uop_taken : brinfos_0_uop_taken; // @[util.scala:96:23]
wire [19:0] b2_uop_out_imm_packed = use_this_mispredict_2 ? brinfos_2_uop_imm_packed : use_this_mispredict_1 ? brinfos_1_uop_imm_packed : brinfos_0_uop_imm_packed; // @[util.scala:96:23]
wire [11:0] b2_uop_out_csr_addr = use_this_mispredict_2 ? brinfos_2_uop_csr_addr : use_this_mispredict_1 ? brinfos_1_uop_csr_addr : brinfos_0_uop_csr_addr; // @[util.scala:96:23]
wire [6:0] b2_uop_out_rob_idx = use_this_mispredict_2 ? brinfos_2_uop_rob_idx : _T_5_uop_rob_idx; // @[util.scala:96:23]
wire [4:0] b2_uop_out_ldq_idx = use_this_mispredict_2 ? brinfos_2_uop_ldq_idx : use_this_mispredict_1 ? brinfos_1_uop_ldq_idx : brinfos_0_uop_ldq_idx; // @[util.scala:96:23]
wire [4:0] b2_uop_out_stq_idx = use_this_mispredict_2 ? brinfos_2_uop_stq_idx : use_this_mispredict_1 ? brinfos_1_uop_stq_idx : brinfos_0_uop_stq_idx; // @[util.scala:96:23]
wire [1:0] b2_uop_out_rxq_idx = use_this_mispredict_2 ? brinfos_2_uop_rxq_idx : use_this_mispredict_1 ? brinfos_1_uop_rxq_idx : brinfos_0_uop_rxq_idx; // @[util.scala:96:23]
wire [6:0] b2_uop_out_pdst = use_this_mispredict_2 ? brinfos_2_uop_pdst : use_this_mispredict_1 ? brinfos_1_uop_pdst : brinfos_0_uop_pdst; // @[util.scala:96:23]
wire [6:0] b2_uop_out_prs1 = use_this_mispredict_2 ? brinfos_2_uop_prs1 : use_this_mispredict_1 ? brinfos_1_uop_prs1 : brinfos_0_uop_prs1; // @[util.scala:96:23]
wire [6:0] b2_uop_out_prs2 = use_this_mispredict_2 ? brinfos_2_uop_prs2 : use_this_mispredict_1 ? brinfos_1_uop_prs2 : brinfos_0_uop_prs2; // @[util.scala:96:23]
wire [6:0] b2_uop_out_prs3 = use_this_mispredict_2 ? brinfos_2_uop_prs3 : use_this_mispredict_1 ? brinfos_1_uop_prs3 : brinfos_0_uop_prs3; // @[util.scala:96:23]
wire [4:0] b2_uop_out_ppred = use_this_mispredict_2 ? brinfos_2_uop_ppred : use_this_mispredict_1 ? brinfos_1_uop_ppred : brinfos_0_uop_ppred; // @[util.scala:96:23]
wire b2_uop_out_prs1_busy = use_this_mispredict_2 ? brinfos_2_uop_prs1_busy : use_this_mispredict_1 ? brinfos_1_uop_prs1_busy : brinfos_0_uop_prs1_busy; // @[util.scala:96:23]
wire b2_uop_out_prs2_busy = use_this_mispredict_2 ? brinfos_2_uop_prs2_busy : use_this_mispredict_1 ? brinfos_1_uop_prs2_busy : brinfos_0_uop_prs2_busy; // @[util.scala:96:23]
wire b2_uop_out_prs3_busy = use_this_mispredict_2 ? brinfos_2_uop_prs3_busy : use_this_mispredict_1 ? brinfos_1_uop_prs3_busy : brinfos_0_uop_prs3_busy; // @[util.scala:96:23]
wire b2_uop_out_ppred_busy = use_this_mispredict_2 ? brinfos_2_uop_ppred_busy : use_this_mispredict_1 ? brinfos_1_uop_ppred_busy : brinfos_0_uop_ppred_busy; // @[util.scala:96:23]
wire [6:0] b2_uop_out_stale_pdst = use_this_mispredict_2 ? brinfos_2_uop_stale_pdst : use_this_mispredict_1 ? brinfos_1_uop_stale_pdst : brinfos_0_uop_stale_pdst; // @[util.scala:96:23]
wire b2_uop_out_exception = use_this_mispredict_2 ? brinfos_2_uop_exception : use_this_mispredict_1 ? brinfos_1_uop_exception : brinfos_0_uop_exception; // @[util.scala:96:23]
wire [63:0] b2_uop_out_exc_cause = use_this_mispredict_2 ? brinfos_2_uop_exc_cause : use_this_mispredict_1 ? brinfos_1_uop_exc_cause : brinfos_0_uop_exc_cause; // @[util.scala:96:23]
wire b2_uop_out_bypassable = use_this_mispredict_2 ? brinfos_2_uop_bypassable : use_this_mispredict_1 ? brinfos_1_uop_bypassable : brinfos_0_uop_bypassable; // @[util.scala:96:23]
wire [4:0] b2_uop_out_mem_cmd = use_this_mispredict_2 ? brinfos_2_uop_mem_cmd : use_this_mispredict_1 ? brinfos_1_uop_mem_cmd : brinfos_0_uop_mem_cmd; // @[util.scala:96:23]
wire [1:0] b2_uop_out_mem_size = use_this_mispredict_2 ? brinfos_2_uop_mem_size : use_this_mispredict_1 ? brinfos_1_uop_mem_size : brinfos_0_uop_mem_size; // @[util.scala:96:23]
wire b2_uop_out_mem_signed = use_this_mispredict_2 ? brinfos_2_uop_mem_signed : use_this_mispredict_1 ? brinfos_1_uop_mem_signed : brinfos_0_uop_mem_signed; // @[util.scala:96:23]
wire b2_uop_out_is_fence = use_this_mispredict_2 ? brinfos_2_uop_is_fence : use_this_mispredict_1 ? brinfos_1_uop_is_fence : brinfos_0_uop_is_fence; // @[util.scala:96:23]
wire b2_uop_out_is_fencei = use_this_mispredict_2 ? brinfos_2_uop_is_fencei : use_this_mispredict_1 ? brinfos_1_uop_is_fencei : brinfos_0_uop_is_fencei; // @[util.scala:96:23]
wire b2_uop_out_is_amo = use_this_mispredict_2 ? brinfos_2_uop_is_amo : use_this_mispredict_1 ? brinfos_1_uop_is_amo : brinfos_0_uop_is_amo; // @[util.scala:96:23]
wire b2_uop_out_uses_ldq = use_this_mispredict_2 ? brinfos_2_uop_uses_ldq : use_this_mispredict_1 ? brinfos_1_uop_uses_ldq : brinfos_0_uop_uses_ldq; // @[util.scala:96:23]
wire b2_uop_out_uses_stq = use_this_mispredict_2 ? brinfos_2_uop_uses_stq : use_this_mispredict_1 ? brinfos_1_uop_uses_stq : brinfos_0_uop_uses_stq; // @[util.scala:96:23]
wire b2_uop_out_is_sys_pc2epc = use_this_mispredict_2 ? brinfos_2_uop_is_sys_pc2epc : use_this_mispredict_1 ? brinfos_1_uop_is_sys_pc2epc : brinfos_0_uop_is_sys_pc2epc; // @[util.scala:96:23]
wire b2_uop_out_is_unique = use_this_mispredict_2 ? brinfos_2_uop_is_unique : use_this_mispredict_1 ? brinfos_1_uop_is_unique : brinfos_0_uop_is_unique; // @[util.scala:96:23]
wire b2_uop_out_flush_on_commit = use_this_mispredict_2 ? brinfos_2_uop_flush_on_commit : use_this_mispredict_1 ? brinfos_1_uop_flush_on_commit : brinfos_0_uop_flush_on_commit; // @[util.scala:96:23]
wire b2_uop_out_ldst_is_rs1 = use_this_mispredict_2 ? brinfos_2_uop_ldst_is_rs1 : use_this_mispredict_1 ? brinfos_1_uop_ldst_is_rs1 : brinfos_0_uop_ldst_is_rs1; // @[util.scala:96:23]
wire [5:0] b2_uop_out_ldst = use_this_mispredict_2 ? brinfos_2_uop_ldst : use_this_mispredict_1 ? brinfos_1_uop_ldst : brinfos_0_uop_ldst; // @[util.scala:96:23]
wire [5:0] b2_uop_out_lrs1 = use_this_mispredict_2 ? brinfos_2_uop_lrs1 : use_this_mispredict_1 ? brinfos_1_uop_lrs1 : brinfos_0_uop_lrs1; // @[util.scala:96:23]
wire [5:0] b2_uop_out_lrs2 = use_this_mispredict_2 ? brinfos_2_uop_lrs2 : use_this_mispredict_1 ? brinfos_1_uop_lrs2 : brinfos_0_uop_lrs2; // @[util.scala:96:23]
wire [5:0] b2_uop_out_lrs3 = use_this_mispredict_2 ? brinfos_2_uop_lrs3 : use_this_mispredict_1 ? brinfos_1_uop_lrs3 : brinfos_0_uop_lrs3; // @[util.scala:96:23]
wire b2_uop_out_ldst_val = use_this_mispredict_2 ? brinfos_2_uop_ldst_val : use_this_mispredict_1 ? brinfos_1_uop_ldst_val : brinfos_0_uop_ldst_val; // @[util.scala:96:23]
wire [1:0] b2_uop_out_dst_rtype = use_this_mispredict_2 ? brinfos_2_uop_dst_rtype : use_this_mispredict_1 ? brinfos_1_uop_dst_rtype : brinfos_0_uop_dst_rtype; // @[util.scala:96:23]
wire [1:0] b2_uop_out_lrs1_rtype = use_this_mispredict_2 ? brinfos_2_uop_lrs1_rtype : use_this_mispredict_1 ? brinfos_1_uop_lrs1_rtype : brinfos_0_uop_lrs1_rtype; // @[util.scala:96:23]
wire [1:0] b2_uop_out_lrs2_rtype = use_this_mispredict_2 ? brinfos_2_uop_lrs2_rtype : use_this_mispredict_1 ? brinfos_1_uop_lrs2_rtype : brinfos_0_uop_lrs2_rtype; // @[util.scala:96:23]
wire b2_uop_out_frs3_en = use_this_mispredict_2 ? brinfos_2_uop_frs3_en : use_this_mispredict_1 ? brinfos_1_uop_frs3_en : brinfos_0_uop_frs3_en; // @[util.scala:96:23]
wire b2_uop_out_fp_val = use_this_mispredict_2 ? brinfos_2_uop_fp_val : use_this_mispredict_1 ? brinfos_1_uop_fp_val : brinfos_0_uop_fp_val; // @[util.scala:96:23]
wire b2_uop_out_fp_single = use_this_mispredict_2 ? brinfos_2_uop_fp_single : use_this_mispredict_1 ? brinfos_1_uop_fp_single : brinfos_0_uop_fp_single; // @[util.scala:96:23]
wire b2_uop_out_xcpt_pf_if = use_this_mispredict_2 ? brinfos_2_uop_xcpt_pf_if : use_this_mispredict_1 ? brinfos_1_uop_xcpt_pf_if : brinfos_0_uop_xcpt_pf_if; // @[util.scala:96:23]
wire b2_uop_out_xcpt_ae_if = use_this_mispredict_2 ? brinfos_2_uop_xcpt_ae_if : use_this_mispredict_1 ? brinfos_1_uop_xcpt_ae_if : brinfos_0_uop_xcpt_ae_if; // @[util.scala:96:23]
wire b2_uop_out_xcpt_ma_if = use_this_mispredict_2 ? brinfos_2_uop_xcpt_ma_if : use_this_mispredict_1 ? brinfos_1_uop_xcpt_ma_if : brinfos_0_uop_xcpt_ma_if; // @[util.scala:96:23]
wire b2_uop_out_bp_debug_if = use_this_mispredict_2 ? brinfos_2_uop_bp_debug_if : use_this_mispredict_1 ? brinfos_1_uop_bp_debug_if : brinfos_0_uop_bp_debug_if; // @[util.scala:96:23]
wire b2_uop_out_bp_xcpt_if = use_this_mispredict_2 ? brinfos_2_uop_bp_xcpt_if : use_this_mispredict_1 ? brinfos_1_uop_bp_xcpt_if : brinfos_0_uop_bp_xcpt_if; // @[util.scala:96:23]
wire [1:0] b2_uop_out_debug_fsrc = use_this_mispredict_2 ? brinfos_2_uop_debug_fsrc : use_this_mispredict_1 ? brinfos_1_uop_debug_fsrc : brinfos_0_uop_debug_fsrc; // @[util.scala:96:23]
wire [1:0] b2_uop_out_debug_tsrc = use_this_mispredict_2 ? brinfos_2_uop_debug_tsrc : use_this_mispredict_1 ? brinfos_1_uop_debug_tsrc : brinfos_0_uop_debug_tsrc; // @[util.scala:96:23]
wire [15:0] _b2_uop_out_br_mask_T_1; // @[util.scala:85:25]
wire [15:0] b2_uop_out_br_mask; // @[util.scala:96:23]
wire [15:0] _b2_uop_out_br_mask_T = ~brupdate_b1_resolve_mask; // @[util.scala:85:27]
assign _b2_uop_out_br_mask_T_1 = (use_this_mispredict_2 ? brinfos_2_uop_br_mask : use_this_mispredict_1 ? brinfos_1_uop_br_mask : brinfos_0_uop_br_mask) & _b2_uop_out_br_mask_T; // @[util.scala:85:{25,27}]
assign b2_uop_out_br_mask = _b2_uop_out_br_mask_T_1; // @[util.scala:85:25, :96:23]
reg [39:0] b2_jalr_target_REG; // @[core.scala:218:28]
wire custom_csrs_csrs_0_ren; // @[core.scala:276:25]
wire custom_csrs_csrs_0_wen; // @[core.scala:276:25]
wire [63:0] custom_csrs_csrs_0_wdata; // @[core.scala:276:25]
wire [63:0] custom_csrs_csrs_0_value; // @[core.scala:276:25]
wire custom_csrs_csrs_1_ren; // @[core.scala:276:25]
wire custom_csrs_csrs_1_wen; // @[core.scala:276:25]
wire [63:0] custom_csrs_csrs_1_wdata; // @[core.scala:276:25]
wire [63:0] custom_csrs_csrs_1_value; // @[core.scala:276:25]
reg [63:0] debug_tsc_reg; // @[core.scala:288:30]
assign io_lsu_tsc_reg_0 = debug_tsc_reg; // @[core.scala:51:7, :288:30]
reg [63:0] debug_irt_reg; // @[core.scala:289:30]
reg [63:0] debug_brs_0; // @[core.scala:290:26]
reg [63:0] debug_brs_1; // @[core.scala:290:26]
reg [63:0] debug_brs_2; // @[core.scala:290:26]
reg [63:0] debug_brs_3; // @[core.scala:290:26]
reg [63:0] debug_jals_0; // @[core.scala:291:26]
reg [63:0] debug_jals_1; // @[core.scala:291:26]
reg [63:0] debug_jals_2; // @[core.scala:291:26]
reg [63:0] debug_jals_3; // @[core.scala:291:26]
reg [63:0] debug_jalrs_0; // @[core.scala:292:26]
reg [63:0] debug_jalrs_1; // @[core.scala:292:26]
reg [63:0] debug_jalrs_2; // @[core.scala:292:26]
reg [63:0] debug_jalrs_3; // @[core.scala:292:26]
wire _GEN_3 = _rob_io_commit_uops_0_debug_fsrc == 2'h0; // @[core.scala:143:32, :297:41]
wire _debug_brs_0_T; // @[core.scala:297:41]
assign _debug_brs_0_T = _GEN_3; // @[core.scala:297:41]
wire _debug_jals_0_T; // @[core.scala:302:41]
assign _debug_jals_0_T = _GEN_3; // @[core.scala:297:41, :302:41]
wire _debug_jalrs_0_T; // @[core.scala:307:41]
assign _debug_jalrs_0_T = _GEN_3; // @[core.scala:297:41, :307:41]
wire _debug_brs_0_T_1 = _rob_io_commit_arch_valids_0 & _debug_brs_0_T; // @[core.scala:143:32, :296:36, :297:41]
wire _debug_brs_0_T_2 = _debug_brs_0_T_1 & _rob_io_commit_uops_0_is_br; // @[core.scala:143:32, :296:36, :297:50]
wire _debug_brs_0_WIRE_0 = _debug_brs_0_T_2; // @[core.scala:295:52, :297:50]
wire _GEN_4 = _rob_io_commit_uops_1_debug_fsrc == 2'h0; // @[core.scala:143:32, :297:41]
wire _debug_brs_0_T_3; // @[core.scala:297:41]
assign _debug_brs_0_T_3 = _GEN_4; // @[core.scala:297:41]
wire _debug_jals_0_T_3; // @[core.scala:302:41]
assign _debug_jals_0_T_3 = _GEN_4; // @[core.scala:297:41, :302:41]
wire _debug_jalrs_0_T_3; // @[core.scala:307:41]
assign _debug_jalrs_0_T_3 = _GEN_4; // @[core.scala:297:41, :307:41]
wire _debug_brs_0_T_4 = _rob_io_commit_arch_valids_1 & _debug_brs_0_T_3; // @[core.scala:143:32, :296:36, :297:41]
wire _debug_brs_0_T_5 = _debug_brs_0_T_4 & _rob_io_commit_uops_1_is_br; // @[core.scala:143:32, :296:36, :297:50]
wire _debug_brs_0_WIRE_1 = _debug_brs_0_T_5; // @[core.scala:295:52, :297:50]
wire _GEN_5 = _rob_io_commit_uops_2_debug_fsrc == 2'h0; // @[core.scala:143:32, :297:41]
wire _debug_brs_0_T_6; // @[core.scala:297:41]
assign _debug_brs_0_T_6 = _GEN_5; // @[core.scala:297:41]
wire _debug_jals_0_T_6; // @[core.scala:302:41]
assign _debug_jals_0_T_6 = _GEN_5; // @[core.scala:297:41, :302:41]
wire _debug_jalrs_0_T_6; // @[core.scala:307:41]
assign _debug_jalrs_0_T_6 = _GEN_5; // @[core.scala:297:41, :307:41]
wire _debug_brs_0_T_7 = _rob_io_commit_arch_valids_2 & _debug_brs_0_T_6; // @[core.scala:143:32, :296:36, :297:41]
wire _debug_brs_0_T_8 = _debug_brs_0_T_7 & _rob_io_commit_uops_2_is_br; // @[core.scala:143:32, :296:36, :297:50]
wire _debug_brs_0_WIRE_2 = _debug_brs_0_T_8; // @[core.scala:295:52, :297:50]
wire [1:0] _debug_brs_0_T_9 = {1'h0, _debug_brs_0_WIRE_1} + {1'h0, _debug_brs_0_WIRE_2}; // @[core.scala:295:{44,52}]
wire [1:0] _debug_brs_0_T_10 = _debug_brs_0_T_9; // @[core.scala:295:44]
wire [2:0] _debug_brs_0_T_11 = {2'h0, _debug_brs_0_WIRE_0} + {1'h0, _debug_brs_0_T_10}; // @[core.scala:295:{44,52}]
wire [1:0] _debug_brs_0_T_12 = _debug_brs_0_T_11[1:0]; // @[core.scala:295:44]
wire [64:0] _debug_brs_0_T_13 = {1'h0, debug_brs_0} + {63'h0, _debug_brs_0_T_12}; // @[core.scala:290:26, :295:{34,44}]
wire [63:0] _debug_brs_0_T_14 = _debug_brs_0_T_13[63:0]; // @[core.scala:295:34]
wire _debug_jals_0_T_1 = _rob_io_commit_arch_valids_0 & _debug_jals_0_T; // @[core.scala:143:32, :301:36, :302:41]
wire _debug_jals_0_T_2 = _debug_jals_0_T_1 & _rob_io_commit_uops_0_is_jal; // @[core.scala:143:32, :301:36, :302:50]
wire _debug_jals_0_WIRE_0 = _debug_jals_0_T_2; // @[core.scala:300:54, :302:50]
wire _debug_jals_0_T_4 = _rob_io_commit_arch_valids_1 & _debug_jals_0_T_3; // @[core.scala:143:32, :301:36, :302:41]
wire _debug_jals_0_T_5 = _debug_jals_0_T_4 & _rob_io_commit_uops_1_is_jal; // @[core.scala:143:32, :301:36, :302:50]
wire _debug_jals_0_WIRE_1 = _debug_jals_0_T_5; // @[core.scala:300:54, :302:50]
wire _debug_jals_0_T_7 = _rob_io_commit_arch_valids_2 & _debug_jals_0_T_6; // @[core.scala:143:32, :301:36, :302:41]
wire _debug_jals_0_T_8 = _debug_jals_0_T_7 & _rob_io_commit_uops_2_is_jal; // @[core.scala:143:32, :301:36, :302:50]
wire _debug_jals_0_WIRE_2 = _debug_jals_0_T_8; // @[core.scala:300:54, :302:50]
wire [1:0] _debug_jals_0_T_9 = {1'h0, _debug_jals_0_WIRE_1} + {1'h0, _debug_jals_0_WIRE_2}; // @[core.scala:300:{46,54}]
wire [1:0] _debug_jals_0_T_10 = _debug_jals_0_T_9; // @[core.scala:300:46]
wire [2:0] _debug_jals_0_T_11 = {2'h0, _debug_jals_0_WIRE_0} + {1'h0, _debug_jals_0_T_10}; // @[core.scala:300:{46,54}]
wire [1:0] _debug_jals_0_T_12 = _debug_jals_0_T_11[1:0]; // @[core.scala:300:46]
wire [64:0] _debug_jals_0_T_13 = {1'h0, debug_jals_0} + {63'h0, _debug_jals_0_T_12}; // @[core.scala:291:26, :295:34, :300:{36,46}]
wire [63:0] _debug_jals_0_T_14 = _debug_jals_0_T_13[63:0]; // @[core.scala:300:36]
wire _debug_jalrs_0_T_1 = _rob_io_commit_arch_valids_0 & _debug_jalrs_0_T; // @[core.scala:143:32, :306:36, :307:41]
wire _debug_jalrs_0_T_2 = _debug_jalrs_0_T_1 & _rob_io_commit_uops_0_is_jalr; // @[core.scala:143:32, :306:36, :307:50]
wire _debug_jalrs_0_WIRE_0 = _debug_jalrs_0_T_2; // @[core.scala:305:56, :307:50]
wire _debug_jalrs_0_T_4 = _rob_io_commit_arch_valids_1 & _debug_jalrs_0_T_3; // @[core.scala:143:32, :306:36, :307:41]
wire _debug_jalrs_0_T_5 = _debug_jalrs_0_T_4 & _rob_io_commit_uops_1_is_jalr; // @[core.scala:143:32, :306:36, :307:50]
wire _debug_jalrs_0_WIRE_1 = _debug_jalrs_0_T_5; // @[core.scala:305:56, :307:50]
wire _debug_jalrs_0_T_7 = _rob_io_commit_arch_valids_2 & _debug_jalrs_0_T_6; // @[core.scala:143:32, :306:36, :307:41]
wire _debug_jalrs_0_T_8 = _debug_jalrs_0_T_7 & _rob_io_commit_uops_2_is_jalr; // @[core.scala:143:32, :306:36, :307:50]
wire _debug_jalrs_0_WIRE_2 = _debug_jalrs_0_T_8; // @[core.scala:305:56, :307:50]
wire [1:0] _debug_jalrs_0_T_9 = {1'h0, _debug_jalrs_0_WIRE_1} + {1'h0, _debug_jalrs_0_WIRE_2}; // @[core.scala:305:{48,56}]
wire [1:0] _debug_jalrs_0_T_10 = _debug_jalrs_0_T_9; // @[core.scala:305:48]
wire [2:0] _debug_jalrs_0_T_11 = {2'h0, _debug_jalrs_0_WIRE_0} + {1'h0, _debug_jalrs_0_T_10}; // @[core.scala:305:{48,56}]
wire [1:0] _debug_jalrs_0_T_12 = _debug_jalrs_0_T_11[1:0]; // @[core.scala:305:48]
wire [64:0] _debug_jalrs_0_T_13 = {1'h0, debug_jalrs_0} + {63'h0, _debug_jalrs_0_T_12}; // @[core.scala:292:26, :295:34, :305:{38,48}]
wire [63:0] _debug_jalrs_0_T_14 = _debug_jalrs_0_T_13[63:0]; // @[core.scala:305:38]
wire _GEN_6 = _rob_io_commit_uops_0_debug_fsrc == 2'h1; // @[core.scala:143:32, :297:41]
wire _debug_brs_1_T; // @[core.scala:297:41]
assign _debug_brs_1_T = _GEN_6; // @[core.scala:297:41]
wire _debug_jals_1_T; // @[core.scala:302:41]
assign _debug_jals_1_T = _GEN_6; // @[core.scala:297:41, :302:41]
wire _debug_jalrs_1_T; // @[core.scala:307:41]
assign _debug_jalrs_1_T = _GEN_6; // @[core.scala:297:41, :307:41]
wire _debug_brs_1_T_1 = _rob_io_commit_arch_valids_0 & _debug_brs_1_T; // @[core.scala:143:32, :296:36, :297:41]
wire _debug_brs_1_T_2 = _debug_brs_1_T_1 & _rob_io_commit_uops_0_is_br; // @[core.scala:143:32, :296:36, :297:50]
wire _debug_brs_1_WIRE_0 = _debug_brs_1_T_2; // @[core.scala:295:52, :297:50]
wire _GEN_7 = _rob_io_commit_uops_1_debug_fsrc == 2'h1; // @[core.scala:143:32, :297:41]
wire _debug_brs_1_T_3; // @[core.scala:297:41]
assign _debug_brs_1_T_3 = _GEN_7; // @[core.scala:297:41]
wire _debug_jals_1_T_3; // @[core.scala:302:41]
assign _debug_jals_1_T_3 = _GEN_7; // @[core.scala:297:41, :302:41]
wire _debug_jalrs_1_T_3; // @[core.scala:307:41]
assign _debug_jalrs_1_T_3 = _GEN_7; // @[core.scala:297:41, :307:41]
wire _debug_brs_1_T_4 = _rob_io_commit_arch_valids_1 & _debug_brs_1_T_3; // @[core.scala:143:32, :296:36, :297:41]
wire _debug_brs_1_T_5 = _debug_brs_1_T_4 & _rob_io_commit_uops_1_is_br; // @[core.scala:143:32, :296:36, :297:50]
wire _debug_brs_1_WIRE_1 = _debug_brs_1_T_5; // @[core.scala:295:52, :297:50]
wire _GEN_8 = _rob_io_commit_uops_2_debug_fsrc == 2'h1; // @[core.scala:143:32, :297:41]
wire _debug_brs_1_T_6; // @[core.scala:297:41]
assign _debug_brs_1_T_6 = _GEN_8; // @[core.scala:297:41]
wire _debug_jals_1_T_6; // @[core.scala:302:41]
assign _debug_jals_1_T_6 = _GEN_8; // @[core.scala:297:41, :302:41]
wire _debug_jalrs_1_T_6; // @[core.scala:307:41]
assign _debug_jalrs_1_T_6 = _GEN_8; // @[core.scala:297:41, :307:41]
wire _debug_brs_1_T_7 = _rob_io_commit_arch_valids_2 & _debug_brs_1_T_6; // @[core.scala:143:32, :296:36, :297:41]
wire _debug_brs_1_T_8 = _debug_brs_1_T_7 & _rob_io_commit_uops_2_is_br; // @[core.scala:143:32, :296:36, :297:50]
wire _debug_brs_1_WIRE_2 = _debug_brs_1_T_8; // @[core.scala:295:52, :297:50]
wire [1:0] _debug_brs_1_T_9 = {1'h0, _debug_brs_1_WIRE_1} + {1'h0, _debug_brs_1_WIRE_2}; // @[core.scala:295:{44,52}]
wire [1:0] _debug_brs_1_T_10 = _debug_brs_1_T_9; // @[core.scala:295:44]
wire [2:0] _debug_brs_1_T_11 = {2'h0, _debug_brs_1_WIRE_0} + {1'h0, _debug_brs_1_T_10}; // @[core.scala:295:{44,52}]
wire [1:0] _debug_brs_1_T_12 = _debug_brs_1_T_11[1:0]; // @[core.scala:295:44]
wire [64:0] _debug_brs_1_T_13 = {1'h0, debug_brs_1} + {63'h0, _debug_brs_1_T_12}; // @[core.scala:290:26, :295:{34,44}]
wire [63:0] _debug_brs_1_T_14 = _debug_brs_1_T_13[63:0]; // @[core.scala:295:34]
wire _debug_jals_1_T_1 = _rob_io_commit_arch_valids_0 & _debug_jals_1_T; // @[core.scala:143:32, :301:36, :302:41]
wire _debug_jals_1_T_2 = _debug_jals_1_T_1 & _rob_io_commit_uops_0_is_jal; // @[core.scala:143:32, :301:36, :302:50]
wire _debug_jals_1_WIRE_0 = _debug_jals_1_T_2; // @[core.scala:300:54, :302:50]
wire _debug_jals_1_T_4 = _rob_io_commit_arch_valids_1 & _debug_jals_1_T_3; // @[core.scala:143:32, :301:36, :302:41]
wire _debug_jals_1_T_5 = _debug_jals_1_T_4 & _rob_io_commit_uops_1_is_jal; // @[core.scala:143:32, :301:36, :302:50]
wire _debug_jals_1_WIRE_1 = _debug_jals_1_T_5; // @[core.scala:300:54, :302:50]
wire _debug_jals_1_T_7 = _rob_io_commit_arch_valids_2 & _debug_jals_1_T_6; // @[core.scala:143:32, :301:36, :302:41]
wire _debug_jals_1_T_8 = _debug_jals_1_T_7 & _rob_io_commit_uops_2_is_jal; // @[core.scala:143:32, :301:36, :302:50]
wire _debug_jals_1_WIRE_2 = _debug_jals_1_T_8; // @[core.scala:300:54, :302:50]
wire [1:0] _debug_jals_1_T_9 = {1'h0, _debug_jals_1_WIRE_1} + {1'h0, _debug_jals_1_WIRE_2}; // @[core.scala:300:{46,54}]
wire [1:0] _debug_jals_1_T_10 = _debug_jals_1_T_9; // @[core.scala:300:46]
wire [2:0] _debug_jals_1_T_11 = {2'h0, _debug_jals_1_WIRE_0} + {1'h0, _debug_jals_1_T_10}; // @[core.scala:300:{46,54}]
wire [1:0] _debug_jals_1_T_12 = _debug_jals_1_T_11[1:0]; // @[core.scala:300:46]
wire [64:0] _debug_jals_1_T_13 = {1'h0, debug_jals_1} + {63'h0, _debug_jals_1_T_12}; // @[core.scala:291:26, :295:34, :300:{36,46}]
wire [63:0] _debug_jals_1_T_14 = _debug_jals_1_T_13[63:0]; // @[core.scala:300:36]
wire _debug_jalrs_1_T_1 = _rob_io_commit_arch_valids_0 & _debug_jalrs_1_T; // @[core.scala:143:32, :306:36, :307:41]
wire _debug_jalrs_1_T_2 = _debug_jalrs_1_T_1 & _rob_io_commit_uops_0_is_jalr; // @[core.scala:143:32, :306:36, :307:50]
wire _debug_jalrs_1_WIRE_0 = _debug_jalrs_1_T_2; // @[core.scala:305:56, :307:50]
wire _debug_jalrs_1_T_4 = _rob_io_commit_arch_valids_1 & _debug_jalrs_1_T_3; // @[core.scala:143:32, :306:36, :307:41]
wire _debug_jalrs_1_T_5 = _debug_jalrs_1_T_4 & _rob_io_commit_uops_1_is_jalr; // @[core.scala:143:32, :306:36, :307:50]
wire _debug_jalrs_1_WIRE_1 = _debug_jalrs_1_T_5; // @[core.scala:305:56, :307:50]
wire _debug_jalrs_1_T_7 = _rob_io_commit_arch_valids_2 & _debug_jalrs_1_T_6; // @[core.scala:143:32, :306:36, :307:41]
wire _debug_jalrs_1_T_8 = _debug_jalrs_1_T_7 & _rob_io_commit_uops_2_is_jalr; // @[core.scala:143:32, :306:36, :307:50]
wire _debug_jalrs_1_WIRE_2 = _debug_jalrs_1_T_8; // @[core.scala:305:56, :307:50]
wire [1:0] _debug_jalrs_1_T_9 = {1'h0, _debug_jalrs_1_WIRE_1} + {1'h0, _debug_jalrs_1_WIRE_2}; // @[core.scala:305:{48,56}]
wire [1:0] _debug_jalrs_1_T_10 = _debug_jalrs_1_T_9; // @[core.scala:305:48]
wire [2:0] _debug_jalrs_1_T_11 = {2'h0, _debug_jalrs_1_WIRE_0} + {1'h0, _debug_jalrs_1_T_10}; // @[core.scala:305:{48,56}]
wire [1:0] _debug_jalrs_1_T_12 = _debug_jalrs_1_T_11[1:0]; // @[core.scala:305:48]
wire [64:0] _debug_jalrs_1_T_13 = {1'h0, debug_jalrs_1} + {63'h0, _debug_jalrs_1_T_12}; // @[core.scala:292:26, :295:34, :305:{38,48}]
wire [63:0] _debug_jalrs_1_T_14 = _debug_jalrs_1_T_13[63:0]; // @[core.scala:305:38]
wire _GEN_9 = _rob_io_commit_uops_0_debug_fsrc == 2'h2; // @[core.scala:143:32, :297:41]
wire _debug_brs_2_T; // @[core.scala:297:41]
assign _debug_brs_2_T = _GEN_9; // @[core.scala:297:41]
wire _debug_jals_2_T; // @[core.scala:302:41]
assign _debug_jals_2_T = _GEN_9; // @[core.scala:297:41, :302:41]
wire _debug_jalrs_2_T; // @[core.scala:307:41]
assign _debug_jalrs_2_T = _GEN_9; // @[core.scala:297:41, :307:41]
wire _debug_brs_2_T_1 = _rob_io_commit_arch_valids_0 & _debug_brs_2_T; // @[core.scala:143:32, :296:36, :297:41]
wire _debug_brs_2_T_2 = _debug_brs_2_T_1 & _rob_io_commit_uops_0_is_br; // @[core.scala:143:32, :296:36, :297:50]
wire _debug_brs_2_WIRE_0 = _debug_brs_2_T_2; // @[core.scala:295:52, :297:50]
wire _GEN_10 = _rob_io_commit_uops_1_debug_fsrc == 2'h2; // @[core.scala:143:32, :297:41]
wire _debug_brs_2_T_3; // @[core.scala:297:41]
assign _debug_brs_2_T_3 = _GEN_10; // @[core.scala:297:41]
wire _debug_jals_2_T_3; // @[core.scala:302:41]
assign _debug_jals_2_T_3 = _GEN_10; // @[core.scala:297:41, :302:41]
wire _debug_jalrs_2_T_3; // @[core.scala:307:41]
assign _debug_jalrs_2_T_3 = _GEN_10; // @[core.scala:297:41, :307:41]
wire _debug_brs_2_T_4 = _rob_io_commit_arch_valids_1 & _debug_brs_2_T_3; // @[core.scala:143:32, :296:36, :297:41]
wire _debug_brs_2_T_5 = _debug_brs_2_T_4 & _rob_io_commit_uops_1_is_br; // @[core.scala:143:32, :296:36, :297:50]
wire _debug_brs_2_WIRE_1 = _debug_brs_2_T_5; // @[core.scala:295:52, :297:50]
wire _GEN_11 = _rob_io_commit_uops_2_debug_fsrc == 2'h2; // @[core.scala:143:32, :297:41]
wire _debug_brs_2_T_6; // @[core.scala:297:41]
assign _debug_brs_2_T_6 = _GEN_11; // @[core.scala:297:41]
wire _debug_jals_2_T_6; // @[core.scala:302:41]
assign _debug_jals_2_T_6 = _GEN_11; // @[core.scala:297:41, :302:41]
wire _debug_jalrs_2_T_6; // @[core.scala:307:41]
assign _debug_jalrs_2_T_6 = _GEN_11; // @[core.scala:297:41, :307:41]
wire _debug_brs_2_T_7 = _rob_io_commit_arch_valids_2 & _debug_brs_2_T_6; // @[core.scala:143:32, :296:36, :297:41]
wire _debug_brs_2_T_8 = _debug_brs_2_T_7 & _rob_io_commit_uops_2_is_br; // @[core.scala:143:32, :296:36, :297:50]
wire _debug_brs_2_WIRE_2 = _debug_brs_2_T_8; // @[core.scala:295:52, :297:50]
wire [1:0] _debug_brs_2_T_9 = {1'h0, _debug_brs_2_WIRE_1} + {1'h0, _debug_brs_2_WIRE_2}; // @[core.scala:295:{44,52}]
wire [1:0] _debug_brs_2_T_10 = _debug_brs_2_T_9; // @[core.scala:295:44]
wire [2:0] _debug_brs_2_T_11 = {2'h0, _debug_brs_2_WIRE_0} + {1'h0, _debug_brs_2_T_10}; // @[core.scala:295:{44,52}]
wire [1:0] _debug_brs_2_T_12 = _debug_brs_2_T_11[1:0]; // @[core.scala:295:44]
wire [64:0] _debug_brs_2_T_13 = {1'h0, debug_brs_2} + {63'h0, _debug_brs_2_T_12}; // @[core.scala:290:26, :295:{34,44}]
wire [63:0] _debug_brs_2_T_14 = _debug_brs_2_T_13[63:0]; // @[core.scala:295:34]
wire _debug_jals_2_T_1 = _rob_io_commit_arch_valids_0 & _debug_jals_2_T; // @[core.scala:143:32, :301:36, :302:41]
wire _debug_jals_2_T_2 = _debug_jals_2_T_1 & _rob_io_commit_uops_0_is_jal; // @[core.scala:143:32, :301:36, :302:50]
wire _debug_jals_2_WIRE_0 = _debug_jals_2_T_2; // @[core.scala:300:54, :302:50]
wire _debug_jals_2_T_4 = _rob_io_commit_arch_valids_1 & _debug_jals_2_T_3; // @[core.scala:143:32, :301:36, :302:41]
wire _debug_jals_2_T_5 = _debug_jals_2_T_4 & _rob_io_commit_uops_1_is_jal; // @[core.scala:143:32, :301:36, :302:50]
wire _debug_jals_2_WIRE_1 = _debug_jals_2_T_5; // @[core.scala:300:54, :302:50]
wire _debug_jals_2_T_7 = _rob_io_commit_arch_valids_2 & _debug_jals_2_T_6; // @[core.scala:143:32, :301:36, :302:41]
wire _debug_jals_2_T_8 = _debug_jals_2_T_7 & _rob_io_commit_uops_2_is_jal; // @[core.scala:143:32, :301:36, :302:50]
wire _debug_jals_2_WIRE_2 = _debug_jals_2_T_8; // @[core.scala:300:54, :302:50]
wire [1:0] _debug_jals_2_T_9 = {1'h0, _debug_jals_2_WIRE_1} + {1'h0, _debug_jals_2_WIRE_2}; // @[core.scala:300:{46,54}]
wire [1:0] _debug_jals_2_T_10 = _debug_jals_2_T_9; // @[core.scala:300:46]
wire [2:0] _debug_jals_2_T_11 = {2'h0, _debug_jals_2_WIRE_0} + {1'h0, _debug_jals_2_T_10}; // @[core.scala:300:{46,54}]
wire [1:0] _debug_jals_2_T_12 = _debug_jals_2_T_11[1:0]; // @[core.scala:300:46]
wire [64:0] _debug_jals_2_T_13 = {1'h0, debug_jals_2} + {63'h0, _debug_jals_2_T_12}; // @[core.scala:291:26, :295:34, :300:{36,46}]
wire [63:0] _debug_jals_2_T_14 = _debug_jals_2_T_13[63:0]; // @[core.scala:300:36]
wire _debug_jalrs_2_T_1 = _rob_io_commit_arch_valids_0 & _debug_jalrs_2_T; // @[core.scala:143:32, :306:36, :307:41]
wire _debug_jalrs_2_T_2 = _debug_jalrs_2_T_1 & _rob_io_commit_uops_0_is_jalr; // @[core.scala:143:32, :306:36, :307:50]
wire _debug_jalrs_2_WIRE_0 = _debug_jalrs_2_T_2; // @[core.scala:305:56, :307:50]
wire _debug_jalrs_2_T_4 = _rob_io_commit_arch_valids_1 & _debug_jalrs_2_T_3; // @[core.scala:143:32, :306:36, :307:41]
wire _debug_jalrs_2_T_5 = _debug_jalrs_2_T_4 & _rob_io_commit_uops_1_is_jalr; // @[core.scala:143:32, :306:36, :307:50]
wire _debug_jalrs_2_WIRE_1 = _debug_jalrs_2_T_5; // @[core.scala:305:56, :307:50]
wire _debug_jalrs_2_T_7 = _rob_io_commit_arch_valids_2 & _debug_jalrs_2_T_6; // @[core.scala:143:32, :306:36, :307:41]
wire _debug_jalrs_2_T_8 = _debug_jalrs_2_T_7 & _rob_io_commit_uops_2_is_jalr; // @[core.scala:143:32, :306:36, :307:50]
wire _debug_jalrs_2_WIRE_2 = _debug_jalrs_2_T_8; // @[core.scala:305:56, :307:50]
wire [1:0] _debug_jalrs_2_T_9 = {1'h0, _debug_jalrs_2_WIRE_1} + {1'h0, _debug_jalrs_2_WIRE_2}; // @[core.scala:305:{48,56}]
wire [1:0] _debug_jalrs_2_T_10 = _debug_jalrs_2_T_9; // @[core.scala:305:48]
wire [2:0] _debug_jalrs_2_T_11 = {2'h0, _debug_jalrs_2_WIRE_0} + {1'h0, _debug_jalrs_2_T_10}; // @[core.scala:305:{48,56}]
wire [1:0] _debug_jalrs_2_T_12 = _debug_jalrs_2_T_11[1:0]; // @[core.scala:305:48]
wire [64:0] _debug_jalrs_2_T_13 = {1'h0, debug_jalrs_2} + {63'h0, _debug_jalrs_2_T_12}; // @[core.scala:292:26, :295:34, :305:{38,48}]
wire [63:0] _debug_jalrs_2_T_14 = _debug_jalrs_2_T_13[63:0]; // @[core.scala:305:38]
wire _debug_brs_3_T = &_rob_io_commit_uops_0_debug_fsrc; // @[core.scala:143:32, :297:41]
wire _debug_brs_3_T_1 = _rob_io_commit_arch_valids_0 & _debug_brs_3_T; // @[core.scala:143:32, :296:36, :297:41]
wire _debug_brs_3_T_2 = _debug_brs_3_T_1 & _rob_io_commit_uops_0_is_br; // @[core.scala:143:32, :296:36, :297:50]
wire _debug_brs_3_WIRE_0 = _debug_brs_3_T_2; // @[core.scala:295:52, :297:50]
wire _debug_brs_3_T_3 = &_rob_io_commit_uops_1_debug_fsrc; // @[core.scala:143:32, :297:41]
wire _debug_brs_3_T_4 = _rob_io_commit_arch_valids_1 & _debug_brs_3_T_3; // @[core.scala:143:32, :296:36, :297:41]
wire _debug_brs_3_T_5 = _debug_brs_3_T_4 & _rob_io_commit_uops_1_is_br; // @[core.scala:143:32, :296:36, :297:50]
wire _debug_brs_3_WIRE_1 = _debug_brs_3_T_5; // @[core.scala:295:52, :297:50]
wire _debug_brs_3_T_6 = &_rob_io_commit_uops_2_debug_fsrc; // @[core.scala:143:32, :297:41]
wire _debug_brs_3_T_7 = _rob_io_commit_arch_valids_2 & _debug_brs_3_T_6; // @[core.scala:143:32, :296:36, :297:41]
wire _debug_brs_3_T_8 = _debug_brs_3_T_7 & _rob_io_commit_uops_2_is_br; // @[core.scala:143:32, :296:36, :297:50]
wire _debug_brs_3_WIRE_2 = _debug_brs_3_T_8; // @[core.scala:295:52, :297:50]
wire [1:0] _debug_brs_3_T_9 = {1'h0, _debug_brs_3_WIRE_1} + {1'h0, _debug_brs_3_WIRE_2}; // @[core.scala:295:{44,52}]
wire [1:0] _debug_brs_3_T_10 = _debug_brs_3_T_9; // @[core.scala:295:44]
wire [2:0] _debug_brs_3_T_11 = {2'h0, _debug_brs_3_WIRE_0} + {1'h0, _debug_brs_3_T_10}; // @[core.scala:295:{44,52}]
wire [1:0] _debug_brs_3_T_12 = _debug_brs_3_T_11[1:0]; // @[core.scala:295:44]
wire [64:0] _debug_brs_3_T_13 = {1'h0, debug_brs_3} + {63'h0, _debug_brs_3_T_12}; // @[core.scala:290:26, :295:{34,44}]
wire [63:0] _debug_brs_3_T_14 = _debug_brs_3_T_13[63:0]; // @[core.scala:295:34]
wire _debug_jals_3_T = &_rob_io_commit_uops_0_debug_fsrc; // @[core.scala:143:32, :297:41, :302:41]
wire _debug_jals_3_T_1 = _rob_io_commit_arch_valids_0 & _debug_jals_3_T; // @[core.scala:143:32, :301:36, :302:41]
wire _debug_jals_3_T_2 = _debug_jals_3_T_1 & _rob_io_commit_uops_0_is_jal; // @[core.scala:143:32, :301:36, :302:50]
wire _debug_jals_3_WIRE_0 = _debug_jals_3_T_2; // @[core.scala:300:54, :302:50]
wire _debug_jals_3_T_3 = &_rob_io_commit_uops_1_debug_fsrc; // @[core.scala:143:32, :297:41, :302:41]
wire _debug_jals_3_T_4 = _rob_io_commit_arch_valids_1 & _debug_jals_3_T_3; // @[core.scala:143:32, :301:36, :302:41]
wire _debug_jals_3_T_5 = _debug_jals_3_T_4 & _rob_io_commit_uops_1_is_jal; // @[core.scala:143:32, :301:36, :302:50]
wire _debug_jals_3_WIRE_1 = _debug_jals_3_T_5; // @[core.scala:300:54, :302:50]
wire _debug_jals_3_T_6 = &_rob_io_commit_uops_2_debug_fsrc; // @[core.scala:143:32, :297:41, :302:41]
wire _debug_jals_3_T_7 = _rob_io_commit_arch_valids_2 & _debug_jals_3_T_6; // @[core.scala:143:32, :301:36, :302:41]
wire _debug_jals_3_T_8 = _debug_jals_3_T_7 & _rob_io_commit_uops_2_is_jal; // @[core.scala:143:32, :301:36, :302:50]
wire _debug_jals_3_WIRE_2 = _debug_jals_3_T_8; // @[core.scala:300:54, :302:50]
wire [1:0] _debug_jals_3_T_9 = {1'h0, _debug_jals_3_WIRE_1} + {1'h0, _debug_jals_3_WIRE_2}; // @[core.scala:300:{46,54}]
wire [1:0] _debug_jals_3_T_10 = _debug_jals_3_T_9; // @[core.scala:300:46]
wire [2:0] _debug_jals_3_T_11 = {2'h0, _debug_jals_3_WIRE_0} + {1'h0, _debug_jals_3_T_10}; // @[core.scala:300:{46,54}]
wire [1:0] _debug_jals_3_T_12 = _debug_jals_3_T_11[1:0]; // @[core.scala:300:46]
wire [64:0] _debug_jals_3_T_13 = {1'h0, debug_jals_3} + {63'h0, _debug_jals_3_T_12}; // @[core.scala:291:26, :295:34, :300:{36,46}]
wire [63:0] _debug_jals_3_T_14 = _debug_jals_3_T_13[63:0]; // @[core.scala:300:36]
wire _debug_jalrs_3_T = &_rob_io_commit_uops_0_debug_fsrc; // @[core.scala:143:32, :297:41, :307:41]
wire _debug_jalrs_3_T_1 = _rob_io_commit_arch_valids_0 & _debug_jalrs_3_T; // @[core.scala:143:32, :306:36, :307:41]
wire _debug_jalrs_3_T_2 = _debug_jalrs_3_T_1 & _rob_io_commit_uops_0_is_jalr; // @[core.scala:143:32, :306:36, :307:50]
wire _debug_jalrs_3_WIRE_0 = _debug_jalrs_3_T_2; // @[core.scala:305:56, :307:50]
wire _debug_jalrs_3_T_3 = &_rob_io_commit_uops_1_debug_fsrc; // @[core.scala:143:32, :297:41, :307:41]
wire _debug_jalrs_3_T_4 = _rob_io_commit_arch_valids_1 & _debug_jalrs_3_T_3; // @[core.scala:143:32, :306:36, :307:41]
wire _debug_jalrs_3_T_5 = _debug_jalrs_3_T_4 & _rob_io_commit_uops_1_is_jalr; // @[core.scala:143:32, :306:36, :307:50]
wire _debug_jalrs_3_WIRE_1 = _debug_jalrs_3_T_5; // @[core.scala:305:56, :307:50]
wire _debug_jalrs_3_T_6 = &_rob_io_commit_uops_2_debug_fsrc; // @[core.scala:143:32, :297:41, :307:41]
wire _debug_jalrs_3_T_7 = _rob_io_commit_arch_valids_2 & _debug_jalrs_3_T_6; // @[core.scala:143:32, :306:36, :307:41]
wire _debug_jalrs_3_T_8 = _debug_jalrs_3_T_7 & _rob_io_commit_uops_2_is_jalr; // @[core.scala:143:32, :306:36, :307:50]
wire _debug_jalrs_3_WIRE_2 = _debug_jalrs_3_T_8; // @[core.scala:305:56, :307:50]
wire [1:0] _debug_jalrs_3_T_9 = {1'h0, _debug_jalrs_3_WIRE_1} + {1'h0, _debug_jalrs_3_WIRE_2}; // @[core.scala:305:{48,56}]
wire [1:0] _debug_jalrs_3_T_10 = _debug_jalrs_3_T_9; // @[core.scala:305:48]
wire [2:0] _debug_jalrs_3_T_11 = {2'h0, _debug_jalrs_3_WIRE_0} + {1'h0, _debug_jalrs_3_T_10}; // @[core.scala:305:{48,56}]
wire [1:0] _debug_jalrs_3_T_12 = _debug_jalrs_3_T_11[1:0]; // @[core.scala:305:48]
wire [64:0] _debug_jalrs_3_T_13 = {1'h0, debug_jalrs_3} + {63'h0, _debug_jalrs_3_T_12}; // @[core.scala:292:26, :295:34, :305:{38,48}]
wire [63:0] _debug_jalrs_3_T_14 = _debug_jalrs_3_T_13[63:0]; // @[core.scala:305:38]
wire [64:0] _debug_tsc_reg_T = {1'h0, debug_tsc_reg} + 65'h1; // @[core.scala:288:30, :316:34]
wire [63:0] _debug_tsc_reg_T_1 = _debug_tsc_reg_T[63:0]; // @[core.scala:316:34]
wire [1:0] _GEN_12 = {_rob_io_commit_arch_valids_2, _rob_io_commit_arch_valids_1}; // @[core.scala:143:32, :317:71]
wire [1:0] debug_irt_reg_hi; // @[core.scala:317:71]
assign debug_irt_reg_hi = _GEN_12; // @[core.scala:317:71]
wire [1:0] csr_io_retire_hi; // @[core.scala:1015:66]
assign csr_io_retire_hi = _GEN_12; // @[core.scala:317:71, :1015:66]
wire [2:0] _debug_irt_reg_T = {debug_irt_reg_hi, _rob_io_commit_arch_valids_0}; // @[core.scala:143:32, :317:71]
wire _debug_irt_reg_T_1 = _debug_irt_reg_T[0]; // @[core.scala:317:{44,71}]
wire _debug_irt_reg_T_2 = _debug_irt_reg_T[1]; // @[core.scala:317:{44,71}]
wire _debug_irt_reg_T_3 = _debug_irt_reg_T[2]; // @[core.scala:317:{44,71}]
wire [1:0] _debug_irt_reg_T_4 = {1'h0, _debug_irt_reg_T_2} + {1'h0, _debug_irt_reg_T_3}; // @[core.scala:317:44]
wire [1:0] _debug_irt_reg_T_5 = _debug_irt_reg_T_4; // @[core.scala:317:44]
wire [2:0] _debug_irt_reg_T_6 = {2'h0, _debug_irt_reg_T_1} + {1'h0, _debug_irt_reg_T_5}; // @[core.scala:317:44]
wire [1:0] _debug_irt_reg_T_7 = _debug_irt_reg_T_6[1:0]; // @[core.scala:317:44]
wire [64:0] _debug_irt_reg_T_8 = {1'h0, debug_irt_reg} + {63'h0, _debug_irt_reg_T_7}; // @[core.scala:289:30, :295:34, :317:{34,44}]
wire [63:0] _debug_irt_reg_T_9 = _debug_irt_reg_T_8[63:0]; // @[core.scala:317:34]
wire _io_ifu_flush_icache_T = _rob_io_commit_arch_valids_0 & _rob_io_commit_uops_0_is_fencei; // @[core.scala:143:32, :388:35]
wire _io_ifu_flush_icache_T_1 = dec_valids_0 & dec_uops_0_is_jalr; // @[core.scala:157:24, :158:24, :389:28]
wire _io_ifu_flush_icache_T_2 = _io_ifu_flush_icache_T_1 & _csr_io_status_debug; // @[core.scala:271:19, :389:{28,51}]
reg io_ifu_flush_icache_REG; // @[core.scala:389:13]
wire _io_ifu_flush_icache_T_3 = _io_ifu_flush_icache_T | io_ifu_flush_icache_REG; // @[core.scala:388:{35,71}, :389:13]
wire _io_ifu_flush_icache_T_4 = _rob_io_commit_arch_valids_1 & _rob_io_commit_uops_1_is_fencei; // @[core.scala:143:32, :388:35]
wire _io_ifu_flush_icache_T_5 = dec_valids_1 & dec_uops_1_is_jalr; // @[core.scala:157:24, :158:24, :389:28]
wire _io_ifu_flush_icache_T_6 = _io_ifu_flush_icache_T_5 & _csr_io_status_debug; // @[core.scala:271:19, :389:{28,51}]
reg io_ifu_flush_icache_REG_1; // @[core.scala:389:13]
wire _io_ifu_flush_icache_T_7 = _io_ifu_flush_icache_T_4 | io_ifu_flush_icache_REG_1; // @[core.scala:388:{35,71}, :389:13]
wire _io_ifu_flush_icache_T_8 = _rob_io_commit_arch_valids_2 & _rob_io_commit_uops_2_is_fencei; // @[core.scala:143:32, :388:35]
wire _io_ifu_flush_icache_T_9 = dec_valids_2 & dec_uops_2_is_jalr; // @[core.scala:157:24, :158:24, :389:28]
wire _io_ifu_flush_icache_T_10 = _io_ifu_flush_icache_T_9 & _csr_io_status_debug; // @[core.scala:271:19, :389:{28,51}]
reg io_ifu_flush_icache_REG_2; // @[core.scala:389:13]
wire _io_ifu_flush_icache_T_11 = _io_ifu_flush_icache_T_8 | io_ifu_flush_icache_REG_2; // @[core.scala:388:{35,71}, :389:13]
wire _io_ifu_flush_icache_T_12 = _io_ifu_flush_icache_T_3 | _io_ifu_flush_icache_T_7; // @[core.scala:388:71, :390:13]
assign _io_ifu_flush_icache_T_13 = _io_ifu_flush_icache_T_12 | _io_ifu_flush_icache_T_11; // @[core.scala:388:71, :390:13]
assign io_ifu_flush_icache_0 = _io_ifu_flush_icache_T_13; // @[core.scala:51:7, :390:13]
reg REG; // @[core.scala:401:16]
reg [2:0] flush_typ; // @[core.scala:404:28]
wire _io_ifu_redirect_pc_T = flush_typ == 3'h3; // @[core.scala:404:28, :411:44]
reg [39:0] io_ifu_redirect_pc_REG; // @[core.scala:412:49]
reg [39:0] io_ifu_redirect_pc_REG_1; // @[core.scala:412:41]
wire [39:0] _io_ifu_redirect_pc_T_1 = _io_ifu_redirect_pc_T ? io_ifu_redirect_pc_REG_1 : _csr_io_evec; // @[core.scala:271:19, :411:{33,44}, :412:41]
wire [39:0] _flush_pc_T = ~io_ifu_get_pc_0_pc_0; // @[util.scala:237:7]
wire [39:0] _flush_pc_T_1 = {_flush_pc_T[39:6], 6'h3F}; // @[util.scala:237:{7,11}]
wire [39:0] _flush_pc_T_2 = ~_flush_pc_T_1; // @[util.scala:237:{5,11}]
reg [5:0] flush_pc_REG; // @[core.scala:416:32]
wire [40:0] _flush_pc_T_3 = {1'h0, _flush_pc_T_2} + {35'h0, flush_pc_REG}; // @[util.scala:237:5]
wire [39:0] _flush_pc_T_4 = _flush_pc_T_3[39:0]; // @[core.scala:416:23]
reg flush_pc_REG_1; // @[core.scala:417:36]
wire [1:0] _flush_pc_T_5 = {flush_pc_REG_1, 1'h0}; // @[core.scala:417:{28,36}]
wire [40:0] _flush_pc_T_6 = {1'h0, _flush_pc_T_4} - {39'h0, _flush_pc_T_5}; // @[core.scala:416:23, :417:{23,28}]
wire [39:0] flush_pc = _flush_pc_T_6[39:0]; // @[core.scala:417:23]
reg flush_pc_next_REG; // @[core.scala:418:49]
wire [2:0] _flush_pc_next_T = flush_pc_next_REG ? 3'h2 : 3'h4; // @[core.scala:418:{41,49}]
wire [40:0] _flush_pc_next_T_1 = {1'h0, flush_pc} + {38'h0, _flush_pc_next_T}; // @[core.scala:417:23, :418:{36,41}]
wire [39:0] flush_pc_next = _flush_pc_next_T_1[39:0]; // @[core.scala:418:36]
wire _io_ifu_redirect_pc_T_2 = flush_typ == 3'h2; // @[rob.scala:167:40]
wire [39:0] _io_ifu_redirect_pc_T_3 = _io_ifu_redirect_pc_T_2 ? flush_pc : flush_pc_next; // @[rob.scala:167:40]
reg [4:0] io_ifu_redirect_ftq_idx_REG; // @[core.scala:423:39]
reg REG_1; // @[core.scala:424:50]
wire _T_18 = brupdate_b2_mispredict & ~REG_1; // @[core.scala:188:23, :424:{39,42,50}]
wire [39:0] _block_pc_T = ~io_ifu_get_pc_1_pc_0; // @[util.scala:237:7]
wire [39:0] _block_pc_T_1 = {_block_pc_T[39:6], 6'h3F}; // @[util.scala:237:{7,11}]
wire [39:0] block_pc = ~_block_pc_T_1; // @[util.scala:237:{5,11}]
wire [39:0] uop_maybe_pc = {block_pc[39:6], block_pc[5:0] | brupdate_b2_uop_pc_lob}; // @[util.scala:237:5]
wire [39:0] _jal_br_target_T = uop_maybe_pc; // @[core.scala:426:33, :429:36]
wire _npc_T = brupdate_b2_uop_is_rvc | brupdate_b2_uop_edge_inst; // @[core.scala:188:23, :427:57]
wire [2:0] _npc_T_1 = _npc_T ? 3'h2 : 3'h4; // @[core.scala:427:{33,57}]
wire [40:0] _npc_T_2 = {1'h0, uop_maybe_pc} + {38'h0, _npc_T_1}; // @[core.scala:418:36, :426:33, :427:{28,33}]
wire [39:0] npc = _npc_T_2[39:0]; // @[core.scala:427:28]
wire [39:0] _jal_br_target_T_10; // @[core.scala:430:75]
wire [39:0] jal_br_target; // @[core.scala:428:29]
wire [40:0] _jal_br_target_T_1 = {_jal_br_target_T[39], _jal_br_target_T} + {{20{brupdate_b2_target_offset[20]}}, brupdate_b2_target_offset}; // @[core.scala:188:23, :429:{36,43}]
wire [39:0] _jal_br_target_T_2 = _jal_br_target_T_1[39:0]; // @[core.scala:429:43]
wire [39:0] _jal_br_target_T_3 = _jal_br_target_T_2; // @[core.scala:429:43]
wire [38:0] _jal_br_target_T_4 = {39{brupdate_b2_uop_edge_inst}}; // @[core.scala:188:23, :430:12]
wire [39:0] _jal_br_target_T_5 = {_jal_br_target_T_4, 1'h0}; // @[core.scala:430:{12,61}]
wire [39:0] _jal_br_target_T_6 = _jal_br_target_T_5; // @[core.scala:430:{61,67}]
wire [40:0] _jal_br_target_T_7 = {_jal_br_target_T_3[39], _jal_br_target_T_3} + {_jal_br_target_T_6[39], _jal_br_target_T_6}; // @[core.scala:429:{43,71}, :430:67]
wire [39:0] _jal_br_target_T_8 = _jal_br_target_T_7[39:0]; // @[core.scala:429:71]
wire [39:0] _jal_br_target_T_9 = _jal_br_target_T_8; // @[core.scala:429:71]
assign _jal_br_target_T_10 = _jal_br_target_T_9; // @[core.scala:429:71, :430:75]
assign jal_br_target = _jal_br_target_T_10; // @[core.scala:428:29, :430:75]
wire _bj_addr_T = brupdate_b2_cfi_type == 3'h3; // @[core.scala:188:23, :431:44]
wire [39:0] bj_addr = _bj_addr_T ? brupdate_b2_jalr_target : jal_br_target; // @[core.scala:188:23, :428:29, :431:{22,44}]
wire _mispredict_target_T = brupdate_b2_pc_sel == 2'h0; // @[core.scala:188:23, :432:52]
wire [39:0] mispredict_target = _mispredict_target_T ? npc : bj_addr; // @[core.scala:427:28, :431:22, :432:{32,52}]
assign io_ifu_redirect_val_0 = REG | _T_18; // @[core.scala:51:7, :401:{16,38}, :402:27, :424:{39,72}]
assign io_ifu_redirect_pc_0 = REG ? (flush_typ[0] ? _io_ifu_redirect_pc_T_1 : _io_ifu_redirect_pc_T_3) : mispredict_target; // @[rob.scala:166:40]
assign io_ifu_redirect_ftq_idx_0 = REG ? io_ifu_redirect_ftq_idx_REG : brupdate_b2_uop_ftq_idx; // @[core.scala:51:7, :188:23, :401:{16,38}, :423:{29,39}, :424:72]
wire _GEN_13 = brupdate_b2_cfi_type == 3'h1; // @[core.scala:188:23, :437:48]
wire _use_same_ghist_T; // @[core.scala:437:48]
assign _use_same_ghist_T = _GEN_13; // @[core.scala:437:48]
wire _next_ghist_T; // @[core.scala:447:28]
assign _next_ghist_T = _GEN_13; // @[core.scala:437:48, :447:28]
wire _use_same_ghist_T_1 = ~brupdate_b2_taken; // @[core.scala:188:23, :438:27]
wire _use_same_ghist_T_2 = _use_same_ghist_T & _use_same_ghist_T_1; // @[core.scala:437:{48,59}, :438:27]
wire [39:0] _use_same_ghist_T_3 = ~block_pc; // @[util.scala:237:5]
wire [39:0] _use_same_ghist_T_4 = {_use_same_ghist_T_3[39:3], 3'h7}; // @[frontend.scala:160:{33,39}]
wire [39:0] _use_same_ghist_T_5 = ~_use_same_ghist_T_4; // @[frontend.scala:160:{31,39}]
wire [39:0] _use_same_ghist_T_6 = ~npc; // @[frontend.scala:160:33]
wire [39:0] _use_same_ghist_T_7 = {_use_same_ghist_T_6[39:3], 3'h7}; // @[frontend.scala:160:{33,39}]
wire [39:0] _use_same_ghist_T_8 = ~_use_same_ghist_T_7; // @[frontend.scala:160:{31,39}]
wire _use_same_ghist_T_9 = _use_same_ghist_T_5 == _use_same_ghist_T_8; // @[frontend.scala:160:31]
wire use_same_ghist = _use_same_ghist_T_2 & _use_same_ghist_T_9; // @[core.scala:437:59, :438:46, :439:47]
wire [3:0] _cfi_idx_T_2 = {_cfi_idx_T, 3'h0}; // @[core.scala:442:{10,32}]
wire [5:0] _cfi_idx_T_3 = {brupdate_b2_uop_pc_lob[5:4], brupdate_b2_uop_pc_lob[3:0] ^ _cfi_idx_T_2}; // @[core.scala:188:23, :441:43, :442:10]
wire [2:0] cfi_idx = _cfi_idx_T_3[3:1]; // @[core.scala:441:43, :442:74]
wire [2:0] next_ghist_cfi_idx_fixed = cfi_idx; // @[frontend.scala:85:32]
wire _GEN_14 = io_ifu_get_pc_1_entry_cfi_idx_bits_0 == cfi_idx; // @[core.scala:51:7, :442:74, :451:55]
wire _next_ghist_T_1; // @[core.scala:451:55]
assign _next_ghist_T_1 = _GEN_14; // @[core.scala:451:55]
wire _next_ghist_T_3; // @[core.scala:452:55]
assign _next_ghist_T_3 = _GEN_14; // @[core.scala:451:55, :452:55]
wire _next_ghist_T_2 = io_ifu_get_pc_1_entry_cfi_is_call_0 & _next_ghist_T_1; // @[core.scala:51:7, :451:{29,55}]
wire _next_ghist_new_history_ras_idx_T = _next_ghist_T_2; // @[frontend.scala:123:42]
wire _next_ghist_T_4 = io_ifu_get_pc_1_entry_cfi_is_ret_0 & _next_ghist_T_3; // @[core.scala:51:7, :452:{29,55}]
wire _next_ghist_new_history_ras_idx_T_4 = _next_ghist_T_4; // @[frontend.scala:124:42]
wire [7:0] next_ghist_cfi_idx_oh = 8'h1 << next_ghist_cfi_idx_fixed; // @[OneHot.scala:58:35]
wire [7:0] _next_ghist_not_taken_branches_T = next_ghist_cfi_idx_oh; // @[OneHot.scala:58:35]
wire [4:0] _next_ghist_new_history_ras_idx_T_9; // @[frontend.scala:123:31]
wire [63:0] next_ghist_old_history; // @[frontend.scala:87:27]
wire next_ghist_new_saw_branch_not_taken; // @[frontend.scala:87:27]
wire next_ghist_new_saw_branch_taken; // @[frontend.scala:87:27]
wire [4:0] next_ghist_ras_idx; // @[frontend.scala:87:27]
wire [7:0] _next_ghist_not_taken_branches_T_1 = {1'h0, next_ghist_cfi_idx_oh[7:1]}; // @[OneHot.scala:58:35]
wire [7:0] _next_ghist_not_taken_branches_T_2 = {2'h0, next_ghist_cfi_idx_oh[7:2]}; // @[OneHot.scala:58:35]
wire [7:0] _next_ghist_not_taken_branches_T_3 = {3'h0, next_ghist_cfi_idx_oh[7:3]}; // @[OneHot.scala:58:35]
wire [7:0] _next_ghist_not_taken_branches_T_4 = {4'h0, next_ghist_cfi_idx_oh[7:4]}; // @[OneHot.scala:58:35]
wire [7:0] _next_ghist_not_taken_branches_T_5 = {5'h0, next_ghist_cfi_idx_oh[7:5]}; // @[OneHot.scala:58:35]
wire [7:0] _next_ghist_not_taken_branches_T_6 = {6'h0, next_ghist_cfi_idx_oh[7:6]}; // @[OneHot.scala:58:35]
wire [7:0] _next_ghist_not_taken_branches_T_7 = {7'h0, next_ghist_cfi_idx_oh[7]}; // @[OneHot.scala:58:35]
wire [7:0] _next_ghist_not_taken_branches_T_8 = _next_ghist_not_taken_branches_T | _next_ghist_not_taken_branches_T_1; // @[util.scala:373:{29,45}]
wire [7:0] _next_ghist_not_taken_branches_T_9 = _next_ghist_not_taken_branches_T_8 | _next_ghist_not_taken_branches_T_2; // @[util.scala:373:{29,45}]
wire [7:0] _next_ghist_not_taken_branches_T_10 = _next_ghist_not_taken_branches_T_9 | _next_ghist_not_taken_branches_T_3; // @[util.scala:373:{29,45}]
wire [7:0] _next_ghist_not_taken_branches_T_11 = _next_ghist_not_taken_branches_T_10 | _next_ghist_not_taken_branches_T_4; // @[util.scala:373:{29,45}]
wire [7:0] _next_ghist_not_taken_branches_T_12 = _next_ghist_not_taken_branches_T_11 | _next_ghist_not_taken_branches_T_5; // @[util.scala:373:{29,45}]
wire [7:0] _next_ghist_not_taken_branches_T_13 = _next_ghist_not_taken_branches_T_12 | _next_ghist_not_taken_branches_T_6; // @[util.scala:373:{29,45}]
wire [7:0] _next_ghist_not_taken_branches_T_14 = _next_ghist_not_taken_branches_T_13 | _next_ghist_not_taken_branches_T_7; // @[util.scala:373:{29,45}]
wire _next_ghist_not_taken_branches_T_15 = _next_ghist_T & brupdate_b2_taken; // @[frontend.scala:90:84]
wire [7:0] _next_ghist_not_taken_branches_T_16 = _next_ghist_not_taken_branches_T_15 ? next_ghist_cfi_idx_oh : 8'h0; // @[OneHot.scala:58:35]
wire [7:0] _next_ghist_not_taken_branches_T_17 = ~_next_ghist_not_taken_branches_T_16; // @[frontend.scala:90:{69,73}]
wire [7:0] _next_ghist_not_taken_branches_T_18 = _next_ghist_not_taken_branches_T_14 & _next_ghist_not_taken_branches_T_17; // @[util.scala:373:45]
wire [7:0] _next_ghist_not_taken_branches_T_20 = _next_ghist_not_taken_branches_T_18; // @[frontend.scala:89:44, :90:67]
wire [7:0] next_ghist_not_taken_branches = io_ifu_get_pc_1_entry_br_mask_0 & _next_ghist_not_taken_branches_T_20; // @[frontend.scala:89:{39,44}]
wire [64:0] _GEN_15 = {io_ifu_get_pc_1_ghist_old_history_0, 1'h0}; // @[frontend.scala:67:75]
wire [64:0] _next_ghist_base_T; // @[frontend.scala:67:75]
assign _next_ghist_base_T = _GEN_15; // @[frontend.scala:67:75]
wire [64:0] _next_ghist_base_T_2; // @[frontend.scala:68:75]
assign _next_ghist_base_T_2 = _GEN_15; // @[frontend.scala:67:75, :68:75]
wire [64:0] _next_ghist_new_history_old_history_T; // @[frontend.scala:67:75]
assign _next_ghist_new_history_old_history_T = _GEN_15; // @[frontend.scala:67:75]
wire [64:0] _next_ghist_new_history_old_history_T_2; // @[frontend.scala:68:75]
assign _next_ghist_new_history_old_history_T_2 = _GEN_15; // @[frontend.scala:67:75, :68:75]
wire [64:0] _next_ghist_new_history_old_history_T_6; // @[frontend.scala:67:75]
assign _next_ghist_new_history_old_history_T_6 = _GEN_15; // @[frontend.scala:67:75]
wire [64:0] _next_ghist_new_history_old_history_T_8; // @[frontend.scala:68:75]
assign _next_ghist_new_history_old_history_T_8 = _GEN_15; // @[frontend.scala:67:75, :68:75]
wire [64:0] _next_ghist_new_history_old_history_T_13; // @[frontend.scala:67:75]
assign _next_ghist_new_history_old_history_T_13 = _GEN_15; // @[frontend.scala:67:75]
wire [64:0] _next_ghist_new_history_old_history_T_15; // @[frontend.scala:68:75]
assign _next_ghist_new_history_old_history_T_15 = _GEN_15; // @[frontend.scala:67:75, :68:75]
wire [64:0] _next_ghist_new_history_old_history_T_19; // @[frontend.scala:67:75]
assign _next_ghist_new_history_old_history_T_19 = _GEN_15; // @[frontend.scala:67:75]
wire [64:0] _next_ghist_new_history_old_history_T_21; // @[frontend.scala:68:75]
assign _next_ghist_new_history_old_history_T_21 = _GEN_15; // @[frontend.scala:67:75, :68:75]
wire [64:0] _next_ghist_base_T_1 = {_next_ghist_base_T[64:1], 1'h1}; // @[frontend.scala:67:{75,80}]
wire [64:0] _GEN_16 = {1'h0, io_ifu_get_pc_1_ghist_old_history_0}; // @[frontend.scala:68:12]
wire [64:0] _next_ghist_base_T_3 = io_ifu_get_pc_1_ghist_new_saw_branch_not_taken_0 ? _next_ghist_base_T_2 : _GEN_16; // @[frontend.scala:68:{12,75}]
wire [64:0] next_ghist_base = io_ifu_get_pc_1_ghist_new_saw_branch_taken_0 ? _next_ghist_base_T_1 : _next_ghist_base_T_3; // @[frontend.scala:67:{12,80}, :68:12]
wire _next_ghist_cfi_in_bank_0_T_1 = ~(next_ghist_cfi_idx_fixed[2]); // @[frontend.scala:85:32, :104:67]
wire next_ghist_cfi_in_bank_0 = _next_ghist_cfi_in_bank_0_T & _next_ghist_cfi_in_bank_0_T_1; // @[frontend.scala:104:{37,50,67}]
wire [2:0] _next_ghist_ignore_second_bank_T = io_ifu_get_pc_1_pc_0[5:3]; // @[frontend.scala:152:28]
wire _next_ghist_ignore_second_bank_T_1 = &_next_ghist_ignore_second_bank_T; // @[frontend.scala:152:{28,66}]
wire _next_ghist_ignore_second_bank_T_2 = _next_ghist_ignore_second_bank_T_1; // @[frontend.scala:152:{21,66}]
wire next_ghist_ignore_second_bank = next_ghist_cfi_in_bank_0 | _next_ghist_ignore_second_bank_T_2; // @[frontend.scala:104:50, :105:46, :152:21]
wire [3:0] _next_ghist_first_bank_saw_not_taken_T = next_ghist_not_taken_branches[3:0]; // @[frontend.scala:89:39, :107:56]
wire _next_ghist_first_bank_saw_not_taken_T_1 = |_next_ghist_first_bank_saw_not_taken_T; // @[frontend.scala:107:{56,72}]
wire next_ghist_first_bank_saw_not_taken = _next_ghist_first_bank_saw_not_taken_T_1 | io_ifu_get_pc_1_ghist_current_saw_branch_not_taken_0; // @[frontend.scala:107:{72,80}]
wire [64:0] _next_ghist_new_history_old_history_T_1 = {_next_ghist_new_history_old_history_T[64:1], 1'h1}; // @[frontend.scala:67:{75,80}]
wire [64:0] _next_ghist_new_history_old_history_T_3 = io_ifu_get_pc_1_ghist_new_saw_branch_not_taken_0 ? _next_ghist_new_history_old_history_T_2 : _GEN_16; // @[frontend.scala:68:{12,75}]
wire [64:0] _next_ghist_new_history_old_history_T_4 = io_ifu_get_pc_1_ghist_new_saw_branch_taken_0 ? _next_ghist_new_history_old_history_T_1 : _next_ghist_new_history_old_history_T_3; // @[frontend.scala:67:{12,80}, :68:12]
wire _GEN_17 = _next_ghist_T & next_ghist_cfi_in_bank_0; // @[frontend.scala:104:50, :112:59]
wire _next_ghist_new_history_new_saw_branch_taken_T; // @[frontend.scala:112:59]
assign _next_ghist_new_history_new_saw_branch_taken_T = _GEN_17; // @[frontend.scala:112:59]
wire _next_ghist_new_history_old_history_T_5; // @[frontend.scala:114:50]
assign _next_ghist_new_history_old_history_T_5 = _GEN_17; // @[frontend.scala:112:59, :114:50]
wire [64:0] _next_ghist_new_history_old_history_T_7 = {_next_ghist_new_history_old_history_T_6[64:1], 1'h1}; // @[frontend.scala:67:{75,80}]
wire [64:0] _next_ghist_new_history_old_history_T_9 = io_ifu_get_pc_1_ghist_new_saw_branch_not_taken_0 ? _next_ghist_new_history_old_history_T_8 : _GEN_16; // @[frontend.scala:68:{12,75}]
wire [64:0] _next_ghist_new_history_old_history_T_10 = io_ifu_get_pc_1_ghist_new_saw_branch_taken_0 ? _next_ghist_new_history_old_history_T_7 : _next_ghist_new_history_old_history_T_9; // @[frontend.scala:67:{12,80}, :68:12]
wire [65:0] _next_ghist_new_history_old_history_T_11 = {_next_ghist_new_history_old_history_T_10, 1'h0}; // @[frontend.scala:67:12, :114:110]
wire [65:0] _next_ghist_new_history_old_history_T_12 = {_next_ghist_new_history_old_history_T_11[65:1], 1'h1}; // @[frontend.scala:114:{110,115}]
wire [64:0] _next_ghist_new_history_old_history_T_14 = {_next_ghist_new_history_old_history_T_13[64:1], 1'h1}; // @[frontend.scala:67:{75,80}]
wire [64:0] _next_ghist_new_history_old_history_T_16 = io_ifu_get_pc_1_ghist_new_saw_branch_not_taken_0 ? _next_ghist_new_history_old_history_T_15 : _GEN_16; // @[frontend.scala:68:{12,75}]
wire [64:0] _next_ghist_new_history_old_history_T_17 = io_ifu_get_pc_1_ghist_new_saw_branch_taken_0 ? _next_ghist_new_history_old_history_T_14 : _next_ghist_new_history_old_history_T_16; // @[frontend.scala:67:{12,80}, :68:12]
wire [65:0] _next_ghist_new_history_old_history_T_18 = {_next_ghist_new_history_old_history_T_17, 1'h0}; // @[frontend.scala:67:12, :115:110]
wire [64:0] _next_ghist_new_history_old_history_T_20 = {_next_ghist_new_history_old_history_T_19[64:1], 1'h1}; // @[frontend.scala:67:{75,80}]
wire [64:0] _next_ghist_new_history_old_history_T_22 = io_ifu_get_pc_1_ghist_new_saw_branch_not_taken_0 ? _next_ghist_new_history_old_history_T_21 : _GEN_16; // @[frontend.scala:68:{12,75}]
wire [64:0] _next_ghist_new_history_old_history_T_23 = io_ifu_get_pc_1_ghist_new_saw_branch_taken_0 ? _next_ghist_new_history_old_history_T_20 : _next_ghist_new_history_old_history_T_22; // @[frontend.scala:67:{12,80}, :68:12]
wire [65:0] _next_ghist_new_history_old_history_T_24 = next_ghist_first_bank_saw_not_taken ? _next_ghist_new_history_old_history_T_18 : {1'h0, _next_ghist_new_history_old_history_T_23}; // @[frontend.scala:67:12, :107:80, :115:{39,110}]
wire [65:0] _next_ghist_new_history_old_history_T_25 = _next_ghist_new_history_old_history_T_5 ? _next_ghist_new_history_old_history_T_12 : _next_ghist_new_history_old_history_T_24; // @[frontend.scala:114:{39,50,115}, :115:39]
assign next_ghist_old_history = next_ghist_ignore_second_bank ? _next_ghist_new_history_old_history_T_4[63:0] : _next_ghist_new_history_old_history_T_25[63:0]; // @[frontend.scala:67:12, :87:27, :105:46, :109:33, :110:33, :114:{33,39}]
wire [3:0] _next_ghist_new_history_new_saw_branch_not_taken_T = next_ghist_not_taken_branches[7:4]; // @[frontend.scala:89:39, :118:67]
wire _next_ghist_new_history_new_saw_branch_not_taken_T_1 = |_next_ghist_new_history_new_saw_branch_not_taken_T; // @[frontend.scala:118:{67,92}]
assign next_ghist_new_saw_branch_not_taken = next_ghist_ignore_second_bank ? next_ghist_first_bank_saw_not_taken : _next_ghist_new_history_new_saw_branch_not_taken_T_1; // @[frontend.scala:87:27, :105:46, :107:80, :109:33, :111:46, :118:{46,92}]
wire _next_ghist_new_history_new_saw_branch_taken_T_2 = _next_ghist_new_history_new_saw_branch_taken_T_1 & _next_ghist_T; // @[frontend.scala:119:{59,72}]
wire _next_ghist_new_history_new_saw_branch_taken_T_3 = ~next_ghist_cfi_in_bank_0; // @[frontend.scala:104:50, :119:88]
wire _next_ghist_new_history_new_saw_branch_taken_T_4 = _next_ghist_new_history_new_saw_branch_taken_T_2 & _next_ghist_new_history_new_saw_branch_taken_T_3; // @[frontend.scala:119:{72,85,88}]
assign next_ghist_new_saw_branch_taken = next_ghist_ignore_second_bank ? _next_ghist_new_history_new_saw_branch_taken_T : _next_ghist_new_history_new_saw_branch_taken_T_4; // @[frontend.scala:87:27, :105:46, :109:33, :112:{46,59}, :119:{46,85}]
wire [5:0] _GEN_18 = {1'h0, io_ifu_get_pc_1_ghist_ras_idx_0}; // @[util.scala:203:14]
wire [5:0] _next_ghist_new_history_ras_idx_T_1 = _GEN_18 + 6'h1; // @[util.scala:203:14]
wire [4:0] _next_ghist_new_history_ras_idx_T_2 = _next_ghist_new_history_ras_idx_T_1[4:0]; // @[util.scala:203:14]
wire [4:0] _next_ghist_new_history_ras_idx_T_3 = _next_ghist_new_history_ras_idx_T_2; // @[util.scala:203:{14,20}]
wire [5:0] _next_ghist_new_history_ras_idx_T_5 = _GEN_18 - 6'h1; // @[util.scala:203:14, :220:14]
wire [4:0] _next_ghist_new_history_ras_idx_T_6 = _next_ghist_new_history_ras_idx_T_5[4:0]; // @[util.scala:220:14]
wire [4:0] _next_ghist_new_history_ras_idx_T_7 = _next_ghist_new_history_ras_idx_T_6; // @[util.scala:220:{14,20}]
wire [4:0] _next_ghist_new_history_ras_idx_T_8 = _next_ghist_new_history_ras_idx_T_4 ? _next_ghist_new_history_ras_idx_T_7 : io_ifu_get_pc_1_ghist_ras_idx_0; // @[util.scala:220:20]
assign _next_ghist_new_history_ras_idx_T_9 = _next_ghist_new_history_ras_idx_T ? _next_ghist_new_history_ras_idx_T_3 : _next_ghist_new_history_ras_idx_T_8; // @[util.scala:203:20]
assign next_ghist_ras_idx = _next_ghist_new_history_ras_idx_T_9; // @[frontend.scala:87:27, :123:31]
wire [63:0] _io_ifu_redirect_ghist_T_old_history = use_same_ghist ? io_ifu_get_pc_1_ghist_old_history_0 : next_ghist_old_history; // @[frontend.scala:87:27]
wire _io_ifu_redirect_ghist_T_current_saw_branch_not_taken = use_same_ghist & io_ifu_get_pc_1_ghist_current_saw_branch_not_taken_0; // @[core.scala:51:7, :438:46, :455:35]
wire _io_ifu_redirect_ghist_T_new_saw_branch_not_taken = use_same_ghist ? io_ifu_get_pc_1_ghist_new_saw_branch_not_taken_0 : next_ghist_new_saw_branch_not_taken; // @[frontend.scala:87:27]
wire _io_ifu_redirect_ghist_T_new_saw_branch_taken = use_same_ghist ? io_ifu_get_pc_1_ghist_new_saw_branch_taken_0 : next_ghist_new_saw_branch_taken; // @[frontend.scala:87:27]
wire [4:0] _io_ifu_redirect_ghist_T_ras_idx = use_same_ghist ? io_ifu_get_pc_1_ghist_ras_idx_0 : next_ghist_ras_idx; // @[frontend.scala:87:27]
assign io_ifu_redirect_ghist_old_history_0 = REG ? 64'h0 : _io_ifu_redirect_ghist_T_old_history; // @[core.scala:51:7, :401:{16,38}, :409:27, :424:72, :455:35]
assign io_ifu_redirect_ghist_new_saw_branch_not_taken_0 = ~REG & _io_ifu_redirect_ghist_T_new_saw_branch_not_taken; // @[core.scala:51:7, :401:{16,38}, :409:27, :424:72, :455:35]
assign io_ifu_redirect_ghist_new_saw_branch_taken_0 = ~REG & _io_ifu_redirect_ghist_T_new_saw_branch_taken; // @[core.scala:51:7, :401:{16,38}, :409:27, :424:72, :455:35]
assign io_ifu_redirect_ghist_ras_idx_0 = REG ? new_ghist_ras_idx : _io_ifu_redirect_ghist_T_ras_idx; // @[core.scala:51:7, :401:{16,38}, :406:29, :409:27, :424:72, :455:35]
assign io_ifu_redirect_ghist_current_saw_branch_not_taken_0 = REG | use_same_ghist; // @[core.scala:51:7, :401:{16,38}, :409:27, :424:72, :438:46]
assign io_ifu_redirect_flush_0 = REG | _T_18 | (|{_rob_io_flush_frontend, brupdate_b1_mispredict_mask}); // @[core.scala:51:7, :143:32, :188:23, :224:42, :401:{16,38}, :403:27, :424:{39,72}, :435:29, :460:{38,78}]
wire [1:0] _youngest_com_idx_T = _rob_io_commit_valids_1 ? 2'h1 : 2'h2; // @[Mux.scala:50:70]
wire [1:0] _youngest_com_idx_T_1 = _rob_io_commit_valids_2 ? 2'h0 : _youngest_com_idx_T; // @[Mux.scala:50:70]
wire [2:0] _youngest_com_idx_T_2 = 3'h2 - {1'h0, _youngest_com_idx_T_1}; // @[Mux.scala:50:70]
wire [1:0] youngest_com_idx = _youngest_com_idx_T_2[1:0]; // @[core.scala:465:42]
wire _io_ifu_commit_valid_T = _rob_io_commit_valids_0 | _rob_io_commit_valids_1; // @[core.scala:143:32, :466:55]
wire _io_ifu_commit_valid_T_1 = _io_ifu_commit_valid_T | _rob_io_commit_valids_2; // @[core.scala:143:32, :466:55]
wire _io_ifu_commit_valid_T_2 = _io_ifu_commit_valid_T_1 | _rob_io_com_xcpt_valid; // @[core.scala:143:32, :466:{55,59}]
wire [3:0][4:0] _GEN_19 = {{_rob_io_commit_uops_0_ftq_idx}, {_rob_io_commit_uops_2_ftq_idx}, {_rob_io_commit_uops_1_ftq_idx}, {_rob_io_commit_uops_0_ftq_idx}}; // @[core.scala:143:32, :467:29]
wire [4:0] _io_ifu_commit_bits_T = _rob_io_com_xcpt_valid ? _rob_io_com_xcpt_bits_ftq_idx : _GEN_19[youngest_com_idx]; // @[core.scala:143:32, :465:42, :467:29]
reg REG_2; // @[core.scala:475:18]
reg io_ifu_sfence_REG_valid; // @[core.scala:476:31]
assign io_ifu_sfence_valid_0 = io_ifu_sfence_REG_valid; // @[core.scala:51:7, :476:31]
reg io_ifu_sfence_REG_bits_rs1; // @[core.scala:476:31]
assign io_ifu_sfence_bits_rs1_0 = io_ifu_sfence_REG_bits_rs1; // @[core.scala:51:7, :476:31]
reg io_ifu_sfence_REG_bits_rs2; // @[core.scala:476:31]
assign io_ifu_sfence_bits_rs2_0 = io_ifu_sfence_REG_bits_rs2; // @[core.scala:51:7, :476:31]
reg [38:0] io_ifu_sfence_REG_bits_addr; // @[core.scala:476:31]
assign io_ifu_sfence_bits_addr_0 = io_ifu_sfence_REG_bits_addr; // @[core.scala:51:7, :476:31]
reg io_ifu_sfence_REG_bits_asid; // @[core.scala:476:31]
assign io_ifu_sfence_bits_asid_0 = io_ifu_sfence_REG_bits_asid; // @[core.scala:51:7, :476:31]
reg [2:0] dec_finished_mask; // @[core.scala:496:34]
wire _dec_valids_0_T = io_ifu_fetchpacket_valid_0 & io_ifu_fetchpacket_bits_uops_0_valid_0; // @[core.scala:51:7, :508:68]
wire _dec_valids_0_T_1 = dec_finished_mask[0]; // @[core.scala:496:34, :509:61]
wire _dec_brmask_logic_io_is_branch_0_T = dec_finished_mask[0]; // @[core.scala:496:34, :509:61, :600:59]
wire _dec_valids_0_T_2 = ~_dec_valids_0_T_1; // @[core.scala:509:{43,61}]
assign _dec_valids_0_T_3 = _dec_valids_0_T & _dec_valids_0_T_2; // @[core.scala:508:{68,97}, :509:43]
assign dec_valids_0 = _dec_valids_0_T_3; // @[core.scala:157:24, :508:97]
wire _dec_valids_1_T = io_ifu_fetchpacket_valid_0 & io_ifu_fetchpacket_bits_uops_1_valid_0; // @[core.scala:51:7, :508:68]
wire _dec_valids_1_T_1 = dec_finished_mask[1]; // @[core.scala:496:34, :509:61]
wire _dec_brmask_logic_io_is_branch_1_T = dec_finished_mask[1]; // @[core.scala:496:34, :509:61, :600:59]
wire _dec_valids_1_T_2 = ~_dec_valids_1_T_1; // @[core.scala:509:{43,61}]
assign _dec_valids_1_T_3 = _dec_valids_1_T & _dec_valids_1_T_2; // @[core.scala:508:{68,97}, :509:43]
assign dec_valids_1 = _dec_valids_1_T_3; // @[core.scala:157:24, :508:97]
wire _dec_valids_2_T = io_ifu_fetchpacket_valid_0 & io_ifu_fetchpacket_bits_uops_2_valid_0; // @[core.scala:51:7, :508:68]
wire _dec_valids_2_T_1 = dec_finished_mask[2]; // @[core.scala:496:34, :509:61]
wire _dec_brmask_logic_io_is_branch_2_T = dec_finished_mask[2]; // @[core.scala:496:34, :509:61, :600:59]
wire _dec_valids_2_T_2 = ~_dec_valids_2_T_1; // @[core.scala:509:{43,61}]
assign _dec_valids_2_T_3 = _dec_valids_2_T & _dec_valids_2_T_2; // @[core.scala:508:{68,97}, :509:43]
assign dec_valids_2 = _dec_valids_2_T_3; // @[core.scala:157:24, :508:97]
wire jmp_pc_req_ready; // @[core.scala:522:25]
wire jmp_pc_req_valid; // @[core.scala:522:25]
wire [4:0] jmp_pc_req_bits; // @[core.scala:522:25]
wire _xcpt_pc_req_valid_T_1; // @[core.scala:551:45]
wire xcpt_pc_req_ready; // @[core.scala:523:25]
wire xcpt_pc_req_valid; // @[core.scala:523:25]
wire [4:0] xcpt_pc_req_bits; // @[core.scala:523:25]
wire flush_pc_req_valid; // @[core.scala:524:26]
wire [4:0] flush_pc_req_bits; // @[core.scala:524:26]
wire _jmp_pc_req_valid_T = iss_uops_1_fu_code == 10'h2; // @[core.scala:173:24, :539:90]
wire _jmp_pc_req_valid_T_1 = iss_valids_1 & _jmp_pc_req_valid_T; // @[core.scala:172:24, :539:{56,90}]
reg jmp_pc_req_valid_REG; // @[core.scala:539:30]
assign jmp_pc_req_valid = jmp_pc_req_valid_REG; // @[core.scala:522:25, :539:30]
reg [4:0] jmp_pc_req_bits_REG; // @[core.scala:540:30]
assign jmp_pc_req_bits = jmp_pc_req_bits_REG; // @[core.scala:522:25, :540:30]
wire [1:0] _xcpt_idx_T = dec_xcpts_1 ? 2'h1 : 2'h2; // @[Mux.scala:50:70]
wire [1:0] xcpt_idx = dec_xcpts_0 ? 2'h0 : _xcpt_idx_T; // @[Mux.scala:50:70]
wire _GEN_20 = dec_xcpts_0 | dec_xcpts_1; // @[core.scala:162:24, :551:45]
wire _xcpt_pc_req_valid_T; // @[core.scala:551:45]
assign _xcpt_pc_req_valid_T = _GEN_20; // @[core.scala:551:45]
wire _dec_xcpt_stall_T; // @[core.scala:567:42]
assign _dec_xcpt_stall_T = _GEN_20; // @[core.scala:551:45, :567:42]
assign _xcpt_pc_req_valid_T_1 = _xcpt_pc_req_valid_T | dec_xcpts_2; // @[core.scala:162:24, :551:45]
assign xcpt_pc_req_valid = _xcpt_pc_req_valid_T_1; // @[core.scala:523:25, :551:45]
wire [3:0][4:0] _GEN_21 = {{dec_uops_0_ftq_idx}, {dec_uops_2_ftq_idx}, {dec_uops_1_ftq_idx}, {dec_uops_0_ftq_idx}}; // @[core.scala:158:24, :552:24]
assign xcpt_pc_req_bits = _GEN_21[xcpt_idx]; // @[Mux.scala:50:70]
assign dec_xcpts_0 = dec_uops_0_exception & dec_valids_0; // @[core.scala:157:24, :158:24, :162:24, :566:71]
assign dec_xcpts_1 = dec_uops_1_exception & dec_valids_1; // @[core.scala:157:24, :158:24, :162:24, :566:71]
assign dec_xcpts_2 = dec_uops_2_exception & dec_valids_2; // @[core.scala:157:24, :158:24, :162:24, :566:71]
wire _dec_xcpt_stall_T_1 = _dec_xcpt_stall_T | dec_xcpts_2; // @[core.scala:162:24, :567:42]
wire _dec_xcpt_stall_T_2 = ~xcpt_pc_req_ready; // @[core.scala:523:25, :567:50]
wire dec_xcpt_stall = _dec_xcpt_stall_T_1 & _dec_xcpt_stall_T_2; // @[core.scala:567:{42,47,50}]
wire branch_mask_full_0; // @[core.scala:569:30]
wire branch_mask_full_1; // @[core.scala:569:30]
wire branch_mask_full_2; // @[core.scala:569:30]
wire _dec_hazards_T = ~dis_ready; // @[core.scala:169:24, :573:26]
wire _dec_hazards_T_1 = _dec_hazards_T | _rob_io_commit_rollback; // @[core.scala:143:32, :573:26, :574:23]
wire _dec_hazards_T_2 = _dec_hazards_T_1 | dec_xcpt_stall; // @[core.scala:567:47, :574:23, :575:23]
wire _dec_hazards_T_3 = _dec_hazards_T_2 | branch_mask_full_0; // @[core.scala:569:30, :575:23, :576:23]
wire _dec_hazards_T_4 = |brupdate_b1_mispredict_mask; // @[core.scala:188:23, :224:42, :577:54]
wire _dec_hazards_T_5 = _dec_hazards_T_3 | _dec_hazards_T_4; // @[core.scala:576:23, :577:{23,54}]
wire _dec_hazards_T_6 = _dec_hazards_T_5 | brupdate_b2_mispredict; // @[core.scala:188:23, :577:23, :578:23]
wire _dec_hazards_T_7 = _dec_hazards_T_6 | io_ifu_redirect_flush_0; // @[core.scala:51:7, :578:23, :579:23]
wire dec_hazards_0 = dec_valids_0 & _dec_hazards_T_7; // @[core.scala:157:24, :572:37, :579:23]
wire dec_stalls_0 = dec_hazards_0; // @[core.scala:572:37, :581:62]
wire _dec_hazards_T_8 = ~dis_ready; // @[core.scala:169:24, :573:26]
wire _dec_hazards_T_9 = _dec_hazards_T_8 | _rob_io_commit_rollback; // @[core.scala:143:32, :573:26, :574:23]
wire _dec_hazards_T_10 = _dec_hazards_T_9 | dec_xcpt_stall; // @[core.scala:567:47, :574:23, :575:23]
wire _dec_hazards_T_11 = _dec_hazards_T_10 | branch_mask_full_1; // @[core.scala:569:30, :575:23, :576:23]
wire _dec_hazards_T_12 = |brupdate_b1_mispredict_mask; // @[core.scala:188:23, :224:42, :577:54]
wire _dec_hazards_T_13 = _dec_hazards_T_11 | _dec_hazards_T_12; // @[core.scala:576:23, :577:{23,54}]
wire _dec_hazards_T_14 = _dec_hazards_T_13 | brupdate_b2_mispredict; // @[core.scala:188:23, :577:23, :578:23]
wire _dec_hazards_T_15 = _dec_hazards_T_14 | io_ifu_redirect_flush_0; // @[core.scala:51:7, :578:23, :579:23]
wire dec_hazards_1 = dec_valids_1 & _dec_hazards_T_15; // @[core.scala:157:24, :572:37, :579:23]
wire _dec_hazards_T_16 = ~dis_ready; // @[core.scala:169:24, :573:26]
wire _dec_hazards_T_17 = _dec_hazards_T_16 | _rob_io_commit_rollback; // @[core.scala:143:32, :573:26, :574:23]
wire _dec_hazards_T_18 = _dec_hazards_T_17 | dec_xcpt_stall; // @[core.scala:567:47, :574:23, :575:23]
wire _dec_hazards_T_19 = _dec_hazards_T_18 | branch_mask_full_2; // @[core.scala:569:30, :575:23, :576:23]
wire _dec_hazards_T_20 = |brupdate_b1_mispredict_mask; // @[core.scala:188:23, :224:42, :577:54]
wire _dec_hazards_T_21 = _dec_hazards_T_19 | _dec_hazards_T_20; // @[core.scala:576:23, :577:{23,54}]
wire _dec_hazards_T_22 = _dec_hazards_T_21 | brupdate_b2_mispredict; // @[core.scala:188:23, :577:23, :578:23]
wire _dec_hazards_T_23 = _dec_hazards_T_22 | io_ifu_redirect_flush_0; // @[core.scala:51:7, :578:23, :579:23]
wire dec_hazards_2 = dec_valids_2 & _dec_hazards_T_23; // @[core.scala:157:24, :572:37, :579:23]
wire dec_stalls_1 = dec_stalls_0 | dec_hazards_1; // @[core.scala:572:37, :581:62]
wire dec_stalls_2 = dec_stalls_1 | dec_hazards_2; // @[core.scala:572:37, :581:62]
assign dec_fire_0 = dec_valids_0 & ~dec_stalls_0; // @[core.scala:157:24, :159:24, :581:62, :582:{58,61}]
assign dec_fire_1 = dec_valids_1 & ~dec_stalls_1; // @[core.scala:157:24, :159:24, :581:62, :582:{58,61}]
assign dec_fire_2 = dec_valids_2 & ~dec_stalls_2; // @[core.scala:157:24, :159:24, :581:62, :582:{58,61}]
wire [1:0] dec_finished_mask_hi = {dec_fire_2, dec_fire_1}; // @[core.scala:159:24, :590:35]
wire [2:0] _dec_finished_mask_T = {dec_finished_mask_hi, dec_fire_0}; // @[core.scala:159:24, :590:35]
wire [2:0] _dec_finished_mask_T_1 = _dec_finished_mask_T | dec_finished_mask; // @[core.scala:496:34, :590:{35,42}]
reg dec_brmask_logic_io_flush_pipeline_REG; // @[core.scala:597:48]
wire _dec_brmask_logic_io_is_branch_0_T_1 = ~_dec_brmask_logic_io_is_branch_0_T; // @[core.scala:600:{41,59}]
wire _dec_brmask_logic_io_is_branch_0_T_2 = ~dec_uops_0_is_sfb; // @[core.scala:158:24]
wire _dec_brmask_logic_io_is_branch_0_T_3 = dec_uops_0_is_br & _dec_brmask_logic_io_is_branch_0_T_2; // @[core.scala:158:24]
wire _dec_brmask_logic_io_is_branch_0_T_4 = _dec_brmask_logic_io_is_branch_0_T_3 | dec_uops_0_is_jalr; // @[core.scala:158:24]
wire _dec_brmask_logic_io_is_branch_0_T_5 = _dec_brmask_logic_io_is_branch_0_T_1 & _dec_brmask_logic_io_is_branch_0_T_4; // @[core.scala:600:{41,63}]
wire _dec_brmask_logic_io_will_fire_0_T = ~dec_uops_0_is_sfb; // @[core.scala:158:24]
wire _dec_brmask_logic_io_will_fire_0_T_1 = dec_uops_0_is_br & _dec_brmask_logic_io_will_fire_0_T; // @[core.scala:158:24]
wire _dec_brmask_logic_io_will_fire_0_T_2 = _dec_brmask_logic_io_will_fire_0_T_1 | dec_uops_0_is_jalr; // @[core.scala:158:24]
wire _dec_brmask_logic_io_will_fire_0_T_3 = dec_fire_0 & _dec_brmask_logic_io_will_fire_0_T_2; // @[core.scala:159:24, :601:54]
wire _dec_brmask_logic_io_is_branch_1_T_1 = ~_dec_brmask_logic_io_is_branch_1_T; // @[core.scala:600:{41,59}]
wire _dec_brmask_logic_io_is_branch_1_T_2 = ~dec_uops_1_is_sfb; // @[core.scala:158:24]
wire _dec_brmask_logic_io_is_branch_1_T_3 = dec_uops_1_is_br & _dec_brmask_logic_io_is_branch_1_T_2; // @[core.scala:158:24]
wire _dec_brmask_logic_io_is_branch_1_T_4 = _dec_brmask_logic_io_is_branch_1_T_3 | dec_uops_1_is_jalr; // @[core.scala:158:24]
wire _dec_brmask_logic_io_is_branch_1_T_5 = _dec_brmask_logic_io_is_branch_1_T_1 & _dec_brmask_logic_io_is_branch_1_T_4; // @[core.scala:600:{41,63}]
wire _dec_brmask_logic_io_will_fire_1_T = ~dec_uops_1_is_sfb; // @[core.scala:158:24]
wire _dec_brmask_logic_io_will_fire_1_T_1 = dec_uops_1_is_br & _dec_brmask_logic_io_will_fire_1_T; // @[core.scala:158:24]
wire _dec_brmask_logic_io_will_fire_1_T_2 = _dec_brmask_logic_io_will_fire_1_T_1 | dec_uops_1_is_jalr; // @[core.scala:158:24]
wire _dec_brmask_logic_io_will_fire_1_T_3 = dec_fire_1 & _dec_brmask_logic_io_will_fire_1_T_2; // @[core.scala:159:24, :601:54]
wire _dec_brmask_logic_io_is_branch_2_T_1 = ~_dec_brmask_logic_io_is_branch_2_T; // @[core.scala:600:{41,59}]
wire _dec_brmask_logic_io_is_branch_2_T_2 = ~dec_uops_2_is_sfb; // @[core.scala:158:24]
wire _dec_brmask_logic_io_is_branch_2_T_3 = dec_uops_2_is_br & _dec_brmask_logic_io_is_branch_2_T_2; // @[core.scala:158:24]
wire _dec_brmask_logic_io_is_branch_2_T_4 = _dec_brmask_logic_io_is_branch_2_T_3 | dec_uops_2_is_jalr; // @[core.scala:158:24]
wire _dec_brmask_logic_io_is_branch_2_T_5 = _dec_brmask_logic_io_is_branch_2_T_1 & _dec_brmask_logic_io_is_branch_2_T_4; // @[core.scala:600:{41,63}]
wire _dec_brmask_logic_io_will_fire_2_T = ~dec_uops_2_is_sfb; // @[core.scala:158:24]
wire _dec_brmask_logic_io_will_fire_2_T_1 = dec_uops_2_is_br & _dec_brmask_logic_io_will_fire_2_T; // @[core.scala:158:24]
wire _dec_brmask_logic_io_will_fire_2_T_2 = _dec_brmask_logic_io_will_fire_2_T_1 | dec_uops_2_is_jalr; // @[core.scala:158:24]
wire _dec_brmask_logic_io_will_fire_2_T_3 = dec_fire_2 & _dec_brmask_logic_io_will_fire_2_T_2; // @[core.scala:159:24, :601:54]
wire _GEN_22 = dis_uops_0_lrs1_rtype == 2'h1; // @[core.scala:167:24, :654:52]
wire _dis_uops_0_prs1_T; // @[core.scala:654:52]
assign _dis_uops_0_prs1_T = _GEN_22; // @[core.scala:654:52]
wire _dis_uops_0_prs1_busy_T_2; // @[core.scala:665:73]
assign _dis_uops_0_prs1_busy_T_2 = _GEN_22; // @[core.scala:654:52, :665:73]
wire _GEN_23 = dis_uops_0_lrs1_rtype == 2'h0; // @[core.scala:167:24, :655:52]
wire _dis_uops_0_prs1_T_1; // @[core.scala:655:52]
assign _dis_uops_0_prs1_T_1 = _GEN_23; // @[core.scala:655:52]
wire _dis_uops_0_prs1_busy_T; // @[core.scala:664:73]
assign _dis_uops_0_prs1_busy_T = _GEN_23; // @[core.scala:655:52, :664:73]
wire [6:0] _dis_uops_0_prs1_T_2 = _dis_uops_0_prs1_T_1 ? _rename_stage_io_ren2_uops_0_prs1 : {1'h0, dis_uops_0_lrs1}; // @[core.scala:103:32, :167:24, :655:{28,52}]
assign _dis_uops_0_prs1_T_3 = _dis_uops_0_prs1_T ? _fp_rename_stage_io_ren2_uops_0_prs1 : _dis_uops_0_prs1_T_2; // @[core.scala:104:46, :654:{28,52}, :655:28]
assign dis_uops_0_prs1 = _dis_uops_0_prs1_T_3; // @[core.scala:167:24, :654:28]
wire _GEN_24 = dis_uops_0_lrs2_rtype == 2'h1; // @[core.scala:167:24, :656:52]
wire _dis_uops_0_prs2_T; // @[core.scala:656:52]
assign _dis_uops_0_prs2_T = _GEN_24; // @[core.scala:656:52]
wire _dis_uops_0_prs2_busy_T_2; // @[core.scala:667:73]
assign _dis_uops_0_prs2_busy_T_2 = _GEN_24; // @[core.scala:656:52, :667:73]
assign _dis_uops_0_prs2_T_1 = _dis_uops_0_prs2_T ? _fp_rename_stage_io_ren2_uops_0_prs2 : _rename_stage_io_ren2_uops_0_prs2; // @[core.scala:103:32, :104:46, :656:{28,52}]
assign dis_uops_0_prs2 = _dis_uops_0_prs2_T_1; // @[core.scala:167:24, :656:28]
wire _GEN_25 = dis_uops_0_dst_rtype == 2'h1; // @[core.scala:167:24, :659:52]
wire _dis_uops_0_pdst_T; // @[core.scala:659:52]
assign _dis_uops_0_pdst_T = _GEN_25; // @[core.scala:659:52]
wire _dis_uops_0_stale_pdst_T; // @[core.scala:662:57]
assign _dis_uops_0_stale_pdst_T = _GEN_25; // @[core.scala:659:52, :662:57]
wire _dis_uops_0_pdst_T_1 = dis_uops_0_dst_rtype == 2'h0; // @[core.scala:167:24, :660:52]
wire [6:0] _dis_uops_0_pdst_T_2 = _dis_uops_0_pdst_T_1 ? _rename_stage_io_ren2_uops_0_pdst : 7'h0; // @[core.scala:103:32, :660:{28,52}]
assign _dis_uops_0_pdst_T_3 = _dis_uops_0_pdst_T ? _fp_rename_stage_io_ren2_uops_0_pdst : _dis_uops_0_pdst_T_2; // @[core.scala:104:46, :659:{28,52}, :660:28]
assign dis_uops_0_pdst = _dis_uops_0_pdst_T_3; // @[core.scala:167:24, :659:28]
assign _dis_uops_0_stale_pdst_T_1 = _dis_uops_0_stale_pdst_T ? _fp_rename_stage_io_ren2_uops_0_stale_pdst : _rename_stage_io_ren2_uops_0_stale_pdst; // @[core.scala:103:32, :104:46, :662:{34,57}]
assign dis_uops_0_stale_pdst = _dis_uops_0_stale_pdst_T_1; // @[core.scala:167:24, :662:34]
wire _dis_uops_0_prs1_busy_T_1 = _rename_stage_io_ren2_uops_0_prs1_busy & _dis_uops_0_prs1_busy_T; // @[core.scala:103:32, :664:{46,73}]
wire _dis_uops_0_prs1_busy_T_3 = _fp_rename_stage_io_ren2_uops_0_prs1_busy & _dis_uops_0_prs1_busy_T_2; // @[core.scala:104:46, :665:{46,73}]
assign _dis_uops_0_prs1_busy_T_4 = _dis_uops_0_prs1_busy_T_1 | _dis_uops_0_prs1_busy_T_3; // @[core.scala:664:{46,85}, :665:46]
assign dis_uops_0_prs1_busy = _dis_uops_0_prs1_busy_T_4; // @[core.scala:167:24, :664:85]
wire _dis_uops_0_prs2_busy_T = dis_uops_0_lrs2_rtype == 2'h0; // @[core.scala:167:24, :666:73]
wire _dis_uops_0_prs2_busy_T_1 = _rename_stage_io_ren2_uops_0_prs2_busy & _dis_uops_0_prs2_busy_T; // @[core.scala:103:32, :666:{46,73}]
wire _dis_uops_0_prs2_busy_T_3 = _fp_rename_stage_io_ren2_uops_0_prs2_busy & _dis_uops_0_prs2_busy_T_2; // @[core.scala:104:46, :667:{46,73}]
assign _dis_uops_0_prs2_busy_T_4 = _dis_uops_0_prs2_busy_T_1 | _dis_uops_0_prs2_busy_T_3; // @[core.scala:666:{46,85}, :667:46]
assign dis_uops_0_prs2_busy = _dis_uops_0_prs2_busy_T_4; // @[core.scala:167:24, :666:85]
assign _dis_uops_0_prs3_busy_T = _fp_rename_stage_io_ren2_uops_0_prs3_busy & dis_uops_0_frs3_en; // @[core.scala:104:46, :167:24, :668:46]
assign dis_uops_0_prs3_busy = _dis_uops_0_prs3_busy_T; // @[core.scala:167:24, :668:46]
wire _dis_uops_0_ppred_busy_T = ~dis_uops_0_is_br; // @[core.scala:167:24]
wire _dis_uops_0_ppred_busy_T_1 = _dis_uops_0_ppred_busy_T & dis_uops_0_is_sfb; // @[core.scala:167:24]
wire _ren_stalls_0_T = _rename_stage_io_ren_stalls_0 | _fp_rename_stage_io_ren_stalls_0; // @[core.scala:103:32, :104:46, :671:52]
assign _ren_stalls_0_T_1 = _ren_stalls_0_T; // @[core.scala:671:{52,63}]
assign ren_stalls_0 = _ren_stalls_0_T_1; // @[core.scala:163:24, :671:63]
wire _GEN_26 = dis_uops_1_lrs1_rtype == 2'h1; // @[core.scala:167:24, :654:52]
wire _dis_uops_1_prs1_T; // @[core.scala:654:52]
assign _dis_uops_1_prs1_T = _GEN_26; // @[core.scala:654:52]
wire _dis_uops_1_prs1_busy_T_2; // @[core.scala:665:73]
assign _dis_uops_1_prs1_busy_T_2 = _GEN_26; // @[core.scala:654:52, :665:73]
wire _GEN_27 = dis_uops_1_lrs1_rtype == 2'h0; // @[core.scala:167:24, :655:52]
wire _dis_uops_1_prs1_T_1; // @[core.scala:655:52]
assign _dis_uops_1_prs1_T_1 = _GEN_27; // @[core.scala:655:52]
wire _dis_uops_1_prs1_busy_T; // @[core.scala:664:73]
assign _dis_uops_1_prs1_busy_T = _GEN_27; // @[core.scala:655:52, :664:73]
wire [6:0] _dis_uops_1_prs1_T_2 = _dis_uops_1_prs1_T_1 ? _rename_stage_io_ren2_uops_1_prs1 : {1'h0, dis_uops_1_lrs1}; // @[core.scala:103:32, :167:24, :655:{28,52}]
assign _dis_uops_1_prs1_T_3 = _dis_uops_1_prs1_T ? _fp_rename_stage_io_ren2_uops_1_prs1 : _dis_uops_1_prs1_T_2; // @[core.scala:104:46, :654:{28,52}, :655:28]
assign dis_uops_1_prs1 = _dis_uops_1_prs1_T_3; // @[core.scala:167:24, :654:28]
wire _GEN_28 = dis_uops_1_lrs2_rtype == 2'h1; // @[core.scala:167:24, :656:52]
wire _dis_uops_1_prs2_T; // @[core.scala:656:52]
assign _dis_uops_1_prs2_T = _GEN_28; // @[core.scala:656:52]
wire _dis_uops_1_prs2_busy_T_2; // @[core.scala:667:73]
assign _dis_uops_1_prs2_busy_T_2 = _GEN_28; // @[core.scala:656:52, :667:73]
assign _dis_uops_1_prs2_T_1 = _dis_uops_1_prs2_T ? _fp_rename_stage_io_ren2_uops_1_prs2 : _rename_stage_io_ren2_uops_1_prs2; // @[core.scala:103:32, :104:46, :656:{28,52}]
assign dis_uops_1_prs2 = _dis_uops_1_prs2_T_1; // @[core.scala:167:24, :656:28]
wire _GEN_29 = dis_uops_1_dst_rtype == 2'h1; // @[core.scala:167:24, :659:52]
wire _dis_uops_1_pdst_T; // @[core.scala:659:52]
assign _dis_uops_1_pdst_T = _GEN_29; // @[core.scala:659:52]
wire _dis_uops_1_stale_pdst_T; // @[core.scala:662:57]
assign _dis_uops_1_stale_pdst_T = _GEN_29; // @[core.scala:659:52, :662:57]
wire _dis_uops_1_pdst_T_1 = dis_uops_1_dst_rtype == 2'h0; // @[core.scala:167:24, :660:52]
wire [6:0] _dis_uops_1_pdst_T_2 = _dis_uops_1_pdst_T_1 ? _rename_stage_io_ren2_uops_1_pdst : 7'h0; // @[core.scala:103:32, :660:{28,52}]
assign _dis_uops_1_pdst_T_3 = _dis_uops_1_pdst_T ? _fp_rename_stage_io_ren2_uops_1_pdst : _dis_uops_1_pdst_T_2; // @[core.scala:104:46, :659:{28,52}, :660:28]
assign dis_uops_1_pdst = _dis_uops_1_pdst_T_3; // @[core.scala:167:24, :659:28]
assign _dis_uops_1_stale_pdst_T_1 = _dis_uops_1_stale_pdst_T ? _fp_rename_stage_io_ren2_uops_1_stale_pdst : _rename_stage_io_ren2_uops_1_stale_pdst; // @[core.scala:103:32, :104:46, :662:{34,57}]
assign dis_uops_1_stale_pdst = _dis_uops_1_stale_pdst_T_1; // @[core.scala:167:24, :662:34]
wire _dis_uops_1_prs1_busy_T_1 = _rename_stage_io_ren2_uops_1_prs1_busy & _dis_uops_1_prs1_busy_T; // @[core.scala:103:32, :664:{46,73}]
wire _dis_uops_1_prs1_busy_T_3 = _fp_rename_stage_io_ren2_uops_1_prs1_busy & _dis_uops_1_prs1_busy_T_2; // @[core.scala:104:46, :665:{46,73}]
assign _dis_uops_1_prs1_busy_T_4 = _dis_uops_1_prs1_busy_T_1 | _dis_uops_1_prs1_busy_T_3; // @[core.scala:664:{46,85}, :665:46]
assign dis_uops_1_prs1_busy = _dis_uops_1_prs1_busy_T_4; // @[core.scala:167:24, :664:85]
wire _dis_uops_1_prs2_busy_T = dis_uops_1_lrs2_rtype == 2'h0; // @[core.scala:167:24, :666:73]
wire _dis_uops_1_prs2_busy_T_1 = _rename_stage_io_ren2_uops_1_prs2_busy & _dis_uops_1_prs2_busy_T; // @[core.scala:103:32, :666:{46,73}]
wire _dis_uops_1_prs2_busy_T_3 = _fp_rename_stage_io_ren2_uops_1_prs2_busy & _dis_uops_1_prs2_busy_T_2; // @[core.scala:104:46, :667:{46,73}]
assign _dis_uops_1_prs2_busy_T_4 = _dis_uops_1_prs2_busy_T_1 | _dis_uops_1_prs2_busy_T_3; // @[core.scala:666:{46,85}, :667:46]
assign dis_uops_1_prs2_busy = _dis_uops_1_prs2_busy_T_4; // @[core.scala:167:24, :666:85]
assign _dis_uops_1_prs3_busy_T = _fp_rename_stage_io_ren2_uops_1_prs3_busy & dis_uops_1_frs3_en; // @[core.scala:104:46, :167:24, :668:46]
assign dis_uops_1_prs3_busy = _dis_uops_1_prs3_busy_T; // @[core.scala:167:24, :668:46]
wire _dis_uops_1_ppred_busy_T = ~dis_uops_1_is_br; // @[core.scala:167:24]
wire _dis_uops_1_ppred_busy_T_1 = _dis_uops_1_ppred_busy_T & dis_uops_1_is_sfb; // @[core.scala:167:24]
wire _ren_stalls_1_T = _rename_stage_io_ren_stalls_1 | _fp_rename_stage_io_ren_stalls_1; // @[core.scala:103:32, :104:46, :671:52]
assign _ren_stalls_1_T_1 = _ren_stalls_1_T; // @[core.scala:671:{52,63}]
assign ren_stalls_1 = _ren_stalls_1_T_1; // @[core.scala:163:24, :671:63]
wire _GEN_30 = dis_uops_2_lrs1_rtype == 2'h1; // @[core.scala:167:24, :654:52]
wire _dis_uops_2_prs1_T; // @[core.scala:654:52]
assign _dis_uops_2_prs1_T = _GEN_30; // @[core.scala:654:52]
wire _dis_uops_2_prs1_busy_T_2; // @[core.scala:665:73]
assign _dis_uops_2_prs1_busy_T_2 = _GEN_30; // @[core.scala:654:52, :665:73]
wire _GEN_31 = dis_uops_2_lrs1_rtype == 2'h0; // @[core.scala:167:24, :655:52]
wire _dis_uops_2_prs1_T_1; // @[core.scala:655:52]
assign _dis_uops_2_prs1_T_1 = _GEN_31; // @[core.scala:655:52]
wire _dis_uops_2_prs1_busy_T; // @[core.scala:664:73]
assign _dis_uops_2_prs1_busy_T = _GEN_31; // @[core.scala:655:52, :664:73]
wire [6:0] _dis_uops_2_prs1_T_2 = _dis_uops_2_prs1_T_1 ? _rename_stage_io_ren2_uops_2_prs1 : {1'h0, dis_uops_2_lrs1}; // @[core.scala:103:32, :167:24, :655:{28,52}]
assign _dis_uops_2_prs1_T_3 = _dis_uops_2_prs1_T ? _fp_rename_stage_io_ren2_uops_2_prs1 : _dis_uops_2_prs1_T_2; // @[core.scala:104:46, :654:{28,52}, :655:28]
assign dis_uops_2_prs1 = _dis_uops_2_prs1_T_3; // @[core.scala:167:24, :654:28]
wire _GEN_32 = dis_uops_2_lrs2_rtype == 2'h1; // @[core.scala:167:24, :656:52]
wire _dis_uops_2_prs2_T; // @[core.scala:656:52]
assign _dis_uops_2_prs2_T = _GEN_32; // @[core.scala:656:52]
wire _dis_uops_2_prs2_busy_T_2; // @[core.scala:667:73]
assign _dis_uops_2_prs2_busy_T_2 = _GEN_32; // @[core.scala:656:52, :667:73]
assign _dis_uops_2_prs2_T_1 = _dis_uops_2_prs2_T ? _fp_rename_stage_io_ren2_uops_2_prs2 : _rename_stage_io_ren2_uops_2_prs2; // @[core.scala:103:32, :104:46, :656:{28,52}]
assign dis_uops_2_prs2 = _dis_uops_2_prs2_T_1; // @[core.scala:167:24, :656:28]
wire _GEN_33 = dis_uops_2_dst_rtype == 2'h1; // @[core.scala:167:24, :659:52]
wire _dis_uops_2_pdst_T; // @[core.scala:659:52]
assign _dis_uops_2_pdst_T = _GEN_33; // @[core.scala:659:52]
wire _dis_uops_2_stale_pdst_T; // @[core.scala:662:57]
assign _dis_uops_2_stale_pdst_T = _GEN_33; // @[core.scala:659:52, :662:57]
wire _dis_uops_2_pdst_T_1 = dis_uops_2_dst_rtype == 2'h0; // @[core.scala:167:24, :660:52]
wire [6:0] _dis_uops_2_pdst_T_2 = _dis_uops_2_pdst_T_1 ? _rename_stage_io_ren2_uops_2_pdst : 7'h0; // @[core.scala:103:32, :660:{28,52}]
assign _dis_uops_2_pdst_T_3 = _dis_uops_2_pdst_T ? _fp_rename_stage_io_ren2_uops_2_pdst : _dis_uops_2_pdst_T_2; // @[core.scala:104:46, :659:{28,52}, :660:28]
assign dis_uops_2_pdst = _dis_uops_2_pdst_T_3; // @[core.scala:167:24, :659:28]
assign _dis_uops_2_stale_pdst_T_1 = _dis_uops_2_stale_pdst_T ? _fp_rename_stage_io_ren2_uops_2_stale_pdst : _rename_stage_io_ren2_uops_2_stale_pdst; // @[core.scala:103:32, :104:46, :662:{34,57}]
assign dis_uops_2_stale_pdst = _dis_uops_2_stale_pdst_T_1; // @[core.scala:167:24, :662:34]
wire _dis_uops_2_prs1_busy_T_1 = _rename_stage_io_ren2_uops_2_prs1_busy & _dis_uops_2_prs1_busy_T; // @[core.scala:103:32, :664:{46,73}]
wire _dis_uops_2_prs1_busy_T_3 = _fp_rename_stage_io_ren2_uops_2_prs1_busy & _dis_uops_2_prs1_busy_T_2; // @[core.scala:104:46, :665:{46,73}]
assign _dis_uops_2_prs1_busy_T_4 = _dis_uops_2_prs1_busy_T_1 | _dis_uops_2_prs1_busy_T_3; // @[core.scala:664:{46,85}, :665:46]
assign dis_uops_2_prs1_busy = _dis_uops_2_prs1_busy_T_4; // @[core.scala:167:24, :664:85]
wire _dis_uops_2_prs2_busy_T = dis_uops_2_lrs2_rtype == 2'h0; // @[core.scala:167:24, :666:73]
wire _dis_uops_2_prs2_busy_T_1 = _rename_stage_io_ren2_uops_2_prs2_busy & _dis_uops_2_prs2_busy_T; // @[core.scala:103:32, :666:{46,73}]
wire _dis_uops_2_prs2_busy_T_3 = _fp_rename_stage_io_ren2_uops_2_prs2_busy & _dis_uops_2_prs2_busy_T_2; // @[core.scala:104:46, :667:{46,73}]
assign _dis_uops_2_prs2_busy_T_4 = _dis_uops_2_prs2_busy_T_1 | _dis_uops_2_prs2_busy_T_3; // @[core.scala:666:{46,85}, :667:46]
assign dis_uops_2_prs2_busy = _dis_uops_2_prs2_busy_T_4; // @[core.scala:167:24, :666:85]
assign _dis_uops_2_prs3_busy_T = _fp_rename_stage_io_ren2_uops_2_prs3_busy & dis_uops_2_frs3_en; // @[core.scala:104:46, :167:24, :668:46]
assign dis_uops_2_prs3_busy = _dis_uops_2_prs3_busy_T; // @[core.scala:167:24, :668:46]
wire _dis_uops_2_ppred_busy_T = ~dis_uops_2_is_br; // @[core.scala:167:24]
wire _dis_uops_2_ppred_busy_T_1 = _dis_uops_2_ppred_busy_T & dis_uops_2_is_sfb; // @[core.scala:167:24]
wire _ren_stalls_2_T = _rename_stage_io_ren_stalls_2 | _fp_rename_stage_io_ren_stalls_2; // @[core.scala:103:32, :104:46, :671:52]
assign _ren_stalls_2_T_1 = _ren_stalls_2_T; // @[core.scala:671:{52,63}]
assign ren_stalls_2 = _ren_stalls_2_T_1; // @[core.scala:163:24, :671:63]
wire dis_prior_slot_valid_2 = dis_prior_slot_valid_1 | dis_valids_1; // @[core.scala:166:24, :683:71]
wire dis_prior_slot_valid_3 = dis_prior_slot_valid_2 | dis_valids_2; // @[core.scala:166:24, :683:71]
wire _dis_prior_slot_unique_T = dis_valids_0 & dis_uops_0_is_unique; // @[core.scala:166:24, :167:24, :684:101]
wire dis_prior_slot_unique_1 = _dis_prior_slot_unique_T; // @[core.scala:684:{96,101}]
wire _dis_prior_slot_unique_T_1 = dis_valids_1 & dis_uops_1_is_unique; // @[core.scala:166:24, :167:24, :684:101]
wire dis_prior_slot_unique_2 = dis_prior_slot_unique_1 | _dis_prior_slot_unique_T_1; // @[core.scala:684:{96,101}]
wire _dis_prior_slot_unique_T_2 = dis_valids_2 & dis_uops_2_is_unique; // @[core.scala:166:24, :167:24, :684:101]
wire dis_prior_slot_unique_3 = dis_prior_slot_unique_2 | _dis_prior_slot_unique_T_2; // @[core.scala:684:{96,101}]
wire _wait_for_empty_pipeline_T = custom_csrs_csrs_0_value[3]; // @[core.scala:276:25]
wire _wait_for_empty_pipeline_T_6 = custom_csrs_csrs_0_value[3]; // @[core.scala:276:25]
wire _wait_for_empty_pipeline_T_12 = custom_csrs_csrs_0_value[3]; // @[core.scala:276:25]
wire _wait_for_empty_pipeline_T_1 = dis_uops_0_is_unique | _wait_for_empty_pipeline_T; // @[core.scala:167:24, :685:85]
wire _wait_for_empty_pipeline_T_2 = ~_rob_io_empty; // @[core.scala:143:32, :686:36]
wire _wait_for_empty_pipeline_T_3 = ~io_lsu_fencei_rdy_0; // @[core.scala:51:7, :686:53]
wire _wait_for_empty_pipeline_T_4 = _wait_for_empty_pipeline_T_2 | _wait_for_empty_pipeline_T_3; // @[core.scala:686:{36,50,53}]
wire _wait_for_empty_pipeline_T_5 = _wait_for_empty_pipeline_T_4; // @[core.scala:686:{50,72}]
wire wait_for_empty_pipeline_0 = _wait_for_empty_pipeline_T_1 & _wait_for_empty_pipeline_T_5; // @[core.scala:685:{85,112}, :686:72]
wire _wait_for_empty_pipeline_T_7 = dis_uops_1_is_unique | _wait_for_empty_pipeline_T_6; // @[core.scala:167:24, :685:85]
wire _wait_for_empty_pipeline_T_8 = ~_rob_io_empty; // @[core.scala:143:32, :686:36]
wire _wait_for_empty_pipeline_T_9 = ~io_lsu_fencei_rdy_0; // @[core.scala:51:7, :686:53]
wire _wait_for_empty_pipeline_T_10 = _wait_for_empty_pipeline_T_8 | _wait_for_empty_pipeline_T_9; // @[core.scala:686:{36,50,53}]
wire _wait_for_empty_pipeline_T_11 = _wait_for_empty_pipeline_T_10 | dis_prior_slot_valid_1; // @[core.scala:683:71, :686:{50,72}]
wire wait_for_empty_pipeline_1 = _wait_for_empty_pipeline_T_7 & _wait_for_empty_pipeline_T_11; // @[core.scala:685:{85,112}, :686:72]
wire _wait_for_empty_pipeline_T_13 = dis_uops_2_is_unique | _wait_for_empty_pipeline_T_12; // @[core.scala:167:24, :685:85]
wire _wait_for_empty_pipeline_T_14 = ~_rob_io_empty; // @[core.scala:143:32, :686:36]
wire _wait_for_empty_pipeline_T_15 = ~io_lsu_fencei_rdy_0; // @[core.scala:51:7, :686:53]
wire _wait_for_empty_pipeline_T_16 = _wait_for_empty_pipeline_T_14 | _wait_for_empty_pipeline_T_15; // @[core.scala:686:{36,50,53}]
wire _wait_for_empty_pipeline_T_17 = _wait_for_empty_pipeline_T_16 | dis_prior_slot_valid_2; // @[core.scala:683:71, :686:{50,72}]
wire wait_for_empty_pipeline_2 = _wait_for_empty_pipeline_T_13 & _wait_for_empty_pipeline_T_17; // @[core.scala:685:{85,112}, :686:72]
wire _wait_for_rocc_T = dis_uops_0_is_fence | dis_uops_0_is_fencei; // @[core.scala:167:24, :689:47]
wire _wait_for_rocc_T_2 = dis_uops_1_is_fence | dis_uops_1_is_fencei; // @[core.scala:167:24, :689:47]
wire _wait_for_rocc_T_4 = dis_uops_2_is_fence | dis_uops_2_is_fencei; // @[core.scala:167:24, :689:47]
wire _GEN_34 = dis_uops_0_uopc == 7'h6C; // @[core.scala:167:24, :691:76]
wire _block_rocc_T; // @[core.scala:691:76]
assign _block_rocc_T = _GEN_34; // @[core.scala:691:76]
wire _dis_rocc_alloc_stall_T; // @[core.scala:692:51]
assign _dis_rocc_alloc_stall_T = _GEN_34; // @[core.scala:691:76, :692:51]
wire _block_rocc_T_1 = dis_valids_0 & _block_rocc_T; // @[core.scala:166:24, :691:{66,76}]
wire block_rocc_1 = _block_rocc_T_1; // @[core.scala:691:{66,109}]
wire _GEN_35 = dis_uops_1_uopc == 7'h6C; // @[core.scala:167:24, :691:76]
wire _block_rocc_T_2; // @[core.scala:691:76]
assign _block_rocc_T_2 = _GEN_35; // @[core.scala:691:76]
wire _dis_rocc_alloc_stall_T_1; // @[core.scala:692:51]
assign _dis_rocc_alloc_stall_T_1 = _GEN_35; // @[core.scala:691:76, :692:51]
wire _block_rocc_T_3 = dis_valids_1 & _block_rocc_T_2; // @[core.scala:166:24, :691:{66,76}]
wire _GEN_36 = dis_uops_2_uopc == 7'h6C; // @[core.scala:167:24, :691:76]
wire _block_rocc_T_4; // @[core.scala:691:76]
assign _block_rocc_T_4 = _GEN_36; // @[core.scala:691:76]
wire _dis_rocc_alloc_stall_T_2; // @[core.scala:692:51]
assign _dis_rocc_alloc_stall_T_2 = _GEN_36; // @[core.scala:691:76, :692:51]
wire _block_rocc_T_5 = dis_valids_2 & _block_rocc_T_4; // @[core.scala:166:24, :691:{66,76}]
wire block_rocc_2 = block_rocc_1 | _block_rocc_T_3; // @[core.scala:691:{66,109}]
wire block_rocc_3 = block_rocc_2 | _block_rocc_T_5; // @[core.scala:691:{66,109}]
wire _dis_hazards_T = ~_rob_io_ready; // @[core.scala:143:32, :697:26]
wire _dis_hazards_T_1 = _dis_hazards_T | ren_stalls_0; // @[core.scala:163:24, :697:26, :698:23]
wire _dis_hazards_T_2 = io_lsu_ldq_full_0_0 & dis_uops_0_uses_ldq; // @[core.scala:51:7, :167:24, :699:45]
wire _dis_hazards_T_3 = _dis_hazards_T_1 | _dis_hazards_T_2; // @[core.scala:698:23, :699:{23,45}]
wire _dis_hazards_T_4 = io_lsu_stq_full_0_0 & dis_uops_0_uses_stq; // @[core.scala:51:7, :167:24, :700:45]
wire _dis_hazards_T_5 = _dis_hazards_T_3 | _dis_hazards_T_4; // @[core.scala:699:23, :700:{23,45}]
wire _dis_hazards_T_6 = ~_dispatcher_io_ren_uops_0_ready; // @[core.scala:114:32, :701:26]
wire _dis_hazards_T_7 = _dis_hazards_T_5 | _dis_hazards_T_6; // @[core.scala:700:23, :701:{23,26}]
wire _dis_hazards_T_8 = _dis_hazards_T_7 | wait_for_empty_pipeline_0; // @[core.scala:685:112, :701:23, :702:23]
wire _dis_hazards_T_9 = _dis_hazards_T_8; // @[core.scala:702:23, :703:23]
wire _dis_hazards_T_10 = _dis_hazards_T_9; // @[core.scala:703:23, :704:23]
wire _dis_hazards_T_11 = _dis_hazards_T_10; // @[core.scala:704:23, :705:23]
wire _dis_hazards_T_12 = |brupdate_b1_mispredict_mask; // @[core.scala:188:23, :224:42, :706:54]
wire _dis_hazards_T_13 = _dis_hazards_T_11 | _dis_hazards_T_12; // @[core.scala:705:23, :706:{23,54}]
wire _dis_hazards_T_14 = _dis_hazards_T_13 | brupdate_b2_mispredict; // @[core.scala:188:23, :706:23, :707:23]
wire _dis_hazards_T_15 = _dis_hazards_T_14 | io_ifu_redirect_flush_0; // @[core.scala:51:7, :707:23, :708:23]
wire dis_hazards_0 = dis_valids_0 & _dis_hazards_T_15; // @[core.scala:166:24, :696:37, :708:23]
wire dis_stalls_0 = dis_hazards_0; // @[core.scala:696:37, :713:62]
wire _dis_hazards_T_16 = ~_rob_io_ready; // @[core.scala:143:32, :697:26]
wire _dis_hazards_T_17 = _dis_hazards_T_16 | ren_stalls_1; // @[core.scala:163:24, :697:26, :698:23]
wire _dis_hazards_T_18 = io_lsu_ldq_full_1_0 & dis_uops_1_uses_ldq; // @[core.scala:51:7, :167:24, :699:45]
wire _dis_hazards_T_19 = _dis_hazards_T_17 | _dis_hazards_T_18; // @[core.scala:698:23, :699:{23,45}]
wire _dis_hazards_T_20 = io_lsu_stq_full_1_0 & dis_uops_1_uses_stq; // @[core.scala:51:7, :167:24, :700:45]
wire _dis_hazards_T_21 = _dis_hazards_T_19 | _dis_hazards_T_20; // @[core.scala:699:23, :700:{23,45}]
wire _dis_hazards_T_22 = ~_dispatcher_io_ren_uops_1_ready; // @[core.scala:114:32, :701:26]
wire _dis_hazards_T_23 = _dis_hazards_T_21 | _dis_hazards_T_22; // @[core.scala:700:23, :701:{23,26}]
wire _dis_hazards_T_24 = _dis_hazards_T_23 | wait_for_empty_pipeline_1; // @[core.scala:685:112, :701:23, :702:23]
wire _dis_hazards_T_25 = _dis_hazards_T_24; // @[core.scala:702:23, :703:23]
wire _dis_hazards_T_26 = _dis_hazards_T_25 | dis_prior_slot_unique_1; // @[core.scala:684:96, :703:23, :704:23]
wire _dis_hazards_T_27 = _dis_hazards_T_26; // @[core.scala:704:23, :705:23]
wire _dis_hazards_T_28 = |brupdate_b1_mispredict_mask; // @[core.scala:188:23, :224:42, :706:54]
wire _dis_hazards_T_29 = _dis_hazards_T_27 | _dis_hazards_T_28; // @[core.scala:705:23, :706:{23,54}]
wire _dis_hazards_T_30 = _dis_hazards_T_29 | brupdate_b2_mispredict; // @[core.scala:188:23, :706:23, :707:23]
wire _dis_hazards_T_31 = _dis_hazards_T_30 | io_ifu_redirect_flush_0; // @[core.scala:51:7, :707:23, :708:23]
wire dis_hazards_1 = dis_valids_1 & _dis_hazards_T_31; // @[core.scala:166:24, :696:37, :708:23]
wire _dis_hazards_T_32 = ~_rob_io_ready; // @[core.scala:143:32, :697:26]
wire _dis_hazards_T_33 = _dis_hazards_T_32 | ren_stalls_2; // @[core.scala:163:24, :697:26, :698:23]
wire _dis_hazards_T_34 = io_lsu_ldq_full_2_0 & dis_uops_2_uses_ldq; // @[core.scala:51:7, :167:24, :699:45]
wire _dis_hazards_T_35 = _dis_hazards_T_33 | _dis_hazards_T_34; // @[core.scala:698:23, :699:{23,45}]
wire _dis_hazards_T_36 = io_lsu_stq_full_2_0 & dis_uops_2_uses_stq; // @[core.scala:51:7, :167:24, :700:45]
wire _dis_hazards_T_37 = _dis_hazards_T_35 | _dis_hazards_T_36; // @[core.scala:699:23, :700:{23,45}]
wire _dis_hazards_T_38 = ~_dispatcher_io_ren_uops_2_ready; // @[core.scala:114:32, :701:26]
wire _dis_hazards_T_39 = _dis_hazards_T_37 | _dis_hazards_T_38; // @[core.scala:700:23, :701:{23,26}]
wire _dis_hazards_T_40 = _dis_hazards_T_39 | wait_for_empty_pipeline_2; // @[core.scala:685:112, :701:23, :702:23]
wire _dis_hazards_T_41 = _dis_hazards_T_40; // @[core.scala:702:23, :703:23]
wire _dis_hazards_T_42 = _dis_hazards_T_41 | dis_prior_slot_unique_2; // @[core.scala:684:96, :703:23, :704:23]
wire _dis_hazards_T_43 = _dis_hazards_T_42; // @[core.scala:704:23, :705:23]
wire _dis_hazards_T_44 = |brupdate_b1_mispredict_mask; // @[core.scala:188:23, :224:42, :706:54]
wire _dis_hazards_T_45 = _dis_hazards_T_43 | _dis_hazards_T_44; // @[core.scala:705:23, :706:{23,54}]
wire _dis_hazards_T_46 = _dis_hazards_T_45 | brupdate_b2_mispredict; // @[core.scala:188:23, :706:23, :707:23]
wire _dis_hazards_T_47 = _dis_hazards_T_46 | io_ifu_redirect_flush_0; // @[core.scala:51:7, :707:23, :708:23]
wire dis_hazards_2 = dis_valids_2 & _dis_hazards_T_47; // @[core.scala:166:24, :696:37, :708:23]
wire _io_lsu_fence_dmem_T = dis_valids_0 & wait_for_empty_pipeline_0; // @[core.scala:166:24, :685:112, :711:86]
wire _io_lsu_fence_dmem_T_1 = dis_valids_1 & wait_for_empty_pipeline_1; // @[core.scala:166:24, :685:112, :711:86]
wire _io_lsu_fence_dmem_T_2 = dis_valids_2 & wait_for_empty_pipeline_2; // @[core.scala:166:24, :685:112, :711:86]
wire _io_lsu_fence_dmem_T_3 = _io_lsu_fence_dmem_T | _io_lsu_fence_dmem_T_1; // @[core.scala:711:{86,101}]
assign _io_lsu_fence_dmem_T_4 = _io_lsu_fence_dmem_T_3 | _io_lsu_fence_dmem_T_2; // @[core.scala:711:{86,101}]
assign io_lsu_fence_dmem_0 = _io_lsu_fence_dmem_T_4; // @[core.scala:51:7, :711:101]
wire dis_stalls_1 = dis_stalls_0 | dis_hazards_1; // @[core.scala:696:37, :713:62]
wire dis_stalls_2 = dis_stalls_1 | dis_hazards_2; // @[core.scala:696:37, :713:62]
assign dis_fire_0 = dis_valids_0 & ~dis_stalls_0; // @[core.scala:166:24, :168:24, :713:62, :714:{62,65}]
assign dis_fire_1 = dis_valids_1 & ~dis_stalls_1; // @[core.scala:166:24, :168:24, :713:62, :714:{62,65}]
assign dis_fire_2 = dis_valids_2 & ~dis_stalls_2; // @[core.scala:166:24, :168:24, :713:62, :714:{62,65}]
assign _dis_ready_T = ~dis_stalls_2; // @[core.scala:713:62, :714:65, :715:16]
assign dis_ready = _dis_ready_T; // @[core.scala:169:24, :715:16]
reg REG_3; // @[core.scala:738:16]
assign io_ifu_commit_valid_0 = REG_3 | _io_ifu_commit_valid_T_2; // @[core.scala:51:7, :466:{23,59}, :738:{16,94}, :739:25]
wire [1:0] _io_ifu_commit_bits_T_1 = dis_valids_1 ? 2'h1 : 2'h2; // @[Mux.scala:50:70]
wire [1:0] _io_ifu_commit_bits_T_2 = dis_valids_0 ? 2'h0 : _io_ifu_commit_bits_T_1; // @[Mux.scala:50:70]
reg [4:0] io_ifu_commit_bits_REG; // @[core.scala:740:35]
assign io_ifu_commit_bits_0 = {27'h0, REG_3 ? io_ifu_commit_bits_REG : _io_ifu_commit_bits_T}; // @[core.scala:51:7, :467:{23,29}, :738:{16,94}, :740:{25,35}]
wire [6:0] _GEN_37 = {2'h0, _rob_io_rob_tail_idx[6:2]}; // @[core.scala:143:32, :749:54]
wire [6:0] _dis_uops_0_rob_idx_T; // @[core.scala:749:54]
assign _dis_uops_0_rob_idx_T = _GEN_37; // @[core.scala:749:54]
wire [6:0] _dis_uops_1_rob_idx_T; // @[core.scala:749:54]
assign _dis_uops_1_rob_idx_T = _GEN_37; // @[core.scala:749:54]
wire [6:0] _dis_uops_2_rob_idx_T; // @[core.scala:749:54]
assign _dis_uops_2_rob_idx_T = _GEN_37; // @[core.scala:749:54]
wire [8:0] _dis_uops_0_rob_idx_T_1 = {_dis_uops_0_rob_idx_T, 2'h0}; // @[core.scala:749:{33,54}]
assign dis_uops_0_rob_idx = _dis_uops_0_rob_idx_T_1[6:0]; // @[core.scala:167:24, :749:{27,33}]
wire [8:0] _dis_uops_1_rob_idx_T_1 = {_dis_uops_1_rob_idx_T, 2'h1}; // @[core.scala:749:{33,54}]
assign dis_uops_1_rob_idx = _dis_uops_1_rob_idx_T_1[6:0]; // @[core.scala:167:24, :749:{27,33}]
wire [8:0] _dis_uops_2_rob_idx_T_1 = {_dis_uops_2_rob_idx_T, 2'h2}; // @[core.scala:749:{33,54}]
assign dis_uops_2_rob_idx = _dis_uops_2_rob_idx_T_1[6:0]; // @[core.scala:167:24, :749:{27,33}]
wire _GEN_38 = _ll_wbarb_io_out_bits_uop_dst_rtype == 2'h0; // @[core.scala:132:32, :795:90]
wire _int_iss_wakeups_0_valid_T_1; // @[core.scala:795:90]
assign _int_iss_wakeups_0_valid_T_1 = _GEN_38; // @[core.scala:795:90]
wire _int_ren_wakeups_0_valid_T_1; // @[core.scala:798:90]
assign _int_ren_wakeups_0_valid_T_1 = _GEN_38; // @[core.scala:795:90, :798:90]
wire _iregfile_io_write_ports_0_wport_valid_T; // @[regfile.scala:57:61]
assign _iregfile_io_write_ports_0_wport_valid_T = _GEN_38; // @[regfile.scala:57:61]
wire _int_iss_wakeups_0_valid_T; // @[Decoupled.scala:51:35]
assign _int_iss_wakeups_0_valid_T_2 = _int_iss_wakeups_0_valid_T & _int_iss_wakeups_0_valid_T_1; // @[Decoupled.scala:51:35]
assign int_iss_wakeups_0_valid = _int_iss_wakeups_0_valid_T_2; // @[core.scala:147:30, :795:52]
wire _int_ren_wakeups_0_valid_T; // @[Decoupled.scala:51:35]
assign _int_ren_wakeups_0_valid_T_2 = _int_ren_wakeups_0_valid_T & _int_ren_wakeups_0_valid_T_1; // @[Decoupled.scala:51:35]
assign int_ren_wakeups_0_valid = _int_ren_wakeups_0_valid_T_2; // @[core.scala:148:30, :798:52]
wire _fast_wakeup_valid_T_7; // @[core.scala:827:52]
assign int_iss_wakeups_1_valid = fast_wakeup_valid; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_valid = fast_wakeup_valid; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_uopc = fast_wakeup_bits_uop_uopc; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_uopc = fast_wakeup_bits_uop_uopc; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_inst = fast_wakeup_bits_uop_inst; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_inst = fast_wakeup_bits_uop_inst; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_debug_inst = fast_wakeup_bits_uop_debug_inst; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_debug_inst = fast_wakeup_bits_uop_debug_inst; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_is_rvc = fast_wakeup_bits_uop_is_rvc; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_is_rvc = fast_wakeup_bits_uop_is_rvc; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_debug_pc = fast_wakeup_bits_uop_debug_pc; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_debug_pc = fast_wakeup_bits_uop_debug_pc; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_iq_type = fast_wakeup_bits_uop_iq_type; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_iq_type = fast_wakeup_bits_uop_iq_type; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_fu_code = fast_wakeup_bits_uop_fu_code; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_fu_code = fast_wakeup_bits_uop_fu_code; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_ctrl_br_type = fast_wakeup_bits_uop_ctrl_br_type; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_ctrl_br_type = fast_wakeup_bits_uop_ctrl_br_type; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_ctrl_op1_sel = fast_wakeup_bits_uop_ctrl_op1_sel; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_ctrl_op1_sel = fast_wakeup_bits_uop_ctrl_op1_sel; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_ctrl_op2_sel = fast_wakeup_bits_uop_ctrl_op2_sel; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_ctrl_op2_sel = fast_wakeup_bits_uop_ctrl_op2_sel; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_ctrl_imm_sel = fast_wakeup_bits_uop_ctrl_imm_sel; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_ctrl_imm_sel = fast_wakeup_bits_uop_ctrl_imm_sel; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_ctrl_op_fcn = fast_wakeup_bits_uop_ctrl_op_fcn; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_ctrl_op_fcn = fast_wakeup_bits_uop_ctrl_op_fcn; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_ctrl_fcn_dw = fast_wakeup_bits_uop_ctrl_fcn_dw; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_ctrl_fcn_dw = fast_wakeup_bits_uop_ctrl_fcn_dw; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_ctrl_csr_cmd = fast_wakeup_bits_uop_ctrl_csr_cmd; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_ctrl_csr_cmd = fast_wakeup_bits_uop_ctrl_csr_cmd; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_ctrl_is_load = fast_wakeup_bits_uop_ctrl_is_load; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_ctrl_is_load = fast_wakeup_bits_uop_ctrl_is_load; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_ctrl_is_sta = fast_wakeup_bits_uop_ctrl_is_sta; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_ctrl_is_sta = fast_wakeup_bits_uop_ctrl_is_sta; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_ctrl_is_std = fast_wakeup_bits_uop_ctrl_is_std; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_ctrl_is_std = fast_wakeup_bits_uop_ctrl_is_std; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_iw_state = fast_wakeup_bits_uop_iw_state; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_iw_state = fast_wakeup_bits_uop_iw_state; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_iw_p1_poisoned = fast_wakeup_bits_uop_iw_p1_poisoned; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_iw_p1_poisoned = fast_wakeup_bits_uop_iw_p1_poisoned; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_iw_p2_poisoned = fast_wakeup_bits_uop_iw_p2_poisoned; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_iw_p2_poisoned = fast_wakeup_bits_uop_iw_p2_poisoned; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_is_br = fast_wakeup_bits_uop_is_br; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_is_br = fast_wakeup_bits_uop_is_br; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_is_jalr = fast_wakeup_bits_uop_is_jalr; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_is_jalr = fast_wakeup_bits_uop_is_jalr; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_is_jal = fast_wakeup_bits_uop_is_jal; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_is_jal = fast_wakeup_bits_uop_is_jal; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_is_sfb = fast_wakeup_bits_uop_is_sfb; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_is_sfb = fast_wakeup_bits_uop_is_sfb; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_br_mask = fast_wakeup_bits_uop_br_mask; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_br_mask = fast_wakeup_bits_uop_br_mask; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_br_tag = fast_wakeup_bits_uop_br_tag; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_br_tag = fast_wakeup_bits_uop_br_tag; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_ftq_idx = fast_wakeup_bits_uop_ftq_idx; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_ftq_idx = fast_wakeup_bits_uop_ftq_idx; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_edge_inst = fast_wakeup_bits_uop_edge_inst; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_edge_inst = fast_wakeup_bits_uop_edge_inst; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_pc_lob = fast_wakeup_bits_uop_pc_lob; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_pc_lob = fast_wakeup_bits_uop_pc_lob; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_taken = fast_wakeup_bits_uop_taken; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_taken = fast_wakeup_bits_uop_taken; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_imm_packed = fast_wakeup_bits_uop_imm_packed; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_imm_packed = fast_wakeup_bits_uop_imm_packed; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_csr_addr = fast_wakeup_bits_uop_csr_addr; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_csr_addr = fast_wakeup_bits_uop_csr_addr; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_rob_idx = fast_wakeup_bits_uop_rob_idx; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_rob_idx = fast_wakeup_bits_uop_rob_idx; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_ldq_idx = fast_wakeup_bits_uop_ldq_idx; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_ldq_idx = fast_wakeup_bits_uop_ldq_idx; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_stq_idx = fast_wakeup_bits_uop_stq_idx; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_stq_idx = fast_wakeup_bits_uop_stq_idx; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_rxq_idx = fast_wakeup_bits_uop_rxq_idx; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_rxq_idx = fast_wakeup_bits_uop_rxq_idx; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_pdst = fast_wakeup_bits_uop_pdst; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_pdst = fast_wakeup_bits_uop_pdst; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_prs1 = fast_wakeup_bits_uop_prs1; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_prs1 = fast_wakeup_bits_uop_prs1; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_prs2 = fast_wakeup_bits_uop_prs2; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_prs2 = fast_wakeup_bits_uop_prs2; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_prs3 = fast_wakeup_bits_uop_prs3; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_prs3 = fast_wakeup_bits_uop_prs3; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_ppred = fast_wakeup_bits_uop_ppred; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_ppred = fast_wakeup_bits_uop_ppred; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_prs1_busy = fast_wakeup_bits_uop_prs1_busy; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_prs1_busy = fast_wakeup_bits_uop_prs1_busy; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_prs2_busy = fast_wakeup_bits_uop_prs2_busy; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_prs2_busy = fast_wakeup_bits_uop_prs2_busy; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_prs3_busy = fast_wakeup_bits_uop_prs3_busy; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_prs3_busy = fast_wakeup_bits_uop_prs3_busy; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_ppred_busy = fast_wakeup_bits_uop_ppred_busy; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_ppred_busy = fast_wakeup_bits_uop_ppred_busy; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_stale_pdst = fast_wakeup_bits_uop_stale_pdst; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_stale_pdst = fast_wakeup_bits_uop_stale_pdst; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_exception = fast_wakeup_bits_uop_exception; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_exception = fast_wakeup_bits_uop_exception; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_exc_cause = fast_wakeup_bits_uop_exc_cause; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_exc_cause = fast_wakeup_bits_uop_exc_cause; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_bypassable = fast_wakeup_bits_uop_bypassable; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_bypassable = fast_wakeup_bits_uop_bypassable; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_mem_cmd = fast_wakeup_bits_uop_mem_cmd; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_mem_cmd = fast_wakeup_bits_uop_mem_cmd; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_mem_size = fast_wakeup_bits_uop_mem_size; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_mem_size = fast_wakeup_bits_uop_mem_size; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_mem_signed = fast_wakeup_bits_uop_mem_signed; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_mem_signed = fast_wakeup_bits_uop_mem_signed; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_is_fence = fast_wakeup_bits_uop_is_fence; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_is_fence = fast_wakeup_bits_uop_is_fence; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_is_fencei = fast_wakeup_bits_uop_is_fencei; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_is_fencei = fast_wakeup_bits_uop_is_fencei; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_is_amo = fast_wakeup_bits_uop_is_amo; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_is_amo = fast_wakeup_bits_uop_is_amo; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_uses_ldq = fast_wakeup_bits_uop_uses_ldq; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_uses_ldq = fast_wakeup_bits_uop_uses_ldq; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_uses_stq = fast_wakeup_bits_uop_uses_stq; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_uses_stq = fast_wakeup_bits_uop_uses_stq; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_is_sys_pc2epc = fast_wakeup_bits_uop_is_sys_pc2epc; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_is_sys_pc2epc = fast_wakeup_bits_uop_is_sys_pc2epc; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_is_unique = fast_wakeup_bits_uop_is_unique; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_is_unique = fast_wakeup_bits_uop_is_unique; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_flush_on_commit = fast_wakeup_bits_uop_flush_on_commit; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_flush_on_commit = fast_wakeup_bits_uop_flush_on_commit; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_ldst_is_rs1 = fast_wakeup_bits_uop_ldst_is_rs1; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_ldst_is_rs1 = fast_wakeup_bits_uop_ldst_is_rs1; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_ldst = fast_wakeup_bits_uop_ldst; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_ldst = fast_wakeup_bits_uop_ldst; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_lrs1 = fast_wakeup_bits_uop_lrs1; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_lrs1 = fast_wakeup_bits_uop_lrs1; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_lrs2 = fast_wakeup_bits_uop_lrs2; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_lrs2 = fast_wakeup_bits_uop_lrs2; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_lrs3 = fast_wakeup_bits_uop_lrs3; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_lrs3 = fast_wakeup_bits_uop_lrs3; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_ldst_val = fast_wakeup_bits_uop_ldst_val; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_ldst_val = fast_wakeup_bits_uop_ldst_val; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_dst_rtype = fast_wakeup_bits_uop_dst_rtype; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_dst_rtype = fast_wakeup_bits_uop_dst_rtype; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_lrs1_rtype = fast_wakeup_bits_uop_lrs1_rtype; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_lrs1_rtype = fast_wakeup_bits_uop_lrs1_rtype; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_lrs2_rtype = fast_wakeup_bits_uop_lrs2_rtype; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_lrs2_rtype = fast_wakeup_bits_uop_lrs2_rtype; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_frs3_en = fast_wakeup_bits_uop_frs3_en; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_frs3_en = fast_wakeup_bits_uop_frs3_en; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_fp_val = fast_wakeup_bits_uop_fp_val; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_fp_val = fast_wakeup_bits_uop_fp_val; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_fp_single = fast_wakeup_bits_uop_fp_single; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_fp_single = fast_wakeup_bits_uop_fp_single; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_xcpt_pf_if = fast_wakeup_bits_uop_xcpt_pf_if; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_xcpt_pf_if = fast_wakeup_bits_uop_xcpt_pf_if; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_xcpt_ae_if = fast_wakeup_bits_uop_xcpt_ae_if; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_xcpt_ae_if = fast_wakeup_bits_uop_xcpt_ae_if; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_xcpt_ma_if = fast_wakeup_bits_uop_xcpt_ma_if; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_xcpt_ma_if = fast_wakeup_bits_uop_xcpt_ma_if; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_bp_debug_if = fast_wakeup_bits_uop_bp_debug_if; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_bp_debug_if = fast_wakeup_bits_uop_bp_debug_if; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_bp_xcpt_if = fast_wakeup_bits_uop_bp_xcpt_if; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_bp_xcpt_if = fast_wakeup_bits_uop_bp_xcpt_if; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_debug_fsrc = fast_wakeup_bits_uop_debug_fsrc; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_debug_fsrc = fast_wakeup_bits_uop_debug_fsrc; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_1_bits_uop_debug_tsrc = fast_wakeup_bits_uop_debug_tsrc; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_1_bits_uop_debug_tsrc = fast_wakeup_bits_uop_debug_tsrc; // @[core.scala:148:30, :814:29]
wire _slow_wakeup_valid_T_5; // @[core.scala:834:59]
assign int_iss_wakeups_2_valid = slow_wakeup_valid; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_valid = slow_wakeup_valid; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_uopc = slow_wakeup_bits_uop_uopc; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_uopc = slow_wakeup_bits_uop_uopc; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_inst = slow_wakeup_bits_uop_inst; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_inst = slow_wakeup_bits_uop_inst; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_debug_inst = slow_wakeup_bits_uop_debug_inst; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_debug_inst = slow_wakeup_bits_uop_debug_inst; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_is_rvc = slow_wakeup_bits_uop_is_rvc; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_is_rvc = slow_wakeup_bits_uop_is_rvc; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_debug_pc = slow_wakeup_bits_uop_debug_pc; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_debug_pc = slow_wakeup_bits_uop_debug_pc; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_iq_type = slow_wakeup_bits_uop_iq_type; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_iq_type = slow_wakeup_bits_uop_iq_type; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_fu_code = slow_wakeup_bits_uop_fu_code; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_fu_code = slow_wakeup_bits_uop_fu_code; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_ctrl_br_type = slow_wakeup_bits_uop_ctrl_br_type; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_ctrl_br_type = slow_wakeup_bits_uop_ctrl_br_type; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_ctrl_op1_sel = slow_wakeup_bits_uop_ctrl_op1_sel; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_ctrl_op1_sel = slow_wakeup_bits_uop_ctrl_op1_sel; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_ctrl_op2_sel = slow_wakeup_bits_uop_ctrl_op2_sel; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_ctrl_op2_sel = slow_wakeup_bits_uop_ctrl_op2_sel; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_ctrl_imm_sel = slow_wakeup_bits_uop_ctrl_imm_sel; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_ctrl_imm_sel = slow_wakeup_bits_uop_ctrl_imm_sel; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_ctrl_op_fcn = slow_wakeup_bits_uop_ctrl_op_fcn; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_ctrl_op_fcn = slow_wakeup_bits_uop_ctrl_op_fcn; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_ctrl_fcn_dw = slow_wakeup_bits_uop_ctrl_fcn_dw; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_ctrl_fcn_dw = slow_wakeup_bits_uop_ctrl_fcn_dw; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_ctrl_csr_cmd = slow_wakeup_bits_uop_ctrl_csr_cmd; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_ctrl_csr_cmd = slow_wakeup_bits_uop_ctrl_csr_cmd; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_ctrl_is_load = slow_wakeup_bits_uop_ctrl_is_load; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_ctrl_is_load = slow_wakeup_bits_uop_ctrl_is_load; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_ctrl_is_sta = slow_wakeup_bits_uop_ctrl_is_sta; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_ctrl_is_sta = slow_wakeup_bits_uop_ctrl_is_sta; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_ctrl_is_std = slow_wakeup_bits_uop_ctrl_is_std; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_ctrl_is_std = slow_wakeup_bits_uop_ctrl_is_std; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_iw_state = slow_wakeup_bits_uop_iw_state; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_iw_state = slow_wakeup_bits_uop_iw_state; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_iw_p1_poisoned = slow_wakeup_bits_uop_iw_p1_poisoned; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_iw_p1_poisoned = slow_wakeup_bits_uop_iw_p1_poisoned; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_iw_p2_poisoned = slow_wakeup_bits_uop_iw_p2_poisoned; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_iw_p2_poisoned = slow_wakeup_bits_uop_iw_p2_poisoned; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_is_br = slow_wakeup_bits_uop_is_br; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_is_br = slow_wakeup_bits_uop_is_br; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_is_jalr = slow_wakeup_bits_uop_is_jalr; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_is_jalr = slow_wakeup_bits_uop_is_jalr; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_is_jal = slow_wakeup_bits_uop_is_jal; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_is_jal = slow_wakeup_bits_uop_is_jal; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_is_sfb = slow_wakeup_bits_uop_is_sfb; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_is_sfb = slow_wakeup_bits_uop_is_sfb; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_br_mask = slow_wakeup_bits_uop_br_mask; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_br_mask = slow_wakeup_bits_uop_br_mask; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_br_tag = slow_wakeup_bits_uop_br_tag; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_br_tag = slow_wakeup_bits_uop_br_tag; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_ftq_idx = slow_wakeup_bits_uop_ftq_idx; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_ftq_idx = slow_wakeup_bits_uop_ftq_idx; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_edge_inst = slow_wakeup_bits_uop_edge_inst; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_edge_inst = slow_wakeup_bits_uop_edge_inst; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_pc_lob = slow_wakeup_bits_uop_pc_lob; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_pc_lob = slow_wakeup_bits_uop_pc_lob; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_taken = slow_wakeup_bits_uop_taken; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_taken = slow_wakeup_bits_uop_taken; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_imm_packed = slow_wakeup_bits_uop_imm_packed; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_imm_packed = slow_wakeup_bits_uop_imm_packed; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_csr_addr = slow_wakeup_bits_uop_csr_addr; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_csr_addr = slow_wakeup_bits_uop_csr_addr; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_rob_idx = slow_wakeup_bits_uop_rob_idx; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_rob_idx = slow_wakeup_bits_uop_rob_idx; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_ldq_idx = slow_wakeup_bits_uop_ldq_idx; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_ldq_idx = slow_wakeup_bits_uop_ldq_idx; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_stq_idx = slow_wakeup_bits_uop_stq_idx; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_stq_idx = slow_wakeup_bits_uop_stq_idx; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_rxq_idx = slow_wakeup_bits_uop_rxq_idx; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_rxq_idx = slow_wakeup_bits_uop_rxq_idx; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_pdst = slow_wakeup_bits_uop_pdst; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_pdst = slow_wakeup_bits_uop_pdst; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_prs1 = slow_wakeup_bits_uop_prs1; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_prs1 = slow_wakeup_bits_uop_prs1; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_prs2 = slow_wakeup_bits_uop_prs2; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_prs2 = slow_wakeup_bits_uop_prs2; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_prs3 = slow_wakeup_bits_uop_prs3; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_prs3 = slow_wakeup_bits_uop_prs3; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_ppred = slow_wakeup_bits_uop_ppred; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_ppred = slow_wakeup_bits_uop_ppred; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_prs1_busy = slow_wakeup_bits_uop_prs1_busy; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_prs1_busy = slow_wakeup_bits_uop_prs1_busy; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_prs2_busy = slow_wakeup_bits_uop_prs2_busy; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_prs2_busy = slow_wakeup_bits_uop_prs2_busy; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_prs3_busy = slow_wakeup_bits_uop_prs3_busy; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_prs3_busy = slow_wakeup_bits_uop_prs3_busy; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_ppred_busy = slow_wakeup_bits_uop_ppred_busy; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_ppred_busy = slow_wakeup_bits_uop_ppred_busy; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_stale_pdst = slow_wakeup_bits_uop_stale_pdst; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_stale_pdst = slow_wakeup_bits_uop_stale_pdst; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_exception = slow_wakeup_bits_uop_exception; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_exception = slow_wakeup_bits_uop_exception; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_exc_cause = slow_wakeup_bits_uop_exc_cause; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_exc_cause = slow_wakeup_bits_uop_exc_cause; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_bypassable = slow_wakeup_bits_uop_bypassable; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_bypassable = slow_wakeup_bits_uop_bypassable; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_mem_cmd = slow_wakeup_bits_uop_mem_cmd; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_mem_cmd = slow_wakeup_bits_uop_mem_cmd; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_mem_size = slow_wakeup_bits_uop_mem_size; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_mem_size = slow_wakeup_bits_uop_mem_size; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_mem_signed = slow_wakeup_bits_uop_mem_signed; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_mem_signed = slow_wakeup_bits_uop_mem_signed; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_is_fence = slow_wakeup_bits_uop_is_fence; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_is_fence = slow_wakeup_bits_uop_is_fence; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_is_fencei = slow_wakeup_bits_uop_is_fencei; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_is_fencei = slow_wakeup_bits_uop_is_fencei; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_is_amo = slow_wakeup_bits_uop_is_amo; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_is_amo = slow_wakeup_bits_uop_is_amo; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_uses_ldq = slow_wakeup_bits_uop_uses_ldq; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_uses_ldq = slow_wakeup_bits_uop_uses_ldq; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_uses_stq = slow_wakeup_bits_uop_uses_stq; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_uses_stq = slow_wakeup_bits_uop_uses_stq; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_is_sys_pc2epc = slow_wakeup_bits_uop_is_sys_pc2epc; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_is_sys_pc2epc = slow_wakeup_bits_uop_is_sys_pc2epc; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_is_unique = slow_wakeup_bits_uop_is_unique; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_is_unique = slow_wakeup_bits_uop_is_unique; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_flush_on_commit = slow_wakeup_bits_uop_flush_on_commit; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_flush_on_commit = slow_wakeup_bits_uop_flush_on_commit; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_ldst_is_rs1 = slow_wakeup_bits_uop_ldst_is_rs1; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_ldst_is_rs1 = slow_wakeup_bits_uop_ldst_is_rs1; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_ldst = slow_wakeup_bits_uop_ldst; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_ldst = slow_wakeup_bits_uop_ldst; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_lrs1 = slow_wakeup_bits_uop_lrs1; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_lrs1 = slow_wakeup_bits_uop_lrs1; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_lrs2 = slow_wakeup_bits_uop_lrs2; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_lrs2 = slow_wakeup_bits_uop_lrs2; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_lrs3 = slow_wakeup_bits_uop_lrs3; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_lrs3 = slow_wakeup_bits_uop_lrs3; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_ldst_val = slow_wakeup_bits_uop_ldst_val; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_ldst_val = slow_wakeup_bits_uop_ldst_val; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_dst_rtype = slow_wakeup_bits_uop_dst_rtype; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_dst_rtype = slow_wakeup_bits_uop_dst_rtype; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_lrs1_rtype = slow_wakeup_bits_uop_lrs1_rtype; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_lrs1_rtype = slow_wakeup_bits_uop_lrs1_rtype; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_lrs2_rtype = slow_wakeup_bits_uop_lrs2_rtype; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_lrs2_rtype = slow_wakeup_bits_uop_lrs2_rtype; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_frs3_en = slow_wakeup_bits_uop_frs3_en; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_frs3_en = slow_wakeup_bits_uop_frs3_en; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_fp_val = slow_wakeup_bits_uop_fp_val; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_fp_val = slow_wakeup_bits_uop_fp_val; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_fp_single = slow_wakeup_bits_uop_fp_single; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_fp_single = slow_wakeup_bits_uop_fp_single; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_xcpt_pf_if = slow_wakeup_bits_uop_xcpt_pf_if; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_xcpt_pf_if = slow_wakeup_bits_uop_xcpt_pf_if; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_xcpt_ae_if = slow_wakeup_bits_uop_xcpt_ae_if; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_xcpt_ae_if = slow_wakeup_bits_uop_xcpt_ae_if; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_xcpt_ma_if = slow_wakeup_bits_uop_xcpt_ma_if; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_xcpt_ma_if = slow_wakeup_bits_uop_xcpt_ma_if; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_bp_debug_if = slow_wakeup_bits_uop_bp_debug_if; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_bp_debug_if = slow_wakeup_bits_uop_bp_debug_if; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_bp_xcpt_if = slow_wakeup_bits_uop_bp_xcpt_if; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_bp_xcpt_if = slow_wakeup_bits_uop_bp_xcpt_if; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_debug_fsrc = slow_wakeup_bits_uop_debug_fsrc; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_debug_fsrc = slow_wakeup_bits_uop_debug_fsrc; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_2_bits_uop_debug_tsrc = slow_wakeup_bits_uop_debug_tsrc; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_2_bits_uop_debug_tsrc = slow_wakeup_bits_uop_debug_tsrc; // @[core.scala:148:30, :815:29]
wire _T_99 = _alu_exe_unit_io_iresp_bits_uop_dst_rtype != 2'h2; // @[execution-units.scala:119:32]
wire _slow_wakeup_valid_T; // @[micro-op.scala:149:36]
assign _slow_wakeup_valid_T = _T_99; // @[micro-op.scala:149:36]
wire _iregfile_io_write_ports_1_valid_T; // @[micro-op.scala:149:36]
assign _iregfile_io_write_ports_1_valid_T = _T_99; // @[micro-op.scala:149:36]
wire _rob_io_debug_wb_valids_1_T; // @[micro-op.scala:149:36]
assign _rob_io_debug_wb_valids_1_T = _T_99; // @[micro-op.scala:149:36]
wire _fast_wakeup_valid_T = iss_valids_1 & iss_uops_1_bypassable; // @[core.scala:172:24, :173:24, :824:45]
wire _fast_wakeup_valid_T_1 = iss_uops_1_dst_rtype == 2'h0; // @[core.scala:173:24, :826:53]
wire _fast_wakeup_valid_T_2 = _fast_wakeup_valid_T & _fast_wakeup_valid_T_1; // @[core.scala:824:45, :825:54, :826:53]
wire _fast_wakeup_valid_T_3 = _fast_wakeup_valid_T_2 & iss_uops_1_ldst_val; // @[core.scala:173:24, :825:54, :826:64]
wire _GEN_39 = iss_uops_1_iw_p1_poisoned | iss_uops_1_iw_p2_poisoned; // @[core.scala:173:24, :828:79]
wire _fast_wakeup_valid_T_4; // @[core.scala:828:79]
assign _fast_wakeup_valid_T_4 = _GEN_39; // @[core.scala:828:79]
wire _pred_wakeup_valid_T_3; // @[core.scala:864:84]
assign _pred_wakeup_valid_T_3 = _GEN_39; // @[core.scala:828:79, :864:84]
wire _iregister_read_io_iss_valids_1_T; // @[core.scala:981:72]
assign _iregister_read_io_iss_valids_1_T = _GEN_39; // @[core.scala:828:79, :981:72]
wire _fast_wakeup_valid_T_5 = io_lsu_ld_miss_0 & _fast_wakeup_valid_T_4; // @[core.scala:51:7, :828:{48,79}]
wire _fast_wakeup_valid_T_6 = ~_fast_wakeup_valid_T_5; // @[core.scala:828:{31,48}]
assign _fast_wakeup_valid_T_7 = _fast_wakeup_valid_T_3 & _fast_wakeup_valid_T_6; // @[core.scala:826:64, :827:52, :828:31]
assign fast_wakeup_valid = _fast_wakeup_valid_T_7; // @[core.scala:814:29, :827:52]
wire _slow_wakeup_valid_T_1 = _alu_exe_unit_io_iresp_valid & _slow_wakeup_valid_T; // @[execution-units.scala:119:32]
wire _slow_wakeup_valid_T_2 = ~_alu_exe_unit_io_iresp_bits_uop_bypassable; // @[execution-units.scala:119:32]
wire _slow_wakeup_valid_T_3 = _slow_wakeup_valid_T_1 & _slow_wakeup_valid_T_2; // @[core.scala:832:42, :833:54, :834:33]
wire _T_93 = _alu_exe_unit_io_iresp_bits_uop_dst_rtype == 2'h0; // @[execution-units.scala:119:32]
wire _slow_wakeup_valid_T_4; // @[core.scala:835:57]
assign _slow_wakeup_valid_T_4 = _T_93; // @[core.scala:835:57]
wire _iregfile_io_write_ports_1_valid_T_2; // @[core.scala:1160:77]
assign _iregfile_io_write_ports_1_valid_T_2 = _T_93; // @[core.scala:835:57, :1160:77]
wire _rob_io_debug_wb_valids_1_T_2; // @[core.scala:1240:86]
assign _rob_io_debug_wb_valids_1_T_2 = _T_93; // @[core.scala:835:57, :1240:86]
assign _slow_wakeup_valid_T_5 = _slow_wakeup_valid_T_3 & _slow_wakeup_valid_T_4; // @[core.scala:833:54, :834:59, :835:57]
assign slow_wakeup_valid = _slow_wakeup_valid_T_5; // @[core.scala:815:29, :834:59]
wire _fast_wakeup_valid_T_15; // @[core.scala:827:52]
assign int_iss_wakeups_3_valid = fast_wakeup_1_valid; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_3_valid = fast_wakeup_1_valid; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_3_bits_uop_uopc = fast_wakeup_1_bits_uop_uopc; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_3_bits_uop_uopc = fast_wakeup_1_bits_uop_uopc; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_3_bits_uop_inst = fast_wakeup_1_bits_uop_inst; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_3_bits_uop_inst = fast_wakeup_1_bits_uop_inst; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_3_bits_uop_debug_inst = fast_wakeup_1_bits_uop_debug_inst; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_3_bits_uop_debug_inst = fast_wakeup_1_bits_uop_debug_inst; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_3_bits_uop_is_rvc = fast_wakeup_1_bits_uop_is_rvc; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_3_bits_uop_is_rvc = fast_wakeup_1_bits_uop_is_rvc; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_3_bits_uop_debug_pc = fast_wakeup_1_bits_uop_debug_pc; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_3_bits_uop_debug_pc = fast_wakeup_1_bits_uop_debug_pc; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_3_bits_uop_iq_type = fast_wakeup_1_bits_uop_iq_type; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_3_bits_uop_iq_type = fast_wakeup_1_bits_uop_iq_type; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_3_bits_uop_fu_code = fast_wakeup_1_bits_uop_fu_code; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_3_bits_uop_fu_code = fast_wakeup_1_bits_uop_fu_code; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_3_bits_uop_ctrl_br_type = fast_wakeup_1_bits_uop_ctrl_br_type; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_3_bits_uop_ctrl_br_type = fast_wakeup_1_bits_uop_ctrl_br_type; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_3_bits_uop_ctrl_op1_sel = fast_wakeup_1_bits_uop_ctrl_op1_sel; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_3_bits_uop_ctrl_op1_sel = fast_wakeup_1_bits_uop_ctrl_op1_sel; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_3_bits_uop_ctrl_op2_sel = fast_wakeup_1_bits_uop_ctrl_op2_sel; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_3_bits_uop_ctrl_op2_sel = fast_wakeup_1_bits_uop_ctrl_op2_sel; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_3_bits_uop_ctrl_imm_sel = fast_wakeup_1_bits_uop_ctrl_imm_sel; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_3_bits_uop_ctrl_imm_sel = fast_wakeup_1_bits_uop_ctrl_imm_sel; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_3_bits_uop_ctrl_op_fcn = fast_wakeup_1_bits_uop_ctrl_op_fcn; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_3_bits_uop_ctrl_op_fcn = fast_wakeup_1_bits_uop_ctrl_op_fcn; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_3_bits_uop_ctrl_fcn_dw = fast_wakeup_1_bits_uop_ctrl_fcn_dw; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_3_bits_uop_ctrl_fcn_dw = fast_wakeup_1_bits_uop_ctrl_fcn_dw; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_3_bits_uop_ctrl_csr_cmd = fast_wakeup_1_bits_uop_ctrl_csr_cmd; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_3_bits_uop_ctrl_csr_cmd = fast_wakeup_1_bits_uop_ctrl_csr_cmd; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_3_bits_uop_ctrl_is_load = fast_wakeup_1_bits_uop_ctrl_is_load; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_3_bits_uop_ctrl_is_load = fast_wakeup_1_bits_uop_ctrl_is_load; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_3_bits_uop_ctrl_is_sta = fast_wakeup_1_bits_uop_ctrl_is_sta; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_3_bits_uop_ctrl_is_sta = fast_wakeup_1_bits_uop_ctrl_is_sta; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_3_bits_uop_ctrl_is_std = fast_wakeup_1_bits_uop_ctrl_is_std; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_3_bits_uop_ctrl_is_std = fast_wakeup_1_bits_uop_ctrl_is_std; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_3_bits_uop_iw_state = fast_wakeup_1_bits_uop_iw_state; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_3_bits_uop_iw_state = fast_wakeup_1_bits_uop_iw_state; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_3_bits_uop_iw_p1_poisoned = fast_wakeup_1_bits_uop_iw_p1_poisoned; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_3_bits_uop_iw_p1_poisoned = fast_wakeup_1_bits_uop_iw_p1_poisoned; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_3_bits_uop_iw_p2_poisoned = fast_wakeup_1_bits_uop_iw_p2_poisoned; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_3_bits_uop_iw_p2_poisoned = fast_wakeup_1_bits_uop_iw_p2_poisoned; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_3_bits_uop_is_br = fast_wakeup_1_bits_uop_is_br; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_3_bits_uop_is_br = fast_wakeup_1_bits_uop_is_br; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_3_bits_uop_is_jalr = fast_wakeup_1_bits_uop_is_jalr; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_3_bits_uop_is_jalr = fast_wakeup_1_bits_uop_is_jalr; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_3_bits_uop_is_jal = fast_wakeup_1_bits_uop_is_jal; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_3_bits_uop_is_jal = fast_wakeup_1_bits_uop_is_jal; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_3_bits_uop_is_sfb = fast_wakeup_1_bits_uop_is_sfb; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_3_bits_uop_is_sfb = fast_wakeup_1_bits_uop_is_sfb; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_3_bits_uop_br_mask = fast_wakeup_1_bits_uop_br_mask; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_3_bits_uop_br_mask = fast_wakeup_1_bits_uop_br_mask; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_3_bits_uop_br_tag = fast_wakeup_1_bits_uop_br_tag; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_3_bits_uop_br_tag = fast_wakeup_1_bits_uop_br_tag; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_3_bits_uop_ftq_idx = fast_wakeup_1_bits_uop_ftq_idx; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_3_bits_uop_ftq_idx = fast_wakeup_1_bits_uop_ftq_idx; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_3_bits_uop_edge_inst = fast_wakeup_1_bits_uop_edge_inst; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_3_bits_uop_edge_inst = fast_wakeup_1_bits_uop_edge_inst; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_3_bits_uop_pc_lob = fast_wakeup_1_bits_uop_pc_lob; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_3_bits_uop_pc_lob = fast_wakeup_1_bits_uop_pc_lob; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_3_bits_uop_taken = fast_wakeup_1_bits_uop_taken; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_3_bits_uop_taken = fast_wakeup_1_bits_uop_taken; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_3_bits_uop_imm_packed = fast_wakeup_1_bits_uop_imm_packed; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_3_bits_uop_imm_packed = fast_wakeup_1_bits_uop_imm_packed; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_3_bits_uop_csr_addr = fast_wakeup_1_bits_uop_csr_addr; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_3_bits_uop_csr_addr = fast_wakeup_1_bits_uop_csr_addr; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_3_bits_uop_rob_idx = fast_wakeup_1_bits_uop_rob_idx; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_3_bits_uop_rob_idx = fast_wakeup_1_bits_uop_rob_idx; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_3_bits_uop_ldq_idx = fast_wakeup_1_bits_uop_ldq_idx; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_3_bits_uop_ldq_idx = fast_wakeup_1_bits_uop_ldq_idx; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_3_bits_uop_stq_idx = fast_wakeup_1_bits_uop_stq_idx; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_3_bits_uop_stq_idx = fast_wakeup_1_bits_uop_stq_idx; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_3_bits_uop_rxq_idx = fast_wakeup_1_bits_uop_rxq_idx; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_3_bits_uop_rxq_idx = fast_wakeup_1_bits_uop_rxq_idx; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_3_bits_uop_pdst = fast_wakeup_1_bits_uop_pdst; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_3_bits_uop_pdst = fast_wakeup_1_bits_uop_pdst; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_3_bits_uop_prs1 = fast_wakeup_1_bits_uop_prs1; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_3_bits_uop_prs1 = fast_wakeup_1_bits_uop_prs1; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_3_bits_uop_prs2 = fast_wakeup_1_bits_uop_prs2; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_3_bits_uop_prs2 = fast_wakeup_1_bits_uop_prs2; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_3_bits_uop_prs3 = fast_wakeup_1_bits_uop_prs3; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_3_bits_uop_prs3 = fast_wakeup_1_bits_uop_prs3; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_3_bits_uop_ppred = fast_wakeup_1_bits_uop_ppred; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_3_bits_uop_ppred = fast_wakeup_1_bits_uop_ppred; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_3_bits_uop_prs1_busy = fast_wakeup_1_bits_uop_prs1_busy; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_3_bits_uop_prs1_busy = fast_wakeup_1_bits_uop_prs1_busy; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_3_bits_uop_prs2_busy = fast_wakeup_1_bits_uop_prs2_busy; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_3_bits_uop_prs2_busy = fast_wakeup_1_bits_uop_prs2_busy; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_3_bits_uop_prs3_busy = fast_wakeup_1_bits_uop_prs3_busy; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_3_bits_uop_prs3_busy = fast_wakeup_1_bits_uop_prs3_busy; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_3_bits_uop_ppred_busy = fast_wakeup_1_bits_uop_ppred_busy; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_3_bits_uop_ppred_busy = fast_wakeup_1_bits_uop_ppred_busy; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_3_bits_uop_stale_pdst = fast_wakeup_1_bits_uop_stale_pdst; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_3_bits_uop_stale_pdst = fast_wakeup_1_bits_uop_stale_pdst; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_3_bits_uop_exception = fast_wakeup_1_bits_uop_exception; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_3_bits_uop_exception = fast_wakeup_1_bits_uop_exception; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_3_bits_uop_exc_cause = fast_wakeup_1_bits_uop_exc_cause; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_3_bits_uop_exc_cause = fast_wakeup_1_bits_uop_exc_cause; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_3_bits_uop_bypassable = fast_wakeup_1_bits_uop_bypassable; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_3_bits_uop_bypassable = fast_wakeup_1_bits_uop_bypassable; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_3_bits_uop_mem_cmd = fast_wakeup_1_bits_uop_mem_cmd; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_3_bits_uop_mem_cmd = fast_wakeup_1_bits_uop_mem_cmd; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_3_bits_uop_mem_size = fast_wakeup_1_bits_uop_mem_size; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_3_bits_uop_mem_size = fast_wakeup_1_bits_uop_mem_size; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_3_bits_uop_mem_signed = fast_wakeup_1_bits_uop_mem_signed; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_3_bits_uop_mem_signed = fast_wakeup_1_bits_uop_mem_signed; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_3_bits_uop_is_fence = fast_wakeup_1_bits_uop_is_fence; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_3_bits_uop_is_fence = fast_wakeup_1_bits_uop_is_fence; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_3_bits_uop_is_fencei = fast_wakeup_1_bits_uop_is_fencei; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_3_bits_uop_is_fencei = fast_wakeup_1_bits_uop_is_fencei; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_3_bits_uop_is_amo = fast_wakeup_1_bits_uop_is_amo; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_3_bits_uop_is_amo = fast_wakeup_1_bits_uop_is_amo; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_3_bits_uop_uses_ldq = fast_wakeup_1_bits_uop_uses_ldq; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_3_bits_uop_uses_ldq = fast_wakeup_1_bits_uop_uses_ldq; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_3_bits_uop_uses_stq = fast_wakeup_1_bits_uop_uses_stq; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_3_bits_uop_uses_stq = fast_wakeup_1_bits_uop_uses_stq; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_3_bits_uop_is_sys_pc2epc = fast_wakeup_1_bits_uop_is_sys_pc2epc; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_3_bits_uop_is_sys_pc2epc = fast_wakeup_1_bits_uop_is_sys_pc2epc; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_3_bits_uop_is_unique = fast_wakeup_1_bits_uop_is_unique; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_3_bits_uop_is_unique = fast_wakeup_1_bits_uop_is_unique; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_3_bits_uop_flush_on_commit = fast_wakeup_1_bits_uop_flush_on_commit; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_3_bits_uop_flush_on_commit = fast_wakeup_1_bits_uop_flush_on_commit; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_3_bits_uop_ldst_is_rs1 = fast_wakeup_1_bits_uop_ldst_is_rs1; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_3_bits_uop_ldst_is_rs1 = fast_wakeup_1_bits_uop_ldst_is_rs1; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_3_bits_uop_ldst = fast_wakeup_1_bits_uop_ldst; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_3_bits_uop_ldst = fast_wakeup_1_bits_uop_ldst; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_3_bits_uop_lrs1 = fast_wakeup_1_bits_uop_lrs1; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_3_bits_uop_lrs1 = fast_wakeup_1_bits_uop_lrs1; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_3_bits_uop_lrs2 = fast_wakeup_1_bits_uop_lrs2; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_3_bits_uop_lrs2 = fast_wakeup_1_bits_uop_lrs2; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_3_bits_uop_lrs3 = fast_wakeup_1_bits_uop_lrs3; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_3_bits_uop_lrs3 = fast_wakeup_1_bits_uop_lrs3; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_3_bits_uop_ldst_val = fast_wakeup_1_bits_uop_ldst_val; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_3_bits_uop_ldst_val = fast_wakeup_1_bits_uop_ldst_val; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_3_bits_uop_dst_rtype = fast_wakeup_1_bits_uop_dst_rtype; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_3_bits_uop_dst_rtype = fast_wakeup_1_bits_uop_dst_rtype; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_3_bits_uop_lrs1_rtype = fast_wakeup_1_bits_uop_lrs1_rtype; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_3_bits_uop_lrs1_rtype = fast_wakeup_1_bits_uop_lrs1_rtype; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_3_bits_uop_lrs2_rtype = fast_wakeup_1_bits_uop_lrs2_rtype; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_3_bits_uop_lrs2_rtype = fast_wakeup_1_bits_uop_lrs2_rtype; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_3_bits_uop_frs3_en = fast_wakeup_1_bits_uop_frs3_en; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_3_bits_uop_frs3_en = fast_wakeup_1_bits_uop_frs3_en; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_3_bits_uop_fp_val = fast_wakeup_1_bits_uop_fp_val; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_3_bits_uop_fp_val = fast_wakeup_1_bits_uop_fp_val; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_3_bits_uop_fp_single = fast_wakeup_1_bits_uop_fp_single; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_3_bits_uop_fp_single = fast_wakeup_1_bits_uop_fp_single; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_3_bits_uop_xcpt_pf_if = fast_wakeup_1_bits_uop_xcpt_pf_if; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_3_bits_uop_xcpt_pf_if = fast_wakeup_1_bits_uop_xcpt_pf_if; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_3_bits_uop_xcpt_ae_if = fast_wakeup_1_bits_uop_xcpt_ae_if; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_3_bits_uop_xcpt_ae_if = fast_wakeup_1_bits_uop_xcpt_ae_if; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_3_bits_uop_xcpt_ma_if = fast_wakeup_1_bits_uop_xcpt_ma_if; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_3_bits_uop_xcpt_ma_if = fast_wakeup_1_bits_uop_xcpt_ma_if; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_3_bits_uop_bp_debug_if = fast_wakeup_1_bits_uop_bp_debug_if; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_3_bits_uop_bp_debug_if = fast_wakeup_1_bits_uop_bp_debug_if; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_3_bits_uop_bp_xcpt_if = fast_wakeup_1_bits_uop_bp_xcpt_if; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_3_bits_uop_bp_xcpt_if = fast_wakeup_1_bits_uop_bp_xcpt_if; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_3_bits_uop_debug_fsrc = fast_wakeup_1_bits_uop_debug_fsrc; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_3_bits_uop_debug_fsrc = fast_wakeup_1_bits_uop_debug_fsrc; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_3_bits_uop_debug_tsrc = fast_wakeup_1_bits_uop_debug_tsrc; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_3_bits_uop_debug_tsrc = fast_wakeup_1_bits_uop_debug_tsrc; // @[core.scala:148:30, :814:29]
wire _slow_wakeup_valid_T_11; // @[core.scala:834:59]
assign int_iss_wakeups_4_valid = slow_wakeup_1_valid; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_4_valid = slow_wakeup_1_valid; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_4_bits_uop_uopc = slow_wakeup_1_bits_uop_uopc; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_4_bits_uop_uopc = slow_wakeup_1_bits_uop_uopc; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_4_bits_uop_inst = slow_wakeup_1_bits_uop_inst; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_4_bits_uop_inst = slow_wakeup_1_bits_uop_inst; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_4_bits_uop_debug_inst = slow_wakeup_1_bits_uop_debug_inst; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_4_bits_uop_debug_inst = slow_wakeup_1_bits_uop_debug_inst; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_4_bits_uop_is_rvc = slow_wakeup_1_bits_uop_is_rvc; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_4_bits_uop_is_rvc = slow_wakeup_1_bits_uop_is_rvc; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_4_bits_uop_debug_pc = slow_wakeup_1_bits_uop_debug_pc; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_4_bits_uop_debug_pc = slow_wakeup_1_bits_uop_debug_pc; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_4_bits_uop_iq_type = slow_wakeup_1_bits_uop_iq_type; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_4_bits_uop_iq_type = slow_wakeup_1_bits_uop_iq_type; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_4_bits_uop_fu_code = slow_wakeup_1_bits_uop_fu_code; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_4_bits_uop_fu_code = slow_wakeup_1_bits_uop_fu_code; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_4_bits_uop_ctrl_br_type = slow_wakeup_1_bits_uop_ctrl_br_type; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_4_bits_uop_ctrl_br_type = slow_wakeup_1_bits_uop_ctrl_br_type; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_4_bits_uop_ctrl_op1_sel = slow_wakeup_1_bits_uop_ctrl_op1_sel; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_4_bits_uop_ctrl_op1_sel = slow_wakeup_1_bits_uop_ctrl_op1_sel; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_4_bits_uop_ctrl_op2_sel = slow_wakeup_1_bits_uop_ctrl_op2_sel; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_4_bits_uop_ctrl_op2_sel = slow_wakeup_1_bits_uop_ctrl_op2_sel; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_4_bits_uop_ctrl_imm_sel = slow_wakeup_1_bits_uop_ctrl_imm_sel; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_4_bits_uop_ctrl_imm_sel = slow_wakeup_1_bits_uop_ctrl_imm_sel; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_4_bits_uop_ctrl_op_fcn = slow_wakeup_1_bits_uop_ctrl_op_fcn; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_4_bits_uop_ctrl_op_fcn = slow_wakeup_1_bits_uop_ctrl_op_fcn; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_4_bits_uop_ctrl_fcn_dw = slow_wakeup_1_bits_uop_ctrl_fcn_dw; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_4_bits_uop_ctrl_fcn_dw = slow_wakeup_1_bits_uop_ctrl_fcn_dw; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_4_bits_uop_ctrl_csr_cmd = slow_wakeup_1_bits_uop_ctrl_csr_cmd; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_4_bits_uop_ctrl_csr_cmd = slow_wakeup_1_bits_uop_ctrl_csr_cmd; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_4_bits_uop_ctrl_is_load = slow_wakeup_1_bits_uop_ctrl_is_load; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_4_bits_uop_ctrl_is_load = slow_wakeup_1_bits_uop_ctrl_is_load; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_4_bits_uop_ctrl_is_sta = slow_wakeup_1_bits_uop_ctrl_is_sta; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_4_bits_uop_ctrl_is_sta = slow_wakeup_1_bits_uop_ctrl_is_sta; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_4_bits_uop_ctrl_is_std = slow_wakeup_1_bits_uop_ctrl_is_std; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_4_bits_uop_ctrl_is_std = slow_wakeup_1_bits_uop_ctrl_is_std; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_4_bits_uop_iw_state = slow_wakeup_1_bits_uop_iw_state; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_4_bits_uop_iw_state = slow_wakeup_1_bits_uop_iw_state; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_4_bits_uop_iw_p1_poisoned = slow_wakeup_1_bits_uop_iw_p1_poisoned; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_4_bits_uop_iw_p1_poisoned = slow_wakeup_1_bits_uop_iw_p1_poisoned; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_4_bits_uop_iw_p2_poisoned = slow_wakeup_1_bits_uop_iw_p2_poisoned; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_4_bits_uop_iw_p2_poisoned = slow_wakeup_1_bits_uop_iw_p2_poisoned; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_4_bits_uop_is_br = slow_wakeup_1_bits_uop_is_br; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_4_bits_uop_is_br = slow_wakeup_1_bits_uop_is_br; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_4_bits_uop_is_jalr = slow_wakeup_1_bits_uop_is_jalr; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_4_bits_uop_is_jalr = slow_wakeup_1_bits_uop_is_jalr; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_4_bits_uop_is_jal = slow_wakeup_1_bits_uop_is_jal; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_4_bits_uop_is_jal = slow_wakeup_1_bits_uop_is_jal; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_4_bits_uop_is_sfb = slow_wakeup_1_bits_uop_is_sfb; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_4_bits_uop_is_sfb = slow_wakeup_1_bits_uop_is_sfb; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_4_bits_uop_br_mask = slow_wakeup_1_bits_uop_br_mask; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_4_bits_uop_br_mask = slow_wakeup_1_bits_uop_br_mask; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_4_bits_uop_br_tag = slow_wakeup_1_bits_uop_br_tag; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_4_bits_uop_br_tag = slow_wakeup_1_bits_uop_br_tag; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_4_bits_uop_ftq_idx = slow_wakeup_1_bits_uop_ftq_idx; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_4_bits_uop_ftq_idx = slow_wakeup_1_bits_uop_ftq_idx; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_4_bits_uop_edge_inst = slow_wakeup_1_bits_uop_edge_inst; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_4_bits_uop_edge_inst = slow_wakeup_1_bits_uop_edge_inst; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_4_bits_uop_pc_lob = slow_wakeup_1_bits_uop_pc_lob; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_4_bits_uop_pc_lob = slow_wakeup_1_bits_uop_pc_lob; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_4_bits_uop_taken = slow_wakeup_1_bits_uop_taken; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_4_bits_uop_taken = slow_wakeup_1_bits_uop_taken; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_4_bits_uop_imm_packed = slow_wakeup_1_bits_uop_imm_packed; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_4_bits_uop_imm_packed = slow_wakeup_1_bits_uop_imm_packed; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_4_bits_uop_csr_addr = slow_wakeup_1_bits_uop_csr_addr; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_4_bits_uop_csr_addr = slow_wakeup_1_bits_uop_csr_addr; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_4_bits_uop_rob_idx = slow_wakeup_1_bits_uop_rob_idx; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_4_bits_uop_rob_idx = slow_wakeup_1_bits_uop_rob_idx; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_4_bits_uop_ldq_idx = slow_wakeup_1_bits_uop_ldq_idx; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_4_bits_uop_ldq_idx = slow_wakeup_1_bits_uop_ldq_idx; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_4_bits_uop_stq_idx = slow_wakeup_1_bits_uop_stq_idx; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_4_bits_uop_stq_idx = slow_wakeup_1_bits_uop_stq_idx; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_4_bits_uop_rxq_idx = slow_wakeup_1_bits_uop_rxq_idx; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_4_bits_uop_rxq_idx = slow_wakeup_1_bits_uop_rxq_idx; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_4_bits_uop_pdst = slow_wakeup_1_bits_uop_pdst; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_4_bits_uop_pdst = slow_wakeup_1_bits_uop_pdst; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_4_bits_uop_prs1 = slow_wakeup_1_bits_uop_prs1; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_4_bits_uop_prs1 = slow_wakeup_1_bits_uop_prs1; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_4_bits_uop_prs2 = slow_wakeup_1_bits_uop_prs2; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_4_bits_uop_prs2 = slow_wakeup_1_bits_uop_prs2; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_4_bits_uop_prs3 = slow_wakeup_1_bits_uop_prs3; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_4_bits_uop_prs3 = slow_wakeup_1_bits_uop_prs3; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_4_bits_uop_ppred = slow_wakeup_1_bits_uop_ppred; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_4_bits_uop_ppred = slow_wakeup_1_bits_uop_ppred; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_4_bits_uop_prs1_busy = slow_wakeup_1_bits_uop_prs1_busy; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_4_bits_uop_prs1_busy = slow_wakeup_1_bits_uop_prs1_busy; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_4_bits_uop_prs2_busy = slow_wakeup_1_bits_uop_prs2_busy; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_4_bits_uop_prs2_busy = slow_wakeup_1_bits_uop_prs2_busy; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_4_bits_uop_prs3_busy = slow_wakeup_1_bits_uop_prs3_busy; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_4_bits_uop_prs3_busy = slow_wakeup_1_bits_uop_prs3_busy; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_4_bits_uop_ppred_busy = slow_wakeup_1_bits_uop_ppred_busy; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_4_bits_uop_ppred_busy = slow_wakeup_1_bits_uop_ppred_busy; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_4_bits_uop_stale_pdst = slow_wakeup_1_bits_uop_stale_pdst; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_4_bits_uop_stale_pdst = slow_wakeup_1_bits_uop_stale_pdst; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_4_bits_uop_exception = slow_wakeup_1_bits_uop_exception; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_4_bits_uop_exception = slow_wakeup_1_bits_uop_exception; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_4_bits_uop_exc_cause = slow_wakeup_1_bits_uop_exc_cause; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_4_bits_uop_exc_cause = slow_wakeup_1_bits_uop_exc_cause; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_4_bits_uop_bypassable = slow_wakeup_1_bits_uop_bypassable; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_4_bits_uop_bypassable = slow_wakeup_1_bits_uop_bypassable; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_4_bits_uop_mem_cmd = slow_wakeup_1_bits_uop_mem_cmd; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_4_bits_uop_mem_cmd = slow_wakeup_1_bits_uop_mem_cmd; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_4_bits_uop_mem_size = slow_wakeup_1_bits_uop_mem_size; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_4_bits_uop_mem_size = slow_wakeup_1_bits_uop_mem_size; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_4_bits_uop_mem_signed = slow_wakeup_1_bits_uop_mem_signed; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_4_bits_uop_mem_signed = slow_wakeup_1_bits_uop_mem_signed; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_4_bits_uop_is_fence = slow_wakeup_1_bits_uop_is_fence; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_4_bits_uop_is_fence = slow_wakeup_1_bits_uop_is_fence; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_4_bits_uop_is_fencei = slow_wakeup_1_bits_uop_is_fencei; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_4_bits_uop_is_fencei = slow_wakeup_1_bits_uop_is_fencei; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_4_bits_uop_is_amo = slow_wakeup_1_bits_uop_is_amo; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_4_bits_uop_is_amo = slow_wakeup_1_bits_uop_is_amo; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_4_bits_uop_uses_ldq = slow_wakeup_1_bits_uop_uses_ldq; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_4_bits_uop_uses_ldq = slow_wakeup_1_bits_uop_uses_ldq; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_4_bits_uop_uses_stq = slow_wakeup_1_bits_uop_uses_stq; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_4_bits_uop_uses_stq = slow_wakeup_1_bits_uop_uses_stq; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_4_bits_uop_is_sys_pc2epc = slow_wakeup_1_bits_uop_is_sys_pc2epc; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_4_bits_uop_is_sys_pc2epc = slow_wakeup_1_bits_uop_is_sys_pc2epc; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_4_bits_uop_is_unique = slow_wakeup_1_bits_uop_is_unique; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_4_bits_uop_is_unique = slow_wakeup_1_bits_uop_is_unique; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_4_bits_uop_flush_on_commit = slow_wakeup_1_bits_uop_flush_on_commit; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_4_bits_uop_flush_on_commit = slow_wakeup_1_bits_uop_flush_on_commit; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_4_bits_uop_ldst_is_rs1 = slow_wakeup_1_bits_uop_ldst_is_rs1; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_4_bits_uop_ldst_is_rs1 = slow_wakeup_1_bits_uop_ldst_is_rs1; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_4_bits_uop_ldst = slow_wakeup_1_bits_uop_ldst; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_4_bits_uop_ldst = slow_wakeup_1_bits_uop_ldst; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_4_bits_uop_lrs1 = slow_wakeup_1_bits_uop_lrs1; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_4_bits_uop_lrs1 = slow_wakeup_1_bits_uop_lrs1; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_4_bits_uop_lrs2 = slow_wakeup_1_bits_uop_lrs2; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_4_bits_uop_lrs2 = slow_wakeup_1_bits_uop_lrs2; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_4_bits_uop_lrs3 = slow_wakeup_1_bits_uop_lrs3; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_4_bits_uop_lrs3 = slow_wakeup_1_bits_uop_lrs3; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_4_bits_uop_ldst_val = slow_wakeup_1_bits_uop_ldst_val; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_4_bits_uop_ldst_val = slow_wakeup_1_bits_uop_ldst_val; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_4_bits_uop_dst_rtype = slow_wakeup_1_bits_uop_dst_rtype; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_4_bits_uop_dst_rtype = slow_wakeup_1_bits_uop_dst_rtype; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_4_bits_uop_lrs1_rtype = slow_wakeup_1_bits_uop_lrs1_rtype; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_4_bits_uop_lrs1_rtype = slow_wakeup_1_bits_uop_lrs1_rtype; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_4_bits_uop_lrs2_rtype = slow_wakeup_1_bits_uop_lrs2_rtype; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_4_bits_uop_lrs2_rtype = slow_wakeup_1_bits_uop_lrs2_rtype; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_4_bits_uop_frs3_en = slow_wakeup_1_bits_uop_frs3_en; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_4_bits_uop_frs3_en = slow_wakeup_1_bits_uop_frs3_en; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_4_bits_uop_fp_val = slow_wakeup_1_bits_uop_fp_val; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_4_bits_uop_fp_val = slow_wakeup_1_bits_uop_fp_val; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_4_bits_uop_fp_single = slow_wakeup_1_bits_uop_fp_single; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_4_bits_uop_fp_single = slow_wakeup_1_bits_uop_fp_single; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_4_bits_uop_xcpt_pf_if = slow_wakeup_1_bits_uop_xcpt_pf_if; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_4_bits_uop_xcpt_pf_if = slow_wakeup_1_bits_uop_xcpt_pf_if; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_4_bits_uop_xcpt_ae_if = slow_wakeup_1_bits_uop_xcpt_ae_if; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_4_bits_uop_xcpt_ae_if = slow_wakeup_1_bits_uop_xcpt_ae_if; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_4_bits_uop_xcpt_ma_if = slow_wakeup_1_bits_uop_xcpt_ma_if; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_4_bits_uop_xcpt_ma_if = slow_wakeup_1_bits_uop_xcpt_ma_if; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_4_bits_uop_bp_debug_if = slow_wakeup_1_bits_uop_bp_debug_if; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_4_bits_uop_bp_debug_if = slow_wakeup_1_bits_uop_bp_debug_if; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_4_bits_uop_bp_xcpt_if = slow_wakeup_1_bits_uop_bp_xcpt_if; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_4_bits_uop_bp_xcpt_if = slow_wakeup_1_bits_uop_bp_xcpt_if; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_4_bits_uop_debug_fsrc = slow_wakeup_1_bits_uop_debug_fsrc; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_4_bits_uop_debug_fsrc = slow_wakeup_1_bits_uop_debug_fsrc; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_4_bits_uop_debug_tsrc = slow_wakeup_1_bits_uop_debug_tsrc; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_4_bits_uop_debug_tsrc = slow_wakeup_1_bits_uop_debug_tsrc; // @[core.scala:148:30, :815:29]
wire _T_124 = _alu_exe_unit_1_io_iresp_bits_uop_dst_rtype != 2'h2; // @[execution-units.scala:119:32]
wire _slow_wakeup_valid_T_6; // @[micro-op.scala:149:36]
assign _slow_wakeup_valid_T_6 = _T_124; // @[micro-op.scala:149:36]
wire _iregfile_io_write_ports_2_valid_T; // @[micro-op.scala:149:36]
assign _iregfile_io_write_ports_2_valid_T = _T_124; // @[micro-op.scala:149:36]
wire _rob_io_debug_wb_valids_2_T; // @[micro-op.scala:149:36]
assign _rob_io_debug_wb_valids_2_T = _T_124; // @[micro-op.scala:149:36]
wire _fast_wakeup_valid_T_8 = iss_valids_2 & iss_uops_2_bypassable; // @[core.scala:172:24, :173:24, :824:45]
wire _fast_wakeup_valid_T_9 = iss_uops_2_dst_rtype == 2'h0; // @[core.scala:173:24, :826:53]
wire _fast_wakeup_valid_T_10 = _fast_wakeup_valid_T_8 & _fast_wakeup_valid_T_9; // @[core.scala:824:45, :825:54, :826:53]
wire _fast_wakeup_valid_T_11 = _fast_wakeup_valid_T_10 & iss_uops_2_ldst_val; // @[core.scala:173:24, :825:54, :826:64]
wire _GEN_40 = iss_uops_2_iw_p1_poisoned | iss_uops_2_iw_p2_poisoned; // @[core.scala:173:24, :828:79]
wire _fast_wakeup_valid_T_12; // @[core.scala:828:79]
assign _fast_wakeup_valid_T_12 = _GEN_40; // @[core.scala:828:79]
wire _iregister_read_io_iss_valids_2_T; // @[core.scala:981:72]
assign _iregister_read_io_iss_valids_2_T = _GEN_40; // @[core.scala:828:79, :981:72]
wire _fast_wakeup_valid_T_13 = io_lsu_ld_miss_0 & _fast_wakeup_valid_T_12; // @[core.scala:51:7, :828:{48,79}]
wire _fast_wakeup_valid_T_14 = ~_fast_wakeup_valid_T_13; // @[core.scala:828:{31,48}]
assign _fast_wakeup_valid_T_15 = _fast_wakeup_valid_T_11 & _fast_wakeup_valid_T_14; // @[core.scala:826:64, :827:52, :828:31]
assign fast_wakeup_1_valid = _fast_wakeup_valid_T_15; // @[core.scala:814:29, :827:52]
wire _slow_wakeup_valid_T_7 = _alu_exe_unit_1_io_iresp_valid & _slow_wakeup_valid_T_6; // @[execution-units.scala:119:32]
wire _slow_wakeup_valid_T_8 = ~_alu_exe_unit_1_io_iresp_bits_uop_bypassable; // @[execution-units.scala:119:32]
wire _slow_wakeup_valid_T_9 = _slow_wakeup_valid_T_7 & _slow_wakeup_valid_T_8; // @[core.scala:832:42, :833:54, :834:33]
wire _T_118 = _alu_exe_unit_1_io_iresp_bits_uop_dst_rtype == 2'h0; // @[execution-units.scala:119:32]
wire _slow_wakeup_valid_T_10; // @[core.scala:835:57]
assign _slow_wakeup_valid_T_10 = _T_118; // @[core.scala:835:57]
wire _iregfile_io_write_ports_2_valid_T_2; // @[core.scala:1160:77]
assign _iregfile_io_write_ports_2_valid_T_2 = _T_118; // @[core.scala:835:57, :1160:77]
wire _rob_io_debug_wb_valids_2_T_2; // @[core.scala:1240:86]
assign _rob_io_debug_wb_valids_2_T_2 = _T_118; // @[core.scala:835:57, :1240:86]
assign _slow_wakeup_valid_T_11 = _slow_wakeup_valid_T_9 & _slow_wakeup_valid_T_10; // @[core.scala:833:54, :834:59, :835:57]
assign slow_wakeup_1_valid = _slow_wakeup_valid_T_11; // @[core.scala:815:29, :834:59]
wire _fast_wakeup_valid_T_23; // @[core.scala:827:52]
assign int_iss_wakeups_5_valid = fast_wakeup_2_valid; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_5_valid = fast_wakeup_2_valid; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_5_bits_uop_uopc = fast_wakeup_2_bits_uop_uopc; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_5_bits_uop_uopc = fast_wakeup_2_bits_uop_uopc; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_5_bits_uop_inst = fast_wakeup_2_bits_uop_inst; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_5_bits_uop_inst = fast_wakeup_2_bits_uop_inst; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_5_bits_uop_debug_inst = fast_wakeup_2_bits_uop_debug_inst; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_5_bits_uop_debug_inst = fast_wakeup_2_bits_uop_debug_inst; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_5_bits_uop_is_rvc = fast_wakeup_2_bits_uop_is_rvc; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_5_bits_uop_is_rvc = fast_wakeup_2_bits_uop_is_rvc; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_5_bits_uop_debug_pc = fast_wakeup_2_bits_uop_debug_pc; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_5_bits_uop_debug_pc = fast_wakeup_2_bits_uop_debug_pc; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_5_bits_uop_iq_type = fast_wakeup_2_bits_uop_iq_type; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_5_bits_uop_iq_type = fast_wakeup_2_bits_uop_iq_type; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_5_bits_uop_fu_code = fast_wakeup_2_bits_uop_fu_code; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_5_bits_uop_fu_code = fast_wakeup_2_bits_uop_fu_code; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_5_bits_uop_ctrl_br_type = fast_wakeup_2_bits_uop_ctrl_br_type; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_5_bits_uop_ctrl_br_type = fast_wakeup_2_bits_uop_ctrl_br_type; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_5_bits_uop_ctrl_op1_sel = fast_wakeup_2_bits_uop_ctrl_op1_sel; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_5_bits_uop_ctrl_op1_sel = fast_wakeup_2_bits_uop_ctrl_op1_sel; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_5_bits_uop_ctrl_op2_sel = fast_wakeup_2_bits_uop_ctrl_op2_sel; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_5_bits_uop_ctrl_op2_sel = fast_wakeup_2_bits_uop_ctrl_op2_sel; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_5_bits_uop_ctrl_imm_sel = fast_wakeup_2_bits_uop_ctrl_imm_sel; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_5_bits_uop_ctrl_imm_sel = fast_wakeup_2_bits_uop_ctrl_imm_sel; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_5_bits_uop_ctrl_op_fcn = fast_wakeup_2_bits_uop_ctrl_op_fcn; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_5_bits_uop_ctrl_op_fcn = fast_wakeup_2_bits_uop_ctrl_op_fcn; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_5_bits_uop_ctrl_fcn_dw = fast_wakeup_2_bits_uop_ctrl_fcn_dw; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_5_bits_uop_ctrl_fcn_dw = fast_wakeup_2_bits_uop_ctrl_fcn_dw; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_5_bits_uop_ctrl_csr_cmd = fast_wakeup_2_bits_uop_ctrl_csr_cmd; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_5_bits_uop_ctrl_csr_cmd = fast_wakeup_2_bits_uop_ctrl_csr_cmd; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_5_bits_uop_ctrl_is_load = fast_wakeup_2_bits_uop_ctrl_is_load; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_5_bits_uop_ctrl_is_load = fast_wakeup_2_bits_uop_ctrl_is_load; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_5_bits_uop_ctrl_is_sta = fast_wakeup_2_bits_uop_ctrl_is_sta; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_5_bits_uop_ctrl_is_sta = fast_wakeup_2_bits_uop_ctrl_is_sta; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_5_bits_uop_ctrl_is_std = fast_wakeup_2_bits_uop_ctrl_is_std; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_5_bits_uop_ctrl_is_std = fast_wakeup_2_bits_uop_ctrl_is_std; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_5_bits_uop_iw_state = fast_wakeup_2_bits_uop_iw_state; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_5_bits_uop_iw_state = fast_wakeup_2_bits_uop_iw_state; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_5_bits_uop_iw_p1_poisoned = fast_wakeup_2_bits_uop_iw_p1_poisoned; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_5_bits_uop_iw_p1_poisoned = fast_wakeup_2_bits_uop_iw_p1_poisoned; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_5_bits_uop_iw_p2_poisoned = fast_wakeup_2_bits_uop_iw_p2_poisoned; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_5_bits_uop_iw_p2_poisoned = fast_wakeup_2_bits_uop_iw_p2_poisoned; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_5_bits_uop_is_br = fast_wakeup_2_bits_uop_is_br; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_5_bits_uop_is_br = fast_wakeup_2_bits_uop_is_br; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_5_bits_uop_is_jalr = fast_wakeup_2_bits_uop_is_jalr; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_5_bits_uop_is_jalr = fast_wakeup_2_bits_uop_is_jalr; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_5_bits_uop_is_jal = fast_wakeup_2_bits_uop_is_jal; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_5_bits_uop_is_jal = fast_wakeup_2_bits_uop_is_jal; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_5_bits_uop_is_sfb = fast_wakeup_2_bits_uop_is_sfb; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_5_bits_uop_is_sfb = fast_wakeup_2_bits_uop_is_sfb; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_5_bits_uop_br_mask = fast_wakeup_2_bits_uop_br_mask; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_5_bits_uop_br_mask = fast_wakeup_2_bits_uop_br_mask; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_5_bits_uop_br_tag = fast_wakeup_2_bits_uop_br_tag; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_5_bits_uop_br_tag = fast_wakeup_2_bits_uop_br_tag; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_5_bits_uop_ftq_idx = fast_wakeup_2_bits_uop_ftq_idx; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_5_bits_uop_ftq_idx = fast_wakeup_2_bits_uop_ftq_idx; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_5_bits_uop_edge_inst = fast_wakeup_2_bits_uop_edge_inst; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_5_bits_uop_edge_inst = fast_wakeup_2_bits_uop_edge_inst; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_5_bits_uop_pc_lob = fast_wakeup_2_bits_uop_pc_lob; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_5_bits_uop_pc_lob = fast_wakeup_2_bits_uop_pc_lob; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_5_bits_uop_taken = fast_wakeup_2_bits_uop_taken; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_5_bits_uop_taken = fast_wakeup_2_bits_uop_taken; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_5_bits_uop_imm_packed = fast_wakeup_2_bits_uop_imm_packed; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_5_bits_uop_imm_packed = fast_wakeup_2_bits_uop_imm_packed; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_5_bits_uop_csr_addr = fast_wakeup_2_bits_uop_csr_addr; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_5_bits_uop_csr_addr = fast_wakeup_2_bits_uop_csr_addr; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_5_bits_uop_rob_idx = fast_wakeup_2_bits_uop_rob_idx; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_5_bits_uop_rob_idx = fast_wakeup_2_bits_uop_rob_idx; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_5_bits_uop_ldq_idx = fast_wakeup_2_bits_uop_ldq_idx; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_5_bits_uop_ldq_idx = fast_wakeup_2_bits_uop_ldq_idx; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_5_bits_uop_stq_idx = fast_wakeup_2_bits_uop_stq_idx; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_5_bits_uop_stq_idx = fast_wakeup_2_bits_uop_stq_idx; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_5_bits_uop_rxq_idx = fast_wakeup_2_bits_uop_rxq_idx; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_5_bits_uop_rxq_idx = fast_wakeup_2_bits_uop_rxq_idx; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_5_bits_uop_pdst = fast_wakeup_2_bits_uop_pdst; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_5_bits_uop_pdst = fast_wakeup_2_bits_uop_pdst; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_5_bits_uop_prs1 = fast_wakeup_2_bits_uop_prs1; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_5_bits_uop_prs1 = fast_wakeup_2_bits_uop_prs1; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_5_bits_uop_prs2 = fast_wakeup_2_bits_uop_prs2; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_5_bits_uop_prs2 = fast_wakeup_2_bits_uop_prs2; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_5_bits_uop_prs3 = fast_wakeup_2_bits_uop_prs3; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_5_bits_uop_prs3 = fast_wakeup_2_bits_uop_prs3; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_5_bits_uop_ppred = fast_wakeup_2_bits_uop_ppred; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_5_bits_uop_ppred = fast_wakeup_2_bits_uop_ppred; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_5_bits_uop_prs1_busy = fast_wakeup_2_bits_uop_prs1_busy; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_5_bits_uop_prs1_busy = fast_wakeup_2_bits_uop_prs1_busy; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_5_bits_uop_prs2_busy = fast_wakeup_2_bits_uop_prs2_busy; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_5_bits_uop_prs2_busy = fast_wakeup_2_bits_uop_prs2_busy; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_5_bits_uop_prs3_busy = fast_wakeup_2_bits_uop_prs3_busy; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_5_bits_uop_prs3_busy = fast_wakeup_2_bits_uop_prs3_busy; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_5_bits_uop_ppred_busy = fast_wakeup_2_bits_uop_ppred_busy; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_5_bits_uop_ppred_busy = fast_wakeup_2_bits_uop_ppred_busy; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_5_bits_uop_stale_pdst = fast_wakeup_2_bits_uop_stale_pdst; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_5_bits_uop_stale_pdst = fast_wakeup_2_bits_uop_stale_pdst; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_5_bits_uop_exception = fast_wakeup_2_bits_uop_exception; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_5_bits_uop_exception = fast_wakeup_2_bits_uop_exception; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_5_bits_uop_exc_cause = fast_wakeup_2_bits_uop_exc_cause; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_5_bits_uop_exc_cause = fast_wakeup_2_bits_uop_exc_cause; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_5_bits_uop_bypassable = fast_wakeup_2_bits_uop_bypassable; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_5_bits_uop_bypassable = fast_wakeup_2_bits_uop_bypassable; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_5_bits_uop_mem_cmd = fast_wakeup_2_bits_uop_mem_cmd; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_5_bits_uop_mem_cmd = fast_wakeup_2_bits_uop_mem_cmd; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_5_bits_uop_mem_size = fast_wakeup_2_bits_uop_mem_size; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_5_bits_uop_mem_size = fast_wakeup_2_bits_uop_mem_size; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_5_bits_uop_mem_signed = fast_wakeup_2_bits_uop_mem_signed; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_5_bits_uop_mem_signed = fast_wakeup_2_bits_uop_mem_signed; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_5_bits_uop_is_fence = fast_wakeup_2_bits_uop_is_fence; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_5_bits_uop_is_fence = fast_wakeup_2_bits_uop_is_fence; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_5_bits_uop_is_fencei = fast_wakeup_2_bits_uop_is_fencei; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_5_bits_uop_is_fencei = fast_wakeup_2_bits_uop_is_fencei; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_5_bits_uop_is_amo = fast_wakeup_2_bits_uop_is_amo; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_5_bits_uop_is_amo = fast_wakeup_2_bits_uop_is_amo; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_5_bits_uop_uses_ldq = fast_wakeup_2_bits_uop_uses_ldq; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_5_bits_uop_uses_ldq = fast_wakeup_2_bits_uop_uses_ldq; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_5_bits_uop_uses_stq = fast_wakeup_2_bits_uop_uses_stq; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_5_bits_uop_uses_stq = fast_wakeup_2_bits_uop_uses_stq; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_5_bits_uop_is_sys_pc2epc = fast_wakeup_2_bits_uop_is_sys_pc2epc; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_5_bits_uop_is_sys_pc2epc = fast_wakeup_2_bits_uop_is_sys_pc2epc; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_5_bits_uop_is_unique = fast_wakeup_2_bits_uop_is_unique; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_5_bits_uop_is_unique = fast_wakeup_2_bits_uop_is_unique; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_5_bits_uop_flush_on_commit = fast_wakeup_2_bits_uop_flush_on_commit; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_5_bits_uop_flush_on_commit = fast_wakeup_2_bits_uop_flush_on_commit; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_5_bits_uop_ldst_is_rs1 = fast_wakeup_2_bits_uop_ldst_is_rs1; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_5_bits_uop_ldst_is_rs1 = fast_wakeup_2_bits_uop_ldst_is_rs1; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_5_bits_uop_ldst = fast_wakeup_2_bits_uop_ldst; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_5_bits_uop_ldst = fast_wakeup_2_bits_uop_ldst; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_5_bits_uop_lrs1 = fast_wakeup_2_bits_uop_lrs1; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_5_bits_uop_lrs1 = fast_wakeup_2_bits_uop_lrs1; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_5_bits_uop_lrs2 = fast_wakeup_2_bits_uop_lrs2; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_5_bits_uop_lrs2 = fast_wakeup_2_bits_uop_lrs2; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_5_bits_uop_lrs3 = fast_wakeup_2_bits_uop_lrs3; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_5_bits_uop_lrs3 = fast_wakeup_2_bits_uop_lrs3; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_5_bits_uop_ldst_val = fast_wakeup_2_bits_uop_ldst_val; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_5_bits_uop_ldst_val = fast_wakeup_2_bits_uop_ldst_val; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_5_bits_uop_dst_rtype = fast_wakeup_2_bits_uop_dst_rtype; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_5_bits_uop_dst_rtype = fast_wakeup_2_bits_uop_dst_rtype; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_5_bits_uop_lrs1_rtype = fast_wakeup_2_bits_uop_lrs1_rtype; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_5_bits_uop_lrs1_rtype = fast_wakeup_2_bits_uop_lrs1_rtype; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_5_bits_uop_lrs2_rtype = fast_wakeup_2_bits_uop_lrs2_rtype; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_5_bits_uop_lrs2_rtype = fast_wakeup_2_bits_uop_lrs2_rtype; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_5_bits_uop_frs3_en = fast_wakeup_2_bits_uop_frs3_en; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_5_bits_uop_frs3_en = fast_wakeup_2_bits_uop_frs3_en; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_5_bits_uop_fp_val = fast_wakeup_2_bits_uop_fp_val; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_5_bits_uop_fp_val = fast_wakeup_2_bits_uop_fp_val; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_5_bits_uop_fp_single = fast_wakeup_2_bits_uop_fp_single; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_5_bits_uop_fp_single = fast_wakeup_2_bits_uop_fp_single; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_5_bits_uop_xcpt_pf_if = fast_wakeup_2_bits_uop_xcpt_pf_if; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_5_bits_uop_xcpt_pf_if = fast_wakeup_2_bits_uop_xcpt_pf_if; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_5_bits_uop_xcpt_ae_if = fast_wakeup_2_bits_uop_xcpt_ae_if; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_5_bits_uop_xcpt_ae_if = fast_wakeup_2_bits_uop_xcpt_ae_if; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_5_bits_uop_xcpt_ma_if = fast_wakeup_2_bits_uop_xcpt_ma_if; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_5_bits_uop_xcpt_ma_if = fast_wakeup_2_bits_uop_xcpt_ma_if; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_5_bits_uop_bp_debug_if = fast_wakeup_2_bits_uop_bp_debug_if; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_5_bits_uop_bp_debug_if = fast_wakeup_2_bits_uop_bp_debug_if; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_5_bits_uop_bp_xcpt_if = fast_wakeup_2_bits_uop_bp_xcpt_if; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_5_bits_uop_bp_xcpt_if = fast_wakeup_2_bits_uop_bp_xcpt_if; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_5_bits_uop_debug_fsrc = fast_wakeup_2_bits_uop_debug_fsrc; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_5_bits_uop_debug_fsrc = fast_wakeup_2_bits_uop_debug_fsrc; // @[core.scala:148:30, :814:29]
assign int_iss_wakeups_5_bits_uop_debug_tsrc = fast_wakeup_2_bits_uop_debug_tsrc; // @[core.scala:147:30, :814:29]
assign int_ren_wakeups_5_bits_uop_debug_tsrc = fast_wakeup_2_bits_uop_debug_tsrc; // @[core.scala:148:30, :814:29]
wire _slow_wakeup_valid_T_17; // @[core.scala:834:59]
assign int_iss_wakeups_6_valid = slow_wakeup_2_valid; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_6_valid = slow_wakeup_2_valid; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_6_bits_uop_uopc = slow_wakeup_2_bits_uop_uopc; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_6_bits_uop_uopc = slow_wakeup_2_bits_uop_uopc; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_6_bits_uop_inst = slow_wakeup_2_bits_uop_inst; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_6_bits_uop_inst = slow_wakeup_2_bits_uop_inst; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_6_bits_uop_debug_inst = slow_wakeup_2_bits_uop_debug_inst; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_6_bits_uop_debug_inst = slow_wakeup_2_bits_uop_debug_inst; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_6_bits_uop_is_rvc = slow_wakeup_2_bits_uop_is_rvc; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_6_bits_uop_is_rvc = slow_wakeup_2_bits_uop_is_rvc; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_6_bits_uop_debug_pc = slow_wakeup_2_bits_uop_debug_pc; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_6_bits_uop_debug_pc = slow_wakeup_2_bits_uop_debug_pc; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_6_bits_uop_iq_type = slow_wakeup_2_bits_uop_iq_type; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_6_bits_uop_iq_type = slow_wakeup_2_bits_uop_iq_type; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_6_bits_uop_fu_code = slow_wakeup_2_bits_uop_fu_code; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_6_bits_uop_fu_code = slow_wakeup_2_bits_uop_fu_code; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_6_bits_uop_ctrl_br_type = slow_wakeup_2_bits_uop_ctrl_br_type; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_6_bits_uop_ctrl_br_type = slow_wakeup_2_bits_uop_ctrl_br_type; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_6_bits_uop_ctrl_op1_sel = slow_wakeup_2_bits_uop_ctrl_op1_sel; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_6_bits_uop_ctrl_op1_sel = slow_wakeup_2_bits_uop_ctrl_op1_sel; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_6_bits_uop_ctrl_op2_sel = slow_wakeup_2_bits_uop_ctrl_op2_sel; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_6_bits_uop_ctrl_op2_sel = slow_wakeup_2_bits_uop_ctrl_op2_sel; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_6_bits_uop_ctrl_imm_sel = slow_wakeup_2_bits_uop_ctrl_imm_sel; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_6_bits_uop_ctrl_imm_sel = slow_wakeup_2_bits_uop_ctrl_imm_sel; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_6_bits_uop_ctrl_op_fcn = slow_wakeup_2_bits_uop_ctrl_op_fcn; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_6_bits_uop_ctrl_op_fcn = slow_wakeup_2_bits_uop_ctrl_op_fcn; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_6_bits_uop_ctrl_fcn_dw = slow_wakeup_2_bits_uop_ctrl_fcn_dw; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_6_bits_uop_ctrl_fcn_dw = slow_wakeup_2_bits_uop_ctrl_fcn_dw; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_6_bits_uop_ctrl_csr_cmd = slow_wakeup_2_bits_uop_ctrl_csr_cmd; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_6_bits_uop_ctrl_csr_cmd = slow_wakeup_2_bits_uop_ctrl_csr_cmd; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_6_bits_uop_ctrl_is_load = slow_wakeup_2_bits_uop_ctrl_is_load; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_6_bits_uop_ctrl_is_load = slow_wakeup_2_bits_uop_ctrl_is_load; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_6_bits_uop_ctrl_is_sta = slow_wakeup_2_bits_uop_ctrl_is_sta; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_6_bits_uop_ctrl_is_sta = slow_wakeup_2_bits_uop_ctrl_is_sta; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_6_bits_uop_ctrl_is_std = slow_wakeup_2_bits_uop_ctrl_is_std; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_6_bits_uop_ctrl_is_std = slow_wakeup_2_bits_uop_ctrl_is_std; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_6_bits_uop_iw_state = slow_wakeup_2_bits_uop_iw_state; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_6_bits_uop_iw_state = slow_wakeup_2_bits_uop_iw_state; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_6_bits_uop_iw_p1_poisoned = slow_wakeup_2_bits_uop_iw_p1_poisoned; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_6_bits_uop_iw_p1_poisoned = slow_wakeup_2_bits_uop_iw_p1_poisoned; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_6_bits_uop_iw_p2_poisoned = slow_wakeup_2_bits_uop_iw_p2_poisoned; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_6_bits_uop_iw_p2_poisoned = slow_wakeup_2_bits_uop_iw_p2_poisoned; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_6_bits_uop_is_br = slow_wakeup_2_bits_uop_is_br; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_6_bits_uop_is_br = slow_wakeup_2_bits_uop_is_br; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_6_bits_uop_is_jalr = slow_wakeup_2_bits_uop_is_jalr; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_6_bits_uop_is_jalr = slow_wakeup_2_bits_uop_is_jalr; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_6_bits_uop_is_jal = slow_wakeup_2_bits_uop_is_jal; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_6_bits_uop_is_jal = slow_wakeup_2_bits_uop_is_jal; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_6_bits_uop_is_sfb = slow_wakeup_2_bits_uop_is_sfb; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_6_bits_uop_is_sfb = slow_wakeup_2_bits_uop_is_sfb; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_6_bits_uop_br_mask = slow_wakeup_2_bits_uop_br_mask; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_6_bits_uop_br_mask = slow_wakeup_2_bits_uop_br_mask; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_6_bits_uop_br_tag = slow_wakeup_2_bits_uop_br_tag; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_6_bits_uop_br_tag = slow_wakeup_2_bits_uop_br_tag; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_6_bits_uop_ftq_idx = slow_wakeup_2_bits_uop_ftq_idx; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_6_bits_uop_ftq_idx = slow_wakeup_2_bits_uop_ftq_idx; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_6_bits_uop_edge_inst = slow_wakeup_2_bits_uop_edge_inst; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_6_bits_uop_edge_inst = slow_wakeup_2_bits_uop_edge_inst; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_6_bits_uop_pc_lob = slow_wakeup_2_bits_uop_pc_lob; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_6_bits_uop_pc_lob = slow_wakeup_2_bits_uop_pc_lob; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_6_bits_uop_taken = slow_wakeup_2_bits_uop_taken; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_6_bits_uop_taken = slow_wakeup_2_bits_uop_taken; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_6_bits_uop_imm_packed = slow_wakeup_2_bits_uop_imm_packed; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_6_bits_uop_imm_packed = slow_wakeup_2_bits_uop_imm_packed; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_6_bits_uop_csr_addr = slow_wakeup_2_bits_uop_csr_addr; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_6_bits_uop_csr_addr = slow_wakeup_2_bits_uop_csr_addr; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_6_bits_uop_rob_idx = slow_wakeup_2_bits_uop_rob_idx; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_6_bits_uop_rob_idx = slow_wakeup_2_bits_uop_rob_idx; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_6_bits_uop_ldq_idx = slow_wakeup_2_bits_uop_ldq_idx; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_6_bits_uop_ldq_idx = slow_wakeup_2_bits_uop_ldq_idx; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_6_bits_uop_stq_idx = slow_wakeup_2_bits_uop_stq_idx; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_6_bits_uop_stq_idx = slow_wakeup_2_bits_uop_stq_idx; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_6_bits_uop_rxq_idx = slow_wakeup_2_bits_uop_rxq_idx; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_6_bits_uop_rxq_idx = slow_wakeup_2_bits_uop_rxq_idx; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_6_bits_uop_pdst = slow_wakeup_2_bits_uop_pdst; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_6_bits_uop_pdst = slow_wakeup_2_bits_uop_pdst; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_6_bits_uop_prs1 = slow_wakeup_2_bits_uop_prs1; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_6_bits_uop_prs1 = slow_wakeup_2_bits_uop_prs1; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_6_bits_uop_prs2 = slow_wakeup_2_bits_uop_prs2; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_6_bits_uop_prs2 = slow_wakeup_2_bits_uop_prs2; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_6_bits_uop_prs3 = slow_wakeup_2_bits_uop_prs3; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_6_bits_uop_prs3 = slow_wakeup_2_bits_uop_prs3; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_6_bits_uop_ppred = slow_wakeup_2_bits_uop_ppred; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_6_bits_uop_ppred = slow_wakeup_2_bits_uop_ppred; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_6_bits_uop_prs1_busy = slow_wakeup_2_bits_uop_prs1_busy; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_6_bits_uop_prs1_busy = slow_wakeup_2_bits_uop_prs1_busy; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_6_bits_uop_prs2_busy = slow_wakeup_2_bits_uop_prs2_busy; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_6_bits_uop_prs2_busy = slow_wakeup_2_bits_uop_prs2_busy; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_6_bits_uop_prs3_busy = slow_wakeup_2_bits_uop_prs3_busy; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_6_bits_uop_prs3_busy = slow_wakeup_2_bits_uop_prs3_busy; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_6_bits_uop_ppred_busy = slow_wakeup_2_bits_uop_ppred_busy; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_6_bits_uop_ppred_busy = slow_wakeup_2_bits_uop_ppred_busy; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_6_bits_uop_stale_pdst = slow_wakeup_2_bits_uop_stale_pdst; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_6_bits_uop_stale_pdst = slow_wakeup_2_bits_uop_stale_pdst; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_6_bits_uop_exception = slow_wakeup_2_bits_uop_exception; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_6_bits_uop_exception = slow_wakeup_2_bits_uop_exception; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_6_bits_uop_exc_cause = slow_wakeup_2_bits_uop_exc_cause; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_6_bits_uop_exc_cause = slow_wakeup_2_bits_uop_exc_cause; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_6_bits_uop_bypassable = slow_wakeup_2_bits_uop_bypassable; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_6_bits_uop_bypassable = slow_wakeup_2_bits_uop_bypassable; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_6_bits_uop_mem_cmd = slow_wakeup_2_bits_uop_mem_cmd; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_6_bits_uop_mem_cmd = slow_wakeup_2_bits_uop_mem_cmd; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_6_bits_uop_mem_size = slow_wakeup_2_bits_uop_mem_size; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_6_bits_uop_mem_size = slow_wakeup_2_bits_uop_mem_size; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_6_bits_uop_mem_signed = slow_wakeup_2_bits_uop_mem_signed; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_6_bits_uop_mem_signed = slow_wakeup_2_bits_uop_mem_signed; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_6_bits_uop_is_fence = slow_wakeup_2_bits_uop_is_fence; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_6_bits_uop_is_fence = slow_wakeup_2_bits_uop_is_fence; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_6_bits_uop_is_fencei = slow_wakeup_2_bits_uop_is_fencei; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_6_bits_uop_is_fencei = slow_wakeup_2_bits_uop_is_fencei; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_6_bits_uop_is_amo = slow_wakeup_2_bits_uop_is_amo; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_6_bits_uop_is_amo = slow_wakeup_2_bits_uop_is_amo; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_6_bits_uop_uses_ldq = slow_wakeup_2_bits_uop_uses_ldq; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_6_bits_uop_uses_ldq = slow_wakeup_2_bits_uop_uses_ldq; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_6_bits_uop_uses_stq = slow_wakeup_2_bits_uop_uses_stq; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_6_bits_uop_uses_stq = slow_wakeup_2_bits_uop_uses_stq; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_6_bits_uop_is_sys_pc2epc = slow_wakeup_2_bits_uop_is_sys_pc2epc; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_6_bits_uop_is_sys_pc2epc = slow_wakeup_2_bits_uop_is_sys_pc2epc; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_6_bits_uop_is_unique = slow_wakeup_2_bits_uop_is_unique; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_6_bits_uop_is_unique = slow_wakeup_2_bits_uop_is_unique; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_6_bits_uop_flush_on_commit = slow_wakeup_2_bits_uop_flush_on_commit; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_6_bits_uop_flush_on_commit = slow_wakeup_2_bits_uop_flush_on_commit; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_6_bits_uop_ldst_is_rs1 = slow_wakeup_2_bits_uop_ldst_is_rs1; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_6_bits_uop_ldst_is_rs1 = slow_wakeup_2_bits_uop_ldst_is_rs1; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_6_bits_uop_ldst = slow_wakeup_2_bits_uop_ldst; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_6_bits_uop_ldst = slow_wakeup_2_bits_uop_ldst; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_6_bits_uop_lrs1 = slow_wakeup_2_bits_uop_lrs1; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_6_bits_uop_lrs1 = slow_wakeup_2_bits_uop_lrs1; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_6_bits_uop_lrs2 = slow_wakeup_2_bits_uop_lrs2; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_6_bits_uop_lrs2 = slow_wakeup_2_bits_uop_lrs2; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_6_bits_uop_lrs3 = slow_wakeup_2_bits_uop_lrs3; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_6_bits_uop_lrs3 = slow_wakeup_2_bits_uop_lrs3; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_6_bits_uop_ldst_val = slow_wakeup_2_bits_uop_ldst_val; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_6_bits_uop_ldst_val = slow_wakeup_2_bits_uop_ldst_val; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_6_bits_uop_dst_rtype = slow_wakeup_2_bits_uop_dst_rtype; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_6_bits_uop_dst_rtype = slow_wakeup_2_bits_uop_dst_rtype; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_6_bits_uop_lrs1_rtype = slow_wakeup_2_bits_uop_lrs1_rtype; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_6_bits_uop_lrs1_rtype = slow_wakeup_2_bits_uop_lrs1_rtype; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_6_bits_uop_lrs2_rtype = slow_wakeup_2_bits_uop_lrs2_rtype; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_6_bits_uop_lrs2_rtype = slow_wakeup_2_bits_uop_lrs2_rtype; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_6_bits_uop_frs3_en = slow_wakeup_2_bits_uop_frs3_en; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_6_bits_uop_frs3_en = slow_wakeup_2_bits_uop_frs3_en; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_6_bits_uop_fp_val = slow_wakeup_2_bits_uop_fp_val; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_6_bits_uop_fp_val = slow_wakeup_2_bits_uop_fp_val; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_6_bits_uop_fp_single = slow_wakeup_2_bits_uop_fp_single; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_6_bits_uop_fp_single = slow_wakeup_2_bits_uop_fp_single; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_6_bits_uop_xcpt_pf_if = slow_wakeup_2_bits_uop_xcpt_pf_if; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_6_bits_uop_xcpt_pf_if = slow_wakeup_2_bits_uop_xcpt_pf_if; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_6_bits_uop_xcpt_ae_if = slow_wakeup_2_bits_uop_xcpt_ae_if; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_6_bits_uop_xcpt_ae_if = slow_wakeup_2_bits_uop_xcpt_ae_if; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_6_bits_uop_xcpt_ma_if = slow_wakeup_2_bits_uop_xcpt_ma_if; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_6_bits_uop_xcpt_ma_if = slow_wakeup_2_bits_uop_xcpt_ma_if; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_6_bits_uop_bp_debug_if = slow_wakeup_2_bits_uop_bp_debug_if; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_6_bits_uop_bp_debug_if = slow_wakeup_2_bits_uop_bp_debug_if; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_6_bits_uop_bp_xcpt_if = slow_wakeup_2_bits_uop_bp_xcpt_if; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_6_bits_uop_bp_xcpt_if = slow_wakeup_2_bits_uop_bp_xcpt_if; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_6_bits_uop_debug_fsrc = slow_wakeup_2_bits_uop_debug_fsrc; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_6_bits_uop_debug_fsrc = slow_wakeup_2_bits_uop_debug_fsrc; // @[core.scala:148:30, :815:29]
assign int_iss_wakeups_6_bits_uop_debug_tsrc = slow_wakeup_2_bits_uop_debug_tsrc; // @[core.scala:147:30, :815:29]
assign int_ren_wakeups_6_bits_uop_debug_tsrc = slow_wakeup_2_bits_uop_debug_tsrc; // @[core.scala:148:30, :815:29]
wire _T_149 = _alu_exe_unit_2_io_iresp_bits_uop_dst_rtype != 2'h2; // @[execution-units.scala:119:32]
wire _slow_wakeup_valid_T_12; // @[micro-op.scala:149:36]
assign _slow_wakeup_valid_T_12 = _T_149; // @[micro-op.scala:149:36]
wire _iregfile_io_write_ports_3_valid_T; // @[micro-op.scala:149:36]
assign _iregfile_io_write_ports_3_valid_T = _T_149; // @[micro-op.scala:149:36]
wire _rob_io_debug_wb_valids_3_T; // @[micro-op.scala:149:36]
assign _rob_io_debug_wb_valids_3_T = _T_149; // @[micro-op.scala:149:36]
wire _fast_wakeup_valid_T_16 = iss_valids_3 & iss_uops_3_bypassable; // @[core.scala:172:24, :173:24, :824:45]
wire _fast_wakeup_valid_T_17 = iss_uops_3_dst_rtype == 2'h0; // @[core.scala:173:24, :826:53]
wire _fast_wakeup_valid_T_18 = _fast_wakeup_valid_T_16 & _fast_wakeup_valid_T_17; // @[core.scala:824:45, :825:54, :826:53]
wire _fast_wakeup_valid_T_19 = _fast_wakeup_valid_T_18 & iss_uops_3_ldst_val; // @[core.scala:173:24, :825:54, :826:64]
wire _GEN_41 = iss_uops_3_iw_p1_poisoned | iss_uops_3_iw_p2_poisoned; // @[core.scala:173:24, :828:79]
wire _fast_wakeup_valid_T_20; // @[core.scala:828:79]
assign _fast_wakeup_valid_T_20 = _GEN_41; // @[core.scala:828:79]
wire _iregister_read_io_iss_valids_3_T; // @[core.scala:981:72]
assign _iregister_read_io_iss_valids_3_T = _GEN_41; // @[core.scala:828:79, :981:72]
wire _fast_wakeup_valid_T_21 = io_lsu_ld_miss_0 & _fast_wakeup_valid_T_20; // @[core.scala:51:7, :828:{48,79}]
wire _fast_wakeup_valid_T_22 = ~_fast_wakeup_valid_T_21; // @[core.scala:828:{31,48}]
assign _fast_wakeup_valid_T_23 = _fast_wakeup_valid_T_19 & _fast_wakeup_valid_T_22; // @[core.scala:826:64, :827:52, :828:31]
assign fast_wakeup_2_valid = _fast_wakeup_valid_T_23; // @[core.scala:814:29, :827:52]
wire _slow_wakeup_valid_T_13 = _alu_exe_unit_2_io_iresp_valid & _slow_wakeup_valid_T_12; // @[execution-units.scala:119:32]
wire _slow_wakeup_valid_T_14 = ~_alu_exe_unit_2_io_iresp_bits_uop_bypassable; // @[execution-units.scala:119:32]
wire _slow_wakeup_valid_T_15 = _slow_wakeup_valid_T_13 & _slow_wakeup_valid_T_14; // @[core.scala:832:42, :833:54, :834:33]
wire _T_143 = _alu_exe_unit_2_io_iresp_bits_uop_dst_rtype == 2'h0; // @[execution-units.scala:119:32]
wire _slow_wakeup_valid_T_16; // @[core.scala:835:57]
assign _slow_wakeup_valid_T_16 = _T_143; // @[core.scala:835:57]
wire _iregfile_io_write_ports_3_valid_T_2; // @[core.scala:1160:77]
assign _iregfile_io_write_ports_3_valid_T_2 = _T_143; // @[core.scala:835:57, :1160:77]
wire _rob_io_debug_wb_valids_3_T_2; // @[core.scala:1240:86]
assign _rob_io_debug_wb_valids_3_T_2 = _T_143; // @[core.scala:835:57, :1240:86]
assign _slow_wakeup_valid_T_17 = _slow_wakeup_valid_T_15 & _slow_wakeup_valid_T_16; // @[core.scala:833:54, :834:59, :835:57]
assign slow_wakeup_2_valid = _slow_wakeup_valid_T_17; // @[core.scala:815:29, :834:59]
wire _pred_wakeup_valid_T = iss_uops_1_is_br & iss_uops_1_is_sfb; // @[core.scala:173:24]
wire _pred_wakeup_valid_T_4 = io_lsu_ld_miss_0 & _pred_wakeup_valid_T_3; // @[core.scala:51:7, :864:{42,84}]
wire _pred_wakeup_valid_T_5 = ~_pred_wakeup_valid_T_4; // @[core.scala:864:{25,42}]
wire loads_saturating = _mem_issue_unit_io_iss_valids_0 & _mem_issue_unit_io_iss_uops_0_uses_ldq; // @[core.scala:108:32, :908:57]
reg [4:0] saturating_loads_counter; // @[core.scala:909:41]
wire [5:0] _saturating_loads_counter_T = {1'h0, saturating_loads_counter} + 6'h1; // @[core.scala:909:41, :910:82]
wire [4:0] _saturating_loads_counter_T_1 = _saturating_loads_counter_T[4:0]; // @[core.scala:910:82]
reg pause_mem_REG; // @[core.scala:912:26]
wire _pause_mem_T_1 = &saturating_loads_counter; // @[core.scala:909:41, :912:73]
wire pause_mem = pause_mem_REG & _pause_mem_T_1; // @[core.scala:912:{26,45,73}]
wire [9:0] _mem_issue_unit_io_fu_types_0_T = {7'h0, ~pause_mem, 2'h0}; // @[core.scala:912:45, :931:53]
wire [9:0] _idiv_issued_T = iss_uops_1_fu_code & 10'h10; // @[core.scala:173:24]
wire _idiv_issued_T_1 = |_idiv_issued_T; // @[micro-op.scala:154:{40,47}]
wire idiv_issued = iss_valids_1 & _idiv_issued_T_1; // @[core.scala:172:24, :924:47]
reg [9:0] REG_4; // @[core.scala:925:38]
wire [9:0] _idiv_issued_T_2 = iss_uops_3_fu_code & 10'h10; // @[core.scala:173:24]
wire _idiv_issued_T_3 = |_idiv_issued_T_2; // @[micro-op.scala:154:{40,47}]
wire idiv_issued_1 = iss_valids_3 & _idiv_issued_T_3; // @[core.scala:172:24, :924:47]
reg [9:0] REG_5; // @[core.scala:925:38]
reg mem_issue_unit_io_flush_pipeline_REG; // @[core.scala:946:49]
reg int_issue_unit_io_flush_pipeline_REG; // @[core.scala:946:49]
reg memExeUnit_io_com_exception_REG; // @[core.scala:952:51]
wire _GEN_42 = int_iss_wakeups_0_bits_uop_iw_p1_poisoned | int_iss_wakeups_0_bits_uop_iw_p2_poisoned; // @[core.scala:147:30, :961:61]
wire _mem_issue_unit_io_wakeup_ports_0_bits_poisoned_T; // @[core.scala:961:61]
assign _mem_issue_unit_io_wakeup_ports_0_bits_poisoned_T = _GEN_42; // @[core.scala:961:61]
wire _int_issue_unit_io_wakeup_ports_0_bits_poisoned_T; // @[core.scala:961:61]
assign _int_issue_unit_io_wakeup_ports_0_bits_poisoned_T = _GEN_42; // @[core.scala:961:61]
wire _GEN_43 = int_iss_wakeups_1_bits_uop_iw_p1_poisoned | int_iss_wakeups_1_bits_uop_iw_p2_poisoned; // @[core.scala:147:30, :961:61]
wire _mem_issue_unit_io_wakeup_ports_1_bits_poisoned_T; // @[core.scala:961:61]
assign _mem_issue_unit_io_wakeup_ports_1_bits_poisoned_T = _GEN_43; // @[core.scala:961:61]
wire _int_issue_unit_io_wakeup_ports_1_bits_poisoned_T; // @[core.scala:961:61]
assign _int_issue_unit_io_wakeup_ports_1_bits_poisoned_T = _GEN_43; // @[core.scala:961:61]
wire _GEN_44 = int_iss_wakeups_2_bits_uop_iw_p1_poisoned | int_iss_wakeups_2_bits_uop_iw_p2_poisoned; // @[core.scala:147:30, :961:61]
wire _mem_issue_unit_io_wakeup_ports_2_bits_poisoned_T; // @[core.scala:961:61]
assign _mem_issue_unit_io_wakeup_ports_2_bits_poisoned_T = _GEN_44; // @[core.scala:961:61]
wire _int_issue_unit_io_wakeup_ports_2_bits_poisoned_T; // @[core.scala:961:61]
assign _int_issue_unit_io_wakeup_ports_2_bits_poisoned_T = _GEN_44; // @[core.scala:961:61]
wire _GEN_45 = int_iss_wakeups_3_bits_uop_iw_p1_poisoned | int_iss_wakeups_3_bits_uop_iw_p2_poisoned; // @[core.scala:147:30, :961:61]
wire _mem_issue_unit_io_wakeup_ports_3_bits_poisoned_T; // @[core.scala:961:61]
assign _mem_issue_unit_io_wakeup_ports_3_bits_poisoned_T = _GEN_45; // @[core.scala:961:61]
wire _int_issue_unit_io_wakeup_ports_3_bits_poisoned_T; // @[core.scala:961:61]
assign _int_issue_unit_io_wakeup_ports_3_bits_poisoned_T = _GEN_45; // @[core.scala:961:61]
wire _GEN_46 = int_iss_wakeups_4_bits_uop_iw_p1_poisoned | int_iss_wakeups_4_bits_uop_iw_p2_poisoned; // @[core.scala:147:30, :961:61]
wire _mem_issue_unit_io_wakeup_ports_4_bits_poisoned_T; // @[core.scala:961:61]
assign _mem_issue_unit_io_wakeup_ports_4_bits_poisoned_T = _GEN_46; // @[core.scala:961:61]
wire _int_issue_unit_io_wakeup_ports_4_bits_poisoned_T; // @[core.scala:961:61]
assign _int_issue_unit_io_wakeup_ports_4_bits_poisoned_T = _GEN_46; // @[core.scala:961:61]
wire _GEN_47 = int_iss_wakeups_5_bits_uop_iw_p1_poisoned | int_iss_wakeups_5_bits_uop_iw_p2_poisoned; // @[core.scala:147:30, :961:61]
wire _mem_issue_unit_io_wakeup_ports_5_bits_poisoned_T; // @[core.scala:961:61]
assign _mem_issue_unit_io_wakeup_ports_5_bits_poisoned_T = _GEN_47; // @[core.scala:961:61]
wire _int_issue_unit_io_wakeup_ports_5_bits_poisoned_T; // @[core.scala:961:61]
assign _int_issue_unit_io_wakeup_ports_5_bits_poisoned_T = _GEN_47; // @[core.scala:961:61]
wire _GEN_48 = int_iss_wakeups_6_bits_uop_iw_p1_poisoned | int_iss_wakeups_6_bits_uop_iw_p2_poisoned; // @[core.scala:147:30, :961:61]
wire _mem_issue_unit_io_wakeup_ports_6_bits_poisoned_T; // @[core.scala:961:61]
assign _mem_issue_unit_io_wakeup_ports_6_bits_poisoned_T = _GEN_48; // @[core.scala:961:61]
wire _int_issue_unit_io_wakeup_ports_6_bits_poisoned_T; // @[core.scala:961:61]
assign _int_issue_unit_io_wakeup_ports_6_bits_poisoned_T = _GEN_48; // @[core.scala:961:61]
wire _iregister_read_io_iss_valids_0_T = iss_uops_0_iw_p1_poisoned | iss_uops_0_iw_p2_poisoned; // @[core.scala:173:24, :981:72]
wire _iregister_read_io_iss_valids_0_T_1 = io_lsu_ld_miss_0 & _iregister_read_io_iss_valids_0_T; // @[core.scala:51:7, :981:{41,72}]
wire _iregister_read_io_iss_valids_0_T_2 = ~_iregister_read_io_iss_valids_0_T_1; // @[core.scala:981:{24,41}]
wire _iregister_read_io_iss_valids_0_T_3 = iss_valids_0 & _iregister_read_io_iss_valids_0_T_2; // @[core.scala:172:24, :981:{21,24}]
wire _iregister_read_io_iss_valids_1_T_1 = io_lsu_ld_miss_0 & _iregister_read_io_iss_valids_1_T; // @[core.scala:51:7, :981:{41,72}]
wire _iregister_read_io_iss_valids_1_T_2 = ~_iregister_read_io_iss_valids_1_T_1; // @[core.scala:981:{24,41}]
wire _iregister_read_io_iss_valids_1_T_3 = iss_valids_1 & _iregister_read_io_iss_valids_1_T_2; // @[core.scala:172:24, :981:{21,24}]
wire _iregister_read_io_iss_valids_2_T_1 = io_lsu_ld_miss_0 & _iregister_read_io_iss_valids_2_T; // @[core.scala:51:7, :981:{41,72}]
wire _iregister_read_io_iss_valids_2_T_2 = ~_iregister_read_io_iss_valids_2_T_1; // @[core.scala:981:{24,41}]
wire _iregister_read_io_iss_valids_2_T_3 = iss_valids_2 & _iregister_read_io_iss_valids_2_T_2; // @[core.scala:172:24, :981:{21,24}]
wire _iregister_read_io_iss_valids_3_T_1 = io_lsu_ld_miss_0 & _iregister_read_io_iss_valids_3_T; // @[core.scala:51:7, :981:{41,72}]
wire _iregister_read_io_iss_valids_3_T_2 = ~_iregister_read_io_iss_valids_3_T_1; // @[core.scala:981:{24,41}]
wire _iregister_read_io_iss_valids_3_T_3 = iss_valids_3 & _iregister_read_io_iss_valids_3_T_2; // @[core.scala:172:24, :981:{21,24}]
reg iregister_read_io_kill_REG; // @[core.scala:987:38]
wire [2:0] _csr_io_rw_cmd_T = {~_alu_exe_unit_1_io_iresp_valid, 2'h0}; // @[CSR.scala:183:15]
wire [2:0] _csr_io_rw_cmd_T_1 = ~_csr_io_rw_cmd_T; // @[CSR.scala:183:{11,15}]
wire [2:0] _csr_io_rw_cmd_T_2 = _alu_exe_unit_1_io_iresp_bits_uop_ctrl_csr_cmd & _csr_io_rw_cmd_T_1; // @[CSR.scala:183:{9,11}]
wire [2:0] _csr_io_retire_T = {csr_io_retire_hi, _rob_io_commit_arch_valids_0}; // @[core.scala:143:32, :1015:66]
wire _csr_io_retire_T_1 = _csr_io_retire_T[0]; // @[core.scala:1015:{39,66}]
wire _csr_io_retire_T_2 = _csr_io_retire_T[1]; // @[core.scala:1015:{39,66}]
wire _csr_io_retire_T_3 = _csr_io_retire_T[2]; // @[core.scala:1015:{39,66}]
wire [1:0] _csr_io_retire_T_4 = {1'h0, _csr_io_retire_T_2} + {1'h0, _csr_io_retire_T_3}; // @[core.scala:1015:39]
wire [1:0] _csr_io_retire_T_5 = _csr_io_retire_T_4; // @[core.scala:1015:39]
wire [2:0] _csr_io_retire_T_6 = {2'h0, _csr_io_retire_T_1} + {1'h0, _csr_io_retire_T_5}; // @[core.scala:1015:39]
wire [1:0] _csr_io_retire_T_7 = _csr_io_retire_T_6[1:0]; // @[core.scala:1015:39]
reg [1:0] csr_io_retire_REG; // @[core.scala:1015:30]
reg csr_io_exception_REG; // @[core.scala:1016:30]
wire [39:0] _csr_io_pc_T = ~io_ifu_get_pc_0_com_pc_0; // @[util.scala:237:7]
wire [39:0] _csr_io_pc_T_1 = {_csr_io_pc_T[39:6], 6'h3F}; // @[util.scala:237:{7,11}]
wire [39:0] _csr_io_pc_T_2 = ~_csr_io_pc_T_1; // @[util.scala:237:{5,11}]
reg [5:0] csr_io_pc_REG; // @[core.scala:1020:31]
wire [40:0] _csr_io_pc_T_3 = {1'h0, _csr_io_pc_T_2} + {35'h0, csr_io_pc_REG}; // @[util.scala:237:5]
wire [39:0] _csr_io_pc_T_4 = _csr_io_pc_T_3[39:0]; // @[core.scala:1020:22]
reg csr_io_pc_REG_1; // @[core.scala:1021:35]
wire [1:0] _csr_io_pc_T_5 = {csr_io_pc_REG_1, 1'h0}; // @[core.scala:1021:{27,35}]
wire [40:0] _csr_io_pc_T_6 = {1'h0, _csr_io_pc_T_4} - {39'h0, _csr_io_pc_T_5}; // @[core.scala:1020:22, :1021:{22,27}]
wire [39:0] _csr_io_pc_T_7 = _csr_io_pc_T_6[39:0]; // @[core.scala:1021:22]
reg [63:0] csr_io_cause_REG; // @[core.scala:1023:30]
wire _tval_valid_T = csr_io_cause_REG == 64'h3; // @[package.scala:16:47]
wire _tval_valid_T_1 = csr_io_cause_REG == 64'h4; // @[package.scala:16:47]
wire _tval_valid_T_2 = csr_io_cause_REG == 64'h6; // @[package.scala:16:47]
wire _tval_valid_T_3 = csr_io_cause_REG == 64'h5; // @[package.scala:16:47]
wire _tval_valid_T_4 = csr_io_cause_REG == 64'h7; // @[package.scala:16:47]
wire _tval_valid_T_5 = csr_io_cause_REG == 64'h1; // @[package.scala:16:47]
wire _tval_valid_T_6 = csr_io_cause_REG == 64'hD; // @[package.scala:16:47]
wire _tval_valid_T_7 = csr_io_cause_REG == 64'hF; // @[package.scala:16:47]
wire _tval_valid_T_8 = csr_io_cause_REG == 64'hC; // @[package.scala:16:47]
wire _tval_valid_T_9 = _tval_valid_T | _tval_valid_T_1; // @[package.scala:16:47, :81:59]
wire _tval_valid_T_10 = _tval_valid_T_9 | _tval_valid_T_2; // @[package.scala:16:47, :81:59]
wire _tval_valid_T_11 = _tval_valid_T_10 | _tval_valid_T_3; // @[package.scala:16:47, :81:59]
wire _tval_valid_T_12 = _tval_valid_T_11 | _tval_valid_T_4; // @[package.scala:16:47, :81:59]
wire _tval_valid_T_13 = _tval_valid_T_12 | _tval_valid_T_5; // @[package.scala:16:47, :81:59]
wire _tval_valid_T_14 = _tval_valid_T_13 | _tval_valid_T_6; // @[package.scala:16:47, :81:59]
wire _tval_valid_T_15 = _tval_valid_T_14 | _tval_valid_T_7; // @[package.scala:16:47, :81:59]
wire _tval_valid_T_16 = _tval_valid_T_15 | _tval_valid_T_8; // @[package.scala:16:47, :81:59]
wire tval_valid = csr_io_exception_REG & _tval_valid_T_16; // @[package.scala:81:59]
wire [63:0] _csr_io_tval_a_T; // @[core.scala:1049:18]
wire [24:0] csr_io_tval_a = _csr_io_tval_a_T[63:39]; // @[core.scala:1049:{18,25}]
wire _csr_io_tval_msb_T = csr_io_tval_a == 25'h0; // @[core.scala:1049:25, :1050:23]
wire _csr_io_tval_msb_T_1 = &csr_io_tval_a; // @[core.scala:1049:25, :1050:36]
wire _csr_io_tval_msb_T_2 = _csr_io_tval_msb_T | _csr_io_tval_msb_T_1; // @[core.scala:1050:{23,31,36}]
wire _csr_io_tval_msb_T_3 = _rob_io_com_xcpt_bits_badvaddr[39]; // @[core.scala:143:32, :1050:48]
wire _csr_io_tval_msb_T_4 = _rob_io_com_xcpt_bits_badvaddr[38]; // @[core.scala:143:32, :1050:64]
wire _csr_io_tval_msb_T_5 = ~_csr_io_tval_msb_T_4; // @[core.scala:1050:{61,64}]
wire csr_io_tval_msb = _csr_io_tval_msb_T_2 ? _csr_io_tval_msb_T_3 : _csr_io_tval_msb_T_5; // @[core.scala:1050:{20,31,48,61}]
wire [38:0] _csr_io_tval_T = _rob_io_com_xcpt_bits_badvaddr[38:0]; // @[core.scala:143:32, :1051:18]
wire [39:0] _csr_io_tval_T_1 = {csr_io_tval_msb, _csr_io_tval_T}; // @[core.scala:1050:20, :1051:{10,18}]
reg [39:0] csr_io_tval_REG; // @[core.scala:1040:12]
wire [39:0] _csr_io_tval_T_2 = tval_valid ? csr_io_tval_REG : 40'h0; // @[core.scala:1026:37, :1039:21, :1040:12]
assign bypasses_0_bits_data = _alu_exe_unit_io_bypass_0_bits_data[63:0]; // @[execution-units.scala:119:32]
assign bypasses_1_bits_data = _alu_exe_unit_1_io_bypass_0_bits_data[63:0]; // @[execution-units.scala:119:32]
assign bypasses_2_bits_data = _alu_exe_unit_2_io_bypass_0_bits_data[63:0]; // @[execution-units.scala:119:32]
assign bypasses_3_bits_data = _alu_exe_unit_2_io_bypass_1_bits_data[63:0]; // @[execution-units.scala:119:32]
assign bypasses_4_bits_data = _alu_exe_unit_2_io_bypass_2_bits_data[63:0]; // @[execution-units.scala:119:32]
assign pred_bypasses_0_bits_data = _alu_exe_unit_io_bypass_0_bits_data[0]; // @[execution-units.scala:119:32]
reg io_lsu_exception_REG; // @[core.scala:1124:30]
assign io_lsu_exception_0 = io_lsu_exception_REG; // @[core.scala:51:7, :1124:30]
wire _iregfile_io_write_ports_0_wport_valid_T_1; // @[regfile.scala:57:35]
wire [6:0] iregfile_io_write_ports_0_wport_bits_addr; // @[regfile.scala:55:22]
wire [63:0] iregfile_io_write_ports_0_wport_bits_data; // @[regfile.scala:55:22]
wire iregfile_io_write_ports_0_wport_valid; // @[regfile.scala:55:22]
assign _iregfile_io_write_ports_0_wport_valid_T_1 = _ll_wbarb_io_out_valid & _iregfile_io_write_ports_0_wport_valid_T; // @[regfile.scala:57:{35,61}]
assign iregfile_io_write_ports_0_wport_valid = _iregfile_io_write_ports_0_wport_valid_T_1; // @[regfile.scala:55:22, :57:35]
wire wbReadsCSR = |_alu_exe_unit_io_iresp_bits_uop_ctrl_csr_cmd; // @[execution-units.scala:119:32]
wire _iregfile_io_write_ports_1_valid_T_1 = _alu_exe_unit_io_iresp_valid & _iregfile_io_write_ports_1_valid_T; // @[execution-units.scala:119:32]
wire _iregfile_io_write_ports_1_valid_T_3 = _iregfile_io_write_ports_1_valid_T_1 & _iregfile_io_write_ports_1_valid_T_2; // @[core.scala:1160:{22,48,77}]
wire wbReadsCSR_1 = |_alu_exe_unit_1_io_iresp_bits_uop_ctrl_csr_cmd; // @[execution-units.scala:119:32]
wire _iregfile_io_write_ports_2_valid_T_1 = _alu_exe_unit_1_io_iresp_valid & _iregfile_io_write_ports_2_valid_T; // @[execution-units.scala:119:32]
wire _iregfile_io_write_ports_2_valid_T_3 = _iregfile_io_write_ports_2_valid_T_1 & _iregfile_io_write_ports_2_valid_T_2; // @[core.scala:1160:{22,48,77}]
wire [64:0] _GEN_49 = {1'h0, _csr_io_rw_rdata}; // @[core.scala:271:19, :1167:56]
wire [64:0] _iregfile_io_write_ports_2_bits_data_T = wbReadsCSR_1 ? _GEN_49 : _alu_exe_unit_1_io_iresp_bits_data; // @[execution-units.scala:119:32]
wire wbReadsCSR_2 = |_alu_exe_unit_2_io_iresp_bits_uop_ctrl_csr_cmd; // @[execution-units.scala:119:32]
wire _iregfile_io_write_ports_3_valid_T_1 = _alu_exe_unit_2_io_iresp_valid & _iregfile_io_write_ports_3_valid_T; // @[execution-units.scala:119:32]
wire _iregfile_io_write_ports_3_valid_T_3 = _iregfile_io_write_ports_3_valid_T_1 & _iregfile_io_write_ports_3_valid_T_2; // @[core.scala:1160:{22,48,77}]
wire _rob_io_wb_resps_0_valid_T = ~_ll_wbarb_io_out_bits_uop_is_amo; // @[core.scala:132:32, :1217:78]
wire _rob_io_wb_resps_0_valid_T_1 = _ll_wbarb_io_out_bits_uop_uses_stq & _rob_io_wb_resps_0_valid_T; // @[core.scala:132:32, :1217:{75,78}]
wire _rob_io_wb_resps_0_valid_T_2 = ~_rob_io_wb_resps_0_valid_T_1; // @[core.scala:1217:{57,75}]
wire _rob_io_wb_resps_0_valid_T_3 = _ll_wbarb_io_out_valid & _rob_io_wb_resps_0_valid_T_2; // @[core.scala:132:32, :1217:{54,57}]
wire _rob_io_debug_wb_valids_0_T = _ll_wbarb_io_out_bits_uop_dst_rtype != 2'h2; // @[core.scala:132:32, :1219:74]
wire _rob_io_debug_wb_valids_0_T_1 = _ll_wbarb_io_out_valid & _rob_io_debug_wb_valids_0_T; // @[core.scala:132:32, :1219:{54,74}]
wire _rob_io_wb_resps_1_valid_T = ~_alu_exe_unit_io_iresp_bits_uop_is_amo; // @[execution-units.scala:119:32]
wire _rob_io_wb_resps_1_valid_T_1 = _alu_exe_unit_io_iresp_bits_uop_uses_stq & _rob_io_wb_resps_1_valid_T; // @[execution-units.scala:119:32]
wire _rob_io_wb_resps_1_valid_T_2 = ~_rob_io_wb_resps_1_valid_T_1; // @[core.scala:1238:{51,69}]
wire _rob_io_wb_resps_1_valid_T_3 = _alu_exe_unit_io_iresp_valid & _rob_io_wb_resps_1_valid_T_2; // @[execution-units.scala:119:32]
wire _rob_io_debug_wb_valids_1_T_1 = _alu_exe_unit_io_iresp_valid & _rob_io_debug_wb_valids_1_T; // @[execution-units.scala:119:32]
wire _rob_io_debug_wb_valids_1_T_3 = _rob_io_debug_wb_valids_1_T_1 & _rob_io_debug_wb_valids_1_T_2; // @[core.scala:1240:{49,66,86}]
wire _rob_io_wb_resps_2_valid_T = ~_alu_exe_unit_1_io_iresp_bits_uop_is_amo; // @[execution-units.scala:119:32]
wire _rob_io_wb_resps_2_valid_T_1 = _alu_exe_unit_1_io_iresp_bits_uop_uses_stq & _rob_io_wb_resps_2_valid_T; // @[execution-units.scala:119:32]
wire _rob_io_wb_resps_2_valid_T_2 = ~_rob_io_wb_resps_2_valid_T_1; // @[core.scala:1238:{51,69}]
wire _rob_io_wb_resps_2_valid_T_3 = _alu_exe_unit_1_io_iresp_valid & _rob_io_wb_resps_2_valid_T_2; // @[execution-units.scala:119:32]
wire _rob_io_debug_wb_valids_2_T_1 = _alu_exe_unit_1_io_iresp_valid & _rob_io_debug_wb_valids_2_T; // @[execution-units.scala:119:32]
wire _rob_io_debug_wb_valids_2_T_3 = _rob_io_debug_wb_valids_2_T_1 & _rob_io_debug_wb_valids_2_T_2; // @[core.scala:1240:{49,66,86}]
wire _rob_io_debug_wb_wdata_2_T = |_alu_exe_unit_1_io_iresp_bits_uop_ctrl_csr_cmd; // @[execution-units.scala:119:32]
wire [64:0] _rob_io_debug_wb_wdata_2_T_1 = _rob_io_debug_wb_wdata_2_T ? _GEN_49 : _alu_exe_unit_1_io_iresp_bits_data; // @[execution-units.scala:119:32]
wire _rob_io_wb_resps_3_valid_T = ~_alu_exe_unit_2_io_iresp_bits_uop_is_amo; // @[execution-units.scala:119:32]
wire _rob_io_wb_resps_3_valid_T_1 = _alu_exe_unit_2_io_iresp_bits_uop_uses_stq & _rob_io_wb_resps_3_valid_T; // @[execution-units.scala:119:32]
wire _rob_io_wb_resps_3_valid_T_2 = ~_rob_io_wb_resps_3_valid_T_1; // @[core.scala:1238:{51,69}]
wire _rob_io_wb_resps_3_valid_T_3 = _alu_exe_unit_2_io_iresp_valid & _rob_io_wb_resps_3_valid_T_2; // @[execution-units.scala:119:32]
wire _rob_io_debug_wb_valids_3_T_1 = _alu_exe_unit_2_io_iresp_valid & _rob_io_debug_wb_valids_3_T; // @[execution-units.scala:119:32]
wire _rob_io_debug_wb_valids_3_T_3 = _rob_io_debug_wb_valids_3_T_1 & _rob_io_debug_wb_valids_3_T_2; // @[core.scala:1240:{49,66,86}]
reg REG_6; // @[core.scala:1306:45]
reg memExeUnit_io_req_bits_kill_REG; // @[core.scala:1310:45]
reg alu_exe_unit_io_req_bits_kill_REG; // @[core.scala:1310:45]
reg alu_exe_unit_io_req_bits_kill_REG_1; // @[core.scala:1310:45]
reg alu_exe_unit_io_req_bits_kill_REG_2; // @[core.scala:1310:45]
reg [4:0] small_0; // @[Counters.scala:45:41]
wire [5:0] nextSmall = {1'h0, small_0} + 6'h1; // @[Counters.scala:45:41, :46:33]
reg [26:0] large_0; // @[Counters.scala:50:31]
wire _large_T = nextSmall[5]; // @[Counters.scala:46:33, :51:20]
wire _large_T_2 = _large_T; // @[Counters.scala:51:{20,33}]
wire [27:0] _large_r_T = {1'h0, large_0} + 28'h1; // @[Counters.scala:50:31, :51:55]
wire [26:0] _large_r_T_1 = _large_r_T[26:0]; // @[Counters.scala:51:55]
wire [31:0] value = {large_0, small_0}; // @[Counters.scala:45:41, :50:31, :55:30]
wire [1:0] hi = {_rob_io_commit_valids_2, _rob_io_commit_valids_1}; // @[core.scala:143:32, :1324:30] |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Bundles.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import freechips.rocketchip.util._
import scala.collection.immutable.ListMap
import chisel3.util.Decoupled
import chisel3.util.DecoupledIO
import chisel3.reflect.DataMirror
abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle
// common combos in lazy policy:
// Put + Acquire
// Release + AccessAck
object TLMessages
{
// A B C D E
def PutFullData = 0.U // . . => AccessAck
def PutPartialData = 1.U // . . => AccessAck
def ArithmeticData = 2.U // . . => AccessAckData
def LogicalData = 3.U // . . => AccessAckData
def Get = 4.U // . . => AccessAckData
def Hint = 5.U // . . => HintAck
def AcquireBlock = 6.U // . => Grant[Data]
def AcquirePerm = 7.U // . => Grant[Data]
def Probe = 6.U // . => ProbeAck[Data]
def AccessAck = 0.U // . .
def AccessAckData = 1.U // . .
def HintAck = 2.U // . .
def ProbeAck = 4.U // .
def ProbeAckData = 5.U // .
def Release = 6.U // . => ReleaseAck
def ReleaseData = 7.U // . => ReleaseAck
def Grant = 4.U // . => GrantAck
def GrantData = 5.U // . => GrantAck
def ReleaseAck = 6.U // .
def GrantAck = 0.U // .
def isA(x: UInt) = x <= AcquirePerm
def isB(x: UInt) = x <= Probe
def isC(x: UInt) = x <= ReleaseData
def isD(x: UInt) = x <= ReleaseAck
def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant)
def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck)
def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("AcquireBlock",TLPermissions.PermMsgGrow),
("AcquirePerm",TLPermissions.PermMsgGrow))
def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("Probe",TLPermissions.PermMsgCap))
def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("ProbeAck",TLPermissions.PermMsgReport),
("ProbeAckData",TLPermissions.PermMsgReport),
("Release",TLPermissions.PermMsgReport),
("ReleaseData",TLPermissions.PermMsgReport))
def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("Grant",TLPermissions.PermMsgCap),
("GrantData",TLPermissions.PermMsgCap),
("ReleaseAck",TLPermissions.PermMsgReserved))
}
/**
* The three primary TileLink permissions are:
* (T)runk: the agent is (or is on inwards path to) the global point of serialization.
* (B)ranch: the agent is on an outwards path to
* (N)one:
* These permissions are permuted by transfer operations in various ways.
* Operations can cap permissions, request for them to be grown or shrunk,
* or for a report on their current status.
*/
object TLPermissions
{
val aWidth = 2
val bdWidth = 2
val cWidth = 3
// Cap types (Grant = new permissions, Probe = permisions <= target)
def toT = 0.U(bdWidth.W)
def toB = 1.U(bdWidth.W)
def toN = 2.U(bdWidth.W)
def isCap(x: UInt) = x <= toN
// Grow types (Acquire = permissions >= target)
def NtoB = 0.U(aWidth.W)
def NtoT = 1.U(aWidth.W)
def BtoT = 2.U(aWidth.W)
def isGrow(x: UInt) = x <= BtoT
// Shrink types (ProbeAck, Release)
def TtoB = 0.U(cWidth.W)
def TtoN = 1.U(cWidth.W)
def BtoN = 2.U(cWidth.W)
def isShrink(x: UInt) = x <= BtoN
// Report types (ProbeAck, Release)
def TtoT = 3.U(cWidth.W)
def BtoB = 4.U(cWidth.W)
def NtoN = 5.U(cWidth.W)
def isReport(x: UInt) = x <= NtoN
def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT")
def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN")
def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN")
def PermMsgReserved:Seq[String] = Seq("Reserved")
}
object TLAtomics
{
val width = 3
// Arithmetic types
def MIN = 0.U(width.W)
def MAX = 1.U(width.W)
def MINU = 2.U(width.W)
def MAXU = 3.U(width.W)
def ADD = 4.U(width.W)
def isArithmetic(x: UInt) = x <= ADD
// Logical types
def XOR = 0.U(width.W)
def OR = 1.U(width.W)
def AND = 2.U(width.W)
def SWAP = 3.U(width.W)
def isLogical(x: UInt) = x <= SWAP
def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD")
def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP")
}
object TLHints
{
val width = 1
def PREFETCH_READ = 0.U(width.W)
def PREFETCH_WRITE = 1.U(width.W)
def isHints(x: UInt) = x <= PREFETCH_WRITE
def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite")
}
sealed trait TLChannel extends TLBundleBase {
val channelName: String
}
sealed trait TLDataChannel extends TLChannel
sealed trait TLAddrChannel extends TLDataChannel
final class TLBundleA(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleA_${params.shortName}"
val channelName = "'A' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleB(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleB_${params.shortName}"
val channelName = "'B' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val address = UInt(params.addressBits.W) // from
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleC(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleC_${params.shortName}"
val channelName = "'C' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.cWidth.W) // shrink or report perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleD(params: TLBundleParameters)
extends TLBundleBase(params) with TLDataChannel
{
override def typeName = s"TLBundleD_${params.shortName}"
val channelName = "'D' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val sink = UInt(params.sinkBits.W) // from
val denied = Bool() // implies corrupt iff *Data
val user = BundleMap(params.responseFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleE(params: TLBundleParameters)
extends TLBundleBase(params) with TLChannel
{
override def typeName = s"TLBundleE_${params.shortName}"
val channelName = "'E' channel"
val sink = UInt(params.sinkBits.W) // to
}
class TLBundle(val params: TLBundleParameters) extends Record
{
// Emulate a Bundle with elements abcde or ad depending on params.hasBCE
private val optA = Some (Decoupled(new TLBundleA(params)))
private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params))))
private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params)))
private val optD = Some (Flipped(Decoupled(new TLBundleD(params))))
private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params)))
def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params)))))
def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params)))))
def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params)))))
def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params)))))
def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params)))))
val elements =
if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a)
else ListMap("d" -> d, "a" -> a)
def tieoff(): Unit = {
DataMirror.specifiedDirectionOf(a.ready) match {
case SpecifiedDirection.Input =>
a.ready := false.B
c.ready := false.B
e.ready := false.B
b.valid := false.B
d.valid := false.B
case SpecifiedDirection.Output =>
a.valid := false.B
c.valid := false.B
e.valid := false.B
b.ready := false.B
d.ready := false.B
case _ =>
}
}
}
object TLBundle
{
def apply(params: TLBundleParameters) = new TLBundle(params)
}
class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle
class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params)
{
val a = new AsyncBundle(new TLBundleA(params.base), params.async)
val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async))
val c = new AsyncBundle(new TLBundleC(params.base), params.async)
val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async))
val e = new AsyncBundle(new TLBundleE(params.base), params.async)
}
class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = RationalIO(new TLBundleA(params))
val b = Flipped(RationalIO(new TLBundleB(params)))
val c = RationalIO(new TLBundleC(params))
val d = Flipped(RationalIO(new TLBundleD(params)))
val e = RationalIO(new TLBundleE(params))
}
class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = CreditedIO(new TLBundleA(params))
val b = Flipped(CreditedIO(new TLBundleB(params)))
val c = CreditedIO(new TLBundleC(params))
val d = Flipped(CreditedIO(new TLBundleD(params)))
val e = CreditedIO(new TLBundleE(params))
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor_27( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [8:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [8:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [8:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [20:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [8:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59]
wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27]
wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25]
wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_30 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_32 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_46 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_48 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_52 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_54 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_58 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_60 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_64 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_66 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_73 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_75 = 1'h1; // @[Parameters.scala:57:20]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28]
wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_first_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_first_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_first_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_first_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_set_wo_ready_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_set_wo_ready_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_opcodes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_opcodes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_sizes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_sizes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_opcodes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_opcodes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_sizes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_sizes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_probe_ack_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_probe_ack_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_probe_ack_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_probe_ack_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _same_cycle_resp_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _same_cycle_resp_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _same_cycle_resp_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _same_cycle_resp_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _same_cycle_resp_WIRE_4_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _same_cycle_resp_WIRE_5_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_first_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_first_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_first_WIRE_2_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_first_WIRE_3_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_set_wo_ready_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_set_wo_ready_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_set_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_set_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_opcodes_set_interm_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_opcodes_set_interm_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_sizes_set_interm_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_sizes_set_interm_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_opcodes_set_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_opcodes_set_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_sizes_set_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_sizes_set_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_probe_ack_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_probe_ack_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_probe_ack_WIRE_2_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_probe_ack_WIRE_3_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _same_cycle_resp_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _same_cycle_resp_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _same_cycle_resp_WIRE_2_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _same_cycle_resp_WIRE_3_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _same_cycle_resp_WIRE_4_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _same_cycle_resp_WIRE_5_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [4098:0] _c_opcodes_set_T_1 = 4099'h0; // @[Monitor.scala:767:54]
wire [4098:0] _c_sizes_set_T_1 = 4099'h0; // @[Monitor.scala:768:52]
wire [11:0] _c_opcodes_set_T = 12'h0; // @[Monitor.scala:767:79]
wire [11:0] _c_sizes_set_T = 12'h0; // @[Monitor.scala:768:77]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51]
wire [511:0] _c_set_wo_ready_T = 512'h1; // @[OneHot.scala:58:35]
wire [511:0] _c_set_T = 512'h1; // @[OneHot.scala:58:35]
wire [1027:0] c_opcodes_set = 1028'h0; // @[Monitor.scala:740:34]
wire [1027:0] c_sizes_set = 1028'h0; // @[Monitor.scala:741:34]
wire [256:0] c_set = 257'h0; // @[Monitor.scala:738:34]
wire [256:0] c_set_wo_ready = 257'h0; // @[Monitor.scala:739:34]
wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46]
wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76]
wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [8:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 9'h90; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [6:0] _source_ok_T_1 = io_in_a_bits_source_0[8:2]; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_T_7 = io_in_a_bits_source_0[8:2]; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_T_13 = io_in_a_bits_source_0[8:2]; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_T_19 = io_in_a_bits_source_0[8:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 7'h20; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 7'h21; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_14 = _source_ok_T_13 == 7'h22; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 7'h23; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire _source_ok_T_25 = io_in_a_bits_source_0 == 9'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31]
wire _source_ok_T_26 = io_in_a_bits_source_0 == 9'h41; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31]
wire _source_ok_T_27 = io_in_a_bits_source_0 == 9'h42; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_7 = _source_ok_T_27; // @[Parameters.scala:1138:31]
wire [5:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[5:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] _source_ok_T_28 = io_in_a_bits_source_0[8:6]; // @[Monitor.scala:36:7]
wire _source_ok_T_29 = _source_ok_T_28 == 3'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_31 = _source_ok_T_29; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_33 = _source_ok_T_31; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_8 = _source_ok_T_33; // @[Parameters.scala:1138:31]
wire _source_ok_T_34 = io_in_a_bits_source_0 == 9'h100; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_9 = _source_ok_T_34; // @[Parameters.scala:1138:31]
wire _source_ok_T_35 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_36 = _source_ok_T_35 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_37 = _source_ok_T_36 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_38 = _source_ok_T_37 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_39 = _source_ok_T_38 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_40 = _source_ok_T_39 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_41 = _source_ok_T_40 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_42 = _source_ok_T_41 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_42 | _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46]
wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [20:0] _is_aligned_T = {15'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 21'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_4 = _uncommonBits_T_4[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_9 = _uncommonBits_T_9[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_14 = _uncommonBits_T_14[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_19 = _uncommonBits_T_19[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_24 = _uncommonBits_T_24[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_29 = _uncommonBits_T_29[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_34 = _uncommonBits_T_34[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_39 = _uncommonBits_T_39[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_44 = _uncommonBits_T_44[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_46 = _uncommonBits_T_46[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_47 = _uncommonBits_T_47[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_49 = _uncommonBits_T_49[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_52 = _uncommonBits_T_52[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_53 = _uncommonBits_T_53[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_54 = _uncommonBits_T_54[5:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_43 = io_in_d_bits_source_0 == 9'h90; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_43; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire [6:0] _source_ok_T_44 = io_in_d_bits_source_0[8:2]; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_T_50 = io_in_d_bits_source_0[8:2]; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_T_56 = io_in_d_bits_source_0[8:2]; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_T_62 = io_in_d_bits_source_0[8:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_45 = _source_ok_T_44 == 7'h20; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_47 = _source_ok_T_45; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_49 = _source_ok_T_47; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_49; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_51 = _source_ok_T_50 == 7'h21; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_53 = _source_ok_T_51; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_55 = _source_ok_T_53; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_55; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_57 = _source_ok_T_56 == 7'h22; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_59 = _source_ok_T_57; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_61 = _source_ok_T_59; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_61; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_63 = _source_ok_T_62 == 7'h23; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_65 = _source_ok_T_63; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_67 = _source_ok_T_65; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_67; // @[Parameters.scala:1138:31]
wire _source_ok_T_68 = io_in_d_bits_source_0 == 9'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_5 = _source_ok_T_68; // @[Parameters.scala:1138:31]
wire _source_ok_T_69 = io_in_d_bits_source_0 == 9'h41; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_6 = _source_ok_T_69; // @[Parameters.scala:1138:31]
wire _source_ok_T_70 = io_in_d_bits_source_0 == 9'h42; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_7 = _source_ok_T_70; // @[Parameters.scala:1138:31]
wire [5:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[5:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] _source_ok_T_71 = io_in_d_bits_source_0[8:6]; // @[Monitor.scala:36:7]
wire _source_ok_T_72 = _source_ok_T_71 == 3'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_74 = _source_ok_T_72; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_76 = _source_ok_T_74; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_8 = _source_ok_T_76; // @[Parameters.scala:1138:31]
wire _source_ok_T_77 = io_in_d_bits_source_0 == 9'h100; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_9 = _source_ok_T_77; // @[Parameters.scala:1138:31]
wire _source_ok_T_78 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_79 = _source_ok_T_78 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_80 = _source_ok_T_79 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_81 = _source_ok_T_80 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_82 = _source_ok_T_81 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_83 = _source_ok_T_82 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_84 = _source_ok_T_83 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_85 = _source_ok_T_84 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_85 | _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46]
wire _T_1187 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1187; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1187; // @[Decoupled.scala:51:35]
wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [8:0] source; // @[Monitor.scala:390:22]
reg [20:0] address; // @[Monitor.scala:391:22]
wire _T_1260 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1260; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1260; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1260; // @[Decoupled.scala:51:35]
wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [8:0] source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [256:0] inflight; // @[Monitor.scala:614:27]
reg [1027:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [1027:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [256:0] a_set; // @[Monitor.scala:626:34]
wire [256:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [1027:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [1027:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [11:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [11:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [11:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [11:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [11:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [11:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [11:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [11:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [11:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [1027:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [1027:0] _a_opcode_lookup_T_6 = {1024'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [1027:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[1027:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [1027:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [1027:0] _a_size_lookup_T_6 = {1024'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [1027:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[1027:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [511:0] _GEN_2 = 512'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [511:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [511:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[256:0] : 257'h0; // @[OneHot.scala:58:35]
wire _T_1113 = _T_1187 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1113 ? _a_set_T[256:0] : 257'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1113 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1113 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [11:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [11:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [11:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [4098:0] _a_opcodes_set_T_1 = {4095'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1113 ? _a_opcodes_set_T_1[1027:0] : 1028'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [4098:0] _a_sizes_set_T_1 = {4095'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1113 ? _a_sizes_set_T_1[1027:0] : 1028'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [256:0] d_clr; // @[Monitor.scala:664:34]
wire [256:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [1027:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [1027:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_1159 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [511:0] _GEN_5 = 512'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [511:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [511:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [511:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [511:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1159 & ~d_release_ack ? _d_clr_wo_ready_T[256:0] : 257'h0; // @[OneHot.scala:58:35]
wire _T_1128 = _T_1260 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1128 ? _d_clr_T[256:0] : 257'h0; // @[OneHot.scala:58:35]
wire [4110:0] _d_opcodes_clr_T_5 = 4111'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1128 ? _d_opcodes_clr_T_5[1027:0] : 1028'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [4110:0] _d_sizes_clr_T_5 = 4111'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1128 ? _d_sizes_clr_T_5[1027:0] : 1028'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [256:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [256:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [256:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [1027:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [1027:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [1027:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [1027:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [1027:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [1027:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [256:0] inflight_1; // @[Monitor.scala:726:35]
wire [256:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [1027:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [1027:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [1027:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [1027:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [1027:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [1027:0] _c_opcode_lookup_T_6 = {1024'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [1027:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[1027:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [1027:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [1027:0] _c_size_lookup_T_6 = {1024'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [1027:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[1027:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [256:0] d_clr_1; // @[Monitor.scala:774:34]
wire [256:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [1027:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [1027:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1231 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1231 & d_release_ack_1 ? _d_clr_wo_ready_T_1[256:0] : 257'h0; // @[OneHot.scala:58:35]
wire _T_1213 = _T_1260 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1213 ? _d_clr_T_1[256:0] : 257'h0; // @[OneHot.scala:58:35]
wire [4110:0] _d_opcodes_clr_T_11 = 4111'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1213 ? _d_opcodes_clr_T_11[1027:0] : 1028'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [4110:0] _d_sizes_clr_T_11 = 4111'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1213 ? _d_sizes_clr_T_11[1027:0] : 1028'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 9'h0; // @[Monitor.scala:36:7, :795:113]
wire [256:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [256:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [1027:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [1027:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [1027:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [1027:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
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